History

phy: qcom-qmp-combo: rename DP_PHY register pointer

The DP_PHY registers have erroneously been referred to as "PCS" registers since DisplayPort support was added to the QMP drivers (including in the devicetree binding). Rename the corresponding pointer to match the register names. Note that the repeated "dp" in the field name is intentional and this DP register block is called "DP_PHY" (not just "PHY").

Johan Hovold committed 3 years ago

Commit 133836a1 parent 9e5b59e1 file · +70 −69Browse files

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drivers/phy/qualcomm/phy-qcom-qmp-combo.c+70−69
@@ -878,7 +878,7 @@ struct qmp_combo { · 877 unmodified lines
878878 void __iomem *dp_serdes;
879879 void __iomem *dp_tx;
880880 void __iomem *dp_tx2;
881− void __iomem *dp_pcs;
881+ void __iomem *dp_dp_phy;
882882
883883 struct clk *pipe_clk;
884884 struct clk_bulk_data *clks;
@@ -1252,20 +1252,20 @@ static void qmp_v3_dp_aux_init(struct qmp_combo *qmp) · 367 unmodified lines
12521252 {
12531253 writel(DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN |
12541254 DP_PHY_PD_CTL_PLL_PWRDN | DP_PHY_PD_CTL_DP_CLAMP_EN,
1255− qmp->dp_pcs + QSERDES_DP_PHY_PD_CTL);
1255+ qmp->dp_dp_phy + QSERDES_DP_PHY_PD_CTL);
12561256
12571257 /* Turn on BIAS current for PHY/PLL */
12581258 writel(QSERDES_V3_COM_BIAS_EN | QSERDES_V3_COM_BIAS_EN_MUX |
12591259 QSERDES_V3_COM_CLKBUF_L_EN | QSERDES_V3_COM_EN_SYSCLK_TX_SEL,
12601260 qmp->dp_serdes + QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN);
12611261
1262− writel(DP_PHY_PD_CTL_PSR_PWRDN, qmp->dp_pcs + QSERDES_DP_PHY_PD_CTL);
1262+ writel(DP_PHY_PD_CTL_PSR_PWRDN, qmp->dp_dp_phy + QSERDES_DP_PHY_PD_CTL);
12631263
12641264 writel(DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN |
12651265 DP_PHY_PD_CTL_LANE_0_1_PWRDN |
12661266 DP_PHY_PD_CTL_LANE_2_3_PWRDN | DP_PHY_PD_CTL_PLL_PWRDN |
12671267 DP_PHY_PD_CTL_DP_CLAMP_EN,
1268− qmp->dp_pcs + QSERDES_DP_PHY_PD_CTL);
1268+ qmp->dp_dp_phy + QSERDES_DP_PHY_PD_CTL);
12691269
12701270 writel(QSERDES_V3_COM_BIAS_EN |
12711271 QSERDES_V3_COM_BIAS_EN_MUX | QSERDES_V3_COM_CLKBUF_R_EN |
@@ -1273,22 +1273,22 @@ static void qmp_v3_dp_aux_init(struct qmp_combo *qmp) · 1 unmodified line
12731273 QSERDES_V3_COM_CLKBUF_RX_DRIVE_L,
12741274 qmp->dp_serdes + QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN);
12751275
1276− writel(0x00, qmp->dp_pcs + QSERDES_DP_PHY_AUX_CFG0);
1277− writel(0x13, qmp->dp_pcs + QSERDES_DP_PHY_AUX_CFG1);
1278− writel(0x24, qmp->dp_pcs + QSERDES_DP_PHY_AUX_CFG2);
1279− writel(0x00, qmp->dp_pcs + QSERDES_DP_PHY_AUX_CFG3);
1280− writel(0x0a, qmp->dp_pcs + QSERDES_DP_PHY_AUX_CFG4);
1281− writel(0x26, qmp->dp_pcs + QSERDES_DP_PHY_AUX_CFG5);
1282− writel(0x0a, qmp->dp_pcs + QSERDES_DP_PHY_AUX_CFG6);
1283− writel(0x03, qmp->dp_pcs + QSERDES_DP_PHY_AUX_CFG7);
1284− writel(0xbb, qmp->dp_pcs + QSERDES_DP_PHY_AUX_CFG8);
1285− writel(0x03, qmp->dp_pcs + QSERDES_DP_PHY_AUX_CFG9);
1276+ writel(0x00, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG0);
1277+ writel(0x13, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG1);
1278+ writel(0x24, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG2);
1279+ writel(0x00, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG3);
1280+ writel(0x0a, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG4);
1281+ writel(0x26, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG5);
1282+ writel(0x0a, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG6);
1283+ writel(0x03, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG7);
1284+ writel(0xbb, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG8);
1285+ writel(0x03, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG9);
12861286 qmp->dp_aux_cfg = 0;
12871287
12881288 writel(PHY_AUX_STOP_ERR_MASK | PHY_AUX_DEC_ERR_MASK |
12891289 PHY_AUX_SYNC_ERR_MASK | PHY_AUX_ALIGN_ERR_MASK |
12901290 PHY_AUX_REQ_ERR_MASK,
1291− qmp->dp_pcs + QSERDES_V3_DP_PHY_AUX_INTERRUPT_MASK);
1291+ qmp->dp_dp_phy + QSERDES_V3_DP_PHY_AUX_INTERRUPT_MASK);
12921292 }
12931293
12941294 static int qmp_combo_configure_dp_swing(struct qmp_combo *qmp,
@@ -1372,12 +1372,12 @@ static bool qmp_combo_configure_dp_mode(struct qmp_combo *qmp) · 77 unmodified lines
13721372 * if (lane_cnt == 4 || orientation == ORIENTATION_CC1)
13731373 * val |= DP_PHY_PD_CTL_LANE_2_3_PWRDN;
13741374 * if (orientation == ORIENTATION_CC2)
1375− * writel(0x4c, qmp->dp_pcs + QSERDES_V3_DP_PHY_MODE);
1375+ * writel(0x4c, qmp->dp_dp_phy + QSERDES_V3_DP_PHY_MODE);
13761376 */
13771377 val |= DP_PHY_PD_CTL_LANE_2_3_PWRDN;
1378− writel(val, qmp->dp_pcs + QSERDES_DP_PHY_PD_CTL);
1378+ writel(val, qmp->dp_dp_phy + QSERDES_DP_PHY_PD_CTL);
13791379
1380− writel(0x5c, qmp->dp_pcs + QSERDES_DP_PHY_MODE);
1380+ writel(0x5c, qmp->dp_dp_phy + QSERDES_DP_PHY_MODE);
13811381
13821382 return reverse;
13831383 }
@@ -1390,8 +1390,8 @@ static int qmp_v3_configure_dp_phy(struct qmp_combo *qmp) · 6 unmodified lines
13901390
13911391 qmp_combo_configure_dp_mode(qmp);
13921392
1393− writel(0x05, qmp->dp_pcs + QSERDES_V3_DP_PHY_TX0_TX1_LANE_CTL);
1394− writel(0x05, qmp->dp_pcs + QSERDES_V3_DP_PHY_TX2_TX3_LANE_CTL);
1393+ writel(0x05, qmp->dp_dp_phy + QSERDES_V3_DP_PHY_TX0_TX1_LANE_CTL);
1394+ writel(0x05, qmp->dp_dp_phy + QSERDES_V3_DP_PHY_TX2_TX3_LANE_CTL);
13951395
13961396 switch (dp_opts->link_rate) {
13971397 case 1620:
@@ -1414,16 +1414,16 @@ static int qmp_v3_configure_dp_phy(struct qmp_combo *qmp) · 16 unmodified lines
14141414 /* Other link rates aren't supported */
14151415 return -EINVAL;
14161416 }
1417− writel(phy_vco_div, qmp->dp_pcs + QSERDES_V3_DP_PHY_VCO_DIV);
1417+ writel(phy_vco_div, qmp->dp_dp_phy + QSERDES_V3_DP_PHY_VCO_DIV);
14181418
14191419 clk_set_rate(qmp->dp_link_hw.clk, dp_opts->link_rate * 100000);
14201420 clk_set_rate(qmp->dp_pixel_hw.clk, pixel_freq);
14211421
1422− writel(0x04, qmp->dp_pcs + QSERDES_DP_PHY_AUX_CFG2);
1423− writel(0x01, qmp->dp_pcs + QSERDES_DP_PHY_CFG);
1424− writel(0x05, qmp->dp_pcs + QSERDES_DP_PHY_CFG);
1425− writel(0x01, qmp->dp_pcs + QSERDES_DP_PHY_CFG);
1426− writel(0x09, qmp->dp_pcs + QSERDES_DP_PHY_CFG);
1422+ writel(0x04, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG2);
1423+ writel(0x01, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG);
1424+ writel(0x05, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG);
1425+ writel(0x01, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG);
1426+ writel(0x09, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG);
14271427
14281428 writel(0x20, qmp->dp_serdes + QSERDES_V3_COM_RESETSM_CNTRL);
14291429
@@ -1434,20 +1434,20 @@ static int qmp_v3_configure_dp_phy(struct qmp_combo *qmp) · 4 unmodified lines
14341434 10000))
14351435 return -ETIMEDOUT;
14361436
1437− writel(0x19, qmp->dp_pcs + QSERDES_DP_PHY_CFG);
1437+ writel(0x19, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG);
14381438
1439− if (readl_poll_timeout(qmp->dp_pcs + QSERDES_V3_DP_PHY_STATUS,
1439+ if (readl_poll_timeout(qmp->dp_dp_phy + QSERDES_V3_DP_PHY_STATUS,
14401440 status,
14411441 ((status & BIT(1)) > 0),
14421442 500,
14431443 10000))
14441444 return -ETIMEDOUT;
14451445
1446− writel(0x18, qmp->dp_pcs + QSERDES_DP_PHY_CFG);
1446+ writel(0x18, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG);
14471447 udelay(2000);
1448− writel(0x19, qmp->dp_pcs + QSERDES_DP_PHY_CFG);
1448+ writel(0x19, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG);
14491449
1450− return readl_poll_timeout(qmp->dp_pcs + QSERDES_V3_DP_PHY_STATUS,
1450+ return readl_poll_timeout(qmp->dp_dp_phy + QSERDES_V3_DP_PHY_STATUS,
14511451 status,
14521452 ((status & BIT(1)) > 0),
14531453 500,
@@ -1467,7 +1467,7 @@ static int qmp_v3_calibrate_dp_phy(struct qmp_combo *qmp) · 13 unmodified lines
14671467 qmp->dp_aux_cfg %= ARRAY_SIZE(cfg1_settings);
14681468 val = cfg1_settings[qmp->dp_aux_cfg];
14691469
1470− writel(val, qmp->dp_pcs + QSERDES_DP_PHY_AUX_CFG1);
1470+ writel(val, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG1);
14711471
14721472 return 0;
14731473 }
@@ -1476,27 +1476,27 @@ static void qmp_v4_dp_aux_init(struct qmp_combo *qmp) · 2 unmodified lines
14761476 {
14771477 writel(DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_PSR_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN |
14781478 DP_PHY_PD_CTL_PLL_PWRDN | DP_PHY_PD_CTL_DP_CLAMP_EN,
1479− qmp->dp_pcs + QSERDES_DP_PHY_PD_CTL);
1479+ qmp->dp_dp_phy + QSERDES_DP_PHY_PD_CTL);
14801480
14811481 /* Turn on BIAS current for PHY/PLL */
14821482 writel(0x17, qmp->dp_serdes + QSERDES_V4_COM_BIAS_EN_CLKBUFLR_EN);
14831483
1484− writel(0x00, qmp->dp_pcs + QSERDES_DP_PHY_AUX_CFG0);
1485− writel(0x13, qmp->dp_pcs + QSERDES_DP_PHY_AUX_CFG1);
1486− writel(0xa4, qmp->dp_pcs + QSERDES_DP_PHY_AUX_CFG2);
1487− writel(0x00, qmp->dp_pcs + QSERDES_DP_PHY_AUX_CFG3);
1488− writel(0x0a, qmp->dp_pcs + QSERDES_DP_PHY_AUX_CFG4);
1489− writel(0x26, qmp->dp_pcs + QSERDES_DP_PHY_AUX_CFG5);
1490− writel(0x0a, qmp->dp_pcs + QSERDES_DP_PHY_AUX_CFG6);
1491− writel(0x03, qmp->dp_pcs + QSERDES_DP_PHY_AUX_CFG7);
1492− writel(0xb7, qmp->dp_pcs + QSERDES_DP_PHY_AUX_CFG8);
1493− writel(0x03, qmp->dp_pcs + QSERDES_DP_PHY_AUX_CFG9);
1484+ writel(0x00, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG0);
1485+ writel(0x13, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG1);
1486+ writel(0xa4, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG2);
1487+ writel(0x00, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG3);
1488+ writel(0x0a, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG4);
1489+ writel(0x26, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG5);
1490+ writel(0x0a, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG6);
1491+ writel(0x03, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG7);
1492+ writel(0xb7, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG8);
1493+ writel(0x03, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG9);
14941494 qmp->dp_aux_cfg = 0;
14951495
14961496 writel(PHY_AUX_STOP_ERR_MASK | PHY_AUX_DEC_ERR_MASK |
14971497 PHY_AUX_SYNC_ERR_MASK | PHY_AUX_ALIGN_ERR_MASK |
14981498 PHY_AUX_REQ_ERR_MASK,
1499− qmp->dp_pcs + QSERDES_V4_DP_PHY_AUX_INTERRUPT_MASK);
1499+ qmp->dp_dp_phy + QSERDES_V4_DP_PHY_AUX_INTERRUPT_MASK);
15001500 }
15011501
15021502 static void qmp_v4_configure_dp_tx(struct qmp_combo *qmp)
@@ -1518,15 +1518,15 @@ static int qmp_v45_configure_dp_phy(struct qmp_combo *qmp) · 15 unmodified lines
15181518 u32 phy_vco_div, status;
15191519 unsigned long pixel_freq;
15201520
1521− writel(0x0f, qmp->dp_pcs + QSERDES_V4_DP_PHY_CFG_1);
1521+ writel(0x0f, qmp->dp_dp_phy + QSERDES_V4_DP_PHY_CFG_1);
15221522
15231523 qmp_combo_configure_dp_mode(qmp);
15241524
1525− writel(0x13, qmp->dp_pcs + QSERDES_DP_PHY_AUX_CFG1);
1526− writel(0xa4, qmp->dp_pcs + QSERDES_DP_PHY_AUX_CFG2);
1525+ writel(0x13, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG1);
1526+ writel(0xa4, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG2);
15271527
1528− writel(0x05, qmp->dp_pcs + QSERDES_V4_DP_PHY_TX0_TX1_LANE_CTL);
1529− writel(0x05, qmp->dp_pcs + QSERDES_V4_DP_PHY_TX2_TX3_LANE_CTL);
1528+ writel(0x05, qmp->dp_dp_phy + QSERDES_V4_DP_PHY_TX0_TX1_LANE_CTL);
1529+ writel(0x05, qmp->dp_dp_phy + QSERDES_V4_DP_PHY_TX2_TX3_LANE_CTL);
15301530
15311531 switch (dp_opts->link_rate) {
15321532 case 1620:
@@ -1549,15 +1549,15 @@ static int qmp_v45_configure_dp_phy(struct qmp_combo *qmp) · 16 unmodified lines
15491549 /* Other link rates aren't supported */
15501550 return -EINVAL;
15511551 }
1552− writel(phy_vco_div, qmp->dp_pcs + QSERDES_V4_DP_PHY_VCO_DIV);
1552+ writel(phy_vco_div, qmp->dp_dp_phy + QSERDES_V4_DP_PHY_VCO_DIV);
15531553
15541554 clk_set_rate(qmp->dp_link_hw.clk, dp_opts->link_rate * 100000);
15551555 clk_set_rate(qmp->dp_pixel_hw.clk, pixel_freq);
15561556
1557− writel(0x01, qmp->dp_pcs + QSERDES_DP_PHY_CFG);
1558− writel(0x05, qmp->dp_pcs + QSERDES_DP_PHY_CFG);
1559− writel(0x01, qmp->dp_pcs + QSERDES_DP_PHY_CFG);
1560− writel(0x09, qmp->dp_pcs + QSERDES_DP_PHY_CFG);
1557+ writel(0x01, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG);
1558+ writel(0x05, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG);
1559+ writel(0x01, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG);
1560+ writel(0x09, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG);
15611561
15621562 writel(0x20, qmp->dp_serdes + QSERDES_V4_COM_RESETSM_CNTRL);
15631563
@@ -1582,16 +1582,16 @@ static int qmp_v45_configure_dp_phy(struct qmp_combo *qmp) · 18 unmodified lines
15821582 10000))
15831583 return -ETIMEDOUT;
15841584
1585− writel(0x19, qmp->dp_pcs + QSERDES_DP_PHY_CFG);
1585+ writel(0x19, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG);
15861586
1587− if (readl_poll_timeout(qmp->dp_pcs + QSERDES_V4_DP_PHY_STATUS,
1587+ if (readl_poll_timeout(qmp->dp_dp_phy + QSERDES_V4_DP_PHY_STATUS,
15881588 status,
15891589 ((status & BIT(0)) > 0),
15901590 500,
15911591 10000))
15921592 return -ETIMEDOUT;
15931593
1594− if (readl_poll_timeout(qmp->dp_pcs + QSERDES_V4_DP_PHY_STATUS,
1594+ if (readl_poll_timeout(qmp->dp_dp_phy + QSERDES_V4_DP_PHY_STATUS,
15951595 status,
15961596 ((status & BIT(1)) > 0),
15971597 500,
@@ -1640,11 +1640,11 @@ static int qmp_v4_configure_dp_phy(struct qmp_combo *qmp) · 42 unmodified lines
16401640 writel(drvr1_en, qmp->dp_tx2 + QSERDES_V4_TX_HIGHZ_DRVR_EN);
16411641 writel(bias1_en, qmp->dp_tx2 + QSERDES_V4_TX_TRANSCEIVER_BIAS_EN);
16421642
1643− writel(0x18, qmp->dp_pcs + QSERDES_DP_PHY_CFG);
1643+ writel(0x18, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG);
16441644 udelay(2000);
1645− writel(0x19, qmp->dp_pcs + QSERDES_DP_PHY_CFG);
1645+ writel(0x19, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG);
16461646
1647− if (readl_poll_timeout(qmp->dp_pcs + QSERDES_V4_DP_PHY_STATUS,
1647+ if (readl_poll_timeout(qmp->dp_dp_phy + QSERDES_V4_DP_PHY_STATUS,
16481648 status,
16491649 ((status & BIT(1)) > 0),
16501650 500,
@@ -1697,11 +1697,11 @@ static int qmp_v5_configure_dp_phy(struct qmp_combo *qmp) · 46 unmodified lines
16971697 writel(drvr1_en, qmp->dp_tx2 + QSERDES_V5_5NM_TX_HIGHZ_DRVR_EN);
16981698 writel(bias1_en, qmp->dp_tx2 + QSERDES_V5_5NM_TX_TRANSCEIVER_BIAS_EN);
16991699
1700− writel(0x18, qmp->dp_pcs + QSERDES_DP_PHY_CFG);
1700+ writel(0x18, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG);
17011701 udelay(2000);
1702− writel(0x19, qmp->dp_pcs + QSERDES_DP_PHY_CFG);
1702+ writel(0x19, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG);
17031703
1704− if (readl_poll_timeout(qmp->dp_pcs + QSERDES_V4_DP_PHY_STATUS,
1704+ if (readl_poll_timeout(qmp->dp_dp_phy + QSERDES_V4_DP_PHY_STATUS,
17051705 status,
17061706 ((status & BIT(1)) > 0),
17071707 500,
@@ -1733,7 +1733,7 @@ static int qmp_v4_calibrate_dp_phy(struct qmp_combo *qmp) · 25 unmodified lines
17331733 qmp->dp_aux_cfg %= ARRAY_SIZE(cfg1_settings);
17341734 val = cfg1_settings[qmp->dp_aux_cfg];
17351735
1736− writel(val, qmp->dp_pcs + QSERDES_DP_PHY_AUX_CFG1);
1736+ writel(val, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG1);
17371737
17381738 return 0;
17391739 }
@@ -1906,7 +1906,7 @@ static int qmp_combo_dp_power_off(struct phy *phy) · 166 unmodified lines
19061906 struct qmp_combo *qmp = phy_get_drvdata(phy);
19071907
19081908 /* Assert DP PHY power down */
1909− writel(DP_PHY_PD_CTL_PSR_PWRDN, qmp->dp_pcs + QSERDES_DP_PHY_PD_CTL);
1909+ writel(DP_PHY_PD_CTL_PSR_PWRDN, qmp->dp_dp_phy + QSERDES_DP_PHY_PD_CTL);
19101910
19111911 return 0;
19121912 }
@@ -2463,15 +2463,16 @@ static int qmp_combo_parse_dt_lecacy_dp(struct qmp_combo *qmp, struct device_nod · 550 unmodified lines
24632463 * Resources are indexed as: tx -> 0; rx -> 1; pcs -> 2;
24642464 * tx2 -> 3; rx2 -> 4
24652465 *
2466− * Note that only tx/tx2 and pcs are used by the DP implementation.
2466+ * Note that only tx/tx2 and pcs (dp_phy) are used by the DP
2467+ * implementation.
24672468 */
24682469 qmp->dp_tx = devm_of_iomap(dev, np, 0, NULL);
24692470 if (IS_ERR(qmp->dp_tx))
24702471 return PTR_ERR(qmp->dp_tx);
24712472
2472− qmp->dp_pcs = devm_of_iomap(dev, np, 2, NULL);
2473− if (IS_ERR(qmp->dp_pcs))
2474− return PTR_ERR(qmp->dp_pcs);
2473+ qmp->dp_dp_phy = devm_of_iomap(dev, np, 2, NULL);
2474+ if (IS_ERR(qmp->dp_dp_phy))
2475+ return PTR_ERR(qmp->dp_dp_phy);
24752476
24762477 qmp->dp_tx2 = devm_of_iomap(dev, np, 3, NULL);
24772478 if (IS_ERR(qmp->dp_tx2))