Misc radeon and amdgpu bug fixes for 4.6. * 'drm-fixes-4.6' of git://people.freedesktop.org/~agd5f/linux: amdgpu/uvd: add uvd fw version for amdgpu drm/amdgpu: forbid mapping of userptr bo through radeon device file drm/radeon: forbid mapping of userptr bo through radeon device file drm/amdgpu: bump the afmt limit for CZ, ST, Polaris drm/amdgpu: use defines for CRTCs and AMFT blocks drm/radeon: print a message if ATPX dGPU power control is missing Revert "drm/radeon: disable runtime pm on PX laptops without dGPU power control" drm/amdgpu/acp: fix resume on CZ systems with AZ audio drm/radeon: add a quirk for a XFX R9 270X drm/radeon: print pci revision as well as pci ids on driver load drm/amdgpu: when suspending, if uvd/vce was running. need to cancel delay work. drm/radeon: fix initial connector audio value
Unified · Split
| @@ -1591,6 +1591,7 @@ struct amdgpu_uvd { · 1590 unmodified lines | ||
| 1591 | 1591 | struct amdgpu_bo *vcpu_bo; |
| 1592 | 1592 | void *cpu_addr; |
| 1593 | 1593 | uint64_t gpu_addr; |
| 1594 | + unsigned fw_version; | |
| 1594 | 1595 | void *saved_bo; |
| 1595 | 1596 | atomic_t handles[AMDGPU_MAX_UVD_HANDLES]; |
| 1596 | 1597 | struct drm_file *filp[AMDGPU_MAX_UVD_HANDLES]; |
| @@ -425,6 +425,10 @@ static int acp_resume(void *handle) · 424 unmodified lines | ||
| 425 | 425 | struct acp_pm_domain *apd; |
| 426 | 426 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
| 427 | 427 | |
| 428 | + /* return early if no ACP */ | |
| 429 | + if (!adev->acp.acp_genpd) | |
| 430 | + return 0; | |
| 431 | + | |
| 428 | 432 | /* SMU block will power on ACP irrespective of ACP runtime status. |
| 429 | 433 | * Power off explicitly based on genpd ACP runtime status so that ACP |
| 430 | 434 | * hw and ACP-genpd status are in sync. |
| @@ -303,7 +303,7 @@ static int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file · 302 unmodified lines | ||
| 303 | 303 | fw_info.feature = adev->vce.fb_version; |
| 304 | 304 | break; |
| 305 | 305 | case AMDGPU_INFO_FW_UVD: |
| 306 | − fw_info.ver = 0; | |
| 306 | + fw_info.ver = adev->uvd.fw_version; | |
| 307 | 307 | fw_info.feature = 0; |
| 308 | 308 | break; |
| 309 | 309 | case AMDGPU_INFO_FW_GMC: |
| @@ -53,7 +53,7 @@ struct amdgpu_hpd; · 52 unmodified lines | ||
| 53 | 53 | |
| 54 | 54 | #define AMDGPU_MAX_HPD_PINS 6 |
| 55 | 55 | #define AMDGPU_MAX_CRTCS 6 |
| 56 | −#define AMDGPU_MAX_AFMT_BLOCKS 7 | |
| 56 | +#define AMDGPU_MAX_AFMT_BLOCKS 9 | |
| 57 | 57 | |
| 58 | 58 | enum amdgpu_rmx_type { |
| 59 | 59 | RMX_OFF, |
| @@ -309,8 +309,8 @@ struct amdgpu_mode_info { · 249 unmodified lines | ||
| 309 | 309 | struct atom_context *atom_context; |
| 310 | 310 | struct card_info *atom_card_info; |
| 311 | 311 | bool mode_config_initialized; |
| 312 | − struct amdgpu_crtc *crtcs[6]; | |
| 313 | − struct amdgpu_afmt *afmt[7]; | |
| 312 | + struct amdgpu_crtc *crtcs[AMDGPU_MAX_CRTCS]; | |
| 313 | + struct amdgpu_afmt *afmt[AMDGPU_MAX_AFMT_BLOCKS]; | |
| 314 | 314 | /* DVI-I properties */ |
| 315 | 315 | struct drm_property *coherent_mode_property; |
| 316 | 316 | /* DAC enable load detect */ |
| @@ -223,6 +223,8 @@ static int amdgpu_verify_access(struct ttm_buffer_object *bo, struct file *filp) · 222 unmodified lines | ||
| 223 | 223 | { |
| 224 | 224 | struct amdgpu_bo *rbo = container_of(bo, struct amdgpu_bo, tbo); |
| 225 | 225 | |
| 226 | + if (amdgpu_ttm_tt_get_usermm(bo->ttm)) | |
| 227 | + return -EPERM; | |
| 226 | 228 | return drm_vma_node_verify_access(&rbo->gem_base.vma_node, filp); |
| 227 | 229 | } |
| 228 | 230 | |
| @@ -158,6 +158,9 @@ int amdgpu_uvd_sw_init(struct amdgpu_device *adev) · 157 unmodified lines | ||
| 158 | 158 | DRM_INFO("Found UVD firmware Version: %hu.%hu Family ID: %hu\n", |
| 159 | 159 | version_major, version_minor, family_id); |
| 160 | 160 | |
| 161 | + adev->uvd.fw_version = ((version_major << 24) | (version_minor << 16) | | |
| 162 | + (family_id << 8)); | |
| 163 | + | |
| 161 | 164 | bo_size = AMDGPU_GPU_PAGE_ALIGN(le32_to_cpu(hdr->ucode_size_bytes) + 8) |
| 162 | 165 | + AMDGPU_UVD_STACK_SIZE + AMDGPU_UVD_HEAP_SIZE; |
| 163 | 166 | r = amdgpu_bo_create(adev, bo_size, PAGE_SIZE, true, |
| @@ -255,6 +258,8 @@ int amdgpu_uvd_suspend(struct amdgpu_device *adev) · 91 unmodified lines | ||
| 255 | 258 | if (i == AMDGPU_MAX_UVD_HANDLES) |
| 256 | 259 | return 0; |
| 257 | 260 | |
| 261 | + cancel_delayed_work_sync(&adev->uvd.idle_work); | |
| 262 | + | |
| 258 | 263 | size = amdgpu_bo_size(adev->uvd.vcpu_bo); |
| 259 | 264 | ptr = adev->uvd.cpu_addr; |
| 260 | 265 | |
| @@ -234,6 +234,7 @@ int amdgpu_vce_suspend(struct amdgpu_device *adev) · 233 unmodified lines | ||
| 234 | 234 | if (i == AMDGPU_MAX_VCE_HANDLES) |
| 235 | 235 | return 0; |
| 236 | 236 | |
| 237 | + cancel_delayed_work_sync(&adev->vce.idle_work); | |
| 237 | 238 | /* TODO: suspending running encoding sessions isn't supported */ |
| 238 | 239 | return -EINVAL; |
| 239 | 240 | } |
| @@ -62,10 +62,6 @@ bool radeon_has_atpx(void) { · 61 unmodified lines | ||
| 62 | 62 | return radeon_atpx_priv.atpx_detected; |
| 63 | 63 | } |
| 64 | 64 | |
| 65 | −bool radeon_has_atpx_dgpu_power_cntl(void) { | |
| 66 | − return radeon_atpx_priv.atpx.functions.power_cntl; | |
| 67 | −} | |
| 68 | − | |
| 69 | 65 | /** |
| 70 | 66 | * radeon_atpx_call - call an ATPX method |
| 71 | 67 | * |
| @@ -145,6 +141,13 @@ static void radeon_atpx_parse_functions(struct radeon_atpx_functions *f, u32 mas · 73 unmodified lines | ||
| 145 | 141 | */ |
| 146 | 142 | static int radeon_atpx_validate(struct radeon_atpx *atpx) |
| 147 | 143 | { |
| 144 | + /* make sure required functions are enabled */ | |
| 145 | + /* dGPU power control is required */ | |
| 146 | + if (atpx->functions.power_cntl == false) { | |
| 147 | + printk("ATPX dGPU power cntl not present, forcing\n"); | |
| 148 | + atpx->functions.power_cntl = true; | |
| 149 | + } | |
| 150 | + | |
| 148 | 151 | if (atpx->functions.px_params) { |
| 149 | 152 | union acpi_object *info; |
| 150 | 153 | struct atpx_px_params output; |
| @@ -2002,10 +2002,12 @@ radeon_add_atom_connector(struct drm_device *dev, · 2001 unmodified lines | ||
| 2002 | 2002 | rdev->mode_info.dither_property, |
| 2003 | 2003 | RADEON_FMT_DITHER_DISABLE); |
| 2004 | 2004 | |
| 2005 | − if (radeon_audio != 0) | |
| 2005 | + if (radeon_audio != 0) { | |
| 2006 | 2006 | drm_object_attach_property(&radeon_connector->base.base, |
| 2007 | 2007 | rdev->mode_info.audio_property, |
| 2008 | 2008 | RADEON_AUDIO_AUTO); |
| 2009 | + radeon_connector->audio = RADEON_AUDIO_AUTO; | |
| 2010 | + } | |
| 2009 | 2011 | if (ASIC_IS_DCE5(rdev)) |
| 2010 | 2012 | drm_object_attach_property(&radeon_connector->base.base, |
| 2011 | 2013 | rdev->mode_info.output_csc_property, |
| @@ -2130,6 +2132,7 @@ radeon_add_atom_connector(struct drm_device *dev, · 118 unmodified lines | ||
| 2130 | 2132 | drm_object_attach_property(&radeon_connector->base.base, |
| 2131 | 2133 | rdev->mode_info.audio_property, |
| 2132 | 2134 | RADEON_AUDIO_AUTO); |
| 2135 | + radeon_connector->audio = RADEON_AUDIO_AUTO; | |
| 2133 | 2136 | } |
| 2134 | 2137 | if (connector_type == DRM_MODE_CONNECTOR_DVII) { |
| 2135 | 2138 | radeon_connector->dac_load_detect = true; |
| @@ -2185,6 +2188,7 @@ radeon_add_atom_connector(struct drm_device *dev, · 49 unmodified lines | ||
| 2185 | 2188 | drm_object_attach_property(&radeon_connector->base.base, |
| 2186 | 2189 | rdev->mode_info.audio_property, |
| 2187 | 2190 | RADEON_AUDIO_AUTO); |
| 2191 | + radeon_connector->audio = RADEON_AUDIO_AUTO; | |
| 2188 | 2192 | } |
| 2189 | 2193 | if (ASIC_IS_DCE5(rdev)) |
| 2190 | 2194 | drm_object_attach_property(&radeon_connector->base.base, |
| @@ -2237,6 +2241,7 @@ radeon_add_atom_connector(struct drm_device *dev, · 46 unmodified lines | ||
| 2237 | 2241 | drm_object_attach_property(&radeon_connector->base.base, |
| 2238 | 2242 | rdev->mode_info.audio_property, |
| 2239 | 2243 | RADEON_AUDIO_AUTO); |
| 2244 | + radeon_connector->audio = RADEON_AUDIO_AUTO; | |
| 2240 | 2245 | } |
| 2241 | 2246 | if (ASIC_IS_DCE5(rdev)) |
| 2242 | 2247 | drm_object_attach_property(&radeon_connector->base.base, |
| @@ -103,12 +103,6 @@ static const char radeon_family_name[][16] = { · 102 unmodified lines | ||
| 103 | 103 | "LAST", |
| 104 | 104 | }; |
| 105 | 105 | |
| 106 | −#if defined(CONFIG_VGA_SWITCHEROO) | |
| 107 | −bool radeon_has_atpx_dgpu_power_cntl(void); | |
| 108 | −#else | |
| 109 | −static inline bool radeon_has_atpx_dgpu_power_cntl(void) { return false; } | |
| 110 | −#endif | |
| 111 | − | |
| 112 | 106 | #define RADEON_PX_QUIRK_DISABLE_PX (1 << 0) |
| 113 | 107 | #define RADEON_PX_QUIRK_LONG_WAKEUP (1 << 1) |
| 114 | 108 | |
| @@ -1305,9 +1299,9 @@ int radeon_device_init(struct radeon_device *rdev, · 1190 unmodified lines | ||
| 1305 | 1299 | } |
| 1306 | 1300 | rdev->fence_context = fence_context_alloc(RADEON_NUM_RINGS); |
| 1307 | 1301 | |
| 1308 | − DRM_INFO("initializing kernel modesetting (%s 0x%04X:0x%04X 0x%04X:0x%04X).\n", | |
| 1309 | − radeon_family_name[rdev->family], pdev->vendor, pdev->device, | |
| 1310 | − pdev->subsystem_vendor, pdev->subsystem_device); | |
| 1302 | + DRM_INFO("initializing kernel modesetting (%s 0x%04X:0x%04X 0x%04X:0x%04X 0x%02X).\n", | |
| 1303 | + radeon_family_name[rdev->family], pdev->vendor, pdev->device, | |
| 1304 | + pdev->subsystem_vendor, pdev->subsystem_device, pdev->revision); | |
| 1311 | 1305 | |
| 1312 | 1306 | /* mutex initialization are all done here so we |
| 1313 | 1307 | * can recall function without having locking issues */ |
| @@ -1439,7 +1433,7 @@ int radeon_device_init(struct radeon_device *rdev, · 125 unmodified lines | ||
| 1439 | 1433 | * ignore it */ |
| 1440 | 1434 | vga_client_register(rdev->pdev, rdev, NULL, radeon_vga_set_decode); |
| 1441 | 1435 | |
| 1442 | − if ((rdev->flags & RADEON_IS_PX) && radeon_has_atpx_dgpu_power_cntl()) | |
| 1436 | + if (rdev->flags & RADEON_IS_PX) | |
| 1443 | 1437 | runtime = true; |
| 1444 | 1438 | vga_switcheroo_register_client(rdev->pdev, &radeon_switcheroo_ops, runtime); |
| 1445 | 1439 | if (runtime) |
| @@ -235,6 +235,8 @@ static int radeon_verify_access(struct ttm_buffer_object *bo, struct file *filp) · 234 unmodified lines | ||
| 235 | 235 | { |
| 236 | 236 | struct radeon_bo *rbo = container_of(bo, struct radeon_bo, tbo); |
| 237 | 237 | |
| 238 | + if (radeon_ttm_tt_has_userptr(bo->ttm)) | |
| 239 | + return -EPERM; | |
| 238 | 240 | return drm_vma_node_verify_access(&rbo->gem_base.vma_node, filp); |
| 239 | 241 | } |
| 240 | 242 | |
| @@ -2931,6 +2931,7 @@ static struct si_dpm_quirk si_dpm_quirk_list[] = { · 2930 unmodified lines | ||
| 2931 | 2931 | { PCI_VENDOR_ID_ATI, 0x6811, 0x1462, 0x2015, 0, 120000 }, |
| 2932 | 2932 | { PCI_VENDOR_ID_ATI, 0x6811, 0x1043, 0x2015, 0, 120000 }, |
| 2933 | 2933 | { PCI_VENDOR_ID_ATI, 0x6811, 0x148c, 0x2015, 0, 120000 }, |
| 2934 | + { PCI_VENDOR_ID_ATI, 0x6810, 0x1682, 0x9275, 0, 120000 }, | |
| 2934 | 2935 | { 0, 0, 0, 0 }, |
| 2935 | 2936 | }; |
| 2936 | 2937 | |