Kalle Valo says: ==================== wireless-next patches for v6.6 The second pull request for v6.6, this time with both stack and driver changes. Unusually we have only one major new feature but lots of small cleanup all over, I guess this is due to people have been on vacation the last month. Major changes: rtw89 - Introduce Time Averaged SAR (TAS) support * tag 'wireless-next-2023-08-25' of git://git.kernel.org/pub/scm/linux/kernel/git/wireless/wireless-next: (114 commits) wifi: rtlwifi: rtl8723: Remove unused function rtl8723_cmd_send_packet() wifi: rtw88: usb: kill and free rx urbs on probe failure wifi: rtw89: Fix clang -Wimplicit-fallthrough in rtw89_query_sar() wifi: rtw89: phy: modify register setting of ENV_MNTR, PHYSTS and DIG wifi: rtw89: phy: add phy_gen_def::cr_base to support WiFi 7 chips wifi: rtw89: mac: define register address of rx_filter to generalize code wifi: rtw89: mac: define internal memory address for WiFi 7 chip wifi: rtw89: mac: generalize code to indirectly access WiFi internal memory wifi: rtw89: mac: add mac_gen_def::band1_offset to map MAC band1 register address wifi: wlcore: sdio: Use module_sdio_driver macro to simplify the code wifi: rtw89: initialize multi-channel handling wifi: rtw89: provide functions to configure NoA for beacon update wifi: rtw89: call rtw89_chan_get() by vif chanctx if aware of vif wifi: rtw89: sar: let caller decide the center frequency to query wifi: rtw89: refine rtw89_correct_cck_chan() by rtw89_hw_to_nl80211_band() wifi: rtw89: add function prototype for coex request duration Fix nomenclature for USB and PCI wireless devices wifi: ath: Use is_multicast_ether_addr() to check multicast Ether address wifi: ath12k: Remove unused declarations wifi: ath12k: add check max message length while scanning with extraie ... ====================
Unified · Split
| @@ -733,7 +733,7 @@ static int ath10k_ahb_probe(struct platform_device *pdev) · 732 unmodified lines | ||
| 733 | 733 | int ret; |
| 734 | 734 | struct ath10k_bus_params bus_params = {}; |
| 735 | 735 | |
| 736 | − hw_rev = (enum ath10k_hw_rev)of_device_get_match_data(&pdev->dev); | |
| 736 | + hw_rev = (uintptr_t)of_device_get_match_data(&pdev->dev); | |
| 737 | 737 | if (!hw_rev) { |
| 738 | 738 | dev_err(&pdev->dev, "OF data missing\n"); |
| 739 | 739 | return -EINVAL; |
| @@ -69,7 +69,7 @@ struct htt_ver_req { · 68 unmodified lines | ||
| 69 | 69 | * The HTT tx descriptor is defined in two manners: by a struct with |
| 70 | 70 | * bitfields, and by a series of [dword offset, bit mask, bit shift] |
| 71 | 71 | * definitions. |
| 72 | − * The target should use the struct def, for simplicitly and clarity, | |
| 72 | + * The target should use the struct def, for simplicity and clarity, | |
| 73 | 73 | * but the host shall use the bit-mast + bit-shift defs, to be endian- |
| 74 | 74 | * neutral. Specifically, the host shall use the get/set macros built |
| 75 | 75 | * around the mask + shift defs. |
| @@ -2086,7 +2086,7 @@ static inline bool ath10k_htt_rx_proc_rx_frag_ind(struct ath10k_htt *htt, · 2010 unmodified lines | ||
| 2086 | 2086 | * for correctly accessing rx descriptor data. |
| 2087 | 2087 | */ |
| 2088 | 2088 | |
| 2089 | −/* base struct used for abstracting the rx descritor representation */ | |
| 2089 | +/* base struct used for abstracting the rx descriptor representation */ | |
| 2090 | 2090 | struct htt_rx_desc { |
| 2091 | 2091 | union { |
| 2092 | 2092 | /* This field is filled on the host using the msdu buffer |
| @@ -1636,7 +1636,7 @@ static int ath10k_pci_dump_memory_generic(struct ath10k *ar, · 1635 unmodified lines | ||
| 1636 | 1636 | buf, |
| 1637 | 1637 | current_region->len); |
| 1638 | 1638 | |
| 1639 | − /* No individiual memory sections defined so we can | |
| 1639 | + /* No individual memory sections defined so we can | |
| 1640 | 1640 | * copy the entire memory region. |
| 1641 | 1641 | */ |
| 1642 | 1642 | ret = ath10k_pci_diag_read_mem(ar, |
| @@ -3816,7 +3816,7 @@ static void __exit ath10k_pci_exit(void) · 2173 unmodified lines | ||
| 3816 | 3816 | module_exit(ath10k_pci_exit); |
| 3817 | 3817 | |
| 3818 | 3818 | MODULE_AUTHOR("Qualcomm Atheros"); |
| 3819 | −MODULE_DESCRIPTION("Driver support for Qualcomm Atheros 802.11ac WLAN PCIe/AHB devices"); | |
| 3819 | +MODULE_DESCRIPTION("Driver support for Qualcomm Atheros PCIe/AHB 802.11ac WLAN devices"); | |
| 3820 | 3820 | MODULE_LICENSE("Dual BSD/GPL"); |
| 3821 | 3821 | |
| 3822 | 3822 | /* QCA988x 2.0 firmware files */ |
| @@ -2389,7 +2389,7 @@ static int ath10k_sdio_dump_memory_generic(struct ath10k *ar, · 2388 unmodified lines | ||
| 2389 | 2389 | buf, |
| 2390 | 2390 | current_region->len); |
| 2391 | 2391 | |
| 2392 | − /* No individiual memory sections defined so we can | |
| 2392 | + /* No individual memory sections defined so we can | |
| 2393 | 2393 | * copy the entire memory region. |
| 2394 | 2394 | */ |
| 2395 | 2395 | if (fast_dump) |
| @@ -1126,5 +1126,5 @@ static struct usb_driver ath10k_usb_driver = { · 1125 unmodified lines | ||
| 1126 | 1126 | module_usb_driver(ath10k_usb_driver); |
| 1127 | 1127 | |
| 1128 | 1128 | MODULE_AUTHOR("Atheros Communications, Inc."); |
| 1129 | −MODULE_DESCRIPTION("Driver support for Qualcomm Atheros 802.11ac WLAN USB devices"); | |
| 1129 | +MODULE_DESCRIPTION("Driver support for Qualcomm Atheros USB 802.11ac WLAN devices"); | |
| 1130 | 1130 | MODULE_LICENSE("Dual BSD/GPL"); |
| @@ -3854,9 +3854,9 @@ enum wmi_pdev_param { · 3853 unmodified lines | ||
| 3854 | 3854 | * retransmitting frames. |
| 3855 | 3855 | */ |
| 3856 | 3856 | WMI_PDEV_PARAM_DYNAMIC_BW, |
| 3857 | − /* Non aggregrate/ 11g sw retry threshold.0-disable */ | |
| 3857 | + /* Non aggregate/ 11g sw retry threshold.0-disable */ | |
| 3858 | 3858 | WMI_PDEV_PARAM_NON_AGG_SW_RETRY_TH, |
| 3859 | − /* aggregrate sw retry threshold. 0-disable*/ | |
| 3859 | + /* aggregate sw retry threshold. 0-disable*/ | |
| 3860 | 3860 | WMI_PDEV_PARAM_AGG_SW_RETRY_TH, |
| 3861 | 3861 | /* Station kickout threshold (non of consecutive failures).0-disable */ |
| 3862 | 3862 | WMI_PDEV_PARAM_STA_KICKOUT_TH, |
| @@ -3953,9 +3953,9 @@ enum wmi_10x_pdev_param { · 90 unmodified lines | ||
| 3953 | 3953 | WMI_10X_PDEV_PARAM_PROTECTION_MODE, |
| 3954 | 3954 | /* Dynamic bandwidth 0: disable 1: enable */ |
| 3955 | 3955 | WMI_10X_PDEV_PARAM_DYNAMIC_BW, |
| 3956 | − /* Non aggregrate/ 11g sw retry threshold.0-disable */ | |
| 3956 | + /* Non aggregate/ 11g sw retry threshold.0-disable */ | |
| 3957 | 3957 | WMI_10X_PDEV_PARAM_NON_AGG_SW_RETRY_TH, |
| 3958 | − /* aggregrate sw retry threshold. 0-disable*/ | |
| 3958 | + /* aggregate sw retry threshold. 0-disable*/ | |
| 3959 | 3959 | WMI_10X_PDEV_PARAM_AGG_SW_RETRY_TH, |
| 3960 | 3960 | /* Station kickout threshold (non of consecutive failures).0-disable */ |
| 3961 | 3961 | WMI_10X_PDEV_PARAM_STA_KICKOUT_TH, |
| @@ -1096,7 +1096,7 @@ static int ath11k_ahb_probe(struct platform_device *pdev) · 1095 unmodified lines | ||
| 1096 | 1096 | return -EINVAL; |
| 1097 | 1097 | } |
| 1098 | 1098 | |
| 1099 | − hw_rev = (enum ath11k_hw_rev)of_id->data; | |
| 1099 | + hw_rev = (uintptr_t)of_id->data; | |
| 1100 | 1100 | |
| 1101 | 1101 | switch (hw_rev) { |
| 1102 | 1102 | case ATH11K_HW_IPQ8074: |
| @@ -1306,17 +1306,7 @@ static struct platform_driver ath11k_ahb_driver = { · 203 unmodified lines | ||
| 1306 | 1306 | .shutdown = ath11k_ahb_shutdown, |
| 1307 | 1307 | }; |
| 1308 | 1308 | |
| 1309 | −static int ath11k_ahb_init(void) | |
| 1310 | −{ | |
| 1311 | − return platform_driver_register(&ath11k_ahb_driver); | |
| 1312 | −} | |
| 1313 | −module_init(ath11k_ahb_init); | |
| 1314 | − | |
| 1315 | −static void ath11k_ahb_exit(void) | |
| 1316 | −{ | |
| 1317 | − platform_driver_unregister(&ath11k_ahb_driver); | |
| 1318 | −} | |
| 1319 | −module_exit(ath11k_ahb_exit); | |
| 1309 | +module_platform_driver(ath11k_ahb_driver); | |
| 1320 | 1310 | |
| 1321 | 1311 | MODULE_DESCRIPTION("Driver support for Qualcomm Technologies 802.11ax WLAN AHB devices"); |
| 1322 | 1312 | MODULE_LICENSE("Dual BSD/GPL"); |
| @@ -203,9 +203,6 @@ int ath11k_ce_alloc_pipes(struct ath11k_base *ab); · 202 unmodified lines | ||
| 203 | 203 | void ath11k_ce_free_pipes(struct ath11k_base *ab); |
| 204 | 204 | int ath11k_ce_get_attr_flags(struct ath11k_base *ab, int ce_id); |
| 205 | 205 | void ath11k_ce_poll_send_completed(struct ath11k_base *ab, u8 pipe_id); |
| 206 | −int ath11k_ce_map_service_to_pipe(struct ath11k_base *ab, u16 service_id, | |
| 207 | − u8 *ul_pipe, u8 *dl_pipe); | |
| 208 | −int ath11k_ce_attr_attach(struct ath11k_base *ab); | |
| 209 | 206 | void ath11k_ce_get_shadow_config(struct ath11k_base *ab, |
| 210 | 207 | u32 **shadow_cfg, u32 *shadow_cfg_len); |
| 211 | 208 | void ath11k_ce_stop_shadow_timers(struct ath11k_base *ab); |
| @@ -635,7 +635,7 @@ enum htt_ppdu_stats_tag_type { · 634 unmodified lines | ||
| 635 | 635 | * b'24 - status_swap: 1 is to swap status TLV |
| 636 | 636 | * b'25 - pkt_swap: 1 is to swap packet TLV |
| 637 | 637 | * b'26:31 - rsvd1: reserved for future use |
| 638 | − * dword1 - b'0:16 - ring_buffer_size: size of bufferes referenced by rx ring, | |
| 638 | + * dword1 - b'0:16 - ring_buffer_size: size of buffers referenced by rx ring, | |
| 639 | 639 | * in byte units. |
| 640 | 640 | * Valid only for HW_TO_SW_RING and SW_TO_HW_RING |
| 641 | 641 | * - b'16:31 - rsvd2: Reserved for future use |
| @@ -3423,7 +3423,7 @@ static int ath11k_dp_rx_h_defrag_reo_reinject(struct ath11k *ar, struct dp_rx_ti · 3422 unmodified lines | ||
| 3423 | 3423 | ath11k_hal_rx_buf_addr_info_set(msdu0, paddr, cookie, |
| 3424 | 3424 | ab->hw_params.hal_params->rx_buf_rbm); |
| 3425 | 3425 | |
| 3426 | − /* Fill mpdu details into reo entrace ring */ | |
| 3426 | + /* Fill mpdu details into reo entrance ring */ | |
| 3427 | 3427 | srng = &ab->hal.srng_list[ab->dp.reo_reinject_ring.ring_id]; |
| 3428 | 3428 | |
| 3429 | 3429 | spin_lock_bh(&srng->lock); |
| @@ -238,7 +238,7 @@ tcl_ring_sel: · 237 unmodified lines | ||
| 238 | 238 | spin_unlock_bh(&tcl_ring->lock); |
| 239 | 239 | ret = -ENOMEM; |
| 240 | 240 | |
| 241 | − /* Checking for available tcl descritors in another ring in | |
| 241 | + /* Checking for available tcl descriptors in another ring in | |
| 242 | 242 | * case of failure due to full tcl ring now, is better than |
| 243 | 243 | * checking this ring earlier for each pkt tx. |
| 244 | 244 | * Restart ring selection if some rings are not checked yet. |
| @@ -344,7 +344,7 @@ ath11k_dp_tx_htt_tx_complete_buf(struct ath11k_base *ab, · 99 unmodified lines | ||
| 344 | 344 | dma_unmap_single(ab->dev, skb_cb->paddr, msdu->len, DMA_TO_DEVICE); |
| 345 | 345 | |
| 346 | 346 | if (!skb_cb->vif) { |
| 347 | − dev_kfree_skb_any(msdu); | |
| 347 | + ieee80211_free_txskb(ar->hw, msdu); | |
| 348 | 348 | return; |
| 349 | 349 | } |
| 350 | 350 | |
| @@ -369,7 +369,7 @@ ath11k_dp_tx_htt_tx_complete_buf(struct ath11k_base *ab, · 18 unmodified lines | ||
| 369 | 369 | "dp_tx: failed to find the peer with peer_id %d\n", |
| 370 | 370 | ts->peer_id); |
| 371 | 371 | spin_unlock_bh(&ab->base_lock); |
| 372 | − dev_kfree_skb_any(msdu); | |
| 372 | + ieee80211_free_txskb(ar->hw, msdu); | |
| 373 | 373 | return; |
| 374 | 374 | } |
| 375 | 375 | spin_unlock_bh(&ab->base_lock); |
| @@ -566,12 +566,12 @@ static void ath11k_dp_tx_complete_msdu(struct ath11k *ar, · 190 unmodified lines | ||
| 566 | 566 | dma_unmap_single(ab->dev, skb_cb->paddr, msdu->len, DMA_TO_DEVICE); |
| 567 | 567 | |
| 568 | 568 | if (unlikely(!rcu_access_pointer(ab->pdevs_active[ar->pdev_idx]))) { |
| 569 | − dev_kfree_skb_any(msdu); | |
| 569 | + ieee80211_free_txskb(ar->hw, msdu); | |
| 570 | 570 | return; |
| 571 | 571 | } |
| 572 | 572 | |
| 573 | 573 | if (unlikely(!skb_cb->vif)) { |
| 574 | − dev_kfree_skb_any(msdu); | |
| 574 | + ieee80211_free_txskb(ar->hw, msdu); | |
| 575 | 575 | return; |
| 576 | 576 | } |
| 577 | 577 | |
| @@ -624,7 +624,7 @@ static void ath11k_dp_tx_complete_msdu(struct ath11k *ar, · 46 unmodified lines | ||
| 624 | 624 | "dp_tx: failed to find the peer with peer_id %d\n", |
| 625 | 625 | ts->peer_id); |
| 626 | 626 | spin_unlock_bh(&ab->base_lock); |
| 627 | − dev_kfree_skb_any(msdu); | |
| 627 | + ieee80211_free_txskb(ar->hw, msdu); | |
| 628 | 628 | return; |
| 629 | 629 | } |
| 630 | 630 | arsta = (struct ath11k_sta *)peer->sta->drv_priv; |
| @@ -566,7 +566,7 @@ static void ath11k_get_arvif_iter(void *data, u8 *mac, · 565 unmodified lines | ||
| 566 | 566 | struct ieee80211_vif *vif) |
| 567 | 567 | { |
| 568 | 568 | struct ath11k_vif_iter *arvif_iter = data; |
| 569 | − struct ath11k_vif *arvif = (void *)vif->drv_priv; | |
| 569 | + struct ath11k_vif *arvif = ath11k_vif_to_arvif(vif); | |
| 570 | 570 | |
| 571 | 571 | if (arvif->vdev_id == arvif_iter->vdev_id) |
| 572 | 572 | arvif_iter->arvif = arvif; |
| @@ -1464,7 +1464,7 @@ static int ath11k_mac_setup_bcn_tmpl_ema(struct ath11k_vif *arvif) · 891 unmodified lines | ||
| 1464 | 1464 | u32 params = 0; |
| 1465 | 1465 | u8 i = 0; |
| 1466 | 1466 | |
| 1467 | − tx_arvif = (void *)arvif->vif->mbssid_tx_vif->drv_priv; | |
| 1467 | + tx_arvif = ath11k_vif_to_arvif(arvif->vif->mbssid_tx_vif); | |
| 1468 | 1468 | |
| 1469 | 1469 | beacons = ieee80211_beacon_get_template_ema_list(tx_arvif->ar->hw, |
| 1470 | 1470 | tx_arvif->vif, 0); |
| @@ -1520,8 +1520,8 @@ static int ath11k_mac_setup_bcn_tmpl_mbssid(struct ath11k_vif *arvif) · 49 unmodified lines | ||
| 1520 | 1520 | struct sk_buff *bcn; |
| 1521 | 1521 | int ret; |
| 1522 | 1522 | |
| 1523 | − if (arvif->vif->mbssid_tx_vif) { | |
| 1524 | − tx_arvif = (void *)arvif->vif->mbssid_tx_vif->drv_priv; | |
| 1523 | + if (vif->mbssid_tx_vif) { | |
| 1524 | + tx_arvif = ath11k_vif_to_arvif(vif->mbssid_tx_vif); | |
| 1525 | 1525 | if (tx_arvif != arvif) { |
| 1526 | 1526 | ar = tx_arvif->ar; |
| 1527 | 1527 | ab = ar->ab; |
| @@ -1562,7 +1562,7 @@ static int ath11k_mac_setup_bcn_tmpl(struct ath11k_vif *arvif) · 34 unmodified lines | ||
| 1562 | 1562 | * non-transmitting interfaces, and results in a crash if sent. |
| 1563 | 1563 | */ |
| 1564 | 1564 | if (vif->mbssid_tx_vif && |
| 1565 | − arvif != (void *)vif->mbssid_tx_vif->drv_priv && arvif->is_up) | |
| 1565 | + arvif != ath11k_vif_to_arvif(vif->mbssid_tx_vif) && arvif->is_up) | |
| 1566 | 1566 | return 0; |
| 1567 | 1567 | |
| 1568 | 1568 | if (vif->bss_conf.ema_ap && vif->mbssid_tx_vif) |
| @@ -1626,7 +1626,7 @@ static void ath11k_control_beaconing(struct ath11k_vif *arvif, · 57 unmodified lines | ||
| 1626 | 1626 | ether_addr_copy(arvif->bssid, info->bssid); |
| 1627 | 1627 | |
| 1628 | 1628 | if (arvif->vif->mbssid_tx_vif) |
| 1629 | − tx_arvif = (struct ath11k_vif *)arvif->vif->mbssid_tx_vif->drv_priv; | |
| 1629 | + tx_arvif = ath11k_vif_to_arvif(arvif->vif->mbssid_tx_vif); | |
| 1630 | 1630 | |
| 1631 | 1631 | ret = ath11k_wmi_vdev_up(arvif->ar, arvif->vdev_id, arvif->aid, |
| 1632 | 1632 | arvif->bssid, |
| @@ -1649,7 +1649,7 @@ static void ath11k_mac_handle_beacon_iter(void *data, u8 *mac, · 16 unmodified lines | ||
| 1649 | 1649 | { |
| 1650 | 1650 | struct sk_buff *skb = data; |
| 1651 | 1651 | struct ieee80211_mgmt *mgmt = (void *)skb->data; |
| 1652 | − struct ath11k_vif *arvif = (void *)vif->drv_priv; | |
| 1652 | + struct ath11k_vif *arvif = ath11k_vif_to_arvif(vif); | |
| 1653 | 1653 | |
| 1654 | 1654 | if (vif->type != NL80211_IFTYPE_STATION) |
| 1655 | 1655 | return; |
| @@ -1672,7 +1672,7 @@ static void ath11k_mac_handle_beacon_miss_iter(void *data, u8 *mac, · 16 unmodified lines | ||
| 1672 | 1672 | struct ieee80211_vif *vif) |
| 1673 | 1673 | { |
| 1674 | 1674 | u32 *vdev_id = data; |
| 1675 | − struct ath11k_vif *arvif = (void *)vif->drv_priv; | |
| 1675 | + struct ath11k_vif *arvif = ath11k_vif_to_arvif(vif); | |
| 1676 | 1676 | struct ath11k *ar = arvif->ar; |
| 1677 | 1677 | struct ieee80211_hw *hw = ar->hw; |
| 1678 | 1678 | |
| @@ -1718,7 +1718,7 @@ static void ath11k_peer_assoc_h_basic(struct ath11k *ar, · 39 unmodified lines | ||
| 1718 | 1718 | struct ieee80211_sta *sta, |
| 1719 | 1719 | struct peer_assoc_params *arg) |
| 1720 | 1720 | { |
| 1721 | − struct ath11k_vif *arvif = (void *)vif->drv_priv; | |
| 1721 | + struct ath11k_vif *arvif = ath11k_vif_to_arvif(vif); | |
| 1722 | 1722 | u32 aid; |
| 1723 | 1723 | |
| 1724 | 1724 | lockdep_assert_held(&ar->conf_mutex); |
| @@ -1746,7 +1746,7 @@ static void ath11k_peer_assoc_h_crypto(struct ath11k *ar, · 21 unmodified lines | ||
| 1746 | 1746 | struct ieee80211_bss_conf *info = &vif->bss_conf; |
| 1747 | 1747 | struct cfg80211_chan_def def; |
| 1748 | 1748 | struct cfg80211_bss *bss; |
| 1749 | − struct ath11k_vif *arvif = (struct ath11k_vif *)vif->drv_priv; | |
| 1749 | + struct ath11k_vif *arvif = ath11k_vif_to_arvif(vif); | |
| 1750 | 1750 | const u8 *rsnie = NULL; |
| 1751 | 1751 | const u8 *wpaie = NULL; |
| 1752 | 1752 | |
| @@ -1804,7 +1804,7 @@ static void ath11k_peer_assoc_h_rates(struct ath11k *ar, · 51 unmodified lines | ||
| 1804 | 1804 | struct ieee80211_sta *sta, |
| 1805 | 1805 | struct peer_assoc_params *arg) |
| 1806 | 1806 | { |
| 1807 | − struct ath11k_vif *arvif = (void *)vif->drv_priv; | |
| 1807 | + struct ath11k_vif *arvif = ath11k_vif_to_arvif(vif); | |
| 1808 | 1808 | struct wmi_rate_set_arg *rateset = &arg->peer_legacy_rates; |
| 1809 | 1809 | struct cfg80211_chan_def def; |
| 1810 | 1810 | const struct ieee80211_supported_band *sband; |
| @@ -1867,7 +1867,7 @@ static void ath11k_peer_assoc_h_ht(struct ath11k *ar, · 56 unmodified lines | ||
| 1867 | 1867 | struct peer_assoc_params *arg) |
| 1868 | 1868 | { |
| 1869 | 1869 | const struct ieee80211_sta_ht_cap *ht_cap = &sta->deflink.ht_cap; |
| 1870 | − struct ath11k_vif *arvif = (void *)vif->drv_priv; | |
| 1870 | + struct ath11k_vif *arvif = ath11k_vif_to_arvif(vif); | |
| 1871 | 1871 | struct cfg80211_chan_def def; |
| 1872 | 1872 | enum nl80211_band band; |
| 1873 | 1873 | const u8 *ht_mcs_mask; |
| @@ -2064,7 +2064,7 @@ static void ath11k_peer_assoc_h_vht(struct ath11k *ar, · 190 unmodified lines | ||
| 2064 | 2064 | struct peer_assoc_params *arg) |
| 2065 | 2065 | { |
| 2066 | 2066 | const struct ieee80211_sta_vht_cap *vht_cap = &sta->deflink.vht_cap; |
| 2067 | − struct ath11k_vif *arvif = (void *)vif->drv_priv; | |
| 2067 | + struct ath11k_vif *arvif = ath11k_vif_to_arvif(vif); | |
| 2068 | 2068 | struct cfg80211_chan_def def; |
| 2069 | 2069 | enum nl80211_band band; |
| 2070 | 2070 | u16 *vht_mcs_mask; |
| @@ -2261,7 +2261,7 @@ static void ath11k_peer_assoc_h_he(struct ath11k *ar, · 190 unmodified lines | ||
| 2261 | 2261 | struct ieee80211_sta *sta, |
| 2262 | 2262 | struct peer_assoc_params *arg) |
| 2263 | 2263 | { |
| 2264 | − struct ath11k_vif *arvif = (void *)vif->drv_priv; | |
| 2264 | + struct ath11k_vif *arvif = ath11k_vif_to_arvif(vif); | |
| 2265 | 2265 | struct cfg80211_chan_def def; |
| 2266 | 2266 | const struct ieee80211_sta_he_cap *he_cap = &sta->deflink.he_cap; |
| 2267 | 2267 | enum nl80211_band band; |
| @@ -2584,7 +2584,7 @@ static void ath11k_peer_assoc_h_qos(struct ath11k *ar, · 316 unmodified lines | ||
| 2584 | 2584 | struct ieee80211_sta *sta, |
| 2585 | 2585 | struct peer_assoc_params *arg) |
| 2586 | 2586 | { |
| 2587 | − struct ath11k_vif *arvif = (void *)vif->drv_priv; | |
| 2587 | + struct ath11k_vif *arvif = ath11k_vif_to_arvif(vif); | |
| 2588 | 2588 | |
| 2589 | 2589 | switch (arvif->vdev_type) { |
| 2590 | 2590 | case WMI_VDEV_TYPE_AP: |
| @@ -2747,7 +2747,7 @@ static void ath11k_peer_assoc_h_phymode(struct ath11k *ar, · 156 unmodified lines | ||
| 2747 | 2747 | struct ieee80211_sta *sta, |
| 2748 | 2748 | struct peer_assoc_params *arg) |
| 2749 | 2749 | { |
| 2750 | − struct ath11k_vif *arvif = (void *)vif->drv_priv; | |
| 2750 | + struct ath11k_vif *arvif = ath11k_vif_to_arvif(vif); | |
| 2751 | 2751 | struct cfg80211_chan_def def; |
| 2752 | 2752 | enum nl80211_band band; |
| 2753 | 2753 | const u8 *ht_mcs_mask; |
| @@ -2933,7 +2933,7 @@ static bool ath11k_mac_vif_recalc_sta_he_txbf(struct ath11k *ar, · 179 unmodified lines | ||
| 2933 | 2933 | struct ieee80211_vif *vif, |
| 2934 | 2934 | struct ieee80211_sta_he_cap *he_cap) |
| 2935 | 2935 | { |
| 2936 | − struct ath11k_vif *arvif = (void *)vif->drv_priv; | |
| 2936 | + struct ath11k_vif *arvif = ath11k_vif_to_arvif(vif); | |
| 2937 | 2937 | struct ieee80211_he_cap_elem he_cap_elem = {0}; |
| 2938 | 2938 | struct ieee80211_sta_he_cap *cap_band = NULL; |
| 2939 | 2939 | struct cfg80211_chan_def def; |
| @@ -2995,7 +2995,7 @@ static void ath11k_bss_assoc(struct ieee80211_hw *hw, · 55 unmodified lines | ||
| 2995 | 2995 | struct ieee80211_bss_conf *bss_conf) |
| 2996 | 2996 | { |
| 2997 | 2997 | struct ath11k *ar = hw->priv; |
| 2998 | − struct ath11k_vif *arvif = (void *)vif->drv_priv; | |
| 2998 | + struct ath11k_vif *arvif = ath11k_vif_to_arvif(vif); | |
| 2999 | 2999 | struct peer_assoc_params peer_arg; |
| 3000 | 3000 | struct ieee80211_sta *ap_sta; |
| 3001 | 3001 | struct ath11k_peer *peer; |
| @@ -3111,7 +3111,7 @@ static void ath11k_bss_disassoc(struct ieee80211_hw *hw, · 109 unmodified lines | ||
| 3111 | 3111 | struct ieee80211_vif *vif) |
| 3112 | 3112 | { |
| 3113 | 3113 | struct ath11k *ar = hw->priv; |
| 3114 | − struct ath11k_vif *arvif = (void *)vif->drv_priv; | |
| 3114 | + struct ath11k_vif *arvif = ath11k_vif_to_arvif(vif); | |
| 3115 | 3115 | int ret; |
| 3116 | 3116 | |
| 3117 | 3117 | lockdep_assert_held(&ar->conf_mutex); |
| @@ -3160,7 +3160,7 @@ static void ath11k_recalculate_mgmt_rate(struct ath11k *ar, · 42 unmodified lines | ||
| 3160 | 3160 | struct ieee80211_vif *vif, |
| 3161 | 3161 | struct cfg80211_chan_def *def) |
| 3162 | 3162 | { |
| 3163 | − struct ath11k_vif *arvif = (void *)vif->drv_priv; | |
| 3163 | + struct ath11k_vif *arvif = ath11k_vif_to_arvif(vif); | |
| 3164 | 3164 | const struct ieee80211_supported_band *sband; |
| 3165 | 3165 | u8 basic_rate_idx; |
| 3166 | 3166 | int hw_rate_code; |
| @@ -4632,7 +4632,7 @@ static int ath11k_station_disassoc(struct ath11k *ar, · 1465 unmodified lines | ||
| 4632 | 4632 | struct ieee80211_vif *vif, |
| 4633 | 4633 | struct ieee80211_sta *sta) |
| 4634 | 4634 | { |
| 4635 | − struct ath11k_vif *arvif = (void *)vif->drv_priv; | |
| 4635 | + struct ath11k_vif *arvif = ath11k_vif_to_arvif(vif); | |
| 4636 | 4636 | int ret = 0; |
| 4637 | 4637 | |
| 4638 | 4638 | lockdep_assert_held(&ar->conf_mutex); |
| @@ -5160,7 +5160,7 @@ static int ath11k_mac_op_sta_set_txpwr(struct ieee80211_hw *hw, · 521 unmodified lines | ||
| 5160 | 5160 | struct ieee80211_sta *sta) |
| 5161 | 5161 | { |
| 5162 | 5162 | struct ath11k *ar = hw->priv; |
| 5163 | − struct ath11k_vif *arvif = (void *)vif->drv_priv; | |
| 5163 | + struct ath11k_vif *arvif = ath11k_vif_to_arvif(vif); | |
| 5164 | 5164 | int ret = 0; |
| 5165 | 5165 | s16 txpwr; |
| 5166 | 5166 | |
| @@ -5210,7 +5210,7 @@ static void ath11k_mac_op_sta_rc_update(struct ieee80211_hw *hw, · 43 unmodified lines | ||
| 5210 | 5210 | { |
| 5211 | 5211 | struct ath11k *ar = hw->priv; |
| 5212 | 5212 | struct ath11k_sta *arsta = (struct ath11k_sta *)sta->drv_priv; |
| 5213 | − struct ath11k_vif *arvif = (void *)vif->drv_priv; | |
| 5213 | + struct ath11k_vif *arvif = ath11k_vif_to_arvif(vif); | |
| 5214 | 5214 | struct ath11k_peer *peer; |
| 5215 | 5215 | u32 bw, smps; |
| 5216 | 5216 | |
| @@ -5337,7 +5337,7 @@ static int ath11k_mac_op_conf_tx(struct ieee80211_hw *hw, · 120 unmodified lines | ||
| 5337 | 5337 | const struct ieee80211_tx_queue_params *params) |
| 5338 | 5338 | { |
| 5339 | 5339 | struct ath11k *ar = hw->priv; |
| 5340 | − struct ath11k_vif *arvif = (void *)vif->drv_priv; | |
| 5340 | + struct ath11k_vif *arvif = ath11k_vif_to_arvif(vif); | |
| 5341 | 5341 | struct wmi_wmm_params_arg *p = NULL; |
| 5342 | 5342 | int ret; |
| 5343 | 5343 | |
| @@ -6455,7 +6455,7 @@ static int ath11k_mac_setup_vdev_params_mbssid(struct ath11k_vif *arvif, · 1111 unmodified lines | ||
| 6455 | 6455 | return 0; |
| 6456 | 6456 | } |
| 6457 | 6457 | |
| 6458 | − tx_arvif = (void *)tx_vif->drv_priv; | |
| 6458 | + tx_arvif = ath11k_vif_to_arvif(tx_vif); | |
| 6459 | 6459 | |
| 6460 | 6460 | if (arvif->vif->bss_conf.nontransmitted) { |
| 6461 | 6461 | if (ar->hw->wiphy != ieee80211_vif_to_wdev(tx_vif)->wiphy) |
| @@ -7408,7 +7408,7 @@ ath11k_mac_update_vif_chan(struct ath11k *ar, · 946 unmodified lines | ||
| 7408 | 7408 | /* TODO: Update ar->rx_channel */ |
| 7409 | 7409 | |
| 7410 | 7410 | for (i = 0; i < n_vifs; i++) { |
| 7411 | − arvif = (void *)vifs[i].vif->drv_priv; | |
| 7411 | + arvif = ath11k_vif_to_arvif(vifs[i].vif); | |
| 7412 | 7412 | |
| 7413 | 7413 | if (WARN_ON(!arvif->is_started)) |
| 7414 | 7414 | continue; |
| @@ -7450,7 +7450,7 @@ ath11k_mac_update_vif_chan(struct ath11k *ar, · 35 unmodified lines | ||
| 7450 | 7450 | |
| 7451 | 7451 | mbssid_tx_vif = arvif->vif->mbssid_tx_vif; |
| 7452 | 7452 | if (mbssid_tx_vif) |
| 7453 | − tx_arvif = (struct ath11k_vif *)mbssid_tx_vif->drv_priv; | |
| 7453 | + tx_arvif = ath11k_vif_to_arvif(mbssid_tx_vif); | |
| 7454 | 7454 | |
| 7455 | 7455 | ret = ath11k_wmi_vdev_up(arvif->ar, arvif->vdev_id, arvif->aid, |
| 7456 | 7456 | arvif->bssid, |
| @@ -7546,7 +7546,7 @@ static int ath11k_start_vdev_delay(struct ieee80211_hw *hw, · 89 unmodified lines | ||
| 7546 | 7546 | { |
| 7547 | 7547 | struct ath11k *ar = hw->priv; |
| 7548 | 7548 | struct ath11k_base *ab = ar->ab; |
| 7549 | − struct ath11k_vif *arvif = (void *)vif->drv_priv; | |
| 7549 | + struct ath11k_vif *arvif = ath11k_vif_to_arvif(vif); | |
| 7550 | 7550 | int ret; |
| 7551 | 7551 | |
| 7552 | 7552 | if (WARN_ON(arvif->is_started)) |
| @@ -7596,7 +7596,7 @@ ath11k_mac_op_assign_vif_chanctx(struct ieee80211_hw *hw, · 43 unmodified lines | ||
| 7596 | 7596 | { |
| 7597 | 7597 | struct ath11k *ar = hw->priv; |
| 7598 | 7598 | struct ath11k_base *ab = ar->ab; |
| 7599 | − struct ath11k_vif *arvif = (void *)vif->drv_priv; | |
| 7599 | + struct ath11k_vif *arvif = ath11k_vif_to_arvif(vif); | |
| 7600 | 7600 | int ret; |
| 7601 | 7601 | struct peer_create_params param; |
| 7602 | 7602 | |
| @@ -7686,7 +7686,7 @@ ath11k_mac_op_unassign_vif_chanctx(struct ieee80211_hw *hw, · 83 unmodified lines | ||
| 7686 | 7686 | { |
| 7687 | 7687 | struct ath11k *ar = hw->priv; |
| 7688 | 7688 | struct ath11k_base *ab = ar->ab; |
| 7689 | − struct ath11k_vif *arvif = (void *)vif->drv_priv; | |
| 7689 | + struct ath11k_vif *arvif = ath11k_vif_to_arvif(vif); | |
| 7690 | 7690 | struct ath11k_peer *peer; |
| 7691 | 7691 | int ret; |
| 7692 | 7692 | |
| @@ -8307,7 +8307,7 @@ ath11k_mac_op_set_bitrate_mask(struct ieee80211_hw *hw, · 614 unmodified lines | ||
| 8307 | 8307 | struct ieee80211_vif *vif, |
| 8308 | 8308 | const struct cfg80211_bitrate_mask *mask) |
| 8309 | 8309 | { |
| 8310 | − struct ath11k_vif *arvif = (void *)vif->drv_priv; | |
| 8310 | + struct ath11k_vif *arvif = ath11k_vif_to_arvif(vif); | |
| 8311 | 8311 | struct cfg80211_chan_def def; |
| 8312 | 8312 | struct ath11k_pdev_cap *cap; |
| 8313 | 8313 | struct ath11k *ar = arvif->ar; |
| @@ -8904,7 +8904,7 @@ static int ath11k_mac_op_remain_on_channel(struct ieee80211_hw *hw, · 590 unmodified lines | ||
| 8904 | 8904 | enum ieee80211_roc_type type) |
| 8905 | 8905 | { |
| 8906 | 8906 | struct ath11k *ar = hw->priv; |
| 8907 | − struct ath11k_vif *arvif = (void *)vif->drv_priv; | |
| 8907 | + struct ath11k_vif *arvif = ath11k_vif_to_arvif(vif); | |
| 8908 | 8908 | struct scan_req_params arg; |
| 8909 | 8909 | int ret; |
| 8910 | 8910 | u32 scan_time_msec; |
| @@ -1036,7 +1036,7 @@ static void ath11k_pci_exit(void) · 1035 unmodified lines | ||
| 1036 | 1036 | |
| 1037 | 1037 | module_exit(ath11k_pci_exit); |
| 1038 | 1038 | |
| 1039 | −MODULE_DESCRIPTION("Driver support for Qualcomm Technologies 802.11ax WLAN PCIe devices"); | |
| 1039 | +MODULE_DESCRIPTION("Driver support for Qualcomm Technologies PCIe 802.11ax WLAN devices"); | |
| 1040 | 1040 | MODULE_LICENSE("Dual BSD/GPL"); |
| 1041 | 1041 | |
| 1042 | 1042 | /* firmware files */ |
| @@ -514,8 +514,6 @@ struct qmi_wlanfw_wlan_ini_resp_msg_v01 { · 513 unmodified lines | ||
| 514 | 514 | int ath11k_qmi_firmware_start(struct ath11k_base *ab, |
| 515 | 515 | u32 mode); |
| 516 | 516 | void ath11k_qmi_firmware_stop(struct ath11k_base *ab); |
| 517 | −void ath11k_qmi_event_work(struct work_struct *work); | |
| 518 | −void ath11k_qmi_msg_recv_work(struct work_struct *work); | |
| 519 | 517 | void ath11k_qmi_deinit_service(struct ath11k_base *ab); |
| 520 | 518 | int ath11k_qmi_init_service(struct ath11k_base *ab); |
| 521 | 519 | void ath11k_qmi_free_resource(struct ath11k_base *ab); |
| @@ -350,7 +350,7 @@ static int ath11k_tm_cmd_wmi(struct ath11k *ar, struct nlattr *tb[], · 349 unmodified lines | ||
| 350 | 350 | if (ar->ab->fw_mode != ATH11K_FIRMWARE_MODE_FTM && |
| 351 | 351 | (tag == WMI_TAG_VDEV_SET_PARAM_CMD || tag == WMI_TAG_UNIT_TEST_CMD)) { |
| 352 | 352 | if (vif) { |
| 353 | − arvif = (struct ath11k_vif *)vif->drv_priv; | |
| 353 | + arvif = ath11k_vif_to_arvif(vif); | |
| 354 | 354 | *ptr = arvif->vdev_id; |
| 355 | 355 | } else { |
| 356 | 356 | ret = -EINVAL; |
| @@ -176,9 +176,6 @@ int ath12k_ce_alloc_pipes(struct ath12k_base *ab); · 175 unmodified lines | ||
| 176 | 176 | void ath12k_ce_free_pipes(struct ath12k_base *ab); |
| 177 | 177 | int ath12k_ce_get_attr_flags(struct ath12k_base *ab, int ce_id); |
| 178 | 178 | void ath12k_ce_poll_send_completed(struct ath12k_base *ab, u8 pipe_id); |
| 179 | −int ath12k_ce_map_service_to_pipe(struct ath12k_base *ab, u16 service_id, | |
| 180 | − u8 *ul_pipe, u8 *dl_pipe); | |
| 181 | −int ath12k_ce_attr_attach(struct ath12k_base *ab); | |
| 182 | 179 | void ath12k_ce_get_shadow_config(struct ath12k_base *ab, |
| 183 | 180 | u32 **shadow_cfg, u32 *shadow_cfg_len); |
| 184 | 181 | #endif |
| @@ -788,7 +788,6 @@ int ath12k_core_fetch_board_data_api_1(struct ath12k_base *ab, · 787 unmodified lines | ||
| 788 | 788 | int ath12k_core_fetch_bdf(struct ath12k_base *ath12k, |
| 789 | 789 | struct ath12k_board_data *bd); |
| 790 | 790 | void ath12k_core_free_bdf(struct ath12k_base *ab, struct ath12k_board_data *bd); |
| 791 | −int ath12k_core_check_dt(struct ath12k_base *ath12k); | |
| 792 | 791 | |
| 793 | 792 | void ath12k_core_halt(struct ath12k *ar); |
| 794 | 793 | int ath12k_core_resume(struct ath12k_base *ab); |
| @@ -1129,6 +1129,7 @@ static void ath12k_dp_cc_cleanup(struct ath12k_base *ab) · 1128 unmodified lines | ||
| 1129 | 1129 | struct ath12k_dp *dp = &ab->dp; |
| 1130 | 1130 | struct sk_buff *skb; |
| 1131 | 1131 | int i; |
| 1132 | + u32 pool_id, tx_spt_page; | |
| 1132 | 1133 | |
| 1133 | 1134 | if (!dp->spt_info) |
| 1134 | 1135 | return; |
| @@ -1148,6 +1149,14 @@ static void ath12k_dp_cc_cleanup(struct ath12k_base *ab) · 13 unmodified lines | ||
| 1148 | 1149 | dev_kfree_skb_any(skb); |
| 1149 | 1150 | } |
| 1150 | 1151 | |
| 1152 | + for (i = 0; i < ATH12K_NUM_RX_SPT_PAGES; i++) { | |
| 1153 | + if (!dp->spt_info->rxbaddr[i]) | |
| 1154 | + continue; | |
| 1155 | + | |
| 1156 | + kfree(dp->spt_info->rxbaddr[i]); | |
| 1157 | + dp->spt_info->rxbaddr[i] = NULL; | |
| 1158 | + } | |
| 1159 | + | |
| 1151 | 1160 | spin_unlock_bh(&dp->rx_desc_lock); |
| 1152 | 1161 | |
| 1153 | 1162 | /* TX Descriptor cleanup */ |
| @@ -1170,6 +1179,21 @@ static void ath12k_dp_cc_cleanup(struct ath12k_base *ab) · 16 unmodified lines | ||
| 1170 | 1179 | spin_unlock_bh(&dp->tx_desc_lock[i]); |
| 1171 | 1180 | } |
| 1172 | 1181 | |
| 1182 | + for (pool_id = 0; pool_id < ATH12K_HW_MAX_QUEUES; pool_id++) { | |
| 1183 | + spin_lock_bh(&dp->tx_desc_lock[pool_id]); | |
| 1184 | + | |
| 1185 | + for (i = 0; i < ATH12K_TX_SPT_PAGES_PER_POOL; i++) { | |
| 1186 | + tx_spt_page = i + pool_id * ATH12K_TX_SPT_PAGES_PER_POOL; | |
| 1187 | + if (!dp->spt_info->txbaddr[tx_spt_page]) | |
| 1188 | + continue; | |
| 1189 | + | |
| 1190 | + kfree(dp->spt_info->txbaddr[tx_spt_page]); | |
| 1191 | + dp->spt_info->txbaddr[tx_spt_page] = NULL; | |
| 1192 | + } | |
| 1193 | + | |
| 1194 | + spin_unlock_bh(&dp->tx_desc_lock[pool_id]); | |
| 1195 | + } | |
| 1196 | + | |
| 1173 | 1197 | /* unmap SPT pages */ |
| 1174 | 1198 | for (i = 0; i < dp->num_spt_pages; i++) { |
| 1175 | 1199 | if (!dp->spt_info[i].vaddr) |
| @@ -1343,6 +1367,8 @@ static int ath12k_dp_cc_desc_init(struct ath12k_base *ab) · 167 unmodified lines | ||
| 1343 | 1367 | return -ENOMEM; |
| 1344 | 1368 | } |
| 1345 | 1369 | |
| 1370 | + dp->spt_info->rxbaddr[i] = &rx_descs[0]; | |
| 1371 | + | |
| 1346 | 1372 | for (j = 0; j < ATH12K_MAX_SPT_ENTRIES; j++) { |
| 1347 | 1373 | rx_descs[j].cookie = ath12k_dp_cc_cookie_gen(i, j); |
| 1348 | 1374 | rx_descs[j].magic = ATH12K_DP_RX_DESC_MAGIC; |
| @@ -1368,8 +1394,10 @@ static int ath12k_dp_cc_desc_init(struct ath12k_base *ab) · 19 unmodified lines | ||
| 1368 | 1394 | return -ENOMEM; |
| 1369 | 1395 | } |
| 1370 | 1396 | |
| 1397 | + tx_spt_page = i + pool_id * ATH12K_TX_SPT_PAGES_PER_POOL; | |
| 1398 | + dp->spt_info->txbaddr[tx_spt_page] = &tx_descs[0]; | |
| 1399 | + | |
| 1371 | 1400 | for (j = 0; j < ATH12K_MAX_SPT_ENTRIES; j++) { |
| 1372 | − tx_spt_page = i + pool_id * ATH12K_TX_SPT_PAGES_PER_POOL; | |
| 1373 | 1401 | ppt_idx = ATH12K_NUM_RX_SPT_PAGES + tx_spt_page; |
| 1374 | 1402 | tx_descs[j].desc_id = ath12k_dp_cc_cookie_gen(ppt_idx, j); |
| 1375 | 1403 | tx_descs[j].pool_id = pool_id; |
| @@ -289,6 +289,8 @@ struct ath12k_tx_desc_info { · 288 unmodified lines | ||
| 289 | 289 | struct ath12k_spt_info { |
| 290 | 290 | dma_addr_t paddr; |
| 291 | 291 | u64 *vaddr; |
| 292 | + struct ath12k_rx_desc_info *rxbaddr[ATH12K_NUM_RX_SPT_PAGES]; | |
| 293 | + struct ath12k_tx_desc_info *txbaddr[ATH12K_NUM_TX_SPT_PAGES]; | |
| 292 | 294 | }; |
| 293 | 295 | |
| 294 | 296 | struct ath12k_reo_queue_ref { |
| @@ -712,7 +714,7 @@ enum htt_stats_internal_ppdu_frametype { · 417 unmodified lines | ||
| 712 | 714 | * b'24 - status_swap: 1 is to swap status TLV |
| 713 | 715 | * b'25 - pkt_swap: 1 is to swap packet TLV |
| 714 | 716 | * b'26:31 - rsvd1: reserved for future use |
| 715 | − * dword1 - b'0:16 - ring_buffer_size: size of bufferes referenced by rx ring, | |
| 717 | + * dword1 - b'0:16 - ring_buffer_size: size of buffers referenced by rx ring, | |
| 716 | 718 | * in byte units. |
| 717 | 719 | * Valid only for HW_TO_SW_RING and SW_TO_HW_RING |
| 718 | 720 | * - b'16:31 - rsvd2: Reserved for future use |
| @@ -3027,7 +3027,7 @@ static int ath12k_dp_rx_h_defrag_reo_reinject(struct ath12k *ar, · 3026 unmodified lines | ||
| 3027 | 3027 | desc_info->cookie, |
| 3028 | 3028 | HAL_RX_BUF_RBM_SW3_BM); |
| 3029 | 3029 | |
| 3030 | − /* Fill mpdu details into reo entrace ring */ | |
| 3030 | + /* Fill mpdu details into reo entrance ring */ | |
| 3031 | 3031 | srng = &ab->hal.srng_list[dp->reo_reinject_ring.ring_id]; |
| 3032 | 3032 | |
| 3033 | 3033 | spin_lock_bh(&srng->lock); |
| @@ -301,7 +301,7 @@ tcl_ring_sel: · 300 unmodified lines | ||
| 301 | 301 | spin_unlock_bh(&tcl_ring->lock); |
| 302 | 302 | ret = -ENOMEM; |
| 303 | 303 | |
| 304 | − /* Checking for available tcl descritors in another ring in | |
| 304 | + /* Checking for available tcl descriptors in another ring in | |
| 305 | 305 | * case of failure due to full tcl ring now, is better than |
| 306 | 306 | * checking this ring earlier for each pkt tx. |
| 307 | 307 | * Restart ring selection if some rings are not checked yet. |
| @@ -5660,7 +5660,6 @@ static void ath12k_mac_op_configure_filter(struct ieee80211_hw *hw, · 5659 unmodified lines | ||
| 5660 | 5660 | |
| 5661 | 5661 | mutex_lock(&ar->conf_mutex); |
| 5662 | 5662 | |
| 5663 | − changed_flags &= SUPPORTED_FILTERS; | |
| 5664 | 5663 | *total_flags &= SUPPORTED_FILTERS; |
| 5665 | 5664 | ar->filter_flags = *total_flags; |
| 5666 | 5665 | |
| @@ -5678,8 +5677,8 @@ static void ath12k_mac_op_configure_filter(struct ieee80211_hw *hw, · 11 unmodified lines | ||
| 5678 | 5677 | "fail to set monitor filter: %d\n", ret); |
| 5679 | 5678 | } |
| 5680 | 5679 | ath12k_dbg(ar->ab, ATH12K_DBG_MAC, |
| 5681 | − "changed_flags:0x%x, total_flags:0x%x, reset_flag:%d\n", | |
| 5682 | − changed_flags, *total_flags, reset_flag); | |
| 5680 | + "total_flags:0x%x, reset_flag:%d\n", | |
| 5681 | + *total_flags, reset_flag); | |
| 5683 | 5682 | |
| 5684 | 5683 | mutex_unlock(&ar->conf_mutex); |
| 5685 | 5684 | } |
| @@ -6771,7 +6770,7 @@ ath12k_mac_op_reconfig_complete(struct ieee80211_hw *hw, · 1085 unmodified lines | ||
| 6771 | 6770 | /* After trigger disconnect, then upper layer will |
| 6772 | 6771 | * trigger connect again, then the PN number of |
| 6773 | 6772 | * upper layer will be reset to keep up with AP |
| 6774 | − * side, hence PN number mis-match will not happened. | |
| 6773 | + * side, hence PN number mismatch will not happen. | |
| 6775 | 6774 | */ |
| 6776 | 6775 | if (arvif->is_up && |
| 6777 | 6776 | arvif->vdev_type == WMI_VDEV_TYPE_STA && |
| @@ -1409,5 +1409,5 @@ static void ath12k_pci_exit(void) · 1408 unmodified lines | ||
| 1409 | 1409 | |
| 1410 | 1410 | module_exit(ath12k_pci_exit); |
| 1411 | 1411 | |
| 1412 | −MODULE_DESCRIPTION("Driver support for Qualcomm Technologies 802.11be WLAN PCIe devices"); | |
| 1412 | +MODULE_DESCRIPTION("Driver support for Qualcomm Technologies PCIe 802.11be WLAN devices"); | |
| 1413 | 1413 | MODULE_LICENSE("Dual BSD/GPL"); |
| @@ -562,8 +562,6 @@ struct qmi_wlanfw_wlan_cfg_resp_msg_v01 { · 561 unmodified lines | ||
| 562 | 562 | int ath12k_qmi_firmware_start(struct ath12k_base *ab, |
| 563 | 563 | u32 mode); |
| 564 | 564 | void ath12k_qmi_firmware_stop(struct ath12k_base *ab); |
| 565 | −void ath12k_qmi_event_work(struct work_struct *work); | |
| 566 | −void ath12k_qmi_msg_recv_work(struct work_struct *work); | |
| 567 | 565 | void ath12k_qmi_deinit_service(struct ath12k_base *ab); |
| 568 | 566 | int ath12k_qmi_init_service(struct ath12k_base *ab); |
| 569 | 567 | |
| @@ -221,7 +221,7 @@ struct rx_mpdu_start_qcn9274 { · 220 unmodified lines | ||
| 221 | 221 | * PPE routing even if RXOLE CCE or flow search indicate 'Use_PPE' |
| 222 | 222 | * This is set by SW for peers which are being handled by a |
| 223 | 223 | * host SW/accelerator subsystem that also handles packet |
| 224 | − * uffer management for WiFi-to-PPE routing. | |
| 224 | + * buffer management for WiFi-to-PPE routing. | |
| 225 | 225 | * |
| 226 | 226 | * This is cleared by SW for peers which are being handled |
| 227 | 227 | * by a different subsystem, completely disabling WiFi-to-PPE |
| @@ -2239,12 +2239,6 @@ int ath12k_wmi_send_scan_start_cmd(struct ath12k *ar, · 2238 unmodified lines | ||
| 2239 | 2239 | if (arg->num_bssid) |
| 2240 | 2240 | len += sizeof(*bssid) * arg->num_bssid; |
| 2241 | 2241 | |
| 2242 | − len += TLV_HDR_SIZE; | |
| 2243 | − if (arg->extraie.len) | |
| 2244 | − extraie_len_with_pad = | |
| 2245 | − roundup(arg->extraie.len, sizeof(u32)); | |
| 2246 | − len += extraie_len_with_pad; | |
| 2247 | − | |
| 2248 | 2242 | if (arg->num_hint_bssid) |
| 2249 | 2243 | len += TLV_HDR_SIZE + |
| 2250 | 2244 | arg->num_hint_bssid * sizeof(*hint_bssid); |
| @@ -2253,6 +2247,18 @@ int ath12k_wmi_send_scan_start_cmd(struct ath12k *ar, · 2 unmodified lines | ||
| 2253 | 2247 | len += TLV_HDR_SIZE + |
| 2254 | 2248 | arg->num_hint_s_ssid * sizeof(*s_ssid); |
| 2255 | 2249 | |
| 2250 | + len += TLV_HDR_SIZE; | |
| 2251 | + if (arg->extraie.len) | |
| 2252 | + extraie_len_with_pad = | |
| 2253 | + roundup(arg->extraie.len, sizeof(u32)); | |
| 2254 | + if (extraie_len_with_pad <= (wmi->wmi_ab->max_msg_len[ar->pdev_idx] - len)) { | |
| 2255 | + len += extraie_len_with_pad; | |
| 2256 | + } else { | |
| 2257 | + ath12k_warn(ar->ab, "discard large size %d bytes extraie for scan start\n", | |
| 2258 | + arg->extraie.len); | |
| 2259 | + extraie_len_with_pad = 0; | |
| 2260 | + } | |
| 2261 | + | |
| 2256 | 2262 | skb = ath12k_wmi_alloc_skb(wmi->wmi_ab, len); |
| 2257 | 2263 | if (!skb) |
| 2258 | 2264 | return -ENOMEM; |
| @@ -2342,7 +2348,7 @@ int ath12k_wmi_send_scan_start_cmd(struct ath12k *ar, · 83 unmodified lines | ||
| 2342 | 2348 | tlv->header = ath12k_wmi_tlv_hdr(WMI_TAG_ARRAY_BYTE, len); |
| 2343 | 2349 | ptr += TLV_HDR_SIZE; |
| 2344 | 2350 | |
| 2345 | − if (arg->extraie.len) | |
| 2351 | + if (extraie_len_with_pad) | |
| 2346 | 2352 | memcpy(ptr, arg->extraie.ptr, |
| 2347 | 2353 | arg->extraie.len); |
| 2348 | 2354 | |
| @@ -4855,8 +4855,6 @@ int ath12k_wmi_vdev_install_key(struct ath12k *ar, · 4854 unmodified lines | ||
| 4855 | 4855 | struct wmi_vdev_install_key_arg *arg); |
| 4856 | 4856 | int ath12k_wmi_pdev_bss_chan_info_request(struct ath12k *ar, |
| 4857 | 4857 | enum wmi_bss_chan_info_req_type type); |
| 4858 | −int ath12k_wmi_send_stats_request_cmd(struct ath12k *ar, u32 stats_id, | |
| 4859 | − u32 vdev_id, u32 pdev_id); | |
| 4860 | 4858 | int ath12k_wmi_send_pdev_temperature_cmd(struct ath12k *ar); |
| 4861 | 4859 | int ath12k_wmi_send_peer_flush_tids_cmd(struct ath12k *ar, |
| 4862 | 4860 | u8 peer_addr[ETH_ALEN], |
| @@ -115,7 +115,6 @@ static int ath_ahb_probe(struct platform_device *pdev) · 114 unmodified lines | ||
| 115 | 115 | |
| 116 | 116 | irq = platform_get_irq(pdev, 0); |
| 117 | 117 | if (irq < 0) { |
| 118 | − dev_err(&pdev->dev, "no IRQ resource found: %d\n", irq); | |
| 119 | 118 | ret = irq; |
| 120 | 119 | goto err_iounmap; |
| 121 | 120 | } |
| @@ -382,7 +382,6 @@ ath5k_configure_filter(struct ieee80211_hw *hw, unsigned int changed_flags, · 381 unmodified lines | ||
| 382 | 382 | mfilt[1] = multicast >> 32; |
| 383 | 383 | |
| 384 | 384 | /* Only deal with supported flags */ |
| 385 | − changed_flags &= SUPPORTED_FIF_FLAGS; | |
| 386 | 385 | *new_flags &= SUPPORTED_FIF_FLAGS; |
| 387 | 386 | |
| 388 | 387 | /* If HW detects any phy or radar errors, leave those filters on. |
| @@ -26,6 +26,7 @@ · 25 unmodified lines | ||
| 26 | 26 | |
| 27 | 27 | #include <linux/delay.h> |
| 28 | 28 | #include <linux/slab.h> |
| 29 | +#include <linux/sort.h> | |
| 29 | 30 | #include <asm/unaligned.h> |
| 30 | 31 | |
| 31 | 32 | #include "ath5k.h" |
| @@ -1554,6 +1555,11 @@ static void ath5k_hw_update_nfcal_hist(struct ath5k_hw *ah, s16 noise_floor) · 1522 unmodified lines | ||
| 1554 | 1555 | hist->nfval[hist->index] = noise_floor; |
| 1555 | 1556 | } |
| 1556 | 1557 | |
| 1558 | +static int cmps16(const void *a, const void *b) | |
| 1559 | +{ | |
| 1560 | + return *(s16 *)a - *(s16 *)b; | |
| 1561 | +} | |
| 1562 | + | |
| 1557 | 1563 | /** |
| 1558 | 1564 | * ath5k_hw_get_median_noise_floor() - Get median NF from history buffer |
| 1559 | 1565 | * @ah: The &struct ath5k_hw |
| @@ -1561,25 +1567,16 @@ static void ath5k_hw_update_nfcal_hist(struct ath5k_hw *ah, s16 noise_floor) · 1 unmodified line | ||
| 1561 | 1567 | static s16 |
| 1562 | 1568 | ath5k_hw_get_median_noise_floor(struct ath5k_hw *ah) |
| 1563 | 1569 | { |
| 1564 | − s16 sort[ATH5K_NF_CAL_HIST_MAX]; | |
| 1565 | − s16 tmp; | |
| 1566 | − int i, j; | |
| 1567 | − | |
| 1568 | − memcpy(sort, ah->ah_nfcal_hist.nfval, sizeof(sort)); | |
| 1569 | − for (i = 0; i < ATH5K_NF_CAL_HIST_MAX - 1; i++) { | |
| 1570 | − for (j = 1; j < ATH5K_NF_CAL_HIST_MAX - i; j++) { | |
| 1571 | − if (sort[j] > sort[j - 1]) { | |
| 1572 | − tmp = sort[j]; | |
| 1573 | − sort[j] = sort[j - 1]; | |
| 1574 | − sort[j - 1] = tmp; | |
| 1575 | − } | |
| 1576 | − } | |
| 1577 | − } | |
| 1570 | + s16 sorted_nfval[ATH5K_NF_CAL_HIST_MAX]; | |
| 1571 | + int i; | |
| 1572 | + | |
| 1573 | + memcpy(sorted_nfval, ah->ah_nfcal_hist.nfval, sizeof(sorted_nfval)); | |
| 1574 | + sort(sorted_nfval, ATH5K_NF_CAL_HIST_MAX, sizeof(s16), cmps16, NULL); | |
| 1578 | 1575 | for (i = 0; i < ATH5K_NF_CAL_HIST_MAX; i++) { |
| 1579 | 1576 | ATH5K_DBG(ah, ATH5K_DEBUG_CALIBRATE, |
| 1580 | − "cal %d:%d\n", i, sort[i]); | |
| 1577 | + "cal %d:%d\n", i, sorted_nfval[i]); | |
| 1581 | 1578 | } |
| 1582 | − return sort[(ATH5K_NF_CAL_HIST_MAX - 1) / 2]; | |
| 1579 | + return sorted_nfval[(ATH5K_NF_CAL_HIST_MAX - 1) / 2]; | |
| 1583 | 1580 | } |
| 1584 | 1581 | |
| 1585 | 1582 | /** |
| @@ -1129,7 +1129,6 @@ void ath_restart_work(struct ath_softc *sc); · 1128 unmodified lines | ||
| 1129 | 1129 | int ath9k_init_device(u16 devid, struct ath_softc *sc, |
| 1130 | 1130 | const struct ath_bus_ops *bus_ops); |
| 1131 | 1131 | void ath9k_deinit_device(struct ath_softc *sc); |
| 1132 | −void ath9k_reload_chainmask_settings(struct ath_softc *sc); | |
| 1133 | 1132 | u8 ath_txchainmask_reduction(struct ath_softc *sc, u8 chainmask, u32 rate); |
| 1134 | 1133 | void ath_start_rfkill_poll(struct ath_softc *sc); |
| 1135 | 1134 | void ath9k_rfkill_poll_state(struct ieee80211_hw *hw); |
| @@ -855,16 +855,11 @@ static ssize_t write_file_spectral_short_repeat(struct file *file, · 854 unmodified lines | ||
| 855 | 855 | { |
| 856 | 856 | struct ath_spec_scan_priv *spec_priv = file->private_data; |
| 857 | 857 | unsigned long val; |
| 858 | − char buf[32]; | |
| 859 | − ssize_t len; | |
| 860 | − | |
| 861 | − len = min(count, sizeof(buf) - 1); | |
| 862 | − if (copy_from_user(buf, user_buf, len)) | |
| 863 | − return -EFAULT; | |
| 858 | + ssize_t ret; | |
| 864 | 859 | |
| 865 | − buf[len] = '\0'; | |
| 866 | − if (kstrtoul(buf, 0, &val)) | |
| 867 | − return -EINVAL; | |
| 860 | + ret = kstrtoul_from_user(user_buf, count, 0, &val); | |
| 861 | + if (ret) | |
| 862 | + return ret; | |
| 868 | 863 | |
| 869 | 864 | if (val > 1) |
| 870 | 865 | return -EINVAL; |
| @@ -903,17 +898,11 @@ static ssize_t write_file_spectral_count(struct file *file, · 32 unmodified lines | ||
| 903 | 898 | { |
| 904 | 899 | struct ath_spec_scan_priv *spec_priv = file->private_data; |
| 905 | 900 | unsigned long val; |
| 906 | − char buf[32]; | |
| 907 | − ssize_t len; | |
| 908 | − | |
| 909 | − len = min(count, sizeof(buf) - 1); | |
| 910 | − if (copy_from_user(buf, user_buf, len)) | |
| 911 | − return -EFAULT; | |
| 912 | − | |
| 913 | − buf[len] = '\0'; | |
| 914 | − if (kstrtoul(buf, 0, &val)) | |
| 915 | − return -EINVAL; | |
| 901 | + ssize_t ret; | |
| 916 | 902 | |
| 903 | + ret = kstrtoul_from_user(user_buf, count, 0, &val); | |
| 904 | + if (ret) | |
| 905 | + return ret; | |
| 917 | 906 | if (val > 255) |
| 918 | 907 | return -EINVAL; |
| 919 | 908 | |
| @@ -951,16 +940,11 @@ static ssize_t write_file_spectral_period(struct file *file, · 31 unmodified lines | ||
| 951 | 940 | { |
| 952 | 941 | struct ath_spec_scan_priv *spec_priv = file->private_data; |
| 953 | 942 | unsigned long val; |
| 954 | − char buf[32]; | |
| 955 | − ssize_t len; | |
| 956 | − | |
| 957 | − len = min(count, sizeof(buf) - 1); | |
| 958 | − if (copy_from_user(buf, user_buf, len)) | |
| 959 | − return -EFAULT; | |
| 943 | + ssize_t ret; | |
| 960 | 944 | |
| 961 | − buf[len] = '\0'; | |
| 962 | − if (kstrtoul(buf, 0, &val)) | |
| 963 | − return -EINVAL; | |
| 945 | + ret = kstrtoul_from_user(user_buf, count, 0, &val); | |
| 946 | + if (ret) | |
| 947 | + return ret; | |
| 964 | 948 | |
| 965 | 949 | if (val > 255) |
| 966 | 950 | return -EINVAL; |
| @@ -999,16 +983,11 @@ static ssize_t write_file_spectral_fft_period(struct file *file, · 32 unmodified lines | ||
| 999 | 983 | { |
| 1000 | 984 | struct ath_spec_scan_priv *spec_priv = file->private_data; |
| 1001 | 985 | unsigned long val; |
| 1002 | − char buf[32]; | |
| 1003 | − ssize_t len; | |
| 1004 | − | |
| 1005 | − len = min(count, sizeof(buf) - 1); | |
| 1006 | − if (copy_from_user(buf, user_buf, len)) | |
| 1007 | − return -EFAULT; | |
| 986 | + ssize_t ret; | |
| 1008 | 987 | |
| 1009 | − buf[len] = '\0'; | |
| 1010 | − if (kstrtoul(buf, 0, &val)) | |
| 1011 | − return -EINVAL; | |
| 988 | + ret = kstrtoul_from_user(user_buf, count, 0, &val); | |
| 989 | + if (ret) | |
| 990 | + return ret; | |
| 1012 | 991 | |
| 1013 | 992 | if (val > 15) |
| 1014 | 993 | return -EINVAL; |
| @@ -85,8 +85,6 @@ struct ath9k_channel *ath9k_cmn_get_channel(struct ieee80211_hw *hw, · 84 unmodified lines | ||
| 85 | 85 | struct ath_hw *ah, |
| 86 | 86 | struct cfg80211_chan_def *chandef); |
| 87 | 87 | int ath9k_cmn_count_streams(unsigned int chainmask, int max); |
| 88 | −void ath9k_cmn_btcoex_bt_stomp(struct ath_common *common, | |
| 89 | − enum ath_stomp_type stomp_type); | |
| 90 | 88 | void ath9k_cmn_update_txpow(struct ath_hw *ah, u16 cur_txpow, |
| 91 | 89 | u16 new_txpow, u16 *txpower); |
| 92 | 90 | void ath9k_cmn_init_crypto(struct ath_hw *ah); |
| @@ -96,21 +96,16 @@ static ssize_t read_file_debug(struct file *file, char __user *user_buf, · 95 unmodified lines | ||
| 96 | 96 | } |
| 97 | 97 | |
| 98 | 98 | static ssize_t write_file_debug(struct file *file, const char __user *user_buf, |
| 99 | − size_t count, loff_t *ppos) | |
| 99 | + size_t count, loff_t *ppos) | |
| 100 | 100 | { |
| 101 | 101 | struct ath_softc *sc = file->private_data; |
| 102 | 102 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); |
| 103 | 103 | unsigned long mask; |
| 104 | − char buf[32]; | |
| 105 | − ssize_t len; | |
| 104 | + ssize_t ret; | |
| 106 | 105 | |
| 107 | − len = min(count, sizeof(buf) - 1); | |
| 108 | − if (copy_from_user(buf, user_buf, len)) | |
| 109 | − return -EFAULT; | |
| 110 | − | |
| 111 | − buf[len] = '\0'; | |
| 112 | − if (kstrtoul(buf, 0, &mask)) | |
| 113 | − return -EINVAL; | |
| 106 | + ret = kstrtoul_from_user(user_buf, count, 0, &mask); | |
| 107 | + if (ret) | |
| 108 | + return ret; | |
| 114 | 109 | |
| 115 | 110 | common->debug_mask = mask; |
| 116 | 111 | return count; |
| @@ -191,16 +186,11 @@ static ssize_t write_file_ani(struct file *file, · 74 unmodified lines | ||
| 191 | 186 | struct ath_softc *sc = file->private_data; |
| 192 | 187 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); |
| 193 | 188 | unsigned long ani; |
| 194 | − char buf[32]; | |
| 195 | − ssize_t len; | |
| 189 | + ssize_t ret; | |
| 196 | 190 | |
| 197 | − len = min(count, sizeof(buf) - 1); | |
| 198 | − if (copy_from_user(buf, user_buf, len)) | |
| 199 | − return -EFAULT; | |
| 200 | − | |
| 201 | − buf[len] = '\0'; | |
| 202 | − if (kstrtoul(buf, 0, &ani)) | |
| 203 | − return -EINVAL; | |
| 191 | + ret = kstrtoul_from_user(user_buf, count, 0, &ani); | |
| 192 | + if (ret) | |
| 193 | + return ret; | |
| 204 | 194 | |
| 205 | 195 | if (ani > 1) |
| 206 | 196 | return -EINVAL; |
| @@ -248,20 +238,15 @@ static ssize_t write_file_bt_ant_diversity(struct file *file, · 41 unmodified lines | ||
| 248 | 238 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); |
| 249 | 239 | struct ath9k_hw_capabilities *pCap = &sc->sc_ah->caps; |
| 250 | 240 | unsigned long bt_ant_diversity; |
| 251 | − char buf[32]; | |
| 252 | − ssize_t len; | |
| 241 | + ssize_t ret; | |
| 253 | 242 | |
| 254 | − len = min(count, sizeof(buf) - 1); | |
| 255 | − if (copy_from_user(buf, user_buf, len)) | |
| 256 | − return -EFAULT; | |
| 243 | + ret = kstrtoul_from_user(user_buf, count, 0, &bt_ant_diversity); | |
| 244 | + if (ret) | |
| 245 | + return ret; | |
| 257 | 246 | |
| 258 | 247 | if (!(pCap->hw_caps & ATH9K_HW_CAP_BT_ANT_DIV)) |
| 259 | 248 | goto exit; |
| 260 | 249 | |
| 261 | − buf[len] = '\0'; | |
| 262 | − if (kstrtoul(buf, 0, &bt_ant_diversity)) | |
| 263 | − return -EINVAL; | |
| 264 | − | |
| 265 | 250 | common->bt_ant_diversity = !!bt_ant_diversity; |
| 266 | 251 | ath9k_ps_wakeup(sc); |
| 267 | 252 | ath9k_hw_set_bt_ant_diversity(sc->sc_ah, common->bt_ant_diversity); |
| @@ -792,16 +777,11 @@ static ssize_t write_file_reset(struct file *file, · 524 unmodified lines | ||
| 792 | 777 | struct ath_hw *ah = sc->sc_ah; |
| 793 | 778 | struct ath_common *common = ath9k_hw_common(ah); |
| 794 | 779 | unsigned long val; |
| 795 | − char buf[32]; | |
| 796 | − ssize_t len; | |
| 797 | − | |
| 798 | − len = min(count, sizeof(buf) - 1); | |
| 799 | − if (copy_from_user(buf, user_buf, len)) | |
| 800 | − return -EFAULT; | |
| 780 | + ssize_t ret; | |
| 801 | 781 | |
| 802 | − buf[len] = '\0'; | |
| 803 | − if (kstrtoul(buf, 0, &val)) | |
| 804 | − return -EINVAL; | |
| 782 | + ret = kstrtoul_from_user(user_buf, count, 0, &val); | |
| 783 | + if (ret) | |
| 784 | + return ret; | |
| 805 | 785 | |
| 806 | 786 | if (val != 1) |
| 807 | 787 | return -EINVAL; |
| @@ -886,16 +866,11 @@ static ssize_t write_file_regidx(struct file *file, const char __user *user_buf, · 78 unmodified lines | ||
| 886 | 866 | { |
| 887 | 867 | struct ath_softc *sc = file->private_data; |
| 888 | 868 | unsigned long regidx; |
| 889 | − char buf[32]; | |
| 890 | − ssize_t len; | |
| 869 | + ssize_t ret; | |
| 891 | 870 | |
| 892 | − len = min(count, sizeof(buf) - 1); | |
| 893 | − if (copy_from_user(buf, user_buf, len)) | |
| 894 | − return -EFAULT; | |
| 895 | − | |
| 896 | − buf[len] = '\0'; | |
| 897 | − if (kstrtoul(buf, 0, ®idx)) | |
| 898 | − return -EINVAL; | |
| 871 | + ret = kstrtoul_from_user(user_buf, count, 0, ®idx); | |
| 872 | + if (ret) | |
| 873 | + return ret; | |
| 899 | 874 | |
| 900 | 875 | sc->debug.regidx = regidx; |
| 901 | 876 | return count; |
| @@ -931,16 +906,11 @@ static ssize_t write_file_regval(struct file *file, const char __user *user_buf, · 29 unmodified lines | ||
| 931 | 906 | struct ath_softc *sc = file->private_data; |
| 932 | 907 | struct ath_hw *ah = sc->sc_ah; |
| 933 | 908 | unsigned long regval; |
| 934 | − char buf[32]; | |
| 935 | − ssize_t len; | |
| 936 | − | |
| 937 | − len = min(count, sizeof(buf) - 1); | |
| 938 | − if (copy_from_user(buf, user_buf, len)) | |
| 939 | − return -EFAULT; | |
| 909 | + ssize_t ret; | |
| 940 | 910 | |
| 941 | − buf[len] = '\0'; | |
| 942 | − if (kstrtoul(buf, 0, ®val)) | |
| 943 | − return -EINVAL; | |
| 911 | + ret = kstrtoul_from_user(user_buf, count, 0, ®val); | |
| 912 | + if (ret) | |
| 913 | + return ret; | |
| 944 | 914 | |
| 945 | 915 | ath9k_ps_wakeup(sc); |
| 946 | 916 | REG_WRITE_D(ah, sc->debug.regidx, regval); |
| @@ -1128,16 +1098,11 @@ static ssize_t write_file_wow(struct file *file, const char __user *user_buf, · 181 unmodified lines | ||
| 1128 | 1098 | { |
| 1129 | 1099 | struct ath_softc *sc = file->private_data; |
| 1130 | 1100 | unsigned long val; |
| 1131 | − char buf[32]; | |
| 1132 | − ssize_t len; | |
| 1133 | − | |
| 1134 | − len = min(count, sizeof(buf) - 1); | |
| 1135 | − if (copy_from_user(buf, user_buf, len)) | |
| 1136 | − return -EFAULT; | |
| 1101 | + ssize_t ret; | |
| 1137 | 1102 | |
| 1138 | − buf[len] = '\0'; | |
| 1139 | − if (kstrtoul(buf, 0, &val)) | |
| 1140 | − return -EINVAL; | |
| 1103 | + ret = kstrtoul_from_user(user_buf, count, 0, &val); | |
| 1104 | + if (ret) | |
| 1105 | + return ret; | |
| 1141 | 1106 | |
| 1142 | 1107 | if (val != 1) |
| 1143 | 1108 | return -EINVAL; |
| @@ -1191,17 +1156,12 @@ static ssize_t write_file_tpc(struct file *file, const char __user *user_buf, · 47 unmodified lines | ||
| 1191 | 1156 | struct ath_softc *sc = file->private_data; |
| 1192 | 1157 | struct ath_hw *ah = sc->sc_ah; |
| 1193 | 1158 | unsigned long val; |
| 1194 | − char buf[32]; | |
| 1195 | − ssize_t len; | |
| 1159 | + ssize_t ret; | |
| 1196 | 1160 | bool tpc_enabled; |
| 1197 | 1161 | |
| 1198 | − len = min(count, sizeof(buf) - 1); | |
| 1199 | − if (copy_from_user(buf, user_buf, len)) | |
| 1200 | − return -EFAULT; | |
| 1201 | − | |
| 1202 | − buf[len] = '\0'; | |
| 1203 | − if (kstrtoul(buf, 0, &val)) | |
| 1204 | − return -EINVAL; | |
| 1162 | + ret = kstrtoul_from_user(user_buf, count, 0, &val); | |
| 1163 | + if (ret) | |
| 1164 | + return ret; | |
| 1205 | 1165 | |
| 1206 | 1166 | if (val > 1) |
| 1207 | 1167 | return -EINVAL; |
| @@ -1420,7 +1380,7 @@ int ath9k_init_debug(struct ath_hw *ah) · 212 unmodified lines | ||
| 1420 | 1380 | |
| 1421 | 1381 | sc->debug.debugfs_phy = debugfs_create_dir("ath9k", |
| 1422 | 1382 | sc->hw->wiphy->debugfsdir); |
| 1423 | − if (!sc->debug.debugfs_phy) | |
| 1383 | + if (IS_ERR(sc->debug.debugfs_phy)) | |
| 1424 | 1384 | return -ENOMEM; |
| 1425 | 1385 | |
| 1426 | 1386 | #ifdef CONFIG_ATH_DEBUG |
| @@ -99,17 +99,11 @@ static ssize_t write_file_dfs(struct file *file, const char __user *user_buf, · 98 unmodified lines | ||
| 99 | 99 | { |
| 100 | 100 | struct ath_softc *sc = file->private_data; |
| 101 | 101 | unsigned long val; |
| 102 | − char buf[32]; | |
| 103 | − ssize_t len; | |
| 104 | − | |
| 105 | − len = min(count, sizeof(buf) - 1); | |
| 106 | − if (copy_from_user(buf, user_buf, len)) | |
| 107 | − return -EFAULT; | |
| 108 | − | |
| 109 | − buf[len] = '\0'; | |
| 110 | − if (kstrtoul(buf, 0, &val)) | |
| 111 | − return -EINVAL; | |
| 102 | + ssize_t ret; | |
| 112 | 103 | |
| 104 | + ret = kstrtoul_from_user(user_buf, count, 0, &val); | |
| 105 | + if (ret) | |
| 106 | + return ret; | |
| 113 | 107 | if (val == DFS_STATS_RESET_MAGIC) |
| 114 | 108 | memset(&sc->debug.stats.dfs_stats, 0, |
| 115 | 109 | sizeof(sc->debug.stats.dfs_stats)); |
| @@ -572,8 +572,7 @@ static void ath9k_hw_set_ar9287_power_per_rate_table(struct ath_hw *ah, · 571 unmodified lines | ||
| 572 | 572 | } |
| 573 | 573 | |
| 574 | 574 | for (ctlMode = 0; ctlMode < numCtlModes; ctlMode++) { |
| 575 | − bool isHt40CtlMode = | |
| 576 | − (pCtlMode[ctlMode] == CTL_2GHT40) ? true : false; | |
| 575 | + bool isHt40CtlMode = pCtlMode[ctlMode] == CTL_2GHT40; | |
| 577 | 576 | |
| 578 | 577 | if (isHt40CtlMode) |
| 579 | 578 | freq = centers.synth_center; |
| @@ -1432,7 +1432,7 @@ static void ath9k_hif_usb_disconnect(struct usb_interface *interface) · 1431 unmodified lines | ||
| 1432 | 1432 | { |
| 1433 | 1433 | struct usb_device *udev = interface_to_usbdev(interface); |
| 1434 | 1434 | struct hif_device_usb *hif_dev = usb_get_intfdata(interface); |
| 1435 | − bool unplugged = (udev->state == USB_STATE_NOTATTACHED) ? true : false; | |
| 1435 | + bool unplugged = udev->state == USB_STATE_NOTATTACHED; | |
| 1436 | 1436 | |
| 1437 | 1437 | if (!hif_dev) |
| 1438 | 1438 | return; |
| @@ -375,16 +375,11 @@ static ssize_t write_file_debug(struct file *file, const char __user *user_buf, · 374 unmodified lines | ||
| 375 | 375 | struct ath9k_htc_priv *priv = file->private_data; |
| 376 | 376 | struct ath_common *common = ath9k_hw_common(priv->ah); |
| 377 | 377 | unsigned long mask; |
| 378 | − char buf[32]; | |
| 379 | − ssize_t len; | |
| 380 | − | |
| 381 | − len = min(count, sizeof(buf) - 1); | |
| 382 | − if (copy_from_user(buf, user_buf, len)) | |
| 383 | − return -EFAULT; | |
| 378 | + ssize_t ret; | |
| 384 | 379 | |
| 385 | − buf[len] = '\0'; | |
| 386 | − if (kstrtoul(buf, 0, &mask)) | |
| 387 | − return -EINVAL; | |
| 380 | + ret = kstrtoul_from_user(user_buf, count, 0, &mask); | |
| 381 | + if (ret) | |
| 382 | + return ret; | |
| 388 | 383 | |
| 389 | 384 | common->debug_mask = mask; |
| 390 | 385 | return count; |
| @@ -491,7 +486,7 @@ int ath9k_htc_init_debug(struct ath_hw *ah) · 100 unmodified lines | ||
| 491 | 486 | |
| 492 | 487 | priv->debug.debugfs_phy = debugfs_create_dir(KBUILD_MODNAME, |
| 493 | 488 | priv->hw->wiphy->debugfsdir); |
| 494 | − if (!priv->debug.debugfs_phy) | |
| 489 | + if (IS_ERR(priv->debug.debugfs_phy)) | |
| 495 | 490 | return -ENOMEM; |
| 496 | 491 | |
| 497 | 492 | ath9k_cmn_spectral_init_debug(&priv->spec_priv, priv->debug.debugfs_phy); |
| @@ -719,7 +719,7 @@ static int ath9k_htc_tx_aggr_oper(struct ath9k_htc_priv *priv, · 718 unmodified lines | ||
| 719 | 719 | |
| 720 | 720 | aggr.sta_index = ista->index; |
| 721 | 721 | aggr.tidno = tid & 0xf; |
| 722 | − aggr.aggr_enable = (action == IEEE80211_AMPDU_TX_START) ? true : false; | |
| 722 | + aggr.aggr_enable = action == IEEE80211_AMPDU_TX_START; | |
| 723 | 723 | |
| 724 | 724 | WMI_CMD_BUF(WMI_TX_AGGR_ENABLE_CMDID, &aggr); |
| 725 | 725 | if (ret) |
| @@ -1264,7 +1264,6 @@ static void ath9k_htc_configure_filter(struct ieee80211_hw *hw, · 538 unmodified lines | ||
| 1264 | 1264 | u32 rfilt; |
| 1265 | 1265 | |
| 1266 | 1266 | mutex_lock(&priv->mutex); |
| 1267 | − changed_flags &= SUPPORTED_FILTERS; | |
| 1268 | 1267 | *total_flags &= SUPPORTED_FILTERS; |
| 1269 | 1268 | |
| 1270 | 1269 | if (test_bit(ATH_OP_INVALID, &common->op_flags)) { |
| @@ -1571,7 +1571,6 @@ static void ath9k_configure_filter(struct ieee80211_hw *hw, · 1570 unmodified lines | ||
| 1571 | 1571 | struct ath_chanctx *ctx; |
| 1572 | 1572 | u32 rfilt; |
| 1573 | 1573 | |
| 1574 | − changed_flags &= SUPPORTED_FILTERS; | |
| 1575 | 1574 | *total_flags &= SUPPORTED_FILTERS; |
| 1576 | 1575 | |
| 1577 | 1576 | spin_lock_bh(&sc->chan_lock); |
| @@ -172,9 +172,8 @@ static ssize_t write_file_tx99(struct file *file, const char __user *user_buf, · 171 unmodified lines | ||
| 172 | 172 | { |
| 173 | 173 | struct ath_softc *sc = file->private_data; |
| 174 | 174 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); |
| 175 | − char buf[32]; | |
| 176 | 175 | bool start; |
| 177 | − ssize_t len; | |
| 176 | + ssize_t ret; | |
| 178 | 177 | int r; |
| 179 | 178 | |
| 180 | 179 | if (count < 1) |
| @@ -183,14 +182,9 @@ static ssize_t write_file_tx99(struct file *file, const char __user *user_buf, · 2 unmodified lines | ||
| 183 | 182 | if (sc->cur_chan->nvifs > 1) |
| 184 | 183 | return -EOPNOTSUPP; |
| 185 | 184 | |
| 186 | − len = min(count, sizeof(buf) - 1); | |
| 187 | − if (copy_from_user(buf, user_buf, len)) | |
| 188 | − return -EFAULT; | |
| 189 | − | |
| 190 | − buf[len] = '\0'; | |
| 191 | − | |
| 192 | − if (kstrtobool(buf, &start)) | |
| 193 | − return -EINVAL; | |
| 185 | + ret = kstrtobool_from_user(user_buf, count, &start); | |
| 186 | + if (ret) | |
| 187 | + return ret; | |
| 194 | 188 | |
| 195 | 189 | mutex_lock(&sc->mutex); |
| 196 | 190 | |
| @@ -242,10 +242,10 @@ static void ath9k_wmi_ctrl_rx(void *priv, struct sk_buff *skb, · 241 unmodified lines | ||
| 242 | 242 | spin_unlock_irqrestore(&wmi->wmi_lock, flags); |
| 243 | 243 | goto free_skb; |
| 244 | 244 | } |
| 245 | − spin_unlock_irqrestore(&wmi->wmi_lock, flags); | |
| 246 | 245 | |
| 247 | 246 | /* WMI command response */ |
| 248 | 247 | ath9k_wmi_rsp_callback(wmi, skb); |
| 248 | + spin_unlock_irqrestore(&wmi->wmi_lock, flags); | |
| 249 | 249 | |
| 250 | 250 | free_skb: |
| 251 | 251 | kfree_skb(skb); |
| @@ -283,7 +283,8 @@ int ath9k_wmi_connect(struct htc_target *htc, struct wmi *wmi, · 31 unmodified lines | ||
| 283 | 283 | |
| 284 | 284 | static int ath9k_wmi_cmd_issue(struct wmi *wmi, |
| 285 | 285 | struct sk_buff *skb, |
| 286 | − enum wmi_cmd_id cmd, u16 len) | |
| 286 | + enum wmi_cmd_id cmd, u16 len, | |
| 287 | + u8 *rsp_buf, u32 rsp_len) | |
| 287 | 288 | { |
| 288 | 289 | struct wmi_cmd_hdr *hdr; |
| 289 | 290 | unsigned long flags; |
| @@ -293,6 +294,11 @@ static int ath9k_wmi_cmd_issue(struct wmi *wmi, · 3 unmodified lines | ||
| 293 | 294 | hdr->seq_no = cpu_to_be16(++wmi->tx_seq_id); |
| 294 | 295 | |
| 295 | 296 | spin_lock_irqsave(&wmi->wmi_lock, flags); |
| 297 | + | |
| 298 | + /* record the rsp buffer and length */ | |
| 299 | + wmi->cmd_rsp_buf = rsp_buf; | |
| 300 | + wmi->cmd_rsp_len = rsp_len; | |
| 301 | + | |
| 296 | 302 | wmi->last_seq_id = wmi->tx_seq_id; |
| 297 | 303 | spin_unlock_irqrestore(&wmi->wmi_lock, flags); |
| 298 | 304 | |
| @@ -308,8 +314,8 @@ int ath9k_wmi_cmd(struct wmi *wmi, enum wmi_cmd_id cmd_id, · 9 unmodified lines | ||
| 308 | 314 | struct ath_common *common = ath9k_hw_common(ah); |
| 309 | 315 | u16 headroom = sizeof(struct htc_frame_hdr) + |
| 310 | 316 | sizeof(struct wmi_cmd_hdr); |
| 317 | + unsigned long time_left, flags; | |
| 311 | 318 | struct sk_buff *skb; |
| 312 | − unsigned long time_left; | |
| 313 | 319 | int ret = 0; |
| 314 | 320 | |
| 315 | 321 | if (ah->ah_flags & AH_UNPLUGGED) |
| @@ -333,11 +339,7 @@ int ath9k_wmi_cmd(struct wmi *wmi, enum wmi_cmd_id cmd_id, · 17 unmodified lines | ||
| 333 | 339 | goto out; |
| 334 | 340 | } |
| 335 | 341 | |
| 336 | − /* record the rsp buffer and length */ | |
| 337 | − wmi->cmd_rsp_buf = rsp_buf; | |
| 338 | − wmi->cmd_rsp_len = rsp_len; | |
| 339 | − | |
| 340 | − ret = ath9k_wmi_cmd_issue(wmi, skb, cmd_id, cmd_len); | |
| 342 | + ret = ath9k_wmi_cmd_issue(wmi, skb, cmd_id, cmd_len, rsp_buf, rsp_len); | |
| 341 | 343 | if (ret) |
| 342 | 344 | goto out; |
| 343 | 345 | |
| @@ -345,7 +347,9 @@ int ath9k_wmi_cmd(struct wmi *wmi, enum wmi_cmd_id cmd_id, · 1 unmodified line | ||
| 345 | 347 | if (!time_left) { |
| 346 | 348 | ath_dbg(common, WMI, "Timeout waiting for WMI command: %s\n", |
| 347 | 349 | wmi_cmd_to_name(cmd_id)); |
| 350 | + spin_lock_irqsave(&wmi->wmi_lock, flags); | |
| 348 | 351 | wmi->last_seq_id = 0; |
| 352 | + spin_unlock_irqrestore(&wmi->wmi_lock, flags); | |
| 349 | 353 | mutex_unlock(&wmi->op_mutex); |
| 350 | 354 | return -ETIMEDOUT; |
| 351 | 355 | } |
| @@ -104,7 +104,7 @@ bool ath_hw_keysetmac(struct ath_common *common, u16 entry, const u8 *mac) · 103 unmodified lines | ||
| 104 | 104 | * Not setting this bit allows the hardware to use the key |
| 105 | 105 | * for multicast frame decryption. |
| 106 | 106 | */ |
| 107 | − if (mac[0] & 0x01) | |
| 107 | + if (is_multicast_ether_addr(mac)) | |
| 108 | 108 | unicast_flag = 0; |
| 109 | 109 | |
| 110 | 110 | macLo = get_unaligned_le32(mac); |
| @@ -10,7 +10,7 @@ · 9 unmodified lines | ||
| 10 | 10 | * Copyright (c) 2007 Kalle Valo <kalle.valo@iki.fi> |
| 11 | 11 | * Copyright (c) 2010 Sebastian Smolorz <sesmo@gmx.net> |
| 12 | 12 | * |
| 13 | − * This file is part of the Berlios driver for WLAN USB devices based on the | |
| 13 | + * This file is part of the Berlios driver for USB WLAN devices based on the | |
| 14 | 14 | * Atmel AT76C503A/505/505A. |
| 15 | 15 | * |
| 16 | 16 | * Some iw_handler code was taken from airo.c, (C) 1999 Benjamin Reed |
| @@ -143,7 +143,7 @@ static const struct usb_device_id dev_table[] = { · 126 unmodified lines | ||
| 143 | 143 | { USB_DEVICE(0x0cde, 0x0001), USB_DEVICE_DATA(BOARD_503_ISL3861) }, |
| 144 | 144 | /* Dynalink/Askey WLL013 (intersil) */ |
| 145 | 145 | { USB_DEVICE(0x069a, 0x0320), USB_DEVICE_DATA(BOARD_503_ISL3861) }, |
| 146 | − /* EZ connect 11Mpbs Wireless USB Adapter SMC2662W v1 */ | |
| 146 | + /* EZ connect 11Mpbs USB Wireless Adapter SMC2662W v1 */ | |
| 147 | 147 | { USB_DEVICE(0x0d5c, 0xa001), USB_DEVICE_DATA(BOARD_503_ISL3861) }, |
| 148 | 148 | /* BenQ AWL300 */ |
| 149 | 149 | { USB_DEVICE(0x04a5, 0x9000), USB_DEVICE_DATA(BOARD_503_ISL3861) }, |
| @@ -195,7 +195,7 @@ static const struct usb_device_id dev_table[] = { · 45 unmodified lines | ||
| 195 | 195 | { USB_DEVICE(0x04a5, 0x9001), USB_DEVICE_DATA(BOARD_503) }, |
| 196 | 196 | /* 3Com 3CRSHEW696 */ |
| 197 | 197 | { USB_DEVICE(0x0506, 0x0a01), USB_DEVICE_DATA(BOARD_503) }, |
| 198 | − /* Siemens Santis ADSL WLAN USB adapter WLL 013 */ | |
| 198 | + /* Siemens Santis ADSL USB WLAN adapter WLL 013 */ | |
| 199 | 199 | { USB_DEVICE(0x0681, 0x001b), USB_DEVICE_DATA(BOARD_503) }, |
| 200 | 200 | /* Belkin F5D6050, version 2 */ |
| 201 | 201 | { USB_DEVICE(0x050d, 0x0050), USB_DEVICE_DATA(BOARD_503) }, |
| @@ -238,7 +238,7 @@ static const struct usb_device_id dev_table[] = { · 36 unmodified lines | ||
| 238 | 238 | { USB_DEVICE(0x1915, 0x2233), USB_DEVICE_DATA(BOARD_505_2958) }, |
| 239 | 239 | /* Xterasys XN-2122B, IBlitzz BWU613B/BWU613SB */ |
| 240 | 240 | { USB_DEVICE(0x12fd, 0x1001), USB_DEVICE_DATA(BOARD_505_2958) }, |
| 241 | − /* Corega WLAN USB Stick 11 */ | |
| 241 | + /* Corega USB WLAN Stick 11 */ | |
| 242 | 242 | { USB_DEVICE(0x07aa, 0x7613), USB_DEVICE_DATA(BOARD_505_2958) }, |
| 243 | 243 | /* Microstar MSI Box MS6978 */ |
| 244 | 244 | { USB_DEVICE(0x0db0, 0x1020), USB_DEVICE_DATA(BOARD_505_2958) }, |
| @@ -1176,23 +1176,20 @@ static ssize_t debug_level_show(struct device_driver *d, char *buf) · 1175 unmodified lines | ||
| 1176 | 1176 | static ssize_t debug_level_store(struct device_driver *d, const char *buf, |
| 1177 | 1177 | size_t count) |
| 1178 | 1178 | { |
| 1179 | − char *p = (char *)buf; | |
| 1180 | − u32 val; | |
| 1179 | + unsigned long val; | |
| 1181 | 1180 | |
| 1182 | − if (p[1] == 'x' || p[1] == 'X' || p[0] == 'x' || p[0] == 'X') { | |
| 1183 | − p++; | |
| 1184 | − if (p[0] == 'x' || p[0] == 'X') | |
| 1185 | − p++; | |
| 1186 | − val = simple_strtoul(p, &p, 16); | |
| 1187 | − } else | |
| 1188 | − val = simple_strtoul(p, &p, 10); | |
| 1189 | − if (p == buf) | |
| 1181 | + int result = kstrtoul(buf, 0, &val); | |
| 1182 | + | |
| 1183 | + if (result == -EINVAL) | |
| 1190 | 1184 | printk(KERN_INFO DRV_NAME |
| 1191 | 1185 | ": %s is not in hex or decimal form.\n", buf); |
| 1186 | + else if (result == -ERANGE) | |
| 1187 | + printk(KERN_INFO DRV_NAME | |
| 1188 | + ": %s has overflowed.\n", buf); | |
| 1192 | 1189 | else |
| 1193 | 1190 | ipw_debug_level = val; |
| 1194 | 1191 | |
| 1195 | − return strnlen(buf, count); | |
| 1192 | + return count; | |
| 1196 | 1193 | } |
| 1197 | 1194 | static DRIVER_ATTR_RW(debug_level); |
| 1198 | 1195 | |
| @@ -1461,25 +1458,13 @@ static ssize_t scan_age_store(struct device *d, struct device_attribute *attr, · 262 unmodified lines | ||
| 1461 | 1458 | { |
| 1462 | 1459 | struct ipw_priv *priv = dev_get_drvdata(d); |
| 1463 | 1460 | struct net_device *dev = priv->net_dev; |
| 1464 | − char buffer[] = "00000000"; | |
| 1465 | − unsigned long len = | |
| 1466 | − (sizeof(buffer) - 1) > count ? count : sizeof(buffer) - 1; | |
| 1467 | − unsigned long val; | |
| 1468 | − char *p = buffer; | |
| 1469 | 1461 | |
| 1470 | 1462 | IPW_DEBUG_INFO("enter\n"); |
| 1471 | 1463 | |
| 1472 | − strncpy(buffer, buf, len); | |
| 1473 | − buffer[len] = 0; | |
| 1464 | + unsigned long val; | |
| 1465 | + int result = kstrtoul(buf, 0, &val); | |
| 1474 | 1466 | |
| 1475 | − if (p[1] == 'x' || p[1] == 'X' || p[0] == 'x' || p[0] == 'X') { | |
| 1476 | − p++; | |
| 1477 | − if (p[0] == 'x' || p[0] == 'X') | |
| 1478 | − p++; | |
| 1479 | − val = simple_strtoul(p, &p, 16); | |
| 1480 | − } else | |
| 1481 | − val = simple_strtoul(p, &p, 10); | |
| 1482 | − if (p == buffer) { | |
| 1467 | + if (result == -EINVAL || result == -ERANGE) { | |
| 1483 | 1468 | IPW_DEBUG_INFO("%s: user supplied invalid value.\n", dev->name); |
| 1484 | 1469 | } else { |
| 1485 | 1470 | priv->ieee->scan_age = val; |
| @@ -1487,7 +1472,7 @@ static ssize_t scan_age_store(struct device *d, struct device_attribute *attr, · 1 unmodified line | ||
| 1487 | 1472 | } |
| 1488 | 1473 | |
| 1489 | 1474 | IPW_DEBUG_INFO("exit\n"); |
| 1490 | − return len; | |
| 1475 | + return count; | |
| 1491 | 1476 | } |
| 1492 | 1477 | |
| 1493 | 1478 | static DEVICE_ATTR_RW(scan_age); |
| @@ -69,6 +69,11 @@ static const struct dmi_system_id dmi_ppag_approved_list[] = { · 68 unmodified lines | ||
| 69 | 69 | DMI_MATCH(DMI_SYS_VENDOR, "Alienware"), |
| 70 | 70 | }, |
| 71 | 71 | }, |
| 72 | + { .ident = "RAZER", | |
| 73 | + .matches = { | |
| 74 | + DMI_MATCH(DMI_SYS_VENDOR, "Razer"), | |
| 75 | + }, | |
| 76 | + }, | |
| 72 | 77 | {} |
| 73 | 78 | }; |
| 74 | 79 | |
| @@ -1,6 +1,6 @@ | ||
| 1 | 1 | /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ |
| 2 | 2 | /* |
| 3 | − * Copyright (C) 2005-2014, 2018-2022 Intel Corporation | |
| 3 | + * Copyright (C) 2005-2014, 2018-2023 Intel Corporation | |
| 4 | 4 | * Copyright (C) 2013-2015 Intel Mobile Communications GmbH |
| 5 | 5 | * Copyright (C) 2016-2017 Intel Deutschland GmbH |
| 6 | 6 | */ |
| @@ -29,6 +29,11 @@ enum iwl_debug_cmds { · 22 unmodified lines | ||
| 29 | 29 | * &struct iwl_dbg_host_event_cfg_cmd |
| 30 | 30 | */ |
| 31 | 31 | HOST_EVENT_CFG = 0x3, |
| 32 | + /** | |
| 33 | + * @INVALID_WR_PTR_CMD: invalid write pointer, set in the TFD | |
| 34 | + * when it's not in use | |
| 35 | + */ | |
| 36 | + INVALID_WR_PTR_CMD = 0x6, | |
| 32 | 37 | /** |
| 33 | 38 | * @DBGC_SUSPEND_RESUME: |
| 34 | 39 | * DBGC suspend/resume commad. Uses a single dword as data: |
| @@ -377,7 +382,7 @@ struct iwl_buf_alloc_cmd { · 342 unmodified lines | ||
| 377 | 382 | #define DRAM_INFO_SECOND_MAGIC_WORD 0x89ABCDEF |
| 378 | 383 | |
| 379 | 384 | /** |
| 380 | − * struct iwL_dram_info - DRAM fragments allocation struct | |
| 385 | + * struct iwl_dram_info - DRAM fragments allocation struct | |
| 381 | 386 | * |
| 382 | 387 | * Driver will fill in the first 1K(+) of the pointed DRAM fragment |
| 383 | 388 | * |
| @@ -182,8 +182,7 @@ static void iwl_fwrt_dump_lmac_error_log(struct iwl_fw_runtime *fwrt, u8 lmac_nu · 181 unmodified lines | ||
| 182 | 182 | base = fwrt->fw->inst_errlog_ptr; |
| 183 | 183 | } |
| 184 | 184 | |
| 185 | − if ((fwrt->trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_BZ && !base) || | |
| 186 | − (fwrt->trans->trans_cfg->device_family < IWL_DEVICE_FAMILY_BZ && base < 0x400000)) { | |
| 185 | + if (!base) { | |
| 187 | 186 | IWL_ERR(fwrt, |
| 188 | 187 | "Not valid error log pointer 0x%08X for %s uCode\n", |
| 189 | 188 | base, |
| @@ -565,6 +565,8 @@ static inline unsigned int FH_MEM_CBBC_QUEUE(struct iwl_trans *trans, · 564 unmodified lines | ||
| 565 | 565 | #define RX_QUEUE_MASK 255 |
| 566 | 566 | #define RX_QUEUE_SIZE_LOG 8 |
| 567 | 567 | |
| 568 | +#define IWL_DEFAULT_RX_QUEUE 0 | |
| 569 | + | |
| 568 | 570 | /** |
| 569 | 571 | * struct iwl_rb_status - reserve buffer status |
| 570 | 572 | * host memory mapped FH registers |
| @@ -990,6 +990,8 @@ iwl_nvm_fixup_sband_iftd(struct iwl_trans *trans, · 989 unmodified lines | ||
| 990 | 990 | case IWL_CFG_RF_TYPE_GF: |
| 991 | 991 | case IWL_CFG_RF_TYPE_MR: |
| 992 | 992 | case IWL_CFG_RF_TYPE_MS: |
| 993 | + case IWL_CFG_RF_TYPE_FM: | |
| 994 | + case IWL_CFG_RF_TYPE_WH: | |
| 993 | 995 | iftype_data->he_cap.he_cap_elem.phy_cap_info[9] |= |
| 994 | 996 | IEEE80211_HE_PHY_CAP9_TX_1024_QAM_LESS_THAN_242_TONE_RU; |
| 995 | 997 | if (!is_ap) |
| @@ -1,6 +1,6 @@ | ||
| 1 | 1 | /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ |
| 2 | 2 | /* |
| 3 | − * Copyright (C) 2005-2014, 2018-2022 Intel Corporation | |
| 3 | + * Copyright (C) 2005-2014, 2018-2023 Intel Corporation | |
| 4 | 4 | * Copyright (C) 2013-2015 Intel Mobile Communications GmbH |
| 5 | 5 | * Copyright (C) 2016-2017 Intel Deutschland GmbH |
| 6 | 6 | */ |
| @@ -1069,6 +1069,7 @@ struct iwl_trans_txqs { · 1062 unmodified lines | ||
| 1069 | 1069 | * @mbx_addr_1_step: step address data 1 |
| 1070 | 1070 | * @pcie_link_speed: current PCIe link speed (%PCI_EXP_LNKSTA_CLS_*), |
| 1071 | 1071 | * only valid for discrete (not integrated) NICs |
| 1072 | + * @invalid_tx_cmd: invalid TX command buffer | |
| 1072 | 1073 | */ |
| 1073 | 1074 | struct iwl_trans { |
| 1074 | 1075 | bool csme_own; |
| @@ -1133,6 +1134,8 @@ struct iwl_trans { · 58 unmodified lines | ||
| 1133 | 1134 | |
| 1134 | 1135 | u8 pcie_link_speed; |
| 1135 | 1136 | |
| 1137 | + struct iwl_dma_ptr invalid_tx_cmd; | |
| 1138 | + | |
| 1136 | 1139 | /* pointer to trans specific struct */ |
| 1137 | 1140 | /*Ensure that this pointer will always be aligned to sizeof pointer */ |
| 1138 | 1141 | char trans_specific[] __aligned(sizeof(void *)); |
| @@ -1490,7 +1493,7 @@ static inline u32 iwl_trans_read_mem32(struct iwl_trans *trans, u32 addr) · 351 unmodified lines | ||
| 1490 | 1493 | { |
| 1491 | 1494 | u32 value; |
| 1492 | 1495 | |
| 1493 | − if (WARN_ON(iwl_trans_read_mem(trans, addr, &value, 1))) | |
| 1496 | + if (iwl_trans_read_mem(trans, addr, &value, 1)) | |
| 1494 | 1497 | return 0xa5a5a5a5; |
| 1495 | 1498 | |
| 1496 | 1499 | return value; |
| @@ -1,6 +1,6 @@ | ||
| 1 | 1 | // SPDX-License-Identifier: GPL-2.0-only |
| 2 | 2 | /* |
| 3 | − * Copyright (C) 2021-2022 Intel Corporation | |
| 3 | + * Copyright (C) 2021-2023 Intel Corporation | |
| 4 | 4 | */ |
| 5 | 5 | |
| 6 | 6 | #include <linux/etherdevice.h> |
| @@ -774,9 +774,13 @@ static void iwl_mei_set_init_conf(struct iwl_mei *mei) · 767 unmodified lines | ||
| 774 | 774 | iwl_mei_send_sap_msg_payload(mei->cldev, &sar_msg.hdr); |
| 775 | 775 | } |
| 776 | 776 | |
| 777 | − ether_addr_copy(nic_info_msg.mac_address, iwl_mei_cache.mac_address); | |
| 778 | − ether_addr_copy(nic_info_msg.nvm_address, iwl_mei_cache.nvm_address); | |
| 779 | − iwl_mei_send_sap_msg_payload(mei->cldev, &nic_info_msg.hdr); | |
| 777 | + if (is_valid_ether_addr(iwl_mei_cache.mac_address)) { | |
| 778 | + ether_addr_copy(nic_info_msg.mac_address, | |
| 779 | + iwl_mei_cache.mac_address); | |
| 780 | + ether_addr_copy(nic_info_msg.nvm_address, | |
| 781 | + iwl_mei_cache.nvm_address); | |
| 782 | + iwl_mei_send_sap_msg_payload(mei->cldev, &nic_info_msg.hdr); | |
| 783 | + } | |
| 780 | 784 | |
| 781 | 785 | iwl_mei_send_sap_msg_payload(mei->cldev, &rfkill_msg.hdr); |
| 782 | 786 | } |
| @@ -1532,7 +1536,7 @@ void iwl_mei_host_associated(const struct iwl_mei_conn_info *conn_info, · 749 unmodified lines | ||
| 1532 | 1536 | |
| 1533 | 1537 | mei = mei_cldev_get_drvdata(iwl_mei_global_cldev); |
| 1534 | 1538 | |
| 1535 | − if (!mei && !mei->amt_enabled) | |
| 1539 | + if (!mei || !mei->amt_enabled) | |
| 1536 | 1540 | goto out; |
| 1537 | 1541 | |
| 1538 | 1542 | iwl_mei_send_sap_msg_payload(mei->cldev, &msg.hdr); |
| @@ -1561,7 +1565,7 @@ void iwl_mei_host_disassociated(void) · 22 unmodified lines | ||
| 1561 | 1565 | |
| 1562 | 1566 | mei = mei_cldev_get_drvdata(iwl_mei_global_cldev); |
| 1563 | 1567 | |
| 1564 | − if (!mei && !mei->amt_enabled) | |
| 1568 | + if (!mei || !mei->amt_enabled) | |
| 1565 | 1569 | goto out; |
| 1566 | 1570 | |
| 1567 | 1571 | iwl_mei_send_sap_msg_payload(mei->cldev, &msg.hdr); |
| @@ -1597,7 +1601,7 @@ void iwl_mei_set_rfkill_state(bool hw_rfkill, bool sw_rfkill) · 29 unmodified lines | ||
| 1597 | 1601 | |
| 1598 | 1602 | mei = mei_cldev_get_drvdata(iwl_mei_global_cldev); |
| 1599 | 1603 | |
| 1600 | − if (!mei && !mei->amt_enabled) | |
| 1604 | + if (!mei || !mei->amt_enabled) | |
| 1601 | 1605 | goto out; |
| 1602 | 1606 | |
| 1603 | 1607 | iwl_mei_send_sap_msg_payload(mei->cldev, &msg.hdr); |
| @@ -1626,7 +1630,7 @@ void iwl_mei_set_nic_info(const u8 *mac_address, const u8 *nvm_address) · 22 unmodified lines | ||
| 1626 | 1630 | |
| 1627 | 1631 | mei = mei_cldev_get_drvdata(iwl_mei_global_cldev); |
| 1628 | 1632 | |
| 1629 | − if (!mei && !mei->amt_enabled) | |
| 1633 | + if (!mei || !mei->amt_enabled) | |
| 1630 | 1634 | goto out; |
| 1631 | 1635 | |
| 1632 | 1636 | iwl_mei_send_sap_msg_payload(mei->cldev, &msg.hdr); |
| @@ -1654,7 +1658,7 @@ void iwl_mei_set_country_code(u16 mcc) · 21 unmodified lines | ||
| 1654 | 1658 | |
| 1655 | 1659 | mei = mei_cldev_get_drvdata(iwl_mei_global_cldev); |
| 1656 | 1660 | |
| 1657 | − if (!mei && !mei->amt_enabled) | |
| 1661 | + if (!mei || !mei->amt_enabled) | |
| 1658 | 1662 | goto out; |
| 1659 | 1663 | |
| 1660 | 1664 | iwl_mei_send_sap_msg_payload(mei->cldev, &msg.hdr); |
| @@ -1680,7 +1684,7 @@ void iwl_mei_set_power_limit(const __le16 *power_limit) · 19 unmodified lines | ||
| 1680 | 1684 | |
| 1681 | 1685 | mei = mei_cldev_get_drvdata(iwl_mei_global_cldev); |
| 1682 | 1686 | |
| 1683 | − if (!mei && !mei->amt_enabled) | |
| 1687 | + if (!mei || !mei->amt_enabled) | |
| 1684 | 1688 | goto out; |
| 1685 | 1689 | |
| 1686 | 1690 | memcpy(msg.sar_chain_info_table, power_limit, sizeof(msg.sar_chain_info_table)); |
| @@ -1832,7 +1836,9 @@ void iwl_mei_unregister_complete(void) · 145 unmodified lines | ||
| 1832 | 1836 | struct iwl_mei *mei = |
| 1833 | 1837 | mei_cldev_get_drvdata(iwl_mei_global_cldev); |
| 1834 | 1838 | |
| 1835 | − iwl_mei_send_sap_msg(mei->cldev, SAP_MSG_NOTIF_WIFIDR_DOWN); | |
| 1839 | + if (mei->amt_enabled) | |
| 1840 | + iwl_mei_send_sap_msg(mei->cldev, | |
| 1841 | + SAP_MSG_NOTIF_WIFIDR_DOWN); | |
| 1836 | 1842 | mei->got_ownership = false; |
| 1837 | 1843 | } |
| 1838 | 1844 | |
| @@ -2070,33 +2076,29 @@ static void iwl_mei_remove(struct mei_cl_device *cldev) · 231 unmodified lines | ||
| 2070 | 2076 | |
| 2071 | 2077 | mutex_lock(&iwl_mei_mutex); |
| 2072 | 2078 | |
| 2073 | − if (mei->amt_enabled) { | |
| 2074 | − /* | |
| 2075 | − * Tell CSME that we are going down so that it won't access the | |
| 2076 | − * memory anymore, make sure this message goes through immediately. | |
| 2077 | − */ | |
| 2078 | − mei->csa_throttled = false; | |
| 2079 | − iwl_mei_send_sap_msg(mei->cldev, | |
| 2080 | − SAP_MSG_NOTIF_HOST_GOES_DOWN); | |
| 2081 | − | |
| 2082 | − for (i = 0; i < SEND_SAP_MAX_WAIT_ITERATION; i++) { | |
| 2083 | − if (!iwl_mei_host_to_me_data_pending(mei)) | |
| 2084 | − break; | |
| 2079 | + /* Tell CSME that we are going down so that it won't access the | |
| 2080 | + * memory anymore, make sure this message goes through immediately. | |
| 2081 | + */ | |
| 2082 | + mei->csa_throttled = false; | |
| 2083 | + iwl_mei_send_sap_msg(mei->cldev, | |
| 2084 | + SAP_MSG_NOTIF_HOST_GOES_DOWN); | |
| 2085 | 2085 | |
| 2086 | − msleep(20); | |
| 2087 | − } | |
| 2086 | + for (i = 0; i < SEND_SAP_MAX_WAIT_ITERATION; i++) { | |
| 2087 | + if (!iwl_mei_host_to_me_data_pending(mei)) | |
| 2088 | + break; | |
| 2088 | 2089 | |
| 2089 | − /* | |
| 2090 | − * If we couldn't make sure that CSME saw the HOST_GOES_DOWN | |
| 2091 | − * message, it means that it will probably keep reading memory | |
| 2092 | − * that we are going to unmap and free, expect IOMMU error | |
| 2093 | − * messages. | |
| 2094 | − */ | |
| 2095 | − if (i == SEND_SAP_MAX_WAIT_ITERATION) | |
| 2096 | − dev_err(&mei->cldev->dev, | |
| 2097 | − "Couldn't get ACK from CSME on HOST_GOES_DOWN message\n"); | |
| 2090 | + msleep(20); | |
| 2098 | 2091 | } |
| 2099 | 2092 | |
| 2093 | + /* If we couldn't make sure that CSME saw the HOST_GOES_DOWN | |
| 2094 | + * message, it means that it will probably keep reading memory | |
| 2095 | + * that we are going to unmap and free, expect IOMMU error | |
| 2096 | + * messages. | |
| 2097 | + */ | |
| 2098 | + if (i == SEND_SAP_MAX_WAIT_ITERATION) | |
| 2099 | + dev_err(&mei->cldev->dev, | |
| 2100 | + "Couldn't get ACK from CSME on HOST_GOES_DOWN message\n"); | |
| 2101 | + | |
| 2100 | 2102 | mutex_unlock(&iwl_mei_mutex); |
| 2101 | 2103 | |
| 2102 | 2104 | /* |
| @@ -315,8 +315,9 @@ int iwl_mvm_mac_setup_register(struct iwl_mvm *mvm) · 314 unmodified lines | ||
| 315 | 315 | ieee80211_hw_set(hw, STA_MMPDU_TXQ); |
| 316 | 316 | |
| 317 | 317 | /* Set this early since we need to have it for the check below */ |
| 318 | − if (mvm->mld_api_is_used && | |
| 319 | − mvm->trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_BZ) | |
| 318 | + if (mvm->mld_api_is_used && mvm->nvm_data->sku_cap_11be_enable && | |
| 319 | + !iwlwifi_mod_params.disable_11ax && | |
| 320 | + !iwlwifi_mod_params.disable_11be) | |
| 320 | 321 | hw->wiphy->flags |= WIPHY_FLAG_SUPPORTS_MLO; |
| 321 | 322 | |
| 322 | 323 | /* With MLD FW API, it tracks timing by itself, |
| @@ -5604,9 +5605,6 @@ void iwl_mvm_mac_flush(struct ieee80211_hw *hw, struct ieee80211_vif *vif, · 5281 unmodified lines | ||
| 5604 | 5605 | return; |
| 5605 | 5606 | } |
| 5606 | 5607 | |
| 5607 | − if (vif->type != NL80211_IFTYPE_STATION) | |
| 5608 | − return; | |
| 5609 | − | |
| 5610 | 5608 | /* Make sure we're done with the deferred traffic before flushing */ |
| 5611 | 5609 | flush_work(&mvm->add_stream_wk); |
| 5612 | 5610 | |
| @@ -5630,9 +5628,6 @@ void iwl_mvm_mac_flush(struct ieee80211_hw *hw, struct ieee80211_vif *vif, · 17 unmodified lines | ||
| 5630 | 5628 | ap_sta_done = true; |
| 5631 | 5629 | } |
| 5632 | 5630 | |
| 5633 | − /* make sure only TDLS peers or the AP are flushed */ | |
| 5634 | − WARN_ON_ONCE(sta != mvmvif->ap_sta && !sta->tdls); | |
| 5635 | − | |
| 5636 | 5631 | if (drop) { |
| 5637 | 5632 | if (iwl_mvm_flush_sta(mvm, mvmsta, false)) |
| 5638 | 5633 | IWL_ERR(mvm, "flush request fail\n"); |
| @@ -1132,12 +1132,6 @@ static int get_crf_id(struct iwl_trans *iwl_trans) · 1131 unmodified lines | ||
| 1132 | 1132 | else |
| 1133 | 1133 | sd_reg_ver_addr = SD_REG_VER; |
| 1134 | 1134 | |
| 1135 | − if (!iwl_trans_grab_nic_access(iwl_trans)) { | |
| 1136 | − IWL_ERR(iwl_trans, "Failed to grab nic access before reading crf id\n"); | |
| 1137 | − ret = -EIO; | |
| 1138 | − goto out; | |
| 1139 | − } | |
| 1140 | − | |
| 1141 | 1135 | /* Enable access to peripheral registers */ |
| 1142 | 1136 | val = iwl_read_umac_prph_no_grab(iwl_trans, WFPM_CTRL_REG); |
| 1143 | 1137 | val |= ENABLE_WFPM; |
| @@ -1157,9 +1151,6 @@ static int get_crf_id(struct iwl_trans *iwl_trans) · 13 unmodified lines | ||
| 1157 | 1151 | iwl_trans->hw_crf_id, iwl_trans->hw_cnv_id, |
| 1158 | 1152 | iwl_trans->hw_wfpm_id); |
| 1159 | 1153 | |
| 1160 | − iwl_trans_release_nic_access(iwl_trans); | |
| 1161 | − | |
| 1162 | −out: | |
| 1163 | 1154 | return ret; |
| 1164 | 1155 | } |
| 1165 | 1156 | |
| @@ -1351,6 +1342,7 @@ static int iwl_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent) · 185 unmodified lines | ||
| 1351 | 1342 | if (ret) |
| 1352 | 1343 | goto out_free_trans; |
| 1353 | 1344 | if (iwl_trans_grab_nic_access(iwl_trans)) { |
| 1345 | + get_crf_id(iwl_trans); | |
| 1354 | 1346 | /* all good */ |
| 1355 | 1347 | iwl_trans_release_nic_access(iwl_trans); |
| 1356 | 1348 | } else { |
| @@ -1360,7 +1352,6 @@ static int iwl_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent) · 3 unmodified lines | ||
| 1360 | 1352 | } |
| 1361 | 1353 | |
| 1362 | 1354 | iwl_trans->hw_rf_id = iwl_read32(iwl_trans, CSR_HW_RF_ID); |
| 1363 | − get_crf_id(iwl_trans); | |
| 1364 | 1355 | |
| 1365 | 1356 | /* |
| 1366 | 1357 | * The RF_ID is set to zero in blank OTP so read version to |
| @@ -1,6 +1,6 @@ | ||
| 1 | 1 | /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ |
| 2 | 2 | /* |
| 3 | − * Copyright (C) 2003-2015, 2018-2022 Intel Corporation | |
| 3 | + * Copyright (C) 2003-2015, 2018-2023 Intel Corporation | |
| 4 | 4 | * Copyright (C) 2013-2015 Intel Mobile Communications GmbH |
| 5 | 5 | * Copyright (C) 2016-2017 Intel Deutschland GmbH |
| 6 | 6 | */ |
| @@ -315,7 +315,6 @@ enum iwl_pcie_imr_status { · 308 unmodified lines | ||
| 315 | 315 | * @ucode_write_complete: indicates that the ucode has been copied. |
| 316 | 316 | * @ucode_write_waitq: wait queue for uCode load |
| 317 | 317 | * @cmd_queue - command queue number |
| 318 | − * @def_rx_queue - default rx queue number | |
| 319 | 318 | * @rx_buf_size: Rx buffer size |
| 320 | 319 | * @scd_set_active: should the transport configure the SCD for HCMD queue |
| 321 | 320 | * @rx_page_order: page order for receive buffer size |
| @@ -398,7 +397,6 @@ struct iwl_trans_pcie { · 76 unmodified lines | ||
| 398 | 397 | wait_queue_head_t ucode_write_waitq; |
| 399 | 398 | wait_queue_head_t sx_waitq; |
| 400 | 399 | |
| 401 | − u8 def_rx_queue; | |
| 402 | 400 | u8 n_no_reclaim_cmds; |
| 403 | 401 | u8 no_reclaim_cmds[MAX_NO_RECLAIM_CMDS]; |
| 404 | 402 | u16 num_rx_bufs; |
| @@ -1373,7 +1373,7 @@ static void iwl_pcie_rx_handle_rb(struct iwl_trans *trans, · 1372 unmodified lines | ||
| 1373 | 1373 | } |
| 1374 | 1374 | } |
| 1375 | 1375 | |
| 1376 | − if (rxq->id == trans_pcie->def_rx_queue) | |
| 1376 | + if (rxq->id == IWL_DEFAULT_RX_QUEUE) | |
| 1377 | 1377 | iwl_op_mode_rx(trans->op_mode, &rxq->napi, |
| 1378 | 1378 | &rxcb); |
| 1379 | 1379 | else |
| @@ -2018,6 +2018,30 @@ void iwl_trans_pcie_free_pnvm_dram_regions(struct iwl_dram_regions *dram_regions · 2017 unmodified lines | ||
| 2018 | 2018 | memset(desc_dram, 0, sizeof(*desc_dram)); |
| 2019 | 2019 | } |
| 2020 | 2020 | |
| 2021 | +static void iwl_pcie_free_invalid_tx_cmd(struct iwl_trans *trans) | |
| 2022 | +{ | |
| 2023 | + iwl_pcie_free_dma_ptr(trans, &trans->invalid_tx_cmd); | |
| 2024 | +} | |
| 2025 | + | |
| 2026 | +static int iwl_pcie_alloc_invalid_tx_cmd(struct iwl_trans *trans) | |
| 2027 | +{ | |
| 2028 | + struct iwl_cmd_header_wide bad_cmd = { | |
| 2029 | + .cmd = INVALID_WR_PTR_CMD, | |
| 2030 | + .group_id = DEBUG_GROUP, | |
| 2031 | + .sequence = cpu_to_le16(0xffff), | |
| 2032 | + .length = cpu_to_le16(0), | |
| 2033 | + .version = 0, | |
| 2034 | + }; | |
| 2035 | + int ret; | |
| 2036 | + | |
| 2037 | + ret = iwl_pcie_alloc_dma_ptr(trans, &trans->invalid_tx_cmd, | |
| 2038 | + sizeof(bad_cmd)); | |
| 2039 | + if (ret) | |
| 2040 | + return ret; | |
| 2041 | + memcpy(trans->invalid_tx_cmd.addr, &bad_cmd, sizeof(bad_cmd)); | |
| 2042 | + return 0; | |
| 2043 | +} | |
| 2044 | + | |
| 2021 | 2045 | void iwl_trans_pcie_free(struct iwl_trans *trans) |
| 2022 | 2046 | { |
| 2023 | 2047 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
| @@ -2048,6 +2072,8 @@ void iwl_trans_pcie_free(struct iwl_trans *trans) · 24 unmodified lines | ||
| 2048 | 2072 | iwl_pcie_free_ict(trans); |
| 2049 | 2073 | } |
| 2050 | 2074 | |
| 2075 | + iwl_pcie_free_invalid_tx_cmd(trans); | |
| 2076 | + | |
| 2051 | 2077 | iwl_pcie_free_fw_monitor(trans); |
| 2052 | 2078 | |
| 2053 | 2079 | iwl_trans_pcie_free_pnvm_dram_regions(&trans_pcie->pnvm_data, |
| @@ -3617,8 +3643,6 @@ struct iwl_trans *iwl_trans_pcie_alloc(struct pci_dev *pdev, · 1563 unmodified lines | ||
| 3617 | 3643 | PCIE_LINK_STATE_CLKPM); |
| 3618 | 3644 | } |
| 3619 | 3645 | |
| 3620 | − trans_pcie->def_rx_queue = 0; | |
| 3621 | − | |
| 3622 | 3646 | pci_set_master(pdev); |
| 3623 | 3647 | |
| 3624 | 3648 | addr_size = trans->txqs.tfd.addr_size; |
| @@ -3686,6 +3710,9 @@ struct iwl_trans *iwl_trans_pcie_alloc(struct pci_dev *pdev, · 61 unmodified lines | ||
| 3686 | 3710 | |
| 3687 | 3711 | init_waitqueue_head(&trans_pcie->sx_waitq); |
| 3688 | 3712 | |
| 3713 | + ret = iwl_pcie_alloc_invalid_tx_cmd(trans); | |
| 3714 | + if (ret) | |
| 3715 | + goto out_no_pci; | |
| 3689 | 3716 | |
| 3690 | 3717 | if (trans_pcie->msix_enabled) { |
| 3691 | 3718 | ret = iwl_pcie_init_msix_handler(pdev, trans_pcie); |
| @@ -132,22 +132,6 @@ void iwl_pcie_txq_check_wrptrs(struct iwl_trans *trans) · 131 unmodified lines | ||
| 132 | 132 | } |
| 133 | 133 | } |
| 134 | 134 | |
| 135 | −static inline void iwl_pcie_tfd_set_tb(struct iwl_trans *trans, void *tfd, | |
| 136 | − u8 idx, dma_addr_t addr, u16 len) | |
| 137 | −{ | |
| 138 | − struct iwl_tfd *tfd_fh = (void *)tfd; | |
| 139 | − struct iwl_tfd_tb *tb = &tfd_fh->tbs[idx]; | |
| 140 | − | |
| 141 | − u16 hi_n_len = len << 4; | |
| 142 | − | |
| 143 | − put_unaligned_le32(addr, &tb->lo); | |
| 144 | − hi_n_len |= iwl_get_dma_hi_addr(addr); | |
| 145 | − | |
| 146 | − tb->hi_n_len = cpu_to_le16(hi_n_len); | |
| 147 | − | |
| 148 | − tfd_fh->num_tbs = idx + 1; | |
| 149 | −} | |
| 150 | − | |
| 151 | 135 | static int iwl_pcie_txq_build_tfd(struct iwl_trans *trans, struct iwl_txq *txq, |
| 152 | 136 | dma_addr_t addr, u16 len, bool reset) |
| 153 | 137 | { |
| @@ -172,7 +156,7 @@ static int iwl_pcie_txq_build_tfd(struct iwl_trans *trans, struct iwl_txq *txq, · 18 unmodified lines | ||
| 172 | 156 | "Unaligned address = %llx\n", (unsigned long long)addr)) |
| 173 | 157 | return -EINVAL; |
| 174 | 158 | |
| 175 | − iwl_pcie_tfd_set_tb(trans, tfd, num_tbs, addr, len); | |
| 159 | + iwl_pcie_gen1_tfd_set_tb(trans, tfd, num_tbs, addr, len); | |
| 176 | 160 | |
| 177 | 161 | return num_tbs; |
| 178 | 162 | } |
| @@ -1203,7 +1187,11 @@ void iwl_pcie_hcmd_complete(struct iwl_trans *trans, · 1024 unmodified lines | ||
| 1203 | 1187 | group_id = cmd->hdr.group_id; |
| 1204 | 1188 | cmd_id = WIDE_ID(group_id, cmd->hdr.cmd); |
| 1205 | 1189 | |
| 1206 | − iwl_txq_gen1_tfd_unmap(trans, meta, txq, index); | |
| 1190 | + if (trans->trans_cfg->gen2) | |
| 1191 | + iwl_txq_gen2_tfd_unmap(trans, meta, | |
| 1192 | + iwl_txq_get_tfd(trans, txq, index)); | |
| 1193 | + else | |
| 1194 | + iwl_txq_gen1_tfd_unmap(trans, meta, txq, index); | |
| 1207 | 1195 | |
| 1208 | 1196 | /* Input error checking is done when commands are added to queue. */ |
| 1209 | 1197 | if (meta->flags & CMD_WANT_SKB) { |
| @@ -10,6 +10,7 @@ · 9 unmodified lines | ||
| 10 | 10 | #include "fw/api/commands.h" |
| 11 | 11 | #include "fw/api/tx.h" |
| 12 | 12 | #include "fw/api/datapath.h" |
| 13 | +#include "fw/api/debug.h" | |
| 13 | 14 | #include "queue/tx.h" |
| 14 | 15 | #include "iwl-fh.h" |
| 15 | 16 | #include "iwl-scd.h" |
| @@ -84,6 +85,50 @@ static u8 iwl_txq_gen2_get_num_tbs(struct iwl_trans *trans, · 68 unmodified lines | ||
| 84 | 85 | return le16_to_cpu(tfd->num_tbs) & 0x1f; |
| 85 | 86 | } |
| 86 | 87 | |
| 88 | +int iwl_txq_gen2_set_tb(struct iwl_trans *trans, struct iwl_tfh_tfd *tfd, | |
| 89 | + dma_addr_t addr, u16 len) | |
| 90 | +{ | |
| 91 | + int idx = iwl_txq_gen2_get_num_tbs(trans, tfd); | |
| 92 | + struct iwl_tfh_tb *tb; | |
| 93 | + | |
| 94 | + /* Only WARN here so we know about the issue, but we mess up our | |
| 95 | + * unmap path because not every place currently checks for errors | |
| 96 | + * returned from this function - it can only return an error if | |
| 97 | + * there's no more space, and so when we know there is enough we | |
| 98 | + * don't always check ... | |
| 99 | + */ | |
| 100 | + WARN(iwl_txq_crosses_4g_boundary(addr, len), | |
| 101 | + "possible DMA problem with iova:0x%llx, len:%d\n", | |
| 102 | + (unsigned long long)addr, len); | |
| 103 | + | |
| 104 | + if (WARN_ON(idx >= IWL_TFH_NUM_TBS)) | |
| 105 | + return -EINVAL; | |
| 106 | + tb = &tfd->tbs[idx]; | |
| 107 | + | |
| 108 | + /* Each TFD can point to a maximum max_tbs Tx buffers */ | |
| 109 | + if (le16_to_cpu(tfd->num_tbs) >= trans->txqs.tfd.max_tbs) { | |
| 110 | + IWL_ERR(trans, "Error can not send more than %d chunks\n", | |
| 111 | + trans->txqs.tfd.max_tbs); | |
| 112 | + return -EINVAL; | |
| 113 | + } | |
| 114 | + | |
| 115 | + put_unaligned_le64(addr, &tb->addr); | |
| 116 | + tb->tb_len = cpu_to_le16(len); | |
| 117 | + | |
| 118 | + tfd->num_tbs = cpu_to_le16(idx + 1); | |
| 119 | + | |
| 120 | + return idx; | |
| 121 | +} | |
| 122 | + | |
| 123 | +static void iwl_txq_set_tfd_invalid_gen2(struct iwl_trans *trans, | |
| 124 | + struct iwl_tfh_tfd *tfd) | |
| 125 | +{ | |
| 126 | + tfd->num_tbs = 0; | |
| 127 | + | |
| 128 | + iwl_txq_gen2_set_tb(trans, tfd, trans->invalid_tx_cmd.dma, | |
| 129 | + trans->invalid_tx_cmd.size); | |
| 130 | +} | |
| 131 | + | |
| 87 | 132 | void iwl_txq_gen2_tfd_unmap(struct iwl_trans *trans, struct iwl_cmd_meta *meta, |
| 88 | 133 | struct iwl_tfh_tfd *tfd) |
| 89 | 134 | { |
| @@ -111,7 +156,7 @@ void iwl_txq_gen2_tfd_unmap(struct iwl_trans *trans, struct iwl_cmd_meta *meta, · 21 unmodified lines | ||
| 111 | 156 | DMA_TO_DEVICE); |
| 112 | 157 | } |
| 113 | 158 | |
| 114 | − tfd->num_tbs = 0; | |
| 159 | + iwl_txq_set_tfd_invalid_gen2(trans, tfd); | |
| 115 | 160 | } |
| 116 | 161 | |
| 117 | 162 | void iwl_txq_gen2_free_tfd(struct iwl_trans *trans, struct iwl_txq *txq) |
| @@ -142,42 +187,6 @@ void iwl_txq_gen2_free_tfd(struct iwl_trans *trans, struct iwl_txq *txq) · 24 unmodified lines | ||
| 142 | 187 | } |
| 143 | 188 | } |
| 144 | 189 | |
| 145 | −int iwl_txq_gen2_set_tb(struct iwl_trans *trans, struct iwl_tfh_tfd *tfd, | |
| 146 | − dma_addr_t addr, u16 len) | |
| 147 | −{ | |
| 148 | − int idx = iwl_txq_gen2_get_num_tbs(trans, tfd); | |
| 149 | − struct iwl_tfh_tb *tb; | |
| 150 | − | |
| 151 | − /* | |
| 152 | − * Only WARN here so we know about the issue, but we mess up our | |
| 153 | − * unmap path because not every place currently checks for errors | |
| 154 | − * returned from this function - it can only return an error if | |
| 155 | − * there's no more space, and so when we know there is enough we | |
| 156 | − * don't always check ... | |
| 157 | − */ | |
| 158 | − WARN(iwl_txq_crosses_4g_boundary(addr, len), | |
| 159 | − "possible DMA problem with iova:0x%llx, len:%d\n", | |
| 160 | − (unsigned long long)addr, len); | |
| 161 | − | |
| 162 | − if (WARN_ON(idx >= IWL_TFH_NUM_TBS)) | |
| 163 | − return -EINVAL; | |
| 164 | − tb = &tfd->tbs[idx]; | |
| 165 | − | |
| 166 | − /* Each TFD can point to a maximum max_tbs Tx buffers */ | |
| 167 | − if (le16_to_cpu(tfd->num_tbs) >= trans->txqs.tfd.max_tbs) { | |
| 168 | − IWL_ERR(trans, "Error can not send more than %d chunks\n", | |
| 169 | − trans->txqs.tfd.max_tbs); | |
| 170 | − return -EINVAL; | |
| 171 | − } | |
| 172 | − | |
| 173 | − put_unaligned_le64(addr, &tb->addr); | |
| 174 | − tb->tb_len = cpu_to_le16(len); | |
| 175 | − | |
| 176 | − tfd->num_tbs = cpu_to_le16(idx + 1); | |
| 177 | − | |
| 178 | − return idx; | |
| 179 | −} | |
| 180 | − | |
| 181 | 190 | static struct page *get_workaround_page(struct iwl_trans *trans, |
| 182 | 191 | struct sk_buff *skb) |
| 183 | 192 | { |
| @@ -1026,11 +1035,21 @@ static void iwl_txq_stuck_timer(struct timer_list *t) · 842 unmodified lines | ||
| 1026 | 1035 | iwl_force_nmi(trans); |
| 1027 | 1036 | } |
| 1028 | 1037 | |
| 1038 | +static void iwl_txq_set_tfd_invalid_gen1(struct iwl_trans *trans, | |
| 1039 | + struct iwl_tfd *tfd) | |
| 1040 | +{ | |
| 1041 | + tfd->num_tbs = 0; | |
| 1042 | + | |
| 1043 | + iwl_pcie_gen1_tfd_set_tb(trans, tfd, 0, trans->invalid_tx_cmd.dma, | |
| 1044 | + trans->invalid_tx_cmd.size); | |
| 1045 | +} | |
| 1046 | + | |
| 1029 | 1047 | int iwl_txq_alloc(struct iwl_trans *trans, struct iwl_txq *txq, int slots_num, |
| 1030 | 1048 | bool cmd_queue) |
| 1031 | 1049 | { |
| 1032 | − size_t tfd_sz = trans->txqs.tfd.size * | |
| 1033 | − trans->trans_cfg->base_params->max_tfd_queue_size; | |
| 1050 | + size_t num_entries = trans->trans_cfg->gen2 ? | |
| 1051 | + slots_num : trans->trans_cfg->base_params->max_tfd_queue_size; | |
| 1052 | + size_t tfd_sz; | |
| 1034 | 1053 | size_t tb0_buf_sz; |
| 1035 | 1054 | int i; |
| 1036 | 1055 | |
| @@ -1040,8 +1059,7 @@ int iwl_txq_alloc(struct iwl_trans *trans, struct iwl_txq *txq, int slots_num, · 3 unmodified lines | ||
| 1040 | 1059 | if (WARN_ON(txq->entries || txq->tfds)) |
| 1041 | 1060 | return -EINVAL; |
| 1042 | 1061 | |
| 1043 | − if (trans->trans_cfg->gen2) | |
| 1044 | − tfd_sz = trans->txqs.tfd.size * slots_num; | |
| 1062 | + tfd_sz = trans->txqs.tfd.size * num_entries; | |
| 1045 | 1063 | |
| 1046 | 1064 | timer_setup(&txq->stuck_timer, iwl_txq_stuck_timer, 0); |
| 1047 | 1065 | txq->trans = trans; |
| @@ -1081,6 +1099,15 @@ int iwl_txq_alloc(struct iwl_trans *trans, struct iwl_txq *txq, int slots_num, · 33 unmodified lines | ||
| 1081 | 1099 | if (!txq->first_tb_bufs) |
| 1082 | 1100 | goto err_free_tfds; |
| 1083 | 1101 | |
| 1102 | + for (i = 0; i < num_entries; i++) { | |
| 1103 | + void *tfd = iwl_txq_get_tfd(trans, txq, i); | |
| 1104 | + | |
| 1105 | + if (trans->trans_cfg->gen2) | |
| 1106 | + iwl_txq_set_tfd_invalid_gen2(trans, tfd); | |
| 1107 | + else | |
| 1108 | + iwl_txq_set_tfd_invalid_gen1(trans, tfd); | |
| 1109 | + } | |
| 1110 | + | |
| 1084 | 1111 | return 0; |
| 1085 | 1112 | err_free_tfds: |
| 1086 | 1113 | dma_free_coherent(trans->dev, tfd_sz, txq->tfds, txq->dma_addr); |
| @@ -1340,22 +1367,12 @@ error: · 253 unmodified lines | ||
| 1340 | 1367 | } |
| 1341 | 1368 | |
| 1342 | 1369 | static inline dma_addr_t iwl_txq_gen1_tfd_tb_get_addr(struct iwl_trans *trans, |
| 1343 | − void *_tfd, u8 idx) | |
| 1370 | + struct iwl_tfd *tfd, u8 idx) | |
| 1344 | 1371 | { |
| 1345 | − struct iwl_tfd *tfd; | |
| 1346 | − struct iwl_tfd_tb *tb; | |
| 1372 | + struct iwl_tfd_tb *tb = &tfd->tbs[idx]; | |
| 1347 | 1373 | dma_addr_t addr; |
| 1348 | 1374 | dma_addr_t hi_len; |
| 1349 | 1375 | |
| 1350 | − if (trans->trans_cfg->gen2) { | |
| 1351 | − struct iwl_tfh_tfd *tfh_tfd = _tfd; | |
| 1352 | − struct iwl_tfh_tb *tfh_tb = &tfh_tfd->tbs[idx]; | |
| 1353 | − | |
| 1354 | − return (dma_addr_t)(le64_to_cpu(tfh_tb->addr)); | |
| 1355 | − } | |
| 1356 | − | |
| 1357 | − tfd = _tfd; | |
| 1358 | − tb = &tfd->tbs[idx]; | |
| 1359 | 1376 | addr = get_unaligned_le32(&tb->lo); |
| 1360 | 1377 | |
| 1361 | 1378 | if (sizeof(dma_addr_t) <= sizeof(u32)) |
| @@ -1376,7 +1393,7 @@ void iwl_txq_gen1_tfd_unmap(struct iwl_trans *trans, · 14 unmodified lines | ||
| 1376 | 1393 | struct iwl_txq *txq, int index) |
| 1377 | 1394 | { |
| 1378 | 1395 | int i, num_tbs; |
| 1379 | − void *tfd = iwl_txq_get_tfd(trans, txq, index); | |
| 1396 | + struct iwl_tfd *tfd = iwl_txq_get_tfd(trans, txq, index); | |
| 1380 | 1397 | |
| 1381 | 1398 | /* Sanity check on number of chunks */ |
| 1382 | 1399 | num_tbs = iwl_txq_gen1_tfd_get_num_tbs(trans, tfd); |
| @@ -1408,15 +1425,7 @@ void iwl_txq_gen1_tfd_unmap(struct iwl_trans *trans, · 25 unmodified lines | ||
| 1408 | 1425 | |
| 1409 | 1426 | meta->tbs = 0; |
| 1410 | 1427 | |
| 1411 | − if (trans->trans_cfg->gen2) { | |
| 1412 | − struct iwl_tfh_tfd *tfd_fh = (void *)tfd; | |
| 1413 | − | |
| 1414 | − tfd_fh->num_tbs = 0; | |
| 1415 | − } else { | |
| 1416 | − struct iwl_tfd *tfd_fh = (void *)tfd; | |
| 1417 | − | |
| 1418 | − tfd_fh->num_tbs = 0; | |
| 1419 | − } | |
| 1428 | + iwl_txq_set_tfd_invalid_gen1(trans, tfd); | |
| 1420 | 1429 | } |
| 1421 | 1430 | |
| 1422 | 1431 | #define IWL_TX_CRC_SIZE 4 |
| @@ -1520,7 +1529,12 @@ void iwl_txq_free_tfd(struct iwl_trans *trans, struct iwl_txq *txq) · 97 unmodified lines | ||
| 1520 | 1529 | /* We have only q->n_window txq->entries, but we use |
| 1521 | 1530 | * TFD_QUEUE_SIZE_MAX tfds |
| 1522 | 1531 | */ |
| 1523 | − iwl_txq_gen1_tfd_unmap(trans, &txq->entries[idx].meta, txq, rd_ptr); | |
| 1532 | + if (trans->trans_cfg->gen2) | |
| 1533 | + iwl_txq_gen2_tfd_unmap(trans, &txq->entries[idx].meta, | |
| 1534 | + iwl_txq_get_tfd(trans, txq, rd_ptr)); | |
| 1535 | + else | |
| 1536 | + iwl_txq_gen1_tfd_unmap(trans, &txq->entries[idx].meta, | |
| 1537 | + txq, rd_ptr); | |
| 1524 | 1538 | |
| 1525 | 1539 | /* free SKB */ |
| 1526 | 1540 | skb = txq->entries[idx].skb; |
| @@ -131,17 +131,8 @@ struct iwl_tso_hdr_page *get_page_hdr(struct iwl_trans *trans, size_t len, · 130 unmodified lines | ||
| 131 | 131 | struct sk_buff *skb); |
| 132 | 132 | #endif |
| 133 | 133 | static inline u8 iwl_txq_gen1_tfd_get_num_tbs(struct iwl_trans *trans, |
| 134 | − void *_tfd) | |
| 134 | + struct iwl_tfd *tfd) | |
| 135 | 135 | { |
| 136 | − struct iwl_tfd *tfd; | |
| 137 | − | |
| 138 | − if (trans->trans_cfg->gen2) { | |
| 139 | − struct iwl_tfh_tfd *tfh_tfd = _tfd; | |
| 140 | − | |
| 141 | − return le16_to_cpu(tfh_tfd->num_tbs) & 0x1f; | |
| 142 | − } | |
| 143 | − | |
| 144 | − tfd = (struct iwl_tfd *)_tfd; | |
| 145 | 136 | return tfd->num_tbs & 0x1f; |
| 146 | 137 | } |
| 147 | 138 | |
| @@ -164,6 +155,21 @@ static inline u16 iwl_txq_gen1_tfd_tb_get_len(struct iwl_trans *trans, · 16 unmodified lines | ||
| 164 | 155 | return le16_to_cpu(tb->hi_n_len) >> 4; |
| 165 | 156 | } |
| 166 | 157 | |
| 158 | +static inline void iwl_pcie_gen1_tfd_set_tb(struct iwl_trans *trans, | |
| 159 | + struct iwl_tfd *tfd, | |
| 160 | + u8 idx, dma_addr_t addr, u16 len) | |
| 161 | +{ | |
| 162 | + struct iwl_tfd_tb *tb = &tfd->tbs[idx]; | |
| 163 | + u16 hi_n_len = len << 4; | |
| 164 | + | |
| 165 | + put_unaligned_le32(addr, &tb->lo); | |
| 166 | + hi_n_len |= iwl_get_dma_hi_addr(addr); | |
| 167 | + | |
| 168 | + tb->hi_n_len = cpu_to_le16(hi_n_len); | |
| 169 | + | |
| 170 | + tfd->num_tbs = idx + 1; | |
| 171 | +} | |
| 172 | + | |
| 167 | 173 | void iwl_txq_gen1_tfd_unmap(struct iwl_trans *trans, |
| 168 | 174 | struct iwl_cmd_meta *meta, |
| 169 | 175 | struct iwl_txq *txq, int index); |
| @@ -129,18 +129,18 @@ MODULE_FIRMWARE("orinoco_ezusb_fw"); · 128 unmodified lines | ||
| 129 | 129 | |
| 130 | 130 | #define USB_AVAYA8_VENDOR_ID 0x0D98 |
| 131 | 131 | #define USB_AVAYAE_VENDOR_ID 0x0D9E |
| 132 | −#define USB_AVAYA_WIRELESS_ID 0x0300 /* Avaya Wireless USB Card */ | |
| 132 | +#define USB_AVAYA_WIRELESS_ID 0x0300 /* Avaya USB Wireless Card */ | |
| 133 | 133 | |
| 134 | 134 | #define USB_AGERE_VENDOR_ID 0x0D4E /* Agere Systems */ |
| 135 | −#define USB_AGERE_MODEL0801_ID 0x1000 /* Wireless USB Card Model 0801 */ | |
| 136 | −#define USB_AGERE_MODEL0802_ID 0x1001 /* Wireless USB Card Model 0802 */ | |
| 137 | −#define USB_AGERE_REBRANDED_ID 0x047A /* WLAN USB Card */ | |
| 135 | +#define USB_AGERE_MODEL0801_ID 0x1000 /* USB Wireless Card Model 0801 */ | |
| 136 | +#define USB_AGERE_MODEL0802_ID 0x1001 /* USB Wireless Card Model 0802 */ | |
| 137 | +#define USB_AGERE_REBRANDED_ID 0x047A /* USB WLAN Card */ | |
| 138 | 138 | |
| 139 | 139 | #define USB_ELSA_VENDOR_ID 0x05CC |
| 140 | 140 | #define USB_ELSA_AIRLANCER_ID 0x3100 /* ELSA AirLancer USB-11 */ |
| 141 | 141 | |
| 142 | 142 | #define USB_LEGEND_VENDOR_ID 0x0E7C |
| 143 | −#define USB_LEGEND_JOYNET_ID 0x0300 /* Joynet WLAN USB Card */ | |
| 143 | +#define USB_LEGEND_JOYNET_ID 0x0300 /* Joynet USB WLAN Card */ | |
| 144 | 144 | |
| 145 | 145 | #define USB_SAMSUNG_VENDOR_ID 0x04E8 |
| 146 | 146 | #define USB_SAMSUNG_SEW2001U1_ID 0x5002 /* Samsung SEW-2001u Card */ |
| @@ -154,7 +154,7 @@ MODULE_FIRMWARE("orinoco_ezusb_fw"); · 7 unmodified lines | ||
| 154 | 154 | #define USB_FUJITSU_E1100_ID 0x1002 /* connect2AIR WLAN E-1100 USB */ |
| 155 | 155 | |
| 156 | 156 | #define USB_2WIRE_VENDOR_ID 0x1630 |
| 157 | −#define USB_2WIRE_WIRELESS_ID 0xff81 /* 2Wire Wireless USB adapter */ | |
| 157 | +#define USB_2WIRE_WIRELESS_ID 0xff81 /* 2Wire USB Wireless adapter */ | |
| 158 | 158 | |
| 159 | 159 | |
| 160 | 160 | #define EZUSB_REQUEST_FW_TRANS 0xA0 |
| @@ -1,6 +1,6 @@ | ||
| 1 | 1 | // SPDX-License-Identifier: GPL-2.0-or-later |
| 2 | 2 | /* |
| 3 | − * Driver for RNDIS based wireless USB devices. | |
| 3 | + * Driver for RNDIS based USB wireless devices. | |
| 4 | 4 | * |
| 5 | 5 | * Copyright (C) 2007 by Bjorge Dijkstra <bjd@jooz.net> |
| 6 | 6 | * Copyright (C) 2008-2009 by Jussi Kivilinna <jussi.kivilinna@iki.fi> |
| @@ -253,8 +253,11 @@ mwifiex_histogram_read(struct file *file, char __user *ubuf, · 252 unmodified lines | ||
| 253 | 253 | if (!p) |
| 254 | 254 | return -ENOMEM; |
| 255 | 255 | |
| 256 | − if (!priv || !priv->hist_data) | |
| 257 | − return -EFAULT; | |
| 256 | + if (!priv || !priv->hist_data) { | |
| 257 | + ret = -EFAULT; | |
| 258 | + goto free_and_exit; | |
| 259 | + } | |
| 260 | + | |
| 258 | 261 | phist_data = priv->hist_data; |
| 259 | 262 | |
| 260 | 263 | p += sprintf(p, "\n" |
| @@ -309,6 +312,8 @@ mwifiex_histogram_read(struct file *file, char __user *ubuf, · 48 unmodified lines | ||
| 309 | 312 | ret = simple_read_from_buffer(ubuf, count, ppos, (char *)page, |
| 310 | 313 | (unsigned long)p - page); |
| 311 | 314 | |
| 315 | +free_and_exit: | |
| 316 | + free_page(page); | |
| 312 | 317 | return ret; |
| 313 | 318 | } |
| 314 | 319 | |
| @@ -420,7 +425,10 @@ mwifiex_regrdwr_write(struct file *file, · 105 unmodified lines | ||
| 420 | 425 | if (IS_ERR(buf)) |
| 421 | 426 | return PTR_ERR(buf); |
| 422 | 427 | |
| 423 | − sscanf(buf, "%u %x %x", ®_type, ®_offset, ®_value); | |
| 428 | + if (sscanf(buf, "%u %x %x", ®_type, ®_offset, ®_value) != 3) { | |
| 429 | + ret = -EINVAL; | |
| 430 | + goto done; | |
| 431 | + } | |
| 424 | 432 | |
| 425 | 433 | if (reg_type == 0 || reg_offset == 0) { |
| 426 | 434 | ret = -EINVAL; |
| @@ -686,7 +694,10 @@ mwifiex_rdeeprom_write(struct file *file, · 259 unmodified lines | ||
| 686 | 694 | if (IS_ERR(buf)) |
| 687 | 695 | return PTR_ERR(buf); |
| 688 | 696 | |
| 689 | − sscanf(buf, "%d %d", &offset, &bytes); | |
| 697 | + if (sscanf(buf, "%d %d", &offset, &bytes) != 2) { | |
| 698 | + ret = -EINVAL; | |
| 699 | + goto done; | |
| 700 | + } | |
| 690 | 701 | |
| 691 | 702 | if (offset == -1 || bytes == -1) { |
| 692 | 703 | ret = -EINVAL; |
| @@ -180,7 +180,6 @@ struct mwifiex_rxinfo { · 179 unmodified lines | ||
| 180 | 180 | }; |
| 181 | 181 | |
| 182 | 182 | struct mwifiex_txinfo { |
| 183 | − u32 status_code; | |
| 184 | 183 | u8 flags; |
| 185 | 184 | u8 bss_num; |
| 186 | 185 | u8 bss_type; |
| @@ -282,14 +282,12 @@ static void mwifiex_init_adapter(struct mwifiex_adapter *adapter) · 281 unmodified lines | ||
| 282 | 282 | sleep_cfm_buf->action = cpu_to_le16(SLEEP_CONFIRM); |
| 283 | 283 | sleep_cfm_buf->resp_ctrl = cpu_to_le16(RESP_NEEDED); |
| 284 | 284 | |
| 285 | − memset(&adapter->sleep_params, 0, sizeof(adapter->sleep_params)); | |
| 286 | 285 | memset(&adapter->sleep_period, 0, sizeof(adapter->sleep_period)); |
| 287 | 286 | adapter->tx_lock_flag = false; |
| 288 | 287 | adapter->null_pkt_interval = 0; |
| 289 | 288 | adapter->fw_bands = 0; |
| 290 | 289 | adapter->config_bands = 0; |
| 291 | 290 | adapter->adhoc_start_band = 0; |
| 292 | − adapter->scan_channels = NULL; | |
| 293 | 291 | adapter->fw_release_number = 0; |
| 294 | 292 | adapter->fw_cap_info = 0; |
| 295 | 293 | memset(&adapter->upld_buf, 0, sizeof(adapter->upld_buf)); |
| @@ -444,15 +444,6 @@ struct mwifiex_current_bss_params { · 443 unmodified lines | ||
| 444 | 444 | u8 data_rates[MWIFIEX_SUPPORTED_RATES]; |
| 445 | 445 | }; |
| 446 | 446 | |
| 447 | −struct mwifiex_sleep_params { | |
| 448 | − u16 sp_error; | |
| 449 | − u16 sp_offset; | |
| 450 | − u16 sp_stable_time; | |
| 451 | − u8 sp_cal_control; | |
| 452 | − u8 sp_ext_sleep_clk; | |
| 453 | − u16 sp_reserved; | |
| 454 | −}; | |
| 455 | − | |
| 456 | 447 | struct mwifiex_sleep_period { |
| 457 | 448 | u16 period; |
| 458 | 449 | u16 reserved; |
| @@ -681,7 +672,6 @@ struct mwifiex_private { · 222 unmodified lines | ||
| 681 | 672 | struct cfg80211_chan_def dfs_chandef; |
| 682 | 673 | struct workqueue_struct *dfs_cac_workqueue; |
| 683 | 674 | struct delayed_work dfs_cac_work; |
| 684 | − struct timer_list dfs_chan_switch_timer; | |
| 685 | 675 | struct workqueue_struct *dfs_chan_sw_workqueue; |
| 686 | 676 | struct delayed_work dfs_chan_sw_work; |
| 687 | 677 | struct cfg80211_beacon_data beacon_after; |
| @@ -888,8 +878,6 @@ struct mwifiex_adapter { · 200 unmodified lines | ||
| 888 | 878 | struct work_struct main_work; |
| 889 | 879 | struct workqueue_struct *rx_workqueue; |
| 890 | 880 | struct work_struct rx_work; |
| 891 | − struct workqueue_struct *dfs_workqueue; | |
| 892 | − struct work_struct dfs_work; | |
| 893 | 881 | bool rx_work_enabled; |
| 894 | 882 | bool rx_processing; |
| 895 | 883 | bool delay_main_work; |
| @@ -953,9 +941,7 @@ struct mwifiex_adapter { · 57 unmodified lines | ||
| 953 | 941 | u8 fw_bands; |
| 954 | 942 | u8 adhoc_start_band; |
| 955 | 943 | u8 config_bands; |
| 956 | − struct mwifiex_chan_scan_param_set *scan_channels; | |
| 957 | 944 | u8 tx_lock_flag; |
| 958 | − struct mwifiex_sleep_params sleep_params; | |
| 959 | 945 | struct mwifiex_sleep_period sleep_period; |
| 960 | 946 | u16 ps_mode; |
| 961 | 947 | u32 ps_state; |
| @@ -1155,8 +1141,10 @@ int mwifiex_process_uap_event(struct mwifiex_private *); · 193 unmodified lines | ||
| 1155 | 1141 | void mwifiex_delete_all_station_list(struct mwifiex_private *priv); |
| 1156 | 1142 | void mwifiex_wmm_del_peer_ra_list(struct mwifiex_private *priv, |
| 1157 | 1143 | const u8 *ra_addr); |
| 1158 | −void *mwifiex_process_sta_txpd(struct mwifiex_private *, struct sk_buff *skb); | |
| 1159 | −void *mwifiex_process_uap_txpd(struct mwifiex_private *, struct sk_buff *skb); | |
| 1144 | +void mwifiex_process_sta_txpd(struct mwifiex_private *priv, | |
| 1145 | + struct sk_buff *skb); | |
| 1146 | +void mwifiex_process_uap_txpd(struct mwifiex_private *priv, | |
| 1147 | + struct sk_buff *skb); | |
| 1160 | 1148 | int mwifiex_sta_init_cmd(struct mwifiex_private *, u8 first_sta, bool init); |
| 1161 | 1149 | int mwifiex_cmd_802_11_scan(struct host_cmd_ds_command *cmd, |
| 1162 | 1150 | struct mwifiex_scan_cmd_config *scan_cfg); |
| @@ -612,7 +612,6 @@ mwifiex_scan_channel_list(struct mwifiex_private *priv, · 611 unmodified lines | ||
| 612 | 612 | struct mwifiex_adapter *adapter = priv->adapter; |
| 613 | 613 | int ret = 0; |
| 614 | 614 | struct mwifiex_chan_scan_param_set *tmp_chan_list; |
| 615 | − struct mwifiex_chan_scan_param_set *start_chan; | |
| 616 | 615 | u32 tlv_idx, rates_size, cmd_no; |
| 617 | 616 | u32 total_scan_time; |
| 618 | 617 | u32 done_early; |
| @@ -643,7 +642,6 @@ mwifiex_scan_channel_list(struct mwifiex_private *priv, · 24 unmodified lines | ||
| 643 | 642 | total_scan_time = 0; |
| 644 | 643 | radio_type = 0; |
| 645 | 644 | chan_tlv_out->header.len = 0; |
| 646 | − start_chan = tmp_chan_list; | |
| 647 | 645 | done_early = false; |
| 648 | 646 | |
| 649 | 647 | /* |
| @@ -750,8 +748,6 @@ mwifiex_scan_channel_list(struct mwifiex_private *priv, · 100 unmodified lines | ||
| 750 | 748 | rates_size = mwifiex_append_rate_tlv(priv, scan_cfg_out, |
| 751 | 749 | radio_type); |
| 752 | 750 | |
| 753 | − priv->adapter->scan_channels = start_chan; | |
| 754 | − | |
| 755 | 751 | /* Send the scan command to the firmware with the specified |
| 756 | 752 | cfg */ |
| 757 | 753 | if (priv->adapter->ext_scan) |
| @@ -828,7 +824,6 @@ mwifiex_config_scan(struct mwifiex_private *priv, · 70 unmodified lines | ||
| 828 | 824 | u8 ssid_filter; |
| 829 | 825 | struct mwifiex_ie_types_htcap *ht_cap; |
| 830 | 826 | struct mwifiex_ie_types_bss_mode *bss_mode; |
| 831 | − const u8 zero_mac[6] = {0, 0, 0, 0, 0, 0}; | |
| 832 | 827 | |
| 833 | 828 | /* The tlv_buf_len is calculated for each scan command. The TLVs added |
| 834 | 829 | in this routine will be preserved since the routine that sends the |
| @@ -966,7 +961,7 @@ mwifiex_config_scan(struct mwifiex_private *priv, · 131 unmodified lines | ||
| 966 | 961 | sizeof(struct mwifiex_ie_types_scan_chan_gap); |
| 967 | 962 | } |
| 968 | 963 | |
| 969 | − if (!ether_addr_equal(user_scan_in->random_mac, zero_mac)) { | |
| 964 | + if (!is_zero_ether_addr(user_scan_in->random_mac)) { | |
| 970 | 965 | random_mac_tlv = (void *)tlv_pos; |
| 971 | 966 | random_mac_tlv->header.type = |
| 972 | 967 | cpu_to_le16(TLV_TYPE_RANDOM_MAC); |
| @@ -1083,17 +1083,17 @@ cont: · 1082 unmodified lines | ||
| 1083 | 1083 | "info: SDIO FUNC1 IO port: %#x\n", adapter->ioport); |
| 1084 | 1084 | |
| 1085 | 1085 | /* Set Host interrupt reset to read to clear */ |
| 1086 | − if (!mwifiex_read_reg(adapter, card->reg->host_int_rsr_reg, ®)) | |
| 1087 | − mwifiex_write_reg(adapter, card->reg->host_int_rsr_reg, | |
| 1088 | − reg | card->reg->sdio_int_mask); | |
| 1089 | − else | |
| 1086 | + if (mwifiex_read_reg(adapter, card->reg->host_int_rsr_reg, ®)) | |
| 1087 | + return -1; | |
| 1088 | + if (mwifiex_write_reg(adapter, card->reg->host_int_rsr_reg, | |
| 1089 | + reg | card->reg->sdio_int_mask)) | |
| 1090 | 1090 | return -1; |
| 1091 | 1091 | |
| 1092 | 1092 | /* Dnld/Upld ready set to auto reset */ |
| 1093 | − if (!mwifiex_read_reg(adapter, card->reg->card_misc_cfg_reg, ®)) | |
| 1094 | − mwifiex_write_reg(adapter, card->reg->card_misc_cfg_reg, | |
| 1095 | − reg | AUTO_RE_ENABLE_INT); | |
| 1096 | − else | |
| 1093 | + if (mwifiex_read_reg(adapter, card->reg->card_misc_cfg_reg, ®)) | |
| 1094 | + return -1; | |
| 1095 | + if (mwifiex_write_reg(adapter, card->reg->card_misc_cfg_reg, | |
| 1096 | + reg | AUTO_RE_ENABLE_INT)) | |
| 1097 | 1097 | return -1; |
| 1098 | 1098 | |
| 1099 | 1099 | return 0; |
| @@ -1556,7 +1556,7 @@ done: · 456 unmodified lines | ||
| 1556 | 1556 | } |
| 1557 | 1557 | |
| 1558 | 1558 | /* |
| 1559 | − * This function decode sdio aggreation pkt. | |
| 1559 | + * This function decodes sdio aggregation pkt. | |
| 1560 | 1560 | * |
| 1561 | 1561 | * Based on the data block size and pkt_len, |
| 1562 | 1562 | * skb data will be decoded to few packets. |
| @@ -2266,7 +2266,7 @@ static int mwifiex_host_to_card_mp_aggr(struct mwifiex_adapter *adapter, · 703 unmodified lines | ||
| 2266 | 2266 | ret = mwifiex_write_data_to_card(adapter, card->mpa_tx.buf, |
| 2267 | 2267 | card->mpa_tx.buf_len, mport); |
| 2268 | 2268 | |
| 2269 | − /* Save the last multi port tx aggreagation info to debug log */ | |
| 2269 | + /* Save the last multi port tx aggregation info to debug log. */ | |
| 2270 | 2270 | index = adapter->dbg.last_sdio_mp_index; |
| 2271 | 2271 | index = (index + 1) % MWIFIEX_DBG_SDIO_MP_NUM; |
| 2272 | 2272 | adapter->dbg.last_sdio_mp_index = index; |
| @@ -2525,7 +2525,8 @@ static int mwifiex_init_sdio(struct mwifiex_adapter *adapter) · 252 unmodified lines | ||
| 2525 | 2525 | mwifiex_read_reg(adapter, card->reg->host_int_status_reg, &sdio_ireg); |
| 2526 | 2526 | |
| 2527 | 2527 | /* Get SDIO ioport */ |
| 2528 | − mwifiex_init_sdio_ioport(adapter); | |
| 2528 | + if (mwifiex_init_sdio_ioport(adapter)) | |
| 2529 | + return -EIO; | |
| 2529 | 2530 | |
| 2530 | 2531 | /* Initialize SDIO variables in card */ |
| 2531 | 2532 | card->mp_rd_bitmap = 0; |
| @@ -3141,7 +3142,8 @@ static void mwifiex_sdio_up_dev(struct mwifiex_adapter *adapter) · 609 unmodified lines | ||
| 3141 | 3142 | */ |
| 3142 | 3143 | mwifiex_read_reg(adapter, card->reg->host_int_status_reg, &sdio_ireg); |
| 3143 | 3144 | |
| 3144 | − mwifiex_init_sdio_ioport(adapter); | |
| 3145 | + if (mwifiex_init_sdio_ioport(adapter)) | |
| 3146 | + dev_err(&card->func->dev, "error enabling SDIO port\n"); | |
| 3145 | 3147 | } |
| 3146 | 3148 | |
| 3147 | 3149 | static struct mwifiex_if_ops sdio_ops = { |
| @@ -92,6 +92,7 @@ int mwifiex_process_rx_packet(struct mwifiex_private *priv, · 91 unmodified lines | ||
| 92 | 92 | skb->len, rx_pkt_off); |
| 93 | 93 | priv->stats.rx_dropped++; |
| 94 | 94 | dev_kfree_skb_any(skb); |
| 95 | + return -1; | |
| 95 | 96 | } |
| 96 | 97 | |
| 97 | 98 | if ((!memcmp(&rx_pkt_hdr->rfc1042_hdr, bridge_tunnel_header, |
| @@ -29,8 +29,8 @@ · 28 unmodified lines | ||
| 29 | 29 | * - Priority specific Tx control |
| 30 | 30 | * - Flags |
| 31 | 31 | */ |
| 32 | −void *mwifiex_process_sta_txpd(struct mwifiex_private *priv, | |
| 33 | − struct sk_buff *skb) | |
| 32 | +void mwifiex_process_sta_txpd(struct mwifiex_private *priv, | |
| 33 | + struct sk_buff *skb) | |
| 34 | 34 | { |
| 35 | 35 | struct mwifiex_adapter *adapter = priv->adapter; |
| 36 | 36 | struct txpd *local_tx_pd; |
| @@ -39,15 +39,6 @@ void *mwifiex_process_sta_txpd(struct mwifiex_private *priv, · 2 unmodified lines | ||
| 39 | 39 | u16 pkt_type, pkt_offset; |
| 40 | 40 | int hroom = adapter->intf_hdr_len; |
| 41 | 41 | |
| 42 | − if (!skb->len) { | |
| 43 | − mwifiex_dbg(adapter, ERROR, | |
| 44 | − "Tx: bad packet length: %d\n", skb->len); | |
| 45 | − tx_info->status_code = -1; | |
| 46 | − return skb->data; | |
| 47 | − } | |
| 48 | − | |
| 49 | − BUG_ON(skb_headroom(skb) < MWIFIEX_MIN_DATA_HEADER_LEN); | |
| 50 | − | |
| 51 | 42 | pkt_type = mwifiex_is_skb_mgmt_frame(skb) ? PKT_TYPE_MGMT : 0; |
| 52 | 43 | |
| 53 | 44 | pad = ((uintptr_t)skb->data - (sizeof(*local_tx_pd) + hroom)) & |
| @@ -109,8 +100,6 @@ void *mwifiex_process_sta_txpd(struct mwifiex_private *priv, · 55 unmodified lines | ||
| 109 | 100 | if (!local_tx_pd->tx_control) |
| 110 | 101 | /* TxCtrl set by user or default */ |
| 111 | 102 | local_tx_pd->tx_control = cpu_to_le32(priv->pkt_tx_ctrl); |
| 112 | − | |
| 113 | − return skb->data; | |
| 114 | 103 | } |
| 115 | 104 | |
| 116 | 105 | /* |
| @@ -72,13 +72,18 @@ EXPORT_SYMBOL_GPL(mwifiex_handle_rx_packet); · 71 unmodified lines | ||
| 72 | 72 | int mwifiex_process_tx(struct mwifiex_private *priv, struct sk_buff *skb, |
| 73 | 73 | struct mwifiex_tx_param *tx_param) |
| 74 | 74 | { |
| 75 | − int hroom, ret = -1; | |
| 75 | + int hroom, ret; | |
| 76 | 76 | struct mwifiex_adapter *adapter = priv->adapter; |
| 77 | − u8 *head_ptr; | |
| 78 | 77 | struct txpd *local_tx_pd = NULL; |
| 79 | 78 | struct mwifiex_sta_node *dest_node; |
| 80 | 79 | struct ethhdr *hdr = (void *)skb->data; |
| 81 | 80 | |
| 81 | + if (unlikely(!skb->len || | |
| 82 | + skb_headroom(skb) < MWIFIEX_MIN_DATA_HEADER_LEN)) { | |
| 83 | + ret = -EINVAL; | |
| 84 | + goto out; | |
| 85 | + } | |
| 86 | + | |
| 82 | 87 | hroom = adapter->intf_hdr_len; |
| 83 | 88 | |
| 84 | 89 | if (priv->bss_role == MWIFIEX_BSS_ROLE_UAP) { |
| @@ -88,33 +93,31 @@ int mwifiex_process_tx(struct mwifiex_private *priv, struct sk_buff *skb, · 3 unmodified lines | ||
| 88 | 93 | dest_node->stats.tx_packets++; |
| 89 | 94 | } |
| 90 | 95 | |
| 91 | − head_ptr = mwifiex_process_uap_txpd(priv, skb); | |
| 96 | + mwifiex_process_uap_txpd(priv, skb); | |
| 92 | 97 | } else { |
| 93 | − head_ptr = mwifiex_process_sta_txpd(priv, skb); | |
| 98 | + mwifiex_process_sta_txpd(priv, skb); | |
| 94 | 99 | } |
| 95 | 100 | |
| 96 | − if ((adapter->data_sent || adapter->tx_lock_flag) && head_ptr) { | |
| 101 | + if (adapter->data_sent || adapter->tx_lock_flag) { | |
| 97 | 102 | skb_queue_tail(&adapter->tx_data_q, skb); |
| 98 | 103 | atomic_inc(&adapter->tx_queued); |
| 99 | 104 | return 0; |
| 100 | 105 | } |
| 101 | 106 | |
| 102 | − if (head_ptr) { | |
| 103 | − if (GET_BSS_ROLE(priv) == MWIFIEX_BSS_ROLE_STA) | |
| 104 | − local_tx_pd = (struct txpd *)(head_ptr + hroom); | |
| 105 | − if (adapter->iface_type == MWIFIEX_USB) { | |
| 106 | − ret = adapter->if_ops.host_to_card(adapter, | |
| 107 | − priv->usb_port, | |
| 108 | − skb, tx_param); | |
| 109 | − } else { | |
| 110 | − ret = adapter->if_ops.host_to_card(adapter, | |
| 111 | − MWIFIEX_TYPE_DATA, | |
| 112 | − skb, tx_param); | |
| 113 | − } | |
| 107 | + if (GET_BSS_ROLE(priv) == MWIFIEX_BSS_ROLE_STA) | |
| 108 | + local_tx_pd = (struct txpd *)(skb->data + hroom); | |
| 109 | + if (adapter->iface_type == MWIFIEX_USB) { | |
| 110 | + ret = adapter->if_ops.host_to_card(adapter, | |
| 111 | + priv->usb_port, | |
| 112 | + skb, tx_param); | |
| 113 | + } else { | |
| 114 | + ret = adapter->if_ops.host_to_card(adapter, | |
| 115 | + MWIFIEX_TYPE_DATA, | |
| 116 | + skb, tx_param); | |
| 114 | 117 | } |
| 115 | 118 | mwifiex_dbg_dump(adapter, DAT_D, "tx pkt:", skb->data, |
| 116 | 119 | min_t(size_t, skb->len, DEBUG_DUMP_DATA_MAX_LEN)); |
| 117 | − | |
| 120 | +out: | |
| 118 | 121 | switch (ret) { |
| 119 | 122 | case -ENOSR: |
| 120 | 123 | mwifiex_dbg(adapter, DATA, "data: -ENOSR is returned\n"); |
| @@ -137,6 +140,11 @@ int mwifiex_process_tx(struct mwifiex_private *priv, struct sk_buff *skb, · 16 unmodified lines | ||
| 137 | 140 | break; |
| 138 | 141 | case -EINPROGRESS: |
| 139 | 142 | break; |
| 143 | + case -EINVAL: | |
| 144 | + mwifiex_dbg(adapter, ERROR, | |
| 145 | + "malformed skb (length: %u, headroom: %u)\n", | |
| 146 | + skb->len, skb_headroom(skb)); | |
| 147 | + fallthrough; | |
| 140 | 148 | case 0: |
| 141 | 149 | mwifiex_write_data_complete(adapter, skb, 0, ret); |
| 142 | 150 | break; |
| @@ -110,6 +110,7 @@ static void mwifiex_uap_queue_bridged_pkt(struct mwifiex_private *priv, · 109 unmodified lines | ||
| 110 | 110 | skb->len, le16_to_cpu(uap_rx_pd->rx_pkt_offset)); |
| 111 | 111 | priv->stats.rx_dropped++; |
| 112 | 112 | dev_kfree_skb_any(skb); |
| 113 | + return; | |
| 113 | 114 | } |
| 114 | 115 | |
| 115 | 116 | if ((!memcmp(&rx_pkt_hdr->rfc1042_hdr, bridge_tunnel_header, |
| @@ -252,7 +253,15 @@ int mwifiex_handle_uap_rx_forward(struct mwifiex_private *priv, · 136 unmodified lines | ||
| 252 | 253 | |
| 253 | 254 | if (is_multicast_ether_addr(ra)) { |
| 254 | 255 | skb_uap = skb_copy(skb, GFP_ATOMIC); |
| 255 | − mwifiex_uap_queue_bridged_pkt(priv, skb_uap); | |
| 256 | + if (likely(skb_uap)) { | |
| 257 | + mwifiex_uap_queue_bridged_pkt(priv, skb_uap); | |
| 258 | + } else { | |
| 259 | + mwifiex_dbg(adapter, ERROR, | |
| 260 | + "failed to copy skb for uAP\n"); | |
| 261 | + priv->stats.rx_dropped++; | |
| 262 | + dev_kfree_skb_any(skb); | |
| 263 | + return -1; | |
| 264 | + } | |
| 256 | 265 | } else { |
| 257 | 266 | if (mwifiex_get_sta_entry(priv, ra)) { |
| 258 | 267 | /* Requeue Intra-BSS packet */ |
| @@ -461,8 +470,8 @@ int mwifiex_process_uap_rx_packet(struct mwifiex_private *priv, · 202 unmodified lines | ||
| 461 | 470 | * - Priority specific Tx control |
| 462 | 471 | * - Flags |
| 463 | 472 | */ |
| 464 | −void *mwifiex_process_uap_txpd(struct mwifiex_private *priv, | |
| 465 | − struct sk_buff *skb) | |
| 473 | +void mwifiex_process_uap_txpd(struct mwifiex_private *priv, | |
| 474 | + struct sk_buff *skb) | |
| 466 | 475 | { |
| 467 | 476 | struct mwifiex_adapter *adapter = priv->adapter; |
| 468 | 477 | struct uap_txpd *txpd; |
| @@ -471,15 +480,6 @@ void *mwifiex_process_uap_txpd(struct mwifiex_private *priv, · 2 unmodified lines | ||
| 471 | 480 | u16 pkt_type, pkt_offset; |
| 472 | 481 | int hroom = adapter->intf_hdr_len; |
| 473 | 482 | |
| 474 | − if (!skb->len) { | |
| 475 | − mwifiex_dbg(adapter, ERROR, | |
| 476 | − "Tx: bad packet length: %d\n", skb->len); | |
| 477 | − tx_info->status_code = -1; | |
| 478 | − return skb->data; | |
| 479 | − } | |
| 480 | − | |
| 481 | − BUG_ON(skb_headroom(skb) < MWIFIEX_MIN_DATA_HEADER_LEN); | |
| 482 | − | |
| 483 | 483 | pkt_type = mwifiex_is_skb_mgmt_frame(skb) ? PKT_TYPE_MGMT : 0; |
| 484 | 484 | |
| 485 | 485 | pad = ((uintptr_t)skb->data - (sizeof(*txpd) + hroom)) & |
| @@ -527,6 +527,4 @@ void *mwifiex_process_uap_txpd(struct mwifiex_private *priv, · 41 unmodified lines | ||
| 527 | 527 | if (!txpd->tx_control) |
| 528 | 528 | /* TxCtrl set by user or default */ |
| 529 | 529 | txpd->tx_control = cpu_to_le32(priv->pkt_tx_ctrl); |
| 530 | − | |
| 531 | − return skb->data; | |
| 532 | 530 | } |
| @@ -5,7 +5,7 @@ config MT7603E · 4 unmodified lines | ||
| 5 | 5 | depends on MAC80211 |
| 6 | 6 | depends on PCI |
| 7 | 7 | help |
| 8 | − This adds support for MT7603E wireless PCIe devices and the WLAN core | |
| 8 | + This adds support for MT7603E PCIe wireless devices and the WLAN core | |
| 9 | 9 | on MT7628/MT7688 SoC devices. This family supports IEEE 802.11n 2x2 |
| 10 | 10 | to 300Mbps PHY rate |
| 11 | 11 | |
| @@ -11,7 +11,7 @@ config MT7615E · 10 unmodified lines | ||
| 11 | 11 | depends on MAC80211 |
| 12 | 12 | depends on PCI |
| 13 | 13 | help |
| 14 | − This adds support for MT7615-based wireless PCIe devices, | |
| 14 | + This adds support for MT7615-based PCIe wireless devices, | |
| 15 | 15 | which support concurrent dual-band operation at both 5GHz |
| 16 | 16 | and 2.4GHz, IEEE 802.11ac 4x4:4SS 1733Mbps PHY rate, wave2 |
| 17 | 17 | MU-MIMO up to 4 users/group and 160MHz channels. |
| @@ -10,7 +10,7 @@ config MT76x0U · 9 unmodified lines | ||
| 10 | 10 | depends on MAC80211 |
| 11 | 11 | depends on USB |
| 12 | 12 | help |
| 13 | − This adds support for MT7610U-based wireless USB 2.0 dongles, | |
| 13 | + This adds support for MT7610U-based USB 2.0 wireless dongles, | |
| 14 | 14 | which comply with IEEE 802.11ac standards and support 1x1 |
| 15 | 15 | 433Mbps PHY rate. |
| 16 | 16 | |
| @@ -22,7 +22,7 @@ config MT76x0E · 5 unmodified lines | ||
| 22 | 22 | depends on MAC80211 |
| 23 | 23 | depends on PCI |
| 24 | 24 | help |
| 25 | − This adds support for MT7610/MT7630-based wireless PCIe devices, | |
| 25 | + This adds support for MT7610/MT7630-based PCIe wireless devices, | |
| 26 | 26 | which comply with IEEE 802.11ac standards and support 1x1 |
| 27 | 27 | 433Mbps PHY rate. |
| 28 | 28 | |
| @@ -9,7 +9,7 @@ config MT76x2E · 8 unmodified lines | ||
| 9 | 9 | depends on MAC80211 |
| 10 | 10 | depends on PCI |
| 11 | 11 | help |
| 12 | − This adds support for MT7612/MT7602/MT7662-based wireless PCIe | |
| 12 | + This adds support for MT7612/MT7602/MT7662-based PCIe wireless | |
| 13 | 13 | devices, which comply with IEEE 802.11ac standards and support |
| 14 | 14 | 2SS to 866Mbit/s PHY rate. |
| 15 | 15 | |
| @@ -22,7 +22,7 @@ config MT76x2U · 6 unmodified lines | ||
| 22 | 22 | depends on MAC80211 |
| 23 | 23 | depends on USB |
| 24 | 24 | help |
| 25 | − This adds support for MT7612U-based wireless USB 3.0 dongles, | |
| 25 | + This adds support for MT7612U-based USB 3.0 wireless dongles, | |
| 26 | 26 | which comply with IEEE 802.11ac standards and support 2SS to |
| 27 | 27 | 866Mbit/s PHY rate. |
| 28 | 28 | |
| @@ -7,7 +7,7 @@ config MT7915E · 6 unmodified lines | ||
| 7 | 7 | depends on PCI |
| 8 | 8 | select RELAY |
| 9 | 9 | help |
| 10 | − This adds support for MT7915-based wireless PCIe devices, | |
| 10 | + This adds support for MT7915-based PCIe wireless devices, | |
| 11 | 11 | which support concurrent dual-band operation at both 5GHz |
| 12 | 12 | and 2.4GHz IEEE 802.11ax 4x4:4SS 1024-QAM, 160MHz channels, |
| 13 | 13 | OFDMA, spatial reuse and dual carrier modulation. |
| @@ -7,7 +7,7 @@ config MT7996E · 6 unmodified lines | ||
| 7 | 7 | depends on MAC80211 |
| 8 | 8 | depends on PCI |
| 9 | 9 | help |
| 10 | − This adds support for MT7996-based wireless PCIe devices, | |
| 10 | + This adds support for MT7996-based PCIe wireless devices, | |
| 11 | 11 | which support concurrent tri-band operation at 6GHz, 5GHz, |
| 12 | 12 | and 2.4GHz IEEE 802.11be 4x4:4SS 4096-QAM, 320MHz channels. |
| 13 | 13 | |
| @@ -4,4 +4,4 @@ config MT7601U · 3 unmodified lines | ||
| 4 | 4 | depends on MAC80211 |
| 5 | 5 | depends on USB |
| 6 | 6 | help |
| 7 | − This adds support for MT7601U-based wireless USB dongles. | |
| 7 | + This adds support for MT7601U-based USB wireless dongles. | |
| @@ -8,15 +8,12 @@ · 7 unmodified lines | ||
| 8 | 8 | #define WILC_CFG80211_H |
| 9 | 9 | #include "netdev.h" |
| 10 | 10 | |
| 11 | −struct wiphy *wilc_cfg_alloc(void); | |
| 12 | 11 | int wilc_cfg80211_init(struct wilc **wilc, struct device *dev, int io_type, |
| 13 | 12 | const struct wilc_hif_func *ops); |
| 14 | 13 | struct wilc *wilc_create_wiphy(struct device *dev); |
| 15 | 14 | void wilc_deinit_host_int(struct net_device *net); |
| 16 | 15 | int wilc_init_host_int(struct net_device *net); |
| 17 | 16 | void wilc_wfi_monitor_rx(struct net_device *mon_dev, u8 *buff, u32 size); |
| 18 | −struct wilc_vif *wilc_netdev_interface(struct wilc *wl, const char *name, | |
| 19 | − enum nl80211_iftype type); | |
| 20 | 17 | void wilc_wfi_deinit_mon_interface(struct wilc *wl, bool rtnl_locked); |
| 21 | 18 | struct net_device *wilc_wfi_init_mon_interface(struct wilc *wl, |
| 22 | 19 | const char *name, |
| @@ -24,7 +21,6 @@ struct net_device *wilc_wfi_init_mon_interface(struct wilc *wl, · 1 unmodified line | ||
| 24 | 21 | void wilc_update_mgmt_frame_registrations(struct wiphy *wiphy, |
| 25 | 22 | struct wireless_dev *wdev, |
| 26 | 23 | struct mgmt_frame_regs *upd); |
| 27 | −struct wilc_vif *wilc_get_interface(struct wilc *wl); | |
| 28 | 24 | struct wilc_vif *wilc_get_wl_to_vif(struct wilc *wl); |
| 29 | 25 | void wlan_deinit_locks(struct wilc *wilc); |
| 30 | 26 | #endif |
| @@ -3,7 +3,7 @@ config PLFXLC · 2 unmodified lines | ||
| 3 | 3 | tristate "pureLiFi X, XL, XC device support" |
| 4 | 4 | depends on CFG80211 && MAC80211 && USB |
| 5 | 5 | help |
| 6 | − This option adds support for pureLiFi LiFi wireless USB | |
| 6 | + This option adds support for pureLiFi LiFi USB wireless | |
| 7 | 7 | adapters. The pureLiFi X, XL, XC USB devices are based on |
| 8 | 8 | 802.11 OFDM PHY but uses light as the transmission medium. |
| 9 | 9 | The driver supports common 802.11 encryption/authentication |
| @@ -170,7 +170,7 @@ config RT2800USB_RT35XX · 169 unmodified lines | ||
| 170 | 170 | config RT2800USB_RT3573 |
| 171 | 171 | bool "rt2800usb - Include support for rt3573 devices (EXPERIMENTAL)" |
| 172 | 172 | help |
| 173 | − This enables support for RT3573 chipset based wireless USB devices | |
| 173 | + This enables support for RT3573 chipset based USB wireless devices | |
| 174 | 174 | in the rt2800usb driver. |
| 175 | 175 | |
| 176 | 176 | config RT2800USB_RT53XX |
| @@ -3865,28 +3865,51 @@ static void rt2800_config_channel_rf7620(struct rt2x00_dev *rt2x00dev, · 3864 unmodified lines | ||
| 3865 | 3865 | } |
| 3866 | 3866 | } |
| 3867 | 3867 | |
| 3868 | −static void rt2800_config_alc(struct rt2x00_dev *rt2x00dev, | |
| 3869 | − struct ieee80211_channel *chan, | |
| 3870 | − int power_level) { | |
| 3871 | − u16 eeprom, target_power, max_power; | |
| 3868 | +static void rt2800_config_alc_rt6352(struct rt2x00_dev *rt2x00dev, | |
| 3869 | + struct ieee80211_channel *chan, | |
| 3870 | + int power_level) | |
| 3871 | +{ | |
| 3872 | + int cur_channel = rt2x00dev->rf_channel; | |
| 3873 | + u16 eeprom, chan_power, rate_power, target_power; | |
| 3874 | + u16 tx_power[2]; | |
| 3875 | + s8 *power_group[2]; | |
| 3872 | 3876 | u32 mac_sys_ctrl; |
| 3873 | − u32 reg; | |
| 3877 | + u32 cnt, reg; | |
| 3874 | 3878 | u8 bbp; |
| 3875 | 3879 | |
| 3876 | − /* hardware unit is 0.5dBm, limited to 23.5dBm */ | |
| 3877 | − power_level *= 2; | |
| 3878 | − if (power_level > 0x2f) | |
| 3879 | − power_level = 0x2f; | |
| 3880 | + if (WARN_ON(cur_channel < 1 || cur_channel > 14)) | |
| 3881 | + return; | |
| 3882 | + | |
| 3883 | + /* get per chain power, 2 chains in total, unit is 0.5dBm */ | |
| 3884 | + power_level = (power_level - 3) * 2; | |
| 3880 | 3885 | |
| 3881 | − max_power = chan->max_power * 2; | |
| 3882 | − if (max_power > 0x2f) | |
| 3883 | − max_power = 0x2f; | |
| 3886 | + /* We can't get the accurate TX power. Based on some tests, the real | |
| 3887 | + * TX power is approximately equal to channel_power + (max)rate_power. | |
| 3888 | + * Usually max rate_power is the gain of the OFDM 6M rate. The antenna | |
| 3889 | + * gain and externel PA gain are not included as we are unable to | |
| 3890 | + * obtain these values. | |
| 3891 | + */ | |
| 3892 | + rate_power = rt2800_eeprom_read_from_array(rt2x00dev, | |
| 3893 | + EEPROM_TXPOWER_BYRATE, 1); | |
| 3894 | + rate_power &= 0x3f; | |
| 3895 | + power_level -= rate_power; | |
| 3896 | + if (power_level < 1) | |
| 3897 | + power_level = 1; | |
| 3898 | + | |
| 3899 | + power_group[0] = rt2800_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_BG1); | |
| 3900 | + power_group[1] = rt2800_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_BG2); | |
| 3901 | + for (cnt = 0; cnt < 2; cnt++) { | |
| 3902 | + chan_power = power_group[cnt][cur_channel - 1]; | |
| 3903 | + if (chan_power >= 0x20 || chan_power == 0) | |
| 3904 | + chan_power = 0x10; | |
| 3905 | + tx_power[cnt] = power_level < chan_power ? power_level : chan_power; | |
| 3906 | + } | |
| 3884 | 3907 | |
| 3885 | 3908 | reg = rt2800_register_read(rt2x00dev, TX_ALC_CFG_0); |
| 3886 | − rt2x00_set_field32(®, TX_ALC_CFG_0_CH_INIT_0, power_level); | |
| 3887 | − rt2x00_set_field32(®, TX_ALC_CFG_0_CH_INIT_1, power_level); | |
| 3888 | − rt2x00_set_field32(®, TX_ALC_CFG_0_LIMIT_0, max_power); | |
| 3889 | − rt2x00_set_field32(®, TX_ALC_CFG_0_LIMIT_1, max_power); | |
| 3909 | + rt2x00_set_field32(®, TX_ALC_CFG_0_CH_INIT_0, tx_power[0]); | |
| 3910 | + rt2x00_set_field32(®, TX_ALC_CFG_0_CH_INIT_1, tx_power[1]); | |
| 3911 | + rt2x00_set_field32(®, TX_ALC_CFG_0_LIMIT_0, 0x2f); | |
| 3912 | + rt2x00_set_field32(®, TX_ALC_CFG_0_LIMIT_1, 0x2f); | |
| 3890 | 3913 | |
| 3891 | 3914 | eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1); |
| 3892 | 3915 | if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_INTERNAL_TX_ALC)) { |
| @@ -5268,7 +5291,7 @@ static void rt2800_config_txpower_rt6352(struct rt2x00_dev *rt2x00dev, · 1375 unmodified lines | ||
| 5268 | 5291 | rt2x00_set_field32(&pwreg, TX_PWR_CFG_9B_STBC_MCS7, t); |
| 5269 | 5292 | rt2800_register_write(rt2x00dev, TX_PWR_CFG_9, pwreg); |
| 5270 | 5293 | |
| 5271 | − rt2800_config_alc(rt2x00dev, chan, power_level); | |
| 5294 | + rt2800_config_alc_rt6352(rt2x00dev, chan, power_level); | |
| 5272 | 5295 | |
| 5273 | 5296 | /* TODO: temperature compensation code! */ |
| 5274 | 5297 | } |
| @@ -8561,7 +8584,7 @@ static void rt2800_r_calibration(struct rt2x00_dev *rt2x00dev) · 3286 unmodified lines | ||
| 8561 | 8584 | rt2x00_warn(rt2x00dev, "Wait MAC Tx Status to MAX !!!\n"); |
| 8562 | 8585 | |
| 8563 | 8586 | maccfg = rt2800_register_read(rt2x00dev, MAC_SYS_CTRL); |
| 8564 | − maccfg &= (~0x04); | |
| 8587 | + maccfg &= (~0x08); | |
| 8565 | 8588 | rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, maccfg); |
| 8566 | 8589 | |
| 8567 | 8590 | if (unlikely(rt2800_wait_bbp_rf_ready(rt2x00dev, MAC_STATUS_CFG_BBP_RF_BUSY_RX))) |
| @@ -1656,7 +1656,7 @@ static int rtl_op_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd, · 1655 unmodified lines | ||
| 1656 | 1656 | memcpy(rtlpriv->sec.key_buf[key_idx], |
| 1657 | 1657 | key->key, key->keylen); |
| 1658 | 1658 | rtlpriv->sec.key_len[key_idx] = key->keylen; |
| 1659 | − memcpy(mac_addr, bcast_addr, ETH_ALEN); | |
| 1659 | + eth_broadcast_addr(mac_addr); | |
| 1660 | 1660 | } else { /* pairwise key */ |
| 1661 | 1661 | rtl_dbg(rtlpriv, COMP_SEC, DBG_DMESG, |
| 1662 | 1662 | "set pairwise key\n"); |
| @@ -215,31 +215,3 @@ int rtl8723_download_fw(struct ieee80211_hw *hw, · 214 unmodified lines | ||
| 215 | 215 | } |
| 216 | 216 | EXPORT_SYMBOL_GPL(rtl8723_download_fw); |
| 217 | 217 | |
| 218 | −bool rtl8723_cmd_send_packet(struct ieee80211_hw *hw, | |
| 219 | − struct sk_buff *skb) | |
| 220 | −{ | |
| 221 | − struct rtl_priv *rtlpriv = rtl_priv(hw); | |
| 222 | − struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); | |
| 223 | − struct rtl8192_tx_ring *ring; | |
| 224 | − struct rtl_tx_desc *pdesc; | |
| 225 | − struct sk_buff *pskb = NULL; | |
| 226 | − unsigned long flags; | |
| 227 | − | |
| 228 | − ring = &rtlpci->tx_ring[BEACON_QUEUE]; | |
| 229 | − | |
| 230 | − pskb = __skb_dequeue(&ring->queue); | |
| 231 | − kfree_skb(pskb); | |
| 232 | − spin_lock_irqsave(&rtlpriv->locks.irq_th_lock, flags); | |
| 233 | − | |
| 234 | − pdesc = &ring->desc[0]; | |
| 235 | − rtlpriv->cfg->ops->fill_tx_cmddesc(hw, (u8 *)pdesc, 1, 1, skb); | |
| 236 | − | |
| 237 | − __skb_queue_tail(&ring->queue, skb); | |
| 238 | − | |
| 239 | − spin_unlock_irqrestore(&rtlpriv->locks.irq_th_lock, flags); | |
| 240 | − | |
| 241 | − rtlpriv->cfg->ops->tx_polling(hw, BEACON_QUEUE); | |
| 242 | − | |
| 243 | − return true; | |
| 244 | −} | |
| 245 | −EXPORT_SYMBOL_GPL(rtl8723_cmd_send_packet); | |
| @@ -66,7 +66,5 @@ void rtl8723_write_fw(struct ieee80211_hw *hw, · 65 unmodified lines | ||
| 66 | 66 | u8 *buffer, u32 size, u8 max_page); |
| 67 | 67 | int rtl8723_fw_free_to_go(struct ieee80211_hw *hw, bool is_8723be, int count); |
| 68 | 68 | int rtl8723_download_fw(struct ieee80211_hw *hw, bool is_8723be, int count); |
| 69 | −bool rtl8723_cmd_send_packet(struct ieee80211_hw *hw, | |
| 70 | − struct sk_buff *skb); | |
| 71 | 69 | |
| 72 | 70 | #endif |
| @@ -1828,5 +1828,5 @@ void rtw_pci_shutdown(struct pci_dev *pdev) · 1827 unmodified lines | ||
| 1828 | 1828 | EXPORT_SYMBOL(rtw_pci_shutdown); |
| 1829 | 1829 | |
| 1830 | 1830 | MODULE_AUTHOR("Realtek Corporation"); |
| 1831 | −MODULE_DESCRIPTION("Realtek 802.11ac wireless PCI driver"); | |
| 1831 | +MODULE_DESCRIPTION("Realtek PCI 802.11ac wireless driver"); | |
| 1832 | 1832 | MODULE_LICENSE("Dual BSD/GPL"); |
| @@ -826,7 +826,7 @@ int rtw_usb_probe(struct usb_interface *intf, const struct usb_device_id *id) · 825 unmodified lines | ||
| 826 | 826 | |
| 827 | 827 | ret = rtw_core_init(rtwdev); |
| 828 | 828 | if (ret) |
| 829 | − goto err_release_hw; | |
| 829 | + goto err_free_rx_bufs; | |
| 830 | 830 | |
| 831 | 831 | ret = rtw_usb_intf_init(rtwdev, intf); |
| 832 | 832 | if (ret) { |
| @@ -872,6 +872,9 @@ err_destroy_usb: · 39 unmodified lines | ||
| 872 | 872 | err_deinit_core: |
| 873 | 873 | rtw_core_deinit(rtwdev); |
| 874 | 874 | |
| 875 | +err_free_rx_bufs: | |
| 876 | + rtw_usb_free_rx_bufs(rtwusb); | |
| 877 | + | |
| 875 | 878 | err_release_hw: |
| 876 | 879 | ieee80211_free_hw(hw); |
| 877 | 880 | |
| @@ -909,5 +912,5 @@ void rtw_usb_disconnect(struct usb_interface *intf) · 31 unmodified lines | ||
| 909 | 912 | EXPORT_SYMBOL(rtw_usb_disconnect); |
| 910 | 913 | |
| 911 | 914 | MODULE_AUTHOR("Realtek Corporation"); |
| 912 | −MODULE_DESCRIPTION("Realtek 802.11ac wireless USB driver"); | |
| 915 | +MODULE_DESCRIPTION("Realtek USB 802.11ac wireless driver"); | |
| 913 | 916 | MODULE_LICENSE("Dual BSD/GPL"); |
| @@ -4,6 +4,8 @@ · 3 unmodified lines | ||
| 4 | 4 | |
| 5 | 5 | #include "chan.h" |
| 6 | 6 | #include "debug.h" |
| 7 | +#include "fw.h" | |
| 8 | +#include "ps.h" | |
| 7 | 9 | #include "util.h" |
| 8 | 10 | |
| 9 | 11 | static enum rtw89_subband rtw89_get_subband_type(enum rtw89_band band, |
| @@ -116,6 +118,7 @@ bool rtw89_assign_entity_chan(struct rtw89_dev *rtwdev, · 106 unmodified lines | ||
| 116 | 118 | rcd->prev_primary_channel = chan->primary_channel; |
| 117 | 119 | rcd->prev_band_type = chan->band_type; |
| 118 | 120 | band_changed = new->band_type != chan->band_type; |
| 121 | + rcd->band_changed = band_changed; | |
| 119 | 122 | |
| 120 | 123 | *chan = *new; |
| 121 | 124 | return band_changed; |
| @@ -193,8 +196,12 @@ void rtw89_entity_init(struct rtw89_dev *rtwdev) · 71 unmodified lines | ||
| 193 | 196 | enum rtw89_entity_mode rtw89_entity_recalc(struct rtw89_dev *rtwdev) |
| 194 | 197 | { |
| 195 | 198 | struct rtw89_hal *hal = &rtwdev->hal; |
| 199 | + const struct cfg80211_chan_def *chandef; | |
| 196 | 200 | enum rtw89_entity_mode mode; |
| 201 | + struct rtw89_chan chan; | |
| 197 | 202 | u8 weight; |
| 203 | + u8 last; | |
| 204 | + u8 idx; | |
| 198 | 205 | |
| 199 | 206 | weight = bitmap_weight(hal->entity_map, NUM_OF_RTW89_SUB_ENTITY); |
| 200 | 207 | switch (weight) { |
| @@ -206,14 +213,121 @@ enum rtw89_entity_mode rtw89_entity_recalc(struct rtw89_dev *rtwdev) · 5 unmodified lines | ||
| 206 | 213 | rtw89_config_default_chandef(rtwdev); |
| 207 | 214 | fallthrough; |
| 208 | 215 | case 1: |
| 216 | + last = RTW89_SUB_ENTITY_0; | |
| 209 | 217 | mode = RTW89_ENTITY_MODE_SCC; |
| 210 | 218 | break; |
| 219 | + case 2: | |
| 220 | + last = RTW89_SUB_ENTITY_1; | |
| 221 | + mode = rtw89_get_entity_mode(rtwdev); | |
| 222 | + if (mode == RTW89_ENTITY_MODE_MCC) | |
| 223 | + break; | |
| 224 | + | |
| 225 | + mode = RTW89_ENTITY_MODE_MCC_PREPARE; | |
| 226 | + break; | |
| 227 | + } | |
| 228 | + | |
| 229 | + for (idx = 0; idx <= last; idx++) { | |
| 230 | + chandef = rtw89_chandef_get(rtwdev, idx); | |
| 231 | + rtw89_get_channel_params(chandef, &chan); | |
| 232 | + if (chan.channel == 0) { | |
| 233 | + WARN(1, "Invalid channel on chanctx %d\n", idx); | |
| 234 | + return RTW89_ENTITY_MODE_INVALID; | |
| 235 | + } | |
| 236 | + | |
| 237 | + rtw89_assign_entity_chan(rtwdev, idx, &chan); | |
| 211 | 238 | } |
| 212 | 239 | |
| 213 | 240 | rtw89_set_entity_mode(rtwdev, mode); |
| 214 | 241 | return mode; |
| 215 | 242 | } |
| 216 | 243 | |
| 244 | +static void rtw89_chanctx_notify(struct rtw89_dev *rtwdev, | |
| 245 | + enum rtw89_chanctx_state state) | |
| 246 | +{ | |
| 247 | + const struct rtw89_chip_info *chip = rtwdev->chip; | |
| 248 | + const struct rtw89_chanctx_listener *listener = chip->chanctx_listener; | |
| 249 | + int i; | |
| 250 | + | |
| 251 | + if (!listener) | |
| 252 | + return; | |
| 253 | + | |
| 254 | + for (i = 0; i < NUM_OF_RTW89_CHANCTX_CALLBACKS; i++) { | |
| 255 | + if (!listener->callbacks[i]) | |
| 256 | + continue; | |
| 257 | + | |
| 258 | + rtw89_debug(rtwdev, RTW89_DBG_CHAN, | |
| 259 | + "chanctx notify listener: cb %d, state %d\n", | |
| 260 | + i, state); | |
| 261 | + | |
| 262 | + listener->callbacks[i](rtwdev, state); | |
| 263 | + } | |
| 264 | +} | |
| 265 | + | |
| 266 | +static int rtw89_mcc_start(struct rtw89_dev *rtwdev) | |
| 267 | +{ | |
| 268 | + if (rtwdev->scanning) | |
| 269 | + rtw89_hw_scan_abort(rtwdev, rtwdev->scan_info.scanning_vif); | |
| 270 | + | |
| 271 | + rtw89_leave_lps(rtwdev); | |
| 272 | + | |
| 273 | + rtw89_debug(rtwdev, RTW89_DBG_CHAN, "MCC start\n"); | |
| 274 | + rtw89_chanctx_notify(rtwdev, RTW89_CHANCTX_STATE_MCC_START); | |
| 275 | + return 0; | |
| 276 | +} | |
| 277 | + | |
| 278 | +static void rtw89_mcc_stop(struct rtw89_dev *rtwdev) | |
| 279 | +{ | |
| 280 | + rtw89_debug(rtwdev, RTW89_DBG_CHAN, "MCC stop\n"); | |
| 281 | + rtw89_chanctx_notify(rtwdev, RTW89_CHANCTX_STATE_MCC_STOP); | |
| 282 | +} | |
| 283 | + | |
| 284 | +void rtw89_chanctx_work(struct work_struct *work) | |
| 285 | +{ | |
| 286 | + struct rtw89_dev *rtwdev = container_of(work, struct rtw89_dev, | |
| 287 | + chanctx_work.work); | |
| 288 | + enum rtw89_entity_mode mode; | |
| 289 | + int ret; | |
| 290 | + | |
| 291 | + mutex_lock(&rtwdev->mutex); | |
| 292 | + | |
| 293 | + mode = rtw89_get_entity_mode(rtwdev); | |
| 294 | + switch (mode) { | |
| 295 | + case RTW89_ENTITY_MODE_MCC_PREPARE: | |
| 296 | + rtw89_set_entity_mode(rtwdev, RTW89_ENTITY_MODE_MCC); | |
| 297 | + rtw89_set_channel(rtwdev); | |
| 298 | + | |
| 299 | + ret = rtw89_mcc_start(rtwdev); | |
| 300 | + if (ret) | |
| 301 | + rtw89_warn(rtwdev, "failed to start MCC: %d\n", ret); | |
| 302 | + break; | |
| 303 | + default: | |
| 304 | + break; | |
| 305 | + } | |
| 306 | + | |
| 307 | + mutex_unlock(&rtwdev->mutex); | |
| 308 | +} | |
| 309 | + | |
| 310 | +void rtw89_queue_chanctx_work(struct rtw89_dev *rtwdev) | |
| 311 | +{ | |
| 312 | + enum rtw89_entity_mode mode; | |
| 313 | + u32 delay; | |
| 314 | + | |
| 315 | + mode = rtw89_get_entity_mode(rtwdev); | |
| 316 | + switch (mode) { | |
| 317 | + default: | |
| 318 | + return; | |
| 319 | + case RTW89_ENTITY_MODE_MCC_PREPARE: | |
| 320 | + delay = ieee80211_tu_to_usec(RTW89_CHANCTX_TIME_MCC_PREPARE); | |
| 321 | + break; | |
| 322 | + } | |
| 323 | + | |
| 324 | + rtw89_debug(rtwdev, RTW89_DBG_CHAN, | |
| 325 | + "queue chanctx work for mode %d with delay %d us\n", | |
| 326 | + mode, delay); | |
| 327 | + ieee80211_queue_delayed_work(rtwdev->hw, &rtwdev->chanctx_work, | |
| 328 | + usecs_to_jiffies(delay)); | |
| 329 | +} | |
| 330 | + | |
| 217 | 331 | int rtw89_chanctx_ops_add(struct rtw89_dev *rtwdev, |
| 218 | 332 | struct ieee80211_chanctx_conf *ctx) |
| 219 | 333 | { |
| @@ -238,6 +352,7 @@ void rtw89_chanctx_ops_remove(struct rtw89_dev *rtwdev, · 18 unmodified lines | ||
| 238 | 352 | { |
| 239 | 353 | struct rtw89_hal *hal = &rtwdev->hal; |
| 240 | 354 | struct rtw89_chanctx_cfg *cfg = (struct rtw89_chanctx_cfg *)ctx->drv_priv; |
| 355 | + enum rtw89_entity_mode mode; | |
| 241 | 356 | struct rtw89_vif *rtwvif; |
| 242 | 357 | u8 drop, roll; |
| 243 | 358 | |
| @@ -267,6 +382,15 @@ void rtw89_chanctx_ops_remove(struct rtw89_dev *rtwdev, · 23 unmodified lines | ||
| 267 | 382 | drop = roll; |
| 268 | 383 | |
| 269 | 384 | out: |
| 385 | + mode = rtw89_get_entity_mode(rtwdev); | |
| 386 | + switch (mode) { | |
| 387 | + case RTW89_ENTITY_MODE_MCC: | |
| 388 | + rtw89_mcc_stop(rtwdev); | |
| 389 | + break; | |
| 390 | + default: | |
| 391 | + break; | |
| 392 | + } | |
| 393 | + | |
| 270 | 394 | clear_bit(drop, hal->entity_map); |
| 271 | 395 | rtw89_set_channel(rtwdev); |
| 272 | 396 | } |
| @@ -7,6 +7,9 @@ · 6 unmodified lines | ||
| 7 | 7 | |
| 8 | 8 | #include "core.h" |
| 9 | 9 | |
| 10 | +/* The dwell time in TU before doing rtw89_chanctx_work(). */ | |
| 11 | +#define RTW89_CHANCTX_TIME_MCC_PREPARE 100 | |
| 12 | + | |
| 10 | 13 | static inline bool rtw89_get_entity_state(struct rtw89_dev *rtwdev) |
| 11 | 14 | { |
| 12 | 15 | struct rtw89_hal *hal = &rtwdev->hal; |
| @@ -50,6 +53,8 @@ void rtw89_config_roc_chandef(struct rtw89_dev *rtwdev, · 37 unmodified lines | ||
| 50 | 53 | const struct cfg80211_chan_def *chandef); |
| 51 | 54 | void rtw89_entity_init(struct rtw89_dev *rtwdev); |
| 52 | 55 | enum rtw89_entity_mode rtw89_entity_recalc(struct rtw89_dev *rtwdev); |
| 56 | +void rtw89_chanctx_work(struct work_struct *work); | |
| 57 | +void rtw89_queue_chanctx_work(struct rtw89_dev *rtwdev); | |
| 53 | 58 | int rtw89_chanctx_ops_add(struct rtw89_dev *rtwdev, |
| 54 | 59 | struct ieee80211_chanctx_conf *ctx); |
| 55 | 60 | void rtw89_chanctx_ops_remove(struct rtw89_dev *rtwdev, |
| @@ -5666,7 +5666,8 @@ enum btc_wl_mode { · 5665 unmodified lines | ||
| 5666 | 5666 | void rtw89_btc_ntfy_role_info(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif, |
| 5667 | 5667 | struct rtw89_sta *rtwsta, enum btc_role_state state) |
| 5668 | 5668 | { |
| 5669 | − const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, RTW89_SUB_ENTITY_0); | |
| 5669 | + const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, | |
| 5670 | + rtwvif->sub_entity_idx); | |
| 5670 | 5671 | struct ieee80211_vif *vif = rtwvif_to_vif(rtwvif); |
| 5671 | 5672 | struct ieee80211_sta *sta = rtwsta_to_sta(rtwsta); |
| 5672 | 5673 | struct rtw89_btc *btc = &rtwdev->btc; |
| @@ -193,4 +193,13 @@ static inline u8 rtw89_btc_path_phymap(struct rtw89_dev *rtwdev, · 192 unmodified lines | ||
| 193 | 193 | return rtw89_btc_phymap(rtwdev, phy_idx, BIT(path)); |
| 194 | 194 | } |
| 195 | 195 | |
| 196 | +/* return bt req len in TU */ | |
| 197 | +static inline u16 rtw89_coex_query_bt_req_len(struct rtw89_dev *rtwdev, | |
| 198 | + enum rtw89_phy_idx phy_idx) | |
| 199 | +{ | |
| 200 | + struct rtw89_btc *btc = &rtwdev->btc; | |
| 201 | + | |
| 202 | + return btc->bt_req_len; | |
| 203 | +} | |
| 204 | + | |
| 196 | 205 | #endif |
| @@ -256,8 +256,8 @@ void rtw89_get_default_chandef(struct cfg80211_chan_def *chandef) · 255 unmodified lines | ||
| 256 | 256 | NL80211_CHAN_NO_HT); |
| 257 | 257 | } |
| 258 | 258 | |
| 259 | −static void rtw89_get_channel_params(const struct cfg80211_chan_def *chandef, | |
| 260 | − struct rtw89_chan *chan) | |
| 259 | +void rtw89_get_channel_params(const struct cfg80211_chan_def *chandef, | |
| 260 | + struct rtw89_chan *chan) | |
| 261 | 261 | { |
| 262 | 262 | struct ieee80211_channel *channel = chandef->chan; |
| 263 | 263 | enum nl80211_chan_width width = chandef->width; |
| @@ -318,9 +318,11 @@ static void rtw89_get_channel_params(const struct cfg80211_chan_def *chandef, · 54 unmodified lines | ||
| 318 | 318 | |
| 319 | 319 | void rtw89_core_set_chip_txpwr(struct rtw89_dev *rtwdev) |
| 320 | 320 | { |
| 321 | + struct rtw89_hal *hal = &rtwdev->hal; | |
| 321 | 322 | const struct rtw89_chip_info *chip = rtwdev->chip; |
| 322 | 323 | const struct rtw89_chan *chan; |
| 323 | 324 | enum rtw89_sub_entity_idx sub_entity_idx; |
| 325 | + enum rtw89_sub_entity_idx roc_idx; | |
| 324 | 326 | enum rtw89_phy_idx phy_idx; |
| 325 | 327 | enum rtw89_entity_mode mode; |
| 326 | 328 | bool entity_active; |
| @@ -330,10 +332,23 @@ void rtw89_core_set_chip_txpwr(struct rtw89_dev *rtwdev) · 3 unmodified lines | ||
| 330 | 332 | return; |
| 331 | 333 | |
| 332 | 334 | mode = rtw89_get_entity_mode(rtwdev); |
| 333 | − if (WARN(mode != RTW89_ENTITY_MODE_SCC, "Invalid ent mode: %d\n", mode)) | |
| 335 | + switch (mode) { | |
| 336 | + case RTW89_ENTITY_MODE_SCC: | |
| 337 | + case RTW89_ENTITY_MODE_MCC: | |
| 338 | + sub_entity_idx = RTW89_SUB_ENTITY_0; | |
| 339 | + break; | |
| 340 | + case RTW89_ENTITY_MODE_MCC_PREPARE: | |
| 341 | + sub_entity_idx = RTW89_SUB_ENTITY_1; | |
| 342 | + break; | |
| 343 | + default: | |
| 344 | + WARN(1, "Invalid ent mode: %d\n", mode); | |
| 334 | 345 | return; |
| 346 | + } | |
| 347 | + | |
| 348 | + roc_idx = atomic_read(&hal->roc_entity_idx); | |
| 349 | + if (roc_idx != RTW89_SUB_ENTITY_IDLE) | |
| 350 | + sub_entity_idx = roc_idx; | |
| 335 | 351 | |
| 336 | − sub_entity_idx = RTW89_SUB_ENTITY_0; | |
| 337 | 352 | phy_idx = RTW89_PHY_0; |
| 338 | 353 | chan = rtw89_chan_get(rtwdev, sub_entity_idx); |
| 339 | 354 | chip->ops->set_txpwr(rtwdev, chan, phy_idx); |
| @@ -341,43 +356,54 @@ void rtw89_core_set_chip_txpwr(struct rtw89_dev *rtwdev) · 1 unmodified line | ||
| 341 | 356 | |
| 342 | 357 | void rtw89_set_channel(struct rtw89_dev *rtwdev) |
| 343 | 358 | { |
| 359 | + struct rtw89_hal *hal = &rtwdev->hal; | |
| 344 | 360 | const struct rtw89_chip_info *chip = rtwdev->chip; |
| 345 | − const struct cfg80211_chan_def *chandef; | |
| 361 | + const struct rtw89_chan_rcd *chan_rcd; | |
| 362 | + const struct rtw89_chan *chan; | |
| 346 | 363 | enum rtw89_sub_entity_idx sub_entity_idx; |
| 364 | + enum rtw89_sub_entity_idx roc_idx; | |
| 347 | 365 | enum rtw89_mac_idx mac_idx; |
| 348 | 366 | enum rtw89_phy_idx phy_idx; |
| 349 | − struct rtw89_chan chan; | |
| 350 | 367 | struct rtw89_channel_help_params bak; |
| 351 | 368 | enum rtw89_entity_mode mode; |
| 352 | − bool band_changed; | |
| 353 | 369 | bool entity_active; |
| 354 | 370 | |
| 355 | 371 | entity_active = rtw89_get_entity_state(rtwdev); |
| 356 | 372 | |
| 357 | 373 | mode = rtw89_entity_recalc(rtwdev); |
| 358 | − if (WARN(mode != RTW89_ENTITY_MODE_SCC, "Invalid ent mode: %d\n", mode)) | |
| 374 | + switch (mode) { | |
| 375 | + case RTW89_ENTITY_MODE_SCC: | |
| 376 | + case RTW89_ENTITY_MODE_MCC: | |
| 377 | + sub_entity_idx = RTW89_SUB_ENTITY_0; | |
| 378 | + break; | |
| 379 | + case RTW89_ENTITY_MODE_MCC_PREPARE: | |
| 380 | + sub_entity_idx = RTW89_SUB_ENTITY_1; | |
| 381 | + break; | |
| 382 | + default: | |
| 383 | + WARN(1, "Invalid ent mode: %d\n", mode); | |
| 359 | 384 | return; |
| 385 | + } | |
| 386 | + | |
| 387 | + roc_idx = atomic_read(&hal->roc_entity_idx); | |
| 388 | + if (roc_idx != RTW89_SUB_ENTITY_IDLE) | |
| 389 | + sub_entity_idx = roc_idx; | |
| 360 | 390 | |
| 361 | − sub_entity_idx = RTW89_SUB_ENTITY_0; | |
| 362 | 391 | mac_idx = RTW89_MAC_0; |
| 363 | 392 | phy_idx = RTW89_PHY_0; |
| 364 | − chandef = rtw89_chandef_get(rtwdev, sub_entity_idx); | |
| 365 | − rtw89_get_channel_params(chandef, &chan); | |
| 366 | − if (WARN(chan.channel == 0, "Invalid channel\n")) | |
| 367 | − return; | |
| 368 | 393 | |
| 369 | − band_changed = rtw89_assign_entity_chan(rtwdev, sub_entity_idx, &chan); | |
| 394 | + chan = rtw89_chan_get(rtwdev, sub_entity_idx); | |
| 395 | + chan_rcd = rtw89_chan_rcd_get(rtwdev, sub_entity_idx); | |
| 370 | 396 | |
| 371 | − rtw89_chip_set_channel_prepare(rtwdev, &bak, &chan, mac_idx, phy_idx); | |
| 397 | + rtw89_chip_set_channel_prepare(rtwdev, &bak, chan, mac_idx, phy_idx); | |
| 372 | 398 | |
| 373 | − chip->ops->set_channel(rtwdev, &chan, mac_idx, phy_idx); | |
| 399 | + chip->ops->set_channel(rtwdev, chan, mac_idx, phy_idx); | |
| 374 | 400 | |
| 375 | − chip->ops->set_txpwr(rtwdev, &chan, phy_idx); | |
| 401 | + chip->ops->set_txpwr(rtwdev, chan, phy_idx); | |
| 376 | 402 | |
| 377 | − rtw89_chip_set_channel_done(rtwdev, &bak, &chan, mac_idx, phy_idx); | |
| 403 | + rtw89_chip_set_channel_done(rtwdev, &bak, chan, mac_idx, phy_idx); | |
| 378 | 404 | |
| 379 | − if (!entity_active || band_changed) { | |
| 380 | − rtw89_btc_ntfy_switch_band(rtwdev, phy_idx, chan.band_type); | |
| 405 | + if (!entity_active || chan_rcd->band_changed) { | |
| 406 | + rtw89_btc_ntfy_switch_band(rtwdev, phy_idx, chan->band_type); | |
| 381 | 407 | rtw89_chip_rfk_band_changed(rtwdev, phy_idx); |
| 382 | 408 | } |
| 383 | 409 | |
| @@ -523,12 +549,12 @@ rtw89_core_tx_update_sec_key(struct rtw89_dev *rtwdev, · 139 unmodified lines | ||
| 523 | 549 | } |
| 524 | 550 | |
| 525 | 551 | static u16 rtw89_core_get_mgmt_rate(struct rtw89_dev *rtwdev, |
| 526 | − struct rtw89_core_tx_request *tx_req) | |
| 552 | + struct rtw89_core_tx_request *tx_req, | |
| 553 | + const struct rtw89_chan *chan) | |
| 527 | 554 | { |
| 528 | 555 | struct sk_buff *skb = tx_req->skb; |
| 529 | 556 | struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb); |
| 530 | 557 | struct ieee80211_vif *vif = tx_info->control.vif; |
| 531 | − const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, RTW89_SUB_ENTITY_0); | |
| 532 | 558 | u16 lowest_rate; |
| 533 | 559 | |
| 534 | 560 | if (tx_info->flags & IEEE80211_TX_CTL_NO_CCK_RATE || |
| @@ -567,7 +593,8 @@ rtw89_core_tx_update_mgmt_info(struct rtw89_dev *rtwdev, · 32 unmodified lines | ||
| 567 | 593 | struct ieee80211_vif *vif = tx_req->vif; |
| 568 | 594 | struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; |
| 569 | 595 | struct rtw89_tx_desc_info *desc_info = &tx_req->desc_info; |
| 570 | − const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, RTW89_SUB_ENTITY_0); | |
| 596 | + const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, | |
| 597 | + rtwvif->sub_entity_idx); | |
| 571 | 598 | u8 qsel, ch_dma; |
| 572 | 599 | |
| 573 | 600 | qsel = desc_info->hiq ? RTW89_TX_QSEL_B0_HI : RTW89_TX_QSEL_B0_MGMT; |
| @@ -584,7 +611,7 @@ rtw89_core_tx_update_mgmt_info(struct rtw89_dev *rtwdev, · 10 unmodified lines | ||
| 584 | 611 | desc_info->en_wd_info = true; |
| 585 | 612 | desc_info->use_rate = true; |
| 586 | 613 | desc_info->dis_data_fb = true; |
| 587 | − desc_info->data_rate = rtw89_core_get_mgmt_rate(rtwdev, tx_req); | |
| 614 | + desc_info->data_rate = rtw89_core_get_mgmt_rate(rtwdev, tx_req, chan); | |
| 588 | 615 | |
| 589 | 616 | rtw89_debug(rtwdev, RTW89_DBG_TXRX, |
| 590 | 617 | "tx mgmt frame with rate 0x%x on channel %d (band %d, bw %d)\n", |
| @@ -603,7 +630,8 @@ rtw89_core_tx_update_h2c_info(struct rtw89_dev *rtwdev, · 12 unmodified lines | ||
| 603 | 630 | desc_info->ch_dma = RTW89_DMA_H2C; |
| 604 | 631 | } |
| 605 | 632 | |
| 606 | −static void rtw89_core_get_no_ul_ofdma_htc(struct rtw89_dev *rtwdev, __le32 *htc) | |
| 633 | +static void rtw89_core_get_no_ul_ofdma_htc(struct rtw89_dev *rtwdev, __le32 *htc, | |
| 634 | + const struct rtw89_chan *chan) | |
| 607 | 635 | { |
| 608 | 636 | static const u8 rtw89_bandwidth_to_om[] = { |
| 609 | 637 | [RTW89_CHANNEL_WIDTH_20] = HTC_OM_CHANNEL_WIDTH_20, |
| @@ -614,7 +642,6 @@ static void rtw89_core_get_no_ul_ofdma_htc(struct rtw89_dev *rtwdev, __le32 *htc · 4 unmodified lines | ||
| 614 | 642 | }; |
| 615 | 643 | const struct rtw89_chip_info *chip = rtwdev->chip; |
| 616 | 644 | struct rtw89_hal *hal = &rtwdev->hal; |
| 617 | − const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, RTW89_SUB_ENTITY_0); | |
| 618 | 645 | u8 om_bandwidth; |
| 619 | 646 | |
| 620 | 647 | if (!chip->dis_2g_40m_ul_ofdma || |
| @@ -1659,8 +1686,7 @@ static void rtw89_correct_cck_chan(struct rtw89_dev *rtwdev, · 1038 unmodified lines | ||
| 1659 | 1686 | const struct rtw89_chan_rcd *rcd = |
| 1660 | 1687 | rtw89_chan_rcd_get(rtwdev, RTW89_SUB_ENTITY_0); |
| 1661 | 1688 | u16 chan = rcd->prev_primary_channel; |
| 1662 | − u8 band = rcd->prev_band_type == RTW89_BAND_2G ? | |
| 1663 | − NL80211_BAND_2GHZ : NL80211_BAND_5GHZ; | |
| 1689 | + u8 band = rtw89_hw_to_nl80211_band(rcd->prev_band_type); | |
| 1664 | 1690 | |
| 1665 | 1691 | if (status->band != NL80211_BAND_2GHZ && |
| 1666 | 1692 | status->encoding == RX_ENC_LEGACY && |
| @@ -1900,7 +1926,6 @@ static void rtw89_core_update_rx_status(struct rtw89_dev *rtwdev, · 233 unmodified lines | ||
| 1900 | 1926 | { |
| 1901 | 1927 | const struct cfg80211_chan_def *chandef = |
| 1902 | 1928 | rtw89_chandef_get(rtwdev, RTW89_SUB_ENTITY_0); |
| 1903 | − const struct rtw89_chan *cur = rtw89_chan_get(rtwdev, RTW89_SUB_ENTITY_0); | |
| 1904 | 1929 | u16 data_rate; |
| 1905 | 1930 | u8 data_rate_mode; |
| 1906 | 1931 | |
| @@ -1910,6 +1935,7 @@ static void rtw89_core_update_rx_status(struct rtw89_dev *rtwdev, · 3 unmodified lines | ||
| 1910 | 1935 | |
| 1911 | 1936 | if (rtwdev->scanning && |
| 1912 | 1937 | RTW89_CHK_FW_FEATURE(SCAN_OFFLOAD, &rtwdev->fw)) { |
| 1938 | + const struct rtw89_chan *cur = rtw89_scan_chan_get(rtwdev); | |
| 1913 | 1939 | u8 chan = cur->primary_channel; |
| 1914 | 1940 | u8 band = cur->band_type; |
| 1915 | 1941 | enum nl80211_band nl_band; |
| @@ -2451,6 +2477,7 @@ out: · 535 unmodified lines | ||
| 2451 | 2477 | |
| 2452 | 2478 | void rtw89_roc_start(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif) |
| 2453 | 2479 | { |
| 2480 | + const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; | |
| 2454 | 2481 | struct ieee80211_hw *hw = rtwdev->hw; |
| 2455 | 2482 | struct rtw89_roc *roc = &rtwvif->roc; |
| 2456 | 2483 | struct cfg80211_chan_def roc_chan; |
| @@ -2478,7 +2505,7 @@ void rtw89_roc_start(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif) · 21 unmodified lines | ||
| 2478 | 2505 | rtw89_config_roc_chandef(rtwdev, rtwvif->sub_entity_idx, &roc_chan); |
| 2479 | 2506 | rtw89_set_channel(rtwdev); |
| 2480 | 2507 | rtw89_write32_clr(rtwdev, |
| 2481 | − rtw89_mac_reg_by_idx(R_AX_RX_FLTR_OPT, RTW89_MAC_0), | |
| 2508 | + rtw89_mac_reg_by_idx(rtwdev, mac->rx_fltr, RTW89_MAC_0), | |
| 2482 | 2509 | B_AX_A_UC_CAM_MATCH | B_AX_A_BC_CAM_MATCH); |
| 2483 | 2510 | |
| 2484 | 2511 | ieee80211_ready_on_channel(hw); |
| @@ -2486,6 +2513,7 @@ void rtw89_roc_start(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif) · 1 unmodified line | ||
| 2486 | 2513 | |
| 2487 | 2514 | void rtw89_roc_end(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif) |
| 2488 | 2515 | { |
| 2516 | + const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; | |
| 2489 | 2517 | struct ieee80211_hw *hw = rtwdev->hw; |
| 2490 | 2518 | struct rtw89_roc *roc = &rtwvif->roc; |
| 2491 | 2519 | struct rtw89_vif *tmp; |
| @@ -2499,7 +2527,7 @@ void rtw89_roc_end(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif) · 7 unmodified lines | ||
| 2499 | 2527 | rtw89_leave_lps(rtwdev); |
| 2500 | 2528 | |
| 2501 | 2529 | rtw89_write32_mask(rtwdev, |
| 2502 | − rtw89_mac_reg_by_idx(R_AX_RX_FLTR_OPT, RTW89_MAC_0), | |
| 2530 | + rtw89_mac_reg_by_idx(rtwdev, mac->rx_fltr, RTW89_MAC_0), | |
| 2503 | 2531 | B_AX_RX_FLTR_CFG_MASK, |
| 2504 | 2532 | rtwdev->hal.rx_fltr); |
| 2505 | 2533 | |
| @@ -2682,6 +2710,7 @@ static void rtw89_track_work(struct work_struct *work) · 176 unmodified lines | ||
| 2682 | 2710 | rtw89_phy_tx_path_div_track(rtwdev); |
| 2683 | 2711 | rtw89_phy_antdiv_track(rtwdev); |
| 2684 | 2712 | rtw89_phy_ul_tb_ctrl_track(rtwdev); |
| 2713 | + rtw89_tas_track(rtwdev); | |
| 2685 | 2714 | |
| 2686 | 2715 | if (rtwdev->lps_enabled && !rtwdev->btc.lps) |
| 2687 | 2716 | rtw89_enter_lps_track(rtwdev); |
| @@ -2970,6 +2999,8 @@ int rtw89_core_sta_assoc(struct rtw89_dev *rtwdev, · 282 unmodified lines | ||
| 2970 | 2999 | struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; |
| 2971 | 3000 | struct rtw89_sta *rtwsta = (struct rtw89_sta *)sta->drv_priv; |
| 2972 | 3001 | struct rtw89_bssid_cam_entry *bssid_cam = rtw89_get_bssid_cam_of(rtwvif, rtwsta); |
| 3002 | + const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, | |
| 3003 | + rtwvif->sub_entity_idx); | |
| 2973 | 3004 | int ret; |
| 2974 | 3005 | |
| 2975 | 3006 | if (vif->type == NL80211_IFTYPE_AP || sta->tdls) { |
| @@ -3023,7 +3054,7 @@ int rtw89_core_sta_assoc(struct rtw89_dev *rtwdev, · 47 unmodified lines | ||
| 3023 | 3054 | |
| 3024 | 3055 | rtw89_btc_ntfy_role_info(rtwdev, rtwvif, rtwsta, |
| 3025 | 3056 | BTC_ROLE_MSTS_STA_CONN_END); |
| 3026 | − rtw89_core_get_no_ul_ofdma_htc(rtwdev, &rtwsta->htc_template); | |
| 3057 | + rtw89_core_get_no_ul_ofdma_htc(rtwdev, &rtwsta->htc_template, chan); | |
| 3027 | 3058 | rtw89_phy_ul_tb_assoc(rtwdev, rtwvif); |
| 3028 | 3059 | |
| 3029 | 3060 | ret = rtw89_fw_h2c_general_pkt(rtwdev, rtwvif, rtwsta->mac_id); |
| @@ -3463,6 +3494,27 @@ void rtw89_complete_cond(struct rtw89_wait_info *wait, unsigned int cond, · 433 unmodified lines | ||
| 3463 | 3494 | complete(&wait->completion); |
| 3464 | 3495 | } |
| 3465 | 3496 | |
| 3497 | +void rtw89_core_ntfy_btc_event(struct rtw89_dev *rtwdev, enum rtw89_btc_hmsg event) | |
| 3498 | +{ | |
| 3499 | + u16 bt_req_len; | |
| 3500 | + | |
| 3501 | + switch (event) { | |
| 3502 | + case RTW89_BTC_HMSG_SET_BT_REQ_SLOT: | |
| 3503 | + bt_req_len = rtw89_coex_query_bt_req_len(rtwdev, RTW89_PHY_0); | |
| 3504 | + rtw89_debug(rtwdev, RTW89_DBG_BTC, | |
| 3505 | + "coex updates BT req len to %d TU\n", bt_req_len); | |
| 3506 | + break; | |
| 3507 | + default: | |
| 3508 | + if (event < NUM_OF_RTW89_BTC_HMSG) | |
| 3509 | + rtw89_debug(rtwdev, RTW89_DBG_BTC, | |
| 3510 | + "unhandled BTC HMSG event: %d\n", event); | |
| 3511 | + else | |
| 3512 | + rtw89_warn(rtwdev, | |
| 3513 | + "unrecognized BTC HMSG event: %d\n", event); | |
| 3514 | + break; | |
| 3515 | + } | |
| 3516 | +} | |
| 3517 | + | |
| 3466 | 3518 | int rtw89_core_start(struct rtw89_dev *rtwdev) |
| 3467 | 3519 | { |
| 3468 | 3520 | int ret; |
| @@ -3496,6 +3548,8 @@ int rtw89_core_start(struct rtw89_dev *rtwdev) · 27 unmodified lines | ||
| 3496 | 3548 | rtw89_mac_cfg_ppdu_status(rtwdev, RTW89_MAC_0, true); |
| 3497 | 3549 | rtw89_mac_update_rts_threshold(rtwdev, RTW89_MAC_0); |
| 3498 | 3550 | |
| 3551 | + rtw89_tas_reset(rtwdev); | |
| 3552 | + | |
| 3499 | 3553 | ret = rtw89_hci_start(rtwdev); |
| 3500 | 3554 | if (ret) { |
| 3501 | 3555 | rtw89_err(rtwdev, "failed to start hci\n"); |
| @@ -3536,6 +3590,7 @@ void rtw89_core_stop(struct rtw89_dev *rtwdev) · 34 unmodified lines | ||
| 3536 | 3590 | cancel_work_sync(&btc->icmp_notify_work); |
| 3537 | 3591 | cancel_delayed_work_sync(&rtwdev->txq_reinvoke_work); |
| 3538 | 3592 | cancel_delayed_work_sync(&rtwdev->track_work); |
| 3593 | + cancel_delayed_work_sync(&rtwdev->chanctx_work); | |
| 3539 | 3594 | cancel_delayed_work_sync(&rtwdev->coex_act1_work); |
| 3540 | 3595 | cancel_delayed_work_sync(&rtwdev->coex_bt_devinfo_work); |
| 3541 | 3596 | cancel_delayed_work_sync(&rtwdev->coex_rfk_chk_work); |
| @@ -3572,6 +3627,7 @@ int rtw89_core_init(struct rtw89_dev *rtwdev) · 30 unmodified lines | ||
| 3572 | 3627 | INIT_WORK(&rtwdev->txq_work, rtw89_core_txq_work); |
| 3573 | 3628 | INIT_DELAYED_WORK(&rtwdev->txq_reinvoke_work, rtw89_core_txq_reinvoke_work); |
| 3574 | 3629 | INIT_DELAYED_WORK(&rtwdev->track_work, rtw89_track_work); |
| 3630 | + INIT_DELAYED_WORK(&rtwdev->chanctx_work, rtw89_chanctx_work); | |
| 3575 | 3631 | INIT_DELAYED_WORK(&rtwdev->coex_act1_work, rtw89_coex_act1_work); |
| 3576 | 3632 | INIT_DELAYED_WORK(&rtwdev->coex_bt_devinfo_work, rtw89_coex_bt_devinfo_work); |
| 3577 | 3633 | INIT_DELAYED_WORK(&rtwdev->coex_rfk_chk_work, rtw89_coex_rfk_chk_work); |
| @@ -3612,6 +3668,7 @@ int rtw89_core_init(struct rtw89_dev *rtwdev) · 34 unmodified lines | ||
| 3612 | 3668 | |
| 3613 | 3669 | rtw89_ser_init(rtwdev); |
| 3614 | 3670 | rtw89_entity_init(rtwdev); |
| 3671 | + rtw89_tas_init(rtwdev); | |
| 3615 | 3672 | |
| 3616 | 3673 | return 0; |
| 3617 | 3674 | } |
| @@ -3632,7 +3689,8 @@ EXPORT_SYMBOL(rtw89_core_deinit); · 14 unmodified lines | ||
| 3632 | 3689 | void rtw89_core_scan_start(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif, |
| 3633 | 3690 | const u8 *mac_addr, bool hw_scan) |
| 3634 | 3691 | { |
| 3635 | − const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, RTW89_SUB_ENTITY_0); | |
| 3692 | + const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, | |
| 3693 | + rtwvif->sub_entity_idx); | |
| 3636 | 3694 | |
| 3637 | 3695 | rtwdev->scanning = true; |
| 3638 | 3696 | rtw89_leave_lps(rtwdev); |
| @@ -14,6 +14,8 @@ · 13 unmodified lines | ||
| 14 | 14 | |
| 15 | 15 | struct rtw89_dev; |
| 16 | 16 | struct rtw89_pci_info; |
| 17 | +struct rtw89_mac_gen_def; | |
| 18 | +struct rtw89_phy_gen_def; | |
| 17 | 19 | |
| 18 | 20 | extern const struct ieee80211_ops rtw89_ops; |
| 19 | 21 | |
| @@ -789,6 +791,7 @@ enum rtw89_phy_idx { · 769 unmodified lines | ||
| 789 | 791 | |
| 790 | 792 | enum rtw89_sub_entity_idx { |
| 791 | 793 | RTW89_SUB_ENTITY_0 = 0, |
| 794 | + RTW89_SUB_ENTITY_1 = 1, | |
| 792 | 795 | |
| 793 | 796 | NUM_OF_RTW89_SUB_ENTITY, |
| 794 | 797 | RTW89_SUB_ENTITY_IDLE = NUM_OF_RTW89_SUB_ENTITY, |
| @@ -900,6 +903,7 @@ struct rtw89_chan { · 105 unmodified lines | ||
| 900 | 903 | struct rtw89_chan_rcd { |
| 901 | 904 | u8 prev_primary_channel; |
| 902 | 905 | enum rtw89_band prev_band_type; |
| 906 | + bool band_changed; | |
| 903 | 907 | }; |
| 904 | 908 | |
| 905 | 909 | struct rtw89_channel_help_params { |
| @@ -2656,6 +2660,17 @@ struct rtw89_btc { · 1750 unmodified lines | ||
| 2656 | 2660 | bool lps; |
| 2657 | 2661 | }; |
| 2658 | 2662 | |
| 2663 | +enum rtw89_btc_hmsg { | |
| 2664 | + RTW89_BTC_HMSG_TMR_EN = 0x0, | |
| 2665 | + RTW89_BTC_HMSG_BT_REG_READBACK = 0x1, | |
| 2666 | + RTW89_BTC_HMSG_SET_BT_REQ_SLOT = 0x2, | |
| 2667 | + RTW89_BTC_HMSG_FW_EV = 0x3, | |
| 2668 | + RTW89_BTC_HMSG_BT_LINK_CHG = 0x4, | |
| 2669 | + RTW89_BTC_HMSG_SET_BT_REQ_STBC = 0x5, | |
| 2670 | + | |
| 2671 | + NUM_OF_RTW89_BTC_HMSG, | |
| 2672 | +}; | |
| 2673 | + | |
| 2659 | 2674 | enum rtw89_ra_mode { |
| 2660 | 2675 | RTW89_RA_MODE_CCK = BIT(0), |
| 2661 | 2676 | RTW89_RA_MODE_OFDM = BIT(1), |
| @@ -2885,6 +2900,32 @@ struct rtw89_roc { · 223 unmodified lines | ||
| 2885 | 2900 | |
| 2886 | 2901 | #define RTW89_P2P_MAX_NOA_NUM 2 |
| 2887 | 2902 | |
| 2903 | +struct rtw89_p2p_ie_head { | |
| 2904 | + u8 eid; | |
| 2905 | + u8 ie_len; | |
| 2906 | + u8 oui[3]; | |
| 2907 | + u8 oui_type; | |
| 2908 | +} __packed; | |
| 2909 | + | |
| 2910 | +struct rtw89_noa_attr_head { | |
| 2911 | + u8 attr_type; | |
| 2912 | + __le16 attr_len; | |
| 2913 | + u8 index; | |
| 2914 | + u8 oppps_ctwindow; | |
| 2915 | +} __packed; | |
| 2916 | + | |
| 2917 | +struct rtw89_p2p_noa_ie { | |
| 2918 | + struct rtw89_p2p_ie_head p2p_head; | |
| 2919 | + struct rtw89_noa_attr_head noa_head; | |
| 2920 | + struct ieee80211_p2p_noa_desc noa_desc[RTW89_P2P_MAX_NOA_NUM]; | |
| 2921 | +} __packed; | |
| 2922 | + | |
| 2923 | +struct rtw89_p2p_noa_setter { | |
| 2924 | + struct rtw89_p2p_noa_ie ie; | |
| 2925 | + u8 noa_count; | |
| 2926 | + u8 noa_index; | |
| 2927 | +}; | |
| 2928 | + | |
| 2888 | 2929 | struct rtw89_vif { |
| 2889 | 2930 | struct list_head list; |
| 2890 | 2931 | struct rtw89_dev *rtwdev; |
| @@ -2927,6 +2968,7 @@ struct rtw89_vif { · 36 unmodified lines | ||
| 2927 | 2968 | struct cfg80211_scan_request *scan_req; |
| 2928 | 2969 | struct ieee80211_scan_ies *scan_ies; |
| 2929 | 2970 | struct list_head general_pkt_list; |
| 2971 | + struct rtw89_p2p_noa_setter p2p_noa; | |
| 2930 | 2972 | }; |
| 2931 | 2973 | |
| 2932 | 2974 | enum rtw89_lv1_rcvy_step { |
| @@ -3339,6 +3381,10 @@ struct rtw89_dig_regs { · 406 unmodified lines | ||
| 3339 | 3381 | u32 seg0_pd_reg; |
| 3340 | 3382 | u32 pd_lower_bound_mask; |
| 3341 | 3383 | u32 pd_spatial_reuse_en; |
| 3384 | + u32 bmode_pd_reg; | |
| 3385 | + u32 bmode_cca_rssi_limit_en; | |
| 3386 | + u32 bmode_pd_lower_bound_reg; | |
| 3387 | + u32 bmode_rssi_nocca_low_th_mask; | |
| 3342 | 3388 | struct rtw89_reg_def p0_lna_init; |
| 3343 | 3389 | struct rtw89_reg_def p1_lna_init; |
| 3344 | 3390 | struct rtw89_reg_def p0_tia_init; |
| @@ -3375,10 +3421,28 @@ struct rtw89_antdiv_info { · 30 unmodified lines | ||
| 3375 | 3421 | bool get_stats; |
| 3376 | 3422 | }; |
| 3377 | 3423 | |
| 3424 | +enum rtw89_chanctx_state { | |
| 3425 | + RTW89_CHANCTX_STATE_MCC_START, | |
| 3426 | + RTW89_CHANCTX_STATE_MCC_STOP, | |
| 3427 | +}; | |
| 3428 | + | |
| 3429 | +enum rtw89_chanctx_callbacks { | |
| 3430 | + RTW89_CHANCTX_CALLBACK_PLACEHOLDER, | |
| 3431 | + | |
| 3432 | + NUM_OF_RTW89_CHANCTX_CALLBACKS, | |
| 3433 | +}; | |
| 3434 | + | |
| 3435 | +struct rtw89_chanctx_listener { | |
| 3436 | + void (*callbacks[NUM_OF_RTW89_CHANCTX_CALLBACKS]) | |
| 3437 | + (struct rtw89_dev *rtwdev, enum rtw89_chanctx_state state); | |
| 3438 | +}; | |
| 3439 | + | |
| 3378 | 3440 | struct rtw89_chip_info { |
| 3379 | 3441 | enum rtw89_core_chip_id chip_id; |
| 3380 | 3442 | enum rtw89_chip_gen chip_gen; |
| 3381 | 3443 | const struct rtw89_chip_ops *ops; |
| 3444 | + const struct rtw89_mac_gen_def *mac_def; | |
| 3445 | + const struct rtw89_phy_gen_def *phy_def; | |
| 3382 | 3446 | const char *fw_basename; |
| 3383 | 3447 | u8 fw_format_max; |
| 3384 | 3448 | bool try_ce_fw; |
| @@ -3434,6 +3498,7 @@ struct rtw89_chip_info { · 49 unmodified lines | ||
| 3434 | 3498 | /* NULL if no rfe-specific, or a null-terminated array by rfe_parms */ |
| 3435 | 3499 | const struct rtw89_rfe_parms_conf *rfe_parms_conf; |
| 3436 | 3500 | const struct rtw89_rfe_parms *dflt_parms; |
| 3501 | + const struct rtw89_chanctx_listener *chanctx_listener; | |
| 3437 | 3502 | |
| 3438 | 3503 | u8 txpwr_factor_rf; |
| 3439 | 3504 | u8 txpwr_factor_mac; |
| @@ -3690,12 +3755,34 @@ struct rtw89_sar_info { · 250 unmodified lines | ||
| 3690 | 3755 | }; |
| 3691 | 3756 | }; |
| 3692 | 3757 | |
| 3758 | +enum rtw89_tas_state { | |
| 3759 | + RTW89_TAS_STATE_DPR_OFF, | |
| 3760 | + RTW89_TAS_STATE_DPR_ON, | |
| 3761 | + RTW89_TAS_STATE_DPR_FORBID, | |
| 3762 | +}; | |
| 3763 | + | |
| 3764 | +#define RTW89_TAS_MAX_WINDOW 50 | |
| 3765 | +struct rtw89_tas_info { | |
| 3766 | + s16 txpwr_history[RTW89_TAS_MAX_WINDOW]; | |
| 3767 | + s32 total_txpwr; | |
| 3768 | + u8 cur_idx; | |
| 3769 | + s8 dpr_gap; | |
| 3770 | + s8 delta; | |
| 3771 | + enum rtw89_tas_state state; | |
| 3772 | + bool enable; | |
| 3773 | +}; | |
| 3774 | + | |
| 3693 | 3775 | struct rtw89_chanctx_cfg { |
| 3694 | 3776 | enum rtw89_sub_entity_idx idx; |
| 3695 | 3777 | }; |
| 3696 | 3778 | |
| 3697 | 3779 | enum rtw89_entity_mode { |
| 3698 | 3780 | RTW89_ENTITY_MODE_SCC, |
| 3781 | + RTW89_ENTITY_MODE_MCC_PREPARE, | |
| 3782 | + RTW89_ENTITY_MODE_MCC, | |
| 3783 | + | |
| 3784 | + NUM_OF_RTW89_ENTITY_MODE, | |
| 3785 | + RTW89_ENTITY_MODE_INVALID = NUM_OF_RTW89_ENTITY_MODE, | |
| 3699 | 3786 | }; |
| 3700 | 3787 | |
| 3701 | 3788 | struct rtw89_sub_entity { |
| @@ -4352,6 +4439,7 @@ struct rtw89_dev { · 650 unmodified lines | ||
| 4352 | 4439 | struct rtw89_antdiv_info antdiv; |
| 4353 | 4440 | |
| 4354 | 4441 | struct delayed_work track_work; |
| 4442 | + struct delayed_work chanctx_work; | |
| 4355 | 4443 | struct delayed_work coex_act1_work; |
| 4356 | 4444 | struct delayed_work coex_bt_devinfo_work; |
| 4357 | 4445 | struct delayed_work coex_rfk_chk_work; |
| @@ -4365,6 +4453,7 @@ struct rtw89_dev { · 7 unmodified lines | ||
| 4365 | 4453 | |
| 4366 | 4454 | struct rtw89_regulatory_info regulatory; |
| 4367 | 4455 | struct rtw89_sar_info sar; |
| 4456 | + struct rtw89_tas_info tas; | |
| 4368 | 4457 | |
| 4369 | 4458 | struct rtw89_btc btc; |
| 4370 | 4459 | enum rtw89_ps_mode ps_mode; |
| @@ -4900,6 +4989,18 @@ const struct rtw89_chan_rcd *rtw89_chan_rcd_get(struct rtw89_dev *rtwdev, · 529 unmodified lines | ||
| 4900 | 4989 | return &hal->sub[idx].rcd; |
| 4901 | 4990 | } |
| 4902 | 4991 | |
| 4992 | +static inline | |
| 4993 | +const struct rtw89_chan *rtw89_scan_chan_get(struct rtw89_dev *rtwdev) | |
| 4994 | +{ | |
| 4995 | + struct ieee80211_vif *vif = rtwdev->scan_info.scanning_vif; | |
| 4996 | + struct rtw89_vif *rtwvif = vif_to_rtwvif_safe(vif); | |
| 4997 | + | |
| 4998 | + if (rtwvif) | |
| 4999 | + return rtw89_chan_get(rtwdev, rtwvif->sub_entity_idx); | |
| 5000 | + else | |
| 5001 | + return rtw89_chan_get(rtwdev, RTW89_SUB_ENTITY_0); | |
| 5002 | +} | |
| 5003 | + | |
| 4903 | 5004 | static inline void rtw89_chip_fem_setup(struct rtw89_dev *rtwdev) |
| 4904 | 5005 | { |
| 4905 | 5006 | const struct rtw89_chip_info *chip = rtwdev->chip; |
| @@ -5273,6 +5374,8 @@ struct rtw89_dev *rtw89_alloc_ieee80211_hw(struct device *device, · 367 unmodified lines | ||
| 5273 | 5374 | void rtw89_free_ieee80211_hw(struct rtw89_dev *rtwdev); |
| 5274 | 5375 | void rtw89_core_set_chip_txpwr(struct rtw89_dev *rtwdev); |
| 5275 | 5376 | void rtw89_get_default_chandef(struct cfg80211_chan_def *chandef); |
| 5377 | +void rtw89_get_channel_params(const struct cfg80211_chan_def *chandef, | |
| 5378 | + struct rtw89_chan *chan); | |
| 5276 | 5379 | void rtw89_set_channel(struct rtw89_dev *rtwdev); |
| 5277 | 5380 | void rtw89_get_channel(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif, |
| 5278 | 5381 | struct rtw89_chan *chan); |
| @@ -5307,5 +5410,6 @@ void rtw89_core_scan_complete(struct rtw89_dev *rtwdev, · 28 unmodified lines | ||
| 5307 | 5410 | struct ieee80211_vif *vif, bool hw_scan); |
| 5308 | 5411 | void rtw89_reg_6ghz_power_recalc(struct rtw89_dev *rtwdev, |
| 5309 | 5412 | struct rtw89_vif *rtwvif, bool active); |
| 5413 | +void rtw89_core_ntfy_btc_event(struct rtw89_dev *rtwdev, enum rtw89_btc_hmsg event); | |
| 5310 | 5414 | |
| 5311 | 5415 | #endif |
| @@ -572,9 +572,9 @@ static int __print_txpwr_map(struct seq_file *m, struct rtw89_dev *rtwdev, · 571 unmodified lines | ||
| 572 | 572 | seq_puts(m, #_regd "\n"); \ |
| 573 | 573 | break |
| 574 | 574 | |
| 575 | −static void __print_regd(struct seq_file *m, struct rtw89_dev *rtwdev) | |
| 575 | +static void __print_regd(struct seq_file *m, struct rtw89_dev *rtwdev, | |
| 576 | + const struct rtw89_chan *chan) | |
| 576 | 577 | { |
| 577 | − const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, RTW89_SUB_ENTITY_0); | |
| 578 | 578 | u8 band = chan->band_type; |
| 579 | 579 | u8 regd = rtw89_regd_get(rtwdev, band); |
| 580 | 580 | |
| @@ -604,16 +604,21 @@ static int rtw89_debug_priv_txpwr_table_get(struct seq_file *m, void *v) · 23 unmodified lines | ||
| 604 | 604 | { |
| 605 | 605 | struct rtw89_debugfs_priv *debugfs_priv = m->private; |
| 606 | 606 | struct rtw89_dev *rtwdev = debugfs_priv->rtwdev; |
| 607 | + const struct rtw89_chan *chan; | |
| 607 | 608 | int ret = 0; |
| 608 | 609 | |
| 609 | 610 | mutex_lock(&rtwdev->mutex); |
| 610 | 611 | rtw89_leave_ps_mode(rtwdev); |
| 612 | + chan = rtw89_chan_get(rtwdev, RTW89_SUB_ENTITY_0); | |
| 611 | 613 | |
| 612 | 614 | seq_puts(m, "[Regulatory] "); |
| 613 | − __print_regd(m, rtwdev); | |
| 615 | + __print_regd(m, rtwdev, chan); | |
| 614 | 616 | |
| 615 | 617 | seq_puts(m, "[SAR]\n"); |
| 616 | − rtw89_print_sar(m, rtwdev); | |
| 618 | + rtw89_print_sar(m, rtwdev, chan->freq); | |
| 619 | + | |
| 620 | + seq_puts(m, "[TAS]\n"); | |
| 621 | + rtw89_print_tas(m, rtwdev); | |
| 617 | 622 | |
| 618 | 623 | seq_puts(m, "\n[TX power byrate]\n"); |
| 619 | 624 | ret = __print_txpwr_map(m, rtwdev, &__txpwr_map_byr); |
| @@ -790,6 +795,9 @@ static void rtw89_debug_dump_mac_mem(struct seq_file *m, · 170 unmodified lines | ||
| 790 | 795 | struct rtw89_dev *rtwdev, |
| 791 | 796 | u8 sel, u32 start_addr, u32 len) |
| 792 | 797 | { |
| 798 | + const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; | |
| 799 | + u32 filter_model_addr = mac->filter_model_addr; | |
| 800 | + u32 indir_access_addr = mac->indir_access_addr; | |
| 793 | 801 | u32 base_addr, start_page, residue; |
| 794 | 802 | u32 i, j, p, pages; |
| 795 | 803 | u32 dump_len, remain; |
| @@ -799,17 +807,17 @@ static void rtw89_debug_dump_mac_mem(struct seq_file *m, · 3 unmodified lines | ||
| 799 | 807 | pages = len / MAC_MEM_DUMP_PAGE_SIZE + 1; |
| 800 | 808 | start_page = start_addr / MAC_MEM_DUMP_PAGE_SIZE; |
| 801 | 809 | residue = start_addr % MAC_MEM_DUMP_PAGE_SIZE; |
| 802 | − base_addr = rtw89_mac_mem_base_addrs[sel]; | |
| 810 | + base_addr = mac->mem_base_addrs[sel]; | |
| 803 | 811 | base_addr += start_page * MAC_MEM_DUMP_PAGE_SIZE; |
| 804 | 812 | |
| 805 | 813 | for (p = 0; p < pages; p++) { |
| 806 | 814 | dump_len = min_t(u32, remain, MAC_MEM_DUMP_PAGE_SIZE); |
| 807 | − rtw89_write32(rtwdev, R_AX_FILTER_MODEL_ADDR, base_addr); | |
| 808 | − for (i = R_AX_INDIR_ACCESS_ENTRY + residue; | |
| 809 | − i < R_AX_INDIR_ACCESS_ENTRY + dump_len;) { | |
| 815 | + rtw89_write32(rtwdev, filter_model_addr, base_addr); | |
| 816 | + for (i = indir_access_addr + residue; | |
| 817 | + i < indir_access_addr + dump_len;) { | |
| 810 | 818 | seq_printf(m, "%08xh:", i); |
| 811 | 819 | for (j = 0; |
| 812 | − j < 4 && i < R_AX_INDIR_ACCESS_ENTRY + dump_len; | |
| 820 | + j < 4 && i < indir_access_addr + dump_len; | |
| 813 | 821 | j++, i += 4) { |
| 814 | 822 | val = rtw89_read32(rtwdev, i); |
| 815 | 823 | seq_printf(m, " %08x", val); |
| @@ -9,6 +9,7 @@ · 8 unmodified lines | ||
| 9 | 9 | #include "fw.h" |
| 10 | 10 | #include "mac.h" |
| 11 | 11 | #include "phy.h" |
| 12 | +#include "ps.h" | |
| 12 | 13 | #include "reg.h" |
| 13 | 14 | #include "util.h" |
| 14 | 15 | |
| @@ -1165,7 +1166,7 @@ void rtw89_fw_log_dump(struct rtw89_dev *rtwdev, u8 *buf, u32 len) · 1150 unmodified lines | ||
| 1165 | 1166 | return; |
| 1166 | 1167 | |
| 1167 | 1168 | plain_log: |
| 1168 | − rtw89_info(rtwdev, "C2H log: %*s", len, buf); | |
| 1169 | + rtw89_info(rtwdev, "C2H log: %.*s", len, buf); | |
| 1169 | 1170 | |
| 1170 | 1171 | } |
| 1171 | 1172 | |
| @@ -1758,7 +1759,8 @@ int rtw89_fw_h2c_assoc_cmac_tbl(struct rtw89_dev *rtwdev, · 586 unmodified lines | ||
| 1758 | 1759 | const struct rtw89_chip_info *chip = rtwdev->chip; |
| 1759 | 1760 | struct rtw89_sta *rtwsta = sta_to_rtwsta_safe(sta); |
| 1760 | 1761 | struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; |
| 1761 | − const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, RTW89_SUB_ENTITY_0); | |
| 1762 | + const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, | |
| 1763 | + rtwvif->sub_entity_idx); | |
| 1762 | 1764 | struct sk_buff *skb; |
| 1763 | 1765 | u8 pads[RTW89_PPE_BW_NUM]; |
| 1764 | 1766 | u8 mac_id = rtwsta ? rtwsta->mac_id : rtwvif->mac_id; |
| @@ -1915,12 +1917,15 @@ int rtw89_fw_h2c_update_beacon(struct rtw89_dev *rtwdev, · 150 unmodified lines | ||
| 1915 | 1917 | struct rtw89_vif *rtwvif) |
| 1916 | 1918 | { |
| 1917 | 1919 | struct ieee80211_vif *vif = rtwvif_to_vif(rtwvif); |
| 1918 | − const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, RTW89_SUB_ENTITY_0); | |
| 1920 | + const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, | |
| 1921 | + rtwvif->sub_entity_idx); | |
| 1919 | 1922 | struct sk_buff *skb; |
| 1920 | 1923 | struct sk_buff *skb_beacon; |
| 1921 | 1924 | u16 tim_offset; |
| 1922 | 1925 | int bcn_total_len; |
| 1923 | 1926 | u16 beacon_rate; |
| 1927 | + void *noa_data; | |
| 1928 | + u8 noa_len; | |
| 1924 | 1929 | int ret; |
| 1925 | 1930 | |
| 1926 | 1931 | if (vif->p2p) |
| @@ -1937,6 +1942,13 @@ int rtw89_fw_h2c_update_beacon(struct rtw89_dev *rtwdev, · 10 unmodified lines | ||
| 1937 | 1942 | return -ENOMEM; |
| 1938 | 1943 | } |
| 1939 | 1944 | |
| 1945 | + noa_len = rtw89_p2p_noa_fetch(rtwvif, &noa_data); | |
| 1946 | + if (noa_len && | |
| 1947 | + (noa_len <= skb_tailroom(skb_beacon) || | |
| 1948 | + pskb_expand_head(skb_beacon, 0, noa_len, GFP_KERNEL) == 0)) { | |
| 1949 | + skb_put_data(skb_beacon, noa_data, noa_len); | |
| 1950 | + } | |
| 1951 | + | |
| 1940 | 1952 | bcn_total_len = H2C_BCN_BASE_LEN + skb_beacon->len; |
| 1941 | 1953 | skb = rtw89_fw_h2c_alloc_skb_with_hdr(rtwdev, bcn_total_len); |
| 1942 | 1954 | if (!skb) { |
| @@ -3851,6 +3863,7 @@ void rtw89_hw_scan_start(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif, · 1908 unmodified lines | ||
| 3851 | 3863 | struct ieee80211_scan_request *scan_req) |
| 3852 | 3864 | { |
| 3853 | 3865 | struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; |
| 3866 | + const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; | |
| 3854 | 3867 | struct cfg80211_scan_request *req = &scan_req->req; |
| 3855 | 3868 | u32 rx_fltr = rtwdev->hal.rx_fltr; |
| 3856 | 3869 | u8 mac_addr[ETH_ALEN]; |
| @@ -3873,7 +3886,7 @@ void rtw89_hw_scan_start(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif, · 16 unmodified lines | ||
| 3873 | 3886 | rx_fltr &= ~B_AX_A_BC; |
| 3874 | 3887 | rx_fltr &= ~B_AX_A_A1_MATCH; |
| 3875 | 3888 | rtw89_write32_mask(rtwdev, |
| 3876 | − rtw89_mac_reg_by_idx(R_AX_RX_FLTR_OPT, RTW89_MAC_0), | |
| 3889 | + rtw89_mac_reg_by_idx(rtwdev, mac->rx_fltr, RTW89_MAC_0), | |
| 3877 | 3890 | B_AX_RX_FLTR_CFG_MASK, |
| 3878 | 3891 | rx_fltr); |
| 3879 | 3892 | } |
| @@ -3881,6 +3894,7 @@ void rtw89_hw_scan_start(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif, · 1 unmodified line | ||
| 3881 | 3894 | void rtw89_hw_scan_complete(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif, |
| 3882 | 3895 | bool aborted) |
| 3883 | 3896 | { |
| 3897 | + const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; | |
| 3884 | 3898 | struct rtw89_hw_scan_info *scan_info = &rtwdev->scan_info; |
| 3885 | 3899 | struct cfg80211_scan_info info = { |
| 3886 | 3900 | .aborted = aborted, |
| @@ -3891,7 +3905,7 @@ void rtw89_hw_scan_complete(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif, · 4 unmodified lines | ||
| 3891 | 3905 | return; |
| 3892 | 3906 | |
| 3893 | 3907 | rtw89_write32_mask(rtwdev, |
| 3894 | − rtw89_mac_reg_by_idx(R_AX_RX_FLTR_OPT, RTW89_MAC_0), | |
| 3908 | + rtw89_mac_reg_by_idx(rtwdev, mac->rx_fltr, RTW89_MAC_0), | |
| 3895 | 3909 | B_AX_RX_FLTR_CFG_MASK, |
| 3896 | 3910 | rtwdev->hal.rx_fltr); |
| 3897 | 3911 | |
| @@ -12,7 +12,7 @@ · 11 unmodified lines | ||
| 12 | 12 | #include "reg.h" |
| 13 | 13 | #include "util.h" |
| 14 | 14 | |
| 15 | −const u32 rtw89_mac_mem_base_addrs[RTW89_MAC_MEM_NUM] = { | |
| 15 | +static const u32 rtw89_mac_mem_base_addrs_ax[RTW89_MAC_MEM_NUM] = { | |
| 16 | 16 | [RTW89_MAC_MEM_AXIDMA] = AXIDMA_BASE_ADDR, |
| 17 | 17 | [RTW89_MAC_MEM_SHARED_BUF] = SHARED_BUF_BASE_ADDR, |
| 18 | 18 | [RTW89_MAC_MEM_DMAC_TBL] = DMAC_TBL_BASE_ADDR, |
| @@ -39,19 +39,21 @@ const u32 rtw89_mac_mem_base_addrs[RTW89_MAC_MEM_NUM] = { · 20 unmodified lines | ||
| 39 | 39 | static void rtw89_mac_mem_write(struct rtw89_dev *rtwdev, u32 offset, |
| 40 | 40 | u32 val, enum rtw89_mac_mem_sel sel) |
| 41 | 41 | { |
| 42 | − u32 addr = rtw89_mac_mem_base_addrs[sel] + offset; | |
| 42 | + const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; | |
| 43 | + u32 addr = mac->mem_base_addrs[sel] + offset; | |
| 43 | 44 | |
| 44 | − rtw89_write32(rtwdev, R_AX_FILTER_MODEL_ADDR, addr); | |
| 45 | − rtw89_write32(rtwdev, R_AX_INDIR_ACCESS_ENTRY, val); | |
| 45 | + rtw89_write32(rtwdev, mac->filter_model_addr, addr); | |
| 46 | + rtw89_write32(rtwdev, mac->indir_access_addr, val); | |
| 46 | 47 | } |
| 47 | 48 | |
| 48 | 49 | static u32 rtw89_mac_mem_read(struct rtw89_dev *rtwdev, u32 offset, |
| 49 | 50 | enum rtw89_mac_mem_sel sel) |
| 50 | 51 | { |
| 51 | − u32 addr = rtw89_mac_mem_base_addrs[sel] + offset; | |
| 52 | + const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; | |
| 53 | + u32 addr = mac->mem_base_addrs[sel] + offset; | |
| 52 | 54 | |
| 53 | − rtw89_write32(rtwdev, R_AX_FILTER_MODEL_ADDR, addr); | |
| 54 | − return rtw89_read32(rtwdev, R_AX_INDIR_ACCESS_ENTRY); | |
| 55 | + rtw89_write32(rtwdev, mac->filter_model_addr, addr); | |
| 56 | + return rtw89_read32(rtwdev, mac->indir_access_addr); | |
| 55 | 57 | } |
| 56 | 58 | |
| 57 | 59 | int rtw89_mac_check_mac_en(struct rtw89_dev *rtwdev, u8 mac_idx, |
| @@ -2082,7 +2084,7 @@ static int addr_cam_init(struct rtw89_dev *rtwdev, u8 mac_idx) · 2024 unmodified lines | ||
| 2082 | 2084 | if (ret) |
| 2083 | 2085 | return ret; |
| 2084 | 2086 | |
| 2085 | − reg = rtw89_mac_reg_by_idx(R_AX_ADDR_CAM_CTRL, mac_idx); | |
| 2087 | + reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_ADDR_CAM_CTRL, mac_idx); | |
| 2086 | 2088 | |
| 2087 | 2089 | val = rtw89_read32(rtwdev, reg); |
| 2088 | 2090 | val |= u32_encode_bits(0x7f, B_AX_ADDR_CAM_RANGE_MASK) | |
| @@ -2109,7 +2111,7 @@ static int scheduler_init(struct rtw89_dev *rtwdev, u8 mac_idx) · 20 unmodified lines | ||
| 2109 | 2111 | if (ret) |
| 2110 | 2112 | return ret; |
| 2111 | 2113 | |
| 2112 | − reg = rtw89_mac_reg_by_idx(R_AX_PREBKF_CFG_1, mac_idx); | |
| 2114 | + reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_PREBKF_CFG_1, mac_idx); | |
| 2113 | 2115 | if (rtwdev->chip->chip_id == RTL8852C) |
| 2114 | 2116 | rtw89_write32_mask(rtwdev, reg, B_AX_SIFS_MACTXEN_T1_MASK, |
| 2115 | 2117 | SIFS_MACTXEN_T1_V1); |
| @@ -2118,14 +2120,14 @@ static int scheduler_init(struct rtw89_dev *rtwdev, u8 mac_idx) · 2 unmodified lines | ||
| 2118 | 2120 | SIFS_MACTXEN_T1); |
| 2119 | 2121 | |
| 2120 | 2122 | if (rtwdev->chip->chip_id == RTL8852B || rtwdev->chip->chip_id == RTL8851B) { |
| 2121 | − reg = rtw89_mac_reg_by_idx(R_AX_SCH_EXT_CTRL, mac_idx); | |
| 2123 | + reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_SCH_EXT_CTRL, mac_idx); | |
| 2122 | 2124 | rtw89_write32_set(rtwdev, reg, B_AX_PORT_RST_TSF_ADV); |
| 2123 | 2125 | } |
| 2124 | 2126 | |
| 2125 | − reg = rtw89_mac_reg_by_idx(R_AX_CCA_CFG_0, mac_idx); | |
| 2127 | + reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_CCA_CFG_0, mac_idx); | |
| 2126 | 2128 | rtw89_write32_clr(rtwdev, reg, B_AX_BTCCA_EN); |
| 2127 | 2129 | |
| 2128 | − reg = rtw89_mac_reg_by_idx(R_AX_PREBKF_CFG_0, mac_idx); | |
| 2130 | + reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_PREBKF_CFG_0, mac_idx); | |
| 2129 | 2131 | if (rtwdev->chip->chip_id == RTL8852C) { |
| 2130 | 2132 | val = rtw89_read32_mask(rtwdev, R_AX_SEC_ENG_CTRL, |
| 2131 | 2133 | B_AX_TX_PARTIAL_MODE); |
| @@ -2165,13 +2167,13 @@ int rtw89_mac_typ_fltr_opt(struct rtw89_dev *rtwdev, · 33 unmodified lines | ||
| 2165 | 2167 | |
| 2166 | 2168 | switch (type) { |
| 2167 | 2169 | case RTW89_MGNT: |
| 2168 | − reg = rtw89_mac_reg_by_idx(R_AX_MGNT_FLTR, mac_idx); | |
| 2170 | + reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_MGNT_FLTR, mac_idx); | |
| 2169 | 2171 | break; |
| 2170 | 2172 | case RTW89_CTRL: |
| 2171 | − reg = rtw89_mac_reg_by_idx(R_AX_CTRL_FLTR, mac_idx); | |
| 2173 | + reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_CTRL_FLTR, mac_idx); | |
| 2172 | 2174 | break; |
| 2173 | 2175 | case RTW89_DATA: |
| 2174 | − reg = rtw89_mac_reg_by_idx(R_AX_DATA_FLTR, mac_idx); | |
| 2176 | + reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_DATA_FLTR, mac_idx); | |
| 2175 | 2177 | break; |
| 2176 | 2178 | default: |
| 2177 | 2179 | rtw89_err(rtwdev, "[ERR]set rx filter type err\n"); |
| @@ -2202,9 +2204,9 @@ static int rx_fltr_init(struct rtw89_dev *rtwdev, u8 mac_idx) · 24 unmodified lines | ||
| 2202 | 2204 | B_AX_LSIG_PARITY_CHK_EN | B_AX_SIGA_CRC_CHK | |
| 2203 | 2205 | B_AX_VHT_SU_SIGB_CRC_CHK | B_AX_VHT_MU_SIGB_CRC_CHK | |
| 2204 | 2206 | B_AX_HE_SIGB_CRC_CHK; |
| 2205 | − rtw89_write32(rtwdev, rtw89_mac_reg_by_idx(R_AX_RX_FLTR_OPT, mac_idx), | |
| 2207 | + rtw89_write32(rtwdev, rtw89_mac_reg_by_idx(rtwdev, R_AX_RX_FLTR_OPT, mac_idx), | |
| 2206 | 2208 | mac_ftlr); |
| 2207 | − rtw89_write16(rtwdev, rtw89_mac_reg_by_idx(R_AX_PLCP_HDR_FLTR, mac_idx), | |
| 2209 | + rtw89_write16(rtwdev, rtw89_mac_reg_by_idx(rtwdev, R_AX_PLCP_HDR_FLTR, mac_idx), | |
| 2208 | 2210 | plcp_ftlr); |
| 2209 | 2211 | |
| 2210 | 2212 | return 0; |
| @@ -2224,20 +2226,20 @@ static void _patch_dis_resp_chk(struct rtw89_dev *rtwdev, u8 mac_idx) · 13 unmodified lines | ||
| 2224 | 2226 | switch (rtwdev->chip->chip_id) { |
| 2225 | 2227 | case RTL8852A: |
| 2226 | 2228 | case RTL8852B: |
| 2227 | − reg = rtw89_mac_reg_by_idx(R_AX_RSP_CHK_SIG, mac_idx); | |
| 2229 | + reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_RSP_CHK_SIG, mac_idx); | |
| 2228 | 2230 | val32 = rtw89_read32(rtwdev, reg) & ~b_rsp_chk_nav; |
| 2229 | 2231 | rtw89_write32(rtwdev, reg, val32); |
| 2230 | 2232 | |
| 2231 | − reg = rtw89_mac_reg_by_idx(R_AX_TRXPTCL_RESP_0, mac_idx); | |
| 2233 | + reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_TRXPTCL_RESP_0, mac_idx); | |
| 2232 | 2234 | val32 = rtw89_read32(rtwdev, reg) & ~b_rsp_chk_cca; |
| 2233 | 2235 | rtw89_write32(rtwdev, reg, val32); |
| 2234 | 2236 | break; |
| 2235 | 2237 | default: |
| 2236 | − reg = rtw89_mac_reg_by_idx(R_AX_RSP_CHK_SIG, mac_idx); | |
| 2238 | + reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_RSP_CHK_SIG, mac_idx); | |
| 2237 | 2239 | val32 = rtw89_read32(rtwdev, reg) | b_rsp_chk_nav; |
| 2238 | 2240 | rtw89_write32(rtwdev, reg, val32); |
| 2239 | 2241 | |
| 2240 | − reg = rtw89_mac_reg_by_idx(R_AX_TRXPTCL_RESP_0, mac_idx); | |
| 2242 | + reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_TRXPTCL_RESP_0, mac_idx); | |
| 2241 | 2243 | val32 = rtw89_read32(rtwdev, reg) | b_rsp_chk_cca; |
| 2242 | 2244 | rtw89_write32(rtwdev, reg, val32); |
| 2243 | 2245 | break; |
| @@ -2253,7 +2255,7 @@ static int cca_ctrl_init(struct rtw89_dev *rtwdev, u8 mac_idx) · 9 unmodified lines | ||
| 2253 | 2255 | if (ret) |
| 2254 | 2256 | return ret; |
| 2255 | 2257 | |
| 2256 | − reg = rtw89_mac_reg_by_idx(R_AX_CCA_CONTROL, mac_idx); | |
| 2258 | + reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_CCA_CONTROL, mac_idx); | |
| 2257 | 2259 | val = rtw89_read32(rtwdev, reg); |
| 2258 | 2260 | val |= (B_AX_TB_CHK_BASIC_NAV | B_AX_TB_CHK_BTCCA | |
| 2259 | 2261 | B_AX_TB_CHK_EDCCA | B_AX_TB_CHK_CCA_P20 | |
| @@ -2294,7 +2296,7 @@ static int spatial_reuse_init(struct rtw89_dev *rtwdev, u8 mac_idx) · 34 unmodified lines | ||
| 2294 | 2296 | ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); |
| 2295 | 2297 | if (ret) |
| 2296 | 2298 | return ret; |
| 2297 | − reg = rtw89_mac_reg_by_idx(R_AX_RX_SR_CTRL, mac_idx); | |
| 2299 | + reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_RX_SR_CTRL, mac_idx); | |
| 2298 | 2300 | rtw89_write8_clr(rtwdev, reg, B_AX_SR_EN); |
| 2299 | 2301 | |
| 2300 | 2302 | return 0; |
| @@ -2309,13 +2311,13 @@ static int tmac_init(struct rtw89_dev *rtwdev, u8 mac_idx) · 8 unmodified lines | ||
| 2309 | 2311 | if (ret) |
| 2310 | 2312 | return ret; |
| 2311 | 2313 | |
| 2312 | − reg = rtw89_mac_reg_by_idx(R_AX_MAC_LOOPBACK, mac_idx); | |
| 2314 | + reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_MAC_LOOPBACK, mac_idx); | |
| 2313 | 2315 | rtw89_write32_clr(rtwdev, reg, B_AX_MACLBK_EN); |
| 2314 | 2316 | |
| 2315 | − reg = rtw89_mac_reg_by_idx(R_AX_TCR0, mac_idx); | |
| 2317 | + reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_TCR0, mac_idx); | |
| 2316 | 2318 | rtw89_write32_mask(rtwdev, reg, B_AX_TCR_UDF_THSD_MASK, TCR_UDF_THSD); |
| 2317 | 2319 | |
| 2318 | − reg = rtw89_mac_reg_by_idx(R_AX_TXD_FIFO_CTRL, mac_idx); | |
| 2320 | + reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_TXD_FIFO_CTRL, mac_idx); | |
| 2319 | 2321 | rtw89_write32_mask(rtwdev, reg, B_AX_TXDFIFO_HIGH_MCS_THRE_MASK, TXDFIFO_HIGH_MCS_THRE); |
| 2320 | 2322 | rtw89_write32_mask(rtwdev, reg, B_AX_TXDFIFO_LOW_MCS_THRE_MASK, TXDFIFO_LOW_MCS_THRE); |
| 2321 | 2323 | |
| @@ -2333,7 +2335,7 @@ static int trxptcl_init(struct rtw89_dev *rtwdev, u8 mac_idx) · 11 unmodified lines | ||
| 2333 | 2335 | if (ret) |
| 2334 | 2336 | return ret; |
| 2335 | 2337 | |
| 2336 | − reg = rtw89_mac_reg_by_idx(R_AX_TRXPTCL_RESP_0, mac_idx); | |
| 2338 | + reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_TRXPTCL_RESP_0, mac_idx); | |
| 2337 | 2339 | val = rtw89_read32(rtwdev, reg); |
| 2338 | 2340 | val &= ~B_AX_WMAC_SPEC_SIFS_CCK_MASK; |
| 2339 | 2341 | val |= FIELD_PREP(B_AX_WMAC_SPEC_SIFS_CCK_MASK, WMAC_SPEC_SIFS_CCK); |
| @@ -2353,12 +2355,12 @@ static int trxptcl_init(struct rtw89_dev *rtwdev, u8 mac_idx) · 13 unmodified lines | ||
| 2353 | 2355 | val |= FIELD_PREP(B_AX_WMAC_SPEC_SIFS_OFDM_MASK, sifs); |
| 2354 | 2356 | rtw89_write32(rtwdev, reg, val); |
| 2355 | 2357 | |
| 2356 | − reg = rtw89_mac_reg_by_idx(R_AX_RXTRIG_TEST_USER_2, mac_idx); | |
| 2358 | + reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_RXTRIG_TEST_USER_2, mac_idx); | |
| 2357 | 2359 | rtw89_write32_set(rtwdev, reg, B_AX_RXTRIG_FCSCHK_EN); |
| 2358 | 2360 | |
| 2359 | − reg = rtw89_mac_reg_by_idx(rrsr->ref_rate.addr, mac_idx); | |
| 2361 | + reg = rtw89_mac_reg_by_idx(rtwdev, rrsr->ref_rate.addr, mac_idx); | |
| 2360 | 2362 | rtw89_write32_mask(rtwdev, reg, rrsr->ref_rate.mask, rrsr->ref_rate.data); |
| 2361 | − reg = rtw89_mac_reg_by_idx(rrsr->rsc.addr, mac_idx); | |
| 2363 | + reg = rtw89_mac_reg_by_idx(rtwdev, rrsr->rsc.addr, mac_idx); | |
| 2362 | 2364 | rtw89_write32_mask(rtwdev, reg, rrsr->rsc.mask, rrsr->rsc.data); |
| 2363 | 2365 | |
| 2364 | 2366 | return 0; |
| @@ -2397,10 +2399,10 @@ static int rmac_init(struct rtw89_dev *rtwdev, u8 mac_idx) · 32 unmodified lines | ||
| 2397 | 2399 | if (mac_idx == RTW89_MAC_0) |
| 2398 | 2400 | rst_bacam(rtwdev); |
| 2399 | 2401 | |
| 2400 | − reg = rtw89_mac_reg_by_idx(R_AX_RESPBA_CAM_CTRL, mac_idx); | |
| 2402 | + reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_RESPBA_CAM_CTRL, mac_idx); | |
| 2401 | 2403 | rtw89_write8_set(rtwdev, reg, B_AX_SSN_SEL); |
| 2402 | 2404 | |
| 2403 | − reg = rtw89_mac_reg_by_idx(R_AX_DLK_PROTECT_CTL, mac_idx); | |
| 2405 | + reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_DLK_PROTECT_CTL, mac_idx); | |
| 2404 | 2406 | val = rtw89_read16(rtwdev, reg); |
| 2405 | 2407 | val = u16_replace_bits(val, TRXCFG_RMAC_DATA_TO, |
| 2406 | 2408 | B_AX_RX_DLK_DATA_TIME_MASK); |
| @@ -2408,10 +2410,10 @@ static int rmac_init(struct rtw89_dev *rtwdev, u8 mac_idx) · 1 unmodified line | ||
| 2408 | 2410 | B_AX_RX_DLK_CCA_TIME_MASK); |
| 2409 | 2411 | rtw89_write16(rtwdev, reg, val); |
| 2410 | 2412 | |
| 2411 | − reg = rtw89_mac_reg_by_idx(R_AX_RCR, mac_idx); | |
| 2413 | + reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_RCR, mac_idx); | |
| 2412 | 2414 | rtw89_write8_mask(rtwdev, reg, B_AX_CH_EN_MASK, 0x1); |
| 2413 | 2415 | |
| 2414 | − reg = rtw89_mac_reg_by_idx(R_AX_RX_FLTR_OPT, mac_idx); | |
| 2416 | + reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_RX_FLTR_OPT, mac_idx); | |
| 2415 | 2417 | if (mac_idx == RTW89_MAC_0) |
| 2416 | 2418 | rx_qta = rtwdev->mac.dle_info.c0_rx_qta; |
| 2417 | 2419 | else |
| @@ -2425,13 +2427,13 @@ static int rmac_init(struct rtw89_dev *rtwdev, u8 mac_idx) · 7 unmodified lines | ||
| 2425 | 2427 | if (rtwdev->chip->chip_id == RTL8852A && |
| 2426 | 2428 | rtwdev->hal.cv == CHIP_CBV) { |
| 2427 | 2429 | rtw89_write16_mask(rtwdev, |
| 2428 | − rtw89_mac_reg_by_idx(R_AX_DLK_PROTECT_CTL, mac_idx), | |
| 2430 | + rtw89_mac_reg_by_idx(rtwdev, R_AX_DLK_PROTECT_CTL, mac_idx), | |
| 2429 | 2431 | B_AX_RX_DLK_CCA_TIME_MASK, 0); |
| 2430 | − rtw89_write16_set(rtwdev, rtw89_mac_reg_by_idx(R_AX_RCR, mac_idx), | |
| 2432 | + rtw89_write16_set(rtwdev, rtw89_mac_reg_by_idx(rtwdev, R_AX_RCR, mac_idx), | |
| 2431 | 2433 | BIT(12)); |
| 2432 | 2434 | } |
| 2433 | 2435 | |
| 2434 | − reg = rtw89_mac_reg_by_idx(R_AX_PLCP_HDR_FLTR, mac_idx); | |
| 2436 | + reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_PLCP_HDR_FLTR, mac_idx); | |
| 2435 | 2437 | rtw89_write8_clr(rtwdev, reg, B_AX_VHT_SU_SIGB_CRC_CHK); |
| 2436 | 2438 | |
| 2437 | 2439 | return ret; |
| @@ -2447,7 +2449,7 @@ static int cmac_com_init(struct rtw89_dev *rtwdev, u8 mac_idx) · 9 unmodified lines | ||
| 2447 | 2449 | if (ret) |
| 2448 | 2450 | return ret; |
| 2449 | 2451 | |
| 2450 | − reg = rtw89_mac_reg_by_idx(R_AX_TX_SUB_CARRIER_VALUE, mac_idx); | |
| 2452 | + reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_TX_SUB_CARRIER_VALUE, mac_idx); | |
| 2451 | 2453 | val = rtw89_read32(rtwdev, reg); |
| 2452 | 2454 | val = u32_replace_bits(val, 0, B_AX_TXSC_20M_MASK); |
| 2453 | 2455 | val = u32_replace_bits(val, 0, B_AX_TXSC_40M_MASK); |
| @@ -2455,7 +2457,7 @@ static int cmac_com_init(struct rtw89_dev *rtwdev, u8 mac_idx) · 1 unmodified line | ||
| 2455 | 2457 | rtw89_write32(rtwdev, reg, val); |
| 2456 | 2458 | |
| 2457 | 2459 | if (chip_id == RTL8852A || chip_id == RTL8852B) { |
| 2458 | − reg = rtw89_mac_reg_by_idx(R_AX_PTCL_RRSR1, mac_idx); | |
| 2460 | + reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_PTCL_RRSR1, mac_idx); | |
| 2459 | 2461 | rtw89_write32_mask(rtwdev, reg, B_AX_RRSR_RATE_EN_MASK, RRSR_OFDM_CCK_EN); |
| 2460 | 2462 | } |
| 2461 | 2463 | |
| @@ -2485,7 +2487,7 @@ static int ptcl_init(struct rtw89_dev *rtwdev, u8 mac_idx) · 23 unmodified lines | ||
| 2485 | 2487 | return ret; |
| 2486 | 2488 | |
| 2487 | 2489 | if (rtwdev->hci.type == RTW89_HCI_TYPE_PCIE) { |
| 2488 | − reg = rtw89_mac_reg_by_idx(R_AX_SIFS_SETTING, mac_idx); | |
| 2490 | + reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_SIFS_SETTING, mac_idx); | |
| 2489 | 2491 | val = rtw89_read32(rtwdev, reg); |
| 2490 | 2492 | val = u32_replace_bits(val, S_AX_CTS2S_TH_1K, |
| 2491 | 2493 | B_AX_HW_CTS2SELF_PKT_LEN_TH_MASK); |
| @@ -2494,7 +2496,7 @@ static int ptcl_init(struct rtw89_dev *rtwdev, u8 mac_idx) · 2 unmodified lines | ||
| 2494 | 2496 | val |= B_AX_HW_CTS2SELF_EN; |
| 2495 | 2497 | rtw89_write32(rtwdev, reg, val); |
| 2496 | 2498 | |
| 2497 | − reg = rtw89_mac_reg_by_idx(R_AX_PTCL_FSM_MON, mac_idx); | |
| 2499 | + reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_PTCL_FSM_MON, mac_idx); | |
| 2498 | 2500 | val = rtw89_read32(rtwdev, reg); |
| 2499 | 2501 | val = u32_replace_bits(val, S_AX_PTCL_TO_2MS, B_AX_PTCL_TX_ARB_TO_THR_MASK); |
| 2500 | 2502 | val &= ~B_AX_PTCL_TX_ARB_TO_MODE; |
| @@ -2531,7 +2533,7 @@ static int cmac_dma_init(struct rtw89_dev *rtwdev, u8 mac_idx) · 30 unmodified lines | ||
| 2531 | 2533 | if (ret) |
| 2532 | 2534 | return ret; |
| 2533 | 2535 | |
| 2534 | − reg = rtw89_mac_reg_by_idx(R_AX_RXDMA_CTRL_0, mac_idx); | |
| 2536 | + reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_RXDMA_CTRL_0, mac_idx); | |
| 2535 | 2537 | rtw89_write8_clr(rtwdev, reg, RX_FULL_MODE); |
| 2536 | 2538 | |
| 2537 | 2539 | return 0; |
| @@ -2725,7 +2727,7 @@ static int rtw89_hw_sch_tx_en_h2c(struct rtw89_dev *rtwdev, u8 band, · 187 unmodified lines | ||
| 2725 | 2727 | static int rtw89_set_hw_sch_tx_en(struct rtw89_dev *rtwdev, u8 mac_idx, |
| 2726 | 2728 | u16 tx_en, u16 tx_en_mask) |
| 2727 | 2729 | { |
| 2728 | − u32 reg = rtw89_mac_reg_by_idx(R_AX_CTN_TXEN, mac_idx); | |
| 2730 | + u32 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_CTN_TXEN, mac_idx); | |
| 2729 | 2731 | u16 val; |
| 2730 | 2732 | int ret; |
| 2731 | 2733 | |
| @@ -2747,7 +2749,7 @@ static int rtw89_set_hw_sch_tx_en(struct rtw89_dev *rtwdev, u8 mac_idx, · 15 unmodified lines | ||
| 2747 | 2749 | static int rtw89_set_hw_sch_tx_en_v1(struct rtw89_dev *rtwdev, u8 mac_idx, |
| 2748 | 2750 | u32 tx_en, u32 tx_en_mask) |
| 2749 | 2751 | { |
| 2750 | − u32 reg = rtw89_mac_reg_by_idx(R_AX_CTN_DRV_TXEN, mac_idx); | |
| 2752 | + u32 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_CTN_DRV_TXEN, mac_idx); | |
| 2751 | 2753 | u32 val; |
| 2752 | 2754 | int ret; |
| 2753 | 2755 | |
| @@ -2768,7 +2770,7 @@ int rtw89_mac_stop_sch_tx(struct rtw89_dev *rtwdev, u8 mac_idx, · 14 unmodified lines | ||
| 2768 | 2770 | int ret; |
| 2769 | 2771 | |
| 2770 | 2772 | *tx_en = rtw89_read16(rtwdev, |
| 2771 | − rtw89_mac_reg_by_idx(R_AX_CTN_TXEN, mac_idx)); | |
| 2773 | + rtw89_mac_reg_by_idx(rtwdev, R_AX_CTN_TXEN, mac_idx)); | |
| 2772 | 2774 | |
| 2773 | 2775 | switch (sel) { |
| 2774 | 2776 | case RTW89_SCH_TX_SEL_ALL: |
| @@ -2809,7 +2811,7 @@ int rtw89_mac_stop_sch_tx_v1(struct rtw89_dev *rtwdev, u8 mac_idx, · 34 unmodified lines | ||
| 2809 | 2811 | int ret; |
| 2810 | 2812 | |
| 2811 | 2813 | *tx_en = rtw89_read32(rtwdev, |
| 2812 | − rtw89_mac_reg_by_idx(R_AX_CTN_DRV_TXEN, mac_idx)); | |
| 2814 | + rtw89_mac_reg_by_idx(rtwdev, R_AX_CTN_DRV_TXEN, mac_idx)); | |
| 2813 | 2815 | |
| 2814 | 2816 | switch (sel) { |
| 2815 | 2817 | case RTW89_SCH_TX_SEL_ALL: |
| @@ -3016,7 +3018,7 @@ static int band_idle_ck_b(struct rtw89_dev *rtwdev, u8 mac_idx) · 200 unmodified lines | ||
| 3016 | 3018 | if (ret) |
| 3017 | 3019 | return ret; |
| 3018 | 3020 | |
| 3019 | − reg = rtw89_mac_reg_by_idx(R_AX_PTCL_TX_CTN_SEL, mac_idx); | |
| 3021 | + reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_PTCL_TX_CTN_SEL, mac_idx); | |
| 3020 | 3022 | |
| 3021 | 3023 | ret = read_poll_timeout(rtw89_read8, val, |
| 3022 | 3024 | (val & B_AX_PTCL_TX_ON_STAT) == 0, |
| @@ -3224,7 +3226,7 @@ static void rtw89_scheduler_imr_enable(struct rtw89_dev *rtwdev, u8 mac_idx) · 201 unmodified lines | ||
| 3224 | 3226 | { |
| 3225 | 3227 | u32 reg; |
| 3226 | 3228 | |
| 3227 | − reg = rtw89_mac_reg_by_idx(R_AX_SCHEDULE_ERR_IMR, mac_idx); | |
| 3229 | + reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_SCHEDULE_ERR_IMR, mac_idx); | |
| 3228 | 3230 | rtw89_write32_clr(rtwdev, reg, B_AX_SORT_NON_IDLE_ERR_INT_EN | |
| 3229 | 3231 | B_AX_FSM_TIMEOUT_ERR_INT_EN); |
| 3230 | 3232 | rtw89_write32_set(rtwdev, reg, B_AX_FSM_TIMEOUT_ERR_INT_EN); |
| @@ -3235,7 +3237,7 @@ static void rtw89_ptcl_imr_enable(struct rtw89_dev *rtwdev, u8 mac_idx) · 4 unmodified lines | ||
| 3235 | 3237 | const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; |
| 3236 | 3238 | u32 reg; |
| 3237 | 3239 | |
| 3238 | − reg = rtw89_mac_reg_by_idx(R_AX_PTCL_IMR0, mac_idx); | |
| 3240 | + reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_PTCL_IMR0, mac_idx); | |
| 3239 | 3241 | rtw89_write32_clr(rtwdev, reg, imr->ptcl_imr_clr); |
| 3240 | 3242 | rtw89_write32_set(rtwdev, reg, imr->ptcl_imr_set); |
| 3241 | 3243 | } |
| @@ -3246,12 +3248,12 @@ static void rtw89_cdma_imr_enable(struct rtw89_dev *rtwdev, u8 mac_idx) · 4 unmodified lines | ||
| 3246 | 3248 | enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id; |
| 3247 | 3249 | u32 reg; |
| 3248 | 3250 | |
| 3249 | − reg = rtw89_mac_reg_by_idx(imr->cdma_imr_0_reg, mac_idx); | |
| 3251 | + reg = rtw89_mac_reg_by_idx(rtwdev, imr->cdma_imr_0_reg, mac_idx); | |
| 3250 | 3252 | rtw89_write32_clr(rtwdev, reg, imr->cdma_imr_0_clr); |
| 3251 | 3253 | rtw89_write32_set(rtwdev, reg, imr->cdma_imr_0_set); |
| 3252 | 3254 | |
| 3253 | 3255 | if (chip_id == RTL8852C) { |
| 3254 | − reg = rtw89_mac_reg_by_idx(imr->cdma_imr_1_reg, mac_idx); | |
| 3256 | + reg = rtw89_mac_reg_by_idx(rtwdev, imr->cdma_imr_1_reg, mac_idx); | |
| 3255 | 3257 | rtw89_write32_clr(rtwdev, reg, imr->cdma_imr_1_clr); |
| 3256 | 3258 | rtw89_write32_set(rtwdev, reg, imr->cdma_imr_1_set); |
| 3257 | 3259 | } |
| @@ -3262,7 +3264,7 @@ static void rtw89_phy_intf_imr_enable(struct rtw89_dev *rtwdev, u8 mac_idx) · 4 unmodified lines | ||
| 3262 | 3264 | const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; |
| 3263 | 3265 | u32 reg; |
| 3264 | 3266 | |
| 3265 | − reg = rtw89_mac_reg_by_idx(imr->phy_intf_imr_reg, mac_idx); | |
| 3267 | + reg = rtw89_mac_reg_by_idx(rtwdev, imr->phy_intf_imr_reg, mac_idx); | |
| 3266 | 3268 | rtw89_write32_clr(rtwdev, reg, imr->phy_intf_imr_clr); |
| 3267 | 3269 | rtw89_write32_set(rtwdev, reg, imr->phy_intf_imr_set); |
| 3268 | 3270 | } |
| @@ -3272,7 +3274,7 @@ static void rtw89_rmac_imr_enable(struct rtw89_dev *rtwdev, u8 mac_idx) · 3 unmodified lines | ||
| 3272 | 3274 | const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; |
| 3273 | 3275 | u32 reg; |
| 3274 | 3276 | |
| 3275 | − reg = rtw89_mac_reg_by_idx(imr->rmac_imr_reg, mac_idx); | |
| 3277 | + reg = rtw89_mac_reg_by_idx(rtwdev, imr->rmac_imr_reg, mac_idx); | |
| 3276 | 3278 | rtw89_write32_clr(rtwdev, reg, imr->rmac_imr_clr); |
| 3277 | 3279 | rtw89_write32_set(rtwdev, reg, imr->rmac_imr_set); |
| 3278 | 3280 | } |
| @@ -3282,7 +3284,7 @@ static void rtw89_tmac_imr_enable(struct rtw89_dev *rtwdev, u8 mac_idx) · 3 unmodified lines | ||
| 3282 | 3284 | const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; |
| 3283 | 3285 | u32 reg; |
| 3284 | 3286 | |
| 3285 | − reg = rtw89_mac_reg_by_idx(imr->tmac_imr_reg, mac_idx); | |
| 3287 | + reg = rtw89_mac_reg_by_idx(rtwdev, imr->tmac_imr_reg, mac_idx); | |
| 3286 | 3288 | rtw89_write32_clr(rtwdev, reg, imr->tmac_imr_clr); |
| 3287 | 3289 | rtw89_write32_set(rtwdev, reg, imr->tmac_imr_set); |
| 3288 | 3290 | } |
| @@ -3661,6 +3663,9 @@ static void rtw89_mac_dmac_tbl_init(struct rtw89_dev *rtwdev, u8 macid) · 372 unmodified lines | ||
| 3661 | 3663 | { |
| 3662 | 3664 | u8 i; |
| 3663 | 3665 | |
| 3666 | + if (rtwdev->chip->chip_gen != RTW89_CHIP_AX) | |
| 3667 | + return; | |
| 3668 | + | |
| 3664 | 3669 | for (i = 0; i < 4; i++) { |
| 3665 | 3670 | rtw89_write32(rtwdev, R_AX_FILTER_MODEL_ADDR, |
| 3666 | 3671 | DMAC_TBL_BASE_ADDR + (macid << 4) + (i << 2)); |
| @@ -3670,6 +3675,9 @@ static void rtw89_mac_dmac_tbl_init(struct rtw89_dev *rtwdev, u8 macid) · 3 unmodified lines | ||
| 3670 | 3675 | |
| 3671 | 3676 | static void rtw89_mac_cmac_tbl_init(struct rtw89_dev *rtwdev, u8 macid) |
| 3672 | 3677 | { |
| 3678 | + if (rtwdev->chip->chip_gen != RTW89_CHIP_AX) | |
| 3679 | + return; | |
| 3680 | + | |
| 3673 | 3681 | rtw89_write32(rtwdev, R_AX_FILTER_MODEL_ADDR, |
| 3674 | 3682 | CMAC_TBL_BASE_ADDR + macid * CCTL_INFO_SIZE); |
| 3675 | 3683 | rtw89_write32(rtwdev, R_AX_INDIR_ACCESS_ENTRY, 0x4); |
| @@ -3860,7 +3868,7 @@ static void rtw89_mac_port_cfg_hiq_win(struct rtw89_dev *rtwdev, · 184 unmodified lines | ||
| 3860 | 3868 | u8 port = rtwvif->port; |
| 3861 | 3869 | u32 reg; |
| 3862 | 3870 | |
| 3863 | − reg = rtw89_mac_reg_by_idx(hiq_win_addr[port], rtwvif->mac_idx); | |
| 3871 | + reg = rtw89_mac_reg_by_idx(rtwdev, hiq_win_addr[port], rtwvif->mac_idx); | |
| 3864 | 3872 | rtw89_write8(rtwdev, reg, win); |
| 3865 | 3873 | } |
| 3866 | 3874 | |
| @@ -3871,7 +3879,7 @@ static void rtw89_mac_port_cfg_hiq_dtim(struct rtw89_dev *rtwdev, · 4 unmodified lines | ||
| 3871 | 3879 | const struct rtw89_port_reg *p = &rtw_port_base; |
| 3872 | 3880 | u32 addr; |
| 3873 | 3881 | |
| 3874 | − addr = rtw89_mac_reg_by_idx(R_AX_MD_TSFT_STMP_CTL, rtwvif->mac_idx); | |
| 3882 | + addr = rtw89_mac_reg_by_idx(rtwdev, R_AX_MD_TSFT_STMP_CTL, rtwvif->mac_idx); | |
| 3875 | 3883 | rtw89_write8_set(rtwdev, addr, B_AX_UPD_HGQMD | B_AX_UPD_TIMIE); |
| 3876 | 3884 | |
| 3877 | 3885 | rtw89_write16_port_mask(rtwdev, rtwvif, p->dtim_ctrl, B_AX_DTIM_NUM_MASK, |
| @@ -3930,7 +3938,7 @@ static void rtw89_mac_port_cfg_bss_color(struct rtw89_dev *rtwdev, · 52 unmodified lines | ||
| 3930 | 3938 | |
| 3931 | 3939 | bss_color = vif->bss_conf.he_bss_color.color; |
| 3932 | 3940 | reg_base = port >= 4 ? R_AX_PTCL_BSS_COLOR_1 : R_AX_PTCL_BSS_COLOR_0; |
| 3933 | − reg = rtw89_mac_reg_by_idx(reg_base, rtwvif->mac_idx); | |
| 3941 | + reg = rtw89_mac_reg_by_idx(rtwdev, reg_base, rtwvif->mac_idx); | |
| 3934 | 3942 | rtw89_write32_mask(rtwdev, reg, masks[port], bss_color); |
| 3935 | 3943 | } |
| 3936 | 3944 | |
| @@ -3944,7 +3952,7 @@ static void rtw89_mac_port_cfg_mbssid(struct rtw89_dev *rtwdev, · 7 unmodified lines | ||
| 3944 | 3952 | return; |
| 3945 | 3953 | |
| 3946 | 3954 | if (port == 0) { |
| 3947 | − reg = rtw89_mac_reg_by_idx(R_AX_MBSSID_CTRL, rtwvif->mac_idx); | |
| 3955 | + reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_MBSSID_CTRL, rtwvif->mac_idx); | |
| 3948 | 3956 | rtw89_write32_clr(rtwdev, reg, B_AX_P0MB_ALL_MASK); |
| 3949 | 3957 | } |
| 3950 | 3958 | } |
| @@ -3956,7 +3964,7 @@ static void rtw89_mac_port_cfg_hiq_drop(struct rtw89_dev *rtwdev, · 5 unmodified lines | ||
| 3956 | 3964 | u32 reg; |
| 3957 | 3965 | u32 val; |
| 3958 | 3966 | |
| 3959 | − reg = rtw89_mac_reg_by_idx(R_AX_MBSSID_DROP_0, rtwvif->mac_idx); | |
| 3967 | + reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_MBSSID_DROP_0, rtwvif->mac_idx); | |
| 3960 | 3968 | val = rtw89_read32(rtwdev, reg); |
| 3961 | 3969 | val &= ~FIELD_PREP(B_AX_PORT_DROP_4_0_MASK, BIT(port)); |
| 3962 | 3970 | if (port == 0) |
| @@ -4014,7 +4022,7 @@ void rtw89_mac_port_tsf_sync(struct rtw89_dev *rtwdev, · 51 unmodified lines | ||
| 4014 | 4022 | u32 val, reg; |
| 4015 | 4023 | |
| 4016 | 4024 | val = RTW89_PORT_OFFSET_TU_TO_32US(offset_tu); |
| 4017 | − reg = rtw89_mac_reg_by_idx(R_AX_PORT0_TSF_SYNC + rtwvif->port * 4, | |
| 4025 | + reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_PORT0_TSF_SYNC + rtwvif->port * 4, | |
| 4018 | 4026 | rtwvif->mac_idx); |
| 4019 | 4027 | |
| 4020 | 4028 | rtw89_write32_mask(rtwdev, reg, B_AX_SYNC_PORT_SRC, rtwvif_src->port); |
| @@ -4204,7 +4212,7 @@ void rtw89_mac_set_he_obss_narrow_bw_ru(struct rtw89_dev *rtwdev, · 183 unmodified lines | ||
| 4204 | 4212 | rtw89_mac_check_he_obss_narrow_bw_ru_iter, |
| 4205 | 4213 | &tolerated); |
| 4206 | 4214 | |
| 4207 | − reg = rtw89_mac_reg_by_idx(R_AX_RXTRIG_TEST_USER_2, rtwvif->mac_idx); | |
| 4215 | + reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_RXTRIG_TEST_USER_2, rtwvif->mac_idx); | |
| 4208 | 4216 | if (tolerated) |
| 4209 | 4217 | rtw89_write32_clr(rtwdev, reg, B_AX_RXTRIG_RU26_DIS); |
| 4210 | 4218 | else |
| @@ -4731,7 +4739,7 @@ bool rtw89_mac_get_txpwr_cr(struct rtw89_dev *rtwdev, · 520 unmodified lines | ||
| 4731 | 4739 | { |
| 4732 | 4740 | const struct rtw89_dle_mem *dle_mem = rtwdev->chip->dle_mem; |
| 4733 | 4741 | enum rtw89_qta_mode mode = dle_mem->mode; |
| 4734 | − u32 addr = rtw89_mac_reg_by_idx(reg_base, phy_idx); | |
| 4742 | + u32 addr = rtw89_mac_reg_by_idx(rtwdev, reg_base, phy_idx); | |
| 4735 | 4743 | |
| 4736 | 4744 | if (addr < R_AX_PWR_RATE_CTRL || addr > CMAC1_END_ADDR) { |
| 4737 | 4745 | rtw89_err(rtwdev, "[TXPWR] addr=0x%x exceed txpwr cr\n", |
| @@ -4760,7 +4768,7 @@ EXPORT_SYMBOL(rtw89_mac_get_txpwr_cr); · 22 unmodified lines | ||
| 4760 | 4768 | |
| 4761 | 4769 | int rtw89_mac_cfg_ppdu_status(struct rtw89_dev *rtwdev, u8 mac_idx, bool enable) |
| 4762 | 4770 | { |
| 4763 | − u32 reg = rtw89_mac_reg_by_idx(R_AX_PPDU_STAT, mac_idx); | |
| 4771 | + u32 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_PPDU_STAT, mac_idx); | |
| 4764 | 4772 | int ret; |
| 4765 | 4773 | |
| 4766 | 4774 | ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); |
| @@ -4807,7 +4815,7 @@ void rtw89_mac_update_rts_threshold(struct rtw89_dev *rtwdev, u8 mac_idx) · 40 unmodified lines | ||
| 4807 | 4815 | time_th = min_t(u32, time_th >> MAC_AX_TIME_TH_SH, MAC_AX_TIME_TH_MAX); |
| 4808 | 4816 | len_th = min_t(u32, len_th >> MAC_AX_LEN_TH_SH, MAC_AX_LEN_TH_MAX); |
| 4809 | 4817 | |
| 4810 | − reg = rtw89_mac_reg_by_idx(R_AX_AGG_LEN_HT_0, mac_idx); | |
| 4818 | + reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_AGG_LEN_HT_0, mac_idx); | |
| 4811 | 4819 | rtw89_write16_mask(rtwdev, reg, B_AX_RTS_TXTIME_TH_MASK, time_th); |
| 4812 | 4820 | rtw89_write16_mask(rtwdev, reg, B_AX_RTS_LEN_TH_MASK, len_th); |
| 4813 | 4821 | } |
| @@ -5043,7 +5051,7 @@ int rtw89_mac_cfg_plt(struct rtw89_dev *rtwdev, struct rtw89_mac_ax_plt *plt) · 229 unmodified lines | ||
| 5043 | 5051 | if (ret) |
| 5044 | 5052 | return ret; |
| 5045 | 5053 | |
| 5046 | − reg = rtw89_mac_reg_by_idx(R_AX_BT_PLT, plt->band); | |
| 5054 | + reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_BT_PLT, plt->band); | |
| 5047 | 5055 | val = (plt->tx & RTW89_MAC_AX_PLT_LTE_RX ? B_AX_TX_PLT_GNT_LTE_RX : 0) | |
| 5048 | 5056 | (plt->tx & RTW89_MAC_AX_PLT_GNT_BT_TX ? B_AX_TX_PLT_GNT_BT_TX : 0) | |
| 5049 | 5057 | (plt->tx & RTW89_MAC_AX_PLT_GNT_BT_RX ? B_AX_TX_PLT_GNT_BT_RX : 0) | |
| @@ -5133,7 +5141,7 @@ u16 rtw89_mac_get_plt_cnt(struct rtw89_dev *rtwdev, u8 band) · 83 unmodified lines | ||
| 5133 | 5141 | u32 reg; |
| 5134 | 5142 | u16 cnt; |
| 5135 | 5143 | |
| 5136 | − reg = rtw89_mac_reg_by_idx(R_AX_BT_PLT, band); | |
| 5144 | + reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_BT_PLT, band); | |
| 5137 | 5145 | cnt = rtw89_read32_mask(rtwdev, reg, B_AX_BT_PLT_PKT_CNT_MASK); |
| 5138 | 5146 | rtw89_write16_set(rtwdev, reg, B_AX_BT_PLT_RST); |
| 5139 | 5147 | |
| @@ -5146,7 +5154,7 @@ static void rtw89_mac_bfee_standby_timer(struct rtw89_dev *rtwdev, u8 mac_idx, · 6 unmodified lines | ||
| 5146 | 5154 | u32 reg; |
| 5147 | 5155 | |
| 5148 | 5156 | rtw89_debug(rtwdev, RTW89_DBG_BF, "set bfee standby_timer to %d\n", keep); |
| 5149 | − reg = rtw89_mac_reg_by_idx(R_AX_BFMEE_RESP_OPTION, mac_idx); | |
| 5157 | + reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_BFMEE_RESP_OPTION, mac_idx); | |
| 5150 | 5158 | if (keep) { |
| 5151 | 5159 | set_bit(RTW89_FLAG_BFEE_TIMER_KEEP, rtwdev->flags); |
| 5152 | 5160 | rtw89_write32_mask(rtwdev, reg, B_AX_BFMEE_BFRP_RX_STANDBY_TIMER_MASK, |
| @@ -5165,7 +5173,7 @@ static void rtw89_mac_bfee_ctrl(struct rtw89_dev *rtwdev, u8 mac_idx, bool en) · 12 unmodified lines | ||
| 5165 | 5173 | B_AX_BFMEE_HE_NDPA_EN; |
| 5166 | 5174 | |
| 5167 | 5175 | rtw89_debug(rtwdev, RTW89_DBG_BF, "set bfee ndpa_en to %d\n", en); |
| 5168 | − reg = rtw89_mac_reg_by_idx(R_AX_BFMEE_RESP_OPTION, mac_idx); | |
| 5176 | + reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_BFMEE_RESP_OPTION, mac_idx); | |
| 5169 | 5177 | if (en) { |
| 5170 | 5178 | set_bit(RTW89_FLAG_BFEE_EN, rtwdev->flags); |
| 5171 | 5179 | rtw89_write32_set(rtwdev, reg, mask); |
| @@ -5187,30 +5195,30 @@ static int rtw89_mac_init_bfee(struct rtw89_dev *rtwdev, u8 mac_idx) · 15 unmodified lines | ||
| 5187 | 5195 | |
| 5188 | 5196 | /* AP mode set tx gid to 63 */ |
| 5189 | 5197 | /* STA mode set tx gid to 0(default) */ |
| 5190 | − reg = rtw89_mac_reg_by_idx(R_AX_BFMER_CTRL_0, mac_idx); | |
| 5198 | + reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_BFMER_CTRL_0, mac_idx); | |
| 5191 | 5199 | rtw89_write32_set(rtwdev, reg, B_AX_BFMER_NDP_BFEN); |
| 5192 | 5200 | |
| 5193 | − reg = rtw89_mac_reg_by_idx(R_AX_TRXPTCL_RESP_CSI_RRSC, mac_idx); | |
| 5201 | + reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_TRXPTCL_RESP_CSI_RRSC, mac_idx); | |
| 5194 | 5202 | rtw89_write32(rtwdev, reg, CSI_RRSC_BMAP); |
| 5195 | 5203 | |
| 5196 | − reg = rtw89_mac_reg_by_idx(R_AX_BFMEE_RESP_OPTION, mac_idx); | |
| 5204 | + reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_BFMEE_RESP_OPTION, mac_idx); | |
| 5197 | 5205 | val32 = FIELD_PREP(B_AX_BFMEE_NDP_RX_STANDBY_TIMER_MASK, NDP_RX_STANDBY_TIMER); |
| 5198 | 5206 | rtw89_write32(rtwdev, reg, val32); |
| 5199 | 5207 | rtw89_mac_bfee_standby_timer(rtwdev, mac_idx, true); |
| 5200 | 5208 | rtw89_mac_bfee_ctrl(rtwdev, mac_idx, true); |
| 5201 | 5209 | |
| 5202 | − reg = rtw89_mac_reg_by_idx(R_AX_TRXPTCL_RESP_CSI_CTRL_0, mac_idx); | |
| 5210 | + reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_TRXPTCL_RESP_CSI_CTRL_0, mac_idx); | |
| 5203 | 5211 | rtw89_write32_set(rtwdev, reg, B_AX_BFMEE_BFPARAM_SEL | |
| 5204 | 5212 | B_AX_BFMEE_USE_NSTS | |
| 5205 | 5213 | B_AX_BFMEE_CSI_GID_SEL | |
| 5206 | 5214 | B_AX_BFMEE_CSI_FORCE_RETE_EN); |
| 5207 | − reg = rtw89_mac_reg_by_idx(R_AX_TRXPTCL_RESP_CSI_RATE, mac_idx); | |
| 5215 | + reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_TRXPTCL_RESP_CSI_RATE, mac_idx); | |
| 5208 | 5216 | rtw89_write32(rtwdev, reg, |
| 5209 | 5217 | u32_encode_bits(CSI_INIT_RATE_HT, B_AX_BFMEE_HT_CSI_RATE_MASK) | |
| 5210 | 5218 | u32_encode_bits(CSI_INIT_RATE_VHT, B_AX_BFMEE_VHT_CSI_RATE_MASK) | |
| 5211 | 5219 | u32_encode_bits(CSI_INIT_RATE_HE, B_AX_BFMEE_HE_CSI_RATE_MASK)); |
| 5212 | 5220 | |
| 5213 | − reg = rtw89_mac_reg_by_idx(R_AX_CSIRPT_OPTION, mac_idx); | |
| 5221 | + reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_CSIRPT_OPTION, mac_idx); | |
| 5214 | 5222 | rtw89_write32_set(rtwdev, reg, |
| 5215 | 5223 | B_AX_CSIPRT_VHTSU_AID_EN | B_AX_CSIPRT_HESU_AID_EN); |
| 5216 | 5224 | |
| @@ -5254,7 +5262,7 @@ static int rtw89_mac_set_csi_para_reg(struct rtw89_dev *rtwdev, · 37 unmodified lines | ||
| 5254 | 5262 | nc = min(nc, sound_dim); |
| 5255 | 5263 | nr = min(nr, sound_dim); |
| 5256 | 5264 | |
| 5257 | − reg = rtw89_mac_reg_by_idx(R_AX_TRXPTCL_RESP_CSI_CTRL_0, mac_idx); | |
| 5265 | + reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_TRXPTCL_RESP_CSI_CTRL_0, mac_idx); | |
| 5258 | 5266 | rtw89_write32_set(rtwdev, reg, B_AX_BFMEE_BFPARAM_SEL); |
| 5259 | 5267 | |
| 5260 | 5268 | val = FIELD_PREP(B_AX_BFMEE_CSIINFO0_NC_MASK, nc) | |
| @@ -5266,9 +5274,9 @@ static int rtw89_mac_set_csi_para_reg(struct rtw89_dev *rtwdev, · 5 unmodified lines | ||
| 5266 | 5274 | FIELD_PREP(B_AX_BFMEE_CSIINFO0_STBC_EN, stbc_en); |
| 5267 | 5275 | |
| 5268 | 5276 | if (port_sel == 0) |
| 5269 | − reg = rtw89_mac_reg_by_idx(R_AX_TRXPTCL_RESP_CSI_CTRL_0, mac_idx); | |
| 5277 | + reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_TRXPTCL_RESP_CSI_CTRL_0, mac_idx); | |
| 5270 | 5278 | else |
| 5271 | − reg = rtw89_mac_reg_by_idx(R_AX_TRXPTCL_RESP_CSI_CTRL_1, mac_idx); | |
| 5279 | + reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_TRXPTCL_RESP_CSI_CTRL_1, mac_idx); | |
| 5272 | 5280 | |
| 5273 | 5281 | rtw89_write16(rtwdev, reg, val); |
| 5274 | 5282 | |
| @@ -5304,11 +5312,11 @@ static int rtw89_mac_csi_rrsc(struct rtw89_dev *rtwdev, · 29 unmodified lines | ||
| 5304 | 5312 | BIT(RTW89_MAC_BF_RRSC_HT_MSC3) | |
| 5305 | 5313 | BIT(RTW89_MAC_BF_RRSC_HT_MSC5)); |
| 5306 | 5314 | } |
| 5307 | − reg = rtw89_mac_reg_by_idx(R_AX_TRXPTCL_RESP_CSI_CTRL_0, mac_idx); | |
| 5315 | + reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_TRXPTCL_RESP_CSI_CTRL_0, mac_idx); | |
| 5308 | 5316 | rtw89_write32_set(rtwdev, reg, B_AX_BFMEE_BFPARAM_SEL); |
| 5309 | 5317 | rtw89_write32_clr(rtwdev, reg, B_AX_BFMEE_CSI_FORCE_RETE_EN); |
| 5310 | 5318 | rtw89_write32(rtwdev, |
| 5311 | − rtw89_mac_reg_by_idx(R_AX_TRXPTCL_RESP_CSI_RRSC, mac_idx), | |
| 5319 | + rtw89_mac_reg_by_idx(rtwdev, R_AX_TRXPTCL_RESP_CSI_RRSC, mac_idx), | |
| 5312 | 5320 | rrsc); |
| 5313 | 5321 | |
| 5314 | 5322 | return 0; |
| @@ -5346,19 +5354,21 @@ void rtw89_mac_bf_set_gid_table(struct rtw89_dev *rtwdev, struct ieee80211_vif * · 31 unmodified lines | ||
| 5346 | 5354 | rtw89_debug(rtwdev, RTW89_DBG_BF, "update bf GID table\n"); |
| 5347 | 5355 | |
| 5348 | 5356 | p = (__le32 *)conf->mu_group.membership; |
| 5349 | − rtw89_write32(rtwdev, rtw89_mac_reg_by_idx(R_AX_GID_POSITION_EN0, mac_idx), | |
| 5357 | + rtw89_write32(rtwdev, | |
| 5358 | + rtw89_mac_reg_by_idx(rtwdev, R_AX_GID_POSITION_EN0, mac_idx), | |
| 5350 | 5359 | le32_to_cpu(p[0])); |
| 5351 | − rtw89_write32(rtwdev, rtw89_mac_reg_by_idx(R_AX_GID_POSITION_EN1, mac_idx), | |
| 5360 | + rtw89_write32(rtwdev, | |
| 5361 | + rtw89_mac_reg_by_idx(rtwdev, R_AX_GID_POSITION_EN1, mac_idx), | |
| 5352 | 5362 | le32_to_cpu(p[1])); |
| 5353 | 5363 | |
| 5354 | 5364 | p = (__le32 *)conf->mu_group.position; |
| 5355 | − rtw89_write32(rtwdev, rtw89_mac_reg_by_idx(R_AX_GID_POSITION0, mac_idx), | |
| 5365 | + rtw89_write32(rtwdev, rtw89_mac_reg_by_idx(rtwdev, R_AX_GID_POSITION0, mac_idx), | |
| 5356 | 5366 | le32_to_cpu(p[0])); |
| 5357 | − rtw89_write32(rtwdev, rtw89_mac_reg_by_idx(R_AX_GID_POSITION1, mac_idx), | |
| 5367 | + rtw89_write32(rtwdev, rtw89_mac_reg_by_idx(rtwdev, R_AX_GID_POSITION1, mac_idx), | |
| 5358 | 5368 | le32_to_cpu(p[1])); |
| 5359 | − rtw89_write32(rtwdev, rtw89_mac_reg_by_idx(R_AX_GID_POSITION2, mac_idx), | |
| 5369 | + rtw89_write32(rtwdev, rtw89_mac_reg_by_idx(rtwdev, R_AX_GID_POSITION2, mac_idx), | |
| 5360 | 5370 | le32_to_cpu(p[2])); |
| 5361 | − rtw89_write32(rtwdev, rtw89_mac_reg_by_idx(R_AX_GID_POSITION3, mac_idx), | |
| 5371 | + rtw89_write32(rtwdev, rtw89_mac_reg_by_idx(rtwdev, R_AX_GID_POSITION3, mac_idx), | |
| 5362 | 5372 | le32_to_cpu(p[3])); |
| 5363 | 5373 | } |
| 5364 | 5374 | |
| @@ -5449,7 +5459,7 @@ __rtw89_mac_set_tx_time(struct rtw89_dev *rtwdev, struct rtw89_sta *rtwsta, · 84 unmodified lines | ||
| 5449 | 5459 | return ret; |
| 5450 | 5460 | } |
| 5451 | 5461 | |
| 5452 | − reg = rtw89_mac_reg_by_idx(R_AX_AMPDU_AGG_LIMIT, mac_idx); | |
| 5462 | + reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_AMPDU_AGG_LIMIT, mac_idx); | |
| 5453 | 5463 | rtw89_write32_mask(rtwdev, reg, B_AX_AMPDU_MAX_TIME_MASK, |
| 5454 | 5464 | max_tx_time >> 5); |
| 5455 | 5465 | } |
| @@ -5489,7 +5499,7 @@ int rtw89_mac_get_tx_time(struct rtw89_dev *rtwdev, struct rtw89_sta *rtwsta, · 33 unmodified lines | ||
| 5489 | 5499 | return ret; |
| 5490 | 5500 | } |
| 5491 | 5501 | |
| 5492 | − reg = rtw89_mac_reg_by_idx(R_AX_AMPDU_AGG_LIMIT, mac_idx); | |
| 5502 | + reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_AMPDU_AGG_LIMIT, mac_idx); | |
| 5493 | 5503 | *tx_time = rtw89_read32_mask(rtwdev, reg, B_AX_AMPDU_MAX_TIME_MASK) << 5; |
| 5494 | 5504 | } |
| 5495 | 5505 | |
| @@ -5531,7 +5541,7 @@ int rtw89_mac_get_tx_retry_limit(struct rtw89_dev *rtwdev, · 35 unmodified lines | ||
| 5531 | 5541 | return ret; |
| 5532 | 5542 | } |
| 5533 | 5543 | |
| 5534 | − reg = rtw89_mac_reg_by_idx(R_AX_TXCNT, mac_idx); | |
| 5544 | + reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_TXCNT, mac_idx); | |
| 5535 | 5545 | *tx_retry = rtw89_read32_mask(rtwdev, reg, B_AX_L_TXCNT_LMT_MASK); |
| 5536 | 5546 | } |
| 5537 | 5547 | |
| @@ -5550,7 +5560,7 @@ int rtw89_mac_set_hw_muedca_ctrl(struct rtw89_dev *rtwdev, · 12 unmodified lines | ||
| 5550 | 5560 | if (ret) |
| 5551 | 5561 | return ret; |
| 5552 | 5562 | |
| 5553 | − reg = rtw89_mac_reg_by_idx(R_AX_MUEDCA_EN, mac_idx); | |
| 5563 | + reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_MUEDCA_EN, mac_idx); | |
| 5554 | 5564 | if (en) |
| 5555 | 5565 | rtw89_write16_set(rtwdev, reg, set); |
| 5556 | 5566 | else |
| @@ -5673,3 +5683,12 @@ int rtw89_mac_ptk_drop_by_band_and_wait(struct rtw89_dev *rtwdev, · 116 unmodified lines | ||
| 5673 | 5683 | } |
| 5674 | 5684 | return ret; |
| 5675 | 5685 | } |
| 5686 | + | |
| 5687 | +const struct rtw89_mac_gen_def rtw89_mac_gen_ax = { | |
| 5688 | + .band1_offset = RTW89_MAC_AX_BAND_REG_OFFSET, | |
| 5689 | + .filter_model_addr = R_AX_FILTER_MODEL_ADDR, | |
| 5690 | + .indir_access_addr = R_AX_INDIR_ACCESS_ENTRY, | |
| 5691 | + .mem_base_addrs = rtw89_mac_mem_base_addrs_ax, | |
| 5692 | + .rx_fltr = R_AX_RX_FLTR_OPT, | |
| 5693 | +}; | |
| 5694 | +EXPORT_SYMBOL(rtw89_mac_gen_ax); | |
| @@ -275,6 +275,7 @@ enum rtw89_mac_dbg_port_sel { · 274 unmodified lines | ||
| 275 | 275 | |
| 276 | 276 | /* SRAM mem dump */ |
| 277 | 277 | #define R_AX_INDIR_ACCESS_ENTRY 0x40000 |
| 278 | +#define R_BE_INDIR_ACCESS_ENTRY 0x80000 | |
| 278 | 279 | |
| 279 | 280 | #define AXIDMA_BASE_ADDR 0x18006000 |
| 280 | 281 | #define STA_SCHED_BASE_ADDR 0x18808000 |
| @@ -298,6 +299,31 @@ enum rtw89_mac_dbg_port_sel { · 17 unmodified lines | ||
| 298 | 299 | #define TXDATA_FIFO_1_BASE_ADDR 0x188A1000 |
| 299 | 300 | #define CPU_LOCAL_BASE_ADDR 0x18003000 |
| 300 | 301 | |
| 302 | +#define WD_PAGE_BASE_ADDR_BE 0x0 | |
| 303 | +#define CPU_LOCAL_BASE_ADDR_BE 0x18003000 | |
| 304 | +#define AXIDMA_BASE_ADDR_BE 0x18006000 | |
| 305 | +#define SHARED_BUF_BASE_ADDR_BE 0x18700000 | |
| 306 | +#define DMAC_TBL_BASE_ADDR_BE 0x18800000 | |
| 307 | +#define SHCUT_MACHDR_BASE_ADDR_BE 0x18800800 | |
| 308 | +#define STA_SCHED_BASE_ADDR_BE 0x18818000 | |
| 309 | +#define NAT25_CAM_BASE_ADDR_BE 0x18820000 | |
| 310 | +#define RXPLD_FLTR_CAM_BASE_ADDR_BE 0x18823000 | |
| 311 | +#define SEC_CAM_BASE_ADDR_BE 0x18824000 | |
| 312 | +#define WOW_CAM_BASE_ADDR_BE 0x18828000 | |
| 313 | +#define MLD_TBL_BASE_ADDR_BE 0x18829000 | |
| 314 | +#define RX_CLSF_CAM_BASE_ADDR_BE 0x1882A000 | |
| 315 | +#define CMAC_TBL_BASE_ADDR_BE 0x18840000 | |
| 316 | +#define ADDR_CAM_BASE_ADDR_BE 0x18850000 | |
| 317 | +#define BSSID_CAM_BASE_ADDR_BE 0x18858000 | |
| 318 | +#define BA_CAM_BASE_ADDR_BE 0x18859000 | |
| 319 | +#define BCN_IE_CAM0_BASE_ADDR_BE 0x18860000 | |
| 320 | +#define TXDATA_FIFO_0_BASE_ADDR_BE 0x18861000 | |
| 321 | +#define TXD_FIFO_0_BASE_ADDR_BE 0x18862000 | |
| 322 | +#define BCN_IE_CAM1_BASE_ADDR_BE 0x18880000 | |
| 323 | +#define TXDATA_FIFO_1_BASE_ADDR_BE 0x18881000 | |
| 324 | +#define TXD_FIFO_1_BASE_ADDR_BE 0x18881800 | |
| 325 | +#define DCPU_LOCAL_BASE_ADDR_BE 0x19C02000 | |
| 326 | + | |
| 301 | 327 | #define CCTL_INFO_SIZE 32 |
| 302 | 328 | |
| 303 | 329 | enum rtw89_mac_mem_sel { |
| @@ -322,13 +348,12 @@ enum rtw89_mac_mem_sel { · 18 unmodified lines | ||
| 322 | 348 | RTW89_MAC_MEM_BSSID_CAM, |
| 323 | 349 | RTW89_MAC_MEM_TXD_FIFO_0_V1, |
| 324 | 350 | RTW89_MAC_MEM_TXD_FIFO_1_V1, |
| 351 | + RTW89_MAC_MEM_WD_PAGE, | |
| 325 | 352 | |
| 326 | 353 | /* keep last */ |
| 327 | 354 | RTW89_MAC_MEM_NUM, |
| 328 | 355 | }; |
| 329 | 356 | |
| 330 | −extern const u32 rtw89_mac_mem_base_addrs[]; | |
| 331 | − | |
| 332 | 357 | enum rtw89_rpwm_req_pwr_state { |
| 333 | 358 | RTW89_MAC_RPWM_REQ_PWR_STATE_ACTIVE = 0, |
| 334 | 359 | RTW89_MAC_RPWM_REQ_PWR_STATE_BAND0_RFON = 1, |
| @@ -478,6 +503,7 @@ enum rtw89_mac_bf_rrsc_rate { · 143 unmodified lines | ||
| 478 | 503 | ({typeof(_addr) __addr = (_addr); \ |
| 479 | 504 | __addr >= R_AX_CMAC_REG_START && __addr <= R_AX_CMAC_REG_END; }) |
| 480 | 505 | #define RTW89_MAC_AX_BAND_REG_OFFSET 0x2000 |
| 506 | +#define RTW89_MAC_BE_BAND_REG_OFFSET 0x4000 | |
| 481 | 507 | |
| 482 | 508 | #define PTCL_IDLE_POLL_CNT 10000 |
| 483 | 509 | #define SW_CVR_DUR_US 8 |
| @@ -826,14 +852,29 @@ struct rtw89_mac_size_set { · 342 unmodified lines | ||
| 826 | 852 | |
| 827 | 853 | extern const struct rtw89_mac_size_set rtw89_mac_size; |
| 828 | 854 | |
| 829 | −static inline u32 rtw89_mac_reg_by_idx(u32 reg_base, u8 band) | |
| 855 | +struct rtw89_mac_gen_def { | |
| 856 | + u32 band1_offset; | |
| 857 | + u32 filter_model_addr; | |
| 858 | + u32 indir_access_addr; | |
| 859 | + const u32 *mem_base_addrs; | |
| 860 | + u32 rx_fltr; | |
| 861 | +}; | |
| 862 | + | |
| 863 | +extern const struct rtw89_mac_gen_def rtw89_mac_gen_ax; | |
| 864 | +extern const struct rtw89_mac_gen_def rtw89_mac_gen_be; | |
| 865 | + | |
| 866 | +static inline | |
| 867 | +u32 rtw89_mac_reg_by_idx(struct rtw89_dev *rtwdev, u32 reg_base, u8 band) | |
| 830 | 868 | { |
| 831 | − return band == 0 ? reg_base : (reg_base + 0x2000); | |
| 869 | + const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; | |
| 870 | + | |
| 871 | + return band == 0 ? reg_base : (reg_base + mac->band1_offset); | |
| 832 | 872 | } |
| 833 | 873 | |
| 834 | −static inline u32 rtw89_mac_reg_by_port(u32 base, u8 port, u8 mac_idx) | |
| 874 | +static inline | |
| 875 | +u32 rtw89_mac_reg_by_port(struct rtw89_dev *rtwdev, u32 base, u8 port, u8 mac_idx) | |
| 835 | 876 | { |
| 836 | − return rtw89_mac_reg_by_idx(base + port * 0x40, mac_idx); | |
| 877 | + return rtw89_mac_reg_by_idx(rtwdev, base + port * 0x40, mac_idx); | |
| 837 | 878 | } |
| 838 | 879 | |
| 839 | 880 | static inline u32 |
| @@ -841,7 +882,7 @@ rtw89_read32_port(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif, u32 base) · 1 unmodified line | ||
| 841 | 882 | { |
| 842 | 883 | u32 reg; |
| 843 | 884 | |
| 844 | − reg = rtw89_mac_reg_by_port(base, rtwvif->port, rtwvif->mac_idx); | |
| 885 | + reg = rtw89_mac_reg_by_port(rtwdev, base, rtwvif->port, rtwvif->mac_idx); | |
| 845 | 886 | return rtw89_read32(rtwdev, reg); |
| 846 | 887 | } |
| 847 | 888 | |
| @@ -851,7 +892,7 @@ rtw89_read32_port_mask(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif, · 3 unmodified lines | ||
| 851 | 892 | { |
| 852 | 893 | u32 reg; |
| 853 | 894 | |
| 854 | − reg = rtw89_mac_reg_by_port(base, rtwvif->port, rtwvif->mac_idx); | |
| 895 | + reg = rtw89_mac_reg_by_port(rtwdev, base, rtwvif->port, rtwvif->mac_idx); | |
| 855 | 896 | return rtw89_read32_mask(rtwdev, reg, mask); |
| 856 | 897 | } |
| 857 | 898 | |
| @@ -861,7 +902,7 @@ rtw89_write32_port(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif, u32 base, · 3 unmodified lines | ||
| 861 | 902 | { |
| 862 | 903 | u32 reg; |
| 863 | 904 | |
| 864 | − reg = rtw89_mac_reg_by_port(base, rtwvif->port, rtwvif->mac_idx); | |
| 905 | + reg = rtw89_mac_reg_by_port(rtwdev, base, rtwvif->port, rtwvif->mac_idx); | |
| 865 | 906 | rtw89_write32(rtwdev, reg, data); |
| 866 | 907 | } |
| 867 | 908 | |
| @@ -871,7 +912,7 @@ rtw89_write32_port_mask(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif, · 3 unmodified lines | ||
| 871 | 912 | { |
| 872 | 913 | u32 reg; |
| 873 | 914 | |
| 874 | − reg = rtw89_mac_reg_by_port(base, rtwvif->port, rtwvif->mac_idx); | |
| 915 | + reg = rtw89_mac_reg_by_port(rtwdev, base, rtwvif->port, rtwvif->mac_idx); | |
| 875 | 916 | rtw89_write32_mask(rtwdev, reg, mask, data); |
| 876 | 917 | } |
| 877 | 918 | |
| @@ -881,7 +922,7 @@ rtw89_write16_port_mask(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif, · 3 unmodified lines | ||
| 881 | 922 | { |
| 882 | 923 | u32 reg; |
| 883 | 924 | |
| 884 | − reg = rtw89_mac_reg_by_port(base, rtwvif->port, rtwvif->mac_idx); | |
| 925 | + reg = rtw89_mac_reg_by_port(rtwdev, base, rtwvif->port, rtwvif->mac_idx); | |
| 885 | 926 | rtw89_write16_mask(rtwdev, reg, mask, data); |
| 886 | 927 | } |
| 887 | 928 | |
| @@ -891,7 +932,7 @@ rtw89_write32_port_clr(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif, · 3 unmodified lines | ||
| 891 | 932 | { |
| 892 | 933 | u32 reg; |
| 893 | 934 | |
| 894 | − reg = rtw89_mac_reg_by_port(base, rtwvif->port, rtwvif->mac_idx); | |
| 935 | + reg = rtw89_mac_reg_by_port(rtwdev, base, rtwvif->port, rtwvif->mac_idx); | |
| 895 | 936 | rtw89_write32_clr(rtwdev, reg, bit); |
| 896 | 937 | } |
| 897 | 938 | |
| @@ -901,7 +942,7 @@ rtw89_write16_port_clr(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif, · 3 unmodified lines | ||
| 901 | 942 | { |
| 902 | 943 | u32 reg; |
| 903 | 944 | |
| 904 | − reg = rtw89_mac_reg_by_port(base, rtwvif->port, rtwvif->mac_idx); | |
| 945 | + reg = rtw89_mac_reg_by_port(rtwdev, base, rtwvif->port, rtwvif->mac_idx); | |
| 905 | 946 | rtw89_write16_clr(rtwdev, reg, bit); |
| 906 | 947 | } |
| 907 | 948 | |
| @@ -911,7 +952,7 @@ rtw89_write32_port_set(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif, · 3 unmodified lines | ||
| 911 | 952 | { |
| 912 | 953 | u32 reg; |
| 913 | 954 | |
| 914 | − reg = rtw89_mac_reg_by_port(base, rtwvif->port, rtwvif->mac_idx); | |
| 955 | + reg = rtw89_mac_reg_by_port(rtwdev, base, rtwvif->port, rtwvif->mac_idx); | |
| 915 | 956 | rtw89_write32_set(rtwdev, reg, bit); |
| 916 | 957 | } |
| 917 | 958 | |
| @@ -224,6 +224,7 @@ static void rtw89_ops_configure_filter(struct ieee80211_hw *hw, · 223 unmodified lines | ||
| 224 | 224 | u64 multicast) |
| 225 | 225 | { |
| 226 | 226 | struct rtw89_dev *rtwdev = hw->priv; |
| 227 | + const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; | |
| 227 | 228 | |
| 228 | 229 | mutex_lock(&rtwdev->mutex); |
| 229 | 230 | rtw89_leave_ps_mode(rtwdev); |
| @@ -271,13 +272,13 @@ static void rtw89_ops_configure_filter(struct ieee80211_hw *hw, · 41 unmodified lines | ||
| 271 | 272 | } |
| 272 | 273 | |
| 273 | 274 | rtw89_write32_mask(rtwdev, |
| 274 | − rtw89_mac_reg_by_idx(R_AX_RX_FLTR_OPT, RTW89_MAC_0), | |
| 275 | + rtw89_mac_reg_by_idx(rtwdev, mac->rx_fltr, RTW89_MAC_0), | |
| 275 | 276 | B_AX_RX_FLTR_CFG_MASK, |
| 276 | 277 | rtwdev->hal.rx_fltr); |
| 277 | 278 | if (!rtwdev->dbcc_en) |
| 278 | 279 | goto out; |
| 279 | 280 | rtw89_write32_mask(rtwdev, |
| 280 | − rtw89_mac_reg_by_idx(R_AX_RX_FLTR_OPT, RTW89_MAC_1), | |
| 281 | + rtw89_mac_reg_by_idx(rtwdev, mac->rx_fltr, RTW89_MAC_1), | |
| 281 | 282 | B_AX_RX_FLTR_CFG_MASK, |
| 282 | 283 | rtwdev->hal.rx_fltr); |
| 283 | 284 | |
| @@ -296,7 +297,8 @@ static u8 rtw89_aifsn_to_aifs(struct rtw89_dev *rtwdev, · 12 unmodified lines | ||
| 296 | 297 | struct rtw89_vif *rtwvif, u8 aifsn) |
| 297 | 298 | { |
| 298 | 299 | struct ieee80211_vif *vif = rtwvif_to_vif(rtwvif); |
| 299 | − const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, RTW89_SUB_ENTITY_0); | |
| 300 | + const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, | |
| 301 | + rtwvif->sub_entity_idx); | |
| 300 | 302 | u8 slot_time; |
| 301 | 303 | u8 sifs; |
| 302 | 304 | |
| @@ -353,7 +355,7 @@ static void ____rtw89_conf_tx_mu_edca(struct rtw89_dev *rtwdev, · 50 unmodified lines | ||
| 353 | 355 | val = FIELD_PREP(B_AX_MUEDCA_BE_PARAM_0_TIMER_MASK, timer_32us) | |
| 354 | 356 | FIELD_PREP(B_AX_MUEDCA_BE_PARAM_0_CW_MASK, mu_edca->ecw_min_max) | |
| 355 | 357 | FIELD_PREP(B_AX_MUEDCA_BE_PARAM_0_AIFS_MASK, aifs); |
| 356 | − reg = rtw89_mac_reg_by_idx(ac_to_mu_edca_param[ac], rtwvif->mac_idx); | |
| 358 | + reg = rtw89_mac_reg_by_idx(rtwdev, ac_to_mu_edca_param[ac], rtwvif->mac_idx); | |
| 357 | 359 | rtw89_write32(rtwdev, reg, val); |
| 358 | 360 | |
| 359 | 361 | rtw89_mac_set_hw_muedca_ctrl(rtwdev, rtwvif, true); |
| @@ -413,6 +415,8 @@ static void rtw89_ops_bss_info_changed(struct ieee80211_hw *hw, · 53 unmodified lines | ||
| 413 | 415 | rtw89_chip_cfg_txpwr_ul_tb_offset(rtwdev, vif); |
| 414 | 416 | rtw89_mac_port_update(rtwdev, rtwvif); |
| 415 | 417 | rtw89_mac_set_he_obss_narrow_bw_ru(rtwdev, vif); |
| 418 | + | |
| 419 | + rtw89_queue_chanctx_work(rtwdev); | |
| 416 | 420 | } else { |
| 417 | 421 | /* Abort ongoing scan if cancel_scan isn't issued |
| 418 | 422 | * when disconnected by peer |
| @@ -476,6 +480,8 @@ static int rtw89_ops_start_ap(struct ieee80211_hw *hw, · 57 unmodified lines | ||
| 476 | 480 | rtw89_fw_h2c_join_info(rtwdev, rtwvif, NULL, true); |
| 477 | 481 | rtw89_fw_h2c_cam(rtwdev, rtwvif, NULL, NULL); |
| 478 | 482 | rtw89_chip_rfk_channel(rtwdev); |
| 483 | + | |
| 484 | + rtw89_queue_chanctx_work(rtwdev); | |
| 479 | 485 | mutex_unlock(&rtwdev->mutex); |
| 480 | 486 | |
| 481 | 487 | return 0; |
| @@ -0,0 +1,38 @@ | ||
| 1 | +// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause | |
| 2 | +/* Copyright(c) 2019-2020 Realtek Corporation | |
| 3 | + */ | |
| 4 | + | |
| 5 | +#include "mac.h" | |
| 6 | +#include "reg.h" | |
| 7 | + | |
| 8 | +static const u32 rtw89_mac_mem_base_addrs_be[RTW89_MAC_MEM_NUM] = { | |
| 9 | + [RTW89_MAC_MEM_AXIDMA] = AXIDMA_BASE_ADDR_BE, | |
| 10 | + [RTW89_MAC_MEM_SHARED_BUF] = SHARED_BUF_BASE_ADDR_BE, | |
| 11 | + [RTW89_MAC_MEM_DMAC_TBL] = DMAC_TBL_BASE_ADDR_BE, | |
| 12 | + [RTW89_MAC_MEM_SHCUT_MACHDR] = SHCUT_MACHDR_BASE_ADDR_BE, | |
| 13 | + [RTW89_MAC_MEM_STA_SCHED] = STA_SCHED_BASE_ADDR_BE, | |
| 14 | + [RTW89_MAC_MEM_RXPLD_FLTR_CAM] = RXPLD_FLTR_CAM_BASE_ADDR_BE, | |
| 15 | + [RTW89_MAC_MEM_SECURITY_CAM] = SEC_CAM_BASE_ADDR_BE, | |
| 16 | + [RTW89_MAC_MEM_WOW_CAM] = WOW_CAM_BASE_ADDR_BE, | |
| 17 | + [RTW89_MAC_MEM_CMAC_TBL] = CMAC_TBL_BASE_ADDR_BE, | |
| 18 | + [RTW89_MAC_MEM_ADDR_CAM] = ADDR_CAM_BASE_ADDR_BE, | |
| 19 | + [RTW89_MAC_MEM_BA_CAM] = BA_CAM_BASE_ADDR_BE, | |
| 20 | + [RTW89_MAC_MEM_BCN_IE_CAM0] = BCN_IE_CAM0_BASE_ADDR_BE, | |
| 21 | + [RTW89_MAC_MEM_BCN_IE_CAM1] = BCN_IE_CAM1_BASE_ADDR_BE, | |
| 22 | + [RTW89_MAC_MEM_TXD_FIFO_0] = TXD_FIFO_0_BASE_ADDR_BE, | |
| 23 | + [RTW89_MAC_MEM_TXD_FIFO_1] = TXD_FIFO_1_BASE_ADDR_BE, | |
| 24 | + [RTW89_MAC_MEM_TXDATA_FIFO_0] = TXDATA_FIFO_0_BASE_ADDR_BE, | |
| 25 | + [RTW89_MAC_MEM_TXDATA_FIFO_1] = TXDATA_FIFO_1_BASE_ADDR_BE, | |
| 26 | + [RTW89_MAC_MEM_CPU_LOCAL] = CPU_LOCAL_BASE_ADDR_BE, | |
| 27 | + [RTW89_MAC_MEM_BSSID_CAM] = BSSID_CAM_BASE_ADDR_BE, | |
| 28 | + [RTW89_MAC_MEM_WD_PAGE] = WD_PAGE_BASE_ADDR_BE, | |
| 29 | +}; | |
| 30 | + | |
| 31 | +const struct rtw89_mac_gen_def rtw89_mac_gen_be = { | |
| 32 | + .band1_offset = RTW89_MAC_BE_BAND_REG_OFFSET, | |
| 33 | + .filter_model_addr = R_BE_FILTER_MODEL_ADDR, | |
| 34 | + .indir_access_addr = R_BE_INDIR_ACCESS_ENTRY, | |
| 35 | + .mem_base_addrs = rtw89_mac_mem_base_addrs_be, | |
| 36 | + .rx_fltr = R_BE_RX_FLTR_OPT, | |
| 37 | +}; | |
| 38 | +EXPORT_SYMBOL(rtw89_mac_gen_be); | |
| @@ -3939,5 +3939,5 @@ void rtw89_pci_remove(struct pci_dev *pdev) · 3938 unmodified lines | ||
| 3939 | 3939 | EXPORT_SYMBOL(rtw89_pci_remove); |
| 3940 | 3940 | |
| 3941 | 3941 | MODULE_AUTHOR("Realtek Corporation"); |
| 3942 | −MODULE_DESCRIPTION("Realtek 802.11ax wireless PCI driver"); | |
| 3942 | +MODULE_DESCRIPTION("Realtek PCI 802.11ax wireless driver"); | |
| 3943 | 3943 | MODULE_LICENSE("Dual BSD/GPL"); |
| @@ -133,10 +133,10 @@ static u64 rtw89_phy_ra_mask_recover(u64 ra_mask, u64 ra_mask_bak) · 132 unmodified lines | ||
| 133 | 133 | return ra_mask; |
| 134 | 134 | } |
| 135 | 135 | |
| 136 | −static u64 rtw89_phy_ra_mask_cfg(struct rtw89_dev *rtwdev, struct rtw89_sta *rtwsta) | |
| 136 | +static u64 rtw89_phy_ra_mask_cfg(struct rtw89_dev *rtwdev, struct rtw89_sta *rtwsta, | |
| 137 | + const struct rtw89_chan *chan) | |
| 137 | 138 | { |
| 138 | 139 | struct ieee80211_sta *sta = rtwsta_to_sta(rtwsta); |
| 139 | − const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, RTW89_SUB_ENTITY_0); | |
| 140 | 140 | struct cfg80211_bitrate_mask *mask = &rtwsta->mask; |
| 141 | 141 | enum nl80211_band band; |
| 142 | 142 | u64 cfg_mask; |
| @@ -197,9 +197,9 @@ rtw89_ra_mask_he_rates[4] = {RA_MASK_HE_1SS_RATES, RA_MASK_HE_2SS_RATES, · 54 unmodified lines | ||
| 197 | 197 | |
| 198 | 198 | static void rtw89_phy_ra_gi_ltf(struct rtw89_dev *rtwdev, |
| 199 | 199 | struct rtw89_sta *rtwsta, |
| 200 | + const struct rtw89_chan *chan, | |
| 200 | 201 | bool *fix_giltf_en, u8 *fix_giltf) |
| 201 | 202 | { |
| 202 | − const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, RTW89_SUB_ENTITY_0); | |
| 203 | 203 | struct cfg80211_bitrate_mask *mask = &rtwsta->mask; |
| 204 | 204 | u8 band = chan->band_type; |
| 205 | 205 | enum nl80211_band nl_band = rtw89_hw_to_nl80211_band(band); |
| @@ -236,7 +236,8 @@ static void rtw89_phy_ra_sta_update(struct rtw89_dev *rtwdev, · 30 unmodified lines | ||
| 236 | 236 | struct rtw89_vif *rtwvif = rtwsta->rtwvif; |
| 237 | 237 | struct rtw89_phy_rate_pattern *rate_pattern = &rtwvif->rate_pattern; |
| 238 | 238 | struct rtw89_ra_info *ra = &rtwsta->ra; |
| 239 | − const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, RTW89_SUB_ENTITY_0); | |
| 239 | + const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, | |
| 240 | + rtwvif->sub_entity_idx); | |
| 240 | 241 | struct ieee80211_vif *vif = rtwvif_to_vif(rtwsta->rtwvif); |
| 241 | 242 | const u64 *high_rate_masks = rtw89_ra_mask_ht_rates; |
| 242 | 243 | u8 rssi = ewma_rssi_read(&rtwsta->avg_rssi); |
| @@ -265,7 +266,7 @@ static void rtw89_phy_ra_sta_update(struct rtw89_dev *rtwdev, · 22 unmodified lines | ||
| 265 | 266 | if (sta->deflink.he_cap.he_cap_elem.phy_cap_info[1] & |
| 266 | 267 | IEEE80211_HE_PHY_CAP1_LDPC_CODING_IN_PAYLOAD) |
| 267 | 268 | ldpc_en = 1; |
| 268 | − rtw89_phy_ra_gi_ltf(rtwdev, rtwsta, &fix_giltf_en, &fix_giltf); | |
| 269 | + rtw89_phy_ra_gi_ltf(rtwdev, rtwsta, chan, &fix_giltf_en, &fix_giltf); | |
| 269 | 270 | } else if (sta->deflink.vht_cap.vht_supported) { |
| 270 | 271 | u16 mcs_map = le16_to_cpu(sta->deflink.vht_cap.vht_mcs.rx_mcs_map); |
| 271 | 272 | |
| @@ -332,7 +333,7 @@ static void rtw89_phy_ra_sta_update(struct rtw89_dev *rtwdev, · 60 unmodified lines | ||
| 332 | 333 | ra_mask &= rtw89_phy_ra_mask_rssi(rtwdev, rssi, 0); |
| 333 | 334 | |
| 334 | 335 | ra_mask = rtw89_phy_ra_mask_recover(ra_mask, ra_mask_bak); |
| 335 | − ra_mask &= rtw89_phy_ra_mask_cfg(rtwdev, rtwsta); | |
| 336 | + ra_mask &= rtw89_phy_ra_mask_cfg(rtwdev, rtwsta, chan); | |
| 336 | 337 | |
| 337 | 338 | switch (sta->deflink.bandwidth) { |
| 338 | 339 | case IEEE80211_STA_RX_BW_160: |
| @@ -362,7 +363,7 @@ static void rtw89_phy_ra_sta_update(struct rtw89_dev *rtwdev, · 23 unmodified lines | ||
| 362 | 363 | ra->dcm_cap = 1; |
| 363 | 364 | |
| 364 | 365 | if (rate_pattern->enable && !vif->p2p) { |
| 365 | − ra_mask = rtw89_phy_ra_mask_cfg(rtwdev, rtwsta); | |
| 366 | + ra_mask = rtw89_phy_ra_mask_cfg(rtwdev, rtwsta, chan); | |
| 366 | 367 | ra_mask &= rate_pattern->ra_mask; |
| 367 | 368 | mode = rate_pattern->ra_mode; |
| 368 | 369 | } |
| @@ -457,7 +458,8 @@ void rtw89_phy_rate_pattern_vif(struct rtw89_dev *rtwdev, · 88 unmodified lines | ||
| 457 | 458 | struct ieee80211_supported_band *sband; |
| 458 | 459 | struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; |
| 459 | 460 | struct rtw89_phy_rate_pattern next_pattern = {0}; |
| 460 | − const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, RTW89_SUB_ENTITY_0); | |
| 461 | + const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, | |
| 462 | + rtwvif->sub_entity_idx); | |
| 461 | 463 | static const u16 hw_rate_he[][RTW89_CHIP_GEN_NUM] = { |
| 462 | 464 | RTW89_HW_RATE_BY_CHIP_GEN(HE_NSS1_MCS0), |
| 463 | 465 | RTW89_HW_RATE_BY_CHIP_GEN(HE_NSS2_MCS0), |
| @@ -1446,6 +1448,9 @@ static u32 rtw89_phy0_phy1_offset(struct rtw89_dev *rtwdev, u32 addr) · 982 unmodified lines | ||
| 1446 | 1448 | u32 phy_page = addr >> 8; |
| 1447 | 1449 | u32 ofst = 0; |
| 1448 | 1450 | |
| 1451 | + if (rtwdev->chip->chip_gen == RTW89_CHIP_BE) | |
| 1452 | + return addr < 0x10000 ? 0x20000 : 0; | |
| 1453 | + | |
| 1449 | 1454 | switch (phy_page) { |
| 1450 | 1455 | case 0x6: |
| 1451 | 1456 | case 0x7: |
| @@ -1647,6 +1652,8 @@ s8 rtw89_phy_read_txpwr_limit(struct rtw89_dev *rtwdev, u8 band, · 195 unmodified lines | ||
| 1647 | 1652 | const struct rtw89_txpwr_rule_5ghz *rule_5ghz = &rfe_parms->rule_5ghz; |
| 1648 | 1653 | const struct rtw89_txpwr_rule_6ghz *rule_6ghz = &rfe_parms->rule_6ghz; |
| 1649 | 1654 | struct rtw89_regulatory_info *regulatory = &rtwdev->regulatory; |
| 1655 | + enum nl80211_band nl_band = rtw89_hw_to_nl80211_band(band); | |
| 1656 | + u32 freq = ieee80211_channel_to_frequency(ch, nl_band); | |
| 1650 | 1657 | u8 ch_idx = rtw89_channel_to_idx(rtwdev, band, ch); |
| 1651 | 1658 | u8 regd = rtw89_regd_get(rtwdev, band); |
| 1652 | 1659 | u8 reg6 = regulatory->reg_6ghz_power; |
| @@ -1682,7 +1689,7 @@ s8 rtw89_phy_read_txpwr_limit(struct rtw89_dev *rtwdev, u8 band, · 29 unmodified lines | ||
| 1682 | 1689 | } |
| 1683 | 1690 | |
| 1684 | 1691 | lmt = _phy_txpwr_rf_to_mac(rtwdev, lmt); |
| 1685 | − sar = rtw89_query_sar(rtwdev); | |
| 1692 | + sar = rtw89_query_sar(rtwdev, freq); | |
| 1686 | 1693 | |
| 1687 | 1694 | return min(lmt, sar); |
| 1688 | 1695 | } |
| @@ -1902,6 +1909,8 @@ static s8 rtw89_phy_read_txpwr_limit_ru(struct rtw89_dev *rtwdev, u8 band, · 213 unmodified lines | ||
| 1902 | 1909 | const struct rtw89_txpwr_rule_5ghz *rule_5ghz = &rfe_parms->rule_5ghz; |
| 1903 | 1910 | const struct rtw89_txpwr_rule_6ghz *rule_6ghz = &rfe_parms->rule_6ghz; |
| 1904 | 1911 | struct rtw89_regulatory_info *regulatory = &rtwdev->regulatory; |
| 1912 | + enum nl80211_band nl_band = rtw89_hw_to_nl80211_band(band); | |
| 1913 | + u32 freq = ieee80211_channel_to_frequency(ch, nl_band); | |
| 1905 | 1914 | u8 ch_idx = rtw89_channel_to_idx(rtwdev, band, ch); |
| 1906 | 1915 | u8 regd = rtw89_regd_get(rtwdev, band); |
| 1907 | 1916 | u8 reg6 = regulatory->reg_6ghz_power; |
| @@ -1937,7 +1946,7 @@ static s8 rtw89_phy_read_txpwr_limit_ru(struct rtw89_dev *rtwdev, u8 band, · 29 unmodified lines | ||
| 1937 | 1946 | } |
| 1938 | 1947 | |
| 1939 | 1948 | lmt_ru = _phy_txpwr_rf_to_mac(rtwdev, lmt_ru); |
| 1940 | − sar = rtw89_query_sar(rtwdev); | |
| 1949 | + sar = rtw89_query_sar(rtwdev, freq); | |
| 1941 | 1950 | |
| 1942 | 1951 | return min(lmt_ru, sar); |
| 1943 | 1952 | } |
| @@ -2885,7 +2894,8 @@ void rtw89_phy_cfo_parse(struct rtw89_dev *rtwdev, s16 cfo_val, · 941 unmodified lines | ||
| 2885 | 2894 | void rtw89_phy_ul_tb_assoc(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif) |
| 2886 | 2895 | { |
| 2887 | 2896 | const struct rtw89_chip_info *chip = rtwdev->chip; |
| 2888 | − const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, RTW89_SUB_ENTITY_0); | |
| 2897 | + const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, | |
| 2898 | + rtwvif->sub_entity_idx); | |
| 2889 | 2899 | struct rtw89_phy_ul_tb_info *ul_tb_info = &rtwdev->ul_tb_info; |
| 2890 | 2900 | |
| 2891 | 2901 | if (!chip->support_ul_tb_ctrl) |
| @@ -3227,7 +3237,9 @@ static u32 rtw89_phy_ccx_idx_to_us(struct rtw89_dev *rtwdev, u16 idx) · 335 unmodified lines | ||
| 3227 | 3237 | |
| 3228 | 3238 | static void rtw89_phy_ccx_top_setting_init(struct rtw89_dev *rtwdev) |
| 3229 | 3239 | { |
| 3240 | + const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def; | |
| 3230 | 3241 | struct rtw89_env_monitor_info *env = &rtwdev->env_monitor; |
| 3242 | + const struct rtw89_ccx_regs *ccx = phy->ccx; | |
| 3231 | 3243 | |
| 3232 | 3244 | env->ccx_manual_ctrl = false; |
| 3233 | 3245 | env->ccx_ongoing = false; |
| @@ -3235,10 +3247,10 @@ static void rtw89_phy_ccx_top_setting_init(struct rtw89_dev *rtwdev) · 1 unmodified line | ||
| 3235 | 3247 | env->ccx_period = 0; |
| 3236 | 3248 | env->ccx_unit_idx = RTW89_CCX_32_US; |
| 3237 | 3249 | |
| 3238 | − rtw89_phy_set_phy_regs(rtwdev, R_CCX, B_CCX_EN_MSK, 1); | |
| 3239 | − rtw89_phy_set_phy_regs(rtwdev, R_CCX, B_CCX_TRIG_OPT_MSK, 1); | |
| 3240 | − rtw89_phy_set_phy_regs(rtwdev, R_CCX, B_MEASUREMENT_TRIG_MSK, 1); | |
| 3241 | − rtw89_phy_set_phy_regs(rtwdev, R_CCX, B_CCX_EDCCA_OPT_MSK, | |
| 3250 | + rtw89_phy_set_phy_regs(rtwdev, ccx->setting_addr, ccx->en_mask, 1); | |
| 3251 | + rtw89_phy_set_phy_regs(rtwdev, ccx->setting_addr, ccx->trig_opt_mask, 1); | |
| 3252 | + rtw89_phy_set_phy_regs(rtwdev, ccx->setting_addr, ccx->measurement_trig_mask, 1); | |
| 3253 | + rtw89_phy_set_phy_regs(rtwdev, ccx->setting_addr, ccx->edcca_opt_mask, | |
| 3242 | 3254 | RTW89_CCX_EDCCA_BW20_0); |
| 3243 | 3255 | } |
| 3244 | 3256 | |
| @@ -3353,25 +3365,27 @@ ifs_update_finished: · 108 unmodified lines | ||
| 3353 | 3365 | |
| 3354 | 3366 | static void rtw89_phy_ifs_clm_set_th_reg(struct rtw89_dev *rtwdev) |
| 3355 | 3367 | { |
| 3368 | + const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def; | |
| 3356 | 3369 | struct rtw89_env_monitor_info *env = &rtwdev->env_monitor; |
| 3370 | + const struct rtw89_ccx_regs *ccx = phy->ccx; | |
| 3357 | 3371 | u8 i = 0; |
| 3358 | 3372 | |
| 3359 | − rtw89_phy_set_phy_regs(rtwdev, R_IFS_T1, B_IFS_T1_TH_LOW_MSK, | |
| 3373 | + rtw89_phy_set_phy_regs(rtwdev, ccx->ifs_t1_addr, ccx->ifs_t1_th_l_mask, | |
| 3360 | 3374 | env->ifs_clm_th_l[0]); |
| 3361 | − rtw89_phy_set_phy_regs(rtwdev, R_IFS_T2, B_IFS_T2_TH_LOW_MSK, | |
| 3375 | + rtw89_phy_set_phy_regs(rtwdev, ccx->ifs_t2_addr, ccx->ifs_t2_th_l_mask, | |
| 3362 | 3376 | env->ifs_clm_th_l[1]); |
| 3363 | − rtw89_phy_set_phy_regs(rtwdev, R_IFS_T3, B_IFS_T3_TH_LOW_MSK, | |
| 3377 | + rtw89_phy_set_phy_regs(rtwdev, ccx->ifs_t3_addr, ccx->ifs_t3_th_l_mask, | |
| 3364 | 3378 | env->ifs_clm_th_l[2]); |
| 3365 | − rtw89_phy_set_phy_regs(rtwdev, R_IFS_T4, B_IFS_T4_TH_LOW_MSK, | |
| 3379 | + rtw89_phy_set_phy_regs(rtwdev, ccx->ifs_t4_addr, ccx->ifs_t4_th_l_mask, | |
| 3366 | 3380 | env->ifs_clm_th_l[3]); |
| 3367 | 3381 | |
| 3368 | − rtw89_phy_set_phy_regs(rtwdev, R_IFS_T1, B_IFS_T1_TH_HIGH_MSK, | |
| 3382 | + rtw89_phy_set_phy_regs(rtwdev, ccx->ifs_t1_addr, ccx->ifs_t1_th_h_mask, | |
| 3369 | 3383 | env->ifs_clm_th_h[0]); |
| 3370 | − rtw89_phy_set_phy_regs(rtwdev, R_IFS_T2, B_IFS_T2_TH_HIGH_MSK, | |
| 3384 | + rtw89_phy_set_phy_regs(rtwdev, ccx->ifs_t2_addr, ccx->ifs_t2_th_h_mask, | |
| 3371 | 3385 | env->ifs_clm_th_h[1]); |
| 3372 | − rtw89_phy_set_phy_regs(rtwdev, R_IFS_T3, B_IFS_T3_TH_HIGH_MSK, | |
| 3386 | + rtw89_phy_set_phy_regs(rtwdev, ccx->ifs_t3_addr, ccx->ifs_t3_th_h_mask, | |
| 3373 | 3387 | env->ifs_clm_th_h[2]); |
| 3374 | − rtw89_phy_set_phy_regs(rtwdev, R_IFS_T4, B_IFS_T4_TH_HIGH_MSK, | |
| 3388 | + rtw89_phy_set_phy_regs(rtwdev, ccx->ifs_t4_addr, ccx->ifs_t4_th_h_mask, | |
| 3375 | 3389 | env->ifs_clm_th_h[3]); |
| 3376 | 3390 | |
| 3377 | 3391 | for (i = 0; i < RTW89_IFS_CLM_NUM; i++) |
| @@ -3382,7 +3396,9 @@ static void rtw89_phy_ifs_clm_set_th_reg(struct rtw89_dev *rtwdev) · 4 unmodified lines | ||
| 3382 | 3396 | |
| 3383 | 3397 | static void rtw89_phy_ifs_clm_setting_init(struct rtw89_dev *rtwdev) |
| 3384 | 3398 | { |
| 3399 | + const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def; | |
| 3385 | 3400 | struct rtw89_env_monitor_info *env = &rtwdev->env_monitor; |
| 3401 | + const struct rtw89_ccx_regs *ccx = phy->ccx; | |
| 3386 | 3402 | struct rtw89_ccx_para_info para = {0}; |
| 3387 | 3403 | |
| 3388 | 3404 | env->ifs_clm_app = RTW89_IFS_CLM_BACKGROUND; |
| @@ -3392,12 +3408,11 @@ static void rtw89_phy_ifs_clm_setting_init(struct rtw89_dev *rtwdev) · 3 unmodified lines | ||
| 3392 | 3408 | if (rtw89_phy_ifs_clm_th_update_check(rtwdev, ¶)) |
| 3393 | 3409 | rtw89_phy_ifs_clm_set_th_reg(rtwdev); |
| 3394 | 3410 | |
| 3395 | − rtw89_phy_set_phy_regs(rtwdev, R_IFS_COUNTER, B_IFS_COLLECT_EN, | |
| 3396 | − true); | |
| 3397 | − rtw89_phy_set_phy_regs(rtwdev, R_IFS_T1, B_IFS_T1_EN_MSK, true); | |
| 3398 | − rtw89_phy_set_phy_regs(rtwdev, R_IFS_T2, B_IFS_T2_EN_MSK, true); | |
| 3399 | − rtw89_phy_set_phy_regs(rtwdev, R_IFS_T3, B_IFS_T3_EN_MSK, true); | |
| 3400 | − rtw89_phy_set_phy_regs(rtwdev, R_IFS_T4, B_IFS_T4_EN_MSK, true); | |
| 3411 | + rtw89_phy_set_phy_regs(rtwdev, ccx->ifs_cnt_addr, ccx->ifs_collect_en_mask, true); | |
| 3412 | + rtw89_phy_set_phy_regs(rtwdev, ccx->ifs_t1_addr, ccx->ifs_t1_en_mask, true); | |
| 3413 | + rtw89_phy_set_phy_regs(rtwdev, ccx->ifs_t2_addr, ccx->ifs_t2_en_mask, true); | |
| 3414 | + rtw89_phy_set_phy_regs(rtwdev, ccx->ifs_t3_addr, ccx->ifs_t3_en_mask, true); | |
| 3415 | + rtw89_phy_set_phy_regs(rtwdev, ccx->ifs_t4_addr, ccx->ifs_t4_en_mask, true); | |
| 3401 | 3416 | } |
| 3402 | 3417 | |
| 3403 | 3418 | static int rtw89_phy_ccx_racing_ctrl(struct rtw89_dev *rtwdev, |
| @@ -3434,12 +3449,14 @@ static int rtw89_phy_ccx_racing_ctrl(struct rtw89_dev *rtwdev, · 30 unmodified lines | ||
| 3434 | 3449 | |
| 3435 | 3450 | static void rtw89_phy_ccx_trigger(struct rtw89_dev *rtwdev) |
| 3436 | 3451 | { |
| 3452 | + const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def; | |
| 3437 | 3453 | struct rtw89_env_monitor_info *env = &rtwdev->env_monitor; |
| 3454 | + const struct rtw89_ccx_regs *ccx = phy->ccx; | |
| 3438 | 3455 | |
| 3439 | − rtw89_phy_set_phy_regs(rtwdev, R_IFS_COUNTER, B_IFS_COUNTER_CLR_MSK, 0); | |
| 3440 | − rtw89_phy_set_phy_regs(rtwdev, R_CCX, B_MEASUREMENT_TRIG_MSK, 0); | |
| 3441 | − rtw89_phy_set_phy_regs(rtwdev, R_IFS_COUNTER, B_IFS_COUNTER_CLR_MSK, 1); | |
| 3442 | − rtw89_phy_set_phy_regs(rtwdev, R_CCX, B_MEASUREMENT_TRIG_MSK, 1); | |
| 3456 | + rtw89_phy_set_phy_regs(rtwdev, ccx->ifs_cnt_addr, ccx->ifs_clm_cnt_clear_mask, 0); | |
| 3457 | + rtw89_phy_set_phy_regs(rtwdev, ccx->setting_addr, ccx->measurement_trig_mask, 0); | |
| 3458 | + rtw89_phy_set_phy_regs(rtwdev, ccx->ifs_cnt_addr, ccx->ifs_clm_cnt_clear_mask, 1); | |
| 3459 | + rtw89_phy_set_phy_regs(rtwdev, ccx->setting_addr, ccx->measurement_trig_mask, 1); | |
| 3443 | 3460 | |
| 3444 | 3461 | env->ccx_ongoing = true; |
| 3445 | 3462 | } |
| @@ -3511,63 +3528,79 @@ static void rtw89_phy_ifs_clm_get_utility(struct rtw89_dev *rtwdev) · 65 unmodified lines | ||
| 3511 | 3528 | |
| 3512 | 3529 | static bool rtw89_phy_ifs_clm_get_result(struct rtw89_dev *rtwdev) |
| 3513 | 3530 | { |
| 3531 | + const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def; | |
| 3514 | 3532 | struct rtw89_env_monitor_info *env = &rtwdev->env_monitor; |
| 3533 | + const struct rtw89_ccx_regs *ccx = phy->ccx; | |
| 3515 | 3534 | u8 i = 0; |
| 3516 | 3535 | |
| 3517 | − if (rtw89_phy_read32_mask(rtwdev, R_IFSCNT, B_IFSCNT_DONE_MSK) == 0) { | |
| 3536 | + if (rtw89_phy_read32_mask(rtwdev, ccx->ifs_total_addr, | |
| 3537 | + ccx->ifs_cnt_done_mask) == 0) { | |
| 3518 | 3538 | rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, |
| 3519 | 3539 | "Get IFS_CLM report Fail\n"); |
| 3520 | 3540 | return false; |
| 3521 | 3541 | } |
| 3522 | 3542 | |
| 3523 | 3543 | env->ifs_clm_tx = |
| 3524 | − rtw89_phy_read32_mask(rtwdev, R_IFS_CLM_TX_CNT, | |
| 3525 | − B_IFS_CLM_TX_CNT_MSK); | |
| 3544 | + rtw89_phy_read32_mask(rtwdev, ccx->ifs_clm_tx_cnt_addr, | |
| 3545 | + ccx->ifs_clm_tx_cnt_msk); | |
| 3526 | 3546 | env->ifs_clm_edcca_excl_cca = |
| 3527 | − rtw89_phy_read32_mask(rtwdev, R_IFS_CLM_TX_CNT, | |
| 3528 | − B_IFS_CLM_EDCCA_EXCLUDE_CCA_FA_MSK); | |
| 3547 | + rtw89_phy_read32_mask(rtwdev, ccx->ifs_clm_tx_cnt_addr, | |
| 3548 | + ccx->ifs_clm_edcca_excl_cca_fa_mask); | |
| 3529 | 3549 | env->ifs_clm_cckcca_excl_fa = |
| 3530 | − rtw89_phy_read32_mask(rtwdev, R_IFS_CLM_CCA, | |
| 3531 | − B_IFS_CLM_CCKCCA_EXCLUDE_FA_MSK); | |
| 3550 | + rtw89_phy_read32_mask(rtwdev, ccx->ifs_clm_cca_addr, | |
| 3551 | + ccx->ifs_clm_cckcca_excl_fa_mask); | |
| 3532 | 3552 | env->ifs_clm_ofdmcca_excl_fa = |
| 3533 | − rtw89_phy_read32_mask(rtwdev, R_IFS_CLM_CCA, | |
| 3534 | − B_IFS_CLM_OFDMCCA_EXCLUDE_FA_MSK); | |
| 3553 | + rtw89_phy_read32_mask(rtwdev, ccx->ifs_clm_cca_addr, | |
| 3554 | + ccx->ifs_clm_ofdmcca_excl_fa_mask); | |
| 3535 | 3555 | env->ifs_clm_cckfa = |
| 3536 | − rtw89_phy_read32_mask(rtwdev, R_IFS_CLM_FA, | |
| 3537 | − B_IFS_CLM_CCK_FA_MSK); | |
| 3556 | + rtw89_phy_read32_mask(rtwdev, ccx->ifs_clm_fa_addr, | |
| 3557 | + ccx->ifs_clm_cck_fa_mask); | |
| 3538 | 3558 | env->ifs_clm_ofdmfa = |
| 3539 | − rtw89_phy_read32_mask(rtwdev, R_IFS_CLM_FA, | |
| 3540 | − B_IFS_CLM_OFDM_FA_MSK); | |
| 3559 | + rtw89_phy_read32_mask(rtwdev, ccx->ifs_clm_fa_addr, | |
| 3560 | + ccx->ifs_clm_ofdm_fa_mask); | |
| 3541 | 3561 | |
| 3542 | 3562 | env->ifs_clm_his[0] = |
| 3543 | − rtw89_phy_read32_mask(rtwdev, R_IFS_HIS, B_IFS_T1_HIS_MSK); | |
| 3563 | + rtw89_phy_read32_mask(rtwdev, ccx->ifs_his_addr, | |
| 3564 | + ccx->ifs_t1_his_mask); | |
| 3544 | 3565 | env->ifs_clm_his[1] = |
| 3545 | − rtw89_phy_read32_mask(rtwdev, R_IFS_HIS, B_IFS_T2_HIS_MSK); | |
| 3566 | + rtw89_phy_read32_mask(rtwdev, ccx->ifs_his_addr, | |
| 3567 | + ccx->ifs_t2_his_mask); | |
| 3546 | 3568 | env->ifs_clm_his[2] = |
| 3547 | − rtw89_phy_read32_mask(rtwdev, R_IFS_HIS, B_IFS_T3_HIS_MSK); | |
| 3569 | + rtw89_phy_read32_mask(rtwdev, ccx->ifs_his_addr, | |
| 3570 | + ccx->ifs_t3_his_mask); | |
| 3548 | 3571 | env->ifs_clm_his[3] = |
| 3549 | − rtw89_phy_read32_mask(rtwdev, R_IFS_HIS, B_IFS_T4_HIS_MSK); | |
| 3572 | + rtw89_phy_read32_mask(rtwdev, ccx->ifs_his_addr, | |
| 3573 | + ccx->ifs_t4_his_mask); | |
| 3550 | 3574 | |
| 3551 | 3575 | env->ifs_clm_avg[0] = |
| 3552 | − rtw89_phy_read32_mask(rtwdev, R_IFS_AVG_L, B_IFS_T1_AVG_MSK); | |
| 3576 | + rtw89_phy_read32_mask(rtwdev, ccx->ifs_avg_l_addr, | |
| 3577 | + ccx->ifs_t1_avg_mask); | |
| 3553 | 3578 | env->ifs_clm_avg[1] = |
| 3554 | − rtw89_phy_read32_mask(rtwdev, R_IFS_AVG_L, B_IFS_T2_AVG_MSK); | |
| 3579 | + rtw89_phy_read32_mask(rtwdev, ccx->ifs_avg_l_addr, | |
| 3580 | + ccx->ifs_t2_avg_mask); | |
| 3555 | 3581 | env->ifs_clm_avg[2] = |
| 3556 | − rtw89_phy_read32_mask(rtwdev, R_IFS_AVG_H, B_IFS_T3_AVG_MSK); | |
| 3582 | + rtw89_phy_read32_mask(rtwdev, ccx->ifs_avg_h_addr, | |
| 3583 | + ccx->ifs_t3_avg_mask); | |
| 3557 | 3584 | env->ifs_clm_avg[3] = |
| 3558 | − rtw89_phy_read32_mask(rtwdev, R_IFS_AVG_H, B_IFS_T4_AVG_MSK); | |
| 3585 | + rtw89_phy_read32_mask(rtwdev, ccx->ifs_avg_h_addr, | |
| 3586 | + ccx->ifs_t4_avg_mask); | |
| 3559 | 3587 | |
| 3560 | 3588 | env->ifs_clm_cca[0] = |
| 3561 | − rtw89_phy_read32_mask(rtwdev, R_IFS_CCA_L, B_IFS_T1_CCA_MSK); | |
| 3589 | + rtw89_phy_read32_mask(rtwdev, ccx->ifs_cca_l_addr, | |
| 3590 | + ccx->ifs_t1_cca_mask); | |
| 3562 | 3591 | env->ifs_clm_cca[1] = |
| 3563 | − rtw89_phy_read32_mask(rtwdev, R_IFS_CCA_L, B_IFS_T2_CCA_MSK); | |
| 3592 | + rtw89_phy_read32_mask(rtwdev, ccx->ifs_cca_l_addr, | |
| 3593 | + ccx->ifs_t2_cca_mask); | |
| 3564 | 3594 | env->ifs_clm_cca[2] = |
| 3565 | − rtw89_phy_read32_mask(rtwdev, R_IFS_CCA_H, B_IFS_T3_CCA_MSK); | |
| 3595 | + rtw89_phy_read32_mask(rtwdev, ccx->ifs_cca_h_addr, | |
| 3596 | + ccx->ifs_t3_cca_mask); | |
| 3566 | 3597 | env->ifs_clm_cca[3] = |
| 3567 | − rtw89_phy_read32_mask(rtwdev, R_IFS_CCA_H, B_IFS_T4_CCA_MSK); | |
| 3598 | + rtw89_phy_read32_mask(rtwdev, ccx->ifs_cca_h_addr, | |
| 3599 | + ccx->ifs_t4_cca_mask); | |
| 3568 | 3600 | |
| 3569 | 3601 | env->ifs_clm_total_ifs = |
| 3570 | − rtw89_phy_read32_mask(rtwdev, R_IFSCNT, B_IFSCNT_TOTAL_CNT_MSK); | |
| 3602 | + rtw89_phy_read32_mask(rtwdev, ccx->ifs_total_addr, | |
| 3603 | + ccx->ifs_total_mask); | |
| 3571 | 3604 | |
| 3572 | 3605 | rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, "IFS-CLM total_ifs = %d\n", |
| 3573 | 3606 | env->ifs_clm_total_ifs); |
| @@ -3595,7 +3628,9 @@ static bool rtw89_phy_ifs_clm_get_result(struct rtw89_dev *rtwdev) · 21 unmodified lines | ||
| 3595 | 3628 | static int rtw89_phy_ifs_clm_set(struct rtw89_dev *rtwdev, |
| 3596 | 3629 | struct rtw89_ccx_para_info *para) |
| 3597 | 3630 | { |
| 3631 | + const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def; | |
| 3598 | 3632 | struct rtw89_env_monitor_info *env = &rtwdev->env_monitor; |
| 3633 | + const struct rtw89_ccx_regs *ccx = phy->ccx; | |
| 3599 | 3634 | u32 period = 0; |
| 3600 | 3635 | u32 unit_idx = 0; |
| 3601 | 3636 | |
| @@ -3611,10 +3646,11 @@ static int rtw89_phy_ifs_clm_set(struct rtw89_dev *rtwdev, · 9 unmodified lines | ||
| 3611 | 3646 | if (para->mntr_time != env->ifs_clm_mntr_time) { |
| 3612 | 3647 | rtw89_phy_ccx_ms_to_period_unit(rtwdev, para->mntr_time, |
| 3613 | 3648 | &period, &unit_idx); |
| 3614 | − rtw89_phy_set_phy_regs(rtwdev, R_IFS_COUNTER, | |
| 3615 | − B_IFS_CLM_PERIOD_MSK, period); | |
| 3616 | − rtw89_phy_set_phy_regs(rtwdev, R_IFS_COUNTER, | |
| 3617 | − B_IFS_CLM_COUNTER_UNIT_MSK, unit_idx); | |
| 3649 | + rtw89_phy_set_phy_regs(rtwdev, ccx->ifs_cnt_addr, | |
| 3650 | + ccx->ifs_clm_period_mask, period); | |
| 3651 | + rtw89_phy_set_phy_regs(rtwdev, ccx->ifs_cnt_addr, | |
| 3652 | + ccx->ifs_clm_cnt_unit_mask, | |
| 3653 | + unit_idx); | |
| 3618 | 3654 | |
| 3619 | 3655 | rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, |
| 3620 | 3656 | "Update IFS-CLM time ((%d)) -> ((%d))\n", |
| @@ -3732,16 +3768,19 @@ static void rtw89_physts_enable_fail_report(struct rtw89_dev *rtwdev, · 111 unmodified lines | ||
| 3732 | 3768 | bool enable, |
| 3733 | 3769 | enum rtw89_phy_idx phy_idx) |
| 3734 | 3770 | { |
| 3771 | + const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def; | |
| 3772 | + const struct rtw89_physts_regs *physts = phy->physts; | |
| 3773 | + | |
| 3735 | 3774 | if (enable) { |
| 3736 | − rtw89_phy_write32_clr(rtwdev, R_PLCP_HISTOGRAM, | |
| 3737 | − B_STS_DIS_TRIG_BY_FAIL); | |
| 3738 | − rtw89_phy_write32_clr(rtwdev, R_PLCP_HISTOGRAM, | |
| 3739 | − B_STS_DIS_TRIG_BY_BRK); | |
| 3775 | + rtw89_phy_write32_clr(rtwdev, physts->setting_addr, | |
| 3776 | + physts->dis_trigger_fail_mask); | |
| 3777 | + rtw89_phy_write32_clr(rtwdev, physts->setting_addr, | |
| 3778 | + physts->dis_trigger_brk_mask); | |
| 3740 | 3779 | } else { |
| 3741 | − rtw89_phy_write32_set(rtwdev, R_PLCP_HISTOGRAM, | |
| 3742 | − B_STS_DIS_TRIG_BY_FAIL); | |
| 3743 | − rtw89_phy_write32_set(rtwdev, R_PLCP_HISTOGRAM, | |
| 3744 | − B_STS_DIS_TRIG_BY_BRK); | |
| 3780 | + rtw89_phy_write32_set(rtwdev, physts->setting_addr, | |
| 3781 | + physts->dis_trigger_fail_mask); | |
| 3782 | + rtw89_phy_write32_set(rtwdev, physts->setting_addr, | |
| 3783 | + physts->dis_trigger_brk_mask); | |
| 3745 | 3784 | } |
| 3746 | 3785 | } |
| 3747 | 3786 | |
| @@ -4169,10 +4208,10 @@ static void rtw89_phy_dig_dyn_pd_th(struct rtw89_dev *rtwdev, u8 rssi, · 421 unmodified lines | ||
| 4169 | 4208 | "igi=%d, cck_ccaTH=%d, backoff=%d, cck_PD_low=((%d))dB\n", |
| 4170 | 4209 | final_rssi, cck_cca_th, under_region, pd_val); |
| 4171 | 4210 | |
| 4172 | − rtw89_phy_write32_mask(rtwdev, R_BMODE_PDTH_EN_V1, | |
| 4173 | − B_BMODE_PDTH_LIMIT_EN_MSK_V1, enable); | |
| 4174 | − rtw89_phy_write32_mask(rtwdev, R_BMODE_PDTH_V1, | |
| 4175 | − B_BMODE_PDTH_LOWER_BOUND_MSK_V1, pd_val); | |
| 4211 | + rtw89_phy_write32_mask(rtwdev, dig_regs->bmode_pd_reg, | |
| 4212 | + dig_regs->bmode_cca_rssi_limit_en, enable); | |
| 4213 | + rtw89_phy_write32_mask(rtwdev, dig_regs->bmode_pd_lower_bound_reg, | |
| 4214 | + dig_regs->bmode_rssi_nocca_low_th_mask, pd_val); | |
| 4176 | 4215 | } |
| 4177 | 4216 | |
| 4178 | 4217 | void rtw89_phy_dig_reset(struct rtw89_dev *rtwdev) |
| @@ -4561,7 +4600,7 @@ void rtw89_phy_tssi_ctrl_set_fast_mode_cfg(struct rtw89_dev *rtwdev, · 382 unmodified lines | ||
| 4561 | 4600 | regs = rtw89_tssi_fastmode_regs_level; |
| 4562 | 4601 | |
| 4563 | 4602 | for (i = 0; i < RTW89_TSSI_FAST_MODE_NUM; i++) { |
| 4564 | − reg = rtw89_mac_reg_by_idx(regs[i].addr, mac_idx); | |
| 4603 | + reg = rtw89_mac_reg_by_idx(rtwdev, regs[i].addr, mac_idx); | |
| 4565 | 4604 | rtw89_write32_mask(rtwdev, reg, regs[i].mask, val); |
| 4566 | 4605 | } |
| 4567 | 4606 | } |
| @@ -4623,11 +4662,11 @@ void rtw89_phy_tssi_ctrl_set_bandedge_cfg(struct rtw89_dev *rtwdev, · 55 unmodified lines | ||
| 4623 | 4662 | data = chip->tssi_dbw_table->data[bandedge_cfg]; |
| 4624 | 4663 | |
| 4625 | 4664 | for (i = 0; i < RTW89_TSSI_SBW_NUM; i++) { |
| 4626 | − reg = rtw89_mac_reg_by_idx(regs[i].addr, mac_idx); | |
| 4665 | + reg = rtw89_mac_reg_by_idx(rtwdev, regs[i].addr, mac_idx); | |
| 4627 | 4666 | rtw89_write32_mask(rtwdev, reg, regs[i].mask, data[i]); |
| 4628 | 4667 | } |
| 4629 | 4668 | |
| 4630 | − reg = rtw89_mac_reg_by_idx(R_AX_BANDEDGE_CFG, mac_idx); | |
| 4669 | + reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_BANDEDGE_CFG, mac_idx); | |
| 4631 | 4670 | rtw89_write32_mask(rtwdev, reg, B_AX_BANDEDGE_CFG_IDX_MASK, bandedge_cfg); |
| 4632 | 4671 | |
| 4633 | 4672 | rtw89_phy_tssi_ctrl_set_fast_mode_cfg(rtwdev, mac_idx, bandedge_cfg, |
| @@ -4725,3 +4764,74 @@ void rtw89_phy_config_edcca(struct rtw89_dev *rtwdev, bool scan) · 91 unmodified lines | ||
| 4725 | 4764 | rtw89_phy_write32(rtwdev, reg, hal->edcca_bak); |
| 4726 | 4765 | } |
| 4727 | 4766 | } |
| 4767 | + | |
| 4768 | +static const struct rtw89_ccx_regs rtw89_ccx_regs_ax = { | |
| 4769 | + .setting_addr = R_CCX, | |
| 4770 | + .edcca_opt_mask = B_CCX_EDCCA_OPT_MSK, | |
| 4771 | + .measurement_trig_mask = B_MEASUREMENT_TRIG_MSK, | |
| 4772 | + .trig_opt_mask = B_CCX_TRIG_OPT_MSK, | |
| 4773 | + .en_mask = B_CCX_EN_MSK, | |
| 4774 | + .ifs_cnt_addr = R_IFS_COUNTER, | |
| 4775 | + .ifs_clm_period_mask = B_IFS_CLM_PERIOD_MSK, | |
| 4776 | + .ifs_clm_cnt_unit_mask = B_IFS_CLM_COUNTER_UNIT_MSK, | |
| 4777 | + .ifs_clm_cnt_clear_mask = B_IFS_COUNTER_CLR_MSK, | |
| 4778 | + .ifs_collect_en_mask = B_IFS_COLLECT_EN, | |
| 4779 | + .ifs_t1_addr = R_IFS_T1, | |
| 4780 | + .ifs_t1_th_h_mask = B_IFS_T1_TH_HIGH_MSK, | |
| 4781 | + .ifs_t1_en_mask = B_IFS_T1_EN_MSK, | |
| 4782 | + .ifs_t1_th_l_mask = B_IFS_T1_TH_LOW_MSK, | |
| 4783 | + .ifs_t2_addr = R_IFS_T2, | |
| 4784 | + .ifs_t2_th_h_mask = B_IFS_T2_TH_HIGH_MSK, | |
| 4785 | + .ifs_t2_en_mask = B_IFS_T2_EN_MSK, | |
| 4786 | + .ifs_t2_th_l_mask = B_IFS_T2_TH_LOW_MSK, | |
| 4787 | + .ifs_t3_addr = R_IFS_T3, | |
| 4788 | + .ifs_t3_th_h_mask = B_IFS_T3_TH_HIGH_MSK, | |
| 4789 | + .ifs_t3_en_mask = B_IFS_T3_EN_MSK, | |
| 4790 | + .ifs_t3_th_l_mask = B_IFS_T3_TH_LOW_MSK, | |
| 4791 | + .ifs_t4_addr = R_IFS_T4, | |
| 4792 | + .ifs_t4_th_h_mask = B_IFS_T4_TH_HIGH_MSK, | |
| 4793 | + .ifs_t4_en_mask = B_IFS_T4_EN_MSK, | |
| 4794 | + .ifs_t4_th_l_mask = B_IFS_T4_TH_LOW_MSK, | |
| 4795 | + .ifs_clm_tx_cnt_addr = R_IFS_CLM_TX_CNT, | |
| 4796 | + .ifs_clm_edcca_excl_cca_fa_mask = B_IFS_CLM_EDCCA_EXCLUDE_CCA_FA_MSK, | |
| 4797 | + .ifs_clm_tx_cnt_msk = B_IFS_CLM_TX_CNT_MSK, | |
| 4798 | + .ifs_clm_cca_addr = R_IFS_CLM_CCA, | |
| 4799 | + .ifs_clm_ofdmcca_excl_fa_mask = B_IFS_CLM_OFDMCCA_EXCLUDE_FA_MSK, | |
| 4800 | + .ifs_clm_cckcca_excl_fa_mask = B_IFS_CLM_CCKCCA_EXCLUDE_FA_MSK, | |
| 4801 | + .ifs_clm_fa_addr = R_IFS_CLM_FA, | |
| 4802 | + .ifs_clm_ofdm_fa_mask = B_IFS_CLM_OFDM_FA_MSK, | |
| 4803 | + .ifs_clm_cck_fa_mask = B_IFS_CLM_CCK_FA_MSK, | |
| 4804 | + .ifs_his_addr = R_IFS_HIS, | |
| 4805 | + .ifs_t4_his_mask = B_IFS_T4_HIS_MSK, | |
| 4806 | + .ifs_t3_his_mask = B_IFS_T3_HIS_MSK, | |
| 4807 | + .ifs_t2_his_mask = B_IFS_T2_HIS_MSK, | |
| 4808 | + .ifs_t1_his_mask = B_IFS_T1_HIS_MSK, | |
| 4809 | + .ifs_avg_l_addr = R_IFS_AVG_L, | |
| 4810 | + .ifs_t2_avg_mask = B_IFS_T2_AVG_MSK, | |
| 4811 | + .ifs_t1_avg_mask = B_IFS_T1_AVG_MSK, | |
| 4812 | + .ifs_avg_h_addr = R_IFS_AVG_H, | |
| 4813 | + .ifs_t4_avg_mask = B_IFS_T4_AVG_MSK, | |
| 4814 | + .ifs_t3_avg_mask = B_IFS_T3_AVG_MSK, | |
| 4815 | + .ifs_cca_l_addr = R_IFS_CCA_L, | |
| 4816 | + .ifs_t2_cca_mask = B_IFS_T2_CCA_MSK, | |
| 4817 | + .ifs_t1_cca_mask = B_IFS_T1_CCA_MSK, | |
| 4818 | + .ifs_cca_h_addr = R_IFS_CCA_H, | |
| 4819 | + .ifs_t4_cca_mask = B_IFS_T4_CCA_MSK, | |
| 4820 | + .ifs_t3_cca_mask = B_IFS_T3_CCA_MSK, | |
| 4821 | + .ifs_total_addr = R_IFSCNT, | |
| 4822 | + .ifs_cnt_done_mask = B_IFSCNT_DONE_MSK, | |
| 4823 | + .ifs_total_mask = B_IFSCNT_TOTAL_CNT_MSK, | |
| 4824 | +}; | |
| 4825 | + | |
| 4826 | +static const struct rtw89_physts_regs rtw89_physts_regs_ax = { | |
| 4827 | + .setting_addr = R_PLCP_HISTOGRAM, | |
| 4828 | + .dis_trigger_fail_mask = B_STS_DIS_TRIG_BY_FAIL, | |
| 4829 | + .dis_trigger_brk_mask = B_STS_DIS_TRIG_BY_BRK, | |
| 4830 | +}; | |
| 4831 | + | |
| 4832 | +const struct rtw89_phy_gen_def rtw89_phy_gen_ax = { | |
| 4833 | + .cr_base = 0x10000, | |
| 4834 | + .ccx = &rtw89_ccx_regs_ax, | |
| 4835 | + .physts = &rtw89_physts_regs_ax, | |
| 4836 | +}; | |
| 4837 | +EXPORT_SYMBOL(rtw89_phy_gen_ax); | |
| @@ -7,7 +7,6 @@ · 6 unmodified lines | ||
| 7 | 7 | |
| 8 | 8 | #include "core.h" |
| 9 | 9 | |
| 10 | −#define RTW89_PHY_ADDR_OFFSET 0x10000 | |
| 11 | 10 | #define RTW89_RF_ADDR_ADSEL_MASK BIT(16) |
| 12 | 11 | |
| 13 | 12 | #define get_phy_headline(addr) FIELD_GET(GENMASK(31, 28), addr) |
| @@ -337,61 +336,154 @@ struct rtw89_nbi_reg_def { · 323 unmodified lines | ||
| 337 | 336 | struct rtw89_reg_def notch2_en; |
| 338 | 337 | }; |
| 339 | 338 | |
| 339 | +struct rtw89_ccx_regs { | |
| 340 | + u32 setting_addr; | |
| 341 | + u32 edcca_opt_mask; | |
| 342 | + u32 measurement_trig_mask; | |
| 343 | + u32 trig_opt_mask; | |
| 344 | + u32 en_mask; | |
| 345 | + u32 ifs_cnt_addr; | |
| 346 | + u32 ifs_clm_period_mask; | |
| 347 | + u32 ifs_clm_cnt_unit_mask; | |
| 348 | + u32 ifs_clm_cnt_clear_mask; | |
| 349 | + u32 ifs_collect_en_mask; | |
| 350 | + u32 ifs_t1_addr; | |
| 351 | + u32 ifs_t1_th_h_mask; | |
| 352 | + u32 ifs_t1_en_mask; | |
| 353 | + u32 ifs_t1_th_l_mask; | |
| 354 | + u32 ifs_t2_addr; | |
| 355 | + u32 ifs_t2_th_h_mask; | |
| 356 | + u32 ifs_t2_en_mask; | |
| 357 | + u32 ifs_t2_th_l_mask; | |
| 358 | + u32 ifs_t3_addr; | |
| 359 | + u32 ifs_t3_th_h_mask; | |
| 360 | + u32 ifs_t3_en_mask; | |
| 361 | + u32 ifs_t3_th_l_mask; | |
| 362 | + u32 ifs_t4_addr; | |
| 363 | + u32 ifs_t4_th_h_mask; | |
| 364 | + u32 ifs_t4_en_mask; | |
| 365 | + u32 ifs_t4_th_l_mask; | |
| 366 | + u32 ifs_clm_tx_cnt_addr; | |
| 367 | + u32 ifs_clm_edcca_excl_cca_fa_mask; | |
| 368 | + u32 ifs_clm_tx_cnt_msk; | |
| 369 | + u32 ifs_clm_cca_addr; | |
| 370 | + u32 ifs_clm_ofdmcca_excl_fa_mask; | |
| 371 | + u32 ifs_clm_cckcca_excl_fa_mask; | |
| 372 | + u32 ifs_clm_fa_addr; | |
| 373 | + u32 ifs_clm_ofdm_fa_mask; | |
| 374 | + u32 ifs_clm_cck_fa_mask; | |
| 375 | + u32 ifs_his_addr; | |
| 376 | + u32 ifs_t4_his_mask; | |
| 377 | + u32 ifs_t3_his_mask; | |
| 378 | + u32 ifs_t2_his_mask; | |
| 379 | + u32 ifs_t1_his_mask; | |
| 380 | + u32 ifs_avg_l_addr; | |
| 381 | + u32 ifs_t2_avg_mask; | |
| 382 | + u32 ifs_t1_avg_mask; | |
| 383 | + u32 ifs_avg_h_addr; | |
| 384 | + u32 ifs_t4_avg_mask; | |
| 385 | + u32 ifs_t3_avg_mask; | |
| 386 | + u32 ifs_cca_l_addr; | |
| 387 | + u32 ifs_t2_cca_mask; | |
| 388 | + u32 ifs_t1_cca_mask; | |
| 389 | + u32 ifs_cca_h_addr; | |
| 390 | + u32 ifs_t4_cca_mask; | |
| 391 | + u32 ifs_t3_cca_mask; | |
| 392 | + u32 ifs_total_addr; | |
| 393 | + u32 ifs_cnt_done_mask; | |
| 394 | + u32 ifs_total_mask; | |
| 395 | +}; | |
| 396 | + | |
| 397 | +struct rtw89_physts_regs { | |
| 398 | + u32 setting_addr; | |
| 399 | + u32 dis_trigger_fail_mask; | |
| 400 | + u32 dis_trigger_brk_mask; | |
| 401 | +}; | |
| 402 | + | |
| 403 | +struct rtw89_phy_gen_def { | |
| 404 | + u32 cr_base; | |
| 405 | + const struct rtw89_ccx_regs *ccx; | |
| 406 | + const struct rtw89_physts_regs *physts; | |
| 407 | +}; | |
| 408 | + | |
| 409 | +extern const struct rtw89_phy_gen_def rtw89_phy_gen_ax; | |
| 410 | +extern const struct rtw89_phy_gen_def rtw89_phy_gen_be; | |
| 411 | + | |
| 340 | 412 | static inline void rtw89_phy_write8(struct rtw89_dev *rtwdev, |
| 341 | 413 | u32 addr, u8 data) |
| 342 | 414 | { |
| 343 | − rtw89_write8(rtwdev, addr | RTW89_PHY_ADDR_OFFSET, data); | |
| 415 | + const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def; | |
| 416 | + | |
| 417 | + rtw89_write8(rtwdev, addr + phy->cr_base, data); | |
| 344 | 418 | } |
| 345 | 419 | |
| 346 | 420 | static inline void rtw89_phy_write16(struct rtw89_dev *rtwdev, |
| 347 | 421 | u32 addr, u16 data) |
| 348 | 422 | { |
| 349 | − rtw89_write16(rtwdev, addr | RTW89_PHY_ADDR_OFFSET, data); | |
| 423 | + const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def; | |
| 424 | + | |
| 425 | + rtw89_write16(rtwdev, addr + phy->cr_base, data); | |
| 350 | 426 | } |
| 351 | 427 | |
| 352 | 428 | static inline void rtw89_phy_write32(struct rtw89_dev *rtwdev, |
| 353 | 429 | u32 addr, u32 data) |
| 354 | 430 | { |
| 355 | − rtw89_write32(rtwdev, addr | RTW89_PHY_ADDR_OFFSET, data); | |
| 431 | + const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def; | |
| 432 | + | |
| 433 | + rtw89_write32(rtwdev, addr + phy->cr_base, data); | |
| 356 | 434 | } |
| 357 | 435 | |
| 358 | 436 | static inline void rtw89_phy_write32_set(struct rtw89_dev *rtwdev, |
| 359 | 437 | u32 addr, u32 bits) |
| 360 | 438 | { |
| 361 | − rtw89_write32_set(rtwdev, addr | RTW89_PHY_ADDR_OFFSET, bits); | |
| 439 | + const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def; | |
| 440 | + | |
| 441 | + rtw89_write32_set(rtwdev, addr + phy->cr_base, bits); | |
| 362 | 442 | } |
| 363 | 443 | |
| 364 | 444 | static inline void rtw89_phy_write32_clr(struct rtw89_dev *rtwdev, |
| 365 | 445 | u32 addr, u32 bits) |
| 366 | 446 | { |
| 367 | − rtw89_write32_clr(rtwdev, addr | RTW89_PHY_ADDR_OFFSET, bits); | |
| 447 | + const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def; | |
| 448 | + | |
| 449 | + rtw89_write32_clr(rtwdev, addr + phy->cr_base, bits); | |
| 368 | 450 | } |
| 369 | 451 | |
| 370 | 452 | static inline void rtw89_phy_write32_mask(struct rtw89_dev *rtwdev, |
| 371 | 453 | u32 addr, u32 mask, u32 data) |
| 372 | 454 | { |
| 373 | − rtw89_write32_mask(rtwdev, addr | RTW89_PHY_ADDR_OFFSET, mask, data); | |
| 455 | + const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def; | |
| 456 | + | |
| 457 | + rtw89_write32_mask(rtwdev, addr + phy->cr_base, mask, data); | |
| 374 | 458 | } |
| 375 | 459 | |
| 376 | 460 | static inline u8 rtw89_phy_read8(struct rtw89_dev *rtwdev, u32 addr) |
| 377 | 461 | { |
| 378 | − return rtw89_read8(rtwdev, addr | RTW89_PHY_ADDR_OFFSET); | |
| 462 | + const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def; | |
| 463 | + | |
| 464 | + return rtw89_read8(rtwdev, addr + phy->cr_base); | |
| 379 | 465 | } |
| 380 | 466 | |
| 381 | 467 | static inline u16 rtw89_phy_read16(struct rtw89_dev *rtwdev, u32 addr) |
| 382 | 468 | { |
| 383 | − return rtw89_read16(rtwdev, addr | RTW89_PHY_ADDR_OFFSET); | |
| 469 | + const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def; | |
| 470 | + | |
| 471 | + return rtw89_read16(rtwdev, addr + phy->cr_base); | |
| 384 | 472 | } |
| 385 | 473 | |
| 386 | 474 | static inline u32 rtw89_phy_read32(struct rtw89_dev *rtwdev, u32 addr) |
| 387 | 475 | { |
| 388 | − return rtw89_read32(rtwdev, addr | RTW89_PHY_ADDR_OFFSET); | |
| 476 | + const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def; | |
| 477 | + | |
| 478 | + return rtw89_read32(rtwdev, addr + phy->cr_base); | |
| 389 | 479 | } |
| 390 | 480 | |
| 391 | 481 | static inline u32 rtw89_phy_read32_mask(struct rtw89_dev *rtwdev, |
| 392 | 482 | u32 addr, u32 mask) |
| 393 | 483 | { |
| 394 | − return rtw89_read32_mask(rtwdev, addr | RTW89_PHY_ADDR_OFFSET, mask); | |
| 484 | + const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def; | |
| 485 | + | |
| 486 | + return rtw89_read32_mask(rtwdev, addr + phy->cr_base, mask); | |
| 395 | 487 | } |
| 396 | 488 | |
| 397 | 489 | static inline |
| @@ -0,0 +1,77 @@ | ||
| 1 | +// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause | |
| 2 | +/* Copyright(c) 2023 Realtek Corporation | |
| 3 | + */ | |
| 4 | + | |
| 5 | +#include "phy.h" | |
| 6 | +#include "reg.h" | |
| 7 | + | |
| 8 | +static const struct rtw89_ccx_regs rtw89_ccx_regs_be = { | |
| 9 | + .setting_addr = R_CCX, | |
| 10 | + .edcca_opt_mask = B_CCX_EDCCA_OPT_MSK_V1, | |
| 11 | + .measurement_trig_mask = B_MEASUREMENT_TRIG_MSK, | |
| 12 | + .trig_opt_mask = B_CCX_TRIG_OPT_MSK, | |
| 13 | + .en_mask = B_CCX_EN_MSK, | |
| 14 | + .ifs_cnt_addr = R_IFS_COUNTER, | |
| 15 | + .ifs_clm_period_mask = B_IFS_CLM_PERIOD_MSK, | |
| 16 | + .ifs_clm_cnt_unit_mask = B_IFS_CLM_COUNTER_UNIT_MSK, | |
| 17 | + .ifs_clm_cnt_clear_mask = B_IFS_COUNTER_CLR_MSK, | |
| 18 | + .ifs_collect_en_mask = B_IFS_COLLECT_EN, | |
| 19 | + .ifs_t1_addr = R_IFS_T1, | |
| 20 | + .ifs_t1_th_h_mask = B_IFS_T1_TH_HIGH_MSK, | |
| 21 | + .ifs_t1_en_mask = B_IFS_T1_EN_MSK, | |
| 22 | + .ifs_t1_th_l_mask = B_IFS_T1_TH_LOW_MSK, | |
| 23 | + .ifs_t2_addr = R_IFS_T2, | |
| 24 | + .ifs_t2_th_h_mask = B_IFS_T2_TH_HIGH_MSK, | |
| 25 | + .ifs_t2_en_mask = B_IFS_T2_EN_MSK, | |
| 26 | + .ifs_t2_th_l_mask = B_IFS_T2_TH_LOW_MSK, | |
| 27 | + .ifs_t3_addr = R_IFS_T3, | |
| 28 | + .ifs_t3_th_h_mask = B_IFS_T3_TH_HIGH_MSK, | |
| 29 | + .ifs_t3_en_mask = B_IFS_T3_EN_MSK, | |
| 30 | + .ifs_t3_th_l_mask = B_IFS_T3_TH_LOW_MSK, | |
| 31 | + .ifs_t4_addr = R_IFS_T4, | |
| 32 | + .ifs_t4_th_h_mask = B_IFS_T4_TH_HIGH_MSK, | |
| 33 | + .ifs_t4_en_mask = B_IFS_T4_EN_MSK, | |
| 34 | + .ifs_t4_th_l_mask = B_IFS_T4_TH_LOW_MSK, | |
| 35 | + .ifs_clm_tx_cnt_addr = R_IFS_CLM_TX_CNT_V1, | |
| 36 | + .ifs_clm_edcca_excl_cca_fa_mask = B_IFS_CLM_EDCCA_EXCLUDE_CCA_FA_MSK, | |
| 37 | + .ifs_clm_tx_cnt_msk = B_IFS_CLM_TX_CNT_MSK, | |
| 38 | + .ifs_clm_cca_addr = R_IFS_CLM_CCA_V1, | |
| 39 | + .ifs_clm_ofdmcca_excl_fa_mask = B_IFS_CLM_OFDMCCA_EXCLUDE_FA_MSK, | |
| 40 | + .ifs_clm_cckcca_excl_fa_mask = B_IFS_CLM_CCKCCA_EXCLUDE_FA_MSK, | |
| 41 | + .ifs_clm_fa_addr = R_IFS_CLM_FA_V1, | |
| 42 | + .ifs_clm_ofdm_fa_mask = B_IFS_CLM_OFDM_FA_MSK, | |
| 43 | + .ifs_clm_cck_fa_mask = B_IFS_CLM_CCK_FA_MSK, | |
| 44 | + .ifs_his_addr = R_IFS_HIS_V1, | |
| 45 | + .ifs_t4_his_mask = B_IFS_T4_HIS_MSK, | |
| 46 | + .ifs_t3_his_mask = B_IFS_T3_HIS_MSK, | |
| 47 | + .ifs_t2_his_mask = B_IFS_T2_HIS_MSK, | |
| 48 | + .ifs_t1_his_mask = B_IFS_T1_HIS_MSK, | |
| 49 | + .ifs_avg_l_addr = R_IFS_AVG_L_V1, | |
| 50 | + .ifs_t2_avg_mask = B_IFS_T2_AVG_MSK, | |
| 51 | + .ifs_t1_avg_mask = B_IFS_T1_AVG_MSK, | |
| 52 | + .ifs_avg_h_addr = R_IFS_AVG_H_V1, | |
| 53 | + .ifs_t4_avg_mask = B_IFS_T4_AVG_MSK, | |
| 54 | + .ifs_t3_avg_mask = B_IFS_T3_AVG_MSK, | |
| 55 | + .ifs_cca_l_addr = R_IFS_CCA_L_V1, | |
| 56 | + .ifs_t2_cca_mask = B_IFS_T2_CCA_MSK, | |
| 57 | + .ifs_t1_cca_mask = B_IFS_T1_CCA_MSK, | |
| 58 | + .ifs_cca_h_addr = R_IFS_CCA_H_V1, | |
| 59 | + .ifs_t4_cca_mask = B_IFS_T4_CCA_MSK, | |
| 60 | + .ifs_t3_cca_mask = B_IFS_T3_CCA_MSK, | |
| 61 | + .ifs_total_addr = R_IFSCNT_V1, | |
| 62 | + .ifs_cnt_done_mask = B_IFSCNT_DONE_MSK, | |
| 63 | + .ifs_total_mask = B_IFSCNT_TOTAL_CNT_MSK, | |
| 64 | +}; | |
| 65 | + | |
| 66 | +static const struct rtw89_physts_regs rtw89_physts_regs_be = { | |
| 67 | + .setting_addr = R_PLCP_HISTOGRAM, | |
| 68 | + .dis_trigger_fail_mask = B_STS_DIS_TRIG_BY_FAIL, | |
| 69 | + .dis_trigger_brk_mask = B_STS_DIS_TRIG_BY_BRK, | |
| 70 | +}; | |
| 71 | + | |
| 72 | +const struct rtw89_phy_gen_def rtw89_phy_gen_be = { | |
| 73 | + .cr_base = 0x20000, | |
| 74 | + .ccx = &rtw89_ccx_regs_be, | |
| 75 | + .physts = &rtw89_physts_regs_be, | |
| 76 | +}; | |
| 77 | +EXPORT_SYMBOL(rtw89_phy_gen_be); | |
| @@ -2,6 +2,7 @@ · 1 unmodified line | ||
| 2 | 2 | /* Copyright(c) 2019-2020 Realtek Corporation |
| 3 | 3 | */ |
| 4 | 4 | |
| 5 | +#include "chan.h" | |
| 5 | 6 | #include "coex.h" |
| 6 | 7 | #include "core.h" |
| 7 | 8 | #include "debug.h" |
| @@ -257,8 +258,13 @@ void rtw89_recalc_lps(struct rtw89_dev *rtwdev) · 249 unmodified lines | ||
| 257 | 258 | { |
| 258 | 259 | struct ieee80211_vif *vif, *found_vif = NULL; |
| 259 | 260 | struct rtw89_vif *rtwvif; |
| 261 | + enum rtw89_entity_mode mode; | |
| 260 | 262 | int count = 0; |
| 261 | 263 | |
| 264 | + mode = rtw89_get_entity_mode(rtwdev); | |
| 265 | + if (mode == RTW89_ENTITY_MODE_MCC) | |
| 266 | + goto disable_lps; | |
| 267 | + | |
| 262 | 268 | rtw89_for_each_rtwvif(rtwdev, rtwvif) { |
| 263 | 269 | vif = rtwvif_to_vif(rtwvif); |
| 264 | 270 | |
| @@ -273,8 +279,71 @@ void rtw89_recalc_lps(struct rtw89_dev *rtwdev) · 8 unmodified lines | ||
| 273 | 279 | |
| 274 | 280 | if (count == 1 && found_vif->cfg.ps) { |
| 275 | 281 | rtwdev->lps_enabled = true; |
| 276 | − } else { | |
| 277 | − rtw89_leave_lps(rtwdev); | |
| 278 | − rtwdev->lps_enabled = false; | |
| 282 | + return; | |
| 279 | 283 | } |
| 284 | + | |
| 285 | +disable_lps: | |
| 286 | + rtw89_leave_lps(rtwdev); | |
| 287 | + rtwdev->lps_enabled = false; | |
| 288 | +} | |
| 289 | + | |
| 290 | +void rtw89_p2p_noa_renew(struct rtw89_vif *rtwvif) | |
| 291 | +{ | |
| 292 | + struct rtw89_p2p_noa_setter *setter = &rtwvif->p2p_noa; | |
| 293 | + struct rtw89_p2p_noa_ie *ie = &setter->ie; | |
| 294 | + struct rtw89_p2p_ie_head *p2p_head = &ie->p2p_head; | |
| 295 | + struct rtw89_noa_attr_head *noa_head = &ie->noa_head; | |
| 296 | + | |
| 297 | + if (setter->noa_count) { | |
| 298 | + setter->noa_index++; | |
| 299 | + setter->noa_count = 0; | |
| 300 | + } | |
| 301 | + | |
| 302 | + memset(ie, 0, sizeof(*ie)); | |
| 303 | + | |
| 304 | + p2p_head->eid = WLAN_EID_VENDOR_SPECIFIC; | |
| 305 | + p2p_head->ie_len = 4 + sizeof(*noa_head); | |
| 306 | + p2p_head->oui[0] = (WLAN_OUI_WFA >> 16) & 0xff; | |
| 307 | + p2p_head->oui[1] = (WLAN_OUI_WFA >> 8) & 0xff; | |
| 308 | + p2p_head->oui[2] = (WLAN_OUI_WFA >> 0) & 0xff; | |
| 309 | + p2p_head->oui_type = WLAN_OUI_TYPE_WFA_P2P; | |
| 310 | + | |
| 311 | + noa_head->attr_type = IEEE80211_P2P_ATTR_ABSENCE_NOTICE; | |
| 312 | + noa_head->attr_len = cpu_to_le16(2); | |
| 313 | + noa_head->index = setter->noa_index; | |
| 314 | + noa_head->oppps_ctwindow = 0; | |
| 315 | +} | |
| 316 | + | |
| 317 | +void rtw89_p2p_noa_append(struct rtw89_vif *rtwvif, | |
| 318 | + const struct ieee80211_p2p_noa_desc *desc) | |
| 319 | +{ | |
| 320 | + struct rtw89_p2p_noa_setter *setter = &rtwvif->p2p_noa; | |
| 321 | + struct rtw89_p2p_noa_ie *ie = &setter->ie; | |
| 322 | + struct rtw89_p2p_ie_head *p2p_head = &ie->p2p_head; | |
| 323 | + struct rtw89_noa_attr_head *noa_head = &ie->noa_head; | |
| 324 | + | |
| 325 | + if (!desc->count || !desc->duration) | |
| 326 | + return; | |
| 327 | + | |
| 328 | + if (setter->noa_count >= RTW89_P2P_MAX_NOA_NUM) | |
| 329 | + return; | |
| 330 | + | |
| 331 | + p2p_head->ie_len += sizeof(*desc); | |
| 332 | + le16_add_cpu(&noa_head->attr_len, sizeof(*desc)); | |
| 333 | + | |
| 334 | + ie->noa_desc[setter->noa_count++] = *desc; | |
| 335 | +} | |
| 336 | + | |
| 337 | +u8 rtw89_p2p_noa_fetch(struct rtw89_vif *rtwvif, void **data) | |
| 338 | +{ | |
| 339 | + struct rtw89_p2p_noa_setter *setter = &rtwvif->p2p_noa; | |
| 340 | + struct rtw89_p2p_noa_ie *ie = &setter->ie; | |
| 341 | + void *tail; | |
| 342 | + | |
| 343 | + if (!setter->noa_count) | |
| 344 | + return 0; | |
| 345 | + | |
| 346 | + *data = ie; | |
| 347 | + tail = ie->noa_desc + setter->noa_count; | |
| 348 | + return tail - *data; | |
| 280 | 349 | } |
| @@ -16,6 +16,10 @@ void rtw89_leave_ips(struct rtw89_dev *rtwdev); · 15 unmodified lines | ||
| 16 | 16 | void rtw89_set_coex_ctrl_lps(struct rtw89_dev *rtwdev, bool btc_ctrl); |
| 17 | 17 | void rtw89_process_p2p_ps(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif); |
| 18 | 18 | void rtw89_recalc_lps(struct rtw89_dev *rtwdev); |
| 19 | +void rtw89_p2p_noa_renew(struct rtw89_vif *rtwvif); | |
| 20 | +void rtw89_p2p_noa_append(struct rtw89_vif *rtwvif, | |
| 21 | + const struct ieee80211_p2p_noa_desc *desc); | |
| 22 | +u8 rtw89_p2p_noa_fetch(struct rtw89_vif *rtwvif, void **data); | |
| 19 | 23 | |
| 20 | 24 | static inline void rtw89_leave_ips_by_hwflags(struct rtw89_dev *rtwdev) |
| 21 | 25 | { |
| @@ -3625,6 +3625,27 @@ · 3624 unmodified lines | ||
| 3625 | 3625 | #define B_AX_GNT_BT_TX_SW_VAL BIT(1) |
| 3626 | 3626 | #define B_AX_GNT_BT_TX_SW_CTRL BIT(0) |
| 3627 | 3627 | |
| 3628 | +#define R_BE_FILTER_MODEL_ADDR 0x0C04 | |
| 3629 | + | |
| 3630 | +#define R_BE_RX_FLTR_OPT 0x11420 | |
| 3631 | +#define R_BE_RX_FLTR_OPT_C1 0x15420 | |
| 3632 | +#define B_BE_UID_FILTER_MASK GENMASK(31, 24) | |
| 3633 | +#define B_BE_UNSPT_TYPE BIT(22) | |
| 3634 | +#define B_BE_RX_MPDU_MAX_LEN_MASK GENMASK(21, 16) | |
| 3635 | +#define B_BE_A_FTM_REQ BIT(14) | |
| 3636 | +#define B_BE_A_ERR_PKT BIT(13) | |
| 3637 | +#define B_BE_A_UNSUP_PKT BIT(12) | |
| 3638 | +#define B_BE_A_CRC32_ERR BIT(11) | |
| 3639 | +#define B_BE_A_BCN_CHK_RULE_MASK GENMASK(9, 8) | |
| 3640 | +#define B_BE_A_BCN_CHK_EN BIT(7) | |
| 3641 | +#define B_BE_A_MC_LIST_CAM_MATCH BIT(6) | |
| 3642 | +#define B_BE_A_BC_CAM_MATCH BIT(5) | |
| 3643 | +#define B_BE_A_UC_CAM_MATCH BIT(4) | |
| 3644 | +#define B_BE_A_MC BIT(3) | |
| 3645 | +#define B_BE_A_BC BIT(2) | |
| 3646 | +#define B_BE_A_A1_MATCH BIT(1) | |
| 3647 | +#define B_BE_SNIFFER_MODE BIT(0) | |
| 3648 | + | |
| 3628 | 3649 | #define RR_MOD 0x00 |
| 3629 | 3650 | #define RR_MOD_V1 0x10000 |
| 3630 | 3651 | #define RR_MOD_IQK GENMASK(19, 4) |
| @@ -3977,6 +3998,7 @@ · 346 unmodified lines | ||
| 3977 | 3998 | #define B_DBCC_80P80_SEL_EVM_RPT_EN BIT(0) |
| 3978 | 3999 | #define R_CCX 0x0C00 |
| 3979 | 4000 | #define B_CCX_EDCCA_OPT_MSK GENMASK(6, 4) |
| 4001 | +#define B_CCX_EDCCA_OPT_MSK_V1 GENMASK(7, 4) | |
| 3980 | 4002 | #define B_MEASUREMENT_TRIG_MSK BIT(2) |
| 3981 | 4003 | #define B_CCX_TRIG_OPT_MSK BIT(1) |
| 3982 | 4004 | #define B_CCX_EN_MSK BIT(0) |
| @@ -4068,32 +4090,41 @@ · 85 unmodified lines | ||
| 4068 | 4090 | #define B_SWSI_R_DATA_DONE_V1 BIT(26) |
| 4069 | 4091 | #define R_TX_COUNTER 0x1A40 |
| 4070 | 4092 | #define R_IFS_CLM_TX_CNT 0x1ACC |
| 4093 | +#define R_IFS_CLM_TX_CNT_V1 0x0ECC | |
| 4071 | 4094 | #define B_IFS_CLM_EDCCA_EXCLUDE_CCA_FA_MSK GENMASK(31, 16) |
| 4072 | 4095 | #define B_IFS_CLM_TX_CNT_MSK GENMASK(15, 0) |
| 4073 | 4096 | #define R_IFS_CLM_CCA 0x1AD0 |
| 4097 | +#define R_IFS_CLM_CCA_V1 0x0ED0 | |
| 4074 | 4098 | #define B_IFS_CLM_OFDMCCA_EXCLUDE_FA_MSK GENMASK(31, 16) |
| 4075 | 4099 | #define B_IFS_CLM_CCKCCA_EXCLUDE_FA_MSK GENMASK(15, 0) |
| 4076 | 4100 | #define R_IFS_CLM_FA 0x1AD4 |
| 4101 | +#define R_IFS_CLM_FA_V1 0x0ED4 | |
| 4077 | 4102 | #define B_IFS_CLM_OFDM_FA_MSK GENMASK(31, 16) |
| 4078 | 4103 | #define B_IFS_CLM_CCK_FA_MSK GENMASK(15, 0) |
| 4079 | 4104 | #define R_IFS_HIS 0x1AD8 |
| 4105 | +#define R_IFS_HIS_V1 0x0ED8 | |
| 4080 | 4106 | #define B_IFS_T4_HIS_MSK GENMASK(31, 24) |
| 4081 | 4107 | #define B_IFS_T3_HIS_MSK GENMASK(23, 16) |
| 4082 | 4108 | #define B_IFS_T2_HIS_MSK GENMASK(15, 8) |
| 4083 | 4109 | #define B_IFS_T1_HIS_MSK GENMASK(7, 0) |
| 4084 | 4110 | #define R_IFS_AVG_L 0x1ADC |
| 4111 | +#define R_IFS_AVG_L_V1 0x0EDC | |
| 4085 | 4112 | #define B_IFS_T2_AVG_MSK GENMASK(31, 16) |
| 4086 | 4113 | #define B_IFS_T1_AVG_MSK GENMASK(15, 0) |
| 4087 | 4114 | #define R_IFS_AVG_H 0x1AE0 |
| 4115 | +#define R_IFS_AVG_H_V1 0x0EE0 | |
| 4088 | 4116 | #define B_IFS_T4_AVG_MSK GENMASK(31, 16) |
| 4089 | 4117 | #define B_IFS_T3_AVG_MSK GENMASK(15, 0) |
| 4090 | 4118 | #define R_IFS_CCA_L 0x1AE4 |
| 4119 | +#define R_IFS_CCA_L_V1 0x0EE4 | |
| 4091 | 4120 | #define B_IFS_T2_CCA_MSK GENMASK(31, 16) |
| 4092 | 4121 | #define B_IFS_T1_CCA_MSK GENMASK(15, 0) |
| 4093 | 4122 | #define R_IFS_CCA_H 0x1AE8 |
| 4123 | +#define R_IFS_CCA_H_V1 0x0EE8 | |
| 4094 | 4124 | #define B_IFS_T4_CCA_MSK GENMASK(31, 16) |
| 4095 | 4125 | #define B_IFS_T3_CCA_MSK GENMASK(15, 0) |
| 4096 | 4126 | #define R_IFSCNT 0x1AEC |
| 4127 | +#define R_IFSCNT_V1 0x0EEC | |
| 4097 | 4128 | #define B_IFSCNT_DONE_MSK BIT(16) |
| 4098 | 4129 | #define B_IFSCNT_TOTAL_CNT_MSK GENMASK(15, 0) |
| 4099 | 4130 | #define R_TXAGC_TP 0x1C04 |
| @@ -4109,6 +4140,8 @@ · 9 unmodified lines | ||
| 4109 | 4140 | #define B_TXAGC_BB_OFT GENMASK(31, 16) |
| 4110 | 4141 | #define B_TXAGC_BB GENMASK(31, 24) |
| 4111 | 4142 | #define B_TXAGC_RF GENMASK(5, 0) |
| 4143 | +#define R_PATH0_TXPWR 0x1C78 | |
| 4144 | +#define B_PATH0_TXPWR GENMASK(8, 0) | |
| 4112 | 4145 | #define R_S0_ADDCK 0x1E00 |
| 4113 | 4146 | #define B_S0_ADDCK_I GENMASK(9, 0) |
| 4114 | 4147 | #define B_S0_ADDCK_Q GENMASK(19, 10) |
| @@ -4184,6 +4217,8 @@ · 69 unmodified lines | ||
| 4184 | 4217 | #define R_TXAGC_BB_S1 0x3C60 |
| 4185 | 4218 | #define B_TXAGC_BB_S1_OFT GENMASK(31, 16) |
| 4186 | 4219 | #define B_TXAGC_BB_S1 GENMASK(31, 24) |
| 4220 | +#define R_PATH1_TXPWR 0x3C78 | |
| 4221 | +#define B_PATH1_TXPWR GENMASK(8, 0) | |
| 4187 | 4222 | #define R_S1_ADDCK 0x3E00 |
| 4188 | 4223 | #define B_S1_ADDCK_I GENMASK(9, 0) |
| 4189 | 4224 | #define B_S1_ADDCK_Q GENMASK(19, 10) |
| @@ -4360,6 +4395,7 @@ · 170 unmodified lines | ||
| 4360 | 4395 | #define B_PKT_POP_EN BIT(8) |
| 4361 | 4396 | #define R_SEG0R_PD 0x481C |
| 4362 | 4397 | #define R_SEG0R_PD_V1 0x4860 |
| 4398 | +#define R_SEG0R_PD_V2 0x6A74 | |
| 4363 | 4399 | #define R_SEG0R_EDCCA_LVL 0x4840 |
| 4364 | 4400 | #define R_SEG0R_EDCCA_LVL_V1 0x4884 |
| 4365 | 4401 | #define B_SEG0R_PPDU_LVL_MSK GENMASK(31, 24) |
| @@ -4478,8 +4514,10 @@ · 112 unmodified lines | ||
| 4478 | 4514 | #define R_DCFO_COMP_S0_V1 0x4A40 |
| 4479 | 4515 | #define B_DCFO_COMP_S0_V1_MSK GENMASK(13, 0) |
| 4480 | 4516 | #define R_BMODE_PDTH_V1 0x4B64 |
| 4517 | +#define R_BMODE_PDTH_V2 0x6708 | |
| 4481 | 4518 | #define B_BMODE_PDTH_LOWER_BOUND_MSK_V1 GENMASK(31, 24) |
| 4482 | 4519 | #define R_BMODE_PDTH_EN_V1 0x4B74 |
| 4520 | +#define R_BMODE_PDTH_EN_V2 0x6718 | |
| 4483 | 4521 | #define B_BMODE_PDTH_LIMIT_EN_MSK_V1 BIT(30) |
| 4484 | 4522 | #define R_CFO_COMP_SEG1_L 0x5384 |
| 4485 | 4523 | #define R_CFO_COMP_SEG1_H 0x5388 |
| @@ -13,10 +13,10 @@ · 12 unmodified lines | ||
| 13 | 13 | } |
| 14 | 14 | |
| 15 | 15 | static const struct rtw89_regd rtw89_ww_regd = |
| 16 | − COUNTRY_REGD("00", RTW89_WW, RTW89_WW); | |
| 16 | + COUNTRY_REGD("00", RTW89_WW, RTW89_WW, RTW89_WW); | |
| 17 | 17 | |
| 18 | 18 | static const struct rtw89_regd rtw89_regd_map[] = { |
| 19 | − COUNTRY_REGD("AR", RTW89_MEXICO, RTW89_MEXICO, RTW89_NA), | |
| 19 | + COUNTRY_REGD("AR", RTW89_MEXICO, RTW89_MEXICO, RTW89_FCC), | |
| 20 | 20 | COUNTRY_REGD("BO", RTW89_FCC, RTW89_FCC, RTW89_FCC), |
| 21 | 21 | COUNTRY_REGD("BR", RTW89_FCC, RTW89_FCC, RTW89_FCC), |
| 22 | 22 | COUNTRY_REGD("CL", RTW89_CHILE, RTW89_CHILE, RTW89_CHILE), |
| @@ -26,7 +26,7 @@ static const struct rtw89_regd rtw89_regd_map[] = { · 3 unmodified lines | ||
| 26 | 26 | COUNTRY_REGD("SV", RTW89_FCC, RTW89_FCC, RTW89_FCC), |
| 27 | 27 | COUNTRY_REGD("GT", RTW89_FCC, RTW89_FCC, RTW89_FCC), |
| 28 | 28 | COUNTRY_REGD("HN", RTW89_FCC, RTW89_FCC, RTW89_FCC), |
| 29 | − COUNTRY_REGD("MX", RTW89_MEXICO, RTW89_MEXICO, RTW89_NA), | |
| 29 | + COUNTRY_REGD("MX", RTW89_MEXICO, RTW89_MEXICO, RTW89_FCC), | |
| 30 | 30 | COUNTRY_REGD("NI", RTW89_FCC, RTW89_FCC, RTW89_NA), |
| 31 | 31 | COUNTRY_REGD("PA", RTW89_FCC, RTW89_FCC, RTW89_NA), |
| 32 | 32 | COUNTRY_REGD("PY", RTW89_FCC, RTW89_FCC, RTW89_NA), |
| @@ -81,7 +81,7 @@ static const struct rtw89_regd rtw89_regd_map[] = { · 48 unmodified lines | ||
| 81 | 81 | COUNTRY_REGD("KE", RTW89_ETSI, RTW89_ETSI, RTW89_ETSI), |
| 82 | 82 | COUNTRY_REGD("KW", RTW89_ETSI, RTW89_ETSI, RTW89_ETSI), |
| 83 | 83 | COUNTRY_REGD("KG", RTW89_ETSI, RTW89_ETSI, RTW89_ETSI), |
| 84 | − COUNTRY_REGD("LB", RTW89_ETSI, RTW89_ETSI, RTW89_NA), | |
| 84 | + COUNTRY_REGD("LB", RTW89_ETSI, RTW89_ETSI, RTW89_ETSI), | |
| 85 | 85 | COUNTRY_REGD("LS", RTW89_ETSI, RTW89_ETSI, RTW89_NA), |
| 86 | 86 | COUNTRY_REGD("MK", RTW89_ETSI, RTW89_ETSI, RTW89_NA), |
| 87 | 87 | COUNTRY_REGD("MA", RTW89_ETSI, RTW89_ETSI, RTW89_ETSI), |
| @@ -96,7 +96,7 @@ static const struct rtw89_regd rtw89_regd_map[] = { · 8 unmodified lines | ||
| 96 | 96 | COUNTRY_REGD("SN", RTW89_ETSI, RTW89_ETSI, RTW89_NA), |
| 97 | 97 | COUNTRY_REGD("RS", RTW89_ETSI, RTW89_ETSI, RTW89_ETSI), |
| 98 | 98 | COUNTRY_REGD("ME", RTW89_ETSI, RTW89_ETSI, RTW89_NA), |
| 99 | − COUNTRY_REGD("ZA", RTW89_ETSI, RTW89_ETSI, RTW89_NA), | |
| 99 | + COUNTRY_REGD("ZA", RTW89_ETSI, RTW89_ETSI, RTW89_ETSI), | |
| 100 | 100 | COUNTRY_REGD("TR", RTW89_ETSI, RTW89_ETSI, RTW89_ETSI), |
| 101 | 101 | COUNTRY_REGD("UA", RTW89_UKRAINE, RTW89_UKRAINE, RTW89_UKRAINE), |
| 102 | 102 | COUNTRY_REGD("AE", RTW89_ETSI, RTW89_ETSI, RTW89_ETSI), |
| @@ -115,7 +115,7 @@ static const struct rtw89_regd rtw89_regd_map[] = { · 12 unmodified lines | ||
| 115 | 115 | COUNTRY_REGD("SG", RTW89_ETSI, RTW89_ETSI, RTW89_NA), |
| 116 | 116 | COUNTRY_REGD("LK", RTW89_ETSI, RTW89_ETSI, RTW89_NA), |
| 117 | 117 | COUNTRY_REGD("TW", RTW89_FCC, RTW89_FCC, RTW89_NA), |
| 118 | − COUNTRY_REGD("TH", RTW89_ETSI, RTW89_ETSI, RTW89_NA), | |
| 118 | + COUNTRY_REGD("TH", RTW89_WW, RTW89_WW, RTW89_WW), | |
| 119 | 119 | COUNTRY_REGD("VN", RTW89_ETSI, RTW89_ETSI, RTW89_NA), |
| 120 | 120 | COUNTRY_REGD("AU", RTW89_ACMA, RTW89_ACMA, RTW89_ACMA), |
| 121 | 121 | COUNTRY_REGD("NZ", RTW89_ACMA, RTW89_ACMA, RTW89_ACMA), |
| @@ -148,7 +148,7 @@ static const struct rtw89_regd rtw89_regd_map[] = { · 26 unmodified lines | ||
| 148 | 148 | COUNTRY_REGD("IO", RTW89_ETSI, RTW89_ETSI, RTW89_NA), |
| 149 | 149 | COUNTRY_REGD("VG", RTW89_FCC, RTW89_FCC, RTW89_FCC), |
| 150 | 150 | COUNTRY_REGD("BN", RTW89_ETSI, RTW89_ETSI, RTW89_NA), |
| 151 | − COUNTRY_REGD("BF", RTW89_ETSI, RTW89_ETSI, RTW89_NA), | |
| 151 | + COUNTRY_REGD("BF", RTW89_ETSI, RTW89_ETSI, RTW89_ETSI), | |
| 152 | 152 | COUNTRY_REGD("MM", RTW89_ETSI, RTW89_ETSI, RTW89_NA), |
| 153 | 153 | COUNTRY_REGD("BI", RTW89_ETSI, RTW89_ETSI, RTW89_ETSI), |
| 154 | 154 | COUNTRY_REGD("CM", RTW89_ETSI, RTW89_ETSI, RTW89_NA), |
| @@ -164,7 +164,7 @@ static const struct rtw89_regd rtw89_regd_map[] = { · 9 unmodified lines | ||
| 164 | 164 | COUNTRY_REGD("CK", RTW89_ETSI, RTW89_ETSI, RTW89_NA), |
| 165 | 165 | COUNTRY_REGD("CI", RTW89_ETSI, RTW89_ETSI, RTW89_NA), |
| 166 | 166 | COUNTRY_REGD("DJ", RTW89_ETSI, RTW89_ETSI, RTW89_ETSI), |
| 167 | − COUNTRY_REGD("DM", RTW89_FCC, RTW89_FCC, RTW89_FCC), | |
| 167 | + COUNTRY_REGD("DM", RTW89_FCC, RTW89_FCC, RTW89_NA), | |
| 168 | 168 | COUNTRY_REGD("GQ", RTW89_ETSI, RTW89_ETSI, RTW89_ETSI), |
| 169 | 169 | COUNTRY_REGD("ER", RTW89_ETSI, RTW89_ETSI, RTW89_NA), |
| 170 | 170 | COUNTRY_REGD("ET", RTW89_ETSI, RTW89_ETSI, RTW89_NA), |
| @@ -179,20 +179,21 @@ static const struct rtw89_regd rtw89_regd_map[] = { · 8 unmodified lines | ||
| 179 | 179 | COUNTRY_REGD("GE", RTW89_ETSI, RTW89_ETSI, RTW89_NA), |
| 180 | 180 | COUNTRY_REGD("GI", RTW89_ETSI, RTW89_ETSI, RTW89_NA), |
| 181 | 181 | COUNTRY_REGD("GL", RTW89_ETSI, RTW89_ETSI, RTW89_NA), |
| 182 | − COUNTRY_REGD("GD", RTW89_FCC, RTW89_FCC, RTW89_FCC), | |
| 182 | + COUNTRY_REGD("GD", RTW89_FCC, RTW89_FCC, RTW89_NA), | |
| 183 | 183 | COUNTRY_REGD("GP", RTW89_ETSI, RTW89_ETSI, RTW89_NA), |
| 184 | 184 | COUNTRY_REGD("GU", RTW89_FCC, RTW89_FCC, RTW89_NA), |
| 185 | 185 | COUNTRY_REGD("GG", RTW89_ETSI, RTW89_ETSI, RTW89_NA), |
| 186 | 186 | COUNTRY_REGD("GN", RTW89_ETSI, RTW89_ETSI, RTW89_ETSI), |
| 187 | 187 | COUNTRY_REGD("GW", RTW89_ETSI, RTW89_ETSI, RTW89_NA), |
| 188 | − COUNTRY_REGD("GY", RTW89_FCC, RTW89_FCC, RTW89_FCC), | |
| 189 | − COUNTRY_REGD("HT", RTW89_FCC, RTW89_FCC, RTW89_NA), | |
| 188 | + COUNTRY_REGD("GY", RTW89_FCC, RTW89_FCC, RTW89_NA), | |
| 189 | + COUNTRY_REGD("HT", RTW89_FCC, RTW89_FCC, RTW89_FCC), | |
| 190 | 190 | COUNTRY_REGD("HM", RTW89_ACMA, RTW89_ACMA, RTW89_NA), |
| 191 | 191 | COUNTRY_REGD("VA", RTW89_ETSI, RTW89_ETSI, RTW89_NA), |
| 192 | 192 | COUNTRY_REGD("IM", RTW89_ETSI, RTW89_ETSI, RTW89_NA), |
| 193 | 193 | COUNTRY_REGD("JE", RTW89_ETSI, RTW89_ETSI, RTW89_NA), |
| 194 | 194 | COUNTRY_REGD("KI", RTW89_ETSI, RTW89_ETSI, RTW89_NA), |
| 195 | − COUNTRY_REGD("LA", RTW89_ETSI, RTW89_ETSI, RTW89_NA), | |
| 195 | + COUNTRY_REGD("XK", RTW89_ETSI, RTW89_ETSI, RTW89_ETSI), | |
| 196 | + COUNTRY_REGD("LA", RTW89_ETSI, RTW89_ETSI, RTW89_ETSI), | |
| 196 | 197 | COUNTRY_REGD("LR", RTW89_ETSI, RTW89_ETSI, RTW89_NA), |
| 197 | 198 | COUNTRY_REGD("LY", RTW89_ETSI, RTW89_ETSI, RTW89_NA), |
| 198 | 199 | COUNTRY_REGD("MO", RTW89_ETSI, RTW89_ETSI, RTW89_NA), |
| @@ -207,7 +208,7 @@ static const struct rtw89_regd rtw89_regd_map[] = { · 8 unmodified lines | ||
| 207 | 208 | COUNTRY_REGD("YT", RTW89_ETSI, RTW89_ETSI, RTW89_NA), |
| 208 | 209 | COUNTRY_REGD("FM", RTW89_FCC, RTW89_FCC, RTW89_NA), |
| 209 | 210 | COUNTRY_REGD("MD", RTW89_ETSI, RTW89_ETSI, RTW89_ETSI), |
| 210 | − COUNTRY_REGD("MN", RTW89_ETSI, RTW89_ETSI, RTW89_NA), | |
| 211 | + COUNTRY_REGD("MN", RTW89_ETSI, RTW89_ETSI, RTW89_ETSI), | |
| 211 | 212 | COUNTRY_REGD("MS", RTW89_ETSI, RTW89_ETSI, RTW89_NA), |
| 212 | 213 | COUNTRY_REGD("NR", RTW89_ETSI, RTW89_ETSI, RTW89_NA), |
| 213 | 214 | COUNTRY_REGD("NP", RTW89_ETSI, RTW89_ETSI, RTW89_NA), |
| @@ -185,6 +185,10 @@ static const struct rtw89_dig_regs rtw8851b_dig_regs = { · 184 unmodified lines | ||
| 185 | 185 | .seg0_pd_reg = R_SEG0R_PD_V1, |
| 186 | 186 | .pd_lower_bound_mask = B_SEG0R_PD_LOWER_BOUND_MSK, |
| 187 | 187 | .pd_spatial_reuse_en = B_SEG0R_PD_SPATIAL_REUSE_EN_MSK_V1, |
| 188 | + .bmode_pd_reg = R_BMODE_PDTH_EN_V1, | |
| 189 | + .bmode_cca_rssi_limit_en = B_BMODE_PDTH_LIMIT_EN_MSK_V1, | |
| 190 | + .bmode_pd_lower_bound_reg = R_BMODE_PDTH_V1, | |
| 191 | + .bmode_rssi_nocca_low_th_mask = B_BMODE_PDTH_LOWER_BOUND_MSK_V1, | |
| 188 | 192 | .p0_lna_init = {R_PATH0_LNA_INIT_V1, B_PATH0_LNA_INIT_IDX_MSK}, |
| 189 | 193 | .p1_lna_init = {R_PATH1_LNA_INIT_V1, B_PATH1_LNA_INIT_IDX_MSK}, |
| 190 | 194 | .p0_tia_init = {R_PATH0_TIA_INIT_V1, B_PATH0_TIA_INIT_IDX_MSK_V1}, |
| @@ -756,9 +760,9 @@ static void rtw8851b_set_channel_mac(struct rtw89_dev *rtwdev, · 565 unmodified lines | ||
| 756 | 760 | const struct rtw89_chan *chan, |
| 757 | 761 | u8 mac_idx) |
| 758 | 762 | { |
| 759 | − u32 sub_carr = rtw89_mac_reg_by_idx(R_AX_TX_SUB_CARRIER_VALUE, mac_idx); | |
| 760 | − u32 chk_rate = rtw89_mac_reg_by_idx(R_AX_TXRATE_CHK, mac_idx); | |
| 761 | − u32 rf_mod = rtw89_mac_reg_by_idx(R_AX_WMAC_RFMOD, mac_idx); | |
| 763 | + u32 sub_carr = rtw89_mac_reg_by_idx(rtwdev, R_AX_TX_SUB_CARRIER_VALUE, mac_idx); | |
| 764 | + u32 chk_rate = rtw89_mac_reg_by_idx(rtwdev, R_AX_TXRATE_CHK, mac_idx); | |
| 765 | + u32 rf_mod = rtw89_mac_reg_by_idx(rtwdev, R_AX_WMAC_RFMOD, mac_idx); | |
| 762 | 766 | u8 txsc20 = 0, txsc40 = 0; |
| 763 | 767 | |
| 764 | 768 | switch (chan->band_width) { |
| @@ -1740,14 +1744,14 @@ void rtw8851b_set_txpwr_ul_tb_offset(struct rtw89_dev *rtwdev, · 975 unmodified lines | ||
| 1740 | 1744 | return; |
| 1741 | 1745 | } |
| 1742 | 1746 | |
| 1743 | − reg = rtw89_mac_reg_by_idx(R_AX_PWR_UL_TB_CTRL, mac_idx); | |
| 1747 | + reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_PWR_UL_TB_CTRL, mac_idx); | |
| 1744 | 1748 | rtw89_write32_set(rtwdev, reg, B_AX_PWR_UL_TB_CTRL_EN); |
| 1745 | 1749 | |
| 1746 | − reg = rtw89_mac_reg_by_idx(R_AX_PWR_UL_TB_1T, mac_idx); | |
| 1750 | + reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_PWR_UL_TB_1T, mac_idx); | |
| 1747 | 1751 | rtw89_write32_mask(rtwdev, reg, B_AX_PWR_UL_TB_1T_MASK, pw_ofst); |
| 1748 | 1752 | |
| 1749 | 1753 | pw_ofst = max_t(s8, pw_ofst - 3, -16); |
| 1750 | − reg = rtw89_mac_reg_by_idx(R_AX_PWR_UL_TB_2T, mac_idx); | |
| 1754 | + reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_PWR_UL_TB_2T, mac_idx); | |
| 1751 | 1755 | rtw89_write32_mask(rtwdev, reg, B_AX_PWR_UL_TB_2T_MASK, pw_ofst); |
| 1752 | 1756 | } |
| 1753 | 1757 | |
| @@ -2336,6 +2340,8 @@ const struct rtw89_chip_info rtw8851b_chip_info = { · 582 unmodified lines | ||
| 2336 | 2340 | .chip_id = RTL8851B, |
| 2337 | 2341 | .chip_gen = RTW89_CHIP_AX, |
| 2338 | 2342 | .ops = &rtw8851b_chip_ops, |
| 2343 | + .mac_def = &rtw89_mac_gen_ax, | |
| 2344 | + .phy_def = &rtw89_phy_gen_ax, | |
| 2339 | 2345 | .fw_basename = RTW8851B_FW_BASENAME, |
| 2340 | 2346 | .fw_format_max = RTW8851B_FW_FORMAT_MAX, |
| 2341 | 2347 | .try_ce_fw = true, |
| @@ -478,6 +478,10 @@ static const struct rtw89_dig_regs rtw8852a_dig_regs = { · 477 unmodified lines | ||
| 478 | 478 | .seg0_pd_reg = R_SEG0R_PD, |
| 479 | 479 | .pd_lower_bound_mask = B_SEG0R_PD_LOWER_BOUND_MSK, |
| 480 | 480 | .pd_spatial_reuse_en = B_SEG0R_PD_SPATIAL_REUSE_EN_MSK, |
| 481 | + .bmode_pd_reg = R_BMODE_PDTH_EN_V1, | |
| 482 | + .bmode_cca_rssi_limit_en = B_BMODE_PDTH_LIMIT_EN_MSK_V1, | |
| 483 | + .bmode_pd_lower_bound_reg = R_BMODE_PDTH_V1, | |
| 484 | + .bmode_rssi_nocca_low_th_mask = B_BMODE_PDTH_LOWER_BOUND_MSK_V1, | |
| 481 | 485 | .p0_lna_init = {R_PATH0_LNA_INIT, B_PATH0_LNA_INIT_IDX_MSK}, |
| 482 | 486 | .p1_lna_init = {R_PATH1_LNA_INIT, B_PATH1_LNA_INIT_IDX_MSK}, |
| 483 | 487 | .p0_tia_init = {R_PATH0_TIA_INIT, B_PATH0_TIA_INIT_IDX_MSK}, |
| @@ -704,10 +708,9 @@ static void rtw8852a_set_channel_mac(struct rtw89_dev *rtwdev, · 220 unmodified lines | ||
| 704 | 708 | const struct rtw89_chan *chan, |
| 705 | 709 | u8 mac_idx) |
| 706 | 710 | { |
| 707 | − u32 rf_mod = rtw89_mac_reg_by_idx(R_AX_WMAC_RFMOD, mac_idx); | |
| 708 | − u32 sub_carr = rtw89_mac_reg_by_idx(R_AX_TX_SUB_CARRIER_VALUE, | |
| 709 | − mac_idx); | |
| 710 | − u32 chk_rate = rtw89_mac_reg_by_idx(R_AX_TXRATE_CHK, mac_idx); | |
| 711 | + u32 rf_mod = rtw89_mac_reg_by_idx(rtwdev, R_AX_WMAC_RFMOD, mac_idx); | |
| 712 | + u32 sub_carr = rtw89_mac_reg_by_idx(rtwdev, R_AX_TX_SUB_CARRIER_VALUE, mac_idx); | |
| 713 | + u32 chk_rate = rtw89_mac_reg_by_idx(rtwdev, R_AX_TXRATE_CHK, mac_idx); | |
| 711 | 714 | u8 txsc20 = 0, txsc40 = 0; |
| 712 | 715 | |
| 713 | 716 | switch (chan->band_width) { |
| @@ -1380,13 +1383,13 @@ void rtw8852a_set_txpwr_ul_tb_offset(struct rtw89_dev *rtwdev, · 666 unmodified lines | ||
| 1380 | 1383 | pw_ofst); |
| 1381 | 1384 | return; |
| 1382 | 1385 | } |
| 1383 | − reg = rtw89_mac_reg_by_idx(R_AX_PWR_UL_TB_CTRL, mac_idx); | |
| 1386 | + reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_PWR_UL_TB_CTRL, mac_idx); | |
| 1384 | 1387 | rtw89_write32_set(rtwdev, reg, B_AX_PWR_UL_TB_CTRL_EN); |
| 1385 | 1388 | val_1t = pw_ofst; |
| 1386 | − reg = rtw89_mac_reg_by_idx(R_AX_PWR_UL_TB_1T, mac_idx); | |
| 1389 | + reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_PWR_UL_TB_1T, mac_idx); | |
| 1387 | 1390 | rtw89_write32_mask(rtwdev, reg, B_AX_PWR_UL_TB_1T_MASK, val_1t); |
| 1388 | 1391 | val_2t = max(val_1t - 3, -16); |
| 1389 | − reg = rtw89_mac_reg_by_idx(R_AX_PWR_UL_TB_2T, mac_idx); | |
| 1392 | + reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_PWR_UL_TB_2T, mac_idx); | |
| 1390 | 1393 | rtw89_write32_mask(rtwdev, reg, B_AX_PWR_UL_TB_2T_MASK, val_2t); |
| 1391 | 1394 | rtw89_debug(rtwdev, RTW89_DBG_TXPWR, "[ULTB] Set TB pwr_offset=(%d, %d)\n", |
| 1392 | 1395 | val_1t, val_2t); |
| @@ -2073,6 +2076,8 @@ const struct rtw89_chip_info rtw8852a_chip_info = { · 680 unmodified lines | ||
| 2073 | 2076 | .chip_id = RTL8852A, |
| 2074 | 2077 | .chip_gen = RTW89_CHIP_AX, |
| 2075 | 2078 | .ops = &rtw8852a_chip_ops, |
| 2079 | + .mac_def = &rtw89_mac_gen_ax, | |
| 2080 | + .phy_def = &rtw89_phy_gen_ax, | |
| 2076 | 2081 | .fw_basename = RTW8852A_FW_BASENAME, |
| 2077 | 2082 | .fw_format_max = RTW8852A_FW_FORMAT_MAX, |
| 2078 | 2083 | .try_ce_fw = false, |
| @@ -310,6 +310,10 @@ static const struct rtw89_dig_regs rtw8852b_dig_regs = { · 309 unmodified lines | ||
| 310 | 310 | .seg0_pd_reg = R_SEG0R_PD_V1, |
| 311 | 311 | .pd_lower_bound_mask = B_SEG0R_PD_LOWER_BOUND_MSK, |
| 312 | 312 | .pd_spatial_reuse_en = B_SEG0R_PD_SPATIAL_REUSE_EN_MSK_V1, |
| 313 | + .bmode_pd_reg = R_BMODE_PDTH_EN_V1, | |
| 314 | + .bmode_cca_rssi_limit_en = B_BMODE_PDTH_LIMIT_EN_MSK_V1, | |
| 315 | + .bmode_pd_lower_bound_reg = R_BMODE_PDTH_V1, | |
| 316 | + .bmode_rssi_nocca_low_th_mask = B_BMODE_PDTH_LOWER_BOUND_MSK_V1, | |
| 313 | 317 | .p0_lna_init = {R_PATH0_LNA_INIT_V1, B_PATH0_LNA_INIT_IDX_MSK}, |
| 314 | 318 | .p1_lna_init = {R_PATH1_LNA_INIT_V1, B_PATH1_LNA_INIT_IDX_MSK}, |
| 315 | 319 | .p0_tia_init = {R_PATH0_TIA_INIT_V1, B_PATH0_TIA_INIT_IDX_MSK_V1}, |
| @@ -843,9 +847,9 @@ static void rtw8852b_set_channel_mac(struct rtw89_dev *rtwdev, · 527 unmodified lines | ||
| 843 | 847 | const struct rtw89_chan *chan, |
| 844 | 848 | u8 mac_idx) |
| 845 | 849 | { |
| 846 | − u32 rf_mod = rtw89_mac_reg_by_idx(R_AX_WMAC_RFMOD, mac_idx); | |
| 847 | − u32 sub_carr = rtw89_mac_reg_by_idx(R_AX_TX_SUB_CARRIER_VALUE, mac_idx); | |
| 848 | − u32 chk_rate = rtw89_mac_reg_by_idx(R_AX_TXRATE_CHK, mac_idx); | |
| 850 | + u32 rf_mod = rtw89_mac_reg_by_idx(rtwdev, R_AX_WMAC_RFMOD, mac_idx); | |
| 851 | + u32 sub_carr = rtw89_mac_reg_by_idx(rtwdev, R_AX_TX_SUB_CARRIER_VALUE, mac_idx); | |
| 852 | + u32 chk_rate = rtw89_mac_reg_by_idx(rtwdev, R_AX_TXRATE_CHK, mac_idx); | |
| 849 | 853 | u8 txsc20 = 0, txsc40 = 0; |
| 850 | 854 | |
| 851 | 855 | switch (chan->band_width) { |
| @@ -1725,14 +1729,14 @@ void rtw8852b_set_txpwr_ul_tb_offset(struct rtw89_dev *rtwdev, · 873 unmodified lines | ||
| 1725 | 1729 | return; |
| 1726 | 1730 | } |
| 1727 | 1731 | |
| 1728 | − reg = rtw89_mac_reg_by_idx(R_AX_PWR_UL_TB_CTRL, mac_idx); | |
| 1732 | + reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_PWR_UL_TB_CTRL, mac_idx); | |
| 1729 | 1733 | rtw89_write32_set(rtwdev, reg, B_AX_PWR_UL_TB_CTRL_EN); |
| 1730 | 1734 | |
| 1731 | − reg = rtw89_mac_reg_by_idx(R_AX_PWR_UL_TB_1T, mac_idx); | |
| 1735 | + reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_PWR_UL_TB_1T, mac_idx); | |
| 1732 | 1736 | rtw89_write32_mask(rtwdev, reg, B_AX_PWR_UL_TB_1T_MASK, pw_ofst); |
| 1733 | 1737 | |
| 1734 | 1738 | pw_ofst = max_t(s8, pw_ofst - 3, -16); |
| 1735 | − reg = rtw89_mac_reg_by_idx(R_AX_PWR_UL_TB_2T, mac_idx); | |
| 1739 | + reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_PWR_UL_TB_2T, mac_idx); | |
| 1736 | 1740 | rtw89_write32_mask(rtwdev, reg, B_AX_PWR_UL_TB_2T_MASK, pw_ofst); |
| 1737 | 1741 | } |
| 1738 | 1742 | |
| @@ -2505,6 +2509,8 @@ const struct rtw89_chip_info rtw8852b_chip_info = { · 766 unmodified lines | ||
| 2505 | 2509 | .chip_id = RTL8852B, |
| 2506 | 2510 | .chip_gen = RTW89_CHIP_AX, |
| 2507 | 2511 | .ops = &rtw8852b_chip_ops, |
| 2512 | + .mac_def = &rtw89_mac_gen_ax, | |
| 2513 | + .phy_def = &rtw89_phy_gen_ax, | |
| 2508 | 2514 | .fw_basename = RTW8852B_FW_BASENAME, |
| 2509 | 2515 | .fw_format_max = RTW8852B_FW_FORMAT_MAX, |
| 2510 | 2516 | .try_ce_fw = true, |
| @@ -846,7 +846,7 @@ static bool _iqk_one_shot(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx, · 845 unmodified lines | ||
| 846 | 846 | case ID_NBTXK: |
| 847 | 847 | rtw89_phy_write32_mask(rtwdev, R_P0_RFCTM, B_P0_RFCTM_EN, 0x0); |
| 848 | 848 | rtw89_phy_write32_mask(rtwdev, R_IQK_DIF4, B_IQK_DIF4_TXT, 0x011); |
| 849 | − iqk_cmd = 0x308 | (1 << (4 + path)); | |
| 849 | + iqk_cmd = 0x408 | (1 << (4 + path)); | |
| 850 | 850 | break; |
| 851 | 851 | case ID_NBRXK: |
| 852 | 852 | rtw89_phy_write32_mask(rtwdev, R_P0_RFCTM, B_P0_RFCTM_EN, 0x1); |
| @@ -1078,7 +1078,7 @@ static bool _iqk_nbtxk(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx, u8 · 225 unmodified lines | ||
| 1078 | 1078 | { |
| 1079 | 1079 | struct rtw89_iqk_info *iqk_info = &rtwdev->iqk; |
| 1080 | 1080 | bool kfail; |
| 1081 | − u8 gp = 0x3; | |
| 1081 | + u8 gp = 0x2; | |
| 1082 | 1082 | |
| 1083 | 1083 | switch (iqk_info->iqk_band[path]) { |
| 1084 | 1084 | case RTW89_BAND_2G: |
| @@ -146,6 +146,10 @@ static const struct rtw89_dig_regs rtw8852c_dig_regs = { · 145 unmodified lines | ||
| 146 | 146 | .seg0_pd_reg = R_SEG0R_PD, |
| 147 | 147 | .pd_lower_bound_mask = B_SEG0R_PD_LOWER_BOUND_MSK, |
| 148 | 148 | .pd_spatial_reuse_en = B_SEG0R_PD_SPATIAL_REUSE_EN_MSK, |
| 149 | + .bmode_pd_reg = R_BMODE_PDTH_EN_V1, | |
| 150 | + .bmode_cca_rssi_limit_en = B_BMODE_PDTH_LIMIT_EN_MSK_V1, | |
| 151 | + .bmode_pd_lower_bound_reg = R_BMODE_PDTH_V1, | |
| 152 | + .bmode_rssi_nocca_low_th_mask = B_BMODE_PDTH_LOWER_BOUND_MSK_V1, | |
| 149 | 153 | .p0_lna_init = {R_PATH0_LNA_INIT_V1, B_PATH0_LNA_INIT_IDX_MSK}, |
| 150 | 154 | .p1_lna_init = {R_PATH1_LNA_INIT_V1, B_PATH1_LNA_INIT_IDX_MSK}, |
| 151 | 155 | .p0_tia_init = {R_PATH0_TIA_INIT_V1, B_PATH0_TIA_INIT_IDX_MSK_V1}, |
| @@ -606,10 +610,9 @@ static void rtw8852c_set_channel_mac(struct rtw89_dev *rtwdev, · 454 unmodified lines | ||
| 606 | 610 | const struct rtw89_chan *chan, |
| 607 | 611 | u8 mac_idx) |
| 608 | 612 | { |
| 609 | − u32 rf_mod = rtw89_mac_reg_by_idx(R_AX_WMAC_RFMOD, mac_idx); | |
| 610 | − u32 sub_carr = rtw89_mac_reg_by_idx(R_AX_TX_SUB_CARRIER_VALUE, | |
| 611 | − mac_idx); | |
| 612 | − u32 chk_rate = rtw89_mac_reg_by_idx(R_AX_TXRATE_CHK, mac_idx); | |
| 613 | + u32 rf_mod = rtw89_mac_reg_by_idx(rtwdev, R_AX_WMAC_RFMOD, mac_idx); | |
| 614 | + u32 sub_carr = rtw89_mac_reg_by_idx(rtwdev, R_AX_TX_SUB_CARRIER_VALUE, mac_idx); | |
| 615 | + u32 chk_rate = rtw89_mac_reg_by_idx(rtwdev, R_AX_TXRATE_CHK, mac_idx); | |
| 613 | 616 | u8 txsc20 = 0, txsc40 = 0, txsc80 = 0; |
| 614 | 617 | u8 rf_mod_val = 0, chk_rate_mask = 0; |
| 615 | 618 | u32 txsc; |
| @@ -1654,8 +1657,7 @@ static void rtw8852c_set_channel_bb(struct rtw89_dev *rtwdev, · 1038 unmodified lines | ||
| 1654 | 1657 | rtwdev->hal.cv != CHIP_CAV) { |
| 1655 | 1658 | rtw89_phy_write32_idx(rtwdev, R_P80_AT_HIGH_FREQ, |
| 1656 | 1659 | B_P80_AT_HIGH_FREQ, 0x0, phy_idx); |
| 1657 | − reg = rtw89_mac_reg_by_idx(R_P80_AT_HIGH_FREQ_BB_WRP, | |
| 1658 | − phy_idx); | |
| 1660 | + reg = rtw89_mac_reg_by_idx(rtwdev, R_P80_AT_HIGH_FREQ_BB_WRP, phy_idx); | |
| 1659 | 1661 | if (chan->primary_channel > chan->channel) { |
| 1660 | 1662 | rtw89_phy_write32_mask(rtwdev, |
| 1661 | 1663 | R_P80_AT_HIGH_FREQ_RU_ALLOC, |
| @@ -1859,12 +1861,12 @@ void rtw8852c_set_txpwr_ul_tb_offset(struct rtw89_dev *rtwdev, · 197 unmodified lines | ||
| 1859 | 1861 | |
| 1860 | 1862 | for (i = 0; i < 4; i++) { |
| 1861 | 1863 | /* 1TX */ |
| 1862 | − reg = rtw89_mac_reg_by_idx(R_AX_PWR_UL_TB_1T, mac_idx); | |
| 1864 | + reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_PWR_UL_TB_1T, mac_idx); | |
| 1863 | 1865 | rtw89_write32_mask(rtwdev, reg, |
| 1864 | 1866 | B_AX_PWR_UL_TB_1T_V1_MASK << (8 * i), |
| 1865 | 1867 | val_1t); |
| 1866 | 1868 | /* 2TX */ |
| 1867 | − reg = rtw89_mac_reg_by_idx(R_AX_PWR_UL_TB_2T, mac_idx); | |
| 1869 | + reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_PWR_UL_TB_2T, mac_idx); | |
| 1868 | 1870 | rtw89_write32_mask(rtwdev, reg, |
| 1869 | 1871 | B_AX_PWR_UL_TB_2T_V1_MASK << (8 * i), |
| 1870 | 1872 | val_2t); |
| @@ -2181,7 +2183,7 @@ static void rtw8852c_ctrl_tx_path_tmac(struct rtw89_dev *rtwdev, u8 tx_path, · 310 unmodified lines | ||
| 2181 | 2183 | |
| 2182 | 2184 | for (addr = R_AX_MACID_ANT_TABLE; |
| 2183 | 2185 | addr <= R_AX_MACID_ANT_TABLE_LAST; addr += 4) { |
| 2184 | − reg = rtw89_mac_reg_by_idx(addr, mac_idx); | |
| 2186 | + reg = rtw89_mac_reg_by_idx(rtwdev, addr, mac_idx); | |
| 2185 | 2187 | rtw89_write32(rtwdev, reg, 0); |
| 2186 | 2188 | } |
| 2187 | 2189 | |
| @@ -2211,7 +2213,7 @@ static void rtw8852c_ctrl_tx_path_tmac(struct rtw89_dev *rtwdev, u8 tx_path, · 23 unmodified lines | ||
| 2211 | 2213 | for (i = 0; i < cr_size; i++) { |
| 2212 | 2214 | rtw89_debug(rtwdev, RTW89_DBG_TSSI, "0x%x = 0x%x\n", |
| 2213 | 2215 | path_com[i].addr, path_com[i].data); |
| 2214 | − reg = rtw89_mac_reg_by_idx(path_com[i].addr, mac_idx); | |
| 2216 | + reg = rtw89_mac_reg_by_idx(rtwdev, path_com[i].addr, mac_idx); | |
| 2215 | 2217 | rtw89_write32(rtwdev, reg, path_com[i].data); |
| 2216 | 2218 | } |
| 2217 | 2219 | } |
| @@ -2804,6 +2806,8 @@ const struct rtw89_chip_info rtw8852c_chip_info = { · 586 unmodified lines | ||
| 2804 | 2806 | .chip_id = RTL8852C, |
| 2805 | 2807 | .chip_gen = RTW89_CHIP_AX, |
| 2806 | 2808 | .ops = &rtw8852c_chip_ops, |
| 2809 | + .mac_def = &rtw89_mac_gen_ax, | |
| 2810 | + .phy_def = &rtw89_phy_gen_ax, | |
| 2807 | 2811 | .fw_basename = RTW8852C_FW_BASENAME, |
| 2808 | 2812 | .fw_format_max = RTW8852C_FW_FORMAT_MAX, |
| 2809 | 2813 | .try_ce_fw = false, |
| @@ -2,9 +2,16 @@ · 1 unmodified line | ||
| 2 | 2 | /* Copyright(c) 2019-2020 Realtek Corporation |
| 3 | 3 | */ |
| 4 | 4 | |
| 5 | +#include "acpi.h" | |
| 5 | 6 | #include "debug.h" |
| 7 | +#include "phy.h" | |
| 8 | +#include "reg.h" | |
| 6 | 9 | #include "sar.h" |
| 7 | 10 | |
| 11 | +#define RTW89_TAS_FACTOR 2 /* unit: 0.25 dBm */ | |
| 12 | +#define RTW89_TAS_DPR_GAP (1 << RTW89_TAS_FACTOR) | |
| 13 | +#define RTW89_TAS_DELTA (2 << RTW89_TAS_FACTOR) | |
| 14 | + | |
| 8 | 15 | static enum rtw89_sar_subband rtw89_sar_get_subband(struct rtw89_dev *rtwdev, |
| 9 | 16 | u32 center_freq) |
| 10 | 17 | { |
| @@ -78,17 +85,15 @@ static const struct rtw89_sar_span rtw89_sar_overlapping_6ghz[] = { · 67 unmodified lines | ||
| 78 | 85 | RTW89_DECL_SAR_6GHZ_SPAN(6885, SUBBAND_7_H, SUBBAND_8), |
| 79 | 86 | }; |
| 80 | 87 | |
| 81 | −static int rtw89_query_sar_config_common(struct rtw89_dev *rtwdev, s32 *cfg) | |
| 88 | +static int rtw89_query_sar_config_common(struct rtw89_dev *rtwdev, | |
| 89 | + u32 center_freq, s32 *cfg) | |
| 82 | 90 | { |
| 83 | 91 | struct rtw89_sar_cfg_common *rtwsar = &rtwdev->sar.cfg_common; |
| 84 | − const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, RTW89_SUB_ENTITY_0); | |
| 85 | − enum rtw89_band band = chan->band_type; | |
| 86 | − u32 center_freq = chan->freq; | |
| 87 | 92 | const struct rtw89_sar_span *span = NULL; |
| 88 | 93 | enum rtw89_sar_subband subband_l, subband_h; |
| 89 | 94 | int idx; |
| 90 | 95 | |
| 91 | − if (band == RTW89_BAND_6G) { | |
| 96 | + if (center_freq >= RTW89_SAR_6GHZ_SPAN_HEAD) { | |
| 92 | 97 | idx = RTW89_SAR_6GHZ_SPAN_IDX(center_freq); |
| 93 | 98 | /* To decrease size of rtw89_sar_overlapping_6ghz[], |
| 94 | 99 | * RTW89_SAR_6GHZ_SPAN_IDX() truncates the leading NULLs |
| @@ -108,8 +113,8 @@ static int rtw89_query_sar_config_common(struct rtw89_dev *rtwdev, s32 *cfg) · 13 unmodified lines | ||
| 108 | 113 | } |
| 109 | 114 | |
| 110 | 115 | rtw89_debug(rtwdev, RTW89_DBG_SAR, |
| 111 | − "for {band %u, center_freq %u}, SAR subband: {%u, %u}\n", | |
| 112 | − band, center_freq, subband_l, subband_h); | |
| 116 | + "center_freq %u: SAR subband {%u, %u}\n", | |
| 117 | + center_freq, subband_l, subband_h); | |
| 113 | 118 | |
| 114 | 119 | if (!rtwsar->set[subband_l] && !rtwsar->set[subband_h]) |
| 115 | 120 | return -ENODATA; |
| @@ -157,11 +162,35 @@ static s8 rtw89_txpwr_sar_to_mac(struct rtw89_dev *rtwdev, u8 fct, s32 cfg) · 41 unmodified lines | ||
| 157 | 162 | RTW89_SAR_TXPWR_MAC_MAX); |
| 158 | 163 | } |
| 159 | 164 | |
| 160 | −s8 rtw89_query_sar(struct rtw89_dev *rtwdev) | |
| 165 | +static s8 rtw89_txpwr_tas_to_sar(const struct rtw89_sar_handler *sar_hdl, | |
| 166 | + s8 cfg) | |
| 167 | +{ | |
| 168 | + const u8 fct = sar_hdl->txpwr_factor_sar; | |
| 169 | + | |
| 170 | + if (fct > RTW89_TAS_FACTOR) | |
| 171 | + return cfg << (fct - RTW89_TAS_FACTOR); | |
| 172 | + else | |
| 173 | + return cfg >> (RTW89_TAS_FACTOR - fct); | |
| 174 | +} | |
| 175 | + | |
| 176 | +static s8 rtw89_txpwr_sar_to_tas(const struct rtw89_sar_handler *sar_hdl, | |
| 177 | + s8 cfg) | |
| 178 | +{ | |
| 179 | + const u8 fct = sar_hdl->txpwr_factor_sar; | |
| 180 | + | |
| 181 | + if (fct > RTW89_TAS_FACTOR) | |
| 182 | + return cfg >> (fct - RTW89_TAS_FACTOR); | |
| 183 | + else | |
| 184 | + return cfg << (RTW89_TAS_FACTOR - fct); | |
| 185 | +} | |
| 186 | + | |
| 187 | +s8 rtw89_query_sar(struct rtw89_dev *rtwdev, u32 center_freq) | |
| 161 | 188 | { |
| 162 | 189 | const enum rtw89_sar_sources src = rtwdev->sar.src; |
| 163 | 190 | /* its members are protected by rtw89_sar_set_src() */ |
| 164 | 191 | const struct rtw89_sar_handler *sar_hdl = &rtw89_sar_handlers[src]; |
| 192 | + struct rtw89_tas_info *tas = &rtwdev->tas; | |
| 193 | + s8 delta; | |
| 165 | 194 | int ret; |
| 166 | 195 | s32 cfg; |
| 167 | 196 | u8 fct; |
| @@ -171,16 +200,30 @@ s8 rtw89_query_sar(struct rtw89_dev *rtwdev) · 3 unmodified lines | ||
| 171 | 200 | if (src == RTW89_SAR_SOURCE_NONE) |
| 172 | 201 | return RTW89_SAR_TXPWR_MAC_MAX; |
| 173 | 202 | |
| 174 | − ret = sar_hdl->query_sar_config(rtwdev, &cfg); | |
| 203 | + ret = sar_hdl->query_sar_config(rtwdev, center_freq, &cfg); | |
| 175 | 204 | if (ret) |
| 176 | 205 | return RTW89_SAR_TXPWR_MAC_MAX; |
| 177 | 206 | |
| 207 | + if (tas->enable) { | |
| 208 | + switch (tas->state) { | |
| 209 | + case RTW89_TAS_STATE_DPR_OFF: | |
| 210 | + return RTW89_SAR_TXPWR_MAC_MAX; | |
| 211 | + case RTW89_TAS_STATE_DPR_ON: | |
| 212 | + delta = rtw89_txpwr_tas_to_sar(sar_hdl, tas->delta); | |
| 213 | + cfg -= delta; | |
| 214 | + break; | |
| 215 | + case RTW89_TAS_STATE_DPR_FORBID: | |
| 216 | + default: | |
| 217 | + break; | |
| 218 | + } | |
| 219 | + } | |
| 220 | + | |
| 178 | 221 | fct = sar_hdl->txpwr_factor_sar; |
| 179 | 222 | |
| 180 | 223 | return rtw89_txpwr_sar_to_mac(rtwdev, fct, cfg); |
| 181 | 224 | } |
| 182 | 225 | |
| 183 | −void rtw89_print_sar(struct seq_file *m, struct rtw89_dev *rtwdev) | |
| 226 | +void rtw89_print_sar(struct seq_file *m, struct rtw89_dev *rtwdev, u32 center_freq) | |
| 184 | 227 | { |
| 185 | 228 | const enum rtw89_sar_sources src = rtwdev->sar.src; |
| 186 | 229 | /* its members are protected by rtw89_sar_set_src() */ |
| @@ -199,7 +242,7 @@ void rtw89_print_sar(struct seq_file *m, struct rtw89_dev *rtwdev) · 12 unmodified lines | ||
| 199 | 242 | |
| 200 | 243 | seq_printf(m, "source: %d (%s)\n", src, sar_hdl->descr_sar_source); |
| 201 | 244 | |
| 202 | − ret = sar_hdl->query_sar_config(rtwdev, &cfg); | |
| 245 | + ret = sar_hdl->query_sar_config(rtwdev, center_freq, &cfg); | |
| 203 | 246 | if (ret) { |
| 204 | 247 | seq_printf(m, "config: return code: %d\n", ret); |
| 205 | 248 | seq_printf(m, "assign: max setting: %d (unit: 1/%lu dBm)\n", |
| @@ -212,6 +255,19 @@ void rtw89_print_sar(struct seq_file *m, struct rtw89_dev *rtwdev) · 6 unmodified lines | ||
| 212 | 255 | seq_printf(m, "config: %d (unit: 1/%lu dBm)\n", cfg, BIT(fct)); |
| 213 | 256 | } |
| 214 | 257 | |
| 258 | +void rtw89_print_tas(struct seq_file *m, struct rtw89_dev *rtwdev) | |
| 259 | +{ | |
| 260 | + struct rtw89_tas_info *tas = &rtwdev->tas; | |
| 261 | + | |
| 262 | + if (!tas->enable) { | |
| 263 | + seq_puts(m, "no TAS is applied\n"); | |
| 264 | + return; | |
| 265 | + } | |
| 266 | + | |
| 267 | + seq_printf(m, "DPR gap: %d\n", tas->dpr_gap); | |
| 268 | + seq_printf(m, "TAS delta: %d\n", tas->delta); | |
| 269 | +} | |
| 270 | + | |
| 215 | 271 | static int rtw89_apply_sar_common(struct rtw89_dev *rtwdev, |
| 216 | 272 | const struct rtw89_sar_cfg_common *sar) |
| 217 | 273 | { |
| @@ -292,3 +348,145 @@ int rtw89_ops_set_sar_specs(struct ieee80211_hw *hw, · 74 unmodified lines | ||
| 292 | 348 | |
| 293 | 349 | return rtw89_apply_sar_common(rtwdev, &sar_common); |
| 294 | 350 | } |
| 351 | + | |
| 352 | +static void rtw89_tas_state_update(struct rtw89_dev *rtwdev) | |
| 353 | +{ | |
| 354 | + const enum rtw89_sar_sources src = rtwdev->sar.src; | |
| 355 | + /* its members are protected by rtw89_sar_set_src() */ | |
| 356 | + const struct rtw89_sar_handler *sar_hdl = &rtw89_sar_handlers[src]; | |
| 357 | + struct rtw89_tas_info *tas = &rtwdev->tas; | |
| 358 | + s32 txpwr_avg = tas->total_txpwr / RTW89_TAS_MAX_WINDOW / PERCENT; | |
| 359 | + s32 dpr_on_threshold, dpr_off_threshold, cfg; | |
| 360 | + enum rtw89_tas_state state = tas->state; | |
| 361 | + const struct rtw89_chan *chan; | |
| 362 | + int ret; | |
| 363 | + | |
| 364 | + lockdep_assert_held(&rtwdev->mutex); | |
| 365 | + | |
| 366 | + if (src == RTW89_SAR_SOURCE_NONE) | |
| 367 | + return; | |
| 368 | + | |
| 369 | + chan = rtw89_chan_get(rtwdev, RTW89_SUB_ENTITY_0); | |
| 370 | + ret = sar_hdl->query_sar_config(rtwdev, chan->freq, &cfg); | |
| 371 | + if (ret) | |
| 372 | + return; | |
| 373 | + | |
| 374 | + cfg = rtw89_txpwr_sar_to_tas(sar_hdl, cfg); | |
| 375 | + | |
| 376 | + if (tas->delta >= cfg) { | |
| 377 | + rtw89_debug(rtwdev, RTW89_DBG_SAR, | |
| 378 | + "TAS delta exceed SAR limit\n"); | |
| 379 | + state = RTW89_TAS_STATE_DPR_FORBID; | |
| 380 | + goto out; | |
| 381 | + } | |
| 382 | + | |
| 383 | + dpr_on_threshold = cfg; | |
| 384 | + dpr_off_threshold = cfg - tas->dpr_gap; | |
| 385 | + rtw89_debug(rtwdev, RTW89_DBG_SAR, | |
| 386 | + "DPR_ON thold: %d, DPR_OFF thold: %d, txpwr_avg: %d\n", | |
| 387 | + dpr_on_threshold, dpr_off_threshold, txpwr_avg); | |
| 388 | + | |
| 389 | + if (txpwr_avg >= dpr_on_threshold) | |
| 390 | + state = RTW89_TAS_STATE_DPR_ON; | |
| 391 | + else if (txpwr_avg < dpr_off_threshold) | |
| 392 | + state = RTW89_TAS_STATE_DPR_OFF; | |
| 393 | + | |
| 394 | +out: | |
| 395 | + if (tas->state == state) | |
| 396 | + return; | |
| 397 | + | |
| 398 | + rtw89_debug(rtwdev, RTW89_DBG_SAR, | |
| 399 | + "TAS old state: %d, new state: %d\n", tas->state, state); | |
| 400 | + tas->state = state; | |
| 401 | + rtw89_core_set_chip_txpwr(rtwdev); | |
| 402 | +} | |
| 403 | + | |
| 404 | +void rtw89_tas_init(struct rtw89_dev *rtwdev) | |
| 405 | +{ | |
| 406 | + struct rtw89_tas_info *tas = &rtwdev->tas; | |
| 407 | + int ret; | |
| 408 | + u8 val; | |
| 409 | + | |
| 410 | + ret = rtw89_acpi_evaluate_dsm(rtwdev, RTW89_ACPI_DSM_FUNC_TAS_EN, &val); | |
| 411 | + if (ret) { | |
| 412 | + rtw89_debug(rtwdev, RTW89_DBG_SAR, | |
| 413 | + "acpi: cannot get TAS: %d\n", ret); | |
| 414 | + return; | |
| 415 | + } | |
| 416 | + | |
| 417 | + switch (val) { | |
| 418 | + case 0: | |
| 419 | + tas->enable = false; | |
| 420 | + break; | |
| 421 | + case 1: | |
| 422 | + tas->enable = true; | |
| 423 | + break; | |
| 424 | + default: | |
| 425 | + break; | |
| 426 | + } | |
| 427 | + | |
| 428 | + if (!tas->enable) { | |
| 429 | + rtw89_debug(rtwdev, RTW89_DBG_SAR, "TAS not enable\n"); | |
| 430 | + return; | |
| 431 | + } | |
| 432 | + | |
| 433 | + tas->dpr_gap = RTW89_TAS_DPR_GAP; | |
| 434 | + tas->delta = RTW89_TAS_DELTA; | |
| 435 | +} | |
| 436 | + | |
| 437 | +void rtw89_tas_reset(struct rtw89_dev *rtwdev) | |
| 438 | +{ | |
| 439 | + struct rtw89_tas_info *tas = &rtwdev->tas; | |
| 440 | + | |
| 441 | + if (!tas->enable) | |
| 442 | + return; | |
| 443 | + | |
| 444 | + memset(&tas->txpwr_history, 0, sizeof(tas->txpwr_history)); | |
| 445 | + tas->total_txpwr = 0; | |
| 446 | + tas->cur_idx = 0; | |
| 447 | + tas->state = RTW89_TAS_STATE_DPR_OFF; | |
| 448 | +} | |
| 449 | + | |
| 450 | +static const struct rtw89_reg_def txpwr_regs[] = { | |
| 451 | + {R_PATH0_TXPWR, B_PATH0_TXPWR}, | |
| 452 | + {R_PATH1_TXPWR, B_PATH1_TXPWR}, | |
| 453 | +}; | |
| 454 | + | |
| 455 | +void rtw89_tas_track(struct rtw89_dev *rtwdev) | |
| 456 | +{ | |
| 457 | + struct rtw89_env_monitor_info *env = &rtwdev->env_monitor; | |
| 458 | + const enum rtw89_sar_sources src = rtwdev->sar.src; | |
| 459 | + u8 max_nss_num = rtwdev->chip->rf_path_num; | |
| 460 | + struct rtw89_tas_info *tas = &rtwdev->tas; | |
| 461 | + s16 tmp, txpwr, instant_txpwr = 0; | |
| 462 | + u32 val; | |
| 463 | + int i; | |
| 464 | + | |
| 465 | + if (!tas->enable || src == RTW89_SAR_SOURCE_NONE) | |
| 466 | + return; | |
| 467 | + | |
| 468 | + if (env->ccx_watchdog_result != RTW89_PHY_ENV_MON_IFS_CLM) | |
| 469 | + return; | |
| 470 | + | |
| 471 | + for (i = 0; i < max_nss_num; i++) { | |
| 472 | + val = rtw89_phy_read32_mask(rtwdev, txpwr_regs[i].addr, | |
| 473 | + txpwr_regs[i].mask); | |
| 474 | + tmp = sign_extend32(val, 8); | |
| 475 | + if (tmp <= 0) | |
| 476 | + return; | |
| 477 | + instant_txpwr += tmp; | |
| 478 | + } | |
| 479 | + | |
| 480 | + instant_txpwr /= max_nss_num; | |
| 481 | + /* in unit of 0.25 dBm multiply by percentage */ | |
| 482 | + txpwr = instant_txpwr * env->ifs_clm_tx_ratio; | |
| 483 | + tas->total_txpwr += txpwr - tas->txpwr_history[tas->cur_idx]; | |
| 484 | + tas->txpwr_history[tas->cur_idx] = txpwr; | |
| 485 | + rtw89_debug(rtwdev, RTW89_DBG_SAR, | |
| 486 | + "instant_txpwr: %d, tx_ratio: %d, txpwr: %d\n", | |
| 487 | + instant_txpwr, env->ifs_clm_tx_ratio, txpwr); | |
| 488 | + | |
| 489 | + tas->cur_idx = (tas->cur_idx + 1) % RTW89_TAS_MAX_WINDOW; | |
| 490 | + | |
| 491 | + rtw89_tas_state_update(rtwdev); | |
| 492 | +} | |
| @@ -13,14 +13,18 @@ · 12 unmodified lines | ||
| 13 | 13 | struct rtw89_sar_handler { |
| 14 | 14 | const char *descr_sar_source; |
| 15 | 15 | u8 txpwr_factor_sar; |
| 16 | − int (*query_sar_config)(struct rtw89_dev *rtwdev, s32 *cfg); | |
| 16 | + int (*query_sar_config)(struct rtw89_dev *rtwdev, u32 center_freq, s32 *cfg); | |
| 17 | 17 | }; |
| 18 | 18 | |
| 19 | 19 | extern const struct cfg80211_sar_capa rtw89_sar_capa; |
| 20 | 20 | |
| 21 | −s8 rtw89_query_sar(struct rtw89_dev *rtwdev); | |
| 22 | −void rtw89_print_sar(struct seq_file *m, struct rtw89_dev *rtwdev); | |
| 21 | +s8 rtw89_query_sar(struct rtw89_dev *rtwdev, u32 center_freq); | |
| 22 | +void rtw89_print_sar(struct seq_file *m, struct rtw89_dev *rtwdev, u32 center_freq); | |
| 23 | +void rtw89_print_tas(struct seq_file *m, struct rtw89_dev *rtwdev); | |
| 23 | 24 | int rtw89_ops_set_sar_specs(struct ieee80211_hw *hw, |
| 24 | 25 | const struct cfg80211_sar_specs *sar); |
| 26 | +void rtw89_tas_init(struct rtw89_dev *rtwdev); | |
| 27 | +void rtw89_tas_reset(struct rtw89_dev *rtwdev); | |
| 28 | +void rtw89_tas_track(struct rtw89_dev *rtwdev); | |
| 25 | 29 | |
| 26 | 30 | #endif |
| @@ -529,6 +529,9 @@ static void ser_do_hci_st_hdl(struct rtw89_ser *ser, u8 evt) · 528 unmodified lines | ||
| 529 | 529 | static void ser_mac_mem_dump(struct rtw89_dev *rtwdev, u8 *buf, |
| 530 | 530 | u8 sel, u32 start_addr, u32 len) |
| 531 | 531 | { |
| 532 | + const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; | |
| 533 | + u32 filter_model_addr = mac->filter_model_addr; | |
| 534 | + u32 indir_access_addr = mac->indir_access_addr; | |
| 532 | 535 | u32 *ptr = (u32 *)buf; |
| 533 | 536 | u32 base_addr, start_page, residue; |
| 534 | 537 | u32 cnt = 0; |
| @@ -536,14 +539,14 @@ static void ser_mac_mem_dump(struct rtw89_dev *rtwdev, u8 *buf, · 1 unmodified line | ||
| 536 | 539 | |
| 537 | 540 | start_page = start_addr / MAC_MEM_DUMP_PAGE_SIZE; |
| 538 | 541 | residue = start_addr % MAC_MEM_DUMP_PAGE_SIZE; |
| 539 | − base_addr = rtw89_mac_mem_base_addrs[sel]; | |
| 542 | + base_addr = mac->mem_base_addrs[sel]; | |
| 540 | 543 | base_addr += start_page * MAC_MEM_DUMP_PAGE_SIZE; |
| 541 | 544 | |
| 542 | 545 | while (cnt < len) { |
| 543 | − rtw89_write32(rtwdev, R_AX_FILTER_MODEL_ADDR, base_addr); | |
| 546 | + rtw89_write32(rtwdev, filter_model_addr, base_addr); | |
| 544 | 547 | |
| 545 | − for (i = R_AX_INDIR_ACCESS_ENTRY + residue; | |
| 546 | − i < R_AX_INDIR_ACCESS_ENTRY + MAC_MEM_DUMP_PAGE_SIZE; | |
| 548 | + for (i = indir_access_addr + residue; | |
| 549 | + i < indir_access_addr + MAC_MEM_DUMP_PAGE_SIZE; | |
| 547 | 550 | i += 4, ptr++) { |
| 548 | 551 | *ptr = rtw89_read32(rtwdev, i); |
| 549 | 552 | cnt += 4; |
| @@ -585,6 +588,9 @@ static int rtw89_ser_fw_backtrace_dump(struct rtw89_dev *rtwdev, u8 *buf, · 35 unmodified lines | ||
| 585 | 588 | const struct __fw_backtrace_entry *ent) |
| 586 | 589 | { |
| 587 | 590 | struct __fw_backtrace_info *ptr = (struct __fw_backtrace_info *)buf; |
| 591 | + const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; | |
| 592 | + u32 filter_model_addr = mac->filter_model_addr; | |
| 593 | + u32 indir_access_addr = mac->indir_access_addr; | |
| 588 | 594 | u32 fwbt_addr = ent->wcpu_addr & RTW89_WCPU_BASE_MASK; |
| 589 | 595 | u32 fwbt_size = ent->size; |
| 590 | 596 | u32 fwbt_key = ent->key; |
| @@ -610,10 +616,10 @@ static int rtw89_ser_fw_backtrace_dump(struct rtw89_dev *rtwdev, u8 *buf, · 19 unmodified lines | ||
| 610 | 616 | } |
| 611 | 617 | |
| 612 | 618 | rtw89_debug(rtwdev, RTW89_DBG_SER, "dump fw backtrace start\n"); |
| 613 | − rtw89_write32(rtwdev, R_AX_FILTER_MODEL_ADDR, fwbt_addr); | |
| 619 | + rtw89_write32(rtwdev, filter_model_addr, fwbt_addr); | |
| 614 | 620 | |
| 615 | − for (i = R_AX_INDIR_ACCESS_ENTRY; | |
| 616 | − i < R_AX_INDIR_ACCESS_ENTRY + fwbt_size; | |
| 621 | + for (i = indir_access_addr; | |
| 622 | + i < indir_access_addr + fwbt_size; | |
| 617 | 623 | i += RTW89_FW_BACKTRACE_INFO_SIZE, ptr++) { |
| 618 | 624 | *ptr = (struct __fw_backtrace_info){ |
| 619 | 625 | .ra = rtw89_read32(rtwdev, i), |
| @@ -40,6 +40,7 @@ static void rtw89_wow_leave_lps(struct rtw89_dev *rtwdev) · 39 unmodified lines | ||
| 40 | 40 | |
| 41 | 41 | static int rtw89_wow_config_mac(struct rtw89_dev *rtwdev, bool enable_wow) |
| 42 | 42 | { |
| 43 | + const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; | |
| 43 | 44 | int ret; |
| 44 | 45 | |
| 45 | 46 | if (enable_wow) { |
| @@ -49,7 +50,7 @@ static int rtw89_wow_config_mac(struct rtw89_dev *rtwdev, bool enable_wow) · 3 unmodified lines | ||
| 49 | 50 | return ret; |
| 50 | 51 | } |
| 51 | 52 | rtw89_write32_set(rtwdev, R_AX_RX_FUNCTION_STOP, B_AX_HDR_RX_STOP); |
| 52 | − rtw89_write32_clr(rtwdev, R_AX_RX_FLTR_OPT, B_AX_SNIFFER_MODE); | |
| 53 | + rtw89_write32_clr(rtwdev, mac->rx_fltr, B_AX_SNIFFER_MODE); | |
| 53 | 54 | rtw89_mac_cfg_ppdu_status(rtwdev, RTW89_MAC_0, false); |
| 54 | 55 | rtw89_write32(rtwdev, R_AX_ACTION_FWD0, 0); |
| 55 | 56 | rtw89_write32(rtwdev, R_AX_ACTION_FWD1, 0); |
| @@ -52,8 +52,7 @@ static void rsi_coex_sched_tx_pkts(struct rsi_coex_ctrl_block *coex_cb) · 51 unmodified lines | ||
| 52 | 52 | |
| 53 | 53 | static void rsi_coex_scheduler_thread(struct rsi_common *common) |
| 54 | 54 | { |
| 55 | − struct rsi_coex_ctrl_block *coex_cb = | |
| 56 | − (struct rsi_coex_ctrl_block *)common->coex_cb; | |
| 55 | + struct rsi_coex_ctrl_block *coex_cb = common->coex_cb; | |
| 57 | 56 | u32 timeout = EVENT_WAIT_FOREVER; |
| 58 | 57 | |
| 59 | 58 | do { |
| @@ -100,9 +99,8 @@ static inline int rsi_map_coex_q(u8 hal_queue) · 40 unmodified lines | ||
| 100 | 99 | |
| 101 | 100 | int rsi_coex_send_pkt(void *priv, struct sk_buff *skb, u8 hal_queue) |
| 102 | 101 | { |
| 103 | − struct rsi_common *common = (struct rsi_common *)priv; | |
| 104 | − struct rsi_coex_ctrl_block *coex_cb = | |
| 105 | − (struct rsi_coex_ctrl_block *)common->coex_cb; | |
| 102 | + struct rsi_common *common = priv; | |
| 103 | + struct rsi_coex_ctrl_block *coex_cb = common->coex_cb; | |
| 106 | 104 | struct skb_info *tx_params = NULL; |
| 107 | 105 | enum rsi_coex_queues coex_q; |
| 108 | 106 | int status; |
| @@ -168,8 +166,7 @@ int rsi_coex_attach(struct rsi_common *common) · 59 unmodified lines | ||
| 168 | 166 | |
| 169 | 167 | void rsi_coex_detach(struct rsi_common *common) |
| 170 | 168 | { |
| 171 | − struct rsi_coex_ctrl_block *coex_cb = | |
| 172 | − (struct rsi_coex_ctrl_block *)common->coex_cb; | |
| 169 | + struct rsi_coex_ctrl_block *coex_cb = common->coex_cb; | |
| 173 | 170 | int cnt; |
| 174 | 171 | |
| 175 | 172 | rsi_kill_thread(&coex_cb->coex_tx_thread); |
| @@ -28,8 +28,7 @@ static int rsi_sdio_stats_read(struct seq_file *seq, void *data) · 27 unmodified lines | ||
| 28 | 28 | { |
| 29 | 29 | struct rsi_common *common = seq->private; |
| 30 | 30 | struct rsi_hw *adapter = common->priv; |
| 31 | − struct rsi_91x_sdiodev *dev = | |
| 32 | − (struct rsi_91x_sdiodev *)adapter->rsi_dev; | |
| 31 | + struct rsi_91x_sdiodev *dev = adapter->rsi_dev; | |
| 33 | 32 | |
| 34 | 33 | seq_printf(seq, "total_sdio_interrupts: %d\n", |
| 35 | 34 | dev->rx_info.sdio_int_counter); |
| @@ -424,7 +424,7 @@ out: · 423 unmodified lines | ||
| 424 | 424 | |
| 425 | 425 | int rsi_prepare_beacon(struct rsi_common *common, struct sk_buff *skb) |
| 426 | 426 | { |
| 427 | − struct rsi_hw *adapter = (struct rsi_hw *)common->priv; | |
| 427 | + struct rsi_hw *adapter = common->priv; | |
| 428 | 428 | struct rsi_data_desc *bcn_frm; |
| 429 | 429 | struct ieee80211_hw *hw = common->priv->hw; |
| 430 | 430 | struct ieee80211_conf *conf = &hw->conf; |
| @@ -1763,8 +1763,8 @@ static int rsi_mac80211_roc(struct ieee80211_hw *hw, struct ieee80211_vif *vif, · 1762 unmodified lines | ||
| 1763 | 1763 | struct ieee80211_channel *chan, int duration, |
| 1764 | 1764 | enum ieee80211_roc_type type) |
| 1765 | 1765 | { |
| 1766 | − struct rsi_hw *adapter = (struct rsi_hw *)hw->priv; | |
| 1767 | − struct rsi_common *common = (struct rsi_common *)adapter->priv; | |
| 1766 | + struct rsi_hw *adapter = hw->priv; | |
| 1767 | + struct rsi_common *common = adapter->priv; | |
| 1768 | 1768 | int status = 0; |
| 1769 | 1769 | |
| 1770 | 1770 | rsi_dbg(INFO_ZONE, "***** Remain on channel *****\n"); |
| @@ -270,14 +270,14 @@ static void rsi_tx_scheduler_thread(struct rsi_common *common) · 269 unmodified lines | ||
| 270 | 270 | #ifdef CONFIG_RSI_COEX |
| 271 | 271 | enum rsi_host_intf rsi_get_host_intf(void *priv) |
| 272 | 272 | { |
| 273 | − struct rsi_common *common = (struct rsi_common *)priv; | |
| 273 | + struct rsi_common *common = priv; | |
| 274 | 274 | |
| 275 | 275 | return common->priv->rsi_host_intf; |
| 276 | 276 | } |
| 277 | 277 | |
| 278 | 278 | void rsi_set_bt_context(void *priv, void *bt_context) |
| 279 | 279 | { |
| 280 | − struct rsi_common *common = (struct rsi_common *)priv; | |
| 280 | + struct rsi_common *common = priv; | |
| 281 | 281 | |
| 282 | 282 | common->bt_adapter = bt_context; |
| 283 | 283 | } |
| @@ -144,8 +144,7 @@ static int rsi_issue_sdiocommand(struct sdio_func *func, · 143 unmodified lines | ||
| 144 | 144 | static void rsi_handle_interrupt(struct sdio_func *function) |
| 145 | 145 | { |
| 146 | 146 | struct rsi_hw *adapter = sdio_get_drvdata(function); |
| 147 | − struct rsi_91x_sdiodev *dev = | |
| 148 | − (struct rsi_91x_sdiodev *)adapter->rsi_dev; | |
| 147 | + struct rsi_91x_sdiodev *dev = adapter->rsi_dev; | |
| 149 | 148 | |
| 150 | 149 | if (adapter->priv->fsm_state == FSM_FW_NOT_LOADED) |
| 151 | 150 | return; |
| @@ -337,8 +336,7 @@ static void rsi_reset_card(struct sdio_func *pfunction) · 185 unmodified lines | ||
| 337 | 336 | */ |
| 338 | 337 | static void rsi_setclock(struct rsi_hw *adapter, u32 freq) |
| 339 | 338 | { |
| 340 | − struct rsi_91x_sdiodev *dev = | |
| 341 | − (struct rsi_91x_sdiodev *)adapter->rsi_dev; | |
| 339 | + struct rsi_91x_sdiodev *dev = adapter->rsi_dev; | |
| 342 | 340 | struct mmc_host *host = dev->pfunction->card->host; |
| 343 | 341 | u32 clock; |
| 344 | 342 | |
| @@ -358,8 +356,7 @@ static void rsi_setclock(struct rsi_hw *adapter, u32 freq) · 13 unmodified lines | ||
| 358 | 356 | */ |
| 359 | 357 | static int rsi_setblocklength(struct rsi_hw *adapter, u32 length) |
| 360 | 358 | { |
| 361 | − struct rsi_91x_sdiodev *dev = | |
| 362 | − (struct rsi_91x_sdiodev *)adapter->rsi_dev; | |
| 359 | + struct rsi_91x_sdiodev *dev = adapter->rsi_dev; | |
| 363 | 360 | int status; |
| 364 | 361 | rsi_dbg(INIT_ZONE, "%s: Setting the block length\n", __func__); |
| 365 | 362 | |
| @@ -380,8 +377,7 @@ static int rsi_setblocklength(struct rsi_hw *adapter, u32 length) · 14 unmodified lines | ||
| 380 | 377 | */ |
| 381 | 378 | static int rsi_setupcard(struct rsi_hw *adapter) |
| 382 | 379 | { |
| 383 | − struct rsi_91x_sdiodev *dev = | |
| 384 | − (struct rsi_91x_sdiodev *)adapter->rsi_dev; | |
| 380 | + struct rsi_91x_sdiodev *dev = adapter->rsi_dev; | |
| 385 | 381 | int status = 0; |
| 386 | 382 | |
| 387 | 383 | rsi_setclock(adapter, 50000); |
| @@ -407,8 +403,7 @@ int rsi_sdio_read_register(struct rsi_hw *adapter, · 19 unmodified lines | ||
| 407 | 403 | u32 addr, |
| 408 | 404 | u8 *data) |
| 409 | 405 | { |
| 410 | − struct rsi_91x_sdiodev *dev = | |
| 411 | − (struct rsi_91x_sdiodev *)adapter->rsi_dev; | |
| 406 | + struct rsi_91x_sdiodev *dev = adapter->rsi_dev; | |
| 412 | 407 | u8 fun_num = 0; |
| 413 | 408 | int status; |
| 414 | 409 | |
| @@ -441,8 +436,7 @@ int rsi_sdio_write_register(struct rsi_hw *adapter, · 26 unmodified lines | ||
| 441 | 436 | u32 addr, |
| 442 | 437 | u8 *data) |
| 443 | 438 | { |
| 444 | − struct rsi_91x_sdiodev *dev = | |
| 445 | − (struct rsi_91x_sdiodev *)adapter->rsi_dev; | |
| 439 | + struct rsi_91x_sdiodev *dev = adapter->rsi_dev; | |
| 446 | 440 | int status = 0; |
| 447 | 441 | |
| 448 | 442 | if (likely(dev->sdio_irq_task != current)) |
| @@ -495,8 +489,7 @@ static int rsi_sdio_read_register_multiple(struct rsi_hw *adapter, · 46 unmodified lines | ||
| 495 | 489 | u8 *data, |
| 496 | 490 | u16 count) |
| 497 | 491 | { |
| 498 | − struct rsi_91x_sdiodev *dev = | |
| 499 | − (struct rsi_91x_sdiodev *)adapter->rsi_dev; | |
| 492 | + struct rsi_91x_sdiodev *dev = adapter->rsi_dev; | |
| 500 | 493 | u32 status; |
| 501 | 494 | |
| 502 | 495 | if (likely(dev->sdio_irq_task != current)) |
| @@ -527,8 +520,7 @@ int rsi_sdio_write_register_multiple(struct rsi_hw *adapter, · 24 unmodified lines | ||
| 527 | 520 | u8 *data, |
| 528 | 521 | u16 count) |
| 529 | 522 | { |
| 530 | − struct rsi_91x_sdiodev *dev = | |
| 531 | − (struct rsi_91x_sdiodev *)adapter->rsi_dev; | |
| 523 | + struct rsi_91x_sdiodev *dev = adapter->rsi_dev; | |
| 532 | 524 | int status; |
| 533 | 525 | |
| 534 | 526 | if (dev->write_fail > 1) { |
| @@ -762,8 +754,7 @@ static int rsi_sdio_host_intf_write_pkt(struct rsi_hw *adapter, · 227 unmodified lines | ||
| 762 | 754 | u8 *pkt, |
| 763 | 755 | u32 len) |
| 764 | 756 | { |
| 765 | − struct rsi_91x_sdiodev *dev = | |
| 766 | − (struct rsi_91x_sdiodev *)adapter->rsi_dev; | |
| 757 | + struct rsi_91x_sdiodev *dev = adapter->rsi_dev; | |
| 767 | 758 | u32 block_size = dev->tx_blk_size; |
| 768 | 759 | u32 num_blocks, address, length; |
| 769 | 760 | u32 queueno; |
| @@ -1045,7 +1036,7 @@ static int rsi_probe(struct sdio_func *pfunction, · 275 unmodified lines | ||
| 1045 | 1036 | goto fail_free_adapter; |
| 1046 | 1037 | } |
| 1047 | 1038 | |
| 1048 | − sdev = (struct rsi_91x_sdiodev *)adapter->rsi_dev; | |
| 1039 | + sdev = adapter->rsi_dev; | |
| 1049 | 1040 | rsi_init_event(&sdev->rx_thread.event); |
| 1050 | 1041 | status = rsi_create_kthread(adapter->priv, &sdev->rx_thread, |
| 1051 | 1042 | rsi_sdio_rx_thread, "SDIO-RX-Thread"); |
| @@ -1221,7 +1212,7 @@ static void rsi_disconnect(struct sdio_func *pfunction) · 169 unmodified lines | ||
| 1221 | 1212 | if (!adapter) |
| 1222 | 1213 | return; |
| 1223 | 1214 | |
| 1224 | − dev = (struct rsi_91x_sdiodev *)adapter->rsi_dev; | |
| 1215 | + dev = adapter->rsi_dev; | |
| 1225 | 1216 | |
| 1226 | 1217 | rsi_kill_thread(&dev->rx_thread); |
| 1227 | 1218 | sdio_claim_host(pfunction); |
| @@ -1255,8 +1246,7 @@ static void rsi_disconnect(struct sdio_func *pfunction) · 27 unmodified lines | ||
| 1255 | 1246 | #ifdef CONFIG_PM |
| 1256 | 1247 | static int rsi_set_sdio_pm_caps(struct rsi_hw *adapter) |
| 1257 | 1248 | { |
| 1258 | − struct rsi_91x_sdiodev *dev = | |
| 1259 | − (struct rsi_91x_sdiodev *)adapter->rsi_dev; | |
| 1249 | + struct rsi_91x_sdiodev *dev = adapter->rsi_dev; | |
| 1260 | 1250 | struct sdio_func *func = dev->pfunction; |
| 1261 | 1251 | int ret; |
| 1262 | 1252 | |
| @@ -1407,7 +1397,7 @@ static int rsi_freeze(struct device *dev) · 144 unmodified lines | ||
| 1407 | 1397 | return -ENODEV; |
| 1408 | 1398 | } |
| 1409 | 1399 | common = adapter->priv; |
| 1410 | − sdev = (struct rsi_91x_sdiodev *)adapter->rsi_dev; | |
| 1400 | + sdev = adapter->rsi_dev; | |
| 1411 | 1401 | |
| 1412 | 1402 | if ((common->wow_flags & RSI_WOW_ENABLED) && |
| 1413 | 1403 | (common->wow_flags & RSI_WOW_NO_CONNECTION)) |
| @@ -1457,8 +1447,7 @@ static void rsi_shutdown(struct device *dev) · 43 unmodified lines | ||
| 1457 | 1447 | { |
| 1458 | 1448 | struct sdio_func *pfunction = dev_to_sdio_func(dev); |
| 1459 | 1449 | struct rsi_hw *adapter = sdio_get_drvdata(pfunction); |
| 1460 | − struct rsi_91x_sdiodev *sdev = | |
| 1461 | − (struct rsi_91x_sdiodev *)adapter->rsi_dev; | |
| 1450 | + struct rsi_91x_sdiodev *sdev = adapter->rsi_dev; | |
| 1462 | 1451 | struct ieee80211_hw *hw = adapter->hw; |
| 1463 | 1452 | |
| 1464 | 1453 | rsi_dbg(ERR_ZONE, "SDIO Bus shutdown =====>\n"); |
| @@ -88,8 +88,7 @@ void rsi_sdio_rx_thread(struct rsi_common *common) · 87 unmodified lines | ||
| 88 | 88 | static int rsi_process_pkt(struct rsi_common *common) |
| 89 | 89 | { |
| 90 | 90 | struct rsi_hw *adapter = common->priv; |
| 91 | − struct rsi_91x_sdiodev *dev = | |
| 92 | − (struct rsi_91x_sdiodev *)adapter->rsi_dev; | |
| 91 | + struct rsi_91x_sdiodev *dev = adapter->rsi_dev; | |
| 93 | 92 | u8 num_blks = 0; |
| 94 | 93 | u32 rcv_pkt_len = 0; |
| 95 | 94 | int status = 0; |
| @@ -147,8 +146,7 @@ static int rsi_process_pkt(struct rsi_common *common) · 51 unmodified lines | ||
| 147 | 146 | */ |
| 148 | 147 | int rsi_init_sdio_slave_regs(struct rsi_hw *adapter) |
| 149 | 148 | { |
| 150 | − struct rsi_91x_sdiodev *dev = | |
| 151 | − (struct rsi_91x_sdiodev *)adapter->rsi_dev; | |
| 149 | + struct rsi_91x_sdiodev *dev = adapter->rsi_dev; | |
| 152 | 150 | u8 function = 0; |
| 153 | 151 | u8 byte; |
| 154 | 152 | int status = 0; |
| @@ -233,8 +231,7 @@ int rsi_init_sdio_slave_regs(struct rsi_hw *adapter) · 78 unmodified lines | ||
| 233 | 231 | static void rsi_rx_handler(struct rsi_hw *adapter) |
| 234 | 232 | { |
| 235 | 233 | struct rsi_common *common = adapter->priv; |
| 236 | − struct rsi_91x_sdiodev *dev = | |
| 237 | − (struct rsi_91x_sdiodev *)adapter->rsi_dev; | |
| 234 | + struct rsi_91x_sdiodev *dev = adapter->rsi_dev; | |
| 238 | 235 | int status; |
| 239 | 236 | u8 isr_status = 0; |
| 240 | 237 | u8 fw_status = 0; |
| @@ -339,8 +336,7 @@ static void rsi_rx_handler(struct rsi_hw *adapter) · 98 unmodified lines | ||
| 339 | 336 | int rsi_sdio_check_buffer_status(struct rsi_hw *adapter, u8 q_num) |
| 340 | 337 | { |
| 341 | 338 | struct rsi_common *common = adapter->priv; |
| 342 | − struct rsi_91x_sdiodev *dev = | |
| 343 | − (struct rsi_91x_sdiodev *)adapter->rsi_dev; | |
| 339 | + struct rsi_91x_sdiodev *dev = adapter->rsi_dev; | |
| 344 | 340 | u8 buf_status = 0; |
| 345 | 341 | int status = 0; |
| 346 | 342 | static int counter = 4; |
| @@ -409,8 +405,7 @@ out: · 62 unmodified lines | ||
| 409 | 405 | */ |
| 410 | 406 | int rsi_sdio_determine_event_timeout(struct rsi_hw *adapter) |
| 411 | 407 | { |
| 412 | − struct rsi_91x_sdiodev *dev = | |
| 413 | − (struct rsi_91x_sdiodev *)adapter->rsi_dev; | |
| 408 | + struct rsi_91x_sdiodev *dev = adapter->rsi_dev; | |
| 414 | 409 | |
| 415 | 410 | /* Once buffer full is seen, event timeout to occur every 2 msecs */ |
| 416 | 411 | if (dev->rx_info.buffer_full) |
| @@ -43,7 +43,7 @@ static int rsi_usb_card_write(struct rsi_hw *adapter, · 42 unmodified lines | ||
| 43 | 43 | u16 len, |
| 44 | 44 | u8 endpoint) |
| 45 | 45 | { |
| 46 | − struct rsi_91x_usbdev *dev = (struct rsi_91x_usbdev *)adapter->rsi_dev; | |
| 46 | + struct rsi_91x_usbdev *dev = adapter->rsi_dev; | |
| 47 | 47 | int status; |
| 48 | 48 | u8 *seg = dev->tx_buffer; |
| 49 | 49 | int transfer; |
| @@ -91,7 +91,7 @@ static int rsi_write_multiple(struct rsi_hw *adapter, · 41 unmodified lines | ||
| 91 | 91 | if (endpoint == 0) |
| 92 | 92 | return -EINVAL; |
| 93 | 93 | |
| 94 | − dev = (struct rsi_91x_usbdev *)adapter->rsi_dev; | |
| 94 | + dev = adapter->rsi_dev; | |
| 95 | 95 | if (dev->write_fail) |
| 96 | 96 | return -ENETDOWN; |
| 97 | 97 | |
| @@ -109,7 +109,7 @@ static int rsi_write_multiple(struct rsi_hw *adapter, · 11 unmodified lines | ||
| 109 | 109 | static int rsi_find_bulk_in_and_out_endpoints(struct usb_interface *interface, |
| 110 | 110 | struct rsi_hw *adapter) |
| 111 | 111 | { |
| 112 | − struct rsi_91x_usbdev *dev = (struct rsi_91x_usbdev *)adapter->rsi_dev; | |
| 112 | + struct rsi_91x_usbdev *dev = adapter->rsi_dev; | |
| 113 | 113 | struct usb_host_interface *iface_desc; |
| 114 | 114 | struct usb_endpoint_descriptor *endpoint; |
| 115 | 115 | __le16 buffer_size; |
| @@ -306,7 +306,7 @@ out: · 190 unmodified lines | ||
| 306 | 306 | |
| 307 | 307 | static void rsi_rx_urb_kill(struct rsi_hw *adapter, u8 ep_num) |
| 308 | 308 | { |
| 309 | − struct rsi_91x_usbdev *dev = (struct rsi_91x_usbdev *)adapter->rsi_dev; | |
| 309 | + struct rsi_91x_usbdev *dev = adapter->rsi_dev; | |
| 310 | 310 | struct rx_usb_ctrl_block *rx_cb = &dev->rx_cb[ep_num - 1]; |
| 311 | 311 | struct urb *urb = rx_cb->rx_urb; |
| 312 | 312 | |
| @@ -323,7 +323,7 @@ static void rsi_rx_urb_kill(struct rsi_hw *adapter, u8 ep_num) · 10 unmodified lines | ||
| 323 | 323 | */ |
| 324 | 324 | static int rsi_rx_urb_submit(struct rsi_hw *adapter, u8 ep_num, gfp_t mem_flags) |
| 325 | 325 | { |
| 326 | − struct rsi_91x_usbdev *dev = (struct rsi_91x_usbdev *)adapter->rsi_dev; | |
| 326 | + struct rsi_91x_usbdev *dev = adapter->rsi_dev; | |
| 327 | 327 | struct rx_usb_ctrl_block *rx_cb = &dev->rx_cb[ep_num - 1]; |
| 328 | 328 | struct urb *urb = rx_cb->rx_urb; |
| 329 | 329 | int status; |
| @@ -362,7 +362,7 @@ static int rsi_rx_urb_submit(struct rsi_hw *adapter, u8 ep_num, gfp_t mem_flags) · 32 unmodified lines | ||
| 362 | 362 | static int rsi_usb_read_register_multiple(struct rsi_hw *adapter, u32 addr, |
| 363 | 363 | u8 *data, u16 count) |
| 364 | 364 | { |
| 365 | − struct rsi_91x_usbdev *dev = (struct rsi_91x_usbdev *)adapter->rsi_dev; | |
| 365 | + struct rsi_91x_usbdev *dev = adapter->rsi_dev; | |
| 366 | 366 | u8 *buf; |
| 367 | 367 | u16 transfer; |
| 368 | 368 | int status; |
| @@ -412,7 +412,7 @@ static int rsi_usb_read_register_multiple(struct rsi_hw *adapter, u32 addr, · 43 unmodified lines | ||
| 412 | 412 | static int rsi_usb_write_register_multiple(struct rsi_hw *adapter, u32 addr, |
| 413 | 413 | u8 *data, u16 count) |
| 414 | 414 | { |
| 415 | − struct rsi_91x_usbdev *dev = (struct rsi_91x_usbdev *)adapter->rsi_dev; | |
| 415 | + struct rsi_91x_usbdev *dev = adapter->rsi_dev; | |
| 416 | 416 | u8 *buf; |
| 417 | 417 | u16 transfer; |
| 418 | 418 | int status = 0; |
| @@ -559,7 +559,7 @@ static struct rsi_host_intf_ops usb_host_intf_ops = { · 140 unmodified lines | ||
| 559 | 559 | */ |
| 560 | 560 | static void rsi_deinit_usb_interface(struct rsi_hw *adapter) |
| 561 | 561 | { |
| 562 | − struct rsi_91x_usbdev *dev = (struct rsi_91x_usbdev *)adapter->rsi_dev; | |
| 562 | + struct rsi_91x_usbdev *dev = adapter->rsi_dev; | |
| 563 | 563 | |
| 564 | 564 | rsi_kill_thread(&dev->rx_thread); |
| 565 | 565 | |
| @@ -572,7 +572,7 @@ static void rsi_deinit_usb_interface(struct rsi_hw *adapter) · 6 unmodified lines | ||
| 572 | 572 | |
| 573 | 573 | static int rsi_usb_init_rx(struct rsi_hw *adapter) |
| 574 | 574 | { |
| 575 | − struct rsi_91x_usbdev *dev = (struct rsi_91x_usbdev *)adapter->rsi_dev; | |
| 575 | + struct rsi_91x_usbdev *dev = adapter->rsi_dev; | |
| 576 | 576 | struct rx_usb_ctrl_block *rx_cb; |
| 577 | 577 | u8 idx, num_rx_cb; |
| 578 | 578 | |
| @@ -822,7 +822,7 @@ static int rsi_probe(struct usb_interface *pfunction, · 243 unmodified lines | ||
| 822 | 822 | goto err1; |
| 823 | 823 | } |
| 824 | 824 | |
| 825 | − dev = (struct rsi_91x_usbdev *)adapter->rsi_dev; | |
| 825 | + dev = adapter->rsi_dev; | |
| 826 | 826 | |
| 827 | 827 | status = rsi_usb_reg_read(dev->usbdev, FW_STATUS_REG, &fw_status, 2); |
| 828 | 828 | if (status < 0) |
| @@ -28,7 +28,7 @@ · 27 unmodified lines | ||
| 28 | 28 | void rsi_usb_rx_thread(struct rsi_common *common) |
| 29 | 29 | { |
| 30 | 30 | struct rsi_hw *adapter = common->priv; |
| 31 | − struct rsi_91x_usbdev *dev = (struct rsi_91x_usbdev *)adapter->rsi_dev; | |
| 31 | + struct rsi_91x_usbdev *dev = adapter->rsi_dev; | |
| 32 | 32 | int status; |
| 33 | 33 | struct sk_buff *skb; |
| 34 | 34 | |
| @@ -293,13 +293,12 @@ struct wfx_dev *wfx_init_common(struct device *dev, const struct wfx_platform_da · 292 unmodified lines | ||
| 293 | 293 | hw->wiphy->max_scan_ie_len = IEEE80211_MAX_DATA_LEN; |
| 294 | 294 | hw->wiphy->n_iface_combinations = ARRAY_SIZE(wfx_iface_combinations); |
| 295 | 295 | hw->wiphy->iface_combinations = wfx_iface_combinations; |
| 296 | − hw->wiphy->bands[NL80211_BAND_2GHZ] = devm_kmalloc(dev, sizeof(wfx_band_2ghz), GFP_KERNEL); | |
| 296 | + /* FIXME: also copy wfx_rates and wfx_2ghz_chantable */ | |
| 297 | + hw->wiphy->bands[NL80211_BAND_2GHZ] = devm_kmemdup(dev, &wfx_band_2ghz, | |
| 298 | + sizeof(wfx_band_2ghz), GFP_KERNEL); | |
| 297 | 299 | if (!hw->wiphy->bands[NL80211_BAND_2GHZ]) |
| 298 | 300 | goto err; |
| 299 | 301 | |
| 300 | − /* FIXME: also copy wfx_rates and wfx_2ghz_chantable */ | |
| 301 | − memcpy(hw->wiphy->bands[NL80211_BAND_2GHZ], &wfx_band_2ghz, sizeof(wfx_band_2ghz)); | |
| 302 | − | |
| 303 | 302 | wdev = hw->priv; |
| 304 | 303 | wdev->hw = hw; |
| 305 | 304 | wdev->dev = dev; |
| @@ -442,18 +442,7 @@ static struct sdio_driver wl1271_sdio_driver = { · 441 unmodified lines | ||
| 442 | 442 | #endif |
| 443 | 443 | }; |
| 444 | 444 | |
| 445 | −static int __init wl1271_init(void) | |
| 446 | −{ | |
| 447 | − return sdio_register_driver(&wl1271_sdio_driver); | |
| 448 | −} | |
| 449 | − | |
| 450 | −static void __exit wl1271_exit(void) | |
| 451 | −{ | |
| 452 | − sdio_unregister_driver(&wl1271_sdio_driver); | |
| 453 | −} | |
| 454 | − | |
| 455 | −module_init(wl1271_init); | |
| 456 | −module_exit(wl1271_exit); | |
| 445 | +module_sdio_driver(wl1271_sdio_driver); | |
| 457 | 446 | |
| 458 | 447 | module_param(dump, bool, 0600); |
| 459 | 448 | MODULE_PARM_DESC(dump, "Enable sdio read/write dumps."); |
| @@ -582,9 +582,8 @@ static int mac80211_hwsim_vendor_cmd_test(struct wiphy *wiphy, · 581 unmodified lines | ||
| 582 | 582 | */ |
| 583 | 583 | |
| 584 | 584 | /* Add vendor data */ |
| 585 | − err = nla_put_u32(skb, QCA_WLAN_VENDOR_ATTR_TEST, val + 1); | |
| 586 | − if (err) | |
| 587 | − return err; | |
| 585 | + nla_put_u32(skb, QCA_WLAN_VENDOR_ATTR_TEST, val + 1); | |
| 586 | + | |
| 588 | 587 | /* Send the event - this will call nla_nest_end() */ |
| 589 | 588 | cfg80211_vendor_event(skb, GFP_KERNEL); |
| 590 | 589 | } |
| @@ -5626,14 +5625,15 @@ static int hwsim_cloned_frame_received_nl(struct sk_buff *skb_2, · 5035 unmodified lines | ||
| 5626 | 5625 | frame_data_len = nla_len(info->attrs[HWSIM_ATTR_FRAME]); |
| 5627 | 5626 | frame_data = (void *)nla_data(info->attrs[HWSIM_ATTR_FRAME]); |
| 5628 | 5627 | |
| 5628 | + if (frame_data_len < sizeof(struct ieee80211_hdr_3addr) || | |
| 5629 | + frame_data_len > IEEE80211_MAX_DATA_LEN) | |
| 5630 | + goto err; | |
| 5631 | + | |
| 5629 | 5632 | /* Allocate new skb here */ |
| 5630 | 5633 | skb = alloc_skb(frame_data_len, GFP_KERNEL); |
| 5631 | 5634 | if (skb == NULL) |
| 5632 | 5635 | goto err; |
| 5633 | 5636 | |
| 5634 | − if (frame_data_len > IEEE80211_MAX_DATA_LEN) | |
| 5635 | − goto err; | |
| 5636 | − | |
| 5637 | 5637 | /* Copy the data */ |
| 5638 | 5638 | skb_put_data(skb, frame_data, frame_data_len); |
| 5639 | 5639 | |
| @@ -6314,7 +6314,7 @@ static void hwsim_virtio_tx_done(struct virtqueue *vq) · 674 unmodified lines | ||
| 6314 | 6314 | |
| 6315 | 6315 | spin_lock_irqsave(&hwsim_virtio_lock, flags); |
| 6316 | 6316 | while ((skb = virtqueue_get_buf(vq, &len))) |
| 6317 | − nlmsg_free(skb); | |
| 6317 | + dev_kfree_skb_irq(skb); | |
| 6318 | 6318 | spin_unlock_irqrestore(&hwsim_virtio_lock, flags); |
| 6319 | 6319 | } |
| 6320 | 6320 | |
| @@ -6383,14 +6383,14 @@ static void hwsim_virtio_rx_work(struct work_struct *work) · 62 unmodified lines | ||
| 6383 | 6383 | |
| 6384 | 6384 | spin_lock_irqsave(&hwsim_virtio_lock, flags); |
| 6385 | 6385 | if (!hwsim_virtio_enabled) { |
| 6386 | − nlmsg_free(skb); | |
| 6386 | + dev_kfree_skb_irq(skb); | |
| 6387 | 6387 | goto out_unlock; |
| 6388 | 6388 | } |
| 6389 | 6389 | vq = hwsim_vqs[HWSIM_VQ_RX]; |
| 6390 | 6390 | sg_init_one(sg, skb->head, skb_end_offset(skb)); |
| 6391 | 6391 | err = virtqueue_add_inbuf(vq, sg, 1, skb, GFP_ATOMIC); |
| 6392 | 6392 | if (WARN(err, "virtqueue_add_inbuf returned %d\n", err)) |
| 6393 | − nlmsg_free(skb); | |
| 6393 | + dev_kfree_skb_irq(skb); | |
| 6394 | 6394 | else |
| 6395 | 6395 | virtqueue_kick(vq); |
| 6396 | 6396 | schedule_work(&hwsim_virtio_rx); |
| @@ -1,6 +1,6 @@ | ||
| 1 | 1 | // SPDX-License-Identifier: GPL-2.0-only |
| 2 | 2 | /* |
| 3 | − * Driver for ZyDAS zd1201 based wireless USB devices. | |
| 3 | + * Driver for ZyDAS zd1201 based USB wireless devices. | |
| 4 | 4 | * |
| 5 | 5 | * Copyright (c) 2004, 2005 Jeroen Vreeken (pe1rxq@amsat.org) |
| 6 | 6 | * |
| @@ -23,8 +23,8 @@ · 16 unmodified lines | ||
| 23 | 23 | #include "zd1201.h" |
| 24 | 24 | |
| 25 | 25 | static const struct usb_device_id zd1201_table[] = { |
| 26 | − {USB_DEVICE(0x0586, 0x3400)}, /* Peabird Wireless USB Adapter */ | |
| 27 | − {USB_DEVICE(0x0ace, 0x1201)}, /* ZyDAS ZD1201 Wireless USB Adapter */ | |
| 26 | + {USB_DEVICE(0x0586, 0x3400)}, /* Peabird USB Wireless Adapter */ | |
| 27 | + {USB_DEVICE(0x0ace, 0x1201)}, /* ZyDAS ZD1201 USB Wireless Adapter */ | |
| 28 | 28 | {USB_DEVICE(0x050d, 0x6051)}, /* Belkin F5D6051 usb adapter */ |
| 29 | 29 | {USB_DEVICE(0x0db0, 0x6823)}, /* MSI UB11B usb adapter */ |
| 30 | 30 | {USB_DEVICE(0x1044, 0x8004)}, /* Gigabyte GN-WLBZ101 */ |
| @@ -1394,7 +1394,7 @@ static int eeepc_acpi_add(struct acpi_device *device) · 1393 unmodified lines | ||
| 1394 | 1394 | * and machine-specific scripts find the fixed name convenient. But |
| 1395 | 1395 | * It's also good for us to exclude multiple instances because both |
| 1396 | 1396 | * our hwmon and our wlan rfkill subdevice use global ACPI objects |
| 1397 | − * (the EC and the wlan PCI slot respectively). | |
| 1397 | + * (the EC and the PCI wlan slot respectively). | |
| 1398 | 1398 | */ |
| 1399 | 1399 | result = eeepc_platform_init(eeepc); |
| 1400 | 1400 | if (result) |
| @@ -11,45 +11,45 @@ · 10 unmodified lines | ||
| 11 | 11 | |
| 12 | 12 | static const struct usb_device_id usb_prism_tbl[] = { |
| 13 | 13 | PRISM_DEV(0x04bb, 0x0922, "IOData AirPort WN-B11/USBS"), |
| 14 | − PRISM_DEV(0x07aa, 0x0012, "Corega Wireless LAN USB Stick-11"), | |
| 15 | − PRISM_DEV(0x09aa, 0x3642, "Prism2.x 11Mbps WLAN USB Adapter"), | |
| 16 | − PRISM_DEV(0x1668, 0x0408, "Actiontec Prism2.5 11Mbps WLAN USB Adapter"), | |
| 17 | − PRISM_DEV(0x1668, 0x0421, "Actiontec Prism2.5 11Mbps WLAN USB Adapter"), | |
| 18 | − PRISM_DEV(0x1915, 0x2236, "Linksys WUSB11v3.0 11Mbps WLAN USB Adapter"), | |
| 19 | − PRISM_DEV(0x066b, 0x2212, "Linksys WUSB11v2.5 11Mbps WLAN USB Adapter"), | |
| 20 | − PRISM_DEV(0x066b, 0x2213, "Linksys WUSB12v1.1 11Mbps WLAN USB Adapter"), | |
| 14 | + PRISM_DEV(0x07aa, 0x0012, "Corega USB Wireless LAN Stick-11"), | |
| 15 | + PRISM_DEV(0x09aa, 0x3642, "Prism2.x 11Mbps USB WLAN Adapter"), | |
| 16 | + PRISM_DEV(0x1668, 0x0408, "Actiontec Prism2.5 11Mbps USB WLAN Adapter"), | |
| 17 | + PRISM_DEV(0x1668, 0x0421, "Actiontec Prism2.5 11Mbps USB WLAN Adapter"), | |
| 18 | + PRISM_DEV(0x1915, 0x2236, "Linksys WUSB11v3.0 11Mbps USB WLAN Adapter"), | |
| 19 | + PRISM_DEV(0x066b, 0x2212, "Linksys WUSB11v2.5 11Mbps USB WLAN Adapter"), | |
| 20 | + PRISM_DEV(0x066b, 0x2213, "Linksys WUSB12v1.1 11Mbps USB WLAN Adapter"), | |
| 21 | 21 | PRISM_DEV(0x0411, 0x0016, "Melco WLI-USB-S11 11Mbps WLAN Adapter"), |
| 22 | − PRISM_DEV(0x08de, 0x7a01, "PRISM25 IEEE 802.11 Mini USB Adapter"), | |
| 23 | − PRISM_DEV(0x8086, 0x1111, "Intel PRO/Wireless 2011B LAN USB Adapter"), | |
| 22 | + PRISM_DEV(0x08de, 0x7a01, "PRISM25 USB IEEE 802.11 Mini Adapter"), | |
| 23 | + PRISM_DEV(0x8086, 0x1111, "Intel PRO/Wireless 2011B USB LAN Adapter"), | |
| 24 | 24 | PRISM_DEV(0x0d8e, 0x7a01, "PRISM25 IEEE 802.11 Mini USB Adapter"), |
| 25 | − PRISM_DEV(0x045e, 0x006e, "Microsoft MN510 Wireless USB Adapter"), | |
| 25 | + PRISM_DEV(0x045e, 0x006e, "Microsoft MN510 USB Wireless Adapter"), | |
| 26 | 26 | PRISM_DEV(0x0967, 0x0204, "Acer Warplink USB Adapter"), |
| 27 | 27 | PRISM_DEV(0x0cde, 0x0002, "Z-Com 725/726 Prism2.5 USB/USB Integrated"), |
| 28 | − PRISM_DEV(0x0cde, 0x0005, "Z-Com Xl735 Wireless 802.11b USB Adapter"), | |
| 29 | − PRISM_DEV(0x413c, 0x8100, "Dell TrueMobile 1180 Wireless USB Adapter"), | |
| 30 | − PRISM_DEV(0x0b3b, 0x1601, "ALLNET 0193 11Mbps WLAN USB Adapter"), | |
| 31 | − PRISM_DEV(0x0b3b, 0x1602, "ZyXEL ZyAIR B200 Wireless USB Adapter"), | |
| 32 | − PRISM_DEV(0x0baf, 0x00eb, "USRobotics USR1120 Wireless USB Adapter"), | |
| 28 | + PRISM_DEV(0x0cde, 0x0005, "Z-Com Xl735 USB Wireless 802.11b Adapter"), | |
| 29 | + PRISM_DEV(0x413c, 0x8100, "Dell TrueMobile 1180 USB Wireless Adapter"), | |
| 30 | + PRISM_DEV(0x0b3b, 0x1601, "ALLNET 0193 11Mbps USB WLAN Adapter"), | |
| 31 | + PRISM_DEV(0x0b3b, 0x1602, "ZyXEL ZyAIR B200 USB Wireless Adapter"), | |
| 32 | + PRISM_DEV(0x0baf, 0x00eb, "USRobotics USR1120 USB Wireless Adapter"), | |
| 33 | 33 | PRISM_DEV(0x0411, 0x0027, "Melco WLI-USB-KS11G 11Mbps WLAN Adapter"), |
| 34 | 34 | PRISM_DEV(0x04f1, 0x3009, "JVC MP-XP7250 Builtin USB WLAN Adapter"), |
| 35 | 35 | PRISM_DEV(0x0846, 0x4110, "NetGear MA111"), |
| 36 | 36 | PRISM_DEV(0x03f3, 0x0020, "Adaptec AWN-8020 USB WLAN Adapter"), |
| 37 | − PRISM_DEV(0x2821, 0x3300, "ASUS-WL140 / Hawking HighDB Wireless USB Adapter"), | |
| 38 | − PRISM_DEV(0x2001, 0x3700, "DWL-122 Wireless USB Adapter"), | |
| 39 | − PRISM_DEV(0x2001, 0x3702, "DWL-120 Rev F Wireless USB Adapter"), | |
| 37 | + PRISM_DEV(0x2821, 0x3300, "ASUS-WL140 / Hawking HighDB USB Wireless Adapter"), | |
| 38 | + PRISM_DEV(0x2001, 0x3700, "DWL-122 USB Wireless Adapter"), | |
| 39 | + PRISM_DEV(0x2001, 0x3702, "DWL-120 Rev F USB Wireless Adapter"), | |
| 40 | 40 | PRISM_DEV(0x50c2, 0x4013, "Averatec USB WLAN Adapter"), |
| 41 | − PRISM_DEV(0x2c02, 0x14ea, "Planex GW-US11H WLAN USB Adapter"), | |
| 42 | − PRISM_DEV(0x124a, 0x168b, "Airvast PRISM3 WLAN USB Adapter"), | |
| 41 | + PRISM_DEV(0x2c02, 0x14ea, "Planex GW-US11H USB WLAN Adapter"), | |
| 42 | + PRISM_DEV(0x124a, 0x168b, "Airvast PRISM3 USB WLAN Adapter"), | |
| 43 | 43 | PRISM_DEV(0x083a, 0x3503, "T-Sinus 111 USB WLAN Adapter"), |
| 44 | 44 | PRISM_DEV(0x0411, 0x0044, "Melco WLI-USB-KB11 11Mbps WLAN Adapter"), |
| 45 | − PRISM_DEV(0x1668, 0x6106, "ROPEX FreeLan 802.11b USB Adapter"), | |
| 46 | − PRISM_DEV(0x124a, 0x4017, "Pheenet WL-503IA 802.11b USB Adapter"), | |
| 45 | + PRISM_DEV(0x1668, 0x6106, "ROPEX FreeLan USB 802.11b Adapter"), | |
| 46 | + PRISM_DEV(0x124a, 0x4017, "Pheenet WL-503IA USB 802.11b Adapter"), | |
| 47 | 47 | PRISM_DEV(0x0bb2, 0x0302, "Ambit Microsystems Corp."), |
| 48 | − PRISM_DEV(0x9016, 0x182d, "Sitecom WL-022 802.11b USB Adapter"), | |
| 48 | + PRISM_DEV(0x9016, 0x182d, "Sitecom WL-022 USB 802.11b Adapter"), | |
| 49 | 49 | PRISM_DEV(0x0543, 0x0f01, |
| 50 | 50 | "ViewSonic Airsync USB Adapter 11Mbps (Prism2.5)"), |
| 51 | 51 | PRISM_DEV(0x067c, 0x1022, |
| 52 | − "Siemens SpeedStream 1022 11Mbps WLAN USB Adapter"), | |
| 52 | + "Siemens SpeedStream 1022 11Mbps USB WLAN Adapter"), | |
| 53 | 53 | PRISM_DEV(0x049f, 0x0033, |
| 54 | 54 | "Compaq/Intel W100 PRO/Wireless 11Mbps multiport WLAN Adapter"), |
| 55 | 55 | { } /* terminator */ |
| @@ -836,9 +836,14 @@ enum ieee80211_preq_target_flags { · 835 unmodified lines | ||
| 836 | 836 | }; |
| 837 | 837 | |
| 838 | 838 | /** |
| 839 | − * struct ieee80211_quiet_ie | |
| 839 | + * struct ieee80211_quiet_ie - Quiet element | |
| 840 | + * @count: Quiet Count | |
| 841 | + * @period: Quiet Period | |
| 842 | + * @duration: Quiet Duration | |
| 843 | + * @offset: Quiet Offset | |
| 840 | 844 | * |
| 841 | − * This structure refers to "Quiet information element" | |
| 845 | + * This structure represents the payload of the "Quiet element" as | |
| 846 | + * described in IEEE Std 802.11-2020 section 9.4.2.22. | |
| 842 | 847 | */ |
| 843 | 848 | struct ieee80211_quiet_ie { |
| 844 | 849 | u8 count; |
| @@ -848,9 +853,15 @@ struct ieee80211_quiet_ie { · 3 unmodified lines | ||
| 848 | 853 | } __packed; |
| 849 | 854 | |
| 850 | 855 | /** |
| 851 | − * struct ieee80211_msrment_ie | |
| 856 | + * struct ieee80211_msrment_ie - Measurement element | |
| 857 | + * @token: Measurement Token | |
| 858 | + * @mode: Measurement Report Mode | |
| 859 | + * @type: Measurement Type | |
| 860 | + * @request: Measurement Request or Measurement Report | |
| 852 | 861 | * |
| 853 | − * This structure refers to "Measurement Request/Report information element" | |
| 862 | + * This structure represents the payload of both the "Measurement | |
| 863 | + * Request element" and the "Measurement Report element" as described | |
| 864 | + * in IEEE Std 802.11-2020 sections 9.4.2.20 and 9.4.2.21. | |
| 854 | 865 | */ |
| 855 | 866 | struct ieee80211_msrment_ie { |
| 856 | 867 | u8 token; |
| @@ -860,9 +871,14 @@ struct ieee80211_msrment_ie { · 3 unmodified lines | ||
| 860 | 871 | } __packed; |
| 861 | 872 | |
| 862 | 873 | /** |
| 863 | − * struct ieee80211_channel_sw_ie | |
| 874 | + * struct ieee80211_channel_sw_ie - Channel Switch Announcement element | |
| 875 | + * @mode: Channel Switch Mode | |
| 876 | + * @new_ch_num: New Channel Number | |
| 877 | + * @count: Channel Switch Count | |
| 864 | 878 | * |
| 865 | − * This structure refers to "Channel Switch Announcement information element" | |
| 879 | + * This structure represents the payload of the "Channel Switch | |
| 880 | + * Announcement element" as described in IEEE Std 802.11-2020 section | |
| 881 | + * 9.4.2.18. | |
| 866 | 882 | */ |
| 867 | 883 | struct ieee80211_channel_sw_ie { |
| 868 | 884 | u8 mode; |
| @@ -871,9 +887,14 @@ struct ieee80211_channel_sw_ie { · 2 unmodified lines | ||
| 871 | 887 | } __packed; |
| 872 | 888 | |
| 873 | 889 | /** |
| 874 | − * struct ieee80211_ext_chansw_ie | |
| 890 | + * struct ieee80211_ext_chansw_ie - Extended Channel Switch Announcement element | |
| 891 | + * @mode: Channel Switch Mode | |
| 892 | + * @new_operating_class: New Operating Class | |
| 893 | + * @new_ch_num: New Channel Number | |
| 894 | + * @count: Channel Switch Count | |
| 875 | 895 | * |
| 876 | − * This structure represents the "Extended Channel Switch Announcement element" | |
| 896 | + * This structure represents the "Extended Channel Switch Announcement | |
| 897 | + * element" as described in IEEE Std 802.11-2020 section 9.4.2.52. | |
| 877 | 898 | */ |
| 878 | 899 | struct ieee80211_ext_chansw_ie { |
| 879 | 900 | u8 mode; |
| @@ -894,8 +915,14 @@ struct ieee80211_sec_chan_offs_ie { · 14 unmodified lines | ||
| 894 | 915 | |
| 895 | 916 | /** |
| 896 | 917 | * struct ieee80211_mesh_chansw_params_ie - mesh channel switch parameters IE |
| 918 | + * @mesh_ttl: Time To Live | |
| 919 | + * @mesh_flags: Flags | |
| 920 | + * @mesh_reason: Reason Code | |
| 921 | + * @mesh_pre_value: Precedence Value | |
| 897 | 922 | * |
| 898 | − * This structure represents the "Mesh Channel Switch Paramters element" | |
| 923 | + * This structure represents the payload of the "Mesh Channel Switch | |
| 924 | + * Parameters element" as described in IEEE Std 802.11-2020 section | |
| 925 | + * 9.4.2.102. | |
| 899 | 926 | */ |
| 900 | 927 | struct ieee80211_mesh_chansw_params_ie { |
| 901 | 928 | u8 mesh_ttl; |
| @@ -906,6 +933,13 @@ struct ieee80211_mesh_chansw_params_ie { · 4 unmodified lines | ||
| 906 | 933 | |
| 907 | 934 | /** |
| 908 | 935 | * struct ieee80211_wide_bw_chansw_ie - wide bandwidth channel switch IE |
| 936 | + * @new_channel_width: New Channel Width | |
| 937 | + * @new_center_freq_seg0: New Channel Center Frequency Segment 0 | |
| 938 | + * @new_center_freq_seg1: New Channel Center Frequency Segment 1 | |
| 939 | + * | |
| 940 | + * This structure represents the payload of the "Wide Bandwidth | |
| 941 | + * Channel Switch element" as described in IEEE Std 802.11-2020 | |
| 942 | + * section 9.4.2.160. | |
| 909 | 943 | */ |
| 910 | 944 | struct ieee80211_wide_bw_chansw_ie { |
| 911 | 945 | u8 new_channel_width; |
| @@ -913,9 +947,14 @@ struct ieee80211_wide_bw_chansw_ie { · 1 unmodified line | ||
| 913 | 947 | } __packed; |
| 914 | 948 | |
| 915 | 949 | /** |
| 916 | − * struct ieee80211_tim | |
| 950 | + * struct ieee80211_tim_ie - Traffic Indication Map information element | |
| 951 | + * @dtim_count: DTIM Count | |
| 952 | + * @dtim_period: DTIM Period | |
| 953 | + * @bitmap_ctrl: Bitmap Control | |
| 954 | + * @virtual_map: Partial Virtual Bitmap | |
| 917 | 955 | * |
| 918 | − * This structure refers to "Traffic Indication Map information element" | |
| 956 | + * This structure represents the payload of the "TIM element" as | |
| 957 | + * described in IEEE Std 802.11-2020 section 9.4.2.5. | |
| 919 | 958 | */ |
| 920 | 959 | struct ieee80211_tim_ie { |
| 921 | 960 | u8 dtim_count; |
| @@ -926,9 +965,17 @@ struct ieee80211_tim_ie { · 4 unmodified lines | ||
| 926 | 965 | } __packed; |
| 927 | 966 | |
| 928 | 967 | /** |
| 929 | − * struct ieee80211_meshconf_ie | |
| 968 | + * struct ieee80211_meshconf_ie - Mesh Configuration element | |
| 969 | + * @meshconf_psel: Active Path Selection Protocol Identifier | |
| 970 | + * @meshconf_pmetric: Active Path Selection Metric Identifier | |
| 971 | + * @meshconf_congest: Congestion Control Mode Identifier | |
| 972 | + * @meshconf_synch: Synchronization Method Identifier | |
| 973 | + * @meshconf_auth: Authentication Protocol Identifier | |
| 974 | + * @meshconf_form: Mesh Formation Info | |
| 975 | + * @meshconf_cap: Mesh Capability (see &enum mesh_config_capab_flags) | |
| 930 | 976 | * |
| 931 | − * This structure refers to "Mesh Configuration information element" | |
| 977 | + * This structure represents the payload of the "Mesh Configuration | |
| 978 | + * element" as described in IEEE Std 802.11-2020 section 9.4.2.97. | |
| 932 | 979 | */ |
| 933 | 980 | struct ieee80211_meshconf_ie { |
| 934 | 981 | u8 meshconf_psel; |
| @@ -950,6 +997,9 @@ struct ieee80211_meshconf_ie { · 15 unmodified lines | ||
| 950 | 997 | * is ongoing |
| 951 | 998 | * @IEEE80211_MESHCONF_CAPAB_POWER_SAVE_LEVEL: STA is in deep sleep mode or has |
| 952 | 999 | * neighbors in deep sleep mode |
| 1000 | + * | |
| 1001 | + * Enumerates the "Mesh Capability" as described in IEEE Std | |
| 1002 | + * 802.11-2020 section 9.4.2.97.7. | |
| 953 | 1003 | */ |
| 954 | 1004 | enum mesh_config_capab_flags { |
| 955 | 1005 | IEEE80211_MESHCONF_CAPAB_ACCEPT_PLINKS = 0x01, |
| @@ -960,7 +1010,7 @@ enum mesh_config_capab_flags { · 4 unmodified lines | ||
| 960 | 1010 | |
| 961 | 1011 | #define IEEE80211_MESHCONF_FORM_CONNECTED_TO_GATE 0x1 |
| 962 | 1012 | |
| 963 | −/** | |
| 1013 | +/* | |
| 964 | 1014 | * mesh channel switch parameters element's flag indicator |
| 965 | 1015 | * |
| 966 | 1016 | */ |
| @@ -969,9 +1019,17 @@ enum mesh_config_capab_flags { · 2 unmodified lines | ||
| 969 | 1019 | #define WLAN_EID_CHAN_SWITCH_PARAM_REASON BIT(2) |
| 970 | 1020 | |
| 971 | 1021 | /** |
| 972 | − * struct ieee80211_rann_ie | |
| 1022 | + * struct ieee80211_rann_ie - RANN (root announcement) element | |
| 1023 | + * @rann_flags: Flags | |
| 1024 | + * @rann_hopcount: Hop Count | |
| 1025 | + * @rann_ttl: Element TTL | |
| 1026 | + * @rann_addr: Root Mesh STA Address | |
| 1027 | + * @rann_seq: HWMP Sequence Number | |
| 1028 | + * @rann_interval: Interval | |
| 1029 | + * @rann_metric: Metric | |
| 973 | 1030 | * |
| 974 | − * This structure refers to "Root Announcement information element" | |
| 1031 | + * This structure represents the payload of the "RANN element" as | |
| 1032 | + * described in IEEE Std 802.11-2020 section 9.4.2.111. | |
| 975 | 1033 | */ |
| 976 | 1034 | struct ieee80211_rann_ie { |
| 977 | 1035 | u8 rann_flags; |
| @@ -993,7 +1051,7 @@ enum ieee80211_ht_chanwidth_values { · 15 unmodified lines | ||
| 993 | 1051 | }; |
| 994 | 1052 | |
| 995 | 1053 | /** |
| 996 | − * enum ieee80211_opmode_bits - VHT operating mode field bits | |
| 1054 | + * enum ieee80211_vht_opmode_bits - VHT operating mode field bits | |
| 997 | 1055 | * @IEEE80211_OPMODE_NOTIF_CHANWIDTH_MASK: channel width mask |
| 998 | 1056 | * @IEEE80211_OPMODE_NOTIF_CHANWIDTH_20MHZ: 20 MHz channel width |
| 999 | 1057 | * @IEEE80211_OPMODE_NOTIF_CHANWIDTH_40MHZ: 40 MHz channel width |
| @@ -1042,9 +1100,12 @@ enum ieee80211_s1g_chanwidth { · 42 unmodified lines | ||
| 1042 | 1100 | #define WLAN_USER_POSITION_LEN 16 |
| 1043 | 1101 | |
| 1044 | 1102 | /** |
| 1045 | − * struct ieee80211_tpc_report_ie | |
| 1103 | + * struct ieee80211_tpc_report_ie - TPC Report element | |
| 1104 | + * @tx_power: Transmit Power | |
| 1105 | + * @link_margin: Link Margin | |
| 1046 | 1106 | * |
| 1047 | − * This structure refers to "TPC Report element" | |
| 1107 | + * This structure represents the payload of the "TPC Report element" as | |
| 1108 | + * described in IEEE Std 802.11-2020 section 9.4.2.16. | |
| 1048 | 1109 | */ |
| 1049 | 1110 | struct ieee80211_tpc_report_ie { |
| 1050 | 1111 | u8 tx_power; |
| @@ -1062,9 +1123,14 @@ struct ieee80211_addba_ext_ie { · 11 unmodified lines | ||
| 1062 | 1123 | } __packed; |
| 1063 | 1124 | |
| 1064 | 1125 | /** |
| 1065 | − * struct ieee80211_s1g_bcn_compat_ie | |
| 1126 | + * struct ieee80211_s1g_bcn_compat_ie - S1G Beacon Compatibility element | |
| 1127 | + * @compat_info: Compatibility Information | |
| 1128 | + * @beacon_int: Beacon Interval | |
| 1129 | + * @tsf_completion: TSF Completion | |
| 1066 | 1130 | * |
| 1067 | − * S1G Beacon Compatibility element | |
| 1131 | + * This structure represents the payload of the "S1G Beacon | |
| 1132 | + * Compatibility element" as described in IEEE Std 802.11-2020 section | |
| 1133 | + * 9.4.2.196. | |
| 1068 | 1134 | */ |
| 1069 | 1135 | struct ieee80211_s1g_bcn_compat_ie { |
| 1070 | 1136 | __le16 compat_info; |
| @@ -1073,9 +1139,15 @@ struct ieee80211_s1g_bcn_compat_ie { · 2 unmodified lines | ||
| 1073 | 1139 | } __packed; |
| 1074 | 1140 | |
| 1075 | 1141 | /** |
| 1076 | − * struct ieee80211_s1g_oper_ie | |
| 1142 | + * struct ieee80211_s1g_oper_ie - S1G Operation element | |
| 1143 | + * @ch_width: S1G Operation Information Channel Width | |
| 1144 | + * @oper_class: S1G Operation Information Operating Class | |
| 1145 | + * @primary_ch: S1G Operation Information Primary Channel Number | |
| 1146 | + * @oper_ch: S1G Operation Information Channel Center Frequency | |
| 1147 | + * @basic_mcs_nss: Basic S1G-MCS and NSS Set | |
| 1077 | 1148 | * |
| 1078 | − * S1G Operation element | |
| 1149 | + * This structure represents the payload of the "S1G Operation | |
| 1150 | + * element" as described in IEEE Std 802.11-2020 section 9.4.2.212. | |
| 1079 | 1151 | */ |
| 1080 | 1152 | struct ieee80211_s1g_oper_ie { |
| 1081 | 1153 | u8 ch_width; |
| @@ -1086,9 +1158,13 @@ struct ieee80211_s1g_oper_ie { · 4 unmodified lines | ||
| 1086 | 1158 | } __packed; |
| 1087 | 1159 | |
| 1088 | 1160 | /** |
| 1089 | − * struct ieee80211_aid_response_ie | |
| 1161 | + * struct ieee80211_aid_response_ie - AID Response element | |
| 1162 | + * @aid: AID/Group AID | |
| 1163 | + * @switch_count: AID Switch Count | |
| 1164 | + * @response_int: AID Response Interval | |
| 1090 | 1165 | * |
| 1091 | − * AID Response element | |
| 1166 | + * This structure represents the payload of the "AID Response element" | |
| 1167 | + * as described in IEEE Std 802.11-2020 section 9.4.2.194. | |
| 1092 | 1168 | */ |
| 1093 | 1169 | struct ieee80211_aid_response_ie { |
| 1094 | 1170 | __le16 aid; |
| @@ -1489,7 +1565,7 @@ struct ieee80211_tdls_data { · 394 unmodified lines | ||
| 1489 | 1565 | /* |
| 1490 | 1566 | * Peer-to-Peer IE attribute related definitions. |
| 1491 | 1567 | */ |
| 1492 | −/** | |
| 1568 | +/* | |
| 1493 | 1569 | * enum ieee80211_p2p_attr_id - identifies type of peer-to-peer attribute. |
| 1494 | 1570 | */ |
| 1495 | 1571 | enum ieee80211_p2p_attr_id { |
| @@ -1539,11 +1615,17 @@ struct ieee80211_p2p_noa_attr { · 43 unmodified lines | ||
| 1539 | 1615 | #define IEEE80211_P2P_OPPPS_CTWINDOW_MASK 0x7F |
| 1540 | 1616 | |
| 1541 | 1617 | /** |
| 1542 | − * struct ieee80211_bar - HT Block Ack Request | |
| 1618 | + * struct ieee80211_bar - Block Ack Request frame format | |
| 1619 | + * @frame_control: Frame Control | |
| 1620 | + * @duration: Duration | |
| 1621 | + * @ra: RA | |
| 1622 | + * @ta: TA | |
| 1623 | + * @control: BAR Control | |
| 1624 | + * @start_seq_num: Starting Sequence Number (see Figure 9-37) | |
| 1543 | 1625 | * |
| 1544 | − * This structure refers to "HT BlockAckReq" as | |
| 1545 | − * described in 802.11n draft section 7.2.1.7.1 | |
| 1546 | − */ | |
| 1626 | + * This structure represents the "BlockAckReq frame format" | |
| 1627 | + * as described in IEEE Std 802.11-2020 section 9.3.1.7. | |
| 1628 | +*/ | |
| 1547 | 1629 | struct ieee80211_bar { |
| 1548 | 1630 | __le16 frame_control; |
| 1549 | 1631 | __le16 duration; |
| @@ -1563,13 +1645,17 @@ struct ieee80211_bar { · 13 unmodified lines | ||
| 1563 | 1645 | #define IEEE80211_HT_MCS_MASK_LEN 10 |
| 1564 | 1646 | |
| 1565 | 1647 | /** |
| 1566 | − * struct ieee80211_mcs_info - MCS information | |
| 1648 | + * struct ieee80211_mcs_info - Supported MCS Set field | |
| 1567 | 1649 | * @rx_mask: RX mask |
| 1568 | 1650 | * @rx_highest: highest supported RX rate. If set represents |
| 1569 | 1651 | * the highest supported RX data rate in units of 1 Mbps. |
| 1570 | 1652 | * If this field is 0 this value should not be used to |
| 1571 | 1653 | * consider the highest RX data rate supported. |
| 1572 | 1654 | * @tx_params: TX parameters |
| 1655 | + * @reserved: Reserved bits | |
| 1656 | + * | |
| 1657 | + * This structure represents the "Supported MCS Set field" as | |
| 1658 | + * described in IEEE Std 802.11-2020 section 9.4.2.55.4. | |
| 1573 | 1659 | */ |
| 1574 | 1660 | struct ieee80211_mcs_info { |
| 1575 | 1661 | u8 rx_mask[IEEE80211_HT_MCS_MASK_LEN]; |
| @@ -1600,10 +1686,16 @@ struct ieee80211_mcs_info { · 24 unmodified lines | ||
| 1600 | 1686 | (IEEE80211_HT_MCS_UNEQUAL_MODULATION_START / 8) |
| 1601 | 1687 | |
| 1602 | 1688 | /** |
| 1603 | − * struct ieee80211_ht_cap - HT capabilities | |
| 1689 | + * struct ieee80211_ht_cap - HT capabilities element | |
| 1690 | + * @cap_info: HT Capability Information | |
| 1691 | + * @ampdu_params_info: A-MPDU Parameters | |
| 1692 | + * @mcs: Supported MCS Set | |
| 1693 | + * @extended_ht_cap_info: HT Extended Capabilities | |
| 1694 | + * @tx_BF_cap_info: Transmit Beamforming Capabilities | |
| 1695 | + * @antenna_selection_info: ASEL Capability | |
| 1604 | 1696 | * |
| 1605 | − * This structure is the "HT capabilities element" as | |
| 1606 | − * described in 802.11n D5.0 7.3.2.57 | |
| 1697 | + * This structure represents the payload of the "HT Capabilities | |
| 1698 | + * element" as described in IEEE Std 802.11-2020 section 9.4.2.55. | |
| 1607 | 1699 | */ |
| 1608 | 1700 | struct ieee80211_ht_cap { |
| 1609 | 1701 | __le16 cap_info; |
| @@ -1691,9 +1783,14 @@ enum ieee80211_min_mpdu_spacing { · 81 unmodified lines | ||
| 1691 | 1783 | |
| 1692 | 1784 | /** |
| 1693 | 1785 | * struct ieee80211_ht_operation - HT operation IE |
| 1786 | + * @primary_chan: Primary Channel | |
| 1787 | + * @ht_param: HT Operation Information parameters | |
| 1788 | + * @operation_mode: HT Operation Information operation mode | |
| 1789 | + * @stbc_param: HT Operation Information STBC params | |
| 1790 | + * @basic_set: Basic HT-MCS Set | |
| 1694 | 1791 | * |
| 1695 | − * This structure is the "HT operation element" as | |
| 1696 | − * described in 802.11n-2009 7.3.2.57 | |
| 1792 | + * This structure represents the payload of the "HT Operation | |
| 1793 | + * element" as described in IEEE Std 802.11-2020 section 9.4.2.56. | |
| 1697 | 1794 | */ |
| 1698 | 1795 | struct ieee80211_ht_operation { |
| 1699 | 1796 | u8 primary_chan; |
| @@ -1862,9 +1959,12 @@ struct ieee80211_vht_operation { · 162 unmodified lines | ||
| 1862 | 1959 | |
| 1863 | 1960 | /** |
| 1864 | 1961 | * struct ieee80211_he_cap_elem - HE capabilities element |
| 1962 | + * @mac_cap_info: HE MAC Capabilities Information | |
| 1963 | + * @phy_cap_info: HE PHY Capabilities Information | |
| 1865 | 1964 | * |
| 1866 | − * This structure is the "HE capabilities element" fixed fields as | |
| 1867 | − * described in P802.11ax_D4.0 section 9.4.2.242.2 and 9.4.2.242.3 | |
| 1965 | + * This structure represents the fixed fields of the payload of the | |
| 1966 | + * "HE capabilities element" as described in IEEE Std 802.11ax-2021 | |
| 1967 | + * sections 9.4.2.248.2 and 9.4.2.248.3. | |
| 1868 | 1968 | */ |
| 1869 | 1969 | struct ieee80211_he_cap_elem { |
| 1870 | 1970 | u8 mac_cap_info[6]; |
| @@ -1923,35 +2023,45 @@ struct ieee80211_he_mcs_nss_supp { · 52 unmodified lines | ||
| 1923 | 2023 | } __packed; |
| 1924 | 2024 | |
| 1925 | 2025 | /** |
| 1926 | − * struct ieee80211_he_operation - HE capabilities element | |
| 2026 | + * struct ieee80211_he_operation - HE Operation element | |
| 2027 | + * @he_oper_params: HE Operation Parameters + BSS Color Information | |
| 2028 | + * @he_mcs_nss_set: Basic HE-MCS And NSS Set | |
| 2029 | + * @optional: Optional fields VHT Operation Information, Max Co-Hosted | |
| 2030 | + * BSSID Indicator, and 6 GHz Operation Information | |
| 1927 | 2031 | * |
| 1928 | − * This structure is the "HE operation element" fields as | |
| 1929 | − * described in P802.11ax_D4.0 section 9.4.2.243 | |
| 2032 | + * This structure represents the payload of the "HE Operation | |
| 2033 | + * element" as described in IEEE Std 802.11ax-2021 section 9.4.2.249. | |
| 1930 | 2034 | */ |
| 1931 | 2035 | struct ieee80211_he_operation { |
| 1932 | 2036 | __le32 he_oper_params; |
| 1933 | 2037 | __le16 he_mcs_nss_set; |
| 1934 | − /* Optional 0,1,3,4,5,7 or 8 bytes: depends on @he_oper_params */ | |
| 1935 | 2038 | u8 optional[]; |
| 1936 | 2039 | } __packed; |
| 1937 | 2040 | |
| 1938 | 2041 | /** |
| 1939 | − * struct ieee80211_he_spr - HE spatial reuse element | |
| 2042 | + * struct ieee80211_he_spr - Spatial Reuse Parameter Set element | |
| 2043 | + * @he_sr_control: SR Control | |
| 2044 | + * @optional: Optional fields Non-SRG OBSS PD Max Offset, SRG OBSS PD | |
| 2045 | + * Min Offset, SRG OBSS PD Max Offset, SRG BSS Color | |
| 2046 | + * Bitmap, and SRG Partial BSSID Bitmap | |
| 1940 | 2047 | * |
| 1941 | − * This structure is the "HE spatial reuse element" element as | |
| 1942 | − * described in P802.11ax_D4.0 section 9.4.2.241 | |
| 2048 | + * This structure represents the payload of the "Spatial Reuse | |
| 2049 | + * Parameter Set element" as described in IEEE Std 802.11ax-2021 | |
| 2050 | + * section 9.4.2.252. | |
| 1943 | 2051 | */ |
| 1944 | 2052 | struct ieee80211_he_spr { |
| 1945 | 2053 | u8 he_sr_control; |
| 1946 | − /* Optional 0 to 19 bytes: depends on @he_sr_control */ | |
| 1947 | 2054 | u8 optional[]; |
| 1948 | 2055 | } __packed; |
| 1949 | 2056 | |
| 1950 | 2057 | /** |
| 1951 | 2058 | * struct ieee80211_he_mu_edca_param_ac_rec - MU AC Parameter Record field |
| 2059 | + * @aifsn: ACI/AIFSN | |
| 2060 | + * @ecw_min_max: ECWmin/ECWmax | |
| 2061 | + * @mu_edca_timer: MU EDCA Timer | |
| 1952 | 2062 | * |
| 1953 | − * This structure is the "MU AC Parameter Record" fields as | |
| 1954 | − * described in P802.11ax_D4.0 section 9.4.2.245 | |
| 2063 | + * This structure represents the "MU AC Parameter Record" as described | |
| 2064 | + * in IEEE Std 802.11ax-2021 section 9.4.2.251, Figure 9-788p. | |
| 1955 | 2065 | */ |
| 1956 | 2066 | struct ieee80211_he_mu_edca_param_ac_rec { |
| 1957 | 2067 | u8 aifsn; |
| @@ -1961,9 +2071,14 @@ struct ieee80211_he_mu_edca_param_ac_rec { · 3 unmodified lines | ||
| 1961 | 2071 | |
| 1962 | 2072 | /** |
| 1963 | 2073 | * struct ieee80211_mu_edca_param_set - MU EDCA Parameter Set element |
| 2074 | + * @mu_qos_info: QoS Info | |
| 2075 | + * @ac_be: MU AC_BE Parameter Record | |
| 2076 | + * @ac_bk: MU AC_BK Parameter Record | |
| 2077 | + * @ac_vi: MU AC_VI Parameter Record | |
| 2078 | + * @ac_vo: MU AC_VO Parameter Record | |
| 1964 | 2079 | * |
| 1965 | − * This structure is the "MU EDCA Parameter Set element" fields as | |
| 1966 | − * described in P802.11ax_D4.0 section 9.4.2.245 | |
| 2080 | + * This structure represents the payload of the "MU EDCA Parameter Set | |
| 2081 | + * element" as described in IEEE Std 802.11ax-2021 section 9.4.2.251. | |
| 1967 | 2082 | */ |
| 1968 | 2083 | struct ieee80211_mu_edca_param_set { |
| 1969 | 2084 | u8 mu_qos_info; |
| @@ -2177,9 +2292,9 @@ int ieee80211_get_vht_max_nss(struct ieee80211_vht_cap *cap, · 207 unmodified lines | ||
| 2177 | 2292 | * enum ieee80211_ap_reg_power - regulatory power for a Access Point |
| 2178 | 2293 | * |
| 2179 | 2294 | * @IEEE80211_REG_UNSET_AP: Access Point has no regulatory power mode |
| 2180 | − * @IEEE80211_REG_LPI: Indoor Access Point | |
| 2181 | − * @IEEE80211_REG_SP: Standard power Access Point | |
| 2182 | − * @IEEE80211_REG_VLP: Very low power Access Point | |
| 2295 | + * @IEEE80211_REG_LPI_AP: Indoor Access Point | |
| 2296 | + * @IEEE80211_REG_SP_AP: Standard power Access Point | |
| 2297 | + * @IEEE80211_REG_VLP_AP: Very low power Access Point | |
| 2183 | 2298 | * @IEEE80211_REG_AP_POWER_AFTER_LAST: internal |
| 2184 | 2299 | * @IEEE80211_REG_AP_POWER_MAX: maximum value |
| 2185 | 2300 | */ |
| @@ -2567,7 +2682,7 @@ static inline bool ieee80211_he_capa_size_ok(const u8 *data, u8 len) · 381 unmodified lines | ||
| 2567 | 2682 | #define IEEE80211_6GHZ_CTRL_REG_SP_AP 1 |
| 2568 | 2683 | |
| 2569 | 2684 | /** |
| 2570 | − * ieee80211_he_6ghz_oper - HE 6 GHz operation Information field | |
| 2685 | + * struct ieee80211_he_6ghz_oper - HE 6 GHz operation Information field | |
| 2571 | 2686 | * @primary: primary channel |
| 2572 | 2687 | * @control: control flags |
| 2573 | 2688 | * @ccfs0: channel center frequency segment 0 |
| @@ -2614,9 +2729,13 @@ enum ieee80211_tx_power_intrpt_type { · 40 unmodified lines | ||
| 2614 | 2729 | }; |
| 2615 | 2730 | |
| 2616 | 2731 | /** |
| 2617 | − * struct ieee80211_tx_pwr_env | |
| 2732 | + * struct ieee80211_tx_pwr_env - Transmit Power Envelope | |
| 2733 | + * @tx_power_info: Transmit Power Information field | |
| 2734 | + * @tx_power: Maximum Transmit Power field | |
| 2618 | 2735 | * |
| 2619 | − * This structure represents the "Transmit Power Envelope element" | |
| 2736 | + * This structure represents the payload of the "Transmit Power | |
| 2737 | + * Envelope element" as described in IEEE Std 802.11ax-2021 section | |
| 2738 | + * 9.4.2.161 | |
| 2620 | 2739 | */ |
| 2621 | 2740 | struct ieee80211_tx_pwr_env { |
| 2622 | 2741 | u8 tx_power_info; |
| @@ -4478,7 +4597,7 @@ static inline bool for_each_element_completed(const struct element *element, · 1855 unmodified lines | ||
| 4478 | 4597 | return (const u8 *)element == (const u8 *)data + datalen; |
| 4479 | 4598 | } |
| 4480 | 4599 | |
| 4481 | −/** | |
| 4600 | +/* | |
| 4482 | 4601 | * RSNX Capabilities: |
| 4483 | 4602 | * bits 0-3: Field length (n-1) |
| 4484 | 4603 | */ |
| @@ -4721,7 +4840,7 @@ ieee80211_mle_get_bss_param_ch_cnt(const struct ieee80211_multi_link_elem *mle) · 236 unmodified lines | ||
| 4721 | 4840 | } |
| 4722 | 4841 | |
| 4723 | 4842 | /** |
| 4724 | − * ieee80211_mle_get_eml_sync_delay - returns the medium sync delay | |
| 4843 | + * ieee80211_mle_get_eml_med_sync_delay - returns the medium sync delay | |
| 4725 | 4844 | * @data: pointer to the multi link EHT IE |
| 4726 | 4845 | * |
| 4727 | 4846 | * The element is assumed to be of the correct type (BASIC) and big enough, |
| @@ -263,7 +263,7 @@ enum ieee80211_privacy { · 262 unmodified lines | ||
| 263 | 263 | * are only for driver use when pointers to this structure are |
| 264 | 264 | * passed around. |
| 265 | 265 | * |
| 266 | − * @flags: rate-specific flags | |
| 266 | + * @flags: rate-specific flags from &enum ieee80211_rate_flags | |
| 267 | 267 | * @bitrate: bitrate in units of 100 Kbps |
| 268 | 268 | * @hw_value: driver/hardware value for this rate |
| 269 | 269 | * @hw_value_short: driver/hardware value for this rate when |
| @@ -811,7 +811,7 @@ struct cfg80211_tid_cfg { · 541 unmodified lines | ||
| 811 | 811 | struct cfg80211_tid_config { |
| 812 | 812 | const u8 *peer; |
| 813 | 813 | u32 n_tid_conf; |
| 814 | − struct cfg80211_tid_cfg tid_conf[]; | |
| 814 | + struct cfg80211_tid_cfg tid_conf[] __counted_by(n_tid_conf); | |
| 815 | 815 | }; |
| 816 | 816 | |
| 817 | 817 | /** |
| @@ -1187,7 +1187,7 @@ struct cfg80211_mbssid_elems { · 369 unmodified lines | ||
| 1187 | 1187 | struct { |
| 1188 | 1188 | const u8 *data; |
| 1189 | 1189 | size_t len; |
| 1190 | − } elem[]; | |
| 1190 | + } elem[] __counted_by(cnt); | |
| 1191 | 1191 | }; |
| 1192 | 1192 | |
| 1193 | 1193 | /** |
| @@ -1204,7 +1204,7 @@ struct cfg80211_rnr_elems { · 10 unmodified lines | ||
| 1204 | 1204 | struct { |
| 1205 | 1205 | const u8 *data; |
| 1206 | 1206 | size_t len; |
| 1207 | − } elem[]; | |
| 1207 | + } elem[] __counted_by(cnt); | |
| 1208 | 1208 | }; |
| 1209 | 1209 | |
| 1210 | 1210 | /** |
| @@ -1282,7 +1282,7 @@ struct cfg80211_acl_data { · 71 unmodified lines | ||
| 1282 | 1282 | int n_acl_entries; |
| 1283 | 1283 | |
| 1284 | 1284 | /* Keep it last */ |
| 1285 | − struct mac_address mac_addrs[]; | |
| 1285 | + struct mac_address mac_addrs[] __counted_by(n_acl_entries); | |
| 1286 | 1286 | }; |
| 1287 | 1287 | |
| 1288 | 1288 | /** |
| @@ -1353,7 +1353,7 @@ struct cfg80211_unsol_bcast_probe_resp { · 64 unmodified lines | ||
| 1353 | 1353 | * @twt_responder: Enable Target Wait Time |
| 1354 | 1354 | * @he_required: stations must support HE |
| 1355 | 1355 | * @sae_h2e_required: stations must support direct H2E technique in SAE |
| 1356 | − * @flags: flags, as defined in enum cfg80211_ap_settings_flags | |
| 1356 | + * @flags: flags, as defined in &enum nl80211_ap_settings_flags | |
| 1357 | 1357 | * @he_obss_pd: OBSS Packet Detection settings |
| 1358 | 1358 | * @he_oper: HE operation IE (or %NULL if HE isn't enabled) |
| 1359 | 1359 | * @fils_discovery: FILS discovery transmission parameters |
| @@ -1482,7 +1482,6 @@ struct iface_combination_params { · 122 unmodified lines | ||
| 1482 | 1482 | * @STATION_PARAM_APPLY_UAPSD: apply new uAPSD parameters (uapsd_queues, max_sp) |
| 1483 | 1483 | * @STATION_PARAM_APPLY_CAPABILITY: apply new capability |
| 1484 | 1484 | * @STATION_PARAM_APPLY_PLINK_STATE: apply new plink state |
| 1485 | − * @STATION_PARAM_APPLY_STA_TXPOWER: apply tx power for STA | |
| 1486 | 1485 | * |
| 1487 | 1486 | * Not all station parameters have in-band "no change" signalling, |
| 1488 | 1487 | * for those that don't these flags will are used. |
| @@ -2156,7 +2155,7 @@ enum mpath_info_flags { · 667 unmodified lines | ||
| 2156 | 2155 | * @sn: target sequence number |
| 2157 | 2156 | * @metric: metric (cost) of this mesh path |
| 2158 | 2157 | * @exptime: expiration time for the mesh path from now, in msecs |
| 2159 | − * @flags: mesh path flags | |
| 2158 | + * @flags: mesh path flags from &enum mesh_path_flags | |
| 2160 | 2159 | * @discovery_timeout: total mesh path discovery timeout, in msecs |
| 2161 | 2160 | * @discovery_retries: mesh path discovery retries |
| 2162 | 2161 | * @generation: generation number for nl80211 dumps. |
| @@ -2496,7 +2495,7 @@ struct cfg80211_scan_6ghz_params { · 333 unmodified lines | ||
| 2496 | 2495 | * the actual dwell time may be shorter. |
| 2497 | 2496 | * @duration_mandatory: if set, the scan duration must be as specified by the |
| 2498 | 2497 | * %duration field. |
| 2499 | − * @flags: bit field of flags controlling operation | |
| 2498 | + * @flags: control flags from &enum nl80211_scan_flags | |
| 2500 | 2499 | * @rates: bitmap of rates to advertise for each band |
| 2501 | 2500 | * @wiphy: the wiphy this was for |
| 2502 | 2501 | * @scan_start: time (in jiffies) when the scan started |
| @@ -2544,7 +2543,7 @@ struct cfg80211_scan_request { · 41 unmodified lines | ||
| 2544 | 2543 | struct cfg80211_scan_6ghz_params *scan_6ghz_params; |
| 2545 | 2544 | |
| 2546 | 2545 | /* keep last */ |
| 2547 | − struct ieee80211_channel *channels[]; | |
| 2546 | + struct ieee80211_channel *channels[] __counted_by(n_channels); | |
| 2548 | 2547 | }; |
| 2549 | 2548 | |
| 2550 | 2549 | static inline void get_random_mask_addr(u8 *buf, const u8 *addr, const u8 *mask) |
| @@ -2616,7 +2615,7 @@ struct cfg80211_bss_select_adjust { · 65 unmodified lines | ||
| 2616 | 2615 | * @scan_width: channel width for scanning |
| 2617 | 2616 | * @ie: optional information element(s) to add into Probe Request or %NULL |
| 2618 | 2617 | * @ie_len: length of ie in octets |
| 2619 | − * @flags: bit field of flags controlling operation | |
| 2618 | + * @flags: control flags from &enum nl80211_scan_flags | |
| 2620 | 2619 | * @match_sets: sets of parameters to be matched for a scan result |
| 2621 | 2620 | * entry to be considered valid and to be passed to the host |
| 2622 | 2621 | * (others are filtered out). |
| @@ -3948,7 +3947,7 @@ struct cfg80211_pmsr_request { · 1325 unmodified lines | ||
| 3948 | 3947 | |
| 3949 | 3948 | struct list_head list; |
| 3950 | 3949 | |
| 3951 | − struct cfg80211_pmsr_request_peer peers[]; | |
| 3950 | + struct cfg80211_pmsr_request_peer peers[] __counted_by(n_peers); | |
| 3952 | 3951 | }; |
| 3953 | 3952 | |
| 3954 | 3953 | /** |
| @@ -8118,7 +8117,7 @@ void cfg80211_conn_failed(struct net_device *dev, const u8 *mac_addr, · 4163 unmodified lines | ||
| 8118 | 8117 | * @link_id: the ID of the link the frame was received on |
| 8119 | 8118 | * @buf: Management frame (header + body) |
| 8120 | 8119 | * @len: length of the frame data |
| 8121 | − * @flags: flags, as defined in enum nl80211_rxmgmt_flags | |
| 8120 | + * @flags: flags, as defined in &enum nl80211_rxmgmt_flags | |
| 8122 | 8121 | * @rx_tstamp: Hardware timestamp of frame RX in nanoseconds |
| 8123 | 8122 | * @ack_tstamp: Hardware timestamp of ack TX in nanoseconds |
| 8124 | 8123 | */ |
| @@ -21,7 +21,7 @@ · 20 unmodified lines | ||
| 21 | 21 | #include <asm/unaligned.h> |
| 22 | 22 | |
| 23 | 23 | /** |
| 24 | − * struct ieee82011_radiotap_header - base radiotap header | |
| 24 | + * struct ieee80211_radiotap_header - base radiotap header | |
| 25 | 25 | */ |
| 26 | 26 | struct ieee80211_radiotap_header { |
| 27 | 27 | /** |
| @@ -575,6 +575,7 @@ enum ieee80211_radiotap_eht_usig_tb { · 547 unmodified lines | ||
| 575 | 575 | |
| 576 | 576 | /** |
| 577 | 577 | * ieee80211_get_radiotap_len - get radiotap header length |
| 578 | + * @data: pointer to the header | |
| 578 | 579 | */ |
| 579 | 580 | static inline u16 ieee80211_get_radiotap_len(const char *data) |
| 580 | 581 | { |
| @@ -426,17 +426,10 @@ struct iw_public_data { · 425 unmodified lines | ||
| 426 | 426 | |
| 427 | 427 | /**************************** PROTOTYPES ****************************/ |
| 428 | 428 | /* |
| 429 | − * Functions part of the Wireless Extensions (defined in net/core/wireless.c). | |
| 430 | − * Those may be called only within the kernel. | |
| 429 | + * Functions part of the Wireless Extensions (defined in net/wireless/wext-core.c). | |
| 430 | + * Those may be called by driver modules. | |
| 431 | 431 | */ |
| 432 | 432 | |
| 433 | −/* First : function strictly used inside the kernel */ | |
| 434 | − | |
| 435 | −/* Handle /proc/net/wireless, called in net/code/dev.c */ | |
| 436 | −int dev_get_wireless_info(char *buffer, char **start, off_t offset, int length); | |
| 437 | − | |
| 438 | −/* Second : functions that may be called by driver modules */ | |
| 439 | − | |
| 440 | 433 | /* Send a single event to user space */ |
| 441 | 434 | void wireless_send_event(struct net_device *dev, unsigned int cmd, |
| 442 | 435 | union iwreq_data *wrqu, const char *extra); |
| @@ -1192,9 +1192,11 @@ struct ieee80211_tx_info { · 1191 unmodified lines | ||
| 1192 | 1192 | u8 ampdu_ack_len; |
| 1193 | 1193 | u8 ampdu_len; |
| 1194 | 1194 | u8 antenna; |
| 1195 | + u8 pad; | |
| 1195 | 1196 | u16 tx_time; |
| 1196 | 1197 | u8 flags; |
| 1197 | − void *status_driver_data[18 / sizeof(void *)]; | |
| 1198 | + u8 pad2; | |
| 1199 | + void *status_driver_data[16 / sizeof(void *)]; | |
| 1198 | 1200 | } status; |
| 1199 | 1201 | struct { |
| 1200 | 1202 | struct ieee80211_tx_rate driver_rates[ |
| @@ -2259,6 +2261,7 @@ struct ieee80211_sta_aggregates { · 1058 unmodified lines | ||
| 2259 | 2261 | * @he_cap: HE capabilities of this STA |
| 2260 | 2262 | * @he_6ghz_capa: on 6 GHz, holds the HE 6 GHz band capabilities |
| 2261 | 2263 | * @eht_cap: EHT capabilities of this STA |
| 2264 | + * @agg: per-link data for multi-link aggregation | |
| 2262 | 2265 | * @bandwidth: current bandwidth the station can receive with |
| 2263 | 2266 | * @rx_nss: in HT/VHT, the maximum number of spatial streams the |
| 2264 | 2267 | * station can receive at the moment, changed by operating mode |
| @@ -3648,12 +3648,6 @@ static int __ieee80211_csa_finalize(struct ieee80211_sub_if_data *sdata) · 3647 unmodified lines | ||
| 3648 | 3648 | lockdep_assert_held(&local->mtx); |
| 3649 | 3649 | lockdep_assert_held(&local->chanctx_mtx); |
| 3650 | 3650 | |
| 3651 | − if (sdata->vif.bss_conf.eht_puncturing != sdata->vif.bss_conf.csa_punct_bitmap) { | |
| 3652 | − sdata->vif.bss_conf.eht_puncturing = | |
| 3653 | − sdata->vif.bss_conf.csa_punct_bitmap; | |
| 3654 | − changed |= BSS_CHANGED_EHT_PUNCTURING; | |
| 3655 | − } | |
| 3656 | − | |
| 3657 | 3651 | /* |
| 3658 | 3652 | * using reservation isn't immediate as it may be deferred until later |
| 3659 | 3653 | * with multi-vif. once reservation is complete it will re-schedule the |
| @@ -3683,6 +3677,12 @@ static int __ieee80211_csa_finalize(struct ieee80211_sub_if_data *sdata) · 23 unmodified lines | ||
| 3683 | 3677 | if (err) |
| 3684 | 3678 | return err; |
| 3685 | 3679 | |
| 3680 | + if (sdata->vif.bss_conf.eht_puncturing != sdata->vif.bss_conf.csa_punct_bitmap) { | |
| 3681 | + sdata->vif.bss_conf.eht_puncturing = | |
| 3682 | + sdata->vif.bss_conf.csa_punct_bitmap; | |
| 3683 | + changed |= BSS_CHANGED_EHT_PUNCTURING; | |
| 3684 | + } | |
| 3685 | + | |
| 3686 | 3686 | ieee80211_link_info_change_notify(sdata, &sdata->deflink, changed); |
| 3687 | 3687 | |
| 3688 | 3688 | if (sdata->deflink.csa_block_tx) { |
| @@ -4133,19 +4133,20 @@ static int ieee80211_probe_client(struct wiphy *wiphy, struct net_device *dev, · 444 unmodified lines | ||
| 4133 | 4133 | mutex_lock(&local->mtx); |
| 4134 | 4134 | |
| 4135 | 4135 | rcu_read_lock(); |
| 4136 | + sta = sta_info_get_bss(sdata, peer); | |
| 4137 | + if (!sta) { | |
| 4138 | + ret = -ENOLINK; | |
| 4139 | + goto unlock; | |
| 4140 | + } | |
| 4141 | + | |
| 4142 | + qos = sta->sta.wme; | |
| 4143 | + | |
| 4136 | 4144 | chanctx_conf = rcu_dereference(sdata->vif.bss_conf.chanctx_conf); |
| 4137 | 4145 | if (WARN_ON(!chanctx_conf)) { |
| 4138 | 4146 | ret = -EINVAL; |
| 4139 | 4147 | goto unlock; |
| 4140 | 4148 | } |
| 4141 | 4149 | band = chanctx_conf->def.chan->band; |
| 4142 | − sta = sta_info_get_bss(sdata, peer); | |
| 4143 | − if (sta) { | |
| 4144 | − qos = sta->sta.wme; | |
| 4145 | − } else { | |
| 4146 | − ret = -ENOLINK; | |
| 4147 | − goto unlock; | |
| 4148 | − } | |
| 4149 | 4150 | |
| 4150 | 4151 | if (qos) { |
| 4151 | 4152 | fc = cpu_to_le16(IEEE80211_FTYPE_DATA | |
| @@ -5,9 +5,9 @@ · 4 unmodified lines | ||
| 5 | 5 | */ |
| 6 | 6 | |
| 7 | 7 | #include <crypto/aes.h> |
| 8 | −#include <crypto/algapi.h> | |
| 9 | 8 | #include <crypto/hash.h> |
| 10 | 9 | #include <crypto/skcipher.h> |
| 10 | +#include <crypto/utils.h> | |
| 11 | 11 | |
| 12 | 12 | #include "ieee80211_i.h" |
| 13 | 13 | #include "aes_cmac.h" |
| @@ -1872,7 +1872,6 @@ void ieee80211_send_pspoll(struct ieee80211_local *local, · 1871 unmodified lines | ||
| 1872 | 1872 | struct ieee80211_sub_if_data *sdata); |
| 1873 | 1873 | void ieee80211_recalc_ps(struct ieee80211_local *local); |
| 1874 | 1874 | void ieee80211_recalc_ps_vif(struct ieee80211_sub_if_data *sdata); |
| 1875 | −int ieee80211_set_arp_filter(struct ieee80211_sub_if_data *sdata); | |
| 1876 | 1875 | void ieee80211_sta_work(struct ieee80211_sub_if_data *sdata); |
| 1877 | 1876 | void ieee80211_sta_rx_queued_mgmt(struct ieee80211_sub_if_data *sdata, |
| 1878 | 1877 | struct sk_buff *skb); |
| @@ -2564,7 +2563,6 @@ void ieee80211_recalc_chanctx_min_def(struct ieee80211_local *local, · 685 unmodified lines | ||
| 2564 | 2563 | struct ieee80211_link_data *rsvd_for); |
| 2565 | 2564 | bool ieee80211_is_radar_required(struct ieee80211_local *local); |
| 2566 | 2565 | |
| 2567 | −void ieee80211_dfs_cac_timer(unsigned long data); | |
| 2568 | 2566 | void ieee80211_dfs_cac_timer_work(struct work_struct *work); |
| 2569 | 2567 | void ieee80211_dfs_cac_cancel(struct ieee80211_local *local); |
| 2570 | 2568 | void ieee80211_dfs_radar_detected_work(struct work_struct *work); |
| @@ -9,6 +9,7 @@ · 8 unmodified lines | ||
| 9 | 9 | * Copyright 2018-2020, 2022-2023 Intel Corporation |
| 10 | 10 | */ |
| 11 | 11 | |
| 12 | +#include <crypto/utils.h> | |
| 12 | 13 | #include <linux/if_ether.h> |
| 13 | 14 | #include <linux/etherdevice.h> |
| 14 | 15 | #include <linux/list.h> |
| @@ -17,7 +18,6 @@ · 2 unmodified lines | ||
| 17 | 18 | #include <linux/slab.h> |
| 18 | 19 | #include <linux/export.h> |
| 19 | 20 | #include <net/mac80211.h> |
| 20 | −#include <crypto/algapi.h> | |
| 21 | 21 | #include <asm/unaligned.h> |
| 22 | 22 | #include "ieee80211_i.h" |
| 23 | 23 | #include "driver-ops.h" |
| @@ -212,7 +212,6 @@ int mesh_rmc_check(struct ieee80211_sub_if_data *sdata, · 211 unmodified lines | ||
| 212 | 212 | const u8 *addr, struct ieee80211s_hdr *mesh_hdr); |
| 213 | 213 | bool mesh_matches_local(struct ieee80211_sub_if_data *sdata, |
| 214 | 214 | struct ieee802_11_elems *ie); |
| 215 | −void mesh_ids_set_default(struct ieee80211_if_mesh *mesh); | |
| 216 | 215 | int mesh_add_meshconf_ie(struct ieee80211_sub_if_data *sdata, |
| 217 | 216 | struct sk_buff *skb); |
| 218 | 217 | int mesh_add_meshid_ie(struct ieee80211_sub_if_data *sdata, |
| @@ -3734,6 +3734,10 @@ ieee80211_rx_h_action(struct ieee80211_rx_data *rx) · 3733 unmodified lines | ||
| 3734 | 3734 | break; |
| 3735 | 3735 | goto queue; |
| 3736 | 3736 | case WLAN_CATEGORY_S1G: |
| 3737 | + if (len < offsetofend(typeof(*mgmt), | |
| 3738 | + u.action.u.s1g.action_code)) | |
| 3739 | + break; | |
| 3740 | + | |
| 3737 | 3741 | switch (mgmt->u.action.u.s1g.action_code) { |
| 3738 | 3742 | case WLAN_S1G_TWT_SETUP: |
| 3739 | 3743 | case WLAN_S1G_TWT_TEARDOWN: |
| @@ -15,7 +15,7 @@ · 14 unmodified lines | ||
| 15 | 15 | #include <asm/unaligned.h> |
| 16 | 16 | #include <net/mac80211.h> |
| 17 | 17 | #include <crypto/aes.h> |
| 18 | −#include <crypto/algapi.h> | |
| 18 | +#include <crypto/utils.h> | |
| 19 | 19 | |
| 20 | 20 | #include "ieee80211_i.h" |
| 21 | 21 | #include "michael.h" |
| @@ -298,7 +298,7 @@ struct cfg80211_cqm_config { · 297 unmodified lines | ||
| 298 | 298 | u32 rssi_hyst; |
| 299 | 299 | s32 last_rssi_event_value; |
| 300 | 300 | int n_rssi_thresholds; |
| 301 | − s32 rssi_thresholds[]; | |
| 301 | + s32 rssi_thresholds[] __counted_by(n_rssi_thresholds); | |
| 302 | 302 | }; |
| 303 | 303 | |
| 304 | 304 | void cfg80211_destroy_ifaces(struct cfg80211_registered_device *rdev); |
| @@ -281,6 +281,11 @@ int cfg80211_mlme_auth(struct cfg80211_registered_device *rdev, · 280 unmodified lines | ||
| 281 | 281 | ether_addr_equal(req->bss->bssid, wdev->u.client.connected_addr)) |
| 282 | 282 | return -EALREADY; |
| 283 | 283 | |
| 284 | + if (ether_addr_equal(req->bss->bssid, dev->dev_addr) || | |
| 285 | + (req->link_id >= 0 && | |
| 286 | + ether_addr_equal(req->ap_mld_addr, dev->dev_addr))) | |
| 287 | + return -EINVAL; | |
| 288 | + | |
| 284 | 289 | return rdev_auth(rdev, dev, req); |
| 285 | 290 | } |
| 286 | 291 | |
| @@ -335,6 +340,9 @@ int cfg80211_mlme_assoc(struct cfg80211_registered_device *rdev, · 48 unmodified lines | ||
| 335 | 340 | if (req->links[i].bss == req->links[j].bss) |
| 336 | 341 | return -EINVAL; |
| 337 | 342 | } |
| 343 | + | |
| 344 | + if (ether_addr_equal(req->links[i].bss->bssid, dev->dev_addr)) | |
| 345 | + return -EINVAL; | |
| 338 | 346 | } |
| 339 | 347 | |
| 340 | 348 | if (wdev->connected && |
| @@ -342,6 +350,11 @@ int cfg80211_mlme_assoc(struct cfg80211_registered_device *rdev, · 1 unmodified line | ||
| 342 | 350 | !ether_addr_equal(wdev->u.client.connected_addr, req->prev_bssid))) |
| 343 | 351 | return -EALREADY; |
| 344 | 352 | |
| 353 | + if ((req->bss && ether_addr_equal(req->bss->bssid, dev->dev_addr)) || | |
| 354 | + (req->link_id >= 0 && | |
| 355 | + ether_addr_equal(req->ap_mld_addr, dev->dev_addr))) | |
| 356 | + return -EINVAL; | |
| 357 | + | |
| 345 | 358 | cfg80211_oper_and_ht_capa(&req->ht_capa_mask, |
| 346 | 359 | rdev->wiphy.ht_capa_mod_mask); |
| 347 | 360 | cfg80211_oper_and_vht_capa(&req->vht_capa_mask, |
| @@ -323,6 +323,7 @@ nl80211_pmsr_ftm_req_attr_policy[NL80211_PMSR_FTM_REQ_ATTR_MAX + 1] = { · 322 unmodified lines | ||
| 323 | 323 | [NL80211_PMSR_FTM_REQ_ATTR_TRIGGER_BASED] = { .type = NLA_FLAG }, |
| 324 | 324 | [NL80211_PMSR_FTM_REQ_ATTR_NON_TRIGGER_BASED] = { .type = NLA_FLAG }, |
| 325 | 325 | [NL80211_PMSR_FTM_REQ_ATTR_LMR_FEEDBACK] = { .type = NLA_FLAG }, |
| 326 | + [NL80211_PMSR_FTM_REQ_ATTR_BSS_COLOR] = { .type = NLA_U8 }, | |
| 326 | 327 | }; |
| 327 | 328 | |
| 328 | 329 | static const struct nla_policy |
| @@ -4889,13 +4890,12 @@ static struct cfg80211_acl_data *parse_acl_data(struct wiphy *wiphy, · 4560 unmodified lines | ||
| 4889 | 4890 | acl = kzalloc(struct_size(acl, mac_addrs, n_entries), GFP_KERNEL); |
| 4890 | 4891 | if (!acl) |
| 4891 | 4892 | return ERR_PTR(-ENOMEM); |
| 4893 | + acl->n_acl_entries = n_entries; | |
| 4892 | 4894 | |
| 4893 | 4895 | nla_for_each_nested(attr, info->attrs[NL80211_ATTR_MAC_ADDRS], tmp) { |
| 4894 | 4896 | memcpy(acl->mac_addrs[i].addr, nla_data(attr), ETH_ALEN); |
| 4895 | 4897 | i++; |
| 4896 | 4898 | } |
| 4897 | − | |
| 4898 | − acl->n_acl_entries = n_entries; | |
| 4899 | 4899 | acl->acl_policy = acl_policy; |
| 4900 | 4900 | |
| 4901 | 4901 | return acl; |
| @@ -5439,13 +5439,13 @@ nl80211_parse_mbssid_elems(struct wiphy *wiphy, struct nlattr *attrs) · 537 unmodified lines | ||
| 5439 | 5439 | elems = kzalloc(struct_size(elems, elem, num_elems), GFP_KERNEL); |
| 5440 | 5440 | if (!elems) |
| 5441 | 5441 | return ERR_PTR(-ENOMEM); |
| 5442 | + elems->cnt = num_elems; | |
| 5442 | 5443 | |
| 5443 | 5444 | nla_for_each_nested(nl_elems, attrs, rem_elems) { |
| 5444 | 5445 | elems->elem[i].data = nla_data(nl_elems); |
| 5445 | 5446 | elems->elem[i].len = nla_len(nl_elems); |
| 5446 | 5447 | i++; |
| 5447 | 5448 | } |
| 5448 | − elems->cnt = num_elems; | |
| 5449 | 5449 | return elems; |
| 5450 | 5450 | } |
| 5451 | 5451 | |
| @@ -5471,13 +5471,13 @@ nl80211_parse_rnr_elems(struct wiphy *wiphy, struct nlattr *attrs, · 19 unmodified lines | ||
| 5471 | 5471 | elems = kzalloc(struct_size(elems, elem, num_elems), GFP_KERNEL); |
| 5472 | 5472 | if (!elems) |
| 5473 | 5473 | return ERR_PTR(-ENOMEM); |
| 5474 | + elems->cnt = num_elems; | |
| 5474 | 5475 | |
| 5475 | 5476 | nla_for_each_nested(nl_elems, attrs, rem_elems) { |
| 5476 | 5477 | elems->elem[i].data = nla_data(nl_elems); |
| 5477 | 5478 | elems->elem[i].len = nla_len(nl_elems); |
| 5478 | 5479 | i++; |
| 5479 | 5480 | } |
| 5480 | − elems->cnt = num_elems; | |
| 5481 | 5481 | return elems; |
| 5482 | 5482 | } |
| 5483 | 5483 | |
| @@ -120,6 +120,5 @@ void cfg80211_rdev_free_coalesce(struct cfg80211_registered_device *rdev); · 119 unmodified lines | ||
| 120 | 120 | |
| 121 | 121 | /* peer measurement */ |
| 122 | 122 | int nl80211_pmsr_start(struct sk_buff *skb, struct genl_info *info); |
| 123 | −int nl80211_pmsr_dump_results(struct sk_buff *skb, struct netlink_callback *cb); | |
| 124 | 123 | |
| 125 | 124 | #endif /* __NET_WIRELESS_NL80211_H */ |
| @@ -68,6 +68,9 @@ int __cfg80211_leave_ocb(struct cfg80211_registered_device *rdev, · 67 unmodified lines | ||
| 68 | 68 | if (!rdev->ops->leave_ocb) |
| 69 | 69 | return -EOPNOTSUPP; |
| 70 | 70 | |
| 71 | + if (!wdev->u.ocb.chandef.chan) | |
| 72 | + return -ENOTCONN; | |
| 73 | + | |
| 71 | 74 | err = rdev_leave_ocb(rdev, dev); |
| 72 | 75 | if (!err) |
| 73 | 76 | memset(&wdev->u.ocb.chandef, 0, sizeof(wdev->u.ocb.chandef)); |
| @@ -291,6 +291,7 @@ int nl80211_pmsr_start(struct sk_buff *skb, struct genl_info *info) · 290 unmodified lines | ||
| 291 | 291 | req = kzalloc(struct_size(req, peers, count), GFP_KERNEL); |
| 292 | 292 | if (!req) |
| 293 | 293 | return -ENOMEM; |
| 294 | + req->n_peers = count; | |
| 294 | 295 | |
| 295 | 296 | if (info->attrs[NL80211_ATTR_TIMEOUT]) |
| 296 | 297 | req->timeout = nla_get_u32(info->attrs[NL80211_ATTR_TIMEOUT]); |
| @@ -321,8 +322,6 @@ int nl80211_pmsr_start(struct sk_buff *skb, struct genl_info *info) · 24 unmodified lines | ||
| 321 | 322 | goto out_err; |
| 322 | 323 | idx++; |
| 323 | 324 | } |
| 324 | − | |
| 325 | − req->n_peers = count; | |
| 326 | 325 | req->cookie = cfg80211_assign_cookie(rdev); |
| 327 | 326 | req->nl_portid = info->snd_portid; |
| 328 | 327 | |