lael-labs/linux

drivers/infiniband/core/addr.c+0−1

@@ -37,7 +37,6 @@ · 36 unmodified lines
37	#include <linux/inetdevice.h>	37	#include <linux/inetdevice.h>
38	#include <linux/slab.h>	38	#include <linux/slab.h>
39	#include <linux/workqueue.h>	39	#include <linux/workqueue.h>
40	#include <linux/module.h>
41	#include <net/arp.h>	40	#include <net/arp.h>
42	#include <net/neighbour.h>	41	#include <net/neighbour.h>
43	#include <net/route.h>	42	#include <net/route.h>

drivers/infiniband/core/cache.c+0−1

@@ -34,7 +34,6 @@ · 33 unmodified lines
34	*/	34	*/
35		35
36	#include <linux/if_vlan.h>	36	#include <linux/if_vlan.h>
37	#include <linux/module.h>
38	#include <linux/errno.h>	37	#include <linux/errno.h>
39	#include <linux/slab.h>	38	#include <linux/slab.h>
40	#include <linux/workqueue.h>	39	#include <linux/workqueue.h>

drivers/infiniband/core/cma.c+1−1

@@ -2642,7 +2642,7 @@ int rdma_set_ack_timeout(struct rdma_cm_id *id, u8 timeout) · 2641 unmodified lines
2642	{	2642	{
2643	struct rdma_id_private *id_priv;	2643	struct rdma_id_private *id_priv;
2644		2644
2645	if (id->qp_type != IB_QPT_RC)	2645	if (id->qp_type != IB_QPT_RC && id->qp_type != IB_QPT_XRC_INI)
2646	return -EINVAL;	2646	return -EINVAL;
2647		2647
2648	id_priv = container_of(id, struct rdma_id_private, id);	2648	id_priv = container_of(id, struct rdma_id_private, id);

drivers/infiniband/core/cma_configfs.c+0−1

@@ -30,7 +30,6 @@ · 29 unmodified lines
30	* SOFTWARE.	30	* SOFTWARE.
31	*/	31	*/
32		32
33	#include <linux/module.h>
34	#include <linux/configfs.h>	33	#include <linux/configfs.h>
35	#include <rdma/ib_verbs.h>	34	#include <rdma/ib_verbs.h>
36	#include <rdma/rdma_cm.h>	35	#include <rdma/rdma_cm.h>

drivers/infiniband/core/cq.c+0−1

@@ -2,7 +2,6 @@ · 1 unmodified line
2	/*	2	/*
3	* Copyright (c) 2015 HGST, a Western Digital Company.	3	* Copyright (c) 2015 HGST, a Western Digital Company.
4	*/	4	*/
5	#include <linux/module.h>
6	#include <linux/err.h>	5	#include <linux/err.h>
7	#include <linux/slab.h>	6	#include <linux/slab.h>
8	#include <rdma/ib_verbs.h>	7	#include <rdma/ib_verbs.h>

drivers/infiniband/core/iwpm_util.h+0−1

@@ -33,7 +33,6 @@ · 32 unmodified lines
33	#ifndef _IWPM_UTIL_H	33	#ifndef _IWPM_UTIL_H
34	#define _IWPM_UTIL_H	34	#define _IWPM_UTIL_H
35		35
36	#include <linux/module.h>
37	#include <linux/io.h>	36	#include <linux/io.h>
38	#include <linux/in.h>	37	#include <linux/in.h>
39	#include <linux/in6.h>	38	#include <linux/in6.h>

drivers/infiniband/core/nldev.c+2−1

 					       u32 port)
 {
 	struct rdma_hw_stats *stats;
-	int rem, i, index, ret = 0;
 	struct nlattr *entry_attr;
 	unsigned long *target;
+	int rem, i, ret = 0;
+	u32 index;
 	stats = ib_get_hw_stats_port(device, port);
 	if (!stats)

drivers/infiniband/core/sa_query.c+0−1

@@ -32,7 +32,6 @@ · 31 unmodified lines
32	* SOFTWARE.	32	* SOFTWARE.
33	*/	33	*/
34		34
35	#include <linux/module.h>
36	#include <linux/init.h>	35	#include <linux/init.h>
37	#include <linux/err.h>	36	#include <linux/err.h>
38	#include <linux/random.h>	37	#include <linux/random.h>

drivers/infiniband/core/verbs.c+1−8

 		return ERR_PTR(-ENOMEM);
 	pd->device = device;
-	pd->uobject = NULL;
-	pd->__internal_mr = NULL;
-	atomic_set(&pd->usecnt, 0);
 	pd->flags = flags;
 	rdma_restrack_new(&pd->res, RDMA_RESTRACK_PD);
 		pd->__internal_mr = NULL;
 	}
-	/* uverbs manipulates usecnt with proper locking, while the kabi
-	 * requires the caller to guarantee we can't race here.
-	 */
-	WARN_ON(atomic_read(&pd->usecnt));
 	ret = pd->device->ops.dealloc_pd(pd, udata);
 	if (ret)
 		return ret;
 		return mr;
 	mr->device = pd->device;
+	mr->type = IB_MR_TYPE_USER;
 	mr->pd = pd;
 	mr->dm = NULL;
 	atomic_inc(&pd->usecnt);

drivers/infiniband/hw/hfi1/affinity.c+2−3

 #include <linux/topology.h>
 #include <linux/cpumask.h>
-#include <linux/module.h>
 #include <linux/interrupt.h>
 #include <linux/numa.h>
 			 * engines, use the same CPU cores as general/control
 			 * context.
 			 */
-			if (cpumask_weight(&entry->def_intr.mask) == 0)
+			if (cpumask_empty(&entry->def_intr.mask))
 				cpumask_copy(&entry->def_intr.mask,
 					     &entry->general_intr_mask);
 		}
 		 * vectors, use the same CPU core as the general/control
 		 * context.
 		 */
-		if (cpumask_weight(&entry->comp_vect_mask) == 0)
+		if (cpumask_empty(&entry->comp_vect_mask))
 			cpumask_copy(&entry->comp_vect_mask,
 				     &entry->general_intr_mask);
 	}

drivers/infiniband/hw/hfi1/debugfs.c+0−1

@@ -7,7 +7,6 @@ · 6 unmodified lines
7	#include <linux/seq_file.h>	7	#include <linux/seq_file.h>
8	#include <linux/kernel.h>	8	#include <linux/kernel.h>
9	#include <linux/export.h>	9	#include <linux/export.h>
10	#include <linux/module.h>
11	#include <linux/string.h>	10	#include <linux/string.h>
12	#include <linux/types.h>	11	#include <linux/types.h>
13	#include <linux/ratelimit.h>	12	#include <linux/ratelimit.h>

drivers/infiniband/hw/hfi1/device.c+0−1

@@ -4,7 +4,6 @@ · 3 unmodified lines
4	*/	4	*/
5		5
6	#include <linux/cdev.h>	6	#include <linux/cdev.h>
7	#include <linux/module.h>
8	#include <linux/device.h>	7	#include <linux/device.h>
9	#include <linux/fs.h>	8	#include <linux/fs.h>
10		9

drivers/infiniband/hw/hfi1/fault.c+0−1

@@ -6,7 +6,6 @@ · 5 unmodified lines
6	#include <linux/debugfs.h>	6	#include <linux/debugfs.h>
7	#include <linux/seq_file.h>	7	#include <linux/seq_file.h>
8	#include <linux/kernel.h>	8	#include <linux/kernel.h>
9	#include <linux/module.h>
10	#include <linux/types.h>	9	#include <linux/types.h>
11	#include <linux/bitmap.h>	10	#include <linux/bitmap.h>
12		11

drivers/infiniband/hw/hfi1/firmware.c+0−1

@@ -5,7 +5,6 @@ · 4 unmodified lines
5		5
6	#include <linux/firmware.h>	6	#include <linux/firmware.h>
7	#include <linux/mutex.h>	7	#include <linux/mutex.h>
8	#include <linux/module.h>
9	#include <linux/delay.h>	8	#include <linux/delay.h>
10	#include <linux/crc32.h>	9	#include <linux/crc32.h>
11		10

drivers/infiniband/hw/hfi1/verbs.c+1−2

@@ -1397,8 +1397,7 @@ static int query_port(struct rvt_dev_info *rdi, u32 port_num, · 1396 unmodified lines
1397	4096 : hfi1_max_mtu), IB_MTU_4096);	1397	4096 : hfi1_max_mtu), IB_MTU_4096);
1398	props->active_mtu = !valid_ib_mtu(ppd->ibmtu) ? props->max_mtu :	1398	props->active_mtu = !valid_ib_mtu(ppd->ibmtu) ? props->max_mtu :
1399	mtu_to_enum(ppd->ibmtu, IB_MTU_4096);	1399	mtu_to_enum(ppd->ibmtu, IB_MTU_4096);
1400	props->phys_mtu = HFI1_CAP_IS_KSET(AIP) ? hfi1_max_mtu :	1400	props->phys_mtu = hfi1_max_mtu;
1401	ib_mtu_enum_to_int(props->max_mtu);
1402		1401
1403	return 0;	1402	return 0;
1404	}	1403	}

drivers/infiniband/hw/hns/hns_roce_cmd.c+51−46

@@ -38,45 +38,36 @@ · 37 unmodified lines
38	#define CMD_POLL_TOKEN 0xffff	38	#define CMD_POLL_TOKEN 0xffff
39	#define CMD_MAX_NUM 32	39	#define CMD_MAX_NUM 32
40		40
41	static int hns_roce_cmd_mbox_post_hw(struct hns_roce_dev *hr_dev, u64 in_param,	41	static int hns_roce_cmd_mbox_post_hw(struct hns_roce_dev *hr_dev,
42	u64 out_param, u32 in_modifier,	42	struct hns_roce_mbox_msg *mbox_msg)
43	u8 op_modifier, u16 op, u16 token,
44	int event)
45	{	43	{
46	return hr_dev->hw->post_mbox(hr_dev, in_param, out_param, in_modifier,	44	return hr_dev->hw->post_mbox(hr_dev, mbox_msg);
47	op_modifier, op, token, event);
48	}	45	}
49		46
50	/* this should be called with "poll_sem" */	47	/* this should be called with "poll_sem" */
51	static int __hns_roce_cmd_mbox_poll(struct hns_roce_dev *hr_dev, u64 in_param,	48	static int __hns_roce_cmd_mbox_poll(struct hns_roce_dev *hr_dev,
52	u64 out_param, unsigned long in_modifier,	49	struct hns_roce_mbox_msg *mbox_msg)
53	u8 op_modifier, u16 op,
54	unsigned int timeout)
55	{	50	{
56	int ret;	51	int ret;
57		52
58	ret = hns_roce_cmd_mbox_post_hw(hr_dev, in_param, out_param,	53	ret = hns_roce_cmd_mbox_post_hw(hr_dev, mbox_msg);
59	in_modifier, op_modifier, op,
60	CMD_POLL_TOKEN, 0);
61	if (ret) {	54	if (ret) {
62	dev_err_ratelimited(hr_dev->dev,	55	dev_err_ratelimited(hr_dev->dev,
63	"failed to post mailbox 0x%x in poll mode, ret = %d.\n",	56	"failed to post mailbox 0x%x in poll mode, ret = %d.\n",
64	op, ret);	57	mbox_msg->cmd, ret);
65	return ret;	58	return ret;
66	}	59	}
67		60
68	return hr_dev->hw->poll_mbox_done(hr_dev, timeout);	61	return hr_dev->hw->poll_mbox_done(hr_dev);
69	}	62	}
70		63
71	static int hns_roce_cmd_mbox_poll(struct hns_roce_dev *hr_dev, u64 in_param,	64	static int hns_roce_cmd_mbox_poll(struct hns_roce_dev *hr_dev,
72	u64 out_param, unsigned long in_modifier,	65	struct hns_roce_mbox_msg *mbox_msg)
73	u8 op_modifier, u16 op, unsigned int timeout)
74	{	66	{
75	int ret;	67	int ret;
76		68
77	down(&hr_dev->cmd.poll_sem);	69	down(&hr_dev->cmd.poll_sem);
78	ret = __hns_roce_cmd_mbox_poll(hr_dev, in_param, out_param, in_modifier,	70	ret = __hns_roce_cmd_mbox_poll(hr_dev, mbox_msg);
79	op_modifier, op, timeout);
80	up(&hr_dev->cmd.poll_sem);	71	up(&hr_dev->cmd.poll_sem);
81		72
82	return ret;	73	return ret;
@@ -100,10 +91,8 @@ void hns_roce_cmd_event(struct hns_roce_dev *hr_dev, u16 token, u8 status, · 17 unmodified lines
100	complete(&context->done);	91	complete(&context->done);
101	}	92	}
102		93
103	static int __hns_roce_cmd_mbox_wait(struct hns_roce_dev *hr_dev, u64 in_param,	94	static int __hns_roce_cmd_mbox_wait(struct hns_roce_dev *hr_dev,
104	u64 out_param, unsigned long in_modifier,	95	struct hns_roce_mbox_msg *mbox_msg)
105	u8 op_modifier, u16 op,
106	unsigned int timeout)
107	{	96	{
108	struct hns_roce_cmdq *cmd = &hr_dev->cmd;	97	struct hns_roce_cmdq *cmd = &hr_dev->cmd;
109	struct hns_roce_cmd_context *context;	98	struct hns_roce_cmd_context *context;
@@ -124,20 +113,19 @@ static int __hns_roce_cmd_mbox_wait(struct hns_roce_dev *hr_dev, u64 in_param, · 14 unmodified lines
124		113
125	reinit_completion(&context->done);	114	reinit_completion(&context->done);
126		115
127	ret = hns_roce_cmd_mbox_post_hw(hr_dev, in_param, out_param,	116	mbox_msg->token = context->token;
128	in_modifier, op_modifier, op,	117	ret = hns_roce_cmd_mbox_post_hw(hr_dev, mbox_msg);
129	context->token, 1);
130	if (ret) {	118	if (ret) {
131	dev_err_ratelimited(dev,	119	dev_err_ratelimited(dev,
132	"failed to post mailbox 0x%x in event mode, ret = %d.\n",	120	"failed to post mailbox 0x%x in event mode, ret = %d.\n",
133	op, ret);	121	mbox_msg->cmd, ret);
134	goto out;	122	goto out;
135	}	123	}
136		124
137	if (!wait_for_completion_timeout(&context->done,	125	if (!wait_for_completion_timeout(&context->done,
138	msecs_to_jiffies(timeout))) {	126	msecs_to_jiffies(HNS_ROCE_CMD_TIMEOUT_MSECS))) {
139	dev_err_ratelimited(dev, "[cmd] token 0x%x mailbox 0x%x timeout.\n",	127	dev_err_ratelimited(dev, "[cmd] token 0x%x mailbox 0x%x timeout.\n",
140	context->token, op);	128	context->token, mbox_msg->cmd);
141	ret = -EBUSY;	129	ret = -EBUSY;
142	goto out;	130	goto out;
143	}	131	}
@@ -145,45 +133,50 @@ static int __hns_roce_cmd_mbox_wait(struct hns_roce_dev *hr_dev, u64 in_param, · 1 unmodified line
145	ret = context->result;	133	ret = context->result;
146	if (ret)	134	if (ret)
147	dev_err_ratelimited(dev, "[cmd] token 0x%x mailbox 0x%x error %d.\n",	135	dev_err_ratelimited(dev, "[cmd] token 0x%x mailbox 0x%x error %d.\n",
148	context->token, op, ret);	136	context->token, mbox_msg->cmd, ret);
149		137
150	out:	138	out:
151	context->busy = 0;	139	context->busy = 0;
152	return ret;	140	return ret;
153	}	141	}
154		142
155	static int hns_roce_cmd_mbox_wait(struct hns_roce_dev *hr_dev, u64 in_param,	143	static int hns_roce_cmd_mbox_wait(struct hns_roce_dev *hr_dev,
156	u64 out_param, unsigned long in_modifier,	144	struct hns_roce_mbox_msg *mbox_msg)
157	u8 op_modifier, u16 op, unsigned int timeout)
158	{	145	{
159	int ret;	146	int ret;
160		147
161	down(&hr_dev->cmd.event_sem);	148	down(&hr_dev->cmd.event_sem);
162	ret = __hns_roce_cmd_mbox_wait(hr_dev, in_param, out_param, in_modifier,	149	ret = __hns_roce_cmd_mbox_wait(hr_dev, mbox_msg);
163	op_modifier, op, timeout);
164	up(&hr_dev->cmd.event_sem);	150	up(&hr_dev->cmd.event_sem);
165		151
166	return ret;	152	return ret;
167	}	153	}
168		154
169	int hns_roce_cmd_mbox(struct hns_roce_dev *hr_dev, u64 in_param, u64 out_param,	155	int hns_roce_cmd_mbox(struct hns_roce_dev *hr_dev, u64 in_param, u64 out_param,
170	unsigned long in_modifier, u8 op_modifier, u16 op,	156	u8 cmd, unsigned long tag)
171	unsigned int timeout)
172	{	157	{
		158	struct hns_roce_mbox_msg mbox_msg = {};
173	bool is_busy;	159	bool is_busy;
174		160
175	if (hr_dev->hw->chk_mbox_avail)	161	if (hr_dev->hw->chk_mbox_avail)
176	if (!hr_dev->hw->chk_mbox_avail(hr_dev, &is_busy))	162	if (!hr_dev->hw->chk_mbox_avail(hr_dev, &is_busy))
177	return is_busy ? -EBUSY : 0;	163	return is_busy ? -EBUSY : 0;
178		164
179	if (hr_dev->cmd.use_events)	165	mbox_msg.in_param = in_param;
180	return hns_roce_cmd_mbox_wait(hr_dev, in_param, out_param,	166	mbox_msg.out_param = out_param;
181	in_modifier, op_modifier, op,	167	mbox_msg.cmd = cmd;
182	timeout);	168	mbox_msg.tag = tag;
183	else	169
184	return hns_roce_cmd_mbox_poll(hr_dev, in_param, out_param,	170	if (hr_dev->cmd.use_events) {
185	in_modifier, op_modifier, op,	171	mbox_msg.event_en = 1;
186	timeout);	172
		173	return hns_roce_cmd_mbox_wait(hr_dev, &mbox_msg);
		174	} else {
		175	mbox_msg.event_en = 0;
		176	mbox_msg.token = CMD_POLL_TOKEN;
		177
		178	return hns_roce_cmd_mbox_poll(hr_dev, &mbox_msg);
		179	}
187	}	180	}
188		181
189	int hns_roce_cmd_init(struct hns_roce_dev *hr_dev)	182	int hns_roce_cmd_init(struct hns_roce_dev *hr_dev)
@@ -269,3 +262,15 @@ void hns_roce_free_cmd_mailbox(struct hns_roce_dev *hr_dev, · 79 unmodified lines
269	dma_pool_free(hr_dev->cmd.pool, mailbox->buf, mailbox->dma);	262	dma_pool_free(hr_dev->cmd.pool, mailbox->buf, mailbox->dma);
270	kfree(mailbox);	263	kfree(mailbox);
271	}	264	}
		265
		266	int hns_roce_create_hw_ctx(struct hns_roce_dev *dev,
		267	struct hns_roce_cmd_mailbox *mailbox,
		268	u8 cmd, unsigned long idx)
		269	{
		270	return hns_roce_cmd_mbox(dev, mailbox->dma, 0, cmd, idx);
		271	}
		272
		273	int hns_roce_destroy_hw_ctx(struct hns_roce_dev *dev, u8 cmd, unsigned long idx)
		274	{
		275	return hns_roce_cmd_mbox(dev, 0, 0, cmd, idx);
		276	}

drivers/infiniband/hw/hns/hns_roce_cmd.h+6−2

 };
 int hns_roce_cmd_mbox(struct hns_roce_dev *hr_dev, u64 in_param, u64 out_param,
-		      unsigned long in_modifier, u8 op_modifier, u16 op,
+		      u8 cmd, unsigned long tag);
-		      unsigned int timeout);
 struct hns_roce_cmd_mailbox *
 hns_roce_alloc_cmd_mailbox(struct hns_roce_dev *hr_dev);
 void hns_roce_free_cmd_mailbox(struct hns_roce_dev *hr_dev,
 			       struct hns_roce_cmd_mailbox *mailbox);
+int hns_roce_create_hw_ctx(struct hns_roce_dev *dev,
+			   struct hns_roce_cmd_mailbox *mailbox,
+			   u8 cmd, unsigned long idx);
+int hns_roce_destroy_hw_ctx(struct hns_roce_dev *dev, u8 cmd,
+			    unsigned long idx);
 #endif /* _HNS_ROCE_CMD_H */

drivers/infiniband/hw/hns/hns_roce_cq.c+39−32

 	mutex_unlock(&cq_table->bank_mutex);
 }
+static int hns_roce_create_cqc(struct hns_roce_dev *hr_dev,
+			       struct hns_roce_cq *hr_cq,
+			       u64 *mtts, dma_addr_t dma_handle)
+{
+	struct ib_device *ibdev = &hr_dev->ib_dev;
+	struct hns_roce_cmd_mailbox *mailbox;
+	int ret;
+	mailbox = hns_roce_alloc_cmd_mailbox(hr_dev);
+	if (IS_ERR(mailbox)) {
+		ibdev_err(ibdev, "failed to alloc mailbox for CQC.\n");
+		return PTR_ERR(mailbox);
+	}
+	hr_dev->hw->write_cqc(hr_dev, hr_cq, mailbox->buf, mtts, dma_handle);
+	ret = hns_roce_create_hw_ctx(hr_dev, mailbox, HNS_ROCE_CMD_CREATE_CQC,
+				     hr_cq->cqn);
+	if (ret)
+		ibdev_err(ibdev,
+			  "failed to send create cmd for CQ(0x%lx), ret = %d.\n",
+			  hr_cq->cqn, ret);
+	hns_roce_free_cmd_mailbox(hr_dev, mailbox);
+	return ret;
+}
 static int alloc_cqc(struct hns_roce_dev *hr_dev, struct hns_roce_cq *hr_cq)
 {
 	struct hns_roce_cq_table *cq_table = &hr_dev->cq_table;
 	struct ib_device *ibdev = &hr_dev->ib_dev;
-	struct hns_roce_cmd_mailbox *mailbox;
+	u64 mtts[MTT_MIN_COUNT] = {};
-	u64 mtts[MTT_MIN_COUNT] = { 0 };
 	dma_addr_t dma_handle;
 	int ret;
 	if (ret) {
 		ibdev_err(ibdev, "failed to get CQ(0x%lx) context, ret = %d.\n",
 			  hr_cq->cqn, ret);
-		goto err_out;
+		return ret;
 	}
 	ret = xa_err(xa_store(&cq_table->array, hr_cq->cqn, hr_cq, GFP_KERNEL));
 		goto err_put;
 	}
-	/* Allocate mailbox memory */
+	ret = hns_roce_create_cqc(hr_dev, hr_cq, mtts, dma_handle);
-	mailbox = hns_roce_alloc_cmd_mailbox(hr_dev);
+	if (ret)
-	if (IS_ERR(mailbox)) {
-		ret = PTR_ERR(mailbox);
-		goto err_xa;
-	}
-	hr_dev->hw->write_cqc(hr_dev, hr_cq, mailbox->buf, mtts, dma_handle);
-	/* Send mailbox to hw */
-	ret = hns_roce_cmd_mbox(hr_dev, mailbox->dma, 0, hr_cq->cqn, 0,
-			HNS_ROCE_CMD_CREATE_CQC, HNS_ROCE_CMD_TIMEOUT_MSECS);
-	hns_roce_free_cmd_mailbox(hr_dev, mailbox);
-	if (ret) {
-		ibdev_err(ibdev,
-			  "failed to send create cmd for CQ(0x%lx), ret = %d.\n",
-			  hr_cq->cqn, ret);
 		goto err_xa;
-	}
-	hr_cq->cons_index = 0;
-	hr_cq->arm_sn = 1;
-	refcount_set(&hr_cq->refcount, 1);
-	init_completion(&hr_cq->free);
 	return 0;
 err_xa:
 	xa_erase(&cq_table->array, hr_cq->cqn);
 err_put:
 	hns_roce_table_put(hr_dev, &cq_table->table, hr_cq->cqn);
-err_out:
 	return ret;
 }
 	struct device *dev = hr_dev->dev;
 	int ret;
-	ret = hns_roce_cmd_mbox(hr_dev, 0, 0, hr_cq->cqn, 1,
+	ret = hns_roce_destroy_hw_ctx(hr_dev, HNS_ROCE_CMD_DESTROY_CQC,
-				HNS_ROCE_CMD_DESTROY_CQC,
+				      hr_cq->cqn);
-				HNS_ROCE_CMD_TIMEOUT_MSECS);
 	if (ret)
 		dev_err(dev, "DESTROY_CQ failed (%d) for CQN %06lx\n", ret,
 			hr_cq->cqn);
 			goto err_cqc;
 	}
+	hr_cq->cons_index = 0;
+	hr_cq->arm_sn = 1;
+	refcount_set(&hr_cq->refcount, 1);
+	init_completion(&hr_cq->free);
 	return 0;
 err_cqc:

drivers/infiniband/hw/hns/hns_roce_device.h+16−10

 	dma_addr_t		dma;
 };
+struct hns_roce_mbox_msg {
+	u64 in_param;
+	u64 out_param;
+	u8 cmd;
+	u32 tag;
+	u16 token;
+	u8 event_en;
+};
 struct hns_roce_dev;
 struct hns_roce_rinl_sge {
 	u32			next_sge;
 	enum ib_mtu		path_mtu;
 	u32			max_inline_data;
+	u8			free_mr_en;
 	/* 0: flush needed, 1: unneeded */
 	unsigned long		flush_flag;
 	int (*hw_profile)(struct hns_roce_dev *hr_dev);
 	int (*hw_init)(struct hns_roce_dev *hr_dev);
 	void (*hw_exit)(struct hns_roce_dev *hr_dev);
-	int (*post_mbox)(struct hns_roce_dev *hr_dev, u64 in_param,
+	int (*post_mbox)(struct hns_roce_dev *hr_dev,
-			 u64 out_param, u32 in_modifier, u8 op_modifier, u16 op,
+			 struct hns_roce_mbox_msg *mbox_msg);
-			 u16 token, int event);
+	int (*poll_mbox_done)(struct hns_roce_dev *hr_dev);
-	int (*poll_mbox_done)(struct hns_roce_dev *hr_dev,
-			      unsigned int timeout);
 	bool (*chk_mbox_avail)(struct hns_roce_dev *hr_dev, bool *is_busy);
 	int (*set_gid)(struct hns_roce_dev *hr_dev, int gid_index,
 		       const union ib_gid *gid, const struct ib_gid_attr *attr);
 			  struct hns_roce_cq *hr_cq, void *mb_buf, u64 *mtts,
 			  dma_addr_t dma_handle);
 	int (*set_hem)(struct hns_roce_dev *hr_dev,
-		       struct hns_roce_hem_table *table, int obj, int step_idx);
+		       struct hns_roce_hem_table *table, int obj, u32 step_idx);
 	int (*clear_hem)(struct hns_roce_dev *hr_dev,
 			 struct hns_roce_hem_table *table, int obj,
-			 int step_idx);
+			 u32 step_idx);
 	int (*modify_qp)(struct ib_qp *ibqp, const struct ib_qp_attr *attr,
 			 int attr_mask, enum ib_qp_state cur_state,
 			 enum ib_qp_state new_state);
 	int (*qp_flow_control_init)(struct hns_roce_dev *hr_dev,
 			 struct hns_roce_qp *hr_qp);
+	void (*dereg_mr)(struct hns_roce_dev *hr_dev);
 	int (*init_eq)(struct hns_roce_dev *hr_dev);
 	void (*cleanup_eq)(struct hns_roce_dev *hr_dev);
 	int (*write_srqc)(struct hns_roce_srq *srq, void *mb_buf);
 int hns_roce_map_mr_sg(struct ib_mr *ibmr, struct scatterlist *sg, int sg_nents,
 		       unsigned int *sg_offset);
 int hns_roce_dereg_mr(struct ib_mr *ibmr, struct ib_udata *udata);
-int hns_roce_hw_destroy_mpt(struct hns_roce_dev *hr_dev,
-			    struct hns_roce_cmd_mailbox *mailbox,
-			    unsigned long mpt_index);
 unsigned long key_to_hw_index(u32 key);
 int hns_roce_alloc_mw(struct ib_mw *mw, struct ib_udata *udata);

drivers/infiniband/hw/hns/hns_roce_hem.c+2−2

@@ -488,7 +488,7 @@ static int set_mhop_hem(struct hns_roce_dev *hr_dev, · 487 unmodified lines
488	struct hns_roce_hem_index *index)	488	struct hns_roce_hem_index *index)
489	{	489	{
490	struct ib_device *ibdev = &hr_dev->ib_dev;	490	struct ib_device *ibdev = &hr_dev->ib_dev;
491	int step_idx;	491	u32 step_idx;
492	int ret = 0;	492	int ret = 0;
493		493
494	if (index->inited & HEM_INDEX_L0) {	494	if (index->inited & HEM_INDEX_L0) {
@@ -618,7 +618,7 @@ static void clear_mhop_hem(struct hns_roce_dev *hr_dev, · 123 unmodified lines
618	struct ib_device *ibdev = &hr_dev->ib_dev;	618	struct ib_device *ibdev = &hr_dev->ib_dev;
619	u32 hop_num = mhop->hop_num;	619	u32 hop_num = mhop->hop_num;
620	u32 chunk_ba_num;	620	u32 chunk_ba_num;
621	int step_idx;	621	u32 step_idx;
622		622
623	index->inited = HEM_INDEX_BUF;	623	index->inited = HEM_INDEX_BUF;
624	chunk_ba_num = mhop->bt_chunk_size / BA_BYTE_LEN;	624	chunk_ba_num = mhop->bt_chunk_size / BA_BYTE_LEN;

drivers/infiniband/hw/hns/hns_roce_hw_v2.c+377−81

@@ -1344,17 +1344,17 @@ static int hns_roce_cmq_send(struct hns_roce_dev *hr_dev, · 1343 unmodified lines
1344	return ret;	1344	return ret;
1345	}	1345	}
1346		1346
1347	static int config_hem_ba_to_hw(struct hns_roce_dev *hr_dev, unsigned long obj,	1347	static int config_hem_ba_to_hw(struct hns_roce_dev *hr_dev,
1348	dma_addr_t base_addr, u16 op)	1348	dma_addr_t base_addr, u8 cmd, unsigned long tag)
1349	{	1349	{
1350	struct hns_roce_cmd_mailbox *mbox = hns_roce_alloc_cmd_mailbox(hr_dev);	1350	struct hns_roce_cmd_mailbox *mbox;
1351	int ret;	1351	int ret;
1352		1352
		1353	mbox = hns_roce_alloc_cmd_mailbox(hr_dev);
1353	if (IS_ERR(mbox))	1354	if (IS_ERR(mbox))
1354	return PTR_ERR(mbox);	1355	return PTR_ERR(mbox);
1355		1356
1356	ret = hns_roce_cmd_mbox(hr_dev, base_addr, mbox->dma, obj, 0, op,	1357	ret = hns_roce_cmd_mbox(hr_dev, base_addr, mbox->dma, cmd, tag);
1357	HNS_ROCE_CMD_TIMEOUT_MSECS);
1358	hns_roce_free_cmd_mailbox(hr_dev, mbox);	1358	hns_roce_free_cmd_mailbox(hr_dev, mbox);
1359	return ret;	1359	return ret;
1360	}	1360	}
@@ -2664,6 +2664,194 @@ static void free_dip_list(struct hns_roce_dev *hr_dev) · 1303 unmodified lines
2664	spin_unlock_irqrestore(&hr_dev->dip_list_lock, flags);	2664	spin_unlock_irqrestore(&hr_dev->dip_list_lock, flags);
2665	}	2665	}
2666		2666
		2667	static void free_mr_exit(struct hns_roce_dev *hr_dev)
		2668	{
		2669	struct hns_roce_v2_priv *priv = hr_dev->priv;
		2670	struct hns_roce_v2_free_mr *free_mr = &priv->free_mr;
		2671	int ret;
		2672	int i;
		2673
		2674	for (i = 0; i < ARRAY_SIZE(free_mr->rsv_qp); i++) {
		2675	if (free_mr->rsv_qp[i]) {
		2676	ret = ib_destroy_qp(free_mr->rsv_qp[i]);
		2677	if (ret)
		2678	ibdev_err(&hr_dev->ib_dev,
		2679	"failed to destroy qp in free mr.\n");
		2680
		2681	free_mr->rsv_qp[i] = NULL;
		2682	}
		2683	}
		2684
		2685	if (free_mr->rsv_cq) {
		2686	ib_destroy_cq(free_mr->rsv_cq);
		2687	free_mr->rsv_cq = NULL;
		2688	}
		2689
		2690	if (free_mr->rsv_pd) {
		2691	ib_dealloc_pd(free_mr->rsv_pd);
		2692	free_mr->rsv_pd = NULL;
		2693	}
		2694	}
		2695
		2696	static int free_mr_alloc_res(struct hns_roce_dev *hr_dev)
		2697	{
		2698	struct hns_roce_v2_priv *priv = hr_dev->priv;
		2699	struct hns_roce_v2_free_mr *free_mr = &priv->free_mr;
		2700	struct ib_device *ibdev = &hr_dev->ib_dev;
		2701	struct ib_cq_init_attr cq_init_attr = {};
		2702	struct ib_qp_init_attr qp_init_attr = {};
		2703	struct ib_pd *pd;
		2704	struct ib_cq *cq;
		2705	struct ib_qp *qp;
		2706	int ret;
		2707	int i;
		2708
		2709	pd = ib_alloc_pd(ibdev, 0);
		2710	if (IS_ERR(pd)) {
		2711	ibdev_err(ibdev, "failed to create pd for free mr.\n");
		2712	return PTR_ERR(pd);
		2713	}
		2714	free_mr->rsv_pd = pd;
		2715
		2716	cq_init_attr.cqe = HNS_ROCE_FREE_MR_USED_CQE_NUM;
		2717	cq = ib_create_cq(ibdev, NULL, NULL, NULL, &cq_init_attr);
		2718	if (IS_ERR(cq)) {
		2719	ibdev_err(ibdev, "failed to create cq for free mr.\n");
		2720	ret = PTR_ERR(cq);
		2721	goto create_failed;
		2722	}
		2723	free_mr->rsv_cq = cq;
		2724
		2725	qp_init_attr.qp_type = IB_QPT_RC;
		2726	qp_init_attr.sq_sig_type = IB_SIGNAL_ALL_WR;
		2727	qp_init_attr.send_cq = free_mr->rsv_cq;
		2728	qp_init_attr.recv_cq = free_mr->rsv_cq;
		2729	for (i = 0; i < ARRAY_SIZE(free_mr->rsv_qp); i++) {
		2730	qp_init_attr.cap.max_send_wr = HNS_ROCE_FREE_MR_USED_SQWQE_NUM;
		2731	qp_init_attr.cap.max_send_sge = HNS_ROCE_FREE_MR_USED_SQSGE_NUM;
		2732	qp_init_attr.cap.max_recv_wr = HNS_ROCE_FREE_MR_USED_RQWQE_NUM;
		2733	qp_init_attr.cap.max_recv_sge = HNS_ROCE_FREE_MR_USED_RQSGE_NUM;
		2734
		2735	qp = ib_create_qp(free_mr->rsv_pd, &qp_init_attr);
		2736	if (IS_ERR(qp)) {
		2737	ibdev_err(ibdev, "failed to create qp for free mr.\n");
		2738	ret = PTR_ERR(qp);
		2739	goto create_failed;
		2740	}
		2741
		2742	free_mr->rsv_qp[i] = qp;
		2743	}
		2744
		2745	return 0;
		2746
		2747	create_failed:
		2748	free_mr_exit(hr_dev);
		2749
		2750	return ret;
		2751	}
		2752
		2753	static int free_mr_modify_rsv_qp(struct hns_roce_dev *hr_dev,
		2754	struct ib_qp_attr *attr, int sl_num)
		2755	{
		2756	struct hns_roce_v2_priv *priv = hr_dev->priv;
		2757	struct hns_roce_v2_free_mr *free_mr = &priv->free_mr;
		2758	struct ib_device *ibdev = &hr_dev->ib_dev;
		2759	struct hns_roce_qp *hr_qp;
		2760	int loopback;
		2761	int mask;
		2762	int ret;
		2763
		2764	hr_qp = to_hr_qp(free_mr->rsv_qp[sl_num]);
		2765	hr_qp->free_mr_en = 1;
		2766
		2767	mask = IB_QP_STATE \| IB_QP_PKEY_INDEX \| IB_QP_PORT \| IB_QP_ACCESS_FLAGS;
		2768	attr->qp_state = IB_QPS_INIT;
		2769	attr->port_num = 1;
		2770	attr->qp_access_flags = IB_ACCESS_REMOTE_WRITE;
		2771	ret = ib_modify_qp(&hr_qp->ibqp, attr, mask);
		2772	if (ret) {
		2773	ibdev_err(ibdev, "failed to modify qp to init, ret = %d.\n",
		2774	ret);
		2775	return ret;
		2776	}
		2777
		2778	loopback = hr_dev->loop_idc;
		2779	/* Set qpc lbi = 1 incidate loopback IO */
		2780	hr_dev->loop_idc = 1;
		2781
		2782	mask = IB_QP_STATE \| IB_QP_AV \| IB_QP_PATH_MTU \| IB_QP_DEST_QPN \|
		2783	IB_QP_RQ_PSN \| IB_QP_MAX_DEST_RD_ATOMIC \| IB_QP_MIN_RNR_TIMER;
		2784	attr->qp_state = IB_QPS_RTR;
		2785	attr->ah_attr.type = RDMA_AH_ATTR_TYPE_ROCE;
		2786	attr->path_mtu = IB_MTU_256;
		2787	attr->dest_qp_num = hr_qp->qpn;
		2788	attr->rq_psn = HNS_ROCE_FREE_MR_USED_PSN;
		2789
		2790	rdma_ah_set_sl(&attr->ah_attr, (u8)sl_num);
		2791
		2792	ret = ib_modify_qp(&hr_qp->ibqp, attr, mask);
		2793	hr_dev->loop_idc = loopback;
		2794	if (ret) {
		2795	ibdev_err(ibdev, "failed to modify qp to rtr, ret = %d.\n",
		2796	ret);
		2797	return ret;
		2798	}
		2799
		2800	mask = IB_QP_STATE \| IB_QP_SQ_PSN \| IB_QP_RETRY_CNT \| IB_QP_TIMEOUT \|
		2801	IB_QP_RNR_RETRY \| IB_QP_MAX_QP_RD_ATOMIC;
		2802	attr->qp_state = IB_QPS_RTS;
		2803	attr->sq_psn = HNS_ROCE_FREE_MR_USED_PSN;
		2804	attr->retry_cnt = HNS_ROCE_FREE_MR_USED_QP_RETRY_CNT;
		2805	attr->timeout = HNS_ROCE_FREE_MR_USED_QP_TIMEOUT;
		2806	ret = ib_modify_qp(&hr_qp->ibqp, attr, mask);
		2807	if (ret)
		2808	ibdev_err(ibdev, "failed to modify qp to rts, ret = %d.\n",
		2809	ret);
		2810
		2811	return ret;
		2812	}
		2813
		2814	static int free_mr_modify_qp(struct hns_roce_dev *hr_dev)
		2815	{
		2816	struct hns_roce_v2_priv *priv = hr_dev->priv;
		2817	struct hns_roce_v2_free_mr *free_mr = &priv->free_mr;
		2818	struct ib_qp_attr attr = {};
		2819	int ret;
		2820	int i;
		2821
		2822	rdma_ah_set_grh(&attr.ah_attr, NULL, 0, 0, 1, 0);
		2823	rdma_ah_set_static_rate(&attr.ah_attr, 3);
		2824	rdma_ah_set_port_num(&attr.ah_attr, 1);
		2825
		2826	for (i = 0; i < ARRAY_SIZE(free_mr->rsv_qp); i++) {
		2827	ret = free_mr_modify_rsv_qp(hr_dev, &attr, i);
		2828	if (ret)
		2829	return ret;
		2830	}
		2831
		2832	return 0;
		2833	}
		2834
		2835	static int free_mr_init(struct hns_roce_dev *hr_dev)
		2836	{
		2837	int ret;
		2838
		2839	ret = free_mr_alloc_res(hr_dev);
		2840	if (ret)
		2841	return ret;
		2842
		2843	ret = free_mr_modify_qp(hr_dev);
		2844	if (ret)
		2845	goto err_modify_qp;
		2846
		2847	return 0;
		2848
		2849	err_modify_qp:
		2850	free_mr_exit(hr_dev);
		2851
		2852	return ret;
		2853	}
		2854
2667	static int get_hem_table(struct hns_roce_dev *hr_dev)	2855	static int get_hem_table(struct hns_roce_dev *hr_dev)
2668	{	2856	{
2669	unsigned int qpc_count;	2857	unsigned int qpc_count;
@@ -2780,21 +2968,21 @@ static void hns_roce_v2_exit(struct hns_roce_dev *hr_dev) · 110 unmodified lines
2780	free_dip_list(hr_dev);	2968	free_dip_list(hr_dev);
2781	}	2969	}
2782		2970
2783	static int hns_roce_mbox_post(struct hns_roce_dev *hr_dev, u64 in_param,	2971	static int hns_roce_mbox_post(struct hns_roce_dev *hr_dev,
2784	u64 out_param, u32 in_modifier, u8 op_modifier,	2972	struct hns_roce_mbox_msg *mbox_msg)
2785	u16 op, u16 token, int event)
2786	{	2973	{
2787	struct hns_roce_cmq_desc desc;	2974	struct hns_roce_cmq_desc desc;
2788	struct hns_roce_post_mbox mb = (struct hns_roce_post_mbox )desc.data;	2975	struct hns_roce_post_mbox mb = (struct hns_roce_post_mbox )desc.data;
2789		2976
2790	hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_POST_MB, false);	2977	hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_POST_MB, false);
2791		2978
2792	mb->in_param_l = cpu_to_le32(in_param);	2979	mb->in_param_l = cpu_to_le32(mbox_msg->in_param);
2793	mb->in_param_h = cpu_to_le32(in_param >> 32);	2980	mb->in_param_h = cpu_to_le32(mbox_msg->in_param >> 32);
2794	mb->out_param_l = cpu_to_le32(out_param);	2981	mb->out_param_l = cpu_to_le32(mbox_msg->out_param);
2795	mb->out_param_h = cpu_to_le32(out_param >> 32);	2982	mb->out_param_h = cpu_to_le32(mbox_msg->out_param >> 32);
2796	mb->cmd_tag = cpu_to_le32(in_modifier << 8 \| op);	2983	mb->cmd_tag = cpu_to_le32(mbox_msg->tag << 8 \| mbox_msg->cmd);
2797	mb->token_event_en = cpu_to_le32(event << 16 \| token);	2984	mb->token_event_en = cpu_to_le32(mbox_msg->event_en << 16 \|
		2985	mbox_msg->token);
2798		2986
2799	return hns_roce_cmq_send(hr_dev, &desc, 1);	2987	return hns_roce_cmq_send(hr_dev, &desc, 1);
2800	}	2988	}
@@ -2847,9 +3035,8 @@ static int v2_wait_mbox_complete(struct hns_roce_dev *hr_dev, u32 timeout, · 46 unmodified lines
2847	return ret;	3035	return ret;
2848	}	3036	}
2849		3037
2850	static int v2_post_mbox(struct hns_roce_dev *hr_dev, u64 in_param,	3038	static int v2_post_mbox(struct hns_roce_dev *hr_dev,
2851	u64 out_param, u32 in_modifier, u8 op_modifier,	3039	struct hns_roce_mbox_msg *mbox_msg)
2852	u16 op, u16 token, int event)
2853	{	3040	{
2854	u8 status = 0;	3041	u8 status = 0;
2855	int ret;	3042	int ret;
@@ -2865,8 +3052,7 @@ static int v2_post_mbox(struct hns_roce_dev *hr_dev, u64 in_param, · 9 unmodified lines
2865	}	3052	}
2866		3053
2867	/* Post new message to mbox */	3054	/* Post new message to mbox */
2868	ret = hns_roce_mbox_post(hr_dev, in_param, out_param, in_modifier,	3055	ret = hns_roce_mbox_post(hr_dev, mbox_msg);
2869	op_modifier, op, token, event);
2870	if (ret)	3056	if (ret)
2871	dev_err_ratelimited(hr_dev->dev,	3057	dev_err_ratelimited(hr_dev->dev,
2872	"failed to post mailbox, ret = %d.\n", ret);	3058	"failed to post mailbox, ret = %d.\n", ret);
@@ -2874,12 +3060,13 @@ static int v2_post_mbox(struct hns_roce_dev *hr_dev, u64 in_param, · 1 unmodified line
2874	return ret;	3060	return ret;
2875	}	3061	}
2876		3062
2877	static int v2_poll_mbox_done(struct hns_roce_dev *hr_dev, unsigned int timeout)	3063	static int v2_poll_mbox_done(struct hns_roce_dev *hr_dev)
2878	{	3064	{
2879	u8 status = 0;	3065	u8 status = 0;
2880	int ret;	3066	int ret;
2881		3067
2882	ret = v2_wait_mbox_complete(hr_dev, timeout, &status);	3068	ret = v2_wait_mbox_complete(hr_dev, HNS_ROCE_CMD_TIMEOUT_MSECS,
		3069	&status);
2883	if (!ret) {	3070	if (!ret) {
2884	if (status != MB_ST_COMPLETE_SUCC)	3071	if (status != MB_ST_COMPLETE_SUCC)
2885	return -EBUSY;	3072	return -EBUSY;
@@ -3245,6 +3432,98 @@ static int hns_roce_v2_mw_write_mtpt(void mb_buf, struct hns_roce_mw mw) · 359 unmodified lines
3245	return 0;	3432	return 0;
3246	}	3433	}
3247		3434
		3435	static int free_mr_post_send_lp_wqe(struct hns_roce_qp *hr_qp)
		3436	{
		3437	struct hns_roce_dev *hr_dev = to_hr_dev(hr_qp->ibqp.device);
		3438	struct ib_device *ibdev = &hr_dev->ib_dev;
		3439	const struct ib_send_wr *bad_wr;
		3440	struct ib_rdma_wr rdma_wr = {};
		3441	struct ib_send_wr *send_wr;
		3442	int ret;
		3443
		3444	send_wr = &rdma_wr.wr;
		3445	send_wr->opcode = IB_WR_RDMA_WRITE;
		3446
		3447	ret = hns_roce_v2_post_send(&hr_qp->ibqp, send_wr, &bad_wr);
		3448	if (ret) {
		3449	ibdev_err(ibdev, "failed to post wqe for free mr, ret = %d.\n",
		3450	ret);
		3451	return ret;
		3452	}
		3453
		3454	return 0;
		3455	}
		3456
		3457	static int hns_roce_v2_poll_cq(struct ib_cq *ibcq, int num_entries,
		3458	struct ib_wc *wc);
		3459
		3460	static void free_mr_send_cmd_to_hw(struct hns_roce_dev *hr_dev)
		3461	{
		3462	struct hns_roce_v2_priv *priv = hr_dev->priv;
		3463	struct hns_roce_v2_free_mr *free_mr = &priv->free_mr;
		3464	struct ib_wc wc[ARRAY_SIZE(free_mr->rsv_qp)];
		3465	struct ib_device *ibdev = &hr_dev->ib_dev;
		3466	struct hns_roce_qp *hr_qp;
		3467	unsigned long end;
		3468	int cqe_cnt = 0;
		3469	int npolled;
		3470	int ret;
		3471	int i;
		3472
		3473	/*
		3474	* If the device initialization is not complete or in the uninstall
		3475	* process, then there is no need to execute free mr.
		3476	*/
		3477	if (priv->handle->rinfo.reset_state == HNS_ROCE_STATE_RST_INIT \|\|
		3478	priv->handle->rinfo.instance_state == HNS_ROCE_STATE_INIT \|\|
		3479	hr_dev->state == HNS_ROCE_DEVICE_STATE_UNINIT)
		3480	return;
		3481
		3482	mutex_lock(&free_mr->mutex);
		3483
		3484	for (i = 0; i < ARRAY_SIZE(free_mr->rsv_qp); i++) {
		3485	hr_qp = to_hr_qp(free_mr->rsv_qp[i]);
		3486
		3487	ret = free_mr_post_send_lp_wqe(hr_qp);
		3488	if (ret) {
		3489	ibdev_err(ibdev,
		3490	"failed to send wqe (qp:0x%lx) for free mr, ret = %d.\n",
		3491	hr_qp->qpn, ret);
		3492	break;
		3493	}
		3494
		3495	cqe_cnt++;
		3496	}
		3497
		3498	end = msecs_to_jiffies(HNS_ROCE_V2_FREE_MR_TIMEOUT) + jiffies;
		3499	while (cqe_cnt) {
		3500	npolled = hns_roce_v2_poll_cq(free_mr->rsv_cq, cqe_cnt, wc);
		3501	if (npolled < 0) {
		3502	ibdev_err(ibdev,
		3503	"failed to poll cqe for free mr, remain %d cqe.\n",
		3504	cqe_cnt);
		3505	goto out;
		3506	}
		3507
		3508	if (time_after(jiffies, end)) {
		3509	ibdev_err(ibdev,
		3510	"failed to poll cqe for free mr and timeout, remain %d cqe.\n",
		3511	cqe_cnt);
		3512	goto out;
		3513	}
		3514	cqe_cnt -= npolled;
		3515	}
		3516
		3517	out:
		3518	mutex_unlock(&free_mr->mutex);
		3519	}
		3520
		3521	static void hns_roce_v2_dereg_mr(struct hns_roce_dev *hr_dev)
		3522	{
		3523	if (hr_dev->pci_dev->revision == PCI_REVISION_ID_HIP08)
		3524	free_mr_send_cmd_to_hw(hr_dev);
		3525	}
		3526
3248	static void get_cqe_v2(struct hns_roce_cq hr_cq, int n)	3527	static void get_cqe_v2(struct hns_roce_cq hr_cq, int n)
3249	{	3528	{
3250	return hns_roce_buf_offset(hr_cq->mtr.kmem, n * hr_cq->cqe_size);	3529	return hns_roce_buf_offset(hr_cq->mtr.kmem, n * hr_cq->cqe_size);
@@ -3818,38 +4097,38 @@ out: · 567 unmodified lines
3818	}	4097	}
3819		4098
3820	static int get_op_for_set_hem(struct hns_roce_dev *hr_dev, u32 type,	4099	static int get_op_for_set_hem(struct hns_roce_dev *hr_dev, u32 type,
3821	int step_idx, u16 *mbox_op)	4100	u32 step_idx, u8 *mbox_cmd)
3822	{	4101	{
3823	u16 op;	4102	u8 cmd;
3824		4103
3825	switch (type) {	4104	switch (type) {
3826	case HEM_TYPE_QPC:	4105	case HEM_TYPE_QPC:
3827	op = HNS_ROCE_CMD_WRITE_QPC_BT0;	4106	cmd = HNS_ROCE_CMD_WRITE_QPC_BT0;
3828	break;	4107	break;
3829	case HEM_TYPE_MTPT:	4108	case HEM_TYPE_MTPT:
3830	op = HNS_ROCE_CMD_WRITE_MPT_BT0;	4109	cmd = HNS_ROCE_CMD_WRITE_MPT_BT0;
3831	break;	4110	break;
3832	case HEM_TYPE_CQC:	4111	case HEM_TYPE_CQC:
3833	op = HNS_ROCE_CMD_WRITE_CQC_BT0;	4112	cmd = HNS_ROCE_CMD_WRITE_CQC_BT0;
3834	break;	4113	break;
3835	case HEM_TYPE_SRQC:	4114	case HEM_TYPE_SRQC:
3836	op = HNS_ROCE_CMD_WRITE_SRQC_BT0;	4115	cmd = HNS_ROCE_CMD_WRITE_SRQC_BT0;
3837	break;	4116	break;
3838	case HEM_TYPE_SCCC:	4117	case HEM_TYPE_SCCC:
3839	op = HNS_ROCE_CMD_WRITE_SCCC_BT0;	4118	cmd = HNS_ROCE_CMD_WRITE_SCCC_BT0;
3840	break;	4119	break;
3841	case HEM_TYPE_QPC_TIMER:	4120	case HEM_TYPE_QPC_TIMER:
3842	op = HNS_ROCE_CMD_WRITE_QPC_TIMER_BT0;	4121	cmd = HNS_ROCE_CMD_WRITE_QPC_TIMER_BT0;
3843	break;	4122	break;
3844	case HEM_TYPE_CQC_TIMER:	4123	case HEM_TYPE_CQC_TIMER:
3845	op = HNS_ROCE_CMD_WRITE_CQC_TIMER_BT0;	4124	cmd = HNS_ROCE_CMD_WRITE_CQC_TIMER_BT0;
3846	break;	4125	break;
3847	default:	4126	default:
3848	dev_warn(hr_dev->dev, "failed to check hem type %u.\n", type);	4127	dev_warn(hr_dev->dev, "failed to check hem type %u.\n", type);
3849	return -EINVAL;	4128	return -EINVAL;
3850	}	4129	}
3851		4130
3852	*mbox_op = op + step_idx;	4131	*mbox_cmd = cmd + step_idx;
3853		4132
3854	return 0;	4133	return 0;
3855	}	4134	}
@@ -3872,10 +4151,10 @@ static int config_gmv_ba_to_hw(struct hns_roce_dev *hr_dev, unsigned long obj, · 16 unmodified lines
3872	}	4151	}
3873		4152
3874	static int set_hem_to_hw(struct hns_roce_dev *hr_dev, int obj,	4153	static int set_hem_to_hw(struct hns_roce_dev *hr_dev, int obj,
3875	dma_addr_t base_addr, u32 hem_type, int step_idx)	4154	dma_addr_t base_addr, u32 hem_type, u32 step_idx)
3876	{	4155	{
3877	int ret;	4156	int ret;
3878	u16 op;	4157	u8 cmd;
3879		4158
3880	if (unlikely(hem_type == HEM_TYPE_GMV))	4159	if (unlikely(hem_type == HEM_TYPE_GMV))
3881	return config_gmv_ba_to_hw(hr_dev, obj, base_addr);	4160	return config_gmv_ba_to_hw(hr_dev, obj, base_addr);
@@ -3883,16 +4162,16 @@ static int set_hem_to_hw(struct hns_roce_dev *hr_dev, int obj, · 1 unmodified line
3883	if (unlikely(hem_type == HEM_TYPE_SCCC && step_idx))	4162	if (unlikely(hem_type == HEM_TYPE_SCCC && step_idx))
3884	return 0;	4163	return 0;
3885		4164
3886	ret = get_op_for_set_hem(hr_dev, hem_type, step_idx, &op);	4165	ret = get_op_for_set_hem(hr_dev, hem_type, step_idx, &cmd);
3887	if (ret < 0)	4166	if (ret < 0)
3888	return ret;	4167	return ret;
3889		4168
3890	return config_hem_ba_to_hw(hr_dev, obj, base_addr, op);	4169	return config_hem_ba_to_hw(hr_dev, base_addr, cmd, obj);
3891	}	4170	}
3892		4171
3893	static int hns_roce_v2_set_hem(struct hns_roce_dev *hr_dev,	4172	static int hns_roce_v2_set_hem(struct hns_roce_dev *hr_dev,
3894	struct hns_roce_hem_table *table, int obj,	4173	struct hns_roce_hem_table *table, int obj,
3895	int step_idx)	4174	u32 step_idx)
3896	{	4175	{
3897	struct hns_roce_hem_iter iter;	4176	struct hns_roce_hem_iter iter;
3898	struct hns_roce_hem_mhop mhop;	4177	struct hns_roce_hem_mhop mhop;
@@ -3950,29 +4229,29 @@ static int hns_roce_v2_set_hem(struct hns_roce_dev *hr_dev, · 51 unmodified lines
3950	}	4229	}
3951		4230
3952	static int hns_roce_v2_clear_hem(struct hns_roce_dev *hr_dev,	4231	static int hns_roce_v2_clear_hem(struct hns_roce_dev *hr_dev,
3953	struct hns_roce_hem_table *table, int obj,	4232	struct hns_roce_hem_table *table,
3954	int step_idx)	4233	int tag, u32 step_idx)
3955	{	4234	{
3956	struct device *dev = hr_dev->dev;
3957	struct hns_roce_cmd_mailbox *mailbox;	4235	struct hns_roce_cmd_mailbox *mailbox;
		4236	struct device *dev = hr_dev->dev;
		4237	u8 cmd = 0xff;
3958	int ret;	4238	int ret;
3959	u16 op = 0xff;
3960		4239
3961	if (!hns_roce_check_whether_mhop(hr_dev, table->type))	4240	if (!hns_roce_check_whether_mhop(hr_dev, table->type))
3962	return 0;	4241	return 0;
3963		4242
3964	switch (table->type) {	4243	switch (table->type) {
3965	case HEM_TYPE_QPC:	4244	case HEM_TYPE_QPC:
3966	op = HNS_ROCE_CMD_DESTROY_QPC_BT0;	4245	cmd = HNS_ROCE_CMD_DESTROY_QPC_BT0;
3967	break;	4246	break;
3968	case HEM_TYPE_MTPT:	4247	case HEM_TYPE_MTPT:
3969	op = HNS_ROCE_CMD_DESTROY_MPT_BT0;	4248	cmd = HNS_ROCE_CMD_DESTROY_MPT_BT0;
3970	break;	4249	break;
3971	case HEM_TYPE_CQC:	4250	case HEM_TYPE_CQC:
3972	op = HNS_ROCE_CMD_DESTROY_CQC_BT0;	4251	cmd = HNS_ROCE_CMD_DESTROY_CQC_BT0;
3973	break;	4252	break;
3974	case HEM_TYPE_SRQC:	4253	case HEM_TYPE_SRQC:
3975	op = HNS_ROCE_CMD_DESTROY_SRQC_BT0;	4254	cmd = HNS_ROCE_CMD_DESTROY_SRQC_BT0;
3976	break;	4255	break;
3977	case HEM_TYPE_SCCC:	4256	case HEM_TYPE_SCCC:
3978	case HEM_TYPE_QPC_TIMER:	4257	case HEM_TYPE_QPC_TIMER:
@@ -3985,15 +4264,13 @@ static int hns_roce_v2_clear_hem(struct hns_roce_dev *hr_dev, · 6 unmodified lines
3985	return 0;	4264	return 0;
3986	}	4265	}
3987		4266
3988	op += step_idx;	4267	cmd += step_idx;
3989		4268
3990	mailbox = hns_roce_alloc_cmd_mailbox(hr_dev);	4269	mailbox = hns_roce_alloc_cmd_mailbox(hr_dev);
3991	if (IS_ERR(mailbox))	4270	if (IS_ERR(mailbox))
3992	return PTR_ERR(mailbox);	4271	return PTR_ERR(mailbox);
3993		4272
3994	/* configure the tag and op */	4273	ret = hns_roce_cmd_mbox(hr_dev, 0, mailbox->dma, cmd, tag);
3995	ret = hns_roce_cmd_mbox(hr_dev, 0, mailbox->dma, obj, 0, op,
3996	HNS_ROCE_CMD_TIMEOUT_MSECS);
3997		4274
3998	hns_roce_free_cmd_mailbox(hr_dev, mailbox);	4275	hns_roce_free_cmd_mailbox(hr_dev, mailbox);
3999	return ret;	4276	return ret;
@@ -4017,9 +4294,8 @@ static int hns_roce_v2_qp_modify(struct hns_roce_dev *hr_dev, · 17 unmodified lines
4017	memcpy(mailbox->buf, context, qpc_size);	4294	memcpy(mailbox->buf, context, qpc_size);
4018	memcpy(mailbox->buf + qpc_size, qpc_mask, qpc_size);	4295	memcpy(mailbox->buf + qpc_size, qpc_mask, qpc_size);
4019		4296
4020	ret = hns_roce_cmd_mbox(hr_dev, mailbox->dma, 0, hr_qp->qpn, 0,	4297	ret = hns_roce_cmd_mbox(hr_dev, mailbox->dma, 0,
4021	HNS_ROCE_CMD_MODIFY_QPC,	4298	HNS_ROCE_CMD_MODIFY_QPC, hr_qp->qpn);
4022	HNS_ROCE_CMD_TIMEOUT_MSECS);
4023		4299
4024	hns_roce_free_cmd_mailbox(hr_dev, mailbox);	4300	hns_roce_free_cmd_mailbox(hr_dev, mailbox);
4025		4301
@@ -4667,6 +4943,18 @@ static int hns_roce_v2_set_path(struct ib_qp *ibqp, · 641 unmodified lines
4667	u8 hr_port;	4943	u8 hr_port;
4668	int ret;	4944	int ret;
4669		4945
		4946	/*
		4947	* If free_mr_en of qp is set, it means that this qp comes from
		4948	* free mr. This qp will perform the loopback operation.
		4949	* In the loopback scenario, only sl needs to be set.
		4950	*/
		4951	if (hr_qp->free_mr_en) {
		4952	hr_reg_write(context, QPC_SL, rdma_ah_get_sl(&attr->ah_attr));
		4953	hr_reg_clear(qpc_mask, QPC_SL);
		4954	hr_qp->sl = rdma_ah_get_sl(&attr->ah_attr);
		4955	return 0;
		4956	}
		4957
4670	ib_port = (attr_mask & IB_QP_PORT) ? attr->port_num : hr_qp->port + 1;	4958	ib_port = (attr_mask & IB_QP_PORT) ? attr->port_num : hr_qp->port + 1;
4671	hr_port = ib_port - 1;	4959	hr_port = ib_port - 1;
4672	is_roce_protocol = rdma_cap_eth_ah(&hr_dev->ib_dev, ib_port) &&	4960	is_roce_protocol = rdma_cap_eth_ah(&hr_dev->ib_dev, ib_port) &&
@@ -5092,9 +5380,8 @@ static int hns_roce_v2_query_qpc(struct hns_roce_dev *hr_dev, · 419 unmodified lines
5092	if (IS_ERR(mailbox))	5380	if (IS_ERR(mailbox))
5093	return PTR_ERR(mailbox);	5381	return PTR_ERR(mailbox);
5094		5382
5095	ret = hns_roce_cmd_mbox(hr_dev, 0, mailbox->dma, hr_qp->qpn, 0,	5383	ret = hns_roce_cmd_mbox(hr_dev, 0, mailbox->dma, HNS_ROCE_CMD_QUERY_QPC,
5096	HNS_ROCE_CMD_QUERY_QPC,	5384	hr_qp->qpn);
5097	HNS_ROCE_CMD_TIMEOUT_MSECS);
5098	if (ret)	5385	if (ret)
5099	goto out;	5386	goto out;
5100		5387
@@ -5460,9 +5747,8 @@ static int hns_roce_v2_modify_srq(struct ib_srq *ibsrq, · 359 unmodified lines
5460	hr_reg_write(srq_context, SRQC_LIMIT_WL, srq_attr->srq_limit);	5747	hr_reg_write(srq_context, SRQC_LIMIT_WL, srq_attr->srq_limit);
5461	hr_reg_clear(srqc_mask, SRQC_LIMIT_WL);	5748	hr_reg_clear(srqc_mask, SRQC_LIMIT_WL);
5462		5749
5463	ret = hns_roce_cmd_mbox(hr_dev, mailbox->dma, 0, srq->srqn, 0,	5750	ret = hns_roce_cmd_mbox(hr_dev, mailbox->dma, 0,
5464	HNS_ROCE_CMD_MODIFY_SRQC,	5751	HNS_ROCE_CMD_MODIFY_SRQC, srq->srqn);
5465	HNS_ROCE_CMD_TIMEOUT_MSECS);
5466	hns_roce_free_cmd_mailbox(hr_dev, mailbox);	5752	hns_roce_free_cmd_mailbox(hr_dev, mailbox);
5467	if (ret) {	5753	if (ret) {
5468	ibdev_err(&hr_dev->ib_dev,	5754	ibdev_err(&hr_dev->ib_dev,
@@ -5488,9 +5774,8 @@ static int hns_roce_v2_query_srq(struct ib_srq ibsrq, struct ib_srq_attr attr) · 19 unmodified lines
5488	return PTR_ERR(mailbox);	5774	return PTR_ERR(mailbox);
5489		5775
5490	srq_context = mailbox->buf;	5776	srq_context = mailbox->buf;
5491	ret = hns_roce_cmd_mbox(hr_dev, 0, mailbox->dma, srq->srqn, 0,	5777	ret = hns_roce_cmd_mbox(hr_dev, 0, mailbox->dma,
5492	HNS_ROCE_CMD_QUERY_SRQC,	5778	HNS_ROCE_CMD_QUERY_SRQC, srq->srqn);
5493	HNS_ROCE_CMD_TIMEOUT_MSECS);
5494	if (ret) {	5779	if (ret) {
5495	ibdev_err(&hr_dev->ib_dev,	5780	ibdev_err(&hr_dev->ib_dev,
5496	"failed to process cmd of querying SRQ, ret = %d.\n",	5781	"failed to process cmd of querying SRQ, ret = %d.\n",
@@ -5540,9 +5825,8 @@ static int hns_roce_v2_modify_cq(struct ib_cq *cq, u16 cq_count, u16 cq_period) · 43 unmodified lines
5540	hr_reg_write(cq_context, CQC_CQ_PERIOD, cq_period);	5825	hr_reg_write(cq_context, CQC_CQ_PERIOD, cq_period);
5541	hr_reg_clear(cqc_mask, CQC_CQ_PERIOD);	5826	hr_reg_clear(cqc_mask, CQC_CQ_PERIOD);
5542		5827
5543	ret = hns_roce_cmd_mbox(hr_dev, mailbox->dma, 0, hr_cq->cqn, 1,	5828	ret = hns_roce_cmd_mbox(hr_dev, mailbox->dma, 0,
5544	HNS_ROCE_CMD_MODIFY_CQC,	5829	HNS_ROCE_CMD_MODIFY_CQC, hr_cq->cqn);
5545	HNS_ROCE_CMD_TIMEOUT_MSECS);
5546	hns_roce_free_cmd_mailbox(hr_dev, mailbox);	5830	hns_roce_free_cmd_mailbox(hr_dev, mailbox);
5547	if (ret)	5831	if (ret)
5548	ibdev_err(&hr_dev->ib_dev,	5832	ibdev_err(&hr_dev->ib_dev,
@@ -5869,15 +6153,14 @@ static void hns_roce_v2_destroy_eqc(struct hns_roce_dev *hr_dev, u32 eqn) · 320 unmodified lines
5869	{	6153	{
5870	struct device *dev = hr_dev->dev;	6154	struct device *dev = hr_dev->dev;
5871	int ret;	6155	int ret;
		6156	u8 cmd;
5872		6157
5873	if (eqn < hr_dev->caps.num_comp_vectors)	6158	if (eqn < hr_dev->caps.num_comp_vectors)
5874	ret = hns_roce_cmd_mbox(hr_dev, 0, 0, eqn & HNS_ROCE_V2_EQN_M,	6159	cmd = HNS_ROCE_CMD_DESTROY_CEQC;
5875	0, HNS_ROCE_CMD_DESTROY_CEQC,
5876	HNS_ROCE_CMD_TIMEOUT_MSECS);
5877	else	6160	else
5878	ret = hns_roce_cmd_mbox(hr_dev, 0, 0, eqn & HNS_ROCE_V2_EQN_M,	6161	cmd = HNS_ROCE_CMD_DESTROY_AEQC;
5879	0, HNS_ROCE_CMD_DESTROY_AEQC,	6162
5880	HNS_ROCE_CMD_TIMEOUT_MSECS);	6163	ret = hns_roce_destroy_hw_ctx(hr_dev, cmd, eqn & HNS_ROCE_V2_EQN_M);
5881	if (ret)	6164	if (ret)
5882	dev_err(dev, "[mailbox cmd] destroy eqc(%u) failed.\n", eqn);	6165	dev_err(dev, "[mailbox cmd] destroy eqc(%u) failed.\n", eqn);
5883	}	6166	}
@@ -5983,16 +6266,15 @@ static int alloc_eq_buf(struct hns_roce_dev hr_dev, struct hns_roce_eq eq) · 99 unmodified lines
5983	}	6266	}
5984		6267
5985	static int hns_roce_v2_create_eq(struct hns_roce_dev *hr_dev,	6268	static int hns_roce_v2_create_eq(struct hns_roce_dev *hr_dev,
5986	struct hns_roce_eq *eq,	6269	struct hns_roce_eq *eq, u8 eq_cmd)
5987	unsigned int eq_cmd)
5988	{	6270	{
5989	struct hns_roce_cmd_mailbox *mailbox;	6271	struct hns_roce_cmd_mailbox *mailbox;
5990	int ret;	6272	int ret;
5991		6273
5992	/* Allocate mailbox memory */	6274	/* Allocate mailbox memory */
5993	mailbox = hns_roce_alloc_cmd_mailbox(hr_dev);	6275	mailbox = hns_roce_alloc_cmd_mailbox(hr_dev);
5994	if (IS_ERR_OR_NULL(mailbox))	6276	if (IS_ERR(mailbox))
5995	return -ENOMEM;	6277	return PTR_ERR(mailbox);
5996		6278
5997	ret = alloc_eq_buf(hr_dev, eq);	6279	ret = alloc_eq_buf(hr_dev, eq);
5998	if (ret)	6280	if (ret)
@@ -6002,8 +6284,7 @@ static int hns_roce_v2_create_eq(struct hns_roce_dev *hr_dev, · 3 unmodified lines
6002	if (ret)	6284	if (ret)
6003	goto err_cmd_mbox;	6285	goto err_cmd_mbox;
6004		6286
6005	ret = hns_roce_cmd_mbox(hr_dev, mailbox->dma, 0, eq->eqn, 0,	6287	ret = hns_roce_create_hw_ctx(hr_dev, mailbox, eq_cmd, eq->eqn);
6006	eq_cmd, HNS_ROCE_CMD_TIMEOUT_MSECS);
6007	if (ret) {	6288	if (ret) {
6008	dev_err(hr_dev->dev, "[mailbox cmd] create eqc failed.\n");	6289	dev_err(hr_dev->dev, "[mailbox cmd] create eqc failed.\n");
6009	goto err_cmd_mbox;	6290	goto err_cmd_mbox;
@@ -6114,14 +6395,14 @@ static int hns_roce_v2_init_eq_table(struct hns_roce_dev *hr_dev) · 104 unmodified lines
6114	struct hns_roce_eq_table *eq_table = &hr_dev->eq_table;	6395	struct hns_roce_eq_table *eq_table = &hr_dev->eq_table;
6115	struct device *dev = hr_dev->dev;	6396	struct device *dev = hr_dev->dev;
6116	struct hns_roce_eq *eq;	6397	struct hns_roce_eq *eq;
6117	unsigned int eq_cmd;
6118	int irq_num;
6119	int eq_num;
6120	int other_num;	6398	int other_num;
6121	int comp_num;	6399	int comp_num;
6122	int aeq_num;	6400	int aeq_num;
6123	int i;	6401	int irq_num;
		6402	int eq_num;
		6403	u8 eq_cmd;
6124	int ret;	6404	int ret;
		6405	int i;
6125		6406
6126	other_num = hr_dev->caps.num_other_vectors;	6407	other_num = hr_dev->caps.num_other_vectors;
6127	comp_num = hr_dev->caps.num_comp_vectors;	6408	comp_num = hr_dev->caps.num_comp_vectors;
@@ -6258,6 +6539,7 @@ static const struct hns_roce_hw hns_roce_hw_v2 = { · 130 unmodified lines
6258	.set_hem = hns_roce_v2_set_hem,	6539	.set_hem = hns_roce_v2_set_hem,
6259	.clear_hem = hns_roce_v2_clear_hem,	6540	.clear_hem = hns_roce_v2_clear_hem,
6260	.modify_qp = hns_roce_v2_modify_qp,	6541	.modify_qp = hns_roce_v2_modify_qp,
		6542	.dereg_mr = hns_roce_v2_dereg_mr,
6261	.qp_flow_control_init = hns_roce_v2_qp_flow_control_init,	6543	.qp_flow_control_init = hns_roce_v2_qp_flow_control_init,
6262	.init_eq = hns_roce_v2_init_eq_table,	6544	.init_eq = hns_roce_v2_init_eq_table,
6263	.cleanup_eq = hns_roce_v2_cleanup_eq_table,	6545	.cleanup_eq = hns_roce_v2_cleanup_eq_table,
@@ -6339,14 +6621,25 @@ static int __hns_roce_hw_v2_init_instance(struct hnae3_handle *handle) · 75 unmodified lines
6339	ret = hns_roce_init(hr_dev);	6621	ret = hns_roce_init(hr_dev);
6340	if (ret) {	6622	if (ret) {
6341	dev_err(hr_dev->dev, "RoCE Engine init failed!\n");	6623	dev_err(hr_dev->dev, "RoCE Engine init failed!\n");
6342	goto error_failed_get_cfg;	6624	goto error_failed_cfg;
		6625	}
		6626
		6627	if (hr_dev->pci_dev->revision == PCI_REVISION_ID_HIP08) {
		6628	ret = free_mr_init(hr_dev);
		6629	if (ret) {
		6630	dev_err(hr_dev->dev, "failed to init free mr!\n");
		6631	goto error_failed_roce_init;
		6632	}
6343	}	6633	}
6344		6634
6345	handle->priv = hr_dev;	6635	handle->priv = hr_dev;
6346		6636
6347	return 0;	6637	return 0;
6348		6638
6349	error_failed_get_cfg:	6639	error_failed_roce_init:
		6640	hns_roce_exit(hr_dev);
		6641
		6642	error_failed_cfg:
6350	kfree(hr_dev->priv);	6643	kfree(hr_dev->priv);
6351		6644
6352	error_failed_kzalloc:	6645	error_failed_kzalloc:
@@ -6368,6 +6661,9 @@ static void __hns_roce_hw_v2_uninit_instance(struct hnae3_handle *handle, · 15 unmodified lines
6368	hr_dev->state = HNS_ROCE_DEVICE_STATE_UNINIT;	6661	hr_dev->state = HNS_ROCE_DEVICE_STATE_UNINIT;
6369	hns_roce_handle_device_err(hr_dev);	6662	hns_roce_handle_device_err(hr_dev);
6370		6663
		6664	if (hr_dev->pci_dev->revision == PCI_REVISION_ID_HIP08)
		6665	free_mr_exit(hr_dev);
		6666
6371	hns_roce_exit(hr_dev);	6667	hns_roce_exit(hr_dev);
6372	kfree(hr_dev->priv);	6668	kfree(hr_dev->priv);
6373	ib_dealloc_device(&hr_dev->ib_dev);	6669	ib_dealloc_device(&hr_dev->ib_dev);

drivers/infiniband/hw/hns/hns_roce_hw_v2.h+20−0

@@ -139,6 +139,18 @@ enum { · 138 unmodified lines
139	#define CMD_CSQ_DESC_NUM 1024	139	#define CMD_CSQ_DESC_NUM 1024
140	#define CMD_CRQ_DESC_NUM 1024	140	#define CMD_CRQ_DESC_NUM 1024
141		141
		142	/* Free mr used parameters */
		143	#define HNS_ROCE_FREE_MR_USED_CQE_NUM 128
		144	#define HNS_ROCE_FREE_MR_USED_QP_NUM 0x8
		145	#define HNS_ROCE_FREE_MR_USED_PSN 0x0808
		146	#define HNS_ROCE_FREE_MR_USED_QP_RETRY_CNT 0x7
		147	#define HNS_ROCE_FREE_MR_USED_QP_TIMEOUT 0x12
		148	#define HNS_ROCE_FREE_MR_USED_SQWQE_NUM 128
		149	#define HNS_ROCE_FREE_MR_USED_SQSGE_NUM 0x2
		150	#define HNS_ROCE_FREE_MR_USED_RQWQE_NUM 128
		151	#define HNS_ROCE_FREE_MR_USED_RQSGE_NUM 0x2
		152	#define HNS_ROCE_V2_FREE_MR_TIMEOUT 4500
		153
142	enum {	154	enum {
143	NO_ARMED = 0x0,	155	NO_ARMED = 0x0,
144	REG_NXT_CEQE = 0x2,	156	REG_NXT_CEQE = 0x2,
@@ -1418,10 +1430,18 @@ struct hns_roce_link_table { · 1273 unmodified lines
1418	#define HNS_ROCE_EXT_LLM_ENTRY(addr, id) (((id) << (64 - 12)) \| ((addr) >> 12))	1430	#define HNS_ROCE_EXT_LLM_ENTRY(addr, id) (((id) << (64 - 12)) \| ((addr) >> 12))
1419	#define HNS_ROCE_EXT_LLM_MIN_PAGES(que_num) ((que_num) * 4 + 2)	1431	#define HNS_ROCE_EXT_LLM_MIN_PAGES(que_num) ((que_num) * 4 + 2)
1420		1432
		1433	struct hns_roce_v2_free_mr {
		1434	struct ib_qp *rsv_qp[HNS_ROCE_FREE_MR_USED_QP_NUM];
		1435	struct ib_cq *rsv_cq;
		1436	struct ib_pd *rsv_pd;
		1437	struct mutex mutex;
		1438	};
		1439
1421	struct hns_roce_v2_priv {	1440	struct hns_roce_v2_priv {
1422	struct hnae3_handle *handle;	1441	struct hnae3_handle *handle;
1423	struct hns_roce_v2_cmq cmq;	1442	struct hns_roce_v2_cmq cmq;
1424	struct hns_roce_link_table ext_llm;	1443	struct hns_roce_link_table ext_llm;
		1444	struct hns_roce_v2_free_mr free_mr;
1425	};	1445	};
1426		1446
1427	struct hns_roce_dip {	1447	struct hns_roce_dip {

drivers/infiniband/hw/hns/hns_roce_hw_v2_dfx.c+2−3

 		return PTR_ERR(mailbox);
 	cq_context = mailbox->buf;
-	ret = hns_roce_cmd_mbox(hr_dev, 0, mailbox->dma, cqn, 0,
+	ret = hns_roce_cmd_mbox(hr_dev, 0, mailbox->dma, HNS_ROCE_CMD_QUERY_CQC,
-				HNS_ROCE_CMD_QUERY_CQC,
+				cqn);
-				HNS_ROCE_CMD_TIMEOUT_MSECS);
 	if (ret) {
 		dev_err(hr_dev->dev, "QUERY cqc cmd process error\n");
 		goto err_mailbox;

drivers/infiniband/hw/hns/hns_roce_mr.c+17−33

@@ -47,24 +47,6 @@ unsigned long key_to_hw_index(u32 key) · 46 unmodified lines
47	return (key << 24) \| (key >> 8);	47	return (key << 24) \| (key >> 8);
48	}	48	}
49		49
50	static int hns_roce_hw_create_mpt(struct hns_roce_dev *hr_dev,
51	struct hns_roce_cmd_mailbox *mailbox,
52	unsigned long mpt_index)
53	{
54	return hns_roce_cmd_mbox(hr_dev, mailbox->dma, 0, mpt_index, 0,
55	HNS_ROCE_CMD_CREATE_MPT,
56	HNS_ROCE_CMD_TIMEOUT_MSECS);
57	}
58
59	int hns_roce_hw_destroy_mpt(struct hns_roce_dev *hr_dev,
60	struct hns_roce_cmd_mailbox *mailbox,
61	unsigned long mpt_index)
62	{
63	return hns_roce_cmd_mbox(hr_dev, 0, mailbox ? mailbox->dma : 0,
64	mpt_index, !mailbox, HNS_ROCE_CMD_DESTROY_MPT,
65	HNS_ROCE_CMD_TIMEOUT_MSECS);
66	}
67
68	static int alloc_mr_key(struct hns_roce_dev hr_dev, struct hns_roce_mr mr)	50	static int alloc_mr_key(struct hns_roce_dev hr_dev, struct hns_roce_mr mr)
69	{	51	{
70	struct hns_roce_ida *mtpt_ida = &hr_dev->mr_table.mtpt_ida;	52	struct hns_roce_ida *mtpt_ida = &hr_dev->mr_table.mtpt_ida;
@@ -137,14 +119,13 @@ static void free_mr_pbl(struct hns_roce_dev hr_dev, struct hns_roce_mr mr) · 66 unmodified lines
137	hns_roce_mtr_destroy(hr_dev, &mr->pbl_mtr);	119	hns_roce_mtr_destroy(hr_dev, &mr->pbl_mtr);
138	}	120	}
139		121
140	static void hns_roce_mr_free(struct hns_roce_dev *hr_dev,	122	static void hns_roce_mr_free(struct hns_roce_dev hr_dev, struct hns_roce_mr mr)
141	struct hns_roce_mr *mr)
142	{	123	{
143	struct ib_device *ibdev = &hr_dev->ib_dev;	124	struct ib_device *ibdev = &hr_dev->ib_dev;
144	int ret;	125	int ret;
145		126
146	if (mr->enabled) {	127	if (mr->enabled) {
147	ret = hns_roce_hw_destroy_mpt(hr_dev, NULL,	128	ret = hns_roce_destroy_hw_ctx(hr_dev, HNS_ROCE_CMD_DESTROY_MPT,
148	key_to_hw_index(mr->key) &	129	key_to_hw_index(mr->key) &
149	(hr_dev->caps.num_mtpts - 1));	130	(hr_dev->caps.num_mtpts - 1));
150	if (ret)	131	if (ret)
@@ -166,10 +147,8 @@ static int hns_roce_mr_enable(struct hns_roce_dev *hr_dev, · 15 unmodified lines
166		147
167	/* Allocate mailbox memory */	148	/* Allocate mailbox memory */
168	mailbox = hns_roce_alloc_cmd_mailbox(hr_dev);	149	mailbox = hns_roce_alloc_cmd_mailbox(hr_dev);
169	if (IS_ERR(mailbox)) {	150	if (IS_ERR(mailbox))
170	ret = PTR_ERR(mailbox);	151	return PTR_ERR(mailbox);
171	return ret;
172	}
173		152
174	if (mr->type != MR_TYPE_FRMR)	153	if (mr->type != MR_TYPE_FRMR)
175	ret = hr_dev->hw->write_mtpt(hr_dev, mailbox->buf, mr);	154	ret = hr_dev->hw->write_mtpt(hr_dev, mailbox->buf, mr);
@@ -180,7 +159,7 @@ static int hns_roce_mr_enable(struct hns_roce_dev *hr_dev, · 4 unmodified lines
180	goto err_page;	159	goto err_page;
181	}	160	}
182		161
183	ret = hns_roce_hw_create_mpt(hr_dev, mailbox,	162	ret = hns_roce_create_hw_ctx(hr_dev, mailbox, HNS_ROCE_CMD_CREATE_MPT,
184	mtpt_idx & (hr_dev->caps.num_mtpts - 1));	163	mtpt_idx & (hr_dev->caps.num_mtpts - 1));
185	if (ret) {	164	if (ret) {
186	dev_err(dev, "failed to create mpt, ret = %d.\n", ret);	165	dev_err(dev, "failed to create mpt, ret = %d.\n", ret);
@@ -303,13 +282,14 @@ struct ib_mr hns_roce_rereg_user_mr(struct ib_mr ibmr, int flags, u64 start, · 116 unmodified lines
303	return ERR_CAST(mailbox);	282	return ERR_CAST(mailbox);
304		283
305	mtpt_idx = key_to_hw_index(mr->key) & (hr_dev->caps.num_mtpts - 1);	284	mtpt_idx = key_to_hw_index(mr->key) & (hr_dev->caps.num_mtpts - 1);
306	ret = hns_roce_cmd_mbox(hr_dev, 0, mailbox->dma, mtpt_idx, 0,	285
307	HNS_ROCE_CMD_QUERY_MPT,	286	ret = hns_roce_cmd_mbox(hr_dev, 0, mailbox->dma, HNS_ROCE_CMD_QUERY_MPT,
308	HNS_ROCE_CMD_TIMEOUT_MSECS);	287	mtpt_idx);
309	if (ret)	288	if (ret)
310	goto free_cmd_mbox;	289	goto free_cmd_mbox;
311		290
312	ret = hns_roce_hw_destroy_mpt(hr_dev, NULL, mtpt_idx);	291	ret = hns_roce_destroy_hw_ctx(hr_dev, HNS_ROCE_CMD_DESTROY_MPT,
		292	mtpt_idx);
313	if (ret)	293	if (ret)
314	ibdev_warn(ib_dev, "failed to destroy MPT, ret = %d.\n", ret);	294	ibdev_warn(ib_dev, "failed to destroy MPT, ret = %d.\n", ret);
315		295
@@ -339,7 +319,8 @@ struct ib_mr hns_roce_rereg_user_mr(struct ib_mr ibmr, int flags, u64 start, · 23 unmodified lines
339	goto free_cmd_mbox;	319	goto free_cmd_mbox;
340	}	320	}
341		321
342	ret = hns_roce_hw_create_mpt(hr_dev, mailbox, mtpt_idx);	322	ret = hns_roce_create_hw_ctx(hr_dev, mailbox, HNS_ROCE_CMD_CREATE_MPT,
		323	mtpt_idx);
343	if (ret) {	324	if (ret) {
344	ibdev_err(ib_dev, "failed to create MPT, ret = %d.\n", ret);	325	ibdev_err(ib_dev, "failed to create MPT, ret = %d.\n", ret);
345	goto free_cmd_mbox;	326	goto free_cmd_mbox;
@@ -361,6 +342,9 @@ int hns_roce_dereg_mr(struct ib_mr ibmr, struct ib_udata udata) · 15 unmodified lines
361	struct hns_roce_mr *mr = to_hr_mr(ibmr);	342	struct hns_roce_mr *mr = to_hr_mr(ibmr);
362	int ret = 0;	343	int ret = 0;
363		344
		345	if (hr_dev->hw->dereg_mr)
		346	hr_dev->hw->dereg_mr(hr_dev);
		347
364	hns_roce_mr_free(hr_dev, mr);	348	hns_roce_mr_free(hr_dev, mr);
365	kfree(mr);	349	kfree(mr);
366		350
@@ -480,7 +464,7 @@ static void hns_roce_mw_free(struct hns_roce_dev *hr_dev, · 113 unmodified lines
480	int ret;	464	int ret;
481		465
482	if (mw->enabled) {	466	if (mw->enabled) {
483	ret = hns_roce_hw_destroy_mpt(hr_dev, NULL,	467	ret = hns_roce_destroy_hw_ctx(hr_dev, HNS_ROCE_CMD_DESTROY_MPT,
484	key_to_hw_index(mw->rkey) &	468	key_to_hw_index(mw->rkey) &
485	(hr_dev->caps.num_mtpts - 1));	469	(hr_dev->caps.num_mtpts - 1));
486	if (ret)	470	if (ret)
@@ -520,7 +504,7 @@ static int hns_roce_mw_enable(struct hns_roce_dev *hr_dev, · 33 unmodified lines
520	goto err_page;	504	goto err_page;
521	}	505	}
522		506
523	ret = hns_roce_hw_create_mpt(hr_dev, mailbox,	507	ret = hns_roce_create_hw_ctx(hr_dev, mailbox, HNS_ROCE_CMD_CREATE_MPT,
524	mtpt_idx & (hr_dev->caps.num_mtpts - 1));	508	mtpt_idx & (hr_dev->caps.num_mtpts - 1));
525	if (ret) {	509	if (ret) {
526	dev_err(dev, "MW CREATE_MPT failed (%d)\n", ret);	510	dev_err(dev, "MW CREATE_MPT failed (%d)\n", ret);

drivers/infiniband/hw/hns/hns_roce_srq.c+57−49

@@ -59,58 +59,39 @@ static void hns_roce_ib_srq_event(struct hns_roce_srq *srq, · 58 unmodified lines
59	}	59	}
60	}	60	}
61		61
62	static int hns_roce_hw_create_srq(struct hns_roce_dev *dev,	62	static int alloc_srqn(struct hns_roce_dev hr_dev, struct hns_roce_srq srq)
63	struct hns_roce_cmd_mailbox *mailbox,
64	unsigned long srq_num)
65	{	63	{
66	return hns_roce_cmd_mbox(dev, mailbox->dma, 0, srq_num, 0,
67	HNS_ROCE_CMD_CREATE_SRQ,
68	HNS_ROCE_CMD_TIMEOUT_MSECS);
69	}
70
71	static int hns_roce_hw_destroy_srq(struct hns_roce_dev *dev,
72	struct hns_roce_cmd_mailbox *mailbox,
73	unsigned long srq_num)
74	{
75	return hns_roce_cmd_mbox(dev, 0, mailbox ? mailbox->dma : 0, srq_num,
76	mailbox ? 0 : 1, HNS_ROCE_CMD_DESTROY_SRQ,
77	HNS_ROCE_CMD_TIMEOUT_MSECS);
78	}
79
80	static int alloc_srqc(struct hns_roce_dev hr_dev, struct hns_roce_srq srq)
81	{
82	struct hns_roce_srq_table *srq_table = &hr_dev->srq_table;
83	struct hns_roce_ida *srq_ida = &hr_dev->srq_table.srq_ida;	64	struct hns_roce_ida *srq_ida = &hr_dev->srq_table.srq_ida;
84	struct ib_device *ibdev = &hr_dev->ib_dev;
85	struct hns_roce_cmd_mailbox *mailbox;
86	int ret;
87	int id;	65	int id;
88		66
89	id = ida_alloc_range(&srq_ida->ida, srq_ida->min, srq_ida->max,	67	id = ida_alloc_range(&srq_ida->ida, srq_ida->min, srq_ida->max,
90	GFP_KERNEL);	68	GFP_KERNEL);
91	if (id < 0) {	69	if (id < 0) {
92	ibdev_err(ibdev, "failed to alloc srq(%d).\n", id);	70	ibdev_err(&hr_dev->ib_dev, "failed to alloc srq(%d).\n", id);
93	return -ENOMEM;	71	return -ENOMEM;
94	}	72	}
95	srq->srqn = (unsigned long)id;
96		73
97	ret = hns_roce_table_get(hr_dev, &srq_table->table, srq->srqn);	74	srq->srqn = id;
98	if (ret) {
99	ibdev_err(ibdev, "failed to get SRQC table, ret = %d.\n", ret);
100	goto err_out;
101	}
102		75
103	ret = xa_err(xa_store(&srq_table->xa, srq->srqn, srq, GFP_KERNEL));	76	return 0;
104	if (ret) {	77	}
105	ibdev_err(ibdev, "failed to store SRQC, ret = %d.\n", ret);	78
106	goto err_put;	79	static void free_srqn(struct hns_roce_dev hr_dev, struct hns_roce_srq srq)
107	}	80	{
		81	ida_free(&hr_dev->srq_table.srq_ida.ida, (int)srq->srqn);
		82	}
		83
		84	static int hns_roce_create_srqc(struct hns_roce_dev *hr_dev,
		85	struct hns_roce_srq *srq)
		86	{
		87	struct ib_device *ibdev = &hr_dev->ib_dev;
		88	struct hns_roce_cmd_mailbox *mailbox;
		89	int ret;
108		90
109	mailbox = hns_roce_alloc_cmd_mailbox(hr_dev);	91	mailbox = hns_roce_alloc_cmd_mailbox(hr_dev);
110	if (IS_ERR_OR_NULL(mailbox)) {	92	if (IS_ERR(mailbox)) {
111	ibdev_err(ibdev, "failed to alloc mailbox for SRQC.\n");	93	ibdev_err(ibdev, "failed to alloc mailbox for SRQC.\n");
112	ret = -ENOMEM;	94	return PTR_ERR(mailbox);
113	goto err_xa;
114	}	95	}
115		96
116	ret = hr_dev->hw->write_srqc(srq, mailbox->buf);	97	ret = hr_dev->hw->write_srqc(srq, mailbox->buf);
@@ -119,24 +100,44 @@ static int alloc_srqc(struct hns_roce_dev hr_dev, struct hns_roce_srq srq) · 2 unmodified lines
119	goto err_mbox;	100	goto err_mbox;
120	}	101	}
121		102
122	ret = hns_roce_hw_create_srq(hr_dev, mailbox, srq->srqn);	103	ret = hns_roce_create_hw_ctx(hr_dev, mailbox, HNS_ROCE_CMD_CREATE_SRQ,
123	if (ret) {	104	srq->srqn);
		105	if (ret)
124	ibdev_err(ibdev, "failed to config SRQC, ret = %d.\n", ret);	106	ibdev_err(ibdev, "failed to config SRQC, ret = %d.\n", ret);
125	goto err_mbox;
126	}
127		107
		108	err_mbox:
128	hns_roce_free_cmd_mailbox(hr_dev, mailbox);	109	hns_roce_free_cmd_mailbox(hr_dev, mailbox);
		110	return ret;
		111	}
		112
		113	static int alloc_srqc(struct hns_roce_dev hr_dev, struct hns_roce_srq srq)
		114	{
		115	struct hns_roce_srq_table *srq_table = &hr_dev->srq_table;
		116	struct ib_device *ibdev = &hr_dev->ib_dev;
		117	int ret;
		118
		119	ret = hns_roce_table_get(hr_dev, &srq_table->table, srq->srqn);
		120	if (ret) {
		121	ibdev_err(ibdev, "failed to get SRQC table, ret = %d.\n", ret);
		122	return ret;
		123	}
		124
		125	ret = xa_err(xa_store(&srq_table->xa, srq->srqn, srq, GFP_KERNEL));
		126	if (ret) {
		127	ibdev_err(ibdev, "failed to store SRQC, ret = %d.\n", ret);
		128	goto err_put;
		129	}
		130
		131	ret = hns_roce_create_srqc(hr_dev, srq);
		132	if (ret)
		133	goto err_xa;
129		134
130	return 0;	135	return 0;
131		136
132	err_mbox:
133	hns_roce_free_cmd_mailbox(hr_dev, mailbox);
134	err_xa:	137	err_xa:
135	xa_erase(&srq_table->xa, srq->srqn);	138	xa_erase(&srq_table->xa, srq->srqn);
136	err_put:	139	err_put:
137	hns_roce_table_put(hr_dev, &srq_table->table, srq->srqn);	140	hns_roce_table_put(hr_dev, &srq_table->table, srq->srqn);
138	err_out:
139	ida_free(&srq_ida->ida, id);
140		141
141	return ret;	142	return ret;
142	}	143	}
@@ -146,7 +147,8 @@ static void free_srqc(struct hns_roce_dev hr_dev, struct hns_roce_srq srq) · 3 unmodified lines
146	struct hns_roce_srq_table *srq_table = &hr_dev->srq_table;	147	struct hns_roce_srq_table *srq_table = &hr_dev->srq_table;
147	int ret;	148	int ret;
148		149
149	ret = hns_roce_hw_destroy_srq(hr_dev, NULL, srq->srqn);	150	ret = hns_roce_destroy_hw_ctx(hr_dev, HNS_ROCE_CMD_DESTROY_SRQ,
		151	srq->srqn);
150	if (ret)	152	if (ret)
151	dev_err(hr_dev->dev, "DESTROY_SRQ failed (%d) for SRQN %06lx\n",	153	dev_err(hr_dev->dev, "DESTROY_SRQ failed (%d) for SRQN %06lx\n",
152	ret, srq->srqn);	154	ret, srq->srqn);
@@ -158,7 +160,6 @@ static void free_srqc(struct hns_roce_dev hr_dev, struct hns_roce_srq srq) · 5 unmodified lines
158	wait_for_completion(&srq->free);	160	wait_for_completion(&srq->free);
159		161
160	hns_roce_table_put(hr_dev, &srq_table->table, srq->srqn);	162	hns_roce_table_put(hr_dev, &srq_table->table, srq->srqn);
161	ida_free(&srq_table->srq_ida.ida, (int)srq->srqn);
162	}	163	}
163		164
164	static int alloc_srq_idx(struct hns_roce_dev hr_dev, struct hns_roce_srq srq,	165	static int alloc_srq_idx(struct hns_roce_dev hr_dev, struct hns_roce_srq srq,
@@ -406,10 +407,14 @@ int hns_roce_create_srq(struct ib_srq *ib_srq, · 241 unmodified lines
406	if (ret)	407	if (ret)
407	return ret;	408	return ret;
408		409
409	ret = alloc_srqc(hr_dev, srq);	410	ret = alloc_srqn(hr_dev, srq);
410	if (ret)	411	if (ret)
411	goto err_srq_buf;	412	goto err_srq_buf;
412		413
		414	ret = alloc_srqc(hr_dev, srq);
		415	if (ret)
		416	goto err_srqn;
		417
413	if (udata) {	418	if (udata) {
414	resp.srqn = srq->srqn;	419	resp.srqn = srq->srqn;
415	if (ib_copy_to_udata(udata, &resp,	420	if (ib_copy_to_udata(udata, &resp,
@@ -428,6 +433,8 @@ int hns_roce_create_srq(struct ib_srq *ib_srq, · 12 unmodified lines
428		433
429	err_srqc:	434	err_srqc:
430	free_srqc(hr_dev, srq);	435	free_srqc(hr_dev, srq);
		436	err_srqn:
		437	free_srqn(hr_dev, srq);
431	err_srq_buf:	438	err_srq_buf:
432	free_srq_buf(hr_dev, srq);	439	free_srq_buf(hr_dev, srq);
433		440
@@ -440,6 +447,7 @@ int hns_roce_destroy_srq(struct ib_srq ibsrq, struct ib_udata udata) · 6 unmodified lines
440	struct hns_roce_srq *srq = to_hr_srq(ibsrq);	447	struct hns_roce_srq *srq = to_hr_srq(ibsrq);
441		448
442	free_srqc(hr_dev, srq);	449	free_srqc(hr_dev, srq);
		450	free_srqn(hr_dev, srq);
443	free_srq_buf(hr_dev, srq);	451	free_srq_buf(hr_dev, srq);
444	return 0;	452	return 0;
445	}	453	}

drivers/infiniband/hw/irdma/cm.c+39−29

  * @cm_info: CM info for parent listen node
  * @cm_parent_listen_node: The parent listen node
  */
-static enum irdma_status_code
+static int irdma_del_multiple_qhash(struct irdma_device *iwdev,
-irdma_del_multiple_qhash(struct irdma_device *iwdev,
+				    struct irdma_cm_info *cm_info,
-			 struct irdma_cm_info *cm_info,
+				    struct irdma_cm_listener *cm_parent_listen_node)
-			 struct irdma_cm_listener *cm_parent_listen_node)
 {
 	struct irdma_cm_listener *child_listen_node;
-	enum irdma_status_code ret = IRDMA_ERR_CFG;
 	struct list_head *pos, *tpos;
 	unsigned long flags;
+	int ret = -EINVAL;
 	spin_lock_irqsave(&iwdev->cm_core.listen_list_lock, flags);
 	list_for_each_safe (pos, tpos,
  * Adds a qhash and a child listen node for every IPv6 address
  * on the adapter and adds the associated qhash filter
  */
-static enum irdma_status_code
+static int irdma_add_mqh_6(struct irdma_device *iwdev,
-irdma_add_mqh_6(struct irdma_device *iwdev, struct irdma_cm_info *cm_info,
+			   struct irdma_cm_info *cm_info,
-		struct irdma_cm_listener *cm_parent_listen_node)
+			   struct irdma_cm_listener *cm_parent_listen_node)
 {
 	struct net_device *ip_dev;
 	struct inet6_dev *idev;
 	struct inet6_ifaddr *ifp, *tmp;
-	enum irdma_status_code ret = 0;
 	struct irdma_cm_listener *child_listen_node;
 	unsigned long flags;
+	int ret = 0;
 	rtnl_lock();
 	for_each_netdev(&init_net, ip_dev) {
 				  child_listen_node);
 			if (!child_listen_node) {
 				ibdev_dbg(&iwdev->ibdev, "CM: listener memory allocation\n");
-				ret = IRDMA_ERR_NO_MEMORY;
+				ret = -ENOMEM;
 				goto exit;
 			}
  * Adds a qhash and a child listen node for every IPv4 address
  * on the adapter and adds the associated qhash filter
  */
-static enum irdma_status_code
+static int irdma_add_mqh_4(struct irdma_device *iwdev,
-irdma_add_mqh_4(struct irdma_device *iwdev, struct irdma_cm_info *cm_info,
+			   struct irdma_cm_info *cm_info,
-		struct irdma_cm_listener *cm_parent_listen_node)
+			   struct irdma_cm_listener *cm_parent_listen_node)
 {
 	struct net_device *ip_dev;
 	struct in_device *idev;
 	struct irdma_cm_listener *child_listen_node;
-	enum irdma_status_code ret = 0;
 	unsigned long flags;
 	const struct in_ifaddr *ifa;
+	int ret = 0;
 	rtnl_lock();
 	for_each_netdev(&init_net, ip_dev) {
 			if (!child_listen_node) {
 				ibdev_dbg(&iwdev->ibdev, "CM: listener memory allocation\n");
 				in_dev_put(idev);
-				ret = IRDMA_ERR_NO_MEMORY;
+				ret = -ENOMEM;
 				goto exit;
 			}
  * @cm_info: CM info for parent listen node
  * @cm_listen_node: The parent listen node
  */
-static enum irdma_status_code
+static int irdma_add_mqh(struct irdma_device *iwdev,
-irdma_add_mqh(struct irdma_device *iwdev, struct irdma_cm_info *cm_info,
+			 struct irdma_cm_info *cm_info,
-	      struct irdma_cm_listener *cm_listen_node)
+			 struct irdma_cm_listener *cm_listen_node)
 {
 	if (cm_info->ipv4)
 		return irdma_add_mqh_4(iwdev, cm_info, cm_listen_node);
 	/* set our node specific transport info */
 	cm_node->ipv4 = cm_info->ipv4;
 	cm_node->vlan_id = cm_info->vlan_id;
-	if (cm_node->vlan_id >= VLAN_N_VID && iwdev->dcb)
+	if (cm_node->vlan_id >= VLAN_N_VID && iwdev->dcb_vlan_mode)
 		cm_node->vlan_id = 0;
 	cm_node->tos = cm_info->tos;
 	cm_node->user_pri = cm_info->user_pri;
 			ibdev_warn(&iwdev->ibdev,
 				   "application TOS[%d] and remote client TOS[%d] mismatch\n",
 				   listener->tos, cm_info->tos);
-		cm_node->tos = max(listener->tos, cm_info->tos);
+		if (iwdev->vsi.dscp_mode) {
-		cm_node->user_pri = rt_tos2priority(cm_node->tos);
+			cm_node->user_pri = listener->user_pri;
+		} else {
+			cm_node->tos = max(listener->tos, cm_info->tos);
+			cm_node->user_pri = rt_tos2priority(cm_node->tos);
+		}
 		ibdev_dbg(&iwdev->ibdev,
 			  "DCB: listener: TOS:[%d] UP:[%d]\n", cm_node->tos,
 			  cm_node->user_pri);
  * @iwdev: iwarp device structure
  * @rdma_ver: HW version
  */
-enum irdma_status_code irdma_setup_cm_core(struct irdma_device *iwdev,
+int irdma_setup_cm_core(struct irdma_device *iwdev, u8 rdma_ver)
-					   u8 rdma_ver)
 {
 	struct irdma_cm_core *cm_core = &iwdev->cm_core;
 	/* Handles CM event work items send to Iwarp core */
 	cm_core->event_wq = alloc_ordered_workqueue("iwarp-event-wq", 0);
 	if (!cm_core->event_wq)
-		return IRDMA_ERR_NO_MEMORY;
+		return -ENOMEM;
 	INIT_LIST_HEAD(&cm_core->listen_list);
 	cm_info.cm_id = cm_id;
 	cm_info.qh_qpid = iwdev->vsi.ilq->qp_id;
 	cm_info.tos = cm_id->tos;
-	cm_info.user_pri = rt_tos2priority(cm_id->tos);
+	if (iwdev->vsi.dscp_mode)
+		cm_info.user_pri =
+			iwqp->sc_qp.vsi->dscp_map[irdma_tos2dscp(cm_info.tos)];
+	else
+		cm_info.user_pri = rt_tos2priority(cm_id->tos);
 	if (iwqp->sc_qp.dev->ws_add(iwqp->sc_qp.vsi, cm_info.user_pri))
 		return -ENOMEM;
 	struct irdma_device *iwdev;
 	struct irdma_cm_listener *cm_listen_node;
 	struct irdma_cm_info cm_info = {};
-	enum irdma_status_code err;
 	struct sockaddr_in *laddr;
 	struct sockaddr_in6 *laddr6;
 	bool wildcard = false;
+	int err;
 	iwdev = to_iwdev(cm_id->device);
 	if (!iwdev)
 		}
 	}
-	if (cm_info.vlan_id >= VLAN_N_VID && iwdev->dcb)
+	if (cm_info.vlan_id >= VLAN_N_VID && iwdev->dcb_vlan_mode)
 		cm_info.vlan_id = 0;
 	cm_info.backlog = backlog;
 	cm_info.cm_id = cm_id;
 	cm_id->provider_data = cm_listen_node;
 	cm_listen_node->tos = cm_id->tos;
-	cm_listen_node->user_pri = rt_tos2priority(cm_id->tos);
+	if (iwdev->vsi.dscp_mode)
+		cm_listen_node->user_pri =
+			iwdev->vsi.dscp_map[irdma_tos2dscp(cm_id->tos)];
+	else
+		cm_listen_node->user_pri = rt_tos2priority(cm_id->tos);
 	cm_info.user_pri = cm_listen_node->user_pri;
 	if (!cm_listen_node->reused_node) {
 		if (wildcard) {
 	struct list_head *child_listen_list = &parent_listen_node->child_listen_list;
 	struct irdma_cm_listener *child_listen_node;
 	struct list_head *pos, *tpos;
-	enum irdma_status_code err;
 	bool node_allocated = false;
 	enum irdma_quad_hash_manage_type op = ifup ?
 					      IRDMA_QHASH_MANAGE_TYPE_ADD :
 					      IRDMA_QHASH_MANAGE_TYPE_DELETE;
+	int err;
 	list_for_each_safe (pos, tpos, child_listen_list) {
 		child_listen_node = list_entry(pos, struct irdma_cm_listener,

drivers/infiniband/hw/irdma/cm.h+7−0

@@ -384,6 +384,13 @@ int irdma_schedule_cm_timer(struct irdma_cm_node *cm_node, · 383 unmodified lines
384	struct irdma_puda_buf *sqbuf,	384	struct irdma_puda_buf *sqbuf,
385	enum irdma_timer_type type, int send_retrans,	385	enum irdma_timer_type type, int send_retrans,
386	int close_when_complete);	386	int close_when_complete);
		387
		388	static inline u8 irdma_tos2dscp(u8 tos)
		389	{
		390	#define IRDMA_DSCP_VAL GENMASK(7, 2)
		391	return (u8)FIELD_GET(IRDMA_DSCP_VAL, tos);
		392	}
		393
387	int irdma_accept(struct iw_cm_id cm_id, struct iw_cm_conn_param conn_param);	394	int irdma_accept(struct iw_cm_id cm_id, struct iw_cm_conn_param conn_param);
388	int irdma_reject(struct iw_cm_id cm_id, const void pdata, u8 pdata_len);	395	int irdma_reject(struct iw_cm_id cm_id, const void pdata, u8 pdata_len);
389	int irdma_connect(struct iw_cm_id cm_id, struct iw_cm_conn_param conn_param);	396	int irdma_connect(struct iw_cm_id cm_id, struct iw_cm_conn_param conn_param);

drivers/infiniband/hw/irdma/ctrl.c+287−315

 #include <linux/etherdevice.h>
 #include "osdep.h"
-#include "status.h"
 #include "hmc.h"
 #include "defs.h"
 #include "type.h"
 	}
 }
+static void irdma_set_qos_info(struct irdma_sc_vsi  *vsi,
+			       struct irdma_l2params *l2p)
+{
+	u8 i;
+	vsi->qos_rel_bw = l2p->vsi_rel_bw;
+	vsi->qos_prio_type = l2p->vsi_prio_type;
+	vsi->dscp_mode = l2p->dscp_mode;
+	if (l2p->dscp_mode) {
+		memcpy(vsi->dscp_map, l2p->dscp_map, sizeof(vsi->dscp_map));
+		for (i = 0; i < IRDMA_MAX_USER_PRIORITY; i++)
+			l2p->up2tc[i] = i;
+	}
+	for (i = 0; i < IRDMA_MAX_USER_PRIORITY; i++) {
+		if (vsi->dev->hw_attrs.uk_attrs.hw_rev == IRDMA_GEN_1)
+			vsi->qos[i].qs_handle = l2p->qs_handle_list[i];
+		vsi->qos[i].traffic_class = l2p->up2tc[i];
+		vsi->qos[i].rel_bw =
+			l2p->tc_info[vsi->qos[i].traffic_class].rel_bw;
+		vsi->qos[i].prio_type =
+			l2p->tc_info[vsi->qos[i].traffic_class].prio_type;
+		vsi->qos[i].valid = false;
+	}
+}
 /**
  * irdma_change_l2params - given the new l2 parameters, change all qp
  * @vsi: RDMA VSI pointer
 		return;
 	vsi->tc_change_pending = false;
+	irdma_set_qos_info(vsi, l2params);
 	irdma_sc_suspend_resume_qps(vsi, IRDMA_OP_RESUME);
 }
  * @scratch: u64 saved to be used during cqp completion
  * @post_sq: flag for cqp db to ring
  */
-static enum irdma_status_code
+static int irdma_sc_add_arp_cache_entry(struct irdma_sc_cqp *cqp,
-irdma_sc_add_arp_cache_entry(struct irdma_sc_cqp *cqp,
+					struct irdma_add_arp_cache_entry_info *info,
-			     struct irdma_add_arp_cache_entry_info *info,
+					u64 scratch, bool post_sq)
-			     u64 scratch, bool post_sq)
 {
 	__le64 *wqe;
 	u64 hdr;
 	wqe = irdma_sc_cqp_get_next_send_wqe(cqp, scratch);
 	if (!wqe)
-		return IRDMA_ERR_RING_FULL;
+		return -ENOMEM;
 	set_64bit_val(wqe, 8, info->reach_max);
 	set_64bit_val(wqe, 16, ether_addr_to_u64(info->mac_addr));
  * @arp_index: arp index to delete arp entry
  * @post_sq: flag for cqp db to ring
  */
-static enum irdma_status_code
+static int irdma_sc_del_arp_cache_entry(struct irdma_sc_cqp *cqp, u64 scratch,
-irdma_sc_del_arp_cache_entry(struct irdma_sc_cqp *cqp, u64 scratch,
+					u16 arp_index, bool post_sq)
-			     u16 arp_index, bool post_sq)
 {
 	__le64 *wqe;
 	u64 hdr;
 	wqe = irdma_sc_cqp_get_next_send_wqe(cqp, scratch);
 	if (!wqe)
-		return IRDMA_ERR_RING_FULL;
+		return -ENOMEM;
 	hdr = arp_index |
 	      FIELD_PREP(IRDMA_CQPSQ_OPCODE, IRDMA_CQP_OP_MANAGE_ARP) |
  * @scratch: u64 saved to be used during cqp completion
  * @post_sq: flag for cqp db to ring
  */
-static enum irdma_status_code
+static int irdma_sc_manage_apbvt_entry(struct irdma_sc_cqp *cqp,
-irdma_sc_manage_apbvt_entry(struct irdma_sc_cqp *cqp,
+				       struct irdma_apbvt_info *info,
-			    struct irdma_apbvt_info *info, u64 scratch,
+				       u64 scratch, bool post_sq)
-			    bool post_sq)
 {
 	__le64 *wqe;
 	u64 hdr;
 	wqe = irdma_sc_cqp_get_next_send_wqe(cqp, scratch);
 	if (!wqe)
-		return IRDMA_ERR_RING_FULL;
+		return -ENOMEM;
 	set_64bit_val(wqe, 16, info->port);
  * quad hash entry in the hardware will point to iwarp's qp
  * number and requires no calls from the driver.
  */
-static enum irdma_status_code
+static int
 irdma_sc_manage_qhash_table_entry(struct irdma_sc_cqp *cqp,
 				  struct irdma_qhash_table_info *info,
 				  u64 scratch, bool post_sq)
 	wqe = irdma_sc_cqp_get_next_send_wqe(cqp, scratch);
 	if (!wqe)
-		return IRDMA_ERR_RING_FULL;
+		return -ENOMEM;
 	set_64bit_val(wqe, 0, ether_addr_to_u64(info->mac_addr));
  * @qp: sc qp
  * @info: initialization qp info
  */
-enum irdma_status_code irdma_sc_qp_init(struct irdma_sc_qp *qp,
+int irdma_sc_qp_init(struct irdma_sc_qp *qp, struct irdma_qp_init_info *info)
-					struct irdma_qp_init_info *info)
 {
-	enum irdma_status_code ret_code;
+	int ret_code;
 	u32 pble_obj_cnt;
 	u16 wqe_size;
 	    info->pd->dev->hw_attrs.uk_attrs.max_hw_wq_frags ||
 	    info->qp_uk_init_info.max_rq_frag_cnt >
 	    info->pd->dev->hw_attrs.uk_attrs.max_hw_wq_frags)
-		return IRDMA_ERR_INVALID_FRAG_COUNT;
+		return -EINVAL;
 	qp->dev = info->pd->dev;
 	qp->vsi = info->vsi;
 	if ((info->virtual_map && info->sq_pa >= pble_obj_cnt) ||
 	    (info->virtual_map && info->rq_pa >= pble_obj_cnt))
-		return IRDMA_ERR_INVALID_PBLE_INDEX;
+		return -EINVAL;
 	qp->llp_stream_handle = (void *)(-1);
 	qp->hw_sq_size = irdma_get_encoded_wqe_size(qp->qp_uk.sq_ring.size,
  * @scratch: u64 saved to be used during cqp completion
  * @post_sq: flag for cqp db to ring
  */
-enum irdma_status_code irdma_sc_qp_create(struct irdma_sc_qp *qp, struct irdma_create_qp_info *info,
+int irdma_sc_qp_create(struct irdma_sc_qp *qp, struct irdma_create_qp_info *info,
-					  u64 scratch, bool post_sq)
+		       u64 scratch, bool post_sq)
 {
 	struct irdma_sc_cqp *cqp;
 	__le64 *wqe;
 	cqp = qp->dev->cqp;
 	if (qp->qp_uk.qp_id < cqp->dev->hw_attrs.min_hw_qp_id ||
-	    qp->qp_uk.qp_id > (cqp->dev->hmc_info->hmc_obj[IRDMA_HMC_IW_QP].max_cnt - 1))
+	    qp->qp_uk.qp_id >= cqp->dev->hmc_info->hmc_obj[IRDMA_HMC_IW_QP].max_cnt)
-		return IRDMA_ERR_INVALID_QP_ID;
+		return -EINVAL;
 	wqe = irdma_sc_cqp_get_next_send_wqe(cqp, scratch);
 	if (!wqe)
-		return IRDMA_ERR_RING_FULL;
+		return -ENOMEM;
 	set_64bit_val(wqe, 16, qp->hw_host_ctx_pa);
 	set_64bit_val(wqe, 40, qp->shadow_area_pa);
  * @scratch: u64 saved to be used during cqp completion
  * @post_sq: flag for cqp db to ring
  */
-enum irdma_status_code irdma_sc_qp_modify(struct irdma_sc_qp *qp,
+int irdma_sc_qp_modify(struct irdma_sc_qp *qp, struct irdma_modify_qp_info *info,
-					  struct irdma_modify_qp_info *info,
+		       u64 scratch, bool post_sq)
-					  u64 scratch, bool post_sq)
 {
 	__le64 *wqe;
 	struct irdma_sc_cqp *cqp;
 	cqp = qp->dev->cqp;
 	wqe = irdma_sc_cqp_get_next_send_wqe(cqp, scratch);
 	if (!wqe)
-		return IRDMA_ERR_RING_FULL;
+		return -ENOMEM;
 	if (info->next_iwarp_state == IRDMA_QP_STATE_TERMINATE) {
 		if (info->dont_send_fin)
  * @ignore_mw_bnd: memory window bind flag
  * @post_sq: flag for cqp db to ring
  */
-enum irdma_status_code irdma_sc_qp_destroy(struct irdma_sc_qp *qp, u64 scratch,
+int irdma_sc_qp_destroy(struct irdma_sc_qp *qp, u64 scratch,
-					   bool remove_hash_idx, bool ignore_mw_bnd,
+			bool remove_hash_idx, bool ignore_mw_bnd, bool post_sq)
-					   bool post_sq)
 {
 	__le64 *wqe;
 	struct irdma_sc_cqp *cqp;
 	cqp = qp->dev->cqp;
 	wqe = irdma_sc_cqp_get_next_send_wqe(cqp, scratch);
 	if (!wqe)
-		return IRDMA_ERR_RING_FULL;
+		return -ENOMEM;
 	set_64bit_val(wqe, 16, qp->hw_host_ctx_pa);
 	set_64bit_val(wqe, 40, qp->shadow_area_pa);
  * @scratch: u64 saved to be used during cqp completion
  * @post_sq: flag for cqp db to ring
  */
-static enum irdma_status_code
+static int irdma_sc_alloc_local_mac_entry(struct irdma_sc_cqp *cqp, u64 scratch,
-irdma_sc_alloc_local_mac_entry(struct irdma_sc_cqp *cqp, u64 scratch,
+					  bool post_sq)
-			       bool post_sq)
 {
 	__le64 *wqe;
 	u64 hdr;
 	wqe = irdma_sc_cqp_get_next_send_wqe(cqp, scratch);
 	if (!wqe)
-		return IRDMA_ERR_RING_FULL;
+		return -ENOMEM;
 	hdr = FIELD_PREP(IRDMA_CQPSQ_OPCODE,
 			 IRDMA_CQP_OP_ALLOCATE_LOC_MAC_TABLE_ENTRY) |
  * @scratch: u64 saved to be used during cqp completion
  * @post_sq: flag for cqp db to ring
  */
-static enum irdma_status_code
+static int irdma_sc_add_local_mac_entry(struct irdma_sc_cqp *cqp,
-irdma_sc_add_local_mac_entry(struct irdma_sc_cqp *cqp,
+					struct irdma_local_mac_entry_info *info,
-			     struct irdma_local_mac_entry_info *info,
+					u64 scratch, bool post_sq)
-			     u64 scratch, bool post_sq)
 {
 	__le64 *wqe;
 	u64 header;
 	wqe = irdma_sc_cqp_get_next_send_wqe(cqp, scratch);
 	if (!wqe)
-		return IRDMA_ERR_RING_FULL;
+		return -ENOMEM;
 	set_64bit_val(wqe, 32, ether_addr_to_u64(info->mac_addr));
  * @ignore_ref_count: to force mac adde delete
  * @post_sq: flag for cqp db to ring
  */
-static enum irdma_status_code
+static int irdma_sc_del_local_mac_entry(struct irdma_sc_cqp *cqp, u64 scratch,
-irdma_sc_del_local_mac_entry(struct irdma_sc_cqp *cqp, u64 scratch,
+					u16 entry_idx, u8 ignore_ref_count,
-			     u16 entry_idx, u8 ignore_ref_count, bool post_sq)
+					bool post_sq)
 {
 	__le64 *wqe;
 	u64 header;
 	wqe = irdma_sc_cqp_get_next_send_wqe(cqp, scratch);
 	if (!wqe)
-		return IRDMA_ERR_RING_FULL;
+		return -ENOMEM;
 	header = FIELD_PREP(IRDMA_CQPSQ_MLM_TABLEIDX, entry_idx) |
 		 FIELD_PREP(IRDMA_CQPSQ_OPCODE,
 			    IRDMA_CQP_OP_MANAGE_LOC_MAC_TABLE) |
  * @scratch: u64 saved to be used during cqp completion
  * @post_sq: flag for cqp db to ring
  */
-static enum irdma_status_code
+static int irdma_sc_alloc_stag(struct irdma_sc_dev *dev,
-irdma_sc_alloc_stag(struct irdma_sc_dev *dev,
+			       struct irdma_allocate_stag_info *info,
-		    struct irdma_allocate_stag_info *info, u64 scratch,
+			       u64 scratch, bool post_sq)
-		    bool post_sq)
 {
 	__le64 *wqe;
 	struct irdma_sc_cqp *cqp;
 	cqp = dev->cqp;
 	wqe = irdma_sc_cqp_get_next_send_wqe(cqp, scratch);
 	if (!wqe)
-		return IRDMA_ERR_RING_FULL;
+		return -ENOMEM;
 	set_64bit_val(wqe, 8,
 		      FLD_LS_64(dev, info->pd_id, IRDMA_CQPSQ_STAG_PDID) |
  * @scratch: u64 saved to be used during cqp completion
  * @post_sq: flag for cqp db to ring
  */
-static enum irdma_status_code
+static int irdma_sc_mr_reg_non_shared(struct irdma_sc_dev *dev,
-irdma_sc_mr_reg_non_shared(struct irdma_sc_dev *dev,
+				      struct irdma_reg_ns_stag_info *info,
-			   struct irdma_reg_ns_stag_info *info, u64 scratch,
+				      u64 scratch, bool post_sq)
-			   bool post_sq)
 {
 	__le64 *wqe;
 	u64 fbo;
 	else if (info->page_size == 0x1000)
 		page_size = IRDMA_PAGE_SIZE_4K;
 	else
-		return IRDMA_ERR_PARAM;
+		return -EINVAL;
 	if (info->access_rights & (IRDMA_ACCESS_FLAGS_REMOTEREAD_ONLY |
 				   IRDMA_ACCESS_FLAGS_REMOTEWRITE_ONLY))
 	pble_obj_cnt = dev->hmc_info->hmc_obj[IRDMA_HMC_IW_PBLE].cnt;
 	if (info->chunk_size && info->first_pm_pbl_index >= pble_obj_cnt)
-		return IRDMA_ERR_INVALID_PBLE_INDEX;
+		return -EINVAL;
 	cqp = dev->cqp;
 	wqe = irdma_sc_cqp_get_next_send_wqe(cqp, scratch);
 	if (!wqe)
-		return IRDMA_ERR_RING_FULL;
+		return -ENOMEM;
 	fbo = info->va & (info->page_size - 1);
 	set_64bit_val(wqe, 0,
  * @scratch: u64 saved to be used during cqp completion
  * @post_sq: flag for cqp db to ring
  */
-static enum irdma_status_code
+static int irdma_sc_dealloc_stag(struct irdma_sc_dev *dev,
-irdma_sc_dealloc_stag(struct irdma_sc_dev *dev,
+				 struct irdma_dealloc_stag_info *info,
-		      struct irdma_dealloc_stag_info *info, u64 scratch,
+				 u64 scratch, bool post_sq)
-		      bool post_sq)
 {
 	u64 hdr;
 	__le64 *wqe;
 	cqp = dev->cqp;
 	wqe = irdma_sc_cqp_get_next_send_wqe(cqp, scratch);
 	if (!wqe)
-		return IRDMA_ERR_RING_FULL;
+		return -ENOMEM;
 	set_64bit_val(wqe, 8,
 		      FLD_LS_64(dev, info->pd_id, IRDMA_CQPSQ_STAG_PDID));
  * @scratch: u64 saved to be used during cqp completion
  * @post_sq: flag for cqp db to ring
  */
-static enum irdma_status_code
+static int irdma_sc_mw_alloc(struct irdma_sc_dev *dev,
-irdma_sc_mw_alloc(struct irdma_sc_dev *dev, struct irdma_mw_alloc_info *info,
+			     struct irdma_mw_alloc_info *info, u64 scratch,
-		  u64 scratch, bool post_sq)
+			     bool post_sq)
 {
 	u64 hdr;
 	struct irdma_sc_cqp *cqp;
 	cqp = dev->cqp;
 	wqe = irdma_sc_cqp_get_next_send_wqe(cqp, scratch);
 	if (!wqe)
-		return IRDMA_ERR_RING_FULL;
+		return -ENOMEM;
 	set_64bit_val(wqe, 8,
 		      FLD_LS_64(dev, info->pd_id, IRDMA_CQPSQ_STAG_PDID));
  * @info: fast mr info
  * @post_sq: flag for cqp db to ring
  */
-enum irdma_status_code
+int irdma_sc_mr_fast_register(struct irdma_sc_qp *qp,
-irdma_sc_mr_fast_register(struct irdma_sc_qp *qp,
+			      struct irdma_fast_reg_stag_info *info,
-			  struct irdma_fast_reg_stag_info *info, bool post_sq)
+			      bool post_sq)
 {
 	u64 temp, hdr;
 	__le64 *wqe;
 	wqe = irdma_qp_get_next_send_wqe(&qp->qp_uk, &wqe_idx,
 					 IRDMA_QP_WQE_MIN_QUANTA, 0, &sq_info);
 	if (!wqe)
-		return IRDMA_ERR_QP_TOOMANY_WRS_POSTED;
+		return -ENOMEM;
 	irdma_clr_wqes(&qp->qp_uk, wqe_idx);
 	}
 }
-static enum irdma_status_code irdma_null_ws_add(struct irdma_sc_vsi *vsi,
+static int irdma_null_ws_add(struct irdma_sc_vsi *vsi, u8 user_pri)
-						u8 user_pri)
 {
 	return 0;
 }
 void irdma_sc_vsi_init(struct irdma_sc_vsi  *vsi,
 		       struct irdma_vsi_init_info *info)
 {
-	struct irdma_l2params *l2p;
 	int i;
 	vsi->dev = info->dev;
 	if (vsi->dev->hw_attrs.uk_attrs.hw_rev == IRDMA_GEN_1)
 		vsi->fcn_id = info->dev->hmc_fn_id;
-	l2p = info->params;
+	irdma_set_qos_info(vsi, info->params);
-	vsi->qos_rel_bw = l2p->vsi_rel_bw;
-	vsi->qos_prio_type = l2p->vsi_prio_type;
 	for (i = 0; i < IRDMA_MAX_USER_PRIORITY; i++) {
-		if (vsi->dev->hw_attrs.uk_attrs.hw_rev == IRDMA_GEN_1)
-			vsi->qos[i].qs_handle = l2p->qs_handle_list[i];
-		vsi->qos[i].traffic_class = info->params->up2tc[i];
-		vsi->qos[i].rel_bw =
-			l2p->tc_info[vsi->qos[i].traffic_class].rel_bw;
-		vsi->qos[i].prio_type =
-			l2p->tc_info[vsi->qos[i].traffic_class].prio_type;
-		vsi->qos[i].valid = false;
 		mutex_init(&vsi->qos[i].qos_mutex);
 		INIT_LIST_HEAD(&vsi->qos[i].qplist);
 	}
  * @vsi: pointer to the vsi structure
  * @info: The info structure used for initialization
  */
-enum irdma_status_code irdma_vsi_stats_init(struct irdma_sc_vsi *vsi,
+int irdma_vsi_stats_init(struct irdma_sc_vsi *vsi,
-					    struct irdma_vsi_stats_info *info)
+			 struct irdma_vsi_stats_info *info)
 {
 	u8 fcn_id = info->fcn_id;
 	struct irdma_dma_mem *stats_buff_mem;
 						&stats_buff_mem->pa,
 						GFP_KERNEL);
 	if (!stats_buff_mem->va)
-		return IRDMA_ERR_NO_MEMORY;
+		return -ENOMEM;
 	vsi->pestat->gather_info.gather_stats_va = stats_buff_mem->va;
 	vsi->pestat->gather_info.last_gather_stats_va =
 			  stats_buff_mem->va, stats_buff_mem->pa);
 	stats_buff_mem->va = NULL;
-	return IRDMA_ERR_CQP_COMPL_ERROR;
+	return -EIO;
 }
 /**
  * @info: gather stats info structure
  * @scratch: u64 saved to be used during cqp completion
  */
-static enum irdma_status_code
+static int irdma_sc_gather_stats(struct irdma_sc_cqp *cqp,
-irdma_sc_gather_stats(struct irdma_sc_cqp *cqp,
+				 struct irdma_stats_gather_info *info,
-		      struct irdma_stats_gather_info *info, u64 scratch)
+				 u64 scratch)
 {
 	__le64 *wqe;
 	u64 temp;
 	if (info->stats_buff_mem.size < IRDMA_GATHER_STATS_BUF_SIZE)
-		return IRDMA_ERR_BUF_TOO_SHORT;
+		return -ENOMEM;
 	wqe = irdma_sc_cqp_get_next_send_wqe(cqp, scratch);
 	if (!wqe)
-		return IRDMA_ERR_RING_FULL;
+		return -ENOMEM;
 	set_64bit_val(wqe, 40,
 		      FIELD_PREP(IRDMA_CQPSQ_STATS_HMC_FCN_INDEX, info->hmc_fcn_index));
  * @alloc: alloc vs. delete flag
  * @scratch: u64 saved to be used during cqp completion
  */
-static enum irdma_status_code
+static int irdma_sc_manage_stats_inst(struct irdma_sc_cqp *cqp,
-irdma_sc_manage_stats_inst(struct irdma_sc_cqp *cqp,
+				      struct irdma_stats_inst_info *info,
-			   struct irdma_stats_inst_info *info, bool alloc,
+				      bool alloc, u64 scratch)
-			   u64 scratch)
 {
 	__le64 *wqe;
 	u64 temp;
 	wqe = irdma_sc_cqp_get_next_send_wqe(cqp, scratch);
 	if (!wqe)
-		return IRDMA_ERR_RING_FULL;
+		return -ENOMEM;
 	set_64bit_val(wqe, 40,
 		      FIELD_PREP(IRDMA_CQPSQ_STATS_HMC_FCN_INDEX, info->hmc_fn_id));
  * @info: User priority map info
  * @scratch: u64 saved to be used during cqp completion
  */
-static enum irdma_status_code irdma_sc_set_up_map(struct irdma_sc_cqp *cqp,
+static int irdma_sc_set_up_map(struct irdma_sc_cqp *cqp,
-						  struct irdma_up_info *info,
+			       struct irdma_up_info *info, u64 scratch)
-						  u64 scratch)
 {
 	__le64 *wqe;
 	u64 temp = 0;
 	wqe = irdma_sc_cqp_get_next_send_wqe(cqp, scratch);
 	if (!wqe)
-		return IRDMA_ERR_RING_FULL;
+		return -ENOMEM;
 	for (i = 0; i < IRDMA_MAX_USER_PRIORITY; i++)
 		temp |= (u64)info->map[i] << (i * 8);
  * @node_op: 0 for add 1 for modify, 2 for delete
  * @scratch: u64 saved to be used during cqp completion
  */
-static enum irdma_status_code
+static int irdma_sc_manage_ws_node(struct irdma_sc_cqp *cqp,
-irdma_sc_manage_ws_node(struct irdma_sc_cqp *cqp,
+				   struct irdma_ws_node_info *info,
-			struct irdma_ws_node_info *info,
+				   enum irdma_ws_node_op node_op, u64 scratch)
-			enum irdma_ws_node_op node_op, u64 scratch)
 {
 	__le64 *wqe;
 	u64 temp = 0;
 	wqe = irdma_sc_cqp_get_next_send_wqe(cqp, scratch);
 	if (!wqe)
-		return IRDMA_ERR_RING_FULL;
+		return -ENOMEM;
 	set_64bit_val(wqe, 32,
 		      FIELD_PREP(IRDMA_CQPSQ_WS_VSI, info->vsi) |
  * @scratch: u64 saved to be used during cqp completion
  * @post_sq: flag for cqp db to ring
  */
-enum irdma_status_code irdma_sc_qp_flush_wqes(struct irdma_sc_qp *qp,
+int irdma_sc_qp_flush_wqes(struct irdma_sc_qp *qp,
-					      struct irdma_qp_flush_info *info,
+			   struct irdma_qp_flush_info *info, u64 scratch,
-					      u64 scratch, bool post_sq)
+			   bool post_sq)
 {
 	u64 temp = 0;
 	__le64 *wqe;
 		ibdev_dbg(to_ibdev(qp->dev),
 			  "CQP: Additional flush request ignored for qp %x\n",
 			  qp->qp_uk.qp_id);
-		return IRDMA_ERR_FLUSHED_Q;
+		return -EALREADY;
 	}
 	cqp = qp->pd->dev->cqp;
 	wqe = irdma_sc_cqp_get_next_send_wqe(cqp, scratch);
 	if (!wqe)
-		return IRDMA_ERR_RING_FULL;
+		return -ENOMEM;
 	if (info->userflushcode) {
 		if (flush_rq)
  * @scratch: u64 saved to be used during cqp completion
  * @post_sq: flag for cqp db to ring
  */
-static enum irdma_status_code irdma_sc_gen_ae(struct irdma_sc_qp *qp,
+static int irdma_sc_gen_ae(struct irdma_sc_qp *qp,
-					      struct irdma_gen_ae_info *info,
+			   struct irdma_gen_ae_info *info, u64 scratch,
-					      u64 scratch, bool post_sq)
+			   bool post_sq)
 {
 	u64 temp;
 	__le64 *wqe;
 	cqp = qp->pd->dev->cqp;
 	wqe = irdma_sc_cqp_get_next_send_wqe(cqp, scratch);
 	if (!wqe)
-		return IRDMA_ERR_RING_FULL;
+		return -ENOMEM;
 	temp = info->ae_code | FIELD_PREP(IRDMA_CQPSQ_FWQE_AESOURCE,
 					  info->ae_src);
  * @scratch: u64 saved to be used during cqp completion
  * @post_sq: flag for cqp db to ring
  */
-static enum irdma_status_code
+static int irdma_sc_qp_upload_context(struct irdma_sc_dev *dev,
-irdma_sc_qp_upload_context(struct irdma_sc_dev *dev,
+				      struct irdma_upload_context_info *info,
-			   struct irdma_upload_context_info *info, u64 scratch,
+				      u64 scratch, bool post_sq)
-			   bool post_sq)
 {
 	__le64 *wqe;
 	struct irdma_sc_cqp *cqp;
 	cqp = dev->cqp;
 	wqe = irdma_sc_cqp_get_next_send_wqe(cqp, scratch);
 	if (!wqe)
-		return IRDMA_ERR_RING_FULL;
+		return -ENOMEM;
 	set_64bit_val(wqe, 16, info->buf_pa);
  * @scratch: u64 saved to be used during cqp completion
  * @post_sq: flag for cqp db to ring
  */
-static enum irdma_status_code
+static int irdma_sc_manage_push_page(struct irdma_sc_cqp *cqp,
-irdma_sc_manage_push_page(struct irdma_sc_cqp *cqp,
+				     struct irdma_cqp_manage_push_page_info *info,
-			  struct irdma_cqp_manage_push_page_info *info,
+				     u64 scratch, bool post_sq)
-			  u64 scratch, bool post_sq)
 {
 	__le64 *wqe;
 	u64 hdr;
 	if (info->free_page &&
 	    info->push_idx >= cqp->dev->hw_attrs.max_hw_device_pages)
-		return IRDMA_ERR_INVALID_PUSH_PAGE_INDEX;
+		return -EINVAL;
 	wqe = irdma_sc_cqp_get_next_send_wqe(cqp, scratch);
 	if (!wqe)
-		return IRDMA_ERR_RING_FULL;
+		return -ENOMEM;
 	set_64bit_val(wqe, 16, info->qs_handle);
 	hdr = FIELD_PREP(IRDMA_CQPSQ_MPP_PPIDX, info->push_idx) |
  * @qp: sc qp struct
  * @scratch: u64 saved to be used during cqp completion
  */
-static enum irdma_status_code irdma_sc_suspend_qp(struct irdma_sc_cqp *cqp,
+static int irdma_sc_suspend_qp(struct irdma_sc_cqp *cqp, struct irdma_sc_qp *qp,
-						  struct irdma_sc_qp *qp,
+			       u64 scratch)
-						  u64 scratch)
 {
 	u64 hdr;
 	__le64 *wqe;
 	wqe = irdma_sc_cqp_get_next_send_wqe(cqp, scratch);
 	if (!wqe)
-		return IRDMA_ERR_RING_FULL;
+		return -ENOMEM;
 	hdr = FIELD_PREP(IRDMA_CQPSQ_SUSPENDQP_QPID, qp->qp_uk.qp_id) |
 	      FIELD_PREP(IRDMA_CQPSQ_OPCODE, IRDMA_CQP_OP_SUSPEND_QP) |
  * @qp: sc qp struct
  * @scratch: u64 saved to be used during cqp completion
  */
-static enum irdma_status_code irdma_sc_resume_qp(struct irdma_sc_cqp *cqp,
+static int irdma_sc_resume_qp(struct irdma_sc_cqp *cqp, struct irdma_sc_qp *qp,
-						 struct irdma_sc_qp *qp,
+			      u64 scratch)
-						 u64 scratch)
 {
 	u64 hdr;
 	__le64 *wqe;
 	wqe = irdma_sc_cqp_get_next_send_wqe(cqp, scratch);
 	if (!wqe)
-		return IRDMA_ERR_RING_FULL;
+		return -ENOMEM;
 	set_64bit_val(wqe, 16,
 		      FIELD_PREP(IRDMA_CQPSQ_RESUMEQP_QSHANDLE, qp->qs_handle));
  * @cq: cq struct
  * @info: cq initialization info
  */
-enum irdma_status_code irdma_sc_cq_init(struct irdma_sc_cq *cq,
+int irdma_sc_cq_init(struct irdma_sc_cq *cq, struct irdma_cq_init_info *info)
-					struct irdma_cq_init_info *info)
 {
 	u32 pble_obj_cnt;
 	pble_obj_cnt = info->dev->hmc_info->hmc_obj[IRDMA_HMC_IW_PBLE].cnt;
 	if (info->virtual_map && info->first_pm_pbl_idx >= pble_obj_cnt)
-		return IRDMA_ERR_INVALID_PBLE_INDEX;
+		return -EINVAL;
 	cq->cq_pa = info->cq_base_pa;
 	cq->dev = info->dev;
  * @check_overflow: flag for overflow check
  * @post_sq: flag for cqp db to ring
  */
-static enum irdma_status_code irdma_sc_cq_create(struct irdma_sc_cq *cq,
+static int irdma_sc_cq_create(struct irdma_sc_cq *cq, u64 scratch,
-						 u64 scratch,
+			      bool check_overflow, bool post_sq)
-						 bool check_overflow,
-						 bool post_sq)
 {
 	__le64 *wqe;
 	struct irdma_sc_cqp *cqp;
 	u64 hdr;
 	struct irdma_sc_ceq *ceq;
-	enum irdma_status_code ret_code = 0;
+	int ret_code = 0;
 	cqp = cq->dev->cqp;
-	if (cq->cq_uk.cq_id > (cqp->dev->hmc_info->hmc_obj[IRDMA_HMC_IW_CQ].max_cnt - 1))
+	if (cq->cq_uk.cq_id >= cqp->dev->hmc_info->hmc_obj[IRDMA_HMC_IW_CQ].max_cnt)
-		return IRDMA_ERR_INVALID_CQ_ID;
+		return -EINVAL;
-	if (cq->ceq_id > (cq->dev->hmc_fpm_misc.max_ceqs - 1))
+	if (cq->ceq_id >= cq->dev->hmc_fpm_misc.max_ceqs)
-		return IRDMA_ERR_INVALID_CEQ_ID;
+		return -EINVAL;
 	ceq = cq->dev->ceq[cq->ceq_id];
 	if (ceq && ceq->reg_cq)
 	if (!wqe) {
 		if (ceq && ceq->reg_cq)
 			irdma_sc_remove_cq_ctx(ceq, cq);
-		return IRDMA_ERR_RING_FULL;
+		return -ENOMEM;
 	}
 	set_64bit_val(wqe, 0, cq->cq_uk.cq_size);
  * @scratch: u64 saved to be used during cqp completion
  * @post_sq: flag for cqp db to ring
  */
-enum irdma_status_code irdma_sc_cq_destroy(struct irdma_sc_cq *cq, u64 scratch,
+int irdma_sc_cq_destroy(struct irdma_sc_cq *cq, u64 scratch, bool post_sq)
-					   bool post_sq)
 {
 	struct irdma_sc_cqp *cqp;
 	__le64 *wqe;
 	cqp = cq->dev->cqp;
 	wqe = irdma_sc_cqp_get_next_send_wqe(cqp, scratch);
 	if (!wqe)
-		return IRDMA_ERR_RING_FULL;
+		return -ENOMEM;
 	ceq = cq->dev->ceq[cq->ceq_id];
 	if (ceq && ceq->reg_cq)
  * @scratch: u64 saved to be used during cqp completion
  * @post_sq: flag to post to sq
  */
-static enum irdma_status_code
+static int irdma_sc_cq_modify(struct irdma_sc_cq *cq,
-irdma_sc_cq_modify(struct irdma_sc_cq *cq, struct irdma_modify_cq_info *info,
+			      struct irdma_modify_cq_info *info, u64 scratch,
-		   u64 scratch, bool post_sq)
+			      bool post_sq)
 {
 	struct irdma_sc_cqp *cqp;
 	__le64 *wqe;
 	pble_obj_cnt = cq->dev->hmc_info->hmc_obj[IRDMA_HMC_IW_PBLE].cnt;
 	if (info->cq_resize && info->virtual_map &&
 	    info->first_pm_pbl_idx >= pble_obj_cnt)
-		return IRDMA_ERR_INVALID_PBLE_INDEX;
+		return -EINVAL;
 	cqp = cq->dev->cqp;
 	wqe = irdma_sc_cqp_get_next_send_wqe(cqp, scratch);
 	if (!wqe)
-		return IRDMA_ERR_RING_FULL;
+		return -ENOMEM;
 	set_64bit_val(wqe, 0, info->cq_size);
 	set_64bit_val(wqe, 8, (uintptr_t)cq >> 1);
  * @tail: wqtail register value
  * @count: how many times to try for completion
  */
-static enum irdma_status_code irdma_cqp_poll_registers(struct irdma_sc_cqp *cqp,
+static int irdma_cqp_poll_registers(struct irdma_sc_cqp *cqp, u32 tail,
-						       u32 tail, u32 count)
+				    u32 count)
 {
 	u32 i = 0;
 	u32 newtail, error, val;
 			ibdev_dbg(to_ibdev(cqp->dev),
 				  "CQP: CQPERRCODES error_code[x%08X]\n",
 				  error);
-			return IRDMA_ERR_CQP_COMPL_ERROR;
+			return -EIO;
 		}
 		if (newtail != tail) {
 			/* SUCCESS */
 		udelay(cqp->dev->hw_attrs.max_sleep_count);
 	}
-	return IRDMA_ERR_TIMEOUT;
+	return -ETIMEDOUT;
 }
 /**
  * parses fpm query buffer and copy max_cnt and
  * size value of hmc objects in hmc_info
  */
-static enum irdma_status_code
+static int irdma_sc_parse_fpm_query_buf(struct irdma_sc_dev *dev, __le64 *buf,
-irdma_sc_parse_fpm_query_buf(struct irdma_sc_dev *dev, __le64 *buf,
+					struct irdma_hmc_info *hmc_info,
-			     struct irdma_hmc_info *hmc_info,
+					struct irdma_hmc_fpm_misc *hmc_fpm_misc)
-			     struct irdma_hmc_fpm_misc *hmc_fpm_misc)
 {
 	struct irdma_hmc_obj_info *obj_info;
 	u64 temp;
 	obj_info[IRDMA_HMC_IW_XFFL].size = 4;
 	hmc_fpm_misc->xf_block_size = FIELD_GET(IRDMA_QUERY_FPM_XFBLOCKSIZE, temp);
 	if (!hmc_fpm_misc->xf_block_size)
-		return IRDMA_ERR_INVALID_SIZE;
+		return -EINVAL;
 	irdma_sc_decode_fpm_query(buf, 72, obj_info, IRDMA_HMC_IW_Q1);
 	get_64bit_val(buf, 80, &temp);
 	hmc_fpm_misc->q1_block_size = FIELD_GET(IRDMA_QUERY_FPM_Q1BLOCKSIZE, temp);
 	if (!hmc_fpm_misc->q1_block_size)
-		return IRDMA_ERR_INVALID_SIZE;
+		return -EINVAL;
 	irdma_sc_decode_fpm_query(buf, 88, obj_info, IRDMA_HMC_IW_TIMER);
 	hmc_fpm_misc->rrf_block_size = FIELD_GET(IRDMA_QUERY_FPM_RRFBLOCKSIZE, temp);
 	if (!hmc_fpm_misc->rrf_block_size &&
 	    obj_info[IRDMA_HMC_IW_RRFFL].max_cnt)
-		return IRDMA_ERR_INVALID_SIZE;
+		return -EINVAL;
 	irdma_sc_decode_fpm_query(buf, 144, obj_info, IRDMA_HMC_IW_HDR);
 	irdma_sc_decode_fpm_query(buf, 152, obj_info, IRDMA_HMC_IW_MD);
 	hmc_fpm_misc->ooiscf_block_size = FIELD_GET(IRDMA_QUERY_FPM_OOISCFBLOCKSIZE, temp);
 	if (!hmc_fpm_misc->ooiscf_block_size &&
 	    obj_info[IRDMA_HMC_IW_OOISCFFL].max_cnt)
-		return IRDMA_ERR_INVALID_SIZE;
+		return -EINVAL;
 	return 0;
 }
  * @ceq: ceq sc structure
  * @cq: cq sc structure
  */
-enum irdma_status_code irdma_sc_add_cq_ctx(struct irdma_sc_ceq *ceq,
+int irdma_sc_add_cq_ctx(struct irdma_sc_ceq *ceq, struct irdma_sc_cq *cq)
-					   struct irdma_sc_cq *cq)
 {
 	unsigned long flags;
 	if (ceq->reg_cq_size == ceq->elem_cnt) {
 		spin_unlock_irqrestore(&ceq->req_cq_lock, flags);
-		return IRDMA_ERR_REG_CQ_FULL;
+		return -ENOMEM;
 	}
 	ceq->reg_cq[ceq->reg_cq_size++] = cq;
  *
  * Initializes the object and context buffers for a control Queue Pair.
  */
-enum irdma_status_code irdma_sc_cqp_init(struct irdma_sc_cqp *cqp,
+int irdma_sc_cqp_init(struct irdma_sc_cqp *cqp,
-					 struct irdma_cqp_init_info *info)
+		      struct irdma_cqp_init_info *info)
 {
 	u8 hw_sq_size;
 	if (info->sq_size > IRDMA_CQP_SW_SQSIZE_2048 ||
 	    info->sq_size < IRDMA_CQP_SW_SQSIZE_4 ||
 	    ((info->sq_size & (info->sq_size - 1))))
-		return IRDMA_ERR_INVALID_SIZE;
+		return -EINVAL;
 	hw_sq_size = irdma_get_encoded_wqe_size(info->sq_size,
 						IRDMA_QUEUE_TYPE_CQP);
  * @maj_err: If error, major err number
  * @min_err: If error, minor err number
  */
-enum irdma_status_code irdma_sc_cqp_create(struct irdma_sc_cqp *cqp, u16 *maj_err,
+int irdma_sc_cqp_create(struct irdma_sc_cqp *cqp, u16 *maj_err, u16 *min_err)
-					   u16 *min_err)
 {
 	u64 temp;
 	u8 hw_rev;
 	u32 cnt = 0, p1, p2, val = 0, err_code;
-	enum irdma_status_code ret_code;
+	int ret_code;
 	hw_rev = cqp->dev->hw_attrs.uk_attrs.hw_rev;
 	cqp->sdbuf.size = ALIGN(IRDMA_UPDATE_SD_BUFF_SIZE * cqp->sq_size,
 					   cqp->sdbuf.size, &cqp->sdbuf.pa,
 					   GFP_KERNEL);
 	if (!cqp->sdbuf.va)
-		return IRDMA_ERR_NO_MEMORY;
+		return -ENOMEM;
 	spin_lock_init(&cqp->dev->cqp_lock);
 	do {
 		if (cnt++ > cqp->dev->hw_attrs.max_done_count) {
-			ret_code = IRDMA_ERR_TIMEOUT;
+			ret_code = -ETIMEDOUT;
 			goto err;
 		}
 		udelay(cqp->dev->hw_attrs.max_sleep_count);
 	} while (!val);
 	if (FLD_RS_32(cqp->dev, val, IRDMA_CCQPSTATUS_CCQP_ERR)) {
-		ret_code = IRDMA_ERR_DEVICE_NOT_SUPPORTED;
+		ret_code = -EOPNOTSUPP;
 		goto err;
 	}
 					   u32 *wqe_idx)
 {
 	__le64 *wqe = NULL;
-	enum irdma_status_code ret_code;
+	int ret_code;
 	if (IRDMA_RING_FULL_ERR(cqp->sq_ring)) {
 		ibdev_dbg(to_ibdev(cqp->dev),
  * irdma_sc_cqp_destroy - destroy cqp during close
  * @cqp: struct for cqp hw
  */
-enum irdma_status_code irdma_sc_cqp_destroy(struct irdma_sc_cqp *cqp)
+int irdma_sc_cqp_destroy(struct irdma_sc_cqp *cqp)
 {
 	u32 cnt = 0, val;
-	enum irdma_status_code ret_code = 0;
+	int ret_code = 0;
 	writel(0, cqp->dev->hw_regs[IRDMA_CCQPHIGH]);
 	writel(0, cqp->dev->hw_regs[IRDMA_CCQPLOW]);
 	do {
 		if (cnt++ > cqp->dev->hw_attrs.max_done_count) {
-			ret_code = IRDMA_ERR_TIMEOUT;
+			ret_code = -ETIMEDOUT;
 			break;
 		}
 		udelay(cqp->dev->hw_attrs.max_sleep_count);
  * @ccq: ccq sc struct
  * @info: completion q entry to return
  */
-enum irdma_status_code irdma_sc_ccq_get_cqe_info(struct irdma_sc_cq *ccq,
+int irdma_sc_ccq_get_cqe_info(struct irdma_sc_cq *ccq,
-						 struct irdma_ccq_cqe_info *info)
+			      struct irdma_ccq_cqe_info *info)
 {
 	u64 qp_ctx, temp, temp1;
 	__le64 *cqe;
 	u32 wqe_idx;
 	u32 error;
 	u8 polarity;
-	enum irdma_status_code ret_code = 0;
+	int ret_code = 0;
 	if (ccq->cq_uk.avoid_mem_cflct)
 		cqe = IRDMA_GET_CURRENT_EXTENDED_CQ_ELEM(&ccq->cq_uk);
 	get_64bit_val(cqe, 24, &temp);
 	polarity = (u8)FIELD_GET(IRDMA_CQ_VALID, temp);
 	if (polarity != ccq->cq_uk.polarity)
-		return IRDMA_ERR_Q_EMPTY;
+		return -ENOENT;
 	get_64bit_val(cqe, 8, &qp_ctx);
 	cqp = (struct irdma_sc_cqp *)(unsigned long)qp_ctx;
  * @op_code: cqp opcode for completion
  * @compl_info: completion q entry to return
  */
-enum irdma_status_code irdma_sc_poll_for_cqp_op_done(struct irdma_sc_cqp *cqp, u8 op_code,
+int irdma_sc_poll_for_cqp_op_done(struct irdma_sc_cqp *cqp, u8 op_code,
-						     struct irdma_ccq_cqe_info *compl_info)
+				  struct irdma_ccq_cqe_info *compl_info)
 {
 	struct irdma_ccq_cqe_info info = {};
 	struct irdma_sc_cq *ccq;
-	enum irdma_status_code ret_code = 0;
+	int ret_code = 0;
 	u32 cnt = 0;
 	ccq = cqp->dev->ccq;
 	while (1) {
 		if (cnt++ > 100 * cqp->dev->hw_attrs.max_done_count)
-			return IRDMA_ERR_TIMEOUT;
+			return -ETIMEDOUT;
 		if (irdma_sc_ccq_get_cqe_info(ccq, &info)) {
 			udelay(cqp->dev->hw_attrs.max_sleep_count);
 			continue;
 		}
 		if (info.error && info.op_code != IRDMA_CQP_OP_QUERY_STAG) {
-			ret_code = IRDMA_ERR_CQP_COMPL_ERROR;
+			ret_code = -EIO;
 			break;
 		}
 		/* make sure op code matches*/
  * @info: info for the manage function table operation
  * @post_sq: flag for cqp db to ring
  */
-static enum irdma_status_code
+static int irdma_sc_manage_hmc_pm_func_table(struct irdma_sc_cqp *cqp,
-irdma_sc_manage_hmc_pm_func_table(struct irdma_sc_cqp *cqp,
+					     struct irdma_hmc_fcn_info *info,
-				  struct irdma_hmc_fcn_info *info,
+					     u64 scratch, bool post_sq)
-				  u64 scratch, bool post_sq)
 {
 	__le64 *wqe;
 	u64 hdr;
 	wqe = irdma_sc_cqp_get_next_send_wqe(cqp, scratch);
 	if (!wqe)
-		return IRDMA_ERR_RING_FULL;
+		return -ENOMEM;
 	set_64bit_val(wqe, 0, 0);
 	set_64bit_val(wqe, 8, 0);
  * for fpm commit
  * @cqp: struct for cqp hw
  */
-static enum irdma_status_code
+static int irdma_sc_commit_fpm_val_done(struct irdma_sc_cqp *cqp)
-irdma_sc_commit_fpm_val_done(struct irdma_sc_cqp *cqp)
 {
 	return irdma_sc_poll_for_cqp_op_done(cqp, IRDMA_CQP_OP_COMMIT_FPM_VAL,
 					     NULL);
  * @post_sq: flag for cqp db to ring
  * @wait_type: poll ccq or cqp registers for cqp completion
  */
-static enum irdma_status_code
+static int irdma_sc_commit_fpm_val(struct irdma_sc_cqp *cqp, u64 scratch,
-irdma_sc_commit_fpm_val(struct irdma_sc_cqp *cqp, u64 scratch, u8 hmc_fn_id,
+				   u8 hmc_fn_id,
-			struct irdma_dma_mem *commit_fpm_mem, bool post_sq,
+				   struct irdma_dma_mem *commit_fpm_mem,
-			u8 wait_type)
+				   bool post_sq, u8 wait_type)
 {
 	__le64 *wqe;
 	u64 hdr;
 	u32 tail, val, error;
-	enum irdma_status_code ret_code = 0;
+	int ret_code = 0;
 	wqe = irdma_sc_cqp_get_next_send_wqe(cqp, scratch);
 	if (!wqe)
-		return IRDMA_ERR_RING_FULL;
+		return -ENOMEM;
 	set_64bit_val(wqe, 16, hmc_fn_id);
 	set_64bit_val(wqe, 32, commit_fpm_mem->pa);
  * query fpm
  * @cqp: struct for cqp hw
  */
-static enum irdma_status_code
+static int irdma_sc_query_fpm_val_done(struct irdma_sc_cqp *cqp)
-irdma_sc_query_fpm_val_done(struct irdma_sc_cqp *cqp)
 {
 	return irdma_sc_poll_for_cqp_op_done(cqp, IRDMA_CQP_OP_QUERY_FPM_VAL,
 					     NULL);
  * @post_sq: flag for cqp db to ring
  * @wait_type: poll ccq or cqp registers for cqp completion
  */
-static enum irdma_status_code
+static int irdma_sc_query_fpm_val(struct irdma_sc_cqp *cqp, u64 scratch,
-irdma_sc_query_fpm_val(struct irdma_sc_cqp *cqp, u64 scratch, u8 hmc_fn_id,
+				  u8 hmc_fn_id,
-		       struct irdma_dma_mem *query_fpm_mem, bool post_sq,
+				  struct irdma_dma_mem *query_fpm_mem,
-		       u8 wait_type)
+				  bool post_sq, u8 wait_type)
 {
 	__le64 *wqe;
 	u64 hdr;
 	u32 tail, val, error;
-	enum irdma_status_code ret_code = 0;
+	int ret_code = 0;
 	wqe = irdma_sc_cqp_get_next_send_wqe(cqp, scratch);
 	if (!wqe)
-		return IRDMA_ERR_RING_FULL;
+		return -ENOMEM;
 	set_64bit_val(wqe, 16, hmc_fn_id);
 	set_64bit_val(wqe, 32, query_fpm_mem->pa);
  * @ceq: ceq sc structure
  * @info: ceq initialization info
  */
-enum irdma_status_code irdma_sc_ceq_init(struct irdma_sc_ceq *ceq,
+int irdma_sc_ceq_init(struct irdma_sc_ceq *ceq,
-					 struct irdma_ceq_init_info *info)
+		      struct irdma_ceq_init_info *info)
 {
 	u32 pble_obj_cnt;
 	if (info->elem_cnt < info->dev->hw_attrs.min_hw_ceq_size ||
 	    info->elem_cnt > info->dev->hw_attrs.max_hw_ceq_size)
-		return IRDMA_ERR_INVALID_SIZE;
+		return -EINVAL;
-	if (info->ceq_id > (info->dev->hmc_fpm_misc.max_ceqs - 1))
+	if (info->ceq_id >= info->dev->hmc_fpm_misc.max_ceqs)
-		return IRDMA_ERR_INVALID_CEQ_ID;
+		return -EINVAL;
 	pble_obj_cnt = info->dev->hmc_info->hmc_obj[IRDMA_HMC_IW_PBLE].cnt;
 	if (info->virtual_map && info->first_pm_pbl_idx >= pble_obj_cnt)
-		return IRDMA_ERR_INVALID_PBLE_INDEX;
+		return -EINVAL;
 	ceq->size = sizeof(*ceq);
 	ceq->ceqe_base = (struct irdma_ceqe *)info->ceqe_base;
  * @post_sq: flag for cqp db to ring
  */
-static enum irdma_status_code irdma_sc_ceq_create(struct irdma_sc_ceq *ceq, u64 scratch,
+static int irdma_sc_ceq_create(struct irdma_sc_ceq *ceq, u64 scratch,
-						  bool post_sq)
+			       bool post_sq)
 {
 	struct irdma_sc_cqp *cqp;
 	__le64 *wqe;
 	cqp = ceq->dev->cqp;
 	wqe = irdma_sc_cqp_get_next_send_wqe(cqp, scratch);
 	if (!wqe)
-		return IRDMA_ERR_RING_FULL;
+		return -ENOMEM;
 	set_64bit_val(wqe, 16, ceq->elem_cnt);
 	set_64bit_val(wqe, 32,
 		      (ceq->virtual_map ? 0 : ceq->ceq_elem_pa));
  * irdma_sc_cceq_create_done - poll for control ceq wqe to complete
  * @ceq: ceq sc structure
  */
-static enum irdma_status_code
+static int irdma_sc_cceq_create_done(struct irdma_sc_ceq *ceq)
-irdma_sc_cceq_create_done(struct irdma_sc_ceq *ceq)
 {
 	struct irdma_sc_cqp *cqp;
  * irdma_sc_cceq_destroy_done - poll for destroy cceq to complete
  * @ceq: ceq sc structure
  */
-enum irdma_status_code irdma_sc_cceq_destroy_done(struct irdma_sc_ceq *ceq)
+int irdma_sc_cceq_destroy_done(struct irdma_sc_ceq *ceq)
 {
 	struct irdma_sc_cqp *cqp;
  * @ceq: ceq sc structure
  * @scratch: u64 saved to be used during cqp completion
  */
-enum irdma_status_code irdma_sc_cceq_create(struct irdma_sc_ceq *ceq, u64 scratch)
+int irdma_sc_cceq_create(struct irdma_sc_ceq *ceq, u64 scratch)
 {
-	enum irdma_status_code ret_code;
+	int ret_code;
 	struct irdma_sc_dev *dev = ceq->dev;
 	dev->ccq->vsi = ceq->vsi;
  * @scratch: u64 saved to be used during cqp completion
  * @post_sq: flag for cqp db to ring
  */
-enum irdma_status_code irdma_sc_ceq_destroy(struct irdma_sc_ceq *ceq, u64 scratch,
+int irdma_sc_ceq_destroy(struct irdma_sc_ceq *ceq, u64 scratch, bool post_sq)
-					    bool post_sq)
 {
 	struct irdma_sc_cqp *cqp;
 	__le64 *wqe;
 	cqp = ceq->dev->cqp;
 	wqe = irdma_sc_cqp_get_next_send_wqe(cqp, scratch);
 	if (!wqe)
-		return IRDMA_ERR_RING_FULL;
+		return -ENOMEM;
 	set_64bit_val(wqe, 16, ceq->elem_cnt);
 	set_64bit_val(wqe, 48, ceq->first_pm_pbl_idx);
  * @aeq: aeq structure ptr
  * @info: aeq initialization info
  */
-enum irdma_status_code irdma_sc_aeq_init(struct irdma_sc_aeq *aeq,
+int irdma_sc_aeq_init(struct irdma_sc_aeq *aeq,
-					 struct irdma_aeq_init_info *info)
+		      struct irdma_aeq_init_info *info)
 {
 	u32 pble_obj_cnt;
 	if (info->elem_cnt < info->dev->hw_attrs.min_hw_aeq_size ||
 	    info->elem_cnt > info->dev->hw_attrs.max_hw_aeq_size)
-		return IRDMA_ERR_INVALID_SIZE;
+		return -EINVAL;
 	pble_obj_cnt = info->dev->hmc_info->hmc_obj[IRDMA_HMC_IW_PBLE].cnt;
 	if (info->virtual_map && info->first_pm_pbl_idx >= pble_obj_cnt)
-		return IRDMA_ERR_INVALID_PBLE_INDEX;
+		return -EINVAL;
 	aeq->size = sizeof(*aeq);
 	aeq->polarity = 1;
  * @scratch: u64 saved to be used during cqp completion
  * @post_sq: flag for cqp db to ring
  */
-static enum irdma_status_code irdma_sc_aeq_create(struct irdma_sc_aeq *aeq,
+static int irdma_sc_aeq_create(struct irdma_sc_aeq *aeq, u64 scratch,
-						  u64 scratch, bool post_sq)
+			       bool post_sq)
 {
 	__le64 *wqe;
 	struct irdma_sc_cqp *cqp;
 	cqp = aeq->dev->cqp;
 	wqe = irdma_sc_cqp_get_next_send_wqe(cqp, scratch);
 	if (!wqe)
-		return IRDMA_ERR_RING_FULL;
+		return -ENOMEM;
 	set_64bit_val(wqe, 16, aeq->elem_cnt);
 	set_64bit_val(wqe, 32,
 		      (aeq->virtual_map ? 0 : aeq->aeq_elem_pa));
  * @scratch: u64 saved to be used during cqp completion
  * @post_sq: flag for cqp db to ring
  */
-static enum irdma_status_code irdma_sc_aeq_destroy(struct irdma_sc_aeq *aeq,
+static int irdma_sc_aeq_destroy(struct irdma_sc_aeq *aeq, u64 scratch,
-						   u64 scratch, bool post_sq)
+				bool post_sq)
 {
 	__le64 *wqe;
 	struct irdma_sc_cqp *cqp;
 	cqp = dev->cqp;
 	wqe = irdma_sc_cqp_get_next_send_wqe(cqp, scratch);
 	if (!wqe)
-		return IRDMA_ERR_RING_FULL;
+		return -ENOMEM;
 	set_64bit_val(wqe, 16, aeq->elem_cnt);
 	set_64bit_val(wqe, 48, aeq->first_pm_pbl_idx);
 	hdr = FIELD_PREP(IRDMA_CQPSQ_OPCODE, IRDMA_CQP_OP_DESTROY_AEQ) |
  * @aeq: aeq structure ptr
  * @info: aeqe info to be returned
  */
-enum irdma_status_code irdma_sc_get_next_aeqe(struct irdma_sc_aeq *aeq,
+int irdma_sc_get_next_aeqe(struct irdma_sc_aeq *aeq,
-					      struct irdma_aeqe_info *info)
+			   struct irdma_aeqe_info *info)
 {
 	u64 temp, compl_ctx;
 	__le64 *aeqe;
 	polarity = (u8)FIELD_GET(IRDMA_AEQE_VALID, temp);
 	if (aeq->polarity != polarity)
-		return IRDMA_ERR_Q_EMPTY;
+		return -ENOENT;
 	print_hex_dump_debug("WQE: AEQ_ENTRY WQE", DUMP_PREFIX_OFFSET, 16, 8,
 			     aeqe, 16, false);
  * @cq: sc's cq ctruct
  * @info: info for control cq initialization
  */
-enum irdma_status_code irdma_sc_ccq_init(struct irdma_sc_cq *cq,
+int irdma_sc_ccq_init(struct irdma_sc_cq *cq, struct irdma_ccq_init_info *info)
-					 struct irdma_ccq_init_info *info)
 {
 	u32 pble_obj_cnt;
 	if (info->num_elem < info->dev->hw_attrs.uk_attrs.min_hw_cq_size ||
 	    info->num_elem > info->dev->hw_attrs.uk_attrs.max_hw_cq_size)
-		return IRDMA_ERR_INVALID_SIZE;
+		return -EINVAL;
-	if (info->ceq_id > (info->dev->hmc_fpm_misc.max_ceqs - 1))
+	if (info->ceq_id >= info->dev->hmc_fpm_misc.max_ceqs)
-		return IRDMA_ERR_INVALID_CEQ_ID;
+		return -EINVAL;
 	pble_obj_cnt = info->dev->hmc_info->hmc_obj[IRDMA_HMC_IW_PBLE].cnt;
 	if (info->virtual_map && info->first_pm_pbl_idx >= pble_obj_cnt)
-		return IRDMA_ERR_INVALID_PBLE_INDEX;
+		return -EINVAL;
 	cq->cq_pa = info->cq_pa;
 	cq->cq_uk.cq_base = info->cq_base;
  * irdma_sc_ccq_create_done - poll cqp for ccq create
  * @ccq: ccq sc struct
  */
-static inline enum irdma_status_code irdma_sc_ccq_create_done(struct irdma_sc_cq *ccq)
+static inline int irdma_sc_ccq_create_done(struct irdma_sc_cq *ccq)
 {
 	struct irdma_sc_cqp *cqp;
  * @check_overflow: overlow flag for ccq
  * @post_sq: flag for cqp db to ring
  */
-enum irdma_status_code irdma_sc_ccq_create(struct irdma_sc_cq *ccq, u64 scratch,
+int irdma_sc_ccq_create(struct irdma_sc_cq *ccq, u64 scratch,
-					   bool check_overflow, bool post_sq)
+			bool check_overflow, bool post_sq)
 {
-	enum irdma_status_code ret_code;
+	int ret_code;
 	ret_code = irdma_sc_cq_create(ccq, scratch, check_overflow, post_sq);
 	if (ret_code)
  * @scratch: u64 saved to be used during cqp completion
  * @post_sq: flag for cqp db to ring
  */
-enum irdma_status_code irdma_sc_ccq_destroy(struct irdma_sc_cq *ccq, u64 scratch,
+int irdma_sc_ccq_destroy(struct irdma_sc_cq *ccq, u64 scratch, bool post_sq)
-					    bool post_sq)
 {
 	struct irdma_sc_cqp *cqp;
 	__le64 *wqe;
 	u64 hdr;
-	enum irdma_status_code ret_code = 0;
+	int ret_code = 0;
 	u32 tail, val, error;
 	cqp = ccq->dev->cqp;
 	wqe = irdma_sc_cqp_get_next_send_wqe(cqp, scratch);
 	if (!wqe)
-		return IRDMA_ERR_RING_FULL;
+		return -ENOMEM;
 	set_64bit_val(wqe, 0, ccq->cq_uk.cq_size);
 	set_64bit_val(wqe, 8, (uintptr_t)ccq >> 1);
  * @dev : ptr to irdma_dev struct
  * @hmc_fn_id: hmc function id
  */
-enum irdma_status_code irdma_sc_init_iw_hmc(struct irdma_sc_dev *dev,
+int irdma_sc_init_iw_hmc(struct irdma_sc_dev *dev, u8 hmc_fn_id)
-					    u8 hmc_fn_id)
 {
 	struct irdma_hmc_info *hmc_info;
 	struct irdma_hmc_fpm_misc *hmc_fpm_misc;
 	struct irdma_dma_mem query_fpm_mem;
-	enum irdma_status_code ret_code = 0;
+	int ret_code = 0;
 	u8 wait_type;
 	hmc_info = dev->hmc_info;
  * @dev : ptr to irdma_dev struct
  * @hmc_fn_id: hmc function id
  */
-static enum irdma_status_code irdma_sc_cfg_iw_fpm(struct irdma_sc_dev *dev,
+static int irdma_sc_cfg_iw_fpm(struct irdma_sc_dev *dev, u8 hmc_fn_id)
-						  u8 hmc_fn_id)
 {
 	struct irdma_hmc_info *hmc_info;
 	struct irdma_hmc_obj_info *obj_info;
 	__le64 *buf;
 	struct irdma_dma_mem commit_fpm_mem;
-	enum irdma_status_code ret_code = 0;
+	int ret_code = 0;
 	u8 wait_type;
 	hmc_info = dev->hmc_info;
  * @info: sd info for wqe
  * @scratch: u64 saved to be used during cqp completion
  */
-static enum irdma_status_code
+static int cqp_sds_wqe_fill(struct irdma_sc_cqp *cqp,
-cqp_sds_wqe_fill(struct irdma_sc_cqp *cqp, struct irdma_update_sds_info *info,
+			    struct irdma_update_sds_info *info, u64 scratch)
-		 u64 scratch)
 {
 	u64 data;
 	u64 hdr;
 	wqe = irdma_sc_cqp_get_next_send_wqe_idx(cqp, scratch, &wqe_idx);
 	if (!wqe)
-		return IRDMA_ERR_RING_FULL;
+		return -ENOMEM;
 	wqe_entries = (info->cnt > 3) ? 3 : info->cnt;
 	mem_entries = info->cnt - wqe_entries;
  * @info: sd info for sd's
  * @scratch: u64 saved to be used during cqp completion
  */
-static enum irdma_status_code
+static int irdma_update_pe_sds(struct irdma_sc_dev *dev,
-irdma_update_pe_sds(struct irdma_sc_dev *dev,
+			       struct irdma_update_sds_info *info, u64 scratch)
-		    struct irdma_update_sds_info *info, u64 scratch)
 {
 	struct irdma_sc_cqp *cqp = dev->cqp;
-	enum irdma_status_code ret_code;
+	int ret_code;
 	ret_code = cqp_sds_wqe_fill(cqp, info, scratch);
 	if (!ret_code)
  * @dev: sc device struct
  * @info: sd info for sd's
  */
-enum irdma_status_code
+int irdma_update_sds_noccq(struct irdma_sc_dev *dev,
-irdma_update_sds_noccq(struct irdma_sc_dev *dev,
+			   struct irdma_update_sds_info *info)
-		       struct irdma_update_sds_info *info)
 {
 	u32 error, val, tail;
 	struct irdma_sc_cqp *cqp = dev->cqp;
-	enum irdma_status_code ret_code;
+	int ret_code;
 	ret_code = cqp_sds_wqe_fill(cqp, info, 0);
 	if (ret_code)
  * @post_sq: flag for cqp db to ring
  * @poll_registers: flag to poll register for cqp completion
  */
-enum irdma_status_code
+int irdma_sc_static_hmc_pages_allocated(struct irdma_sc_cqp *cqp, u64 scratch,
-irdma_sc_static_hmc_pages_allocated(struct irdma_sc_cqp *cqp, u64 scratch,
+					u8 hmc_fn_id, bool post_sq,
-				    u8 hmc_fn_id, bool post_sq,
+					bool poll_registers)
-				    bool poll_registers)
 {
 	u64 hdr;
 	__le64 *wqe;
 	wqe = irdma_sc_cqp_get_next_send_wqe(cqp, scratch);
 	if (!wqe)
-		return IRDMA_ERR_RING_FULL;
+		return -ENOMEM;
 	set_64bit_val(wqe, 16,
 		      FIELD_PREP(IRDMA_SHMC_PAGE_ALLOCATED_HMC_FN_ID, hmc_fn_id));
  * irdma_sc_query_rdma_features_done - poll cqp for query features done
  * @cqp: struct for cqp hw
  */
-static enum irdma_status_code
+static int irdma_sc_query_rdma_features_done(struct irdma_sc_cqp *cqp)
-irdma_sc_query_rdma_features_done(struct irdma_sc_cqp *cqp)
 {
 	return irdma_sc_poll_for_cqp_op_done(cqp,
 					     IRDMA_CQP_OP_QUERY_RDMA_FEATURES,
  * @buf: buffer to hold query info
  * @scratch: u64 saved to be used during cqp completion
  */
-static enum irdma_status_code
+static int irdma_sc_query_rdma_features(struct irdma_sc_cqp *cqp,
-irdma_sc_query_rdma_features(struct irdma_sc_cqp *cqp,
+					struct irdma_dma_mem *buf, u64 scratch)
-			     struct irdma_dma_mem *buf, u64 scratch)
 {
 	__le64 *wqe;
 	u64 temp;
 	wqe = irdma_sc_cqp_get_next_send_wqe(cqp, scratch);
 	if (!wqe)
-		return IRDMA_ERR_RING_FULL;
+		return -ENOMEM;
 	temp = buf->pa;
 	set_64bit_val(wqe, 32, temp);
  * irdma_get_rdma_features - get RDMA features
  * @dev: sc device struct
  */
-enum irdma_status_code irdma_get_rdma_features(struct irdma_sc_dev *dev)
+int irdma_get_rdma_features(struct irdma_sc_dev *dev)
 {
-	enum irdma_status_code ret_code;
+	int ret_code;
 	struct irdma_dma_mem feat_buf;
 	u64 temp;
 	u16 byte_idx, feat_type, feat_cnt, feat_idx;
 	feat_buf.va = dma_alloc_coherent(dev->hw->device, feat_buf.size,
 					 &feat_buf.pa, GFP_KERNEL);
 	if (!feat_buf.va)
-		return IRDMA_ERR_NO_MEMORY;
+		return -ENOMEM;
 	ret_code = irdma_sc_query_rdma_features(dev->cqp, &feat_buf, 0);
 	if (!ret_code)
 	get_64bit_val(feat_buf.va, 0, &temp);
 	feat_cnt = (u16)FIELD_GET(IRDMA_FEATURE_CNT, temp);
 	if (feat_cnt < 2) {
-		ret_code = IRDMA_ERR_INVALID_FEAT_CNT;
+		ret_code = -EINVAL;
 		goto exit;
 	} else if (feat_cnt > IRDMA_MAX_FEATURES) {
 		ibdev_dbg(to_ibdev(dev),
 						 feat_buf.size, &feat_buf.pa,
 						 GFP_KERNEL);
 		if (!feat_buf.va)
-			return IRDMA_ERR_NO_MEMORY;
+			return -ENOMEM;
 		ret_code = irdma_sc_query_rdma_features(dev->cqp, &feat_buf, 0);
 		if (!ret_code)
 		get_64bit_val(feat_buf.va, 0, &temp);
 		feat_cnt = (u16)FIELD_GET(IRDMA_FEATURE_CNT, temp);
 		if (feat_cnt < 2) {
-			ret_code = IRDMA_ERR_INVALID_FEAT_CNT;
+			ret_code = -EINVAL;
 			goto exit;
 		}
 	}
  * @dev: sc device struct
  * @qp_count: desired qp count
  */
-enum irdma_status_code irdma_cfg_fpm_val(struct irdma_sc_dev *dev, u32 qp_count)
+int irdma_cfg_fpm_val(struct irdma_sc_dev *dev, u32 qp_count)
 {
 	struct irdma_virt_mem virt_mem;
 	u32 i, mem_size;
 	u32 loop_count = 0;
 	struct irdma_hmc_info *hmc_info;
 	struct irdma_hmc_fpm_misc *hmc_fpm_misc;
-	enum irdma_status_code ret_code = 0;
+	int ret_code = 0;
 	hmc_info = dev->hmc_info;
 	hmc_fpm_misc = &dev->hmc_fpm_misc;
 		ibdev_dbg(to_ibdev(dev),
 			  "HMC: cfg_fpm failed loop_cnt=%d, sd_needed=%d, max sd count %d\n",
 			  loop_count, sd_needed, hmc_info->sd_table.sd_cnt);
-		return IRDMA_ERR_CFG;
+		return -EINVAL;
 	}
 	if (loop_count > 1 && sd_needed < hmc_fpm_misc->max_sds) {
 	if (!virt_mem.va) {
 		ibdev_dbg(to_ibdev(dev),
 			  "HMC: failed to allocate memory for sd_entry buffer\n");
-		return IRDMA_ERR_NO_MEMORY;
+		return -ENOMEM;
 	}
 	hmc_info->sd_table.sd_entry = virt_mem.va;
  * @dev: rdma device
  * @pcmdinfo: cqp command info
  */
-static enum irdma_status_code irdma_exec_cqp_cmd(struct irdma_sc_dev *dev,
+static int irdma_exec_cqp_cmd(struct irdma_sc_dev *dev,
-						 struct cqp_cmds_info *pcmdinfo)
+			      struct cqp_cmds_info *pcmdinfo)
 {
-	enum irdma_status_code status;
+	int status;
 	struct irdma_dma_mem val_mem;
 	bool alloc = false;
 						   pcmdinfo->in.u.mc_modify.scratch);
 		break;
 	default:
-		status = IRDMA_NOT_SUPPORTED;
+		status = -EOPNOTSUPP;
 		break;
 	}
  * @dev: sc device struct
  * @pcmdinfo: cqp command info
  */
-enum irdma_status_code irdma_process_cqp_cmd(struct irdma_sc_dev *dev,
+int irdma_process_cqp_cmd(struct irdma_sc_dev *dev,
-					     struct cqp_cmds_info *pcmdinfo)
+			  struct cqp_cmds_info *pcmdinfo)
 {
-	enum irdma_status_code status = 0;
+	int status = 0;
 	unsigned long flags;
 	spin_lock_irqsave(&dev->cqp_lock, flags);
  * irdma_process_bh - called from tasklet for cqp list
  * @dev: sc device struct
  */
-enum irdma_status_code irdma_process_bh(struct irdma_sc_dev *dev)
+int irdma_process_bh(struct irdma_sc_dev *dev)
 {
-	enum irdma_status_code status = 0;
+	int status = 0;
 	struct cqp_cmds_info *pcmdinfo;
 	unsigned long flags;
  * @dev: Device pointer
  * @info: Device init info
  */
-enum irdma_status_code irdma_sc_dev_init(enum irdma_vers ver,
+int irdma_sc_dev_init(enum irdma_vers ver, struct irdma_sc_dev *dev,
-					 struct irdma_sc_dev *dev,
+		      struct irdma_device_init_info *info)
-					 struct irdma_device_init_info *info)
 {
 	u32 val;
-	enum irdma_status_code ret_code = 0;
+	int ret_code = 0;
 	u8 db_size;
 	INIT_LIST_HEAD(&dev->cqp_cmd_head); /* for CQP command backlog */
 	irdma_sc_init_hw(dev);
 	if (irdma_wait_pe_ready(dev))
-		return IRDMA_ERR_TIMEOUT;
+		return -ETIMEDOUT;
 	val = readl(dev->hw_regs[IRDMA_GLPCI_LBARCTRL]);
 	db_size = (u8)FIELD_GET(IRDMA_GLPCI_LBARCTRL_PE_DB_SIZE, val);
 		ibdev_dbg(to_ibdev(dev),
 			  "DEV: RDMA PE doorbell is not enabled in CSR val 0x%x db_size=%d\n",
 			  val, db_size);
-		return IRDMA_ERR_PE_DOORBELL_NOT_ENA;
+		return -ENODEV;
 	}
 	dev->db_addr = dev->hw->hw_addr + (uintptr_t)dev->hw_regs[IRDMA_DB_ADDR_OFFSET];

drivers/infiniband/hw/irdma/defs.h+4−4

@@ -964,7 +964,7 @@ enum irdma_cqp_op_type { · 963 unmodified lines
964	(_ring).head = ((_ring).head + 1) % size; \	964	(_ring).head = ((_ring).head + 1) % size; \
965	(_retcode) = 0; \	965	(_retcode) = 0; \
966	} else { \	966	} else { \
967	(_retcode) = IRDMA_ERR_RING_FULL; \	967	(_retcode) = -ENOMEM; \
968	} \	968	} \
969	}	969	}
970	#define IRDMA_RING_MOVE_HEAD_BY_COUNT(_ring, _count, _retcode) \	970	#define IRDMA_RING_MOVE_HEAD_BY_COUNT(_ring, _count, _retcode) \
@@ -975,7 +975,7 @@ enum irdma_cqp_op_type { · 4 unmodified lines
975	(_ring).head = ((_ring).head + (_count)) % size; \	975	(_ring).head = ((_ring).head + (_count)) % size; \
976	(_retcode) = 0; \	976	(_retcode) = 0; \
977	} else { \	977	} else { \
978	(_retcode) = IRDMA_ERR_RING_FULL; \	978	(_retcode) = -ENOMEM; \
979	} \	979	} \
980	}	980	}
981	#define IRDMA_SQ_RING_MOVE_HEAD(_ring, _retcode) \	981	#define IRDMA_SQ_RING_MOVE_HEAD(_ring, _retcode) \
@@ -986,7 +986,7 @@ enum irdma_cqp_op_type { · 4 unmodified lines
986	(_ring).head = ((_ring).head + 1) % size; \	986	(_ring).head = ((_ring).head + 1) % size; \
987	(_retcode) = 0; \	987	(_retcode) = 0; \
988	} else { \	988	} else { \
989	(_retcode) = IRDMA_ERR_RING_FULL; \	989	(_retcode) = -ENOMEM; \
990	} \	990	} \
991	}	991	}
992	#define IRDMA_SQ_RING_MOVE_HEAD_BY_COUNT(_ring, _count, _retcode) \	992	#define IRDMA_SQ_RING_MOVE_HEAD_BY_COUNT(_ring, _count, _retcode) \
@@ -997,7 +997,7 @@ enum irdma_cqp_op_type { · 4 unmodified lines
997	(_ring).head = ((_ring).head + (_count)) % size; \	997	(_ring).head = ((_ring).head + (_count)) % size; \
998	(_retcode) = 0; \	998	(_retcode) = 0; \
999	} else { \	999	} else { \
1000	(_retcode) = IRDMA_ERR_RING_FULL; \	1000	(_retcode) = -ENOMEM; \
1001	} \	1001	} \
1002	}	1002	}
1003	#define IRDMA_RING_MOVE_HEAD_BY_COUNT_NOCHECK(_ring, _count) \	1003	#define IRDMA_RING_MOVE_HEAD_BY_COUNT_NOCHECK(_ring, _count) \

drivers/infiniband/hw/irdma/hmc.c+46−59

 // SPDX-License-Identifier: GPL-2.0 or Linux-OpenIB
 /* Copyright (c) 2015 - 2021 Intel Corporation */
 #include "osdep.h"
-#include "status.h"
 #include "hmc.h"
 #include "defs.h"
 #include "type.h"
  * @type: paged or direct sd
  * @setsd: flag to set or clear sd
  */
-enum irdma_status_code irdma_hmc_sd_one(struct irdma_sc_dev *dev, u8 hmc_fn_id,
+int irdma_hmc_sd_one(struct irdma_sc_dev *dev, u8 hmc_fn_id, u64 pa, u32 sd_idx,
-					u64 pa, u32 sd_idx,
+		     enum irdma_sd_entry_type type, bool setsd)
-					enum irdma_sd_entry_type type,
-					bool setsd)
 {
 	struct irdma_update_sds_info sdinfo;
  * @sd_cnt: number of sd entries
  * @setsd: flag to set or clear sd
  */
-static enum irdma_status_code irdma_hmc_sd_grp(struct irdma_sc_dev *dev,
+static int irdma_hmc_sd_grp(struct irdma_sc_dev *dev,
-					       struct irdma_hmc_info *hmc_info,
+			    struct irdma_hmc_info *hmc_info, u32 sd_index,
-					       u32 sd_index, u32 sd_cnt,
+			    u32 sd_cnt, bool setsd)
-					       bool setsd)
 {
 	struct irdma_hmc_sd_entry *sd_entry;
 	struct irdma_update_sds_info sdinfo = {};
 	u64 pa;
 	u32 i;
-	enum irdma_status_code ret_code = 0;
+	int ret_code = 0;
 	sdinfo.hmc_fn_id = hmc_info->hmc_fn_id;
 	for (i = sd_index; i < sd_index + sd_cnt; i++) {
  * @dev: pointer to the device structure
  * @info: create obj info
  */
-static enum irdma_status_code
+static int irdma_hmc_finish_add_sd_reg(struct irdma_sc_dev *dev,
-irdma_hmc_finish_add_sd_reg(struct irdma_sc_dev *dev,
+				       struct irdma_hmc_create_obj_info *info)
-			    struct irdma_hmc_create_obj_info *info)
 {
 	if (info->start_idx >= info->hmc_info->hmc_obj[info->rsrc_type].cnt)
-		return IRDMA_ERR_INVALID_HMC_OBJ_INDEX;
+		return -EINVAL;
 	if ((info->start_idx + info->count) >
 	    info->hmc_info->hmc_obj[info->rsrc_type].cnt)
-		return IRDMA_ERR_INVALID_HMC_OBJ_COUNT;
+		return -EINVAL;
 	if (!info->add_sd_cnt)
 		return 0;
  * This will allocate memory for PDs and backing pages and populate
  * the sd and pd entries.
  */
-enum irdma_status_code
+int irdma_sc_create_hmc_obj(struct irdma_sc_dev *dev,
-irdma_sc_create_hmc_obj(struct irdma_sc_dev *dev,
+			    struct irdma_hmc_create_obj_info *info)
-			struct irdma_hmc_create_obj_info *info)
 {
 	struct irdma_hmc_sd_entry *sd_entry;
 	u32 sd_idx, sd_lmt;
 	u32 pd_idx1 = 0, pd_lmt1 = 0;
 	u32 i, j;
 	bool pd_error = false;
-	enum irdma_status_code ret_code = 0;
+	int ret_code = 0;
 	if (info->start_idx >= info->hmc_info->hmc_obj[info->rsrc_type].cnt)
-		return IRDMA_ERR_INVALID_HMC_OBJ_INDEX;
+		return -EINVAL;
 	if ((info->start_idx + info->count) >
 	    info->hmc_info->hmc_obj[info->rsrc_type].cnt) {
 			  "HMC: error type %u, start = %u, req cnt %u, cnt = %u\n",
 			  info->rsrc_type, info->start_idx, info->count,
 			  info->hmc_info->hmc_obj[info->rsrc_type].cnt);
-		return IRDMA_ERR_INVALID_HMC_OBJ_COUNT;
+		return -EINVAL;
 	}
 	irdma_find_sd_index_limit(info->hmc_info, info->rsrc_type,
 				  &sd_lmt);
 	if (sd_idx >= info->hmc_info->sd_table.sd_cnt ||
 	    sd_lmt > info->hmc_info->sd_table.sd_cnt) {
-		return IRDMA_ERR_INVALID_SD_INDEX;
+		return -EINVAL;
 	}
 	irdma_find_pd_index_limit(info->hmc_info, info->rsrc_type,
 			irdma_prep_remove_pd_page(info->hmc_info, (j - 1));
 			break;
 		default:
-			ret_code = IRDMA_ERR_INVALID_SD_TYPE;
+			ret_code = -EINVAL;
 			break;
 		}
 		j--;
  * @info: dele obj info
  * @reset: true if called before reset
  */
-static enum irdma_status_code
+static int irdma_finish_del_sd_reg(struct irdma_sc_dev *dev,
-irdma_finish_del_sd_reg(struct irdma_sc_dev *dev,
+				   struct irdma_hmc_del_obj_info *info,
-			struct irdma_hmc_del_obj_info *info, bool reset)
+				   bool reset)
 {
 	struct irdma_hmc_sd_entry *sd_entry;
-	enum irdma_status_code ret_code = 0;
+	int ret_code = 0;
 	u32 i, sd_idx;
 	struct irdma_dma_mem *mem;
  * caller should deallocate memory allocated previously for
  * book-keeping information about PDs and backing storage.
  */
-enum irdma_status_code irdma_sc_del_hmc_obj(struct irdma_sc_dev *dev,
+int irdma_sc_del_hmc_obj(struct irdma_sc_dev *dev,
-					    struct irdma_hmc_del_obj_info *info,
+			 struct irdma_hmc_del_obj_info *info, bool reset)
-					    bool reset)
 {
 	struct irdma_hmc_pd_table *pd_table;
 	u32 sd_idx, sd_lmt;
 	u32 pd_idx, pd_lmt, rel_pd_idx;
 	u32 i, j;
-	enum irdma_status_code ret_code = 0;
+	int ret_code = 0;
 	if (info->start_idx >= info->hmc_info->hmc_obj[info->rsrc_type].cnt) {
 		ibdev_dbg(to_ibdev(dev),
 			  "HMC: error start_idx[%04d]  >= [type %04d].cnt[%04d]\n",
 			  info->start_idx, info->rsrc_type,
 			  info->hmc_info->hmc_obj[info->rsrc_type].cnt);
-		return IRDMA_ERR_INVALID_HMC_OBJ_INDEX;
+		return -EINVAL;
 	}
 	if ((info->start_idx + info->count) >
 			  "HMC: error start_idx[%04d] + count %04d  >= [type %04d].cnt[%04d]\n",
 			  info->start_idx, info->count, info->rsrc_type,
 			  info->hmc_info->hmc_obj[info->rsrc_type].cnt);
-		return IRDMA_ERR_INVALID_HMC_OBJ_COUNT;
+		return -EINVAL;
 	}
 	irdma_find_pd_index_limit(info->hmc_info, info->rsrc_type,
 	if (sd_idx >= info->hmc_info->sd_table.sd_cnt ||
 	    sd_lmt > info->hmc_info->sd_table.sd_cnt) {
 		ibdev_dbg(to_ibdev(dev), "HMC: invalid sd_idx\n");
-		return IRDMA_ERR_INVALID_SD_INDEX;
+		return -EINVAL;
 	}
 	for (i = sd_idx; i < sd_lmt; i++) {
  * @type: what type of segment descriptor we're manipulating
  * @direct_mode_sz: size to alloc in direct mode
  */
-enum irdma_status_code irdma_add_sd_table_entry(struct irdma_hw *hw,
+int irdma_add_sd_table_entry(struct irdma_hw *hw,
-						struct irdma_hmc_info *hmc_info,
+			     struct irdma_hmc_info *hmc_info, u32 sd_index,
-						u32 sd_index,
+			     enum irdma_sd_entry_type type, u64 direct_mode_sz)
-						enum irdma_sd_entry_type type,
-						u64 direct_mode_sz)
 {
 	struct irdma_hmc_sd_entry *sd_entry;
 	struct irdma_dma_mem dma_mem;
 		dma_mem.va = dma_alloc_coherent(hw->device, dma_mem.size,
 						&dma_mem.pa, GFP_KERNEL);
 		if (!dma_mem.va)
-			return IRDMA_ERR_NO_MEMORY;
+			return -ENOMEM;
 		if (type == IRDMA_SD_TYPE_PAGED) {
 			struct irdma_virt_mem *vmem =
 				&sd_entry->u.pd_table.pd_entry_virt_mem;
 				dma_free_coherent(hw->device, dma_mem.size,
 						  dma_mem.va, dma_mem.pa);
 				dma_mem.va = NULL;
-				return IRDMA_ERR_NO_MEMORY;
+				return -ENOMEM;
 			}
 			sd_entry->u.pd_table.pd_entry = vmem->va;
  *	   aligned on 4K boundary and zeroed memory.
  *	2. It should be 4K in size.
  */
-enum irdma_status_code irdma_add_pd_table_entry(struct irdma_sc_dev *dev,
+int irdma_add_pd_table_entry(struct irdma_sc_dev *dev,
-						struct irdma_hmc_info *hmc_info,
+			     struct irdma_hmc_info *hmc_info, u32 pd_index,
-						u32 pd_index,
+			     struct irdma_dma_mem *rsrc_pg)
-						struct irdma_dma_mem *rsrc_pg)
 {
 	struct irdma_hmc_pd_table *pd_table;
 	struct irdma_hmc_pd_entry *pd_entry;
 	u64 page_desc;
 	if (pd_index / IRDMA_HMC_PD_CNT_IN_SD >= hmc_info->sd_table.sd_cnt)
-		return IRDMA_ERR_INVALID_PAGE_DESC_INDEX;
+		return -EINVAL;
 	sd_idx = (pd_index / IRDMA_HMC_PD_CNT_IN_SD);
 	if (hmc_info->sd_table.sd_entry[sd_idx].entry_type !=
 						      page->size, &page->pa,
 						      GFP_KERNEL);
 			if (!page->va)
-				return IRDMA_ERR_NO_MEMORY;
+				return -ENOMEM;
 			pd_entry->rsrc_pg = false;
 		}
  *	1. Caller can deallocate the memory used by backing storage after this
  *	   function returns.
  */
-enum irdma_status_code irdma_remove_pd_bp(struct irdma_sc_dev *dev,
+int irdma_remove_pd_bp(struct irdma_sc_dev *dev,
-					  struct irdma_hmc_info *hmc_info,
+		       struct irdma_hmc_info *hmc_info, u32 idx)
-					  u32 idx)
 {
 	struct irdma_hmc_pd_entry *pd_entry;
 	struct irdma_hmc_pd_table *pd_table;
 	sd_idx = idx / IRDMA_HMC_PD_CNT_IN_SD;
 	rel_pd_idx = idx % IRDMA_HMC_PD_CNT_IN_SD;
 	if (sd_idx >= hmc_info->sd_table.sd_cnt)
-		return IRDMA_ERR_INVALID_PAGE_DESC_INDEX;
+		return -EINVAL;
 	sd_entry = &hmc_info->sd_table.sd_entry[sd_idx];
 	if (sd_entry->entry_type != IRDMA_SD_TYPE_PAGED)
-		return IRDMA_ERR_INVALID_SD_TYPE;
+		return -EINVAL;
 	pd_table = &hmc_info->sd_table.sd_entry[sd_idx].u.pd_table;
 	pd_entry = &pd_table->pd_entry[rel_pd_idx];
 	if (!pd_entry->rsrc_pg) {
 		mem = &pd_entry->bp.addr;
 		if (!mem || !mem->va)
-			return IRDMA_ERR_PARAM;
+			return -EINVAL;
 		dma_free_coherent(dev->hw->device, mem->size, mem->va,
 				  mem->pa);
  * @hmc_info: pointer to the HMC configuration information structure
  * @idx: the page index
  */
-enum irdma_status_code irdma_prep_remove_sd_bp(struct irdma_hmc_info *hmc_info,
+int irdma_prep_remove_sd_bp(struct irdma_hmc_info *hmc_info, u32 idx)
-					       u32 idx)
 {
 	struct irdma_hmc_sd_entry *sd_entry;
 	sd_entry = &hmc_info->sd_table.sd_entry[idx];
 	if (--sd_entry->u.bp.use_cnt)
-		return IRDMA_ERR_NOT_READY;
+		return -EBUSY;
 	hmc_info->sd_table.use_cnt--;
 	sd_entry->valid = false;
  * @hmc_info: pointer to the HMC configuration information structure
  * @idx: segment descriptor index to find the relevant page descriptor
  */
-enum irdma_status_code
+int irdma_prep_remove_pd_page(struct irdma_hmc_info *hmc_info, u32 idx)
-irdma_prep_remove_pd_page(struct irdma_hmc_info *hmc_info, u32 idx)
 {
 	struct irdma_hmc_sd_entry *sd_entry;
 	sd_entry = &hmc_info->sd_table.sd_entry[idx];
 	if (sd_entry->u.pd_table.use_cnt)
-		return IRDMA_ERR_NOT_READY;
+		return -EBUSY;
 	sd_entry->valid = false;
 	hmc_info->sd_table.use_cnt--;

drivers/infiniband/hw/irdma/hmc.h+21−32

@@ -141,40 +141,29 @@ struct irdma_hmc_del_obj_info { · 140 unmodified lines
141	bool privileged;	141	bool privileged;
142	};	142	};
143		143
144	enum irdma_status_code irdma_copy_dma_mem(struct irdma_hw hw, void dest_buf,	144	int irdma_copy_dma_mem(struct irdma_hw hw, void dest_buf,
145	struct irdma_dma_mem *src_mem,	145	struct irdma_dma_mem *src_mem, u64 src_offset, u64 size);
146	u64 src_offset, u64 size);	146	int irdma_sc_create_hmc_obj(struct irdma_sc_dev *dev,
147	enum irdma_status_code	147	struct irdma_hmc_create_obj_info *info);
148	irdma_sc_create_hmc_obj(struct irdma_sc_dev *dev,	148	int irdma_sc_del_hmc_obj(struct irdma_sc_dev *dev,
149	struct irdma_hmc_create_obj_info *info);	149	struct irdma_hmc_del_obj_info *info, bool reset);
150	enum irdma_status_code irdma_sc_del_hmc_obj(struct irdma_sc_dev *dev,	150	int irdma_hmc_sd_one(struct irdma_sc_dev *dev, u8 hmc_fn_id, u64 pa, u32 sd_idx,
151	struct irdma_hmc_del_obj_info *info,	151	enum irdma_sd_entry_type type,
152	bool reset);	152	bool setsd);
153	enum irdma_status_code irdma_hmc_sd_one(struct irdma_sc_dev *dev, u8 hmc_fn_id,	153	int irdma_update_sds_noccq(struct irdma_sc_dev *dev,
154	u64 pa, u32 sd_idx,	154	struct irdma_update_sds_info *info);
155	enum irdma_sd_entry_type type,
156	bool setsd);
157	enum irdma_status_code
158	irdma_update_sds_noccq(struct irdma_sc_dev *dev,
159	struct irdma_update_sds_info *info);
160	struct irdma_vfdev irdma_vfdev_from_fpm(struct irdma_sc_dev dev,	155	struct irdma_vfdev irdma_vfdev_from_fpm(struct irdma_sc_dev dev,
161	u8 hmc_fn_id);	156	u8 hmc_fn_id);
162	struct irdma_hmc_info irdma_vf_hmcinfo_from_fpm(struct irdma_sc_dev dev,	157	struct irdma_hmc_info irdma_vf_hmcinfo_from_fpm(struct irdma_sc_dev dev,
163	u8 hmc_fn_id);	158	u8 hmc_fn_id);
164	enum irdma_status_code irdma_add_sd_table_entry(struct irdma_hw *hw,	159	int irdma_add_sd_table_entry(struct irdma_hw *hw,
165	struct irdma_hmc_info *hmc_info,	160	struct irdma_hmc_info *hmc_info, u32 sd_index,
166	u32 sd_index,	161	enum irdma_sd_entry_type type, u64 direct_mode_sz);
167	enum irdma_sd_entry_type type,	162	int irdma_add_pd_table_entry(struct irdma_sc_dev *dev,
168	u64 direct_mode_sz);	163	struct irdma_hmc_info *hmc_info, u32 pd_index,
169	enum irdma_status_code irdma_add_pd_table_entry(struct irdma_sc_dev *dev,	164	struct irdma_dma_mem *rsrc_pg);
170	struct irdma_hmc_info *hmc_info,	165	int irdma_remove_pd_bp(struct irdma_sc_dev *dev,
171	u32 pd_index,	166	struct irdma_hmc_info *hmc_info, u32 idx);
172	struct irdma_dma_mem *rsrc_pg);	167	int irdma_prep_remove_sd_bp(struct irdma_hmc_info *hmc_info, u32 idx);
173	enum irdma_status_code irdma_remove_pd_bp(struct irdma_sc_dev *dev,	168	int irdma_prep_remove_pd_page(struct irdma_hmc_info *hmc_info, u32 idx);
174	struct irdma_hmc_info *hmc_info,
175	u32 idx);
176	enum irdma_status_code irdma_prep_remove_sd_bp(struct irdma_hmc_info *hmc_info,
177	u32 idx);
178	enum irdma_status_code
179	irdma_prep_remove_pd_page(struct irdma_hmc_info *hmc_info, u32 idx);
180	#endif /* IRDMA_HMC_H */	169	#endif /* IRDMA_HMC_H */

drivers/infiniband/hw/irdma/hw.c+90−102

 				  struct irdma_sc_cq *cq)
 {
 	struct irdma_sc_dev *dev = &rf->sc_dev;
-	enum irdma_status_code status;
 	u32 compl_error;
+	int status;
 	do {
 		status = irdma_puda_poll_cmpl(dev, cq, &compl_error);
-		if (status == IRDMA_ERR_Q_EMPTY)
+		if (status == -ENOENT)
 			break;
 		if (status) {
 			ibdev_dbg(to_ibdev(dev), "ERR: puda status = %d\n", status);
  * Allocate iwdev msix table and copy the msix info to the table
  * Return 0 if successful, otherwise return error
  */
-static enum irdma_status_code irdma_save_msix_info(struct irdma_pci_f *rf)
+static int irdma_save_msix_info(struct irdma_pci_f *rf)
 {
 	struct irdma_qvlist_info *iw_qvlist;
 	struct irdma_qv_info *iw_qvinfo;
 	size_t size;
 	if (!rf->msix_count)
-		return IRDMA_ERR_NO_INTR;
+		return -EINVAL;
 	size = sizeof(struct irdma_msix_vector) * rf->msix_count;
 	size += struct_size(iw_qvlist, qv_info, rf->msix_count);
 	rf->iw_msixtbl = kzalloc(size, GFP_KERNEL);
 	if (!rf->iw_msixtbl)
-		return IRDMA_ERR_NO_MEMORY;
+		return -ENOMEM;
 	rf->iw_qvlist = (struct irdma_qvlist_info *)
 			(&rf->iw_msixtbl[rf->msix_count]);
  */
 static void irdma_destroy_cqp(struct irdma_pci_f *rf, bool free_hwcqp)
 {
-	enum irdma_status_code status = 0;
 	struct irdma_sc_dev *dev = &rf->sc_dev;
 	struct irdma_cqp *cqp = &rf->cqp;
+	int status = 0;
 	if (rf->cqp_cmpl_wq)
 		destroy_workqueue(rf->cqp_cmpl_wq);
  */
 static void irdma_destroy_aeq(struct irdma_pci_f *rf)
 {
-	enum irdma_status_code status = IRDMA_ERR_NOT_READY;
 	struct irdma_sc_dev *dev = &rf->sc_dev;
 	struct irdma_aeq *aeq = &rf->aeq;
+	int status = -EBUSY;
 	if (!rf->msix_shared) {
 		rf->sc_dev.irq_ops->irdma_cfg_aeq(&rf->sc_dev, rf->iw_msixtbl->idx, false);
  */
 static void irdma_destroy_ceq(struct irdma_pci_f *rf, struct irdma_ceq *iwceq)
 {
-	enum irdma_status_code status;
 	struct irdma_sc_dev *dev = &rf->sc_dev;
+	int status;
 	if (rf->reset)
 		goto exit;
 {
 	struct irdma_sc_dev *dev = &rf->sc_dev;
 	struct irdma_ccq *ccq = &rf->ccq;
-	enum irdma_status_code status = 0;
+	int status = 0;
 	if (!rf->reset)
 		status = irdma_sc_ccq_destroy(dev->ccq, 0, true);
  * @dev: hardware control device structure
  * @info: information for the hmc object to create
  */
-static enum irdma_status_code
+static int irdma_create_hmc_obj_type(struct irdma_sc_dev *dev,
-irdma_create_hmc_obj_type(struct irdma_sc_dev *dev,
+				     struct irdma_hmc_create_obj_info *info)
-			  struct irdma_hmc_create_obj_info *info)
 {
 	return irdma_sc_create_hmc_obj(dev, info);
 }
  * Create the device hmc objects and allocate hmc pages
  * Return 0 if successful, otherwise clean up and return error
  */
-static enum irdma_status_code
+static int irdma_create_hmc_objs(struct irdma_pci_f *rf, bool privileged,
-irdma_create_hmc_objs(struct irdma_pci_f *rf, bool privileged, enum irdma_vers vers)
+				 enum irdma_vers vers)
 {
 	struct irdma_sc_dev *dev = &rf->sc_dev;
 	struct irdma_hmc_create_obj_info info = {};
-	enum irdma_status_code status = 0;
+	int i, status = 0;
-	int i;
 	info.hmc_info = dev->hmc_info;
 	info.privileged = privileged;
  * update the memptr to point to the new aligned memory
  * Return 0 if successful, otherwise return no memory error
  */
-static enum irdma_status_code
+static int irdma_obj_aligned_mem(struct irdma_pci_f *rf,
-irdma_obj_aligned_mem(struct irdma_pci_f *rf, struct irdma_dma_mem *memptr,
+				 struct irdma_dma_mem *memptr, u32 size,
-		      u32 size, u32 mask)
+				 u32 mask)
 {
 	unsigned long va, newva;
 	unsigned long extra;
 	memptr->pa = rf->obj_next.pa + extra;
 	memptr->size = size;
 	if (((u8 *)memptr->va + size) > ((u8 *)rf->obj_mem.va + rf->obj_mem.size))
-		return IRDMA_ERR_NO_MEMORY;
+		return -ENOMEM;
 	rf->obj_next.va = (u8 *)memptr->va + size;
 	rf->obj_next.pa = memptr->pa + size;
  * Return 0, if the cqp and all the resources associated with it
  * are successfully created, otherwise return error
  */
-static enum irdma_status_code irdma_create_cqp(struct irdma_pci_f *rf)
+static int irdma_create_cqp(struct irdma_pci_f *rf)
 {
-	enum irdma_status_code status;
 	u32 sqsize = IRDMA_CQP_SW_SQSIZE_2048;
 	struct irdma_dma_mem mem;
 	struct irdma_sc_dev *dev = &rf->sc_dev;
 	struct irdma_cqp_init_info cqp_init_info = {};
 	struct irdma_cqp *cqp = &rf->cqp;
 	u16 maj_err, min_err;
-	int i;
+	int i, status;
 	cqp->cqp_requests = kcalloc(sqsize, sizeof(*cqp->cqp_requests), GFP_KERNEL);
 	if (!cqp->cqp_requests)
-		return IRDMA_ERR_NO_MEMORY;
+		return -ENOMEM;
 	cqp->scratch_array = kcalloc(sqsize, sizeof(*cqp->scratch_array), GFP_KERNEL);
 	if (!cqp->scratch_array) {
 		kfree(cqp->cqp_requests);
-		return IRDMA_ERR_NO_MEMORY;
+		return -ENOMEM;
 	}
 	dev->cqp = &cqp->sc_cqp;
 	if (!cqp->sq.va) {
 		kfree(cqp->scratch_array);
 		kfree(cqp->cqp_requests);
-		return IRDMA_ERR_NO_MEMORY;
+		return -ENOMEM;
 	}
 	status = irdma_obj_aligned_mem(rf, &mem, sizeof(struct irdma_cqp_ctx),
  * Return 0, if the ccq and the resources associated with it
  * are successfully created, otherwise return error
  */
-static enum irdma_status_code irdma_create_ccq(struct irdma_pci_f *rf)
+static int irdma_create_ccq(struct irdma_pci_f *rf)
 {
 	struct irdma_sc_dev *dev = &rf->sc_dev;
-	enum irdma_status_code status;
 	struct irdma_ccq_init_info info = {};
 	struct irdma_ccq *ccq = &rf->ccq;
+	int status;
 	dev->ccq = &ccq->sc_cq;
 	dev->ccq->dev = dev;
 	ccq->mem_cq.va = dma_alloc_coherent(dev->hw->device, ccq->mem_cq.size,
 					    &ccq->mem_cq.pa, GFP_KERNEL);
 	if (!ccq->mem_cq.va)
-		return IRDMA_ERR_NO_MEMORY;
+		return -ENOMEM;
 	status = irdma_obj_aligned_mem(rf, &ccq->shadow_area,
 				       ccq->shadow_area.size,
  * Allocate a mac ip entry and add it to the hw table Return 0
  * if successful, otherwise return error
  */
-static enum irdma_status_code irdma_alloc_set_mac(struct irdma_device *iwdev)
+static int irdma_alloc_set_mac(struct irdma_device *iwdev)
 {
-	enum irdma_status_code status;
+	int status;
 	status = irdma_alloc_local_mac_entry(iwdev->rf,
 					     &iwdev->mac_ip_table_idx);
  * Allocate interrupt resources and enable irq handling
  * Return 0 if successful, otherwise return error
  */
-static enum irdma_status_code
+static int irdma_cfg_ceq_vector(struct irdma_pci_f *rf, struct irdma_ceq *iwceq,
-irdma_cfg_ceq_vector(struct irdma_pci_f *rf, struct irdma_ceq *iwceq,
+				u32 ceq_id, struct irdma_msix_vector *msix_vec)
-		     u32 ceq_id, struct irdma_msix_vector *msix_vec)
 {
 	int status;
 	irq_update_affinity_hint(msix_vec->irq, &msix_vec->mask);
 	if (status) {
 		ibdev_dbg(&rf->iwdev->ibdev, "ERR: ceq irq config fail\n");
-		return IRDMA_ERR_CFG;
+		return status;
 	}
 	msix_vec->ceq_id = ceq_id;
  * Allocate interrupt resources and enable irq handling
  * Return 0 if successful, otherwise return error
  */
-static enum irdma_status_code irdma_cfg_aeq_vector(struct irdma_pci_f *rf)
+static int irdma_cfg_aeq_vector(struct irdma_pci_f *rf)
 {
 	struct irdma_msix_vector *msix_vec = rf->iw_msixtbl;
 	u32 ret = 0;
 	}
 	if (ret) {
 		ibdev_dbg(&rf->iwdev->ibdev, "ERR: aeq irq config fail\n");
-		return IRDMA_ERR_CFG;
+		return -EINVAL;
 	}
 	rf->sc_dev.irq_ops->irdma_cfg_aeq(&rf->sc_dev, msix_vec->idx, true);
  * Return 0, if the ceq and the resources associated with it
  * are successfully created, otherwise return error
  */
-static enum irdma_status_code irdma_create_ceq(struct irdma_pci_f *rf,
+static int irdma_create_ceq(struct irdma_pci_f *rf, struct irdma_ceq *iwceq,
-					       struct irdma_ceq *iwceq,
+			    u32 ceq_id, struct irdma_sc_vsi *vsi)
-					       u32 ceq_id,
-					       struct irdma_sc_vsi *vsi)
 {
-	enum irdma_status_code status;
+	int status;
 	struct irdma_ceq_init_info info = {};
 	struct irdma_sc_dev *dev = &rf->sc_dev;
 	u64 scratch;
 	iwceq->mem.va = dma_alloc_coherent(dev->hw->device, iwceq->mem.size,
 					   &iwceq->mem.pa, GFP_KERNEL);
 	if (!iwceq->mem.va)
-		return IRDMA_ERR_NO_MEMORY;
+		return -ENOMEM;
 	info.ceq_id = ceq_id;
 	info.ceqe_base = iwceq->mem.va;
  * Create the ceq 0 and configure it's msix interrupt vector
  * Return 0, if successfully set up, otherwise return error
  */
-static enum irdma_status_code irdma_setup_ceq_0(struct irdma_pci_f *rf)
+static int irdma_setup_ceq_0(struct irdma_pci_f *rf)
 {
 	struct irdma_ceq *iwceq;
 	struct irdma_msix_vector *msix_vec;
 	u32 i;
-	enum irdma_status_code status = 0;
+	int status = 0;
 	u32 num_ceqs;
 	num_ceqs = min(rf->msix_count, rf->sc_dev.hmc_fpm_misc.max_ceqs);
 	rf->ceqlist = kcalloc(num_ceqs, sizeof(*rf->ceqlist), GFP_KERNEL);
 	if (!rf->ceqlist) {
-		status = IRDMA_ERR_NO_MEMORY;
+		status = -ENOMEM;
 		goto exit;
 	}
  * Create the ceq's and configure their msix interrupt vectors
  * Return 0, if ceqs are successfully set up, otherwise return error
  */
-static enum irdma_status_code irdma_setup_ceqs(struct irdma_pci_f *rf,
+static int irdma_setup_ceqs(struct irdma_pci_f *rf, struct irdma_sc_vsi *vsi)
-					       struct irdma_sc_vsi *vsi)
 {
 	u32 i;
 	u32 ceq_id;
 	struct irdma_ceq *iwceq;
 	struct irdma_msix_vector *msix_vec;
-	enum irdma_status_code status;
+	int status;
 	u32 num_ceqs;
 	num_ceqs = min(rf->msix_count, rf->sc_dev.hmc_fpm_misc.max_ceqs);
 	return status;
 }
-static enum irdma_status_code irdma_create_virt_aeq(struct irdma_pci_f *rf,
+static int irdma_create_virt_aeq(struct irdma_pci_f *rf, u32 size)
-						    u32 size)
 {
-	enum irdma_status_code status = IRDMA_ERR_NO_MEMORY;
 	struct irdma_aeq *aeq = &rf->aeq;
 	dma_addr_t *pg_arr;
 	u32 pg_cnt;
+	int status;
 	if (rf->rdma_ver < IRDMA_GEN_2)
-		return IRDMA_NOT_SUPPORTED;
+		return -EOPNOTSUPP;
 	aeq->mem.size = sizeof(struct irdma_sc_aeqe) * size;
 	aeq->mem.va = vzalloc(aeq->mem.size);
 	if (!aeq->mem.va)
-		return status;
+		return -ENOMEM;
 	pg_cnt = DIV_ROUND_UP(aeq->mem.size, PAGE_SIZE);
 	status = irdma_get_pble(rf->pble_rsrc, &aeq->palloc, pg_cnt, true);
  * Return 0, if the aeq and the resources associated with it
  * are successfully created, otherwise return error
  */
-static enum irdma_status_code irdma_create_aeq(struct irdma_pci_f *rf)
+static int irdma_create_aeq(struct irdma_pci_f *rf)
 {
-	enum irdma_status_code status;
 	struct irdma_aeq_init_info info = {};
 	struct irdma_sc_dev *dev = &rf->sc_dev;
 	struct irdma_aeq *aeq = &rf->aeq;
 	struct irdma_hmc_info *hmc_info = rf->sc_dev.hmc_info;
 	u32 aeq_size;
 	u8 multiplier = (rf->protocol_used == IRDMA_IWARP_PROTOCOL_ONLY) ? 2 : 1;
+	int status;
 	aeq_size = multiplier * hmc_info->hmc_obj[IRDMA_HMC_IW_QP].cnt +
 		   hmc_info->hmc_obj[IRDMA_HMC_IW_CQ].cnt;
  * Create the aeq and configure its msix interrupt vector
  * Return 0 if successful, otherwise return error
  */
-static enum irdma_status_code irdma_setup_aeq(struct irdma_pci_f *rf)
+static int irdma_setup_aeq(struct irdma_pci_f *rf)
 {
 	struct irdma_sc_dev *dev = &rf->sc_dev;
-	enum irdma_status_code status;
+	int status;
 	status = irdma_create_aeq(rf);
 	if (status)
  *
  * Return 0 if successful, otherwise return error
  */
-static enum irdma_status_code irdma_initialize_ilq(struct irdma_device *iwdev)
+static int irdma_initialize_ilq(struct irdma_device *iwdev)
 {
 	struct irdma_puda_rsrc_info info = {};
-	enum irdma_status_code status;
+	int status;
 	info.type = IRDMA_PUDA_RSRC_TYPE_ILQ;
 	info.cq_id = 1;
  *
  * Return 0 if successful, otherwise return error
  */
-static enum irdma_status_code irdma_initialize_ieq(struct irdma_device *iwdev)
+static int irdma_initialize_ieq(struct irdma_device *iwdev)
 {
 	struct irdma_puda_rsrc_info info = {};
-	enum irdma_status_code status;
+	int status;
 	info.type = IRDMA_PUDA_RSRC_TYPE_IEQ;
 	info.cq_id = 2;
  * the hmc objects and create the objects
  * Return 0 if successful, otherwise return error
  */
-static enum irdma_status_code irdma_hmc_setup(struct irdma_pci_f *rf)
+static int irdma_hmc_setup(struct irdma_pci_f *rf)
 {
-	enum irdma_status_code status;
+	int status;
 	u32 qpcnt;
 	if (rf->rdma_ver == IRDMA_GEN_1)
  * Return 0 if successful, otherwise clean up the resources
  * and return error
  */
-static enum irdma_status_code irdma_initialize_dev(struct irdma_pci_f *rf)
+static int irdma_initialize_dev(struct irdma_pci_f *rf)
 {
-	enum irdma_status_code status;
+	int status;
 	struct irdma_sc_dev *dev = &rf->sc_dev;
 	struct irdma_device_init_info info = {};
 	struct irdma_dma_mem mem;
 	rf->hmc_info_mem = kzalloc(size, GFP_KERNEL);
 	if (!rf->hmc_info_mem)
-		return IRDMA_ERR_NO_MEMORY;
+		return -ENOMEM;
 	rf->pble_rsrc = (struct irdma_hmc_pble_rsrc *)rf->hmc_info_mem;
 	dev->hmc_info = &rf->hw.hmc;
 	info.fpm_commit_buf = mem.va;
 	info.bar0 = rf->hw.hw_addr;
-	info.hmc_fn_id = PCI_FUNC(rf->pcidev->devfn);
+	info.hmc_fn_id = rf->pf_id;
 	info.hw = &rf->hw;
 	status = irdma_sc_dev_init(rf->rdma_ver, &rf->sc_dev, &info);
 	if (status)
 		destroy_workqueue(iwdev->cleanup_wq);
 }
-static enum irdma_status_code irdma_setup_init_state(struct irdma_pci_f *rf)
+static int irdma_setup_init_state(struct irdma_pci_f *rf)
 {
-	enum irdma_status_code status;
+	int status;
 	status = irdma_save_msix_info(rf);
 	if (status)
 	rf->obj_mem.va = dma_alloc_coherent(rf->hw.device, rf->obj_mem.size,
 					    &rf->obj_mem.pa, GFP_KERNEL);
 	if (!rf->obj_mem.va) {
-		status = IRDMA_ERR_NO_MEMORY;
+		status = -ENOMEM;
 		goto clean_msixtbl;
 	}
  * Create device queues ILQ, IEQ, CEQs and PBLEs. Setup irdma
  * device resource objects.
  */
-enum irdma_status_code irdma_rt_init_hw(struct irdma_device *iwdev,
+int irdma_rt_init_hw(struct irdma_device *iwdev,
-					struct irdma_l2params *l2params)
+		     struct irdma_l2params *l2params)
 {
 	struct irdma_pci_f *rf = iwdev->rf;
 	struct irdma_sc_dev *dev = &rf->sc_dev;
-	enum irdma_status_code status;
 	struct irdma_vsi_init_info vsi_info = {};
 	struct irdma_vsi_stats_info stats_info = {};
+	int status;
 	vsi_info.dev = dev;
 	vsi_info.back_vsi = iwdev;
 	stats_info.pestat = kzalloc(sizeof(*stats_info.pestat), GFP_KERNEL);
 	if (!stats_info.pestat) {
 		irdma_cleanup_cm_core(&iwdev->cm_core);
-		return IRDMA_ERR_NO_MEMORY;
+		return -ENOMEM;
 	}
 	stats_info.fcn_id = dev->hmc_fn_id;
 	status = irdma_vsi_stats_init(&iwdev->vsi, &stats_info);
 		iwdev->cleanup_wq = alloc_workqueue("irdma-cleanup-wq",
 					WQ_UNBOUND, WQ_UNBOUND_MAX_ACTIVE);
 		if (!iwdev->cleanup_wq)
-			return IRDMA_ERR_NO_MEMORY;
+			return -ENOMEM;
 		irdma_get_used_rsrc(iwdev);
 		init_waitqueue_head(&iwdev->suspend_wq);
  *
  * Create admin queues, HMC obejcts and RF resource objects
  */
-enum irdma_status_code irdma_ctrl_init_hw(struct irdma_pci_f *rf)
+int irdma_ctrl_init_hw(struct irdma_pci_f *rf)
 {
 	struct irdma_sc_dev *dev = &rf->sc_dev;
-	enum irdma_status_code status;
+	int status;
 	do {
 		status = irdma_setup_init_state(rf);
 		if (status)
 		rf->cqp_cmpl_wq = alloc_ordered_workqueue("cqp_cmpl_wq",
 						WQ_HIGHPRI | WQ_UNBOUND);
 		if (!rf->cqp_cmpl_wq) {
-			status = IRDMA_ERR_NO_MEMORY;
+			status = -ENOMEM;
 			break;
 		}
 		INIT_WORK(&rf->cqp_cmpl_work, cqp_compl_worker);
 	struct irdma_cqp *iwcqp = &rf->cqp;
 	struct irdma_cqp_request *cqp_request;
 	struct cqp_cmds_info *cqp_info;
-	enum irdma_status_code status;
+	int status;
 	cqp_request = irdma_alloc_and_get_cqp_request(iwcqp, true);
 	if (!cqp_request)
-		return IRDMA_ERR_NO_MEMORY;
+		return -ENOMEM;
 	cqp_info = &cqp_request->info;
 	cqp_info->post_sq = 1;
 	struct irdma_cqp *iwcqp = &rf->cqp;
 	struct irdma_cqp_request *cqp_request;
 	struct cqp_cmds_info *cqp_info;
-	enum irdma_status_code status = 0;
+	int status = 0;
 	cqp_request = irdma_alloc_and_get_cqp_request(iwcqp, true);
 	if (!cqp_request)
-		return IRDMA_ERR_NO_MEMORY;
+		return -ENOMEM;
 	cqp_info = &cqp_request->info;
 	cqp_info->cqp_cmd = IRDMA_OP_ALLOC_LOCAL_MAC_ENTRY;
  * @accel_local_port: port for apbvt
  * @add_port: add ordelete port
  */
-static enum irdma_status_code
+static int irdma_cqp_manage_apbvt_cmd(struct irdma_device *iwdev,
-irdma_cqp_manage_apbvt_cmd(struct irdma_device *iwdev, u16 accel_local_port,
+				      u16 accel_local_port, bool add_port)
-			   bool add_port)
 {
 	struct irdma_apbvt_info *info;
 	struct irdma_cqp_request *cqp_request;
 	struct cqp_cmds_info *cqp_info;
-	enum irdma_status_code status;
+	int status;
 	cqp_request = irdma_alloc_and_get_cqp_request(&iwdev->rf->cqp, add_port);
 	if (!cqp_request)
-		return IRDMA_ERR_NO_MEMORY;
+		return -ENOMEM;
 	cqp_info = &cqp_request->info;
 	info = &cqp_info->in.u.manage_apbvt_entry.info;
  * @cmnode: cmnode associated with connection
  * @wait: wait for completion
  */
-enum irdma_status_code
+int irdma_manage_qhash(struct irdma_device *iwdev, struct irdma_cm_info *cminfo,
-irdma_manage_qhash(struct irdma_device *iwdev, struct irdma_cm_info *cminfo,
+		       enum irdma_quad_entry_type etype,
-		   enum irdma_quad_entry_type etype,
+		       enum irdma_quad_hash_manage_type mtype, void *cmnode,
-		   enum irdma_quad_hash_manage_type mtype, void *cmnode,
+		       bool wait)
-		   bool wait)
 {
 	struct irdma_qhash_table_info *info;
-	enum irdma_status_code status;
 	struct irdma_cqp *iwcqp = &iwdev->rf->cqp;
 	struct irdma_cqp_request *cqp_request;
 	struct cqp_cmds_info *cqp_info;
 	struct irdma_cm_node *cm_node = cmnode;
+	int status;
 	cqp_request = irdma_alloc_and_get_cqp_request(iwcqp, wait);
 	if (!cqp_request)
-		return IRDMA_ERR_NO_MEMORY;
+		return -ENOMEM;
 	cqp_info = &cqp_request->info;
 	info = &cqp_info->in.u.manage_qhash_table_entry.info;
  * @info: info for flush
  * @wait: flag wait for completion
  */
-enum irdma_status_code irdma_hw_flush_wqes(struct irdma_pci_f *rf,
+int irdma_hw_flush_wqes(struct irdma_pci_f *rf, struct irdma_sc_qp *qp,
-					   struct irdma_sc_qp *qp,
+			struct irdma_qp_flush_info *info, bool wait)
-					   struct irdma_qp_flush_info *info,
-					   bool wait)
 {
-	enum irdma_status_code status;
+	int status;
 	struct irdma_qp_flush_info *hw_info;
 	struct irdma_cqp_request *cqp_request;
 	struct cqp_cmds_info *cqp_info;
 	cqp_request = irdma_alloc_and_get_cqp_request(&rf->cqp, wait);
 	if (!cqp_request)
-		return IRDMA_ERR_NO_MEMORY;
+		return -ENOMEM;
 	cqp_info = &cqp_request->info;
 	if (!wait)
 				info->sq = true;
 				new_req = irdma_alloc_and_get_cqp_request(&rf->cqp, true);
 				if (!new_req) {
-					status = IRDMA_ERR_NO_MEMORY;
+					status = -ENOMEM;
 					goto put_cqp;
 				}
 				cqp_info = &new_req->info;

drivers/infiniband/hw/irdma/i40iw_hw.c+0−1

@@ -3,7 +3,6 @@ · 2 unmodified lines
3	#include "osdep.h"	3	#include "osdep.h"
4	#include "type.h"	4	#include "type.h"
5	#include "i40iw_hw.h"	5	#include "i40iw_hw.h"
6	#include "status.h"
7	#include "protos.h"	6	#include "protos.h"
8		7
9	static u32 i40iw_regs[IRDMA_MAX_REGS] = {	8	static u32 i40iw_regs[IRDMA_MAX_REGS] = {

drivers/infiniband/hw/irdma/i40iw_if.c+2−1

 	rf->rdma_ver = IRDMA_GEN_1;
 	rf->gen_ops.request_reset = i40iw_request_reset;
 	rf->pcidev = cdev_info->pcidev;
+	rf->pf_id = cdev_info->fid;
 	rf->hw.hw_addr = cdev_info->hw_addr;
 	rf->cdev = cdev_info;
 	rf->msix_count = cdev_info->msix_count;
 		if (last_qset == IRDMA_NO_QSET)
 			last_qset = qset;
 		else if ((qset != last_qset) && (qset != IRDMA_NO_QSET))
-			iwdev->dcb = true;
+			iwdev->dcb_vlan_mode = true;
 	}
 	if (irdma_rt_init_hw(iwdev, &l2params)) {

drivers/infiniband/hw/irdma/main.c+18−11

@@ -79,6 +79,10 @@ static void irdma_fill_qos_info(struct irdma_l2params *l2params, · 78 unmodified lines
79	}	79	}
80	for (i = 0; i < IIDC_MAX_USER_PRIORITY; i++)	80	for (i = 0; i < IIDC_MAX_USER_PRIORITY; i++)
81	l2params->up2tc[i] = qos_info->up2tc[i];	81	l2params->up2tc[i] = qos_info->up2tc[i];
		82	if (qos_info->pfc_mode == IIDC_DSCP_PFC_MODE) {
		83	l2params->dscp_mode = true;
		84	memcpy(l2params->dscp_map, qos_info->dscp_map, sizeof(l2params->dscp_map));
		85	}
82	}	86	}
83		87
84	static void irdma_iidc_event_handler(struct ice_pf pf, struct iidc_event event)	88	static void irdma_iidc_event_handler(struct ice_pf pf, struct iidc_event event)
@@ -108,8 +112,9 @@ static void irdma_iidc_event_handler(struct ice_pf pf, struct iidc_event event · 23 unmodified lines
108	l2params.tc_changed = true;	112	l2params.tc_changed = true;
109	ibdev_dbg(&iwdev->ibdev, "CLNT: TC Change\n");	113	ibdev_dbg(&iwdev->ibdev, "CLNT: TC Change\n");
110	ice_get_qos_params(pf, &qos_info);	114	ice_get_qos_params(pf, &qos_info);
111	iwdev->dcb = qos_info.num_tc > 1;
112	irdma_fill_qos_info(&l2params, &qos_info);	115	irdma_fill_qos_info(&l2params, &qos_info);
		116	if (iwdev->rf->protocol_used != IRDMA_IWARP_PROTOCOL_ONLY)
		117	iwdev->dcb_vlan_mode = qos_info.num_tc > 1 && !l2params.dscp_mode;
113	irdma_change_l2params(&iwdev->vsi, &l2params);	118	irdma_change_l2params(&iwdev->vsi, &l2params);
114	} else if (*event->type & BIT(IIDC_EVENT_CRIT_ERR)) {	119	} else if (*event->type & BIT(IIDC_EVENT_CRIT_ERR)) {
115	ibdev_warn(&iwdev->ibdev, "ICE OICR event notification: oicr = 0x%08x\n",	120	ibdev_warn(&iwdev->ibdev, "ICE OICR event notification: oicr = 0x%08x\n",
@@ -157,8 +162,8 @@ static void irdma_request_reset(struct irdma_pci_f *rf) · 41 unmodified lines
157	* @vsi: vsi structure	162	* @vsi: vsi structure
158	* @tc_node: Traffic class node	163	* @tc_node: Traffic class node
159	*/	164	*/
160	static enum irdma_status_code irdma_lan_register_qset(struct irdma_sc_vsi *vsi,	165	static int irdma_lan_register_qset(struct irdma_sc_vsi *vsi,
161	struct irdma_ws_node *tc_node)	166	struct irdma_ws_node *tc_node)
162	{	167	{
163	struct irdma_device *iwdev = vsi->back_vsi;	168	struct irdma_device *iwdev = vsi->back_vsi;
164	struct ice_pf *pf = iwdev->rf->cdev;	169	struct ice_pf *pf = iwdev->rf->cdev;
@@ -171,7 +176,7 @@ static enum irdma_status_code irdma_lan_register_qset(struct irdma_sc_vsi *vsi, · 6 unmodified lines
171	ret = ice_add_rdma_qset(pf, &qset);	176	ret = ice_add_rdma_qset(pf, &qset);
172	if (ret) {	177	if (ret) {
173	ibdev_dbg(&iwdev->ibdev, "WS: LAN alloc_res for rdma qset failed.\n");	178	ibdev_dbg(&iwdev->ibdev, "WS: LAN alloc_res for rdma qset failed.\n");
174	return IRDMA_ERR_REG_QSET;	179	return ret;
175	}	180	}
176		181
177	tc_node->l2_sched_node_id = qset.teid;	182	tc_node->l2_sched_node_id = qset.teid;
@@ -226,6 +231,7 @@ static void irdma_fill_device_info(struct irdma_device iwdev, struct ice_pf pf · 48 unmodified lines
226	rf->hw.hw_addr = pf->hw.hw_addr;	231	rf->hw.hw_addr = pf->hw.hw_addr;
227	rf->pcidev = pf->pdev;	232	rf->pcidev = pf->pdev;
228	rf->msix_count = pf->num_rdma_msix;	233	rf->msix_count = pf->num_rdma_msix;
		234	rf->pf_id = pf->hw.pf_id;
229	rf->msix_entries = &pf->msix_entries[pf->rdma_base_vector];	235	rf->msix_entries = &pf->msix_entries[pf->rdma_base_vector];
230	rf->default_vsi.vsi_idx = vsi->vsi_num;	236	rf->default_vsi.vsi_idx = vsi->vsi_num;
231	rf->protocol_used = pf->rdma_mode & IIDC_RDMA_PROTOCOL_ROCEV2 ?	237	rf->protocol_used = pf->rdma_mode & IIDC_RDMA_PROTOCOL_ROCEV2 ?
@@ -236,7 +242,7 @@ static void irdma_fill_device_info(struct irdma_device iwdev, struct ice_pf pf · 4 unmodified lines
236	rf->gen_ops.request_reset = irdma_request_reset;	242	rf->gen_ops.request_reset = irdma_request_reset;
237	rf->limits_sel = 7;	243	rf->limits_sel = 7;
238	rf->iwdev = iwdev;	244	rf->iwdev = iwdev;
239		245	mutex_init(&iwdev->ah_tbl_lock);
240	iwdev->netdev = vsi->netdev;	246	iwdev->netdev = vsi->netdev;
241	iwdev->vsi_num = vsi->vsi_num;	247	iwdev->vsi_num = vsi->vsi_num;
242	iwdev->init_state = INITIAL_STATE;	248	iwdev->init_state = INITIAL_STATE;
@@ -275,18 +281,19 @@ static int irdma_probe(struct auxiliary_device *aux_dev, const struct auxiliary_ · 32 unmodified lines
275	irdma_fill_device_info(iwdev, pf, vsi);	281	irdma_fill_device_info(iwdev, pf, vsi);
276	rf = iwdev->rf;	282	rf = iwdev->rf;
277		283
278	if (irdma_ctrl_init_hw(rf)) {	284	err = irdma_ctrl_init_hw(rf);
279	err = -EIO;	285	if (err)
280	goto err_ctrl_init;	286	goto err_ctrl_init;
281	}
282		287
283	l2params.mtu = iwdev->netdev->mtu;	288	l2params.mtu = iwdev->netdev->mtu;
284	ice_get_qos_params(pf, &qos_info);	289	ice_get_qos_params(pf, &qos_info);
285	irdma_fill_qos_info(&l2params, &qos_info);	290	irdma_fill_qos_info(&l2params, &qos_info);
286	if (irdma_rt_init_hw(iwdev, &l2params)) {	291	if (iwdev->rf->protocol_used != IRDMA_IWARP_PROTOCOL_ONLY)
287	err = -EIO;	292	iwdev->dcb_vlan_mode = l2params.num_tc > 1 && !l2params.dscp_mode;
		293
		294	err = irdma_rt_init_hw(iwdev, &l2params);
		295	if (err)
288	goto err_rt_init;	296	goto err_rt_init;
289	}
290		297
291	err = irdma_ib_register_device(iwdev);	298	err = irdma_ib_register_device(iwdev);
292	if (err)	299	if (err)

drivers/infiniband/hw/irdma/main.h+21−26

 #include <rdma/ib_umem.h>
 #include <rdma/ib_cache.h>
 #include <rdma/uverbs_ioctl.h>
-#include "status.h"
 #include "osdep.h"
 #include "defs.h"
 #include "hmc.h"
 struct irdma_gen_ops {
 	void (*request_reset)(struct irdma_pci_f *rf);
-	enum irdma_status_code (*register_qset)(struct irdma_sc_vsi *vsi,
+	int (*register_qset)(struct irdma_sc_vsi *vsi,
-						struct irdma_ws_node *tc_node);
+			     struct irdma_ws_node *tc_node);
 	void (*unregister_qset)(struct irdma_sc_vsi *vsi,
 				struct irdma_ws_node *tc_node);
 };
 	u8 *mem_rsrc;
 	u8 rdma_ver;
 	u8 rst_to;
+	u8 pf_id;
 	enum irdma_protocol_used protocol_used;
 	u32 sd_type;
 	u32 msix_count;
 	struct workqueue_struct *cleanup_wq;
 	struct irdma_sc_vsi vsi;
 	struct irdma_cm_core cm_core;
+	DECLARE_HASHTABLE(ah_hash_tbl, 8);
+	struct mutex ah_tbl_lock; /* protect AH hash table access */
 	u32 roce_cwnd;
 	u32 roce_ackcreds;
 	u32 vendor_id;
 	u8 iw_status;
 	bool roce_mode:1;
 	bool roce_dcqcn_en:1;
-	bool dcb:1;
+	bool dcb_vlan_mode:1;
 	bool iw_ooo:1;
 	enum init_completion_state init_state;
 	spin_unlock_irqrestore(&rf->rsrc_lock, flags);
 }
-enum irdma_status_code irdma_ctrl_init_hw(struct irdma_pci_f *rf);
+int irdma_ctrl_init_hw(struct irdma_pci_f *rf);
 void irdma_ctrl_deinit_hw(struct irdma_pci_f *rf);
-enum irdma_status_code irdma_rt_init_hw(struct irdma_device *iwdev,
+int irdma_rt_init_hw(struct irdma_device *iwdev,
-					struct irdma_l2params *l2params);
+		     struct irdma_l2params *l2params);
 void irdma_rt_deinit_hw(struct irdma_device *iwdev);
 void irdma_qp_add_ref(struct ib_qp *ibqp);
 void irdma_qp_rem_ref(struct ib_qp *ibqp);
 bool irdma_cqp_crit_err(struct irdma_sc_dev *dev, u8 cqp_cmd,
 			u16 maj_err_code, u16 min_err_code);
-enum irdma_status_code
+int irdma_handle_cqp_op(struct irdma_pci_f *rf,
-irdma_handle_cqp_op(struct irdma_pci_f *rf,
+			struct irdma_cqp_request *cqp_request);
-		    struct irdma_cqp_request *cqp_request);
 int irdma_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr, int attr_mask,
 		    struct ib_udata *udata);
 void irdma_cq_wq_destroy(struct irdma_pci_f *rf, struct irdma_sc_cq *cq);
 void irdma_cleanup_pending_cqp_op(struct irdma_pci_f *rf);
-enum irdma_status_code irdma_hw_modify_qp(struct irdma_device *iwdev,
+int irdma_hw_modify_qp(struct irdma_device *iwdev, struct irdma_qp *iwqp,
-					  struct irdma_qp *iwqp,
+		       struct irdma_modify_qp_info *info, bool wait);
-					  struct irdma_modify_qp_info *info,
+int irdma_qp_suspend_resume(struct irdma_sc_qp *qp, bool suspend);
-					  bool wait);
+int irdma_manage_qhash(struct irdma_device *iwdev, struct irdma_cm_info *cminfo,
-enum irdma_status_code irdma_qp_suspend_resume(struct irdma_sc_qp *qp,
+		       enum irdma_quad_entry_type etype,
-					       bool suspend);
+		       enum irdma_quad_hash_manage_type mtype, void *cmnode,
-enum irdma_status_code
+		       bool wait);
-irdma_manage_qhash(struct irdma_device *iwdev, struct irdma_cm_info *cminfo,
-		   enum irdma_quad_entry_type etype,
-		   enum irdma_quad_hash_manage_type mtype, void *cmnode,
-		   bool wait);
 void irdma_receive_ilq(struct irdma_sc_vsi *vsi, struct irdma_puda_buf *rbuf);
 void irdma_free_sqbuf(struct irdma_sc_vsi *vsi, void *bufp);
 void irdma_free_qp_rsrc(struct irdma_qp *iwqp);
-enum irdma_status_code irdma_setup_cm_core(struct irdma_device *iwdev, u8 ver);
+int irdma_setup_cm_core(struct irdma_device *iwdev, u8 ver);
 void irdma_cleanup_cm_core(struct irdma_cm_core *cm_core);
 void irdma_next_iw_state(struct irdma_qp *iwqp, u8 state, u8 del_hash, u8 term,
 			 u8 term_len);
 struct irdma_cm_node *irdma_find_node(struct irdma_cm_core *cm_core,
 				      u16 rem_port, u32 *rem_addr, u16 loc_port,
 				      u32 *loc_addr, u16 vlan_id);
-enum irdma_status_code irdma_hw_flush_wqes(struct irdma_pci_f *rf,
+int irdma_hw_flush_wqes(struct irdma_pci_f *rf, struct irdma_sc_qp *qp,
-					   struct irdma_sc_qp *qp,
+			struct irdma_qp_flush_info *info, bool wait);
-					   struct irdma_qp_flush_info *info,
-					   bool wait);
 void irdma_gen_ae(struct irdma_pci_f *rf, struct irdma_sc_qp *qp,
 		  struct irdma_gen_ae_info *info, bool wait);
 void irdma_copy_ip_ntohl(u32 *dst, __be32 *src);

drivers/infiniband/hw/irdma/osdep.h+19−22

@@ -5,6 +5,7 @@ · 4 unmodified lines
5		5
6	#include <linux/pci.h>	6	#include <linux/pci.h>
7	#include <linux/bitfield.h>	7	#include <linux/bitfield.h>
		8	#include <linux/net/intel/iidc.h>
8	#include <crypto/hash.h>	9	#include <crypto/hash.h>
9	#include <rdma/ib_verbs.h>	10	#include <rdma/ib_verbs.h>
10		11
@@ -42,32 +43,28 @@ enum irdma_status_code irdma_vf_wait_vchnl_resp(struct irdma_sc_dev *dev); · 31 unmodified lines
42	bool irdma_vf_clear_to_send(struct irdma_sc_dev *dev);	43	bool irdma_vf_clear_to_send(struct irdma_sc_dev *dev);
43	void irdma_add_dev_ref(struct irdma_sc_dev *dev);	44	void irdma_add_dev_ref(struct irdma_sc_dev *dev);
44	void irdma_put_dev_ref(struct irdma_sc_dev *dev);	45	void irdma_put_dev_ref(struct irdma_sc_dev *dev);
45	enum irdma_status_code irdma_ieq_check_mpacrc(struct shash_desc *desc,	46	int irdma_ieq_check_mpacrc(struct shash_desc desc, void addr, u32 len,
46	void *addr, u32 len, u32 val);	47	u32 val);
47	struct irdma_sc_qp irdma_ieq_get_qp(struct irdma_sc_dev dev,	48	struct irdma_sc_qp irdma_ieq_get_qp(struct irdma_sc_dev dev,
48	struct irdma_puda_buf *buf);	49	struct irdma_puda_buf *buf);
49	void irdma_send_ieq_ack(struct irdma_sc_qp *qp);	50	void irdma_send_ieq_ack(struct irdma_sc_qp *qp);
50	void irdma_ieq_update_tcpip_info(struct irdma_puda_buf *buf, u16 len,	51	void irdma_ieq_update_tcpip_info(struct irdma_puda_buf *buf, u16 len,
51	u32 seqnum);	52	u32 seqnum);
52	void irdma_free_hash_desc(struct shash_desc *hash_desc);	53	void irdma_free_hash_desc(struct shash_desc *hash_desc);
53	enum irdma_status_code irdma_init_hash_desc(struct shash_desc **hash_desc);	54	int irdma_init_hash_desc(struct shash_desc **hash_desc);
54	enum irdma_status_code	55	int irdma_puda_get_tcpip_info(struct irdma_puda_cmpl_info *info,
55	irdma_puda_get_tcpip_info(struct irdma_puda_cmpl_info *info,	56	struct irdma_puda_buf *buf);
56	struct irdma_puda_buf *buf);	57	int irdma_cqp_sds_cmd(struct irdma_sc_dev *dev,
57	enum irdma_status_code irdma_cqp_sds_cmd(struct irdma_sc_dev *dev,	58	struct irdma_update_sds_info *info);
58	struct irdma_update_sds_info *info);	59	int irdma_cqp_manage_hmc_fcn_cmd(struct irdma_sc_dev *dev,
59	enum irdma_status_code	60	struct irdma_hmc_fcn_info *hmcfcninfo,
60	irdma_cqp_manage_hmc_fcn_cmd(struct irdma_sc_dev *dev,	61	u16 *pmf_idx);
61	struct irdma_hmc_fcn_info *hmcfcninfo,	62	int irdma_cqp_query_fpm_val_cmd(struct irdma_sc_dev *dev,
62	u16 *pmf_idx);	63	struct irdma_dma_mem *val_mem, u8 hmc_fn_id);
63	enum irdma_status_code	64	int irdma_cqp_commit_fpm_val_cmd(struct irdma_sc_dev *dev,
64	irdma_cqp_query_fpm_val_cmd(struct irdma_sc_dev *dev,	65	struct irdma_dma_mem *val_mem, u8 hmc_fn_id);
65	struct irdma_dma_mem *val_mem, u8 hmc_fn_id);	66	int irdma_alloc_query_fpm_buf(struct irdma_sc_dev *dev,
66	enum irdma_status_code	67	struct irdma_dma_mem *mem);
67	irdma_cqp_commit_fpm_val_cmd(struct irdma_sc_dev *dev,
68	struct irdma_dma_mem *val_mem, u8 hmc_fn_id);
69	enum irdma_status_code irdma_alloc_query_fpm_buf(struct irdma_sc_dev *dev,
70	struct irdma_dma_mem *mem);
71	void irdma_remove_cqp_head(struct irdma_sc_dev dev);	68	void irdma_remove_cqp_head(struct irdma_sc_dev dev);
72	void irdma_term_modify_qp(struct irdma_sc_qp *qp, u8 next_state, u8 term,	69	void irdma_term_modify_qp(struct irdma_sc_qp *qp, u8 next_state, u8 term,
73	u8 term_len);	70	u8 term_len);
@@ -79,7 +76,7 @@ void irdma_hw_stats_stop_timer(struct irdma_sc_vsi *vsi); · 5 unmodified lines
79	void wr32(struct irdma_hw *hw, u32 reg, u32 val);	76	void wr32(struct irdma_hw *hw, u32 reg, u32 val);
80	u32 rd32(struct irdma_hw *hw, u32 reg);	77	u32 rd32(struct irdma_hw *hw, u32 reg);
81	u64 rd64(struct irdma_hw *hw, u32 reg);	78	u64 rd64(struct irdma_hw *hw, u32 reg);
82	enum irdma_status_code irdma_map_vm_page_list(struct irdma_hw hw, void va,	79	int irdma_map_vm_page_list(struct irdma_hw hw, void va, dma_addr_t *pg_dma,
83	dma_addr_t *pg_dma, u32 pg_cnt);	80	u32 pg_cnt);
84	void irdma_unmap_vm_page_list(struct irdma_hw hw, dma_addr_t pg_dma, u32 pg_cnt);	81	void irdma_unmap_vm_page_list(struct irdma_hw hw, dma_addr_t pg_dma, u32 pg_cnt);
85	#endif /* IRDMA_OSDEP_H */	82	#endif /* IRDMA_OSDEP_H */

drivers/infiniband/hw/irdma/pble.c+34−43

 // SPDX-License-Identifier: GPL-2.0 or Linux-OpenIB
 /* Copyright (c) 2015 - 2021 Intel Corporation */
 #include "osdep.h"
-#include "status.h"
 #include "hmc.h"
 #include "defs.h"
 #include "type.h"
 #include "protos.h"
 #include "pble.h"
-static enum irdma_status_code
+static int add_pble_prm(struct irdma_hmc_pble_rsrc *pble_rsrc);
-add_pble_prm(struct irdma_hmc_pble_rsrc *pble_rsrc);
 /**
  * irdma_destroy_pble_prm - destroy prm during module unload
  * @dev: irdma_sc_dev struct
  * @pble_rsrc: pble resources
  */
-enum irdma_status_code
+int irdma_hmc_init_pble(struct irdma_sc_dev *dev,
-irdma_hmc_init_pble(struct irdma_sc_dev *dev,
+			struct irdma_hmc_pble_rsrc *pble_rsrc)
-		    struct irdma_hmc_pble_rsrc *pble_rsrc)
 {
 	struct irdma_hmc_info *hmc_info;
 	u32 fpm_idx = 0;
-	enum irdma_status_code status = 0;
+	int status = 0;
 	hmc_info = dev->hmc_info;
 	pble_rsrc->dev = dev;
 	INIT_LIST_HEAD(&pble_rsrc->pinfo.clist);
 	if (add_pble_prm(pble_rsrc)) {
 		irdma_destroy_pble_prm(pble_rsrc);
-		status = IRDMA_ERR_NO_MEMORY;
+		status = -ENOMEM;
 	}
 	return status;
  * @pble_rsrc: pble resource ptr
  * @info: page info for sd
  */
-static enum irdma_status_code
+static int add_sd_direct(struct irdma_hmc_pble_rsrc *pble_rsrc,
-add_sd_direct(struct irdma_hmc_pble_rsrc *pble_rsrc,
+			 struct irdma_add_page_info *info)
-	      struct irdma_add_page_info *info)
 {
 	struct irdma_sc_dev *dev = pble_rsrc->dev;
-	enum irdma_status_code ret_code = 0;
+	int ret_code = 0;
 	struct sd_pd_idx *idx = &info->idx;
 	struct irdma_chunk *chunk = info->chunk;
 	struct irdma_hmc_info *hmc_info = info->hmc_info;
  * @pble_rsrc: pble resource management
  * @info: page info for sd
  */
-static enum irdma_status_code
+static int add_bp_pages(struct irdma_hmc_pble_rsrc *pble_rsrc,
-add_bp_pages(struct irdma_hmc_pble_rsrc *pble_rsrc,
+			struct irdma_add_page_info *info)
-	     struct irdma_add_page_info *info)
 {
 	struct irdma_sc_dev *dev = pble_rsrc->dev;
 	u8 *addr;
 	struct irdma_hmc_sd_entry *sd_entry = info->sd_entry;
 	struct irdma_hmc_info *hmc_info = info->hmc_info;
 	struct irdma_chunk *chunk = info->chunk;
-	enum irdma_status_code status = 0;
+	int status = 0;
 	u32 rel_pd_idx = info->idx.rel_pd_idx;
 	u32 pd_idx = info->idx.pd_idx;
 	u32 i;
 	if (irdma_pble_get_paged_mem(chunk, info->pages))
-		return IRDMA_ERR_NO_MEMORY;
+		return -ENOMEM;
 	status = irdma_add_sd_table_entry(dev->hw, hmc_info, info->idx.sd_idx,
 					  IRDMA_SD_TYPE_PAGED,
  * add_pble_prm - add a sd entry for pble resoure
  * @pble_rsrc: pble resource management
  */
-static enum irdma_status_code
+static int add_pble_prm(struct irdma_hmc_pble_rsrc *pble_rsrc)
-add_pble_prm(struct irdma_hmc_pble_rsrc *pble_rsrc)
 {
 	struct irdma_sc_dev *dev = pble_rsrc->dev;
 	struct irdma_hmc_sd_entry *sd_entry;
 	struct irdma_chunk *chunk;
 	struct irdma_add_page_info info;
 	struct sd_pd_idx *idx = &info.idx;
-	enum irdma_status_code ret_code = 0;
+	int ret_code = 0;
 	enum irdma_sd_entry_type sd_entry_type;
 	u64 sd_reg_val = 0;
 	struct irdma_virt_mem chunkmem;
 	u32 pages;
 	if (pble_rsrc->unallocated_pble < PBLE_PER_PAGE)
-		return IRDMA_ERR_NO_MEMORY;
+		return -ENOMEM;
 	if (pble_rsrc->next_fpm_addr & 0xfff)
-		return IRDMA_ERR_INVALID_PAGE_DESC_INDEX;
+		return -EINVAL;
 	chunkmem.size = sizeof(*chunk);
 	chunkmem.va = kzalloc(chunkmem.size, GFP_KERNEL);
 	if (!chunkmem.va)
-		return IRDMA_ERR_NO_MEMORY;
+		return -ENOMEM;
 	chunk = chunkmem.va;
 	chunk->chunkmem = chunkmem;
  * @pble_rsrc: pble resource management
  * @palloc: level 2 pble allocation
  */
-static enum irdma_status_code
+static int get_lvl2_pble(struct irdma_hmc_pble_rsrc *pble_rsrc,
-get_lvl2_pble(struct irdma_hmc_pble_rsrc *pble_rsrc,
+			 struct irdma_pble_alloc *palloc)
-	      struct irdma_pble_alloc *palloc)
 {
 	u32 lf4k, lflast, total, i;
 	u32 pblcnt = PBLE_PER_PAGE;
 	struct irdma_pble_level2 *lvl2 = &palloc->level2;
 	struct irdma_pble_info *root = &lvl2->root;
 	struct irdma_pble_info *leaf;
-	enum irdma_status_code ret_code;
+	int ret_code;
 	u64 fpm_addr;
 	/* number of full 512 (4K) leafs) */
 	lvl2->leafmem.size = (sizeof(*leaf) * total);
 	lvl2->leafmem.va = kzalloc(lvl2->leafmem.size, GFP_KERNEL);
 	if (!lvl2->leafmem.va)
-		return IRDMA_ERR_NO_MEMORY;
+		return -ENOMEM;
 	lvl2->leaf = lvl2->leafmem.va;
 	leaf = lvl2->leaf;
 	if (ret_code) {
 		kfree(lvl2->leafmem.va);
 		lvl2->leaf = NULL;
-		return IRDMA_ERR_NO_MEMORY;
+		return -ENOMEM;
 	}
 	root->idx = fpm_to_idx(pble_rsrc, fpm_addr);
 error:
 	free_lvl2(pble_rsrc, palloc);
-	return IRDMA_ERR_NO_MEMORY;
+	return -ENOMEM;
 }
 /**
  * @pble_rsrc: pble resource management
  * @palloc: level 1 pble allocation
  */
-static enum irdma_status_code
+static int get_lvl1_pble(struct irdma_hmc_pble_rsrc *pble_rsrc,
-get_lvl1_pble(struct irdma_hmc_pble_rsrc *pble_rsrc,
+			 struct irdma_pble_alloc *palloc)
-	      struct irdma_pble_alloc *palloc)
 {
-	enum irdma_status_code ret_code;
+	int ret_code;
 	u64 fpm_addr;
 	struct irdma_pble_info *lvl1 = &palloc->level1;
 				       palloc->total_cnt << 3, &lvl1->addr,
 				       &fpm_addr);
 	if (ret_code)
-		return IRDMA_ERR_NO_MEMORY;
+		return -ENOMEM;
 	palloc->level = PBLE_LEVEL_1;
 	lvl1->idx = fpm_to_idx(pble_rsrc, fpm_addr);
  * @palloc: contains all inforamtion regarding pble (idx + pble addr)
  * @level1_only: flag for a level 1 PBLE
  */
-static enum irdma_status_code
+static int get_lvl1_lvl2_pble(struct irdma_hmc_pble_rsrc *pble_rsrc,
-get_lvl1_lvl2_pble(struct irdma_hmc_pble_rsrc *pble_rsrc,
+			      struct irdma_pble_alloc *palloc, bool level1_only)
-		   struct irdma_pble_alloc *palloc, bool level1_only)
 {
-	enum irdma_status_code status = 0;
+	int status = 0;
 	status = get_lvl1_pble(pble_rsrc, palloc);
 	if (!status || level1_only || palloc->total_cnt <= PBLE_PER_PAGE)
  * @pble_cnt: #of pbles requested
  * @level1_only: true if only pble level 1 to acquire
  */
-enum irdma_status_code irdma_get_pble(struct irdma_hmc_pble_rsrc *pble_rsrc,
+int irdma_get_pble(struct irdma_hmc_pble_rsrc *pble_rsrc,
-				      struct irdma_pble_alloc *palloc,
+		   struct irdma_pble_alloc *palloc, u32 pble_cnt,
-				      u32 pble_cnt, bool level1_only)
+		   bool level1_only)
 {
-	enum irdma_status_code status = 0;
+	int status = 0;
 	int max_sds = 0;
 	int i;

drivers/infiniband/hw/irdma/pble.h+11−14

@@ -108,20 +108,18 @@ struct irdma_hmc_pble_rsrc { · 107 unmodified lines
108	};	108	};
109		109
110	void irdma_destroy_pble_prm(struct irdma_hmc_pble_rsrc *pble_rsrc);	110	void irdma_destroy_pble_prm(struct irdma_hmc_pble_rsrc *pble_rsrc);
111	enum irdma_status_code	111	int irdma_hmc_init_pble(struct irdma_sc_dev *dev,
112	irdma_hmc_init_pble(struct irdma_sc_dev *dev,	112	struct irdma_hmc_pble_rsrc *pble_rsrc);
113	struct irdma_hmc_pble_rsrc *pble_rsrc);
114	void irdma_free_pble(struct irdma_hmc_pble_rsrc *pble_rsrc,	113	void irdma_free_pble(struct irdma_hmc_pble_rsrc *pble_rsrc,
115	struct irdma_pble_alloc *palloc);	114	struct irdma_pble_alloc *palloc);
116	enum irdma_status_code irdma_get_pble(struct irdma_hmc_pble_rsrc *pble_rsrc,	115	int irdma_get_pble(struct irdma_hmc_pble_rsrc *pble_rsrc,
117	struct irdma_pble_alloc *palloc,	116	struct irdma_pble_alloc *palloc, u32 pble_cnt,
118	u32 pble_cnt, bool level1_only);	117	bool level1_only);
119	enum irdma_status_code irdma_prm_add_pble_mem(struct irdma_pble_prm *pprm,	118	int irdma_prm_add_pble_mem(struct irdma_pble_prm *pprm,
120	struct irdma_chunk *pchunk);	119	struct irdma_chunk *pchunk);
121	enum irdma_status_code	120	int irdma_prm_get_pbles(struct irdma_pble_prm *pprm,
122	irdma_prm_get_pbles(struct irdma_pble_prm *pprm,	121	struct irdma_pble_chunkinfo *chunkinfo, u64 mem_size,
123	struct irdma_pble_chunkinfo *chunkinfo, u64 mem_size,	122	u64 *vaddr, u64 fpm_addr);
124	u64 *vaddr, u64 fpm_addr);
125	void irdma_prm_return_pbles(struct irdma_pble_prm *pprm,	123	void irdma_prm_return_pbles(struct irdma_pble_prm *pprm,
126	struct irdma_pble_chunkinfo *chunkinfo);	124	struct irdma_pble_chunkinfo *chunkinfo);
127	void irdma_pble_acquire_lock(struct irdma_hmc_pble_rsrc *pble_rsrc,	125	void irdma_pble_acquire_lock(struct irdma_hmc_pble_rsrc *pble_rsrc,
@@ -129,7 +127,6 @@ void irdma_pble_acquire_lock(struct irdma_hmc_pble_rsrc *pble_rsrc, · 1 unmodified line
129	void irdma_pble_release_lock(struct irdma_hmc_pble_rsrc *pble_rsrc,	127	void irdma_pble_release_lock(struct irdma_hmc_pble_rsrc *pble_rsrc,
130	unsigned long *flags);	128	unsigned long *flags);
131	void irdma_pble_free_paged_mem(struct irdma_chunk *chunk);	129	void irdma_pble_free_paged_mem(struct irdma_chunk *chunk);
132	enum irdma_status_code irdma_pble_get_paged_mem(struct irdma_chunk *chunk,	130	int irdma_pble_get_paged_mem(struct irdma_chunk *chunk, u32 pg_cnt);
133	u32 pg_cnt);
134	void irdma_prm_rem_bitmapmem(struct irdma_hw hw, struct irdma_chunk chunk);	131	void irdma_prm_rem_bitmapmem(struct irdma_hw hw, struct irdma_chunk chunk);
135	#endif /* IRDMA_PBLE_H */	132	#endif /* IRDMA_PBLE_H */

drivers/infiniband/hw/irdma/protos.h+39−51

@@ -12,58 +12,51 @@ · 11 unmodified lines
12	#define CQP_TIMEOUT_THRESHOLD 500	12	#define CQP_TIMEOUT_THRESHOLD 500
13		13
14	/* init operations */	14	/* init operations */
15	enum irdma_status_code irdma_sc_dev_init(enum irdma_vers ver,	15	int irdma_sc_dev_init(enum irdma_vers ver, struct irdma_sc_dev *dev,
16	struct irdma_sc_dev *dev,	16	struct irdma_device_init_info *info);
17	struct irdma_device_init_info *info);
18	void irdma_sc_rt_init(struct irdma_sc_dev *dev);	17	void irdma_sc_rt_init(struct irdma_sc_dev *dev);
19	void irdma_sc_cqp_post_sq(struct irdma_sc_cqp *cqp);	18	void irdma_sc_cqp_post_sq(struct irdma_sc_cqp *cqp);
20	__le64 irdma_sc_cqp_get_next_send_wqe(struct irdma_sc_cqp cqp, u64 scratch);	19	__le64 irdma_sc_cqp_get_next_send_wqe(struct irdma_sc_cqp cqp, u64 scratch);
21	enum irdma_status_code	20	int irdma_sc_mr_fast_register(struct irdma_sc_qp *qp,
22	irdma_sc_mr_fast_register(struct irdma_sc_qp *qp,	21	struct irdma_fast_reg_stag_info *info,
23	struct irdma_fast_reg_stag_info *info, bool post_sq);	22	bool post_sq);
24	/* HMC/FPM functions */	23	/* HMC/FPM functions */
25	enum irdma_status_code irdma_sc_init_iw_hmc(struct irdma_sc_dev *dev,	24	int irdma_sc_init_iw_hmc(struct irdma_sc_dev *dev, u8 hmc_fn_id);
26	u8 hmc_fn_id);
27	/* stats misc */	25	/* stats misc */
28	enum irdma_status_code	26	int irdma_cqp_gather_stats_cmd(struct irdma_sc_dev *dev,
29	irdma_cqp_gather_stats_cmd(struct irdma_sc_dev *dev,	27	struct irdma_vsi_pestat *pestat, bool wait);
30	struct irdma_vsi_pestat *pestat, bool wait);
31	void irdma_cqp_gather_stats_gen1(struct irdma_sc_dev *dev,	28	void irdma_cqp_gather_stats_gen1(struct irdma_sc_dev *dev,
32	struct irdma_vsi_pestat *pestat);	29	struct irdma_vsi_pestat *pestat);
33	void irdma_hw_stats_read_all(struct irdma_vsi_pestat *stats,	30	void irdma_hw_stats_read_all(struct irdma_vsi_pestat *stats,
34	struct irdma_dev_hw_stats *stats_values,	31	struct irdma_dev_hw_stats *stats_values,
35	u64 hw_stats_regs_32, u64 hw_stats_regs_64,	32	u64 hw_stats_regs_32, u64 hw_stats_regs_64,
36	u8 hw_rev);	33	u8 hw_rev);
37	enum irdma_status_code	34	int irdma_cqp_ws_node_cmd(struct irdma_sc_dev *dev, u8 cmd,
38	irdma_cqp_ws_node_cmd(struct irdma_sc_dev *dev, u8 cmd,	35	struct irdma_ws_node_info *node_info);
39	struct irdma_ws_node_info *node_info);	36	int irdma_cqp_ceq_cmd(struct irdma_sc_dev dev, struct irdma_sc_ceq sc_ceq,
40	enum irdma_status_code irdma_cqp_ceq_cmd(struct irdma_sc_dev *dev,	37	u8 op);
41	struct irdma_sc_ceq *sc_ceq, u8 op);	38	int irdma_cqp_aeq_cmd(struct irdma_sc_dev dev, struct irdma_sc_aeq sc_aeq,
42	enum irdma_status_code irdma_cqp_aeq_cmd(struct irdma_sc_dev *dev,	39	u8 op);
43	struct irdma_sc_aeq *sc_aeq, u8 op);	40	int irdma_cqp_stats_inst_cmd(struct irdma_sc_vsi *vsi, u8 cmd,
44	enum irdma_status_code	41	struct irdma_stats_inst_info *stats_info);
45	irdma_cqp_stats_inst_cmd(struct irdma_sc_vsi *vsi, u8 cmd,
46	struct irdma_stats_inst_info *stats_info);
47	u16 irdma_alloc_ws_node_id(struct irdma_sc_dev *dev);	42	u16 irdma_alloc_ws_node_id(struct irdma_sc_dev *dev);
48	void irdma_free_ws_node_id(struct irdma_sc_dev *dev, u16 node_id);	43	void irdma_free_ws_node_id(struct irdma_sc_dev *dev, u16 node_id);
49	void irdma_update_stats(struct irdma_dev_hw_stats *hw_stats,	44	void irdma_update_stats(struct irdma_dev_hw_stats *hw_stats,
50	struct irdma_gather_stats *gather_stats,	45	struct irdma_gather_stats *gather_stats,
51	struct irdma_gather_stats *last_gather_stats);	46	struct irdma_gather_stats *last_gather_stats);
52	/* vsi functions */	47	/* vsi functions */
53	enum irdma_status_code irdma_vsi_stats_init(struct irdma_sc_vsi *vsi,	48	int irdma_vsi_stats_init(struct irdma_sc_vsi *vsi,
54	struct irdma_vsi_stats_info *info);	49	struct irdma_vsi_stats_info *info);
55	void irdma_vsi_stats_free(struct irdma_sc_vsi *vsi);	50	void irdma_vsi_stats_free(struct irdma_sc_vsi *vsi);
56	void irdma_sc_vsi_init(struct irdma_sc_vsi *vsi,	51	void irdma_sc_vsi_init(struct irdma_sc_vsi *vsi,
57	struct irdma_vsi_init_info *info);	52	struct irdma_vsi_init_info *info);
58	enum irdma_status_code irdma_sc_add_cq_ctx(struct irdma_sc_ceq *ceq,	53	int irdma_sc_add_cq_ctx(struct irdma_sc_ceq ceq, struct irdma_sc_cq cq);
59	struct irdma_sc_cq *cq);
60	void irdma_sc_remove_cq_ctx(struct irdma_sc_ceq ceq, struct irdma_sc_cq cq);	54	void irdma_sc_remove_cq_ctx(struct irdma_sc_ceq ceq, struct irdma_sc_cq cq);
61	/* misc L2 param change functions */	55	/* misc L2 param change functions */
62	void irdma_change_l2params(struct irdma_sc_vsi *vsi,	56	void irdma_change_l2params(struct irdma_sc_vsi *vsi,
63	struct irdma_l2params *l2params);	57	struct irdma_l2params *l2params);
64	void irdma_sc_suspend_resume_qps(struct irdma_sc_vsi *vsi, u8 suspend);	58	void irdma_sc_suspend_resume_qps(struct irdma_sc_vsi *vsi, u8 suspend);
65	enum irdma_status_code irdma_cqp_qp_suspend_resume(struct irdma_sc_qp *qp,	59	int irdma_cqp_qp_suspend_resume(struct irdma_sc_qp *qp, u8 cmd);
66	u8 cmd);
67	void irdma_qp_add_qos(struct irdma_sc_qp *qp);	60	void irdma_qp_add_qos(struct irdma_sc_qp *qp);
68	void irdma_qp_rem_qos(struct irdma_sc_qp *qp);	61	void irdma_qp_rem_qos(struct irdma_sc_qp *qp);
69	struct irdma_sc_qp irdma_get_qp_from_list(struct list_head head,	62	struct irdma_sc_qp irdma_get_qp_from_list(struct list_head head,
@@ -81,31 +74,26 @@ void irdma_terminate_received(struct irdma_sc_qp *qp, · 11 unmodified lines
81	/* misc */	74	/* misc */
82	u8 irdma_get_encoded_wqe_size(u32 wqsize, enum irdma_queue_type queue_type);	75	u8 irdma_get_encoded_wqe_size(u32 wqsize, enum irdma_queue_type queue_type);
83	void irdma_modify_qp_to_err(struct irdma_sc_qp *sc_qp);	76	void irdma_modify_qp_to_err(struct irdma_sc_qp *sc_qp);
84	enum irdma_status_code	77	int irdma_sc_static_hmc_pages_allocated(struct irdma_sc_cqp *cqp, u64 scratch,
85	irdma_sc_static_hmc_pages_allocated(struct irdma_sc_cqp *cqp, u64 scratch,	78	u8 hmc_fn_id, bool post_sq,
86	u8 hmc_fn_id, bool post_sq,	79	bool poll_registers);
87	bool poll_registers);	80	int irdma_cfg_fpm_val(struct irdma_sc_dev *dev, u32 qp_count);
88	enum irdma_status_code irdma_cfg_fpm_val(struct irdma_sc_dev *dev,	81	int irdma_get_rdma_features(struct irdma_sc_dev *dev);
89	u32 qp_count);
90	enum irdma_status_code irdma_get_rdma_features(struct irdma_sc_dev *dev);
91	void free_sd_mem(struct irdma_sc_dev *dev);	82	void free_sd_mem(struct irdma_sc_dev *dev);
92	enum irdma_status_code irdma_process_cqp_cmd(struct irdma_sc_dev *dev,	83	int irdma_process_cqp_cmd(struct irdma_sc_dev *dev,
93	struct cqp_cmds_info *pcmdinfo);	84	struct cqp_cmds_info *pcmdinfo);
94	enum irdma_status_code irdma_process_bh(struct irdma_sc_dev *dev);	85	int irdma_process_bh(struct irdma_sc_dev *dev);
95	enum irdma_status_code irdma_cqp_sds_cmd(struct irdma_sc_dev *dev,	86	int irdma_cqp_sds_cmd(struct irdma_sc_dev *dev,
96	struct irdma_update_sds_info *info);	87	struct irdma_update_sds_info *info);
97	enum irdma_status_code	88	int irdma_cqp_query_fpm_val_cmd(struct irdma_sc_dev *dev,
98	irdma_cqp_query_fpm_val_cmd(struct irdma_sc_dev *dev,	89	struct irdma_dma_mem *val_mem, u8 hmc_fn_id);
99	struct irdma_dma_mem *val_mem, u8 hmc_fn_id);	90	int irdma_cqp_commit_fpm_val_cmd(struct irdma_sc_dev *dev,
100	enum irdma_status_code	91	struct irdma_dma_mem *val_mem, u8 hmc_fn_id);
101	irdma_cqp_commit_fpm_val_cmd(struct irdma_sc_dev *dev,	92	int irdma_alloc_query_fpm_buf(struct irdma_sc_dev *dev,
102	struct irdma_dma_mem *val_mem, u8 hmc_fn_id);	93	struct irdma_dma_mem *mem);
103	enum irdma_status_code irdma_alloc_query_fpm_buf(struct irdma_sc_dev *dev,	94	int irdma_cqp_manage_hmc_fcn_cmd(struct irdma_sc_dev *dev,
104	struct irdma_dma_mem *mem);	95	struct irdma_hmc_fcn_info *hmcfcninfo,
105	enum irdma_status_code	96	u16 *pmf_idx);
106	irdma_cqp_manage_hmc_fcn_cmd(struct irdma_sc_dev *dev,
107	struct irdma_hmc_fcn_info *hmcfcninfo,
108	u16 *pmf_idx);
109	void irdma_add_dev_ref(struct irdma_sc_dev *dev);	97	void irdma_add_dev_ref(struct irdma_sc_dev *dev);
110	void irdma_put_dev_ref(struct irdma_sc_dev *dev);	98	void irdma_put_dev_ref(struct irdma_sc_dev *dev);
111	void irdma_remove_cqp_head(struct irdma_sc_dev dev);	99	void irdma_remove_cqp_head(struct irdma_sc_dev dev);

drivers/infiniband/hw/irdma/puda.c+62−70

 // SPDX-License-Identifier: GPL-2.0 or Linux-OpenIB
 /* Copyright (c) 2015 - 2021 Intel Corporation */
 #include "osdep.h"
-#include "status.h"
 #include "hmc.h"
 #include "defs.h"
 #include "type.h"
  * @rsrc: resource to use for buffer
  * @initial: flag if during init time
  */
-static enum irdma_status_code
+static int irdma_puda_replenish_rq(struct irdma_puda_rsrc *rsrc, bool initial)
-irdma_puda_replenish_rq(struct irdma_puda_rsrc *rsrc, bool initial)
 {
 	u32 i;
 	u32 invalid_cnt = rsrc->rxq_invalid_cnt;
 	for (i = 0; i < invalid_cnt; i++) {
 		buf = irdma_puda_get_bufpool(rsrc);
 		if (!buf)
-			return IRDMA_ERR_list_empty;
+			return -ENOBUFS;
 		irdma_puda_post_recvbuf(rsrc, rsrc->rx_wqe_idx, buf, initial);
 		rsrc->rx_wqe_idx = ((rsrc->rx_wqe_idx + 1) % rsrc->rq_size);
 		rsrc->rxq_invalid_cnt--;
 					    u32 *wqe_idx)
 {
 	__le64 *wqe = NULL;
-	enum irdma_status_code ret_code = 0;
+	int ret_code = 0;
 	*wqe_idx = IRDMA_RING_CURRENT_HEAD(qp->sq_ring);
 	if (!*wqe_idx)
  * @cq: cq for poll
  * @info: info return for successful completion
  */
-static enum irdma_status_code
+static int irdma_puda_poll_info(struct irdma_sc_cq *cq,
-irdma_puda_poll_info(struct irdma_sc_cq *cq, struct irdma_puda_cmpl_info *info)
+				struct irdma_puda_cmpl_info *info)
 {
 	struct irdma_cq_uk *cq_uk = &cq->cq_uk;
 	u64 qword0, qword2, qword3, qword6;
 	get_64bit_val(cqe, 24, &qword3);
 	valid_bit = (bool)FIELD_GET(IRDMA_CQ_VALID, qword3);
 	if (valid_bit != cq_uk->polarity)
-		return IRDMA_ERR_Q_EMPTY;
+		return -ENOENT;
 	if (cq->dev->hw_attrs.uk_attrs.hw_rev >= IRDMA_GEN_2)
 		ext_valid = (bool)FIELD_GET(IRDMA_CQ_EXTCQE, qword3);
 		if (!peek_head)
 			polarity ^= 1;
 		if (polarity != cq_uk->polarity)
-			return IRDMA_ERR_Q_EMPTY;
+			return -ENOENT;
 		IRDMA_RING_MOVE_HEAD_NOCHECK(cq_uk->cq_ring);
 		if (!IRDMA_RING_CURRENT_HEAD(cq_uk->cq_ring))
 		major_err = (u32)(FIELD_GET(IRDMA_CQ_MAJERR, qword3));
 		minor_err = (u32)(FIELD_GET(IRDMA_CQ_MINERR, qword3));
 		info->compl_error = major_err << 16 | minor_err;
-		return IRDMA_ERR_CQ_COMPL_ERROR;
+		return -EIO;
 	}
 	get_64bit_val(cqe, 0, &qword0);
  * @cq: cq getting interrupt
  * @compl_err: return any completion err
  */
-enum irdma_status_code irdma_puda_poll_cmpl(struct irdma_sc_dev *dev,
+int irdma_puda_poll_cmpl(struct irdma_sc_dev *dev, struct irdma_sc_cq *cq,
-					    struct irdma_sc_cq *cq,
+			 u32 *compl_err)
-					    u32 *compl_err)
 {
 	struct irdma_qp_uk *qp;
 	struct irdma_cq_uk *cq_uk = &cq->cq_uk;
 	struct irdma_puda_cmpl_info info = {};
-	enum irdma_status_code ret = 0;
+	int ret = 0;
 	struct irdma_puda_buf *buf;
 	struct irdma_puda_rsrc *rsrc;
 	u8 cq_type = cq->cq_type;
 							cq->vsi->ieq;
 	} else {
 		ibdev_dbg(to_ibdev(dev), "PUDA: qp_type error\n");
-		return IRDMA_ERR_BAD_PTR;
+		return -EINVAL;
 	}
 	ret = irdma_puda_poll_info(cq, &info);
 	*compl_err = info.compl_error;
-	if (ret == IRDMA_ERR_Q_EMPTY)
+	if (ret == -ENOENT)
 		return ret;
 	if (ret)
 		goto done;
 	qp = info.qp;
 	if (!qp || !rsrc) {
-		ret = IRDMA_ERR_BAD_PTR;
+		ret = -EFAULT;
 		goto done;
 	}
 	if (qp->qp_id != rsrc->qp_id) {
-		ret = IRDMA_ERR_BAD_PTR;
+		ret = -EFAULT;
 		goto done;
 	}
  * @qp: puda qp for send
  * @info: buffer information for transmit
  */
-enum irdma_status_code irdma_puda_send(struct irdma_sc_qp *qp,
+int irdma_puda_send(struct irdma_sc_qp *qp, struct irdma_puda_send_info *info)
-				       struct irdma_puda_send_info *info)
 {
 	__le64 *wqe;
 	u32 iplen, l4len;
 	wqe = irdma_puda_get_next_send_wqe(&qp->qp_uk, &wqe_idx);
 	if (!wqe)
-		return IRDMA_ERR_QP_TOOMANY_WRS_POSTED;
+		return -ENOMEM;
 	qp->qp_uk.sq_wrtrk_array[wqe_idx].wrid = (uintptr_t)info->scratch;
 	/* Third line of WQE descriptor */
 			 struct irdma_puda_buf *buf)
 {
 	struct irdma_puda_send_info info;
-	enum irdma_status_code ret = 0;
+	int ret = 0;
 	unsigned long flags;
 	spin_lock_irqsave(&rsrc->bufpool_lock, flags);
  * @dev: Device
  * @qp: Resource qp
  */
-static enum irdma_status_code irdma_puda_qp_wqe(struct irdma_sc_dev *dev,
+static int irdma_puda_qp_wqe(struct irdma_sc_dev *dev, struct irdma_sc_qp *qp)
-						struct irdma_sc_qp *qp)
 {
 	struct irdma_sc_cqp *cqp;
 	__le64 *wqe;
 	u64 hdr;
 	struct irdma_ccq_cqe_info compl_info;
-	enum irdma_status_code status = 0;
+	int status = 0;
 	cqp = dev->cqp;
 	wqe = irdma_sc_cqp_get_next_send_wqe(cqp, 0);
 	if (!wqe)
-		return IRDMA_ERR_RING_FULL;
+		return -ENOMEM;
 	set_64bit_val(wqe, 16, qp->hw_host_ctx_pa);
 	set_64bit_val(wqe, 40, qp->shadow_area_pa);
  * irdma_puda_qp_create - create qp for resource
  * @rsrc: resource to use for buffer
  */
-static enum irdma_status_code irdma_puda_qp_create(struct irdma_puda_rsrc *rsrc)
+static int irdma_puda_qp_create(struct irdma_puda_rsrc *rsrc)
 {
 	struct irdma_sc_qp *qp = &rsrc->qp;
 	struct irdma_qp_uk *ukqp = &qp->qp_uk;
-	enum irdma_status_code ret = 0;
+	int ret = 0;
 	u32 sq_size, rq_size;
 	struct irdma_dma_mem *mem;
 					    rsrc->qpmem.size, &rsrc->qpmem.pa,
 					    GFP_KERNEL);
 	if (!rsrc->qpmem.va)
-		return IRDMA_ERR_NO_MEMORY;
+		return -ENOMEM;
 	mem = &rsrc->qpmem;
 	memset(mem->va, 0, rsrc->qpmem.size);
  * @dev: Device
  * @cq: resource for cq
  */
-static enum irdma_status_code irdma_puda_cq_wqe(struct irdma_sc_dev *dev,
+static int irdma_puda_cq_wqe(struct irdma_sc_dev *dev, struct irdma_sc_cq *cq)
-						struct irdma_sc_cq *cq)
 {
 	__le64 *wqe;
 	struct irdma_sc_cqp *cqp;
 	u64 hdr;
 	struct irdma_ccq_cqe_info compl_info;
-	enum irdma_status_code status = 0;
+	int status = 0;
 	cqp = dev->cqp;
 	wqe = irdma_sc_cqp_get_next_send_wqe(cqp, 0);
 	if (!wqe)
-		return IRDMA_ERR_RING_FULL;
+		return -ENOMEM;
 	set_64bit_val(wqe, 0, cq->cq_uk.cq_size);
 	set_64bit_val(wqe, 8, (uintptr_t)cq >> 1);
  * irdma_puda_cq_create - create cq for resource
  * @rsrc: resource for which cq to create
  */
-static enum irdma_status_code irdma_puda_cq_create(struct irdma_puda_rsrc *rsrc)
+static int irdma_puda_cq_create(struct irdma_puda_rsrc *rsrc)
 {
 	struct irdma_sc_dev *dev = rsrc->dev;
 	struct irdma_sc_cq *cq = &rsrc->cq;
-	enum irdma_status_code ret = 0;
+	int ret = 0;
 	u32 cqsize;
 	struct irdma_dma_mem *mem;
 	struct irdma_cq_init_info info = {};
 	rsrc->cqmem.va = dma_alloc_coherent(dev->hw->device, rsrc->cqmem.size,
 					    &rsrc->cqmem.pa, GFP_KERNEL);
 	if (!rsrc->cqmem.va)
-		return IRDMA_ERR_NO_MEMORY;
+		return -ENOMEM;
 	mem = &rsrc->cqmem;
 	info.dev = dev;
  */
 static void irdma_puda_free_qp(struct irdma_puda_rsrc *rsrc)
 {
-	enum irdma_status_code ret;
+	int ret;
 	struct irdma_ccq_cqe_info compl_info;
 	struct irdma_sc_dev *dev = rsrc->dev;
  */
 static void irdma_puda_free_cq(struct irdma_puda_rsrc *rsrc)
 {
-	enum irdma_status_code ret;
+	int ret;
 	struct irdma_ccq_cqe_info compl_info;
 	struct irdma_sc_dev *dev = rsrc->dev;
  * @rsrc: resource for buffer allocation
  * @count: number of buffers to create
  */
-static enum irdma_status_code irdma_puda_allocbufs(struct irdma_puda_rsrc *rsrc,
+static int irdma_puda_allocbufs(struct irdma_puda_rsrc *rsrc, u32 count)
-						   u32 count)
 {
 	u32 i;
 	struct irdma_puda_buf *buf;
 		buf = irdma_puda_alloc_buf(rsrc->dev, rsrc->buf_size);
 		if (!buf) {
 			rsrc->stats_buf_alloc_fail++;
-			return IRDMA_ERR_NO_MEMORY;
+			return -ENOMEM;
 		}
 		irdma_puda_ret_bufpool(rsrc, buf);
 		rsrc->alloc_buf_count++;
  * @vsi: sc VSI struct
  * @info: resource information
  */
-enum irdma_status_code irdma_puda_create_rsrc(struct irdma_sc_vsi *vsi,
+int irdma_puda_create_rsrc(struct irdma_sc_vsi *vsi,
-					      struct irdma_puda_rsrc_info *info)
+			   struct irdma_puda_rsrc_info *info)
 {
 	struct irdma_sc_dev *dev = vsi->dev;
-	enum irdma_status_code ret = 0;
+	int ret = 0;
 	struct irdma_puda_rsrc *rsrc;
 	u32 pudasize;
 	u32 sqwridsize, rqwridsize;
 		vmem = &vsi->ieq_mem;
 		break;
 	default:
-		return IRDMA_NOT_SUPPORTED;
+		return -EOPNOTSUPP;
 	}
 	vmem->size = pudasize + sqwridsize + rqwridsize;
 	vmem->va = kzalloc(vmem->size, GFP_KERNEL);
 	if (!vmem->va)
-		return IRDMA_ERR_NO_MEMORY;
+		return -ENOMEM;
 	rsrc = vmem->va;
 	spin_lock_init(&rsrc->bufpool_lock);
 		rsrc->xmit_complete = irdma_ieq_tx_compl;
 		break;
 	default:
-		return IRDMA_NOT_SUPPORTED;
+		return -EOPNOTSUPP;
 	}
 	rsrc->type = info->type;
  * @buf: first receive buffer
  * @fpdu_len: total length of fpdu
  */
-static enum irdma_status_code
+static int irdma_ieq_create_pbufl(struct irdma_pfpdu *pfpdu,
-irdma_ieq_create_pbufl(struct irdma_pfpdu *pfpdu, struct list_head *rxlist,
+				  struct list_head *rxlist,
-		       struct list_head *pbufl, struct irdma_puda_buf *buf,
+				  struct list_head *pbufl,
-		       u16 fpdu_len)
+				  struct irdma_puda_buf *buf, u16 fpdu_len)
 {
-	enum irdma_status_code status = 0;
+	int status = 0;
 	struct irdma_puda_buf *nextbuf;
 	u32 nextseqnum;
 	u16 plen = fpdu_len - buf->datalen;
 	do {
 		nextbuf = irdma_puda_get_listbuf(rxlist);
 		if (!nextbuf) {
-			status = IRDMA_ERR_list_empty;
+			status = -ENOBUFS;
 			break;
 		}
 		list_add_tail(&nextbuf->list, pbufl);
 		if (nextbuf->seqnum != nextseqnum) {
 			pfpdu->bad_seq_num++;
-			status = IRDMA_ERR_SEQ_NUM;
+			status = -ERANGE;
 			break;
 		}
 		if (nextbuf->datalen >= plen) {
  * @buf: receive buffer
  * @fpdu_len: fpdu len in the buffer
  */
-static enum irdma_status_code
+static int irdma_ieq_handle_partial(struct irdma_puda_rsrc *ieq,
-irdma_ieq_handle_partial(struct irdma_puda_rsrc *ieq, struct irdma_pfpdu *pfpdu,
+				    struct irdma_pfpdu *pfpdu,
-			 struct irdma_puda_buf *buf, u16 fpdu_len)
+				    struct irdma_puda_buf *buf, u16 fpdu_len)
 {
-	enum irdma_status_code status = 0;
+	int status = 0;
 	u8 *crcptr;
 	u32 mpacrc;
 	u32 seqnum = buf->seqnum;
 	txbuf = irdma_puda_get_bufpool(ieq);
 	if (!txbuf) {
 		pfpdu->no_tx_bufs++;
-		status = IRDMA_ERR_NO_TXBUFS;
+		status = -ENOBUFS;
 		goto error;
 	}
  * @pfpdu: partial management per user qp
  * @buf: receive buffer
  */
-static enum irdma_status_code irdma_ieq_process_buf(struct irdma_puda_rsrc *ieq,
+static int irdma_ieq_process_buf(struct irdma_puda_rsrc *ieq,
-						    struct irdma_pfpdu *pfpdu,
+				 struct irdma_pfpdu *pfpdu,
-						    struct irdma_puda_buf *buf)
+				 struct irdma_puda_buf *buf)
 {
 	u16 fpdu_len = 0;
 	u16 datalen = buf->datalen;
 	bool partial = false;
 	struct irdma_puda_buf *txbuf;
 	struct list_head *rxlist = &pfpdu->rxlist;
-	enum irdma_status_code ret = 0;
+	int ret = 0;
 	ioffset = (u16)(buf->data - (u8 *)buf->mem.va);
 	while (datalen) {
 			ibdev_dbg(to_ibdev(ieq->dev),
 				  "IEQ: error bad fpdu len\n");
 			list_add(&buf->list, rxlist);
-			return IRDMA_ERR_MPA_CRC;
+			return -EINVAL;
 		}
 		if (datalen < fpdu_len) {
 			list_add(&buf->list, rxlist);
 			ibdev_dbg(to_ibdev(ieq->dev),
 				  "ERR: IRDMA_ERR_MPA_CRC\n");
-			return IRDMA_ERR_MPA_CRC;
+			return -EINVAL;
 		}
 		full++;
 		pfpdu->fpdu_processed++;
 		if (!txbuf) {
 			pfpdu->no_tx_bufs++;
 			list_add(&buf->list, rxlist);
-			return IRDMA_ERR_NO_TXBUFS;
+			return -ENOBUFS;
 		}
 		/* modify txbuf's buffer header */
 		irdma_ieq_setup_tx_buf(buf, txbuf);
 	struct irdma_pfpdu *pfpdu = &qp->pfpdu;
 	struct list_head *rxlist = &pfpdu->rxlist;
 	struct irdma_puda_buf *buf;
-	enum irdma_status_code status;
+	int status;
 	do {
 		if (list_empty(rxlist))
 		}
 		/* keep processing buffers from the head of the list */
 		status = irdma_ieq_process_buf(ieq, pfpdu, buf);
-		if (status == IRDMA_ERR_MPA_CRC) {
+		if (status == -EINVAL) {
 			pfpdu->mpa_crc_err = true;
 			while (!list_empty(rxlist)) {
 				buf = irdma_puda_get_listbuf(rxlist);
  * @qp: qp pointer
  * @buf: buf received on IEQ used to create AH
  */
-static enum irdma_status_code irdma_ieq_create_ah(struct irdma_sc_qp *qp,
+static int irdma_ieq_create_ah(struct irdma_sc_qp *qp, struct irdma_puda_buf *buf)
-						  struct irdma_puda_buf *buf)
 {
 	struct irdma_ah_info ah_info = {};

drivers/infiniband/hw/irdma/puda.h+17−26

@@ -151,42 +151,33 @@ void irdma_puda_ret_bufpool(struct irdma_puda_rsrc *rsrc, · 150 unmodified lines
151	struct irdma_puda_buf *buf);	151	struct irdma_puda_buf *buf);
152	void irdma_puda_send_buf(struct irdma_puda_rsrc *rsrc,	152	void irdma_puda_send_buf(struct irdma_puda_rsrc *rsrc,
153	struct irdma_puda_buf *buf);	153	struct irdma_puda_buf *buf);
154	enum irdma_status_code irdma_puda_send(struct irdma_sc_qp *qp,	154	int irdma_puda_send(struct irdma_sc_qp qp, struct irdma_puda_send_info info);
155	struct irdma_puda_send_info *info);	155	int irdma_puda_create_rsrc(struct irdma_sc_vsi *vsi,
156	enum irdma_status_code	156	struct irdma_puda_rsrc_info *info);
157	irdma_puda_create_rsrc(struct irdma_sc_vsi *vsi,
158	struct irdma_puda_rsrc_info *info);
159	void irdma_puda_dele_rsrc(struct irdma_sc_vsi *vsi, enum puda_rsrc_type type,	157	void irdma_puda_dele_rsrc(struct irdma_sc_vsi *vsi, enum puda_rsrc_type type,
160	bool reset);	158	bool reset);
161	enum irdma_status_code irdma_puda_poll_cmpl(struct irdma_sc_dev *dev,	159	int irdma_puda_poll_cmpl(struct irdma_sc_dev dev, struct irdma_sc_cq cq,
162	struct irdma_sc_cq *cq,	160	u32 *compl_err);
163	u32 *compl_err);
164		161
165	struct irdma_sc_qp irdma_ieq_get_qp(struct irdma_sc_dev dev,	162	struct irdma_sc_qp irdma_ieq_get_qp(struct irdma_sc_dev dev,
166	struct irdma_puda_buf *buf);	163	struct irdma_puda_buf *buf);
167	enum irdma_status_code	164	int irdma_puda_get_tcpip_info(struct irdma_puda_cmpl_info *info,
168	irdma_puda_get_tcpip_info(struct irdma_puda_cmpl_info *info,	165	struct irdma_puda_buf *buf);
169	struct irdma_puda_buf *buf);	166	int irdma_ieq_check_mpacrc(struct shash_desc desc, void addr, u32 len, u32 val);
170	enum irdma_status_code irdma_ieq_check_mpacrc(struct shash_desc *desc,	167	int irdma_init_hash_desc(struct shash_desc **desc);
171	void *addr, u32 len, u32 val);
172	enum irdma_status_code irdma_init_hash_desc(struct shash_desc **desc);
173	void irdma_ieq_mpa_crc_ae(struct irdma_sc_dev dev, struct irdma_sc_qp qp);	168	void irdma_ieq_mpa_crc_ae(struct irdma_sc_dev dev, struct irdma_sc_qp qp);
174	void irdma_free_hash_desc(struct shash_desc *desc);	169	void irdma_free_hash_desc(struct shash_desc *desc);
175	void irdma_ieq_update_tcpip_info(struct irdma_puda_buf *buf, u16 len,	170	void irdma_ieq_update_tcpip_info(struct irdma_puda_buf *buf, u16 len, u32 seqnum);
176	u32 seqnum);	171	int irdma_cqp_qp_create_cmd(struct irdma_sc_dev dev, struct irdma_sc_qp qp);
177	enum irdma_status_code irdma_cqp_qp_create_cmd(struct irdma_sc_dev *dev,	172	int irdma_cqp_cq_create_cmd(struct irdma_sc_dev dev, struct irdma_sc_cq cq);
178	struct irdma_sc_qp *qp);	173	int irdma_cqp_qp_destroy_cmd(struct irdma_sc_dev dev, struct irdma_sc_qp qp);
179	enum irdma_status_code irdma_cqp_cq_create_cmd(struct irdma_sc_dev *dev,
180	struct irdma_sc_cq *cq);
181	enum irdma_status_code irdma_cqp_qp_destroy_cmd(struct irdma_sc_dev dev, struct irdma_sc_qp qp);
182	void irdma_cqp_cq_destroy_cmd(struct irdma_sc_dev dev, struct irdma_sc_cq cq);	174	void irdma_cqp_cq_destroy_cmd(struct irdma_sc_dev dev, struct irdma_sc_cq cq);
183	void irdma_puda_ieq_get_ah_info(struct irdma_sc_qp *qp,	175	void irdma_puda_ieq_get_ah_info(struct irdma_sc_qp *qp,
184	struct irdma_ah_info *ah_info);	176	struct irdma_ah_info *ah_info);
185	enum irdma_status_code irdma_puda_create_ah(struct irdma_sc_dev *dev,	177	int irdma_puda_create_ah(struct irdma_sc_dev *dev,
186	struct irdma_ah_info *ah_info,	178	struct irdma_ah_info *ah_info, bool wait,
187	bool wait, enum puda_rsrc_type type,	179	enum puda_rsrc_type type, void *cb_param,
188	void *cb_param,	180	struct irdma_sc_ah **ah);
189	struct irdma_sc_ah **ah);
190	void irdma_puda_free_ah(struct irdma_sc_dev dev, struct irdma_sc_ah ah);	181	void irdma_puda_free_ah(struct irdma_sc_dev dev, struct irdma_sc_ah ah);
191	void irdma_ieq_process_fpdus(struct irdma_sc_qp *qp,	182	void irdma_ieq_process_fpdus(struct irdma_sc_qp *qp,
192	struct irdma_puda_rsrc *ieq);	183	struct irdma_puda_rsrc *ieq);

drivers/infiniband/hw/irdma/status.h+0−71

@@ -1,71 +0,0 @@
1	/* SPDX-License-Identifier: GPL-2.0 or Linux-OpenIB */
2	/* Copyright (c) 2015 - 2020 Intel Corporation */
3	#ifndef IRDMA_STATUS_H
4	#define IRDMA_STATUS_H
5
6	/* Error Codes */
7	enum irdma_status_code {
8	IRDMA_SUCCESS = 0,
9	IRDMA_ERR_NVM = -1,
10	IRDMA_ERR_NVM_CHECKSUM = -2,
11	IRDMA_ERR_CFG = -4,
12	IRDMA_ERR_PARAM = -5,
13	IRDMA_ERR_DEVICE_NOT_SUPPORTED = -6,
14	IRDMA_ERR_RESET_FAILED = -7,
15	IRDMA_ERR_SWFW_SYNC = -8,
16	IRDMA_ERR_NO_MEMORY = -9,
17	IRDMA_ERR_BAD_PTR = -10,
18	IRDMA_ERR_INVALID_PD_ID = -11,
19	IRDMA_ERR_INVALID_QP_ID = -12,
20	IRDMA_ERR_INVALID_CQ_ID = -13,
21	IRDMA_ERR_INVALID_CEQ_ID = -14,
22	IRDMA_ERR_INVALID_AEQ_ID = -15,
23	IRDMA_ERR_INVALID_SIZE = -16,
24	IRDMA_ERR_INVALID_ARP_INDEX = -17,
25	IRDMA_ERR_INVALID_FPM_FUNC_ID = -18,
26	IRDMA_ERR_QP_INVALID_MSG_SIZE = -19,
27	IRDMA_ERR_QP_TOOMANY_WRS_POSTED = -20,
28	IRDMA_ERR_INVALID_FRAG_COUNT = -21,
29	IRDMA_ERR_Q_EMPTY = -22,
30	IRDMA_ERR_INVALID_ALIGNMENT = -23,
31	IRDMA_ERR_FLUSHED_Q = -24,
32	IRDMA_ERR_INVALID_PUSH_PAGE_INDEX = -25,
33	IRDMA_ERR_INVALID_INLINE_DATA_SIZE = -26,
34	IRDMA_ERR_TIMEOUT = -27,
35	IRDMA_ERR_OPCODE_MISMATCH = -28,
36	IRDMA_ERR_CQP_COMPL_ERROR = -29,
37	IRDMA_ERR_INVALID_VF_ID = -30,
38	IRDMA_ERR_INVALID_HMCFN_ID = -31,
39	IRDMA_ERR_BACKING_PAGE_ERROR = -32,
40	IRDMA_ERR_NO_PBLCHUNKS_AVAILABLE = -33,
41	IRDMA_ERR_INVALID_PBLE_INDEX = -34,
42	IRDMA_ERR_INVALID_SD_INDEX = -35,
43	IRDMA_ERR_INVALID_PAGE_DESC_INDEX = -36,
44	IRDMA_ERR_INVALID_SD_TYPE = -37,
45	IRDMA_ERR_MEMCPY_FAILED = -38,
46	IRDMA_ERR_INVALID_HMC_OBJ_INDEX = -39,
47	IRDMA_ERR_INVALID_HMC_OBJ_COUNT = -40,
48	IRDMA_ERR_BUF_TOO_SHORT = -43,
49	IRDMA_ERR_BAD_IWARP_CQE = -44,
50	IRDMA_ERR_NVM_BLANK_MODE = -45,
51	IRDMA_ERR_NOT_IMPL = -46,
52	IRDMA_ERR_PE_DOORBELL_NOT_ENA = -47,
53	IRDMA_ERR_NOT_READY = -48,
54	IRDMA_NOT_SUPPORTED = -49,
55	IRDMA_ERR_FIRMWARE_API_VER = -50,
56	IRDMA_ERR_RING_FULL = -51,
57	IRDMA_ERR_MPA_CRC = -61,
58	IRDMA_ERR_NO_TXBUFS = -62,
59	IRDMA_ERR_SEQ_NUM = -63,
60	IRDMA_ERR_list_empty = -64,
61	IRDMA_ERR_INVALID_MAC_ADDR = -65,
62	IRDMA_ERR_BAD_STAG = -66,
63	IRDMA_ERR_CQ_COMPL_ERROR = -67,
64	IRDMA_ERR_Q_DESTROYED = -68,
65	IRDMA_ERR_INVALID_FEAT_CNT = -69,
66	IRDMA_ERR_REG_CQ_FULL = -70,
67	IRDMA_ERR_VF_MSG_ERROR = -71,
68	IRDMA_ERR_NO_INTR = -72,
69	IRDMA_ERR_REG_QSET = -73,
70	};
71	#endif /* IRDMA_STATUS_H */

drivers/infiniband/hw/irdma/type.h+54−59

@@ -2,7 +2,6 @@ · 1 unmodified line
2	/* Copyright (c) 2015 - 2021 Intel Corporation */	2	/* Copyright (c) 2015 - 2021 Intel Corporation */
3	#ifndef IRDMA_TYPE_H	3	#ifndef IRDMA_TYPE_H
4	#define IRDMA_TYPE_H	4	#define IRDMA_TYPE_H
5	#include "status.h"
6	#include "osdep.h"	5	#include "osdep.h"
7	#include "irdma.h"	6	#include "irdma.h"
8	#include "user.h"	7	#include "user.h"
@@ -402,8 +401,8 @@ struct irdma_sc_cqp { · 393 unmodified lines
402	u64 host_ctx_pa;	401	u64 host_ctx_pa;
403	void *back_cqp;	402	void *back_cqp;
404	struct irdma_sc_dev *dev;	403	struct irdma_sc_dev *dev;
405	enum irdma_status_code (process_cqp_sds)(struct irdma_sc_dev dev,	404	int (process_cqp_sds)(struct irdma_sc_dev dev,
406	struct irdma_update_sds_info *info);	405	struct irdma_update_sds_info *info);
407	struct irdma_dma_mem sdbuf;	406	struct irdma_dma_mem sdbuf;
408	struct irdma_ring sq_ring;	407	struct irdma_ring sq_ring;
409	struct irdma_cqp_quanta *sq_base;	408	struct irdma_cqp_quanta *sq_base;
@@ -605,12 +604,14 @@ struct irdma_sc_vsi { · 195 unmodified lines
605	struct irdma_qos qos[IRDMA_MAX_USER_PRIORITY];	604	struct irdma_qos qos[IRDMA_MAX_USER_PRIORITY];
606	struct irdma_vsi_pestat *pestat;	605	struct irdma_vsi_pestat *pestat;
607	atomic_t qp_suspend_reqs;	606	atomic_t qp_suspend_reqs;
608	enum irdma_status_code (register_qset)(struct irdma_sc_vsi vsi,	607	int (register_qset)(struct irdma_sc_vsi vsi,
609	struct irdma_ws_node *tc_node);	608	struct irdma_ws_node *tc_node);
610	void (unregister_qset)(struct irdma_sc_vsi vsi,	609	void (unregister_qset)(struct irdma_sc_vsi vsi,
611	struct irdma_ws_node *tc_node);	610	struct irdma_ws_node *tc_node);
612	u8 qos_rel_bw;	611	u8 qos_rel_bw;
613	u8 qos_prio_type;	612	u8 qos_prio_type;
		613	u8 dscp_map[IIDC_MAX_DSCP_MAPPING];
		614	bool dscp_mode:1;
614	};	615	};
615		616
616	struct irdma_sc_dev {	617	struct irdma_sc_dev {
@@ -655,7 +656,7 @@ struct irdma_sc_dev { · 38 unmodified lines
655	bool vchnl_up:1;	656	bool vchnl_up:1;
656	bool ceq_valid:1;	657	bool ceq_valid:1;
657	u8 pci_rev;	658	u8 pci_rev;
658	enum irdma_status_code (ws_add)(struct irdma_sc_vsi vsi, u8 user_pri);	659	int (ws_add)(struct irdma_sc_vsi vsi, u8 user_pri);
659	void (ws_remove)(struct irdma_sc_vsi vsi, u8 user_pri);	660	void (ws_remove)(struct irdma_sc_vsi vsi, u8 user_pri);
660	void (ws_reset)(struct irdma_sc_vsi vsi);	661	void (ws_reset)(struct irdma_sc_vsi vsi);
661	};	662	};
@@ -735,11 +736,13 @@ struct irdma_l2params { · 73 unmodified lines
735	u16 qs_handle_list[IRDMA_MAX_USER_PRIORITY];	736	u16 qs_handle_list[IRDMA_MAX_USER_PRIORITY];
736	u16 mtu;	737	u16 mtu;
737	u8 up2tc[IRDMA_MAX_USER_PRIORITY];	738	u8 up2tc[IRDMA_MAX_USER_PRIORITY];
		739	u8 dscp_map[IIDC_MAX_DSCP_MAPPING];
738	u8 num_tc;	740	u8 num_tc;
739	u8 vsi_rel_bw;	741	u8 vsi_rel_bw;
740	u8 vsi_prio_type;	742	u8 vsi_prio_type;
741	bool mtu_changed:1;	743	bool mtu_changed:1;
742	bool tc_changed:1;	744	bool tc_changed:1;
		745	bool dscp_mode:1;
743	};	746	};
744		747
745	struct irdma_vsi_init_info {	748	struct irdma_vsi_init_info {
@@ -750,8 +753,8 @@ struct irdma_vsi_init_info { · 4 unmodified lines
750	u16 pf_data_vsi_num;	753	u16 pf_data_vsi_num;
751	enum irdma_vm_vf_type vm_vf_type;	754	enum irdma_vm_vf_type vm_vf_type;
752	u16 vm_id;	755	u16 vm_id;
753	enum irdma_status_code (register_qset)(struct irdma_sc_vsi vsi,	756	int (register_qset)(struct irdma_sc_vsi vsi,
754	struct irdma_ws_node *tc_node);	757	struct irdma_ws_node *tc_node);
755	void (unregister_qset)(struct irdma_sc_vsi vsi,	758	void (unregister_qset)(struct irdma_sc_vsi vsi,
756	struct irdma_ws_node *tc_node);	759	struct irdma_ws_node *tc_node);
757	};	760	};
@@ -1198,29 +1201,27 @@ struct irdma_irq_ops { · 440 unmodified lines
1198	};	1201	};
1199		1202
1200	void irdma_sc_ccq_arm(struct irdma_sc_cq *ccq);	1203	void irdma_sc_ccq_arm(struct irdma_sc_cq *ccq);
1201	enum irdma_status_code irdma_sc_ccq_create(struct irdma_sc_cq *ccq, u64 scratch,	1204	int irdma_sc_ccq_create(struct irdma_sc_cq *ccq, u64 scratch,
1202	bool check_overflow, bool post_sq);	1205	bool check_overflow, bool post_sq);
1203	enum irdma_status_code irdma_sc_ccq_destroy(struct irdma_sc_cq *ccq, u64 scratch,	1206	int irdma_sc_ccq_destroy(struct irdma_sc_cq *ccq, u64 scratch, bool post_sq);
1204	bool post_sq);	1207	int irdma_sc_ccq_get_cqe_info(struct irdma_sc_cq *ccq,
1205	enum irdma_status_code irdma_sc_ccq_get_cqe_info(struct irdma_sc_cq *ccq,	1208	struct irdma_ccq_cqe_info *info);
1206	struct irdma_ccq_cqe_info *info);	1209	int irdma_sc_ccq_init(struct irdma_sc_cq *ccq,
1207	enum irdma_status_code irdma_sc_ccq_init(struct irdma_sc_cq *ccq,	1210	struct irdma_ccq_init_info *info);
1208	struct irdma_ccq_init_info *info);	1211
1209		1212	int irdma_sc_cceq_create(struct irdma_sc_ceq *ceq, u64 scratch);
1210	enum irdma_status_code irdma_sc_cceq_create(struct irdma_sc_ceq *ceq, u64 scratch);	1213	int irdma_sc_cceq_destroy_done(struct irdma_sc_ceq *ceq);
1211	enum irdma_status_code irdma_sc_cceq_destroy_done(struct irdma_sc_ceq *ceq);	1214
1212		1215	int irdma_sc_ceq_destroy(struct irdma_sc_ceq *ceq, u64 scratch, bool post_sq);
1213	enum irdma_status_code irdma_sc_ceq_destroy(struct irdma_sc_ceq *ceq, u64 scratch,	1216	int irdma_sc_ceq_init(struct irdma_sc_ceq *ceq,
1214	bool post_sq);	1217	struct irdma_ceq_init_info *info);
1215	enum irdma_status_code irdma_sc_ceq_init(struct irdma_sc_ceq *ceq,
1216	struct irdma_ceq_init_info *info);
1217	void irdma_sc_cleanup_ceqes(struct irdma_sc_cq cq, struct irdma_sc_ceq ceq);	1218	void irdma_sc_cleanup_ceqes(struct irdma_sc_cq cq, struct irdma_sc_ceq ceq);
1218	void irdma_sc_process_ceq(struct irdma_sc_dev dev, struct irdma_sc_ceq *ceq);	1219	void irdma_sc_process_ceq(struct irdma_sc_dev dev, struct irdma_sc_ceq *ceq);
1219		1220
1220	enum irdma_status_code irdma_sc_aeq_init(struct irdma_sc_aeq *aeq,	1221	int irdma_sc_aeq_init(struct irdma_sc_aeq *aeq,
1221	struct irdma_aeq_init_info *info);	1222	struct irdma_aeq_init_info *info);
1222	enum irdma_status_code irdma_sc_get_next_aeqe(struct irdma_sc_aeq *aeq,	1223	int irdma_sc_get_next_aeqe(struct irdma_sc_aeq *aeq,
1223	struct irdma_aeqe_info *info);	1224	struct irdma_aeqe_info *info);
1224	void irdma_sc_repost_aeq_entries(struct irdma_sc_dev *dev, u32 count);	1225	void irdma_sc_repost_aeq_entries(struct irdma_sc_dev *dev, u32 count);
1225		1226
1226	void irdma_sc_pd_init(struct irdma_sc_dev dev, struct irdma_sc_pd pd, u32 pd_id,	1227	void irdma_sc_pd_init(struct irdma_sc_dev dev, struct irdma_sc_pd pd, u32 pd_id,
@@ -1228,31 +1229,27 @@ void irdma_sc_pd_init(struct irdma_sc_dev dev, struct irdma_sc_pd pd, u32 pd_i · 1 unmodified line
1228	void irdma_cfg_aeq(struct irdma_sc_dev *dev, u32 idx, bool enable);	1229	void irdma_cfg_aeq(struct irdma_sc_dev *dev, u32 idx, bool enable);
1229	void irdma_check_cqp_progress(struct irdma_cqp_timeout *cqp_timeout,	1230	void irdma_check_cqp_progress(struct irdma_cqp_timeout *cqp_timeout,
1230	struct irdma_sc_dev *dev);	1231	struct irdma_sc_dev *dev);
1231	enum irdma_status_code irdma_sc_cqp_create(struct irdma_sc_cqp cqp, u16 maj_err,	1232	int irdma_sc_cqp_create(struct irdma_sc_cqp cqp, u16 maj_err, u16 *min_err);
1232	u16 *min_err);	1233	int irdma_sc_cqp_destroy(struct irdma_sc_cqp *cqp);
1233	enum irdma_status_code irdma_sc_cqp_destroy(struct irdma_sc_cqp *cqp);	1234	int irdma_sc_cqp_init(struct irdma_sc_cqp *cqp,
1234	enum irdma_status_code irdma_sc_cqp_init(struct irdma_sc_cqp *cqp,	1235	struct irdma_cqp_init_info *info);
1235	struct irdma_cqp_init_info *info);
1236	void irdma_sc_cqp_post_sq(struct irdma_sc_cqp *cqp);	1236	void irdma_sc_cqp_post_sq(struct irdma_sc_cqp *cqp);
1237	enum irdma_status_code irdma_sc_poll_for_cqp_op_done(struct irdma_sc_cqp *cqp, u8 opcode,	1237	int irdma_sc_poll_for_cqp_op_done(struct irdma_sc_cqp *cqp, u8 opcode,
1238	struct irdma_ccq_cqe_info *cmpl_info);	1238	struct irdma_ccq_cqe_info *cmpl_info);
1239	enum irdma_status_code irdma_sc_fast_register(struct irdma_sc_qp *qp,	1239	int irdma_sc_fast_register(struct irdma_sc_qp *qp,
1240	struct irdma_fast_reg_stag_info *info,	1240	struct irdma_fast_reg_stag_info *info, bool post_sq);
1241	bool post_sq);	1241	int irdma_sc_qp_create(struct irdma_sc_qp *qp,
1242	enum irdma_status_code irdma_sc_qp_create(struct irdma_sc_qp *qp,	1242	struct irdma_create_qp_info *info, u64 scratch,
1243	struct irdma_create_qp_info *info,	1243	bool post_sq);
1244	u64 scratch, bool post_sq);	1244	int irdma_sc_qp_destroy(struct irdma_sc_qp *qp, u64 scratch,
1245	enum irdma_status_code irdma_sc_qp_destroy(struct irdma_sc_qp *qp,	1245	bool remove_hash_idx, bool ignore_mw_bnd, bool post_sq);
1246	u64 scratch, bool remove_hash_idx,	1246	int irdma_sc_qp_flush_wqes(struct irdma_sc_qp *qp,
1247	bool ignore_mw_bnd, bool post_sq);	1247	struct irdma_qp_flush_info *info, u64 scratch,
1248	enum irdma_status_code irdma_sc_qp_flush_wqes(struct irdma_sc_qp *qp,	1248	bool post_sq);
1249	struct irdma_qp_flush_info *info,	1249	int irdma_sc_qp_init(struct irdma_sc_qp qp, struct irdma_qp_init_info info);
1250	u64 scratch, bool post_sq);	1250	int irdma_sc_qp_modify(struct irdma_sc_qp *qp,
1251	enum irdma_status_code irdma_sc_qp_init(struct irdma_sc_qp *qp,	1251	struct irdma_modify_qp_info *info, u64 scratch,
1252	struct irdma_qp_init_info *info);	1252	bool post_sq);
1253	enum irdma_status_code irdma_sc_qp_modify(struct irdma_sc_qp *qp,
1254	struct irdma_modify_qp_info *info,
1255	u64 scratch, bool post_sq);
1256	void irdma_sc_send_lsmm(struct irdma_sc_qp qp, void lsmm_buf, u32 size,	1253	void irdma_sc_send_lsmm(struct irdma_sc_qp qp, void lsmm_buf, u32 size,
1257	irdma_stag stag);	1254	irdma_stag stag);
1258		1255
@@ -1261,14 +1258,12 @@ void irdma_sc_qp_setctx(struct irdma_sc_qp qp, __le64 qp_ctx, · 2 unmodified lines
1261	struct irdma_qp_host_ctx_info *info);	1258	struct irdma_qp_host_ctx_info *info);
1262	void irdma_sc_qp_setctx_roce(struct irdma_sc_qp qp, __le64 qp_ctx,	1259	void irdma_sc_qp_setctx_roce(struct irdma_sc_qp qp, __le64 qp_ctx,
1263	struct irdma_qp_host_ctx_info *info);	1260	struct irdma_qp_host_ctx_info *info);
1264	enum irdma_status_code irdma_sc_cq_destroy(struct irdma_sc_cq *cq, u64 scratch,	1261	int irdma_sc_cq_destroy(struct irdma_sc_cq *cq, u64 scratch, bool post_sq);
1265	bool post_sq);	1262	int irdma_sc_cq_init(struct irdma_sc_cq cq, struct irdma_cq_init_info info);
1266	enum irdma_status_code irdma_sc_cq_init(struct irdma_sc_cq *cq,
1267	struct irdma_cq_init_info *info);
1268	void irdma_sc_cq_resize(struct irdma_sc_cq cq, struct irdma_modify_cq_info info);	1263	void irdma_sc_cq_resize(struct irdma_sc_cq cq, struct irdma_modify_cq_info info);
1269	enum irdma_status_code irdma_sc_static_hmc_pages_allocated(struct irdma_sc_cqp *cqp,	1264	int irdma_sc_static_hmc_pages_allocated(struct irdma_sc_cqp *cqp, u64 scratch,
1270	u64 scratch, u8 hmc_fn_id,	1265	u8 hmc_fn_id, bool post_sq,
1271	bool post_sq, bool poll_registers);	1266	bool poll_registers);
1272		1267
1273	void sc_vsi_update_stats(struct irdma_sc_vsi *vsi);	1268	void sc_vsi_update_stats(struct irdma_sc_vsi *vsi);
1274	struct cqp_info {	1269	struct cqp_info {

drivers/infiniband/hw/irdma/uda.c+16−24

 #include <linux/etherdevice.h>
 #include "osdep.h"
-#include "status.h"
 #include "hmc.h"
 #include "defs.h"
 #include "type.h"
  * @op: Operation
  * @scratch: u64 saved to be used during cqp completion
  */
-enum irdma_status_code irdma_sc_access_ah(struct irdma_sc_cqp *cqp,
+int irdma_sc_access_ah(struct irdma_sc_cqp *cqp, struct irdma_ah_info *info,
-					  struct irdma_ah_info *info,
+		       u32 op, u64 scratch)
-					  u32 op, u64 scratch)
 {
 	__le64 *wqe;
 	u64 qw1, qw2;
 	wqe = irdma_sc_cqp_get_next_send_wqe(cqp, scratch);
 	if (!wqe)
-		return IRDMA_ERR_RING_FULL;
+		return -ENOMEM;
 	set_64bit_val(wqe, 0, ether_addr_to_u64(info->mac_addr) << 16);
 	qw1 = FIELD_PREP(IRDMA_UDA_CQPSQ_MAV_PDINDEXLO, info->pd_idx) |
  * irdma_create_mg_ctx() - create a mcg context
  * @info: multicast group context info
  */
-static enum irdma_status_code
+static void irdma_create_mg_ctx(struct irdma_mcast_grp_info *info)
-irdma_create_mg_ctx(struct irdma_mcast_grp_info *info)
 {
 	struct irdma_mcast_grp_ctx_entry_info *entry_info = NULL;
 	u8 idx = 0; /* index in the array */
 			ctx_idx++;
 		}
 	}
-	return 0;
 }
 /**
  * @op: operation to perform
  * @scratch: u64 saved to be used during cqp completion
  */
-enum irdma_status_code irdma_access_mcast_grp(struct irdma_sc_cqp *cqp,
+int irdma_access_mcast_grp(struct irdma_sc_cqp *cqp,
-					      struct irdma_mcast_grp_info *info,
+			   struct irdma_mcast_grp_info *info, u32 op,
-					      u32 op, u64 scratch)
+			   u64 scratch)
 {
 	__le64 *wqe;
-	enum irdma_status_code ret_code = 0;
 	if (info->mg_id >= IRDMA_UDA_MAX_FSI_MGS) {
 		ibdev_dbg(to_ibdev(cqp->dev), "WQE: mg_id out of range\n");
-		return IRDMA_ERR_PARAM;
+		return -EINVAL;
 	}
 	wqe = irdma_sc_cqp_get_next_send_wqe(cqp, scratch);
 	if (!wqe) {
 		ibdev_dbg(to_ibdev(cqp->dev), "WQE: ring full\n");
-		return IRDMA_ERR_RING_FULL;
+		return -ENOMEM;
 	}
-	ret_code = irdma_create_mg_ctx(info);
+	irdma_create_mg_ctx(info);
-	if (ret_code)
-		return ret_code;
 	set_64bit_val(wqe, 32, info->dma_mem_mc.pa);
 	set_64bit_val(wqe, 16,
  * @ctx: Multcast group context
  * @mg: Multcast group info
  */
-enum irdma_status_code irdma_sc_add_mcast_grp(struct irdma_mcast_grp_info *ctx,
+int irdma_sc_add_mcast_grp(struct irdma_mcast_grp_info *ctx,
-					      struct irdma_mcast_grp_ctx_entry_info *mg)
+			   struct irdma_mcast_grp_ctx_entry_info *mg)
 {
 	u32 idx;
 	bool free_entry_found = false;
 		return 0;
 	}
-	return IRDMA_ERR_NO_MEMORY;
+	return -ENOMEM;
 }
 /**
  * Finds and removes a specific mulicast group from context, all
  * parameters must match to remove a multicast group.
  */
-enum irdma_status_code irdma_sc_del_mcast_grp(struct irdma_mcast_grp_info *ctx,
+int irdma_sc_del_mcast_grp(struct irdma_mcast_grp_info *ctx,
-					      struct irdma_mcast_grp_ctx_entry_info *mg)
+			   struct irdma_mcast_grp_ctx_entry_info *mg)
 {
 	u32 idx;
 		}
 	}
-	return IRDMA_ERR_PARAM;
+	return -EINVAL;
 }

drivers/infiniband/hw/irdma/uda.h+22−24

@@ -32,56 +32,54 @@ struct irdma_sc_ah { · 31 unmodified lines
32	struct irdma_ah_info ah_info;	32	struct irdma_ah_info ah_info;
33	};	33	};
34		34
35	enum irdma_status_code irdma_sc_add_mcast_grp(struct irdma_mcast_grp_info *ctx,	35	int irdma_sc_add_mcast_grp(struct irdma_mcast_grp_info *ctx,
36	struct irdma_mcast_grp_ctx_entry_info *mg);	36	struct irdma_mcast_grp_ctx_entry_info *mg);
37	enum irdma_status_code irdma_sc_del_mcast_grp(struct irdma_mcast_grp_info *ctx,	37	int irdma_sc_del_mcast_grp(struct irdma_mcast_grp_info *ctx,
38	struct irdma_mcast_grp_ctx_entry_info *mg);	38	struct irdma_mcast_grp_ctx_entry_info *mg);
39	enum irdma_status_code irdma_sc_access_ah(struct irdma_sc_cqp cqp, struct irdma_ah_info info,	39	int irdma_sc_access_ah(struct irdma_sc_cqp cqp, struct irdma_ah_info info,
40	u32 op, u64 scratch);	40	u32 op, u64 scratch);
41	enum irdma_status_code irdma_access_mcast_grp(struct irdma_sc_cqp *cqp,	41	int irdma_access_mcast_grp(struct irdma_sc_cqp *cqp,
42	struct irdma_mcast_grp_info *info,	42	struct irdma_mcast_grp_info *info, u32 op,
43	u32 op, u64 scratch);	43	u64 scratch);
44		44
45	static inline void irdma_sc_init_ah(struct irdma_sc_dev dev, struct irdma_sc_ah ah)	45	static inline void irdma_sc_init_ah(struct irdma_sc_dev dev, struct irdma_sc_ah ah)
46	{	46	{
47	ah->dev = dev;	47	ah->dev = dev;
48	}	48	}
49		49
50	static inline enum irdma_status_code irdma_sc_create_ah(struct irdma_sc_cqp *cqp,	50	static inline int irdma_sc_create_ah(struct irdma_sc_cqp *cqp,
51	struct irdma_ah_info *info,	51	struct irdma_ah_info *info, u64 scratch)
52	u64 scratch)
53	{	52	{
54	return irdma_sc_access_ah(cqp, info, IRDMA_CQP_OP_CREATE_ADDR_HANDLE,	53	return irdma_sc_access_ah(cqp, info, IRDMA_CQP_OP_CREATE_ADDR_HANDLE,
55	scratch);	54	scratch);
56	}	55	}
57		56
58	static inline enum irdma_status_code irdma_sc_destroy_ah(struct irdma_sc_cqp *cqp,	57	static inline int irdma_sc_destroy_ah(struct irdma_sc_cqp *cqp,
59	struct irdma_ah_info *info,	58	struct irdma_ah_info *info, u64 scratch)
60	u64 scratch)
61	{	59	{
62	return irdma_sc_access_ah(cqp, info, IRDMA_CQP_OP_DESTROY_ADDR_HANDLE,	60	return irdma_sc_access_ah(cqp, info, IRDMA_CQP_OP_DESTROY_ADDR_HANDLE,
63	scratch);	61	scratch);
64	}	62	}
65		63
66	static inline enum irdma_status_code irdma_sc_create_mcast_grp(struct irdma_sc_cqp *cqp,	64	static inline int irdma_sc_create_mcast_grp(struct irdma_sc_cqp *cqp,
67	struct irdma_mcast_grp_info *info,	65	struct irdma_mcast_grp_info *info,
68	u64 scratch)	66	u64 scratch)
69	{	67	{
70	return irdma_access_mcast_grp(cqp, info, IRDMA_CQP_OP_CREATE_MCAST_GRP,	68	return irdma_access_mcast_grp(cqp, info, IRDMA_CQP_OP_CREATE_MCAST_GRP,
71	scratch);	69	scratch);
72	}	70	}
73		71
74	static inline enum irdma_status_code irdma_sc_modify_mcast_grp(struct irdma_sc_cqp *cqp,	72	static inline int irdma_sc_modify_mcast_grp(struct irdma_sc_cqp *cqp,
75	struct irdma_mcast_grp_info *info,	73	struct irdma_mcast_grp_info *info,
76	u64 scratch)	74	u64 scratch)
77	{	75	{
78	return irdma_access_mcast_grp(cqp, info, IRDMA_CQP_OP_MODIFY_MCAST_GRP,	76	return irdma_access_mcast_grp(cqp, info, IRDMA_CQP_OP_MODIFY_MCAST_GRP,
79	scratch);	77	scratch);
80	}	78	}
81		79
82	static inline enum irdma_status_code irdma_sc_destroy_mcast_grp(struct irdma_sc_cqp *cqp,	80	static inline int irdma_sc_destroy_mcast_grp(struct irdma_sc_cqp *cqp,
83	struct irdma_mcast_grp_info *info,	81	struct irdma_mcast_grp_info *info,
84	u64 scratch)	82	u64 scratch)
85	{	83	{
86	return irdma_access_mcast_grp(cqp, info, IRDMA_CQP_OP_DESTROY_MCAST_GRP,	84	return irdma_access_mcast_grp(cqp, info, IRDMA_CQP_OP_DESTROY_MCAST_GRP,
87	scratch);	85	scratch);

drivers/infiniband/hw/irdma/uk.c+57−65

 // SPDX-License-Identifier: GPL-2.0 or Linux-OpenIB
 /* Copyright (c) 2015 - 2021 Intel Corporation */
 #include "osdep.h"
-#include "status.h"
 #include "defs.h"
 #include "user.h"
 #include "irdma.h"
  * irdma_nop_1 - insert a NOP wqe
  * @qp: hw qp ptr
  */
-static enum irdma_status_code irdma_nop_1(struct irdma_qp_uk *qp)
+static int irdma_nop_1(struct irdma_qp_uk *qp)
 {
 	u64 hdr;
 	__le64 *wqe;
 	bool signaled = false;
 	if (!qp->sq_ring.head)
-		return IRDMA_ERR_PARAM;
+		return -EINVAL;
 	wqe_idx = IRDMA_RING_CURRENT_HEAD(qp->sq_ring);
 	wqe = qp->sq_base[wqe_idx].elem;
 __le64 *irdma_qp_get_next_recv_wqe(struct irdma_qp_uk *qp, u32 *wqe_idx)
 {
 	__le64 *wqe;
-	enum irdma_status_code ret_code;
+	int ret_code;
 	if (IRDMA_RING_FULL_ERR(qp->rq_ring))
 		return NULL;
  * @info: post sq information
  * @post_sq: flag to post sq
  */
-enum irdma_status_code irdma_uk_rdma_write(struct irdma_qp_uk *qp,
+int irdma_uk_rdma_write(struct irdma_qp_uk *qp, struct irdma_post_sq_info *info,
-					   struct irdma_post_sq_info *info,
+			bool post_sq)
-					   bool post_sq)
 {
 	u64 hdr;
 	__le64 *wqe;
 	struct irdma_rdma_write *op_info;
 	u32 i, wqe_idx;
 	u32 total_size = 0, byte_off;
-	enum irdma_status_code ret_code;
+	int ret_code;
 	u32 frag_cnt, addl_frag_cnt;
 	bool read_fence = false;
 	u16 quanta;
 	op_info = &info->op.rdma_write;
 	if (op_info->num_lo_sges > qp->max_sq_frag_cnt)
-		return IRDMA_ERR_INVALID_FRAG_COUNT;
+		return -EINVAL;
 	for (i = 0; i < op_info->num_lo_sges; i++)
 		total_size += op_info->lo_sg_list[i].length;
 	wqe = irdma_qp_get_next_send_wqe(qp, &wqe_idx, quanta, total_size,
 					 info);
 	if (!wqe)
-		return IRDMA_ERR_QP_TOOMANY_WRS_POSTED;
+		return -ENOMEM;
 	irdma_clr_wqes(qp, wqe_idx);
  * @inv_stag: flag for inv_stag
  * @post_sq: flag to post sq
  */
-enum irdma_status_code irdma_uk_rdma_read(struct irdma_qp_uk *qp,
+int irdma_uk_rdma_read(struct irdma_qp_uk *qp, struct irdma_post_sq_info *info,
-					  struct irdma_post_sq_info *info,
+		       bool inv_stag, bool post_sq)
-					  bool inv_stag, bool post_sq)
 {
 	struct irdma_rdma_read *op_info;
-	enum irdma_status_code ret_code;
+	int ret_code;
 	u32 i, byte_off, total_size = 0;
 	bool local_fence = false;
 	u32 addl_frag_cnt;
 	op_info = &info->op.rdma_read;
 	if (qp->max_sq_frag_cnt < op_info->num_lo_sges)
-		return IRDMA_ERR_INVALID_FRAG_COUNT;
+		return -EINVAL;
 	for (i = 0; i < op_info->num_lo_sges; i++)
 		total_size += op_info->lo_sg_list[i].length;
 	wqe = irdma_qp_get_next_send_wqe(qp, &wqe_idx, quanta, total_size,
 					 info);
 	if (!wqe)
-		return IRDMA_ERR_QP_TOOMANY_WRS_POSTED;
+		return -ENOMEM;
 	irdma_clr_wqes(qp, wqe_idx);
  * @info: post sq information
  * @post_sq: flag to post sq
  */
-enum irdma_status_code irdma_uk_send(struct irdma_qp_uk *qp,
+int irdma_uk_send(struct irdma_qp_uk *qp, struct irdma_post_sq_info *info,
-				     struct irdma_post_sq_info *info,
+		  bool post_sq)
-				     bool post_sq)
 {
 	__le64 *wqe;
 	struct irdma_post_send *op_info;
 	u64 hdr;
 	u32 i, wqe_idx, total_size = 0, byte_off;
-	enum irdma_status_code ret_code;
+	int ret_code;
 	u32 frag_cnt, addl_frag_cnt;
 	bool read_fence = false;
 	u16 quanta;
 	op_info = &info->op.send;
 	if (qp->max_sq_frag_cnt < op_info->num_sges)
-		return IRDMA_ERR_INVALID_FRAG_COUNT;
+		return -EINVAL;
 	for (i = 0; i < op_info->num_sges; i++)
 		total_size += op_info->sg_list[i].length;
 	wqe = irdma_qp_get_next_send_wqe(qp, &wqe_idx, quanta, total_size,
 					 info);
 	if (!wqe)
-		return IRDMA_ERR_QP_TOOMANY_WRS_POSTED;
+		return -ENOMEM;
 	irdma_clr_wqes(qp, wqe_idx);
  * @info: post sq information
  * @post_sq: flag to post sq
  */
-enum irdma_status_code
+int irdma_uk_inline_rdma_write(struct irdma_qp_uk *qp,
-irdma_uk_inline_rdma_write(struct irdma_qp_uk *qp, struct irdma_post_sq_info *info,
+			       struct irdma_post_sq_info *info, bool post_sq)
-			   bool post_sq)
 {
 	__le64 *wqe;
 	struct irdma_inline_rdma_write *op_info;
 	op_info = &info->op.inline_rdma_write;
 	if (op_info->len > qp->max_inline_data)
-		return IRDMA_ERR_INVALID_INLINE_DATA_SIZE;
+		return -EINVAL;
 	quanta = qp->wqe_ops.iw_inline_data_size_to_quanta(op_info->len);
 	wqe = irdma_qp_get_next_send_wqe(qp, &wqe_idx, quanta, op_info->len,
 					 info);
 	if (!wqe)
-		return IRDMA_ERR_QP_TOOMANY_WRS_POSTED;
+		return -ENOMEM;
 	irdma_clr_wqes(qp, wqe_idx);
  * @info: post sq information
  * @post_sq: flag to post sq
  */
-enum irdma_status_code irdma_uk_inline_send(struct irdma_qp_uk *qp,
+int irdma_uk_inline_send(struct irdma_qp_uk *qp,
-					    struct irdma_post_sq_info *info,
+			 struct irdma_post_sq_info *info, bool post_sq)
-					    bool post_sq)
 {
 	__le64 *wqe;
 	struct irdma_post_inline_send *op_info;
 	op_info = &info->op.inline_send;
 	if (op_info->len > qp->max_inline_data)
-		return IRDMA_ERR_INVALID_INLINE_DATA_SIZE;
+		return -EINVAL;
 	quanta = qp->wqe_ops.iw_inline_data_size_to_quanta(op_info->len);
 	wqe = irdma_qp_get_next_send_wqe(qp, &wqe_idx, quanta, op_info->len,
 					 info);
 	if (!wqe)
-		return IRDMA_ERR_QP_TOOMANY_WRS_POSTED;
+		return -ENOMEM;
 	irdma_clr_wqes(qp, wqe_idx);
  * @info: post sq information
  * @post_sq: flag to post sq
  */
-enum irdma_status_code
+int irdma_uk_stag_local_invalidate(struct irdma_qp_uk *qp,
-irdma_uk_stag_local_invalidate(struct irdma_qp_uk *qp,
+				   struct irdma_post_sq_info *info,
-			       struct irdma_post_sq_info *info, bool post_sq)
+				   bool post_sq)
 {
 	__le64 *wqe;
 	struct irdma_inv_local_stag *op_info;
 	wqe = irdma_qp_get_next_send_wqe(qp, &wqe_idx, IRDMA_QP_WQE_MIN_QUANTA,
 					 0, info);
 	if (!wqe)
-		return IRDMA_ERR_QP_TOOMANY_WRS_POSTED;
+		return -ENOMEM;
 	irdma_clr_wqes(qp, wqe_idx);
  * @qp: hw qp ptr
  * @info: post rq information
  */
-enum irdma_status_code irdma_uk_post_receive(struct irdma_qp_uk *qp,
+int irdma_uk_post_receive(struct irdma_qp_uk *qp,
-					     struct irdma_post_rq_info *info)
+			  struct irdma_post_rq_info *info)
 {
 	u32 wqe_idx, i, byte_off;
 	u32 addl_frag_cnt;
 	u64 hdr;
 	if (qp->max_rq_frag_cnt < info->num_sges)
-		return IRDMA_ERR_INVALID_FRAG_COUNT;
+		return -EINVAL;
 	wqe = irdma_qp_get_next_recv_wqe(qp, &wqe_idx);
 	if (!wqe)
-		return IRDMA_ERR_QP_TOOMANY_WRS_POSTED;
+		return -ENOMEM;
 	qp->rq_wrid_array[wqe_idx] = info->wr_id;
 	addl_frag_cnt = info->num_sges > 1 ? (info->num_sges - 1) : 0;
  * @cq: hw cq
  * @info: cq poll information returned
  */
-enum irdma_status_code
+int irdma_uk_cq_poll_cmpl(struct irdma_cq_uk *cq,
-irdma_uk_cq_poll_cmpl(struct irdma_cq_uk *cq, struct irdma_cq_poll_info *info)
+			  struct irdma_cq_poll_info *info)
 {
 	u64 comp_ctx, qword0, qword2, qword3;
 	__le64 *cqe;
 	struct irdma_qp_uk *qp;
 	struct irdma_ring *pring = NULL;
 	u32 wqe_idx, q_type;
-	enum irdma_status_code ret_code;
+	int ret_code;
 	bool move_cq_head = true;
 	u8 polarity;
 	bool ext_valid;
 	get_64bit_val(cqe, 24, &qword3);
 	polarity = (u8)FIELD_GET(IRDMA_CQ_VALID, qword3);
 	if (polarity != cq->polarity)
-		return IRDMA_ERR_Q_EMPTY;
+		return -ENOENT;
 	/* Ensure CQE contents are read after valid bit is checked */
 	dma_rmb();
 				polarity ^= 1;
 		}
 		if (polarity != cq->polarity)
-			return IRDMA_ERR_Q_EMPTY;
+			return -ENOENT;
 		/* Ensure ext CQE contents are read after ext valid bit is checked */
 		dma_rmb();
 	info->solicited_event = (bool)FIELD_GET(IRDMACQ_SOEVENT, qword3);
 	qp = (struct irdma_qp_uk *)(unsigned long)comp_ctx;
 	if (!qp || qp->destroy_pending) {
-		ret_code = IRDMA_ERR_Q_DESTROYED;
+		ret_code = -EFAULT;
 		goto exit;
 	}
 	wqe_idx = (u32)FIELD_GET(IRDMA_CQ_WQEIDX, qword3);
 		if (info->comp_status == IRDMA_COMPL_STATUS_FLUSHED ||
 		    info->comp_status == IRDMA_COMPL_STATUS_UNKNOWN) {
 			if (!IRDMA_RING_MORE_WORK(qp->rq_ring)) {
-				ret_code = IRDMA_ERR_Q_EMPTY;
+				ret_code = -ENOENT;
 				goto exit;
 			}
 					    wqe_idx + qp->sq_wrtrk_array[wqe_idx].quanta);
 		} else {
 			if (!IRDMA_RING_MORE_WORK(qp->sq_ring)) {
-				ret_code = IRDMA_ERR_Q_EMPTY;
+				ret_code = -ENOENT;
 				goto exit;
 			}
  * @sqdepth: depth of SQ
  *
  */
-enum irdma_status_code irdma_get_sqdepth(struct irdma_uk_attrs *uk_attrs,
+int irdma_get_sqdepth(struct irdma_uk_attrs *uk_attrs, u32 sq_size, u8 shift,
-					 u32 sq_size, u8 shift, u32 *sqdepth)
+		      u32 *sqdepth)
 {
 	*sqdepth = irdma_qp_round_up((sq_size << shift) + IRDMA_SQ_RSVD);
 	if (*sqdepth < (IRDMA_QP_SW_MIN_WQSIZE << shift))
 		*sqdepth = IRDMA_QP_SW_MIN_WQSIZE << shift;
 	else if (*sqdepth > uk_attrs->max_hw_wq_quanta)
-		return IRDMA_ERR_INVALID_SIZE;
+		return -EINVAL;
 	return 0;
 }
  * @shift: shift which determines size of WQE
  * @rqdepth: depth of RQ
  */
-enum irdma_status_code irdma_get_rqdepth(struct irdma_uk_attrs *uk_attrs,
+int irdma_get_rqdepth(struct irdma_uk_attrs *uk_attrs, u32 rq_size, u8 shift,
-					 u32 rq_size, u8 shift, u32 *rqdepth)
+		      u32 *rqdepth)
 {
 	*rqdepth = irdma_qp_round_up((rq_size << shift) + IRDMA_RQ_RSVD);
 	if (*rqdepth < (IRDMA_QP_SW_MIN_WQSIZE << shift))
 		*rqdepth = IRDMA_QP_SW_MIN_WQSIZE << shift;
 	else if (*rqdepth > uk_attrs->max_hw_rq_quanta)
-		return IRDMA_ERR_INVALID_SIZE;
+		return -EINVAL;
 	return 0;
 }
  * allowed. Then size of wqe * the number of wqes should be the
  * amount of memory allocated for sq and rq.
  */
-enum irdma_status_code irdma_uk_qp_init(struct irdma_qp_uk *qp,
+int irdma_uk_qp_init(struct irdma_qp_uk *qp, struct irdma_qp_uk_init_info *info)
-					struct irdma_qp_uk_init_info *info)
 {
-	enum irdma_status_code ret_code = 0;
+	int ret_code = 0;
 	u32 sq_ring_size;
 	u8 sqshift, rqshift;
 	qp->uk_attrs = info->uk_attrs;
 	if (info->max_sq_frag_cnt > qp->uk_attrs->max_hw_wq_frags ||
 	    info->max_rq_frag_cnt > qp->uk_attrs->max_hw_wq_frags)
-		return IRDMA_ERR_INVALID_FRAG_COUNT;
+		return -EINVAL;
 	irdma_get_wqe_shift(qp->uk_attrs, info->max_rq_frag_cnt, 0, &rqshift);
 	if (qp->uk_attrs->hw_rev == IRDMA_GEN_1) {
  * @signaled: signaled for completion
  * @post_sq: ring doorbell
  */
-enum irdma_status_code irdma_nop(struct irdma_qp_uk *qp, u64 wr_id,
+int irdma_nop(struct irdma_qp_uk *qp, u64 wr_id, bool signaled, bool post_sq)
-				 bool signaled, bool post_sq)
 {
 	__le64 *wqe;
 	u64 hdr;
 	wqe = irdma_qp_get_next_send_wqe(qp, &wqe_idx, IRDMA_QP_WQE_MIN_QUANTA,
 					 0, &info);
 	if (!wqe)
-		return IRDMA_ERR_QP_TOOMANY_WRS_POSTED;
+		return -ENOMEM;
 	irdma_clr_wqes(qp, wqe_idx);
  * @frag_cnt: number of fragments
  * @quanta: quanta for frag_cnt
  */
-enum irdma_status_code irdma_fragcnt_to_quanta_sq(u32 frag_cnt, u16 *quanta)
+int irdma_fragcnt_to_quanta_sq(u32 frag_cnt, u16 *quanta)
 {
 	switch (frag_cnt) {
 	case 0:
 		*quanta = 8;
 		break;
 	default:
-		return IRDMA_ERR_INVALID_FRAG_COUNT;
+		return -EINVAL;
 	}
 	return 0;
  * @frag_cnt: number of fragments
  * @wqe_size: size in bytes given frag_cnt
  */
-enum irdma_status_code irdma_fragcnt_to_wqesize_rq(u32 frag_cnt, u16 *wqe_size)
+int irdma_fragcnt_to_wqesize_rq(u32 frag_cnt, u16 *wqe_size)
 {
 	switch (frag_cnt) {
 	case 0:
 		*wqe_size = 256;
 		break;
 	default:
-		return IRDMA_ERR_INVALID_FRAG_COUNT;
+		return -EINVAL;
 	}
 	return 0;

drivers/infiniband/hw/irdma/user.h+28−34

@@ -270,29 +270,24 @@ struct irdma_cq_poll_info { · 269 unmodified lines
270	bool imm_valid:1;	270	bool imm_valid:1;
271	};	271	};
272		272
273	enum irdma_status_code irdma_uk_inline_rdma_write(struct irdma_qp_uk *qp,	273	int irdma_uk_inline_rdma_write(struct irdma_qp_uk *qp,
274	struct irdma_post_sq_info *info,	274	struct irdma_post_sq_info *info, bool post_sq);
275	bool post_sq);	275	int irdma_uk_inline_send(struct irdma_qp_uk *qp,
276	enum irdma_status_code irdma_uk_inline_send(struct irdma_qp_uk *qp,	276	struct irdma_post_sq_info *info, bool post_sq);
277	struct irdma_post_sq_info *info,	277	int irdma_uk_post_nop(struct irdma_qp_uk *qp, u64 wr_id, bool signaled,
278	bool post_sq);	278	bool post_sq);
279		279	int irdma_uk_post_receive(struct irdma_qp_uk *qp,
280	enum irdma_status_code irdma_uk_post_nop(struct irdma_qp_uk *qp, u64 wr_id,	280	struct irdma_post_rq_info *info);
281	bool signaled, bool post_sq);
282	enum irdma_status_code irdma_uk_post_receive(struct irdma_qp_uk *qp,
283	struct irdma_post_rq_info *info);
284	void irdma_uk_qp_post_wr(struct irdma_qp_uk *qp);	281	void irdma_uk_qp_post_wr(struct irdma_qp_uk *qp);
285	enum irdma_status_code irdma_uk_rdma_read(struct irdma_qp_uk *qp,	282	int irdma_uk_rdma_read(struct irdma_qp_uk qp, struct irdma_post_sq_info info,
286	struct irdma_post_sq_info *info,	283	bool inv_stag, bool post_sq);
287	bool inv_stag, bool post_sq);	284	int irdma_uk_rdma_write(struct irdma_qp_uk qp, struct irdma_post_sq_info info,
288	enum irdma_status_code irdma_uk_rdma_write(struct irdma_qp_uk *qp,	285	bool post_sq);
289	struct irdma_post_sq_info *info,	286	int irdma_uk_send(struct irdma_qp_uk qp, struct irdma_post_sq_info info,
290	bool post_sq);	287	bool post_sq);
291	enum irdma_status_code irdma_uk_send(struct irdma_qp_uk *qp,	288	int irdma_uk_stag_local_invalidate(struct irdma_qp_uk *qp,
292	struct irdma_post_sq_info *info, bool post_sq);	289	struct irdma_post_sq_info *info,
293	enum irdma_status_code irdma_uk_stag_local_invalidate(struct irdma_qp_uk *qp,	290	bool post_sq);
294	struct irdma_post_sq_info *info,
295	bool post_sq);
296		291
297	struct irdma_wqe_uk_ops {	292	struct irdma_wqe_uk_ops {
298	void (iw_copy_inline_data)(u8 dest, u8 *src, u32 len, u8 polarity);	293	void (iw_copy_inline_data)(u8 dest, u8 *src, u32 len, u8 polarity);
@@ -303,16 +298,16 @@ struct irdma_wqe_uk_ops { · 4 unmodified lines
303	struct irdma_bind_window *op_info);	298	struct irdma_bind_window *op_info);
304	};	299	};
305		300
306	enum irdma_status_code irdma_uk_cq_poll_cmpl(struct irdma_cq_uk *cq,	301	int irdma_uk_cq_poll_cmpl(struct irdma_cq_uk *cq,
307	struct irdma_cq_poll_info *info);	302	struct irdma_cq_poll_info *info);
308	void irdma_uk_cq_request_notification(struct irdma_cq_uk *cq,	303	void irdma_uk_cq_request_notification(struct irdma_cq_uk *cq,
309	enum irdma_cmpl_notify cq_notify);	304	enum irdma_cmpl_notify cq_notify);
310	void irdma_uk_cq_resize(struct irdma_cq_uk cq, void cq_base, int size);	305	void irdma_uk_cq_resize(struct irdma_cq_uk cq, void cq_base, int size);
311	void irdma_uk_cq_set_resized_cnt(struct irdma_cq_uk *qp, u16 cnt);	306	void irdma_uk_cq_set_resized_cnt(struct irdma_cq_uk *qp, u16 cnt);
312	void irdma_uk_cq_init(struct irdma_cq_uk *cq,	307	void irdma_uk_cq_init(struct irdma_cq_uk *cq,
313	struct irdma_cq_uk_init_info *info);	308	struct irdma_cq_uk_init_info *info);
314	enum irdma_status_code irdma_uk_qp_init(struct irdma_qp_uk *qp,	309	int irdma_uk_qp_init(struct irdma_qp_uk *qp,
315	struct irdma_qp_uk_init_info *info);	310	struct irdma_qp_uk_init_info *info);
316	struct irdma_sq_uk_wr_trk_info {	311	struct irdma_sq_uk_wr_trk_info {
317	u64 wrid;	312	u64 wrid;
318	u32 wr_len;	313	u32 wr_len;
@@ -413,16 +408,15 @@ __le64 irdma_qp_get_next_send_wqe(struct irdma_qp_uk qp, u32 *wqe_idx, · 94 unmodified lines
413	struct irdma_post_sq_info *info);	408	struct irdma_post_sq_info *info);
414	__le64 irdma_qp_get_next_recv_wqe(struct irdma_qp_uk qp, u32 *wqe_idx);	409	__le64 irdma_qp_get_next_recv_wqe(struct irdma_qp_uk qp, u32 *wqe_idx);
415	void irdma_uk_clean_cq(void q, struct irdma_cq_uk cq);	410	void irdma_uk_clean_cq(void q, struct irdma_cq_uk cq);
416	enum irdma_status_code irdma_nop(struct irdma_qp_uk *qp, u64 wr_id,	411	int irdma_nop(struct irdma_qp_uk *qp, u64 wr_id, bool signaled, bool post_sq);
417	bool signaled, bool post_sq);	412	int irdma_fragcnt_to_quanta_sq(u32 frag_cnt, u16 *quanta);
418	enum irdma_status_code irdma_fragcnt_to_quanta_sq(u32 frag_cnt, u16 *quanta);	413	int irdma_fragcnt_to_wqesize_rq(u32 frag_cnt, u16 *wqe_size);
419	enum irdma_status_code irdma_fragcnt_to_wqesize_rq(u32 frag_cnt, u16 *wqe_size);
420	void irdma_get_wqe_shift(struct irdma_uk_attrs *uk_attrs, u32 sge,	414	void irdma_get_wqe_shift(struct irdma_uk_attrs *uk_attrs, u32 sge,
421	u32 inline_data, u8 *shift);	415	u32 inline_data, u8 *shift);
422	enum irdma_status_code irdma_get_sqdepth(struct irdma_uk_attrs *uk_attrs,	416	int irdma_get_sqdepth(struct irdma_uk_attrs *uk_attrs, u32 sq_size, u8 shift,
423	u32 sq_size, u8 shift, u32 *wqdepth);	417	u32 *wqdepth);
424	enum irdma_status_code irdma_get_rqdepth(struct irdma_uk_attrs *uk_attrs,	418	int irdma_get_rqdepth(struct irdma_uk_attrs *uk_attrs, u32 rq_size, u8 shift,
425	u32 rq_size, u8 shift, u32 *wqdepth);	419	u32 *wqdepth);
426	void irdma_qp_push_wqe(struct irdma_qp_uk qp, __le64 wqe, u16 quanta,	420	void irdma_qp_push_wqe(struct irdma_qp_uk qp, __le64 wqe, u16 quanta,
427	u32 wqe_idx, bool post_sq);	421	u32 wqe_idx, bool post_sq);
428	void irdma_clr_wqes(struct irdma_qp_uk *qp, u32 qp_wqe_idx);	422	void irdma_clr_wqes(struct irdma_qp_uk *qp, u32 qp_wqe_idx);

drivers/infiniband/hw/irdma/utils.c+122−125

 			 void *ptr)
 {
 	struct in_ifaddr *ifa = ptr;
-	struct net_device *netdev = ifa->ifa_dev->dev;
+	struct net_device *real_dev, *netdev = ifa->ifa_dev->dev;
 	struct irdma_device *iwdev;
 	struct ib_device *ibdev;
 	u32 local_ipaddr;
-	ibdev = ib_device_get_by_netdev(netdev, RDMA_DRIVER_IRDMA);
+	real_dev = rdma_vlan_dev_real_dev(netdev);
+	if (!real_dev)
+		real_dev = netdev;
+	ibdev = ib_device_get_by_netdev(real_dev, RDMA_DRIVER_IRDMA);
 	if (!ibdev)
 		return NOTIFY_DONE;
 	iwdev = to_iwdev(ibdev);
 	local_ipaddr = ntohl(ifa->ifa_address);
 	ibdev_dbg(&iwdev->ibdev,
-		  "DEV: netdev %p event %lu local_ip=%pI4 MAC=%pM\n", netdev,
+		  "DEV: netdev %p event %lu local_ip=%pI4 MAC=%pM\n", real_dev,
-		  event, &local_ipaddr, netdev->dev_addr);
+		  event, &local_ipaddr, real_dev->dev_addr);
 	switch (event) {
 	case NETDEV_DOWN:
-		irdma_manage_arp_cache(iwdev->rf, netdev->dev_addr,
+		irdma_manage_arp_cache(iwdev->rf, real_dev->dev_addr,
 				       &local_ipaddr, true, IRDMA_ARP_DELETE);
-		irdma_if_notify(iwdev, netdev, &local_ipaddr, true, false);
+		irdma_if_notify(iwdev, real_dev, &local_ipaddr, true, false);
 		irdma_gid_change_event(&iwdev->ibdev);
 		break;
 	case NETDEV_UP:
 	case NETDEV_CHANGEADDR:
-		irdma_add_arp(iwdev->rf, &local_ipaddr, true, netdev->dev_addr);
+		irdma_add_arp(iwdev->rf, &local_ipaddr, true, real_dev->dev_addr);
-		irdma_if_notify(iwdev, netdev, &local_ipaddr, true, true);
+		irdma_if_notify(iwdev, real_dev, &local_ipaddr, true, true);
 		irdma_gid_change_event(&iwdev->ibdev);
 		break;
 	default:
 			  void *ptr)
 {
 	struct inet6_ifaddr *ifa = ptr;
-	struct net_device *netdev = ifa->idev->dev;
+	struct net_device *real_dev, *netdev = ifa->idev->dev;
 	struct irdma_device *iwdev;
 	struct ib_device *ibdev;
 	u32 local_ipaddr6[4];
-	ibdev = ib_device_get_by_netdev(netdev, RDMA_DRIVER_IRDMA);
+	real_dev = rdma_vlan_dev_real_dev(netdev);
+	if (!real_dev)
+		real_dev = netdev;
+	ibdev = ib_device_get_by_netdev(real_dev, RDMA_DRIVER_IRDMA);
 	if (!ibdev)
 		return NOTIFY_DONE;
 	iwdev = to_iwdev(ibdev);
 	irdma_copy_ip_ntohl(local_ipaddr6, ifa->addr.in6_u.u6_addr32);
 	ibdev_dbg(&iwdev->ibdev,
-		  "DEV: netdev %p event %lu local_ip=%pI6 MAC=%pM\n", netdev,
+		  "DEV: netdev %p event %lu local_ip=%pI6 MAC=%pM\n", real_dev,
-		  event, local_ipaddr6, netdev->dev_addr);
+		  event, local_ipaddr6, real_dev->dev_addr);
 	switch (event) {
 	case NETDEV_DOWN:
-		irdma_manage_arp_cache(iwdev->rf, netdev->dev_addr,
+		irdma_manage_arp_cache(iwdev->rf, real_dev->dev_addr,
 				       local_ipaddr6, false, IRDMA_ARP_DELETE);
-		irdma_if_notify(iwdev, netdev, local_ipaddr6, false, false);
+		irdma_if_notify(iwdev, real_dev, local_ipaddr6, false, false);
 		irdma_gid_change_event(&iwdev->ibdev);
 		break;
 	case NETDEV_UP:
 	case NETDEV_CHANGEADDR:
 		irdma_add_arp(iwdev->rf, local_ipaddr6, false,
-			      netdev->dev_addr);
+			      real_dev->dev_addr);
-		irdma_if_notify(iwdev, netdev, local_ipaddr6, false, true);
+		irdma_if_notify(iwdev, real_dev, local_ipaddr6, false, true);
 		irdma_gid_change_event(&iwdev->ibdev);
 		break;
 	default:
 		    void *ptr)
 {
 	struct neighbour *neigh = ptr;
+	struct net_device *real_dev, *netdev = (struct net_device *)neigh->dev;
 	struct irdma_device *iwdev;
 	struct ib_device *ibdev;
 	__be32 *p;
 	u32 local_ipaddr[4] = {};
 	bool ipv4 = true;
-	ibdev = ib_device_get_by_netdev((struct net_device *)neigh->dev,
+	real_dev = rdma_vlan_dev_real_dev(netdev);
-					RDMA_DRIVER_IRDMA);
+	if (!real_dev)
+		real_dev = netdev;
+	ibdev = ib_device_get_by_netdev(real_dev, RDMA_DRIVER_IRDMA);
 	if (!ibdev)
 		return NOTIFY_DONE;
  * @rf: RDMA PCI function
  * @cqp_request: cqp request to wait
  */
-static enum irdma_status_code irdma_wait_event(struct irdma_pci_f *rf,
+static int irdma_wait_event(struct irdma_pci_f *rf,
-					       struct irdma_cqp_request *cqp_request)
+			    struct irdma_cqp_request *cqp_request)
 {
 	struct irdma_cqp_timeout cqp_timeout = {};
 	bool cqp_error = false;
-	enum irdma_status_code err_code = 0;
+	int err_code = 0;
 	cqp_timeout.compl_cqp_cmds = rf->sc_dev.cqp_cmd_stats[IRDMA_OP_CMPL_CMDS];
 	do {
 			rf->reset = true;
 			rf->gen_ops.request_reset(rf);
 		}
-		return IRDMA_ERR_TIMEOUT;
+		return -ETIMEDOUT;
 	} while (1);
 	cqp_error = cqp_request->compl_info.error;
 	if (cqp_error) {
-		err_code = IRDMA_ERR_CQP_COMPL_ERROR;
+		err_code = -EIO;
 		if (cqp_request->compl_info.maj_err_code == 0xFFFF &&
 		    cqp_request->compl_info.min_err_code == 0x8029) {
 			if (!rf->reset) {
  * @rf: RDMA PCI function
  * @cqp_request: cqp request to process
  */
-enum irdma_status_code irdma_handle_cqp_op(struct irdma_pci_f *rf,
+int irdma_handle_cqp_op(struct irdma_pci_f *rf,
-					   struct irdma_cqp_request *cqp_request)
+			struct irdma_cqp_request *cqp_request)
 {
 	struct irdma_sc_dev *dev = &rf->sc_dev;
 	struct cqp_cmds_info *info = &cqp_request->info;
-	enum irdma_status_code status;
+	int status;
 	bool put_cqp_request = true;
 	if (rf->reset)
-		return IRDMA_ERR_NOT_READY;
+		return -EBUSY;
 	irdma_get_cqp_request(cqp_request);
 	status = irdma_process_cqp_cmd(dev, info);
  * @sdinfo: information for sd cqp
  *
  */
-enum irdma_status_code irdma_cqp_sds_cmd(struct irdma_sc_dev *dev,
+int irdma_cqp_sds_cmd(struct irdma_sc_dev *dev,
-					 struct irdma_update_sds_info *sdinfo)
+		      struct irdma_update_sds_info *sdinfo)
 {
 	struct irdma_cqp_request *cqp_request;
 	struct cqp_cmds_info *cqp_info;
 	struct irdma_pci_f *rf = dev_to_rf(dev);
-	enum irdma_status_code status;
+	int status;
 	cqp_request = irdma_alloc_and_get_cqp_request(&rf->cqp, true);
 	if (!cqp_request)
-		return IRDMA_ERR_NO_MEMORY;
+		return -ENOMEM;
 	cqp_info = &cqp_request->info;
 	memcpy(&cqp_info->in.u.update_pe_sds.info, sdinfo,
  * @qp: hardware control qp
  * @op: suspend or resume
  */
-enum irdma_status_code irdma_cqp_qp_suspend_resume(struct irdma_sc_qp *qp,
+int irdma_cqp_qp_suspend_resume(struct irdma_sc_qp *qp, u8 op)
-						   u8 op)
 {
 	struct irdma_sc_dev *dev = qp->dev;
 	struct irdma_cqp_request *cqp_request;
 	struct irdma_sc_cqp *cqp = dev->cqp;
 	struct cqp_cmds_info *cqp_info;
 	struct irdma_pci_f *rf = dev_to_rf(dev);
-	enum irdma_status_code status;
+	int status;
 	cqp_request = irdma_alloc_and_get_cqp_request(&rf->cqp, false);
 	if (!cqp_request)
-		return IRDMA_ERR_NO_MEMORY;
+		return -ENOMEM;
 	cqp_info = &cqp_request->info;
 	cqp_info->cqp_cmd = op;
  * @val_mem: buffer for fpm
  * @hmc_fn_id: function id for fpm
  */
-enum irdma_status_code
+int irdma_cqp_query_fpm_val_cmd(struct irdma_sc_dev *dev,
-irdma_cqp_query_fpm_val_cmd(struct irdma_sc_dev *dev,
+				struct irdma_dma_mem *val_mem, u8 hmc_fn_id)
-			    struct irdma_dma_mem *val_mem, u8 hmc_fn_id)
 {
 	struct irdma_cqp_request *cqp_request;
 	struct cqp_cmds_info *cqp_info;
 	struct irdma_pci_f *rf = dev_to_rf(dev);
-	enum irdma_status_code status;
+	int status;
 	cqp_request = irdma_alloc_and_get_cqp_request(&rf->cqp, true);
 	if (!cqp_request)
-		return IRDMA_ERR_NO_MEMORY;
+		return -ENOMEM;
 	cqp_info = &cqp_request->info;
 	cqp_request->param = NULL;
  * @val_mem: buffer with fpm values
  * @hmc_fn_id: function id for fpm
  */
-enum irdma_status_code
+int irdma_cqp_commit_fpm_val_cmd(struct irdma_sc_dev *dev,
-irdma_cqp_commit_fpm_val_cmd(struct irdma_sc_dev *dev,
+				 struct irdma_dma_mem *val_mem, u8 hmc_fn_id)
-			     struct irdma_dma_mem *val_mem, u8 hmc_fn_id)
 {
 	struct irdma_cqp_request *cqp_request;
 	struct cqp_cmds_info *cqp_info;
 	struct irdma_pci_f *rf = dev_to_rf(dev);
-	enum irdma_status_code status;
+	int status;
 	cqp_request = irdma_alloc_and_get_cqp_request(&rf->cqp, true);
 	if (!cqp_request)
-		return IRDMA_ERR_NO_MEMORY;
+		return -ENOMEM;
 	cqp_info = &cqp_request->info;
 	cqp_request->param = NULL;
  * @dev: device pointer
  * @cq: pointer to created cq
  */
-enum irdma_status_code irdma_cqp_cq_create_cmd(struct irdma_sc_dev *dev,
+int irdma_cqp_cq_create_cmd(struct irdma_sc_dev *dev, struct irdma_sc_cq *cq)
-					       struct irdma_sc_cq *cq)
 {
 	struct irdma_pci_f *rf = dev_to_rf(dev);
 	struct irdma_cqp *iwcqp = &rf->cqp;
 	struct irdma_cqp_request *cqp_request;
 	struct cqp_cmds_info *cqp_info;
-	enum irdma_status_code status;
+	int status;
 	cqp_request = irdma_alloc_and_get_cqp_request(iwcqp, true);
 	if (!cqp_request)
-		return IRDMA_ERR_NO_MEMORY;
+		return -ENOMEM;
 	cqp_info = &cqp_request->info;
 	cqp_info->cqp_cmd = IRDMA_OP_CQ_CREATE;
  * @dev: device pointer
  * @qp: pointer to created qp
  */
-enum irdma_status_code irdma_cqp_qp_create_cmd(struct irdma_sc_dev *dev,
+int irdma_cqp_qp_create_cmd(struct irdma_sc_dev *dev, struct irdma_sc_qp *qp)
-					       struct irdma_sc_qp *qp)
 {
 	struct irdma_pci_f *rf = dev_to_rf(dev);
 	struct irdma_cqp *iwcqp = &rf->cqp;
 	struct irdma_cqp_request *cqp_request;
 	struct cqp_cmds_info *cqp_info;
 	struct irdma_create_qp_info *qp_info;
-	enum irdma_status_code status;
+	int status;
 	cqp_request = irdma_alloc_and_get_cqp_request(iwcqp, true);
 	if (!cqp_request)
-		return IRDMA_ERR_NO_MEMORY;
+		return -ENOMEM;
 	cqp_info = &cqp_request->info;
 	qp_info = &cqp_request->info.in.u.qp_create.info;
 {
 	struct irdma_cqp_request *cqp_request;
 	struct cqp_cmds_info *cqp_info;
-	enum irdma_status_code status;
+	int status;
 	if (qp->push_idx == IRDMA_INVALID_PUSH_PAGE_INDEX)
 		return;
  * @info: info for modify qp
  * @wait: flag to wait or not for modify qp completion
  */
-enum irdma_status_code irdma_hw_modify_qp(struct irdma_device *iwdev,
+int irdma_hw_modify_qp(struct irdma_device *iwdev, struct irdma_qp *iwqp,
-					  struct irdma_qp *iwqp,
+		       struct irdma_modify_qp_info *info, bool wait)
-					  struct irdma_modify_qp_info *info,
-					  bool wait)
 {
-	enum irdma_status_code status;
+	int status;
 	struct irdma_pci_f *rf = iwdev->rf;
 	struct irdma_cqp_request *cqp_request;
 	struct cqp_cmds_info *cqp_info;
 	cqp_request = irdma_alloc_and_get_cqp_request(&rf->cqp, wait);
 	if (!cqp_request)
-		return IRDMA_ERR_NO_MEMORY;
+		return -ENOMEM;
 	if (!wait) {
 		cqp_request->callback_fcn = irdma_hw_modify_qp_callback;
 				cqp_request = irdma_alloc_and_get_cqp_request(&rf->cqp,
 									      wait);
 				if (!cqp_request)
-					return IRDMA_ERR_NO_MEMORY;
+					return -ENOMEM;
 				cqp_info = &cqp_request->info;
 				m_info = &cqp_info->in.u.qp_modify.info;
  * @dev: device pointer
  * @qp: pointer to qp
  */
-enum irdma_status_code irdma_cqp_qp_destroy_cmd(struct irdma_sc_dev *dev, struct irdma_sc_qp *qp)
+int irdma_cqp_qp_destroy_cmd(struct irdma_sc_dev *dev, struct irdma_sc_qp *qp)
 {
 	struct irdma_pci_f *rf = dev_to_rf(dev);
 	struct irdma_cqp *iwcqp = &rf->cqp;
 	struct irdma_cqp_request *cqp_request;
 	struct cqp_cmds_info *cqp_info;
-	enum irdma_status_code status;
+	int status;
 	cqp_request = irdma_alloc_and_get_cqp_request(iwcqp, true);
 	if (!cqp_request)
-		return IRDMA_ERR_NO_MEMORY;
+		return -ENOMEM;
 	cqp_info = &cqp_request->info;
 	memset(cqp_info, 0, sizeof(*cqp_info));
  * irdma_init_hash_desc - initialize hash for crc calculation
  * @desc: cryption type
  */
-enum irdma_status_code irdma_init_hash_desc(struct shash_desc **desc)
+int irdma_init_hash_desc(struct shash_desc **desc)
 {
 	struct crypto_shash *tfm;
 	struct shash_desc *tdesc;
 	tfm = crypto_alloc_shash("crc32c", 0, 0);
 	if (IS_ERR(tfm))
-		return IRDMA_ERR_MPA_CRC;
+		return -EINVAL;
 	tdesc = kzalloc(sizeof(*tdesc) + crypto_shash_descsize(tfm),
 			GFP_KERNEL);
 	if (!tdesc) {
 		crypto_free_shash(tfm);
-		return IRDMA_ERR_MPA_CRC;
+		return -EINVAL;
 	}
 	tdesc->tfm = tfm;
  * @len: length of buffer
  * @val: value to be compared
  */
-enum irdma_status_code irdma_ieq_check_mpacrc(struct shash_desc *desc,
+int irdma_ieq_check_mpacrc(struct shash_desc *desc, void *addr, u32 len,
-					      void *addr, u32 len, u32 val)
+			   u32 val)
 {
 	u32 crc = 0;
 	int ret;
-	enum irdma_status_code ret_code = 0;
+	int ret_code = 0;
 	crypto_shash_init(desc);
 	ret = crypto_shash_update(desc, addr, len);
 	if (!ret)
 		crypto_shash_final(desc, (u8 *)&crc);
 	if (crc != val)
-		ret_code = IRDMA_ERR_MPA_CRC;
+		ret_code = -EINVAL;
 	return ret_code;
 }
  * @info: to get information
  * @buf: puda buffer
  */
-static enum irdma_status_code
+static int irdma_gen1_puda_get_tcpip_info(struct irdma_puda_cmpl_info *info,
-irdma_gen1_puda_get_tcpip_info(struct irdma_puda_cmpl_info *info,
+					  struct irdma_puda_buf *buf)
-			       struct irdma_puda_buf *buf)
 {
 	struct iphdr *iph;
 	struct ipv6hdr *ip6h;
 		ibdev_dbg(to_ibdev(buf->vsi->dev),
 			  "ERR: payload_len = 0x%x totallen expected0x%x\n",
 			  info->payload_len, buf->totallen);
-		return IRDMA_ERR_INVALID_SIZE;
+		return -EINVAL;
 	}
 	buf->tcphlen = tcph->doff << 2;
  * @info: to get information
  * @buf: puda buffer
  */
-enum irdma_status_code
+int irdma_puda_get_tcpip_info(struct irdma_puda_cmpl_info *info,
-irdma_puda_get_tcpip_info(struct irdma_puda_cmpl_info *info,
+			      struct irdma_puda_buf *buf)
-			  struct irdma_puda_buf *buf)
 {
 	struct tcphdr *tcph;
 	u32 pkt_len;
  * @pestat: pointer to stats info
  * @wait: flag to wait or not wait for stats
  */
-enum irdma_status_code
+int irdma_cqp_gather_stats_cmd(struct irdma_sc_dev *dev,
-irdma_cqp_gather_stats_cmd(struct irdma_sc_dev *dev,
+			       struct irdma_vsi_pestat *pestat, bool wait)
-			   struct irdma_vsi_pestat *pestat, bool wait)
 {
 	struct irdma_pci_f *rf = dev_to_rf(dev);
 	struct irdma_cqp *iwcqp = &rf->cqp;
 	struct irdma_cqp_request *cqp_request;
 	struct cqp_cmds_info *cqp_info;
-	enum irdma_status_code status;
+	int status;
 	cqp_request = irdma_alloc_and_get_cqp_request(iwcqp, wait);
 	if (!cqp_request)
-		return IRDMA_ERR_NO_MEMORY;
+		return -ENOMEM;
 	cqp_info = &cqp_request->info;
 	memset(cqp_info, 0, sizeof(*cqp_info));
  * @cmd: command to allocate or free
  * @stats_info: pointer to allocate stats info
  */
-enum irdma_status_code
+int irdma_cqp_stats_inst_cmd(struct irdma_sc_vsi *vsi, u8 cmd,
-irdma_cqp_stats_inst_cmd(struct irdma_sc_vsi *vsi, u8 cmd,
+			     struct irdma_stats_inst_info *stats_info)
-			 struct irdma_stats_inst_info *stats_info)
 {
 	struct irdma_pci_f *rf = dev_to_rf(vsi->dev);
 	struct irdma_cqp *iwcqp = &rf->cqp;
 	struct irdma_cqp_request *cqp_request;
 	struct cqp_cmds_info *cqp_info;
-	enum irdma_status_code status;
+	int status;
 	bool wait = false;
 	if (cmd == IRDMA_OP_STATS_ALLOCATE)
 		wait = true;
 	cqp_request = irdma_alloc_and_get_cqp_request(iwcqp, wait);
 	if (!cqp_request)
-		return IRDMA_ERR_NO_MEMORY;
+		return -ENOMEM;
 	cqp_info = &cqp_request->info;
 	memset(cqp_info, 0, sizeof(*cqp_info));
  * @sc_ceq: pointer to ceq structure
  * @op: Create or Destroy
  */
-enum irdma_status_code irdma_cqp_ceq_cmd(struct irdma_sc_dev *dev,
+int irdma_cqp_ceq_cmd(struct irdma_sc_dev *dev, struct irdma_sc_ceq *sc_ceq,
-					 struct irdma_sc_ceq *sc_ceq, u8 op)
+		      u8 op)
 {
 	struct irdma_cqp_request *cqp_request;
 	struct cqp_cmds_info *cqp_info;
 	struct irdma_pci_f *rf = dev_to_rf(dev);
-	enum irdma_status_code status;
+	int status;
 	cqp_request = irdma_alloc_and_get_cqp_request(&rf->cqp, true);
 	if (!cqp_request)
-		return IRDMA_ERR_NO_MEMORY;
+		return -ENOMEM;
 	cqp_info = &cqp_request->info;
 	cqp_info->post_sq = 1;
  * @sc_aeq: pointer to aeq structure
  * @op: Create or Destroy
  */
-enum irdma_status_code irdma_cqp_aeq_cmd(struct irdma_sc_dev *dev,
+int irdma_cqp_aeq_cmd(struct irdma_sc_dev *dev, struct irdma_sc_aeq *sc_aeq,
-					 struct irdma_sc_aeq *sc_aeq, u8 op)
+		      u8 op)
 {
 	struct irdma_cqp_request *cqp_request;
 	struct cqp_cmds_info *cqp_info;
 	struct irdma_pci_f *rf = dev_to_rf(dev);
-	enum irdma_status_code status;
+	int status;
 	cqp_request = irdma_alloc_and_get_cqp_request(&rf->cqp, true);
 	if (!cqp_request)
-		return IRDMA_ERR_NO_MEMORY;
+		return -ENOMEM;
 	cqp_info = &cqp_request->info;
 	cqp_info->post_sq = 1;
  * @cmd: Add, modify or delete
  * @node_info: pointer to ws node info
  */
-enum irdma_status_code
+int irdma_cqp_ws_node_cmd(struct irdma_sc_dev *dev, u8 cmd,
-irdma_cqp_ws_node_cmd(struct irdma_sc_dev *dev, u8 cmd,
+			  struct irdma_ws_node_info *node_info)
-		      struct irdma_ws_node_info *node_info)
 {
 	struct irdma_pci_f *rf = dev_to_rf(dev);
 	struct irdma_cqp *iwcqp = &rf->cqp;
 	struct irdma_sc_cqp *cqp = &iwcqp->sc_cqp;
 	struct irdma_cqp_request *cqp_request;
 	struct cqp_cmds_info *cqp_info;
-	enum irdma_status_code status;
+	int status;
 	bool poll;
 	if (!rf->sc_dev.ceq_valid)
 	cqp_request = irdma_alloc_and_get_cqp_request(iwcqp, !poll);
 	if (!cqp_request)
-		return IRDMA_ERR_NO_MEMORY;
+		return -ENOMEM;
 	cqp_info = &cqp_request->info;
 	memset(cqp_info, 0, sizeof(*cqp_info));
 {
 	struct irdma_cqp_request *cqp_request;
 	struct cqp_cmds_info *cqp_info;
-	enum irdma_status_code status;
+	int status;
 	if (cmd != IRDMA_OP_AH_CREATE && cmd != IRDMA_OP_AH_DESTROY)
 		return -EINVAL;
  * @ah_ret: Returned pointer to address handle if created
  *
  */
-enum irdma_status_code irdma_puda_create_ah(struct irdma_sc_dev *dev,
+int irdma_puda_create_ah(struct irdma_sc_dev *dev,
-					    struct irdma_ah_info *ah_info,
+			 struct irdma_ah_info *ah_info, bool wait,
-					    bool wait, enum puda_rsrc_type type,
+			 enum puda_rsrc_type type, void *cb_param,
-					    void *cb_param,
+			 struct irdma_sc_ah **ah_ret)
-					    struct irdma_sc_ah **ah_ret)
 {
 	struct irdma_sc_ah *ah;
 	struct irdma_pci_f *rf = dev_to_rf(dev);
 	ah = kzalloc(sizeof(*ah), GFP_ATOMIC);
 	*ah_ret = ah;
 	if (!ah)
-		return IRDMA_ERR_NO_MEMORY;
+		return -ENOMEM;
 	err = irdma_alloc_rsrc(rf, rf->allocated_ahs, rf->max_ah,
 			       &ah_info->ah_idx, &rf->next_ah);
 err_free:
 	kfree(ah);
 	*ah_ret = NULL;
-	return IRDMA_ERR_NO_MEMORY;
+	return -ENOMEM;
 }
 /**
  * @pprm: pble resource manager
  * @pchunk: chunk of memory to add
  */
-enum irdma_status_code irdma_prm_add_pble_mem(struct irdma_pble_prm *pprm,
+int irdma_prm_add_pble_mem(struct irdma_pble_prm *pprm,
-					      struct irdma_chunk *pchunk)
+			   struct irdma_chunk *pchunk)
 {
 	u64 sizeofbitmap;
 	if (pchunk->size & 0xfff)
-		return IRDMA_ERR_PARAM;
+		return -EINVAL;
 	sizeofbitmap = (u64)pchunk->size >> pprm->pble_shift;
 	pchunk->bitmapbuf = bitmap_zalloc(sizeofbitmap, GFP_KERNEL);
 	if (!pchunk->bitmapbuf)
-		return IRDMA_ERR_NO_MEMORY;
+		return -ENOMEM;
 	pchunk->sizeofbitmap = sizeofbitmap;
 	/* each pble is 8 bytes hence shift by 3 */
  * @vaddr: returns virtual address of pble memory
  * @fpm_addr: returns fpm address of pble memory
  */
-enum irdma_status_code
+int irdma_prm_get_pbles(struct irdma_pble_prm *pprm,
-irdma_prm_get_pbles(struct irdma_pble_prm *pprm,
+			struct irdma_pble_chunkinfo *chunkinfo, u64 mem_size,
-		    struct irdma_pble_chunkinfo *chunkinfo, u64 mem_size,
+			u64 **vaddr, u64 *fpm_addr)
-		    u64 **vaddr, u64 *fpm_addr)
 {
 	u64 bits_needed;
 	u64 bit_idx = PBLE_INVALID_IDX;
 	if (!pchunk || bit_idx >= pchunk->sizeofbitmap) {
 		spin_unlock_irqrestore(&pprm->prm_lock, flags);
-		return IRDMA_ERR_NO_MEMORY;
+		return -ENOMEM;
 	}
 	bitmap_set(pchunk->bitmapbuf, bit_idx, bits_needed);
 	spin_unlock_irqrestore(&pprm->prm_lock, flags);
 }
-enum irdma_status_code irdma_map_vm_page_list(struct irdma_hw *hw, void *va,
+int irdma_map_vm_page_list(struct irdma_hw *hw, void *va, dma_addr_t *pg_dma,
-					      dma_addr_t *pg_dma, u32 pg_cnt)
+			   u32 pg_cnt)
 {
 	struct page *vm_page;
 	int i;
 err:
 	irdma_unmap_vm_page_list(hw, pg_dma, i);
-	return IRDMA_ERR_NO_MEMORY;
+	return -ENOMEM;
 }
 void irdma_unmap_vm_page_list(struct irdma_hw *hw, dma_addr_t *pg_dma, u32 pg_cnt)
  * @chunk: chunk to add for paged memory
  * @pg_cnt: number of pages needed
  */
-enum irdma_status_code irdma_pble_get_paged_mem(struct irdma_chunk *chunk,
+int irdma_pble_get_paged_mem(struct irdma_chunk *chunk, u32 pg_cnt)
-						u32 pg_cnt)
 {
 	u32 size;
 	void *va;
 	chunk->dmainfo.dmaaddrs = kzalloc(pg_cnt << 3, GFP_KERNEL);
 	if (!chunk->dmainfo.dmaaddrs)
-		return IRDMA_ERR_NO_MEMORY;
+		return -ENOMEM;
 	size = PAGE_SIZE * pg_cnt;
 	va = vmalloc(size);
 	kfree(chunk->dmainfo.dmaaddrs);
 	chunk->dmainfo.dmaaddrs = NULL;
-	return IRDMA_ERR_NO_MEMORY;
+	return -ENOMEM;
 }
 /**

drivers/infiniband/hw/irdma/verbs.c+213−178

@@ -256,7 +256,7 @@ static void irdma_alloc_push_page(struct irdma_qp *iwqp) · 255 unmodified lines
256	struct cqp_cmds_info *cqp_info;	256	struct cqp_cmds_info *cqp_info;
257	struct irdma_device *iwdev = iwqp->iwdev;	257	struct irdma_device *iwdev = iwqp->iwdev;
258	struct irdma_sc_qp *qp = &iwqp->sc_qp;	258	struct irdma_sc_qp *qp = &iwqp->sc_qp;
259	enum irdma_status_code status;	259	int status;
260		260
261	cqp_request = irdma_alloc_and_get_cqp_request(&iwdev->rf->cqp, true);	261	cqp_request = irdma_alloc_and_get_cqp_request(&iwdev->rf->cqp, true);
262	if (!cqp_request)	262	if (!cqp_request)
@@ -592,7 +592,7 @@ static int irdma_setup_kmode_qp(struct irdma_device *iwdev, · 329 unmodified lines
592	u32 sqdepth, rqdepth;	592	u32 sqdepth, rqdepth;
593	u8 sqshift, rqshift;	593	u8 sqshift, rqshift;
594	u32 size;	594	u32 size;
595	enum irdma_status_code status;	595	int status;
596	struct irdma_qp_uk_init_info *ukinfo = &info->qp_uk_init_info;	596	struct irdma_qp_uk_init_info *ukinfo = &info->qp_uk_init_info;
597	struct irdma_uk_attrs *uk_attrs = &iwdev->rf->sc_dev.hw_attrs.uk_attrs;	597	struct irdma_uk_attrs *uk_attrs = &iwdev->rf->sc_dev.hw_attrs.uk_attrs;
598		598
@@ -603,7 +603,7 @@ static int irdma_setup_kmode_qp(struct irdma_device *iwdev, · 4 unmodified lines
603	status = irdma_get_sqdepth(uk_attrs, ukinfo->sq_size, sqshift,	603	status = irdma_get_sqdepth(uk_attrs, ukinfo->sq_size, sqshift,
604	&sqdepth);	604	&sqdepth);
605	if (status)	605	if (status)
606	return -ENOMEM;	606	return status;
607		607
608	if (uk_attrs->hw_rev == IRDMA_GEN_1)	608	if (uk_attrs->hw_rev == IRDMA_GEN_1)
609	rqshift = IRDMA_MAX_RQ_WQE_SHIFT_GEN1;	609	rqshift = IRDMA_MAX_RQ_WQE_SHIFT_GEN1;
@@ -614,7 +614,7 @@ static int irdma_setup_kmode_qp(struct irdma_device *iwdev, · 4 unmodified lines
614	status = irdma_get_rqdepth(uk_attrs, ukinfo->rq_size, rqshift,	614	status = irdma_get_rqdepth(uk_attrs, ukinfo->rq_size, rqshift,
615	&rqdepth);	615	&rqdepth);
616	if (status)	616	if (status)
617	return -ENOMEM;	617	return status;
618		618
619	iwqp->kqp.sq_wrid_mem =	619	iwqp->kqp.sq_wrid_mem =
620	kcalloc(sqdepth, sizeof(*iwqp->kqp.sq_wrid_mem), GFP_KERNEL);	620	kcalloc(sqdepth, sizeof(*iwqp->kqp.sq_wrid_mem), GFP_KERNEL);
@@ -668,7 +668,7 @@ static int irdma_cqp_create_qp_cmd(struct irdma_qp *iwqp) · 47 unmodified lines
668	struct irdma_cqp_request *cqp_request;	668	struct irdma_cqp_request *cqp_request;
669	struct cqp_cmds_info *cqp_info;	669	struct cqp_cmds_info *cqp_info;
670	struct irdma_create_qp_info *qp_info;	670	struct irdma_create_qp_info *qp_info;
671	enum irdma_status_code status;	671	int status;
672		672
673	cqp_request = irdma_alloc_and_get_cqp_request(&rf->cqp, true);	673	cqp_request = irdma_alloc_and_get_cqp_request(&rf->cqp, true);
674	if (!cqp_request)	674	if (!cqp_request)
@@ -688,7 +688,7 @@ static int irdma_cqp_create_qp_cmd(struct irdma_qp *iwqp) · 13 unmodified lines
688	status = irdma_handle_cqp_op(rf, cqp_request);	688	status = irdma_handle_cqp_op(rf, cqp_request);
689	irdma_put_cqp_request(&rf->cqp, cqp_request);	689	irdma_put_cqp_request(&rf->cqp, cqp_request);
690		690
691	return status ? -ENOMEM : 0;	691	return status;
692	}	692	}
693		693
694	static void irdma_roce_fill_and_set_qpctx_info(struct irdma_qp *iwqp,	694	static void irdma_roce_fill_and_set_qpctx_info(struct irdma_qp *iwqp,
@@ -806,7 +806,6 @@ static int irdma_create_qp(struct ib_qp *ibqp, · 111 unmodified lines
806	struct irdma_create_qp_req req;	806	struct irdma_create_qp_req req;
807	struct irdma_create_qp_resp uresp = {};	807	struct irdma_create_qp_resp uresp = {};
808	u32 qp_num = 0;	808	u32 qp_num = 0;
809	enum irdma_status_code ret;
810	int err_code;	809	int err_code;
811	int sq_size;	810	int sq_size;
812	int rq_size;	811	int rq_size;
@@ -936,9 +935,8 @@ static int irdma_create_qp(struct ib_qp *ibqp, · 123 unmodified lines
936	if (dev->hw_attrs.uk_attrs.hw_rev > IRDMA_GEN_1)	935	if (dev->hw_attrs.uk_attrs.hw_rev > IRDMA_GEN_1)
937	init_info.qp_uk_init_info.qp_caps \|= IRDMA_PUSH_MODE;	936	init_info.qp_uk_init_info.qp_caps \|= IRDMA_PUSH_MODE;
938		937
939	ret = irdma_sc_qp_init(qp, &init_info);	938	err_code = irdma_sc_qp_init(qp, &init_info);
940	if (ret) {	939	if (err_code) {
941	err_code = -EPROTO;
942	ibdev_dbg(&iwdev->ibdev, "VERBS: qp_init fail\n");	940	ibdev_dbg(&iwdev->ibdev, "VERBS: qp_init fail\n");
943	goto error;	941	goto error;
944	}	942	}
@@ -1189,7 +1187,7 @@ int irdma_modify_qp_roce(struct ib_qp ibqp, struct ib_qp_attr attr, · 244 unmodified lines
1189	if (ret)	1187	if (ret)
1190	return ret;	1188	return ret;
1191		1189
1192	if (vlan_id >= VLAN_N_VID && iwdev->dcb)	1190	if (vlan_id >= VLAN_N_VID && iwdev->dcb_vlan_mode)
1193	vlan_id = 0;	1191	vlan_id = 0;
1194	if (vlan_id < VLAN_N_VID) {	1192	if (vlan_id < VLAN_N_VID) {
1195	udp_info->insert_vlan_tag = true;	1193	udp_info->insert_vlan_tag = true;
@@ -1202,7 +1200,7 @@ int irdma_modify_qp_roce(struct ib_qp ibqp, struct ib_qp_attr attr, · 6 unmodified lines
1202	av->attrs = attr->ah_attr;	1200	av->attrs = attr->ah_attr;
1203	rdma_gid2ip((struct sockaddr *)&av->sgid_addr, &sgid_attr->gid);	1201	rdma_gid2ip((struct sockaddr *)&av->sgid_addr, &sgid_attr->gid);
1204	rdma_gid2ip((struct sockaddr *)&av->dgid_addr, &attr->ah_attr.grh.dgid);	1202	rdma_gid2ip((struct sockaddr *)&av->dgid_addr, &attr->ah_attr.grh.dgid);
1205	if (av->sgid_addr.saddr.sa_family == AF_INET6) {	1203	if (av->net_type == RDMA_NETWORK_IPV6) {
1206	__be32 *daddr =	1204	__be32 *daddr =
1207	av->dgid_addr.saddr_in6.sin6_addr.in6_u.u6_addr32;	1205	av->dgid_addr.saddr_in6.sin6_addr.in6_u.u6_addr32;
1208	__be32 *saddr =	1206	__be32 *saddr =
@@ -1218,7 +1216,7 @@ int irdma_modify_qp_roce(struct ib_qp ibqp, struct ib_qp_attr attr, · 9 unmodified lines
1218	&local_ip[0],	1216	&local_ip[0],
1219	false, NULL,	1217	false, NULL,
1220	IRDMA_ARP_RESOLVE);	1218	IRDMA_ARP_RESOLVE);
1221	} else {	1219	} else if (av->net_type == RDMA_NETWORK_IPV4) {
1222	__be32 saddr = av->sgid_addr.saddr_in.sin_addr.s_addr;	1220	__be32 saddr = av->sgid_addr.saddr_in.sin_addr.s_addr;
1223	__be32 daddr = av->dgid_addr.saddr_in.sin_addr.s_addr;	1221	__be32 daddr = av->dgid_addr.saddr_in.sin_addr.s_addr;
1224		1222
@@ -1792,7 +1790,6 @@ static int irdma_resize_cq(struct ib_cq *ibcq, int entries, · 567 unmodified lines
1792	struct irdma_device *iwdev;	1790	struct irdma_device *iwdev;
1793	struct irdma_pci_f *rf;	1791	struct irdma_pci_f *rf;
1794	struct irdma_cq_buf *cq_buf = NULL;	1792	struct irdma_cq_buf *cq_buf = NULL;
1795	enum irdma_status_code status = 0;
1796	unsigned long flags;	1793	unsigned long flags;
1797	int ret;	1794	int ret;
1798		1795
@@ -1885,12 +1882,10 @@ static int irdma_resize_cq(struct ib_cq *ibcq, int entries, · 86 unmodified lines
1885	cqp_info->in.u.cq_modify.cq = &iwcq->sc_cq;	1882	cqp_info->in.u.cq_modify.cq = &iwcq->sc_cq;
1886	cqp_info->in.u.cq_modify.scratch = (uintptr_t)cqp_request;	1883	cqp_info->in.u.cq_modify.scratch = (uintptr_t)cqp_request;
1887	cqp_info->post_sq = 1;	1884	cqp_info->post_sq = 1;
1888	status = irdma_handle_cqp_op(rf, cqp_request);	1885	ret = irdma_handle_cqp_op(rf, cqp_request);
1889	irdma_put_cqp_request(&rf->cqp, cqp_request);	1886	irdma_put_cqp_request(&rf->cqp, cqp_request);
1890	if (status) {	1887	if (ret)
1891	ret = -EPROTO;
1892	goto error;	1888	goto error;
1893	}
1894		1889
1895	spin_lock_irqsave(&iwcq->lock, flags);	1890	spin_lock_irqsave(&iwcq->lock, flags);
1896	if (cq_buf) {	1891	if (cq_buf) {
@@ -1945,7 +1940,6 @@ static int irdma_create_cq(struct ib_cq *ibcq, · 48 unmodified lines
1945	struct irdma_sc_cq *cq;	1940	struct irdma_sc_cq *cq;
1946	struct irdma_sc_dev *dev = &rf->sc_dev;	1941	struct irdma_sc_dev *dev = &rf->sc_dev;
1947	struct irdma_cq_init_info info = {};	1942	struct irdma_cq_init_info info = {};
1948	enum irdma_status_code status;
1949	struct irdma_cqp_request *cqp_request;	1943	struct irdma_cqp_request *cqp_request;
1950	struct cqp_cmds_info *cqp_info;	1944	struct cqp_cmds_info *cqp_info;
1951	struct irdma_cq_uk_init_info *ukinfo = &info.cq_uk_init_info;	1945	struct irdma_cq_uk_init_info *ukinfo = &info.cq_uk_init_info;
@@ -2095,12 +2089,10 @@ static int irdma_create_cq(struct ib_cq *ibcq, · 143 unmodified lines
2095	cqp_info->in.u.cq_create.cq = cq;	2089	cqp_info->in.u.cq_create.cq = cq;
2096	cqp_info->in.u.cq_create.check_overflow = true;	2090	cqp_info->in.u.cq_create.check_overflow = true;
2097	cqp_info->in.u.cq_create.scratch = (uintptr_t)cqp_request;	2091	cqp_info->in.u.cq_create.scratch = (uintptr_t)cqp_request;
2098	status = irdma_handle_cqp_op(rf, cqp_request);	2092	err_code = irdma_handle_cqp_op(rf, cqp_request);
2099	irdma_put_cqp_request(&rf->cqp, cqp_request);	2093	irdma_put_cqp_request(&rf->cqp, cqp_request);
2100	if (status) {	2094	if (err_code)
2101	err_code = -ENOMEM;
2102	goto cq_free_rsrc;	2095	goto cq_free_rsrc;
2103	}
2104		2096
2105	if (udata) {	2097	if (udata) {
2106	struct irdma_create_cq_resp resp = {};	2098	struct irdma_create_cq_resp resp = {};
@@ -2309,14 +2301,14 @@ static int irdma_setup_pbles(struct irdma_pci_f rf, struct irdma_mr iwmr, · 202 unmodified lines
2309	struct irdma_pble_alloc *palloc = &iwpbl->pble_alloc;	2301	struct irdma_pble_alloc *palloc = &iwpbl->pble_alloc;
2310	struct irdma_pble_info *pinfo;	2302	struct irdma_pble_info *pinfo;
2311	u64 *pbl;	2303	u64 *pbl;
2312	enum irdma_status_code status;	2304	int status;
2313	enum irdma_pble_level level = PBLE_LEVEL_1;	2305	enum irdma_pble_level level = PBLE_LEVEL_1;
2314		2306
2315	if (use_pbles) {	2307	if (use_pbles) {
2316	status = irdma_get_pble(rf->pble_rsrc, palloc, iwmr->page_cnt,	2308	status = irdma_get_pble(rf->pble_rsrc, palloc, iwmr->page_cnt,
2317	false);	2309	false);
2318	if (status)	2310	if (status)
2319	return -ENOMEM;	2311	return status;
2320		2312
2321	iwpbl->pbl_allocated = true;	2313	iwpbl->pbl_allocated = true;
2322	level = palloc->level;	2314	level = palloc->level;
@@ -2434,7 +2426,7 @@ static int irdma_hw_alloc_mw(struct irdma_device iwdev, struct irdma_mr iwmr) · 111 unmodified lines
2434	struct irdma_pd *iwpd = to_iwpd(iwmr->ibmr.pd);	2426	struct irdma_pd *iwpd = to_iwpd(iwmr->ibmr.pd);
2435	struct irdma_cqp_request *cqp_request;	2427	struct irdma_cqp_request *cqp_request;
2436	struct cqp_cmds_info *cqp_info;	2428	struct cqp_cmds_info *cqp_info;
2437	enum irdma_status_code status;	2429	int status;
2438		2430
2439	cqp_request = irdma_alloc_and_get_cqp_request(&iwdev->rf->cqp, true);	2431	cqp_request = irdma_alloc_and_get_cqp_request(&iwdev->rf->cqp, true);
2440	if (!cqp_request)	2432	if (!cqp_request)
@@ -2457,7 +2449,7 @@ static int irdma_hw_alloc_mw(struct irdma_device iwdev, struct irdma_mr iwmr) · 16 unmodified lines
2457	status = irdma_handle_cqp_op(iwdev->rf, cqp_request);	2449	status = irdma_handle_cqp_op(iwdev->rf, cqp_request);
2458	irdma_put_cqp_request(&iwdev->rf->cqp, cqp_request);	2450	irdma_put_cqp_request(&iwdev->rf->cqp, cqp_request);
2459		2451
2460	return status ? -ENOMEM : 0;	2452	return status;
2461	}	2453	}
2462		2454
2463	/**	2455	/**
@@ -2509,7 +2501,7 @@ static int irdma_dealloc_mw(struct ib_mw *ibmw) · 45 unmodified lines
2509	cqp_info = &cqp_request->info;	2501	cqp_info = &cqp_request->info;
2510	info = &cqp_info->in.u.dealloc_stag.info;	2502	info = &cqp_info->in.u.dealloc_stag.info;
2511	memset(info, 0, sizeof(*info));	2503	memset(info, 0, sizeof(*info));
2512	info->pd_id = iwpd->sc_pd.pd_id & 0x00007fff;	2504	info->pd_id = iwpd->sc_pd.pd_id;
2513	info->stag_idx = ibmw->rkey >> IRDMA_CQPSQ_STAG_IDX_S;	2505	info->stag_idx = ibmw->rkey >> IRDMA_CQPSQ_STAG_IDX_S;
2514	info->mr = false;	2506	info->mr = false;
2515	cqp_info->cqp_cmd = IRDMA_OP_DEALLOC_STAG;	2507	cqp_info->cqp_cmd = IRDMA_OP_DEALLOC_STAG;
@@ -2533,8 +2525,7 @@ static int irdma_hw_alloc_stag(struct irdma_device *iwdev, · 17 unmodified lines
2533	{	2525	{
2534	struct irdma_allocate_stag_info *info;	2526	struct irdma_allocate_stag_info *info;
2535	struct irdma_pd *iwpd = to_iwpd(iwmr->ibmr.pd);	2527	struct irdma_pd *iwpd = to_iwpd(iwmr->ibmr.pd);
2536	enum irdma_status_code status;	2528	int status;
2537	int err = 0;
2538	struct irdma_cqp_request *cqp_request;	2529	struct irdma_cqp_request *cqp_request;
2539	struct cqp_cmds_info *cqp_info;	2530	struct cqp_cmds_info *cqp_info;
2540		2531
@@ -2556,10 +2547,8 @@ static int irdma_hw_alloc_stag(struct irdma_device *iwdev, · 15 unmodified lines
2556	cqp_info->in.u.alloc_stag.scratch = (uintptr_t)cqp_request;	2547	cqp_info->in.u.alloc_stag.scratch = (uintptr_t)cqp_request;
2557	status = irdma_handle_cqp_op(iwdev->rf, cqp_request);	2548	status = irdma_handle_cqp_op(iwdev->rf, cqp_request);
2558	irdma_put_cqp_request(&iwdev->rf->cqp, cqp_request);	2549	irdma_put_cqp_request(&iwdev->rf->cqp, cqp_request);
2559	if (status)
2560	err = -ENOMEM;
2561		2550
2562	return err;	2551	return status;
2563	}	2552	}
2564		2553
2565	/**	2554	/**
@@ -2575,9 +2564,8 @@ static struct ib_mr irdma_alloc_mr(struct ib_pd pd, enum ib_mr_type mr_type, · 9 unmodified lines
2575	struct irdma_pble_alloc *palloc;	2564	struct irdma_pble_alloc *palloc;
2576	struct irdma_pbl *iwpbl;	2565	struct irdma_pbl *iwpbl;
2577	struct irdma_mr *iwmr;	2566	struct irdma_mr *iwmr;
2578	enum irdma_status_code status;
2579	u32 stag;	2567	u32 stag;
2580	int err_code = -ENOMEM;	2568	int err_code;
2581		2569
2582	iwmr = kzalloc(sizeof(*iwmr), GFP_KERNEL);	2570	iwmr = kzalloc(sizeof(*iwmr), GFP_KERNEL);
2583	if (!iwmr)	2571	if (!iwmr)
@@ -2599,9 +2587,9 @@ static struct ib_mr irdma_alloc_mr(struct ib_pd pd, enum ib_mr_type mr_type, · 15 unmodified lines
2599	iwmr->type = IRDMA_MEMREG_TYPE_MEM;	2587	iwmr->type = IRDMA_MEMREG_TYPE_MEM;
2600	palloc = &iwpbl->pble_alloc;	2588	palloc = &iwpbl->pble_alloc;
2601	iwmr->page_cnt = max_num_sg;	2589	iwmr->page_cnt = max_num_sg;
2602	status = irdma_get_pble(iwdev->rf->pble_rsrc, palloc, iwmr->page_cnt,	2590	err_code = irdma_get_pble(iwdev->rf->pble_rsrc, palloc, iwmr->page_cnt,
2603	true);	2591	true);
2604	if (status)	2592	if (err_code)
2605	goto err_get_pble;	2593	goto err_get_pble;
2606		2594
2607	err_code = irdma_hw_alloc_stag(iwdev, iwmr);	2595	err_code = irdma_hw_alloc_stag(iwdev, iwmr);
@@ -2672,10 +2660,9 @@ static int irdma_hwreg_mr(struct irdma_device iwdev, struct irdma_mr iwmr, · 64 unmodified lines
2672	struct irdma_reg_ns_stag_info *stag_info;	2660	struct irdma_reg_ns_stag_info *stag_info;
2673	struct irdma_pd *iwpd = to_iwpd(iwmr->ibmr.pd);	2661	struct irdma_pd *iwpd = to_iwpd(iwmr->ibmr.pd);
2674	struct irdma_pble_alloc *palloc = &iwpbl->pble_alloc;	2662	struct irdma_pble_alloc *palloc = &iwpbl->pble_alloc;
2675	enum irdma_status_code status;
2676	int err = 0;
2677	struct irdma_cqp_request *cqp_request;	2663	struct irdma_cqp_request *cqp_request;
2678	struct cqp_cmds_info *cqp_info;	2664	struct cqp_cmds_info *cqp_info;
		2665	int ret;
2679		2666
2680	cqp_request = irdma_alloc_and_get_cqp_request(&iwdev->rf->cqp, true);	2667	cqp_request = irdma_alloc_and_get_cqp_request(&iwdev->rf->cqp, true);
2681	if (!cqp_request)	2668	if (!cqp_request)
@@ -2712,12 +2699,10 @@ static int irdma_hwreg_mr(struct irdma_device iwdev, struct irdma_mr iwmr, · 30 unmodified lines
2712	cqp_info->post_sq = 1;	2699	cqp_info->post_sq = 1;
2713	cqp_info->in.u.mr_reg_non_shared.dev = &iwdev->rf->sc_dev;	2700	cqp_info->in.u.mr_reg_non_shared.dev = &iwdev->rf->sc_dev;
2714	cqp_info->in.u.mr_reg_non_shared.scratch = (uintptr_t)cqp_request;	2701	cqp_info->in.u.mr_reg_non_shared.scratch = (uintptr_t)cqp_request;
2715	status = irdma_handle_cqp_op(iwdev->rf, cqp_request);	2702	ret = irdma_handle_cqp_op(iwdev->rf, cqp_request);
2716	irdma_put_cqp_request(&iwdev->rf->cqp, cqp_request);	2703	irdma_put_cqp_request(&iwdev->rf->cqp, cqp_request);
2717	if (status)
2718	err = -ENOMEM;
2719		2704
2720	return err;	2705	return ret;
2721	}	2706	}
2722		2707
2723	/**	2708	/**
@@ -2897,7 +2882,6 @@ struct ib_mr irdma_reg_phys_mr(struct ib_pd pd, u64 addr, u64 size, int access · 173 unmodified lines
2897	struct irdma_device *iwdev = to_iwdev(pd->device);	2882	struct irdma_device *iwdev = to_iwdev(pd->device);
2898	struct irdma_pbl *iwpbl;	2883	struct irdma_pbl *iwpbl;
2899	struct irdma_mr *iwmr;	2884	struct irdma_mr *iwmr;
2900	enum irdma_status_code status;
2901	u32 stag;	2885	u32 stag;
2902	int ret;	2886	int ret;
2903		2887
@@ -2925,10 +2909,9 @@ struct ib_mr irdma_reg_phys_mr(struct ib_pd pd, u64 addr, u64 size, int access · 21 unmodified lines
2925	iwmr->pgaddrmem[0] = addr;	2909	iwmr->pgaddrmem[0] = addr;
2926	iwmr->len = size;	2910	iwmr->len = size;
2927	iwmr->page_size = SZ_4K;	2911	iwmr->page_size = SZ_4K;
2928	status = irdma_hwreg_mr(iwdev, iwmr, access);	2912	ret = irdma_hwreg_mr(iwdev, iwmr, access);
2929	if (status) {	2913	if (ret) {
2930	irdma_free_stag(iwdev, stag);	2914	irdma_free_stag(iwdev, stag);
2931	ret = -ENOMEM;
2932	goto err;	2915	goto err;
2933	}	2916	}
2934		2917
@@ -3021,7 +3004,7 @@ static int irdma_dereg_mr(struct ib_mr ib_mr, struct ib_udata udata) · 86 unmodified lines
3021	cqp_info = &cqp_request->info;	3004	cqp_info = &cqp_request->info;
3022	info = &cqp_info->in.u.dealloc_stag.info;	3005	info = &cqp_info->in.u.dealloc_stag.info;
3023	memset(info, 0, sizeof(*info));	3006	memset(info, 0, sizeof(*info));
3024	info->pd_id = iwpd->sc_pd.pd_id & 0x00007fff;	3007	info->pd_id = iwpd->sc_pd.pd_id;
3025	info->stag_idx = ib_mr->rkey >> IRDMA_CQPSQ_STAG_IDX_S;	3008	info->stag_idx = ib_mr->rkey >> IRDMA_CQPSQ_STAG_IDX_S;
3026	info->mr = true;	3009	info->mr = true;
3027	if (iwpbl->pbl_allocated)	3010	if (iwpbl->pbl_allocated)
@@ -3057,7 +3040,6 @@ static int irdma_post_send(struct ib_qp *ibqp, · 29 unmodified lines
3057	struct irdma_qp_uk *ukqp;	3040	struct irdma_qp_uk *ukqp;
3058	struct irdma_sc_dev *dev;	3041	struct irdma_sc_dev *dev;
3059	struct irdma_post_sq_info info;	3042	struct irdma_post_sq_info info;
3060	enum irdma_status_code ret;
3061	int err = 0;	3043	int err = 0;
3062	unsigned long flags;	3044	unsigned long flags;
3063	bool inv_stag;	3045	bool inv_stag;
@@ -3116,7 +3098,7 @@ static int irdma_post_send(struct ib_qp *ibqp, · 52 unmodified lines
3116	info.op.inline_send.qkey = ud_wr(ib_wr)->remote_qkey;	3098	info.op.inline_send.qkey = ud_wr(ib_wr)->remote_qkey;
3117	info.op.inline_send.dest_qp = ud_wr(ib_wr)->remote_qpn;	3099	info.op.inline_send.dest_qp = ud_wr(ib_wr)->remote_qpn;
3118	}	3100	}
3119	ret = irdma_uk_inline_send(ukqp, &info, false);	3101	err = irdma_uk_inline_send(ukqp, &info, false);
3120	} else {	3102	} else {
3121	info.op.send.num_sges = ib_wr->num_sge;	3103	info.op.send.num_sges = ib_wr->num_sge;
3122	info.op.send.sg_list = ib_wr->sg_list;	3104	info.op.send.sg_list = ib_wr->sg_list;
@@ -3127,14 +3109,7 @@ static int irdma_post_send(struct ib_qp *ibqp, · 4 unmodified lines
3127	info.op.send.qkey = ud_wr(ib_wr)->remote_qkey;	3109	info.op.send.qkey = ud_wr(ib_wr)->remote_qkey;
3128	info.op.send.dest_qp = ud_wr(ib_wr)->remote_qpn;	3110	info.op.send.dest_qp = ud_wr(ib_wr)->remote_qpn;
3129	}	3111	}
3130	ret = irdma_uk_send(ukqp, &info, false);	3112	err = irdma_uk_send(ukqp, &info, false);
3131	}
3132
3133	if (ret) {
3134	if (ret == IRDMA_ERR_QP_TOOMANY_WRS_POSTED)
3135	err = -ENOMEM;
3136	else
3137	err = -EINVAL;
3138	}	3113	}
3139	break;	3114	break;
3140	case IB_WR_RDMA_WRITE_WITH_IMM:	3115	case IB_WR_RDMA_WRITE_WITH_IMM:
@@ -3160,20 +3135,13 @@ static int irdma_post_send(struct ib_qp *ibqp, · 19 unmodified lines
3160	rdma_wr(ib_wr)->remote_addr;	3135	rdma_wr(ib_wr)->remote_addr;
3161	info.op.inline_rdma_write.rem_addr.lkey =	3136	info.op.inline_rdma_write.rem_addr.lkey =
3162	rdma_wr(ib_wr)->rkey;	3137	rdma_wr(ib_wr)->rkey;
3163	ret = irdma_uk_inline_rdma_write(ukqp, &info, false);	3138	err = irdma_uk_inline_rdma_write(ukqp, &info, false);
3164	} else {	3139	} else {
3165	info.op.rdma_write.lo_sg_list = (void *)ib_wr->sg_list;	3140	info.op.rdma_write.lo_sg_list = (void *)ib_wr->sg_list;
3166	info.op.rdma_write.num_lo_sges = ib_wr->num_sge;	3141	info.op.rdma_write.num_lo_sges = ib_wr->num_sge;
3167	info.op.rdma_write.rem_addr.addr = rdma_wr(ib_wr)->remote_addr;	3142	info.op.rdma_write.rem_addr.addr = rdma_wr(ib_wr)->remote_addr;
3168	info.op.rdma_write.rem_addr.lkey = rdma_wr(ib_wr)->rkey;	3143	info.op.rdma_write.rem_addr.lkey = rdma_wr(ib_wr)->rkey;
3169	ret = irdma_uk_rdma_write(ukqp, &info, false);	3144	err = irdma_uk_rdma_write(ukqp, &info, false);
3170	}
3171
3172	if (ret) {
3173	if (ret == IRDMA_ERR_QP_TOOMANY_WRS_POSTED)
3174	err = -ENOMEM;
3175	else
3176	err = -EINVAL;
3177	}	3145	}
3178	break;	3146	break;
3179	case IB_WR_RDMA_READ_WITH_INV:	3147	case IB_WR_RDMA_READ_WITH_INV:
@@ -3190,21 +3158,12 @@ static int irdma_post_send(struct ib_qp *ibqp, · 10 unmodified lines
3190	info.op.rdma_read.rem_addr.lkey = rdma_wr(ib_wr)->rkey;	3158	info.op.rdma_read.rem_addr.lkey = rdma_wr(ib_wr)->rkey;
3191	info.op.rdma_read.lo_sg_list = (void *)ib_wr->sg_list;	3159	info.op.rdma_read.lo_sg_list = (void *)ib_wr->sg_list;
3192	info.op.rdma_read.num_lo_sges = ib_wr->num_sge;	3160	info.op.rdma_read.num_lo_sges = ib_wr->num_sge;
3193		3161	err = irdma_uk_rdma_read(ukqp, &info, inv_stag, false);
3194	ret = irdma_uk_rdma_read(ukqp, &info, inv_stag, false);
3195	if (ret) {
3196	if (ret == IRDMA_ERR_QP_TOOMANY_WRS_POSTED)
3197	err = -ENOMEM;
3198	else
3199	err = -EINVAL;
3200	}
3201	break;	3162	break;
3202	case IB_WR_LOCAL_INV:	3163	case IB_WR_LOCAL_INV:
3203	info.op_type = IRDMA_OP_TYPE_INV_STAG;	3164	info.op_type = IRDMA_OP_TYPE_INV_STAG;
3204	info.op.inv_local_stag.target_stag = ib_wr->ex.invalidate_rkey;	3165	info.op.inv_local_stag.target_stag = ib_wr->ex.invalidate_rkey;
3205	ret = irdma_uk_stag_local_invalidate(ukqp, &info, true);	3166	err = irdma_uk_stag_local_invalidate(ukqp, &info, true);
3206	if (ret)
3207	err = -ENOMEM;
3208	break;	3167	break;
3209	case IB_WR_REG_MR: {	3168	case IB_WR_REG_MR: {
3210	struct irdma_mr *iwmr = to_iwmr(reg_wr(ib_wr)->mr);	3169	struct irdma_mr *iwmr = to_iwmr(reg_wr(ib_wr)->mr);
@@ -3226,10 +3185,8 @@ static int irdma_post_send(struct ib_qp *ibqp, · 15 unmodified lines
3226	stag_info.local_fence = ib_wr->send_flags & IB_SEND_FENCE;	3185	stag_info.local_fence = ib_wr->send_flags & IB_SEND_FENCE;
3227	if (iwmr->npages > IRDMA_MIN_PAGES_PER_FMR)	3186	if (iwmr->npages > IRDMA_MIN_PAGES_PER_FMR)
3228	stag_info.chunk_size = 1;	3187	stag_info.chunk_size = 1;
3229	ret = irdma_sc_mr_fast_register(&iwqp->sc_qp, &stag_info,	3188	err = irdma_sc_mr_fast_register(&iwqp->sc_qp, &stag_info,
3230	true);	3189	true);
3231	if (ret)
3232	err = -ENOMEM;
3233	break;	3190	break;
3234	}	3191	}
3235	default:	3192	default:
@@ -3274,7 +3231,6 @@ static int irdma_post_recv(struct ib_qp *ibqp, · 38 unmodified lines
3274	struct irdma_qp *iwqp;	3231	struct irdma_qp *iwqp;
3275	struct irdma_qp_uk *ukqp;	3232	struct irdma_qp_uk *ukqp;
3276	struct irdma_post_rq_info post_recv = {};	3233	struct irdma_post_rq_info post_recv = {};
3277	enum irdma_status_code ret = 0;
3278	unsigned long flags;	3234	unsigned long flags;
3279	int err = 0;	3235	int err = 0;
3280	bool reflush = false;	3236	bool reflush = false;
@@ -3289,14 +3245,10 @@ static int irdma_post_recv(struct ib_qp *ibqp, · 8 unmodified lines
3289	post_recv.num_sges = ib_wr->num_sge;	3245	post_recv.num_sges = ib_wr->num_sge;
3290	post_recv.wr_id = ib_wr->wr_id;	3246	post_recv.wr_id = ib_wr->wr_id;
3291	post_recv.sg_list = ib_wr->sg_list;	3247	post_recv.sg_list = ib_wr->sg_list;
3292	ret = irdma_uk_post_receive(ukqp, &post_recv);	3248	err = irdma_uk_post_receive(ukqp, &post_recv);
3293	if (ret) {	3249	if (err) {
3294	ibdev_dbg(&iwqp->iwdev->ibdev,	3250	ibdev_dbg(&iwqp->iwdev->ibdev,
3295	"VERBS: post_recv err %d\n", ret);	3251	"VERBS: post_recv err %d\n", err);
3296	if (ret == IRDMA_ERR_QP_TOOMANY_WRS_POSTED)
3297	err = -ENOMEM;
3298	else
3299	err = -EINVAL;
3300	goto out;	3252	goto out;
3301	}	3253	}
3302		3254
@@ -3483,7 +3435,7 @@ static int __irdma_poll_cq(struct irdma_cq *iwcq, int num_entries, struct ib_wc · 180 unmodified lines
3483	struct irdma_cq_buf *last_buf = NULL;	3435	struct irdma_cq_buf *last_buf = NULL;
3484	struct irdma_cq_poll_info *cur_cqe = &iwcq->cur_cqe;	3436	struct irdma_cq_poll_info *cur_cqe = &iwcq->cur_cqe;
3485	struct irdma_cq_buf *cq_buf;	3437	struct irdma_cq_buf *cq_buf;
3486	enum irdma_status_code ret;	3438	int ret;
3487	struct irdma_device *iwdev;	3439	struct irdma_device *iwdev;
3488	struct irdma_cq_uk *ukcq;	3440	struct irdma_cq_uk *ukcq;
3489	bool cq_new_cqe = false;	3441	bool cq_new_cqe = false;
@@ -3503,10 +3455,10 @@ static int __irdma_poll_cq(struct irdma_cq *iwcq, int num_entries, struct ib_wc · 13 unmodified lines
3503	cq_new_cqe = true;	3455	cq_new_cqe = true;
3504	continue;	3456	continue;
3505	}	3457	}
3506	if (ret == IRDMA_ERR_Q_EMPTY)	3458	if (ret == -ENOENT)
3507	break;	3459	break;
3508	/* QP using the CQ is destroyed. Skip reporting this CQE */	3460	/* QP using the CQ is destroyed. Skip reporting this CQE */
3509	if (ret == IRDMA_ERR_Q_DESTROYED) {	3461	if (ret == -EFAULT) {
3510	cq_new_cqe = true;	3462	cq_new_cqe = true;
3511	continue;	3463	continue;
3512	}	3464	}
@@ -3528,10 +3480,10 @@ static int __irdma_poll_cq(struct irdma_cq *iwcq, int num_entries, struct ib_wc · 15 unmodified lines
3528	continue;	3480	continue;
3529	}	3481	}
3530		3482
3531	if (ret == IRDMA_ERR_Q_EMPTY)	3483	if (ret == -ENOENT)
3532	break;	3484	break;
3533	/* QP using the CQ is destroyed. Skip reporting this CQE */	3485	/* QP using the CQ is destroyed. Skip reporting this CQE */
3534	if (ret == IRDMA_ERR_Q_DESTROYED) {	3486	if (ret == -EFAULT) {
3535	cq_new_cqe = true;	3487	cq_new_cqe = true;
3536	continue;	3488	continue;
3537	}	3489	}
@@ -3553,7 +3505,7 @@ error: · 15 unmodified lines
3553	ibdev_dbg(&iwdev->ibdev, "%s: Error polling CQ, irdma_err: %d\n",	3505	ibdev_dbg(&iwdev->ibdev, "%s: Error polling CQ, irdma_err: %d\n",
3554	__func__, ret);	3506	__func__, ret);
3555		3507
3556	return -EINVAL;	3508	return ret;
3557	}	3509	}
3558		3510
3559	/**	3511	/**
@@ -3859,7 +3811,7 @@ static int irdma_mcast_cqp_op(struct irdma_device *iwdev, · 299 unmodified lines
3859	{	3811	{
3860	struct cqp_cmds_info *cqp_info;	3812	struct cqp_cmds_info *cqp_info;
3861	struct irdma_cqp_request *cqp_request;	3813	struct irdma_cqp_request *cqp_request;
3862	enum irdma_status_code status;	3814	int status;
3863		3815
3864	cqp_request = irdma_alloc_and_get_cqp_request(&iwdev->rf->cqp, true);	3816	cqp_request = irdma_alloc_and_get_cqp_request(&iwdev->rf->cqp, true);
3865	if (!cqp_request)	3817	if (!cqp_request)
@@ -3873,10 +3825,8 @@ static int irdma_mcast_cqp_op(struct irdma_device *iwdev, · 7 unmodified lines
3873	cqp_info->in.u.mc_create.cqp = &iwdev->rf->cqp.sc_cqp;	3825	cqp_info->in.u.mc_create.cqp = &iwdev->rf->cqp.sc_cqp;
3874	status = irdma_handle_cqp_op(iwdev->rf, cqp_request);	3826	status = irdma_handle_cqp_op(iwdev->rf, cqp_request);
3875	irdma_put_cqp_request(&iwdev->rf->cqp, cqp_request);	3827	irdma_put_cqp_request(&iwdev->rf->cqp, cqp_request);
3876	if (status)
3877	return -ENOMEM;
3878		3828
3879	return 0;	3829	return status;
3880	}	3830	}
3881		3831
3882	/**	3832	/**
@@ -3932,11 +3882,7 @@ static int irdma_attach_mcast(struct ib_qp ibqp, union ib_gid ibgid, u16 lid) · 49 unmodified lines
3932	int ret = 0;	3882	int ret = 0;
3933	bool ipv4;	3883	bool ipv4;
3934	u16 vlan_id;	3884	u16 vlan_id;
3935	union {	3885	union irdma_sockaddr sgid_addr;
3936	struct sockaddr saddr;
3937	struct sockaddr_in saddr_in;
3938	struct sockaddr_in6 saddr_in6;
3939	} sgid_addr;
3940	unsigned char dmac[ETH_ALEN];	3886	unsigned char dmac[ETH_ALEN];
3941		3887
3942	rdma_gid2ip((struct sockaddr *)&sgid_addr, ibgid);	3888	rdma_gid2ip((struct sockaddr *)&sgid_addr, ibgid);
@@ -4072,11 +4018,7 @@ static int irdma_detach_mcast(struct ib_qp ibqp, union ib_gid ibgid, u16 lid) · 129 unmodified lines
4072	struct irdma_mcast_grp_ctx_entry_info mcg_info = {};	4018	struct irdma_mcast_grp_ctx_entry_info mcg_info = {};
4073	int ret;	4019	int ret;
4074	unsigned long flags;	4020	unsigned long flags;
4075	union {	4021	union irdma_sockaddr sgid_addr;
4076	struct sockaddr saddr;
4077	struct sockaddr_in saddr_in;
4078	struct sockaddr_in6 saddr_in6;
4079	} sgid_addr;
4080		4022
4081	rdma_gid2ip((struct sockaddr *)&sgid_addr, ibgid);	4023	rdma_gid2ip((struct sockaddr *)&sgid_addr, ibgid);
4082	if (!ipv6_addr_v4mapped((struct in6_addr *)ibgid))	4024	if (!ipv6_addr_v4mapped((struct in6_addr *)ibgid))
@@ -4132,17 +4074,47 @@ static int irdma_detach_mcast(struct ib_qp ibqp, union ib_gid ibgid, u16 lid) · 49 unmodified lines
4132	return 0;	4074	return 0;
4133	}	4075	}
4134		4076
4135	/**	4077	static int irdma_create_hw_ah(struct irdma_device iwdev, struct irdma_ah ah, bool sleep)
4136	* irdma_create_ah - create address handle	4078	{
4137	* @ibah: address handle	4079	struct irdma_pci_f *rf = iwdev->rf;
4138	* @attr: address handle attributes	4080	int err;
4139	* @udata: User data	4081
4140	*	4082	err = irdma_alloc_rsrc(rf, rf->allocated_ahs, rf->max_ah, &ah->sc_ah.ah_info.ah_idx,
4141	* returns 0 on success, error otherwise	4083	&rf->next_ah);
4142	*/	4084	if (err)
4143	static int irdma_create_ah(struct ib_ah *ibah,	4085	return err;
4144	struct rdma_ah_init_attr *attr,	4086
4145	struct ib_udata *udata)	4087	err = irdma_ah_cqp_op(rf, &ah->sc_ah, IRDMA_OP_AH_CREATE, sleep,
		4088	irdma_gsi_ud_qp_ah_cb, &ah->sc_ah);
		4089
		4090	if (err) {
		4091	ibdev_dbg(&iwdev->ibdev, "VERBS: CQP-OP Create AH fail");
		4092	goto err_ah_create;
		4093	}
		4094
		4095	if (!sleep) {
		4096	int cnt = CQP_COMPL_WAIT_TIME_MS * CQP_TIMEOUT_THRESHOLD;
		4097
		4098	do {
		4099	irdma_cqp_ce_handler(rf, &rf->ccq.sc_cq);
		4100	mdelay(1);
		4101	} while (!ah->sc_ah.ah_info.ah_valid && --cnt);
		4102
		4103	if (!cnt) {
		4104	ibdev_dbg(&iwdev->ibdev, "VERBS: CQP create AH timed out");
		4105	err = -ETIMEDOUT;
		4106	goto err_ah_create;
		4107	}
		4108	}
		4109	return 0;
		4110
		4111	err_ah_create:
		4112	irdma_free_rsrc(iwdev->rf, iwdev->rf->allocated_ahs, ah->sc_ah.ah_info.ah_idx);
		4113
		4114	return err;
		4115	}
		4116
		4117	static int irdma_setup_ah(struct ib_ah ibah, struct rdma_ah_init_attr attr)
4146	{	4118	{
4147	struct irdma_pd *pd = to_iwpd(ibah->pd);	4119	struct irdma_pd *pd = to_iwpd(ibah->pd);
4148	struct irdma_ah *ah = container_of(ibah, struct irdma_ah, ibah);	4120	struct irdma_ah *ah = container_of(ibah, struct irdma_ah, ibah);
@@ -4151,25 +4123,13 @@ static int irdma_create_ah(struct ib_ah *ibah, · 2 unmodified lines
4151	struct irdma_device *iwdev = to_iwdev(ibah->pd->device);	4123	struct irdma_device *iwdev = to_iwdev(ibah->pd->device);
4152	struct irdma_pci_f *rf = iwdev->rf;	4124	struct irdma_pci_f *rf = iwdev->rf;
4153	struct irdma_sc_ah *sc_ah;	4125	struct irdma_sc_ah *sc_ah;
4154	u32 ah_id = 0;
4155	struct irdma_ah_info *ah_info;	4126	struct irdma_ah_info *ah_info;
4156	struct irdma_create_ah_resp uresp;	4127	union irdma_sockaddr sgid_addr, dgid_addr;
4157	union {
4158	struct sockaddr saddr;
4159	struct sockaddr_in saddr_in;
4160	struct sockaddr_in6 saddr_in6;
4161	} sgid_addr, dgid_addr;
4162	int err;	4128	int err;
4163	u8 dmac[ETH_ALEN];	4129	u8 dmac[ETH_ALEN];
4164		4130
4165	err = irdma_alloc_rsrc(rf, rf->allocated_ahs, rf->max_ah, &ah_id,
4166	&rf->next_ah);
4167	if (err)
4168	return err;
4169
4170	ah->pd = pd;	4131	ah->pd = pd;
4171	sc_ah = &ah->sc_ah;	4132	sc_ah = &ah->sc_ah;
4172	sc_ah->ah_info.ah_idx = ah_id;
4173	sc_ah->ah_info.vsi = &iwdev->vsi;	4133	sc_ah->ah_info.vsi = &iwdev->vsi;
4174	irdma_sc_init_ah(&rf->sc_dev, sc_ah);	4134	irdma_sc_init_ah(&rf->sc_dev, sc_ah);
4175	ah->sgid_index = ah_attr->grh.sgid_index;	4135	ah->sgid_index = ah_attr->grh.sgid_index;
@@ -4179,10 +4139,7 @@ static int irdma_create_ah(struct ib_ah *ibah, · 3 unmodified lines
4179	rdma_gid2ip((struct sockaddr *)&dgid_addr, &ah_attr->grh.dgid);	4139	rdma_gid2ip((struct sockaddr *)&dgid_addr, &ah_attr->grh.dgid);
4180	ah->av.attrs = *ah_attr;	4140	ah->av.attrs = *ah_attr;
4181	ah->av.net_type = rdma_gid_attr_network_type(sgid_attr);	4141	ah->av.net_type = rdma_gid_attr_network_type(sgid_attr);
4182	ah->av.sgid_addr.saddr = sgid_addr.saddr;
4183	ah->av.dgid_addr.saddr = dgid_addr.saddr;
4184	ah_info = &sc_ah->ah_info;	4142	ah_info = &sc_ah->ah_info;
4185	ah_info->ah_idx = ah_id;
4186	ah_info->pd_idx = pd->sc_pd.pd_id;	4143	ah_info->pd_idx = pd->sc_pd.pd_id;
4187	if (ah_attr->ah_flags & IB_AH_GRH) {	4144	if (ah_attr->ah_flags & IB_AH_GRH) {
4188	ah_info->flow_label = ah_attr->grh.flow_label;	4145	ah_info->flow_label = ah_attr->grh.flow_label;
@@ -4191,7 +4148,7 @@ static int irdma_create_ah(struct ib_ah *ibah, · 2 unmodified lines
4191	}	4148	}
4192		4149
4193	ether_addr_copy(dmac, ah_attr->roce.dmac);	4150	ether_addr_copy(dmac, ah_attr->roce.dmac);
4194	if (rdma_gid_attr_network_type(sgid_attr) == RDMA_NETWORK_IPV4) {	4151	if (ah->av.net_type == RDMA_NETWORK_IPV4) {
4195	ah_info->ipv4_valid = true;	4152	ah_info->ipv4_valid = true;
4196	ah_info->dest_ip_addr[0] =	4153	ah_info->dest_ip_addr[0] =
4197	ntohl(dgid_addr.saddr_in.sin_addr.s_addr);	4154	ntohl(dgid_addr.saddr_in.sin_addr.s_addr);
@@ -4219,17 +4176,15 @@ static int irdma_create_ah(struct ib_ah *ibah, · 21 unmodified lines
4219	err = rdma_read_gid_l2_fields(sgid_attr, &ah_info->vlan_tag,	4176	err = rdma_read_gid_l2_fields(sgid_attr, &ah_info->vlan_tag,
4220	ah_info->mac_addr);	4177	ah_info->mac_addr);
4221	if (err)	4178	if (err)
4222	goto error;	4179	return err;
4223		4180
4224	ah_info->dst_arpindex = irdma_add_arp(iwdev->rf, ah_info->dest_ip_addr,	4181	ah_info->dst_arpindex = irdma_add_arp(iwdev->rf, ah_info->dest_ip_addr,
4225	ah_info->ipv4_valid, dmac);	4182	ah_info->ipv4_valid, dmac);
4226		4183
4227	if (ah_info->dst_arpindex == -1) {	4184	if (ah_info->dst_arpindex == -1)
4228	err = -EINVAL;	4185	return -EINVAL;
4229	goto error;
4230	}
4231		4186
4232	if (ah_info->vlan_tag >= VLAN_N_VID && iwdev->dcb)	4187	if (ah_info->vlan_tag >= VLAN_N_VID && iwdev->dcb_vlan_mode)
4233	ah_info->vlan_tag = 0;	4188	ah_info->vlan_tag = 0;
4234		4189
4235	if (ah_info->vlan_tag < VLAN_N_VID) {	4190	if (ah_info->vlan_tag < VLAN_N_VID) {
@@ -4238,43 +4193,38 @@ static int irdma_create_ah(struct ib_ah *ibah, · 2 unmodified lines
4238	rt_tos2priority(ah_info->tc_tos) << VLAN_PRIO_SHIFT;	4193	rt_tos2priority(ah_info->tc_tos) << VLAN_PRIO_SHIFT;
4239	}	4194	}
4240		4195
4241	err = irdma_ah_cqp_op(iwdev->rf, sc_ah, IRDMA_OP_AH_CREATE,	4196	return 0;
4242	attr->flags & RDMA_CREATE_AH_SLEEPABLE,	4197	}
4243	irdma_gsi_ud_qp_ah_cb, sc_ah);
4244
4245	if (err) {
4246	ibdev_dbg(&iwdev->ibdev,
4247	"VERBS: CQP-OP Create AH fail");
4248	goto error;
4249	}
4250
4251	if (!(attr->flags & RDMA_CREATE_AH_SLEEPABLE)) {
4252	int cnt = CQP_COMPL_WAIT_TIME_MS * CQP_TIMEOUT_THRESHOLD;
4253
4254	do {
4255	irdma_cqp_ce_handler(rf, &rf->ccq.sc_cq);
4256	mdelay(1);
4257	} while (!sc_ah->ah_info.ah_valid && --cnt);
4258		4198
4259	if (!cnt) {	4199	/**
4260	ibdev_dbg(&iwdev->ibdev,	4200	* irdma_ah_exists - Check for existing identical AH
4261	"VERBS: CQP create AH timed out");	4201	* @iwdev: irdma device
4262	err = -ETIMEDOUT;	4202	* @new_ah: AH to check for
4263	goto error;	4203	*
		4204	* returns true if AH is found, false if not found.
		4205	*/
		4206	static bool irdma_ah_exists(struct irdma_device *iwdev,
		4207	struct irdma_ah *new_ah)
		4208	{
		4209	struct irdma_ah *ah;
		4210	u32 key = new_ah->sc_ah.ah_info.dest_ip_addr[0] ^
		4211	new_ah->sc_ah.ah_info.dest_ip_addr[1] ^
		4212	new_ah->sc_ah.ah_info.dest_ip_addr[2] ^
		4213	new_ah->sc_ah.ah_info.dest_ip_addr[3];
		4214
		4215	hash_for_each_possible(iwdev->ah_hash_tbl, ah, list, key) {
		4216	/* Set ah_valid and ah_id the same so memcmp can work */
		4217	new_ah->sc_ah.ah_info.ah_idx = ah->sc_ah.ah_info.ah_idx;
		4218	new_ah->sc_ah.ah_info.ah_valid = ah->sc_ah.ah_info.ah_valid;
		4219	if (!memcmp(&ah->sc_ah.ah_info, &new_ah->sc_ah.ah_info,
		4220	sizeof(ah->sc_ah.ah_info))) {
		4221	refcount_inc(&ah->refcnt);
		4222	new_ah->parent_ah = ah;
		4223	return true;
4264	}	4224	}
4265	}	4225	}
4266		4226
4267	if (udata) {	4227	return false;
4268	uresp.ah_id = ah->sc_ah.ah_info.ah_idx;
4269	err = ib_copy_to_udata(udata, &uresp,
4270	min(sizeof(uresp), udata->outlen));
4271	}
4272	return 0;
4273
4274	error:
4275	irdma_free_rsrc(iwdev->rf, iwdev->rf->allocated_ahs, ah_id);
4276
4277	return err;
4278	}	4228	}
4279		4229
4280	/**	4230	/**
@@ -4287,6 +4237,17 @@ static int irdma_destroy_ah(struct ib_ah *ibah, u32 ah_flags) · 6 unmodified lines
4287	struct irdma_device *iwdev = to_iwdev(ibah->device);	4237	struct irdma_device *iwdev = to_iwdev(ibah->device);
4288	struct irdma_ah *ah = to_iwah(ibah);	4238	struct irdma_ah *ah = to_iwah(ibah);
4289		4239
		4240	if ((ah_flags & RDMA_DESTROY_AH_SLEEPABLE) && ah->parent_ah) {
		4241	mutex_lock(&iwdev->ah_tbl_lock);
		4242	if (!refcount_dec_and_test(&ah->parent_ah->refcnt)) {
		4243	mutex_unlock(&iwdev->ah_tbl_lock);
		4244	return 0;
		4245	}
		4246	hash_del(&ah->parent_ah->list);
		4247	kfree(ah->parent_ah);
		4248	mutex_unlock(&iwdev->ah_tbl_lock);
		4249	}
		4250
4290	irdma_ah_cqp_op(iwdev->rf, &ah->sc_ah, IRDMA_OP_AH_DESTROY,	4251	irdma_ah_cqp_op(iwdev->rf, &ah->sc_ah, IRDMA_OP_AH_DESTROY,
4291	false, NULL, ah);	4252	false, NULL, ah);
4292		4253
@@ -4296,6 +4257,80 @@ static int irdma_destroy_ah(struct ib_ah *ibah, u32 ah_flags) · 3 unmodified lines
4296	return 0;	4257	return 0;
4297	}	4258	}
4298		4259
		4260	/**
		4261	* irdma_create_user_ah - create user address handle
		4262	* @ibah: address handle
		4263	* @attr: address handle attributes
		4264	* @udata: User data
		4265	*
		4266	* returns 0 on success, error otherwise
		4267	*/
		4268	static int irdma_create_user_ah(struct ib_ah *ibah,
		4269	struct rdma_ah_init_attr *attr,
		4270	struct ib_udata *udata)
		4271	{
		4272	struct irdma_ah *ah = container_of(ibah, struct irdma_ah, ibah);
		4273	struct irdma_device *iwdev = to_iwdev(ibah->pd->device);
		4274	struct irdma_create_ah_resp uresp;
		4275	struct irdma_ah *parent_ah;
		4276	int err;
		4277
		4278	err = irdma_setup_ah(ibah, attr);
		4279	if (err)
		4280	return err;
		4281	mutex_lock(&iwdev->ah_tbl_lock);
		4282	if (!irdma_ah_exists(iwdev, ah)) {
		4283	err = irdma_create_hw_ah(iwdev, ah, true);
		4284	if (err) {
		4285	mutex_unlock(&iwdev->ah_tbl_lock);
		4286	return err;
		4287	}
		4288	/* Add new AH to list */
		4289	parent_ah = kmemdup(ah, sizeof(*ah), GFP_KERNEL);
		4290	if (parent_ah) {
		4291	u32 key = parent_ah->sc_ah.ah_info.dest_ip_addr[0] ^
		4292	parent_ah->sc_ah.ah_info.dest_ip_addr[1] ^
		4293	parent_ah->sc_ah.ah_info.dest_ip_addr[2] ^
		4294	parent_ah->sc_ah.ah_info.dest_ip_addr[3];
		4295
		4296	ah->parent_ah = parent_ah;
		4297	hash_add(iwdev->ah_hash_tbl, &parent_ah->list, key);
		4298	refcount_set(&parent_ah->refcnt, 1);
		4299	}
		4300	}
		4301	mutex_unlock(&iwdev->ah_tbl_lock);
		4302
		4303	uresp.ah_id = ah->sc_ah.ah_info.ah_idx;
		4304	err = ib_copy_to_udata(udata, &uresp, min(sizeof(uresp), udata->outlen));
		4305	if (err)
		4306	irdma_destroy_ah(ibah, attr->flags);
		4307
		4308	return err;
		4309	}
		4310
		4311	/**
		4312	* irdma_create_ah - create address handle
		4313	* @ibah: address handle
		4314	* @attr: address handle attributes
		4315	* @udata: NULL
		4316	*
		4317	* returns 0 on success, error otherwise
		4318	*/
		4319	static int irdma_create_ah(struct ib_ah ibah, struct rdma_ah_init_attr attr,
		4320	struct ib_udata *udata)
		4321	{
		4322	struct irdma_ah *ah = container_of(ibah, struct irdma_ah, ibah);
		4323	struct irdma_device *iwdev = to_iwdev(ibah->pd->device);
		4324	int err;
		4325
		4326	err = irdma_setup_ah(ibah, attr);
		4327	if (err)
		4328	return err;
		4329	err = irdma_create_hw_ah(iwdev, ah, attr->flags & RDMA_CREATE_AH_SLEEPABLE);
		4330
		4331	return err;
		4332	}
		4333
4299	/**	4334	/**
4300	* irdma_query_ah - Query address handle	4335	* irdma_query_ah - Query address handle
4301	* @ibah: pointer to address handle	4336	* @ibah: pointer to address handle
@@ -4329,7 +4364,7 @@ static enum rdma_link_layer irdma_get_link_layer(struct ib_device *ibdev, · 27 unmodified lines
4329	static const struct ib_device_ops irdma_roce_dev_ops = {	4364	static const struct ib_device_ops irdma_roce_dev_ops = {
4330	.attach_mcast = irdma_attach_mcast,	4365	.attach_mcast = irdma_attach_mcast,
4331	.create_ah = irdma_create_ah,	4366	.create_ah = irdma_create_ah,
4332	.create_user_ah = irdma_create_ah,	4367	.create_user_ah = irdma_create_user_ah,
4333	.destroy_ah = irdma_destroy_ah,	4368	.destroy_ah = irdma_destroy_ah,
4334	.detach_mcast = irdma_detach_mcast,	4369	.detach_mcast = irdma_detach_mcast,
4335	.get_link_layer = irdma_get_link_layer,	4370	.get_link_layer = irdma_get_link_layer,

drivers/infiniband/hw/irdma/verbs.h+10−5

 	struct irdma_sc_pd sc_pd;
 };
+union irdma_sockaddr {
+	struct sockaddr_in saddr_in;
+	struct sockaddr_in6 saddr_in6;
+};
 struct irdma_av {
 	u8 macaddr[16];
 	struct rdma_ah_attr attrs;
-	union {
+	union irdma_sockaddr sgid_addr;
-		struct sockaddr saddr;
+	union irdma_sockaddr dgid_addr;
-		struct sockaddr_in saddr_in;
-		struct sockaddr_in6 saddr_in6;
-	} sgid_addr, dgid_addr;
 	u8 net_type;
 };
 	struct irdma_av av;
 	u8 sgid_index;
 	union ib_gid dgid;
+	struct hlist_node list;
+	refcount_t refcnt;
+	struct irdma_ah *parent_ah; /* AH from cached list */
 };
 struct irdma_hmc_pble {

drivers/infiniband/hw/irdma/ws.c+9−10

 // SPDX-License-Identifier: GPL-2.0 or Linux-OpenIB
 /* Copyright (c) 2017 - 2021 Intel Corporation */
 #include "osdep.h"
-#include "status.h"
 #include "hmc.h"
 #include "defs.h"
 #include "type.h"
  * @node: pointer to node
  * @cmd: add, remove or modify
  */
-static enum irdma_status_code
+static int irdma_ws_cqp_cmd(struct irdma_sc_vsi *vsi,
-irdma_ws_cqp_cmd(struct irdma_sc_vsi *vsi, struct irdma_ws_node *node, u8 cmd)
+			    struct irdma_ws_node *node, u8 cmd)
 {
 	struct irdma_ws_node_info node_info = {};
 	node_info.enable = node->enable;
 	if (irdma_cqp_ws_node_cmd(vsi->dev, cmd, &node_info)) {
 		ibdev_dbg(to_ibdev(vsi->dev), "WS: CQP WS CMD failed\n");
-		return IRDMA_ERR_NO_MEMORY;
+		return -ENOMEM;
 	}
 	if (node->type_leaf && cmd == IRDMA_OP_WS_ADD_NODE) {
  * @vsi: vsi pointer
  * @user_pri: user priority
  */
-enum irdma_status_code irdma_ws_add(struct irdma_sc_vsi *vsi, u8 user_pri)
+int irdma_ws_add(struct irdma_sc_vsi *vsi, u8 user_pri)
 {
 	struct irdma_ws_node *ws_tree_root;
 	struct irdma_ws_node *vsi_node;
 	struct irdma_ws_node *tc_node;
 	u16 traffic_class;
-	enum irdma_status_code ret = 0;
+	int ret = 0;
 	int i;
 	mutex_lock(&vsi->dev->ws_mutex);
 	if (vsi->tc_change_pending) {
-		ret = IRDMA_ERR_NOT_READY;
+		ret = -EBUSY;
 		goto exit;
 	}
 		ws_tree_root = irdma_alloc_node(vsi, user_pri,
 						WS_NODE_TYPE_PARENT, NULL);
 		if (!ws_tree_root) {
-			ret = IRDMA_ERR_NO_MEMORY;
+			ret = -ENOMEM;
 			goto exit;
 		}
 		vsi_node = irdma_alloc_node(vsi, user_pri, WS_NODE_TYPE_PARENT,
 					    ws_tree_root);
 		if (!vsi_node) {
-			ret = IRDMA_ERR_NO_MEMORY;
+			ret = -ENOMEM;
 			goto vsi_add_err;
 		}
 		tc_node = irdma_alloc_node(vsi, user_pri, WS_NODE_TYPE_LEAF,
 					   vsi_node);
 		if (!tc_node) {
-			ret = IRDMA_ERR_NO_MEMORY;
+			ret = -ENOMEM;
 			goto leaf_add_err;
 		}

drivers/infiniband/hw/irdma/ws.h+1−1

@@ -34,7 +34,7 @@ struct irdma_ws_node { · 33 unmodified lines
34	};	34	};
35		35
36	struct irdma_sc_vsi;	36	struct irdma_sc_vsi;
37	enum irdma_status_code irdma_ws_add(struct irdma_sc_vsi *vsi, u8 user_pri);	37	int irdma_ws_add(struct irdma_sc_vsi *vsi, u8 user_pri);
38	void irdma_ws_remove(struct irdma_sc_vsi *vsi, u8 user_pri);	38	void irdma_ws_remove(struct irdma_sc_vsi *vsi, u8 user_pri);
39	void irdma_ws_reset(struct irdma_sc_vsi *vsi);	39	void irdma_ws_reset(struct irdma_sc_vsi *vsi);
40		40

drivers/infiniband/hw/mlx4/alias_GUID.c+0−1

@@ -38,7 +38,6 @@ · 37 unmodified lines
38	#include <rdma/ib_sa.h>	38	#include <rdma/ib_sa.h>
39	#include <rdma/ib_pack.h>	39	#include <rdma/ib_pack.h>
40	#include <linux/mlx4/cmd.h>	40	#include <linux/mlx4/cmd.h>
41	#include <linux/module.h>
42	#include <linux/init.h>	41	#include <linux/init.h>
43	#include <linux/errno.h>	42	#include <linux/errno.h>
44	#include <rdma/ib_user_verbs.h>	43	#include <rdma/ib_user_verbs.h>

drivers/infiniband/hw/mlx4/srq.c+0−1

@@ -320,7 +320,6 @@ int mlx4_ib_post_srq_recv(struct ib_srq ibsrq, const struct ib_recv_wr wr, · 319 unmodified lines
320	if (mdev->dev->persist->state & MLX4_DEVICE_STATE_INTERNAL_ERROR) {	320	if (mdev->dev->persist->state & MLX4_DEVICE_STATE_INTERNAL_ERROR) {
321	err = -EIO;	321	err = -EIO;
322	*bad_wr = wr;	322	*bad_wr = wr;
323	nreq = 0;
324	goto out;	323	goto out;
325	}	324	}
326		325

drivers/infiniband/hw/mlx5/devx.c+3−1

 				key_level2,
 				obj_event,
 				GFP_KERNEL);
-		if (err)
+		if (err) {
+			kfree(obj_event);
 			return err;
+		}
 		INIT_LIST_HEAD(&obj_event->obj_sub_list);
 	}

drivers/infiniband/hw/mlx5/ib_virt.c+0−1

@@ -30,7 +30,6 @@ · 29 unmodified lines
30	* SOFTWARE.	30	* SOFTWARE.
31	*/	31	*/
32		32
33	#include <linux/module.h>
34	#include <linux/mlx5/vport.h>	33	#include <linux/mlx5/vport.h>
35	#include "mlx5_ib.h"	34	#include "mlx5_ib.h"
36		35

drivers/infiniband/hw/mlx5/mem.c+0−1

@@ -30,7 +30,6 @@ · 29 unmodified lines
30	* SOFTWARE.	30	* SOFTWARE.
31	*/	31	*/
32		32
33	#include <linux/module.h>
34	#include <rdma/ib_umem.h>	33	#include <rdma/ib_umem.h>
35	#include <rdma/ib_umem_odp.h>	34	#include <rdma/ib_umem_odp.h>
36	#include "mlx5_ib.h"	35	#include "mlx5_ib.h"

drivers/infiniband/hw/mlx5/mlx5_ib.h+3−9

 	char                    name[4];
 	u32                     order;
-	u32			xlt;
 	u32			access_mode;
 	u32			page;
+	unsigned int		ndescs;
 	u8 disabled:1;
 	u8 fill_to_high_water:1;
 	u32                     miss;
 	struct mlx5_ib_dev     *dev;
-	struct work_struct	work;
 	struct delayed_work	dwork;
 };
 int mlx5_mr_cache_cleanup(struct mlx5_ib_dev *dev);
 struct mlx5_ib_mr *mlx5_mr_cache_alloc(struct mlx5_ib_dev *dev,
-				       unsigned int entry, int access_flags);
+				       struct mlx5_cache_ent *ent,
+				       int access_flags);
 int mlx5_ib_check_mr_status(struct ib_mr *ibmr, u32 check_mask,
 			    struct ib_mr_status *mr_status);
 				MLX5_UARS_IN_PAGE : 1;
 }
-static inline int get_num_static_uars(struct mlx5_ib_dev *dev,
-				      struct mlx5_bfreg_info *bfregi)
-{
-	return get_uars_per_sys_page(dev, bfregi->lib_uar_4k) * bfregi->num_static_sys_pages;
-}
 extern void *xlt_emergency_page;
 int bfregn_to_uar_index(struct mlx5_ib_dev *dev,

drivers/infiniband/hw/mlx5/mr.c+39−65

 					  struct ib_pd *pd)
 {
 	struct mlx5_ib_dev *dev = to_mdev(pd->device);
-	bool ro_pci_enabled = pcie_relaxed_ordering_enabled(dev->mdev->pdev);
 	MLX5_SET(mkc, mkc, a, !!(acc & IB_ACCESS_REMOTE_ATOMIC));
 	MLX5_SET(mkc, mkc, rw, !!(acc & IB_ACCESS_REMOTE_WRITE));
 	MLX5_SET(mkc, mkc, lw, !!(acc & IB_ACCESS_LOCAL_WRITE));
 	MLX5_SET(mkc, mkc, lr, 1);
-	if (MLX5_CAP_GEN(dev->mdev, relaxed_ordering_write))
+	if ((acc & IB_ACCESS_RELAXED_ORDERING) &&
-		MLX5_SET(mkc, mkc, relaxed_ordering_write,
+	    pcie_relaxed_ordering_enabled(dev->mdev->pdev)) {
-			 (acc & IB_ACCESS_RELAXED_ORDERING) && ro_pci_enabled);
+		if (MLX5_CAP_GEN(dev->mdev, relaxed_ordering_write))
-	if (MLX5_CAP_GEN(dev->mdev, relaxed_ordering_read))
+			MLX5_SET(mkc, mkc, relaxed_ordering_write, 1);
-		MLX5_SET(mkc, mkc, relaxed_ordering_read,
+		if (MLX5_CAP_GEN(dev->mdev, relaxed_ordering_read))
-			 (acc & IB_ACCESS_RELAXED_ORDERING) && ro_pci_enabled);
+			MLX5_SET(mkc, mkc, relaxed_ordering_read, 1);
+	}
 	MLX5_SET(mkc, mkc, pd, to_mpd(pd)->pdn);
 	MLX5_SET(mkc, mkc, qpn, 0xffffff);
 	spin_unlock_irqrestore(&ent->lock, flags);
 }
+static int get_mkc_octo_size(unsigned int access_mode, unsigned int ndescs)
+{
+	int ret = 0;
+	switch (access_mode) {
+	case MLX5_MKC_ACCESS_MODE_MTT:
+		ret = DIV_ROUND_UP(ndescs, MLX5_IB_UMR_OCTOWORD /
+						   sizeof(struct mlx5_mtt));
+		break;
+	case MLX5_MKC_ACCESS_MODE_KSM:
+		ret = DIV_ROUND_UP(ndescs, MLX5_IB_UMR_OCTOWORD /
+						   sizeof(struct mlx5_klm));
+		break;
+	default:
+		WARN_ON(1);
+	}
+	return ret;
+}
 static struct mlx5_ib_mr *alloc_cache_mr(struct mlx5_cache_ent *ent, void *mkc)
 {
 	struct mlx5_ib_mr *mr;
 	MLX5_SET(mkc, mkc, access_mode_1_0, ent->access_mode & 0x3);
 	MLX5_SET(mkc, mkc, access_mode_4_2, (ent->access_mode >> 2) & 0x7);
-	MLX5_SET(mkc, mkc, translations_octword_size, ent->xlt);
+	MLX5_SET(mkc, mkc, translations_octword_size,
+		 get_mkc_octo_size(ent->access_mode, ent->ndescs));
 	MLX5_SET(mkc, mkc, log_page_size, ent->page);
 	return mr;
 }
 		return;
 	if (ent->available_mrs < ent->limit) {
 		ent->fill_to_high_water = true;
-		queue_work(ent->dev->cache.wq, &ent->work);
+		mod_delayed_work(ent->dev->cache.wq, &ent->dwork, 0);
 	} else if (ent->fill_to_high_water &&
 		   ent->available_mrs + ent->pending < 2 * ent->limit) {
 		/*
 		 * Once we start populating due to hitting a low water mark
 		 * continue until we pass the high water mark.
 		 */
-		queue_work(ent->dev->cache.wq, &ent->work);
+		mod_delayed_work(ent->dev->cache.wq, &ent->dwork, 0);
 	} else if (ent->available_mrs == 2 * ent->limit) {
 		ent->fill_to_high_water = false;
 	} else if (ent->available_mrs > 2 * ent->limit) {
 			queue_delayed_work(ent->dev->cache.wq, &ent->dwork,
 					   msecs_to_jiffies(1000));
 		else
-			queue_work(ent->dev->cache.wq, &ent->work);
+			mod_delayed_work(ent->dev->cache.wq, &ent->dwork, 0);
 	}
 }
 	__cache_work_func(ent);
 }
-static void cache_work_func(struct work_struct *work)
-{
-	struct mlx5_cache_ent *ent;
-	ent = container_of(work, struct mlx5_cache_ent, work);
-	__cache_work_func(ent);
-}
-/* Allocate a special entry from the cache */
 struct mlx5_ib_mr *mlx5_mr_cache_alloc(struct mlx5_ib_dev *dev,
-				       unsigned int entry, int access_flags)
+				       struct mlx5_cache_ent *ent,
+				       int access_flags)
 {
-	struct mlx5_mr_cache *cache = &dev->cache;
-	struct mlx5_cache_ent *ent;
 	struct mlx5_ib_mr *mr;
-	if (WARN_ON(entry <= MR_CACHE_LAST_STD_ENTRY ||
-		    entry >= ARRAY_SIZE(cache->ent)))
-		return ERR_PTR(-EINVAL);
 	/* Matches access in alloc_cache_mr() */
 	if (!mlx5_ib_can_reconfig_with_umr(dev, 0, access_flags))
 		return ERR_PTR(-EOPNOTSUPP);
-	ent = &cache->ent[entry];
 	spin_lock_irq(&ent->lock);
 	if (list_empty(&ent->head)) {
+		queue_adjust_cache_locked(ent);
+		ent->miss++;
 		spin_unlock_irq(&ent->lock);
 		mr = create_cache_mr(ent);
 		if (IS_ERR(mr))
 		mlx5_clear_mr(mr);
 	}
-	mr->access_flags = access_flags;
 	return mr;
 }
-/* Return a MR already available in the cache */
-static struct mlx5_ib_mr *get_cache_mr(struct mlx5_cache_ent *req_ent)
-{
-	struct mlx5_ib_mr *mr = NULL;
-	struct mlx5_cache_ent *ent = req_ent;
-	spin_lock_irq(&ent->lock);
-	if (!list_empty(&ent->head)) {
-		mr = list_first_entry(&ent->head, struct mlx5_ib_mr, list);
-		list_del(&mr->list);
-		ent->available_mrs--;
-		queue_adjust_cache_locked(ent);
-		spin_unlock_irq(&ent->lock);
-		mlx5_clear_mr(mr);
-		return mr;
-	}
-	queue_adjust_cache_locked(ent);
-	spin_unlock_irq(&ent->lock);
-	req_ent->miss++;
-	return NULL;
-}
 static void mlx5_mr_cache_free(struct mlx5_ib_dev *dev, struct mlx5_ib_mr *mr)
 {
 	struct mlx5_cache_ent *ent = mr->cache_ent;
 		ent->dev = dev;
 		ent->limit = 0;
-		INIT_WORK(&ent->work, cache_work_func);
 		INIT_DELAYED_WORK(&ent->dwork, delayed_cache_work_func);
 		if (i > MR_CACHE_LAST_STD_ENTRY) {
 			continue;
 		ent->page = PAGE_SHIFT;
-		ent->xlt = (1 << ent->order) * sizeof(struct mlx5_mtt) /
+		ent->ndescs = 1 << ent->order;
-			   MLX5_IB_UMR_OCTOWORD;
 		ent->access_mode = MLX5_MKC_ACCESS_MODE_MTT;
 		if ((dev->mdev->profile.mask & MLX5_PROF_MASK_MR_CACHE) &&
 		    !dev->is_rep && mlx5_core_is_pf(dev->mdev) &&
 		spin_lock_irq(&ent->lock);
 		ent->disabled = true;
 		spin_unlock_irq(&ent->lock);
-		cancel_work_sync(&ent->work);
 		cancel_delayed_work_sync(&ent->dwork);
 	}
 		return mr;
 	}
-	mr = get_cache_mr(ent);
+	mr = mlx5_mr_cache_alloc(dev, ent, access_flags);
-	if (!mr) {
+	if (IS_ERR(mr))
-		mr = create_cache_mr(ent);
+		return mr;
-		/*
-		 * The above already tried to do the same stuff as reg_create(),
-		 * no reason to try it again.
-		 */
-		if (IS_ERR(mr))
-			return mr;
-	}
 	mr->ibmr.pd = pd;
 	mr->umem = umem;

drivers/infiniband/hw/mlx5/odp.c+10−9

 static struct mlx5_ib_mr *implicit_get_child_mr(struct mlx5_ib_mr *imr,
 						unsigned long idx)
 {
+	struct mlx5_ib_dev *dev = mr_to_mdev(imr);
 	struct ib_umem_odp *odp;
 	struct mlx5_ib_mr *mr;
 	struct mlx5_ib_mr *ret;
 	if (IS_ERR(odp))
 		return ERR_CAST(odp);
-	mr = mlx5_mr_cache_alloc(
+	mr = mlx5_mr_cache_alloc(dev, &dev->cache.ent[MLX5_IMR_MTT_CACHE_ENTRY],
-		mr_to_mdev(imr), MLX5_IMR_MTT_CACHE_ENTRY, imr->access_flags);
+				 imr->access_flags);
 	if (IS_ERR(mr)) {
 		ib_umem_odp_release(odp);
 		return mr;
 	}
+	mr->access_flags = imr->access_flags;
 	mr->ibmr.pd = imr->ibmr.pd;
 	mr->ibmr.device = &mr_to_mdev(imr)->ib_dev;
 	mr->umem = &odp->umem;
 	if (IS_ERR(umem_odp))
 		return ERR_CAST(umem_odp);
-	imr = mlx5_mr_cache_alloc(dev, MLX5_IMR_KSM_CACHE_ENTRY, access_flags);
+	imr = mlx5_mr_cache_alloc(dev,
+				  &dev->cache.ent[MLX5_IMR_KSM_CACHE_ENTRY],
+				  access_flags);
 	if (IS_ERR(imr)) {
 		ib_umem_odp_release(umem_odp);
 		return imr;
 	}
+	imr->access_flags = access_flags;
 	imr->ibmr.pd = &pd->ibpd;
 	imr->ibmr.iova = 0;
 	imr->umem = &umem_odp->umem;
 	switch (ent->order - 2) {
 	case MLX5_IMR_MTT_CACHE_ENTRY:
 		ent->page = PAGE_SHIFT;
-		ent->xlt = MLX5_IMR_MTT_ENTRIES *
+		ent->ndescs = MLX5_IMR_MTT_ENTRIES;
-			   sizeof(struct mlx5_mtt) /
-			   MLX5_IB_UMR_OCTOWORD;
 		ent->access_mode = MLX5_MKC_ACCESS_MODE_MTT;
 		ent->limit = 0;
 		break;
 	case MLX5_IMR_KSM_CACHE_ENTRY:
 		ent->page = MLX5_KSM_PAGE_SHIFT;
-		ent->xlt = mlx5_imr_ksm_entries *
+		ent->ndescs = mlx5_imr_ksm_entries;
-			   sizeof(struct mlx5_klm) /
-			   MLX5_IB_UMR_OCTOWORD;
 		ent->access_mode = MLX5_MKC_ACCESS_MODE_KSM;
 		ent->limit = 0;
 		break;

drivers/infiniband/hw/mlx5/qp.c+2−2

  */
 #include <linux/etherdevice.h>
-#include <linux/module.h>
 #include <rdma/ib_umem.h>
 #include <rdma/ib_cache.h>
 #include <rdma/ib_user_verbs.h>
 static int max_bfregs(struct mlx5_ib_dev *dev, struct mlx5_bfreg_info *bfregi)
 {
-	return get_num_static_uars(dev, bfregi) * MLX5_NON_FP_BFREGS_PER_UAR;
+	return get_uars_per_sys_page(dev, bfregi->lib_uar_4k) *
+	       bfregi->num_static_sys_pages * MLX5_NON_FP_BFREGS_PER_UAR;
 }
 static int num_med_bfreg(struct mlx5_ib_dev *dev,

drivers/infiniband/hw/mlx5/srq.c+0−1

@@ -3,7 +3,6 @@ · 2 unmodified lines
3	* Copyright (c) 2013-2018, Mellanox Technologies inc. All rights reserved.	3	* Copyright (c) 2013-2018, Mellanox Technologies inc. All rights reserved.
4	*/	4	*/
5		5
6	#include <linux/module.h>
7	#include <linux/mlx5/qp.h>	6	#include <linux/mlx5/qp.h>
8	#include <linux/slab.h>	7	#include <linux/slab.h>
9	#include <rdma/ib_umem.h>	8	#include <rdma/ib_umem.h>

drivers/infiniband/hw/mthca/mthca_main.c+2−6

 	err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));
 	if (err) {
-		dev_warn(&pdev->dev, "Warning: couldn't set 64-bit PCI DMA mask.\n");
+		dev_err(&pdev->dev, "Can't set PCI DMA mask, aborting.\n");
-		err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
+		goto err_free_res;
-		if (err) {
-			dev_err(&pdev->dev, "Can't set PCI DMA mask, aborting.\n");
-			goto err_free_res;
-		}
 	}
 	/* We can handle large RDMA requests, so allow larger segments. */

drivers/infiniband/hw/mthca/mthca_profile.c+0−2

@@ -31,8 +31,6 @@ · 30 unmodified lines
31	* SOFTWARE.	31	* SOFTWARE.
32	*/	32	*/
33		33
34	#include <linux/module.h>
35	#include <linux/moduleparam.h>
36	#include <linux/string.h>	34	#include <linux/string.h>
37	#include <linux/slab.h>	35	#include <linux/slab.h>
38		36

drivers/infiniband/hw/qib/qib_fs.c+0−1

@@ -32,7 +32,6 @@ · 31 unmodified lines
32	* SOFTWARE.	32	* SOFTWARE.
33	*/	33	*/
34		34
35	#include <linux/module.h>
36	#include <linux/fs.h>	35	#include <linux/fs.h>
37	#include <linux/fs_context.h>	36	#include <linux/fs_context.h>
38	#include <linux/mount.h>	37	#include <linux/mount.h>

drivers/infiniband/hw/qib/qib_iba7220.c+2−2

drivers/infiniband/hw/usnic/usnic_debugfs.c+0−1

@@ -32,7 +32,6 @@ · 31 unmodified lines
32	*/	32	*/
33		33
34	#include <linux/debugfs.h>	34	#include <linux/debugfs.h>
35	#include <linux/module.h>
36		35
37	#include "usnic.h"	36	#include "usnic.h"
38	#include "usnic_log.h"	37	#include "usnic_log.h"

drivers/infiniband/hw/usnic/usnic_ib_qp_grp.c+0−1

@@ -32,7 +32,6 @@ · 31 unmodified lines
32	*/	32	*/
33	#include <linux/bug.h>	33	#include <linux/bug.h>
34	#include <linux/errno.h>	34	#include <linux/errno.h>
35	#include <linux/module.h>
36	#include <linux/spinlock.h>	35	#include <linux/spinlock.h>
37		36
38	#include "usnic_log.h"	37	#include "usnic_log.h"

drivers/infiniband/hw/usnic/usnic_ib_sysfs.c+0−1

@@ -31,7 +31,6 @@ · 30 unmodified lines
31	*	31	*
32	*/	32	*/
33		33
34	#include <linux/module.h>
35	#include <linux/init.h>	34	#include <linux/init.h>
36	#include <linux/errno.h>	35	#include <linux/errno.h>
37		36

drivers/infiniband/hw/usnic/usnic_ib_verbs.c+0−1

@@ -30,7 +30,6 @@ · 29 unmodified lines
30	* SOFTWARE.	30	* SOFTWARE.
31	*	31	*
32	*/	32	*/
33	#include <linux/module.h>
34	#include <linux/init.h>	33	#include <linux/init.h>
35	#include <linux/slab.h>	34	#include <linux/slab.h>
36	#include <linux/errno.h>	35	#include <linux/errno.h>

drivers/infiniband/hw/usnic/usnic_transport.c+0−1

@@ -32,7 +32,6 @@ · 31 unmodified lines
32	*/	32	*/
33	#include <linux/bitmap.h>	33	#include <linux/bitmap.h>
34	#include <linux/file.h>	34	#include <linux/file.h>
35	#include <linux/module.h>
36	#include <linux/slab.h>	35	#include <linux/slab.h>
37	#include <net/inet_sock.h>	36	#include <net/inet_sock.h>
38		37

drivers/infiniband/hw/usnic/usnic_vnic.c+0−1

@@ -31,7 +31,6 @@ · 30 unmodified lines
31	*	31	*
32	*/	32	*/
33	#include <linux/errno.h>	33	#include <linux/errno.h>
34	#include <linux/module.h>
35	#include <linux/pci.h>	34	#include <linux/pci.h>
36		35
37	#include "usnic_ib.h"	36	#include "usnic_ib.h"

drivers/infiniband/hw/vmw_pvrdma/pvrdma_main.c+4−6

 	}
 	/* Enable 64-Bit DMA */
-	if (dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)) != 0) {
+	ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));
-		ret = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
+	if (ret) {
-		if (ret != 0) {
+		dev_err(&pdev->dev, "dma_set_mask failed\n");
-			dev_err(&pdev->dev, "dma_set_mask failed\n");
+		goto err_free_resource;
-			goto err_free_resource;
-		}
 	}
 	dma_set_max_seg_size(&pdev->dev, UINT_MAX);
 	pci_set_master(pdev);

drivers/infiniband/sw/rxe/rxe.c+18−92

@@ -28,8 +28,8 @@ void rxe_dealloc(struct ib_device *ib_dev) · 27 unmodified lines
28	rxe_pool_cleanup(&rxe->cq_pool);	28	rxe_pool_cleanup(&rxe->cq_pool);
29	rxe_pool_cleanup(&rxe->mr_pool);	29	rxe_pool_cleanup(&rxe->mr_pool);
30	rxe_pool_cleanup(&rxe->mw_pool);	30	rxe_pool_cleanup(&rxe->mw_pool);
31	rxe_pool_cleanup(&rxe->mc_grp_pool);	31
32	rxe_pool_cleanup(&rxe->mc_elem_pool);	32	WARN_ON(!RB_EMPTY_ROOT(&rxe->mcg_tree));
33		33
34	if (rxe->tfm)	34	if (rxe->tfm)
35	crypto_free_shash(rxe->tfm);	35	crypto_free_shash(rxe->tfm);
@@ -114,106 +114,37 @@ static void rxe_init_ports(struct rxe_dev *rxe) · 78 unmodified lines
114	}	114	}
115		115
116	/* init pools of managed objects */	116	/* init pools of managed objects */
117	static int rxe_init_pools(struct rxe_dev *rxe)	117	static void rxe_init_pools(struct rxe_dev *rxe)
118	{	118	{
119	int err;	119	rxe_pool_init(rxe, &rxe->uc_pool, RXE_TYPE_UC);
120		120	rxe_pool_init(rxe, &rxe->pd_pool, RXE_TYPE_PD);
121	err = rxe_pool_init(rxe, &rxe->uc_pool, RXE_TYPE_UC,	121	rxe_pool_init(rxe, &rxe->ah_pool, RXE_TYPE_AH);
122	rxe->max_ucontext);	122	rxe_pool_init(rxe, &rxe->srq_pool, RXE_TYPE_SRQ);
123	if (err)	123	rxe_pool_init(rxe, &rxe->qp_pool, RXE_TYPE_QP);
124	goto err1;	124	rxe_pool_init(rxe, &rxe->cq_pool, RXE_TYPE_CQ);
125		125	rxe_pool_init(rxe, &rxe->mr_pool, RXE_TYPE_MR);
126	err = rxe_pool_init(rxe, &rxe->pd_pool, RXE_TYPE_PD,	126	rxe_pool_init(rxe, &rxe->mw_pool, RXE_TYPE_MW);
127	rxe->attr.max_pd);
128	if (err)
129	goto err2;
130
131	err = rxe_pool_init(rxe, &rxe->ah_pool, RXE_TYPE_AH,
132	rxe->attr.max_ah);
133	if (err)
134	goto err3;
135
136	err = rxe_pool_init(rxe, &rxe->srq_pool, RXE_TYPE_SRQ,
137	rxe->attr.max_srq);
138	if (err)
139	goto err4;
140
141	err = rxe_pool_init(rxe, &rxe->qp_pool, RXE_TYPE_QP,
142	rxe->attr.max_qp);
143	if (err)
144	goto err5;
145
146	err = rxe_pool_init(rxe, &rxe->cq_pool, RXE_TYPE_CQ,
147	rxe->attr.max_cq);
148	if (err)
149	goto err6;
150
151	err = rxe_pool_init(rxe, &rxe->mr_pool, RXE_TYPE_MR,
152	rxe->attr.max_mr);
153	if (err)
154	goto err7;
155
156	err = rxe_pool_init(rxe, &rxe->mw_pool, RXE_TYPE_MW,
157	rxe->attr.max_mw);
158	if (err)
159	goto err8;
160
161	err = rxe_pool_init(rxe, &rxe->mc_grp_pool, RXE_TYPE_MC_GRP,
162	rxe->attr.max_mcast_grp);
163	if (err)
164	goto err9;
165
166	err = rxe_pool_init(rxe, &rxe->mc_elem_pool, RXE_TYPE_MC_ELEM,
167	rxe->attr.max_total_mcast_qp_attach);
168	if (err)
169	goto err10;
170
171	return 0;
172
173	err10:
174	rxe_pool_cleanup(&rxe->mc_grp_pool);
175	err9:
176	rxe_pool_cleanup(&rxe->mw_pool);
177	err8:
178	rxe_pool_cleanup(&rxe->mr_pool);
179	err7:
180	rxe_pool_cleanup(&rxe->cq_pool);
181	err6:
182	rxe_pool_cleanup(&rxe->qp_pool);
183	err5:
184	rxe_pool_cleanup(&rxe->srq_pool);
185	err4:
186	rxe_pool_cleanup(&rxe->ah_pool);
187	err3:
188	rxe_pool_cleanup(&rxe->pd_pool);
189	err2:
190	rxe_pool_cleanup(&rxe->uc_pool);
191	err1:
192	return err;
193	}	127	}
194		128
195	/* initialize rxe device state */	129	/* initialize rxe device state */
196	static int rxe_init(struct rxe_dev *rxe)	130	static void rxe_init(struct rxe_dev *rxe)
197	{	131	{
198	int err;
199
200	/* init default device parameters */	132	/* init default device parameters */
201	rxe_init_device_param(rxe);	133	rxe_init_device_param(rxe);
202		134
203	rxe_init_ports(rxe);	135	rxe_init_ports(rxe);
204		136	rxe_init_pools(rxe);
205	err = rxe_init_pools(rxe);
206	if (err)
207	return err;
208		137
209	/* init pending mmap list */	138	/* init pending mmap list */
210	spin_lock_init(&rxe->mmap_offset_lock);	139	spin_lock_init(&rxe->mmap_offset_lock);
211	spin_lock_init(&rxe->pending_lock);	140	spin_lock_init(&rxe->pending_lock);
212	INIT_LIST_HEAD(&rxe->pending_mmaps);	141	INIT_LIST_HEAD(&rxe->pending_mmaps);
213		142
214	mutex_init(&rxe->usdev_lock);	143	/* init multicast support */
		144	spin_lock_init(&rxe->mcg_lock);
		145	rxe->mcg_tree = RB_ROOT;
215		146
216	return 0;	147	mutex_init(&rxe->usdev_lock);
217	}	148	}
218		149
219	void rxe_set_mtu(struct rxe_dev *rxe, unsigned int ndev_mtu)	150	void rxe_set_mtu(struct rxe_dev *rxe, unsigned int ndev_mtu)
@@ -235,12 +166,7 @@ void rxe_set_mtu(struct rxe_dev *rxe, unsigned int ndev_mtu) · 15 unmodified lines
235	*/	166	*/
236	int rxe_add(struct rxe_dev rxe, unsigned int mtu, const char ibdev_name)	167	int rxe_add(struct rxe_dev rxe, unsigned int mtu, const char ibdev_name)
237	{	168	{
238	int err;	169	rxe_init(rxe);
239
240	err = rxe_init(rxe);
241	if (err)
242	return err;
243
244	rxe_set_mtu(rxe, mtu);	170	rxe_set_mtu(rxe, mtu);
245		171
246	return rxe_register_device(rxe, ibdev_name);	172	return rxe_register_device(rxe, ibdev_name);

drivers/infiniband/sw/rxe/rxe.h+0−1

@@ -12,7 +12,6 @@ · 11 unmodified lines
12	#endif	12	#endif
13	#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt	13	#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
14		14
15	#include <linux/module.h>
16	#include <linux/skbuff.h>	15	#include <linux/skbuff.h>
17		16
18	#include <rdma/ib_verbs.h>	17	#include <rdma/ib_verbs.h>

drivers/infiniband/sw/rxe/rxe_av.c+17−2

 	av->network_type = type;
 }
-struct rxe_av *rxe_get_av(struct rxe_pkt_info *pkt)
+struct rxe_av *rxe_get_av(struct rxe_pkt_info *pkt, struct rxe_ah **ahp)
 {
 	struct rxe_ah *ah;
 	u32 ah_num;
+	if (ahp)
+		*ahp = NULL;
 	if (!pkt || !pkt->qp)
 		return NULL;
 	if (ah_num) {
 		/* only new user provider or kernel client */
 		ah = rxe_pool_get_index(&pkt->rxe->ah_pool, ah_num);
-		if (!ah || ah->ah_num != ah_num || rxe_ah_pd(ah) != pkt->qp->pd) {
+		if (!ah) {
 			pr_warn("Unable to find AH matching ah_num\n");
 			return NULL;
 		}
+		if (rxe_ah_pd(ah) != pkt->qp->pd) {
+			pr_warn("PDs don't match for AH and QP\n");
+			rxe_put(ah);
+			return NULL;
+		}
+		if (ahp)
+			*ahp = ah;
+		else
+			rxe_put(ah);
 		return &ah->av;
 	}

drivers/infiniband/sw/rxe/rxe_comp.c+4−4

@@ -526,7 +526,7 @@ static void rxe_drain_resp_pkts(struct rxe_qp *qp, bool notify) · 525 unmodified lines
526	struct rxe_queue *q = qp->sq.queue;	526	struct rxe_queue *q = qp->sq.queue;
527		527
528	while ((skb = skb_dequeue(&qp->resp_pkts))) {	528	while ((skb = skb_dequeue(&qp->resp_pkts))) {
529	rxe_drop_ref(qp);	529	rxe_put(qp);
530	kfree_skb(skb);	530	kfree_skb(skb);
531	ib_device_put(qp->ibqp.device);	531	ib_device_put(qp->ibqp.device);
532	}	532	}
@@ -548,7 +548,7 @@ static void free_pkt(struct rxe_pkt_info *pkt) · 15 unmodified lines
548	struct ib_device *dev = qp->ibqp.device;	548	struct ib_device *dev = qp->ibqp.device;
549		549
550	kfree_skb(skb);	550	kfree_skb(skb);
551	rxe_drop_ref(qp);	551	rxe_put(qp);
552	ib_device_put(dev);	552	ib_device_put(dev);
553	}	553	}
554		554
@@ -562,7 +562,7 @@ int rxe_completer(void *arg) · 7 unmodified lines
562	enum comp_state state;	562	enum comp_state state;
563	int ret = 0;	563	int ret = 0;
564		564
565	rxe_add_ref(qp);	565	rxe_get(qp);
566		566
567	if (!qp->valid \|\| qp->req.state == QP_STATE_ERROR \|\|	567	if (!qp->valid \|\| qp->req.state == QP_STATE_ERROR \|\|
568	qp->req.state == QP_STATE_RESET) {	568	qp->req.state == QP_STATE_RESET) {
@@ -761,7 +761,7 @@ int rxe_completer(void *arg) · 192 unmodified lines
761	done:	761	done:
762	if (pkt)	762	if (pkt)
763	free_pkt(pkt);	763	free_pkt(pkt);
764	rxe_drop_ref(qp);	764	rxe_put(qp);
765		765
766	return ret;	766	return ret;
767	}	767	}

drivers/infiniband/sw/rxe/rxe_cq.c+12−8

 static void rxe_send_complete(struct tasklet_struct *t)
 {
 	struct rxe_cq *cq = from_tasklet(cq, t, comp_task);
+	unsigned long flags;
-	spin_lock_bh(&cq->cq_lock);
+	spin_lock_irqsave(&cq->cq_lock, flags);
 	if (cq->is_dying) {
-		spin_unlock_bh(&cq->cq_lock);
+		spin_unlock_irqrestore(&cq->cq_lock, flags);
 		return;
 	}
-	spin_unlock_bh(&cq->cq_lock);
+	spin_unlock_irqrestore(&cq->cq_lock, flags);
 	cq->ibcq.comp_handler(&cq->ibcq, cq->ibcq.cq_context);
 }
 	struct ib_event ev;
 	int full;
 	void *addr;
+	unsigned long flags;
-	spin_lock_bh(&cq->cq_lock);
+	spin_lock_irqsave(&cq->cq_lock, flags);
 	full = queue_full(cq->queue, QUEUE_TYPE_TO_CLIENT);
 	if (unlikely(full)) {
-		spin_unlock_bh(&cq->cq_lock);
+		spin_unlock_irqrestore(&cq->cq_lock, flags);
 		if (cq->ibcq.event_handler) {
 			ev.device = cq->ibcq.device;
 			ev.element.cq = &cq->ibcq;
 	queue_advance_producer(cq->queue, QUEUE_TYPE_TO_CLIENT);
-	spin_unlock_bh(&cq->cq_lock);
+	spin_unlock_irqrestore(&cq->cq_lock, flags);
 	if ((cq->notify == IB_CQ_NEXT_COMP) ||
 	    (cq->notify == IB_CQ_SOLICITED && solicited)) {
 void rxe_cq_disable(struct rxe_cq *cq)
 {
-	spin_lock_bh(&cq->cq_lock);
+	unsigned long flags;
+	spin_lock_irqsave(&cq->cq_lock, flags);
 	cq->is_dying = true;
-	spin_unlock_bh(&cq->cq_lock);
+	spin_unlock_irqrestore(&cq->cq_lock, flags);
 }
 void rxe_cq_cleanup(struct rxe_pool_elem *elem)

drivers/infiniband/sw/rxe/rxe_loc.h+8−24

@@ -19,7 +19,7 @@ void rxe_av_to_attr(struct rxe_av av, struct rdma_ah_attr attr); · 18 unmodified lines
19		19
20	void rxe_av_fill_ip_info(struct rxe_av av, struct rdma_ah_attr attr);	20	void rxe_av_fill_ip_info(struct rxe_av av, struct rdma_ah_attr attr);
21		21
22	struct rxe_av rxe_get_av(struct rxe_pkt_info pkt);	22	struct rxe_av rxe_get_av(struct rxe_pkt_info pkt, struct rxe_ah **ahp);
23		23
24	/* rxe_cq.c */	24	/* rxe_cq.c */
25	int rxe_cq_chk_attr(struct rxe_dev rxe, struct rxe_cq cq,	25	int rxe_cq_chk_attr(struct rxe_dev rxe, struct rxe_cq cq,
@@ -40,18 +40,10 @@ void rxe_cq_disable(struct rxe_cq *cq); · 14 unmodified lines
40	void rxe_cq_cleanup(struct rxe_pool_elem *arg);	40	void rxe_cq_cleanup(struct rxe_pool_elem *arg);
41		41
42	/* rxe_mcast.c */	42	/* rxe_mcast.c */
43	int rxe_mcast_get_grp(struct rxe_dev rxe, union ib_gid mgid,	43	struct rxe_mcg rxe_lookup_mcg(struct rxe_dev rxe, union ib_gid *mgid);
44	struct rxe_mc_grp **grp_p);	44	int rxe_attach_mcast(struct ib_qp ibqp, union ib_gid mgid, u16 mlid);
45		45	int rxe_detach_mcast(struct ib_qp ibqp, union ib_gid mgid, u16 mlid);
46	int rxe_mcast_add_grp_elem(struct rxe_dev rxe, struct rxe_qp qp,	46	void rxe_cleanup_mcg(struct kref *kref);
47	struct rxe_mc_grp *grp);
48
49	int rxe_mcast_drop_grp_elem(struct rxe_dev rxe, struct rxe_qp qp,
50	union ib_gid *mgid);
51
52	void rxe_drop_all_mcast_groups(struct rxe_qp *qp);
53
54	void rxe_mc_cleanup(struct rxe_pool_elem *arg);
55		47
56	/* rxe_mmap.c */	48	/* rxe_mmap.c */
57	struct rxe_mmap_info {	49	struct rxe_mmap_info {
@@ -102,35 +94,27 @@ void rxe_mw_cleanup(struct rxe_pool_elem *arg); · 44 unmodified lines
102	/* rxe_net.c */	94	/* rxe_net.c */
103	struct sk_buff rxe_init_packet(struct rxe_dev rxe, struct rxe_av *av,	95	struct sk_buff rxe_init_packet(struct rxe_dev rxe, struct rxe_av *av,
104	int paylen, struct rxe_pkt_info *pkt);	96	int paylen, struct rxe_pkt_info *pkt);
105	int rxe_prepare(struct rxe_pkt_info pkt, struct sk_buff skb);	97	int rxe_prepare(struct rxe_av av, struct rxe_pkt_info pkt,
		98	struct sk_buff *skb);
106	int rxe_xmit_packet(struct rxe_qp qp, struct rxe_pkt_info pkt,	99	int rxe_xmit_packet(struct rxe_qp qp, struct rxe_pkt_info pkt,
107	struct sk_buff *skb);	100	struct sk_buff *skb);
108	const char rxe_parent_name(struct rxe_dev rxe, unsigned int port_num);	101	const char rxe_parent_name(struct rxe_dev rxe, unsigned int port_num);
109	int rxe_mcast_add(struct rxe_dev rxe, union ib_gid mgid);
110	int rxe_mcast_delete(struct rxe_dev rxe, union ib_gid mgid);
111		102
112	/* rxe_qp.c */	103	/* rxe_qp.c */
113	int rxe_qp_chk_init(struct rxe_dev rxe, struct ib_qp_init_attr init);	104	int rxe_qp_chk_init(struct rxe_dev rxe, struct ib_qp_init_attr init);
114
115	int rxe_qp_from_init(struct rxe_dev rxe, struct rxe_qp qp, struct rxe_pd *pd,	105	int rxe_qp_from_init(struct rxe_dev rxe, struct rxe_qp qp, struct rxe_pd *pd,
116	struct ib_qp_init_attr *init,	106	struct ib_qp_init_attr *init,
117	struct rxe_create_qp_resp __user *uresp,	107	struct rxe_create_qp_resp __user *uresp,
118	struct ib_pd ibpd, struct ib_udata udata);	108	struct ib_pd ibpd, struct ib_udata udata);
119
120	int rxe_qp_to_init(struct rxe_qp qp, struct ib_qp_init_attr init);	109	int rxe_qp_to_init(struct rxe_qp qp, struct ib_qp_init_attr init);
121
122	int rxe_qp_chk_attr(struct rxe_dev rxe, struct rxe_qp qp,	110	int rxe_qp_chk_attr(struct rxe_dev rxe, struct rxe_qp qp,
123	struct ib_qp_attr *attr, int mask);	111	struct ib_qp_attr *attr, int mask);
124
125	int rxe_qp_from_attr(struct rxe_qp qp, struct ib_qp_attr attr,	112	int rxe_qp_from_attr(struct rxe_qp qp, struct ib_qp_attr attr,
126	int mask, struct ib_udata *udata);	113	int mask, struct ib_udata *udata);
127
128	int rxe_qp_to_attr(struct rxe_qp qp, struct ib_qp_attr attr, int mask);	114	int rxe_qp_to_attr(struct rxe_qp qp, struct ib_qp_attr attr, int mask);
129
130	void rxe_qp_error(struct rxe_qp *qp);	115	void rxe_qp_error(struct rxe_qp *qp);
131		116	int rxe_qp_chk_destroy(struct rxe_qp *qp);
132	void rxe_qp_destroy(struct rxe_qp *qp);	117	void rxe_qp_destroy(struct rxe_qp *qp);
133
134	void rxe_qp_cleanup(struct rxe_pool_elem *elem);	118	void rxe_qp_cleanup(struct rxe_pool_elem *elem);
135		119
136	static inline int qp_num(struct rxe_qp *qp)	120	static inline int qp_num(struct rxe_qp *qp)

drivers/infiniband/sw/rxe/rxe_mcast.c+426−116

@@ -1,178 +1,488 @@
1	// SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB	1	// SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB
2	/*	2	/*
		3	* Copyright (c) 2022 Hewlett Packard Enterprise, Inc. All rights reserved.
3	* Copyright (c) 2016 Mellanox Technologies Ltd. All rights reserved.	4	* Copyright (c) 2016 Mellanox Technologies Ltd. All rights reserved.
4	* Copyright (c) 2015 System Fabric Works, Inc. All rights reserved.	5	* Copyright (c) 2015 System Fabric Works, Inc. All rights reserved.
5	*/	6	*/
6		7
		8	/*
		9	* rxe_mcast.c implements driver support for multicast transport.
		10	* It is based on two data structures struct rxe_mcg ('mcg') and
		11	* struct rxe_mca ('mca'). An mcg is allocated each time a qp is
		12	* attached to a new mgid for the first time. These are indexed by
		13	* a red-black tree using the mgid. This data structure is searched
		14	* for the mcg when a multicast packet is received and when another
		15	* qp is attached to the same mgid. It is cleaned up when the last qp
		16	* is detached from the mcg. Each time a qp is attached to an mcg an
		17	* mca is created. It holds a pointer to the qp and is added to a list
		18	* of qp's that are attached to the mcg. The qp_list is used to replicate
		19	* mcast packets in the rxe receive path.
		20	*/
		21
7	#include "rxe.h"	22	#include "rxe.h"
8	#include "rxe_loc.h"
9		23
10	/* caller should hold mc_grp_pool->pool_lock */	24	/**
11	static struct rxe_mc_grp create_grp(struct rxe_dev rxe,	25	* rxe_mcast_add - add multicast address to rxe device
12	struct rxe_pool *pool,	26	* @rxe: rxe device object
13	union ib_gid *mgid)	27	* @mgid: multicast address as a gid
		28	*
		29	* Returns 0 on success else an error
		30	*/
		31	static int rxe_mcast_add(struct rxe_dev rxe, union ib_gid mgid)
14	{	32	{
15	int err;	33	unsigned char ll_addr[ETH_ALEN];
16	struct rxe_mc_grp *grp;
17		34
18	grp = rxe_alloc_locked(&rxe->mc_grp_pool);	35	ipv6_eth_mc_map((struct in6_addr *)mgid->raw, ll_addr);
19	if (!grp)
20	return ERR_PTR(-ENOMEM);
21		36
22	INIT_LIST_HEAD(&grp->qp_list);	37	return dev_mc_add(rxe->ndev, ll_addr);
23	spin_lock_init(&grp->mcg_lock);	38	}
24	grp->rxe = rxe;
25	rxe_add_key_locked(grp, mgid);
26		39
27	err = rxe_mcast_add(rxe, mgid);	40	/**
28	if (unlikely(err)) {	41	* rxe_mcast_delete - delete multicast address from rxe device
29	rxe_drop_key_locked(grp);	42	* @rxe: rxe device object
30	rxe_drop_ref(grp);	43	* @mgid: multicast address as a gid
31	return ERR_PTR(err);	44	*
		45	* Returns 0 on success else an error
		46	*/
		47	static int rxe_mcast_delete(struct rxe_dev rxe, union ib_gid mgid)
		48	{
		49	unsigned char ll_addr[ETH_ALEN];
		50
		51	ipv6_eth_mc_map((struct in6_addr *)mgid->raw, ll_addr);
		52
		53	return dev_mc_del(rxe->ndev, ll_addr);
		54	}
		55
		56	/**
		57	* __rxe_insert_mcg - insert an mcg into red-black tree (rxe->mcg_tree)
		58	* @mcg: mcg object with an embedded red-black tree node
		59	*
		60	* Context: caller must hold a reference to mcg and rxe->mcg_lock and
		61	* is responsible to avoid adding the same mcg twice to the tree.
		62	*/
		63	static void __rxe_insert_mcg(struct rxe_mcg *mcg)
		64	{
		65	struct rb_root *tree = &mcg->rxe->mcg_tree;
		66	struct rb_node **link = &tree->rb_node;
		67	struct rb_node *node = NULL;
		68	struct rxe_mcg *tmp;
		69	int cmp;
		70
		71	while (*link) {
		72	node = *link;
		73	tmp = rb_entry(node, struct rxe_mcg, node);
		74
		75	cmp = memcmp(&tmp->mgid, &mcg->mgid, sizeof(mcg->mgid));
		76	if (cmp > 0)
		77	link = &(*link)->rb_left;
		78	else
		79	link = &(*link)->rb_right;
32	}	80	}
33		81
34	return grp;	82	rb_link_node(&mcg->node, node, link);
		83	rb_insert_color(&mcg->node, tree);
35	}	84	}
36		85
37	int rxe_mcast_get_grp(struct rxe_dev rxe, union ib_gid mgid,	86	/**
38	struct rxe_mc_grp **grp_p)	87	* __rxe_remove_mcg - remove an mcg from red-black tree holding lock
		88	* @mcg: mcast group object with an embedded red-black tree node
		89	*
		90	* Context: caller must hold a reference to mcg and rxe->mcg_lock
		91	*/
		92	static void __rxe_remove_mcg(struct rxe_mcg *mcg)
39	{	93	{
40	int err;	94	rb_erase(&mcg->node, &mcg->rxe->mcg_tree);
41	struct rxe_mc_grp *grp;	95	}
42	struct rxe_pool *pool = &rxe->mc_grp_pool;
43		96
44	if (rxe->attr.max_mcast_qp_attach == 0)	97	/**
45	return -EINVAL;	98	* __rxe_lookup_mcg - lookup mcg in rxe->mcg_tree while holding lock
		99	* @rxe: rxe device object
		100	* @mgid: multicast IP address
		101	*
		102	* Context: caller must hold rxe->mcg_lock
		103	* Returns: mcg on success and takes a ref to mcg else NULL
		104	*/
		105	static struct rxe_mcg __rxe_lookup_mcg(struct rxe_dev rxe,
		106	union ib_gid *mgid)
		107	{
		108	struct rb_root *tree = &rxe->mcg_tree;
		109	struct rxe_mcg *mcg;
		110	struct rb_node *node;
		111	int cmp;
46		112
47	write_lock_bh(&pool->pool_lock);	113	node = tree->rb_node;
48		114
49	grp = rxe_pool_get_key_locked(pool, mgid);	115	while (node) {
50	if (grp)	116	mcg = rb_entry(node, struct rxe_mcg, node);
51	goto done;
52		117
53	grp = create_grp(rxe, pool, mgid);	118	cmp = memcmp(&mcg->mgid, mgid, sizeof(*mgid));
54	if (IS_ERR(grp)) {	119
55	write_unlock_bh(&pool->pool_lock);	120	if (cmp > 0)
56	err = PTR_ERR(grp);	121	node = node->rb_left;
57	return err;	122	else if (cmp < 0)
		123	node = node->rb_right;
		124	else
		125	break;
58	}	126	}
59		127
60	done:	128	if (node) {
61	write_unlock_bh(&pool->pool_lock);	129	kref_get(&mcg->ref_cnt);
62	*grp_p = grp;	130	return mcg;
		131	}
		132
		133	return NULL;
		134	}
		135
		136	/**
		137	* rxe_lookup_mcg - lookup up mcg in red-back tree
		138	* @rxe: rxe device object
		139	* @mgid: multicast IP address
		140	*
		141	* Returns: mcg if found else NULL
		142	*/
		143	struct rxe_mcg rxe_lookup_mcg(struct rxe_dev rxe, union ib_gid *mgid)
		144	{
		145	struct rxe_mcg *mcg;
		146	unsigned long flags;
		147
		148	spin_lock_irqsave(&rxe->mcg_lock, flags);
		149	mcg = __rxe_lookup_mcg(rxe, mgid);
		150	spin_unlock_irqrestore(&rxe->mcg_lock, flags);
		151
		152	return mcg;
		153	}
		154
		155	/**
		156	* __rxe_init_mcg - initialize a new mcg
		157	* @rxe: rxe device
		158	* @mgid: multicast address as a gid
		159	* @mcg: new mcg object
		160	*
		161	* Context: caller should hold rxe->mcg lock
		162	* Returns: 0 on success else an error
		163	*/
		164	static int __rxe_init_mcg(struct rxe_dev rxe, union ib_gid mgid,
		165	struct rxe_mcg *mcg)
		166	{
		167	int err;
		168
		169	err = rxe_mcast_add(rxe, mgid);
		170	if (unlikely(err))
		171	return err;
		172
		173	kref_init(&mcg->ref_cnt);
		174	memcpy(&mcg->mgid, mgid, sizeof(mcg->mgid));
		175	INIT_LIST_HEAD(&mcg->qp_list);
		176	mcg->rxe = rxe;
		177
		178	/* caller holds a ref on mcg but that will be
		179	* dropped when mcg goes out of scope. We need to take a ref
		180	* on the pointer that will be saved in the red-black tree
		181	* by __rxe_insert_mcg and used to lookup mcg from mgid later.
		182	* Inserting mcg makes it visible to outside so this should
		183	* be done last after the object is ready.
		184	*/
		185	kref_get(&mcg->ref_cnt);
		186	__rxe_insert_mcg(mcg);
		187
63	return 0;	188	return 0;
64	}	189	}
65		190
66	int rxe_mcast_add_grp_elem(struct rxe_dev rxe, struct rxe_qp qp,	191	/**
67	struct rxe_mc_grp *grp)	192	* rxe_get_mcg - lookup or allocate a mcg
		193	* @rxe: rxe device object
		194	* @mgid: multicast IP address as a gid
		195	*
		196	* Returns: mcg on success else ERR_PTR(error)
		197	*/
		198	static struct rxe_mcg rxe_get_mcg(struct rxe_dev rxe, union ib_gid *mgid)
68	{	199	{
		200	struct rxe_mcg mcg, tmp;
		201	unsigned long flags;
69	int err;	202	int err;
70	struct rxe_mc_elem *elem;
71		203
72	/* check to see of the qp is already a member of the group */	204	if (rxe->attr.max_mcast_grp == 0)
73	spin_lock_bh(&qp->grp_lock);	205	return ERR_PTR(-EINVAL);
74	spin_lock_bh(&grp->mcg_lock);
75	list_for_each_entry(elem, &grp->qp_list, qp_list) {
76	if (elem->qp == qp) {
77	err = 0;
78	goto out;
79	}
80	}
81		206
82	if (grp->num_qp >= rxe->attr.max_mcast_qp_attach) {	207	/* check to see if mcg already exists */
83	err = -ENOMEM;	208	mcg = rxe_lookup_mcg(rxe, mgid);
		209	if (mcg)
		210	return mcg;
		211
		212	/* speculative alloc of new mcg */
		213	mcg = kzalloc(sizeof(*mcg), GFP_KERNEL);
		214	if (!mcg)
		215	return ERR_PTR(-ENOMEM);
		216
		217	spin_lock_irqsave(&rxe->mcg_lock, flags);
		218	/* re-check to see if someone else just added it */
		219	tmp = __rxe_lookup_mcg(rxe, mgid);
		220	if (tmp) {
		221	kfree(mcg);
		222	mcg = tmp;
84	goto out;	223	goto out;
85	}	224	}
86		225
87	elem = rxe_alloc_locked(&rxe->mc_elem_pool);	226	if (atomic_inc_return(&rxe->mcg_num) > rxe->attr.max_mcast_grp) {
88	if (!elem) {
89	err = -ENOMEM;	227	err = -ENOMEM;
90	goto out;	228	goto err_dec;
		229	}
		230
		231	err = __rxe_init_mcg(rxe, mgid, mcg);
		232	if (err)
		233	goto err_dec;
		234	out:
		235	spin_unlock_irqrestore(&rxe->mcg_lock, flags);
		236	return mcg;
		237
		238	err_dec:
		239	atomic_dec(&rxe->mcg_num);
		240	spin_unlock_irqrestore(&rxe->mcg_lock, flags);
		241	kfree(mcg);
		242	return ERR_PTR(err);
		243	}
		244
		245	/**
		246	* rxe_cleanup_mcg - cleanup mcg for kref_put
		247	* @kref: struct kref embnedded in mcg
		248	*/
		249	void rxe_cleanup_mcg(struct kref *kref)
		250	{
		251	struct rxe_mcg mcg = container_of(kref, typeof(mcg), ref_cnt);
		252
		253	kfree(mcg);
		254	}
		255
		256	/**
		257	* __rxe_destroy_mcg - destroy mcg object holding rxe->mcg_lock
		258	* @mcg: the mcg object
		259	*
		260	* Context: caller is holding rxe->mcg_lock
		261	* no qp's are attached to mcg
		262	*/
		263	static void __rxe_destroy_mcg(struct rxe_mcg *mcg)
		264	{
		265	struct rxe_dev *rxe = mcg->rxe;
		266
		267	/* remove mcg from red-black tree then drop ref */
		268	__rxe_remove_mcg(mcg);
		269	kref_put(&mcg->ref_cnt, rxe_cleanup_mcg);
		270
		271	rxe_mcast_delete(mcg->rxe, &mcg->mgid);
		272	atomic_dec(&rxe->mcg_num);
		273	}
		274
		275	/**
		276	* rxe_destroy_mcg - destroy mcg object
		277	* @mcg: the mcg object
		278	*
		279	* Context: no qp's are attached to mcg
		280	*/
		281	static void rxe_destroy_mcg(struct rxe_mcg *mcg)
		282	{
		283	unsigned long flags;
		284
		285	spin_lock_irqsave(&mcg->rxe->mcg_lock, flags);
		286	__rxe_destroy_mcg(mcg);
		287	spin_unlock_irqrestore(&mcg->rxe->mcg_lock, flags);
		288	}
		289
		290	/**
		291	* __rxe_init_mca - initialize a new mca holding lock
		292	* @qp: qp object
		293	* @mcg: mcg object
		294	* @mca: empty space for new mca
		295	*
		296	* Context: caller must hold references on qp and mcg, rxe->mcg_lock
		297	* and pass memory for new mca
		298	*
		299	* Returns: 0 on success else an error
		300	*/
		301	static int __rxe_init_mca(struct rxe_qp qp, struct rxe_mcg mcg,
		302	struct rxe_mca *mca)
		303	{
		304	struct rxe_dev *rxe = to_rdev(qp->ibqp.device);
		305	int n;
		306
		307	n = atomic_inc_return(&rxe->mcg_attach);
		308	if (n > rxe->attr.max_total_mcast_qp_attach) {
		309	atomic_dec(&rxe->mcg_attach);
		310	return -ENOMEM;
91	}	311	}
92		312
93	/* each qp holds a ref on the grp */	313	n = atomic_inc_return(&mcg->qp_num);
94	rxe_add_ref(grp);	314	if (n > rxe->attr.max_mcast_qp_attach) {
		315	atomic_dec(&mcg->qp_num);
		316	atomic_dec(&rxe->mcg_attach);
		317	return -ENOMEM;
		318	}
		319
		320	atomic_inc(&qp->mcg_num);
95		321
96	grp->num_qp++;	322	rxe_get(qp);
97	elem->qp = qp;	323	mca->qp = qp;
98	elem->grp = grp;
99		324
100	list_add(&elem->qp_list, &grp->qp_list);	325	list_add_tail(&mca->qp_list, &mcg->qp_list);
101	list_add(&elem->grp_list, &qp->grp_list);
102		326
103	err = 0;	327	return 0;
		328	}
		329
		330	/**
		331	* rxe_attach_mcg - attach qp to mcg if not already attached
		332	* @qp: qp object
		333	* @mcg: mcg object
		334	*
		335	* Context: caller must hold reference on qp and mcg.
		336	* Returns: 0 on success else an error
		337	*/
		338	static int rxe_attach_mcg(struct rxe_mcg mcg, struct rxe_qp qp)
		339	{
		340	struct rxe_dev *rxe = mcg->rxe;
		341	struct rxe_mca mca, tmp;
		342	unsigned long flags;
		343	int err;
		344
		345	/* check to see if the qp is already a member of the group */
		346	spin_lock_irqsave(&rxe->mcg_lock, flags);
		347	list_for_each_entry(mca, &mcg->qp_list, qp_list) {
		348	if (mca->qp == qp) {
		349	spin_unlock_irqrestore(&rxe->mcg_lock, flags);
		350	return 0;
		351	}
		352	}
		353	spin_unlock_irqrestore(&rxe->mcg_lock, flags);
		354
		355	/* speculative alloc new mca without using GFP_ATOMIC */
		356	mca = kzalloc(sizeof(*mca), GFP_KERNEL);
		357	if (!mca)
		358	return -ENOMEM;
		359
		360	spin_lock_irqsave(&rxe->mcg_lock, flags);
		361	/* re-check to see if someone else just attached qp */
		362	list_for_each_entry(tmp, &mcg->qp_list, qp_list) {
		363	if (tmp->qp == qp) {
		364	kfree(mca);
		365	err = 0;
		366	goto out;
		367	}
		368	}
		369
		370	err = __rxe_init_mca(qp, mcg, mca);
		371	if (err)
		372	kfree(mca);
104	out:	373	out:
105	spin_unlock_bh(&grp->mcg_lock);	374	spin_unlock_irqrestore(&rxe->mcg_lock, flags);
106	spin_unlock_bh(&qp->grp_lock);
107	return err;	375	return err;
108	}	376	}
109		377
110	int rxe_mcast_drop_grp_elem(struct rxe_dev rxe, struct rxe_qp qp,	378	/**
111	union ib_gid *mgid)	379	* __rxe_cleanup_mca - cleanup mca object holding lock
		380	* @mca: mca object
		381	* @mcg: mcg object
		382	*
		383	* Context: caller must hold a reference to mcg and rxe->mcg_lock
		384	*/
		385	static void __rxe_cleanup_mca(struct rxe_mca mca, struct rxe_mcg mcg)
112	{	386	{
113	struct rxe_mc_grp *grp;	387	list_del(&mca->qp_list);
114	struct rxe_mc_elem elem, tmp;
115		388
116	grp = rxe_pool_get_key(&rxe->mc_grp_pool, mgid);	389	atomic_dec(&mcg->qp_num);
117	if (!grp)	390	atomic_dec(&mcg->rxe->mcg_attach);
118	goto err1;	391	atomic_dec(&mca->qp->mcg_num);
		392	rxe_put(mca->qp);
119		393
120	spin_lock_bh(&qp->grp_lock);	394	kfree(mca);
121	spin_lock_bh(&grp->mcg_lock);	395	}
122		396
123	list_for_each_entry_safe(elem, tmp, &grp->qp_list, qp_list) {	397	/**
124	if (elem->qp == qp) {	398	* rxe_detach_mcg - detach qp from mcg
125	list_del(&elem->qp_list);	399	* @mcg: mcg object
126	list_del(&elem->grp_list);	400	* @qp: qp object
127	grp->num_qp--;	401	*
		402	* Returns: 0 on success else an error if qp is not attached.
		403	*/
		404	static int rxe_detach_mcg(struct rxe_mcg mcg, struct rxe_qp qp)
		405	{
		406	struct rxe_dev *rxe = mcg->rxe;
		407	struct rxe_mca mca, tmp;
		408	unsigned long flags;
128		409
129	spin_unlock_bh(&grp->mcg_lock);	410	spin_lock_irqsave(&rxe->mcg_lock, flags);
130	spin_unlock_bh(&qp->grp_lock);	411	list_for_each_entry_safe(mca, tmp, &mcg->qp_list, qp_list) {
131	rxe_drop_ref(elem);	412	if (mca->qp == qp) {
132	rxe_drop_ref(grp); /* ref held by QP */	413	__rxe_cleanup_mca(mca, mcg);
133	rxe_drop_ref(grp); /* ref from get_key */	414
		415	/* if the number of qp's attached to the
		416	* mcast group falls to zero go ahead and
		417	* tear it down. This will not free the
		418	* object since we are still holding a ref
		419	* from the caller
		420	*/
		421	if (atomic_read(&mcg->qp_num) <= 0)
		422	__rxe_destroy_mcg(mcg);
		423
		424	spin_unlock_irqrestore(&rxe->mcg_lock, flags);
134	return 0;	425	return 0;
135	}	426	}
136	}	427	}
137		428
138	spin_unlock_bh(&grp->mcg_lock);	429	/* we didn't find the qp on the list */
139	spin_unlock_bh(&qp->grp_lock);	430	spin_unlock_irqrestore(&rxe->mcg_lock, flags);
140	rxe_drop_ref(grp); /* ref from get_key */
141	err1:
142	return -EINVAL;	431	return -EINVAL;
143	}	432	}
144		433
145	void rxe_drop_all_mcast_groups(struct rxe_qp *qp)	434	/**
		435	* rxe_attach_mcast - attach qp to multicast group (see IBA-11.3.1)
		436	* @ibqp: (IB) qp object
		437	* @mgid: multicast IP address
		438	* @mlid: multicast LID, ignored for RoCEv2 (see IBA-A17.5.6)
		439	*
		440	* Returns: 0 on success else an errno
		441	*/
		442	int rxe_attach_mcast(struct ib_qp ibqp, union ib_gid mgid, u16 mlid)
146	{	443	{
147	struct rxe_mc_grp *grp;	444	int err;
148	struct rxe_mc_elem *elem;	445	struct rxe_dev *rxe = to_rdev(ibqp->device);
		446	struct rxe_qp *qp = to_rqp(ibqp);
		447	struct rxe_mcg *mcg;
149		448
150	while (1) {	449	/* takes a ref on mcg if successful */
151	spin_lock_bh(&qp->grp_lock);	450	mcg = rxe_get_mcg(rxe, mgid);
152	if (list_empty(&qp->grp_list)) {	451	if (IS_ERR(mcg))
153	spin_unlock_bh(&qp->grp_lock);	452	return PTR_ERR(mcg);
154	break;	453
155	}	454	err = rxe_attach_mcg(mcg, qp);
156	elem = list_first_entry(&qp->grp_list, struct rxe_mc_elem,	455
157	grp_list);	456	/* if we failed to attach the first qp to mcg tear it down */
158	list_del(&elem->grp_list);	457	if (atomic_read(&mcg->qp_num) == 0)
159	spin_unlock_bh(&qp->grp_lock);	458	rxe_destroy_mcg(mcg);
160		459
161	grp = elem->grp;	460	kref_put(&mcg->ref_cnt, rxe_cleanup_mcg);
162	spin_lock_bh(&grp->mcg_lock);	461
163	list_del(&elem->qp_list);	462	return err;
164	grp->num_qp--;
165	spin_unlock_bh(&grp->mcg_lock);
166	rxe_drop_ref(grp);
167	rxe_drop_ref(elem);
168	}
169	}	463	}
170		464
171	void rxe_mc_cleanup(struct rxe_pool_elem *elem)	465	/**
		466	* rxe_detach_mcast - detach qp from multicast group (see IBA-11.3.2)
		467	* @ibqp: address of (IB) qp object
		468	* @mgid: multicast IP address
		469	* @mlid: multicast LID, ignored for RoCEv2 (see IBA-A17.5.6)
		470	*
		471	* Returns: 0 on success else an errno
		472	*/
		473	int rxe_detach_mcast(struct ib_qp ibqp, union ib_gid mgid, u16 mlid)
172	{	474	{
173	struct rxe_mc_grp grp = container_of(elem, typeof(grp), elem);	475	struct rxe_dev *rxe = to_rdev(ibqp->device);
174	struct rxe_dev *rxe = grp->rxe;	476	struct rxe_qp *qp = to_rqp(ibqp);
		477	struct rxe_mcg *mcg;
		478	int err;
175		479
176	rxe_drop_key(grp);	480	mcg = rxe_lookup_mcg(rxe, mgid);
177	rxe_mcast_delete(rxe, &grp->mgid);	481	if (!mcg)
		482	return -EINVAL;
		483
		484	err = rxe_detach_mcg(mcg, qp);
		485	kref_put(&mcg->ref_cnt, rxe_cleanup_mcg);
		486
		487	return err;
178	}	488	}

drivers/infiniband/sw/rxe/rxe_mmap.c+0−1

@@ -4,7 +4,6 @@ · 3 unmodified lines
4	* Copyright (c) 2015 System Fabric Works, Inc. All rights reserved.	4	* Copyright (c) 2015 System Fabric Works, Inc. All rights reserved.
5	*/	5	*/
6		6
7	#include <linux/module.h>
8	#include <linux/vmalloc.h>	7	#include <linux/vmalloc.h>
9	#include <linux/mm.h>	8	#include <linux/mm.h>
10	#include <linux/errno.h>	9	#include <linux/errno.h>

drivers/infiniband/sw/rxe/rxe_mr.c+7−8

 		if (offset >= sge->length) {
 			if (mr) {
-				rxe_drop_ref(mr);
+				rxe_put(mr);
 				mr = NULL;
 			}
 			sge++;
 	dma->resid	= resid;
 	if (mr)
-		rxe_drop_ref(mr);
+		rxe_put(mr);
 	return 0;
 err2:
 	if (mr)
-		rxe_drop_ref(mr);
+		rxe_put(mr);
 err1:
 	return err;
 }
 		     (type == RXE_LOOKUP_REMOTE && mr->rkey != key) ||
 		     mr_pd(mr) != pd || (access && !(access & mr->access)) ||
 		     mr->state != RXE_MR_STATE_VALID)) {
-		rxe_drop_ref(mr);
+		rxe_put(mr);
 		mr = NULL;
 	}
 	ret = 0;
 err_drop_ref:
-	rxe_drop_ref(mr);
+	rxe_put(mr);
 err:
 	return ret;
 }
 	}
 	mr->state = RXE_MR_STATE_INVALID;
-	rxe_drop_ref(mr_pd(mr));
+	rxe_put(mr_pd(mr));
-	rxe_drop_index(mr);
+	rxe_put(mr);
-	rxe_drop_ref(mr);
 	return 0;
 }

drivers/infiniband/sw/rxe/rxe_mw.c+15−23

 	struct rxe_dev *rxe = to_rdev(ibmw->device);
 	int ret;
-	rxe_add_ref(pd);
+	rxe_get(pd);
 	ret = rxe_add_to_pool(&rxe->mw_pool, mw);
 	if (ret) {
-		rxe_drop_ref(pd);
+		rxe_put(pd);
 		return ret;
 	}
-	rxe_add_index(mw);
 	mw->rkey = ibmw->rkey = (mw->elem.index << 8) | rxe_get_next_key(-1);
 	mw->state = (mw->ibmw.type == IB_MW_TYPE_2) ?
 			RXE_MW_STATE_FREE : RXE_MW_STATE_VALID;
 		mw->mr = NULL;
 		atomic_dec(&mr->num_mw);
-		rxe_drop_ref(mr);
+		rxe_put(mr);
 	}
 	if (mw->qp) {
 		struct rxe_qp *qp = mw->qp;
 		mw->qp = NULL;
-		rxe_drop_ref(qp);
+		rxe_put(qp);
 	}
 	mw->access = 0;
 	rxe_do_dealloc_mw(mw);
 	spin_unlock_bh(&mw->lock);
-	rxe_drop_ref(mw);
+	rxe_put(mw);
-	rxe_drop_ref(pd);
+	rxe_put(pd);
 	return 0;
 }
 	mw->length = wqe->wr.wr.mw.length;
 	if (mw->mr) {
-		rxe_drop_ref(mw->mr);
+		rxe_put(mw->mr);
 		atomic_dec(&mw->mr->num_mw);
 		mw->mr = NULL;
 	}
 	if (mw->length) {
 		mw->mr = mr;
 		atomic_inc(&mr->num_mw);
-		rxe_add_ref(mr);
+		rxe_get(mr);
 	}
 	if (mw->ibmw.type == IB_MW_TYPE_2) {
-		rxe_add_ref(qp);
+		rxe_get(qp);
 		mw->qp = qp;
 	}
 }
 	spin_unlock_bh(&mw->lock);
 err_drop_mr:
 	if (mr)
-		rxe_drop_ref(mr);
+		rxe_put(mr);
 err_drop_mw:
-	rxe_drop_ref(mw);
+	rxe_put(mw);
 err:
 	return ret;
 }
 	/* valid type 2 MW will always have a QP pointer */
 	qp = mw->qp;
 	mw->qp = NULL;
-	rxe_drop_ref(qp);
+	rxe_put(qp);
 	/* valid type 2 MW will always have an MR pointer */
 	mr = mw->mr;
 	mw->mr = NULL;
 	atomic_dec(&mr->num_mw);
-	rxe_drop_ref(mr);
+	rxe_put(mr);
 	mw->access = 0;
 	mw->addr = 0;
 err_unlock:
 	spin_unlock_bh(&mw->lock);
 err_drop_ref:
-	rxe_drop_ref(mw);
+	rxe_put(mw);
 err:
 	return ret;
 }
 		     (mw->length == 0) ||
 		     (access && !(access & mw->access)) ||
 		     mw->state != RXE_MW_STATE_VALID)) {
-		rxe_drop_ref(mw);
+		rxe_put(mw);
 		return NULL;
 	}
 	return mw;
 }
-void rxe_mw_cleanup(struct rxe_pool_elem *elem)
-{
-	struct rxe_mw *mw = container_of(elem, typeof(*mw), elem);
-	rxe_drop_index(mw);
-}

drivers/infiniband/sw/rxe/rxe_net.c+12−29

 static struct rxe_recv_sockets recv_sockets;
-int rxe_mcast_add(struct rxe_dev *rxe, union ib_gid *mgid)
-{
-	unsigned char ll_addr[ETH_ALEN];
-	ipv6_eth_mc_map((struct in6_addr *)mgid->raw, ll_addr);
-	return dev_mc_add(rxe->ndev, ll_addr);
-}
-int rxe_mcast_delete(struct rxe_dev *rxe, union ib_gid *mgid)
-{
-	unsigned char ll_addr[ETH_ALEN];
-	ipv6_eth_mc_map((struct in6_addr *)mgid->raw, ll_addr);
-	return dev_mc_del(rxe->ndev, ll_addr);
-}
 static struct dst_entry *rxe_find_route4(struct net_device *ndev,
 				  struct in_addr *saddr,
 				  struct in_addr *daddr)
 	ip6h->payload_len = htons(skb->len - sizeof(*ip6h));
 }
-static int prepare4(struct rxe_pkt_info *pkt, struct sk_buff *skb)
+static int prepare4(struct rxe_av *av, struct rxe_pkt_info *pkt,
+		    struct sk_buff *skb)
 {
 	struct rxe_qp *qp = pkt->qp;
 	struct dst_entry *dst;
 	bool xnet = false;
 	__be16 df = htons(IP_DF);
-	struct rxe_av *av = rxe_get_av(pkt);
 	struct in_addr *saddr = &av->sgid_addr._sockaddr_in.sin_addr;
 	struct in_addr *daddr = &av->dgid_addr._sockaddr_in.sin_addr;
 	return 0;
 }
-static int prepare6(struct rxe_pkt_info *pkt, struct sk_buff *skb)
+static int prepare6(struct rxe_av *av, struct rxe_pkt_info *pkt,
+		    struct sk_buff *skb)
 {
 	struct rxe_qp *qp = pkt->qp;
 	struct dst_entry *dst;
-	struct rxe_av *av = rxe_get_av(pkt);
 	struct in6_addr *saddr = &av->sgid_addr._sockaddr_in6.sin6_addr;
 	struct in6_addr *daddr = &av->dgid_addr._sockaddr_in6.sin6_addr;
 	return 0;
 }
-int rxe_prepare(struct rxe_pkt_info *pkt, struct sk_buff *skb)
+int rxe_prepare(struct rxe_av *av, struct rxe_pkt_info *pkt,
+		struct sk_buff *skb)
 {
 	int err = 0;
 	if (skb->protocol == htons(ETH_P_IP))
-		err = prepare4(pkt, skb);
+		err = prepare4(av, pkt, skb);
 	else if (skb->protocol == htons(ETH_P_IPV6))
-		err = prepare6(pkt, skb);
+		err = prepare6(av, pkt, skb);
-	if (ether_addr_equal(skb->dev->dev_addr, rxe_get_av(pkt)->dmac))
+	if (ether_addr_equal(skb->dev->dev_addr, av->dmac))
 		pkt->mask |= RXE_LOOPBACK_MASK;
 	return err;
 		     skb_out < RXE_INFLIGHT_SKBS_PER_QP_LOW))
 		rxe_run_task(&qp->req.task, 1);
-	rxe_drop_ref(qp);
+	rxe_put(qp);
 }
 static int rxe_send(struct sk_buff *skb, struct rxe_pkt_info *pkt)
 	skb->destructor = rxe_skb_tx_dtor;
 	skb->sk = pkt->qp->sk->sk;
-	rxe_add_ref(pkt->qp);
+	rxe_get(pkt->qp);
 	atomic_inc(&pkt->qp->skb_out);
 	if (skb->protocol == htons(ETH_P_IP)) {
 	} else {
 		pr_err("Unknown layer 3 protocol: %d\n", skb->protocol);
 		atomic_dec(&pkt->qp->skb_out);
-		rxe_drop_ref(pkt->qp);
+		rxe_put(pkt->qp);
 		kfree_skb(skb);
 		return -EINVAL;
 	}

drivers/infiniband/sw/rxe/rxe_pool.c+81−352

@@ -12,129 +12,93 @@ static const struct rxe_type_info { · 11 unmodified lines
12	const char *name;	12	const char *name;
13	size_t size;	13	size_t size;
14	size_t elem_offset;	14	size_t elem_offset;
15	void (cleanup)(struct rxe_pool_elem obj);	15	void (cleanup)(struct rxe_pool_elem elem);
16	enum rxe_pool_flags flags;	16	enum rxe_pool_flags flags;
17	u32 min_index;	17	u32 min_index;
18	u32 max_index;	18	u32 max_index;
19	size_t key_offset;	19	u32 max_elem;
20	size_t key_size;
21	} rxe_type_info[RXE_NUM_TYPES] = {	20	} rxe_type_info[RXE_NUM_TYPES] = {
22	[RXE_TYPE_UC] = {	21	[RXE_TYPE_UC] = {
23	.name = "rxe-uc",	22	.name = "uc",
24	.size = sizeof(struct rxe_ucontext),	23	.size = sizeof(struct rxe_ucontext),
25	.elem_offset = offsetof(struct rxe_ucontext, elem),	24	.elem_offset = offsetof(struct rxe_ucontext, elem),
26	.flags = RXE_POOL_NO_ALLOC,	25	.min_index = 1,
		26	.max_index = UINT_MAX,
		27	.max_elem = UINT_MAX,
27	},	28	},
28	[RXE_TYPE_PD] = {	29	[RXE_TYPE_PD] = {
29	.name = "rxe-pd",	30	.name = "pd",
30	.size = sizeof(struct rxe_pd),	31	.size = sizeof(struct rxe_pd),
31	.elem_offset = offsetof(struct rxe_pd, elem),	32	.elem_offset = offsetof(struct rxe_pd, elem),
32	.flags = RXE_POOL_NO_ALLOC,	33	.min_index = 1,
		34	.max_index = UINT_MAX,
		35	.max_elem = UINT_MAX,
33	},	36	},
34	[RXE_TYPE_AH] = {	37	[RXE_TYPE_AH] = {
35	.name = "rxe-ah",	38	.name = "ah",
36	.size = sizeof(struct rxe_ah),	39	.size = sizeof(struct rxe_ah),
37	.elem_offset = offsetof(struct rxe_ah, elem),	40	.elem_offset = offsetof(struct rxe_ah, elem),
38	.flags = RXE_POOL_INDEX \| RXE_POOL_NO_ALLOC,
39	.min_index = RXE_MIN_AH_INDEX,	41	.min_index = RXE_MIN_AH_INDEX,
40	.max_index = RXE_MAX_AH_INDEX,	42	.max_index = RXE_MAX_AH_INDEX,
		43	.max_elem = RXE_MAX_AH_INDEX - RXE_MIN_AH_INDEX + 1,
41	},	44	},
42	[RXE_TYPE_SRQ] = {	45	[RXE_TYPE_SRQ] = {
43	.name = "rxe-srq",	46	.name = "srq",
44	.size = sizeof(struct rxe_srq),	47	.size = sizeof(struct rxe_srq),
45	.elem_offset = offsetof(struct rxe_srq, elem),	48	.elem_offset = offsetof(struct rxe_srq, elem),
46	.flags = RXE_POOL_INDEX \| RXE_POOL_NO_ALLOC,
47	.min_index = RXE_MIN_SRQ_INDEX,	49	.min_index = RXE_MIN_SRQ_INDEX,
48	.max_index = RXE_MAX_SRQ_INDEX,	50	.max_index = RXE_MAX_SRQ_INDEX,
		51	.max_elem = RXE_MAX_SRQ_INDEX - RXE_MIN_SRQ_INDEX + 1,
49	},	52	},
50	[RXE_TYPE_QP] = {	53	[RXE_TYPE_QP] = {
51	.name = "rxe-qp",	54	.name = "qp",
52	.size = sizeof(struct rxe_qp),	55	.size = sizeof(struct rxe_qp),
53	.elem_offset = offsetof(struct rxe_qp, elem),	56	.elem_offset = offsetof(struct rxe_qp, elem),
54	.cleanup = rxe_qp_cleanup,	57	.cleanup = rxe_qp_cleanup,
55	.flags = RXE_POOL_INDEX \| RXE_POOL_NO_ALLOC,
56	.min_index = RXE_MIN_QP_INDEX,	58	.min_index = RXE_MIN_QP_INDEX,
57	.max_index = RXE_MAX_QP_INDEX,	59	.max_index = RXE_MAX_QP_INDEX,
		60	.max_elem = RXE_MAX_QP_INDEX - RXE_MIN_QP_INDEX + 1,
58	},	61	},
59	[RXE_TYPE_CQ] = {	62	[RXE_TYPE_CQ] = {
60	.name = "rxe-cq",	63	.name = "cq",
61	.size = sizeof(struct rxe_cq),	64	.size = sizeof(struct rxe_cq),
62	.elem_offset = offsetof(struct rxe_cq, elem),	65	.elem_offset = offsetof(struct rxe_cq, elem),
63	.flags = RXE_POOL_NO_ALLOC,
64	.cleanup = rxe_cq_cleanup,	66	.cleanup = rxe_cq_cleanup,
		67	.min_index = 1,
		68	.max_index = UINT_MAX,
		69	.max_elem = UINT_MAX,
65	},	70	},
66	[RXE_TYPE_MR] = {	71	[RXE_TYPE_MR] = {
67	.name = "rxe-mr",	72	.name = "mr",
68	.size = sizeof(struct rxe_mr),	73	.size = sizeof(struct rxe_mr),
69	.elem_offset = offsetof(struct rxe_mr, elem),	74	.elem_offset = offsetof(struct rxe_mr, elem),
70	.cleanup = rxe_mr_cleanup,	75	.cleanup = rxe_mr_cleanup,
71	.flags = RXE_POOL_INDEX,	76	.flags = RXE_POOL_ALLOC,
72	.min_index = RXE_MIN_MR_INDEX,	77	.min_index = RXE_MIN_MR_INDEX,
73	.max_index = RXE_MAX_MR_INDEX,	78	.max_index = RXE_MAX_MR_INDEX,
		79	.max_elem = RXE_MAX_MR_INDEX - RXE_MIN_MR_INDEX + 1,
74	},	80	},
75	[RXE_TYPE_MW] = {	81	[RXE_TYPE_MW] = {
76	.name = "rxe-mw",	82	.name = "mw",
77	.size = sizeof(struct rxe_mw),	83	.size = sizeof(struct rxe_mw),
78	.elem_offset = offsetof(struct rxe_mw, elem),	84	.elem_offset = offsetof(struct rxe_mw, elem),
79	.cleanup = rxe_mw_cleanup,
80	.flags = RXE_POOL_INDEX \| RXE_POOL_NO_ALLOC,
81	.min_index = RXE_MIN_MW_INDEX,	85	.min_index = RXE_MIN_MW_INDEX,
82	.max_index = RXE_MAX_MW_INDEX,	86	.max_index = RXE_MAX_MW_INDEX,
83	},	87	.max_elem = RXE_MAX_MW_INDEX - RXE_MIN_MW_INDEX + 1,
84	[RXE_TYPE_MC_GRP] = {
85	.name = "rxe-mc_grp",
86	.size = sizeof(struct rxe_mc_grp),
87	.elem_offset = offsetof(struct rxe_mc_grp, elem),
88	.cleanup = rxe_mc_cleanup,
89	.flags = RXE_POOL_KEY,
90	.key_offset = offsetof(struct rxe_mc_grp, mgid),
91	.key_size = sizeof(union ib_gid),
92	},
93	[RXE_TYPE_MC_ELEM] = {
94	.name = "rxe-mc_elem",
95	.size = sizeof(struct rxe_mc_elem),
96	.elem_offset = offsetof(struct rxe_mc_elem, elem),
97	},	88	},
98	};	89	};
99		90
100	static int rxe_pool_init_index(struct rxe_pool *pool, u32 max, u32 min)	91	void rxe_pool_init(struct rxe_dev rxe, struct rxe_pool pool,
101	{	92	enum rxe_elem_type type)
102	int err = 0;
103
104	if ((max - min + 1) < pool->max_elem) {
105	pr_warn("not enough indices for max_elem\n");
106	err = -EINVAL;
107	goto out;
108	}
109
110	pool->index.max_index = max;
111	pool->index.min_index = min;
112
113	pool->index.table = bitmap_zalloc(max - min + 1, GFP_KERNEL);
114	if (!pool->index.table) {
115	err = -ENOMEM;
116	goto out;
117	}
118
119	out:
120	return err;
121	}
122
123	int rxe_pool_init(
124	struct rxe_dev *rxe,
125	struct rxe_pool *pool,
126	enum rxe_elem_type type,
127	unsigned int max_elem)
128	{	93	{
129	const struct rxe_type_info *info = &rxe_type_info[type];	94	const struct rxe_type_info *info = &rxe_type_info[type];
130	int err = 0;
131		95
132	memset(pool, 0, sizeof(*pool));	96	memset(pool, 0, sizeof(*pool));
133		97
134	pool->rxe = rxe;	98	pool->rxe = rxe;
135	pool->name = info->name;	99	pool->name = info->name;
136	pool->type = type;	100	pool->type = type;
137	pool->max_elem = max_elem;	101	pool->max_elem = info->max_elem;
138	pool->elem_size = ALIGN(info->size, RXE_POOL_ALIGN);	102	pool->elem_size = ALIGN(info->size, RXE_POOL_ALIGN);
139	pool->elem_offset = info->elem_offset;	103	pool->elem_offset = info->elem_offset;
140	pool->flags = info->flags;	104	pool->flags = info->flags;
@@ -142,225 +106,31 @@ int rxe_pool_init( · 1 unmodified line
142		106
143	atomic_set(&pool->num_elem, 0);	107	atomic_set(&pool->num_elem, 0);
144		108
145	rwlock_init(&pool->pool_lock);	109	xa_init_flags(&pool->xa, XA_FLAGS_ALLOC);
146		110	pool->limit.min = info->min_index;
147	if (pool->flags & RXE_POOL_INDEX) {	111	pool->limit.max = info->max_index;
148	pool->index.tree = RB_ROOT;
149	err = rxe_pool_init_index(pool, info->max_index,
150	info->min_index);
151	if (err)
152	goto out;
153	}
154
155	if (pool->flags & RXE_POOL_KEY) {
156	pool->key.tree = RB_ROOT;
157	pool->key.key_offset = info->key_offset;
158	pool->key.key_size = info->key_size;
159	}
160
161	out:
162	return err;
163	}	112	}
164		113
165	void rxe_pool_cleanup(struct rxe_pool *pool)	114	void rxe_pool_cleanup(struct rxe_pool *pool)
166	{	115	{
167	if (atomic_read(&pool->num_elem) > 0)	116	WARN_ON(!xa_empty(&pool->xa));
168	pr_warn("%s pool destroyed with unfree'd elem\n",
169	pool->name);
170
171	if (pool->flags & RXE_POOL_INDEX)
172	bitmap_free(pool->index.table);
173	}
174
175	static u32 alloc_index(struct rxe_pool *pool)
176	{
177	u32 index;
178	u32 range = pool->index.max_index - pool->index.min_index + 1;
179
180	index = find_next_zero_bit(pool->index.table, range, pool->index.last);
181	if (index >= range)
182	index = find_first_zero_bit(pool->index.table, range);
183
184	WARN_ON_ONCE(index >= range);
185	set_bit(index, pool->index.table);
186	pool->index.last = index;
187	return index + pool->index.min_index;
188	}
189
190	static int rxe_insert_index(struct rxe_pool pool, struct rxe_pool_elem new)
191	{
192	struct rb_node **link = &pool->index.tree.rb_node;
193	struct rb_node *parent = NULL;
194	struct rxe_pool_elem *elem;
195
196	while (*link) {
197	parent = *link;
198	elem = rb_entry(parent, struct rxe_pool_elem, index_node);
199
200	if (elem->index == new->index) {
201	pr_warn("element already exists!\n");
202	return -EINVAL;
203	}
204
205	if (elem->index > new->index)
206	link = &(*link)->rb_left;
207	else
208	link = &(*link)->rb_right;
209	}
210
211	rb_link_node(&new->index_node, parent, link);
212	rb_insert_color(&new->index_node, &pool->index.tree);
213
214	return 0;
215	}
216
217	static int rxe_insert_key(struct rxe_pool pool, struct rxe_pool_elem new)
218	{
219	struct rb_node **link = &pool->key.tree.rb_node;
220	struct rb_node *parent = NULL;
221	struct rxe_pool_elem *elem;
222	int cmp;
223
224	while (*link) {
225	parent = *link;
226	elem = rb_entry(parent, struct rxe_pool_elem, key_node);
227
228	cmp = memcmp((u8 *)elem + pool->key.key_offset,
229	(u8 *)new + pool->key.key_offset,
230	pool->key.key_size);
231
232	if (cmp == 0) {
233	pr_warn("key already exists!\n");
234	return -EINVAL;
235	}
236
237	if (cmp > 0)
238	link = &(*link)->rb_left;
239	else
240	link = &(*link)->rb_right;
241	}
242
243	rb_link_node(&new->key_node, parent, link);
244	rb_insert_color(&new->key_node, &pool->key.tree);
245
246	return 0;
247	}
248
249	int __rxe_add_key_locked(struct rxe_pool_elem elem, void key)
250	{
251	struct rxe_pool *pool = elem->pool;
252	int err;
253
254	memcpy((u8 *)elem + pool->key.key_offset, key, pool->key.key_size);
255	err = rxe_insert_key(pool, elem);
256
257	return err;
258	}
259
260	int __rxe_add_key(struct rxe_pool_elem elem, void key)
261	{
262	struct rxe_pool *pool = elem->pool;
263	int err;
264
265	write_lock_bh(&pool->pool_lock);
266	err = __rxe_add_key_locked(elem, key);
267	write_unlock_bh(&pool->pool_lock);
268
269	return err;
270	}
271
272	void __rxe_drop_key_locked(struct rxe_pool_elem *elem)
273	{
274	struct rxe_pool *pool = elem->pool;
275
276	rb_erase(&elem->key_node, &pool->key.tree);
277	}
278
279	void __rxe_drop_key(struct rxe_pool_elem *elem)
280	{
281	struct rxe_pool *pool = elem->pool;
282
283	write_lock_bh(&pool->pool_lock);
284	__rxe_drop_key_locked(elem);
285	write_unlock_bh(&pool->pool_lock);
286	}
287
288	int __rxe_add_index_locked(struct rxe_pool_elem *elem)
289	{
290	struct rxe_pool *pool = elem->pool;
291	int err;
292
293	elem->index = alloc_index(pool);
294	err = rxe_insert_index(pool, elem);
295
296	return err;
297	}
298
299	int __rxe_add_index(struct rxe_pool_elem *elem)
300	{
301	struct rxe_pool *pool = elem->pool;
302	int err;
303
304	write_lock_bh(&pool->pool_lock);
305	err = __rxe_add_index_locked(elem);
306	write_unlock_bh(&pool->pool_lock);
307
308	return err;
309	}
310
311	void __rxe_drop_index_locked(struct rxe_pool_elem *elem)
312	{
313	struct rxe_pool *pool = elem->pool;
314
315	clear_bit(elem->index - pool->index.min_index, pool->index.table);
316	rb_erase(&elem->index_node, &pool->index.tree);
317	}
318
319	void __rxe_drop_index(struct rxe_pool_elem *elem)
320	{
321	struct rxe_pool *pool = elem->pool;
322
323	write_lock_bh(&pool->pool_lock);
324	__rxe_drop_index_locked(elem);
325	write_unlock_bh(&pool->pool_lock);
326	}
327
328	void rxe_alloc_locked(struct rxe_pool pool)
329	{
330	struct rxe_pool_elem *elem;
331	void *obj;
332
333	if (atomic_inc_return(&pool->num_elem) > pool->max_elem)
334	goto out_cnt;
335
336	obj = kzalloc(pool->elem_size, GFP_ATOMIC);
337	if (!obj)
338	goto out_cnt;
339
340	elem = (struct rxe_pool_elem )((u8 )obj + pool->elem_offset);
341
342	elem->pool = pool;
343	elem->obj = obj;
344	kref_init(&elem->ref_cnt);
345
346	return obj;
347
348	out_cnt:
349	atomic_dec(&pool->num_elem);
350	return NULL;
351	}	117	}
352		118
353	void rxe_alloc(struct rxe_pool pool)	119	void rxe_alloc(struct rxe_pool pool)
354	{	120	{
355	struct rxe_pool_elem *elem;	121	struct rxe_pool_elem *elem;
356	void *obj;	122	void *obj;
		123	int err;
		124
		125	if (WARN_ON(!(pool->flags & RXE_POOL_ALLOC)))
		126	return NULL;
357		127
358	if (atomic_inc_return(&pool->num_elem) > pool->max_elem)	128	if (atomic_inc_return(&pool->num_elem) > pool->max_elem)
359	goto out_cnt;	129	goto err_cnt;
360		130
361	obj = kzalloc(pool->elem_size, GFP_KERNEL);	131	obj = kzalloc(pool->elem_size, GFP_KERNEL);
362	if (!obj)	132	if (!obj)
363	goto out_cnt;	133	goto err_cnt;
364		134
365	elem = (struct rxe_pool_elem )((u8 )obj + pool->elem_offset);	135	elem = (struct rxe_pool_elem )((u8 )obj + pool->elem_offset);
366		136
@@ -368,127 +138,86 @@ void rxe_alloc(struct rxe_pool pool) · 1 unmodified line
368	elem->obj = obj;	138	elem->obj = obj;
369	kref_init(&elem->ref_cnt);	139	kref_init(&elem->ref_cnt);
370		140
		141	err = xa_alloc_cyclic(&pool->xa, &elem->index, elem, pool->limit,
		142	&pool->next, GFP_KERNEL);
		143	if (err)
		144	goto err_free;
		145
371	return obj;	146	return obj;
372		147
373	out_cnt:	148	err_free:
		149	kfree(obj);
		150	err_cnt:
374	atomic_dec(&pool->num_elem);	151	atomic_dec(&pool->num_elem);
375	return NULL;	152	return NULL;
376	}	153	}
377		154
378	int __rxe_add_to_pool(struct rxe_pool pool, struct rxe_pool_elem elem)	155	int __rxe_add_to_pool(struct rxe_pool pool, struct rxe_pool_elem elem)
379	{	156	{
		157	int err;
		158
		159	if (WARN_ON(pool->flags & RXE_POOL_ALLOC))
		160	return -EINVAL;
		161
380	if (atomic_inc_return(&pool->num_elem) > pool->max_elem)	162	if (atomic_inc_return(&pool->num_elem) > pool->max_elem)
381	goto out_cnt;	163	goto err_cnt;
382		164
383	elem->pool = pool;	165	elem->pool = pool;
384	elem->obj = (u8 *)elem - pool->elem_offset;	166	elem->obj = (u8 *)elem - pool->elem_offset;
385	kref_init(&elem->ref_cnt);	167	kref_init(&elem->ref_cnt);
386		168
		169	err = xa_alloc_cyclic(&pool->xa, &elem->index, elem, pool->limit,
		170	&pool->next, GFP_KERNEL);
		171	if (err)
		172	goto err_cnt;
		173
387	return 0;	174	return 0;
388		175
389	out_cnt:	176	err_cnt:
390	atomic_dec(&pool->num_elem);	177	atomic_dec(&pool->num_elem);
391	return -EINVAL;	178	return -EINVAL;
392	}	179	}
393		180
394	void rxe_elem_release(struct kref *kref)	181	void rxe_pool_get_index(struct rxe_pool pool, u32 index)
395	{
396	struct rxe_pool_elem *elem =
397	container_of(kref, struct rxe_pool_elem, ref_cnt);
398	struct rxe_pool *pool = elem->pool;
399	void *obj;
400
401	if (pool->cleanup)
402	pool->cleanup(elem);
403
404	if (!(pool->flags & RXE_POOL_NO_ALLOC)) {
405	obj = elem->obj;
406	kfree(obj);
407	}
408
409	atomic_dec(&pool->num_elem);
410	}
411
412	void rxe_pool_get_index_locked(struct rxe_pool pool, u32 index)
413	{	182	{
414	struct rb_node *node;
415	struct rxe_pool_elem *elem;	183	struct rxe_pool_elem *elem;
		184	struct xarray *xa = &pool->xa;
		185	unsigned long flags;
416	void *obj;	186	void *obj;
417		187
418	node = pool->index.tree.rb_node;	188	xa_lock_irqsave(xa, flags);
419		189	elem = xa_load(xa, index);
420	while (node) {	190	if (elem && kref_get_unless_zero(&elem->ref_cnt))
421	elem = rb_entry(node, struct rxe_pool_elem, index_node);
422
423	if (elem->index > index)
424	node = node->rb_left;
425	else if (elem->index < index)
426	node = node->rb_right;
427	else
428	break;
429	}
430
431	if (node) {
432	kref_get(&elem->ref_cnt);
433	obj = elem->obj;	191	obj = elem->obj;
434	} else {	192	else
435	obj = NULL;	193	obj = NULL;
436	}	194	xa_unlock_irqrestore(xa, flags);
437
438	return obj;
439	}
440
441	void rxe_pool_get_index(struct rxe_pool pool, u32 index)
442	{
443	void *obj;
444
445	read_lock_bh(&pool->pool_lock);
446	obj = rxe_pool_get_index_locked(pool, index);
447	read_unlock_bh(&pool->pool_lock);
448		195
449	return obj;	196	return obj;
450	}	197	}
451		198
452	void rxe_pool_get_key_locked(struct rxe_pool pool, void *key)	199	static void rxe_elem_release(struct kref *kref)
453	{	200	{
454	struct rb_node *node;	201	struct rxe_pool_elem elem = container_of(kref, typeof(elem), ref_cnt);
455	struct rxe_pool_elem *elem;	202	struct rxe_pool *pool = elem->pool;
456	void *obj;
457	int cmp;
458
459	node = pool->key.tree.rb_node;
460		203
461	while (node) {	204	xa_erase(&pool->xa, elem->index);
462	elem = rb_entry(node, struct rxe_pool_elem, key_node);
463		205
464	cmp = memcmp((u8 *)elem + pool->key.key_offset,	206	if (pool->cleanup)
465	key, pool->key.key_size);	207	pool->cleanup(elem);
466		208
467	if (cmp > 0)	209	if (pool->flags & RXE_POOL_ALLOC)
468	node = node->rb_left;	210	kfree(elem->obj);
469	else if (cmp < 0)
470	node = node->rb_right;
471	else
472	break;
473	}
474		211
475	if (node) {	212	atomic_dec(&pool->num_elem);
476	kref_get(&elem->ref_cnt);
477	obj = elem->obj;
478	} else {
479	obj = NULL;
480	}
481
482	return obj;
483	}	213	}
484		214
485	void rxe_pool_get_key(struct rxe_pool pool, void *key)	215	int __rxe_get(struct rxe_pool_elem *elem)
486	{	216	{
487	void *obj;	217	return kref_get_unless_zero(&elem->ref_cnt);
488		218	}
489	read_lock_bh(&pool->pool_lock);
490	obj = rxe_pool_get_key_locked(pool, key);
491	read_unlock_bh(&pool->pool_lock);
492		219
493	return obj;	220	int __rxe_put(struct rxe_pool_elem *elem)
		221	{
		222	return kref_put(&elem->ref_cnt, rxe_elem_release);
494	}	223	}

drivers/infiniband/sw/rxe/rxe_pool.h+14−91

@@ -8,9 +8,7 @@ · 7 unmodified lines
8	#define RXE_POOL_H	8	#define RXE_POOL_H
9		9
10	enum rxe_pool_flags {	10	enum rxe_pool_flags {
11	RXE_POOL_INDEX = BIT(1),	11	RXE_POOL_ALLOC = BIT(1),
12	RXE_POOL_KEY = BIT(2),
13	RXE_POOL_NO_ALLOC = BIT(4),
14	};	12	};
15		13
16	enum rxe_elem_type {	14	enum rxe_elem_type {
@@ -22,8 +20,6 @@ enum rxe_elem_type { · 5 unmodified lines
22	RXE_TYPE_CQ,	20	RXE_TYPE_CQ,
23	RXE_TYPE_MR,	21	RXE_TYPE_MR,
24	RXE_TYPE_MW,	22	RXE_TYPE_MW,
25	RXE_TYPE_MC_GRP,
26	RXE_TYPE_MC_ELEM,
27	RXE_NUM_TYPES, /* keep me last */	23	RXE_NUM_TYPES, /* keep me last */
28	};	24	};
29		25
@@ -32,20 +28,13 @@ struct rxe_pool_elem { · 2 unmodified lines
32	void *obj;	28	void *obj;
33	struct kref ref_cnt;	29	struct kref ref_cnt;
34	struct list_head list;	30	struct list_head list;
35
36	/* only used if keyed */
37	struct rb_node key_node;
38
39	/* only used if indexed */
40	struct rb_node index_node;
41	u32 index;	31	u32 index;
42	};	32	};
43		33
44	struct rxe_pool {	34	struct rxe_pool {
45	struct rxe_dev *rxe;	35	struct rxe_dev *rxe;
46	const char *name;	36	const char *name;
47	rwlock_t pool_lock; /* protects pool add/del/search */	37	void (cleanup)(struct rxe_pool_elem elem);
48	void (cleanup)(struct rxe_pool_elem obj);
49	enum rxe_pool_flags flags;	38	enum rxe_pool_flags flags;
50	enum rxe_elem_type type;	39	enum rxe_elem_type type;
51		40
@@ -54,36 +43,22 @@ struct rxe_pool { · 2 unmodified lines
54	size_t elem_size;	43	size_t elem_size;
55	size_t elem_offset;	44	size_t elem_offset;
56		45
57	/* only used if indexed */	46	struct xarray xa;
58	struct {	47	struct xa_limit limit;
59	struct rb_root tree;	48	u32 next;
60	unsigned long *table;
61	u32 last;
62	u32 max_index;
63	u32 min_index;
64	} index;
65
66	/* only used if keyed */
67	struct {
68	struct rb_root tree;
69	size_t key_offset;
70	size_t key_size;
71	} key;
72	};	49	};
73		50
74	/* initialize a pool of objects with given limit on	51	/* initialize a pool of objects with given limit on
75	* number of elements. gets parameters from rxe_type_info	52	* number of elements. gets parameters from rxe_type_info
76	* pool elements will be allocated out of a slab cache	53	* pool elements will be allocated out of a slab cache
77	*/	54	*/
78	int rxe_pool_init(struct rxe_dev rxe, struct rxe_pool pool,	55	void rxe_pool_init(struct rxe_dev rxe, struct rxe_pool pool,
79	enum rxe_elem_type type, u32 max_elem);	56	enum rxe_elem_type type);
80		57
81	/* free resources from object pool */	58	/* free resources from object pool */
82	void rxe_pool_cleanup(struct rxe_pool *pool);	59	void rxe_pool_cleanup(struct rxe_pool *pool);
83		60
84	/* allocate an object from pool holding and not holding the pool lock */	61	/* allocate an object from pool */
85	void rxe_alloc_locked(struct rxe_pool pool);
86
87	void rxe_alloc(struct rxe_pool pool);	62	void rxe_alloc(struct rxe_pool pool);
88		63
89	/* connect already allocated object to pool */	64	/* connect already allocated object to pool */
@@ -91,69 +66,17 @@ int __rxe_add_to_pool(struct rxe_pool pool, struct rxe_pool_elem elem); · 1 unmodified line
91		66
92	#define rxe_add_to_pool(pool, obj) __rxe_add_to_pool(pool, &(obj)->elem)	67	#define rxe_add_to_pool(pool, obj) __rxe_add_to_pool(pool, &(obj)->elem)
93		68
94	/* assign an index to an indexed object and insert object into	69	/* lookup an indexed object from index. takes a reference on object */
95	* pool's rb tree holding and not holding the pool_lock
96	*/
97	int __rxe_add_index_locked(struct rxe_pool_elem *elem);
98
99	#define rxe_add_index_locked(obj) __rxe_add_index_locked(&(obj)->elem)
100
101	int __rxe_add_index(struct rxe_pool_elem *elem);
102
103	#define rxe_add_index(obj) __rxe_add_index(&(obj)->elem)
104
105	/* drop an index and remove object from rb tree
106	* holding and not holding the pool_lock
107	*/
108	void __rxe_drop_index_locked(struct rxe_pool_elem *elem);
109
110	#define rxe_drop_index_locked(obj) __rxe_drop_index_locked(&(obj)->elem)
111
112	void __rxe_drop_index(struct rxe_pool_elem *elem);
113
114	#define rxe_drop_index(obj) __rxe_drop_index(&(obj)->elem)
115
116	/* assign a key to a keyed object and insert object into
117	* pool's rb tree holding and not holding pool_lock
118	*/
119	int __rxe_add_key_locked(struct rxe_pool_elem elem, void key);
120
121	#define rxe_add_key_locked(obj, key) __rxe_add_key_locked(&(obj)->elem, key)
122
123	int __rxe_add_key(struct rxe_pool_elem elem, void key);
124
125	#define rxe_add_key(obj, key) __rxe_add_key(&(obj)->elem, key)
126
127	/* remove elem from rb tree holding and not holding the pool_lock */
128	void __rxe_drop_key_locked(struct rxe_pool_elem *elem);
129
130	#define rxe_drop_key_locked(obj) __rxe_drop_key_locked(&(obj)->elem)
131
132	void __rxe_drop_key(struct rxe_pool_elem *elem);
133
134	#define rxe_drop_key(obj) __rxe_drop_key(&(obj)->elem)
135
136	/* lookup an indexed object from index holding and not holding the pool_lock.
137	* takes a reference on object
138	*/
139	void rxe_pool_get_index_locked(struct rxe_pool pool, u32 index);
140
141	void rxe_pool_get_index(struct rxe_pool pool, u32 index);	70	void rxe_pool_get_index(struct rxe_pool pool, u32 index);
142		71
143	/* lookup keyed object from key holding and not holding the pool_lock.	72	int __rxe_get(struct rxe_pool_elem *elem);
144	* takes a reference on the objecti
145	*/
146	void rxe_pool_get_key_locked(struct rxe_pool pool, void *key);
147		73
148	void rxe_pool_get_key(struct rxe_pool pool, void *key);	74	#define rxe_get(obj) __rxe_get(&(obj)->elem)
149		75
150	/* cleanup an object when all references are dropped */	76	int __rxe_put(struct rxe_pool_elem *elem);
151	void rxe_elem_release(struct kref *kref);
152		77
153	/* take a reference on an object */	78	#define rxe_put(obj) __rxe_put(&(obj)->elem)
154	#define rxe_add_ref(obj) kref_get(&(obj)->elem.ref_cnt)
155		79
156	/* drop a reference on an object */	80	#define rxe_read(obj) kref_read(&(obj)->elem.ref_cnt)
157	#define rxe_drop_ref(obj) kref_put(&(obj)->elem.ref_cnt, rxe_elem_release)
158		81
159	#endif /* RXE_POOL_H */	82	#endif /* RXE_POOL_H */

drivers/infiniband/sw/rxe/rxe_qp.c+30−27

 void free_rd_atomic_resource(struct rxe_qp *qp, struct resp_res *res)
 {
-	if (res->type == RXE_ATOMIC_MASK) {
+	if (res->type == RXE_ATOMIC_MASK)
 		kfree_skb(res->atomic.skb);
-	} else if (res->type == RXE_READ_MASK) {
-		if (res->read.mr)
-			rxe_drop_ref(res->read.mr);
-	}
 	res->type = 0;
 }
 		break;
 	}
-	INIT_LIST_HEAD(&qp->grp_list);
-	spin_lock_init(&qp->grp_lock);
 	spin_lock_init(&qp->state_lock);
 	atomic_set(&qp->ssn, 0);
 	struct rxe_cq *scq = to_rcq(init->send_cq);
 	struct rxe_srq *srq = init->srq ? to_rsrq(init->srq) : NULL;
-	rxe_add_ref(pd);
+	rxe_get(pd);
-	rxe_add_ref(rcq);
+	rxe_get(rcq);
-	rxe_add_ref(scq);
+	rxe_get(scq);
 	if (srq)
-		rxe_add_ref(srq);
+		rxe_get(srq);
 	qp->pd			= pd;
 	qp->rcq			= rcq;
 	qp->srq = NULL;
 	if (srq)
-		rxe_drop_ref(srq);
+		rxe_put(srq);
-	rxe_drop_ref(scq);
+	rxe_put(scq);
-	rxe_drop_ref(rcq);
+	rxe_put(rcq);
-	rxe_drop_ref(pd);
+	rxe_put(pd);
 	return err;
 }
 	qp->resp.sent_psn_nak = 0;
 	if (qp->resp.mr) {
-		rxe_drop_ref(qp->resp.mr);
+		rxe_put(qp->resp.mr);
 		qp->resp.mr = NULL;
 	}
 	return 0;
 }
+int rxe_qp_chk_destroy(struct rxe_qp *qp)
+{
+	/* See IBA o10-2.2.3
+	 * An attempt to destroy a QP while attached to a mcast group
+	 * will fail immediately.
+	 */
+	if (atomic_read(&qp->mcg_num)) {
+		pr_debug("Attempt to destroy QP while attached to multicast group\n");
+		return -EBUSY;
+	}
+	return 0;
+}
 /* called by the destroy qp verb */
 void rxe_qp_destroy(struct rxe_qp *qp)
 {
 {
 	struct rxe_qp *qp = container_of(work, typeof(*qp), cleanup_work.work);
-	rxe_drop_all_mcast_groups(qp);
 	if (qp->sq.queue)
 		rxe_queue_cleanup(qp->sq.queue);
 	if (qp->srq)
-		rxe_drop_ref(qp->srq);
+		rxe_put(qp->srq);
 	if (qp->rq.queue)
 		rxe_queue_cleanup(qp->rq.queue);
 	if (qp->scq)
-		rxe_drop_ref(qp->scq);
+		rxe_put(qp->scq);
 	if (qp->rcq)
-		rxe_drop_ref(qp->rcq);
+		rxe_put(qp->rcq);
 	if (qp->pd)
-		rxe_drop_ref(qp->pd);
+		rxe_put(qp->pd);
-	if (qp->resp.mr) {
+	if (qp->resp.mr)
-		rxe_drop_ref(qp->resp.mr);
+		rxe_put(qp->resp.mr);
-		qp->resp.mr = NULL;
-	}
 	if (qp_type(qp) == IB_QPT_RC)
 		sk_dst_reset(qp->sk->sk);

drivers/infiniband/sw/rxe/rxe_queue.c+6−4

 	struct rxe_queue *new_q;
 	unsigned int num_elem = *num_elem_p;
 	int err;
+	unsigned long producer_flags;
+	unsigned long consumer_flags;
 	new_q = rxe_queue_init(q->rxe, &num_elem, elem_size, q->type);
 	if (!new_q)
 		goto err1;
 	}
-	spin_lock_bh(consumer_lock);
+	spin_lock_irqsave(consumer_lock, consumer_flags);
 	if (producer_lock) {
-		spin_lock_bh(producer_lock);
+		spin_lock_irqsave(producer_lock, producer_flags);
 		err = resize_finish(q, new_q, num_elem);
-		spin_unlock_bh(producer_lock);
+		spin_unlock_irqrestore(producer_lock, producer_flags);
 	} else {
 		err = resize_finish(q, new_q, num_elem);
 	}
-	spin_unlock_bh(consumer_lock);
+	spin_unlock_irqrestore(consumer_lock, consumer_flags);
 	rxe_queue_cleanup(new_q);	/* new/old dep on err */
 	if (err)

drivers/infiniband/sw/rxe/rxe_recv.c+13−13

@@ -217,7 +217,7 @@ static int hdr_check(struct rxe_pkt_info *pkt) · 216 unmodified lines
217	return 0;	217	return 0;
218		218
219	err2:	219	err2:
220	rxe_drop_ref(qp);	220	rxe_put(qp);
221	err1:	221	err1:
222	return -EINVAL;	222	return -EINVAL;
223	}	223	}
@@ -233,8 +233,8 @@ static inline void rxe_rcv_pkt(struct rxe_pkt_info pkt, struct sk_buff skb) · 9 unmodified lines
233	static void rxe_rcv_mcast_pkt(struct rxe_dev rxe, struct sk_buff skb)	233	static void rxe_rcv_mcast_pkt(struct rxe_dev rxe, struct sk_buff skb)
234	{	234	{
235	struct rxe_pkt_info *pkt = SKB_TO_PKT(skb);	235	struct rxe_pkt_info *pkt = SKB_TO_PKT(skb);
236	struct rxe_mc_grp *mcg;	236	struct rxe_mcg *mcg;
237	struct rxe_mc_elem *mce;	237	struct rxe_mca *mca;
238	struct rxe_qp *qp;	238	struct rxe_qp *qp;
239	union ib_gid dgid;	239	union ib_gid dgid;
240	int err;	240	int err;
@@ -246,19 +246,19 @@ static void rxe_rcv_mcast_pkt(struct rxe_dev rxe, struct sk_buff skb) · 5 unmodified lines
246	memcpy(&dgid, &ipv6_hdr(skb)->daddr, sizeof(dgid));	246	memcpy(&dgid, &ipv6_hdr(skb)->daddr, sizeof(dgid));
247		247
248	/* lookup mcast group corresponding to mgid, takes a ref */	248	/* lookup mcast group corresponding to mgid, takes a ref */
249	mcg = rxe_pool_get_key(&rxe->mc_grp_pool, &dgid);	249	mcg = rxe_lookup_mcg(rxe, &dgid);
250	if (!mcg)	250	if (!mcg)
251	goto drop; /* mcast group not registered */	251	goto drop; /* mcast group not registered */
252		252
253	spin_lock_bh(&mcg->mcg_lock);	253	spin_lock_bh(&rxe->mcg_lock);
254		254
255	/* this is unreliable datagram service so we let	255	/* this is unreliable datagram service so we let
256	* failures to deliver a multicast packet to a	256	* failures to deliver a multicast packet to a
257	* single QP happen and just move on and try	257	* single QP happen and just move on and try
258	* the rest of them on the list	258	* the rest of them on the list
259	*/	259	*/
260	list_for_each_entry(mce, &mcg->qp_list, qp_list) {	260	list_for_each_entry(mca, &mcg->qp_list, qp_list) {
261	qp = mce->qp;	261	qp = mca->qp;
262		262
263	/* validate qp for incoming packet */	263	/* validate qp for incoming packet */
264	err = check_type_state(rxe, pkt, qp);	264	err = check_type_state(rxe, pkt, qp);
@@ -273,7 +273,7 @@ static void rxe_rcv_mcast_pkt(struct rxe_dev rxe, struct sk_buff skb) · 8 unmodified lines
273	* skb and pass to the QP. Pass the original skb to	273	* skb and pass to the QP. Pass the original skb to
274	* the last QP in the list.	274	* the last QP in the list.
275	*/	275	*/
276	if (mce->qp_list.next != &mcg->qp_list) {	276	if (mca->qp_list.next != &mcg->qp_list) {
277	struct sk_buff *cskb;	277	struct sk_buff *cskb;
278	struct rxe_pkt_info *cpkt;	278	struct rxe_pkt_info *cpkt;
279		279
@@ -288,19 +288,19 @@ static void rxe_rcv_mcast_pkt(struct rxe_dev rxe, struct sk_buff skb) · 8 unmodified lines
288		288
289	cpkt = SKB_TO_PKT(cskb);	289	cpkt = SKB_TO_PKT(cskb);
290	cpkt->qp = qp;	290	cpkt->qp = qp;
291	rxe_add_ref(qp);	291	rxe_get(qp);
292	rxe_rcv_pkt(cpkt, cskb);	292	rxe_rcv_pkt(cpkt, cskb);
293	} else {	293	} else {
294	pkt->qp = qp;	294	pkt->qp = qp;
295	rxe_add_ref(qp);	295	rxe_get(qp);
296	rxe_rcv_pkt(pkt, skb);	296	rxe_rcv_pkt(pkt, skb);
297	skb = NULL; /* mark consumed */	297	skb = NULL; /* mark consumed */
298	}	298	}
299	}	299	}
300		300
301	spin_unlock_bh(&mcg->mcg_lock);	301	spin_unlock_bh(&rxe->mcg_lock);
302		302
303	rxe_drop_ref(mcg); /* drop ref from rxe_pool_get_key. */	303	kref_put(&mcg->ref_cnt, rxe_cleanup_mcg);
304		304
305	if (likely(!skb))	305	if (likely(!skb))
306	return;	306	return;
@@ -397,7 +397,7 @@ void rxe_rcv(struct sk_buff *skb) · 90 unmodified lines
397		397
398	drop:	398	drop:
399	if (pkt->qp)	399	if (pkt->qp)
400	rxe_drop_ref(pkt->qp);	400	rxe_put(pkt->qp);
401		401
402	kfree_skb(skb);	402	kfree_skb(skb);
403	ib_device_put(&rxe->ib_dev);	403	ib_device_put(&rxe->ib_dev);

drivers/infiniband/sw/rxe/rxe_req.c+41−30

@@ -358,14 +358,14 @@ static inline int get_mtu(struct rxe_qp *qp) · 357 unmodified lines
358	}	358	}
359		359
360	static struct sk_buff init_req_packet(struct rxe_qp qp,	360	static struct sk_buff init_req_packet(struct rxe_qp qp,
		361	struct rxe_av *av,
361	struct rxe_send_wqe *wqe,	362	struct rxe_send_wqe *wqe,
362	int opcode, int payload,	363	int opcode, u32 payload,
363	struct rxe_pkt_info *pkt)	364	struct rxe_pkt_info *pkt)
364	{	365	{
365	struct rxe_dev *rxe = to_rdev(qp->ibqp.device);	366	struct rxe_dev *rxe = to_rdev(qp->ibqp.device);
366	struct sk_buff *skb;	367	struct sk_buff *skb;
367	struct rxe_send_wr *ibwr = &wqe->wr;	368	struct rxe_send_wr *ibwr = &wqe->wr;
368	struct rxe_av *av;
369	int pad = (-payload) & 0x3;	369	int pad = (-payload) & 0x3;
370	int paylen;	370	int paylen;
371	int solicited;	371	int solicited;
@@ -374,21 +374,9 @@ static struct sk_buff init_req_packet(struct rxe_qp qp, · 2 unmodified lines
374		374
375	/* length from start of bth to end of icrc */	375	/* length from start of bth to end of icrc */
376	paylen = rxe_opcode[opcode].length + payload + pad + RXE_ICRC_SIZE;	376	paylen = rxe_opcode[opcode].length + payload + pad + RXE_ICRC_SIZE;
377		377	pkt->paylen = paylen;
378	/* pkt->hdr, port_num and mask are initialized in ifc layer */
379	pkt->rxe = rxe;
380	pkt->opcode = opcode;
381	pkt->qp = qp;
382	pkt->psn = qp->req.psn;
383	pkt->mask = rxe_opcode[opcode].mask;
384	pkt->paylen = paylen;
385	pkt->wqe = wqe;
386		378
387	/* init skb */	379	/* init skb */
388	av = rxe_get_av(pkt);
389	if (!av)
390	return NULL;
391
392	skb = rxe_init_packet(rxe, av, paylen, pkt);	380	skb = rxe_init_packet(rxe, av, paylen, pkt);
393	if (unlikely(!skb))	381	if (unlikely(!skb))
394	return NULL;	382	return NULL;
@@ -447,13 +435,13 @@ static struct sk_buff init_req_packet(struct rxe_qp qp, · 52 unmodified lines
447	return skb;	435	return skb;
448	}	436	}
449		437
450	static int finish_packet(struct rxe_qp qp, struct rxe_send_wqe wqe,	438	static int finish_packet(struct rxe_qp qp, struct rxe_av av,
451	struct rxe_pkt_info pkt, struct sk_buff skb,	439	struct rxe_send_wqe wqe, struct rxe_pkt_info pkt,
452	int paylen)	440	struct sk_buff *skb, u32 paylen)
453	{	441	{
454	int err;	442	int err;
455		443
456	err = rxe_prepare(pkt, skb);	444	err = rxe_prepare(av, pkt, skb);
457	if (err)	445	if (err)
458	return err;	446	return err;
459		447
@@ -497,7 +485,7 @@ static void update_wqe_state(struct rxe_qp *qp, · 37 unmodified lines
497	static void update_wqe_psn(struct rxe_qp *qp,	485	static void update_wqe_psn(struct rxe_qp *qp,
498	struct rxe_send_wqe *wqe,	486	struct rxe_send_wqe *wqe,
499	struct rxe_pkt_info *pkt,	487	struct rxe_pkt_info *pkt,
500	int payload)	488	u32 payload)
501	{	489	{
502	/* number of packets left to send including current one */	490	/* number of packets left to send including current one */
503	int num_pkt = (wqe->dma.resid + payload + qp->mtu - 1) / qp->mtu;	491	int num_pkt = (wqe->dma.resid + payload + qp->mtu - 1) / qp->mtu;
@@ -540,7 +528,7 @@ static void rollback_state(struct rxe_send_wqe *wqe, · 36 unmodified lines
540	}	528	}
541		529
542	static void update_state(struct rxe_qp qp, struct rxe_send_wqe wqe,	530	static void update_state(struct rxe_qp qp, struct rxe_send_wqe wqe,
543	struct rxe_pkt_info *pkt, int payload)	531	struct rxe_pkt_info *pkt)
544	{	532	{
545	qp->req.opcode = pkt->opcode;	533	qp->req.opcode = pkt->opcode;
546		534
@@ -608,19 +596,22 @@ static int rxe_do_local_ops(struct rxe_qp qp, struct rxe_send_wqe wqe) · 61 unmodified lines
608	int rxe_requester(void *arg)	596	int rxe_requester(void *arg)
609	{	597	{
610	struct rxe_qp qp = (struct rxe_qp )arg;	598	struct rxe_qp qp = (struct rxe_qp )arg;
		599	struct rxe_dev *rxe = to_rdev(qp->ibqp.device);
611	struct rxe_pkt_info pkt;	600	struct rxe_pkt_info pkt;
612	struct sk_buff *skb;	601	struct sk_buff *skb;
613	struct rxe_send_wqe *wqe;	602	struct rxe_send_wqe *wqe;
614	enum rxe_hdr_mask mask;	603	enum rxe_hdr_mask mask;
615	int payload;	604	u32 payload;
616	int mtu;	605	int mtu;
617	int opcode;	606	int opcode;
618	int ret;	607	int ret;
619	struct rxe_send_wqe rollback_wqe;	608	struct rxe_send_wqe rollback_wqe;
620	u32 rollback_psn;	609	u32 rollback_psn;
621	struct rxe_queue *q = qp->sq.queue;	610	struct rxe_queue *q = qp->sq.queue;
		611	struct rxe_ah *ah;
		612	struct rxe_av *av;
622		613
623	rxe_add_ref(qp);	614	rxe_get(qp);
624		615
625	next_wqe:	616	next_wqe:
626	if (unlikely(!qp->valid \|\| qp->req.state == QP_STATE_ERROR))	617	if (unlikely(!qp->valid \|\| qp->req.state == QP_STATE_ERROR))
@@ -699,20 +690,34 @@ next_wqe: · 72 unmodified lines
699	wqe->state = wqe_state_done;	690	wqe->state = wqe_state_done;
700	wqe->status = IB_WC_SUCCESS;	691	wqe->status = IB_WC_SUCCESS;
701	__rxe_do_task(&qp->comp.task);	692	__rxe_do_task(&qp->comp.task);
702	rxe_drop_ref(qp);	693	rxe_put(qp);
703	return 0;	694	return 0;
704	}	695	}
705	payload = mtu;	696	payload = mtu;
706	}	697	}
707		698
708	skb = init_req_packet(qp, wqe, opcode, payload, &pkt);	699	pkt.rxe = rxe;
		700	pkt.opcode = opcode;
		701	pkt.qp = qp;
		702	pkt.psn = qp->req.psn;
		703	pkt.mask = rxe_opcode[opcode].mask;
		704	pkt.wqe = wqe;
		705
		706	av = rxe_get_av(&pkt, &ah);
		707	if (unlikely(!av)) {
		708	pr_err("qp#%d Failed no address vector\n", qp_num(qp));
		709	wqe->status = IB_WC_LOC_QP_OP_ERR;
		710	goto err_drop_ah;
		711	}
		712
		713	skb = init_req_packet(qp, av, wqe, opcode, payload, &pkt);
709	if (unlikely(!skb)) {	714	if (unlikely(!skb)) {
710	pr_err("qp#%d Failed allocating skb\n", qp_num(qp));	715	pr_err("qp#%d Failed allocating skb\n", qp_num(qp));
711	wqe->status = IB_WC_LOC_QP_OP_ERR;	716	wqe->status = IB_WC_LOC_QP_OP_ERR;
712	goto err;	717	goto err_drop_ah;
713	}	718	}
714		719
715	ret = finish_packet(qp, wqe, &pkt, skb, payload);	720	ret = finish_packet(qp, av, wqe, &pkt, skb, payload);
716	if (unlikely(ret)) {	721	if (unlikely(ret)) {
717	pr_debug("qp#%d Error during finish packet\n", qp_num(qp));	722	pr_debug("qp#%d Error during finish packet\n", qp_num(qp));
718	if (ret == -EFAULT)	723	if (ret == -EFAULT)
@@ -720,9 +725,12 @@ next_wqe: · 1 unmodified line
720	else	725	else
721	wqe->status = IB_WC_LOC_QP_OP_ERR;	726	wqe->status = IB_WC_LOC_QP_OP_ERR;
722	kfree_skb(skb);	727	kfree_skb(skb);
723	goto err;	728	goto err_drop_ah;
724	}	729	}
725		730
		731	if (ah)
		732	rxe_put(ah);
		733
726	/*	734	/*
727	* To prevent a race on wqe access between requester and completer,	735	* To prevent a race on wqe access between requester and completer,
728	* wqe members state and psn need to be set before calling	736	* wqe members state and psn need to be set before calling
@@ -747,15 +755,18 @@ next_wqe: · 18 unmodified lines
747	goto err;	755	goto err;
748	}	756	}
749		757
750	update_state(qp, wqe, &pkt, payload);	758	update_state(qp, wqe, &pkt);
751		759
752	goto next_wqe;	760	goto next_wqe;
753		761
		762	err_drop_ah:
		763	if (ah)
		764	rxe_put(ah);
754	err:	765	err:
755	wqe->state = wqe_state_error;	766	wqe->state = wqe_state_error;
756	__rxe_do_task(&qp->comp.task);	767	__rxe_do_task(&qp->comp.task);
757		768
758	exit:	769	exit:
759	rxe_drop_ref(qp);	770	rxe_put(qp);
760	return -EAGAIN;	771	return -EAGAIN;
761	}	772	}

drivers/infiniband/sw/rxe/rxe_resp.c+110−60

 	if (qp->resp.state == QP_STATE_ERROR) {
 		while ((skb = skb_dequeue(&qp->req_pkts))) {
-			rxe_drop_ref(qp);
+			rxe_put(qp);
 			kfree_skb(skb);
 			ib_device_put(qp->ibqp.device);
 		}
 	struct ib_event ev;
 	unsigned int count;
 	size_t size;
+	unsigned long flags;
 	if (srq->error)
 		return RESPST_ERR_RNR;
-	spin_lock_bh(&srq->rq.consumer_lock);
+	spin_lock_irqsave(&srq->rq.consumer_lock, flags);
 	wqe = queue_head(q, QUEUE_TYPE_FROM_CLIENT);
 	if (!wqe) {
-		spin_unlock_bh(&srq->rq.consumer_lock);
+		spin_unlock_irqrestore(&srq->rq.consumer_lock, flags);
 		return RESPST_ERR_RNR;
 	}
 	/* don't trust user space data */
 	if (unlikely(wqe->dma.num_sge > srq->rq.max_sge)) {
-		spin_unlock_bh(&srq->rq.consumer_lock);
+		spin_unlock_irqrestore(&srq->rq.consumer_lock, flags);
 		pr_warn("%s: invalid num_sge in SRQ entry\n", __func__);
 		return RESPST_ERR_MALFORMED_WQE;
 	}
 		goto event;
 	}
-	spin_unlock_bh(&srq->rq.consumer_lock);
+	spin_unlock_irqrestore(&srq->rq.consumer_lock, flags);
 	return RESPST_CHK_LENGTH;
 event:
-	spin_unlock_bh(&srq->rq.consumer_lock);
+	spin_unlock_irqrestore(&srq->rq.consumer_lock, flags);
 	ev.device = qp->ibqp.device;
 	ev.element.srq = qp->ibqp.srq;
 	ev.event = IB_EVENT_SRQ_LIMIT_REACHED;
 		if (mw->access & IB_ZERO_BASED)
 			qp->resp.offset = mw->addr;
-		rxe_drop_ref(mw);
+		rxe_put(mw);
-		rxe_add_ref(mr);
+		rxe_get(mr);
 	} else {
 		mr = lookup_mr(qp->pd, access, rkey, RXE_LOOKUP_REMOTE);
 		if (!mr) {
 err:
 	if (mr)
-		rxe_drop_ref(mr);
+		rxe_put(mr);
 	if (mw)
-		rxe_drop_ref(mw);
+		rxe_put(mw);
 	return state;
 }
 	if (ack->mask & RXE_ATMACK_MASK)
 		atmack_set_orig(ack, qp->resp.atomic_orig);
-	err = rxe_prepare(ack, skb);
+	err = rxe_prepare(&qp->pri_av, ack, skb);
 	if (err) {
 		kfree_skb(skb);
 		return NULL;
 	return skb;
 }
+static struct resp_res *rxe_prepare_read_res(struct rxe_qp *qp,
+					struct rxe_pkt_info *pkt)
+{
+	struct resp_res *res;
+	u32 pkts;
+	res = &qp->resp.resources[qp->resp.res_head];
+	rxe_advance_resp_resource(qp);
+	free_rd_atomic_resource(qp, res);
+	res->type = RXE_READ_MASK;
+	res->replay = 0;
+	res->read.va = qp->resp.va + qp->resp.offset;
+	res->read.va_org = qp->resp.va + qp->resp.offset;
+	res->read.resid = qp->resp.resid;
+	res->read.length = qp->resp.resid;
+	res->read.rkey = qp->resp.rkey;
+	pkts = max_t(u32, (reth_len(pkt) + qp->mtu - 1)/qp->mtu, 1);
+	res->first_psn = pkt->psn;
+	res->cur_psn = pkt->psn;
+	res->last_psn = (pkt->psn + pkts - 1) & BTH_PSN_MASK;
+	res->state = rdatm_res_state_new;
+	return res;
+}
+/**
+ * rxe_recheck_mr - revalidate MR from rkey and get a reference
+ * @qp: the qp
+ * @rkey: the rkey
+ *
+ * This code allows the MR to be invalidated or deregistered or
+ * the MW if one was used to be invalidated or deallocated.
+ * It is assumed that the access permissions if originally good
+ * are OK and the mappings to be unchanged.
+ *
+ * Return: mr on success else NULL
+ */
+static struct rxe_mr *rxe_recheck_mr(struct rxe_qp *qp, u32 rkey)
+{
+	struct rxe_dev *rxe = to_rdev(qp->ibqp.device);
+	struct rxe_mr *mr;
+	struct rxe_mw *mw;
+	if (rkey_is_mw(rkey)) {
+		mw = rxe_pool_get_index(&rxe->mw_pool, rkey >> 8);
+		if (!mw || mw->rkey != rkey)
+			return NULL;
+		if (mw->state != RXE_MW_STATE_VALID) {
+			rxe_put(mw);
+			return NULL;
+		}
+		mr = mw->mr;
+		rxe_put(mw);
+	} else {
+		mr = rxe_pool_get_index(&rxe->mr_pool, rkey >> 8);
+		if (!mr || mr->rkey != rkey)
+			return NULL;
+	}
+	if (mr->state != RXE_MR_STATE_VALID) {
+		rxe_put(mr);
+		return NULL;
+	}
+	return mr;
+}
 /* RDMA read response. If res is not NULL, then we have a current RDMA request
  * being processed or replayed.
  */
 	int opcode;
 	int err;
 	struct resp_res *res = qp->resp.res;
+	struct rxe_mr *mr;
 	if (!res) {
-		/* This is the first time we process that request. Get a
+		res = rxe_prepare_read_res(qp, req_pkt);
-		 * resource
+		qp->resp.res = res;
-		 */
-		res = &qp->resp.resources[qp->resp.res_head];
-		free_rd_atomic_resource(qp, res);
-		rxe_advance_resp_resource(qp);
-		res->type		= RXE_READ_MASK;
-		res->replay		= 0;
-		res->read.va		= qp->resp.va +
-					  qp->resp.offset;
-		res->read.va_org	= qp->resp.va +
-					  qp->resp.offset;
-		res->first_psn		= req_pkt->psn;
-		if (reth_len(req_pkt)) {
-			res->last_psn	= (req_pkt->psn +
-					   (reth_len(req_pkt) + mtu - 1) /
-					   mtu - 1) & BTH_PSN_MASK;
-		} else {
-			res->last_psn	= res->first_psn;
-		}
-		res->cur_psn		= req_pkt->psn;
-		res->read.resid		= qp->resp.resid;
-		res->read.length	= qp->resp.resid;
-		res->read.rkey		= qp->resp.rkey;
-		/* note res inherits the reference to mr from qp */
-		res->read.mr		= qp->resp.mr;
-		qp->resp.mr		= NULL;
-		qp->resp.res		= res;
-		res->state		= rdatm_res_state_new;
 	}
 	if (res->state == rdatm_res_state_new) {
+		mr = qp->resp.mr;
+		qp->resp.mr = NULL;
 		if (res->read.resid <= mtu)
 			opcode = IB_OPCODE_RC_RDMA_READ_RESPONSE_ONLY;
 		else
 			opcode = IB_OPCODE_RC_RDMA_READ_RESPONSE_FIRST;
 	} else {
+		mr = rxe_recheck_mr(qp, res->read.rkey);
+		if (!mr)
+			return RESPST_ERR_RKEY_VIOLATION;
 		if (res->read.resid > mtu)
 			opcode = IB_OPCODE_RC_RDMA_READ_RESPONSE_MIDDLE;
 		else
 	if (!skb)
 		return RESPST_ERR_RNR;
-	err = rxe_mr_copy(res->read.mr, res->read.va, payload_addr(&ack_pkt),
+	err = rxe_mr_copy(mr, res->read.va, payload_addr(&ack_pkt),
 			  payload, RXE_FROM_MR_OBJ);
 	if (err)
 		pr_err("Failed copying memory\n");
+	if (mr)
+		rxe_put(mr);
 	if (bth_pad(&ack_pkt)) {
 		u8 *pad = payload_addr(&ack_pkt) + payload;
 			return RESPST_ERR_INVALIDATE_RKEY;
 	}
+	if (pkt->mask & RXE_END_MASK)
+		/* We successfully processed this new request. */
+		qp->resp.msn++;
 	/* next expected psn, read handles this separately */
 	qp->resp.psn = (pkt->psn + 1) & BTH_PSN_MASK;
 	qp->resp.ack_psn = qp->resp.psn;
 	qp->resp.opcode = pkt->opcode;
 	qp->resp.status = IB_WC_SUCCESS;
-	if (pkt->mask & RXE_COMP_MASK) {
+	if (pkt->mask & RXE_COMP_MASK)
-		/* We successfully processed this new request. */
-		qp->resp.msn++;
 		return RESPST_COMPLETE;
-	} else if (qp_type(qp) == IB_QPT_RC)
+	else if (qp_type(qp) == IB_QPT_RC)
 		return RESPST_ACKNOWLEDGE;
 	else
 		return RESPST_CLEANUP;
 	rc = rxe_xmit_packet(qp, &ack_pkt, skb);
 	if (rc) {
 		pr_err_ratelimited("Failed sending ack\n");
-		rxe_drop_ref(qp);
+		rxe_put(qp);
 	}
 out:
 	return rc;
 	if (pkt) {
 		skb = skb_dequeue(&qp->req_pkts);
-		rxe_drop_ref(qp);
+		rxe_put(qp);
 		kfree_skb(skb);
 		ib_device_put(qp->ibqp.device);
 	}
 	if (qp->resp.mr) {
-		rxe_drop_ref(qp->resp.mr);
+		rxe_put(qp->resp.mr);
 		qp->resp.mr = NULL;
 	}
 		}
 		if (qp->resp.mr) {
-			rxe_drop_ref(qp->resp.mr);
+			rxe_put(qp->resp.mr);
 			qp->resp.mr = NULL;
 		}
 	struct rxe_queue *q = qp->rq.queue;
 	while ((skb = skb_dequeue(&qp->req_pkts))) {
-		rxe_drop_ref(qp);
+		rxe_put(qp);
 		kfree_skb(skb);
 		ib_device_put(qp->ibqp.device);
 	}
 	struct rxe_pkt_info *pkt = NULL;
 	int ret = 0;
-	rxe_add_ref(qp);
+	rxe_get(qp);
 	qp->resp.aeth_syndrome = AETH_ACK_UNLIMITED;
 exit:
 	ret = -EAGAIN;
 done:
-	rxe_drop_ref(qp);
+	rxe_put(qp);
 	return ret;
 }

drivers/infiniband/sw/rxe/rxe_verbs.c+40−68

 {
 	struct rxe_ucontext *uc = to_ruc(ibuc);
-	rxe_drop_ref(uc);
+	rxe_put(uc);
 }
 static int rxe_port_immutable(struct ib_device *dev, u32 port_num,
 {
 	struct rxe_pd *pd = to_rpd(ibpd);
-	rxe_drop_ref(pd);
+	rxe_put(pd);
 	return 0;
 }
 		return err;
 	/* create index > 0 */
-	rxe_add_index(ah);
 	ah->ah_num = ah->elem.index;
 	if (uresp) {
 		err = copy_to_user(&uresp->ah_num, &ah->ah_num,
 					 sizeof(uresp->ah_num));
 		if (err) {
-			rxe_drop_index(ah);
+			rxe_put(ah);
-			rxe_drop_ref(ah);
 			return -EFAULT;
 		}
 	} else if (ah->is_user) {
 {
 	struct rxe_ah *ah = to_rah(ibah);
-	rxe_drop_index(ah);
+	rxe_put(ah);
-	rxe_drop_ref(ah);
 	return 0;
 }
 	if (err)
 		goto err1;
-	rxe_add_ref(pd);
+	rxe_get(pd);
 	srq->pd = pd;
 	err = rxe_srq_from_init(rxe, srq, init, udata, uresp);
 	return 0;
 err2:
-	rxe_drop_ref(pd);
+	rxe_put(pd);
-	rxe_drop_ref(srq);
+	rxe_put(srq);
 err1:
 	return err;
 }
 	if (srq->rq.queue)
 		rxe_queue_cleanup(srq->rq.queue);
-	rxe_drop_ref(srq->pd);
+	rxe_put(srq->pd);
-	rxe_drop_ref(srq);
+	rxe_put(srq);
 	return 0;
 }
 {
 	int err = 0;
 	struct rxe_srq *srq = to_rsrq(ibsrq);
+	unsigned long flags;
-	spin_lock_bh(&srq->rq.producer_lock);
+	spin_lock_irqsave(&srq->rq.producer_lock, flags);
 	while (wr) {
 		err = post_one_recv(&srq->rq, wr);
 		wr = wr->next;
 	}
-	spin_unlock_bh(&srq->rq.producer_lock);
+	spin_unlock_irqrestore(&srq->rq.producer_lock, flags);
 	if (err)
 		*bad_wr = wr;
 	if (err)
 		return err;
-	rxe_add_index(qp);
 	err = rxe_qp_from_init(rxe, qp, pd, init, uresp, ibqp->pd, udata);
 	if (err)
 		goto qp_init;
 	return 0;
 qp_init:
-	rxe_drop_index(qp);
+	rxe_put(qp);
-	rxe_drop_ref(qp);
 	return err;
 }
 static int rxe_destroy_qp(struct ib_qp *ibqp, struct ib_udata *udata)
 {
 	struct rxe_qp *qp = to_rqp(ibqp);
+	int ret;
+	ret = rxe_qp_chk_destroy(qp);
+	if (ret)
+		return ret;
 	rxe_qp_destroy(qp);
-	rxe_drop_index(qp);
+	rxe_put(qp);
-	rxe_drop_ref(qp);
 	return 0;
 }
 	int err;
 	struct rxe_sq *sq = &qp->sq;
 	struct rxe_send_wqe *send_wqe;
+	unsigned long flags;
 	int full;
 	err = validate_send_wr(qp, ibwr, mask, length);
 	if (err)
 		return err;
-	spin_lock_bh(&qp->sq.sq_lock);
+	spin_lock_irqsave(&qp->sq.sq_lock, flags);
 	full = queue_full(sq->queue, QUEUE_TYPE_TO_DRIVER);
 	if (unlikely(full)) {
-		spin_unlock_bh(&qp->sq.sq_lock);
+		spin_unlock_irqrestore(&qp->sq.sq_lock, flags);
 		return -ENOMEM;
 	}
 	queue_advance_producer(sq->queue, QUEUE_TYPE_TO_DRIVER);
-	spin_unlock_bh(&qp->sq.sq_lock);
+	spin_unlock_irqrestore(&qp->sq.sq_lock, flags);
 	return 0;
 }
 	int err = 0;
 	struct rxe_qp *qp = to_rqp(ibqp);
 	struct rxe_rq *rq = &qp->rq;
+	unsigned long flags;
 	if (unlikely((qp_state(qp) < IB_QPS_INIT) || !qp->valid)) {
 		*bad_wr = wr;
 		goto err1;
 	}
-	spin_lock_bh(&rq->producer_lock);
+	spin_lock_irqsave(&rq->producer_lock, flags);
 	while (wr) {
 		err = post_one_recv(rq, wr);
 		wr = wr->next;
 	}
-	spin_unlock_bh(&rq->producer_lock);
+	spin_unlock_irqrestore(&rq->producer_lock, flags);
 	if (qp->resp.state == QP_STATE_ERROR)
 		rxe_run_task(&qp->resp.task, 1);
 	rxe_cq_disable(cq);
-	rxe_drop_ref(cq);
+	rxe_put(cq);
 	return 0;
 }
 	int i;
 	struct rxe_cq *cq = to_rcq(ibcq);
 	struct rxe_cqe *cqe;
+	unsigned long flags;
-	spin_lock_bh(&cq->cq_lock);
+	spin_lock_irqsave(&cq->cq_lock, flags);
 	for (i = 0; i < num_entries; i++) {
 		cqe = queue_head(cq->queue, QUEUE_TYPE_FROM_DRIVER);
 		if (!cqe)
 		memcpy(wc++, &cqe->ibwc, sizeof(*wc));
 		queue_advance_consumer(cq->queue, QUEUE_TYPE_FROM_DRIVER);
 	}
-	spin_unlock_bh(&cq->cq_lock);
+	spin_unlock_irqrestore(&cq->cq_lock, flags);
 	return i;
 }
 	struct rxe_cq *cq = to_rcq(ibcq);
 	int ret = 0;
 	int empty;
+	unsigned long irq_flags;
-	spin_lock_bh(&cq->cq_lock);
+	spin_lock_irqsave(&cq->cq_lock, irq_flags);
 	if (cq->notify != IB_CQ_NEXT_COMP)
 		cq->notify = flags & IB_CQ_SOLICITED_MASK;
 	if ((flags & IB_CQ_REPORT_MISSED_EVENTS) && !empty)
 		ret = 1;
-	spin_unlock_bh(&cq->cq_lock);
+	spin_unlock_irqrestore(&cq->cq_lock, irq_flags);
 	return ret;
 }
 	if (!mr)
 		return ERR_PTR(-ENOMEM);
-	rxe_add_index(mr);
+	rxe_get(pd);
-	rxe_add_ref(pd);
 	rxe_mr_init_dma(pd, access, mr);
 	return &mr->ibmr;
 		goto err2;
 	}
-	rxe_add_index(mr);
-	rxe_add_ref(pd);
+	rxe_get(pd);
 	err = rxe_mr_init_user(pd, start, length, iova, access, mr);
 	if (err)
 	return &mr->ibmr;
 err3:
-	rxe_drop_ref(pd);
+	rxe_put(pd);
-	rxe_drop_index(mr);
+	rxe_put(mr);
-	rxe_drop_ref(mr);
 err2:
 	return ERR_PTR(err);
 }
 		goto err1;
 	}
-	rxe_add_index(mr);
+	rxe_get(pd);
-	rxe_add_ref(pd);
 	err = rxe_mr_init_fast(pd, max_num_sg, mr);
 	if (err)
 	return &mr->ibmr;
 err2:
-	rxe_drop_ref(pd);
+	rxe_put(pd);
-	rxe_drop_index(mr);
+	rxe_put(mr);
-	rxe_drop_ref(mr);
 err1:
 	return ERR_PTR(err);
 }
 	return n;
 }
-static int rxe_attach_mcast(struct ib_qp *ibqp, union ib_gid *mgid, u16 mlid)
-{
-	int err;
-	struct rxe_dev *rxe = to_rdev(ibqp->device);
-	struct rxe_qp *qp = to_rqp(ibqp);
-	struct rxe_mc_grp *grp;
-	/* takes a ref on grp if successful */
-	err = rxe_mcast_get_grp(rxe, mgid, &grp);
-	if (err)
-		return err;
-	err = rxe_mcast_add_grp_elem(rxe, qp, grp);
-	rxe_drop_ref(grp);
-	return err;
-}
-static int rxe_detach_mcast(struct ib_qp *ibqp, union ib_gid *mgid, u16 mlid)
-{
-	struct rxe_dev *rxe = to_rdev(ibqp->device);
-	struct rxe_qp *qp = to_rqp(ibqp);
-	return rxe_mcast_drop_grp_elem(rxe, qp, mgid);
-}
 static ssize_t parent_show(struct device *device,
 			   struct device_attribute *attr, char *buf)
 {

drivers/infiniband/sw/rxe/rxe_verbs.h+12−15

@@ -157,7 +157,6 @@ struct resp_res { · 156 unmodified lines
157	struct sk_buff *skb;	157	struct sk_buff *skb;
158	} atomic;	158	} atomic;
159	struct {	159	struct {
160	struct rxe_mr *mr;
161	u64 va_org;	160	u64 va_org;
162	u32 rkey;	161	u32 rkey;
163	u32 length;	162	u32 length;
@@ -232,9 +231,7 @@ struct rxe_qp { · 68 unmodified lines
232	struct rxe_av pri_av;	231	struct rxe_av pri_av;
233	struct rxe_av alt_av;	232	struct rxe_av alt_av;
234		233
235	/* list of mcast groups qp has joined (for cleanup) */	234	atomic_t mcg_num;
236	struct list_head grp_list;
237	spinlock_t grp_lock; /* guard grp_list */
238		235
239	struct sk_buff_head req_pkts;	236	struct sk_buff_head req_pkts;
240	struct sk_buff_head resp_pkts;	237	struct sk_buff_head resp_pkts;
@@ -353,23 +350,20 @@ struct rxe_mw { · 112 unmodified lines
353	u64 length;	350	u64 length;
354	};	351	};
355		352
356	struct rxe_mc_grp {	353	struct rxe_mcg {
357	struct rxe_pool_elem elem;	354	struct rb_node node;
358	spinlock_t mcg_lock; /* guard group */	355	struct kref ref_cnt;
359	struct rxe_dev *rxe;	356	struct rxe_dev *rxe;
360	struct list_head qp_list;	357	struct list_head qp_list;
361	union ib_gid mgid;	358	union ib_gid mgid;
362	int num_qp;	359	atomic_t qp_num;
363	u32 qkey;	360	u32 qkey;
364	u16 pkey;	361	u16 pkey;
365	};	362	};
366		363
367	struct rxe_mc_elem {	364	struct rxe_mca {
368	struct rxe_pool_elem elem;
369	struct list_head qp_list;	365	struct list_head qp_list;
370	struct list_head grp_list;
371	struct rxe_qp *qp;	366	struct rxe_qp *qp;
372	struct rxe_mc_grp *grp;
373	};	367	};
374		368
375	struct rxe_port {	369	struct rxe_port {
@@ -401,7 +395,12 @@ struct rxe_dev { · 25 unmodified lines
401	struct rxe_pool mr_pool;	395	struct rxe_pool mr_pool;
402	struct rxe_pool mw_pool;	396	struct rxe_pool mw_pool;
403	struct rxe_pool mc_grp_pool;	397	struct rxe_pool mc_grp_pool;
404	struct rxe_pool mc_elem_pool;	398
		399	/* multicast support */
		400	spinlock_t mcg_lock;
		401	struct rb_root mcg_tree;
		402	atomic_t mcg_num;
		403	atomic_t mcg_attach;
405		404
406	spinlock_t pending_lock; /* guard pending_mmaps */	405	spinlock_t pending_lock; /* guard pending_mmaps */
407	struct list_head pending_mmaps;	406	struct list_head pending_mmaps;
@@ -482,6 +481,4 @@ static inline struct rxe_pd rxe_mw_pd(struct rxe_mw mw) · 74 unmodified lines
482		481
483	int rxe_register_device(struct rxe_dev rxe, const char ibdev_name);	482	int rxe_register_device(struct rxe_dev rxe, const char ibdev_name);
484		483
485	void rxe_mc_cleanup(struct rxe_pool_elem *elem);
486
487	#endif /* RXE_VERBS_H */	484	#endif /* RXE_VERBS_H */

drivers/infiniband/ulp/ipoib/ipoib_netlink.c+0−1

@@ -32,7 +32,6 @@ · 31 unmodified lines
32		32
33	#include <linux/netdevice.h>	33	#include <linux/netdevice.h>
34	#include <linux/if_arp.h> /* For ARPHRD_xxx */	34	#include <linux/if_arp.h> /* For ARPHRD_xxx */
35	#include <linux/module.h>
36	#include <net/rtnetlink.h>	35	#include <net/rtnetlink.h>
37	#include "ipoib.h"	36	#include "ipoib.h"
38		37

drivers/infiniband/ulp/ipoib/ipoib_vlan.c+0−1

@@ -30,7 +30,6 @@ · 29 unmodified lines
30	* SOFTWARE.	30	* SOFTWARE.
31	*/	31	*/
32		32
33	#include <linux/module.h>
34	#include <linux/sched/signal.h>	33	#include <linux/sched/signal.h>
35		34
36	#include <linux/init.h>	35	#include <linux/init.h>

drivers/infiniband/ulp/iser/iscsi_iser.h+6−7

  *
  * @sge:          memory region sg element
  * @rkey:         memory region remote key
- * @mem_h:        pointer to registration context (FMR/Fastreg)
+ * @desc:         pointer to fast registration context
  */
 struct iser_mem_reg {
-	struct ib_sge	 sge;
+	struct ib_sge sge;
-	u32		 rkey;
+	u32 rkey;
-	void		*mem_h;
+	struct iser_fr_desc *desc;
 };
 enum iser_desc_type {
 int  iser_post_send(struct ib_conn *ib_conn, struct iser_tx_desc *tx_desc);
 int iser_dma_map_task_data(struct iscsi_iser_task *iser_task,
-			   struct iser_data_buf *data,
 			   enum iser_data_dir iser_dir,
 			   enum dma_data_direction dma_dir);
 void iser_dma_unmap_task_data(struct iscsi_iser_task *iser_task,
-			      struct iser_data_buf *data,
+			      enum iser_data_dir iser_dir,
-			      enum dma_data_direction dir);
+			      enum dma_data_direction dma_dir);
 int  iser_initialize_task_headers(struct iscsi_task *task,
 			struct iser_tx_desc *tx_desc);

drivers/infiniband/ulp/iser/iser_initiator.c+15−43

 	struct iser_mem_reg *mem_reg;
 	int err;
 	struct iser_ctrl *hdr = &iser_task->desc.iser_header;
-	struct iser_data_buf *buf_in = &iser_task->data[ISER_DIR_IN];
 	err = iser_dma_map_task_data(iser_task,
-				     buf_in,
 				     ISER_DIR_IN,
 				     DMA_FROM_DEVICE);
 	if (err)
 		return err;
-	if (scsi_prot_sg_count(iser_task->sc)) {
-		struct iser_data_buf *pbuf_in = &iser_task->prot[ISER_DIR_IN];
-		err = iser_dma_map_task_data(iser_task,
-					     pbuf_in,
-					     ISER_DIR_IN,
-					     DMA_FROM_DEVICE);
-		if (err)
-			return err;
-	}
 	err = iser_reg_mem_fastreg(iser_task, ISER_DIR_IN, false);
 	if (err) {
 		iser_err("Failed to set up Data-IN RDMA\n");
-		return err;
+		goto out_err;
 	}
 	mem_reg = &iser_task->rdma_reg[ISER_DIR_IN];
 		 (unsigned long long)mem_reg->sge.addr);
 	return 0;
+out_err:
+	iser_dma_unmap_task_data(iser_task, ISER_DIR_IN, DMA_FROM_DEVICE);
+	return err;
 }
 /* Register user buffer memory and initialize passive rdma
 	struct ib_sge *tx_dsg = &iser_task->desc.tx_sg[1];
 	err = iser_dma_map_task_data(iser_task,
-				     buf_out,
 				     ISER_DIR_OUT,
 				     DMA_TO_DEVICE);
 	if (err)
 		return err;
-	if (scsi_prot_sg_count(iser_task->sc)) {
-		struct iser_data_buf *pbuf_out = &iser_task->prot[ISER_DIR_OUT];
-		err = iser_dma_map_task_data(iser_task,
-					     pbuf_out,
-					     ISER_DIR_OUT,
-					     DMA_TO_DEVICE);
-		if (err)
-			return err;
-	}
 	err = iser_reg_mem_fastreg(iser_task, ISER_DIR_OUT,
 				   buf_out->data_len == imm_sz);
-	if (err != 0) {
+	if (err) {
 		iser_err("Failed to register write cmd RDMA mem\n");
-		return err;
+		goto out_err;
 	}
 	mem_reg = &iser_task->rdma_reg[ISER_DIR_OUT];
 	}
 	return 0;
+out_err:
+	iser_dma_unmap_task_data(iser_task, ISER_DIR_OUT, DMA_TO_DEVICE);
+	return err;
 }
 /* creates a new tx descriptor and adds header regd buffer */
 			struct iser_fr_desc *desc;
 			if (iser_task->dir[ISER_DIR_IN]) {
-				desc = iser_task->rdma_reg[ISER_DIR_IN].mem_h;
+				desc = iser_task->rdma_reg[ISER_DIR_IN].desc;
 				if (unlikely(iser_inv_desc(desc, rkey)))
 					return -EINVAL;
 			}
 			if (iser_task->dir[ISER_DIR_OUT]) {
-				desc = iser_task->rdma_reg[ISER_DIR_OUT].mem_h;
+				desc = iser_task->rdma_reg[ISER_DIR_OUT].desc;
 				if (unlikely(iser_inv_desc(desc, rkey)))
 					return -EINVAL;
 			}
 void iser_task_rdma_finalize(struct iscsi_iser_task *iser_task)
 {
-	int prot_count = scsi_prot_sg_count(iser_task->sc);
 	if (iser_task->dir[ISER_DIR_IN]) {
 		iser_unreg_mem_fastreg(iser_task, ISER_DIR_IN);
-		iser_dma_unmap_task_data(iser_task,
+		iser_dma_unmap_task_data(iser_task, ISER_DIR_IN,
-					 &iser_task->data[ISER_DIR_IN],
 					 DMA_FROM_DEVICE);
-		if (prot_count)
-			iser_dma_unmap_task_data(iser_task,
-						 &iser_task->prot[ISER_DIR_IN],
-						 DMA_FROM_DEVICE);
 	}
 	if (iser_task->dir[ISER_DIR_OUT]) {
 		iser_unreg_mem_fastreg(iser_task, ISER_DIR_OUT);
-		iser_dma_unmap_task_data(iser_task,
+		iser_dma_unmap_task_data(iser_task, ISER_DIR_OUT,
-					 &iser_task->data[ISER_DIR_OUT],
 					 DMA_TO_DEVICE);
-		if (prot_count)
-			iser_dma_unmap_task_data(iser_task,
-						 &iser_task->prot[ISER_DIR_OUT],
-						 DMA_TO_DEVICE);
 	}
 }

drivers/infiniband/ulp/iser/iser_memory.c+39−30

  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  * SOFTWARE.
  */
-#include <linux/module.h>
 #include <linux/kernel.h>
 #include <linux/slab.h>
 #include <linux/mm.h>
 }
 int iser_dma_map_task_data(struct iscsi_iser_task *iser_task,
-			   struct iser_data_buf *data,
 			   enum iser_data_dir iser_dir,
 			   enum dma_data_direction dma_dir)
 {
+	struct iser_data_buf *data = &iser_task->data[iser_dir];
 	struct ib_device *dev;
 	iser_task->dir[iser_dir] = 1;
 		iser_err("dma_map_sg failed!!!\n");
 		return -EINVAL;
 	}
+	if (scsi_prot_sg_count(iser_task->sc)) {
+		struct iser_data_buf *pdata = &iser_task->prot[iser_dir];
+		pdata->dma_nents = ib_dma_map_sg(dev, pdata->sg, pdata->size, dma_dir);
+		if (unlikely(pdata->dma_nents == 0)) {
+			iser_err("protection dma_map_sg failed!!!\n");
+			goto out_unmap;
+		}
+	}
 	return 0;
+out_unmap:
+	ib_dma_unmap_sg(dev, data->sg, data->size, dma_dir);
+	return -EINVAL;
 }
 void iser_dma_unmap_task_data(struct iscsi_iser_task *iser_task,
-			      struct iser_data_buf *data,
+			      enum iser_data_dir iser_dir,
-			      enum dma_data_direction dir)
+			      enum dma_data_direction dma_dir)
 {
+	struct iser_data_buf *data = &iser_task->data[iser_dir];
 	struct ib_device *dev;
 	dev = iser_task->iser_conn->ib_conn.device->ib_device;
-	ib_dma_unmap_sg(dev, data->sg, data->size, dir);
+	ib_dma_unmap_sg(dev, data->sg, data->size, dma_dir);
+	if (scsi_prot_sg_count(iser_task->sc)) {
+		struct iser_data_buf *pdata = &iser_task->prot[iser_dir];
+		ib_dma_unmap_sg(dev, pdata->sg, pdata->size, dma_dir);
+	}
 }
 static int iser_reg_dma(struct iser_device *device, struct iser_data_buf *mem,
 	struct iser_fr_desc *desc;
 	struct ib_mr_status mr_status;
-	desc = reg->mem_h;
+	desc = reg->desc;
 	if (!desc)
 		return;
 		ib_check_mr_status(desc->rsc.sig_mr, IB_MR_CHECK_SIG_STATUS,
 				   &mr_status);
 	}
-	iser_reg_desc_put_fr(&iser_task->iser_conn->ib_conn, reg->mem_h);
+	iser_reg_desc_put_fr(&iser_task->iser_conn->ib_conn, reg->desc);
-	reg->mem_h = NULL;
+	reg->desc = NULL;
 }
 static void iser_set_dif_domain(struct scsi_cmnd *sc,
 	return 0;
 }
-static int iser_reg_data_sg(struct iscsi_iser_task *task,
-			    struct iser_data_buf *mem,
-			    struct iser_fr_desc *desc, bool use_dma_key,
-			    struct iser_mem_reg *reg)
-{
-	struct iser_device *device = task->iser_conn->ib_conn.device;
-	if (use_dma_key)
-		return iser_reg_dma(device, mem, reg);
-	return iser_fast_reg_mr(task, mem, &desc->rsc, reg);
-}
 int iser_reg_mem_fastreg(struct iscsi_iser_task *task,
 			 enum iser_data_dir dir,
 			 bool all_imm)
 {
 	struct ib_conn *ib_conn = &task->iser_conn->ib_conn;
+	struct iser_device *device = ib_conn->device;
 	struct iser_data_buf *mem = &task->data[dir];
 	struct iser_mem_reg *reg = &task->rdma_reg[dir];
-	struct iser_fr_desc *desc = NULL;
+	struct iser_fr_desc *desc;
 	bool use_dma_key;
 	int err;
 	use_dma_key = mem->dma_nents == 1 && (all_imm || !iser_always_reg) &&
 		      scsi_get_prot_op(task->sc) == SCSI_PROT_NORMAL;
+	if (use_dma_key)
+		return iser_reg_dma(device, mem, reg);
-	if (!use_dma_key) {
+	desc = iser_reg_desc_get_fr(ib_conn);
-		desc = iser_reg_desc_get_fr(ib_conn);
-		reg->mem_h = desc;
-	}
 	if (scsi_get_prot_op(task->sc) == SCSI_PROT_NORMAL) {
-		err = iser_reg_data_sg(task, mem, desc, use_dma_key, reg);
+		err = iser_fast_reg_mr(task, mem, &desc->rsc, reg);
 		if (unlikely(err))
 			goto err_reg;
 	} else {
 		desc->sig_protected = true;
 	}
+	reg->desc = desc;
 	return 0;
 err_reg:
-	if (desc)
+	iser_reg_desc_put_fr(ib_conn, desc);
-		iser_reg_desc_put_fr(ib_conn, desc);
 	return err;
 }

drivers/infiniband/ulp/iser/iser_verbs.c+1−2

  * SOFTWARE.
  */
 #include <linux/kernel.h>
-#include <linux/module.h>
 #include <linux/slab.h>
 #include <linux/delay.h>
 			     enum iser_data_dir cmd_dir, sector_t *sector)
 {
 	struct iser_mem_reg *reg = &iser_task->rdma_reg[cmd_dir];
-	struct iser_fr_desc *desc = reg->mem_h;
+	struct iser_fr_desc *desc = reg->desc;
 	unsigned long sector_size = iser_task->sc->device->sector_size;
 	struct ib_mr_status mr_status;
 	int ret;

drivers/infiniband/ulp/opa_vnic/opa_vnic_netdev.c+0−1

@@ -50,7 +50,6 @@ · 49 unmodified lines
50	* netdev functionality.	50	* netdev functionality.
51	*/	51	*/
52		52
53	#include <linux/module.h>
54	#include <linux/if_vlan.h>	53	#include <linux/if_vlan.h>
55	#include <linux/crc32.h>	54	#include <linux/crc32.h>
56		55

drivers/infiniband/ulp/rtrs/rtrs-clt-sysfs.c+1−2

 static ssize_t add_path_show(struct device *dev,
 			     struct device_attribute *attr, char *page)
 {
-	return sysfs_emit(
+	return sysfs_emit(page,
-		page,
 		"Usage: echo [<source addr>@]<destination addr> > %s\n\n*addr ::= [ ip:<ipv4|ipv6> | gid:<gid> ]\n",
 		attr->attr.name);
 }

drivers/infiniband/ulp/rtrs/rtrs-clt.c+23−19

 	return changed;
 }
+static void rtrs_clt_stop_and_destroy_conns(struct rtrs_clt_path *clt_path);
 static void rtrs_rdma_error_recovery(struct rtrs_clt_con *con)
 {
 	struct rtrs_clt_path *clt_path = to_clt_path(con->c.path);
 	if (rtrs_clt_change_state_from_to(clt_path,
 					   RTRS_CLT_CONNECTED,
 					   RTRS_CLT_RECONNECTING)) {
-		struct rtrs_clt_sess *clt = clt_path->clt;
+		queue_work(rtrs_wq, &clt_path->err_recovery_work);
-		unsigned int delay_ms;
-		/*
-		 * Normal scenario, reconnect if we were successfully connected
-		 */
-		delay_ms = clt->reconnect_delay_sec * 1000;
-		queue_delayed_work(rtrs_wq, &clt_path->reconnect_dwork,
-				   msecs_to_jiffies(delay_ms +
-						    prandom_u32() % RTRS_RECONNECT_SEED));
 	} else {
 		/*
 		 * Error can happen just on establishing new connection,
 {
 	struct list_head *skip, *tmp;
 	/*
-	 * The skip_list is used only for the MIN_INFLIGHT policy.
+	 * The skip_list is used only for the MIN_INFLIGHT and MIN_LATENCY policies.
 	 * We need to remove paths from it, so that next IO can insert
 	 * paths (->mp_skip_entry) into a skip_list again.
 	 */
 static void rtrs_clt_reconnect_work(struct work_struct *work);
 static void rtrs_clt_close_work(struct work_struct *work);
+static void rtrs_clt_err_recovery_work(struct work_struct *work)
+{
+	struct rtrs_clt_path *clt_path;
+	struct rtrs_clt_sess *clt;
+	int delay_ms;
+	clt_path = container_of(work, struct rtrs_clt_path, err_recovery_work);
+	clt = clt_path->clt;
+	delay_ms = clt->reconnect_delay_sec * 1000;
+	rtrs_clt_stop_and_destroy_conns(clt_path);
+	queue_delayed_work(rtrs_wq, &clt_path->reconnect_dwork,
+			   msecs_to_jiffies(delay_ms +
+					    prandom_u32() %
+					    RTRS_RECONNECT_SEED));
+}
 static struct rtrs_clt_path *alloc_path(struct rtrs_clt_sess *clt,
 					const struct rtrs_addr *path,
 					size_t con_num, u32 nr_poll_queues)
 	clt_path->state = RTRS_CLT_CONNECTING;
 	atomic_set(&clt_path->connected_cnt, 0);
 	INIT_WORK(&clt_path->close_work, rtrs_clt_close_work);
+	INIT_WORK(&clt_path->err_recovery_work, rtrs_clt_err_recovery_work);
 	INIT_DELAYED_WORK(&clt_path->reconnect_dwork, rtrs_clt_reconnect_work);
 	rtrs_clt_init_hb(clt_path);
 	clt_path = container_of(work, struct rtrs_clt_path, close_work);
+	cancel_work_sync(&clt_path->err_recovery_work);
 	cancel_delayed_work_sync(&clt_path->reconnect_dwork);
 	rtrs_clt_stop_and_destroy_conns(clt_path);
 	rtrs_clt_change_state_get_old(clt_path, RTRS_CLT_CLOSED, NULL);
 {
 	struct rtrs_clt_path *clt_path;
 	struct rtrs_clt_sess *clt;
-	unsigned int delay_ms;
 	int err;
 	clt_path = container_of(to_delayed_work(work), struct rtrs_clt_path,
 	}
 	clt_path->reconnect_attempts++;
-	/* Stop everything */
-	rtrs_clt_stop_and_destroy_conns(clt_path);
 	msleep(RTRS_RECONNECT_BACKOFF);
 	if (rtrs_clt_change_state_get_old(clt_path, RTRS_CLT_CONNECTING, NULL)) {
 		err = init_path(clt_path);
 reconnect_again:
 	if (rtrs_clt_change_state_get_old(clt_path, RTRS_CLT_RECONNECTING, NULL)) {
 		clt_path->stats->reconnects.fail_cnt++;
-		delay_ms = clt->reconnect_delay_sec * 1000;
+		queue_work(rtrs_wq, &clt_path->err_recovery_work);
-		queue_delayed_work(rtrs_wq, &clt_path->reconnect_dwork,
-				   msecs_to_jiffies(delay_ms +
-						    prandom_u32() %
-						    RTRS_RECONNECT_SEED));
 	}
 }
 						 &old_state);
 	if (changed) {
 		clt_path->reconnect_attempts = 0;
+		rtrs_clt_stop_and_destroy_conns(clt_path);
 		queue_delayed_work(rtrs_wq, &clt_path->reconnect_dwork, 0);
 	}
 	if (changed || old_state == RTRS_CLT_RECONNECTING) {

drivers/infiniband/ulp/rtrs/rtrs-clt.h+1−0

@@ -134,6 +134,7 @@ struct rtrs_clt_path { · 133 unmodified lines
134	struct rtrs_clt_io_req *reqs;	134	struct rtrs_clt_io_req *reqs;
135	struct delayed_work reconnect_dwork;	135	struct delayed_work reconnect_dwork;
136	struct work_struct close_work;	136	struct work_struct close_work;
		137	struct work_struct err_recovery_work;
137	unsigned int reconnect_attempts;	138	unsigned int reconnect_attempts;
138	bool established;	139	bool established;
139	struct rtrs_rbuf *rbufs;	140	struct rtrs_rbuf *rbufs;

drivers/infiniband/ulp/rtrs/rtrs.c+0−1

@@ -479,7 +479,6 @@ static int rtrs_str_to_sockaddr(const char *addr, size_t len, · 478 unmodified lines
479	*/	479	*/
480	int sockaddr_to_str(const struct sockaddr addr, char buf, size_t len)	480	int sockaddr_to_str(const struct sockaddr addr, char buf, size_t len)
481	{	481	{
482
483	switch (addr->sa_family) {	482	switch (addr->sa_family) {
484	case AF_IB:	483	case AF_IB:
485	return scnprintf(buf, len, "gid:%pI6",	484	return scnprintf(buf, len, "gid:%pI6",

drivers/infiniband/ulp/srp/ib_srp.h+10−1

 };
 /*
+ * RDMA adapter in the initiator system.
+ *
+ * @dev_list: List of RDMA ports associated with this RDMA adapter (srp_host).
  * @mr_page_mask: HCA memory registration page mask.
  * @mr_page_size: HCA memory registration page size.
  * @mr_max_size: Maximum size in bytes of a single FR registration request.
 	bool			use_fast_reg;
 };
+/*
+ * One port of an RDMA adapter in the initiator system.
+ *
+ * @target_list: List of connected target ports (struct srp_target_port).
+ * @target_lock: Protects @target_list.
+ */
 struct srp_host {
 	struct srp_device      *srp_dev;
 	u8			port;
 };
 /**
- * struct srp_target_port
+ * struct srp_target_port - RDMA port in the SRP target system
  * @comp_vector: Completion vector used by the first RDMA channel created for
  *   this target port.
  */

Merge tag 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/rdma/rdma

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@@ -634,7 +634,7 @@ static const struct qib_hwerror_msgs qib_7220_hwerror_msgs[] = { · 633 unmodified lines
634	QLOGIC_IB_HWE_MSG(QLOGIC_IB_HWE_PCIECPLTIMEOUT,	634	QLOGIC_IB_HWE_MSG(QLOGIC_IB_HWE_PCIECPLTIMEOUT,
635	"PCIe completion timeout"),	635	"PCIe completion timeout"),
636	/*	636	/*
637	* In practice, it's unlikely wthat we'll see PCIe PLL, or bus	637	* In practice, it's unlikely that we'll see PCIe PLL, or bus
638	* parity or memory parity error failures, because most likely we	638	* parity or memory parity error failures, because most likely we
639	* won't be able to talk to the core of the chip. Nonetheless, we	639	* won't be able to talk to the core of the chip. Nonetheless, we
640	* might see them, if they are in parts of the PCIe core that aren't	640	* might see them, if they are in parts of the PCIe core that aren't
@@ -2988,7 +2988,7 @@ done: · 2347 unmodified lines
2988	* the utility. Names need to be 12 chars or less (w/o newline), for proper	2988	* the utility. Names need to be 12 chars or less (w/o newline), for proper
2989	* display by utility.	2989	* display by utility.
2990	* Non-error counters are first.	2990	* Non-error counters are first.
2991	* Start of "error" conters is indicated by a leading "E " on the first	2991	* Start of "error" counters is indicated by a leading "E " on the first
2992	* "error" counter, and doesn't count in label length.	2992	* "error" counter, and doesn't count in label length.
2993	* The EgrOvfl list needs to be last so we truncate them at the configured	2993	* The EgrOvfl list needs to be last so we truncate them at the configured
2994	* context count for the device.	2994	* context count for the device.