History

perf/x86/intel: Fix ICL/SPR INST_RETIRED.PREC_DIST encodings

This patch fixes the encoding for INST_RETIRED.PREC_DIST as published by Intel (download.01.org/perfmon/) for Icelake. The official encoding is event code 0x00 umask 0x1, a change from Skylake where it was code 0xc0 umask 0x1. With this patch applied it is possible to run: $ perf record -a -e cpu/event=0x00,umask=0x1/pp ..... Whereas before this would fail. To avoid problems with tools which may use the old code, we maintain the old encoding for Icelake.

Stephane Eranian committed 5 years ago

Commit 2de71ee1 parent 26da4ab2 files · +6 −4Browse files

Unified · Split

2 files
  1. arch/x86/events/intel/core.c +3 −2
  2. arch/x86/events/intel/ds.c +3 −2
arch/x86/events/intel/core.c+3−2
@@ -243,7 +243,8 @@ static struct extra_reg intel_skl_extra_regs[] __read_mostly = { · 242 unmodified lines
243 243
244static struct event_constraint intel_icl_event_constraints[] = {244static struct event_constraint intel_icl_event_constraints[] = {
245 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */245 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
246 FIXED_EVENT_CONSTRAINT(0x01c0, 0), /* INST_RETIRED.PREC_DIST */246 FIXED_EVENT_CONSTRAINT(0x01c0, 0), /* old INST_RETIRED.PREC_DIST */
247 FIXED_EVENT_CONSTRAINT(0x0100, 0), /* INST_RETIRED.PREC_DIST */
247 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */248 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
248 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */249 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
249 FIXED_EVENT_CONSTRAINT(0x0400, 3), /* SLOTS */250 FIXED_EVENT_CONSTRAINT(0x0400, 3), /* SLOTS */
@@ -287,7 +288,7 @@ static struct extra_reg intel_spr_extra_regs[] __read_mostly = { · 37 unmodified lines
287 288
288static struct event_constraint intel_spr_event_constraints[] = {289static struct event_constraint intel_spr_event_constraints[] = {
289 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */290 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
290 FIXED_EVENT_CONSTRAINT(0x01c0, 0), /* INST_RETIRED.PREC_DIST */291 FIXED_EVENT_CONSTRAINT(0x0100, 0), /* INST_RETIRED.PREC_DIST */
291 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */292 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
292 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */293 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
293 FIXED_EVENT_CONSTRAINT(0x0400, 3), /* SLOTS */294 FIXED_EVENT_CONSTRAINT(0x0400, 3), /* SLOTS */
arch/x86/events/intel/ds.c+3−2
@@ -923,7 +923,8 @@ struct event_constraint intel_skl_pebs_event_constraints[] = { · 922 unmodified lines
923};923};
924 924
925struct event_constraint intel_icl_pebs_event_constraints[] = {925struct event_constraint intel_icl_pebs_event_constraints[] = {
926 INTEL_FLAGS_UEVENT_CONSTRAINT(0x1c0, 0x100000000ULL), /* INST_RETIRED.PREC_DIST */926 INTEL_FLAGS_UEVENT_CONSTRAINT(0x01c0, 0x100000000ULL), /* old INST_RETIRED.PREC_DIST */
927 INTEL_FLAGS_UEVENT_CONSTRAINT(0x0100, 0x100000000ULL), /* INST_RETIRED.PREC_DIST */
927 INTEL_FLAGS_UEVENT_CONSTRAINT(0x0400, 0x800000000ULL), /* SLOTS */928 INTEL_FLAGS_UEVENT_CONSTRAINT(0x0400, 0x800000000ULL), /* SLOTS */
928 929
929 INTEL_PLD_CONSTRAINT(0x1cd, 0xff), /* MEM_TRANS_RETIRED.LOAD_LATENCY */930 INTEL_PLD_CONSTRAINT(0x1cd, 0xff), /* MEM_TRANS_RETIRED.LOAD_LATENCY */
@@ -943,7 +944,7 @@ struct event_constraint intel_icl_pebs_event_constraints[] = { · 13 unmodified lines
943};944};
944 945
945struct event_constraint intel_spr_pebs_event_constraints[] = {946struct event_constraint intel_spr_pebs_event_constraints[] = {
946 INTEL_FLAGS_UEVENT_CONSTRAINT(0x1c0, 0x100000000ULL),947 INTEL_FLAGS_UEVENT_CONSTRAINT(0x100, 0x100000000ULL), /* INST_RETIRED.PREC_DIST */
947 INTEL_FLAGS_UEVENT_CONSTRAINT(0x0400, 0x800000000ULL),948 INTEL_FLAGS_UEVENT_CONSTRAINT(0x0400, 0x800000000ULL),
948 949
949 INTEL_FLAGS_EVENT_CONSTRAINT(0xc0, 0xfe),950 INTEL_FLAGS_EVENT_CONSTRAINT(0xc0, 0xfe),