Merge tag 'x86_cleanups_for_v6.18_rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip

Pull x86 cleanups from Borislav Petkov: - Simplify inline asm flag output operands now that the minimum compiler version supports the =@ccCOND syntax - Remove a bunch of AS_* Kconfig symbols which detect assembler support for various instruction mnemonics now that the minimum assembler version supports them all - The usual cleanups all over the place * tag 'x86_cleanups_for_v6.18_rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: x86/asm: Remove code depending on __GCC_ASM_FLAG_OUTPUTS__ x86/sgx: Use ENCLS mnemonic in <kernel/cpu/sgx/encls.h> x86/mtrr: Remove license boilerplate text with bad FSF address x86/asm: Use RDPKRU and WRPKRU mnemonics in <asm/special_insns.h> x86/idle: Use MONITORX and MWAITX mnemonics in <asm/mwait.h> x86/entry/fred: Push __KERNEL_CS directly x86/kconfig: Remove CONFIG_AS_AVX512 crypto: x86 - Remove CONFIG_AS_VPCLMULQDQ crypto: X86 - Remove CONFIG_AS_VAES crypto: x86 - Remove CONFIG_AS_GFNI x86/kconfig: Drop unused and needless config X86_64_SMP

Linus Torvalds committed 1 year ago

Commit 2f0a7502 parents 6bb71f0 c6c973d34 files · +55 −239Browse files

Unified · Split

34 files

arch/x86/Kconfig +0 −4
arch/x86/Kconfig.assembler +0 −20
arch/x86/boot/bitops.h +1 −1
arch/x86/boot/boot.h +4 −4
arch/x86/boot/string.c +2 −2
arch/x86/crypto/Kconfig +1 −1
arch/x86/crypto/Makefile +2 −4
arch/x86/crypto/aes-ctr-avx-x86_64.S +0 −2
arch/x86/crypto/aes-xts-avx-x86_64.S +0 −2
arch/x86/crypto/aesni-intel_glue.c +3 −19
arch/x86/crypto/aria-aesni-avx-asm_64.S +0 −10
arch/x86/crypto/aria-aesni-avx2-asm_64.S +1 −9
arch/x86/crypto/aria_aesni_avx2_glue.c +1 −3
arch/x86/crypto/aria_aesni_avx_glue.c +1 −3
arch/x86/entry/entry_64_fred.S +1 −2
arch/x86/include/asm/archrandom.h +2 −4
arch/x86/include/asm/asm.h +0 −12
arch/x86/include/asm/bitops.h +6 −12
arch/x86/include/asm/cmpxchg.h +4 −8
arch/x86/include/asm/cmpxchg_32.h +2 −4
arch/x86/include/asm/cmpxchg_64.h +1 −2
arch/x86/include/asm/mtrr.h +1 −14
arch/x86/include/asm/mwait.h +2 −6
arch/x86/include/asm/percpu.h +4 −8
arch/x86/include/asm/rmwcc.h +2 −24
arch/x86/include/asm/sev.h +1 −2
arch/x86/include/asm/signal.h +1 −2
arch/x86/include/asm/special_insns.h +3 −7
arch/x86/include/asm/uaccess.h +3 −4
arch/x86/kernel/cpu/mtrr/cleanup.c +1 −14
arch/x86/kernel/cpu/mtrr/mtrr.c +1 −14
arch/x86/kernel/cpu/sgx/encls.h +3 −3
tools/arch/x86/include/asm/asm.h +0 −12
tools/perf/bench/find-bit-bench.c +1 −1

arch/x86/Kconfig+0−4

@@ -412,10 +412,6 @@ config HAVE_INTEL_TXT · 411 unmodified lines
412	412	def_bool y
413	413	depends on INTEL_IOMMU && ACPI
414	414
415		−config X86_64_SMP
416		− def_bool y
417		− depends on X86_64 && SMP
418		−
419	415	config ARCH_SUPPORTS_UPROBES
420	416	def_bool y
421	417

arch/x86/Kconfig.assembler+0−20

@@ -1,26 +1,6 @@
1	1	# SPDX-License-Identifier: GPL-2.0
2	2	# Copyright (C) 2020 Jason A. Donenfeld <Jason@zx2c4.com>. All Rights Reserved.
3	3
4		−config AS_AVX512
5		− def_bool $(as-instr,vpmovm2b %k1$(comma)%zmm5)
6		− help
7		− Supported by binutils >= 2.25 and LLVM integrated assembler
8		−
9		−config AS_GFNI
10		− def_bool $(as-instr,vgf2p8mulb %xmm0$(comma)%xmm1$(comma)%xmm2)
11		− help
12		− Supported by binutils >= 2.30 and LLVM integrated assembler
13		−
14		−config AS_VAES
15		− def_bool $(as-instr,vaesenc %ymm0$(comma)%ymm1$(comma)%ymm2)
16		− help
17		− Supported by binutils >= 2.30 and LLVM integrated assembler
18		−
19		−config AS_VPCLMULQDQ
20		− def_bool $(as-instr,vpclmulqdq \$0x10$(comma)%ymm0$(comma)%ymm1$(comma)%ymm2)
21		− help
22		− Supported by binutils >= 2.30 and LLVM integrated assembler
23		−
24	4	config AS_WRUSS
25	5	def_bool $(as-instr64,wrussq %rax$(comma)(%rbx))
26	6	help

arch/x86/boot/bitops.h+1−1

@@ -27,7 +27,7 @@ static inline bool variable_test_bit(int nr, const void *addr) · 26 unmodified lines
27	27	bool v;
28	28	const u32 *p = addr;
29	29
30		− asm("btl %2,%1" CC_SET(c) : CC_OUT(c) (v) : "m" (*p), "Ir" (nr));
	30	+ asm("btl %2,%1" : "=@ccc" (v) : "m" (*p), "Ir" (nr));
31	31	return v;
32	32	}
33	33

arch/x86/boot/boot.h+4−4

@@ -155,15 +155,15 @@ static inline void wrgs32(u32 v, addr_t addr) · 154 unmodified lines
155	155	static inline bool memcmp_fs(const void *s1, addr_t s2, size_t len)
156	156	{
157	157	bool diff;
158		− asm volatile("fs repe cmpsb" CC_SET(nz)
159		− : CC_OUT(nz) (diff), "+D" (s1), "+S" (s2), "+c" (len));
	158	+ asm volatile("fs repe cmpsb"
	159	+ : "=@ccnz" (diff), "+D" (s1), "+S" (s2), "+c" (len));
160	160	return diff;
161	161	}
162	162	static inline bool memcmp_gs(const void *s1, addr_t s2, size_t len)
163	163	{
164	164	bool diff;
165		− asm volatile("gs repe cmpsb" CC_SET(nz)
166		− : CC_OUT(nz) (diff), "+D" (s1), "+S" (s2), "+c" (len));
	165	+ asm volatile("gs repe cmpsb"
	166	+ : "=@ccnz" (diff), "+D" (s1), "+S" (s2), "+c" (len));
167	167	return diff;
168	168	}
169	169

arch/x86/boot/string.c+2−2

@@ -32,8 +32,8 @@ · 31 unmodified lines
32	32	int memcmp(const void s1, const void s2, size_t len)
33	33	{
34	34	bool diff;
35		− asm("repe cmpsb" CC_SET(nz)
36		− : CC_OUT(nz) (diff), "+D" (s1), "+S" (s2), "+c" (len));
	35	+ asm("repe cmpsb"
	36	+ : "=@ccnz" (diff), "+D" (s1), "+S" (s2), "+c" (len));
37	37	return diff;
38	38	}
39	39

arch/x86/crypto/Kconfig+1−1

@@ -306,7 +306,7 @@ config CRYPTO_ARIA_AESNI_AVX2_X86_64 · 305 unmodified lines
306	306
307	307	config CRYPTO_ARIA_GFNI_AVX512_X86_64
308	308	tristate "Ciphers: ARIA with modes: ECB, CTR (AVX512/GFNI)"
309		− depends on 64BIT && AS_GFNI
	309	+ depends on 64BIT
310	310	select CRYPTO_SKCIPHER
311	311	select CRYPTO_ALGAPI
312	312	select CRYPTO_ARIA

arch/x86/crypto/Makefile+2−4

@@ -46,10 +46,8 @@ obj-$(CONFIG_CRYPTO_AES_NI_INTEL) += aesni-intel.o · 45 unmodified lines
46	46	aesni-intel-y := aesni-intel_asm.o aesni-intel_glue.o
47	47	aesni-intel-$(CONFIG_64BIT) += aes-ctr-avx-x86_64.o \
48	48	aes-gcm-aesni-x86_64.o \
49		− aes-xts-avx-x86_64.o
50		−ifeq ($(CONFIG_AS_VAES)$(CONFIG_AS_VPCLMULQDQ),yy)
51		−aesni-intel-$(CONFIG_64BIT) += aes-gcm-avx10-x86_64.o
52		−endif
	49	+ aes-xts-avx-x86_64.o \
	50	+ aes-gcm-avx10-x86_64.o
53	51
54	52	obj-$(CONFIG_CRYPTO_GHASH_CLMUL_NI_INTEL) += ghash-clmulni-intel.o
55	53	ghash-clmulni-intel-y := ghash-clmulni-intel_asm.o ghash-clmulni-intel_glue.o

arch/x86/crypto/aes-ctr-avx-x86_64.S+0−2

@@ -552,7 +552,6 @@ SYM_TYPED_FUNC_START(aes_xctr_crypt_aesni_avx) · 551 unmodified lines
552	552	_aes_ctr_crypt 1
553	553	SYM_FUNC_END(aes_xctr_crypt_aesni_avx)
554	554
555		−#if defined(CONFIG_AS_VAES) && defined(CONFIG_AS_VPCLMULQDQ)
556	555	.set VL, 32
557	556	.set USE_AVX512, 0
558	557	SYM_TYPED_FUNC_START(aes_ctr64_crypt_vaes_avx2)
@@ -570,4 +569,3 @@ SYM_FUNC_END(aes_ctr64_crypt_vaes_avx512) · 11 unmodified lines
570	569	SYM_TYPED_FUNC_START(aes_xctr_crypt_vaes_avx512)
571	570	_aes_ctr_crypt 1
572	571	SYM_FUNC_END(aes_xctr_crypt_vaes_avx512)
573		−#endif // CONFIG_AS_VAES && CONFIG_AS_VPCLMULQDQ

arch/x86/crypto/aes-xts-avx-x86_64.S+0−2

@@ -886,7 +886,6 @@ SYM_TYPED_FUNC_START(aes_xts_decrypt_aesni_avx) · 885 unmodified lines
886	886	_aes_xts_crypt 0
887	887	SYM_FUNC_END(aes_xts_decrypt_aesni_avx)
888	888
889		−#if defined(CONFIG_AS_VAES) && defined(CONFIG_AS_VPCLMULQDQ)
890	889	.set VL, 32
891	890	.set USE_AVX512, 0
892	891	SYM_TYPED_FUNC_START(aes_xts_encrypt_vaes_avx2)
@@ -904,4 +903,3 @@ SYM_FUNC_END(aes_xts_encrypt_vaes_avx512) · 11 unmodified lines
904	903	SYM_TYPED_FUNC_START(aes_xts_decrypt_vaes_avx512)
905	904	_aes_xts_crypt 0
906	905	SYM_FUNC_END(aes_xts_decrypt_vaes_avx512)
907		−#endif /* CONFIG_AS_VAES && CONFIG_AS_VPCLMULQDQ */

arch/x86/crypto/aesni-intel_glue.c+3−19

@@ -828,10 +828,8 @@ static struct skcipher_alg skcipher_algs_##suffix[] = {{ \ · 827 unmodified lines
828	828	}}
829	829
830	830	DEFINE_AVX_SKCIPHER_ALGS(aesni_avx, "aesni-avx", 500);
831		−#if defined(CONFIG_AS_VAES) && defined(CONFIG_AS_VPCLMULQDQ)
832	831	DEFINE_AVX_SKCIPHER_ALGS(vaes_avx2, "vaes-avx2", 600);
833	832	DEFINE_AVX_SKCIPHER_ALGS(vaes_avx512, "vaes-avx512", 800);
834		−#endif
835	833
836	834	/* The common part of the x86_64 AES-GCM key struct */
837	835	struct aes_gcm_key {
@@ -912,17 +910,8 @@ struct aes_gcm_key_avx10 { · 74 unmodified lines
912	910	#define FLAG_RFC4106 BIT(0)
913	911	#define FLAG_ENC BIT(1)
914	912	#define FLAG_AVX BIT(2)
915		−#if defined(CONFIG_AS_VAES) && defined(CONFIG_AS_VPCLMULQDQ)
916		−# define FLAG_AVX10_256 BIT(3)
917		−# define FLAG_AVX10_512 BIT(4)
918		−#else
919		− /*
920		− * This should cause all calls to the AVX10 assembly functions to be
921		− * optimized out, avoiding the need to ifdef each call individually.
922		− */
923		−# define FLAG_AVX10_256 0
924		−# define FLAG_AVX10_512 0
925		−#endif
	913	+#define FLAG_AVX10_256 BIT(3)
	914	+#define FLAG_AVX10_512 BIT(4)
926	915
927	916	static inline struct aes_gcm_key *
928	917	aes_gcm_key_get(struct crypto_aead *tfm, int flags)
@@ -1519,7 +1508,6 @@ DEFINE_GCM_ALGS(aesni_avx, FLAG_AVX, · 590 unmodified lines
1519	1508	"generic-gcm-aesni-avx", "rfc4106-gcm-aesni-avx",
1520	1509	AES_GCM_KEY_AESNI_SIZE, 500);
1521	1510
1522		−#if defined(CONFIG_AS_VAES) && defined(CONFIG_AS_VPCLMULQDQ)
1523	1511	/* aes_gcm_algs_vaes_avx10_256 */
1524	1512	DEFINE_GCM_ALGS(vaes_avx10_256, FLAG_AVX10_256,
1525	1513	"generic-gcm-vaes-avx10_256", "rfc4106-gcm-vaes-avx10_256",
@@ -1529,7 +1517,6 @@ DEFINE_GCM_ALGS(vaes_avx10_256, FLAG_AVX10_256, · 3 unmodified lines
1529	1517	DEFINE_GCM_ALGS(vaes_avx10_512, FLAG_AVX10_512,
1530	1518	"generic-gcm-vaes-avx10_512", "rfc4106-gcm-vaes-avx10_512",
1531	1519	AES_GCM_KEY_AVX10_SIZE, 800);
1532		−#endif /* CONFIG_AS_VAES && CONFIG_AS_VPCLMULQDQ */
1533	1520
1534	1521	static int __init register_avx_algs(void)
1535	1522	{
@@ -1551,7 +1538,6 @@ static int __init register_avx_algs(void) · 15 unmodified lines
1551	1538	* Similarly, the assembler support was added at about the same time.
1552	1539	* For simplicity, just always check for VAES and VPCLMULQDQ together.
1553	1540	*/
1554		−#if defined(CONFIG_AS_VAES) && defined(CONFIG_AS_VPCLMULQDQ)
1555	1541	if (!boot_cpu_has(X86_FEATURE_AVX2) \|\|
1556	1542	!boot_cpu_has(X86_FEATURE_VAES) \|\|
1557	1543	!boot_cpu_has(X86_FEATURE_VPCLMULQDQ) \|\|
@@ -1592,7 +1578,7 @@ static int __init register_avx_algs(void) · 34 unmodified lines
1592	1578	ARRAY_SIZE(aes_gcm_algs_vaes_avx10_512));
1593	1579	if (err)
1594	1580	return err;
1595		−#endif /* CONFIG_AS_VAES && CONFIG_AS_VPCLMULQDQ */
	1581	+
1596	1582	return 0;
1597	1583	}
1598	1584
@@ -1607,12 +1593,10 @@ static void unregister_avx_algs(void) · 8 unmodified lines
1607	1593	{
1608	1594	unregister_skciphers(skcipher_algs_aesni_avx);
1609	1595	unregister_aeads(aes_gcm_algs_aesni_avx);
1610		−#if defined(CONFIG_AS_VAES) && defined(CONFIG_AS_VPCLMULQDQ)
1611	1596	unregister_skciphers(skcipher_algs_vaes_avx2);
1612	1597	unregister_skciphers(skcipher_algs_vaes_avx512);
1613	1598	unregister_aeads(aes_gcm_algs_vaes_avx10_256);
1614	1599	unregister_aeads(aes_gcm_algs_vaes_avx10_512);
1615		−#endif
1616	1600	}
1617	1601	#else /* CONFIG_X86_64 */
1618	1602	static struct aead_alg aes_gcm_algs_aesni[0];

arch/x86/crypto/aria-aesni-avx-asm_64.S+0−10

@@ -295,7 +295,6 @@ · 294 unmodified lines
295	295	vpshufb t1, t0, t2; \
296	296	vpxor t2, x7, x7;
297	297
298		−#ifdef CONFIG_AS_GFNI
299	298	#define aria_sbox_8way_gfni(x0, x1, x2, x3, \
300	299	x4, x5, x6, x7, \
301	300	t0, t1, t2, t3, \
@@ -318,8 +317,6 @@ · 16 unmodified lines
318	317	vgf2p8affineinvqb $0, t2, x3, x3; \
319	318	vgf2p8affineinvqb $0, t2, x7, x7
320	319
321		−#endif /* CONFIG_AS_GFNI */
322		−
323	320	#define aria_sbox_8way(x0, x1, x2, x3, \
324	321	x4, x5, x6, x7, \
325	322	t0, t1, t2, t3, \
@@ -561,7 +558,6 @@ · 235 unmodified lines
561	558	y4, y5, y6, y7, \
562	559	mem_tmp, 8);
563	560
564		−#ifdef CONFIG_AS_GFNI
565	561	#define aria_fe_gfni(x0, x1, x2, x3, \
566	562	x4, x5, x6, x7, \
567	563	y0, y1, y2, y3, \
@@ -719,8 +715,6 @@ · 151 unmodified lines
719	715	y4, y5, y6, y7, \
720	716	mem_tmp, 8);
721	717
722		−#endif /* CONFIG_AS_GFNI */
723		−
724	718	/* NB: section is mergeable, all elements must be aligned 16-byte blocks */
725	719	.section .rodata.cst16, "aM", @progbits, 16
726	720	.align 16
@@ -772,7 +766,6 @@ · 45 unmodified lines
772	766	.Ltf_hi__x2__and__fwd_aff:
773	767	.octa 0x3F893781E95FE1576CDA64D2BA0CB204
774	768
775		−#ifdef CONFIG_AS_GFNI
776	769	/* AES affine: */
777	770	#define tf_aff_const BV8(1, 1, 0, 0, 0, 1, 1, 0)
778	771	.Ltf_aff_bitmatrix:
@@ -871,7 +864,6 @@ · 92 unmodified lines
871	864	BV8(0, 0, 0, 0, 0, 1, 0, 0),
872	865	BV8(0, 0, 0, 0, 0, 0, 1, 0),
873	866	BV8(0, 0, 0, 0, 0, 0, 0, 1))
874		−#endif /* CONFIG_AS_GFNI */
875	867
876	868	/* 4-bit mask */
877	869	.section .rodata.cst4.L0f0f0f0f, "aM", @progbits, 4
@@ -1140,7 +1132,6 @@ SYM_TYPED_FUNC_START(aria_aesni_avx_ctr_crypt_16way) · 262 unmodified lines
1140	1132	RET;
1141	1133	SYM_FUNC_END(aria_aesni_avx_ctr_crypt_16way)
1142	1134
1143		−#ifdef CONFIG_AS_GFNI
1144	1135	SYM_FUNC_START_LOCAL(__aria_aesni_avx_gfni_crypt_16way)
1145	1136	/* input:
1146	1137	* %r9: rk
@@ -1359,4 +1350,3 @@ SYM_TYPED_FUNC_START(aria_aesni_avx_gfni_ctr_crypt_16way) · 212 unmodified lines
1359	1350	FRAME_END
1360	1351	RET;
1361	1352	SYM_FUNC_END(aria_aesni_avx_gfni_ctr_crypt_16way)
1362		−#endif /* CONFIG_AS_GFNI */

arch/x86/crypto/aria-aesni-avx2-asm_64.S+1−9

@@ -302,7 +302,6 @@ · 301 unmodified lines
302	302	vpbroadcastb ((round * 16) + idx + 4)(rk), t0; \
303	303	vpxor t0, x7, x7;
304	304
305		−#ifdef CONFIG_AS_GFNI
306	305	#define aria_sbox_8way_gfni(x0, x1, x2, x3, \
307	306	x4, x5, x6, x7, \
308	307	t0, t1, t2, t3, \
@@ -325,7 +324,6 @@ · 16 unmodified lines
325	324	vgf2p8affineinvqb $0, t2, x3, x3; \
326	325	vgf2p8affineinvqb $0, t2, x7, x7
327	326
328		−#endif /* CONFIG_AS_GFNI */
329	327	#define aria_sbox_8way(x0, x1, x2, x3, \
330	328	x4, x5, x6, x7, \
331	329	t0, t1, t2, t3, \
@@ -598,7 +596,7 @@ · 266 unmodified lines
598	596	aria_load_state_8way(y0, y1, y2, y3, \
599	597	y4, y5, y6, y7, \
600	598	mem_tmp, 8);
601		−#ifdef CONFIG_AS_GFNI
	599	+
602	600	#define aria_fe_gfni(x0, x1, x2, x3, \
603	601	x4, x5, x6, x7, \
604	602	y0, y1, y2, y3, \
@@ -752,7 +750,6 @@ · 147 unmodified lines
752	750	aria_load_state_8way(y0, y1, y2, y3, \
753	751	y4, y5, y6, y7, \
754	752	mem_tmp, 8);
755		−#endif /* CONFIG_AS_GFNI */
756	753
757	754	.section .rodata.cst32.shufb_16x16b, "aM", @progbits, 32
758	755	.align 32
@@ -806,7 +803,6 @@ · 47 unmodified lines
806	803	.Ltf_hi__x2__and__fwd_aff:
807	804	.octa 0x3F893781E95FE1576CDA64D2BA0CB204
808	805
809		−#ifdef CONFIG_AS_GFNI
810	806	.section .rodata.cst8, "aM", @progbits, 8
811	807	.align 8
812	808	/* AES affine: */
@@ -868,8 +864,6 @@ · 55 unmodified lines
868	864	BV8(0, 0, 0, 0, 0, 0, 1, 0),
869	865	BV8(0, 0, 0, 0, 0, 0, 0, 1))
870	866
871		−#endif /* CONFIG_AS_GFNI */
872		−
873	867	/* 4-bit mask */
874	868	.section .rodata.cst4.L0f0f0f0f, "aM", @progbits, 4
875	869	.align 4
@@ -1219,7 +1213,6 @@ SYM_TYPED_FUNC_START(aria_aesni_avx2_ctr_crypt_32way) · 343 unmodified lines
1219	1213	RET;
1220	1214	SYM_FUNC_END(aria_aesni_avx2_ctr_crypt_32way)
1221	1215
1222		−#ifdef CONFIG_AS_GFNI
1223	1216	SYM_FUNC_START_LOCAL(__aria_aesni_avx2_gfni_crypt_32way)
1224	1217	/* input:
1225	1218	* %r9: rk
@@ -1438,4 +1431,3 @@ SYM_TYPED_FUNC_START(aria_aesni_avx2_gfni_ctr_crypt_32way) · 212 unmodified lines
1438	1431	FRAME_END
1439	1432	RET;
1440	1433	SYM_FUNC_END(aria_aesni_avx2_gfni_ctr_crypt_32way)
1441		−#endif /* CONFIG_AS_GFNI */

arch/x86/crypto/aria_aesni_avx2_glue.c+1−3

@@ -26,7 +26,6 @@ asmlinkage void aria_aesni_avx2_ctr_crypt_32way(const void ctx, u8 dst, · 25 unmodified lines
26	26	const u8 *src,
27	27	u8 keystream, u8 iv);
28	28	EXPORT_SYMBOL_GPL(aria_aesni_avx2_ctr_crypt_32way);
29		−#ifdef CONFIG_AS_GFNI
30	29	asmlinkage void aria_aesni_avx2_gfni_encrypt_32way(const void ctx, u8 dst,
31	30	const u8 *src);
32	31	EXPORT_SYMBOL_GPL(aria_aesni_avx2_gfni_encrypt_32way);
@@ -37,7 +36,6 @@ asmlinkage void aria_aesni_avx2_gfni_ctr_crypt_32way(const void ctx, u8 dst, · 4 unmodified lines
37	36	const u8 *src,
38	37	u8 keystream, u8 iv);
39	38	EXPORT_SYMBOL_GPL(aria_aesni_avx2_gfni_ctr_crypt_32way);
40		−#endif /* CONFIG_AS_GFNI */
41	39
42	40	static struct aria_avx_ops aria_ops;
43	41
@@ -213,7 +211,7 @@ static int __init aria_avx2_init(void) · 169 unmodified lines
213	211	return -ENODEV;
214	212	}
215	213
216		− if (boot_cpu_has(X86_FEATURE_GFNI) && IS_ENABLED(CONFIG_AS_GFNI)) {
	214	+ if (boot_cpu_has(X86_FEATURE_GFNI)) {
217	215	aria_ops.aria_encrypt_16way = aria_aesni_avx_gfni_encrypt_16way;
218	216	aria_ops.aria_decrypt_16way = aria_aesni_avx_gfni_decrypt_16way;
219	217	aria_ops.aria_ctr_crypt_16way = aria_aesni_avx_gfni_ctr_crypt_16way;

arch/x86/crypto/aria_aesni_avx_glue.c+1−3

@@ -26,7 +26,6 @@ asmlinkage void aria_aesni_avx_ctr_crypt_16way(const void ctx, u8 dst, · 25 unmodified lines
26	26	const u8 *src,
27	27	u8 keystream, u8 iv);
28	28	EXPORT_SYMBOL_GPL(aria_aesni_avx_ctr_crypt_16way);
29		−#ifdef CONFIG_AS_GFNI
30	29	asmlinkage void aria_aesni_avx_gfni_encrypt_16way(const void ctx, u8 dst,
31	30	const u8 *src);
32	31	EXPORT_SYMBOL_GPL(aria_aesni_avx_gfni_encrypt_16way);
@@ -37,7 +36,6 @@ asmlinkage void aria_aesni_avx_gfni_ctr_crypt_16way(const void ctx, u8 dst, · 4 unmodified lines
37	36	const u8 *src,
38	37	u8 keystream, u8 iv);
39	38	EXPORT_SYMBOL_GPL(aria_aesni_avx_gfni_ctr_crypt_16way);
40		−#endif /* CONFIG_AS_GFNI */
41	39
42	40	static struct aria_avx_ops aria_ops;
43	41
@@ -199,7 +197,7 @@ static int __init aria_avx_init(void) · 155 unmodified lines
199	197	return -ENODEV;
200	198	}
201	199
202		− if (boot_cpu_has(X86_FEATURE_GFNI) && IS_ENABLED(CONFIG_AS_GFNI)) {
	200	+ if (boot_cpu_has(X86_FEATURE_GFNI)) {
203	201	aria_ops.aria_encrypt_16way = aria_aesni_avx_gfni_encrypt_16way;
204	202	aria_ops.aria_decrypt_16way = aria_aesni_avx_gfni_decrypt_16way;
205	203	aria_ops.aria_ctr_crypt_16way = aria_aesni_avx_gfni_ctr_crypt_16way;

arch/x86/entry/entry_64_fred.S+1−2

@@ -97,8 +97,7 @@ SYM_FUNC_START(asm_fred_entry_from_kvm) · 96 unmodified lines
97	97	push %rdi /* fred_ss handed in by the caller */
98	98	push %rbp
99	99	pushf
100		− mov $__KERNEL_CS, %rax
101		− push %rax
	100	+ push $__KERNEL_CS
102	101
103	102	/*
104	103	* Unlike the IDT event delivery, FRED _always_ pushes an error code

arch/x86/include/asm/archrandom.h+2−4

@@ -23,8 +23,7 @@ static inline bool __must_check rdrand_long(unsigned long *v) · 22 unmodified lines
23	23	unsigned int retry = RDRAND_RETRY_LOOPS;
24	24	do {
25	25	asm volatile("rdrand %[out]"
26		− CC_SET(c)
27		− : CC_OUT(c) (ok), [out] "=r" (*v));
	26	+ : "=@ccc" (ok), [out] "=r" (*v));
28	27	if (ok)
29	28	return true;
30	29	} while (--retry);
@@ -35,8 +34,7 @@ static inline bool __must_check rdseed_long(unsigned long *v) · 4 unmodified lines
35	34	{
36	35	bool ok;
37	36	asm volatile("rdseed %[out]"
38		− CC_SET(c)
39		− : CC_OUT(c) (ok), [out] "=r" (*v));
	37	+ : "=@ccc" (ok), [out] "=r" (*v));
40	38	return ok;
41	39	}
42	40

arch/x86/include/asm/asm.h+0−12

@@ -122,18 +122,6 @@ static __always_inline __pure void rip_rel_ptr(void p) · 121 unmodified lines
122	122	}
123	123	#endif
124	124
125		−/*
126		− * Macros to generate condition code outputs from inline assembly,
127		− * The output operand must be type "bool".
128		− */
129		−#ifdef __GCC_ASM_FLAG_OUTPUTS__
130		−# define CC_SET(c) "\n\t/* output condition code " #c "*/\n"
131		−# define CC_OUT(c) "=@cc" #c
132		−#else
133		−# define CC_SET(c) "\n\tset" #c " %[_cc_" #c "]\n"
134		−# define CC_OUT(c) [_cc_ ## c] "=qm"
135		−#endif
136		−
137	125	#ifdef __KERNEL__
138	126
139	127	# include <asm/extable_fixup_types.h>

arch/x86/include/asm/bitops.h+6−12

@@ -99,8 +99,7 @@ static __always_inline bool arch_xor_unlock_is_negative_byte(unsigned long mask, · 98 unmodified lines
99	99	{
100	100	bool negative;
101	101	asm_inline volatile(LOCK_PREFIX "xorb %2,%1"
102		− CC_SET(s)
103		− : CC_OUT(s) (negative), WBYTE_ADDR(addr)
	102	+ : "=@ccs" (negative), WBYTE_ADDR(addr)
104	103	: "iq" ((char)mask) : "memory");
105	104	return negative;
106	105	}
@@ -149,8 +148,7 @@ arch___test_and_set_bit(unsigned long nr, volatile unsigned long *addr) · 42 unmodified lines
149	148	bool oldbit;
150	149
151	150	asm(__ASM_SIZE(bts) " %2,%1"
152		− CC_SET(c)
153		− : CC_OUT(c) (oldbit)
	151	+ : "=@ccc" (oldbit)
154	152	: ADDR, "Ir" (nr) : "memory");
155	153	return oldbit;
156	154	}
@@ -175,8 +173,7 @@ arch___test_and_clear_bit(unsigned long nr, volatile unsigned long *addr) · 18 unmodified lines
175	173	bool oldbit;
176	174
177	175	asm volatile(__ASM_SIZE(btr) " %2,%1"
178		− CC_SET(c)
179		− : CC_OUT(c) (oldbit)
	176	+ : "=@ccc" (oldbit)
180	177	: ADDR, "Ir" (nr) : "memory");
181	178	return oldbit;
182	179	}
@@ -187,8 +184,7 @@ arch___test_and_change_bit(unsigned long nr, volatile unsigned long *addr) · 4 unmodified lines
187	184	bool oldbit;
188	185
189	186	asm volatile(__ASM_SIZE(btc) " %2,%1"
190		− CC_SET(c)
191		− : CC_OUT(c) (oldbit)
	187	+ : "=@ccc" (oldbit)
192	188	: ADDR, "Ir" (nr) : "memory");
193	189
194	190	return oldbit;
@@ -211,8 +207,7 @@ static __always_inline bool constant_test_bit_acquire(long nr, const volatile un · 16 unmodified lines
211	207	bool oldbit;
212	208
213	209	asm volatile("testb %2,%1"
214		− CC_SET(nz)
215		− : CC_OUT(nz) (oldbit)
	210	+ : "=@ccnz" (oldbit)
216	211	: "m" (((unsigned char *)addr)[nr >> 3]),
217	212	"i" (1 << (nr & 7))
218	213	:"memory");
@@ -225,8 +220,7 @@ static __always_inline bool variable_test_bit(long nr, volatile const unsigned l · 6 unmodified lines
225	220	bool oldbit;
226	221
227	222	asm volatile(__ASM_SIZE(bt) " %2,%1"
228		− CC_SET(c)
229		− : CC_OUT(c) (oldbit)
	223	+ : "=@ccc" (oldbit)
230	224	: "m" ((unsigned long )addr), "Ir" (nr) : "memory");
231	225
232	226	return oldbit;

arch/x86/include/asm/cmpxchg.h+4−8

@@ -166,8 +166,7 @@ extern void __add_wrong_size(void) · 165 unmodified lines
166	166	{ \
167	167	volatile u8 __ptr = (volatile u8 )(_ptr); \
168	168	asm_inline volatile(lock "cmpxchgb %[new], %[ptr]" \
169		− CC_SET(z) \
170		− : CC_OUT(z) (success), \
	169	+ : "=@ccz" (success), \
171	170	[ptr] "+m" (*__ptr), \
172	171	[old] "+a" (__old) \
173	172	: [new] "q" (__new) \
@@ -178,8 +177,7 @@ extern void __add_wrong_size(void) · 4 unmodified lines
178	177	{ \
179	178	volatile u16 __ptr = (volatile u16 )(_ptr); \
180	179	asm_inline volatile(lock "cmpxchgw %[new], %[ptr]" \
181		− CC_SET(z) \
182		− : CC_OUT(z) (success), \
	180	+ : "=@ccz" (success), \
183	181	[ptr] "+m" (*__ptr), \
184	182	[old] "+a" (__old) \
185	183	: [new] "r" (__new) \
@@ -190,8 +188,7 @@ extern void __add_wrong_size(void) · 4 unmodified lines
190	188	{ \
191	189	volatile u32 __ptr = (volatile u32 )(_ptr); \
192	190	asm_inline volatile(lock "cmpxchgl %[new], %[ptr]" \
193		− CC_SET(z) \
194		− : CC_OUT(z) (success), \
	191	+ : "=@ccz" (success), \
195	192	[ptr] "+m" (*__ptr), \
196	193	[old] "+a" (__old) \
197	194	: [new] "r" (__new) \
@@ -202,8 +199,7 @@ extern void __add_wrong_size(void) · 4 unmodified lines
202	199	{ \
203	200	volatile u64 __ptr = (volatile u64 )(_ptr); \
204	201	asm_inline volatile(lock "cmpxchgq %[new], %[ptr]" \
205		− CC_SET(z) \
206		− : CC_OUT(z) (success), \
	202	+ : "=@ccz" (success), \
207	203	[ptr] "+m" (*__ptr), \
208	204	[old] "+a" (__old) \
209	205	: [new] "r" (__new) \

arch/x86/include/asm/cmpxchg_32.h+2−4

@@ -46,8 +46,7 @@ static __always_inline u64 __cmpxchg64_local(volatile u64 *ptr, u64 old, u64 new · 45 unmodified lines
46	46	bool ret; \
47	47	\
48	48	asm_inline volatile(_lock "cmpxchg8b %[ptr]" \
49		− CC_SET(e) \
50		− : CC_OUT(e) (ret), \
	49	+ : "=@ccz" (ret), \
51	50	[ptr] "+m" (*(_ptr)), \
52	51	"+a" (o.low), "+d" (o.high) \
53	52	: "b" (n.low), "c" (n.high) \
@@ -125,8 +124,7 @@ static __always_inline u64 arch_cmpxchg64_local(volatile u64 *ptr, u64 old, u64 · 71 unmodified lines
125	124	ALTERNATIVE(_lock_loc \
126	125	"call cmpxchg8b_emu", \
127	126	_lock "cmpxchg8b %a[ptr]", X86_FEATURE_CX8) \
128		− CC_SET(e) \
129		− : ALT_OUTPUT_SP(CC_OUT(e) (ret), \
	127	+ : ALT_OUTPUT_SP("=@ccz" (ret), \
130	128	"+a" (o.low), "+d" (o.high)) \
131	129	: "b" (n.low), "c" (n.high), \
132	130	[ptr] "S" (_ptr) \

arch/x86/include/asm/cmpxchg_64.h+1−2

@@ -66,8 +66,7 @@ static __always_inline u128 arch_cmpxchg128_local(volatile u128 *ptr, u128 old, · 65 unmodified lines
66	66	bool ret; \
67	67	\
68	68	asm_inline volatile(_lock "cmpxchg16b %[ptr]" \
69		− CC_SET(e) \
70		− : CC_OUT(e) (ret), \
	69	+ : "=@ccz" (ret), \
71	70	[ptr] "+m" (*(_ptr)), \
72	71	"+a" (o.low), "+d" (o.high) \
73	72	: "b" (n.low), "c" (n.high) \

arch/x86/include/asm/mtrr.h+1−14

@@ -1,21 +1,8 @@
	1	+/* SPDX-License-Identifier: LGPL-2.0+ */
1	2	/* Generic MTRR (Memory Type Range Register) ioctls.
2	3
3	4	Copyright (C) 1997-1999 Richard Gooch
4	5
5		− This library is free software; you can redistribute it and/or
6		− modify it under the terms of the GNU Library General Public
7		− License as published by the Free Software Foundation; either
8		− version 2 of the License, or (at your option) any later version.
9		−
10		− This library is distributed in the hope that it will be useful,
11		− but WITHOUT ANY WARRANTY; without even the implied warranty of
12		− MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
13		− Library General Public License for more details.
14		−
15		− You should have received a copy of the GNU Library General Public
16		− License along with this library; if not, write to the Free
17		− Software Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
18		−
19	6	Richard Gooch may be reached by email at rgooch@atnf.csiro.au
20	7	The postal address is:
21	8	Richard Gooch, c/o ATNF, P. O. Box 76, Epping, N.S.W., 2121, Australia.

arch/x86/include/asm/mwait.h+2−6

@@ -36,9 +36,7 @@ static __always_inline void __monitor(const void *eax, u32 ecx, u32 edx) · 35 unmodified lines
36	36
37	37	static __always_inline void __monitorx(const void *eax, u32 ecx, u32 edx)
38	38	{
39		− /* "monitorx %eax, %ecx, %edx" */
40		− asm volatile(".byte 0x0f, 0x01, 0xfa"
41		− :: "a" (eax), "c" (ecx), "d"(edx));
	39	+ asm volatile("monitorx" :: "a" (eax), "c" (ecx), "d"(edx));
42	40	}
43	41
44	42	static __always_inline void __mwait(u32 eax, u32 ecx)
@@ -80,9 +78,7 @@ static __always_inline void __mwaitx(u32 eax, u32 ebx, u32 ecx) · 35 unmodified lines
80	78	{
81	79	/* No need for TSA buffer clearing on AMD */
82	80
83		− /* "mwaitx %eax, %ebx, %ecx" */
84		− asm volatile(".byte 0x0f, 0x01, 0xfb"
85		− :: "a" (eax), "b" (ebx), "c" (ecx));
	81	+ asm volatile("mwaitx" :: "a" (eax), "b" (ebx), "c" (ecx));
86	82	}
87	83
88	84	/*

arch/x86/include/asm/percpu.h+4−8

@@ -309,8 +309,7 @@ do { \ · 308 unmodified lines
309	309	\
310	310	asm qual (__pcpu_op_##size("cmpxchg") "%[nval], " \
311	311	__percpu_arg([var]) \
312		− CC_SET(z) \
313		− : CC_OUT(z) (success), \
	312	+ : "=@ccz" (success), \
314	313	[oval] "+a" (pco_old__), \
315	314	[var] "+m" (__my_cpu_var(_var)) \
316	315	: [nval] __pcpu_reg_##size(, pco_new__) \
@@ -367,8 +366,7 @@ do { \ · 50 unmodified lines
367	366	asm_inline qual ( \
368	367	ALTERNATIVE("call this_cpu_cmpxchg8b_emu", \
369	368	"cmpxchg8b " __percpu_arg([var]), X86_FEATURE_CX8) \
370		− CC_SET(z) \
371		− : ALT_OUTPUT_SP(CC_OUT(z) (success), \
	369	+ : ALT_OUTPUT_SP("=@ccz" (success), \
372	370	[var] "+m" (__my_cpu_var(_var)), \
373	371	"+a" (old__.low), "+d" (old__.high)) \
374	372	: "b" (new__.low), "c" (new__.high), \
@@ -436,8 +434,7 @@ do { \ · 61 unmodified lines
436	434	asm_inline qual ( \
437	435	ALTERNATIVE("call this_cpu_cmpxchg16b_emu", \
438	436	"cmpxchg16b " __percpu_arg([var]), X86_FEATURE_CX16) \
439		− CC_SET(z) \
440		− : ALT_OUTPUT_SP(CC_OUT(z) (success), \
	437	+ : ALT_OUTPUT_SP("=@ccz" (success), \
441	438	[var] "+m" (__my_cpu_var(_var)), \
442	439	"+a" (old__.low), "+d" (old__.high)) \
443	440	: "b" (new__.low), "c" (new__.high), \
@@ -585,8 +582,7 @@ do { \ · 141 unmodified lines
585	582	bool oldbit; \
586	583	\
587	584	asm volatile("btl %[nr], " __percpu_arg([var]) \
588		− CC_SET(c) \
589		− : CC_OUT(c) (oldbit) \
	585	+ : "=@ccc" (oldbit) \
590	586	: [var] "m" (__my_cpu_var(_var)), \
591	587	[nr] "rI" (_nr)); \
592	588	oldbit; \

arch/x86/include/asm/rmwcc.h+2−24

@@ -6,37 +6,15 @@ · 5 unmodified lines
6	6
7	7	#define __CLOBBERS_MEM(clb...) "memory", ## clb
8	8
9		−#ifndef __GCC_ASM_FLAG_OUTPUTS__
10		−
11		−/* Use asm goto */
12		−
13		−#define __GEN_RMWcc(fullop, _var, cc, clobbers, ...) \
14		−({ \
15		− bool c = false; \
16		− asm goto (fullop "; j" #cc " %l[cc_label]" \
17		− : : [var] "m" (_var), ## __VA_ARGS__ \
18		− : clobbers : cc_label); \
19		− if (0) { \
20		−cc_label: c = true; \
21		− } \
22		− c; \
23		−})
24		−
25		−#else /* defined(__GCC_ASM_FLAG_OUTPUTS__) */
26		−
27		−/* Use flags output or a set instruction */
28		−
29	9	#define __GEN_RMWcc(fullop, _var, cc, clobbers, ...) \
30	10	({ \
31	11	bool c; \
32		− asm_inline volatile (fullop CC_SET(cc) \
33		− : [var] "+m" (_var), CC_OUT(cc) (c) \
	12	+ asm_inline volatile (fullop \
	13	+ : [var] "+m" (_var), "=@cc" #cc (c) \
34	14	: __VA_ARGS__ : clobbers); \
35	15	c; \
36	16	})
37	17
38		−#endif /* defined(__GCC_ASM_FLAG_OUTPUTS__) */
39		−
40	18	#define GEN_UNARY_RMWcc_4(op, var, cc, arg0) \
41	19	__GEN_RMWcc(op " " arg0, var, cc, __CLOBBERS_MEM())
42	20

arch/x86/include/asm/sev.h+1−2

@@ -491,8 +491,7 @@ static inline int pvalidate(unsigned long vaddr, bool rmp_psize, bool validate) · 490 unmodified lines
491	491
492	492	/* "pvalidate" mnemonic support in binutils 2.36 and newer */
493	493	asm volatile(".byte 0xF2, 0x0F, 0x01, 0xFF\n\t"
494		− CC_SET(c)
495		− : CC_OUT(c) (no_rmpupdate), "=a"(rc)
	494	+ : "=@ccc"(no_rmpupdate), "=a"(rc)
496	495	: "a"(vaddr), "c"(rmp_psize), "d"(validate)
497	496	: "memory", "cc");
498	497

arch/x86/include/asm/signal.h+1−2

@@ -83,8 +83,7 @@ static inline int __const_sigismember(sigset_t *set, int _sig) · 82 unmodified lines
83	83	static inline int __gen_sigismember(sigset_t *set, int _sig)
84	84	{
85	85	bool ret;
86		− asm("btl %2,%1" CC_SET(c)
87		− : CC_OUT(c) (ret) : "m"(*set), "Ir"(_sig-1));
	86	+ asm("btl %2,%1" : "=@ccc"(ret) : "m"(*set), "Ir"(_sig-1));
88	87	return ret;
89	88	}
90	89

arch/x86/include/asm/special_insns.h+3−7

@@ -75,9 +75,7 @@ static inline u32 rdpkru(void) · 74 unmodified lines
75	75	* "rdpkru" instruction. Places PKRU contents in to EAX,
76	76	* clears EDX and requires that ecx=0.
77	77	*/
78		− asm volatile(".byte 0x0f,0x01,0xee\n\t"
79		− : "=a" (pkru), "=d" (edx)
80		− : "c" (ecx));
	78	+ asm volatile("rdpkru" : "=a" (pkru), "=d" (edx) : "c" (ecx));
81	79	return pkru;
82	80	}
83	81
@@ -89,8 +87,7 @@ static inline void wrpkru(u32 pkru) · 5 unmodified lines
89	87	* "wrpkru" instruction. Loads contents in EAX to PKRU,
90	88	* requires that ecx = edx = 0.
91	89	*/
92		− asm volatile(".byte 0x0f,0x01,0xef\n\t"
93		− : : "a" (pkru), "c"(ecx), "d"(edx));
	90	+ asm volatile("wrpkru" : : "a" (pkru), "c"(ecx), "d"(edx));
94	91	}
95	92
96	93	#else
@@ -287,8 +284,7 @@ static inline int enqcmds(void __iomem dst, const void src) · 190 unmodified lines
287	284	* See movdir64b()'s comment on operand specification.
288	285	*/
289	286	asm volatile(".byte 0xf3, 0x0f, 0x38, 0xf8, 0x02, 0x66, 0x90"
290		− CC_SET(z)
291		− : CC_OUT(z) (zf), "+m" (*__dst)
	287	+ : "=@ccz" (zf), "+m" (*__dst)
292	288	: "m" (*__src), "a" (__dst), "d" (__src));
293	289
294	290	/* Submission failure is indicated via EFLAGS.ZF=1 */

arch/x86/include/asm/uaccess.h+3−4

@@ -378,7 +378,7 @@ do { \ · 377 unmodified lines
378	378	asm_goto_output("\n" \
379	379	"1: " LOCK_PREFIX "cmpxchg"itype" %[new], %[ptr]\n"\
380	380	_ASM_EXTABLE_UA(1b, %l[label]) \
381		− : CC_OUT(z) (success), \
	381	+ : "=@ccz" (success), \
382	382	[ptr] "+m" (*_ptr), \
383	383	[old] "+a" (__old) \
384	384	: [new] ltype (__new) \
@@ -397,7 +397,7 @@ do { \ · 12 unmodified lines
397	397	asm_goto_output("\n" \
398	398	"1: " LOCK_PREFIX "cmpxchg8b %[ptr]\n" \
399	399	_ASM_EXTABLE_UA(1b, %l[label]) \
400		− : CC_OUT(z) (success), \
	400	+ : "=@ccz" (success), \
401	401	"+A" (__old), \
402	402	[ptr] "+m" (*_ptr) \
403	403	: "b" ((u32)__new), \
@@ -417,11 +417,10 @@ do { \ · 13 unmodified lines
417	417	__typeof__(*(_ptr)) __new = (_new); \
418	418	asm volatile("\n" \
419	419	"1: " LOCK_PREFIX "cmpxchg"itype" %[new], %[ptr]\n"\
420		− CC_SET(z) \
421	420	"2:\n" \
422	421	_ASM_EXTABLE_TYPE_REG(1b, 2b, EX_TYPE_EFAULT_REG, \
423	422	%[errout]) \
424		− : CC_OUT(z) (success), \
	423	+ : "=@ccz" (success), \
425	424	[errout] "+r" (__err), \
426	425	[ptr] "+m" (*_ptr), \
427	426	[old] "+a" (__old) \

arch/x86/kernel/cpu/mtrr/cleanup.c+1−14

@@ -1,21 +1,8 @@
	1	+// SPDX-License-Identifier: LGPL-2.0+
1	2	/*
2	3	* MTRR (Memory Type Range Register) cleanup
3	4	*
4	5	* Copyright (C) 2009 Yinghai Lu
5		− *
6		− * This library is free software; you can redistribute it and/or
7		− * modify it under the terms of the GNU Library General Public
8		− * License as published by the Free Software Foundation; either
9		− * version 2 of the License, or (at your option) any later version.
10		− *
11		− * This library is distributed in the hope that it will be useful,
12		− * but WITHOUT ANY WARRANTY; without even the implied warranty of
13		− * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14		− * Library General Public License for more details.
15		− *
16		− * You should have received a copy of the GNU Library General Public
17		− * License along with this library; if not, write to the Free
18		− * Software Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
19	6	*/
20	7	#include <linux/init.h>
21	8	#include <linux/pci.h>

arch/x86/kernel/cpu/mtrr/mtrr.c+1−14

@@ -1,22 +1,9 @@
	1	+// SPDX-License-Identifier: LGPL-2.0+
1	2	/* Generic MTRR (Memory Type Range Register) driver.
2	3
3	4	Copyright (C) 1997-2000 Richard Gooch
4	5	Copyright (c) 2002 Patrick Mochel
5	6
6		− This library is free software; you can redistribute it and/or
7		− modify it under the terms of the GNU Library General Public
8		− License as published by the Free Software Foundation; either
9		− version 2 of the License, or (at your option) any later version.
10		−
11		− This library is distributed in the hope that it will be useful,
12		− but WITHOUT ANY WARRANTY; without even the implied warranty of
13		− MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14		− Library General Public License for more details.
15		−
16		− You should have received a copy of the GNU Library General Public
17		− License along with this library; if not, write to the Free
18		− Software Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
19		−
20	7	Richard Gooch may be reached by email at rgooch@atnf.csiro.au
21	8	The postal address is:
22	9	Richard Gooch, c/o ATNF, P. O. Box 76, Epping, N.S.W., 2121, Australia.

arch/x86/kernel/cpu/sgx/encls.h+3−3

@@ -68,7 +68,7 @@ static inline bool encls_failed(int ret) · 67 unmodified lines
68	68	({ \
69	69	int ret; \
70	70	asm volatile( \
71		− "1: .byte 0x0f, 0x01, 0xcf;\n\t" \
	71	+ "1: encls\n" \
72	72	"2:\n" \
73	73	_ASM_EXTABLE_TYPE(1b, 2b, EX_TYPE_FAULT_SGX) \
74	74	: "=a"(ret) \
@@ -111,8 +111,8 @@ static inline bool encls_failed(int ret) · 36 unmodified lines
111	111	({ \
112	112	int ret; \
113	113	asm volatile( \
114		− "1: .byte 0x0f, 0x01, 0xcf;\n\t" \
115		− " xor %%eax,%%eax;\n" \
	114	+ "1: encls\n\t" \
	115	+ "xor %%eax,%%eax\n" \
116	116	"2:\n" \
117	117	_ASM_EXTABLE_TYPE(1b, 2b, EX_TYPE_FAULT_SGX) \
118	118	: "=a"(ret), "=b"(rbx_out) \

tools/arch/x86/include/asm/asm.h+0−12

@@ -108,18 +108,6 @@ · 107 unmodified lines
108	108
109	109	#endif
110	110
111		−/*
112		− * Macros to generate condition code outputs from inline assembly,
113		− * The output operand must be type "bool".
114		− */
115		−#ifdef __GCC_ASM_FLAG_OUTPUTS__
116		−# define CC_SET(c) "\n\t/* output condition code " #c "*/\n"
117		−# define CC_OUT(c) "=@cc" #c
118		−#else
119		−# define CC_SET(c) "\n\tset" #c " %[_cc_" #c "]\n"
120		−# define CC_OUT(c) [_cc_ ## c] "=qm"
121		−#endif
122		−
123	111	#ifdef __KERNEL__
124	112
125	113	/* Exception table entry */

tools/perf/bench/find-bit-bench.c+1−1

@@ -37,7 +37,7 @@ static noinline void workload(int val) · 36 unmodified lines
37	37	accumulator++;
38	38	}
39	39
40		−#if (defined(__i386__) \|\| defined(__x86_64__)) && defined(__GCC_ASM_FLAG_OUTPUTS__)
	40	+#if defined(__i386__) \|\| defined(__x86_64__)
41	41	static bool asm_test_bit(long nr, const unsigned long *addr)
42	42	{
43	43	bool oldbit;

Merge tag 'x86_cleanups_for_v6.18_rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip

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