This is required to properly calculate the tiling parameters in userspace.
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| @@ -981,6 +981,8 @@ struct drm_radeon_cs { · 980 unmodified lines | |||
| 981 | #define RADEON_INFO_SI_TILE_MODE_ARRAY 0x16 | 981 | #define RADEON_INFO_SI_TILE_MODE_ARRAY 0x16 |
| 982 | /* query if CP DMA is supported on the compute ring */ | 982 | /* query if CP DMA is supported on the compute ring */ |
| 983 | #define RADEON_INFO_SI_CP_DMA_COMPUTE 0x17 | 983 | #define RADEON_INFO_SI_CP_DMA_COMPUTE 0x17 |
| 984 | /* CIK macrotile mode array */ | ||
| 985 | #define RADEON_INFO_CIK_MACROTILE_MODE_ARRAY 0x18 | ||
| 984 | 986 | ||
| 985 | 987 | ||
| 986 | struct drm_radeon_info { | 988 | struct drm_radeon_info { |