History

Merge tag 'drm-msm-next-2021-06-23b' of https://gitlab.freedesktop.org/drm/msm into drm-next

* devcoredump support for display errors * dpu: irq cleanup/refactor * dpu: dt bindings conversion to yaml * dsi: dt bindings conversion to yaml * mdp5: alpha/blend_mode/zpos support * a6xx: cached coherent buffer support * a660 support * gpu iova fault improvements: - info about which block triggered the fault, etc - generation of gpu devcoredump on fault * assortment of other cleanups and fixes

Dave Airlie committed 5 years ago

Commit 334200b2 parents 61c0cb8 e88bbc9133 files · +7203 −6274Browse files

Unified · Split

133 files
  1. Documentation/devicetree/bindings/display/msm/dp-controller.yaml +146 −0
  2. Documentation/devicetree/bindings/display/msm/dpu-sc7180.yaml +228 −0
  3. Documentation/devicetree/bindings/display/msm/dpu-sdm845.yaml +212 −0
  4. Documentation/devicetree/bindings/display/msm/dpu.txt +0 −141
  5. Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml +185 −0
  6. Documentation/devicetree/bindings/display/msm/dsi-phy-10nm.yaml +68 −0
  7. Documentation/devicetree/bindings/display/msm/dsi-phy-14nm.yaml +66 −0
  8. Documentation/devicetree/bindings/display/msm/dsi-phy-20nm.yaml +71 −0
  9. Documentation/devicetree/bindings/display/msm/dsi-phy-28nm.yaml +68 −0
  10. Documentation/devicetree/bindings/display/msm/dsi-phy-common.yaml +40 −0
  11. Documentation/devicetree/bindings/display/msm/dsi.txt +0 −249
  12. drivers/gpu/drm/drm_atomic.c +23 −5
  13. drivers/gpu/drm/drm_atomic_uapi.c +3 −1
  14. drivers/gpu/drm/drm_crtc_internal.h +3 −1
  15. drivers/gpu/drm/msm/Makefile +2 −1
  16. drivers/gpu/drm/msm/adreno/a2xx.xml.h +42 −18
  17. drivers/gpu/drm/msm/adreno/a3xx.xml.h +20 −20
  18. drivers/gpu/drm/msm/adreno/a4xx.xml.h +19 −19
  19. drivers/gpu/drm/msm/adreno/a5xx.xml.h +70 −25
  20. drivers/gpu/drm/msm/adreno/a5xx_gpu.c +22 −7
  21. drivers/gpu/drm/msm/adreno/a5xx_power.c +1 −1
  22. drivers/gpu/drm/msm/adreno/a5xx_preempt.c +2 −2
  23. drivers/gpu/drm/msm/adreno/a6xx.xml.h +1059 −1142
  24. drivers/gpu/drm/msm/adreno/a6xx_gmu.c +42 −13
  25. drivers/gpu/drm/msm/adreno/a6xx_gmu.xml.h +19 −15
  26. drivers/gpu/drm/msm/adreno/a6xx_gpu.c +258 −47
  27. drivers/gpu/drm/msm/adreno/a6xx_gpu.h +0 −2
  28. drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c +35 −9
  29. drivers/gpu/drm/msm/adreno/a6xx_hfi.c +33 −0
  30. drivers/gpu/drm/msm/adreno/adreno_common.xml.h +15 −15
  31. drivers/gpu/drm/msm/adreno/adreno_device.c +14 −0
  32. drivers/gpu/drm/msm/adreno/adreno_gpu.c +19 −7
  33. drivers/gpu/drm/msm/adreno/adreno_gpu.h +12 −1
  34. drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h +79 −40
  35. drivers/gpu/drm/msm/disp/dpu1/dpu_core_irq.c +42 −188
  36. drivers/gpu/drm/msm/disp/dpu1/dpu_core_irq.h +0 −43
  37. drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c +11 −11
  38. drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c +20 −23
  39. drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c +39 −71
  40. drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h +0 −4
  41. drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c +21 −37
  42. drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c +20 −34
  43. drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c +3 −3
  44. drivers/gpu/drm/msm/disp/dpu1/dpu_hw_blk.c +0 −139
  45. drivers/gpu/drm/msm/disp/dpu1/dpu_hw_blk.h +1 −21
  46. drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c +136 −66
  47. drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h +12 −4
  48. drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c +0 −6
  49. drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dspp.c +0 −7
  50. drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c +110 −1398
  51. drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h +38 −94
  52. drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c +0 −6
  53. drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c +0 −6
  54. drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h +1 −1
  55. drivers/gpu/drm/msm/disp/dpu1/dpu_hw_merge3d.c +0 −6
  56. drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.c +0 −6
  57. drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.h +3 −1
  58. drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c +0 −6
  59. drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c +0 −6
  60. drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c +55 −15
  61. drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h +1 −7
  62. drivers/gpu/drm/msm/disp/dpu1/dpu_mdss.c +5 −3
  63. drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c +10 −13
  64. drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c +2 −2
  65. drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h +18 −45
  66. drivers/gpu/drm/msm/disp/dpu1/dpu_vbif.c +7 −7
  67. drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h +21 −13
  68. drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h +25 −13
  69. drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.c +35 −0
  70. drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.h +7 −0
  71. drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c +7 −5
  72. drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.h +0 −5
  73. drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c +19 −116
  74. drivers/gpu/drm/msm/disp/mdp_common.xml.h +21 −13
  75. drivers/gpu/drm/msm/disp/msm_disp_snapshot.c +125 −0
  76. drivers/gpu/drm/msm/disp/msm_disp_snapshot.h +136 −0
  77. drivers/gpu/drm/msm/disp/msm_disp_snapshot_util.c +187 −0
  78. drivers/gpu/drm/msm/dp/dp_aux.c +78 −103
  79. drivers/gpu/drm/msm/dp/dp_aux.h +0 −8
  80. drivers/gpu/drm/msm/dp/dp_catalog.c +13 −5
  81. drivers/gpu/drm/msm/dp/dp_catalog.h +5 −2
  82. drivers/gpu/drm/msm/dp/dp_ctrl.c +63 −24
  83. drivers/gpu/drm/msm/dp/dp_ctrl.h +2 −1
  84. drivers/gpu/drm/msm/dp/dp_display.c +76 −45
  85. drivers/gpu/drm/msm/dp/dp_display.h +1 −0
  86. drivers/gpu/drm/msm/dp/dp_link.c +6 −15
  87. drivers/gpu/drm/msm/dp/dp_panel.c +1 −3
  88. drivers/gpu/drm/msm/dp/dp_power.h +2 −2
  89. drivers/gpu/drm/msm/dsi/dsi.c +6 −0
  90. drivers/gpu/drm/msm/dsi/dsi.h +3 −1
  91. drivers/gpu/drm/msm/dsi/dsi.xml.h +22 −1700
  92. drivers/gpu/drm/msm/dsi/dsi_host.c +19 −11
  93. drivers/gpu/drm/msm/dsi/dsi_manager.c +6 −6
  94. drivers/gpu/drm/msm/dsi/dsi_phy_10nm.xml.h +228 −0
  95. drivers/gpu/drm/msm/dsi/dsi_phy_14nm.xml.h +310 −0
  96. drivers/gpu/drm/msm/dsi/dsi_phy_20nm.xml.h +238 −0
  97. drivers/gpu/drm/msm/dsi/dsi_phy_28nm.xml.h +385 −0
  98. drivers/gpu/drm/msm/dsi/dsi_phy_28nm_8960.xml.h +287 −0
  99. drivers/gpu/drm/msm/dsi/dsi_phy_5nm.xml.h +480 −0
  100. drivers/gpu/drm/msm/dsi/dsi_phy_7nm.xml.h +482 −0
  101. drivers/gpu/drm/msm/dsi/mmss_cc.xml.h +21 −13
  102. drivers/gpu/drm/msm/dsi/phy/dsi_phy.c +27 −4
  103. drivers/gpu/drm/msm/dsi/phy/dsi_phy.h +4 −0
  104. drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c +1 −0
  105. drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c +1 −0
  106. drivers/gpu/drm/msm/dsi/phy/dsi_phy_20nm.c +1 −0
  107. drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c +1 −0
  108. drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c +1 −0
  109. drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c +6 −1
  110. drivers/gpu/drm/msm/dsi/sfpb.xml.h +21 −13
  111. drivers/gpu/drm/msm/edp/edp.xml.h +21 −13
  112. drivers/gpu/drm/msm/hdmi/hdmi.xml.h +21 −13
  113. drivers/gpu/drm/msm/hdmi/qfprom.xml.h +21 −13
  114. drivers/gpu/drm/msm/msm_debugfs.c +31 −0
  115. drivers/gpu/drm/msm/msm_drv.c +26 −7
  116. drivers/gpu/drm/msm/msm_drv.h +23 −1
  117. drivers/gpu/drm/msm/msm_fb.c +4 −4
  118. drivers/gpu/drm/msm/msm_gem.c +19 −19
  119. drivers/gpu/drm/msm/msm_gem.h +1 −0
  120. drivers/gpu/drm/msm/msm_gem_shrinker.c +18 −0
  121. drivers/gpu/drm/msm/msm_gem_submit.c +1 −0
  122. drivers/gpu/drm/msm/msm_gpu.c +50 −1
  123. drivers/gpu/drm/msm/msm_gpu.h +18 −11
  124. drivers/gpu/drm/msm/msm_gpummu.c +5 −0
  125. drivers/gpu/drm/msm/msm_iommu.c +21 −1
  126. drivers/gpu/drm/msm/msm_kms.h +9 −0
  127. drivers/gpu/drm/msm/msm_mmu.h +3 −2
  128. drivers/gpu/drm/selftests/test-drm_framebuffer.c +1 −0
  129. drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c +50 −0
  130. drivers/iommu/arm/arm-smmu/arm-smmu.c +7 −2
  131. drivers/iommu/arm/arm-smmu/arm-smmu.h +2 −0
  132. include/linux/adreno-smmu-priv.h +37 −1
  133. include/uapi/drm/msm_drm.h +3 −4
Documentation/devicetree/bindings/display/msm/dp-controller.yaml+146−0
@@ -0,0 +1,146 @@
1+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2+%YAML 1.2
3+---
4+$id: http://devicetree.org/schemas/display/msm/dp-controller.yaml#
5+$schema: http://devicetree.org/meta-schemas/core.yaml#
6+
7+title: MSM Display Port Controller
8+
9+maintainers:
10+ - Kuogee Hsieh <khsieh@codeaurora.org>
11+
12+description: |
13+ Device tree bindings for DisplayPort host controller for MSM targets
14+ that are compatible with VESA DisplayPort interface specification.
15+
16+properties:
17+ compatible:
18+ enum:
19+ - qcom,sc7180-dp
20+
21+ reg:
22+ maxItems: 1
23+
24+ interrupts:
25+ maxItems: 1
26+
27+ clocks:
28+ items:
29+ - description: AHB clock to enable register access
30+ - description: Display Port AUX clock
31+ - description: Display Port Link clock
32+ - description: Link interface clock between DP and PHY
33+ - description: Display Port Pixel clock
34+
35+ clock-names:
36+ items:
37+ - const: core_iface
38+ - const: core_aux
39+ - const: ctrl_link
40+ - const: ctrl_link_iface
41+ - const: stream_pixel
42+
43+ assigned-clocks:
44+ items:
45+ - description: link clock source
46+ - description: pixel clock source
47+
48+ assigned-clock-parents:
49+ items:
50+ - description: phy 0 parent
51+ - description: phy 1 parent
52+
53+ phys:
54+ maxItems: 1
55+
56+ phy-names:
57+ items:
58+ - const: dp
59+
60+ operating-points-v2:
61+ maxItems: 1
62+
63+ power-domains:
64+ maxItems: 1
65+
66+ "#sound-dai-cells":
67+ const: 0
68+
69+ ports:
70+ $ref: /schemas/graph.yaml#/properties/ports
71+ properties:
72+ port@0:
73+ $ref: /schemas/graph.yaml#/properties/port
74+ description: Input endpoint of the controller
75+
76+ port@1:
77+ $ref: /schemas/graph.yaml#/properties/port
78+ description: Output endpoint of the controller
79+
80+required:
81+ - compatible
82+ - reg
83+ - interrupts
84+ - clocks
85+ - clock-names
86+ - phys
87+ - phy-names
88+ - "#sound-dai-cells"
89+ - power-domains
90+ - ports
91+
92+additionalProperties: false
93+
94+examples:
95+ - |
96+ #include <dt-bindings/interrupt-controller/arm-gic.h>
97+ #include <dt-bindings/clock/qcom,dispcc-sc7180.h>
98+ #include <dt-bindings/power/qcom-aoss-qmp.h>
99+ #include <dt-bindings/power/qcom-rpmpd.h>
100+
101+ displayport-controller@ae90000 {
102+ compatible = "qcom,sc7180-dp";
103+ reg = <0xae90000 0x1400>;
104+ interrupt-parent = <&mdss>;
105+ interrupts = <12>;
106+ clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
107+ <&dispcc DISP_CC_MDSS_DP_AUX_CLK>,
108+ <&dispcc DISP_CC_MDSS_DP_LINK_CLK>,
109+ <&dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>,
110+ <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>;
111+ clock-names = "core_iface", "core_aux",
112+ "ctrl_link",
113+ "ctrl_link_iface", "stream_pixel";
114+
115+ assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>,
116+ <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>;
117+
118+ assigned-clock-parents = <&dp_phy 0>, <&dp_phy 1>;
119+
120+ phys = <&dp_phy>;
121+ phy-names = "dp";
122+
123+ #sound-dai-cells = <0>;
124+
125+ power-domains = <&rpmhpd SC7180_CX>;
126+
127+ ports {
128+ #address-cells = <1>;
129+ #size-cells = <0>;
130+
131+ port@0 {
132+ reg = <0>;
133+ endpoint {
134+ remote-endpoint = <&dpu_intf0_out>;
135+ };
136+ };
137+
138+ port@1 {
139+ reg = <1>;
140+ endpoint {
141+ remote-endpoint = <&typec>;
142+ };
143+ };
144+ };
145+ };
146+...
Documentation/devicetree/bindings/display/msm/dpu-sc7180.yaml+228−0
@@ -0,0 +1,228 @@
1+# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
2+%YAML 1.2
3+---
4+$id: http://devicetree.org/schemas/display/msm/dpu-sc7180.yaml#
5+$schema: http://devicetree.org/meta-schemas/core.yaml#
6+
7+title: Qualcomm Display DPU dt properties for SC7180 target
8+
9+maintainers:
10+ - Krishna Manikandan <mkrishn@codeaurora.org>
11+
12+description: |
13+ Device tree bindings for MSM Mobile Display Subsystem(MDSS) that encapsulates
14+ sub-blocks like DPU display controller, DSI and DP interfaces etc. Device tree
15+ bindings of MDSS and DPU are mentioned for SC7180 target.
16+
17+properties:
18+ compatible:
19+ items:
20+ - const: qcom,sc7180-mdss
21+
22+ reg:
23+ maxItems: 1
24+
25+ reg-names:
26+ const: mdss
27+
28+ power-domains:
29+ maxItems: 1
30+
31+ clocks:
32+ items:
33+ - description: Display AHB clock from gcc
34+ - description: Display AHB clock from dispcc
35+ - description: Display core clock
36+
37+ clock-names:
38+ items:
39+ - const: iface
40+ - const: ahb
41+ - const: core
42+
43+ interrupts:
44+ maxItems: 1
45+
46+ interrupt-controller: true
47+
48+ "#address-cells": true
49+
50+ "#size-cells": true
51+
52+ "#interrupt-cells":
53+ const: 1
54+
55+ iommus:
56+ items:
57+ - description: Phandle to apps_smmu node with SID mask for Hard-Fail port0
58+
59+ ranges: true
60+
61+ interconnects:
62+ items:
63+ - description: Interconnect path specifying the port ids for data bus
64+
65+ interconnect-names:
66+ const: mdp0-mem
67+
68+patternProperties:
69+ "^display-controller@[0-9a-f]+$":
70+ type: object
71+ description: Node containing the properties of DPU.
72+
73+ properties:
74+ compatible:
75+ items:
76+ - const: qcom,sc7180-dpu
77+
78+ reg:
79+ items:
80+ - description: Address offset and size for mdp register set
81+ - description: Address offset and size for vbif register set
82+
83+ reg-names:
84+ items:
85+ - const: mdp
86+ - const: vbif
87+
88+ clocks:
89+ items:
90+ - description: Display hf axi clock
91+ - description: Display ahb clock
92+ - description: Display rotator clock
93+ - description: Display lut clock
94+ - description: Display core clock
95+ - description: Display vsync clock
96+
97+ clock-names:
98+ items:
99+ - const: bus
100+ - const: iface
101+ - const: rot
102+ - const: lut
103+ - const: core
104+ - const: vsync
105+
106+ interrupts:
107+ maxItems: 1
108+
109+ power-domains:
110+ maxItems: 1
111+
112+ operating-points-v2: true
113+
114+ ports:
115+ $ref: /schemas/graph.yaml#/properties/ports
116+ description: |
117+ Contains the list of output ports from DPU device. These ports
118+ connect to interfaces that are external to the DPU hardware,
119+ such as DSI, DP etc. Each output port contains an endpoint that
120+ describes how it is connected to an external interface.
121+
122+ properties:
123+ port@0:
124+ $ref: /schemas/graph.yaml#/properties/port
125+ description: DPU_INTF1 (DSI1)
126+
127+ port@2:
128+ $ref: /schemas/graph.yaml#/properties/port
129+ description: DPU_INTF0 (DP)
130+
131+ required:
132+ - port@0
133+
134+ required:
135+ - compatible
136+ - reg
137+ - reg-names
138+ - clocks
139+ - interrupts
140+ - power-domains
141+ - operating-points-v2
142+ - ports
143+
144+required:
145+ - compatible
146+ - reg
147+ - reg-names
148+ - power-domains
149+ - clocks
150+ - interrupts
151+ - interrupt-controller
152+ - iommus
153+ - ranges
154+
155+additionalProperties: false
156+
157+examples:
158+ - |
159+ #include <dt-bindings/clock/qcom,dispcc-sc7180.h>
160+ #include <dt-bindings/clock/qcom,gcc-sc7180.h>
161+ #include <dt-bindings/interrupt-controller/arm-gic.h>
162+ #include <dt-bindings/interconnect/qcom,sdm845.h>
163+ #include <dt-bindings/power/qcom-rpmpd.h>
164+
165+ display-subsystem@ae00000 {
166+ #address-cells = <1>;
167+ #size-cells = <1>;
168+ compatible = "qcom,sc7180-mdss";
169+ reg = <0xae00000 0x1000>;
170+ reg-names = "mdss";
171+ power-domains = <&dispcc MDSS_GDSC>;
172+ clocks = <&gcc GCC_DISP_AHB_CLK>,
173+ <&dispcc DISP_CC_MDSS_AHB_CLK>,
174+ <&dispcc DISP_CC_MDSS_MDP_CLK>;
175+ clock-names = "iface", "ahb", "core";
176+
177+ interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
178+ interrupt-controller;
179+ #interrupt-cells = <1>;
180+
181+ interconnects = <&mmss_noc MASTER_MDP0 &mc_virt SLAVE_EBI1>;
182+ interconnect-names = "mdp0-mem";
183+
184+ iommus = <&apps_smmu 0x800 0x2>;
185+ ranges;
186+
187+ display-controller@ae01000 {
188+ compatible = "qcom,sc7180-dpu";
189+ reg = <0x0ae01000 0x8f000>,
190+ <0x0aeb0000 0x2008>;
191+
192+ reg-names = "mdp", "vbif";
193+
194+ clocks = <&gcc GCC_DISP_HF_AXI_CLK>,
195+ <&dispcc DISP_CC_MDSS_AHB_CLK>,
196+ <&dispcc DISP_CC_MDSS_ROT_CLK>,
197+ <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
198+ <&dispcc DISP_CC_MDSS_MDP_CLK>,
199+ <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
200+ clock-names = "bus", "iface", "rot", "lut", "core",
201+ "vsync";
202+
203+ interrupt-parent = <&mdss>;
204+ interrupts = <0>;
205+ power-domains = <&rpmhpd SC7180_CX>;
206+ operating-points-v2 = <&mdp_opp_table>;
207+
208+ ports {
209+ #address-cells = <1>;
210+ #size-cells = <0>;
211+
212+ port@0 {
213+ reg = <0>;
214+ dpu_intf1_out: endpoint {
215+ remote-endpoint = <&dsi0_in>;
216+ };
217+ };
218+
219+ port@2 {
220+ reg = <2>;
221+ dpu_intf0_out: endpoint {
222+ remote-endpoint = <&dp_in>;
223+ };
224+ };
225+ };
226+ };
227+ };
228+...
Documentation/devicetree/bindings/display/msm/dpu-sdm845.yaml+212−0
@@ -0,0 +1,212 @@
1+# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
2+%YAML 1.2
3+---
4+$id: http://devicetree.org/schemas/display/msm/dpu-sdm845.yaml#
5+$schema: http://devicetree.org/meta-schemas/core.yaml#
6+
7+title: Qualcomm Display DPU dt properties for SDM845 target
8+
9+maintainers:
10+ - Krishna Manikandan <mkrishn@codeaurora.org>
11+
12+description: |
13+ Device tree bindings for MSM Mobile Display Subsystem(MDSS) that encapsulates
14+ sub-blocks like DPU display controller, DSI and DP interfaces etc. Device tree
15+ bindings of MDSS and DPU are mentioned for SDM845 target.
16+
17+properties:
18+ compatible:
19+ items:
20+ - const: qcom,sdm845-mdss
21+
22+ reg:
23+ maxItems: 1
24+
25+ reg-names:
26+ const: mdss
27+
28+ power-domains:
29+ maxItems: 1
30+
31+ clocks:
32+ items:
33+ - description: Display AHB clock from gcc
34+ - description: Display AXI clock
35+ - description: Display core clock
36+
37+ clock-names:
38+ items:
39+ - const: iface
40+ - const: bus
41+ - const: core
42+
43+ interrupts:
44+ maxItems: 1
45+
46+ interrupt-controller: true
47+
48+ "#address-cells": true
49+
50+ "#size-cells": true
51+
52+ "#interrupt-cells":
53+ const: 1
54+
55+ iommus:
56+ items:
57+ - description: Phandle to apps_smmu node with SID mask for Hard-Fail port0
58+ - description: Phandle to apps_smmu node with SID mask for Hard-Fail port1
59+
60+ ranges: true
61+
62+patternProperties:
63+ "^display-controller@[0-9a-f]+$":
64+ type: object
65+ description: Node containing the properties of DPU.
66+
67+ properties:
68+ compatible:
69+ items:
70+ - const: qcom,sdm845-dpu
71+
72+ reg:
73+ items:
74+ - description: Address offset and size for mdp register set
75+ - description: Address offset and size for vbif register set
76+
77+ reg-names:
78+ items:
79+ - const: mdp
80+ - const: vbif
81+
82+ clocks:
83+ items:
84+ - description: Display ahb clock
85+ - description: Display axi clock
86+ - description: Display core clock
87+ - description: Display vsync clock
88+
89+ clock-names:
90+ items:
91+ - const: iface
92+ - const: bus
93+ - const: core
94+ - const: vsync
95+
96+ interrupts:
97+ maxItems: 1
98+
99+ power-domains:
100+ maxItems: 1
101+
102+ operating-points-v2: true
103+ ports:
104+ $ref: /schemas/graph.yaml#/properties/ports
105+ description: |
106+ Contains the list of output ports from DPU device. These ports
107+ connect to interfaces that are external to the DPU hardware,
108+ such as DSI, DP etc. Each output port contains an endpoint that
109+ describes how it is connected to an external interface.
110+
111+ properties:
112+ port@0:
113+ $ref: /schemas/graph.yaml#/properties/port
114+ description: DPU_INTF1 (DSI1)
115+
116+ port@1:
117+ $ref: /schemas/graph.yaml#/properties/port
118+ description: DPU_INTF2 (DSI2)
119+
120+ required:
121+ - port@0
122+ - port@1
123+
124+ required:
125+ - compatible
126+ - reg
127+ - reg-names
128+ - clocks
129+ - interrupts
130+ - power-domains
131+ - operating-points-v2
132+ - ports
133+
134+required:
135+ - compatible
136+ - reg
137+ - reg-names
138+ - power-domains
139+ - clocks
140+ - interrupts
141+ - interrupt-controller
142+ - iommus
143+ - ranges
144+
145+additionalProperties: false
146+
147+examples:
148+ - |
149+ #include <dt-bindings/clock/qcom,dispcc-sdm845.h>
150+ #include <dt-bindings/clock/qcom,gcc-sdm845.h>
151+ #include <dt-bindings/interrupt-controller/arm-gic.h>
152+ #include <dt-bindings/power/qcom-rpmpd.h>
153+
154+ display-subsystem@ae00000 {
155+ #address-cells = <1>;
156+ #size-cells = <1>;
157+ compatible = "qcom,sdm845-mdss";
158+ reg = <0x0ae00000 0x1000>;
159+ reg-names = "mdss";
160+ power-domains = <&dispcc MDSS_GDSC>;
161+
162+ clocks = <&gcc GCC_DISP_AHB_CLK>,
163+ <&gcc GCC_DISP_AXI_CLK>,
164+ <&dispcc DISP_CC_MDSS_MDP_CLK>;
165+ clock-names = "iface", "bus", "core";
166+
167+ interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
168+ interrupt-controller;
169+ #interrupt-cells = <1>;
170+
171+ iommus = <&apps_smmu 0x880 0x8>,
172+ <&apps_smmu 0xc80 0x8>;
173+ ranges;
174+
175+ display-controller@ae01000 {
176+ compatible = "qcom,sdm845-dpu";
177+ reg = <0x0ae01000 0x8f000>,
178+ <0x0aeb0000 0x2008>;
179+ reg-names = "mdp", "vbif";
180+
181+ clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
182+ <&dispcc DISP_CC_MDSS_AXI_CLK>,
183+ <&dispcc DISP_CC_MDSS_MDP_CLK>,
184+ <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
185+ clock-names = "iface", "bus", "core", "vsync";
186+
187+ interrupt-parent = <&mdss>;
188+ interrupts = <0>;
189+ power-domains = <&rpmhpd SDM845_CX>;
190+ operating-points-v2 = <&mdp_opp_table>;
191+
192+ ports {
193+ #address-cells = <1>;
194+ #size-cells = <0>;
195+
196+ port@0 {
197+ reg = <0>;
198+ dpu_intf1_out: endpoint {
199+ remote-endpoint = <&dsi0_in>;
200+ };
201+ };
202+
203+ port@1 {
204+ reg = <1>;
205+ dpu_intf2_out: endpoint {
206+ remote-endpoint = <&dsi1_in>;
207+ };
208+ };
209+ };
210+ };
211+ };
212+...
Documentation/devicetree/bindings/display/msm/dpu.txt+0−141
@@ -1,141 +0,0 @@
1−Qualcomm Technologies, Inc. DPU KMS
2−
3−Description:
4−
5−Device tree bindings for MSM Mobile Display Subsystem(MDSS) that encapsulates
6−sub-blocks like DPU display controller, DSI and DP interfaces etc.
7−The DPU display controller is found in SDM845 SoC.
8−
9−MDSS:
10−Required properties:
11−- compatible: "qcom,sdm845-mdss", "qcom,sc7180-mdss"
12−- reg: physical base address and length of controller's registers.
13−- reg-names: register region names. The following region is required:
14− * "mdss"
15−- power-domains: a power domain consumer specifier according to
16− Documentation/devicetree/bindings/power/power_domain.txt
17−- clocks: list of clock specifiers for clocks needed by the device.
18−- clock-names: device clock names, must be in same order as clocks property.
19− The following clocks are required:
20− * "iface"
21− * "bus"
22− * "core"
23−- interrupts: interrupt signal from MDSS.
24−- interrupt-controller: identifies the node as an interrupt controller.
25−- #interrupt-cells: specifies the number of cells needed to encode an interrupt
26− source, should be 1.
27−- iommus: phandle of iommu device node.
28−- #address-cells: number of address cells for the MDSS children. Should be 1.
29−- #size-cells: Should be 1.
30−- ranges: parent bus address space is the same as the child bus address space.
31−- interconnects : interconnect path specifier for MDSS according to
32− Documentation/devicetree/bindings/interconnect/interconnect.txt. Should be
33− 2 paths corresponding to 2 AXI ports.
34−- interconnect-names : MDSS will have 2 port names to differentiate between the
35− 2 interconnect paths defined with interconnect specifier.
36−
37−Optional properties:
38−- assigned-clocks: list of clock specifiers for clocks needing rate assignment
39−- assigned-clock-rates: list of clock frequencies sorted in the same order as
40− the assigned-clocks property.
41−
42−MDP:
43−Required properties:
44−- compatible: "qcom,sdm845-dpu", "qcom,sc7180-dpu"
45−- reg: physical base address and length of controller's registers.
46−- reg-names : register region names. The following region is required:
47− * "mdp"
48− * "vbif"
49−- clocks: list of clock specifiers for clocks needed by the device.
50−- clock-names: device clock names, must be in same order as clocks property.
51− The following clocks are required.
52− * "bus"
53− * "iface"
54− * "core"
55− * "vsync"
56−- interrupts: interrupt line from DPU to MDSS.
57−- ports: contains the list of output ports from DPU device. These ports connect
58− to interfaces that are external to the DPU hardware, such as DSI, DP etc.
59−
60− Each output port contains an endpoint that describes how it is connected to an
61− external interface. These are described by the standard properties documented
62− here:
63− Documentation/devicetree/bindings/graph.txt
64− Documentation/devicetree/bindings/media/video-interfaces.txt
65−
66− Port 0 -> DPU_INTF1 (DSI1)
67− Port 1 -> DPU_INTF2 (DSI2)
68−
69−Optional properties:
70−- assigned-clocks: list of clock specifiers for clocks needing rate assignment
71−- assigned-clock-rates: list of clock frequencies sorted in the same order as
72− the assigned-clocks property.
73−
74−Example:
75−
76− mdss: mdss@ae00000 {
77− compatible = "qcom,sdm845-mdss";
78− reg = <0xae00000 0x1000>;
79− reg-names = "mdss";
80−
81− power-domains = <&clock_dispcc 0>;
82−
83− clocks = <&gcc GCC_DISP_AHB_CLK>, <&gcc GCC_DISP_AXI_CLK>,
84− <&clock_dispcc DISP_CC_MDSS_MDP_CLK>;
85− clock-names = "iface", "bus", "core";
86−
87− assigned-clocks = <&clock_dispcc DISP_CC_MDSS_MDP_CLK>;
88− assigned-clock-rates = <300000000>;
89−
90− interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
91− interrupt-controller;
92− #interrupt-cells = <1>;
93−
94− interconnects = <&rsc_hlos MASTER_MDP0 &rsc_hlos SLAVE_EBI1>,
95− <&rsc_hlos MASTER_MDP1 &rsc_hlos SLAVE_EBI1>;
96−
97− interconnect-names = "mdp0-mem", "mdp1-mem";
98−
99− iommus = <&apps_iommu 0>;
100−
101− #address-cells = <2>;
102− #size-cells = <1>;
103− ranges = <0 0 0xae00000 0xb2008>;
104−
105− mdss_mdp: mdp@ae01000 {
106− compatible = "qcom,sdm845-dpu";
107− reg = <0 0x1000 0x8f000>, <0 0xb0000 0x2008>;
108− reg-names = "mdp", "vbif";
109−
110− clocks = <&clock_dispcc DISP_CC_MDSS_AHB_CLK>,
111− <&clock_dispcc DISP_CC_MDSS_AXI_CLK>,
112− <&clock_dispcc DISP_CC_MDSS_MDP_CLK>,
113− <&clock_dispcc DISP_CC_MDSS_VSYNC_CLK>;
114− clock-names = "iface", "bus", "core", "vsync";
115−
116− assigned-clocks = <&clock_dispcc DISP_CC_MDSS_MDP_CLK>,
117− <&clock_dispcc DISP_CC_MDSS_VSYNC_CLK>;
118− assigned-clock-rates = <0 0 300000000 19200000>;
119−
120− interrupts = <0 IRQ_TYPE_LEVEL_HIGH>;
121−
122− ports {
123− #address-cells = <1>;
124− #size-cells = <0>;
125−
126− port@0 {
127− reg = <0>;
128− dpu_intf1_out: endpoint {
129− remote-endpoint = <&dsi0_in>;
130− };
131− };
132−
133− port@1 {
134− reg = <1>;
135− dpu_intf2_out: endpoint {
136− remote-endpoint = <&dsi1_in>;
137− };
138− };
139− };
140− };
141− };
Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml+185−0
@@ -0,0 +1,185 @@
1+# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
2+%YAML 1.2
3+---
4+$id: http://devicetree.org/schemas/display/msm/dsi-controller-main.yaml#
5+$schema: http://devicetree.org/meta-schemas/core.yaml#
6+
7+title: Qualcomm Display DSI controller
8+
9+maintainers:
10+ - Krishna Manikandan <mkrishn@codeaurora.org>
11+
12+allOf:
13+ - $ref: "../dsi-controller.yaml#"
14+
15+properties:
16+ compatible:
17+ items:
18+ - const: qcom,mdss-dsi-ctrl
19+
20+ reg:
21+ maxItems: 1
22+
23+ reg-names:
24+ const: dsi_ctrl
25+
26+ interrupts:
27+ maxItems: 1
28+
29+ clocks:
30+ items:
31+ - description: Display byte clock
32+ - description: Display byte interface clock
33+ - description: Display pixel clock
34+ - description: Display escape clock
35+ - description: Display AHB clock
36+ - description: Display AXI clock
37+
38+ clock-names:
39+ items:
40+ - const: byte
41+ - const: byte_intf
42+ - const: pixel
43+ - const: core
44+ - const: iface
45+ - const: bus
46+
47+ phys:
48+ maxItems: 1
49+
50+ phy-names:
51+ const: dsi
52+
53+ "#address-cells": true
54+
55+ "#size-cells": true
56+
57+ syscon-sfpb:
58+ description: A phandle to mmss_sfpb syscon node (only for DSIv2).
59+ $ref: "/schemas/types.yaml#/definitions/phandle"
60+
61+ qcom,dual-dsi-mode:
62+ type: boolean
63+ description: |
64+ Indicates if the DSI controller is driving a panel which needs
65+ 2 DSI links.
66+
67+ power-domains:
68+ maxItems: 1
69+
70+ operating-points-v2: true
71+
72+ ports:
73+ $ref: "/schemas/graph.yaml#/properties/ports"
74+ description: |
75+ Contains DSI controller input and output ports as children, each
76+ containing one endpoint subnode.
77+
78+ properties:
79+ port@0:
80+ $ref: "/schemas/graph.yaml#/properties/port"
81+ description: |
82+ Input endpoints of the controller.
83+ properties:
84+ endpoint:
85+ $ref: /schemas/media/video-interfaces.yaml#
86+ unevaluatedProperties: false
87+ properties:
88+ data-lanes:
89+ maxItems: 4
90+ minItems: 4
91+ items:
92+ enum: [ 0, 1, 2, 3 ]
93+
94+ port@1:
95+ $ref: "/schemas/graph.yaml#/properties/port"
96+ description: |
97+ Output endpoints of the controller.
98+ properties:
99+ endpoint:
100+ $ref: /schemas/media/video-interfaces.yaml#
101+ unevaluatedProperties: false
102+ properties:
103+ data-lanes:
104+ maxItems: 4
105+ minItems: 4
106+ items:
107+ enum: [ 0, 1, 2, 3 ]
108+
109+ required:
110+ - port@0
111+ - port@1
112+
113+required:
114+ - compatible
115+ - reg
116+ - reg-names
117+ - interrupts
118+ - clocks
119+ - clock-names
120+ - phys
121+ - phy-names
122+ - power-domains
123+ - operating-points-v2
124+ - ports
125+
126+additionalProperties: false
127+
128+examples:
129+ - |
130+ #include <dt-bindings/interrupt-controller/arm-gic.h>
131+ #include <dt-bindings/clock/qcom,dispcc-sdm845.h>
132+ #include <dt-bindings/clock/qcom,gcc-sdm845.h>
133+ #include <dt-bindings/power/qcom-rpmpd.h>
134+
135+ dsi@ae94000 {
136+ compatible = "qcom,mdss-dsi-ctrl";
137+ reg = <0x0ae94000 0x400>;
138+ reg-names = "dsi_ctrl";
139+
140+ #address-cells = <1>;
141+ #size-cells = <0>;
142+
143+ interrupt-parent = <&mdss>;
144+ interrupts = <4>;
145+
146+ clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
147+ <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
148+ <&dispcc DISP_CC_MDSS_PCLK0_CLK>,
149+ <&dispcc DISP_CC_MDSS_ESC0_CLK>,
150+ <&dispcc DISP_CC_MDSS_AHB_CLK>,
151+ <&dispcc DISP_CC_MDSS_AXI_CLK>;
152+ clock-names = "byte",
153+ "byte_intf",
154+ "pixel",
155+ "core",
156+ "iface",
157+ "bus";
158+
159+ phys = <&dsi0_phy>;
160+ phy-names = "dsi";
161+
162+ power-domains = <&rpmhpd SC7180_CX>;
163+ operating-points-v2 = <&dsi_opp_table>;
164+
165+ ports {
166+ #address-cells = <1>;
167+ #size-cells = <0>;
168+
169+ port@0 {
170+ reg = <0>;
171+ dsi0_in: endpoint {
172+ remote-endpoint = <&dpu_intf1_out>;
173+ };
174+ };
175+
176+ port@1 {
177+ reg = <1>;
178+ dsi0_out: endpoint {
179+ remote-endpoint = <&sn65dsi86_in>;
180+ data-lanes = <0 1 2 3>;
181+ };
182+ };
183+ };
184+ };
185+...
Documentation/devicetree/bindings/display/msm/dsi-phy-10nm.yaml+68−0
@@ -0,0 +1,68 @@
1+# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
2+%YAML 1.2
3+---
4+$id: http://devicetree.org/schemas/display/msm/dsi-phy-10nm.yaml#
5+$schema: http://devicetree.org/meta-schemas/core.yaml#
6+
7+title: Qualcomm Display DSI 10nm PHY
8+
9+maintainers:
10+ - Krishna Manikandan <mkrishn@codeaurora.org>
11+
12+allOf:
13+ - $ref: dsi-phy-common.yaml#
14+
15+properties:
16+ compatible:
17+ oneOf:
18+ - const: qcom,dsi-phy-10nm
19+ - const: qcom,dsi-phy-10nm-8998
20+
21+ reg:
22+ items:
23+ - description: dsi phy register set
24+ - description: dsi phy lane register set
25+ - description: dsi pll register set
26+
27+ reg-names:
28+ items:
29+ - const: dsi_phy
30+ - const: dsi_phy_lane
31+ - const: dsi_pll
32+
33+ vdds-supply:
34+ description: |
35+ Connected to DSI0_MIPI_DSI_PLL_VDDA0P9 pin for sc7180 target and
36+ connected to VDDA_MIPI_DSI_0_PLL_0P9 pin for sdm845 target
37+
38+required:
39+ - compatible
40+ - reg
41+ - reg-names
42+ - vdds-supply
43+
44+unevaluatedProperties: false
45+
46+examples:
47+ - |
48+ #include <dt-bindings/clock/qcom,dispcc-sdm845.h>
49+ #include <dt-bindings/clock/qcom,rpmh.h>
50+
51+ dsi-phy@ae94400 {
52+ compatible = "qcom,dsi-phy-10nm";
53+ reg = <0x0ae94400 0x200>,
54+ <0x0ae94600 0x280>,
55+ <0x0ae94a00 0x1e0>;
56+ reg-names = "dsi_phy",
57+ "dsi_phy_lane",
58+ "dsi_pll";
59+
60+ #clock-cells = <1>;
61+ #phy-cells = <0>;
62+
63+ vdds-supply = <&vdda_mipi_dsi0_pll>;
64+ clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
65+ <&rpmhcc RPMH_CXO_CLK>;
66+ clock-names = "iface", "ref";
67+ };
68+...
Documentation/devicetree/bindings/display/msm/dsi-phy-14nm.yaml+66−0
@@ -0,0 +1,66 @@
1+# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
2+%YAML 1.2
3+---
4+$id: http://devicetree.org/schemas/display/msm/dsi-phy-14nm.yaml#
5+$schema: http://devicetree.org/meta-schemas/core.yaml#
6+
7+title: Qualcomm Display DSI 14nm PHY
8+
9+maintainers:
10+ - Krishna Manikandan <mkrishn@codeaurora.org>
11+
12+allOf:
13+ - $ref: dsi-phy-common.yaml#
14+
15+properties:
16+ compatible:
17+ oneOf:
18+ - const: qcom,dsi-phy-14nm
19+ - const: qcom,dsi-phy-14nm-660
20+
21+ reg:
22+ items:
23+ - description: dsi phy register set
24+ - description: dsi phy lane register set
25+ - description: dsi pll register set
26+
27+ reg-names:
28+ items:
29+ - const: dsi_phy
30+ - const: dsi_phy_lane
31+ - const: dsi_pll
32+
33+ vcca-supply:
34+ description: Phandle to vcca regulator device node.
35+
36+required:
37+ - compatible
38+ - reg
39+ - reg-names
40+ - vcca-supply
41+
42+unevaluatedProperties: false
43+
44+examples:
45+ - |
46+ #include <dt-bindings/clock/qcom,dispcc-sdm845.h>
47+ #include <dt-bindings/clock/qcom,rpmh.h>
48+
49+ dsi-phy@ae94400 {
50+ compatible = "qcom,dsi-phy-14nm";
51+ reg = <0x0ae94400 0x200>,
52+ <0x0ae94600 0x280>,
53+ <0x0ae94a00 0x1e0>;
54+ reg-names = "dsi_phy",
55+ "dsi_phy_lane",
56+ "dsi_pll";
57+
58+ #clock-cells = <1>;
59+ #phy-cells = <0>;
60+
61+ vcca-supply = <&vcca_reg>;
62+ clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
63+ <&rpmhcc RPMH_CXO_CLK>;
64+ clock-names = "iface", "ref";
65+ };
66+...
Documentation/devicetree/bindings/display/msm/dsi-phy-20nm.yaml+71−0
@@ -0,0 +1,71 @@
1+# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
2+%YAML 1.2
3+---
4+$id: http://devicetree.org/schemas/display/msm/dsi-phy-20nm.yaml#
5+$schema: http://devicetree.org/meta-schemas/core.yaml#
6+
7+title: Qualcomm Display DSI 20nm PHY
8+
9+maintainers:
10+ - Krishna Manikandan <mkrishn@codeaurora.org>
11+
12+allOf:
13+ - $ref: dsi-phy-common.yaml#
14+
15+properties:
16+ compatible:
17+ oneOf:
18+ - const: qcom,dsi-phy-20nm
19+
20+ reg:
21+ items:
22+ - description: dsi pll register set
23+ - description: dsi phy register set
24+ - description: dsi phy regulator register set
25+
26+ reg-names:
27+ items:
28+ - const: dsi_pll
29+ - const: dsi_phy
30+ - const: dsi_phy_regulator
31+
32+ vcca-supply:
33+ description: Phandle to vcca regulator device node.
34+
35+ vddio-supply:
36+ description: Phandle to vdd-io regulator device node.
37+
38+required:
39+ - compatible
40+ - reg
41+ - reg-names
42+ - vddio-supply
43+ - vcca-supply
44+
45+unevaluatedProperties: false
46+
47+examples:
48+ - |
49+ #include <dt-bindings/clock/qcom,dispcc-sdm845.h>
50+ #include <dt-bindings/clock/qcom,rpmh.h>
51+
52+ dsi-phy@fd922a00 {
53+ compatible = "qcom,dsi-phy-20nm";
54+ reg = <0xfd922a00 0xd4>,
55+ <0xfd922b00 0x2b0>,
56+ <0xfd922d80 0x7b>;
57+ reg-names = "dsi_pll",
58+ "dsi_phy",
59+ "dsi_phy_regulator";
60+
61+ #clock-cells = <1>;
62+ #phy-cells = <0>;
63+
64+ vcca-supply = <&vcca_reg>;
65+ vddio-supply = <&vddio_reg>;
66+
67+ clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
68+ <&rpmhcc RPMH_CXO_CLK>;
69+ clock-names = "iface", "ref";
70+ };
71+...
Documentation/devicetree/bindings/display/msm/dsi-phy-28nm.yaml+68−0
@@ -0,0 +1,68 @@
1+# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
2+%YAML 1.2
3+---
4+$id: http://devicetree.org/schemas/display/msm/dsi-phy-28nm.yaml#
5+$schema: http://devicetree.org/meta-schemas/core.yaml#
6+
7+title: Qualcomm Display DSI 28nm PHY
8+
9+maintainers:
10+ - Krishna Manikandan <mkrishn@codeaurora.org>
11+
12+allOf:
13+ - $ref: dsi-phy-common.yaml#
14+
15+properties:
16+ compatible:
17+ oneOf:
18+ - const: qcom,dsi-phy-28nm-hpm
19+ - const: qcom,dsi-phy-28nm-lp
20+ - const: qcom,dsi-phy-28nm-8960
21+
22+ reg:
23+ items:
24+ - description: dsi pll register set
25+ - description: dsi phy register set
26+ - description: dsi phy regulator register set
27+
28+ reg-names:
29+ items:
30+ - const: dsi_pll
31+ - const: dsi_phy
32+ - const: dsi_phy_regulator
33+
34+ vddio-supply:
35+ description: Phandle to vdd-io regulator device node.
36+
37+required:
38+ - compatible
39+ - reg
40+ - reg-names
41+ - vddio-supply
42+
43+unevaluatedProperties: false
44+
45+examples:
46+ - |
47+ #include <dt-bindings/clock/qcom,dispcc-sdm845.h>
48+ #include <dt-bindings/clock/qcom,rpmh.h>
49+
50+ dsi-phy@fd922a00 {
51+ compatible = "qcom,dsi-phy-28nm-lp";
52+ reg = <0xfd922a00 0xd4>,
53+ <0xfd922b00 0x2b0>,
54+ <0xfd922d80 0x7b>;
55+ reg-names = "dsi_pll",
56+ "dsi_phy",
57+ "dsi_phy_regulator";
58+
59+ #clock-cells = <1>;
60+ #phy-cells = <0>;
61+
62+ vddio-supply = <&vddio_reg>;
63+
64+ clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
65+ <&rpmhcc RPMH_CXO_CLK>;
66+ clock-names = "iface", "ref";
67+ };
68+...
Documentation/devicetree/bindings/display/msm/dsi-phy-common.yaml+40−0
@@ -0,0 +1,40 @@
1+# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
2+%YAML 1.2
3+---
4+$id: http://devicetree.org/schemas/display/msm/dsi-phy-common.yaml#
5+$schema: http://devicetree.org/meta-schemas/core.yaml#
6+
7+title: Description of Qualcomm Display DSI PHY common dt properties
8+
9+maintainers:
10+ - Krishna Manikandan <mkrishn@codeaurora.org>
11+
12+description: |
13+ This defines the DSI PHY dt properties which are common for all
14+ dsi phy versions.
15+
16+properties:
17+ "#clock-cells":
18+ const: 1
19+
20+ "#phy-cells":
21+ const: 0
22+
23+ clocks:
24+ items:
25+ - description: Display AHB clock
26+ - description: Board XO source
27+
28+ clock-names:
29+ items:
30+ - const: iface
31+ - const: ref
32+
33+required:
34+ - clocks
35+ - clock-names
36+ - "#clock-cells"
37+ - "#phy-cells"
38+
39+additionalProperties: true
40+...
Documentation/devicetree/bindings/display/msm/dsi.txt+0−249
@@ -1,249 +0,0 @@
1−Qualcomm Technologies Inc. adreno/snapdragon DSI output
2−
3−DSI Controller:
4−Required properties:
5−- compatible:
6− * "qcom,mdss-dsi-ctrl"
7−- reg: Physical base address and length of the registers of controller
8−- reg-names: The names of register regions. The following regions are required:
9− * "dsi_ctrl"
10−- interrupts: The interrupt signal from the DSI block.
11−- power-domains: Should be <&mmcc MDSS_GDSC>.
12−- clocks: Phandles to device clocks.
13−- clock-names: the following clocks are required:
14− * "mdp_core"
15− * "iface"
16− * "bus"
17− * "core_mmss"
18− * "byte"
19− * "pixel"
20− * "core"
21− For DSIv2, we need an additional clock:
22− * "src"
23− For DSI6G v2.0 onwards, we need also need the clock:
24− * "byte_intf"
25−- assigned-clocks: Parents of "byte" and "pixel" for the given platform.
26−- assigned-clock-parents: The Byte clock and Pixel clock PLL outputs provided
27− by a DSI PHY block. See [1] for details on clock bindings.
28−- vdd-supply: phandle to vdd regulator device node
29−- vddio-supply: phandle to vdd-io regulator device node
30−- vdda-supply: phandle to vdda regulator device node
31−- phys: phandle to DSI PHY device node
32−- phy-names: the name of the corresponding PHY device
33−- syscon-sfpb: A phandle to mmss_sfpb syscon node (only for DSIv2)
34−- ports: Contains 2 DSI controller ports as child nodes. Each port contains
35− an endpoint subnode as defined in [2] and [3].
36−
37−Optional properties:
38−- panel@0: Node of panel connected to this DSI controller.
39− See files in [4] for each supported panel.
40−- qcom,dual-dsi-mode: Boolean value indicating if the DSI controller is
41− driving a panel which needs 2 DSI links.
42−- qcom,master-dsi: Boolean value indicating if the DSI controller is driving
43− the master link of the 2-DSI panel.
44−- qcom,sync-dual-dsi: Boolean value indicating if the DSI controller is
45− driving a 2-DSI panel whose 2 links need receive command simultaneously.
46−- pinctrl-names: the pin control state names; should contain "default"
47−- pinctrl-0: the default pinctrl state (active)
48−- pinctrl-n: the "sleep" pinctrl state
49−- ports: contains DSI controller input and output ports as children, each
50− containing one endpoint subnode.
51−
52− DSI Endpoint properties:
53− - remote-endpoint: For port@0, set to phandle of the connected panel/bridge's
54− input endpoint. For port@1, set to the MDP interface output. See [2] for
55− device graph info.
56−
57− - data-lanes: this describes how the physical DSI data lanes are mapped
58− to the logical lanes on the given platform. The value contained in
59− index n describes what physical lane is mapped to the logical lane n
60− (DATAn, where n lies between 0 and 3). The clock lane position is fixed
61− and can't be changed. Hence, they aren't a part of the DT bindings. See
62− [3] for more info on the data-lanes property.
63−
64− For example:
65−
66− data-lanes = <3 0 1 2>;
67−
68− The above mapping describes that the logical data lane DATA0 is mapped to
69− the physical data lane DATA3, logical DATA1 to physical DATA0, logic DATA2
70− to phys DATA1 and logic DATA3 to phys DATA2.
71−
72− There are only a limited number of physical to logical mappings possible:
73− <0 1 2 3>
74− <1 2 3 0>
75− <2 3 0 1>
76− <3 0 1 2>
77− <0 3 2 1>
78− <1 0 3 2>
79− <2 1 0 3>
80− <3 2 1 0>
81−
82−DSI PHY:
83−Required properties:
84−- compatible: Could be the following
85− * "qcom,dsi-phy-28nm-hpm"
86− * "qcom,dsi-phy-28nm-lp"
87− * "qcom,dsi-phy-20nm"
88− * "qcom,dsi-phy-28nm-8960"
89− * "qcom,dsi-phy-14nm"
90− * "qcom,dsi-phy-14nm-660"
91− * "qcom,dsi-phy-10nm"
92− * "qcom,dsi-phy-10nm-8998"
93− * "qcom,dsi-phy-7nm"
94− * "qcom,dsi-phy-7nm-8150"
95−- reg: Physical base address and length of the registers of PLL, PHY. Some
96− revisions require the PHY regulator base address, whereas others require the
97− PHY lane base address. See below for each PHY revision.
98−- reg-names: The names of register regions. The following regions are required:
99− For DSI 28nm HPM/LP/8960 PHYs and 20nm PHY:
100− * "dsi_pll"
101− * "dsi_phy"
102− * "dsi_phy_regulator"
103− For DSI 14nm, 10nm and 7nm PHYs:
104− * "dsi_pll"
105− * "dsi_phy"
106− * "dsi_phy_lane"
107−- clock-cells: Must be 1. The DSI PHY block acts as a clock provider, creating
108− 2 clocks: A byte clock (index 0), and a pixel clock (index 1).
109−- power-domains: Should be <&mmcc MDSS_GDSC>.
110−- clocks: Phandles to device clocks. See [1] for details on clock bindings.
111−- clock-names: the following clocks are required:
112− * "iface"
113− * "ref" (only required for new DTS files/entries)
114− For 28nm HPM/LP, 28nm 8960 PHYs:
115−- vddio-supply: phandle to vdd-io regulator device node
116− For 20nm PHY:
117−- vddio-supply: phandle to vdd-io regulator device node
118−- vcca-supply: phandle to vcca regulator device node
119− For 14nm PHY:
120−- vcca-supply: phandle to vcca regulator device node
121− For 10nm and 7nm PHY:
122−- vdds-supply: phandle to vdds regulator device node
123−
124−Optional properties:
125−- qcom,dsi-phy-regulator-ldo-mode: Boolean value indicating if the LDO mode PHY
126− regulator is wanted.
127−- qcom,mdss-mdp-transfer-time-us: Specifies the dsi transfer time for command mode
128− panels in microseconds. Driver uses this number to adjust
129− the clock rate according to the expected transfer time.
130− Increasing this value would slow down the mdp processing
131− and can result in slower performance.
132− Decreasing this value can speed up the mdp processing,
133− but this can also impact power consumption.
134− As a rule this time should not be higher than the time
135− that would be expected with the processing at the
136− dsi link rate since anyways this would be the maximum
137− transfer time that could be achieved.
138− If ping pong split is enabled, this time should not be higher
139− than two times the dsi link rate time.
140− If the property is not specified, then the default value is 14000 us.
141−
142−[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
143−[2] Documentation/devicetree/bindings/graph.txt
144−[3] Documentation/devicetree/bindings/media/video-interfaces.txt
145−[4] Documentation/devicetree/bindings/display/panel/
146−
147−Example:
148− dsi0: dsi@fd922800 {
149− compatible = "qcom,mdss-dsi-ctrl";
150− qcom,dsi-host-index = <0>;
151− interrupt-parent = <&mdp>;
152− interrupts = <4 0>;
153− reg-names = "dsi_ctrl";
154− reg = <0xfd922800 0x200>;
155− power-domains = <&mmcc MDSS_GDSC>;
156− clock-names =
157− "bus",
158− "byte",
159− "core",
160− "core_mmss",
161− "iface",
162− "mdp_core",
163− "pixel";
164− clocks =
165− <&mmcc MDSS_AXI_CLK>,
166− <&mmcc MDSS_BYTE0_CLK>,
167− <&mmcc MDSS_ESC0_CLK>,
168− <&mmcc MMSS_MISC_AHB_CLK>,
169− <&mmcc MDSS_AHB_CLK>,
170− <&mmcc MDSS_MDP_CLK>,
171− <&mmcc MDSS_PCLK0_CLK>;
172−
173− assigned-clocks =
174− <&mmcc BYTE0_CLK_SRC>,
175− <&mmcc PCLK0_CLK_SRC>;
176− assigned-clock-parents =
177− <&dsi_phy0 0>,
178− <&dsi_phy0 1>;
179−
180− vdda-supply = <&pma8084_l2>;
181− vdd-supply = <&pma8084_l22>;
182− vddio-supply = <&pma8084_l12>;
183−
184− phys = <&dsi_phy0>;
185− phy-names ="dsi-phy";
186−
187− qcom,dual-dsi-mode;
188− qcom,master-dsi;
189− qcom,sync-dual-dsi;
190−
191− qcom,mdss-mdp-transfer-time-us = <12000>;
192−
193− pinctrl-names = "default", "sleep";
194− pinctrl-0 = <&dsi_active>;
195− pinctrl-1 = <&dsi_suspend>;
196−
197− ports {
198− #address-cells = <1>;
199− #size-cells = <0>;
200−
201− port@0 {
202− reg = <0>;
203− dsi0_in: endpoint {
204− remote-endpoint = <&mdp_intf1_out>;
205− };
206− };
207−
208− port@1 {
209− reg = <1>;
210− dsi0_out: endpoint {
211− remote-endpoint = <&panel_in>;
212− data-lanes = <0 1 2 3>;
213− };
214− };
215− };
216−
217− panel: panel@0 {
218− compatible = "sharp,lq101r1sx01";
219− reg = <0>;
220− link2 = <&secondary>;
221−
222− power-supply = <...>;
223− backlight = <...>;
224−
225− port {
226− panel_in: endpoint {
227− remote-endpoint = <&dsi0_out>;
228− };
229− };
230− };
231− };
232−
233− dsi_phy0: dsi-phy@fd922a00 {
234− compatible = "qcom,dsi-phy-28nm-hpm";
235− qcom,dsi-phy-index = <0>;
236− reg-names =
237− "dsi_pll",
238− "dsi_phy",
239− "dsi_phy_regulator";
240− reg = <0xfd922a00 0xd4>,
241− <0xfd922b00 0x2b0>,
242− <0xfd922d80 0x7b>;
243− clock-names = "iface";
244− clocks = <&mmcc MDSS_AHB_CLK>;
245− #clock-cells = <1>;
246− vddio-supply = <&pma8084_l12>;
247−
248− qcom,dsi-phy-regulator-ldo-mode;
249− };
drivers/gpu/drm/drm_atomic.c+23−5
@@ -1,6 +1,7 @@
11 /*
22 * Copyright (C) 2014 Red Hat
33 * Copyright (C) 2014 Intel Corp.
4+ * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved.
45 *
56 * Permission is hereby granted, free of charge, to any person obtaining a
67 * copy of this software and associated documentation files (the "Software"),
@@ -1609,9 +1610,20 @@ commit: · 1602 unmodified lines
16091610 }
16101611 EXPORT_SYMBOL(__drm_atomic_helper_set_config);
16111612
1612−void drm_atomic_print_state(const struct drm_atomic_state *state)
1613+/**
1614+ * drm_atomic_print_new_state - prints drm atomic state
1615+ * @state: atomic configuration to check
1616+ * @p: drm printer
1617+ *
1618+ * This functions prints the drm atomic state snapshot using the drm printer
1619+ * which is passed to it. This snapshot can be used for debugging purposes.
1620+ *
1621+ * Note that this function looks into the new state objects and hence its not
1622+ * safe to be used after the call to drm_atomic_helper_commit_hw_done().
1623+ */
1624+void drm_atomic_print_new_state(const struct drm_atomic_state *state,
1625+ struct drm_printer *p)
16131626 {
1614− struct drm_printer p = drm_info_printer(state->dev->dev);
16151627 struct drm_plane *plane;
16161628 struct drm_plane_state *plane_state;
16171629 struct drm_crtc *crtc;
@@ -1620,17 +1632,23 @@ void drm_atomic_print_state(const struct drm_atomic_state *state) · 2 unmodified lines
16201632 struct drm_connector_state *connector_state;
16211633 int i;
16221634
1635+ if (!p) {
1636+ DRM_ERROR("invalid drm printer\n");
1637+ return;
1638+ }
1639+
16231640 DRM_DEBUG_ATOMIC("checking %p\n", state);
16241641
16251642 for_each_new_plane_in_state(state, plane, plane_state, i)
1626− drm_atomic_plane_print_state(&p, plane_state);
1643+ drm_atomic_plane_print_state(p, plane_state);
16271644
16281645 for_each_new_crtc_in_state(state, crtc, crtc_state, i)
1629− drm_atomic_crtc_print_state(&p, crtc_state);
1646+ drm_atomic_crtc_print_state(p, crtc_state);
16301647
16311648 for_each_new_connector_in_state(state, connector, connector_state, i)
1632− drm_atomic_connector_print_state(&p, connector_state);
1649+ drm_atomic_connector_print_state(p, connector_state);
16331650 }
1651+EXPORT_SYMBOL(drm_atomic_print_new_state);
16341652
16351653 static void __drm_state_dump(struct drm_device *dev, struct drm_printer *p,
16361654 bool take_locks)
drivers/gpu/drm/drm_atomic_uapi.c+3−1
@@ -2,6 +2,7 @@ · 1 unmodified line
22 * Copyright (C) 2014 Red Hat
33 * Copyright (C) 2014 Intel Corp.
44 * Copyright (C) 2018 Intel Corp.
5+ * Copyright (c) 2020, The Linux Foundation. All rights reserved.
56 *
67 * Permission is hereby granted, free of charge, to any person obtaining a
78 * copy of this software and associated documentation files (the "Software"),
@@ -1321,6 +1322,7 @@ int drm_mode_atomic_ioctl(struct drm_device *dev, · 1313 unmodified lines
13211322 struct drm_out_fence_state *fence_state;
13221323 int ret = 0;
13231324 unsigned int i, j, num_fences;
1325+ struct drm_printer p = drm_info_printer(dev->dev);
13241326
13251327 /* disallow for drivers not supporting atomic: */
13261328 if (!drm_core_check_feature(dev, DRIVER_ATOMIC))
@@ -1453,7 +1455,7 @@ retry: · 126 unmodified lines
14531455 ret = drm_atomic_nonblocking_commit(state);
14541456 } else {
14551457 if (drm_debug_enabled(DRM_UT_STATE))
1456− drm_atomic_print_state(state);
1458+ drm_atomic_print_new_state(state, &p);
14571459
14581460 ret = drm_atomic_commit(state);
14591461 }
drivers/gpu/drm/drm_crtc_internal.h+3−1
@@ -5,6 +5,7 @@ · 4 unmodified lines
55 * Jesse Barnes <jesse.barnes@intel.com>
66 * Copyright © 2014 Intel Corporation
77 * Daniel Vetter <daniel.vetter@ffwll.ch>
8+ * Copyright (c) 2020, The Linux Foundation. All rights reserved.
89 *
910 * Permission is hereby granted, free of charge, to any person obtaining a
1011 * copy of this software and associated documentation files (the "Software"),
@@ -236,7 +237,8 @@ int __drm_atomic_helper_disable_plane(struct drm_plane *plane, · 225 unmodified lines
236237 int __drm_atomic_helper_set_config(struct drm_mode_set *set,
237238 struct drm_atomic_state *state);
238239
239−void drm_atomic_print_state(const struct drm_atomic_state *state);
240+void drm_atomic_print_new_state(const struct drm_atomic_state *state,
241+ struct drm_printer *p);
240242
241243 /* drm_atomic_uapi.c */
242244 int drm_atomic_connector_commit_dpms(struct drm_atomic_state *state,
drivers/gpu/drm/msm/Makefile+2−1
@@ -58,7 +58,6 @@ msm-y := \ · 57 unmodified lines
5858 disp/dpu1/dpu_encoder_phys_cmd.o \
5959 disp/dpu1/dpu_encoder_phys_vid.o \
6060 disp/dpu1/dpu_formats.o \
61− disp/dpu1/dpu_hw_blk.o \
6261 disp/dpu1/dpu_hw_catalog.o \
6362 disp/dpu1/dpu_hw_ctl.o \
6463 disp/dpu1/dpu_hw_interrupts.o \
@@ -77,6 +76,8 @@ msm-y := \ · 12 unmodified lines
7776 disp/dpu1/dpu_plane.o \
7877 disp/dpu1/dpu_rm.o \
7978 disp/dpu1/dpu_vbif.o \
79+ disp/msm_disp_snapshot.o \
80+ disp/msm_disp_snapshot_util.o \
8081 msm_atomic.o \
8182 msm_atomic_tracepoints.o \
8283 msm_debugfs.o \
drivers/gpu/drm/msm/adreno/a2xx.xml.h+42−18
@@ -8,21 +8,21 @@ http://github.com/freedreno/envytools/ · 7 unmodified lines
88 git clone https://github.com/freedreno/envytools.git
99
1010 The rules-ng-ng source files this header was generated from are:
11−- /home/robclark/src/envytools/rnndb/adreno.xml ( 594 bytes, from 2020-07-23 21:58:14)
12−- /home/robclark/src/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2020-07-23 21:58:14)
13−- /home/robclark/src/envytools/rnndb/adreno/a2xx.xml ( 90159 bytes, from 2020-07-23 21:58:14)
14−- /home/robclark/src/envytools/rnndb/adreno/adreno_common.xml ( 14386 bytes, from 2020-07-23 21:58:14)
15−- /home/robclark/src/envytools/rnndb/adreno/adreno_pm4.xml ( 65048 bytes, from 2020-07-23 21:58:14)
16−- /home/robclark/src/envytools/rnndb/adreno/a3xx.xml ( 84226 bytes, from 2020-07-23 21:58:14)
17−- /home/robclark/src/envytools/rnndb/adreno/a4xx.xml ( 112556 bytes, from 2020-07-23 21:58:14)
18−- /home/robclark/src/envytools/rnndb/adreno/a5xx.xml ( 149461 bytes, from 2020-07-23 21:58:14)
19−- /home/robclark/src/envytools/rnndb/adreno/a6xx.xml ( 184695 bytes, from 2020-07-23 21:58:14)
20−- /home/robclark/src/envytools/rnndb/adreno/a6xx_gmu.xml ( 11218 bytes, from 2020-07-23 21:58:14)
21−- /home/robclark/src/envytools/rnndb/adreno/ocmem.xml ( 1773 bytes, from 2020-07-23 21:58:14)
22−- /home/robclark/src/envytools/rnndb/adreno/adreno_control_regs.xml ( 4559 bytes, from 2020-07-23 21:58:14)
23−- /home/robclark/src/envytools/rnndb/adreno/adreno_pipe_regs.xml ( 2872 bytes, from 2020-07-23 21:58:14)
24−
25−Copyright (C) 2013-2020 by the following authors:
11+- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno.xml ( 594 bytes, from 2021-02-18 16:45:44)
12+- /home/robclark/src/mesa/mesa/src/freedreno/registers/freedreno_copyright.xml ( 1572 bytes, from 2021-02-18 16:45:44)
13+- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a2xx.xml ( 90810 bytes, from 2021-02-18 16:45:44)
14+- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_common.xml ( 14386 bytes, from 2021-02-18 16:45:44)
15+- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_pm4.xml ( 67699 bytes, from 2021-05-31 20:21:57)
16+- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a3xx.xml ( 84226 bytes, from 2021-02-18 16:45:44)
17+- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a4xx.xml ( 112551 bytes, from 2021-02-18 16:45:44)
18+- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a5xx.xml ( 150713 bytes, from 2021-06-10 22:34:02)
19+- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a6xx.xml ( 180049 bytes, from 2021-06-02 21:44:19)
20+- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a6xx_gmu.xml ( 11331 bytes, from 2021-05-21 19:18:08)
21+- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/ocmem.xml ( 1773 bytes, from 2021-02-18 16:45:44)
22+- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_control_regs.xml ( 6038 bytes, from 2021-05-27 20:22:36)
23+- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_pipe_regs.xml ( 2924 bytes, from 2021-05-27 20:18:13)
24+
25+Copyright (C) 2013-2021 by the following authors:
2626 - Rob Clark <robdclark@gmail.com> (robclark)
2727 - Ilia Mirkin <imirkin@alum.mit.edu> (imirkin)
2828
@@ -1258,11 +1258,17 @@ static inline uint32_t A2XX_MH_MMU_VA_RANGE_VA_BASE(uint32_t val) · 1229 unmodified lines
12581258
12591259 #define REG_A2XX_NQWAIT_UNTIL 0x00000394
12601260
1261−#define REG_A2XX_RBBM_PERFCOUNTER1_SELECT 0x00000395
1261+#define REG_A2XX_RBBM_PERFCOUNTER0_SELECT 0x00000395
12621262
1263−#define REG_A2XX_RBBM_PERFCOUNTER1_LO 0x00000397
1263+#define REG_A2XX_RBBM_PERFCOUNTER1_SELECT 0x00000396
12641264
1265−#define REG_A2XX_RBBM_PERFCOUNTER1_HI 0x00000398
1265+#define REG_A2XX_RBBM_PERFCOUNTER0_LO 0x00000397
1266+
1267+#define REG_A2XX_RBBM_PERFCOUNTER0_HI 0x00000398
1268+
1269+#define REG_A2XX_RBBM_PERFCOUNTER1_LO 0x00000399
1270+
1271+#define REG_A2XX_RBBM_PERFCOUNTER1_HI 0x0000039a
12661272
12671273 #define REG_A2XX_RBBM_DEBUG 0x0000039b
12681274
@@ -2922,10 +2928,28 @@ static inline uint32_t A2XX_RB_COPY_DEST_OFFSET_Y(uint32_t val) · 1653 unmodified lines
29222928
29232929 #define REG_A2XX_RB_PERFCOUNTER0_SELECT 0x00000f04
29242930
2931+#define REG_A2XX_RB_PERFCOUNTER1_SELECT 0x00000f05
2932+
2933+#define REG_A2XX_RB_PERFCOUNTER2_SELECT 0x00000f06
2934+
2935+#define REG_A2XX_RB_PERFCOUNTER3_SELECT 0x00000f07
2936+
29252937 #define REG_A2XX_RB_PERFCOUNTER0_LOW 0x00000f08
29262938
29272939 #define REG_A2XX_RB_PERFCOUNTER0_HI 0x00000f09
29282940
2941+#define REG_A2XX_RB_PERFCOUNTER1_LOW 0x00000f0a
2942+
2943+#define REG_A2XX_RB_PERFCOUNTER1_HI 0x00000f0b
2944+
2945+#define REG_A2XX_RB_PERFCOUNTER2_LOW 0x00000f0c
2946+
2947+#define REG_A2XX_RB_PERFCOUNTER2_HI 0x00000f0d
2948+
2949+#define REG_A2XX_RB_PERFCOUNTER3_LOW 0x00000f0e
2950+
2951+#define REG_A2XX_RB_PERFCOUNTER3_HI 0x00000f0f
2952+
29292953 #define REG_A2XX_SQ_TEX_0 0x00000000
29302954 #define A2XX_SQ_TEX_0_TYPE__MASK 0x00000003
29312955 #define A2XX_SQ_TEX_0_TYPE__SHIFT 0
drivers/gpu/drm/msm/adreno/a3xx.xml.h+20−20
@@ -8,21 +8,21 @@ http://github.com/freedreno/envytools/ · 7 unmodified lines
88 git clone https://github.com/freedreno/envytools.git
99
1010 The rules-ng-ng source files this header was generated from are:
11−- /home/robclark/src/envytools/rnndb/adreno.xml ( 594 bytes, from 2020-07-23 21:58:14)
12−- /home/robclark/src/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2020-07-23 21:58:14)
13−- /home/robclark/src/envytools/rnndb/adreno/a2xx.xml ( 90159 bytes, from 2020-07-23 21:58:14)
14−- /home/robclark/src/envytools/rnndb/adreno/adreno_common.xml ( 14386 bytes, from 2020-07-23 21:58:14)
15−- /home/robclark/src/envytools/rnndb/adreno/adreno_pm4.xml ( 65048 bytes, from 2020-07-23 21:58:14)
16−- /home/robclark/src/envytools/rnndb/adreno/a3xx.xml ( 84226 bytes, from 2020-07-23 21:58:14)
17−- /home/robclark/src/envytools/rnndb/adreno/a4xx.xml ( 112556 bytes, from 2020-07-23 21:58:14)
18−- /home/robclark/src/envytools/rnndb/adreno/a5xx.xml ( 149461 bytes, from 2020-07-23 21:58:14)
19−- /home/robclark/src/envytools/rnndb/adreno/a6xx.xml ( 184695 bytes, from 2020-07-23 21:58:14)
20−- /home/robclark/src/envytools/rnndb/adreno/a6xx_gmu.xml ( 11218 bytes, from 2020-07-23 21:58:14)
21−- /home/robclark/src/envytools/rnndb/adreno/ocmem.xml ( 1773 bytes, from 2020-07-23 21:58:14)
22−- /home/robclark/src/envytools/rnndb/adreno/adreno_control_regs.xml ( 4559 bytes, from 2020-07-23 21:58:14)
23−- /home/robclark/src/envytools/rnndb/adreno/adreno_pipe_regs.xml ( 2872 bytes, from 2020-07-23 21:58:14)
24−
25−Copyright (C) 2013-2020 by the following authors:
11+- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno.xml ( 594 bytes, from 2021-02-18 16:45:44)
12+- /home/robclark/src/mesa/mesa/src/freedreno/registers/freedreno_copyright.xml ( 1572 bytes, from 2021-02-18 16:45:44)
13+- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a2xx.xml ( 90810 bytes, from 2021-02-18 16:45:44)
14+- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_common.xml ( 14386 bytes, from 2021-02-18 16:45:44)
15+- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_pm4.xml ( 67699 bytes, from 2021-05-31 20:21:57)
16+- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a3xx.xml ( 84226 bytes, from 2021-02-18 16:45:44)
17+- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a4xx.xml ( 112551 bytes, from 2021-02-18 16:45:44)
18+- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a5xx.xml ( 150713 bytes, from 2021-06-10 22:34:02)
19+- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a6xx.xml ( 180049 bytes, from 2021-06-02 21:44:19)
20+- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a6xx_gmu.xml ( 11331 bytes, from 2021-05-21 19:18:08)
21+- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/ocmem.xml ( 1773 bytes, from 2021-02-18 16:45:44)
22+- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_control_regs.xml ( 6038 bytes, from 2021-05-27 20:22:36)
23+- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_pipe_regs.xml ( 2924 bytes, from 2021-05-27 20:18:13)
24+
25+Copyright (C) 2013-2021 by the following authors:
2626 - Rob Clark <robdclark@gmail.com> (robclark)
2727 - Ilia Mirkin <imirkin@alum.mit.edu> (imirkin)
2828
@@ -1215,7 +1215,7 @@ static inline uint32_t A3XX_RB_ALPHA_REF_UINT(uint32_t val) · 1186 unmodified lines
12151215 #define A3XX_RB_ALPHA_REF_FLOAT__SHIFT 16
12161216 static inline uint32_t A3XX_RB_ALPHA_REF_FLOAT(float val)
12171217 {
1218− return ((util_float_to_half(val)) << A3XX_RB_ALPHA_REF_FLOAT__SHIFT) & A3XX_RB_ALPHA_REF_FLOAT__MASK;
1218+ return ((_mesa_float_to_half(val)) << A3XX_RB_ALPHA_REF_FLOAT__SHIFT) & A3XX_RB_ALPHA_REF_FLOAT__MASK;
12191219 }
12201220
12211221 static inline uint32_t REG_A3XX_RB_MRT(uint32_t i0) { return 0x000020c4 + 0x4*i0; }
@@ -1328,7 +1328,7 @@ static inline uint32_t A3XX_RB_BLEND_RED_UINT(uint32_t val) · 106 unmodified lines
13281328 #define A3XX_RB_BLEND_RED_FLOAT__SHIFT 16
13291329 static inline uint32_t A3XX_RB_BLEND_RED_FLOAT(float val)
13301330 {
1331− return ((util_float_to_half(val)) << A3XX_RB_BLEND_RED_FLOAT__SHIFT) & A3XX_RB_BLEND_RED_FLOAT__MASK;
1331+ return ((_mesa_float_to_half(val)) << A3XX_RB_BLEND_RED_FLOAT__SHIFT) & A3XX_RB_BLEND_RED_FLOAT__MASK;
13321332 }
13331333
13341334 #define REG_A3XX_RB_BLEND_GREEN 0x000020e5
@@ -1342,7 +1342,7 @@ static inline uint32_t A3XX_RB_BLEND_GREEN_UINT(uint32_t val) · 7 unmodified lines
13421342 #define A3XX_RB_BLEND_GREEN_FLOAT__SHIFT 16
13431343 static inline uint32_t A3XX_RB_BLEND_GREEN_FLOAT(float val)
13441344 {
1345− return ((util_float_to_half(val)) << A3XX_RB_BLEND_GREEN_FLOAT__SHIFT) & A3XX_RB_BLEND_GREEN_FLOAT__MASK;
1345+ return ((_mesa_float_to_half(val)) << A3XX_RB_BLEND_GREEN_FLOAT__SHIFT) & A3XX_RB_BLEND_GREEN_FLOAT__MASK;
13461346 }
13471347
13481348 #define REG_A3XX_RB_BLEND_BLUE 0x000020e6
@@ -1356,7 +1356,7 @@ static inline uint32_t A3XX_RB_BLEND_BLUE_UINT(uint32_t val) · 7 unmodified lines
13561356 #define A3XX_RB_BLEND_BLUE_FLOAT__SHIFT 16
13571357 static inline uint32_t A3XX_RB_BLEND_BLUE_FLOAT(float val)
13581358 {
1359− return ((util_float_to_half(val)) << A3XX_RB_BLEND_BLUE_FLOAT__SHIFT) & A3XX_RB_BLEND_BLUE_FLOAT__MASK;
1359+ return ((_mesa_float_to_half(val)) << A3XX_RB_BLEND_BLUE_FLOAT__SHIFT) & A3XX_RB_BLEND_BLUE_FLOAT__MASK;
13601360 }
13611361
13621362 #define REG_A3XX_RB_BLEND_ALPHA 0x000020e7
@@ -1370,7 +1370,7 @@ static inline uint32_t A3XX_RB_BLEND_ALPHA_UINT(uint32_t val) · 7 unmodified lines
13701370 #define A3XX_RB_BLEND_ALPHA_FLOAT__SHIFT 16
13711371 static inline uint32_t A3XX_RB_BLEND_ALPHA_FLOAT(float val)
13721372 {
1373− return ((util_float_to_half(val)) << A3XX_RB_BLEND_ALPHA_FLOAT__SHIFT) & A3XX_RB_BLEND_ALPHA_FLOAT__MASK;
1373+ return ((_mesa_float_to_half(val)) << A3XX_RB_BLEND_ALPHA_FLOAT__SHIFT) & A3XX_RB_BLEND_ALPHA_FLOAT__MASK;
13741374 }
13751375
13761376 #define REG_A3XX_RB_CLEAR_COLOR_DW0 0x000020e8
drivers/gpu/drm/msm/adreno/a4xx.xml.h+19−19
@@ -8,21 +8,21 @@ http://github.com/freedreno/envytools/ · 7 unmodified lines
88 git clone https://github.com/freedreno/envytools.git
99
1010 The rules-ng-ng source files this header was generated from are:
11−- /home/robclark/src/envytools/rnndb/adreno.xml ( 594 bytes, from 2020-07-23 21:58:14)
12−- /home/robclark/src/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2020-07-23 21:58:14)
13−- /home/robclark/src/envytools/rnndb/adreno/a2xx.xml ( 90159 bytes, from 2020-07-23 21:58:14)
14−- /home/robclark/src/envytools/rnndb/adreno/adreno_common.xml ( 14386 bytes, from 2020-07-23 21:58:14)
15−- /home/robclark/src/envytools/rnndb/adreno/adreno_pm4.xml ( 65048 bytes, from 2020-07-23 21:58:14)
16−- /home/robclark/src/envytools/rnndb/adreno/a3xx.xml ( 84226 bytes, from 2020-07-23 21:58:14)
17−- /home/robclark/src/envytools/rnndb/adreno/a4xx.xml ( 112556 bytes, from 2020-07-23 21:58:14)
18−- /home/robclark/src/envytools/rnndb/adreno/a5xx.xml ( 149461 bytes, from 2020-07-23 21:58:14)
19−- /home/robclark/src/envytools/rnndb/adreno/a6xx.xml ( 184695 bytes, from 2020-07-23 21:58:14)
20−- /home/robclark/src/envytools/rnndb/adreno/a6xx_gmu.xml ( 11218 bytes, from 2020-07-23 21:58:14)
21−- /home/robclark/src/envytools/rnndb/adreno/ocmem.xml ( 1773 bytes, from 2020-07-23 21:58:14)
22−- /home/robclark/src/envytools/rnndb/adreno/adreno_control_regs.xml ( 4559 bytes, from 2020-07-23 21:58:14)
23−- /home/robclark/src/envytools/rnndb/adreno/adreno_pipe_regs.xml ( 2872 bytes, from 2020-07-23 21:58:14)
24−
25−Copyright (C) 2013-2020 by the following authors:
11+- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno.xml ( 594 bytes, from 2021-02-18 16:45:44)
12+- /home/robclark/src/mesa/mesa/src/freedreno/registers/freedreno_copyright.xml ( 1572 bytes, from 2021-02-18 16:45:44)
13+- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a2xx.xml ( 90810 bytes, from 2021-02-18 16:45:44)
14+- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_common.xml ( 14386 bytes, from 2021-02-18 16:45:44)
15+- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_pm4.xml ( 67699 bytes, from 2021-05-31 20:21:57)
16+- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a3xx.xml ( 84226 bytes, from 2021-02-18 16:45:44)
17+- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a4xx.xml ( 112551 bytes, from 2021-02-18 16:45:44)
18+- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a5xx.xml ( 150713 bytes, from 2021-06-10 22:34:02)
19+- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a6xx.xml ( 180049 bytes, from 2021-06-02 21:44:19)
20+- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a6xx_gmu.xml ( 11331 bytes, from 2021-05-21 19:18:08)
21+- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/ocmem.xml ( 1773 bytes, from 2021-02-18 16:45:44)
22+- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_control_regs.xml ( 6038 bytes, from 2021-05-27 20:22:36)
23+- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_pipe_regs.xml ( 2924 bytes, from 2021-05-27 20:18:13)
24+
25+Copyright (C) 2013-2021 by the following authors:
2626 - Rob Clark <robdclark@gmail.com> (robclark)
2727 - Ilia Mirkin <imirkin@alum.mit.edu> (imirkin)
2828
@@ -1085,7 +1085,7 @@ static inline uint32_t A4XX_RB_BLEND_RED_SINT(uint32_t val) · 1056 unmodified lines
10851085 #define A4XX_RB_BLEND_RED_FLOAT__SHIFT 16
10861086 static inline uint32_t A4XX_RB_BLEND_RED_FLOAT(float val)
10871087 {
1088− return ((util_float_to_half(val)) << A4XX_RB_BLEND_RED_FLOAT__SHIFT) & A4XX_RB_BLEND_RED_FLOAT__MASK;
1088+ return ((_mesa_float_to_half(val)) << A4XX_RB_BLEND_RED_FLOAT__SHIFT) & A4XX_RB_BLEND_RED_FLOAT__MASK;
10891089 }
10901090
10911091 #define REG_A4XX_RB_BLEND_RED_F32 0x000020f1
@@ -1113,7 +1113,7 @@ static inline uint32_t A4XX_RB_BLEND_GREEN_SINT(uint32_t val) · 21 unmodified lines
11131113 #define A4XX_RB_BLEND_GREEN_FLOAT__SHIFT 16
11141114 static inline uint32_t A4XX_RB_BLEND_GREEN_FLOAT(float val)
11151115 {
1116− return ((util_float_to_half(val)) << A4XX_RB_BLEND_GREEN_FLOAT__SHIFT) & A4XX_RB_BLEND_GREEN_FLOAT__MASK;
1116+ return ((_mesa_float_to_half(val)) << A4XX_RB_BLEND_GREEN_FLOAT__SHIFT) & A4XX_RB_BLEND_GREEN_FLOAT__MASK;
11171117 }
11181118
11191119 #define REG_A4XX_RB_BLEND_GREEN_F32 0x000020f3
@@ -1141,7 +1141,7 @@ static inline uint32_t A4XX_RB_BLEND_BLUE_SINT(uint32_t val) · 21 unmodified lines
11411141 #define A4XX_RB_BLEND_BLUE_FLOAT__SHIFT 16
11421142 static inline uint32_t A4XX_RB_BLEND_BLUE_FLOAT(float val)
11431143 {
1144− return ((util_float_to_half(val)) << A4XX_RB_BLEND_BLUE_FLOAT__SHIFT) & A4XX_RB_BLEND_BLUE_FLOAT__MASK;
1144+ return ((_mesa_float_to_half(val)) << A4XX_RB_BLEND_BLUE_FLOAT__SHIFT) & A4XX_RB_BLEND_BLUE_FLOAT__MASK;
11451145 }
11461146
11471147 #define REG_A4XX_RB_BLEND_BLUE_F32 0x000020f5
@@ -1169,7 +1169,7 @@ static inline uint32_t A4XX_RB_BLEND_ALPHA_SINT(uint32_t val) · 21 unmodified lines
11691169 #define A4XX_RB_BLEND_ALPHA_FLOAT__SHIFT 16
11701170 static inline uint32_t A4XX_RB_BLEND_ALPHA_FLOAT(float val)
11711171 {
1172− return ((util_float_to_half(val)) << A4XX_RB_BLEND_ALPHA_FLOAT__SHIFT) & A4XX_RB_BLEND_ALPHA_FLOAT__MASK;
1172+ return ((_mesa_float_to_half(val)) << A4XX_RB_BLEND_ALPHA_FLOAT__SHIFT) & A4XX_RB_BLEND_ALPHA_FLOAT__MASK;
11731173 }
11741174
11751175 #define REG_A4XX_RB_BLEND_ALPHA_F32 0x000020f7
drivers/gpu/drm/msm/adreno/a5xx.xml.h+70−25
@@ -8,21 +8,21 @@ http://github.com/freedreno/envytools/ · 7 unmodified lines
88 git clone https://github.com/freedreno/envytools.git
99
1010 The rules-ng-ng source files this header was generated from are:
11−- /home/robclark/src/envytools/rnndb/adreno.xml ( 594 bytes, from 2020-07-23 21:58:14)
12−- /home/robclark/src/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2020-07-23 21:58:14)
13−- /home/robclark/src/envytools/rnndb/adreno/a2xx.xml ( 90159 bytes, from 2020-07-23 21:58:14)
14−- /home/robclark/src/envytools/rnndb/adreno/adreno_common.xml ( 14386 bytes, from 2020-07-23 21:58:14)
15−- /home/robclark/src/envytools/rnndb/adreno/adreno_pm4.xml ( 65048 bytes, from 2020-07-23 21:58:14)
16−- /home/robclark/src/envytools/rnndb/adreno/a3xx.xml ( 84226 bytes, from 2020-07-23 21:58:14)
17−- /home/robclark/src/envytools/rnndb/adreno/a4xx.xml ( 112556 bytes, from 2020-07-23 21:58:14)
18−- /home/robclark/src/envytools/rnndb/adreno/a5xx.xml ( 149461 bytes, from 2020-07-23 21:58:14)
19−- /home/robclark/src/envytools/rnndb/adreno/a6xx.xml ( 184695 bytes, from 2020-07-23 21:58:14)
20−- /home/robclark/src/envytools/rnndb/adreno/a6xx_gmu.xml ( 11218 bytes, from 2020-07-23 21:58:14)
21−- /home/robclark/src/envytools/rnndb/adreno/ocmem.xml ( 1773 bytes, from 2020-07-23 21:58:14)
22−- /home/robclark/src/envytools/rnndb/adreno/adreno_control_regs.xml ( 4559 bytes, from 2020-07-23 21:58:14)
23−- /home/robclark/src/envytools/rnndb/adreno/adreno_pipe_regs.xml ( 2872 bytes, from 2020-07-23 21:58:14)
24−
25−Copyright (C) 2013-2020 by the following authors:
11+- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno.xml ( 594 bytes, from 2021-02-18 16:45:44)
12+- /home/robclark/src/mesa/mesa/src/freedreno/registers/freedreno_copyright.xml ( 1572 bytes, from 2021-02-18 16:45:44)
13+- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a2xx.xml ( 90810 bytes, from 2021-02-18 16:45:44)
14+- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_common.xml ( 14386 bytes, from 2021-02-18 16:45:44)
15+- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_pm4.xml ( 67699 bytes, from 2021-05-31 20:21:57)
16+- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a3xx.xml ( 84226 bytes, from 2021-02-18 16:45:44)
17+- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a4xx.xml ( 112551 bytes, from 2021-02-18 16:45:44)
18+- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a5xx.xml ( 150713 bytes, from 2021-06-10 22:34:02)
19+- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a6xx.xml ( 180049 bytes, from 2021-06-02 21:44:19)
20+- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a6xx_gmu.xml ( 11331 bytes, from 2021-05-21 19:18:08)
21+- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/ocmem.xml ( 1773 bytes, from 2021-02-18 16:45:44)
22+- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_control_regs.xml ( 6038 bytes, from 2021-05-27 20:22:36)
23+- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_pipe_regs.xml ( 2924 bytes, from 2021-05-27 20:18:13)
24+
25+Copyright (C) 2013-2021 by the following authors:
2626 - Rob Clark <robdclark@gmail.com> (robclark)
2727 - Ilia Mirkin <imirkin@alum.mit.edu> (imirkin)
2828
@@ -2021,6 +2021,7 @@ static inline uint32_t A5XX_RBBM_STATUS_CP_ME_BUSY(uint32_t val) · 1992 unmodified lines
20212021 #define A5XX_RBBM_STATUS_HI_BUSY 0x00000001
20222022
20232023 #define REG_A5XX_RBBM_STATUS3 0x00000530
2024+#define A5XX_RBBM_STATUS3_SMMU_STALLED_ON_FAULT 0x01000000
20242025
20252026 #define REG_A5XX_RBBM_INT_0_STATUS 0x000004e1
20262027
@@ -2351,6 +2352,7 @@ static inline uint32_t A5XX_VSC_RESOLVE_CNTL_Y(uint32_t val) · 324 unmodified lines
23512352 #define REG_A5XX_VFD_PERFCTR_VFD_SEL_7 0x00000e57
23522353
23532354 #define REG_A5XX_VPC_DBG_ECO_CNTL 0x00000e60
2355+#define A5XX_VPC_DBG_ECO_CNTL_ALLFLATOPTDIS 0x00000400
23542356
23552357 #define REG_A5XX_VPC_ADDR_MODE_CNTL 0x00000e61
23562358
@@ -2808,7 +2810,19 @@ static inline uint32_t A5XX_VSC_RESOLVE_CNTL_Y(uint32_t val) · 451 unmodified lines
28082810 #define REG_A5XX_GRAS_CL_CNTL 0x0000e000
28092811 #define A5XX_GRAS_CL_CNTL_ZERO_GB_SCALE_Z 0x00000040
28102812
2811−#define REG_A5XX_UNKNOWN_E001 0x0000e001
2813+#define REG_A5XX_GRAS_VS_CL_CNTL 0x0000e001
2814+#define A5XX_GRAS_VS_CL_CNTL_CLIP_MASK__MASK 0x000000ff
2815+#define A5XX_GRAS_VS_CL_CNTL_CLIP_MASK__SHIFT 0
2816+static inline uint32_t A5XX_GRAS_VS_CL_CNTL_CLIP_MASK(uint32_t val)
2817+{
2818+ return ((val) << A5XX_GRAS_VS_CL_CNTL_CLIP_MASK__SHIFT) & A5XX_GRAS_VS_CL_CNTL_CLIP_MASK__MASK;
2819+}
2820+#define A5XX_GRAS_VS_CL_CNTL_CULL_MASK__MASK 0x0000ff00
2821+#define A5XX_GRAS_VS_CL_CNTL_CULL_MASK__SHIFT 8
2822+static inline uint32_t A5XX_GRAS_VS_CL_CNTL_CULL_MASK(uint32_t val)
2823+{
2824+ return ((val) << A5XX_GRAS_VS_CL_CNTL_CULL_MASK__SHIFT) & A5XX_GRAS_VS_CL_CNTL_CULL_MASK__MASK;
2825+}
28122826
28132827 #define REG_A5XX_UNKNOWN_E004 0x0000e004
28142828
@@ -3345,7 +3359,7 @@ static inline uint32_t A5XX_RB_BLEND_RED_SINT(uint32_t val) · 530 unmodified lines
33453359 #define A5XX_RB_BLEND_RED_FLOAT__SHIFT 16
33463360 static inline uint32_t A5XX_RB_BLEND_RED_FLOAT(float val)
33473361 {
3348− return ((util_float_to_half(val)) << A5XX_RB_BLEND_RED_FLOAT__SHIFT) & A5XX_RB_BLEND_RED_FLOAT__MASK;
3362+ return ((_mesa_float_to_half(val)) << A5XX_RB_BLEND_RED_FLOAT__SHIFT) & A5XX_RB_BLEND_RED_FLOAT__MASK;
33493363 }
33503364
33513365 #define REG_A5XX_RB_BLEND_RED_F32 0x0000e1a1
@@ -3373,7 +3387,7 @@ static inline uint32_t A5XX_RB_BLEND_GREEN_SINT(uint32_t val) · 21 unmodified lines
33733387 #define A5XX_RB_BLEND_GREEN_FLOAT__SHIFT 16
33743388 static inline uint32_t A5XX_RB_BLEND_GREEN_FLOAT(float val)
33753389 {
3376− return ((util_float_to_half(val)) << A5XX_RB_BLEND_GREEN_FLOAT__SHIFT) & A5XX_RB_BLEND_GREEN_FLOAT__MASK;
3390+ return ((_mesa_float_to_half(val)) << A5XX_RB_BLEND_GREEN_FLOAT__SHIFT) & A5XX_RB_BLEND_GREEN_FLOAT__MASK;
33773391 }
33783392
33793393 #define REG_A5XX_RB_BLEND_GREEN_F32 0x0000e1a3
@@ -3401,7 +3415,7 @@ static inline uint32_t A5XX_RB_BLEND_BLUE_SINT(uint32_t val) · 21 unmodified lines
34013415 #define A5XX_RB_BLEND_BLUE_FLOAT__SHIFT 16
34023416 static inline uint32_t A5XX_RB_BLEND_BLUE_FLOAT(float val)
34033417 {
3404− return ((util_float_to_half(val)) << A5XX_RB_BLEND_BLUE_FLOAT__SHIFT) & A5XX_RB_BLEND_BLUE_FLOAT__MASK;
3418+ return ((_mesa_float_to_half(val)) << A5XX_RB_BLEND_BLUE_FLOAT__SHIFT) & A5XX_RB_BLEND_BLUE_FLOAT__MASK;
34053419 }
34063420
34073421 #define REG_A5XX_RB_BLEND_BLUE_F32 0x0000e1a5
@@ -3429,7 +3443,7 @@ static inline uint32_t A5XX_RB_BLEND_ALPHA_SINT(uint32_t val) · 21 unmodified lines
34293443 #define A5XX_RB_BLEND_ALPHA_FLOAT__SHIFT 16
34303444 static inline uint32_t A5XX_RB_BLEND_ALPHA_FLOAT(float val)
34313445 {
3432− return ((util_float_to_half(val)) << A5XX_RB_BLEND_ALPHA_FLOAT__SHIFT) & A5XX_RB_BLEND_ALPHA_FLOAT__MASK;
3446+ return ((_mesa_float_to_half(val)) << A5XX_RB_BLEND_ALPHA_FLOAT__SHIFT) & A5XX_RB_BLEND_ALPHA_FLOAT__MASK;
34333447 }
34343448
34353449 #define REG_A5XX_RB_BLEND_ALPHA_F32 0x0000e1a7
@@ -3806,7 +3820,25 @@ static inline uint32_t REG_A5XX_VPC_VAR_DISABLE(uint32_t i0) { return 0x0000e294 · 370 unmodified lines
38063820
38073821 #define REG_A5XX_VPC_GS_SIV_CNTL 0x0000e298
38083822
3809−#define REG_A5XX_UNKNOWN_E29A 0x0000e29a
3823+#define REG_A5XX_VPC_CLIP_CNTL 0x0000e29a
3824+#define A5XX_VPC_CLIP_CNTL_CLIP_MASK__MASK 0x000000ff
3825+#define A5XX_VPC_CLIP_CNTL_CLIP_MASK__SHIFT 0
3826+static inline uint32_t A5XX_VPC_CLIP_CNTL_CLIP_MASK(uint32_t val)
3827+{
3828+ return ((val) << A5XX_VPC_CLIP_CNTL_CLIP_MASK__SHIFT) & A5XX_VPC_CLIP_CNTL_CLIP_MASK__MASK;
3829+}
3830+#define A5XX_VPC_CLIP_CNTL_CLIP_DIST_03_LOC__MASK 0x0000ff00
3831+#define A5XX_VPC_CLIP_CNTL_CLIP_DIST_03_LOC__SHIFT 8
3832+static inline uint32_t A5XX_VPC_CLIP_CNTL_CLIP_DIST_03_LOC(uint32_t val)
3833+{
3834+ return ((val) << A5XX_VPC_CLIP_CNTL_CLIP_DIST_03_LOC__SHIFT) & A5XX_VPC_CLIP_CNTL_CLIP_DIST_03_LOC__MASK;
3835+}
3836+#define A5XX_VPC_CLIP_CNTL_CLIP_DIST_47_LOC__MASK 0x00ff0000
3837+#define A5XX_VPC_CLIP_CNTL_CLIP_DIST_47_LOC__SHIFT 16
3838+static inline uint32_t A5XX_VPC_CLIP_CNTL_CLIP_DIST_47_LOC(uint32_t val)
3839+{
3840+ return ((val) << A5XX_VPC_CLIP_CNTL_CLIP_DIST_47_LOC__SHIFT) & A5XX_VPC_CLIP_CNTL_CLIP_DIST_47_LOC__MASK;
3841+}
38103842
38113843 #define REG_A5XX_VPC_PACK 0x0000e29d
38123844 #define A5XX_VPC_PACK_NUMNONPOSVAR__MASK 0x000000ff
@@ -3910,7 +3942,13 @@ static inline uint32_t A5XX_PC_RASTER_CNTL_POLYMODE_BACK_PTYPE(enum adreno_pa_su · 97 unmodified lines
39103942 }
39113943 #define A5XX_PC_RASTER_CNTL_POLYMODE_ENABLE 0x00000040
39123944
3913−#define REG_A5XX_UNKNOWN_E389 0x0000e389
3945+#define REG_A5XX_PC_CLIP_CNTL 0x0000e389
3946+#define A5XX_PC_CLIP_CNTL_CLIP_MASK__MASK 0x000000ff
3947+#define A5XX_PC_CLIP_CNTL_CLIP_MASK__SHIFT 0
3948+static inline uint32_t A5XX_PC_CLIP_CNTL_CLIP_MASK(uint32_t val)
3949+{
3950+ return ((val) << A5XX_PC_CLIP_CNTL_CLIP_MASK__SHIFT) & A5XX_PC_CLIP_CNTL_CLIP_MASK__MASK;
3951+}
39143952
39153953 #define REG_A5XX_PC_RESTART_INDEX 0x0000e38c
39163954
@@ -4302,7 +4340,12 @@ static inline uint32_t A5XX_SP_FS_CTRL_REG0_BRANCHSTACK(uint32_t val) · 385 unmodified lines
43024340 #define REG_A5XX_SP_FS_OBJ_START_HI 0x0000e5c4
43034341
43044342 #define REG_A5XX_SP_BLEND_CNTL 0x0000e5c9
4305−#define A5XX_SP_BLEND_CNTL_ENABLED 0x00000001
4343+#define A5XX_SP_BLEND_CNTL_ENABLE_BLEND__MASK 0x000000ff
4344+#define A5XX_SP_BLEND_CNTL_ENABLE_BLEND__SHIFT 0
4345+static inline uint32_t A5XX_SP_BLEND_CNTL_ENABLE_BLEND(uint32_t val)
4346+{
4347+ return ((val) << A5XX_SP_BLEND_CNTL_ENABLE_BLEND__SHIFT) & A5XX_SP_BLEND_CNTL_ENABLE_BLEND__MASK;
4348+}
43064349 #define A5XX_SP_BLEND_CNTL_UNK8 0x00000100
43074350 #define A5XX_SP_BLEND_CNTL_ALPHA_TO_COVERAGE 0x00000400
43084351
@@ -5192,8 +5235,8 @@ static inline uint32_t A5XX_TEX_SAMP_1_MIN_LOD(float val) · 883 unmodified lines
51925235 }
51935236
51945237 #define REG_A5XX_TEX_SAMP_2 0x00000002
5195−#define A5XX_TEX_SAMP_2_BCOLOR_OFFSET__MASK 0xfffffff0
5196−#define A5XX_TEX_SAMP_2_BCOLOR_OFFSET__SHIFT 4
5238+#define A5XX_TEX_SAMP_2_BCOLOR_OFFSET__MASK 0xffffff80
5239+#define A5XX_TEX_SAMP_2_BCOLOR_OFFSET__SHIFT 7
51975240 static inline uint32_t A5XX_TEX_SAMP_2_BCOLOR_OFFSET(uint32_t val)
51985241 {
51995242 return ((val) << A5XX_TEX_SAMP_2_BCOLOR_OFFSET__SHIFT) & A5XX_TEX_SAMP_2_BCOLOR_OFFSET__MASK;
@@ -5273,6 +5316,7 @@ static inline uint32_t A5XX_TEX_CONST_1_HEIGHT(uint32_t val) · 73 unmodified lines
52735316 }
52745317
52755318 #define REG_A5XX_TEX_CONST_2 0x00000002
5319+#define A5XX_TEX_CONST_2_UNK4 0x00000010
52765320 #define A5XX_TEX_CONST_2_PITCHALIGN__MASK 0x0000000f
52775321 #define A5XX_TEX_CONST_2_PITCHALIGN__SHIFT 0
52785322 static inline uint32_t A5XX_TEX_CONST_2_PITCHALIGN(uint32_t val)
@@ -5291,6 +5335,7 @@ static inline uint32_t A5XX_TEX_CONST_2_TYPE(enum a5xx_tex_type val) · 12 unmodified lines
52915335 {
52925336 return ((val) << A5XX_TEX_CONST_2_TYPE__SHIFT) & A5XX_TEX_CONST_2_TYPE__MASK;
52935337 }
5338+#define A5XX_TEX_CONST_2_UNK31 0x80000000
52945339
52955340 #define REG_A5XX_TEX_CONST_3 0x00000003
52965341 #define A5XX_TEX_CONST_3_ARRAY_PITCH__MASK 0x00003fff
drivers/gpu/drm/msm/adreno/a5xx_gpu.c+22−7
@@ -902,7 +902,7 @@ static int a5xx_hw_init(struct msm_gpu *gpu) · 901 unmodified lines
902902 if (!a5xx_gpu->shadow_bo) {
903903 a5xx_gpu->shadow = msm_gem_kernel_new(gpu->dev,
904904 sizeof(u32) * gpu->nr_rings,
905− MSM_BO_UNCACHED | MSM_BO_MAP_PRIV,
905+ MSM_BO_WC | MSM_BO_MAP_PRIV,
906906 gpu->aspace, &a5xx_gpu->shadow_bo,
907907 &a5xx_gpu->shadow_iova);
908908
@@ -1075,7 +1075,7 @@ bool a5xx_idle(struct msm_gpu *gpu, struct msm_ringbuffer *ring) · 166 unmodified lines
10751075 return true;
10761076 }
10771077
1078−static int a5xx_fault_handler(void *arg, unsigned long iova, int flags)
1078+static int a5xx_fault_handler(void *arg, unsigned long iova, int flags, void *data)
10791079 {
10801080 struct msm_gpu *gpu = arg;
10811081 pr_warn_ratelimited("*** gpu fault: iova=%08lx, flags=%d (%u,%u,%u,%u)\n",
@@ -1085,7 +1085,7 @@ static int a5xx_fault_handler(void *arg, unsigned long iova, int flags) · 3 unmodified lines
10851085 gpu_read(gpu, REG_A5XX_CP_SCRATCH_REG(6)),
10861086 gpu_read(gpu, REG_A5XX_CP_SCRATCH_REG(7)));
10871087
1088− return -EFAULT;
1088+ return 0;
10891089 }
10901090
10911091 static void a5xx_cp_err_irq(struct msm_gpu *gpu)
@@ -1200,6 +1200,15 @@ static void a5xx_fault_detect_irq(struct msm_gpu *gpu) · 108 unmodified lines
12001200 struct drm_device *dev = gpu->dev;
12011201 struct msm_ringbuffer *ring = gpu->funcs->active_ring(gpu);
12021202
1203+ /*
1204+ * If stalled on SMMU fault, we could trip the GPU's hang detection,
1205+ * but the fault handler will trigger the devcore dump, and we want
1206+ * to otherwise resume normally rather than killing the submit, so
1207+ * just bail.
1208+ */
1209+ if (gpu_read(gpu, REG_A5XX_RBBM_STATUS3) & BIT(24))
1210+ return;
1211+
12031212 DRM_DEV_ERROR(dev->dev, "gpu fault ring %d fence %x status %8.8X rb %4.4x/%4.4x ib1 %16.16llX/%4.4x ib2 %16.16llX/%4.4x\n",
12041213 ring ? ring->id : -1, ring ? ring->seqno : 0,
12051214 gpu_read(gpu, REG_A5XX_RBBM_STATUS),
@@ -1407,7 +1416,7 @@ static int a5xx_crashdumper_init(struct msm_gpu *gpu, · 201 unmodified lines
14071416 struct a5xx_crashdumper *dumper)
14081417 {
14091418 dumper->ptr = msm_gem_kernel_new_locked(gpu->dev,
1410− SZ_1M, MSM_BO_UNCACHED, gpu->aspace,
1419+ SZ_1M, MSM_BO_WC, gpu->aspace,
14111420 &dumper->bo, &dumper->iova);
14121421
14131422 if (!IS_ERR(dumper->ptr))
@@ -1523,6 +1532,7 @@ static struct msm_gpu_state *a5xx_gpu_state_get(struct msm_gpu *gpu) · 109 unmodified lines
15231532 {
15241533 struct a5xx_gpu_state *a5xx_state = kzalloc(sizeof(*a5xx_state),
15251534 GFP_KERNEL);
1535+ bool stalled = !!(gpu_read(gpu, REG_A5XX_RBBM_STATUS3) & BIT(24));
15261536
15271537 if (!a5xx_state)
15281538 return ERR_PTR(-ENOMEM);
@@ -1535,8 +1545,13 @@ static struct msm_gpu_state *a5xx_gpu_state_get(struct msm_gpu *gpu) · 6 unmodified lines
15351545
15361546 a5xx_state->base.rbbm_status = gpu_read(gpu, REG_A5XX_RBBM_STATUS);
15371547
1538− /* Get the HLSQ regs with the help of the crashdumper */
1539− a5xx_gpu_state_get_hlsq_regs(gpu, a5xx_state);
1548+ /*
1549+ * Get the HLSQ regs with the help of the crashdumper, but only if
1550+ * we are not stalled in an iommu fault (in which case the crashdumper
1551+ * would not have access to memory)
1552+ */
1553+ if (!stalled)
1554+ a5xx_gpu_state_get_hlsq_regs(gpu, a5xx_state);
15401555
15411556 a5xx_set_hwcg(gpu, true);
15421557
@@ -1705,7 +1720,7 @@ static void check_speed_bin(struct device *dev) · 162 unmodified lines
17051720 nvmem_cell_put(cell);
17061721 }
17071722
1708− dev_pm_opp_set_supported_hw(dev, &val, 1);
1723+ devm_pm_opp_set_supported_hw(dev, &val, 1);
17091724 }
17101725
17111726 struct msm_gpu *a5xx_gpu_init(struct drm_device *dev)
drivers/gpu/drm/msm/adreno/a5xx_power.c+1−1
@@ -363,7 +363,7 @@ void a5xx_gpmu_ucode_init(struct msm_gpu *gpu) · 362 unmodified lines
363363 bosize = (cmds_size + (cmds_size / TYPE4_MAX_PAYLOAD) + 1) << 2;
364364
365365 ptr = msm_gem_kernel_new_locked(drm, bosize,
366− MSM_BO_UNCACHED | MSM_BO_GPU_READONLY, gpu->aspace,
366+ MSM_BO_WC | MSM_BO_GPU_READONLY, gpu->aspace,
367367 &a5xx_gpu->gpmu_bo, &a5xx_gpu->gpmu_iova);
368368 if (IS_ERR(ptr))
369369 return;
drivers/gpu/drm/msm/adreno/a5xx_preempt.c+2−2
@@ -230,7 +230,7 @@ static int preempt_init_ring(struct a5xx_gpu *a5xx_gpu, · 229 unmodified lines
230230
231231 ptr = msm_gem_kernel_new(gpu->dev,
232232 A5XX_PREEMPT_RECORD_SIZE + A5XX_PREEMPT_COUNTER_SIZE,
233− MSM_BO_UNCACHED | MSM_BO_MAP_PRIV, gpu->aspace, &bo, &iova);
233+ MSM_BO_WC | MSM_BO_MAP_PRIV, gpu->aspace, &bo, &iova);
234234
235235 if (IS_ERR(ptr))
236236 return PTR_ERR(ptr);
@@ -238,7 +238,7 @@ static int preempt_init_ring(struct a5xx_gpu *a5xx_gpu, · 1 unmodified line
238238 /* The buffer to store counters needs to be unprivileged */
239239 counters = msm_gem_kernel_new(gpu->dev,
240240 A5XX_PREEMPT_COUNTER_SIZE,
241− MSM_BO_UNCACHED, gpu->aspace, &counters_bo, &counters_iova);
241+ MSM_BO_WC, gpu->aspace, &counters_bo, &counters_iova);
242242 if (IS_ERR(counters)) {
243243 msm_gem_kernel_put(bo, gpu->aspace, true);
244244 return PTR_ERR(counters);
drivers/gpu/drm/msm/adreno/a6xx.xml.h+1059−1142
@@ -8,21 +8,21 @@ http://github.com/freedreno/envytools/ · 7 unmodified lines
88 git clone https://github.com/freedreno/envytools.git
99
1010 The rules-ng-ng source files this header was generated from are:
11−- /home/robclark/src/envytools/rnndb/adreno.xml ( 594 bytes, from 2020-07-23 21:58:14)
12−- /home/robclark/src/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2020-07-23 21:58:14)
13−- /home/robclark/src/envytools/rnndb/adreno/a2xx.xml ( 90159 bytes, from 2020-07-23 21:58:14)
14−- /home/robclark/src/envytools/rnndb/adreno/adreno_common.xml ( 14386 bytes, from 2020-07-23 21:58:14)
15−- /home/robclark/src/envytools/rnndb/adreno/adreno_pm4.xml ( 65048 bytes, from 2020-07-23 21:58:14)
16−- /home/robclark/src/envytools/rnndb/adreno/a3xx.xml ( 84226 bytes, from 2020-07-23 21:58:14)
17−- /home/robclark/src/envytools/rnndb/adreno/a4xx.xml ( 112556 bytes, from 2020-07-23 21:58:14)
18−- /home/robclark/src/envytools/rnndb/adreno/a5xx.xml ( 149461 bytes, from 2020-07-23 21:58:14)
19−- /home/robclark/src/envytools/rnndb/adreno/a6xx.xml ( 184695 bytes, from 2020-07-23 21:58:14)
20−- /home/robclark/src/envytools/rnndb/adreno/a6xx_gmu.xml ( 11218 bytes, from 2020-07-23 21:58:14)
21−- /home/robclark/src/envytools/rnndb/adreno/ocmem.xml ( 1773 bytes, from 2020-07-23 21:58:14)
22−- /home/robclark/src/envytools/rnndb/adreno/adreno_control_regs.xml ( 4559 bytes, from 2020-07-23 21:58:14)
23−- /home/robclark/src/envytools/rnndb/adreno/adreno_pipe_regs.xml ( 2872 bytes, from 2020-07-23 21:58:14)
24−
25−Copyright (C) 2013-2020 by the following authors:
11+- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno.xml ( 594 bytes, from 2021-02-18 16:45:44)
12+- /home/robclark/src/mesa/mesa/src/freedreno/registers/freedreno_copyright.xml ( 1572 bytes, from 2021-02-18 16:45:44)
13+- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a2xx.xml ( 90810 bytes, from 2021-02-18 16:45:44)
14+- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_common.xml ( 14386 bytes, from 2021-02-18 16:45:44)
15+- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_pm4.xml ( 67699 bytes, from 2021-05-31 20:21:57)
16+- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a3xx.xml ( 84226 bytes, from 2021-02-18 16:45:44)
17+- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a4xx.xml ( 112551 bytes, from 2021-02-18 16:45:44)
18+- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a5xx.xml ( 150713 bytes, from 2021-06-10 22:34:02)
19+- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a6xx.xml ( 180049 bytes, from 2021-06-02 21:44:19)
20+- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a6xx_gmu.xml ( 11331 bytes, from 2021-05-21 19:18:08)
21+- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/ocmem.xml ( 1773 bytes, from 2021-02-18 16:45:44)
22+- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_control_regs.xml ( 6038 bytes, from 2021-05-27 20:22:36)
23+- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_pipe_regs.xml ( 2924 bytes, from 2021-05-27 20:18:13)
24+
25+Copyright (C) 2013-2021 by the following authors:
2626 - Rob Clark <robdclark@gmail.com> (robclark)
2727 - Ilia Mirkin <imirkin@alum.mit.edu> (imirkin)
2828
@@ -168,7 +168,7 @@ enum a6xx_format { · 139 unmodified lines
168168 FMT6_ASTC_10x10 = 204,
169169 FMT6_ASTC_12x10 = 205,
170170 FMT6_ASTC_12x12 = 206,
171− FMT6_S8Z24_UINT = 234,
171+ FMT6_Z24_UINT_S8_UINT = 234,
172172 FMT6_NONE = 255,
173173 };
174174
@@ -907,6 +907,11 @@ enum a6xx_tess_output { · 732 unmodified lines
907907 TESS_CCW_TRIS = 3,
908908 };
909909
910+enum a6xx_threadsize {
911+ THREAD64 = 0,
912+ THREAD128 = 1,
913+};
914+
910915 enum a6xx_tex_filter {
911916 A6XX_TEX_NEAREST = 0,
912917 A6XX_TEX_LINEAR = 1,
@@ -1007,9 +1012,7 @@ enum a6xx_tex_type { · 94 unmodified lines
10071012
10081013 #define REG_A6XX_CP_PROTECT_STATUS 0x00000824
10091014
1010−#define REG_A6XX_CP_SQE_INSTR_BASE_LO 0x00000830
1011−
1012−#define REG_A6XX_CP_SQE_INSTR_BASE_HI 0x00000831
1015+#define REG_A6XX_CP_SQE_INSTR_BASE 0x00000830
10131016
10141017 #define REG_A6XX_CP_MISC_CNTL 0x00000840
10151018
@@ -1104,33 +1107,7 @@ static inline uint32_t A6XX_CP_PROTECT_REG_MASK_LEN(uint32_t val) · 88 unmodified lines
11041107
11051108 #define REG_A6XX_CP_CONTEXT_SWITCH_NON_PRIV_RESTORE_ADDR_HI 0x000008a8
11061109
1107−#define REG_A6XX_CP_PERFCTR_CP_SEL_0 0x000008d0
1108−
1109−#define REG_A6XX_CP_PERFCTR_CP_SEL_1 0x000008d1
1110−
1111−#define REG_A6XX_CP_PERFCTR_CP_SEL_2 0x000008d2
1112−
1113−#define REG_A6XX_CP_PERFCTR_CP_SEL_3 0x000008d3
1114−
1115−#define REG_A6XX_CP_PERFCTR_CP_SEL_4 0x000008d4
1116−
1117−#define REG_A6XX_CP_PERFCTR_CP_SEL_5 0x000008d5
1118−
1119−#define REG_A6XX_CP_PERFCTR_CP_SEL_6 0x000008d6
1120−
1121−#define REG_A6XX_CP_PERFCTR_CP_SEL_7 0x000008d7
1122−
1123−#define REG_A6XX_CP_PERFCTR_CP_SEL_8 0x000008d8
1124−
1125−#define REG_A6XX_CP_PERFCTR_CP_SEL_9 0x000008d9
1126−
1127−#define REG_A6XX_CP_PERFCTR_CP_SEL_10 0x000008da
1128−
1129−#define REG_A6XX_CP_PERFCTR_CP_SEL_11 0x000008db
1130−
1131−#define REG_A6XX_CP_PERFCTR_CP_SEL_12 0x000008dc
1132−
1133−#define REG_A6XX_CP_PERFCTR_CP_SEL_13 0x000008dd
1110+static inline uint32_t REG_A6XX_CP_PERFCTR_CP_SEL(uint32_t i0) { return 0x000008d0 + 0x1*i0; }
11341111
11351112 #define REG_A6XX_CP_CRASH_SCRIPT_BASE_LO 0x00000900
11361113
@@ -1176,15 +1153,21 @@ static inline uint32_t A6XX_CP_PROTECT_REG_MASK_LEN(uint32_t val) · 39 unmodified lines
11761153
11771154 #define REG_A6XX_CP_SDS_BASE_HI 0x0000092f
11781155
1179−#define REG_A6XX_CP_SDS_REM_SIZE 0x0000092e
1156+#define REG_A6XX_CP_SDS_REM_SIZE 0x00000930
1157+
1158+#define REG_A6XX_CP_MRB_BASE 0x00000931
1159+
1160+#define REG_A6XX_CP_MRB_BASE_HI 0x00000932
11801161
1181−#define REG_A6XX_CP_BIN_SIZE_ADDRESS 0x00000931
1162+#define REG_A6XX_CP_MRB_REM_SIZE 0x00000933
11821163
1183−#define REG_A6XX_CP_BIN_SIZE_ADDRESS_HI 0x00000932
1164+#define REG_A6XX_CP_VSD_BASE 0x00000934
11841165
1185−#define REG_A6XX_CP_BIN_DATA_ADDR 0x00000934
1166+#define REG_A6XX_CP_VSD_BASE_HI 0x00000935
11861167
1187−#define REG_A6XX_CP_BIN_DATA_ADDR_HI 0x00000935
1168+#define REG_A6XX_CP_MRB_DWORDS 0x00000946
1169+
1170+#define REG_A6XX_CP_VSD_DWORDS 0x00000947
11881171
11891172 #define REG_A6XX_CP_CSQ_IB1_STAT 0x00000949
11901173 #define A6XX_CP_CSQ_IB1_STAT_REM__MASK 0xffff0000
@@ -1202,6 +1185,14 @@ static inline uint32_t A6XX_CP_CSQ_IB2_STAT_REM(uint32_t val) · 11 unmodified lines
12021185 return ((val) << A6XX_CP_CSQ_IB2_STAT_REM__SHIFT) & A6XX_CP_CSQ_IB2_STAT_REM__MASK;
12031186 }
12041187
1188+#define REG_A6XX_CP_MRQ_MRB_STAT 0x0000094c
1189+#define A6XX_CP_MRQ_MRB_STAT_REM__MASK 0xffff0000
1190+#define A6XX_CP_MRQ_MRB_STAT_REM__SHIFT 16
1191+static inline uint32_t A6XX_CP_MRQ_MRB_STAT_REM(uint32_t val)
1192+{
1193+ return ((val) << A6XX_CP_MRQ_MRB_STAT_REM__SHIFT) & A6XX_CP_MRQ_MRB_STAT_REM__MASK;
1194+}
1195+
12051196 #define REG_A6XX_CP_ALWAYS_ON_COUNTER_LO 0x00000980
12061197
12071198 #define REG_A6XX_CP_ALWAYS_ON_COUNTER_HI 0x00000981
@@ -1212,6 +1203,10 @@ static inline uint32_t A6XX_CP_CSQ_IB2_STAT_REM(uint32_t val) · 4 unmodified lines
12121203
12131204 #define REG_A6XX_CP_APERTURE_CNTL_CD 0x00000a03
12141205
1206+#define REG_A6XX_CP_LPAC_PROG_FIFO_SIZE 0x00000b34
1207+
1208+#define REG_A6XX_CP_LPAC_SQE_INSTR_BASE 0x00000b82
1209+
12151210 #define REG_A6XX_VSC_ADDR_MODE_CNTL 0x00000c01
12161211
12171212 #define REG_A6XX_RBBM_INT_0_STATUS 0x00000201
@@ -1247,505 +1242,37 @@ static inline uint32_t A6XX_CP_CSQ_IB2_STAT_REM(uint32_t val) · 29 unmodified lines
12471242
12481243 #define REG_A6XX_RBBM_VBIF_GX_RESET_STATUS 0x00000215
12491244
1250−#define REG_A6XX_RBBM_PERFCTR_CP_0_LO 0x00000400
1251−
1252−#define REG_A6XX_RBBM_PERFCTR_CP_0_HI 0x00000401
1253−
1254−#define REG_A6XX_RBBM_PERFCTR_CP_1_LO 0x00000402
1255−
1256−#define REG_A6XX_RBBM_PERFCTR_CP_1_HI 0x00000403
1257−
1258−#define REG_A6XX_RBBM_PERFCTR_CP_2_LO 0x00000404
1259−
1260−#define REG_A6XX_RBBM_PERFCTR_CP_2_HI 0x00000405
1261−
1262−#define REG_A6XX_RBBM_PERFCTR_CP_3_LO 0x00000406
1263−
1264−#define REG_A6XX_RBBM_PERFCTR_CP_3_HI 0x00000407
1265−
1266−#define REG_A6XX_RBBM_PERFCTR_CP_4_LO 0x00000408
1267−
1268−#define REG_A6XX_RBBM_PERFCTR_CP_4_HI 0x00000409
1269−
1270−#define REG_A6XX_RBBM_PERFCTR_CP_5_LO 0x0000040a
1271−
1272−#define REG_A6XX_RBBM_PERFCTR_CP_5_HI 0x0000040b
1273−
1274−#define REG_A6XX_RBBM_PERFCTR_CP_6_LO 0x0000040c
1275−
1276−#define REG_A6XX_RBBM_PERFCTR_CP_6_HI 0x0000040d
1277−
1278−#define REG_A6XX_RBBM_PERFCTR_CP_7_LO 0x0000040e
1279−
1280−#define REG_A6XX_RBBM_PERFCTR_CP_7_HI 0x0000040f
1281−
1282−#define REG_A6XX_RBBM_PERFCTR_CP_8_LO 0x00000410
1283−
1284−#define REG_A6XX_RBBM_PERFCTR_CP_8_HI 0x00000411
1285−
1286−#define REG_A6XX_RBBM_PERFCTR_CP_9_LO 0x00000412
1287−
1288−#define REG_A6XX_RBBM_PERFCTR_CP_9_HI 0x00000413
1289−
1290−#define REG_A6XX_RBBM_PERFCTR_CP_10_LO 0x00000414
1291−
1292−#define REG_A6XX_RBBM_PERFCTR_CP_10_HI 0x00000415
1293−
1294−#define REG_A6XX_RBBM_PERFCTR_CP_11_LO 0x00000416
1295−
1296−#define REG_A6XX_RBBM_PERFCTR_CP_11_HI 0x00000417
1297−
1298−#define REG_A6XX_RBBM_PERFCTR_CP_12_LO 0x00000418
1299−
1300−#define REG_A6XX_RBBM_PERFCTR_CP_12_HI 0x00000419
1301−
1302−#define REG_A6XX_RBBM_PERFCTR_CP_13_LO 0x0000041a
1303−
1304−#define REG_A6XX_RBBM_PERFCTR_CP_13_HI 0x0000041b
1305−
1306−#define REG_A6XX_RBBM_PERFCTR_RBBM_0_LO 0x0000041c
1307−
1308−#define REG_A6XX_RBBM_PERFCTR_RBBM_0_HI 0x0000041d
1309−
1310−#define REG_A6XX_RBBM_PERFCTR_RBBM_1_LO 0x0000041e
1311−
1312−#define REG_A6XX_RBBM_PERFCTR_RBBM_1_HI 0x0000041f
1313−
1314−#define REG_A6XX_RBBM_PERFCTR_RBBM_2_LO 0x00000420
1315−
1316−#define REG_A6XX_RBBM_PERFCTR_RBBM_2_HI 0x00000421
1317−
1318−#define REG_A6XX_RBBM_PERFCTR_RBBM_3_LO 0x00000422
1319−
1320−#define REG_A6XX_RBBM_PERFCTR_RBBM_3_HI 0x00000423
1321−
1322−#define REG_A6XX_RBBM_PERFCTR_PC_0_LO 0x00000424
1323−
1324−#define REG_A6XX_RBBM_PERFCTR_PC_0_HI 0x00000425
1325−
1326−#define REG_A6XX_RBBM_PERFCTR_PC_1_LO 0x00000426
1327−
1328−#define REG_A6XX_RBBM_PERFCTR_PC_1_HI 0x00000427
1329−
1330−#define REG_A6XX_RBBM_PERFCTR_PC_2_LO 0x00000428
1331−
1332−#define REG_A6XX_RBBM_PERFCTR_PC_2_HI 0x00000429
1333−
1334−#define REG_A6XX_RBBM_PERFCTR_PC_3_LO 0x0000042a
1335−
1336−#define REG_A6XX_RBBM_PERFCTR_PC_3_HI 0x0000042b
1337−
1338−#define REG_A6XX_RBBM_PERFCTR_PC_4_LO 0x0000042c
1339−
1340−#define REG_A6XX_RBBM_PERFCTR_PC_4_HI 0x0000042d
1341−
1342−#define REG_A6XX_RBBM_PERFCTR_PC_5_LO 0x0000042e
1343−
1344−#define REG_A6XX_RBBM_PERFCTR_PC_5_HI 0x0000042f
1345−
1346−#define REG_A6XX_RBBM_PERFCTR_PC_6_LO 0x00000430
1347−
1348−#define REG_A6XX_RBBM_PERFCTR_PC_6_HI 0x00000431
1349−
1350−#define REG_A6XX_RBBM_PERFCTR_PC_7_LO 0x00000432
1351−
1352−#define REG_A6XX_RBBM_PERFCTR_PC_7_HI 0x00000433
1353−
1354−#define REG_A6XX_RBBM_PERFCTR_VFD_0_LO 0x00000434
1355−
1356−#define REG_A6XX_RBBM_PERFCTR_VFD_0_HI 0x00000435
1357−
1358−#define REG_A6XX_RBBM_PERFCTR_VFD_1_LO 0x00000436
1359−
1360−#define REG_A6XX_RBBM_PERFCTR_VFD_1_HI 0x00000437
1361−
1362−#define REG_A6XX_RBBM_PERFCTR_VFD_2_LO 0x00000438
1363−
1364−#define REG_A6XX_RBBM_PERFCTR_VFD_2_HI 0x00000439
1365−
1366−#define REG_A6XX_RBBM_PERFCTR_VFD_3_LO 0x0000043a
1367−
1368−#define REG_A6XX_RBBM_PERFCTR_VFD_3_HI 0x0000043b
1369−
1370−#define REG_A6XX_RBBM_PERFCTR_VFD_4_LO 0x0000043c
1371−
1372−#define REG_A6XX_RBBM_PERFCTR_VFD_4_HI 0x0000043d
1373−
1374−#define REG_A6XX_RBBM_PERFCTR_VFD_5_LO 0x0000043e
1375−
1376−#define REG_A6XX_RBBM_PERFCTR_VFD_5_HI 0x0000043f
1377−
1378−#define REG_A6XX_RBBM_PERFCTR_VFD_6_LO 0x00000440
1379−
1380−#define REG_A6XX_RBBM_PERFCTR_VFD_6_HI 0x00000441
1381−
1382−#define REG_A6XX_RBBM_PERFCTR_VFD_7_LO 0x00000442
1383−
1384−#define REG_A6XX_RBBM_PERFCTR_VFD_7_HI 0x00000443
1385−
1386−#define REG_A6XX_RBBM_PERFCTR_HLSQ_0_LO 0x00000444
1387−
1388−#define REG_A6XX_RBBM_PERFCTR_HLSQ_0_HI 0x00000445
1389−
1390−#define REG_A6XX_RBBM_PERFCTR_HLSQ_1_LO 0x00000446
1391−
1392−#define REG_A6XX_RBBM_PERFCTR_HLSQ_1_HI 0x00000447
1393−
1394−#define REG_A6XX_RBBM_PERFCTR_HLSQ_2_LO 0x00000448
1395−
1396−#define REG_A6XX_RBBM_PERFCTR_HLSQ_2_HI 0x00000449
1397−
1398−#define REG_A6XX_RBBM_PERFCTR_HLSQ_3_LO 0x0000044a
1399−
1400−#define REG_A6XX_RBBM_PERFCTR_HLSQ_3_HI 0x0000044b
1401−
1402−#define REG_A6XX_RBBM_PERFCTR_HLSQ_4_LO 0x0000044c
1403−
1404−#define REG_A6XX_RBBM_PERFCTR_HLSQ_4_HI 0x0000044d
1405−
1406−#define REG_A6XX_RBBM_PERFCTR_HLSQ_5_LO 0x0000044e
1407−
1408−#define REG_A6XX_RBBM_PERFCTR_HLSQ_5_HI 0x0000044f
1409−
1410−#define REG_A6XX_RBBM_PERFCTR_VPC_0_LO 0x00000450
1411−
1412−#define REG_A6XX_RBBM_PERFCTR_VPC_0_HI 0x00000451
1413−
1414−#define REG_A6XX_RBBM_PERFCTR_VPC_1_LO 0x00000452
1415−
1416−#define REG_A6XX_RBBM_PERFCTR_VPC_1_HI 0x00000453
1417−
1418−#define REG_A6XX_RBBM_PERFCTR_VPC_2_LO 0x00000454
1419−
1420−#define REG_A6XX_RBBM_PERFCTR_VPC_2_HI 0x00000455
1421−
1422−#define REG_A6XX_RBBM_PERFCTR_VPC_3_LO 0x00000456
1423−
1424−#define REG_A6XX_RBBM_PERFCTR_VPC_3_HI 0x00000457
1425−
1426−#define REG_A6XX_RBBM_PERFCTR_VPC_4_LO 0x00000458
1427−
1428−#define REG_A6XX_RBBM_PERFCTR_VPC_4_HI 0x00000459
1429−
1430−#define REG_A6XX_RBBM_PERFCTR_VPC_5_LO 0x0000045a
1431−
1432−#define REG_A6XX_RBBM_PERFCTR_VPC_5_HI 0x0000045b
1433−
1434−#define REG_A6XX_RBBM_PERFCTR_CCU_0_LO 0x0000045c
1435−
1436−#define REG_A6XX_RBBM_PERFCTR_CCU_0_HI 0x0000045d
1437−
1438−#define REG_A6XX_RBBM_PERFCTR_CCU_1_LO 0x0000045e
1439−
1440−#define REG_A6XX_RBBM_PERFCTR_CCU_1_HI 0x0000045f
1441−
1442−#define REG_A6XX_RBBM_PERFCTR_CCU_2_LO 0x00000460
1443−
1444−#define REG_A6XX_RBBM_PERFCTR_CCU_2_HI 0x00000461
1445−
1446−#define REG_A6XX_RBBM_PERFCTR_CCU_3_LO 0x00000462
1447−
1448−#define REG_A6XX_RBBM_PERFCTR_CCU_3_HI 0x00000463
1449−
1450−#define REG_A6XX_RBBM_PERFCTR_CCU_4_LO 0x00000464
1451−
1452−#define REG_A6XX_RBBM_PERFCTR_CCU_4_HI 0x00000465
1453−
1454−#define REG_A6XX_RBBM_PERFCTR_TSE_0_LO 0x00000466
1455−
1456−#define REG_A6XX_RBBM_PERFCTR_TSE_0_HI 0x00000467
1457−
1458−#define REG_A6XX_RBBM_PERFCTR_TSE_1_LO 0x00000468
1459−
1460−#define REG_A6XX_RBBM_PERFCTR_TSE_1_HI 0x00000469
1461−
1462−#define REG_A6XX_RBBM_PERFCTR_TSE_2_LO 0x0000046a
1463−
1464−#define REG_A6XX_RBBM_PERFCTR_TSE_2_HI 0x0000046b
1465−
1466−#define REG_A6XX_RBBM_PERFCTR_TSE_3_LO 0x0000046c
1467−
1468−#define REG_A6XX_RBBM_PERFCTR_TSE_3_HI 0x0000046d
1469−
1470−#define REG_A6XX_RBBM_PERFCTR_RAS_0_LO 0x0000046e
1471−
1472−#define REG_A6XX_RBBM_PERFCTR_RAS_0_HI 0x0000046f
1473−
1474−#define REG_A6XX_RBBM_PERFCTR_RAS_1_LO 0x00000470
1475−
1476−#define REG_A6XX_RBBM_PERFCTR_RAS_1_HI 0x00000471
1477−
1478−#define REG_A6XX_RBBM_PERFCTR_RAS_2_LO 0x00000472
1479−
1480−#define REG_A6XX_RBBM_PERFCTR_RAS_2_HI 0x00000473
1481−
1482−#define REG_A6XX_RBBM_PERFCTR_RAS_3_LO 0x00000474
1483−
1484−#define REG_A6XX_RBBM_PERFCTR_RAS_3_HI 0x00000475
1485−
1486−#define REG_A6XX_RBBM_PERFCTR_UCHE_0_LO 0x00000476
1487−
1488−#define REG_A6XX_RBBM_PERFCTR_UCHE_0_HI 0x00000477
1489−
1490−#define REG_A6XX_RBBM_PERFCTR_UCHE_1_LO 0x00000478
1491−
1492−#define REG_A6XX_RBBM_PERFCTR_UCHE_1_HI 0x00000479
1493−
1494−#define REG_A6XX_RBBM_PERFCTR_UCHE_2_LO 0x0000047a
1495−
1496−#define REG_A6XX_RBBM_PERFCTR_UCHE_2_HI 0x0000047b
1497−
1498−#define REG_A6XX_RBBM_PERFCTR_UCHE_3_LO 0x0000047c
1499−
1500−#define REG_A6XX_RBBM_PERFCTR_UCHE_3_HI 0x0000047d
1501−
1502−#define REG_A6XX_RBBM_PERFCTR_UCHE_4_LO 0x0000047e
1503−
1504−#define REG_A6XX_RBBM_PERFCTR_UCHE_4_HI 0x0000047f
1505−
1506−#define REG_A6XX_RBBM_PERFCTR_UCHE_5_LO 0x00000480
1507−
1508−#define REG_A6XX_RBBM_PERFCTR_UCHE_5_HI 0x00000481
1509−
1510−#define REG_A6XX_RBBM_PERFCTR_UCHE_6_LO 0x00000482
1511−
1512−#define REG_A6XX_RBBM_PERFCTR_UCHE_6_HI 0x00000483
1513−
1514−#define REG_A6XX_RBBM_PERFCTR_UCHE_7_LO 0x00000484
1515−
1516−#define REG_A6XX_RBBM_PERFCTR_UCHE_7_HI 0x00000485
1517−
1518−#define REG_A6XX_RBBM_PERFCTR_UCHE_8_LO 0x00000486
1519−
1520−#define REG_A6XX_RBBM_PERFCTR_UCHE_8_HI 0x00000487
1521−
1522−#define REG_A6XX_RBBM_PERFCTR_UCHE_9_LO 0x00000488
1523−
1524−#define REG_A6XX_RBBM_PERFCTR_UCHE_9_HI 0x00000489
1525−
1526−#define REG_A6XX_RBBM_PERFCTR_UCHE_10_LO 0x0000048a
1527−
1528−#define REG_A6XX_RBBM_PERFCTR_UCHE_10_HI 0x0000048b
1529−
1530−#define REG_A6XX_RBBM_PERFCTR_UCHE_11_LO 0x0000048c
1531−
1532−#define REG_A6XX_RBBM_PERFCTR_UCHE_11_HI 0x0000048d
1533−
1534−#define REG_A6XX_RBBM_PERFCTR_TP_0_LO 0x0000048e
1535−
1536−#define REG_A6XX_RBBM_PERFCTR_TP_0_HI 0x0000048f
1537−
1538−#define REG_A6XX_RBBM_PERFCTR_TP_1_LO 0x00000490
1539−
1540−#define REG_A6XX_RBBM_PERFCTR_TP_1_HI 0x00000491
1541−
1542−#define REG_A6XX_RBBM_PERFCTR_TP_2_LO 0x00000492
1543−
1544−#define REG_A6XX_RBBM_PERFCTR_TP_2_HI 0x00000493
1545−
1546−#define REG_A6XX_RBBM_PERFCTR_TP_3_LO 0x00000494
1547−
1548−#define REG_A6XX_RBBM_PERFCTR_TP_3_HI 0x00000495
1549−
1550−#define REG_A6XX_RBBM_PERFCTR_TP_4_LO 0x00000496
1551−
1552−#define REG_A6XX_RBBM_PERFCTR_TP_4_HI 0x00000497
1553−
1554−#define REG_A6XX_RBBM_PERFCTR_TP_5_LO 0x00000498
1555−
1556−#define REG_A6XX_RBBM_PERFCTR_TP_5_HI 0x00000499
1557−
1558−#define REG_A6XX_RBBM_PERFCTR_TP_6_LO 0x0000049a
1559−
1560−#define REG_A6XX_RBBM_PERFCTR_TP_6_HI 0x0000049b
1561−
1562−#define REG_A6XX_RBBM_PERFCTR_TP_7_LO 0x0000049c
1563−
1564−#define REG_A6XX_RBBM_PERFCTR_TP_7_HI 0x0000049d
1565−
1566−#define REG_A6XX_RBBM_PERFCTR_TP_8_LO 0x0000049e
1567−
1568−#define REG_A6XX_RBBM_PERFCTR_TP_8_HI 0x0000049f
1245+static inline uint32_t REG_A6XX_RBBM_PERFCTR_CP(uint32_t i0) { return 0x00000400 + 0x2*i0; }
15691246
1570−#define REG_A6XX_RBBM_PERFCTR_TP_9_LO 0x000004a0
1247+static inline uint32_t REG_A6XX_RBBM_PERFCTR_RBBM(uint32_t i0) { return 0x0000041c + 0x2*i0; }
15711248
1572−#define REG_A6XX_RBBM_PERFCTR_TP_9_HI 0x000004a1
1249+static inline uint32_t REG_A6XX_RBBM_PERFCTR_PC(uint32_t i0) { return 0x00000424 + 0x2*i0; }
15731250
1574−#define REG_A6XX_RBBM_PERFCTR_TP_10_LO 0x000004a2
1251+static inline uint32_t REG_A6XX_RBBM_PERFCTR_VFD(uint32_t i0) { return 0x00000434 + 0x2*i0; }
15751252
1576−#define REG_A6XX_RBBM_PERFCTR_TP_10_HI 0x000004a3
1253+static inline uint32_t REG_A6XX_RBBM_PERFCTR_HLSQ(uint32_t i0) { return 0x00000444 + 0x2*i0; }
15771254
1578−#define REG_A6XX_RBBM_PERFCTR_TP_11_LO 0x000004a4
1255+static inline uint32_t REG_A6XX_RBBM_PERFCTR_VPC(uint32_t i0) { return 0x00000450 + 0x2*i0; }
15791256
1580−#define REG_A6XX_RBBM_PERFCTR_TP_11_HI 0x000004a5
1257+static inline uint32_t REG_A6XX_RBBM_PERFCTR_CCU(uint32_t i0) { return 0x0000045c + 0x2*i0; }
15811258
1582−#define REG_A6XX_RBBM_PERFCTR_SP_0_LO 0x000004a6
1259+static inline uint32_t REG_A6XX_RBBM_PERFCTR_TSE(uint32_t i0) { return 0x00000466 + 0x2*i0; }
15831260
1584−#define REG_A6XX_RBBM_PERFCTR_SP_0_HI 0x000004a7
1261+static inline uint32_t REG_A6XX_RBBM_PERFCTR_RAS(uint32_t i0) { return 0x0000046e + 0x2*i0; }
15851262
1586−#define REG_A6XX_RBBM_PERFCTR_SP_1_LO 0x000004a8
1263+static inline uint32_t REG_A6XX_RBBM_PERFCTR_UCHE(uint32_t i0) { return 0x00000476 + 0x2*i0; }
15871264
1588−#define REG_A6XX_RBBM_PERFCTR_SP_1_HI 0x000004a9
1265+static inline uint32_t REG_A6XX_RBBM_PERFCTR_TP(uint32_t i0) { return 0x0000048e + 0x2*i0; }
15891266
1590−#define REG_A6XX_RBBM_PERFCTR_SP_2_LO 0x000004aa
1267+static inline uint32_t REG_A6XX_RBBM_PERFCTR_SP(uint32_t i0) { return 0x000004a6 + 0x2*i0; }
15911268
1592−#define REG_A6XX_RBBM_PERFCTR_SP_2_HI 0x000004ab
1269+static inline uint32_t REG_A6XX_RBBM_PERFCTR_RB(uint32_t i0) { return 0x000004d6 + 0x2*i0; }
15931270
1594−#define REG_A6XX_RBBM_PERFCTR_SP_3_LO 0x000004ac
1271+static inline uint32_t REG_A6XX_RBBM_PERFCTR_VSC(uint32_t i0) { return 0x000004e6 + 0x2*i0; }
15951272
1596−#define REG_A6XX_RBBM_PERFCTR_SP_3_HI 0x000004ad
1273+static inline uint32_t REG_A6XX_RBBM_PERFCTR_LRZ(uint32_t i0) { return 0x000004ea + 0x2*i0; }
15971274
1598−#define REG_A6XX_RBBM_PERFCTR_SP_4_LO 0x000004ae
1599−
1600−#define REG_A6XX_RBBM_PERFCTR_SP_4_HI 0x000004af
1601−
1602−#define REG_A6XX_RBBM_PERFCTR_SP_5_LO 0x000004b0
1603−
1604−#define REG_A6XX_RBBM_PERFCTR_SP_5_HI 0x000004b1
1605−
1606−#define REG_A6XX_RBBM_PERFCTR_SP_6_LO 0x000004b2
1607−
1608−#define REG_A6XX_RBBM_PERFCTR_SP_6_HI 0x000004b3
1609−
1610−#define REG_A6XX_RBBM_PERFCTR_SP_7_LO 0x000004b4
1611−
1612−#define REG_A6XX_RBBM_PERFCTR_SP_7_HI 0x000004b5
1613−
1614−#define REG_A6XX_RBBM_PERFCTR_SP_8_LO 0x000004b6
1615−
1616−#define REG_A6XX_RBBM_PERFCTR_SP_8_HI 0x000004b7
1617−
1618−#define REG_A6XX_RBBM_PERFCTR_SP_9_LO 0x000004b8
1619−
1620−#define REG_A6XX_RBBM_PERFCTR_SP_9_HI 0x000004b9
1621−
1622−#define REG_A6XX_RBBM_PERFCTR_SP_10_LO 0x000004ba
1623−
1624−#define REG_A6XX_RBBM_PERFCTR_SP_10_HI 0x000004bb
1625−
1626−#define REG_A6XX_RBBM_PERFCTR_SP_11_LO 0x000004bc
1627−
1628−#define REG_A6XX_RBBM_PERFCTR_SP_11_HI 0x000004bd
1629−
1630−#define REG_A6XX_RBBM_PERFCTR_SP_12_LO 0x000004be
1631−
1632−#define REG_A6XX_RBBM_PERFCTR_SP_12_HI 0x000004bf
1633−
1634−#define REG_A6XX_RBBM_PERFCTR_SP_13_LO 0x000004c0
1635−
1636−#define REG_A6XX_RBBM_PERFCTR_SP_13_HI 0x000004c1
1637−
1638−#define REG_A6XX_RBBM_PERFCTR_SP_14_LO 0x000004c2
1639−
1640−#define REG_A6XX_RBBM_PERFCTR_SP_14_HI 0x000004c3
1641−
1642−#define REG_A6XX_RBBM_PERFCTR_SP_15_LO 0x000004c4
1643−
1644−#define REG_A6XX_RBBM_PERFCTR_SP_15_HI 0x000004c5
1645−
1646−#define REG_A6XX_RBBM_PERFCTR_SP_16_LO 0x000004c6
1647−
1648−#define REG_A6XX_RBBM_PERFCTR_SP_16_HI 0x000004c7
1649−
1650−#define REG_A6XX_RBBM_PERFCTR_SP_17_LO 0x000004c8
1651−
1652−#define REG_A6XX_RBBM_PERFCTR_SP_17_HI 0x000004c9
1653−
1654−#define REG_A6XX_RBBM_PERFCTR_SP_18_LO 0x000004ca
1655−
1656−#define REG_A6XX_RBBM_PERFCTR_SP_18_HI 0x000004cb
1657−
1658−#define REG_A6XX_RBBM_PERFCTR_SP_19_LO 0x000004cc
1659−
1660−#define REG_A6XX_RBBM_PERFCTR_SP_19_HI 0x000004cd
1661−
1662−#define REG_A6XX_RBBM_PERFCTR_SP_20_LO 0x000004ce
1663−
1664−#define REG_A6XX_RBBM_PERFCTR_SP_20_HI 0x000004cf
1665−
1666−#define REG_A6XX_RBBM_PERFCTR_SP_21_LO 0x000004d0
1667−
1668−#define REG_A6XX_RBBM_PERFCTR_SP_21_HI 0x000004d1
1669−
1670−#define REG_A6XX_RBBM_PERFCTR_SP_22_LO 0x000004d2
1671−
1672−#define REG_A6XX_RBBM_PERFCTR_SP_22_HI 0x000004d3
1673−
1674−#define REG_A6XX_RBBM_PERFCTR_SP_23_LO 0x000004d4
1675−
1676−#define REG_A6XX_RBBM_PERFCTR_SP_23_HI 0x000004d5
1677−
1678−#define REG_A6XX_RBBM_PERFCTR_RB_0_LO 0x000004d6
1679−
1680−#define REG_A6XX_RBBM_PERFCTR_RB_0_HI 0x000004d7
1681−
1682−#define REG_A6XX_RBBM_PERFCTR_RB_1_LO 0x000004d8
1683−
1684−#define REG_A6XX_RBBM_PERFCTR_RB_1_HI 0x000004d9
1685−
1686−#define REG_A6XX_RBBM_PERFCTR_RB_2_LO 0x000004da
1687−
1688−#define REG_A6XX_RBBM_PERFCTR_RB_2_HI 0x000004db
1689−
1690−#define REG_A6XX_RBBM_PERFCTR_RB_3_LO 0x000004dc
1691−
1692−#define REG_A6XX_RBBM_PERFCTR_RB_3_HI 0x000004dd
1693−
1694−#define REG_A6XX_RBBM_PERFCTR_RB_4_LO 0x000004de
1695−
1696−#define REG_A6XX_RBBM_PERFCTR_RB_4_HI 0x000004df
1697−
1698−#define REG_A6XX_RBBM_PERFCTR_RB_5_LO 0x000004e0
1699−
1700−#define REG_A6XX_RBBM_PERFCTR_RB_5_HI 0x000004e1
1701−
1702−#define REG_A6XX_RBBM_PERFCTR_RB_6_LO 0x000004e2
1703−
1704−#define REG_A6XX_RBBM_PERFCTR_RB_6_HI 0x000004e3
1705−
1706−#define REG_A6XX_RBBM_PERFCTR_RB_7_LO 0x000004e4
1707−
1708−#define REG_A6XX_RBBM_PERFCTR_RB_7_HI 0x000004e5
1709−
1710−#define REG_A6XX_RBBM_PERFCTR_VSC_0_LO 0x000004e6
1711−
1712−#define REG_A6XX_RBBM_PERFCTR_VSC_0_HI 0x000004e7
1713−
1714−#define REG_A6XX_RBBM_PERFCTR_VSC_1_LO 0x000004e8
1715−
1716−#define REG_A6XX_RBBM_PERFCTR_VSC_1_HI 0x000004e9
1717−
1718−#define REG_A6XX_RBBM_PERFCTR_LRZ_0_LO 0x000004ea
1719−
1720−#define REG_A6XX_RBBM_PERFCTR_LRZ_0_HI 0x000004eb
1721−
1722−#define REG_A6XX_RBBM_PERFCTR_LRZ_1_LO 0x000004ec
1723−
1724−#define REG_A6XX_RBBM_PERFCTR_LRZ_1_HI 0x000004ed
1725−
1726−#define REG_A6XX_RBBM_PERFCTR_LRZ_2_LO 0x000004ee
1727−
1728−#define REG_A6XX_RBBM_PERFCTR_LRZ_2_HI 0x000004ef
1729−
1730−#define REG_A6XX_RBBM_PERFCTR_LRZ_3_LO 0x000004f0
1731−
1732−#define REG_A6XX_RBBM_PERFCTR_LRZ_3_HI 0x000004f1
1733−
1734−#define REG_A6XX_RBBM_PERFCTR_CMP_0_LO 0x000004f2
1735−
1736−#define REG_A6XX_RBBM_PERFCTR_CMP_0_HI 0x000004f3
1737−
1738−#define REG_A6XX_RBBM_PERFCTR_CMP_1_LO 0x000004f4
1739−
1740−#define REG_A6XX_RBBM_PERFCTR_CMP_1_HI 0x000004f5
1741−
1742−#define REG_A6XX_RBBM_PERFCTR_CMP_2_LO 0x000004f6
1743−
1744−#define REG_A6XX_RBBM_PERFCTR_CMP_2_HI 0x000004f7
1745−
1746−#define REG_A6XX_RBBM_PERFCTR_CMP_3_LO 0x000004f8
1747−
1748−#define REG_A6XX_RBBM_PERFCTR_CMP_3_HI 0x000004f9
1275+static inline uint32_t REG_A6XX_RBBM_PERFCTR_CMP(uint32_t i0) { return 0x000004f2 + 0x2*i0; }
17491276
17501277 #define REG_A6XX_RBBM_PERFCTR_CNTL 0x00000500
17511278
@@ -1761,13 +1288,7 @@ static inline uint32_t A6XX_CP_CSQ_IB2_STAT_REM(uint32_t val) · 9 unmodified lines
17611288
17621289 #define REG_A6XX_RBBM_PERFCTR_LOAD_VALUE_HI 0x00000506
17631290
1764−#define REG_A6XX_RBBM_PERFCTR_RBBM_SEL_0 0x00000507
1765−
1766−#define REG_A6XX_RBBM_PERFCTR_RBBM_SEL_1 0x00000508
1767−
1768−#define REG_A6XX_RBBM_PERFCTR_RBBM_SEL_2 0x00000509
1769−
1770−#define REG_A6XX_RBBM_PERFCTR_RBBM_SEL_3 0x0000050a
1291+static inline uint32_t REG_A6XX_RBBM_PERFCTR_RBBM_SEL(uint32_t i0) { return 0x00000507 + 0x1*i0; }
17711292
17721293 #define REG_A6XX_RBBM_PERFCTR_GPU_BUSY_MASKED 0x0000050b
17731294
@@ -2231,204 +1752,60 @@ static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL14(uint32_t val) · 457 unmodified lines
22311752 }
22321753 #define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL15__MASK 0xf0000000
22331754 #define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL15__SHIFT 28
2234−static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL15(uint32_t val)
2235−{
2236− return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL15__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL15__MASK;
2237−}
2238−
2239−#define REG_A6XX_DBGC_CFG_DBGBUS_TRACE_BUF1 0x0000062f
2240−
2241−#define REG_A6XX_DBGC_CFG_DBGBUS_TRACE_BUF2 0x00000630
2242−
2243−#define REG_A6XX_VSC_PERFCTR_VSC_SEL_0 0x00000cd8
2244−
2245−#define REG_A6XX_VSC_PERFCTR_VSC_SEL_1 0x00000cd9
2246−
2247−#define REG_A6XX_HLSQ_ADDR_MODE_CNTL 0x0000be05
2248−
2249−#define REG_A6XX_HLSQ_PERFCTR_HLSQ_SEL_0 0x0000be10
2250−
2251−#define REG_A6XX_HLSQ_PERFCTR_HLSQ_SEL_1 0x0000be11
2252−
2253−#define REG_A6XX_HLSQ_PERFCTR_HLSQ_SEL_2 0x0000be12
2254−
2255−#define REG_A6XX_HLSQ_PERFCTR_HLSQ_SEL_3 0x0000be13
2256−
2257−#define REG_A6XX_HLSQ_PERFCTR_HLSQ_SEL_4 0x0000be14
2258−
2259−#define REG_A6XX_HLSQ_PERFCTR_HLSQ_SEL_5 0x0000be15
2260−
2261−#define REG_A6XX_HLSQ_DBG_AHB_READ_APERTURE 0x0000c800
2262−
2263−#define REG_A6XX_HLSQ_DBG_READ_SEL 0x0000d000
2264−
2265−#define REG_A6XX_VFD_ADDR_MODE_CNTL 0x0000a601
2266−
2267−#define REG_A6XX_VFD_PERFCTR_VFD_SEL_0 0x0000a610
2268−
2269−#define REG_A6XX_VFD_PERFCTR_VFD_SEL_1 0x0000a611
2270−
2271−#define REG_A6XX_VFD_PERFCTR_VFD_SEL_2 0x0000a612
2272−
2273−#define REG_A6XX_VFD_PERFCTR_VFD_SEL_3 0x0000a613
2274−
2275−#define REG_A6XX_VFD_PERFCTR_VFD_SEL_4 0x0000a614
2276−
2277−#define REG_A6XX_VFD_PERFCTR_VFD_SEL_5 0x0000a615
2278−
2279−#define REG_A6XX_VFD_PERFCTR_VFD_SEL_6 0x0000a616
2280−
2281−#define REG_A6XX_VFD_PERFCTR_VFD_SEL_7 0x0000a617
2282−
2283−#define REG_A6XX_UCHE_ADDR_MODE_CNTL 0x00000e00
2284−
2285−#define REG_A6XX_UCHE_MODE_CNTL 0x00000e01
2286−
2287−#define REG_A6XX_UCHE_WRITE_RANGE_MAX_LO 0x00000e05
2288−
2289−#define REG_A6XX_UCHE_WRITE_RANGE_MAX_HI 0x00000e06
2290−
2291−#define REG_A6XX_UCHE_WRITE_THRU_BASE_LO 0x00000e07
2292−
2293−#define REG_A6XX_UCHE_WRITE_THRU_BASE_HI 0x00000e08
2294−
2295−#define REG_A6XX_UCHE_TRAP_BASE_LO 0x00000e09
2296−
2297−#define REG_A6XX_UCHE_TRAP_BASE_HI 0x00000e0a
2298−
2299−#define REG_A6XX_UCHE_GMEM_RANGE_MIN_LO 0x00000e0b
2300−
2301−#define REG_A6XX_UCHE_GMEM_RANGE_MIN_HI 0x00000e0c
2302−
2303−#define REG_A6XX_UCHE_GMEM_RANGE_MAX_LO 0x00000e0d
2304−
2305−#define REG_A6XX_UCHE_GMEM_RANGE_MAX_HI 0x00000e0e
2306−
2307−#define REG_A6XX_UCHE_CACHE_WAYS 0x00000e17
2308−
2309−#define REG_A6XX_UCHE_FILTER_CNTL 0x00000e18
2310−
2311−#define REG_A6XX_UCHE_CLIENT_PF 0x00000e19
2312−#define A6XX_UCHE_CLIENT_PF_PERFSEL__MASK 0x000000ff
2313−#define A6XX_UCHE_CLIENT_PF_PERFSEL__SHIFT 0
2314−static inline uint32_t A6XX_UCHE_CLIENT_PF_PERFSEL(uint32_t val)
2315−{
2316− return ((val) << A6XX_UCHE_CLIENT_PF_PERFSEL__SHIFT) & A6XX_UCHE_CLIENT_PF_PERFSEL__MASK;
2317−}
2318−
2319−#define REG_A6XX_UCHE_PERFCTR_UCHE_SEL_0 0x00000e1c
2320−
2321−#define REG_A6XX_UCHE_PERFCTR_UCHE_SEL_1 0x00000e1d
2322−
2323−#define REG_A6XX_UCHE_PERFCTR_UCHE_SEL_2 0x00000e1e
2324−
2325−#define REG_A6XX_UCHE_PERFCTR_UCHE_SEL_3 0x00000e1f
2326−
2327−#define REG_A6XX_UCHE_PERFCTR_UCHE_SEL_4 0x00000e20
2328−
2329−#define REG_A6XX_UCHE_PERFCTR_UCHE_SEL_5 0x00000e21
2330−
2331−#define REG_A6XX_UCHE_PERFCTR_UCHE_SEL_6 0x00000e22
2332−
2333−#define REG_A6XX_UCHE_PERFCTR_UCHE_SEL_7 0x00000e23
2334−
2335−#define REG_A6XX_UCHE_PERFCTR_UCHE_SEL_8 0x00000e24
2336−
2337−#define REG_A6XX_UCHE_PERFCTR_UCHE_SEL_9 0x00000e25
2338−
2339−#define REG_A6XX_UCHE_PERFCTR_UCHE_SEL_10 0x00000e26
2340−
2341−#define REG_A6XX_UCHE_PERFCTR_UCHE_SEL_11 0x00000e27
2342−
2343−#define REG_A6XX_SP_ADDR_MODE_CNTL 0x0000ae01
2344−
2345−#define REG_A6XX_SP_NC_MODE_CNTL 0x0000ae02
2346−
2347−#define REG_A6XX_SP_PERFCTR_SP_SEL_0 0x0000ae10
2348−
2349−#define REG_A6XX_SP_PERFCTR_SP_SEL_1 0x0000ae11
2350−
2351−#define REG_A6XX_SP_PERFCTR_SP_SEL_2 0x0000ae12
2352−
2353−#define REG_A6XX_SP_PERFCTR_SP_SEL_3 0x0000ae13
2354−
2355−#define REG_A6XX_SP_PERFCTR_SP_SEL_4 0x0000ae14
2356−
2357−#define REG_A6XX_SP_PERFCTR_SP_SEL_5 0x0000ae15
2358−
2359−#define REG_A6XX_SP_PERFCTR_SP_SEL_6 0x0000ae16
2360−
2361−#define REG_A6XX_SP_PERFCTR_SP_SEL_7 0x0000ae17
2362−
2363−#define REG_A6XX_SP_PERFCTR_SP_SEL_8 0x0000ae18
2364−
2365−#define REG_A6XX_SP_PERFCTR_SP_SEL_9 0x0000ae19
2366−
2367−#define REG_A6XX_SP_PERFCTR_SP_SEL_10 0x0000ae1a
2368−
2369−#define REG_A6XX_SP_PERFCTR_SP_SEL_11 0x0000ae1b
2370−
2371−#define REG_A6XX_SP_PERFCTR_SP_SEL_12 0x0000ae1c
2372−
2373−#define REG_A6XX_SP_PERFCTR_SP_SEL_13 0x0000ae1d
2374−
2375−#define REG_A6XX_SP_PERFCTR_SP_SEL_14 0x0000ae1e
2376−
2377−#define REG_A6XX_SP_PERFCTR_SP_SEL_15 0x0000ae1f
2378−
2379−#define REG_A6XX_SP_PERFCTR_SP_SEL_16 0x0000ae20
2380−
2381−#define REG_A6XX_SP_PERFCTR_SP_SEL_17 0x0000ae21
2382−
2383−#define REG_A6XX_SP_PERFCTR_SP_SEL_18 0x0000ae22
2384−
2385−#define REG_A6XX_SP_PERFCTR_SP_SEL_19 0x0000ae23
2386−
2387−#define REG_A6XX_SP_PERFCTR_SP_SEL_20 0x0000ae24
1755+static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL15(uint32_t val)
1756+{
1757+ return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL15__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL15__MASK;
1758+}
23881759
2389−#define REG_A6XX_SP_PERFCTR_SP_SEL_21 0x0000ae25
1760+#define REG_A6XX_DBGC_CFG_DBGBUS_TRACE_BUF1 0x0000062f
23901761
2391−#define REG_A6XX_SP_PERFCTR_SP_SEL_22 0x0000ae26
1762+#define REG_A6XX_DBGC_CFG_DBGBUS_TRACE_BUF2 0x00000630
23921763
2393−#define REG_A6XX_SP_PERFCTR_SP_SEL_23 0x0000ae27
1764+static inline uint32_t REG_A6XX_VSC_PERFCTR_VSC_SEL(uint32_t i0) { return 0x00000cd8 + 0x1*i0; }
23941765
2395−#define REG_A6XX_TPL1_ADDR_MODE_CNTL 0x0000b601
1766+#define REG_A6XX_HLSQ_DBG_AHB_READ_APERTURE 0x0000c800
23961767
2397−#define REG_A6XX_TPL1_NC_MODE_CNTL 0x0000b604
1768+#define REG_A6XX_HLSQ_DBG_READ_SEL 0x0000d000
23981769
2399−#define REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_0 0x0000b608
1770+#define REG_A6XX_UCHE_ADDR_MODE_CNTL 0x00000e00
24001771
2401−#define REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_1 0x0000b609
1772+#define REG_A6XX_UCHE_MODE_CNTL 0x00000e01
24021773
2403−#define REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_2 0x0000b60a
1774+#define REG_A6XX_UCHE_WRITE_RANGE_MAX_LO 0x00000e05
24041775
2405−#define REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_3 0x0000b60b
1776+#define REG_A6XX_UCHE_WRITE_RANGE_MAX_HI 0x00000e06
24061777
2407−#define REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_4 0x0000b60c
1778+#define REG_A6XX_UCHE_WRITE_THRU_BASE_LO 0x00000e07
24081779
2409−#define REG_A6XX_TPL1_PERFCTR_TP_SEL_0 0x0000b610
1780+#define REG_A6XX_UCHE_WRITE_THRU_BASE_HI 0x00000e08
24101781
2411−#define REG_A6XX_TPL1_PERFCTR_TP_SEL_1 0x0000b611
1782+#define REG_A6XX_UCHE_TRAP_BASE_LO 0x00000e09
24121783
2413−#define REG_A6XX_TPL1_PERFCTR_TP_SEL_2 0x0000b612
1784+#define REG_A6XX_UCHE_TRAP_BASE_HI 0x00000e0a
24141785
2415−#define REG_A6XX_TPL1_PERFCTR_TP_SEL_3 0x0000b613
1786+#define REG_A6XX_UCHE_GMEM_RANGE_MIN_LO 0x00000e0b
24161787
2417−#define REG_A6XX_TPL1_PERFCTR_TP_SEL_4 0x0000b614
1788+#define REG_A6XX_UCHE_GMEM_RANGE_MIN_HI 0x00000e0c
24181789
2419−#define REG_A6XX_TPL1_PERFCTR_TP_SEL_5 0x0000b615
1790+#define REG_A6XX_UCHE_GMEM_RANGE_MAX_LO 0x00000e0d
24201791
2421−#define REG_A6XX_TPL1_PERFCTR_TP_SEL_6 0x0000b616
1792+#define REG_A6XX_UCHE_GMEM_RANGE_MAX_HI 0x00000e0e
24221793
2423−#define REG_A6XX_TPL1_PERFCTR_TP_SEL_7 0x0000b617
1794+#define REG_A6XX_UCHE_CACHE_WAYS 0x00000e17
24241795
2425−#define REG_A6XX_TPL1_PERFCTR_TP_SEL_8 0x0000b618
1796+#define REG_A6XX_UCHE_FILTER_CNTL 0x00000e18
24261797
2427−#define REG_A6XX_TPL1_PERFCTR_TP_SEL_9 0x0000b619
1798+#define REG_A6XX_UCHE_CLIENT_PF 0x00000e19
1799+#define A6XX_UCHE_CLIENT_PF_PERFSEL__MASK 0x000000ff
1800+#define A6XX_UCHE_CLIENT_PF_PERFSEL__SHIFT 0
1801+static inline uint32_t A6XX_UCHE_CLIENT_PF_PERFSEL(uint32_t val)
1802+{
1803+ return ((val) << A6XX_UCHE_CLIENT_PF_PERFSEL__SHIFT) & A6XX_UCHE_CLIENT_PF_PERFSEL__MASK;
1804+}
24281805
2429−#define REG_A6XX_TPL1_PERFCTR_TP_SEL_10 0x0000b61a
1806+static inline uint32_t REG_A6XX_UCHE_PERFCTR_UCHE_SEL(uint32_t i0) { return 0x00000e1c + 0x1*i0; }
24301807
2431−#define REG_A6XX_TPL1_PERFCTR_TP_SEL_11 0x0000b61b
1808+#define REG_A6XX_UCHE_CMDQ_CONFIG 0x00000e3c
24321809
24331810 #define REG_A6XX_VBIF_VERSION 0x00003000
24341811
@@ -2507,6 +1884,8 @@ static inline uint32_t A6XX_VBIF_TEST_BUS2_CTRL1_DATA_SEL(uint32_t val) · 72 unmodified lines
25071884
25081885 #define REG_A6XX_VBIF_PERF_PWR_CNT_HIGH2 0x0000311a
25091886
1887+#define REG_A6XX_GBIF_SCACHE_CNTL0 0x00003c01
1888+
25101889 #define REG_A6XX_GBIF_SCACHE_CNTL1 0x00003c02
25111890
25121891 #define REG_A6XX_GBIF_QSB_SIDE0 0x00003c03
@@ -2555,36 +1934,6 @@ static inline uint32_t A6XX_VBIF_TEST_BUS2_CTRL1_DATA_SEL(uint32_t val) · 42 unmodified lines
25551934
25561935 #define REG_A6XX_GBIF_PWR_CNT_HIGH2 0x00003cd1
25571936
2558−#define REG_A6XX_SP_WINDOW_OFFSET 0x0000b4d1
2559−#define A6XX_SP_WINDOW_OFFSET_WINDOW_OFFSET_DISABLE 0x80000000
2560−#define A6XX_SP_WINDOW_OFFSET_X__MASK 0x00007fff
2561−#define A6XX_SP_WINDOW_OFFSET_X__SHIFT 0
2562−static inline uint32_t A6XX_SP_WINDOW_OFFSET_X(uint32_t val)
2563−{
2564− return ((val) << A6XX_SP_WINDOW_OFFSET_X__SHIFT) & A6XX_SP_WINDOW_OFFSET_X__MASK;
2565−}
2566−#define A6XX_SP_WINDOW_OFFSET_Y__MASK 0x7fff0000
2567−#define A6XX_SP_WINDOW_OFFSET_Y__SHIFT 16
2568−static inline uint32_t A6XX_SP_WINDOW_OFFSET_Y(uint32_t val)
2569−{
2570− return ((val) << A6XX_SP_WINDOW_OFFSET_Y__SHIFT) & A6XX_SP_WINDOW_OFFSET_Y__MASK;
2571−}
2572−
2573−#define REG_A6XX_SP_TP_WINDOW_OFFSET 0x0000b307
2574−#define A6XX_SP_TP_WINDOW_OFFSET_WINDOW_OFFSET_DISABLE 0x80000000
2575−#define A6XX_SP_TP_WINDOW_OFFSET_X__MASK 0x00007fff
2576−#define A6XX_SP_TP_WINDOW_OFFSET_X__SHIFT 0
2577−static inline uint32_t A6XX_SP_TP_WINDOW_OFFSET_X(uint32_t val)
2578−{
2579− return ((val) << A6XX_SP_TP_WINDOW_OFFSET_X__SHIFT) & A6XX_SP_TP_WINDOW_OFFSET_X__MASK;
2580−}
2581−#define A6XX_SP_TP_WINDOW_OFFSET_Y__MASK 0x7fff0000
2582−#define A6XX_SP_TP_WINDOW_OFFSET_Y__SHIFT 16
2583−static inline uint32_t A6XX_SP_TP_WINDOW_OFFSET_Y(uint32_t val)
2584−{
2585− return ((val) << A6XX_SP_TP_WINDOW_OFFSET_Y__SHIFT) & A6XX_SP_TP_WINDOW_OFFSET_Y__MASK;
2586−}
2587−
25881937 #define REG_A6XX_VSC_BIN_SIZE 0x00000c02
25891938 #define A6XX_VSC_BIN_SIZE_WIDTH__MASK 0x000000ff
25901939 #define A6XX_VSC_BIN_SIZE_WIDTH__SHIFT 0
@@ -2599,10 +1948,6 @@ static inline uint32_t A6XX_VSC_BIN_SIZE_HEIGHT(uint32_t val) · 8 unmodified lines
25991948 return ((val >> 4) << A6XX_VSC_BIN_SIZE_HEIGHT__SHIFT) & A6XX_VSC_BIN_SIZE_HEIGHT__MASK;
26001949 }
26011950
2602−#define REG_A6XX_VSC_DRAW_STRM_SIZE_ADDRESS_LO 0x00000c03
2603−
2604−#define REG_A6XX_VSC_DRAW_STRM_SIZE_ADDRESS_HI 0x00000c04
2605−
26061951 #define REG_A6XX_VSC_DRAW_STRM_SIZE_ADDRESS 0x00000c03
26071952
26081953 #define REG_A6XX_VSC_BIN_COUNT 0x00000c06
@@ -2647,20 +1992,12 @@ static inline uint32_t A6XX_VSC_PIPE_CONFIG_REG_H(uint32_t val) · 38 unmodified lines
26471992 return ((val) << A6XX_VSC_PIPE_CONFIG_REG_H__SHIFT) & A6XX_VSC_PIPE_CONFIG_REG_H__MASK;
26481993 }
26491994
2650−#define REG_A6XX_VSC_PRIM_STRM_ADDRESS_LO 0x00000c30
2651−
2652−#define REG_A6XX_VSC_PRIM_STRM_ADDRESS_HI 0x00000c31
2653−
26541995 #define REG_A6XX_VSC_PRIM_STRM_ADDRESS 0x00000c30
26551996
26561997 #define REG_A6XX_VSC_PRIM_STRM_PITCH 0x00000c32
26571998
26581999 #define REG_A6XX_VSC_PRIM_STRM_LIMIT 0x00000c33
26592000
2660−#define REG_A6XX_VSC_DRAW_STRM_ADDRESS_LO 0x00000c34
2661−
2662−#define REG_A6XX_VSC_DRAW_STRM_ADDRESS_HI 0x00000c35
2663−
26642001 #define REG_A6XX_VSC_DRAW_STRM_ADDRESS 0x00000c34
26652002
26662003 #define REG_A6XX_VSC_DRAW_STRM_PITCH 0x00000c36
@@ -2849,12 +2186,20 @@ static inline uint32_t A6XX_GRAS_SU_CNTL_UNK12(uint32_t val) · 182 unmodified lines
28492186 return ((val) << A6XX_GRAS_SU_CNTL_UNK12__SHIFT) & A6XX_GRAS_SU_CNTL_UNK12__MASK;
28502187 }
28512188 #define A6XX_GRAS_SU_CNTL_MSAA_ENABLE 0x00002000
2852−#define A6XX_GRAS_SU_CNTL_UNK15__MASK 0x007f8000
2189+#define A6XX_GRAS_SU_CNTL_UNK15__MASK 0x00018000
28532190 #define A6XX_GRAS_SU_CNTL_UNK15__SHIFT 15
28542191 static inline uint32_t A6XX_GRAS_SU_CNTL_UNK15(uint32_t val)
28552192 {
28562193 return ((val) << A6XX_GRAS_SU_CNTL_UNK15__SHIFT) & A6XX_GRAS_SU_CNTL_UNK15__MASK;
28572194 }
2195+#define A6XX_GRAS_SU_CNTL_UNK17 0x00020000
2196+#define A6XX_GRAS_SU_CNTL_MULTIVIEW_ENABLE 0x00040000
2197+#define A6XX_GRAS_SU_CNTL_UNK19__MASK 0x00780000
2198+#define A6XX_GRAS_SU_CNTL_UNK19__SHIFT 19
2199+static inline uint32_t A6XX_GRAS_SU_CNTL_UNK19(uint32_t val)
2200+{
2201+ return ((val) << A6XX_GRAS_SU_CNTL_UNK19__SHIFT) & A6XX_GRAS_SU_CNTL_UNK19__MASK;
2202+}
28582203
28592204 #define REG_A6XX_GRAS_SU_POINT_MINMAX 0x00008091
28602205 #define A6XX_GRAS_SU_POINT_MINMAX_MIN__MASK 0x0000ffff
@@ -3205,11 +2550,12 @@ static inline uint32_t A6XX_GRAS_SC_WINDOW_SCISSOR_BR_Y(uint32_t val) · 344 unmodified lines
32052550 #define A6XX_GRAS_LRZ_CNTL_GREATER 0x00000004
32062551 #define A6XX_GRAS_LRZ_CNTL_FC_ENABLE 0x00000008
32072552 #define A6XX_GRAS_LRZ_CNTL_Z_TEST_ENABLE 0x00000010
3208−#define A6XX_GRAS_LRZ_CNTL_UNK5__MASK 0x000003e0
3209−#define A6XX_GRAS_LRZ_CNTL_UNK5__SHIFT 5
3210−static inline uint32_t A6XX_GRAS_LRZ_CNTL_UNK5(uint32_t val)
2553+#define A6XX_GRAS_LRZ_CNTL_Z_BOUNDS_ENABLE 0x00000020
2554+#define A6XX_GRAS_LRZ_CNTL_UNK6__MASK 0x000003c0
2555+#define A6XX_GRAS_LRZ_CNTL_UNK6__SHIFT 6
2556+static inline uint32_t A6XX_GRAS_LRZ_CNTL_UNK6(uint32_t val)
32112557 {
3212− return ((val) << A6XX_GRAS_LRZ_CNTL_UNK5__SHIFT) & A6XX_GRAS_LRZ_CNTL_UNK5__MASK;
2558+ return ((val) << A6XX_GRAS_LRZ_CNTL_UNK6__SHIFT) & A6XX_GRAS_LRZ_CNTL_UNK6__MASK;
32132559 }
32142560
32152561 #define REG_A6XX_GRAS_UNKNOWN_8101 0x00008101
@@ -3222,10 +2568,6 @@ static inline uint32_t A6XX_GRAS_2D_BLIT_INFO_COLOR_FORMAT(enum a6xx_format val) · 6 unmodified lines
32222568 return ((val) << A6XX_GRAS_2D_BLIT_INFO_COLOR_FORMAT__SHIFT) & A6XX_GRAS_2D_BLIT_INFO_COLOR_FORMAT__MASK;
32232569 }
32242570
3225−#define REG_A6XX_GRAS_LRZ_BUFFER_BASE_LO 0x00008103
3226−
3227−#define REG_A6XX_GRAS_LRZ_BUFFER_BASE_HI 0x00008104
3228−
32292571 #define REG_A6XX_GRAS_LRZ_BUFFER_BASE 0x00008103
32302572 #define A6XX_GRAS_LRZ_BUFFER_BASE__MASK 0xffffffff
32312573 #define A6XX_GRAS_LRZ_BUFFER_BASE__SHIFT 0
@@ -3248,10 +2590,6 @@ static inline uint32_t A6XX_GRAS_LRZ_BUFFER_PITCH_ARRAY_PITCH(uint32_t val) · 16 unmodified lines
32482590 return ((val >> 4) << A6XX_GRAS_LRZ_BUFFER_PITCH_ARRAY_PITCH__SHIFT) & A6XX_GRAS_LRZ_BUFFER_PITCH_ARRAY_PITCH__MASK;
32492591 }
32502592
3251−#define REG_A6XX_GRAS_LRZ_FAST_CLEAR_BUFFER_BASE_LO 0x00008106
3252−
3253−#define REG_A6XX_GRAS_LRZ_FAST_CLEAR_BUFFER_BASE_HI 0x00008107
3254−
32552593 #define REG_A6XX_GRAS_LRZ_FAST_CLEAR_BUFFER_BASE 0x00008106
32562594 #define A6XX_GRAS_LRZ_FAST_CLEAR_BUFFER_BASE__MASK 0xffffffff
32572595 #define A6XX_GRAS_LRZ_FAST_CLEAR_BUFFER_BASE__SHIFT 0
@@ -3406,29 +2744,11 @@ static inline uint32_t A6XX_GRAS_2D_RESOLVE_CNTL_2_Y(uint32_t val) · 148 unmodified lines
34062744
34072745 #define REG_A6XX_GRAS_ADDR_MODE_CNTL 0x00008601
34082746
3409−#define REG_A6XX_GRAS_PERFCTR_TSE_SEL_0 0x00008610
3410−
3411−#define REG_A6XX_GRAS_PERFCTR_TSE_SEL_1 0x00008611
3412−
3413−#define REG_A6XX_GRAS_PERFCTR_TSE_SEL_2 0x00008612
3414−
3415−#define REG_A6XX_GRAS_PERFCTR_TSE_SEL_3 0x00008613
3416−
3417−#define REG_A6XX_GRAS_PERFCTR_RAS_SEL_0 0x00008614
3418−
3419−#define REG_A6XX_GRAS_PERFCTR_RAS_SEL_1 0x00008615
3420−
3421−#define REG_A6XX_GRAS_PERFCTR_RAS_SEL_2 0x00008616
3422−
3423−#define REG_A6XX_GRAS_PERFCTR_RAS_SEL_3 0x00008617
2747+static inline uint32_t REG_A6XX_GRAS_PERFCTR_TSE_SEL(uint32_t i0) { return 0x00008610 + 0x1*i0; }
34242748
3425−#define REG_A6XX_GRAS_PERFCTR_LRZ_SEL_0 0x00008618
2749+static inline uint32_t REG_A6XX_GRAS_PERFCTR_RAS_SEL(uint32_t i0) { return 0x00008614 + 0x1*i0; }
34262750
3427−#define REG_A6XX_GRAS_PERFCTR_LRZ_SEL_1 0x00008619
3428−
3429−#define REG_A6XX_GRAS_PERFCTR_LRZ_SEL_2 0x0000861a
3430−
3431−#define REG_A6XX_GRAS_PERFCTR_LRZ_SEL_3 0x0000861b
2751+static inline uint32_t REG_A6XX_GRAS_PERFCTR_LRZ_SEL(uint32_t i0) { return 0x00008618 + 0x1*i0; }
34322752
34332753 #define REG_A6XX_RB_BIN_CONTROL 0x00008800
34342754 #define A6XX_RB_BIN_CONTROL_BINW__MASK 0x0000003f
@@ -3889,10 +3209,6 @@ static inline uint32_t A6XX_RB_MRT_ARRAY_PITCH(uint32_t val) · 454 unmodified lines
38893209 return ((val >> 6) << A6XX_RB_MRT_ARRAY_PITCH__SHIFT) & A6XX_RB_MRT_ARRAY_PITCH__MASK;
38903210 }
38913211
3892−static inline uint32_t REG_A6XX_RB_MRT_BASE_LO(uint32_t i0) { return 0x00008825 + 0x8*i0; }
3893−
3894−static inline uint32_t REG_A6XX_RB_MRT_BASE_HI(uint32_t i0) { return 0x00008826 + 0x8*i0; }
3895−
38963212 static inline uint32_t REG_A6XX_RB_MRT_BASE(uint32_t i0) { return 0x00008825 + 0x8*i0; }
38973213 #define A6XX_RB_MRT_BASE__MASK 0xffffffff
38983214 #define A6XX_RB_MRT_BASE__SHIFT 0
@@ -4025,10 +3341,6 @@ static inline uint32_t A6XX_RB_DEPTH_BUFFER_ARRAY_PITCH(uint32_t val) · 126 unmodified lines
40253341 return ((val >> 6) << A6XX_RB_DEPTH_BUFFER_ARRAY_PITCH__SHIFT) & A6XX_RB_DEPTH_BUFFER_ARRAY_PITCH__MASK;
40263342 }
40273343
4028−#define REG_A6XX_RB_DEPTH_BUFFER_BASE_LO 0x00008875
4029−
4030−#define REG_A6XX_RB_DEPTH_BUFFER_BASE_HI 0x00008876
4031−
40323344 #define REG_A6XX_RB_DEPTH_BUFFER_BASE 0x00008875
40333345 #define A6XX_RB_DEPTH_BUFFER_BASE__MASK 0xffffffff
40343346 #define A6XX_RB_DEPTH_BUFFER_BASE__SHIFT 0
@@ -4134,10 +3446,6 @@ static inline uint32_t A6XX_RB_STENCIL_BUFFER_ARRAY_PITCH(uint32_t val) · 99 unmodified lines
41343446 return ((val >> 6) << A6XX_RB_STENCIL_BUFFER_ARRAY_PITCH__SHIFT) & A6XX_RB_STENCIL_BUFFER_ARRAY_PITCH__MASK;
41353447 }
41363448
4137−#define REG_A6XX_RB_STENCIL_BUFFER_BASE_LO 0x00008884
4138−
4139−#define REG_A6XX_RB_STENCIL_BUFFER_BASE_HI 0x00008885
4140−
41413449 #define REG_A6XX_RB_STENCIL_BUFFER_BASE 0x00008884
41423450 #define A6XX_RB_STENCIL_BUFFER_BASE__MASK 0xffffffff
41433451 #define A6XX_RB_STENCIL_BUFFER_BASE__SHIFT 0
@@ -4355,10 +3663,6 @@ static inline uint32_t A6XX_RB_BLIT_DST(uint32_t val) · 211 unmodified lines
43553663 return ((val) << A6XX_RB_BLIT_DST__SHIFT) & A6XX_RB_BLIT_DST__MASK;
43563664 }
43573665
4358−#define REG_A6XX_RB_BLIT_DST_LO 0x000088d8
4359−
4360−#define REG_A6XX_RB_BLIT_DST_HI 0x000088d9
4361−
43623666 #define REG_A6XX_RB_BLIT_DST_PITCH 0x000088da
43633667 #define A6XX_RB_BLIT_DST_PITCH__MASK 0x0000ffff
43643668 #define A6XX_RB_BLIT_DST_PITCH__SHIFT 0
@@ -4383,10 +3687,6 @@ static inline uint32_t A6XX_RB_BLIT_FLAG_DST(uint32_t val) · 18 unmodified lines
43833687 return ((val) << A6XX_RB_BLIT_FLAG_DST__SHIFT) & A6XX_RB_BLIT_FLAG_DST__MASK;
43843688 }
43853689
4386−#define REG_A6XX_RB_BLIT_FLAG_DST_LO 0x000088dc
4387−
4388−#define REG_A6XX_RB_BLIT_FLAG_DST_HI 0x000088dd
4389−
43903690 #define REG_A6XX_RB_BLIT_FLAG_DST_PITCH 0x000088de
43913691 #define A6XX_RB_BLIT_FLAG_DST_PITCH_PITCH__MASK 0x000007ff
43923692 #define A6XX_RB_BLIT_FLAG_DST_PITCH_PITCH__SHIFT 0
@@ -4412,7 +3712,7 @@ static inline uint32_t A6XX_RB_BLIT_FLAG_DST_PITCH_ARRAY_PITCH(uint32_t val) · 19 unmodified lines
44123712 #define REG_A6XX_RB_BLIT_INFO 0x000088e3
44133713 #define A6XX_RB_BLIT_INFO_UNK0 0x00000001
44143714 #define A6XX_RB_BLIT_INFO_GMEM 0x00000002
4415−#define A6XX_RB_BLIT_INFO_INTEGER 0x00000004
3715+#define A6XX_RB_BLIT_INFO_SAMPLE_0 0x00000004
44163716 #define A6XX_RB_BLIT_INFO_DEPTH 0x00000008
44173717 #define A6XX_RB_BLIT_INFO_CLEAR_MASK__MASK 0x000000f0
44183718 #define A6XX_RB_BLIT_INFO_CLEAR_MASK__SHIFT 4
@@ -4459,10 +3759,6 @@ static inline uint32_t A6XX_RB_UNK_FLAG_BUFFER_PITCH_ARRAY_PITCH(uint32_t val) · 40 unmodified lines
44593759
44603760 #define REG_A6XX_RB_UNKNOWN_88F4 0x000088f4
44613761
4462−#define REG_A6XX_RB_DEPTH_FLAG_BUFFER_BASE_LO 0x00008900
4463−
4464−#define REG_A6XX_RB_DEPTH_FLAG_BUFFER_BASE_HI 0x00008901
4465−
44663762 #define REG_A6XX_RB_DEPTH_FLAG_BUFFER_BASE 0x00008900
44673763 #define A6XX_RB_DEPTH_FLAG_BUFFER_BASE__MASK 0xffffffff
44683764 #define A6XX_RB_DEPTH_FLAG_BUFFER_BASE__SHIFT 0
@@ -4493,10 +3789,6 @@ static inline uint32_t A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_ARRAY_PITCH(uint32_t val) · 24 unmodified lines
44933789
44943790 static inline uint32_t REG_A6XX_RB_MRT_FLAG_BUFFER(uint32_t i0) { return 0x00008903 + 0x3*i0; }
44953791
4496−static inline uint32_t REG_A6XX_RB_MRT_FLAG_BUFFER_ADDR_LO(uint32_t i0) { return 0x00008903 + 0x3*i0; }
4497−
4498−static inline uint32_t REG_A6XX_RB_MRT_FLAG_BUFFER_ADDR_HI(uint32_t i0) { return 0x00008904 + 0x3*i0; }
4499−
45003792 static inline uint32_t REG_A6XX_RB_MRT_FLAG_BUFFER_ADDR(uint32_t i0) { return 0x00008903 + 0x3*i0; }
45013793 #define A6XX_RB_MRT_FLAG_BUFFER_ADDR__MASK 0xffffffff
45023794 #define A6XX_RB_MRT_FLAG_BUFFER_ADDR__SHIFT 0
@@ -4519,10 +3811,6 @@ static inline uint32_t A6XX_RB_MRT_FLAG_BUFFER_PITCH_ARRAY_PITCH(uint32_t val) · 16 unmodified lines
45193811 return ((val >> 7) << A6XX_RB_MRT_FLAG_BUFFER_PITCH_ARRAY_PITCH__SHIFT) & A6XX_RB_MRT_FLAG_BUFFER_PITCH_ARRAY_PITCH__MASK;
45203812 }
45213813
4522−#define REG_A6XX_RB_SAMPLE_COUNT_ADDR_LO 0x00008927
4523−
4524−#define REG_A6XX_RB_SAMPLE_COUNT_ADDR_HI 0x00008928
4525−
45263814 #define REG_A6XX_RB_SAMPLE_COUNT_ADDR 0x00008927
45273815 #define A6XX_RB_SAMPLE_COUNT_ADDR__MASK 0xffffffff
45283816 #define A6XX_RB_SAMPLE_COUNT_ADDR__SHIFT 0
@@ -4608,13 +3896,19 @@ static inline uint32_t A6XX_RB_2D_DST_INFO_SAMPLES(enum a3xx_msaa_samples val) · 79 unmodified lines
46083896 return ((val) << A6XX_RB_2D_DST_INFO_SAMPLES__SHIFT) & A6XX_RB_2D_DST_INFO_SAMPLES__MASK;
46093897 }
46103898 #define A6XX_RB_2D_DST_INFO_FILTER 0x00010000
3899+#define A6XX_RB_2D_DST_INFO_UNK17 0x00020000
46113900 #define A6XX_RB_2D_DST_INFO_SAMPLES_AVERAGE 0x00040000
3901+#define A6XX_RB_2D_DST_INFO_UNK19 0x00080000
46123902 #define A6XX_RB_2D_DST_INFO_UNK20 0x00100000
3903+#define A6XX_RB_2D_DST_INFO_UNK21 0x00200000
46133904 #define A6XX_RB_2D_DST_INFO_UNK22 0x00400000
4614−
4615−#define REG_A6XX_RB_2D_DST_LO 0x00008c18
4616−
4617−#define REG_A6XX_RB_2D_DST_HI 0x00008c19
3905+#define A6XX_RB_2D_DST_INFO_UNK23__MASK 0x07800000
3906+#define A6XX_RB_2D_DST_INFO_UNK23__SHIFT 23
3907+static inline uint32_t A6XX_RB_2D_DST_INFO_UNK23(uint32_t val)
3908+{
3909+ return ((val) << A6XX_RB_2D_DST_INFO_UNK23__SHIFT) & A6XX_RB_2D_DST_INFO_UNK23__MASK;
3910+}
3911+#define A6XX_RB_2D_DST_INFO_UNK28 0x10000000
46183912
46193913 #define REG_A6XX_RB_2D_DST 0x00008c18
46203914 #define A6XX_RB_2D_DST__MASK 0xffffffff
@@ -4656,10 +3950,6 @@ static inline uint32_t A6XX_RB_2D_DST_PLANE2(uint32_t val) · 35 unmodified lines
46563950 return ((val) << A6XX_RB_2D_DST_PLANE2__SHIFT) & A6XX_RB_2D_DST_PLANE2__MASK;
46573951 }
46583952
4659−#define REG_A6XX_RB_2D_DST_FLAGS_LO 0x00008c20
4660−
4661−#define REG_A6XX_RB_2D_DST_FLAGS_HI 0x00008c21
4662−
46633953 #define REG_A6XX_RB_2D_DST_FLAGS 0x00008c20
46643954 #define A6XX_RB_2D_DST_FLAGS__MASK 0xffffffff
46653955 #define A6XX_RB_2D_DST_FLAGS__SHIFT 0
@@ -4740,41 +4030,13 @@ static inline uint32_t A6XX_RB_NC_MODE_CNTL_UNK12(uint32_t val) · 74 unmodified lines
47404030 return ((val) << A6XX_RB_NC_MODE_CNTL_UNK12__SHIFT) & A6XX_RB_NC_MODE_CNTL_UNK12__MASK;
47414031 }
47424032
4743−#define REG_A6XX_RB_PERFCTR_RB_SEL_0 0x00008e10
4744−
4745−#define REG_A6XX_RB_PERFCTR_RB_SEL_1 0x00008e11
4746−
4747−#define REG_A6XX_RB_PERFCTR_RB_SEL_2 0x00008e12
4748−
4749−#define REG_A6XX_RB_PERFCTR_RB_SEL_3 0x00008e13
4750−
4751−#define REG_A6XX_RB_PERFCTR_RB_SEL_4 0x00008e14
4752−
4753−#define REG_A6XX_RB_PERFCTR_RB_SEL_5 0x00008e15
4754−
4755−#define REG_A6XX_RB_PERFCTR_RB_SEL_6 0x00008e16
4756−
4757−#define REG_A6XX_RB_PERFCTR_RB_SEL_7 0x00008e17
4758−
4759−#define REG_A6XX_RB_PERFCTR_CCU_SEL_0 0x00008e18
4033+static inline uint32_t REG_A6XX_RB_PERFCTR_RB_SEL(uint32_t i0) { return 0x00008e10 + 0x1*i0; }
47604034
4761−#define REG_A6XX_RB_PERFCTR_CCU_SEL_1 0x00008e19
4762−
4763−#define REG_A6XX_RB_PERFCTR_CCU_SEL_2 0x00008e1a
4764−
4765−#define REG_A6XX_RB_PERFCTR_CCU_SEL_3 0x00008e1b
4766−
4767−#define REG_A6XX_RB_PERFCTR_CCU_SEL_4 0x00008e1c
4035+static inline uint32_t REG_A6XX_RB_PERFCTR_CCU_SEL(uint32_t i0) { return 0x00008e18 + 0x1*i0; }
47684036
47694037 #define REG_A6XX_RB_UNKNOWN_8E28 0x00008e28
47704038
4771−#define REG_A6XX_RB_PERFCTR_CMP_SEL_0 0x00008e2c
4772−
4773−#define REG_A6XX_RB_PERFCTR_CMP_SEL_1 0x00008e2d
4774−
4775−#define REG_A6XX_RB_PERFCTR_CMP_SEL_2 0x00008e2e
4776−
4777−#define REG_A6XX_RB_PERFCTR_CMP_SEL_3 0x00008e2f
4039+static inline uint32_t REG_A6XX_RB_PERFCTR_CMP_SEL(uint32_t i0) { return 0x00008e2c + 0x1*i0; }
47784040
47794041 #define REG_A6XX_RB_RB_SUB_BLOCK_SEL_CNTL_HOST 0x00008e3b
47804042
@@ -4895,6 +4157,8 @@ static inline uint32_t A6XX_VPC_DS_LAYER_CNTL_VIEWLOC(uint32_t val) · 114 unmodified lines
48954157 }
48964158
48974159 #define REG_A6XX_VPC_UNKNOWN_9107 0x00009107
4160+#define A6XX_VPC_UNKNOWN_9107_RASTER_DISCARD 0x00000001
4161+#define A6XX_VPC_UNKNOWN_9107_UNK2 0x00000004
48984162
48994163 #define REG_A6XX_VPC_POLYGON_MODE 0x00009108
49004164 #define A6XX_VPC_POLYGON_MODE_MODE__MASK 0x00000003
@@ -4921,13 +4185,13 @@ static inline uint32_t REG_A6XX_VPC_VAR(uint32_t i0) { return 0x00009212 + 0x1*i · 20 unmodified lines
49214185 static inline uint32_t REG_A6XX_VPC_VAR_DISABLE(uint32_t i0) { return 0x00009212 + 0x1*i0; }
49224186
49234187 #define REG_A6XX_VPC_SO_CNTL 0x00009216
4924−#define A6XX_VPC_SO_CNTL_UNK0__MASK 0x000000ff
4925−#define A6XX_VPC_SO_CNTL_UNK0__SHIFT 0
4926−static inline uint32_t A6XX_VPC_SO_CNTL_UNK0(uint32_t val)
4188+#define A6XX_VPC_SO_CNTL_ADDR__MASK 0x000000ff
4189+#define A6XX_VPC_SO_CNTL_ADDR__SHIFT 0
4190+static inline uint32_t A6XX_VPC_SO_CNTL_ADDR(uint32_t val)
49274191 {
4928− return ((val) << A6XX_VPC_SO_CNTL_UNK0__SHIFT) & A6XX_VPC_SO_CNTL_UNK0__MASK;
4192+ return ((val) << A6XX_VPC_SO_CNTL_ADDR__SHIFT) & A6XX_VPC_SO_CNTL_ADDR__MASK;
49294193 }
4930−#define A6XX_VPC_SO_CNTL_ENABLE 0x00010000
4194+#define A6XX_VPC_SO_CNTL_RESET 0x00010000
49314195
49324196 #define REG_A6XX_VPC_SO_PROG 0x00009217
49334197 #define A6XX_VPC_SO_PROG_A_BUF__MASK 0x00000003
@@ -4957,10 +4221,6 @@ static inline uint32_t A6XX_VPC_SO_PROG_B_OFF(uint32_t val) · 23 unmodified lines
49574221 }
49584222 #define A6XX_VPC_SO_PROG_B_EN 0x00800000
49594223
4960−#define REG_A6XX_VPC_SO_STREAM_COUNTS_LO 0x00009218
4961−
4962−#define REG_A6XX_VPC_SO_STREAM_COUNTS_HI 0x00009219
4963−
49644224 #define REG_A6XX_VPC_SO_STREAM_COUNTS 0x00009218
49654225 #define A6XX_VPC_SO_STREAM_COUNTS__MASK 0xffffffff
49664226 #define A6XX_VPC_SO_STREAM_COUNTS__SHIFT 0
@@ -4979,10 +4239,6 @@ static inline uint32_t A6XX_VPC_SO_BUFFER_BASE(uint32_t val) · 12 unmodified lines
49794239 return ((val) << A6XX_VPC_SO_BUFFER_BASE__SHIFT) & A6XX_VPC_SO_BUFFER_BASE__MASK;
49804240 }
49814241
4982−static inline uint32_t REG_A6XX_VPC_SO_BUFFER_BASE_LO(uint32_t i0) { return 0x0000921a + 0x7*i0; }
4983−
4984−static inline uint32_t REG_A6XX_VPC_SO_BUFFER_BASE_HI(uint32_t i0) { return 0x0000921b + 0x7*i0; }
4985−
49864242 static inline uint32_t REG_A6XX_VPC_SO_BUFFER_SIZE(uint32_t i0) { return 0x0000921c + 0x7*i0; }
49874243 #define A6XX_VPC_SO_BUFFER_SIZE__MASK 0xfffffffc
49884244 #define A6XX_VPC_SO_BUFFER_SIZE__SHIFT 2
@@ -5009,10 +4265,6 @@ static inline uint32_t A6XX_VPC_SO_FLUSH_BASE(uint32_t val) · 20 unmodified lines
50094265 return ((val) << A6XX_VPC_SO_FLUSH_BASE__SHIFT) & A6XX_VPC_SO_FLUSH_BASE__MASK;
50104266 }
50114267
5012−static inline uint32_t REG_A6XX_VPC_SO_FLUSH_BASE_LO(uint32_t i0) { return 0x0000921f + 0x7*i0; }
5013−
5014−static inline uint32_t REG_A6XX_VPC_SO_FLUSH_BASE_HI(uint32_t i0) { return 0x00009220 + 0x7*i0; }
5015−
50164268 #define REG_A6XX_VPC_POINT_COORD_INVERT 0x00009236
50174269 #define A6XX_VPC_POINT_COORD_INVERT_INVERT 0x00000001
50184270
@@ -5037,11 +4289,11 @@ static inline uint32_t A6XX_VPC_VS_PACK_PSIZELOC(uint32_t val) · 18 unmodified lines
50374289 {
50384290 return ((val) << A6XX_VPC_VS_PACK_PSIZELOC__SHIFT) & A6XX_VPC_VS_PACK_PSIZELOC__MASK;
50394291 }
5040−#define A6XX_VPC_VS_PACK_UNK24__MASK 0x0f000000
5041−#define A6XX_VPC_VS_PACK_UNK24__SHIFT 24
5042−static inline uint32_t A6XX_VPC_VS_PACK_UNK24(uint32_t val)
4292+#define A6XX_VPC_VS_PACK_EXTRAPOS__MASK 0x0f000000
4293+#define A6XX_VPC_VS_PACK_EXTRAPOS__SHIFT 24
4294+static inline uint32_t A6XX_VPC_VS_PACK_EXTRAPOS(uint32_t val)
50434295 {
5044− return ((val) << A6XX_VPC_VS_PACK_UNK24__SHIFT) & A6XX_VPC_VS_PACK_UNK24__MASK;
4296+ return ((val) << A6XX_VPC_VS_PACK_EXTRAPOS__SHIFT) & A6XX_VPC_VS_PACK_EXTRAPOS__MASK;
50454297 }
50464298
50474299 #define REG_A6XX_VPC_GS_PACK 0x00009302
@@ -5063,11 +4315,11 @@ static inline uint32_t A6XX_VPC_GS_PACK_PSIZELOC(uint32_t val) · 15 unmodified lines
50634315 {
50644316 return ((val) << A6XX_VPC_GS_PACK_PSIZELOC__SHIFT) & A6XX_VPC_GS_PACK_PSIZELOC__MASK;
50654317 }
5066−#define A6XX_VPC_GS_PACK_UNK24__MASK 0x0f000000
5067−#define A6XX_VPC_GS_PACK_UNK24__SHIFT 24
5068−static inline uint32_t A6XX_VPC_GS_PACK_UNK24(uint32_t val)
4318+#define A6XX_VPC_GS_PACK_EXTRAPOS__MASK 0x0f000000
4319+#define A6XX_VPC_GS_PACK_EXTRAPOS__SHIFT 24
4320+static inline uint32_t A6XX_VPC_GS_PACK_EXTRAPOS(uint32_t val)
50694321 {
5070− return ((val) << A6XX_VPC_GS_PACK_UNK24__SHIFT) & A6XX_VPC_GS_PACK_UNK24__MASK;
4322+ return ((val) << A6XX_VPC_GS_PACK_EXTRAPOS__SHIFT) & A6XX_VPC_GS_PACK_EXTRAPOS__MASK;
50714323 }
50724324
50734325 #define REG_A6XX_VPC_DS_PACK 0x00009303
@@ -5089,11 +4341,11 @@ static inline uint32_t A6XX_VPC_DS_PACK_PSIZELOC(uint32_t val) · 15 unmodified lines
50894341 {
50904342 return ((val) << A6XX_VPC_DS_PACK_PSIZELOC__SHIFT) & A6XX_VPC_DS_PACK_PSIZELOC__MASK;
50914343 }
5092−#define A6XX_VPC_DS_PACK_UNK24__MASK 0x0f000000
5093−#define A6XX_VPC_DS_PACK_UNK24__SHIFT 24
5094−static inline uint32_t A6XX_VPC_DS_PACK_UNK24(uint32_t val)
4344+#define A6XX_VPC_DS_PACK_EXTRAPOS__MASK 0x0f000000
4345+#define A6XX_VPC_DS_PACK_EXTRAPOS__SHIFT 24
4346+static inline uint32_t A6XX_VPC_DS_PACK_EXTRAPOS(uint32_t val)
50954347 {
5096− return ((val) << A6XX_VPC_DS_PACK_UNK24__SHIFT) & A6XX_VPC_DS_PACK_UNK24__MASK;
4348+ return ((val) << A6XX_VPC_DS_PACK_EXTRAPOS__SHIFT) & A6XX_VPC_DS_PACK_EXTRAPOS__MASK;
50974349 }
50984350
50994351 #define REG_A6XX_VPC_CNTL_0 0x00009304
@@ -5110,24 +4362,43 @@ static inline uint32_t A6XX_VPC_CNTL_0_PRIMIDLOC(uint32_t val) · 10 unmodified lines
51104362 return ((val) << A6XX_VPC_CNTL_0_PRIMIDLOC__SHIFT) & A6XX_VPC_CNTL_0_PRIMIDLOC__MASK;
51114363 }
51124364 #define A6XX_VPC_CNTL_0_VARYING 0x00010000
5113−#define A6XX_VPC_CNTL_0_UNKLOC__MASK 0xff000000
5114−#define A6XX_VPC_CNTL_0_UNKLOC__SHIFT 24
5115−static inline uint32_t A6XX_VPC_CNTL_0_UNKLOC(uint32_t val)
4365+#define A6XX_VPC_CNTL_0_VIEWIDLOC__MASK 0xff000000
4366+#define A6XX_VPC_CNTL_0_VIEWIDLOC__SHIFT 24
4367+static inline uint32_t A6XX_VPC_CNTL_0_VIEWIDLOC(uint32_t val)
51164368 {
5117− return ((val) << A6XX_VPC_CNTL_0_UNKLOC__SHIFT) & A6XX_VPC_CNTL_0_UNKLOC__MASK;
4369+ return ((val) << A6XX_VPC_CNTL_0_VIEWIDLOC__SHIFT) & A6XX_VPC_CNTL_0_VIEWIDLOC__MASK;
51184370 }
51194371
5120−#define REG_A6XX_VPC_SO_BUF_CNTL 0x00009305
5121−#define A6XX_VPC_SO_BUF_CNTL_BUF0 0x00000001
5122−#define A6XX_VPC_SO_BUF_CNTL_BUF1 0x00000008
5123−#define A6XX_VPC_SO_BUF_CNTL_BUF2 0x00000040
5124−#define A6XX_VPC_SO_BUF_CNTL_BUF3 0x00000200
5125−#define A6XX_VPC_SO_BUF_CNTL_ENABLE 0x00008000
5126−#define A6XX_VPC_SO_BUF_CNTL_UNK16__MASK 0x000f0000
5127−#define A6XX_VPC_SO_BUF_CNTL_UNK16__SHIFT 16
5128−static inline uint32_t A6XX_VPC_SO_BUF_CNTL_UNK16(uint32_t val)
4372+#define REG_A6XX_VPC_SO_STREAM_CNTL 0x00009305
4373+#define A6XX_VPC_SO_STREAM_CNTL_BUF0_STREAM__MASK 0x00000007
4374+#define A6XX_VPC_SO_STREAM_CNTL_BUF0_STREAM__SHIFT 0
4375+static inline uint32_t A6XX_VPC_SO_STREAM_CNTL_BUF0_STREAM(uint32_t val)
4376+{
4377+ return ((val) << A6XX_VPC_SO_STREAM_CNTL_BUF0_STREAM__SHIFT) & A6XX_VPC_SO_STREAM_CNTL_BUF0_STREAM__MASK;
4378+}
4379+#define A6XX_VPC_SO_STREAM_CNTL_BUF1_STREAM__MASK 0x00000038
4380+#define A6XX_VPC_SO_STREAM_CNTL_BUF1_STREAM__SHIFT 3
4381+static inline uint32_t A6XX_VPC_SO_STREAM_CNTL_BUF1_STREAM(uint32_t val)
4382+{
4383+ return ((val) << A6XX_VPC_SO_STREAM_CNTL_BUF1_STREAM__SHIFT) & A6XX_VPC_SO_STREAM_CNTL_BUF1_STREAM__MASK;
4384+}
4385+#define A6XX_VPC_SO_STREAM_CNTL_BUF2_STREAM__MASK 0x000001c0
4386+#define A6XX_VPC_SO_STREAM_CNTL_BUF2_STREAM__SHIFT 6
4387+static inline uint32_t A6XX_VPC_SO_STREAM_CNTL_BUF2_STREAM(uint32_t val)
51294388 {
5130− return ((val) << A6XX_VPC_SO_BUF_CNTL_UNK16__SHIFT) & A6XX_VPC_SO_BUF_CNTL_UNK16__MASK;
4389+ return ((val) << A6XX_VPC_SO_STREAM_CNTL_BUF2_STREAM__SHIFT) & A6XX_VPC_SO_STREAM_CNTL_BUF2_STREAM__MASK;
4390+}
4391+#define A6XX_VPC_SO_STREAM_CNTL_BUF3_STREAM__MASK 0x00000e00
4392+#define A6XX_VPC_SO_STREAM_CNTL_BUF3_STREAM__SHIFT 9
4393+static inline uint32_t A6XX_VPC_SO_STREAM_CNTL_BUF3_STREAM(uint32_t val)
4394+{
4395+ return ((val) << A6XX_VPC_SO_STREAM_CNTL_BUF3_STREAM__SHIFT) & A6XX_VPC_SO_STREAM_CNTL_BUF3_STREAM__MASK;
4396+}
4397+#define A6XX_VPC_SO_STREAM_CNTL_STREAM_ENABLE__MASK 0x00078000
4398+#define A6XX_VPC_SO_STREAM_CNTL_STREAM_ENABLE__SHIFT 15
4399+static inline uint32_t A6XX_VPC_SO_STREAM_CNTL_STREAM_ENABLE(uint32_t val)
4400+{
4401+ return ((val) << A6XX_VPC_SO_STREAM_CNTL_STREAM_ENABLE__SHIFT) & A6XX_VPC_SO_STREAM_CNTL_STREAM_ENABLE__MASK;
51314402 }
51324403
51334404 #define REG_A6XX_VPC_SO_DISABLE 0x00009306
@@ -5141,32 +4412,22 @@ static inline uint32_t A6XX_VPC_SO_BUF_CNTL_UNK16(uint32_t val) · 7 unmodified lines
51414412
51424413 #define REG_A6XX_VPC_UNKNOWN_9603 0x00009603
51434414
5144−#define REG_A6XX_VPC_PERFCTR_VPC_SEL_0 0x00009604
5145−
5146−#define REG_A6XX_VPC_PERFCTR_VPC_SEL_1 0x00009605
5147−
5148−#define REG_A6XX_VPC_PERFCTR_VPC_SEL_2 0x00009606
5149−
5150−#define REG_A6XX_VPC_PERFCTR_VPC_SEL_3 0x00009607
5151−
5152−#define REG_A6XX_VPC_PERFCTR_VPC_SEL_4 0x00009608
5153−
5154−#define REG_A6XX_VPC_PERFCTR_VPC_SEL_5 0x00009609
4415+static inline uint32_t REG_A6XX_VPC_PERFCTR_VPC_SEL(uint32_t i0) { return 0x00009604 + 0x1*i0; }
51554416
51564417 #define REG_A6XX_PC_TESS_NUM_VERTEX 0x00009800
51574418
5158−#define REG_A6XX_PC_UNKNOWN_9801 0x00009801
5159−#define A6XX_PC_UNKNOWN_9801_UNK0__MASK 0x000007ff
5160−#define A6XX_PC_UNKNOWN_9801_UNK0__SHIFT 0
5161−static inline uint32_t A6XX_PC_UNKNOWN_9801_UNK0(uint32_t val)
4419+#define REG_A6XX_PC_HS_INPUT_SIZE 0x00009801
4420+#define A6XX_PC_HS_INPUT_SIZE_SIZE__MASK 0x000007ff
4421+#define A6XX_PC_HS_INPUT_SIZE_SIZE__SHIFT 0
4422+static inline uint32_t A6XX_PC_HS_INPUT_SIZE_SIZE(uint32_t val)
51624423 {
5163− return ((val) << A6XX_PC_UNKNOWN_9801_UNK0__SHIFT) & A6XX_PC_UNKNOWN_9801_UNK0__MASK;
4424+ return ((val) << A6XX_PC_HS_INPUT_SIZE_SIZE__SHIFT) & A6XX_PC_HS_INPUT_SIZE_SIZE__MASK;
51644425 }
5165−#define A6XX_PC_UNKNOWN_9801_UNK13__MASK 0x00002000
5166−#define A6XX_PC_UNKNOWN_9801_UNK13__SHIFT 13
5167−static inline uint32_t A6XX_PC_UNKNOWN_9801_UNK13(uint32_t val)
4426+#define A6XX_PC_HS_INPUT_SIZE_UNK13__MASK 0x00002000
4427+#define A6XX_PC_HS_INPUT_SIZE_UNK13__SHIFT 13
4428+static inline uint32_t A6XX_PC_HS_INPUT_SIZE_UNK13(uint32_t val)
51684429 {
5169− return ((val) << A6XX_PC_UNKNOWN_9801_UNK13__SHIFT) & A6XX_PC_UNKNOWN_9801_UNK13__MASK;
4430+ return ((val) << A6XX_PC_HS_INPUT_SIZE_UNK13__SHIFT) & A6XX_PC_HS_INPUT_SIZE_UNK13__MASK;
51704431 }
51714432
51724433 #define REG_A6XX_PC_TESS_CNTL 0x00009802
@@ -5221,6 +4482,8 @@ static inline uint32_t A6XX_PC_EVENT_CMD_EVENT(enum vgt_event_type val) · 48 unmodified lines
52214482 return ((val) << A6XX_PC_EVENT_CMD_EVENT__SHIFT) & A6XX_PC_EVENT_CMD_EVENT__MASK;
52224483 }
52234484
4485+#define REG_A6XX_PC_MARKER 0x00009880
4486+
52244487 #define REG_A6XX_PC_POLYGON_MODE 0x00009981
52254488 #define A6XX_PC_POLYGON_MODE_MODE__MASK 0x00000003
52264489 #define A6XX_PC_POLYGON_MODE_MODE__SHIFT 0
@@ -5229,7 +4492,14 @@ static inline uint32_t A6XX_PC_POLYGON_MODE_MODE(enum a6xx_polygon_mode val) · 2 unmodified lines
52294492 return ((val) << A6XX_PC_POLYGON_MODE_MODE__SHIFT) & A6XX_PC_POLYGON_MODE_MODE__MASK;
52304493 }
52314494
5232−#define REG_A6XX_PC_UNKNOWN_9980 0x00009980
4495+#define REG_A6XX_PC_RASTER_CNTL 0x00009980
4496+#define A6XX_PC_RASTER_CNTL_STREAM__MASK 0x00000003
4497+#define A6XX_PC_RASTER_CNTL_STREAM__SHIFT 0
4498+static inline uint32_t A6XX_PC_RASTER_CNTL_STREAM(uint32_t val)
4499+{
4500+ return ((val) << A6XX_PC_RASTER_CNTL_STREAM__SHIFT) & A6XX_PC_RASTER_CNTL_STREAM__MASK;
4501+}
4502+#define A6XX_PC_RASTER_CNTL_DISCARD 0x00000004
52334503
52344504 #define REG_A6XX_PC_PRIMITIVE_CNTL_0 0x00009b00
52354505 #define A6XX_PC_PRIMITIVE_CNTL_0_PRIMITIVE_RESTART 0x00000001
@@ -5327,9 +4597,17 @@ static inline uint32_t A6XX_PC_PRIMITIVE_CNTL_6_STRIDE_IN_VPC(uint32_t val) · 91 unmodified lines
53274597 return ((val) << A6XX_PC_PRIMITIVE_CNTL_6_STRIDE_IN_VPC__SHIFT) & A6XX_PC_PRIMITIVE_CNTL_6_STRIDE_IN_VPC__MASK;
53284598 }
53294599
5330−#define REG_A6XX_PC_UNKNOWN_9B07 0x00009b07
4600+#define REG_A6XX_PC_MULTIVIEW_CNTL 0x00009b07
4601+#define A6XX_PC_MULTIVIEW_CNTL_ENABLE 0x00000001
4602+#define A6XX_PC_MULTIVIEW_CNTL_DISABLEMULTIPOS 0x00000002
4603+#define A6XX_PC_MULTIVIEW_CNTL_VIEWS__MASK 0x0000007c
4604+#define A6XX_PC_MULTIVIEW_CNTL_VIEWS__SHIFT 2
4605+static inline uint32_t A6XX_PC_MULTIVIEW_CNTL_VIEWS(uint32_t val)
4606+{
4607+ return ((val) << A6XX_PC_MULTIVIEW_CNTL_VIEWS__SHIFT) & A6XX_PC_MULTIVIEW_CNTL_VIEWS__MASK;
4608+}
53314609
5332−#define REG_A6XX_PC_UNKNOWN_9B08 0x00009b08
4610+#define REG_A6XX_PC_MULTIVIEW_MASK 0x00009b08
53334611
53344612 #define REG_A6XX_PC_2D_EVENT_CMD 0x00009c00
53354613 #define A6XX_PC_2D_EVENT_CMD_EVENT__MASK 0x0000007f
@@ -5349,9 +4627,11 @@ static inline uint32_t A6XX_PC_2D_EVENT_CMD_STATE_ID(uint32_t val) · 13 unmodified lines
53494627
53504628 #define REG_A6XX_PC_ADDR_MODE_CNTL 0x00009e01
53514629
5352−#define REG_A6XX_PC_TESSFACTOR_ADDR_LO 0x00009e08
4630+#define REG_A6XX_PC_DRAW_INDX_BASE 0x00009e04
53534631
5354−#define REG_A6XX_PC_TESSFACTOR_ADDR_HI 0x00009e09
4632+#define REG_A6XX_PC_DRAW_FIRST_INDX 0x00009e06
4633+
4634+#define REG_A6XX_PC_DRAW_MAX_INDICES 0x00009e07
53554635
53564636 #define REG_A6XX_PC_TESSFACTOR_ADDR 0x00009e08
53574637 #define A6XX_PC_TESSFACTOR_ADDR__MASK 0xffffffff
@@ -5361,6 +4641,44 @@ static inline uint32_t A6XX_PC_TESSFACTOR_ADDR(uint32_t val) · 3 unmodified lines
53614641 return ((val) << A6XX_PC_TESSFACTOR_ADDR__SHIFT) & A6XX_PC_TESSFACTOR_ADDR__MASK;
53624642 }
53634643
4644+#define REG_A6XX_PC_DRAW_INITIATOR 0x00009e0b
4645+#define A6XX_PC_DRAW_INITIATOR_PRIM_TYPE__MASK 0x0000003f
4646+#define A6XX_PC_DRAW_INITIATOR_PRIM_TYPE__SHIFT 0
4647+static inline uint32_t A6XX_PC_DRAW_INITIATOR_PRIM_TYPE(enum pc_di_primtype val)
4648+{
4649+ return ((val) << A6XX_PC_DRAW_INITIATOR_PRIM_TYPE__SHIFT) & A6XX_PC_DRAW_INITIATOR_PRIM_TYPE__MASK;
4650+}
4651+#define A6XX_PC_DRAW_INITIATOR_SOURCE_SELECT__MASK 0x000000c0
4652+#define A6XX_PC_DRAW_INITIATOR_SOURCE_SELECT__SHIFT 6
4653+static inline uint32_t A6XX_PC_DRAW_INITIATOR_SOURCE_SELECT(enum pc_di_src_sel val)
4654+{
4655+ return ((val) << A6XX_PC_DRAW_INITIATOR_SOURCE_SELECT__SHIFT) & A6XX_PC_DRAW_INITIATOR_SOURCE_SELECT__MASK;
4656+}
4657+#define A6XX_PC_DRAW_INITIATOR_VIS_CULL__MASK 0x00000300
4658+#define A6XX_PC_DRAW_INITIATOR_VIS_CULL__SHIFT 8
4659+static inline uint32_t A6XX_PC_DRAW_INITIATOR_VIS_CULL(enum pc_di_vis_cull_mode val)
4660+{
4661+ return ((val) << A6XX_PC_DRAW_INITIATOR_VIS_CULL__SHIFT) & A6XX_PC_DRAW_INITIATOR_VIS_CULL__MASK;
4662+}
4663+#define A6XX_PC_DRAW_INITIATOR_INDEX_SIZE__MASK 0x00000c00
4664+#define A6XX_PC_DRAW_INITIATOR_INDEX_SIZE__SHIFT 10
4665+static inline uint32_t A6XX_PC_DRAW_INITIATOR_INDEX_SIZE(enum a4xx_index_size val)
4666+{
4667+ return ((val) << A6XX_PC_DRAW_INITIATOR_INDEX_SIZE__SHIFT) & A6XX_PC_DRAW_INITIATOR_INDEX_SIZE__MASK;
4668+}
4669+#define A6XX_PC_DRAW_INITIATOR_PATCH_TYPE__MASK 0x00003000
4670+#define A6XX_PC_DRAW_INITIATOR_PATCH_TYPE__SHIFT 12
4671+static inline uint32_t A6XX_PC_DRAW_INITIATOR_PATCH_TYPE(enum a6xx_patch_type val)
4672+{
4673+ return ((val) << A6XX_PC_DRAW_INITIATOR_PATCH_TYPE__SHIFT) & A6XX_PC_DRAW_INITIATOR_PATCH_TYPE__MASK;
4674+}
4675+#define A6XX_PC_DRAW_INITIATOR_GS_ENABLE 0x00010000
4676+#define A6XX_PC_DRAW_INITIATOR_TESS_ENABLE 0x00020000
4677+
4678+#define REG_A6XX_PC_DRAW_NUM_INSTANCES 0x00009e0c
4679+
4680+#define REG_A6XX_PC_DRAW_NUM_INDICES 0x00009e0d
4681+
53644682 #define REG_A6XX_PC_VSTREAM_CONTROL 0x00009e11
53654683 #define A6XX_PC_VSTREAM_CONTROL_UNK0__MASK 0x0000ffff
53664684 #define A6XX_PC_VSTREAM_CONTROL_UNK0__SHIFT 0
@@ -5397,21 +4715,10 @@ static inline uint32_t A6XX_PC_BIN_DRAW_STRM(uint32_t val) · 30 unmodified lines
53974715 return ((val) << A6XX_PC_BIN_DRAW_STRM__SHIFT) & A6XX_PC_BIN_DRAW_STRM__MASK;
53984716 }
53994717
5400−#define REG_A6XX_PC_PERFCTR_PC_SEL_0 0x00009e34
5401−
5402−#define REG_A6XX_PC_PERFCTR_PC_SEL_1 0x00009e35
5403−
5404−#define REG_A6XX_PC_PERFCTR_PC_SEL_2 0x00009e36
5405−
5406−#define REG_A6XX_PC_PERFCTR_PC_SEL_3 0x00009e37
5407−
5408−#define REG_A6XX_PC_PERFCTR_PC_SEL_4 0x00009e38
4718+#define REG_A6XX_PC_VISIBILITY_OVERRIDE 0x00009e1c
4719+#define A6XX_PC_VISIBILITY_OVERRIDE_OVERRIDE 0x00000001
54094720
5410−#define REG_A6XX_PC_PERFCTR_PC_SEL_5 0x00009e39
5411−
5412−#define REG_A6XX_PC_PERFCTR_PC_SEL_6 0x00009e3a
5413−
5414−#define REG_A6XX_PC_PERFCTR_PC_SEL_7 0x00009e3b
4721+static inline uint32_t REG_A6XX_PC_PERFCTR_PC_SEL(uint32_t i0) { return 0x00009e34 + 0x1*i0; }
54154722
54164723 #define REG_A6XX_PC_UNKNOWN_9E72 0x00009e72
54174724
@@ -5448,6 +4755,12 @@ static inline uint32_t A6XX_VFD_CONTROL_1_REGID4PRIMID(uint32_t val) · 30 unmodified lines
54484755 {
54494756 return ((val) << A6XX_VFD_CONTROL_1_REGID4PRIMID__SHIFT) & A6XX_VFD_CONTROL_1_REGID4PRIMID__MASK;
54504757 }
4758+#define A6XX_VFD_CONTROL_1_REGID4VIEWID__MASK 0xff000000
4759+#define A6XX_VFD_CONTROL_1_REGID4VIEWID__SHIFT 24
4760+static inline uint32_t A6XX_VFD_CONTROL_1_REGID4VIEWID(uint32_t val)
4761+{
4762+ return ((val) << A6XX_VFD_CONTROL_1_REGID4VIEWID__SHIFT) & A6XX_VFD_CONTROL_1_REGID4VIEWID__MASK;
4763+}
54514764
54524765 #define REG_A6XX_VFD_CONTROL_2 0x0000a002
54534766 #define A6XX_VFD_CONTROL_2_REGID_HSPATCHID__MASK 0x000000ff
@@ -5464,6 +4777,12 @@ static inline uint32_t A6XX_VFD_CONTROL_2_REGID_INVOCATIONID(uint32_t val) · 10 unmodified lines
54644777 }
54654778
54664779 #define REG_A6XX_VFD_CONTROL_3 0x0000a003
4780+#define A6XX_VFD_CONTROL_3_UNK0__MASK 0x000000ff
4781+#define A6XX_VFD_CONTROL_3_UNK0__SHIFT 0
4782+static inline uint32_t A6XX_VFD_CONTROL_3_UNK0(uint32_t val)
4783+{
4784+ return ((val) << A6XX_VFD_CONTROL_3_UNK0__SHIFT) & A6XX_VFD_CONTROL_3_UNK0__MASK;
4785+}
54674786 #define A6XX_VFD_CONTROL_3_REGID_DSPATCHID__MASK 0x0000ff00
54684787 #define A6XX_VFD_CONTROL_3_REGID_DSPATCHID__SHIFT 8
54694788 static inline uint32_t A6XX_VFD_CONTROL_3_REGID_DSPATCHID(uint32_t val)
@@ -5484,6 +4803,12 @@ static inline uint32_t A6XX_VFD_CONTROL_3_REGID_TESSY(uint32_t val) · 14 unmodified lines
54844803 }
54854804
54864805 #define REG_A6XX_VFD_CONTROL_4 0x0000a004
4806+#define A6XX_VFD_CONTROL_4_UNK0__MASK 0x000000ff
4807+#define A6XX_VFD_CONTROL_4_UNK0__SHIFT 0
4808+static inline uint32_t A6XX_VFD_CONTROL_4_UNK0(uint32_t val)
4809+{
4810+ return ((val) << A6XX_VFD_CONTROL_4_UNK0__SHIFT) & A6XX_VFD_CONTROL_4_UNK0__MASK;
4811+}
54874812
54884813 #define REG_A6XX_VFD_CONTROL_5 0x0000a005
54894814 #define A6XX_VFD_CONTROL_5_REGID_GSHEADER__MASK 0x000000ff
@@ -5492,14 +4817,30 @@ static inline uint32_t A6XX_VFD_CONTROL_5_REGID_GSHEADER(uint32_t val) · 2 unmodified lines
54924817 {
54934818 return ((val) << A6XX_VFD_CONTROL_5_REGID_GSHEADER__SHIFT) & A6XX_VFD_CONTROL_5_REGID_GSHEADER__MASK;
54944819 }
4820+#define A6XX_VFD_CONTROL_5_UNK8__MASK 0x0000ff00
4821+#define A6XX_VFD_CONTROL_5_UNK8__SHIFT 8
4822+static inline uint32_t A6XX_VFD_CONTROL_5_UNK8(uint32_t val)
4823+{
4824+ return ((val) << A6XX_VFD_CONTROL_5_UNK8__SHIFT) & A6XX_VFD_CONTROL_5_UNK8__MASK;
4825+}
54954826
54964827 #define REG_A6XX_VFD_CONTROL_6 0x0000a006
54974828 #define A6XX_VFD_CONTROL_6_PRIMID_PASSTHRU 0x00000001
54984829
54994830 #define REG_A6XX_VFD_MODE_CNTL 0x0000a007
55004831 #define A6XX_VFD_MODE_CNTL_BINNING_PASS 0x00000001
4832+#define A6XX_VFD_MODE_CNTL_UNK1 0x00000002
4833+#define A6XX_VFD_MODE_CNTL_UNK2 0x00000004
55014834
5502−#define REG_A6XX_VFD_UNKNOWN_A008 0x0000a008
4835+#define REG_A6XX_VFD_MULTIVIEW_CNTL 0x0000a008
4836+#define A6XX_VFD_MULTIVIEW_CNTL_ENABLE 0x00000001
4837+#define A6XX_VFD_MULTIVIEW_CNTL_DISABLEMULTIPOS 0x00000002
4838+#define A6XX_VFD_MULTIVIEW_CNTL_VIEWS__MASK 0x0000007c
4839+#define A6XX_VFD_MULTIVIEW_CNTL_VIEWS__SHIFT 2
4840+static inline uint32_t A6XX_VFD_MULTIVIEW_CNTL_VIEWS(uint32_t val)
4841+{
4842+ return ((val) << A6XX_VFD_MULTIVIEW_CNTL_VIEWS__SHIFT) & A6XX_VFD_MULTIVIEW_CNTL_VIEWS__MASK;
4843+}
55034844
55044845 #define REG_A6XX_VFD_ADD_OFFSET 0x0000a009
55054846 #define A6XX_VFD_ADD_OFFSET_VERTEX 0x00000001
@@ -5512,10 +4853,12 @@ static inline uint32_t A6XX_VFD_CONTROL_5_REGID_GSHEADER(uint32_t val) · 6 unmodified lines
55124853 static inline uint32_t REG_A6XX_VFD_FETCH(uint32_t i0) { return 0x0000a010 + 0x4*i0; }
55134854
55144855 static inline uint32_t REG_A6XX_VFD_FETCH_BASE(uint32_t i0) { return 0x0000a010 + 0x4*i0; }
5515−
5516−static inline uint32_t REG_A6XX_VFD_FETCH_BASE_LO(uint32_t i0) { return 0x0000a010 + 0x4*i0; }
5517−
5518−static inline uint32_t REG_A6XX_VFD_FETCH_BASE_HI(uint32_t i0) { return 0x0000a011 + 0x4*i0; }
4856+#define A6XX_VFD_FETCH_BASE__MASK 0xffffffff
4857+#define A6XX_VFD_FETCH_BASE__SHIFT 0
4858+static inline uint32_t A6XX_VFD_FETCH_BASE(uint32_t val)
4859+{
4860+ return ((val) << A6XX_VFD_FETCH_BASE__SHIFT) & A6XX_VFD_FETCH_BASE__MASK;
4861+}
55194862
55204863 static inline uint32_t REG_A6XX_VFD_FETCH_SIZE(uint32_t i0) { return 0x0000a012 + 0x4*i0; }
55214864
@@ -5572,7 +4915,19 @@ static inline uint32_t A6XX_VFD_DEST_CNTL_INSTR_REGID(uint32_t val) · 50 unmodified lines
55724915
55734916 #define REG_A6XX_SP_UNKNOWN_A0F8 0x0000a0f8
55744917
4918+#define REG_A6XX_VFD_ADDR_MODE_CNTL 0x0000a601
4919+
4920+static inline uint32_t REG_A6XX_VFD_PERFCTR_VFD_SEL(uint32_t i0) { return 0x0000a610 + 0x1*i0; }
4921+
55754922 #define REG_A6XX_SP_VS_CTRL_REG0 0x0000a800
4923+#define A6XX_SP_VS_CTRL_REG0_MERGEDREGS 0x00100000
4924+#define A6XX_SP_VS_CTRL_REG0_UNK21 0x00200000
4925+#define A6XX_SP_VS_CTRL_REG0_THREADMODE__MASK 0x00000001
4926+#define A6XX_SP_VS_CTRL_REG0_THREADMODE__SHIFT 0
4927+static inline uint32_t A6XX_SP_VS_CTRL_REG0_THREADMODE(enum a3xx_threadmode val)
4928+{
4929+ return ((val) << A6XX_SP_VS_CTRL_REG0_THREADMODE__SHIFT) & A6XX_SP_VS_CTRL_REG0_THREADMODE__MASK;
4930+}
55764931 #define A6XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__MASK 0x0000007e
55774932 #define A6XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT 1
55784933 static inline uint32_t A6XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val)
@@ -5585,22 +4940,13 @@ static inline uint32_t A6XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val) · 6 unmodified lines
55854940 {
55864941 return ((val) << A6XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT) & A6XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__MASK;
55874942 }
4943+#define A6XX_SP_VS_CTRL_REG0_UNK13 0x00002000
55884944 #define A6XX_SP_VS_CTRL_REG0_BRANCHSTACK__MASK 0x000fc000
55894945 #define A6XX_SP_VS_CTRL_REG0_BRANCHSTACK__SHIFT 14
55904946 static inline uint32_t A6XX_SP_VS_CTRL_REG0_BRANCHSTACK(uint32_t val)
55914947 {
55924948 return ((val) << A6XX_SP_VS_CTRL_REG0_BRANCHSTACK__SHIFT) & A6XX_SP_VS_CTRL_REG0_BRANCHSTACK__MASK;
55934949 }
5594−#define A6XX_SP_VS_CTRL_REG0_THREADSIZE__MASK 0x00100000
5595−#define A6XX_SP_VS_CTRL_REG0_THREADSIZE__SHIFT 20
5596−static inline uint32_t A6XX_SP_VS_CTRL_REG0_THREADSIZE(enum a3xx_threadsize val)
5597−{
5598− return ((val) << A6XX_SP_VS_CTRL_REG0_THREADSIZE__SHIFT) & A6XX_SP_VS_CTRL_REG0_THREADSIZE__MASK;
5599−}
5600−#define A6XX_SP_VS_CTRL_REG0_VARYING 0x00400000
5601−#define A6XX_SP_VS_CTRL_REG0_DIFF_FINE 0x00800000
5602−#define A6XX_SP_VS_CTRL_REG0_PIXLODENABLE 0x04000000
5603−#define A6XX_SP_VS_CTRL_REG0_MERGEDREGS 0x80000000
56044950
56054951 #define REG_A6XX_SP_VS_BRANCH_COND 0x0000a801
56064952
@@ -5611,6 +4957,12 @@ static inline uint32_t A6XX_SP_VS_PRIMITIVE_CNTL_OUT(uint32_t val) · 4 unmodified lines
56114957 {
56124958 return ((val) << A6XX_SP_VS_PRIMITIVE_CNTL_OUT__SHIFT) & A6XX_SP_VS_PRIMITIVE_CNTL_OUT__MASK;
56134959 }
4960+#define A6XX_SP_VS_PRIMITIVE_CNTL_FLAGS_REGID__MASK 0x00003fc0
4961+#define A6XX_SP_VS_PRIMITIVE_CNTL_FLAGS_REGID__SHIFT 6
4962+static inline uint32_t A6XX_SP_VS_PRIMITIVE_CNTL_FLAGS_REGID(uint32_t val)
4963+{
4964+ return ((val) << A6XX_SP_VS_PRIMITIVE_CNTL_FLAGS_REGID__SHIFT) & A6XX_SP_VS_PRIMITIVE_CNTL_FLAGS_REGID__MASK;
4965+}
56144966
56154967 static inline uint32_t REG_A6XX_SP_VS_OUT(uint32_t i0) { return 0x0000a803 + 0x1*i0; }
56164968
@@ -5668,11 +5020,46 @@ static inline uint32_t A6XX_SP_VS_VPC_DST_REG_OUTLOC3(uint32_t val) · 51 unmodified lines
56685020 return ((val) << A6XX_SP_VS_VPC_DST_REG_OUTLOC3__SHIFT) & A6XX_SP_VS_VPC_DST_REG_OUTLOC3__MASK;
56695021 }
56705022
5671−#define REG_A6XX_SP_UNKNOWN_A81B 0x0000a81b
5023+#define REG_A6XX_SP_VS_OBJ_FIRST_EXEC_OFFSET 0x0000a81b
5024+
5025+#define REG_A6XX_SP_VS_OBJ_START 0x0000a81c
5026+#define A6XX_SP_VS_OBJ_START__MASK 0xffffffff
5027+#define A6XX_SP_VS_OBJ_START__SHIFT 0
5028+static inline uint32_t A6XX_SP_VS_OBJ_START(uint32_t val)
5029+{
5030+ return ((val) << A6XX_SP_VS_OBJ_START__SHIFT) & A6XX_SP_VS_OBJ_START__MASK;
5031+}
5032+
5033+#define REG_A6XX_SP_VS_PVT_MEM_PARAM 0x0000a81e
5034+#define A6XX_SP_VS_PVT_MEM_PARAM_MEMSIZEPERITEM__MASK 0x000000ff
5035+#define A6XX_SP_VS_PVT_MEM_PARAM_MEMSIZEPERITEM__SHIFT 0
5036+static inline uint32_t A6XX_SP_VS_PVT_MEM_PARAM_MEMSIZEPERITEM(uint32_t val)
5037+{
5038+ return ((val >> 9) << A6XX_SP_VS_PVT_MEM_PARAM_MEMSIZEPERITEM__SHIFT) & A6XX_SP_VS_PVT_MEM_PARAM_MEMSIZEPERITEM__MASK;
5039+}
5040+#define A6XX_SP_VS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__MASK 0xff000000
5041+#define A6XX_SP_VS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__SHIFT 24
5042+static inline uint32_t A6XX_SP_VS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD(uint32_t val)
5043+{
5044+ return ((val) << A6XX_SP_VS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__SHIFT) & A6XX_SP_VS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__MASK;
5045+}
56725046
5673−#define REG_A6XX_SP_VS_OBJ_START_LO 0x0000a81c
5047+#define REG_A6XX_SP_VS_PVT_MEM_ADDR 0x0000a81f
5048+#define A6XX_SP_VS_PVT_MEM_ADDR__MASK 0xffffffff
5049+#define A6XX_SP_VS_PVT_MEM_ADDR__SHIFT 0
5050+static inline uint32_t A6XX_SP_VS_PVT_MEM_ADDR(uint32_t val)
5051+{
5052+ return ((val) << A6XX_SP_VS_PVT_MEM_ADDR__SHIFT) & A6XX_SP_VS_PVT_MEM_ADDR__MASK;
5053+}
56745054
5675−#define REG_A6XX_SP_VS_OBJ_START_HI 0x0000a81d
5055+#define REG_A6XX_SP_VS_PVT_MEM_SIZE 0x0000a821
5056+#define A6XX_SP_VS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__MASK 0x0003ffff
5057+#define A6XX_SP_VS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__SHIFT 0
5058+static inline uint32_t A6XX_SP_VS_PVT_MEM_SIZE_TOTALPVTMEMSIZE(uint32_t val)
5059+{
5060+ return ((val >> 12) << A6XX_SP_VS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__SHIFT) & A6XX_SP_VS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__MASK;
5061+}
5062+#define A6XX_SP_VS_PVT_MEM_SIZE_PERWAVEMEMLAYOUT 0x80000000
56765063
56775064 #define REG_A6XX_SP_VS_TEX_COUNT 0x0000a822
56785065
@@ -5694,7 +5081,7 @@ static inline uint32_t A6XX_SP_VS_CONFIG_NSAMP(uint32_t val) · 15 unmodified lines
56945081 {
56955082 return ((val) << A6XX_SP_VS_CONFIG_NSAMP__SHIFT) & A6XX_SP_VS_CONFIG_NSAMP__MASK;
56965083 }
5697−#define A6XX_SP_VS_CONFIG_NIBO__MASK 0x3fc00000
5084+#define A6XX_SP_VS_CONFIG_NIBO__MASK 0x1fc00000
56985085 #define A6XX_SP_VS_CONFIG_NIBO__SHIFT 22
56995086 static inline uint32_t A6XX_SP_VS_CONFIG_NIBO(uint32_t val)
57005087 {
@@ -5703,7 +5090,22 @@ static inline uint32_t A6XX_SP_VS_CONFIG_NIBO(uint32_t val) · 2 unmodified lines
57035090
57045091 #define REG_A6XX_SP_VS_INSTRLEN 0x0000a824
57055092
5093+#define REG_A6XX_SP_VS_PVT_MEM_HW_STACK_OFFSET 0x0000a825
5094+#define A6XX_SP_VS_PVT_MEM_HW_STACK_OFFSET__MASK 0x0007ffff
5095+#define A6XX_SP_VS_PVT_MEM_HW_STACK_OFFSET__SHIFT 0
5096+static inline uint32_t A6XX_SP_VS_PVT_MEM_HW_STACK_OFFSET(uint32_t val)
5097+{
5098+ return ((val >> 11) << A6XX_SP_VS_PVT_MEM_HW_STACK_OFFSET__SHIFT) & A6XX_SP_VS_PVT_MEM_HW_STACK_OFFSET__MASK;
5099+}
5100+
57065101 #define REG_A6XX_SP_HS_CTRL_REG0 0x0000a830
5102+#define A6XX_SP_HS_CTRL_REG0_UNK20 0x00100000
5103+#define A6XX_SP_HS_CTRL_REG0_THREADMODE__MASK 0x00000001
5104+#define A6XX_SP_HS_CTRL_REG0_THREADMODE__SHIFT 0
5105+static inline uint32_t A6XX_SP_HS_CTRL_REG0_THREADMODE(enum a3xx_threadmode val)
5106+{
5107+ return ((val) << A6XX_SP_HS_CTRL_REG0_THREADMODE__SHIFT) & A6XX_SP_HS_CTRL_REG0_THREADMODE__MASK;
5108+}
57075109 #define A6XX_SP_HS_CTRL_REG0_HALFREGFOOTPRINT__MASK 0x0000007e
57085110 #define A6XX_SP_HS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT 1
57095111 static inline uint32_t A6XX_SP_HS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val)
@@ -5716,30 +5118,58 @@ static inline uint32_t A6XX_SP_HS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val) · 6 unmodified lines
57165118 {
57175119 return ((val) << A6XX_SP_HS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT) & A6XX_SP_HS_CTRL_REG0_FULLREGFOOTPRINT__MASK;
57185120 }
5121+#define A6XX_SP_HS_CTRL_REG0_UNK13 0x00002000
57195122 #define A6XX_SP_HS_CTRL_REG0_BRANCHSTACK__MASK 0x000fc000
57205123 #define A6XX_SP_HS_CTRL_REG0_BRANCHSTACK__SHIFT 14
57215124 static inline uint32_t A6XX_SP_HS_CTRL_REG0_BRANCHSTACK(uint32_t val)
57225125 {
57235126 return ((val) << A6XX_SP_HS_CTRL_REG0_BRANCHSTACK__SHIFT) & A6XX_SP_HS_CTRL_REG0_BRANCHSTACK__MASK;
57245127 }
5725−#define A6XX_SP_HS_CTRL_REG0_THREADSIZE__MASK 0x00100000
5726−#define A6XX_SP_HS_CTRL_REG0_THREADSIZE__SHIFT 20
5727−static inline uint32_t A6XX_SP_HS_CTRL_REG0_THREADSIZE(enum a3xx_threadsize val)
5128+
5129+#define REG_A6XX_SP_HS_WAVE_INPUT_SIZE 0x0000a831
5130+
5131+#define REG_A6XX_SP_HS_BRANCH_COND 0x0000a832
5132+
5133+#define REG_A6XX_SP_HS_OBJ_FIRST_EXEC_OFFSET 0x0000a833
5134+
5135+#define REG_A6XX_SP_HS_OBJ_START 0x0000a834
5136+#define A6XX_SP_HS_OBJ_START__MASK 0xffffffff
5137+#define A6XX_SP_HS_OBJ_START__SHIFT 0
5138+static inline uint32_t A6XX_SP_HS_OBJ_START(uint32_t val)
57285139 {
5729− return ((val) << A6XX_SP_HS_CTRL_REG0_THREADSIZE__SHIFT) & A6XX_SP_HS_CTRL_REG0_THREADSIZE__MASK;
5140+ return ((val) << A6XX_SP_HS_OBJ_START__SHIFT) & A6XX_SP_HS_OBJ_START__MASK;
57305141 }
5731−#define A6XX_SP_HS_CTRL_REG0_VARYING 0x00400000
5732−#define A6XX_SP_HS_CTRL_REG0_DIFF_FINE 0x00800000
5733−#define A6XX_SP_HS_CTRL_REG0_PIXLODENABLE 0x04000000
5734−#define A6XX_SP_HS_CTRL_REG0_MERGEDREGS 0x80000000
57355142
5736−#define REG_A6XX_SP_HS_UNKNOWN_A831 0x0000a831
5737−
5738−#define REG_A6XX_SP_HS_UNKNOWN_A833 0x0000a833
5143+#define REG_A6XX_SP_HS_PVT_MEM_PARAM 0x0000a836
5144+#define A6XX_SP_HS_PVT_MEM_PARAM_MEMSIZEPERITEM__MASK 0x000000ff
5145+#define A6XX_SP_HS_PVT_MEM_PARAM_MEMSIZEPERITEM__SHIFT 0
5146+static inline uint32_t A6XX_SP_HS_PVT_MEM_PARAM_MEMSIZEPERITEM(uint32_t val)
5147+{
5148+ return ((val >> 9) << A6XX_SP_HS_PVT_MEM_PARAM_MEMSIZEPERITEM__SHIFT) & A6XX_SP_HS_PVT_MEM_PARAM_MEMSIZEPERITEM__MASK;
5149+}
5150+#define A6XX_SP_HS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__MASK 0xff000000
5151+#define A6XX_SP_HS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__SHIFT 24
5152+static inline uint32_t A6XX_SP_HS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD(uint32_t val)
5153+{
5154+ return ((val) << A6XX_SP_HS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__SHIFT) & A6XX_SP_HS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__MASK;
5155+}
57395156
5740−#define REG_A6XX_SP_HS_OBJ_START_LO 0x0000a834
5157+#define REG_A6XX_SP_HS_PVT_MEM_ADDR 0x0000a837
5158+#define A6XX_SP_HS_PVT_MEM_ADDR__MASK 0xffffffff
5159+#define A6XX_SP_HS_PVT_MEM_ADDR__SHIFT 0
5160+static inline uint32_t A6XX_SP_HS_PVT_MEM_ADDR(uint32_t val)
5161+{
5162+ return ((val) << A6XX_SP_HS_PVT_MEM_ADDR__SHIFT) & A6XX_SP_HS_PVT_MEM_ADDR__MASK;
5163+}
57415164
5742−#define REG_A6XX_SP_HS_OBJ_START_HI 0x0000a835
5165+#define REG_A6XX_SP_HS_PVT_MEM_SIZE 0x0000a839
5166+#define A6XX_SP_HS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__MASK 0x0003ffff
5167+#define A6XX_SP_HS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__SHIFT 0
5168+static inline uint32_t A6XX_SP_HS_PVT_MEM_SIZE_TOTALPVTMEMSIZE(uint32_t val)
5169+{
5170+ return ((val >> 12) << A6XX_SP_HS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__SHIFT) & A6XX_SP_HS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__MASK;
5171+}
5172+#define A6XX_SP_HS_PVT_MEM_SIZE_PERWAVEMEMLAYOUT 0x80000000
57435173
57445174 #define REG_A6XX_SP_HS_TEX_COUNT 0x0000a83a
57455175
@@ -5761,7 +5191,7 @@ static inline uint32_t A6XX_SP_HS_CONFIG_NSAMP(uint32_t val) · 15 unmodified lines
57615191 {
57625192 return ((val) << A6XX_SP_HS_CONFIG_NSAMP__SHIFT) & A6XX_SP_HS_CONFIG_NSAMP__MASK;
57635193 }
5764−#define A6XX_SP_HS_CONFIG_NIBO__MASK 0x3fc00000
5194+#define A6XX_SP_HS_CONFIG_NIBO__MASK 0x1fc00000
57655195 #define A6XX_SP_HS_CONFIG_NIBO__SHIFT 22
57665196 static inline uint32_t A6XX_SP_HS_CONFIG_NIBO(uint32_t val)
57675197 {
@@ -5770,7 +5200,22 @@ static inline uint32_t A6XX_SP_HS_CONFIG_NIBO(uint32_t val) · 2 unmodified lines
57705200
57715201 #define REG_A6XX_SP_HS_INSTRLEN 0x0000a83c
57725202
5203+#define REG_A6XX_SP_HS_PVT_MEM_HW_STACK_OFFSET 0x0000a83d
5204+#define A6XX_SP_HS_PVT_MEM_HW_STACK_OFFSET__MASK 0x0007ffff
5205+#define A6XX_SP_HS_PVT_MEM_HW_STACK_OFFSET__SHIFT 0
5206+static inline uint32_t A6XX_SP_HS_PVT_MEM_HW_STACK_OFFSET(uint32_t val)
5207+{
5208+ return ((val >> 11) << A6XX_SP_HS_PVT_MEM_HW_STACK_OFFSET__SHIFT) & A6XX_SP_HS_PVT_MEM_HW_STACK_OFFSET__MASK;
5209+}
5210+
57735211 #define REG_A6XX_SP_DS_CTRL_REG0 0x0000a840
5212+#define A6XX_SP_DS_CTRL_REG0_MERGEDREGS 0x00100000
5213+#define A6XX_SP_DS_CTRL_REG0_THREADMODE__MASK 0x00000001
5214+#define A6XX_SP_DS_CTRL_REG0_THREADMODE__SHIFT 0
5215+static inline uint32_t A6XX_SP_DS_CTRL_REG0_THREADMODE(enum a3xx_threadmode val)
5216+{
5217+ return ((val) << A6XX_SP_DS_CTRL_REG0_THREADMODE__SHIFT) & A6XX_SP_DS_CTRL_REG0_THREADMODE__MASK;
5218+}
57745219 #define A6XX_SP_DS_CTRL_REG0_HALFREGFOOTPRINT__MASK 0x0000007e
57755220 #define A6XX_SP_DS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT 1
57765221 static inline uint32_t A6XX_SP_DS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val)
@@ -5783,22 +5228,15 @@ static inline uint32_t A6XX_SP_DS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val) · 6 unmodified lines
57835228 {
57845229 return ((val) << A6XX_SP_DS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT) & A6XX_SP_DS_CTRL_REG0_FULLREGFOOTPRINT__MASK;
57855230 }
5231+#define A6XX_SP_DS_CTRL_REG0_UNK13 0x00002000
57865232 #define A6XX_SP_DS_CTRL_REG0_BRANCHSTACK__MASK 0x000fc000
57875233 #define A6XX_SP_DS_CTRL_REG0_BRANCHSTACK__SHIFT 14
57885234 static inline uint32_t A6XX_SP_DS_CTRL_REG0_BRANCHSTACK(uint32_t val)
57895235 {
57905236 return ((val) << A6XX_SP_DS_CTRL_REG0_BRANCHSTACK__SHIFT) & A6XX_SP_DS_CTRL_REG0_BRANCHSTACK__MASK;
57915237 }
5792−#define A6XX_SP_DS_CTRL_REG0_THREADSIZE__MASK 0x00100000
5793−#define A6XX_SP_DS_CTRL_REG0_THREADSIZE__SHIFT 20
5794−static inline uint32_t A6XX_SP_DS_CTRL_REG0_THREADSIZE(enum a3xx_threadsize val)
5795−{
5796− return ((val) << A6XX_SP_DS_CTRL_REG0_THREADSIZE__SHIFT) & A6XX_SP_DS_CTRL_REG0_THREADSIZE__MASK;
5797−}
5798−#define A6XX_SP_DS_CTRL_REG0_VARYING 0x00400000
5799−#define A6XX_SP_DS_CTRL_REG0_DIFF_FINE 0x00800000
5800−#define A6XX_SP_DS_CTRL_REG0_PIXLODENABLE 0x04000000
5801−#define A6XX_SP_DS_CTRL_REG0_MERGEDREGS 0x80000000
5238+
5239+#define REG_A6XX_SP_DS_BRANCH_COND 0x0000a841
58025240
58035241 #define REG_A6XX_SP_DS_PRIMITIVE_CNTL 0x0000a842
58045242 #define A6XX_SP_DS_PRIMITIVE_CNTL_OUT__MASK 0x0000003f
@@ -5807,6 +5245,12 @@ static inline uint32_t A6XX_SP_DS_PRIMITIVE_CNTL_OUT(uint32_t val) · 2 unmodified lines
58075245 {
58085246 return ((val) << A6XX_SP_DS_PRIMITIVE_CNTL_OUT__SHIFT) & A6XX_SP_DS_PRIMITIVE_CNTL_OUT__MASK;
58095247 }
5248+#define A6XX_SP_DS_PRIMITIVE_CNTL_FLAGS_REGID__MASK 0x00003fc0
5249+#define A6XX_SP_DS_PRIMITIVE_CNTL_FLAGS_REGID__SHIFT 6
5250+static inline uint32_t A6XX_SP_DS_PRIMITIVE_CNTL_FLAGS_REGID(uint32_t val)
5251+{
5252+ return ((val) << A6XX_SP_DS_PRIMITIVE_CNTL_FLAGS_REGID__SHIFT) & A6XX_SP_DS_PRIMITIVE_CNTL_FLAGS_REGID__MASK;
5253+}
58105254
58115255 static inline uint32_t REG_A6XX_SP_DS_OUT(uint32_t i0) { return 0x0000a843 + 0x1*i0; }
58125256
@@ -5864,11 +5308,46 @@ static inline uint32_t A6XX_SP_DS_VPC_DST_REG_OUTLOC3(uint32_t val) · 51 unmodified lines
58645308 return ((val) << A6XX_SP_DS_VPC_DST_REG_OUTLOC3__SHIFT) & A6XX_SP_DS_VPC_DST_REG_OUTLOC3__MASK;
58655309 }
58665310
5867−#define REG_A6XX_SP_DS_UNKNOWN_A85B 0x0000a85b
5311+#define REG_A6XX_SP_DS_OBJ_FIRST_EXEC_OFFSET 0x0000a85b
5312+
5313+#define REG_A6XX_SP_DS_OBJ_START 0x0000a85c
5314+#define A6XX_SP_DS_OBJ_START__MASK 0xffffffff
5315+#define A6XX_SP_DS_OBJ_START__SHIFT 0
5316+static inline uint32_t A6XX_SP_DS_OBJ_START(uint32_t val)
5317+{
5318+ return ((val) << A6XX_SP_DS_OBJ_START__SHIFT) & A6XX_SP_DS_OBJ_START__MASK;
5319+}
5320+
5321+#define REG_A6XX_SP_DS_PVT_MEM_PARAM 0x0000a85e
5322+#define A6XX_SP_DS_PVT_MEM_PARAM_MEMSIZEPERITEM__MASK 0x000000ff
5323+#define A6XX_SP_DS_PVT_MEM_PARAM_MEMSIZEPERITEM__SHIFT 0
5324+static inline uint32_t A6XX_SP_DS_PVT_MEM_PARAM_MEMSIZEPERITEM(uint32_t val)
5325+{
5326+ return ((val >> 9) << A6XX_SP_DS_PVT_MEM_PARAM_MEMSIZEPERITEM__SHIFT) & A6XX_SP_DS_PVT_MEM_PARAM_MEMSIZEPERITEM__MASK;
5327+}
5328+#define A6XX_SP_DS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__MASK 0xff000000
5329+#define A6XX_SP_DS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__SHIFT 24
5330+static inline uint32_t A6XX_SP_DS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD(uint32_t val)
5331+{
5332+ return ((val) << A6XX_SP_DS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__SHIFT) & A6XX_SP_DS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__MASK;
5333+}
58685334
5869−#define REG_A6XX_SP_DS_OBJ_START_LO 0x0000a85c
5335+#define REG_A6XX_SP_DS_PVT_MEM_ADDR 0x0000a85f
5336+#define A6XX_SP_DS_PVT_MEM_ADDR__MASK 0xffffffff
5337+#define A6XX_SP_DS_PVT_MEM_ADDR__SHIFT 0
5338+static inline uint32_t A6XX_SP_DS_PVT_MEM_ADDR(uint32_t val)
5339+{
5340+ return ((val) << A6XX_SP_DS_PVT_MEM_ADDR__SHIFT) & A6XX_SP_DS_PVT_MEM_ADDR__MASK;
5341+}
58705342
5871−#define REG_A6XX_SP_DS_OBJ_START_HI 0x0000a85d
5343+#define REG_A6XX_SP_DS_PVT_MEM_SIZE 0x0000a861
5344+#define A6XX_SP_DS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__MASK 0x0003ffff
5345+#define A6XX_SP_DS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__SHIFT 0
5346+static inline uint32_t A6XX_SP_DS_PVT_MEM_SIZE_TOTALPVTMEMSIZE(uint32_t val)
5347+{
5348+ return ((val >> 12) << A6XX_SP_DS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__SHIFT) & A6XX_SP_DS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__MASK;
5349+}
5350+#define A6XX_SP_DS_PVT_MEM_SIZE_PERWAVEMEMLAYOUT 0x80000000
58725351
58735352 #define REG_A6XX_SP_DS_TEX_COUNT 0x0000a862
58745353
@@ -5890,7 +5369,7 @@ static inline uint32_t A6XX_SP_DS_CONFIG_NSAMP(uint32_t val) · 15 unmodified lines
58905369 {
58915370 return ((val) << A6XX_SP_DS_CONFIG_NSAMP__SHIFT) & A6XX_SP_DS_CONFIG_NSAMP__MASK;
58925371 }
5893−#define A6XX_SP_DS_CONFIG_NIBO__MASK 0x3fc00000
5372+#define A6XX_SP_DS_CONFIG_NIBO__MASK 0x1fc00000
58945373 #define A6XX_SP_DS_CONFIG_NIBO__SHIFT 22
58955374 static inline uint32_t A6XX_SP_DS_CONFIG_NIBO(uint32_t val)
58965375 {
@@ -5899,7 +5378,22 @@ static inline uint32_t A6XX_SP_DS_CONFIG_NIBO(uint32_t val) · 2 unmodified lines
58995378
59005379 #define REG_A6XX_SP_DS_INSTRLEN 0x0000a864
59015380
5381+#define REG_A6XX_SP_DS_PVT_MEM_HW_STACK_OFFSET 0x0000a865
5382+#define A6XX_SP_DS_PVT_MEM_HW_STACK_OFFSET__MASK 0x0007ffff
5383+#define A6XX_SP_DS_PVT_MEM_HW_STACK_OFFSET__SHIFT 0
5384+static inline uint32_t A6XX_SP_DS_PVT_MEM_HW_STACK_OFFSET(uint32_t val)
5385+{
5386+ return ((val >> 11) << A6XX_SP_DS_PVT_MEM_HW_STACK_OFFSET__SHIFT) & A6XX_SP_DS_PVT_MEM_HW_STACK_OFFSET__MASK;
5387+}
5388+
59025389 #define REG_A6XX_SP_GS_CTRL_REG0 0x0000a870
5390+#define A6XX_SP_GS_CTRL_REG0_UNK20 0x00100000
5391+#define A6XX_SP_GS_CTRL_REG0_THREADMODE__MASK 0x00000001
5392+#define A6XX_SP_GS_CTRL_REG0_THREADMODE__SHIFT 0
5393+static inline uint32_t A6XX_SP_GS_CTRL_REG0_THREADMODE(enum a3xx_threadmode val)
5394+{
5395+ return ((val) << A6XX_SP_GS_CTRL_REG0_THREADMODE__SHIFT) & A6XX_SP_GS_CTRL_REG0_THREADMODE__MASK;
5396+}
59035397 #define A6XX_SP_GS_CTRL_REG0_HALFREGFOOTPRINT__MASK 0x0000007e
59045398 #define A6XX_SP_GS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT 1
59055399 static inline uint32_t A6XX_SP_GS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val)
@@ -5912,22 +5406,13 @@ static inline uint32_t A6XX_SP_GS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val) · 6 unmodified lines
59125406 {
59135407 return ((val) << A6XX_SP_GS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT) & A6XX_SP_GS_CTRL_REG0_FULLREGFOOTPRINT__MASK;
59145408 }
5409+#define A6XX_SP_GS_CTRL_REG0_UNK13 0x00002000
59155410 #define A6XX_SP_GS_CTRL_REG0_BRANCHSTACK__MASK 0x000fc000
59165411 #define A6XX_SP_GS_CTRL_REG0_BRANCHSTACK__SHIFT 14
59175412 static inline uint32_t A6XX_SP_GS_CTRL_REG0_BRANCHSTACK(uint32_t val)
59185413 {
59195414 return ((val) << A6XX_SP_GS_CTRL_REG0_BRANCHSTACK__SHIFT) & A6XX_SP_GS_CTRL_REG0_BRANCHSTACK__MASK;
59205415 }
5921−#define A6XX_SP_GS_CTRL_REG0_THREADSIZE__MASK 0x00100000
5922−#define A6XX_SP_GS_CTRL_REG0_THREADSIZE__SHIFT 20
5923−static inline uint32_t A6XX_SP_GS_CTRL_REG0_THREADSIZE(enum a3xx_threadsize val)
5924−{
5925− return ((val) << A6XX_SP_GS_CTRL_REG0_THREADSIZE__SHIFT) & A6XX_SP_GS_CTRL_REG0_THREADSIZE__MASK;
5926−}
5927−#define A6XX_SP_GS_CTRL_REG0_VARYING 0x00400000
5928−#define A6XX_SP_GS_CTRL_REG0_DIFF_FINE 0x00800000
5929−#define A6XX_SP_GS_CTRL_REG0_PIXLODENABLE 0x04000000
5930−#define A6XX_SP_GS_CTRL_REG0_MERGEDREGS 0x80000000
59315416
59325417 #define REG_A6XX_SP_GS_PRIM_SIZE 0x0000a871
59335418
@@ -6003,9 +5488,46 @@ static inline uint32_t A6XX_SP_GS_VPC_DST_REG_OUTLOC3(uint32_t val) · 69 unmodified lines
60035488 return ((val) << A6XX_SP_GS_VPC_DST_REG_OUTLOC3__SHIFT) & A6XX_SP_GS_VPC_DST_REG_OUTLOC3__MASK;
60045489 }
60055490
6006−#define REG_A6XX_SP_GS_OBJ_START_LO 0x0000a88d
6007−
6008−#define REG_A6XX_SP_GS_OBJ_START_HI 0x0000a88e
5491+#define REG_A6XX_SP_GS_OBJ_FIRST_EXEC_OFFSET 0x0000a88c
5492+
5493+#define REG_A6XX_SP_GS_OBJ_START 0x0000a88d
5494+#define A6XX_SP_GS_OBJ_START__MASK 0xffffffff
5495+#define A6XX_SP_GS_OBJ_START__SHIFT 0
5496+static inline uint32_t A6XX_SP_GS_OBJ_START(uint32_t val)
5497+{
5498+ return ((val) << A6XX_SP_GS_OBJ_START__SHIFT) & A6XX_SP_GS_OBJ_START__MASK;
5499+}
5500+
5501+#define REG_A6XX_SP_GS_PVT_MEM_PARAM 0x0000a88f
5502+#define A6XX_SP_GS_PVT_MEM_PARAM_MEMSIZEPERITEM__MASK 0x000000ff
5503+#define A6XX_SP_GS_PVT_MEM_PARAM_MEMSIZEPERITEM__SHIFT 0
5504+static inline uint32_t A6XX_SP_GS_PVT_MEM_PARAM_MEMSIZEPERITEM(uint32_t val)
5505+{
5506+ return ((val >> 9) << A6XX_SP_GS_PVT_MEM_PARAM_MEMSIZEPERITEM__SHIFT) & A6XX_SP_GS_PVT_MEM_PARAM_MEMSIZEPERITEM__MASK;
5507+}
5508+#define A6XX_SP_GS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__MASK 0xff000000
5509+#define A6XX_SP_GS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__SHIFT 24
5510+static inline uint32_t A6XX_SP_GS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD(uint32_t val)
5511+{
5512+ return ((val) << A6XX_SP_GS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__SHIFT) & A6XX_SP_GS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__MASK;
5513+}
5514+
5515+#define REG_A6XX_SP_GS_PVT_MEM_ADDR 0x0000a890
5516+#define A6XX_SP_GS_PVT_MEM_ADDR__MASK 0xffffffff
5517+#define A6XX_SP_GS_PVT_MEM_ADDR__SHIFT 0
5518+static inline uint32_t A6XX_SP_GS_PVT_MEM_ADDR(uint32_t val)
5519+{
5520+ return ((val) << A6XX_SP_GS_PVT_MEM_ADDR__SHIFT) & A6XX_SP_GS_PVT_MEM_ADDR__MASK;
5521+}
5522+
5523+#define REG_A6XX_SP_GS_PVT_MEM_SIZE 0x0000a892
5524+#define A6XX_SP_GS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__MASK 0x0003ffff
5525+#define A6XX_SP_GS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__SHIFT 0
5526+static inline uint32_t A6XX_SP_GS_PVT_MEM_SIZE_TOTALPVTMEMSIZE(uint32_t val)
5527+{
5528+ return ((val >> 12) << A6XX_SP_GS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__SHIFT) & A6XX_SP_GS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__MASK;
5529+}
5530+#define A6XX_SP_GS_PVT_MEM_SIZE_PERWAVEMEMLAYOUT 0x80000000
60095531
60105532 #define REG_A6XX_SP_GS_TEX_COUNT 0x0000a893
60115533
@@ -6027,7 +5549,7 @@ static inline uint32_t A6XX_SP_GS_CONFIG_NSAMP(uint32_t val) · 15 unmodified lines
60275549 {
60285550 return ((val) << A6XX_SP_GS_CONFIG_NSAMP__SHIFT) & A6XX_SP_GS_CONFIG_NSAMP__MASK;
60295551 }
6030−#define A6XX_SP_GS_CONFIG_NIBO__MASK 0x3fc00000
5552+#define A6XX_SP_GS_CONFIG_NIBO__MASK 0x1fc00000
60315553 #define A6XX_SP_GS_CONFIG_NIBO__SHIFT 22
60325554 static inline uint32_t A6XX_SP_GS_CONFIG_NIBO(uint32_t val)
60335555 {
@@ -6036,39 +5558,104 @@ static inline uint32_t A6XX_SP_GS_CONFIG_NIBO(uint32_t val) · 2 unmodified lines
60365558
60375559 #define REG_A6XX_SP_GS_INSTRLEN 0x0000a895
60385560
6039−#define REG_A6XX_SP_VS_TEX_SAMP_LO 0x0000a8a0
6040−
6041−#define REG_A6XX_SP_VS_TEX_SAMP_HI 0x0000a8a1
6042−
6043−#define REG_A6XX_SP_HS_TEX_SAMP_LO 0x0000a8a2
6044−
6045−#define REG_A6XX_SP_HS_TEX_SAMP_HI 0x0000a8a3
6046−
6047−#define REG_A6XX_SP_DS_TEX_SAMP_LO 0x0000a8a4
6048−
6049−#define REG_A6XX_SP_DS_TEX_SAMP_HI 0x0000a8a5
6050−
6051−#define REG_A6XX_SP_GS_TEX_SAMP_LO 0x0000a8a6
6052−
6053−#define REG_A6XX_SP_GS_TEX_SAMP_HI 0x0000a8a7
5561+#define REG_A6XX_SP_GS_PVT_MEM_HW_STACK_OFFSET 0x0000a896
5562+#define A6XX_SP_GS_PVT_MEM_HW_STACK_OFFSET__MASK 0x0007ffff
5563+#define A6XX_SP_GS_PVT_MEM_HW_STACK_OFFSET__SHIFT 0
5564+static inline uint32_t A6XX_SP_GS_PVT_MEM_HW_STACK_OFFSET(uint32_t val)
5565+{
5566+ return ((val >> 11) << A6XX_SP_GS_PVT_MEM_HW_STACK_OFFSET__SHIFT) & A6XX_SP_GS_PVT_MEM_HW_STACK_OFFSET__MASK;
5567+}
60545568
6055−#define REG_A6XX_SP_VS_TEX_CONST_LO 0x0000a8a8
5569+#define REG_A6XX_SP_VS_TEX_SAMP 0x0000a8a0
5570+#define A6XX_SP_VS_TEX_SAMP__MASK 0xffffffff
5571+#define A6XX_SP_VS_TEX_SAMP__SHIFT 0
5572+static inline uint32_t A6XX_SP_VS_TEX_SAMP(uint32_t val)
5573+{
5574+ return ((val) << A6XX_SP_VS_TEX_SAMP__SHIFT) & A6XX_SP_VS_TEX_SAMP__MASK;
5575+}
60565576
6057−#define REG_A6XX_SP_VS_TEX_CONST_HI 0x0000a8a9
5577+#define REG_A6XX_SP_HS_TEX_SAMP 0x0000a8a2
5578+#define A6XX_SP_HS_TEX_SAMP__MASK 0xffffffff
5579+#define A6XX_SP_HS_TEX_SAMP__SHIFT 0
5580+static inline uint32_t A6XX_SP_HS_TEX_SAMP(uint32_t val)
5581+{
5582+ return ((val) << A6XX_SP_HS_TEX_SAMP__SHIFT) & A6XX_SP_HS_TEX_SAMP__MASK;
5583+}
60585584
6059−#define REG_A6XX_SP_HS_TEX_CONST_LO 0x0000a8aa
5585+#define REG_A6XX_SP_DS_TEX_SAMP 0x0000a8a4
5586+#define A6XX_SP_DS_TEX_SAMP__MASK 0xffffffff
5587+#define A6XX_SP_DS_TEX_SAMP__SHIFT 0
5588+static inline uint32_t A6XX_SP_DS_TEX_SAMP(uint32_t val)
5589+{
5590+ return ((val) << A6XX_SP_DS_TEX_SAMP__SHIFT) & A6XX_SP_DS_TEX_SAMP__MASK;
5591+}
60605592
6061−#define REG_A6XX_SP_HS_TEX_CONST_HI 0x0000a8ab
5593+#define REG_A6XX_SP_GS_TEX_SAMP 0x0000a8a6
5594+#define A6XX_SP_GS_TEX_SAMP__MASK 0xffffffff
5595+#define A6XX_SP_GS_TEX_SAMP__SHIFT 0
5596+static inline uint32_t A6XX_SP_GS_TEX_SAMP(uint32_t val)
5597+{
5598+ return ((val) << A6XX_SP_GS_TEX_SAMP__SHIFT) & A6XX_SP_GS_TEX_SAMP__MASK;
5599+}
60625600
6063−#define REG_A6XX_SP_DS_TEX_CONST_LO 0x0000a8ac
5601+#define REG_A6XX_SP_VS_TEX_CONST 0x0000a8a8
5602+#define A6XX_SP_VS_TEX_CONST__MASK 0xffffffff
5603+#define A6XX_SP_VS_TEX_CONST__SHIFT 0
5604+static inline uint32_t A6XX_SP_VS_TEX_CONST(uint32_t val)
5605+{
5606+ return ((val) << A6XX_SP_VS_TEX_CONST__SHIFT) & A6XX_SP_VS_TEX_CONST__MASK;
5607+}
60645608
6065−#define REG_A6XX_SP_DS_TEX_CONST_HI 0x0000a8ad
5609+#define REG_A6XX_SP_HS_TEX_CONST 0x0000a8aa
5610+#define A6XX_SP_HS_TEX_CONST__MASK 0xffffffff
5611+#define A6XX_SP_HS_TEX_CONST__SHIFT 0
5612+static inline uint32_t A6XX_SP_HS_TEX_CONST(uint32_t val)
5613+{
5614+ return ((val) << A6XX_SP_HS_TEX_CONST__SHIFT) & A6XX_SP_HS_TEX_CONST__MASK;
5615+}
60665616
6067−#define REG_A6XX_SP_GS_TEX_CONST_LO 0x0000a8ae
5617+#define REG_A6XX_SP_DS_TEX_CONST 0x0000a8ac
5618+#define A6XX_SP_DS_TEX_CONST__MASK 0xffffffff
5619+#define A6XX_SP_DS_TEX_CONST__SHIFT 0
5620+static inline uint32_t A6XX_SP_DS_TEX_CONST(uint32_t val)
5621+{
5622+ return ((val) << A6XX_SP_DS_TEX_CONST__SHIFT) & A6XX_SP_DS_TEX_CONST__MASK;
5623+}
60685624
6069−#define REG_A6XX_SP_GS_TEX_CONST_HI 0x0000a8af
5625+#define REG_A6XX_SP_GS_TEX_CONST 0x0000a8ae
5626+#define A6XX_SP_GS_TEX_CONST__MASK 0xffffffff
5627+#define A6XX_SP_GS_TEX_CONST__SHIFT 0
5628+static inline uint32_t A6XX_SP_GS_TEX_CONST(uint32_t val)
5629+{
5630+ return ((val) << A6XX_SP_GS_TEX_CONST__SHIFT) & A6XX_SP_GS_TEX_CONST__MASK;
5631+}
60705632
60715633 #define REG_A6XX_SP_FS_CTRL_REG0 0x0000a980
5634+#define A6XX_SP_FS_CTRL_REG0_THREADSIZE__MASK 0x00100000
5635+#define A6XX_SP_FS_CTRL_REG0_THREADSIZE__SHIFT 20
5636+static inline uint32_t A6XX_SP_FS_CTRL_REG0_THREADSIZE(enum a6xx_threadsize val)
5637+{
5638+ return ((val) << A6XX_SP_FS_CTRL_REG0_THREADSIZE__SHIFT) & A6XX_SP_FS_CTRL_REG0_THREADSIZE__MASK;
5639+}
5640+#define A6XX_SP_FS_CTRL_REG0_UNK21 0x00200000
5641+#define A6XX_SP_FS_CTRL_REG0_VARYING 0x00400000
5642+#define A6XX_SP_FS_CTRL_REG0_DIFF_FINE 0x00800000
5643+#define A6XX_SP_FS_CTRL_REG0_UNK24 0x01000000
5644+#define A6XX_SP_FS_CTRL_REG0_UNK25 0x02000000
5645+#define A6XX_SP_FS_CTRL_REG0_PIXLODENABLE 0x04000000
5646+#define A6XX_SP_FS_CTRL_REG0_UNK27__MASK 0x18000000
5647+#define A6XX_SP_FS_CTRL_REG0_UNK27__SHIFT 27
5648+static inline uint32_t A6XX_SP_FS_CTRL_REG0_UNK27(uint32_t val)
5649+{
5650+ return ((val) << A6XX_SP_FS_CTRL_REG0_UNK27__SHIFT) & A6XX_SP_FS_CTRL_REG0_UNK27__MASK;
5651+}
5652+#define A6XX_SP_FS_CTRL_REG0_MERGEDREGS 0x80000000
5653+#define A6XX_SP_FS_CTRL_REG0_THREADMODE__MASK 0x00000001
5654+#define A6XX_SP_FS_CTRL_REG0_THREADMODE__SHIFT 0
5655+static inline uint32_t A6XX_SP_FS_CTRL_REG0_THREADMODE(enum a3xx_threadmode val)
5656+{
5657+ return ((val) << A6XX_SP_FS_CTRL_REG0_THREADMODE__SHIFT) & A6XX_SP_FS_CTRL_REG0_THREADMODE__MASK;
5658+}
60725659 #define A6XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__MASK 0x0000007e
60735660 #define A6XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT 1
60745661 static inline uint32_t A6XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val)
@@ -6081,33 +5668,64 @@ static inline uint32_t A6XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val) · 6 unmodified lines
60815668 {
60825669 return ((val) << A6XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT) & A6XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__MASK;
60835670 }
5671+#define A6XX_SP_FS_CTRL_REG0_UNK13 0x00002000
60845672 #define A6XX_SP_FS_CTRL_REG0_BRANCHSTACK__MASK 0x000fc000
60855673 #define A6XX_SP_FS_CTRL_REG0_BRANCHSTACK__SHIFT 14
60865674 static inline uint32_t A6XX_SP_FS_CTRL_REG0_BRANCHSTACK(uint32_t val)
60875675 {
60885676 return ((val) << A6XX_SP_FS_CTRL_REG0_BRANCHSTACK__SHIFT) & A6XX_SP_FS_CTRL_REG0_BRANCHSTACK__MASK;
60895677 }
6090−#define A6XX_SP_FS_CTRL_REG0_THREADSIZE__MASK 0x00100000
6091−#define A6XX_SP_FS_CTRL_REG0_THREADSIZE__SHIFT 20
6092−static inline uint32_t A6XX_SP_FS_CTRL_REG0_THREADSIZE(enum a3xx_threadsize val)
6093−{
6094− return ((val) << A6XX_SP_FS_CTRL_REG0_THREADSIZE__SHIFT) & A6XX_SP_FS_CTRL_REG0_THREADSIZE__MASK;
6095−}
6096−#define A6XX_SP_FS_CTRL_REG0_VARYING 0x00400000
6097−#define A6XX_SP_FS_CTRL_REG0_DIFF_FINE 0x00800000
6098−#define A6XX_SP_FS_CTRL_REG0_PIXLODENABLE 0x04000000
6099−#define A6XX_SP_FS_CTRL_REG0_MERGEDREGS 0x80000000
61005678
61015679 #define REG_A6XX_SP_FS_BRANCH_COND 0x0000a981
61025680
6103−#define REG_A6XX_SP_UNKNOWN_A982 0x0000a982
5681+#define REG_A6XX_SP_FS_OBJ_FIRST_EXEC_OFFSET 0x0000a982
5682+
5683+#define REG_A6XX_SP_FS_OBJ_START 0x0000a983
5684+#define A6XX_SP_FS_OBJ_START__MASK 0xffffffff
5685+#define A6XX_SP_FS_OBJ_START__SHIFT 0
5686+static inline uint32_t A6XX_SP_FS_OBJ_START(uint32_t val)
5687+{
5688+ return ((val) << A6XX_SP_FS_OBJ_START__SHIFT) & A6XX_SP_FS_OBJ_START__MASK;
5689+}
5690+
5691+#define REG_A6XX_SP_FS_PVT_MEM_PARAM 0x0000a985
5692+#define A6XX_SP_FS_PVT_MEM_PARAM_MEMSIZEPERITEM__MASK 0x000000ff
5693+#define A6XX_SP_FS_PVT_MEM_PARAM_MEMSIZEPERITEM__SHIFT 0
5694+static inline uint32_t A6XX_SP_FS_PVT_MEM_PARAM_MEMSIZEPERITEM(uint32_t val)
5695+{
5696+ return ((val >> 9) << A6XX_SP_FS_PVT_MEM_PARAM_MEMSIZEPERITEM__SHIFT) & A6XX_SP_FS_PVT_MEM_PARAM_MEMSIZEPERITEM__MASK;
5697+}
5698+#define A6XX_SP_FS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__MASK 0xff000000
5699+#define A6XX_SP_FS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__SHIFT 24
5700+static inline uint32_t A6XX_SP_FS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD(uint32_t val)
5701+{
5702+ return ((val) << A6XX_SP_FS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__SHIFT) & A6XX_SP_FS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__MASK;
5703+}
61045704
6105−#define REG_A6XX_SP_FS_OBJ_START_LO 0x0000a983
5705+#define REG_A6XX_SP_FS_PVT_MEM_ADDR 0x0000a986
5706+#define A6XX_SP_FS_PVT_MEM_ADDR__MASK 0xffffffff
5707+#define A6XX_SP_FS_PVT_MEM_ADDR__SHIFT 0
5708+static inline uint32_t A6XX_SP_FS_PVT_MEM_ADDR(uint32_t val)
5709+{
5710+ return ((val) << A6XX_SP_FS_PVT_MEM_ADDR__SHIFT) & A6XX_SP_FS_PVT_MEM_ADDR__MASK;
5711+}
61065712
6107−#define REG_A6XX_SP_FS_OBJ_START_HI 0x0000a984
5713+#define REG_A6XX_SP_FS_PVT_MEM_SIZE 0x0000a988
5714+#define A6XX_SP_FS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__MASK 0x0003ffff
5715+#define A6XX_SP_FS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__SHIFT 0
5716+static inline uint32_t A6XX_SP_FS_PVT_MEM_SIZE_TOTALPVTMEMSIZE(uint32_t val)
5717+{
5718+ return ((val >> 12) << A6XX_SP_FS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__SHIFT) & A6XX_SP_FS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__MASK;
5719+}
5720+#define A6XX_SP_FS_PVT_MEM_SIZE_PERWAVEMEMLAYOUT 0x80000000
61085721
61095722 #define REG_A6XX_SP_BLEND_CNTL 0x0000a989
6110−#define A6XX_SP_BLEND_CNTL_ENABLED 0x00000001
5723+#define A6XX_SP_BLEND_CNTL_ENABLE_BLEND__MASK 0x000000ff
5724+#define A6XX_SP_BLEND_CNTL_ENABLE_BLEND__SHIFT 0
5725+static inline uint32_t A6XX_SP_BLEND_CNTL_ENABLE_BLEND(uint32_t val)
5726+{
5727+ return ((val) << A6XX_SP_BLEND_CNTL_ENABLE_BLEND__SHIFT) & A6XX_SP_BLEND_CNTL_ENABLE_BLEND__MASK;
5728+}
61115729 #define A6XX_SP_BLEND_CNTL_UNK8 0x00000100
61125730 #define A6XX_SP_BLEND_CNTL_DUAL_COLOR_IN_ENABLE 0x00000200
61135731 #define A6XX_SP_BLEND_CNTL_ALPHA_TO_COVERAGE 0x00000400
@@ -6201,6 +5819,17 @@ static inline uint32_t A6XX_SP_FS_OUTPUT_CNTL1_MRT(uint32_t val) · 87 unmodified lines
62015819 return ((val) << A6XX_SP_FS_OUTPUT_CNTL1_MRT__SHIFT) & A6XX_SP_FS_OUTPUT_CNTL1_MRT__MASK;
62025820 }
62035821
5822+static inline uint32_t REG_A6XX_SP_FS_OUTPUT(uint32_t i0) { return 0x0000a98e + 0x1*i0; }
5823+
5824+static inline uint32_t REG_A6XX_SP_FS_OUTPUT_REG(uint32_t i0) { return 0x0000a98e + 0x1*i0; }
5825+#define A6XX_SP_FS_OUTPUT_REG_REGID__MASK 0x000000ff
5826+#define A6XX_SP_FS_OUTPUT_REG_REGID__SHIFT 0
5827+static inline uint32_t A6XX_SP_FS_OUTPUT_REG_REGID(uint32_t val)
5828+{
5829+ return ((val) << A6XX_SP_FS_OUTPUT_REG_REGID__SHIFT) & A6XX_SP_FS_OUTPUT_REG_REGID__MASK;
5830+}
5831+#define A6XX_SP_FS_OUTPUT_REG_HALF_PRECISION 0x00000100
5832+
62045833 static inline uint32_t REG_A6XX_SP_FS_MRT(uint32_t i0) { return 0x0000a996 + 0x1*i0; }
62055834
62065835 static inline uint32_t REG_A6XX_SP_FS_MRT_REG(uint32_t i0) { return 0x0000a996 + 0x1*i0; }
@@ -6212,6 +5841,7 @@ static inline uint32_t A6XX_SP_FS_MRT_REG_COLOR_FORMAT(enum a6xx_format val) · 5 unmodified lines
62125841 }
62135842 #define A6XX_SP_FS_MRT_REG_COLOR_SINT 0x00000100
62145843 #define A6XX_SP_FS_MRT_REG_COLOR_UINT 0x00000200
5844+#define A6XX_SP_FS_MRT_REG_UNK10 0x00000400
62155845
62165846 #define REG_A6XX_SP_FS_PREFETCH_CNTL 0x0000a99e
62175847 #define A6XX_SP_FS_PREFETCH_CNTL_COUNT__MASK 0x00000007
@@ -6227,6 +5857,12 @@ static inline uint32_t A6XX_SP_FS_PREFETCH_CNTL_UNK4(uint32_t val) · 9 unmodified lines
62275857 {
62285858 return ((val) << A6XX_SP_FS_PREFETCH_CNTL_UNK4__SHIFT) & A6XX_SP_FS_PREFETCH_CNTL_UNK4__MASK;
62295859 }
5860+#define A6XX_SP_FS_PREFETCH_CNTL_UNK12__MASK 0x00007000
5861+#define A6XX_SP_FS_PREFETCH_CNTL_UNK12__SHIFT 12
5862+static inline uint32_t A6XX_SP_FS_PREFETCH_CNTL_UNK12(uint32_t val)
5863+{
5864+ return ((val) << A6XX_SP_FS_PREFETCH_CNTL_UNK12__SHIFT) & A6XX_SP_FS_PREFETCH_CNTL_UNK12__MASK;
5865+}
62305866
62315867 static inline uint32_t REG_A6XX_SP_FS_PREFETCH(uint32_t i0) { return 0x0000a99f + 0x1*i0; }
62325868
@@ -6272,13 +5908,13 @@ static inline uint32_t A6XX_SP_FS_PREFETCH_CMD_CMD(uint32_t val) · 39 unmodified lines
62725908 static inline uint32_t REG_A6XX_SP_FS_BINDLESS_PREFETCH(uint32_t i0) { return 0x0000a9a3 + 0x1*i0; }
62735909
62745910 static inline uint32_t REG_A6XX_SP_FS_BINDLESS_PREFETCH_CMD(uint32_t i0) { return 0x0000a9a3 + 0x1*i0; }
6275−#define A6XX_SP_FS_BINDLESS_PREFETCH_CMD_SAMP_ID__MASK 0x000000ff
5911+#define A6XX_SP_FS_BINDLESS_PREFETCH_CMD_SAMP_ID__MASK 0x0000ffff
62765912 #define A6XX_SP_FS_BINDLESS_PREFETCH_CMD_SAMP_ID__SHIFT 0
62775913 static inline uint32_t A6XX_SP_FS_BINDLESS_PREFETCH_CMD_SAMP_ID(uint32_t val)
62785914 {
62795915 return ((val) << A6XX_SP_FS_BINDLESS_PREFETCH_CMD_SAMP_ID__SHIFT) & A6XX_SP_FS_BINDLESS_PREFETCH_CMD_SAMP_ID__MASK;
62805916 }
6281−#define A6XX_SP_FS_BINDLESS_PREFETCH_CMD_TEX_ID__MASK 0x00ff0000
5917+#define A6XX_SP_FS_BINDLESS_PREFETCH_CMD_TEX_ID__MASK 0xffff0000
62825918 #define A6XX_SP_FS_BINDLESS_PREFETCH_CMD_TEX_ID__SHIFT 16
62835919 static inline uint32_t A6XX_SP_FS_BINDLESS_PREFETCH_CMD_TEX_ID(uint32_t val)
62845920 {
@@ -6289,50 +5925,31 @@ static inline uint32_t A6XX_SP_FS_BINDLESS_PREFETCH_CMD_TEX_ID(uint32_t val) · 4 unmodified lines
62895925
62905926 #define REG_A6XX_SP_UNKNOWN_A9A8 0x0000a9a8
62915927
6292−#define REG_A6XX_SP_CS_UNKNOWN_A9B1 0x0000a9b1
6293−#define A6XX_SP_CS_UNKNOWN_A9B1_SHARED_SIZE_2K__MASK 0x00000001
6294−#define A6XX_SP_CS_UNKNOWN_A9B1_SHARED_SIZE_2K__SHIFT 0
6295−static inline uint32_t A6XX_SP_CS_UNKNOWN_A9B1_SHARED_SIZE_2K(uint32_t val)
5928+#define REG_A6XX_SP_FS_PVT_MEM_HW_STACK_OFFSET 0x0000a9a9
5929+#define A6XX_SP_FS_PVT_MEM_HW_STACK_OFFSET__MASK 0x0007ffff
5930+#define A6XX_SP_FS_PVT_MEM_HW_STACK_OFFSET__SHIFT 0
5931+static inline uint32_t A6XX_SP_FS_PVT_MEM_HW_STACK_OFFSET(uint32_t val)
62965932 {
6297− return ((val) << A6XX_SP_CS_UNKNOWN_A9B1_SHARED_SIZE_2K__SHIFT) & A6XX_SP_CS_UNKNOWN_A9B1_SHARED_SIZE_2K__MASK;
5933+ return ((val >> 11) << A6XX_SP_FS_PVT_MEM_HW_STACK_OFFSET__SHIFT) & A6XX_SP_FS_PVT_MEM_HW_STACK_OFFSET__MASK;
62985934 }
62995935
6300−#define REG_A6XX_SP_CS_UNKNOWN_A9B3 0x0000a9b3
6301−
6302−#define REG_A6XX_SP_CS_TEX_COUNT 0x0000a9ba
6303−
6304−#define REG_A6XX_SP_FS_TEX_SAMP_LO 0x0000a9e0
6305−
6306−#define REG_A6XX_SP_FS_TEX_SAMP_HI 0x0000a9e1
6307−
6308−#define REG_A6XX_SP_CS_TEX_SAMP_LO 0x0000a9e2
6309−
6310−#define REG_A6XX_SP_CS_TEX_SAMP_HI 0x0000a9e3
6311−
6312−#define REG_A6XX_SP_FS_TEX_CONST_LO 0x0000a9e4
6313−
6314−#define REG_A6XX_SP_FS_TEX_CONST_HI 0x0000a9e5
6315−
6316−#define REG_A6XX_SP_CS_TEX_CONST_LO 0x0000a9e6
6317−
6318−#define REG_A6XX_SP_CS_TEX_CONST_HI 0x0000a9e7
6319−
6320−static inline uint32_t REG_A6XX_SP_CS_BINDLESS_BASE(uint32_t i0) { return 0x0000a9e8 + 0x2*i0; }
6321−
6322−static inline uint32_t REG_A6XX_SP_CS_BINDLESS_BASE_ADDR(uint32_t i0) { return 0x0000a9e8 + 0x2*i0; }
6323−
6324−static inline uint32_t REG_A6XX_SP_FS_OUTPUT(uint32_t i0) { return 0x0000a98e + 0x1*i0; }
6325−
6326−static inline uint32_t REG_A6XX_SP_FS_OUTPUT_REG(uint32_t i0) { return 0x0000a98e + 0x1*i0; }
6327−#define A6XX_SP_FS_OUTPUT_REG_REGID__MASK 0x000000ff
6328−#define A6XX_SP_FS_OUTPUT_REG_REGID__SHIFT 0
6329−static inline uint32_t A6XX_SP_FS_OUTPUT_REG_REGID(uint32_t val)
5936+#define REG_A6XX_SP_CS_CTRL_REG0 0x0000a9b0
5937+#define A6XX_SP_CS_CTRL_REG0_THREADSIZE__MASK 0x00100000
5938+#define A6XX_SP_CS_CTRL_REG0_THREADSIZE__SHIFT 20
5939+static inline uint32_t A6XX_SP_CS_CTRL_REG0_THREADSIZE(enum a6xx_threadsize val)
63305940 {
6331− return ((val) << A6XX_SP_FS_OUTPUT_REG_REGID__SHIFT) & A6XX_SP_FS_OUTPUT_REG_REGID__MASK;
5941+ return ((val) << A6XX_SP_CS_CTRL_REG0_THREADSIZE__SHIFT) & A6XX_SP_CS_CTRL_REG0_THREADSIZE__MASK;
5942+}
5943+#define A6XX_SP_CS_CTRL_REG0_UNK21 0x00200000
5944+#define A6XX_SP_CS_CTRL_REG0_UNK22 0x00400000
5945+#define A6XX_SP_CS_CTRL_REG0_SEPARATEPROLOG 0x00800000
5946+#define A6XX_SP_CS_CTRL_REG0_MERGEDREGS 0x80000000
5947+#define A6XX_SP_CS_CTRL_REG0_THREADMODE__MASK 0x00000001
5948+#define A6XX_SP_CS_CTRL_REG0_THREADMODE__SHIFT 0
5949+static inline uint32_t A6XX_SP_CS_CTRL_REG0_THREADMODE(enum a3xx_threadmode val)
5950+{
5951+ return ((val) << A6XX_SP_CS_CTRL_REG0_THREADMODE__SHIFT) & A6XX_SP_CS_CTRL_REG0_THREADMODE__MASK;
63325952 }
6333−#define A6XX_SP_FS_OUTPUT_REG_HALF_PRECISION 0x00000100
6334−
6335−#define REG_A6XX_SP_CS_CTRL_REG0 0x0000a9b0
63365953 #define A6XX_SP_CS_CTRL_REG0_HALFREGFOOTPRINT__MASK 0x0000007e
63375954 #define A6XX_SP_CS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT 1
63385955 static inline uint32_t A6XX_SP_CS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val)
@@ -6345,26 +5962,68 @@ static inline uint32_t A6XX_SP_CS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val) · 6 unmodified lines
63455962 {
63465963 return ((val) << A6XX_SP_CS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT) & A6XX_SP_CS_CTRL_REG0_FULLREGFOOTPRINT__MASK;
63475964 }
5965+#define A6XX_SP_CS_CTRL_REG0_UNK13 0x00002000
63485966 #define A6XX_SP_CS_CTRL_REG0_BRANCHSTACK__MASK 0x000fc000
63495967 #define A6XX_SP_CS_CTRL_REG0_BRANCHSTACK__SHIFT 14
63505968 static inline uint32_t A6XX_SP_CS_CTRL_REG0_BRANCHSTACK(uint32_t val)
63515969 {
63525970 return ((val) << A6XX_SP_CS_CTRL_REG0_BRANCHSTACK__SHIFT) & A6XX_SP_CS_CTRL_REG0_BRANCHSTACK__MASK;
63535971 }
6354−#define A6XX_SP_CS_CTRL_REG0_THREADSIZE__MASK 0x00100000
6355−#define A6XX_SP_CS_CTRL_REG0_THREADSIZE__SHIFT 20
6356−static inline uint32_t A6XX_SP_CS_CTRL_REG0_THREADSIZE(enum a3xx_threadsize val)
5972+
5973+#define REG_A6XX_SP_CS_UNKNOWN_A9B1 0x0000a9b1
5974+#define A6XX_SP_CS_UNKNOWN_A9B1_SHARED_SIZE__MASK 0x0000001f
5975+#define A6XX_SP_CS_UNKNOWN_A9B1_SHARED_SIZE__SHIFT 0
5976+static inline uint32_t A6XX_SP_CS_UNKNOWN_A9B1_SHARED_SIZE(uint32_t val)
63575977 {
6358− return ((val) << A6XX_SP_CS_CTRL_REG0_THREADSIZE__SHIFT) & A6XX_SP_CS_CTRL_REG0_THREADSIZE__MASK;
5978+ return ((val) << A6XX_SP_CS_UNKNOWN_A9B1_SHARED_SIZE__SHIFT) & A6XX_SP_CS_UNKNOWN_A9B1_SHARED_SIZE__MASK;
5979+}
5980+#define A6XX_SP_CS_UNKNOWN_A9B1_UNK5 0x00000020
5981+#define A6XX_SP_CS_UNKNOWN_A9B1_UNK6 0x00000040
5982+
5983+#define REG_A6XX_SP_CS_BRANCH_COND 0x0000a9b2
5984+
5985+#define REG_A6XX_SP_CS_OBJ_FIRST_EXEC_OFFSET 0x0000a9b3
5986+
5987+#define REG_A6XX_SP_CS_OBJ_START 0x0000a9b4
5988+#define A6XX_SP_CS_OBJ_START__MASK 0xffffffff
5989+#define A6XX_SP_CS_OBJ_START__SHIFT 0
5990+static inline uint32_t A6XX_SP_CS_OBJ_START(uint32_t val)
5991+{
5992+ return ((val) << A6XX_SP_CS_OBJ_START__SHIFT) & A6XX_SP_CS_OBJ_START__MASK;
5993+}
5994+
5995+#define REG_A6XX_SP_CS_PVT_MEM_PARAM 0x0000a9b6
5996+#define A6XX_SP_CS_PVT_MEM_PARAM_MEMSIZEPERITEM__MASK 0x000000ff
5997+#define A6XX_SP_CS_PVT_MEM_PARAM_MEMSIZEPERITEM__SHIFT 0
5998+static inline uint32_t A6XX_SP_CS_PVT_MEM_PARAM_MEMSIZEPERITEM(uint32_t val)
5999+{
6000+ return ((val >> 9) << A6XX_SP_CS_PVT_MEM_PARAM_MEMSIZEPERITEM__SHIFT) & A6XX_SP_CS_PVT_MEM_PARAM_MEMSIZEPERITEM__MASK;
6001+}
6002+#define A6XX_SP_CS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__MASK 0xff000000
6003+#define A6XX_SP_CS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__SHIFT 24
6004+static inline uint32_t A6XX_SP_CS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD(uint32_t val)
6005+{
6006+ return ((val) << A6XX_SP_CS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__SHIFT) & A6XX_SP_CS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__MASK;
6007+}
6008+
6009+#define REG_A6XX_SP_CS_PVT_MEM_ADDR 0x0000a9b7
6010+#define A6XX_SP_CS_PVT_MEM_ADDR__MASK 0xffffffff
6011+#define A6XX_SP_CS_PVT_MEM_ADDR__SHIFT 0
6012+static inline uint32_t A6XX_SP_CS_PVT_MEM_ADDR(uint32_t val)
6013+{
6014+ return ((val) << A6XX_SP_CS_PVT_MEM_ADDR__SHIFT) & A6XX_SP_CS_PVT_MEM_ADDR__MASK;
63596015 }
6360−#define A6XX_SP_CS_CTRL_REG0_VARYING 0x00400000
6361−#define A6XX_SP_CS_CTRL_REG0_DIFF_FINE 0x00800000
6362−#define A6XX_SP_CS_CTRL_REG0_PIXLODENABLE 0x04000000
6363−#define A6XX_SP_CS_CTRL_REG0_MERGEDREGS 0x80000000
63646016
6365−#define REG_A6XX_SP_CS_OBJ_START_LO 0x0000a9b4
6017+#define REG_A6XX_SP_CS_PVT_MEM_SIZE 0x0000a9b9
6018+#define A6XX_SP_CS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__MASK 0x0003ffff
6019+#define A6XX_SP_CS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__SHIFT 0
6020+static inline uint32_t A6XX_SP_CS_PVT_MEM_SIZE_TOTALPVTMEMSIZE(uint32_t val)
6021+{
6022+ return ((val >> 12) << A6XX_SP_CS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__SHIFT) & A6XX_SP_CS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__MASK;
6023+}
6024+#define A6XX_SP_CS_PVT_MEM_SIZE_PERWAVEMEMLAYOUT 0x80000000
63666025
6367−#define REG_A6XX_SP_CS_OBJ_START_HI 0x0000a9b5
6026+#define REG_A6XX_SP_CS_TEX_COUNT 0x0000a9ba
63686027
63696028 #define REG_A6XX_SP_CS_CONFIG 0x0000a9bb
63706029 #define A6XX_SP_CS_CONFIG_BINDLESS_TEX 0x00000001
@@ -6384,7 +6043,7 @@ static inline uint32_t A6XX_SP_CS_CONFIG_NSAMP(uint32_t val) · 13 unmodified lines
63846043 {
63856044 return ((val) << A6XX_SP_CS_CONFIG_NSAMP__SHIFT) & A6XX_SP_CS_CONFIG_NSAMP__MASK;
63866045 }
6387−#define A6XX_SP_CS_CONFIG_NIBO__MASK 0x3fc00000
6046+#define A6XX_SP_CS_CONFIG_NIBO__MASK 0x1fc00000
63886047 #define A6XX_SP_CS_CONFIG_NIBO__SHIFT 22
63896048 static inline uint32_t A6XX_SP_CS_CONFIG_NIBO(uint32_t val)
63906049 {
@@ -6393,13 +6052,65 @@ static inline uint32_t A6XX_SP_CS_CONFIG_NIBO(uint32_t val) · 2 unmodified lines
63936052
63946053 #define REG_A6XX_SP_CS_INSTRLEN 0x0000a9bc
63956054
6396−#define REG_A6XX_SP_CS_IBO_LO 0x0000a9f2
6055+#define REG_A6XX_SP_CS_PVT_MEM_HW_STACK_OFFSET 0x0000a9bd
6056+#define A6XX_SP_CS_PVT_MEM_HW_STACK_OFFSET__MASK 0x0007ffff
6057+#define A6XX_SP_CS_PVT_MEM_HW_STACK_OFFSET__SHIFT 0
6058+static inline uint32_t A6XX_SP_CS_PVT_MEM_HW_STACK_OFFSET(uint32_t val)
6059+{
6060+ return ((val >> 11) << A6XX_SP_CS_PVT_MEM_HW_STACK_OFFSET__SHIFT) & A6XX_SP_CS_PVT_MEM_HW_STACK_OFFSET__MASK;
6061+}
6062+
6063+#define REG_A6XX_SP_FS_TEX_SAMP 0x0000a9e0
6064+#define A6XX_SP_FS_TEX_SAMP__MASK 0xffffffff
6065+#define A6XX_SP_FS_TEX_SAMP__SHIFT 0
6066+static inline uint32_t A6XX_SP_FS_TEX_SAMP(uint32_t val)
6067+{
6068+ return ((val) << A6XX_SP_FS_TEX_SAMP__SHIFT) & A6XX_SP_FS_TEX_SAMP__MASK;
6069+}
6070+
6071+#define REG_A6XX_SP_CS_TEX_SAMP 0x0000a9e2
6072+#define A6XX_SP_CS_TEX_SAMP__MASK 0xffffffff
6073+#define A6XX_SP_CS_TEX_SAMP__SHIFT 0
6074+static inline uint32_t A6XX_SP_CS_TEX_SAMP(uint32_t val)
6075+{
6076+ return ((val) << A6XX_SP_CS_TEX_SAMP__SHIFT) & A6XX_SP_CS_TEX_SAMP__MASK;
6077+}
6078+
6079+#define REG_A6XX_SP_FS_TEX_CONST 0x0000a9e4
6080+#define A6XX_SP_FS_TEX_CONST__MASK 0xffffffff
6081+#define A6XX_SP_FS_TEX_CONST__SHIFT 0
6082+static inline uint32_t A6XX_SP_FS_TEX_CONST(uint32_t val)
6083+{
6084+ return ((val) << A6XX_SP_FS_TEX_CONST__SHIFT) & A6XX_SP_FS_TEX_CONST__MASK;
6085+}
6086+
6087+#define REG_A6XX_SP_CS_TEX_CONST 0x0000a9e6
6088+#define A6XX_SP_CS_TEX_CONST__MASK 0xffffffff
6089+#define A6XX_SP_CS_TEX_CONST__SHIFT 0
6090+static inline uint32_t A6XX_SP_CS_TEX_CONST(uint32_t val)
6091+{
6092+ return ((val) << A6XX_SP_CS_TEX_CONST__SHIFT) & A6XX_SP_CS_TEX_CONST__MASK;
6093+}
6094+
6095+static inline uint32_t REG_A6XX_SP_CS_BINDLESS_BASE(uint32_t i0) { return 0x0000a9e8 + 0x2*i0; }
63976096
6398−#define REG_A6XX_SP_CS_IBO_HI 0x0000a9f3
6097+static inline uint32_t REG_A6XX_SP_CS_BINDLESS_BASE_ADDR(uint32_t i0) { return 0x0000a9e8 + 0x2*i0; }
6098+
6099+#define REG_A6XX_SP_CS_IBO 0x0000a9f2
6100+#define A6XX_SP_CS_IBO__MASK 0xffffffff
6101+#define A6XX_SP_CS_IBO__SHIFT 0
6102+static inline uint32_t A6XX_SP_CS_IBO(uint32_t val)
6103+{
6104+ return ((val) << A6XX_SP_CS_IBO__SHIFT) & A6XX_SP_CS_IBO__MASK;
6105+}
63996106
64006107 #define REG_A6XX_SP_CS_IBO_COUNT 0x0000aa00
64016108
6402−#define REG_A6XX_SP_UNKNOWN_AB00 0x0000ab00
6109+#define REG_A6XX_SP_MODE_CONTROL 0x0000ab00
6110+#define A6XX_SP_MODE_CONTROL_CONSTANT_DEMOTION_ENABLE 0x00000001
6111+#define A6XX_SP_MODE_CONTROL_UNK1 0x00000002
6112+#define A6XX_SP_MODE_CONTROL_UNK2 0x00000004
6113+#define A6XX_SP_MODE_CONTROL_SHARED_CONSTS_ENABLE 0x00000008
64036114
64046115 #define REG_A6XX_SP_FS_CONFIG 0x0000ab04
64056116 #define A6XX_SP_FS_CONFIG_BINDLESS_TEX 0x00000001
@@ -6419,7 +6130,7 @@ static inline uint32_t A6XX_SP_FS_CONFIG_NSAMP(uint32_t val) · 13 unmodified lines
64196130 {
64206131 return ((val) << A6XX_SP_FS_CONFIG_NSAMP__SHIFT) & A6XX_SP_FS_CONFIG_NSAMP__MASK;
64216132 }
6422−#define A6XX_SP_FS_CONFIG_NIBO__MASK 0x3fc00000
6133+#define A6XX_SP_FS_CONFIG_NIBO__MASK 0x1fc00000
64236134 #define A6XX_SP_FS_CONFIG_NIBO__SHIFT 22
64246135 static inline uint32_t A6XX_SP_FS_CONFIG_NIBO(uint32_t val)
64256136 {
@@ -6432,9 +6143,13 @@ static inline uint32_t REG_A6XX_SP_BINDLESS_BASE(uint32_t i0) { return 0x0000ab1 · 6 unmodified lines
64326143
64336144 static inline uint32_t REG_A6XX_SP_BINDLESS_BASE_ADDR(uint32_t i0) { return 0x0000ab10 + 0x2*i0; }
64346145
6435−#define REG_A6XX_SP_IBO_LO 0x0000ab1a
6436−
6437−#define REG_A6XX_SP_IBO_HI 0x0000ab1b
6146+#define REG_A6XX_SP_IBO 0x0000ab1a
6147+#define A6XX_SP_IBO__MASK 0xffffffff
6148+#define A6XX_SP_IBO__SHIFT 0
6149+static inline uint32_t A6XX_SP_IBO(uint32_t val)
6150+{
6151+ return ((val) << A6XX_SP_IBO__SHIFT) & A6XX_SP_IBO__MASK;
6152+}
64386153
64396154 #define REG_A6XX_SP_IBO_COUNT 0x0000ab20
64406155
@@ -6458,18 +6173,41 @@ static inline uint32_t A6XX_SP_2D_DST_FORMAT_MASK(uint32_t val) · 17 unmodified lines
64586173
64596174 #define REG_A6XX_SP_UNKNOWN_AE00 0x0000ae00
64606175
6176+#define REG_A6XX_SP_ADDR_MODE_CNTL 0x0000ae01
6177+
6178+#define REG_A6XX_SP_NC_MODE_CNTL 0x0000ae02
6179+
64616180 #define REG_A6XX_SP_UNKNOWN_AE03 0x0000ae03
64626181
6463−#define REG_A6XX_SP_UNKNOWN_AE04 0x0000ae04
6182+#define REG_A6XX_SP_FLOAT_CNTL 0x0000ae04
6183+#define A6XX_SP_FLOAT_CNTL_F16_NO_INF 0x00000008
6184+
6185+#define REG_A6XX_SP_PERFCTR_ENABLE 0x0000ae0f
6186+#define A6XX_SP_PERFCTR_ENABLE_VS 0x00000001
6187+#define A6XX_SP_PERFCTR_ENABLE_HS 0x00000002
6188+#define A6XX_SP_PERFCTR_ENABLE_DS 0x00000004
6189+#define A6XX_SP_PERFCTR_ENABLE_GS 0x00000008
6190+#define A6XX_SP_PERFCTR_ENABLE_FS 0x00000010
6191+#define A6XX_SP_PERFCTR_ENABLE_CS 0x00000020
64646192
6465−#define REG_A6XX_SP_UNKNOWN_AE0F 0x0000ae0f
6193+static inline uint32_t REG_A6XX_SP_PERFCTR_SP_SEL(uint32_t i0) { return 0x0000ae10 + 0x1*i0; }
64666194
64676195 #define REG_A6XX_SP_PS_TP_BORDER_COLOR_BASE_ADDR 0x0000b180
6196+#define A6XX_SP_PS_TP_BORDER_COLOR_BASE_ADDR__MASK 0xffffffff
6197+#define A6XX_SP_PS_TP_BORDER_COLOR_BASE_ADDR__SHIFT 0
6198+static inline uint32_t A6XX_SP_PS_TP_BORDER_COLOR_BASE_ADDR(uint32_t val)
6199+{
6200+ return ((val) << A6XX_SP_PS_TP_BORDER_COLOR_BASE_ADDR__SHIFT) & A6XX_SP_PS_TP_BORDER_COLOR_BASE_ADDR__MASK;
6201+}
64686202
64696203 #define REG_A6XX_SP_UNKNOWN_B182 0x0000b182
64706204
64716205 #define REG_A6XX_SP_UNKNOWN_B183 0x0000b183
64726206
6207+#define REG_A6XX_SP_UNKNOWN_B190 0x0000b190
6208+
6209+#define REG_A6XX_SP_UNKNOWN_B191 0x0000b191
6210+
64736211 #define REG_A6XX_SP_TP_RAS_MSAA_CNTL 0x0000b300
64746212 #define A6XX_SP_TP_RAS_MSAA_CNTL_SAMPLES__MASK 0x00000003
64756213 #define A6XX_SP_TP_RAS_MSAA_CNTL_SAMPLES__SHIFT 0
@@ -6477,6 +6215,12 @@ static inline uint32_t A6XX_SP_TP_RAS_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples v · 1 unmodified line
64776215 {
64786216 return ((val) << A6XX_SP_TP_RAS_MSAA_CNTL_SAMPLES__SHIFT) & A6XX_SP_TP_RAS_MSAA_CNTL_SAMPLES__MASK;
64796217 }
6218+#define A6XX_SP_TP_RAS_MSAA_CNTL_UNK2__MASK 0x0000000c
6219+#define A6XX_SP_TP_RAS_MSAA_CNTL_UNK2__SHIFT 2
6220+static inline uint32_t A6XX_SP_TP_RAS_MSAA_CNTL_UNK2(uint32_t val)
6221+{
6222+ return ((val) << A6XX_SP_TP_RAS_MSAA_CNTL_UNK2__SHIFT) & A6XX_SP_TP_RAS_MSAA_CNTL_UNK2__MASK;
6223+}
64806224
64816225 #define REG_A6XX_SP_TP_DEST_MSAA_CNTL 0x0000b301
64826226 #define A6XX_SP_TP_DEST_MSAA_CNTL_SAMPLES__MASK 0x00000003
@@ -6488,10 +6232,12 @@ static inline uint32_t A6XX_SP_TP_DEST_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples · 5 unmodified lines
64886232 #define A6XX_SP_TP_DEST_MSAA_CNTL_MSAA_DISABLE 0x00000004
64896233
64906234 #define REG_A6XX_SP_TP_BORDER_COLOR_BASE_ADDR 0x0000b302
6491−
6492−#define REG_A6XX_SP_TP_BORDER_COLOR_BASE_ADDR_LO 0x0000b302
6493−
6494−#define REG_A6XX_SP_TP_BORDER_COLOR_BASE_ADDR_HI 0x0000b303
6235+#define A6XX_SP_TP_BORDER_COLOR_BASE_ADDR__MASK 0xffffffff
6236+#define A6XX_SP_TP_BORDER_COLOR_BASE_ADDR__SHIFT 0
6237+static inline uint32_t A6XX_SP_TP_BORDER_COLOR_BASE_ADDR(uint32_t val)
6238+{
6239+ return ((val) << A6XX_SP_TP_BORDER_COLOR_BASE_ADDR__SHIFT) & A6XX_SP_TP_BORDER_COLOR_BASE_ADDR__MASK;
6240+}
64956241
64966242 #define REG_A6XX_SP_TP_SAMPLE_CONFIG 0x0000b304
64976243 #define A6XX_SP_TP_SAMPLE_CONFIG_UNK0 0x00000001
@@ -6597,6 +6343,20 @@ static inline uint32_t A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_3_Y(float val) · 99 unmodified lines
65976343 return ((((int32_t)(val * 1.0))) << A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_3_Y__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_3_Y__MASK;
65986344 }
65996345
6346+#define REG_A6XX_SP_TP_WINDOW_OFFSET 0x0000b307
6347+#define A6XX_SP_TP_WINDOW_OFFSET_X__MASK 0x00003fff
6348+#define A6XX_SP_TP_WINDOW_OFFSET_X__SHIFT 0
6349+static inline uint32_t A6XX_SP_TP_WINDOW_OFFSET_X(uint32_t val)
6350+{
6351+ return ((val) << A6XX_SP_TP_WINDOW_OFFSET_X__SHIFT) & A6XX_SP_TP_WINDOW_OFFSET_X__MASK;
6352+}
6353+#define A6XX_SP_TP_WINDOW_OFFSET_Y__MASK 0x3fff0000
6354+#define A6XX_SP_TP_WINDOW_OFFSET_Y__SHIFT 16
6355+static inline uint32_t A6XX_SP_TP_WINDOW_OFFSET_Y(uint32_t val)
6356+{
6357+ return ((val) << A6XX_SP_TP_WINDOW_OFFSET_Y__SHIFT) & A6XX_SP_TP_WINDOW_OFFSET_Y__MASK;
6358+}
6359+
66006360 #define REG_A6XX_SP_TP_UNKNOWN_B309 0x0000b309
66016361
66026362 #define REG_A6XX_SP_PS_2D_SRC_INFO 0x0000b4c0
@@ -6627,9 +6387,19 @@ static inline uint32_t A6XX_SP_PS_2D_SRC_INFO_SAMPLES(enum a3xx_msaa_samples val · 24 unmodified lines
66276387 return ((val) << A6XX_SP_PS_2D_SRC_INFO_SAMPLES__SHIFT) & A6XX_SP_PS_2D_SRC_INFO_SAMPLES__MASK;
66286388 }
66296389 #define A6XX_SP_PS_2D_SRC_INFO_FILTER 0x00010000
6390+#define A6XX_SP_PS_2D_SRC_INFO_UNK17 0x00020000
66306391 #define A6XX_SP_PS_2D_SRC_INFO_SAMPLES_AVERAGE 0x00040000
6392+#define A6XX_SP_PS_2D_SRC_INFO_UNK19 0x00080000
66316393 #define A6XX_SP_PS_2D_SRC_INFO_UNK20 0x00100000
6394+#define A6XX_SP_PS_2D_SRC_INFO_UNK21 0x00200000
66326395 #define A6XX_SP_PS_2D_SRC_INFO_UNK22 0x00400000
6396+#define A6XX_SP_PS_2D_SRC_INFO_UNK23__MASK 0x07800000
6397+#define A6XX_SP_PS_2D_SRC_INFO_UNK23__SHIFT 23
6398+static inline uint32_t A6XX_SP_PS_2D_SRC_INFO_UNK23(uint32_t val)
6399+{
6400+ return ((val) << A6XX_SP_PS_2D_SRC_INFO_UNK23__SHIFT) & A6XX_SP_PS_2D_SRC_INFO_UNK23__MASK;
6401+}
6402+#define A6XX_SP_PS_2D_SRC_INFO_UNK28 0x10000000
66336403
66346404 #define REG_A6XX_SP_PS_2D_SRC_SIZE 0x0000b4c1
66356405 #define A6XX_SP_PS_2D_SRC_SIZE_WIDTH__MASK 0x00007fff
@@ -6645,43 +6415,131 @@ static inline uint32_t A6XX_SP_PS_2D_SRC_SIZE_HEIGHT(uint32_t val) · 9 unmodified lines
66456415 return ((val) << A6XX_SP_PS_2D_SRC_SIZE_HEIGHT__SHIFT) & A6XX_SP_PS_2D_SRC_SIZE_HEIGHT__MASK;
66466416 }
66476417
6648−#define REG_A6XX_SP_PS_2D_SRC_LO 0x0000b4c2
6649−
6650−#define REG_A6XX_SP_PS_2D_SRC_HI 0x0000b4c3
6651−
66526418 #define REG_A6XX_SP_PS_2D_SRC 0x0000b4c2
6419+#define A6XX_SP_PS_2D_SRC__MASK 0xffffffff
6420+#define A6XX_SP_PS_2D_SRC__SHIFT 0
6421+static inline uint32_t A6XX_SP_PS_2D_SRC(uint32_t val)
6422+{
6423+ return ((val) << A6XX_SP_PS_2D_SRC__SHIFT) & A6XX_SP_PS_2D_SRC__MASK;
6424+}
66536425
66546426 #define REG_A6XX_SP_PS_2D_SRC_PITCH 0x0000b4c4
6655−#define A6XX_SP_PS_2D_SRC_PITCH_PITCH__MASK 0x01fffe00
6427+#define A6XX_SP_PS_2D_SRC_PITCH_UNK0__MASK 0x000001ff
6428+#define A6XX_SP_PS_2D_SRC_PITCH_UNK0__SHIFT 0
6429+static inline uint32_t A6XX_SP_PS_2D_SRC_PITCH_UNK0(uint32_t val)
6430+{
6431+ return ((val) << A6XX_SP_PS_2D_SRC_PITCH_UNK0__SHIFT) & A6XX_SP_PS_2D_SRC_PITCH_UNK0__MASK;
6432+}
6433+#define A6XX_SP_PS_2D_SRC_PITCH_PITCH__MASK 0x00fffe00
66566434 #define A6XX_SP_PS_2D_SRC_PITCH_PITCH__SHIFT 9
66576435 static inline uint32_t A6XX_SP_PS_2D_SRC_PITCH_PITCH(uint32_t val)
66586436 {
66596437 return ((val >> 6) << A6XX_SP_PS_2D_SRC_PITCH_PITCH__SHIFT) & A6XX_SP_PS_2D_SRC_PITCH_PITCH__MASK;
66606438 }
66616439
6662−#define REG_A6XX_SP_PS_2D_SRC_FLAGS_LO 0x0000b4ca
6440+#define REG_A6XX_SP_PS_2D_SRC_PLANE1 0x0000b4c5
6441+#define A6XX_SP_PS_2D_SRC_PLANE1__MASK 0xffffffff
6442+#define A6XX_SP_PS_2D_SRC_PLANE1__SHIFT 0
6443+static inline uint32_t A6XX_SP_PS_2D_SRC_PLANE1(uint32_t val)
6444+{
6445+ return ((val) << A6XX_SP_PS_2D_SRC_PLANE1__SHIFT) & A6XX_SP_PS_2D_SRC_PLANE1__MASK;
6446+}
6447+
6448+#define REG_A6XX_SP_PS_2D_SRC_PLANE_PITCH 0x0000b4c7
6449+#define A6XX_SP_PS_2D_SRC_PLANE_PITCH__MASK 0x00000fff
6450+#define A6XX_SP_PS_2D_SRC_PLANE_PITCH__SHIFT 0
6451+static inline uint32_t A6XX_SP_PS_2D_SRC_PLANE_PITCH(uint32_t val)
6452+{
6453+ return ((val >> 6) << A6XX_SP_PS_2D_SRC_PLANE_PITCH__SHIFT) & A6XX_SP_PS_2D_SRC_PLANE_PITCH__MASK;
6454+}
66636455
6664−#define REG_A6XX_SP_PS_2D_SRC_FLAGS_HI 0x0000b4cb
6456+#define REG_A6XX_SP_PS_2D_SRC_PLANE2 0x0000b4c8
6457+#define A6XX_SP_PS_2D_SRC_PLANE2__MASK 0xffffffff
6458+#define A6XX_SP_PS_2D_SRC_PLANE2__SHIFT 0
6459+static inline uint32_t A6XX_SP_PS_2D_SRC_PLANE2(uint32_t val)
6460+{
6461+ return ((val) << A6XX_SP_PS_2D_SRC_PLANE2__SHIFT) & A6XX_SP_PS_2D_SRC_PLANE2__MASK;
6462+}
66656463
66666464 #define REG_A6XX_SP_PS_2D_SRC_FLAGS 0x0000b4ca
6465+#define A6XX_SP_PS_2D_SRC_FLAGS__MASK 0xffffffff
6466+#define A6XX_SP_PS_2D_SRC_FLAGS__SHIFT 0
6467+static inline uint32_t A6XX_SP_PS_2D_SRC_FLAGS(uint32_t val)
6468+{
6469+ return ((val) << A6XX_SP_PS_2D_SRC_FLAGS__SHIFT) & A6XX_SP_PS_2D_SRC_FLAGS__MASK;
6470+}
66676471
66686472 #define REG_A6XX_SP_PS_2D_SRC_FLAGS_PITCH 0x0000b4cc
6669−#define A6XX_SP_PS_2D_SRC_FLAGS_PITCH_PITCH__MASK 0x000007ff
6670−#define A6XX_SP_PS_2D_SRC_FLAGS_PITCH_PITCH__SHIFT 0
6671−static inline uint32_t A6XX_SP_PS_2D_SRC_FLAGS_PITCH_PITCH(uint32_t val)
6473+#define A6XX_SP_PS_2D_SRC_FLAGS_PITCH__MASK 0x000000ff
6474+#define A6XX_SP_PS_2D_SRC_FLAGS_PITCH__SHIFT 0
6475+static inline uint32_t A6XX_SP_PS_2D_SRC_FLAGS_PITCH(uint32_t val)
6476+{
6477+ return ((val >> 6) << A6XX_SP_PS_2D_SRC_FLAGS_PITCH__SHIFT) & A6XX_SP_PS_2D_SRC_FLAGS_PITCH__MASK;
6478+}
6479+
6480+#define REG_A6XX_SP_PS_UNKNOWN_B4CD 0x0000b4cd
6481+
6482+#define REG_A6XX_SP_PS_UNKNOWN_B4CE 0x0000b4ce
6483+
6484+#define REG_A6XX_SP_PS_UNKNOWN_B4CF 0x0000b4cf
6485+
6486+#define REG_A6XX_SP_PS_UNKNOWN_B4D0 0x0000b4d0
6487+
6488+#define REG_A6XX_SP_WINDOW_OFFSET 0x0000b4d1
6489+#define A6XX_SP_WINDOW_OFFSET_X__MASK 0x00003fff
6490+#define A6XX_SP_WINDOW_OFFSET_X__SHIFT 0
6491+static inline uint32_t A6XX_SP_WINDOW_OFFSET_X(uint32_t val)
6492+{
6493+ return ((val) << A6XX_SP_WINDOW_OFFSET_X__SHIFT) & A6XX_SP_WINDOW_OFFSET_X__MASK;
6494+}
6495+#define A6XX_SP_WINDOW_OFFSET_Y__MASK 0x3fff0000
6496+#define A6XX_SP_WINDOW_OFFSET_Y__SHIFT 16
6497+static inline uint32_t A6XX_SP_WINDOW_OFFSET_Y(uint32_t val)
6498+{
6499+ return ((val) << A6XX_SP_WINDOW_OFFSET_Y__SHIFT) & A6XX_SP_WINDOW_OFFSET_Y__MASK;
6500+}
6501+
6502+#define REG_A6XX_TPL1_UNKNOWN_B600 0x0000b600
6503+
6504+#define REG_A6XX_TPL1_ADDR_MODE_CNTL 0x0000b601
6505+
6506+#define REG_A6XX_TPL1_UNKNOWN_B602 0x0000b602
6507+
6508+#define REG_A6XX_TPL1_NC_MODE_CNTL 0x0000b604
6509+#define A6XX_TPL1_NC_MODE_CNTL_MODE 0x00000001
6510+#define A6XX_TPL1_NC_MODE_CNTL_LOWER_BIT__MASK 0x00000006
6511+#define A6XX_TPL1_NC_MODE_CNTL_LOWER_BIT__SHIFT 1
6512+static inline uint32_t A6XX_TPL1_NC_MODE_CNTL_LOWER_BIT(uint32_t val)
6513+{
6514+ return ((val) << A6XX_TPL1_NC_MODE_CNTL_LOWER_BIT__SHIFT) & A6XX_TPL1_NC_MODE_CNTL_LOWER_BIT__MASK;
6515+}
6516+#define A6XX_TPL1_NC_MODE_CNTL_MIN_ACCESS_LENGTH 0x00000008
6517+#define A6XX_TPL1_NC_MODE_CNTL_UPPER_BIT__MASK 0x00000010
6518+#define A6XX_TPL1_NC_MODE_CNTL_UPPER_BIT__SHIFT 4
6519+static inline uint32_t A6XX_TPL1_NC_MODE_CNTL_UPPER_BIT(uint32_t val)
66726520 {
6673− return ((val >> 6) << A6XX_SP_PS_2D_SRC_FLAGS_PITCH_PITCH__SHIFT) & A6XX_SP_PS_2D_SRC_FLAGS_PITCH_PITCH__MASK;
6521+ return ((val) << A6XX_TPL1_NC_MODE_CNTL_UPPER_BIT__SHIFT) & A6XX_TPL1_NC_MODE_CNTL_UPPER_BIT__MASK;
66746522 }
6675−#define A6XX_SP_PS_2D_SRC_FLAGS_PITCH_ARRAY_PITCH__MASK 0x003ff800
6676−#define A6XX_SP_PS_2D_SRC_FLAGS_PITCH_ARRAY_PITCH__SHIFT 11
6677−static inline uint32_t A6XX_SP_PS_2D_SRC_FLAGS_PITCH_ARRAY_PITCH(uint32_t val)
6523+#define A6XX_TPL1_NC_MODE_CNTL_UNK6__MASK 0x000000c0
6524+#define A6XX_TPL1_NC_MODE_CNTL_UNK6__SHIFT 6
6525+static inline uint32_t A6XX_TPL1_NC_MODE_CNTL_UNK6(uint32_t val)
66786526 {
6679− return ((val >> 7) << A6XX_SP_PS_2D_SRC_FLAGS_PITCH_ARRAY_PITCH__SHIFT) & A6XX_SP_PS_2D_SRC_FLAGS_PITCH_ARRAY_PITCH__MASK;
6527+ return ((val) << A6XX_TPL1_NC_MODE_CNTL_UNK6__SHIFT) & A6XX_TPL1_NC_MODE_CNTL_UNK6__MASK;
66806528 }
66816529
6682−#define REG_A6XX_SP_UNKNOWN_B600 0x0000b600
6530+#define REG_A6XX_TPL1_UNKNOWN_B605 0x0000b605
6531+
6532+#define REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_0 0x0000b608
6533+
6534+#define REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_1 0x0000b609
6535+
6536+#define REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_2 0x0000b60a
6537+
6538+#define REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_3 0x0000b60b
6539+
6540+#define REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_4 0x0000b60c
66836541
6684−#define REG_A6XX_SP_UNKNOWN_B605 0x0000b605
6542+static inline uint32_t REG_A6XX_TPL1_PERFCTR_TP_SEL(uint32_t i0) { return 0x0000b610 + 0x1*i0; }
66856543
66866544 #define REG_A6XX_HLSQ_VS_CNTL 0x0000b800
66876545 #define A6XX_HLSQ_VS_CNTL_CONSTLEN__MASK 0x000000ff
@@ -6722,10 +6580,31 @@ static inline uint32_t A6XX_HLSQ_GS_CNTL_CONSTLEN(uint32_t val) · 34 unmodified lines
67226580 #define REG_A6XX_HLSQ_LOAD_STATE_GEOM_CMD 0x0000b820
67236581
67246582 #define REG_A6XX_HLSQ_LOAD_STATE_GEOM_EXT_SRC_ADDR 0x0000b821
6583+#define A6XX_HLSQ_LOAD_STATE_GEOM_EXT_SRC_ADDR__MASK 0xffffffff
6584+#define A6XX_HLSQ_LOAD_STATE_GEOM_EXT_SRC_ADDR__SHIFT 0
6585+static inline uint32_t A6XX_HLSQ_LOAD_STATE_GEOM_EXT_SRC_ADDR(uint32_t val)
6586+{
6587+ return ((val) << A6XX_HLSQ_LOAD_STATE_GEOM_EXT_SRC_ADDR__SHIFT) & A6XX_HLSQ_LOAD_STATE_GEOM_EXT_SRC_ADDR__MASK;
6588+}
67256589
67266590 #define REG_A6XX_HLSQ_LOAD_STATE_GEOM_DATA 0x0000b823
67276591
6728−#define REG_A6XX_HLSQ_UNKNOWN_B980 0x0000b980
6592+#define REG_A6XX_HLSQ_FS_CNTL_0 0x0000b980
6593+#define A6XX_HLSQ_FS_CNTL_0_THREADSIZE__MASK 0x00000001
6594+#define A6XX_HLSQ_FS_CNTL_0_THREADSIZE__SHIFT 0
6595+static inline uint32_t A6XX_HLSQ_FS_CNTL_0_THREADSIZE(enum a6xx_threadsize val)
6596+{
6597+ return ((val) << A6XX_HLSQ_FS_CNTL_0_THREADSIZE__SHIFT) & A6XX_HLSQ_FS_CNTL_0_THREADSIZE__MASK;
6598+}
6599+#define A6XX_HLSQ_FS_CNTL_0_VARYINGS 0x00000002
6600+#define A6XX_HLSQ_FS_CNTL_0_UNK2__MASK 0x00000ffc
6601+#define A6XX_HLSQ_FS_CNTL_0_UNK2__SHIFT 2
6602+static inline uint32_t A6XX_HLSQ_FS_CNTL_0_UNK2(uint32_t val)
6603+{
6604+ return ((val) << A6XX_HLSQ_FS_CNTL_0_UNK2__SHIFT) & A6XX_HLSQ_FS_CNTL_0_UNK2__MASK;
6605+}
6606+
6607+#define REG_A6XX_HLSQ_UNKNOWN_B981 0x0000b981
67296608
67306609 #define REG_A6XX_HLSQ_CONTROL_1_REG 0x0000b982
67316610
@@ -6808,6 +6687,18 @@ static inline uint32_t A6XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID(uint32_t val) · 76 unmodified lines
68086687 }
68096688
68106689 #define REG_A6XX_HLSQ_CONTROL_5_REG 0x0000b986
6690+#define A6XX_HLSQ_CONTROL_5_REG_UNK0__MASK 0x000000ff
6691+#define A6XX_HLSQ_CONTROL_5_REG_UNK0__SHIFT 0
6692+static inline uint32_t A6XX_HLSQ_CONTROL_5_REG_UNK0(uint32_t val)
6693+{
6694+ return ((val) << A6XX_HLSQ_CONTROL_5_REG_UNK0__SHIFT) & A6XX_HLSQ_CONTROL_5_REG_UNK0__MASK;
6695+}
6696+#define A6XX_HLSQ_CONTROL_5_REG_UNK8__MASK 0x0000ff00
6697+#define A6XX_HLSQ_CONTROL_5_REG_UNK8__SHIFT 8
6698+static inline uint32_t A6XX_HLSQ_CONTROL_5_REG_UNK8(uint32_t val)
6699+{
6700+ return ((val) << A6XX_HLSQ_CONTROL_5_REG_UNK8__SHIFT) & A6XX_HLSQ_CONTROL_5_REG_UNK8__MASK;
6701+}
68116702
68126703 #define REG_A6XX_HLSQ_CS_CNTL 0x0000b987
68136704 #define A6XX_HLSQ_CS_CNTL_CONSTLEN__MASK 0x000000ff
@@ -6899,17 +6790,17 @@ static inline uint32_t A6XX_HLSQ_CS_CNTL_0_WGIDCONSTID(uint32_t val) · 85 unmodified lines
68996790 {
69006791 return ((val) << A6XX_HLSQ_CS_CNTL_0_WGIDCONSTID__SHIFT) & A6XX_HLSQ_CS_CNTL_0_WGIDCONSTID__MASK;
69016792 }
6902−#define A6XX_HLSQ_CS_CNTL_0_UNK0__MASK 0x0000ff00
6903−#define A6XX_HLSQ_CS_CNTL_0_UNK0__SHIFT 8
6904−static inline uint32_t A6XX_HLSQ_CS_CNTL_0_UNK0(uint32_t val)
6793+#define A6XX_HLSQ_CS_CNTL_0_WGSIZECONSTID__MASK 0x0000ff00
6794+#define A6XX_HLSQ_CS_CNTL_0_WGSIZECONSTID__SHIFT 8
6795+static inline uint32_t A6XX_HLSQ_CS_CNTL_0_WGSIZECONSTID(uint32_t val)
69056796 {
6906− return ((val) << A6XX_HLSQ_CS_CNTL_0_UNK0__SHIFT) & A6XX_HLSQ_CS_CNTL_0_UNK0__MASK;
6797+ return ((val) << A6XX_HLSQ_CS_CNTL_0_WGSIZECONSTID__SHIFT) & A6XX_HLSQ_CS_CNTL_0_WGSIZECONSTID__MASK;
69076798 }
6908−#define A6XX_HLSQ_CS_CNTL_0_UNK1__MASK 0x00ff0000
6909−#define A6XX_HLSQ_CS_CNTL_0_UNK1__SHIFT 16
6910−static inline uint32_t A6XX_HLSQ_CS_CNTL_0_UNK1(uint32_t val)
6799+#define A6XX_HLSQ_CS_CNTL_0_WGOFFSETCONSTID__MASK 0x00ff0000
6800+#define A6XX_HLSQ_CS_CNTL_0_WGOFFSETCONSTID__SHIFT 16
6801+static inline uint32_t A6XX_HLSQ_CS_CNTL_0_WGOFFSETCONSTID(uint32_t val)
69116802 {
6912− return ((val) << A6XX_HLSQ_CS_CNTL_0_UNK1__SHIFT) & A6XX_HLSQ_CS_CNTL_0_UNK1__MASK;
6803+ return ((val) << A6XX_HLSQ_CS_CNTL_0_WGOFFSETCONSTID__SHIFT) & A6XX_HLSQ_CS_CNTL_0_WGOFFSETCONSTID__MASK;
69136804 }
69146805 #define A6XX_HLSQ_CS_CNTL_0_LOCALIDREGID__MASK 0xff000000
69156806 #define A6XX_HLSQ_CS_CNTL_0_LOCALIDREGID__SHIFT 24
@@ -6918,7 +6809,21 @@ static inline uint32_t A6XX_HLSQ_CS_CNTL_0_LOCALIDREGID(uint32_t val) · 2 unmodified lines
69186809 return ((val) << A6XX_HLSQ_CS_CNTL_0_LOCALIDREGID__SHIFT) & A6XX_HLSQ_CS_CNTL_0_LOCALIDREGID__MASK;
69196810 }
69206811
6921−#define REG_A6XX_HLSQ_CS_UNKNOWN_B998 0x0000b998
6812+#define REG_A6XX_HLSQ_CS_CNTL_1 0x0000b998
6813+#define A6XX_HLSQ_CS_CNTL_1_LINEARLOCALIDREGID__MASK 0x000000ff
6814+#define A6XX_HLSQ_CS_CNTL_1_LINEARLOCALIDREGID__SHIFT 0
6815+static inline uint32_t A6XX_HLSQ_CS_CNTL_1_LINEARLOCALIDREGID(uint32_t val)
6816+{
6817+ return ((val) << A6XX_HLSQ_CS_CNTL_1_LINEARLOCALIDREGID__SHIFT) & A6XX_HLSQ_CS_CNTL_1_LINEARLOCALIDREGID__MASK;
6818+}
6819+#define A6XX_HLSQ_CS_CNTL_1_SINGLE_SP_CORE 0x00000100
6820+#define A6XX_HLSQ_CS_CNTL_1_THREADSIZE__MASK 0x00000200
6821+#define A6XX_HLSQ_CS_CNTL_1_THREADSIZE__SHIFT 9
6822+static inline uint32_t A6XX_HLSQ_CS_CNTL_1_THREADSIZE(enum a6xx_threadsize val)
6823+{
6824+ return ((val) << A6XX_HLSQ_CS_CNTL_1_THREADSIZE__SHIFT) & A6XX_HLSQ_CS_CNTL_1_THREADSIZE__MASK;
6825+}
6826+#define A6XX_HLSQ_CS_CNTL_1_THREADSIZE_SCALAR 0x00000400
69226827
69236828 #define REG_A6XX_HLSQ_CS_KERNEL_GROUP_X 0x0000b999
69246829
@@ -6929,6 +6834,12 @@ static inline uint32_t A6XX_HLSQ_CS_CNTL_0_LOCALIDREGID(uint32_t val) · 4 unmodified lines
69296834 #define REG_A6XX_HLSQ_LOAD_STATE_FRAG_CMD 0x0000b9a0
69306835
69316836 #define REG_A6XX_HLSQ_LOAD_STATE_FRAG_EXT_SRC_ADDR 0x0000b9a1
6837+#define A6XX_HLSQ_LOAD_STATE_FRAG_EXT_SRC_ADDR__MASK 0xffffffff
6838+#define A6XX_HLSQ_LOAD_STATE_FRAG_EXT_SRC_ADDR__SHIFT 0
6839+static inline uint32_t A6XX_HLSQ_LOAD_STATE_FRAG_EXT_SRC_ADDR(uint32_t val)
6840+{
6841+ return ((val) << A6XX_HLSQ_LOAD_STATE_FRAG_EXT_SRC_ADDR__SHIFT) & A6XX_HLSQ_LOAD_STATE_FRAG_EXT_SRC_ADDR__MASK;
6842+}
69326843
69336844 #define REG_A6XX_HLSQ_LOAD_STATE_FRAG_DATA 0x0000b9a3
69346845
@@ -7026,6 +6937,12 @@ static inline uint32_t A6XX_HLSQ_2D_EVENT_CMD_EVENT(enum vgt_event_type val) · 91 unmodified lines
70266937
70276938 #define REG_A6XX_HLSQ_UNKNOWN_BE04 0x0000be04
70286939
6940+#define REG_A6XX_HLSQ_ADDR_MODE_CNTL 0x0000be05
6941+
6942+#define REG_A6XX_HLSQ_UNKNOWN_BE08 0x0000be08
6943+
6944+static inline uint32_t REG_A6XX_HLSQ_PERFCTR_HLSQ_SEL(uint32_t i0) { return 0x0000be10 + 0x1*i0; }
6945+
70296946 #define REG_A6XX_CP_EVENT_START 0x0000d600
70306947 #define A6XX_CP_EVENT_START_STATE_ID__MASK 0x000000ff
70316948 #define A6XX_CP_EVENT_START_STATE_ID__SHIFT 0
@@ -7135,11 +7052,11 @@ static inline uint32_t A6XX_TEX_SAMP_2_REDUCTION_MODE(enum a6xx_reduction_mode v · 103 unmodified lines
71357052 return ((val) << A6XX_TEX_SAMP_2_REDUCTION_MODE__SHIFT) & A6XX_TEX_SAMP_2_REDUCTION_MODE__MASK;
71367053 }
71377054 #define A6XX_TEX_SAMP_2_CHROMA_LINEAR 0x00000020
7138−#define A6XX_TEX_SAMP_2_BCOLOR_OFFSET__MASK 0xffffff80
7139−#define A6XX_TEX_SAMP_2_BCOLOR_OFFSET__SHIFT 7
7140−static inline uint32_t A6XX_TEX_SAMP_2_BCOLOR_OFFSET(uint32_t val)
7055+#define A6XX_TEX_SAMP_2_BCOLOR__MASK 0xffffff80
7056+#define A6XX_TEX_SAMP_2_BCOLOR__SHIFT 7
7057+static inline uint32_t A6XX_TEX_SAMP_2_BCOLOR(uint32_t val)
71417058 {
7142− return ((val >> 7) << A6XX_TEX_SAMP_2_BCOLOR_OFFSET__SHIFT) & A6XX_TEX_SAMP_2_BCOLOR_OFFSET__MASK;
7059+ return ((val) << A6XX_TEX_SAMP_2_BCOLOR__SHIFT) & A6XX_TEX_SAMP_2_BCOLOR__MASK;
71437060 }
71447061
71457062 #define REG_A6XX_TEX_SAMP_3 0x00000003
drivers/gpu/drm/msm/adreno/a6xx_gmu.c+42−13
@@ -512,19 +512,26 @@ static void a6xx_gmu_rpmh_init(struct a6xx_gmu *gmu) · 511 unmodified lines
512512 struct adreno_gpu *adreno_gpu = &a6xx_gpu->base;
513513 struct platform_device *pdev = to_platform_device(gmu->dev);
514514 void __iomem *pdcptr = a6xx_gmu_get_mmio(pdev, "gmu_pdc");
515− void __iomem *seqptr = a6xx_gmu_get_mmio(pdev, "gmu_pdc_seq");
515+ void __iomem *seqptr;
516516 uint32_t pdc_address_offset;
517+ bool pdc_in_aop = false;
517518
518− if (!pdcptr || !seqptr)
519+ if (!pdcptr)
519520 goto err;
520521
521− if (adreno_is_a618(adreno_gpu) || adreno_is_a640(adreno_gpu))
522+ if (adreno_is_a650(adreno_gpu) || adreno_is_a660(adreno_gpu))
523+ pdc_in_aop = true;
524+ else if (adreno_is_a618(adreno_gpu) || adreno_is_a640(adreno_gpu))
522525 pdc_address_offset = 0x30090;
523− else if (adreno_is_a650(adreno_gpu))
524− pdc_address_offset = 0x300a0;
525526 else
526527 pdc_address_offset = 0x30080;
527528
529+ if (!pdc_in_aop) {
530+ seqptr = a6xx_gmu_get_mmio(pdev, "gmu_pdc_seq");
531+ if (!seqptr)
532+ goto err;
533+ }
534+
528535 /* Disable SDE clock gating */
529536 gmu_write_rscc(gmu, REG_A6XX_GPU_RSCC_RSC_STATUS0_DRV0, BIT(24));
530537
@@ -542,7 +549,7 @@ static void a6xx_gmu_rpmh_init(struct a6xx_gmu *gmu) · 11 unmodified lines
542549 gmu_write_rscc(gmu, REG_A6XX_RSCC_PDC_MATCH_VALUE_HI, 0x4514);
543550
544551 /* Load RSC sequencer uCode for sleep and wakeup */
545− if (adreno_is_a650(adreno_gpu)) {
552+ if (adreno_is_a650_family(adreno_gpu)) {
546553 gmu_write_rscc(gmu, REG_A6XX_RSCC_SEQ_MEM_0_DRV0, 0xeaaae5a0);
547554 gmu_write_rscc(gmu, REG_A6XX_RSCC_SEQ_MEM_0_DRV0 + 1, 0xe1a1ebab);
548555 gmu_write_rscc(gmu, REG_A6XX_RSCC_SEQ_MEM_0_DRV0 + 2, 0xa2e0a581);
@@ -556,6 +563,9 @@ static void a6xx_gmu_rpmh_init(struct a6xx_gmu *gmu) · 7 unmodified lines
556563 gmu_write_rscc(gmu, REG_A6XX_RSCC_SEQ_MEM_0_DRV0 + 4, 0x0020e8a8);
557564 }
558565
566+ if (pdc_in_aop)
567+ goto setup_pdc;
568+
559569 /* Load PDC sequencer uCode for power up and power down sequence */
560570 pdc_write(seqptr, REG_A6XX_PDC_GPU_SEQ_MEM_0, 0xfebea1e1);
561571 pdc_write(seqptr, REG_A6XX_PDC_GPU_SEQ_MEM_0 + 1, 0xa5a4a3a2);
@@ -587,7 +597,7 @@ static void a6xx_gmu_rpmh_init(struct a6xx_gmu *gmu) · 25 unmodified lines
587597
588598 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_MSGID + 4, 0x10108);
589599 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_ADDR + 4, 0x30000);
590− if (adreno_is_a618(adreno_gpu) || adreno_is_a650(adreno_gpu))
600+ if (adreno_is_a618(adreno_gpu) || adreno_is_a650_family(adreno_gpu))
591601 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_DATA + 4, 0x2);
592602 else
593603 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_DATA + 4, 0x3);
@@ -596,6 +606,7 @@ static void a6xx_gmu_rpmh_init(struct a6xx_gmu *gmu) · 2 unmodified lines
596606 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_DATA + 8, 0x3);
597607
598608 /* Setup GPU PDC */
609+setup_pdc:
599610 pdc_write(pdcptr, REG_A6XX_PDC_GPU_SEQ_START_ADDR, 0);
600611 pdc_write(pdcptr, REG_A6XX_PDC_GPU_ENABLE_PDC, 0x80000001);
601612
@@ -687,7 +698,7 @@ static int a6xx_gmu_fw_load(struct a6xx_gmu *gmu) · 85 unmodified lines
687698 u32 itcm_base = 0x00000000;
688699 u32 dtcm_base = 0x00040000;
689700
690− if (adreno_is_a650(adreno_gpu))
701+ if (adreno_is_a650_family(adreno_gpu))
691702 dtcm_base = 0x10004000;
692703
693704 if (gmu->legacy) {
@@ -740,8 +751,10 @@ static int a6xx_gmu_fw_start(struct a6xx_gmu *gmu, unsigned int state) · 46 unmodified lines
740751 int ret;
741752 u32 chipid;
742753
743− if (adreno_is_a650(adreno_gpu))
754+ if (adreno_is_a650_family(adreno_gpu)) {
755+ gmu_write(gmu, REG_A6XX_GPU_GMU_CX_GMU_CX_FALNEXT_INTF, 1);
744756 gmu_write(gmu, REG_A6XX_GPU_GMU_CX_GMU_CX_FAL_INTF, 1);
757+ }
745758
746759 if (state == GMU_WARM_BOOT) {
747760 ret = a6xx_rpmh_start(gmu);
@@ -1346,7 +1359,7 @@ static int a6xx_gmu_pwrlevels_probe(struct a6xx_gmu *gmu) · 598 unmodified lines
13461359 * The GMU handles its own frequency switching so build a list of
13471360 * available frequencies to send during initialization
13481361 */
1349− ret = dev_pm_opp_of_add_table(gmu->dev);
1362+ ret = devm_pm_opp_of_add_table(gmu->dev);
13501363 if (ret) {
13511364 DRM_DEV_ERROR(gmu->dev, "Unable to set the OPP table for the GMU\n");
13521365 return ret;
@@ -1483,12 +1496,28 @@ int a6xx_gmu_init(struct a6xx_gpu *a6xx_gpu, struct device_node *node) · 130 unmodified lines
14831496 if (ret)
14841497 goto err_put_device;
14851498
1499+
1500+ /* A660 now requires handling "prealloc requests" in GMU firmware
1501+ * For now just hardcode allocations based on the known firmware.
1502+ * note: there is no indication that these correspond to "dummy" or
1503+ * "debug" regions, but this "guess" allows reusing these BOs which
1504+ * are otherwise unused by a660.
1505+ */
1506+ gmu->dummy.size = SZ_4K;
1507+ if (adreno_is_a660(adreno_gpu)) {
1508+ ret = a6xx_gmu_memory_alloc(gmu, &gmu->debug, SZ_4K * 7, 0x60400000);
1509+ if (ret)
1510+ goto err_memory;
1511+
1512+ gmu->dummy.size = SZ_8K;
1513+ }
1514+
14861515 /* Allocate memory for the GMU dummy page */
1487− ret = a6xx_gmu_memory_alloc(gmu, &gmu->dummy, SZ_4K, 0x60000000);
1516+ ret = a6xx_gmu_memory_alloc(gmu, &gmu->dummy, gmu->dummy.size, 0x60000000);
14881517 if (ret)
14891518 goto err_memory;
14901519
1491− if (adreno_is_a650(adreno_gpu)) {
1520+ if (adreno_is_a650_family(adreno_gpu)) {
14921521 ret = a6xx_gmu_memory_alloc(gmu, &gmu->icache,
14931522 SZ_16M - SZ_16K, 0x04000);
14941523 if (ret)
@@ -1530,7 +1559,7 @@ int a6xx_gmu_init(struct a6xx_gpu *a6xx_gpu, struct device_node *node) · 35 unmodified lines
15301559 goto err_memory;
15311560 }
15321561
1533− if (adreno_is_a650(adreno_gpu)) {
1562+ if (adreno_is_a650_family(adreno_gpu)) {
15341563 gmu->rscc = a6xx_gmu_get_mmio(pdev, "rscc");
15351564 if (IS_ERR(gmu->rscc))
15361565 goto err_mmio;
drivers/gpu/drm/msm/adreno/a6xx_gmu.xml.h+19−15
@@ -8,21 +8,21 @@ http://github.com/freedreno/envytools/ · 7 unmodified lines
88 git clone https://github.com/freedreno/envytools.git
99
1010 The rules-ng-ng source files this header was generated from are:
11−- /home/robclark/src/envytools/rnndb/adreno.xml ( 594 bytes, from 2020-07-23 21:58:14)
12−- /home/robclark/src/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2020-07-23 21:58:14)
13−- /home/robclark/src/envytools/rnndb/adreno/a2xx.xml ( 90159 bytes, from 2020-07-23 21:58:14)
14−- /home/robclark/src/envytools/rnndb/adreno/adreno_common.xml ( 14386 bytes, from 2020-07-23 21:58:14)
15−- /home/robclark/src/envytools/rnndb/adreno/adreno_pm4.xml ( 65048 bytes, from 2020-07-23 21:58:14)
16−- /home/robclark/src/envytools/rnndb/adreno/a3xx.xml ( 84226 bytes, from 2020-07-23 21:58:14)
17−- /home/robclark/src/envytools/rnndb/adreno/a4xx.xml ( 112556 bytes, from 2020-07-23 21:58:14)
18−- /home/robclark/src/envytools/rnndb/adreno/a5xx.xml ( 149461 bytes, from 2020-07-23 21:58:14)
19−- /home/robclark/src/envytools/rnndb/adreno/a6xx.xml ( 184695 bytes, from 2020-07-23 21:58:14)
20−- /home/robclark/src/envytools/rnndb/adreno/a6xx_gmu.xml ( 11218 bytes, from 2020-07-23 21:58:14)
21−- /home/robclark/src/envytools/rnndb/adreno/ocmem.xml ( 1773 bytes, from 2020-07-23 21:58:14)
22−- /home/robclark/src/envytools/rnndb/adreno/adreno_control_regs.xml ( 4559 bytes, from 2020-07-23 21:58:14)
23−- /home/robclark/src/envytools/rnndb/adreno/adreno_pipe_regs.xml ( 2872 bytes, from 2020-07-23 21:58:14)
24−
25−Copyright (C) 2013-2020 by the following authors:
11+- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno.xml ( 594 bytes, from 2021-02-18 16:45:44)
12+- /home/robclark/src/mesa/mesa/src/freedreno/registers/freedreno_copyright.xml ( 1572 bytes, from 2021-02-18 16:45:44)
13+- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a2xx.xml ( 90810 bytes, from 2021-02-18 16:45:44)
14+- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_common.xml ( 14386 bytes, from 2021-02-18 16:45:44)
15+- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_pm4.xml ( 67699 bytes, from 2021-05-31 20:21:57)
16+- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a3xx.xml ( 84226 bytes, from 2021-02-18 16:45:44)
17+- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a4xx.xml ( 112551 bytes, from 2021-02-18 16:45:44)
18+- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a5xx.xml ( 150713 bytes, from 2021-06-10 22:34:02)
19+- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a6xx.xml ( 180049 bytes, from 2021-06-02 21:44:19)
20+- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a6xx_gmu.xml ( 11331 bytes, from 2021-05-21 19:18:08)
21+- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/ocmem.xml ( 1773 bytes, from 2021-02-18 16:45:44)
22+- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_control_regs.xml ( 6038 bytes, from 2021-05-27 20:22:36)
23+- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_pipe_regs.xml ( 2924 bytes, from 2021-05-27 20:18:13)
24+
25+Copyright (C) 2013-2021 by the following authors:
2626 - Rob Clark <robdclark@gmail.com> (robclark)
2727 - Ilia Mirkin <imirkin@alum.mit.edu> (imirkin)
2828
@@ -292,6 +292,8 @@ static inline uint32_t A6XX_GMU_GPU_NAP_CTRL_SID(uint32_t val) · 263 unmodified lines
292292
293293 #define REG_A6XX_GPU_GMU_CX_GMU_CX_FAL_INTF 0x000050f0
294294
295+#define REG_A6XX_GPU_GMU_CX_GMU_CX_FALNEXT_INTF 0x000050f1
296+
295297 #define REG_A6XX_GPU_GMU_CX_GMU_PWR_COL_CP_MSG 0x00005100
296298
297299 #define REG_A6XX_GPU_GMU_CX_GMU_PWR_COL_CP_RESP 0x00005101
@@ -439,6 +441,8 @@ static inline uint32_t A6XX_GMU_GPU_NAP_CTRL_SID(uint32_t val) · 141 unmodified lines
439441
440442 #define REG_A6XX_GPU_CC_GX_DOMAIN_MISC 0x00009d42
441443
444+#define REG_A6XX_GPU_CPR_FSM_CTL 0x0000c001
445+
442446 #define REG_A6XX_GPU_RSCC_RSC_STATUS0_DRV0 0x00000004
443447
444448 #define REG_A6XX_RSCC_PDC_SEQ_START_ADDR 0x00000008
drivers/gpu/drm/msm/adreno/a6xx_gpu.c+258−47
@@ -149,7 +149,7 @@ static void a6xx_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit) · 148 unmodified lines
149149
150150 a6xx_set_pagetable(a6xx_gpu, ring, submit->queue->ctx);
151151
152− get_stats_counter(ring, REG_A6XX_RBBM_PERFCTR_CP_0_LO,
152+ get_stats_counter(ring, REG_A6XX_RBBM_PERFCTR_CP(0),
153153 rbmemptr_stats(ring, index, cpcycles_start));
154154
155155 /*
@@ -185,7 +185,7 @@ static void a6xx_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit) · 29 unmodified lines
185185 }
186186 }
187187
188− get_stats_counter(ring, REG_A6XX_RBBM_PERFCTR_CP_0_LO,
188+ get_stats_counter(ring, REG_A6XX_RBBM_PERFCTR_CP(0),
189189 rbmemptr_stats(ring, index, cpcycles_end));
190190 get_stats_counter(ring, REG_A6XX_CP_ALWAYS_ON_COUNTER_LO,
191191 rbmemptr_stats(ring, index, alwayson_end));
@@ -427,6 +427,59 @@ const struct adreno_reglist a650_hwcg[] = { · 235 unmodified lines
427427 {},
428428 };
429429
430+const struct adreno_reglist a660_hwcg[] = {
431+ {REG_A6XX_RBBM_CLOCK_CNTL_SP0, 0x02222222},
432+ {REG_A6XX_RBBM_CLOCK_CNTL2_SP0, 0x02222220},
433+ {REG_A6XX_RBBM_CLOCK_DELAY_SP0, 0x00000080},
434+ {REG_A6XX_RBBM_CLOCK_HYST_SP0, 0x0000F3CF},
435+ {REG_A6XX_RBBM_CLOCK_CNTL_TP0, 0x22222222},
436+ {REG_A6XX_RBBM_CLOCK_CNTL2_TP0, 0x22222222},
437+ {REG_A6XX_RBBM_CLOCK_CNTL3_TP0, 0x22222222},
438+ {REG_A6XX_RBBM_CLOCK_CNTL4_TP0, 0x00022222},
439+ {REG_A6XX_RBBM_CLOCK_DELAY_TP0, 0x11111111},
440+ {REG_A6XX_RBBM_CLOCK_DELAY2_TP0, 0x11111111},
441+ {REG_A6XX_RBBM_CLOCK_DELAY3_TP0, 0x11111111},
442+ {REG_A6XX_RBBM_CLOCK_DELAY4_TP0, 0x00011111},
443+ {REG_A6XX_RBBM_CLOCK_HYST_TP0, 0x77777777},
444+ {REG_A6XX_RBBM_CLOCK_HYST2_TP0, 0x77777777},
445+ {REG_A6XX_RBBM_CLOCK_HYST3_TP0, 0x77777777},
446+ {REG_A6XX_RBBM_CLOCK_HYST4_TP0, 0x00077777},
447+ {REG_A6XX_RBBM_CLOCK_CNTL_RB0, 0x22222222},
448+ {REG_A6XX_RBBM_CLOCK_CNTL2_RB0, 0x01002222},
449+ {REG_A6XX_RBBM_CLOCK_CNTL_CCU0, 0x00002220},
450+ {REG_A6XX_RBBM_CLOCK_HYST_RB_CCU0, 0x00040F00},
451+ {REG_A6XX_RBBM_CLOCK_CNTL_RAC, 0x25222022},
452+ {REG_A6XX_RBBM_CLOCK_CNTL2_RAC, 0x00005555},
453+ {REG_A6XX_RBBM_CLOCK_DELAY_RAC, 0x00000011},
454+ {REG_A6XX_RBBM_CLOCK_HYST_RAC, 0x00445044},
455+ {REG_A6XX_RBBM_CLOCK_CNTL_TSE_RAS_RBBM, 0x04222222},
456+ {REG_A6XX_RBBM_CLOCK_MODE_VFD, 0x00002222},
457+ {REG_A6XX_RBBM_CLOCK_MODE_GPC, 0x00222222},
458+ {REG_A6XX_RBBM_CLOCK_DELAY_HLSQ_2, 0x00000002},
459+ {REG_A6XX_RBBM_CLOCK_MODE_HLSQ, 0x00002222},
460+ {REG_A6XX_RBBM_CLOCK_DELAY_TSE_RAS_RBBM, 0x00004000},
461+ {REG_A6XX_RBBM_CLOCK_DELAY_VFD, 0x00002222},
462+ {REG_A6XX_RBBM_CLOCK_DELAY_GPC, 0x00000200},
463+ {REG_A6XX_RBBM_CLOCK_DELAY_HLSQ, 0x00000000},
464+ {REG_A6XX_RBBM_CLOCK_HYST_TSE_RAS_RBBM, 0x00000000},
465+ {REG_A6XX_RBBM_CLOCK_HYST_VFD, 0x00000000},
466+ {REG_A6XX_RBBM_CLOCK_HYST_GPC, 0x04104004},
467+ {REG_A6XX_RBBM_CLOCK_HYST_HLSQ, 0x00000000},
468+ {REG_A6XX_RBBM_CLOCK_CNTL_TEX_FCHE, 0x00000222},
469+ {REG_A6XX_RBBM_CLOCK_DELAY_TEX_FCHE, 0x00000111},
470+ {REG_A6XX_RBBM_CLOCK_HYST_TEX_FCHE, 0x00000000},
471+ {REG_A6XX_RBBM_CLOCK_CNTL_UCHE, 0x22222222},
472+ {REG_A6XX_RBBM_CLOCK_HYST_UCHE, 0x00000004},
473+ {REG_A6XX_RBBM_CLOCK_DELAY_UCHE, 0x00000002},
474+ {REG_A6XX_RBBM_ISDB_CNT, 0x00000182},
475+ {REG_A6XX_RBBM_RAC_THRESHOLD_CNT, 0x00000000},
476+ {REG_A6XX_RBBM_SP_HYST_CNT, 0x00000000},
477+ {REG_A6XX_RBBM_CLOCK_CNTL_GMU_GX, 0x00000222},
478+ {REG_A6XX_RBBM_CLOCK_DELAY_GMU_GX, 0x00000111},
479+ {REG_A6XX_RBBM_CLOCK_HYST_GMU_GX, 0x00000555},
480+ {},
481+};
482+
430483 static void a6xx_set_hwcg(struct msm_gpu *gpu, bool state)
431484 {
432485 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
@@ -541,6 +594,51 @@ static const u32 a650_protect[] = { · 108 unmodified lines
541594 A6XX_PROTECT_NORDWR(0x1f8c0, 0x0000), /* note: infinite range */
542595 };
543596
597+/* These are for a635 and a660 */
598+static const u32 a660_protect[] = {
599+ A6XX_PROTECT_RDONLY(0x00000, 0x04ff),
600+ A6XX_PROTECT_RDONLY(0x00501, 0x0005),
601+ A6XX_PROTECT_RDONLY(0x0050b, 0x02f4),
602+ A6XX_PROTECT_NORDWR(0x0050e, 0x0000),
603+ A6XX_PROTECT_NORDWR(0x00510, 0x0000),
604+ A6XX_PROTECT_NORDWR(0x00534, 0x0000),
605+ A6XX_PROTECT_NORDWR(0x00800, 0x0082),
606+ A6XX_PROTECT_NORDWR(0x008a0, 0x0008),
607+ A6XX_PROTECT_NORDWR(0x008ab, 0x0024),
608+ A6XX_PROTECT_RDONLY(0x008de, 0x00ae),
609+ A6XX_PROTECT_NORDWR(0x00900, 0x004d),
610+ A6XX_PROTECT_NORDWR(0x0098d, 0x0272),
611+ A6XX_PROTECT_NORDWR(0x00e00, 0x0001),
612+ A6XX_PROTECT_NORDWR(0x00e03, 0x000c),
613+ A6XX_PROTECT_NORDWR(0x03c00, 0x00c3),
614+ A6XX_PROTECT_RDONLY(0x03cc4, 0x1fff),
615+ A6XX_PROTECT_NORDWR(0x08630, 0x01cf),
616+ A6XX_PROTECT_NORDWR(0x08e00, 0x0000),
617+ A6XX_PROTECT_NORDWR(0x08e08, 0x0000),
618+ A6XX_PROTECT_NORDWR(0x08e50, 0x001f),
619+ A6XX_PROTECT_NORDWR(0x08e80, 0x027f),
620+ A6XX_PROTECT_NORDWR(0x09624, 0x01db),
621+ A6XX_PROTECT_NORDWR(0x09e60, 0x0011),
622+ A6XX_PROTECT_NORDWR(0x09e78, 0x0187),
623+ A6XX_PROTECT_NORDWR(0x0a630, 0x01cf),
624+ A6XX_PROTECT_NORDWR(0x0ae02, 0x0000),
625+ A6XX_PROTECT_NORDWR(0x0ae50, 0x012f),
626+ A6XX_PROTECT_NORDWR(0x0b604, 0x0000),
627+ A6XX_PROTECT_NORDWR(0x0b608, 0x0006),
628+ A6XX_PROTECT_NORDWR(0x0be02, 0x0001),
629+ A6XX_PROTECT_NORDWR(0x0be20, 0x015f),
630+ A6XX_PROTECT_NORDWR(0x0d000, 0x05ff),
631+ A6XX_PROTECT_NORDWR(0x0f000, 0x0bff),
632+ A6XX_PROTECT_RDONLY(0x0fc00, 0x1fff),
633+ A6XX_PROTECT_NORDWR(0x18400, 0x1fff),
634+ A6XX_PROTECT_NORDWR(0x1a400, 0x1fff),
635+ A6XX_PROTECT_NORDWR(0x1f400, 0x0443),
636+ A6XX_PROTECT_RDONLY(0x1f844, 0x007b),
637+ A6XX_PROTECT_NORDWR(0x1f860, 0x0000),
638+ A6XX_PROTECT_NORDWR(0x1f887, 0x001b),
639+ A6XX_PROTECT_NORDWR(0x1f8c0, 0x0000), /* note: infinite range */
640+};
641+
544642 static void a6xx_set_cp_protect(struct msm_gpu *gpu)
545643 {
546644 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
@@ -554,6 +652,10 @@ static void a6xx_set_cp_protect(struct msm_gpu *gpu) · 7 unmodified lines
554652 regs = a650_protect;
555653 count = ARRAY_SIZE(a650_protect);
556654 count_max = 48;
655+ } else if (adreno_is_a660(adreno_gpu)) {
656+ regs = a660_protect;
657+ count = ARRAY_SIZE(a660_protect);
658+ count_max = 48;
557659 }
558660
559661 /*
@@ -584,7 +686,7 @@ static void a6xx_set_ubwc_config(struct msm_gpu *gpu) · 24 unmodified lines
584686 if (adreno_is_a640(adreno_gpu))
585687 amsbc = 1;
586688
587− if (adreno_is_a650(adreno_gpu)) {
689+ if (adreno_is_a650(adreno_gpu) || adreno_is_a660(adreno_gpu)) {
588690 /* TODO: get ddr type from bootloader and use 2 for LPDDR4 */
589691 lower_bit = 3;
590692 amsbc = 1;
@@ -648,6 +750,11 @@ static bool a6xx_ucode_check_version(struct a6xx_gpu *a6xx_gpu, · 57 unmodified lines
648750 * Targets up to a640 (a618, a630 and a640) need to check for a
649751 * microcode version that is patched to support the whereami opcode or
650752 * one that is new enough to include it by default.
753+ *
754+ * a650 tier targets don't need whereami but still need to be
755+ * equal to or newer than 0.95 for other security fixes
756+ *
757+ * a660 targets have all the critical security fixes from the start
651758 */
652759 if (adreno_is_a618(adreno_gpu) || adreno_is_a630(adreno_gpu) ||
653760 adreno_is_a640(adreno_gpu)) {
@@ -671,27 +778,20 @@ static bool a6xx_ucode_check_version(struct a6xx_gpu *a6xx_gpu, · 17 unmodified lines
671778 DRM_DEV_ERROR(&gpu->pdev->dev,
672779 "a630 SQE ucode is too old. Have version %x need at least %x\n",
673780 buf[0] & 0xfff, 0x190);
674− } else {
675− /*
676− * a650 tier targets don't need whereami but still need to be
677− * equal to or newer than 0.95 for other security fixes
678− */
679− if (adreno_is_a650(adreno_gpu)) {
680− if ((buf[0] & 0xfff) >= 0x095) {
681− ret = true;
682− goto out;
683− }
684−
685− DRM_DEV_ERROR(&gpu->pdev->dev,
686− "a650 SQE ucode is too old. Have version %x need at least %x\n",
687− buf[0] & 0xfff, 0x095);
781+ } else if (adreno_is_a650(adreno_gpu)) {
782+ if ((buf[0] & 0xfff) >= 0x095) {
783+ ret = true;
784+ goto out;
688785 }
689786
690− /*
691− * When a660 is added those targets should return true here
692− * since those have all the critical security fixes built in
693− * from the start
694− */
787+ DRM_DEV_ERROR(&gpu->pdev->dev,
788+ "a650 SQE ucode is too old. Have version %x need at least %x\n",
789+ buf[0] & 0xfff, 0x095);
790+ } else if (adreno_is_a660(adreno_gpu)) {
791+ ret = true;
792+ } else {
793+ DRM_DEV_ERROR(&gpu->pdev->dev,
794+ "unknown GPU, add it to a6xx_ucode_check_version()!!\n");
695795 }
696796 out:
697797 msm_gem_put_vaddr(obj);
@@ -727,8 +827,8 @@ static int a6xx_ucode_init(struct msm_gpu *gpu) · 29 unmodified lines
727827 }
728828 }
729829
730− gpu_write64(gpu, REG_A6XX_CP_SQE_INSTR_BASE_LO,
731− REG_A6XX_CP_SQE_INSTR_BASE_HI, a6xx_gpu->sqe_iova);
830+ gpu_write64(gpu, REG_A6XX_CP_SQE_INSTR_BASE,
831+ REG_A6XX_CP_SQE_INSTR_BASE+1, a6xx_gpu->sqe_iova);
732832
733833 return 0;
734834 }
@@ -797,7 +897,7 @@ static int a6xx_hw_init(struct msm_gpu *gpu) · 62 unmodified lines
797897 a6xx_set_hwcg(gpu, true);
798898
799899 /* VBIF/GBIF start*/
800− if (adreno_is_a640(adreno_gpu) || adreno_is_a650(adreno_gpu)) {
900+ if (adreno_is_a640(adreno_gpu) || adreno_is_a650_family(adreno_gpu)) {
801901 gpu_write(gpu, REG_A6XX_GBIF_QSB_SIDE0, 0x00071620);
802902 gpu_write(gpu, REG_A6XX_GBIF_QSB_SIDE1, 0x00071620);
803903 gpu_write(gpu, REG_A6XX_GBIF_QSB_SIDE2, 0x00071620);
@@ -822,7 +922,7 @@ static int a6xx_hw_init(struct msm_gpu *gpu) · 18 unmodified lines
822922 gpu_write(gpu, REG_A6XX_UCHE_WRITE_THRU_BASE_LO, 0xfffff000);
823923 gpu_write(gpu, REG_A6XX_UCHE_WRITE_THRU_BASE_HI, 0x0001ffff);
824924
825− if (!adreno_is_a650(adreno_gpu)) {
925+ if (!adreno_is_a650_family(adreno_gpu)) {
826926 /* Set the GMEM VA range [0x100000:0x100000 + gpu->gmem - 1] */
827927 gpu_write64(gpu, REG_A6XX_UCHE_GMEM_RANGE_MIN_LO,
828928 REG_A6XX_UCHE_GMEM_RANGE_MIN_HI, 0x00100000);
@@ -835,22 +935,27 @@ static int a6xx_hw_init(struct msm_gpu *gpu) · 6 unmodified lines
835935 gpu_write(gpu, REG_A6XX_UCHE_FILTER_CNTL, 0x804);
836936 gpu_write(gpu, REG_A6XX_UCHE_CACHE_WAYS, 0x4);
837937
838− if (adreno_is_a640(adreno_gpu) || adreno_is_a650(adreno_gpu))
938+ if (adreno_is_a640(adreno_gpu) || adreno_is_a650_family(adreno_gpu))
839939 gpu_write(gpu, REG_A6XX_CP_ROQ_THRESHOLDS_2, 0x02000140);
840940 else
841941 gpu_write(gpu, REG_A6XX_CP_ROQ_THRESHOLDS_2, 0x010000c0);
842942 gpu_write(gpu, REG_A6XX_CP_ROQ_THRESHOLDS_1, 0x8040362c);
843943
944+ if (adreno_is_a660(adreno_gpu))
945+ gpu_write(gpu, REG_A6XX_CP_LPAC_PROG_FIFO_SIZE, 0x00000020);
946+
844947 /* Setting the mem pool size */
845948 gpu_write(gpu, REG_A6XX_CP_MEM_POOL_SIZE, 128);
846949
847− /* Setting the primFifo thresholds default values */
848− if (adreno_is_a650(adreno_gpu))
849− gpu_write(gpu, REG_A6XX_PC_DBG_ECO_CNTL, 0x00300000);
950+ /* Setting the primFifo thresholds default values,
951+ * and vccCacheSkipDis=1 bit (0x200) for A640 and newer
952+ */
953+ if (adreno_is_a650(adreno_gpu) || adreno_is_a660(adreno_gpu))
954+ gpu_write(gpu, REG_A6XX_PC_DBG_ECO_CNTL, 0x00300200);
850955 else if (adreno_is_a640(adreno_gpu))
851− gpu_write(gpu, REG_A6XX_PC_DBG_ECO_CNTL, 0x00200000);
956+ gpu_write(gpu, REG_A6XX_PC_DBG_ECO_CNTL, 0x00200200);
852957 else
853− gpu_write(gpu, REG_A6XX_PC_DBG_ECO_CNTL, (0x300 << 11));
958+ gpu_write(gpu, REG_A6XX_PC_DBG_ECO_CNTL, 0x00180000);
854959
855960 /* Set the AHB default slave response to "ERROR" */
856961 gpu_write(gpu, REG_A6XX_CP_AHB_CNTL, 0x1);
@@ -859,7 +964,7 @@ static int a6xx_hw_init(struct msm_gpu *gpu) · 2 unmodified lines
859964 gpu_write(gpu, REG_A6XX_RBBM_PERFCTR_CNTL, 0x1);
860965
861966 /* Select CP0 to always count cycles */
862− gpu_write(gpu, REG_A6XX_CP_PERFCTR_CP_SEL_0, PERF_CP_ALWAYS_COUNT);
967+ gpu_write(gpu, REG_A6XX_CP_PERFCTR_CP_SEL(0), PERF_CP_ALWAYS_COUNT);
863968
864969 a6xx_set_ubwc_config(gpu);
865970
@@ -870,7 +975,7 @@ static int a6xx_hw_init(struct msm_gpu *gpu) · 4 unmodified lines
870975 gpu_write(gpu, REG_A6XX_UCHE_CLIENT_PF, 1);
871976
872977 /* Set weights for bicubic filtering */
873− if (adreno_is_a650(adreno_gpu)) {
978+ if (adreno_is_a650_family(adreno_gpu)) {
874979 gpu_write(gpu, REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_0, 0);
875980 gpu_write(gpu, REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_1,
876981 0x3fe05ff4);
@@ -885,6 +990,13 @@ static int a6xx_hw_init(struct msm_gpu *gpu) · 8 unmodified lines
885990 /* Protect registers from the CP */
886991 a6xx_set_cp_protect(gpu);
887992
993+ if (adreno_is_a660(adreno_gpu)) {
994+ gpu_write(gpu, REG_A6XX_CP_CHICKEN_DBG, 0x1);
995+ gpu_write(gpu, REG_A6XX_RBBM_GBIF_CLIENT_QOS_CNTL, 0x0);
996+ /* Set dualQ + disable afull for A660 GPU but not for A635 */
997+ gpu_write(gpu, REG_A6XX_UCHE_CMDQ_CONFIG, 0x66906);
998+ }
999+
8881000 /* Enable expanded apriv for targets that support it */
8891001 if (gpu->hw_apriv) {
8901002 gpu_write(gpu, REG_A6XX_CP_APRIV_CNTL,
@@ -925,7 +1037,7 @@ static int a6xx_hw_init(struct msm_gpu *gpu) · 34 unmodified lines
9251037 if (!a6xx_gpu->shadow_bo) {
9261038 a6xx_gpu->shadow = msm_gem_kernel_new_locked(gpu->dev,
9271039 sizeof(u32) * gpu->nr_rings,
928− MSM_BO_UNCACHED | MSM_BO_MAP_PRIV,
1040+ MSM_BO_WC | MSM_BO_MAP_PRIV,
9291041 gpu->aspace, &a6xx_gpu->shadow_bo,
9301042 &a6xx_gpu->shadow_iova);
9311043
@@ -1032,18 +1144,113 @@ static void a6xx_recover(struct msm_gpu *gpu) · 100 unmodified lines
10321144 msm_gpu_hw_init(gpu);
10331145 }
10341146
1035−static int a6xx_fault_handler(void *arg, unsigned long iova, int flags)
1147+static const char *a6xx_uche_fault_block(struct msm_gpu *gpu, u32 mid)
1148+{
1149+ static const char *uche_clients[7] = {
1150+ "VFD", "SP", "VSC", "VPC", "HLSQ", "PC", "LRZ",
1151+ };
1152+ u32 val;
1153+
1154+ if (mid < 1 || mid > 3)
1155+ return "UNKNOWN";
1156+
1157+ /*
1158+ * The source of the data depends on the mid ID read from FSYNR1.
1159+ * and the client ID read from the UCHE block
1160+ */
1161+ val = gpu_read(gpu, REG_A6XX_UCHE_CLIENT_PF);
1162+
1163+ /* mid = 3 is most precise and refers to only one block per client */
1164+ if (mid == 3)
1165+ return uche_clients[val & 7];
1166+
1167+ /* For mid=2 the source is TP or VFD except when the client id is 0 */
1168+ if (mid == 2)
1169+ return ((val & 7) == 0) ? "TP" : "TP|VFD";
1170+
1171+ /* For mid=1 just return "UCHE" as a catchall for everything else */
1172+ return "UCHE";
1173+}
1174+
1175+static const char *a6xx_fault_block(struct msm_gpu *gpu, u32 id)
1176+{
1177+ if (id == 0)
1178+ return "CP";
1179+ else if (id == 4)
1180+ return "CCU";
1181+ else if (id == 6)
1182+ return "CDP Prefetch";
1183+
1184+ return a6xx_uche_fault_block(gpu, id);
1185+}
1186+
1187+#define ARM_SMMU_FSR_TF BIT(1)
1188+#define ARM_SMMU_FSR_PF BIT(3)
1189+#define ARM_SMMU_FSR_EF BIT(4)
1190+
1191+static int a6xx_fault_handler(void *arg, unsigned long iova, int flags, void *data)
10361192 {
10371193 struct msm_gpu *gpu = arg;
1194+ struct adreno_smmu_fault_info *info = data;
1195+ const char *type = "UNKNOWN";
1196+ const char *block;
1197+ bool do_devcoredump = info && !READ_ONCE(gpu->crashstate);
1198+
1199+ /*
1200+ * If we aren't going to be resuming later from fault_worker, then do
1201+ * it now.
1202+ */
1203+ if (!do_devcoredump) {
1204+ gpu->aspace->mmu->funcs->resume_translation(gpu->aspace->mmu);
1205+ }
10381206
1039− pr_warn_ratelimited("*** gpu fault: iova=%08lx, flags=%d (%u,%u,%u,%u)\n",
1207+ /*
1208+ * Print a default message if we couldn't get the data from the
1209+ * adreno-smmu-priv
1210+ */
1211+ if (!info) {
1212+ pr_warn_ratelimited("*** gpu fault: iova=%.16lx flags=%d (%u,%u,%u,%u)\n",
10401213 iova, flags,
10411214 gpu_read(gpu, REG_A6XX_CP_SCRATCH_REG(4)),
10421215 gpu_read(gpu, REG_A6XX_CP_SCRATCH_REG(5)),
10431216 gpu_read(gpu, REG_A6XX_CP_SCRATCH_REG(6)),
10441217 gpu_read(gpu, REG_A6XX_CP_SCRATCH_REG(7)));
10451218
1046− return -EFAULT;
1219+ return 0;
1220+ }
1221+
1222+ if (info->fsr & ARM_SMMU_FSR_TF)
1223+ type = "TRANSLATION";
1224+ else if (info->fsr & ARM_SMMU_FSR_PF)
1225+ type = "PERMISSION";
1226+ else if (info->fsr & ARM_SMMU_FSR_EF)
1227+ type = "EXTERNAL";
1228+
1229+ block = a6xx_fault_block(gpu, info->fsynr1 & 0xff);
1230+
1231+ pr_warn_ratelimited("*** gpu fault: ttbr0=%.16llx iova=%.16lx dir=%s type=%s source=%s (%u,%u,%u,%u)\n",
1232+ info->ttbr0, iova,
1233+ flags & IOMMU_FAULT_WRITE ? "WRITE" : "READ",
1234+ type, block,
1235+ gpu_read(gpu, REG_A6XX_CP_SCRATCH_REG(4)),
1236+ gpu_read(gpu, REG_A6XX_CP_SCRATCH_REG(5)),
1237+ gpu_read(gpu, REG_A6XX_CP_SCRATCH_REG(6)),
1238+ gpu_read(gpu, REG_A6XX_CP_SCRATCH_REG(7)));
1239+
1240+ if (do_devcoredump) {
1241+ /* Turn off the hangcheck timer to keep it from bothering us */
1242+ del_timer(&gpu->hangcheck_timer);
1243+
1244+ gpu->fault_info.ttbr0 = info->ttbr0;
1245+ gpu->fault_info.iova = iova;
1246+ gpu->fault_info.flags = flags;
1247+ gpu->fault_info.type = type;
1248+ gpu->fault_info.block = block;
1249+
1250+ kthread_queue_work(gpu->worker, &gpu->fault_work);
1251+ }
1252+
1253+ return 0;
10471254 }
10481255
10491256 static void a6xx_cp_hw_err_irq(struct msm_gpu *gpu)
@@ -1094,6 +1301,15 @@ static void a6xx_fault_detect_irq(struct msm_gpu *gpu) · 44 unmodified lines
10941301 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu);
10951302 struct msm_ringbuffer *ring = gpu->funcs->active_ring(gpu);
10961303
1304+ /*
1305+ * If stalled on SMMU fault, we could trip the GPU's hang detection,
1306+ * but the fault handler will trigger the devcore dump, and we want
1307+ * to otherwise resume normally rather than killing the submit, so
1308+ * just bail.
1309+ */
1310+ if (gpu_read(gpu, REG_A6XX_RBBM_STATUS3) & A6XX_RBBM_STATUS3_SMMU_STALLED_ON_FAULT)
1311+ return;
1312+
10971313 /*
10981314 * Force the GPU to stay on until after we finish
10991315 * collecting information
@@ -1339,9 +1555,6 @@ static void a6xx_destroy(struct msm_gpu *gpu) · 239 unmodified lines
13391555
13401556 adreno_gpu_cleanup(adreno_gpu);
13411557
1342− if (a6xx_gpu->opp_table)
1343− dev_pm_opp_put_supported_hw(a6xx_gpu->opp_table);
1344−
13451558 kfree(a6xx_gpu);
13461559 }
13471560
@@ -1474,7 +1687,6 @@ static u32 fuse_to_supp_hw(struct device *dev, u32 revn, u32 fuse) · 126 unmodified lines
14741687 static int a6xx_set_supported_hw(struct device *dev, struct a6xx_gpu *a6xx_gpu,
14751688 u32 revn)
14761689 {
1477− struct opp_table *opp_table;
14781690 u32 supp_hw = UINT_MAX;
14791691 u16 speedbin;
14801692 int ret;
@@ -1497,11 +1709,10 @@ static int a6xx_set_supported_hw(struct device *dev, struct a6xx_gpu *a6xx_gpu, · 16 unmodified lines
14971709 supp_hw = fuse_to_supp_hw(dev, revn, speedbin);
14981710
14991711 done:
1500− opp_table = dev_pm_opp_set_supported_hw(dev, &supp_hw, 1);
1501− if (IS_ERR(opp_table))
1502− return PTR_ERR(opp_table);
1712+ ret = devm_pm_opp_set_supported_hw(dev, &supp_hw, 1);
1713+ if (ret)
1714+ return ret;
15031715
1504− a6xx_gpu->opp_table = opp_table;
15051716 return 0;
15061717 }
15071718
@@ -1561,7 +1772,7 @@ struct msm_gpu *a6xx_gpu_init(struct drm_device *dev) · 53 unmodified lines
15611772 */
15621773 info = adreno_info(config->rev);
15631774
1564− if (info && info->revn == 650)
1775+ if (info && (info->revn == 650 || info->revn == 660))
15651776 adreno_gpu->base.hw_apriv = true;
15661777
15671778 a6xx_llc_slices_init(pdev, a6xx_gpu);
drivers/gpu/drm/msm/adreno/a6xx_gpu.h+0−2
@@ -33,8 +33,6 @@ struct a6xx_gpu { · 32 unmodified lines
3333 void *llc_slice;
3434 void *htw_llc_slice;
3535 bool have_mmu500;
36−
37− struct opp_table *opp_table;
3836 };
3937
4038 #define to_a6xx_gpu(x) container_of(x, struct a6xx_gpu, base)
drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c+35−9
@@ -113,7 +113,7 @@ static int a6xx_crashdumper_init(struct msm_gpu *gpu, · 112 unmodified lines
113113 struct a6xx_crashdumper *dumper)
114114 {
115115 dumper->ptr = msm_gem_kernel_new_locked(gpu->dev,
116− SZ_1M, MSM_BO_UNCACHED, gpu->aspace,
116+ SZ_1M, MSM_BO_WC, gpu->aspace,
117117 &dumper->bo, &dumper->iova);
118118
119119 if (!IS_ERR(dumper->ptr))
@@ -832,6 +832,20 @@ static void a6xx_get_registers(struct msm_gpu *gpu, · 712 unmodified lines
832832 a6xx_get_ahb_gpu_registers(gpu,
833833 a6xx_state, &a6xx_vbif_reglist,
834834 &a6xx_state->registers[index++]);
835+ if (!dumper) {
836+ /*
837+ * We can't use the crashdumper when the SMMU is stalled,
838+ * because the GPU has no memory access until we resume
839+ * translation (but we don't want to do that until after
840+ * we have captured as much useful GPU state as possible).
841+ * So instead collect registers via the CPU:
842+ */
843+ for (i = 0; i < ARRAY_SIZE(a6xx_reglist); i++)
844+ a6xx_get_ahb_gpu_registers(gpu,
845+ a6xx_state, &a6xx_reglist[i],
846+ &a6xx_state->registers[index++]);
847+ return;
848+ }
835849
836850 for (i = 0; i < ARRAY_SIZE(a6xx_reglist); i++)
837851 a6xx_get_crashdumper_registers(gpu,
@@ -905,11 +919,13 @@ static void a6xx_get_indexed_registers(struct msm_gpu *gpu, · 67 unmodified lines
905919
906920 struct msm_gpu_state *a6xx_gpu_state_get(struct msm_gpu *gpu)
907921 {
908− struct a6xx_crashdumper dumper = { 0 };
922+ struct a6xx_crashdumper _dumper = { 0 }, *dumper = NULL;
909923 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
910924 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu);
911925 struct a6xx_gpu_state *a6xx_state = kzalloc(sizeof(*a6xx_state),
912926 GFP_KERNEL);
927+ bool stalled = !!(gpu_read(gpu, REG_A6XX_RBBM_STATUS3) &
928+ A6XX_RBBM_STATUS3_SMMU_STALLED_ON_FAULT);
913929
914930 if (!a6xx_state)
915931 return ERR_PTR(-ENOMEM);
@@ -928,14 +944,24 @@ struct msm_gpu_state *a6xx_gpu_state_get(struct msm_gpu *gpu) · 12 unmodified lines
928944 /* Get the banks of indexed registers */
929945 a6xx_get_indexed_registers(gpu, a6xx_state);
930946
931− /* Try to initialize the crashdumper */
932− if (!a6xx_crashdumper_init(gpu, &dumper)) {
933− a6xx_get_registers(gpu, a6xx_state, &dumper);
934− a6xx_get_shaders(gpu, a6xx_state, &dumper);
935− a6xx_get_clusters(gpu, a6xx_state, &dumper);
936− a6xx_get_dbgahb_clusters(gpu, a6xx_state, &dumper);
947+ /*
948+ * Try to initialize the crashdumper, if we are not dumping state
949+ * with the SMMU stalled. The crashdumper needs memory access to
950+ * write out GPU state, so we need to skip this when the SMMU is
951+ * stalled in response to an iova fault
952+ */
953+ if (!stalled && !a6xx_crashdumper_init(gpu, &_dumper)) {
954+ dumper = &_dumper;
955+ }
956+
957+ a6xx_get_registers(gpu, a6xx_state, dumper);
958+
959+ if (dumper) {
960+ a6xx_get_shaders(gpu, a6xx_state, dumper);
961+ a6xx_get_clusters(gpu, a6xx_state, dumper);
962+ a6xx_get_dbgahb_clusters(gpu, a6xx_state, dumper);
937963
938− msm_gem_kernel_put(dumper.bo, gpu->aspace, true);
964+ msm_gem_kernel_put(dumper->bo, gpu->aspace, true);
939965 }
940966
941967 if (snapshot_debugbus)
drivers/gpu/drm/msm/adreno/a6xx_hfi.c+33−0
@@ -351,6 +351,37 @@ static void a650_build_bw_table(struct a6xx_hfi_msg_bw_table *msg) · 350 unmodified lines
351351 msg->cnoc_cmds_data[1][0] = 0x60000001;
352352 }
353353
354+static void a660_build_bw_table(struct a6xx_hfi_msg_bw_table *msg)
355+{
356+ /*
357+ * Send a single "off" entry just to get things running
358+ * TODO: bus scaling
359+ */
360+ msg->bw_level_num = 1;
361+
362+ msg->ddr_cmds_num = 3;
363+ msg->ddr_wait_bitmask = 0x01;
364+
365+ msg->ddr_cmds_addrs[0] = 0x50004;
366+ msg->ddr_cmds_addrs[1] = 0x500a0;
367+ msg->ddr_cmds_addrs[2] = 0x50000;
368+
369+ msg->ddr_cmds_data[0][0] = 0x40000000;
370+ msg->ddr_cmds_data[0][1] = 0x40000000;
371+ msg->ddr_cmds_data[0][2] = 0x40000000;
372+
373+ /*
374+ * These are the CX (CNOC) votes - these are used by the GMU but the
375+ * votes are known and fixed for the target
376+ */
377+ msg->cnoc_cmds_num = 1;
378+ msg->cnoc_wait_bitmask = 0x01;
379+
380+ msg->cnoc_cmds_addrs[0] = 0x50070;
381+ msg->cnoc_cmds_data[0][0] = 0x40000000;
382+ msg->cnoc_cmds_data[1][0] = 0x60000001;
383+}
384+
354385 static void a6xx_build_bw_table(struct a6xx_hfi_msg_bw_table *msg)
355386 {
356387 /* Send a single "off" entry since the 630 GMU doesn't do bus scaling */
@@ -401,6 +432,8 @@ static int a6xx_hfi_send_bw_table(struct a6xx_gmu *gmu) · 44 unmodified lines
401432 a640_build_bw_table(&msg);
402433 else if (adreno_is_a650(adreno_gpu))
403434 a650_build_bw_table(&msg);
435+ else if (adreno_is_a660(adreno_gpu))
436+ a660_build_bw_table(&msg);
404437 else
405438 a6xx_build_bw_table(&msg);
406439
drivers/gpu/drm/msm/adreno/adreno_common.xml.h+15−15
@@ -8,21 +8,21 @@ http://github.com/freedreno/envytools/ · 7 unmodified lines
88 git clone https://github.com/freedreno/envytools.git
99
1010 The rules-ng-ng source files this header was generated from are:
11−- /home/robclark/src/envytools/rnndb/adreno.xml ( 594 bytes, from 2020-07-23 21:58:14)
12−- /home/robclark/src/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2020-07-23 21:58:14)
13−- /home/robclark/src/envytools/rnndb/adreno/a2xx.xml ( 90159 bytes, from 2020-07-23 21:58:14)
14−- /home/robclark/src/envytools/rnndb/adreno/adreno_common.xml ( 14386 bytes, from 2020-07-23 21:58:14)
15−- /home/robclark/src/envytools/rnndb/adreno/adreno_pm4.xml ( 65048 bytes, from 2020-07-23 21:58:14)
16−- /home/robclark/src/envytools/rnndb/adreno/a3xx.xml ( 84226 bytes, from 2020-07-23 21:58:14)
17−- /home/robclark/src/envytools/rnndb/adreno/a4xx.xml ( 112556 bytes, from 2020-07-23 21:58:14)
18−- /home/robclark/src/envytools/rnndb/adreno/a5xx.xml ( 149461 bytes, from 2020-07-23 21:58:14)
19−- /home/robclark/src/envytools/rnndb/adreno/a6xx.xml ( 184695 bytes, from 2020-07-23 21:58:14)
20−- /home/robclark/src/envytools/rnndb/adreno/a6xx_gmu.xml ( 11218 bytes, from 2020-07-23 21:58:14)
21−- /home/robclark/src/envytools/rnndb/adreno/ocmem.xml ( 1773 bytes, from 2020-07-23 21:58:14)
22−- /home/robclark/src/envytools/rnndb/adreno/adreno_control_regs.xml ( 4559 bytes, from 2020-07-23 21:58:14)
23−- /home/robclark/src/envytools/rnndb/adreno/adreno_pipe_regs.xml ( 2872 bytes, from 2020-07-23 21:58:14)
24−
25−Copyright (C) 2013-2020 by the following authors:
11+- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno.xml ( 594 bytes, from 2021-02-18 16:45:44)
12+- /home/robclark/src/mesa/mesa/src/freedreno/registers/freedreno_copyright.xml ( 1572 bytes, from 2021-02-18 16:45:44)
13+- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a2xx.xml ( 90810 bytes, from 2021-02-18 16:45:44)
14+- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_common.xml ( 14386 bytes, from 2021-02-18 16:45:44)
15+- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_pm4.xml ( 67699 bytes, from 2021-05-31 20:21:57)
16+- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a3xx.xml ( 84226 bytes, from 2021-02-18 16:45:44)
17+- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a4xx.xml ( 112551 bytes, from 2021-02-18 16:45:44)
18+- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a5xx.xml ( 150713 bytes, from 2021-06-10 22:34:02)
19+- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a6xx.xml ( 180049 bytes, from 2021-06-02 21:44:19)
20+- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a6xx_gmu.xml ( 11331 bytes, from 2021-05-21 19:18:08)
21+- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/ocmem.xml ( 1773 bytes, from 2021-02-18 16:45:44)
22+- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_control_regs.xml ( 6038 bytes, from 2021-05-27 20:22:36)
23+- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_pipe_regs.xml ( 2924 bytes, from 2021-05-27 20:18:13)
24+
25+Copyright (C) 2013-2021 by the following authors:
2626 - Rob Clark <robdclark@gmail.com> (robclark)
2727 - Ilia Mirkin <imirkin@alum.mit.edu> (imirkin)
2828
drivers/gpu/drm/msm/adreno/adreno_device.c+14−0
@@ -287,6 +287,19 @@ static const struct adreno_info gpulist[] = { · 286 unmodified lines
287287 .init = a6xx_gpu_init,
288288 .zapfw = "a650_zap.mdt",
289289 .hwcg = a650_hwcg,
290+ }, {
291+ .rev = ADRENO_REV(6, 6, 0, ANY_ID),
292+ .revn = 660,
293+ .name = "A660",
294+ .fw = {
295+ [ADRENO_FW_SQE] = "a660_sqe.fw",
296+ [ADRENO_FW_GMU] = "a660_gmu.bin",
297+ },
298+ .gmem = SZ_1M + SZ_512K,
299+ .inactive_period = DRM_MSM_INACTIVE_PERIOD,
300+ .init = a6xx_gpu_init,
301+ .zapfw = "a660_zap.mdt",
302+ .hwcg = a660_hwcg,
290303 },
291304 };
292305
@@ -466,6 +479,7 @@ static int adreno_bind(struct device *dev, struct device *master, void *data) · 173 unmodified lines
466479 config.rev.minor, config.rev.patchid);
467480
468481 priv->is_a2xx = config.rev.core == 2;
482+ priv->has_cached_coherent = config.rev.core >= 6;
469483
470484 gpu = info->init(drm);
471485 if (IS_ERR(gpu)) {
drivers/gpu/drm/msm/adreno/adreno_gpu.c+19−7
@@ -239,7 +239,7 @@ int adreno_get_param(struct msm_gpu *gpu, uint32_t param, uint64_t *value) · 238 unmodified lines
239239 *value = adreno_gpu->gmem;
240240 return 0;
241241 case MSM_PARAM_GMEM_BASE:
242− *value = !adreno_is_a650(adreno_gpu) ? 0x100000 : 0;
242+ *value = !adreno_is_a650_family(adreno_gpu) ? 0x100000 : 0;
243243 return 0;
244244 case MSM_PARAM_CHIP_ID:
245245 *value = adreno_gpu->rev.patchid |
@@ -391,7 +391,7 @@ struct drm_gem_object *adreno_fw_create_bo(struct msm_gpu *gpu, · 145 unmodified lines
391391 void *ptr;
392392
393393 ptr = msm_gem_kernel_new_locked(gpu->dev, fw->size - 4,
394− MSM_BO_UNCACHED | MSM_BO_GPU_READONLY, gpu->aspace, &bo, iova);
394+ MSM_BO_WC | MSM_BO_GPU_READONLY, gpu->aspace, &bo, iova);
395395
396396 if (IS_ERR(ptr))
397397 return ERR_CAST(ptr);
@@ -408,7 +408,7 @@ int adreno_hw_init(struct msm_gpu *gpu) · 10 unmodified lines
408408 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
409409 int ret, i;
410410
411− DBG("%s", gpu->name);
411+ VERB("%s", gpu->name);
412412
413413 ret = adreno_load_fw(adreno_gpu);
414414 if (ret)
@@ -684,6 +684,21 @@ void adreno_show(struct msm_gpu *gpu, struct msm_gpu_state *state, · 269 unmodified lines
684684 adreno_gpu->info->revn, adreno_gpu->rev.core,
685685 adreno_gpu->rev.major, adreno_gpu->rev.minor,
686686 adreno_gpu->rev.patchid);
687+ /*
688+ * If this is state collected due to iova fault, so fault related info
689+ *
690+ * TTBR0 would not be zero, so this is a good way to distinguish
691+ */
692+ if (state->fault_info.ttbr0) {
693+ const struct msm_gpu_fault_info *info = &state->fault_info;
694+
695+ drm_puts(p, "fault-info:\n");
696+ drm_printf(p, " - ttbr0=%.16llx\n", info->ttbr0);
697+ drm_printf(p, " - iova=%.16lx\n", info->iova);
698+ drm_printf(p, " - dir=%s\n", info->flags & IOMMU_FAULT_WRITE ? "WRITE" : "READ");
699+ drm_printf(p, " - type=%s\n", info->type);
700+ drm_printf(p, " - source=%s\n", info->block);
701+ }
687702
688703 drm_printf(p, "rbbm-status: 0x%08x\n", state->rbbm_status);
689704
@@ -841,7 +856,7 @@ static void adreno_get_pwrlevels(struct device *dev, · 151 unmodified lines
841856 if (!of_find_property(dev->of_node, "operating-points-v2", NULL))
842857 ret = adreno_get_legacy_pwrlevels(dev);
843858 else {
844− ret = dev_pm_opp_of_add_table(dev);
859+ ret = devm_pm_opp_of_add_table(dev);
845860 if (ret)
846861 DRM_DEV_ERROR(dev, "Unable to set the OPP table\n");
847862 }
@@ -946,7 +961,4 @@ void adreno_gpu_cleanup(struct adreno_gpu *adreno_gpu) · 98 unmodified lines
946961 pm_runtime_disable(&priv->gpu_pdev->dev);
947962
948963 msm_gpu_cleanup(&adreno_gpu->base);
949−
950− icc_put(gpu->icc_path);
951− icc_put(gpu->ocmem_icc_path);
952964 }
drivers/gpu/drm/msm/adreno/adreno_gpu.h+12−1
@@ -55,7 +55,7 @@ struct adreno_reglist { · 54 unmodified lines
5555 u32 value;
5656 };
5757
58−extern const struct adreno_reglist a630_hwcg[], a640_hwcg[], a650_hwcg[];
58+extern const struct adreno_reglist a630_hwcg[], a640_hwcg[], a650_hwcg[], a660_hwcg[];
5959
6060 struct adreno_info {
6161 struct adreno_rev rev;
@@ -247,6 +247,17 @@ static inline int adreno_is_a650(struct adreno_gpu *gpu) · 185 unmodified lines
247247 return gpu->revn == 650;
248248 }
249249
250+static inline int adreno_is_a660(struct adreno_gpu *gpu)
251+{
252+ return gpu->revn == 660;
253+}
254+
255+/* check for a650, a660, or any derivatives */
256+static inline int adreno_is_a650_family(struct adreno_gpu *gpu)
257+{
258+ return gpu->revn == 650 || gpu->revn == 620 || gpu->revn == 660;
259+}
260+
250261 int adreno_get_param(struct msm_gpu *gpu, uint32_t param, uint64_t *value);
251262 const struct firmware *adreno_request_fw(struct adreno_gpu *adreno_gpu,
252263 const char *fwname);
drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h+79−40
@@ -8,21 +8,21 @@ http://github.com/freedreno/envytools/ · 7 unmodified lines
88 git clone https://github.com/freedreno/envytools.git
99
1010 The rules-ng-ng source files this header was generated from are:
11−- /home/robclark/src/envytools/rnndb/adreno.xml ( 594 bytes, from 2020-07-23 21:58:14)
12−- /home/robclark/src/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2020-07-23 21:58:14)
13−- /home/robclark/src/envytools/rnndb/adreno/a2xx.xml ( 90159 bytes, from 2020-07-23 21:58:14)
14−- /home/robclark/src/envytools/rnndb/adreno/adreno_common.xml ( 14386 bytes, from 2020-07-23 21:58:14)
15−- /home/robclark/src/envytools/rnndb/adreno/adreno_pm4.xml ( 65048 bytes, from 2020-07-23 21:58:14)
16−- /home/robclark/src/envytools/rnndb/adreno/a3xx.xml ( 84226 bytes, from 2020-07-23 21:58:14)
17−- /home/robclark/src/envytools/rnndb/adreno/a4xx.xml ( 112556 bytes, from 2020-07-23 21:58:14)
18−- /home/robclark/src/envytools/rnndb/adreno/a5xx.xml ( 149461 bytes, from 2020-07-23 21:58:14)
19−- /home/robclark/src/envytools/rnndb/adreno/a6xx.xml ( 184695 bytes, from 2020-07-23 21:58:14)
20−- /home/robclark/src/envytools/rnndb/adreno/a6xx_gmu.xml ( 11218 bytes, from 2020-07-23 21:58:14)
21−- /home/robclark/src/envytools/rnndb/adreno/ocmem.xml ( 1773 bytes, from 2020-07-23 21:58:14)
22−- /home/robclark/src/envytools/rnndb/adreno/adreno_control_regs.xml ( 4559 bytes, from 2020-07-23 21:58:14)
23−- /home/robclark/src/envytools/rnndb/adreno/adreno_pipe_regs.xml ( 2872 bytes, from 2020-07-23 21:58:14)
24−
25−Copyright (C) 2013-2020 by the following authors:
11+- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno.xml ( 594 bytes, from 2021-02-18 16:45:44)
12+- /home/robclark/src/mesa/mesa/src/freedreno/registers/freedreno_copyright.xml ( 1572 bytes, from 2021-02-18 16:45:44)
13+- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a2xx.xml ( 90810 bytes, from 2021-02-18 16:45:44)
14+- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_common.xml ( 14386 bytes, from 2021-02-18 16:45:44)
15+- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_pm4.xml ( 67699 bytes, from 2021-05-31 20:21:57)
16+- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a3xx.xml ( 84226 bytes, from 2021-02-18 16:45:44)
17+- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a4xx.xml ( 112551 bytes, from 2021-02-18 16:45:44)
18+- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a5xx.xml ( 150713 bytes, from 2021-06-10 22:34:02)
19+- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a6xx.xml ( 180049 bytes, from 2021-06-02 21:44:19)
20+- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a6xx_gmu.xml ( 11331 bytes, from 2021-05-21 19:18:08)
21+- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/ocmem.xml ( 1773 bytes, from 2021-02-18 16:45:44)
22+- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_control_regs.xml ( 6038 bytes, from 2021-05-27 20:22:36)
23+- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_pipe_regs.xml ( 2924 bytes, from 2021-05-27 20:18:13)
24+
25+Copyright (C) 2013-2021 by the following authors:
2626 - Rob Clark <robdclark@gmail.com> (robclark)
2727 - Ilia Mirkin <imirkin@alum.mit.edu> (imirkin)
2828
@@ -247,9 +247,9 @@ enum adreno_pm4_type3_packets { · 218 unmodified lines
247247 CP_DRAW_INDX_INDIRECT = 41,
248248 CP_DRAW_INDIRECT_MULTI = 42,
249249 CP_DRAW_AUTO = 36,
250− CP_UNKNOWN_19 = 25,
251− CP_UNKNOWN_1A = 26,
252− CP_UNKNOWN_4E = 78,
250+ CP_DRAW_PRED_ENABLE_GLOBAL = 25,
251+ CP_DRAW_PRED_ENABLE_LOCAL = 26,
252+ CP_DRAW_PRED_SET = 78,
253253 CP_WIDE_REG_WRITE = 116,
254254 CP_SCRATCH_TO_REG = 77,
255255 CP_REG_TO_SCRATCH = 74,
@@ -267,6 +267,7 @@ enum adreno_pm4_type3_packets { · 11 unmodified lines
267267 CP_SKIP_IB2_ENABLE_GLOBAL = 29,
268268 CP_SKIP_IB2_ENABLE_LOCAL = 35,
269269 CP_SET_SUBDRAW_SIZE = 53,
270+ CP_WHERE_AM_I = 98,
270271 CP_SET_VISIBILITY_OVERRIDE = 100,
271272 CP_PREEMPT_ENABLE_GLOBAL = 105,
272273 CP_PREEMPT_ENABLE_LOCAL = 106,
@@ -298,7 +299,6 @@ enum adreno_pm4_type3_packets { · 25 unmodified lines
298299 CP_SET_BIN_DATA5_OFFSET = 46,
299300 CP_SET_CTXSWITCH_IB = 85,
300301 CP_REG_WRITE = 109,
301− CP_WHERE_AM_I = 98,
302302 };
303303
304304 enum adreno_state_block {
@@ -400,6 +400,17 @@ enum a6xx_patch_type { · 95 unmodified lines
400400 enum a6xx_draw_indirect_opcode {
401401 INDIRECT_OP_NORMAL = 2,
402402 INDIRECT_OP_INDEXED = 4,
403+ INDIRECT_OP_INDIRECT_COUNT = 6,
404+ INDIRECT_OP_INDIRECT_COUNT_INDEXED = 7,
405+};
406+
407+enum cp_draw_pred_src {
408+ PRED_SRC_MEM = 5,
409+};
410+
411+enum cp_draw_pred_test {
412+ NE_0_PASS = 0,
413+ EQ_0_PASS = 1,
403414 };
404415
405416 enum cp_cond_function {
@@ -1040,33 +1051,61 @@ static inline uint32_t A6XX_CP_DRAW_INDIRECT_MULTI_1_DST_OFF(uint32_t val) · 634 unmodified lines
10401051 return ((val) << A6XX_CP_DRAW_INDIRECT_MULTI_1_DST_OFF__SHIFT) & A6XX_CP_DRAW_INDIRECT_MULTI_1_DST_OFF__MASK;
10411052 }
10421053
1043−#define REG_A6XX_CP_DRAW_INDIRECT_MULTI_2 0x00000002
1044−#define A6XX_CP_DRAW_INDIRECT_MULTI_2_DRAW_COUNT__MASK 0xffffffff
1045−#define A6XX_CP_DRAW_INDIRECT_MULTI_2_DRAW_COUNT__SHIFT 0
1046−static inline uint32_t A6XX_CP_DRAW_INDIRECT_MULTI_2_DRAW_COUNT(uint32_t val)
1047−{
1048− return ((val) << A6XX_CP_DRAW_INDIRECT_MULTI_2_DRAW_COUNT__SHIFT) & A6XX_CP_DRAW_INDIRECT_MULTI_2_DRAW_COUNT__MASK;
1049−}
1054+#define REG_A6XX_CP_DRAW_INDIRECT_MULTI_DRAW_COUNT 0x00000002
10501055
1051−#define REG_A6XX_CP_DRAW_INDIRECT_MULTI_ADDRESS_0 0x00000003
10521056
1053−#define REG_A6XX_CP_DRAW_INDIRECT_MULTI_5 0x00000005
1054−#define A6XX_CP_DRAW_INDIRECT_MULTI_5_PARAM_0__MASK 0xffffffff
1055−#define A6XX_CP_DRAW_INDIRECT_MULTI_5_PARAM_0__SHIFT 0
1056−static inline uint32_t A6XX_CP_DRAW_INDIRECT_MULTI_5_PARAM_0(uint32_t val)
1057−{
1058− return ((val) << A6XX_CP_DRAW_INDIRECT_MULTI_5_PARAM_0__SHIFT) & A6XX_CP_DRAW_INDIRECT_MULTI_5_PARAM_0__MASK;
1059−}
1057+#define REG_A6XX_CP_DRAW_INDIRECT_MULTI_INDIRECT 0x00000003
1058+
1059+#define REG_A6XX_CP_DRAW_INDIRECT_MULTI_STRIDE 0x00000005
1060+
1061+
1062+#define REG_CP_DRAW_INDIRECT_MULTI_INDEX_INDEXED 0x00000003
1063+
1064+#define REG_CP_DRAW_INDIRECT_MULTI_MAX_INDICES_INDEXED 0x00000005
1065+
1066+#define REG_CP_DRAW_INDIRECT_MULTI_INDIRECT_INDEXED 0x00000006
10601067
1061−#define REG_A6XX_CP_DRAW_INDIRECT_MULTI_INDIRECT 0x00000006
1068+#define REG_CP_DRAW_INDIRECT_MULTI_STRIDE_INDEXED 0x00000008
10621069
1063−#define REG_A6XX_CP_DRAW_INDIRECT_MULTI_8 0x00000008
1064−#define A6XX_CP_DRAW_INDIRECT_MULTI_8_STRIDE__MASK 0xffffffff
1065−#define A6XX_CP_DRAW_INDIRECT_MULTI_8_STRIDE__SHIFT 0
1066−static inline uint32_t A6XX_CP_DRAW_INDIRECT_MULTI_8_STRIDE(uint32_t val)
1070+
1071+#define REG_CP_DRAW_INDIRECT_MULTI_INDIRECT_INDIRECT 0x00000003
1072+
1073+#define REG_CP_DRAW_INDIRECT_MULTI_INDIRECT_COUNT_INDIRECT 0x00000005
1074+
1075+#define REG_CP_DRAW_INDIRECT_MULTI_STRIDE_INDIRECT 0x00000007
1076+
1077+
1078+#define REG_CP_DRAW_INDIRECT_MULTI_INDEX_INDIRECT_INDEXED 0x00000003
1079+
1080+#define REG_CP_DRAW_INDIRECT_MULTI_MAX_INDICES_INDIRECT_INDEXED 0x00000005
1081+
1082+#define REG_CP_DRAW_INDIRECT_MULTI_INDIRECT_INDIRECT_INDEXED 0x00000006
1083+
1084+#define REG_CP_DRAW_INDIRECT_MULTI_INDIRECT_COUNT_INDIRECT_INDEXED 0x00000008
1085+
1086+#define REG_CP_DRAW_INDIRECT_MULTI_STRIDE_INDIRECT_INDEXED 0x0000000a
1087+
1088+#define REG_CP_DRAW_PRED_ENABLE_GLOBAL_0 0x00000000
1089+#define CP_DRAW_PRED_ENABLE_GLOBAL_0_ENABLE 0x00000001
1090+
1091+#define REG_CP_DRAW_PRED_ENABLE_LOCAL_0 0x00000000
1092+#define CP_DRAW_PRED_ENABLE_LOCAL_0_ENABLE 0x00000001
1093+
1094+#define REG_CP_DRAW_PRED_SET_0 0x00000000
1095+#define CP_DRAW_PRED_SET_0_SRC__MASK 0x000000f0
1096+#define CP_DRAW_PRED_SET_0_SRC__SHIFT 4
1097+static inline uint32_t CP_DRAW_PRED_SET_0_SRC(enum cp_draw_pred_src val)
10671098 {
1068− return ((val) << A6XX_CP_DRAW_INDIRECT_MULTI_8_STRIDE__SHIFT) & A6XX_CP_DRAW_INDIRECT_MULTI_8_STRIDE__MASK;
1099+ return ((val) << CP_DRAW_PRED_SET_0_SRC__SHIFT) & CP_DRAW_PRED_SET_0_SRC__MASK;
10691100 }
1101+#define CP_DRAW_PRED_SET_0_TEST__MASK 0x00000100
1102+#define CP_DRAW_PRED_SET_0_TEST__SHIFT 8
1103+static inline uint32_t CP_DRAW_PRED_SET_0_TEST(enum cp_draw_pred_test val)
1104+{
1105+ return ((val) << CP_DRAW_PRED_SET_0_TEST__SHIFT) & CP_DRAW_PRED_SET_0_TEST__MASK;
1106+}
1107+
1108+#define REG_CP_DRAW_PRED_SET_MEM_ADDR 0x00000001
10701109
10711110 static inline uint32_t REG_CP_SET_DRAW_STATE_(uint32_t i0) { return 0x00000000 + 0x3*i0; }
10721111
drivers/gpu/drm/msm/disp/dpu1/dpu_core_irq.c+42−188
@@ -22,165 +22,20 @@ static void dpu_core_irq_callback_handler(void *arg, int irq_idx) · 21 unmodified lines
2222 struct dpu_kms *dpu_kms = arg;
2323 struct dpu_irq *irq_obj = &dpu_kms->irq_obj;
2424 struct dpu_irq_callback *cb;
25− unsigned long irq_flags;
2625
27− pr_debug("irq_idx=%d\n", irq_idx);
26+ VERB("irq_idx=%d\n", irq_idx);
2827
29− if (list_empty(&irq_obj->irq_cb_tbl[irq_idx])) {
30− DRM_ERROR("no registered cb, idx:%d enable_count:%d\n", irq_idx,
31− atomic_read(&dpu_kms->irq_obj.enable_counts[irq_idx]));
32− }
28+ if (list_empty(&irq_obj->irq_cb_tbl[irq_idx]))
29+ DRM_ERROR("no registered cb, idx:%d\n", irq_idx);
3330
3431 atomic_inc(&irq_obj->irq_counts[irq_idx]);
3532
3633 /*
3734 * Perform registered function callback
3835 */
39− spin_lock_irqsave(&dpu_kms->irq_obj.cb_lock, irq_flags);
4036 list_for_each_entry(cb, &irq_obj->irq_cb_tbl[irq_idx], list)
4137 if (cb->func)
4238 cb->func(cb->arg, irq_idx);
43− spin_unlock_irqrestore(&dpu_kms->irq_obj.cb_lock, irq_flags);
44−
45− /*
46− * Clear pending interrupt status in HW.
47− * NOTE: dpu_core_irq_callback_handler is protected by top-level
48− * spinlock, so it is safe to clear any interrupt status here.
49− */
50− dpu_kms->hw_intr->ops.clear_intr_status_nolock(
51− dpu_kms->hw_intr,
52− irq_idx);
53−}
54−
55−int dpu_core_irq_idx_lookup(struct dpu_kms *dpu_kms,
56− enum dpu_intr_type intr_type, u32 instance_idx)
57−{
58− if (!dpu_kms->hw_intr || !dpu_kms->hw_intr->ops.irq_idx_lookup)
59− return -EINVAL;
60−
61− return dpu_kms->hw_intr->ops.irq_idx_lookup(dpu_kms->hw_intr,
62− intr_type, instance_idx);
63−}
64−
65−/**
66− * _dpu_core_irq_enable - enable core interrupt given by the index
67− * @dpu_kms: Pointer to dpu kms context
68− * @irq_idx: interrupt index
69− */
70−static int _dpu_core_irq_enable(struct dpu_kms *dpu_kms, int irq_idx)
71−{
72− unsigned long irq_flags;
73− int ret = 0, enable_count;
74−
75− if (!dpu_kms->hw_intr ||
76− !dpu_kms->irq_obj.enable_counts ||
77− !dpu_kms->irq_obj.irq_counts) {
78− DPU_ERROR("invalid params\n");
79− return -EINVAL;
80− }
81−
82− if (irq_idx < 0 || irq_idx >= dpu_kms->hw_intr->irq_idx_tbl_size) {
83− DPU_ERROR("invalid IRQ index: [%d]\n", irq_idx);
84− return -EINVAL;
85− }
86−
87− enable_count = atomic_read(&dpu_kms->irq_obj.enable_counts[irq_idx]);
88− DRM_DEBUG_KMS("irq_idx=%d enable_count=%d\n", irq_idx, enable_count);
89− trace_dpu_core_irq_enable_idx(irq_idx, enable_count);
90−
91− if (atomic_inc_return(&dpu_kms->irq_obj.enable_counts[irq_idx]) == 1) {
92− ret = dpu_kms->hw_intr->ops.enable_irq(
93− dpu_kms->hw_intr,
94− irq_idx);
95− if (ret)
96− DPU_ERROR("Fail to enable IRQ for irq_idx:%d\n",
97− irq_idx);
98−
99− DPU_DEBUG("irq_idx=%d ret=%d\n", irq_idx, ret);
100−
101− spin_lock_irqsave(&dpu_kms->irq_obj.cb_lock, irq_flags);
102− /* empty callback list but interrupt is enabled */
103− if (list_empty(&dpu_kms->irq_obj.irq_cb_tbl[irq_idx]))
104− DPU_ERROR("irq_idx=%d enabled with no callback\n",
105− irq_idx);
106− spin_unlock_irqrestore(&dpu_kms->irq_obj.cb_lock, irq_flags);
107− }
108−
109− return ret;
110−}
111−
112−int dpu_core_irq_enable(struct dpu_kms *dpu_kms, int *irq_idxs, u32 irq_count)
113−{
114− int i, ret = 0, counts;
115−
116− if (!irq_idxs || !irq_count) {
117− DPU_ERROR("invalid params\n");
118− return -EINVAL;
119− }
120−
121− counts = atomic_read(&dpu_kms->irq_obj.enable_counts[irq_idxs[0]]);
122− if (counts)
123− DRM_ERROR("irq_idx=%d enable_count=%d\n", irq_idxs[0], counts);
124−
125− for (i = 0; (i < irq_count) && !ret; i++)
126− ret = _dpu_core_irq_enable(dpu_kms, irq_idxs[i]);
127−
128− return ret;
129−}
130−
131−/**
132− * _dpu_core_irq_disable - disable core interrupt given by the index
133− * @dpu_kms: Pointer to dpu kms context
134− * @irq_idx: interrupt index
135− */
136−static int _dpu_core_irq_disable(struct dpu_kms *dpu_kms, int irq_idx)
137−{
138− int ret = 0, enable_count;
139−
140− if (!dpu_kms->hw_intr || !dpu_kms->irq_obj.enable_counts) {
141− DPU_ERROR("invalid params\n");
142− return -EINVAL;
143− }
144−
145− if (irq_idx < 0 || irq_idx >= dpu_kms->hw_intr->irq_idx_tbl_size) {
146− DPU_ERROR("invalid IRQ index: [%d]\n", irq_idx);
147− return -EINVAL;
148− }
149−
150− enable_count = atomic_read(&dpu_kms->irq_obj.enable_counts[irq_idx]);
151− DRM_DEBUG_KMS("irq_idx=%d enable_count=%d\n", irq_idx, enable_count);
152− trace_dpu_core_irq_disable_idx(irq_idx, enable_count);
153−
154− if (atomic_dec_return(&dpu_kms->irq_obj.enable_counts[irq_idx]) == 0) {
155− ret = dpu_kms->hw_intr->ops.disable_irq(
156− dpu_kms->hw_intr,
157− irq_idx);
158− if (ret)
159− DPU_ERROR("Fail to disable IRQ for irq_idx:%d\n",
160− irq_idx);
161− DPU_DEBUG("irq_idx=%d ret=%d\n", irq_idx, ret);
162− }
163−
164− return ret;
165−}
166−
167−int dpu_core_irq_disable(struct dpu_kms *dpu_kms, int *irq_idxs, u32 irq_count)
168−{
169− int i, ret = 0, counts;
170−
171− if (!irq_idxs || !irq_count) {
172− DPU_ERROR("invalid params\n");
173− return -EINVAL;
174− }
175−
176− counts = atomic_read(&dpu_kms->irq_obj.enable_counts[irq_idxs[0]]);
177− if (counts == 2)
178− DRM_ERROR("irq_idx=%d enable_count=%d\n", irq_idxs[0], counts);
179−
180− for (i = 0; (i < irq_count) && !ret; i++)
181− ret = _dpu_core_irq_disable(dpu_kms, irq_idxs[i]);
182−
183− return ret;
18439 }
18540
18641 u32 dpu_core_irq_read(struct dpu_kms *dpu_kms, int irq_idx, bool clear)
@@ -217,19 +72,28 @@ int dpu_core_irq_register_callback(struct dpu_kms *dpu_kms, int irq_idx, · 30 unmodified lines
21772 return -EINVAL;
21873 }
21974
220− if (irq_idx < 0 || irq_idx >= dpu_kms->hw_intr->irq_idx_tbl_size) {
75+ if (irq_idx < 0 || irq_idx >= dpu_kms->hw_intr->total_irqs) {
22176 DPU_ERROR("invalid IRQ index: [%d]\n", irq_idx);
22277 return -EINVAL;
22378 }
22479
225− DPU_DEBUG("[%pS] irq_idx=%d\n", __builtin_return_address(0), irq_idx);
80+ VERB("[%pS] irq_idx=%d\n", __builtin_return_address(0), irq_idx);
22681
227− spin_lock_irqsave(&dpu_kms->irq_obj.cb_lock, irq_flags);
82+ irq_flags = dpu_kms->hw_intr->ops.lock(dpu_kms->hw_intr);
22883 trace_dpu_core_irq_register_callback(irq_idx, register_irq_cb);
22984 list_del_init(&register_irq_cb->list);
23085 list_add_tail(&register_irq_cb->list,
23186 &dpu_kms->irq_obj.irq_cb_tbl[irq_idx]);
232− spin_unlock_irqrestore(&dpu_kms->irq_obj.cb_lock, irq_flags);
87+ if (list_is_first(&register_irq_cb->list,
88+ &dpu_kms->irq_obj.irq_cb_tbl[irq_idx])) {
89+ int ret = dpu_kms->hw_intr->ops.enable_irq_locked(
90+ dpu_kms->hw_intr,
91+ irq_idx);
92+ if (ret)
93+ DPU_ERROR("Fail to enable IRQ for irq_idx:%d\n",
94+ irq_idx);
95+ }
96+ dpu_kms->hw_intr->ops.unlock(dpu_kms->hw_intr, irq_flags);
23397
23498 return 0;
23599 }
@@ -252,21 +116,27 @@ int dpu_core_irq_unregister_callback(struct dpu_kms *dpu_kms, int irq_idx, · 16 unmodified lines
252116 return -EINVAL;
253117 }
254118
255− if (irq_idx < 0 || irq_idx >= dpu_kms->hw_intr->irq_idx_tbl_size) {
119+ if (irq_idx < 0 || irq_idx >= dpu_kms->hw_intr->total_irqs) {
256120 DPU_ERROR("invalid IRQ index: [%d]\n", irq_idx);
257121 return -EINVAL;
258122 }
259123
260− DPU_DEBUG("[%pS] irq_idx=%d\n", __builtin_return_address(0), irq_idx);
124+ VERB("[%pS] irq_idx=%d\n", __builtin_return_address(0), irq_idx);
261125
262− spin_lock_irqsave(&dpu_kms->irq_obj.cb_lock, irq_flags);
126+ irq_flags = dpu_kms->hw_intr->ops.lock(dpu_kms->hw_intr);
263127 trace_dpu_core_irq_unregister_callback(irq_idx, register_irq_cb);
264128 list_del_init(&register_irq_cb->list);
265129 /* empty callback list but interrupt is still enabled */
266− if (list_empty(&dpu_kms->irq_obj.irq_cb_tbl[irq_idx]) &&
267− atomic_read(&dpu_kms->irq_obj.enable_counts[irq_idx]))
268− DPU_ERROR("irq_idx=%d enabled with no callback\n", irq_idx);
269− spin_unlock_irqrestore(&dpu_kms->irq_obj.cb_lock, irq_flags);
130+ if (list_empty(&dpu_kms->irq_obj.irq_cb_tbl[irq_idx])) {
131+ int ret = dpu_kms->hw_intr->ops.disable_irq_locked(
132+ dpu_kms->hw_intr,
133+ irq_idx);
134+ if (ret)
135+ DPU_ERROR("Fail to disable IRQ for irq_idx:%d\n",
136+ irq_idx);
137+ VERB("irq_idx=%d ret=%d\n", irq_idx, ret);
138+ }
139+ dpu_kms->hw_intr->ops.unlock(dpu_kms->hw_intr, irq_flags);
270140
271141 return 0;
272142 }
@@ -290,26 +160,26 @@ static void dpu_disable_all_irqs(struct dpu_kms *dpu_kms) · 17 unmodified lines
290160 #ifdef CONFIG_DEBUG_FS
291161 static int dpu_debugfs_core_irq_show(struct seq_file *s, void *v)
292162 {
293− struct dpu_irq *irq_obj = s->private;
163+ struct dpu_kms *dpu_kms = s->private;
164+ struct dpu_irq *irq_obj = &dpu_kms->irq_obj;
294165 struct dpu_irq_callback *cb;
295166 unsigned long irq_flags;
296− int i, irq_count, enable_count, cb_count;
167+ int i, irq_count, cb_count;
297168
298− if (WARN_ON(!irq_obj->enable_counts || !irq_obj->irq_cb_tbl))
169+ if (WARN_ON(!irq_obj->irq_cb_tbl))
299170 return 0;
300171
301172 for (i = 0; i < irq_obj->total_irqs; i++) {
302− spin_lock_irqsave(&irq_obj->cb_lock, irq_flags);
173+ irq_flags = dpu_kms->hw_intr->ops.lock(dpu_kms->hw_intr);
303174 cb_count = 0;
304175 irq_count = atomic_read(&irq_obj->irq_counts[i]);
305− enable_count = atomic_read(&irq_obj->enable_counts[i]);
306176 list_for_each_entry(cb, &irq_obj->irq_cb_tbl[i], list)
307177 cb_count++;
308− spin_unlock_irqrestore(&irq_obj->cb_lock, irq_flags);
178+ dpu_kms->hw_intr->ops.unlock(dpu_kms->hw_intr, irq_flags);
309179
310− if (irq_count || enable_count || cb_count)
311− seq_printf(s, "idx:%d irq:%d enable:%d cb:%d\n",
312− i, irq_count, enable_count, cb_count);
180+ if (irq_count || cb_count)
181+ seq_printf(s, "idx:%d irq:%d cb:%d\n",
182+ i, irq_count, cb_count);
313183 }
314184
315185 return 0;
@@ -320,7 +190,7 @@ DEFINE_SHOW_ATTRIBUTE(dpu_debugfs_core_irq); · 4 unmodified lines
320190 void dpu_debugfs_core_irq_init(struct dpu_kms *dpu_kms,
321191 struct dentry *parent)
322192 {
323− debugfs_create_file("core_irq", 0600, parent, &dpu_kms->irq_obj,
193+ debugfs_create_file("core_irq", 0600, parent, dpu_kms,
324194 &dpu_debugfs_core_irq_fops);
325195 }
326196 #endif
@@ -334,19 +204,14 @@ void dpu_core_irq_preinstall(struct dpu_kms *dpu_kms) · 7 unmodified lines
334204 dpu_disable_all_irqs(dpu_kms);
335205 pm_runtime_put_sync(&dpu_kms->pdev->dev);
336206
337− spin_lock_init(&dpu_kms->irq_obj.cb_lock);
338−
339207 /* Create irq callbacks for all possible irq_idx */
340− dpu_kms->irq_obj.total_irqs = dpu_kms->hw_intr->irq_idx_tbl_size;
208+ dpu_kms->irq_obj.total_irqs = dpu_kms->hw_intr->total_irqs;
341209 dpu_kms->irq_obj.irq_cb_tbl = kcalloc(dpu_kms->irq_obj.total_irqs,
342210 sizeof(struct list_head), GFP_KERNEL);
343− dpu_kms->irq_obj.enable_counts = kcalloc(dpu_kms->irq_obj.total_irqs,
344− sizeof(atomic_t), GFP_KERNEL);
345211 dpu_kms->irq_obj.irq_counts = kcalloc(dpu_kms->irq_obj.total_irqs,
346212 sizeof(atomic_t), GFP_KERNEL);
347213 for (i = 0; i < dpu_kms->irq_obj.total_irqs; i++) {
348214 INIT_LIST_HEAD(&dpu_kms->irq_obj.irq_cb_tbl[i]);
349− atomic_set(&dpu_kms->irq_obj.enable_counts[i], 0);
350215 atomic_set(&dpu_kms->irq_obj.irq_counts[i], 0);
351216 }
352217 }
@@ -357,8 +222,7 @@ void dpu_core_irq_uninstall(struct dpu_kms *dpu_kms) · 4 unmodified lines
357222
358223 pm_runtime_get_sync(&dpu_kms->pdev->dev);
359224 for (i = 0; i < dpu_kms->irq_obj.total_irqs; i++)
360− if (atomic_read(&dpu_kms->irq_obj.enable_counts[i]) ||
361− !list_empty(&dpu_kms->irq_obj.irq_cb_tbl[i]))
225+ if (!list_empty(&dpu_kms->irq_obj.irq_cb_tbl[i]))
362226 DPU_ERROR("irq_idx=%d still enabled/registered\n", i);
363227
364228 dpu_clear_all_irqs(dpu_kms);
@@ -366,25 +230,14 @@ void dpu_core_irq_uninstall(struct dpu_kms *dpu_kms) · 1 unmodified line
366230 pm_runtime_put_sync(&dpu_kms->pdev->dev);
367231
368232 kfree(dpu_kms->irq_obj.irq_cb_tbl);
369− kfree(dpu_kms->irq_obj.enable_counts);
370233 kfree(dpu_kms->irq_obj.irq_counts);
371234 dpu_kms->irq_obj.irq_cb_tbl = NULL;
372− dpu_kms->irq_obj.enable_counts = NULL;
373235 dpu_kms->irq_obj.irq_counts = NULL;
374236 dpu_kms->irq_obj.total_irqs = 0;
375237 }
376238
377239 irqreturn_t dpu_core_irq(struct dpu_kms *dpu_kms)
378240 {
379− /*
380− * Read interrupt status from all sources. Interrupt status are
381− * stored within hw_intr.
382− * Function will also clear the interrupt status after reading.
383− * Individual interrupt status bit will only get stored if it
384− * is enabled.
385− */
386− dpu_kms->hw_intr->ops.get_interrupt_statuses(dpu_kms->hw_intr);
387−
388241 /*
389242 * Dispatch to HW driver to handle interrupt lookup that is being
390243 * fired. When matching interrupt is located, HW driver will call to
@@ -392,6 +245,7 @@ irqreturn_t dpu_core_irq(struct dpu_kms *dpu_kms) · 1 unmodified line
392245 * dpu_core_irq_callback_handler will perform the registered function
393246 * callback, and do the interrupt status clearing once the registered
394247 * callback is finished.
248+ * Function will also clear the interrupt status after reading.
395249 */
396250 dpu_kms->hw_intr->ops.dispatch_irqs(
397251 dpu_kms->hw_intr,
drivers/gpu/drm/msm/disp/dpu1/dpu_core_irq.h+0−43
@@ -29,49 +29,6 @@ void dpu_core_irq_uninstall(struct dpu_kms *dpu_kms); · 28 unmodified lines
2929 */
3030 irqreturn_t dpu_core_irq(struct dpu_kms *dpu_kms);
3131
32−/**
33− * dpu_core_irq_idx_lookup - IRQ helper function for lookup irq_idx from HW
34− * interrupt mapping table.
35− * @dpu_kms: DPU handle
36− * @intr_type: DPU HW interrupt type for lookup
37− * @instance_idx: DPU HW block instance defined in dpu_hw_mdss.h
38− * @return: irq_idx or -EINVAL when fail to lookup
39− */
40−int dpu_core_irq_idx_lookup(
41− struct dpu_kms *dpu_kms,
42− enum dpu_intr_type intr_type,
43− uint32_t instance_idx);
44−
45−/**
46− * dpu_core_irq_enable - IRQ helper function for enabling one or more IRQs
47− * @dpu_kms: DPU handle
48− * @irq_idxs: Array of irq index
49− * @irq_count: Number of irq_idx provided in the array
50− * @return: 0 for success enabling IRQ, otherwise failure
51− *
52− * This function increments count on each enable and decrements on each
53− * disable. Interrupts is enabled if count is 0 before increment.
54− */
55−int dpu_core_irq_enable(
56− struct dpu_kms *dpu_kms,
57− int *irq_idxs,
58− uint32_t irq_count);
59−
60−/**
61− * dpu_core_irq_disable - IRQ helper function for disabling one of more IRQs
62− * @dpu_kms: DPU handle
63− * @irq_idxs: Array of irq index
64− * @irq_count: Number of irq_idx provided in the array
65− * @return: 0 for success disabling IRQ, otherwise failure
66− *
67− * This function increments count on each enable and decrements on each
68− * disable. Interrupts is disabled if count is 0 after decrement.
69− */
70−int dpu_core_irq_disable(
71− struct dpu_kms *dpu_kms,
72− int *irq_idxs,
73− uint32_t irq_count);
74−
7532 /**
7633 * dpu_core_irq_read - IRQ helper function for reading IRQ status
7734 * @dpu_kms: DPU handle
drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c+11−11
@@ -132,7 +132,7 @@ static void _dpu_core_perf_calc_crtc(struct dpu_kms *kms, · 131 unmodified lines
132132 perf->core_clk_rate = _dpu_core_perf_calc_clk(kms, crtc, state);
133133 }
134134
135− DPU_DEBUG(
135+ DRM_DEBUG_ATOMIC(
136136 "crtc=%d clk_rate=%llu core_ib=%llu core_ab=%llu\n",
137137 crtc->base.id, perf->core_clk_rate,
138138 perf->max_per_pipe_ib, perf->bw_ctl);
@@ -178,7 +178,7 @@ int dpu_core_perf_crtc_check(struct drm_crtc *crtc, · 39 unmodified lines
178178 struct dpu_crtc_state *tmp_cstate =
179179 to_dpu_crtc_state(tmp_crtc->state);
180180
181− DPU_DEBUG("crtc:%d bw:%llu ctrl:%d\n",
181+ DRM_DEBUG_ATOMIC("crtc:%d bw:%llu ctrl:%d\n",
182182 tmp_crtc->base.id, tmp_cstate->new_perf.bw_ctl,
183183 tmp_cstate->bw_control);
184184
@@ -187,11 +187,11 @@ int dpu_core_perf_crtc_check(struct drm_crtc *crtc, · 2 unmodified lines
187187
188188 /* convert bandwidth to kb */
189189 bw = DIV_ROUND_UP_ULL(bw_sum_of_intfs, 1000);
190− DPU_DEBUG("calculated bandwidth=%uk\n", bw);
190+ DRM_DEBUG_ATOMIC("calculated bandwidth=%uk\n", bw);
191191
192192 threshold = kms->catalog->perf.max_bw_high;
193193
194− DPU_DEBUG("final threshold bw limit = %d\n", threshold);
194+ DRM_DEBUG_ATOMIC("final threshold bw limit = %d\n", threshold);
195195
196196 if (!threshold) {
197197 DPU_ERROR("no bandwidth limits specified\n");
@@ -228,7 +228,7 @@ static int _dpu_core_perf_crtc_update_bus(struct dpu_kms *kms, · 30 unmodified lines
228228
229229 perf.bw_ctl += dpu_cstate->new_perf.bw_ctl;
230230
231− DPU_DEBUG("crtc=%d bw=%llu paths:%d\n",
231+ DRM_DEBUG_ATOMIC("crtc=%d bw=%llu paths:%d\n",
232232 tmp_crtc->base.id,
233233 dpu_cstate->new_perf.bw_ctl, kms->num_paths);
234234 }
@@ -278,7 +278,7 @@ void dpu_core_perf_crtc_release_bw(struct drm_crtc *crtc) · 43 unmodified lines
278278 /* Release the bandwidth */
279279 if (kms->perf.enable_bw_release) {
280280 trace_dpu_cmd_release_bw(crtc->base.id);
281− DPU_DEBUG("Release BW crtc=%d\n", crtc->base.id);
281+ DRM_DEBUG_ATOMIC("Release BW crtc=%d\n", crtc->base.id);
282282 dpu_crtc->cur_perf.bw_ctl = 0;
283283 _dpu_core_perf_crtc_update_bus(kms, crtc);
284284 }
@@ -314,7 +314,7 @@ static u64 _dpu_core_perf_get_core_clk_rate(struct dpu_kms *kms) · 29 unmodified lines
314314 if (kms->perf.perf_tune.mode == DPU_PERF_MODE_FIXED)
315315 clk_rate = kms->perf.fix_core_clk_rate;
316316
317− DPU_DEBUG("clk:%llu\n", clk_rate);
317+ DRM_DEBUG_ATOMIC("clk:%llu\n", clk_rate);
318318
319319 return clk_rate;
320320 }
@@ -344,7 +344,7 @@ int dpu_core_perf_crtc_update(struct drm_crtc *crtc, · 23 unmodified lines
344344 dpu_crtc = to_dpu_crtc(crtc);
345345 dpu_cstate = to_dpu_crtc_state(crtc->state);
346346
347− DPU_DEBUG("crtc:%d stop_req:%d core_clk:%llu\n",
347+ DRM_DEBUG_ATOMIC("crtc:%d stop_req:%d core_clk:%llu\n",
348348 crtc->base.id, stop_req, kms->perf.core_clk_rate);
349349
350350 old = &dpu_crtc->cur_perf;
@@ -362,7 +362,7 @@ int dpu_core_perf_crtc_update(struct drm_crtc *crtc, · 11 unmodified lines
362362 (new->max_per_pipe_ib > old->max_per_pipe_ib))) ||
363363 (!params_changed && ((new->bw_ctl < old->bw_ctl) ||
364364 (new->max_per_pipe_ib < old->max_per_pipe_ib)))) {
365− DPU_DEBUG("crtc=%d p=%d new_bw=%llu,old_bw=%llu\n",
365+ DRM_DEBUG_ATOMIC("crtc=%d p=%d new_bw=%llu,old_bw=%llu\n",
366366 crtc->base.id, params_changed,
367367 new->bw_ctl, old->bw_ctl);
368368 old->bw_ctl = new->bw_ctl;
@@ -378,7 +378,7 @@ int dpu_core_perf_crtc_update(struct drm_crtc *crtc, · 9 unmodified lines
378378 update_clk = true;
379379 }
380380 } else {
381− DPU_DEBUG("crtc=%d disable\n", crtc->base.id);
381+ DRM_DEBUG_ATOMIC("crtc=%d disable\n", crtc->base.id);
382382 memset(old, 0, sizeof(*old));
383383 update_bus = true;
384384 update_clk = true;
@@ -413,7 +413,7 @@ int dpu_core_perf_crtc_update(struct drm_crtc *crtc, · 28 unmodified lines
413413 }
414414
415415 kms->perf.core_clk_rate = clk_rate;
416− DPU_DEBUG("update clk rate = %lld HZ\n", clk_rate);
416+ DRM_DEBUG_ATOMIC("update clk rate = %lld HZ\n", clk_rate);
417417 }
418418 return 0;
419419 }
drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c+20−23
@@ -57,8 +57,6 @@ static void dpu_crtc_destroy(struct drm_crtc *crtc) · 56 unmodified lines
5757 {
5858 struct dpu_crtc *dpu_crtc = to_dpu_crtc(crtc);
5959
60− DPU_DEBUG("\n");
61−
6260 if (!crtc)
6361 return;
6462
@@ -163,7 +161,7 @@ static void _dpu_crtc_setup_blend_cfg(struct dpu_crtc_mixer *mixer, · 98 unmodified lines
163161 lm->ops.setup_blend_config(lm, pstate->stage,
164162 0xFF, 0, blend_op);
165163
166− DPU_DEBUG("format:%p4cc, alpha_en:%u blend_op:0x%x\n",
164+ DRM_DEBUG_ATOMIC("format:%p4cc, alpha_en:%u blend_op:0x%x\n",
167165 &format->base.pixel_format, format->alpha_enable, blend_op);
168166 }
169167
@@ -220,7 +218,8 @@ static void _dpu_crtc_blend_setup_mixer(struct drm_crtc *crtc, · 50 unmodified lines
220218
221219 dpu_plane_get_ctl_flush(plane, ctl, &flush_mask);
222220 set_bit(dpu_plane_pipe(plane), fetch_active);
223− DPU_DEBUG("crtc %d stage:%d - plane %d sspp %d fb %d\n",
221+
222+ DRM_DEBUG_ATOMIC("crtc %d stage:%d - plane %d sspp %d fb %d\n",
224223 crtc->base.id,
225224 pstate->stage,
226225 plane->base.id,
@@ -278,7 +277,7 @@ static void _dpu_crtc_blend_setup(struct drm_crtc *crtc) · 51 unmodified lines
278277 struct dpu_hw_mixer *lm;
279278 int i;
280279
281− DPU_DEBUG("%s\n", dpu_crtc->name);
280+ DRM_DEBUG_ATOMIC("%s\n", dpu_crtc->name);
282281
283282 for (i = 0; i < cstate->num_mixers; i++) {
284283 mixer[i].mixer_op_mode = 0;
@@ -305,7 +304,7 @@ static void _dpu_crtc_blend_setup(struct drm_crtc *crtc) · 20 unmodified lines
305304 /* stage config flush mask */
306305 ctl->ops.update_pending_flush(ctl, mixer[i].flush_mask);
307306
308− DPU_DEBUG("lm %d, op_mode 0x%X, ctl %d, flush mask 0x%x\n",
307+ DRM_DEBUG_ATOMIC("lm %d, op_mode 0x%X, ctl %d, flush mask 0x%x\n",
309308 mixer[i].hw_lm->idx - LM_0,
310309 mixer[i].mixer_op_mode,
311310 ctl->idx - CTL_0,
@@ -388,7 +387,7 @@ static void dpu_crtc_frame_event_work(struct kthread_work *work) · 76 unmodified lines
388387
389388 DPU_ATRACE_BEGIN("crtc_frame_event");
390389
391− DRM_DEBUG_KMS("crtc%d event:%u ts:%lld\n", crtc->base.id, fevent->event,
390+ DRM_DEBUG_ATOMIC("crtc%d event:%u ts:%lld\n", crtc->base.id, fevent->event,
392391 ktime_to_ns(fevent->ts));
393392
394393 if (fevent->event & (DPU_ENCODER_FRAME_EVENT_DONE
@@ -407,9 +406,6 @@ static void dpu_crtc_frame_event_work(struct kthread_work *work) · 12 unmodified lines
407406 fevent->event);
408407 }
409408
410− if (fevent->event & DPU_ENCODER_FRAME_EVENT_DONE)
411− dpu_core_perf_crtc_update(crtc, 0, false);
412−
413409 if (fevent->event & (DPU_ENCODER_FRAME_EVENT_DONE
414410 | DPU_ENCODER_FRAME_EVENT_ERROR))
415411 frame_done = true;
@@ -477,6 +473,7 @@ static void dpu_crtc_frame_event_cb(void *data, u32 event) · 61 unmodified lines
477473 void dpu_crtc_complete_commit(struct drm_crtc *crtc)
478474 {
479475 trace_dpu_crtc_complete_commit(DRMID(crtc));
476+ dpu_core_perf_crtc_update(crtc, 0, false);
480477 _dpu_crtc_complete_flip(crtc);
481478 }
482479
@@ -558,7 +555,7 @@ static void _dpu_crtc_setup_cp_blocks(struct drm_crtc *crtc) · 75 unmodified lines
558555 /* stage config flush mask */
559556 ctl->ops.update_pending_flush(ctl, mixer[i].flush_mask);
560557
561− DPU_DEBUG("lm %d, ctl %d, flush mask 0x%x\n",
558+ DRM_DEBUG_ATOMIC("lm %d, ctl %d, flush mask 0x%x\n",
562559 mixer[i].hw_lm->idx - DSPP_0,
563560 ctl->idx - CTL_0,
564561 mixer[i].flush_mask);
@@ -572,12 +569,12 @@ static void dpu_crtc_atomic_begin(struct drm_crtc *crtc, · 7 unmodified lines
572569 struct drm_encoder *encoder;
573570
574571 if (!crtc->state->enable) {
575− DPU_DEBUG("crtc%d -> enable %d, skip atomic_begin\n",
572+ DRM_DEBUG_ATOMIC("crtc%d -> enable %d, skip atomic_begin\n",
576573 crtc->base.id, crtc->state->enable);
577574 return;
578575 }
579576
580− DPU_DEBUG("crtc%d\n", crtc->base.id);
577+ DRM_DEBUG_ATOMIC("crtc%d\n", crtc->base.id);
581578
582579 _dpu_crtc_setup_lm_bounds(crtc, crtc->state);
583580
@@ -617,12 +614,12 @@ static void dpu_crtc_atomic_flush(struct drm_crtc *crtc, · 33 unmodified lines
617614 struct dpu_crtc_state *cstate;
618615
619616 if (!crtc->state->enable) {
620− DPU_DEBUG("crtc%d -> enable %d, skip atomic_flush\n",
617+ DRM_DEBUG_ATOMIC("crtc%d -> enable %d, skip atomic_flush\n",
621618 crtc->base.id, crtc->state->enable);
622619 return;
623620 }
624621
625− DPU_DEBUG("crtc%d\n", crtc->base.id);
622+ DRM_DEBUG_ATOMIC("crtc%d\n", crtc->base.id);
626623
627624 dpu_crtc = to_dpu_crtc(crtc);
628625 cstate = to_dpu_crtc_state(crtc->state);
@@ -675,7 +672,7 @@ static void dpu_crtc_destroy_state(struct drm_crtc *crtc, · 46 unmodified lines
675672 {
676673 struct dpu_crtc_state *cstate = to_dpu_crtc_state(state);
677674
678− DPU_DEBUG("crtc%d\n", crtc->base.id);
675+ DRM_DEBUG_ATOMIC("crtc%d\n", crtc->base.id);
679676
680677 __drm_atomic_helper_crtc_destroy_state(state);
681678
@@ -688,7 +685,7 @@ static int _dpu_crtc_wait_for_frame_done(struct drm_crtc *crtc) · 6 unmodified lines
688685 int ret, rc = 0;
689686
690687 if (!atomic_read(&dpu_crtc->frame_pending)) {
691− DPU_DEBUG("no frames pending\n");
688+ DRM_DEBUG_ATOMIC("no frames pending\n");
692689 return 0;
693690 }
694691
@@ -731,9 +728,9 @@ void dpu_crtc_commit_kickoff(struct drm_crtc *crtc) · 36 unmodified lines
731728
732729 if (atomic_inc_return(&dpu_crtc->frame_pending) == 1) {
733730 /* acquire bandwidth and other resources */
734− DPU_DEBUG("crtc%d first commit\n", crtc->base.id);
731+ DRM_DEBUG_ATOMIC("crtc%d first commit\n", crtc->base.id);
735732 } else
736− DPU_DEBUG("crtc%d commit\n", crtc->base.id);
733+ DRM_DEBUG_ATOMIC("crtc%d commit\n", crtc->base.id);
737734
738735 dpu_crtc->play_count++;
739736
@@ -908,7 +905,7 @@ static int dpu_crtc_atomic_check(struct drm_crtc *crtc, · 168 unmodified lines
908905 pstates = kzalloc(sizeof(*pstates) * DPU_STAGE_MAX * 4, GFP_KERNEL);
909906
910907 if (!crtc_state->enable || !crtc_state->active) {
911− DPU_DEBUG("crtc%d -> enable %d, active %d, skip atomic_check\n",
908+ DRM_DEBUG_ATOMIC("crtc%d -> enable %d, active %d, skip atomic_check\n",
912909 crtc->base.id, crtc_state->enable,
913910 crtc_state->active);
914911 memset(&cstate->new_perf, 0, sizeof(cstate->new_perf));
@@ -916,7 +913,7 @@ static int dpu_crtc_atomic_check(struct drm_crtc *crtc, · 1 unmodified line
916913 }
917914
918915 mode = &crtc_state->adjusted_mode;
919− DPU_DEBUG("%s: check\n", dpu_crtc->name);
916+ DRM_DEBUG_ATOMIC("%s: check\n", dpu_crtc->name);
920917
921918 /* force a full mode set if active state changed */
922919 if (crtc_state->active_changed)
@@ -1024,7 +1021,7 @@ static int dpu_crtc_atomic_check(struct drm_crtc *crtc, · 101 unmodified lines
10241021 }
10251022
10261023 pstates[i].dpu_pstate->stage = z_pos + DPU_STAGE_0;
1027− DPU_DEBUG("%s: zpos %d\n", dpu_crtc->name, z_pos);
1024+ DRM_DEBUG_ATOMIC("%s: zpos %d\n", dpu_crtc->name, z_pos);
10281025 }
10291026
10301027 for (i = 0; i < multirect_count; i++) {
@@ -1376,6 +1373,6 @@ struct drm_crtc *dpu_crtc_init(struct drm_device *dev, struct drm_plane *plane, · 345 unmodified lines
13761373 /* initialize event handling */
13771374 spin_lock_init(&dpu_crtc->event_lock);
13781375
1379− DPU_DEBUG("%s: successfully initialized crtc\n", dpu_crtc->name);
1376+ DRM_DEBUG_KMS("%s: successfully initialized crtc\n", dpu_crtc->name);
13801377 return crtc;
13811378 }
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c+39−71
@@ -1,6 +1,6 @@
11 // SPDX-License-Identifier: GPL-2.0-only
22 /*
3− * Copyright (c) 2014-2018, The Linux Foundation. All rights reserved.
3+ * Copyright (c) 2014-2018, 2020-2021 The Linux Foundation. All rights reserved.
44 * Copyright (C) 2013 Red Hat
55 * Author: Rob Clark <robdclark@gmail.com>
66 */
@@ -26,14 +26,15 @@ · 19 unmodified lines
2626 #include "dpu_crtc.h"
2727 #include "dpu_trace.h"
2828 #include "dpu_core_irq.h"
29+#include "disp/msm_disp_snapshot.h"
2930
30−#define DPU_DEBUG_ENC(e, fmt, ...) DPU_DEBUG("enc%d " fmt,\
31+#define DPU_DEBUG_ENC(e, fmt, ...) DRM_DEBUG_ATOMIC("enc%d " fmt,\
3132 (e) ? (e)->base.base.id : -1, ##__VA_ARGS__)
3233
3334 #define DPU_ERROR_ENC(e, fmt, ...) DPU_ERROR("enc%d " fmt,\
3435 (e) ? (e)->base.base.id : -1, ##__VA_ARGS__)
3536
36−#define DPU_DEBUG_PHYS(p, fmt, ...) DPU_DEBUG("enc%d intf%d pp%d " fmt,\
37+#define DPU_DEBUG_PHYS(p, fmt, ...) DRM_DEBUG_ATOMIC("enc%d intf%d pp%d " fmt,\
3738 (p) ? (p)->parent->base.id : -1, \
3839 (p) ? (p)->intf_idx - INTF_0 : -1, \
3940 (p) ? ((p)->hw_pp ? (p)->hw_pp->idx - PINGPONG_0 : -1) : -1, \
@@ -253,7 +254,7 @@ void dpu_encoder_helper_report_irq_timeout(struct dpu_encoder_phys *phys_enc, · 213 unmodified lines
253254 }
254255
255256 static int dpu_encoder_helper_wait_event_timeout(int32_t drm_id,
256− int32_t hw_id, struct dpu_encoder_wait_info *info);
257+ u32 irq_idx, struct dpu_encoder_wait_info *info);
257258
258259 int dpu_encoder_helper_wait_for_irq(struct dpu_encoder_phys *phys_enc,
259260 enum dpu_intr_idx intr_idx,
@@ -273,27 +274,27 @@ int dpu_encoder_helper_wait_for_irq(struct dpu_encoder_phys *phys_enc, · 13 unmodified lines
273274
274275 /* return EWOULDBLOCK since we know the wait isn't necessary */
275276 if (phys_enc->enable_state == DPU_ENC_DISABLED) {
276− DRM_ERROR("encoder is disabled id=%u, intr=%d, hw=%d, irq=%d",
277− DRMID(phys_enc->parent), intr_idx, irq->hw_idx,
277+ DRM_ERROR("encoder is disabled id=%u, intr=%d, irq=%d",
278+ DRMID(phys_enc->parent), intr_idx,
278279 irq->irq_idx);
279280 return -EWOULDBLOCK;
280281 }
281282
282283 if (irq->irq_idx < 0) {
283− DRM_DEBUG_KMS("skip irq wait id=%u, intr=%d, hw=%d, irq=%s",
284− DRMID(phys_enc->parent), intr_idx, irq->hw_idx,
284+ DRM_DEBUG_KMS("skip irq wait id=%u, intr=%d, irq=%s",
285+ DRMID(phys_enc->parent), intr_idx,
285286 irq->name);
286287 return 0;
287288 }
288289
289− DRM_DEBUG_KMS("id=%u, intr=%d, hw=%d, irq=%d, pp=%d, pending_cnt=%d",
290− DRMID(phys_enc->parent), intr_idx, irq->hw_idx,
290+ DRM_DEBUG_KMS("id=%u, intr=%d, irq=%d, pp=%d, pending_cnt=%d",
291+ DRMID(phys_enc->parent), intr_idx,
291292 irq->irq_idx, phys_enc->hw_pp->idx - PINGPONG_0,
292293 atomic_read(wait_info->atomic_cnt));
293294
294295 ret = dpu_encoder_helper_wait_event_timeout(
295296 DRMID(phys_enc->parent),
296− irq->hw_idx,
297+ irq->irq_idx,
297298 wait_info);
298299
299300 if (ret <= 0) {
@@ -303,9 +304,9 @@ int dpu_encoder_helper_wait_for_irq(struct dpu_encoder_phys *phys_enc, · 3 unmodified lines
303304 unsigned long flags;
304305
305306 DRM_DEBUG_KMS("irq not triggered id=%u, intr=%d, "
306− "hw=%d, irq=%d, pp=%d, atomic_cnt=%d",
307+ "irq=%d, pp=%d, atomic_cnt=%d",
307308 DRMID(phys_enc->parent), intr_idx,
308− irq->hw_idx, irq->irq_idx,
309+ irq->irq_idx,
309310 phys_enc->hw_pp->idx - PINGPONG_0,
310311 atomic_read(wait_info->atomic_cnt));
311312 local_irq_save(flags);
@@ -315,16 +316,16 @@ int dpu_encoder_helper_wait_for_irq(struct dpu_encoder_phys *phys_enc, · 3 unmodified lines
315316 } else {
316317 ret = -ETIMEDOUT;
317318 DRM_DEBUG_KMS("irq timeout id=%u, intr=%d, "
318− "hw=%d, irq=%d, pp=%d, atomic_cnt=%d",
319+ "irq=%d, pp=%d, atomic_cnt=%d",
319320 DRMID(phys_enc->parent), intr_idx,
320− irq->hw_idx, irq->irq_idx,
321+ irq->irq_idx,
321322 phys_enc->hw_pp->idx - PINGPONG_0,
322323 atomic_read(wait_info->atomic_cnt));
323324 }
324325 } else {
325326 ret = 0;
326327 trace_dpu_enc_irq_wait_success(DRMID(phys_enc->parent),
327− intr_idx, irq->hw_idx, irq->irq_idx,
328+ intr_idx, irq->irq_idx,
328329 phys_enc->hw_pp->idx - PINGPONG_0,
329330 atomic_read(wait_info->atomic_cnt));
330331 }
@@ -344,19 +345,9 @@ int dpu_encoder_helper_register_irq(struct dpu_encoder_phys *phys_enc, · 13 unmodified lines
344345 }
345346 irq = &phys_enc->irq[intr_idx];
346347
347− if (irq->irq_idx >= 0) {
348− DPU_DEBUG_PHYS(phys_enc,
349− "skipping already registered irq %s type %d\n",
350− irq->name, irq->intr_type);
351− return 0;
352− }
353−
354− irq->irq_idx = dpu_core_irq_idx_lookup(phys_enc->dpu_kms,
355− irq->intr_type, irq->hw_idx);
356348 if (irq->irq_idx < 0) {
357349 DPU_ERROR_PHYS(phys_enc,
358− "failed to lookup IRQ index for %s type:%d\n",
359− irq->name, irq->intr_type);
350+ "invalid IRQ index:%d\n", irq->irq_idx);
360351 return -EINVAL;
361352 }
362353
@@ -370,19 +361,8 @@ int dpu_encoder_helper_register_irq(struct dpu_encoder_phys *phys_enc, · 7 unmodified lines
370361 return ret;
371362 }
372363
373− ret = dpu_core_irq_enable(phys_enc->dpu_kms, &irq->irq_idx, 1);
374− if (ret) {
375− DRM_ERROR("enable failed id=%u, intr=%d, hw=%d, irq=%d",
376− DRMID(phys_enc->parent), intr_idx, irq->hw_idx,
377− irq->irq_idx);
378− dpu_core_irq_unregister_callback(phys_enc->dpu_kms,
379− irq->irq_idx, &irq->cb);
380− irq->irq_idx = -EINVAL;
381− return ret;
382− }
383−
384364 trace_dpu_enc_irq_register_success(DRMID(phys_enc->parent), intr_idx,
385− irq->hw_idx, irq->irq_idx);
365+ irq->irq_idx);
386366
387367 return ret;
388368 }
@@ -397,31 +377,22 @@ int dpu_encoder_helper_unregister_irq(struct dpu_encoder_phys *phys_enc, · 8 unmodified lines
397377
398378 /* silently skip irqs that weren't registered */
399379 if (irq->irq_idx < 0) {
400− DRM_ERROR("duplicate unregister id=%u, intr=%d, hw=%d, irq=%d",
401− DRMID(phys_enc->parent), intr_idx, irq->hw_idx,
380+ DRM_ERROR("duplicate unregister id=%u, intr=%d, irq=%d",
381+ DRMID(phys_enc->parent), intr_idx,
402382 irq->irq_idx);
403383 return 0;
404384 }
405385
406− ret = dpu_core_irq_disable(phys_enc->dpu_kms, &irq->irq_idx, 1);
407− if (ret) {
408− DRM_ERROR("disable failed id=%u, intr=%d, hw=%d, irq=%d ret=%d",
409− DRMID(phys_enc->parent), intr_idx, irq->hw_idx,
410− irq->irq_idx, ret);
411− }
412−
413386 ret = dpu_core_irq_unregister_callback(phys_enc->dpu_kms, irq->irq_idx,
414387 &irq->cb);
415388 if (ret) {
416− DRM_ERROR("unreg cb fail id=%u, intr=%d, hw=%d, irq=%d ret=%d",
417− DRMID(phys_enc->parent), intr_idx, irq->hw_idx,
389+ DRM_ERROR("unreg cb fail id=%u, intr=%d, irq=%d ret=%d",
390+ DRMID(phys_enc->parent), intr_idx,
418391 irq->irq_idx, ret);
419392 }
420393
421394 trace_dpu_enc_irq_unregister_success(DRMID(phys_enc->parent), intr_idx,
422− irq->hw_idx, irq->irq_idx);
423−
424− irq->irq_idx = -EINVAL;
395+ irq->irq_idx);
425396
426397 return 0;
427398 }
@@ -820,13 +791,13 @@ static int dpu_encoder_resource_control(struct drm_encoder *drm_enc, · 392 unmodified lines
820791
821792 /* return if the resource control is already in ON state */
822793 if (dpu_enc->rc_state == DPU_ENC_RC_STATE_ON) {
823− DRM_DEBUG_KMS("id;%u, sw_event:%d, rc in ON state\n",
794+ DRM_DEBUG_ATOMIC("id;%u, sw_event:%d, rc in ON state\n",
824795 DRMID(drm_enc), sw_event);
825796 mutex_unlock(&dpu_enc->rc_lock);
826797 return 0;
827798 } else if (dpu_enc->rc_state != DPU_ENC_RC_STATE_OFF &&
828799 dpu_enc->rc_state != DPU_ENC_RC_STATE_IDLE) {
829− DRM_DEBUG_KMS("id;%u, sw_event:%d, rc in state %d\n",
800+ DRM_DEBUG_ATOMIC("id;%u, sw_event:%d, rc in state %d\n",
830801 DRMID(drm_enc), sw_event,
831802 dpu_enc->rc_state);
832803 mutex_unlock(&dpu_enc->rc_lock);
@@ -1336,6 +1307,11 @@ static void dpu_encoder_underrun_callback(struct drm_encoder *drm_enc, · 503 unmodified lines
13361307
13371308 DPU_ATRACE_BEGIN("encoder_underrun_callback");
13381309 atomic_inc(&phy_enc->underrun_cnt);
1310+
1311+ /* trigger dump only on the first underrun */
1312+ if (atomic_read(&phy_enc->underrun_cnt) == 1)
1313+ msm_disp_snapshot_state(drm_enc->dev);
1314+
13391315 trace_dpu_enc_underrun_cb(DRMID(drm_enc),
13401316 atomic_read(&phy_enc->underrun_cnt));
13411317 DPU_ATRACE_END("encoder_underrun_callback");
@@ -1453,11 +1429,6 @@ static void dpu_encoder_off_work(struct work_struct *work) · 111 unmodified lines
14531429 struct dpu_encoder_virt *dpu_enc = container_of(work,
14541430 struct dpu_encoder_virt, delayed_off_work.work);
14551431
1456− if (!dpu_enc) {
1457− DPU_ERROR("invalid dpu encoder\n");
1458− return;
1459− }
1460−
14611432 dpu_encoder_resource_control(&dpu_enc->base,
14621433 DPU_ENC_RC_EVENT_ENTER_IDLE);
14631434
@@ -1537,7 +1508,7 @@ void dpu_encoder_helper_trigger_start(struct dpu_encoder_phys *phys_enc) · 73 unmodified lines
15371508
15381509 static int dpu_encoder_helper_wait_event_timeout(
15391510 int32_t drm_id,
1540− int32_t hw_id,
1511+ u32 irq_idx,
15411512 struct dpu_encoder_wait_info *info)
15421513 {
15431514 int rc = 0;
@@ -1550,7 +1521,7 @@ static int dpu_encoder_helper_wait_event_timeout( · 6 unmodified lines
15501521 atomic_read(info->atomic_cnt) == 0, jiffies);
15511522 time = ktime_to_ms(ktime_get());
15521523
1553− trace_dpu_enc_wait_event_timeout(drm_id, hw_id, rc, time,
1524+ trace_dpu_enc_wait_event_timeout(drm_id, irq_idx, rc, time,
15541525 expected_time,
15551526 atomic_read(info->atomic_cnt));
15561527 /* If we timed out, counter is valid and time is less, wait again */
@@ -1565,19 +1536,23 @@ static void dpu_encoder_helper_hw_reset(struct dpu_encoder_phys *phys_enc) · 8 unmodified lines
15651536 struct dpu_encoder_virt *dpu_enc;
15661537 struct dpu_hw_ctl *ctl;
15671538 int rc;
1539+ struct drm_encoder *drm_enc;
15681540
15691541 dpu_enc = to_dpu_encoder_virt(phys_enc->parent);
15701542 ctl = phys_enc->hw_ctl;
1543+ drm_enc = phys_enc->parent;
15711544
15721545 if (!ctl->ops.reset)
15731546 return;
15741547
1575− DRM_DEBUG_KMS("id:%u ctl %d reset\n", DRMID(phys_enc->parent),
1548+ DRM_DEBUG_KMS("id:%u ctl %d reset\n", DRMID(drm_enc),
15761549 ctl->idx);
15771550
15781551 rc = ctl->ops.reset(ctl);
1579− if (rc)
1552+ if (rc) {
15801553 DPU_ERROR_ENC(dpu_enc, "ctl %d reset failure\n", ctl->idx);
1554+ msm_disp_snapshot_state(drm_enc->dev);
1555+ }
15811556
15821557 phys_enc->enable_state = DPU_ENC_ENABLED;
15831558 }
@@ -1797,11 +1772,6 @@ static void dpu_encoder_vsync_event_work_handler(struct kthread_work *work) · 213 unmodified lines
17971772 struct dpu_encoder_virt, vsync_event_work);
17981773 ktime_t wakeup_time;
17991774
1800− if (!dpu_enc) {
1801− DPU_ERROR("invalid dpu encoder\n");
1802− return;
1803− }
1804−
18051775 if (dpu_encoder_vsync_time(&dpu_enc->base, &wakeup_time))
18061776 return;
18071777
@@ -2068,8 +2038,6 @@ static int dpu_encoder_setup_display(struct dpu_encoder_virt *dpu_enc, · 260 unmodified lines
20682038 phys_params.parent_ops = &dpu_encoder_parent_ops;
20692039 phys_params.enc_spinlock = &dpu_enc->enc_spinlock;
20702040
2071− DPU_DEBUG("\n");
2072−
20732041 switch (disp_info->intf_type) {
20742042 case DRM_MODE_ENCODER_DSI:
20752043 intf_type = INTF_DSI;
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h+0−4
@@ -165,18 +165,14 @@ enum dpu_intr_idx { · 164 unmodified lines
165165 /**
166166 * dpu_encoder_irq - tracking structure for interrupts
167167 * @name: string name of interrupt
168− * @intr_type: Encoder interrupt type
169168 * @intr_idx: Encoder interrupt enumeration
170− * @hw_idx: HW Block ID
171169 * @irq_idx: IRQ interface lookup index from DPU IRQ framework
172170 * will be -EINVAL if IRQ is not registered
173171 * @irq_cb: interrupt callback
174172 */
175173 struct dpu_encoder_irq {
176174 const char *name;
177− enum dpu_intr_type intr_type;
178175 enum dpu_intr_idx intr_idx;
179− int hw_idx;
180176 int irq_idx;
181177 struct dpu_irq_callback cb;
182178 };
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c+21−37
@@ -1,6 +1,6 @@
11 // SPDX-License-Identifier: GPL-2.0-only
22 /*
3− * Copyright (c) 2015-2018 The Linux Foundation. All rights reserved.
3+ * Copyright (c) 2015-2018, 2020-2021 The Linux Foundation. All rights reserved.
44 */
55
66 #define pr_fmt(fmt) "[drm:%s:%d] " fmt, __func__, __LINE__
@@ -11,6 +11,7 @@ · 4 unmodified lines
1111 #include "dpu_core_irq.h"
1212 #include "dpu_formats.h"
1313 #include "dpu_trace.h"
14+#include "disp/msm_disp_snapshot.h"
1415
1516 #define DPU_DEBUG_CMDENC(e, fmt, ...) DPU_DEBUG("enc%d intf%d " fmt, \
1617 (e) && (e)->base.parent ? \
@@ -143,28 +144,6 @@ static void dpu_encoder_phys_cmd_underrun_irq(void *arg, int irq_idx) · 126 unmodified lines
143144 phys_enc);
144145 }
145146
146−static void _dpu_encoder_phys_cmd_setup_irq_hw_idx(
147− struct dpu_encoder_phys *phys_enc)
148−{
149− struct dpu_encoder_irq *irq;
150−
151− irq = &phys_enc->irq[INTR_IDX_CTL_START];
152− irq->hw_idx = phys_enc->hw_ctl->idx;
153− irq->irq_idx = -EINVAL;
154−
155− irq = &phys_enc->irq[INTR_IDX_PINGPONG];
156− irq->hw_idx = phys_enc->hw_pp->idx;
157− irq->irq_idx = -EINVAL;
158−
159− irq = &phys_enc->irq[INTR_IDX_RDPTR];
160− irq->hw_idx = phys_enc->hw_pp->idx;
161− irq->irq_idx = -EINVAL;
162−
163− irq = &phys_enc->irq[INTR_IDX_UNDERRUN];
164− irq->hw_idx = phys_enc->intf_idx;
165− irq->irq_idx = -EINVAL;
166−}
167−
168147 static void dpu_encoder_phys_cmd_mode_set(
169148 struct dpu_encoder_phys *phys_enc,
170149 struct drm_display_mode *mode,
@@ -172,6 +151,7 @@ static void dpu_encoder_phys_cmd_mode_set( · 1 unmodified line
172151 {
173152 struct dpu_encoder_phys_cmd *cmd_enc =
174153 to_dpu_encoder_phys_cmd(phys_enc);
154+ struct dpu_encoder_irq *irq;
175155
176156 if (!mode || !adj_mode) {
177157 DPU_ERROR("invalid args\n");
@@ -181,7 +161,17 @@ static void dpu_encoder_phys_cmd_mode_set( · 3 unmodified lines
181161 DPU_DEBUG_CMDENC(cmd_enc, "caching mode:\n");
182162 drm_mode_debug_printmodeline(adj_mode);
183163
184− _dpu_encoder_phys_cmd_setup_irq_hw_idx(phys_enc);
164+ irq = &phys_enc->irq[INTR_IDX_CTL_START];
165+ irq->irq_idx = phys_enc->hw_ctl->caps->intr_start;
166+
167+ irq = &phys_enc->irq[INTR_IDX_PINGPONG];
168+ irq->irq_idx = phys_enc->hw_pp->caps->intr_done;
169+
170+ irq = &phys_enc->irq[INTR_IDX_RDPTR];
171+ irq->irq_idx = phys_enc->hw_pp->caps->intr_rdptr;
172+
173+ irq = &phys_enc->irq[INTR_IDX_UNDERRUN];
174+ irq->irq_idx = phys_enc->hw_intf->cap->intr_underrun;
185175 }
186176
187177 static int _dpu_encoder_phys_cmd_handle_ppdone_timeout(
@@ -191,10 +181,13 @@ static int _dpu_encoder_phys_cmd_handle_ppdone_timeout( · 3 unmodified lines
191181 to_dpu_encoder_phys_cmd(phys_enc);
192182 u32 frame_event = DPU_ENCODER_FRAME_EVENT_ERROR;
193183 bool do_log = false;
184+ struct drm_encoder *drm_enc;
194185
195186 if (!phys_enc->hw_pp)
196187 return -EINVAL;
197188
189+ drm_enc = phys_enc->parent;
190+
198191 cmd_enc->pp_timeout_report_cnt++;
199192 if (cmd_enc->pp_timeout_report_cnt == PP_TIMEOUT_MAX_TRIALS) {
200193 frame_event |= DPU_ENCODER_FRAME_EVENT_PANEL_DEAD;
@@ -203,7 +196,7 @@ static int _dpu_encoder_phys_cmd_handle_ppdone_timeout( · 2 unmodified lines
203196 do_log = true;
204197 }
205198
206− trace_dpu_enc_phys_cmd_pdone_timeout(DRMID(phys_enc->parent),
199+ trace_dpu_enc_phys_cmd_pdone_timeout(DRMID(drm_enc),
207200 phys_enc->hw_pp->idx - PINGPONG_0,
208201 cmd_enc->pp_timeout_report_cnt,
209202 atomic_read(&phys_enc->pending_kickoff_cnt),
@@ -212,12 +205,12 @@ static int _dpu_encoder_phys_cmd_handle_ppdone_timeout( · 2 unmodified lines
212205 /* to avoid flooding, only log first time, and "dead" time */
213206 if (do_log) {
214207 DRM_ERROR("id:%d pp:%d kickoff timeout %d cnt %d koff_cnt %d\n",
215− DRMID(phys_enc->parent),
208+ DRMID(drm_enc),
216209 phys_enc->hw_pp->idx - PINGPONG_0,
217210 phys_enc->hw_ctl->idx - CTL_0,
218211 cmd_enc->pp_timeout_report_cnt,
219212 atomic_read(&phys_enc->pending_kickoff_cnt));
220−
213+ msm_disp_snapshot_state(drm_enc->dev);
221214 dpu_encoder_helper_unregister_irq(phys_enc, INTR_IDX_RDPTR);
222215 }
223216
@@ -228,7 +221,7 @@ static int _dpu_encoder_phys_cmd_handle_ppdone_timeout( · 4 unmodified lines
228221
229222 if (phys_enc->parent_ops->handle_frame_done)
230223 phys_enc->parent_ops->handle_frame_done(
231− phys_enc->parent, phys_enc, frame_event);
224+ drm_enc, phys_enc, frame_event);
232225
233226 return -ETIMEDOUT;
234227 }
@@ -685,10 +678,6 @@ static int dpu_encoder_phys_cmd_wait_for_tx_complete( · 450 unmodified lines
685678 static int dpu_encoder_phys_cmd_wait_for_commit_done(
686679 struct dpu_encoder_phys *phys_enc)
687680 {
688− struct dpu_encoder_phys_cmd *cmd_enc;
689−
690− cmd_enc = to_dpu_encoder_phys_cmd(phys_enc);
691−
692681 /* only required for master controller */
693682 if (!dpu_encoder_phys_cmd_is_master(phys_enc))
694683 return 0;
@@ -795,31 +784,26 @@ struct dpu_encoder_phys *dpu_encoder_phys_cmd_init( · 100 unmodified lines
795784 irq = &phys_enc->irq[i];
796785 INIT_LIST_HEAD(&irq->cb.list);
797786 irq->irq_idx = -EINVAL;
798− irq->hw_idx = -EINVAL;
799787 irq->cb.arg = phys_enc;
800788 }
801789
802790 irq = &phys_enc->irq[INTR_IDX_CTL_START];
803791 irq->name = "ctl_start";
804− irq->intr_type = DPU_IRQ_TYPE_CTL_START;
805792 irq->intr_idx = INTR_IDX_CTL_START;
806793 irq->cb.func = dpu_encoder_phys_cmd_ctl_start_irq;
807794
808795 irq = &phys_enc->irq[INTR_IDX_PINGPONG];
809796 irq->name = "pp_done";
810− irq->intr_type = DPU_IRQ_TYPE_PING_PONG_COMP;
811797 irq->intr_idx = INTR_IDX_PINGPONG;
812798 irq->cb.func = dpu_encoder_phys_cmd_pp_tx_done_irq;
813799
814800 irq = &phys_enc->irq[INTR_IDX_RDPTR];
815801 irq->name = "pp_rd_ptr";
816− irq->intr_type = DPU_IRQ_TYPE_PING_PONG_RD_PTR;
817802 irq->intr_idx = INTR_IDX_RDPTR;
818803 irq->cb.func = dpu_encoder_phys_cmd_pp_rd_ptr_irq;
819804
820805 irq = &phys_enc->irq[INTR_IDX_UNDERRUN];
821806 irq->name = "underrun";
822− irq->intr_type = DPU_IRQ_TYPE_INTF_UNDER_RUN;
823807 irq->intr_idx = INTR_IDX_UNDERRUN;
824808 irq->cb.func = dpu_encoder_phys_cmd_underrun_irq;
825809
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c+20−34
@@ -1,5 +1,5 @@
11 // SPDX-License-Identifier: GPL-2.0-only
2−/* Copyright (c) 2015-2018, The Linux Foundation. All rights reserved.
2+/* Copyright (c) 2015-2018, 2020-2021 The Linux Foundation. All rights reserved.
33 */
44
55 #define pr_fmt(fmt) "[drm:%s:%d] " fmt, __func__, __LINE__
@@ -9,6 +9,7 @@ · 3 unmodified lines
99 #include "dpu_core_irq.h"
1010 #include "dpu_formats.h"
1111 #include "dpu_trace.h"
12+#include "disp/msm_disp_snapshot.h"
1213
1314 #define DPU_DEBUG_VIDENC(e, fmt, ...) DPU_DEBUG("enc%d intf%d " fmt, \
1415 (e) && (e)->parent ? \
@@ -284,7 +285,7 @@ static void dpu_encoder_phys_vid_setup_timing_engine( · 269 unmodified lines
284285 intf_cfg.stream_sel = 0; /* Don't care value for video mode */
285286 intf_cfg.mode_3d = dpu_encoder_helper_get_3d_blend_mode(phys_enc);
286287 if (phys_enc->hw_pp->merge_3d)
287− intf_cfg.merge_3d = phys_enc->hw_pp->merge_3d->id;
288+ intf_cfg.merge_3d = phys_enc->hw_pp->merge_3d->idx;
288289
289290 spin_lock_irqsave(phys_enc->enc_spinlock, lock_flags);
290291 phys_enc->hw_intf->ops.setup_timing_gen(phys_enc->hw_intf,
@@ -298,11 +299,8 @@ static void dpu_encoder_phys_vid_setup_timing_engine( · 7 unmodified lines
298299 true,
299300 phys_enc->hw_pp->idx);
300301
301− if (phys_enc->hw_pp->merge_3d) {
302− struct dpu_hw_merge_3d *merge_3d = to_dpu_hw_merge_3d(phys_enc->hw_pp->merge_3d);
303−
304− merge_3d->ops.setup_3d_mode(merge_3d, intf_cfg.mode_3d);
305− }
302+ if (phys_enc->hw_pp->merge_3d)
303+ phys_enc->hw_pp->merge_3d->ops.setup_3d_mode(phys_enc->hw_pp->merge_3d, intf_cfg.mode_3d);
306304
307305 spin_unlock_irqrestore(phys_enc->enc_spinlock, lock_flags);
308306
@@ -363,38 +361,24 @@ static bool dpu_encoder_phys_vid_needs_single_flush( · 54 unmodified lines
363361 return phys_enc->split_role != ENC_ROLE_SOLO;
364362 }
365363
366−static void _dpu_encoder_phys_vid_setup_irq_hw_idx(
367− struct dpu_encoder_phys *phys_enc)
368−{
369− struct dpu_encoder_irq *irq;
370−
371− /*
372− * Initialize irq->hw_idx only when irq is not registered.
373− * Prevent invalidating irq->irq_idx as modeset may be
374− * called many times during dfps.
375− */
376−
377− irq = &phys_enc->irq[INTR_IDX_VSYNC];
378− if (irq->irq_idx < 0)
379− irq->hw_idx = phys_enc->intf_idx;
380−
381− irq = &phys_enc->irq[INTR_IDX_UNDERRUN];
382− if (irq->irq_idx < 0)
383− irq->hw_idx = phys_enc->intf_idx;
384−}
385−
386364 static void dpu_encoder_phys_vid_mode_set(
387365 struct dpu_encoder_phys *phys_enc,
388366 struct drm_display_mode *mode,
389367 struct drm_display_mode *adj_mode)
390368 {
369+ struct dpu_encoder_irq *irq;
370+
391371 if (adj_mode) {
392372 phys_enc->cached_mode = *adj_mode;
393373 drm_mode_debug_printmodeline(adj_mode);
394374 DPU_DEBUG_VIDENC(phys_enc, "caching mode:\n");
395375 }
396376
397− _dpu_encoder_phys_vid_setup_irq_hw_idx(phys_enc);
377+ irq = &phys_enc->irq[INTR_IDX_VSYNC];
378+ irq->irq_idx = phys_enc->hw_intf->cap->intr_vsync;
379+
380+ irq = &phys_enc->irq[INTR_IDX_UNDERRUN];
381+ irq->irq_idx = phys_enc->hw_intf->cap->intr_underrun;
398382 }
399383
400384 static int dpu_encoder_phys_vid_control_vblank_irq(
@@ -416,7 +400,7 @@ static int dpu_encoder_phys_vid_control_vblank_irq( · 15 unmodified lines
416400 goto end;
417401 }
418402
419− DRM_DEBUG_KMS("id:%u enable=%d/%d\n", DRMID(phys_enc->parent), enable,
403+ DRM_DEBUG_VBL("id:%u enable=%d/%d\n", DRMID(phys_enc->parent), enable,
420404 atomic_read(&phys_enc->vblank_refcount));
421405
422406 if (enable && atomic_inc_return(&phys_enc->vblank_refcount) == 1)
@@ -461,13 +445,14 @@ static void dpu_encoder_phys_vid_enable(struct dpu_encoder_phys *phys_enc) · 38 unmodified lines
461445
462446 ctl->ops.update_pending_flush_intf(ctl, phys_enc->hw_intf->idx);
463447 if (ctl->ops.update_pending_flush_merge_3d && phys_enc->hw_pp->merge_3d)
464− ctl->ops.update_pending_flush_merge_3d(ctl, phys_enc->hw_pp->merge_3d->id);
448+ ctl->ops.update_pending_flush_merge_3d(ctl, phys_enc->hw_pp->merge_3d->idx);
465449
466450 skip_flush:
467451 DPU_DEBUG_VIDENC(phys_enc,
468452 "update pending flush ctl %d intf %d\n",
469453 ctl->idx - CTL_0, phys_enc->hw_intf->idx);
470454
455+ atomic_set(&phys_enc->underrun_cnt, 0);
471456
472457 /* ctl_flush & timing engine enable will be triggered by framework */
473458 if (phys_enc->enable_state == DPU_ENC_DISABLED)
@@ -537,6 +522,9 @@ static void dpu_encoder_phys_vid_prepare_for_kickoff( · 63 unmodified lines
537522 {
538523 struct dpu_hw_ctl *ctl;
539524 int rc;
525+ struct drm_encoder *drm_enc;
526+
527+ drm_enc = phys_enc->parent;
540528
541529 ctl = phys_enc->hw_ctl;
542530 if (!ctl->ops.wait_reset_status)
@@ -550,6 +538,7 @@ static void dpu_encoder_phys_vid_prepare_for_kickoff( · 7 unmodified lines
550538 if (rc) {
551539 DPU_ERROR_VIDENC(phys_enc, "ctl %d reset failure: %d\n",
552540 ctl->idx, rc);
541+ msm_disp_snapshot_state(drm_enc->dev);
553542 dpu_encoder_helper_unregister_irq(phys_enc, INTR_IDX_VSYNC);
554543 }
555544 }
@@ -636,7 +625,7 @@ static void dpu_encoder_phys_vid_irq_control(struct dpu_encoder_phys *phys_enc, · 80 unmodified lines
636625
637626 if (enable) {
638627 ret = dpu_encoder_phys_vid_control_vblank_irq(phys_enc, true);
639− if (ret)
628+ if (WARN_ON(ret))
640629 return;
641630
642631 dpu_encoder_helper_register_irq(phys_enc, INTR_IDX_UNDERRUN);
@@ -738,19 +727,16 @@ struct dpu_encoder_phys *dpu_encoder_phys_vid_init( · 95 unmodified lines
738727 irq = &phys_enc->irq[i];
739728 INIT_LIST_HEAD(&irq->cb.list);
740729 irq->irq_idx = -EINVAL;
741− irq->hw_idx = -EINVAL;
742730 irq->cb.arg = phys_enc;
743731 }
744732
745733 irq = &phys_enc->irq[INTR_IDX_VSYNC];
746734 irq->name = "vsync_irq";
747− irq->intr_type = DPU_IRQ_TYPE_INTF_VSYNC;
748735 irq->intr_idx = INTR_IDX_VSYNC;
749736 irq->cb.func = dpu_encoder_phys_vid_vblank_irq;
750737
751738 irq = &phys_enc->irq[INTR_IDX_UNDERRUN];
752739 irq->name = "underrun";
753− irq->intr_type = DPU_IRQ_TYPE_INTF_UNDER_RUN;
754740 irq->intr_idx = INTR_IDX_UNDERRUN;
755741 irq->cb.func = dpu_encoder_phys_vid_underrun_irq;
756742
drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c+3−3
@@ -992,7 +992,7 @@ const struct dpu_format *dpu_get_dpu_format_ext( · 991 unmodified lines
992992 * Currently only support exactly zero or one modifier.
993993 * All planes use the same modifier.
994994 */
995− DPU_DEBUG("plane format modifier 0x%llX\n", modifier);
995+ DRM_DEBUG_ATOMIC("plane format modifier 0x%llX\n", modifier);
996996
997997 switch (modifier) {
998998 case 0:
@@ -1002,7 +1002,7 @@ const struct dpu_format *dpu_get_dpu_format_ext( · 3 unmodified lines
10021002 case DRM_FORMAT_MOD_QCOM_COMPRESSED:
10031003 map = dpu_format_map_ubwc;
10041004 map_size = ARRAY_SIZE(dpu_format_map_ubwc);
1005− DPU_DEBUG("found fmt: %4.4s DRM_FORMAT_MOD_QCOM_COMPRESSED\n",
1005+ DRM_DEBUG_ATOMIC("found fmt: %4.4s DRM_FORMAT_MOD_QCOM_COMPRESSED\n",
10061006 (char *)&format);
10071007 break;
10081008 default:
@@ -1021,7 +1021,7 @@ const struct dpu_format *dpu_get_dpu_format_ext( · 12 unmodified lines
10211021 DPU_ERROR("unsupported fmt: %4.4s modifier 0x%llX\n",
10221022 (char *)&format, modifier);
10231023 else
1024− DPU_DEBUG("fmt %4.4s mod 0x%llX ubwc %d yuv %d\n",
1024+ DRM_DEBUG_ATOMIC("fmt %4.4s mod 0x%llX ubwc %d yuv %d\n",
10251025 (char *)&format, modifier,
10261026 DPU_FORMAT_IS_UBWC(fmt),
10271027 DPU_FORMAT_IS_YUV(fmt));
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_blk.c+0−139
@@ -1,139 +0,0 @@
1−// SPDX-License-Identifier: GPL-2.0-only
2−/* Copyright (c) 2017-2018, The Linux Foundation. All rights reserved.
3− */
4−
5−#define pr_fmt(fmt) "[drm:%s:%d] " fmt, __func__, __LINE__
6−
7−#include <linux/mutex.h>
8−#include <linux/errno.h>
9−#include <linux/slab.h>
10−
11−#include "dpu_hw_mdss.h"
12−#include "dpu_hw_blk.h"
13−
14−/* Serialization lock for dpu_hw_blk_list */
15−static DEFINE_MUTEX(dpu_hw_blk_lock);
16−
17−/* List of all hw block objects */
18−static LIST_HEAD(dpu_hw_blk_list);
19−
20−/**
21− * dpu_hw_blk_init - initialize hw block object
22− * @hw_blk: pointer to hw block object
23− * @type: hw block type - enum dpu_hw_blk_type
24− * @id: instance id of the hw block
25− * @ops: Pointer to block operations
26− */
27−void dpu_hw_blk_init(struct dpu_hw_blk *hw_blk, u32 type, int id,
28− struct dpu_hw_blk_ops *ops)
29−{
30− INIT_LIST_HEAD(&hw_blk->list);
31− hw_blk->type = type;
32− hw_blk->id = id;
33− atomic_set(&hw_blk->refcount, 0);
34−
35− if (ops)
36− hw_blk->ops = *ops;
37−
38− mutex_lock(&dpu_hw_blk_lock);
39− list_add(&hw_blk->list, &dpu_hw_blk_list);
40− mutex_unlock(&dpu_hw_blk_lock);
41−}
42−
43−/**
44− * dpu_hw_blk_destroy - destroy hw block object.
45− * @hw_blk: pointer to hw block object
46− * return: none
47− */
48−void dpu_hw_blk_destroy(struct dpu_hw_blk *hw_blk)
49−{
50− if (!hw_blk) {
51− pr_err("invalid parameters\n");
52− return;
53− }
54−
55− if (atomic_read(&hw_blk->refcount))
56− pr_err("hw_blk:%d.%d invalid refcount\n", hw_blk->type,
57− hw_blk->id);
58−
59− mutex_lock(&dpu_hw_blk_lock);
60− list_del(&hw_blk->list);
61− mutex_unlock(&dpu_hw_blk_lock);
62−}
63−
64−/**
65− * dpu_hw_blk_get - get hw_blk from free pool
66− * @hw_blk: if specified, increment reference count only
67− * @type: if hw_blk is not specified, allocate the next available of this type
68− * @id: if specified (>= 0), allocate the given instance of the above type
69− * return: pointer to hw block object
70− */
71−struct dpu_hw_blk *dpu_hw_blk_get(struct dpu_hw_blk *hw_blk, u32 type, int id)
72−{
73− struct dpu_hw_blk *curr;
74− int rc, refcount;
75−
76− if (!hw_blk) {
77− mutex_lock(&dpu_hw_blk_lock);
78− list_for_each_entry(curr, &dpu_hw_blk_list, list) {
79− if ((curr->type != type) ||
80− (id >= 0 && curr->id != id) ||
81− (id < 0 &&
82− atomic_read(&curr->refcount)))
83− continue;
84−
85− hw_blk = curr;
86− break;
87− }
88− mutex_unlock(&dpu_hw_blk_lock);
89− }
90−
91− if (!hw_blk) {
92− pr_debug("no hw_blk:%d\n", type);
93− return NULL;
94− }
95−
96− refcount = atomic_inc_return(&hw_blk->refcount);
97−
98− if (refcount == 1 && hw_blk->ops.start) {
99− rc = hw_blk->ops.start(hw_blk);
100− if (rc) {
101− pr_err("failed to start hw_blk:%d rc:%d\n", type, rc);
102− goto error_start;
103− }
104− }
105−
106− pr_debug("hw_blk:%d.%d refcount:%d\n", hw_blk->type,
107− hw_blk->id, refcount);
108− return hw_blk;
109−
110−error_start:
111− dpu_hw_blk_put(hw_blk);
112− return ERR_PTR(rc);
113−}
114−
115−/**
116− * dpu_hw_blk_put - put hw_blk to free pool if decremented refcount is zero
117− * @hw_blk: hw block to be freed
118− */
119−void dpu_hw_blk_put(struct dpu_hw_blk *hw_blk)
120−{
121− if (!hw_blk) {
122− pr_err("invalid parameters\n");
123− return;
124− }
125−
126− pr_debug("hw_blk:%d.%d refcount:%d\n", hw_blk->type, hw_blk->id,
127− atomic_read(&hw_blk->refcount));
128−
129− if (!atomic_read(&hw_blk->refcount)) {
130− pr_err("hw_blk:%d.%d invalid put\n", hw_blk->type, hw_blk->id);
131− return;
132− }
133−
134− if (atomic_dec_return(&hw_blk->refcount))
135− return;
136−
137− if (hw_blk->ops.stop)
138− hw_blk->ops.stop(hw_blk);
139−}
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_blk.h+1−21
@@ -7,19 +7,9 @@ · 6 unmodified lines
77
88 #include <linux/types.h>
99 #include <linux/list.h>
10−#include <linux/atomic.h>
1110
1211 struct dpu_hw_blk;
1312
14−/**
15− * struct dpu_hw_blk_ops - common hardware block operations
16− * @start: start operation on first get
17− * @stop: stop operation on last put
18− */
19−struct dpu_hw_blk_ops {
20− int (*start)(struct dpu_hw_blk *);
21− void (*stop)(struct dpu_hw_blk *);
22−};
2313
2414 /**
2515 * struct dpu_hw_blk - definition of hardware block object
@@ -29,17 +19,7 @@ struct dpu_hw_blk_ops { · 3 unmodified lines
2919 * @refcount: reference/usage count
3020 */
3121 struct dpu_hw_blk {
32− struct list_head list;
33− u32 type;
34− int id;
35− atomic_t refcount;
36− struct dpu_hw_blk_ops ops;
22+ /* opaque */
3723 };
3824
39−void dpu_hw_blk_init(struct dpu_hw_blk *hw_blk, u32 type, int id,
40− struct dpu_hw_blk_ops *ops);
41−void dpu_hw_blk_destroy(struct dpu_hw_blk *hw_blk);
42−
43−struct dpu_hw_blk *dpu_hw_blk_get(struct dpu_hw_blk *hw_blk, u32 type, int id);
44−void dpu_hw_blk_put(struct dpu_hw_blk *hw_blk);
4525 #endif /*_DPU_HW_BLK_H */
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c+136−66
@@ -7,6 +7,7 @@ · 6 unmodified lines
77 #include <linux/of_address.h>
88 #include <linux/platform_device.h>
99 #include "dpu_hw_mdss.h"
10+#include "dpu_hw_interrupts.h"
1011 #include "dpu_hw_catalog.h"
1112 #include "dpu_kms.h"
1213
@@ -56,12 +57,39 @@ · 43 unmodified lines
5657
5758 #define INTF_SC7280_MASK INTF_SC7180_MASK | BIT(DPU_DATA_HCTL_EN)
5859
59−#define INTR_SC7180_MASK \
60− (BIT(DPU_IRQ_TYPE_PING_PONG_RD_PTR) |\
61− BIT(DPU_IRQ_TYPE_PING_PONG_WR_PTR) |\
62− BIT(DPU_IRQ_TYPE_PING_PONG_AUTO_REF) |\
63− BIT(DPU_IRQ_TYPE_PING_PONG_TEAR_CHECK) |\
64− BIT(DPU_IRQ_TYPE_PING_PONG_TE_CHECK))
60+#define IRQ_SDM845_MASK (BIT(MDP_SSPP_TOP0_INTR) | \
61+ BIT(MDP_SSPP_TOP0_INTR2) | \
62+ BIT(MDP_SSPP_TOP0_HIST_INTR) | \
63+ BIT(MDP_INTF0_INTR) | \
64+ BIT(MDP_INTF1_INTR) | \
65+ BIT(MDP_INTF2_INTR) | \
66+ BIT(MDP_INTF3_INTR) | \
67+ BIT(MDP_INTF4_INTR) | \
68+ BIT(MDP_AD4_0_INTR) | \
69+ BIT(MDP_AD4_1_INTR))
70+
71+#define IRQ_SC7180_MASK (BIT(MDP_SSPP_TOP0_INTR) | \
72+ BIT(MDP_SSPP_TOP0_INTR2) | \
73+ BIT(MDP_SSPP_TOP0_HIST_INTR) | \
74+ BIT(MDP_INTF0_INTR) | \
75+ BIT(MDP_INTF1_INTR))
76+
77+#define IRQ_SC7280_MASK (BIT(MDP_SSPP_TOP0_INTR) | \
78+ BIT(MDP_SSPP_TOP0_INTR2) | \
79+ BIT(MDP_SSPP_TOP0_HIST_INTR) | \
80+ BIT(MDP_INTF0_7xxx_INTR) | \
81+ BIT(MDP_INTF1_7xxx_INTR) | \
82+ BIT(MDP_INTF5_7xxx_INTR))
83+
84+#define IRQ_SM8250_MASK (BIT(MDP_SSPP_TOP0_INTR) | \
85+ BIT(MDP_SSPP_TOP0_INTR2) | \
86+ BIT(MDP_SSPP_TOP0_HIST_INTR) | \
87+ BIT(MDP_INTF0_INTR) | \
88+ BIT(MDP_INTF1_INTR) | \
89+ BIT(MDP_INTF2_INTR) | \
90+ BIT(MDP_INTF3_INTR) | \
91+ BIT(MDP_INTF4_INTR))
92+
6593
6694 #define DEFAULT_PIXEL_RAM_SIZE (50 * 1024)
6795 #define DEFAULT_DPU_LINE_WIDTH 2048
@@ -315,27 +343,32 @@ static const struct dpu_ctl_cfg sdm845_ctl[] = { · 247 unmodified lines
315343 {
316344 .name = "ctl_0", .id = CTL_0,
317345 .base = 0x1000, .len = 0xE4,
318− .features = BIT(DPU_CTL_SPLIT_DISPLAY)
346+ .features = BIT(DPU_CTL_SPLIT_DISPLAY),
347+ .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
319348 },
320349 {
321350 .name = "ctl_1", .id = CTL_1,
322351 .base = 0x1200, .len = 0xE4,
323− .features = BIT(DPU_CTL_SPLIT_DISPLAY)
352+ .features = BIT(DPU_CTL_SPLIT_DISPLAY),
353+ .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
324354 },
325355 {
326356 .name = "ctl_2", .id = CTL_2,
327357 .base = 0x1400, .len = 0xE4,
328− .features = 0
358+ .features = 0,
359+ .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),
329360 },
330361 {
331362 .name = "ctl_3", .id = CTL_3,
332363 .base = 0x1600, .len = 0xE4,
333− .features = 0
364+ .features = 0,
365+ .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12),
334366 },
335367 {
336368 .name = "ctl_4", .id = CTL_4,
337369 .base = 0x1800, .len = 0xE4,
338− .features = 0
370+ .features = 0,
371+ .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13),
339372 },
340373 };
341374
@@ -343,17 +376,20 @@ static const struct dpu_ctl_cfg sc7180_ctl[] = { · 1 unmodified line
343376 {
344377 .name = "ctl_0", .id = CTL_0,
345378 .base = 0x1000, .len = 0xE4,
346− .features = BIT(DPU_CTL_ACTIVE_CFG)
379+ .features = BIT(DPU_CTL_ACTIVE_CFG),
380+ .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
347381 },
348382 {
349383 .name = "ctl_1", .id = CTL_1,
350384 .base = 0x1200, .len = 0xE4,
351− .features = BIT(DPU_CTL_ACTIVE_CFG)
385+ .features = BIT(DPU_CTL_ACTIVE_CFG),
386+ .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
352387 },
353388 {
354389 .name = "ctl_2", .id = CTL_2,
355390 .base = 0x1400, .len = 0xE4,
356− .features = BIT(DPU_CTL_ACTIVE_CFG)
391+ .features = BIT(DPU_CTL_ACTIVE_CFG),
392+ .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),
357393 },
358394 };
359395
@@ -361,32 +397,38 @@ static const struct dpu_ctl_cfg sm8150_ctl[] = { · 1 unmodified line
361397 {
362398 .name = "ctl_0", .id = CTL_0,
363399 .base = 0x1000, .len = 0x1e0,
364− .features = BIT(DPU_CTL_ACTIVE_CFG) | BIT(DPU_CTL_SPLIT_DISPLAY)
400+ .features = BIT(DPU_CTL_ACTIVE_CFG) | BIT(DPU_CTL_SPLIT_DISPLAY),
401+ .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
365402 },
366403 {
367404 .name = "ctl_1", .id = CTL_1,
368405 .base = 0x1200, .len = 0x1e0,
369− .features = BIT(DPU_CTL_ACTIVE_CFG) | BIT(DPU_CTL_SPLIT_DISPLAY)
406+ .features = BIT(DPU_CTL_ACTIVE_CFG) | BIT(DPU_CTL_SPLIT_DISPLAY),
407+ .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
370408 },
371409 {
372410 .name = "ctl_2", .id = CTL_2,
373411 .base = 0x1400, .len = 0x1e0,
374− .features = BIT(DPU_CTL_ACTIVE_CFG)
412+ .features = BIT(DPU_CTL_ACTIVE_CFG),
413+ .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),
375414 },
376415 {
377416 .name = "ctl_3", .id = CTL_3,
378417 .base = 0x1600, .len = 0x1e0,
379− .features = BIT(DPU_CTL_ACTIVE_CFG)
418+ .features = BIT(DPU_CTL_ACTIVE_CFG),
419+ .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12),
380420 },
381421 {
382422 .name = "ctl_4", .id = CTL_4,
383423 .base = 0x1800, .len = 0x1e0,
384− .features = BIT(DPU_CTL_ACTIVE_CFG)
424+ .features = BIT(DPU_CTL_ACTIVE_CFG),
425+ .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13),
385426 },
386427 {
387428 .name = "ctl_5", .id = CTL_5,
388429 .base = 0x1a00, .len = 0x1e0,
389− .features = BIT(DPU_CTL_ACTIVE_CFG)
430+ .features = BIT(DPU_CTL_ACTIVE_CFG),
431+ .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 23),
390432 },
391433 };
392434
@@ -394,22 +436,26 @@ static const struct dpu_ctl_cfg sc7280_ctl[] = { · 1 unmodified line
394436 {
395437 .name = "ctl_0", .id = CTL_0,
396438 .base = 0x15000, .len = 0x1E8,
397− .features = CTL_SC7280_MASK
439+ .features = CTL_SC7280_MASK,
440+ .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
398441 },
399442 {
400443 .name = "ctl_1", .id = CTL_1,
401444 .base = 0x16000, .len = 0x1E8,
402− .features = CTL_SC7280_MASK
445+ .features = CTL_SC7280_MASK,
446+ .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
403447 },
404448 {
405449 .name = "ctl_2", .id = CTL_2,
406450 .base = 0x17000, .len = 0x1E8,
407− .features = CTL_SC7280_MASK
451+ .features = CTL_SC7280_MASK,
452+ .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),
408453 },
409454 {
410455 .name = "ctl_3", .id = CTL_3,
411456 .base = 0x18000, .len = 0x1E8,
412− .features = CTL_SC7280_MASK
457+ .features = CTL_SC7280_MASK,
458+ .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12),
413459 },
414460 };
415461
@@ -690,42 +736,66 @@ static const struct dpu_pingpong_sub_blks sc7280_pp_sblk = { · 274 unmodified lines
690736 .len = 0x20, .version = 0x20000},
691737 };
692738
693−#define PP_BLK_TE(_name, _id, _base, _merge_3d, _sblk) \
739+#define PP_BLK_TE(_name, _id, _base, _merge_3d, _sblk, _done, _rdptr) \
694740 {\
695741 .name = _name, .id = _id, \
696742 .base = _base, .len = 0xd4, \
697743 .features = PINGPONG_SDM845_SPLIT_MASK, \
698744 .merge_3d = _merge_3d, \
699− .sblk = &_sblk \
745+ .sblk = &_sblk, \
746+ .intr_done = _done, \
747+ .intr_rdptr = _rdptr, \
700748 }
701−#define PP_BLK(_name, _id, _base, _merge_3d, _sblk) \
749+#define PP_BLK(_name, _id, _base, _merge_3d, _sblk, _done, _rdptr) \
702750 {\
703751 .name = _name, .id = _id, \
704752 .base = _base, .len = 0xd4, \
705753 .features = PINGPONG_SDM845_MASK, \
706754 .merge_3d = _merge_3d, \
707− .sblk = &_sblk \
755+ .sblk = &_sblk, \
756+ .intr_done = _done, \
757+ .intr_rdptr = _rdptr, \
708758 }
709759
710760 static const struct dpu_pingpong_cfg sdm845_pp[] = {
711− PP_BLK_TE("pingpong_0", PINGPONG_0, 0x70000, 0, sdm845_pp_sblk_te),
712− PP_BLK_TE("pingpong_1", PINGPONG_1, 0x70800, 0, sdm845_pp_sblk_te),
713− PP_BLK("pingpong_2", PINGPONG_2, 0x71000, 0, sdm845_pp_sblk),
714− PP_BLK("pingpong_3", PINGPONG_3, 0x71800, 0, sdm845_pp_sblk),
761+ PP_BLK_TE("pingpong_0", PINGPONG_0, 0x70000, 0, sdm845_pp_sblk_te,
762+ DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8),
763+ DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 12)),
764+ PP_BLK_TE("pingpong_1", PINGPONG_1, 0x70800, 0, sdm845_pp_sblk_te,
765+ DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9),
766+ DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 13)),
767+ PP_BLK("pingpong_2", PINGPONG_2, 0x71000, 0, sdm845_pp_sblk,
768+ DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10),
769+ DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 14)),
770+ PP_BLK("pingpong_3", PINGPONG_3, 0x71800, 0, sdm845_pp_sblk,
771+ DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 11),
772+ DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 15)),
715773 };
716774
717775 static struct dpu_pingpong_cfg sc7180_pp[] = {
718− PP_BLK_TE("pingpong_0", PINGPONG_0, 0x70000, 0, sdm845_pp_sblk_te),
719− PP_BLK_TE("pingpong_1", PINGPONG_1, 0x70800, 0, sdm845_pp_sblk_te),
776+ PP_BLK_TE("pingpong_0", PINGPONG_0, 0x70000, 0, sdm845_pp_sblk_te, -1, -1),
777+ PP_BLK_TE("pingpong_1", PINGPONG_1, 0x70800, 0, sdm845_pp_sblk_te, -1, -1),
720778 };
721779
722780 static const struct dpu_pingpong_cfg sm8150_pp[] = {
723− PP_BLK_TE("pingpong_0", PINGPONG_0, 0x70000, MERGE_3D_0, sdm845_pp_sblk_te),
724− PP_BLK_TE("pingpong_1", PINGPONG_1, 0x70800, MERGE_3D_0, sdm845_pp_sblk_te),
725− PP_BLK("pingpong_2", PINGPONG_2, 0x71000, MERGE_3D_1, sdm845_pp_sblk),
726− PP_BLK("pingpong_3", PINGPONG_3, 0x71800, MERGE_3D_1, sdm845_pp_sblk),
727− PP_BLK("pingpong_4", PINGPONG_4, 0x72000, MERGE_3D_2, sdm845_pp_sblk),
728− PP_BLK("pingpong_5", PINGPONG_5, 0x72800, MERGE_3D_2, sdm845_pp_sblk),
781+ PP_BLK_TE("pingpong_0", PINGPONG_0, 0x70000, MERGE_3D_0, sdm845_pp_sblk_te,
782+ DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8),
783+ DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 12)),
784+ PP_BLK_TE("pingpong_1", PINGPONG_1, 0x70800, MERGE_3D_0, sdm845_pp_sblk_te,
785+ DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9),
786+ DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 13)),
787+ PP_BLK("pingpong_2", PINGPONG_2, 0x71000, MERGE_3D_1, sdm845_pp_sblk,
788+ DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10),
789+ DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 14)),
790+ PP_BLK("pingpong_3", PINGPONG_3, 0x71800, MERGE_3D_1, sdm845_pp_sblk,
791+ DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 11),
792+ DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 15)),
793+ PP_BLK("pingpong_4", PINGPONG_4, 0x72000, MERGE_3D_2, sdm845_pp_sblk,
794+ DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 30),
795+ -1),
796+ PP_BLK("pingpong_5", PINGPONG_5, 0x72800, MERGE_3D_2, sdm845_pp_sblk,
797+ DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 30),
798+ -1),
729799 };
730800
731801 /*************************************************************
@@ -746,47 +816,49 @@ static const struct dpu_merge_3d_cfg sm8150_merge_3d[] = { · 14 unmodified lines
746816 };
747817
748818 static const struct dpu_pingpong_cfg sc7280_pp[] = {
749− PP_BLK("pingpong_0", PINGPONG_0, 0x59000, 0, sc7280_pp_sblk),
750− PP_BLK("pingpong_1", PINGPONG_1, 0x6a000, 0, sc7280_pp_sblk),
751− PP_BLK("pingpong_2", PINGPONG_2, 0x6b000, 0, sc7280_pp_sblk),
752− PP_BLK("pingpong_3", PINGPONG_3, 0x6c000, 0, sc7280_pp_sblk),
819+ PP_BLK("pingpong_0", PINGPONG_0, 0x59000, 0, sc7280_pp_sblk, -1, -1),
820+ PP_BLK("pingpong_1", PINGPONG_1, 0x6a000, 0, sc7280_pp_sblk, -1, -1),
821+ PP_BLK("pingpong_2", PINGPONG_2, 0x6b000, 0, sc7280_pp_sblk, -1, -1),
822+ PP_BLK("pingpong_3", PINGPONG_3, 0x6c000, 0, sc7280_pp_sblk, -1, -1),
753823 };
754824 /*************************************************************
755825 * INTF sub blocks config
756826 *************************************************************/
757−#define INTF_BLK(_name, _id, _base, _type, _ctrl_id, _progfetch, _features) \
827+#define INTF_BLK(_name, _id, _base, _type, _ctrl_id, _progfetch, _features, _reg, _underrun_bit, _vsync_bit) \
758828 {\
759829 .name = _name, .id = _id, \
760830 .base = _base, .len = 0x280, \
761831 .features = _features, \
762832 .type = _type, \
763833 .controller_id = _ctrl_id, \
764− .prog_fetch_lines_worst_case = _progfetch \
834+ .prog_fetch_lines_worst_case = _progfetch, \
835+ .intr_underrun = DPU_IRQ_IDX(_reg, _underrun_bit), \
836+ .intr_vsync = DPU_IRQ_IDX(_reg, _vsync_bit), \
765837 }
766838
767839 static const struct dpu_intf_cfg sdm845_intf[] = {
768− INTF_BLK("intf_0", INTF_0, 0x6A000, INTF_DP, 0, 24, INTF_SDM845_MASK),
769− INTF_BLK("intf_1", INTF_1, 0x6A800, INTF_DSI, 0, 24, INTF_SDM845_MASK),
770− INTF_BLK("intf_2", INTF_2, 0x6B000, INTF_DSI, 1, 24, INTF_SDM845_MASK),
771− INTF_BLK("intf_3", INTF_3, 0x6B800, INTF_DP, 1, 24, INTF_SDM845_MASK),
840+ INTF_BLK("intf_0", INTF_0, 0x6A000, INTF_DP, 0, 24, INTF_SDM845_MASK, MDP_SSPP_TOP0_INTR, 24, 25),
841+ INTF_BLK("intf_1", INTF_1, 0x6A800, INTF_DSI, 0, 24, INTF_SDM845_MASK, MDP_SSPP_TOP0_INTR, 26, 27),
842+ INTF_BLK("intf_2", INTF_2, 0x6B000, INTF_DSI, 1, 24, INTF_SDM845_MASK, MDP_SSPP_TOP0_INTR, 28, 29),
843+ INTF_BLK("intf_3", INTF_3, 0x6B800, INTF_DP, 1, 24, INTF_SDM845_MASK, MDP_SSPP_TOP0_INTR, 30, 31),
772844 };
773845
774846 static const struct dpu_intf_cfg sc7180_intf[] = {
775− INTF_BLK("intf_0", INTF_0, 0x6A000, INTF_DP, 0, 24, INTF_SC7180_MASK),
776− INTF_BLK("intf_1", INTF_1, 0x6A800, INTF_DSI, 0, 24, INTF_SC7180_MASK),
847+ INTF_BLK("intf_0", INTF_0, 0x6A000, INTF_DP, 0, 24, INTF_SC7180_MASK, MDP_SSPP_TOP0_INTR, 24, 25),
848+ INTF_BLK("intf_1", INTF_1, 0x6A800, INTF_DSI, 0, 24, INTF_SC7180_MASK, MDP_SSPP_TOP0_INTR, 26, 27),
777849 };
778850
779851 static const struct dpu_intf_cfg sm8150_intf[] = {
780− INTF_BLK("intf_0", INTF_0, 0x6A000, INTF_DP, 0, 24, INTF_SC7180_MASK),
781− INTF_BLK("intf_1", INTF_1, 0x6A800, INTF_DSI, 0, 24, INTF_SC7180_MASK),
782− INTF_BLK("intf_2", INTF_2, 0x6B000, INTF_DSI, 1, 24, INTF_SC7180_MASK),
783− INTF_BLK("intf_3", INTF_3, 0x6B800, INTF_DP, 1, 24, INTF_SC7180_MASK),
852+ INTF_BLK("intf_0", INTF_0, 0x6A000, INTF_DP, 0, 24, INTF_SC7180_MASK, MDP_SSPP_TOP0_INTR, 24, 25),
853+ INTF_BLK("intf_1", INTF_1, 0x6A800, INTF_DSI, 0, 24, INTF_SC7180_MASK, MDP_SSPP_TOP0_INTR, 26, 27),
854+ INTF_BLK("intf_2", INTF_2, 0x6B000, INTF_DSI, 1, 24, INTF_SC7180_MASK, MDP_SSPP_TOP0_INTR, 28, 29),
855+ INTF_BLK("intf_3", INTF_3, 0x6B800, INTF_DP, 1, 24, INTF_SC7180_MASK, MDP_SSPP_TOP0_INTR, 30, 31),
784856 };
785857
786858 static const struct dpu_intf_cfg sc7280_intf[] = {
787− INTF_BLK("intf_0", INTF_0, 0x34000, INTF_DP, 0, 24, INTF_SC7280_MASK),
788− INTF_BLK("intf_1", INTF_1, 0x35000, INTF_DSI, 0, 24, INTF_SC7280_MASK),
789− INTF_BLK("intf_5", INTF_5, 0x39000, INTF_EDP, 0, 24, INTF_SC7280_MASK),
859+ INTF_BLK("intf_0", INTF_0, 0x34000, INTF_DP, 0, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 24, 25),
860+ INTF_BLK("intf_1", INTF_1, 0x35000, INTF_DSI, 0, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 26, 27),
861+ INTF_BLK("intf_5", INTF_5, 0x39000, INTF_EDP, 0, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 22, 23),
790862 };
791863
792864 /*************************************************************
@@ -1060,7 +1132,7 @@ static void sdm845_cfg_init(struct dpu_mdss_cfg *dpu_cfg) · 267 unmodified lines
10601132 .reg_dma_count = 1,
10611133 .dma_cfg = sdm845_regdma,
10621134 .perf = sdm845_perf_data,
1063− .mdss_irqs = 0x3ff,
1135+ .mdss_irqs = IRQ_SDM845_MASK,
10641136 };
10651137 }
10661138
@@ -1091,8 +1163,7 @@ static void sc7180_cfg_init(struct dpu_mdss_cfg *dpu_cfg) · 24 unmodified lines
10911163 .reg_dma_count = 1,
10921164 .dma_cfg = sdm845_regdma,
10931165 .perf = sc7180_perf_data,
1094− .mdss_irqs = 0x3f,
1095− .obsolete_irq = INTR_SC7180_MASK,
1166+ .mdss_irqs = IRQ_SC7180_MASK,
10961167 };
10971168 }
10981169
@@ -1125,7 +1196,7 @@ static void sm8150_cfg_init(struct dpu_mdss_cfg *dpu_cfg) · 26 unmodified lines
11251196 .reg_dma_count = 1,
11261197 .dma_cfg = sm8150_regdma,
11271198 .perf = sm8150_perf_data,
1128− .mdss_irqs = 0x3ff,
1199+ .mdss_irqs = IRQ_SDM845_MASK,
11291200 };
11301201 }
11311202
@@ -1158,7 +1229,7 @@ static void sm8250_cfg_init(struct dpu_mdss_cfg *dpu_cfg) · 26 unmodified lines
11581229 .reg_dma_count = 1,
11591230 .dma_cfg = sm8250_regdma,
11601231 .perf = sm8250_perf_data,
1161− .mdss_irqs = 0xff,
1232+ .mdss_irqs = IRQ_SM8250_MASK,
11621233 };
11631234 }
11641235
@@ -1181,8 +1252,7 @@ static void sc7280_cfg_init(struct dpu_mdss_cfg *dpu_cfg) · 16 unmodified lines
11811252 .vbif_count = ARRAY_SIZE(sdm845_vbif),
11821253 .vbif = sdm845_vbif,
11831254 .perf = sc7280_perf_data,
1184− .mdss_irqs = 0x1c07,
1185− .obsolete_irq = INTR_SC7180_MASK,
1255+ .mdss_irqs = IRQ_SC7280_MASK,
11861256 };
11871257 }
11881258
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h+12−4
@@ -1,5 +1,5 @@
11 /* SPDX-License-Identifier: GPL-2.0-only */
2−/* Copyright (c) 2015-2018, The Linux Foundation. All rights reserved.
2+/* Copyright (c) 2015-2018, 2020 The Linux Foundation. All rights reserved.
33 */
44
55 #ifndef _DPU_HW_CATALOG_H
@@ -464,13 +464,15 @@ struct dpu_mdp_cfg { · 458 unmodified lines
464464 struct dpu_clk_ctrl_reg clk_ctrls[DPU_CLK_CTRL_MAX];
465465 };
466466
467−/* struct dpu_mdp_cfg : MDP TOP-BLK instance info
467+/* struct dpu_ctl_cfg : MDP CTL instance info
468468 * @id: index identifying this block
469469 * @base: register base offset to mdss
470470 * @features bit mask identifying sub-blocks/features
471+ * @intr_start: interrupt index for CTL_START
471472 */
472473 struct dpu_ctl_cfg {
473474 DPU_HW_BLK_INFO;
475+ s32 intr_start;
474476 };
475477
476478 /**
@@ -526,11 +528,15 @@ struct dpu_dspp_cfg { · 49 unmodified lines
526528 * @id enum identifying this block
527529 * @base register offset of this block
528530 * @features bit mask identifying sub-blocks/features
531+ * @intr_done: index for PINGPONG done interrupt
532+ * @intr_rdptr: index for PINGPONG readpointer done interrupt
529533 * @sblk sub-blocks information
530534 */
531535 struct dpu_pingpong_cfg {
532536 DPU_HW_BLK_INFO;
533537 u32 merge_3d;
538+ s32 intr_done;
539+ s32 intr_rdptr;
534540 const struct dpu_pingpong_sub_blks *sblk;
535541 };
536542
@@ -555,12 +561,16 @@ struct dpu_merge_3d_cfg { · 18 unmodified lines
555561 * @type: Interface type(DSI, DP, HDMI)
556562 * @controller_id: Controller Instance ID in case of multiple of intf type
557563 * @prog_fetch_lines_worst_case Worst case latency num lines needed to prefetch
564+ * @intr_underrun: index for INTF underrun interrupt
565+ * @intr_vsync: index for INTF VSYNC interrupt
558566 */
559567 struct dpu_intf_cfg {
560568 DPU_HW_BLK_INFO;
561569 u32 type; /* interface type*/
562570 u32 controller_id;
563571 u32 prog_fetch_lines_worst_case;
572+ s32 intr_underrun;
573+ s32 intr_vsync;
564574 };
565575
566576 /**
@@ -723,7 +733,6 @@ struct dpu_perf_cfg { · 156 unmodified lines
723733 * @cursor_formats Supported formats for cursor pipe
724734 * @vig_formats Supported formats for vig pipe
725735 * @mdss_irqs: Bitmap with the irqs supported by the target
726− * @obsolete_irq: Irq types that are obsolete for a particular target
727736 */
728737 struct dpu_mdss_cfg {
729738 u32 hwversion;
@@ -770,7 +779,6 @@ struct dpu_mdss_cfg { · 40 unmodified lines
770779 const struct dpu_format_extended *vig_formats;
771780
772781 unsigned long mdss_irqs;
773− unsigned long obsolete_irq;
774782 };
775783
776784 struct dpu_mdss_hw_cfg_handler {
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c+0−6
@@ -589,8 +589,6 @@ static void _setup_ctl_ops(struct dpu_hw_ctl_ops *ops, · 588 unmodified lines
589589 ops->set_active_pipes = dpu_hw_ctl_set_fetch_pipe_active;
590590 };
591591
592−static struct dpu_hw_blk_ops dpu_hw_ops;
593−
594592 struct dpu_hw_ctl *dpu_hw_ctl_init(enum dpu_ctl idx,
595593 void __iomem *addr,
596594 const struct dpu_mdss_cfg *m)
@@ -615,14 +613,10 @@ struct dpu_hw_ctl *dpu_hw_ctl_init(enum dpu_ctl idx, · 18 unmodified lines
615613 c->mixer_count = m->mixer_count;
616614 c->mixer_hw_caps = m->mixer;
617615
618− dpu_hw_blk_init(&c->base, DPU_HW_BLK_CTL, idx, &dpu_hw_ops);
619−
620616 return c;
621617 }
622618
623619 void dpu_hw_ctl_destroy(struct dpu_hw_ctl *ctx)
624620 {
625− if (ctx)
626− dpu_hw_blk_destroy(&ctx->base);
627621 kfree(ctx);
628622 }
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dspp.c+0−7
@@ -85,8 +85,6 @@ static const struct dpu_dspp_cfg *_dspp_offset(enum dpu_dspp dspp, · 84 unmodified lines
8585 return ERR_PTR(-EINVAL);
8686 }
8787
88−static struct dpu_hw_blk_ops dpu_hw_ops;
89−
9088 struct dpu_hw_dspp *dpu_hw_dspp_init(enum dpu_dspp idx,
9189 void __iomem *addr,
9290 const struct dpu_mdss_cfg *m)
@@ -112,16 +110,11 @@ struct dpu_hw_dspp *dpu_hw_dspp_init(enum dpu_dspp idx, · 19 unmodified lines
112110 c->cap = cfg;
113111 _setup_dspp_ops(c, c->cap->features);
114112
115− dpu_hw_blk_init(&c->base, DPU_HW_BLK_DSPP, idx, &dpu_hw_ops);
116−
117113 return c;
118114 }
119115
120116 void dpu_hw_dspp_destroy(struct dpu_hw_dspp *dspp)
121117 {
122− if (dspp)
123− dpu_hw_blk_destroy(&dspp->base);
124−
125118 kfree(dspp);
126119 }
127120
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c+110−1398
@@ -29,145 +29,6 @@ · 28 unmodified lines
2929 #define MDP_INTF_1_OFF_REV_7xxx 0x35000
3030 #define MDP_INTF_5_OFF_REV_7xxx 0x39000
3131
32−/**
33− * WB interrupt status bit definitions
34− */
35−#define DPU_INTR_WB_0_DONE BIT(0)
36−#define DPU_INTR_WB_1_DONE BIT(1)
37−#define DPU_INTR_WB_2_DONE BIT(4)
38−
39−/**
40− * WDOG timer interrupt status bit definitions
41− */
42−#define DPU_INTR_WD_TIMER_0_DONE BIT(2)
43−#define DPU_INTR_WD_TIMER_1_DONE BIT(3)
44−#define DPU_INTR_WD_TIMER_2_DONE BIT(5)
45−#define DPU_INTR_WD_TIMER_3_DONE BIT(6)
46−#define DPU_INTR_WD_TIMER_4_DONE BIT(7)
47−
48−/**
49− * Pingpong interrupt status bit definitions
50− */
51−#define DPU_INTR_PING_PONG_0_DONE BIT(8)
52−#define DPU_INTR_PING_PONG_1_DONE BIT(9)
53−#define DPU_INTR_PING_PONG_2_DONE BIT(10)
54−#define DPU_INTR_PING_PONG_3_DONE BIT(11)
55−#define DPU_INTR_PING_PONG_0_RD_PTR BIT(12)
56−#define DPU_INTR_PING_PONG_1_RD_PTR BIT(13)
57−#define DPU_INTR_PING_PONG_2_RD_PTR BIT(14)
58−#define DPU_INTR_PING_PONG_3_RD_PTR BIT(15)
59−#define DPU_INTR_PING_PONG_0_WR_PTR BIT(16)
60−#define DPU_INTR_PING_PONG_1_WR_PTR BIT(17)
61−#define DPU_INTR_PING_PONG_2_WR_PTR BIT(18)
62−#define DPU_INTR_PING_PONG_3_WR_PTR BIT(19)
63−#define DPU_INTR_PING_PONG_0_AUTOREFRESH_DONE BIT(20)
64−#define DPU_INTR_PING_PONG_1_AUTOREFRESH_DONE BIT(21)
65−#define DPU_INTR_PING_PONG_2_AUTOREFRESH_DONE BIT(22)
66−#define DPU_INTR_PING_PONG_3_AUTOREFRESH_DONE BIT(23)
67−
68−/**
69− * Interface interrupt status bit definitions
70− */
71−#define DPU_INTR_INTF_0_UNDERRUN BIT(24)
72−#define DPU_INTR_INTF_1_UNDERRUN BIT(26)
73−#define DPU_INTR_INTF_2_UNDERRUN BIT(28)
74−#define DPU_INTR_INTF_3_UNDERRUN BIT(30)
75−#define DPU_INTR_INTF_5_UNDERRUN BIT(22)
76−#define DPU_INTR_INTF_0_VSYNC BIT(25)
77−#define DPU_INTR_INTF_1_VSYNC BIT(27)
78−#define DPU_INTR_INTF_2_VSYNC BIT(29)
79−#define DPU_INTR_INTF_3_VSYNC BIT(31)
80−#define DPU_INTR_INTF_5_VSYNC BIT(23)
81−
82−/**
83− * Pingpong Secondary interrupt status bit definitions
84− */
85−#define DPU_INTR_PING_PONG_S0_AUTOREFRESH_DONE BIT(0)
86−#define DPU_INTR_PING_PONG_S0_WR_PTR BIT(4)
87−#define DPU_INTR_PING_PONG_S0_RD_PTR BIT(8)
88−#define DPU_INTR_PING_PONG_S0_TEAR_DETECTED BIT(22)
89−#define DPU_INTR_PING_PONG_S0_TE_DETECTED BIT(28)
90−
91−/**
92− * Pingpong TEAR detection interrupt status bit definitions
93− */
94−#define DPU_INTR_PING_PONG_0_TEAR_DETECTED BIT(16)
95−#define DPU_INTR_PING_PONG_1_TEAR_DETECTED BIT(17)
96−#define DPU_INTR_PING_PONG_2_TEAR_DETECTED BIT(18)
97−#define DPU_INTR_PING_PONG_3_TEAR_DETECTED BIT(19)
98−
99−/**
100− * Pingpong TE detection interrupt status bit definitions
101− */
102−#define DPU_INTR_PING_PONG_0_TE_DETECTED BIT(24)
103−#define DPU_INTR_PING_PONG_1_TE_DETECTED BIT(25)
104−#define DPU_INTR_PING_PONG_2_TE_DETECTED BIT(26)
105−#define DPU_INTR_PING_PONG_3_TE_DETECTED BIT(27)
106−
107−/**
108− * Ctl start interrupt status bit definitions
109− */
110−#define DPU_INTR_CTL_0_START BIT(9)
111−#define DPU_INTR_CTL_1_START BIT(10)
112−#define DPU_INTR_CTL_2_START BIT(11)
113−#define DPU_INTR_CTL_3_START BIT(12)
114−#define DPU_INTR_CTL_4_START BIT(13)
115−
116−/**
117− * Concurrent WB overflow interrupt status bit definitions
118− */
119−#define DPU_INTR_CWB_2_OVERFLOW BIT(14)
120−#define DPU_INTR_CWB_3_OVERFLOW BIT(15)
121−
122−/**
123− * Histogram VIG done interrupt status bit definitions
124− */
125−#define DPU_INTR_HIST_VIG_0_DONE BIT(0)
126−#define DPU_INTR_HIST_VIG_1_DONE BIT(4)
127−#define DPU_INTR_HIST_VIG_2_DONE BIT(8)
128−#define DPU_INTR_HIST_VIG_3_DONE BIT(10)
129−
130−/**
131− * Histogram VIG reset Sequence done interrupt status bit definitions
132− */
133−#define DPU_INTR_HIST_VIG_0_RSTSEQ_DONE BIT(1)
134−#define DPU_INTR_HIST_VIG_1_RSTSEQ_DONE BIT(5)
135−#define DPU_INTR_HIST_VIG_2_RSTSEQ_DONE BIT(9)
136−#define DPU_INTR_HIST_VIG_3_RSTSEQ_DONE BIT(11)
137−
138−/**
139− * Histogram DSPP done interrupt status bit definitions
140− */
141−#define DPU_INTR_HIST_DSPP_0_DONE BIT(12)
142−#define DPU_INTR_HIST_DSPP_1_DONE BIT(16)
143−#define DPU_INTR_HIST_DSPP_2_DONE BIT(20)
144−#define DPU_INTR_HIST_DSPP_3_DONE BIT(22)
145−
146−/**
147− * Histogram DSPP reset Sequence done interrupt status bit definitions
148− */
149−#define DPU_INTR_HIST_DSPP_0_RSTSEQ_DONE BIT(13)
150−#define DPU_INTR_HIST_DSPP_1_RSTSEQ_DONE BIT(17)
151−#define DPU_INTR_HIST_DSPP_2_RSTSEQ_DONE BIT(21)
152−#define DPU_INTR_HIST_DSPP_3_RSTSEQ_DONE BIT(23)
153−
154−/**
155− * INTF interrupt status bit definitions
156− */
157−#define DPU_INTR_VIDEO_INTO_STATIC BIT(0)
158−#define DPU_INTR_VIDEO_OUTOF_STATIC BIT(1)
159−#define DPU_INTR_DSICMD_0_INTO_STATIC BIT(2)
160−#define DPU_INTR_DSICMD_0_OUTOF_STATIC BIT(3)
161−#define DPU_INTR_DSICMD_1_INTO_STATIC BIT(4)
162−#define DPU_INTR_DSICMD_1_OUTOF_STATIC BIT(5)
163−#define DPU_INTR_DSICMD_2_INTO_STATIC BIT(6)
164−#define DPU_INTR_DSICMD_2_OUTOF_STATIC BIT(7)
165−#define DPU_INTR_PROG_LINE BIT(8)
166−
167−/**
168− * AD4 interrupt status bit definitions
169− */
170−#define DPU_INTR_BACKLIGHT_UPDATED BIT(0)
17132 /**
17233 * struct dpu_intr_reg - array of DPU register sets
17334 * @clr_off: offset to CLEAR reg
@@ -180,22 +41,10 @@ struct dpu_intr_reg { · 6 unmodified lines
18041 u32 status_off;
18142 };
18243
183−/**
184− * struct dpu_irq_type - maps each irq with i/f
185− * @intr_type: type of interrupt listed in dpu_intr_type
186− * @instance_idx: instance index of the associated HW block in DPU
187− * @irq_mask: corresponding bit in the interrupt status reg
188− * @reg_idx: which reg set to use
189− */
190−struct dpu_irq_type {
191− u32 intr_type;
192− u32 instance_idx;
193− u32 irq_mask;
194− u32 reg_idx;
195−};
196−
19744 /*
19845 * struct dpu_intr_reg - List of DPU interrupt registers
46+ *
47+ * When making changes be sure to sync with dpu_hw_intr_reg
19948 */
20049 static const struct dpu_intr_reg dpu_intr_set[] = {
20150 {
@@ -265,1101 +114,22 @@ static const struct dpu_intr_reg dpu_intr_set[] = { · 63 unmodified lines
265114 },
266115 };
267116
268−/*
269− * struct dpu_irq_type - IRQ mapping table use for lookup an irq_idx in this
270− * table that have a matching interface type and
271− * instance index.
272− */
273−static const struct dpu_irq_type dpu_irq_map[] = {
274− /* BEGIN MAP_RANGE: 0-31, INTR */
275− /* irq_idx: 0-3 */
276− { DPU_IRQ_TYPE_WB_ROT_COMP, WB_0, DPU_INTR_WB_0_DONE, 0},
277− { DPU_IRQ_TYPE_WB_ROT_COMP, WB_1, DPU_INTR_WB_1_DONE, 0},
278− { DPU_IRQ_TYPE_WD_TIMER, WD_TIMER_0, DPU_INTR_WD_TIMER_0_DONE, 0},
279− { DPU_IRQ_TYPE_WD_TIMER, WD_TIMER_1, DPU_INTR_WD_TIMER_1_DONE, 0},
280− /* irq_idx: 4-7 */
281− { DPU_IRQ_TYPE_WB_WFD_COMP, WB_2, DPU_INTR_WB_2_DONE, 0},
282− { DPU_IRQ_TYPE_WD_TIMER, WD_TIMER_2, DPU_INTR_WD_TIMER_2_DONE, 0},
283− { DPU_IRQ_TYPE_WD_TIMER, WD_TIMER_3, DPU_INTR_WD_TIMER_3_DONE, 0},
284− { DPU_IRQ_TYPE_WD_TIMER, WD_TIMER_4, DPU_INTR_WD_TIMER_4_DONE, 0},
285− /* irq_idx: 8-11 */
286− { DPU_IRQ_TYPE_PING_PONG_COMP, PINGPONG_0,
287− DPU_INTR_PING_PONG_0_DONE, 0},
288− { DPU_IRQ_TYPE_PING_PONG_COMP, PINGPONG_1,
289− DPU_INTR_PING_PONG_1_DONE, 0},
290− { DPU_IRQ_TYPE_PING_PONG_COMP, PINGPONG_2,
291− DPU_INTR_PING_PONG_2_DONE, 0},
292− { DPU_IRQ_TYPE_PING_PONG_COMP, PINGPONG_3,
293− DPU_INTR_PING_PONG_3_DONE, 0},
294− /* irq_idx: 12-15 */
295− { DPU_IRQ_TYPE_PING_PONG_RD_PTR, PINGPONG_0,
296− DPU_INTR_PING_PONG_0_RD_PTR, 0},
297− { DPU_IRQ_TYPE_PING_PONG_RD_PTR, PINGPONG_1,
298− DPU_INTR_PING_PONG_1_RD_PTR, 0},
299− { DPU_IRQ_TYPE_PING_PONG_RD_PTR, PINGPONG_2,
300− DPU_INTR_PING_PONG_2_RD_PTR, 0},
301− { DPU_IRQ_TYPE_PING_PONG_RD_PTR, PINGPONG_3,
302− DPU_INTR_PING_PONG_3_RD_PTR, 0},
303− /* irq_idx: 16-19 */
304− { DPU_IRQ_TYPE_PING_PONG_WR_PTR, PINGPONG_0,
305− DPU_INTR_PING_PONG_0_WR_PTR, 0},
306− { DPU_IRQ_TYPE_PING_PONG_WR_PTR, PINGPONG_1,
307− DPU_INTR_PING_PONG_1_WR_PTR, 0},
308− { DPU_IRQ_TYPE_PING_PONG_WR_PTR, PINGPONG_2,
309− DPU_INTR_PING_PONG_2_WR_PTR, 0},
310− { DPU_IRQ_TYPE_PING_PONG_WR_PTR, PINGPONG_3,
311− DPU_INTR_PING_PONG_3_WR_PTR, 0},
312− /* irq_idx: 20-23 */
313− { DPU_IRQ_TYPE_PING_PONG_AUTO_REF, PINGPONG_0,
314− DPU_INTR_PING_PONG_0_AUTOREFRESH_DONE, 0},
315− { DPU_IRQ_TYPE_PING_PONG_AUTO_REF, PINGPONG_1,
316− DPU_INTR_PING_PONG_1_AUTOREFRESH_DONE, 0},
317− { DPU_IRQ_TYPE_PING_PONG_AUTO_REF, PINGPONG_2,
318− DPU_INTR_PING_PONG_2_AUTOREFRESH_DONE, 0},
319− { DPU_IRQ_TYPE_PING_PONG_AUTO_REF, PINGPONG_3,
320− DPU_INTR_PING_PONG_3_AUTOREFRESH_DONE, 0},
321− /* irq_idx: 24-27 */
322− { DPU_IRQ_TYPE_INTF_UNDER_RUN, INTF_0, DPU_INTR_INTF_0_UNDERRUN, 0},
323− { DPU_IRQ_TYPE_INTF_VSYNC, INTF_0, DPU_INTR_INTF_0_VSYNC, 0},
324− { DPU_IRQ_TYPE_INTF_UNDER_RUN, INTF_1, DPU_INTR_INTF_1_UNDERRUN, 0},
325− { DPU_IRQ_TYPE_INTF_VSYNC, INTF_1, DPU_INTR_INTF_1_VSYNC, 0},
326− /* irq_idx: 28-31 */
327− { DPU_IRQ_TYPE_INTF_UNDER_RUN, INTF_2, DPU_INTR_INTF_2_UNDERRUN, 0},
328− { DPU_IRQ_TYPE_INTF_VSYNC, INTF_2, DPU_INTR_INTF_2_VSYNC, 0},
329− { DPU_IRQ_TYPE_INTF_UNDER_RUN, INTF_3, DPU_INTR_INTF_3_UNDERRUN, 0},
330− { DPU_IRQ_TYPE_INTF_VSYNC, INTF_3, DPU_INTR_INTF_3_VSYNC, 0},
331− /* irq_idx:32-33 */
332− { DPU_IRQ_TYPE_INTF_UNDER_RUN, INTF_5, DPU_INTR_INTF_5_UNDERRUN, 0},
333− { DPU_IRQ_TYPE_INTF_VSYNC, INTF_5, DPU_INTR_INTF_5_VSYNC, 0},
334− /* irq_idx:34-63 */
335− { DPU_IRQ_TYPE_RESERVED, 0, 0, 0},
336− { DPU_IRQ_TYPE_RESERVED, 0, 0, 0},
337− { DPU_IRQ_TYPE_RESERVED, 0, 0, 0},
338− { DPU_IRQ_TYPE_RESERVED, 0, 0, 0},
339− { DPU_IRQ_TYPE_RESERVED, 0, 0, 0},
340− { DPU_IRQ_TYPE_RESERVED, 0, 0, 0},
341− { DPU_IRQ_TYPE_RESERVED, 0, 0, 0},
342− { DPU_IRQ_TYPE_RESERVED, 0, 0, 0},
343− { DPU_IRQ_TYPE_RESERVED, 0, 0, 0},
344− { DPU_IRQ_TYPE_RESERVED, 0, 0, 0},
345− { DPU_IRQ_TYPE_RESERVED, 0, 0, 0},
346− { DPU_IRQ_TYPE_RESERVED, 0, 0, 0},
347− { DPU_IRQ_TYPE_RESERVED, 0, 0, 0},
348− { DPU_IRQ_TYPE_RESERVED, 0, 0, 0},
349− { DPU_IRQ_TYPE_RESERVED, 0, 0, 0},
350− { DPU_IRQ_TYPE_RESERVED, 0, 0, 0},
351− { DPU_IRQ_TYPE_RESERVED, 0, 0, 0},
352− { DPU_IRQ_TYPE_RESERVED, 0, 0, 0},
353− { DPU_IRQ_TYPE_RESERVED, 0, 0, 0},
354− { DPU_IRQ_TYPE_RESERVED, 0, 0, 0},
355− { DPU_IRQ_TYPE_RESERVED, 0, 0, 0},
356− { DPU_IRQ_TYPE_RESERVED, 0, 0, 0},
357− { DPU_IRQ_TYPE_RESERVED, 0, 0, 0},
358− { DPU_IRQ_TYPE_RESERVED, 0, 0, 0},
359− { DPU_IRQ_TYPE_RESERVED, 0, 0, 0},
360− { DPU_IRQ_TYPE_RESERVED, 0, 0, 0},
361− { DPU_IRQ_TYPE_RESERVED, 0, 0, 0},
362− { DPU_IRQ_TYPE_RESERVED, 0, 0, 0},
363− { DPU_IRQ_TYPE_RESERVED, 0, 0, 0},
364− { DPU_IRQ_TYPE_RESERVED, 0, 0, 0},
365− { DPU_IRQ_TYPE_RESERVED, 0, 0, 0},
366− { DPU_IRQ_TYPE_RESERVED, 0, 0, 0},
367− /* BEGIN MAP_RANGE: 64-95, INTR2 */
368− /* irq_idx: 64-67 */
369− { DPU_IRQ_TYPE_PING_PONG_AUTO_REF, PINGPONG_S0,
370− DPU_INTR_PING_PONG_S0_AUTOREFRESH_DONE, 1},
371− { DPU_IRQ_TYPE_RESERVED, 0, 0, 1},
372− { DPU_IRQ_TYPE_RESERVED, 0, 0, 1},
373− { DPU_IRQ_TYPE_RESERVED, 0, 0, 1},
374− /* irq_idx: 68-71 */
375− { DPU_IRQ_TYPE_PING_PONG_WR_PTR, PINGPONG_S0,
376− DPU_INTR_PING_PONG_S0_WR_PTR, 1},
377− { DPU_IRQ_TYPE_RESERVED, 0, 0, 1},
378− { DPU_IRQ_TYPE_RESERVED, 0, 0, 1},
379− { DPU_IRQ_TYPE_RESERVED, 0, 0, 1},
380− /* irq_idx: 72 */
381− { DPU_IRQ_TYPE_PING_PONG_RD_PTR, PINGPONG_S0,
382− DPU_INTR_PING_PONG_S0_RD_PTR, 1},
383− /* irq_idx: 73-77 */
384− { DPU_IRQ_TYPE_CTL_START, CTL_0,
385− DPU_INTR_CTL_0_START, 1},
386− { DPU_IRQ_TYPE_CTL_START, CTL_1,
387− DPU_INTR_CTL_1_START, 1},
388− { DPU_IRQ_TYPE_CTL_START, CTL_2,
389− DPU_INTR_CTL_2_START, 1},
390− { DPU_IRQ_TYPE_CTL_START, CTL_3,
391− DPU_INTR_CTL_3_START, 1},
392− { DPU_IRQ_TYPE_CTL_START, CTL_4,
393− DPU_INTR_CTL_4_START, 1},
394− /* irq_idx: 78-79 */
395− { DPU_IRQ_TYPE_CWB_OVERFLOW, CWB_2, DPU_INTR_CWB_2_OVERFLOW, 1},
396− { DPU_IRQ_TYPE_CWB_OVERFLOW, CWB_3, DPU_INTR_CWB_3_OVERFLOW, 1},
397− /* irq_idx: 80-83 */
398− { DPU_IRQ_TYPE_PING_PONG_TEAR_CHECK, PINGPONG_0,
399− DPU_INTR_PING_PONG_0_TEAR_DETECTED, 1},
400− { DPU_IRQ_TYPE_PING_PONG_TEAR_CHECK, PINGPONG_1,
401− DPU_INTR_PING_PONG_1_TEAR_DETECTED, 1},
402− { DPU_IRQ_TYPE_PING_PONG_TEAR_CHECK, PINGPONG_2,
403− DPU_INTR_PING_PONG_2_TEAR_DETECTED, 1},
404− { DPU_IRQ_TYPE_PING_PONG_TEAR_CHECK, PINGPONG_3,
405− DPU_INTR_PING_PONG_3_TEAR_DETECTED, 1},
406− /* irq_idx: 84-87 */
407− { DPU_IRQ_TYPE_RESERVED, 0, 0, 1},
408− { DPU_IRQ_TYPE_RESERVED, 0, 0, 1},
409− { DPU_IRQ_TYPE_PING_PONG_TEAR_CHECK, PINGPONG_S0,
410− DPU_INTR_PING_PONG_S0_TEAR_DETECTED, 1},
411− { DPU_IRQ_TYPE_RESERVED, 0, 0, 1},
412− /* irq_idx: 88-91 */
413− { DPU_IRQ_TYPE_PING_PONG_TE_CHECK, PINGPONG_0,
414− DPU_INTR_PING_PONG_0_TE_DETECTED, 1},
415− { DPU_IRQ_TYPE_PING_PONG_TE_CHECK, PINGPONG_1,
416− DPU_INTR_PING_PONG_1_TE_DETECTED, 1},
417− { DPU_IRQ_TYPE_PING_PONG_TE_CHECK, PINGPONG_2,
418− DPU_INTR_PING_PONG_2_TE_DETECTED, 1},
419− { DPU_IRQ_TYPE_PING_PONG_TE_CHECK, PINGPONG_3,
420− DPU_INTR_PING_PONG_3_TE_DETECTED, 1},
421− /* irq_idx: 92-95 */
422− { DPU_IRQ_TYPE_PING_PONG_TE_CHECK, PINGPONG_S0,
423− DPU_INTR_PING_PONG_S0_TE_DETECTED, 1},
424− { DPU_IRQ_TYPE_RESERVED, 0, 0, 1},
425− { DPU_IRQ_TYPE_RESERVED, 0, 0, 1},
426− { DPU_IRQ_TYPE_RESERVED, 0, 0, 1},
427− /* irq_idx: 96-127 */
428− { DPU_IRQ_TYPE_RESERVED, 0, 0, 1},
429− { DPU_IRQ_TYPE_RESERVED, 0, 0, 1},
430− { DPU_IRQ_TYPE_RESERVED, 0, 0, 1},
431− { DPU_IRQ_TYPE_RESERVED, 0, 0, 1},
432− { DPU_IRQ_TYPE_RESERVED, 0, 0, 1},
433− { DPU_IRQ_TYPE_RESERVED, 0, 0, 1},
434− { DPU_IRQ_TYPE_RESERVED, 0, 0, 1},
435− { DPU_IRQ_TYPE_RESERVED, 0, 0, 1},
436− { DPU_IRQ_TYPE_RESERVED, 0, 0, 1},
437− { DPU_IRQ_TYPE_RESERVED, 0, 0, 1},
438− { DPU_IRQ_TYPE_RESERVED, 0, 0, 1},
439− { DPU_IRQ_TYPE_RESERVED, 0, 0, 1},
440− { DPU_IRQ_TYPE_RESERVED, 0, 0, 1},
441− { DPU_IRQ_TYPE_RESERVED, 0, 0, 1},
442− { DPU_IRQ_TYPE_RESERVED, 0, 0, 1},
443− { DPU_IRQ_TYPE_RESERVED, 0, 0, 1},
444− { DPU_IRQ_TYPE_RESERVED, 0, 0, 1},
445− { DPU_IRQ_TYPE_RESERVED, 0, 0, 1},
446− { DPU_IRQ_TYPE_RESERVED, 0, 0, 1},
447− { DPU_IRQ_TYPE_RESERVED, 0, 0, 1},
448− { DPU_IRQ_TYPE_RESERVED, 0, 0, 1},
449− { DPU_IRQ_TYPE_RESERVED, 0, 0, 1},
450− { DPU_IRQ_TYPE_RESERVED, 0, 0, 1},
451− { DPU_IRQ_TYPE_RESERVED, 0, 0, 1},
452− { DPU_IRQ_TYPE_RESERVED, 0, 0, 1},
453− { DPU_IRQ_TYPE_RESERVED, 0, 0, 1},
454− { DPU_IRQ_TYPE_RESERVED, 0, 0, 1},
455− { DPU_IRQ_TYPE_RESERVED, 0, 0, 1},
456− { DPU_IRQ_TYPE_RESERVED, 0, 0, 1},
457− { DPU_IRQ_TYPE_RESERVED, 0, 0, 1},
458− { DPU_IRQ_TYPE_RESERVED, 0, 0, 1},
459− { DPU_IRQ_TYPE_RESERVED, 0, 0, 1},
460− /* BEGIN MAP_RANGE: 128-159 HIST */
461− /* irq_idx: 128-131 */
462− { DPU_IRQ_TYPE_HIST_VIG_DONE, SSPP_VIG0, DPU_INTR_HIST_VIG_0_DONE, 2},
463− { DPU_IRQ_TYPE_HIST_VIG_RSTSEQ, SSPP_VIG0,
464− DPU_INTR_HIST_VIG_0_RSTSEQ_DONE, 2},
465− { DPU_IRQ_TYPE_RESERVED, 0, 0, 2},
466− { DPU_IRQ_TYPE_RESERVED, 0, 0, 2},
467− /* irq_idx: 132-135 */
468− { DPU_IRQ_TYPE_HIST_VIG_DONE, SSPP_VIG1, DPU_INTR_HIST_VIG_1_DONE, 2},
469− { DPU_IRQ_TYPE_HIST_VIG_RSTSEQ, SSPP_VIG1,
470− DPU_INTR_HIST_VIG_1_RSTSEQ_DONE, 2},
471− { DPU_IRQ_TYPE_RESERVED, 0, 0, 2},
472− { DPU_IRQ_TYPE_RESERVED, 0, 0, 2},
473− /* irq_idx: 136-139 */
474− { DPU_IRQ_TYPE_HIST_VIG_DONE, SSPP_VIG2, DPU_INTR_HIST_VIG_2_DONE, 2},
475− { DPU_IRQ_TYPE_HIST_VIG_RSTSEQ, SSPP_VIG2,
476− DPU_INTR_HIST_VIG_2_RSTSEQ_DONE, 2},
477− { DPU_IRQ_TYPE_HIST_VIG_DONE, SSPP_VIG3, DPU_INTR_HIST_VIG_3_DONE, 2},
478− { DPU_IRQ_TYPE_HIST_VIG_RSTSEQ, SSPP_VIG3,
479− DPU_INTR_HIST_VIG_3_RSTSEQ_DONE, 2},
480− /* irq_idx: 140-143 */
481− { DPU_IRQ_TYPE_HIST_DSPP_DONE, DSPP_0, DPU_INTR_HIST_DSPP_0_DONE, 2},
482− { DPU_IRQ_TYPE_HIST_DSPP_RSTSEQ, DSPP_0,
483− DPU_INTR_HIST_DSPP_0_RSTSEQ_DONE, 2},
484− { DPU_IRQ_TYPE_RESERVED, 0, 0, 2},
485− { DPU_IRQ_TYPE_RESERVED, 0, 0, 2},
486− /* irq_idx: 144-147 */
487− { DPU_IRQ_TYPE_HIST_DSPP_DONE, DSPP_1, DPU_INTR_HIST_DSPP_1_DONE, 2},
488− { DPU_IRQ_TYPE_HIST_DSPP_RSTSEQ, DSPP_1,
489− DPU_INTR_HIST_DSPP_1_RSTSEQ_DONE, 2},
490− { DPU_IRQ_TYPE_RESERVED, 0, 0, 2},
491− { DPU_IRQ_TYPE_RESERVED, 0, 0, 2},
492− /* irq_idx: 148-151 */
493− { DPU_IRQ_TYPE_HIST_DSPP_DONE, DSPP_2, DPU_INTR_HIST_DSPP_2_DONE, 2},
494− { DPU_IRQ_TYPE_HIST_DSPP_RSTSEQ, DSPP_2,
495− DPU_INTR_HIST_DSPP_2_RSTSEQ_DONE, 2},
496− { DPU_IRQ_TYPE_HIST_DSPP_DONE, DSPP_3, DPU_INTR_HIST_DSPP_3_DONE, 2},
497− { DPU_IRQ_TYPE_HIST_DSPP_RSTSEQ, DSPP_3,
498− DPU_INTR_HIST_DSPP_3_RSTSEQ_DONE, 2},
499− /* irq_idx: 152-155 */
500− { DPU_IRQ_TYPE_RESERVED, 0, 0, 2},
501− { DPU_IRQ_TYPE_RESERVED, 0, 0, 2},
502− { DPU_IRQ_TYPE_RESERVED, 0, 0, 2},
503− { DPU_IRQ_TYPE_RESERVED, 0, 0, 2},
504− /* irq_idx: 156-159 */
505− { DPU_IRQ_TYPE_RESERVED, 0, 0, 2},
506− { DPU_IRQ_TYPE_RESERVED, 0, 0, 2},
507− { DPU_IRQ_TYPE_RESERVED, 0, 0, 2},
508− { DPU_IRQ_TYPE_RESERVED, 0, 0, 2},
509− /* irq_idx: 160-191 */
510− { DPU_IRQ_TYPE_RESERVED, 0, 0, 2},
511− { DPU_IRQ_TYPE_RESERVED, 0, 0, 2},
512− { DPU_IRQ_TYPE_RESERVED, 0, 0, 2},
513− { DPU_IRQ_TYPE_RESERVED, 0, 0, 2},
514− { DPU_IRQ_TYPE_RESERVED, 0, 0, 2},
515− { DPU_IRQ_TYPE_RESERVED, 0, 0, 2},
516− { DPU_IRQ_TYPE_RESERVED, 0, 0, 2},
517− { DPU_IRQ_TYPE_RESERVED, 0, 0, 2},
518− { DPU_IRQ_TYPE_RESERVED, 0, 0, 2},
519− { DPU_IRQ_TYPE_RESERVED, 0, 0, 2},
520− { DPU_IRQ_TYPE_RESERVED, 0, 0, 2},
521− { DPU_IRQ_TYPE_RESERVED, 0, 0, 2},
522− { DPU_IRQ_TYPE_RESERVED, 0, 0, 2},
523− { DPU_IRQ_TYPE_RESERVED, 0, 0, 2},
524− { DPU_IRQ_TYPE_RESERVED, 0, 0, 2},
525− { DPU_IRQ_TYPE_RESERVED, 0, 0, 2},
526− { DPU_IRQ_TYPE_RESERVED, 0, 0, 2},
527− { DPU_IRQ_TYPE_RESERVED, 0, 0, 2},
528− { DPU_IRQ_TYPE_RESERVED, 0, 0, 2},
529− { DPU_IRQ_TYPE_RESERVED, 0, 0, 2},
530− { DPU_IRQ_TYPE_RESERVED, 0, 0, 2},
531− { DPU_IRQ_TYPE_RESERVED, 0, 0, 2},
532− { DPU_IRQ_TYPE_RESERVED, 0, 0, 2},
533− { DPU_IRQ_TYPE_RESERVED, 0, 0, 2},
534− { DPU_IRQ_TYPE_RESERVED, 0, 0, 2},
535− { DPU_IRQ_TYPE_RESERVED, 0, 0, 2},
536− { DPU_IRQ_TYPE_RESERVED, 0, 0, 2},
537− { DPU_IRQ_TYPE_RESERVED, 0, 0, 2},
538− { DPU_IRQ_TYPE_RESERVED, 0, 0, 2},
539− { DPU_IRQ_TYPE_RESERVED, 0, 0, 2},
540− { DPU_IRQ_TYPE_RESERVED, 0, 0, 2},
541− { DPU_IRQ_TYPE_RESERVED, 0, 0, 2},
542− /* BEGIN MAP_RANGE: 192-255 INTF_0_INTR */
543− /* irq_idx: 192-195 */
544− { DPU_IRQ_TYPE_SFI_VIDEO_IN, INTF_0,
545− DPU_INTR_VIDEO_INTO_STATIC, 3},
546− { DPU_IRQ_TYPE_SFI_VIDEO_OUT, INTF_0,
547− DPU_INTR_VIDEO_OUTOF_STATIC, 3},
548− { DPU_IRQ_TYPE_SFI_CMD_0_IN, INTF_0,
549− DPU_INTR_DSICMD_0_INTO_STATIC, 3},
550− { DPU_IRQ_TYPE_SFI_CMD_0_OUT, INTF_0,
551− DPU_INTR_DSICMD_0_OUTOF_STATIC, 3},
552− /* irq_idx: 196-199 */
553− { DPU_IRQ_TYPE_SFI_CMD_1_IN, INTF_0,
554− DPU_INTR_DSICMD_1_INTO_STATIC, 3},
555− { DPU_IRQ_TYPE_SFI_CMD_1_OUT, INTF_0,
556− DPU_INTR_DSICMD_1_OUTOF_STATIC, 3},
557− { DPU_IRQ_TYPE_SFI_CMD_2_IN, INTF_0,
558− DPU_INTR_DSICMD_2_INTO_STATIC, 3},
559− { DPU_IRQ_TYPE_SFI_CMD_2_OUT, INTF_0,
560− DPU_INTR_DSICMD_2_OUTOF_STATIC, 3},
561− /* irq_idx: 200-203 */
562− { DPU_IRQ_TYPE_PROG_LINE, INTF_0, DPU_INTR_PROG_LINE, 3},
563− { DPU_IRQ_TYPE_RESERVED, 0, 0, 3},
564− { DPU_IRQ_TYPE_RESERVED, 0, 0, 3},
565− { DPU_IRQ_TYPE_RESERVED, 0, 0, 3},
566− /* irq_idx: 204-207 */
567− { DPU_IRQ_TYPE_RESERVED, 0, 0, 3},
568− { DPU_IRQ_TYPE_RESERVED, 0, 0, 3},
569− { DPU_IRQ_TYPE_RESERVED, 0, 0, 3},
570− { DPU_IRQ_TYPE_RESERVED, 0, 0, 3},
571− /* irq_idx: 208-211 */
572− { DPU_IRQ_TYPE_RESERVED, 0, 0, 3},
573− { DPU_IRQ_TYPE_RESERVED, 0, 0, 3},
574− { DPU_IRQ_TYPE_RESERVED, 0, 0, 3},
575− { DPU_IRQ_TYPE_RESERVED, 0, 0, 3},
576− /* irq_idx: 212-215 */
577− { DPU_IRQ_TYPE_RESERVED, 0, 0, 3},
578− { DPU_IRQ_TYPE_RESERVED, 0, 0, 3},
579− { DPU_IRQ_TYPE_RESERVED, 0, 0, 3},
580− { DPU_IRQ_TYPE_RESERVED, 0, 0, 3},
581− /* irq_idx: 216-219 */
582− { DPU_IRQ_TYPE_RESERVED, 0, 0, 3},
583− { DPU_IRQ_TYPE_RESERVED, 0, 0, 3},
584− { DPU_IRQ_TYPE_RESERVED, 0, 0, 3},
585− { DPU_IRQ_TYPE_RESERVED, 0, 0, 3},
586− /* irq_idx: 220-223 */
587− { DPU_IRQ_TYPE_RESERVED, 0, 0, 3},
588− { DPU_IRQ_TYPE_RESERVED, 0, 0, 3},
589− { DPU_IRQ_TYPE_RESERVED, 0, 0, 3},
590− { DPU_IRQ_TYPE_RESERVED, 0, 0, 3},
591− /* irq_idx: 224-255 */
592− { DPU_IRQ_TYPE_RESERVED, 0, 0, 3},
593− { DPU_IRQ_TYPE_RESERVED, 0, 0, 3},
594− { DPU_IRQ_TYPE_RESERVED, 0, 0, 3},
595− { DPU_IRQ_TYPE_RESERVED, 0, 0, 3},
596− { DPU_IRQ_TYPE_RESERVED, 0, 0, 3},
597− { DPU_IRQ_TYPE_RESERVED, 0, 0, 3},
598− { DPU_IRQ_TYPE_RESERVED, 0, 0, 3},
599− { DPU_IRQ_TYPE_RESERVED, 0, 0, 3},
600− { DPU_IRQ_TYPE_RESERVED, 0, 0, 3},
601− { DPU_IRQ_TYPE_RESERVED, 0, 0, 3},
602− { DPU_IRQ_TYPE_RESERVED, 0, 0, 3},
603− { DPU_IRQ_TYPE_RESERVED, 0, 0, 3},
604− { DPU_IRQ_TYPE_RESERVED, 0, 0, 3},
605− { DPU_IRQ_TYPE_RESERVED, 0, 0, 3},
606− { DPU_IRQ_TYPE_RESERVED, 0, 0, 3},
607− { DPU_IRQ_TYPE_RESERVED, 0, 0, 3},
608− { DPU_IRQ_TYPE_RESERVED, 0, 0, 3},
609− { DPU_IRQ_TYPE_RESERVED, 0, 0, 3},
610− { DPU_IRQ_TYPE_RESERVED, 0, 0, 3},
611− { DPU_IRQ_TYPE_RESERVED, 0, 0, 3},
612− { DPU_IRQ_TYPE_RESERVED, 0, 0, 3},
613− { DPU_IRQ_TYPE_RESERVED, 0, 0, 3},
614− { DPU_IRQ_TYPE_RESERVED, 0, 0, 3},
615− { DPU_IRQ_TYPE_RESERVED, 0, 0, 3},
616− { DPU_IRQ_TYPE_RESERVED, 0, 0, 3},
617− { DPU_IRQ_TYPE_RESERVED, 0, 0, 3},
618− { DPU_IRQ_TYPE_RESERVED, 0, 0, 3},
619− { DPU_IRQ_TYPE_RESERVED, 0, 0, 3},
620− { DPU_IRQ_TYPE_RESERVED, 0, 0, 3},
621− { DPU_IRQ_TYPE_RESERVED, 0, 0, 3},
622− { DPU_IRQ_TYPE_RESERVED, 0, 0, 3},
623− { DPU_IRQ_TYPE_RESERVED, 0, 0, 3},
624− /* BEGIN MAP_RANGE: 256-319 INTF_1_INTR */
625− /* irq_idx: 256-259 */
626− { DPU_IRQ_TYPE_SFI_VIDEO_IN, INTF_1,
627− DPU_INTR_VIDEO_INTO_STATIC, 4},
628− { DPU_IRQ_TYPE_SFI_VIDEO_OUT, INTF_1,
629− DPU_INTR_VIDEO_OUTOF_STATIC, 4},
630− { DPU_IRQ_TYPE_SFI_CMD_0_IN, INTF_1,
631− DPU_INTR_DSICMD_0_INTO_STATIC, 4},
632− { DPU_IRQ_TYPE_SFI_CMD_0_OUT, INTF_1,
633− DPU_INTR_DSICMD_0_OUTOF_STATIC, 4},
634− /* irq_idx: 260-263 */
635− { DPU_IRQ_TYPE_SFI_CMD_1_IN, INTF_1,
636− DPU_INTR_DSICMD_1_INTO_STATIC, 4},
637− { DPU_IRQ_TYPE_SFI_CMD_1_OUT, INTF_1,
638− DPU_INTR_DSICMD_1_OUTOF_STATIC, 4},
639− { DPU_IRQ_TYPE_SFI_CMD_2_IN, INTF_1,
640− DPU_INTR_DSICMD_2_INTO_STATIC, 4},
641− { DPU_IRQ_TYPE_SFI_CMD_2_OUT, INTF_1,
642− DPU_INTR_DSICMD_2_OUTOF_STATIC, 4},
643− /* irq_idx: 264-267 */
644− { DPU_IRQ_TYPE_PROG_LINE, INTF_1, DPU_INTR_PROG_LINE, 4},
645− { DPU_IRQ_TYPE_RESERVED, 0, 0, 4},
646− { DPU_IRQ_TYPE_RESERVED, 0, 0, 4},
647− { DPU_IRQ_TYPE_RESERVED, 0, 0, 4},
648− /* irq_idx: 268-271 */
649− { DPU_IRQ_TYPE_RESERVED, 0, 0, 4},
650− { DPU_IRQ_TYPE_RESERVED, 0, 0, 4},
651− { DPU_IRQ_TYPE_RESERVED, 0, 0, 4},
652− { DPU_IRQ_TYPE_RESERVED, 0, 0, 4},
653− /* irq_idx: 272-275 */
654− { DPU_IRQ_TYPE_RESERVED, 0, 0, 4},
655− { DPU_IRQ_TYPE_RESERVED, 0, 0, 4},
656− { DPU_IRQ_TYPE_RESERVED, 0, 0, 4},
657− { DPU_IRQ_TYPE_RESERVED, 0, 0, 4},
658− /* irq_idx: 276-279 */
659− { DPU_IRQ_TYPE_RESERVED, 0, 0, 4},
660− { DPU_IRQ_TYPE_RESERVED, 0, 0, 4},
661− { DPU_IRQ_TYPE_RESERVED, 0, 0, 4},
662− { DPU_IRQ_TYPE_RESERVED, 0, 0, 4},
663− /* irq_idx: 280-283 */
664− { DPU_IRQ_TYPE_RESERVED, 0, 0, 4},
665− { DPU_IRQ_TYPE_RESERVED, 0, 0, 4},
666− { DPU_IRQ_TYPE_RESERVED, 0, 0, 4},
667− { DPU_IRQ_TYPE_RESERVED, 0, 0, 4},
668− /* irq_idx: 284-287 */
669− { DPU_IRQ_TYPE_RESERVED, 0, 0, 4},
670− { DPU_IRQ_TYPE_RESERVED, 0, 0, 4},
671− { DPU_IRQ_TYPE_RESERVED, 0, 0, 4},
672− { DPU_IRQ_TYPE_RESERVED, 0, 0, 4},
673− /* irq_idx: 288-319 */
674− { DPU_IRQ_TYPE_RESERVED, 0, 0, 4},
675− { DPU_IRQ_TYPE_RESERVED, 0, 0, 4},
676− { DPU_IRQ_TYPE_RESERVED, 0, 0, 4},
677− { DPU_IRQ_TYPE_RESERVED, 0, 0, 4},
678− { DPU_IRQ_TYPE_RESERVED, 0, 0, 4},
679− { DPU_IRQ_TYPE_RESERVED, 0, 0, 4},
680− { DPU_IRQ_TYPE_RESERVED, 0, 0, 4},
681− { DPU_IRQ_TYPE_RESERVED, 0, 0, 4},
682− { DPU_IRQ_TYPE_RESERVED, 0, 0, 4},
683− { DPU_IRQ_TYPE_RESERVED, 0, 0, 4},
684− { DPU_IRQ_TYPE_RESERVED, 0, 0, 4},
685− { DPU_IRQ_TYPE_RESERVED, 0, 0, 4},
686− { DPU_IRQ_TYPE_RESERVED, 0, 0, 4},
687− { DPU_IRQ_TYPE_RESERVED, 0, 0, 4},
688− { DPU_IRQ_TYPE_RESERVED, 0, 0, 4},
689− { DPU_IRQ_TYPE_RESERVED, 0, 0, 4},
690− { DPU_IRQ_TYPE_RESERVED, 0, 0, 4},
691− { DPU_IRQ_TYPE_RESERVED, 0, 0, 4},
692− { DPU_IRQ_TYPE_RESERVED, 0, 0, 4},
693− { DPU_IRQ_TYPE_RESERVED, 0, 0, 4},
694− { DPU_IRQ_TYPE_RESERVED, 0, 0, 4},
695− { DPU_IRQ_TYPE_RESERVED, 0, 0, 4},
696− { DPU_IRQ_TYPE_RESERVED, 0, 0, 4},
697− { DPU_IRQ_TYPE_RESERVED, 0, 0, 4},
698− { DPU_IRQ_TYPE_RESERVED, 0, 0, 4},
699− { DPU_IRQ_TYPE_RESERVED, 0, 0, 4},
700− { DPU_IRQ_TYPE_RESERVED, 0, 0, 4},
701− { DPU_IRQ_TYPE_RESERVED, 0, 0, 4},
702− { DPU_IRQ_TYPE_RESERVED, 0, 0, 4},
703− { DPU_IRQ_TYPE_RESERVED, 0, 0, 4},
704− { DPU_IRQ_TYPE_RESERVED, 0, 0, 4},
705− { DPU_IRQ_TYPE_RESERVED, 0, 0, 4},
706− /* BEGIN MAP_RANGE: 320-383 INTF_2_INTR */
707− /* irq_idx: 320-323 */
708− { DPU_IRQ_TYPE_SFI_VIDEO_IN, INTF_2,
709− DPU_INTR_VIDEO_INTO_STATIC, 5},
710− { DPU_IRQ_TYPE_SFI_VIDEO_OUT, INTF_2,
711− DPU_INTR_VIDEO_OUTOF_STATIC, 5},
712− { DPU_IRQ_TYPE_SFI_CMD_0_IN, INTF_2,
713− DPU_INTR_DSICMD_0_INTO_STATIC, 5},
714− { DPU_IRQ_TYPE_SFI_CMD_0_OUT, INTF_2,
715− DPU_INTR_DSICMD_0_OUTOF_STATIC, 5},
716− /* irq_idx: 324-327 */
717− { DPU_IRQ_TYPE_SFI_CMD_1_IN, INTF_2,
718− DPU_INTR_DSICMD_1_INTO_STATIC, 5},
719− { DPU_IRQ_TYPE_SFI_CMD_1_OUT, INTF_2,
720− DPU_INTR_DSICMD_1_OUTOF_STATIC, 5},
721− { DPU_IRQ_TYPE_SFI_CMD_2_IN, INTF_2,
722− DPU_INTR_DSICMD_2_INTO_STATIC, 5},
723− { DPU_IRQ_TYPE_SFI_CMD_2_OUT, INTF_2,
724− DPU_INTR_DSICMD_2_OUTOF_STATIC, 5},
725− /* irq_idx: 328-331 */
726− { DPU_IRQ_TYPE_PROG_LINE, INTF_2, DPU_INTR_PROG_LINE, 5},
727− { DPU_IRQ_TYPE_RESERVED, 0, 0, 5},
728− { DPU_IRQ_TYPE_RESERVED, 0, 0, 5},
729− { DPU_IRQ_TYPE_RESERVED, 0, 0, 5},
730− /* irq_idx: 332-335 */
731− { DPU_IRQ_TYPE_RESERVED, 0, 0, 5},
732− { DPU_IRQ_TYPE_RESERVED, 0, 0, 5},
733− { DPU_IRQ_TYPE_RESERVED, 0, 0, 5},
734− { DPU_IRQ_TYPE_RESERVED, 0, 0, 5},
735− /* irq_idx: 336-339 */
736− { DPU_IRQ_TYPE_RESERVED, 0, 0, 5},
737− { DPU_IRQ_TYPE_RESERVED, 0, 0, 5},
738− { DPU_IRQ_TYPE_RESERVED, 0, 0, 5},
739− { DPU_IRQ_TYPE_RESERVED, 0, 0, 5},
740− /* irq_idx: 340-343 */
741− { DPU_IRQ_TYPE_RESERVED, 0, 0, 5},
742− { DPU_IRQ_TYPE_RESERVED, 0, 0, 5},
743− { DPU_IRQ_TYPE_RESERVED, 0, 0, 5},
744− { DPU_IRQ_TYPE_RESERVED, 0, 0, 5},
745− /* irq_idx: 344-347 */
746− { DPU_IRQ_TYPE_RESERVED, 0, 0, 5},
747− { DPU_IRQ_TYPE_RESERVED, 0, 0, 5},
748− { DPU_IRQ_TYPE_RESERVED, 0, 0, 5},
749− { DPU_IRQ_TYPE_RESERVED, 0, 0, 5},
750− /* irq_idx: 348-351 */
751− { DPU_IRQ_TYPE_RESERVED, 0, 0, 5},
752− { DPU_IRQ_TYPE_RESERVED, 0, 0, 5},
753− { DPU_IRQ_TYPE_RESERVED, 0, 0, 5},
754− { DPU_IRQ_TYPE_RESERVED, 0, 0, 5},
755− /* irq_idx: 352-383 */
756− { DPU_IRQ_TYPE_RESERVED, 0, 0, 5},
757− { DPU_IRQ_TYPE_RESERVED, 0, 0, 5},
758− { DPU_IRQ_TYPE_RESERVED, 0, 0, 5},
759− { DPU_IRQ_TYPE_RESERVED, 0, 0, 5},
760− { DPU_IRQ_TYPE_RESERVED, 0, 0, 5},
761− { DPU_IRQ_TYPE_RESERVED, 0, 0, 5},
762− { DPU_IRQ_TYPE_RESERVED, 0, 0, 5},
763− { DPU_IRQ_TYPE_RESERVED, 0, 0, 5},
764− { DPU_IRQ_TYPE_RESERVED, 0, 0, 5},
765− { DPU_IRQ_TYPE_RESERVED, 0, 0, 5},
766− { DPU_IRQ_TYPE_RESERVED, 0, 0, 5},
767− { DPU_IRQ_TYPE_RESERVED, 0, 0, 5},
768− { DPU_IRQ_TYPE_RESERVED, 0, 0, 5},
769− { DPU_IRQ_TYPE_RESERVED, 0, 0, 5},
770− { DPU_IRQ_TYPE_RESERVED, 0, 0, 5},
771− { DPU_IRQ_TYPE_RESERVED, 0, 0, 5},
772− { DPU_IRQ_TYPE_RESERVED, 0, 0, 5},
773− { DPU_IRQ_TYPE_RESERVED, 0, 0, 5},
774− { DPU_IRQ_TYPE_RESERVED, 0, 0, 5},
775− { DPU_IRQ_TYPE_RESERVED, 0, 0, 5},
776− { DPU_IRQ_TYPE_RESERVED, 0, 0, 5},
777− { DPU_IRQ_TYPE_RESERVED, 0, 0, 5},
778− { DPU_IRQ_TYPE_RESERVED, 0, 0, 5},
779− { DPU_IRQ_TYPE_RESERVED, 0, 0, 5},
780− { DPU_IRQ_TYPE_RESERVED, 0, 0, 5},
781− { DPU_IRQ_TYPE_RESERVED, 0, 0, 5},
782− { DPU_IRQ_TYPE_RESERVED, 0, 0, 5},
783− { DPU_IRQ_TYPE_RESERVED, 0, 0, 5},
784− { DPU_IRQ_TYPE_RESERVED, 0, 0, 5},
785− { DPU_IRQ_TYPE_RESERVED, 0, 0, 5},
786− { DPU_IRQ_TYPE_RESERVED, 0, 0, 5},
787− { DPU_IRQ_TYPE_RESERVED, 0, 0, 5},
788− /* BEGIN MAP_RANGE: 384-447 INTF_3_INTR */
789− /* irq_idx: 384-387 */
790− { DPU_IRQ_TYPE_SFI_VIDEO_IN, INTF_3,
791− DPU_INTR_VIDEO_INTO_STATIC, 6},
792− { DPU_IRQ_TYPE_SFI_VIDEO_OUT, INTF_3,
793− DPU_INTR_VIDEO_OUTOF_STATIC, 6},
794− { DPU_IRQ_TYPE_SFI_CMD_0_IN, INTF_3,
795− DPU_INTR_DSICMD_0_INTO_STATIC, 6},
796− { DPU_IRQ_TYPE_SFI_CMD_0_OUT, INTF_3,
797− DPU_INTR_DSICMD_0_OUTOF_STATIC, 6},
798− /* irq_idx: 388-391 */
799− { DPU_IRQ_TYPE_SFI_CMD_1_IN, INTF_3,
800− DPU_INTR_DSICMD_1_INTO_STATIC, 6},
801− { DPU_IRQ_TYPE_SFI_CMD_1_OUT, INTF_3,
802− DPU_INTR_DSICMD_1_OUTOF_STATIC, 6},
803− { DPU_IRQ_TYPE_SFI_CMD_2_IN, INTF_3,
804− DPU_INTR_DSICMD_2_INTO_STATIC, 6},
805− { DPU_IRQ_TYPE_SFI_CMD_2_OUT, INTF_3,
806− DPU_INTR_DSICMD_2_OUTOF_STATIC, 6},
807− /* irq_idx: 392-395 */
808− { DPU_IRQ_TYPE_PROG_LINE, INTF_3, DPU_INTR_PROG_LINE, 6},
809− { DPU_IRQ_TYPE_RESERVED, 0, 0, 6},
810− { DPU_IRQ_TYPE_RESERVED, 0, 0, 6},
811− { DPU_IRQ_TYPE_RESERVED, 0, 0, 6},
812− /* irq_idx: 396-399 */
813− { DPU_IRQ_TYPE_RESERVED, 0, 0, 6},
814− { DPU_IRQ_TYPE_RESERVED, 0, 0, 6},
815− { DPU_IRQ_TYPE_RESERVED, 0, 0, 6},
816− { DPU_IRQ_TYPE_RESERVED, 0, 0, 6},
817− /* irq_idx: 400-403 */
818− { DPU_IRQ_TYPE_RESERVED, 0, 0, 6},
819− { DPU_IRQ_TYPE_RESERVED, 0, 0, 6},
820− { DPU_IRQ_TYPE_RESERVED, 0, 0, 6},
821− { DPU_IRQ_TYPE_RESERVED, 0, 0, 6},
822− /* irq_idx: 404-407 */
823− { DPU_IRQ_TYPE_RESERVED, 0, 0, 6},
824− { DPU_IRQ_TYPE_RESERVED, 0, 0, 6},
825− { DPU_IRQ_TYPE_RESERVED, 0, 0, 6},
826− { DPU_IRQ_TYPE_RESERVED, 0, 0, 6},
827− /* irq_idx: 408-411 */
828− { DPU_IRQ_TYPE_RESERVED, 0, 0, 6},
829− { DPU_IRQ_TYPE_RESERVED, 0, 0, 6},
830− { DPU_IRQ_TYPE_RESERVED, 0, 0, 6},
831− { DPU_IRQ_TYPE_RESERVED, 0, 0, 6},
832− /* irq_idx: 412-415 */
833− { DPU_IRQ_TYPE_RESERVED, 0, 0, 6},
834− { DPU_IRQ_TYPE_RESERVED, 0, 0, 6},
835− { DPU_IRQ_TYPE_RESERVED, 0, 0, 6},
836− { DPU_IRQ_TYPE_RESERVED, 0, 0, 6},
837− /* irq_idx: 416-447*/
838− { DPU_IRQ_TYPE_RESERVED, 0, 0, 6},
839− { DPU_IRQ_TYPE_RESERVED, 0, 0, 6},
840− { DPU_IRQ_TYPE_RESERVED, 0, 0, 6},
841− { DPU_IRQ_TYPE_RESERVED, 0, 0, 6},
842− { DPU_IRQ_TYPE_RESERVED, 0, 0, 6},
843− { DPU_IRQ_TYPE_RESERVED, 0, 0, 6},
844− { DPU_IRQ_TYPE_RESERVED, 0, 0, 6},
845− { DPU_IRQ_TYPE_RESERVED, 0, 0, 6},
846− { DPU_IRQ_TYPE_RESERVED, 0, 0, 6},
847− { DPU_IRQ_TYPE_RESERVED, 0, 0, 6},
848− { DPU_IRQ_TYPE_RESERVED, 0, 0, 6},
849− { DPU_IRQ_TYPE_RESERVED, 0, 0, 6},
850− { DPU_IRQ_TYPE_RESERVED, 0, 0, 6},
851− { DPU_IRQ_TYPE_RESERVED, 0, 0, 6},
852− { DPU_IRQ_TYPE_RESERVED, 0, 0, 6},
853− { DPU_IRQ_TYPE_RESERVED, 0, 0, 6},
854− { DPU_IRQ_TYPE_RESERVED, 0, 0, 6},
855− { DPU_IRQ_TYPE_RESERVED, 0, 0, 6},
856− { DPU_IRQ_TYPE_RESERVED, 0, 0, 6},
857− { DPU_IRQ_TYPE_RESERVED, 0, 0, 6},
858− { DPU_IRQ_TYPE_RESERVED, 0, 0, 6},
859− { DPU_IRQ_TYPE_RESERVED, 0, 0, 6},
860− { DPU_IRQ_TYPE_RESERVED, 0, 0, 6},
861− { DPU_IRQ_TYPE_RESERVED, 0, 0, 6},
862− { DPU_IRQ_TYPE_RESERVED, 0, 0, 6},
863− { DPU_IRQ_TYPE_RESERVED, 0, 0, 6},
864− { DPU_IRQ_TYPE_RESERVED, 0, 0, 6},
865− { DPU_IRQ_TYPE_RESERVED, 0, 0, 6},
866− { DPU_IRQ_TYPE_RESERVED, 0, 0, 6},
867− { DPU_IRQ_TYPE_RESERVED, 0, 0, 6},
868− { DPU_IRQ_TYPE_RESERVED, 0, 0, 6},
869− { DPU_IRQ_TYPE_RESERVED, 0, 0, 6},
870− /* BEGIN MAP_RANGE: 448-511 INTF_4_INTR */
871− /* irq_idx: 448-451 */
872− { DPU_IRQ_TYPE_SFI_VIDEO_IN, INTF_4,
873− DPU_INTR_VIDEO_INTO_STATIC, 7},
874− { DPU_IRQ_TYPE_SFI_VIDEO_OUT, INTF_4,
875− DPU_INTR_VIDEO_OUTOF_STATIC, 7},
876− { DPU_IRQ_TYPE_SFI_CMD_0_IN, INTF_4,
877− DPU_INTR_DSICMD_0_INTO_STATIC, 7},
878− { DPU_IRQ_TYPE_SFI_CMD_0_OUT, INTF_4,
879− DPU_INTR_DSICMD_0_OUTOF_STATIC, 7},
880− /* irq_idx: 452-455 */
881− { DPU_IRQ_TYPE_SFI_CMD_1_IN, INTF_4,
882− DPU_INTR_DSICMD_1_INTO_STATIC, 7},
883− { DPU_IRQ_TYPE_SFI_CMD_1_OUT, INTF_4,
884− DPU_INTR_DSICMD_1_OUTOF_STATIC, 7},
885− { DPU_IRQ_TYPE_SFI_CMD_2_IN, INTF_4,
886− DPU_INTR_DSICMD_2_INTO_STATIC, 7},
887− { DPU_IRQ_TYPE_SFI_CMD_2_OUT, INTF_4,
888− DPU_INTR_DSICMD_2_OUTOF_STATIC, 7},
889− /* irq_idx: 456-459 */
890− { DPU_IRQ_TYPE_PROG_LINE, INTF_4, DPU_INTR_PROG_LINE, 7},
891− { DPU_IRQ_TYPE_RESERVED, 0, 0, 7},
892− { DPU_IRQ_TYPE_RESERVED, 0, 0, 7},
893− { DPU_IRQ_TYPE_RESERVED, 0, 0, 7},
894− /* irq_idx: 460-463 */
895− { DPU_IRQ_TYPE_RESERVED, 0, 0, 7},
896− { DPU_IRQ_TYPE_RESERVED, 0, 0, 7},
897− { DPU_IRQ_TYPE_RESERVED, 0, 0, 7},
898− { DPU_IRQ_TYPE_RESERVED, 0, 0, 7},
899− /* irq_idx: 464-467 */
900− { DPU_IRQ_TYPE_RESERVED, 0, 0, 7},
901− { DPU_IRQ_TYPE_RESERVED, 0, 0, 7},
902− { DPU_IRQ_TYPE_RESERVED, 0, 0, 7},
903− { DPU_IRQ_TYPE_RESERVED, 0, 0, 7},
904− /* irq_idx: 468-471 */
905− { DPU_IRQ_TYPE_RESERVED, 0, 0, 7},
906− { DPU_IRQ_TYPE_RESERVED, 0, 0, 7},
907− { DPU_IRQ_TYPE_RESERVED, 0, 0, 7},
908− { DPU_IRQ_TYPE_RESERVED, 0, 0, 7},
909− /* irq_idx: 472-475 */
910− { DPU_IRQ_TYPE_RESERVED, 0, 0, 7},
911− { DPU_IRQ_TYPE_RESERVED, 0, 0, 7},
912− { DPU_IRQ_TYPE_RESERVED, 0, 0, 7},
913− { DPU_IRQ_TYPE_RESERVED, 0, 0, 7},
914− /* irq_idx: 476-479 */
915− { DPU_IRQ_TYPE_RESERVED, 0, 0, 7},
916− { DPU_IRQ_TYPE_RESERVED, 0, 0, 7},
917− { DPU_IRQ_TYPE_RESERVED, 0, 0, 7},
918− { DPU_IRQ_TYPE_RESERVED, 0, 0, 7},
919− /* irq_idx: 480-511 */
920− { DPU_IRQ_TYPE_RESERVED, 0, 0, 7},
921− { DPU_IRQ_TYPE_RESERVED, 0, 0, 7},
922− { DPU_IRQ_TYPE_RESERVED, 0, 0, 7},
923− { DPU_IRQ_TYPE_RESERVED, 0, 0, 7},
924− { DPU_IRQ_TYPE_RESERVED, 0, 0, 7},
925− { DPU_IRQ_TYPE_RESERVED, 0, 0, 7},
926− { DPU_IRQ_TYPE_RESERVED, 0, 0, 7},
927− { DPU_IRQ_TYPE_RESERVED, 0, 0, 7},
928− { DPU_IRQ_TYPE_RESERVED, 0, 0, 7},
929− { DPU_IRQ_TYPE_RESERVED, 0, 0, 7},
930− { DPU_IRQ_TYPE_RESERVED, 0, 0, 7},
931− { DPU_IRQ_TYPE_RESERVED, 0, 0, 7},
932− { DPU_IRQ_TYPE_RESERVED, 0, 0, 7},
933− { DPU_IRQ_TYPE_RESERVED, 0, 0, 7},
934− { DPU_IRQ_TYPE_RESERVED, 0, 0, 7},
935− { DPU_IRQ_TYPE_RESERVED, 0, 0, 7},
936− { DPU_IRQ_TYPE_RESERVED, 0, 0, 7},
937− { DPU_IRQ_TYPE_RESERVED, 0, 0, 7},
938− { DPU_IRQ_TYPE_RESERVED, 0, 0, 7},
939− { DPU_IRQ_TYPE_RESERVED, 0, 0, 7},
940− { DPU_IRQ_TYPE_RESERVED, 0, 0, 7},
941− { DPU_IRQ_TYPE_RESERVED, 0, 0, 7},
942− { DPU_IRQ_TYPE_RESERVED, 0, 0, 7},
943− { DPU_IRQ_TYPE_RESERVED, 0, 0, 7},
944− { DPU_IRQ_TYPE_RESERVED, 0, 0, 7},
945− { DPU_IRQ_TYPE_RESERVED, 0, 0, 7},
946− { DPU_IRQ_TYPE_RESERVED, 0, 0, 7},
947− { DPU_IRQ_TYPE_RESERVED, 0, 0, 7},
948− { DPU_IRQ_TYPE_RESERVED, 0, 0, 7},
949− { DPU_IRQ_TYPE_RESERVED, 0, 0, 7},
950− { DPU_IRQ_TYPE_RESERVED, 0, 0, 7},
951− { DPU_IRQ_TYPE_RESERVED, 0, 0, 7},
952− /* BEGIN MAP_RANGE: 512-575 AD4_0_INTR */
953− /* irq_idx: 512-515 */
954− { DPU_IRQ_TYPE_AD4_BL_DONE, DSPP_0, DPU_INTR_BACKLIGHT_UPDATED, 8},
955− { DPU_IRQ_TYPE_RESERVED, 0, 0, 8},
956− { DPU_IRQ_TYPE_RESERVED, 0, 0, 8},
957− { DPU_IRQ_TYPE_RESERVED, 0, 0, 8},
958− /* irq_idx: 516-519 */
959− { DPU_IRQ_TYPE_RESERVED, 0, 0, 8},
960− { DPU_IRQ_TYPE_RESERVED, 0, 0, 8},
961− { DPU_IRQ_TYPE_RESERVED, 0, 0, 8},
962− { DPU_IRQ_TYPE_RESERVED, 0, 0, 8},
963− /* irq_idx: 520-523 */
964− { DPU_IRQ_TYPE_RESERVED, 0, 0, 8},
965− { DPU_IRQ_TYPE_RESERVED, 0, 0, 8},
966− { DPU_IRQ_TYPE_RESERVED, 0, 0, 8},
967− { DPU_IRQ_TYPE_RESERVED, 0, 0, 8},
968− /* irq_idx: 524-527 */
969− { DPU_IRQ_TYPE_RESERVED, 0, 0, 8},
970− { DPU_IRQ_TYPE_RESERVED, 0, 0, 8},
971− { DPU_IRQ_TYPE_RESERVED, 0, 0, 8},
972− { DPU_IRQ_TYPE_RESERVED, 0, 0, 8},
973− /* irq_idx: 528-531 */
974− { DPU_IRQ_TYPE_RESERVED, 0, 0, 8},
975− { DPU_IRQ_TYPE_RESERVED, 0, 0, 8},
976− { DPU_IRQ_TYPE_RESERVED, 0, 0, 8},
977− { DPU_IRQ_TYPE_RESERVED, 0, 0, 8},
978− /* irq_idx: 532-535 */
979− { DPU_IRQ_TYPE_RESERVED, 0, 0, 8},
980− { DPU_IRQ_TYPE_RESERVED, 0, 0, 8},
981− { DPU_IRQ_TYPE_RESERVED, 0, 0, 8},
982− { DPU_IRQ_TYPE_RESERVED, 0, 0, 8},
983− /* irq_idx: 536-539 */
984− { DPU_IRQ_TYPE_RESERVED, 0, 0, 8},
985− { DPU_IRQ_TYPE_RESERVED, 0, 0, 8},
986− { DPU_IRQ_TYPE_RESERVED, 0, 0, 8},
987− { DPU_IRQ_TYPE_RESERVED, 0, 0, 8},
988− /* irq_idx: 540-543 */
989− { DPU_IRQ_TYPE_RESERVED, 0, 0, 8},
990− { DPU_IRQ_TYPE_RESERVED, 0, 0, 8},
991− { DPU_IRQ_TYPE_RESERVED, 0, 0, 8},
992− { DPU_IRQ_TYPE_RESERVED, 0, 0, 8},
993− /* irq_idx: 544-575*/
994− { DPU_IRQ_TYPE_RESERVED, 0, 0, 8},
995− { DPU_IRQ_TYPE_RESERVED, 0, 0, 8},
996− { DPU_IRQ_TYPE_RESERVED, 0, 0, 8},
997− { DPU_IRQ_TYPE_RESERVED, 0, 0, 8},
998− { DPU_IRQ_TYPE_RESERVED, 0, 0, 8},
999− { DPU_IRQ_TYPE_RESERVED, 0, 0, 8},
1000− { DPU_IRQ_TYPE_RESERVED, 0, 0, 8},
1001− { DPU_IRQ_TYPE_RESERVED, 0, 0, 8},
1002− { DPU_IRQ_TYPE_RESERVED, 0, 0, 8},
1003− { DPU_IRQ_TYPE_RESERVED, 0, 0, 8},
1004− { DPU_IRQ_TYPE_RESERVED, 0, 0, 8},
1005− { DPU_IRQ_TYPE_RESERVED, 0, 0, 8},
1006− { DPU_IRQ_TYPE_RESERVED, 0, 0, 8},
1007− { DPU_IRQ_TYPE_RESERVED, 0, 0, 8},
1008− { DPU_IRQ_TYPE_RESERVED, 0, 0, 8},
1009− { DPU_IRQ_TYPE_RESERVED, 0, 0, 8},
1010− { DPU_IRQ_TYPE_RESERVED, 0, 0, 8},
1011− { DPU_IRQ_TYPE_RESERVED, 0, 0, 8},
1012− { DPU_IRQ_TYPE_RESERVED, 0, 0, 8},
1013− { DPU_IRQ_TYPE_RESERVED, 0, 0, 8},
1014− { DPU_IRQ_TYPE_RESERVED, 0, 0, 8},
1015− { DPU_IRQ_TYPE_RESERVED, 0, 0, 8},
1016− { DPU_IRQ_TYPE_RESERVED, 0, 0, 8},
1017− { DPU_IRQ_TYPE_RESERVED, 0, 0, 8},
1018− { DPU_IRQ_TYPE_RESERVED, 0, 0, 8},
1019− { DPU_IRQ_TYPE_RESERVED, 0, 0, 8},
1020− { DPU_IRQ_TYPE_RESERVED, 0, 0, 8},
1021− { DPU_IRQ_TYPE_RESERVED, 0, 0, 8},
1022− { DPU_IRQ_TYPE_RESERVED, 0, 0, 8},
1023− { DPU_IRQ_TYPE_RESERVED, 0, 0, 8},
1024− { DPU_IRQ_TYPE_RESERVED, 0, 0, 8},
1025− { DPU_IRQ_TYPE_RESERVED, 0, 0, 8},
1026− /* BEGIN MAP_RANGE: 576-639 AD4_1_INTR */
1027− /* irq_idx: 576-579 */
1028− { DPU_IRQ_TYPE_AD4_BL_DONE, DSPP_1, DPU_INTR_BACKLIGHT_UPDATED, 9},
1029− { DPU_IRQ_TYPE_RESERVED, 0, 0, 9},
1030− { DPU_IRQ_TYPE_RESERVED, 0, 0, 9},
1031− { DPU_IRQ_TYPE_RESERVED, 0, 0, 9},
1032− /* irq_idx: 580-583 */
1033− { DPU_IRQ_TYPE_RESERVED, 0, 0, 9},
1034− { DPU_IRQ_TYPE_RESERVED, 0, 0, 9},
1035− { DPU_IRQ_TYPE_RESERVED, 0, 0, 9},
1036− { DPU_IRQ_TYPE_RESERVED, 0, 0, 9},
1037− /* irq_idx: 584-587 */
1038− { DPU_IRQ_TYPE_RESERVED, 0, 0, 9},
1039− { DPU_IRQ_TYPE_RESERVED, 0, 0, 9},
1040− { DPU_IRQ_TYPE_RESERVED, 0, 0, 9},
1041− { DPU_IRQ_TYPE_RESERVED, 0, 0, 9},
1042− /* irq_idx: 588-591 */
1043− { DPU_IRQ_TYPE_RESERVED, 0, 0, 9},
1044− { DPU_IRQ_TYPE_RESERVED, 0, 0, 9},
1045− { DPU_IRQ_TYPE_RESERVED, 0, 0, 9},
1046− { DPU_IRQ_TYPE_RESERVED, 0, 0, 9},
1047− /* irq_idx: 592-595 */
1048− { DPU_IRQ_TYPE_RESERVED, 0, 0, 9},
1049− { DPU_IRQ_TYPE_RESERVED, 0, 0, 9},
1050− { DPU_IRQ_TYPE_RESERVED, 0, 0, 9},
1051− { DPU_IRQ_TYPE_RESERVED, 0, 0, 9},
1052− /* irq_idx: 596-599 */
1053− { DPU_IRQ_TYPE_RESERVED, 0, 0, 9},
1054− { DPU_IRQ_TYPE_RESERVED, 0, 0, 9},
1055− { DPU_IRQ_TYPE_RESERVED, 0, 0, 9},
1056− { DPU_IRQ_TYPE_RESERVED, 0, 0, 9},
1057− /* irq_idx: 600-603 */
1058− { DPU_IRQ_TYPE_RESERVED, 0, 0, 9},
1059− { DPU_IRQ_TYPE_RESERVED, 0, 0, 9},
1060− { DPU_IRQ_TYPE_RESERVED, 0, 0, 9},
1061− { DPU_IRQ_TYPE_RESERVED, 0, 0, 9},
1062− /* irq_idx: 604-607 */
1063− { DPU_IRQ_TYPE_RESERVED, 0, 0, 9},
1064− { DPU_IRQ_TYPE_RESERVED, 0, 0, 9},
1065− { DPU_IRQ_TYPE_RESERVED, 0, 0, 9},
1066− { DPU_IRQ_TYPE_RESERVED, 0, 0, 9},
1067− /* irq_idx: 608-639 */
1068− { DPU_IRQ_TYPE_RESERVED, 0, 0, 9},
1069− { DPU_IRQ_TYPE_RESERVED, 0, 0, 9},
1070− { DPU_IRQ_TYPE_RESERVED, 0, 0, 9},
1071− { DPU_IRQ_TYPE_RESERVED, 0, 0, 9},
1072− { DPU_IRQ_TYPE_RESERVED, 0, 0, 9},
1073− { DPU_IRQ_TYPE_RESERVED, 0, 0, 9},
1074− { DPU_IRQ_TYPE_RESERVED, 0, 0, 9},
1075− { DPU_IRQ_TYPE_RESERVED, 0, 0, 9},
1076− { DPU_IRQ_TYPE_RESERVED, 0, 0, 9},
1077− { DPU_IRQ_TYPE_RESERVED, 0, 0, 9},
1078− { DPU_IRQ_TYPE_RESERVED, 0, 0, 9},
1079− { DPU_IRQ_TYPE_RESERVED, 0, 0, 9},
1080− { DPU_IRQ_TYPE_RESERVED, 0, 0, 9},
1081− { DPU_IRQ_TYPE_RESERVED, 0, 0, 9},
1082− { DPU_IRQ_TYPE_RESERVED, 0, 0, 9},
1083− { DPU_IRQ_TYPE_RESERVED, 0, 0, 9},
1084− { DPU_IRQ_TYPE_RESERVED, 0, 0, 9},
1085− { DPU_IRQ_TYPE_RESERVED, 0, 0, 9},
1086− { DPU_IRQ_TYPE_RESERVED, 0, 0, 9},
1087− { DPU_IRQ_TYPE_RESERVED, 0, 0, 9},
1088− { DPU_IRQ_TYPE_RESERVED, 0, 0, 9},
1089− { DPU_IRQ_TYPE_RESERVED, 0, 0, 9},
1090− { DPU_IRQ_TYPE_RESERVED, 0, 0, 9},
1091− { DPU_IRQ_TYPE_RESERVED, 0, 0, 9},
1092− { DPU_IRQ_TYPE_RESERVED, 0, 0, 9},
1093− { DPU_IRQ_TYPE_RESERVED, 0, 0, 9},
1094− { DPU_IRQ_TYPE_RESERVED, 0, 0, 9},
1095− { DPU_IRQ_TYPE_RESERVED, 0, 0, 9},
1096− { DPU_IRQ_TYPE_RESERVED, 0, 0, 9},
1097− { DPU_IRQ_TYPE_RESERVED, 0, 0, 9},
1098− { DPU_IRQ_TYPE_RESERVED, 0, 0, 9},
1099− { DPU_IRQ_TYPE_RESERVED, 0, 0, 9},
1100− /* BEGIN MAP_RANGE: 640-703 INTF_0_SC7280_INTR */
1101− /* irq_idx: 640-643 */
1102− { DPU_IRQ_TYPE_SFI_VIDEO_IN, INTF_0,
1103− DPU_INTR_VIDEO_INTO_STATIC, 10},
1104− { DPU_IRQ_TYPE_SFI_VIDEO_OUT, INTF_0,
1105− DPU_INTR_VIDEO_OUTOF_STATIC, 10},
1106− { DPU_IRQ_TYPE_SFI_CMD_0_IN, INTF_0,
1107− DPU_INTR_DSICMD_0_INTO_STATIC, 10},
1108− { DPU_IRQ_TYPE_SFI_CMD_0_OUT, INTF_0,
1109− DPU_INTR_DSICMD_0_OUTOF_STATIC, 10},
1110− /* irq_idx: 644-647 */
1111− { DPU_IRQ_TYPE_SFI_CMD_1_IN, INTF_0,
1112− DPU_INTR_DSICMD_1_INTO_STATIC, 10},
1113− { DPU_IRQ_TYPE_SFI_CMD_1_OUT, INTF_0,
1114− DPU_INTR_DSICMD_1_OUTOF_STATIC, 10},
1115− { DPU_IRQ_TYPE_SFI_CMD_2_IN, INTF_0,
1116− DPU_INTR_DSICMD_2_INTO_STATIC, 10},
1117− { DPU_IRQ_TYPE_SFI_CMD_2_OUT, INTF_0,
1118− DPU_INTR_DSICMD_2_OUTOF_STATIC, 10},
1119− /* irq_idx: 648-651 */
1120− { DPU_IRQ_TYPE_PROG_LINE, INTF_0, DPU_INTR_PROG_LINE, 10},
1121− { DPU_IRQ_TYPE_RESERVED, 0, 0, 10},
1122− { DPU_IRQ_TYPE_RESERVED, 0, 0, 10},
1123− { DPU_IRQ_TYPE_RESERVED, 0, 0, 10},
1124− /* irq_idx: 652-655 */
1125− { DPU_IRQ_TYPE_RESERVED, 0, 0, 10},
1126− { DPU_IRQ_TYPE_RESERVED, 0, 0, 10},
1127− { DPU_IRQ_TYPE_RESERVED, 0, 0, 10},
1128− { DPU_IRQ_TYPE_RESERVED, 0, 0, 10},
1129− /* irq_idx: 656-659 */
1130− { DPU_IRQ_TYPE_RESERVED, 0, 0, 10},
1131− { DPU_IRQ_TYPE_RESERVED, 0, 0, 10},
1132− { DPU_IRQ_TYPE_RESERVED, 0, 0, 10},
1133− { DPU_IRQ_TYPE_RESERVED, 0, 0, 10},
1134− /* irq_idx: 660-663 */
1135− { DPU_IRQ_TYPE_RESERVED, 0, 0, 10},
1136− { DPU_IRQ_TYPE_RESERVED, 0, 0, 10},
1137− { DPU_IRQ_TYPE_RESERVED, 0, 0, 10},
1138− { DPU_IRQ_TYPE_RESERVED, 0, 0, 10},
1139− /* irq_idx: 664-667 */
1140− { DPU_IRQ_TYPE_RESERVED, 0, 0, 10},
1141− { DPU_IRQ_TYPE_RESERVED, 0, 0, 10},
1142− { DPU_IRQ_TYPE_RESERVED, 0, 0, 10},
1143− { DPU_IRQ_TYPE_RESERVED, 0, 0, 10},
1144− /* irq_idx: 668-671 */
1145− { DPU_IRQ_TYPE_RESERVED, 0, 0, 10},
1146− { DPU_IRQ_TYPE_RESERVED, 0, 0, 10},
1147− { DPU_IRQ_TYPE_RESERVED, 0, 0, 10},
1148− { DPU_IRQ_TYPE_RESERVED, 0, 0, 10},
1149− /* irq_idx: 672-703 */
1150− { DPU_IRQ_TYPE_RESERVED, 0, 0, 10},
1151− { DPU_IRQ_TYPE_RESERVED, 0, 0, 10},
1152− { DPU_IRQ_TYPE_RESERVED, 0, 0, 10},
1153− { DPU_IRQ_TYPE_RESERVED, 0, 0, 10},
1154− { DPU_IRQ_TYPE_RESERVED, 0, 0, 10},
1155− { DPU_IRQ_TYPE_RESERVED, 0, 0, 10},
1156− { DPU_IRQ_TYPE_RESERVED, 0, 0, 10},
1157− { DPU_IRQ_TYPE_RESERVED, 0, 0, 10},
1158− { DPU_IRQ_TYPE_RESERVED, 0, 0, 10},
1159− { DPU_IRQ_TYPE_RESERVED, 0, 0, 10},
1160− { DPU_IRQ_TYPE_RESERVED, 0, 0, 10},
1161− { DPU_IRQ_TYPE_RESERVED, 0, 0, 10},
1162− { DPU_IRQ_TYPE_RESERVED, 0, 0, 10},
1163− { DPU_IRQ_TYPE_RESERVED, 0, 0, 10},
1164− { DPU_IRQ_TYPE_RESERVED, 0, 0, 10},
1165− { DPU_IRQ_TYPE_RESERVED, 0, 0, 10},
1166− { DPU_IRQ_TYPE_RESERVED, 0, 0, 10},
1167− { DPU_IRQ_TYPE_RESERVED, 0, 0, 10},
1168− { DPU_IRQ_TYPE_RESERVED, 0, 0, 10},
1169− { DPU_IRQ_TYPE_RESERVED, 0, 0, 10},
1170− { DPU_IRQ_TYPE_RESERVED, 0, 0, 10},
1171− { DPU_IRQ_TYPE_RESERVED, 0, 0, 10},
1172− { DPU_IRQ_TYPE_RESERVED, 0, 0, 10},
1173− { DPU_IRQ_TYPE_RESERVED, 0, 0, 10},
1174− { DPU_IRQ_TYPE_RESERVED, 0, 0, 10},
1175− { DPU_IRQ_TYPE_RESERVED, 0, 0, 10},
1176− { DPU_IRQ_TYPE_RESERVED, 0, 0, 10},
1177− { DPU_IRQ_TYPE_RESERVED, 0, 0, 10},
1178− { DPU_IRQ_TYPE_RESERVED, 0, 0, 10},
1179− { DPU_IRQ_TYPE_RESERVED, 0, 0, 10},
1180− { DPU_IRQ_TYPE_RESERVED, 0, 0, 10},
1181− { DPU_IRQ_TYPE_RESERVED, 0, 0, 10},
1182− /* BEGIN MAP_RANGE: 704-767 INTF_1_SC7280_INTR */
1183− /* irq_idx: 704-707 */
1184− { DPU_IRQ_TYPE_SFI_VIDEO_IN, INTF_1,
1185− DPU_INTR_VIDEO_INTO_STATIC, 11},
1186− { DPU_IRQ_TYPE_SFI_VIDEO_OUT, INTF_1,
1187− DPU_INTR_VIDEO_OUTOF_STATIC, 11},
1188− { DPU_IRQ_TYPE_SFI_CMD_0_IN, INTF_1,
1189− DPU_INTR_DSICMD_0_INTO_STATIC, 11},
1190− { DPU_IRQ_TYPE_SFI_CMD_0_OUT, INTF_1,
1191− DPU_INTR_DSICMD_0_OUTOF_STATIC, 11},
1192− /* irq_idx: 708-711 */
1193− { DPU_IRQ_TYPE_SFI_CMD_1_IN, INTF_1,
1194− DPU_INTR_DSICMD_1_INTO_STATIC, 11},
1195− { DPU_IRQ_TYPE_SFI_CMD_1_OUT, INTF_1,
1196− DPU_INTR_DSICMD_1_OUTOF_STATIC, 11},
1197− { DPU_IRQ_TYPE_SFI_CMD_2_IN, INTF_1,
1198− DPU_INTR_DSICMD_2_INTO_STATIC, 11},
1199− { DPU_IRQ_TYPE_SFI_CMD_2_OUT, INTF_1,
1200− DPU_INTR_DSICMD_2_OUTOF_STATIC, 11},
1201− /* irq_idx: 712-715 */
1202− { DPU_IRQ_TYPE_PROG_LINE, INTF_1, DPU_INTR_PROG_LINE, 11},
1203− { DPU_IRQ_TYPE_RESERVED, 0, 0, 11},
1204− { DPU_IRQ_TYPE_RESERVED, 0, 0, 11},
1205− { DPU_IRQ_TYPE_RESERVED, 0, 0, 11},
1206− /* irq_idx: 716-719 */
1207− { DPU_IRQ_TYPE_RESERVED, 0, 0, 11},
1208− { DPU_IRQ_TYPE_RESERVED, 0, 0, 11},
1209− { DPU_IRQ_TYPE_RESERVED, 0, 0, 11},
1210− { DPU_IRQ_TYPE_RESERVED, 0, 0, 11},
1211− /* irq_idx: 720-723 */
1212− { DPU_IRQ_TYPE_RESERVED, 0, 0, 11},
1213− { DPU_IRQ_TYPE_RESERVED, 0, 0, 11},
1214− { DPU_IRQ_TYPE_RESERVED, 0, 0, 11},
1215− { DPU_IRQ_TYPE_RESERVED, 0, 0, 11},
1216− /* irq_idx: 724-727 */
1217− { DPU_IRQ_TYPE_RESERVED, 0, 0, 11},
1218− { DPU_IRQ_TYPE_RESERVED, 0, 0, 11},
1219− { DPU_IRQ_TYPE_RESERVED, 0, 0, 11},
1220− { DPU_IRQ_TYPE_RESERVED, 0, 0, 11},
1221− /* irq_idx: 728-731 */
1222− { DPU_IRQ_TYPE_RESERVED, 0, 0, 11},
1223− { DPU_IRQ_TYPE_RESERVED, 0, 0, 11},
1224− { DPU_IRQ_TYPE_RESERVED, 0, 0, 11},
1225− { DPU_IRQ_TYPE_RESERVED, 0, 0, 11},
1226− /* irq_idx: 732-735 */
1227− { DPU_IRQ_TYPE_RESERVED, 0, 0, 11},
1228− { DPU_IRQ_TYPE_RESERVED, 0, 0, 11},
1229− { DPU_IRQ_TYPE_RESERVED, 0, 0, 11},
1230− { DPU_IRQ_TYPE_RESERVED, 0, 0, 11},
1231− /* irq_idx: 736-767 */
1232− { DPU_IRQ_TYPE_RESERVED, 0, 0, 11},
1233− { DPU_IRQ_TYPE_RESERVED, 0, 0, 11},
1234− { DPU_IRQ_TYPE_RESERVED, 0, 0, 11},
1235− { DPU_IRQ_TYPE_RESERVED, 0, 0, 11},
1236− { DPU_IRQ_TYPE_RESERVED, 0, 0, 11},
1237− { DPU_IRQ_TYPE_RESERVED, 0, 0, 11},
1238− { DPU_IRQ_TYPE_RESERVED, 0, 0, 11},
1239− { DPU_IRQ_TYPE_RESERVED, 0, 0, 11},
1240− { DPU_IRQ_TYPE_RESERVED, 0, 0, 11},
1241− { DPU_IRQ_TYPE_RESERVED, 0, 0, 11},
1242− { DPU_IRQ_TYPE_RESERVED, 0, 0, 11},
1243− { DPU_IRQ_TYPE_RESERVED, 0, 0, 11},
1244− { DPU_IRQ_TYPE_RESERVED, 0, 0, 11},
1245− { DPU_IRQ_TYPE_RESERVED, 0, 0, 11},
1246− { DPU_IRQ_TYPE_RESERVED, 0, 0, 11},
1247− { DPU_IRQ_TYPE_RESERVED, 0, 0, 11},
1248− { DPU_IRQ_TYPE_RESERVED, 0, 0, 11},
1249− { DPU_IRQ_TYPE_RESERVED, 0, 0, 11},
1250− { DPU_IRQ_TYPE_RESERVED, 0, 0, 11},
1251− { DPU_IRQ_TYPE_RESERVED, 0, 0, 11},
1252− { DPU_IRQ_TYPE_RESERVED, 0, 0, 11},
1253− { DPU_IRQ_TYPE_RESERVED, 0, 0, 11},
1254− { DPU_IRQ_TYPE_RESERVED, 0, 0, 11},
1255− { DPU_IRQ_TYPE_RESERVED, 0, 0, 11},
1256− { DPU_IRQ_TYPE_RESERVED, 0, 0, 11},
1257− { DPU_IRQ_TYPE_RESERVED, 0, 0, 11},
1258− { DPU_IRQ_TYPE_RESERVED, 0, 0, 11},
1259− { DPU_IRQ_TYPE_RESERVED, 0, 0, 11},
1260− { DPU_IRQ_TYPE_RESERVED, 0, 0, 11},
1261− { DPU_IRQ_TYPE_RESERVED, 0, 0, 11},
1262− { DPU_IRQ_TYPE_RESERVED, 0, 0, 11},
1263− { DPU_IRQ_TYPE_RESERVED, 0, 0, 11},
1264− /* BEGIN MAP_RANGE: 768-831 INTF_5_SC7280_INTR */
1265− /* irq_idx: 768-771 */
1266− { DPU_IRQ_TYPE_SFI_VIDEO_IN, INTF_5,
1267− DPU_INTR_VIDEO_INTO_STATIC, 12},
1268− { DPU_IRQ_TYPE_SFI_VIDEO_OUT, INTF_5,
1269− DPU_INTR_VIDEO_OUTOF_STATIC, 12},
1270− { DPU_IRQ_TYPE_SFI_CMD_0_IN, INTF_5,
1271− DPU_INTR_DSICMD_0_INTO_STATIC, 12},
1272− { DPU_IRQ_TYPE_SFI_CMD_0_OUT, INTF_5,
1273− DPU_INTR_DSICMD_0_OUTOF_STATIC, 12},
1274− /* irq_idx: 772-775 */
1275− { DPU_IRQ_TYPE_SFI_CMD_1_IN, INTF_5,
1276− DPU_INTR_DSICMD_1_INTO_STATIC, 12},
1277− { DPU_IRQ_TYPE_SFI_CMD_1_OUT, INTF_5,
1278− DPU_INTR_DSICMD_1_OUTOF_STATIC, 12},
1279− { DPU_IRQ_TYPE_SFI_CMD_2_IN, INTF_5,
1280− DPU_INTR_DSICMD_2_INTO_STATIC, 12},
1281− { DPU_IRQ_TYPE_SFI_CMD_2_OUT, INTF_5,
1282− DPU_INTR_DSICMD_2_OUTOF_STATIC, 12},
1283− /* irq_idx: 776-779 */
1284− { DPU_IRQ_TYPE_PROG_LINE, INTF_5, DPU_INTR_PROG_LINE, 12},
1285− { DPU_IRQ_TYPE_RESERVED, 0, 0, 12},
1286− { DPU_IRQ_TYPE_RESERVED, 0, 0, 12},
1287− { DPU_IRQ_TYPE_RESERVED, 0, 0, 12},
1288− /* irq_idx: 780-783 */
1289− { DPU_IRQ_TYPE_RESERVED, 0, 0, 12},
1290− { DPU_IRQ_TYPE_RESERVED, 0, 0, 12},
1291− { DPU_IRQ_TYPE_RESERVED, 0, 0, 12},
1292− { DPU_IRQ_TYPE_RESERVED, 0, 0, 12},
1293− /* irq_idx: 784-787 */
1294− { DPU_IRQ_TYPE_RESERVED, 0, 0, 12},
1295− { DPU_IRQ_TYPE_RESERVED, 0, 0, 12},
1296− { DPU_IRQ_TYPE_RESERVED, 0, 0, 12},
1297− { DPU_IRQ_TYPE_RESERVED, 0, 0, 12},
1298− /* irq_idx: 788-791 */
1299− { DPU_IRQ_TYPE_RESERVED, 0, 0, 12},
1300− { DPU_IRQ_TYPE_RESERVED, 0, 0, 12},
1301− { DPU_IRQ_TYPE_RESERVED, 0, 0, 12},
1302− { DPU_IRQ_TYPE_RESERVED, 0, 0, 12},
1303− /* irq_idx: 792-795 */
1304− { DPU_IRQ_TYPE_RESERVED, 0, 0, 12},
1305− { DPU_IRQ_TYPE_RESERVED, 0, 0, 12},
1306− { DPU_IRQ_TYPE_RESERVED, 0, 0, 12},
1307− { DPU_IRQ_TYPE_RESERVED, 0, 0, 12},
1308− /* irq_idx: 796-799 */
1309− { DPU_IRQ_TYPE_RESERVED, 0, 0, 12},
1310− { DPU_IRQ_TYPE_RESERVED, 0, 0, 12},
1311− { DPU_IRQ_TYPE_RESERVED, 0, 0, 12},
1312− { DPU_IRQ_TYPE_RESERVED, 0, 0, 12},
1313− /* irq_idx: 800-831 */
1314− { DPU_IRQ_TYPE_RESERVED, 0, 0, 12},
1315− { DPU_IRQ_TYPE_RESERVED, 0, 0, 12},
1316− { DPU_IRQ_TYPE_RESERVED, 0, 0, 12},
1317− { DPU_IRQ_TYPE_RESERVED, 0, 0, 12},
1318− { DPU_IRQ_TYPE_RESERVED, 0, 0, 12},
1319− { DPU_IRQ_TYPE_RESERVED, 0, 0, 12},
1320− { DPU_IRQ_TYPE_RESERVED, 0, 0, 12},
1321− { DPU_IRQ_TYPE_RESERVED, 0, 0, 12},
1322− { DPU_IRQ_TYPE_RESERVED, 0, 0, 12},
1323− { DPU_IRQ_TYPE_RESERVED, 0, 0, 12},
1324− { DPU_IRQ_TYPE_RESERVED, 0, 0, 12},
1325− { DPU_IRQ_TYPE_RESERVED, 0, 0, 12},
1326− { DPU_IRQ_TYPE_RESERVED, 0, 0, 12},
1327− { DPU_IRQ_TYPE_RESERVED, 0, 0, 12},
1328− { DPU_IRQ_TYPE_RESERVED, 0, 0, 12},
1329− { DPU_IRQ_TYPE_RESERVED, 0, 0, 12},
1330− { DPU_IRQ_TYPE_RESERVED, 0, 0, 12},
1331− { DPU_IRQ_TYPE_RESERVED, 0, 0, 12},
1332− { DPU_IRQ_TYPE_RESERVED, 0, 0, 12},
1333− { DPU_IRQ_TYPE_RESERVED, 0, 0, 12},
1334− { DPU_IRQ_TYPE_RESERVED, 0, 0, 12},
1335− { DPU_IRQ_TYPE_RESERVED, 0, 0, 12},
1336− { DPU_IRQ_TYPE_RESERVED, 0, 0, 12},
1337− { DPU_IRQ_TYPE_RESERVED, 0, 0, 12},
1338− { DPU_IRQ_TYPE_RESERVED, 0, 0, 12},
1339− { DPU_IRQ_TYPE_RESERVED, 0, 0, 12},
1340− { DPU_IRQ_TYPE_RESERVED, 0, 0, 12},
1341− { DPU_IRQ_TYPE_RESERVED, 0, 0, 12},
1342− { DPU_IRQ_TYPE_RESERVED, 0, 0, 12},
1343− { DPU_IRQ_TYPE_RESERVED, 0, 0, 12},
1344− { DPU_IRQ_TYPE_RESERVED, 0, 0, 12},
1345− { DPU_IRQ_TYPE_RESERVED, 0, 0, 12},
1346−};
117+#define DPU_IRQ_REG(irq_idx) (irq_idx / 32)
118+#define DPU_IRQ_MASK(irq_idx) (BIT(irq_idx % 32))
1347119
1348−static int dpu_hw_intr_irqidx_lookup(struct dpu_hw_intr *intr,
1349− enum dpu_intr_type intr_type, u32 instance_idx)
120+static void dpu_hw_intr_clear_intr_status_nolock(struct dpu_hw_intr *intr,
121+ int irq_idx)
1350122 {
1351− int i;
123+ int reg_idx;
1352124
1353− for (i = 0; i < ARRAY_SIZE(dpu_irq_map); i++) {
1354− if (intr_type == dpu_irq_map[i].intr_type &&
1355− instance_idx == dpu_irq_map[i].instance_idx &&
1356− !(intr->obsolete_irq & BIT(dpu_irq_map[i].intr_type)))
1357− return i;
1358− }
125+ if (!intr)
126+ return;
1359127
1360− pr_debug("IRQ lookup fail!! intr_type=%d, instance_idx=%d\n",
1361− intr_type, instance_idx);
1362− return -EINVAL;
128+ reg_idx = DPU_IRQ_REG(irq_idx);
129+ DPU_REG_WRITE(&intr->hw, dpu_intr_set[reg_idx].clr_off, DPU_IRQ_MASK(irq_idx));
130+
131+ /* ensure register writes go through */
132+ wmb();
1363133 }
1364134
1365135 static void dpu_hw_intr_dispatch_irq(struct dpu_hw_intr *intr,
@@ -1368,9 +138,9 @@ static void dpu_hw_intr_dispatch_irq(struct dpu_hw_intr *intr, · 2 unmodified lines
1368138 {
1369139 int reg_idx;
1370140 int irq_idx;
1371− int start_idx;
1372− int end_idx;
1373141 u32 irq_status;
142+ u32 enable_mask;
143+ int bit;
1374144 unsigned long irq_flags;
1375145
1376146 if (!intr)
@@ -1383,86 +153,92 @@ static void dpu_hw_intr_dispatch_irq(struct dpu_hw_intr *intr, · 6 unmodified lines
1383153 */
1384154 spin_lock_irqsave(&intr->irq_lock, irq_flags);
1385155 for (reg_idx = 0; reg_idx < ARRAY_SIZE(dpu_intr_set); reg_idx++) {
1386− irq_status = intr->save_irq_status[reg_idx];
156+ if (!test_bit(reg_idx, &intr->irq_mask))
157+ continue;
1387158
1388− /*
1389− * Each Interrupt register has a range of 64 indexes, and
1390− * that is static for dpu_irq_map.
1391− */
1392− start_idx = reg_idx * 64;
1393− end_idx = start_idx + 64;
159+ /* Read interrupt status */
160+ irq_status = DPU_REG_READ(&intr->hw, dpu_intr_set[reg_idx].status_off);
161+
162+ /* Read enable mask */
163+ enable_mask = DPU_REG_READ(&intr->hw, dpu_intr_set[reg_idx].en_off);
164+
165+ /* and clear the interrupt */
166+ if (irq_status)
167+ DPU_REG_WRITE(&intr->hw, dpu_intr_set[reg_idx].clr_off,
168+ irq_status);
1394169
1395− if (!test_bit(reg_idx, &intr->irq_mask) ||
1396− start_idx >= ARRAY_SIZE(dpu_irq_map))
170+ /* Finally update IRQ status based on enable mask */
171+ irq_status &= enable_mask;
172+
173+ if (!irq_status)
1397174 continue;
1398175
1399176 /*
1400− * Search through matching intr status from irq map.
1401− * start_idx and end_idx defined the search range in
1402− * the dpu_irq_map.
177+ * Search through matching intr status.
1403178 */
1404− for (irq_idx = start_idx;
1405− (irq_idx < end_idx) && irq_status;
1406− irq_idx++)
1407− if ((irq_status & dpu_irq_map[irq_idx].irq_mask) &&
1408− (dpu_irq_map[irq_idx].reg_idx == reg_idx) &&
1409− !(intr->obsolete_irq &
1410− BIT(dpu_irq_map[irq_idx].intr_type))) {
1411− /*
1412− * Once a match on irq mask, perform a callback
1413− * to the given cbfunc. cbfunc will take care
1414− * the interrupt status clearing. If cbfunc is
1415− * not provided, then the interrupt clearing
1416− * is here.
1417− */
1418− if (cbfunc)
1419− cbfunc(arg, irq_idx);
1420− else
1421− intr->ops.clear_intr_status_nolock(
1422− intr, irq_idx);
1423−
1424− /*
1425− * When callback finish, clear the irq_status
1426− * with the matching mask. Once irq_status
1427− * is all cleared, the search can be stopped.
1428− */
1429− irq_status &= ~dpu_irq_map[irq_idx].irq_mask;
1430− }
179+ while ((bit = ffs(irq_status)) != 0) {
180+ irq_idx = DPU_IRQ_IDX(reg_idx, bit - 1);
181+ /*
182+ * Once a match on irq mask, perform a callback
183+ * to the given cbfunc. cbfunc will take care
184+ * the interrupt status clearing. If cbfunc is
185+ * not provided, then the interrupt clearing
186+ * is here.
187+ */
188+ if (cbfunc)
189+ cbfunc(arg, irq_idx);
190+
191+ dpu_hw_intr_clear_intr_status_nolock(intr, irq_idx);
192+
193+ /*
194+ * When callback finish, clear the irq_status
195+ * with the matching mask. Once irq_status
196+ * is all cleared, the search can be stopped.
197+ */
198+ irq_status &= ~BIT(bit - 1);
199+ }
1431200 }
201+
202+ /* ensure register writes go through */
203+ wmb();
204+
1432205 spin_unlock_irqrestore(&intr->irq_lock, irq_flags);
1433206 }
1434207
1435−static int dpu_hw_intr_enable_irq(struct dpu_hw_intr *intr, int irq_idx)
208+static int dpu_hw_intr_enable_irq_locked(struct dpu_hw_intr *intr, int irq_idx)
1436209 {
1437210 int reg_idx;
1438− unsigned long irq_flags;
1439211 const struct dpu_intr_reg *reg;
1440− const struct dpu_irq_type *irq;
1441212 const char *dbgstr = NULL;
1442213 uint32_t cache_irq_mask;
1443214
1444215 if (!intr)
1445216 return -EINVAL;
1446217
1447− if (irq_idx < 0 || irq_idx >= ARRAY_SIZE(dpu_irq_map)) {
218+ if (irq_idx < 0 || irq_idx >= intr->total_irqs) {
1448219 pr_err("invalid IRQ index: [%d]\n", irq_idx);
1449220 return -EINVAL;
1450221 }
1451222
1452− irq = &dpu_irq_map[irq_idx];
1453− reg_idx = irq->reg_idx;
223+ /*
224+ * The cache_irq_mask and hardware RMW operations needs to be done
225+ * under irq_lock and it's the caller's responsibility to ensure that's
226+ * held.
227+ */
228+ assert_spin_locked(&intr->irq_lock);
229+
230+ reg_idx = DPU_IRQ_REG(irq_idx);
1454231 reg = &dpu_intr_set[reg_idx];
1455232
1456− spin_lock_irqsave(&intr->irq_lock, irq_flags);
1457233 cache_irq_mask = intr->cache_irq_mask[reg_idx];
1458− if (cache_irq_mask & irq->irq_mask) {
234+ if (cache_irq_mask & DPU_IRQ_MASK(irq_idx)) {
1459235 dbgstr = "DPU IRQ already set:";
1460236 } else {
1461237 dbgstr = "DPU IRQ enabled:";
1462238
1463− cache_irq_mask |= irq->irq_mask;
239+ cache_irq_mask |= DPU_IRQ_MASK(irq_idx);
1464240 /* Cleaning any pending interrupt */
1465− DPU_REG_WRITE(&intr->hw, reg->clr_off, irq->irq_mask);
241+ DPU_REG_WRITE(&intr->hw, reg->clr_off, DPU_IRQ_MASK(irq_idx));
1466242 /* Enabling interrupts with the new mask */
1467243 DPU_REG_WRITE(&intr->hw, reg->en_off, cache_irq_mask);
1468244
@@ -1471,45 +247,49 @@ static int dpu_hw_intr_enable_irq(struct dpu_hw_intr *intr, int irq_idx) · 2 unmodified lines
1471247
1472248 intr->cache_irq_mask[reg_idx] = cache_irq_mask;
1473249 }
1474− spin_unlock_irqrestore(&intr->irq_lock, irq_flags);
1475250
1476− pr_debug("%s MASK:0x%.8x, CACHE-MASK:0x%.8x\n", dbgstr,
1477− irq->irq_mask, cache_irq_mask);
251+ pr_debug("%s MASK:0x%.8lx, CACHE-MASK:0x%.8x\n", dbgstr,
252+ DPU_IRQ_MASK(irq_idx), cache_irq_mask);
1478253
1479254 return 0;
1480255 }
1481256
1482−static int dpu_hw_intr_disable_irq_nolock(struct dpu_hw_intr *intr, int irq_idx)
257+static int dpu_hw_intr_disable_irq_locked(struct dpu_hw_intr *intr, int irq_idx)
1483258 {
1484259 int reg_idx;
1485260 const struct dpu_intr_reg *reg;
1486− const struct dpu_irq_type *irq;
1487261 const char *dbgstr = NULL;
1488262 uint32_t cache_irq_mask;
1489263
1490264 if (!intr)
1491265 return -EINVAL;
1492266
1493− if (irq_idx < 0 || irq_idx >= ARRAY_SIZE(dpu_irq_map)) {
267+ if (irq_idx < 0 || irq_idx >= intr->total_irqs) {
1494268 pr_err("invalid IRQ index: [%d]\n", irq_idx);
1495269 return -EINVAL;
1496270 }
1497271
1498− irq = &dpu_irq_map[irq_idx];
1499− reg_idx = irq->reg_idx;
272+ /*
273+ * The cache_irq_mask and hardware RMW operations needs to be done
274+ * under irq_lock and it's the caller's responsibility to ensure that's
275+ * held.
276+ */
277+ assert_spin_locked(&intr->irq_lock);
278+
279+ reg_idx = DPU_IRQ_REG(irq_idx);
1500280 reg = &dpu_intr_set[reg_idx];
1501281
1502282 cache_irq_mask = intr->cache_irq_mask[reg_idx];
1503− if ((cache_irq_mask & irq->irq_mask) == 0) {
283+ if ((cache_irq_mask & DPU_IRQ_MASK(irq_idx)) == 0) {
1504284 dbgstr = "DPU IRQ is already cleared:";
1505285 } else {
1506286 dbgstr = "DPU IRQ mask disable:";
1507287
1508− cache_irq_mask &= ~irq->irq_mask;
288+ cache_irq_mask &= ~DPU_IRQ_MASK(irq_idx);
1509289 /* Disable interrupts based on the new mask */
1510290 DPU_REG_WRITE(&intr->hw, reg->en_off, cache_irq_mask);
1511291 /* Cleaning any pending interrupt */
1512− DPU_REG_WRITE(&intr->hw, reg->clr_off, irq->irq_mask);
292+ DPU_REG_WRITE(&intr->hw, reg->clr_off, DPU_IRQ_MASK(irq_idx));
1513293
1514294 /* ensure register write goes through */
1515295 wmb();
@@ -1517,27 +297,8 @@ static int dpu_hw_intr_disable_irq_nolock(struct dpu_hw_intr *intr, int irq_idx) · 1 unmodified line
1517297 intr->cache_irq_mask[reg_idx] = cache_irq_mask;
1518298 }
1519299
1520− pr_debug("%s MASK:0x%.8x, CACHE-MASK:0x%.8x\n", dbgstr,
1521− irq->irq_mask, cache_irq_mask);
1522−
1523− return 0;
1524−}
1525−
1526−static int dpu_hw_intr_disable_irq(struct dpu_hw_intr *intr, int irq_idx)
1527−{
1528− unsigned long irq_flags;
1529−
1530− if (!intr)
1531− return -EINVAL;
1532−
1533− if (irq_idx < 0 || irq_idx >= ARRAY_SIZE(dpu_irq_map)) {
1534− pr_err("invalid IRQ index: [%d]\n", irq_idx);
1535− return -EINVAL;
1536− }
1537−
1538− spin_lock_irqsave(&intr->irq_lock, irq_flags);
1539− dpu_hw_intr_disable_irq_nolock(intr, irq_idx);
1540− spin_unlock_irqrestore(&intr->irq_lock, irq_flags);
300+ pr_debug("%s MASK:0x%.8lx, CACHE-MASK:0x%.8x\n", dbgstr,
301+ DPU_IRQ_MASK(irq_idx), cache_irq_mask);
1541302
1542303 return 0;
1543304 }
@@ -1580,58 +341,6 @@ static int dpu_hw_intr_disable_irqs(struct dpu_hw_intr *intr) · 36 unmodified lines
1580341 return 0;
1581342 }
1582343
1583−static void dpu_hw_intr_get_interrupt_statuses(struct dpu_hw_intr *intr)
1584−{
1585− int i;
1586− u32 enable_mask;
1587− unsigned long irq_flags;
1588−
1589− if (!intr)
1590− return;
1591−
1592− spin_lock_irqsave(&intr->irq_lock, irq_flags);
1593− for (i = 0; i < ARRAY_SIZE(dpu_intr_set); i++) {
1594− if (!test_bit(i, &intr->irq_mask))
1595− continue;
1596−
1597− /* Read interrupt status */
1598− intr->save_irq_status[i] = DPU_REG_READ(&intr->hw,
1599− dpu_intr_set[i].status_off);
1600−
1601− /* Read enable mask */
1602− enable_mask = DPU_REG_READ(&intr->hw, dpu_intr_set[i].en_off);
1603−
1604− /* and clear the interrupt */
1605− if (intr->save_irq_status[i])
1606− DPU_REG_WRITE(&intr->hw, dpu_intr_set[i].clr_off,
1607− intr->save_irq_status[i]);
1608−
1609− /* Finally update IRQ status based on enable mask */
1610− intr->save_irq_status[i] &= enable_mask;
1611− }
1612−
1613− /* ensure register writes go through */
1614− wmb();
1615−
1616− spin_unlock_irqrestore(&intr->irq_lock, irq_flags);
1617−}
1618−
1619−static void dpu_hw_intr_clear_intr_status_nolock(struct dpu_hw_intr *intr,
1620− int irq_idx)
1621−{
1622− int reg_idx;
1623−
1624− if (!intr)
1625− return;
1626−
1627− reg_idx = dpu_irq_map[irq_idx].reg_idx;
1628− DPU_REG_WRITE(&intr->hw, dpu_intr_set[reg_idx].clr_off,
1629− dpu_irq_map[irq_idx].irq_mask);
1630−
1631− /* ensure register writes go through */
1632− wmb();
1633−}
1634−
1635344 static u32 dpu_hw_intr_get_interrupt_status(struct dpu_hw_intr *intr,
1636345 int irq_idx, bool clear)
1637346 {
@@ -1642,17 +351,17 @@ static u32 dpu_hw_intr_get_interrupt_status(struct dpu_hw_intr *intr, · 4 unmodified lines
1642351 if (!intr)
1643352 return 0;
1644353
1645− if (irq_idx >= ARRAY_SIZE(dpu_irq_map) || irq_idx < 0) {
354+ if (irq_idx < 0 || irq_idx >= intr->total_irqs) {
1646355 pr_err("invalid IRQ index: [%d]\n", irq_idx);
1647356 return 0;
1648357 }
1649358
1650359 spin_lock_irqsave(&intr->irq_lock, irq_flags);
1651360
1652− reg_idx = dpu_irq_map[irq_idx].reg_idx;
361+ reg_idx = DPU_IRQ_REG(irq_idx);
1653362 intr_status = DPU_REG_READ(&intr->hw,
1654363 dpu_intr_set[reg_idx].status_off) &
1655− dpu_irq_map[irq_idx].irq_mask;
364+ DPU_IRQ_MASK(irq_idx);
1656365 if (intr_status && clear)
1657366 DPU_REG_WRITE(&intr->hw, dpu_intr_set[reg_idx].clr_off,
1658367 intr_status);
@@ -1665,17 +374,30 @@ static u32 dpu_hw_intr_get_interrupt_status(struct dpu_hw_intr *intr, · 6 unmodified lines
1665374 return intr_status;
1666375 }
1667376
377+static unsigned long dpu_hw_intr_lock(struct dpu_hw_intr *intr)
378+{
379+ unsigned long irq_flags;
380+
381+ spin_lock_irqsave(&intr->irq_lock, irq_flags);
382+
383+ return irq_flags;
384+}
385+
386+static void dpu_hw_intr_unlock(struct dpu_hw_intr *intr, unsigned long irq_flags)
387+{
388+ spin_unlock_irqrestore(&intr->irq_lock, irq_flags);
389+}
390+
1668391 static void __setup_intr_ops(struct dpu_hw_intr_ops *ops)
1669392 {
1670− ops->irq_idx_lookup = dpu_hw_intr_irqidx_lookup;
1671− ops->enable_irq = dpu_hw_intr_enable_irq;
1672− ops->disable_irq = dpu_hw_intr_disable_irq;
393+ ops->enable_irq_locked = dpu_hw_intr_enable_irq_locked;
394+ ops->disable_irq_locked = dpu_hw_intr_disable_irq_locked;
1673395 ops->dispatch_irqs = dpu_hw_intr_dispatch_irq;
1674396 ops->clear_all_irqs = dpu_hw_intr_clear_irqs;
1675397 ops->disable_all_irqs = dpu_hw_intr_disable_irqs;
1676− ops->get_interrupt_statuses = dpu_hw_intr_get_interrupt_statuses;
1677− ops->clear_intr_status_nolock = dpu_hw_intr_clear_intr_status_nolock;
1678398 ops->get_interrupt_status = dpu_hw_intr_get_interrupt_status;
399+ ops->lock = dpu_hw_intr_lock;
400+ ops->unlock = dpu_hw_intr_unlock;
1679401 }
1680402
1681403 static void __intr_offset(struct dpu_mdss_cfg *m,
@@ -1701,7 +423,7 @@ struct dpu_hw_intr *dpu_hw_intr_init(void __iomem *addr, · 19 unmodified lines
1701423 __intr_offset(m, addr, &intr->hw);
1702424 __setup_intr_ops(&intr->ops);
1703425
1704− intr->irq_idx_tbl_size = ARRAY_SIZE(dpu_irq_map);
426+ intr->total_irqs = ARRAY_SIZE(dpu_intr_set) * 32;
1705427
1706428 intr->cache_irq_mask = kcalloc(ARRAY_SIZE(dpu_intr_set), sizeof(u32),
1707429 GFP_KERNEL);
@@ -1710,16 +432,7 @@ struct dpu_hw_intr *dpu_hw_intr_init(void __iomem *addr, · 2 unmodified lines
1710432 return ERR_PTR(-ENOMEM);
1711433 }
1712434
1713− intr->save_irq_status = kcalloc(ARRAY_SIZE(dpu_intr_set), sizeof(u32),
1714− GFP_KERNEL);
1715− if (intr->save_irq_status == NULL) {
1716− kfree(intr->cache_irq_mask);
1717− kfree(intr);
1718− return ERR_PTR(-ENOMEM);
1719− }
1720−
1721435 intr->irq_mask = m->mdss_irqs;
1722− intr->obsolete_irq = m->obsolete_irq;
1723436
1724437 spin_lock_init(&intr->irq_lock);
1725438
@@ -1730,7 +443,6 @@ void dpu_hw_intr_destroy(struct dpu_hw_intr *intr) · 4 unmodified lines
1730443 {
1731444 if (intr) {
1732445 kfree(intr->cache_irq_mask);
1733− kfree(intr->save_irq_status);
1734446 kfree(intr);
1735447 }
1736448 }
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h+38−94
@@ -12,85 +12,32 @@ · 11 unmodified lines
1212 #include "dpu_hw_util.h"
1313 #include "dpu_hw_mdss.h"
1414
15−/**
16− * dpu_intr_type - HW Interrupt Type
17− * @DPU_IRQ_TYPE_WB_ROT_COMP: WB rotator done
18− * @DPU_IRQ_TYPE_WB_WFD_COMP: WB WFD done
19− * @DPU_IRQ_TYPE_PING_PONG_COMP: PingPong done
20− * @DPU_IRQ_TYPE_PING_PONG_RD_PTR: PingPong read pointer
21− * @DPU_IRQ_TYPE_PING_PONG_WR_PTR: PingPong write pointer
22− * @DPU_IRQ_TYPE_PING_PONG_AUTO_REF: PingPong auto refresh
23− * @DPU_IRQ_TYPE_PING_PONG_TEAR_CHECK: PingPong Tear check
24− * @DPU_IRQ_TYPE_PING_PONG_TE_CHECK: PingPong TE detection
25− * @DPU_IRQ_TYPE_INTF_UNDER_RUN: INTF underrun
26− * @DPU_IRQ_TYPE_INTF_VSYNC: INTF VSYNC
27− * @DPU_IRQ_TYPE_CWB_OVERFLOW: Concurrent WB overflow
28− * @DPU_IRQ_TYPE_HIST_VIG_DONE: VIG Histogram done
29− * @DPU_IRQ_TYPE_HIST_VIG_RSTSEQ: VIG Histogram reset
30− * @DPU_IRQ_TYPE_HIST_DSPP_DONE: DSPP Histogram done
31− * @DPU_IRQ_TYPE_HIST_DSPP_RSTSEQ: DSPP Histogram reset
32− * @DPU_IRQ_TYPE_WD_TIMER: Watchdog timer
33− * @DPU_IRQ_TYPE_SFI_VIDEO_IN: Video static frame INTR into static
34− * @DPU_IRQ_TYPE_SFI_VIDEO_OUT: Video static frame INTR out-of static
35− * @DPU_IRQ_TYPE_SFI_CMD_0_IN: DSI CMD0 static frame INTR into static
36− * @DPU_IRQ_TYPE_SFI_CMD_0_OUT: DSI CMD0 static frame INTR out-of static
37− * @DPU_IRQ_TYPE_SFI_CMD_1_IN: DSI CMD1 static frame INTR into static
38− * @DPU_IRQ_TYPE_SFI_CMD_1_OUT: DSI CMD1 static frame INTR out-of static
39− * @DPU_IRQ_TYPE_SFI_CMD_2_IN: DSI CMD2 static frame INTR into static
40− * @DPU_IRQ_TYPE_SFI_CMD_2_OUT: DSI CMD2 static frame INTR out-of static
41− * @DPU_IRQ_TYPE_PROG_LINE: Programmable Line interrupt
42− * @DPU_IRQ_TYPE_AD4_BL_DONE: AD4 backlight
43− * @DPU_IRQ_TYPE_CTL_START: Control start
44− * @DPU_IRQ_TYPE_RESERVED: Reserved for expansion
45− */
46−enum dpu_intr_type {
47− DPU_IRQ_TYPE_WB_ROT_COMP,
48− DPU_IRQ_TYPE_WB_WFD_COMP,
49− DPU_IRQ_TYPE_PING_PONG_COMP,
50− DPU_IRQ_TYPE_PING_PONG_RD_PTR,
51− DPU_IRQ_TYPE_PING_PONG_WR_PTR,
52− DPU_IRQ_TYPE_PING_PONG_AUTO_REF,
53− DPU_IRQ_TYPE_PING_PONG_TEAR_CHECK,
54− DPU_IRQ_TYPE_PING_PONG_TE_CHECK,
55− DPU_IRQ_TYPE_INTF_UNDER_RUN,
56− DPU_IRQ_TYPE_INTF_VSYNC,
57− DPU_IRQ_TYPE_CWB_OVERFLOW,
58− DPU_IRQ_TYPE_HIST_VIG_DONE,
59− DPU_IRQ_TYPE_HIST_VIG_RSTSEQ,
60− DPU_IRQ_TYPE_HIST_DSPP_DONE,
61− DPU_IRQ_TYPE_HIST_DSPP_RSTSEQ,
62− DPU_IRQ_TYPE_WD_TIMER,
63− DPU_IRQ_TYPE_SFI_VIDEO_IN,
64− DPU_IRQ_TYPE_SFI_VIDEO_OUT,
65− DPU_IRQ_TYPE_SFI_CMD_0_IN,
66− DPU_IRQ_TYPE_SFI_CMD_0_OUT,
67− DPU_IRQ_TYPE_SFI_CMD_1_IN,
68− DPU_IRQ_TYPE_SFI_CMD_1_OUT,
69− DPU_IRQ_TYPE_SFI_CMD_2_IN,
70− DPU_IRQ_TYPE_SFI_CMD_2_OUT,
71− DPU_IRQ_TYPE_PROG_LINE,
72− DPU_IRQ_TYPE_AD4_BL_DONE,
73− DPU_IRQ_TYPE_CTL_START,
74− DPU_IRQ_TYPE_RESERVED,
15+/* When making changes be sure to sync with dpu_intr_set */
16+enum dpu_hw_intr_reg {
17+ MDP_SSPP_TOP0_INTR,
18+ MDP_SSPP_TOP0_INTR2,
19+ MDP_SSPP_TOP0_HIST_INTR,
20+ MDP_INTF0_INTR,
21+ MDP_INTF1_INTR,
22+ MDP_INTF2_INTR,
23+ MDP_INTF3_INTR,
24+ MDP_INTF4_INTR,
25+ MDP_AD4_0_INTR,
26+ MDP_AD4_1_INTR,
27+ MDP_INTF0_7xxx_INTR,
28+ MDP_INTF1_7xxx_INTR,
29+ MDP_INTF5_7xxx_INTR,
30+ MDP_INTR_MAX,
7531 };
7632
33+#define DPU_IRQ_IDX(reg_idx, offset) (reg_idx * 32 + offset)
34+
7735 struct dpu_hw_intr;
7836
7937 /**
8038 * Interrupt operations.
8139 */
8240 struct dpu_hw_intr_ops {
83− /**
84− * irq_idx_lookup - Lookup IRQ index on the HW interrupt type
85− * Used for all irq related ops
86− * @intr: HW interrupt handle
87− * @intr_type: Interrupt type defined in dpu_intr_type
88− * @instance_idx: HW interrupt block instance
89− * @return: irq_idx or -EINVAL for lookup fail
90− */
91− int (*irq_idx_lookup)(struct dpu_hw_intr *intr,
92− enum dpu_intr_type intr_type,
93− u32 instance_idx);
9441
9542 /**
9643 * enable_irq - Enable IRQ based on lookup IRQ index
@@ -98,7 +45,7 @@ struct dpu_hw_intr_ops { · 1 unmodified line
9845 * @irq_idx: Lookup irq index return from irq_idx_lookup
9946 * @return: 0 for success, otherwise failure
10047 */
101− int (*enable_irq)(
48+ int (*enable_irq_locked)(
10249 struct dpu_hw_intr *intr,
10350 int irq_idx);
10451
@@ -108,7 +55,7 @@ struct dpu_hw_intr_ops { · 3 unmodified lines
10855 * @irq_idx: Lookup irq index return from irq_idx_lookup
10956 * @return: 0 for success, otherwise failure
11057 */
111− int (*disable_irq)(
58+ int (*disable_irq_locked)(
11259 struct dpu_hw_intr *intr,
11360 int irq_idx);
11461
@@ -142,23 +89,6 @@ struct dpu_hw_intr_ops { · 27 unmodified lines
14289 void (*cbfunc)(void *arg, int irq_idx),
14390 void *arg);
14491
145− /**
146− * get_interrupt_statuses - Gets and store value from all interrupt
147− * status registers that are currently fired.
148− * @intr: HW interrupt handle
149− */
150− void (*get_interrupt_statuses)(
151− struct dpu_hw_intr *intr);
152−
153− /**
154− * clear_intr_status_nolock() - clears the HW interrupts without lock
155− * @intr: HW interrupt handle
156− * @irq_idx: Lookup irq index return from irq_idx_lookup
157− */
158− void (*clear_intr_status_nolock)(
159− struct dpu_hw_intr *intr,
160− int irq_idx);
161−
16292 /**
16393 * get_interrupt_status - Gets HW interrupt status, and clear if set,
16494 * based on given lookup IRQ index.
@@ -170,6 +100,22 @@ struct dpu_hw_intr_ops { · 5 unmodified lines
170100 struct dpu_hw_intr *intr,
171101 int irq_idx,
172102 bool clear);
103+
104+ /**
105+ * lock - take the IRQ lock
106+ * @intr: HW interrupt handle
107+ * @return: irq_flags for the taken spinlock
108+ */
109+ unsigned long (*lock)(
110+ struct dpu_hw_intr *intr);
111+
112+ /**
113+ * unlock - take the IRQ lock
114+ * @intr: HW interrupt handle
115+ * @irq_flags: the irq_flags returned from lock
116+ */
117+ void (*unlock)(
118+ struct dpu_hw_intr *intr, unsigned long irq_flags);
173119 };
174120
175121 /**
@@ -178,19 +124,17 @@ struct dpu_hw_intr_ops { · 2 unmodified lines
178124 * @ops: function pointer mapping for IRQ handling
179125 * @cache_irq_mask: array of IRQ enable masks reg storage created during init
180126 * @save_irq_status: array of IRQ status reg storage created during init
181− * @irq_idx_tbl_size: total number of irq_idx mapped in the hw_interrupts
127+ * @total_irqs: total number of irq_idx mapped in the hw_interrupts
182128 * @irq_lock: spinlock for accessing IRQ resources
183− * @obsolete_irq: irq types that are obsolete for a particular target
184129 */
185130 struct dpu_hw_intr {
186131 struct dpu_hw_blk_reg_map hw;
187132 struct dpu_hw_intr_ops ops;
188133 u32 *cache_irq_mask;
189134 u32 *save_irq_status;
190− u32 irq_idx_tbl_size;
135+ u32 total_irqs;
191136 spinlock_t irq_lock;
192137 unsigned long irq_mask;
193− unsigned long obsolete_irq;
194138 };
195139
196140 /**
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c+0−6
@@ -299,8 +299,6 @@ static void _setup_intf_ops(struct dpu_hw_intf_ops *ops, · 298 unmodified lines
299299 ops->bind_pingpong_blk = dpu_hw_intf_bind_pingpong_blk;
300300 }
301301
302−static struct dpu_hw_blk_ops dpu_hw_ops;
303−
304302 struct dpu_hw_intf *dpu_hw_intf_init(enum dpu_intf idx,
305303 void __iomem *addr,
306304 const struct dpu_mdss_cfg *m)
@@ -327,15 +325,11 @@ struct dpu_hw_intf *dpu_hw_intf_init(enum dpu_intf idx, · 20 unmodified lines
327325 c->mdss = m;
328326 _setup_intf_ops(&c->ops, c->cap->features);
329327
330− dpu_hw_blk_init(&c->base, DPU_HW_BLK_INTF, idx, &dpu_hw_ops);
331−
332328 return c;
333329 }
334330
335331 void dpu_hw_intf_destroy(struct dpu_hw_intf *intf)
336332 {
337− if (intf)
338− dpu_hw_blk_destroy(&intf->base);
339333 kfree(intf);
340334 }
341335
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c+0−6
@@ -160,8 +160,6 @@ static void _setup_mixer_ops(const struct dpu_mdss_cfg *m, · 159 unmodified lines
160160 ops->setup_border_color = dpu_hw_lm_setup_border_color;
161161 }
162162
163−static struct dpu_hw_blk_ops dpu_hw_ops;
164−
165163 struct dpu_hw_mixer *dpu_hw_lm_init(enum dpu_lm idx,
166164 void __iomem *addr,
167165 const struct dpu_mdss_cfg *m)
@@ -184,14 +182,10 @@ struct dpu_hw_mixer *dpu_hw_lm_init(enum dpu_lm idx, · 16 unmodified lines
184182 c->cap = cfg;
185183 _setup_mixer_ops(m, &c->ops, c->cap->features);
186184
187− dpu_hw_blk_init(&c->base, DPU_HW_BLK_LM, idx, &dpu_hw_ops);
188−
189185 return c;
190186 }
191187
192188 void dpu_hw_lm_destroy(struct dpu_hw_mixer *lm)
193189 {
194− if (lm)
195− dpu_hw_blk_destroy(&lm->base);
196190 kfree(lm);
197191 }
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h+1−1
@@ -343,7 +343,7 @@ enum dpu_3d_blend_mode { · 342 unmodified lines
343343
344344 /** struct dpu_format - defines the format configuration which
345345 * allows DPU HW to correctly fetch and decode the format
346− * @base: base msm_format struture containing fourcc code
346+ * @base: base msm_format structure containing fourcc code
347347 * @fetch_planes: how the color components are packed in pixel format
348348 * @element: element color ordering
349349 * @bits: element bit widths
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_merge3d.c+0−6
@@ -58,8 +58,6 @@ static void _setup_merge_3d_ops(struct dpu_hw_merge_3d *c, · 57 unmodified lines
5858 c->ops.setup_3d_mode = dpu_hw_merge_3d_setup_3d_mode;
5959 };
6060
61−static struct dpu_hw_blk_ops dpu_hw_ops;
62−
6361 struct dpu_hw_merge_3d *dpu_hw_merge_3d_init(enum dpu_merge_3d idx,
6462 void __iomem *addr,
6563 const struct dpu_mdss_cfg *m)
@@ -81,14 +79,10 @@ struct dpu_hw_merge_3d *dpu_hw_merge_3d_init(enum dpu_merge_3d idx, · 15 unmodified lines
8179 c->caps = cfg;
8280 _setup_merge_3d_ops(c, c->caps->features);
8381
84− dpu_hw_blk_init(&c->base, DPU_HW_BLK_MERGE_3D, idx, &dpu_hw_ops);
85−
8682 return c;
8783 }
8884
8985 void dpu_hw_merge_3d_destroy(struct dpu_hw_merge_3d *hw)
9086 {
91− if (hw)
92− dpu_hw_blk_destroy(&hw->base);
9387 kfree(hw);
9488 }
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.c+0−6
@@ -261,8 +261,6 @@ static void _setup_pingpong_ops(struct dpu_hw_pingpong *c, · 260 unmodified lines
261261 c->ops.setup_dither = dpu_hw_pp_setup_dither;
262262 };
263263
264−static struct dpu_hw_blk_ops dpu_hw_ops;
265−
266264 struct dpu_hw_pingpong *dpu_hw_pingpong_init(enum dpu_pingpong idx,
267265 void __iomem *addr,
268266 const struct dpu_mdss_cfg *m)
@@ -284,14 +282,10 @@ struct dpu_hw_pingpong *dpu_hw_pingpong_init(enum dpu_pingpong idx, · 15 unmodified lines
284282 c->caps = cfg;
285283 _setup_pingpong_ops(c, c->caps->features);
286284
287− dpu_hw_blk_init(&c->base, DPU_HW_BLK_PINGPONG, idx, &dpu_hw_ops);
288−
289285 return c;
290286 }
291287
292288 void dpu_hw_pingpong_destroy(struct dpu_hw_pingpong *pp)
293289 {
294− if (pp)
295− dpu_hw_blk_destroy(&pp->base);
296290 kfree(pp);
297291 }
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.h+3−1
@@ -126,6 +126,8 @@ struct dpu_hw_pingpong_ops { · 125 unmodified lines
126126 struct dpu_hw_dither_cfg *cfg);
127127 };
128128
129+struct dpu_hw_merge_3d;
130+
129131 struct dpu_hw_pingpong {
130132 struct dpu_hw_blk base;
131133 struct dpu_hw_blk_reg_map hw;
@@ -133,7 +135,7 @@ struct dpu_hw_pingpong { · 1 unmodified line
133135 /* pingpong */
134136 enum dpu_pingpong idx;
135137 const struct dpu_pingpong_cfg *caps;
136− struct dpu_hw_blk *merge_3d;
138+ struct dpu_hw_merge_3d *merge_3d;
137139
138140 /* ops */
139141 struct dpu_hw_pingpong_ops ops;
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c+0−6
@@ -706,8 +706,6 @@ static const struct dpu_sspp_cfg *_sspp_offset(enum dpu_sspp sspp, · 705 unmodified lines
706706 return ERR_PTR(-ENOMEM);
707707 }
708708
709−static struct dpu_hw_blk_ops dpu_hw_ops;
710−
711709 struct dpu_hw_pipe *dpu_hw_sspp_init(enum dpu_sspp idx,
712710 void __iomem *addr, struct dpu_mdss_cfg *catalog,
713711 bool is_virtual_pipe)
@@ -735,15 +733,11 @@ struct dpu_hw_pipe *dpu_hw_sspp_init(enum dpu_sspp idx, · 21 unmodified lines
735733 hw_pipe->cap = cfg;
736734 _setup_layer_ops(hw_pipe, hw_pipe->cap->features);
737735
738− dpu_hw_blk_init(&hw_pipe->base, DPU_HW_BLK_SSPP, idx, &dpu_hw_ops);
739−
740736 return hw_pipe;
741737 }
742738
743739 void dpu_hw_sspp_destroy(struct dpu_hw_pipe *ctx)
744740 {
745− if (ctx)
746− dpu_hw_blk_destroy(&ctx->base);
747741 kfree(ctx);
748742 }
749743
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c+0−6
@@ -295,8 +295,6 @@ static const struct dpu_mdp_cfg *_top_offset(enum dpu_mdp mdp, · 294 unmodified lines
295295 return ERR_PTR(-EINVAL);
296296 }
297297
298−static struct dpu_hw_blk_ops dpu_hw_ops;
299−
300298 struct dpu_hw_mdp *dpu_hw_mdptop_init(enum dpu_mdp idx,
301299 void __iomem *addr,
302300 const struct dpu_mdss_cfg *m)
@@ -324,15 +322,11 @@ struct dpu_hw_mdp *dpu_hw_mdptop_init(enum dpu_mdp idx, · 21 unmodified lines
324322 mdp->caps = cfg;
325323 _setup_mdp_ops(&mdp->ops, mdp->caps->features);
326324
327− dpu_hw_blk_init(&mdp->base, DPU_HW_BLK_TOP, idx, &dpu_hw_ops);
328−
329325 return mdp;
330326 }
331327
332328 void dpu_hw_mdp_destroy(struct dpu_hw_mdp *mdp)
333329 {
334− if (mdp)
335− dpu_hw_blk_destroy(&mdp->base);
336330 kfree(mdp);
337331 }
338332
drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c+55−15
@@ -19,6 +19,7 @@ · 18 unmodified lines
1919 #include "msm_drv.h"
2020 #include "msm_mmu.h"
2121 #include "msm_gem.h"
22+#include "disp/msm_disp_snapshot.h"
2223
2324 #include "dpu_kms.h"
2425 #include "dpu_core_irq.h"
@@ -798,6 +799,51 @@ static void dpu_irq_uninstall(struct msm_kms *kms) · 773 unmodified lines
798799 dpu_core_irq_uninstall(dpu_kms);
799800 }
800801
802+static void dpu_kms_mdp_snapshot(struct msm_disp_state *disp_state, struct msm_kms *kms)
803+{
804+ int i;
805+ struct dpu_kms *dpu_kms;
806+ struct dpu_mdss_cfg *cat;
807+ struct dpu_hw_mdp *top;
808+
809+ dpu_kms = to_dpu_kms(kms);
810+
811+ cat = dpu_kms->catalog;
812+ top = dpu_kms->hw_mdp;
813+
814+ pm_runtime_get_sync(&dpu_kms->pdev->dev);
815+
816+ /* dump CTL sub-blocks HW regs info */
817+ for (i = 0; i < cat->ctl_count; i++)
818+ msm_disp_snapshot_add_block(disp_state, cat->ctl[i].len,
819+ dpu_kms->mmio + cat->ctl[i].base, "ctl_%d", i);
820+
821+ /* dump DSPP sub-blocks HW regs info */
822+ for (i = 0; i < cat->dspp_count; i++)
823+ msm_disp_snapshot_add_block(disp_state, cat->dspp[i].len,
824+ dpu_kms->mmio + cat->dspp[i].base, "dspp_%d", i);
825+
826+ /* dump INTF sub-blocks HW regs info */
827+ for (i = 0; i < cat->intf_count; i++)
828+ msm_disp_snapshot_add_block(disp_state, cat->intf[i].len,
829+ dpu_kms->mmio + cat->intf[i].base, "intf_%d", i);
830+
831+ /* dump PP sub-blocks HW regs info */
832+ for (i = 0; i < cat->pingpong_count; i++)
833+ msm_disp_snapshot_add_block(disp_state, cat->pingpong[i].len,
834+ dpu_kms->mmio + cat->pingpong[i].base, "pingpong_%d", i);
835+
836+ /* dump SSPP sub-blocks HW regs info */
837+ for (i = 0; i < cat->sspp_count; i++)
838+ msm_disp_snapshot_add_block(disp_state, cat->sspp[i].len,
839+ dpu_kms->mmio + cat->sspp[i].base, "sspp_%d", i);
840+
841+ msm_disp_snapshot_add_block(disp_state, top->hw.length,
842+ dpu_kms->mmio + top->hw.blk_off, "top");
843+
844+ pm_runtime_put_sync(&dpu_kms->pdev->dev);
845+}
846+
801847 static const struct msm_kms_funcs kms_funcs = {
802848 .hw_init = dpu_kms_hw_init,
803849 .irq_preinstall = dpu_irq_preinstall,
@@ -818,6 +864,7 @@ static const struct msm_kms_funcs kms_funcs = { · 14 unmodified lines
818864 .round_pixclk = dpu_kms_round_pixclk,
819865 .destroy = dpu_kms_destroy,
820866 .set_encoder_mode = _dpu_kms_set_encoder_mode,
867+ .snapshot = dpu_kms_mdp_snapshot,
821868 #ifdef CONFIG_DEBUG_FS
822869 .debugfs_init = dpu_kms_debugfs_init,
823870 #endif
@@ -1089,21 +1136,21 @@ static int dpu_bind(struct device *dev, struct device *master, void *data) · 265 unmodified lines
10891136 if (!dpu_kms)
10901137 return -ENOMEM;
10911138
1092− dpu_kms->opp_table = dev_pm_opp_set_clkname(dev, "core");
1093− if (IS_ERR(dpu_kms->opp_table))
1094− return PTR_ERR(dpu_kms->opp_table);
1139+ ret = devm_pm_opp_set_clkname(dev, "core");
1140+ if (ret)
1141+ return ret;
10951142 /* OPP table is optional */
1096− ret = dev_pm_opp_of_add_table(dev);
1143+ ret = devm_pm_opp_of_add_table(dev);
10971144 if (ret && ret != -ENODEV) {
10981145 dev_err(dev, "invalid OPP table in device tree\n");
1099− goto put_clkname;
1146+ return ret;
11001147 }
11011148
11021149 mp = &dpu_kms->mp;
11031150 ret = msm_dss_parse_clock(pdev, mp);
11041151 if (ret) {
11051152 DPU_ERROR("failed to parse clocks, ret=%d\n", ret);
1106− goto err;
1153+ return ret;
11071154 }
11081155
11091156 platform_set_drvdata(pdev, dpu_kms);
@@ -1111,7 +1158,7 @@ static int dpu_bind(struct device *dev, struct device *master, void *data) · 1 unmodified line
11111158 ret = msm_kms_init(&dpu_kms->base, &kms_funcs);
11121159 if (ret) {
11131160 DPU_ERROR("failed to init kms, ret=%d\n", ret);
1114− goto err;
1161+ return ret;
11151162 }
11161163 dpu_kms->dev = ddev;
11171164 dpu_kms->pdev = pdev;
@@ -1120,11 +1167,7 @@ static int dpu_bind(struct device *dev, struct device *master, void *data) · 2 unmodified lines
11201167 dpu_kms->rpm_enabled = true;
11211168
11221169 priv->kms = &dpu_kms->base;
1123− return ret;
1124−err:
1125− dev_pm_opp_of_remove_table(dev);
1126−put_clkname:
1127− dev_pm_opp_put_clkname(dpu_kms->opp_table);
1170+
11281171 return ret;
11291172 }
11301173
@@ -1140,9 +1183,6 @@ static void dpu_unbind(struct device *dev, struct device *master, void *data) · 9 unmodified lines
11401183
11411184 if (dpu_kms->rpm_enabled)
11421185 pm_runtime_disable(&pdev->dev);
1143−
1144− dev_pm_opp_of_remove_table(dev);
1145− dev_pm_opp_put_clkname(dpu_kms->opp_table);
11461186 }
11471187
11481188 static const struct component_ops dpu_ops = {
drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h+1−7
@@ -82,16 +82,12 @@ struct dpu_irq_callback { · 81 unmodified lines
8282 * struct dpu_irq: IRQ structure contains callback registration info
8383 * @total_irq: total number of irq_idx obtained from HW interrupts mapping
8484 * @irq_cb_tbl: array of IRQ callbacks setting
85− * @enable_counts array of IRQ enable counts
86− * @cb_lock: callback lock
8785 * @debugfs_file: debugfs file for irq statistics
8886 */
8987 struct dpu_irq {
9088 u32 total_irqs;
9189 struct list_head *irq_cb_tbl;
92− atomic_t *enable_counts;
9390 atomic_t *irq_counts;
94− spinlock_t cb_lock;
9591 };
9692
9793 struct dpu_kms {
@@ -130,8 +126,6 @@ struct dpu_kms { · 32 unmodified lines
130126 struct platform_device *pdev;
131127 bool rpm_enabled;
132128
133− struct opp_table *opp_table;
134−
135129 struct dss_module_power mp;
136130
137131 /* reference count bandwidth requests, so we know when we can
@@ -258,7 +252,7 @@ void dpu_kms_encoder_enable(struct drm_encoder *encoder); · 120 unmodified lines
258252
259253 /**
260254 * dpu_kms_get_clk_rate() - get the clock rate
261− * @dpu_kms: poiner to dpu_kms structure
255+ * @dpu_kms: pointer to dpu_kms structure
262256 * @clock_name: clock name to get the rate
263257 *
264258 * Return: current clock rate
drivers/gpu/drm/msm/disp/dpu1/dpu_mdss.c+5−3
@@ -225,7 +225,7 @@ int dpu_mdss_init(struct drm_device *dev) · 224 unmodified lines
225225 struct msm_drm_private *priv = dev->dev_private;
226226 struct dpu_mdss *dpu_mdss;
227227 struct dss_module_power *mp;
228− int ret = 0;
228+ int ret;
229229 int irq;
230230
231231 dpu_mdss = devm_kzalloc(dev->dev, sizeof(*dpu_mdss), GFP_KERNEL);
@@ -253,8 +253,10 @@ int dpu_mdss_init(struct drm_device *dev) · 21 unmodified lines
253253 goto irq_domain_error;
254254
255255 irq = platform_get_irq(pdev, 0);
256− if (irq < 0)
256+ if (irq < 0) {
257+ ret = irq;
257258 goto irq_error;
259+ }
258260
259261 irq_set_chained_handler_and_data(irq, dpu_mdss_irq,
260262 dpu_mdss);
@@ -263,7 +265,7 @@ int dpu_mdss_init(struct drm_device *dev) · 2 unmodified lines
263265
264266 pm_runtime_enable(dev->dev);
265267
266− return ret;
268+ return 0;
267269
268270 irq_error:
269271 _dpu_mdss_irq_domain_fini(dpu_mdss);
drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c+10−13
@@ -25,7 +25,7 @@ · 24 unmodified lines
2525 #include "dpu_vbif.h"
2626 #include "dpu_plane.h"
2727
28−#define DPU_DEBUG_PLANE(pl, fmt, ...) DPU_DEBUG("plane%d " fmt,\
28+#define DPU_DEBUG_PLANE(pl, fmt, ...) DRM_DEBUG_ATOMIC("plane%d " fmt,\
2929 (pl) ? (pl)->base.base.id : -1, ##__VA_ARGS__)
3030
3131 #define DPU_ERROR_PLANE(pl, fmt, ...) DPU_ERROR("plane%d " fmt,\
@@ -284,8 +284,8 @@ static int _dpu_plane_calc_fill_level(struct drm_plane *plane, · 252 unmodified lines
284284 }
285285 }
286286
287− DPU_DEBUG("plane%u: pnum:%d fmt: %4.4s w:%u fl:%u\n",
288− plane->base.id, pdpu->pipe - SSPP_VIG0,
287+ DPU_DEBUG_PLANE(pdpu, "pnum:%d fmt: %4.4s w:%u fl:%u\n",
288+ pdpu->pipe - SSPP_VIG0,
289289 (char *)&fmt->base.pixel_format,
290290 src_width, total_fl);
291291
@@ -354,8 +354,7 @@ static void _dpu_plane_set_qos_lut(struct drm_plane *plane, · 62 unmodified lines
354354 (fmt) ? fmt->base.pixel_format : 0,
355355 pdpu->is_rt_pipe, total_fl, qos_lut, lut_usage);
356356
357− DPU_DEBUG("plane%u: pnum:%d fmt: %4.4s rt:%d fl:%u lut:0x%llx\n",
358− plane->base.id,
357+ DPU_DEBUG_PLANE(pdpu, "pnum:%d fmt: %4.4s rt:%d fl:%u lut:0x%llx\n",
359358 pdpu->pipe - SSPP_VIG0,
360359 fmt ? (char *)&fmt->base.pixel_format : NULL,
361360 pdpu->is_rt_pipe, total_fl, qos_lut);
@@ -364,7 +363,7 @@ static void _dpu_plane_set_qos_lut(struct drm_plane *plane, · 2 unmodified lines
364363 }
365364
366365 /**
367− * _dpu_plane_set_panic_lut - set danger/safe LUT of the given plane
366+ * _dpu_plane_set_danger_lut - set danger/safe LUT of the given plane
368367 * @plane: Pointer to drm plane
369368 * @fb: Pointer to framebuffer associated with the given plane
370369 */
@@ -407,8 +406,7 @@ static void _dpu_plane_set_danger_lut(struct drm_plane *plane, · 36 unmodified lines
407406 pdpu->pipe_qos_cfg.danger_lut,
408407 pdpu->pipe_qos_cfg.safe_lut);
409408
410− DPU_DEBUG("plane%u: pnum:%d fmt: %4.4s mode:%d luts[0x%x, 0x%x]\n",
411− plane->base.id,
409+ DPU_DEBUG_PLANE(pdpu, "pnum:%d fmt: %4.4s mode:%d luts[0x%x, 0x%x]\n",
412410 pdpu->pipe - SSPP_VIG0,
413411 fmt ? (char *)&fmt->base.pixel_format : NULL,
414412 fmt ? fmt->fetch_mode : -1,
@@ -451,8 +449,7 @@ static void _dpu_plane_set_qos_ctrl(struct drm_plane *plane, · 36 unmodified lines
451449 pdpu->pipe_qos_cfg.danger_safe_en = false;
452450 }
453451
454− DPU_DEBUG("plane%u: pnum:%d ds:%d vb:%d pri[0x%x, 0x%x] is_rt:%d\n",
455− plane->base.id,
452+ DPU_DEBUG_PLANE(pdpu, "pnum:%d ds:%d vb:%d pri[0x%x, 0x%x] is_rt:%d\n",
456453 pdpu->pipe - SSPP_VIG0,
457454 pdpu->pipe_qos_cfg.danger_safe_en,
458455 pdpu->pipe_qos_cfg.vblank_en,
@@ -491,7 +488,7 @@ static void _dpu_plane_set_ot_limit(struct drm_plane *plane, · 32 unmodified lines
491488 }
492489
493490 /**
494− * _dpu_plane_set_vbif_qos - set vbif QoS for the given plane
491+ * _dpu_plane_set_qos_remap - set vbif QoS for the given plane
495492 * @plane: Pointer to drm plane
496493 */
497494 static void _dpu_plane_set_qos_remap(struct drm_plane *plane)
@@ -507,8 +504,8 @@ static void _dpu_plane_set_qos_remap(struct drm_plane *plane) · 9 unmodified lines
507504 qos_params.num = pdpu->pipe_hw->idx - SSPP_VIG0;
508505 qos_params.is_rt = pdpu->is_rt_pipe;
509506
510− DPU_DEBUG("plane%d pipe:%d vbif:%d xin:%d rt:%d, clk_ctrl:%d\n",
511− plane->base.id, qos_params.num,
507+ DPU_DEBUG_PLANE(pdpu, "pipe:%d vbif:%d xin:%d rt:%d, clk_ctrl:%d\n",
508+ qos_params.num,
512509 qos_params.vbif_idx,
513510 qos_params.xin_id, qos_params.is_rt,
514511 qos_params.clk_ctrl);
drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c+2−2
@@ -162,7 +162,7 @@ int dpu_rm_init(struct dpu_rm *rm, · 161 unmodified lines
162162 goto fail;
163163 }
164164 if (pp->merge_3d && pp->merge_3d < MERGE_3D_MAX)
165− hw->merge_3d = rm->merge_3d_blks[pp->merge_3d - MERGE_3D_0];
165+ hw->merge_3d = to_dpu_hw_merge_3d(rm->merge_3d_blks[pp->merge_3d - MERGE_3D_0]);
166166 rm->pingpong_blks[pp->id - PINGPONG_0] = &hw->base;
167167 }
168168
@@ -428,7 +428,7 @@ static int _dpu_rm_reserve_ctls( · 259 unmodified lines
428428 features = ctl->caps->features;
429429 has_split_display = BIT(DPU_CTL_SPLIT_DISPLAY) & features;
430430
431− DPU_DEBUG("ctl %d caps 0x%lX\n", rm->ctl_blks[j]->id, features);
431+ DPU_DEBUG("ctl %d caps 0x%lX\n", j + CTL_0, features);
432432
433433 if (needs_split_display != has_split_display)
434434 continue;
drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h+18−45
@@ -168,44 +168,41 @@ TRACE_EVENT(dpu_perf_crtc_update, · 167 unmodified lines
168168 );
169169
170170 DECLARE_EVENT_CLASS(dpu_enc_irq_template,
171− TP_PROTO(uint32_t drm_id, enum dpu_intr_idx intr_idx, int hw_idx,
171+ TP_PROTO(uint32_t drm_id, enum dpu_intr_idx intr_idx,
172172 int irq_idx),
173− TP_ARGS(drm_id, intr_idx, hw_idx, irq_idx),
173+ TP_ARGS(drm_id, intr_idx, irq_idx),
174174 TP_STRUCT__entry(
175175 __field( uint32_t, drm_id )
176176 __field( enum dpu_intr_idx, intr_idx )
177− __field( int, hw_idx )
178177 __field( int, irq_idx )
179178 ),
180179 TP_fast_assign(
181180 __entry->drm_id = drm_id;
182181 __entry->intr_idx = intr_idx;
183− __entry->hw_idx = hw_idx;
184182 __entry->irq_idx = irq_idx;
185183 ),
186− TP_printk("id=%u, intr=%d, hw=%d, irq=%d",
187− __entry->drm_id, __entry->intr_idx, __entry->hw_idx,
184+ TP_printk("id=%u, intr=%d, irq=%d",
185+ __entry->drm_id, __entry->intr_idx,
188186 __entry->irq_idx)
189187 );
190188 DEFINE_EVENT(dpu_enc_irq_template, dpu_enc_irq_register_success,
191− TP_PROTO(uint32_t drm_id, enum dpu_intr_idx intr_idx, int hw_idx,
189+ TP_PROTO(uint32_t drm_id, enum dpu_intr_idx intr_idx,
192190 int irq_idx),
193− TP_ARGS(drm_id, intr_idx, hw_idx, irq_idx)
191+ TP_ARGS(drm_id, intr_idx, irq_idx)
194192 );
195193 DEFINE_EVENT(dpu_enc_irq_template, dpu_enc_irq_unregister_success,
196− TP_PROTO(uint32_t drm_id, enum dpu_intr_idx intr_idx, int hw_idx,
194+ TP_PROTO(uint32_t drm_id, enum dpu_intr_idx intr_idx,
197195 int irq_idx),
198− TP_ARGS(drm_id, intr_idx, hw_idx, irq_idx)
196+ TP_ARGS(drm_id, intr_idx, irq_idx)
199197 );
200198
201199 TRACE_EVENT(dpu_enc_irq_wait_success,
202− TP_PROTO(uint32_t drm_id, enum dpu_intr_idx intr_idx, int hw_idx,
200+ TP_PROTO(uint32_t drm_id, enum dpu_intr_idx intr_idx,
203201 int irq_idx, enum dpu_pingpong pp_idx, int atomic_cnt),
204− TP_ARGS(drm_id, intr_idx, hw_idx, irq_idx, pp_idx, atomic_cnt),
202+ TP_ARGS(drm_id, intr_idx, irq_idx, pp_idx, atomic_cnt),
205203 TP_STRUCT__entry(
206204 __field( uint32_t, drm_id )
207205 __field( enum dpu_intr_idx, intr_idx )
208− __field( int, hw_idx )
209206 __field( int, irq_idx )
210207 __field( enum dpu_pingpong, pp_idx )
211208 __field( int, atomic_cnt )
@@ -213,13 +210,12 @@ TRACE_EVENT(dpu_enc_irq_wait_success, · 1 unmodified line
213210 TP_fast_assign(
214211 __entry->drm_id = drm_id;
215212 __entry->intr_idx = intr_idx;
216− __entry->hw_idx = hw_idx;
217213 __entry->irq_idx = irq_idx;
218214 __entry->pp_idx = pp_idx;
219215 __entry->atomic_cnt = atomic_cnt;
220216 ),
221− TP_printk("id=%u, intr=%d, hw=%d, irq=%d, pp=%d, atomic_cnt=%d",
222− __entry->drm_id, __entry->intr_idx, __entry->hw_idx,
217+ TP_printk("id=%u, intr=%d, irq=%d, pp=%d, atomic_cnt=%d",
218+ __entry->drm_id, __entry->intr_idx,
223219 __entry->irq_idx, __entry->pp_idx, __entry->atomic_cnt)
224220 );
225221
@@ -514,12 +510,12 @@ DEFINE_EVENT(dpu_id_event_template, dpu_crtc_frame_event_more_pending, · 288 unmodified lines
514510 );
515511
516512 TRACE_EVENT(dpu_enc_wait_event_timeout,
517− TP_PROTO(uint32_t drm_id, int32_t hw_id, int rc, s64 time,
513+ TP_PROTO(uint32_t drm_id, int irq_idx, int rc, s64 time,
518514 s64 expected_time, int atomic_cnt),
519− TP_ARGS(drm_id, hw_id, rc, time, expected_time, atomic_cnt),
515+ TP_ARGS(drm_id, irq_idx, rc, time, expected_time, atomic_cnt),
520516 TP_STRUCT__entry(
521517 __field( uint32_t, drm_id )
522− __field( int32_t, hw_id )
518+ __field( int, irq_idx )
523519 __field( int, rc )
524520 __field( s64, time )
525521 __field( s64, expected_time )
@@ -527,14 +523,14 @@ TRACE_EVENT(dpu_enc_wait_event_timeout, · 1 unmodified line
527523 ),
528524 TP_fast_assign(
529525 __entry->drm_id = drm_id;
530− __entry->hw_id = hw_id;
526+ __entry->irq_idx = irq_idx;
531527 __entry->rc = rc;
532528 __entry->time = time;
533529 __entry->expected_time = expected_time;
534530 __entry->atomic_cnt = atomic_cnt;
535531 ),
536− TP_printk("id=%u, hw_id=%d, rc=%d, time=%lld, expected=%lld cnt=%d",
537− __entry->drm_id, __entry->hw_id, __entry->rc, __entry->time,
532+ TP_printk("id=%u, irq_idx=%d, rc=%d, time=%lld, expected=%lld cnt=%d",
533+ __entry->drm_id, __entry->irq_idx, __entry->rc, __entry->time,
538534 __entry->expected_time, __entry->atomic_cnt)
539535 );
540536
@@ -879,29 +875,6 @@ TRACE_EVENT(dpu_pp_connect_ext_te, · 338 unmodified lines
879875 TP_printk("pp:%d cfg:%u", __entry->pp, __entry->cfg)
880876 );
881877
882−DECLARE_EVENT_CLASS(dpu_core_irq_idx_cnt_template,
883− TP_PROTO(int irq_idx, int enable_count),
884− TP_ARGS(irq_idx, enable_count),
885− TP_STRUCT__entry(
886− __field( int, irq_idx )
887− __field( int, enable_count )
888− ),
889− TP_fast_assign(
890− __entry->irq_idx = irq_idx;
891− __entry->enable_count = enable_count;
892− ),
893− TP_printk("irq_idx:%d enable_count:%u", __entry->irq_idx,
894− __entry->enable_count)
895−);
896−DEFINE_EVENT(dpu_core_irq_idx_cnt_template, dpu_core_irq_enable_idx,
897− TP_PROTO(int irq_idx, int enable_count),
898− TP_ARGS(irq_idx, enable_count)
899−);
900−DEFINE_EVENT(dpu_core_irq_idx_cnt_template, dpu_core_irq_disable_idx,
901− TP_PROTO(int irq_idx, int enable_count),
902− TP_ARGS(irq_idx, enable_count)
903−);
904−
905878 DECLARE_EVENT_CLASS(dpu_core_irq_callback_template,
906879 TP_PROTO(int irq_idx, struct dpu_irq_callback *callback),
907880 TP_ARGS(irq_idx, callback),
drivers/gpu/drm/msm/disp/dpu1/dpu_vbif.c+7−7
@@ -46,7 +46,7 @@ static int _dpu_vbif_wait_for_xin_halt(struct dpu_hw_vbif *vbif, u32 xin_id) · 45 unmodified lines
4646 vbif->idx - VBIF_0, xin_id);
4747 } else {
4848 rc = 0;
49− DPU_DEBUG("VBIF %d client %d is halted\n",
49+ DRM_DEBUG_ATOMIC("VBIF %d client %d is halted\n",
5050 vbif->idx - VBIF_0, xin_id);
5151 }
5252
@@ -87,7 +87,7 @@ static void _dpu_vbif_apply_dynamic_ot_limit(struct dpu_hw_vbif *vbif, · 34 unmodified lines
8787 }
8888 }
8989
90− DPU_DEBUG("vbif:%d xin:%d w:%d h:%d fps:%d pps:%llu ot:%u\n",
90+ DRM_DEBUG_ATOMIC("vbif:%d xin:%d w:%d h:%d fps:%d pps:%llu ot:%u\n",
9191 vbif->idx - VBIF_0, params->xin_id,
9292 params->width, params->height, params->frame_rate,
9393 pps, *ot_lim);
@@ -133,7 +133,7 @@ static u32 _dpu_vbif_get_ot_limit(struct dpu_hw_vbif *vbif, · 39 unmodified lines
133133 }
134134
135135 exit:
136− DPU_DEBUG("vbif:%d xin:%d ot_lim:%d\n",
136+ DRM_DEBUG_ATOMIC("vbif:%d xin:%d ot_lim:%d\n",
137137 vbif->idx - VBIF_0, params->xin_id, ot_lim);
138138 return ot_lim;
139139 }
@@ -163,7 +163,7 @@ void dpu_vbif_set_ot_limit(struct dpu_kms *dpu_kms, · 23 unmodified lines
163163 }
164164
165165 if (!vbif || !mdp) {
166− DPU_DEBUG("invalid arguments vbif %d mdp %d\n",
166+ DRM_DEBUG_ATOMIC("invalid arguments vbif %d mdp %d\n",
167167 vbif != NULL, mdp != NULL);
168168 return;
169169 }
@@ -230,7 +230,7 @@ void dpu_vbif_set_qos_remap(struct dpu_kms *dpu_kms, · 60 unmodified lines
230230 }
231231
232232 if (!vbif->ops.set_qos_remap || !mdp->ops.setup_clk_force_ctrl) {
233− DPU_DEBUG("qos remap not supported\n");
233+ DRM_DEBUG_ATOMIC("qos remap not supported\n");
234234 return;
235235 }
236236
@@ -238,14 +238,14 @@ void dpu_vbif_set_qos_remap(struct dpu_kms *dpu_kms, · 1 unmodified line
238238 &vbif->cap->qos_nrt_tbl;
239239
240240 if (!qos_tbl->npriority_lvl || !qos_tbl->priority_lvl) {
241− DPU_DEBUG("qos tbl not defined\n");
241+ DRM_DEBUG_ATOMIC("qos tbl not defined\n");
242242 return;
243243 }
244244
245245 forced_on = mdp->ops.setup_clk_force_ctrl(mdp, params->clk_ctrl, true);
246246
247247 for (i = 0; i < qos_tbl->npriority_lvl; i++) {
248− DPU_DEBUG("vbif:%d xin:%d lvl:%d/%d\n",
248+ DRM_DEBUG_ATOMIC("vbif:%d xin:%d lvl:%d/%d\n",
249249 params->vbif_idx, params->xin_id, i,
250250 qos_tbl->priority_lvl[i]);
251251 vbif->ops.set_qos_remap(vbif, params->xin_id, i,
drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h+21−13
@@ -8,19 +8,27 @@ http://github.com/freedreno/envytools/ · 7 unmodified lines
88 git clone https://github.com/freedreno/envytools.git
99
1010 The rules-ng-ng source files this header was generated from are:
11−- /home/robclark/src/envytools/rnndb/msm.xml ( 676 bytes, from 2020-07-23 21:58:14)
12−- /home/robclark/src/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2020-07-23 21:58:14)
13−- /home/robclark/src/envytools/rnndb/mdp/mdp4.xml ( 20915 bytes, from 2020-07-23 21:58:14)
14−- /home/robclark/src/envytools/rnndb/mdp/mdp_common.xml ( 2849 bytes, from 2020-07-23 21:58:14)
15−- /home/robclark/src/envytools/rnndb/mdp/mdp5.xml ( 37411 bytes, from 2020-07-23 21:58:14)
16−- /home/robclark/src/envytools/rnndb/dsi/dsi.xml ( 42301 bytes, from 2020-07-23 21:58:14)
17−- /home/robclark/src/envytools/rnndb/dsi/sfpb.xml ( 602 bytes, from 2020-07-23 21:58:14)
18−- /home/robclark/src/envytools/rnndb/dsi/mmss_cc.xml ( 1686 bytes, from 2020-07-23 21:58:14)
19−- /home/robclark/src/envytools/rnndb/hdmi/qfprom.xml ( 600 bytes, from 2020-07-23 21:58:14)
20−- /home/robclark/src/envytools/rnndb/hdmi/hdmi.xml ( 41874 bytes, from 2020-07-23 21:58:14)
21−- /home/robclark/src/envytools/rnndb/edp/edp.xml ( 10416 bytes, from 2020-07-23 21:58:14)
22−
23−Copyright (C) 2013-2020 by the following authors:
11+- /home/robclark/src/mesa/mesa/src/freedreno/registers/msm.xml ( 981 bytes, from 2021-06-05 21:37:42)
12+- /home/robclark/src/mesa/mesa/src/freedreno/registers/freedreno_copyright.xml ( 1572 bytes, from 2021-02-18 16:45:44)
13+- /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp4.xml ( 20912 bytes, from 2021-02-18 16:45:44)
14+- /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp_common.xml ( 2849 bytes, from 2021-02-18 16:45:44)
15+- /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp5.xml ( 37461 bytes, from 2021-02-18 16:45:44)
16+- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi.xml ( 15291 bytes, from 2021-06-15 22:36:13)
17+- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_v2.xml ( 3236 bytes, from 2021-06-05 21:37:42)
18+- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_28nm_8960.xml ( 4935 bytes, from 2021-05-21 19:18:08)
19+- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_28nm.xml ( 7004 bytes, from 2021-05-21 19:18:08)
20+- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_20nm.xml ( 3712 bytes, from 2021-05-21 19:18:08)
21+- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_14nm.xml ( 5381 bytes, from 2021-05-21 19:18:08)
22+- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_10nm.xml ( 4499 bytes, from 2021-05-21 19:18:08)
23+- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_7nm.xml ( 10953 bytes, from 2021-05-21 19:18:08)
24+- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_5nm.xml ( 10900 bytes, from 2021-05-21 19:18:08)
25+- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/sfpb.xml ( 602 bytes, from 2021-02-18 16:45:44)
26+- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/mmss_cc.xml ( 1686 bytes, from 2021-02-18 16:45:44)
27+- /home/robclark/src/mesa/mesa/src/freedreno/registers/hdmi/qfprom.xml ( 600 bytes, from 2021-02-18 16:45:44)
28+- /home/robclark/src/mesa/mesa/src/freedreno/registers/hdmi/hdmi.xml ( 41874 bytes, from 2021-02-18 16:45:44)
29+- /home/robclark/src/mesa/mesa/src/freedreno/registers/edp/edp.xml ( 10416 bytes, from 2021-02-18 16:45:44)
30+
31+Copyright (C) 2013-2021 by the following authors:
2432 - Rob Clark <robdclark@gmail.com> (robclark)
2533 - Ilia Mirkin <imirkin@alum.mit.edu> (imirkin)
2634
drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h+25−13
@@ -8,19 +8,27 @@ http://github.com/freedreno/envytools/ · 7 unmodified lines
88 git clone https://github.com/freedreno/envytools.git
99
1010 The rules-ng-ng source files this header was generated from are:
11−- /home/robclark/src/envytools/rnndb/msm.xml ( 676 bytes, from 2020-07-23 21:58:14)
12−- /home/robclark/src/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2020-07-23 21:58:14)
13−- /home/robclark/src/envytools/rnndb/mdp/mdp4.xml ( 20915 bytes, from 2020-07-23 21:58:14)
14−- /home/robclark/src/envytools/rnndb/mdp/mdp_common.xml ( 2849 bytes, from 2020-07-23 21:58:14)
15−- /home/robclark/src/envytools/rnndb/mdp/mdp5.xml ( 37411 bytes, from 2020-07-23 21:58:14)
16−- /home/robclark/src/envytools/rnndb/dsi/dsi.xml ( 42301 bytes, from 2020-07-23 21:58:14)
17−- /home/robclark/src/envytools/rnndb/dsi/sfpb.xml ( 602 bytes, from 2020-07-23 21:58:14)
18−- /home/robclark/src/envytools/rnndb/dsi/mmss_cc.xml ( 1686 bytes, from 2020-07-23 21:58:14)
19−- /home/robclark/src/envytools/rnndb/hdmi/qfprom.xml ( 600 bytes, from 2020-07-23 21:58:14)
20−- /home/robclark/src/envytools/rnndb/hdmi/hdmi.xml ( 41874 bytes, from 2020-07-23 21:58:14)
21−- /home/robclark/src/envytools/rnndb/edp/edp.xml ( 10416 bytes, from 2020-07-23 21:58:14)
22−
23−Copyright (C) 2013-2020 by the following authors:
11+- /home/robclark/src/mesa/mesa/src/freedreno/registers/msm.xml ( 981 bytes, from 2021-06-05 21:37:42)
12+- /home/robclark/src/mesa/mesa/src/freedreno/registers/freedreno_copyright.xml ( 1572 bytes, from 2021-02-18 16:45:44)
13+- /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp4.xml ( 20912 bytes, from 2021-02-18 16:45:44)
14+- /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp_common.xml ( 2849 bytes, from 2021-02-18 16:45:44)
15+- /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp5.xml ( 37461 bytes, from 2021-02-18 16:45:44)
16+- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi.xml ( 15291 bytes, from 2021-06-15 22:36:13)
17+- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_v2.xml ( 3236 bytes, from 2021-06-05 21:37:42)
18+- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_28nm_8960.xml ( 4935 bytes, from 2021-05-21 19:18:08)
19+- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_28nm.xml ( 7004 bytes, from 2021-05-21 19:18:08)
20+- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_20nm.xml ( 3712 bytes, from 2021-05-21 19:18:08)
21+- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_14nm.xml ( 5381 bytes, from 2021-05-21 19:18:08)
22+- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_10nm.xml ( 4499 bytes, from 2021-05-21 19:18:08)
23+- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_7nm.xml ( 10953 bytes, from 2021-05-21 19:18:08)
24+- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_5nm.xml ( 10900 bytes, from 2021-05-21 19:18:08)
25+- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/sfpb.xml ( 602 bytes, from 2021-02-18 16:45:44)
26+- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/mmss_cc.xml ( 1686 bytes, from 2021-02-18 16:45:44)
27+- /home/robclark/src/mesa/mesa/src/freedreno/registers/hdmi/qfprom.xml ( 600 bytes, from 2021-02-18 16:45:44)
28+- /home/robclark/src/mesa/mesa/src/freedreno/registers/hdmi/hdmi.xml ( 41874 bytes, from 2021-02-18 16:45:44)
29+- /home/robclark/src/mesa/mesa/src/freedreno/registers/edp/edp.xml ( 10416 bytes, from 2021-02-18 16:45:44)
30+
31+Copyright (C) 2013-2021 by the following authors:
2432 - Rob Clark <robdclark@gmail.com> (robclark)
2533 - Ilia Mirkin <imirkin@alum.mit.edu> (imirkin)
2634
@@ -80,6 +88,10 @@ enum mdp5_pipe { · 53 unmodified lines
8088 SSPP_CURSOR1 = 12,
8189 };
8290
91+enum mdp5_format {
92+ DUMMY = 0,
93+};
94+
8395 enum mdp5_ctl_mode {
8496 MODE_NONE = 0,
8597 MODE_WB_0_BLOCK = 1,
drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.c+35−0
@@ -95,6 +95,11 @@ static const struct mdp5_cfg_hw msm8x74v1_config = { · 94 unmodified lines
9595 [3] = INTF_HDMI,
9696 },
9797 },
98+ .perf = {
99+ .ab_inefficiency = 200,
100+ .ib_inefficiency = 120,
101+ .clk_inefficiency = 125
102+ },
98103 .max_clk = 200000000,
99104 };
100105
@@ -177,6 +182,11 @@ static const struct mdp5_cfg_hw msm8x74v2_config = { · 76 unmodified lines
177182 [3] = INTF_HDMI,
178183 },
179184 },
185+ .perf = {
186+ .ab_inefficiency = 200,
187+ .ib_inefficiency = 120,
188+ .clk_inefficiency = 125
189+ },
180190 .max_clk = 320000000,
181191 };
182192
@@ -272,6 +282,11 @@ static const struct mdp5_cfg_hw apq8084_config = { · 89 unmodified lines
272282 [3] = INTF_HDMI,
273283 },
274284 },
285+ .perf = {
286+ .ab_inefficiency = 200,
287+ .ib_inefficiency = 120,
288+ .clk_inefficiency = 105
289+ },
275290 .max_clk = 320000000,
276291 };
277292
@@ -339,6 +354,11 @@ static const struct mdp5_cfg_hw msm8x16_config = { · 61 unmodified lines
339354 [1] = INTF_DSI,
340355 },
341356 },
357+ .perf = {
358+ .ab_inefficiency = 100,
359+ .ib_inefficiency = 200,
360+ .clk_inefficiency = 105
361+ },
342362 .max_clk = 320000000,
343363 };
344364
@@ -414,6 +434,11 @@ static const struct mdp5_cfg_hw msm8x36_config = { · 69 unmodified lines
414434 [2] = INTF_DSI,
415435 },
416436 },
437+ .perf = {
438+ .ab_inefficiency = 100,
439+ .ib_inefficiency = 200,
440+ .clk_inefficiency = 105
441+ },
417442 .max_clk = 366670000,
418443 };
419444
@@ -509,6 +534,11 @@ static const struct mdp5_cfg_hw msm8x94_config = { · 89 unmodified lines
509534 [3] = INTF_HDMI,
510535 },
511536 },
537+ .perf = {
538+ .ab_inefficiency = 100,
539+ .ib_inefficiency = 100,
540+ .clk_inefficiency = 105
541+ },
512542 .max_clk = 400000000,
513543 };
514544
@@ -617,6 +647,11 @@ static const struct mdp5_cfg_hw msm8x96_config = { · 102 unmodified lines
617647 [3] = INTF_HDMI,
618648 },
619649 },
650+ .perf = {
651+ .ab_inefficiency = 100,
652+ .ib_inefficiency = 200,
653+ .clk_inefficiency = 105
654+ },
620655 .max_clk = 412500000,
621656 };
622657
drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.h+7−0
@@ -76,6 +76,12 @@ struct mdp5_intf_block { · 75 unmodified lines
7676 u32 connect[MDP5_INTF_NUM_MAX]; /* array of enum mdp5_intf_type */
7777 };
7878
79+struct mdp5_perf_block {
80+ u32 ab_inefficiency;
81+ u32 ib_inefficiency;
82+ u32 clk_inefficiency;
83+};
84+
7985 struct mdp5_cfg_hw {
8086 char *name;
8187
@@ -93,6 +99,7 @@ struct mdp5_cfg_hw { · 11 unmodified lines
9399 struct mdp5_sub_block dsc;
94100 struct mdp5_sub_block cdm;
95101 struct mdp5_intf_block intf;
102+ struct mdp5_perf_block perf;
96103
97104 uint32_t max_clk;
98105 };
drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c+7−5
@@ -291,8 +291,8 @@ static void blend_setup(struct drm_crtc *crtc) · 290 unmodified lines
291291 plane = pstates[i]->base.plane;
292292 blend_op = MDP5_LM_BLEND_OP_MODE_FG_ALPHA(FG_CONST) |
293293 MDP5_LM_BLEND_OP_MODE_BG_ALPHA(BG_CONST);
294− fg_alpha = pstates[i]->alpha;
295− bg_alpha = 0xFF - pstates[i]->alpha;
294+ fg_alpha = pstates[i]->base.alpha >> 8;
295+ bg_alpha = 0xFF - fg_alpha;
296296
297297 if (!format->alpha_enable && bg_alpha_enabled)
298298 mixer_op_mode = 0;
@@ -301,7 +301,8 @@ static void blend_setup(struct drm_crtc *crtc) · 2 unmodified lines
301301
302302 DBG("Stage %d fg_alpha %x bg_alpha %x", i, fg_alpha, bg_alpha);
303303
304− if (format->alpha_enable && pstates[i]->premultiplied) {
304+ if (format->alpha_enable &&
305+ pstates[i]->base.pixel_blend_mode == DRM_MODE_BLEND_PREMULTI) {
305306 blend_op = MDP5_LM_BLEND_OP_MODE_FG_ALPHA(FG_CONST) |
306307 MDP5_LM_BLEND_OP_MODE_BG_ALPHA(FG_PIXEL);
307308 if (fg_alpha != 0xff) {
@@ -312,7 +313,8 @@ static void blend_setup(struct drm_crtc *crtc) · 4 unmodified lines
312313 } else {
313314 blend_op |= MDP5_LM_BLEND_OP_MODE_BG_INV_ALPHA;
314315 }
315− } else if (format->alpha_enable) {
316+ } else if (format->alpha_enable &&
317+ pstates[i]->base.pixel_blend_mode == DRM_MODE_BLEND_COVERAGE) {
316318 blend_op = MDP5_LM_BLEND_OP_MODE_FG_ALPHA(FG_PIXEL) |
317319 MDP5_LM_BLEND_OP_MODE_BG_ALPHA(FG_PIXEL);
318320 if (fg_alpha != 0xff) {
@@ -648,7 +650,7 @@ static int pstate_cmp(const void *a, const void *b) · 329 unmodified lines
648650 {
649651 struct plane_state *pa = (struct plane_state *)a;
650652 struct plane_state *pb = (struct plane_state *)b;
651− return pa->state->zpos - pb->state->zpos;
653+ return pa->state->base.normalized_zpos - pb->state->base.normalized_zpos;
652654 }
653655
654656 /* is there a helper for this? */
drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.h+0−5
@@ -98,11 +98,6 @@ struct mdp5_plane_state { · 97 unmodified lines
9898 struct mdp5_hw_pipe *hwpipe;
9999 struct mdp5_hw_pipe *r_hwpipe; /* right hwpipe */
100100
101− /* aligned with property */
102− uint8_t premultiplied;
103− uint8_t zpos;
104− uint8_t alpha;
105−
106101 /* assigned by crtc blender */
107102 enum mdp_mixer_stage_id stage;
108103 };
drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c+19−116
@@ -44,8 +44,9 @@ static void mdp5_plane_destroy(struct drm_plane *plane) · 43 unmodified lines
4444 kfree(mdp5_plane);
4545 }
4646
47−static void mdp5_plane_install_rotation_property(struct drm_device *dev,
48− struct drm_plane *plane)
47+/* helper to install properties which are common to planes and crtcs */
48+static void mdp5_plane_install_properties(struct drm_plane *plane,
49+ struct drm_mode_object *obj)
4950 {
5051 drm_plane_create_rotation_property(plane,
5152 DRM_MODE_ROTATE_0,
@@ -53,104 +54,12 @@ static void mdp5_plane_install_rotation_property(struct drm_device *dev, · 1 unmodified line
5354 DRM_MODE_ROTATE_180 |
5455 DRM_MODE_REFLECT_X |
5556 DRM_MODE_REFLECT_Y);
56−}
57−
58−/* helper to install properties which are common to planes and crtcs */
59−static void mdp5_plane_install_properties(struct drm_plane *plane,
60− struct drm_mode_object *obj)
61−{
62− struct drm_device *dev = plane->dev;
63− struct msm_drm_private *dev_priv = dev->dev_private;
64− struct drm_property *prop;
65−
66−#define INSTALL_PROPERTY(name, NAME, init_val, fnc, ...) do { \
67− prop = dev_priv->plane_property[PLANE_PROP_##NAME]; \
68− if (!prop) { \
69− prop = drm_property_##fnc(dev, 0, #name, \
70− ##__VA_ARGS__); \
71− if (!prop) { \
72− dev_warn(dev->dev, \
73− "Create property %s failed\n", \
74− #name); \
75− return; \
76− } \
77− dev_priv->plane_property[PLANE_PROP_##NAME] = prop; \
78− } \
79− drm_object_attach_property(&plane->base, prop, init_val); \
80− } while (0)
81−
82−#define INSTALL_RANGE_PROPERTY(name, NAME, min, max, init_val) \
83− INSTALL_PROPERTY(name, NAME, init_val, \
84− create_range, min, max)
85−
86−#define INSTALL_ENUM_PROPERTY(name, NAME, init_val) \
87− INSTALL_PROPERTY(name, NAME, init_val, \
88− create_enum, name##_prop_enum_list, \
89− ARRAY_SIZE(name##_prop_enum_list))
90−
91− INSTALL_RANGE_PROPERTY(zpos, ZPOS, 1, 255, 1);
92−
93− mdp5_plane_install_rotation_property(dev, plane);
94−
95−#undef INSTALL_RANGE_PROPERTY
96−#undef INSTALL_ENUM_PROPERTY
97−#undef INSTALL_PROPERTY
98−}
99−
100−static int mdp5_plane_atomic_set_property(struct drm_plane *plane,
101− struct drm_plane_state *state, struct drm_property *property,
102− uint64_t val)
103−{
104− struct drm_device *dev = plane->dev;
105− struct mdp5_plane_state *pstate;
106− struct msm_drm_private *dev_priv = dev->dev_private;
107− int ret = 0;
108−
109− pstate = to_mdp5_plane_state(state);
110−
111−#define SET_PROPERTY(name, NAME, type) do { \
112− if (dev_priv->plane_property[PLANE_PROP_##NAME] == property) { \
113− pstate->name = (type)val; \
114− DBG("Set property %s %d", #name, (type)val); \
115− goto done; \
116− } \
117− } while (0)
118−
119− SET_PROPERTY(zpos, ZPOS, uint8_t);
120−
121− DRM_DEV_ERROR(dev->dev, "Invalid property\n");
122− ret = -EINVAL;
123−done:
124− return ret;
125−#undef SET_PROPERTY
126−}
127−
128−static int mdp5_plane_atomic_get_property(struct drm_plane *plane,
129− const struct drm_plane_state *state,
130− struct drm_property *property, uint64_t *val)
131−{
132− struct drm_device *dev = plane->dev;
133− struct mdp5_plane_state *pstate;
134− struct msm_drm_private *dev_priv = dev->dev_private;
135− int ret = 0;
136−
137− pstate = to_mdp5_plane_state(state);
138−
139−#define GET_PROPERTY(name, NAME, type) do { \
140− if (dev_priv->plane_property[PLANE_PROP_##NAME] == property) { \
141− *val = pstate->name; \
142− DBG("Get property %s %lld", #name, *val); \
143− goto done; \
144− } \
145− } while (0)
146−
147− GET_PROPERTY(zpos, ZPOS, uint8_t);
148−
149− DRM_DEV_ERROR(dev->dev, "Invalid property\n");
150− ret = -EINVAL;
151−done:
152− return ret;
153−#undef SET_PROPERTY
57+ drm_plane_create_alpha_property(plane);
58+ drm_plane_create_blend_mode_property(plane,
59+ BIT(DRM_MODE_BLEND_PIXEL_NONE) |
60+ BIT(DRM_MODE_BLEND_PREMULTI) |
61+ BIT(DRM_MODE_BLEND_COVERAGE));
62+ drm_plane_create_zpos_property(plane, 1, 1, 255);
15463 }
15564
15665 static void
@@ -166,9 +75,10 @@ mdp5_plane_atomic_print_state(struct drm_printer *p, · 9 unmodified lines
16675 drm_printf(p, "\tright-hwpipe=%s\n",
16776 pstate->r_hwpipe ? pstate->r_hwpipe->name :
16877 "(null)");
169− drm_printf(p, "\tpremultiplied=%u\n", pstate->premultiplied);
170− drm_printf(p, "\tzpos=%u\n", pstate->zpos);
171− drm_printf(p, "\talpha=%u\n", pstate->alpha);
78+ drm_printf(p, "\tblend_mode=%u\n", pstate->base.pixel_blend_mode);
79+ drm_printf(p, "\tzpos=%u\n", pstate->base.zpos);
80+ drm_printf(p, "\tnormalized_zpos=%u\n", pstate->base.normalized_zpos);
81+ drm_printf(p, "\talpha=%u\n", pstate->base.alpha);
17282 drm_printf(p, "\tstage=%s\n", stage2name(pstate->stage));
17383 }
17484
@@ -176,24 +86,19 @@ static void mdp5_plane_reset(struct drm_plane *plane) · 1 unmodified line
17686 {
17787 struct mdp5_plane_state *mdp5_state;
17888
179− if (plane->state && plane->state->fb)
180− drm_framebuffer_put(plane->state->fb);
89+ if (plane->state)
90+ __drm_atomic_helper_plane_destroy_state(plane->state);
18191
18292 kfree(to_mdp5_plane_state(plane->state));
18393 mdp5_state = kzalloc(sizeof(*mdp5_state), GFP_KERNEL);
18494
185− /* assign default blend parameters */
186− mdp5_state->alpha = 255;
187− mdp5_state->premultiplied = 0;
188−
18995 if (plane->type == DRM_PLANE_TYPE_PRIMARY)
190− mdp5_state->zpos = STAGE_BASE;
96+ mdp5_state->base.zpos = STAGE_BASE;
19197 else
192− mdp5_state->zpos = STAGE0 + drm_plane_index(plane);
193−
194− mdp5_state->base.plane = plane;
98+ mdp5_state->base.zpos = STAGE0 + drm_plane_index(plane);
99+ mdp5_state->base.normalized_zpos = mdp5_state->base.zpos;
195100
196− plane->state = &mdp5_state->base;
101+ __drm_atomic_helper_plane_reset(plane, &mdp5_state->base);
197102 }
198103
199104 static struct drm_plane_state *
@@ -229,8 +134,6 @@ static const struct drm_plane_funcs mdp5_plane_funcs = { · 29 unmodified lines
229134 .update_plane = drm_atomic_helper_update_plane,
230135 .disable_plane = drm_atomic_helper_disable_plane,
231136 .destroy = mdp5_plane_destroy,
232− .atomic_set_property = mdp5_plane_atomic_set_property,
233− .atomic_get_property = mdp5_plane_atomic_get_property,
234137 .reset = mdp5_plane_reset,
235138 .atomic_duplicate_state = mdp5_plane_duplicate_state,
236139 .atomic_destroy_state = mdp5_plane_destroy_state,
drivers/gpu/drm/msm/disp/mdp_common.xml.h+21−13
@@ -8,19 +8,27 @@ http://github.com/freedreno/envytools/ · 7 unmodified lines
88 git clone https://github.com/freedreno/envytools.git
99
1010 The rules-ng-ng source files this header was generated from are:
11−- /home/robclark/src/envytools/rnndb/msm.xml ( 676 bytes, from 2020-07-23 21:58:14)
12−- /home/robclark/src/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2020-07-23 21:58:14)
13−- /home/robclark/src/envytools/rnndb/mdp/mdp4.xml ( 20915 bytes, from 2020-07-23 21:58:14)
14−- /home/robclark/src/envytools/rnndb/mdp/mdp_common.xml ( 2849 bytes, from 2020-07-23 21:58:14)
15−- /home/robclark/src/envytools/rnndb/mdp/mdp5.xml ( 37411 bytes, from 2020-07-23 21:58:14)
16−- /home/robclark/src/envytools/rnndb/dsi/dsi.xml ( 42301 bytes, from 2020-07-23 21:58:14)
17−- /home/robclark/src/envytools/rnndb/dsi/sfpb.xml ( 602 bytes, from 2020-07-23 21:58:14)
18−- /home/robclark/src/envytools/rnndb/dsi/mmss_cc.xml ( 1686 bytes, from 2020-07-23 21:58:14)
19−- /home/robclark/src/envytools/rnndb/hdmi/qfprom.xml ( 600 bytes, from 2020-07-23 21:58:14)
20−- /home/robclark/src/envytools/rnndb/hdmi/hdmi.xml ( 41874 bytes, from 2020-07-23 21:58:14)
21−- /home/robclark/src/envytools/rnndb/edp/edp.xml ( 10416 bytes, from 2020-07-23 21:58:14)
22−
23−Copyright (C) 2013-2020 by the following authors:
11+- /home/robclark/src/mesa/mesa/src/freedreno/registers/msm.xml ( 981 bytes, from 2021-06-05 21:37:42)
12+- /home/robclark/src/mesa/mesa/src/freedreno/registers/freedreno_copyright.xml ( 1572 bytes, from 2021-02-18 16:45:44)
13+- /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp4.xml ( 20912 bytes, from 2021-02-18 16:45:44)
14+- /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp_common.xml ( 2849 bytes, from 2021-02-18 16:45:44)
15+- /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp5.xml ( 37461 bytes, from 2021-02-18 16:45:44)
16+- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi.xml ( 15291 bytes, from 2021-06-15 22:36:13)
17+- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_v2.xml ( 3236 bytes, from 2021-06-05 21:37:42)
18+- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_28nm_8960.xml ( 4935 bytes, from 2021-05-21 19:18:08)
19+- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_28nm.xml ( 7004 bytes, from 2021-05-21 19:18:08)
20+- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_20nm.xml ( 3712 bytes, from 2021-05-21 19:18:08)
21+- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_14nm.xml ( 5381 bytes, from 2021-05-21 19:18:08)
22+- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_10nm.xml ( 4499 bytes, from 2021-05-21 19:18:08)
23+- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_7nm.xml ( 10953 bytes, from 2021-05-21 19:18:08)
24+- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_5nm.xml ( 10900 bytes, from 2021-05-21 19:18:08)
25+- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/sfpb.xml ( 602 bytes, from 2021-02-18 16:45:44)
26+- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/mmss_cc.xml ( 1686 bytes, from 2021-02-18 16:45:44)
27+- /home/robclark/src/mesa/mesa/src/freedreno/registers/hdmi/qfprom.xml ( 600 bytes, from 2021-02-18 16:45:44)
28+- /home/robclark/src/mesa/mesa/src/freedreno/registers/hdmi/hdmi.xml ( 41874 bytes, from 2021-02-18 16:45:44)
29+- /home/robclark/src/mesa/mesa/src/freedreno/registers/edp/edp.xml ( 10416 bytes, from 2021-02-18 16:45:44)
30+
31+Copyright (C) 2013-2021 by the following authors:
2432 - Rob Clark <robdclark@gmail.com> (robclark)
2533 - Ilia Mirkin <imirkin@alum.mit.edu> (imirkin)
2634
drivers/gpu/drm/msm/disp/msm_disp_snapshot.c+125−0
@@ -0,0 +1,125 @@
1+// SPDX-License-Identifier: GPL-2.0-only
2+/*
3+ * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved.
4+ */
5+
6+#define pr_fmt(fmt) "[drm:%s:%d] " fmt, __func__, __LINE__
7+
8+#include "msm_disp_snapshot.h"
9+
10+static ssize_t __maybe_unused disp_devcoredump_read(char *buffer, loff_t offset,
11+ size_t count, void *data, size_t datalen)
12+{
13+ struct drm_print_iterator iter;
14+ struct drm_printer p;
15+ struct msm_disp_state *disp_state;
16+
17+ disp_state = data;
18+
19+ iter.data = buffer;
20+ iter.offset = 0;
21+ iter.start = offset;
22+ iter.remain = count;
23+
24+ p = drm_coredump_printer(&iter);
25+
26+ msm_disp_state_print(disp_state, &p);
27+
28+ return count - iter.remain;
29+}
30+
31+static void _msm_disp_snapshot_work(struct kthread_work *work)
32+{
33+ struct msm_kms *kms = container_of(work, struct msm_kms, dump_work);
34+ struct drm_device *drm_dev = kms->dev;
35+ struct msm_disp_state *disp_state;
36+ struct drm_printer p;
37+
38+ disp_state = kzalloc(sizeof(struct msm_disp_state), GFP_KERNEL);
39+ if (!disp_state)
40+ return;
41+
42+ disp_state->dev = drm_dev->dev;
43+ disp_state->drm_dev = drm_dev;
44+
45+ INIT_LIST_HEAD(&disp_state->blocks);
46+
47+ /* Serialize dumping here */
48+ mutex_lock(&kms->dump_mutex);
49+
50+ msm_disp_snapshot_capture_state(disp_state);
51+
52+ mutex_unlock(&kms->dump_mutex);
53+
54+ if (MSM_DISP_SNAPSHOT_DUMP_IN_CONSOLE) {
55+ p = drm_info_printer(disp_state->drm_dev->dev);
56+ msm_disp_state_print(disp_state, &p);
57+ }
58+
59+ /*
60+ * If COREDUMP is disabled, the stub will call the free function.
61+ * If there is a codedump pending for the device, the dev_coredumpm()
62+ * will also free new coredump state.
63+ */
64+ dev_coredumpm(disp_state->dev, THIS_MODULE, disp_state, 0, GFP_KERNEL,
65+ disp_devcoredump_read, msm_disp_state_free);
66+}
67+
68+void msm_disp_snapshot_state(struct drm_device *drm_dev)
69+{
70+ struct msm_drm_private *priv;
71+ struct msm_kms *kms;
72+
73+ if (!drm_dev) {
74+ DRM_ERROR("invalid params\n");
75+ return;
76+ }
77+
78+ priv = drm_dev->dev_private;
79+ kms = priv->kms;
80+
81+ kthread_queue_work(kms->dump_worker, &kms->dump_work);
82+}
83+
84+int msm_disp_snapshot_init(struct drm_device *drm_dev)
85+{
86+ struct msm_drm_private *priv;
87+ struct msm_kms *kms;
88+
89+ if (!drm_dev) {
90+ DRM_ERROR("invalid params\n");
91+ return -EINVAL;
92+ }
93+
94+ priv = drm_dev->dev_private;
95+ kms = priv->kms;
96+
97+ mutex_init(&kms->dump_mutex);
98+
99+ kms->dump_worker = kthread_create_worker(0, "%s", "disp_snapshot");
100+ if (IS_ERR(kms->dump_worker))
101+ DRM_ERROR("failed to create disp state task\n");
102+
103+ kthread_init_work(&kms->dump_work, _msm_disp_snapshot_work);
104+
105+ return 0;
106+}
107+
108+void msm_disp_snapshot_destroy(struct drm_device *drm_dev)
109+{
110+ struct msm_kms *kms;
111+ struct msm_drm_private *priv;
112+
113+ if (!drm_dev) {
114+ DRM_ERROR("invalid params\n");
115+ return;
116+ }
117+
118+ priv = drm_dev->dev_private;
119+ kms = priv->kms;
120+
121+ if (kms->dump_worker)
122+ kthread_destroy_worker(kms->dump_worker);
123+
124+ mutex_destroy(&kms->dump_mutex);
125+}
drivers/gpu/drm/msm/disp/msm_disp_snapshot.h+136−0
@@ -0,0 +1,136 @@
1+/* SPDX-License-Identifier: GPL-2.0-only */
2+/*
3+ * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved.
4+ */
5+
6+#ifndef MSM_DISP_SNAPSHOT_H_
7+#define MSM_DISP_SNAPSHOT_H_
8+
9+#include <drm/drm_atomic_helper.h>
10+#include <drm/drm_device.h>
11+#include "../../../drm_crtc_internal.h"
12+#include <drm/drm_print.h>
13+#include <drm/drm_atomic.h>
14+#include <linux/debugfs.h>
15+#include <linux/list.h>
16+#include <linux/delay.h>
17+#include <linux/spinlock.h>
18+#include <linux/ktime.h>
19+#include <linux/debugfs.h>
20+#include <linux/uaccess.h>
21+#include <linux/dma-buf.h>
22+#include <linux/slab.h>
23+#include <linux/list_sort.h>
24+#include <linux/pm.h>
25+#include <linux/pm_runtime.h>
26+#include <linux/kthread.h>
27+#include <linux/devcoredump.h>
28+#include <stdarg.h>
29+#include "msm_kms.h"
30+
31+#define MSM_DISP_SNAPSHOT_MAX_BLKS 10
32+
33+/* debug option to print the registers in logs */
34+#define MSM_DISP_SNAPSHOT_DUMP_IN_CONSOLE 0
35+
36+/* print debug ranges in groups of 4 u32s */
37+#define REG_DUMP_ALIGN 16
38+
39+/**
40+ * struct msm_disp_state - structure to store current dpu state
41+ * @dev: device pointer
42+ * @drm_dev: drm device pointer
43+ * @atomic_state: atomic state duplicated at the time of the error
44+ * @timestamp: timestamp at which the coredump was captured
45+ */
46+struct msm_disp_state {
47+ struct device *dev;
48+ struct drm_device *drm_dev;
49+
50+ struct list_head blocks;
51+
52+ struct drm_atomic_state *atomic_state;
53+
54+ ktime_t timestamp;
55+};
56+
57+/**
58+ * struct msm_disp_state_block - structure to store each hardware block state
59+ * @name: name of the block
60+ * @drm_dev: handle to the linked list head
61+ * @size: size of the register space of this hardware block
62+ * @state: array holding the register dump of this hardware block
63+ * @base_addr: starting address of this hardware block's register space
64+ */
65+struct msm_disp_state_block {
66+ char name[SZ_128];
67+ struct list_head node;
68+ unsigned int size;
69+ u32 *state;
70+ void __iomem *base_addr;
71+};
72+
73+/**
74+ * msm_disp_snapshot_init - initialize display snapshot
75+ * @drm_dev: drm device handle
76+ *
77+ * Returns: 0 or -ERROR
78+ */
79+int msm_disp_snapshot_init(struct drm_device *drm_dev);
80+
81+/**
82+ * msm_disp_snapshot_destroy - destroy the display snapshot
83+ * @drm_dev: drm device handle
84+ *
85+ * Returns: none
86+ */
87+void msm_disp_snapshot_destroy(struct drm_device *drm_dev);
88+
89+/**
90+ * msm_disp_snapshot_state - trigger to dump the display snapshot
91+ * @drm_dev: handle to drm device
92+
93+ * Returns: none
94+ */
95+void msm_disp_snapshot_state(struct drm_device *drm_dev);
96+
97+/**
98+ * msm_disp_state_print - print out the current dpu state
99+ * @disp_state: handle to drm device
100+ * @p: handle to drm printer
101+ *
102+ * Returns: none
103+ */
104+void msm_disp_state_print(struct msm_disp_state *disp_state, struct drm_printer *p);
105+
106+/**
107+ * msm_disp_snapshot_capture_state - utility to capture atomic state and hw registers
108+ * @disp_state: handle to msm_disp_state struct
109+
110+ * Returns: none
111+ */
112+void msm_disp_snapshot_capture_state(struct msm_disp_state *disp_state);
113+
114+/**
115+ * msm_disp_state_free - free the memory after the coredump has been read
116+ * @data: handle to struct msm_disp_state
117+
118+ * Returns: none
119+ */
120+void msm_disp_state_free(void *data);
121+
122+/**
123+ * msm_disp_snapshot_add_block - add a hardware block with its register dump
124+ * @disp_state: handle to struct msm_disp_state
125+ * @name: name of the hardware block
126+ * @len: size of the register space of the hardware block
127+ * @base_addr: starting address of the register space of the hardware block
128+ * @fmt: format in which the block names need to be printed
129+ *
130+ * Returns: none
131+ */
132+__printf(4, 5)
133+void msm_disp_snapshot_add_block(struct msm_disp_state *disp_state, u32 len,
134+ void __iomem *base_addr, const char *fmt, ...);
135+
136+#endif /* MSM_DISP_SNAPSHOT_H_ */
drivers/gpu/drm/msm/disp/msm_disp_snapshot_util.c+187−0
@@ -0,0 +1,187 @@
1+// SPDX-License-Identifier: GPL-2.0-only
2+/*
3+ * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved.
4+ */
5+
6+#define pr_fmt(fmt) "[drm:%s:%d] " fmt, __func__, __LINE__
7+
8+#include "msm_disp_snapshot.h"
9+
10+static void msm_disp_state_dump_regs(u32 **reg, u32 aligned_len, void __iomem *base_addr)
11+{
12+ u32 len_padded;
13+ u32 num_rows;
14+ u32 x0, x4, x8, xc;
15+ void __iomem *addr;
16+ u32 *dump_addr = NULL;
17+ void __iomem *end_addr;
18+ int i;
19+
20+ len_padded = aligned_len * REG_DUMP_ALIGN;
21+ num_rows = aligned_len / REG_DUMP_ALIGN;
22+
23+ addr = base_addr;
24+ end_addr = base_addr + aligned_len;
25+
26+ if (!(*reg))
27+ *reg = kzalloc(len_padded, GFP_KERNEL);
28+
29+ if (*reg)
30+ dump_addr = *reg;
31+
32+ for (i = 0; i < num_rows; i++) {
33+ x0 = (addr < end_addr) ? readl_relaxed(addr + 0x0) : 0;
34+ x4 = (addr + 0x4 < end_addr) ? readl_relaxed(addr + 0x4) : 0;
35+ x8 = (addr + 0x8 < end_addr) ? readl_relaxed(addr + 0x8) : 0;
36+ xc = (addr + 0xc < end_addr) ? readl_relaxed(addr + 0xc) : 0;
37+
38+ if (dump_addr) {
39+ dump_addr[i * 4] = x0;
40+ dump_addr[i * 4 + 1] = x4;
41+ dump_addr[i * 4 + 2] = x8;
42+ dump_addr[i * 4 + 3] = xc;
43+ }
44+
45+ addr += REG_DUMP_ALIGN;
46+ }
47+}
48+
49+static void msm_disp_state_print_regs(u32 **reg, u32 len, void __iomem *base_addr,
50+ struct drm_printer *p)
51+{
52+ int i;
53+ u32 *dump_addr = NULL;
54+ void __iomem *addr;
55+ u32 num_rows;
56+
57+ addr = base_addr;
58+ num_rows = len / REG_DUMP_ALIGN;
59+
60+ if (*reg)
61+ dump_addr = *reg;
62+
63+ for (i = 0; i < num_rows; i++) {
64+ drm_printf(p, "0x%lx : %08x %08x %08x %08x\n",
65+ (unsigned long)(addr - base_addr),
66+ dump_addr[i * 4], dump_addr[i * 4 + 1],
67+ dump_addr[i * 4 + 2], dump_addr[i * 4 + 3]);
68+ addr += REG_DUMP_ALIGN;
69+ }
70+}
71+
72+void msm_disp_state_print(struct msm_disp_state *state, struct drm_printer *p)
73+{
74+ struct msm_disp_state_block *block, *tmp;
75+
76+ if (!p) {
77+ DRM_ERROR("invalid drm printer\n");
78+ return;
79+ }
80+
81+ drm_printf(p, "---\n");
82+
83+ drm_printf(p, "module: " KBUILD_MODNAME "\n");
84+ drm_printf(p, "dpu devcoredump\n");
85+ drm_printf(p, "timestamp %lld\n", ktime_to_ns(state->timestamp));
86+
87+ list_for_each_entry_safe(block, tmp, &state->blocks, node) {
88+ drm_printf(p, "====================%s================\n", block->name);
89+ msm_disp_state_print_regs(&block->state, block->size, block->base_addr, p);
90+ }
91+
92+ drm_printf(p, "===================dpu drm state================\n");
93+
94+ if (state->atomic_state)
95+ drm_atomic_print_new_state(state->atomic_state, p);
96+}
97+
98+static void msm_disp_capture_atomic_state(struct msm_disp_state *disp_state)
99+{
100+ struct drm_device *ddev;
101+ struct drm_modeset_acquire_ctx ctx;
102+
103+ disp_state->timestamp = ktime_get();
104+
105+ ddev = disp_state->drm_dev;
106+
107+ drm_modeset_acquire_init(&ctx, 0);
108+
109+ while (drm_modeset_lock_all_ctx(ddev, &ctx) != 0)
110+ drm_modeset_backoff(&ctx);
111+
112+ disp_state->atomic_state = drm_atomic_helper_duplicate_state(ddev,
113+ &ctx);
114+ drm_modeset_drop_locks(&ctx);
115+ drm_modeset_acquire_fini(&ctx);
116+}
117+
118+void msm_disp_snapshot_capture_state(struct msm_disp_state *disp_state)
119+{
120+ struct msm_drm_private *priv;
121+ struct drm_device *drm_dev;
122+ struct msm_kms *kms;
123+ int i;
124+
125+ drm_dev = disp_state->drm_dev;
126+ priv = drm_dev->dev_private;
127+ kms = priv->kms;
128+
129+ if (priv->dp)
130+ msm_dp_snapshot(disp_state, priv->dp);
131+
132+ for (i = 0; i < ARRAY_SIZE(priv->dsi); i++) {
133+ if (!priv->dsi[i])
134+ continue;
135+
136+ msm_dsi_snapshot(disp_state, priv->dsi[i]);
137+ }
138+
139+ if (kms->funcs->snapshot)
140+ kms->funcs->snapshot(disp_state, kms);
141+
142+ msm_disp_capture_atomic_state(disp_state);
143+}
144+
145+void msm_disp_state_free(void *data)
146+{
147+ struct msm_disp_state *disp_state = data;
148+ struct msm_disp_state_block *block, *tmp;
149+
150+ if (disp_state->atomic_state) {
151+ drm_atomic_state_put(disp_state->atomic_state);
152+ disp_state->atomic_state = NULL;
153+ }
154+
155+ list_for_each_entry_safe(block, tmp, &disp_state->blocks, node) {
156+ list_del(&block->node);
157+ kfree(block->state);
158+ kfree(block);
159+ }
160+
161+ kfree(disp_state);
162+}
163+
164+void msm_disp_snapshot_add_block(struct msm_disp_state *disp_state, u32 len,
165+ void __iomem *base_addr, const char *fmt, ...)
166+{
167+ struct msm_disp_state_block *new_blk;
168+ struct va_format vaf;
169+ va_list va;
170+
171+ new_blk = kzalloc(sizeof(struct msm_disp_state_block), GFP_KERNEL);
172+
173+ va_start(va, fmt);
174+
175+ vaf.fmt = fmt;
176+ vaf.va = &va;
177+ snprintf(new_blk->name, sizeof(new_blk->name), "%pV", &vaf);
178+
179+ va_end(va);
180+
181+ INIT_LIST_HEAD(&new_blk->node);
182+ new_blk->size = ALIGN(len, REG_DUMP_ALIGN);
183+ new_blk->base_addr = base_addr;
184+
185+ msm_disp_state_dump_regs(&new_blk->state, new_blk->size, base_addr);
186+ list_add(&new_blk->node, &disp_state->blocks);
187+}
drivers/gpu/drm/msm/dp/dp_aux.c+78−103
@@ -9,7 +9,15 @@ · 8 unmodified lines
99 #include "dp_reg.h"
1010 #include "dp_aux.h"
1111
12−#define DP_AUX_ENUM_STR(x) #x
12+enum msm_dp_aux_err {
13+ DP_AUX_ERR_NONE,
14+ DP_AUX_ERR_ADDR,
15+ DP_AUX_ERR_TOUT,
16+ DP_AUX_ERR_NACK,
17+ DP_AUX_ERR_DEFER,
18+ DP_AUX_ERR_NACK_DEFER,
19+ DP_AUX_ERR_PHY,
20+};
1321
1422 struct dp_aux_private {
1523 struct device *dev;
@@ -18,7 +26,7 @@ struct dp_aux_private { · 2 unmodified lines
1826 struct mutex mutex;
1927 struct completion comp;
2028
21− u32 aux_error_num;
29+ enum msm_dp_aux_err aux_error_num;
2230 u32 retry_cnt;
2331 bool cmd_busy;
2432 bool native;
@@ -27,69 +35,51 @@ struct dp_aux_private { · 2 unmodified lines
2735 bool no_send_stop;
2836 u32 offset;
2937 u32 segment;
30− u32 isr;
3138
3239 struct drm_dp_aux dp_aux;
3340 };
3441
3542 #define MAX_AUX_RETRIES 5
3643
37−static const char *dp_aux_get_error(u32 aux_error)
38−{
39− switch (aux_error) {
40− case DP_AUX_ERR_NONE:
41− return DP_AUX_ENUM_STR(DP_AUX_ERR_NONE);
42− case DP_AUX_ERR_ADDR:
43− return DP_AUX_ENUM_STR(DP_AUX_ERR_ADDR);
44− case DP_AUX_ERR_TOUT:
45− return DP_AUX_ENUM_STR(DP_AUX_ERR_TOUT);
46− case DP_AUX_ERR_NACK:
47− return DP_AUX_ENUM_STR(DP_AUX_ERR_NACK);
48− case DP_AUX_ERR_DEFER:
49− return DP_AUX_ENUM_STR(DP_AUX_ERR_DEFER);
50− case DP_AUX_ERR_NACK_DEFER:
51− return DP_AUX_ENUM_STR(DP_AUX_ERR_NACK_DEFER);
52− default:
53− return "unknown";
54− }
55−}
56−
57−static u32 dp_aux_write(struct dp_aux_private *aux,
44+static ssize_t dp_aux_write(struct dp_aux_private *aux,
5845 struct drm_dp_aux_msg *msg)
5946 {
60− u32 data[4], reg, len;
47+ u8 data[4];
48+ u32 reg;
49+ ssize_t len;
6150 u8 *msgdata = msg->buffer;
6251 int const AUX_CMD_FIFO_LEN = 128;
6352 int i = 0;
6453
6554 if (aux->read)
66− len = 4;
55+ len = 0;
6756 else
68− len = msg->size + 4;
57+ len = msg->size;
6958
7059 /*
7160 * cmd fifo only has depth of 144 bytes
7261 * limit buf length to 128 bytes here
7362 */
74− if (len > AUX_CMD_FIFO_LEN) {
63+ if (len > AUX_CMD_FIFO_LEN - 4) {
7564 DRM_ERROR("buf size greater than allowed size of 128 bytes\n");
76− return 0;
65+ return -EINVAL;
7766 }
7867
7968 /* Pack cmd and write to HW */
80− data[0] = (msg->address >> 16) & 0xf; /* addr[19:16] */
69+ data[0] = (msg->address >> 16) & 0xf; /* addr[19:16] */
8170 if (aux->read)
82− data[0] |= BIT(4); /* R/W */
71+ data[0] |= BIT(4); /* R/W */
8372
84− data[1] = (msg->address >> 8) & 0xff; /* addr[15:8] */
85− data[2] = msg->address & 0xff; /* addr[7:0] */
86− data[3] = (msg->size - 1) & 0xff; /* len[7:0] */
73+ data[1] = msg->address >> 8; /* addr[15:8] */
74+ data[2] = msg->address; /* addr[7:0] */
75+ data[3] = msg->size - 1; /* len[7:0] */
8776
88− for (i = 0; i < len; i++) {
77+ for (i = 0; i < len + 4; i++) {
8978 reg = (i < 4) ? data[i] : msgdata[i - 4];
79+ reg <<= DP_AUX_DATA_OFFSET;
80+ reg &= DP_AUX_DATA_MASK;
81+ reg |= DP_AUX_DATA_WRITE;
9082 /* index = 0, write */
91− reg = (((reg) << DP_AUX_DATA_OFFSET)
92− & DP_AUX_DATA_MASK) | DP_AUX_DATA_WRITE;
9383 if (i == 0)
9484 reg |= DP_AUX_DATA_INDEX_WRITE;
9585 aux->catalog->aux_data = reg;
@@ -117,39 +107,27 @@ static u32 dp_aux_write(struct dp_aux_private *aux, · 21 unmodified lines
117107 return len;
118108 }
119109
120−static int dp_aux_cmd_fifo_tx(struct dp_aux_private *aux,
110+static ssize_t dp_aux_cmd_fifo_tx(struct dp_aux_private *aux,
121111 struct drm_dp_aux_msg *msg)
122112 {
123− u32 ret, len, timeout;
124− int aux_timeout_ms = HZ/4;
113+ ssize_t ret;
114+ unsigned long time_left;
125115
126116 reinit_completion(&aux->comp);
127117
128− len = dp_aux_write(aux, msg);
129− if (len == 0) {
130− DRM_ERROR("DP AUX write failed\n");
131− return -EINVAL;
132− }
118+ ret = dp_aux_write(aux, msg);
119+ if (ret < 0)
120+ return ret;
133121
134− timeout = wait_for_completion_timeout(&aux->comp, aux_timeout_ms);
135− if (!timeout) {
136− DRM_ERROR("aux %s timeout\n", (aux->read ? "read" : "write"));
122+ time_left = wait_for_completion_timeout(&aux->comp,
123+ msecs_to_jiffies(250));
124+ if (!time_left)
137125 return -ETIMEDOUT;
138− }
139−
140− if (aux->aux_error_num == DP_AUX_ERR_NONE) {
141− ret = len;
142− } else {
143− DRM_ERROR_RATELIMITED("aux err: %s\n",
144− dp_aux_get_error(aux->aux_error_num));
145−
146− ret = -EINVAL;
147− }
148126
149127 return ret;
150128 }
151129
152−static void dp_aux_cmd_fifo_rx(struct dp_aux_private *aux,
130+static ssize_t dp_aux_cmd_fifo_rx(struct dp_aux_private *aux,
153131 struct drm_dp_aux_msg *msg)
154132 {
155133 u32 data;
@@ -176,15 +154,14 @@ static void dp_aux_cmd_fifo_rx(struct dp_aux_private *aux, · 20 unmodified lines
176154
177155 actual_i = (data >> DP_AUX_DATA_INDEX_OFFSET) & 0xFF;
178156 if (i != actual_i)
179− DRM_ERROR("Index mismatch: expected %d, found %d\n",
180− i, actual_i);
157+ break;
181158 }
159+
160+ return i;
182161 }
183162
184−static void dp_aux_native_handler(struct dp_aux_private *aux)
163+static void dp_aux_native_handler(struct dp_aux_private *aux, u32 isr)
185164 {
186− u32 isr = aux->isr;
187−
188165 if (isr & DP_INTR_AUX_I2C_DONE)
189166 aux->aux_error_num = DP_AUX_ERR_NONE;
190167 else if (isr & DP_INTR_WRONG_ADDR)
@@ -197,14 +174,10 @@ static void dp_aux_native_handler(struct dp_aux_private *aux) · 6 unmodified lines
197174 aux->aux_error_num = DP_AUX_ERR_PHY;
198175 dp_catalog_aux_clear_hw_interrupts(aux->catalog);
199176 }
200−
201− complete(&aux->comp);
202177 }
203178
204−static void dp_aux_i2c_handler(struct dp_aux_private *aux)
179+static void dp_aux_i2c_handler(struct dp_aux_private *aux, u32 isr)
205180 {
206− u32 isr = aux->isr;
207−
208181 if (isr & DP_INTR_AUX_I2C_DONE) {
209182 if (isr & (DP_INTR_I2C_NACK | DP_INTR_I2C_DEFER))
210183 aux->aux_error_num = DP_AUX_ERR_NACK;
@@ -226,8 +199,6 @@ static void dp_aux_i2c_handler(struct dp_aux_private *aux) · 15 unmodified lines
226199 dp_catalog_aux_clear_hw_interrupts(aux->catalog);
227200 }
228201 }
229−
230− complete(&aux->comp);
231202 }
232203
233204 static void dp_aux_update_offset_and_segment(struct dp_aux_private *aux,
@@ -338,30 +309,29 @@ static ssize_t dp_aux_transfer(struct drm_dp_aux *dp_aux, · 104 unmodified lines
338309 ssize_t ret;
339310 int const aux_cmd_native_max = 16;
340311 int const aux_cmd_i2c_max = 128;
341− struct dp_aux_private *aux = container_of(dp_aux,
342− struct dp_aux_private, dp_aux);
312+ struct dp_aux_private *aux;
343313
344− mutex_lock(&aux->mutex);
314+ aux = container_of(dp_aux, struct dp_aux_private, dp_aux);
345315
346316 aux->native = msg->request & (DP_AUX_NATIVE_WRITE & DP_AUX_NATIVE_READ);
347317
348318 /* Ignore address only message */
349− if ((msg->size == 0) || (msg->buffer == NULL)) {
319+ if (msg->size == 0 || !msg->buffer) {
350320 msg->reply = aux->native ?
351321 DP_AUX_NATIVE_REPLY_ACK : DP_AUX_I2C_REPLY_ACK;
352− ret = msg->size;
353− goto unlock_exit;
322+ return msg->size;
354323 }
355324
356325 /* msg sanity check */
357− if ((aux->native && (msg->size > aux_cmd_native_max)) ||
358− (msg->size > aux_cmd_i2c_max)) {
326+ if ((aux->native && msg->size > aux_cmd_native_max) ||
327+ msg->size > aux_cmd_i2c_max) {
359328 DRM_ERROR("%s: invalid msg: size(%zu), request(%x)\n",
360329 __func__, msg->size, msg->request);
361− ret = -EINVAL;
362− goto unlock_exit;
330+ return -EINVAL;
363331 }
364332
333+ mutex_lock(&aux->mutex);
334+
365335 dp_aux_update_offset_and_segment(aux, msg);
366336 dp_aux_transfer_helper(aux, msg, true);
367337
@@ -377,41 +347,44 @@ static ssize_t dp_aux_transfer(struct drm_dp_aux *dp_aux, · 9 unmodified lines
377347 }
378348
379349 ret = dp_aux_cmd_fifo_tx(aux, msg);
380−
381350 if (ret < 0) {
382351 if (aux->native) {
383352 aux->retry_cnt++;
384353 if (!(aux->retry_cnt % MAX_AUX_RETRIES))
385354 dp_catalog_aux_update_cfg(aux->catalog);
386355 }
387− usleep_range(400, 500); /* at least 400us to next try */
388− goto unlock_exit;
389− }
390−
391− if (aux->aux_error_num == DP_AUX_ERR_NONE) {
392− if (aux->read)
393− dp_aux_cmd_fifo_rx(aux, msg);
394−
395− msg->reply = aux->native ?
396− DP_AUX_NATIVE_REPLY_ACK : DP_AUX_I2C_REPLY_ACK;
397356 } else {
398− /* Reply defer to retry */
399− msg->reply = aux->native ?
400− DP_AUX_NATIVE_REPLY_DEFER : DP_AUX_I2C_REPLY_DEFER;
357+ aux->retry_cnt = 0;
358+ switch (aux->aux_error_num) {
359+ case DP_AUX_ERR_NONE:
360+ if (aux->read)
361+ ret = dp_aux_cmd_fifo_rx(aux, msg);
362+ msg->reply = aux->native ? DP_AUX_NATIVE_REPLY_ACK : DP_AUX_I2C_REPLY_ACK;
363+ break;
364+ case DP_AUX_ERR_DEFER:
365+ msg->reply = aux->native ? DP_AUX_NATIVE_REPLY_DEFER : DP_AUX_I2C_REPLY_DEFER;
366+ break;
367+ case DP_AUX_ERR_PHY:
368+ case DP_AUX_ERR_ADDR:
369+ case DP_AUX_ERR_NACK:
370+ case DP_AUX_ERR_NACK_DEFER:
371+ msg->reply = aux->native ? DP_AUX_NATIVE_REPLY_NACK : DP_AUX_I2C_REPLY_NACK;
372+ break;
373+ case DP_AUX_ERR_TOUT:
374+ ret = -ETIMEDOUT;
375+ break;
376+ }
401377 }
402378
403− /* Return requested size for success or retry */
404− ret = msg->size;
405− aux->retry_cnt = 0;
406−
407−unlock_exit:
408379 aux->cmd_busy = false;
409380 mutex_unlock(&aux->mutex);
381+
410382 return ret;
411383 }
412384
413385 void dp_aux_isr(struct drm_dp_aux *dp_aux)
414386 {
387+ u32 isr;
415388 struct dp_aux_private *aux;
416389
417390 if (!dp_aux) {
@@ -421,15 +394,17 @@ void dp_aux_isr(struct drm_dp_aux *dp_aux) · 3 unmodified lines
421394
422395 aux = container_of(dp_aux, struct dp_aux_private, dp_aux);
423396
424− aux->isr = dp_catalog_aux_get_irq(aux->catalog);
397+ isr = dp_catalog_aux_get_irq(aux->catalog);
425398
426399 if (!aux->cmd_busy)
427400 return;
428401
429402 if (aux->native)
430− dp_aux_native_handler(aux);
403+ dp_aux_native_handler(aux, isr);
431404 else
432− dp_aux_i2c_handler(aux);
405+ dp_aux_i2c_handler(aux, isr);
406+
407+ complete(&aux->comp);
433408 }
434409
435410 void dp_aux_reconfig(struct drm_dp_aux *dp_aux)
drivers/gpu/drm/msm/dp/dp_aux.h+0−8
@@ -9,14 +9,6 @@ · 8 unmodified lines
99 #include "dp_catalog.h"
1010 #include <drm/drm_dp_helper.h>
1111
12−#define DP_AUX_ERR_NONE 0
13−#define DP_AUX_ERR_ADDR -1
14−#define DP_AUX_ERR_TOUT -2
15−#define DP_AUX_ERR_NACK -3
16−#define DP_AUX_ERR_DEFER -4
17−#define DP_AUX_ERR_NACK_DEFER -5
18−#define DP_AUX_ERR_PHY -6
19−
2012 int dp_aux_register(struct drm_dp_aux *dp_aux);
2113 void dp_aux_unregister(struct drm_dp_aux *dp_aux);
2214 void dp_aux_isr(struct drm_dp_aux *dp_aux);
drivers/gpu/drm/msm/dp/dp_catalog.c+13−5
@@ -62,6 +62,15 @@ struct dp_catalog_private { · 61 unmodified lines
6262 u8 aux_lut_cfg_index[PHY_AUX_CFG_MAX];
6363 };
6464
65+void dp_catalog_snapshot(struct dp_catalog *dp_catalog, struct msm_disp_state *disp_state)
66+{
67+ struct dp_catalog_private *catalog = container_of(dp_catalog,
68+ struct dp_catalog_private, dp_catalog);
69+
70+ msm_disp_snapshot_add_block(disp_state, catalog->io->dp_controller.len,
71+ catalog->io->dp_controller.base, "dp_ctrl");
72+}
73+
6574 static inline u32 dp_read_aux(struct dp_catalog_private *catalog, u32 offset)
6675 {
6776 offset += MSM_DP_CONTROLLER_AUX_OFFSET;
@@ -193,7 +202,7 @@ int dp_catalog_aux_clear_hw_interrupts(struct dp_catalog *dp_catalog) · 125 unmodified lines
193202 /**
194203 * dp_catalog_aux_reset() - reset AUX controller
195204 *
196− * @aux: DP catalog structure
205+ * @dp_catalog: DP catalog structure
197206 *
198207 * return: void
199208 *
@@ -292,7 +301,7 @@ void dp_catalog_dump_regs(struct dp_catalog *dp_catalog) · 92 unmodified lines
292301 dump_regs(catalog->io->dp_controller.base + offset, len);
293302 }
294303
295−int dp_catalog_aux_get_irq(struct dp_catalog *dp_catalog)
304+u32 dp_catalog_aux_get_irq(struct dp_catalog *dp_catalog)
296305 {
297306 struct dp_catalog_private *catalog = container_of(dp_catalog,
298307 struct dp_catalog_private, dp_catalog);
@@ -582,10 +591,9 @@ void dp_catalog_ctrl_hpd_config(struct dp_catalog *dp_catalog) · 283 unmodified lines
582591
583592 u32 reftimer = dp_read_aux(catalog, REG_DP_DP_HPD_REFTIMER);
584593
585− /* enable HPD interrupts */
594+ /* enable HPD plug and unplug interrupts */
586595 dp_catalog_hpd_config_intr(dp_catalog,
587− DP_DP_HPD_PLUG_INT_MASK | DP_DP_IRQ_HPD_INT_MASK
588− | DP_DP_HPD_UNPLUG_INT_MASK | DP_DP_HPD_REPLUG_INT_MASK, true);
596+ DP_DP_HPD_PLUG_INT_MASK | DP_DP_HPD_UNPLUG_INT_MASK, true);
589597
590598 /* Configure REFTIMER and enable it */
591599 reftimer |= DP_DP_HPD_REFTIMER_ENABLE;
drivers/gpu/drm/msm/dp/dp_catalog.h+5−2
@@ -9,6 +9,7 @@ · 8 unmodified lines
99 #include <drm/drm_modes.h>
1010
1111 #include "dp_parser.h"
12+#include "disp/msm_disp_snapshot.h"
1213
1314 /* interrupts */
1415 #define DP_INTR_HPD BIT(0)
@@ -71,6 +72,9 @@ struct dp_catalog { · 56 unmodified lines
7172 u32 audio_data;
7273 };
7374
75+/* Debug module */
76+void dp_catalog_snapshot(struct dp_catalog *dp_catalog, struct msm_disp_state *disp_state);
77+
7478 /* AUX APIs */
7579 u32 dp_catalog_aux_read_data(struct dp_catalog *dp_catalog);
7680 int dp_catalog_aux_write_data(struct dp_catalog *dp_catalog);
@@ -80,7 +84,7 @@ int dp_catalog_aux_clear_hw_interrupts(struct dp_catalog *dp_catalog); · 3 unmodified lines
8084 void dp_catalog_aux_reset(struct dp_catalog *dp_catalog);
8185 void dp_catalog_aux_enable(struct dp_catalog *dp_catalog, bool enable);
8286 void dp_catalog_aux_update_cfg(struct dp_catalog *dp_catalog);
83−int dp_catalog_aux_get_irq(struct dp_catalog *dp_catalog);
87+u32 dp_catalog_aux_get_irq(struct dp_catalog *dp_catalog);
8488
8589 /* DP Controller APIs */
8690 void dp_catalog_ctrl_state_ctrl(struct dp_catalog *dp_catalog, u32 state);
@@ -124,7 +128,6 @@ void dp_catalog_audio_get_header(struct dp_catalog *catalog); · 37 unmodified lines
124128 void dp_catalog_audio_set_header(struct dp_catalog *catalog);
125129 void dp_catalog_audio_config_acr(struct dp_catalog *catalog);
126130 void dp_catalog_audio_enable(struct dp_catalog *catalog);
127−void dp_catalog_audio_enable(struct dp_catalog *catalog);
128131 void dp_catalog_audio_config_sdp(struct dp_catalog *catalog);
129132 void dp_catalog_audio_init(struct dp_catalog *catalog);
130133 void dp_catalog_audio_sfe_level(struct dp_catalog *catalog);
drivers/gpu/drm/msm/dp/dp_ctrl.c+63−24
@@ -77,8 +77,6 @@ struct dp_ctrl_private { · 76 unmodified lines
7777 struct dp_parser *parser;
7878 struct dp_catalog *catalog;
7979
80− struct opp_table *opp_table;
81−
8280 struct completion idle_comp;
8381 struct completion video_comp;
8482 };
@@ -1809,6 +1807,63 @@ end: · 1724 unmodified lines
18091807 return ret;
18101808 }
18111809
1810+int dp_ctrl_off_link_stream(struct dp_ctrl *dp_ctrl)
1811+{
1812+ struct dp_ctrl_private *ctrl;
1813+ struct dp_io *dp_io;
1814+ struct phy *phy;
1815+ int ret;
1816+
1817+ ctrl = container_of(dp_ctrl, struct dp_ctrl_private, dp_ctrl);
1818+ dp_io = &ctrl->parser->io;
1819+ phy = dp_io->phy;
1820+
1821+ /* set dongle to D3 (power off) mode */
1822+ dp_link_psm_config(ctrl->link, &ctrl->panel->link_info, true);
1823+
1824+ dp_catalog_ctrl_mainlink_ctrl(ctrl->catalog, false);
1825+
1826+ if (dp_power_clk_status(ctrl->power, DP_STREAM_PM)) {
1827+ ret = dp_power_clk_enable(ctrl->power, DP_STREAM_PM, false);
1828+ if (ret) {
1829+ DRM_ERROR("Failed to disable pclk. ret=%d\n", ret);
1830+ return ret;
1831+ }
1832+ }
1833+
1834+ ret = dp_power_clk_enable(ctrl->power, DP_CTRL_PM, false);
1835+ if (ret) {
1836+ DRM_ERROR("Failed to disable link clocks. ret=%d\n", ret);
1837+ return ret;
1838+ }
1839+
1840+ phy_power_off(phy);
1841+
1842+ /* aux channel down, reinit phy */
1843+ phy_exit(phy);
1844+ phy_init(phy);
1845+
1846+ DRM_DEBUG_DP("DP off link/stream done\n");
1847+ return ret;
1848+}
1849+
1850+void dp_ctrl_off_phy(struct dp_ctrl *dp_ctrl)
1851+{
1852+ struct dp_ctrl_private *ctrl;
1853+ struct dp_io *dp_io;
1854+ struct phy *phy;
1855+
1856+ ctrl = container_of(dp_ctrl, struct dp_ctrl_private, dp_ctrl);
1857+ dp_io = &ctrl->parser->io;
1858+ phy = dp_io->phy;
1859+
1860+ dp_catalog_ctrl_reset(ctrl->catalog);
1861+
1862+ phy_exit(phy);
1863+
1864+ DRM_DEBUG_DP("DP off phy done\n");
1865+}
1866+
18121867 int dp_ctrl_off(struct dp_ctrl *dp_ctrl)
18131868 {
18141869 struct dp_ctrl_private *ctrl;
@@ -1886,20 +1941,17 @@ struct dp_ctrl *dp_ctrl_get(struct device *dev, struct dp_link *link, · 71 unmodified lines
18861941 return ERR_PTR(-ENOMEM);
18871942 }
18881943
1889− ctrl->opp_table = dev_pm_opp_set_clkname(dev, "ctrl_link");
1890− if (IS_ERR(ctrl->opp_table)) {
1944+ ret = devm_pm_opp_set_clkname(dev, "ctrl_link");
1945+ if (ret) {
18911946 dev_err(dev, "invalid DP OPP table in device tree\n");
1892− /* caller do PTR_ERR(ctrl->opp_table) */
1893− return (struct dp_ctrl *)ctrl->opp_table;
1947+ /* caller do PTR_ERR(opp_table) */
1948+ return (struct dp_ctrl *)ERR_PTR(ret);
18941949 }
18951950
18961951 /* OPP table is optional */
1897− ret = dev_pm_opp_of_add_table(dev);
1898− if (ret) {
1952+ ret = devm_pm_opp_of_add_table(dev);
1953+ if (ret)
18991954 dev_err(dev, "failed to add DP OPP table\n");
1900− dev_pm_opp_put_clkname(ctrl->opp_table);
1901− ctrl->opp_table = NULL;
1902− }
19031955
19041956 init_completion(&ctrl->idle_comp);
19051957 init_completion(&ctrl->video_comp);
@@ -1915,16 +1967,3 @@ struct dp_ctrl *dp_ctrl_get(struct device *dev, struct dp_link *link, · 9 unmodified lines
19151967
19161968 return &ctrl->dp_ctrl;
19171969 }
1918−
1919−void dp_ctrl_put(struct dp_ctrl *dp_ctrl)
1920−{
1921− struct dp_ctrl_private *ctrl;
1922−
1923− ctrl = container_of(dp_ctrl, struct dp_ctrl_private, dp_ctrl);
1924−
1925− if (ctrl->opp_table) {
1926− dev_pm_opp_of_remove_table(ctrl->dev);
1927− dev_pm_opp_put_clkname(ctrl->opp_table);
1928− ctrl->opp_table = NULL;
1929− }
1930−}
drivers/gpu/drm/msm/dp/dp_ctrl.h+2−1
@@ -23,6 +23,8 @@ int dp_ctrl_host_init(struct dp_ctrl *dp_ctrl, bool flip, bool reset); · 22 unmodified lines
2323 void dp_ctrl_host_deinit(struct dp_ctrl *dp_ctrl);
2424 int dp_ctrl_on_link(struct dp_ctrl *dp_ctrl);
2525 int dp_ctrl_on_stream(struct dp_ctrl *dp_ctrl);
26+int dp_ctrl_off_link_stream(struct dp_ctrl *dp_ctrl);
27+void dp_ctrl_off_phy(struct dp_ctrl *dp_ctrl);
2628 int dp_ctrl_off(struct dp_ctrl *dp_ctrl);
2729 void dp_ctrl_push_idle(struct dp_ctrl *dp_ctrl);
2830 void dp_ctrl_isr(struct dp_ctrl *dp_ctrl);
@@ -31,6 +33,5 @@ struct dp_ctrl *dp_ctrl_get(struct device *dev, struct dp_link *link, · 2 unmodified lines
3133 struct dp_panel *panel, struct drm_dp_aux *aux,
3234 struct dp_power *power, struct dp_catalog *catalog,
3335 struct dp_parser *parser);
34−void dp_ctrl_put(struct dp_ctrl *dp_ctrl);
3536
3637 #endif /* _DP_CTRL_H_ */
drivers/gpu/drm/msm/dp/dp_display.c+76−45
@@ -208,10 +208,6 @@ static int dp_display_bind(struct device *dev, struct device *master, · 207 unmodified lines
208208
209209 dp = container_of(g_dp_display,
210210 struct dp_display_private, dp_display);
211− if (!dp) {
212− DRM_ERROR("DP driver bind failed. Invalid driver data\n");
213− return -EINVAL;
214− }
215211
216212 dp->dp_display.drm_dev = drm;
217213 priv = drm->dev_private;
@@ -252,10 +248,6 @@ static void dp_display_unbind(struct device *dev, struct device *master, · 34 unmodified lines
252248
253249 dp = container_of(g_dp_display,
254250 struct dp_display_private, dp_display);
255− if (!dp) {
256− DRM_ERROR("Invalid DP driver data\n");
257− return;
258− }
259251
260252 dp_power_client_deinit(dp->power);
261253 dp_aux_unregister(dp->aux);
@@ -346,6 +338,12 @@ static int dp_display_process_hpd_high(struct dp_display_private *dp) · 84 unmodified lines
346338 dp->dp_display.max_pclk_khz = DP_MAX_PIXEL_CLK_KHZ;
347339 dp->dp_display.max_dp_lanes = dp->parser->max_dp_lanes;
348340
341+ /*
342+ * set sink to normal operation mode -- D0
343+ * before dpcd read
344+ */
345+ dp_link_psm_config(dp->link, &dp->panel->link_info, false);
346+
349347 dp_link_reset_phy_params_vx_px(dp->link);
350348 rc = dp_ctrl_on_link(dp->ctrl);
351349 if (rc) {
@@ -406,19 +404,9 @@ static int dp_display_usbpd_configure_cb(struct device *dev) · 54 unmodified lines
406404
407405 dp = container_of(g_dp_display,
408406 struct dp_display_private, dp_display);
409− if (!dp) {
410− DRM_ERROR("no driver data found\n");
411− rc = -ENODEV;
412− goto end;
413− }
414407
415408 dp_display_host_init(dp, false);
416409
417− /*
418− * set sink to normal operation mode -- D0
419− * before dpcd read
420− */
421− dp_link_psm_config(dp->link, &dp->panel->link_info, false);
422410 rc = dp_display_process_hpd_high(dp);
423411 end:
424412 return rc;
@@ -437,11 +425,6 @@ static int dp_display_usbpd_disconnect_cb(struct device *dev) · 12 unmodified lines
437425
438426 dp = container_of(g_dp_display,
439427 struct dp_display_private, dp_display);
440− if (!dp) {
441− DRM_ERROR("no driver data found\n");
442− rc = -ENODEV;
443− return rc;
444− }
445428
446429 dp_add_event(dp, EV_USER_NOTIFICATION, false, 0);
447430
@@ -502,7 +485,6 @@ static int dp_display_usbpd_attention_cb(struct device *dev) · 54 unmodified lines
502485 int rc = 0;
503486 u32 sink_request;
504487 struct dp_display_private *dp;
505− struct dp_usbpd *hpd;
506488
507489 if (!dev) {
508490 DRM_ERROR("invalid dev\n");
@@ -511,12 +493,6 @@ static int dp_display_usbpd_attention_cb(struct device *dev) · 2 unmodified lines
511493
512494 dp = container_of(g_dp_display,
513495 struct dp_display_private, dp_display);
514− if (!dp) {
515− DRM_ERROR("no driver data found\n");
516− return -ENODEV;
517− }
518−
519− hpd = dp->usbpd;
520496
521497 /* check for any test request issued by sink */
522498 rc = dp_link_process_request(dp->link);
@@ -579,6 +555,10 @@ static int dp_hpd_plug_handle(struct dp_display_private *dp, u32 data) · 56 unmodified lines
579555 dp_add_event(dp, EV_CONNECT_PENDING_TIMEOUT, 0, tout);
580556 }
581557
558+ /* enable HDP irq_hpd/replug interrupt */
559+ dp_catalog_hpd_config_intr(dp->catalog,
560+ DP_DP_IRQ_HPD_INT_MASK | DP_DP_HPD_REPLUG_INT_MASK, true);
561+
582562 mutex_unlock(&dp->event_mutex);
583563
584564 /* uevent will complete connection part */
@@ -628,7 +608,26 @@ static int dp_hpd_unplug_handle(struct dp_display_private *dp, u32 data) · 43 unmodified lines
628608 mutex_lock(&dp->event_mutex);
629609
630610 state = dp->hpd_state;
631− if (state == ST_DISCONNECT_PENDING || state == ST_DISCONNECTED) {
611+
612+ /* disable irq_hpd/replug interrupts */
613+ dp_catalog_hpd_config_intr(dp->catalog,
614+ DP_DP_IRQ_HPD_INT_MASK | DP_DP_HPD_REPLUG_INT_MASK, false);
615+
616+ /* unplugged, no more irq_hpd handle */
617+ dp_del_event(dp, EV_IRQ_HPD_INT);
618+
619+ if (state == ST_DISCONNECTED) {
620+ /* triggered by irq_hdp with sink_count = 0 */
621+ if (dp->link->sink_count == 0) {
622+ dp_ctrl_off_phy(dp->ctrl);
623+ hpd->hpd_high = 0;
624+ dp->core_initialized = false;
625+ }
626+ mutex_unlock(&dp->event_mutex);
627+ return 0;
628+ }
629+
630+ if (state == ST_DISCONNECT_PENDING) {
632631 mutex_unlock(&dp->event_mutex);
633632 return 0;
634633 }
@@ -642,9 +641,8 @@ static int dp_hpd_unplug_handle(struct dp_display_private *dp, u32 data) · 7 unmodified lines
642641
643642 dp->hpd_state = ST_DISCONNECT_PENDING;
644643
645− /* disable HPD plug interrupt until disconnect is done */
646− dp_catalog_hpd_config_intr(dp->catalog, DP_DP_HPD_PLUG_INT_MASK
647− | DP_DP_IRQ_HPD_INT_MASK, false);
644+ /* disable HPD plug interrupts */
645+ dp_catalog_hpd_config_intr(dp->catalog, DP_DP_HPD_PLUG_INT_MASK, false);
648646
649647 hpd->hpd_high = 0;
650648
@@ -660,8 +658,8 @@ static int dp_hpd_unplug_handle(struct dp_display_private *dp, u32 data) · 9 unmodified lines
660658 /* signal the disconnect event early to ensure proper teardown */
661659 dp_display_handle_plugged_change(g_dp_display, false);
662660
663− dp_catalog_hpd_config_intr(dp->catalog, DP_DP_HPD_PLUG_INT_MASK |
664− DP_DP_IRQ_HPD_INT_MASK, true);
661+ /* enable HDP plug interrupt to prepare for next plugin */
662+ dp_catalog_hpd_config_intr(dp->catalog, DP_DP_HPD_PLUG_INT_MASK, true);
665663
666664 /* uevent will complete disconnection part */
667665 mutex_unlock(&dp->event_mutex);
@@ -692,7 +690,7 @@ static int dp_irq_hpd_handle(struct dp_display_private *dp, u32 data) · 24 unmodified lines
692690
693691 /* irq_hpd can happen at either connected or disconnected state */
694692 state = dp->hpd_state;
695− if (state == ST_DISPLAY_OFF) {
693+ if (state == ST_DISPLAY_OFF || state == ST_SUSPENDED) {
696694 mutex_unlock(&dp->event_mutex);
697695 return 0;
698696 }
@@ -724,7 +722,6 @@ static int dp_irq_hpd_handle(struct dp_display_private *dp, u32 data) · 25 unmodified lines
724722 static void dp_display_deinit_sub_modules(struct dp_display_private *dp)
725723 {
726724 dp_debug_put(dp->debug);
727− dp_ctrl_put(dp->ctrl);
728725 dp_panel_put(dp->panel);
729726 dp_aux_put(dp->aux);
730727 dp_audio_put(dp->audio);
@@ -818,13 +815,11 @@ static int dp_init_sub_modules(struct dp_display_private *dp) · 87 unmodified lines
818815 rc = PTR_ERR(dp->audio);
819816 pr_err("failed to initialize audio, rc = %d\n", rc);
820817 dp->audio = NULL;
821− goto error_audio;
818+ goto error_ctrl;
822819 }
823820
824821 return rc;
825822
826−error_audio:
827− dp_ctrl_put(dp->ctrl);
828823 error_ctrl:
829824 dp_panel_put(dp->panel);
830825 error_link:
@@ -910,9 +905,13 @@ static int dp_display_disable(struct dp_display_private *dp, u32 data) · 79 unmodified lines
910905
911906 dp_display->audio_enabled = false;
912907
913− dp_ctrl_off(dp->ctrl);
914−
915− dp->core_initialized = false;
908+ /* triggered by irq_hpd with sink_count = 0 */
909+ if (dp->link->sink_count == 0) {
910+ dp_ctrl_off_link_stream(dp->ctrl);
911+ } else {
912+ dp_ctrl_off(dp->ctrl);
913+ dp->core_initialized = false;
914+ }
916915
917916 dp_display->power_on = false;
918917
@@ -1012,6 +1011,33 @@ int dp_display_get_test_bpp(struct msm_dp *dp) · 93 unmodified lines
10121011 dp_display->link->test_video.test_bit_depth);
10131012 }
10141013
1014+void msm_dp_snapshot(struct msm_disp_state *disp_state, struct msm_dp *dp)
1015+{
1016+ struct dp_display_private *dp_display;
1017+ struct drm_device *drm;
1018+
1019+ dp_display = container_of(dp, struct dp_display_private, dp_display);
1020+ drm = dp->drm_dev;
1021+
1022+ /*
1023+ * if we are reading registers we need the link clocks to be on
1024+ * however till DP cable is connected this will not happen as we
1025+ * do not know the resolution to power up with. Hence check the
1026+ * power_on status before dumping DP registers to avoid crash due
1027+ * to unclocked access
1028+ */
1029+ mutex_lock(&dp_display->event_mutex);
1030+
1031+ if (!dp->power_on) {
1032+ mutex_unlock(&dp_display->event_mutex);
1033+ return;
1034+ }
1035+
1036+ dp_catalog_snapshot(dp_display->catalog, disp_state);
1037+
1038+ mutex_unlock(&dp_display->event_mutex);
1039+}
1040+
10151041 static void dp_display_config_hpd(struct dp_display_private *dp)
10161042 {
10171043
@@ -1300,8 +1326,13 @@ static int dp_pm_suspend(struct device *dev) · 282 unmodified lines
13001326
13011327 mutex_lock(&dp->event_mutex);
13021328
1303− if (dp->core_initialized == true)
1329+ if (dp->core_initialized == true) {
1330+ /* mainlink enabled */
1331+ if (dp_power_clk_status(dp->power, DP_CTRL_PM))
1332+ dp_ctrl_off_link_stream(dp->ctrl);
1333+
13041334 dp_display_host_deinit(dp);
1335+ }
13051336
13061337 dp->hpd_state = ST_SUSPENDED;
13071338
drivers/gpu/drm/msm/dp/dp_display.h+1−0
@@ -8,6 +8,7 @@ · 7 unmodified lines
88
99 #include "dp_panel.h"
1010 #include <sound/hdmi-codec.h>
11+#include "disp/msm_disp_snapshot.h"
1112
1213 struct msm_dp {
1314 struct drm_device *drm_dev;
drivers/gpu/drm/msm/dp/dp_link.c+6−15
@@ -364,7 +364,7 @@ static int dp_link_parse_timing_params3(struct dp_link_private *link, · 363 unmodified lines
364364 }
365365
366366 /**
367− * dp_parse_video_pattern_params() - parses video pattern parameters from DPCD
367+ * dp_link_parse_video_pattern_params() - parses video pattern parameters from DPCD
368368 * @link: Display Port Driver data
369369 *
370370 * Returns 0 if it successfully parses the video link pattern and the link
@@ -563,7 +563,7 @@ static int dp_link_parse_link_training_params(struct dp_link_private *link) · 192 unmodified lines
563563 }
564564
565565 /**
566− * dp_parse_phy_test_params() - parses the phy link parameters
566+ * dp_link_parse_phy_test_params() - parses the phy link parameters
567567 * @link: Display Port Driver data
568568 *
569569 * Parses the DPCD (Byte 0x248) for the DP PHY link pattern that is being
@@ -843,10 +843,8 @@ bool dp_link_send_edid_checksum(struct dp_link *dp_link, u8 checksum) · 273 unmodified lines
843843 return ret == 1;
844844 }
845845
846−static int dp_link_parse_vx_px(struct dp_link_private *link)
846+static void dp_link_parse_vx_px(struct dp_link_private *link)
847847 {
848− int ret = 0;
849−
850848 DRM_DEBUG_DP("vx: 0=%d, 1=%d, 2=%d, 3=%d\n",
851849 drm_dp_get_adjust_request_voltage(link->link_status, 0),
852850 drm_dp_get_adjust_request_voltage(link->link_status, 1),
@@ -876,8 +874,6 @@ static int dp_link_parse_vx_px(struct dp_link_private *link) · 23 unmodified lines
876874 DRM_DEBUG_DP("Requested: v_level = 0x%x, p_level = 0x%x\n",
877875 link->dp_link.phy_params.v_level,
878876 link->dp_link.phy_params.p_level);
879−
880− return ret;
881877 }
882878
883879 /**
@@ -891,8 +887,6 @@ static int dp_link_parse_vx_px(struct dp_link_private *link) · 7 unmodified lines
891887 static int dp_link_process_phy_test_pattern_request(
892888 struct dp_link_private *link)
893889 {
894− int ret = 0;
895−
896890 if (!(link->request.test_requested & DP_TEST_LINK_PHY_TEST_PATTERN)) {
897891 DRM_DEBUG_DP("no phy test\n");
898892 return -EINVAL;
@@ -918,12 +912,9 @@ static int dp_link_process_phy_test_pattern_request( · 19 unmodified lines
918912 link->dp_link.link_params.rate =
919913 drm_dp_bw_code_to_link_rate(link->request.test_link_rate);
920914
921− ret = dp_link_parse_vx_px(link);
922−
923− if (ret)
924− DRM_ERROR("parse_vx_px failed. ret=%d\n", ret);
915+ dp_link_parse_vx_px(link);
925916
926− return ret;
917+ return 0;
927918 }
928919
929920 static u8 get_link_status(const u8 link_status[DP_LINK_STATUS_SIZE], int r)
@@ -961,7 +952,7 @@ static int dp_link_process_link_status_update(struct dp_link_private *link) · 31 unmodified lines
961952 }
962953
963954 /**
964− * dp_link_process_downstream_port_status_change() - process port status changes
955+ * dp_link_process_ds_port_status_change() - process port status changes
965956 * @link: Display Port Driver data
966957 *
967958 * This function will handle downstream port updates that are initiated by
drivers/gpu/drm/msm/dp/dp_panel.c+1−3
@@ -141,7 +141,6 @@ static int dp_panel_update_modes(struct drm_connector *connector, · 140 unmodified lines
141141 return rc;
142142 }
143143 rc = drm_add_edid_modes(connector, edid);
144− DRM_DEBUG_DP("%s -", __func__);
145144 return rc;
146145 }
147146
@@ -351,7 +350,6 @@ void dp_panel_dump_regs(struct dp_panel *dp_panel) · 203 unmodified lines
351350
352351 int dp_panel_timing_cfg(struct dp_panel *dp_panel)
353352 {
354− int rc = 0;
355353 u32 data, total_ver, total_hor;
356354 struct dp_catalog *catalog;
357355 struct dp_panel_private *panel;
@@ -404,7 +402,7 @@ int dp_panel_timing_cfg(struct dp_panel *dp_panel) · 46 unmodified lines
404402 dp_catalog_panel_timing_cfg(catalog);
405403 panel->panel_on = true;
406404
407− return rc;
405+ return 0;
408406 }
409407
410408 int dp_panel_init_panel_info(struct dp_panel *dp_panel)
drivers/gpu/drm/msm/dp/dp_power.h+2−2
@@ -88,7 +88,7 @@ int dp_power_client_init(struct dp_power *power); · 87 unmodified lines
8888 * return: 0 for success, error for failure.
8989 *
9090 * This API will de-initialize the DisplayPort's clocks and regulator
91− * modueles.
91+ * modules.
9292 */
9393 void dp_power_client_deinit(struct dp_power *power);
9494
@@ -100,7 +100,7 @@ void dp_power_client_deinit(struct dp_power *power); · 5 unmodified lines
100100 *
101101 * This API will configure the DisplayPort's power module and provides
102102 * methods to be called by the client to configure the power related
103− * modueles.
103+ * modules.
104104 */
105105 struct dp_power *dp_power_get(struct device *dev, struct dp_parser *parser);
106106
drivers/gpu/drm/msm/dsi/dsi.c+6−0
@@ -266,3 +266,9 @@ fail: · 265 unmodified lines
266266 return ret;
267267 }
268268
269+void msm_dsi_snapshot(struct msm_disp_state *disp_state, struct msm_dsi *msm_dsi)
270+{
271+ msm_dsi_host_snapshot(disp_state, msm_dsi->host);
272+ msm_dsi_phy_snapshot(disp_state, msm_dsi->phy);
273+}
274+
drivers/gpu/drm/msm/dsi/dsi.h+3−1
@@ -15,6 +15,7 @@ · 14 unmodified lines
1515 #include <drm/drm_panel.h>
1616
1717 #include "msm_drv.h"
18+#include "disp/msm_disp_snapshot.h"
1819
1920 #define DSI_0 0
2021 #define DSI_1 1
@@ -146,7 +147,7 @@ int dsi_clk_init_v2(struct msm_dsi_host *msm_host); · 125 unmodified lines
146147 int dsi_clk_init_6g_v2(struct msm_dsi_host *msm_host);
147148 int dsi_calc_clk_rate_v2(struct msm_dsi_host *msm_host, bool is_dual_dsi);
148149 int dsi_calc_clk_rate_6g(struct msm_dsi_host *msm_host, bool is_dual_dsi);
149−
150+void msm_dsi_host_snapshot(struct msm_disp_state *disp_state, struct mipi_dsi_host *host);
150151 /* dsi phy */
151152 struct msm_dsi_phy;
152153 struct msm_dsi_phy_shared_timings {
@@ -173,6 +174,7 @@ int msm_dsi_phy_get_clk_provider(struct msm_dsi_phy *phy, · 20 unmodified lines
173174 struct clk **byte_clk_provider, struct clk **pixel_clk_provider);
174175 void msm_dsi_phy_pll_save_state(struct msm_dsi_phy *phy);
175176 int msm_dsi_phy_pll_restore_state(struct msm_dsi_phy *phy);
177+void msm_dsi_phy_snapshot(struct msm_disp_state *disp_state, struct msm_dsi_phy *phy);
176178
177179 #endif /* __DSI_CONNECTOR_H__ */
178180
drivers/gpu/drm/msm/dsi/dsi.xml.h+22−1700
@@ -8,19 +8,27 @@ http://github.com/freedreno/envytools/ · 7 unmodified lines
88 git clone https://github.com/freedreno/envytools.git
99
1010 The rules-ng-ng source files this header was generated from are:
11−- /home/robclark/src/envytools/rnndb/msm.xml ( 676 bytes, from 2020-07-23 21:58:14)
12−- /home/robclark/src/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2020-07-23 21:58:14)
13−- /home/robclark/src/envytools/rnndb/mdp/mdp4.xml ( 20915 bytes, from 2020-07-23 21:58:14)
14−- /home/robclark/src/envytools/rnndb/mdp/mdp_common.xml ( 2849 bytes, from 2020-07-23 21:58:14)
15−- /home/robclark/src/envytools/rnndb/mdp/mdp5.xml ( 37411 bytes, from 2020-07-23 21:58:14)
16−- /home/robclark/src/envytools/rnndb/dsi/dsi.xml ( 42301 bytes, from 2020-07-23 21:58:14)
17−- /home/robclark/src/envytools/rnndb/dsi/sfpb.xml ( 602 bytes, from 2020-07-23 21:58:14)
18−- /home/robclark/src/envytools/rnndb/dsi/mmss_cc.xml ( 1686 bytes, from 2020-07-23 21:58:14)
19−- /home/robclark/src/envytools/rnndb/hdmi/qfprom.xml ( 600 bytes, from 2020-07-23 21:58:14)
20−- /home/robclark/src/envytools/rnndb/hdmi/hdmi.xml ( 41874 bytes, from 2020-07-23 21:58:14)
21−- /home/robclark/src/envytools/rnndb/edp/edp.xml ( 10416 bytes, from 2020-07-23 21:58:14)
22−
23−Copyright (C) 2013-2020 by the following authors:
11+- /home/robclark/src/mesa/mesa/src/freedreno/registers/msm.xml ( 981 bytes, from 2021-06-05 21:37:42)
12+- /home/robclark/src/mesa/mesa/src/freedreno/registers/freedreno_copyright.xml ( 1572 bytes, from 2021-02-18 16:45:44)
13+- /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp4.xml ( 20912 bytes, from 2021-02-18 16:45:44)
14+- /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp_common.xml ( 2849 bytes, from 2021-02-18 16:45:44)
15+- /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp5.xml ( 37461 bytes, from 2021-02-18 16:45:44)
16+- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi.xml ( 15291 bytes, from 2021-06-15 22:36:13)
17+- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_v2.xml ( 3236 bytes, from 2021-06-05 21:37:42)
18+- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_28nm_8960.xml ( 4935 bytes, from 2021-05-21 19:18:08)
19+- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_28nm.xml ( 7004 bytes, from 2021-05-21 19:18:08)
20+- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_20nm.xml ( 3712 bytes, from 2021-05-21 19:18:08)
21+- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_14nm.xml ( 5381 bytes, from 2021-05-21 19:18:08)
22+- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_10nm.xml ( 4499 bytes, from 2021-05-21 19:18:08)
23+- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_7nm.xml ( 10953 bytes, from 2021-05-21 19:18:08)
24+- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_5nm.xml ( 10900 bytes, from 2021-05-21 19:18:08)
25+- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/sfpb.xml ( 602 bytes, from 2021-02-18 16:45:44)
26+- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/mmss_cc.xml ( 1686 bytes, from 2021-02-18 16:45:44)
27+- /home/robclark/src/mesa/mesa/src/freedreno/registers/hdmi/qfprom.xml ( 600 bytes, from 2021-02-18 16:45:44)
28+- /home/robclark/src/mesa/mesa/src/freedreno/registers/hdmi/hdmi.xml ( 41874 bytes, from 2021-02-18 16:45:44)
29+- /home/robclark/src/mesa/mesa/src/freedreno/registers/edp/edp.xml ( 10416 bytes, from 2021-02-18 16:45:44)
30+
31+Copyright (C) 2013-2021 by the following authors:
2432 - Rob Clark <robdclark@gmail.com> (robclark)
2533 - Ilia Mirkin <imirkin@alum.mit.edu> (imirkin)
2634
@@ -621,1693 +629,7 @@ static inline uint32_t DSI_VERSION_MAJOR(uint32_t val) · 594 unmodified lines
621629 return ((val) << DSI_VERSION_MAJOR__SHIFT) & DSI_VERSION_MAJOR__MASK;
622630 }
623631
624−#define REG_DSI_PHY_PLL_CTRL_0 0x00000200
625−#define DSI_PHY_PLL_CTRL_0_ENABLE 0x00000001
626−
627−#define REG_DSI_PHY_PLL_CTRL_1 0x00000204
628−
629−#define REG_DSI_PHY_PLL_CTRL_2 0x00000208
630−
631−#define REG_DSI_PHY_PLL_CTRL_3 0x0000020c
632−
633−#define REG_DSI_PHY_PLL_CTRL_4 0x00000210
634−
635−#define REG_DSI_PHY_PLL_CTRL_5 0x00000214
636−
637−#define REG_DSI_PHY_PLL_CTRL_6 0x00000218
638−
639−#define REG_DSI_PHY_PLL_CTRL_7 0x0000021c
640−
641−#define REG_DSI_PHY_PLL_CTRL_8 0x00000220
642−
643−#define REG_DSI_PHY_PLL_CTRL_9 0x00000224
644−
645−#define REG_DSI_PHY_PLL_CTRL_10 0x00000228
646−
647−#define REG_DSI_PHY_PLL_CTRL_11 0x0000022c
648−
649−#define REG_DSI_PHY_PLL_CTRL_12 0x00000230
650−
651−#define REG_DSI_PHY_PLL_CTRL_13 0x00000234
652−
653−#define REG_DSI_PHY_PLL_CTRL_14 0x00000238
654−
655−#define REG_DSI_PHY_PLL_CTRL_15 0x0000023c
656−
657−#define REG_DSI_PHY_PLL_CTRL_16 0x00000240
658−
659−#define REG_DSI_PHY_PLL_CTRL_17 0x00000244
660−
661−#define REG_DSI_PHY_PLL_CTRL_18 0x00000248
662−
663−#define REG_DSI_PHY_PLL_CTRL_19 0x0000024c
664−
665−#define REG_DSI_PHY_PLL_CTRL_20 0x00000250
666−
667−#define REG_DSI_PHY_PLL_STATUS 0x00000280
668−#define DSI_PHY_PLL_STATUS_PLL_BUSY 0x00000001
669−
670−#define REG_DSI_8x60_PHY_TPA_CTRL_1 0x00000258
671−
672−#define REG_DSI_8x60_PHY_TPA_CTRL_2 0x0000025c
673−
674−#define REG_DSI_8x60_PHY_TIMING_CTRL_0 0x00000260
675−
676−#define REG_DSI_8x60_PHY_TIMING_CTRL_1 0x00000264
677−
678−#define REG_DSI_8x60_PHY_TIMING_CTRL_2 0x00000268
679−
680−#define REG_DSI_8x60_PHY_TIMING_CTRL_3 0x0000026c
681−
682−#define REG_DSI_8x60_PHY_TIMING_CTRL_4 0x00000270
683−
684−#define REG_DSI_8x60_PHY_TIMING_CTRL_5 0x00000274
685−
686−#define REG_DSI_8x60_PHY_TIMING_CTRL_6 0x00000278
687−
688−#define REG_DSI_8x60_PHY_TIMING_CTRL_7 0x0000027c
689−
690−#define REG_DSI_8x60_PHY_TIMING_CTRL_8 0x00000280
691−
692−#define REG_DSI_8x60_PHY_TIMING_CTRL_9 0x00000284
693−
694−#define REG_DSI_8x60_PHY_TIMING_CTRL_10 0x00000288
695−
696−#define REG_DSI_8x60_PHY_TIMING_CTRL_11 0x0000028c
697−
698−#define REG_DSI_8x60_PHY_CTRL_0 0x00000290
699−
700−#define REG_DSI_8x60_PHY_CTRL_1 0x00000294
701−
702−#define REG_DSI_8x60_PHY_CTRL_2 0x00000298
703−
704−#define REG_DSI_8x60_PHY_CTRL_3 0x0000029c
705−
706−#define REG_DSI_8x60_PHY_STRENGTH_0 0x000002a0
707−
708−#define REG_DSI_8x60_PHY_STRENGTH_1 0x000002a4
709−
710−#define REG_DSI_8x60_PHY_STRENGTH_2 0x000002a8
711−
712−#define REG_DSI_8x60_PHY_STRENGTH_3 0x000002ac
713−
714−#define REG_DSI_8x60_PHY_REGULATOR_CTRL_0 0x000002cc
715−
716−#define REG_DSI_8x60_PHY_REGULATOR_CTRL_1 0x000002d0
717−
718−#define REG_DSI_8x60_PHY_REGULATOR_CTRL_2 0x000002d4
719−
720−#define REG_DSI_8x60_PHY_REGULATOR_CTRL_3 0x000002d8
721−
722−#define REG_DSI_8x60_PHY_REGULATOR_CTRL_4 0x000002dc
723−
724−#define REG_DSI_8x60_PHY_CAL_HW_TRIGGER 0x000000f0
725−
726−#define REG_DSI_8x60_PHY_CAL_CTRL 0x000000f4
727−
728−#define REG_DSI_8x60_PHY_CAL_STATUS 0x000000fc
729−#define DSI_8x60_PHY_CAL_STATUS_CAL_BUSY 0x10000000
730−
731−static inline uint32_t REG_DSI_28nm_8960_PHY_LN(uint32_t i0) { return 0x00000000 + 0x40*i0; }
732−
733−static inline uint32_t REG_DSI_28nm_8960_PHY_LN_CFG_0(uint32_t i0) { return 0x00000000 + 0x40*i0; }
734−
735−static inline uint32_t REG_DSI_28nm_8960_PHY_LN_CFG_1(uint32_t i0) { return 0x00000004 + 0x40*i0; }
736−
737−static inline uint32_t REG_DSI_28nm_8960_PHY_LN_CFG_2(uint32_t i0) { return 0x00000008 + 0x40*i0; }
738−
739−static inline uint32_t REG_DSI_28nm_8960_PHY_LN_TEST_DATAPATH(uint32_t i0) { return 0x0000000c + 0x40*i0; }
740−
741−static inline uint32_t REG_DSI_28nm_8960_PHY_LN_TEST_STR_0(uint32_t i0) { return 0x00000014 + 0x40*i0; }
742−
743−static inline uint32_t REG_DSI_28nm_8960_PHY_LN_TEST_STR_1(uint32_t i0) { return 0x00000018 + 0x40*i0; }
744−
745−#define REG_DSI_28nm_8960_PHY_LNCK_CFG_0 0x00000100
746−
747−#define REG_DSI_28nm_8960_PHY_LNCK_CFG_1 0x00000104
748−
749−#define REG_DSI_28nm_8960_PHY_LNCK_CFG_2 0x00000108
750−
751−#define REG_DSI_28nm_8960_PHY_LNCK_TEST_DATAPATH 0x0000010c
752−
753−#define REG_DSI_28nm_8960_PHY_LNCK_TEST_STR0 0x00000114
754−
755−#define REG_DSI_28nm_8960_PHY_LNCK_TEST_STR1 0x00000118
756−
757−#define REG_DSI_28nm_8960_PHY_TIMING_CTRL_0 0x00000140
758−#define DSI_28nm_8960_PHY_TIMING_CTRL_0_CLK_ZERO__MASK 0x000000ff
759−#define DSI_28nm_8960_PHY_TIMING_CTRL_0_CLK_ZERO__SHIFT 0
760−static inline uint32_t DSI_28nm_8960_PHY_TIMING_CTRL_0_CLK_ZERO(uint32_t val)
761−{
762− return ((val) << DSI_28nm_8960_PHY_TIMING_CTRL_0_CLK_ZERO__SHIFT) & DSI_28nm_8960_PHY_TIMING_CTRL_0_CLK_ZERO__MASK;
763−}
764−
765−#define REG_DSI_28nm_8960_PHY_TIMING_CTRL_1 0x00000144
766−#define DSI_28nm_8960_PHY_TIMING_CTRL_1_CLK_TRAIL__MASK 0x000000ff
767−#define DSI_28nm_8960_PHY_TIMING_CTRL_1_CLK_TRAIL__SHIFT 0
768−static inline uint32_t DSI_28nm_8960_PHY_TIMING_CTRL_1_CLK_TRAIL(uint32_t val)
769−{
770− return ((val) << DSI_28nm_8960_PHY_TIMING_CTRL_1_CLK_TRAIL__SHIFT) & DSI_28nm_8960_PHY_TIMING_CTRL_1_CLK_TRAIL__MASK;
771−}
772−
773−#define REG_DSI_28nm_8960_PHY_TIMING_CTRL_2 0x00000148
774−#define DSI_28nm_8960_PHY_TIMING_CTRL_2_CLK_PREPARE__MASK 0x000000ff
775−#define DSI_28nm_8960_PHY_TIMING_CTRL_2_CLK_PREPARE__SHIFT 0
776−static inline uint32_t DSI_28nm_8960_PHY_TIMING_CTRL_2_CLK_PREPARE(uint32_t val)
777−{
778− return ((val) << DSI_28nm_8960_PHY_TIMING_CTRL_2_CLK_PREPARE__SHIFT) & DSI_28nm_8960_PHY_TIMING_CTRL_2_CLK_PREPARE__MASK;
779−}
780−
781−#define REG_DSI_28nm_8960_PHY_TIMING_CTRL_3 0x0000014c
782−
783−#define REG_DSI_28nm_8960_PHY_TIMING_CTRL_4 0x00000150
784−#define DSI_28nm_8960_PHY_TIMING_CTRL_4_HS_EXIT__MASK 0x000000ff
785−#define DSI_28nm_8960_PHY_TIMING_CTRL_4_HS_EXIT__SHIFT 0
786−static inline uint32_t DSI_28nm_8960_PHY_TIMING_CTRL_4_HS_EXIT(uint32_t val)
787−{
788− return ((val) << DSI_28nm_8960_PHY_TIMING_CTRL_4_HS_EXIT__SHIFT) & DSI_28nm_8960_PHY_TIMING_CTRL_4_HS_EXIT__MASK;
789−}
790−
791−#define REG_DSI_28nm_8960_PHY_TIMING_CTRL_5 0x00000154
792−#define DSI_28nm_8960_PHY_TIMING_CTRL_5_HS_ZERO__MASK 0x000000ff
793−#define DSI_28nm_8960_PHY_TIMING_CTRL_5_HS_ZERO__SHIFT 0
794−static inline uint32_t DSI_28nm_8960_PHY_TIMING_CTRL_5_HS_ZERO(uint32_t val)
795−{
796− return ((val) << DSI_28nm_8960_PHY_TIMING_CTRL_5_HS_ZERO__SHIFT) & DSI_28nm_8960_PHY_TIMING_CTRL_5_HS_ZERO__MASK;
797−}
798−
799−#define REG_DSI_28nm_8960_PHY_TIMING_CTRL_6 0x00000158
800−#define DSI_28nm_8960_PHY_TIMING_CTRL_6_HS_PREPARE__MASK 0x000000ff
801−#define DSI_28nm_8960_PHY_TIMING_CTRL_6_HS_PREPARE__SHIFT 0
802−static inline uint32_t DSI_28nm_8960_PHY_TIMING_CTRL_6_HS_PREPARE(uint32_t val)
803−{
804− return ((val) << DSI_28nm_8960_PHY_TIMING_CTRL_6_HS_PREPARE__SHIFT) & DSI_28nm_8960_PHY_TIMING_CTRL_6_HS_PREPARE__MASK;
805−}
806−
807−#define REG_DSI_28nm_8960_PHY_TIMING_CTRL_7 0x0000015c
808−#define DSI_28nm_8960_PHY_TIMING_CTRL_7_HS_TRAIL__MASK 0x000000ff
809−#define DSI_28nm_8960_PHY_TIMING_CTRL_7_HS_TRAIL__SHIFT 0
810−static inline uint32_t DSI_28nm_8960_PHY_TIMING_CTRL_7_HS_TRAIL(uint32_t val)
811−{
812− return ((val) << DSI_28nm_8960_PHY_TIMING_CTRL_7_HS_TRAIL__SHIFT) & DSI_28nm_8960_PHY_TIMING_CTRL_7_HS_TRAIL__MASK;
813−}
814−
815−#define REG_DSI_28nm_8960_PHY_TIMING_CTRL_8 0x00000160
816−#define DSI_28nm_8960_PHY_TIMING_CTRL_8_HS_RQST__MASK 0x000000ff
817−#define DSI_28nm_8960_PHY_TIMING_CTRL_8_HS_RQST__SHIFT 0
818−static inline uint32_t DSI_28nm_8960_PHY_TIMING_CTRL_8_HS_RQST(uint32_t val)
819−{
820− return ((val) << DSI_28nm_8960_PHY_TIMING_CTRL_8_HS_RQST__SHIFT) & DSI_28nm_8960_PHY_TIMING_CTRL_8_HS_RQST__MASK;
821−}
822−
823−#define REG_DSI_28nm_8960_PHY_TIMING_CTRL_9 0x00000164
824−#define DSI_28nm_8960_PHY_TIMING_CTRL_9_TA_GO__MASK 0x00000007
825−#define DSI_28nm_8960_PHY_TIMING_CTRL_9_TA_GO__SHIFT 0
826−static inline uint32_t DSI_28nm_8960_PHY_TIMING_CTRL_9_TA_GO(uint32_t val)
827−{
828− return ((val) << DSI_28nm_8960_PHY_TIMING_CTRL_9_TA_GO__SHIFT) & DSI_28nm_8960_PHY_TIMING_CTRL_9_TA_GO__MASK;
829−}
830−#define DSI_28nm_8960_PHY_TIMING_CTRL_9_TA_SURE__MASK 0x00000070
831−#define DSI_28nm_8960_PHY_TIMING_CTRL_9_TA_SURE__SHIFT 4
832−static inline uint32_t DSI_28nm_8960_PHY_TIMING_CTRL_9_TA_SURE(uint32_t val)
833−{
834− return ((val) << DSI_28nm_8960_PHY_TIMING_CTRL_9_TA_SURE__SHIFT) & DSI_28nm_8960_PHY_TIMING_CTRL_9_TA_SURE__MASK;
835−}
836−
837−#define REG_DSI_28nm_8960_PHY_TIMING_CTRL_10 0x00000168
838−#define DSI_28nm_8960_PHY_TIMING_CTRL_10_TA_GET__MASK 0x00000007
839−#define DSI_28nm_8960_PHY_TIMING_CTRL_10_TA_GET__SHIFT 0
840−static inline uint32_t DSI_28nm_8960_PHY_TIMING_CTRL_10_TA_GET(uint32_t val)
841−{
842− return ((val) << DSI_28nm_8960_PHY_TIMING_CTRL_10_TA_GET__SHIFT) & DSI_28nm_8960_PHY_TIMING_CTRL_10_TA_GET__MASK;
843−}
844−
845−#define REG_DSI_28nm_8960_PHY_TIMING_CTRL_11 0x0000016c
846−#define DSI_28nm_8960_PHY_TIMING_CTRL_11_TRIG3_CMD__MASK 0x000000ff
847−#define DSI_28nm_8960_PHY_TIMING_CTRL_11_TRIG3_CMD__SHIFT 0
848−static inline uint32_t DSI_28nm_8960_PHY_TIMING_CTRL_11_TRIG3_CMD(uint32_t val)
849−{
850− return ((val) << DSI_28nm_8960_PHY_TIMING_CTRL_11_TRIG3_CMD__SHIFT) & DSI_28nm_8960_PHY_TIMING_CTRL_11_TRIG3_CMD__MASK;
851−}
852−
853−#define REG_DSI_28nm_8960_PHY_CTRL_0 0x00000170
854−
855−#define REG_DSI_28nm_8960_PHY_CTRL_1 0x00000174
856−
857−#define REG_DSI_28nm_8960_PHY_CTRL_2 0x00000178
858−
859−#define REG_DSI_28nm_8960_PHY_CTRL_3 0x0000017c
860−
861−#define REG_DSI_28nm_8960_PHY_STRENGTH_0 0x00000180
862−
863−#define REG_DSI_28nm_8960_PHY_STRENGTH_1 0x00000184
864−
865−#define REG_DSI_28nm_8960_PHY_STRENGTH_2 0x00000188
866−
867−#define REG_DSI_28nm_8960_PHY_BIST_CTRL_0 0x0000018c
868−
869−#define REG_DSI_28nm_8960_PHY_BIST_CTRL_1 0x00000190
870−
871−#define REG_DSI_28nm_8960_PHY_BIST_CTRL_2 0x00000194
872−
873−#define REG_DSI_28nm_8960_PHY_BIST_CTRL_3 0x00000198
874−
875−#define REG_DSI_28nm_8960_PHY_BIST_CTRL_4 0x0000019c
876−
877−#define REG_DSI_28nm_8960_PHY_LDO_CTRL 0x000001b0
878−
879−#define REG_DSI_28nm_8960_PHY_MISC_REGULATOR_CTRL_0 0x00000000
880−
881−#define REG_DSI_28nm_8960_PHY_MISC_REGULATOR_CTRL_1 0x00000004
882−
883−#define REG_DSI_28nm_8960_PHY_MISC_REGULATOR_CTRL_2 0x00000008
884−
885−#define REG_DSI_28nm_8960_PHY_MISC_REGULATOR_CTRL_3 0x0000000c
886−
887−#define REG_DSI_28nm_8960_PHY_MISC_REGULATOR_CTRL_4 0x00000010
888−
889−#define REG_DSI_28nm_8960_PHY_MISC_REGULATOR_CTRL_5 0x00000014
890−
891−#define REG_DSI_28nm_8960_PHY_MISC_REGULATOR_CAL_PWR_CFG 0x00000018
892−
893−#define REG_DSI_28nm_8960_PHY_MISC_CAL_HW_TRIGGER 0x00000028
894−
895−#define REG_DSI_28nm_8960_PHY_MISC_CAL_SW_CFG_0 0x0000002c
896−
897−#define REG_DSI_28nm_8960_PHY_MISC_CAL_SW_CFG_1 0x00000030
898−
899−#define REG_DSI_28nm_8960_PHY_MISC_CAL_SW_CFG_2 0x00000034
900−
901−#define REG_DSI_28nm_8960_PHY_MISC_CAL_HW_CFG_0 0x00000038
902−
903−#define REG_DSI_28nm_8960_PHY_MISC_CAL_HW_CFG_1 0x0000003c
904−
905−#define REG_DSI_28nm_8960_PHY_MISC_CAL_HW_CFG_2 0x00000040
906−
907−#define REG_DSI_28nm_8960_PHY_MISC_CAL_HW_CFG_3 0x00000044
908−
909−#define REG_DSI_28nm_8960_PHY_MISC_CAL_HW_CFG_4 0x00000048
910−
911−#define REG_DSI_28nm_8960_PHY_MISC_CAL_STATUS 0x00000050
912−#define DSI_28nm_8960_PHY_MISC_CAL_STATUS_CAL_BUSY 0x00000010
913−
914−#define REG_DSI_28nm_8960_PHY_PLL_CTRL_0 0x00000000
915−#define DSI_28nm_8960_PHY_PLL_CTRL_0_ENABLE 0x00000001
916−
917−#define REG_DSI_28nm_8960_PHY_PLL_CTRL_1 0x00000004
918−
919−#define REG_DSI_28nm_8960_PHY_PLL_CTRL_2 0x00000008
920−
921−#define REG_DSI_28nm_8960_PHY_PLL_CTRL_3 0x0000000c
922−
923−#define REG_DSI_28nm_8960_PHY_PLL_CTRL_4 0x00000010
924−
925−#define REG_DSI_28nm_8960_PHY_PLL_CTRL_5 0x00000014
926−
927−#define REG_DSI_28nm_8960_PHY_PLL_CTRL_6 0x00000018
928−
929−#define REG_DSI_28nm_8960_PHY_PLL_CTRL_7 0x0000001c
930−
931−#define REG_DSI_28nm_8960_PHY_PLL_CTRL_8 0x00000020
932−
933−#define REG_DSI_28nm_8960_PHY_PLL_CTRL_9 0x00000024
934−
935−#define REG_DSI_28nm_8960_PHY_PLL_CTRL_10 0x00000028
936−
937−#define REG_DSI_28nm_8960_PHY_PLL_CTRL_11 0x0000002c
938−
939−#define REG_DSI_28nm_8960_PHY_PLL_CTRL_12 0x00000030
940−
941−#define REG_DSI_28nm_8960_PHY_PLL_CTRL_13 0x00000034
942−
943−#define REG_DSI_28nm_8960_PHY_PLL_CTRL_14 0x00000038
944−
945−#define REG_DSI_28nm_8960_PHY_PLL_CTRL_15 0x0000003c
946−
947−#define REG_DSI_28nm_8960_PHY_PLL_CTRL_16 0x00000040
948−
949−#define REG_DSI_28nm_8960_PHY_PLL_CTRL_17 0x00000044
950−
951−#define REG_DSI_28nm_8960_PHY_PLL_CTRL_18 0x00000048
952−
953−#define REG_DSI_28nm_8960_PHY_PLL_CTRL_19 0x0000004c
954−
955−#define REG_DSI_28nm_8960_PHY_PLL_CTRL_20 0x00000050
956−
957−#define REG_DSI_28nm_8960_PHY_PLL_RDY 0x00000080
958−#define DSI_28nm_8960_PHY_PLL_RDY_PLL_RDY 0x00000001
959−
960−static inline uint32_t REG_DSI_28nm_PHY_LN(uint32_t i0) { return 0x00000000 + 0x40*i0; }
961−
962−static inline uint32_t REG_DSI_28nm_PHY_LN_CFG_0(uint32_t i0) { return 0x00000000 + 0x40*i0; }
963−
964−static inline uint32_t REG_DSI_28nm_PHY_LN_CFG_1(uint32_t i0) { return 0x00000004 + 0x40*i0; }
965−
966−static inline uint32_t REG_DSI_28nm_PHY_LN_CFG_2(uint32_t i0) { return 0x00000008 + 0x40*i0; }
967−
968−static inline uint32_t REG_DSI_28nm_PHY_LN_CFG_3(uint32_t i0) { return 0x0000000c + 0x40*i0; }
969−
970−static inline uint32_t REG_DSI_28nm_PHY_LN_CFG_4(uint32_t i0) { return 0x00000010 + 0x40*i0; }
971−
972−static inline uint32_t REG_DSI_28nm_PHY_LN_TEST_DATAPATH(uint32_t i0) { return 0x00000014 + 0x40*i0; }
973−
974−static inline uint32_t REG_DSI_28nm_PHY_LN_DEBUG_SEL(uint32_t i0) { return 0x00000018 + 0x40*i0; }
975−
976−static inline uint32_t REG_DSI_28nm_PHY_LN_TEST_STR_0(uint32_t i0) { return 0x0000001c + 0x40*i0; }
977−
978−static inline uint32_t REG_DSI_28nm_PHY_LN_TEST_STR_1(uint32_t i0) { return 0x00000020 + 0x40*i0; }
979−
980−#define REG_DSI_28nm_PHY_LNCK_CFG_0 0x00000100
981−
982−#define REG_DSI_28nm_PHY_LNCK_CFG_1 0x00000104
983−
984−#define REG_DSI_28nm_PHY_LNCK_CFG_2 0x00000108
985−
986−#define REG_DSI_28nm_PHY_LNCK_CFG_3 0x0000010c
987−
988−#define REG_DSI_28nm_PHY_LNCK_CFG_4 0x00000110
989−
990−#define REG_DSI_28nm_PHY_LNCK_TEST_DATAPATH 0x00000114
991−
992−#define REG_DSI_28nm_PHY_LNCK_DEBUG_SEL 0x00000118
993−
994−#define REG_DSI_28nm_PHY_LNCK_TEST_STR0 0x0000011c
995−
996−#define REG_DSI_28nm_PHY_LNCK_TEST_STR1 0x00000120
997−
998−#define REG_DSI_28nm_PHY_TIMING_CTRL_0 0x00000140
999−#define DSI_28nm_PHY_TIMING_CTRL_0_CLK_ZERO__MASK 0x000000ff
1000−#define DSI_28nm_PHY_TIMING_CTRL_0_CLK_ZERO__SHIFT 0
1001−static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_0_CLK_ZERO(uint32_t val)
1002−{
1003− return ((val) << DSI_28nm_PHY_TIMING_CTRL_0_CLK_ZERO__SHIFT) & DSI_28nm_PHY_TIMING_CTRL_0_CLK_ZERO__MASK;
1004−}
1005−
1006−#define REG_DSI_28nm_PHY_TIMING_CTRL_1 0x00000144
1007−#define DSI_28nm_PHY_TIMING_CTRL_1_CLK_TRAIL__MASK 0x000000ff
1008−#define DSI_28nm_PHY_TIMING_CTRL_1_CLK_TRAIL__SHIFT 0
1009−static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_1_CLK_TRAIL(uint32_t val)
1010−{
1011− return ((val) << DSI_28nm_PHY_TIMING_CTRL_1_CLK_TRAIL__SHIFT) & DSI_28nm_PHY_TIMING_CTRL_1_CLK_TRAIL__MASK;
1012−}
1013−
1014−#define REG_DSI_28nm_PHY_TIMING_CTRL_2 0x00000148
1015−#define DSI_28nm_PHY_TIMING_CTRL_2_CLK_PREPARE__MASK 0x000000ff
1016−#define DSI_28nm_PHY_TIMING_CTRL_2_CLK_PREPARE__SHIFT 0
1017−static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_2_CLK_PREPARE(uint32_t val)
1018−{
1019− return ((val) << DSI_28nm_PHY_TIMING_CTRL_2_CLK_PREPARE__SHIFT) & DSI_28nm_PHY_TIMING_CTRL_2_CLK_PREPARE__MASK;
1020−}
1021−
1022−#define REG_DSI_28nm_PHY_TIMING_CTRL_3 0x0000014c
1023−#define DSI_28nm_PHY_TIMING_CTRL_3_CLK_ZERO_8 0x00000001
1024−
1025−#define REG_DSI_28nm_PHY_TIMING_CTRL_4 0x00000150
1026−#define DSI_28nm_PHY_TIMING_CTRL_4_HS_EXIT__MASK 0x000000ff
1027−#define DSI_28nm_PHY_TIMING_CTRL_4_HS_EXIT__SHIFT 0
1028−static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_4_HS_EXIT(uint32_t val)
1029−{
1030− return ((val) << DSI_28nm_PHY_TIMING_CTRL_4_HS_EXIT__SHIFT) & DSI_28nm_PHY_TIMING_CTRL_4_HS_EXIT__MASK;
1031−}
1032−
1033−#define REG_DSI_28nm_PHY_TIMING_CTRL_5 0x00000154
1034−#define DSI_28nm_PHY_TIMING_CTRL_5_HS_ZERO__MASK 0x000000ff
1035−#define DSI_28nm_PHY_TIMING_CTRL_5_HS_ZERO__SHIFT 0
1036−static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_5_HS_ZERO(uint32_t val)
1037−{
1038− return ((val) << DSI_28nm_PHY_TIMING_CTRL_5_HS_ZERO__SHIFT) & DSI_28nm_PHY_TIMING_CTRL_5_HS_ZERO__MASK;
1039−}
1040−
1041−#define REG_DSI_28nm_PHY_TIMING_CTRL_6 0x00000158
1042−#define DSI_28nm_PHY_TIMING_CTRL_6_HS_PREPARE__MASK 0x000000ff
1043−#define DSI_28nm_PHY_TIMING_CTRL_6_HS_PREPARE__SHIFT 0
1044−static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_6_HS_PREPARE(uint32_t val)
1045−{
1046− return ((val) << DSI_28nm_PHY_TIMING_CTRL_6_HS_PREPARE__SHIFT) & DSI_28nm_PHY_TIMING_CTRL_6_HS_PREPARE__MASK;
1047−}
1048−
1049−#define REG_DSI_28nm_PHY_TIMING_CTRL_7 0x0000015c
1050−#define DSI_28nm_PHY_TIMING_CTRL_7_HS_TRAIL__MASK 0x000000ff
1051−#define DSI_28nm_PHY_TIMING_CTRL_7_HS_TRAIL__SHIFT 0
1052−static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_7_HS_TRAIL(uint32_t val)
1053−{
1054− return ((val) << DSI_28nm_PHY_TIMING_CTRL_7_HS_TRAIL__SHIFT) & DSI_28nm_PHY_TIMING_CTRL_7_HS_TRAIL__MASK;
1055−}
1056−
1057−#define REG_DSI_28nm_PHY_TIMING_CTRL_8 0x00000160
1058−#define DSI_28nm_PHY_TIMING_CTRL_8_HS_RQST__MASK 0x000000ff
1059−#define DSI_28nm_PHY_TIMING_CTRL_8_HS_RQST__SHIFT 0
1060−static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_8_HS_RQST(uint32_t val)
1061−{
1062− return ((val) << DSI_28nm_PHY_TIMING_CTRL_8_HS_RQST__SHIFT) & DSI_28nm_PHY_TIMING_CTRL_8_HS_RQST__MASK;
1063−}
1064−
1065−#define REG_DSI_28nm_PHY_TIMING_CTRL_9 0x00000164
1066−#define DSI_28nm_PHY_TIMING_CTRL_9_TA_GO__MASK 0x00000007
1067−#define DSI_28nm_PHY_TIMING_CTRL_9_TA_GO__SHIFT 0
1068−static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_9_TA_GO(uint32_t val)
1069−{
1070− return ((val) << DSI_28nm_PHY_TIMING_CTRL_9_TA_GO__SHIFT) & DSI_28nm_PHY_TIMING_CTRL_9_TA_GO__MASK;
1071−}
1072−#define DSI_28nm_PHY_TIMING_CTRL_9_TA_SURE__MASK 0x00000070
1073−#define DSI_28nm_PHY_TIMING_CTRL_9_TA_SURE__SHIFT 4
1074−static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_9_TA_SURE(uint32_t val)
1075−{
1076− return ((val) << DSI_28nm_PHY_TIMING_CTRL_9_TA_SURE__SHIFT) & DSI_28nm_PHY_TIMING_CTRL_9_TA_SURE__MASK;
1077−}
1078−
1079−#define REG_DSI_28nm_PHY_TIMING_CTRL_10 0x00000168
1080−#define DSI_28nm_PHY_TIMING_CTRL_10_TA_GET__MASK 0x00000007
1081−#define DSI_28nm_PHY_TIMING_CTRL_10_TA_GET__SHIFT 0
1082−static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_10_TA_GET(uint32_t val)
1083−{
1084− return ((val) << DSI_28nm_PHY_TIMING_CTRL_10_TA_GET__SHIFT) & DSI_28nm_PHY_TIMING_CTRL_10_TA_GET__MASK;
1085−}
1086−
1087−#define REG_DSI_28nm_PHY_TIMING_CTRL_11 0x0000016c
1088−#define DSI_28nm_PHY_TIMING_CTRL_11_TRIG3_CMD__MASK 0x000000ff
1089−#define DSI_28nm_PHY_TIMING_CTRL_11_TRIG3_CMD__SHIFT 0
1090−static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_11_TRIG3_CMD(uint32_t val)
1091−{
1092− return ((val) << DSI_28nm_PHY_TIMING_CTRL_11_TRIG3_CMD__SHIFT) & DSI_28nm_PHY_TIMING_CTRL_11_TRIG3_CMD__MASK;
1093−}
1094−
1095−#define REG_DSI_28nm_PHY_CTRL_0 0x00000170
1096−
1097−#define REG_DSI_28nm_PHY_CTRL_1 0x00000174
1098−
1099−#define REG_DSI_28nm_PHY_CTRL_2 0x00000178
1100−
1101−#define REG_DSI_28nm_PHY_CTRL_3 0x0000017c
1102−
1103−#define REG_DSI_28nm_PHY_CTRL_4 0x00000180
1104−
1105−#define REG_DSI_28nm_PHY_STRENGTH_0 0x00000184
1106−
1107−#define REG_DSI_28nm_PHY_STRENGTH_1 0x00000188
1108−
1109−#define REG_DSI_28nm_PHY_BIST_CTRL_0 0x000001b4
1110−
1111−#define REG_DSI_28nm_PHY_BIST_CTRL_1 0x000001b8
1112−
1113−#define REG_DSI_28nm_PHY_BIST_CTRL_2 0x000001bc
1114−
1115−#define REG_DSI_28nm_PHY_BIST_CTRL_3 0x000001c0
1116−
1117−#define REG_DSI_28nm_PHY_BIST_CTRL_4 0x000001c4
1118−
1119−#define REG_DSI_28nm_PHY_BIST_CTRL_5 0x000001c8
1120−
1121−#define REG_DSI_28nm_PHY_GLBL_TEST_CTRL 0x000001d4
1122−#define DSI_28nm_PHY_GLBL_TEST_CTRL_BITCLK_HS_SEL 0x00000001
1123−
1124−#define REG_DSI_28nm_PHY_LDO_CNTRL 0x000001dc
1125−
1126−#define REG_DSI_28nm_PHY_REGULATOR_CTRL_0 0x00000000
1127−
1128−#define REG_DSI_28nm_PHY_REGULATOR_CTRL_1 0x00000004
1129−
1130−#define REG_DSI_28nm_PHY_REGULATOR_CTRL_2 0x00000008
1131−
1132−#define REG_DSI_28nm_PHY_REGULATOR_CTRL_3 0x0000000c
1133−
1134−#define REG_DSI_28nm_PHY_REGULATOR_CTRL_4 0x00000010
1135−
1136−#define REG_DSI_28nm_PHY_REGULATOR_CTRL_5 0x00000014
1137−
1138−#define REG_DSI_28nm_PHY_REGULATOR_CAL_PWR_CFG 0x00000018
1139−
1140−#define REG_DSI_28nm_PHY_PLL_REFCLK_CFG 0x00000000
1141−#define DSI_28nm_PHY_PLL_REFCLK_CFG_DBLR 0x00000001
1142−
1143−#define REG_DSI_28nm_PHY_PLL_POSTDIV1_CFG 0x00000004
1144−
1145−#define REG_DSI_28nm_PHY_PLL_CHGPUMP_CFG 0x00000008
1146−
1147−#define REG_DSI_28nm_PHY_PLL_VCOLPF_CFG 0x0000000c
1148−
1149−#define REG_DSI_28nm_PHY_PLL_VREG_CFG 0x00000010
1150−#define DSI_28nm_PHY_PLL_VREG_CFG_POSTDIV1_BYPASS_B 0x00000002
1151−
1152−#define REG_DSI_28nm_PHY_PLL_PWRGEN_CFG 0x00000014
1153−
1154−#define REG_DSI_28nm_PHY_PLL_DMUX_CFG 0x00000018
1155−
1156−#define REG_DSI_28nm_PHY_PLL_AMUX_CFG 0x0000001c
1157−
1158−#define REG_DSI_28nm_PHY_PLL_GLB_CFG 0x00000020
1159−#define DSI_28nm_PHY_PLL_GLB_CFG_PLL_PWRDN_B 0x00000001
1160−#define DSI_28nm_PHY_PLL_GLB_CFG_PLL_LDO_PWRDN_B 0x00000002
1161−#define DSI_28nm_PHY_PLL_GLB_CFG_PLL_PWRGEN_PWRDN_B 0x00000004
1162−#define DSI_28nm_PHY_PLL_GLB_CFG_PLL_ENABLE 0x00000008
1163−
1164−#define REG_DSI_28nm_PHY_PLL_POSTDIV2_CFG 0x00000024
1165−
1166−#define REG_DSI_28nm_PHY_PLL_POSTDIV3_CFG 0x00000028
1167−
1168−#define REG_DSI_28nm_PHY_PLL_LPFR_CFG 0x0000002c
1169−
1170−#define REG_DSI_28nm_PHY_PLL_LPFC1_CFG 0x00000030
1171−
1172−#define REG_DSI_28nm_PHY_PLL_LPFC2_CFG 0x00000034
1173−
1174−#define REG_DSI_28nm_PHY_PLL_SDM_CFG0 0x00000038
1175−#define DSI_28nm_PHY_PLL_SDM_CFG0_BYP_DIV__MASK 0x0000003f
1176−#define DSI_28nm_PHY_PLL_SDM_CFG0_BYP_DIV__SHIFT 0
1177−static inline uint32_t DSI_28nm_PHY_PLL_SDM_CFG0_BYP_DIV(uint32_t val)
1178−{
1179− return ((val) << DSI_28nm_PHY_PLL_SDM_CFG0_BYP_DIV__SHIFT) & DSI_28nm_PHY_PLL_SDM_CFG0_BYP_DIV__MASK;
1180−}
1181−#define DSI_28nm_PHY_PLL_SDM_CFG0_BYP 0x00000040
1182−
1183−#define REG_DSI_28nm_PHY_PLL_SDM_CFG1 0x0000003c
1184−#define DSI_28nm_PHY_PLL_SDM_CFG1_DC_OFFSET__MASK 0x0000003f
1185−#define DSI_28nm_PHY_PLL_SDM_CFG1_DC_OFFSET__SHIFT 0
1186−static inline uint32_t DSI_28nm_PHY_PLL_SDM_CFG1_DC_OFFSET(uint32_t val)
1187−{
1188− return ((val) << DSI_28nm_PHY_PLL_SDM_CFG1_DC_OFFSET__SHIFT) & DSI_28nm_PHY_PLL_SDM_CFG1_DC_OFFSET__MASK;
1189−}
1190−#define DSI_28nm_PHY_PLL_SDM_CFG1_DITHER_EN__MASK 0x00000040
1191−#define DSI_28nm_PHY_PLL_SDM_CFG1_DITHER_EN__SHIFT 6
1192−static inline uint32_t DSI_28nm_PHY_PLL_SDM_CFG1_DITHER_EN(uint32_t val)
1193−{
1194− return ((val) << DSI_28nm_PHY_PLL_SDM_CFG1_DITHER_EN__SHIFT) & DSI_28nm_PHY_PLL_SDM_CFG1_DITHER_EN__MASK;
1195−}
1196−
1197−#define REG_DSI_28nm_PHY_PLL_SDM_CFG2 0x00000040
1198−#define DSI_28nm_PHY_PLL_SDM_CFG2_FREQ_SEED_7_0__MASK 0x000000ff
1199−#define DSI_28nm_PHY_PLL_SDM_CFG2_FREQ_SEED_7_0__SHIFT 0
1200−static inline uint32_t DSI_28nm_PHY_PLL_SDM_CFG2_FREQ_SEED_7_0(uint32_t val)
1201−{
1202− return ((val) << DSI_28nm_PHY_PLL_SDM_CFG2_FREQ_SEED_7_0__SHIFT) & DSI_28nm_PHY_PLL_SDM_CFG2_FREQ_SEED_7_0__MASK;
1203−}
1204−
1205−#define REG_DSI_28nm_PHY_PLL_SDM_CFG3 0x00000044
1206−#define DSI_28nm_PHY_PLL_SDM_CFG3_FREQ_SEED_15_8__MASK 0x000000ff
1207−#define DSI_28nm_PHY_PLL_SDM_CFG3_FREQ_SEED_15_8__SHIFT 0
1208−static inline uint32_t DSI_28nm_PHY_PLL_SDM_CFG3_FREQ_SEED_15_8(uint32_t val)
1209−{
1210− return ((val) << DSI_28nm_PHY_PLL_SDM_CFG3_FREQ_SEED_15_8__SHIFT) & DSI_28nm_PHY_PLL_SDM_CFG3_FREQ_SEED_15_8__MASK;
1211−}
1212−
1213−#define REG_DSI_28nm_PHY_PLL_SDM_CFG4 0x00000048
1214−
1215−#define REG_DSI_28nm_PHY_PLL_SSC_CFG0 0x0000004c
1216−
1217−#define REG_DSI_28nm_PHY_PLL_SSC_CFG1 0x00000050
1218−
1219−#define REG_DSI_28nm_PHY_PLL_SSC_CFG2 0x00000054
1220−
1221−#define REG_DSI_28nm_PHY_PLL_SSC_CFG3 0x00000058
1222−
1223−#define REG_DSI_28nm_PHY_PLL_LKDET_CFG0 0x0000005c
1224−
1225−#define REG_DSI_28nm_PHY_PLL_LKDET_CFG1 0x00000060
1226−
1227−#define REG_DSI_28nm_PHY_PLL_LKDET_CFG2 0x00000064
1228−
1229−#define REG_DSI_28nm_PHY_PLL_TEST_CFG 0x00000068
1230−#define DSI_28nm_PHY_PLL_TEST_CFG_PLL_SW_RESET 0x00000001
1231−
1232−#define REG_DSI_28nm_PHY_PLL_CAL_CFG0 0x0000006c
1233−
1234−#define REG_DSI_28nm_PHY_PLL_CAL_CFG1 0x00000070
1235−
1236−#define REG_DSI_28nm_PHY_PLL_CAL_CFG2 0x00000074
1237−
1238−#define REG_DSI_28nm_PHY_PLL_CAL_CFG3 0x00000078
1239−
1240−#define REG_DSI_28nm_PHY_PLL_CAL_CFG4 0x0000007c
1241−
1242−#define REG_DSI_28nm_PHY_PLL_CAL_CFG5 0x00000080
1243−
1244−#define REG_DSI_28nm_PHY_PLL_CAL_CFG6 0x00000084
1245−
1246−#define REG_DSI_28nm_PHY_PLL_CAL_CFG7 0x00000088
1247−
1248−#define REG_DSI_28nm_PHY_PLL_CAL_CFG8 0x0000008c
1249−
1250−#define REG_DSI_28nm_PHY_PLL_CAL_CFG9 0x00000090
1251−
1252−#define REG_DSI_28nm_PHY_PLL_CAL_CFG10 0x00000094
1253−
1254−#define REG_DSI_28nm_PHY_PLL_CAL_CFG11 0x00000098
1255−
1256−#define REG_DSI_28nm_PHY_PLL_EFUSE_CFG 0x0000009c
1257−
1258−#define REG_DSI_28nm_PHY_PLL_DEBUG_BUS_SEL 0x000000a0
1259−
1260−#define REG_DSI_28nm_PHY_PLL_CTRL_42 0x000000a4
1261−
1262−#define REG_DSI_28nm_PHY_PLL_CTRL_43 0x000000a8
1263−
1264−#define REG_DSI_28nm_PHY_PLL_CTRL_44 0x000000ac
1265−
1266−#define REG_DSI_28nm_PHY_PLL_CTRL_45 0x000000b0
1267−
1268−#define REG_DSI_28nm_PHY_PLL_CTRL_46 0x000000b4
1269−
1270−#define REG_DSI_28nm_PHY_PLL_CTRL_47 0x000000b8
1271−
1272−#define REG_DSI_28nm_PHY_PLL_CTRL_48 0x000000bc
1273−
1274−#define REG_DSI_28nm_PHY_PLL_STATUS 0x000000c0
1275−#define DSI_28nm_PHY_PLL_STATUS_PLL_RDY 0x00000001
1276−
1277−#define REG_DSI_28nm_PHY_PLL_DEBUG_BUS0 0x000000c4
1278−
1279−#define REG_DSI_28nm_PHY_PLL_DEBUG_BUS1 0x000000c8
1280−
1281−#define REG_DSI_28nm_PHY_PLL_DEBUG_BUS2 0x000000cc
1282−
1283−#define REG_DSI_28nm_PHY_PLL_DEBUG_BUS3 0x000000d0
1284−
1285−#define REG_DSI_28nm_PHY_PLL_CTRL_54 0x000000d4
1286−
1287−static inline uint32_t REG_DSI_20nm_PHY_LN(uint32_t i0) { return 0x00000000 + 0x40*i0; }
1288−
1289−static inline uint32_t REG_DSI_20nm_PHY_LN_CFG_0(uint32_t i0) { return 0x00000000 + 0x40*i0; }
1290−
1291−static inline uint32_t REG_DSI_20nm_PHY_LN_CFG_1(uint32_t i0) { return 0x00000004 + 0x40*i0; }
1292−
1293−static inline uint32_t REG_DSI_20nm_PHY_LN_CFG_2(uint32_t i0) { return 0x00000008 + 0x40*i0; }
1294−
1295−static inline uint32_t REG_DSI_20nm_PHY_LN_CFG_3(uint32_t i0) { return 0x0000000c + 0x40*i0; }
1296−
1297−static inline uint32_t REG_DSI_20nm_PHY_LN_CFG_4(uint32_t i0) { return 0x00000010 + 0x40*i0; }
1298−
1299−static inline uint32_t REG_DSI_20nm_PHY_LN_TEST_DATAPATH(uint32_t i0) { return 0x00000014 + 0x40*i0; }
1300−
1301−static inline uint32_t REG_DSI_20nm_PHY_LN_DEBUG_SEL(uint32_t i0) { return 0x00000018 + 0x40*i0; }
1302−
1303−static inline uint32_t REG_DSI_20nm_PHY_LN_TEST_STR_0(uint32_t i0) { return 0x0000001c + 0x40*i0; }
1304−
1305−static inline uint32_t REG_DSI_20nm_PHY_LN_TEST_STR_1(uint32_t i0) { return 0x00000020 + 0x40*i0; }
1306−
1307−#define REG_DSI_20nm_PHY_LNCK_CFG_0 0x00000100
1308−
1309−#define REG_DSI_20nm_PHY_LNCK_CFG_1 0x00000104
1310−
1311−#define REG_DSI_20nm_PHY_LNCK_CFG_2 0x00000108
1312−
1313−#define REG_DSI_20nm_PHY_LNCK_CFG_3 0x0000010c
1314−
1315−#define REG_DSI_20nm_PHY_LNCK_CFG_4 0x00000110
1316−
1317−#define REG_DSI_20nm_PHY_LNCK_TEST_DATAPATH 0x00000114
1318−
1319−#define REG_DSI_20nm_PHY_LNCK_DEBUG_SEL 0x00000118
1320−
1321−#define REG_DSI_20nm_PHY_LNCK_TEST_STR0 0x0000011c
1322−
1323−#define REG_DSI_20nm_PHY_LNCK_TEST_STR1 0x00000120
1324−
1325−#define REG_DSI_20nm_PHY_TIMING_CTRL_0 0x00000140
1326−#define DSI_20nm_PHY_TIMING_CTRL_0_CLK_ZERO__MASK 0x000000ff
1327−#define DSI_20nm_PHY_TIMING_CTRL_0_CLK_ZERO__SHIFT 0
1328−static inline uint32_t DSI_20nm_PHY_TIMING_CTRL_0_CLK_ZERO(uint32_t val)
1329−{
1330− return ((val) << DSI_20nm_PHY_TIMING_CTRL_0_CLK_ZERO__SHIFT) & DSI_20nm_PHY_TIMING_CTRL_0_CLK_ZERO__MASK;
1331−}
1332−
1333−#define REG_DSI_20nm_PHY_TIMING_CTRL_1 0x00000144
1334−#define DSI_20nm_PHY_TIMING_CTRL_1_CLK_TRAIL__MASK 0x000000ff
1335−#define DSI_20nm_PHY_TIMING_CTRL_1_CLK_TRAIL__SHIFT 0
1336−static inline uint32_t DSI_20nm_PHY_TIMING_CTRL_1_CLK_TRAIL(uint32_t val)
1337−{
1338− return ((val) << DSI_20nm_PHY_TIMING_CTRL_1_CLK_TRAIL__SHIFT) & DSI_20nm_PHY_TIMING_CTRL_1_CLK_TRAIL__MASK;
1339−}
1340−
1341−#define REG_DSI_20nm_PHY_TIMING_CTRL_2 0x00000148
1342−#define DSI_20nm_PHY_TIMING_CTRL_2_CLK_PREPARE__MASK 0x000000ff
1343−#define DSI_20nm_PHY_TIMING_CTRL_2_CLK_PREPARE__SHIFT 0
1344−static inline uint32_t DSI_20nm_PHY_TIMING_CTRL_2_CLK_PREPARE(uint32_t val)
1345−{
1346− return ((val) << DSI_20nm_PHY_TIMING_CTRL_2_CLK_PREPARE__SHIFT) & DSI_20nm_PHY_TIMING_CTRL_2_CLK_PREPARE__MASK;
1347−}
1348−
1349−#define REG_DSI_20nm_PHY_TIMING_CTRL_3 0x0000014c
1350−#define DSI_20nm_PHY_TIMING_CTRL_3_CLK_ZERO_8 0x00000001
1351−
1352−#define REG_DSI_20nm_PHY_TIMING_CTRL_4 0x00000150
1353−#define DSI_20nm_PHY_TIMING_CTRL_4_HS_EXIT__MASK 0x000000ff
1354−#define DSI_20nm_PHY_TIMING_CTRL_4_HS_EXIT__SHIFT 0
1355−static inline uint32_t DSI_20nm_PHY_TIMING_CTRL_4_HS_EXIT(uint32_t val)
1356−{
1357− return ((val) << DSI_20nm_PHY_TIMING_CTRL_4_HS_EXIT__SHIFT) & DSI_20nm_PHY_TIMING_CTRL_4_HS_EXIT__MASK;
1358−}
1359−
1360−#define REG_DSI_20nm_PHY_TIMING_CTRL_5 0x00000154
1361−#define DSI_20nm_PHY_TIMING_CTRL_5_HS_ZERO__MASK 0x000000ff
1362−#define DSI_20nm_PHY_TIMING_CTRL_5_HS_ZERO__SHIFT 0
1363−static inline uint32_t DSI_20nm_PHY_TIMING_CTRL_5_HS_ZERO(uint32_t val)
1364−{
1365− return ((val) << DSI_20nm_PHY_TIMING_CTRL_5_HS_ZERO__SHIFT) & DSI_20nm_PHY_TIMING_CTRL_5_HS_ZERO__MASK;
1366−}
1367−
1368−#define REG_DSI_20nm_PHY_TIMING_CTRL_6 0x00000158
1369−#define DSI_20nm_PHY_TIMING_CTRL_6_HS_PREPARE__MASK 0x000000ff
1370−#define DSI_20nm_PHY_TIMING_CTRL_6_HS_PREPARE__SHIFT 0
1371−static inline uint32_t DSI_20nm_PHY_TIMING_CTRL_6_HS_PREPARE(uint32_t val)
1372−{
1373− return ((val) << DSI_20nm_PHY_TIMING_CTRL_6_HS_PREPARE__SHIFT) & DSI_20nm_PHY_TIMING_CTRL_6_HS_PREPARE__MASK;
1374−}
1375−
1376−#define REG_DSI_20nm_PHY_TIMING_CTRL_7 0x0000015c
1377−#define DSI_20nm_PHY_TIMING_CTRL_7_HS_TRAIL__MASK 0x000000ff
1378−#define DSI_20nm_PHY_TIMING_CTRL_7_HS_TRAIL__SHIFT 0
1379−static inline uint32_t DSI_20nm_PHY_TIMING_CTRL_7_HS_TRAIL(uint32_t val)
1380−{
1381− return ((val) << DSI_20nm_PHY_TIMING_CTRL_7_HS_TRAIL__SHIFT) & DSI_20nm_PHY_TIMING_CTRL_7_HS_TRAIL__MASK;
1382−}
1383−
1384−#define REG_DSI_20nm_PHY_TIMING_CTRL_8 0x00000160
1385−#define DSI_20nm_PHY_TIMING_CTRL_8_HS_RQST__MASK 0x000000ff
1386−#define DSI_20nm_PHY_TIMING_CTRL_8_HS_RQST__SHIFT 0
1387−static inline uint32_t DSI_20nm_PHY_TIMING_CTRL_8_HS_RQST(uint32_t val)
1388−{
1389− return ((val) << DSI_20nm_PHY_TIMING_CTRL_8_HS_RQST__SHIFT) & DSI_20nm_PHY_TIMING_CTRL_8_HS_RQST__MASK;
1390−}
1391−
1392−#define REG_DSI_20nm_PHY_TIMING_CTRL_9 0x00000164
1393−#define DSI_20nm_PHY_TIMING_CTRL_9_TA_GO__MASK 0x00000007
1394−#define DSI_20nm_PHY_TIMING_CTRL_9_TA_GO__SHIFT 0
1395−static inline uint32_t DSI_20nm_PHY_TIMING_CTRL_9_TA_GO(uint32_t val)
1396−{
1397− return ((val) << DSI_20nm_PHY_TIMING_CTRL_9_TA_GO__SHIFT) & DSI_20nm_PHY_TIMING_CTRL_9_TA_GO__MASK;
1398−}
1399−#define DSI_20nm_PHY_TIMING_CTRL_9_TA_SURE__MASK 0x00000070
1400−#define DSI_20nm_PHY_TIMING_CTRL_9_TA_SURE__SHIFT 4
1401−static inline uint32_t DSI_20nm_PHY_TIMING_CTRL_9_TA_SURE(uint32_t val)
1402−{
1403− return ((val) << DSI_20nm_PHY_TIMING_CTRL_9_TA_SURE__SHIFT) & DSI_20nm_PHY_TIMING_CTRL_9_TA_SURE__MASK;
1404−}
1405−
1406−#define REG_DSI_20nm_PHY_TIMING_CTRL_10 0x00000168
1407−#define DSI_20nm_PHY_TIMING_CTRL_10_TA_GET__MASK 0x00000007
1408−#define DSI_20nm_PHY_TIMING_CTRL_10_TA_GET__SHIFT 0
1409−static inline uint32_t DSI_20nm_PHY_TIMING_CTRL_10_TA_GET(uint32_t val)
1410−{
1411− return ((val) << DSI_20nm_PHY_TIMING_CTRL_10_TA_GET__SHIFT) & DSI_20nm_PHY_TIMING_CTRL_10_TA_GET__MASK;
1412−}
1413−
1414−#define REG_DSI_20nm_PHY_TIMING_CTRL_11 0x0000016c
1415−#define DSI_20nm_PHY_TIMING_CTRL_11_TRIG3_CMD__MASK 0x000000ff
1416−#define DSI_20nm_PHY_TIMING_CTRL_11_TRIG3_CMD__SHIFT 0
1417−static inline uint32_t DSI_20nm_PHY_TIMING_CTRL_11_TRIG3_CMD(uint32_t val)
1418−{
1419− return ((val) << DSI_20nm_PHY_TIMING_CTRL_11_TRIG3_CMD__SHIFT) & DSI_20nm_PHY_TIMING_CTRL_11_TRIG3_CMD__MASK;
1420−}
1421−
1422−#define REG_DSI_20nm_PHY_CTRL_0 0x00000170
1423−
1424−#define REG_DSI_20nm_PHY_CTRL_1 0x00000174
1425−
1426−#define REG_DSI_20nm_PHY_CTRL_2 0x00000178
1427−
1428−#define REG_DSI_20nm_PHY_CTRL_3 0x0000017c
1429−
1430−#define REG_DSI_20nm_PHY_CTRL_4 0x00000180
1431−
1432−#define REG_DSI_20nm_PHY_STRENGTH_0 0x00000184
1433−
1434−#define REG_DSI_20nm_PHY_STRENGTH_1 0x00000188
1435−
1436−#define REG_DSI_20nm_PHY_BIST_CTRL_0 0x000001b4
1437−
1438−#define REG_DSI_20nm_PHY_BIST_CTRL_1 0x000001b8
1439−
1440−#define REG_DSI_20nm_PHY_BIST_CTRL_2 0x000001bc
1441−
1442−#define REG_DSI_20nm_PHY_BIST_CTRL_3 0x000001c0
1443−
1444−#define REG_DSI_20nm_PHY_BIST_CTRL_4 0x000001c4
1445−
1446−#define REG_DSI_20nm_PHY_BIST_CTRL_5 0x000001c8
1447−
1448−#define REG_DSI_20nm_PHY_GLBL_TEST_CTRL 0x000001d4
1449−#define DSI_20nm_PHY_GLBL_TEST_CTRL_BITCLK_HS_SEL 0x00000001
1450−
1451−#define REG_DSI_20nm_PHY_LDO_CNTRL 0x000001dc
1452−
1453−#define REG_DSI_20nm_PHY_REGULATOR_CTRL_0 0x00000000
1454−
1455−#define REG_DSI_20nm_PHY_REGULATOR_CTRL_1 0x00000004
1456−
1457−#define REG_DSI_20nm_PHY_REGULATOR_CTRL_2 0x00000008
1458−
1459−#define REG_DSI_20nm_PHY_REGULATOR_CTRL_3 0x0000000c
1460−
1461−#define REG_DSI_20nm_PHY_REGULATOR_CTRL_4 0x00000010
1462−
1463−#define REG_DSI_20nm_PHY_REGULATOR_CTRL_5 0x00000014
1464−
1465−#define REG_DSI_20nm_PHY_REGULATOR_CAL_PWR_CFG 0x00000018
1466−
1467−#define REG_DSI_14nm_PHY_CMN_REVISION_ID0 0x00000000
1468−
1469−#define REG_DSI_14nm_PHY_CMN_REVISION_ID1 0x00000004
1470−
1471−#define REG_DSI_14nm_PHY_CMN_REVISION_ID2 0x00000008
1472−
1473−#define REG_DSI_14nm_PHY_CMN_REVISION_ID3 0x0000000c
1474−
1475−#define REG_DSI_14nm_PHY_CMN_CLK_CFG0 0x00000010
1476−#define DSI_14nm_PHY_CMN_CLK_CFG0_DIV_CTRL_3_0__MASK 0x000000f0
1477−#define DSI_14nm_PHY_CMN_CLK_CFG0_DIV_CTRL_3_0__SHIFT 4
1478−static inline uint32_t DSI_14nm_PHY_CMN_CLK_CFG0_DIV_CTRL_3_0(uint32_t val)
1479−{
1480− return ((val) << DSI_14nm_PHY_CMN_CLK_CFG0_DIV_CTRL_3_0__SHIFT) & DSI_14nm_PHY_CMN_CLK_CFG0_DIV_CTRL_3_0__MASK;
1481−}
1482−#define DSI_14nm_PHY_CMN_CLK_CFG0_DIV_CTRL_7_4__MASK 0x000000f0
1483−#define DSI_14nm_PHY_CMN_CLK_CFG0_DIV_CTRL_7_4__SHIFT 4
1484−static inline uint32_t DSI_14nm_PHY_CMN_CLK_CFG0_DIV_CTRL_7_4(uint32_t val)
1485−{
1486− return ((val) << DSI_14nm_PHY_CMN_CLK_CFG0_DIV_CTRL_7_4__SHIFT) & DSI_14nm_PHY_CMN_CLK_CFG0_DIV_CTRL_7_4__MASK;
1487−}
1488−
1489−#define REG_DSI_14nm_PHY_CMN_CLK_CFG1 0x00000014
1490−#define DSI_14nm_PHY_CMN_CLK_CFG1_DSICLK_SEL 0x00000001
1491−
1492−#define REG_DSI_14nm_PHY_CMN_GLBL_TEST_CTRL 0x00000018
1493−#define DSI_14nm_PHY_CMN_GLBL_TEST_CTRL_BITCLK_HS_SEL 0x00000004
1494−
1495−#define REG_DSI_14nm_PHY_CMN_CTRL_0 0x0000001c
1496−
1497−#define REG_DSI_14nm_PHY_CMN_CTRL_1 0x00000020
1498−
1499−#define REG_DSI_14nm_PHY_CMN_HW_TRIGGER 0x00000024
1500−
1501−#define REG_DSI_14nm_PHY_CMN_SW_CFG0 0x00000028
1502−
1503−#define REG_DSI_14nm_PHY_CMN_SW_CFG1 0x0000002c
1504−
1505−#define REG_DSI_14nm_PHY_CMN_SW_CFG2 0x00000030
1506−
1507−#define REG_DSI_14nm_PHY_CMN_HW_CFG0 0x00000034
1508−
1509−#define REG_DSI_14nm_PHY_CMN_HW_CFG1 0x00000038
1510−
1511−#define REG_DSI_14nm_PHY_CMN_HW_CFG2 0x0000003c
1512−
1513−#define REG_DSI_14nm_PHY_CMN_HW_CFG3 0x00000040
1514−
1515−#define REG_DSI_14nm_PHY_CMN_HW_CFG4 0x00000044
1516−
1517−#define REG_DSI_14nm_PHY_CMN_PLL_CNTRL 0x00000048
1518−#define DSI_14nm_PHY_CMN_PLL_CNTRL_PLL_START 0x00000001
1519−
1520−#define REG_DSI_14nm_PHY_CMN_LDO_CNTRL 0x0000004c
1521−#define DSI_14nm_PHY_CMN_LDO_CNTRL_VREG_CTRL__MASK 0x0000003f
1522−#define DSI_14nm_PHY_CMN_LDO_CNTRL_VREG_CTRL__SHIFT 0
1523−static inline uint32_t DSI_14nm_PHY_CMN_LDO_CNTRL_VREG_CTRL(uint32_t val)
1524−{
1525− return ((val) << DSI_14nm_PHY_CMN_LDO_CNTRL_VREG_CTRL__SHIFT) & DSI_14nm_PHY_CMN_LDO_CNTRL_VREG_CTRL__MASK;
1526−}
1527−
1528−static inline uint32_t REG_DSI_14nm_PHY_LN(uint32_t i0) { return 0x00000000 + 0x80*i0; }
1529−
1530−static inline uint32_t REG_DSI_14nm_PHY_LN_CFG0(uint32_t i0) { return 0x00000000 + 0x80*i0; }
1531−#define DSI_14nm_PHY_LN_CFG0_PREPARE_DLY__MASK 0x000000c0
1532−#define DSI_14nm_PHY_LN_CFG0_PREPARE_DLY__SHIFT 6
1533−static inline uint32_t DSI_14nm_PHY_LN_CFG0_PREPARE_DLY(uint32_t val)
1534−{
1535− return ((val) << DSI_14nm_PHY_LN_CFG0_PREPARE_DLY__SHIFT) & DSI_14nm_PHY_LN_CFG0_PREPARE_DLY__MASK;
1536−}
1537−
1538−static inline uint32_t REG_DSI_14nm_PHY_LN_CFG1(uint32_t i0) { return 0x00000004 + 0x80*i0; }
1539−#define DSI_14nm_PHY_LN_CFG1_HALFBYTECLK_EN 0x00000001
1540−
1541−static inline uint32_t REG_DSI_14nm_PHY_LN_CFG2(uint32_t i0) { return 0x00000008 + 0x80*i0; }
1542−
1543−static inline uint32_t REG_DSI_14nm_PHY_LN_CFG3(uint32_t i0) { return 0x0000000c + 0x80*i0; }
1544−
1545−static inline uint32_t REG_DSI_14nm_PHY_LN_TEST_DATAPATH(uint32_t i0) { return 0x00000010 + 0x80*i0; }
1546−
1547−static inline uint32_t REG_DSI_14nm_PHY_LN_TEST_STR(uint32_t i0) { return 0x00000014 + 0x80*i0; }
1548−
1549−static inline uint32_t REG_DSI_14nm_PHY_LN_TIMING_CTRL_4(uint32_t i0) { return 0x00000018 + 0x80*i0; }
1550−#define DSI_14nm_PHY_LN_TIMING_CTRL_4_HS_EXIT__MASK 0x000000ff
1551−#define DSI_14nm_PHY_LN_TIMING_CTRL_4_HS_EXIT__SHIFT 0
1552−static inline uint32_t DSI_14nm_PHY_LN_TIMING_CTRL_4_HS_EXIT(uint32_t val)
1553−{
1554− return ((val) << DSI_14nm_PHY_LN_TIMING_CTRL_4_HS_EXIT__SHIFT) & DSI_14nm_PHY_LN_TIMING_CTRL_4_HS_EXIT__MASK;
1555−}
1556−
1557−static inline uint32_t REG_DSI_14nm_PHY_LN_TIMING_CTRL_5(uint32_t i0) { return 0x0000001c + 0x80*i0; }
1558−#define DSI_14nm_PHY_LN_TIMING_CTRL_5_HS_ZERO__MASK 0x000000ff
1559−#define DSI_14nm_PHY_LN_TIMING_CTRL_5_HS_ZERO__SHIFT 0
1560−static inline uint32_t DSI_14nm_PHY_LN_TIMING_CTRL_5_HS_ZERO(uint32_t val)
1561−{
1562− return ((val) << DSI_14nm_PHY_LN_TIMING_CTRL_5_HS_ZERO__SHIFT) & DSI_14nm_PHY_LN_TIMING_CTRL_5_HS_ZERO__MASK;
1563−}
1564−
1565−static inline uint32_t REG_DSI_14nm_PHY_LN_TIMING_CTRL_6(uint32_t i0) { return 0x00000020 + 0x80*i0; }
1566−#define DSI_14nm_PHY_LN_TIMING_CTRL_6_HS_PREPARE__MASK 0x000000ff
1567−#define DSI_14nm_PHY_LN_TIMING_CTRL_6_HS_PREPARE__SHIFT 0
1568−static inline uint32_t DSI_14nm_PHY_LN_TIMING_CTRL_6_HS_PREPARE(uint32_t val)
1569−{
1570− return ((val) << DSI_14nm_PHY_LN_TIMING_CTRL_6_HS_PREPARE__SHIFT) & DSI_14nm_PHY_LN_TIMING_CTRL_6_HS_PREPARE__MASK;
1571−}
1572−
1573−static inline uint32_t REG_DSI_14nm_PHY_LN_TIMING_CTRL_7(uint32_t i0) { return 0x00000024 + 0x80*i0; }
1574−#define DSI_14nm_PHY_LN_TIMING_CTRL_7_HS_TRAIL__MASK 0x000000ff
1575−#define DSI_14nm_PHY_LN_TIMING_CTRL_7_HS_TRAIL__SHIFT 0
1576−static inline uint32_t DSI_14nm_PHY_LN_TIMING_CTRL_7_HS_TRAIL(uint32_t val)
1577−{
1578− return ((val) << DSI_14nm_PHY_LN_TIMING_CTRL_7_HS_TRAIL__SHIFT) & DSI_14nm_PHY_LN_TIMING_CTRL_7_HS_TRAIL__MASK;
1579−}
1580−
1581−static inline uint32_t REG_DSI_14nm_PHY_LN_TIMING_CTRL_8(uint32_t i0) { return 0x00000028 + 0x80*i0; }
1582−#define DSI_14nm_PHY_LN_TIMING_CTRL_8_HS_RQST__MASK 0x000000ff
1583−#define DSI_14nm_PHY_LN_TIMING_CTRL_8_HS_RQST__SHIFT 0
1584−static inline uint32_t DSI_14nm_PHY_LN_TIMING_CTRL_8_HS_RQST(uint32_t val)
1585−{
1586− return ((val) << DSI_14nm_PHY_LN_TIMING_CTRL_8_HS_RQST__SHIFT) & DSI_14nm_PHY_LN_TIMING_CTRL_8_HS_RQST__MASK;
1587−}
1588−
1589−static inline uint32_t REG_DSI_14nm_PHY_LN_TIMING_CTRL_9(uint32_t i0) { return 0x0000002c + 0x80*i0; }
1590−#define DSI_14nm_PHY_LN_TIMING_CTRL_9_TA_GO__MASK 0x00000007
1591−#define DSI_14nm_PHY_LN_TIMING_CTRL_9_TA_GO__SHIFT 0
1592−static inline uint32_t DSI_14nm_PHY_LN_TIMING_CTRL_9_TA_GO(uint32_t val)
1593−{
1594− return ((val) << DSI_14nm_PHY_LN_TIMING_CTRL_9_TA_GO__SHIFT) & DSI_14nm_PHY_LN_TIMING_CTRL_9_TA_GO__MASK;
1595−}
1596−#define DSI_14nm_PHY_LN_TIMING_CTRL_9_TA_SURE__MASK 0x00000070
1597−#define DSI_14nm_PHY_LN_TIMING_CTRL_9_TA_SURE__SHIFT 4
1598−static inline uint32_t DSI_14nm_PHY_LN_TIMING_CTRL_9_TA_SURE(uint32_t val)
1599−{
1600− return ((val) << DSI_14nm_PHY_LN_TIMING_CTRL_9_TA_SURE__SHIFT) & DSI_14nm_PHY_LN_TIMING_CTRL_9_TA_SURE__MASK;
1601−}
1602−
1603−static inline uint32_t REG_DSI_14nm_PHY_LN_TIMING_CTRL_10(uint32_t i0) { return 0x00000030 + 0x80*i0; }
1604−#define DSI_14nm_PHY_LN_TIMING_CTRL_10_TA_GET__MASK 0x00000007
1605−#define DSI_14nm_PHY_LN_TIMING_CTRL_10_TA_GET__SHIFT 0
1606−static inline uint32_t DSI_14nm_PHY_LN_TIMING_CTRL_10_TA_GET(uint32_t val)
1607−{
1608− return ((val) << DSI_14nm_PHY_LN_TIMING_CTRL_10_TA_GET__SHIFT) & DSI_14nm_PHY_LN_TIMING_CTRL_10_TA_GET__MASK;
1609−}
1610−
1611−static inline uint32_t REG_DSI_14nm_PHY_LN_TIMING_CTRL_11(uint32_t i0) { return 0x00000034 + 0x80*i0; }
1612−#define DSI_14nm_PHY_LN_TIMING_CTRL_11_TRIG3_CMD__MASK 0x000000ff
1613−#define DSI_14nm_PHY_LN_TIMING_CTRL_11_TRIG3_CMD__SHIFT 0
1614−static inline uint32_t DSI_14nm_PHY_LN_TIMING_CTRL_11_TRIG3_CMD(uint32_t val)
1615−{
1616− return ((val) << DSI_14nm_PHY_LN_TIMING_CTRL_11_TRIG3_CMD__SHIFT) & DSI_14nm_PHY_LN_TIMING_CTRL_11_TRIG3_CMD__MASK;
1617−}
1618−
1619−static inline uint32_t REG_DSI_14nm_PHY_LN_STRENGTH_CTRL_0(uint32_t i0) { return 0x00000038 + 0x80*i0; }
1620−
1621−static inline uint32_t REG_DSI_14nm_PHY_LN_STRENGTH_CTRL_1(uint32_t i0) { return 0x0000003c + 0x80*i0; }
1622−
1623−static inline uint32_t REG_DSI_14nm_PHY_LN_VREG_CNTRL(uint32_t i0) { return 0x00000064 + 0x80*i0; }
1624−
1625−#define REG_DSI_14nm_PHY_PLL_IE_TRIM 0x00000000
1626−
1627−#define REG_DSI_14nm_PHY_PLL_IP_TRIM 0x00000004
1628−
1629−#define REG_DSI_14nm_PHY_PLL_IPTAT_TRIM 0x00000010
1630−
1631−#define REG_DSI_14nm_PHY_PLL_CLKBUFLR_EN 0x0000001c
1632−
1633−#define REG_DSI_14nm_PHY_PLL_SYSCLK_EN_RESET 0x00000028
1634−
1635−#define REG_DSI_14nm_PHY_PLL_RESETSM_CNTRL 0x0000002c
1636−
1637−#define REG_DSI_14nm_PHY_PLL_RESETSM_CNTRL2 0x00000030
1638−
1639−#define REG_DSI_14nm_PHY_PLL_RESETSM_CNTRL3 0x00000034
1640−
1641−#define REG_DSI_14nm_PHY_PLL_RESETSM_CNTRL4 0x00000038
1642−
1643−#define REG_DSI_14nm_PHY_PLL_RESETSM_CNTRL5 0x0000003c
1644−
1645−#define REG_DSI_14nm_PHY_PLL_KVCO_DIV_REF1 0x00000040
1646−
1647−#define REG_DSI_14nm_PHY_PLL_KVCO_DIV_REF2 0x00000044
1648−
1649−#define REG_DSI_14nm_PHY_PLL_KVCO_COUNT1 0x00000048
1650−
1651−#define REG_DSI_14nm_PHY_PLL_KVCO_COUNT2 0x0000004c
1652−
1653−#define REG_DSI_14nm_PHY_PLL_VREF_CFG1 0x0000005c
1654−
1655−#define REG_DSI_14nm_PHY_PLL_KVCO_CODE 0x00000058
1656−
1657−#define REG_DSI_14nm_PHY_PLL_VCO_DIV_REF1 0x0000006c
1658−
1659−#define REG_DSI_14nm_PHY_PLL_VCO_DIV_REF2 0x00000070
1660−
1661−#define REG_DSI_14nm_PHY_PLL_VCO_COUNT1 0x00000074
1662−
1663−#define REG_DSI_14nm_PHY_PLL_VCO_COUNT2 0x00000078
1664−
1665−#define REG_DSI_14nm_PHY_PLL_PLLLOCK_CMP1 0x0000007c
1666−
1667−#define REG_DSI_14nm_PHY_PLL_PLLLOCK_CMP2 0x00000080
1668−
1669−#define REG_DSI_14nm_PHY_PLL_PLLLOCK_CMP3 0x00000084
1670−
1671−#define REG_DSI_14nm_PHY_PLL_PLLLOCK_CMP_EN 0x00000088
1672−
1673−#define REG_DSI_14nm_PHY_PLL_PLL_VCO_TUNE 0x0000008c
1674−
1675−#define REG_DSI_14nm_PHY_PLL_DEC_START 0x00000090
1676−
1677−#define REG_DSI_14nm_PHY_PLL_SSC_EN_CENTER 0x00000094
1678−
1679−#define REG_DSI_14nm_PHY_PLL_SSC_ADJ_PER1 0x00000098
1680−
1681−#define REG_DSI_14nm_PHY_PLL_SSC_ADJ_PER2 0x0000009c
1682−
1683−#define REG_DSI_14nm_PHY_PLL_SSC_PER1 0x000000a0
1684−
1685−#define REG_DSI_14nm_PHY_PLL_SSC_PER2 0x000000a4
1686−
1687−#define REG_DSI_14nm_PHY_PLL_SSC_STEP_SIZE1 0x000000a8
1688−
1689−#define REG_DSI_14nm_PHY_PLL_SSC_STEP_SIZE2 0x000000ac
1690−
1691−#define REG_DSI_14nm_PHY_PLL_DIV_FRAC_START1 0x000000b4
1692−
1693−#define REG_DSI_14nm_PHY_PLL_DIV_FRAC_START2 0x000000b8
1694−
1695−#define REG_DSI_14nm_PHY_PLL_DIV_FRAC_START3 0x000000bc
1696−
1697−#define REG_DSI_14nm_PHY_PLL_TXCLK_EN 0x000000c0
1698−
1699−#define REG_DSI_14nm_PHY_PLL_PLL_CRCTRL 0x000000c4
1700−
1701−#define REG_DSI_14nm_PHY_PLL_RESET_SM_READY_STATUS 0x000000cc
1702−
1703−#define REG_DSI_14nm_PHY_PLL_PLL_MISC1 0x000000e8
1704−
1705−#define REG_DSI_14nm_PHY_PLL_CP_SET_CUR 0x000000f0
1706−
1707−#define REG_DSI_14nm_PHY_PLL_PLL_ICPMSET 0x000000f4
1708−
1709−#define REG_DSI_14nm_PHY_PLL_PLL_ICPCSET 0x000000f8
1710−
1711−#define REG_DSI_14nm_PHY_PLL_PLL_ICP_SET 0x000000fc
1712−
1713−#define REG_DSI_14nm_PHY_PLL_PLL_LPF1 0x00000100
1714−
1715−#define REG_DSI_14nm_PHY_PLL_PLL_LPF2_POSTDIV 0x00000104
1716−
1717−#define REG_DSI_14nm_PHY_PLL_PLL_BANDGAP 0x00000108
1718−
1719−#define REG_DSI_10nm_PHY_CMN_REVISION_ID0 0x00000000
1720−
1721−#define REG_DSI_10nm_PHY_CMN_REVISION_ID1 0x00000004
1722−
1723−#define REG_DSI_10nm_PHY_CMN_REVISION_ID2 0x00000008
1724−
1725−#define REG_DSI_10nm_PHY_CMN_REVISION_ID3 0x0000000c
1726−
1727−#define REG_DSI_10nm_PHY_CMN_CLK_CFG0 0x00000010
1728−
1729−#define REG_DSI_10nm_PHY_CMN_CLK_CFG1 0x00000014
1730−
1731−#define REG_DSI_10nm_PHY_CMN_GLBL_CTRL 0x00000018
1732−
1733−#define REG_DSI_10nm_PHY_CMN_RBUF_CTRL 0x0000001c
1734−
1735−#define REG_DSI_10nm_PHY_CMN_VREG_CTRL 0x00000020
1736−
1737−#define REG_DSI_10nm_PHY_CMN_CTRL_0 0x00000024
1738−
1739−#define REG_DSI_10nm_PHY_CMN_CTRL_1 0x00000028
1740−
1741−#define REG_DSI_10nm_PHY_CMN_CTRL_2 0x0000002c
1742−
1743−#define REG_DSI_10nm_PHY_CMN_LANE_CFG0 0x00000030
1744−
1745−#define REG_DSI_10nm_PHY_CMN_LANE_CFG1 0x00000034
1746−
1747−#define REG_DSI_10nm_PHY_CMN_PLL_CNTRL 0x00000038
1748−
1749−#define REG_DSI_10nm_PHY_CMN_LANE_CTRL0 0x00000098
1750−
1751−#define REG_DSI_10nm_PHY_CMN_LANE_CTRL1 0x0000009c
1752−
1753−#define REG_DSI_10nm_PHY_CMN_LANE_CTRL2 0x000000a0
1754−
1755−#define REG_DSI_10nm_PHY_CMN_LANE_CTRL3 0x000000a4
1756−
1757−#define REG_DSI_10nm_PHY_CMN_LANE_CTRL4 0x000000a8
1758−
1759−#define REG_DSI_10nm_PHY_CMN_TIMING_CTRL_0 0x000000ac
1760−
1761−#define REG_DSI_10nm_PHY_CMN_TIMING_CTRL_1 0x000000b0
1762−
1763−#define REG_DSI_10nm_PHY_CMN_TIMING_CTRL_2 0x000000b4
1764−
1765−#define REG_DSI_10nm_PHY_CMN_TIMING_CTRL_3 0x000000b8
1766−
1767−#define REG_DSI_10nm_PHY_CMN_TIMING_CTRL_4 0x000000bc
1768−
1769−#define REG_DSI_10nm_PHY_CMN_TIMING_CTRL_5 0x000000c0
1770−
1771−#define REG_DSI_10nm_PHY_CMN_TIMING_CTRL_6 0x000000c4
1772−
1773−#define REG_DSI_10nm_PHY_CMN_TIMING_CTRL_7 0x000000c8
1774−
1775−#define REG_DSI_10nm_PHY_CMN_TIMING_CTRL_8 0x000000cc
1776−
1777−#define REG_DSI_10nm_PHY_CMN_TIMING_CTRL_9 0x000000d0
1778−
1779−#define REG_DSI_10nm_PHY_CMN_TIMING_CTRL_10 0x000000d4
1780−
1781−#define REG_DSI_10nm_PHY_CMN_TIMING_CTRL_11 0x000000d8
1782−
1783−#define REG_DSI_10nm_PHY_CMN_PHY_STATUS 0x000000ec
1784−
1785−#define REG_DSI_10nm_PHY_CMN_LANE_STATUS0 0x000000f4
1786−
1787−#define REG_DSI_10nm_PHY_CMN_LANE_STATUS1 0x000000f8
1788−
1789−static inline uint32_t REG_DSI_10nm_PHY_LN(uint32_t i0) { return 0x00000000 + 0x80*i0; }
1790−
1791−static inline uint32_t REG_DSI_10nm_PHY_LN_CFG0(uint32_t i0) { return 0x00000000 + 0x80*i0; }
1792−
1793−static inline uint32_t REG_DSI_10nm_PHY_LN_CFG1(uint32_t i0) { return 0x00000004 + 0x80*i0; }
1794−
1795−static inline uint32_t REG_DSI_10nm_PHY_LN_CFG2(uint32_t i0) { return 0x00000008 + 0x80*i0; }
1796−
1797−static inline uint32_t REG_DSI_10nm_PHY_LN_CFG3(uint32_t i0) { return 0x0000000c + 0x80*i0; }
1798−
1799−static inline uint32_t REG_DSI_10nm_PHY_LN_TEST_DATAPATH(uint32_t i0) { return 0x00000010 + 0x80*i0; }
1800−
1801−static inline uint32_t REG_DSI_10nm_PHY_LN_PIN_SWAP(uint32_t i0) { return 0x00000014 + 0x80*i0; }
1802−
1803−static inline uint32_t REG_DSI_10nm_PHY_LN_HSTX_STR_CTRL(uint32_t i0) { return 0x00000018 + 0x80*i0; }
1804−
1805−static inline uint32_t REG_DSI_10nm_PHY_LN_OFFSET_TOP_CTRL(uint32_t i0) { return 0x0000001c + 0x80*i0; }
1806−
1807−static inline uint32_t REG_DSI_10nm_PHY_LN_OFFSET_BOT_CTRL(uint32_t i0) { return 0x00000020 + 0x80*i0; }
1808−
1809−static inline uint32_t REG_DSI_10nm_PHY_LN_LPTX_STR_CTRL(uint32_t i0) { return 0x00000024 + 0x80*i0; }
1810−
1811−static inline uint32_t REG_DSI_10nm_PHY_LN_LPRX_CTRL(uint32_t i0) { return 0x00000028 + 0x80*i0; }
1812−
1813−static inline uint32_t REG_DSI_10nm_PHY_LN_TX_DCTRL(uint32_t i0) { return 0x0000002c + 0x80*i0; }
1814−
1815−#define REG_DSI_10nm_PHY_PLL_ANALOG_CONTROLS_ONE 0x00000000
1816−
1817−#define REG_DSI_10nm_PHY_PLL_ANALOG_CONTROLS_TWO 0x00000004
1818−
1819−#define REG_DSI_10nm_PHY_PLL_ANALOG_CONTROLS_THREE 0x00000010
1820−
1821−#define REG_DSI_10nm_PHY_PLL_DSM_DIVIDER 0x0000001c
1822−
1823−#define REG_DSI_10nm_PHY_PLL_FEEDBACK_DIVIDER 0x00000020
1824−
1825−#define REG_DSI_10nm_PHY_PLL_SYSTEM_MUXES 0x00000024
1826−
1827−#define REG_DSI_10nm_PHY_PLL_CMODE 0x0000002c
1828−
1829−#define REG_DSI_10nm_PHY_PLL_CALIBRATION_SETTINGS 0x00000030
1830−
1831−#define REG_DSI_10nm_PHY_PLL_BAND_SEL_CAL_SETTINGS_THREE 0x00000054
1832−
1833−#define REG_DSI_10nm_PHY_PLL_FREQ_DETECT_SETTINGS_ONE 0x00000064
1834−
1835−#define REG_DSI_10nm_PHY_PLL_PFILT 0x0000007c
1836−
1837−#define REG_DSI_10nm_PHY_PLL_IFILT 0x00000080
1838−
1839−#define REG_DSI_10nm_PHY_PLL_OUTDIV 0x00000094
1840−
1841−#define REG_DSI_10nm_PHY_PLL_CORE_OVERRIDE 0x000000a4
1842−
1843−#define REG_DSI_10nm_PHY_PLL_CORE_INPUT_OVERRIDE 0x000000a8
1844−
1845−#define REG_DSI_10nm_PHY_PLL_PLL_DIGITAL_TIMERS_TWO 0x000000b4
1846−
1847−#define REG_DSI_10nm_PHY_PLL_DECIMAL_DIV_START_1 0x000000cc
1848−
1849−#define REG_DSI_10nm_PHY_PLL_FRAC_DIV_START_LOW_1 0x000000d0
1850−
1851−#define REG_DSI_10nm_PHY_PLL_FRAC_DIV_START_MID_1 0x000000d4
1852−
1853−#define REG_DSI_10nm_PHY_PLL_FRAC_DIV_START_HIGH_1 0x000000d8
1854−
1855−#define REG_DSI_10nm_PHY_PLL_SSC_STEPSIZE_LOW_1 0x0000010c
1856−
1857−#define REG_DSI_10nm_PHY_PLL_SSC_STEPSIZE_HIGH_1 0x00000110
1858−
1859−#define REG_DSI_10nm_PHY_PLL_SSC_DIV_PER_LOW_1 0x00000114
1860−
1861−#define REG_DSI_10nm_PHY_PLL_SSC_DIV_PER_HIGH_1 0x00000118
1862−
1863−#define REG_DSI_10nm_PHY_PLL_SSC_DIV_ADJPER_LOW_1 0x0000011c
1864−
1865−#define REG_DSI_10nm_PHY_PLL_SSC_DIV_ADJPER_HIGH_1 0x00000120
1866−
1867−#define REG_DSI_10nm_PHY_PLL_SSC_CONTROL 0x0000013c
1868−
1869−#define REG_DSI_10nm_PHY_PLL_PLL_OUTDIV_RATE 0x00000140
1870−
1871−#define REG_DSI_10nm_PHY_PLL_PLL_LOCKDET_RATE_1 0x00000144
1872−
1873−#define REG_DSI_10nm_PHY_PLL_PLL_PROP_GAIN_RATE_1 0x0000014c
1874−
1875−#define REG_DSI_10nm_PHY_PLL_PLL_BAND_SET_RATE_1 0x00000154
1876−
1877−#define REG_DSI_10nm_PHY_PLL_PLL_INT_GAIN_IFILT_BAND_1 0x0000015c
1878−
1879−#define REG_DSI_10nm_PHY_PLL_PLL_FL_INT_GAIN_PFILT_BAND_1 0x00000164
1880−
1881−#define REG_DSI_10nm_PHY_PLL_PLL_LOCK_OVERRIDE 0x00000180
1882−
1883−#define REG_DSI_10nm_PHY_PLL_PLL_LOCK_DELAY 0x00000184
1884−
1885−#define REG_DSI_10nm_PHY_PLL_CLOCK_INVERTERS 0x0000018c
1886−
1887−#define REG_DSI_10nm_PHY_PLL_COMMON_STATUS_ONE 0x000001a0
1888−
1889−#define REG_DSI_7nm_PHY_CMN_REVISION_ID0 0x00000000
1890−
1891−#define REG_DSI_7nm_PHY_CMN_REVISION_ID1 0x00000004
1892−
1893−#define REG_DSI_7nm_PHY_CMN_REVISION_ID2 0x00000008
1894−
1895−#define REG_DSI_7nm_PHY_CMN_REVISION_ID3 0x0000000c
1896−
1897−#define REG_DSI_7nm_PHY_CMN_CLK_CFG0 0x00000010
1898−
1899−#define REG_DSI_7nm_PHY_CMN_CLK_CFG1 0x00000014
1900−
1901−#define REG_DSI_7nm_PHY_CMN_GLBL_CTRL 0x00000018
1902−
1903−#define REG_DSI_7nm_PHY_CMN_RBUF_CTRL 0x0000001c
1904−
1905−#define REG_DSI_7nm_PHY_CMN_VREG_CTRL_0 0x00000020
1906−
1907−#define REG_DSI_7nm_PHY_CMN_CTRL_0 0x00000024
1908−
1909−#define REG_DSI_7nm_PHY_CMN_CTRL_1 0x00000028
1910−
1911−#define REG_DSI_7nm_PHY_CMN_CTRL_2 0x0000002c
1912−
1913−#define REG_DSI_7nm_PHY_CMN_CTRL_3 0x00000030
1914−
1915−#define REG_DSI_7nm_PHY_CMN_LANE_CFG0 0x00000034
1916−
1917−#define REG_DSI_7nm_PHY_CMN_LANE_CFG1 0x00000038
1918−
1919−#define REG_DSI_7nm_PHY_CMN_PLL_CNTRL 0x0000003c
1920−
1921−#define REG_DSI_7nm_PHY_CMN_DPHY_SOT 0x00000040
1922−
1923−#define REG_DSI_7nm_PHY_CMN_LANE_CTRL0 0x000000a0
1924−
1925−#define REG_DSI_7nm_PHY_CMN_LANE_CTRL1 0x000000a4
1926−
1927−#define REG_DSI_7nm_PHY_CMN_LANE_CTRL2 0x000000a8
1928−
1929−#define REG_DSI_7nm_PHY_CMN_LANE_CTRL3 0x000000ac
1930−
1931−#define REG_DSI_7nm_PHY_CMN_LANE_CTRL4 0x000000b0
1932−
1933−#define REG_DSI_7nm_PHY_CMN_TIMING_CTRL_0 0x000000b4
1934−
1935−#define REG_DSI_7nm_PHY_CMN_TIMING_CTRL_1 0x000000b8
1936−
1937−#define REG_DSI_7nm_PHY_CMN_TIMING_CTRL_2 0x000000bc
1938−
1939−#define REG_DSI_7nm_PHY_CMN_TIMING_CTRL_3 0x000000c0
1940−
1941−#define REG_DSI_7nm_PHY_CMN_TIMING_CTRL_4 0x000000c4
1942−
1943−#define REG_DSI_7nm_PHY_CMN_TIMING_CTRL_5 0x000000c8
1944−
1945−#define REG_DSI_7nm_PHY_CMN_TIMING_CTRL_6 0x000000cc
1946−
1947−#define REG_DSI_7nm_PHY_CMN_TIMING_CTRL_7 0x000000d0
1948−
1949−#define REG_DSI_7nm_PHY_CMN_TIMING_CTRL_8 0x000000d4
1950−
1951−#define REG_DSI_7nm_PHY_CMN_TIMING_CTRL_9 0x000000d8
1952−
1953−#define REG_DSI_7nm_PHY_CMN_TIMING_CTRL_10 0x000000dc
1954−
1955−#define REG_DSI_7nm_PHY_CMN_TIMING_CTRL_11 0x000000e0
1956−
1957−#define REG_DSI_7nm_PHY_CMN_TIMING_CTRL_12 0x000000e4
1958−
1959−#define REG_DSI_7nm_PHY_CMN_TIMING_CTRL_13 0x000000e8
1960−
1961−#define REG_DSI_7nm_PHY_CMN_GLBL_HSTX_STR_CTRL_0 0x000000ec
1962−
1963−#define REG_DSI_7nm_PHY_CMN_GLBL_HSTX_STR_CTRL_1 0x000000f0
1964−
1965−#define REG_DSI_7nm_PHY_CMN_GLBL_RESCODE_OFFSET_TOP_CTRL 0x000000f4
1966−
1967−#define REG_DSI_7nm_PHY_CMN_GLBL_RESCODE_OFFSET_BOT_CTRL 0x000000f8
1968−
1969−#define REG_DSI_7nm_PHY_CMN_GLBL_RESCODE_OFFSET_MID_CTRL 0x000000fc
1970−
1971−#define REG_DSI_7nm_PHY_CMN_GLBL_LPTX_STR_CTRL 0x00000100
1972−
1973−#define REG_DSI_7nm_PHY_CMN_GLBL_PEMPH_CTRL_0 0x00000104
1974−
1975−#define REG_DSI_7nm_PHY_CMN_GLBL_PEMPH_CTRL_1 0x00000108
1976−
1977−#define REG_DSI_7nm_PHY_CMN_GLBL_STR_SWI_CAL_SEL_CTRL 0x0000010c
1978−
1979−#define REG_DSI_7nm_PHY_CMN_VREG_CTRL_1 0x00000110
1980−
1981−#define REG_DSI_7nm_PHY_CMN_CTRL_4 0x00000114
1982−
1983−#define REG_DSI_7nm_PHY_CMN_GLBL_DIGTOP_SPARE4 0x00000128
1984−
1985−#define REG_DSI_7nm_PHY_CMN_PHY_STATUS 0x00000140
1986−
1987−#define REG_DSI_7nm_PHY_CMN_LANE_STATUS0 0x00000148
1988−
1989−#define REG_DSI_7nm_PHY_CMN_LANE_STATUS1 0x0000014c
1990−
1991−static inline uint32_t REG_DSI_7nm_PHY_LN(uint32_t i0) { return 0x00000000 + 0x80*i0; }
1992−
1993−static inline uint32_t REG_DSI_7nm_PHY_LN_CFG0(uint32_t i0) { return 0x00000000 + 0x80*i0; }
1994−
1995−static inline uint32_t REG_DSI_7nm_PHY_LN_CFG1(uint32_t i0) { return 0x00000004 + 0x80*i0; }
1996−
1997−static inline uint32_t REG_DSI_7nm_PHY_LN_CFG2(uint32_t i0) { return 0x00000008 + 0x80*i0; }
1998−
1999−static inline uint32_t REG_DSI_7nm_PHY_LN_TEST_DATAPATH(uint32_t i0) { return 0x0000000c + 0x80*i0; }
2000−
2001−static inline uint32_t REG_DSI_7nm_PHY_LN_PIN_SWAP(uint32_t i0) { return 0x00000010 + 0x80*i0; }
2002−
2003−static inline uint32_t REG_DSI_7nm_PHY_LN_LPRX_CTRL(uint32_t i0) { return 0x00000014 + 0x80*i0; }
2004−
2005−static inline uint32_t REG_DSI_7nm_PHY_LN_TX_DCTRL(uint32_t i0) { return 0x00000018 + 0x80*i0; }
2006−
2007−#define REG_DSI_7nm_PHY_PLL_ANALOG_CONTROLS_ONE 0x00000000
2008−
2009−#define REG_DSI_7nm_PHY_PLL_ANALOG_CONTROLS_TWO 0x00000004
2010−
2011−#define REG_DSI_7nm_PHY_PLL_INT_LOOP_SETTINGS 0x00000008
2012−
2013−#define REG_DSI_7nm_PHY_PLL_INT_LOOP_SETTINGS_TWO 0x0000000c
2014−
2015−#define REG_DSI_7nm_PHY_PLL_ANALOG_CONTROLS_THREE 0x00000010
2016−
2017−#define REG_DSI_7nm_PHY_PLL_ANALOG_CONTROLS_FOUR 0x00000014
2018−
2019−#define REG_DSI_7nm_PHY_PLL_ANALOG_CONTROLS_FIVE 0x00000018
2020−
2021−#define REG_DSI_7nm_PHY_PLL_INT_LOOP_CONTROLS 0x0000001c
2022−
2023−#define REG_DSI_7nm_PHY_PLL_DSM_DIVIDER 0x00000020
2024−
2025−#define REG_DSI_7nm_PHY_PLL_FEEDBACK_DIVIDER 0x00000024
2026−
2027−#define REG_DSI_7nm_PHY_PLL_SYSTEM_MUXES 0x00000028
2028−
2029−#define REG_DSI_7nm_PHY_PLL_FREQ_UPDATE_CONTROL_OVERRIDES 0x0000002c
2030−
2031−#define REG_DSI_7nm_PHY_PLL_CMODE 0x00000030
2032−
2033−#define REG_DSI_7nm_PHY_PLL_PSM_CTRL 0x00000034
2034−
2035−#define REG_DSI_7nm_PHY_PLL_RSM_CTRL 0x00000038
2036−
2037−#define REG_DSI_7nm_PHY_PLL_VCO_TUNE_MAP 0x0000003c
2038−
2039−#define REG_DSI_7nm_PHY_PLL_PLL_CNTRL 0x00000040
2040−
2041−#define REG_DSI_7nm_PHY_PLL_CALIBRATION_SETTINGS 0x00000044
2042−
2043−#define REG_DSI_7nm_PHY_PLL_BAND_SEL_CAL_TIMER_LOW 0x00000048
2044−
2045−#define REG_DSI_7nm_PHY_PLL_BAND_SEL_CAL_TIMER_HIGH 0x0000004c
2046−
2047−#define REG_DSI_7nm_PHY_PLL_BAND_SEL_CAL_SETTINGS 0x00000050
2048−
2049−#define REG_DSI_7nm_PHY_PLL_BAND_SEL_MIN 0x00000054
2050−
2051−#define REG_DSI_7nm_PHY_PLL_BAND_SEL_MAX 0x00000058
2052−
2053−#define REG_DSI_7nm_PHY_PLL_BAND_SEL_PFILT 0x0000005c
2054−
2055−#define REG_DSI_7nm_PHY_PLL_BAND_SEL_IFILT 0x00000060
2056−
2057−#define REG_DSI_7nm_PHY_PLL_BAND_SEL_CAL_SETTINGS_TWO 0x00000064
2058−
2059−#define REG_DSI_7nm_PHY_PLL_BAND_SEL_CAL_SETTINGS_THREE 0x00000068
2060−
2061−#define REG_DSI_7nm_PHY_PLL_BAND_SEL_CAL_SETTINGS_FOUR 0x0000006c
2062−
2063−#define REG_DSI_7nm_PHY_PLL_BAND_SEL_ICODE_HIGH 0x00000070
2064−
2065−#define REG_DSI_7nm_PHY_PLL_BAND_SEL_ICODE_LOW 0x00000074
2066−
2067−#define REG_DSI_7nm_PHY_PLL_FREQ_DETECT_SETTINGS_ONE 0x00000078
2068−
2069−#define REG_DSI_7nm_PHY_PLL_FREQ_DETECT_THRESH 0x0000007c
2070−
2071−#define REG_DSI_7nm_PHY_PLL_FREQ_DET_REFCLK_HIGH 0x00000080
2072−
2073−#define REG_DSI_7nm_PHY_PLL_FREQ_DET_REFCLK_LOW 0x00000084
2074−
2075−#define REG_DSI_7nm_PHY_PLL_FREQ_DET_PLLCLK_HIGH 0x00000088
2076−
2077−#define REG_DSI_7nm_PHY_PLL_FREQ_DET_PLLCLK_LOW 0x0000008c
2078−
2079−#define REG_DSI_7nm_PHY_PLL_PFILT 0x00000090
2080−
2081−#define REG_DSI_7nm_PHY_PLL_IFILT 0x00000094
2082−
2083−#define REG_DSI_7nm_PHY_PLL_PLL_GAIN 0x00000098
2084−
2085−#define REG_DSI_7nm_PHY_PLL_ICODE_LOW 0x0000009c
2086−
2087−#define REG_DSI_7nm_PHY_PLL_ICODE_HIGH 0x000000a0
2088−
2089−#define REG_DSI_7nm_PHY_PLL_LOCKDET 0x000000a4
2090−
2091−#define REG_DSI_7nm_PHY_PLL_OUTDIV 0x000000a8
2092−
2093−#define REG_DSI_7nm_PHY_PLL_FASTLOCK_CONTROL 0x000000ac
2094−
2095−#define REG_DSI_7nm_PHY_PLL_PASS_OUT_OVERRIDE_ONE 0x000000b0
2096−
2097−#define REG_DSI_7nm_PHY_PLL_PASS_OUT_OVERRIDE_TWO 0x000000b4
2098−
2099−#define REG_DSI_7nm_PHY_PLL_CORE_OVERRIDE 0x000000b8
2100−
2101−#define REG_DSI_7nm_PHY_PLL_CORE_INPUT_OVERRIDE 0x000000bc
2102−
2103−#define REG_DSI_7nm_PHY_PLL_RATE_CHANGE 0x000000c0
2104−
2105−#define REG_DSI_7nm_PHY_PLL_PLL_DIGITAL_TIMERS 0x000000c4
2106−
2107−#define REG_DSI_7nm_PHY_PLL_PLL_DIGITAL_TIMERS_TWO 0x000000c8
2108−
2109−#define REG_DSI_7nm_PHY_PLL_DECIMAL_DIV_START 0x000000cc
2110−
2111−#define REG_DSI_7nm_PHY_PLL_FRAC_DIV_START_LOW 0x000000d0
2112−
2113−#define REG_DSI_7nm_PHY_PLL_FRAC_DIV_START_MID 0x000000d4
2114−
2115−#define REG_DSI_7nm_PHY_PLL_FRAC_DIV_START_HIGH 0x000000d8
2116−
2117−#define REG_DSI_7nm_PHY_PLL_DEC_FRAC_MUXES 0x000000dc
2118−
2119−#define REG_DSI_7nm_PHY_PLL_DECIMAL_DIV_START_1 0x000000e0
2120−
2121−#define REG_DSI_7nm_PHY_PLL_FRAC_DIV_START_LOW_1 0x000000e4
2122−
2123−#define REG_DSI_7nm_PHY_PLL_FRAC_DIV_START_MID_1 0x000000e8
2124−
2125−#define REG_DSI_7nm_PHY_PLL_FRAC_DIV_START_HIGH_1 0x000000ec
2126−
2127−#define REG_DSI_7nm_PHY_PLL_DECIMAL_DIV_START_2 0x000000f0
2128−
2129−#define REG_DSI_7nm_PHY_PLL_FRAC_DIV_START_LOW_2 0x000000f4
2130−
2131−#define REG_DSI_7nm_PHY_PLL_FRAC_DIV_START_MID_2 0x000000f8
2132−
2133−#define REG_DSI_7nm_PHY_PLL_FRAC_DIV_START_HIGH_2 0x000000fc
2134−
2135−#define REG_DSI_7nm_PHY_PLL_MASH_CONTROL 0x00000100
2136−
2137−#define REG_DSI_7nm_PHY_PLL_SSC_STEPSIZE_LOW 0x00000104
2138−
2139−#define REG_DSI_7nm_PHY_PLL_SSC_STEPSIZE_HIGH 0x00000108
2140−
2141−#define REG_DSI_7nm_PHY_PLL_SSC_DIV_PER_LOW 0x0000010c
2142−
2143−#define REG_DSI_7nm_PHY_PLL_SSC_DIV_PER_HIGH 0x00000110
2144−
2145−#define REG_DSI_7nm_PHY_PLL_SSC_ADJPER_LOW 0x00000114
2146−
2147−#define REG_DSI_7nm_PHY_PLL_SSC_ADJPER_HIGH 0x00000118
2148−
2149−#define REG_DSI_7nm_PHY_PLL_SSC_MUX_CONTROL 0x0000011c
2150−
2151−#define REG_DSI_7nm_PHY_PLL_SSC_STEPSIZE_LOW_1 0x00000120
2152−
2153−#define REG_DSI_7nm_PHY_PLL_SSC_STEPSIZE_HIGH_1 0x00000124
2154−
2155−#define REG_DSI_7nm_PHY_PLL_SSC_DIV_PER_LOW_1 0x00000128
2156−
2157−#define REG_DSI_7nm_PHY_PLL_SSC_DIV_PER_HIGH_1 0x0000012c
2158−
2159−#define REG_DSI_7nm_PHY_PLL_SSC_ADJPER_LOW_1 0x00000130
2160−
2161−#define REG_DSI_7nm_PHY_PLL_SSC_ADJPER_HIGH_1 0x00000134
2162−
2163−#define REG_DSI_7nm_PHY_PLL_SSC_STEPSIZE_LOW_2 0x00000138
2164−
2165−#define REG_DSI_7nm_PHY_PLL_SSC_STEPSIZE_HIGH_2 0x0000013c
2166−
2167−#define REG_DSI_7nm_PHY_PLL_SSC_DIV_PER_LOW_2 0x00000140
2168−
2169−#define REG_DSI_7nm_PHY_PLL_SSC_DIV_PER_HIGH_2 0x00000144
2170−
2171−#define REG_DSI_7nm_PHY_PLL_SSC_ADJPER_LOW_2 0x00000148
2172−
2173−#define REG_DSI_7nm_PHY_PLL_SSC_ADJPER_HIGH_2 0x0000014c
2174−
2175−#define REG_DSI_7nm_PHY_PLL_SSC_CONTROL 0x00000150
2176−
2177−#define REG_DSI_7nm_PHY_PLL_PLL_OUTDIV_RATE 0x00000154
2178−
2179−#define REG_DSI_7nm_PHY_PLL_PLL_LOCKDET_RATE_1 0x00000158
2180−
2181−#define REG_DSI_7nm_PHY_PLL_PLL_LOCKDET_RATE_2 0x0000015c
2182−
2183−#define REG_DSI_7nm_PHY_PLL_PLL_PROP_GAIN_RATE_1 0x00000160
2184−
2185−#define REG_DSI_7nm_PHY_PLL_PLL_PROP_GAIN_RATE_2 0x00000164
2186−
2187−#define REG_DSI_7nm_PHY_PLL_PLL_BAND_SEL_RATE_1 0x00000168
2188−
2189−#define REG_DSI_7nm_PHY_PLL_PLL_BAND_SEL_RATE_2 0x0000016c
2190−
2191−#define REG_DSI_7nm_PHY_PLL_PLL_INT_GAIN_IFILT_BAND_1 0x00000170
2192−
2193−#define REG_DSI_7nm_PHY_PLL_PLL_INT_GAIN_IFILT_BAND_2 0x00000174
2194−
2195−#define REG_DSI_7nm_PHY_PLL_PLL_FL_INT_GAIN_PFILT_BAND_1 0x00000178
2196−
2197−#define REG_DSI_7nm_PHY_PLL_PLL_FL_INT_GAIN_PFILT_BAND_2 0x0000017c
2198−
2199−#define REG_DSI_7nm_PHY_PLL_PLL_FASTLOCK_EN_BAND 0x00000180
2200−
2201−#define REG_DSI_7nm_PHY_PLL_FREQ_TUNE_ACCUM_INIT_MID 0x00000184
2202−
2203−#define REG_DSI_7nm_PHY_PLL_FREQ_TUNE_ACCUM_INIT_HIGH 0x00000188
2204−
2205−#define REG_DSI_7nm_PHY_PLL_FREQ_TUNE_ACCUM_INIT_MUX 0x0000018c
2206−
2207−#define REG_DSI_7nm_PHY_PLL_PLL_LOCK_OVERRIDE 0x00000190
2208−
2209−#define REG_DSI_7nm_PHY_PLL_PLL_LOCK_DELAY 0x00000194
2210−
2211−#define REG_DSI_7nm_PHY_PLL_PLL_LOCK_MIN_DELAY 0x00000198
2212−
2213−#define REG_DSI_7nm_PHY_PLL_CLOCK_INVERTERS 0x0000019c
2214−
2215−#define REG_DSI_7nm_PHY_PLL_SPARE_AND_JPC_OVERRIDES 0x000001a0
2216−
2217−#define REG_DSI_7nm_PHY_PLL_BIAS_CONTROL_1 0x000001a4
2218−
2219−#define REG_DSI_7nm_PHY_PLL_BIAS_CONTROL_2 0x000001a8
2220−
2221−#define REG_DSI_7nm_PHY_PLL_ALOG_OBSV_BUS_CTRL_1 0x000001ac
2222−
2223−#define REG_DSI_7nm_PHY_PLL_COMMON_STATUS_ONE 0x000001b0
2224−
2225−#define REG_DSI_7nm_PHY_PLL_COMMON_STATUS_TWO 0x000001b4
2226−
2227−#define REG_DSI_7nm_PHY_PLL_BAND_SEL_CAL 0x000001b8
2228−
2229−#define REG_DSI_7nm_PHY_PLL_ICODE_ACCUM_STATUS_LOW 0x000001bc
2230−
2231−#define REG_DSI_7nm_PHY_PLL_ICODE_ACCUM_STATUS_HIGH 0x000001c0
2232−
2233−#define REG_DSI_7nm_PHY_PLL_FD_OUT_LOW 0x000001c4
2234−
2235−#define REG_DSI_7nm_PHY_PLL_FD_OUT_HIGH 0x000001c8
2236−
2237−#define REG_DSI_7nm_PHY_PLL_ALOG_OBSV_BUS_STATUS_1 0x000001cc
2238−
2239−#define REG_DSI_7nm_PHY_PLL_PLL_MISC_CONFIG 0x000001d0
2240−
2241−#define REG_DSI_7nm_PHY_PLL_FLL_CONFIG 0x000001d4
2242−
2243−#define REG_DSI_7nm_PHY_PLL_FLL_FREQ_ACQ_TIME 0x000001d8
2244−
2245−#define REG_DSI_7nm_PHY_PLL_FLL_CODE0 0x000001dc
2246−
2247−#define REG_DSI_7nm_PHY_PLL_FLL_CODE1 0x000001e0
2248−
2249−#define REG_DSI_7nm_PHY_PLL_FLL_GAIN0 0x000001e4
2250−
2251−#define REG_DSI_7nm_PHY_PLL_FLL_GAIN1 0x000001e8
2252−
2253−#define REG_DSI_7nm_PHY_PLL_SW_RESET 0x000001ec
2254−
2255−#define REG_DSI_7nm_PHY_PLL_FAST_PWRUP 0x000001f0
2256−
2257−#define REG_DSI_7nm_PHY_PLL_LOCKTIME0 0x000001f4
2258−
2259−#define REG_DSI_7nm_PHY_PLL_LOCKTIME1 0x000001f8
2260−
2261−#define REG_DSI_7nm_PHY_PLL_DEBUG_BUS_SEL 0x000001fc
2262−
2263−#define REG_DSI_7nm_PHY_PLL_DEBUG_BUS0 0x00000200
2264−
2265−#define REG_DSI_7nm_PHY_PLL_DEBUG_BUS1 0x00000204
2266−
2267−#define REG_DSI_7nm_PHY_PLL_DEBUG_BUS2 0x00000208
2268−
2269−#define REG_DSI_7nm_PHY_PLL_DEBUG_BUS3 0x0000020c
2270−
2271−#define REG_DSI_7nm_PHY_PLL_ANALOG_FLL_CONTROL_OVERRIDES 0x00000210
2272−
2273−#define REG_DSI_7nm_PHY_PLL_VCO_CONFIG 0x00000214
2274−
2275−#define REG_DSI_7nm_PHY_PLL_VCO_CAL_CODE1_MODE0_STATUS 0x00000218
2276−
2277−#define REG_DSI_7nm_PHY_PLL_VCO_CAL_CODE1_MODE1_STATUS 0x0000021c
2278−
2279−#define REG_DSI_7nm_PHY_PLL_RESET_SM_STATUS 0x00000220
2280−
2281−#define REG_DSI_7nm_PHY_PLL_TDC_OFFSET 0x00000224
2282−
2283−#define REG_DSI_7nm_PHY_PLL_PS3_PWRDOWN_CONTROLS 0x00000228
2284−
2285−#define REG_DSI_7nm_PHY_PLL_PS4_PWRDOWN_CONTROLS 0x0000022c
2286−
2287−#define REG_DSI_7nm_PHY_PLL_PLL_RST_CONTROLS 0x00000230
2288−
2289−#define REG_DSI_7nm_PHY_PLL_GEAR_BAND_SELECT_CONTROLS 0x00000234
2290−
2291−#define REG_DSI_7nm_PHY_PLL_PSM_CLK_CONTROLS 0x00000238
2292−
2293−#define REG_DSI_7nm_PHY_PLL_SYSTEM_MUXES_2 0x0000023c
2294−
2295−#define REG_DSI_7nm_PHY_PLL_VCO_CONFIG_1 0x00000240
2296−
2297−#define REG_DSI_7nm_PHY_PLL_VCO_CONFIG_2 0x00000244
2298−
2299−#define REG_DSI_7nm_PHY_PLL_CLOCK_INVERTERS_1 0x00000248
2300−
2301−#define REG_DSI_7nm_PHY_PLL_CLOCK_INVERTERS_2 0x0000024c
2302−
2303−#define REG_DSI_7nm_PHY_PLL_CMODE_1 0x00000250
2304−
2305−#define REG_DSI_7nm_PHY_PLL_CMODE_2 0x00000254
2306−
2307−#define REG_DSI_7nm_PHY_PLL_ANALOG_CONTROLS_FIVE_1 0x00000258
2308−
2309−#define REG_DSI_7nm_PHY_PLL_ANALOG_CONTROLS_FIVE_2 0x0000025c
632+#define REG_DSI_CPHY_MODE_CTRL 0x000002d4
2310633
2311−#define REG_DSI_7nm_PHY_PLL_PERF_OPTIMIZE 0x00000260
2312634
2313635 #endif /* DSI_XML */
drivers/gpu/drm/msm/dsi/dsi_host.c+19−11
@@ -102,6 +102,7 @@ struct msm_dsi_host { · 101 unmodified lines
102102 int id;
103103
104104 void __iomem *ctrl_base;
105+ phys_addr_t ctrl_size;
105106 struct regulator_bulk_data supplies[DSI_DEV_REGULATOR_MAX];
106107
107108 struct clk *bus_clks[DSI_BUS_CLK_MAX];
@@ -113,8 +114,6 @@ struct msm_dsi_host { · 5 unmodified lines
113114 struct clk *pixel_clk_src;
114115 struct clk *byte_intf_clk;
115116
116− struct opp_table *opp_table;
117−
118117 u32 byte_clk_rate;
119118 u32 pixel_clk_rate;
120119 u32 esc_clk_rate;
@@ -1092,7 +1091,7 @@ int dsi_tx_buf_alloc_6g(struct msm_dsi_host *msm_host, int size) · 971 unmodified lines
10921091 uint64_t iova;
10931092 u8 *data;
10941093
1095− data = msm_gem_kernel_new(dev, size, MSM_BO_UNCACHED,
1094+ data = msm_gem_kernel_new(dev, size, MSM_BO_WC,
10961095 priv->kms->aspace,
10971096 &msm_host->tx_gem_obj, &iova);
10981097
@@ -1839,7 +1838,7 @@ int msm_dsi_host_init(struct msm_dsi *msm_dsi) · 740 unmodified lines
18391838 goto fail;
18401839 }
18411840
1842− msm_host->ctrl_base = msm_ioremap(pdev, "dsi_ctrl", "DSI CTRL");
1841+ msm_host->ctrl_base = msm_ioremap_size(pdev, "dsi_ctrl", "DSI CTRL", &msm_host->ctrl_size);
18431842 if (IS_ERR(msm_host->ctrl_base)) {
18441843 pr_err("%s: unable to map Dsi ctrl base\n", __func__);
18451844 ret = PTR_ERR(msm_host->ctrl_base);
@@ -1884,14 +1883,13 @@ int msm_dsi_host_init(struct msm_dsi *msm_dsi) · 38 unmodified lines
18841883 goto fail;
18851884 }
18861885
1887− msm_host->opp_table = dev_pm_opp_set_clkname(&pdev->dev, "byte");
1888− if (IS_ERR(msm_host->opp_table))
1889− return PTR_ERR(msm_host->opp_table);
1886+ ret = devm_pm_opp_set_clkname(&pdev->dev, "byte");
1887+ if (ret)
1888+ return ret;
18901889 /* OPP table is optional */
1891− ret = dev_pm_opp_of_add_table(&pdev->dev);
1890+ ret = devm_pm_opp_of_add_table(&pdev->dev);
18921891 if (ret && ret != -ENODEV) {
18931892 dev_err(&pdev->dev, "invalid OPP table in device tree\n");
1894− dev_pm_opp_put_clkname(msm_host->opp_table);
18951893 return ret;
18961894 }
18971895
@@ -1930,8 +1928,6 @@ void msm_dsi_host_destroy(struct mipi_dsi_host *host) · 32 unmodified lines
19301928 mutex_destroy(&msm_host->cmd_mutex);
19311929 mutex_destroy(&msm_host->dev_mutex);
19321930
1933− dev_pm_opp_of_remove_table(&msm_host->pdev->dev);
1934− dev_pm_opp_put_clkname(msm_host->opp_table);
19351931 pm_runtime_disable(&msm_host->pdev->dev);
19361932 }
19371933
@@ -2487,3 +2483,15 @@ struct drm_bridge *msm_dsi_host_get_bridge(struct mipi_dsi_host *host) · 549 unmodified lines
24872483
24882484 return of_drm_find_bridge(msm_host->device_node);
24892485 }
2486+
2487+void msm_dsi_host_snapshot(struct msm_disp_state *disp_state, struct mipi_dsi_host *host)
2488+{
2489+ struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
2490+
2491+ pm_runtime_get_sync(&msm_host->pdev->dev);
2492+
2493+ msm_disp_snapshot_add_block(disp_state, msm_host->ctrl_size,
2494+ msm_host->ctrl_base, "dsi%d_ctrl", msm_host->id);
2495+
2496+ pm_runtime_put_sync(&msm_host->pdev->dev);
2497+}
drivers/gpu/drm/msm/dsi/dsi_manager.c+6−6
@@ -373,14 +373,14 @@ static void dsi_mgr_bridge_pre_enable(struct drm_bridge *bridge) · 372 unmodified lines
373373 if (!msm_dsi_device_connected(msm_dsi))
374374 return;
375375
376− ret = dsi_mgr_phy_enable(id, phy_shared_timings);
377− if (ret)
378− goto phy_en_fail;
379−
380376 /* Do nothing with the host if it is slave-DSI in case of dual DSI */
381377 if (is_dual_dsi && !IS_MASTER_DSI_LINK(id))
382378 return;
383379
380+ ret = dsi_mgr_phy_enable(id, phy_shared_timings);
381+ if (ret)
382+ goto phy_en_fail;
383+
384384 ret = msm_dsi_host_power_on(host, &phy_shared_timings[id], is_dual_dsi);
385385 if (ret) {
386386 pr_err("%s: power on host %d failed, %d\n", __func__, id, ret);
@@ -817,8 +817,8 @@ int msm_dsi_manager_register(struct msm_dsi *msm_dsi) · 430 unmodified lines
817817
818818 ret = dsi_mgr_setup_components(id);
819819 if (ret) {
820− pr_err("%s: failed to register mipi dsi host for DSI %d\n",
821− __func__, id);
820+ pr_err("%s: failed to register mipi dsi host for DSI %d: %d\n",
821+ __func__, id, ret);
822822 goto fail;
823823 }
824824
drivers/gpu/drm/msm/dsi/dsi_phy_10nm.xml.h+228−0
@@ -0,0 +1,228 @@
1+#ifndef DSI_PHY_10NM_XML
2+#define DSI_PHY_10NM_XML
3+
4+/* Autogenerated file, DO NOT EDIT manually!
5+
6+This file was generated by the rules-ng-ng headergen tool in this git repository:
7+http://github.com/freedreno/envytools/
8+git clone https://github.com/freedreno/envytools.git
9+
10+The rules-ng-ng source files this header was generated from are:
11+- /home/robclark/src/mesa/mesa/src/freedreno/registers/msm.xml ( 981 bytes, from 2021-06-05 21:37:42)
12+- /home/robclark/src/mesa/mesa/src/freedreno/registers/freedreno_copyright.xml ( 1572 bytes, from 2021-02-18 16:45:44)
13+- /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp4.xml ( 20912 bytes, from 2021-02-18 16:45:44)
14+- /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp_common.xml ( 2849 bytes, from 2021-02-18 16:45:44)
15+- /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp5.xml ( 37461 bytes, from 2021-02-18 16:45:44)
16+- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi.xml ( 15291 bytes, from 2021-06-15 22:36:13)
17+- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_v2.xml ( 3236 bytes, from 2021-06-05 21:37:42)
18+- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_28nm_8960.xml ( 4935 bytes, from 2021-05-21 19:18:08)
19+- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_28nm.xml ( 7004 bytes, from 2021-05-21 19:18:08)
20+- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_20nm.xml ( 3712 bytes, from 2021-05-21 19:18:08)
21+- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_14nm.xml ( 5381 bytes, from 2021-05-21 19:18:08)
22+- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_10nm.xml ( 4499 bytes, from 2021-05-21 19:18:08)
23+- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_7nm.xml ( 10953 bytes, from 2021-05-21 19:18:08)
24+- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_5nm.xml ( 10900 bytes, from 2021-05-21 19:18:08)
25+- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/sfpb.xml ( 602 bytes, from 2021-02-18 16:45:44)
26+- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/mmss_cc.xml ( 1686 bytes, from 2021-02-18 16:45:44)
27+- /home/robclark/src/mesa/mesa/src/freedreno/registers/hdmi/qfprom.xml ( 600 bytes, from 2021-02-18 16:45:44)
28+- /home/robclark/src/mesa/mesa/src/freedreno/registers/hdmi/hdmi.xml ( 41874 bytes, from 2021-02-18 16:45:44)
29+- /home/robclark/src/mesa/mesa/src/freedreno/registers/edp/edp.xml ( 10416 bytes, from 2021-02-18 16:45:44)
30+
31+Copyright (C) 2013-2021 by the following authors:
32+- Rob Clark <robdclark@gmail.com> (robclark)
33+- Ilia Mirkin <imirkin@alum.mit.edu> (imirkin)
34+
35+Permission is hereby granted, free of charge, to any person obtaining
36+a copy of this software and associated documentation files (the
37+"Software"), to deal in the Software without restriction, including
38+without limitation the rights to use, copy, modify, merge, publish,
39+distribute, sublicense, and/or sell copies of the Software, and to
40+permit persons to whom the Software is furnished to do so, subject to
41+the following conditions:
42+
43+The above copyright notice and this permission notice (including the
44+next paragraph) shall be included in all copies or substantial
45+portions of the Software.
46+
47+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
48+EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
49+MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
50+IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
51+LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
52+OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
53+WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
54+*/
55+
56+
57+#define REG_DSI_10nm_PHY_CMN_REVISION_ID0 0x00000000
58+
59+#define REG_DSI_10nm_PHY_CMN_REVISION_ID1 0x00000004
60+
61+#define REG_DSI_10nm_PHY_CMN_REVISION_ID2 0x00000008
62+
63+#define REG_DSI_10nm_PHY_CMN_REVISION_ID3 0x0000000c
64+
65+#define REG_DSI_10nm_PHY_CMN_CLK_CFG0 0x00000010
66+
67+#define REG_DSI_10nm_PHY_CMN_CLK_CFG1 0x00000014
68+
69+#define REG_DSI_10nm_PHY_CMN_GLBL_CTRL 0x00000018
70+
71+#define REG_DSI_10nm_PHY_CMN_RBUF_CTRL 0x0000001c
72+
73+#define REG_DSI_10nm_PHY_CMN_VREG_CTRL 0x00000020
74+
75+#define REG_DSI_10nm_PHY_CMN_CTRL_0 0x00000024
76+
77+#define REG_DSI_10nm_PHY_CMN_CTRL_1 0x00000028
78+
79+#define REG_DSI_10nm_PHY_CMN_CTRL_2 0x0000002c
80+
81+#define REG_DSI_10nm_PHY_CMN_LANE_CFG0 0x00000030
82+
83+#define REG_DSI_10nm_PHY_CMN_LANE_CFG1 0x00000034
84+
85+#define REG_DSI_10nm_PHY_CMN_PLL_CNTRL 0x00000038
86+
87+#define REG_DSI_10nm_PHY_CMN_LANE_CTRL0 0x00000098
88+
89+#define REG_DSI_10nm_PHY_CMN_LANE_CTRL1 0x0000009c
90+
91+#define REG_DSI_10nm_PHY_CMN_LANE_CTRL2 0x000000a0
92+
93+#define REG_DSI_10nm_PHY_CMN_LANE_CTRL3 0x000000a4
94+
95+#define REG_DSI_10nm_PHY_CMN_LANE_CTRL4 0x000000a8
96+
97+#define REG_DSI_10nm_PHY_CMN_TIMING_CTRL_0 0x000000ac
98+
99+#define REG_DSI_10nm_PHY_CMN_TIMING_CTRL_1 0x000000b0
100+
101+#define REG_DSI_10nm_PHY_CMN_TIMING_CTRL_2 0x000000b4
102+
103+#define REG_DSI_10nm_PHY_CMN_TIMING_CTRL_3 0x000000b8
104+
105+#define REG_DSI_10nm_PHY_CMN_TIMING_CTRL_4 0x000000bc
106+
107+#define REG_DSI_10nm_PHY_CMN_TIMING_CTRL_5 0x000000c0
108+
109+#define REG_DSI_10nm_PHY_CMN_TIMING_CTRL_6 0x000000c4
110+
111+#define REG_DSI_10nm_PHY_CMN_TIMING_CTRL_7 0x000000c8
112+
113+#define REG_DSI_10nm_PHY_CMN_TIMING_CTRL_8 0x000000cc
114+
115+#define REG_DSI_10nm_PHY_CMN_TIMING_CTRL_9 0x000000d0
116+
117+#define REG_DSI_10nm_PHY_CMN_TIMING_CTRL_10 0x000000d4
118+
119+#define REG_DSI_10nm_PHY_CMN_TIMING_CTRL_11 0x000000d8
120+
121+#define REG_DSI_10nm_PHY_CMN_PHY_STATUS 0x000000ec
122+
123+#define REG_DSI_10nm_PHY_CMN_LANE_STATUS0 0x000000f4
124+
125+#define REG_DSI_10nm_PHY_CMN_LANE_STATUS1 0x000000f8
126+
127+static inline uint32_t REG_DSI_10nm_PHY_LN(uint32_t i0) { return 0x00000000 + 0x80*i0; }
128+
129+static inline uint32_t REG_DSI_10nm_PHY_LN_CFG0(uint32_t i0) { return 0x00000000 + 0x80*i0; }
130+
131+static inline uint32_t REG_DSI_10nm_PHY_LN_CFG1(uint32_t i0) { return 0x00000004 + 0x80*i0; }
132+
133+static inline uint32_t REG_DSI_10nm_PHY_LN_CFG2(uint32_t i0) { return 0x00000008 + 0x80*i0; }
134+
135+static inline uint32_t REG_DSI_10nm_PHY_LN_CFG3(uint32_t i0) { return 0x0000000c + 0x80*i0; }
136+
137+static inline uint32_t REG_DSI_10nm_PHY_LN_TEST_DATAPATH(uint32_t i0) { return 0x00000010 + 0x80*i0; }
138+
139+static inline uint32_t REG_DSI_10nm_PHY_LN_PIN_SWAP(uint32_t i0) { return 0x00000014 + 0x80*i0; }
140+
141+static inline uint32_t REG_DSI_10nm_PHY_LN_HSTX_STR_CTRL(uint32_t i0) { return 0x00000018 + 0x80*i0; }
142+
143+static inline uint32_t REG_DSI_10nm_PHY_LN_OFFSET_TOP_CTRL(uint32_t i0) { return 0x0000001c + 0x80*i0; }
144+
145+static inline uint32_t REG_DSI_10nm_PHY_LN_OFFSET_BOT_CTRL(uint32_t i0) { return 0x00000020 + 0x80*i0; }
146+
147+static inline uint32_t REG_DSI_10nm_PHY_LN_LPTX_STR_CTRL(uint32_t i0) { return 0x00000024 + 0x80*i0; }
148+
149+static inline uint32_t REG_DSI_10nm_PHY_LN_LPRX_CTRL(uint32_t i0) { return 0x00000028 + 0x80*i0; }
150+
151+static inline uint32_t REG_DSI_10nm_PHY_LN_TX_DCTRL(uint32_t i0) { return 0x0000002c + 0x80*i0; }
152+
153+#define REG_DSI_10nm_PHY_PLL_ANALOG_CONTROLS_ONE 0x00000000
154+
155+#define REG_DSI_10nm_PHY_PLL_ANALOG_CONTROLS_TWO 0x00000004
156+
157+#define REG_DSI_10nm_PHY_PLL_ANALOG_CONTROLS_THREE 0x00000010
158+
159+#define REG_DSI_10nm_PHY_PLL_DSM_DIVIDER 0x0000001c
160+
161+#define REG_DSI_10nm_PHY_PLL_FEEDBACK_DIVIDER 0x00000020
162+
163+#define REG_DSI_10nm_PHY_PLL_SYSTEM_MUXES 0x00000024
164+
165+#define REG_DSI_10nm_PHY_PLL_CMODE 0x0000002c
166+
167+#define REG_DSI_10nm_PHY_PLL_CALIBRATION_SETTINGS 0x00000030
168+
169+#define REG_DSI_10nm_PHY_PLL_BAND_SEL_CAL_SETTINGS_THREE 0x00000054
170+
171+#define REG_DSI_10nm_PHY_PLL_FREQ_DETECT_SETTINGS_ONE 0x00000064
172+
173+#define REG_DSI_10nm_PHY_PLL_PFILT 0x0000007c
174+
175+#define REG_DSI_10nm_PHY_PLL_IFILT 0x00000080
176+
177+#define REG_DSI_10nm_PHY_PLL_OUTDIV 0x00000094
178+
179+#define REG_DSI_10nm_PHY_PLL_CORE_OVERRIDE 0x000000a4
180+
181+#define REG_DSI_10nm_PHY_PLL_CORE_INPUT_OVERRIDE 0x000000a8
182+
183+#define REG_DSI_10nm_PHY_PLL_PLL_DIGITAL_TIMERS_TWO 0x000000b4
184+
185+#define REG_DSI_10nm_PHY_PLL_DECIMAL_DIV_START_1 0x000000cc
186+
187+#define REG_DSI_10nm_PHY_PLL_FRAC_DIV_START_LOW_1 0x000000d0
188+
189+#define REG_DSI_10nm_PHY_PLL_FRAC_DIV_START_MID_1 0x000000d4
190+
191+#define REG_DSI_10nm_PHY_PLL_FRAC_DIV_START_HIGH_1 0x000000d8
192+
193+#define REG_DSI_10nm_PHY_PLL_SSC_STEPSIZE_LOW_1 0x0000010c
194+
195+#define REG_DSI_10nm_PHY_PLL_SSC_STEPSIZE_HIGH_1 0x00000110
196+
197+#define REG_DSI_10nm_PHY_PLL_SSC_DIV_PER_LOW_1 0x00000114
198+
199+#define REG_DSI_10nm_PHY_PLL_SSC_DIV_PER_HIGH_1 0x00000118
200+
201+#define REG_DSI_10nm_PHY_PLL_SSC_DIV_ADJPER_LOW_1 0x0000011c
202+
203+#define REG_DSI_10nm_PHY_PLL_SSC_DIV_ADJPER_HIGH_1 0x00000120
204+
205+#define REG_DSI_10nm_PHY_PLL_SSC_CONTROL 0x0000013c
206+
207+#define REG_DSI_10nm_PHY_PLL_PLL_OUTDIV_RATE 0x00000140
208+
209+#define REG_DSI_10nm_PHY_PLL_PLL_LOCKDET_RATE_1 0x00000144
210+
211+#define REG_DSI_10nm_PHY_PLL_PLL_PROP_GAIN_RATE_1 0x0000014c
212+
213+#define REG_DSI_10nm_PHY_PLL_PLL_BAND_SET_RATE_1 0x00000154
214+
215+#define REG_DSI_10nm_PHY_PLL_PLL_INT_GAIN_IFILT_BAND_1 0x0000015c
216+
217+#define REG_DSI_10nm_PHY_PLL_PLL_FL_INT_GAIN_PFILT_BAND_1 0x00000164
218+
219+#define REG_DSI_10nm_PHY_PLL_PLL_LOCK_OVERRIDE 0x00000180
220+
221+#define REG_DSI_10nm_PHY_PLL_PLL_LOCK_DELAY 0x00000184
222+
223+#define REG_DSI_10nm_PHY_PLL_CLOCK_INVERTERS 0x0000018c
224+
225+#define REG_DSI_10nm_PHY_PLL_COMMON_STATUS_ONE 0x000001a0
226+
227+
228+#endif /* DSI_PHY_10NM_XML */
drivers/gpu/drm/msm/dsi/dsi_phy_14nm.xml.h+310−0
@@ -0,0 +1,310 @@
1+#ifndef DSI_PHY_14NM_XML
2+#define DSI_PHY_14NM_XML
3+
4+/* Autogenerated file, DO NOT EDIT manually!
5+
6+This file was generated by the rules-ng-ng headergen tool in this git repository:
7+http://github.com/freedreno/envytools/
8+git clone https://github.com/freedreno/envytools.git
9+
10+The rules-ng-ng source files this header was generated from are:
11+- /home/robclark/src/mesa/mesa/src/freedreno/registers/msm.xml ( 981 bytes, from 2021-06-05 21:37:42)
12+- /home/robclark/src/mesa/mesa/src/freedreno/registers/freedreno_copyright.xml ( 1572 bytes, from 2021-02-18 16:45:44)
13+- /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp4.xml ( 20912 bytes, from 2021-02-18 16:45:44)
14+- /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp_common.xml ( 2849 bytes, from 2021-02-18 16:45:44)
15+- /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp5.xml ( 37461 bytes, from 2021-02-18 16:45:44)
16+- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi.xml ( 15291 bytes, from 2021-06-15 22:36:13)
17+- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_v2.xml ( 3236 bytes, from 2021-06-05 21:37:42)
18+- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_28nm_8960.xml ( 4935 bytes, from 2021-05-21 19:18:08)
19+- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_28nm.xml ( 7004 bytes, from 2021-05-21 19:18:08)
20+- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_20nm.xml ( 3712 bytes, from 2021-05-21 19:18:08)
21+- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_14nm.xml ( 5381 bytes, from 2021-05-21 19:18:08)
22+- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_10nm.xml ( 4499 bytes, from 2021-05-21 19:18:08)
23+- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_7nm.xml ( 10953 bytes, from 2021-05-21 19:18:08)
24+- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_5nm.xml ( 10900 bytes, from 2021-05-21 19:18:08)
25+- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/sfpb.xml ( 602 bytes, from 2021-02-18 16:45:44)
26+- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/mmss_cc.xml ( 1686 bytes, from 2021-02-18 16:45:44)
27+- /home/robclark/src/mesa/mesa/src/freedreno/registers/hdmi/qfprom.xml ( 600 bytes, from 2021-02-18 16:45:44)
28+- /home/robclark/src/mesa/mesa/src/freedreno/registers/hdmi/hdmi.xml ( 41874 bytes, from 2021-02-18 16:45:44)
29+- /home/robclark/src/mesa/mesa/src/freedreno/registers/edp/edp.xml ( 10416 bytes, from 2021-02-18 16:45:44)
30+
31+Copyright (C) 2013-2021 by the following authors:
32+- Rob Clark <robdclark@gmail.com> (robclark)
33+- Ilia Mirkin <imirkin@alum.mit.edu> (imirkin)
34+
35+Permission is hereby granted, free of charge, to any person obtaining
36+a copy of this software and associated documentation files (the
37+"Software"), to deal in the Software without restriction, including
38+without limitation the rights to use, copy, modify, merge, publish,
39+distribute, sublicense, and/or sell copies of the Software, and to
40+permit persons to whom the Software is furnished to do so, subject to
41+the following conditions:
42+
43+The above copyright notice and this permission notice (including the
44+next paragraph) shall be included in all copies or substantial
45+portions of the Software.
46+
47+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
48+EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
49+MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
50+IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
51+LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
52+OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
53+WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
54+*/
55+
56+
57+#define REG_DSI_14nm_PHY_CMN_REVISION_ID0 0x00000000
58+
59+#define REG_DSI_14nm_PHY_CMN_REVISION_ID1 0x00000004
60+
61+#define REG_DSI_14nm_PHY_CMN_REVISION_ID2 0x00000008
62+
63+#define REG_DSI_14nm_PHY_CMN_REVISION_ID3 0x0000000c
64+
65+#define REG_DSI_14nm_PHY_CMN_CLK_CFG0 0x00000010
66+#define DSI_14nm_PHY_CMN_CLK_CFG0_DIV_CTRL_3_0__MASK 0x000000f0
67+#define DSI_14nm_PHY_CMN_CLK_CFG0_DIV_CTRL_3_0__SHIFT 4
68+static inline uint32_t DSI_14nm_PHY_CMN_CLK_CFG0_DIV_CTRL_3_0(uint32_t val)
69+{
70+ return ((val) << DSI_14nm_PHY_CMN_CLK_CFG0_DIV_CTRL_3_0__SHIFT) & DSI_14nm_PHY_CMN_CLK_CFG0_DIV_CTRL_3_0__MASK;
71+}
72+#define DSI_14nm_PHY_CMN_CLK_CFG0_DIV_CTRL_7_4__MASK 0x000000f0
73+#define DSI_14nm_PHY_CMN_CLK_CFG0_DIV_CTRL_7_4__SHIFT 4
74+static inline uint32_t DSI_14nm_PHY_CMN_CLK_CFG0_DIV_CTRL_7_4(uint32_t val)
75+{
76+ return ((val) << DSI_14nm_PHY_CMN_CLK_CFG0_DIV_CTRL_7_4__SHIFT) & DSI_14nm_PHY_CMN_CLK_CFG0_DIV_CTRL_7_4__MASK;
77+}
78+
79+#define REG_DSI_14nm_PHY_CMN_CLK_CFG1 0x00000014
80+#define DSI_14nm_PHY_CMN_CLK_CFG1_DSICLK_SEL 0x00000001
81+
82+#define REG_DSI_14nm_PHY_CMN_GLBL_TEST_CTRL 0x00000018
83+#define DSI_14nm_PHY_CMN_GLBL_TEST_CTRL_BITCLK_HS_SEL 0x00000004
84+
85+#define REG_DSI_14nm_PHY_CMN_CTRL_0 0x0000001c
86+
87+#define REG_DSI_14nm_PHY_CMN_CTRL_1 0x00000020
88+
89+#define REG_DSI_14nm_PHY_CMN_HW_TRIGGER 0x00000024
90+
91+#define REG_DSI_14nm_PHY_CMN_SW_CFG0 0x00000028
92+
93+#define REG_DSI_14nm_PHY_CMN_SW_CFG1 0x0000002c
94+
95+#define REG_DSI_14nm_PHY_CMN_SW_CFG2 0x00000030
96+
97+#define REG_DSI_14nm_PHY_CMN_HW_CFG0 0x00000034
98+
99+#define REG_DSI_14nm_PHY_CMN_HW_CFG1 0x00000038
100+
101+#define REG_DSI_14nm_PHY_CMN_HW_CFG2 0x0000003c
102+
103+#define REG_DSI_14nm_PHY_CMN_HW_CFG3 0x00000040
104+
105+#define REG_DSI_14nm_PHY_CMN_HW_CFG4 0x00000044
106+
107+#define REG_DSI_14nm_PHY_CMN_PLL_CNTRL 0x00000048
108+#define DSI_14nm_PHY_CMN_PLL_CNTRL_PLL_START 0x00000001
109+
110+#define REG_DSI_14nm_PHY_CMN_LDO_CNTRL 0x0000004c
111+#define DSI_14nm_PHY_CMN_LDO_CNTRL_VREG_CTRL__MASK 0x0000003f
112+#define DSI_14nm_PHY_CMN_LDO_CNTRL_VREG_CTRL__SHIFT 0
113+static inline uint32_t DSI_14nm_PHY_CMN_LDO_CNTRL_VREG_CTRL(uint32_t val)
114+{
115+ return ((val) << DSI_14nm_PHY_CMN_LDO_CNTRL_VREG_CTRL__SHIFT) & DSI_14nm_PHY_CMN_LDO_CNTRL_VREG_CTRL__MASK;
116+}
117+
118+static inline uint32_t REG_DSI_14nm_PHY_LN(uint32_t i0) { return 0x00000000 + 0x80*i0; }
119+
120+static inline uint32_t REG_DSI_14nm_PHY_LN_CFG0(uint32_t i0) { return 0x00000000 + 0x80*i0; }
121+#define DSI_14nm_PHY_LN_CFG0_PREPARE_DLY__MASK 0x000000c0
122+#define DSI_14nm_PHY_LN_CFG0_PREPARE_DLY__SHIFT 6
123+static inline uint32_t DSI_14nm_PHY_LN_CFG0_PREPARE_DLY(uint32_t val)
124+{
125+ return ((val) << DSI_14nm_PHY_LN_CFG0_PREPARE_DLY__SHIFT) & DSI_14nm_PHY_LN_CFG0_PREPARE_DLY__MASK;
126+}
127+
128+static inline uint32_t REG_DSI_14nm_PHY_LN_CFG1(uint32_t i0) { return 0x00000004 + 0x80*i0; }
129+#define DSI_14nm_PHY_LN_CFG1_HALFBYTECLK_EN 0x00000001
130+
131+static inline uint32_t REG_DSI_14nm_PHY_LN_CFG2(uint32_t i0) { return 0x00000008 + 0x80*i0; }
132+
133+static inline uint32_t REG_DSI_14nm_PHY_LN_CFG3(uint32_t i0) { return 0x0000000c + 0x80*i0; }
134+
135+static inline uint32_t REG_DSI_14nm_PHY_LN_TEST_DATAPATH(uint32_t i0) { return 0x00000010 + 0x80*i0; }
136+
137+static inline uint32_t REG_DSI_14nm_PHY_LN_TEST_STR(uint32_t i0) { return 0x00000014 + 0x80*i0; }
138+
139+static inline uint32_t REG_DSI_14nm_PHY_LN_TIMING_CTRL_4(uint32_t i0) { return 0x00000018 + 0x80*i0; }
140+#define DSI_14nm_PHY_LN_TIMING_CTRL_4_HS_EXIT__MASK 0x000000ff
141+#define DSI_14nm_PHY_LN_TIMING_CTRL_4_HS_EXIT__SHIFT 0
142+static inline uint32_t DSI_14nm_PHY_LN_TIMING_CTRL_4_HS_EXIT(uint32_t val)
143+{
144+ return ((val) << DSI_14nm_PHY_LN_TIMING_CTRL_4_HS_EXIT__SHIFT) & DSI_14nm_PHY_LN_TIMING_CTRL_4_HS_EXIT__MASK;
145+}
146+
147+static inline uint32_t REG_DSI_14nm_PHY_LN_TIMING_CTRL_5(uint32_t i0) { return 0x0000001c + 0x80*i0; }
148+#define DSI_14nm_PHY_LN_TIMING_CTRL_5_HS_ZERO__MASK 0x000000ff
149+#define DSI_14nm_PHY_LN_TIMING_CTRL_5_HS_ZERO__SHIFT 0
150+static inline uint32_t DSI_14nm_PHY_LN_TIMING_CTRL_5_HS_ZERO(uint32_t val)
151+{
152+ return ((val) << DSI_14nm_PHY_LN_TIMING_CTRL_5_HS_ZERO__SHIFT) & DSI_14nm_PHY_LN_TIMING_CTRL_5_HS_ZERO__MASK;
153+}
154+
155+static inline uint32_t REG_DSI_14nm_PHY_LN_TIMING_CTRL_6(uint32_t i0) { return 0x00000020 + 0x80*i0; }
156+#define DSI_14nm_PHY_LN_TIMING_CTRL_6_HS_PREPARE__MASK 0x000000ff
157+#define DSI_14nm_PHY_LN_TIMING_CTRL_6_HS_PREPARE__SHIFT 0
158+static inline uint32_t DSI_14nm_PHY_LN_TIMING_CTRL_6_HS_PREPARE(uint32_t val)
159+{
160+ return ((val) << DSI_14nm_PHY_LN_TIMING_CTRL_6_HS_PREPARE__SHIFT) & DSI_14nm_PHY_LN_TIMING_CTRL_6_HS_PREPARE__MASK;
161+}
162+
163+static inline uint32_t REG_DSI_14nm_PHY_LN_TIMING_CTRL_7(uint32_t i0) { return 0x00000024 + 0x80*i0; }
164+#define DSI_14nm_PHY_LN_TIMING_CTRL_7_HS_TRAIL__MASK 0x000000ff
165+#define DSI_14nm_PHY_LN_TIMING_CTRL_7_HS_TRAIL__SHIFT 0
166+static inline uint32_t DSI_14nm_PHY_LN_TIMING_CTRL_7_HS_TRAIL(uint32_t val)
167+{
168+ return ((val) << DSI_14nm_PHY_LN_TIMING_CTRL_7_HS_TRAIL__SHIFT) & DSI_14nm_PHY_LN_TIMING_CTRL_7_HS_TRAIL__MASK;
169+}
170+
171+static inline uint32_t REG_DSI_14nm_PHY_LN_TIMING_CTRL_8(uint32_t i0) { return 0x00000028 + 0x80*i0; }
172+#define DSI_14nm_PHY_LN_TIMING_CTRL_8_HS_RQST__MASK 0x000000ff
173+#define DSI_14nm_PHY_LN_TIMING_CTRL_8_HS_RQST__SHIFT 0
174+static inline uint32_t DSI_14nm_PHY_LN_TIMING_CTRL_8_HS_RQST(uint32_t val)
175+{
176+ return ((val) << DSI_14nm_PHY_LN_TIMING_CTRL_8_HS_RQST__SHIFT) & DSI_14nm_PHY_LN_TIMING_CTRL_8_HS_RQST__MASK;
177+}
178+
179+static inline uint32_t REG_DSI_14nm_PHY_LN_TIMING_CTRL_9(uint32_t i0) { return 0x0000002c + 0x80*i0; }
180+#define DSI_14nm_PHY_LN_TIMING_CTRL_9_TA_GO__MASK 0x00000007
181+#define DSI_14nm_PHY_LN_TIMING_CTRL_9_TA_GO__SHIFT 0
182+static inline uint32_t DSI_14nm_PHY_LN_TIMING_CTRL_9_TA_GO(uint32_t val)
183+{
184+ return ((val) << DSI_14nm_PHY_LN_TIMING_CTRL_9_TA_GO__SHIFT) & DSI_14nm_PHY_LN_TIMING_CTRL_9_TA_GO__MASK;
185+}
186+#define DSI_14nm_PHY_LN_TIMING_CTRL_9_TA_SURE__MASK 0x00000070
187+#define DSI_14nm_PHY_LN_TIMING_CTRL_9_TA_SURE__SHIFT 4
188+static inline uint32_t DSI_14nm_PHY_LN_TIMING_CTRL_9_TA_SURE(uint32_t val)
189+{
190+ return ((val) << DSI_14nm_PHY_LN_TIMING_CTRL_9_TA_SURE__SHIFT) & DSI_14nm_PHY_LN_TIMING_CTRL_9_TA_SURE__MASK;
191+}
192+
193+static inline uint32_t REG_DSI_14nm_PHY_LN_TIMING_CTRL_10(uint32_t i0) { return 0x00000030 + 0x80*i0; }
194+#define DSI_14nm_PHY_LN_TIMING_CTRL_10_TA_GET__MASK 0x00000007
195+#define DSI_14nm_PHY_LN_TIMING_CTRL_10_TA_GET__SHIFT 0
196+static inline uint32_t DSI_14nm_PHY_LN_TIMING_CTRL_10_TA_GET(uint32_t val)
197+{
198+ return ((val) << DSI_14nm_PHY_LN_TIMING_CTRL_10_TA_GET__SHIFT) & DSI_14nm_PHY_LN_TIMING_CTRL_10_TA_GET__MASK;
199+}
200+
201+static inline uint32_t REG_DSI_14nm_PHY_LN_TIMING_CTRL_11(uint32_t i0) { return 0x00000034 + 0x80*i0; }
202+#define DSI_14nm_PHY_LN_TIMING_CTRL_11_TRIG3_CMD__MASK 0x000000ff
203+#define DSI_14nm_PHY_LN_TIMING_CTRL_11_TRIG3_CMD__SHIFT 0
204+static inline uint32_t DSI_14nm_PHY_LN_TIMING_CTRL_11_TRIG3_CMD(uint32_t val)
205+{
206+ return ((val) << DSI_14nm_PHY_LN_TIMING_CTRL_11_TRIG3_CMD__SHIFT) & DSI_14nm_PHY_LN_TIMING_CTRL_11_TRIG3_CMD__MASK;
207+}
208+
209+static inline uint32_t REG_DSI_14nm_PHY_LN_STRENGTH_CTRL_0(uint32_t i0) { return 0x00000038 + 0x80*i0; }
210+
211+static inline uint32_t REG_DSI_14nm_PHY_LN_STRENGTH_CTRL_1(uint32_t i0) { return 0x0000003c + 0x80*i0; }
212+
213+static inline uint32_t REG_DSI_14nm_PHY_LN_VREG_CNTRL(uint32_t i0) { return 0x00000064 + 0x80*i0; }
214+
215+#define REG_DSI_14nm_PHY_PLL_IE_TRIM 0x00000000
216+
217+#define REG_DSI_14nm_PHY_PLL_IP_TRIM 0x00000004
218+
219+#define REG_DSI_14nm_PHY_PLL_IPTAT_TRIM 0x00000010
220+
221+#define REG_DSI_14nm_PHY_PLL_CLKBUFLR_EN 0x0000001c
222+
223+#define REG_DSI_14nm_PHY_PLL_SYSCLK_EN_RESET 0x00000028
224+
225+#define REG_DSI_14nm_PHY_PLL_RESETSM_CNTRL 0x0000002c
226+
227+#define REG_DSI_14nm_PHY_PLL_RESETSM_CNTRL2 0x00000030
228+
229+#define REG_DSI_14nm_PHY_PLL_RESETSM_CNTRL3 0x00000034
230+
231+#define REG_DSI_14nm_PHY_PLL_RESETSM_CNTRL4 0x00000038
232+
233+#define REG_DSI_14nm_PHY_PLL_RESETSM_CNTRL5 0x0000003c
234+
235+#define REG_DSI_14nm_PHY_PLL_KVCO_DIV_REF1 0x00000040
236+
237+#define REG_DSI_14nm_PHY_PLL_KVCO_DIV_REF2 0x00000044
238+
239+#define REG_DSI_14nm_PHY_PLL_KVCO_COUNT1 0x00000048
240+
241+#define REG_DSI_14nm_PHY_PLL_KVCO_COUNT2 0x0000004c
242+
243+#define REG_DSI_14nm_PHY_PLL_VREF_CFG1 0x0000005c
244+
245+#define REG_DSI_14nm_PHY_PLL_KVCO_CODE 0x00000058
246+
247+#define REG_DSI_14nm_PHY_PLL_VCO_DIV_REF1 0x0000006c
248+
249+#define REG_DSI_14nm_PHY_PLL_VCO_DIV_REF2 0x00000070
250+
251+#define REG_DSI_14nm_PHY_PLL_VCO_COUNT1 0x00000074
252+
253+#define REG_DSI_14nm_PHY_PLL_VCO_COUNT2 0x00000078
254+
255+#define REG_DSI_14nm_PHY_PLL_PLLLOCK_CMP1 0x0000007c
256+
257+#define REG_DSI_14nm_PHY_PLL_PLLLOCK_CMP2 0x00000080
258+
259+#define REG_DSI_14nm_PHY_PLL_PLLLOCK_CMP3 0x00000084
260+
261+#define REG_DSI_14nm_PHY_PLL_PLLLOCK_CMP_EN 0x00000088
262+
263+#define REG_DSI_14nm_PHY_PLL_PLL_VCO_TUNE 0x0000008c
264+
265+#define REG_DSI_14nm_PHY_PLL_DEC_START 0x00000090
266+
267+#define REG_DSI_14nm_PHY_PLL_SSC_EN_CENTER 0x00000094
268+
269+#define REG_DSI_14nm_PHY_PLL_SSC_ADJ_PER1 0x00000098
270+
271+#define REG_DSI_14nm_PHY_PLL_SSC_ADJ_PER2 0x0000009c
272+
273+#define REG_DSI_14nm_PHY_PLL_SSC_PER1 0x000000a0
274+
275+#define REG_DSI_14nm_PHY_PLL_SSC_PER2 0x000000a4
276+
277+#define REG_DSI_14nm_PHY_PLL_SSC_STEP_SIZE1 0x000000a8
278+
279+#define REG_DSI_14nm_PHY_PLL_SSC_STEP_SIZE2 0x000000ac
280+
281+#define REG_DSI_14nm_PHY_PLL_DIV_FRAC_START1 0x000000b4
282+
283+#define REG_DSI_14nm_PHY_PLL_DIV_FRAC_START2 0x000000b8
284+
285+#define REG_DSI_14nm_PHY_PLL_DIV_FRAC_START3 0x000000bc
286+
287+#define REG_DSI_14nm_PHY_PLL_TXCLK_EN 0x000000c0
288+
289+#define REG_DSI_14nm_PHY_PLL_PLL_CRCTRL 0x000000c4
290+
291+#define REG_DSI_14nm_PHY_PLL_RESET_SM_READY_STATUS 0x000000cc
292+
293+#define REG_DSI_14nm_PHY_PLL_PLL_MISC1 0x000000e8
294+
295+#define REG_DSI_14nm_PHY_PLL_CP_SET_CUR 0x000000f0
296+
297+#define REG_DSI_14nm_PHY_PLL_PLL_ICPMSET 0x000000f4
298+
299+#define REG_DSI_14nm_PHY_PLL_PLL_ICPCSET 0x000000f8
300+
301+#define REG_DSI_14nm_PHY_PLL_PLL_ICP_SET 0x000000fc
302+
303+#define REG_DSI_14nm_PHY_PLL_PLL_LPF1 0x00000100
304+
305+#define REG_DSI_14nm_PHY_PLL_PLL_LPF2_POSTDIV 0x00000104
306+
307+#define REG_DSI_14nm_PHY_PLL_PLL_BANDGAP 0x00000108
308+
309+
310+#endif /* DSI_PHY_14NM_XML */
drivers/gpu/drm/msm/dsi/dsi_phy_20nm.xml.h+238−0
@@ -0,0 +1,238 @@
1+#ifndef DSI_PHY_20NM_XML
2+#define DSI_PHY_20NM_XML
3+
4+/* Autogenerated file, DO NOT EDIT manually!
5+
6+This file was generated by the rules-ng-ng headergen tool in this git repository:
7+http://github.com/freedreno/envytools/
8+git clone https://github.com/freedreno/envytools.git
9+
10+The rules-ng-ng source files this header was generated from are:
11+- /home/robclark/src/mesa/mesa/src/freedreno/registers/msm.xml ( 981 bytes, from 2021-06-05 21:37:42)
12+- /home/robclark/src/mesa/mesa/src/freedreno/registers/freedreno_copyright.xml ( 1572 bytes, from 2021-02-18 16:45:44)
13+- /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp4.xml ( 20912 bytes, from 2021-02-18 16:45:44)
14+- /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp_common.xml ( 2849 bytes, from 2021-02-18 16:45:44)
15+- /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp5.xml ( 37461 bytes, from 2021-02-18 16:45:44)
16+- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi.xml ( 15291 bytes, from 2021-06-15 22:36:13)
17+- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_v2.xml ( 3236 bytes, from 2021-06-05 21:37:42)
18+- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_28nm_8960.xml ( 4935 bytes, from 2021-05-21 19:18:08)
19+- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_28nm.xml ( 7004 bytes, from 2021-05-21 19:18:08)
20+- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_20nm.xml ( 3712 bytes, from 2021-05-21 19:18:08)
21+- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_14nm.xml ( 5381 bytes, from 2021-05-21 19:18:08)
22+- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_10nm.xml ( 4499 bytes, from 2021-05-21 19:18:08)
23+- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_7nm.xml ( 10953 bytes, from 2021-05-21 19:18:08)
24+- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_5nm.xml ( 10900 bytes, from 2021-05-21 19:18:08)
25+- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/sfpb.xml ( 602 bytes, from 2021-02-18 16:45:44)
26+- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/mmss_cc.xml ( 1686 bytes, from 2021-02-18 16:45:44)
27+- /home/robclark/src/mesa/mesa/src/freedreno/registers/hdmi/qfprom.xml ( 600 bytes, from 2021-02-18 16:45:44)
28+- /home/robclark/src/mesa/mesa/src/freedreno/registers/hdmi/hdmi.xml ( 41874 bytes, from 2021-02-18 16:45:44)
29+- /home/robclark/src/mesa/mesa/src/freedreno/registers/edp/edp.xml ( 10416 bytes, from 2021-02-18 16:45:44)
30+
31+Copyright (C) 2013-2021 by the following authors:
32+- Rob Clark <robdclark@gmail.com> (robclark)
33+- Ilia Mirkin <imirkin@alum.mit.edu> (imirkin)
34+
35+Permission is hereby granted, free of charge, to any person obtaining
36+a copy of this software and associated documentation files (the
37+"Software"), to deal in the Software without restriction, including
38+without limitation the rights to use, copy, modify, merge, publish,
39+distribute, sublicense, and/or sell copies of the Software, and to
40+permit persons to whom the Software is furnished to do so, subject to
41+the following conditions:
42+
43+The above copyright notice and this permission notice (including the
44+next paragraph) shall be included in all copies or substantial
45+portions of the Software.
46+
47+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
48+EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
49+MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
50+IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
51+LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
52+OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
53+WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
54+*/
55+
56+
57+static inline uint32_t REG_DSI_20nm_PHY_LN(uint32_t i0) { return 0x00000000 + 0x40*i0; }
58+
59+static inline uint32_t REG_DSI_20nm_PHY_LN_CFG_0(uint32_t i0) { return 0x00000000 + 0x40*i0; }
60+
61+static inline uint32_t REG_DSI_20nm_PHY_LN_CFG_1(uint32_t i0) { return 0x00000004 + 0x40*i0; }
62+
63+static inline uint32_t REG_DSI_20nm_PHY_LN_CFG_2(uint32_t i0) { return 0x00000008 + 0x40*i0; }
64+
65+static inline uint32_t REG_DSI_20nm_PHY_LN_CFG_3(uint32_t i0) { return 0x0000000c + 0x40*i0; }
66+
67+static inline uint32_t REG_DSI_20nm_PHY_LN_CFG_4(uint32_t i0) { return 0x00000010 + 0x40*i0; }
68+
69+static inline uint32_t REG_DSI_20nm_PHY_LN_TEST_DATAPATH(uint32_t i0) { return 0x00000014 + 0x40*i0; }
70+
71+static inline uint32_t REG_DSI_20nm_PHY_LN_DEBUG_SEL(uint32_t i0) { return 0x00000018 + 0x40*i0; }
72+
73+static inline uint32_t REG_DSI_20nm_PHY_LN_TEST_STR_0(uint32_t i0) { return 0x0000001c + 0x40*i0; }
74+
75+static inline uint32_t REG_DSI_20nm_PHY_LN_TEST_STR_1(uint32_t i0) { return 0x00000020 + 0x40*i0; }
76+
77+#define REG_DSI_20nm_PHY_LNCK_CFG_0 0x00000100
78+
79+#define REG_DSI_20nm_PHY_LNCK_CFG_1 0x00000104
80+
81+#define REG_DSI_20nm_PHY_LNCK_CFG_2 0x00000108
82+
83+#define REG_DSI_20nm_PHY_LNCK_CFG_3 0x0000010c
84+
85+#define REG_DSI_20nm_PHY_LNCK_CFG_4 0x00000110
86+
87+#define REG_DSI_20nm_PHY_LNCK_TEST_DATAPATH 0x00000114
88+
89+#define REG_DSI_20nm_PHY_LNCK_DEBUG_SEL 0x00000118
90+
91+#define REG_DSI_20nm_PHY_LNCK_TEST_STR0 0x0000011c
92+
93+#define REG_DSI_20nm_PHY_LNCK_TEST_STR1 0x00000120
94+
95+#define REG_DSI_20nm_PHY_TIMING_CTRL_0 0x00000140
96+#define DSI_20nm_PHY_TIMING_CTRL_0_CLK_ZERO__MASK 0x000000ff
97+#define DSI_20nm_PHY_TIMING_CTRL_0_CLK_ZERO__SHIFT 0
98+static inline uint32_t DSI_20nm_PHY_TIMING_CTRL_0_CLK_ZERO(uint32_t val)
99+{
100+ return ((val) << DSI_20nm_PHY_TIMING_CTRL_0_CLK_ZERO__SHIFT) & DSI_20nm_PHY_TIMING_CTRL_0_CLK_ZERO__MASK;
101+}
102+
103+#define REG_DSI_20nm_PHY_TIMING_CTRL_1 0x00000144
104+#define DSI_20nm_PHY_TIMING_CTRL_1_CLK_TRAIL__MASK 0x000000ff
105+#define DSI_20nm_PHY_TIMING_CTRL_1_CLK_TRAIL__SHIFT 0
106+static inline uint32_t DSI_20nm_PHY_TIMING_CTRL_1_CLK_TRAIL(uint32_t val)
107+{
108+ return ((val) << DSI_20nm_PHY_TIMING_CTRL_1_CLK_TRAIL__SHIFT) & DSI_20nm_PHY_TIMING_CTRL_1_CLK_TRAIL__MASK;
109+}
110+
111+#define REG_DSI_20nm_PHY_TIMING_CTRL_2 0x00000148
112+#define DSI_20nm_PHY_TIMING_CTRL_2_CLK_PREPARE__MASK 0x000000ff
113+#define DSI_20nm_PHY_TIMING_CTRL_2_CLK_PREPARE__SHIFT 0
114+static inline uint32_t DSI_20nm_PHY_TIMING_CTRL_2_CLK_PREPARE(uint32_t val)
115+{
116+ return ((val) << DSI_20nm_PHY_TIMING_CTRL_2_CLK_PREPARE__SHIFT) & DSI_20nm_PHY_TIMING_CTRL_2_CLK_PREPARE__MASK;
117+}
118+
119+#define REG_DSI_20nm_PHY_TIMING_CTRL_3 0x0000014c
120+#define DSI_20nm_PHY_TIMING_CTRL_3_CLK_ZERO_8 0x00000001
121+
122+#define REG_DSI_20nm_PHY_TIMING_CTRL_4 0x00000150
123+#define DSI_20nm_PHY_TIMING_CTRL_4_HS_EXIT__MASK 0x000000ff
124+#define DSI_20nm_PHY_TIMING_CTRL_4_HS_EXIT__SHIFT 0
125+static inline uint32_t DSI_20nm_PHY_TIMING_CTRL_4_HS_EXIT(uint32_t val)
126+{
127+ return ((val) << DSI_20nm_PHY_TIMING_CTRL_4_HS_EXIT__SHIFT) & DSI_20nm_PHY_TIMING_CTRL_4_HS_EXIT__MASK;
128+}
129+
130+#define REG_DSI_20nm_PHY_TIMING_CTRL_5 0x00000154
131+#define DSI_20nm_PHY_TIMING_CTRL_5_HS_ZERO__MASK 0x000000ff
132+#define DSI_20nm_PHY_TIMING_CTRL_5_HS_ZERO__SHIFT 0
133+static inline uint32_t DSI_20nm_PHY_TIMING_CTRL_5_HS_ZERO(uint32_t val)
134+{
135+ return ((val) << DSI_20nm_PHY_TIMING_CTRL_5_HS_ZERO__SHIFT) & DSI_20nm_PHY_TIMING_CTRL_5_HS_ZERO__MASK;
136+}
137+
138+#define REG_DSI_20nm_PHY_TIMING_CTRL_6 0x00000158
139+#define DSI_20nm_PHY_TIMING_CTRL_6_HS_PREPARE__MASK 0x000000ff
140+#define DSI_20nm_PHY_TIMING_CTRL_6_HS_PREPARE__SHIFT 0
141+static inline uint32_t DSI_20nm_PHY_TIMING_CTRL_6_HS_PREPARE(uint32_t val)
142+{
143+ return ((val) << DSI_20nm_PHY_TIMING_CTRL_6_HS_PREPARE__SHIFT) & DSI_20nm_PHY_TIMING_CTRL_6_HS_PREPARE__MASK;
144+}
145+
146+#define REG_DSI_20nm_PHY_TIMING_CTRL_7 0x0000015c
147+#define DSI_20nm_PHY_TIMING_CTRL_7_HS_TRAIL__MASK 0x000000ff
148+#define DSI_20nm_PHY_TIMING_CTRL_7_HS_TRAIL__SHIFT 0
149+static inline uint32_t DSI_20nm_PHY_TIMING_CTRL_7_HS_TRAIL(uint32_t val)
150+{
151+ return ((val) << DSI_20nm_PHY_TIMING_CTRL_7_HS_TRAIL__SHIFT) & DSI_20nm_PHY_TIMING_CTRL_7_HS_TRAIL__MASK;
152+}
153+
154+#define REG_DSI_20nm_PHY_TIMING_CTRL_8 0x00000160
155+#define DSI_20nm_PHY_TIMING_CTRL_8_HS_RQST__MASK 0x000000ff
156+#define DSI_20nm_PHY_TIMING_CTRL_8_HS_RQST__SHIFT 0
157+static inline uint32_t DSI_20nm_PHY_TIMING_CTRL_8_HS_RQST(uint32_t val)
158+{
159+ return ((val) << DSI_20nm_PHY_TIMING_CTRL_8_HS_RQST__SHIFT) & DSI_20nm_PHY_TIMING_CTRL_8_HS_RQST__MASK;
160+}
161+
162+#define REG_DSI_20nm_PHY_TIMING_CTRL_9 0x00000164
163+#define DSI_20nm_PHY_TIMING_CTRL_9_TA_GO__MASK 0x00000007
164+#define DSI_20nm_PHY_TIMING_CTRL_9_TA_GO__SHIFT 0
165+static inline uint32_t DSI_20nm_PHY_TIMING_CTRL_9_TA_GO(uint32_t val)
166+{
167+ return ((val) << DSI_20nm_PHY_TIMING_CTRL_9_TA_GO__SHIFT) & DSI_20nm_PHY_TIMING_CTRL_9_TA_GO__MASK;
168+}
169+#define DSI_20nm_PHY_TIMING_CTRL_9_TA_SURE__MASK 0x00000070
170+#define DSI_20nm_PHY_TIMING_CTRL_9_TA_SURE__SHIFT 4
171+static inline uint32_t DSI_20nm_PHY_TIMING_CTRL_9_TA_SURE(uint32_t val)
172+{
173+ return ((val) << DSI_20nm_PHY_TIMING_CTRL_9_TA_SURE__SHIFT) & DSI_20nm_PHY_TIMING_CTRL_9_TA_SURE__MASK;
174+}
175+
176+#define REG_DSI_20nm_PHY_TIMING_CTRL_10 0x00000168
177+#define DSI_20nm_PHY_TIMING_CTRL_10_TA_GET__MASK 0x00000007
178+#define DSI_20nm_PHY_TIMING_CTRL_10_TA_GET__SHIFT 0
179+static inline uint32_t DSI_20nm_PHY_TIMING_CTRL_10_TA_GET(uint32_t val)
180+{
181+ return ((val) << DSI_20nm_PHY_TIMING_CTRL_10_TA_GET__SHIFT) & DSI_20nm_PHY_TIMING_CTRL_10_TA_GET__MASK;
182+}
183+
184+#define REG_DSI_20nm_PHY_TIMING_CTRL_11 0x0000016c
185+#define DSI_20nm_PHY_TIMING_CTRL_11_TRIG3_CMD__MASK 0x000000ff
186+#define DSI_20nm_PHY_TIMING_CTRL_11_TRIG3_CMD__SHIFT 0
187+static inline uint32_t DSI_20nm_PHY_TIMING_CTRL_11_TRIG3_CMD(uint32_t val)
188+{
189+ return ((val) << DSI_20nm_PHY_TIMING_CTRL_11_TRIG3_CMD__SHIFT) & DSI_20nm_PHY_TIMING_CTRL_11_TRIG3_CMD__MASK;
190+}
191+
192+#define REG_DSI_20nm_PHY_CTRL_0 0x00000170
193+
194+#define REG_DSI_20nm_PHY_CTRL_1 0x00000174
195+
196+#define REG_DSI_20nm_PHY_CTRL_2 0x00000178
197+
198+#define REG_DSI_20nm_PHY_CTRL_3 0x0000017c
199+
200+#define REG_DSI_20nm_PHY_CTRL_4 0x00000180
201+
202+#define REG_DSI_20nm_PHY_STRENGTH_0 0x00000184
203+
204+#define REG_DSI_20nm_PHY_STRENGTH_1 0x00000188
205+
206+#define REG_DSI_20nm_PHY_BIST_CTRL_0 0x000001b4
207+
208+#define REG_DSI_20nm_PHY_BIST_CTRL_1 0x000001b8
209+
210+#define REG_DSI_20nm_PHY_BIST_CTRL_2 0x000001bc
211+
212+#define REG_DSI_20nm_PHY_BIST_CTRL_3 0x000001c0
213+
214+#define REG_DSI_20nm_PHY_BIST_CTRL_4 0x000001c4
215+
216+#define REG_DSI_20nm_PHY_BIST_CTRL_5 0x000001c8
217+
218+#define REG_DSI_20nm_PHY_GLBL_TEST_CTRL 0x000001d4
219+#define DSI_20nm_PHY_GLBL_TEST_CTRL_BITCLK_HS_SEL 0x00000001
220+
221+#define REG_DSI_20nm_PHY_LDO_CNTRL 0x000001dc
222+
223+#define REG_DSI_20nm_PHY_REGULATOR_CTRL_0 0x00000000
224+
225+#define REG_DSI_20nm_PHY_REGULATOR_CTRL_1 0x00000004
226+
227+#define REG_DSI_20nm_PHY_REGULATOR_CTRL_2 0x00000008
228+
229+#define REG_DSI_20nm_PHY_REGULATOR_CTRL_3 0x0000000c
230+
231+#define REG_DSI_20nm_PHY_REGULATOR_CTRL_4 0x00000010
232+
233+#define REG_DSI_20nm_PHY_REGULATOR_CTRL_5 0x00000014
234+
235+#define REG_DSI_20nm_PHY_REGULATOR_CAL_PWR_CFG 0x00000018
236+
237+
238+#endif /* DSI_PHY_20NM_XML */
drivers/gpu/drm/msm/dsi/dsi_phy_28nm.xml.h+385−0
@@ -0,0 +1,385 @@
1+#ifndef DSI_PHY_28NM_XML
2+#define DSI_PHY_28NM_XML
3+
4+/* Autogenerated file, DO NOT EDIT manually!
5+
6+This file was generated by the rules-ng-ng headergen tool in this git repository:
7+http://github.com/freedreno/envytools/
8+git clone https://github.com/freedreno/envytools.git
9+
10+The rules-ng-ng source files this header was generated from are:
11+- /home/robclark/src/mesa/mesa/src/freedreno/registers/msm.xml ( 981 bytes, from 2021-06-05 21:37:42)
12+- /home/robclark/src/mesa/mesa/src/freedreno/registers/freedreno_copyright.xml ( 1572 bytes, from 2021-02-18 16:45:44)
13+- /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp4.xml ( 20912 bytes, from 2021-02-18 16:45:44)
14+- /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp_common.xml ( 2849 bytes, from 2021-02-18 16:45:44)
15+- /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp5.xml ( 37461 bytes, from 2021-02-18 16:45:44)
16+- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi.xml ( 15291 bytes, from 2021-06-15 22:36:13)
17+- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_v2.xml ( 3236 bytes, from 2021-06-05 21:37:42)
18+- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_28nm_8960.xml ( 4935 bytes, from 2021-05-21 19:18:08)
19+- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_28nm.xml ( 7004 bytes, from 2021-05-21 19:18:08)
20+- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_20nm.xml ( 3712 bytes, from 2021-05-21 19:18:08)
21+- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_14nm.xml ( 5381 bytes, from 2021-05-21 19:18:08)
22+- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_10nm.xml ( 4499 bytes, from 2021-05-21 19:18:08)
23+- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_7nm.xml ( 10953 bytes, from 2021-05-21 19:18:08)
24+- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_5nm.xml ( 10900 bytes, from 2021-05-21 19:18:08)
25+- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/sfpb.xml ( 602 bytes, from 2021-02-18 16:45:44)
26+- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/mmss_cc.xml ( 1686 bytes, from 2021-02-18 16:45:44)
27+- /home/robclark/src/mesa/mesa/src/freedreno/registers/hdmi/qfprom.xml ( 600 bytes, from 2021-02-18 16:45:44)
28+- /home/robclark/src/mesa/mesa/src/freedreno/registers/hdmi/hdmi.xml ( 41874 bytes, from 2021-02-18 16:45:44)
29+- /home/robclark/src/mesa/mesa/src/freedreno/registers/edp/edp.xml ( 10416 bytes, from 2021-02-18 16:45:44)
30+
31+Copyright (C) 2013-2021 by the following authors:
32+- Rob Clark <robdclark@gmail.com> (robclark)
33+- Ilia Mirkin <imirkin@alum.mit.edu> (imirkin)
34+
35+Permission is hereby granted, free of charge, to any person obtaining
36+a copy of this software and associated documentation files (the
37+"Software"), to deal in the Software without restriction, including
38+without limitation the rights to use, copy, modify, merge, publish,
39+distribute, sublicense, and/or sell copies of the Software, and to
40+permit persons to whom the Software is furnished to do so, subject to
41+the following conditions:
42+
43+The above copyright notice and this permission notice (including the
44+next paragraph) shall be included in all copies or substantial
45+portions of the Software.
46+
47+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
48+EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
49+MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
50+IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
51+LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
52+OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
53+WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
54+*/
55+
56+
57+static inline uint32_t REG_DSI_28nm_PHY_LN(uint32_t i0) { return 0x00000000 + 0x40*i0; }
58+
59+static inline uint32_t REG_DSI_28nm_PHY_LN_CFG_0(uint32_t i0) { return 0x00000000 + 0x40*i0; }
60+
61+static inline uint32_t REG_DSI_28nm_PHY_LN_CFG_1(uint32_t i0) { return 0x00000004 + 0x40*i0; }
62+
63+static inline uint32_t REG_DSI_28nm_PHY_LN_CFG_2(uint32_t i0) { return 0x00000008 + 0x40*i0; }
64+
65+static inline uint32_t REG_DSI_28nm_PHY_LN_CFG_3(uint32_t i0) { return 0x0000000c + 0x40*i0; }
66+
67+static inline uint32_t REG_DSI_28nm_PHY_LN_CFG_4(uint32_t i0) { return 0x00000010 + 0x40*i0; }
68+
69+static inline uint32_t REG_DSI_28nm_PHY_LN_TEST_DATAPATH(uint32_t i0) { return 0x00000014 + 0x40*i0; }
70+
71+static inline uint32_t REG_DSI_28nm_PHY_LN_DEBUG_SEL(uint32_t i0) { return 0x00000018 + 0x40*i0; }
72+
73+static inline uint32_t REG_DSI_28nm_PHY_LN_TEST_STR_0(uint32_t i0) { return 0x0000001c + 0x40*i0; }
74+
75+static inline uint32_t REG_DSI_28nm_PHY_LN_TEST_STR_1(uint32_t i0) { return 0x00000020 + 0x40*i0; }
76+
77+#define REG_DSI_28nm_PHY_LNCK_CFG_0 0x00000100
78+
79+#define REG_DSI_28nm_PHY_LNCK_CFG_1 0x00000104
80+
81+#define REG_DSI_28nm_PHY_LNCK_CFG_2 0x00000108
82+
83+#define REG_DSI_28nm_PHY_LNCK_CFG_3 0x0000010c
84+
85+#define REG_DSI_28nm_PHY_LNCK_CFG_4 0x00000110
86+
87+#define REG_DSI_28nm_PHY_LNCK_TEST_DATAPATH 0x00000114
88+
89+#define REG_DSI_28nm_PHY_LNCK_DEBUG_SEL 0x00000118
90+
91+#define REG_DSI_28nm_PHY_LNCK_TEST_STR0 0x0000011c
92+
93+#define REG_DSI_28nm_PHY_LNCK_TEST_STR1 0x00000120
94+
95+#define REG_DSI_28nm_PHY_TIMING_CTRL_0 0x00000140
96+#define DSI_28nm_PHY_TIMING_CTRL_0_CLK_ZERO__MASK 0x000000ff
97+#define DSI_28nm_PHY_TIMING_CTRL_0_CLK_ZERO__SHIFT 0
98+static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_0_CLK_ZERO(uint32_t val)
99+{
100+ return ((val) << DSI_28nm_PHY_TIMING_CTRL_0_CLK_ZERO__SHIFT) & DSI_28nm_PHY_TIMING_CTRL_0_CLK_ZERO__MASK;
101+}
102+
103+#define REG_DSI_28nm_PHY_TIMING_CTRL_1 0x00000144
104+#define DSI_28nm_PHY_TIMING_CTRL_1_CLK_TRAIL__MASK 0x000000ff
105+#define DSI_28nm_PHY_TIMING_CTRL_1_CLK_TRAIL__SHIFT 0
106+static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_1_CLK_TRAIL(uint32_t val)
107+{
108+ return ((val) << DSI_28nm_PHY_TIMING_CTRL_1_CLK_TRAIL__SHIFT) & DSI_28nm_PHY_TIMING_CTRL_1_CLK_TRAIL__MASK;
109+}
110+
111+#define REG_DSI_28nm_PHY_TIMING_CTRL_2 0x00000148
112+#define DSI_28nm_PHY_TIMING_CTRL_2_CLK_PREPARE__MASK 0x000000ff
113+#define DSI_28nm_PHY_TIMING_CTRL_2_CLK_PREPARE__SHIFT 0
114+static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_2_CLK_PREPARE(uint32_t val)
115+{
116+ return ((val) << DSI_28nm_PHY_TIMING_CTRL_2_CLK_PREPARE__SHIFT) & DSI_28nm_PHY_TIMING_CTRL_2_CLK_PREPARE__MASK;
117+}
118+
119+#define REG_DSI_28nm_PHY_TIMING_CTRL_3 0x0000014c
120+#define DSI_28nm_PHY_TIMING_CTRL_3_CLK_ZERO_8 0x00000001
121+
122+#define REG_DSI_28nm_PHY_TIMING_CTRL_4 0x00000150
123+#define DSI_28nm_PHY_TIMING_CTRL_4_HS_EXIT__MASK 0x000000ff
124+#define DSI_28nm_PHY_TIMING_CTRL_4_HS_EXIT__SHIFT 0
125+static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_4_HS_EXIT(uint32_t val)
126+{
127+ return ((val) << DSI_28nm_PHY_TIMING_CTRL_4_HS_EXIT__SHIFT) & DSI_28nm_PHY_TIMING_CTRL_4_HS_EXIT__MASK;
128+}
129+
130+#define REG_DSI_28nm_PHY_TIMING_CTRL_5 0x00000154
131+#define DSI_28nm_PHY_TIMING_CTRL_5_HS_ZERO__MASK 0x000000ff
132+#define DSI_28nm_PHY_TIMING_CTRL_5_HS_ZERO__SHIFT 0
133+static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_5_HS_ZERO(uint32_t val)
134+{
135+ return ((val) << DSI_28nm_PHY_TIMING_CTRL_5_HS_ZERO__SHIFT) & DSI_28nm_PHY_TIMING_CTRL_5_HS_ZERO__MASK;
136+}
137+
138+#define REG_DSI_28nm_PHY_TIMING_CTRL_6 0x00000158
139+#define DSI_28nm_PHY_TIMING_CTRL_6_HS_PREPARE__MASK 0x000000ff
140+#define DSI_28nm_PHY_TIMING_CTRL_6_HS_PREPARE__SHIFT 0
141+static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_6_HS_PREPARE(uint32_t val)
142+{
143+ return ((val) << DSI_28nm_PHY_TIMING_CTRL_6_HS_PREPARE__SHIFT) & DSI_28nm_PHY_TIMING_CTRL_6_HS_PREPARE__MASK;
144+}
145+
146+#define REG_DSI_28nm_PHY_TIMING_CTRL_7 0x0000015c
147+#define DSI_28nm_PHY_TIMING_CTRL_7_HS_TRAIL__MASK 0x000000ff
148+#define DSI_28nm_PHY_TIMING_CTRL_7_HS_TRAIL__SHIFT 0
149+static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_7_HS_TRAIL(uint32_t val)
150+{
151+ return ((val) << DSI_28nm_PHY_TIMING_CTRL_7_HS_TRAIL__SHIFT) & DSI_28nm_PHY_TIMING_CTRL_7_HS_TRAIL__MASK;
152+}
153+
154+#define REG_DSI_28nm_PHY_TIMING_CTRL_8 0x00000160
155+#define DSI_28nm_PHY_TIMING_CTRL_8_HS_RQST__MASK 0x000000ff
156+#define DSI_28nm_PHY_TIMING_CTRL_8_HS_RQST__SHIFT 0
157+static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_8_HS_RQST(uint32_t val)
158+{
159+ return ((val) << DSI_28nm_PHY_TIMING_CTRL_8_HS_RQST__SHIFT) & DSI_28nm_PHY_TIMING_CTRL_8_HS_RQST__MASK;
160+}
161+
162+#define REG_DSI_28nm_PHY_TIMING_CTRL_9 0x00000164
163+#define DSI_28nm_PHY_TIMING_CTRL_9_TA_GO__MASK 0x00000007
164+#define DSI_28nm_PHY_TIMING_CTRL_9_TA_GO__SHIFT 0
165+static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_9_TA_GO(uint32_t val)
166+{
167+ return ((val) << DSI_28nm_PHY_TIMING_CTRL_9_TA_GO__SHIFT) & DSI_28nm_PHY_TIMING_CTRL_9_TA_GO__MASK;
168+}
169+#define DSI_28nm_PHY_TIMING_CTRL_9_TA_SURE__MASK 0x00000070
170+#define DSI_28nm_PHY_TIMING_CTRL_9_TA_SURE__SHIFT 4
171+static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_9_TA_SURE(uint32_t val)
172+{
173+ return ((val) << DSI_28nm_PHY_TIMING_CTRL_9_TA_SURE__SHIFT) & DSI_28nm_PHY_TIMING_CTRL_9_TA_SURE__MASK;
174+}
175+
176+#define REG_DSI_28nm_PHY_TIMING_CTRL_10 0x00000168
177+#define DSI_28nm_PHY_TIMING_CTRL_10_TA_GET__MASK 0x00000007
178+#define DSI_28nm_PHY_TIMING_CTRL_10_TA_GET__SHIFT 0
179+static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_10_TA_GET(uint32_t val)
180+{
181+ return ((val) << DSI_28nm_PHY_TIMING_CTRL_10_TA_GET__SHIFT) & DSI_28nm_PHY_TIMING_CTRL_10_TA_GET__MASK;
182+}
183+
184+#define REG_DSI_28nm_PHY_TIMING_CTRL_11 0x0000016c
185+#define DSI_28nm_PHY_TIMING_CTRL_11_TRIG3_CMD__MASK 0x000000ff
186+#define DSI_28nm_PHY_TIMING_CTRL_11_TRIG3_CMD__SHIFT 0
187+static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_11_TRIG3_CMD(uint32_t val)
188+{
189+ return ((val) << DSI_28nm_PHY_TIMING_CTRL_11_TRIG3_CMD__SHIFT) & DSI_28nm_PHY_TIMING_CTRL_11_TRIG3_CMD__MASK;
190+}
191+
192+#define REG_DSI_28nm_PHY_CTRL_0 0x00000170
193+
194+#define REG_DSI_28nm_PHY_CTRL_1 0x00000174
195+
196+#define REG_DSI_28nm_PHY_CTRL_2 0x00000178
197+
198+#define REG_DSI_28nm_PHY_CTRL_3 0x0000017c
199+
200+#define REG_DSI_28nm_PHY_CTRL_4 0x00000180
201+
202+#define REG_DSI_28nm_PHY_STRENGTH_0 0x00000184
203+
204+#define REG_DSI_28nm_PHY_STRENGTH_1 0x00000188
205+
206+#define REG_DSI_28nm_PHY_BIST_CTRL_0 0x000001b4
207+
208+#define REG_DSI_28nm_PHY_BIST_CTRL_1 0x000001b8
209+
210+#define REG_DSI_28nm_PHY_BIST_CTRL_2 0x000001bc
211+
212+#define REG_DSI_28nm_PHY_BIST_CTRL_3 0x000001c0
213+
214+#define REG_DSI_28nm_PHY_BIST_CTRL_4 0x000001c4
215+
216+#define REG_DSI_28nm_PHY_BIST_CTRL_5 0x000001c8
217+
218+#define REG_DSI_28nm_PHY_GLBL_TEST_CTRL 0x000001d4
219+#define DSI_28nm_PHY_GLBL_TEST_CTRL_BITCLK_HS_SEL 0x00000001
220+
221+#define REG_DSI_28nm_PHY_LDO_CNTRL 0x000001dc
222+
223+#define REG_DSI_28nm_PHY_REGULATOR_CTRL_0 0x00000000
224+
225+#define REG_DSI_28nm_PHY_REGULATOR_CTRL_1 0x00000004
226+
227+#define REG_DSI_28nm_PHY_REGULATOR_CTRL_2 0x00000008
228+
229+#define REG_DSI_28nm_PHY_REGULATOR_CTRL_3 0x0000000c
230+
231+#define REG_DSI_28nm_PHY_REGULATOR_CTRL_4 0x00000010
232+
233+#define REG_DSI_28nm_PHY_REGULATOR_CTRL_5 0x00000014
234+
235+#define REG_DSI_28nm_PHY_REGULATOR_CAL_PWR_CFG 0x00000018
236+
237+#define REG_DSI_28nm_PHY_PLL_REFCLK_CFG 0x00000000
238+#define DSI_28nm_PHY_PLL_REFCLK_CFG_DBLR 0x00000001
239+
240+#define REG_DSI_28nm_PHY_PLL_POSTDIV1_CFG 0x00000004
241+
242+#define REG_DSI_28nm_PHY_PLL_CHGPUMP_CFG 0x00000008
243+
244+#define REG_DSI_28nm_PHY_PLL_VCOLPF_CFG 0x0000000c
245+
246+#define REG_DSI_28nm_PHY_PLL_VREG_CFG 0x00000010
247+#define DSI_28nm_PHY_PLL_VREG_CFG_POSTDIV1_BYPASS_B 0x00000002
248+
249+#define REG_DSI_28nm_PHY_PLL_PWRGEN_CFG 0x00000014
250+
251+#define REG_DSI_28nm_PHY_PLL_DMUX_CFG 0x00000018
252+
253+#define REG_DSI_28nm_PHY_PLL_AMUX_CFG 0x0000001c
254+
255+#define REG_DSI_28nm_PHY_PLL_GLB_CFG 0x00000020
256+#define DSI_28nm_PHY_PLL_GLB_CFG_PLL_PWRDN_B 0x00000001
257+#define DSI_28nm_PHY_PLL_GLB_CFG_PLL_LDO_PWRDN_B 0x00000002
258+#define DSI_28nm_PHY_PLL_GLB_CFG_PLL_PWRGEN_PWRDN_B 0x00000004
259+#define DSI_28nm_PHY_PLL_GLB_CFG_PLL_ENABLE 0x00000008
260+
261+#define REG_DSI_28nm_PHY_PLL_POSTDIV2_CFG 0x00000024
262+
263+#define REG_DSI_28nm_PHY_PLL_POSTDIV3_CFG 0x00000028
264+
265+#define REG_DSI_28nm_PHY_PLL_LPFR_CFG 0x0000002c
266+
267+#define REG_DSI_28nm_PHY_PLL_LPFC1_CFG 0x00000030
268+
269+#define REG_DSI_28nm_PHY_PLL_LPFC2_CFG 0x00000034
270+
271+#define REG_DSI_28nm_PHY_PLL_SDM_CFG0 0x00000038
272+#define DSI_28nm_PHY_PLL_SDM_CFG0_BYP_DIV__MASK 0x0000003f
273+#define DSI_28nm_PHY_PLL_SDM_CFG0_BYP_DIV__SHIFT 0
274+static inline uint32_t DSI_28nm_PHY_PLL_SDM_CFG0_BYP_DIV(uint32_t val)
275+{
276+ return ((val) << DSI_28nm_PHY_PLL_SDM_CFG0_BYP_DIV__SHIFT) & DSI_28nm_PHY_PLL_SDM_CFG0_BYP_DIV__MASK;
277+}
278+#define DSI_28nm_PHY_PLL_SDM_CFG0_BYP 0x00000040
279+
280+#define REG_DSI_28nm_PHY_PLL_SDM_CFG1 0x0000003c
281+#define DSI_28nm_PHY_PLL_SDM_CFG1_DC_OFFSET__MASK 0x0000003f
282+#define DSI_28nm_PHY_PLL_SDM_CFG1_DC_OFFSET__SHIFT 0
283+static inline uint32_t DSI_28nm_PHY_PLL_SDM_CFG1_DC_OFFSET(uint32_t val)
284+{
285+ return ((val) << DSI_28nm_PHY_PLL_SDM_CFG1_DC_OFFSET__SHIFT) & DSI_28nm_PHY_PLL_SDM_CFG1_DC_OFFSET__MASK;
286+}
287+#define DSI_28nm_PHY_PLL_SDM_CFG1_DITHER_EN__MASK 0x00000040
288+#define DSI_28nm_PHY_PLL_SDM_CFG1_DITHER_EN__SHIFT 6
289+static inline uint32_t DSI_28nm_PHY_PLL_SDM_CFG1_DITHER_EN(uint32_t val)
290+{
291+ return ((val) << DSI_28nm_PHY_PLL_SDM_CFG1_DITHER_EN__SHIFT) & DSI_28nm_PHY_PLL_SDM_CFG1_DITHER_EN__MASK;
292+}
293+
294+#define REG_DSI_28nm_PHY_PLL_SDM_CFG2 0x00000040
295+#define DSI_28nm_PHY_PLL_SDM_CFG2_FREQ_SEED_7_0__MASK 0x000000ff
296+#define DSI_28nm_PHY_PLL_SDM_CFG2_FREQ_SEED_7_0__SHIFT 0
297+static inline uint32_t DSI_28nm_PHY_PLL_SDM_CFG2_FREQ_SEED_7_0(uint32_t val)
298+{
299+ return ((val) << DSI_28nm_PHY_PLL_SDM_CFG2_FREQ_SEED_7_0__SHIFT) & DSI_28nm_PHY_PLL_SDM_CFG2_FREQ_SEED_7_0__MASK;
300+}
301+
302+#define REG_DSI_28nm_PHY_PLL_SDM_CFG3 0x00000044
303+#define DSI_28nm_PHY_PLL_SDM_CFG3_FREQ_SEED_15_8__MASK 0x000000ff
304+#define DSI_28nm_PHY_PLL_SDM_CFG3_FREQ_SEED_15_8__SHIFT 0
305+static inline uint32_t DSI_28nm_PHY_PLL_SDM_CFG3_FREQ_SEED_15_8(uint32_t val)
306+{
307+ return ((val) << DSI_28nm_PHY_PLL_SDM_CFG3_FREQ_SEED_15_8__SHIFT) & DSI_28nm_PHY_PLL_SDM_CFG3_FREQ_SEED_15_8__MASK;
308+}
309+
310+#define REG_DSI_28nm_PHY_PLL_SDM_CFG4 0x00000048
311+
312+#define REG_DSI_28nm_PHY_PLL_SSC_CFG0 0x0000004c
313+
314+#define REG_DSI_28nm_PHY_PLL_SSC_CFG1 0x00000050
315+
316+#define REG_DSI_28nm_PHY_PLL_SSC_CFG2 0x00000054
317+
318+#define REG_DSI_28nm_PHY_PLL_SSC_CFG3 0x00000058
319+
320+#define REG_DSI_28nm_PHY_PLL_LKDET_CFG0 0x0000005c
321+
322+#define REG_DSI_28nm_PHY_PLL_LKDET_CFG1 0x00000060
323+
324+#define REG_DSI_28nm_PHY_PLL_LKDET_CFG2 0x00000064
325+
326+#define REG_DSI_28nm_PHY_PLL_TEST_CFG 0x00000068
327+#define DSI_28nm_PHY_PLL_TEST_CFG_PLL_SW_RESET 0x00000001
328+
329+#define REG_DSI_28nm_PHY_PLL_CAL_CFG0 0x0000006c
330+
331+#define REG_DSI_28nm_PHY_PLL_CAL_CFG1 0x00000070
332+
333+#define REG_DSI_28nm_PHY_PLL_CAL_CFG2 0x00000074
334+
335+#define REG_DSI_28nm_PHY_PLL_CAL_CFG3 0x00000078
336+
337+#define REG_DSI_28nm_PHY_PLL_CAL_CFG4 0x0000007c
338+
339+#define REG_DSI_28nm_PHY_PLL_CAL_CFG5 0x00000080
340+
341+#define REG_DSI_28nm_PHY_PLL_CAL_CFG6 0x00000084
342+
343+#define REG_DSI_28nm_PHY_PLL_CAL_CFG7 0x00000088
344+
345+#define REG_DSI_28nm_PHY_PLL_CAL_CFG8 0x0000008c
346+
347+#define REG_DSI_28nm_PHY_PLL_CAL_CFG9 0x00000090
348+
349+#define REG_DSI_28nm_PHY_PLL_CAL_CFG10 0x00000094
350+
351+#define REG_DSI_28nm_PHY_PLL_CAL_CFG11 0x00000098
352+
353+#define REG_DSI_28nm_PHY_PLL_EFUSE_CFG 0x0000009c
354+
355+#define REG_DSI_28nm_PHY_PLL_DEBUG_BUS_SEL 0x000000a0
356+
357+#define REG_DSI_28nm_PHY_PLL_CTRL_42 0x000000a4
358+
359+#define REG_DSI_28nm_PHY_PLL_CTRL_43 0x000000a8
360+
361+#define REG_DSI_28nm_PHY_PLL_CTRL_44 0x000000ac
362+
363+#define REG_DSI_28nm_PHY_PLL_CTRL_45 0x000000b0
364+
365+#define REG_DSI_28nm_PHY_PLL_CTRL_46 0x000000b4
366+
367+#define REG_DSI_28nm_PHY_PLL_CTRL_47 0x000000b8
368+
369+#define REG_DSI_28nm_PHY_PLL_CTRL_48 0x000000bc
370+
371+#define REG_DSI_28nm_PHY_PLL_STATUS 0x000000c0
372+#define DSI_28nm_PHY_PLL_STATUS_PLL_RDY 0x00000001
373+
374+#define REG_DSI_28nm_PHY_PLL_DEBUG_BUS0 0x000000c4
375+
376+#define REG_DSI_28nm_PHY_PLL_DEBUG_BUS1 0x000000c8
377+
378+#define REG_DSI_28nm_PHY_PLL_DEBUG_BUS2 0x000000cc
379+
380+#define REG_DSI_28nm_PHY_PLL_DEBUG_BUS3 0x000000d0
381+
382+#define REG_DSI_28nm_PHY_PLL_CTRL_54 0x000000d4
383+
384+
385+#endif /* DSI_PHY_28NM_XML */
drivers/gpu/drm/msm/dsi/dsi_phy_28nm_8960.xml.h+287−0
@@ -0,0 +1,287 @@
1+#ifndef DSI_PHY_28NM_8960_XML
2+#define DSI_PHY_28NM_8960_XML
3+
4+/* Autogenerated file, DO NOT EDIT manually!
5+
6+This file was generated by the rules-ng-ng headergen tool in this git repository:
7+http://github.com/freedreno/envytools/
8+git clone https://github.com/freedreno/envytools.git
9+
10+The rules-ng-ng source files this header was generated from are:
11+- /home/robclark/src/mesa/mesa/src/freedreno/registers/msm.xml ( 981 bytes, from 2021-06-05 21:37:42)
12+- /home/robclark/src/mesa/mesa/src/freedreno/registers/freedreno_copyright.xml ( 1572 bytes, from 2021-02-18 16:45:44)
13+- /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp4.xml ( 20912 bytes, from 2021-02-18 16:45:44)
14+- /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp_common.xml ( 2849 bytes, from 2021-02-18 16:45:44)
15+- /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp5.xml ( 37461 bytes, from 2021-02-18 16:45:44)
16+- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi.xml ( 15291 bytes, from 2021-06-15 22:36:13)
17+- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_v2.xml ( 3236 bytes, from 2021-06-05 21:37:42)
18+- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_28nm_8960.xml ( 4935 bytes, from 2021-05-21 19:18:08)
19+- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_28nm.xml ( 7004 bytes, from 2021-05-21 19:18:08)
20+- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_20nm.xml ( 3712 bytes, from 2021-05-21 19:18:08)
21+- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_14nm.xml ( 5381 bytes, from 2021-05-21 19:18:08)
22+- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_10nm.xml ( 4499 bytes, from 2021-05-21 19:18:08)
23+- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_7nm.xml ( 10953 bytes, from 2021-05-21 19:18:08)
24+- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_5nm.xml ( 10900 bytes, from 2021-05-21 19:18:08)
25+- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/sfpb.xml ( 602 bytes, from 2021-02-18 16:45:44)
26+- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/mmss_cc.xml ( 1686 bytes, from 2021-02-18 16:45:44)
27+- /home/robclark/src/mesa/mesa/src/freedreno/registers/hdmi/qfprom.xml ( 600 bytes, from 2021-02-18 16:45:44)
28+- /home/robclark/src/mesa/mesa/src/freedreno/registers/hdmi/hdmi.xml ( 41874 bytes, from 2021-02-18 16:45:44)
29+- /home/robclark/src/mesa/mesa/src/freedreno/registers/edp/edp.xml ( 10416 bytes, from 2021-02-18 16:45:44)
30+
31+Copyright (C) 2013-2021 by the following authors:
32+- Rob Clark <robdclark@gmail.com> (robclark)
33+- Ilia Mirkin <imirkin@alum.mit.edu> (imirkin)
34+
35+Permission is hereby granted, free of charge, to any person obtaining
36+a copy of this software and associated documentation files (the
37+"Software"), to deal in the Software without restriction, including
38+without limitation the rights to use, copy, modify, merge, publish,
39+distribute, sublicense, and/or sell copies of the Software, and to
40+permit persons to whom the Software is furnished to do so, subject to
41+the following conditions:
42+
43+The above copyright notice and this permission notice (including the
44+next paragraph) shall be included in all copies or substantial
45+portions of the Software.
46+
47+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
48+EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
49+MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
50+IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
51+LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
52+OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
53+WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
54+*/
55+
56+
57+static inline uint32_t REG_DSI_28nm_8960_PHY_LN(uint32_t i0) { return 0x00000000 + 0x40*i0; }
58+
59+static inline uint32_t REG_DSI_28nm_8960_PHY_LN_CFG_0(uint32_t i0) { return 0x00000000 + 0x40*i0; }
60+
61+static inline uint32_t REG_DSI_28nm_8960_PHY_LN_CFG_1(uint32_t i0) { return 0x00000004 + 0x40*i0; }
62+
63+static inline uint32_t REG_DSI_28nm_8960_PHY_LN_CFG_2(uint32_t i0) { return 0x00000008 + 0x40*i0; }
64+
65+static inline uint32_t REG_DSI_28nm_8960_PHY_LN_TEST_DATAPATH(uint32_t i0) { return 0x0000000c + 0x40*i0; }
66+
67+static inline uint32_t REG_DSI_28nm_8960_PHY_LN_TEST_STR_0(uint32_t i0) { return 0x00000014 + 0x40*i0; }
68+
69+static inline uint32_t REG_DSI_28nm_8960_PHY_LN_TEST_STR_1(uint32_t i0) { return 0x00000018 + 0x40*i0; }
70+
71+#define REG_DSI_28nm_8960_PHY_LNCK_CFG_0 0x00000100
72+
73+#define REG_DSI_28nm_8960_PHY_LNCK_CFG_1 0x00000104
74+
75+#define REG_DSI_28nm_8960_PHY_LNCK_CFG_2 0x00000108
76+
77+#define REG_DSI_28nm_8960_PHY_LNCK_TEST_DATAPATH 0x0000010c
78+
79+#define REG_DSI_28nm_8960_PHY_LNCK_TEST_STR0 0x00000114
80+
81+#define REG_DSI_28nm_8960_PHY_LNCK_TEST_STR1 0x00000118
82+
83+#define REG_DSI_28nm_8960_PHY_TIMING_CTRL_0 0x00000140
84+#define DSI_28nm_8960_PHY_TIMING_CTRL_0_CLK_ZERO__MASK 0x000000ff
85+#define DSI_28nm_8960_PHY_TIMING_CTRL_0_CLK_ZERO__SHIFT 0
86+static inline uint32_t DSI_28nm_8960_PHY_TIMING_CTRL_0_CLK_ZERO(uint32_t val)
87+{
88+ return ((val) << DSI_28nm_8960_PHY_TIMING_CTRL_0_CLK_ZERO__SHIFT) & DSI_28nm_8960_PHY_TIMING_CTRL_0_CLK_ZERO__MASK;
89+}
90+
91+#define REG_DSI_28nm_8960_PHY_TIMING_CTRL_1 0x00000144
92+#define DSI_28nm_8960_PHY_TIMING_CTRL_1_CLK_TRAIL__MASK 0x000000ff
93+#define DSI_28nm_8960_PHY_TIMING_CTRL_1_CLK_TRAIL__SHIFT 0
94+static inline uint32_t DSI_28nm_8960_PHY_TIMING_CTRL_1_CLK_TRAIL(uint32_t val)
95+{
96+ return ((val) << DSI_28nm_8960_PHY_TIMING_CTRL_1_CLK_TRAIL__SHIFT) & DSI_28nm_8960_PHY_TIMING_CTRL_1_CLK_TRAIL__MASK;
97+}
98+
99+#define REG_DSI_28nm_8960_PHY_TIMING_CTRL_2 0x00000148
100+#define DSI_28nm_8960_PHY_TIMING_CTRL_2_CLK_PREPARE__MASK 0x000000ff
101+#define DSI_28nm_8960_PHY_TIMING_CTRL_2_CLK_PREPARE__SHIFT 0
102+static inline uint32_t DSI_28nm_8960_PHY_TIMING_CTRL_2_CLK_PREPARE(uint32_t val)
103+{
104+ return ((val) << DSI_28nm_8960_PHY_TIMING_CTRL_2_CLK_PREPARE__SHIFT) & DSI_28nm_8960_PHY_TIMING_CTRL_2_CLK_PREPARE__MASK;
105+}
106+
107+#define REG_DSI_28nm_8960_PHY_TIMING_CTRL_3 0x0000014c
108+
109+#define REG_DSI_28nm_8960_PHY_TIMING_CTRL_4 0x00000150
110+#define DSI_28nm_8960_PHY_TIMING_CTRL_4_HS_EXIT__MASK 0x000000ff
111+#define DSI_28nm_8960_PHY_TIMING_CTRL_4_HS_EXIT__SHIFT 0
112+static inline uint32_t DSI_28nm_8960_PHY_TIMING_CTRL_4_HS_EXIT(uint32_t val)
113+{
114+ return ((val) << DSI_28nm_8960_PHY_TIMING_CTRL_4_HS_EXIT__SHIFT) & DSI_28nm_8960_PHY_TIMING_CTRL_4_HS_EXIT__MASK;
115+}
116+
117+#define REG_DSI_28nm_8960_PHY_TIMING_CTRL_5 0x00000154
118+#define DSI_28nm_8960_PHY_TIMING_CTRL_5_HS_ZERO__MASK 0x000000ff
119+#define DSI_28nm_8960_PHY_TIMING_CTRL_5_HS_ZERO__SHIFT 0
120+static inline uint32_t DSI_28nm_8960_PHY_TIMING_CTRL_5_HS_ZERO(uint32_t val)
121+{
122+ return ((val) << DSI_28nm_8960_PHY_TIMING_CTRL_5_HS_ZERO__SHIFT) & DSI_28nm_8960_PHY_TIMING_CTRL_5_HS_ZERO__MASK;
123+}
124+
125+#define REG_DSI_28nm_8960_PHY_TIMING_CTRL_6 0x00000158
126+#define DSI_28nm_8960_PHY_TIMING_CTRL_6_HS_PREPARE__MASK 0x000000ff
127+#define DSI_28nm_8960_PHY_TIMING_CTRL_6_HS_PREPARE__SHIFT 0
128+static inline uint32_t DSI_28nm_8960_PHY_TIMING_CTRL_6_HS_PREPARE(uint32_t val)
129+{
130+ return ((val) << DSI_28nm_8960_PHY_TIMING_CTRL_6_HS_PREPARE__SHIFT) & DSI_28nm_8960_PHY_TIMING_CTRL_6_HS_PREPARE__MASK;
131+}
132+
133+#define REG_DSI_28nm_8960_PHY_TIMING_CTRL_7 0x0000015c
134+#define DSI_28nm_8960_PHY_TIMING_CTRL_7_HS_TRAIL__MASK 0x000000ff
135+#define DSI_28nm_8960_PHY_TIMING_CTRL_7_HS_TRAIL__SHIFT 0
136+static inline uint32_t DSI_28nm_8960_PHY_TIMING_CTRL_7_HS_TRAIL(uint32_t val)
137+{
138+ return ((val) << DSI_28nm_8960_PHY_TIMING_CTRL_7_HS_TRAIL__SHIFT) & DSI_28nm_8960_PHY_TIMING_CTRL_7_HS_TRAIL__MASK;
139+}
140+
141+#define REG_DSI_28nm_8960_PHY_TIMING_CTRL_8 0x00000160
142+#define DSI_28nm_8960_PHY_TIMING_CTRL_8_HS_RQST__MASK 0x000000ff
143+#define DSI_28nm_8960_PHY_TIMING_CTRL_8_HS_RQST__SHIFT 0
144+static inline uint32_t DSI_28nm_8960_PHY_TIMING_CTRL_8_HS_RQST(uint32_t val)
145+{
146+ return ((val) << DSI_28nm_8960_PHY_TIMING_CTRL_8_HS_RQST__SHIFT) & DSI_28nm_8960_PHY_TIMING_CTRL_8_HS_RQST__MASK;
147+}
148+
149+#define REG_DSI_28nm_8960_PHY_TIMING_CTRL_9 0x00000164
150+#define DSI_28nm_8960_PHY_TIMING_CTRL_9_TA_GO__MASK 0x00000007
151+#define DSI_28nm_8960_PHY_TIMING_CTRL_9_TA_GO__SHIFT 0
152+static inline uint32_t DSI_28nm_8960_PHY_TIMING_CTRL_9_TA_GO(uint32_t val)
153+{
154+ return ((val) << DSI_28nm_8960_PHY_TIMING_CTRL_9_TA_GO__SHIFT) & DSI_28nm_8960_PHY_TIMING_CTRL_9_TA_GO__MASK;
155+}
156+#define DSI_28nm_8960_PHY_TIMING_CTRL_9_TA_SURE__MASK 0x00000070
157+#define DSI_28nm_8960_PHY_TIMING_CTRL_9_TA_SURE__SHIFT 4
158+static inline uint32_t DSI_28nm_8960_PHY_TIMING_CTRL_9_TA_SURE(uint32_t val)
159+{
160+ return ((val) << DSI_28nm_8960_PHY_TIMING_CTRL_9_TA_SURE__SHIFT) & DSI_28nm_8960_PHY_TIMING_CTRL_9_TA_SURE__MASK;
161+}
162+
163+#define REG_DSI_28nm_8960_PHY_TIMING_CTRL_10 0x00000168
164+#define DSI_28nm_8960_PHY_TIMING_CTRL_10_TA_GET__MASK 0x00000007
165+#define DSI_28nm_8960_PHY_TIMING_CTRL_10_TA_GET__SHIFT 0
166+static inline uint32_t DSI_28nm_8960_PHY_TIMING_CTRL_10_TA_GET(uint32_t val)
167+{
168+ return ((val) << DSI_28nm_8960_PHY_TIMING_CTRL_10_TA_GET__SHIFT) & DSI_28nm_8960_PHY_TIMING_CTRL_10_TA_GET__MASK;
169+}
170+
171+#define REG_DSI_28nm_8960_PHY_TIMING_CTRL_11 0x0000016c
172+#define DSI_28nm_8960_PHY_TIMING_CTRL_11_TRIG3_CMD__MASK 0x000000ff
173+#define DSI_28nm_8960_PHY_TIMING_CTRL_11_TRIG3_CMD__SHIFT 0
174+static inline uint32_t DSI_28nm_8960_PHY_TIMING_CTRL_11_TRIG3_CMD(uint32_t val)
175+{
176+ return ((val) << DSI_28nm_8960_PHY_TIMING_CTRL_11_TRIG3_CMD__SHIFT) & DSI_28nm_8960_PHY_TIMING_CTRL_11_TRIG3_CMD__MASK;
177+}
178+
179+#define REG_DSI_28nm_8960_PHY_CTRL_0 0x00000170
180+
181+#define REG_DSI_28nm_8960_PHY_CTRL_1 0x00000174
182+
183+#define REG_DSI_28nm_8960_PHY_CTRL_2 0x00000178
184+
185+#define REG_DSI_28nm_8960_PHY_CTRL_3 0x0000017c
186+
187+#define REG_DSI_28nm_8960_PHY_STRENGTH_0 0x00000180
188+
189+#define REG_DSI_28nm_8960_PHY_STRENGTH_1 0x00000184
190+
191+#define REG_DSI_28nm_8960_PHY_STRENGTH_2 0x00000188
192+
193+#define REG_DSI_28nm_8960_PHY_BIST_CTRL_0 0x0000018c
194+
195+#define REG_DSI_28nm_8960_PHY_BIST_CTRL_1 0x00000190
196+
197+#define REG_DSI_28nm_8960_PHY_BIST_CTRL_2 0x00000194
198+
199+#define REG_DSI_28nm_8960_PHY_BIST_CTRL_3 0x00000198
200+
201+#define REG_DSI_28nm_8960_PHY_BIST_CTRL_4 0x0000019c
202+
203+#define REG_DSI_28nm_8960_PHY_LDO_CTRL 0x000001b0
204+
205+#define REG_DSI_28nm_8960_PHY_MISC_REGULATOR_CTRL_0 0x00000000
206+
207+#define REG_DSI_28nm_8960_PHY_MISC_REGULATOR_CTRL_1 0x00000004
208+
209+#define REG_DSI_28nm_8960_PHY_MISC_REGULATOR_CTRL_2 0x00000008
210+
211+#define REG_DSI_28nm_8960_PHY_MISC_REGULATOR_CTRL_3 0x0000000c
212+
213+#define REG_DSI_28nm_8960_PHY_MISC_REGULATOR_CTRL_4 0x00000010
214+
215+#define REG_DSI_28nm_8960_PHY_MISC_REGULATOR_CTRL_5 0x00000014
216+
217+#define REG_DSI_28nm_8960_PHY_MISC_REGULATOR_CAL_PWR_CFG 0x00000018
218+
219+#define REG_DSI_28nm_8960_PHY_MISC_CAL_HW_TRIGGER 0x00000028
220+
221+#define REG_DSI_28nm_8960_PHY_MISC_CAL_SW_CFG_0 0x0000002c
222+
223+#define REG_DSI_28nm_8960_PHY_MISC_CAL_SW_CFG_1 0x00000030
224+
225+#define REG_DSI_28nm_8960_PHY_MISC_CAL_SW_CFG_2 0x00000034
226+
227+#define REG_DSI_28nm_8960_PHY_MISC_CAL_HW_CFG_0 0x00000038
228+
229+#define REG_DSI_28nm_8960_PHY_MISC_CAL_HW_CFG_1 0x0000003c
230+
231+#define REG_DSI_28nm_8960_PHY_MISC_CAL_HW_CFG_2 0x00000040
232+
233+#define REG_DSI_28nm_8960_PHY_MISC_CAL_HW_CFG_3 0x00000044
234+
235+#define REG_DSI_28nm_8960_PHY_MISC_CAL_HW_CFG_4 0x00000048
236+
237+#define REG_DSI_28nm_8960_PHY_MISC_CAL_STATUS 0x00000050
238+#define DSI_28nm_8960_PHY_MISC_CAL_STATUS_CAL_BUSY 0x00000010
239+
240+#define REG_DSI_28nm_8960_PHY_PLL_CTRL_0 0x00000000
241+#define DSI_28nm_8960_PHY_PLL_CTRL_0_ENABLE 0x00000001
242+
243+#define REG_DSI_28nm_8960_PHY_PLL_CTRL_1 0x00000004
244+
245+#define REG_DSI_28nm_8960_PHY_PLL_CTRL_2 0x00000008
246+
247+#define REG_DSI_28nm_8960_PHY_PLL_CTRL_3 0x0000000c
248+
249+#define REG_DSI_28nm_8960_PHY_PLL_CTRL_4 0x00000010
250+
251+#define REG_DSI_28nm_8960_PHY_PLL_CTRL_5 0x00000014
252+
253+#define REG_DSI_28nm_8960_PHY_PLL_CTRL_6 0x00000018
254+
255+#define REG_DSI_28nm_8960_PHY_PLL_CTRL_7 0x0000001c
256+
257+#define REG_DSI_28nm_8960_PHY_PLL_CTRL_8 0x00000020
258+
259+#define REG_DSI_28nm_8960_PHY_PLL_CTRL_9 0x00000024
260+
261+#define REG_DSI_28nm_8960_PHY_PLL_CTRL_10 0x00000028
262+
263+#define REG_DSI_28nm_8960_PHY_PLL_CTRL_11 0x0000002c
264+
265+#define REG_DSI_28nm_8960_PHY_PLL_CTRL_12 0x00000030
266+
267+#define REG_DSI_28nm_8960_PHY_PLL_CTRL_13 0x00000034
268+
269+#define REG_DSI_28nm_8960_PHY_PLL_CTRL_14 0x00000038
270+
271+#define REG_DSI_28nm_8960_PHY_PLL_CTRL_15 0x0000003c
272+
273+#define REG_DSI_28nm_8960_PHY_PLL_CTRL_16 0x00000040
274+
275+#define REG_DSI_28nm_8960_PHY_PLL_CTRL_17 0x00000044
276+
277+#define REG_DSI_28nm_8960_PHY_PLL_CTRL_18 0x00000048
278+
279+#define REG_DSI_28nm_8960_PHY_PLL_CTRL_19 0x0000004c
280+
281+#define REG_DSI_28nm_8960_PHY_PLL_CTRL_20 0x00000050
282+
283+#define REG_DSI_28nm_8960_PHY_PLL_RDY 0x00000080
284+#define DSI_28nm_8960_PHY_PLL_RDY_PLL_RDY 0x00000001
285+
286+
287+#endif /* DSI_PHY_28NM_8960_XML */
drivers/gpu/drm/msm/dsi/dsi_phy_5nm.xml.h+480−0
@@ -0,0 +1,480 @@
1+#ifndef DSI_PHY_5NM_XML
2+#define DSI_PHY_5NM_XML
3+
4+/* Autogenerated file, DO NOT EDIT manually!
5+
6+This file was generated by the rules-ng-ng headergen tool in this git repository:
7+http://github.com/freedreno/envytools/
8+git clone https://github.com/freedreno/envytools.git
9+
10+The rules-ng-ng source files this header was generated from are:
11+- /home/robclark/src/mesa/mesa/src/freedreno/registers/msm.xml ( 981 bytes, from 2021-06-05 21:37:42)
12+- /home/robclark/src/mesa/mesa/src/freedreno/registers/freedreno_copyright.xml ( 1572 bytes, from 2021-02-18 16:45:44)
13+- /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp4.xml ( 20912 bytes, from 2021-02-18 16:45:44)
14+- /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp_common.xml ( 2849 bytes, from 2021-02-18 16:45:44)
15+- /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp5.xml ( 37461 bytes, from 2021-02-18 16:45:44)
16+- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi.xml ( 15291 bytes, from 2021-06-15 22:36:13)
17+- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_v2.xml ( 3236 bytes, from 2021-06-05 21:37:42)
18+- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_28nm_8960.xml ( 4935 bytes, from 2021-05-21 19:18:08)
19+- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_28nm.xml ( 7004 bytes, from 2021-05-21 19:18:08)
20+- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_20nm.xml ( 3712 bytes, from 2021-05-21 19:18:08)
21+- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_14nm.xml ( 5381 bytes, from 2021-05-21 19:18:08)
22+- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_10nm.xml ( 4499 bytes, from 2021-05-21 19:18:08)
23+- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_7nm.xml ( 10953 bytes, from 2021-05-21 19:18:08)
24+- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_5nm.xml ( 10900 bytes, from 2021-05-21 19:18:08)
25+- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/sfpb.xml ( 602 bytes, from 2021-02-18 16:45:44)
26+- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/mmss_cc.xml ( 1686 bytes, from 2021-02-18 16:45:44)
27+- /home/robclark/src/mesa/mesa/src/freedreno/registers/hdmi/qfprom.xml ( 600 bytes, from 2021-02-18 16:45:44)
28+- /home/robclark/src/mesa/mesa/src/freedreno/registers/hdmi/hdmi.xml ( 41874 bytes, from 2021-02-18 16:45:44)
29+- /home/robclark/src/mesa/mesa/src/freedreno/registers/edp/edp.xml ( 10416 bytes, from 2021-02-18 16:45:44)
30+
31+Copyright (C) 2013-2021 by the following authors:
32+- Rob Clark <robdclark@gmail.com> (robclark)
33+- Ilia Mirkin <imirkin@alum.mit.edu> (imirkin)
34+
35+Permission is hereby granted, free of charge, to any person obtaining
36+a copy of this software and associated documentation files (the
37+"Software"), to deal in the Software without restriction, including
38+without limitation the rights to use, copy, modify, merge, publish,
39+distribute, sublicense, and/or sell copies of the Software, and to
40+permit persons to whom the Software is furnished to do so, subject to
41+the following conditions:
42+
43+The above copyright notice and this permission notice (including the
44+next paragraph) shall be included in all copies or substantial
45+portions of the Software.
46+
47+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
48+EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
49+MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
50+IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
51+LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
52+OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
53+WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
54+*/
55+
56+
57+#define REG_DSI_5nm_PHY_CMN_REVISION_ID0 0x00000000
58+
59+#define REG_DSI_5nm_PHY_CMN_REVISION_ID1 0x00000004
60+
61+#define REG_DSI_5nm_PHY_CMN_REVISION_ID2 0x00000008
62+
63+#define REG_DSI_5nm_PHY_CMN_REVISION_ID3 0x0000000c
64+
65+#define REG_DSI_5nm_PHY_CMN_CLK_CFG0 0x00000010
66+
67+#define REG_DSI_5nm_PHY_CMN_CLK_CFG1 0x00000014
68+
69+#define REG_DSI_5nm_PHY_CMN_GLBL_CTRL 0x00000018
70+
71+#define REG_DSI_5nm_PHY_CMN_RBUF_CTRL 0x0000001c
72+
73+#define REG_DSI_5nm_PHY_CMN_VREG_CTRL_0 0x00000020
74+
75+#define REG_DSI_5nm_PHY_CMN_CTRL_0 0x00000024
76+
77+#define REG_DSI_5nm_PHY_CMN_CTRL_1 0x00000028
78+
79+#define REG_DSI_5nm_PHY_CMN_CTRL_2 0x0000002c
80+
81+#define REG_DSI_5nm_PHY_CMN_CTRL_3 0x00000030
82+
83+#define REG_DSI_5nm_PHY_CMN_LANE_CFG0 0x00000034
84+
85+#define REG_DSI_5nm_PHY_CMN_LANE_CFG1 0x00000038
86+
87+#define REG_DSI_5nm_PHY_CMN_PLL_CNTRL 0x0000003c
88+
89+#define REG_DSI_5nm_PHY_CMN_DPHY_SOT 0x00000040
90+
91+#define REG_DSI_5nm_PHY_CMN_LANE_CTRL0 0x000000a0
92+
93+#define REG_DSI_5nm_PHY_CMN_LANE_CTRL1 0x000000a4
94+
95+#define REG_DSI_5nm_PHY_CMN_LANE_CTRL2 0x000000a8
96+
97+#define REG_DSI_5nm_PHY_CMN_LANE_CTRL3 0x000000ac
98+
99+#define REG_DSI_5nm_PHY_CMN_LANE_CTRL4 0x000000b0
100+
101+#define REG_DSI_5nm_PHY_CMN_TIMING_CTRL_0 0x000000b4
102+
103+#define REG_DSI_5nm_PHY_CMN_TIMING_CTRL_1 0x000000b8
104+
105+#define REG_DSI_5nm_PHY_CMN_TIMING_CTRL_2 0x000000bc
106+
107+#define REG_DSI_5nm_PHY_CMN_TIMING_CTRL_3 0x000000c0
108+
109+#define REG_DSI_5nm_PHY_CMN_TIMING_CTRL_4 0x000000c4
110+
111+#define REG_DSI_5nm_PHY_CMN_TIMING_CTRL_5 0x000000c8
112+
113+#define REG_DSI_5nm_PHY_CMN_TIMING_CTRL_6 0x000000cc
114+
115+#define REG_DSI_5nm_PHY_CMN_TIMING_CTRL_7 0x000000d0
116+
117+#define REG_DSI_5nm_PHY_CMN_TIMING_CTRL_8 0x000000d4
118+
119+#define REG_DSI_5nm_PHY_CMN_TIMING_CTRL_9 0x000000d8
120+
121+#define REG_DSI_5nm_PHY_CMN_TIMING_CTRL_10 0x000000dc
122+
123+#define REG_DSI_5nm_PHY_CMN_TIMING_CTRL_11 0x000000e0
124+
125+#define REG_DSI_5nm_PHY_CMN_TIMING_CTRL_12 0x000000e4
126+
127+#define REG_DSI_5nm_PHY_CMN_TIMING_CTRL_13 0x000000e8
128+
129+#define REG_DSI_5nm_PHY_CMN_GLBL_HSTX_STR_CTRL_0 0x000000ec
130+
131+#define REG_DSI_5nm_PHY_CMN_GLBL_HSTX_STR_CTRL_1 0x000000f0
132+
133+#define REG_DSI_5nm_PHY_CMN_GLBL_RESCODE_OFFSET_TOP_CTRL 0x000000f4
134+
135+#define REG_DSI_5nm_PHY_CMN_GLBL_RESCODE_OFFSET_BOT_CTRL 0x000000f8
136+
137+#define REG_DSI_5nm_PHY_CMN_GLBL_RESCODE_OFFSET_MID_CTRL 0x000000fc
138+
139+#define REG_DSI_5nm_PHY_CMN_GLBL_LPTX_STR_CTRL 0x00000100
140+
141+#define REG_DSI_5nm_PHY_CMN_GLBL_PEMPH_CTRL_0 0x00000104
142+
143+#define REG_DSI_5nm_PHY_CMN_GLBL_PEMPH_CTRL_1 0x00000108
144+
145+#define REG_DSI_5nm_PHY_CMN_GLBL_STR_SWI_CAL_SEL_CTRL 0x0000010c
146+
147+#define REG_DSI_5nm_PHY_CMN_VREG_CTRL_1 0x00000110
148+
149+#define REG_DSI_5nm_PHY_CMN_CTRL_4 0x00000114
150+
151+#define REG_DSI_5nm_PHY_CMN_PHY_STATUS 0x00000140
152+
153+#define REG_DSI_5nm_PHY_CMN_LANE_STATUS0 0x00000148
154+
155+#define REG_DSI_5nm_PHY_CMN_LANE_STATUS1 0x0000014c
156+
157+static inline uint32_t REG_DSI_5nm_PHY_LN(uint32_t i0) { return 0x00000000 + 0x80*i0; }
158+
159+static inline uint32_t REG_DSI_5nm_PHY_LN_CFG0(uint32_t i0) { return 0x00000000 + 0x80*i0; }
160+
161+static inline uint32_t REG_DSI_5nm_PHY_LN_CFG1(uint32_t i0) { return 0x00000004 + 0x80*i0; }
162+
163+static inline uint32_t REG_DSI_5nm_PHY_LN_CFG2(uint32_t i0) { return 0x00000008 + 0x80*i0; }
164+
165+static inline uint32_t REG_DSI_5nm_PHY_LN_TEST_DATAPATH(uint32_t i0) { return 0x0000000c + 0x80*i0; }
166+
167+static inline uint32_t REG_DSI_5nm_PHY_LN_PIN_SWAP(uint32_t i0) { return 0x00000010 + 0x80*i0; }
168+
169+static inline uint32_t REG_DSI_5nm_PHY_LN_LPRX_CTRL(uint32_t i0) { return 0x00000014 + 0x80*i0; }
170+
171+static inline uint32_t REG_DSI_5nm_PHY_LN_TX_DCTRL(uint32_t i0) { return 0x00000018 + 0x80*i0; }
172+
173+#define REG_DSI_5nm_PHY_PLL_ANALOG_CONTROLS_ONE 0x00000000
174+
175+#define REG_DSI_5nm_PHY_PLL_ANALOG_CONTROLS_TWO 0x00000004
176+
177+#define REG_DSI_5nm_PHY_PLL_INT_LOOP_SETTINGS 0x00000008
178+
179+#define REG_DSI_5nm_PHY_PLL_INT_LOOP_SETTINGS_TWO 0x0000000c
180+
181+#define REG_DSI_5nm_PHY_PLL_ANALOG_CONTROLS_THREE 0x00000010
182+
183+#define REG_DSI_5nm_PHY_PLL_ANALOG_CONTROLS_FOUR 0x00000014
184+
185+#define REG_DSI_5nm_PHY_PLL_ANALOG_CONTROLS_FIVE 0x00000018
186+
187+#define REG_DSI_5nm_PHY_PLL_INT_LOOP_CONTROLS 0x0000001c
188+
189+#define REG_DSI_5nm_PHY_PLL_DSM_DIVIDER 0x00000020
190+
191+#define REG_DSI_5nm_PHY_PLL_FEEDBACK_DIVIDER 0x00000024
192+
193+#define REG_DSI_5nm_PHY_PLL_SYSTEM_MUXES 0x00000028
194+
195+#define REG_DSI_5nm_PHY_PLL_FREQ_UPDATE_CONTROL_OVERRIDES 0x0000002c
196+
197+#define REG_DSI_5nm_PHY_PLL_CMODE 0x00000030
198+
199+#define REG_DSI_5nm_PHY_PLL_PSM_CTRL 0x00000034
200+
201+#define REG_DSI_5nm_PHY_PLL_RSM_CTRL 0x00000038
202+
203+#define REG_DSI_5nm_PHY_PLL_VCO_TUNE_MAP 0x0000003c
204+
205+#define REG_DSI_5nm_PHY_PLL_PLL_CNTRL 0x00000040
206+
207+#define REG_DSI_5nm_PHY_PLL_CALIBRATION_SETTINGS 0x00000044
208+
209+#define REG_DSI_5nm_PHY_PLL_BAND_SEL_CAL_TIMER_LOW 0x00000048
210+
211+#define REG_DSI_5nm_PHY_PLL_BAND_SEL_CAL_TIMER_HIGH 0x0000004c
212+
213+#define REG_DSI_5nm_PHY_PLL_BAND_SEL_CAL_SETTINGS 0x00000050
214+
215+#define REG_DSI_5nm_PHY_PLL_BAND_SEL_MIN 0x00000054
216+
217+#define REG_DSI_5nm_PHY_PLL_BAND_SEL_MAX 0x00000058
218+
219+#define REG_DSI_5nm_PHY_PLL_BAND_SEL_PFILT 0x0000005c
220+
221+#define REG_DSI_5nm_PHY_PLL_BAND_SEL_IFILT 0x00000060
222+
223+#define REG_DSI_5nm_PHY_PLL_BAND_SEL_CAL_SETTINGS_TWO 0x00000064
224+
225+#define REG_DSI_5nm_PHY_PLL_BAND_SEL_CAL_SETTINGS_THREE 0x00000068
226+
227+#define REG_DSI_5nm_PHY_PLL_BAND_SEL_CAL_SETTINGS_FOUR 0x0000006c
228+
229+#define REG_DSI_5nm_PHY_PLL_BAND_SEL_ICODE_HIGH 0x00000070
230+
231+#define REG_DSI_5nm_PHY_PLL_BAND_SEL_ICODE_LOW 0x00000074
232+
233+#define REG_DSI_5nm_PHY_PLL_FREQ_DETECT_SETTINGS_ONE 0x00000078
234+
235+#define REG_DSI_5nm_PHY_PLL_FREQ_DETECT_THRESH 0x0000007c
236+
237+#define REG_DSI_5nm_PHY_PLL_FREQ_DET_REFCLK_HIGH 0x00000080
238+
239+#define REG_DSI_5nm_PHY_PLL_FREQ_DET_REFCLK_LOW 0x00000084
240+
241+#define REG_DSI_5nm_PHY_PLL_FREQ_DET_PLLCLK_HIGH 0x00000088
242+
243+#define REG_DSI_5nm_PHY_PLL_FREQ_DET_PLLCLK_LOW 0x0000008c
244+
245+#define REG_DSI_5nm_PHY_PLL_PFILT 0x00000090
246+
247+#define REG_DSI_5nm_PHY_PLL_IFILT 0x00000094
248+
249+#define REG_DSI_5nm_PHY_PLL_PLL_GAIN 0x00000098
250+
251+#define REG_DSI_5nm_PHY_PLL_ICODE_LOW 0x0000009c
252+
253+#define REG_DSI_5nm_PHY_PLL_ICODE_HIGH 0x000000a0
254+
255+#define REG_DSI_5nm_PHY_PLL_LOCKDET 0x000000a4
256+
257+#define REG_DSI_5nm_PHY_PLL_OUTDIV 0x000000a8
258+
259+#define REG_DSI_5nm_PHY_PLL_FASTLOCK_CONTROL 0x000000ac
260+
261+#define REG_DSI_5nm_PHY_PLL_PASS_OUT_OVERRIDE_ONE 0x000000b0
262+
263+#define REG_DSI_5nm_PHY_PLL_PASS_OUT_OVERRIDE_TWO 0x000000b4
264+
265+#define REG_DSI_5nm_PHY_PLL_CORE_OVERRIDE 0x000000b8
266+
267+#define REG_DSI_5nm_PHY_PLL_CORE_INPUT_OVERRIDE 0x000000bc
268+
269+#define REG_DSI_5nm_PHY_PLL_RATE_CHANGE 0x000000c0
270+
271+#define REG_DSI_5nm_PHY_PLL_PLL_DIGITAL_TIMERS 0x000000c4
272+
273+#define REG_DSI_5nm_PHY_PLL_PLL_DIGITAL_TIMERS_TWO 0x000000c8
274+
275+#define REG_DSI_5nm_PHY_PLL_DECIMAL_DIV_START 0x000000cc
276+
277+#define REG_DSI_5nm_PHY_PLL_FRAC_DIV_START_LOW 0x000000d0
278+
279+#define REG_DSI_5nm_PHY_PLL_FRAC_DIV_START_MID 0x000000d4
280+
281+#define REG_DSI_5nm_PHY_PLL_FRAC_DIV_START_HIGH 0x000000d8
282+
283+#define REG_DSI_5nm_PHY_PLL_DEC_FRAC_MUXES 0x000000dc
284+
285+#define REG_DSI_5nm_PHY_PLL_DECIMAL_DIV_START_1 0x000000e0
286+
287+#define REG_DSI_5nm_PHY_PLL_FRAC_DIV_START_LOW_1 0x000000e4
288+
289+#define REG_DSI_5nm_PHY_PLL_FRAC_DIV_START_MID_1 0x000000e8
290+
291+#define REG_DSI_5nm_PHY_PLL_FRAC_DIV_START_HIGH_1 0x000000ec
292+
293+#define REG_DSI_5nm_PHY_PLL_DECIMAL_DIV_START_2 0x000000f0
294+
295+#define REG_DSI_5nm_PHY_PLL_FRAC_DIV_START_LOW_2 0x000000f4
296+
297+#define REG_DSI_5nm_PHY_PLL_FRAC_DIV_START_MID_2 0x000000f8
298+
299+#define REG_DSI_5nm_PHY_PLL_FRAC_DIV_START_HIGH_2 0x000000fc
300+
301+#define REG_DSI_5nm_PHY_PLL_MASH_CONTROL 0x00000100
302+
303+#define REG_DSI_5nm_PHY_PLL_SSC_STEPSIZE_LOW 0x00000104
304+
305+#define REG_DSI_5nm_PHY_PLL_SSC_STEPSIZE_HIGH 0x00000108
306+
307+#define REG_DSI_5nm_PHY_PLL_SSC_DIV_PER_LOW 0x0000010c
308+
309+#define REG_DSI_5nm_PHY_PLL_SSC_DIV_PER_HIGH 0x00000110
310+
311+#define REG_DSI_5nm_PHY_PLL_SSC_ADJPER_LOW 0x00000114
312+
313+#define REG_DSI_5nm_PHY_PLL_SSC_ADJPER_HIGH 0x00000118
314+
315+#define REG_DSI_5nm_PHY_PLL_SSC_MUX_CONTROL 0x0000011c
316+
317+#define REG_DSI_5nm_PHY_PLL_SSC_STEPSIZE_LOW_1 0x00000120
318+
319+#define REG_DSI_5nm_PHY_PLL_SSC_STEPSIZE_HIGH_1 0x00000124
320+
321+#define REG_DSI_5nm_PHY_PLL_SSC_DIV_PER_LOW_1 0x00000128
322+
323+#define REG_DSI_5nm_PHY_PLL_SSC_DIV_PER_HIGH_1 0x0000012c
324+
325+#define REG_DSI_5nm_PHY_PLL_SSC_ADJPER_LOW_1 0x00000130
326+
327+#define REG_DSI_5nm_PHY_PLL_SSC_ADJPER_HIGH_1 0x00000134
328+
329+#define REG_DSI_5nm_PHY_PLL_SSC_STEPSIZE_LOW_2 0x00000138
330+
331+#define REG_DSI_5nm_PHY_PLL_SSC_STEPSIZE_HIGH_2 0x0000013c
332+
333+#define REG_DSI_5nm_PHY_PLL_SSC_DIV_PER_LOW_2 0x00000140
334+
335+#define REG_DSI_5nm_PHY_PLL_SSC_DIV_PER_HIGH_2 0x00000144
336+
337+#define REG_DSI_5nm_PHY_PLL_SSC_ADJPER_LOW_2 0x00000148
338+
339+#define REG_DSI_5nm_PHY_PLL_SSC_ADJPER_HIGH_2 0x0000014c
340+
341+#define REG_DSI_5nm_PHY_PLL_SSC_CONTROL 0x00000150
342+
343+#define REG_DSI_5nm_PHY_PLL_PLL_OUTDIV_RATE 0x00000154
344+
345+#define REG_DSI_5nm_PHY_PLL_PLL_LOCKDET_RATE_1 0x00000158
346+
347+#define REG_DSI_5nm_PHY_PLL_PLL_LOCKDET_RATE_2 0x0000015c
348+
349+#define REG_DSI_5nm_PHY_PLL_PLL_PROP_GAIN_RATE_1 0x00000160
350+
351+#define REG_DSI_5nm_PHY_PLL_PLL_PROP_GAIN_RATE_2 0x00000164
352+
353+#define REG_DSI_5nm_PHY_PLL_PLL_BAND_SEL_RATE_1 0x00000168
354+
355+#define REG_DSI_5nm_PHY_PLL_PLL_BAND_SEL_RATE_2 0x0000016c
356+
357+#define REG_DSI_5nm_PHY_PLL_PLL_INT_GAIN_IFILT_BAND_1 0x00000170
358+
359+#define REG_DSI_5nm_PHY_PLL_PLL_INT_GAIN_IFILT_BAND_2 0x00000174
360+
361+#define REG_DSI_5nm_PHY_PLL_PLL_FL_INT_GAIN_PFILT_BAND_1 0x00000178
362+
363+#define REG_DSI_5nm_PHY_PLL_PLL_FL_INT_GAIN_PFILT_BAND_2 0x0000017c
364+
365+#define REG_DSI_5nm_PHY_PLL_PLL_FASTLOCK_EN_BAND 0x00000180
366+
367+#define REG_DSI_5nm_PHY_PLL_FREQ_TUNE_ACCUM_INIT_MID 0x00000184
368+
369+#define REG_DSI_5nm_PHY_PLL_FREQ_TUNE_ACCUM_INIT_HIGH 0x00000188
370+
371+#define REG_DSI_5nm_PHY_PLL_FREQ_TUNE_ACCUM_INIT_MUX 0x0000018c
372+
373+#define REG_DSI_5nm_PHY_PLL_PLL_LOCK_OVERRIDE 0x00000190
374+
375+#define REG_DSI_5nm_PHY_PLL_PLL_LOCK_DELAY 0x00000194
376+
377+#define REG_DSI_5nm_PHY_PLL_PLL_LOCK_MIN_DELAY 0x00000198
378+
379+#define REG_DSI_5nm_PHY_PLL_CLOCK_INVERTERS 0x0000019c
380+
381+#define REG_DSI_5nm_PHY_PLL_SPARE_AND_JPC_OVERRIDES 0x000001a0
382+
383+#define REG_DSI_5nm_PHY_PLL_BIAS_CONTROL_1 0x000001a4
384+
385+#define REG_DSI_5nm_PHY_PLL_BIAS_CONTROL_2 0x000001a8
386+
387+#define REG_DSI_5nm_PHY_PLL_ALOG_OBSV_BUS_CTRL_1 0x000001ac
388+
389+#define REG_DSI_5nm_PHY_PLL_COMMON_STATUS_ONE 0x000001b0
390+
391+#define REG_DSI_5nm_PHY_PLL_COMMON_STATUS_TWO 0x000001b4
392+
393+#define REG_DSI_5nm_PHY_PLL_BAND_SEL_CAL 0x000001b8
394+
395+#define REG_DSI_5nm_PHY_PLL_ICODE_ACCUM_STATUS_LOW 0x000001bc
396+
397+#define REG_DSI_5nm_PHY_PLL_ICODE_ACCUM_STATUS_HIGH 0x000001c0
398+
399+#define REG_DSI_5nm_PHY_PLL_FD_OUT_LOW 0x000001c4
400+
401+#define REG_DSI_5nm_PHY_PLL_FD_OUT_HIGH 0x000001c8
402+
403+#define REG_DSI_5nm_PHY_PLL_ALOG_OBSV_BUS_STATUS_1 0x000001cc
404+
405+#define REG_DSI_5nm_PHY_PLL_PLL_MISC_CONFIG 0x000001d0
406+
407+#define REG_DSI_5nm_PHY_PLL_FLL_CONFIG 0x000001d4
408+
409+#define REG_DSI_5nm_PHY_PLL_FLL_FREQ_ACQ_TIME 0x000001d8
410+
411+#define REG_DSI_5nm_PHY_PLL_FLL_CODE0 0x000001dc
412+
413+#define REG_DSI_5nm_PHY_PLL_FLL_CODE1 0x000001e0
414+
415+#define REG_DSI_5nm_PHY_PLL_FLL_GAIN0 0x000001e4
416+
417+#define REG_DSI_5nm_PHY_PLL_FLL_GAIN1 0x000001e8
418+
419+#define REG_DSI_5nm_PHY_PLL_SW_RESET 0x000001ec
420+
421+#define REG_DSI_5nm_PHY_PLL_FAST_PWRUP 0x000001f0
422+
423+#define REG_DSI_5nm_PHY_PLL_LOCKTIME0 0x000001f4
424+
425+#define REG_DSI_5nm_PHY_PLL_LOCKTIME1 0x000001f8
426+
427+#define REG_DSI_5nm_PHY_PLL_DEBUG_BUS_SEL 0x000001fc
428+
429+#define REG_DSI_5nm_PHY_PLL_DEBUG_BUS0 0x00000200
430+
431+#define REG_DSI_5nm_PHY_PLL_DEBUG_BUS1 0x00000204
432+
433+#define REG_DSI_5nm_PHY_PLL_DEBUG_BUS2 0x00000208
434+
435+#define REG_DSI_5nm_PHY_PLL_DEBUG_BUS3 0x0000020c
436+
437+#define REG_DSI_5nm_PHY_PLL_ANALOG_FLL_CONTROL_OVERRIDES 0x00000210
438+
439+#define REG_DSI_5nm_PHY_PLL_VCO_CONFIG 0x00000214
440+
441+#define REG_DSI_5nm_PHY_PLL_VCO_CAL_CODE1_MODE0_STATUS 0x00000218
442+
443+#define REG_DSI_5nm_PHY_PLL_VCO_CAL_CODE1_MODE1_STATUS 0x0000021c
444+
445+#define REG_DSI_5nm_PHY_PLL_RESET_SM_STATUS 0x00000220
446+
447+#define REG_DSI_5nm_PHY_PLL_TDC_OFFSET 0x00000224
448+
449+#define REG_DSI_5nm_PHY_PLL_PS3_PWRDOWN_CONTROLS 0x00000228
450+
451+#define REG_DSI_5nm_PHY_PLL_PS4_PWRDOWN_CONTROLS 0x0000022c
452+
453+#define REG_DSI_5nm_PHY_PLL_PLL_RST_CONTROLS 0x00000230
454+
455+#define REG_DSI_5nm_PHY_PLL_GEAR_BAND_SELECT_CONTROLS 0x00000234
456+
457+#define REG_DSI_5nm_PHY_PLL_PSM_CLK_CONTROLS 0x00000238
458+
459+#define REG_DSI_5nm_PHY_PLL_SYSTEM_MUXES_2 0x0000023c
460+
461+#define REG_DSI_5nm_PHY_PLL_VCO_CONFIG_1 0x00000240
462+
463+#define REG_DSI_5nm_PHY_PLL_VCO_CONFIG_2 0x00000244
464+
465+#define REG_DSI_5nm_PHY_PLL_CLOCK_INVERTERS_1 0x00000248
466+
467+#define REG_DSI_5nm_PHY_PLL_CLOCK_INVERTERS_2 0x0000024c
468+
469+#define REG_DSI_5nm_PHY_PLL_CMODE_1 0x00000250
470+
471+#define REG_DSI_5nm_PHY_PLL_CMODE_2 0x00000254
472+
473+#define REG_DSI_5nm_PHY_PLL_ANALOG_CONTROLS_FIVE_1 0x00000258
474+
475+#define REG_DSI_5nm_PHY_PLL_ANALOG_CONTROLS_FIVE_2 0x0000025c
476+
477+#define REG_DSI_5nm_PHY_PLL_PERF_OPTIMIZE 0x00000260
478+
479+
480+#endif /* DSI_PHY_5NM_XML */
drivers/gpu/drm/msm/dsi/dsi_phy_7nm.xml.h+482−0
@@ -0,0 +1,482 @@
1+#ifndef DSI_PHY_7NM_XML
2+#define DSI_PHY_7NM_XML
3+
4+/* Autogenerated file, DO NOT EDIT manually!
5+
6+This file was generated by the rules-ng-ng headergen tool in this git repository:
7+http://github.com/freedreno/envytools/
8+git clone https://github.com/freedreno/envytools.git
9+
10+The rules-ng-ng source files this header was generated from are:
11+- /home/robclark/src/mesa/mesa/src/freedreno/registers/msm.xml ( 981 bytes, from 2021-06-05 21:37:42)
12+- /home/robclark/src/mesa/mesa/src/freedreno/registers/freedreno_copyright.xml ( 1572 bytes, from 2021-02-18 16:45:44)
13+- /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp4.xml ( 20912 bytes, from 2021-02-18 16:45:44)
14+- /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp_common.xml ( 2849 bytes, from 2021-02-18 16:45:44)
15+- /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp5.xml ( 37461 bytes, from 2021-02-18 16:45:44)
16+- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi.xml ( 15291 bytes, from 2021-06-15 22:36:13)
17+- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_v2.xml ( 3236 bytes, from 2021-06-05 21:37:42)
18+- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_28nm_8960.xml ( 4935 bytes, from 2021-05-21 19:18:08)
19+- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_28nm.xml ( 7004 bytes, from 2021-05-21 19:18:08)
20+- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_20nm.xml ( 3712 bytes, from 2021-05-21 19:18:08)
21+- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_14nm.xml ( 5381 bytes, from 2021-05-21 19:18:08)
22+- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_10nm.xml ( 4499 bytes, from 2021-05-21 19:18:08)
23+- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_7nm.xml ( 10953 bytes, from 2021-05-21 19:18:08)
24+- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_5nm.xml ( 10900 bytes, from 2021-05-21 19:18:08)
25+- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/sfpb.xml ( 602 bytes, from 2021-02-18 16:45:44)
26+- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/mmss_cc.xml ( 1686 bytes, from 2021-02-18 16:45:44)
27+- /home/robclark/src/mesa/mesa/src/freedreno/registers/hdmi/qfprom.xml ( 600 bytes, from 2021-02-18 16:45:44)
28+- /home/robclark/src/mesa/mesa/src/freedreno/registers/hdmi/hdmi.xml ( 41874 bytes, from 2021-02-18 16:45:44)
29+- /home/robclark/src/mesa/mesa/src/freedreno/registers/edp/edp.xml ( 10416 bytes, from 2021-02-18 16:45:44)
30+
31+Copyright (C) 2013-2021 by the following authors:
32+- Rob Clark <robdclark@gmail.com> (robclark)
33+- Ilia Mirkin <imirkin@alum.mit.edu> (imirkin)
34+
35+Permission is hereby granted, free of charge, to any person obtaining
36+a copy of this software and associated documentation files (the
37+"Software"), to deal in the Software without restriction, including
38+without limitation the rights to use, copy, modify, merge, publish,
39+distribute, sublicense, and/or sell copies of the Software, and to
40+permit persons to whom the Software is furnished to do so, subject to
41+the following conditions:
42+
43+The above copyright notice and this permission notice (including the
44+next paragraph) shall be included in all copies or substantial
45+portions of the Software.
46+
47+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
48+EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
49+MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
50+IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
51+LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
52+OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
53+WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
54+*/
55+
56+
57+#define REG_DSI_7nm_PHY_CMN_REVISION_ID0 0x00000000
58+
59+#define REG_DSI_7nm_PHY_CMN_REVISION_ID1 0x00000004
60+
61+#define REG_DSI_7nm_PHY_CMN_REVISION_ID2 0x00000008
62+
63+#define REG_DSI_7nm_PHY_CMN_REVISION_ID3 0x0000000c
64+
65+#define REG_DSI_7nm_PHY_CMN_CLK_CFG0 0x00000010
66+
67+#define REG_DSI_7nm_PHY_CMN_CLK_CFG1 0x00000014
68+
69+#define REG_DSI_7nm_PHY_CMN_GLBL_CTRL 0x00000018
70+
71+#define REG_DSI_7nm_PHY_CMN_RBUF_CTRL 0x0000001c
72+
73+#define REG_DSI_7nm_PHY_CMN_VREG_CTRL_0 0x00000020
74+
75+#define REG_DSI_7nm_PHY_CMN_CTRL_0 0x00000024
76+
77+#define REG_DSI_7nm_PHY_CMN_CTRL_1 0x00000028
78+
79+#define REG_DSI_7nm_PHY_CMN_CTRL_2 0x0000002c
80+
81+#define REG_DSI_7nm_PHY_CMN_CTRL_3 0x00000030
82+
83+#define REG_DSI_7nm_PHY_CMN_LANE_CFG0 0x00000034
84+
85+#define REG_DSI_7nm_PHY_CMN_LANE_CFG1 0x00000038
86+
87+#define REG_DSI_7nm_PHY_CMN_PLL_CNTRL 0x0000003c
88+
89+#define REG_DSI_7nm_PHY_CMN_DPHY_SOT 0x00000040
90+
91+#define REG_DSI_7nm_PHY_CMN_LANE_CTRL0 0x000000a0
92+
93+#define REG_DSI_7nm_PHY_CMN_LANE_CTRL1 0x000000a4
94+
95+#define REG_DSI_7nm_PHY_CMN_LANE_CTRL2 0x000000a8
96+
97+#define REG_DSI_7nm_PHY_CMN_LANE_CTRL3 0x000000ac
98+
99+#define REG_DSI_7nm_PHY_CMN_LANE_CTRL4 0x000000b0
100+
101+#define REG_DSI_7nm_PHY_CMN_TIMING_CTRL_0 0x000000b4
102+
103+#define REG_DSI_7nm_PHY_CMN_TIMING_CTRL_1 0x000000b8
104+
105+#define REG_DSI_7nm_PHY_CMN_TIMING_CTRL_2 0x000000bc
106+
107+#define REG_DSI_7nm_PHY_CMN_TIMING_CTRL_3 0x000000c0
108+
109+#define REG_DSI_7nm_PHY_CMN_TIMING_CTRL_4 0x000000c4
110+
111+#define REG_DSI_7nm_PHY_CMN_TIMING_CTRL_5 0x000000c8
112+
113+#define REG_DSI_7nm_PHY_CMN_TIMING_CTRL_6 0x000000cc
114+
115+#define REG_DSI_7nm_PHY_CMN_TIMING_CTRL_7 0x000000d0
116+
117+#define REG_DSI_7nm_PHY_CMN_TIMING_CTRL_8 0x000000d4
118+
119+#define REG_DSI_7nm_PHY_CMN_TIMING_CTRL_9 0x000000d8
120+
121+#define REG_DSI_7nm_PHY_CMN_TIMING_CTRL_10 0x000000dc
122+
123+#define REG_DSI_7nm_PHY_CMN_TIMING_CTRL_11 0x000000e0
124+
125+#define REG_DSI_7nm_PHY_CMN_TIMING_CTRL_12 0x000000e4
126+
127+#define REG_DSI_7nm_PHY_CMN_TIMING_CTRL_13 0x000000e8
128+
129+#define REG_DSI_7nm_PHY_CMN_GLBL_HSTX_STR_CTRL_0 0x000000ec
130+
131+#define REG_DSI_7nm_PHY_CMN_GLBL_HSTX_STR_CTRL_1 0x000000f0
132+
133+#define REG_DSI_7nm_PHY_CMN_GLBL_RESCODE_OFFSET_TOP_CTRL 0x000000f4
134+
135+#define REG_DSI_7nm_PHY_CMN_GLBL_RESCODE_OFFSET_BOT_CTRL 0x000000f8
136+
137+#define REG_DSI_7nm_PHY_CMN_GLBL_RESCODE_OFFSET_MID_CTRL 0x000000fc
138+
139+#define REG_DSI_7nm_PHY_CMN_GLBL_LPTX_STR_CTRL 0x00000100
140+
141+#define REG_DSI_7nm_PHY_CMN_GLBL_PEMPH_CTRL_0 0x00000104
142+
143+#define REG_DSI_7nm_PHY_CMN_GLBL_PEMPH_CTRL_1 0x00000108
144+
145+#define REG_DSI_7nm_PHY_CMN_GLBL_STR_SWI_CAL_SEL_CTRL 0x0000010c
146+
147+#define REG_DSI_7nm_PHY_CMN_VREG_CTRL_1 0x00000110
148+
149+#define REG_DSI_7nm_PHY_CMN_CTRL_4 0x00000114
150+
151+#define REG_DSI_7nm_PHY_CMN_GLBL_DIGTOP_SPARE4 0x00000128
152+
153+#define REG_DSI_7nm_PHY_CMN_PHY_STATUS 0x00000140
154+
155+#define REG_DSI_7nm_PHY_CMN_LANE_STATUS0 0x00000148
156+
157+#define REG_DSI_7nm_PHY_CMN_LANE_STATUS1 0x0000014c
158+
159+static inline uint32_t REG_DSI_7nm_PHY_LN(uint32_t i0) { return 0x00000000 + 0x80*i0; }
160+
161+static inline uint32_t REG_DSI_7nm_PHY_LN_CFG0(uint32_t i0) { return 0x00000000 + 0x80*i0; }
162+
163+static inline uint32_t REG_DSI_7nm_PHY_LN_CFG1(uint32_t i0) { return 0x00000004 + 0x80*i0; }
164+
165+static inline uint32_t REG_DSI_7nm_PHY_LN_CFG2(uint32_t i0) { return 0x00000008 + 0x80*i0; }
166+
167+static inline uint32_t REG_DSI_7nm_PHY_LN_TEST_DATAPATH(uint32_t i0) { return 0x0000000c + 0x80*i0; }
168+
169+static inline uint32_t REG_DSI_7nm_PHY_LN_PIN_SWAP(uint32_t i0) { return 0x00000010 + 0x80*i0; }
170+
171+static inline uint32_t REG_DSI_7nm_PHY_LN_LPRX_CTRL(uint32_t i0) { return 0x00000014 + 0x80*i0; }
172+
173+static inline uint32_t REG_DSI_7nm_PHY_LN_TX_DCTRL(uint32_t i0) { return 0x00000018 + 0x80*i0; }
174+
175+#define REG_DSI_7nm_PHY_PLL_ANALOG_CONTROLS_ONE 0x00000000
176+
177+#define REG_DSI_7nm_PHY_PLL_ANALOG_CONTROLS_TWO 0x00000004
178+
179+#define REG_DSI_7nm_PHY_PLL_INT_LOOP_SETTINGS 0x00000008
180+
181+#define REG_DSI_7nm_PHY_PLL_INT_LOOP_SETTINGS_TWO 0x0000000c
182+
183+#define REG_DSI_7nm_PHY_PLL_ANALOG_CONTROLS_THREE 0x00000010
184+
185+#define REG_DSI_7nm_PHY_PLL_ANALOG_CONTROLS_FOUR 0x00000014
186+
187+#define REG_DSI_7nm_PHY_PLL_ANALOG_CONTROLS_FIVE 0x00000018
188+
189+#define REG_DSI_7nm_PHY_PLL_INT_LOOP_CONTROLS 0x0000001c
190+
191+#define REG_DSI_7nm_PHY_PLL_DSM_DIVIDER 0x00000020
192+
193+#define REG_DSI_7nm_PHY_PLL_FEEDBACK_DIVIDER 0x00000024
194+
195+#define REG_DSI_7nm_PHY_PLL_SYSTEM_MUXES 0x00000028
196+
197+#define REG_DSI_7nm_PHY_PLL_FREQ_UPDATE_CONTROL_OVERRIDES 0x0000002c
198+
199+#define REG_DSI_7nm_PHY_PLL_CMODE 0x00000030
200+
201+#define REG_DSI_7nm_PHY_PLL_PSM_CTRL 0x00000034
202+
203+#define REG_DSI_7nm_PHY_PLL_RSM_CTRL 0x00000038
204+
205+#define REG_DSI_7nm_PHY_PLL_VCO_TUNE_MAP 0x0000003c
206+
207+#define REG_DSI_7nm_PHY_PLL_PLL_CNTRL 0x00000040
208+
209+#define REG_DSI_7nm_PHY_PLL_CALIBRATION_SETTINGS 0x00000044
210+
211+#define REG_DSI_7nm_PHY_PLL_BAND_SEL_CAL_TIMER_LOW 0x00000048
212+
213+#define REG_DSI_7nm_PHY_PLL_BAND_SEL_CAL_TIMER_HIGH 0x0000004c
214+
215+#define REG_DSI_7nm_PHY_PLL_BAND_SEL_CAL_SETTINGS 0x00000050
216+
217+#define REG_DSI_7nm_PHY_PLL_BAND_SEL_MIN 0x00000054
218+
219+#define REG_DSI_7nm_PHY_PLL_BAND_SEL_MAX 0x00000058
220+
221+#define REG_DSI_7nm_PHY_PLL_BAND_SEL_PFILT 0x0000005c
222+
223+#define REG_DSI_7nm_PHY_PLL_BAND_SEL_IFILT 0x00000060
224+
225+#define REG_DSI_7nm_PHY_PLL_BAND_SEL_CAL_SETTINGS_TWO 0x00000064
226+
227+#define REG_DSI_7nm_PHY_PLL_BAND_SEL_CAL_SETTINGS_THREE 0x00000068
228+
229+#define REG_DSI_7nm_PHY_PLL_BAND_SEL_CAL_SETTINGS_FOUR 0x0000006c
230+
231+#define REG_DSI_7nm_PHY_PLL_BAND_SEL_ICODE_HIGH 0x00000070
232+
233+#define REG_DSI_7nm_PHY_PLL_BAND_SEL_ICODE_LOW 0x00000074
234+
235+#define REG_DSI_7nm_PHY_PLL_FREQ_DETECT_SETTINGS_ONE 0x00000078
236+
237+#define REG_DSI_7nm_PHY_PLL_FREQ_DETECT_THRESH 0x0000007c
238+
239+#define REG_DSI_7nm_PHY_PLL_FREQ_DET_REFCLK_HIGH 0x00000080
240+
241+#define REG_DSI_7nm_PHY_PLL_FREQ_DET_REFCLK_LOW 0x00000084
242+
243+#define REG_DSI_7nm_PHY_PLL_FREQ_DET_PLLCLK_HIGH 0x00000088
244+
245+#define REG_DSI_7nm_PHY_PLL_FREQ_DET_PLLCLK_LOW 0x0000008c
246+
247+#define REG_DSI_7nm_PHY_PLL_PFILT 0x00000090
248+
249+#define REG_DSI_7nm_PHY_PLL_IFILT 0x00000094
250+
251+#define REG_DSI_7nm_PHY_PLL_PLL_GAIN 0x00000098
252+
253+#define REG_DSI_7nm_PHY_PLL_ICODE_LOW 0x0000009c
254+
255+#define REG_DSI_7nm_PHY_PLL_ICODE_HIGH 0x000000a0
256+
257+#define REG_DSI_7nm_PHY_PLL_LOCKDET 0x000000a4
258+
259+#define REG_DSI_7nm_PHY_PLL_OUTDIV 0x000000a8
260+
261+#define REG_DSI_7nm_PHY_PLL_FASTLOCK_CONTROL 0x000000ac
262+
263+#define REG_DSI_7nm_PHY_PLL_PASS_OUT_OVERRIDE_ONE 0x000000b0
264+
265+#define REG_DSI_7nm_PHY_PLL_PASS_OUT_OVERRIDE_TWO 0x000000b4
266+
267+#define REG_DSI_7nm_PHY_PLL_CORE_OVERRIDE 0x000000b8
268+
269+#define REG_DSI_7nm_PHY_PLL_CORE_INPUT_OVERRIDE 0x000000bc
270+
271+#define REG_DSI_7nm_PHY_PLL_RATE_CHANGE 0x000000c0
272+
273+#define REG_DSI_7nm_PHY_PLL_PLL_DIGITAL_TIMERS 0x000000c4
274+
275+#define REG_DSI_7nm_PHY_PLL_PLL_DIGITAL_TIMERS_TWO 0x000000c8
276+
277+#define REG_DSI_7nm_PHY_PLL_DECIMAL_DIV_START 0x000000cc
278+
279+#define REG_DSI_7nm_PHY_PLL_FRAC_DIV_START_LOW 0x000000d0
280+
281+#define REG_DSI_7nm_PHY_PLL_FRAC_DIV_START_MID 0x000000d4
282+
283+#define REG_DSI_7nm_PHY_PLL_FRAC_DIV_START_HIGH 0x000000d8
284+
285+#define REG_DSI_7nm_PHY_PLL_DEC_FRAC_MUXES 0x000000dc
286+
287+#define REG_DSI_7nm_PHY_PLL_DECIMAL_DIV_START_1 0x000000e0
288+
289+#define REG_DSI_7nm_PHY_PLL_FRAC_DIV_START_LOW_1 0x000000e4
290+
291+#define REG_DSI_7nm_PHY_PLL_FRAC_DIV_START_MID_1 0x000000e8
292+
293+#define REG_DSI_7nm_PHY_PLL_FRAC_DIV_START_HIGH_1 0x000000ec
294+
295+#define REG_DSI_7nm_PHY_PLL_DECIMAL_DIV_START_2 0x000000f0
296+
297+#define REG_DSI_7nm_PHY_PLL_FRAC_DIV_START_LOW_2 0x000000f4
298+
299+#define REG_DSI_7nm_PHY_PLL_FRAC_DIV_START_MID_2 0x000000f8
300+
301+#define REG_DSI_7nm_PHY_PLL_FRAC_DIV_START_HIGH_2 0x000000fc
302+
303+#define REG_DSI_7nm_PHY_PLL_MASH_CONTROL 0x00000100
304+
305+#define REG_DSI_7nm_PHY_PLL_SSC_STEPSIZE_LOW 0x00000104
306+
307+#define REG_DSI_7nm_PHY_PLL_SSC_STEPSIZE_HIGH 0x00000108
308+
309+#define REG_DSI_7nm_PHY_PLL_SSC_DIV_PER_LOW 0x0000010c
310+
311+#define REG_DSI_7nm_PHY_PLL_SSC_DIV_PER_HIGH 0x00000110
312+
313+#define REG_DSI_7nm_PHY_PLL_SSC_ADJPER_LOW 0x00000114
314+
315+#define REG_DSI_7nm_PHY_PLL_SSC_ADJPER_HIGH 0x00000118
316+
317+#define REG_DSI_7nm_PHY_PLL_SSC_MUX_CONTROL 0x0000011c
318+
319+#define REG_DSI_7nm_PHY_PLL_SSC_STEPSIZE_LOW_1 0x00000120
320+
321+#define REG_DSI_7nm_PHY_PLL_SSC_STEPSIZE_HIGH_1 0x00000124
322+
323+#define REG_DSI_7nm_PHY_PLL_SSC_DIV_PER_LOW_1 0x00000128
324+
325+#define REG_DSI_7nm_PHY_PLL_SSC_DIV_PER_HIGH_1 0x0000012c
326+
327+#define REG_DSI_7nm_PHY_PLL_SSC_ADJPER_LOW_1 0x00000130
328+
329+#define REG_DSI_7nm_PHY_PLL_SSC_ADJPER_HIGH_1 0x00000134
330+
331+#define REG_DSI_7nm_PHY_PLL_SSC_STEPSIZE_LOW_2 0x00000138
332+
333+#define REG_DSI_7nm_PHY_PLL_SSC_STEPSIZE_HIGH_2 0x0000013c
334+
335+#define REG_DSI_7nm_PHY_PLL_SSC_DIV_PER_LOW_2 0x00000140
336+
337+#define REG_DSI_7nm_PHY_PLL_SSC_DIV_PER_HIGH_2 0x00000144
338+
339+#define REG_DSI_7nm_PHY_PLL_SSC_ADJPER_LOW_2 0x00000148
340+
341+#define REG_DSI_7nm_PHY_PLL_SSC_ADJPER_HIGH_2 0x0000014c
342+
343+#define REG_DSI_7nm_PHY_PLL_SSC_CONTROL 0x00000150
344+
345+#define REG_DSI_7nm_PHY_PLL_PLL_OUTDIV_RATE 0x00000154
346+
347+#define REG_DSI_7nm_PHY_PLL_PLL_LOCKDET_RATE_1 0x00000158
348+
349+#define REG_DSI_7nm_PHY_PLL_PLL_LOCKDET_RATE_2 0x0000015c
350+
351+#define REG_DSI_7nm_PHY_PLL_PLL_PROP_GAIN_RATE_1 0x00000160
352+
353+#define REG_DSI_7nm_PHY_PLL_PLL_PROP_GAIN_RATE_2 0x00000164
354+
355+#define REG_DSI_7nm_PHY_PLL_PLL_BAND_SEL_RATE_1 0x00000168
356+
357+#define REG_DSI_7nm_PHY_PLL_PLL_BAND_SEL_RATE_2 0x0000016c
358+
359+#define REG_DSI_7nm_PHY_PLL_PLL_INT_GAIN_IFILT_BAND_1 0x00000170
360+
361+#define REG_DSI_7nm_PHY_PLL_PLL_INT_GAIN_IFILT_BAND_2 0x00000174
362+
363+#define REG_DSI_7nm_PHY_PLL_PLL_FL_INT_GAIN_PFILT_BAND_1 0x00000178
364+
365+#define REG_DSI_7nm_PHY_PLL_PLL_FL_INT_GAIN_PFILT_BAND_2 0x0000017c
366+
367+#define REG_DSI_7nm_PHY_PLL_PLL_FASTLOCK_EN_BAND 0x00000180
368+
369+#define REG_DSI_7nm_PHY_PLL_FREQ_TUNE_ACCUM_INIT_MID 0x00000184
370+
371+#define REG_DSI_7nm_PHY_PLL_FREQ_TUNE_ACCUM_INIT_HIGH 0x00000188
372+
373+#define REG_DSI_7nm_PHY_PLL_FREQ_TUNE_ACCUM_INIT_MUX 0x0000018c
374+
375+#define REG_DSI_7nm_PHY_PLL_PLL_LOCK_OVERRIDE 0x00000190
376+
377+#define REG_DSI_7nm_PHY_PLL_PLL_LOCK_DELAY 0x00000194
378+
379+#define REG_DSI_7nm_PHY_PLL_PLL_LOCK_MIN_DELAY 0x00000198
380+
381+#define REG_DSI_7nm_PHY_PLL_CLOCK_INVERTERS 0x0000019c
382+
383+#define REG_DSI_7nm_PHY_PLL_SPARE_AND_JPC_OVERRIDES 0x000001a0
384+
385+#define REG_DSI_7nm_PHY_PLL_BIAS_CONTROL_1 0x000001a4
386+
387+#define REG_DSI_7nm_PHY_PLL_BIAS_CONTROL_2 0x000001a8
388+
389+#define REG_DSI_7nm_PHY_PLL_ALOG_OBSV_BUS_CTRL_1 0x000001ac
390+
391+#define REG_DSI_7nm_PHY_PLL_COMMON_STATUS_ONE 0x000001b0
392+
393+#define REG_DSI_7nm_PHY_PLL_COMMON_STATUS_TWO 0x000001b4
394+
395+#define REG_DSI_7nm_PHY_PLL_BAND_SEL_CAL 0x000001b8
396+
397+#define REG_DSI_7nm_PHY_PLL_ICODE_ACCUM_STATUS_LOW 0x000001bc
398+
399+#define REG_DSI_7nm_PHY_PLL_ICODE_ACCUM_STATUS_HIGH 0x000001c0
400+
401+#define REG_DSI_7nm_PHY_PLL_FD_OUT_LOW 0x000001c4
402+
403+#define REG_DSI_7nm_PHY_PLL_FD_OUT_HIGH 0x000001c8
404+
405+#define REG_DSI_7nm_PHY_PLL_ALOG_OBSV_BUS_STATUS_1 0x000001cc
406+
407+#define REG_DSI_7nm_PHY_PLL_PLL_MISC_CONFIG 0x000001d0
408+
409+#define REG_DSI_7nm_PHY_PLL_FLL_CONFIG 0x000001d4
410+
411+#define REG_DSI_7nm_PHY_PLL_FLL_FREQ_ACQ_TIME 0x000001d8
412+
413+#define REG_DSI_7nm_PHY_PLL_FLL_CODE0 0x000001dc
414+
415+#define REG_DSI_7nm_PHY_PLL_FLL_CODE1 0x000001e0
416+
417+#define REG_DSI_7nm_PHY_PLL_FLL_GAIN0 0x000001e4
418+
419+#define REG_DSI_7nm_PHY_PLL_FLL_GAIN1 0x000001e8
420+
421+#define REG_DSI_7nm_PHY_PLL_SW_RESET 0x000001ec
422+
423+#define REG_DSI_7nm_PHY_PLL_FAST_PWRUP 0x000001f0
424+
425+#define REG_DSI_7nm_PHY_PLL_LOCKTIME0 0x000001f4
426+
427+#define REG_DSI_7nm_PHY_PLL_LOCKTIME1 0x000001f8
428+
429+#define REG_DSI_7nm_PHY_PLL_DEBUG_BUS_SEL 0x000001fc
430+
431+#define REG_DSI_7nm_PHY_PLL_DEBUG_BUS0 0x00000200
432+
433+#define REG_DSI_7nm_PHY_PLL_DEBUG_BUS1 0x00000204
434+
435+#define REG_DSI_7nm_PHY_PLL_DEBUG_BUS2 0x00000208
436+
437+#define REG_DSI_7nm_PHY_PLL_DEBUG_BUS3 0x0000020c
438+
439+#define REG_DSI_7nm_PHY_PLL_ANALOG_FLL_CONTROL_OVERRIDES 0x00000210
440+
441+#define REG_DSI_7nm_PHY_PLL_VCO_CONFIG 0x00000214
442+
443+#define REG_DSI_7nm_PHY_PLL_VCO_CAL_CODE1_MODE0_STATUS 0x00000218
444+
445+#define REG_DSI_7nm_PHY_PLL_VCO_CAL_CODE1_MODE1_STATUS 0x0000021c
446+
447+#define REG_DSI_7nm_PHY_PLL_RESET_SM_STATUS 0x00000220
448+
449+#define REG_DSI_7nm_PHY_PLL_TDC_OFFSET 0x00000224
450+
451+#define REG_DSI_7nm_PHY_PLL_PS3_PWRDOWN_CONTROLS 0x00000228
452+
453+#define REG_DSI_7nm_PHY_PLL_PS4_PWRDOWN_CONTROLS 0x0000022c
454+
455+#define REG_DSI_7nm_PHY_PLL_PLL_RST_CONTROLS 0x00000230
456+
457+#define REG_DSI_7nm_PHY_PLL_GEAR_BAND_SELECT_CONTROLS 0x00000234
458+
459+#define REG_DSI_7nm_PHY_PLL_PSM_CLK_CONTROLS 0x00000238
460+
461+#define REG_DSI_7nm_PHY_PLL_SYSTEM_MUXES_2 0x0000023c
462+
463+#define REG_DSI_7nm_PHY_PLL_VCO_CONFIG_1 0x00000240
464+
465+#define REG_DSI_7nm_PHY_PLL_VCO_CONFIG_2 0x00000244
466+
467+#define REG_DSI_7nm_PHY_PLL_CLOCK_INVERTERS_1 0x00000248
468+
469+#define REG_DSI_7nm_PHY_PLL_CLOCK_INVERTERS_2 0x0000024c
470+
471+#define REG_DSI_7nm_PHY_PLL_CMODE_1 0x00000250
472+
473+#define REG_DSI_7nm_PHY_PLL_CMODE_2 0x00000254
474+
475+#define REG_DSI_7nm_PHY_PLL_ANALOG_CONTROLS_FIVE_1 0x00000258
476+
477+#define REG_DSI_7nm_PHY_PLL_ANALOG_CONTROLS_FIVE_2 0x0000025c
478+
479+#define REG_DSI_7nm_PHY_PLL_PERF_OPTIMIZE 0x00000260
480+
481+
482+#endif /* DSI_PHY_7NM_XML */
drivers/gpu/drm/msm/dsi/mmss_cc.xml.h+21−13
@@ -8,19 +8,27 @@ http://github.com/freedreno/envytools/ · 7 unmodified lines
88 git clone https://github.com/freedreno/envytools.git
99
1010 The rules-ng-ng source files this header was generated from are:
11−- /home/robclark/src/envytools/rnndb/msm.xml ( 676 bytes, from 2020-07-23 21:58:14)
12−- /home/robclark/src/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2020-07-23 21:58:14)
13−- /home/robclark/src/envytools/rnndb/mdp/mdp4.xml ( 20915 bytes, from 2020-07-23 21:58:14)
14−- /home/robclark/src/envytools/rnndb/mdp/mdp_common.xml ( 2849 bytes, from 2020-07-23 21:58:14)
15−- /home/robclark/src/envytools/rnndb/mdp/mdp5.xml ( 37411 bytes, from 2020-07-23 21:58:14)
16−- /home/robclark/src/envytools/rnndb/dsi/dsi.xml ( 42301 bytes, from 2020-07-23 21:58:14)
17−- /home/robclark/src/envytools/rnndb/dsi/sfpb.xml ( 602 bytes, from 2020-07-23 21:58:14)
18−- /home/robclark/src/envytools/rnndb/dsi/mmss_cc.xml ( 1686 bytes, from 2020-07-23 21:58:14)
19−- /home/robclark/src/envytools/rnndb/hdmi/qfprom.xml ( 600 bytes, from 2020-07-23 21:58:14)
20−- /home/robclark/src/envytools/rnndb/hdmi/hdmi.xml ( 41874 bytes, from 2020-07-23 21:58:14)
21−- /home/robclark/src/envytools/rnndb/edp/edp.xml ( 10416 bytes, from 2020-07-23 21:58:14)
22−
23−Copyright (C) 2013-2020 by the following authors:
11+- /home/robclark/src/mesa/mesa/src/freedreno/registers/msm.xml ( 981 bytes, from 2021-06-05 21:37:42)
12+- /home/robclark/src/mesa/mesa/src/freedreno/registers/freedreno_copyright.xml ( 1572 bytes, from 2021-02-18 16:45:44)
13+- /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp4.xml ( 20912 bytes, from 2021-02-18 16:45:44)
14+- /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp_common.xml ( 2849 bytes, from 2021-02-18 16:45:44)
15+- /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp5.xml ( 37461 bytes, from 2021-02-18 16:45:44)
16+- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi.xml ( 15291 bytes, from 2021-06-15 22:36:13)
17+- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_v2.xml ( 3236 bytes, from 2021-06-05 21:37:42)
18+- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_28nm_8960.xml ( 4935 bytes, from 2021-05-21 19:18:08)
19+- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_28nm.xml ( 7004 bytes, from 2021-05-21 19:18:08)
20+- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_20nm.xml ( 3712 bytes, from 2021-05-21 19:18:08)
21+- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_14nm.xml ( 5381 bytes, from 2021-05-21 19:18:08)
22+- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_10nm.xml ( 4499 bytes, from 2021-05-21 19:18:08)
23+- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_7nm.xml ( 10953 bytes, from 2021-05-21 19:18:08)
24+- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_5nm.xml ( 10900 bytes, from 2021-05-21 19:18:08)
25+- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/sfpb.xml ( 602 bytes, from 2021-02-18 16:45:44)
26+- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/mmss_cc.xml ( 1686 bytes, from 2021-02-18 16:45:44)
27+- /home/robclark/src/mesa/mesa/src/freedreno/registers/hdmi/qfprom.xml ( 600 bytes, from 2021-02-18 16:45:44)
28+- /home/robclark/src/mesa/mesa/src/freedreno/registers/hdmi/hdmi.xml ( 41874 bytes, from 2021-02-18 16:45:44)
29+- /home/robclark/src/mesa/mesa/src/freedreno/registers/edp/edp.xml ( 10416 bytes, from 2021-02-18 16:45:44)
30+
31+Copyright (C) 2013-2021 by the following authors:
2432 - Rob Clark <robdclark@gmail.com> (robclark)
2533 - Ilia Mirkin <imirkin@alum.mit.edu> (imirkin)
2634
drivers/gpu/drm/msm/dsi/phy/dsi_phy.c+27−4
@@ -658,14 +658,14 @@ static int dsi_phy_driver_probe(struct platform_device *pdev) · 657 unmodified lines
658658 phy->regulator_ldo_mode = of_property_read_bool(dev->of_node,
659659 "qcom,dsi-phy-regulator-ldo-mode");
660660
661− phy->base = msm_ioremap(pdev, "dsi_phy", "DSI_PHY");
661+ phy->base = msm_ioremap_size(pdev, "dsi_phy", "DSI_PHY", &phy->base_size);
662662 if (IS_ERR(phy->base)) {
663663 DRM_DEV_ERROR(dev, "%s: failed to map phy base\n", __func__);
664664 ret = -ENOMEM;
665665 goto fail;
666666 }
667667
668− phy->pll_base = msm_ioremap(pdev, "dsi_pll", "DSI_PLL");
668+ phy->pll_base = msm_ioremap_size(pdev, "dsi_pll", "DSI_PLL", &phy->pll_size);
669669 if (IS_ERR(phy->pll_base)) {
670670 DRM_DEV_ERROR(&pdev->dev, "%s: failed to map pll base\n", __func__);
671671 ret = -ENOMEM;
@@ -673,7 +673,7 @@ static int dsi_phy_driver_probe(struct platform_device *pdev) · 1 unmodified line
673673 }
674674
675675 if (phy->cfg->has_phy_lane) {
676− phy->lane_base = msm_ioremap(pdev, "dsi_phy_lane", "DSI_PHY_LANE");
676+ phy->lane_base = msm_ioremap_size(pdev, "dsi_phy_lane", "DSI_PHY_LANE", &phy->lane_size);
677677 if (IS_ERR(phy->lane_base)) {
678678 DRM_DEV_ERROR(&pdev->dev, "%s: failed to map phy lane base\n", __func__);
679679 ret = -ENOMEM;
@@ -682,7 +682,7 @@ static int dsi_phy_driver_probe(struct platform_device *pdev) · 2 unmodified lines
682682 }
683683
684684 if (phy->cfg->has_phy_regulator) {
685− phy->reg_base = msm_ioremap(pdev, "dsi_phy_regulator", "DSI_PHY_REG");
685+ phy->reg_base = msm_ioremap_size(pdev, "dsi_phy_regulator", "DSI_PHY_REG", &phy->reg_size);
686686 if (IS_ERR(phy->reg_base)) {
687687 DRM_DEV_ERROR(&pdev->dev, "%s: failed to map phy regulator base\n", __func__);
688688 ret = -ENOMEM;
@@ -868,3 +868,26 @@ int msm_dsi_phy_pll_restore_state(struct msm_dsi_phy *phy) · 179 unmodified lines
868868
869869 return 0;
870870 }
871+
872+void msm_dsi_phy_snapshot(struct msm_disp_state *disp_state, struct msm_dsi_phy *phy)
873+{
874+ msm_disp_snapshot_add_block(disp_state,
875+ phy->base_size, phy->base,
876+ "dsi%d_phy", phy->id);
877+
878+ /* Do not try accessing PLL registers if it is switched off */
879+ if (phy->pll_on)
880+ msm_disp_snapshot_add_block(disp_state,
881+ phy->pll_size, phy->pll_base,
882+ "dsi%d_pll", phy->id);
883+
884+ if (phy->lane_base)
885+ msm_disp_snapshot_add_block(disp_state,
886+ phy->lane_size, phy->lane_base,
887+ "dsi%d_lane", phy->id);
888+
889+ if (phy->reg_base)
890+ msm_disp_snapshot_add_block(disp_state,
891+ phy->reg_size, phy->reg_base,
892+ "dsi%d_reg", phy->id);
893+}
drivers/gpu/drm/msm/dsi/phy/dsi_phy.h+4−0
@@ -85,6 +85,10 @@ struct msm_dsi_phy { · 84 unmodified lines
8585 void __iomem *pll_base;
8686 void __iomem *reg_base;
8787 void __iomem *lane_base;
88+ phys_addr_t base_size;
89+ phys_addr_t pll_size;
90+ phys_addr_t reg_size;
91+ phys_addr_t lane_size;
8892 int id;
8993
9094 struct clk *ahb_clk;
drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c+1−0
@@ -9,6 +9,7 @@ · 8 unmodified lines
99
1010 #include "dsi_phy.h"
1111 #include "dsi.xml.h"
12+#include "dsi_phy_10nm.xml.h"
1213
1314 /*
1415 * DSI PLL 10nm - clock diagram (eg: DSI0):
drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c+1−0
@@ -9,6 +9,7 @@ · 8 unmodified lines
99
1010 #include "dsi_phy.h"
1111 #include "dsi.xml.h"
12+#include "dsi_phy_14nm.xml.h"
1213
1314 #define PHY_14NM_CKLN_IDX 4
1415
drivers/gpu/drm/msm/dsi/phy/dsi_phy_20nm.c+1−0
@@ -5,6 +5,7 @@ · 4 unmodified lines
55
66 #include "dsi_phy.h"
77 #include "dsi.xml.h"
8+#include "dsi_phy_20nm.xml.h"
89
910 static void dsi_20nm_dphy_set_timing(struct msm_dsi_phy *phy,
1011 struct msm_dsi_dphy_timing *timing)
drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c+1−0
@@ -8,6 +8,7 @@ · 7 unmodified lines
88
99 #include "dsi_phy.h"
1010 #include "dsi.xml.h"
11+#include "dsi_phy_28nm.xml.h"
1112
1213 /*
1314 * DSI PLL 28nm - clock diagram (eg: DSI0):
drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c+1−0
@@ -8,6 +8,7 @@ · 7 unmodified lines
88
99 #include "dsi_phy.h"
1010 #include "dsi.xml.h"
11+#include "dsi_phy_28nm_8960.xml.h"
1112
1213 /*
1314 * DSI PLL 28nm (8960/A family) - clock diagram (eg: DSI1):
drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c+6−1
@@ -9,6 +9,7 @@ · 8 unmodified lines
99
1010 #include "dsi_phy.h"
1111 #include "dsi.xml.h"
12+#include "dsi_phy_7nm.xml.h"
1213
1314 /*
1415 * DSI PLL 7nm - clock diagram (eg: DSI0): TODO: updated CPHY diagram
@@ -973,7 +974,11 @@ const struct msm_dsi_phy_cfg dsi_phy_7nm_cfgs = { · 958 unmodified lines
973974 .restore_pll_state = dsi_7nm_pll_restore_state,
974975 },
975976 .min_pll_rate = 600000000UL,
976− .max_pll_rate = (5000000000ULL < ULONG_MAX) ? 5000000000ULL : ULONG_MAX,
977+#ifdef CONFIG_64BIT
978+ .max_pll_rate = 5000000000UL,
979+#else
980+ .max_pll_rate = ULONG_MAX,
981+#endif
977982 .io_start = { 0xae94400, 0xae96400 },
978983 .num_dsi_phy = 2,
979984 .quirks = DSI_PHY_7NM_QUIRK_V4_1,
drivers/gpu/drm/msm/dsi/sfpb.xml.h+21−13
@@ -8,19 +8,27 @@ http://github.com/freedreno/envytools/ · 7 unmodified lines
88 git clone https://github.com/freedreno/envytools.git
99
1010 The rules-ng-ng source files this header was generated from are:
11−- /home/robclark/src/envytools/rnndb/msm.xml ( 676 bytes, from 2020-07-23 21:58:14)
12−- /home/robclark/src/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2020-07-23 21:58:14)
13−- /home/robclark/src/envytools/rnndb/mdp/mdp4.xml ( 20915 bytes, from 2020-07-23 21:58:14)
14−- /home/robclark/src/envytools/rnndb/mdp/mdp_common.xml ( 2849 bytes, from 2020-07-23 21:58:14)
15−- /home/robclark/src/envytools/rnndb/mdp/mdp5.xml ( 37411 bytes, from 2020-07-23 21:58:14)
16−- /home/robclark/src/envytools/rnndb/dsi/dsi.xml ( 42301 bytes, from 2020-07-23 21:58:14)
17−- /home/robclark/src/envytools/rnndb/dsi/sfpb.xml ( 602 bytes, from 2020-07-23 21:58:14)
18−- /home/robclark/src/envytools/rnndb/dsi/mmss_cc.xml ( 1686 bytes, from 2020-07-23 21:58:14)
19−- /home/robclark/src/envytools/rnndb/hdmi/qfprom.xml ( 600 bytes, from 2020-07-23 21:58:14)
20−- /home/robclark/src/envytools/rnndb/hdmi/hdmi.xml ( 41874 bytes, from 2020-07-23 21:58:14)
21−- /home/robclark/src/envytools/rnndb/edp/edp.xml ( 10416 bytes, from 2020-07-23 21:58:14)
22−
23−Copyright (C) 2013-2020 by the following authors:
11+- /home/robclark/src/mesa/mesa/src/freedreno/registers/msm.xml ( 981 bytes, from 2021-06-05 21:37:42)
12+- /home/robclark/src/mesa/mesa/src/freedreno/registers/freedreno_copyright.xml ( 1572 bytes, from 2021-02-18 16:45:44)
13+- /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp4.xml ( 20912 bytes, from 2021-02-18 16:45:44)
14+- /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp_common.xml ( 2849 bytes, from 2021-02-18 16:45:44)
15+- /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp5.xml ( 37461 bytes, from 2021-02-18 16:45:44)
16+- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi.xml ( 15291 bytes, from 2021-06-15 22:36:13)
17+- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_v2.xml ( 3236 bytes, from 2021-06-05 21:37:42)
18+- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_28nm_8960.xml ( 4935 bytes, from 2021-05-21 19:18:08)
19+- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_28nm.xml ( 7004 bytes, from 2021-05-21 19:18:08)
20+- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_20nm.xml ( 3712 bytes, from 2021-05-21 19:18:08)
21+- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_14nm.xml ( 5381 bytes, from 2021-05-21 19:18:08)
22+- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_10nm.xml ( 4499 bytes, from 2021-05-21 19:18:08)
23+- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_7nm.xml ( 10953 bytes, from 2021-05-21 19:18:08)
24+- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_5nm.xml ( 10900 bytes, from 2021-05-21 19:18:08)
25+- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/sfpb.xml ( 602 bytes, from 2021-02-18 16:45:44)
26+- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/mmss_cc.xml ( 1686 bytes, from 2021-02-18 16:45:44)
27+- /home/robclark/src/mesa/mesa/src/freedreno/registers/hdmi/qfprom.xml ( 600 bytes, from 2021-02-18 16:45:44)
28+- /home/robclark/src/mesa/mesa/src/freedreno/registers/hdmi/hdmi.xml ( 41874 bytes, from 2021-02-18 16:45:44)
29+- /home/robclark/src/mesa/mesa/src/freedreno/registers/edp/edp.xml ( 10416 bytes, from 2021-02-18 16:45:44)
30+
31+Copyright (C) 2013-2021 by the following authors:
2432 - Rob Clark <robdclark@gmail.com> (robclark)
2533 - Ilia Mirkin <imirkin@alum.mit.edu> (imirkin)
2634
drivers/gpu/drm/msm/edp/edp.xml.h+21−13
@@ -8,19 +8,27 @@ http://github.com/freedreno/envytools/ · 7 unmodified lines
88 git clone https://github.com/freedreno/envytools.git
99
1010 The rules-ng-ng source files this header was generated from are:
11−- /home/robclark/src/envytools/rnndb/msm.xml ( 676 bytes, from 2020-07-23 21:58:14)
12−- /home/robclark/src/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2020-07-23 21:58:14)
13−- /home/robclark/src/envytools/rnndb/mdp/mdp4.xml ( 20915 bytes, from 2020-07-23 21:58:14)
14−- /home/robclark/src/envytools/rnndb/mdp/mdp_common.xml ( 2849 bytes, from 2020-07-23 21:58:14)
15−- /home/robclark/src/envytools/rnndb/mdp/mdp5.xml ( 37411 bytes, from 2020-07-23 21:58:14)
16−- /home/robclark/src/envytools/rnndb/dsi/dsi.xml ( 42301 bytes, from 2020-07-23 21:58:14)
17−- /home/robclark/src/envytools/rnndb/dsi/sfpb.xml ( 602 bytes, from 2020-07-23 21:58:14)
18−- /home/robclark/src/envytools/rnndb/dsi/mmss_cc.xml ( 1686 bytes, from 2020-07-23 21:58:14)
19−- /home/robclark/src/envytools/rnndb/hdmi/qfprom.xml ( 600 bytes, from 2020-07-23 21:58:14)
20−- /home/robclark/src/envytools/rnndb/hdmi/hdmi.xml ( 41874 bytes, from 2020-07-23 21:58:14)
21−- /home/robclark/src/envytools/rnndb/edp/edp.xml ( 10416 bytes, from 2020-07-23 21:58:14)
22−
23−Copyright (C) 2013-2020 by the following authors:
11+- /home/robclark/src/mesa/mesa/src/freedreno/registers/msm.xml ( 981 bytes, from 2021-06-05 21:37:42)
12+- /home/robclark/src/mesa/mesa/src/freedreno/registers/freedreno_copyright.xml ( 1572 bytes, from 2021-02-18 16:45:44)
13+- /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp4.xml ( 20912 bytes, from 2021-02-18 16:45:44)
14+- /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp_common.xml ( 2849 bytes, from 2021-02-18 16:45:44)
15+- /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp5.xml ( 37461 bytes, from 2021-02-18 16:45:44)
16+- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi.xml ( 15291 bytes, from 2021-06-15 22:36:13)
17+- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_v2.xml ( 3236 bytes, from 2021-06-05 21:37:42)
18+- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_28nm_8960.xml ( 4935 bytes, from 2021-05-21 19:18:08)
19+- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_28nm.xml ( 7004 bytes, from 2021-05-21 19:18:08)
20+- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_20nm.xml ( 3712 bytes, from 2021-05-21 19:18:08)
21+- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_14nm.xml ( 5381 bytes, from 2021-05-21 19:18:08)
22+- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_10nm.xml ( 4499 bytes, from 2021-05-21 19:18:08)
23+- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_7nm.xml ( 10953 bytes, from 2021-05-21 19:18:08)
24+- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_5nm.xml ( 10900 bytes, from 2021-05-21 19:18:08)
25+- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/sfpb.xml ( 602 bytes, from 2021-02-18 16:45:44)
26+- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/mmss_cc.xml ( 1686 bytes, from 2021-02-18 16:45:44)
27+- /home/robclark/src/mesa/mesa/src/freedreno/registers/hdmi/qfprom.xml ( 600 bytes, from 2021-02-18 16:45:44)
28+- /home/robclark/src/mesa/mesa/src/freedreno/registers/hdmi/hdmi.xml ( 41874 bytes, from 2021-02-18 16:45:44)
29+- /home/robclark/src/mesa/mesa/src/freedreno/registers/edp/edp.xml ( 10416 bytes, from 2021-02-18 16:45:44)
30+
31+Copyright (C) 2013-2021 by the following authors:
2432 - Rob Clark <robdclark@gmail.com> (robclark)
2533 - Ilia Mirkin <imirkin@alum.mit.edu> (imirkin)
2634
drivers/gpu/drm/msm/hdmi/hdmi.xml.h+21−13
@@ -8,19 +8,27 @@ http://github.com/freedreno/envytools/ · 7 unmodified lines
88 git clone https://github.com/freedreno/envytools.git
99
1010 The rules-ng-ng source files this header was generated from are:
11−- /home/robclark/src/envytools/rnndb/msm.xml ( 676 bytes, from 2020-07-23 21:58:14)
12−- /home/robclark/src/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2020-07-23 21:58:14)
13−- /home/robclark/src/envytools/rnndb/mdp/mdp4.xml ( 20915 bytes, from 2020-07-23 21:58:14)
14−- /home/robclark/src/envytools/rnndb/mdp/mdp_common.xml ( 2849 bytes, from 2020-07-23 21:58:14)
15−- /home/robclark/src/envytools/rnndb/mdp/mdp5.xml ( 37411 bytes, from 2020-07-23 21:58:14)
16−- /home/robclark/src/envytools/rnndb/dsi/dsi.xml ( 42301 bytes, from 2020-07-23 21:58:14)
17−- /home/robclark/src/envytools/rnndb/dsi/sfpb.xml ( 602 bytes, from 2020-07-23 21:58:14)
18−- /home/robclark/src/envytools/rnndb/dsi/mmss_cc.xml ( 1686 bytes, from 2020-07-23 21:58:14)
19−- /home/robclark/src/envytools/rnndb/hdmi/qfprom.xml ( 600 bytes, from 2020-07-23 21:58:14)
20−- /home/robclark/src/envytools/rnndb/hdmi/hdmi.xml ( 41874 bytes, from 2020-07-23 21:58:14)
21−- /home/robclark/src/envytools/rnndb/edp/edp.xml ( 10416 bytes, from 2020-07-23 21:58:14)
22−
23−Copyright (C) 2013-2020 by the following authors:
11+- /home/robclark/src/mesa/mesa/src/freedreno/registers/msm.xml ( 981 bytes, from 2021-06-05 21:37:42)
12+- /home/robclark/src/mesa/mesa/src/freedreno/registers/freedreno_copyright.xml ( 1572 bytes, from 2021-02-18 16:45:44)
13+- /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp4.xml ( 20912 bytes, from 2021-02-18 16:45:44)
14+- /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp_common.xml ( 2849 bytes, from 2021-02-18 16:45:44)
15+- /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp5.xml ( 37461 bytes, from 2021-02-18 16:45:44)
16+- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi.xml ( 15291 bytes, from 2021-06-15 22:36:13)
17+- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_v2.xml ( 3236 bytes, from 2021-06-05 21:37:42)
18+- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_28nm_8960.xml ( 4935 bytes, from 2021-05-21 19:18:08)
19+- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_28nm.xml ( 7004 bytes, from 2021-05-21 19:18:08)
20+- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_20nm.xml ( 3712 bytes, from 2021-05-21 19:18:08)
21+- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_14nm.xml ( 5381 bytes, from 2021-05-21 19:18:08)
22+- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_10nm.xml ( 4499 bytes, from 2021-05-21 19:18:08)
23+- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_7nm.xml ( 10953 bytes, from 2021-05-21 19:18:08)
24+- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_5nm.xml ( 10900 bytes, from 2021-05-21 19:18:08)
25+- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/sfpb.xml ( 602 bytes, from 2021-02-18 16:45:44)
26+- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/mmss_cc.xml ( 1686 bytes, from 2021-02-18 16:45:44)
27+- /home/robclark/src/mesa/mesa/src/freedreno/registers/hdmi/qfprom.xml ( 600 bytes, from 2021-02-18 16:45:44)
28+- /home/robclark/src/mesa/mesa/src/freedreno/registers/hdmi/hdmi.xml ( 41874 bytes, from 2021-02-18 16:45:44)
29+- /home/robclark/src/mesa/mesa/src/freedreno/registers/edp/edp.xml ( 10416 bytes, from 2021-02-18 16:45:44)
30+
31+Copyright (C) 2013-2021 by the following authors:
2432 - Rob Clark <robdclark@gmail.com> (robclark)
2533 - Ilia Mirkin <imirkin@alum.mit.edu> (imirkin)
2634
drivers/gpu/drm/msm/hdmi/qfprom.xml.h+21−13
@@ -8,19 +8,27 @@ http://github.com/freedreno/envytools/ · 7 unmodified lines
88 git clone https://github.com/freedreno/envytools.git
99
1010 The rules-ng-ng source files this header was generated from are:
11−- /home/robclark/src/envytools/rnndb/msm.xml ( 676 bytes, from 2020-07-23 21:58:14)
12−- /home/robclark/src/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2020-07-23 21:58:14)
13−- /home/robclark/src/envytools/rnndb/mdp/mdp4.xml ( 20915 bytes, from 2020-07-23 21:58:14)
14−- /home/robclark/src/envytools/rnndb/mdp/mdp_common.xml ( 2849 bytes, from 2020-07-23 21:58:14)
15−- /home/robclark/src/envytools/rnndb/mdp/mdp5.xml ( 37411 bytes, from 2020-07-23 21:58:14)
16−- /home/robclark/src/envytools/rnndb/dsi/dsi.xml ( 42301 bytes, from 2020-07-23 21:58:14)
17−- /home/robclark/src/envytools/rnndb/dsi/sfpb.xml ( 602 bytes, from 2020-07-23 21:58:14)
18−- /home/robclark/src/envytools/rnndb/dsi/mmss_cc.xml ( 1686 bytes, from 2020-07-23 21:58:14)
19−- /home/robclark/src/envytools/rnndb/hdmi/qfprom.xml ( 600 bytes, from 2020-07-23 21:58:14)
20−- /home/robclark/src/envytools/rnndb/hdmi/hdmi.xml ( 41874 bytes, from 2020-07-23 21:58:14)
21−- /home/robclark/src/envytools/rnndb/edp/edp.xml ( 10416 bytes, from 2020-07-23 21:58:14)
22−
23−Copyright (C) 2013-2020 by the following authors:
11+- /home/robclark/src/mesa/mesa/src/freedreno/registers/msm.xml ( 981 bytes, from 2021-06-05 21:37:42)
12+- /home/robclark/src/mesa/mesa/src/freedreno/registers/freedreno_copyright.xml ( 1572 bytes, from 2021-02-18 16:45:44)
13+- /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp4.xml ( 20912 bytes, from 2021-02-18 16:45:44)
14+- /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp_common.xml ( 2849 bytes, from 2021-02-18 16:45:44)
15+- /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp5.xml ( 37461 bytes, from 2021-02-18 16:45:44)
16+- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi.xml ( 15291 bytes, from 2021-06-15 22:36:13)
17+- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_v2.xml ( 3236 bytes, from 2021-06-05 21:37:42)
18+- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_28nm_8960.xml ( 4935 bytes, from 2021-05-21 19:18:08)
19+- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_28nm.xml ( 7004 bytes, from 2021-05-21 19:18:08)
20+- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_20nm.xml ( 3712 bytes, from 2021-05-21 19:18:08)
21+- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_14nm.xml ( 5381 bytes, from 2021-05-21 19:18:08)
22+- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_10nm.xml ( 4499 bytes, from 2021-05-21 19:18:08)
23+- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_7nm.xml ( 10953 bytes, from 2021-05-21 19:18:08)
24+- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_5nm.xml ( 10900 bytes, from 2021-05-21 19:18:08)
25+- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/sfpb.xml ( 602 bytes, from 2021-02-18 16:45:44)
26+- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/mmss_cc.xml ( 1686 bytes, from 2021-02-18 16:45:44)
27+- /home/robclark/src/mesa/mesa/src/freedreno/registers/hdmi/qfprom.xml ( 600 bytes, from 2021-02-18 16:45:44)
28+- /home/robclark/src/mesa/mesa/src/freedreno/registers/hdmi/hdmi.xml ( 41874 bytes, from 2021-02-18 16:45:44)
29+- /home/robclark/src/mesa/mesa/src/freedreno/registers/edp/edp.xml ( 10416 bytes, from 2021-02-18 16:45:44)
30+
31+Copyright (C) 2013-2021 by the following authors:
2432 - Rob Clark <robdclark@gmail.com> (robclark)
2533 - Ilia Mirkin <imirkin@alum.mit.edu> (imirkin)
2634
drivers/gpu/drm/msm/msm_debugfs.c+31−0
@@ -108,6 +108,31 @@ static const struct file_operations msm_gpu_fops = { · 107 unmodified lines
108108 .release = msm_gpu_release,
109109 };
110110
111+static unsigned long last_shrink_freed;
112+
113+static int
114+shrink_get(void *data, u64 *val)
115+{
116+ *val = last_shrink_freed;
117+
118+ return 0;
119+}
120+
121+static int
122+shrink_set(void *data, u64 val)
123+{
124+ struct drm_device *dev = data;
125+
126+ last_shrink_freed = msm_gem_shrinker_shrink(dev, val);
127+
128+ return 0;
129+}
130+
131+DEFINE_SIMPLE_ATTRIBUTE(shrink_fops,
132+ shrink_get, shrink_set,
133+ "0x%08llx\n");
134+
135+
111136 static int msm_gem_show(struct drm_device *dev, struct seq_file *m)
112137 {
113138 struct msm_drm_private *priv = dev->dev_private;
@@ -226,6 +251,12 @@ void msm_debugfs_init(struct drm_minor *minor) · 112 unmodified lines
226251 debugfs_create_file("gpu", S_IRUSR, minor->debugfs_root,
227252 dev, &msm_gpu_fops);
228253
254+ debugfs_create_u32("hangcheck_period_ms", 0600, minor->debugfs_root,
255+ &priv->hangcheck_period);
256+
257+ debugfs_create_file("shrink", S_IRWXU, minor->debugfs_root,
258+ dev, &shrink_fops);
259+
229260 if (priv->kms && priv->kms->funcs->debugfs_init)
230261 priv->kms->funcs->debugfs_init(priv->kms, minor);
231262 }
drivers/gpu/drm/msm/msm_drv.c+26−7
@@ -1,6 +1,6 @@
11 // SPDX-License-Identifier: GPL-2.0-only
22 /*
3− * Copyright (c) 2016-2018, The Linux Foundation. All rights reserved.
3+ * Copyright (c) 2016-2018, 2020-2021 The Linux Foundation. All rights reserved.
44 * Copyright (C) 2013 Red Hat
55 * Author: Rob Clark <robdclark@gmail.com>
66 */
@@ -19,6 +19,7 @@ · 12 unmodified lines
1919 #include <drm/drm_of.h>
2020 #include <drm/drm_vblank.h>
2121
22+#include "disp/msm_disp_snapshot.h"
2223 #include "msm_drv.h"
2324 #include "msm_debugfs.h"
2425 #include "msm_fence.h"
@@ -40,9 +41,10 @@ · 15 unmodified lines
4041 * - 1.5.0 - Add SUBMITQUERY_QUERY ioctl
4142 * - 1.6.0 - Syncobj support
4243 * - 1.7.0 - Add MSM_PARAM_SUSPENDS to access suspend count
44+ * - 1.8.0 - Add MSM_BO_CACHED_COHERENT for supported GPUs (a6xx)
4345 */
4446 #define MSM_VERSION_MAJOR 1
45−#define MSM_VERSION_MINOR 7
47+#define MSM_VERSION_MINOR 8
4648 #define MSM_VERSION_PATCHLEVEL 0
4749
4850 static const struct drm_mode_config_funcs mode_config_funcs = {
@@ -123,7 +125,7 @@ struct clk *msm_clk_get(struct platform_device *pdev, const char *name) · 74 unmodified lines
123125 }
124126
125127 static void __iomem *_msm_ioremap(struct platform_device *pdev, const char *name,
126− const char *dbgname, bool quiet)
128+ const char *dbgname, bool quiet, phys_addr_t *psize)
127129 {
128130 struct resource *res;
129131 unsigned long size;
@@ -152,19 +154,28 @@ static void __iomem *_msm_ioremap(struct platform_device *pdev, const char *name · 22 unmodified lines
152154 if (reglog)
153155 printk(KERN_DEBUG "IO:region %s %p %08lx\n", dbgname, ptr, size);
154156
157+ if (psize)
158+ *psize = size;
159+
155160 return ptr;
156161 }
157162
158163 void __iomem *msm_ioremap(struct platform_device *pdev, const char *name,
159164 const char *dbgname)
160165 {
161− return _msm_ioremap(pdev, name, dbgname, false);
166+ return _msm_ioremap(pdev, name, dbgname, false, NULL);
162167 }
163168
164169 void __iomem *msm_ioremap_quiet(struct platform_device *pdev, const char *name,
165170 const char *dbgname)
166171 {
167− return _msm_ioremap(pdev, name, dbgname, true);
172+ return _msm_ioremap(pdev, name, dbgname, true, NULL);
173+}
174+
175+void __iomem *msm_ioremap_size(struct platform_device *pdev, const char *name,
176+ const char *dbgname, phys_addr_t *psize)
177+{
178+ return _msm_ioremap(pdev, name, dbgname, false, psize);
168179 }
169180
170181 void msm_writel(u32 data, void __iomem *addr)
@@ -278,6 +289,8 @@ static int msm_drm_uninit(struct device *dev) · 107 unmodified lines
278289 msm_fbdev_free(ddev);
279290 #endif
280291
292+ msm_disp_snapshot_destroy(ddev);
293+
281294 drm_mode_config_cleanup(ddev);
282295
283296 pm_runtime_get_sync(dev);
@@ -446,6 +459,7 @@ static int msm_drm_init(struct device *dev, const struct drm_driver *drv) · 162 unmodified lines
446459 mdss = priv->mdss;
447460
448461 priv->wq = alloc_ordered_workqueue("msm", 0);
462+ priv->hangcheck_period = DRM_MSM_HANGCHECK_DEFAULT_PERIOD;
449463
450464 INIT_LIST_HEAD(&priv->objects);
451465 mutex_init(&priv->obj_lock);
@@ -523,6 +537,7 @@ static int msm_drm_init(struct device *dev, const struct drm_driver *drv) · 71 unmodified lines
523537 priv->event_thread[i].worker = kthread_create_worker(0,
524538 "crtc_event:%d", priv->event_thread[i].crtc_id);
525539 if (IS_ERR(priv->event_thread[i].worker)) {
540+ ret = PTR_ERR(priv->event_thread[i].worker);
526541 DRM_DEV_ERROR(dev, "failed to create crtc_event kthread\n");
527542 goto err_msm_uninit;
528543 }
@@ -550,6 +565,10 @@ static int msm_drm_init(struct device *dev, const struct drm_driver *drv) · 21 unmodified lines
550565 if (ret)
551566 goto err_msm_uninit;
552567
568+ ret = msm_disp_snapshot_init(ddev);
569+ if (ret)
570+ DRM_DEV_ERROR(dev, "msm_disp_snapshot_init failed ret = %d\n", ret);
571+
553572 drm_mode_config_reset(ddev);
554573
555574 #ifdef CONFIG_DRM_FBDEV_EMULATION
@@ -688,7 +707,7 @@ int msm_crtc_enable_vblank(struct drm_crtc *crtc) · 132 unmodified lines
688707 struct msm_kms *kms = priv->kms;
689708 if (!kms)
690709 return -ENXIO;
691− DBG("dev=%p, crtc=%u", dev, pipe);
710+ drm_dbg_vbl(dev, "crtc=%u", pipe);
692711 return vblank_ctrl_queue_work(priv, pipe, true);
693712 }
694713
@@ -700,7 +719,7 @@ void msm_crtc_disable_vblank(struct drm_crtc *crtc) · 5 unmodified lines
700719 struct msm_kms *kms = priv->kms;
701720 if (!kms)
702721 return;
703− DBG("dev=%p, crtc=%u", dev, pipe);
722+ drm_dbg_vbl(dev, "crtc=%u", pipe);
704723 vblank_ctrl_queue_work(priv, pipe, false);
705724 }
706725
drivers/gpu/drm/msm/msm_drv.h+23−1
@@ -43,6 +43,7 @@ struct msm_gem_submit; · 42 unmodified lines
4343 struct msm_fence_context;
4444 struct msm_gem_address_space;
4545 struct msm_gem_vma;
46+struct msm_disp_state;
4647
4748 #define MAX_CRTCS 8
4849 #define MAX_PLANES 20
@@ -167,6 +168,7 @@ struct msm_drm_private { · 118 unmodified lines
167168 struct msm_file_private *lastctx;
168169 /* gpu is only set on open(), but we need this info earlier */
169170 bool is_a2xx;
171+ bool has_cached_coherent;
170172
171173 struct drm_fb_helper *fbdev;
172174
@@ -242,6 +244,9 @@ struct msm_drm_private { · 69 unmodified lines
242244 struct shrinker shrinker;
243245
244246 struct drm_atomic_state *pm_state;
247+
248+ /* For hang detection, in ms */
249+ unsigned int hangcheck_period;
245250 };
246251
247252 struct msm_format {
@@ -294,6 +299,10 @@ bool msm_use_mmu(struct drm_device *dev); · 46 unmodified lines
294299 int msm_ioctl_gem_submit(struct drm_device *dev, void *data,
295300 struct drm_file *file);
296301
302+#ifdef CONFIG_DEBUG_FS
303+unsigned long msm_gem_shrinker_shrink(struct drm_device *dev, unsigned long nr_to_scan);
304+#endif
305+
297306 void msm_gem_shrinker_init(struct drm_device *dev);
298307 void msm_gem_shrinker_cleanup(struct drm_device *dev);
299308
@@ -340,6 +349,8 @@ void __init msm_dsi_register(void); · 40 unmodified lines
340349 void __exit msm_dsi_unregister(void);
341350 int msm_dsi_modeset_init(struct msm_dsi *msm_dsi, struct drm_device *dev,
342351 struct drm_encoder *encoder);
352+void msm_dsi_snapshot(struct msm_disp_state *disp_state, struct msm_dsi *msm_dsi);
353+
343354 #else
344355 static inline void __init msm_dsi_register(void)
345356 {
@@ -353,6 +364,10 @@ static inline int msm_dsi_modeset_init(struct msm_dsi *msm_dsi, · 7 unmodified lines
353364 {
354365 return -EINVAL;
355366 }
367+static inline void msm_dsi_snapshot(struct msm_disp_state *disp_state, struct msm_dsi *msm_dsi)
368+{
369+}
370+
356371 #endif
357372
358373 #ifdef CONFIG_DRM_MSM_DP
@@ -367,6 +382,7 @@ void msm_dp_display_mode_set(struct msm_dp *dp, struct drm_encoder *encoder, · 8 unmodified lines
367382 struct drm_display_mode *mode,
368383 struct drm_display_mode *adjusted_mode);
369384 void msm_dp_irq_postinstall(struct msm_dp *dp_display);
385+void msm_dp_snapshot(struct msm_disp_state *disp_state, struct msm_dp *dp_display);
370386
371387 void msm_dp_debugfs_init(struct msm_dp *dp_display, struct drm_minor *minor);
372388
@@ -410,6 +426,10 @@ static inline void msm_dp_irq_postinstall(struct msm_dp *dp_display) · 37 unmodified lines
410426 {
411427 }
412428
429+static inline void msm_dp_snapshot(struct msm_disp_state *disp_state, struct msm_dp *dp_display)
430+{
431+}
432+
413433 static inline void msm_dp_debugfs_init(struct msm_dp *dp_display,
414434 struct drm_minor *minor)
415435 {
@@ -448,6 +468,8 @@ struct clk *msm_clk_bulk_get_clock(struct clk_bulk_data *bulk, int count, · 32 unmodified lines
448468 const char *name);
449469 void __iomem *msm_ioremap(struct platform_device *pdev, const char *name,
450470 const char *dbgname);
471+void __iomem *msm_ioremap_size(struct platform_device *pdev, const char *name,
472+ const char *dbgname, phys_addr_t *size);
451473 void __iomem *msm_ioremap_quiet(struct platform_device *pdev, const char *name,
452474 const char *dbgname);
453475 void msm_writel(u32 data, void __iomem *addr);
@@ -502,7 +524,7 @@ static inline int align_pitch(int width, int bpp) · 48 unmodified lines
502524 /* for the generated headers: */
503525 #define INVALID_IDX(idx) ({BUG(); 0;})
504526 #define fui(x) ({BUG(); 0;})
505−#define util_float_to_half(x) ({BUG(); 0;})
527+#define _mesa_float_to_half(x) ({BUG(); 0;})
506528
507529
508530 #define FIELD(val, name) (((val) & name ## __MASK) >> name ## __SHIFT)
drivers/gpu/drm/msm/msm_fb.c+4−4
@@ -61,7 +61,7 @@ int msm_framebuffer_prepare(struct drm_framebuffer *fb, · 60 unmodified lines
6161
6262 for (i = 0; i < n; i++) {
6363 ret = msm_gem_get_and_pin_iova(fb->obj[i], aspace, &iova);
64− DBG("FB[%u]: iova[%d]: %08llx (%d)", fb->base.id, i, iova, ret);
64+ drm_dbg_state(fb->dev, "FB[%u]: iova[%d]: %08llx (%d)", fb->base.id, i, iova, ret);
6565 if (ret)
6666 return ret;
6767 }
@@ -140,8 +140,8 @@ static struct drm_framebuffer *msm_framebuffer_init(struct drm_device *dev, · 72 unmodified lines
140140 const struct msm_format *format;
141141 int ret, i, n;
142142
143− DBG("create framebuffer: dev=%p, mode_cmd=%p (%dx%d@%4.4s)",
144− dev, mode_cmd, mode_cmd->width, mode_cmd->height,
143+ drm_dbg_state(dev, "create framebuffer: mode_cmd=%p (%dx%d@%4.4s)",
144+ mode_cmd, mode_cmd->width, mode_cmd->height,
145145 (char *)&mode_cmd->pixel_format);
146146
147147 n = info->num_planes;
@@ -194,7 +194,7 @@ static struct drm_framebuffer *msm_framebuffer_init(struct drm_device *dev, · 46 unmodified lines
194194 goto fail;
195195 }
196196
197− DBG("create: FB ID: %d (%p)", fb->base.id, fb);
197+ drm_dbg_state(dev, "create: FB ID: %d (%p)", fb->base.id, fb);
198198
199199 return fb;
200200
drivers/gpu/drm/msm/msm_gem.c+19−19
@@ -211,6 +211,13 @@ void msm_gem_put_pages(struct drm_gem_object *obj) · 210 unmodified lines
211211 msm_gem_unlock(obj);
212212 }
213213
214+static pgprot_t msm_gem_pgprot(struct msm_gem_object *msm_obj, pgprot_t prot)
215+{
216+ if (msm_obj->flags & (MSM_BO_WC|MSM_BO_UNCACHED))
217+ return pgprot_writecombine(prot);
218+ return prot;
219+}
220+
214221 int msm_gem_mmap_obj(struct drm_gem_object *obj,
215222 struct vm_area_struct *vma)
216223 {
@@ -218,22 +225,7 @@ int msm_gem_mmap_obj(struct drm_gem_object *obj, · 1 unmodified line
218225
219226 vma->vm_flags &= ~VM_PFNMAP;
220227 vma->vm_flags |= VM_MIXEDMAP;
221−
222− if (msm_obj->flags & MSM_BO_WC) {
223− vma->vm_page_prot = pgprot_writecombine(vm_get_page_prot(vma->vm_flags));
224− } else if (msm_obj->flags & MSM_BO_UNCACHED) {
225− vma->vm_page_prot = pgprot_noncached(vm_get_page_prot(vma->vm_flags));
226− } else {
227− /*
228− * Shunt off cached objs to shmem file so they have their own
229− * address_space (so unmap_mapping_range does what we want,
230− * in particular in the case of mmap'd dmabufs)
231− */
232− vma->vm_pgoff = 0;
233− vma_set_file(vma, obj->filp);
234−
235− vma->vm_page_prot = vm_get_page_prot(vma->vm_flags);
236− }
228+ vma->vm_page_prot = msm_gem_pgprot(msm_obj, vm_get_page_prot(vma->vm_flags));
237229
238230 return 0;
239231 }
@@ -372,7 +364,7 @@ static void del_vma(struct msm_gem_vma *vma) · 132 unmodified lines
372364 kfree(vma);
373365 }
374366
375−/**
367+/*
376368 * If close is true, this also closes the VMA (releasing the allocated
377369 * iova range) in addition to removing the iommu mapping. In the eviction
378370 * case (!close), we keep the iova allocated, but only remove the iommu
@@ -451,6 +443,9 @@ static int msm_gem_pin_iova(struct drm_gem_object *obj, · 72 unmodified lines
451443 if (msm_obj->flags & MSM_BO_MAP_PRIV)
452444 prot |= IOMMU_PRIV;
453445
446+ if (msm_obj->flags & MSM_BO_CACHED_COHERENT)
447+ prot |= IOMMU_CACHE;
448+
454449 GEM_WARN_ON(!msm_gem_is_locked(obj));
455450
456451 if (GEM_WARN_ON(msm_obj->madv != MSM_MADV_WILLNEED))
@@ -653,7 +648,7 @@ static void *get_vaddr(struct drm_gem_object *obj, unsigned madv) · 196 unmodified lines
653648 goto fail;
654649 }
655650 msm_obj->vaddr = vmap(pages, obj->size >> PAGE_SHIFT,
656− VM_MAP, pgprot_writecombine(PAGE_KERNEL));
651+ VM_MAP, msm_gem_pgprot(msm_obj, PAGE_KERNEL));
657652 if (msm_obj->vaddr == NULL) {
658653 ret = -ENOMEM;
659654 goto fail;
@@ -773,7 +768,7 @@ void msm_gem_purge(struct drm_gem_object *obj) · 113 unmodified lines
773768 0, (loff_t)-1);
774769 }
775770
776−/**
771+/*
777772 * Unpin the backing pages and make them available to be swapped out.
778773 */
779774 void msm_gem_evict(struct drm_gem_object *obj)
@@ -1163,6 +1158,7 @@ static int msm_gem_new_impl(struct drm_device *dev, · 383 unmodified lines
11631158 uint32_t size, uint32_t flags,
11641159 struct drm_gem_object **obj)
11651160 {
1161+ struct msm_drm_private *priv = dev->dev_private;
11661162 struct msm_gem_object *msm_obj;
11671163
11681164 switch (flags & MSM_BO_CACHE_MASK) {
@@ -1170,6 +1166,10 @@ static int msm_gem_new_impl(struct drm_device *dev, · 1 unmodified line
11701166 case MSM_BO_CACHED:
11711167 case MSM_BO_WC:
11721168 break;
1169+ case MSM_BO_CACHED_COHERENT:
1170+ if (priv->has_cached_coherent)
1171+ break;
1172+ /* fallthrough */
11731173 default:
11741174 DRM_DEV_ERROR(dev->dev, "invalid cache flag: %x\n",
11751175 (flags & MSM_BO_CACHE_MASK));
drivers/gpu/drm/msm/msm_gem.h+1−0
@@ -328,6 +328,7 @@ struct msm_gem_submit { · 327 unmodified lines
328328 struct dma_fence *fence;
329329 struct msm_gpu_submitqueue *queue;
330330 struct pid *pid; /* submitting process */
331+ bool fault_dumped; /* Limit devcoredump dumping to one per submit */
331332 bool valid; /* true if no cmdstream patching needed */
332333 bool in_rb; /* "sudo" mode, copy cmds into RB */
333334 struct msm_ringbuffer *ring;
drivers/gpu/drm/msm/msm_gem_shrinker.c+18−0
@@ -145,6 +145,24 @@ msm_gem_shrinker_scan(struct shrinker *shrinker, struct shrink_control *sc) · 144 unmodified lines
145145 return (freed > 0) ? freed : SHRINK_STOP;
146146 }
147147
148+#ifdef CONFIG_DEBUG_FS
149+unsigned long
150+msm_gem_shrinker_shrink(struct drm_device *dev, unsigned long nr_to_scan)
151+{
152+ struct msm_drm_private *priv = dev->dev_private;
153+ struct shrink_control sc = {
154+ .nr_to_scan = nr_to_scan,
155+ };
156+ int ret;
157+
158+ fs_reclaim_acquire(GFP_KERNEL);
159+ ret = msm_gem_shrinker_scan(&priv->shrinker, &sc);
160+ fs_reclaim_release(GFP_KERNEL);
161+
162+ return ret;
163+}
164+#endif
165+
148166 /* since we don't know any better, lets bail after a few
149167 * and if necessary the shrinker will be invoked again.
150168 * Seems better than unmapping *everything*
drivers/gpu/drm/msm/msm_gem_submit.c+1−0
@@ -50,6 +50,7 @@ static struct msm_gem_submit *submit_create(struct drm_device *dev, · 49 unmodified lines
5050 submit->cmd = (void *)&submit->bos[nr_bos];
5151 submit->queue = queue;
5252 submit->ring = gpu->rb[queue->prio];
53+ submit->fault_dumped = false;
5354
5455 /* initially, until copy_from_user() and bo lookup succeeds: */
5556 submit->nr_bos = 0;
drivers/gpu/drm/msm/msm_gpu.c+50−1
@@ -387,6 +387,7 @@ static void msm_gpu_crashstate_capture(struct msm_gpu *gpu, · 386 unmodified lines
387387 /* Fill in the additional crash state information */
388388 state->comm = kstrdup(comm, GFP_KERNEL);
389389 state->cmd = kstrdup(cmd, GFP_KERNEL);
390+ state->fault_info = gpu->fault_info;
390391
391392 if (submit) {
392393 int i, nr = 0;
@@ -559,10 +560,57 @@ static void recover_worker(struct kthread_work *work) · 166 unmodified lines
559560 msm_gpu_retire(gpu);
560561 }
561562
563+static void fault_worker(struct kthread_work *work)
564+{
565+ struct msm_gpu *gpu = container_of(work, struct msm_gpu, fault_work);
566+ struct drm_device *dev = gpu->dev;
567+ struct msm_gem_submit *submit;
568+ struct msm_ringbuffer *cur_ring = gpu->funcs->active_ring(gpu);
569+ char *comm = NULL, *cmd = NULL;
570+
571+ mutex_lock(&dev->struct_mutex);
572+
573+ submit = find_submit(cur_ring, cur_ring->memptrs->fence + 1);
574+ if (submit && submit->fault_dumped)
575+ goto resume_smmu;
576+
577+ if (submit) {
578+ struct task_struct *task;
579+
580+ task = get_pid_task(submit->pid, PIDTYPE_PID);
581+ if (task) {
582+ comm = kstrdup(task->comm, GFP_KERNEL);
583+ cmd = kstrdup_quotable_cmdline(task, GFP_KERNEL);
584+ put_task_struct(task);
585+ }
586+
587+ /*
588+ * When we get GPU iova faults, we can get 1000s of them,
589+ * but we really only want to log the first one.
590+ */
591+ submit->fault_dumped = true;
592+ }
593+
594+ /* Record the crash state */
595+ pm_runtime_get_sync(&gpu->pdev->dev);
596+ msm_gpu_crashstate_capture(gpu, submit, comm, cmd);
597+ pm_runtime_put_sync(&gpu->pdev->dev);
598+
599+ kfree(cmd);
600+ kfree(comm);
601+
602+resume_smmu:
603+ memset(&gpu->fault_info, 0, sizeof(gpu->fault_info));
604+ gpu->aspace->mmu->funcs->resume_translation(gpu->aspace->mmu);
605+
606+ mutex_unlock(&dev->struct_mutex);
607+}
608+
562609 static void hangcheck_timer_reset(struct msm_gpu *gpu)
563610 {
611+ struct msm_drm_private *priv = gpu->dev->dev_private;
564612 mod_timer(&gpu->hangcheck_timer,
565− round_jiffies_up(jiffies + DRM_MSM_HANGCHECK_JIFFIES));
613+ round_jiffies_up(jiffies + msecs_to_jiffies(priv->hangcheck_period)));
566614 }
567615
568616 static void hangcheck_handler(struct timer_list *t)
@@ -922,6 +970,7 @@ int msm_gpu_init(struct drm_device *drm, struct platform_device *pdev, · 353 unmodified lines
922970 INIT_LIST_HEAD(&gpu->active_list);
923971 kthread_init_work(&gpu->retire_work, retire_worker);
924972 kthread_init_work(&gpu->recover_work, recover_worker);
973+ kthread_init_work(&gpu->fault_work, fault_worker);
925974
926975 timer_setup(&gpu->hangcheck_timer, hangcheck_handler, 0);
927976
drivers/gpu/drm/msm/msm_gpu.h+18−11
@@ -71,6 +71,15 @@ struct msm_gpu_funcs { · 70 unmodified lines
7171 uint32_t (*get_rptr)(struct msm_gpu *gpu, struct msm_ringbuffer *ring);
7272 };
7373
74+/* Additional state for iommu faults: */
75+struct msm_gpu_fault_info {
76+ u64 ttbr0;
77+ unsigned long iova;
78+ int flags;
79+ const char *type;
80+ const char *block;
81+};
82+
7483 struct msm_gpu {
7584 const char *name;
7685 struct drm_device *dev;
@@ -118,23 +127,19 @@ struct msm_gpu { · 41 unmodified lines
118127 struct clk *ebi1_clk, *core_clk, *rbbmtimer_clk;
119128 uint32_t fast_rate;
120129
121− /* The gfx-mem interconnect path that's used by all GPU types. */
122− struct icc_path *icc_path;
123−
124− /*
125− * Second interconnect path for some A3xx and all A4xx GPUs to the
126− * On Chip MEMory (OCMEM).
127− */
128− struct icc_path *ocmem_icc_path;
129−
130130 /* Hang and Inactivity Detection:
131131 */
132132 #define DRM_MSM_INACTIVE_PERIOD 66 /* in ms (roughly four frames) */
133133
134−#define DRM_MSM_HANGCHECK_PERIOD 500 /* in ms */
135−#define DRM_MSM_HANGCHECK_JIFFIES msecs_to_jiffies(DRM_MSM_HANGCHECK_PERIOD)
134+#define DRM_MSM_HANGCHECK_DEFAULT_PERIOD 500 /* in ms */
136135 struct timer_list hangcheck_timer;
137136
137+ /* Fault info for most recent iova fault: */
138+ struct msm_gpu_fault_info fault_info;
139+
140+ /* work for handling GPU ioval faults: */
141+ struct kthread_work fault_work;
142+
138143 /* work for handling GPU recovery: */
139144 struct kthread_work recover_work;
140145
@@ -242,6 +247,8 @@ struct msm_gpu_state { · 101 unmodified lines
242247 char *comm;
243248 char *cmd;
244249
250+ struct msm_gpu_fault_info fault_info;
251+
245252 int nr_bos;
246253 struct msm_gpu_state_bo *bos;
247254 };
drivers/gpu/drm/msm/msm_gpummu.c+5−0
@@ -68,6 +68,10 @@ static int msm_gpummu_unmap(struct msm_mmu *mmu, uint64_t iova, size_t len) · 67 unmodified lines
6868 return 0;
6969 }
7070
71+static void msm_gpummu_resume_translation(struct msm_mmu *mmu)
72+{
73+}
74+
7175 static void msm_gpummu_destroy(struct msm_mmu *mmu)
7276 {
7377 struct msm_gpummu *gpummu = to_msm_gpummu(mmu);
@@ -83,6 +87,7 @@ static const struct msm_mmu_funcs funcs = { · 9 unmodified lines
8387 .map = msm_gpummu_map,
8488 .unmap = msm_gpummu_unmap,
8589 .destroy = msm_gpummu_destroy,
90+ .resume_translation = msm_gpummu_resume_translation,
8691 };
8792
8893 struct msm_mmu *msm_gpummu_new(struct device *dev, struct msm_gpu *gpu)
drivers/gpu/drm/msm/msm_iommu.c+21−1
@@ -184,6 +184,9 @@ struct msm_mmu *msm_iommu_pagetable_create(struct msm_mmu *parent) · 183 unmodified lines
184184 * the arm-smmu driver as a trigger to set up TTBR0
185185 */
186186 if (atomic_inc_return(&iommu->pagetables) == 1) {
187+ /* Enable stall on iommu fault: */
188+ adreno_smmu->set_stall(adreno_smmu->cookie, true);
189+
187190 ret = adreno_smmu->set_ttbr0_cfg(adreno_smmu->cookie, &ttbr0_cfg);
188191 if (ret) {
189192 free_io_pgtable_ops(pagetable->pgtbl_ops);
@@ -211,12 +214,28 @@ static int msm_fault_handler(struct iommu_domain *domain, struct device *dev, · 21 unmodified lines
211214 unsigned long iova, int flags, void *arg)
212215 {
213216 struct msm_iommu *iommu = arg;
217+ struct adreno_smmu_priv *adreno_smmu = dev_get_drvdata(iommu->base.dev);
218+ struct adreno_smmu_fault_info info, *ptr = NULL;
219+
220+ if (adreno_smmu->get_fault_info) {
221+ adreno_smmu->get_fault_info(adreno_smmu->cookie, &info);
222+ ptr = &info;
223+ }
224+
214225 if (iommu->base.handler)
215− return iommu->base.handler(iommu->base.arg, iova, flags);
226+ return iommu->base.handler(iommu->base.arg, iova, flags, ptr);
227+
216228 pr_warn_ratelimited("*** fault: iova=%16lx, flags=%d\n", iova, flags);
217229 return 0;
218230 }
219231
232+static void msm_iommu_resume_translation(struct msm_mmu *mmu)
233+{
234+ struct adreno_smmu_priv *adreno_smmu = dev_get_drvdata(mmu->dev);
235+
236+ adreno_smmu->resume_translation(adreno_smmu->cookie, true);
237+}
238+
220239 static void msm_iommu_detach(struct msm_mmu *mmu)
221240 {
222241 struct msm_iommu *iommu = to_msm_iommu(mmu);
@@ -264,6 +283,7 @@ static const struct msm_mmu_funcs funcs = { · 41 unmodified lines
264283 .map = msm_iommu_map,
265284 .unmap = msm_iommu_unmap,
266285 .destroy = msm_iommu_destroy,
286+ .resume_translation = msm_iommu_resume_translation,
267287 };
268288
269289 struct msm_mmu *msm_iommu_new(struct device *dev, struct iommu_domain *domain)
drivers/gpu/drm/msm/msm_kms.h+9−0
@@ -122,6 +122,10 @@ struct msm_kms_funcs { · 121 unmodified lines
122122 bool cmd_mode);
123123 /* cleanup: */
124124 void (*destroy)(struct msm_kms *kms);
125+
126+ /* snapshot: */
127+ void (*snapshot)(struct msm_disp_state *disp_state, struct msm_kms *kms);
128+
125129 #ifdef CONFIG_DEBUG_FS
126130 /* debugfs: */
127131 int (*debugfs_init)(struct msm_kms *kms, struct drm_minor *minor);
@@ -152,6 +156,11 @@ struct msm_kms { · 24 unmodified lines
152156 /* mapper-id used to request GEM buffer mapped for scanout: */
153157 struct msm_gem_address_space *aspace;
154158
159+ /* disp snapshot support */
160+ struct kthread_worker *dump_worker;
161+ struct kthread_work dump_work;
162+ struct mutex dump_mutex;
163+
155164 /*
156165 * For async commit, where ->flush_commit() and later happens
157166 * from the crtc's pending_timer close to end of the frame:
drivers/gpu/drm/msm/msm_mmu.h+3−2
@@ -15,6 +15,7 @@ struct msm_mmu_funcs { · 14 unmodified lines
1515 size_t len, int prot);
1616 int (*unmap)(struct msm_mmu *mmu, uint64_t iova, size_t len);
1717 void (*destroy)(struct msm_mmu *mmu);
18+ void (*resume_translation)(struct msm_mmu *mmu);
1819 };
1920
2021 enum msm_mmu_type {
@@ -26,7 +27,7 @@ enum msm_mmu_type { · 5 unmodified lines
2627 struct msm_mmu {
2728 const struct msm_mmu_funcs *funcs;
2829 struct device *dev;
29− int (*handler)(void *arg, unsigned long iova, int flags);
30+ int (*handler)(void *arg, unsigned long iova, int flags, void *data);
3031 void *arg;
3132 enum msm_mmu_type type;
3233 };
@@ -43,7 +44,7 @@ struct msm_mmu *msm_iommu_new(struct device *dev, struct iommu_domain *domain); · 10 unmodified lines
4344 struct msm_mmu *msm_gpummu_new(struct device *dev, struct msm_gpu *gpu);
4445
4546 static inline void msm_mmu_set_fault_handler(struct msm_mmu *mmu, void *arg,
46− int (*handler)(void *arg, unsigned long iova, int flags))
47+ int (*handler)(void *arg, unsigned long iova, int flags, void *data))
4748 {
4849 mmu->arg = arg;
4950 mmu->handler = handler;
drivers/gpu/drm/selftests/test-drm_framebuffer.c+1−0
@@ -8,6 +8,7 @@ · 7 unmodified lines
88 #include <drm/drm_device.h>
99 #include <drm/drm_mode.h>
1010 #include <drm/drm_fourcc.h>
11+#include <drm/drm_print.h>
1112
1213 #include "../drm_crtc_internal.h"
1314
drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c+50−0
@@ -13,6 +13,7 @@ struct qcom_smmu { · 12 unmodified lines
1313 struct arm_smmu_device smmu;
1414 bool bypass_quirk;
1515 u8 bypass_cbndx;
16+ u32 stall_enabled;
1617 };
1718
1819 static struct qcom_smmu *to_qcom_smmu(struct arm_smmu_device *smmu)
@@ -23,15 +24,61 @@ static struct qcom_smmu *to_qcom_smmu(struct arm_smmu_device *smmu) · 4 unmodified lines
2324 static void qcom_adreno_smmu_write_sctlr(struct arm_smmu_device *smmu, int idx,
2425 u32 reg)
2526 {
27+ struct qcom_smmu *qsmmu = to_qcom_smmu(smmu);
28+
2629 /*
2730 * On the GPU device we want to process subsequent transactions after a
2831 * fault to keep the GPU from hanging
2932 */
3033 reg |= ARM_SMMU_SCTLR_HUPCF;
3134
35+ if (qsmmu->stall_enabled & BIT(idx))
36+ reg |= ARM_SMMU_SCTLR_CFCFG;
37+
3238 arm_smmu_cb_write(smmu, idx, ARM_SMMU_CB_SCTLR, reg);
3339 }
3440
41+static void qcom_adreno_smmu_get_fault_info(const void *cookie,
42+ struct adreno_smmu_fault_info *info)
43+{
44+ struct arm_smmu_domain *smmu_domain = (void *)cookie;
45+ struct arm_smmu_cfg *cfg = &smmu_domain->cfg;
46+ struct arm_smmu_device *smmu = smmu_domain->smmu;
47+
48+ info->fsr = arm_smmu_cb_read(smmu, cfg->cbndx, ARM_SMMU_CB_FSR);
49+ info->fsynr0 = arm_smmu_cb_read(smmu, cfg->cbndx, ARM_SMMU_CB_FSYNR0);
50+ info->fsynr1 = arm_smmu_cb_read(smmu, cfg->cbndx, ARM_SMMU_CB_FSYNR1);
51+ info->far = arm_smmu_cb_readq(smmu, cfg->cbndx, ARM_SMMU_CB_FAR);
52+ info->cbfrsynra = arm_smmu_gr1_read(smmu, ARM_SMMU_GR1_CBFRSYNRA(cfg->cbndx));
53+ info->ttbr0 = arm_smmu_cb_read(smmu, cfg->cbndx, ARM_SMMU_CB_TTBR0);
54+ info->contextidr = arm_smmu_cb_read(smmu, cfg->cbndx, ARM_SMMU_CB_CONTEXTIDR);
55+}
56+
57+static void qcom_adreno_smmu_set_stall(const void *cookie, bool enabled)
58+{
59+ struct arm_smmu_domain *smmu_domain = (void *)cookie;
60+ struct arm_smmu_cfg *cfg = &smmu_domain->cfg;
61+ struct qcom_smmu *qsmmu = to_qcom_smmu(smmu_domain->smmu);
62+
63+ if (enabled)
64+ qsmmu->stall_enabled |= BIT(cfg->cbndx);
65+ else
66+ qsmmu->stall_enabled &= ~BIT(cfg->cbndx);
67+}
68+
69+static void qcom_adreno_smmu_resume_translation(const void *cookie, bool terminate)
70+{
71+ struct arm_smmu_domain *smmu_domain = (void *)cookie;
72+ struct arm_smmu_cfg *cfg = &smmu_domain->cfg;
73+ struct arm_smmu_device *smmu = smmu_domain->smmu;
74+ u32 reg = 0;
75+
76+ if (terminate)
77+ reg |= ARM_SMMU_RESUME_TERMINATE;
78+
79+ arm_smmu_cb_write(smmu, cfg->cbndx, ARM_SMMU_CB_RESUME, reg);
80+}
81+
3582 #define QCOM_ADRENO_SMMU_GPU_SID 0
3683
3784 static bool qcom_adreno_smmu_is_gpu_device(struct device *dev)
@@ -156,6 +203,9 @@ static int qcom_adreno_smmu_init_context(struct arm_smmu_domain *smmu_domain, · 118 unmodified lines
156203 priv->cookie = smmu_domain;
157204 priv->get_ttbr1_cfg = qcom_adreno_smmu_get_ttbr1_cfg;
158205 priv->set_ttbr0_cfg = qcom_adreno_smmu_set_ttbr0_cfg;
206+ priv->get_fault_info = qcom_adreno_smmu_get_fault_info;
207+ priv->set_stall = qcom_adreno_smmu_set_stall;
208+ priv->resume_translation = qcom_adreno_smmu_resume_translation;
159209
160210 return 0;
161211 }
drivers/iommu/arm/arm-smmu/arm-smmu.c+7−2
@@ -408,6 +408,7 @@ static irqreturn_t arm_smmu_context_fault(int irq, void *dev) · 407 unmodified lines
408408 struct arm_smmu_domain *smmu_domain = to_smmu_domain(domain);
409409 struct arm_smmu_device *smmu = smmu_domain->smmu;
410410 int idx = smmu_domain->cfg.cbndx;
411+ int ret;
411412
412413 fsr = arm_smmu_cb_read(smmu, idx, ARM_SMMU_CB_FSR);
413414 if (!(fsr & ARM_SMMU_FSR_FAULT))
@@ -417,8 +418,12 @@ static irqreturn_t arm_smmu_context_fault(int irq, void *dev) · 3 unmodified lines
417418 iova = arm_smmu_cb_readq(smmu, idx, ARM_SMMU_CB_FAR);
418419 cbfrsynra = arm_smmu_gr1_read(smmu, ARM_SMMU_GR1_CBFRSYNRA(idx));
419420
420− dev_err_ratelimited(smmu->dev,
421− "Unhandled context fault: fsr=0x%x, iova=0x%08lx, fsynr=0x%x, cbfrsynra=0x%x, cb=%d\n",
421+ ret = report_iommu_fault(domain, NULL, iova,
422+ fsynr & ARM_SMMU_FSYNR0_WNR ? IOMMU_FAULT_WRITE : IOMMU_FAULT_READ);
423+
424+ if (ret == -ENOSYS)
425+ dev_err_ratelimited(smmu->dev,
426+ "Unhandled context fault: fsr=0x%x, iova=0x%08lx, fsynr=0x%x, cbfrsynra=0x%x, cb=%d\n",
422427 fsr, iova, fsynr, cbfrsynra, idx);
423428
424429 arm_smmu_cb_write(smmu, idx, ARM_SMMU_CB_FSR, fsr);
drivers/iommu/arm/arm-smmu/arm-smmu.h+2−0
@@ -224,6 +224,8 @@ enum arm_smmu_cbar_type { · 223 unmodified lines
224224 #define ARM_SMMU_CB_FSYNR0 0x68
225225 #define ARM_SMMU_FSYNR0_WNR BIT(4)
226226
227+#define ARM_SMMU_CB_FSYNR1 0x6c
228+
227229 #define ARM_SMMU_CB_S1_TLBIVA 0x600
228230 #define ARM_SMMU_CB_S1_TLBIASID 0x610
229231 #define ARM_SMMU_CB_S1_TLBIVAL 0x620
include/linux/adreno-smmu-priv.h+37−1
@@ -8,6 +8,32 @@ · 7 unmodified lines
88
99 #include <linux/io-pgtable.h>
1010
11+/**
12+ * struct adreno_smmu_fault_info - container for key fault information
13+ *
14+ * @far: The faulting IOVA from ARM_SMMU_CB_FAR
15+ * @ttbr0: The current TTBR0 pagetable from ARM_SMMU_CB_TTBR0
16+ * @contextidr: The value of ARM_SMMU_CB_CONTEXTIDR
17+ * @fsr: The fault status from ARM_SMMU_CB_FSR
18+ * @fsynr0: The value of FSYNR0 from ARM_SMMU_CB_FSYNR0
19+ * @fsynr1: The value of FSYNR1 from ARM_SMMU_CB_FSYNR0
20+ * @cbfrsynra: The value of CBFRSYNRA from ARM_SMMU_GR1_CBFRSYNRA(idx)
21+ *
22+ * This struct passes back key page fault information to the GPU driver
23+ * through the get_fault_info function pointer.
24+ * The GPU driver can use this information to print informative
25+ * log messages and provide deeper GPU specific insight into the fault.
26+ */
27+struct adreno_smmu_fault_info {
28+ u64 far;
29+ u64 ttbr0;
30+ u32 contextidr;
31+ u32 fsr;
32+ u32 fsynr0;
33+ u32 fsynr1;
34+ u32 cbfrsynra;
35+};
36+
1137 /**
1238 * struct adreno_smmu_priv - private interface between adreno-smmu and GPU
1339 *
@@ -17,6 +43,13 @@ · 3 unmodified lines
1743 * @set_ttbr0_cfg: Set the TTBR0 config for the GPUs context bank. A
1844 * NULL config disables TTBR0 translation, otherwise
1945 * TTBR0 translation is enabled with the specified cfg
46+ * @get_fault_info: Called by the GPU fault handler to get information about
47+ * the fault
48+ * @set_stall: Configure whether stall on fault (CFCFG) is enabled. Call
49+ * before set_ttbr0_cfg(). If stalling on fault is enabled,
50+ * the GPU driver must call resume_translation()
51+ * @resume_translation: Resume translation after a fault
52+ *
2053 *
2154 * The GPU driver (drm/msm) and adreno-smmu work together for controlling
2255 * the GPU's SMMU instance. This is by necessity, as the GPU is directly
@@ -31,6 +64,9 @@ struct adreno_smmu_priv { · 8 unmodified lines
3164 const void *cookie;
3265 const struct io_pgtable_cfg *(*get_ttbr1_cfg)(const void *cookie);
3366 int (*set_ttbr0_cfg)(const void *cookie, const struct io_pgtable_cfg *cfg);
67+ void (*get_fault_info)(const void *cookie, struct adreno_smmu_fault_info *info);
68+ void (*set_stall)(const void *cookie, bool enabled);
69+ void (*resume_translation)(const void *cookie, bool terminate);
3470 };
3571
36−#endif /* __ADRENO_SMMU_PRIV_H */
72+#endif /* __ADRENO_SMMU_PRIV_H */
include/uapi/drm/msm_drm.h+3−4
@@ -94,13 +94,12 @@ struct drm_msm_param { · 93 unmodified lines
9494 /* cache modes */
9595 #define MSM_BO_CACHED 0x00010000
9696 #define MSM_BO_WC 0x00020000
97−#define MSM_BO_UNCACHED 0x00040000
97+#define MSM_BO_UNCACHED 0x00040000 /* deprecated, use MSM_BO_WC */
98+#define MSM_BO_CACHED_COHERENT 0x080000
9899
99100 #define MSM_BO_FLAGS (MSM_BO_SCANOUT | \
100101 MSM_BO_GPU_READONLY | \
101− MSM_BO_CACHED | \
102− MSM_BO_WC | \
103− MSM_BO_UNCACHED)
102+ MSM_BO_CACHE_MASK)
104103
105104 struct drm_msm_gem_new {
106105 __u64 size; /* in */