History

Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux

Pull clk updates from Stephen Boyd: "We have a couple patches in the framework core this time around but they're mostly minor cleanups and some debugfs stuff. The real work that's in here is the typical pile of clk driver updates and new SoC support. Per usual (or maybe just recent trends), Qualcomm gains a handful of SoC drivers additions and has the largest diffstat. After that there are quite a few updates to the Allwinner (sunxi) drivers to support modular drivers and Renesas is heavily updated to add more support for various clks. Overall it looks pretty normal. New Drivers: - Add MDMA and BDMA clks to Ingenic JZ4760 and JZ4770 - MediaTek mt7986 SoC basic support - Clock and reset driver for Toshiba Visconti SoCs - Initial clock driver for the Exynos7885 SoC (Samsung Galaxy A8) - Allwinner D1 clks - Lan966x Generic Clock Controller driver and associated DT bindings - Qualcomm SDX65, SM8450, and MSM8976 GCC clks - Qualcomm SDX65 and SM8450 RPMh clks Updates: - Set suppress_bind_attrs to true for i.MX8ULP driver - Switch from do_div to div64_ul for throughout all i.MX drivers - Fix imx8mn_clko1_sels for i.MX8MN - Remove unused IPG_AUDIO_ROOT from i.MX8MP - Switch parent for audio_root_clk to audio ahb in i.MX8MP driver - Removal of all remaining uses of __clk_lookup() in drivers/clk/samsung - Refactoring of the CPU clocks registration to use common interface - An update of the Exynos850 driver (support for more clock domains) required by the E850-96 development board - Prep for runtime PM and generic power domains on Tegra - Support modular Allwinner clk drivers via platform bus - Lan966x clock driver extended to support clock gating - Add serial (SCI1), watchdog (WDT), timer (OSTM), SPI (RSPI), and thermal (TSU) clocks and resets on Renesas RZ/G2L - Rework SDHI clock handling in the Renesas R-Car Gen3 and RZ/G2 clock drivers, and in the Renesas SDHI driver - Make the Cortex-A55 (I) clock on Renesas RZ/G2L programmable - Document support for the new Renesas R-Car S4-8 (R8A779F0) SoC - Add support for the new Renesas R-Car S4-8 (R8A779F0) SoC - Add GPU clock and resets on Renesas RZ/G2L - Add clk-provider.h to various Qualcomm clk drivers - devm version of clk_hw_register_gate() - kerneldoc fixes in a couple drivers" * tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (131 commits) clk: visconti: Remove pointless NULL check in visconti_pll_add_lookup() clk: mediatek: add mt7986 clock support clk: mediatek: add mt7986 clock IDs dt-bindings: clock: mediatek: document clk bindings for mediatek mt7986 SoC clk: mediatek: clk-gate: Use regmap_{set/clear}_bits helpers clk: mediatek: clk-gate: Shrink by adding clockgating bit check helper clk: x86: Fix clk_gate_flags for RV_CLK_GATE clk: x86: Use dynamic con_id string during clk registration ACPI: APD: Add a fmw property clk-name drivers: acpi: acpi_apd: Remove unused device property "is-rv" x86: clk: clk-fch: Add support for newer family of AMD's SOC clk: ingenic: Add MDMA and BDMA clocks dt-bindings: clk/ingenic: Add MDMA and BDMA clocks clk: bm1880: remove kfrees on static allocations clk: Drop unused COMMON_CLK_STM32MP157_SCMI config clk: st: clkgen-mux: search reg within node or parent clk: st: clkgen-fsyn: search reg within node or parent clk: Enable/Disable runtime PM for clk_summary MAINTAINERS: Add entries for Toshiba Visconti PLL and clock controller clk: visconti: Add support common clock driver and reset driver ...

Linus Torvalds committed 4 years ago

Commit 455e73a2 parents d9b5941 4afd2a9198 files · +18551 −1240Browse files

Showing the changes to include (20 of 198 files). Show all

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20 files
  1. include/dt-bindings/clock/exynos4.h +3 −1
  2. include/dt-bindings/clock/exynos5250.h +3 −1
  3. include/dt-bindings/clock/exynos7885.h +115 −0
  4. include/dt-bindings/clock/exynos850.h +52 −2
  5. include/dt-bindings/clock/imx8mp-clock.h +0 −1
  6. include/dt-bindings/clock/ingenic,jz4760-cgu.h +2 −0
  7. include/dt-bindings/clock/ingenic,jz4770-cgu.h +1 −0
  8. include/dt-bindings/clock/microchip,lan966x.h +34 −0
  9. include/dt-bindings/clock/mt7986-clk.h +169 −0
  10. include/dt-bindings/clock/qcom,gcc-msm8976.h +240 −0
  11. include/dt-bindings/clock/sun20i-d1-ccu.h +156 −0
  12. include/dt-bindings/clock/sun20i-d1-r-ccu.h +19 −0
  13. include/dt-bindings/clock/toshiba,tmpv770x.h +181 −0
  14. include/dt-bindings/reset/sun20i-d1-ccu.h +77 −0
  15. include/dt-bindings/reset/sun20i-d1-r-ccu.h +16 −0
  16. include/dt-bindings/reset/toshiba,tmpv770x.h +41 −0
  17. include/linux/clk-provider.h +23 −0
  18. include/linux/clk/sunxi-ng.h +0 −15
  19. include/linux/mfd/tps68470.h +11 −0
  20. include/linux/platform_data/clk-fch.h +1 −1
include/dt-bindings/clock/exynos4.h+3−1
@@ -209,6 +209,7 @@ · 208 unmodified lines
209209 #define CLK_ACLK400_MCUISP 395 /* Exynos4x12 only */
210210 #define CLK_MOUT_HDMI 396
211211 #define CLK_MOUT_MIXER 397
212+#define CLK_MOUT_VPLLSRC 398
212213
213214 /* gate clocks - ppmu */
214215 #define CLK_PPMULEFT 400
@@ -236,9 +237,10 @@ · 21 unmodified lines
236237 #define CLK_DIV_C2C 458 /* Exynos4x12 only */
237238 #define CLK_DIV_GDL 459
238239 #define CLK_DIV_GDR 460
240+#define CLK_DIV_CORE2 461
239241
240242 /* must be greater than maximal clock id */
241−#define CLK_NR_CLKS 461
243+#define CLK_NR_CLKS 462
242244
243245 /* Exynos4x12 ISP clocks */
244246 #define CLK_ISP_FIMC_ISP 1
include/dt-bindings/clock/exynos5250.h+3−1
@@ -19,6 +19,7 @@ · 18 unmodified lines
1919 #define CLK_FOUT_EPLL 7
2020 #define CLK_FOUT_VPLL 8
2121 #define CLK_ARM_CLK 9
22+#define CLK_DIV_ARM2 10
2223
2324 /* gate for special clocks (sclk) */
2425 #define CLK_SCLK_CAM_BAYER 128
@@ -174,8 +175,9 @@ · 149 unmodified lines
174175 #define CLK_MOUT_ACLK300_DISP1_SUB 1027
175176 #define CLK_MOUT_APLL 1028
176177 #define CLK_MOUT_MPLL 1029
178+#define CLK_MOUT_VPLLSRC 1030
177179
178180 /* must be greater than maximal clock id */
179−#define CLK_NR_CLKS 1030
181+#define CLK_NR_CLKS 1031
180182
181183 #endif /* _DT_BINDINGS_CLOCK_EXYNOS_5250_H */
include/dt-bindings/clock/exynos7885.h+115−0
@@ -0,0 +1,115 @@
1+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
2+/*
3+ * Copyright (c) 2021 Dávid Virág
4+ *
5+ * Device Tree binding constants for Exynos7885 clock controller.
6+ */
7+
8+#ifndef _DT_BINDINGS_CLOCK_EXYNOS_7885_H
9+#define _DT_BINDINGS_CLOCK_EXYNOS_7885_H
10+
11+/* CMU_TOP */
12+#define CLK_FOUT_SHARED0_PLL 1
13+#define CLK_FOUT_SHARED1_PLL 2
14+#define CLK_DOUT_SHARED0_DIV2 3
15+#define CLK_DOUT_SHARED0_DIV3 4
16+#define CLK_DOUT_SHARED0_DIV4 5
17+#define CLK_DOUT_SHARED0_DIV5 6
18+#define CLK_DOUT_SHARED1_DIV2 7
19+#define CLK_DOUT_SHARED1_DIV3 8
20+#define CLK_DOUT_SHARED1_DIV4 9
21+#define CLK_MOUT_CORE_BUS 10
22+#define CLK_MOUT_CORE_CCI 11
23+#define CLK_MOUT_CORE_G3D 12
24+#define CLK_DOUT_CORE_BUS 13
25+#define CLK_DOUT_CORE_CCI 14
26+#define CLK_DOUT_CORE_G3D 15
27+#define CLK_GOUT_CORE_BUS 16
28+#define CLK_GOUT_CORE_CCI 17
29+#define CLK_GOUT_CORE_G3D 18
30+#define CLK_MOUT_PERI_BUS 19
31+#define CLK_MOUT_PERI_SPI0 20
32+#define CLK_MOUT_PERI_SPI1 21
33+#define CLK_MOUT_PERI_UART0 22
34+#define CLK_MOUT_PERI_UART1 23
35+#define CLK_MOUT_PERI_UART2 24
36+#define CLK_MOUT_PERI_USI0 25
37+#define CLK_MOUT_PERI_USI1 26
38+#define CLK_MOUT_PERI_USI2 27
39+#define CLK_DOUT_PERI_BUS 28
40+#define CLK_DOUT_PERI_SPI0 29
41+#define CLK_DOUT_PERI_SPI1 30
42+#define CLK_DOUT_PERI_UART0 31
43+#define CLK_DOUT_PERI_UART1 32
44+#define CLK_DOUT_PERI_UART2 33
45+#define CLK_DOUT_PERI_USI0 34
46+#define CLK_DOUT_PERI_USI1 35
47+#define CLK_DOUT_PERI_USI2 36
48+#define CLK_GOUT_PERI_BUS 37
49+#define CLK_GOUT_PERI_SPI0 38
50+#define CLK_GOUT_PERI_SPI1 39
51+#define CLK_GOUT_PERI_UART0 40
52+#define CLK_GOUT_PERI_UART1 41
53+#define CLK_GOUT_PERI_UART2 42
54+#define CLK_GOUT_PERI_USI0 43
55+#define CLK_GOUT_PERI_USI1 44
56+#define CLK_GOUT_PERI_USI2 45
57+#define TOP_NR_CLK 46
58+
59+/* CMU_CORE */
60+#define CLK_MOUT_CORE_BUS_USER 1
61+#define CLK_MOUT_CORE_CCI_USER 2
62+#define CLK_MOUT_CORE_G3D_USER 3
63+#define CLK_MOUT_CORE_GIC 4
64+#define CLK_DOUT_CORE_BUSP 5
65+#define CLK_GOUT_CCI_ACLK 6
66+#define CLK_GOUT_GIC400_CLK 7
67+#define CORE_NR_CLK 8
68+
69+/* CMU_PERI */
70+#define CLK_MOUT_PERI_BUS_USER 1
71+#define CLK_MOUT_PERI_SPI0_USER 2
72+#define CLK_MOUT_PERI_SPI1_USER 3
73+#define CLK_MOUT_PERI_UART0_USER 4
74+#define CLK_MOUT_PERI_UART1_USER 5
75+#define CLK_MOUT_PERI_UART2_USER 6
76+#define CLK_MOUT_PERI_USI0_USER 7
77+#define CLK_MOUT_PERI_USI1_USER 8
78+#define CLK_MOUT_PERI_USI2_USER 9
79+#define CLK_GOUT_GPIO_TOP_PCLK 10
80+#define CLK_GOUT_HSI2C0_PCLK 11
81+#define CLK_GOUT_HSI2C1_PCLK 12
82+#define CLK_GOUT_HSI2C2_PCLK 13
83+#define CLK_GOUT_HSI2C3_PCLK 14
84+#define CLK_GOUT_I2C0_PCLK 15
85+#define CLK_GOUT_I2C1_PCLK 16
86+#define CLK_GOUT_I2C2_PCLK 17
87+#define CLK_GOUT_I2C3_PCLK 18
88+#define CLK_GOUT_I2C4_PCLK 19
89+#define CLK_GOUT_I2C5_PCLK 20
90+#define CLK_GOUT_I2C6_PCLK 21
91+#define CLK_GOUT_I2C7_PCLK 22
92+#define CLK_GOUT_PWM_MOTOR_PCLK 23
93+#define CLK_GOUT_SPI0_PCLK 24
94+#define CLK_GOUT_SPI0_EXT_CLK 25
95+#define CLK_GOUT_SPI1_PCLK 26
96+#define CLK_GOUT_SPI1_EXT_CLK 27
97+#define CLK_GOUT_UART0_EXT_UCLK 28
98+#define CLK_GOUT_UART0_PCLK 29
99+#define CLK_GOUT_UART1_EXT_UCLK 30
100+#define CLK_GOUT_UART1_PCLK 31
101+#define CLK_GOUT_UART2_EXT_UCLK 32
102+#define CLK_GOUT_UART2_PCLK 33
103+#define CLK_GOUT_USI0_PCLK 34
104+#define CLK_GOUT_USI0_SCLK 35
105+#define CLK_GOUT_USI1_PCLK 36
106+#define CLK_GOUT_USI1_SCLK 37
107+#define CLK_GOUT_USI2_PCLK 38
108+#define CLK_GOUT_USI2_SCLK 39
109+#define CLK_GOUT_MCT_PCLK 40
110+#define CLK_GOUT_SYSREG_PERI_PCLK 41
111+#define CLK_GOUT_WDT0_PCLK 42
112+#define CLK_GOUT_WDT1_PCLK 43
113+#define PERI_NR_CLK 44
114+
115+#endif /* _DT_BINDINGS_CLOCK_EXYNOS_7885_H */
include/dt-bindings/clock/exynos850.h+52−2
@@ -55,7 +55,55 @@ · 54 unmodified lines
5555 #define CLK_GOUT_PERI_BUS 43
5656 #define CLK_GOUT_PERI_UART 44
5757 #define CLK_GOUT_PERI_IP 45
58−#define TOP_NR_CLK 46
58+#define CLK_MOUT_CLKCMU_APM_BUS 46
59+#define CLK_DOUT_CLKCMU_APM_BUS 47
60+#define CLK_GOUT_CLKCMU_APM_BUS 48
61+#define TOP_NR_CLK 49
62+
63+/* CMU_APM */
64+#define CLK_RCO_I3C_PMIC 1
65+#define OSCCLK_RCO_APM 2
66+#define CLK_RCO_APM__ALV 3
67+#define CLK_DLL_DCO 4
68+#define CLK_MOUT_APM_BUS_USER 5
69+#define CLK_MOUT_RCO_APM_I3C_USER 6
70+#define CLK_MOUT_RCO_APM_USER 7
71+#define CLK_MOUT_DLL_USER 8
72+#define CLK_MOUT_CLKCMU_CHUB_BUS 9
73+#define CLK_MOUT_APM_BUS 10
74+#define CLK_MOUT_APM_I3C 11
75+#define CLK_DOUT_CLKCMU_CHUB_BUS 12
76+#define CLK_DOUT_APM_BUS 13
77+#define CLK_DOUT_APM_I3C 14
78+#define CLK_GOUT_CLKCMU_CMGP_BUS 15
79+#define CLK_GOUT_CLKCMU_CHUB_BUS 16
80+#define CLK_GOUT_RTC_PCLK 17
81+#define CLK_GOUT_TOP_RTC_PCLK 18
82+#define CLK_GOUT_I3C_PCLK 19
83+#define CLK_GOUT_I3C_SCLK 20
84+#define CLK_GOUT_SPEEDY_PCLK 21
85+#define CLK_GOUT_GPIO_ALIVE_PCLK 22
86+#define CLK_GOUT_PMU_ALIVE_PCLK 23
87+#define CLK_GOUT_SYSREG_APM_PCLK 24
88+#define APM_NR_CLK 25
89+
90+/* CMU_CMGP */
91+#define CLK_RCO_CMGP 1
92+#define CLK_MOUT_CMGP_ADC 2
93+#define CLK_MOUT_CMGP_USI0 3
94+#define CLK_MOUT_CMGP_USI1 4
95+#define CLK_DOUT_CMGP_ADC 5
96+#define CLK_DOUT_CMGP_USI0 6
97+#define CLK_DOUT_CMGP_USI1 7
98+#define CLK_GOUT_CMGP_ADC_S0_PCLK 8
99+#define CLK_GOUT_CMGP_ADC_S1_PCLK 9
100+#define CLK_GOUT_CMGP_GPIO_PCLK 10
101+#define CLK_GOUT_CMGP_USI0_IPCLK 11
102+#define CLK_GOUT_CMGP_USI0_PCLK 12
103+#define CLK_GOUT_CMGP_USI1_IPCLK 13
104+#define CLK_GOUT_CMGP_USI1_PCLK 14
105+#define CLK_GOUT_SYSREG_CMGP_PCLK 15
106+#define CMGP_NR_CLK 16
59107
60108 /* CMU_HSI */
61109 #define CLK_MOUT_HSI_BUS_USER 1
@@ -123,7 +171,9 @@ · 61 unmodified lines
123171 #define CLK_GOUT_MMC_EMBD_SDCLKIN 10
124172 #define CLK_GOUT_SSS_ACLK 11
125173 #define CLK_GOUT_SSS_PCLK 12
126−#define CORE_NR_CLK 13
174+#define CLK_GOUT_GPIO_CORE_PCLK 13
175+#define CLK_GOUT_SYSREG_CORE_PCLK 14
176+#define CORE_NR_CLK 15
127177
128178 /* CMU_DPU */
129179 #define CLK_MOUT_DPU_USER 1
include/dt-bindings/clock/imx8mp-clock.h+0−1
@@ -117,7 +117,6 @@ · 116 unmodified lines
117117 #define IMX8MP_CLK_AUDIO_AHB 108
118118 #define IMX8MP_CLK_MIPI_DSI_ESC_RX 109
119119 #define IMX8MP_CLK_IPG_ROOT 110
120−#define IMX8MP_CLK_IPG_AUDIO_ROOT 111
121120 #define IMX8MP_CLK_DRAM_ALT 112
122121 #define IMX8MP_CLK_DRAM_APB 113
123122 #define IMX8MP_CLK_VPU_G1 114
include/dt-bindings/clock/ingenic,jz4760-cgu.h+2−0
@@ -50,5 +50,7 @@ · 49 unmodified lines
5050 #define JZ4760_CLK_LPCLK_DIV 41
5151 #define JZ4760_CLK_TVE 42
5252 #define JZ4760_CLK_LPCLK 43
53+#define JZ4760_CLK_MDMA 44
54+#define JZ4760_CLK_BDMA 45
5355
5456 #endif /* __DT_BINDINGS_CLOCK_JZ4760_CGU_H__ */
include/dt-bindings/clock/ingenic,jz4770-cgu.h+1−0
@@ -54,5 +54,6 @@ · 53 unmodified lines
5454 #define JZ4770_CLK_OTG_PHY 45
5555 #define JZ4770_CLK_EXT512 46
5656 #define JZ4770_CLK_RTC 47
57+#define JZ4770_CLK_BDMA 48
5758
5859 #endif /* __DT_BINDINGS_CLOCK_JZ4770_CGU_H__ */
include/dt-bindings/clock/microchip,lan966x.h+34−0
@@ -0,0 +1,34 @@
1+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
2+/*
3+ * Copyright (c) 2021 Microchip Inc.
4+ *
5+ * Author: Kavyasree Kotagiri <kavyasree.kotagiri@microchip.com>
6+ */
7+
8+#ifndef _DT_BINDINGS_CLK_LAN966X_H
9+#define _DT_BINDINGS_CLK_LAN966X_H
10+
11+#define GCK_ID_QSPI0 0
12+#define GCK_ID_QSPI1 1
13+#define GCK_ID_QSPI2 2
14+#define GCK_ID_SDMMC0 3
15+#define GCK_ID_PI 4
16+#define GCK_ID_MCAN0 5
17+#define GCK_ID_MCAN1 6
18+#define GCK_ID_FLEXCOM0 7
19+#define GCK_ID_FLEXCOM1 8
20+#define GCK_ID_FLEXCOM2 9
21+#define GCK_ID_FLEXCOM3 10
22+#define GCK_ID_FLEXCOM4 11
23+#define GCK_ID_TIMER 12
24+#define GCK_ID_USB_REFCLK 13
25+
26+/* Gate clocks */
27+#define GCK_GATE_UHPHS 14
28+#define GCK_GATE_UDPHS 15
29+#define GCK_GATE_MCRAMC 16
30+#define GCK_GATE_HMATRIX 17
31+
32+#define N_CLOCKS 18
33+
34+#endif
include/dt-bindings/clock/mt7986-clk.h+169−0
@@ -0,0 +1,169 @@
1+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
2+/*
3+ * Copyright (c) 2021 MediaTek Inc.
4+ * Author: Sam Shih <sam.shih@mediatek.com>
5+ */
6+
7+#ifndef _DT_BINDINGS_CLK_MT7986_H
8+#define _DT_BINDINGS_CLK_MT7986_H
9+
10+/* APMIXEDSYS */
11+
12+#define CLK_APMIXED_ARMPLL 0
13+#define CLK_APMIXED_NET2PLL 1
14+#define CLK_APMIXED_MMPLL 2
15+#define CLK_APMIXED_SGMPLL 3
16+#define CLK_APMIXED_WEDMCUPLL 4
17+#define CLK_APMIXED_NET1PLL 5
18+#define CLK_APMIXED_MPLL 6
19+#define CLK_APMIXED_APLL2 7
20+
21+/* TOPCKGEN */
22+
23+#define CLK_TOP_XTAL 0
24+#define CLK_TOP_XTAL_D2 1
25+#define CLK_TOP_RTC_32K 2
26+#define CLK_TOP_RTC_32P7K 3
27+#define CLK_TOP_MPLL_D2 4
28+#define CLK_TOP_MPLL_D4 5
29+#define CLK_TOP_MPLL_D8 6
30+#define CLK_TOP_MPLL_D8_D2 7
31+#define CLK_TOP_MPLL_D3_D2 8
32+#define CLK_TOP_MMPLL_D2 9
33+#define CLK_TOP_MMPLL_D4 10
34+#define CLK_TOP_MMPLL_D8 11
35+#define CLK_TOP_MMPLL_D8_D2 12
36+#define CLK_TOP_MMPLL_D3_D8 13
37+#define CLK_TOP_MMPLL_U2PHY 14
38+#define CLK_TOP_APLL2_D4 15
39+#define CLK_TOP_NET1PLL_D4 16
40+#define CLK_TOP_NET1PLL_D5 17
41+#define CLK_TOP_NET1PLL_D5_D2 18
42+#define CLK_TOP_NET1PLL_D5_D4 19
43+#define CLK_TOP_NET1PLL_D8_D2 20
44+#define CLK_TOP_NET1PLL_D8_D4 21
45+#define CLK_TOP_NET2PLL_D4 22
46+#define CLK_TOP_NET2PLL_D4_D2 23
47+#define CLK_TOP_NET2PLL_D3_D2 24
48+#define CLK_TOP_WEDMCUPLL_D5_D2 25
49+#define CLK_TOP_NFI1X_SEL 26
50+#define CLK_TOP_SPINFI_SEL 27
51+#define CLK_TOP_SPI_SEL 28
52+#define CLK_TOP_SPIM_MST_SEL 29
53+#define CLK_TOP_UART_SEL 30
54+#define CLK_TOP_PWM_SEL 31
55+#define CLK_TOP_I2C_SEL 32
56+#define CLK_TOP_PEXTP_TL_SEL 33
57+#define CLK_TOP_EMMC_250M_SEL 34
58+#define CLK_TOP_EMMC_416M_SEL 35
59+#define CLK_TOP_F_26M_ADC_SEL 36
60+#define CLK_TOP_DRAMC_SEL 37
61+#define CLK_TOP_DRAMC_MD32_SEL 38
62+#define CLK_TOP_SYSAXI_SEL 39
63+#define CLK_TOP_SYSAPB_SEL 40
64+#define CLK_TOP_ARM_DB_MAIN_SEL 41
65+#define CLK_TOP_ARM_DB_JTSEL 42
66+#define CLK_TOP_NETSYS_SEL 43
67+#define CLK_TOP_NETSYS_500M_SEL 44
68+#define CLK_TOP_NETSYS_MCU_SEL 45
69+#define CLK_TOP_NETSYS_2X_SEL 46
70+#define CLK_TOP_SGM_325M_SEL 47
71+#define CLK_TOP_SGM_REG_SEL 48
72+#define CLK_TOP_A1SYS_SEL 49
73+#define CLK_TOP_CONN_MCUSYS_SEL 50
74+#define CLK_TOP_EIP_B_SEL 51
75+#define CLK_TOP_PCIE_PHY_SEL 52
76+#define CLK_TOP_USB3_PHY_SEL 53
77+#define CLK_TOP_F26M_SEL 54
78+#define CLK_TOP_AUD_L_SEL 55
79+#define CLK_TOP_A_TUNER_SEL 56
80+#define CLK_TOP_U2U3_SEL 57
81+#define CLK_TOP_U2U3_SYS_SEL 58
82+#define CLK_TOP_U2U3_XHCI_SEL 59
83+#define CLK_TOP_DA_U2_REFSEL 60
84+#define CLK_TOP_DA_U2_CK_1P_SEL 61
85+#define CLK_TOP_AP2CNN_HOST_SEL 62
86+#define CLK_TOP_JTAG 63
87+
88+/* INFRACFG */
89+
90+#define CLK_INFRA_SYSAXI_D2 0
91+#define CLK_INFRA_UART0_SEL 1
92+#define CLK_INFRA_UART1_SEL 2
93+#define CLK_INFRA_UART2_SEL 3
94+#define CLK_INFRA_SPI0_SEL 4
95+#define CLK_INFRA_SPI1_SEL 5
96+#define CLK_INFRA_PWM1_SEL 6
97+#define CLK_INFRA_PWM2_SEL 7
98+#define CLK_INFRA_PWM_BSEL 8
99+#define CLK_INFRA_PCIE_SEL 9
100+#define CLK_INFRA_GPT_STA 10
101+#define CLK_INFRA_PWM_HCK 11
102+#define CLK_INFRA_PWM_STA 12
103+#define CLK_INFRA_PWM1_CK 13
104+#define CLK_INFRA_PWM2_CK 14
105+#define CLK_INFRA_CQ_DMA_CK 15
106+#define CLK_INFRA_EIP97_CK 16
107+#define CLK_INFRA_AUD_BUS_CK 17
108+#define CLK_INFRA_AUD_26M_CK 18
109+#define CLK_INFRA_AUD_L_CK 19
110+#define CLK_INFRA_AUD_AUD_CK 20
111+#define CLK_INFRA_AUD_EG2_CK 21
112+#define CLK_INFRA_DRAMC_26M_CK 22
113+#define CLK_INFRA_DBG_CK 23
114+#define CLK_INFRA_AP_DMA_CK 24
115+#define CLK_INFRA_SEJ_CK 25
116+#define CLK_INFRA_SEJ_13M_CK 26
117+#define CLK_INFRA_THERM_CK 27
118+#define CLK_INFRA_I2C0_CK 28
119+#define CLK_INFRA_UART0_CK 29
120+#define CLK_INFRA_UART1_CK 30
121+#define CLK_INFRA_UART2_CK 31
122+#define CLK_INFRA_NFI1_CK 32
123+#define CLK_INFRA_SPINFI1_CK 33
124+#define CLK_INFRA_NFI_HCK_CK 34
125+#define CLK_INFRA_SPI0_CK 35
126+#define CLK_INFRA_SPI1_CK 36
127+#define CLK_INFRA_SPI0_HCK_CK 37
128+#define CLK_INFRA_SPI1_HCK_CK 38
129+#define CLK_INFRA_FRTC_CK 39
130+#define CLK_INFRA_MSDC_CK 40
131+#define CLK_INFRA_MSDC_HCK_CK 41
132+#define CLK_INFRA_MSDC_133M_CK 42
133+#define CLK_INFRA_MSDC_66M_CK 43
134+#define CLK_INFRA_ADC_26M_CK 44
135+#define CLK_INFRA_ADC_FRC_CK 45
136+#define CLK_INFRA_FBIST2FPC_CK 46
137+#define CLK_INFRA_IUSB_133_CK 47
138+#define CLK_INFRA_IUSB_66M_CK 48
139+#define CLK_INFRA_IUSB_SYS_CK 49
140+#define CLK_INFRA_IUSB_CK 50
141+#define CLK_INFRA_IPCIE_CK 51
142+#define CLK_INFRA_IPCIE_PIPE_CK 52
143+#define CLK_INFRA_IPCIER_CK 53
144+#define CLK_INFRA_IPCIEB_CK 54
145+#define CLK_INFRA_TRNG_CK 55
146+
147+/* SGMIISYS_0 */
148+
149+#define CLK_SGMII0_TX250M_EN 0
150+#define CLK_SGMII0_RX250M_EN 1
151+#define CLK_SGMII0_CDR_REF 2
152+#define CLK_SGMII0_CDR_FB 3
153+
154+/* SGMIISYS_1 */
155+
156+#define CLK_SGMII1_TX250M_EN 0
157+#define CLK_SGMII1_RX250M_EN 1
158+#define CLK_SGMII1_CDR_REF 2
159+#define CLK_SGMII1_CDR_FB 3
160+
161+/* ETHSYS */
162+
163+#define CLK_ETH_FE_EN 0
164+#define CLK_ETH_GP2_EN 1
165+#define CLK_ETH_GP1_EN 2
166+#define CLK_ETH_WOCPU1_EN 3
167+#define CLK_ETH_WOCPU0_EN 4
168+
169+#endif /* _DT_BINDINGS_CLK_MT7986_H */
include/dt-bindings/clock/qcom,gcc-msm8976.h+240−0
@@ -0,0 +1,240 @@
1+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
2+/*
3+ * Copyright (C) 2016, The Linux Foundation. All rights reserved.
4+ * Copyright (C) 2016-2021, AngeloGioacchino Del Regno
5+ * <angelogioacchino.delregno@somainline.org>
6+ */
7+
8+#ifndef _DT_BINDINGS_CLK_MSM_GCC_8976_H
9+#define _DT_BINDINGS_CLK_MSM_GCC_8976_H
10+
11+#define GPLL0 0
12+#define GPLL2 1
13+#define GPLL3 2
14+#define GPLL4 3
15+#define GPLL6 4
16+#define GPLL0_CLK_SRC 5
17+#define GPLL2_CLK_SRC 6
18+#define GPLL3_CLK_SRC 7
19+#define GPLL4_CLK_SRC 8
20+#define GPLL6_CLK_SRC 9
21+#define GCC_BLSP1_QUP1_SPI_APPS_CLK 10
22+#define GCC_BLSP1_QUP1_I2C_APPS_CLK 11
23+#define GCC_BLSP1_QUP2_I2C_APPS_CLK 12
24+#define GCC_BLSP1_QUP2_SPI_APPS_CLK 13
25+#define GCC_BLSP1_QUP3_I2C_APPS_CLK 14
26+#define GCC_BLSP1_QUP3_SPI_APPS_CLK 15
27+#define GCC_BLSP1_QUP4_I2C_APPS_CLK 16
28+#define GCC_BLSP1_QUP4_SPI_APPS_CLK 17
29+#define GCC_BLSP1_UART1_APPS_CLK 18
30+#define GCC_BLSP1_UART2_APPS_CLK 19
31+#define GCC_BLSP2_QUP1_I2C_APPS_CLK 20
32+#define GCC_BLSP2_QUP1_SPI_APPS_CLK 21
33+#define GCC_BLSP2_QUP2_I2C_APPS_CLK 22
34+#define GCC_BLSP2_QUP2_SPI_APPS_CLK 23
35+#define GCC_BLSP2_QUP3_I2C_APPS_CLK 24
36+#define GCC_BLSP2_QUP3_SPI_APPS_CLK 25
37+#define GCC_BLSP2_QUP4_I2C_APPS_CLK 26
38+#define GCC_BLSP2_QUP4_SPI_APPS_CLK 27
39+#define GCC_BLSP2_UART1_APPS_CLK 28
40+#define GCC_BLSP2_UART2_APPS_CLK 29
41+#define GCC_CAMSS_CCI_AHB_CLK 30
42+#define GCC_CAMSS_CCI_CLK 31
43+#define GCC_CAMSS_CPP_AHB_CLK 32
44+#define GCC_CAMSS_CPP_AXI_CLK 33
45+#define GCC_CAMSS_CPP_CLK 34
46+#define GCC_CAMSS_CSI0_AHB_CLK 35
47+#define GCC_CAMSS_CSI0_CLK 36
48+#define GCC_CAMSS_CSI0PHY_CLK 37
49+#define GCC_CAMSS_CSI0PIX_CLK 38
50+#define GCC_CAMSS_CSI0RDI_CLK 39
51+#define GCC_CAMSS_CSI1_AHB_CLK 40
52+#define GCC_CAMSS_CSI1_CLK 41
53+#define GCC_CAMSS_CSI1PHY_CLK 42
54+#define GCC_CAMSS_CSI1PIX_CLK 43
55+#define GCC_CAMSS_CSI1RDI_CLK 44
56+#define GCC_CAMSS_CSI2_AHB_CLK 45
57+#define GCC_CAMSS_CSI2_CLK 46
58+#define GCC_CAMSS_CSI2PHY_CLK 47
59+#define GCC_CAMSS_CSI2PIX_CLK 48
60+#define GCC_CAMSS_CSI2RDI_CLK 49
61+#define GCC_CAMSS_CSI_VFE0_CLK 50
62+#define GCC_CAMSS_CSI_VFE1_CLK 51
63+#define GCC_CAMSS_GP0_CLK 52
64+#define GCC_CAMSS_GP1_CLK 53
65+#define GCC_CAMSS_ISPIF_AHB_CLK 54
66+#define GCC_CAMSS_JPEG0_CLK 55
67+#define GCC_CAMSS_JPEG_AHB_CLK 56
68+#define GCC_CAMSS_JPEG_AXI_CLK 57
69+#define GCC_CAMSS_MCLK0_CLK 58
70+#define GCC_CAMSS_MCLK1_CLK 59
71+#define GCC_CAMSS_MCLK2_CLK 60
72+#define GCC_CAMSS_MICRO_AHB_CLK 61
73+#define GCC_CAMSS_CSI0PHYTIMER_CLK 62
74+#define GCC_CAMSS_CSI1PHYTIMER_CLK 63
75+#define GCC_CAMSS_AHB_CLK 64
76+#define GCC_CAMSS_TOP_AHB_CLK 65
77+#define GCC_CAMSS_VFE0_CLK 66
78+#define GCC_CAMSS_VFE_AHB_CLK 67
79+#define GCC_CAMSS_VFE_AXI_CLK 68
80+#define GCC_CAMSS_VFE1_AHB_CLK 69
81+#define GCC_CAMSS_VFE1_AXI_CLK 70
82+#define GCC_CAMSS_VFE1_CLK 71
83+#define GCC_DCC_CLK 72
84+#define GCC_GP1_CLK 73
85+#define GCC_GP2_CLK 74
86+#define GCC_GP3_CLK 75
87+#define GCC_MDSS_AHB_CLK 76
88+#define GCC_MDSS_AXI_CLK 77
89+#define GCC_MDSS_ESC0_CLK 78
90+#define GCC_MDSS_ESC1_CLK 79
91+#define GCC_MDSS_MDP_CLK 80
92+#define GCC_MDSS_VSYNC_CLK 81
93+#define GCC_MSS_CFG_AHB_CLK 82
94+#define GCC_MSS_Q6_BIMC_AXI_CLK 83
95+#define GCC_PDM2_CLK 84
96+#define GCC_PRNG_AHB_CLK 85
97+#define GCC_PDM_AHB_CLK 86
98+#define GCC_RBCPR_GFX_AHB_CLK 87
99+#define GCC_RBCPR_GFX_CLK 88
100+#define GCC_SDCC1_AHB_CLK 89
101+#define GCC_SDCC1_APPS_CLK 90
102+#define GCC_SDCC1_ICE_CORE_CLK 91
103+#define GCC_SDCC2_AHB_CLK 92
104+#define GCC_SDCC2_APPS_CLK 93
105+#define GCC_SDCC3_AHB_CLK 94
106+#define GCC_SDCC3_APPS_CLK 95
107+#define GCC_USB2A_PHY_SLEEP_CLK 96
108+#define GCC_USB_HS_PHY_CFG_AHB_CLK 97
109+#define GCC_USB_FS_AHB_CLK 98
110+#define GCC_USB_FS_IC_CLK 99
111+#define GCC_USB_FS_SYSTEM_CLK 100
112+#define GCC_USB_HS_AHB_CLK 101
113+#define GCC_USB_HS_SYSTEM_CLK 102
114+#define GCC_VENUS0_AHB_CLK 103
115+#define GCC_VENUS0_AXI_CLK 104
116+#define GCC_VENUS0_CORE0_VCODEC0_CLK 105
117+#define GCC_VENUS0_CORE1_VCODEC0_CLK 106
118+#define GCC_VENUS0_VCODEC0_CLK 107
119+#define GCC_APSS_AHB_CLK 108
120+#define GCC_APSS_AXI_CLK 109
121+#define GCC_BLSP1_AHB_CLK 110
122+#define GCC_BLSP2_AHB_CLK 111
123+#define GCC_BOOT_ROM_AHB_CLK 112
124+#define GCC_CRYPTO_AHB_CLK 113
125+#define GCC_CRYPTO_AXI_CLK 114
126+#define GCC_CRYPTO_CLK 115
127+#define GCC_CPP_TBU_CLK 116
128+#define GCC_APSS_TCU_CLK 117
129+#define GCC_JPEG_TBU_CLK 118
130+#define GCC_MDP_RT_TBU_CLK 119
131+#define GCC_MDP_TBU_CLK 120
132+#define GCC_SMMU_CFG_CLK 121
133+#define GCC_VENUS_1_TBU_CLK 122
134+#define GCC_VENUS_TBU_CLK 123
135+#define GCC_VFE1_TBU_CLK 124
136+#define GCC_VFE_TBU_CLK 125
137+#define GCC_APS_0_CLK 126
138+#define GCC_APS_1_CLK 127
139+#define APS_0_CLK_SRC 128
140+#define APS_1_CLK_SRC 129
141+#define APSS_AHB_CLK_SRC 130
142+#define BLSP1_QUP1_I2C_APPS_CLK_SRC 131
143+#define BLSP1_QUP1_SPI_APPS_CLK_SRC 132
144+#define BLSP1_QUP2_I2C_APPS_CLK_SRC 133
145+#define BLSP1_QUP2_SPI_APPS_CLK_SRC 134
146+#define BLSP1_QUP3_I2C_APPS_CLK_SRC 135
147+#define BLSP1_QUP3_SPI_APPS_CLK_SRC 136
148+#define BLSP1_QUP4_I2C_APPS_CLK_SRC 137
149+#define BLSP1_QUP4_SPI_APPS_CLK_SRC 138
150+#define BLSP1_UART1_APPS_CLK_SRC 139
151+#define BLSP1_UART2_APPS_CLK_SRC 140
152+#define BLSP2_QUP1_I2C_APPS_CLK_SRC 141
153+#define BLSP2_QUP1_SPI_APPS_CLK_SRC 142
154+#define BLSP2_QUP2_I2C_APPS_CLK_SRC 143
155+#define BLSP2_QUP2_SPI_APPS_CLK_SRC 144
156+#define BLSP2_QUP3_I2C_APPS_CLK_SRC 145
157+#define BLSP2_QUP3_SPI_APPS_CLK_SRC 146
158+#define BLSP2_QUP4_I2C_APPS_CLK_SRC 147
159+#define BLSP2_QUP4_SPI_APPS_CLK_SRC 148
160+#define BLSP2_UART1_APPS_CLK_SRC 149
161+#define BLSP2_UART2_APPS_CLK_SRC 150
162+#define CCI_CLK_SRC 151
163+#define CPP_CLK_SRC 152
164+#define CSI0_CLK_SRC 153
165+#define CSI1_CLK_SRC 154
166+#define CSI2_CLK_SRC 155
167+#define CAMSS_GP0_CLK_SRC 156
168+#define CAMSS_GP1_CLK_SRC 157
169+#define JPEG0_CLK_SRC 158
170+#define MCLK0_CLK_SRC 159
171+#define MCLK1_CLK_SRC 160
172+#define MCLK2_CLK_SRC 161
173+#define CSI0PHYTIMER_CLK_SRC 162
174+#define CSI1PHYTIMER_CLK_SRC 163
175+#define CAMSS_TOP_AHB_CLK_SRC 164
176+#define VFE0_CLK_SRC 165
177+#define VFE1_CLK_SRC 166
178+#define CRYPTO_CLK_SRC 167
179+#define GP1_CLK_SRC 168
180+#define GP2_CLK_SRC 169
181+#define GP3_CLK_SRC 170
182+#define ESC0_CLK_SRC 171
183+#define ESC1_CLK_SRC 172
184+#define MDP_CLK_SRC 173
185+#define VSYNC_CLK_SRC 174
186+#define PDM2_CLK_SRC 175
187+#define RBCPR_GFX_CLK_SRC 176
188+#define SDCC1_APPS_CLK_SRC 177
189+#define SDCC1_ICE_CORE_CLK_SRC 178
190+#define SDCC2_APPS_CLK_SRC 179
191+#define SDCC3_APPS_CLK_SRC 180
192+#define USB_FS_IC_CLK_SRC 181
193+#define USB_FS_SYSTEM_CLK_SRC 182
194+#define USB_HS_SYSTEM_CLK_SRC 183
195+#define VCODEC0_CLK_SRC 184
196+#define GCC_MDSS_BYTE0_CLK_SRC 185
197+#define GCC_MDSS_BYTE1_CLK_SRC 186
198+#define GCC_MDSS_BYTE0_CLK 187
199+#define GCC_MDSS_BYTE1_CLK 188
200+#define GCC_MDSS_PCLK0_CLK_SRC 189
201+#define GCC_MDSS_PCLK1_CLK_SRC 190
202+#define GCC_MDSS_PCLK0_CLK 191
203+#define GCC_MDSS_PCLK1_CLK 192
204+#define GCC_GFX3D_CLK_SRC 193
205+#define GCC_GFX3D_OXILI_CLK 194
206+#define GCC_GFX3D_BIMC_CLK 195
207+#define GCC_GFX3D_OXILI_AHB_CLK 196
208+#define GCC_GFX3D_OXILI_AON_CLK 197
209+#define GCC_GFX3D_OXILI_GMEM_CLK 198
210+#define GCC_GFX3D_OXILI_TIMER_CLK 199
211+#define GCC_GFX3D_TBU0_CLK 200
212+#define GCC_GFX3D_TBU1_CLK 201
213+#define GCC_GFX3D_TCU_CLK 202
214+#define GCC_GFX3D_GTCU_AHB_CLK 203
215+
216+/* GCC block resets */
217+#define RST_CAMSS_MICRO_BCR 0
218+#define RST_USB_HS_BCR 1
219+#define RST_QUSB2_PHY_BCR 2
220+#define RST_USB2_HS_PHY_ONLY_BCR 3
221+#define RST_USB_HS_PHY_CFG_AHB_BCR 4
222+#define RST_USB_FS_BCR 5
223+#define RST_CAMSS_CSI1PIX_BCR 6
224+#define RST_CAMSS_CSI_VFE1_BCR 7
225+#define RST_CAMSS_VFE1_BCR 8
226+#define RST_CAMSS_CPP_BCR 9
227+
228+/* GDSCs */
229+#define VENUS_GDSC 0
230+#define VENUS_CORE0_GDSC 1
231+#define VENUS_CORE1_GDSC 2
232+#define MDSS_GDSC 3
233+#define JPEG_GDSC 4
234+#define VFE0_GDSC 5
235+#define VFE1_GDSC 6
236+#define CPP_GDSC 7
237+#define OXILI_GX_GDSC 8
238+#define OXILI_CX_GDSC 9
239+
240+#endif /* _DT_BINDINGS_CLK_MSM_GCC_8976_H */
include/dt-bindings/clock/sun20i-d1-ccu.h+156−0
@@ -0,0 +1,156 @@
1+/* SPDX-License-Identifier: (GPL-2.0+ or MIT) */
2+/*
3+ * Copyright (C) 2020 huangzhenwei@allwinnertech.com
4+ * Copyright (C) 2021 Samuel Holland <samuel@sholland.org>
5+ */
6+
7+#ifndef _DT_BINDINGS_CLK_SUN20I_D1_CCU_H_
8+#define _DT_BINDINGS_CLK_SUN20I_D1_CCU_H_
9+
10+#define CLK_PLL_CPUX 0
11+#define CLK_PLL_DDR0 1
12+#define CLK_PLL_PERIPH0_4X 2
13+#define CLK_PLL_PERIPH0_2X 3
14+#define CLK_PLL_PERIPH0_800M 4
15+#define CLK_PLL_PERIPH0 5
16+#define CLK_PLL_PERIPH0_DIV3 6
17+#define CLK_PLL_VIDEO0_4X 7
18+#define CLK_PLL_VIDEO0_2X 8
19+#define CLK_PLL_VIDEO0 9
20+#define CLK_PLL_VIDEO1_4X 10
21+#define CLK_PLL_VIDEO1_2X 11
22+#define CLK_PLL_VIDEO1 12
23+#define CLK_PLL_VE 13
24+#define CLK_PLL_AUDIO0_4X 14
25+#define CLK_PLL_AUDIO0_2X 15
26+#define CLK_PLL_AUDIO0 16
27+#define CLK_PLL_AUDIO1 17
28+#define CLK_PLL_AUDIO1_DIV2 18
29+#define CLK_PLL_AUDIO1_DIV5 19
30+#define CLK_CPUX 20
31+#define CLK_CPUX_AXI 21
32+#define CLK_CPUX_APB 22
33+#define CLK_PSI_AHB 23
34+#define CLK_APB0 24
35+#define CLK_APB1 25
36+#define CLK_MBUS 26
37+#define CLK_DE 27
38+#define CLK_BUS_DE 28
39+#define CLK_DI 29
40+#define CLK_BUS_DI 30
41+#define CLK_G2D 31
42+#define CLK_BUS_G2D 32
43+#define CLK_CE 33
44+#define CLK_BUS_CE 34
45+#define CLK_VE 35
46+#define CLK_BUS_VE 36
47+#define CLK_BUS_DMA 37
48+#define CLK_BUS_MSGBOX0 38
49+#define CLK_BUS_MSGBOX1 39
50+#define CLK_BUS_MSGBOX2 40
51+#define CLK_BUS_SPINLOCK 41
52+#define CLK_BUS_HSTIMER 42
53+#define CLK_AVS 43
54+#define CLK_BUS_DBG 44
55+#define CLK_BUS_PWM 45
56+#define CLK_BUS_IOMMU 46
57+#define CLK_DRAM 47
58+#define CLK_MBUS_DMA 48
59+#define CLK_MBUS_VE 49
60+#define CLK_MBUS_CE 50
61+#define CLK_MBUS_TVIN 51
62+#define CLK_MBUS_CSI 52
63+#define CLK_MBUS_G2D 53
64+#define CLK_MBUS_RISCV 54
65+#define CLK_BUS_DRAM 55
66+#define CLK_MMC0 56
67+#define CLK_MMC1 57
68+#define CLK_MMC2 58
69+#define CLK_BUS_MMC0 59
70+#define CLK_BUS_MMC1 60
71+#define CLK_BUS_MMC2 61
72+#define CLK_BUS_UART0 62
73+#define CLK_BUS_UART1 63
74+#define CLK_BUS_UART2 64
75+#define CLK_BUS_UART3 65
76+#define CLK_BUS_UART4 66
77+#define CLK_BUS_UART5 67
78+#define CLK_BUS_I2C0 68
79+#define CLK_BUS_I2C1 69
80+#define CLK_BUS_I2C2 70
81+#define CLK_BUS_I2C3 71
82+#define CLK_SPI0 72
83+#define CLK_SPI1 73
84+#define CLK_BUS_SPI0 74
85+#define CLK_BUS_SPI1 75
86+#define CLK_EMAC_25M 76
87+#define CLK_BUS_EMAC 77
88+#define CLK_IR_TX 78
89+#define CLK_BUS_IR_TX 79
90+#define CLK_BUS_GPADC 80
91+#define CLK_BUS_THS 81
92+#define CLK_I2S0 82
93+#define CLK_I2S1 83
94+#define CLK_I2S2 84
95+#define CLK_I2S2_ASRC 85
96+#define CLK_BUS_I2S0 86
97+#define CLK_BUS_I2S1 87
98+#define CLK_BUS_I2S2 88
99+#define CLK_SPDIF_TX 89
100+#define CLK_SPDIF_RX 90
101+#define CLK_BUS_SPDIF 91
102+#define CLK_DMIC 92
103+#define CLK_BUS_DMIC 93
104+#define CLK_AUDIO_DAC 94
105+#define CLK_AUDIO_ADC 95
106+#define CLK_BUS_AUDIO 96
107+#define CLK_USB_OHCI0 97
108+#define CLK_USB_OHCI1 98
109+#define CLK_BUS_OHCI0 99
110+#define CLK_BUS_OHCI1 100
111+#define CLK_BUS_EHCI0 101
112+#define CLK_BUS_EHCI1 102
113+#define CLK_BUS_OTG 103
114+#define CLK_BUS_LRADC 104
115+#define CLK_BUS_DPSS_TOP 105
116+#define CLK_HDMI_24M 106
117+#define CLK_HDMI_CEC_32K 107
118+#define CLK_HDMI_CEC 108
119+#define CLK_BUS_HDMI 109
120+#define CLK_MIPI_DSI 110
121+#define CLK_BUS_MIPI_DSI 111
122+#define CLK_TCON_LCD0 112
123+#define CLK_BUS_TCON_LCD0 113
124+#define CLK_TCON_TV 114
125+#define CLK_BUS_TCON_TV 115
126+#define CLK_TVE 116
127+#define CLK_BUS_TVE_TOP 117
128+#define CLK_BUS_TVE 118
129+#define CLK_TVD 119
130+#define CLK_BUS_TVD_TOP 120
131+#define CLK_BUS_TVD 121
132+#define CLK_LEDC 122
133+#define CLK_BUS_LEDC 123
134+#define CLK_CSI_TOP 124
135+#define CLK_CSI_MCLK 125
136+#define CLK_BUS_CSI 126
137+#define CLK_TPADC 127
138+#define CLK_BUS_TPADC 128
139+#define CLK_BUS_TZMA 129
140+#define CLK_DSP 130
141+#define CLK_BUS_DSP_CFG 131
142+#define CLK_RISCV 132
143+#define CLK_RISCV_AXI 133
144+#define CLK_BUS_RISCV_CFG 134
145+#define CLK_FANOUT_24M 135
146+#define CLK_FANOUT_12M 136
147+#define CLK_FANOUT_16M 137
148+#define CLK_FANOUT_25M 138
149+#define CLK_FANOUT_32K 139
150+#define CLK_FANOUT_27M 140
151+#define CLK_FANOUT_PCLK 141
152+#define CLK_FANOUT0 142
153+#define CLK_FANOUT1 143
154+#define CLK_FANOUT2 144
155+
156+#endif /* _DT_BINDINGS_CLK_SUN20I_D1_CCU_H_ */
include/dt-bindings/clock/sun20i-d1-r-ccu.h+19−0
@@ -0,0 +1,19 @@
1+/* SPDX-License-Identifier: (GPL-2.0+ or MIT) */
2+/*
3+ * Copyright (C) 2021 Samuel Holland <samuel@sholland.org>
4+ */
5+
6+#ifndef _DT_BINDINGS_CLK_SUN20I_D1_R_CCU_H_
7+#define _DT_BINDINGS_CLK_SUN20I_D1_R_CCU_H_
8+
9+#define CLK_R_AHB 0
10+
11+#define CLK_BUS_R_TIMER 2
12+#define CLK_BUS_R_TWD 3
13+#define CLK_BUS_R_PPU 4
14+#define CLK_R_IR_RX 5
15+#define CLK_BUS_R_IR_RX 6
16+#define CLK_BUS_R_RTC 7
17+#define CLK_BUS_R_CPUCFG 8
18+
19+#endif /* _DT_BINDINGS_CLK_SUN20I_D1_R_CCU_H_ */
include/dt-bindings/clock/toshiba,tmpv770x.h+181−0
@@ -0,0 +1,181 @@
1+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
2+
3+#ifndef _DT_BINDINGS_CLOCK_TOSHIBA_TMPV770X_H_
4+#define _DT_BINDINGS_CLOCK_TOSHIBA_TMPV770X_H_
5+
6+/* PLL */
7+#define TMPV770X_PLL_PIPLL0 0
8+#define TMPV770X_PLL_PIPLL1 1
9+#define TMPV770X_PLL_PIDNNPLL 2
10+#define TMPV770X_PLL_PIETHERPLL 3
11+#define TMPV770X_PLL_PIDDRCPLL 4
12+#define TMPV770X_PLL_PIVOIFPLL 5
13+#define TMPV770X_PLL_PIIMGERPLL 6
14+#define TMPV770X_NR_PLL 7
15+
16+/* Clocks */
17+#define TMPV770X_CLK_PIPLL1_DIV1 0
18+#define TMPV770X_CLK_PIPLL1_DIV2 1
19+#define TMPV770X_CLK_PIPLL1_DIV4 2
20+#define TMPV770X_CLK_PIDNNPLL_DIV1 3
21+#define TMPV770X_CLK_DDRC_PHY_PLL0 4
22+#define TMPV770X_CLK_DDRC_PHY_PLL1 5
23+#define TMPV770X_CLK_D_PHYPLL 6
24+#define TMPV770X_CLK_PHY_PCIEPLL 7
25+#define TMPV770X_CLK_CA53CL0 8
26+#define TMPV770X_CLK_CA53CL1 9
27+#define TMPV770X_CLK_PISDMAC 10
28+#define TMPV770X_CLK_PIPDMAC0 11
29+#define TMPV770X_CLK_PIPDMAC1 12
30+#define TMPV770X_CLK_PIWRAM 13
31+#define TMPV770X_CLK_DDRC0 14
32+#define TMPV770X_CLK_DDRC0_SCLK 15
33+#define TMPV770X_CLK_DDRC0_NCLK 16
34+#define TMPV770X_CLK_DDRC0_MCLK 17
35+#define TMPV770X_CLK_DDRC0_APBCLK 18
36+#define TMPV770X_CLK_DDRC1 19
37+#define TMPV770X_CLK_DDRC1_SCLK 20
38+#define TMPV770X_CLK_DDRC1_NCLK 21
39+#define TMPV770X_CLK_DDRC1_MCLK 22
40+#define TMPV770X_CLK_DDRC1_APBCLK 23
41+#define TMPV770X_CLK_HOX 24
42+#define TMPV770X_CLK_PCIE_MSTR 25
43+#define TMPV770X_CLK_PCIE_AUX 26
44+#define TMPV770X_CLK_PIINTC 27
45+#define TMPV770X_CLK_PIETHER_BUS 28
46+#define TMPV770X_CLK_PISPI0 29
47+#define TMPV770X_CLK_PISPI1 30
48+#define TMPV770X_CLK_PISPI2 31
49+#define TMPV770X_CLK_PISPI3 32
50+#define TMPV770X_CLK_PISPI4 33
51+#define TMPV770X_CLK_PISPI5 34
52+#define TMPV770X_CLK_PISPI6 35
53+#define TMPV770X_CLK_PIUART0 36
54+#define TMPV770X_CLK_PIUART1 37
55+#define TMPV770X_CLK_PIUART2 38
56+#define TMPV770X_CLK_PIUART3 39
57+#define TMPV770X_CLK_PII2C0 40
58+#define TMPV770X_CLK_PII2C1 41
59+#define TMPV770X_CLK_PII2C2 42
60+#define TMPV770X_CLK_PII2C3 43
61+#define TMPV770X_CLK_PII2C4 44
62+#define TMPV770X_CLK_PII2C5 45
63+#define TMPV770X_CLK_PII2C6 46
64+#define TMPV770X_CLK_PII2C7 47
65+#define TMPV770X_CLK_PII2C8 48
66+#define TMPV770X_CLK_PIGPIO 49
67+#define TMPV770X_CLK_PIPGM 50
68+#define TMPV770X_CLK_PIPCMIF 51
69+#define TMPV770X_CLK_PIPCMIF_AUDIO_O 52
70+#define TMPV770X_CLK_PIPCMIF_AUDIO_I 53
71+#define TMPV770X_CLK_PICMPT0 54
72+#define TMPV770X_CLK_PICMPT1 55
73+#define TMPV770X_CLK_PITSC 56
74+#define TMPV770X_CLK_PIUWDT 57
75+#define TMPV770X_CLK_PISWDT 58
76+#define TMPV770X_CLK_WDTCLK 59
77+#define TMPV770X_CLK_PISUBUS_150M 60
78+#define TMPV770X_CLK_PISUBUS_300M 61
79+#define TMPV770X_CLK_PIPMU 62
80+#define TMPV770X_CLK_PIGPMU 63
81+#define TMPV770X_CLK_PITMU 64
82+#define TMPV770X_CLK_WRCK 65
83+#define TMPV770X_CLK_PIEMM 66
84+#define TMPV770X_CLK_PIMISC 67
85+#define TMPV770X_CLK_PIGCOMM 68
86+#define TMPV770X_CLK_PIDCOMM 69
87+#define TMPV770X_CLK_PICKMON 70
88+#define TMPV770X_CLK_PIMBUS 71
89+#define TMPV770X_CLK_SBUSCLK 72
90+#define TMPV770X_CLK_DDR0_APBCLKCLK 73
91+#define TMPV770X_CLK_DDR1_APBCLKCLK 74
92+#define TMPV770X_CLK_DSP0_PBCLK 75
93+#define TMPV770X_CLK_DSP1_PBCLK 76
94+#define TMPV770X_CLK_DSP2_PBCLK 77
95+#define TMPV770X_CLK_DSP3_PBCLK 78
96+#define TMPV770X_CLK_DSVIIF0_APBCLK 79
97+#define TMPV770X_CLK_VIIF0_APBCLK 80
98+#define TMPV770X_CLK_VIIF0_CFGCLK 81
99+#define TMPV770X_CLK_VIIF1_APBCLK 82
100+#define TMPV770X_CLK_VIIF1_CFGCLK 83
101+#define TMPV770X_CLK_VIIF2_APBCLK 84
102+#define TMPV770X_CLK_VIIF2_CFGCLK 85
103+#define TMPV770X_CLK_VIIF3_APBCLK 86
104+#define TMPV770X_CLK_VIIF3_CFGCLK 87
105+#define TMPV770X_CLK_VIIF4_APBCLK 88
106+#define TMPV770X_CLK_VIIF4_CFGCLK 89
107+#define TMPV770X_CLK_VIIF5_APBCLK 90
108+#define TMPV770X_CLK_VIIF5_CFGCLK 91
109+#define TMPV770X_CLK_VOIF_SBUSCLK 92
110+#define TMPV770X_CLK_VOIF_PROCCLK 93
111+#define TMPV770X_CLK_VOIF_DPHYCFGCLK 94
112+#define TMPV770X_CLK_DNN0 95
113+#define TMPV770X_CLK_STMAT 96
114+#define TMPV770X_CLK_HWA0 97
115+#define TMPV770X_CLK_AFFINE0 98
116+#define TMPV770X_CLK_HAMAT 99
117+#define TMPV770X_CLK_SMLDB 100
118+#define TMPV770X_CLK_HWA0_ASYNC 101
119+#define TMPV770X_CLK_HWA2 102
120+#define TMPV770X_CLK_FLMAT 103
121+#define TMPV770X_CLK_PYRAMID 104
122+#define TMPV770X_CLK_HWA2_ASYNC 105
123+#define TMPV770X_CLK_DSP0 106
124+#define TMPV770X_CLK_VIIFBS0 107
125+#define TMPV770X_CLK_VIIFBS0_L2ISP 108
126+#define TMPV770X_CLK_VIIFBS0_L1ISP 109
127+#define TMPV770X_CLK_VIIFBS0_PROC 110
128+#define TMPV770X_CLK_VIIFBS1 111
129+#define TMPV770X_CLK_VIIFBS2 112
130+#define TMPV770X_CLK_VIIFOP_MBUS 113
131+#define TMPV770X_CLK_VIIFOP0_PROC 114
132+#define TMPV770X_CLK_PIETHER_2P5M 115
133+#define TMPV770X_CLK_PIETHER_25M 116
134+#define TMPV770X_CLK_PIETHER_50M 117
135+#define TMPV770X_CLK_PIETHER_125M 118
136+#define TMPV770X_CLK_VOIF0_DPHYCFG 119
137+#define TMPV770X_CLK_VOIF0_PROC 120
138+#define TMPV770X_CLK_VOIF0_SBUS 121
139+#define TMPV770X_CLK_VOIF0_DSIREF 122
140+#define TMPV770X_CLK_VOIF0_PIXEL 123
141+#define TMPV770X_CLK_PIREFCLK 124
142+#define TMPV770X_CLK_SBUS 125
143+#define TMPV770X_CLK_BUSLCK 126
144+#define TMPV770X_NR_CLK 127
145+
146+/* Reset */
147+#define TMPV770X_RESET_PIETHER_2P5M 0
148+#define TMPV770X_RESET_PIETHER_25M 1
149+#define TMPV770X_RESET_PIETHER_50M 2
150+#define TMPV770X_RESET_PIETHER_125M 3
151+#define TMPV770X_RESET_HOX 4
152+#define TMPV770X_RESET_PCIE_MSTR 5
153+#define TMPV770X_RESET_PCIE_AUX 6
154+#define TMPV770X_RESET_PIINTC 7
155+#define TMPV770X_RESET_PIETHER_BUS 8
156+#define TMPV770X_RESET_PISPI0 9
157+#define TMPV770X_RESET_PISPI1 10
158+#define TMPV770X_RESET_PISPI2 11
159+#define TMPV770X_RESET_PISPI3 12
160+#define TMPV770X_RESET_PISPI4 13
161+#define TMPV770X_RESET_PISPI5 14
162+#define TMPV770X_RESET_PISPI6 15
163+#define TMPV770X_RESET_PIUART0 16
164+#define TMPV770X_RESET_PIUART1 17
165+#define TMPV770X_RESET_PIUART2 18
166+#define TMPV770X_RESET_PIUART3 19
167+#define TMPV770X_RESET_PII2C0 20
168+#define TMPV770X_RESET_PII2C1 21
169+#define TMPV770X_RESET_PII2C2 22
170+#define TMPV770X_RESET_PII2C3 23
171+#define TMPV770X_RESET_PII2C4 24
172+#define TMPV770X_RESET_PII2C5 25
173+#define TMPV770X_RESET_PII2C6 26
174+#define TMPV770X_RESET_PII2C7 27
175+#define TMPV770X_RESET_PII2C8 28
176+#define TMPV770X_RESET_PIPCMIF 29
177+#define TMPV770X_RESET_PICKMON 30
178+#define TMPV770X_RESET_SBUSCLK 31
179+#define TMPV770X_NR_RESET 32
180+
181+#endif /*_DT_BINDINGS_CLOCK_TOSHIBA_TMPV770X_H_ */
include/dt-bindings/reset/sun20i-d1-ccu.h+77−0
@@ -0,0 +1,77 @@
1+/* SPDX-License-Identifier: (GPL-2.0+ or MIT) */
2+/*
3+ * Copyright (c) 2020 huangzhenwei@allwinnertech.com
4+ * Copyright (C) 2021 Samuel Holland <samuel@sholland.org>
5+ */
6+
7+#ifndef _DT_BINDINGS_RST_SUN20I_D1_CCU_H_
8+#define _DT_BINDINGS_RST_SUN20I_D1_CCU_H_
9+
10+#define RST_MBUS 0
11+#define RST_BUS_DE 1
12+#define RST_BUS_DI 2
13+#define RST_BUS_G2D 3
14+#define RST_BUS_CE 4
15+#define RST_BUS_VE 5
16+#define RST_BUS_DMA 6
17+#define RST_BUS_MSGBOX0 7
18+#define RST_BUS_MSGBOX1 8
19+#define RST_BUS_MSGBOX2 9
20+#define RST_BUS_SPINLOCK 10
21+#define RST_BUS_HSTIMER 11
22+#define RST_BUS_DBG 12
23+#define RST_BUS_PWM 13
24+#define RST_BUS_DRAM 14
25+#define RST_BUS_MMC0 15
26+#define RST_BUS_MMC1 16
27+#define RST_BUS_MMC2 17
28+#define RST_BUS_UART0 18
29+#define RST_BUS_UART1 19
30+#define RST_BUS_UART2 20
31+#define RST_BUS_UART3 21
32+#define RST_BUS_UART4 22
33+#define RST_BUS_UART5 23
34+#define RST_BUS_I2C0 24
35+#define RST_BUS_I2C1 25
36+#define RST_BUS_I2C2 26
37+#define RST_BUS_I2C3 27
38+#define RST_BUS_SPI0 28
39+#define RST_BUS_SPI1 29
40+#define RST_BUS_EMAC 30
41+#define RST_BUS_IR_TX 31
42+#define RST_BUS_GPADC 32
43+#define RST_BUS_THS 33
44+#define RST_BUS_I2S0 34
45+#define RST_BUS_I2S1 35
46+#define RST_BUS_I2S2 36
47+#define RST_BUS_SPDIF 37
48+#define RST_BUS_DMIC 38
49+#define RST_BUS_AUDIO 39
50+#define RST_USB_PHY0 40
51+#define RST_USB_PHY1 41
52+#define RST_BUS_OHCI0 42
53+#define RST_BUS_OHCI1 43
54+#define RST_BUS_EHCI0 44
55+#define RST_BUS_EHCI1 45
56+#define RST_BUS_OTG 46
57+#define RST_BUS_LRADC 47
58+#define RST_BUS_DPSS_TOP 48
59+#define RST_BUS_HDMI_SUB 49
60+#define RST_BUS_HDMI_MAIN 50
61+#define RST_BUS_MIPI_DSI 51
62+#define RST_BUS_TCON_LCD0 52
63+#define RST_BUS_TCON_TV 53
64+#define RST_BUS_LVDS0 54
65+#define RST_BUS_TVE 55
66+#define RST_BUS_TVE_TOP 56
67+#define RST_BUS_TVD 57
68+#define RST_BUS_TVD_TOP 58
69+#define RST_BUS_LEDC 59
70+#define RST_BUS_CSI 60
71+#define RST_BUS_TPADC 61
72+#define RST_DSP 62
73+#define RST_BUS_DSP_CFG 63
74+#define RST_BUS_DSP_DBG 64
75+#define RST_BUS_RISCV_CFG 65
76+
77+#endif /* _DT_BINDINGS_RST_SUN20I_D1_CCU_H_ */
include/dt-bindings/reset/sun20i-d1-r-ccu.h+16−0
@@ -0,0 +1,16 @@
1+/* SPDX-License-Identifier: (GPL-2.0+ or MIT) */
2+/*
3+ * Copyright (C) 2021 Samuel Holland <samuel@sholland.org>
4+ */
5+
6+#ifndef _DT_BINDINGS_RST_SUN20I_D1_R_CCU_H_
7+#define _DT_BINDINGS_RST_SUN20I_D1_R_CCU_H_
8+
9+#define RST_BUS_R_TIMER 0
10+#define RST_BUS_R_TWD 1
11+#define RST_BUS_R_PPU 2
12+#define RST_BUS_R_IR_RX 3
13+#define RST_BUS_R_RTC 4
14+#define RST_BUS_R_CPUCFG 5
15+
16+#endif /* _DT_BINDINGS_RST_SUN20I_D1_R_CCU_H_ */
include/dt-bindings/reset/toshiba,tmpv770x.h+41−0
@@ -0,0 +1,41 @@
1+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
2+
3+#ifndef _DT_BINDINGS_RESET_TOSHIBA_TMPV770X_H_
4+#define _DT_BINDINGS_RESET_TOSHIBA_TMPV770X_H_
5+
6+/* Reset */
7+#define TMPV770X_RESET_PIETHER_2P5M 0
8+#define TMPV770X_RESET_PIETHER_25M 1
9+#define TMPV770X_RESET_PIETHER_50M 2
10+#define TMPV770X_RESET_PIETHER_125M 3
11+#define TMPV770X_RESET_HOX 4
12+#define TMPV770X_RESET_PCIE_MSTR 5
13+#define TMPV770X_RESET_PCIE_AUX 6
14+#define TMPV770X_RESET_PIINTC 7
15+#define TMPV770X_RESET_PIETHER_BUS 8
16+#define TMPV770X_RESET_PISPI0 9
17+#define TMPV770X_RESET_PISPI1 10
18+#define TMPV770X_RESET_PISPI2 11
19+#define TMPV770X_RESET_PISPI3 12
20+#define TMPV770X_RESET_PISPI4 13
21+#define TMPV770X_RESET_PISPI5 14
22+#define TMPV770X_RESET_PISPI6 15
23+#define TMPV770X_RESET_PIUART0 16
24+#define TMPV770X_RESET_PIUART1 17
25+#define TMPV770X_RESET_PIUART2 18
26+#define TMPV770X_RESET_PIUART3 19
27+#define TMPV770X_RESET_PII2C0 20
28+#define TMPV770X_RESET_PII2C1 21
29+#define TMPV770X_RESET_PII2C2 22
30+#define TMPV770X_RESET_PII2C3 23
31+#define TMPV770X_RESET_PII2C4 24
32+#define TMPV770X_RESET_PII2C5 25
33+#define TMPV770X_RESET_PII2C6 26
34+#define TMPV770X_RESET_PII2C7 27
35+#define TMPV770X_RESET_PII2C8 28
36+#define TMPV770X_RESET_PIPCMIF 29
37+#define TMPV770X_RESET_PICKMON 30
38+#define TMPV770X_RESET_SBUSCLK 31
39+#define TMPV770X_NR_RESET 32
40+
41+#endif /*_DT_BINDINGS_RESET_TOSHIBA_TMPV770X_H_ */
include/linux/clk-provider.h+23−0
@@ -490,6 +490,13 @@ struct clk_hw *__clk_hw_register_gate(struct device *dev, · 489 unmodified lines
490490 unsigned long flags,
491491 void __iomem *reg, u8 bit_idx,
492492 u8 clk_gate_flags, spinlock_t *lock);
493+struct clk_hw *__devm_clk_hw_register_gate(struct device *dev,
494+ struct device_node *np, const char *name,
495+ const char *parent_name, const struct clk_hw *parent_hw,
496+ const struct clk_parent_data *parent_data,
497+ unsigned long flags,
498+ void __iomem *reg, u8 bit_idx,
499+ u8 clk_gate_flags, spinlock_t *lock);
493500 struct clk *clk_register_gate(struct device *dev, const char *name,
494501 const char *parent_name, unsigned long flags,
495502 void __iomem *reg, u8 bit_idx,
@@ -544,6 +551,22 @@ struct clk *clk_register_gate(struct device *dev, const char *name, · 48 unmodified lines
544551 __clk_hw_register_gate((dev), NULL, (name), NULL, NULL, (parent_data), \
545552 (flags), (reg), (bit_idx), \
546553 (clk_gate_flags), (lock))
554+/**
555+ * devm_clk_hw_register_gate - register a gate clock with the clock framework
556+ * @dev: device that is registering this clock
557+ * @name: name of this clock
558+ * @parent_name: name of this clock's parent
559+ * @flags: framework-specific flags for this clock
560+ * @reg: register address to control gating of this clock
561+ * @bit_idx: which bit in the register controls gating of this clock
562+ * @clk_gate_flags: gate-specific flags for this clock
563+ * @lock: shared register lock for this clock
564+ */
565+#define devm_clk_hw_register_gate(dev, name, parent_name, flags, reg, bit_idx,\
566+ clk_gate_flags, lock) \
567+ __devm_clk_hw_register_gate((dev), NULL, (name), (parent_name), NULL, \
568+ NULL, (flags), (reg), (bit_idx), \
569+ (clk_gate_flags), (lock))
547570 void clk_unregister_gate(struct clk *clk);
548571 void clk_hw_unregister_gate(struct clk_hw *hw);
549572 int clk_gate_is_enabled(struct clk_hw *hw);
include/linux/clk/sunxi-ng.h+0−15
@@ -6,22 +6,7 @@ · 5 unmodified lines
66 #ifndef _LINUX_CLK_SUNXI_NG_H_
77 #define _LINUX_CLK_SUNXI_NG_H_
88
9−#include <linux/errno.h>
10−
11−#ifdef CONFIG_SUNXI_CCU
129 int sunxi_ccu_set_mmc_timing_mode(struct clk *clk, bool new_mode);
1310 int sunxi_ccu_get_mmc_timing_mode(struct clk *clk);
14−#else
15−static inline int sunxi_ccu_set_mmc_timing_mode(struct clk *clk,
16− bool new_mode)
17−{
18− return -ENOTSUPP;
19−}
20−
21−static inline int sunxi_ccu_get_mmc_timing_mode(struct clk *clk)
22−{
23− return -ENOTSUPP;
24−}
25−#endif
2611
2712 #endif
include/linux/mfd/tps68470.h+11−0
@@ -75,6 +75,17 @@ · 74 unmodified lines
7575 #define TPS68470_CLKCFG1_MODE_A_MASK GENMASK(1, 0)
7676 #define TPS68470_CLKCFG1_MODE_B_MASK GENMASK(3, 2)
7777
78+#define TPS68470_CLKCFG2_DRV_STR_2MA 0x05
79+#define TPS68470_PLL_OUTPUT_ENABLE 0x02
80+#define TPS68470_CLK_SRC_XTAL BIT(0)
81+#define TPS68470_PLLSWR_DEFAULT GENMASK(1, 0)
82+#define TPS68470_OSC_EXT_CAP_DEFAULT 0x05
83+
84+#define TPS68470_OUTPUT_A_SHIFT 0x00
85+#define TPS68470_OUTPUT_B_SHIFT 0x02
86+#define TPS68470_CLK_SRC_SHIFT GENMASK(2, 0)
87+#define TPS68470_OSC_EXT_CAP_SHIFT BIT(2)
88+
7889 #define TPS68470_GPIO_CTL_REG_A(x) (TPS68470_REG_GPCTL0A + (x) * 2)
7990 #define TPS68470_GPIO_CTL_REG_B(x) (TPS68470_REG_GPCTL0B + (x) * 2)
8091 #define TPS68470_GPIO_MODE_MASK GENMASK(1, 0)
include/linux/platform_data/clk-fch.h+1−1
@@ -12,7 +12,7 @@ · 11 unmodified lines
1212
1313 struct fch_clk_data {
1414 void __iomem *base;
15− u32 is_rv;
15+ char *name;
1616 };
1717
1818 #endif /* __CLK_FCH_H */

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