Pull dmaengine updates from Vinod Koul: - Add support in dmaengine core to do device node checks for DT devices and update bunch of drivers to use that and remove open coding from drivers - New driver/driver support for new hardware, namely: - MediaTek UART APDMA - Freescale i.mx7ulp edma2 - Synopsys eDMA IP core version 0 - Allwinner H6 DMA - Updates to axi-dma and support for interleaved cyclic transfers - Greg's debugfs return value check removals on drivers - Updates to stm32-dma, hsu, dw, pl330, tegra drivers * tag 'dmaengine-5.3-rc1' of git://git.infradead.org/users/vkoul/slave-dma: (68 commits) dmaengine: Revert "dmaengine: fsl-edma: add i.mx7ulp edma2 version support" dmaengine: at_xdmac: check for non-empty xfers_list before invoking callback Documentation: dmaengine: clean up description of dmatest usage dmaengine: tegra210-adma: remove PM_CLK dependency dmaengine: fsl-edma: add i.mx7ulp edma2 version support dt-bindings: dma: fsl-edma: add new i.mx7ulp-edma dmaengine: fsl-edma-common: version check for v2 instead dmaengine: fsl-edma-common: move dmamux register to another single function dmaengine: fsl-edma: add drvdata for fsl-edma dmaengine: Revert "dmaengine: fsl-edma: support little endian for edma driver" dmaengine: rcar-dmac: Reject zero-length slave DMA requests dmaengine: dw: Enable iDMA 32-bit on Intel Elkhart Lake dmaengine: dw-edma: fix semicolon.cocci warnings dmaengine: sh: usb-dmac: Use [] to denote a flexible array member dmaengine: dmatest: timeout value of -1 should specify infinite wait dmaengine: dw: Distinguish ->remove() between DW and iDMA 32-bit dmaengine: fsl-edma: support little endian for edma driver dmaengine: hsu: Revert "set HSU_CH_MTSR to memory width" dmagengine: pl330: add code to get reset property dt-bindings: pl330: document the optional resets property ...
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| @@ -0,0 +1,47 @@ | ||
| 1 | +/* SPDX-License-Identifier: GPL-2.0 */ | |
| 2 | +/* | |
| 3 | + * Copyright (c) 2018-2019 Synopsys, Inc. and/or its affiliates. | |
| 4 | + * Synopsys DesignWare eDMA core driver | |
| 5 | + * | |
| 6 | + * Author: Gustavo Pimentel <gustavo.pimentel@synopsys.com> | |
| 7 | + */ | |
| 8 | + | |
| 9 | +#ifndef _DW_EDMA_H | |
| 10 | +#define _DW_EDMA_H | |
| 11 | + | |
| 12 | +#include <linux/device.h> | |
| 13 | +#include <linux/dmaengine.h> | |
| 14 | + | |
| 15 | +struct dw_edma; | |
| 16 | + | |
| 17 | +/** | |
| 18 | + * struct dw_edma_chip - representation of DesignWare eDMA controller hardware | |
| 19 | + * @dev: struct device of the eDMA controller | |
| 20 | + * @id: instance ID | |
| 21 | + * @irq: irq line | |
| 22 | + * @dw: struct dw_edma that is filed by dw_edma_probe() | |
| 23 | + */ | |
| 24 | +struct dw_edma_chip { | |
| 25 | + struct device *dev; | |
| 26 | + int id; | |
| 27 | + int irq; | |
| 28 | + struct dw_edma *dw; | |
| 29 | +}; | |
| 30 | + | |
| 31 | +/* Export to the platform drivers */ | |
| 32 | +#if IS_ENABLED(CONFIG_DW_EDMA) | |
| 33 | +int dw_edma_probe(struct dw_edma_chip *chip); | |
| 34 | +int dw_edma_remove(struct dw_edma_chip *chip); | |
| 35 | +#else | |
| 36 | +static inline int dw_edma_probe(struct dw_edma_chip *chip) | |
| 37 | +{ | |
| 38 | + return -ENODEV; | |
| 39 | +} | |
| 40 | + | |
| 41 | +static inline int dw_edma_remove(struct dw_edma_chip *chip) | |
| 42 | +{ | |
| 43 | + return 0; | |
| 44 | +} | |
| 45 | +#endif /* CONFIG_DW_EDMA */ | |
| 46 | + | |
| 47 | +#endif /* _DW_EDMA_H */ | |
| @@ -1302,7 +1302,8 @@ enum dma_status dma_sync_wait(struct dma_chan *chan, dma_cookie_t cookie); · 1301 unmodified lines | ||
| 1302 | 1302 | enum dma_status dma_wait_for_async_tx(struct dma_async_tx_descriptor *tx); |
| 1303 | 1303 | void dma_issue_pending_all(void); |
| 1304 | 1304 | struct dma_chan *__dma_request_channel(const dma_cap_mask_t *mask, |
| 1305 | − dma_filter_fn fn, void *fn_param); | |
| 1305 | + dma_filter_fn fn, void *fn_param, | |
| 1306 | + struct device_node *np); | |
| 1306 | 1307 | struct dma_chan *dma_request_slave_channel(struct device *dev, const char *name); |
| 1307 | 1308 | |
| 1308 | 1309 | struct dma_chan *dma_request_chan(struct device *dev, const char *name); |
| @@ -1327,7 +1328,9 @@ static inline void dma_issue_pending_all(void) · 18 unmodified lines | ||
| 1327 | 1328 | { |
| 1328 | 1329 | } |
| 1329 | 1330 | static inline struct dma_chan *__dma_request_channel(const dma_cap_mask_t *mask, |
| 1330 | − dma_filter_fn fn, void *fn_param) | |
| 1331 | + dma_filter_fn fn, | |
| 1332 | + void *fn_param, | |
| 1333 | + struct device_node *np) | |
| 1331 | 1334 | { |
| 1332 | 1335 | return NULL; |
| 1333 | 1336 | } |
| @@ -1399,7 +1402,8 @@ void dma_async_device_unregister(struct dma_device *device); · 65 unmodified lines | ||
| 1399 | 1402 | void dma_run_dependencies(struct dma_async_tx_descriptor *tx); |
| 1400 | 1403 | struct dma_chan *dma_get_slave_channel(struct dma_chan *chan); |
| 1401 | 1404 | struct dma_chan *dma_get_any_slave_channel(struct dma_device *device); |
| 1402 | −#define dma_request_channel(mask, x, y) __dma_request_channel(&(mask), x, y) | |
| 1405 | +#define dma_request_channel(mask, x, y) \ | |
| 1406 | + __dma_request_channel(&(mask), x, y, NULL) | |
| 1403 | 1407 | #define dma_request_slave_channel_compat(mask, x, y, dev, name) \ |
| 1404 | 1408 | __dma_request_slave_channel_compat(&(mask), x, y, dev, name) |
| 1405 | 1409 | |
| @@ -1417,6 +1421,6 @@ static inline struct dma_chan · 11 unmodified lines | ||
| 1417 | 1421 | if (!fn || !fn_param) |
| 1418 | 1422 | return NULL; |
| 1419 | 1423 | |
| 1420 | − return __dma_request_channel(mask, fn, fn_param); | |
| 1424 | + return __dma_request_channel(mask, fn, fn_param, NULL); | |
| 1421 | 1425 | } |
| 1422 | 1426 | #endif /* DMAENGINE_H */ |
| @@ -0,0 +1,19 @@ | ||
| 1 | +/* SPDX-License-Identifier: GPL-2.0 */ | |
| 2 | +/* | |
| 3 | + * Analog Devices AXI common registers & definitions | |
| 4 | + * | |
| 5 | + * Copyright 2019 Analog Devices Inc. | |
| 6 | + * | |
| 7 | + * https://wiki.analog.com/resources/fpga/docs/axi_ip | |
| 8 | + * https://wiki.analog.com/resources/fpga/docs/hdl/regmap | |
| 9 | + */ | |
| 10 | + | |
| 11 | +#ifndef ADI_AXI_COMMON_H_ | |
| 12 | +#define ADI_AXI_COMMON_H_ | |
| 13 | + | |
| 14 | +#define ADI_AXI_REG_VERSION 0x0000 | |
| 15 | + | |
| 16 | +#define ADI_AXI_PCORE_VER(major, minor, patch) \ | |
| 17 | + (((major) << 16) | ((minor) << 8) | (patch)) | |
| 18 | + | |
| 19 | +#endif /* ADI_AXI_COMMON_H_ */ | |
| @@ -2367,6 +2367,7 @@ · 2366 unmodified lines | ||
| 2367 | 2367 | #define PCI_DEVICE_ID_SYNOPSYS_HAPSUSB3 0xabcd |
| 2368 | 2368 | #define PCI_DEVICE_ID_SYNOPSYS_HAPSUSB3_AXI 0xabce |
| 2369 | 2369 | #define PCI_DEVICE_ID_SYNOPSYS_HAPSUSB31 0xabcf |
| 2370 | +#define PCI_DEVICE_ID_SYNOPSYS_EDDA 0xedda | |
| 2370 | 2371 | |
| 2371 | 2372 | #define PCI_VENDOR_ID_USR 0x16ec |
| 2372 | 2373 | |
| @@ -52,7 +52,6 @@ struct imx_dma_data { · 51 unmodified lines | ||
| 52 | 52 | int dma_request2; /* secondary DMA request line */ |
| 53 | 53 | enum sdma_peripheral_type peripheral_type; |
| 54 | 54 | int priority; |
| 55 | − struct device_node *of_node; | |
| 56 | 55 | }; |
| 57 | 56 | |
| 58 | 57 | static inline int imx_dma_is_ipu(struct dma_chan *chan) |
| @@ -1,49 +0,0 @@ | ||
| 1 | −/* SPDX-License-Identifier: GPL-2.0-only */ | |
| 2 | −/* | |
| 3 | − * Header for the SUDMAC driver | |
| 4 | − * | |
| 5 | − * Copyright (C) 2013 Renesas Solutions Corp. | |
| 6 | − */ | |
| 7 | −#ifndef SUDMAC_H | |
| 8 | −#define SUDMAC_H | |
| 9 | − | |
| 10 | −#include <linux/dmaengine.h> | |
| 11 | −#include <linux/shdma-base.h> | |
| 12 | −#include <linux/types.h> | |
| 13 | − | |
| 14 | −/* Used by slave DMA clients to request DMA to/from a specific peripheral */ | |
| 15 | −struct sudmac_slave { | |
| 16 | − struct shdma_slave shdma_slave; /* Set by the platform */ | |
| 17 | −}; | |
| 18 | − | |
| 19 | −/* | |
| 20 | − * Supplied by platforms to specify, how a DMA channel has to be configured for | |
| 21 | − * a certain peripheral | |
| 22 | − */ | |
| 23 | −struct sudmac_slave_config { | |
| 24 | − int slave_id; | |
| 25 | −}; | |
| 26 | − | |
| 27 | −struct sudmac_channel { | |
| 28 | − unsigned long offset; | |
| 29 | − unsigned long config; | |
| 30 | − unsigned long wait; /* The configuable range is 0 to 3 */ | |
| 31 | − unsigned long dint_end_bit; | |
| 32 | −}; | |
| 33 | − | |
| 34 | −struct sudmac_pdata { | |
| 35 | − const struct sudmac_slave_config *slave; | |
| 36 | − int slave_num; | |
| 37 | − const struct sudmac_channel *channel; | |
| 38 | − int channel_num; | |
| 39 | −}; | |
| 40 | − | |
| 41 | −/* Definitions for the sudmac_channel.config */ | |
| 42 | −#define SUDMAC_TX_BUFFER_MODE BIT(0) | |
| 43 | −#define SUDMAC_RX_END_MODE BIT(1) | |
| 44 | − | |
| 45 | −/* Definitions for the sudmac_channel.dint_end_bit */ | |
| 46 | −#define SUDMAC_DMA_BIT_CH0 BIT(0) | |
| 47 | −#define SUDMAC_DMA_BIT_CH1 BIT(1) | |
| 48 | − | |
| 49 | −#endif | |