Merge tag 'mips_5.3' of git://git.kernel.org/pub/scm/linux/kernel/git/mips/linux

Pull MIPS updates from Paul Burton: "A light batch this time around but significant improvements for certain systems: - Removal of readq & writeq for MIPS32 kernels where they would simply BUG() anyway, allowing drivers or other code that #ifdefs on their presence to work properly. - Improvements for Ingenic JZ4740 systems, including support for the external memory controller & pinmuxing fixes for qi_lb60/NanoNote systems. - Improvements for Lantiq systems, in particular around SMP & IPIs. - DT updates for ralink/MediaTek MT7628a systems to probe & configure a bunch more devices. - Miscellaneous cleanups & build fixes" * tag 'mips_5.3' of git://git.kernel.org/pub/scm/linux/kernel/git/mips/linux: (30 commits) MIPS: fix some more fall through errors in arch/mips MIPS: perf events: handle switch statement falling through warnings mips/kprobes: Export kprobe_fault_handler() MAINTAINERS: Add myself as Ingenic SoCs maintainer MIPS: ralink: mt7628a.dtsi: Add watchdog controller DT node MIPS: ralink: mt7628a.dtsi: Add SPI controller DT node MIPS: ralink: mt7628a.dtsi: Add GPIO controller DT node MIPS: ralink: mt7628a.dtsi: Add pinctrl DT properties to the UART nodes MIPS: ralink: mt7628a.dtsi: Add pinmux DT node MIPS: ralink: mt7628a.dtsi: Add SPDX GPL-2.0 license identifier MIPS: lantiq: Add SMP support for lantiq interrupt controller MIPS: lantiq: Shorten register names, remove unused macros MIPS: lantiq: Fix bitfield masking MIPS: lantiq: Remove unused macros MIPS: lantiq: Fix attributes of of_device_id structure MIPS: lantiq: Change variables to the same type as the source MIPS: lantiq: Move macro directly to iomem function mips: Remove q-accessors from non-64bit platforms FDDI: defza: Include linux/io-64-nonatomic-lo-hi.h MIPS: configs: Remove useless UEVENT_HELPER_PATH ...

Linus Torvalds committed 7 years ago

Commit fa121bb2 parents 7d4901c e5793cd50 files · +412 −192Browse files

Unified · Split

50 files

MAINTAINERS +27 −0
arch/mips/ar7/setup.c +1 −0
arch/mips/ath79/setup.c +1 −1
arch/mips/bcm63xx/dev-flash.c +1 −0
arch/mips/boot/dts/ralink/mt7628a.dtsi +147 −1
arch/mips/cavium-octeon/executive/cvmx-pko.c +1 −1
arch/mips/configs/ar7_defconfig +0 −1
arch/mips/configs/ath25_defconfig +0 −1
arch/mips/configs/ath79_defconfig +0 −1
arch/mips/configs/bcm63xx_defconfig +0 −1
arch/mips/configs/bigsur_defconfig +0 −1
arch/mips/configs/bmips_be_defconfig +0 −1
arch/mips/configs/bmips_stb_defconfig +0 −1
arch/mips/configs/cavium_octeon_defconfig +0 −1
arch/mips/configs/ci20_defconfig +0 −1
arch/mips/configs/cobalt_defconfig +0 −1
arch/mips/configs/fuloong2e_defconfig +0 −1
arch/mips/configs/gpr_defconfig +0 −1
arch/mips/configs/ip27_defconfig +0 −1
arch/mips/configs/ip32_defconfig +0 −1
arch/mips/configs/lemote2f_defconfig +0 −2
arch/mips/configs/loongson1b_defconfig +0 −1
arch/mips/configs/loongson1c_defconfig +0 −1
arch/mips/configs/loongson3_defconfig +0 −1
arch/mips/configs/malta_defconfig +0 −1
arch/mips/configs/malta_kvm_defconfig +0 −1
arch/mips/configs/malta_kvm_guest_defconfig +0 −1
arch/mips/configs/maltaup_xpa_defconfig +0 −1
arch/mips/configs/mips_paravirt_defconfig +0 −1
arch/mips/configs/omega2p_defconfig +0 −1
arch/mips/configs/pistachio_defconfig +0 −1
arch/mips/configs/pnx8335_stb225_defconfig +0 −1
arch/mips/configs/qi_lb60_defconfig +0 −2
arch/mips/configs/rb532_defconfig +0 −1
arch/mips/configs/rt305x_defconfig +0 −1
arch/mips/configs/sb1250_swarm_defconfig +0 −1
arch/mips/configs/tb0219_defconfig +0 −1
arch/mips/configs/tb0226_defconfig +0 −1
arch/mips/configs/tb0287_defconfig +0 −1
arch/mips/configs/vocore2_defconfig +0 −1
arch/mips/configs/xway_defconfig +0 −1
arch/mips/include/asm/cpu.h +60 −65
arch/mips/include/asm/io.h +11 −0
arch/mips/include/asm/mach-ralink/pinmux.h +0 −1
arch/mips/jz4740/board-qi_lb60.c +8 −8
arch/mips/kernel/ftrace.c +12 −11
arch/mips/kernel/perf_event_mipsxx.c +15 −15
arch/mips/lantiq/irq.c +126 −51
drivers/memory/jz4780-nemc.c +1 −1
drivers/net/fddi/defza.c +1 −0

MAINTAINERS+27−0

@@ -7955,6 +7955,33 @@ L: linux-mtd@lists.infradead.org · 7954 unmodified lines
7955	7955	S: Maintained
7956	7956	F: drivers/mtd/nand/raw/ingenic/
7957	7957
	7958	+INGENIC JZ47xx SoCs
	7959	+M: Paul Cercueil <paul@crapouillou.net>
	7960	+S: Maintained
	7961	+F: arch/mips/boot/dts/ingenic/
	7962	+F: arch/mips/include/asm/mach-jz4740/
	7963	+F: arch/mips/jz4740/
	7964	+F: drivers/clk/ingenic/
	7965	+F: drivers/dma/dma-jz4780.c
	7966	+F: drivers/gpu/drm/ingenic/
	7967	+F: drivers/i2c/busses/i2c-jz4780.c
	7968	+F: drivers/iio/adc/ingenic-adc.c
	7969	+F: drivers/irqchip/irq-ingenic.c
	7970	+F: drivers/memory/jz4780-nemc.c
	7971	+F: drivers/mmc/host/jz4740_mmc.c
	7972	+F: drivers/mtd/nand/raw/ingenic/
	7973	+F: drivers/pinctrl/pinctrl-ingenic.c
	7974	+F: drivers/power/supply/ingenic-battery.c
	7975	+F: drivers/pwm/pwm-jz4740.c
	7976	+F: drivers/rtc/rtc-jz4740.c
	7977	+F: drivers/tty/serial/8250/8250_ingenic.c
	7978	+F: drivers/usb/musb/jz4740.c
	7979	+F: drivers/watchdog/jz4740_wdt.c
	7980	+F: include/dt-bindings/iio/adc/ingenic,adc.h
	7981	+F: include/linux/mfd/ingenic-tcu.h
	7982	+F: sound/soc/jz4740/
	7983	+F: sound/soc/codecs/jz47*
	7984	+
7958	7985	INOTIFY
7959	7986	M: Jan Kara <jack@suse.cz>
7960	7987	R: Amir Goldstein <amir73il@gmail.com>

arch/mips/ar7/setup.c+1−0

@@ -57,6 +57,7 @@ const char *get_system_type(void) · 56 unmodified lines
57	57	case TITAN_CHIP_1060:
58	58	return "TI AR7 (TNETV1060)";
59	59	}
	60	+ /* fall through */
60	61	default:
61	62	return "TI AR7 (unknown)";
62	63	}

arch/mips/ath79/setup.c+1−1

@@ -153,7 +153,7 @@ static void __init ath79_detect_sys_type(void) · 152 unmodified lines
153	153	case REV_ID_MAJOR_QCA9533_V2:
154	154	ver = 2;
155	155	ath79_soc_rev = 2;
156		− /* drop through */
	156	+ /* fall through */
157	157
158	158	case REV_ID_MAJOR_QCA9533:
159	159	ath79_soc = ATH79_SOC_QCA9533;

arch/mips/bcm63xx/dev-flash.c+1−0

@@ -94,6 +94,7 @@ static int __init bcm63xx_detect_flash_type(void) · 93 unmodified lines
94	94	case STRAPBUS_6368_BOOT_SEL_PARALLEL:
95	95	return BCM63XX_FLASH_TYPE_PARALLEL;
96	96	}
	97	+ /* fall through */
97	98	default:
98	99	return -EINVAL;
99	100	}

arch/mips/boot/dts/ralink/mt7628a.dtsi+147−1

@@ -1,3 +1,5 @@
	1	+// SPDX-License-Identifier: GPL-2.0
	2	+
1	3	/ {
2	4	#address-cells = <1>;
3	5	#size-cells = <1>;
@@ -36,7 +38,113 @@ · 32 unmodified lines
36	38
37	39	sysc: system-controller@0 {
38	40	compatible = "ralink,mt7620a-sysc", "syscon";
39		− reg = <0x0 0x100>;
	41	+ reg = <0x0 0x60>;
	42	+ };
	43	+
	44	+ pinmux: pinmux@60 {
	45	+ compatible = "pinctrl-single";
	46	+ reg = <0x60 0x8>;
	47	+ #address-cells = <1>;
	48	+ #size-cells = <0>;
	49	+ #pinctrl-cells = <2>;
	50	+ pinctrl-single,bit-per-mux;
	51	+ pinctrl-single,register-width = <32>;
	52	+ pinctrl-single,function-mask = <0x1>;
	53	+
	54	+ pinmux_gpio_gpio: pinmux_gpio_gpio {
	55	+ pinctrl-single,bits = <0x0 0x0 0x3>;
	56	+ };
	57	+
	58	+ pinmux_spi_cs1_cs: pinmux_spi_cs1_cs {
	59	+ pinctrl-single,bits = <0x0 0x0 0x30>;
	60	+ };
	61	+
	62	+ pinmux_i2s_gpio: pinmux_i2s_gpio {
	63	+ pinctrl-single,bits = <0x0 0x40 0xc0>;
	64	+ };
	65	+
	66	+ pinmux_uart0_uart: pinmux_uart0_uart0 {
	67	+ pinctrl-single,bits = <0x0 0x0 0x300>;
	68	+ };
	69	+
	70	+ pinmux_sdmode_sdxc: pinmux_sdmode_sdxc {
	71	+ pinctrl-single,bits = <0x0 0x0 0xc00>;
	72	+ };
	73	+
	74	+ pinmux_sdmode_gpio: pinmux_sdmode_gpio {
	75	+ pinctrl-single,bits = <0x0 0x400 0xc00>;
	76	+ };
	77	+
	78	+ pinmux_spi_spi: pinmux_spi_spi {
	79	+ pinctrl-single,bits = <0x0 0x0 0x1000>;
	80	+ };
	81	+
	82	+ pinmux_refclk_gpio: pinmux_refclk_gpio {
	83	+ pinctrl-single,bits = <0x0 0x40000 0x40000>;
	84	+ };
	85	+
	86	+ pinmux_i2c_i2c: pinmux_i2c_i2c {
	87	+ pinctrl-single,bits = <0x0 0x0 0x300000>;
	88	+ };
	89	+
	90	+ pinmux_uart1_uart: pinmux_uart1_uart1 {
	91	+ pinctrl-single,bits = <0x0 0x0 0x3000000>;
	92	+ };
	93	+
	94	+ pinmux_uart2_uart: pinmux_uart2_uart {
	95	+ pinctrl-single,bits = <0x0 0x0 0xc000000>;
	96	+ };
	97	+
	98	+ pinmux_pwm0_pwm: pinmux_pwm0_pwm {
	99	+ pinctrl-single,bits = <0x0 0x0 0x30000000>;
	100	+ };
	101	+
	102	+ pinmux_pwm0_gpio: pinmux_pwm0_gpio {
	103	+ pinctrl-single,bits = <0x0 0x10000000
	104	+ 0x30000000>;
	105	+ };
	106	+
	107	+ pinmux_pwm1_pwm: pinmux_pwm1_pwm {
	108	+ pinctrl-single,bits = <0x0 0x0 0xc0000000>;
	109	+ };
	110	+
	111	+ pinmux_pwm1_gpio: pinmux_pwm1_gpio {
	112	+ pinctrl-single,bits = <0x0 0x40000000
	113	+ 0xc0000000>;
	114	+ };
	115	+
	116	+ pinmux_p0led_an_gpio: pinmux_p0led_an_gpio {
	117	+ pinctrl-single,bits = <0x4 0x4 0xc>;
	118	+ };
	119	+
	120	+ pinmux_p1led_an_gpio: pinmux_p1led_an_gpio {
	121	+ pinctrl-single,bits = <0x4 0x10 0x30>;
	122	+ };
	123	+
	124	+ pinmux_p2led_an_gpio: pinmux_p2led_an_gpio {
	125	+ pinctrl-single,bits = <0x4 0x40 0xc0>;
	126	+ };
	127	+
	128	+ pinmux_p3led_an_gpio: pinmux_p3led_an_gpio {
	129	+ pinctrl-single,bits = <0x4 0x100 0x300>;
	130	+ };
	131	+
	132	+ pinmux_p4led_an_gpio: pinmux_p4led_an_gpio {
	133	+ pinctrl-single,bits = <0x4 0x400 0xc00>;
	134	+ };
	135	+ };
	136	+
	137	+ watchdog: watchdog@100 {
	138	+ compatible = "mediatek,mt7621-wdt";
	139	+ reg = <0x100 0x30>;
	140	+
	141	+ resets = <&resetc 8>;
	142	+ reset-names = "wdt";
	143	+
	144	+ interrupt-parent = <&intc>;
	145	+ interrupts = <24>;
	146	+
	147	+ status = "disabled";
40	148	};
41	149
42	150	intc: interrupt-controller@200 {
@@ -62,10 +170,42 @@ · 19 unmodified lines
62	170	reg = <0x300 0x100>;
63	171	};
64	172
	173	+ gpio: gpio@600 {
	174	+ compatible = "mediatek,mt7621-gpio";
	175	+ reg = <0x600 0x100>;
	176	+
	177	+ gpio-controller;
	178	+ interrupt-controller;
	179	+ #gpio-cells = <2>;
	180	+ #interrupt-cells = <2>;
	181	+
	182	+ interrupt-parent = <&intc>;
	183	+ interrupts = <6>;
	184	+ };
	185	+
	186	+ spi: spi@b00 {
	187	+ compatible = "ralink,mt7621-spi";
	188	+ reg = <0xb00 0x100>;
	189	+
	190	+ pinctrl-names = "default";
	191	+ pinctrl-0 = <&pinmux_spi_spi>;
	192	+
	193	+ resets = <&resetc 18>;
	194	+ reset-names = "spi";
	195	+
	196	+ #address-cells = <1>;
	197	+ #size-cells = <0>;
	198	+
	199	+ status = "disabled";
	200	+ };
	201	+
65	202	uart0: uartlite@c00 {
66	203	compatible = "ns16550a";
67	204	reg = <0xc00 0x100>;
68	205
	206	+ pinctrl-names = "default";
	207	+ pinctrl-0 = <&pinmux_uart0_uart>;
	208	+
69	209	resets = <&resetc 12>;
70	210	reset-names = "uart0";
71	211
@@ -79,6 +219,9 @@ · 7 unmodified lines
79	219	compatible = "ns16550a";
80	220	reg = <0xd00 0x100>;
81	221
	222	+ pinctrl-names = "default";
	223	+ pinctrl-0 = <&pinmux_uart1_uart>;
	224	+
82	225	resets = <&resetc 19>;
83	226	reset-names = "uart1";
84	227
@@ -92,6 +235,9 @@ · 7 unmodified lines
92	235	compatible = "ns16550a";
93	236	reg = <0xe00 0x100>;
94	237
	238	+ pinctrl-names = "default";
	239	+ pinctrl-0 = <&pinmux_uart2_uart>;
	240	+
95	241	resets = <&resetc 20>;
96	242	reset-names = "uart2";
97	243

arch/mips/cavium-octeon/executive/cvmx-pko.c+1−1

@@ -485,11 +485,11 @@ cvmx_pko_status_t cvmx_pko_config_port(uint64_t port, uint64_t base_queue, · 484 unmodified lines
485	485	config.s.qos_mask = 0xff;
486	486	break;
487	487	case CVMX_PKO_QUEUE_STATIC_PRIORITY:
488		− /* Pass 1 will fall through to the error case */
489	488	if (!cvmx_octeon_is_pass1()) {
490	489	config.s.qos_mask = 0xff;
491	490	break;
492	491	}
	492	+ /* fall through - to the error case, when Pass 1 */
493	493	default:
494	494	cvmx_dprintf("ERROR: cvmx_pko_config_port: Invalid "
495	495	"priority %llu\n",

arch/mips/configs/ar7_defconfig+0−1

@@ -71,7 +71,6 @@ CONFIG_NET_ACT_POLICE=y · 70 unmodified lines
71	71	CONFIG_HAMRADIO=y
72	72	CONFIG_CFG80211=m
73	73	CONFIG_MAC80211=m
74		−CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
75	74	CONFIG_MTD=y
76	75	CONFIG_MTD_BLOCK=y
77	76	CONFIG_MTD_CFI=y

arch/mips/configs/ath25_defconfig+0−1

@@ -37,7 +37,6 @@ CONFIG_IP_ADVANCED_ROUTER=y · 36 unmodified lines
37	37	CONFIG_CFG80211=m
38	38	CONFIG_MAC80211=m
39	39	CONFIG_MAC80211_DEBUGFS=y
40		−CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
41	40	CONFIG_MTD=y
42	41	CONFIG_MTD_REDBOOT_PARTS=y
43	42	CONFIG_MTD_REDBOOT_DIRECTORY_BLOCK=-2

arch/mips/configs/ath79_defconfig+0−1

@@ -37,7 +37,6 @@ CONFIG_IP_ADVANCED_ROUTER=y · 36 unmodified lines
37	37	CONFIG_CFG80211=m
38	38	CONFIG_MAC80211=m
39	39	CONFIG_MAC80211_DEBUGFS=y
40		−CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
41	40	CONFIG_MTD=y
42	41	CONFIG_MTD_REDBOOT_PARTS=y
43	42	CONFIG_MTD_REDBOOT_DIRECTORY_BLOCK=-2

arch/mips/configs/bcm63xx_defconfig+0−1

@@ -34,7 +34,6 @@ CONFIG_INET=y · 33 unmodified lines
34	34	CONFIG_CFG80211=y
35	35	CONFIG_NL80211_TESTMODE=y
36	36	CONFIG_MAC80211=y
37		−CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
38	37	# CONFIG_STANDALONE is not set
39	38	# CONFIG_PREVENT_FIRMWARE_BUILD is not set
40	39	CONFIG_MTD=y

arch/mips/configs/bigsur_defconfig+0−1

@@ -99,7 +99,6 @@ CONFIG_BPQETHER=m · 98 unmodified lines
99	99	CONFIG_BAYCOM_SER_FDX=m
100	100	CONFIG_BAYCOM_SER_HDX=m
101	101	CONFIG_YAM=m
102		−CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
103	102	CONFIG_FW_LOADER=m
104	103	CONFIG_BLK_DEV_LOOP=m
105	104	CONFIG_BLK_DEV_CRYPTOLOOP=m

arch/mips/configs/bmips_be_defconfig+0−1

@@ -26,7 +26,6 @@ CONFIG_INET=y · 25 unmodified lines
26	26	CONFIG_CFG80211=y
27	27	CONFIG_NL80211_TESTMODE=y
28	28	CONFIG_MAC80211=y
29		−CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
30	29	CONFIG_DEVTMPFS=y
31	30	CONFIG_DEVTMPFS_MOUNT=y
32	31	# CONFIG_STANDALONE is not set

arch/mips/configs/bmips_stb_defconfig+0−1

@@ -35,7 +35,6 @@ CONFIG_INET=y · 34 unmodified lines
35	35	CONFIG_CFG80211=y
36	36	CONFIG_NL80211_TESTMODE=y
37	37	CONFIG_MAC80211=y
38		−CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
39	38	CONFIG_DEVTMPFS=y
40	39	CONFIG_DEVTMPFS_MOUNT=y
41	40	# CONFIG_STANDALONE is not set

arch/mips/configs/cavium_octeon_defconfig+0−1

@@ -42,7 +42,6 @@ CONFIG_IP_MROUTE=y · 41 unmodified lines
42	42	CONFIG_IP_PIMSM_V1=y
43	43	CONFIG_IP_PIMSM_V2=y
44	44	CONFIG_SYN_COOKIES=y
45		−CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
46	45	CONFIG_DEVTMPFS=y
47	46	# CONFIG_FW_LOADER is not set
48	47	CONFIG_MTD=y

arch/mips/configs/ci20_defconfig+0−1

@@ -44,7 +44,6 @@ CONFIG_IP_PNP_DHCP=y · 43 unmodified lines
44	44	# CONFIG_INET_DIAG is not set
45	45	# CONFIG_IPV6 is not set
46	46	# CONFIG_WIRELESS is not set
47		−CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
48	47	CONFIG_DEVTMPFS=y
49	48	# CONFIG_FW_LOADER is not set
50	49	# CONFIG_ALLOW_DEV_COREDUMP is not set

arch/mips/configs/cobalt_defconfig+0−1

@@ -14,7 +14,6 @@ CONFIG_NET_KEY=y · 13 unmodified lines
14	14	CONFIG_NET_KEY_MIGRATE=y
15	15	CONFIG_INET=y
16	16	# CONFIG_IPV6 is not set
17		−CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
18	17	CONFIG_MTD=y
19	18	CONFIG_MTD_JEDECPROBE=y
20	19	CONFIG_MTD_CFI_AMDSTD=y

arch/mips/configs/fuloong2e_defconfig+0−1

@@ -83,7 +83,6 @@ CONFIG_IP_NF_ARPFILTER=m · 82 unmodified lines
83	83	CONFIG_IP_NF_ARP_MANGLE=m
84	84	CONFIG_PHONET=m
85	85	CONFIG_NET_9P=m
86		−CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
87	86	CONFIG_FW_LOADER=m
88	87	CONFIG_MTD=m
89	88	CONFIG_MTD_BLOCK=m

arch/mips/configs/gpr_defconfig+0−1

@@ -249,7 +249,6 @@ CONFIG_WATCHDOG_NOWAYOUT=y · 248 unmodified lines
249	249	CONFIG_SSB=m
250	250	CONFIG_SSB_DRIVER_PCICORE=y
251	251	# CONFIG_VGA_ARB is not set
252		−CONFIG_BACKLIGHT_LCD_SUPPORT=y
253	252	# CONFIG_LCD_CLASS_DEVICE is not set
254	253	CONFIG_BACKLIGHT_CLASS_DEVICE=y
255	254	# CONFIG_BACKLIGHT_GENERIC is not set

arch/mips/configs/ip27_defconfig+0−1

@@ -91,7 +91,6 @@ CONFIG_NET_ACT_SKBEDIT=m · 90 unmodified lines
91	91	CONFIG_CFG80211=m
92	92	CONFIG_MAC80211=m
93	93	CONFIG_RFKILL=m
94		−CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
95	94	CONFIG_BLK_DEV_LOOP=y
96	95	CONFIG_BLK_DEV_CRYPTOLOOP=m
97	96	CONFIG_CDROM_PKTCDVD=m

arch/mips/configs/ip32_defconfig+0−1

@@ -42,7 +42,6 @@ CONFIG_INET6_ESP=m · 41 unmodified lines
42	42	CONFIG_INET6_IPCOMP=m
43	43	CONFIG_IPV6_TUNNEL=m
44	44	CONFIG_NETWORK_SECMARK=y
45		−CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
46	45	CONFIG_CONNECTOR=y
47	46	CONFIG_BLK_DEV_LOOP=m
48	47	CONFIG_BLK_DEV_CRYPTOLOOP=m

arch/mips/configs/lemote2f_defconfig+0−2

@@ -77,7 +77,6 @@ CONFIG_MAC80211=m · 76 unmodified lines
77	77	CONFIG_MAC80211_LEDS=y
78	78	CONFIG_RFKILL=m
79	79	CONFIG_RFKILL_INPUT=y
80		−CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
81	80	CONFIG_BLK_DEV_LOOP=y
82	81	CONFIG_BLK_DEV_CRYPTOLOOP=m
83	82	CONFIG_BLK_DEV_RAM=y
@@ -144,7 +143,6 @@ CONFIG_FB_TILEBLITTING=y · 60 unmodified lines
144	143	CONFIG_FB_SIS=y
145	144	CONFIG_FB_SIS_300=y
146	145	CONFIG_FB_SIS_315=y
147		−CONFIG_BACKLIGHT_LCD_SUPPORT=y
148	146	# CONFIG_LCD_CLASS_DEVICE is not set
149	147	CONFIG_BACKLIGHT_CLASS_DEVICE=y
150	148	CONFIG_BACKLIGHT_GENERIC=m

arch/mips/configs/loongson1b_defconfig+0−1

@@ -34,7 +34,6 @@ CONFIG_SYN_COOKIES=y · 33 unmodified lines
34	34	# CONFIG_INET_DIAG is not set
35	35	# CONFIG_IPV6 is not set
36	36	# CONFIG_WIRELESS is not set
37		−CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
38	37	CONFIG_DEVTMPFS=y
39	38	CONFIG_DEVTMPFS_MOUNT=y
40	39	# CONFIG_STANDALONE is not set

arch/mips/configs/loongson1c_defconfig+0−1

@@ -35,7 +35,6 @@ CONFIG_SYN_COOKIES=y · 34 unmodified lines
35	35	# CONFIG_INET_DIAG is not set
36	36	# CONFIG_IPV6 is not set
37	37	# CONFIG_WIRELESS is not set
38		−CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
39	38	CONFIG_DEVTMPFS=y
40	39	CONFIG_DEVTMPFS_MOUNT=y
41	40	# CONFIG_STANDALONE is not set

arch/mips/configs/loongson3_defconfig+0−1

@@ -97,7 +97,6 @@ CONFIG_CFG80211_WEXT=y · 96 unmodified lines
97	97	CONFIG_MAC80211=m
98	98	CONFIG_RFKILL=m
99	99	CONFIG_RFKILL_INPUT=y
100		−CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
101	100	CONFIG_DEVTMPFS=y
102	101	CONFIG_DEVTMPFS_MOUNT=y
103	102	CONFIG_MTD=m

arch/mips/configs/malta_defconfig+0−1

@@ -214,7 +214,6 @@ CONFIG_CFG80211=m · 213 unmodified lines
214	214	CONFIG_MAC80211=m
215	215	CONFIG_MAC80211_MESH=y
216	216	CONFIG_RFKILL=m
217		−CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
218	217	CONFIG_DEVTMPFS=y
219	218	CONFIG_CONNECTOR=m
220	219	CONFIG_MTD=y

arch/mips/configs/malta_kvm_defconfig+0−1

@@ -219,7 +219,6 @@ CONFIG_CFG80211=m · 218 unmodified lines
219	219	CONFIG_MAC80211=m
220	220	CONFIG_MAC80211_MESH=y
221	221	CONFIG_RFKILL=m
222		−CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
223	222	CONFIG_DEVTMPFS=y
224	223	CONFIG_CONNECTOR=m
225	224	CONFIG_MTD=y

arch/mips/configs/malta_kvm_guest_defconfig+0−1

@@ -216,7 +216,6 @@ CONFIG_CFG80211=m · 215 unmodified lines
216	216	CONFIG_MAC80211=m
217	217	CONFIG_MAC80211_MESH=y
218	218	CONFIG_RFKILL=m
219		−CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
220	219	CONFIG_DEVTMPFS=y
221	220	CONFIG_CONNECTOR=m
222	221	CONFIG_MTD=y

arch/mips/configs/maltaup_xpa_defconfig+0−1

@@ -216,7 +216,6 @@ CONFIG_CFG80211=m · 215 unmodified lines
216	216	CONFIG_MAC80211=m
217	217	CONFIG_MAC80211_MESH=y
218	218	CONFIG_RFKILL=m
219		−CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
220	219	CONFIG_DEVTMPFS=y
221	220	CONFIG_DEVTMPFS_MOUNT=y
222	221	CONFIG_CONNECTOR=m

arch/mips/configs/mips_paravirt_defconfig+0−1

@@ -39,7 +39,6 @@ CONFIG_IP_PIMSM_V1=y · 38 unmodified lines
39	39	CONFIG_IP_PIMSM_V2=y
40	40	CONFIG_SYN_COOKIES=y
41	41	# CONFIG_WIRELESS is not set
42		−CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
43	42	# CONFIG_FW_LOADER is not set
44	43	CONFIG_BLK_DEV_LOOP=y
45	44	CONFIG_VIRTIO_BLK=y

arch/mips/configs/omega2p_defconfig+0−1

@@ -42,7 +42,6 @@ CONFIG_INET=y · 41 unmodified lines
42	42	# CONFIG_INET_DIAG is not set
43	43	# CONFIG_IPV6 is not set
44	44	# CONFIG_WIRELESS is not set
45		−CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
46	45	CONFIG_DEVTMPFS=y
47	46	# CONFIG_FW_LOADER is not set
48	47	# CONFIG_ALLOW_DEV_COREDUMP is not set

arch/mips/configs/pistachio_defconfig+0−1

@@ -214,7 +214,6 @@ CONFIG_IR_IMG_RC6=y · 213 unmodified lines
214	214	CONFIG_MEDIA_SUPPORT=y
215	215	CONFIG_FB=y
216	216	CONFIG_FB_MODE_HELPERS=y
217		−CONFIG_BACKLIGHT_LCD_SUPPORT=y
218	217	# CONFIG_LCD_CLASS_DEVICE is not set
219	218	CONFIG_BACKLIGHT_CLASS_DEVICE=y
220	219	CONFIG_SOUND=y

arch/mips/configs/pnx8335_stb225_defconfig+0−1

@@ -25,7 +25,6 @@ CONFIG_IP_PNP=y · 24 unmodified lines
25	25	CONFIG_IP_PNP_DHCP=y
26	26	CONFIG_INET_AH=y
27	27	# CONFIG_IPV6 is not set
28		−CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
29	28	CONFIG_MTD=y
30	29	CONFIG_MTD_CMDLINE_PARTS=y
31	30	CONFIG_MTD_BLOCK=y

arch/mips/configs/qi_lb60_defconfig+0−2

@@ -41,7 +41,6 @@ CONFIG_TCP_CONG_ADVANCED=y · 40 unmodified lines
41	41	CONFIG_TCP_CONG_WESTWOOD=y
42	42	# CONFIG_TCP_CONG_HTCP is not set
43	43	# CONFIG_IPV6 is not set
44		−CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
45	44	CONFIG_MTD=y
46	45	CONFIG_MTD_BLOCK=y
47	46	CONFIG_MTD_RAW_NAND=y
@@ -77,7 +76,6 @@ CONFIG_REGULATOR=y · 29 unmodified lines
77	76	CONFIG_REGULATOR_FIXED_VOLTAGE=y
78	77	CONFIG_FB=y
79	78	CONFIG_FB_JZ4740=y
80		−CONFIG_BACKLIGHT_LCD_SUPPORT=y
81	79	CONFIG_LCD_CLASS_DEVICE=y
82	80	# CONFIG_BACKLIGHT_CLASS_DEVICE is not set
83	81	# CONFIG_VGA_CONSOLE is not set

arch/mips/configs/rb532_defconfig+0−1

@@ -104,7 +104,6 @@ CONFIG_NET_ACT_MIRRED=m · 103 unmodified lines
104	104	CONFIG_NET_ACT_IPT=m
105	105	CONFIG_NET_ACT_PEDIT=m
106	106	CONFIG_HAMRADIO=y
107		−CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
108	107	CONFIG_MTD=y
109	108	CONFIG_MTD_BLOCK=y
110	109	CONFIG_MTD_BLOCK2MTD=y

arch/mips/configs/rt305x_defconfig+0−1

@@ -69,7 +69,6 @@ CONFIG_BRIDGE=y · 68 unmodified lines
69	69	CONFIG_VLAN_8021Q=y
70	70	CONFIG_NET_SCHED=y
71	71	CONFIG_HAMRADIO=y
72		−CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
73	72	CONFIG_MTD=y
74	73	CONFIG_MTD_CMDLINE_PARTS=y
75	74	CONFIG_MTD_BLOCK=y

arch/mips/configs/sb1250_swarm_defconfig+0−1

@@ -43,7 +43,6 @@ CONFIG_NETWORK_SECMARK=y · 42 unmodified lines
43	43	CONFIG_CFG80211=m
44	44	CONFIG_MAC80211=m
45	45	CONFIG_RFKILL=m
46		−CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
47	46	CONFIG_FW_LOADER=m
48	47	CONFIG_CONNECTOR=m
49	48	CONFIG_BLK_DEV_RAM=y

arch/mips/configs/tb0219_defconfig+0−1

@@ -28,7 +28,6 @@ CONFIG_SYN_COOKIES=y · 27 unmodified lines
28	28	# CONFIG_INET_XFRM_MODE_BEET is not set
29	29	# CONFIG_IPV6 is not set
30	30	CONFIG_NETWORK_SECMARK=y
31		−CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
32	31	CONFIG_BLK_DEV_LOOP=m
33	32	CONFIG_BLK_DEV_NBD=m
34	33	CONFIG_BLK_DEV_RAM=y

arch/mips/configs/tb0226_defconfig+0−1

@@ -26,7 +26,6 @@ CONFIG_SYN_COOKIES=y · 25 unmodified lines
26	26	# CONFIG_INET_XFRM_MODE_BEET is not set
27	27	# CONFIG_IPV6 is not set
28	28	CONFIG_NETWORK_SECMARK=y
29		−CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
30	29	CONFIG_BLK_DEV_LOOP=m
31	30	CONFIG_BLK_DEV_NBD=m
32	31	CONFIG_BLK_DEV_RAM=y

arch/mips/configs/tb0287_defconfig+0−1

@@ -30,7 +30,6 @@ CONFIG_TCP_CONG_BIC=y · 29 unmodified lines
30	30	CONFIG_TCP_CONG_CUBIC=m
31	31	# CONFIG_IPV6 is not set
32	32	CONFIG_NETWORK_SECMARK=y
33		−CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
34	33	CONFIG_BLK_DEV_LOOP=m
35	34	CONFIG_BLK_DEV_NBD=m
36	35	CONFIG_BLK_DEV_RAM=y

arch/mips/configs/vocore2_defconfig+0−1

@@ -42,7 +42,6 @@ CONFIG_INET=y · 41 unmodified lines
42	42	# CONFIG_INET_DIAG is not set
43	43	# CONFIG_IPV6 is not set
44	44	# CONFIG_WIRELESS is not set
45		−CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
46	45	CONFIG_DEVTMPFS=y
47	46	# CONFIG_FW_LOADER is not set
48	47	# CONFIG_ALLOW_DEV_COREDUMP is not set

arch/mips/configs/xway_defconfig+0−1

@@ -71,7 +71,6 @@ CONFIG_BRIDGE=y · 70 unmodified lines
71	71	CONFIG_VLAN_8021Q=y
72	72	CONFIG_NET_SCHED=y
73	73	CONFIG_HAMRADIO=y
74		−CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
75	74	CONFIG_MTD=y
76	75	CONFIG_MTD_CMDLINE_PARTS=y
77	76	CONFIG_MTD_BLOCK=y

arch/mips/include/asm/cpu.h+60−65

@@ -9,6 +9,8 @@ · 8 unmodified lines
9	9	#ifndef _ASM_CPU_H
10	10	#define _ASM_CPU_H
11	11
	12	+#include <linux/bits.h>
	13	+
12	14	/*
13	15	As of the MIPS32 and MIPS64 specs from MTI, the PRId register (CP0
14	16	register 15, select 0) is defined in this (backwards compatible) way:
@@ -352,77 +354,70 @@ enum cpu_type_enum { · 337 unmodified lines
352	354	MIPS_CPU_ISA_V \| MIPS_CPU_ISA_M64R1 \| MIPS_CPU_ISA_M64R2 \| \
353	355	MIPS_CPU_ISA_M64R6)
354	356
355		−/*
356		− * Private version of BIT_ULL() to escape include file recursion hell.
357		− * We soon will have to switch to another mechanism that will work with
358		− * more than 64 bits anyway.
359		− */
360		−#define MBIT_ULL(bit) (1ULL << (bit))
361		−
362	357	/*
363	358	* CPU Option encodings
364	359	*/
365		−#define MIPS_CPU_TLB MBIT_ULL( 0) /* CPU has TLB */
366		−#define MIPS_CPU_4KEX MBIT_ULL( 1) /* "R4K" exception model */
367		−#define MIPS_CPU_3K_CACHE MBIT_ULL( 2) /* R3000-style caches */
368		−#define MIPS_CPU_4K_CACHE MBIT_ULL( 3) /* R4000-style caches */
369		−#define MIPS_CPU_TX39_CACHE MBIT_ULL( 4) /* TX3900-style caches */
370		−#define MIPS_CPU_FPU MBIT_ULL( 5) /* CPU has FPU */
371		−#define MIPS_CPU_32FPR MBIT_ULL( 6) /* 32 dbl. prec. FP registers */
372		−#define MIPS_CPU_COUNTER MBIT_ULL( 7) /* Cycle count/compare */
373		−#define MIPS_CPU_WATCH MBIT_ULL( 8) /* watchpoint registers */
374		−#define MIPS_CPU_DIVEC MBIT_ULL( 9) /* dedicated interrupt vector */
375		−#define MIPS_CPU_VCE MBIT_ULL(10) /* virt. coherence conflict possible */
376		−#define MIPS_CPU_CACHE_CDEX_P MBIT_ULL(11) /* Create_Dirty_Exclusive CACHE op */
377		−#define MIPS_CPU_CACHE_CDEX_S MBIT_ULL(12) /* ... same for seconary cache ... */
378		−#define MIPS_CPU_MCHECK MBIT_ULL(13) /* Machine check exception */
379		−#define MIPS_CPU_EJTAG MBIT_ULL(14) /* EJTAG exception */
380		−#define MIPS_CPU_NOFPUEX MBIT_ULL(15) /* no FPU exception */
381		−#define MIPS_CPU_LLSC MBIT_ULL(16) /* CPU has ll/sc instructions */
382		−#define MIPS_CPU_INCLUSIVE_CACHES MBIT_ULL(17) /* P-cache subset enforced */
383		−#define MIPS_CPU_PREFETCH MBIT_ULL(18) /* CPU has usable prefetch */
384		−#define MIPS_CPU_VINT MBIT_ULL(19) /* CPU supports MIPSR2 vectored interrupts */
385		−#define MIPS_CPU_VEIC MBIT_ULL(20) /* CPU supports MIPSR2 external interrupt controller mode */
386		−#define MIPS_CPU_ULRI MBIT_ULL(21) /* CPU has ULRI feature */
387		−#define MIPS_CPU_PCI MBIT_ULL(22) /* CPU has Perf Ctr Int indicator */
388		−#define MIPS_CPU_RIXI MBIT_ULL(23) /* CPU has TLB Read/eXec Inhibit */
389		−#define MIPS_CPU_MICROMIPS MBIT_ULL(24) /* CPU has microMIPS capability */
390		−#define MIPS_CPU_TLBINV MBIT_ULL(25) /* CPU supports TLBINV/F */
391		−#define MIPS_CPU_SEGMENTS MBIT_ULL(26) /* CPU supports Segmentation Control registers */
392		−#define MIPS_CPU_EVA MBIT_ULL(27) /* CPU supports Enhanced Virtual Addressing */
393		−#define MIPS_CPU_HTW MBIT_ULL(28) /* CPU support Hardware Page Table Walker */
394		−#define MIPS_CPU_RIXIEX MBIT_ULL(29) /* CPU has unique exception codes for {Read, Execute}-Inhibit exceptions */
395		−#define MIPS_CPU_MAAR MBIT_ULL(30) /* MAAR(I) registers are present */
396		−#define MIPS_CPU_FRE MBIT_ULL(31) /* FRE & UFE bits implemented */
397		−#define MIPS_CPU_RW_LLB MBIT_ULL(32) /* LLADDR/LLB writes are allowed */
398		−#define MIPS_CPU_LPA MBIT_ULL(33) /* CPU supports Large Physical Addressing */
399		−#define MIPS_CPU_CDMM MBIT_ULL(34) /* CPU has Common Device Memory Map */
400		−#define MIPS_CPU_BP_GHIST MBIT_ULL(35) /* R12K+ Branch Prediction Global History */
401		−#define MIPS_CPU_SP MBIT_ULL(36) /* Small (1KB) page support */
402		−#define MIPS_CPU_FTLB MBIT_ULL(37) /* CPU has Fixed-page-size TLB */
403		−#define MIPS_CPU_NAN_LEGACY MBIT_ULL(38) /* Legacy NaN implemented */
404		−#define MIPS_CPU_NAN_2008 MBIT_ULL(39) /* 2008 NaN implemented */
405		−#define MIPS_CPU_VP MBIT_ULL(40) /* MIPSr6 Virtual Processors (multi-threading) */
406		−#define MIPS_CPU_LDPTE MBIT_ULL(41) /* CPU has ldpte/lddir instructions */
407		−#define MIPS_CPU_MVH MBIT_ULL(42) /* CPU supports MFHC0/MTHC0 */
408		−#define MIPS_CPU_EBASE_WG MBIT_ULL(43) /* CPU has EBase.WG */
409		−#define MIPS_CPU_BADINSTR MBIT_ULL(44) /* CPU has BadInstr register */
410		−#define MIPS_CPU_BADINSTRP MBIT_ULL(45) /* CPU has BadInstrP register */
411		−#define MIPS_CPU_CTXTC MBIT_ULL(46) /* CPU has [X]ConfigContext registers */
412		−#define MIPS_CPU_PERF MBIT_ULL(47) /* CPU has MIPS performance counters */
413		−#define MIPS_CPU_GUESTCTL0EXT MBIT_ULL(48) /* CPU has VZ GuestCtl0Ext register */
414		−#define MIPS_CPU_GUESTCTL1 MBIT_ULL(49) /* CPU has VZ GuestCtl1 register */
415		−#define MIPS_CPU_GUESTCTL2 MBIT_ULL(50) /* CPU has VZ GuestCtl2 register */
416		−#define MIPS_CPU_GUESTID MBIT_ULL(51) /* CPU uses VZ ASE GuestID feature */
417		−#define MIPS_CPU_DRG MBIT_ULL(52) /* CPU has VZ Direct Root to Guest (DRG) */
418		−#define MIPS_CPU_UFR MBIT_ULL(53) /* CPU supports User mode FR switching */
	360	+#define MIPS_CPU_TLB BIT_ULL( 0) /* CPU has TLB */
	361	+#define MIPS_CPU_4KEX BIT_ULL( 1) /* "R4K" exception model */
	362	+#define MIPS_CPU_3K_CACHE BIT_ULL( 2) /* R3000-style caches */
	363	+#define MIPS_CPU_4K_CACHE BIT_ULL( 3) /* R4000-style caches */
	364	+#define MIPS_CPU_TX39_CACHE BIT_ULL( 4) /* TX3900-style caches */
	365	+#define MIPS_CPU_FPU BIT_ULL( 5) /* CPU has FPU */
	366	+#define MIPS_CPU_32FPR BIT_ULL( 6) /* 32 dbl. prec. FP registers */
	367	+#define MIPS_CPU_COUNTER BIT_ULL( 7) /* Cycle count/compare */
	368	+#define MIPS_CPU_WATCH BIT_ULL( 8) /* watchpoint registers */
	369	+#define MIPS_CPU_DIVEC BIT_ULL( 9) /* dedicated interrupt vector */
	370	+#define MIPS_CPU_VCE BIT_ULL(10) /* virt. coherence conflict possible */
	371	+#define MIPS_CPU_CACHE_CDEX_P BIT_ULL(11) /* Create_Dirty_Exclusive CACHE op */
	372	+#define MIPS_CPU_CACHE_CDEX_S BIT_ULL(12) /* ... same for seconary cache ... */
	373	+#define MIPS_CPU_MCHECK BIT_ULL(13) /* Machine check exception */
	374	+#define MIPS_CPU_EJTAG BIT_ULL(14) /* EJTAG exception */
	375	+#define MIPS_CPU_NOFPUEX BIT_ULL(15) /* no FPU exception */
	376	+#define MIPS_CPU_LLSC BIT_ULL(16) /* CPU has ll/sc instructions */
	377	+#define MIPS_CPU_INCLUSIVE_CACHES BIT_ULL(17) /* P-cache subset enforced */
	378	+#define MIPS_CPU_PREFETCH BIT_ULL(18) /* CPU has usable prefetch */
	379	+#define MIPS_CPU_VINT BIT_ULL(19) /* CPU supports MIPSR2 vectored interrupts */
	380	+#define MIPS_CPU_VEIC BIT_ULL(20) /* CPU supports MIPSR2 external interrupt controller mode */
	381	+#define MIPS_CPU_ULRI BIT_ULL(21) /* CPU has ULRI feature */
	382	+#define MIPS_CPU_PCI BIT_ULL(22) /* CPU has Perf Ctr Int indicator */
	383	+#define MIPS_CPU_RIXI BIT_ULL(23) /* CPU has TLB Read/eXec Inhibit */
	384	+#define MIPS_CPU_MICROMIPS BIT_ULL(24) /* CPU has microMIPS capability */
	385	+#define MIPS_CPU_TLBINV BIT_ULL(25) /* CPU supports TLBINV/F */
	386	+#define MIPS_CPU_SEGMENTS BIT_ULL(26) /* CPU supports Segmentation Control registers */
	387	+#define MIPS_CPU_EVA BIT_ULL(27) /* CPU supports Enhanced Virtual Addressing */
	388	+#define MIPS_CPU_HTW BIT_ULL(28) /* CPU support Hardware Page Table Walker */
	389	+#define MIPS_CPU_RIXIEX BIT_ULL(29) /* CPU has unique exception codes for {Read, Execute}-Inhibit exceptions */
	390	+#define MIPS_CPU_MAAR BIT_ULL(30) /* MAAR(I) registers are present */
	391	+#define MIPS_CPU_FRE BIT_ULL(31) /* FRE & UFE bits implemented */
	392	+#define MIPS_CPU_RW_LLB BIT_ULL(32) /* LLADDR/LLB writes are allowed */
	393	+#define MIPS_CPU_LPA BIT_ULL(33) /* CPU supports Large Physical Addressing */
	394	+#define MIPS_CPU_CDMM BIT_ULL(34) /* CPU has Common Device Memory Map */
	395	+#define MIPS_CPU_BP_GHIST BIT_ULL(35) /* R12K+ Branch Prediction Global History */
	396	+#define MIPS_CPU_SP BIT_ULL(36) /* Small (1KB) page support */
	397	+#define MIPS_CPU_FTLB BIT_ULL(37) /* CPU has Fixed-page-size TLB */
	398	+#define MIPS_CPU_NAN_LEGACY BIT_ULL(38) /* Legacy NaN implemented */
	399	+#define MIPS_CPU_NAN_2008 BIT_ULL(39) /* 2008 NaN implemented */
	400	+#define MIPS_CPU_VP BIT_ULL(40) /* MIPSr6 Virtual Processors (multi-threading) */
	401	+#define MIPS_CPU_LDPTE BIT_ULL(41) /* CPU has ldpte/lddir instructions */
	402	+#define MIPS_CPU_MVH BIT_ULL(42) /* CPU supports MFHC0/MTHC0 */
	403	+#define MIPS_CPU_EBASE_WG BIT_ULL(43) /* CPU has EBase.WG */
	404	+#define MIPS_CPU_BADINSTR BIT_ULL(44) /* CPU has BadInstr register */
	405	+#define MIPS_CPU_BADINSTRP BIT_ULL(45) /* CPU has BadInstrP register */
	406	+#define MIPS_CPU_CTXTC BIT_ULL(46) /* CPU has [X]ConfigContext registers */
	407	+#define MIPS_CPU_PERF BIT_ULL(47) /* CPU has MIPS performance counters */
	408	+#define MIPS_CPU_GUESTCTL0EXT BIT_ULL(48) /* CPU has VZ GuestCtl0Ext register */
	409	+#define MIPS_CPU_GUESTCTL1 BIT_ULL(49) /* CPU has VZ GuestCtl1 register */
	410	+#define MIPS_CPU_GUESTCTL2 BIT_ULL(50) /* CPU has VZ GuestCtl2 register */
	411	+#define MIPS_CPU_GUESTID BIT_ULL(51) /* CPU uses VZ ASE GuestID feature */
	412	+#define MIPS_CPU_DRG BIT_ULL(52) /* CPU has VZ Direct Root to Guest (DRG) */
	413	+#define MIPS_CPU_UFR BIT_ULL(53) /* CPU supports User mode FR switching */
419	414	#define MIPS_CPU_SHARED_FTLB_RAM \
420		− MBIT_ULL(54) /* CPU shares FTLB RAM with another */
	415	+ BIT_ULL(54) /* CPU shares FTLB RAM with another */
421	416	#define MIPS_CPU_SHARED_FTLB_ENTRIES \
422		− MBIT_ULL(55) /* CPU shares FTLB entries with another */
	417	+ BIT_ULL(55) /* CPU shares FTLB entries with another */
423	418	#define MIPS_CPU_MT_PER_TC_PERF_COUNTERS \
424		− MBIT_ULL(56) /* CPU has perf counters implemented per TC (MIPSMT ASE) */
425		−#define MIPS_CPU_MMID MBIT_ULL(57) /* CPU supports MemoryMapIDs */
	419	+ BIT_ULL(56) /* CPU has perf counters implemented per TC (MIPSMT ASE) */
	420	+#define MIPS_CPU_MMID BIT_ULL(57) /* CPU supports MemoryMapIDs */
426	421
427	422	/*
428	423	* CPU ASE encodings

arch/mips/include/asm/io.h+11−0

@@ -460,7 +460,12 @@ __BUILD_MEMORY_PFX(, bwlq, type, 0) · 459 unmodified lines
460	460	BUILDIO_MEM(b, u8)
461	461	BUILDIO_MEM(w, u16)
462	462	BUILDIO_MEM(l, u32)
	463	+#ifdef CONFIG_64BIT
463	464	BUILDIO_MEM(q, u64)
	465	+#else
	466	+__BUILD_MEMORY_PFX(__raw_, q, u64, 0)
	467	+__BUILD_MEMORY_PFX(__mem_, q, u64, 0)
	468	+#endif
464	469
465	470	#define __BUILD_IOPORT_PFX(bus, bwlq, type) \
466	471	__BUILD_IOPORT_SINGLE(bus, bwlq, type, 1, 0,) \
@@ -486,12 +491,16 @@ __BUILDIO(q, u64) · 19 unmodified lines
486	491	#define readb_relaxed __relaxed_readb
487	492	#define readw_relaxed __relaxed_readw
488	493	#define readl_relaxed __relaxed_readl
	494	+#ifdef CONFIG_64BIT
489	495	#define readq_relaxed __relaxed_readq
	496	+#endif
490	497
491	498	#define writeb_relaxed __relaxed_writeb
492	499	#define writew_relaxed __relaxed_writew
493	500	#define writel_relaxed __relaxed_writel
	501	+#ifdef CONFIG_64BIT
494	502	#define writeq_relaxed __relaxed_writeq
	503	+#endif
495	504
496	505	#define readb_be(addr) \
497	506	__raw_readb((__force unsigned *)(addr))
@@ -514,8 +523,10 @@ __BUILDIO(q, u64) · 16 unmodified lines
514	523	/*
515	524	* Some code tests for these symbols
516	525	*/
	526	+#ifdef CONFIG_64BIT
517	527	#define readq readq
518	528	#define writeq writeq
	529	+#endif
519	530
520	531	#define __BUILD_MEMORY_STRING(bwlq, type) \
521	532	\

arch/mips/include/asm/mach-ralink/pinmux.h+0−1

@@ -1,6 +1,5 @@
1	1	/* SPDX-License-Identifier: GPL-2.0-only */
2	2	/*
3		− *
4	3	* Copyright (C) 2012 John Crispin <john@phrozen.org>
5	4	*/
6	5

arch/mips/jz4740/board-qi_lb60.c+8−8

@@ -466,27 +466,27 @@ static unsigned long pin_cfg_bias_disable[] = { · 465 unmodified lines
466	466	static struct pinctrl_map pin_map[] __initdata = {
467	467	/* NAND pin configuration */
468	468	PIN_MAP_MUX_GROUP_DEFAULT("jz4740-nand",
469		− "10010000.jz4740-pinctrl", "nand", "nand-cs1"),
	469	+ "10010000.pin-controller", "nand-cs1", "nand"),
470	470
471	471	/* fbdev pin configuration */
472	472	PIN_MAP_MUX_GROUP("jz4740-fb", PINCTRL_STATE_DEFAULT,
473		− "10010000.jz4740-pinctrl", "lcd", "lcd-8bit"),
	473	+ "10010000.pin-controller", "lcd-8bit", "lcd"),
474	474	PIN_MAP_MUX_GROUP("jz4740-fb", PINCTRL_STATE_SLEEP,
475		− "10010000.jz4740-pinctrl", "lcd", "lcd-no-pins"),
	475	+ "10010000.pin-controller", "lcd-no-pins", "lcd"),
476	476
477	477	/* MMC pin configuration */
478	478	PIN_MAP_MUX_GROUP_DEFAULT("jz4740-mmc.0",
479		− "10010000.jz4740-pinctrl", "mmc", "mmc-1bit"),
	479	+ "10010000.pin-controller", "mmc-1bit", "mmc"),
480	480	PIN_MAP_MUX_GROUP_DEFAULT("jz4740-mmc.0",
481		− "10010000.jz4740-pinctrl", "mmc", "mmc-4bit"),
	481	+ "10010000.pin-controller", "mmc-4bit", "mmc"),
482	482	PIN_MAP_CONFIGS_PIN_DEFAULT("jz4740-mmc.0",
483		− "10010000.jz4740-pinctrl", "PD0", pin_cfg_bias_disable),
	483	+ "10010000.pin-controller", "PD0", pin_cfg_bias_disable),
484	484	PIN_MAP_CONFIGS_PIN_DEFAULT("jz4740-mmc.0",
485		− "10010000.jz4740-pinctrl", "PD2", pin_cfg_bias_disable),
	485	+ "10010000.pin-controller", "PD2", pin_cfg_bias_disable),
486	486
487	487	/* PWM pin configuration */
488	488	PIN_MAP_MUX_GROUP_DEFAULT("jz4740-pwm",
489		− "10010000.jz4740-pinctrl", "pwm4", "pwm4"),
	489	+ "10010000.pin-controller", "pwm4", "pwm4"),
490	490	};
491	491
492	492

arch/mips/kernel/ftrace.c+12−11

@@ -333,20 +333,21 @@ void prepare_ftrace_return(unsigned long *parent_ra_addr, unsigned long self_ra, · 332 unmodified lines
333	333	return;
334	334
335	335	/*
336		− * "parent_ra_addr" is the stack address saved the return address of
337		− * the caller of _mcount.
	336	+ * "parent_ra_addr" is the stack address where the return address of
	337	+ * the caller of _mcount is saved.
338	338	*
339		− * if the gcc < 4.5, a leaf function does not save the return address
340		− * in the stack address, so, we "emulate" one in _mcount's stack space,
341		− * and hijack it directly, but for a non-leaf function, it save the
342		− * return address to the its own stack space, we can not hijack it
343		− * directly, but need to find the real stack address,
344		− * ftrace_get_parent_addr() does it!
	339	+ * If gcc < 4.5, a leaf function does not save the return address
	340	+ * in the stack address, so we "emulate" one in _mcount's stack space,
	341	+ * and hijack it directly.
	342	+ * For a non-leaf function, it does save the return address to its own
	343	+ * stack space, so we can not hijack it directly, but need to find the
	344	+ * real stack address, which is done by ftrace_get_parent_addr().
345	345	*
346		− * if gcc>= 4.5, with the new -mmcount-ra-address option, for a
	346	+ * If gcc >= 4.5, with the new -mmcount-ra-address option, for a
347	347	* non-leaf function, the location of the return address will be saved
348		− * to $12 for us, and for a leaf function, only put a zero into $12. we
349		− * do it in ftrace_graph_caller of mcount.S.
	348	+ * to $12 for us.
	349	+ * For a leaf function, it just puts a zero into $12, so we handle
	350	+ * it in ftrace_graph_caller() of mcount.S.
350	351	*/
351	352
352	353	/* old_parent_ra = parent_ra_addr; /

arch/mips/kernel/perf_event_mipsxx.c+15−15

@@ -790,15 +790,19 @@ static void reset_counters(void *arg) · 789 unmodified lines
790	790	case 4:
791	791	mipsxx_pmu_write_control(3, 0);
792	792	mipspmu.write_counter(3, 0);
	793	+ /* fall through */
793	794	case 3:
794	795	mipsxx_pmu_write_control(2, 0);
795	796	mipspmu.write_counter(2, 0);
	797	+ /* fall through */
796	798	case 2:
797	799	mipsxx_pmu_write_control(1, 0);
798	800	mipspmu.write_counter(1, 0);
	801	+ /* fall through */
799	802	case 1:
800	803	mipsxx_pmu_write_control(0, 0);
801	804	mipspmu.write_counter(0, 0);
	805	+ /* fall through */
802	806	}
803	807	}
804	808
@@ -1380,7 +1384,7 @@ static int mipsxx_pmu_handle_shared_irq(void) · 575 unmodified lines
1380	1384	struct perf_sample_data data;
1381	1385	unsigned int counters = mipspmu.num_counters;
1382	1386	u64 counter;
1383		− int handled = IRQ_NONE;
	1387	+ int n, handled = IRQ_NONE;
1384	1388	struct pt_regs *regs;
1385	1389
1386	1390	if (cpu_has_perf_cntr_intr_bit && !(read_c0_cause() & CAUSEF_PCI))
@@ -1401,20 +1405,16 @@ static int mipsxx_pmu_handle_shared_irq(void) · 14 unmodified lines
1401	1405
1402	1406	perf_sample_data_init(&data, 0, 0);
1403	1407
1404		− switch (counters) {
1405		−#define HANDLE_COUNTER(n) \
1406		− case n + 1: \
1407		− if (test_bit(n, cpuc->used_mask)) { \
1408		− counter = mipspmu.read_counter(n); \
1409		− if (counter & mipspmu.overflow) { \
1410		− handle_associated_event(cpuc, n, &data, regs); \
1411		− handled = IRQ_HANDLED; \
1412		− } \
1413		− }
1414		− HANDLE_COUNTER(3)
1415		− HANDLE_COUNTER(2)
1416		− HANDLE_COUNTER(1)
1417		− HANDLE_COUNTER(0)
	1408	+ for (n = counters - 1; n >= 0; n--) {
	1409	+ if (!test_bit(n, cpuc->used_mask))
	1410	+ continue;
	1411	+
	1412	+ counter = mipspmu.read_counter(n);
	1413	+ if (!(counter & mipspmu.overflow))
	1414	+ continue;
	1415	+
	1416	+ handle_associated_event(cpuc, n, &data, regs);
	1417	+ handled = IRQ_HANDLED;
1418	1418	}
1419	1419
1420	1420	#ifdef CONFIG_MIPS_PERF_SHARED_TC_COUNTERS

arch/mips/lantiq/irq.c+126−51

@@ -20,13 +20,13 @@ · 19 unmodified lines
20	20	#include <irq.h>
21	21
22	22	/* register definitions - internal irqs */
23		−#define LTQ_ICU_IM0_ISR 0x0000
24		−#define LTQ_ICU_IM0_IER 0x0008
25		−#define LTQ_ICU_IM0_IOSR 0x0010
26		−#define LTQ_ICU_IM0_IRSR 0x0018
27		−#define LTQ_ICU_IM0_IMR 0x0020
28		−#define LTQ_ICU_IM1_ISR 0x0028
29		−#define LTQ_ICU_OFFSET (LTQ_ICU_IM1_ISR - LTQ_ICU_IM0_ISR)
	23	+#define LTQ_ICU_ISR 0x0000
	24	+#define LTQ_ICU_IER 0x0008
	25	+#define LTQ_ICU_IOSR 0x0010
	26	+#define LTQ_ICU_IRSR 0x0018
	27	+#define LTQ_ICU_IMR 0x0020
	28	+
	29	+#define LTQ_ICU_IM_SIZE 0x28
30	30
31	31	/* register definitions - external irqs */
32	32	#define LTQ_EIU_EXIN_C 0x0000
@@ -46,24 +46,25 @@ · 13 unmodified lines
46	46	*/
47	47	#define LTQ_ICU_EBU_IRQ 22
48	48
49		−#define ltq_icu_w32(m, x, y) ltq_w32((x), ltq_icu_membase[m] + (y))
50		−#define ltq_icu_r32(m, x) ltq_r32(ltq_icu_membase[m] + (x))
	49	+#define ltq_icu_w32(vpe, m, x, y) \
	50	+ ltq_w32((x), ltq_icu_membase[vpe] + m*LTQ_ICU_IM_SIZE + (y))
	51	+
	52	+#define ltq_icu_r32(vpe, m, x) \
	53	+ ltq_r32(ltq_icu_membase[vpe] + m*LTQ_ICU_IM_SIZE + (x))
51	54
52	55	#define ltq_eiu_w32(x, y) ltq_w32((x), ltq_eiu_membase + (y))
53	56	#define ltq_eiu_r32(x) ltq_r32(ltq_eiu_membase + (x))
54	57
55		−/* our 2 ipi interrupts for VSMP */
56		−#define MIPS_CPU_IPI_RESCHED_IRQ 0
57		−#define MIPS_CPU_IPI_CALL_IRQ 1
58		−
59	58	/* we have a cascade of 8 irqs */
60	59	#define MIPS_CPU_IRQ_CASCADE 8
61	60
62	61	static int exin_avail;
63	62	static u32 ltq_eiu_irq[MAX_EIU];
64		−static void __iomem *ltq_icu_membase[MAX_IM];
	63	+static void __iomem *ltq_icu_membase[NR_CPUS];
65	64	static void __iomem *ltq_eiu_membase;
66	65	static struct irq_domain *ltq_domain;
	66	+static DEFINE_SPINLOCK(ltq_eiu_lock);
	67	+static DEFINE_RAW_SPINLOCK(ltq_icu_lock);
67	68	static int ltq_perfcount_irq;
68	69
69	70	int ltq_eiu_get_irq(int exin)
@@ -75,49 +76,84 @@ int ltq_eiu_get_irq(int exin) · 5 unmodified lines
75	76
76	77	void ltq_disable_irq(struct irq_data *d)
77	78	{
78		− u32 ier = LTQ_ICU_IM0_IER;
79		− int offset = d->hwirq - MIPS_CPU_IRQ_CASCADE;
80		− int im = offset / INT_NUM_IM_OFFSET;
	79	+ unsigned long offset = d->hwirq - MIPS_CPU_IRQ_CASCADE;
	80	+ unsigned long im = offset / INT_NUM_IM_OFFSET;
	81	+ unsigned long flags;
	82	+ int vpe;
81	83
82	84	offset %= INT_NUM_IM_OFFSET;
83		− ltq_icu_w32(im, ltq_icu_r32(im, ier) & ~BIT(offset), ier);
	85	+
	86	+ raw_spin_lock_irqsave(&ltq_icu_lock, flags);
	87	+ for_each_present_cpu(vpe) {
	88	+ ltq_icu_w32(vpe, im,
	89	+ ltq_icu_r32(vpe, im, LTQ_ICU_IER) & ~BIT(offset),
	90	+ LTQ_ICU_IER);
	91	+ }
	92	+ raw_spin_unlock_irqrestore(&ltq_icu_lock, flags);
84	93	}
85	94
86	95	void ltq_mask_and_ack_irq(struct irq_data *d)
87	96	{
88		− u32 ier = LTQ_ICU_IM0_IER;
89		− u32 isr = LTQ_ICU_IM0_ISR;
90		− int offset = d->hwirq - MIPS_CPU_IRQ_CASCADE;
91		− int im = offset / INT_NUM_IM_OFFSET;
	97	+ unsigned long offset = d->hwirq - MIPS_CPU_IRQ_CASCADE;
	98	+ unsigned long im = offset / INT_NUM_IM_OFFSET;
	99	+ unsigned long flags;
	100	+ int vpe;
92	101
93	102	offset %= INT_NUM_IM_OFFSET;
94		− ltq_icu_w32(im, ltq_icu_r32(im, ier) & ~BIT(offset), ier);
95		− ltq_icu_w32(im, BIT(offset), isr);
	103	+
	104	+ raw_spin_lock_irqsave(&ltq_icu_lock, flags);
	105	+ for_each_present_cpu(vpe) {
	106	+ ltq_icu_w32(vpe, im,
	107	+ ltq_icu_r32(vpe, im, LTQ_ICU_IER) & ~BIT(offset),
	108	+ LTQ_ICU_IER);
	109	+ ltq_icu_w32(vpe, im, BIT(offset), LTQ_ICU_ISR);
	110	+ }
	111	+ raw_spin_unlock_irqrestore(&ltq_icu_lock, flags);
96	112	}
97	113
98	114	static void ltq_ack_irq(struct irq_data *d)
99	115	{
100		− u32 isr = LTQ_ICU_IM0_ISR;
101		− int offset = d->hwirq - MIPS_CPU_IRQ_CASCADE;
102		− int im = offset / INT_NUM_IM_OFFSET;
	116	+ unsigned long offset = d->hwirq - MIPS_CPU_IRQ_CASCADE;
	117	+ unsigned long im = offset / INT_NUM_IM_OFFSET;
	118	+ unsigned long flags;
	119	+ int vpe;
103	120
104	121	offset %= INT_NUM_IM_OFFSET;
105		− ltq_icu_w32(im, BIT(offset), isr);
	122	+
	123	+ raw_spin_lock_irqsave(&ltq_icu_lock, flags);
	124	+ for_each_present_cpu(vpe) {
	125	+ ltq_icu_w32(vpe, im, BIT(offset), LTQ_ICU_ISR);
	126	+ }
	127	+ raw_spin_unlock_irqrestore(&ltq_icu_lock, flags);
106	128	}
107	129
108	130	void ltq_enable_irq(struct irq_data *d)
109	131	{
110		− u32 ier = LTQ_ICU_IM0_IER;
111		− int offset = d->hwirq - MIPS_CPU_IRQ_CASCADE;
112		− int im = offset / INT_NUM_IM_OFFSET;
	132	+ unsigned long offset = d->hwirq - MIPS_CPU_IRQ_CASCADE;
	133	+ unsigned long im = offset / INT_NUM_IM_OFFSET;
	134	+ unsigned long flags;
	135	+ int vpe;
113	136
114	137	offset %= INT_NUM_IM_OFFSET;
115		− ltq_icu_w32(im, ltq_icu_r32(im, ier) \| BIT(offset), ier);
	138	+
	139	+ vpe = cpumask_first(irq_data_get_effective_affinity_mask(d));
	140	+
	141	+ /* This shouldn't be even possible, maybe during CPU hotplug spam */
	142	+ if (unlikely(vpe >= nr_cpu_ids))
	143	+ vpe = smp_processor_id();
	144	+
	145	+ raw_spin_lock_irqsave(&ltq_icu_lock, flags);
	146	+
	147	+ ltq_icu_w32(vpe, im, ltq_icu_r32(vpe, im, LTQ_ICU_IER) \| BIT(offset),
	148	+ LTQ_ICU_IER);
	149	+
	150	+ raw_spin_unlock_irqrestore(&ltq_icu_lock, flags);
116	151	}
117	152
118	153	static int ltq_eiu_settype(struct irq_data *d, unsigned int type)
119	154	{
120	155	int i;
	156	+ unsigned long flags;
121	157
122	158	for (i = 0; i < exin_avail; i++) {
123	159	if (d->hwirq == ltq_eiu_irq[i]) {
@@ -154,8 +190,11 @@ static int ltq_eiu_settype(struct irq_data *d, unsigned int type) · 30 unmodified lines
154	190	if (edge)
155	191	irq_set_handler(d->hwirq, handle_edge_irq);
156	192
157		− ltq_eiu_w32(ltq_eiu_r32(LTQ_EIU_EXIN_C) \|
158		− (val << (i * 4)), LTQ_EIU_EXIN_C);
	193	+ spin_lock_irqsave(&ltq_eiu_lock, flags);
	194	+ ltq_eiu_w32((ltq_eiu_r32(LTQ_EIU_EXIN_C) &
	195	+ (~(7 << (i * 4)))) \| (val << (i * 4)),
	196	+ LTQ_EIU_EXIN_C);
	197	+ spin_unlock_irqrestore(&ltq_eiu_lock, flags);
159	198	}
160	199	}
161	200
@@ -199,6 +238,21 @@ static void ltq_shutdown_eiu_irq(struct irq_data *d) · 37 unmodified lines
199	238	}
200	239	}
201	240
	241	+#if defined(CONFIG_SMP)
	242	+static int ltq_icu_irq_set_affinity(struct irq_data *d,
	243	+ const struct cpumask *cpumask, bool force)
	244	+{
	245	+ struct cpumask tmask;
	246	+
	247	+ if (!cpumask_and(&tmask, cpumask, cpu_online_mask))
	248	+ return -EINVAL;
	249	+
	250	+ irq_data_update_effective_affinity(d, &tmask);
	251	+
	252	+ return IRQ_SET_MASK_OK;
	253	+}
	254	+#endif
	255	+
202	256	static struct irq_chip ltq_irq_type = {
203	257	.name = "icu",
204	258	.irq_enable = ltq_enable_irq,
@@ -207,6 +261,9 @@ static struct irq_chip ltq_irq_type = { · 2 unmodified lines
207	261	.irq_ack = ltq_ack_irq,
208	262	.irq_mask = ltq_disable_irq,
209	263	.irq_mask_ack = ltq_mask_and_ack_irq,
	264	+#if defined(CONFIG_SMP)
	265	+ .irq_set_affinity = ltq_icu_irq_set_affinity,
	266	+#endif
210	267	};
211	268
212	269	static struct irq_chip ltq_eiu_type = {
@@ -220,15 +277,19 @@ static struct irq_chip ltq_eiu_type = { · 7 unmodified lines
220	277	.irq_mask = ltq_disable_irq,
221	278	.irq_mask_ack = ltq_mask_and_ack_irq,
222	279	.irq_set_type = ltq_eiu_settype,
	280	+#if defined(CONFIG_SMP)
	281	+ .irq_set_affinity = ltq_icu_irq_set_affinity,
	282	+#endif
223	283	};
224	284
225	285	static void ltq_hw_irq_handler(struct irq_desc *desc)
226	286	{
227		− int module = irq_desc_get_irq(desc) - 2;
	287	+ unsigned int module = irq_desc_get_irq(desc) - 2;
228	288	u32 irq;
229		− int hwirq;
	289	+ irq_hw_number_t hwirq;
	290	+ int vpe = smp_processor_id();
230	291
231		− irq = ltq_icu_r32(module, LTQ_ICU_IM0_IOSR);
	292	+ irq = ltq_icu_r32(vpe, module, LTQ_ICU_IOSR);
232	293	if (irq == 0)
233	294	return;
234	295
@@ -249,6 +310,7 @@ static void ltq_hw_irq_handler(struct irq_desc *desc) · 14 unmodified lines
249	310	static int icu_map(struct irq_domain *d, unsigned int irq, irq_hw_number_t hw)
250	311	{
251	312	struct irq_chip *chip = &ltq_irq_type;
	313	+ struct irq_data *data;
252	314	int i;
253	315
254	316	if (hw < MIPS_CPU_IRQ_CASCADE)
@@ -258,6 +320,10 @@ static int icu_map(struct irq_domain *d, unsigned int irq, irq_hw_number_t hw) · 3 unmodified lines
258	320	if (hw == ltq_eiu_irq[i])
259	321	chip = &ltq_eiu_type;
260	322
	323	+ data = irq_get_irq_data(irq);
	324	+
	325	+ irq_data_update_effective_affinity(data, cpumask_of(0));
	326	+
261	327	irq_set_chip_and_handler(irq, chip, handle_level_irq);
262	328
263	329	return 0;
@@ -272,28 +338,37 @@ int __init icu_of_init(struct device_node node, struct device_node parent) · 8 unmodified lines
272	338	{
273	339	struct device_node *eiu_node;
274	340	struct resource res;
275		− int i, ret;
	341	+ int i, ret, vpe;
276	342
277		− for (i = 0; i < MAX_IM; i++) {
278		− if (of_address_to_resource(node, i, &res))
279		− panic("Failed to get icu memory range");
	343	+ /* load register regions of available ICUs */
	344	+ for_each_possible_cpu(vpe) {
	345	+ if (of_address_to_resource(node, vpe, &res))
	346	+ panic("Failed to get icu%i memory range", vpe);
280	347
281	348	if (!request_mem_region(res.start, resource_size(&res),
282	349	res.name))
283		− pr_err("Failed to request icu memory");
	350	+ pr_err("Failed to request icu%i memory\n", vpe);
284	351
285		− ltq_icu_membase[i] = ioremap_nocache(res.start,
	352	+ ltq_icu_membase[vpe] = ioremap_nocache(res.start,
286	353	resource_size(&res));
287		− if (!ltq_icu_membase[i])
288		− panic("Failed to remap icu memory");
	354	+
	355	+ if (!ltq_icu_membase[vpe])
	356	+ panic("Failed to remap icu%i memory", vpe);
289	357	}
290	358
291	359	/* turn off all irqs by default */
292		− for (i = 0; i < MAX_IM; i++) {
293		− /* make sure all irqs are turned off by default */
294		− ltq_icu_w32(i, 0, LTQ_ICU_IM0_IER);
295		− /* clear all possibly pending interrupts */
296		− ltq_icu_w32(i, ~0, LTQ_ICU_IM0_ISR);
	360	+ for_each_possible_cpu(vpe) {
	361	+ for (i = 0; i < MAX_IM; i++) {
	362	+ /* make sure all irqs are turned off by default */
	363	+ ltq_icu_w32(vpe, i, 0, LTQ_ICU_IER);
	364	+
	365	+ /* clear all possibly pending interrupts */
	366	+ ltq_icu_w32(vpe, i, ~0, LTQ_ICU_ISR);
	367	+ ltq_icu_w32(vpe, i, ~0, LTQ_ICU_IMR);
	368	+
	369	+ /* clear resend */
	370	+ ltq_icu_w32(vpe, i, 0, LTQ_ICU_IRSR);
	371	+ }
297	372	}
298	373
299	374	mips_cpu_irq_init();
@@ -347,7 +422,7 @@ unsigned int get_c0_compare_int(void) · 47 unmodified lines
347	422	return CP0_LEGACY_COMPARE_IRQ;
348	423	}
349	424
350		−static struct of_device_id __initdata of_irq_ids[] = {
	425	+static const struct of_device_id of_irq_ids[] __initconst = {
351	426	{ .compatible = "lantiq,icu", .data = icu_of_init },
352	427	{},
353	428	};

drivers/memory/jz4780-nemc.c+1−1

@@ -61,7 +61,7 @@ struct jz4780_nemc { · 60 unmodified lines
61	61	*
62	62	* Return: The number of unique NEMC banks referred to by the specified NEMC
63	63	* child device. Unique here means that a device that references the same bank
64		− * multiple times in the its "reg" property will only count once.
	64	+ * multiple times in its "reg" property will only count once.
65	65	*/
66	66	unsigned int jz4780_nemc_num_banks(struct device *dev)
67	67	{

drivers/net/fddi/defza.c+1−0

@@ -33,6 +33,7 @@ · 32 unmodified lines
33	33	#include <linux/init.h>
34	34	#include <linux/interrupt.h>
35	35	#include <linux/io.h>
	36	+#include <linux/io-64-nonatomic-lo-hi.h>
36	37	#include <linux/ioport.h>
37	38	#include <linux/kernel.h>
38	39	#include <linux/list.h>

Merge tag 'mips_5.3' of git://git.kernel.org/pub/scm/linux/kernel/git/mips/linux

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Issues, pull requests and Inbox

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