Define 200G, 400G and 800G link modes using 200Gbps per lane.
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| @@ -2057,6 +2057,24 @@ enum ethtool_link_mode_bit_indices { · 2056 unmodified lines | |||
| 2057 | ETHTOOL_LINK_MODE_10baseT1S_Half_BIT = 100, | 2057 | ETHTOOL_LINK_MODE_10baseT1S_Half_BIT = 100, |
| 2058 | ETHTOOL_LINK_MODE_10baseT1S_P2MP_Half_BIT = 101, | 2058 | ETHTOOL_LINK_MODE_10baseT1S_P2MP_Half_BIT = 101, |
| 2059 | ETHTOOL_LINK_MODE_10baseT1BRR_Full_BIT = 102, | 2059 | ETHTOOL_LINK_MODE_10baseT1BRR_Full_BIT = 102, |
| 2060 | ETHTOOL_LINK_MODE_200000baseCR_Full_BIT = 103, | ||
| 2061 | ETHTOOL_LINK_MODE_200000baseKR_Full_BIT = 104, | ||
| 2062 | ETHTOOL_LINK_MODE_200000baseDR_Full_BIT = 105, | ||
| 2063 | ETHTOOL_LINK_MODE_200000baseDR_2_Full_BIT = 106, | ||
| 2064 | ETHTOOL_LINK_MODE_200000baseSR_Full_BIT = 107, | ||
| 2065 | ETHTOOL_LINK_MODE_200000baseVR_Full_BIT = 108, | ||
| 2066 | ETHTOOL_LINK_MODE_400000baseCR2_Full_BIT = 109, | ||
| 2067 | ETHTOOL_LINK_MODE_400000baseKR2_Full_BIT = 110, | ||
| 2068 | ETHTOOL_LINK_MODE_400000baseDR2_Full_BIT = 111, | ||
| 2069 | ETHTOOL_LINK_MODE_400000baseDR2_2_Full_BIT = 112, | ||
| 2070 | ETHTOOL_LINK_MODE_400000baseSR2_Full_BIT = 113, | ||
| 2071 | ETHTOOL_LINK_MODE_400000baseVR2_Full_BIT = 114, | ||
| 2072 | ETHTOOL_LINK_MODE_800000baseCR4_Full_BIT = 115, | ||
| 2073 | ETHTOOL_LINK_MODE_800000baseKR4_Full_BIT = 116, | ||
| 2074 | ETHTOOL_LINK_MODE_800000baseDR4_Full_BIT = 117, | ||
| 2075 | ETHTOOL_LINK_MODE_800000baseDR4_2_Full_BIT = 118, | ||
| 2076 | ETHTOOL_LINK_MODE_800000baseSR4_Full_BIT = 119, | ||
| 2077 | ETHTOOL_LINK_MODE_800000baseVR4_Full_BIT = 120, | ||
| 2060 | 2078 | ||
| 2061 | /* must be last entry */ | 2079 | /* must be last entry */ |
| 2062 | __ETHTOOL_LINK_MODE_MASK_NBITS | 2080 | __ETHTOOL_LINK_MODE_MASK_NBITS |