Pull MFD updates from Lee Jones: "New Drivers: - Add support for Merrifield Basin Cove PMIC New Device Support: - Add support for Intel Tiger Lake to Intel LPSS PCI - Add support for Intel Sky Lake to Intel LPSS PCI - Add support for ST-Ericsson DB8520 to DB8500 PRCMU New Functionality: - Add RTC and PWRC support to MT6323 Fix-ups: - Clean-up include files; davinci_voicecodec, asic3, sm501, mt6397 - Ignore return values from debugfs_create*(); ab3100-*, ab8500-debugfs, aat2870-core - Device Tree changes; rn5t618, mt6397 - Use new I2C API; tps80031, 88pm860x-core, ab3100-core, bcm590xx, da9150-core, max14577, max77693, max77843, max8907, max8925-i2c, max8997, max8998, palmas, twl-core, - Remove obsolete code; da9063, jz4740-adc - Simplify semantics; timberdale, htc-i2cpld - Add 'fall-through' tags; omap-usb-host, db8500-prcmu - Remove superfluous prints; ab8500-debugfs, db8500-prcmu, fsl-imx25-tsadc, intel_soc_pmic_bxtwc, qcom_rpm, sm501 - Trivial rename/whitespace/typo fixes; mt6397-core, MAINTAINERS - Reorganise code structure; mt6397-* - Improve code consistency; intel-lpss - Use MODULE_SOFTDEP() helper; intel-lpss - Use DEFINE_RES_*() helpers; mt6397-core Bug Fixes: - Clean-up resources; max77620 - Prevent input events being dropped on resume; intel-lpss-pci - Prevent sleeping in IRQ context; ezx-pcap" * tag 'mfd-next-5.4' of git://git.kernel.org/pub/scm/linux/kernel/git/lee/mfd: (48 commits) mfd: mt6323: Add MT6323 RTC and PWRC mfd: mt6323: Replace boilerplate resource code with DEFINE_RES_* macros mfd: mt6397: Add mutex include dt-bindings: mfd: mediatek: Add MT6323 Power Controller dt-bindings: mfd: mediatek: Update RTC to include MT6323 dt-bindings: mfd: mediatek: mt6397: Change to relative paths mfd: db8500-prcmu: Support the higher DB8520 ARMSS mfd: intel-lpss: Use MODULE_SOFTDEP() instead of implicit request mfd: htc-i2cpld: Drop check because i2c_unregister_device() is NULL safe mfd: sm501: Include the GPIO driver header mfd: intel-lpss: Add Intel Skylake ACPI IDs mfd: intel-lpss: Consistently use GENMASK() mfd: Add support for Merrifield Basin Cove PMIC mfd: ezx-pcap: Replace mutex_lock with spin_lock mfd: asic3: Include the right header MAINTAINERS: altera-sysmgr: Fix typo in a filepath mfd: mt6397: Extract IRQ related code from core driver mfd: mt6397: Rename macros to something more readable mfd: Remove dev_err() usage after platform_get_irq() mfd: db8500-prcmu: Mark expected switch fall-throughs ...
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| @@ -1,60 +0,0 @@ | ||
| 1 | −/* SPDX-License-Identifier: GPL-2.0-or-later */ | |
| 2 | −/* | |
| 3 | − * Platform configuration options for DA9063 | |
| 4 | − * | |
| 5 | − * Copyright 2012 Dialog Semiconductor Ltd. | |
| 6 | − * | |
| 7 | − * Author: Michal Hajduk, Dialog Semiconductor | |
| 8 | − * Author: Krystian Garbaciak, Dialog Semiconductor | |
| 9 | − */ | |
| 10 | − | |
| 11 | −#ifndef __MFD_DA9063_PDATA_H__ | |
| 12 | −#define __MFD_DA9063_PDATA_H__ | |
| 13 | − | |
| 14 | −/* | |
| 15 | − * RGB LED configuration | |
| 16 | − */ | |
| 17 | −/* LED IDs for flags in struct led_info. */ | |
| 18 | −enum { | |
| 19 | − DA9063_GPIO11_LED, | |
| 20 | − DA9063_GPIO14_LED, | |
| 21 | − DA9063_GPIO15_LED, | |
| 22 | − | |
| 23 | − DA9063_LED_NUM | |
| 24 | −}; | |
| 25 | −#define DA9063_LED_ID_MASK 0x3 | |
| 26 | − | |
| 27 | −/* LED polarity for flags in struct led_info. */ | |
| 28 | −#define DA9063_LED_HIGH_LEVEL_ACTIVE 0x0 | |
| 29 | −#define DA9063_LED_LOW_LEVEL_ACTIVE 0x4 | |
| 30 | − | |
| 31 | − | |
| 32 | −/* | |
| 33 | − * General PMIC configuration | |
| 34 | − */ | |
| 35 | −/* HWMON ADC channels configuration */ | |
| 36 | −#define DA9063_FLG_FORCE_IN0_MANUAL_MODE 0x0010 | |
| 37 | −#define DA9063_FLG_FORCE_IN0_AUTO_MODE 0x0020 | |
| 38 | −#define DA9063_FLG_FORCE_IN1_MANUAL_MODE 0x0040 | |
| 39 | −#define DA9063_FLG_FORCE_IN1_AUTO_MODE 0x0080 | |
| 40 | −#define DA9063_FLG_FORCE_IN2_MANUAL_MODE 0x0100 | |
| 41 | −#define DA9063_FLG_FORCE_IN2_AUTO_MODE 0x0200 | |
| 42 | −#define DA9063_FLG_FORCE_IN3_MANUAL_MODE 0x0400 | |
| 43 | −#define DA9063_FLG_FORCE_IN3_AUTO_MODE 0x0800 | |
| 44 | − | |
| 45 | −/* Disable register caching. */ | |
| 46 | −#define DA9063_FLG_NO_CACHE 0x0008 | |
| 47 | − | |
| 48 | −struct da9063; | |
| 49 | − | |
| 50 | −/* DA9063 platform data */ | |
| 51 | −struct da9063_pdata { | |
| 52 | − int (*init)(struct da9063 *da9063); | |
| 53 | − int irq_base; | |
| 54 | − bool key_power; | |
| 55 | − unsigned flags; | |
| 56 | − struct da9063_regulators_pdata *regulators_pdata; | |
| 57 | − struct led_platform_data *leds_pdata; | |
| 58 | −}; | |
| 59 | − | |
| 60 | −#endif /* __MFD_DA9063_PDATA_H__ */ | |
| @@ -0,0 +1,81 @@ | ||
| 1 | +/* SPDX-License-Identifier: GPL-2.0 */ | |
| 2 | +/* | |
| 3 | + * Header file for Intel Merrifield Basin Cove PMIC | |
| 4 | + * | |
| 5 | + * Copyright (C) 2019 Intel Corporation. All rights reserved. | |
| 6 | + */ | |
| 7 | + | |
| 8 | +#ifndef __INTEL_SOC_PMIC_MRFLD_H__ | |
| 9 | +#define __INTEL_SOC_PMIC_MRFLD_H__ | |
| 10 | + | |
| 11 | +#include <linux/bits.h> | |
| 12 | + | |
| 13 | +#define BCOVE_ID 0x00 | |
| 14 | + | |
| 15 | +#define BCOVE_ID_MINREV0 GENMASK(2, 0) | |
| 16 | +#define BCOVE_ID_MAJREV0 GENMASK(5, 3) | |
| 17 | +#define BCOVE_ID_VENDID0 GENMASK(7, 6) | |
| 18 | + | |
| 19 | +#define BCOVE_MINOR(x) (unsigned int)(((x) & BCOVE_ID_MINREV0) >> 0) | |
| 20 | +#define BCOVE_MAJOR(x) (unsigned int)(((x) & BCOVE_ID_MAJREV0) >> 3) | |
| 21 | +#define BCOVE_VENDOR(x) (unsigned int)(((x) & BCOVE_ID_VENDID0) >> 6) | |
| 22 | + | |
| 23 | +#define BCOVE_IRQLVL1 0x01 | |
| 24 | + | |
| 25 | +#define BCOVE_PBIRQ 0x02 | |
| 26 | +#define BCOVE_TMUIRQ 0x03 | |
| 27 | +#define BCOVE_THRMIRQ 0x04 | |
| 28 | +#define BCOVE_BCUIRQ 0x05 | |
| 29 | +#define BCOVE_ADCIRQ 0x06 | |
| 30 | +#define BCOVE_CHGRIRQ0 0x07 | |
| 31 | +#define BCOVE_CHGRIRQ1 0x08 | |
| 32 | +#define BCOVE_GPIOIRQ 0x09 | |
| 33 | +#define BCOVE_CRITIRQ 0x0B | |
| 34 | + | |
| 35 | +#define BCOVE_MIRQLVL1 0x0C | |
| 36 | + | |
| 37 | +#define BCOVE_MPBIRQ 0x0D | |
| 38 | +#define BCOVE_MTMUIRQ 0x0E | |
| 39 | +#define BCOVE_MTHRMIRQ 0x0F | |
| 40 | +#define BCOVE_MBCUIRQ 0x10 | |
| 41 | +#define BCOVE_MADCIRQ 0x11 | |
| 42 | +#define BCOVE_MCHGRIRQ0 0x12 | |
| 43 | +#define BCOVE_MCHGRIRQ1 0x13 | |
| 44 | +#define BCOVE_MGPIOIRQ 0x14 | |
| 45 | +#define BCOVE_MCRITIRQ 0x16 | |
| 46 | + | |
| 47 | +#define BCOVE_SCHGRIRQ0 0x4E | |
| 48 | +#define BCOVE_SCHGRIRQ1 0x4F | |
| 49 | + | |
| 50 | +/* Level 1 IRQs */ | |
| 51 | +#define BCOVE_LVL1_PWRBTN BIT(0) /* power button */ | |
| 52 | +#define BCOVE_LVL1_TMU BIT(1) /* time management unit */ | |
| 53 | +#define BCOVE_LVL1_THRM BIT(2) /* thermal */ | |
| 54 | +#define BCOVE_LVL1_BCU BIT(3) /* burst control unit */ | |
| 55 | +#define BCOVE_LVL1_ADC BIT(4) /* ADC */ | |
| 56 | +#define BCOVE_LVL1_CHGR BIT(5) /* charger */ | |
| 57 | +#define BCOVE_LVL1_GPIO BIT(6) /* GPIO */ | |
| 58 | +#define BCOVE_LVL1_CRIT BIT(7) /* critical event */ | |
| 59 | + | |
| 60 | +/* Level 2 IRQs: power button */ | |
| 61 | +#define BCOVE_PBIRQ_PBTN BIT(0) | |
| 62 | +#define BCOVE_PBIRQ_UBTN BIT(1) | |
| 63 | + | |
| 64 | +/* Level 2 IRQs: ADC */ | |
| 65 | +#define BCOVE_ADCIRQ_BATTEMP BIT(2) | |
| 66 | +#define BCOVE_ADCIRQ_SYSTEMP BIT(3) | |
| 67 | +#define BCOVE_ADCIRQ_BATTID BIT(4) | |
| 68 | +#define BCOVE_ADCIRQ_VIBATT BIT(5) | |
| 69 | +#define BCOVE_ADCIRQ_CCTICK BIT(7) | |
| 70 | + | |
| 71 | +/* Level 2 IRQs: charger */ | |
| 72 | +#define BCOVE_CHGRIRQ_BAT0ALRT BIT(4) | |
| 73 | +#define BCOVE_CHGRIRQ_BAT1ALRT BIT(5) | |
| 74 | +#define BCOVE_CHGRIRQ_BATCRIT BIT(6) | |
| 75 | + | |
| 76 | +#define BCOVE_CHGRIRQ_VBUSDET BIT(0) | |
| 77 | +#define BCOVE_CHGRIRQ_DCDET BIT(1) | |
| 78 | +#define BCOVE_CHGRIRQ_BATTDET BIT(2) | |
| 79 | +#define BCOVE_CHGRIRQ_USBIDDET BIT(3) | |
| 80 | + | |
| 81 | +#endif /* __INTEL_SOC_PMIC_MRFLD_H__ */ | |
| @@ -7,6 +7,14 @@ · 6 unmodified lines | ||
| 7 | 7 | #ifndef __MFD_MT6397_CORE_H__ |
| 8 | 8 | #define __MFD_MT6397_CORE_H__ |
| 9 | 9 | |
| 10 | +#include <linux/mutex.h> | |
| 11 | + | |
| 12 | +enum chip_id { | |
| 13 | + MT6323_CHIP_ID = 0x23, | |
| 14 | + MT6391_CHIP_ID = 0x91, | |
| 15 | + MT6397_CHIP_ID = 0x97, | |
| 16 | +}; | |
| 17 | + | |
| 10 | 18 | enum mt6397_irq_numbers { |
| 11 | 19 | MT6397_IRQ_SPKL_AB = 0, |
| 12 | 20 | MT6397_IRQ_SPKR_AB, |
| @@ -54,6 +62,9 @@ struct mt6397_chip { · 41 unmodified lines | ||
| 54 | 62 | u16 irq_masks_cache[2]; |
| 55 | 63 | u16 int_con[2]; |
| 56 | 64 | u16 int_status[2]; |
| 65 | + u16 chip_id; | |
| 57 | 66 | }; |
| 58 | 67 | |
| 68 | +int mt6397_irq_init(struct mt6397_chip *chip); | |
| 69 | + | |
| 59 | 70 | #endif /* __MFD_MT6397_CORE_H__ */ |
| @@ -5513,6 +5513,18 @@ struct ec_params_fp_seed { · 5512 unmodified lines | ||
| 5513 | 5513 | uint8_t seed[FP_CONTEXT_TPM_BYTES]; |
| 5514 | 5514 | } __ec_align4; |
| 5515 | 5515 | |
| 5516 | +#define EC_CMD_FP_ENC_STATUS 0x0409 | |
| 5517 | + | |
| 5518 | +/* FP TPM seed has been set or not */ | |
| 5519 | +#define FP_ENC_STATUS_SEED_SET BIT(0) | |
| 5520 | + | |
| 5521 | +struct ec_response_fp_encryption_status { | |
| 5522 | + /* Used bits in encryption engine status */ | |
| 5523 | + uint32_t valid_flags; | |
| 5524 | + /* Encryption engine status */ | |
| 5525 | + uint32_t status; | |
| 5526 | +} __ec_align4; | |
| 5527 | + | |
| 5516 | 5528 | /*****************************************************************************/ |
| 5517 | 5529 | /* Touchpad MCU commands: range 0x0500-0x05FF */ |
| 5518 | 5530 | |