History

Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux

Pull clk updates from Stephen Boyd: "We've finally gotten rid of the struct clk_ops::round_rate() code after months of effort from Brian Masney. Now the only option is to use determine_rate(), which is good because that takes a struct argument instead of just a couple unsigned longs, allowing us to easily modify the way we determine and set rates in the clk tree. Beyond that core framework change we've got the typical pile of new SoC clk driver additions, fixes for clk data and/or adding missing clks because the consumer driver using those clks wasn't ready, etc. The usual suspects are all here: Qualcomm, Samsung, Mediatek, and Rockchip along with some newcomers making RISC-V SoCs like ESWIN's eic700 and Tenstorrent's Atlantis. The clk driver side of this looks pretty normal. Core: - Remove the round_rate() clk op (yay!) New Drivers: - ESWIN eic700 SoC clk support - Econet EN751221 SoC clock/reset support - Global TCSR, RPMh, and display clock controller support for the Qualcomm Eliza platform - TCSR, the multiple global, and the RPMh clock controller support for the Qualcomm Nord platform - GPU clock controller support for Qualcomm SM8750 - Video and GPU clock controller support for Qualcomm Glymur - Global clock controller support for Qualcomm IPQ5210 - Axis ARTPEC-9: Add new PLL clocks and new drivers for eight clock controllers on the SoC - ExynosAutov920: Add G3D (GPU) clock controller - Clock driver for the Rockchip RV1103B SoC - Initial support for the Renesas RZ/G3L (R9A08G046) SoC - Clock and reset controllers (e.g. PRCM) in the Tenstorrent Atlantis SoC" * tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (132 commits) clk: visconti: pll: initialize clk_init_data to zero clk: fsl-sai: Add MCLK generation support clk: fsl-sai: Extract clock setup into fsl_sai_clk_register() dt-bindings: clock: fsl-sai: Document clock-cells = <1> support clk: fsl-sai: Add i.MX8M support with 8 byte register offset clk: fsl-sai: Sort the headers dt-bindings: clock: fsl-sai: Document i.MX8M support clk: qcom: gcc: Add multiple global clock controller driver for Nord SoC clk: qcom: rpmh: Add support for Nord rpmh clocks clk: qcom: Add TCSR clock driver for Nord SoC dt-bindings: clock: qcom: Add Nord Global Clock Controller dt-bindings: clock: qcom-rpmhcc: Add support for Nord SoCs dt-bindings: clock: qcom: Document the Nord SoC TCSR Clock Controller clk: qcom: gcc-x1e80100: Keep GCC USB QTB clock always ON clk: qcom: Constify list of critical CBCR registers clk: qcom: Constify qcom_cc_driver_data clk: qcom: videocc-glymur: Constify qcom_cc_desc clk: qcom: Add a driver for SM8750 GPU clocks dt-bindings: clock: qcom: Add SM8750 GPU clocks clk: qcom: ipq-cmn-pll: Add IPQ8074 SoC support ...

Linus Torvalds committed 6 months ago

Commit 4ee64202 parents a85d6ff 6b701fd179 files · +24821 −3464Browse files

Showing the changes to include/linux (1 of 179 files). Show all

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include/linux/clk-provider.h+26−40
@@ -136,10 +136,6 @@ struct clk_duty { · 135 unmodified lines
136136 * 0. Returns the calculated rate. Optional, but recommended - if
137137 * this op is not set then clock rate will be initialized to 0.
138138 *
139− * @round_rate: Given a target rate as input, returns the closest rate actually
140− * supported by the clock. The parent rate is an input/output
141− * parameter.
142− *
143139 * @determine_rate: Given a target rate as input, returns the closest rate
144140 * actually supported by the clock, and optionally the parent clock
145141 * that should be used to provide the clock rate.
@@ -163,13 +159,13 @@ struct clk_duty { · 17 unmodified lines
163159 *
164160 * @set_rate: Change the rate of this clock. The requested rate is specified
165161 * by the second argument, which should typically be the return
166− * of .round_rate call. The third argument gives the parent rate
167− * which is likely helpful for most .set_rate implementation.
162+ * of .determine_rate call. The third argument gives the parent
163+ * rate which is likely helpful for most .set_rate implementation.
168164 * Returns 0 on success, -EERROR otherwise.
169165 *
170166 * @set_rate_and_parent: Change the rate and the parent of this clock. The
171167 * requested rate is specified by the second argument, which
172− * should typically be the return of .round_rate call. The
168+ * should typically be the return of clk_round_rate() call. The
173169 * third argument gives the parent rate which is likely helpful
174170 * for most .set_rate_and_parent implementation. The fourth
175171 * argument gives the parent index. This callback is optional (and
@@ -244,8 +240,6 @@ struct clk_ops { · 68 unmodified lines
244240 void (*restore_context)(struct clk_hw *hw);
245241 unsigned long (*recalc_rate)(struct clk_hw *hw,
246242 unsigned long parent_rate);
247− long (*round_rate)(struct clk_hw *hw, unsigned long rate,
248− unsigned long *parent_rate);
249243 int (*determine_rate)(struct clk_hw *hw,
250244 struct clk_rate_request *req);
251245 int (*set_parent)(struct clk_hw *hw, u8 index);
@@ -679,7 +673,7 @@ struct clk_div_table { · 427 unmodified lines
679673 * @lock: register lock
680674 *
681675 * Clock with an adjustable divider affecting its output frequency. Implements
682− * .recalc_rate, .set_rate and .round_rate
676+ * .recalc_rate, .set_rate and .determine_rate
683677 *
684678 * @flags:
685679 * CLK_DIVIDER_ONE_BASED - by default the divisor is the value read from the
@@ -739,14 +733,6 @@ extern const struct clk_ops clk_divider_ro_ops; · 53 unmodified lines
739733 unsigned long divider_recalc_rate(struct clk_hw *hw, unsigned long parent_rate,
740734 unsigned int val, const struct clk_div_table *table,
741735 unsigned long flags, unsigned long width);
742−long divider_round_rate_parent(struct clk_hw *hw, struct clk_hw *parent,
743− unsigned long rate, unsigned long *prate,
744− const struct clk_div_table *table,
745− u8 width, unsigned long flags);
746−long divider_ro_round_rate_parent(struct clk_hw *hw, struct clk_hw *parent,
747− unsigned long rate, unsigned long *prate,
748− const struct clk_div_table *table, u8 width,
749− unsigned long flags, unsigned int val);
750736 int divider_determine_rate(struct clk_hw *hw, struct clk_rate_request *req,
751737 const struct clk_div_table *table, u8 width,
752738 unsigned long flags);
@@ -947,6 +933,26 @@ struct clk *clk_register_divider_table(struct device *dev, const char *name, · 194 unmodified lines
947933 (parent_hw), NULL, (flags), (reg), \
948934 (shift), (width), (clk_divider_flags), \
949935 NULL, (lock))
936+/**
937+ * devm_clk_hw_register_divider_parent_data - register a divider clock with the
938+ * clock framework
939+ * @dev: device registering this clock
940+ * @name: name of this clock
941+ * @parent_data: parent clk data
942+ * @flags: framework-specific flags
943+ * @reg: register address to adjust divider
944+ * @shift: number of bits to shift the bitfield
945+ * @width: width of the bitfield
946+ * @clk_divider_flags: divider-specific flags for this clock
947+ * @lock: shared register lock for this clock
948+ */
949+#define devm_clk_hw_register_divider_parent_data(dev, name, parent_data, \
950+ flags, reg, shift, width, \
951+ clk_divider_flags, lock) \
952+ __devm_clk_hw_register_divider((dev), NULL, (name), NULL, NULL, \
953+ (parent_data), (flags), (reg), (shift), \
954+ (width), (clk_divider_flags), NULL, \
955+ (lock))
950956 /**
951957 * devm_clk_hw_register_divider_table - register a table based divider clock
952958 * with the clock framework (devres variant)
@@ -1126,7 +1132,7 @@ void of_fixed_factor_clk_setup(struct device_node *node); · 173 unmodified lines
11261132 *
11271133 * Clock with a fixed multiplier and divider. The output frequency is the
11281134 * parent clock rate divided by div and multiplied by mult.
1129− * Implements .recalc_rate, .set_rate, .round_rate and .recalc_accuracy
1135+ * Implements .recalc_rate, .set_rate, .determine_rate and .recalc_accuracy
11301136 *
11311137 * Flags:
11321138 * * CLK_FIXED_FACTOR_FIXED_ACCURACY - Use the value in @acc instead of the
@@ -1254,7 +1260,7 @@ void clk_hw_unregister_fractional_divider(struct clk_hw *hw); · 121 unmodified lines
12541260 * @lock: register lock
12551261 *
12561262 * Clock with an adjustable multiplier affecting its output frequency.
1257− * Implements .recalc_rate, .set_rate and .round_rate
1263+ * Implements .recalc_rate, .set_rate and .determine_rate
12581264 *
12591265 * @flags:
12601266 * CLK_MULTIPLIER_ZERO_BYPASS - By default, the multiplier is the value read
@@ -1437,26 +1443,6 @@ static inline void __clk_hw_set_clk(struct clk_hw *dst, struct clk_hw *src) · 176 unmodified lines
14371443 dst->core = src->core;
14381444 }
14391445
1440−static inline long divider_round_rate(struct clk_hw *hw, unsigned long rate,
1441− unsigned long *prate,
1442− const struct clk_div_table *table,
1443− u8 width, unsigned long flags)
1444−{
1445− return divider_round_rate_parent(hw, clk_hw_get_parent(hw),
1446− rate, prate, table, width, flags);
1447−}
1448−
1449−static inline long divider_ro_round_rate(struct clk_hw *hw, unsigned long rate,
1450− unsigned long *prate,
1451− const struct clk_div_table *table,
1452− u8 width, unsigned long flags,
1453− unsigned int val)
1454−{
1455− return divider_ro_round_rate_parent(hw, clk_hw_get_parent(hw),
1456− rate, prate, table, width, flags,
1457− val);
1458−}
1459−
14601446 /*
14611447 * FIXME clock api without lock protection
14621448 */