Merge tag 'drm-xe-next-fixes-2025-06-05' of https://gitlab.freedesktop.org/drm/xe/kernel into drm-next

Driver Changes: - A couple of vm init fixes (Matt Auld) - Hwmon fixes (Karthik) - Drop reduntant conversion to bool (Raag) - Fix CONFIG_INTEL_VSEC dependency (Arnd) - Rework eviction rejection of bound external bos (Thomas) - Stop re-submitting signalled jobs (Matt Auld) - A couple of pxp fixes (Daniele) - Add back a fix that got lost in a merge (Matt Auld) - Create LRC bo without VM (Niranjana) - Fix for the above fix (Maciej) Signed-off-by: Dave Airlie <airlied@redhat.com>

Dave Airlie committed 1 year ago

Commit 4f577be2 parents 27bba88 7c7c5cb21 files · +491 −186Browse files

Unified · Split

21 files

Documentation/ABI/testing/sysfs-driver-intel-xe-hwmon +10 −10
drivers/gpu/drm/xe/Kconfig +2 −1
drivers/gpu/drm/xe/regs/xe_mchbar_regs.h +5 −5
drivers/gpu/drm/xe/regs/xe_pcode_regs.h +0 −4
drivers/gpu/drm/xe/xe_bo.c +29 −19
drivers/gpu/drm/xe/xe_device_sysfs.c +1 −1
drivers/gpu/drm/xe/xe_device_types.h +4 −0
drivers/gpu/drm/xe/xe_exec_queue.c +1 −14
drivers/gpu/drm/xe/xe_gpu_scheduler.h +9 −1
drivers/gpu/drm/xe/xe_guc_submit.c +11 −0
drivers/gpu/drm/xe/xe_hwmon.c +285 −99
drivers/gpu/drm/xe/xe_lrc.c +4 −19
drivers/gpu/drm/xe/xe_pci.c +5 −0
drivers/gpu/drm/xe/xe_pcode.c +11 −0
drivers/gpu/drm/xe/xe_pcode.h +3 −0
drivers/gpu/drm/xe/xe_pcode_api.h +7 −0
drivers/gpu/drm/xe/xe_pxp.c +6 −2
drivers/gpu/drm/xe/xe_vm.c +16 −11
drivers/gpu/drm/xe/xe_vm.h +69 −0
drivers/gpu/drm/xe/xe_vm_types.h +8 −0
include/uapi/drm/xe_drm.h +5 −0

Documentation/ABI/testing/sysfs-driver-intel-xe-hwmon+10−10

@@ -60,26 +60,26 @@ Description: RO. Package default power limit (default TDP setting). · 59 unmodified lines
60	60
61	61	Only supported for particular Intel Xe graphics platforms.
62	62
63		−What: /sys/bus/pci/drivers/xe/.../hwmon/hwmon<i>/power2_crit
64		−Date: February 2024
65		−KernelVersion: 6.8
	63	+What: /sys/bus/pci/drivers/xe/.../hwmon/hwmon<i>/power1_crit
	64	+Date: May 2025
	65	+KernelVersion: 6.15
66	66	Contact: intel-xe@lists.freedesktop.org
67		−Description: RW. Package reactive critical (I1) power limit in microwatts.
	67	+Description: RW. Card reactive critical (I1) power limit in microwatts.
68	68
69		− Package reactive critical (I1) power limit in microwatts is exposed
	69	+ Card reactive critical (I1) power limit in microwatts is exposed
70	70	for client products. The power controller will throttle the
71	71	operating frequency if the power averaged over a window exceeds
72	72	this limit.
73	73
74	74	Only supported for particular Intel Xe graphics platforms.
75	75
76		−What: /sys/bus/pci/drivers/xe/.../hwmon/hwmon<i>/curr2_crit
77		−Date: February 2024
78		−KernelVersion: 6.8
	76	+What: /sys/bus/pci/drivers/xe/.../hwmon/hwmon<i>/curr1_crit
	77	+Date: May 2025
	78	+KernelVersion: 6.15
79	79	Contact: intel-xe@lists.freedesktop.org
80		−Description: RW. Package reactive critical (I1) power limit in milliamperes.
	80	+Description: RW. Card reactive critical (I1) power limit in milliamperes.
81	81
82		− Package reactive critical (I1) power limit in milliamperes is
	82	+ Card reactive critical (I1) power limit in milliamperes is
83	83	exposed for server products. The power controller will throttle
84	84	the operating frequency if the power averaged over a window
85	85	exceeds this limit.

drivers/gpu/drm/xe/Kconfig+2−1

@@ -2,6 +2,8 @@ · 1 unmodified line
2	2	config DRM_XE
3	3	tristate "Intel Xe Graphics"
4	4	depends on DRM && PCI && MMU && (m \|\| (y && KUNIT=y))
	5	+ depends on INTEL_VSEC \|\| !INTEL_VSEC
	6	+ depends on X86_PLATFORM_DEVICES \|\| !(X86 && ACPI)
5	7	select INTERVAL_TREE
6	8	# we need shmfs for the swappable backing store, and in particular
7	9	# the shmem_readpage() which depends upon tmpfs
@@ -27,7 +29,6 @@ config DRM_XE · 19 unmodified lines
27	29	select BACKLIGHT_CLASS_DEVICE if ACPI
28	30	select INPUT if ACPI
29	31	select ACPI_VIDEO if X86 && ACPI
30		− select X86_PLATFORM_DEVICES if X86 && ACPI
31	32	select ACPI_WMI if X86 && ACPI
32	33	select SYNC_FILE
33	34	select IOSF_MBI

drivers/gpu/drm/xe/regs/xe_mchbar_regs.h+5−5

@@ -38,10 +38,10 @@ · 37 unmodified lines
38	38	#define TEMP_MASK REG_GENMASK(7, 0)
39	39
40	40	#define PCU_CR_PACKAGE_RAPL_LIMIT XE_REG(MCHBAR_MIRROR_BASE_SNB + 0x59a0)
41		−#define PKG_PWR_LIM_1 REG_GENMASK(14, 0)
42		−#define PKG_PWR_LIM_1_EN REG_BIT(15)
43		−#define PKG_PWR_LIM_1_TIME REG_GENMASK(23, 17)
44		−#define PKG_PWR_LIM_1_TIME_X REG_GENMASK(23, 22)
45		−#define PKG_PWR_LIM_1_TIME_Y REG_GENMASK(21, 17)
	41	+#define PWR_LIM_VAL REG_GENMASK(14, 0)
	42	+#define PWR_LIM_EN REG_BIT(15)
	43	+#define PWR_LIM_TIME REG_GENMASK(23, 17)
	44	+#define PWR_LIM_TIME_X REG_GENMASK(23, 22)
	45	+#define PWR_LIM_TIME_Y REG_GENMASK(21, 17)
46	46
47	47	#endif /* _XE_MCHBAR_REGS_H_ */

drivers/gpu/drm/xe/regs/xe_pcode_regs.h+0−4

@@ -18,16 +18,12 @@ · 17 unmodified lines
18	18	#define PVC_GT0_PLATFORM_ENERGY_STATUS XE_REG(0x28106c)
19	19	#define PVC_GT0_PACKAGE_POWER_SKU XE_REG(0x281080)
20	20
21		−#define BMG_PACKAGE_POWER_SKU XE_REG(0x138098)
22		−#define BMG_PACKAGE_POWER_SKU_UNIT XE_REG(0x1380dc)
23	21	#define BMG_PACKAGE_ENERGY_STATUS XE_REG(0x138120)
24	22	#define BMG_FAN_1_SPEED XE_REG(0x138140)
25	23	#define BMG_FAN_2_SPEED XE_REG(0x138170)
26	24	#define BMG_FAN_3_SPEED XE_REG(0x1381a0)
27	25	#define BMG_VRAM_TEMPERATURE XE_REG(0x1382c0)
28	26	#define BMG_PACKAGE_TEMPERATURE XE_REG(0x138434)
29		−#define BMG_PACKAGE_RAPL_LIMIT XE_REG(0x138440)
30	27	#define BMG_PLATFORM_ENERGY_STATUS XE_REG(0x138458)
31		−#define BMG_PLATFORM_POWER_LIMIT XE_REG(0x138460)
32	28
33	29	#endif /* _XE_PCODE_REGS_H_ */

drivers/gpu/drm/xe/xe_bo.c+29−19

@@ -841,21 +841,6 @@ static int xe_bo_move(struct ttm_buffer_object *ttm_bo, bool evict, · 840 unmodified lines
841	841	goto out;
842	842	}
843	843
844		− /* Reject BO eviction if BO is bound to current VM. */
845		− if (evict && ctx->resv) {
846		− struct drm_gpuvm_bo *vm_bo;
847		−
848		− drm_gem_for_each_gpuvm_bo(vm_bo, &bo->ttm.base) {
849		− struct xe_vm *vm = gpuvm_to_vm(vm_bo->vm);
850		−
851		− if (xe_vm_resv(vm) == ctx->resv &&
852		− xe_vm_in_preempt_fence_mode(vm)) {
853		− ret = -EBUSY;
854		− goto out;
855		− }
856		− }
857		− }
858		−
859	844	/*
860	845	* Failed multi-hop where the old_mem is still marked as
861	846	* TTM_PL_FLAG_TEMPORARY, should just be a dummy move.
@@ -1013,6 +998,25 @@ static long xe_bo_shrink_purge(struct ttm_operation_ctx *ctx, · 151 unmodified lines
1013	998	return lret;
1014	999	}
1015	1000
	1001	+static bool
	1002	+xe_bo_eviction_valuable(struct ttm_buffer_object bo, const struct ttm_place place)
	1003	+{
	1004	+ struct drm_gpuvm_bo *vm_bo;
	1005	+
	1006	+ if (!ttm_bo_eviction_valuable(bo, place))
	1007	+ return false;
	1008	+
	1009	+ if (!xe_bo_is_xe_bo(bo))
	1010	+ return true;
	1011	+
	1012	+ drm_gem_for_each_gpuvm_bo(vm_bo, &bo->base) {
	1013	+ if (xe_vm_is_validating(gpuvm_to_vm(vm_bo->vm)))
	1014	+ return false;
	1015	+ }
	1016	+
	1017	+ return true;
	1018	+}
	1019	+
1016	1020	/**
1017	1021	* xe_bo_shrink() - Try to shrink an xe bo.
1018	1022	* @ctx: The struct ttm_operation_ctx used for shrinking.
@@ -1047,7 +1051,7 @@ long xe_bo_shrink(struct ttm_operation_ctx ctx, struct ttm_buffer_object bo, · 28 unmodified lines
1047	1051	(flags.purge && !xe_tt->purgeable))
1048	1052	return -EBUSY;
1049	1053
1050		− if (!ttm_bo_eviction_valuable(bo, &place))
	1054	+ if (!xe_bo_eviction_valuable(bo, &place))
1051	1055	return -EBUSY;
1052	1056
1053	1057	if (!xe_bo_is_xe_bo(bo) \|\| !xe_bo_get_unless_zero(xe_bo))
@@ -1588,7 +1592,7 @@ const struct ttm_device_funcs xe_ttm_funcs = { · 534 unmodified lines
1588	1592	.io_mem_pfn = xe_ttm_io_mem_pfn,
1589	1593	.access_memory = xe_ttm_access_memory,
1590	1594	.release_notify = xe_ttm_bo_release_notify,
1591		− .eviction_valuable = ttm_bo_eviction_valuable,
	1595	+ .eviction_valuable = xe_bo_eviction_valuable,
1592	1596	.delete_mem_notify = xe_ttm_bo_delete_mem_notify,
1593	1597	.swap_notify = xe_ttm_bo_swap_notify,
1594	1598	};
@@ -2431,6 +2435,8 @@ int xe_bo_validate(struct xe_bo bo, struct xe_vm vm, bool allow_res_evict) · 836 unmodified lines
2431	2435	.no_wait_gpu = false,
2432	2436	.gfp_retry_mayfail = true,
2433	2437	};
	2438	+ struct pin_cookie cookie;
	2439	+ int ret;
2434	2440
2435	2441	if (vm) {
2436	2442	lockdep_assert_held(&vm->lock);
@@ -2440,8 +2446,12 @@ int xe_bo_validate(struct xe_bo bo, struct xe_vm vm, bool allow_res_evict) · 3 unmodified lines
2440	2446	ctx.resv = xe_vm_resv(vm);
2441	2447	}
2442	2448
	2449	+ cookie = xe_vm_set_validating(vm, allow_res_evict);
2443	2450	trace_xe_bo_validate(bo);
2444		− return ttm_bo_validate(&bo->ttm, &bo->placement, &ctx);
	2451	+ ret = ttm_bo_validate(&bo->ttm, &bo->placement, &ctx);
	2452	+ xe_vm_clear_validating(vm, allow_res_evict, cookie);
	2453	+
	2454	+ return ret;
2445	2455	}
2446	2456
2447	2457	bool xe_bo_is_xe_bo(struct ttm_buffer_object *bo)
@@ -2557,7 +2567,7 @@ typedef int (xe_gem_create_set_property_fn)(struct xe_device xe, · 109 unmodified lines
2557	2567	u64 value);
2558	2568
2559	2569	static const xe_gem_create_set_property_fn gem_create_set_property_funcs[] = {
2560		− [DRM_XE_GEM_CREATE_EXTENSION_SET_PROPERTY] = gem_create_set_pxp_type,
	2570	+ [DRM_XE_GEM_CREATE_SET_PROPERTY_PXP_TYPE] = gem_create_set_pxp_type,
2561	2571	};
2562	2572
2563	2573	static int gem_create_user_ext_set_property(struct xe_device *xe,

drivers/gpu/drm/xe/xe_device_sysfs.c+1−1

@@ -115,7 +115,7 @@ auto_link_downgrade_capable_show(struct device dev, struct device_attribute at · 114 unmodified lines
115	115	xe_pm_runtime_put(xe);
116	116
117	117	cap = REG_FIELD_GET(LINK_DOWNGRADE, val);
118		− return sysfs_emit(buf, "%u\n", cap == DOWNGRADE_CAPABLE ? true : false);
	118	+ return sysfs_emit(buf, "%u\n", cap == DOWNGRADE_CAPABLE);
119	119	}
120	120	static DEVICE_ATTR_ADMIN_RO(auto_link_downgrade_capable);
121	121

drivers/gpu/drm/xe/xe_device_types.h+4−0

@@ -325,6 +325,10 @@ struct xe_device { · 324 unmodified lines
325	325	u8 has_heci_gscfi:1;
326	326	/** @info.has_llc: Device has a shared CPU+GPU last level cache */
327	327	u8 has_llc:1;
	328	+ /** @info.has_mbx_power_limits: Device has support to manage power limits using
	329	+ * pcode mailbox commands.
	330	+ */
	331	+ u8 has_mbx_power_limits:1;
328	332	/** @info.has_pxp: Device has PXP support */
329	333	u8 has_pxp:1;
330	334	/** @info.has_range_tlb_invalidation: Has range based TLB invalidations */

drivers/gpu/drm/xe/xe_exec_queue.c+1−14

@@ -114,7 +114,6 @@ static struct xe_exec_queue __xe_exec_queue_alloc(struct xe_device xe, · 113 unmodified lines
114	114
115	115	static int __xe_exec_queue_init(struct xe_exec_queue *q)
116	116	{
117		− struct xe_vm *vm = q->vm;
118	117	int i, err;
119	118	u32 flags = 0;
120	119
@@ -132,32 +131,20 @@ static int __xe_exec_queue_init(struct xe_exec_queue *q) · 11 unmodified lines
132	131	flags \|= XE_LRC_CREATE_RUNALONE;
133	132	}
134	133
135		− if (vm) {
136		− err = xe_vm_lock(vm, true);
137		− if (err)
138		− return err;
139		− }
140		−
141	134	for (i = 0; i < q->width; ++i) {
142	135	q->lrc[i] = xe_lrc_create(q->hwe, q->vm, SZ_16K, q->msix_vec, flags);
143	136	if (IS_ERR(q->lrc[i])) {
144	137	err = PTR_ERR(q->lrc[i]);
145		− goto err_unlock;
	138	+ goto err_lrc;
146	139	}
147	140	}
148	141
149		− if (vm)
150		− xe_vm_unlock(vm);
151		−
152	142	err = q->ops->init(q);
153	143	if (err)
154	144	goto err_lrc;
155	145
156	146	return 0;
157	147
158		−err_unlock:
159		− if (vm)
160		− xe_vm_unlock(vm);
161	148	err_lrc:
162	149	for (i = i - 1; i >= 0; --i)
163	150	xe_lrc_put(q->lrc[i]);

drivers/gpu/drm/xe/xe_gpu_scheduler.h+9−1

@@ -51,7 +51,15 @@ static inline void xe_sched_tdr_queue_imm(struct xe_gpu_scheduler *sched) · 50 unmodified lines
51	51
52	52	static inline void xe_sched_resubmit_jobs(struct xe_gpu_scheduler *sched)
53	53	{
54		− drm_sched_resubmit_jobs(&sched->base);
	54	+ struct drm_sched_job *s_job;
	55	+
	56	+ list_for_each_entry(s_job, &sched->base.pending_list, list) {
	57	+ struct drm_sched_fence *s_fence = s_job->s_fence;
	58	+ struct dma_fence *hw_fence = s_fence->parent;
	59	+
	60	+ if (hw_fence && !dma_fence_is_signaled(hw_fence))
	61	+ sched->base.ops->run_job(s_job);
	62	+ }
55	63	}
56	64
57	65	static inline bool

drivers/gpu/drm/xe/xe_guc_submit.c+11−0

@@ -229,6 +229,17 @@ static bool exec_queue_killed_or_banned_or_wedged(struct xe_exec_queue *q) · 228 unmodified lines
229	229	static void guc_submit_fini(struct drm_device drm, void arg)
230	230	{
231	231	struct xe_guc *guc = arg;
	232	+ struct xe_device *xe = guc_to_xe(guc);
	233	+ struct xe_gt *gt = guc_to_gt(guc);
	234	+ int ret;
	235	+
	236	+ ret = wait_event_timeout(guc->submission_state.fini_wq,
	237	+ xa_empty(&guc->submission_state.exec_queue_lookup),
	238	+ HZ * 5);
	239	+
	240	+ drain_workqueue(xe->destroy_wq);
	241	+
	242	+ xe_gt_assert(gt, ret);
232	243
233	244	xa_destroy(&guc->submission_state.exec_queue_lookup);
234	245	}

drivers/gpu/drm/xe/xe_hwmon.c+285−99

@@ -51,6 +51,14 @@ enum xe_fan_channel { · 50 unmodified lines
51	51	FAN_MAX,
52	52	};
53	53
	54	+/*
	55	+ * For platforms that support mailbox commands for power limits, REG_PKG_POWER_SKU_UNIT is
	56	+ * not supported and below are SKU units to be used.
	57	+ */
	58	+#define PWR_UNIT 0x3
	59	+#define ENERGY_UNIT 0xe
	60	+#define TIME_UNIT 0xa
	61	+
54	62	/*
55	63	* SF_* - scale factors for particular quantities according to hwmon spec.
56	64	*/
@@ -60,6 +68,18 @@ enum xe_fan_channel { · 3 unmodified lines
60	68	#define SF_ENERGY 1000000 /* microjoules */
61	69	#define SF_TIME 1000 /* milliseconds */
62	70
	71	+/*
	72	+ * PL*_HWMON_ATTR - mapping of hardware power limits to corresponding hwmon power attribute.
	73	+ */
	74	+#define PL1_HWMON_ATTR hwmon_power_max
	75	+
	76	+#define PWR_ATTR_TO_STR(attr) (((attr) == hwmon_power_max) ? "PL1" : "Invalid")
	77	+
	78	+/*
	79	+ * Timeout for power limit write mailbox command.
	80	+ */
	81	+#define PL_WRITE_MBX_TIMEOUT_MS (1)
	82	+
63	83	/**
64	84	* struct xe_hwmon_energy_info - to accumulate energy
65	85	*/
@@ -100,8 +120,80 @@ struct xe_hwmon { · 34 unmodified lines
100	120	struct xe_hwmon_energy_info ei[CHANNEL_MAX];
101	121	/** @fi: Fan info for fanN_input */
102	122	struct xe_hwmon_fan_info fi[FAN_MAX];
	123	+ /** @boot_power_limit_read: is boot power limits read */
	124	+ bool boot_power_limit_read;
	125	+ /** @pl1_on_boot: power limit PL1 on boot */
	126	+ u32 pl1_on_boot[CHANNEL_MAX];
103	127	};
104	128
	129	+static int xe_hwmon_pcode_read_power_limit(const struct xe_hwmon *hwmon, u32 attr, int channel,
	130	+ u32 *uval)
	131	+{
	132	+ struct xe_tile *root_tile = xe_device_get_root_tile(hwmon->xe);
	133	+ u32 val0 = 0, val1 = 0;
	134	+ int ret = 0;
	135	+
	136	+ ret = xe_pcode_read(root_tile, PCODE_MBOX(PCODE_POWER_SETUP,
	137	+ (channel == CHANNEL_CARD) ?
	138	+ READ_PSYSGPU_POWER_LIMIT :
	139	+ READ_PACKAGE_POWER_LIMIT,
	140	+ hwmon->boot_power_limit_read ?
	141	+ READ_PL_FROM_PCODE : READ_PL_FROM_FW),
	142	+ &val0, &val1);
	143	+
	144	+ if (ret) {
	145	+ drm_dbg(&hwmon->xe->drm, "read failed ch %d val0 0x%08x, val1 0x%08x, ret %d\n",
	146	+ channel, val0, val1, ret);
	147	+ *uval = 0;
	148	+ return ret;
	149	+ }
	150	+
	151	+ /* return the value only if limit is enabled */
	152	+ if (attr == PL1_HWMON_ATTR)
	153	+ *uval = (val0 & PWR_LIM_EN) ? val0 : 0;
	154	+ else if (attr == hwmon_power_label)
	155	+ *uval = (val0 & PWR_LIM_EN) ? 1 : 0;
	156	+ else
	157	+ *uval = 0;
	158	+
	159	+ return ret;
	160	+}
	161	+
	162	+static int xe_hwmon_pcode_write_power_limit(const struct xe_hwmon *hwmon, u32 attr, u8 channel,
	163	+ u32 uval)
	164	+{
	165	+ struct xe_tile *root_tile = xe_device_get_root_tile(hwmon->xe);
	166	+ u32 val0, val1;
	167	+ int ret = 0;
	168	+
	169	+ ret = xe_pcode_read(root_tile, PCODE_MBOX(PCODE_POWER_SETUP,
	170	+ (channel == CHANNEL_CARD) ?
	171	+ READ_PSYSGPU_POWER_LIMIT :
	172	+ READ_PACKAGE_POWER_LIMIT,
	173	+ hwmon->boot_power_limit_read ?
	174	+ READ_PL_FROM_PCODE : READ_PL_FROM_FW),
	175	+ &val0, &val1);
	176	+
	177	+ if (ret)
	178	+ drm_dbg(&hwmon->xe->drm, "read failed ch %d val0 0x%08x, val1 0x%08x, ret %d\n",
	179	+ channel, val0, val1, ret);
	180	+
	181	+ if (attr == PL1_HWMON_ATTR)
	182	+ val0 = uval;
	183	+ else
	184	+ return -EIO;
	185	+
	186	+ ret = xe_pcode_write64_timeout(root_tile, PCODE_MBOX(PCODE_POWER_SETUP,
	187	+ (channel == CHANNEL_CARD) ?
	188	+ WRITE_PSYSGPU_POWER_LIMIT :
	189	+ WRITE_PACKAGE_POWER_LIMIT, 0),
	190	+ val0, val1, PL_WRITE_MBX_TIMEOUT_MS);
	191	+ if (ret)
	192	+ drm_dbg(&hwmon->xe->drm, "write failed ch %d val0 0x%08x, val1 0x%08x, ret %d\n",
	193	+ channel, val0, val1, ret);
	194	+ return ret;
	195	+}
	196	+
105	197	static struct xe_reg xe_hwmon_get_reg(struct xe_hwmon *hwmon, enum xe_hwmon_reg hwmon_reg,
106	198	int channel)
107	199	{
@@ -122,29 +214,19 @@ static struct xe_reg xe_hwmon_get_reg(struct xe_hwmon *hwmon, enum xe_hwmon_reg · 14 unmodified lines
122	214	}
123	215	break;
124	216	case REG_PKG_RAPL_LIMIT:
125		− if (xe->info.platform == XE_BATTLEMAGE) {
126		− if (channel == CHANNEL_PKG)
127		− return BMG_PACKAGE_RAPL_LIMIT;
128		− else
129		− return BMG_PLATFORM_POWER_LIMIT;
130		− } else if (xe->info.platform == XE_PVC && channel == CHANNEL_PKG) {
	217	+ if (xe->info.platform == XE_PVC && channel == CHANNEL_PKG)
131	218	return PVC_GT0_PACKAGE_RAPL_LIMIT;
132		− } else if ((xe->info.platform == XE_DG2) && (channel == CHANNEL_PKG)) {
	219	+ else if ((xe->info.platform == XE_DG2) && (channel == CHANNEL_PKG))
133	220	return PCU_CR_PACKAGE_RAPL_LIMIT;
134		− }
135	221	break;
136	222	case REG_PKG_POWER_SKU:
137		− if (xe->info.platform == XE_BATTLEMAGE)
138		− return BMG_PACKAGE_POWER_SKU;
139		− else if (xe->info.platform == XE_PVC && channel == CHANNEL_PKG)
	223	+ if (xe->info.platform == XE_PVC && channel == CHANNEL_PKG)
140	224	return PVC_GT0_PACKAGE_POWER_SKU;
141	225	else if ((xe->info.platform == XE_DG2) && (channel == CHANNEL_PKG))
142	226	return PCU_CR_PACKAGE_POWER_SKU;
143	227	break;
144	228	case REG_PKG_POWER_SKU_UNIT:
145		− if (xe->info.platform == XE_BATTLEMAGE)
146		− return BMG_PACKAGE_POWER_SKU_UNIT;
147		− else if (xe->info.platform == XE_PVC)
	229	+ if (xe->info.platform == XE_PVC)
148	230	return PVC_GT0_PACKAGE_POWER_SKU_UNIT;
149	231	else if (xe->info.platform == XE_DG2)
150	232	return PCU_CR_PACKAGE_POWER_SKU_UNIT;
@@ -181,7 +263,7 @@ static struct xe_reg xe_hwmon_get_reg(struct xe_hwmon *hwmon, enum xe_hwmon_reg · 30 unmodified lines
181	263	return XE_REG(0);
182	264	}
183	265
184		−#define PL1_DISABLE 0
	266	+#define PL_DISABLE 0
185	267
186	268	/*
187	269	* HW allows arbitrary PL1 limits to be set but silently clamps these values to
@@ -189,67 +271,83 @@ static struct xe_reg xe_hwmon_get_reg(struct xe_hwmon *hwmon, enum xe_hwmon_reg · 1 unmodified line
189	271	* same pattern for sysfs, allow arbitrary PL1 limits to be set but display
190	272	* clamped values when read.
191	273	*/
192		−static void xe_hwmon_power_max_read(struct xe_hwmon hwmon, int channel, long value)
	274	+static void xe_hwmon_power_max_read(struct xe_hwmon hwmon, u32 attr, int channel, long value)
193	275	{
194	276	u64 reg_val, min, max;
195	277	struct xe_device *xe = hwmon->xe;
196	278	struct xe_reg rapl_limit, pkg_power_sku;
197	279	struct xe_mmio *mmio = xe_root_tile_mmio(xe);
198	280
199		− rapl_limit = xe_hwmon_get_reg(hwmon, REG_PKG_RAPL_LIMIT, channel);
200		− pkg_power_sku = xe_hwmon_get_reg(hwmon, REG_PKG_POWER_SKU, channel);
	281	+ mutex_lock(&hwmon->hwmon_lock);
201	282
202		− /*
203		− * Valid check of REG_PKG_RAPL_LIMIT is already done in xe_hwmon_power_is_visible.
204		− * So not checking it again here.
205		− */
206		− if (!xe_reg_is_valid(pkg_power_sku)) {
207		− drm_warn(&xe->drm, "pkg_power_sku invalid\n");
208		− *value = 0;
209		− return;
	283	+ if (hwmon->xe->info.has_mbx_power_limits) {
	284	+ xe_hwmon_pcode_read_power_limit(hwmon, attr, channel, (u32 *)&reg_val);
	285	+ } else {
	286	+ rapl_limit = xe_hwmon_get_reg(hwmon, REG_PKG_RAPL_LIMIT, channel);
	287	+ pkg_power_sku = xe_hwmon_get_reg(hwmon, REG_PKG_POWER_SKU, channel);
	288	+
	289	+ /*
	290	+ * Valid check of REG_PKG_RAPL_LIMIT is already done in xe_hwmon_power_is_visible.
	291	+ * So not checking it again here.
	292	+ */
	293	+ if (!xe_reg_is_valid(pkg_power_sku)) {
	294	+ drm_warn(&xe->drm, "pkg_power_sku invalid\n");
	295	+ *value = 0;
	296	+ goto unlock;
	297	+ }
	298	+ reg_val = xe_mmio_read32(mmio, rapl_limit);
210	299	}
211	300
212		− mutex_lock(&hwmon->hwmon_lock);
213		−
214		− reg_val = xe_mmio_read32(mmio, rapl_limit);
215		− /* Check if PL1 limit is disabled */
216		− if (!(reg_val & PKG_PWR_LIM_1_EN)) {
217		− *value = PL1_DISABLE;
	301	+ /* Check if PL limits are disabled. */
	302	+ if (!(reg_val & PWR_LIM_EN)) {
	303	+ *value = PL_DISABLE;
	304	+ drm_info(&hwmon->xe->drm, "%s disabled for channel %d, val 0x%016llx\n",
	305	+ PWR_ATTR_TO_STR(attr), channel, reg_val);
218	306	goto unlock;
219	307	}
220	308
221		− reg_val = REG_FIELD_GET(PKG_PWR_LIM_1, reg_val);
	309	+ reg_val = REG_FIELD_GET(PWR_LIM_VAL, reg_val);
222	310	*value = mul_u64_u32_shr(reg_val, SF_POWER, hwmon->scl_shift_power);
223	311
224		− reg_val = xe_mmio_read64_2x32(mmio, pkg_power_sku);
225		− min = REG_FIELD_GET(PKG_MIN_PWR, reg_val);
226		− min = mul_u64_u32_shr(min, SF_POWER, hwmon->scl_shift_power);
227		− max = REG_FIELD_GET(PKG_MAX_PWR, reg_val);
228		− max = mul_u64_u32_shr(max, SF_POWER, hwmon->scl_shift_power);
229		−
230		− if (min && max)
231		− value = clamp_t(u64, value, min, max);
	312	+ /* For platforms with mailbox power limit support clamping would be done by pcode. */
	313	+ if (!hwmon->xe->info.has_mbx_power_limits) {
	314	+ reg_val = xe_mmio_read64_2x32(mmio, pkg_power_sku);
	315	+ min = REG_FIELD_GET(PKG_MIN_PWR, reg_val);
	316	+ max = REG_FIELD_GET(PKG_MAX_PWR, reg_val);
	317	+ min = mul_u64_u32_shr(min, SF_POWER, hwmon->scl_shift_power);
	318	+ max = mul_u64_u32_shr(max, SF_POWER, hwmon->scl_shift_power);
	319	+ if (min && max)
	320	+ value = clamp_t(u64, value, min, max);
	321	+ }
232	322	unlock:
233	323	mutex_unlock(&hwmon->hwmon_lock);
234	324	}
235	325
236		−static int xe_hwmon_power_max_write(struct xe_hwmon *hwmon, int channel, long value)
	326	+static int xe_hwmon_power_max_write(struct xe_hwmon *hwmon, u32 attr, int channel, long value)
237	327	{
238	328	struct xe_mmio *mmio = xe_root_tile_mmio(hwmon->xe);
239	329	int ret = 0;
240		− u64 reg_val;
	330	+ u32 reg_val;
241	331	struct xe_reg rapl_limit;
242	332
	333	+ mutex_lock(&hwmon->hwmon_lock);
	334	+
243	335	rapl_limit = xe_hwmon_get_reg(hwmon, REG_PKG_RAPL_LIMIT, channel);
244	336
245		− mutex_lock(&hwmon->hwmon_lock);
	337	+ /* Disable Power Limit and verify, as limit cannot be disabled on all platforms. */
	338	+ if (value == PL_DISABLE) {
	339	+ if (hwmon->xe->info.has_mbx_power_limits) {
	340	+ drm_dbg(&hwmon->xe->drm, "disabling %s on channel %d\n",
	341	+ PWR_ATTR_TO_STR(attr), channel);
	342	+ xe_hwmon_pcode_write_power_limit(hwmon, attr, channel, 0);
	343	+ xe_hwmon_pcode_read_power_limit(hwmon, attr, channel, &reg_val);
	344	+ } else {
	345	+ reg_val = xe_mmio_rmw32(mmio, rapl_limit, PWR_LIM_EN, 0);
	346	+ reg_val = xe_mmio_read32(mmio, rapl_limit);
	347	+ }
246	348
247		− /* Disable PL1 limit and verify, as limit cannot be disabled on all platforms */
248		− if (value == PL1_DISABLE) {
249		− reg_val = xe_mmio_rmw32(mmio, rapl_limit, PKG_PWR_LIM_1_EN, 0);
250		− reg_val = xe_mmio_read32(mmio, rapl_limit);
251		− if (reg_val & PKG_PWR_LIM_1_EN) {
252		− drm_warn(&hwmon->xe->drm, "PL1 disable is not supported!\n");
	349	+ if (reg_val & PWR_LIM_EN) {
	350	+ drm_warn(&hwmon->xe->drm, "Power limit disable is not supported!\n");
253	351	ret = -EOPNOTSUPP;
254	352	}
255	353	goto unlock;
@@ -257,26 +355,50 @@ static int xe_hwmon_power_max_write(struct xe_hwmon *hwmon, int channel, long va · 1 unmodified line
257	355
258	356	/* Computation in 64-bits to avoid overflow. Round to nearest. */
259	357	reg_val = DIV_ROUND_CLOSEST_ULL((u64)value << hwmon->scl_shift_power, SF_POWER);
260		− reg_val = PKG_PWR_LIM_1_EN \| REG_FIELD_PREP(PKG_PWR_LIM_1, reg_val);
261		− reg_val = xe_mmio_rmw32(mmio, rapl_limit, PKG_PWR_LIM_1_EN \| PKG_PWR_LIM_1, reg_val);
	358	+ reg_val = PWR_LIM_EN \| REG_FIELD_PREP(PWR_LIM_VAL, reg_val);
262	359
	360	+ /*
	361	+ * Clamp power limit to card-firmware default as maximum, as an additional protection to
	362	+ * pcode clamp.
	363	+ */
	364	+ if (hwmon->xe->info.has_mbx_power_limits) {
	365	+ if (reg_val > REG_FIELD_GET(PWR_LIM_VAL, hwmon->pl1_on_boot[channel])) {
	366	+ reg_val = REG_FIELD_GET(PWR_LIM_VAL, hwmon->pl1_on_boot[channel]);
	367	+ drm_dbg(&hwmon->xe->drm, "Clamping power limit to firmware default 0x%x\n",
	368	+ reg_val);
	369	+ }
	370	+ }
	371	+
	372	+ if (hwmon->xe->info.has_mbx_power_limits)
	373	+ ret = xe_hwmon_pcode_write_power_limit(hwmon, attr, channel, reg_val);
	374	+ else
	375	+ reg_val = xe_mmio_rmw32(mmio, rapl_limit, PWR_LIM_EN \| PWR_LIM_VAL,
	376	+ reg_val);
263	377	unlock:
264	378	mutex_unlock(&hwmon->hwmon_lock);
265	379	return ret;
266	380	}
267	381
268		−static void xe_hwmon_power_rated_max_read(struct xe_hwmon hwmon, int channel, long value)
	382	+static void xe_hwmon_power_rated_max_read(struct xe_hwmon *hwmon, u32 attr, int channel,
	383	+ long *value)
269	384	{
270	385	struct xe_mmio *mmio = xe_root_tile_mmio(hwmon->xe);
271		− struct xe_reg reg = xe_hwmon_get_reg(hwmon, REG_PKG_POWER_SKU, channel);
272		− u64 reg_val;
	386	+ u32 reg_val;
	387	+
	388	+ if (hwmon->xe->info.has_mbx_power_limits) {
	389	+ /* PL1 is rated max if supported. */
	390	+ xe_hwmon_pcode_read_power_limit(hwmon, PL1_HWMON_ATTR, channel, &reg_val);
	391	+ } else {
	392	+ /*
	393	+ * This sysfs file won't be visible if REG_PKG_POWER_SKU is invalid, so valid check
	394	+ * for this register can be skipped.
	395	+ * See xe_hwmon_power_is_visible.
	396	+ */
	397	+ struct xe_reg reg = xe_hwmon_get_reg(hwmon, REG_PKG_POWER_SKU, channel);
	398	+
	399	+ reg_val = xe_mmio_read32(mmio, reg);
	400	+ }
273	401
274		− /*
275		− * This sysfs file won't be visible if REG_PKG_POWER_SKU is invalid, so valid check
276		− * for this register can be skipped.
277		− * See xe_hwmon_power_is_visible.
278		− */
279		− reg_val = xe_mmio_read32(mmio, reg);
280	402	reg_val = REG_FIELD_GET(PKG_TDP, reg_val);
281	403	*value = mul_u64_u32_shr(reg_val, SF_POWER, hwmon->scl_shift_power);
282	404	}
@@ -330,23 +452,35 @@ xe_hwmon_power_max_interval_show(struct device dev, struct device_attribute at · 47 unmodified lines
330	452	struct xe_mmio *mmio = xe_root_tile_mmio(hwmon->xe);
331	453	u32 x, y, x_w = 2; /* 2 bits */
332	454	u64 r, tau4, out;
333		− int sensor_index = to_sensor_dev_attr(attr)->index;
	455	+ int channel = to_sensor_dev_attr(attr)->index;
	456	+ u32 power_attr = PL1_HWMON_ATTR;
	457	+ int ret = 0;
334	458
335	459	xe_pm_runtime_get(hwmon->xe);
336	460
337	461	mutex_lock(&hwmon->hwmon_lock);
338	462
339		− r = xe_mmio_read32(mmio, xe_hwmon_get_reg(hwmon, REG_PKG_RAPL_LIMIT, sensor_index));
	463	+ if (hwmon->xe->info.has_mbx_power_limits) {
	464	+ ret = xe_hwmon_pcode_read_power_limit(hwmon, power_attr, channel, (u32 *)&r);
	465	+ if (ret) {
	466	+ drm_err(&hwmon->xe->drm,
	467	+ "power interval read fail, ch %d, attr %d, r 0%llx, ret %d\n",
	468	+ channel, power_attr, r, ret);
	469	+ r = 0;
	470	+ }
	471	+ } else {
	472	+ r = xe_mmio_read32(mmio, xe_hwmon_get_reg(hwmon, REG_PKG_RAPL_LIMIT, channel));
	473	+ }
340	474
341	475	mutex_unlock(&hwmon->hwmon_lock);
342	476
343	477	xe_pm_runtime_put(hwmon->xe);
344	478
345		− x = REG_FIELD_GET(PKG_PWR_LIM_1_TIME_X, r);
346		− y = REG_FIELD_GET(PKG_PWR_LIM_1_TIME_Y, r);
	479	+ x = REG_FIELD_GET(PWR_LIM_TIME_X, r);
	480	+ y = REG_FIELD_GET(PWR_LIM_TIME_Y, r);
347	481
348	482	/*
349		− * tau = 1.x * power(2,y), x = bits(23:22), y = bits(21:17)
	483	+ * tau = (1 + (x / 4)) * power(2,y), x = bits(23:22), y = bits(21:17)
350	484	* = (4 \| x) << (y - 2)
351	485	*
352	486	* Here (y - 2) ensures a 1.x fixed point representation of 1.x
@@ -373,14 +507,15 @@ xe_hwmon_power_max_interval_store(struct device dev, struct device_attribute a · 20 unmodified lines
373	507	u64 tau4, r, max_win;
374	508	unsigned long val;
375	509	int ret;
376		− int sensor_index = to_sensor_dev_attr(attr)->index;
	510	+ int channel = to_sensor_dev_attr(attr)->index;
	511	+ u32 power_attr = PL1_HWMON_ATTR;
377	512
378	513	ret = kstrtoul(buf, 0, &val);
379	514	if (ret)
380	515	return ret;
381	516
382	517	/*
383		− * Max HW supported tau in '1.x * power(2,y)' format, x = 0, y = 0x12.
	518	+ * Max HW supported tau in '(1 + (x / 4)) * power(2,y)' format, x = 0, y = 0x12.
384	519	* The hwmon->scl_shift_time default of 0xa results in a max tau of 256 seconds.
385	520	*
386	521	* The ideal scenario is for PKG_MAX_WIN to be read from the PKG_PWR_SKU register.
@@ -400,11 +535,13 @@ xe_hwmon_power_max_interval_store(struct device dev, struct device_attribute a · 13 unmodified lines
400	535	tau4 = (u64)((1 << x_w) \| x) << y;
401	536	max_win = mul_u64_u32_shr(tau4, SF_TIME, hwmon->scl_shift_time + x_w);
402	537
403		− if (val > max_win)
	538	+ if (val > max_win) {
	539	+ drm_warn(&hwmon->xe->drm, "power_interval invalid val 0x%lx\n", val);
404	540	return -EINVAL;
	541	+ }
405	542
406	543	/* val in hw units */
407		− val = DIV_ROUND_CLOSEST_ULL((u64)val << hwmon->scl_shift_time, SF_TIME);
	544	+ val = DIV_ROUND_CLOSEST_ULL((u64)val << hwmon->scl_shift_time, SF_TIME) + 1;
408	545
409	546	/*
410	547	* Convert val to 1.x * power(2,y)
@@ -419,14 +556,21 @@ xe_hwmon_power_max_interval_store(struct device dev, struct device_attribute a · 8 unmodified lines
419	556	x = (val - (1ul << y)) << x_w >> y;
420	557	}
421	558
422		− rxy = REG_FIELD_PREP(PKG_PWR_LIM_1_TIME_X, x) \| REG_FIELD_PREP(PKG_PWR_LIM_1_TIME_Y, y);
	559	+ rxy = REG_FIELD_PREP(PWR_LIM_TIME_X, x) \|
	560	+ REG_FIELD_PREP(PWR_LIM_TIME_Y, y);
423	561
424	562	xe_pm_runtime_get(hwmon->xe);
425	563
426	564	mutex_lock(&hwmon->hwmon_lock);
427	565
428		− r = xe_mmio_rmw32(mmio, xe_hwmon_get_reg(hwmon, REG_PKG_RAPL_LIMIT, sensor_index),
429		− PKG_PWR_LIM_1_TIME, rxy);
	566	+ if (hwmon->xe->info.has_mbx_power_limits) {
	567	+ ret = xe_hwmon_pcode_read_power_limit(hwmon, power_attr, channel, (u32 *)&r);
	568	+ r = (r & ~PWR_LIM_TIME) \| rxy;
	569	+ xe_hwmon_pcode_write_power_limit(hwmon, power_attr, channel, r);
	570	+ } else {
	571	+ r = xe_mmio_rmw32(mmio, xe_hwmon_get_reg(hwmon, REG_PKG_RAPL_LIMIT, channel),
	572	+ PWR_LIM_TIME, rxy);
	573	+ }
430	574
431	575	mutex_unlock(&hwmon->hwmon_lock);
432	576
@@ -435,6 +579,7 @@ xe_hwmon_power_max_interval_store(struct device dev, struct device_attribute a · 2 unmodified lines
435	579	return count;
436	580	}
437	581
	582	+/* PSYS PL1 */
438	583	static SENSOR_DEVICE_ATTR(power1_max_interval, 0664,
439	584	xe_hwmon_power_max_interval_show,
440	585	xe_hwmon_power_max_interval_store, CHANNEL_CARD);
@@ -455,10 +600,19 @@ static umode_t xe_hwmon_attributes_visible(struct kobject *kobj, · 14 unmodified lines
455	600	struct device *dev = kobj_to_dev(kobj);
456	601	struct xe_hwmon *hwmon = dev_get_drvdata(dev);
457	602	int ret = 0;
	603	+ int channel = index ? CHANNEL_PKG : CHANNEL_CARD;
	604	+ u32 power_attr = PL1_HWMON_ATTR;
	605	+ u32 uval;
458	606
459	607	xe_pm_runtime_get(hwmon->xe);
460	608
461		− ret = xe_reg_is_valid(xe_hwmon_get_reg(hwmon, REG_PKG_RAPL_LIMIT, index)) ? attr->mode : 0;
	609	+ if (hwmon->xe->info.has_mbx_power_limits) {
	610	+ xe_hwmon_pcode_read_power_limit(hwmon, power_attr, channel, &uval);
	611	+ ret = (uval & PWR_LIM_EN) ? attr->mode : 0;
	612	+ } else {
	613	+ ret = xe_reg_is_valid(xe_hwmon_get_reg(hwmon, REG_PKG_RAPL_LIMIT,
	614	+ channel)) ? attr->mode : 0;
	615	+ }
462	616
463	617	xe_pm_runtime_put(hwmon->xe);
464	618
@@ -478,8 +632,8 @@ static const struct attribute_group *hwmon_groups[] = { · 13 unmodified lines
478	632	static const struct hwmon_channel_info * const hwmon_info[] = {
479	633	HWMON_CHANNEL_INFO(temp, HWMON_T_LABEL, HWMON_T_INPUT \| HWMON_T_LABEL,
480	634	HWMON_T_INPUT \| HWMON_T_LABEL),
481		− HWMON_CHANNEL_INFO(power, HWMON_P_MAX \| HWMON_P_RATED_MAX \| HWMON_P_LABEL,
482		− HWMON_P_MAX \| HWMON_P_RATED_MAX \| HWMON_P_CRIT \| HWMON_P_LABEL),
	635	+ HWMON_CHANNEL_INFO(power, HWMON_P_MAX \| HWMON_P_RATED_MAX \| HWMON_P_LABEL \| HWMON_P_CRIT,
	636	+ HWMON_P_MAX \| HWMON_P_RATED_MAX \| HWMON_P_LABEL),
483	637	HWMON_CHANNEL_INFO(curr, HWMON_C_LABEL, HWMON_C_CRIT \| HWMON_C_LABEL),
484	638	HWMON_CHANNEL_INFO(in, HWMON_I_INPUT \| HWMON_I_LABEL, HWMON_I_INPUT \| HWMON_I_LABEL),
485	639	HWMON_CHANNEL_INFO(energy, HWMON_E_INPUT \| HWMON_E_LABEL, HWMON_E_INPUT \| HWMON_E_LABEL),
@@ -604,19 +758,27 @@ xe_hwmon_power_is_visible(struct xe_hwmon *hwmon, u32 attr, int channel) · 118 unmodified lines
604	758
605	759	switch (attr) {
606	760	case hwmon_power_max:
607		− return xe_reg_is_valid(xe_hwmon_get_reg(hwmon, REG_PKG_RAPL_LIMIT,
	761	+ if (hwmon->xe->info.has_mbx_power_limits) {
	762	+ xe_hwmon_pcode_read_power_limit(hwmon, attr, channel, &uval);
	763	+ return (uval) ? 0664 : 0;
	764	+ } else {
	765	+ return xe_reg_is_valid(xe_hwmon_get_reg(hwmon, REG_PKG_RAPL_LIMIT,
608	766	channel)) ? 0664 : 0;
	767	+ }
609	768	case hwmon_power_rated_max:
610		− return xe_reg_is_valid(xe_hwmon_get_reg(hwmon, REG_PKG_POWER_SKU,
611		− channel)) ? 0444 : 0;
	769	+ if (hwmon->xe->info.has_mbx_power_limits)
	770	+ return 0;
	771	+ else
	772	+ return xe_reg_is_valid(xe_hwmon_get_reg(hwmon, REG_PKG_POWER_SKU,
	773	+ channel)) ? 0444 : 0;
612	774	case hwmon_power_crit:
613		− if (channel == CHANNEL_PKG)
614		− return (xe_hwmon_pcode_read_i1(hwmon, &uval) \|\|
615		− !(uval & POWER_SETUP_I1_WATTS)) ? 0 : 0644;
616		− break;
617	775	case hwmon_power_label:
618		− return xe_reg_is_valid(xe_hwmon_get_reg(hwmon, REG_PKG_POWER_SKU_UNIT,
619		− channel)) ? 0444 : 0;
	776	+ if (channel == CHANNEL_CARD) {
	777	+ xe_hwmon_pcode_read_i1(hwmon, &uval);
	778	+ return (uval & POWER_SETUP_I1_WATTS) ? (attr == hwmon_power_label) ?
	779	+ 0444 : 0644 : 0;
	780	+ }
	781	+ break;
620	782	default:
621	783	return 0;
622	784	}
@@ -628,10 +790,10 @@ xe_hwmon_power_read(struct xe_hwmon hwmon, u32 attr, int channel, long val) · 5 unmodified lines
628	790	{
629	791	switch (attr) {
630	792	case hwmon_power_max:
631		− xe_hwmon_power_max_read(hwmon, channel, val);
	793	+ xe_hwmon_power_max_read(hwmon, attr, channel, val);
632	794	return 0;
633	795	case hwmon_power_rated_max:
634		− xe_hwmon_power_rated_max_read(hwmon, channel, val);
	796	+ xe_hwmon_power_rated_max_read(hwmon, attr, channel, val);
635	797	return 0;
636	798	case hwmon_power_crit:
637	799	return xe_hwmon_power_curr_crit_read(hwmon, channel, val, SF_POWER);
@@ -645,7 +807,7 @@ xe_hwmon_power_write(struct xe_hwmon *hwmon, u32 attr, int channel, long val) · 7 unmodified lines
645	807	{
646	808	switch (attr) {
647	809	case hwmon_power_max:
648		− return xe_hwmon_power_max_write(hwmon, channel, val);
	810	+ return xe_hwmon_power_max_write(hwmon, attr, channel, val);
649	811	case hwmon_power_crit:
650	812	return xe_hwmon_power_curr_crit_write(hwmon, channel, val, SF_POWER);
651	813	default:
@@ -965,18 +1127,42 @@ xe_hwmon_get_preregistration_info(struct xe_hwmon *hwmon) · 313 unmodified lines
965	1127	int channel;
966	1128	struct xe_reg pkg_power_sku_unit;
967	1129
968		− /*
969		− * The contents of register PKG_POWER_SKU_UNIT do not change,
970		− * so read it once and store the shift values.
971		− */
972		− pkg_power_sku_unit = xe_hwmon_get_reg(hwmon, REG_PKG_POWER_SKU_UNIT, 0);
973		− if (xe_reg_is_valid(pkg_power_sku_unit)) {
974		− val_sku_unit = xe_mmio_read32(mmio, pkg_power_sku_unit);
975		− hwmon->scl_shift_power = REG_FIELD_GET(PKG_PWR_UNIT, val_sku_unit);
976		− hwmon->scl_shift_energy = REG_FIELD_GET(PKG_ENERGY_UNIT, val_sku_unit);
977		− hwmon->scl_shift_time = REG_FIELD_GET(PKG_TIME_UNIT, val_sku_unit);
	1130	+ if (hwmon->xe->info.has_mbx_power_limits) {
	1131	+ /* Check if card firmware support mailbox power limits commands. */
	1132	+ if (xe_hwmon_pcode_read_power_limit(hwmon, PL1_HWMON_ATTR, CHANNEL_CARD,
	1133	+ &hwmon->pl1_on_boot[CHANNEL_CARD]) \|
	1134	+ xe_hwmon_pcode_read_power_limit(hwmon, PL1_HWMON_ATTR, CHANNEL_PKG,
	1135	+ &hwmon->pl1_on_boot[CHANNEL_PKG])) {
	1136	+ drm_warn(&hwmon->xe->drm,
	1137	+ "Failed to read power limits, check card firmware !\n");
	1138	+ } else {
	1139	+ drm_info(&hwmon->xe->drm, "Using mailbox commands for power limits\n");
	1140	+ /* Write default limits to read from pcode from now on. */
	1141	+ xe_hwmon_pcode_write_power_limit(hwmon, PL1_HWMON_ATTR,
	1142	+ CHANNEL_CARD,
	1143	+ hwmon->pl1_on_boot[CHANNEL_CARD]);
	1144	+ xe_hwmon_pcode_write_power_limit(hwmon, PL1_HWMON_ATTR,
	1145	+ CHANNEL_PKG,
	1146	+ hwmon->pl1_on_boot[CHANNEL_PKG]);
	1147	+ hwmon->scl_shift_power = PWR_UNIT;
	1148	+ hwmon->scl_shift_energy = ENERGY_UNIT;
	1149	+ hwmon->scl_shift_time = TIME_UNIT;
	1150	+ hwmon->boot_power_limit_read = true;
	1151	+ }
	1152	+ } else {
	1153	+ drm_info(&hwmon->xe->drm, "Using register for power limits\n");
	1154	+ /*
	1155	+ * The contents of register PKG_POWER_SKU_UNIT do not change,
	1156	+ * so read it once and store the shift values.
	1157	+ */
	1158	+ pkg_power_sku_unit = xe_hwmon_get_reg(hwmon, REG_PKG_POWER_SKU_UNIT, 0);
	1159	+ if (xe_reg_is_valid(pkg_power_sku_unit)) {
	1160	+ val_sku_unit = xe_mmio_read32(mmio, pkg_power_sku_unit);
	1161	+ hwmon->scl_shift_power = REG_FIELD_GET(PKG_PWR_UNIT, val_sku_unit);
	1162	+ hwmon->scl_shift_energy = REG_FIELD_GET(PKG_ENERGY_UNIT, val_sku_unit);
	1163	+ hwmon->scl_shift_time = REG_FIELD_GET(PKG_TIME_UNIT, val_sku_unit);
	1164	+ }
978	1165	}
979		−
980	1166	/*
981	1167	* Initialize 'struct xe_hwmon_energy_info', i.e. set fields to the
982	1168	* first value of the energy register read

drivers/gpu/drm/xe/xe_lrc.c+4−19

@@ -876,10 +876,7 @@ static void xe_lrc_set_ppgtt(struct xe_lrc lrc, struct xe_vm vm) · 875 unmodified lines
876	876	static void xe_lrc_finish(struct xe_lrc *lrc)
877	877	{
878	878	xe_hw_fence_ctx_finish(&lrc->fence_ctx);
879		− xe_bo_lock(lrc->bo, false);
880		− xe_bo_unpin(lrc->bo);
881		− xe_bo_unlock(lrc->bo);
882		− xe_bo_put(lrc->bo);
	879	+ xe_bo_unpin_map_no_vm(lrc->bo);
883	880	}
884	881
885	882	#define PVC_CTX_ASID (0x2e + 1)
@@ -914,7 +911,7 @@ static int xe_lrc_init(struct xe_lrc lrc, struct xe_hw_engine hwe, · 28 unmodified lines
914	911	* FIXME: Perma-pinning LRC as we don't yet support moving GGTT address
915	912	* via VM bind calls.
916	913	*/
917		− lrc->bo = xe_bo_create_pin_map(xe, tile, vm, lrc_size,
	914	+ lrc->bo = xe_bo_create_pin_map(xe, tile, NULL, lrc_size,
918	915	ttm_bo_type_kernel,
919	916	bo_flags);
920	917	if (IS_ERR(lrc->bo))
@@ -1676,9 +1673,6 @@ struct xe_lrc_snapshot xe_lrc_snapshot_capture(struct xe_lrc lrc) · 755 unmodified lines
1676	1673	if (!snapshot)
1677	1674	return NULL;
1678	1675
1679		− if (lrc->bo->vm)
1680		− xe_vm_get(lrc->bo->vm);
1681		−
1682	1676	snapshot->context_desc = xe_lrc_ggtt_addr(lrc);
1683	1677	snapshot->ring_addr = __xe_lrc_ring_ggtt_addr(lrc);
1684	1678	snapshot->indirect_context_desc = xe_lrc_indirect_ring_ggtt_addr(lrc);
@@ -1700,14 +1694,12 @@ struct xe_lrc_snapshot xe_lrc_snapshot_capture(struct xe_lrc lrc) · 15 unmodified lines
1700	1694	void xe_lrc_snapshot_capture_delayed(struct xe_lrc_snapshot *snapshot)
1701	1695	{
1702	1696	struct xe_bo *bo;
1703		− struct xe_vm *vm;
1704	1697	struct iosys_map src;
1705	1698
1706	1699	if (!snapshot)
1707	1700	return;
1708	1701
1709	1702	bo = snapshot->lrc_bo;
1710		− vm = bo->vm;
1711	1703	snapshot->lrc_bo = NULL;
1712	1704
1713	1705	snapshot->lrc_snapshot = kvmalloc(snapshot->lrc_size, GFP_KERNEL);
@@ -1727,8 +1719,6 @@ void xe_lrc_snapshot_capture_delayed(struct xe_lrc_snapshot *snapshot) · 13 unmodified lines
1727	1719	xe_bo_unlock(bo);
1728	1720	put_bo:
1729	1721	xe_bo_put(bo);
1730		− if (vm)
1731		− xe_vm_put(vm);
1732	1722	}
1733	1723
1734	1724	void xe_lrc_snapshot_print(struct xe_lrc_snapshot snapshot, struct drm_printer p)
@@ -1781,14 +1771,9 @@ void xe_lrc_snapshot_free(struct xe_lrc_snapshot *snapshot) · 46 unmodified lines
1781	1771	return;
1782	1772
1783	1773	kvfree(snapshot->lrc_snapshot);
1784		− if (snapshot->lrc_bo) {
1785		− struct xe_vm *vm;
1786		−
1787		− vm = snapshot->lrc_bo->vm;
	1774	+ if (snapshot->lrc_bo)
1788	1775	xe_bo_put(snapshot->lrc_bo);
1789		− if (vm)
1790		− xe_vm_put(vm);
1791		− }
	1776	+
1792	1777	kfree(snapshot);
1793	1778	}
1794	1779

drivers/gpu/drm/xe/xe_pci.c+5−0

@@ -66,6 +66,7 @@ struct xe_device_desc { · 65 unmodified lines
66	66	u8 has_heci_gscfi:1;
67	67	u8 has_heci_cscfi:1;
68	68	u8 has_llc:1;
	69	+ u8 has_mbx_power_limits:1;
69	70	u8 has_pxp:1;
70	71	u8 has_sriov:1;
71	72	u8 needs_scratch:1;
@@ -305,6 +306,7 @@ static const struct xe_device_desc dg2_desc = { · 233 unmodified lines
305	306	DG2_FEATURES,
306	307	.has_display = true,
307	308	.has_fan_control = true,
	309	+ .has_mbx_power_limits = false,
308	310	};
309	311
310	312	static const __maybe_unused struct xe_device_desc pvc_desc = {
@@ -316,6 +318,7 @@ static const __maybe_unused struct xe_device_desc pvc_desc = { · 5 unmodified lines
316	318	.has_heci_gscfi = 1,
317	319	.max_remote_tiles = 1,
318	320	.require_force_probe = true,
	321	+ .has_mbx_power_limits = false,
319	322	};
320	323
321	324	static const struct xe_device_desc mtl_desc = {
@@ -341,6 +344,7 @@ static const struct xe_device_desc bmg_desc = { · 19 unmodified lines
341	344	.dma_mask_size = 46,
342	345	.has_display = true,
343	346	.has_fan_control = true,
	347	+ .has_mbx_power_limits = true,
344	348	.has_heci_cscfi = 1,
345	349	.needs_scratch = true,
346	350	};
@@ -583,6 +587,7 @@ static int xe_info_init_early(struct xe_device *xe, · 236 unmodified lines
583	587	xe->info.dma_mask_size = desc->dma_mask_size;
584	588	xe->info.is_dgfx = desc->is_dgfx;
585	589	xe->info.has_fan_control = desc->has_fan_control;
	590	+ xe->info.has_mbx_power_limits = desc->has_mbx_power_limits;
586	591	xe->info.has_heci_gscfi = desc->has_heci_gscfi;
587	592	xe->info.has_heci_cscfi = desc->has_heci_cscfi;
588	593	xe->info.has_llc = desc->has_llc;

drivers/gpu/drm/xe/xe_pcode.c+11−0

@@ -109,6 +109,17 @@ int xe_pcode_write_timeout(struct xe_tile *tile, u32 mbox, u32 data, int timeout · 108 unmodified lines
109	109	return err;
110	110	}
111	111
	112	+int xe_pcode_write64_timeout(struct xe_tile *tile, u32 mbox, u32 data0, u32 data1, int timeout)
	113	+{
	114	+ int err;
	115	+
	116	+ mutex_lock(&tile->pcode.lock);
	117	+ err = pcode_mailbox_rw(tile, mbox, &data0, &data1, timeout, false, false);
	118	+ mutex_unlock(&tile->pcode.lock);
	119	+
	120	+ return err;
	121	+}
	122	+
112	123	int xe_pcode_read(struct xe_tile tile, u32 mbox, u32 val, u32 *val1)
113	124	{
114	125	int err;

drivers/gpu/drm/xe/xe_pcode.h+3−0

@@ -18,6 +18,9 @@ int xe_pcode_init_min_freq_table(struct xe_tile *tile, u32 min_gt_freq, · 17 unmodified lines
18	18	int xe_pcode_read(struct xe_tile tile, u32 mbox, u32 val, u32 *val1);
19	19	int xe_pcode_write_timeout(struct xe_tile *tile, u32 mbox, u32 val,
20	20	int timeout_ms);
	21	+int xe_pcode_write64_timeout(struct xe_tile *tile, u32 mbox, u32 data0,
	22	+ u32 data1, int timeout);
	23	+
21	24	#define xe_pcode_write(tile, mbox, val) \
22	25	xe_pcode_write_timeout(tile, mbox, val, 1)
23	26

drivers/gpu/drm/xe/xe_pcode_api.h+7−0

@@ -43,6 +43,13 @@ · 42 unmodified lines
43	43	#define POWER_SETUP_I1_SHIFT 6 /* 10.6 fixed point format */
44	44	#define POWER_SETUP_I1_DATA_MASK REG_GENMASK(15, 0)
45	45
	46	+#define READ_PSYSGPU_POWER_LIMIT 0x6
	47	+#define WRITE_PSYSGPU_POWER_LIMIT 0x7
	48	+#define READ_PACKAGE_POWER_LIMIT 0x8
	49	+#define WRITE_PACKAGE_POWER_LIMIT 0x9
	50	+#define READ_PL_FROM_FW 0x1
	51	+#define READ_PL_FROM_PCODE 0x0
	52	+
46	53	#define PCODE_FREQUENCY_CONFIG 0x6e
47	54	/* Frequency Config Sub Commands (param1) */
48	55	#define PCODE_MBOX_FC_SC_READ_FUSED_P0 0x0

drivers/gpu/drm/xe/xe_pxp.c+6−2

@@ -541,10 +541,14 @@ int xe_pxp_exec_queue_add(struct xe_pxp pxp, struct xe_exec_queue q) · 540 unmodified lines
541	541	*/
542	542	xe_pm_runtime_get(pxp->xe);
543	543
544		− if (!pxp_prerequisites_done(pxp)) {
545		− ret = -EBUSY;
	544	+ /* get_readiness_status() returns 0 for in-progress and 1 for done */
	545	+ ret = xe_pxp_get_readiness_status(pxp);
	546	+ if (ret <= 0) {
	547	+ if (!ret)
	548	+ ret = -EBUSY;
546	549	goto out;
547	550	}
	551	+ ret = 0;
548	552
549	553	wait_for_idle:
550	554	/*

drivers/gpu/drm/xe/xe_vm.c+16−11

@@ -1678,13 +1678,21 @@ struct xe_vm xe_vm_create(struct xe_device xe, u32 flags) · 1677 unmodified lines
1678	1678	* scheduler drops all the references of it, hence protecting the VM
1679	1679	* for this case is necessary.
1680	1680	*/
1681		− if (flags & XE_VM_FLAG_LR_MODE)
	1681	+ if (flags & XE_VM_FLAG_LR_MODE) {
	1682	+ INIT_WORK(&vm->preempt.rebind_work, preempt_rebind_work_func);
1682	1683	xe_pm_runtime_get_noresume(xe);
	1684	+ }
	1685	+
	1686	+ if (flags & XE_VM_FLAG_FAULT_MODE) {
	1687	+ err = xe_svm_init(vm);
	1688	+ if (err)
	1689	+ goto err_no_resv;
	1690	+ }
1683	1691
1684	1692	vm_resv_obj = drm_gpuvm_resv_object_alloc(&xe->drm);
1685	1693	if (!vm_resv_obj) {
1686	1694	err = -ENOMEM;
1687		− goto err_no_resv;
	1695	+ goto err_svm_fini;
1688	1696	}
1689	1697
1690	1698	drm_gpuvm_init(&vm->gpuvm, "Xe VM", DRM_GPUVM_RESV_PROTECTED, &xe->drm,
@@ -1724,10 +1732,8 @@ struct xe_vm xe_vm_create(struct xe_device xe, u32 flags) · 33 unmodified lines
1724	1732	vm->batch_invalidate_tlb = true;
1725	1733	}
1726	1734
1727		− if (vm->flags & XE_VM_FLAG_LR_MODE) {
1728		− INIT_WORK(&vm->preempt.rebind_work, preempt_rebind_work_func);
	1735	+ if (vm->flags & XE_VM_FLAG_LR_MODE)
1729	1736	vm->batch_invalidate_tlb = false;
1730		− }
1731	1737
1732	1738	/* Fill pt_root after allocating scratch tables */
1733	1739	for_each_tile(tile, xe, id) {
@@ -1757,12 +1763,6 @@ struct xe_vm xe_vm_create(struct xe_device xe, u32 flags) · 23 unmodified lines
1757	1763	}
1758	1764	}
1759	1765
1760		− if (flags & XE_VM_FLAG_FAULT_MODE) {
1761		− err = xe_svm_init(vm);
1762		− if (err)
1763		− goto err_close;
1764		− }
1765		−
1766	1766	if (number_tiles > 1)
1767	1767	vm->composite_fence_ctx = dma_fence_context_alloc(1);
1768	1768
@@ -1776,6 +1776,11 @@ err_close: · 7 unmodified lines
1776	1776	xe_vm_close_and_put(vm);
1777	1777	return ERR_PTR(err);
1778	1778
	1779	+err_svm_fini:
	1780	+ if (flags & XE_VM_FLAG_FAULT_MODE) {
	1781	+ vm->size = 0; /* close the vm */
	1782	+ xe_svm_fini(vm);
	1783	+ }
1779	1784	err_no_resv:
1780	1785	mutex_destroy(&vm->snap_mutex);
1781	1786	for_each_tile(tile, xe, id)

drivers/gpu/drm/xe/xe_vm.h+69−0

@@ -301,6 +301,75 @@ void xe_vm_snapshot_capture_delayed(struct xe_vm_snapshot *snap); · 300 unmodified lines
301	301	void xe_vm_snapshot_print(struct xe_vm_snapshot snap, struct drm_printer p);
302	302	void xe_vm_snapshot_free(struct xe_vm_snapshot *snap);
303	303
	304	+/**
	305	+ * xe_vm_set_validating() - Register this task as currently making bos resident
	306	+ * @allow_res_evict: Allow eviction of buffer objects bound to @vm when
	307	+ * validating.
	308	+ * @vm: Pointer to the vm or NULL.
	309	+ *
	310	+ * Register this task as currently making bos resident for the vm. Intended
	311	+ * to avoid eviction by the same task of shared bos bound to the vm.
	312	+ * Call with the vm's resv lock held.
	313	+ *
	314	+ * Return: A pin cookie that should be used for xe_vm_clear_validating().
	315	+ */
	316	+static inline struct pin_cookie xe_vm_set_validating(struct xe_vm *vm,
	317	+ bool allow_res_evict)
	318	+{
	319	+ struct pin_cookie cookie = {};
	320	+
	321	+ if (vm && !allow_res_evict) {
	322	+ xe_vm_assert_held(vm);
	323	+ cookie = lockdep_pin_lock(&xe_vm_resv(vm)->lock.base);
	324	+ /* Pairs with READ_ONCE in xe_vm_is_validating() */
	325	+ WRITE_ONCE(vm->validating, current);
	326	+ }
	327	+
	328	+ return cookie;
	329	+}
	330	+
	331	+/**
	332	+ * xe_vm_clear_validating() - Unregister this task as currently making bos resident
	333	+ * @vm: Pointer to the vm or NULL
	334	+ * @allow_res_evict: Eviction from @vm was allowed. Must be set to the same
	335	+ * value as for xe_vm_set_validation().
	336	+ * @cookie: Cookie obtained from xe_vm_set_validating().
	337	+ *
	338	+ * Register this task as currently making bos resident for the vm. Intended
	339	+ * to avoid eviction by the same task of shared bos bound to the vm.
	340	+ * Call with the vm's resv lock held.
	341	+ */
	342	+static inline void xe_vm_clear_validating(struct xe_vm *vm, bool allow_res_evict,
	343	+ struct pin_cookie cookie)
	344	+{
	345	+ if (vm && !allow_res_evict) {
	346	+ lockdep_unpin_lock(&xe_vm_resv(vm)->lock.base, cookie);
	347	+ /* Pairs with READ_ONCE in xe_vm_is_validating() */
	348	+ WRITE_ONCE(vm->validating, NULL);
	349	+ }
	350	+}
	351	+
	352	+/**
	353	+ * xe_vm_is_validating() - Whether bos bound to the vm are currently being made resident
	354	+ * by the current task.
	355	+ * @vm: Pointer to the vm.
	356	+ *
	357	+ * If this function returns %true, we should be in a vm resv locked region, since
	358	+ * the current process is the same task that called xe_vm_set_validating().
	359	+ * The function asserts that that's indeed the case.
	360	+ *
	361	+ * Return: %true if the task is currently making bos resident, %false otherwise.
	362	+ */
	363	+static inline bool xe_vm_is_validating(struct xe_vm *vm)
	364	+{
	365	+ /* Pairs with WRITE_ONCE in xe_vm_is_validating() */
	366	+ if (READ_ONCE(vm->validating) == current) {
	367	+ xe_vm_assert_held(vm);
	368	+ return true;
	369	+ }
	370	+ return false;
	371	+}
	372	+
304	373	#if IS_ENABLED(CONFIG_DRM_XE_USERPTR_INVAL_INJECT)
305	374	void xe_vma_userptr_force_invalidate(struct xe_userptr_vma *uvma);
306	375	#else

drivers/gpu/drm/xe/xe_vm_types.h+8−0

@@ -310,6 +310,14 @@ struct xe_vm { · 309 unmodified lines
310	310	* protected by the vm resv.
311	311	*/
312	312	u64 tlb_flush_seqno;
	313	+ /**
	314	+ * @validating: The task that is currently making bos resident for this vm.
	315	+ * Protected by the VM's resv for writing. Opportunistic reading can be done
	316	+ * using READ_ONCE. Note: This is a workaround for the
	317	+ * TTM eviction_valuable() callback not being passed a struct
	318	+ * ttm_operation_context(). Future work might want to address this.
	319	+ */
	320	+ struct task_struct *validating;
313	321	/** @batch_invalidate_tlb: Always invalidate TLB before batch start */
314	322	bool batch_invalidate_tlb;
315	323	/** @xef: XE file handle for tracking this VM's drm client */

include/uapi/drm/xe_drm.h+5−0

@@ -1210,6 +1210,11 @@ struct drm_xe_vm_bind { · 1209 unmodified lines
1210	1210	* there is no need to explicitly set that. When a queue of type
1211	1211	* %DRM_XE_PXP_TYPE_HWDRM is created, the PXP default HWDRM session
1212	1212	* (%XE_PXP_HWDRM_DEFAULT_SESSION) will be started, if isn't already running.
	1213	+ * The user is expected to query the PXP status via the query ioctl (see
	1214	+ * %DRM_XE_DEVICE_QUERY_PXP_STATUS) and to wait for PXP to be ready before
	1215	+ * attempting to create a queue with this property. When a queue is created
	1216	+ * before PXP is ready, the ioctl will return -EBUSY if init is still in
	1217	+ * progress or -EIO if init failed.
1213	1218	* Given that going into a power-saving state kills PXP HWDRM sessions,
1214	1219	* runtime PM will be blocked while queues of this type are alive.
1215	1220	* All PXP queues will be killed if a PXP invalidation event occurs.