Pull MMC updates from Ulf Hansson: "It's been an busy period for mmc. Quite some changes in the mmc core, two new mmc host drivers, some existing drivers being extended to support new IP versions and lots of other updates. MMC core: - Delete eMMC packed command support - Introduce mmc_abort_tuning() to enable eMMC tuning to fail gracefully - Introduce mmc_can_retune() to see if a host can be retuned - Re-work and improve the sequence when sending a CMD6 for mmc - Enable CDM13 polling when switching to HS and HS DDR mode for mmc - Relax checking for CMD6 errors after switch to HS200 - Re-factoring the code dealing with the mmc block queue - Recognize whether the eMMC card supports CMDQ - Fix 4K native sector check - Don't power off the card when starting the host - Increase MMC_IOC_MAX_BYTES to support bigger firmware binaries - Improve error handling and drop meaningless BUG_ONs() - Lots of clean-ups and changes to improve the quality of the code MMC host: - sdhci: Fix tuning sequence and clean-up the related code - sdhci: Add support to via DT override broken SDHCI cap register bits - sdhci-cadence: Add new driver for Cadence SD4HC SDHCI variant - sdhci-msm: Update clock management - sdhci-msm: Add support for eMMC HS400 mode - sdhci-msm: Deploy runtime/system PM support - sdhci-iproc: Extend driver support to newer IP versions - sdhci-pci: Add support for Intel GLK - sdhci-pci: Add support for Intel NI byt sdio - sdhci-acpi: Add support for 80860F14 UID 2 SDIO bus - sdhci: Lots of various small improvements and clean-ups - tmio: Add support for tuning - sh_mobile_sdhi: Add support for tuning - sh_mobile_sdhi: Extend driver to support SDHI IP on R7S72100 SoC - sh_mobile_sdhi: remove support for sh7372 - davinci: Use mmc_of_parse() to enable generic mmc DT bindings - meson: Add new driver to support GX platforms - dw_mmc: Deploy generic runtime/system PM support - dw_mmc: Lots of various small improvements As a part of the mmc changes this time, I have also pulled in an immutable branch/tag (soc-device-match-tag1) hosted by Geert Uytterhoeven, to share the implementation of the new soc_device_match() interface. This is needed by these mmc related changes: - mmc: sdhci-of-esdhc: Get correct IP version for T4240-R1.0-R2.0 - soc: fsl: add GUTS driver for QorIQ platforms" * tag 'mmc-v4.10' of git://git.kernel.org/pub/scm/linux/kernel/git/ulfh/mmc: (136 commits) mmc: sdhci-cadence: add Cadence SD4HC support mmc: sdhci: export sdhci_execute_tuning() mmc: sdhci: Tidy tuning loop mmc: sdhci: Simplify tuning block size logic mmc: sdhci: Factor out tuning helper functions mmc: sdhci: Use mmc_abort_tuning() mmc: mmc: Introduce mmc_abort_tuning() mmc: sdhci: Always allow tuning to fall back to fixed sampling mmc: sdhci: Fix tuning reset after exhausting the maximum number of loops mmc: sdhci: Fix recovery from tuning timeout Revert "mmc: sdhci: Reset cmd and data circuits after tuning failure" mmc: mmc: Relax checking for switch errors after HS200 switch mmc: sdhci-acpi: support 80860F14 UID 2 SDIO bus mmc: sdhci-of-at91: remove bogus MMC_SDHCI_IO_ACCESSORS select mmc: sdhci-pci: Use ACPI to get max frequency for Intel NI byt sdio mmc: sdhci-pci: Add PCI ID for Intel NI byt sdio mmc: sdhci-s3c: add spin_unlock_irq() before calling clk_round_rate mmc: dw_mmc: display the clock message only one time when card is polling mmc: dw_mmc: add the debug message for polling and non-removable mmc: dw_mmc: check the "present" variable before checking flags ...
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| @@ -29,83 +29,112 @@ · 28 unmodified lines | ||
| 29 | 29 | * #ifdefs. |
| 30 | 30 | */ |
| 31 | 31 | struct ccsr_guts { |
| 32 | − __be32 porpllsr; /* 0x.0000 - POR PLL Ratio Status Register */ | |
| 33 | − __be32 porbmsr; /* 0x.0004 - POR Boot Mode Status Register */ | |
| 34 | − __be32 porimpscr; /* 0x.0008 - POR I/O Impedance Status and Control Register */ | |
| 35 | − __be32 pordevsr; /* 0x.000c - POR I/O Device Status Register */ | |
| 36 | − __be32 pordbgmsr; /* 0x.0010 - POR Debug Mode Status Register */ | |
| 37 | − __be32 pordevsr2; /* 0x.0014 - POR device status register 2 */ | |
| 32 | + u32 porpllsr; /* 0x.0000 - POR PLL Ratio Status Register */ | |
| 33 | + u32 porbmsr; /* 0x.0004 - POR Boot Mode Status Register */ | |
| 34 | + u32 porimpscr; /* 0x.0008 - POR I/O Impedance Status and | |
| 35 | + * Control Register | |
| 36 | + */ | |
| 37 | + u32 pordevsr; /* 0x.000c - POR I/O Device Status Register */ | |
| 38 | + u32 pordbgmsr; /* 0x.0010 - POR Debug Mode Status Register */ | |
| 39 | + u32 pordevsr2; /* 0x.0014 - POR device status register 2 */ | |
| 38 | 40 | u8 res018[0x20 - 0x18]; |
| 39 | − __be32 porcir; /* 0x.0020 - POR Configuration Information Register */ | |
| 41 | + u32 porcir; /* 0x.0020 - POR Configuration Information | |
| 42 | + * Register | |
| 43 | + */ | |
| 40 | 44 | u8 res024[0x30 - 0x24]; |
| 41 | − __be32 gpiocr; /* 0x.0030 - GPIO Control Register */ | |
| 45 | + u32 gpiocr; /* 0x.0030 - GPIO Control Register */ | |
| 42 | 46 | u8 res034[0x40 - 0x34]; |
| 43 | − __be32 gpoutdr; /* 0x.0040 - General-Purpose Output Data Register */ | |
| 47 | + u32 gpoutdr; /* 0x.0040 - General-Purpose Output Data | |
| 48 | + * Register | |
| 49 | + */ | |
| 44 | 50 | u8 res044[0x50 - 0x44]; |
| 45 | − __be32 gpindr; /* 0x.0050 - General-Purpose Input Data Register */ | |
| 51 | + u32 gpindr; /* 0x.0050 - General-Purpose Input Data | |
| 52 | + * Register | |
| 53 | + */ | |
| 46 | 54 | u8 res054[0x60 - 0x54]; |
| 47 | − __be32 pmuxcr; /* 0x.0060 - Alternate Function Signal Multiplex Control */ | |
| 48 | − __be32 pmuxcr2; /* 0x.0064 - Alternate function signal multiplex control 2 */ | |
| 49 | − __be32 dmuxcr; /* 0x.0068 - DMA Mux Control Register */ | |
| 55 | + u32 pmuxcr; /* 0x.0060 - Alternate Function Signal | |
| 56 | + * Multiplex Control | |
| 57 | + */ | |
| 58 | + u32 pmuxcr2; /* 0x.0064 - Alternate function signal | |
| 59 | + * multiplex control 2 | |
| 60 | + */ | |
| 61 | + u32 dmuxcr; /* 0x.0068 - DMA Mux Control Register */ | |
| 50 | 62 | u8 res06c[0x70 - 0x6c]; |
| 51 | − __be32 devdisr; /* 0x.0070 - Device Disable Control */ | |
| 63 | + u32 devdisr; /* 0x.0070 - Device Disable Control */ | |
| 52 | 64 | #define CCSR_GUTS_DEVDISR_TB1 0x00001000 |
| 53 | 65 | #define CCSR_GUTS_DEVDISR_TB0 0x00004000 |
| 54 | − __be32 devdisr2; /* 0x.0074 - Device Disable Control 2 */ | |
| 66 | + u32 devdisr2; /* 0x.0074 - Device Disable Control 2 */ | |
| 55 | 67 | u8 res078[0x7c - 0x78]; |
| 56 | − __be32 pmjcr; /* 0x.007c - 4 Power Management Jog Control Register */ | |
| 57 | − __be32 powmgtcsr; /* 0x.0080 - Power Management Status and Control Register */ | |
| 58 | − __be32 pmrccr; /* 0x.0084 - Power Management Reset Counter Configuration Register */ | |
| 59 | − __be32 pmpdccr; /* 0x.0088 - Power Management Power Down Counter Configuration Register */ | |
| 60 | − __be32 pmcdr; /* 0x.008c - 4Power management clock disable register */ | |
| 61 | − __be32 mcpsumr; /* 0x.0090 - Machine Check Summary Register */ | |
| 62 | − __be32 rstrscr; /* 0x.0094 - Reset Request Status and Control Register */ | |
| 63 | − __be32 ectrstcr; /* 0x.0098 - Exception reset control register */ | |
| 64 | − __be32 autorstsr; /* 0x.009c - Automatic reset status register */ | |
| 65 | − __be32 pvr; /* 0x.00a0 - Processor Version Register */ | |
| 66 | − __be32 svr; /* 0x.00a4 - System Version Register */ | |
| 68 | + u32 pmjcr; /* 0x.007c - 4 Power Management Jog Control | |
| 69 | + * Register | |
| 70 | + */ | |
| 71 | + u32 powmgtcsr; /* 0x.0080 - Power Management Status and | |
| 72 | + * Control Register | |
| 73 | + */ | |
| 74 | + u32 pmrccr; /* 0x.0084 - Power Management Reset Counter | |
| 75 | + * Configuration Register | |
| 76 | + */ | |
| 77 | + u32 pmpdccr; /* 0x.0088 - Power Management Power Down Counter | |
| 78 | + * Configuration Register | |
| 79 | + */ | |
| 80 | + u32 pmcdr; /* 0x.008c - 4Power management clock disable | |
| 81 | + * register | |
| 82 | + */ | |
| 83 | + u32 mcpsumr; /* 0x.0090 - Machine Check Summary Register */ | |
| 84 | + u32 rstrscr; /* 0x.0094 - Reset Request Status and | |
| 85 | + * Control Register | |
| 86 | + */ | |
| 87 | + u32 ectrstcr; /* 0x.0098 - Exception reset control register */ | |
| 88 | + u32 autorstsr; /* 0x.009c - Automatic reset status register */ | |
| 89 | + u32 pvr; /* 0x.00a0 - Processor Version Register */ | |
| 90 | + u32 svr; /* 0x.00a4 - System Version Register */ | |
| 67 | 91 | u8 res0a8[0xb0 - 0xa8]; |
| 68 | − __be32 rstcr; /* 0x.00b0 - Reset Control Register */ | |
| 92 | + u32 rstcr; /* 0x.00b0 - Reset Control Register */ | |
| 69 | 93 | u8 res0b4[0xc0 - 0xb4]; |
| 70 | − __be32 iovselsr; /* 0x.00c0 - I/O voltage select status register | |
| 94 | + u32 iovselsr; /* 0x.00c0 - I/O voltage select status register | |
| 71 | 95 | Called 'elbcvselcr' on 86xx SOCs */ |
| 72 | 96 | u8 res0c4[0x100 - 0xc4]; |
| 73 | − __be32 rcwsr[16]; /* 0x.0100 - Reset Control Word Status registers | |
| 97 | + u32 rcwsr[16]; /* 0x.0100 - Reset Control Word Status registers | |
| 74 | 98 | There are 16 registers */ |
| 75 | 99 | u8 res140[0x224 - 0x140]; |
| 76 | − __be32 iodelay1; /* 0x.0224 - IO delay control register 1 */ | |
| 77 | − __be32 iodelay2; /* 0x.0228 - IO delay control register 2 */ | |
| 100 | + u32 iodelay1; /* 0x.0224 - IO delay control register 1 */ | |
| 101 | + u32 iodelay2; /* 0x.0228 - IO delay control register 2 */ | |
| 78 | 102 | u8 res22c[0x604 - 0x22c]; |
| 79 | − __be32 pamubypenr; /* 0x.604 - PAMU bypass enable register */ | |
| 103 | + u32 pamubypenr; /* 0x.604 - PAMU bypass enable register */ | |
| 80 | 104 | u8 res608[0x800 - 0x608]; |
| 81 | − __be32 clkdvdr; /* 0x.0800 - Clock Divide Register */ | |
| 105 | + u32 clkdvdr; /* 0x.0800 - Clock Divide Register */ | |
| 82 | 106 | u8 res804[0x900 - 0x804]; |
| 83 | − __be32 ircr; /* 0x.0900 - Infrared Control Register */ | |
| 107 | + u32 ircr; /* 0x.0900 - Infrared Control Register */ | |
| 84 | 108 | u8 res904[0x908 - 0x904]; |
| 85 | − __be32 dmacr; /* 0x.0908 - DMA Control Register */ | |
| 109 | + u32 dmacr; /* 0x.0908 - DMA Control Register */ | |
| 86 | 110 | u8 res90c[0x914 - 0x90c]; |
| 87 | − __be32 elbccr; /* 0x.0914 - eLBC Control Register */ | |
| 111 | + u32 elbccr; /* 0x.0914 - eLBC Control Register */ | |
| 88 | 112 | u8 res918[0xb20 - 0x918]; |
| 89 | − __be32 ddr1clkdr; /* 0x.0b20 - DDR1 Clock Disable Register */ | |
| 90 | − __be32 ddr2clkdr; /* 0x.0b24 - DDR2 Clock Disable Register */ | |
| 91 | − __be32 ddrclkdr; /* 0x.0b28 - DDR Clock Disable Register */ | |
| 113 | + u32 ddr1clkdr; /* 0x.0b20 - DDR1 Clock Disable Register */ | |
| 114 | + u32 ddr2clkdr; /* 0x.0b24 - DDR2 Clock Disable Register */ | |
| 115 | + u32 ddrclkdr; /* 0x.0b28 - DDR Clock Disable Register */ | |
| 92 | 116 | u8 resb2c[0xe00 - 0xb2c]; |
| 93 | − __be32 clkocr; /* 0x.0e00 - Clock Out Select Register */ | |
| 117 | + u32 clkocr; /* 0x.0e00 - Clock Out Select Register */ | |
| 94 | 118 | u8 rese04[0xe10 - 0xe04]; |
| 95 | − __be32 ddrdllcr; /* 0x.0e10 - DDR DLL Control Register */ | |
| 119 | + u32 ddrdllcr; /* 0x.0e10 - DDR DLL Control Register */ | |
| 96 | 120 | u8 rese14[0xe20 - 0xe14]; |
| 97 | − __be32 lbcdllcr; /* 0x.0e20 - LBC DLL Control Register */ | |
| 98 | − __be32 cpfor; /* 0x.0e24 - L2 charge pump fuse override register */ | |
| 121 | + u32 lbcdllcr; /* 0x.0e20 - LBC DLL Control Register */ | |
| 122 | + u32 cpfor; /* 0x.0e24 - L2 charge pump fuse override | |
| 123 | + * register | |
| 124 | + */ | |
| 99 | 125 | u8 rese28[0xf04 - 0xe28]; |
| 100 | − __be32 srds1cr0; /* 0x.0f04 - SerDes1 Control Register 0 */ | |
| 101 | − __be32 srds1cr1; /* 0x.0f08 - SerDes1 Control Register 0 */ | |
| 126 | + u32 srds1cr0; /* 0x.0f04 - SerDes1 Control Register 0 */ | |
| 127 | + u32 srds1cr1; /* 0x.0f08 - SerDes1 Control Register 0 */ | |
| 102 | 128 | u8 resf0c[0xf2c - 0xf0c]; |
| 103 | − __be32 itcr; /* 0x.0f2c - Internal transaction control register */ | |
| 129 | + u32 itcr; /* 0x.0f2c - Internal transaction control | |
| 130 | + * register | |
| 131 | + */ | |
| 104 | 132 | u8 resf30[0xf40 - 0xf30]; |
| 105 | − __be32 srds2cr0; /* 0x.0f40 - SerDes2 Control Register 0 */ | |
| 106 | − __be32 srds2cr1; /* 0x.0f44 - SerDes2 Control Register 0 */ | |
| 133 | + u32 srds2cr0; /* 0x.0f40 - SerDes2 Control Register 0 */ | |
| 134 | + u32 srds2cr1; /* 0x.0f44 - SerDes2 Control Register 0 */ | |
| 107 | 135 | } __attribute__ ((packed)); |
| 108 | 136 | |
| 137 | +u32 fsl_guts_get_svr(void); | |
| 109 | 138 | |
| 110 | 139 | /* Alternate function signal multiplex control */ |
| 111 | 140 | #define MPC85xx_PMUXCR_QE(x) (0x8000 >> (x)) |
| @@ -99,6 +99,11 @@ · 98 unmodified lines | ||
| 99 | 99 | */ |
| 100 | 100 | #define TMIO_MMC_SDIO_STATUS_QUIRK (1 << 8) |
| 101 | 101 | |
| 102 | +/* | |
| 103 | + * Some controllers have a 32-bit wide data port register | |
| 104 | + */ | |
| 105 | +#define TMIO_MMC_32BIT_DATA_PORT (1 << 9) | |
| 106 | + | |
| 102 | 107 | /* |
| 103 | 108 | * Some controllers allows to set SDx actual clock |
| 104 | 109 | */ |
| @@ -89,6 +89,8 @@ struct mmc_ext_csd { · 88 unmodified lines | ||
| 89 | 89 | unsigned int boot_ro_lock; /* ro lock support */ |
| 90 | 90 | bool boot_ro_lockable; |
| 91 | 91 | bool ffu_capable; /* Firmware upgrade support */ |
| 92 | + bool cmdq_support; /* Command Queue supported */ | |
| 93 | + unsigned int cmdq_depth; /* Command Queue depth */ | |
| 92 | 94 | #define MMC_FIRMWARE_LEN 8 |
| 93 | 95 | u8 fwrev[MMC_FIRMWARE_LEN]; /* FW version */ |
| 94 | 96 | u8 raw_exception_status; /* 54 */ |
| @@ -207,18 +209,6 @@ struct sdio_func_tuple; · 112 unmodified lines | ||
| 207 | 209 | |
| 208 | 210 | #define SDIO_MAX_FUNCS 7 |
| 209 | 211 | |
| 210 | −enum mmc_blk_status { | |
| 211 | − MMC_BLK_SUCCESS = 0, | |
| 212 | − MMC_BLK_PARTIAL, | |
| 213 | − MMC_BLK_CMD_ERR, | |
| 214 | − MMC_BLK_RETRY, | |
| 215 | − MMC_BLK_ABORT, | |
| 216 | − MMC_BLK_DATA_ERR, | |
| 217 | − MMC_BLK_ECC_ERR, | |
| 218 | − MMC_BLK_NOMEDIUM, | |
| 219 | − MMC_BLK_NEW_REQUEST, | |
| 220 | −}; | |
| 221 | − | |
| 222 | 212 | /* The number of MMC physical partitions. These consist of: |
| 223 | 213 | * boot partitions (2), general purpose partitions (4) and |
| 224 | 214 | * RPMB partition (1) in MMC v4.4. |
| @@ -15,6 +15,18 @@ struct request; · 14 unmodified lines | ||
| 15 | 15 | struct mmc_data; |
| 16 | 16 | struct mmc_request; |
| 17 | 17 | |
| 18 | +enum mmc_blk_status { | |
| 19 | + MMC_BLK_SUCCESS = 0, | |
| 20 | + MMC_BLK_PARTIAL, | |
| 21 | + MMC_BLK_CMD_ERR, | |
| 22 | + MMC_BLK_RETRY, | |
| 23 | + MMC_BLK_ABORT, | |
| 24 | + MMC_BLK_DATA_ERR, | |
| 25 | + MMC_BLK_ECC_ERR, | |
| 26 | + MMC_BLK_NOMEDIUM, | |
| 27 | + MMC_BLK_NEW_REQUEST, | |
| 28 | +}; | |
| 29 | + | |
| 18 | 30 | struct mmc_command { |
| 19 | 31 | u32 opcode; |
| 20 | 32 | u32 arg; |
| @@ -150,7 +162,8 @@ struct mmc_async_req; · 129 unmodified lines | ||
| 150 | 162 | extern int mmc_stop_bkops(struct mmc_card *); |
| 151 | 163 | extern int mmc_read_bkops_status(struct mmc_card *); |
| 152 | 164 | extern struct mmc_async_req *mmc_start_req(struct mmc_host *, |
| 153 | − struct mmc_async_req *, int *); | |
| 165 | + struct mmc_async_req *, | |
| 166 | + enum mmc_blk_status *); | |
| 154 | 167 | extern int mmc_interrupt_hpi(struct mmc_card *); |
| 155 | 168 | extern void mmc_wait_for_req(struct mmc_host *, struct mmc_request *); |
| 156 | 169 | extern void mmc_wait_for_req_done(struct mmc_host *host, |
| @@ -163,6 +176,7 @@ extern int mmc_wait_for_app_cmd(struct mmc_host *, struct mmc_card *, · 6 unmodified lines | ||
| 163 | 176 | extern void mmc_start_bkops(struct mmc_card *card, bool from_exception); |
| 164 | 177 | extern int mmc_switch(struct mmc_card *, u8, u8, u8, unsigned int); |
| 165 | 178 | extern int mmc_send_tuning(struct mmc_host *host, u32 opcode, int *cmd_error); |
| 179 | +extern int mmc_abort_tuning(struct mmc_host *host, u32 opcode); | |
| 166 | 180 | extern int mmc_get_ext_csd(struct mmc_card *card, u8 **new_ext_csd); |
| 167 | 181 | |
| 168 | 182 | #define MMC_ERASE_ARG 0x00000000 |
| @@ -39,6 +39,12 @@ enum { · 38 unmodified lines | ||
| 39 | 39 | EVENT_DATA_ERROR, |
| 40 | 40 | }; |
| 41 | 41 | |
| 42 | +enum dw_mci_cookie { | |
| 43 | + COOKIE_UNMAPPED, | |
| 44 | + COOKIE_PRE_MAPPED, /* mapped by pre_req() of dwmmc */ | |
| 45 | + COOKIE_MAPPED, /* mapped by prepare_data() of dwmmc */ | |
| 46 | +}; | |
| 47 | + | |
| 42 | 48 | struct mmc_data; |
| 43 | 49 | |
| 44 | 50 | enum { |
| @@ -93,8 +93,7 @@ struct mmc_host_ops { · 92 unmodified lines | ||
| 93 | 93 | */ |
| 94 | 94 | void (*post_req)(struct mmc_host *host, struct mmc_request *req, |
| 95 | 95 | int err); |
| 96 | − void (*pre_req)(struct mmc_host *host, struct mmc_request *req, | |
| 97 | − bool is_first_req); | |
| 96 | + void (*pre_req)(struct mmc_host *host, struct mmc_request *req); | |
| 98 | 97 | void (*request)(struct mmc_host *host, struct mmc_request *req); |
| 99 | 98 | |
| 100 | 99 | /* |
| @@ -173,7 +172,7 @@ struct mmc_async_req { · 72 unmodified lines | ||
| 173 | 172 | * Check error status of completed mmc request. |
| 174 | 173 | * Returns 0 if success otherwise non zero. |
| 175 | 174 | */ |
| 176 | − int (*err_check) (struct mmc_card *, struct mmc_async_req *); | |
| 175 | + enum mmc_blk_status (*err_check)(struct mmc_card *, struct mmc_async_req *); | |
| 177 | 176 | }; |
| 178 | 177 | |
| 179 | 178 | /** |
| @@ -198,14 +197,12 @@ struct mmc_slot { · 18 unmodified lines | ||
| 198 | 197 | * @is_new_req wake up reason was new request |
| 199 | 198 | * @is_waiting_last_req mmc context waiting for single running request |
| 200 | 199 | * @wait wait queue |
| 201 | − * @lock lock to protect data fields | |
| 202 | 200 | */ |
| 203 | 201 | struct mmc_context_info { |
| 204 | 202 | bool is_done_rcv; |
| 205 | 203 | bool is_new_req; |
| 206 | 204 | bool is_waiting_last_req; |
| 207 | 205 | wait_queue_head_t wait; |
| 208 | − spinlock_t lock; | |
| 209 | 206 | }; |
| 210 | 207 | |
| 211 | 208 | struct regulator; |
| @@ -495,11 +492,6 @@ static inline int mmc_host_uhs(struct mmc_host *host) · 283 unmodified lines | ||
| 495 | 492 | MMC_CAP_UHS_DDR50); |
| 496 | 493 | } |
| 497 | 494 | |
| 498 | −static inline int mmc_host_packed_wr(struct mmc_host *host) | |
| 499 | −{ | |
| 500 | − return host->caps2 & MMC_CAP2_PACKED_WR; | |
| 501 | −} | |
| 502 | − | |
| 503 | 495 | static inline int mmc_card_hs(struct mmc_card *card) |
| 504 | 496 | { |
| 505 | 497 | return card->host->ios.timing == MMC_TIMING_SD_HS || |
| @@ -546,6 +538,11 @@ static inline void mmc_retune_recheck(struct mmc_host *host) · 40 unmodified lines | ||
| 546 | 538 | host->retune_now = 1; |
| 547 | 539 | } |
| 548 | 540 | |
| 541 | +static inline bool mmc_can_retune(struct mmc_host *host) | |
| 542 | +{ | |
| 543 | + return host->can_retune == 1; | |
| 544 | +} | |
| 545 | + | |
| 549 | 546 | void mmc_retune_pause(struct mmc_host *host); |
| 550 | 547 | void mmc_retune_unpause(struct mmc_host *host); |
| 551 | 548 | |
| @@ -84,6 +84,13 @@ · 83 unmodified lines | ||
| 84 | 84 | #define MMC_APP_CMD 55 /* ac [31:16] RCA R1 */ |
| 85 | 85 | #define MMC_GEN_CMD 56 /* adtc [0] RD/WR R1 */ |
| 86 | 86 | |
| 87 | + /* class 11 */ | |
| 88 | +#define MMC_QUE_TASK_PARAMS 44 /* ac [20:16] task id R1 */ | |
| 89 | +#define MMC_QUE_TASK_ADDR 45 /* ac [31:0] data addr R1 */ | |
| 90 | +#define MMC_EXECUTE_READ_TASK 46 /* adtc [20:16] task id R1 */ | |
| 91 | +#define MMC_EXECUTE_WRITE_TASK 47 /* adtc [20:16] task id R1 */ | |
| 92 | +#define MMC_CMDQ_TASK_MGMT 48 /* ac [20:16] task id R1b */ | |
| 93 | + | |
| 87 | 94 | static inline bool mmc_op_multi(u32 opcode) |
| 88 | 95 | { |
| 89 | 96 | return opcode == MMC_WRITE_MULTIPLE_BLOCK || |
| @@ -272,6 +279,7 @@ struct _mmc_csd { · 182 unmodified lines | ||
| 272 | 279 | * EXT_CSD fields |
| 273 | 280 | */ |
| 274 | 281 | |
| 282 | +#define EXT_CSD_CMDQ_MODE_EN 15 /* R/W */ | |
| 275 | 283 | #define EXT_CSD_FLUSH_CACHE 32 /* W */ |
| 276 | 284 | #define EXT_CSD_CACHE_CTRL 33 /* R/W */ |
| 277 | 285 | #define EXT_CSD_POWER_OFF_NOTIFICATION 34 /* R/W */ |
| @@ -331,6 +339,8 @@ struct _mmc_csd { · 53 unmodified lines | ||
| 331 | 339 | #define EXT_CSD_CACHE_SIZE 249 /* RO, 4 bytes */ |
| 332 | 340 | #define EXT_CSD_PWR_CL_DDR_200_360 253 /* RO */ |
| 333 | 341 | #define EXT_CSD_FIRMWARE_VERSION 254 /* RO, 8 bytes */ |
| 342 | +#define EXT_CSD_CMDQ_DEPTH 307 /* RO */ | |
| 343 | +#define EXT_CSD_CMDQ_SUPPORT 308 /* RO */ | |
| 334 | 344 | #define EXT_CSD_SUPPORTED_MODE 493 /* RO */ |
| 335 | 345 | #define EXT_CSD_TAG_UNIT_SIZE 498 /* RO */ |
| 336 | 346 | #define EXT_CSD_DATA_TAG_SUPPORT 499 /* RO */ |
| @@ -437,6 +447,13 @@ struct _mmc_csd { · 100 unmodified lines | ||
| 437 | 447 | */ |
| 438 | 448 | #define EXT_CSD_MANUAL_BKOPS_MASK 0x01 |
| 439 | 449 | |
| 450 | +/* | |
| 451 | + * Command Queue | |
| 452 | + */ | |
| 453 | +#define EXT_CSD_CMDQ_MODE_ENABLED BIT(0) | |
| 454 | +#define EXT_CSD_CMDQ_DEPTH_MASK GENMASK(4, 0) | |
| 455 | +#define EXT_CSD_CMDQ_SUPPORTED BIT(0) | |
| 456 | + | |
| 440 | 457 | /* |
| 441 | 458 | * MMC_SWITCH access modes |
| 442 | 459 | */ |
| @@ -29,5 +29,6 @@ int mmc_gpiod_request_ro(struct mmc_host *host, const char *con_id, · 28 unmodified lines | ||
| 29 | 29 | void mmc_gpio_set_cd_isr(struct mmc_host *host, |
| 30 | 30 | irqreturn_t (*isr)(int irq, void *dev_id)); |
| 31 | 31 | void mmc_gpiod_request_cd_irq(struct mmc_host *host); |
| 32 | +bool mmc_can_gpio_cd(struct mmc_host *host); | |
| 32 | 33 | |
| 33 | 34 | #endif |
| @@ -13,6 +13,7 @@ struct soc_device_attribute { · 12 unmodified lines | ||
| 13 | 13 | const char *family; |
| 14 | 14 | const char *revision; |
| 15 | 15 | const char *soc_id; |
| 16 | + const void *data; | |
| 16 | 17 | }; |
| 17 | 18 | |
| 18 | 19 | /** |
| @@ -34,4 +35,12 @@ void soc_device_unregister(struct soc_device *soc_dev); · 15 unmodified lines | ||
| 34 | 35 | */ |
| 35 | 36 | struct device *soc_device_to_device(struct soc_device *soc); |
| 36 | 37 | |
| 38 | +#ifdef CONFIG_SOC_BUS | |
| 39 | +const struct soc_device_attribute *soc_device_match( | |
| 40 | + const struct soc_device_attribute *matches); | |
| 41 | +#else | |
| 42 | +static inline const struct soc_device_attribute *soc_device_match( | |
| 43 | + const struct soc_device_attribute *matches) { return NULL; } | |
| 44 | +#endif | |
| 45 | + | |
| 37 | 46 | #endif /* __SOC_BUS_H */ |
| @@ -69,6 +69,6 @@ struct mmc_ioc_multi_cmd { · 68 unmodified lines | ||
| 69 | 69 | * is enforced per ioctl call. For larger data transfers, use the normal |
| 70 | 70 | * block device operations. |
| 71 | 71 | */ |
| 72 | −#define MMC_IOC_MAX_BYTES (512L * 256) | |
| 72 | +#define MMC_IOC_MAX_BYTES (512L * 1024) | |
| 73 | 73 | #define MMC_IOC_MAX_CMDS 255 |
| 74 | 74 | #endif /* LINUX_MMC_IOCTL_H */ |