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Merge mlx5-next into rdma for-next

From git://git.kernel.org/pub/scm/linux/kernel/git/mellanox/linux Required for dependencies in the next patches. * mlx5-next: net/mlx5: Add rts2rts_qp_counters_set_id field in hca cap net/mlx5: Properly name the generic WQE control field net/mlx5: Introduce TLS TX offload hardware bits and structures net/mlx5: Refactor mlx5_esw_query_functions for modularity net/mlx5: E-Switch prepare functions change handler to be modular net/mlx5: Introduce and use mlx5_eswitch_get_total_vports()

Jason Gunthorpe committed 7 years ago

Commit 5600a412 parents bcde9a8 f8efee013 files · +235 −62Browse files

Showing the changes to include/linux (6 of 13 files). Show all

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6 files
  1. include/linux/mlx5/device.h +14 −0
  2. include/linux/mlx5/driver.h +5 −4
  3. include/linux/mlx5/eswitch.h +3 −0
  4. include/linux/mlx5/mlx5_ifc.h +103 −5
  5. include/linux/mlx5/qp.h +6 −1
  6. include/linux/mlx5/vport.h +0 −3
include/linux/mlx5/device.h+14−0
@@ -437,6 +437,7 @@ enum { · 436 unmodified lines
437437 MLX5_OPCODE_SET_PSV = 0x20,
438438 MLX5_OPCODE_GET_PSV = 0x21,
439439 MLX5_OPCODE_CHECK_PSV = 0x22,
440+ MLX5_OPCODE_DUMP = 0x23,
440441 MLX5_OPCODE_RGET_PSV = 0x26,
441442 MLX5_OPCODE_RCHECK_PSV = 0x27,
442443
@@ -444,6 +445,14 @@ enum { · 1 unmodified line
444445
445446 };
446447
448+enum {
449+ MLX5_OPC_MOD_TLS_TIS_STATIC_PARAMS = 0x20,
450+};
451+
452+enum {
453+ MLX5_OPC_MOD_TLS_TIS_PROGRESS_PARAMS = 0x20,
454+};
455+
447456 enum {
448457 MLX5_SET_PORT_RESET_QKEY = 0,
449458 MLX5_SET_PORT_GUID0 = 16,
@@ -1077,6 +1086,8 @@ enum mlx5_cap_type { · 627 unmodified lines
10771086 MLX5_CAP_DEBUG,
10781087 MLX5_CAP_RESERVED_14,
10791088 MLX5_CAP_DEV_MEM,
1089+ MLX5_CAP_RESERVED_16,
1090+ MLX5_CAP_TLS,
10801091 MLX5_CAP_DEV_EVENT = 0x14,
10811092 /* NUM OF CAP Types */
10821093 MLX5_CAP_NUM
@@ -1256,6 +1267,9 @@ enum mlx5_qcam_feature_groups { · 173 unmodified lines
12561267 #define MLX5_CAP64_DEV_MEM(mdev, cap)\
12571268 MLX5_GET64(device_mem_cap, mdev->caps.hca_cur[MLX5_CAP_DEV_MEM], cap)
12581269
1270+#define MLX5_CAP_TLS(mdev, cap) \
1271+ MLX5_GET(tls_cap, (mdev)->caps.hca_cur[MLX5_CAP_TLS], cap)
1272+
12591273 #define MLX5_CAP_DEV_EVENT(mdev, cap)\
12601274 MLX5_ADDR_OF(device_event_cap, (mdev)->caps.hca_cur[MLX5_CAP_DEV_EVENT], cap)
12611275
include/linux/mlx5/driver.h+5−4
@@ -1085,7 +1085,7 @@ enum { · 1084 unmodified lines
10851085 MLX5_PCI_DEV_IS_VF = 1 << 0,
10861086 };
10871087
1088−static inline bool mlx5_core_is_pf(struct mlx5_core_dev *dev)
1088+static inline bool mlx5_core_is_pf(const struct mlx5_core_dev *dev)
10891089 {
10901090 return dev->coredev_type == MLX5_COREDEV_PF;
10911091 }
@@ -1095,17 +1095,18 @@ static inline bool mlx5_core_is_ecpf(struct mlx5_core_dev *dev) · 3 unmodified lines
10951095 return dev->caps.embedded_cpu;
10961096 }
10971097
1098−static inline bool mlx5_core_is_ecpf_esw_manager(struct mlx5_core_dev *dev)
1098+static inline bool
1099+mlx5_core_is_ecpf_esw_manager(const struct mlx5_core_dev *dev)
10991100 {
11001101 return dev->caps.embedded_cpu && MLX5_CAP_GEN(dev, eswitch_manager);
11011102 }
11021103
1103−static inline bool mlx5_ecpf_vport_exists(struct mlx5_core_dev *dev)
1104+static inline bool mlx5_ecpf_vport_exists(const struct mlx5_core_dev *dev)
11041105 {
11051106 return mlx5_core_is_pf(dev) && MLX5_CAP_ESW(dev, ecpf_vport_exists);
11061107 }
11071108
1108−static inline u16 mlx5_core_max_vfs(struct mlx5_core_dev *dev)
1109+static inline u16 mlx5_core_max_vfs(const struct mlx5_core_dev *dev)
11091110 {
11101111 return dev->priv.sriov.max_vfs;
11111112 }
include/linux/mlx5/eswitch.h+3−0
@@ -66,6 +66,8 @@ struct mlx5_flow_handle * · 65 unmodified lines
6666 mlx5_eswitch_add_send_to_vport_rule(struct mlx5_eswitch *esw,
6767 u16 vport_num, u32 sqn);
6868
69+u16 mlx5_eswitch_get_total_vports(const struct mlx5_core_dev *dev);
70+
6971 #ifdef CONFIG_MLX5_ESWITCH
7072 enum devlink_eswitch_encap_mode
7173 mlx5_eswitch_get_encap_mode(const struct mlx5_core_dev *dev);
@@ -93,4 +95,5 @@ mlx5_eswitch_get_vport_metadata_for_match(const struct mlx5_eswitch *esw, · 21 unmodified lines
9395 return 0;
9496 };
9597 #endif /* CONFIG_MLX5_ESWITCH */
98+
9699 #endif
include/linux/mlx5/mlx5_ifc.h+103−5
@@ -973,6 +973,16 @@ struct mlx5_ifc_vector_calc_cap_bits { · 972 unmodified lines
973973 u8 reserved_at_c0[0x720];
974974 };
975975
976+struct mlx5_ifc_tls_cap_bits {
977+ u8 tls_1_2_aes_gcm_128[0x1];
978+ u8 tls_1_3_aes_gcm_128[0x1];
979+ u8 tls_1_2_aes_gcm_256[0x1];
980+ u8 tls_1_3_aes_gcm_256[0x1];
981+ u8 reserved_at_4[0x1c];
982+
983+ u8 reserved_at_20[0x7e0];
984+};
985+
976986 enum {
977987 MLX5_WQ_TYPE_LINKED_LIST = 0x0,
978988 MLX5_WQ_TYPE_CYCLIC = 0x1,
@@ -1086,7 +1096,9 @@ struct mlx5_ifc_cmd_hca_cap_bits { · 107 unmodified lines
10861096 u8 cc_modify_allowed[0x1];
10871097 u8 start_pad[0x1];
10881098 u8 cache_line_128byte[0x1];
1089− u8 reserved_at_165[0xa];
1099+ u8 reserved_at_165[0x4];
1100+ u8 rts2rts_qp_counters_set_id[0x1];
1101+ u8 reserved_at_16a[0x5];
10901102 u8 qcam_reg[0x1];
10911103 u8 gid_table_size[0x10];
10921104
@@ -1303,7 +1315,8 @@ struct mlx5_ifc_cmd_hca_cap_bits { · 210 unmodified lines
13031315
13041316 u8 reserved_at_440[0x20];
13051317
1306− u8 reserved_at_460[0x3];
1318+ u8 tls[0x1];
1319+ u8 reserved_at_461[0x2];
13071320 u8 log_max_uctx[0x5];
13081321 u8 reserved_at_468[0x3];
13091322 u8 log_max_umem[0x5];
@@ -1328,7 +1341,9 @@ struct mlx5_ifc_cmd_hca_cap_bits { · 18 unmodified lines
13281341 u8 max_geneve_tlv_option_data_len[0x5];
13291342 u8 reserved_at_570[0x10];
13301343
1331− u8 reserved_at_580[0x3c];
1344+ u8 reserved_at_580[0x33];
1345+ u8 log_max_dek[0x5];
1346+ u8 reserved_at_5b8[0x4];
13321347 u8 mini_cqe_resp_stride_index[0x1];
13331348 u8 cqe_128_always[0x1];
13341349 u8 cqe_compression_128[0x1];
@@ -2607,6 +2622,7 @@ union mlx5_ifc_hca_cap_union_bits { · 1272 unmodified lines
26072622 struct mlx5_ifc_qos_cap_bits qos_cap;
26082623 struct mlx5_ifc_debug_cap_bits debug_cap;
26092624 struct mlx5_ifc_fpga_cap_bits fpga_cap;
2625+ struct mlx5_ifc_tls_cap_bits tls_cap;
26102626 u8 reserved_at_0[0x8000];
26112627 };
26122628
@@ -2746,7 +2762,8 @@ struct mlx5_ifc_traffic_counter_bits { · 133 unmodified lines
27462762
27472763 struct mlx5_ifc_tisc_bits {
27482764 u8 strict_lag_tx_port_affinity[0x1];
2749− u8 reserved_at_1[0x3];
2765+ u8 tls_en[0x1];
2766+ u8 reserved_at_1[0x2];
27502767 u8 lag_tx_port_affinity[0x04];
27512768
27522769 u8 reserved_at_8[0x4];
@@ -2760,7 +2777,11 @@ struct mlx5_ifc_tisc_bits { · 7 unmodified lines
27602777
27612778 u8 reserved_at_140[0x8];
27622779 u8 underlay_qpn[0x18];
2763− u8 reserved_at_160[0x3a0];
2780+
2781+ u8 reserved_at_160[0x8];
2782+ u8 pd[0x18];
2783+
2784+ u8 reserved_at_180[0x380];
27642785 };
27652786
27662787 enum {
@@ -9965,4 +9986,81 @@ struct mlx5_ifc_affiliated_event_header_bits { · 7198 unmodified lines
99659986 u8 obj_id[0x20];
99669987 };
99679988
9989+enum {
9990+ MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_ENCRYPTION_KEY = BIT(0xc),
9991+};
9992+
9993+enum {
9994+ MLX5_GENERAL_OBJECT_TYPES_ENCRYPTION_KEY = 0xc,
9995+};
9996+
9997+struct mlx5_ifc_encryption_key_obj_bits {
9998+ u8 modify_field_select[0x40];
9999+
10000+ u8 reserved_at_40[0x14];
10001+ u8 key_size[0x4];
10002+ u8 reserved_at_58[0x4];
10003+ u8 key_type[0x4];
10004+
10005+ u8 reserved_at_60[0x8];
10006+ u8 pd[0x18];
10007+
10008+ u8 reserved_at_80[0x180];
10009+ u8 key[8][0x20];
10010+
10011+ u8 reserved_at_300[0x500];
10012+};
10013+
10014+struct mlx5_ifc_create_encryption_key_in_bits {
10015+ struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr;
10016+ struct mlx5_ifc_encryption_key_obj_bits encryption_key_object;
10017+};
10018+
10019+enum {
10020+ MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_KEY_SIZE_128 = 0x0,
10021+ MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_KEY_SIZE_256 = 0x1,
10022+};
10023+
10024+enum {
10025+ MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_TYPE_DEK = 0x1,
10026+};
10027+
10028+struct mlx5_ifc_tls_static_params_bits {
10029+ u8 const_2[0x2];
10030+ u8 tls_version[0x4];
10031+ u8 const_1[0x2];
10032+ u8 reserved_at_8[0x14];
10033+ u8 encryption_standard[0x4];
10034+
10035+ u8 reserved_at_20[0x20];
10036+
10037+ u8 initial_record_number[0x40];
10038+
10039+ u8 resync_tcp_sn[0x20];
10040+
10041+ u8 gcm_iv[0x20];
10042+
10043+ u8 implicit_iv[0x40];
10044+
10045+ u8 reserved_at_100[0x8];
10046+ u8 dek_index[0x18];
10047+
10048+ u8 reserved_at_120[0xe0];
10049+};
10050+
10051+struct mlx5_ifc_tls_progress_params_bits {
10052+ u8 valid[0x1];
10053+ u8 reserved_at_1[0x7];
10054+ u8 pd[0x18];
10055+
10056+ u8 next_record_tcp_sn[0x20];
10057+
10058+ u8 hw_resync_tcp_sn[0x20];
10059+
10060+ u8 record_tracker_state[0x2];
10061+ u8 auth_state[0x2];
10062+ u8 reserved_at_64[0x4];
10063+ u8 hw_offset_record_number[0x18];
10064+};
10065+
996810066 #endif /* MLX5_IFC_H */
include/linux/mlx5/qp.h+6−1
@@ -203,7 +203,12 @@ struct mlx5_wqe_ctrl_seg { · 202 unmodified lines
203203 u8 signature;
204204 u8 rsvd[2];
205205 u8 fm_ce_se;
206− __be32 imm;
206+ union {
207+ __be32 general_id;
208+ __be32 imm;
209+ __be32 umr_mkey;
210+ __be32 tisn;
211+ };
207212 };
208213
209214 #define MLX5_WQE_CTRL_DS_MASK 0x3f
include/linux/mlx5/vport.h+0−3
@@ -44,9 +44,6 @@ · 43 unmodified lines
4444 MLX5_VPORT_UPLINK_PLACEHOLDER + \
4545 MLX5_VPORT_ECPF_PLACEHOLDER(mdev))
4646
47−#define MLX5_TOTAL_VPORTS(mdev) (MLX5_SPECIAL_VPORTS(mdev) + \
48− mlx5_core_max_vfs(mdev))
49−
5047 #define MLX5_VPORT_MANAGER(mdev) \
5148 (MLX5_CAP_GEN(mdev, vport_group_manager) && \
5249 (MLX5_CAP_GEN(mdev, port_type) == MLX5_CAP_PORT_TYPE_ETH) && \

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