History

net: hns3: fix mis-counting IRQ vector numbers issue

Currently, the num_msi_left means the vector numbers of NIC, but if the PF supported RoCE, it contains the vector numbers of NIC and RoCE(Not expected). This may cause interrupts lost in some case, because of the NIC module used the vector resources which belongs to RoCE. This patch adds a new variable num_nic_msi to store the vector numbers of NIC, and adjust the default TQP numbers and rss_size according to the value of num_nic_msi.

Yonglong Liu committed 7 years ago

Commit 580a05f1 parent 38b4fe36 files · +58 −6Browse files

Unified · Split

6 files
  1. drivers/net/ethernet/hisilicon/hns3/hnae3.h +2 −0
  2. drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c +20 −1
  3. drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h +1 −0
  4. drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_tm.c +9 −2
  5. drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_main.c +25 −3
  6. drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_main.h +1 −0
drivers/net/ethernet/hisilicon/hns3/hnae3.h+2−0
@@ -32,6 +32,8 @@ · 31 unmodified lines
3232
3333 #define HNAE3_MOD_VERSION "1.0"
3434
35+#define HNAE3_MIN_VECTOR_NUM 2 /* first one for misc, another for IO */
36+
3537 /* Device IDs */
3638 #define HNAE3_DEV_ID_GE 0xA220
3739 #define HNAE3_DEV_ID_25GE 0xA221
drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c+20−1
@@ -906,6 +906,9 @@ static int hclge_query_pf_resource(struct hclge_dev *hdev) · 905 unmodified lines
906906 hnae3_get_field(__le16_to_cpu(req->pf_intr_vector_number),
907907 HCLGE_PF_VEC_NUM_M, HCLGE_PF_VEC_NUM_S);
908908
909+ /* nic's msix numbers is always equals to the roce's. */
910+ hdev->num_nic_msi = hdev->num_roce_msi;
911+
909912 /* PF should have NIC vectors and Roce vectors,
910913 * NIC vectors are queued before Roce vectors.
911914 */
@@ -915,6 +918,15 @@ static int hclge_query_pf_resource(struct hclge_dev *hdev) · 3 unmodified lines
915918 hdev->num_msi =
916919 hnae3_get_field(__le16_to_cpu(req->pf_intr_vector_number),
917920 HCLGE_PF_VEC_NUM_M, HCLGE_PF_VEC_NUM_S);
921+
922+ hdev->num_nic_msi = hdev->num_msi;
923+ }
924+
925+ if (hdev->num_nic_msi < HNAE3_MIN_VECTOR_NUM) {
926+ dev_err(&hdev->pdev->dev,
927+ "Just %u msi resources, not enough for pf(min:2).\n",
928+ hdev->num_nic_msi);
929+ return -EINVAL;
918930 }
919931
920932 return 0;
@@ -1507,6 +1519,10 @@ static int hclge_assign_tqp(struct hclge_vport *vport, u16 num_tqps) · 586 unmodified lines
15071519 kinfo->rss_size = min_t(u16, hdev->rss_size_max,
15081520 vport->alloc_tqps / hdev->tm_info.num_tc);
15091521
1522+ /* ensure one to one mapping between irq and queue at default */
1523+ kinfo->rss_size = min_t(u16, kinfo->rss_size,
1524+ (hdev->num_nic_msi - 1) / hdev->tm_info.num_tc);
1525+
15101526 return 0;
15111527 }
15121528
@@ -2285,7 +2301,8 @@ static int hclge_init_msi(struct hclge_dev *hdev) · 772 unmodified lines
22852301 int vectors;
22862302 int i;
22872303
2288− vectors = pci_alloc_irq_vectors(pdev, 1, hdev->num_msi,
2304+ vectors = pci_alloc_irq_vectors(pdev, HNAE3_MIN_VECTOR_NUM,
2305+ hdev->num_msi,
22892306 PCI_IRQ_MSI | PCI_IRQ_MSIX);
22902307 if (vectors < 0) {
22912308 dev_err(&pdev->dev,
@@ -2300,6 +2317,7 @@ static int hclge_init_msi(struct hclge_dev *hdev) · 8 unmodified lines
23002317
23012318 hdev->num_msi = vectors;
23022319 hdev->num_msi_left = vectors;
2320+
23032321 hdev->base_msi_vector = pdev->irq;
23042322 hdev->roce_base_vector = hdev->base_msi_vector +
23052323 hdev->roce_base_msix_offset;
@@ -3903,6 +3921,7 @@ static int hclge_get_vector(struct hnae3_handle *handle, u16 vector_num, · 1597 unmodified lines
39033921 int alloc = 0;
39043922 int i, j;
39053923
3924+ vector_num = min_t(u16, hdev->num_nic_msi - 1, vector_num);
39063925 vector_num = min(hdev->num_msi_left, vector_num);
39073926
39083927 for (j = 0; j < vector_num; j++) {
drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h+1−0
@@ -763,6 +763,7 @@ struct hclge_dev { · 762 unmodified lines
763763 u32 base_msi_vector;
764764 u16 *vector_status;
765765 int *vector_irq;
766+ u16 num_nic_msi; /* Num of nic vectors for this PF */
766767 u16 num_roce_msi; /* Num of roce vectors for this PF */
767768 int roce_base_vector;
768769
drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_tm.c+9−2
@@ -537,9 +537,16 @@ static void hclge_tm_vport_tc_info_update(struct hclge_vport *vport) · 536 unmodified lines
537537 kinfo->rss_size = kinfo->req_rss_size;
538538 } else if (kinfo->rss_size > max_rss_size ||
539539 (!kinfo->req_rss_size && kinfo->rss_size < max_rss_size)) {
540+ /* if user not set rss, the rss_size should compare with the
541+ * valid msi numbers to ensure one to one map between tqp and
542+ * irq as default.
543+ */
544+ if (!kinfo->req_rss_size)
545+ max_rss_size = min_t(u16, max_rss_size,
546+ (hdev->num_nic_msi - 1) /
547+ kinfo->num_tc);
548+
540549 /* Set to the maximum specification value (max_rss_size). */
541− dev_info(&hdev->pdev->dev, "rss changes from %d to %d\n",
542− kinfo->rss_size, max_rss_size);
543550 kinfo->rss_size = max_rss_size;
544551 }
545552
drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_main.c+25−3
@@ -411,6 +411,13 @@ static int hclgevf_knic_setup(struct hclgevf_dev *hdev) · 410 unmodified lines
411411 kinfo->tqp[i] = &hdev->htqp[i].q;
412412 }
413413
414+ /* after init the max rss_size and tqps, adjust the default tqp numbers
415+ * and rss size with the actual vector numbers
416+ */
417+ kinfo->num_tqps = min_t(u16, hdev->num_nic_msix - 1, kinfo->num_tqps);
418+ kinfo->rss_size = min_t(u16, kinfo->num_tqps / kinfo->num_tc,
419+ kinfo->rss_size);
420+
414421 return 0;
415422 }
416423
@@ -502,6 +509,7 @@ static int hclgevf_get_vector(struct hnae3_handle *handle, u16 vector_num, · 85 unmodified lines
502509 int alloc = 0;
503510 int i, j;
504511
512+ vector_num = min_t(u16, hdev->num_nic_msix - 1, vector_num);
505513 vector_num = min(hdev->num_msi_left, vector_num);
506514
507515 for (j = 0; j < vector_num; j++) {
@@ -2246,13 +2254,14 @@ static int hclgevf_init_msi(struct hclgevf_dev *hdev) · 1738 unmodified lines
22462254 int vectors;
22472255 int i;
22482256
2249− if (hnae3_get_bit(hdev->ae_dev->flag, HNAE3_DEV_SUPPORT_ROCE_B))
2257+ if (hnae3_dev_roce_supported(hdev))
22502258 vectors = pci_alloc_irq_vectors(pdev,
22512259 hdev->roce_base_msix_offset + 1,
22522260 hdev->num_msi,
22532261 PCI_IRQ_MSIX);
22542262 else
2255− vectors = pci_alloc_irq_vectors(pdev, 1, hdev->num_msi,
2263+ vectors = pci_alloc_irq_vectors(pdev, HNAE3_MIN_VECTOR_NUM,
2264+ hdev->num_msi,
22562265 PCI_IRQ_MSI | PCI_IRQ_MSIX);
22572266
22582267 if (vectors < 0) {
@@ -2268,6 +2277,7 @@ static int hclgevf_init_msi(struct hclgevf_dev *hdev) · 9 unmodified lines
22682277
22692278 hdev->num_msi = vectors;
22702279 hdev->num_msi_left = vectors;
2280+
22712281 hdev->base_msi_vector = pdev->irq;
22722282 hdev->roce_base_vector = pdev->irq + hdev->roce_base_msix_offset;
22732283
@@ -2533,7 +2543,7 @@ static int hclgevf_query_vf_resource(struct hclgevf_dev *hdev) · 259 unmodified lines
25332543
25342544 req = (struct hclgevf_query_res_cmd *)desc.data;
25352545
2536− if (hnae3_get_bit(hdev->ae_dev->flag, HNAE3_DEV_SUPPORT_ROCE_B)) {
2546+ if (hnae3_dev_roce_supported(hdev)) {
25372547 hdev->roce_base_msix_offset =
25382548 hnae3_get_field(__le16_to_cpu(req->msixcap_localid_ba_rocee),
25392549 HCLGEVF_MSIX_OFT_ROCEE_M,
@@ -2542,6 +2552,9 @@ static int hclgevf_query_vf_resource(struct hclgevf_dev *hdev) · 2 unmodified lines
25422552 hnae3_get_field(__le16_to_cpu(req->vf_intr_vector_number),
25432553 HCLGEVF_VEC_NUM_M, HCLGEVF_VEC_NUM_S);
25442554
2555+ /* nic's msix numbers is always equals to the roce's. */
2556+ hdev->num_nic_msix = hdev->num_roce_msix;
2557+
25452558 /* VF should have NIC vectors and Roce vectors, NIC vectors
25462559 * are queued before Roce vectors. The offset is fixed to 64.
25472560 */
@@ -2551,6 +2564,15 @@ static int hclgevf_query_vf_resource(struct hclgevf_dev *hdev) · 3 unmodified lines
25512564 hdev->num_msi =
25522565 hnae3_get_field(__le16_to_cpu(req->vf_intr_vector_number),
25532566 HCLGEVF_VEC_NUM_M, HCLGEVF_VEC_NUM_S);
2567+
2568+ hdev->num_nic_msix = hdev->num_msi;
2569+ }
2570+
2571+ if (hdev->num_nic_msix < HNAE3_MIN_VECTOR_NUM) {
2572+ dev_err(&hdev->pdev->dev,
2573+ "Just %u msi resources, not enough for vf(min:2).\n",
2574+ hdev->num_nic_msix);
2575+ return -EINVAL;
25542576 }
25552577
25562578 return 0;
drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_main.h+1−0
@@ -270,6 +270,7 @@ struct hclgevf_dev { · 269 unmodified lines
270270 u16 num_msi;
271271 u16 num_msi_left;
272272 u16 num_msi_used;
273+ u16 num_nic_msix; /* Num of nic vectors for this VF */
273274 u16 num_roce_msix; /* Num of roce vectors for this VF */
274275 u16 roce_base_msix_offset;
275276 int roce_base_vector;