History

Merge branch 'qca8k-QCA8334-switch-support'

Michal Vokáč says: ==================== Add support for QCA8334 switch This series basically adds support for a QCA8334 ethernet switch to the qca8k driver. It is a four-port variant of the already supported seven port QCA8337. Register map is the same for the whole familly and all chips have the same device ID. Major part of this series enhances the CPU port setting. Currently the CPU port is not set to any sensible defaults compatible with the xGMII interface. This series forces the CPU port to its maximum bandwidth and also allows to adjust the new defaults using fixed-link device tree sub-node. Alongside these changes I fixed two checkpatch warnings regarding SPDX and redundant parentheses. Changes in v3: - Rebased on latest net-next/master. - Corrected fixed-link documentation. ====================

David S. Miller committed 8 years ago

Commit 5a867ab2 parents 038ed45 38222b13 files · +79 −15Browse files

Unified · Split

3 files
  1. Documentation/devicetree/bindings/net/dsa/qca8k.txt +22 −1
  2. drivers/net/dsa/qca8k.c +52 −12
  3. drivers/net/dsa/qca8k.h +5 −2
Documentation/devicetree/bindings/net/dsa/qca8k.txt+22−1
@@ -2,7 +2,10 @@ · 1 unmodified line
22
33 Required properties:
44
5−- compatible: should be "qca,qca8337"
5+- compatible: should be one of:
6+ "qca,qca8334"
7+ "qca,qca8337"
8+
69 - #size-cells: must be 0
710 - #address-cells: must be 1
811
@@ -14,6 +17,20 @@ port and PHY id, each subnode describing a port needs to have a valid phandle · 5 unmodified lines
1417 referencing the internal PHY connected to it. The CPU port of this switch is
1518 always port 0.
1619
20+A CPU port node has the following optional node:
21+
22+- fixed-link : Fixed-link subnode describing a link to a non-MDIO
23+ managed entity. See
24+ Documentation/devicetree/bindings/net/fixed-link.txt
25+ for details.
26+
27+For QCA8K the 'fixed-link' sub-node supports only the following properties:
28+
29+- 'speed' (integer, mandatory), to indicate the link speed. Accepted
30+ values are 10, 100 and 1000
31+- 'full-duplex' (boolean, optional), to indicate that full duplex is
32+ used. When absent, half duplex is assumed.
33+
1734 Example:
1835
1936
@@ -53,6 +70,10 @@ Example: · 33 unmodified lines
5370 label = "cpu";
5471 ethernet = <&gmac1>;
5572 phy-mode = "rgmii";
73+ fixed-link {
74+ speed = 1000;
75+ full-duplex;
76+ };
5677 };
5778
5879 port@1 {
drivers/net/dsa/qca8k.c+52−12
@@ -1,17 +1,9 @@
1+// SPDX-License-Identifier: GPL-2.0
12 /*
23 * Copyright (C) 2009 Felix Fietkau <nbd@nbd.name>
34 * Copyright (C) 2011-2012 Gabor Juhos <juhosg@openwrt.org>
45 * Copyright (c) 2015, The Linux Foundation. All rights reserved.
56 * Copyright (c) 2016 John Crispin <john@phrozen.org>
6− *
7− * This program is free software; you can redistribute it and/or modify
8− * it under the terms of the GNU General Public License version 2 and
9− * only version 2 as published by the Free Software Foundation.
10− *
11− * This program is distributed in the hope that it will be useful,
12− * but WITHOUT ANY WARRANTY; without even the implied warranty of
13− * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14− * GNU General Public License for more details.
157 */
168
179 #include <linux/module.h>
@@ -473,10 +465,10 @@ qca8k_set_pad_ctrl(struct qca8k_priv *priv, int port, int mode) · 455 unmodified lines
473465 static void
474466 qca8k_port_set_status(struct qca8k_priv *priv, int port, int enable)
475467 {
476− u32 mask = QCA8K_PORT_STATUS_TXMAC;
468+ u32 mask = QCA8K_PORT_STATUS_TXMAC | QCA8K_PORT_STATUS_RXMAC;
477469
478470 /* Port 0 and 6 have no internal PHY */
479− if ((port > 0) && (port < 6))
471+ if (port > 0 && port < 6)
480472 mask |= QCA8K_PORT_STATUS_LINK_AUTO;
481473
482474 if (enable)
@@ -490,6 +482,7 @@ qca8k_setup(struct dsa_switch *ds) · 7 unmodified lines
490482 {
491483 struct qca8k_priv *priv = (struct qca8k_priv *)ds->priv;
492484 int ret, i, phy_mode = -1;
485+ u32 mask;
493486
494487 /* Make sure that port 0 is the cpu port */
495488 if (!dsa_is_cpu_port(ds, 0)) {
@@ -515,7 +508,10 @@ qca8k_setup(struct dsa_switch *ds) · 19 unmodified lines
515508 if (ret < 0)
516509 return ret;
517510
518− /* Enable CPU Port */
511+ /* Enable CPU Port, force it to maximum bandwidth and full-duplex */
512+ mask = QCA8K_PORT_STATUS_SPEED_1000 | QCA8K_PORT_STATUS_TXFLOW |
513+ QCA8K_PORT_STATUS_RXFLOW | QCA8K_PORT_STATUS_DUPLEX;
514+ qca8k_write(priv, QCA8K_REG_PORT_STATUS(QCA8K_CPU_PORT), mask);
519515 qca8k_reg_set(priv, QCA8K_REG_GLOBAL_FW_CTRL0,
520516 QCA8K_GLOBAL_FW_CTRL0_CPU_PORT_EN);
521517 qca8k_port_set_status(priv, QCA8K_CPU_PORT, 1);
@@ -583,6 +579,47 @@ qca8k_setup(struct dsa_switch *ds) · 61 unmodified lines
583579 return 0;
584580 }
585581
582+static void
583+qca8k_adjust_link(struct dsa_switch *ds, int port, struct phy_device *phy)
584+{
585+ struct qca8k_priv *priv = ds->priv;
586+ u32 reg;
587+
588+ /* Force fixed-link setting for CPU port, skip others. */
589+ if (!phy_is_pseudo_fixed_link(phy))
590+ return;
591+
592+ /* Set port speed */
593+ switch (phy->speed) {
594+ case 10:
595+ reg = QCA8K_PORT_STATUS_SPEED_10;
596+ break;
597+ case 100:
598+ reg = QCA8K_PORT_STATUS_SPEED_100;
599+ break;
600+ case 1000:
601+ reg = QCA8K_PORT_STATUS_SPEED_1000;
602+ break;
603+ default:
604+ dev_dbg(priv->dev, "port%d link speed %dMbps not supported.\n",
605+ port, phy->speed);
606+ return;
607+ }
608+
609+ /* Set duplex mode */
610+ if (phy->duplex == DUPLEX_FULL)
611+ reg |= QCA8K_PORT_STATUS_DUPLEX;
612+
613+ /* Force flow control */
614+ if (dsa_is_cpu_port(ds, port))
615+ reg |= QCA8K_PORT_STATUS_RXFLOW | QCA8K_PORT_STATUS_TXFLOW;
616+
617+ /* Force link down before changing MAC options */
618+ qca8k_port_set_status(priv, port, 0);
619+ qca8k_write(priv, QCA8K_REG_PORT_STATUS(port), reg);
620+ qca8k_port_set_status(priv, port, 1);
621+}
622+
586623 static int
587624 qca8k_phy_read(struct dsa_switch *ds, int phy, int regnum)
588625 {
@@ -837,6 +874,7 @@ qca8k_get_tag_protocol(struct dsa_switch *ds, int port) · 248 unmodified lines
837874 static const struct dsa_switch_ops qca8k_switch_ops = {
838875 .get_tag_protocol = qca8k_get_tag_protocol,
839876 .setup = qca8k_setup,
877+ .adjust_link = qca8k_adjust_link,
840878 .get_strings = qca8k_get_strings,
841879 .phy_read = qca8k_phy_read,
842880 .phy_write = qca8k_phy_write,
@@ -868,6 +906,7 @@ qca8k_sw_probe(struct mdio_device *mdiodev) · 25 unmodified lines
868906 return -ENOMEM;
869907
870908 priv->bus = mdiodev->bus;
909+ priv->dev = &mdiodev->dev;
871910
872911 /* read the switches ID register */
873912 id = qca8k_read(priv, QCA8K_REG_MASK_CTRL);
@@ -939,6 +978,7 @@ static SIMPLE_DEV_PM_OPS(qca8k_pm_ops, · 65 unmodified lines
939978 qca8k_suspend, qca8k_resume);
940979
941980 static const struct of_device_id qca8k_of_match[] = {
981+ { .compatible = "qca,qca8334" },
942982 { .compatible = "qca,qca8337" },
943983 { /* sentinel */ },
944984 };
drivers/net/dsa/qca8k.h+5−2
@@ -51,8 +51,10 @@ · 50 unmodified lines
5151 #define QCA8K_GOL_MAC_ADDR0 0x60
5252 #define QCA8K_GOL_MAC_ADDR1 0x64
5353 #define QCA8K_REG_PORT_STATUS(_i) (0x07c + (_i) * 4)
54−#define QCA8K_PORT_STATUS_SPEED GENMASK(2, 0)
55−#define QCA8K_PORT_STATUS_SPEED_S 0
54+#define QCA8K_PORT_STATUS_SPEED GENMASK(1, 0)
55+#define QCA8K_PORT_STATUS_SPEED_10 0
56+#define QCA8K_PORT_STATUS_SPEED_100 0x1
57+#define QCA8K_PORT_STATUS_SPEED_1000 0x2
5658 #define QCA8K_PORT_STATUS_TXMAC BIT(2)
5759 #define QCA8K_PORT_STATUS_RXMAC BIT(3)
5860 #define QCA8K_PORT_STATUS_TXFLOW BIT(4)
@@ -165,6 +167,7 @@ struct qca8k_priv { · 106 unmodified lines
165167 struct ar8xxx_port_status port_sts[QCA8K_NUM_PORTS];
166168 struct dsa_switch *ds;
167169 struct mutex reg_mutex;
170+ struct device *dev;
168171 };
169172
170173 struct qca8k_mib_desc {