Pull habanalabs updates from Greg KH: "Here is another round of misc driver patches for 5.15-rc1. In here is only updates for the Habanalabs driver. This request is late because the previously-objected-to dma-buf patches are all removed and some fixes that you and others found are now included in here as well. All of these have been in linux-next for well over a week with no reports of problems, and they are all self-contained to only this one driver. Full details are in the shortlog" * tag 'char-misc-5.15-rc1-2' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/char-misc: (61 commits) habanalabs/gaudi: hwmon default card name habanalabs: add support for f/w reset habanalabs/gaudi: block ICACHE_BASE_ADDERESS_HIGH in TPC habanalabs: cannot sleep while holding spinlock habanalabs: never copy_from_user inside spinlock habanalabs: remove unnecessary device status check habanalabs: disable IRQ in user interrupts spinlock habanalabs: add "in device creation" status habanalabs/gaudi: invalidate PMMU mem cache on init habanalabs/gaudi: size should be printed in decimal habanalabs/gaudi: define DC POWER for secured PMC habanalabs/gaudi: unmask out of bounds SLM access interrupt habanalabs: add userptr_lookup node in debugfs habanalabs/gaudi: fetch TPC/MME ECC errors from F/W habanalabs: modify multi-CS to wait on stream masters habanalabs/gaudi: add monitored SOBs to state dump habanalabs/gaudi: restore user registers when context opens habanalabs/gaudi: increase boot fit timeout habanalabs: update to latest firmware headers habanalabs/gaudi: minimize number of register reads ...
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| @@ -276,7 +276,17 @@ enum hl_device_status { · 275 unmodified lines | |||
| 276 | HL_DEVICE_STATUS_OPERATIONAL, | 276 | HL_DEVICE_STATUS_OPERATIONAL, |
| 277 | HL_DEVICE_STATUS_IN_RESET, | 277 | HL_DEVICE_STATUS_IN_RESET, |
| 278 | HL_DEVICE_STATUS_MALFUNCTION, | 278 | HL_DEVICE_STATUS_MALFUNCTION, |
| 279 | HL_DEVICE_STATUS_NEEDS_RESET | 279 | HL_DEVICE_STATUS_NEEDS_RESET, |
| 280 | HL_DEVICE_STATUS_IN_DEVICE_CREATION, | ||
| 281 | HL_DEVICE_STATUS_LAST = HL_DEVICE_STATUS_IN_DEVICE_CREATION | ||
| 282 | }; | ||
| 283 | |||
| 284 | enum hl_server_type { | ||
| 285 | HL_SERVER_TYPE_UNKNOWN = 0, | ||
| 286 | HL_SERVER_GAUDI_HLS1 = 1, | ||
| 287 | HL_SERVER_GAUDI_HLS1H = 2, | ||
| 288 | HL_SERVER_GAUDI_TYPE1 = 3, | ||
| 289 | HL_SERVER_GAUDI_TYPE2 = 4 | ||
| 280 | }; | 290 | }; |
| 281 | 291 | ||
| 282 | /* Opcode for management ioctl | 292 | /* Opcode for management ioctl |
| @@ -337,17 +347,49 @@ enum hl_device_status { · 54 unmodified lines | |||
| 337 | #define HL_INFO_VERSION_MAX_LEN 128 | 347 | #define HL_INFO_VERSION_MAX_LEN 128 |
| 338 | #define HL_INFO_CARD_NAME_MAX_LEN 16 | 348 | #define HL_INFO_CARD_NAME_MAX_LEN 16 |
| 339 | 349 | ||
| 350 | /** | ||
| 351 | * struct hl_info_hw_ip_info - hardware information on various IPs in the ASIC | ||
| 352 | * @sram_base_address: The first SRAM physical base address that is free to be | ||
| 353 | * used by the user. | ||
| 354 | * @dram_base_address: The first DRAM virtual or physical base address that is | ||
| 355 | * free to be used by the user. | ||
| 356 | * @dram_size: The DRAM size that is available to the user. | ||
| 357 | * @sram_size: The SRAM size that is available to the user. | ||
| 358 | * @num_of_events: The number of events that can be received from the f/w. This | ||
| 359 | * is needed so the user can what is the size of the h/w events | ||
| 360 | * array he needs to pass to the kernel when he wants to fetch | ||
| 361 | * the event counters. | ||
| 362 | * @device_id: PCI device ID of the ASIC. | ||
| 363 | * @module_id: Module ID of the ASIC for mezzanine cards in servers | ||
| 364 | * (From OCP spec). | ||
| 365 | * @first_available_interrupt_id: The first available interrupt ID for the user | ||
| 366 | * to be used when it works with user interrupts. | ||
| 367 | * @server_type: Server type that the Gaudi ASIC is currently installed in. | ||
| 368 | * The value is according to enum hl_server_type | ||
| 369 | * @cpld_version: CPLD version on the board. | ||
| 370 | * @psoc_pci_pll_nr: PCI PLL NR value. Needed by the profiler in some ASICs. | ||
| 371 | * @psoc_pci_pll_nf: PCI PLL NF value. Needed by the profiler in some ASICs. | ||
| 372 | * @psoc_pci_pll_od: PCI PLL OD value. Needed by the profiler in some ASICs. | ||
| 373 | * @psoc_pci_pll_div_factor: PCI PLL DIV factor value. Needed by the profiler | ||
| 374 | * in some ASICs. | ||
| 375 | * @tpc_enabled_mask: Bit-mask that represents which TPCs are enabled. Relevant | ||
| 376 | * for Goya/Gaudi only. | ||
| 377 | * @dram_enabled: Whether the DRAM is enabled. | ||
| 378 | * @cpucp_version: The CPUCP f/w version. | ||
| 379 | * @card_name: The card name as passed by the f/w. | ||
| 380 | * @dram_page_size: The DRAM physical page size. | ||
| 381 | */ | ||
| 340 | struct hl_info_hw_ip_info { | 382 | struct hl_info_hw_ip_info { |
| 341 | __u64 sram_base_address; | 383 | __u64 sram_base_address; |
| 342 | __u64 dram_base_address; | 384 | __u64 dram_base_address; |
| 343 | __u64 dram_size; | 385 | __u64 dram_size; |
| 344 | __u32 sram_size; | 386 | __u32 sram_size; |
| 345 | __u32 num_of_events; | 387 | __u32 num_of_events; |
| 346 | __u32 device_id; /* PCI Device ID */ | 388 | __u32 device_id; |
| 347 | __u32 module_id; /* For mezzanine cards in servers (From OCP spec.) */ | 389 | __u32 module_id; |
| 348 | __u32 reserved; | 390 | __u32 reserved; |
| 349 | __u16 first_available_interrupt_id; | 391 | __u16 first_available_interrupt_id; |
| 350 | __u16 reserved2; | 392 | __u16 server_type; |
| 351 | __u32 cpld_version; | 393 | __u32 cpld_version; |
| 352 | __u32 psoc_pci_pll_nr; | 394 | __u32 psoc_pci_pll_nr; |
| 353 | __u32 psoc_pci_pll_nf; | 395 | __u32 psoc_pci_pll_nf; |
| @@ -358,7 +400,7 @@ struct hl_info_hw_ip_info { · 4 unmodified lines | |||
| 358 | __u8 pad[2]; | 400 | __u8 pad[2]; |
| 359 | __u8 cpucp_version[HL_INFO_VERSION_MAX_LEN]; | 401 | __u8 cpucp_version[HL_INFO_VERSION_MAX_LEN]; |
| 360 | __u8 card_name[HL_INFO_CARD_NAME_MAX_LEN]; | 402 | __u8 card_name[HL_INFO_CARD_NAME_MAX_LEN]; |
| 361 | __u64 reserved3; | 403 | __u64 reserved2; |
| 362 | __u64 dram_page_size; | 404 | __u64 dram_page_size; |
| 363 | }; | 405 | }; |
| 364 | 406 | ||
| @@ -628,12 +670,21 @@ struct hl_cs_chunk { · 263 unmodified lines | |||
| 628 | __u64 cb_handle; | 670 | __u64 cb_handle; |
| 629 | 671 | ||
| 630 | /* Relevant only when HL_CS_FLAGS_WAIT or | 672 | /* Relevant only when HL_CS_FLAGS_WAIT or |
| 631 | * HL_CS_FLAGS_COLLECTIVE_WAIT is set. | 673 | * HL_CS_FLAGS_COLLECTIVE_WAIT is set |
| 632 | * This holds address of array of u64 values that contain | 674 | * This holds address of array of u64 values that contain |
| 633 | * signal CS sequence numbers. The wait described by this job | 675 | * signal CS sequence numbers. The wait described by |
| 634 | * will listen on all those signals (wait event per signal) | 676 | * this job will listen on all those signals |
| 677 | * (wait event per signal) | ||
| 635 | */ | 678 | */ |
| 636 | __u64 signal_seq_arr; | 679 | __u64 signal_seq_arr; |
| 680 | |||
| 681 | /* | ||
| 682 | * Relevant only when HL_CS_FLAGS_WAIT or | ||
| 683 | * HL_CS_FLAGS_COLLECTIVE_WAIT is set | ||
| 684 | * along with HL_CS_FLAGS_ENCAP_SIGNALS. | ||
| 685 | * This is the CS sequence which has the encapsulated signals. | ||
| 686 | */ | ||
| 687 | __u64 encaps_signal_seq; | ||
| 637 | }; | 688 | }; |
| 638 | 689 | ||
| 639 | /* Index of queue to put the CB on */ | 690 | /* Index of queue to put the CB on */ |
| @@ -651,6 +702,17 @@ struct hl_cs_chunk { · 11 unmodified lines | |||
| 651 | * Number of entries in signal_seq_arr | 702 | * Number of entries in signal_seq_arr |
| 652 | */ | 703 | */ |
| 653 | __u32 num_signal_seq_arr; | 704 | __u32 num_signal_seq_arr; |
| 705 | |||
| 706 | /* Relevant only when HL_CS_FLAGS_WAIT or | ||
| 707 | * HL_CS_FLAGS_COLLECTIVE_WAIT is set along | ||
| 708 | * with HL_CS_FLAGS_ENCAP_SIGNALS | ||
| 709 | * This set the signals range that the user want to wait for | ||
| 710 | * out of the whole reserved signals range. | ||
| 711 | * e.g if the signals range is 20, and user don't want | ||
| 712 | * to wait for signal 8, so he set this offset to 7, then | ||
| 713 | * he call the API again with 9 and so on till 20. | ||
| 714 | */ | ||
| 715 | __u32 encaps_signal_offset; | ||
| 654 | }; | 716 | }; |
| 655 | 717 | ||
| 656 | /* HL_CS_CHUNK_FLAGS_* */ | 718 | /* HL_CS_CHUNK_FLAGS_* */ |
| @@ -678,6 +740,28 @@ struct hl_cs_chunk { · 21 unmodified lines | |||
| 678 | #define HL_CS_FLAGS_CUSTOM_TIMEOUT 0x200 | 740 | #define HL_CS_FLAGS_CUSTOM_TIMEOUT 0x200 |
| 679 | #define HL_CS_FLAGS_SKIP_RESET_ON_TIMEOUT 0x400 | 741 | #define HL_CS_FLAGS_SKIP_RESET_ON_TIMEOUT 0x400 |
| 680 | 742 | ||
| 743 | /* | ||
| 744 | * The encapsulated signals CS is merged into the existing CS ioctls. | ||
| 745 | * In order to use this feature need to follow the below procedure: | ||
| 746 | * 1. Reserve signals, set the CS type to HL_CS_FLAGS_RESERVE_SIGNALS_ONLY | ||
| 747 | * the output of this API will be the SOB offset from CFG_BASE. | ||
| 748 | * this address will be used to patch CB cmds to do the signaling for this | ||
| 749 | * SOB by incrementing it's value. | ||
| 750 | * for reverting the reservation use HL_CS_FLAGS_UNRESERVE_SIGNALS_ONLY | ||
| 751 | * CS type, note that this might fail if out-of-sync happened to the SOB | ||
| 752 | * value, in case other signaling request to the same SOB occurred between | ||
| 753 | * reserve-unreserve calls. | ||
| 754 | * 2. Use the staged CS to do the encapsulated signaling jobs. | ||
| 755 | * use HL_CS_FLAGS_STAGED_SUBMISSION and HL_CS_FLAGS_STAGED_SUBMISSION_FIRST | ||
| 756 | * along with HL_CS_FLAGS_ENCAP_SIGNALS flag, and set encaps_signal_offset | ||
| 757 | * field. This offset allows app to wait on part of the reserved signals. | ||
| 758 | * 3. Use WAIT/COLLECTIVE WAIT CS along with HL_CS_FLAGS_ENCAP_SIGNALS flag | ||
| 759 | * to wait for the encapsulated signals. | ||
| 760 | */ | ||
| 761 | #define HL_CS_FLAGS_ENCAP_SIGNALS 0x800 | ||
| 762 | #define HL_CS_FLAGS_RESERVE_SIGNALS_ONLY 0x1000 | ||
| 763 | #define HL_CS_FLAGS_UNRESERVE_SIGNALS_ONLY 0x2000 | ||
| 764 | |||
| 681 | #define HL_CS_STATUS_SUCCESS 0 | 765 | #define HL_CS_STATUS_SUCCESS 0 |
| 682 | 766 | ||
| 683 | #define HL_MAX_JOBS_PER_CS 512 | 767 | #define HL_MAX_JOBS_PER_CS 512 |
| @@ -690,10 +774,35 @@ struct hl_cs_in { · 6 unmodified lines | |||
| 690 | /* holds address of array of hl_cs_chunk for execution phase */ | 774 | /* holds address of array of hl_cs_chunk for execution phase */ |
| 691 | __u64 chunks_execute; | 775 | __u64 chunks_execute; |
| 692 | 776 | ||
| 693 | /* Sequence number of a staged submission CS | 777 | union { |
| 694 | * valid only if HL_CS_FLAGS_STAGED_SUBMISSION is set | 778 | /* |
| 695 | */ | 779 | * Sequence number of a staged submission CS |
| 696 | __u64 seq; | 780 | * valid only if HL_CS_FLAGS_STAGED_SUBMISSION is set and |
| 781 | * HL_CS_FLAGS_STAGED_SUBMISSION_FIRST is unset. | ||
| 782 | */ | ||
| 783 | __u64 seq; | ||
| 784 | |||
| 785 | /* | ||
| 786 | * Encapsulated signals handle id | ||
| 787 | * Valid for two flows: | ||
| 788 | * 1. CS with encapsulated signals: | ||
| 789 | * when HL_CS_FLAGS_STAGED_SUBMISSION and | ||
| 790 | * HL_CS_FLAGS_STAGED_SUBMISSION_FIRST | ||
| 791 | * and HL_CS_FLAGS_ENCAP_SIGNALS are set. | ||
| 792 | * 2. unreserve signals: | ||
| 793 | * valid when HL_CS_FLAGS_UNRESERVE_SIGNALS_ONLY is set. | ||
| 794 | */ | ||
| 795 | __u32 encaps_sig_handle_id; | ||
| 796 | |||
| 797 | /* Valid only when HL_CS_FLAGS_RESERVE_SIGNALS_ONLY is set */ | ||
| 798 | struct { | ||
| 799 | /* Encapsulated signals number */ | ||
| 800 | __u32 encaps_signals_count; | ||
| 801 | |||
| 802 | /* Encapsulated signals queue index (stream) */ | ||
| 803 | __u32 encaps_signals_q_idx; | ||
| 804 | }; | ||
| 805 | }; | ||
| 697 | 806 | ||
| 698 | /* Number of chunks in restore phase array. Maximum number is | 807 | /* Number of chunks in restore phase array. Maximum number is |
| 699 | * HL_MAX_JOBS_PER_CS | 808 | * HL_MAX_JOBS_PER_CS |
| @@ -718,14 +827,31 @@ struct hl_cs_in { · 18 unmodified lines | |||
| 718 | }; | 827 | }; |
| 719 | 828 | ||
| 720 | struct hl_cs_out { | 829 | struct hl_cs_out { |
| 830 | union { | ||
| 831 | /* | ||
| 832 | * seq holds the sequence number of the CS to pass to wait | ||
| 833 | * ioctl. All values are valid except for 0 and ULLONG_MAX | ||
| 834 | */ | ||
| 835 | __u64 seq; | ||
| 836 | |||
| 837 | /* Valid only when HL_CS_FLAGS_RESERVE_SIGNALS_ONLY is set */ | ||
| 838 | struct { | ||
| 839 | /* This is the resereved signal handle id */ | ||
| 840 | __u32 handle_id; | ||
| 841 | |||
| 842 | /* This is the signals count */ | ||
| 843 | __u32 count; | ||
| 844 | }; | ||
| 845 | }; | ||
| 846 | |||
| 847 | /* HL_CS_STATUS */ | ||
| 848 | __u32 status; | ||
| 849 | |||
| 721 | /* | 850 | /* |
| 722 | * seq holds the sequence number of the CS to pass to wait ioctl. All | 851 | * SOB base address offset |
| 723 | * values are valid except for 0 and ULLONG_MAX | 852 | * Valid only when HL_CS_FLAGS_RESERVE_SIGNALS_ONLY is set |
| 724 | */ | 853 | */ |
| 725 | __u64 seq; | 854 | __u32 sob_base_addr_offset; |
| 726 | /* HL_CS_STATUS_* */ | ||
| 727 | __u32 status; | ||
| 728 | __u32 pad; | ||
| 729 | }; | 855 | }; |
| 730 | 856 | ||
| 731 | union hl_cs_args { | 857 | union hl_cs_args { |
| @@ -735,11 +861,18 @@ union hl_cs_args { · 3 unmodified lines | |||
| 735 | 861 | ||
| 736 | #define HL_WAIT_CS_FLAGS_INTERRUPT 0x2 | 862 | #define HL_WAIT_CS_FLAGS_INTERRUPT 0x2 |
| 737 | #define HL_WAIT_CS_FLAGS_INTERRUPT_MASK 0xFFF00000 | 863 | #define HL_WAIT_CS_FLAGS_INTERRUPT_MASK 0xFFF00000 |
| 864 | #define HL_WAIT_CS_FLAGS_MULTI_CS 0x4 | ||
| 865 | |||
| 866 | #define HL_WAIT_MULTI_CS_LIST_MAX_LEN 32 | ||
| 738 | 867 | ||
| 739 | struct hl_wait_cs_in { | 868 | struct hl_wait_cs_in { |
| 740 | union { | 869 | union { |
| 741 | struct { | 870 | struct { |
| 742 | /* Command submission sequence number */ | 871 | /* |
| 872 | * In case of wait_cs holds the CS sequence number. | ||
| 873 | * In case of wait for multi CS hold a user pointer to | ||
| 874 | * an array of CS sequence numbers | ||
| 875 | */ | ||
| 743 | __u64 seq; | 876 | __u64 seq; |
| 744 | /* Absolute timeout to wait for command submission | 877 | /* Absolute timeout to wait for command submission |
| 745 | * in microseconds | 878 | * in microseconds |
| @@ -767,12 +900,17 @@ struct hl_wait_cs_in { · 21 unmodified lines | |||
| 767 | 900 | ||
| 768 | /* Context ID - Currently not in use */ | 901 | /* Context ID - Currently not in use */ |
| 769 | __u32 ctx_id; | 902 | __u32 ctx_id; |
| 903 | |||
| 770 | /* HL_WAIT_CS_FLAGS_* | 904 | /* HL_WAIT_CS_FLAGS_* |
| 771 | * If HL_WAIT_CS_FLAGS_INTERRUPT is set, this field should include | 905 | * If HL_WAIT_CS_FLAGS_INTERRUPT is set, this field should include |
| 772 | * interrupt id according to HL_WAIT_CS_FLAGS_INTERRUPT_MASK, in order | 906 | * interrupt id according to HL_WAIT_CS_FLAGS_INTERRUPT_MASK, in order |
| 773 | * not to specify an interrupt id ,set mask to all 1s. | 907 | * not to specify an interrupt id ,set mask to all 1s. |
| 774 | */ | 908 | */ |
| 775 | __u32 flags; | 909 | __u32 flags; |
| 910 | |||
| 911 | /* Multi CS API info- valid entries in multi-CS array */ | ||
| 912 | __u8 seq_arr_len; | ||
| 913 | __u8 pad[7]; | ||
| 776 | }; | 914 | }; |
| 777 | 915 | ||
| 778 | #define HL_WAIT_CS_STATUS_COMPLETED 0 | 916 | #define HL_WAIT_CS_STATUS_COMPLETED 0 |
| @@ -789,8 +927,15 @@ struct hl_wait_cs_out { · 10 unmodified lines | |||
| 789 | __u32 status; | 927 | __u32 status; |
| 790 | /* HL_WAIT_CS_STATUS_FLAG* */ | 928 | /* HL_WAIT_CS_STATUS_FLAG* */ |
| 791 | __u32 flags; | 929 | __u32 flags; |
| 792 | /* valid only if HL_WAIT_CS_STATUS_FLAG_TIMESTAMP_VLD is set */ | 930 | /* |
| 931 | * valid only if HL_WAIT_CS_STATUS_FLAG_TIMESTAMP_VLD is set | ||
| 932 | * for wait_cs: timestamp of CS completion | ||
| 933 | * for wait_multi_cs: timestamp of FIRST CS completion | ||
| 934 | */ | ||
| 793 | __s64 timestamp_nsec; | 935 | __s64 timestamp_nsec; |
| 936 | /* multi CS completion bitmap */ | ||
| 937 | __u32 cs_completion_map; | ||
| 938 | __u32 pad; | ||
| 794 | }; | 939 | }; |
| 795 | 940 | ||
| 796 | union hl_wait_cs_args { | 941 | union hl_wait_cs_args { |
| @@ -813,6 +958,7 @@ union hl_wait_cs_args { · 16 unmodified lines | |||
| 813 | #define HL_MEM_CONTIGUOUS 0x1 | 958 | #define HL_MEM_CONTIGUOUS 0x1 |
| 814 | #define HL_MEM_SHARED 0x2 | 959 | #define HL_MEM_SHARED 0x2 |
| 815 | #define HL_MEM_USERPTR 0x4 | 960 | #define HL_MEM_USERPTR 0x4 |
| 961 | #define HL_MEM_FORCE_HINT 0x8 | ||
| 816 | 962 | ||
| 817 | struct hl_mem_in { | 963 | struct hl_mem_in { |
| 818 | union { | 964 | union { |