* master.kernel.org:/home/rmk/linux-2.6-arm: ARM: 6524/1: GIC irq desciptor bug fix ARM: 6523/1: iop: ensure sched_clock() is notrace ARM: 6456/1: Fix for building DEBUG with sa11xx_base.c as a module. ARM: 6519/1: kuser: Fix incorrect cmpxchg syscall in kuser helpers ARM: 6505/1: kprobes: Don't HAVE_KPROBES when CONFIG_THUMB2_KERNEL is selected ARM: 6508/1: vexpress: Correct data alignment in headsmp.S for CONFIG_THUMB2_KERNEL ARM: 6507/1: RealView: Correct data alignment in headsmp.S for CONFIG_THUMB2_KERNEL ARM: 6504/1: Thumb-2: Fix long-distance conditional branches in head.S for Thumb-2. ARM: 6503/1: Thumb-2: Restore sensible zImage header layout for CONFIG_THUMB2_KERNEL ARM: 6502/1: Thumb-2: Fix CONFIG_THUMB2_KERNEL breakage in compressed/head.S ARM: 6501/1: Thumb-2: Correct data alignment for CONFIG_THUMB2_KERNEL in mm/proc-v7.S ARM: 6500/1: Thumb-2: Correct data alignment for CONFIG_THUMB2_KERNEL in kernel/head.S ARM: 6499/1: Thumb-2: Correct data alignment for CONFIG_THUMB2_KERNEL in bootp/init.S ARM: 6498/1: vfp: Correct data alignment for CONFIG_THUMB2_KERNEL ARM: 6497/1: kexec: Correct data alignment for CONFIG_THUMB2_KERNEL ARM: 6496/1: GIC: Do not try to register more then NR_IRQS interrupts ARM: cns3xxx: Fix build with CONFIG_PCI=y
Unified · Split
| @@ -9,7 +9,7 @@ config ARM · 8 unmodified lines | ||
| 9 | 9 | select GENERIC_ATOMIC64 if (!CPU_32v6K || !AEABI) |
| 10 | 10 | select HAVE_OPROFILE if (HAVE_PERF_EVENTS) |
| 11 | 11 | select HAVE_ARCH_KGDB |
| 12 | − select HAVE_KPROBES if (!XIP_KERNEL) | |
| 12 | + select HAVE_KPROBES if (!XIP_KERNEL && !THUMB2_KERNEL) | |
| 13 | 13 | select HAVE_KRETPROBES if (HAVE_KPROBES) |
| 14 | 14 | select HAVE_FUNCTION_TRACER if (!XIP_KERNEL) |
| 15 | 15 | select HAVE_FTRACE_MCOUNT_RECORD if (!XIP_KERNEL) |
| @@ -70,12 +70,7 @@ else · 69 unmodified lines | ||
| 70 | 70 | $(obj)/uImage: LOADADDR=$(ZRELADDR) |
| 71 | 71 | endif |
| 72 | 72 | |
| 73 | −ifeq ($(CONFIG_THUMB2_KERNEL),y) | |
| 74 | −# Set bit 0 to 1 so that "mov pc, rx" switches to Thumb-2 mode | |
| 75 | −$(obj)/uImage: STARTADDR=$(shell echo $(LOADADDR) | sed -e "s/.$$/1/") | |
| 76 | −else | |
| 77 | 73 | $(obj)/uImage: STARTADDR=$(LOADADDR) |
| 78 | −endif | |
| 79 | 74 | |
| 80 | 75 | $(obj)/uImage: $(obj)/zImage FORCE |
| 81 | 76 | $(call if_changed,uimage) |
| @@ -73,6 +73,8 @@ move: ldmia r4!, {r7 - r10} @ move 32-bytes at a time · 72 unmodified lines | ||
| 73 | 73 | |
| 74 | 74 | .size _start, . - _start |
| 75 | 75 | |
| 76 | + .align | |
| 77 | + | |
| 76 | 78 | .type data,#object |
| 77 | 79 | data: .word initrd_start @ source initrd address |
| 78 | 80 | .word initrd_phys @ destination initrd address |
| @@ -125,9 +125,13 @@ wait: mrc p14, 0, pc, c0, c1, 0 · 124 unmodified lines | ||
| 125 | 125 | * sort out different calling conventions |
| 126 | 126 | */ |
| 127 | 127 | .align |
| 128 | + .arm @ Always enter in ARM state | |
| 128 | 129 | start: |
| 129 | 130 | .type start,#function |
| 130 | − .rept 8 | |
| 131 | + THUMB( adr r12, BSYM(1f) ) | |
| 132 | + THUMB( bx r12 ) | |
| 133 | + THUMB( .rept 6 ) | |
| 134 | + ARM( .rept 8 ) | |
| 131 | 135 | mov r0, r0 |
| 132 | 136 | .endr |
| 133 | 137 | |
| @@ -135,6 +139,7 @@ start: · 1 unmodified line | ||
| 135 | 139 | .word 0x016f2818 @ Magic numbers to help the loader |
| 136 | 140 | .word start @ absolute load/run zImage address |
| 137 | 141 | .word _edata @ zImage end address |
| 142 | + THUMB( .thumb ) | |
| 138 | 143 | 1: mov r7, r1 @ save architecture ID |
| 139 | 144 | mov r8, r2 @ save atags pointer |
| 140 | 145 | |
| @@ -174,7 +179,8 @@ not_angel: · 33 unmodified lines | ||
| 174 | 179 | ldr sp, [r0, #28] |
| 175 | 180 | #ifdef CONFIG_AUTO_ZRELADDR |
| 176 | 181 | @ determine final kernel image address |
| 177 | − and r4, pc, #0xf8000000 | |
| 182 | + mov r4, pc | |
| 183 | + and r4, r4, #0xf8000000 | |
| 178 | 184 | add r4, r4, #TEXT_OFFSET |
| 179 | 185 | #else |
| 180 | 186 | ldr r4, =zreladdr |
| @@ -445,7 +451,8 @@ __setup_mmu: sub r3, r4, #16384 @ Page directory size · 264 unmodified lines | ||
| 445 | 451 | */ |
| 446 | 452 | mov r1, #0x1e |
| 447 | 453 | orr r1, r1, #3 << 10 |
| 448 | − mov r2, pc, lsr #20 | |
| 454 | + mov r2, pc | |
| 455 | + mov r2, r2, lsr #20 | |
| 449 | 456 | orr r1, r1, r2, lsl #20 |
| 450 | 457 | add r0, r3, r2, lsl #2 |
| 451 | 458 | str r1, [r0], #4 |
| @@ -146,9 +146,15 @@ static int gic_set_cpu(unsigned int irq, const struct cpumask *mask_val) · 145 unmodified lines | ||
| 146 | 146 | unsigned int shift = (irq % 4) * 8; |
| 147 | 147 | unsigned int cpu = cpumask_first(mask_val); |
| 148 | 148 | u32 val; |
| 149 | + struct irq_desc *desc; | |
| 149 | 150 | |
| 150 | 151 | spin_lock(&irq_controller_lock); |
| 151 | − irq_desc[irq].node = cpu; | |
| 152 | + desc = irq_to_desc(irq); | |
| 153 | + if (desc == NULL) { | |
| 154 | + spin_unlock(&irq_controller_lock); | |
| 155 | + return -EINVAL; | |
| 156 | + } | |
| 157 | + desc->node = cpu; | |
| 152 | 158 | val = readl(reg) & ~(0xff << shift); |
| 153 | 159 | val |= 1 << (cpu + shift); |
| 154 | 160 | writel(val, reg); |
| @@ -210,7 +216,7 @@ void __init gic_cascade_irq(unsigned int gic_nr, unsigned int irq) · 55 unmodified lines | ||
| 210 | 216 | void __init gic_dist_init(unsigned int gic_nr, void __iomem *base, |
| 211 | 217 | unsigned int irq_start) |
| 212 | 218 | { |
| 213 | − unsigned int max_irq, i; | |
| 219 | + unsigned int gic_irqs, irq_limit, i; | |
| 214 | 220 | u32 cpumask = 1 << smp_processor_id(); |
| 215 | 221 | |
| 216 | 222 | if (gic_nr >= MAX_GIC_NR) |
| @@ -226,47 +232,49 @@ void __init gic_dist_init(unsigned int gic_nr, void __iomem *base, · 9 unmodified lines | ||
| 226 | 232 | |
| 227 | 233 | /* |
| 228 | 234 | * Find out how many interrupts are supported. |
| 229 | − */ | |
| 230 | − max_irq = readl(base + GIC_DIST_CTR) & 0x1f; | |
| 231 | − max_irq = (max_irq + 1) * 32; | |
| 232 | − | |
| 233 | − /* | |
| 234 | 235 | * The GIC only supports up to 1020 interrupt sources. |
| 235 | − * Limit this to either the architected maximum, or the | |
| 236 | − * platform maximum. | |
| 237 | 236 | */ |
| 238 | − if (max_irq > max(1020, NR_IRQS)) | |
| 239 | − max_irq = max(1020, NR_IRQS); | |
| 237 | + gic_irqs = readl(base + GIC_DIST_CTR) & 0x1f; | |
| 238 | + gic_irqs = (gic_irqs + 1) * 32; | |
| 239 | + if (gic_irqs > 1020) | |
| 240 | + gic_irqs = 1020; | |
| 240 | 241 | |
| 241 | 242 | /* |
| 242 | 243 | * Set all global interrupts to be level triggered, active low. |
| 243 | 244 | */ |
| 244 | − for (i = 32; i < max_irq; i += 16) | |
| 245 | + for (i = 32; i < gic_irqs; i += 16) | |
| 245 | 246 | writel(0, base + GIC_DIST_CONFIG + i * 4 / 16); |
| 246 | 247 | |
| 247 | 248 | /* |
| 248 | 249 | * Set all global interrupts to this CPU only. |
| 249 | 250 | */ |
| 250 | − for (i = 32; i < max_irq; i += 4) | |
| 251 | + for (i = 32; i < gic_irqs; i += 4) | |
| 251 | 252 | writel(cpumask, base + GIC_DIST_TARGET + i * 4 / 4); |
| 252 | 253 | |
| 253 | 254 | /* |
| 254 | 255 | * Set priority on all global interrupts. |
| 255 | 256 | */ |
| 256 | − for (i = 32; i < max_irq; i += 4) | |
| 257 | + for (i = 32; i < gic_irqs; i += 4) | |
| 257 | 258 | writel(0xa0a0a0a0, base + GIC_DIST_PRI + i * 4 / 4); |
| 258 | 259 | |
| 259 | 260 | /* |
| 260 | 261 | * Disable all interrupts. Leave the PPI and SGIs alone |
| 261 | 262 | * as these enables are banked registers. |
| 262 | 263 | */ |
| 263 | − for (i = 32; i < max_irq; i += 32) | |
| 264 | + for (i = 32; i < gic_irqs; i += 32) | |
| 264 | 265 | writel(0xffffffff, base + GIC_DIST_ENABLE_CLEAR + i * 4 / 32); |
| 265 | 266 | |
| 267 | + /* | |
| 268 | + * Limit number of interrupts registered to the platform maximum | |
| 269 | + */ | |
| 270 | + irq_limit = gic_data[gic_nr].irq_offset + gic_irqs; | |
| 271 | + if (WARN_ON(irq_limit > NR_IRQS)) | |
| 272 | + irq_limit = NR_IRQS; | |
| 273 | + | |
| 266 | 274 | /* |
| 267 | 275 | * Setup the Linux IRQ subsystem. |
| 268 | 276 | */ |
| 269 | − for (i = irq_start; i < gic_data[gic_nr].irq_offset + max_irq; i++) { | |
| 277 | + for (i = irq_start; i < irq_limit; i++) { | |
| 270 | 278 | set_irq_chip(i, &gic_chip); |
| 271 | 279 | set_irq_chip_data(i, &gic_data[gic_nr]); |
| 272 | 280 | set_irq_handler(i, handle_level_irq); |
| @@ -911,7 +911,7 @@ __kuser_cmpxchg: @ 0xffff0fc0 · 910 unmodified lines | ||
| 911 | 911 | * A special ghost syscall is used for that (see traps.c). |
| 912 | 912 | */ |
| 913 | 913 | stmfd sp!, {r7, lr} |
| 914 | − ldr r7, =1f @ it's 20 bits | |
| 914 | + ldr r7, 1f @ it's 20 bits | |
| 915 | 915 | swi __ARM_NR_cmpxchg |
| 916 | 916 | ldmfd sp!, {r7, pc} |
| 917 | 917 | 1: .word __ARM_NR_cmpxchg |
| @@ -85,9 +85,11 @@ ENTRY(stext) · 84 unmodified lines | ||
| 85 | 85 | mrc p15, 0, r9, c0, c0 @ get processor id |
| 86 | 86 | bl __lookup_processor_type @ r5=procinfo r9=cpuid |
| 87 | 87 | movs r10, r5 @ invalid processor (r5=0)? |
| 88 | + THUMB( it eq ) @ force fixup-able long branch encoding | |
| 88 | 89 | beq __error_p @ yes, error 'p' |
| 89 | 90 | bl __lookup_machine_type @ r5=machinfo |
| 90 | 91 | movs r8, r5 @ invalid machine (r5=0)? |
| 92 | + THUMB( it eq ) @ force fixup-able long branch encoding | |
| 91 | 93 | beq __error_a @ yes, error 'a' |
| 92 | 94 | bl __vet_atags |
| 93 | 95 | #ifdef CONFIG_SMP_ON_UP |
| @@ -262,6 +264,7 @@ __create_page_tables: · 168 unmodified lines | ||
| 262 | 264 | mov pc, lr |
| 263 | 265 | ENDPROC(__create_page_tables) |
| 264 | 266 | .ltorg |
| 267 | + .align | |
| 265 | 268 | __enable_mmu_loc: |
| 266 | 269 | .long . |
| 267 | 270 | .long __enable_mmu |
| @@ -282,6 +285,7 @@ ENTRY(secondary_startup) · 14 unmodified lines | ||
| 282 | 285 | bl __lookup_processor_type |
| 283 | 286 | movs r10, r5 @ invalid processor? |
| 284 | 287 | moveq r0, #'p' @ yes, error 'p' |
| 288 | + THUMB( it eq ) @ force fixup-able long branch encoding | |
| 285 | 289 | beq __error_p |
| 286 | 290 | |
| 287 | 291 | /* |
| @@ -308,6 +312,8 @@ ENTRY(__secondary_switched) · 20 unmodified lines | ||
| 308 | 312 | b secondary_start_kernel |
| 309 | 313 | ENDPROC(__secondary_switched) |
| 310 | 314 | |
| 315 | + .align | |
| 316 | + | |
| 311 | 317 | .type __secondary_data, %object |
| 312 | 318 | __secondary_data: |
| 313 | 319 | .long . |
| @@ -413,6 +419,7 @@ __fixup_smp_on_up: · 99 unmodified lines | ||
| 413 | 419 | mov pc, lr |
| 414 | 420 | ENDPROC(__fixup_smp) |
| 415 | 421 | |
| 422 | + .align | |
| 416 | 423 | 1: .word . |
| 417 | 424 | .word __smpalt_begin |
| 418 | 425 | .word __smpalt_end |
| @@ -59,6 +59,8 @@ relocate_new_kernel: · 58 unmodified lines | ||
| 59 | 59 | ldr r2,kexec_boot_atags |
| 60 | 60 | mov pc,lr |
| 61 | 61 | |
| 62 | + .align | |
| 63 | + | |
| 62 | 64 | .globl kexec_start_address |
| 63 | 65 | kexec_start_address: |
| 64 | 66 | .long 0x0 |
| @@ -369,7 +369,7 @@ static int __init cns3xxx_pcie_init(void) · 368 unmodified lines | ||
| 369 | 369 | { |
| 370 | 370 | int i; |
| 371 | 371 | |
| 372 | − hook_fault_code(16 + 6, cns3xxx_pcie_abort_handler, SIGBUS, | |
| 372 | + hook_fault_code(16 + 6, cns3xxx_pcie_abort_handler, SIGBUS, 0, | |
| 373 | 373 | "imprecise external abort"); |
| 374 | 374 | |
| 375 | 375 | for (i = 0; i < ARRAY_SIZE(cns3xxx_pcie); i++) { |
| @@ -35,5 +35,6 @@ pen: ldr r7, [r6] · 34 unmodified lines | ||
| 35 | 35 | */ |
| 36 | 36 | b secondary_startup |
| 37 | 37 | |
| 38 | + .align | |
| 38 | 39 | 1: .long . |
| 39 | 40 | .long pen_release |
| @@ -35,5 +35,6 @@ pen: ldr r7, [r6] · 34 unmodified lines | ||
| 35 | 35 | */ |
| 36 | 36 | b secondary_startup |
| 37 | 37 | |
| 38 | + .align | |
| 38 | 39 | 1: .long . |
| 39 | 40 | .long pen_release |
| @@ -381,7 +381,7 @@ __v7_ca9mp_proc_info: · 380 unmodified lines | ||
| 381 | 381 | PMD_SECT_XN | \ |
| 382 | 382 | PMD_SECT_AP_WRITE | \ |
| 383 | 383 | PMD_SECT_AP_READ |
| 384 | − b __v7_ca9mp_setup | |
| 384 | + W(b) __v7_ca9mp_setup | |
| 385 | 385 | .long cpu_arch_name |
| 386 | 386 | .long cpu_elf_name |
| 387 | 387 | .long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP|HWCAP_TLS |
| @@ -413,7 +413,7 @@ __v7_proc_info: · 25 unmodified lines | ||
| 413 | 413 | PMD_SECT_XN | \ |
| 414 | 414 | PMD_SECT_AP_WRITE | \ |
| 415 | 415 | PMD_SECT_AP_READ |
| 416 | − b __v7_setup | |
| 416 | + W(b) __v7_setup | |
| 417 | 417 | .long cpu_arch_name |
| 418 | 418 | .long cpu_elf_name |
| 419 | 419 | .long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP|HWCAP_TLS |
| @@ -18,6 +18,7 @@ · 17 unmodified lines | ||
| 18 | 18 | #include <linux/time.h> |
| 19 | 19 | #include <linux/init.h> |
| 20 | 20 | #include <linux/timex.h> |
| 21 | +#include <linux/sched.h> | |
| 21 | 22 | #include <linux/io.h> |
| 22 | 23 | #include <linux/clocksource.h> |
| 23 | 24 | #include <linux/clockchips.h> |
| @@ -36,7 +37,7 @@ · 12 unmodified lines | ||
| 36 | 37 | /* |
| 37 | 38 | * IOP clocksource (free-running timer 1). |
| 38 | 39 | */ |
| 39 | −static cycle_t iop_clocksource_read(struct clocksource *unused) | |
| 40 | +static cycle_t notrace iop_clocksource_read(struct clocksource *unused) | |
| 40 | 41 | { |
| 41 | 42 | return 0xffffffffu - read_tcr1(); |
| 42 | 43 | } |
| @@ -206,6 +206,7 @@ ENTRY(vfp_save_state) · 205 unmodified lines | ||
| 206 | 206 | mov pc, lr |
| 207 | 207 | ENDPROC(vfp_save_state) |
| 208 | 208 | |
| 209 | + .align | |
| 209 | 210 | last_VFP_context_address: |
| 210 | 211 | .word last_VFP_context |
| 211 | 212 | |
| @@ -70,6 +70,7 @@ void soc_pcmcia_debug(struct soc_pcmcia_socket *skt, const char *func, · 69 unmodified lines | ||
| 70 | 70 | va_end(args); |
| 71 | 71 | } |
| 72 | 72 | } |
| 73 | +EXPORT_SYMBOL(soc_pcmcia_debug); | |
| 73 | 74 | |
| 74 | 75 | #endif |
| 75 | 76 | |