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Merge branch 'drm-radeon-testing' of /ssd/git/drm-radeon-next into drm-next-stage

* 'drm-radeon-testing' of /ssd/git/drm-radeon-next: drm/radeon: r100/r200 ums: block ability for userspace app to trash 0 page and beyond drm/ttm: fix function prototype to match implementation drm/radeon: use ALIGN instead of open coding it drm/radeon/kms: initialize set_surface_reg reg for rs600 asic

Dave Airlie committed 16 years ago

Commit 68de7742 parents cf7934a 566d84d7 files · +15 −4Browse files

Unified · Split

7 files
  1. drivers/gpu/drm/radeon/r600_blit.c +1 −1
  2. drivers/gpu/drm/radeon/r600_blit_kms.c +2 −2
  3. drivers/gpu/drm/radeon/radeon_asic.h +2 −0
  4. drivers/gpu/drm/radeon/radeon_cp.c +1 −0
  5. drivers/gpu/drm/radeon/radeon_drv.h +2 −0
  6. drivers/gpu/drm/radeon/radeon_state.c +6 −0
  7. include/drm/ttm/ttm_bo_driver.h +1 −1
drivers/gpu/drm/radeon/r600_blit.c+1−1
@@ -49,7 +49,7 @@ set_render_target(drm_radeon_private_t *dev_priv, int format, int w, int h, u64 · 48 unmodified lines
49 RING_LOCALS;49 RING_LOCALS;
50 DRM_DEBUG("\n");50 DRM_DEBUG("\n");
51 51
52 h = (h + 7) & ~7;52 h = ALIGN(h, 8);
53 if (h < 8)53 if (h < 8)
54 h = 8;54 h = 8;
55 55
drivers/gpu/drm/radeon/r600_blit_kms.c+2−2
@@ -25,7 +25,7 @@ set_render_target(struct radeon_device *rdev, int format, · 24 unmodified lines
25 u32 cb_color_info;25 u32 cb_color_info;
26 int pitch, slice;26 int pitch, slice;
27 27
28 h = (h + 7) & ~7;28 h = ALIGN(h, 8);
29 if (h < 8)29 if (h < 8)
30 h = 8;30 h = 8;
31 31
@@ -396,7 +396,7 @@ set_default_state(struct radeon_device *rdev) · 364 unmodified lines
396 NUM_ES_STACK_ENTRIES(num_es_stack_entries));396 NUM_ES_STACK_ENTRIES(num_es_stack_entries));
397 397
398 /* emit an IB pointing at default state */398 /* emit an IB pointing at default state */
399 dwords = (rdev->r600_blit.state_len + 0xf) & ~0xf;399 dwords = ALIGN(rdev->r600_blit.state_len, 0x10);
400 gpu_addr = rdev->r600_blit.shader_gpu_addr + rdev->r600_blit.state_offset;400 gpu_addr = rdev->r600_blit.shader_gpu_addr + rdev->r600_blit.state_offset;
401 radeon_ring_write(rdev, PACKET3(PACKET3_INDIRECT_BUFFER, 2));401 radeon_ring_write(rdev, PACKET3(PACKET3_INDIRECT_BUFFER, 2));
402 radeon_ring_write(rdev, gpu_addr & 0xFFFFFFFC);402 radeon_ring_write(rdev, gpu_addr & 0xFFFFFFFC);
drivers/gpu/drm/radeon/radeon_asic.h+2−0
@@ -407,6 +407,8 @@ static struct radeon_asic rs600_asic = { · 406 unmodified lines
407 .get_pcie_lanes = NULL,407 .get_pcie_lanes = NULL,
408 .set_pcie_lanes = NULL,408 .set_pcie_lanes = NULL,
409 .set_clock_gating = &radeon_atom_set_clock_gating,409 .set_clock_gating = &radeon_atom_set_clock_gating,
410 .set_surface_reg = r100_set_surface_reg,
411 .clear_surface_reg = r100_clear_surface_reg,
410 .bandwidth_update = &rs600_bandwidth_update,412 .bandwidth_update = &rs600_bandwidth_update,
411 .hpd_init = &rs600_hpd_init,413 .hpd_init = &rs600_hpd_init,
412 .hpd_fini = &rs600_hpd_fini,414 .hpd_fini = &rs600_hpd_fini,
drivers/gpu/drm/radeon/radeon_cp.c+1−0
@@ -1644,6 +1644,7 @@ static int radeon_do_resume_cp(struct drm_device *dev, struct drm_file *file_pri · 1643 unmodified lines
1644 radeon_cp_load_microcode(dev_priv);1644 radeon_cp_load_microcode(dev_priv);
1645 radeon_cp_init_ring_buffer(dev, dev_priv, file_priv);1645 radeon_cp_init_ring_buffer(dev, dev_priv, file_priv);
1646 1646
1647 dev_priv->have_z_offset = 0;
1647 radeon_do_engine_reset(dev);1648 radeon_do_engine_reset(dev);
1648 radeon_irq_set_state(dev, RADEON_SW_INT_ENABLE, 1);1649 radeon_irq_set_state(dev, RADEON_SW_INT_ENABLE, 1);
1649 1650
drivers/gpu/drm/radeon/radeon_drv.h+2−0
@@ -268,6 +268,8 @@ typedef struct drm_radeon_private { · 267 unmodified lines
268 268
269 u32 scratch_ages[5];269 u32 scratch_ages[5];
270 270
271 int have_z_offset;
272
271 /* starting from here on, data is preserved accross an open */273 /* starting from here on, data is preserved accross an open */
272 uint32_t flags; /* see radeon_chip_flags */274 uint32_t flags; /* see radeon_chip_flags */
273 resource_size_t fb_aper_offset;275 resource_size_t fb_aper_offset;
drivers/gpu/drm/radeon/radeon_state.c+6−0
@@ -105,6 +105,7 @@ static __inline__ int radeon_check_and_fixup_packets(drm_radeon_private_t * · 104 unmodified lines
105 DRM_ERROR("Invalid depth buffer offset\n");105 DRM_ERROR("Invalid depth buffer offset\n");
106 return -EINVAL;106 return -EINVAL;
107 }107 }
108 dev_priv->have_z_offset = 1;
108 break;109 break;
109 110
110 case RADEON_EMIT_PP_CNTL:111 case RADEON_EMIT_PP_CNTL:
@@ -898,6 +899,11 @@ static void radeon_cp_dispatch_clear(struct drm_device * dev, · 787 unmodified lines
898 if (tmp & RADEON_BACK)899 if (tmp & RADEON_BACK)
899 flags |= RADEON_FRONT;900 flags |= RADEON_FRONT;
900 }901 }
902 if (flags & (RADEON_DEPTH|RADEON_STENCIL)) {
903 if (!dev_priv->have_z_offset)
904 printk_once(KERN_ERR "radeon: illegal depth clear request. Buggy mesa detected - please update.\n");
905 flags &= ~(RADEON_DEPTH | RADEON_STENCIL);
906 }
901 907
902 if (flags & (RADEON_FRONT | RADEON_BACK)) {908 if (flags & (RADEON_FRONT | RADEON_BACK)) {
903 909
include/drm/ttm/ttm_bo_driver.h+1−1
@@ -908,7 +908,7 @@ extern int ttm_bo_move_accel_cleanup(struct ttm_buffer_object *bo, · 907 unmodified lines
908 * Utility function that returns the pgprot_t that should be used for908 * Utility function that returns the pgprot_t that should be used for
909 * setting up a PTE with the caching model indicated by @c_state.909 * setting up a PTE with the caching model indicated by @c_state.
910 */910 */
911extern pgprot_t ttm_io_prot(enum ttm_caching_state c_state, pgprot_t tmp);911extern pgprot_t ttm_io_prot(uint32_t caching_flags, pgprot_t tmp);
912 912
913#if (defined(CONFIG_AGP) || (defined(CONFIG_AGP_MODULE) && defined(MODULE)))913#if (defined(CONFIG_AGP) || (defined(CONFIG_AGP_MODULE) && defined(MODULE)))
914#define TTM_HAS_AGP914#define TTM_HAS_AGP