* 'drm-radeon-testing' of /ssd/git/drm-radeon-next: drm/radeon: r100/r200 ums: block ability for userspace app to trash 0 page and beyond drm/ttm: fix function prototype to match implementation drm/radeon: use ALIGN instead of open coding it drm/radeon/kms: initialize set_surface_reg reg for rs600 asic
Unified · Split
| @@ -49,7 +49,7 @@ set_render_target(drm_radeon_private_t *dev_priv, int format, int w, int h, u64 · 48 unmodified lines | ||
| 49 | 49 | RING_LOCALS; |
| 50 | 50 | DRM_DEBUG("\n"); |
| 51 | 51 | |
| 52 | − h = (h + 7) & ~7; | |
| 52 | + h = ALIGN(h, 8); | |
| 53 | 53 | if (h < 8) |
| 54 | 54 | h = 8; |
| 55 | 55 | |
| @@ -25,7 +25,7 @@ set_render_target(struct radeon_device *rdev, int format, · 24 unmodified lines | ||
| 25 | 25 | u32 cb_color_info; |
| 26 | 26 | int pitch, slice; |
| 27 | 27 | |
| 28 | − h = (h + 7) & ~7; | |
| 28 | + h = ALIGN(h, 8); | |
| 29 | 29 | if (h < 8) |
| 30 | 30 | h = 8; |
| 31 | 31 | |
| @@ -396,7 +396,7 @@ set_default_state(struct radeon_device *rdev) · 364 unmodified lines | ||
| 396 | 396 | NUM_ES_STACK_ENTRIES(num_es_stack_entries)); |
| 397 | 397 | |
| 398 | 398 | /* emit an IB pointing at default state */ |
| 399 | − dwords = (rdev->r600_blit.state_len + 0xf) & ~0xf; | |
| 399 | + dwords = ALIGN(rdev->r600_blit.state_len, 0x10); | |
| 400 | 400 | gpu_addr = rdev->r600_blit.shader_gpu_addr + rdev->r600_blit.state_offset; |
| 401 | 401 | radeon_ring_write(rdev, PACKET3(PACKET3_INDIRECT_BUFFER, 2)); |
| 402 | 402 | radeon_ring_write(rdev, gpu_addr & 0xFFFFFFFC); |
| @@ -407,6 +407,8 @@ static struct radeon_asic rs600_asic = { · 406 unmodified lines | ||
| 407 | 407 | .get_pcie_lanes = NULL, |
| 408 | 408 | .set_pcie_lanes = NULL, |
| 409 | 409 | .set_clock_gating = &radeon_atom_set_clock_gating, |
| 410 | + .set_surface_reg = r100_set_surface_reg, | |
| 411 | + .clear_surface_reg = r100_clear_surface_reg, | |
| 410 | 412 | .bandwidth_update = &rs600_bandwidth_update, |
| 411 | 413 | .hpd_init = &rs600_hpd_init, |
| 412 | 414 | .hpd_fini = &rs600_hpd_fini, |
| @@ -1644,6 +1644,7 @@ static int radeon_do_resume_cp(struct drm_device *dev, struct drm_file *file_pri · 1643 unmodified lines | ||
| 1644 | 1644 | radeon_cp_load_microcode(dev_priv); |
| 1645 | 1645 | radeon_cp_init_ring_buffer(dev, dev_priv, file_priv); |
| 1646 | 1646 | |
| 1647 | + dev_priv->have_z_offset = 0; | |
| 1647 | 1648 | radeon_do_engine_reset(dev); |
| 1648 | 1649 | radeon_irq_set_state(dev, RADEON_SW_INT_ENABLE, 1); |
| 1649 | 1650 | |
| @@ -268,6 +268,8 @@ typedef struct drm_radeon_private { · 267 unmodified lines | ||
| 268 | 268 | |
| 269 | 269 | u32 scratch_ages[5]; |
| 270 | 270 | |
| 271 | + int have_z_offset; | |
| 272 | + | |
| 271 | 273 | /* starting from here on, data is preserved accross an open */ |
| 272 | 274 | uint32_t flags; /* see radeon_chip_flags */ |
| 273 | 275 | resource_size_t fb_aper_offset; |
| @@ -105,6 +105,7 @@ static __inline__ int radeon_check_and_fixup_packets(drm_radeon_private_t * · 104 unmodified lines | ||
| 105 | 105 | DRM_ERROR("Invalid depth buffer offset\n"); |
| 106 | 106 | return -EINVAL; |
| 107 | 107 | } |
| 108 | + dev_priv->have_z_offset = 1; | |
| 108 | 109 | break; |
| 109 | 110 | |
| 110 | 111 | case RADEON_EMIT_PP_CNTL: |
| @@ -898,6 +899,11 @@ static void radeon_cp_dispatch_clear(struct drm_device * dev, · 787 unmodified lines | ||
| 898 | 899 | if (tmp & RADEON_BACK) |
| 899 | 900 | flags |= RADEON_FRONT; |
| 900 | 901 | } |
| 902 | + if (flags & (RADEON_DEPTH|RADEON_STENCIL)) { | |
| 903 | + if (!dev_priv->have_z_offset) | |
| 904 | + printk_once(KERN_ERR "radeon: illegal depth clear request. Buggy mesa detected - please update.\n"); | |
| 905 | + flags &= ~(RADEON_DEPTH | RADEON_STENCIL); | |
| 906 | + } | |
| 901 | 907 | |
| 902 | 908 | if (flags & (RADEON_FRONT | RADEON_BACK)) { |
| 903 | 909 | |
| @@ -908,7 +908,7 @@ extern int ttm_bo_move_accel_cleanup(struct ttm_buffer_object *bo, · 907 unmodified lines | ||
| 908 | 908 | * Utility function that returns the pgprot_t that should be used for |
| 909 | 909 | * setting up a PTE with the caching model indicated by @c_state. |
| 910 | 910 | */ |
| 911 | −extern pgprot_t ttm_io_prot(enum ttm_caching_state c_state, pgprot_t tmp); | |
| 911 | +extern pgprot_t ttm_io_prot(uint32_t caching_flags, pgprot_t tmp); | |
| 912 | 912 | |
| 913 | 913 | #if (defined(CONFIG_AGP) || (defined(CONFIG_AGP_MODULE) && defined(MODULE))) |
| 914 | 914 | #define TTM_HAS_AGP |