History

drm/amd/pp: Remove unneeded void * casts for Vega10

Removes unneeded void * casts for the following pointers: hwmgr->backend hwmgr->smu_backend

Rex Zhu committed 8 years ago

Commit 690dc621 parent 25380904 files · +87 −138Browse files

Unified · Split

4 files
  1. drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c +70 −114
  2. drivers/gpu/drm/amd/powerplay/hwmgr/vega10_powertune.c +6 −9
  3. drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c +7 −7
  4. drivers/gpu/drm/amd/powerplay/smumgr/vega10_smumgr.c +4 −8
drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c+70−114
@@ -107,8 +107,7 @@ const struct vega10_power_state *cast_const_phw_vega10_power_state( · 106 unmodified lines
107107
108108 static void vega10_set_default_registry_data(struct pp_hwmgr *hwmgr)
109109 {
110− struct vega10_hwmgr *data =
111− (struct vega10_hwmgr *)(hwmgr->backend);
110+ struct vega10_hwmgr *data = hwmgr->backend;
112111
113112 data->registry_data.sclk_dpm_key_disabled =
114113 hwmgr->feature_mask & PP_SCLK_DPM_MASK ? false : true;
@@ -185,8 +184,7 @@ static void vega10_set_default_registry_data(struct pp_hwmgr *hwmgr) · 70 unmodified lines
185184
186185 static int vega10_set_features_platform_caps(struct pp_hwmgr *hwmgr)
187186 {
188− struct vega10_hwmgr *data =
189− (struct vega10_hwmgr *)(hwmgr->backend);
187+ struct vega10_hwmgr *data = hwmgr->backend;
190188 struct phm_ppt_v2_information *table_info =
191189 (struct phm_ppt_v2_information *)hwmgr->pptable;
192190 struct amdgpu_device *adev = hwmgr->adev;
@@ -296,7 +294,7 @@ static int vega10_set_features_platform_caps(struct pp_hwmgr *hwmgr) · 103 unmodified lines
296294
297295 static void vega10_init_dpm_defaults(struct pp_hwmgr *hwmgr)
298296 {
299− struct vega10_hwmgr *data = (struct vega10_hwmgr *)(hwmgr->backend);
297+ struct vega10_hwmgr *data = hwmgr->backend;
300298 int i;
301299 uint32_t sub_vendor_id, hw_revision;
302300 struct amdgpu_device *adev = hwmgr->adev;
@@ -484,7 +482,7 @@ static int vega10_get_socclk_for_voltage_evv(struct pp_hwmgr *hwmgr, · 181 unmodified lines
484482 */
485483 static int vega10_get_evv_voltages(struct pp_hwmgr *hwmgr)
486484 {
487− struct vega10_hwmgr *data = (struct vega10_hwmgr *)(hwmgr->backend);
485+ struct vega10_hwmgr *data = hwmgr->backend;
488486 uint16_t vv_id;
489487 uint32_t vddc = 0;
490488 uint16_t i, j;
@@ -675,7 +673,7 @@ static int vega10_complete_dependency_tables(struct pp_hwmgr *hwmgr) · 184 unmodified lines
675673 struct phm_ppt_v2_information *table_info =
676674 (struct phm_ppt_v2_information *)(hwmgr->pptable);
677675 #ifdef PPLIB_VEGA10_EVV_SUPPORT
678− struct vega10_hwmgr *data = (struct vega10_hwmgr *)(hwmgr->backend);
676+ struct vega10_hwmgr *data = hwmgr->backend;
679677
680678 tmp_result = vega10_patch_lookup_table_with_leakage(hwmgr,
681679 table_info->vddc_lookup_table, &(data->vddc_leakage));
@@ -878,8 +876,7 @@ static int vega10_hwmgr_backend_init(struct pp_hwmgr *hwmgr) · 196 unmodified lines
878876
879877 static int vega10_init_sclk_threshold(struct pp_hwmgr *hwmgr)
880878 {
881− struct vega10_hwmgr *data =
882− (struct vega10_hwmgr *)(hwmgr->backend);
879+ struct vega10_hwmgr *data = hwmgr->backend;
883880
884881 data->low_sclk_interrupt_threshold = 0;
885882
@@ -888,8 +885,7 @@ static int vega10_init_sclk_threshold(struct pp_hwmgr *hwmgr) · 2 unmodified lines
888885
889886 static int vega10_setup_dpm_led_config(struct pp_hwmgr *hwmgr)
890887 {
891− struct vega10_hwmgr *data =
892− (struct vega10_hwmgr *)(hwmgr->backend);
888+ struct vega10_hwmgr *data = hwmgr->backend;
893889 PPTable_t *pp_table = &(data->smc_state_table.pp_table);
894890
895891 struct pp_atomfwctrl_voltage_table table;
@@ -1092,7 +1088,7 @@ static void vega10_trim_voltage_table_to_fit_state_table( · 196 unmodified lines
10921088 */
10931089 static int vega10_construct_voltage_tables(struct pp_hwmgr *hwmgr)
10941090 {
1095− struct vega10_hwmgr *data = (struct vega10_hwmgr *)(hwmgr->backend);
1091+ struct vega10_hwmgr *data = hwmgr->backend;
10961092 struct phm_ppt_v2_information *table_info =
10971093 (struct phm_ppt_v2_information *)hwmgr->pptable;
10981094 int result;
@@ -1180,8 +1176,7 @@ static void vega10_setup_default_single_dpm_table(struct pp_hwmgr *hwmgr, · 81 unmodified lines
11801176 }
11811177 static int vega10_setup_default_pcie_table(struct pp_hwmgr *hwmgr)
11821178 {
1183− struct vega10_hwmgr *data =
1184− (struct vega10_hwmgr *)(hwmgr->backend);
1179+ struct vega10_hwmgr *data = hwmgr->backend;
11851180 struct vega10_pcie_table *pcie_table = &(data->dpm_table.pcie_table);
11861181 struct phm_ppt_v2_information *table_info =
11871182 (struct phm_ppt_v2_information *)(hwmgr->pptable);
@@ -1230,8 +1225,7 @@ static int vega10_setup_default_pcie_table(struct pp_hwmgr *hwmgr) · 42 unmodified lines
12301225 */
12311226 static int vega10_setup_default_dpm_tables(struct pp_hwmgr *hwmgr)
12321227 {
1233− struct vega10_hwmgr *data =
1234− (struct vega10_hwmgr *)(hwmgr->backend);
1228+ struct vega10_hwmgr *data = hwmgr->backend;
12351229 struct phm_ppt_v2_information *table_info =
12361230 (struct phm_ppt_v2_information *)(hwmgr->pptable);
12371231 struct vega10_single_dpm_table *dpm_table;
@@ -1431,8 +1425,7 @@ static int vega10_setup_default_dpm_tables(struct pp_hwmgr *hwmgr) · 193 unmodified lines
14311425 */
14321426 static int vega10_populate_ulv_state(struct pp_hwmgr *hwmgr)
14331427 {
1434− struct vega10_hwmgr *data =
1435− (struct vega10_hwmgr *)(hwmgr->backend);
1428+ struct vega10_hwmgr *data = hwmgr->backend;
14361429 struct phm_ppt_v2_information *table_info =
14371430 (struct phm_ppt_v2_information *)(hwmgr->pptable);
14381431
@@ -1473,8 +1466,7 @@ static int vega10_populate_single_lclk_level(struct pp_hwmgr *hwmgr, · 34 unmodified lines
14731466 static int vega10_populate_smc_link_levels(struct pp_hwmgr *hwmgr)
14741467 {
14751468 int result = -1;
1476− struct vega10_hwmgr *data =
1477− (struct vega10_hwmgr *)(hwmgr->backend);
1469+ struct vega10_hwmgr *data = hwmgr->backend;
14781470 PPTable_t *pp_table = &(data->smc_state_table.pp_table);
14791471 struct vega10_pcie_table *pcie_table =
14801472 &(data->dpm_table.pcie_table);
@@ -1525,8 +1517,7 @@ static int vega10_populate_single_gfx_level(struct pp_hwmgr *hwmgr, · 44 unmodified lines
15251517 (struct phm_ppt_v2_information *)(hwmgr->pptable);
15261518 struct phm_ppt_v1_clock_voltage_dependency_table *dep_on_sclk =
15271519 table_info->vdd_dep_on_sclk;
1528− struct vega10_hwmgr *data =
1529− (struct vega10_hwmgr *)(hwmgr->backend);
1520+ struct vega10_hwmgr *data = hwmgr->backend;
15301521 struct pp_atomfwctrl_clock_dividers_soc15 dividers;
15311522 uint32_t gfx_max_clock =
15321523 hwmgr->platform_descriptor.overdriveLimit.engineClock;
@@ -1638,8 +1629,7 @@ uint16_t vega10_locate_vddc_given_clock(struct pp_hwmgr *hwmgr, · 105 unmodified lines
16381629 */
16391630 static int vega10_populate_all_graphic_levels(struct pp_hwmgr *hwmgr)
16401631 {
1641− struct vega10_hwmgr *data =
1642− (struct vega10_hwmgr *)(hwmgr->backend);
1632+ struct vega10_hwmgr *data = hwmgr->backend;
16431633 struct phm_ppt_v2_information *table_info =
16441634 (struct phm_ppt_v2_information *)(hwmgr->pptable);
16451635 struct phm_ppt_v1_clock_voltage_dependency_table *dep_table =
@@ -1713,8 +1703,7 @@ static int vega10_populate_single_memory_level(struct pp_hwmgr *hwmgr, · 67 unmodified lines
17131703 uint32_t mem_clock, uint8_t *current_mem_vid,
17141704 PllSetting_t *current_memclk_level, uint8_t *current_mem_soc_vind)
17151705 {
1716− struct vega10_hwmgr *data =
1717− (struct vega10_hwmgr *)(hwmgr->backend);
1706+ struct vega10_hwmgr *data = hwmgr->backend;
17181707 struct phm_ppt_v2_information *table_info =
17191708 (struct phm_ppt_v2_information *)(hwmgr->pptable);
17201709 struct phm_ppt_v1_clock_voltage_dependency_table *dep_on_mclk =
@@ -1772,8 +1761,7 @@ static int vega10_populate_single_memory_level(struct pp_hwmgr *hwmgr, · 51 unmodified lines
17721761 */
17731762 static int vega10_populate_all_memory_levels(struct pp_hwmgr *hwmgr)
17741763 {
1775− struct vega10_hwmgr *data =
1776− (struct vega10_hwmgr *)(hwmgr->backend);
1764+ struct vega10_hwmgr *data = hwmgr->backend;
17771765 PPTable_t *pp_table = &(data->smc_state_table.pp_table);
17781766 struct vega10_single_dpm_table *dpm_table =
17791767 &(data->dpm_table.mem_table);
@@ -1816,8 +1804,7 @@ static int vega10_populate_all_memory_levels(struct pp_hwmgr *hwmgr) · 36 unmodified lines
18161804 static int vega10_populate_single_display_type(struct pp_hwmgr *hwmgr,
18171805 DSPCLK_e disp_clock)
18181806 {
1819− struct vega10_hwmgr *data =
1820− (struct vega10_hwmgr *)(hwmgr->backend);
1807+ struct vega10_hwmgr *data = hwmgr->backend;
18211808 PPTable_t *pp_table = &(data->smc_state_table.pp_table);
18221809 struct phm_ppt_v2_information *table_info =
18231810 (struct phm_ppt_v2_information *)
@@ -1912,8 +1899,7 @@ static int vega10_populate_single_eclock_level(struct pp_hwmgr *hwmgr, · 88 unmodified lines
19121899
19131900 static int vega10_populate_smc_vce_levels(struct pp_hwmgr *hwmgr)
19141901 {
1915− struct vega10_hwmgr *data =
1916− (struct vega10_hwmgr *)(hwmgr->backend);
1902+ struct vega10_hwmgr *data = hwmgr->backend;
19171903 PPTable_t *pp_table = &(data->smc_state_table.pp_table);
19181904 struct vega10_single_dpm_table *dpm_table = &(data->dpm_table.eclk_table);
19191905 int result = -EINVAL;
@@ -1976,8 +1962,7 @@ static int vega10_populate_single_dclock_level(struct pp_hwmgr *hwmgr, · 56 unmodified lines
19761962
19771963 static int vega10_populate_smc_uvd_levels(struct pp_hwmgr *hwmgr)
19781964 {
1979− struct vega10_hwmgr *data =
1980− (struct vega10_hwmgr *)(hwmgr->backend);
1965+ struct vega10_hwmgr *data = hwmgr->backend;
19811966 PPTable_t *pp_table = &(data->smc_state_table.pp_table);
19821967 struct vega10_single_dpm_table *vclk_dpm_table =
19831968 &(data->dpm_table.vclk_table);
@@ -2048,8 +2033,7 @@ static int vega10_populate_smc_uvd_levels(struct pp_hwmgr *hwmgr) · 64 unmodified lines
20482033
20492034 static int vega10_populate_clock_stretcher_table(struct pp_hwmgr *hwmgr)
20502035 {
2051− struct vega10_hwmgr *data =
2052− (struct vega10_hwmgr *)(hwmgr->backend);
2036+ struct vega10_hwmgr *data = hwmgr->backend;
20532037 PPTable_t *pp_table = &(data->smc_state_table.pp_table);
20542038 struct phm_ppt_v2_information *table_info =
20552039 (struct phm_ppt_v2_information *)(hwmgr->pptable);
@@ -2068,8 +2052,7 @@ static int vega10_populate_clock_stretcher_table(struct pp_hwmgr *hwmgr) · 12 unmodified lines
20682052
20692053 static int vega10_populate_avfs_parameters(struct pp_hwmgr *hwmgr)
20702054 {
2071− struct vega10_hwmgr *data =
2072− (struct vega10_hwmgr *)(hwmgr->backend);
2055+ struct vega10_hwmgr *data = hwmgr->backend;
20732056 PPTable_t *pp_table = &(data->smc_state_table.pp_table);
20742057 struct phm_ppt_v2_information *table_info =
20752058 (struct phm_ppt_v2_information *)(hwmgr->pptable);
@@ -2260,8 +2243,7 @@ static int vega10_populate_avfs_parameters(struct pp_hwmgr *hwmgr) · 184 unmodified lines
22602243
22612244 static int vega10_acg_enable(struct pp_hwmgr *hwmgr)
22622245 {
2263− struct vega10_hwmgr *data =
2264− (struct vega10_hwmgr *)(hwmgr->backend);
2246+ struct vega10_hwmgr *data = hwmgr->backend;
22652247 uint32_t agc_btc_response;
22662248
22672249 if (data->smu_features[GNLD_ACG].supported) {
@@ -2293,8 +2275,7 @@ static int vega10_acg_enable(struct pp_hwmgr *hwmgr) · 25 unmodified lines
22932275
22942276 static int vega10_acg_disable(struct pp_hwmgr *hwmgr)
22952277 {
2296− struct vega10_hwmgr *data =
2297− (struct vega10_hwmgr *)(hwmgr->backend);
2278+ struct vega10_hwmgr *data = hwmgr->backend;
22982279
22992280 if (data->smu_features[GNLD_ACG].supported &&
23002281 data->smu_features[GNLD_ACG].enabled)
@@ -2307,8 +2288,7 @@ static int vega10_acg_disable(struct pp_hwmgr *hwmgr) · 6 unmodified lines
23072288
23082289 static int vega10_populate_gpio_parameters(struct pp_hwmgr *hwmgr)
23092290 {
2310− struct vega10_hwmgr *data =
2311− (struct vega10_hwmgr *)(hwmgr->backend);
2291+ struct vega10_hwmgr *data = hwmgr->backend;
23122292 PPTable_t *pp_table = &(data->smc_state_table.pp_table);
23132293 struct pp_atomfwctrl_gpio_parameters gpio_params = {0};
23142294 int result;
@@ -2343,8 +2323,7 @@ static int vega10_populate_gpio_parameters(struct pp_hwmgr *hwmgr) · 28 unmodified lines
23432323
23442324 static int vega10_avfs_enable(struct pp_hwmgr *hwmgr, bool enable)
23452325 {
2346− struct vega10_hwmgr *data =
2347− (struct vega10_hwmgr *)(hwmgr->backend);
2326+ struct vega10_hwmgr *data = hwmgr->backend;
23482327
23492328 if (data->smu_features[GNLD_AVFS].supported) {
23502329 if (enable) {
@@ -2375,7 +2354,7 @@ static int vega10_populate_and_upload_avfs_fuse_override(struct pp_hwmgr *hwmgr) · 24 unmodified lines
23752354 uint32_t top32, bottom32;
23762355 struct phm_fuses_default fuse;
23772356
2378− struct vega10_hwmgr *data = (struct vega10_hwmgr *)(hwmgr->backend);
2357+ struct vega10_hwmgr *data = hwmgr->backend;
23792358 AvfsFuseOverride_t *avfs_fuse_table = &(data->smc_state_table.avfs_fuse_override_table);
23802359
23812360 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_ReadSerialNumTop32);
@@ -2416,8 +2395,7 @@ static int vega10_populate_and_upload_avfs_fuse_override(struct pp_hwmgr *hwmgr) · 34 unmodified lines
24162395 static int vega10_init_smc_table(struct pp_hwmgr *hwmgr)
24172396 {
24182397 int result;
2419− struct vega10_hwmgr *data =
2420− (struct vega10_hwmgr *)(hwmgr->backend);
2398+ struct vega10_hwmgr *data = hwmgr->backend;
24212399 struct phm_ppt_v2_information *table_info =
24222400 (struct phm_ppt_v2_information *)(hwmgr->pptable);
24232401 PPTable_t *pp_table = &(data->smc_state_table.pp_table);
@@ -2555,7 +2533,7 @@ static int vega10_init_smc_table(struct pp_hwmgr *hwmgr) · 131 unmodified lines
25552533
25562534 static int vega10_enable_thermal_protection(struct pp_hwmgr *hwmgr)
25572535 {
2558− struct vega10_hwmgr *data = (struct vega10_hwmgr *)(hwmgr->backend);
2536+ struct vega10_hwmgr *data = hwmgr->backend;
25592537
25602538 if (data->smu_features[GNLD_THERMAL].supported) {
25612539 if (data->smu_features[GNLD_THERMAL].enabled)
@@ -2575,7 +2553,7 @@ static int vega10_enable_thermal_protection(struct pp_hwmgr *hwmgr) · 13 unmodified lines
25752553
25762554 static int vega10_disable_thermal_protection(struct pp_hwmgr *hwmgr)
25772555 {
2578− struct vega10_hwmgr *data = (struct vega10_hwmgr *)(hwmgr->backend);
2556+ struct vega10_hwmgr *data = hwmgr->backend;
25792557
25802558 if (data->smu_features[GNLD_THERMAL].supported) {
25812559 if (!data->smu_features[GNLD_THERMAL].enabled)
@@ -2595,8 +2573,7 @@ static int vega10_disable_thermal_protection(struct pp_hwmgr *hwmgr) · 13 unmodified lines
25952573
25962574 static int vega10_enable_vrhot_feature(struct pp_hwmgr *hwmgr)
25972575 {
2598− struct vega10_hwmgr *data =
2599− (struct vega10_hwmgr *)(hwmgr->backend);
2576+ struct vega10_hwmgr *data = hwmgr->backend;
26002577
26012578 if (PP_CAP(PHM_PlatformCaps_RegulatorHot)) {
26022579 if (data->smu_features[GNLD_VR0HOT].supported) {
@@ -2624,8 +2601,7 @@ static int vega10_enable_vrhot_feature(struct pp_hwmgr *hwmgr) · 21 unmodified lines
26242601
26252602 static int vega10_enable_ulv(struct pp_hwmgr *hwmgr)
26262603 {
2627− struct vega10_hwmgr *data =
2628− (struct vega10_hwmgr *)(hwmgr->backend);
2604+ struct vega10_hwmgr *data = hwmgr->backend;
26292605
26302606 if (data->registry_data.ulv_support) {
26312607 PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,
@@ -2640,8 +2616,7 @@ static int vega10_enable_ulv(struct pp_hwmgr *hwmgr) · 8 unmodified lines
26402616
26412617 static int vega10_disable_ulv(struct pp_hwmgr *hwmgr)
26422618 {
2643− struct vega10_hwmgr *data =
2644− (struct vega10_hwmgr *)(hwmgr->backend);
2619+ struct vega10_hwmgr *data = hwmgr->backend;
26452620
26462621 if (data->registry_data.ulv_support) {
26472622 PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,
@@ -2656,8 +2631,7 @@ static int vega10_disable_ulv(struct pp_hwmgr *hwmgr) · 8 unmodified lines
26562631
26572632 static int vega10_enable_deep_sleep_master_switch(struct pp_hwmgr *hwmgr)
26582633 {
2659− struct vega10_hwmgr *data =
2660− (struct vega10_hwmgr *)(hwmgr->backend);
2634+ struct vega10_hwmgr *data = hwmgr->backend;
26612635
26622636 if (data->smu_features[GNLD_DS_GFXCLK].supported) {
26632637 PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,
@@ -2696,8 +2670,7 @@ static int vega10_enable_deep_sleep_master_switch(struct pp_hwmgr *hwmgr) · 32 unmodified lines
26962670
26972671 static int vega10_disable_deep_sleep_master_switch(struct pp_hwmgr *hwmgr)
26982672 {
2699− struct vega10_hwmgr *data =
2700− (struct vega10_hwmgr *)(hwmgr->backend);
2673+ struct vega10_hwmgr *data = hwmgr->backend;
27012674
27022675 if (data->smu_features[GNLD_DS_GFXCLK].supported) {
27032676 PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,
@@ -2736,8 +2709,7 @@ static int vega10_disable_deep_sleep_master_switch(struct pp_hwmgr *hwmgr) · 32 unmodified lines
27362709
27372710 static int vega10_stop_dpm(struct pp_hwmgr *hwmgr, uint32_t bitmap)
27382711 {
2739− struct vega10_hwmgr *data =
2740− (struct vega10_hwmgr *)(hwmgr->backend);
2712+ struct vega10_hwmgr *data = hwmgr->backend;
27412713 uint32_t i, feature_mask = 0;
27422714
27432715
@@ -2774,8 +2746,7 @@ static int vega10_stop_dpm(struct pp_hwmgr *hwmgr, uint32_t bitmap) · 30 unmodified lines
27742746 */
27752747 static int vega10_start_dpm(struct pp_hwmgr *hwmgr, uint32_t bitmap)
27762748 {
2777− struct vega10_hwmgr *data =
2778− (struct vega10_hwmgr *)(hwmgr->backend);
2749+ struct vega10_hwmgr *data = hwmgr->backend;
27792750 uint32_t i, feature_mask = 0;
27802751
27812752 for (i = 0; i < GNLD_DPM_MAX; i++) {
@@ -2827,8 +2798,7 @@ static int vega10_start_dpm(struct pp_hwmgr *hwmgr, uint32_t bitmap) · 45 unmodified lines
28272798
28282799 static int vega10_enable_disable_PCC_limit_feature(struct pp_hwmgr *hwmgr, bool enable)
28292800 {
2830− struct vega10_hwmgr *data =
2831− (struct vega10_hwmgr *)(hwmgr->backend);
2801+ struct vega10_hwmgr *data = hwmgr->backend;
28322802
28332803 if (data->smu_features[GNLD_PCC_LIMIT].supported) {
28342804 if (enable == data->smu_features[GNLD_PCC_LIMIT].enabled)
@@ -2845,8 +2815,7 @@ static int vega10_enable_disable_PCC_limit_feature(struct pp_hwmgr *hwmgr, bool · 10 unmodified lines
28452815
28462816 static int vega10_enable_dpm_tasks(struct pp_hwmgr *hwmgr)
28472817 {
2848− struct vega10_hwmgr *data =
2849− (struct vega10_hwmgr *)(hwmgr->backend);
2818+ struct vega10_hwmgr *data = hwmgr->backend;
28502819 int tmp_result, result = 0;
28512820
28522821 vega10_enable_disable_PCC_limit_feature(hwmgr, true);
@@ -3063,7 +3032,7 @@ static int vega10_apply_state_adjust_rules(struct pp_hwmgr *hwmgr, · 210 unmodified lines
30633032 struct cgs_display_info info = {0};
30643033 const struct phm_clock_and_voltage_limits *max_limits;
30653034 uint32_t i;
3066− struct vega10_hwmgr *data = (struct vega10_hwmgr *)(hwmgr->backend);
3035+ struct vega10_hwmgr *data = hwmgr->backend;
30673036 struct phm_ppt_v2_information *table_info =
30683037 (struct phm_ppt_v2_information *)(hwmgr->pptable);
30693038 int32_t count;
@@ -3207,8 +3176,7 @@ static int vega10_find_dpm_states_clocks_in_dpm_table(struct pp_hwmgr *hwmgr, co · 137 unmodified lines
32073176 (const struct phm_set_power_state_input *)input;
32083177 const struct vega10_power_state *vega10_ps =
32093178 cast_const_phw_vega10_power_state(states->pnew_state);
3210− struct vega10_hwmgr *data =
3211− (struct vega10_hwmgr *)(hwmgr->backend);
3179+ struct vega10_hwmgr *data = hwmgr->backend;
32123180 struct vega10_single_dpm_table *sclk_table =
32133181 &(data->dpm_table.gfx_table);
32143182 uint32_t sclk = vega10_ps->performance_levels
@@ -3296,8 +3264,7 @@ static int vega10_populate_and_upload_sclk_mclk_dpm_levels( · 81 unmodified lines
32963264 (const struct phm_set_power_state_input *)input;
32973265 const struct vega10_power_state *vega10_ps =
32983266 cast_const_phw_vega10_power_state(states->pnew_state);
3299− struct vega10_hwmgr *data =
3300− (struct vega10_hwmgr *)(hwmgr->backend);
3267+ struct vega10_hwmgr *data = hwmgr->backend;
33013268 uint32_t sclk = vega10_ps->performance_levels
33023269 [vega10_ps->performance_level_count - 1].gfx_clock;
33033270 uint32_t mclk = vega10_ps->performance_levels
@@ -3522,8 +3489,7 @@ static int vega10_trim_single_dpm_states_with_mask(struct pp_hwmgr *hwmgr, · 218 unmodified lines
35223489 static int vega10_trim_dpm_states(struct pp_hwmgr *hwmgr,
35233490 const struct vega10_power_state *vega10_ps)
35243491 {
3525− struct vega10_hwmgr *data =
3526− (struct vega10_hwmgr *)(hwmgr->backend);
3492+ struct vega10_hwmgr *data = hwmgr->backend;
35273493 uint32_t high_limit_count;
35283494
35293495 PP_ASSERT_WITH_CODE((vega10_ps->performance_level_count >= 1),
@@ -3601,8 +3567,7 @@ static int vega10_get_soc_index_for_max_uclk(struct pp_hwmgr *hwmgr) · 71 unmodified lines
36013567
36023568 static int vega10_upload_dpm_bootup_level(struct pp_hwmgr *hwmgr)
36033569 {
3604− struct vega10_hwmgr *data =
3605− (struct vega10_hwmgr *)(hwmgr->backend);
3570+ struct vega10_hwmgr *data = hwmgr->backend;
36063571 uint32_t socclk_idx;
36073572
36083573 vega10_apply_dal_minimum_voltage_request(hwmgr);
@@ -3641,8 +3606,7 @@ static int vega10_upload_dpm_bootup_level(struct pp_hwmgr *hwmgr) · 32 unmodified lines
36413606
36423607 static int vega10_upload_dpm_max_level(struct pp_hwmgr *hwmgr)
36433608 {
3644− struct vega10_hwmgr *data =
3645− (struct vega10_hwmgr *)(hwmgr->backend);
3609+ struct vega10_hwmgr *data = hwmgr->backend;
36463610
36473611 vega10_apply_dal_minimum_voltage_request(hwmgr);
36483612
@@ -3674,8 +3638,7 @@ static int vega10_upload_dpm_max_level(struct pp_hwmgr *hwmgr) · 25 unmodified lines
36743638 static int vega10_generate_dpm_level_enable_mask(
36753639 struct pp_hwmgr *hwmgr, const void *input)
36763640 {
3677− struct vega10_hwmgr *data =
3678− (struct vega10_hwmgr *)(hwmgr->backend);
3641+ struct vega10_hwmgr *data = hwmgr->backend;
36793642 const struct phm_set_power_state_input *states =
36803643 (const struct phm_set_power_state_input *)input;
36813644 const struct vega10_power_state *vega10_ps =
@@ -3713,8 +3676,7 @@ static int vega10_generate_dpm_level_enable_mask( · 31 unmodified lines
37133676
37143677 int vega10_enable_disable_vce_dpm(struct pp_hwmgr *hwmgr, bool enable)
37153678 {
3716− struct vega10_hwmgr *data =
3717− (struct vega10_hwmgr *)(hwmgr->backend);
3679+ struct vega10_hwmgr *data = hwmgr->backend;
37183680
37193681 if (data->smu_features[GNLD_DPM_VCE].supported) {
37203682 PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,
@@ -3730,8 +3692,7 @@ int vega10_enable_disable_vce_dpm(struct pp_hwmgr *hwmgr, bool enable) · 9 unmodified lines
37303692
37313693 static int vega10_update_sclk_threshold(struct pp_hwmgr *hwmgr)
37323694 {
3733− struct vega10_hwmgr *data =
3734− (struct vega10_hwmgr *)(hwmgr->backend);
3695+ struct vega10_hwmgr *data = hwmgr->backend;
37353696 uint32_t low_sclk_interrupt_threshold = 0;
37363697
37373698 if (PP_CAP(PHM_PlatformCaps_SclkThrottleLowNotification) &&
@@ -3755,8 +3716,7 @@ static int vega10_set_power_state_tasks(struct pp_hwmgr *hwmgr, · 17 unmodified lines
37553716 const void *input)
37563717 {
37573718 int tmp_result, result = 0;
3758− struct vega10_hwmgr *data =
3759− (struct vega10_hwmgr *)(hwmgr->backend);
3719+ struct vega10_hwmgr *data = hwmgr->backend;
37603720 PPTable_t *pp_table = &(data->smc_state_table.pp_table);
37613721
37623722 tmp_result = vega10_find_dpm_states_clocks_in_dpm_table(hwmgr, input);
@@ -3852,7 +3812,7 @@ static int vega10_read_sensor(struct pp_hwmgr *hwmgr, int idx, · 89 unmodified lines
38523812 void *value, int *size)
38533813 {
38543814 uint32_t sclk_idx, mclk_idx, activity_percent = 0;
3855− struct vega10_hwmgr *data = (struct vega10_hwmgr *)(hwmgr->backend);
3815+ struct vega10_hwmgr *data = hwmgr->backend;
38563816 struct vega10_dpm_table *dpm_table = &data->dpm_table;
38573817 int ret = 0;
38583818 uint32_t reg, val_vid;
@@ -3990,8 +3950,7 @@ static uint8_t vega10_get_uclk_index(struct pp_hwmgr *hwmgr, · 131 unmodified lines
39903950 static int vega10_notify_smc_display_config_after_ps_adjustment(
39913951 struct pp_hwmgr *hwmgr)
39923952 {
3993− struct vega10_hwmgr *data =
3994− (struct vega10_hwmgr *)(hwmgr->backend);
3953+ struct vega10_hwmgr *data = hwmgr->backend;
39953954 struct vega10_single_dpm_table *dpm_table =
39963955 &data->dpm_table.dcef_table;
39973956 struct phm_ppt_v2_information *table_info =
@@ -4049,8 +4008,7 @@ static int vega10_notify_smc_display_config_after_ps_adjustment( · 51 unmodified lines
40494008
40504009 static int vega10_force_dpm_highest(struct pp_hwmgr *hwmgr)
40514010 {
4052− struct vega10_hwmgr *data =
4053− (struct vega10_hwmgr *)(hwmgr->backend);
4011+ struct vega10_hwmgr *data = hwmgr->backend;
40544012
40554013 data->smc_state_table.gfx_boot_level =
40564014 data->smc_state_table.gfx_max_level =
@@ -4072,8 +4030,7 @@ static int vega10_force_dpm_highest(struct pp_hwmgr *hwmgr) · 15 unmodified lines
40724030
40734031 static int vega10_force_dpm_lowest(struct pp_hwmgr *hwmgr)
40744032 {
4075− struct vega10_hwmgr *data =
4076− (struct vega10_hwmgr *)(hwmgr->backend);
4033+ struct vega10_hwmgr *data = hwmgr->backend;
40774034
40784035 data->smc_state_table.gfx_boot_level =
40794036 data->smc_state_table.gfx_max_level =
@@ -4096,7 +4053,7 @@ static int vega10_force_dpm_lowest(struct pp_hwmgr *hwmgr) · 16 unmodified lines
40964053
40974054 static int vega10_unforce_dpm_levels(struct pp_hwmgr *hwmgr)
40984055 {
4099− struct vega10_hwmgr *data = (struct vega10_hwmgr *)(hwmgr->backend);
4056+ struct vega10_hwmgr *data = hwmgr->backend;
41004057
41014058 data->smc_state_table.gfx_boot_level =
41024059 vega10_find_lowest_dpm_level(&(data->dpm_table.gfx_table));
@@ -4213,7 +4170,7 @@ static int vega10_dpm_force_dpm_level(struct pp_hwmgr *hwmgr, · 110 unmodified lines
42134170
42144171 static uint32_t vega10_get_fan_control_mode(struct pp_hwmgr *hwmgr)
42154172 {
4216− struct vega10_hwmgr *data = (struct vega10_hwmgr *)(hwmgr->backend);
4173+ struct vega10_hwmgr *data = hwmgr->backend;
42174174
42184175 if (data->smu_features[GNLD_FAN_CONTROL].enabled == false)
42194176 return AMD_FAN_CTRL_MANUAL;
@@ -4273,7 +4230,7 @@ static void vega10_get_memclocks(struct pp_hwmgr *hwmgr, · 53 unmodified lines
42734230 (struct phm_ppt_v2_information *)hwmgr->pptable;
42744231 struct phm_ppt_v1_clock_voltage_dependency_table *dep_table =
42754232 table_info->vdd_dep_on_mclk;
4276− struct vega10_hwmgr *data = (struct vega10_hwmgr *)(hwmgr->backend);
4233+ struct vega10_hwmgr *data = hwmgr->backend;
42774234 uint32_t i;
42784235
42794236 clocks->num_levels = 0;
@@ -4397,7 +4354,7 @@ static int vega10_get_clock_by_type_with_voltage(struct pp_hwmgr *hwmgr, · 117 unmodified lines
43974354 static int vega10_set_watermarks_for_clocks_ranges(struct pp_hwmgr *hwmgr,
43984355 struct pp_wm_sets_with_clock_ranges_soc15 *wm_with_clock_ranges)
43994356 {
4400− struct vega10_hwmgr *data = (struct vega10_hwmgr *)(hwmgr->backend);
4357+ struct vega10_hwmgr *data = hwmgr->backend;
44014358 Watermarks_t *table = &(data->smc_state_table.water_marks_table);
44024359 int result = 0;
44034360 uint32_t i;
@@ -4453,7 +4410,7 @@ static int vega10_set_watermarks_for_clocks_ranges(struct pp_hwmgr *hwmgr, · 49 unmodified lines
44534410 static int vega10_force_clock_level(struct pp_hwmgr *hwmgr,
44544411 enum pp_clock_type type, uint32_t mask)
44554412 {
4456− struct vega10_hwmgr *data = (struct vega10_hwmgr *)(hwmgr->backend);
4413+ struct vega10_hwmgr *data = hwmgr->backend;
44574414
44584415 switch (type) {
44594416 case PP_SCLK:
@@ -4494,7 +4451,7 @@ static int vega10_force_clock_level(struct pp_hwmgr *hwmgr, · 34 unmodified lines
44944451 static int vega10_print_clock_levels(struct pp_hwmgr *hwmgr,
44954452 enum pp_clock_type type, char *buf)
44964453 {
4497− struct vega10_hwmgr *data = (struct vega10_hwmgr *)(hwmgr->backend);
4454+ struct vega10_hwmgr *data = hwmgr->backend;
44984455 struct vega10_single_dpm_table *sclk_table = &(data->dpm_table.gfx_table);
44994456 struct vega10_single_dpm_table *mclk_table = &(data->dpm_table.mem_table);
45004457 struct vega10_pcie_table *pcie_table = &(data->dpm_table.pcie_table);
@@ -4544,7 +4501,7 @@ static int vega10_print_clock_levels(struct pp_hwmgr *hwmgr, · 43 unmodified lines
45444501
45454502 static int vega10_display_configuration_changed_task(struct pp_hwmgr *hwmgr)
45464503 {
4547− struct vega10_hwmgr *data = (struct vega10_hwmgr *)(hwmgr->backend);
4504+ struct vega10_hwmgr *data = hwmgr->backend;
45484505 int result = 0;
45494506 uint32_t num_turned_on_displays = 1;
45504507 Watermarks_t *wm_table = &(data->smc_state_table.water_marks_table);
@@ -4569,8 +4526,7 @@ static int vega10_display_configuration_changed_task(struct pp_hwmgr *hwmgr) · 18 unmodified lines
45694526
45704527 int vega10_enable_disable_uvd_dpm(struct pp_hwmgr *hwmgr, bool enable)
45714528 {
4572− struct vega10_hwmgr *data =
4573− (struct vega10_hwmgr *)(hwmgr->backend);
4529+ struct vega10_hwmgr *data = hwmgr->backend;
45744530
45754531 if (data->smu_features[GNLD_DPM_UVD].supported) {
45764532 PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,
@@ -4585,7 +4541,7 @@ int vega10_enable_disable_uvd_dpm(struct pp_hwmgr *hwmgr, bool enable) · 8 unmodified lines
45854541
45864542 static void vega10_power_gate_vce(struct pp_hwmgr *hwmgr, bool bgate)
45874543 {
4588− struct vega10_hwmgr *data = (struct vega10_hwmgr *)(hwmgr->backend);
4544+ struct vega10_hwmgr *data = hwmgr->backend;
45894545
45904546 data->vce_power_gated = bgate;
45914547 vega10_enable_disable_vce_dpm(hwmgr, !bgate);
@@ -4593,7 +4549,7 @@ static void vega10_power_gate_vce(struct pp_hwmgr *hwmgr, bool bgate) · 1 unmodified line
45934549
45944550 static void vega10_power_gate_uvd(struct pp_hwmgr *hwmgr, bool bgate)
45954551 {
4596− struct vega10_hwmgr *data = (struct vega10_hwmgr *)(hwmgr->backend);
4552+ struct vega10_hwmgr *data = hwmgr->backend;
45974553
45984554 data->uvd_power_gated = bgate;
45994555 vega10_enable_disable_uvd_dpm(hwmgr, !bgate);
@@ -4646,7 +4602,7 @@ static int vega10_check_states_equal(struct pp_hwmgr *hwmgr, · 46 unmodified lines
46464602 static bool
46474603 vega10_check_smc_update_required_for_display_configuration(struct pp_hwmgr *hwmgr)
46484604 {
4649− struct vega10_hwmgr *data = (struct vega10_hwmgr *)(hwmgr->backend);
4605+ struct vega10_hwmgr *data = hwmgr->backend;
46504606 bool is_update_required = false;
46514607 struct cgs_display_info info = {0, 0, NULL};
46524608
@@ -4704,7 +4660,7 @@ static int vega10_disable_dpm_tasks(struct pp_hwmgr *hwmgr) · 51 unmodified lines
47044660
47054661 static int vega10_power_off_asic(struct pp_hwmgr *hwmgr)
47064662 {
4707− struct vega10_hwmgr *data = (struct vega10_hwmgr *)(hwmgr->backend);
4663+ struct vega10_hwmgr *data = hwmgr->backend;
47084664 int result;
47094665
47104666 result = vega10_disable_dpm_tasks(hwmgr);
@@ -4718,7 +4674,7 @@ static int vega10_power_off_asic(struct pp_hwmgr *hwmgr) · 7 unmodified lines
47184674
47194675 static int vega10_get_sclk_od(struct pp_hwmgr *hwmgr)
47204676 {
4721− struct vega10_hwmgr *data = (struct vega10_hwmgr *)(hwmgr->backend);
4677+ struct vega10_hwmgr *data = hwmgr->backend;
47224678 struct vega10_single_dpm_table *sclk_table = &(data->dpm_table.gfx_table);
47234679 struct vega10_single_dpm_table *golden_sclk_table =
47244680 &(data->golden_dpm_table.gfx_table);
@@ -4736,7 +4692,7 @@ static int vega10_get_sclk_od(struct pp_hwmgr *hwmgr) · 11 unmodified lines
47364692
47374693 static int vega10_set_sclk_od(struct pp_hwmgr *hwmgr, uint32_t value)
47384694 {
4739− struct vega10_hwmgr *data = (struct vega10_hwmgr *)(hwmgr->backend);
4695+ struct vega10_hwmgr *data = hwmgr->backend;
47404696 struct vega10_single_dpm_table *golden_sclk_table =
47414697 &(data->golden_dpm_table.gfx_table);
47424698 struct pp_power_state *ps;
@@ -4769,7 +4725,7 @@ static int vega10_set_sclk_od(struct pp_hwmgr *hwmgr, uint32_t value) · 26 unmodified lines
47694725
47704726 static int vega10_get_mclk_od(struct pp_hwmgr *hwmgr)
47714727 {
4772− struct vega10_hwmgr *data = (struct vega10_hwmgr *)(hwmgr->backend);
4728+ struct vega10_hwmgr *data = hwmgr->backend;
47734729 struct vega10_single_dpm_table *mclk_table = &(data->dpm_table.mem_table);
47744730 struct vega10_single_dpm_table *golden_mclk_table =
47754731 &(data->golden_dpm_table.mem_table);
@@ -4788,7 +4744,7 @@ static int vega10_get_mclk_od(struct pp_hwmgr *hwmgr) · 12 unmodified lines
47884744
47894745 static int vega10_set_mclk_od(struct pp_hwmgr *hwmgr, uint32_t value)
47904746 {
4791− struct vega10_hwmgr *data = (struct vega10_hwmgr *)(hwmgr->backend);
4747+ struct vega10_hwmgr *data = hwmgr->backend;
47924748 struct vega10_single_dpm_table *golden_mclk_table =
47934749 &(data->golden_dpm_table.mem_table);
47944750 struct pp_power_state *ps;
@@ -4894,7 +4850,7 @@ static int vega10_register_thermal_interrupt(struct pp_hwmgr *hwmgr, · 99 unmodified lines
48944850
48954851 static int vega10_get_power_profile_mode(struct pp_hwmgr *hwmgr, char *buf)
48964852 {
4897− struct vega10_hwmgr *data = (struct vega10_hwmgr *)(hwmgr->backend);
4853+ struct vega10_hwmgr *data = hwmgr->backend;
48984854 uint32_t i, size = 0;
48994855 static const uint8_t profile_mode_setting[5][4] = {{70, 60, 1, 3,},
49004856 {90, 60, 0, 0,},
@@ -4935,7 +4891,7 @@ static int vega10_get_power_profile_mode(struct pp_hwmgr *hwmgr, char *buf) · 34 unmodified lines
49354891
49364892 static int vega10_set_power_profile_mode(struct pp_hwmgr *hwmgr, long *input, uint32_t size)
49374893 {
4938− struct vega10_hwmgr *data = (struct vega10_hwmgr *)(hwmgr->backend);
4894+ struct vega10_hwmgr *data = hwmgr->backend;
49394895 uint8_t busy_set_point;
49404896 uint8_t FPS;
49414897 uint8_t use_rlc_busy;
drivers/gpu/drm/amd/powerplay/hwmgr/vega10_powertune.c+6−9
@@ -1193,7 +1193,7 @@ static int vega10_disable_se_edc_force_stall_config(struct pp_hwmgr *hwmgr) · 1192 unmodified lines
11931193 int vega10_enable_didt_config(struct pp_hwmgr *hwmgr)
11941194 {
11951195 int result = 0;
1196− struct vega10_hwmgr *data = (struct vega10_hwmgr *)(hwmgr->backend);
1196+ struct vega10_hwmgr *data = hwmgr->backend;
11971197
11981198 if (data->smu_features[GNLD_DIDT].supported) {
11991199 if (data->smu_features[GNLD_DIDT].enabled)
@@ -1240,7 +1240,7 @@ int vega10_enable_didt_config(struct pp_hwmgr *hwmgr) · 40 unmodified lines
12401240 int vega10_disable_didt_config(struct pp_hwmgr *hwmgr)
12411241 {
12421242 int result = 0;
1243− struct vega10_hwmgr *data = (struct vega10_hwmgr *)(hwmgr->backend);
1243+ struct vega10_hwmgr *data = hwmgr->backend;
12441244
12451245 if (data->smu_features[GNLD_DIDT].supported) {
12461246 if (!data->smu_features[GNLD_DIDT].enabled)
@@ -1286,7 +1286,7 @@ int vega10_disable_didt_config(struct pp_hwmgr *hwmgr) · 39 unmodified lines
12861286
12871287 void vega10_initialize_power_tune_defaults(struct pp_hwmgr *hwmgr)
12881288 {
1289− struct vega10_hwmgr *data = (struct vega10_hwmgr *)(hwmgr->backend);
1289+ struct vega10_hwmgr *data = hwmgr->backend;
12901290 struct phm_ppt_v2_information *table_info =
12911291 (struct phm_ppt_v2_information *)(hwmgr->pptable);
12921292 struct phm_tdp_table *tdp_table = table_info->tdp_table;
@@ -1325,8 +1325,7 @@ void vega10_initialize_power_tune_defaults(struct pp_hwmgr *hwmgr) · 32 unmodified lines
13251325
13261326 int vega10_set_power_limit(struct pp_hwmgr *hwmgr, uint32_t n)
13271327 {
1328− struct vega10_hwmgr *data =
1329− (struct vega10_hwmgr *)(hwmgr->backend);
1328+ struct vega10_hwmgr *data = hwmgr->backend;
13301329
13311330 if (data->registry_data.enable_pkg_pwr_tracking_feature)
13321331 smum_send_msg_to_smc_with_parameter(hwmgr,
@@ -1337,8 +1336,7 @@ int vega10_set_power_limit(struct pp_hwmgr *hwmgr, uint32_t n) · 4 unmodified lines
13371336
13381337 int vega10_enable_power_containment(struct pp_hwmgr *hwmgr)
13391338 {
1340− struct vega10_hwmgr *data =
1341− (struct vega10_hwmgr *)(hwmgr->backend);
1339+ struct vega10_hwmgr *data = hwmgr->backend;
13421340 struct phm_ppt_v2_information *table_info =
13431341 (struct phm_ppt_v2_information *)(hwmgr->pptable);
13441342 struct phm_tdp_table *tdp_table = table_info->tdp_table;
@@ -1371,8 +1369,7 @@ int vega10_enable_power_containment(struct pp_hwmgr *hwmgr) · 26 unmodified lines
13711369
13721370 int vega10_disable_power_containment(struct pp_hwmgr *hwmgr)
13731371 {
1374− struct vega10_hwmgr *data =
1375− (struct vega10_hwmgr *)(hwmgr->backend);
1372+ struct vega10_hwmgr *data = hwmgr->backend;
13761373
13771374 if (PP_CAP(PHM_PlatformCaps_PowerContainment)) {
13781375 if (data->smu_features[GNLD_PPT].supported)
drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c+7−7
@@ -89,7 +89,7 @@ int vega10_fan_ctrl_get_fan_speed_percent(struct pp_hwmgr *hwmgr, · 88 unmodified lines
8989
9090 int vega10_fan_ctrl_get_fan_speed_rpm(struct pp_hwmgr *hwmgr, uint32_t *speed)
9191 {
92− struct vega10_hwmgr *data = (struct vega10_hwmgr *)(hwmgr->backend);
92+ struct vega10_hwmgr *data = hwmgr->backend;
9393 uint32_t tach_period;
9494 uint32_t crystal_clock_freq;
9595 int result = 0;
@@ -188,7 +188,7 @@ int vega10_fan_ctrl_set_default_mode(struct pp_hwmgr *hwmgr) · 92 unmodified lines
188188 */
189189 static int vega10_enable_fan_control_feature(struct pp_hwmgr *hwmgr)
190190 {
191− struct vega10_hwmgr *data = (struct vega10_hwmgr *)(hwmgr->backend);
191+ struct vega10_hwmgr *data = hwmgr->backend;
192192
193193 if (data->smu_features[GNLD_FAN_CONTROL].supported) {
194194 PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(
@@ -205,7 +205,7 @@ static int vega10_enable_fan_control_feature(struct pp_hwmgr *hwmgr) · 10 unmodified lines
205205
206206 static int vega10_disable_fan_control_feature(struct pp_hwmgr *hwmgr)
207207 {
208− struct vega10_hwmgr *data = (struct vega10_hwmgr *)(hwmgr->backend);
208+ struct vega10_hwmgr *data = hwmgr->backend;
209209
210210 if (data->smu_features[GNLD_FAN_CONTROL].supported) {
211211 PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(
@@ -235,7 +235,7 @@ int vega10_fan_ctrl_start_smc_fan_control(struct pp_hwmgr *hwmgr) · 23 unmodified lines
235235
236236 int vega10_fan_ctrl_stop_smc_fan_control(struct pp_hwmgr *hwmgr)
237237 {
238− struct vega10_hwmgr *data = (struct vega10_hwmgr *)(hwmgr->backend);
238+ struct vega10_hwmgr *data = hwmgr->backend;
239239
240240 if (hwmgr->thermal_controller.fanInfo.bNoFan)
241241 return -1;
@@ -445,7 +445,7 @@ static int vega10_thermal_initialize(struct pp_hwmgr *hwmgr) · 203 unmodified lines
445445 */
446446 static int vega10_thermal_enable_alert(struct pp_hwmgr *hwmgr)
447447 {
448− struct vega10_hwmgr *data = (struct vega10_hwmgr *)(hwmgr->backend);
448+ struct vega10_hwmgr *data = hwmgr->backend;
449449 uint32_t val = 0;
450450 uint32_t reg;
451451
@@ -477,7 +477,7 @@ static int vega10_thermal_enable_alert(struct pp_hwmgr *hwmgr) · 25 unmodified lines
477477 */
478478 int vega10_thermal_disable_alert(struct pp_hwmgr *hwmgr)
479479 {
480− struct vega10_hwmgr *data = (struct vega10_hwmgr *)(hwmgr->backend);
480+ struct vega10_hwmgr *data = hwmgr->backend;
481481 uint32_t reg;
482482
483483 if (data->smu_features[GNLD_FW_CTF].supported) {
@@ -526,7 +526,7 @@ int vega10_thermal_stop_thermal_controller(struct pp_hwmgr *hwmgr) · 42 unmodified lines
526526 int vega10_thermal_setup_fan_table(struct pp_hwmgr *hwmgr)
527527 {
528528 int ret;
529− struct vega10_hwmgr *data = (struct vega10_hwmgr *)(hwmgr->backend);
529+ struct vega10_hwmgr *data = hwmgr->backend;
530530 PPTable_t *table = &(data->smc_state_table.pp_table);
531531
532532 if (!data->smu_features[GNLD_FAN_CONTROL].supported)
drivers/gpu/drm/amd/powerplay/smumgr/vega10_smumgr.c+4−8
@@ -185,8 +185,7 @@ static int vega10_get_argument(struct pp_hwmgr *hwmgr) · 184 unmodified lines
185185 static int vega10_copy_table_from_smc(struct pp_hwmgr *hwmgr,
186186 uint8_t *table, int16_t table_id)
187187 {
188− struct vega10_smumgr *priv =
189− (struct vega10_smumgr *)(hwmgr->smu_backend);
188+ struct vega10_smumgr *priv = hwmgr->smu_backend;
190189
191190 PP_ASSERT_WITH_CODE(table_id < MAX_SMU_TABLE,
192191 "Invalid SMU Table ID!", return -EINVAL);
@@ -213,8 +212,7 @@ static int vega10_copy_table_from_smc(struct pp_hwmgr *hwmgr, · 20 unmodified lines
213212 static int vega10_copy_table_to_smc(struct pp_hwmgr *hwmgr,
214213 uint8_t *table, int16_t table_id)
215214 {
216− struct vega10_smumgr *priv =
217− (struct vega10_smumgr *)(hwmgr->smu_backend);
215+ struct vega10_smumgr *priv = hwmgr->smu_backend;
218216
219217 PP_ASSERT_WITH_CODE(table_id < MAX_SMU_TABLE,
220218 "Invalid SMU Table ID!", return -EINVAL);
@@ -265,8 +263,7 @@ static bool vega10_is_dpm_running(struct pp_hwmgr *hwmgr) · 44 unmodified lines
265263
266264 static int vega10_set_tools_address(struct pp_hwmgr *hwmgr)
267265 {
268− struct vega10_smumgr *priv =
269− (struct vega10_smumgr *)(hwmgr->smu_backend);
266+ struct vega10_smumgr *priv = hwmgr->smu_backend;
270267
271268 if (priv->smu_tables.entry[TOOLSTABLE].mc_addr) {
272269 vega10_send_msg_to_smc_with_parameter(hwmgr,
@@ -435,8 +432,7 @@ free_backend: · 162 unmodified lines
435432
436433 static int vega10_smu_fini(struct pp_hwmgr *hwmgr)
437434 {
438− struct vega10_smumgr *priv =
439− (struct vega10_smumgr *)(hwmgr->smu_backend);
435+ struct vega10_smumgr *priv = hwmgr->smu_backend;
440436
441437 if (priv) {
442438 amdgpu_bo_free_kernel(&priv->smu_tables.entry[PPTABLE].handle,

Keyboard shortcuts

General

Show keyboard shortcuts
?
Focus the current search
/

Issues and pull requests

Open filters
f

Issues, pull requests and Inbox

Select next item
j↓
Select previous item
k↑
Open selected item
Enter
Dismiss filters or clear selection
Esc

Repository code

Go to file
t