Pull dmaengine updates from Vinod Koul: "The last dmaengine updates for this year :) This contains couple of new drivers, new device support and updates to bunch of drivers. New drivers/devices: - Qualcomm ADM driver - Qualcomm GPI driver - Allwinner A100 DMA support - Microchip Sama7g5 support - Mediatek MT8516 apdma Updates: - more updates to idxd driver and support for IAX config - runtime PM support for dw driver - TI drivers" * tag 'dmaengine-5.11-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/vkoul/dmaengine: (75 commits) soc: ti: k3-ringacc: Use correct error casting in k3_ringacc_dmarings_init dmaengine: ti: k3-udma-glue: Add support for K3 PKTDMA dmaengine: ti: k3-udma: Initial support for K3 PKTDMA dmaengine: ti: k3-udma: Add support for BCDMA channel TPL handling dmaengine: ti: k3-udma: Initial support for K3 BCDMA soc: ti: k3-ringacc: add AM64 DMA rings support. dmaengine: ti: Add support for k3 event routers dmaengine: ti: k3-psil: Add initial map for AM64 dmaengine: ti: k3-psil: Extend psil_endpoint_config for K3 PKTDMA dt-bindings: dma: ti: Add document for K3 PKTDMA dt-bindings: dma: ti: Add document for K3 BCDMA dmaengine: dmatest: Use dmaengine_get_dma_device dmaengine: doc: client: Update for dmaengine_get_dma_device() usage dmaengine: Add support for per channel coherency handling dmaengine: of-dma: Add support for optional router configuration callback dmaengine: ti: k3-udma-glue: Configure the dma_dev for rings dmaengine: ti: k3-udma-glue: Get the ringacc from udma_dev dmaengine: ti: k3-udma-glue: Add function to get device pointer for DMA API dmaengine: ti: k3-udma: Add support for second resource range from sysfw dmaengine: ti: k3-udma: Wait for peer teardown completion if supported ...
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| @@ -26,6 +26,9 @@ · 25 unmodified lines | |||
| 26 | #define IDXD_OP_FLAG_DRDBK 0x4000 | 26 | #define IDXD_OP_FLAG_DRDBK 0x4000 |
| 27 | #define IDXD_OP_FLAG_DSTS 0x8000 | 27 | #define IDXD_OP_FLAG_DSTS 0x8000 |
| 28 | 28 | ||
| 29 | /* IAX */ | ||
| 30 | #define IDXD_OP_FLAG_RD_SRC2_AECS 0x010000 | ||
| 31 | |||
| 29 | /* Opcode */ | 32 | /* Opcode */ |
| 30 | enum dsa_opcode { | 33 | enum dsa_opcode { |
| 31 | DSA_OPCODE_NOOP = 0, | 34 | DSA_OPCODE_NOOP = 0, |
| @@ -47,6 +50,14 @@ enum dsa_opcode { · 15 unmodified lines | |||
| 47 | DSA_OPCODE_CFLUSH = 0x20, | 50 | DSA_OPCODE_CFLUSH = 0x20, |
| 48 | }; | 51 | }; |
| 49 | 52 | ||
| 53 | enum iax_opcode { | ||
| 54 | IAX_OPCODE_NOOP = 0, | ||
| 55 | IAX_OPCODE_DRAIN = 2, | ||
| 56 | IAX_OPCODE_MEMMOVE, | ||
| 57 | IAX_OPCODE_DECOMPRESS = 0x42, | ||
| 58 | IAX_OPCODE_COMPRESS, | ||
| 59 | }; | ||
| 60 | |||
| 50 | /* Completion record status */ | 61 | /* Completion record status */ |
| 51 | enum dsa_completion_status { | 62 | enum dsa_completion_status { |
| 52 | DSA_COMP_NONE = 0, | 63 | DSA_COMP_NONE = 0, |
| @@ -80,6 +91,33 @@ enum dsa_completion_status { · 27 unmodified lines | |||
| 80 | DSA_COMP_TRANSLATION_FAIL, | 91 | DSA_COMP_TRANSLATION_FAIL, |
| 81 | }; | 92 | }; |
| 82 | 93 | ||
| 94 | enum iax_completion_status { | ||
| 95 | IAX_COMP_NONE = 0, | ||
| 96 | IAX_COMP_SUCCESS, | ||
| 97 | IAX_COMP_PAGE_FAULT_IR = 0x04, | ||
| 98 | IAX_COMP_OUTBUF_OVERFLOW, | ||
| 99 | IAX_COMP_BAD_OPCODE = 0x10, | ||
| 100 | IAX_COMP_INVALID_FLAGS, | ||
| 101 | IAX_COMP_NOZERO_RESERVE, | ||
| 102 | IAX_COMP_INVALID_SIZE, | ||
| 103 | IAX_COMP_OVERLAP_BUFFERS = 0x16, | ||
| 104 | IAX_COMP_INT_HANDLE_INVAL = 0x19, | ||
| 105 | IAX_COMP_CRA_XLAT, | ||
| 106 | IAX_COMP_CRA_ALIGN, | ||
| 107 | IAX_COMP_ADDR_ALIGN, | ||
| 108 | IAX_COMP_PRIV_BAD, | ||
| 109 | IAX_COMP_TRAFFIC_CLASS_CONF, | ||
| 110 | IAX_COMP_PFAULT_RDBA, | ||
| 111 | IAX_COMP_HW_ERR1, | ||
| 112 | IAX_COMP_HW_ERR_DRB, | ||
| 113 | IAX_COMP_TRANSLATION_FAIL, | ||
| 114 | IAX_COMP_PRS_TIMEOUT, | ||
| 115 | IAX_COMP_WATCHDOG, | ||
| 116 | IAX_COMP_INVALID_COMP_FLAG = 0x30, | ||
| 117 | IAX_COMP_INVALID_FILTER_FLAG, | ||
| 118 | IAX_COMP_INVALID_NUM_ELEMS = 0x33, | ||
| 119 | }; | ||
| 120 | |||
| 83 | #define DSA_COMP_STATUS_MASK 0x7f | 121 | #define DSA_COMP_STATUS_MASK 0x7f |
| 84 | #define DSA_COMP_STATUS_WRITE 0x80 | 122 | #define DSA_COMP_STATUS_WRITE 0x80 |
| 85 | 123 | ||
| @@ -163,6 +201,28 @@ struct dsa_hw_desc { · 77 unmodified lines | |||
| 163 | }; | 201 | }; |
| 164 | } __attribute__((packed)); | 202 | } __attribute__((packed)); |
| 165 | 203 | ||
| 204 | struct iax_hw_desc { | ||
| 205 | uint32_t pasid:20; | ||
| 206 | uint32_t rsvd:11; | ||
| 207 | uint32_t priv:1; | ||
| 208 | uint32_t flags:24; | ||
| 209 | uint32_t opcode:8; | ||
| 210 | uint64_t completion_addr; | ||
| 211 | uint64_t src1_addr; | ||
| 212 | uint64_t dst_addr; | ||
| 213 | uint32_t src1_size; | ||
| 214 | uint16_t int_handle; | ||
| 215 | union { | ||
| 216 | uint16_t compr_flags; | ||
| 217 | uint16_t decompr_flags; | ||
| 218 | }; | ||
| 219 | uint64_t src2_addr; | ||
| 220 | uint32_t max_dst_size; | ||
| 221 | uint32_t src2_size; | ||
| 222 | uint32_t filter_flags; | ||
| 223 | uint32_t num_inputs; | ||
| 224 | } __attribute__((packed)); | ||
| 225 | |||
| 166 | struct dsa_raw_desc { | 226 | struct dsa_raw_desc { |
| 167 | uint64_t field[8]; | 227 | uint64_t field[8]; |
| 168 | } __attribute__((packed)); | 228 | } __attribute__((packed)); |
| @@ -223,4 +283,23 @@ struct dsa_raw_completion_record { · 54 unmodified lines | |||
| 223 | uint64_t field[4]; | 283 | uint64_t field[4]; |
| 224 | } __attribute__((packed)); | 284 | } __attribute__((packed)); |
| 225 | 285 | ||
| 286 | struct iax_completion_record { | ||
| 287 | volatile uint8_t status; | ||
| 288 | uint8_t error_code; | ||
| 289 | uint16_t rsvd; | ||
| 290 | uint32_t bytes_completed; | ||
| 291 | uint64_t fault_addr; | ||
| 292 | uint32_t invalid_flags; | ||
| 293 | uint32_t rsvd2; | ||
| 294 | uint32_t output_size; | ||
| 295 | uint8_t output_bits; | ||
| 296 | uint8_t rsvd3; | ||
| 297 | uint16_t rsvd4; | ||
| 298 | uint64_t rsvd5[4]; | ||
| 299 | } __attribute__((packed)); | ||
| 300 | |||
| 301 | struct iax_raw_completion_record { | ||
| 302 | uint64_t field[8]; | ||
| 303 | } __attribute__((packed)); | ||
| 304 | |||
| 226 | #endif | 305 | #endif |