Merge tag 'drm-misc-next-2021-01-19' of git://anongit.freedesktop.org/drm/drm-misc into drm-next

drm-misc-next for v5.12: UAPI Changes: - Fix fourcc macro for amlogic video fbc. Cross-subsystem Changes: - Export pci_rebar_bytes_to_size. - Add a PCI quirk to increase bar0 for RX 5600 XT Pulse to max possible size. - Convert devicetree bindings to use the OF graph schema. - Update s6e63m0 bindings. - Make omapfb2 DSI_CM incompatible with drm/omap2 DSI-CM because of module conflicts. - Add Zack Rusin as vmwgfx maintainer. - Add CONFIG_DMABUF_DEBUG for validating dma-buf users don't loo kat struct page when importing or detaching. Core Changes: - Remove references to drm_device.pdev - Fix regression in ttm_bo_move_to_lru_tail(). - Assorted docbook updates. - Do not send dp-mst hotplug events on error when probing. - Move some agp macros to agpsupport.c, so it's not always compiled. - Move drm_need_swiotlb.h to drm_cache.c - Only build drm_memory.o for legacy drivers, and move CONFIG_DRM_VM to legacy. - Nuke drm_device.hose - Warn when the ttm resource manager is non-empty when disabling. - Assorted small fixes. Driver Changes: - Small assorted fixes in radeon, v3d, hisilicon, mipi-dbi, panfrost, hibmc, vc4, amdgpu, vkms, vmwgfx. - Move hisilicon to use simple encode. - Add writeback connector to vkms. - Add support for BT2020 to DE3. - Use gem prime mmap helpers in vc4, and move the mmap function upwards. - Use managed drm device, and cleanup error paths and display registers in vmwgfx. - Use correct bus_format and connector_type for innolux_n116bge. - Fix a lot of warnings with W=1 (Lee Jones)

Daniel Vetter committed 5 years ago

Commit 71c46fc2 parents 1777b18 c31eb10229 files · +1500 −2273Browse files

Unified · Split

229 files

Documentation/devicetree/bindings/display/allwinner,sun4i-a10-display-backend.yaml +5 −18
Documentation/devicetree/bindings/display/allwinner,sun4i-a10-display-frontend.yaml +3 −16
Documentation/devicetree/bindings/display/allwinner,sun4i-a10-hdmi.yaml +3 −16
Documentation/devicetree/bindings/display/allwinner,sun4i-a10-tcon.yaml +6 −19
Documentation/devicetree/bindings/display/allwinner,sun4i-a10-tv-encoder.yaml +2 −4
Documentation/devicetree/bindings/display/allwinner,sun6i-a31-drc.yaml +3 −16
Documentation/devicetree/bindings/display/allwinner,sun6i-a31-mipi-dsi.yaml +2 −4
Documentation/devicetree/bindings/display/allwinner,sun8i-a83t-de2-mixer.yaml +3 −16
Documentation/devicetree/bindings/display/allwinner,sun8i-a83t-dw-hdmi.yaml +3 −16
Documentation/devicetree/bindings/display/allwinner,sun8i-r40-tcon-top.yaml +7 −103
Documentation/devicetree/bindings/display/allwinner,sun9i-a80-deu.yaml +3 −16
Documentation/devicetree/bindings/display/amlogic,meson-dw-hdmi.yaml +2 −2
Documentation/devicetree/bindings/display/amlogic,meson-vpu.yaml +2 −2
Documentation/devicetree/bindings/display/brcm,bcm2835-dpi.yaml +3 −4
Documentation/devicetree/bindings/display/bridge/analogix,anx7625.yaml +3 −3
Documentation/devicetree/bindings/display/bridge/analogix,anx7814.yaml +3 −16
Documentation/devicetree/bindings/display/bridge/anx6345.yaml +5 −13
Documentation/devicetree/bindings/display/bridge/cdns,mhdp8546.yaml +6 −16
Documentation/devicetree/bindings/display/bridge/chrontel,ch7033.yaml +3 −3
Documentation/devicetree/bindings/display/bridge/intel,keembay-dsi.yaml +3 −11
Documentation/devicetree/bindings/display/bridge/ite,it6505.yaml +1 −1
Documentation/devicetree/bindings/display/bridge/lontium,lt9611.yaml +7 −63
Documentation/devicetree/bindings/display/bridge/lvds-codec.yaml +4 −14
Documentation/devicetree/bindings/display/bridge/nwl-dsi.yaml +7 −34
Documentation/devicetree/bindings/display/bridge/ps8640.yaml +6 −18
Documentation/devicetree/bindings/display/bridge/renesas,lvds.yaml +3 −15
Documentation/devicetree/bindings/display/bridge/simple-bridge.yaml +4 −14
Documentation/devicetree/bindings/display/bridge/snps,dw-mipi-dsi.yaml +4 −3
Documentation/devicetree/bindings/display/bridge/thine,thc63lvd1024.yaml +5 −16
Documentation/devicetree/bindings/display/bridge/ti,sn65dsi86.yaml +6 −39
Documentation/devicetree/bindings/display/bridge/ti,tfp410.yaml +6 −18
Documentation/devicetree/bindings/display/bridge/toshiba,tc358762.yaml +5 −47
Documentation/devicetree/bindings/display/bridge/toshiba,tc358768.yaml +6 −42
Documentation/devicetree/bindings/display/bridge/toshiba,tc358775.yaml +5 −14
Documentation/devicetree/bindings/display/connector/analog-tv-connector.yaml +1 −0
Documentation/devicetree/bindings/display/connector/dvi-connector.yaml +1 −0
Documentation/devicetree/bindings/display/connector/hdmi-connector.yaml +1 −0
Documentation/devicetree/bindings/display/connector/vga-connector.yaml +1 −0
Documentation/devicetree/bindings/display/imx/nxp,imx8mq-dcss.yaml +1 −1
Documentation/devicetree/bindings/display/ingenic,ipu.yaml +2 −3
Documentation/devicetree/bindings/display/ingenic,lcd.yaml +5 −5
Documentation/devicetree/bindings/display/intel,keembay-display.yaml +1 −1
Documentation/devicetree/bindings/display/panel/advantech,idk-2121wr.yaml +10 −11
Documentation/devicetree/bindings/display/panel/panel-common.yaml +1 −10
Documentation/devicetree/bindings/display/panel/samsung,s6e63m0.yaml +3 −1
Documentation/devicetree/bindings/display/rockchip/rockchip,rk3066-hdmi.yaml +3 −13
Documentation/devicetree/bindings/display/rockchip/rockchip-vop.yaml +1 −4
Documentation/devicetree/bindings/display/st,stm32-dsi.yaml +4 −8
Documentation/devicetree/bindings/display/st,stm32-ltdc.yaml +3 −5
Documentation/devicetree/bindings/display/ste,mcde.yaml +2 −3
Documentation/devicetree/bindings/display/ti/ti,am65x-dss.yaml +4 −15
Documentation/devicetree/bindings/display/ti/ti,j721e-dss.yaml +6 −17
Documentation/devicetree/bindings/display/ti/ti,k2g-dss.yaml +1 −2
Documentation/gpu/vkms.rst +12 −0
MAINTAINERS +1 −0
drivers/dma-buf/Kconfig +8 −0
drivers/dma-buf/dma-buf.c +42 −4
drivers/gpu/drm/Kconfig +0 −5
drivers/gpu/drm/Makefile +3 −3
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +16 −14
drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c +0 −1
drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c +1 −1
drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c +5 −5
drivers/gpu/drm/amd/amdgpu/amdgpu_i2c.c +1 −1
drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c +5 −5
drivers/gpu/drm/ast/ast_drv.c +2 −2
drivers/gpu/drm/ast/ast_main.c +13 −12
drivers/gpu/drm/ast/ast_mm.c +9 −8
drivers/gpu/drm/ast/ast_mode.c +3 −2
drivers/gpu/drm/ast/ast_post.c +5 −3
drivers/gpu/drm/bochs/bochs_drv.c +0 −1
drivers/gpu/drm/bochs/bochs_hw.c +2 −2
drivers/gpu/drm/drm_agpsupport.c +23 −44
drivers/gpu/drm/drm_bufs.c +2 −2
drivers/gpu/drm/drm_cache.c +33 −0
drivers/gpu/drm/drm_dp_helper.c +2 −1
drivers/gpu/drm/drm_dp_mst_topology.c +1 −1
drivers/gpu/drm/drm_drv.c +3 −0
drivers/gpu/drm/drm_edid.c +6 −1
drivers/gpu/drm/drm_file.c +2 −3
drivers/gpu/drm/drm_gem.c +10 −9
drivers/gpu/drm/drm_irq.c +7 −5
drivers/gpu/drm/drm_legacy.h +1 −1
drivers/gpu/drm/drm_memory.c +0 −51
drivers/gpu/drm/drm_modes.c +2 −2
drivers/gpu/drm/drm_pci.c +15 −11
drivers/gpu/drm/drm_prime.c +2 −0
drivers/gpu/drm/drm_vblank.c +1 −1
drivers/gpu/drm/drm_vm.c +1 −1
drivers/gpu/drm/gma500/cdv_device.c +19 −11
drivers/gpu/drm/gma500/cdv_intel_crt.c +2 −3
drivers/gpu/drm/gma500/cdv_intel_display.c +1 −1
drivers/gpu/drm/gma500/cdv_intel_dp.c +2 −2
drivers/gpu/drm/gma500/cdv_intel_lvds.c +6 −5
drivers/gpu/drm/gma500/framebuffer.c +8 −7
drivers/gpu/drm/gma500/gem.c +4 −2
drivers/gpu/drm/gma500/gem.h +2 −0
drivers/gpu/drm/gma500/gma_device.c +3 −1
drivers/gpu/drm/gma500/gma_display.c +6 −6
drivers/gpu/drm/gma500/gtt.c +11 −9
drivers/gpu/drm/gma500/intel_bios.c +4 −4
drivers/gpu/drm/gma500/intel_gmbus.c +2 −2
drivers/gpu/drm/gma500/intel_i2c.c +2 −3
drivers/gpu/drm/gma500/mdfld_device.c +3 −1
drivers/gpu/drm/gma500/mdfld_dsi_dpi.c +4 −4
drivers/gpu/drm/gma500/mdfld_dsi_output.c +2 −2
drivers/gpu/drm/gma500/mdfld_intel_display.c +3 −3
drivers/gpu/drm/gma500/mid_bios.c +6 −3
drivers/gpu/drm/gma500/mmu.c +3 −12
drivers/gpu/drm/gma500/oaktrail_crtc.c +3 −3
drivers/gpu/drm/gma500/oaktrail_device.c +3 −2
drivers/gpu/drm/gma500/oaktrail_lvds.c +3 −2
drivers/gpu/drm/gma500/oaktrail_lvds_i2c.c +5 −5
drivers/gpu/drm/gma500/opregion.c +2 −1
drivers/gpu/drm/gma500/power.c +11 −10
drivers/gpu/drm/gma500/psb_drv.c +8 −8
drivers/gpu/drm/gma500/psb_drv.h +4 −4
drivers/gpu/drm/gma500/psb_intel_display.c +1 −1
drivers/gpu/drm/gma500/psb_intel_lvds.c +4 −3
drivers/gpu/drm/gma500/psb_intel_modes.c +2 −1
drivers/gpu/drm/gma500/psb_intel_sdvo.c +4 −4
drivers/gpu/drm/gma500/psb_irq.c +1 −2
drivers/gpu/drm/gma500/tc35876x-dsi-lvds.c +18 −18
drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_drv.c +6 −7
drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_i2c.c +1 −1
drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_vdac.c +4 −14
drivers/gpu/drm/mga/mga_ioc32.c +7 −7
drivers/gpu/drm/mgag200/mgag200_drv.c +11 −9
drivers/gpu/drm/mgag200/mgag200_i2c.c +1 −1
drivers/gpu/drm/mgag200/mgag200_mm.c +6 −4
drivers/gpu/drm/nouveau/dispnv04/arb.c +7 −5
drivers/gpu/drm/nouveau/dispnv04/dfp.c +3 −2
drivers/gpu/drm/nouveau/dispnv04/disp.h +8 −6
drivers/gpu/drm/nouveau/dispnv04/hw.c +6 −4
drivers/gpu/drm/nouveau/nouveau_abi16.c +4 −3
drivers/gpu/drm/nouveau/nouveau_acpi.c +1 −1
drivers/gpu/drm/nouveau/nouveau_bios.c +8 −3
drivers/gpu/drm/nouveau/nouveau_connector.c +6 −4
drivers/gpu/drm/nouveau/nouveau_drm.c +2 −3
drivers/gpu/drm/nouveau/nouveau_fbcon.c +4 −2
drivers/gpu/drm/nouveau/nouveau_vga.c +12 −8
drivers/gpu/drm/panel/panel-simple.c +2 −0
drivers/gpu/drm/panfrost/panfrost_devfreq.c +1 −0
drivers/gpu/drm/qxl/qxl_drv.c +1 −1
drivers/gpu/drm/qxl/qxl_ioctl.c +2 −1
drivers/gpu/drm/qxl/qxl_irq.c +2 −1
drivers/gpu/drm/qxl/qxl_kms.c +0 −1
drivers/gpu/drm/r128/r128_ioc32.c +7 −7
drivers/gpu/drm/radeon/atombios_encoders.c +3 −3
drivers/gpu/drm/radeon/r100.c +13 −14
drivers/gpu/drm/radeon/radeon.h +19 −16
drivers/gpu/drm/radeon/radeon_atombios.c +45 −44
drivers/gpu/drm/radeon/radeon_bios.c +3 −3
drivers/gpu/drm/radeon/radeon_combios.c +29 −26
drivers/gpu/drm/radeon/radeon_cs.c +1 −2
drivers/gpu/drm/radeon/radeon_device.c +10 −7
drivers/gpu/drm/radeon/radeon_display.c +1 −1
drivers/gpu/drm/radeon/radeon_drv.c +1 −6
drivers/gpu/drm/radeon/radeon_fb.c +1 −1
drivers/gpu/drm/radeon/radeon_gem.c +3 −3
drivers/gpu/drm/radeon/radeon_i2c.c +1 −1
drivers/gpu/drm/radeon/radeon_irq_kms.c +1 −1
drivers/gpu/drm/radeon/radeon_kms.c +14 −10
drivers/gpu/drm/radeon/radeon_legacy_encoders.c +3 −3
drivers/gpu/drm/radeon/radeon_ttm.c +1 −1
drivers/gpu/drm/radeon/rs780_dpm.c +3 −4
drivers/gpu/drm/scheduler/sched_main.c +3 −0
drivers/gpu/drm/sun4i/sun4i_tcon.c +2 −19
drivers/gpu/drm/sun4i/sun4i_tcon.h +1 −0
drivers/gpu/drm/sun4i/sun8i_csc.c +44 −65
drivers/gpu/drm/sun4i/sun8i_mixer.h +2 −4
drivers/gpu/drm/sun4i/sun8i_vi_layer.c +2 −0
drivers/gpu/drm/tiny/cirrus.c +0 −1
drivers/gpu/drm/ttm/ttm_bo.c +3 −1
drivers/gpu/drm/v3d/v3d_drv.c +2 −2
drivers/gpu/drm/v3d/v3d_irq.c +2 −5
drivers/gpu/drm/vboxvideo/vbox_drv.c +6 −5
drivers/gpu/drm/vboxvideo/vbox_irq.c +3 −1
drivers/gpu/drm/vboxvideo/vbox_main.c +6 −2
drivers/gpu/drm/vboxvideo/vbox_ttm.c +4 −3
drivers/gpu/drm/vc4/vc4_bo.c +19 −92
drivers/gpu/drm/vc4/vc4_drv.c +2 −17
drivers/gpu/drm/vc4/vc4_drv.h +0 −8
drivers/gpu/drm/virtio/virtgpu_drv.c +0 −1
drivers/gpu/drm/virtio/virtgpu_gem.c +5 −3
drivers/gpu/drm/virtio/virtgpu_vram.c +1 −0
drivers/gpu/drm/vkms/vkms_drv.c +41 −8
drivers/gpu/drm/vkms/vkms_drv.h +10 −2
drivers/gpu/drm/vkms/vkms_output.c +8 −5
drivers/gpu/drm/vmwgfx/Makefile +3 −3
drivers/gpu/drm/vmwgfx/vmwgfx_binding.c +26 −26
drivers/gpu/drm/vmwgfx/vmwgfx_cmd.c +59 −67
drivers/gpu/drm/vmwgfx/vmwgfx_cmdbuf.c +9 −13
drivers/gpu/drm/vmwgfx/vmwgfx_context.c +20 −20
drivers/gpu/drm/vmwgfx/vmwgfx_cotable.c +6 −6
drivers/gpu/drm/vmwgfx/vmwgfx_drv.c +113 −122
drivers/gpu/drm/vmwgfx/vmwgfx_drv.h +33 −60
drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c +9 −13
drivers/gpu/drm/vmwgfx/vmwgfx_fb.c +6 −6
drivers/gpu/drm/vmwgfx/vmwgfx_fence.c +12 −16
drivers/gpu/drm/vmwgfx/vmwgfx_gmr.c +4 −4
drivers/gpu/drm/vmwgfx/vmwgfx_ioctl.c +7 −8
drivers/gpu/drm/vmwgfx/vmwgfx_irq.c +3 −7
drivers/gpu/drm/vmwgfx/vmwgfx_kms.c +35 −39
drivers/gpu/drm/vmwgfx/vmwgfx_ldu.c +4 −5
drivers/gpu/drm/vmwgfx/vmwgfx_marker.c +0 −155
drivers/gpu/drm/vmwgfx/vmwgfx_mob.c +8 −8
drivers/gpu/drm/vmwgfx/vmwgfx_overlay.c +4 −4
drivers/gpu/drm/vmwgfx/vmwgfx_resource.c +2 −2
drivers/gpu/drm/vmwgfx/vmwgfx_scrn.c +14 −14
drivers/gpu/drm/vmwgfx/vmwgfx_shader.c +12 −12
drivers/gpu/drm/vmwgfx/vmwgfx_so.c +4 −4
drivers/gpu/drm/vmwgfx/vmwgfx_stdu.c +16 −16
drivers/gpu/drm/vmwgfx/vmwgfx_streamoutput.c +4 −4
drivers/gpu/drm/vmwgfx/vmwgfx_surface.c +20 −20
drivers/gpu/drm/vmwgfx/vmwgfx_ttm_buffer.c +3 −3
drivers/pci/pci.c +10 −2
drivers/pci/pci.h +0 −1
drivers/video/fbdev/omap2/omapfb/displays/Kconfig +1 −0
include/drm/drm_agpsupport.h +0 −18
include/drm/drm_crtc.h +1 −1
include/drm/drm_device.h +5 −4
include/drm/drm_mipi_dbi.h +1 −1
include/drm/drm_property.h +1 −1
include/drm/ttm/ttm_resource.h +4 −0
include/linux/dma-buf.h +6 −0
include/linux/pci.h +9 −0
include/linux/vgaarb.h +3 −3
include/uapi/drm/drm_fourcc.h +2 −2

Documentation/devicetree/bindings/display/allwinner,sun4i-a10-display-backend.yaml+5−18

@@ -84,36 +84,23 @@ properties: · 83 unmodified lines
84	84	const: dma-mem
85	85
86	86	ports:
87		− type: object
88		− description: \|
89		− A ports node with endpoint definitions as defined in
90		− Documentation/devicetree/bindings/media/video-interfaces.txt.
	87	+ $ref: /schemas/graph.yaml#/properties/ports
91	88
92	89	properties:
93		− "#address-cells":
94		− const: 1
95		−
96		− "#size-cells":
97		− const: 0
98		−
99	90	port@0:
100		− type: object
101		− description: \|
	91	+ $ref: /schemas/graph.yaml#/properties/port
	92	+ description:
102	93	Input endpoints of the controller.
103	94
104	95	port@1:
105		− type: object
106		− description: \|
	96	+ $ref: /schemas/graph.yaml#/properties/port
	97	+ description:
107	98	Output endpoints of the controller.
108	99
109	100	required:
110		− - "#address-cells"
111		− - "#size-cells"
112	101	- port@0
113	102	- port@1
114	103
115		− additionalProperties: false
116		−
117	104	required:
118	105	- compatible
119	106	- reg

Documentation/devicetree/bindings/display/allwinner,sun4i-a10-display-frontend.yaml+3−16

@@ -57,35 +57,22 @@ properties: · 56 unmodified lines
57	57	maxItems: 1
58	58
59	59	ports:
60		− type: object
61		− description: \|
62		− A ports node with endpoint definitions as defined in
63		− Documentation/devicetree/bindings/media/video-interfaces.txt.
	60	+ $ref: /schemas/graph.yaml#/properties/ports
64	61
65	62	properties:
66		− "#address-cells":
67		− const: 1
68		−
69		− "#size-cells":
70		− const: 0
71		−
72	63	port@0:
73		− type: object
	64	+ $ref: /schemas/graph.yaml#/properties/port
74	65	description: \|
75	66	Input endpoints of the controller.
76	67
77	68	port@1:
78		− type: object
	69	+ $ref: /schemas/graph.yaml#/properties/port
79	70	description: \|
80	71	Output endpoints of the controller.
81	72
82	73	required:
83		− - "#address-cells"
84		− - "#size-cells"
85	74	- port@1
86	75
87		− additionalProperties: false
88		−
89	76	required:
90	77	- compatible
91	78	- reg

Documentation/devicetree/bindings/display/allwinner,sun4i-a10-hdmi.yaml+3−16

@@ -76,37 +76,24 @@ properties: · 75 unmodified lines
76	76	- const: audio-tx
77	77
78	78	ports:
79		− type: object
80		− description: \|
81		− A ports node with endpoint definitions as defined in
82		− Documentation/devicetree/bindings/media/video-interfaces.txt.
	79	+ $ref: /schemas/graph.yaml#/properties/ports
83	80
84	81	properties:
85		− "#address-cells":
86		− const: 1
87		−
88		− "#size-cells":
89		− const: 0
90		−
91	82	port@0:
92		− type: object
	83	+ $ref: /schemas/graph.yaml#/properties/port
93	84	description: \|
94	85	Input endpoints of the controller.
95	86
96	87	port@1:
97		− type: object
	88	+ $ref: /schemas/graph.yaml#/properties/port
98	89	description: \|
99	90	Output endpoints of the controller. Usually an HDMI
100	91	connector.
101	92
102	93	required:
103		− - "#address-cells"
104		− - "#size-cells"
105	94	- port@0
106	95	- port@1
107	96
108		− additionalProperties: false
109		−
110	97	required:
111	98	- compatible
112	99	- reg

Documentation/devicetree/bindings/display/allwinner,sun4i-a10-tcon.yaml+6−19

@@ -115,31 +115,24 @@ properties: · 114 unmodified lines
115	115	- const: lvds
116	116
117	117	ports:
118		− type: object
119		− description: \|
120		− A ports node with endpoint definitions as defined in
121		− Documentation/devicetree/bindings/media/video-interfaces.txt.
	118	+ $ref: /schemas/graph.yaml#/properties/ports
122	119
123	120	properties:
124		− "#address-cells":
125		− const: 1
126		−
127		− "#size-cells":
128		− const: 0
129		−
130	121	port@0:
131		− type: object
	122	+ $ref: /schemas/graph.yaml#/properties/port
132	123	description: \|
133	124	Input endpoints of the controller.
134	125
135	126	port@1:
136		− type: object
	127	+ $ref: /schemas/graph.yaml#/$defs/port-base
	128	+ unevaluatedProperties: false
137	129	description: \|
138	130	Output endpoints of the controller.
139	131
140	132	patternProperties:
141	133	"^endpoint(@[0-9])$":
142		− type: object
	134	+ $ref: /schemas/graph.yaml#/$defs/endpoint-base
	135	+ unevaluatedProperties: false
143	136
144	137	properties:
145	138	allwinner,tcon-channel:
@@ -156,16 +149,10 @@ properties: · 10 unmodified lines
156	149	property is not present, the endpoint number will be
157	150	used as the channel number.
158	151
159		− unevaluatedProperties: true
160		−
161	152	required:
162		− - "#address-cells"
163		− - "#size-cells"
164	153	- port@0
165	154	- port@1
166	155
167		− additionalProperties: false
168		−
169	156	required:
170	157	- compatible
171	158	- reg

Documentation/devicetree/bindings/display/allwinner,sun4i-a10-tv-encoder.yaml+2−4

@@ -24,11 +24,9 @@ properties: · 23 unmodified lines
24	24	maxItems: 1
25	25
26	26	port:
27		− type: object
	27	+ $ref: /schemas/graph.yaml#/properties/port
28	28	description:
29		− A port node with endpoint definitions as defined in
30		− Documentation/devicetree/bindings/media/video-interfaces.txt. The
31		− first port should be the input endpoint, usually coming from the
	29	+ The first port should be the input endpoint, usually coming from the
32	30	associated TCON.
33	31
34	32	required:

Documentation/devicetree/bindings/display/allwinner,sun6i-a31-drc.yaml+3−16

@@ -46,36 +46,23 @@ properties: · 45 unmodified lines
46	46	maxItems: 1
47	47
48	48	ports:
49		− type: object
50		− description: \|
51		− A ports node with endpoint definitions as defined in
52		− Documentation/devicetree/bindings/media/video-interfaces.txt.
	49	+ $ref: /schemas/graph.yaml#/properties/ports
53	50
54	51	properties:
55		− "#address-cells":
56		− const: 1
57		−
58		− "#size-cells":
59		− const: 0
60		−
61	52	port@0:
62		− type: object
	53	+ $ref: /schemas/graph.yaml#/properties/port
63	54	description: \|
64	55	Input endpoints of the controller.
65	56
66	57	port@1:
67		− type: object
	58	+ $ref: /schemas/graph.yaml#/properties/port
68	59	description: \|
69	60	Output endpoints of the controller.
70	61
71	62	required:
72		− - "#address-cells"
73		− - "#size-cells"
74	63	- port@0
75	64	- port@1
76	65
77		− additionalProperties: false
78		−
79	66	required:
80	67	- compatible
81	68	- reg

Documentation/devicetree/bindings/display/allwinner,sun6i-a31-mipi-dsi.yaml+2−4

@@ -47,11 +47,9 @@ properties: · 46 unmodified lines
47	47	const: dphy
48	48
49	49	port:
50		− type: object
	50	+ $ref: /schemas/graph.yaml#/properties/port
51	51	description:
52		− A port node with endpoint definitions as defined in
53		− Documentation/devicetree/bindings/media/video-interfaces.txt. That
54		− port should be the input endpoint, usually coming from the
	52	+ The port should be the input endpoint, usually coming from the
55	53	associated TCON.
56	54
57	55	required:

Documentation/devicetree/bindings/display/allwinner,sun8i-a83t-de2-mixer.yaml+3−16

@@ -43,35 +43,22 @@ properties: · 42 unmodified lines
43	43	maxItems: 1
44	44
45	45	ports:
46		− type: object
47		− description: \|
48		− A ports node with endpoint definitions as defined in
49		− Documentation/devicetree/bindings/media/video-interfaces.txt.
	46	+ $ref: /schemas/graph.yaml#/properties/ports
50	47
51	48	properties:
52		− "#address-cells":
53		− const: 1
54		−
55		− "#size-cells":
56		− const: 0
57		−
58	49	port@0:
59		− type: object
	50	+ $ref: /schemas/graph.yaml#/properties/port
60	51	description: \|
61	52	Input endpoints of the controller.
62	53
63	54	port@1:
64		− type: object
	55	+ $ref: /schemas/graph.yaml#/properties/port
65	56	description: \|
66	57	Output endpoints of the controller.
67	58
68	59	required:
69		− - "#address-cells"
70		− - "#size-cells"
71	60	- port@1
72	61
73		− additionalProperties: false
74		−
75	62	required:
76	63	- compatible
77	64	- reg

Documentation/devicetree/bindings/display/allwinner,sun8i-a83t-dw-hdmi.yaml+3−16

@@ -93,38 +93,25 @@ properties: · 92 unmodified lines
93	93	The VCC power supply of the controller
94	94
95	95	ports:
96		− type: object
97		− description: \|
98		− A ports node with endpoint definitions as defined in
99		− Documentation/devicetree/bindings/media/video-interfaces.txt.
	96	+ $ref: /schemas/graph.yaml#/properties/ports
100	97
101	98	properties:
102		− "#address-cells":
103		− const: 1
104		−
105		− "#size-cells":
106		− const: 0
107		−
108	99	port@0:
109		− type: object
	100	+ $ref: /schemas/graph.yaml#/properties/port
110	101	description: \|
111	102	Input endpoints of the controller. Usually the associated
112	103	TCON.
113	104
114	105	port@1:
115		− type: object
	106	+ $ref: /schemas/graph.yaml#/properties/port
116	107	description: \|
117	108	Output endpoints of the controller. Usually an HDMI
118	109	connector.
119	110
120	111	required:
121		− - "#address-cells"
122		− - "#size-cells"
123	112	- port@0
124	113	- port@1
125	114
126		− additionalProperties: false
127		−
128	115	required:
129	116	- compatible
130	117	- reg

Documentation/devicetree/bindings/display/allwinner,sun8i-r40-tcon-top.yaml+7−103

@@ -80,141 +80,45 @@ properties: · 79 unmodified lines
80	80	maxItems: 1
81	81
82	82	ports:
83		− type: object
84		− description: \|
85		− A ports node with endpoint definitions as defined in
86		− Documentation/devicetree/bindings/media/video-interfaces.txt.
87		− All ports should have only one endpoint connected to
88		− remote endpoint.
	83	+ $ref: /schemas/graph.yaml#/properties/ports
89	84
90	85	properties:
91		− "#address-cells":
92		− const: 1
93		−
94		− "#size-cells":
95		− const: 0
96		−
97	86	port@0:
98		− type: object
	87	+ $ref: /schemas/graph.yaml#/properties/port
99	88	description: \|
100	89	Input endpoint for Mixer 0 mux.
101	90
102	91	port@1:
103		− type: object
	92	+ $ref: /schemas/graph.yaml#/properties/port
104	93	description: \|
105	94	Output endpoint for Mixer 0 mux
106	95
107		− properties:
108		− "#address-cells":
109		− const: 1
110		−
111		− "#size-cells":
112		− const: 0
113		−
114		− reg: true
115		−
116		− patternProperties:
117		− "^endpoint@[0-9]$":
118		− type: object
119		−
120		− properties:
121		− reg:
122		− description: \|
123		− ID of the target TCON
124		−
125		− required:
126		− - reg
127		−
128		− required:
129		− - "#address-cells"
130		− - "#size-cells"
131		−
132		− additionalProperties: false
133		−
134	96	port@2:
135		− type: object
	97	+ $ref: /schemas/graph.yaml#/properties/port
136	98	description: \|
137	99	Input endpoint for Mixer 1 mux.
138	100
139	101	port@3:
140		− type: object
	102	+ $ref: /schemas/graph.yaml#/properties/port
141	103	description: \|
142	104	Output endpoint for Mixer 1 mux
143	105
144		− properties:
145		− "#address-cells":
146		− const: 1
147		−
148		− "#size-cells":
149		− const: 0
150		−
151		− reg: true
152		−
153		− patternProperties:
154		− "^endpoint@[0-9]$":
155		− type: object
156		−
157		− properties:
158		− reg:
159		− description: \|
160		− ID of the target TCON
161		−
162		− required:
163		− - reg
164		−
165		− required:
166		− - "#address-cells"
167		− - "#size-cells"
168		−
169		− additionalProperties: false
170		−
171	106	port@4:
172		− type: object
	107	+ $ref: /schemas/graph.yaml#/properties/port
173	108	description: \|
174	109	Input endpoint for HDMI mux.
175	110
176		− properties:
177		− "#address-cells":
178		− const: 1
179		−
180		− "#size-cells":
181		− const: 0
182		−
183		− reg: true
184		−
185		− patternProperties:
186		− "^endpoint@[0-9]$":
187		− type: object
188		−
189		− properties:
190		− reg:
191		− description: \|
192		− ID of the target TCON
193		−
194		− required:
195		− - reg
196		−
197		− required:
198		− - "#address-cells"
199		− - "#size-cells"
200		−
201		− additionalProperties: false
202		−
203	111	port@5:
204		− type: object
	112	+ $ref: /schemas/graph.yaml#/properties/port
205	113	description: \|
206	114	Output endpoint for HDMI mux
207	115
208	116	required:
209		− - "#address-cells"
210		− - "#size-cells"
211	117	- port@0
212	118	- port@1
213	119	- port@4
214	120	- port@5
215	121
216		− additionalProperties: false
217		−
218	122	required:
219	123	- "#clock-cells"
220	124	- compatible

Documentation/devicetree/bindings/display/allwinner,sun9i-a80-deu.yaml+3−16

@@ -40,36 +40,23 @@ properties: · 39 unmodified lines
40	40	maxItems: 1
41	41
42	42	ports:
43		− type: object
44		− description: \|
45		− A ports node with endpoint definitions as defined in
46		− Documentation/devicetree/bindings/media/video-interfaces.txt.
	43	+ $ref: /schemas/graph.yaml#/properties/ports
47	44
48	45	properties:
49		− "#address-cells":
50		− const: 1
51		−
52		− "#size-cells":
53		− const: 0
54		−
55	46	port@0:
56		− type: object
	47	+ $ref: /schemas/graph.yaml#/properties/port
57	48	description: \|
58	49	Input endpoints of the controller.
59	50
60	51	port@1:
61		− type: object
	52	+ $ref: /schemas/graph.yaml#/properties/port
62	53	description: \|
63	54	Output endpoints of the controller.
64	55
65	56	required:
66		− - "#address-cells"
67		− - "#size-cells"
68	57	- port@0
69	58	- port@1
70	59
71		− additionalProperties: false
72		−
73	60	required:
74	61	- compatible
75	62	- reg

Documentation/devicetree/bindings/display/amlogic,meson-dw-hdmi.yaml+2−2

@@ -81,12 +81,12 @@ properties: · 80 unmodified lines
81	81	description: phandle to an external 5V regulator to power the HDMI logic
82	82
83	83	port@0:
84		− type: object
	84	+ $ref: /schemas/graph.yaml#/properties/port
85	85	description:
86	86	A port node pointing to the VENC Input port node.
87	87
88	88	port@1:
89		− type: object
	89	+ $ref: /schemas/graph.yaml#/properties/port
90	90	description:
91	91	A port node pointing to the TMDS Output port node.
92	92

Documentation/devicetree/bindings/display/amlogic,meson-vpu.yaml+2−2

@@ -83,12 +83,12 @@ properties: · 82 unmodified lines
83	83	description: phandle to the associated power domain
84	84
85	85	port@0:
86		− type: object
	86	+ $ref: /schemas/graph.yaml#/properties/port
87	87	description:
88	88	A port node pointing to the CVBS VDAC port node.
89	89
90	90	port@1:
91		− type: object
	91	+ $ref: /schemas/graph.yaml#/properties/port
92	92	description:
93	93	A port node pointing to the HDMI-TX port node.
94	94

Documentation/devicetree/bindings/display/brcm,bcm2835-dpi.yaml+3−4

@@ -27,10 +27,9 @@ properties: · 26 unmodified lines
27	27	- const: pixel
28	28
29	29	port:
30		− type: object
31		− description: >
32		− Port node with a single endpoint connecting to the panel, as
33		− defined in Documentation/devicetree/bindings/media/video-interfaces.txt.
	30	+ $ref: /schemas/graph.yaml#/properties/port
	31	+ description:
	32	+ Port node with a single endpoint connecting to the panel.
34	33
35	34	required:
36	35	- compatible

Documentation/devicetree/bindings/display/bridge/analogix,anx7625.yaml+3−3

@@ -35,16 +35,16 @@ properties: · 34 unmodified lines
35	35	maxItems: 1
36	36
37	37	ports:
38		− type: object
	38	+ $ref: /schemas/graph.yaml#/properties/ports
39	39
40	40	properties:
41	41	port@0:
42		− type: object
	42	+ $ref: /schemas/graph.yaml#/properties/port
43	43	description:
44	44	Video port for MIPI DSI input.
45	45
46	46	port@1:
47		− type: object
	47	+ $ref: /schemas/graph.yaml#/properties/port
48	48	description:
49	49	Video port for panel or connector.
50	50

Documentation/devicetree/bindings/display/bridge/analogix,anx7814.yaml+3−16

@@ -42,31 +42,18 @@ properties: · 41 unmodified lines
42	42	description: Regulator for 1.0V digital core power.
43	43
44	44	ports:
45		− type: object
46		− description:
47		− A node containing input and output port nodes with endpoint
48		− definitions as documented in
49		− Documentation/devicetree/bindings/media/video-interfaces.txt
50		− Documentation/devicetree/bindings/graph.txt
	45	+ $ref: /schemas/graph.yaml#/properties/ports
51	46
52	47	properties:
53	48	port@0:
54		− type: object
	49	+ $ref: /schemas/graph.yaml#/properties/port
55	50	description: Video port for HDMI input.
56	51
57		− properties:
58		− reg:
59		− const: 0
60		−
61	52	port@1:
62		− type: object
	53	+ $ref: /schemas/graph.yaml#/properties/port
63	54	description:
64	55	Video port for SlimPort, DisplayPort, eDP or MyDP output.
65	56
66		− properties:
67		− reg:
68		− const: 1
69		−
70	57	required:
71	58	- port@0
72	59	- port@1

Documentation/devicetree/bindings/display/bridge/anx6345.yaml+5−13

@@ -32,31 +32,23 @@ properties: · 31 unmodified lines
32	32	description: Regulator for 2.5V digital core power.
33	33
34	34	ports:
35		− type: object
	35	+ $ref: /schemas/graph.yaml#/properties/ports
36	36
37	37	properties:
38		− '#address-cells':
39		− const: 1
40		−
41		− '#size-cells':
42		− const: 0
43		−
44	38	port@0:
45		− type: object
46		− description: \|
	39	+ $ref: /schemas/graph.yaml#/properties/port
	40	+ description:
47	41	Video port for LVTTL input
48	42
49	43	port@1:
50		− type: object
51		− description: \|
	44	+ $ref: /schemas/graph.yaml#/properties/port
	45	+ description:
52	46	Video port for eDP output (panel or connector).
53	47	May be omitted if EDID works reliably.
54	48
55	49	required:
56	50	- port@0
57	51
58		− additionalProperties: false
59		−
60	52	required:
61	53	- compatible
62	54	- reg

Documentation/devicetree/bindings/display/bridge/cdns,mhdp8546.yaml+6−16

@@ -57,47 +57,37 @@ properties: · 56 unmodified lines
57	57	maxItems: 1
58	58
59	59	ports:
60		− type: object
61		− description:
62		− Ports as described in Documentation/devicetree/bindings/graph.txt.
	60	+ $ref: /schemas/graph.yaml#/properties/ports
63	61
64	62	properties:
65		− '#address-cells':
66		− const: 1
67		−
68		− '#size-cells':
69		− const: 0
70		−
71	63	port@0:
72		− type: object
	64	+ $ref: /schemas/graph.yaml#/properties/port
73	65	description:
74	66	First input port representing the DP bridge input.
75	67
76	68	port@1:
77		− type: object
	69	+ $ref: /schemas/graph.yaml#/properties/port
78	70	description:
79	71	Second input port representing the DP bridge input.
80	72
81	73	port@2:
82		− type: object
	74	+ $ref: /schemas/graph.yaml#/properties/port
83	75	description:
84	76	Third input port representing the DP bridge input.
85	77
86	78	port@3:
87		− type: object
	79	+ $ref: /schemas/graph.yaml#/properties/port
88	80	description:
89	81	Fourth input port representing the DP bridge input.
90	82
91	83	port@4:
92		− type: object
	84	+ $ref: /schemas/graph.yaml#/properties/port
93	85	description:
94	86	Output port representing the DP bridge output.
95	87
96	88	required:
97	89	- port@0
98	90	- port@4
99		− - '#address-cells'
100		− - '#size-cells'
101	91
102	92	allOf:
103	93	- if:

Documentation/devicetree/bindings/display/bridge/chrontel,ch7033.yaml+3−3

@@ -19,16 +19,16 @@ properties: · 18 unmodified lines
19	19	description: I2C address of the device
20	20
21	21	ports:
22		− type: object
	22	+ $ref: /schemas/graph.yaml#/properties/ports
23	23
24	24	properties:
25	25	port@0:
26		− type: object
	26	+ $ref: /schemas/graph.yaml#/properties/port
27	27	description: \|
28	28	Video port for RGB input.
29	29
30	30	port@1:
31		− type: object
	31	+ $ref: /schemas/graph.yaml#/properties/port
32	32	description: \|
33	33	DVI port, should be connected to a node compatible with the
34	34	dvi-connector binding.

Documentation/devicetree/bindings/display/bridge/intel,keembay-dsi.yaml+3−11

@@ -35,29 +35,21 @@ properties: · 34 unmodified lines
35	35	- const: clk_mipi_cfg
36	36
37	37	ports:
38		− type: object
	38	+ $ref: /schemas/graph.yaml#/properties/ports
39	39
40	40	properties:
41		− '#address-cells':
42		− const: 1
43		−
44		− '#size-cells':
45		− const: 0
46		−
47	41	port@0:
48		− type: object
	42	+ $ref: /schemas/graph.yaml#/properties/port
49	43	description: MIPI DSI input port.
50	44
51	45	port@1:
52		− type: object
	46	+ $ref: /schemas/graph.yaml#/properties/port
53	47	description: DSI output port.
54	48
55	49	required:
56	50	- port@0
57	51	- port@1
58	52
59		− additionalProperties: false
60		−
61	53	required:
62	54	- compatible
63	55	- reg

Documentation/devicetree/bindings/display/bridge/ite,it6505.yaml+1−1

@@ -53,7 +53,7 @@ properties: · 52 unmodified lines
53	53	description: extcon specifier for the Power Delivery
54	54
55	55	port:
56		− type: object
	56	+ $ref: /schemas/graph.yaml#/properties/port
57	57	description: A port node pointing to DPI host port node
58	58
59	59	required:

Documentation/devicetree/bindings/display/bridge/lontium,lt9611.yaml+7−63

@@ -38,82 +38,26 @@ properties: · 37 unmodified lines
38	38	description: Regulator for 3.3V IO power.
39	39
40	40	ports:
41		− type: object
	41	+ $ref: /schemas/graph.yaml#/properties/ports
42	42
43	43	properties:
44		− "#address-cells":
45		− const: 1
46		−
47		− "#size-cells":
48		− const: 0
49		−
50	44	port@0:
51		− type: object
52		− description: \|
	45	+ $ref: /schemas/graph.yaml#/properties/port
	46	+ description:
53	47	Primary MIPI port-1 for MIPI input
54	48
55		− properties:
56		− reg:
57		− const: 0
58		−
59		− patternProperties:
60		− "^endpoint(@[0-9])$":
61		− type: object
62		− additionalProperties: false
63		−
64		− properties:
65		− remote-endpoint:
66		− $ref: /schemas/types.yaml#/definitions/phandle
67		−
68		− required:
69		− - reg
70		−
71	49	port@1:
72		− type: object
73		− description: \|
	50	+ $ref: /schemas/graph.yaml#/properties/port
	51	+ description:
74	52	Additional MIPI port-2 for MIPI input, used in combination
75	53	with primary MIPI port-1 to drive higher resolution displays
76	54
77		− properties:
78		− reg:
79		− const: 1
80		−
81		− patternProperties:
82		− "^endpoint(@[0-9])$":
83		− type: object
84		− additionalProperties: false
85		−
86		− properties:
87		− remote-endpoint:
88		− $ref: /schemas/types.yaml#/definitions/phandle
89		−
90		− required:
91		− - reg
92		−
93	55	port@2:
94		− type: object
95		− description: \|
	56	+ $ref: /schemas/graph.yaml#/properties/port
	57	+ description:
96	58	HDMI port for HDMI output
97	59
98		− properties:
99		− reg:
100		− const: 2
101		−
102		− patternProperties:
103		− "^endpoint(@[0-9])$":
104		− type: object
105		− additionalProperties: false
106		−
107		− properties:
108		− remote-endpoint:
109		− $ref: /schemas/types.yaml#/definitions/phandle
110		−
111		− required:
112		− - reg
113		−
114	60	required:
115		− - "#address-cells"
116		− - "#size-cells"
117	61	- port@0
118	62	- port@2
119	63

Documentation/devicetree/bindings/display/bridge/lvds-codec.yaml+4−14

@@ -45,25 +45,17 @@ properties: · 44 unmodified lines
45	45	- thine,thc63lvdm83d # For the THC63LVDM83D LVDS serializer
46	46
47	47	ports:
48		− type: object
49		− description: \|
50		− This device has two video ports. Their connections are modeled using the
51		− OF graph bindings specified in Documentation/devicetree/bindings/graph.txt
52		− properties:
53		− '#address-cells':
54		− const: 1
55		−
56		− '#size-cells':
57		− const: 0
	48	+ $ref: /schemas/graph.yaml#/properties/ports
58	49
	50	+ properties:
59	51	port@0:
60		− type: object
	52	+ $ref: /schemas/graph.yaml#/properties/port
61	53	description: \|
62	54	For LVDS encoders, port 0 is the parallel input
63	55	For LVDS decoders, port 0 is the LVDS input
64	56
65	57	port@1:
66		− type: object
	58	+ $ref: /schemas/graph.yaml#/properties/port
67	59	description: \|
68	60	For LVDS encoders, port 1 is the LVDS output
69	61	For LVDS decoders, port 1 is the parallel output
@@ -72,8 +64,6 @@ properties: · 2 unmodified lines
72	64	- port@0
73	65	- port@1
74	66
75		− additionalProperties: false
76		−
77	67	powerdown-gpios:
78	68	description:
79	69	The GPIO used to control the power down line of this device.

Documentation/devicetree/bindings/display/bridge/nwl-dsi.yaml+7−34

@@ -84,40 +84,23 @@ properties: · 83 unmodified lines
84	84	- const: pclk
85	85
86	86	ports:
87		− type: object
88		− description:
89		− A node containing DSI input & output port nodes with endpoint
90		− definitions as documented in
91		− Documentation/devicetree/bindings/graph.txt.
	87	+ $ref: /schemas/graph.yaml#/properties/ports
	88	+
92	89	properties:
93	90	port@0:
94		− type: object
	91	+ $ref: /schemas/graph.yaml#/$defs/port-base
95	92	description:
96	93	Input port node to receive pixel data from the
97	94	display controller. Exactly one endpoint must be
98	95	specified.
99	96	properties:
100		− '#address-cells':
101		− const: 1
102		−
103		− '#size-cells':
104		− const: 0
105		−
106	97	endpoint@0:
	98	+ $ref: /schemas/graph.yaml#/properties/endpoint
107	99	description: sub-node describing the input from LCDIF
108		− type: object
109	100
110	101	endpoint@1:
	102	+ $ref: /schemas/graph.yaml#/properties/endpoint
111	103	description: sub-node describing the input from DCSS
112		− type: object
113		−
114		− reg:
115		− const: 0
116		−
117		− required:
118		− - '#address-cells'
119		− - '#size-cells'
120		− - reg
121	104
122	105	oneOf:
123	106	- required:
@@ -125,28 +108,18 @@ properties: · 1 unmodified line
125	108	- required:
126	109	- endpoint@1
127	110
128		− additionalProperties: false
	111	+ unevaluatedProperties: false
129	112
130	113	port@1:
131		− type: object
	114	+ $ref: /schemas/graph.yaml#/properties/port
132	115	description:
133	116	DSI output port node to the panel or the next bridge
134	117	in the chain
135	118
136		− '#address-cells':
137		− const: 1
138		−
139		− '#size-cells':
140		− const: 0
141		−
142	119	required:
143		− - '#address-cells'
144		− - '#size-cells'
145	120	- port@0
146	121	- port@1
147	122
148		− additionalProperties: false
149		−
150	123	required:
151	124	- '#address-cells'
152	125	- '#size-cells'

Documentation/devicetree/bindings/display/bridge/ps8640.yaml+6−18

@@ -41,34 +41,22 @@ properties: · 40 unmodified lines
41	41	description: Regulator for 3.3V digital core power.
42	42
43	43	ports:
44		− type: object
45		− description:
46		− A node containing DSI input & output port nodes with endpoint
47		− definitions as documented in
48		− Documentation/devicetree/bindings/media/video-interfaces.txt
49		− Documentation/devicetree/bindings/graph.txt
50		− properties:
51		− '#address-cells':
52		− const: 1
53		−
54		− '#size-cells':
55		− const: 0
	44	+ $ref: /schemas/graph.yaml#/properties/ports
56	45
	46	+ properties:
57	47	port@0:
58		− type: object
59		− description: \|
	48	+ $ref: /schemas/graph.yaml#/properties/port
	49	+ description:
60	50	Video port for DSI input
61	51
62	52	port@1:
63		− type: object
64		− description: \|
	53	+ $ref: /schemas/graph.yaml#/properties/port
	54	+ description:
65	55	Video port for eDP output (panel or connector).
66	56
67	57	required:
68	58	- port@0
69	59
70		− additionalProperties: false
71		−
72	60	required:
73	61	- compatible
74	62	- reg

Documentation/devicetree/bindings/display/bridge/renesas,lvds.yaml+3−15

@@ -49,33 +49,21 @@ properties: · 48 unmodified lines
49	49	maxItems: 1
50	50
51	51	ports:
52		− type: object
53		− description: \|
54		− This device has two video ports. Their connections are modelled using the
55		− OF graph bindings specified in Documentation/devicetree/bindings/graph.txt.
56		− Each port shall have a single endpoint.
	52	+ $ref: /schemas/graph.yaml#/properties/ports
57	53
58	54	properties:
59		− '#address-cells':
60		− const: 1
61		−
62		− '#size-cells':
63		− const: 0
64		−
65	55	port@0:
66		− type: object
	56	+ $ref: /schemas/graph.yaml#/properties/port
67	57	description: Parallel RGB input port
68	58
69	59	port@1:
70		− type: object
	60	+ $ref: /schemas/graph.yaml#/properties/port
71	61	description: LVDS output port
72	62
73	63	required:
74	64	- port@0
75	65	- port@1
76	66
77		− additionalProperties: false
78		−
79	67	power-domains:
80	68	maxItems: 1
81	69

Documentation/devicetree/bindings/display/bridge/simple-bridge.yaml+4−14

@@ -30,31 +30,21 @@ properties: · 29 unmodified lines
30	30	- ti,ths8135
31	31
32	32	ports:
33		− type: object
34		− description: \|
35		− This device has two video ports. Their connections are modeled using the
36		− OF graph bindings specified in Documentation/devicetree/bindings/graph.txt.
37		− properties:
38		− '#address-cells':
39		− const: 1
40		−
41		− '#size-cells':
42		− const: 0
	33	+ $ref: /schemas/graph.yaml#/properties/ports
43	34
	35	+ properties:
44	36	port@0:
45		− type: object
	37	+ $ref: /schemas/graph.yaml#/properties/port
46	38	description: The bridge input
47	39
48	40	port@1:
49		− type: object
	41	+ $ref: /schemas/graph.yaml#/properties/port
50	42	description: The bridge output
51	43
52	44	required:
53	45	- port@0
54	46	- port@1
55	47
56		− additionalProperties: false
57		−
58	48	enable-gpios:
59	49	maxItems: 1
60	50	description: GPIO controlling bridge enable

Documentation/devicetree/bindings/display/bridge/snps,dw-mipi-dsi.yaml+4−3

@@ -47,14 +47,15 @@ properties: · 46 unmodified lines
47	47	const: apb
48	48
49	49	ports:
50		− type: object
	50	+ $ref: /schemas/graph.yaml#/properties/ports
51	51
52	52	properties:
53	53	port@0:
54		− type: object
	54	+ $ref: /schemas/graph.yaml#/properties/port
55	55	description: Input node to receive pixel data.
	56	+
56	57	port@1:
57		− type: object
	58	+ $ref: /schemas/graph.yaml#/properties/port
58	59	description: DSI output node to panel.
59	60
60	61	required:

Documentation/devicetree/bindings/display/bridge/thine,thc63lvd1024.yaml+5−16

@@ -25,11 +25,8 @@ properties: · 24 unmodified lines
25	25	const: thine,thc63lvd1024
26	26
27	27	ports:
28		− type: object
	28	+ $ref: /schemas/graph.yaml#/properties/ports
29	29	description: \|
30		− This device has four video ports. Their connections are modeled using the
31		− OF graph bindings specified in Documentation/devicetree/bindings/graph.txt.
32		−
33	30	The device can operate in single or dual input and output modes.
34	31
35	32	When operating in single input mode, all pixels are received on port@0,
@@ -43,34 +40,26 @@ properties: · 7 unmodified lines
43	40	port@3 shall contain endpoints.
44	41
45	42	properties:
46		− '#address-cells':
47		− const: 1
48		−
49		− '#size-cells':
50		− const: 0
51		−
52	43	port@0:
53		− type: object
	44	+ $ref: /schemas/graph.yaml#/properties/port
54	45	description: First LVDS input port
55	46
56	47	port@1:
57		− type: object
	48	+ $ref: /schemas/graph.yaml#/properties/port
58	49	description: Second LVDS input port
59	50
60	51	port@2:
61		− type: object
	52	+ $ref: /schemas/graph.yaml#/properties/port
62	53	description: First digital CMOS/TTL parallel output
63	54
64	55	port@3:
65		− type: object
	56	+ $ref: /schemas/graph.yaml#/properties/port
66	57	description: Second digital CMOS/TTL parallel output
67	58
68	59	required:
69	60	- port@0
70	61	- port@2
71	62
72		− additionalProperties: false
73		−
74	63	oe-gpios:
75	64	maxItems: 1
76	65	description: Output enable GPIO signal, pin name "OE", active high.

Documentation/devicetree/bindings/display/bridge/ti,sn65dsi86.yaml+6−39

@@ -71,54 +71,26 @@ properties: · 70 unmodified lines
71	71	description: See ../../pwm/pwm.yaml for description of the cell formats.
72	72
73	73	ports:
74		− type: object
75		− additionalProperties: false
	74	+ $ref: /schemas/graph.yaml#/properties/ports
76	75
77	76	properties:
78		− "#address-cells":
79		− const: 1
80		−
81		− "#size-cells":
82		− const: 0
83		−
84	77	port@0:
85		− type: object
86		− additionalProperties: false
87		−
	78	+ $ref: /schemas/graph.yaml#/properties/port
88	79	description:
89	80	Video port for MIPI DSI input
90	81
91		− properties:
92		− reg:
93		− const: 0
94		−
95		− endpoint:
96		− type: object
97		− additionalProperties: false
98		− properties:
99		− remote-endpoint: true
100		−
101		− required:
102		− - reg
103		−
104	82	port@1:
105		− type: object
106		− additionalProperties: false
107		−
	83	+ $ref: /schemas/graph.yaml#/$defs/port-base
	84	+ unevaluatedProperties: false
108	85	description:
109	86	Video port for eDP output (panel or connector).
110	87
111	88	properties:
112		− reg:
113		− const: 1
114		−
115	89	endpoint:
116		− type: object
117		− additionalProperties: false
	90	+ $ref: /schemas/graph.yaml#/$defs/endpoint-base
	91	+ unevaluatedProperties: false
118	92
119	93	properties:
120		− remote-endpoint: true
121		−
122	94	data-lanes:
123	95	oneOf:
124	96	- minItems: 1
@@ -171,12 +143,7 @@ properties: · 46 unmodified lines
171	143	dependencies:
172	144	lane-polarities: [data-lanes]
173	145
174		− required:
175		− - reg
176		−
177	146	required:
178		− - "#address-cells"
179		− - "#size-cells"
180	147	- port@0
181	148	- port@1
182	149

Documentation/devicetree/bindings/display/bridge/ti,tfp410.yaml+6−18

@@ -31,23 +31,18 @@ properties: · 30 unmodified lines
31	31	maximum: 7
32	32
33	33	ports:
34		− description:
35		− A node containing input and output port nodes with endpoint
36		− definitions as documented in
37		− Documentation/devicetree/bindings/media/video-interfaces.txt
38		− type: object
	34	+ $ref: /schemas/graph.yaml#/properties/ports
39	35
40	36	properties:
41	37	port@0:
	38	+ $ref: /schemas/graph.yaml#/$defs/port-base
	39	+ unevaluatedProperties: false
42	40	description: DPI input port.
43		− type: object
44	41
45	42	properties:
46		− reg:
47		− const: 0
48		−
49	43	endpoint:
50		− type: object
	44	+ $ref: /schemas/graph.yaml#/$defs/endpoint-base
	45	+ unevaluatedProperties: false
51	46
52	47	properties:
53	48	pclk-sample:
@@ -67,15 +62,8 @@ properties: · 13 unmodified lines
67	62	default: 24
68	63
69	64	port@1:
	65	+ $ref: /schemas/graph.yaml#/properties/port
70	66	description: DVI output port.
71		− type: object
72		−
73		− properties:
74		− reg:
75		− const: 1
76		−
77		− endpoint:
78		− type: object
79	67
80	68	required:
81	69	- port@0

Documentation/devicetree/bindings/display/bridge/toshiba,tc358762.yaml+5−47

@@ -25,62 +25,20 @@ properties: · 24 unmodified lines
25	25	description: Regulator for 1.2V internal core power.
26	26
27	27	ports:
28		− type: object
	28	+ $ref: /schemas/graph.yaml#/properties/ports
29	29
30	30	properties:
31		− "#address-cells":
32		− const: 1
33		−
34		− "#size-cells":
35		− const: 0
36		−
37	31	port@0:
38		− type: object
39		− additionalProperties: false
40		−
41		− description: \|
	32	+ $ref: /schemas/graph.yaml#/properties/port
	33	+ description:
42	34	Video port for MIPI DSI input
43	35
44		− properties:
45		− reg:
46		− const: 0
47		−
48		− patternProperties:
49		− endpoint:
50		− type: object
51		− additionalProperties: false
52		−
53		− properties:
54		− remote-endpoint: true
55		−
56		− required:
57		− - reg
58		−
59	36	port@1:
60		− type: object
61		− additionalProperties: false
62		−
63		− description: \|
	37	+ $ref: /schemas/graph.yaml#/properties/port
	38	+ description:
64	39	Video port for MIPI DPI output (panel or connector).
65	40
66		− properties:
67		− reg:
68		− const: 1
69		−
70		− patternProperties:
71		− endpoint:
72		− type: object
73		− additionalProperties: false
74		−
75		− properties:
76		− remote-endpoint: true
77		−
78		− required:
79		− - reg
80		−
81	41	required:
82		− - "#address-cells"
83		− - "#size-cells"
84	42	- port@0
85	43	- port@1
86	44

Documentation/devicetree/bindings/display/bridge/toshiba,tc358768.yaml+6−42

@@ -42,65 +42,30 @@ properties: · 41 unmodified lines
42	42	const: refclk
43	43
44	44	ports:
45		− type: object
	45	+ $ref: /schemas/graph.yaml#/properties/ports
46	46
47	47	properties:
48		− "#address-cells":
49		− const: 1
50		−
51		− "#size-cells":
52		− const: 0
53		−
54	48	port@0:
55		− type: object
56		− additionalProperties: false
57		−
	49	+ $ref: /schemas/graph.yaml#/$defs/port-base
	50	+ unevaluatedProperties: false
58	51	description: \|
59	52	Video port for RGB input
60	53
61	54	properties:
62		− reg:
63		− const: 0
64		−
65		− patternProperties:
66	55	endpoint:
67		− type: object
68		− additionalProperties: false
	56	+ $ref: /schemas/graph.yaml#/$defs/endpoint-base
	57	+ unevaluatedProperties: false
69	58
70	59	properties:
71	60	data-lines:
72	61	enum: [ 16, 18, 24 ]
73	62
74		− remote-endpoint: true
75		−
76		− required:
77		− - reg
78		−
79	63	port@1:
80		− type: object
81		− additionalProperties: false
82		−
	64	+ $ref: /schemas/graph.yaml#/properties/port
83	65	description: \|
84	66	Video port for DSI output (panel or connector).
85	67
86		− properties:
87		− reg:
88		− const: 1
89		−
90		− patternProperties:
91		− endpoint:
92		− type: object
93		− additionalProperties: false
94		−
95		− properties:
96		− remote-endpoint: true
97		−
98		− required:
99		− - reg
100		−
101	68	required:
102		− - "#address-cells"
103		− - "#size-cells"
104	69	- port@0
105	70	- port@1
106	71
@@ -156,4 +121,3 @@ examples: · 49 unmodified lines
156	121	};
157	122	};
158	123	};
159		−

Documentation/devicetree/bindings/display/bridge/toshiba,tc358775.yaml+5−14

@@ -42,31 +42,22 @@ properties: · 41 unmodified lines
42	42	description: Hardware reset, Low active
43	43
44	44	ports:
45		− type: object
46		− description:
47		− A node containing input and output port nodes with endpoint definitions
48		− as documented in
49		− Documentation/devicetree/bindings/media/video-interfaces.txt
50		− properties:
51		− "#address-cells":
52		− const: 1
53		−
54		− "#size-cells":
55		− const: 0
	45	+ $ref: /schemas/graph.yaml#/properties/ports
56	46
	47	+ properties:
57	48	port@0:
58		− type: object
	49	+ $ref: /schemas/graph.yaml#/properties/port
59	50	description: \|
60	51	DSI Input. The remote endpoint phandle should be a
61	52	reference to a valid mipi_dsi_host device node.
62	53
63	54	port@1:
64		− type: object
	55	+ $ref: /schemas/graph.yaml#/properties/port
65	56	description: \|
66	57	Video port for LVDS output (panel or connector).
67	58
68	59	port@2:
69		− type: object
	60	+ $ref: /schemas/graph.yaml#/properties/port
70	61	description: \|
71	62	Video port for Dual link LVDS output (panel or connector).
72	63

Documentation/devicetree/bindings/display/connector/analog-tv-connector.yaml+1−0

@@ -25,6 +25,7 @@ properties: · 24 unmodified lines
25	25	$ref: /schemas/types.yaml#/definitions/uint32
26	26
27	27	port:
	28	+ $ref: /schemas/graph.yaml#/properties/port
28	29	description: Connection to controller providing analog TV signals
29	30
30	31	required:

Documentation/devicetree/bindings/display/connector/dvi-connector.yaml+1−0

@@ -36,6 +36,7 @@ properties: · 35 unmodified lines
36	36	description: the connector has pins for DVI dual-link
37	37
38	38	port:
	39	+ $ref: /schemas/graph.yaml#/properties/port
39	40	description: Connection to controller providing DVI signals
40	41
41	42	required:

Documentation/devicetree/bindings/display/connector/hdmi-connector.yaml+1−0

@@ -37,6 +37,7 @@ properties: · 36 unmodified lines
37	37	maxItems: 1
38	38
39	39	port:
	40	+ $ref: /schemas/graph.yaml#/properties/port
40	41	description: Connection to controller providing HDMI signals
41	42
42	43	required:

Documentation/devicetree/bindings/display/connector/vga-connector.yaml+1−0

@@ -20,6 +20,7 @@ properties: · 19 unmodified lines
20	20	$ref: /schemas/types.yaml#/definitions/phandle
21	21
22	22	port:
	23	+ $ref: /schemas/graph.yaml#/properties/port
23	24	description: Connection to controller providing VGA signals
24	25
25	26	required:

Documentation/devicetree/bindings/display/imx/nxp,imx8mq-dcss.yaml+1−1

@@ -74,7 +74,7 @@ properties: · 73 unmodified lines
74	74	- description: Must be 400 MHz
75	75
76	76	port:
77		− type: object
	77	+ $ref: /schemas/graph.yaml#/properties/port
78	78	description:
79	79	A port node pointing to the input port of a HDMI/DP or MIPI display bridge.
80	80

Documentation/devicetree/bindings/display/ingenic,ipu.yaml+2−3

@@ -31,9 +31,8 @@ properties: · 30 unmodified lines
31	31	clock-names:
32	32	const: ipu
33	33
34		−patternProperties:
35		− "^ports?$":
36		− description: OF graph bindings (specified in bindings/graph.txt).
	34	+ port:
	35	+ $ref: /schemas/graph.yaml#/properties/port
37	36
38	37	required:
39	38	- compatible

Documentation/devicetree/bindings/display/ingenic,lcd.yaml+5−5

@@ -39,18 +39,18 @@ properties: · 38 unmodified lines
39	39	minItems: 1
40	40
41	41	port:
42		− description: OF graph bindings (specified in bindings/graph.txt).
	42	+ $ref: /schemas/graph.yaml#/properties/port
43	43
44	44	ports:
45		− description: OF graph bindings (specified in bindings/graph.txt).
46		− type: object
	45	+ $ref: /schemas/graph.yaml#/properties/ports
	46	+
47	47	properties:
48	48	port@0:
49		− type: object
	49	+ $ref: /schemas/graph.yaml#/properties/port
50	50	description: DPI output, to interface with TFT panels.
51	51
52	52	port@8:
53		− type: object
	53	+ $ref: /schemas/graph.yaml#/properties/port
54	54	description: Link to the Image Processing Unit (IPU).
55	55	(See ingenic,ipu.yaml).
56	56

Documentation/devicetree/bindings/display/intel,keembay-display.yaml+1−1

@@ -36,7 +36,7 @@ properties: · 35 unmodified lines
36	36	maxItems: 1
37	37
38	38	port:
39		− type: object
	39	+ $ref: /schemas/graph.yaml#/properties/port
40	40	description: Display output node to DSI.
41	41
42	42	required:

Documentation/devicetree/bindings/display/panel/advantech,idk-2121wr.yaml+10−11

@@ -37,34 +37,33 @@ properties: · 36 unmodified lines
37	37	panel-timing: true
38	38
39	39	ports:
40		− type: object
	40	+ $ref: /schemas/graph.yaml#/properties/ports
	41	+
41	42	properties:
42	43	port@0:
43		− type: object
	44	+ $ref: /schemas/graph.yaml#/$defs/port-base
	45	+ unevaluatedProperties: false
44	46	description: The sink for odd pixels.
45	47	properties:
46		− reg:
47		− const: 0
48		−
49	48	dual-lvds-odd-pixels: true
50	49
51	50	required:
52		− - reg
53	51	- dual-lvds-odd-pixels
54	52
55	53	port@1:
56		− type: object
	54	+ $ref: /schemas/graph.yaml#/$defs/port-base
	55	+ unevaluatedProperties: false
57	56	description: The sink for even pixels.
58	57	properties:
59		− reg:
60		− const: 1
61		−
62	58	dual-lvds-even-pixels: true
63	59
64	60	required:
65		− - reg
66	61	- dual-lvds-even-pixels
67	62
	63	+ required:
	64	+ - port@0
	65	+ - port@1
	66	+
68	67	additionalProperties: false
69	68
70	69	required:

Documentation/devicetree/bindings/display/panel/panel-common.yaml+1−10

@@ -68,16 +68,7 @@ properties: · 67 unmodified lines
68	68
69	69	# Connectivity
70	70	port:
71		− type: object
72		−
73		− ports:
74		− type: object
75		− description:
76		− Panels receive video data through one or multiple connections. While
77		− the nature of those connections is specific to the panel type, the
78		− connectivity is expressed in a standard fashion using ports as specified
79		− in the device graph bindings defined in
80		− Documentation/devicetree/bindings/graph.txt.
	71	+ $ref: /schemas/graph.yaml#/properties/port
81	72
82	73	ddc-i2c-bus:
83	74	$ref: /schemas/types.yaml#/definitions/phandle

Documentation/devicetree/bindings/display/panel/samsung,s6e63m0.yaml+3−1

@@ -11,6 +11,7 @@ maintainers: · 10 unmodified lines
11	11
12	12	allOf:
13	13	- $ref: panel-common.yaml#
	14	+ - $ref: /schemas/leds/backlight/common.yaml#
14	15
15	16	properties:
16	17	compatible:
@@ -19,6 +20,8 @@ properties: · 2 unmodified lines
19	20	reg: true
20	21	reset-gpios: true
21	22	port: true
	23	+ default-brightness: true
	24	+ max-brightness: true
22	25
23	26	vdd3-supply:
24	27	description: VDD regulator
@@ -31,7 +34,6 @@ required: · 6 unmodified lines
31	34	- reset-gpios
32	35	- vdd3-supply
33	36	- vci-supply
34		− - port
35	37
36	38	unevaluatedProperties: false
37	39

Documentation/devicetree/bindings/display/rockchip/rockchip,rk3066-hdmi.yaml+3−13

@@ -43,34 +43,24 @@ properties: · 42 unmodified lines
43	43	This soc uses GRF regs to switch the HDMI TX input between vop0 and vop1.
44	44
45	45	ports:
46		− type: object
	46	+ $ref: /schemas/graph.yaml#/properties/ports
47	47
48	48	properties:
49		− "#address-cells":
50		− const: 1
51		−
52		− "#size-cells":
53		− const: 0
54		−
55	49	port@0:
56		− type: object
	50	+ $ref: /schemas/graph.yaml#/properties/port
57	51	description:
58	52	Port node with two endpoints, numbered 0 and 1,
59	53	connected respectively to vop0 and vop1.
60	54
61	55	port@1:
62		− type: object
	56	+ $ref: /schemas/graph.yaml#/properties/port
63	57	description:
64	58	Port node with one endpoint connected to a hdmi-connector node.
65	59
66	60	required:
67		− - "#address-cells"
68		− - "#size-cells"
69	61	- port@0
70	62	- port@1
71	63
72		− additionalProperties: false
73		−
74	64	required:
75	65	- compatible
76	66	- reg

Documentation/devicetree/bindings/display/rockchip/rockchip-vop.yaml+1−4

@@ -70,10 +70,7 @@ properties: · 69 unmodified lines
70	70	- const: dclk
71	71
72	72	port:
73		− type: object
74		− description:
75		− A port node with endpoint definitions as defined in
76		− Documentation/devicetree/bindings/media/video-interfaces.txt.
	73	+ $ref: /schemas/graph.yaml#/properties/port
77	74
78	75	assigned-clocks:
79	76	maxItems: 2

Documentation/devicetree/bindings/display/st,stm32-dsi.yaml+4−8

@@ -51,20 +51,16 @@ properties: · 50 unmodified lines
51	51	Phandle of the regulator that provides the supply voltage.
52	52
53	53	ports:
54		− type: object
55		− description:
56		− A node containing DSI input & output port nodes with endpoint
57		− definitions as documented in
58		− Documentation/devicetree/bindings/media/video-interfaces.txt
59		− Documentation/devicetree/bindings/graph.txt
	54	+ $ref: /schemas/graph.yaml#/properties/ports
	55	+
60	56	properties:
61	57	port@0:
62		− type: object
	58	+ $ref: /schemas/graph.yaml#/properties/port
63	59	description:
64	60	DSI input port node, connected to the ltdc rgb output port.
65	61
66	62	port@1:
67		− type: object
	63	+ $ref: /schemas/graph.yaml#/properties/port
68	64	description:
69	65	DSI output port node, connected to a panel or a bridge input port"
70	66

Documentation/devicetree/bindings/display/st,stm32-ltdc.yaml+3−5

@@ -35,15 +35,13 @@ properties: · 34 unmodified lines
35	35	maxItems: 1
36	36
37	37	port:
38		− type: object
39		− description:
40		− "Video port for DPI RGB output.
	38	+ $ref: /schemas/graph.yaml#/properties/port
	39	+ description: \|
	40	+ Video port for DPI RGB output.
41	41	ltdc has one video port with up to 2 endpoints:
42	42	- for external dpi rgb panel or bridge, using gpios.
43	43	- for internal dpi input of the MIPI DSI host controller.
44	44	Note: These 2 endpoints cannot be activated simultaneously.
45		− Please refer to the bindings defined in
46		− Documentation/devicetree/bindings/media/video-interfaces.txt."
47	45
48	46	required:
49	47	- compatible

Documentation/devicetree/bindings/display/ste,mcde.yaml+2−3

@@ -42,10 +42,9 @@ properties: · 41 unmodified lines
42	42	description: a phandle to the analog voltage regulator
43	43
44	44	port:
45		− type: object
	45	+ $ref: /schemas/graph.yaml#/properties/port
46	46	description:
47		− A DPI port node with endpoint definitions as defined in
48		− Documentation/devicetree/bindings/media/video-interfaces.txt
	47	+ A DPI port node
49	48
50	49	"#address-cells":
51	50	const: 1

Documentation/devicetree/bindings/display/ti/ti,am65x-dss.yaml+4−15

@@ -74,30 +74,19 @@ properties: · 73 unmodified lines
74	74	type: boolean
75	75
76	76	ports:
77		− type: object
78		− description:
79		− Ports as described in Documentation/devicetree/bindings/graph.txt
80		− properties:
81		− "#address-cells":
82		− const: 1
83		−
84		− "#size-cells":
85		− const: 0
	77	+ $ref: /schemas/graph.yaml#/properties/ports
86	78
	79	+ properties:
87	80	port@0:
88		− type: object
	81	+ $ref: /schemas/graph.yaml#/properties/port
89	82	description:
90	83	The DSS OLDI output port node form video port 1
91	84
92	85	port@1:
93		− type: object
	86	+ $ref: /schemas/graph.yaml#/properties/port
94	87	description:
95	88	The DSS DPI output port node from video port 2
96	89
97		− required:
98		− - "#address-cells"
99		− - "#size-cells"
100		−
101	90	ti,am65x-oldi-io-ctrl:
102	91	$ref: "/schemas/types.yaml#/definitions/phandle-array"
103	92	maxItems: 1

Documentation/devicetree/bindings/display/ti/ti,j721e-dss.yaml+6−17

@@ -107,40 +107,29 @@ properties: · 106 unmodified lines
107	107	type: boolean
108	108
109	109	ports:
110		− type: object
111		− description:
112		− Ports as described in Documentation/devicetree/bindings/graph.txt
113		− properties:
114		− "#address-cells":
115		− const: 1
116		−
117		− "#size-cells":
118		− const: 0
	110	+ $ref: /schemas/graph.yaml#/properties/ports
119	111
	112	+ properties:
120	113	port@0:
121		− type: object
	114	+ $ref: /schemas/graph.yaml#/properties/port
122	115	description:
123	116	The output port node form video port 1
124	117
125	118	port@1:
126		− type: object
	119	+ $ref: /schemas/graph.yaml#/properties/port
127	120	description:
128	121	The output port node from video port 2
129	122
130	123	port@2:
131		− type: object
	124	+ $ref: /schemas/graph.yaml#/properties/port
132	125	description:
133	126	The output port node from video port 3
134	127
135	128	port@3:
136		− type: object
	129	+ $ref: /schemas/graph.yaml#/properties/port
137	130	description:
138	131	The output port node from video port 4
139	132
140		− required:
141		− - "#address-cells"
142		− - "#size-cells"
143		−
144	133	max-memory-bandwidth:
145	134	$ref: /schemas/types.yaml#/definitions/uint32
146	135	description:

Documentation/devicetree/bindings/display/ti/ti,k2g-dss.yaml+1−2

@@ -54,9 +54,8 @@ properties: · 53 unmodified lines
54	54	description: phandle to the associated power domain
55	55
56	56	port:
57		− type: object
	57	+ $ref: /schemas/graph.yaml#/properties/port
58	58	description:
59		− Port as described in Documentation/devicetree/bindings/graph.txt.
60	59	The DSS DPI output port node
61	60
62	61	max-memory-bandwidth:

Documentation/gpu/vkms.rst+12−0

@@ -35,6 +35,18 @@ Now, to load the driver, use:: · 34 unmodified lines
35	35	On running the lsmod command now, the VKMS driver will appear listed.
36	36	You can also observe the driver being loaded in the dmesg logs.
37	37
	38	+The VKMS driver has optional features to simulate different kinds of hardware,
	39	+which are exposed as module options. You can use the `modinfo` command
	40	+to see the module options for vkms::
	41	+
	42	+ modinfo vkms
	43	+
	44	+Module options are helpful when testing, and enabling modules
	45	+can be done while loading vkms. For example, to load vkms with cursor enabled,
	46	+use::
	47	+
	48	+ sudo modprobe vkms enable_cursor=1
	49	+
38	50	To disable the driver, use ::
39	51
40	52	sudo modprobe -r vkms

MAINTAINERS+1−0

@@ -5784,6 +5784,7 @@ F: drivers/gpu/drm/vboxvideo/ · 5783 unmodified lines
5784	5784	DRM DRIVER FOR VMWARE VIRTUAL GPU
5785	5785	M: "VMware Graphics" <linux-graphics-maintainer@vmware.com>
5786	5786	M: Roland Scheidegger <sroland@vmware.com>
	5787	+M: Zack Rusin <zackr@vmware.com>
5787	5788	L: dri-devel@lists.freedesktop.org
5788	5789	S: Supported
5789	5790	T: git git://people.freedesktop.org/~sroland/linux

drivers/dma-buf/Kconfig+8−0

@@ -50,6 +50,14 @@ config DMABUF_MOVE_NOTIFY · 49 unmodified lines
50	50	This is marked experimental because we don't yet have a consistent
51	51	execution context and memory management between drivers.
52	52
	53	+config DMABUF_DEBUG
	54	+ bool "DMA-BUF debug checks"
	55	+ default y if DMA_API_DEBUG
	56	+ help
	57	+ This option enables additional checks for DMA-BUF importers and
	58	+ exporters. Specifically it validates that importers do not peek at the
	59	+ underlying struct page when they import a buffer.
	60	+
53	61	config DMABUF_SELFTESTS
54	62	tristate "Selftests for the dma-buf interfaces"
55	63	default n

drivers/dma-buf/dma-buf.c+42−4

@@ -653,6 +653,34 @@ void dma_buf_put(struct dma_buf *dmabuf) · 652 unmodified lines
653	653	}
654	654	EXPORT_SYMBOL_GPL(dma_buf_put);
655	655
	656	+static void mangle_sg_table(struct sg_table *sg_table)
	657	+{
	658	+#ifdef CONFIG_DMABUF_DEBUG
	659	+ int i;
	660	+ struct scatterlist *sg;
	661	+
	662	+ /* To catch abuse of the underlying struct page by importers mix
	663	+ * up the bits, but take care to preserve the low SG_ bits to
	664	+ * not corrupt the sgt. The mixing is undone in __unmap_dma_buf
	665	+ * before passing the sgt back to the exporter. */
	666	+ for_each_sgtable_sg(sg_table, sg, i)
	667	+ sg->page_link ^= ~0xffUL;
	668	+#endif
	669	+
	670	+}
	671	+static struct sg_table * __map_dma_buf(struct dma_buf_attachment *attach,
	672	+ enum dma_data_direction direction)
	673	+{
	674	+ struct sg_table *sg_table;
	675	+
	676	+ sg_table = attach->dmabuf->ops->map_dma_buf(attach, direction);
	677	+
	678	+ if (!IS_ERR_OR_NULL(sg_table))
	679	+ mangle_sg_table(sg_table);
	680	+
	681	+ return sg_table;
	682	+}
	683	+
656	684	/**
657	685	* dma_buf_dynamic_attach - Add the device to dma_buf's attachments list
658	686	* @dmabuf: [in] buffer to attach device to.
@@ -724,7 +752,7 @@ dma_buf_dynamic_attach(struct dma_buf dmabuf, struct device dev, · 65 unmodified lines
724	752	goto err_unlock;
725	753	}
726	754
727		− sgt = dmabuf->ops->map_dma_buf(attach, DMA_BIDIRECTIONAL);
	755	+ sgt = __map_dma_buf(attach, DMA_BIDIRECTIONAL);
728	756	if (!sgt)
729	757	sgt = ERR_PTR(-ENOMEM);
730	758	if (IS_ERR(sgt)) {
@@ -771,6 +799,16 @@ struct dma_buf_attachment dma_buf_attach(struct dma_buf dmabuf, · 40 unmodified lines
771	799	}
772	800	EXPORT_SYMBOL_GPL(dma_buf_attach);
773	801
	802	+static void __unmap_dma_buf(struct dma_buf_attachment *attach,
	803	+ struct sg_table *sg_table,
	804	+ enum dma_data_direction direction)
	805	+{
	806	+ /* uses XOR, hence this unmangles */
	807	+ mangle_sg_table(sg_table);
	808	+
	809	+ attach->dmabuf->ops->unmap_dma_buf(attach, sg_table, direction);
	810	+}
	811	+
774	812	/**
775	813	* dma_buf_detach - Remove the given attachment from dmabuf's attachments list
776	814	* @dmabuf: [in] buffer to detach from.
@@ -789,7 +827,7 @@ void dma_buf_detach(struct dma_buf dmabuf, struct dma_buf_attachment attach) · 12 unmodified lines
789	827	if (dma_buf_is_dynamic(attach->dmabuf))
790	828	dma_resv_lock(attach->dmabuf->resv, NULL);
791	829
792		− dmabuf->ops->unmap_dma_buf(attach, attach->sgt, attach->dir);
	830	+ __unmap_dma_buf(attach, attach->sgt, attach->dir);
793	831
794	832	if (dma_buf_is_dynamic(attach->dmabuf)) {
795	833	dma_buf_unpin(attach);
@@ -911,7 +949,7 @@ struct sg_table dma_buf_map_attachment(struct dma_buf_attachment attach, · 115 unmodified lines
911	949	}
912	950	}
913	951
914		− sg_table = attach->dmabuf->ops->map_dma_buf(attach, direction);
	952	+ sg_table = __map_dma_buf(attach, direction);
915	953	if (!sg_table)
916	954	sg_table = ERR_PTR(-ENOMEM);
917	955
@@ -974,7 +1012,7 @@ void dma_buf_unmap_attachment(struct dma_buf_attachment *attach, · 56 unmodified lines
974	1012	if (dma_buf_is_dynamic(attach->dmabuf))
975	1013	dma_resv_assert_held(attach->dmabuf->resv);
976	1014
977		− attach->dmabuf->ops->unmap_dma_buf(attach, sg_table, direction);
	1015	+ __unmap_dma_buf(attach, sg_table, direction);
978	1016
979	1017	if (dma_buf_is_dynamic(attach->dmabuf) &&
980	1018	!IS_ENABLED(CONFIG_DMABUF_MOVE_NOTIFY))

drivers/gpu/drm/Kconfig+0−5

@@ -214,10 +214,6 @@ config DRM_GEM_SHMEM_HELPER · 213 unmodified lines
214	214	help
215	215	Choose this if you need the GEM shmem helper functions
216	216
217		−config DRM_VM
218		− bool
219		− depends on DRM && MMU
220		−
221	217	config DRM_SCHED
222	218	tristate
223	219	depends on DRM
@@ -391,7 +387,6 @@ source "drivers/gpu/drm/xlnx/Kconfig" · 167 unmodified lines
391	387	menuconfig DRM_LEGACY
392	388	bool "Enable legacy drivers (DANGEROUS)"
393	389	depends on DRM && MMU
394		− select DRM_VM
395	390	help
396	391	Enable legacy DRI1 drivers. Those drivers expose unsafe and dangerous
397	392	APIs to user-space, which can be used to circumvent access

drivers/gpu/drm/Makefile+3−3

@@ -5,7 +5,7 @@ · 4 unmodified lines
5	5
6	6	drm-y := drm_auth.o drm_cache.o \
7	7	drm_file.o drm_gem.o drm_ioctl.o drm_irq.o \
8		− drm_memory.o drm_drv.o \
	8	+ drm_drv.o \
9	9	drm_sysfs.o drm_hashtab.o drm_mm.o \
10	10	drm_crtc.o drm_fourcc.o drm_modes.o drm_edid.o \
11	11	drm_encoder_slave.o \
@@ -20,9 +20,9 @@ drm-y := drm_auth.o drm_cache.o \ · 8 unmodified lines
20	20	drm_client_modeset.o drm_atomic_uapi.o drm_hdcp.o \
21	21	drm_managed.o drm_vblank_work.o
22	22
23		−drm-$(CONFIG_DRM_LEGACY) += drm_legacy_misc.o drm_bufs.o drm_context.o drm_dma.o drm_scatter.o drm_lock.o
	23	+drm-$(CONFIG_DRM_LEGACY) += drm_bufs.o drm_context.o drm_dma.o drm_legacy_misc.o drm_lock.o \
	24	+ drm_memory.o drm_scatter.o drm_vm.o
24	25	drm-$(CONFIG_DRM_LIB_RANDOM) += lib/drm_random.o
25		−drm-$(CONFIG_DRM_VM) += drm_vm.o
26	26	drm-$(CONFIG_COMPAT) += drm_ioc32.o
27	27	drm-$(CONFIG_DRM_GEM_CMA_HELPER) += drm_gem_cma_helper.o
28	28	drm-$(CONFIG_DRM_GEM_SHMEM_HELPER) += drm_gem_shmem_helper.o

drivers/gpu/drm/amd/amdgpu/amdgpu_device.c+16−14

@@ -1106,8 +1106,7 @@ void amdgpu_device_wb_free(struct amdgpu_device *adev, u32 wb) · 1105 unmodified lines
1106	1106	*/
1107	1107	int amdgpu_device_resize_fb_bar(struct amdgpu_device *adev)
1108	1108	{
1109		− u64 space_needed = roundup_pow_of_two(adev->gmc.real_vram_size);
1110		− u32 rbar_size = order_base_2(((space_needed >> 20) \| 1)) - 1;
	1109	+ int rbar_size = pci_rebar_bytes_to_size(adev->gmc.real_vram_size);
1111	1110	struct pci_bus *root;
1112	1111	struct resource *res;
1113	1112	unsigned i;
@@ -1138,6 +1137,10 @@ int amdgpu_device_resize_fb_bar(struct amdgpu_device *adev) · 24 unmodified lines
1138	1137	if (!res)
1139	1138	return 0;
1140	1139
	1140	+ /* Limit the BAR size to what is available */
	1141	+ rbar_size = min(fls(pci_rebar_get_possible_sizes(adev->pdev, 0)) - 1,
	1142	+ rbar_size);
	1143	+
1141	1144	/* Disable memory decoding while we change the BAR addresses and size */
1142	1145	pci_read_config_word(adev->pdev, PCI_COMMAND, &cmd);
1143	1146	pci_write_config_word(adev->pdev, PCI_COMMAND,
@@ -1423,9 +1426,9 @@ static void amdgpu_switcheroo_set_state(struct pci_dev *pdev, · 279 unmodified lines
1423	1426	/* don't suspend or resume card normally */
1424	1427	dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
1425	1428
1426		− pci_set_power_state(dev->pdev, PCI_D0);
1427		− amdgpu_device_load_pci_state(dev->pdev);
1428		− r = pci_enable_device(dev->pdev);
	1429	+ pci_set_power_state(pdev, PCI_D0);
	1430	+ amdgpu_device_load_pci_state(pdev);
	1431	+ r = pci_enable_device(pdev);
1429	1432	if (r)
1430	1433	DRM_WARN("pci_enable_device failed (%d)\n", r);
1431	1434	amdgpu_device_resume(dev, true);
@@ -1437,10 +1440,10 @@ static void amdgpu_switcheroo_set_state(struct pci_dev *pdev, · 5 unmodified lines
1437	1440	drm_kms_helper_poll_disable(dev);
1438	1441	dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
1439	1442	amdgpu_device_suspend(dev, true);
1440		− amdgpu_device_cache_pci_state(dev->pdev);
	1443	+ amdgpu_device_cache_pci_state(pdev);
1441	1444	/* Shut down the device */
1442		− pci_disable_device(dev->pdev);
1443		− pci_set_power_state(dev->pdev, PCI_D3cold);
	1445	+ pci_disable_device(pdev);
	1446	+ pci_set_power_state(pdev, PCI_D3cold);
1444	1447	dev->switch_power_state = DRM_SWITCH_POWER_OFF;
1445	1448	}
1446	1449	}
@@ -1703,8 +1706,7 @@ static void amdgpu_device_enable_virtual_display(struct amdgpu_device *adev) · 256 unmodified lines
1703	1706	adev->enable_virtual_display = false;
1704	1707
1705	1708	if (amdgpu_virtual_display) {
1706		− struct drm_device *ddev = adev_to_drm(adev);
1707		− const char *pci_address_name = pci_name(ddev->pdev);
	1709	+ const char *pci_address_name = pci_name(adev->pdev);
1708	1710	char pciaddstr, pciaddstr_tmp, pciaddname_tmp, pciaddname;
1709	1711
1710	1712	pciaddstr = kstrdup(amdgpu_virtual_display, GFP_KERNEL);
@@ -3397,7 +3399,7 @@ int amdgpu_device_init(struct amdgpu_device *adev, · 1686 unmodified lines
3397	3399	}
3398	3400	}
3399	3401
3400		− pci_enable_pcie_error_reporting(adev->ddev.pdev);
	3402	+ pci_enable_pcie_error_reporting(adev->pdev);
3401	3403
3402	3404	/* Post card if necessary */
3403	3405	if (amdgpu_device_need_post(adev)) {
@@ -4950,8 +4952,8 @@ pci_ers_result_t amdgpu_pci_error_detected(struct pci_dev *pdev, pci_channel_sta · 1546 unmodified lines
4950	4952	case pci_channel_io_normal:
4951	4953	return PCI_ERS_RESULT_CAN_RECOVER;
4952	4954	/* Fatal error, prepare for slot reset */
4953		− case pci_channel_io_frozen:
4954		− /*
	4955	+ case pci_channel_io_frozen:
	4956	+ /*
4955	4957	* Cancel and wait for all TDRs in progress if failing to
4956	4958	* set adev->in_gpu_reset in amdgpu_device_lock_adev
4957	4959	*
@@ -5042,7 +5044,7 @@ pci_ers_result_t amdgpu_pci_slot_reset(struct pci_dev *pdev) · 84 unmodified lines
5042	5044	goto out;
5043	5045	}
5044	5046
5045		− adev->in_pci_err_recovery = true;
	5047	+ adev->in_pci_err_recovery = true;
5046	5048	r = amdgpu_device_pre_asic_reset(adev, NULL, &need_full_reset);
5047	5049	adev->in_pci_err_recovery = false;
5048	5050	if (r)

drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c+0−1

@@ -1204,7 +1204,6 @@ static int amdgpu_pci_probe(struct pci_dev *pdev, · 1203 unmodified lines
1204	1204	if (ret)
1205	1205	return ret;
1206	1206
1207		− ddev->pdev = pdev;
1208	1207	pci_set_drvdata(pdev, ddev);
1209	1208
1210	1209	ret = amdgpu_driver_load_kms(adev, ent->driver_data);

drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c+1−1

@@ -271,7 +271,7 @@ static int amdgpufb_create(struct drm_fb_helper *helper, · 270 unmodified lines
271	271	DRM_INFO("fb depth is %d\n", fb->format->depth);
272	272	DRM_INFO(" pitch is %d\n", fb->pitches[0]);
273	273
274		− vga_switcheroo_client_fb_set(adev_to_drm(adev)->pdev, info);
	274	+ vga_switcheroo_client_fb_set(adev->pdev, info);
275	275	return 0;
276	276
277	277	out:

drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c+5−5

@@ -619,7 +619,7 @@ int amdgpu_gem_va_ioctl(struct drm_device dev, void data, · 618 unmodified lines
619	619	int r = 0;
620	620
621	621	if (args->va_address < AMDGPU_VA_RESERVED_SIZE) {
622		− dev_dbg(&dev->pdev->dev,
	622	+ dev_dbg(dev->dev,
623	623	"va_address 0x%LX is in reserved area 0x%LX\n",
624	624	args->va_address, AMDGPU_VA_RESERVED_SIZE);
625	625	return -EINVAL;
@@ -627,7 +627,7 @@ int amdgpu_gem_va_ioctl(struct drm_device dev, void data, · 1 unmodified line
627	627
628	628	if (args->va_address >= AMDGPU_GMC_HOLE_START &&
629	629	args->va_address < AMDGPU_GMC_HOLE_END) {
630		− dev_dbg(&dev->pdev->dev,
	630	+ dev_dbg(dev->dev,
631	631	"va_address 0x%LX is in VA hole 0x%LX-0x%LX\n",
632	632	args->va_address, AMDGPU_GMC_HOLE_START,
633	633	AMDGPU_GMC_HOLE_END);
@@ -639,14 +639,14 @@ int amdgpu_gem_va_ioctl(struct drm_device dev, void data, · 5 unmodified lines
639	639	vm_size = adev->vm_manager.max_pfn * AMDGPU_GPU_PAGE_SIZE;
640	640	vm_size -= AMDGPU_VA_RESERVED_SIZE;
641	641	if (args->va_address + args->map_size > vm_size) {
642		− dev_dbg(&dev->pdev->dev,
	642	+ dev_dbg(dev->dev,
643	643	"va_address 0x%llx is in top reserved area 0x%llx\n",
644	644	args->va_address + args->map_size, vm_size);
645	645	return -EINVAL;
646	646	}
647	647
648	648	if ((args->flags & ~valid_flags) && (args->flags & ~prt_flags)) {
649		− dev_dbg(&dev->pdev->dev, "invalid flags combination 0x%08X\n",
	649	+ dev_dbg(dev->dev, "invalid flags combination 0x%08X\n",
650	650	args->flags);
651	651	return -EINVAL;
652	652	}
@@ -658,7 +658,7 @@ int amdgpu_gem_va_ioctl(struct drm_device dev, void data, · 5 unmodified lines
658	658	case AMDGPU_VA_OP_REPLACE:
659	659	break;
660	660	default:
661		− dev_dbg(&dev->pdev->dev, "unsupported operation %d\n",
	661	+ dev_dbg(dev->dev, "unsupported operation %d\n",
662	662	args->operation);
663	663	return -EINVAL;
664	664	}

drivers/gpu/drm/amd/amdgpu/amdgpu_i2c.c+1−1

@@ -176,7 +176,7 @@ struct amdgpu_i2c_chan amdgpu_i2c_create(struct drm_device dev, · 175 unmodified lines
176	176	i2c->rec = *rec;
177	177	i2c->adapter.owner = THIS_MODULE;
178	178	i2c->adapter.class = I2C_CLASS_DDC;
179		− i2c->adapter.dev.parent = &dev->pdev->dev;
	179	+ i2c->adapter.dev.parent = dev->dev;
180	180	i2c->dev = dev;
181	181	i2c_set_adapdata(&i2c->adapter, i2c);
182	182	mutex_init(&i2c->mutex);

drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c+5−5

@@ -142,7 +142,7 @@ int amdgpu_driver_load_kms(struct amdgpu_device *adev, unsigned long flags) · 141 unmodified lines
142	142	(amdgpu_is_atpx_hybrid() \|\|
143	143	amdgpu_has_atpx_dgpu_power_cntl()) &&
144	144	((flags & AMD_IS_APU) == 0) &&
145		− !pci_is_thunderbolt_attached(dev->pdev))
	145	+ !pci_is_thunderbolt_attached(to_pci_dev(dev->dev)))
146	146	flags \|= AMD_IS_PX;
147	147
148	148	parent = pci_upstream_bridge(adev->pdev);
@@ -156,7 +156,7 @@ int amdgpu_driver_load_kms(struct amdgpu_device *adev, unsigned long flags) · 7 unmodified lines
156	156	*/
157	157	r = amdgpu_device_init(adev, flags);
158	158	if (r) {
159		− dev_err(&dev->pdev->dev, "Fatal error during GPU init\n");
	159	+ dev_err(dev->dev, "Fatal error during GPU init\n");
160	160	goto out;
161	161	}
162	162
@@ -199,7 +199,7 @@ int amdgpu_driver_load_kms(struct amdgpu_device *adev, unsigned long flags) · 36 unmodified lines
199	199
200	200	acpi_status = amdgpu_acpi_init(adev);
201	201	if (acpi_status)
202		− dev_dbg(&dev->pdev->dev, "Error during ACPI methods call\n");
	202	+ dev_dbg(dev->dev, "Error during ACPI methods call\n");
203	203
204	204	if (adev->runpm) {
205	205	/* only need to skip on ATPX */
@@ -735,10 +735,10 @@ int amdgpu_info_ioctl(struct drm_device dev, void data, struct drm_file *filp) · 529 unmodified lines
735	735	if (!dev_info)
736	736	return -ENOMEM;
737	737
738		− dev_info->device_id = dev->pdev->device;
	738	+ dev_info->device_id = adev->pdev->device;
739	739	dev_info->chip_rev = adev->rev_id;
740	740	dev_info->external_rev = adev->external_rev_id;
741		− dev_info->pci_rev = dev->pdev->revision;
	741	+ dev_info->pci_rev = adev->pdev->revision;
742	742	dev_info->family = adev->family;
743	743	dev_info->num_shader_engines = adev->gfx.config.max_shader_engines;
744	744	dev_info->num_shader_arrays_per_engine = adev->gfx.config.max_sh_per_se;

drivers/gpu/drm/ast/ast_drv.c+2−2

@@ -147,7 +147,7 @@ static int ast_drm_freeze(struct drm_device *dev) · 146 unmodified lines
147	147	error = drm_mode_config_helper_suspend(dev);
148	148	if (error)
149	149	return error;
150		− pci_save_state(dev->pdev);
	150	+ pci_save_state(to_pci_dev(dev->dev));
151	151	return 0;
152	152	}
153	153
@@ -162,7 +162,7 @@ static int ast_drm_resume(struct drm_device *dev) · 8 unmodified lines
162	162	{
163	163	int ret;
164	164
165		− if (pci_enable_device(dev->pdev))
	165	+ if (pci_enable_device(to_pci_dev(dev->dev)))
166	166	return -EIO;
167	167
168	168	ret = ast_drm_thaw(dev);

drivers/gpu/drm/ast/ast_main.c+13−12

@@ -67,8 +67,9 @@ uint8_t ast_get_index_reg_mask(struct ast_private *ast, · 66 unmodified lines
67	67
68	68	static void ast_detect_config_mode(struct drm_device dev, u32 scu_rev)
69	69	{
70		− struct device_node *np = dev->pdev->dev.of_node;
	70	+ struct device_node *np = dev->dev->of_node;
71	71	struct ast_private *ast = to_ast_private(dev);
	72	+ struct pci_dev *pdev = to_pci_dev(dev->dev);
72	73	uint32_t data, jregd0, jregd1;
73	74
74	75	/* Defaults */
@@ -85,7 +86,7 @@ static void ast_detect_config_mode(struct drm_device dev, u32 scu_rev) · 10 unmodified lines
85	86	}
86	87
87	88	/* Not all families have a P2A bridge */
88		− if (dev->pdev->device != PCI_CHIP_AST2000)
	89	+ if (pdev->device != PCI_CHIP_AST2000)
89	90	return;
90	91
91	92	/*
@@ -119,6 +120,7 @@ static void ast_detect_config_mode(struct drm_device dev, u32 scu_rev) · 27 unmodified lines
119	120	static int ast_detect_chip(struct drm_device dev, bool need_post)
120	121	{
121	122	struct ast_private *ast = to_ast_private(dev);
	123	+ struct pci_dev *pdev = to_pci_dev(dev->dev);
122	124	uint32_t jreg, scu_rev;
123	125
124	126	/*
@@ -143,19 +145,19 @@ static int ast_detect_chip(struct drm_device dev, bool need_post) · 18 unmodified lines
143	145	ast_detect_config_mode(dev, &scu_rev);
144	146
145	147	/* Identify chipset */
146		− if (dev->pdev->revision >= 0x50) {
	148	+ if (pdev->revision >= 0x50) {
147	149	ast->chip = AST2600;
148	150	drm_info(dev, "AST 2600 detected\n");
149		− } else if (dev->pdev->revision >= 0x40) {
	151	+ } else if (pdev->revision >= 0x40) {
150	152	ast->chip = AST2500;
151	153	drm_info(dev, "AST 2500 detected\n");
152		− } else if (dev->pdev->revision >= 0x30) {
	154	+ } else if (pdev->revision >= 0x30) {
153	155	ast->chip = AST2400;
154	156	drm_info(dev, "AST 2400 detected\n");
155		− } else if (dev->pdev->revision >= 0x20) {
	157	+ } else if (pdev->revision >= 0x20) {
156	158	ast->chip = AST2300;
157	159	drm_info(dev, "AST 2300 detected\n");
158		− } else if (dev->pdev->revision >= 0x10) {
	160	+ } else if (pdev->revision >= 0x10) {
159	161	switch (scu_rev & 0x0300) {
160	162	case 0x0200:
161	163	ast->chip = AST1100;
@@ -265,7 +267,7 @@ static int ast_detect_chip(struct drm_device dev, bool need_post) · 103 unmodified lines
265	267
266	268	static int ast_get_dram_info(struct drm_device *dev)
267	269	{
268		− struct device_node *np = dev->pdev->dev.of_node;
	270	+ struct device_node *np = dev->dev->of_node;
269	271	struct ast_private *ast = to_ast_private(dev);
270	272	uint32_t mcr_cfg, mcr_scu_mpll, mcr_scu_strap;
271	273	uint32_t denum, num, div, ref_pll, dsel;
@@ -409,10 +411,9 @@ struct ast_private ast_device_create(const struct drm_driver drv, · 137 unmodified lines
409	411	return ast;
410	412	dev = &ast->base;
411	413
412		− dev->pdev = pdev;
413	414	pci_set_drvdata(pdev, dev);
414	415
415		− ast->regs = pci_iomap(dev->pdev, 1, 0);
	416	+ ast->regs = pci_iomap(pdev, 1, 0);
416	417	if (!ast->regs)
417	418	return ERR_PTR(-EIO);
418	419
@@ -421,14 +422,14 @@ struct ast_private ast_device_create(const struct drm_driver drv, · 2 unmodified lines
421	422	* assume the chip has MMIO enabled by default (rev 0x20
422	423	* and higher).
423	424	*/
424		− if (!(pci_resource_flags(dev->pdev, 2) & IORESOURCE_IO)) {
	425	+ if (!(pci_resource_flags(pdev, 2) & IORESOURCE_IO)) {
425	426	drm_info(dev, "platform has no IO space, trying MMIO\n");
426	427	ast->ioregs = ast->regs + AST_IO_MM_OFFSET;
427	428	}
428	429
429	430	/* "map" IO regs if the above hasn't done so already */
430	431	if (!ast->ioregs) {
431		− ast->ioregs = pci_iomap(dev->pdev, 2, 0);
	432	+ ast->ioregs = pci_iomap(pdev, 2, 0);
432	433	if (!ast->ioregs)
433	434	return ERR_PTR(-EIO);
434	435	}

drivers/gpu/drm/ast/ast_mm.c+9−8

@@ -77,31 +77,32 @@ static u32 ast_get_vram_size(struct ast_private *ast) · 76 unmodified lines
77	77	static void ast_mm_release(struct drm_device dev, void ptr)
78	78	{
79	79	struct ast_private *ast = to_ast_private(dev);
	80	+ struct pci_dev *pdev = to_pci_dev(dev->dev);
80	81
81	82	arch_phys_wc_del(ast->fb_mtrr);
82		− arch_io_free_memtype_wc(pci_resource_start(dev->pdev, 0),
83		− pci_resource_len(dev->pdev, 0));
	83	+ arch_io_free_memtype_wc(pci_resource_start(pdev, 0),
	84	+ pci_resource_len(pdev, 0));
84	85	}
85	86
86	87	int ast_mm_init(struct ast_private *ast)
87	88	{
88	89	struct drm_device *dev = &ast->base;
	90	+ struct pci_dev *pdev = to_pci_dev(dev->dev);
89	91	u32 vram_size;
90	92	int ret;
91	93
92	94	vram_size = ast_get_vram_size(ast);
93	95
94		− ret = drmm_vram_helper_init(dev, pci_resource_start(dev->pdev, 0),
95		− vram_size);
	96	+ ret = drmm_vram_helper_init(dev, pci_resource_start(pdev, 0), vram_size);
96	97	if (ret) {
97	98	drm_err(dev, "Error initializing VRAM MM; %d\n", ret);
98	99	return ret;
99	100	}
100	101
101		− arch_io_reserve_memtype_wc(pci_resource_start(dev->pdev, 0),
102		− pci_resource_len(dev->pdev, 0));
103		− ast->fb_mtrr = arch_phys_wc_add(pci_resource_start(dev->pdev, 0),
104		− pci_resource_len(dev->pdev, 0));
	102	+ arch_io_reserve_memtype_wc(pci_resource_start(pdev, 0),
	103	+ pci_resource_len(pdev, 0));
	104	+ ast->fb_mtrr = arch_phys_wc_add(pci_resource_start(pdev, 0),
	105	+ pci_resource_len(pdev, 0));
105	106
106	107	return drmm_add_action_or_reset(dev, ast_mm_release, NULL);
107	108	}

drivers/gpu/drm/ast/ast_mode.c+3−2

@@ -1106,6 +1106,7 @@ static const struct drm_mode_config_funcs ast_mode_config_funcs = { · 1105 unmodified lines
1106	1106	int ast_mode_config_init(struct ast_private *ast)
1107	1107	{
1108	1108	struct drm_device *dev = &ast->base;
	1109	+ struct pci_dev *pdev = to_pci_dev(dev->dev);
1109	1110	int ret;
1110	1111
1111	1112	ret = ast_cursor_init(ast);
@@ -1121,7 +1122,7 @@ int ast_mode_config_init(struct ast_private *ast) · 9 unmodified lines
1121	1122	dev->mode_config.min_height = 0;
1122	1123	dev->mode_config.preferred_depth = 24;
1123	1124	dev->mode_config.prefer_shadow = 1;
1124		− dev->mode_config.fb_base = pci_resource_start(dev->pdev, 0);
	1125	+ dev->mode_config.fb_base = pci_resource_start(pdev, 0);
1125	1126
1126	1127	if (ast->chip == AST2100 \|\|
1127	1128	ast->chip == AST2200 \|\|
@@ -1258,7 +1259,7 @@ static struct ast_i2c_chan ast_i2c_create(struct drm_device dev) · 130 unmodified lines
1258	1259
1259	1260	i2c->adapter.owner = THIS_MODULE;
1260	1261	i2c->adapter.class = I2C_CLASS_DDC;
1261		− i2c->adapter.dev.parent = &dev->pdev->dev;
	1262	+ i2c->adapter.dev.parent = dev->dev;
1262	1263	i2c->dev = dev;
1263	1264	i2c_set_adapdata(&i2c->adapter, i2c);
1264	1265	snprintf(i2c->adapter.name, sizeof(i2c->adapter.name),

drivers/gpu/drm/ast/ast_post.c+5−3

@@ -71,6 +71,7 @@ static void · 70 unmodified lines
71	71	ast_set_def_ext_reg(struct drm_device *dev)
72	72	{
73	73	struct ast_private *ast = to_ast_private(dev);
	74	+ struct pci_dev *pdev = to_pci_dev(dev->dev);
74	75	u8 i, index, reg;
75	76	const u8 *ext_reg_info;
76	77
@@ -80,7 +81,7 @@ ast_set_def_ext_reg(struct drm_device *dev) · 3 unmodified lines
80	81
81	82	if (ast->chip == AST2300 \|\| ast->chip == AST2400 \|\|
82	83	ast->chip == AST2500) {
83		− if (dev->pdev->revision >= 0x20)
	84	+ if (pdev->revision >= 0x20)
84	85	ext_reg_info = extreginfo_ast2300;
85	86	else
86	87	ext_reg_info = extreginfo_ast2300a0;
@@ -366,11 +367,12 @@ static void ast_init_dram_reg(struct drm_device *dev) · 279 unmodified lines
366	367	void ast_post_gpu(struct drm_device *dev)
367	368	{
368	369	struct ast_private *ast = to_ast_private(dev);
	370	+ struct pci_dev *pdev = to_pci_dev(dev->dev);
369	371	u32 reg;
370	372
371		− pci_read_config_dword(dev->pdev, 0x04, &reg);
	373	+ pci_read_config_dword(pdev, 0x04, &reg);
372	374	reg \|= 0x3;
373		− pci_write_config_dword(dev->pdev, 0x04, reg);
	375	+ pci_write_config_dword(pdev, 0x04, reg);
374	376
375	377	ast_enable_vga(dev);
376	378	ast_open_key(ast);

drivers/gpu/drm/bochs/bochs_drv.c+0−1

@@ -121,7 +121,6 @@ static int bochs_pci_probe(struct pci_dev *pdev, · 120 unmodified lines
121	121	if (ret)
122	122	goto err_free_dev;
123	123
124		− dev->pdev = pdev;
125	124	pci_set_drvdata(pdev, dev);
126	125
127	126	ret = bochs_load(dev);

drivers/gpu/drm/bochs/bochs_hw.c+2−2

@@ -110,7 +110,7 @@ int bochs_hw_load_edid(struct bochs_device *bochs) · 109 unmodified lines
110	110	int bochs_hw_init(struct drm_device *dev)
111	111	{
112	112	struct bochs_device *bochs = dev->dev_private;
113		− struct pci_dev *pdev = dev->pdev;
	113	+ struct pci_dev *pdev = to_pci_dev(dev->dev);
114	114	unsigned long addr, size, mem, ioaddr, iosize;
115	115	u16 id;
116	116
@@ -201,7 +201,7 @@ void bochs_hw_fini(struct drm_device *dev) · 84 unmodified lines
201	201	release_region(VBE_DISPI_IOPORT_INDEX, 2);
202	202	if (bochs->fb_map)
203	203	iounmap(bochs->fb_map);
204		− pci_release_regions(dev->pdev);
	204	+ pci_release_regions(to_pci_dev(dev->dev));
205	205	kfree(bochs->edid);
206	206	}
207	207

drivers/gpu/drm/drm_agpsupport.c+23−44

@@ -45,13 +45,9 @@ · 44 unmodified lines
45	45
46	46	#include "drm_legacy.h"
47	47
48		−/**
	48	+/*
49	49	* Get AGP information.
50	50	*
51		− * \param inode device inode.
52		− * \param file_priv DRM file private.
53		− * \param cmd command.
54		− * \param arg pointer to a (output) drm_agp_info structure.
55	51	* \return zero on success or a negative number on failure.
56	52	*
57	53	* Verifies the AGP device has been initialized and acquired and fills in the
@@ -92,7 +88,7 @@ int drm_agp_info_ioctl(struct drm_device dev, void data, · 34 unmodified lines
92	88	return 0;
93	89	}
94	90
95		−/**
	91	+/*
96	92	* Acquire the AGP device.
97	93	*
98	94	* \param dev DRM device that is to acquire AGP.
@@ -103,11 +99,13 @@ int drm_agp_info_ioctl(struct drm_device dev, void data, · 4 unmodified lines
103	99	*/
104	100	int drm_agp_acquire(struct drm_device *dev)
105	101	{
	102	+ struct pci_dev *pdev = to_pci_dev(dev->dev);
	103	+
106	104	if (!dev->agp)
107	105	return -ENODEV;
108	106	if (dev->agp->acquired)
109	107	return -EBUSY;
110		− dev->agp->bridge = agp_backend_acquire(dev->pdev);
	108	+ dev->agp->bridge = agp_backend_acquire(pdev);
111	109	if (!dev->agp->bridge)
112	110	return -ENODEV;
113	111	dev->agp->acquired = 1;
@@ -115,13 +113,9 @@ int drm_agp_acquire(struct drm_device *dev) · 1 unmodified line
115	113	}
116	114	EXPORT_SYMBOL(drm_agp_acquire);
117	115
118		−/**
	116	+/*
119	117	* Acquire the AGP device (ioctl).
120	118	*
121		− * \param inode device inode.
122		− * \param file_priv DRM file private.
123		− * \param cmd command.
124		− * \param arg user argument.
125	119	* \return zero on success or a negative number on failure.
126	120	*
127	121	* Verifies the AGP device hasn't been acquired before and calls
@@ -133,7 +127,7 @@ int drm_agp_acquire_ioctl(struct drm_device dev, void data, · 5 unmodified lines
133	127	return drm_agp_acquire((struct drm_device *) file_priv->minor->dev);
134	128	}
135	129
136		−/**
	130	+/*
137	131	* Release the AGP device.
138	132	*
139	133	* \param dev DRM device that is to release AGP.
@@ -157,7 +151,7 @@ int drm_agp_release_ioctl(struct drm_device dev, void data, · 17 unmodified lines
157	151	return drm_agp_release(dev);
158	152	}
159	153
160		−/**
	154	+/*
161	155	* Enable the AGP bus.
162	156	*
163	157	* \param dev DRM device that has previously acquired AGP.
@@ -187,13 +181,9 @@ int drm_agp_enable_ioctl(struct drm_device dev, void data, · 23 unmodified lines
187	181	return drm_agp_enable(dev, *mode);
188	182	}
189	183
190		−/**
	184	+/*
191	185	* Allocate AGP memory.
192	186	*
193		− * \param inode device inode.
194		− * \param file_priv file private pointer.
195		− * \param cmd command.
196		− * \param arg pointer to a drm_agp_buffer structure.
197	187	* \return zero on success or a negative number on failure.
198	188	*
199	189	* Verifies the AGP device is present and has been acquired, allocates the
@@ -242,7 +232,7 @@ int drm_agp_alloc_ioctl(struct drm_device dev, void data, · 42 unmodified lines
242	232	return drm_agp_alloc(dev, request);
243	233	}
244	234
245		−/**
	235	+/*
246	236	* Search for the AGP memory entry associated with a handle.
247	237	*
248	238	* \param dev DRM device structure.
@@ -263,13 +253,9 @@ static struct drm_agp_mem drm_agp_lookup_entry(struct drm_device dev, · 14 unmodified lines
263	253	return NULL;
264	254	}
265	255
266		−/**
	256	+/*
267	257	* Unbind AGP memory from the GATT (ioctl).
268	258	*
269		− * \param inode device inode.
270		− * \param file_priv DRM file private.
271		− * \param cmd command.
272		− * \param arg pointer to a drm_agp_binding structure.
273	259	* \return zero on success or a negative number on failure.
274	260	*
275	261	* Verifies the AGP device is present and acquired, looks-up the AGP memory
@@ -285,7 +271,7 @@ int drm_agp_unbind(struct drm_device dev, struct drm_agp_binding request) · 9 unmodified lines
285	271	entry = drm_agp_lookup_entry(dev, request->handle);
286	272	if (!entry \|\| !entry->bound)
287	273	return -EINVAL;
288		− ret = drm_unbind_agp(entry->memory);
	274	+ ret = agp_unbind_memory(entry->memory);
289	275	if (ret == 0)
290	276	entry->bound = 0;
291	277	return ret;
@@ -301,13 +287,9 @@ int drm_agp_unbind_ioctl(struct drm_device dev, void data, · 9 unmodified lines
301	287	return drm_agp_unbind(dev, request);
302	288	}
303	289
304		−/**
	290	+/*
305	291	* Bind AGP memory into the GATT (ioctl)
306	292	*
307		− * \param inode device inode.
308		− * \param file_priv DRM file private.
309		− * \param cmd command.
310		− * \param arg pointer to a drm_agp_binding structure.
311	293	* \return zero on success or a negative number on failure.
312	294	*
313	295	* Verifies the AGP device is present and has been acquired and that no memory
@@ -326,7 +308,7 @@ int drm_agp_bind(struct drm_device dev, struct drm_agp_binding request) · 12 unmodified lines
326	308	if (!entry \|\| entry->bound)
327	309	return -EINVAL;
328	310	page = DIV_ROUND_UP(request->offset, PAGE_SIZE);
329		− retcode = drm_bind_agp(entry->memory, page);
	311	+ retcode = agp_bind_memory(entry->memory, page);
330	312	if (retcode)
331	313	return retcode;
332	314	entry->bound = dev->agp->base + (page << PAGE_SHIFT);
@@ -345,13 +327,9 @@ int drm_agp_bind_ioctl(struct drm_device dev, void data, · 12 unmodified lines
345	327	return drm_agp_bind(dev, request);
346	328	}
347	329
348		−/**
	330	+/*
349	331	* Free AGP memory (ioctl).
350	332	*
351		− * \param inode device inode.
352		− * \param file_priv DRM file private.
353		− * \param cmd command.
354		− * \param arg pointer to a drm_agp_buffer structure.
355	333	* \return zero on success or a negative number on failure.
356	334	*
357	335	* Verifies the AGP device is present and has been acquired and looks up the
@@ -369,11 +347,11 @@ int drm_agp_free(struct drm_device dev, struct drm_agp_buffer request) · 11 unmodified lines
369	347	if (!entry)
370	348	return -EINVAL;
371	349	if (entry->bound)
372		− drm_unbind_agp(entry->memory);
	350	+ agp_unbind_memory(entry->memory);
373	351
374	352	list_del(&entry->head);
375	353
376		− drm_free_agp(entry->memory, entry->pages);
	354	+ agp_free_memory(entry->memory);
377	355	kfree(entry);
378	356	return 0;
379	357	}
@@ -388,7 +366,7 @@ int drm_agp_free_ioctl(struct drm_device dev, void data, · 8 unmodified lines
388	366	return drm_agp_free(dev, request);
389	367	}
390	368
391		−/**
	369	+/*
392	370	* Initialize the AGP resources.
393	371	*
394	372	* \return pointer to a drm_agp_head structure.
@@ -402,14 +380,15 @@ int drm_agp_free_ioctl(struct drm_device dev, void data, · 7 unmodified lines
402	380	*/
403	381	struct drm_agp_head drm_agp_init(struct drm_device dev)
404	382	{
	383	+ struct pci_dev *pdev = to_pci_dev(dev->dev);
405	384	struct drm_agp_head *head = NULL;
406	385
407	386	head = kzalloc(sizeof(*head), GFP_KERNEL);
408	387	if (!head)
409	388	return NULL;
410		− head->bridge = agp_find_bridge(dev->pdev);
	389	+ head->bridge = agp_find_bridge(pdev);
411	390	if (!head->bridge) {
412		− head->bridge = agp_backend_acquire(dev->pdev);
	391	+ head->bridge = agp_backend_acquire(pdev);
413	392	if (!head->bridge) {
414	393	kfree(head);
415	394	return NULL;
@@ -453,8 +432,8 @@ void drm_legacy_agp_clear(struct drm_device *dev) · 37 unmodified lines
453	432
454	433	list_for_each_entry_safe(entry, tempe, &dev->agp->memory, head) {
455	434	if (entry->bound)
456		− drm_unbind_agp(entry->memory);
457		− drm_free_agp(entry->memory, entry->pages);
	435	+ agp_unbind_memory(entry->memory);
	436	+ agp_free_memory(entry->memory);
458	437	kfree(entry);
459	438	}
460	439	INIT_LIST_HEAD(&dev->agp->memory);

drivers/gpu/drm/drm_bufs.c+2−2

@@ -326,7 +326,7 @@ static int drm_addmap_core(struct drm_device *dev, resource_size_t offset, · 325 unmodified lines
326	326	* As we're limiting the address to 2^32-1 (or less),
327	327	* casting it down to 32 bits is no problem, but we
328	328	* need to point to a 64bit variable first. */
329		− map->handle = dma_alloc_coherent(&dev->pdev->dev,
	329	+ map->handle = dma_alloc_coherent(dev->dev,
330	330	map->size,
331	331	&map->offset,
332	332	GFP_KERNEL);
@@ -556,7 +556,7 @@ int drm_legacy_rmmap_locked(struct drm_device dev, struct drm_local_map map) · 223 unmodified lines
556	556	case _DRM_SCATTER_GATHER:
557	557	break;
558	558	case _DRM_CONSISTENT:
559		− dma_free_coherent(&dev->pdev->dev,
	559	+ dma_free_coherent(dev->dev,
560	560	map->size,
561	561	map->handle,
562	562	map->offset);

drivers/gpu/drm/drm_cache.c+33−0

@@ -30,6 +30,8 @@ · 29 unmodified lines
30	30
31	31	#include <linux/export.h>
32	32	#include <linux/highmem.h>
	33	+#include <linux/mem_encrypt.h>
	34	+#include <xen/xen.h>
33	35
34	36	#include <drm/drm_cache.h>
35	37
@@ -176,3 +178,34 @@ drm_clflush_virt_range(void *addr, unsigned long length) · 140 unmodified lines
176	178	#endif
177	179	}
178	180	EXPORT_SYMBOL(drm_clflush_virt_range);
	181	+
	182	+bool drm_need_swiotlb(int dma_bits)
	183	+{
	184	+ struct resource *tmp;
	185	+ resource_size_t max_iomem = 0;
	186	+
	187	+ /*
	188	+ * Xen paravirtual hosts require swiotlb regardless of requested dma
	189	+ * transfer size.
	190	+ *
	191	+ * NOTE: Really, what it requires is use of the dma_alloc_coherent
	192	+ * allocator used in ttm_dma_populate() instead of
	193	+ * ttm_populate_and_map_pages(), which bounce buffers so much in
	194	+ * Xen it leads to swiotlb buffer exhaustion.
	195	+ */
	196	+ if (xen_pv_domain())
	197	+ return true;
	198	+
	199	+ /*
	200	+ * Enforce dma_alloc_coherent when memory encryption is active as well
	201	+ * for the same reasons as for Xen paravirtual hosts.
	202	+ */
	203	+ if (mem_encrypt_active())
	204	+ return true;
	205	+
	206	+ for (tmp = iomem_resource.child; tmp; tmp = tmp->sibling)
	207	+ max_iomem = max(max_iomem, tmp->end);
	208	+
	209	+ return max_iomem > ((u64)1 << dma_bits);
	210	+}
	211	+EXPORT_SYMBOL(drm_need_swiotlb);

drivers/gpu/drm/drm_dp_helper.c+2−1

@@ -954,7 +954,7 @@ EXPORT_SYMBOL(drm_dp_downstream_444_to_420_conversion); · 953 unmodified lines
954	954	* RGB->YCbCr conversion capability
955	955	* @dpcd: DisplayPort configuration data
956	956	* @port_cap: downstream facing port capabilities
957		− * @colorspc: Colorspace for which conversion cap is sought
	957	+ * @color_spc: Colorspace for which conversion cap is sought
958	958	*
959	959	* Returns: whether the downstream facing port can convert RGB->YCbCr for a given
960	960	* colorspace.
@@ -2671,6 +2671,7 @@ EXPORT_SYMBOL(drm_dp_get_pcon_max_frl_bw); · 1710 unmodified lines
2671	2671	/**
2672	2672	* drm_dp_pcon_frl_prepare() - Prepare PCON for FRL.
2673	2673	* @aux: DisplayPort AUX channel
	2674	+ * @enable_frl_ready_hpd: Configure DP_PCON_ENABLE_HPD_READY.
2674	2675	*
2675	2676	* Returns 0 if success, else returns negative error code.
2676	2677	*/

drivers/gpu/drm/drm_dp_mst_topology.c+1−1

@@ -2751,7 +2751,7 @@ static void drm_dp_mst_link_probe_work(struct work_struct *work) · 2750 unmodified lines
2751	2751	drm_dp_mst_topology_put_mstb(mstb);
2752	2752
2753	2753	mutex_unlock(&mgr->probe_lock);
2754		− if (ret)
	2754	+ if (ret > 0)
2755	2755	drm_kms_helper_hotplug_event(dev);
2756	2756	}
2757	2757

drivers/gpu/drm/drm_drv.c+3−0

@@ -469,6 +469,9 @@ void drm_dev_unplug(struct drm_device *dev) · 468 unmodified lines
469	469	synchronize_srcu(&drm_unplug_srcu);
470	470
471	471	drm_dev_unregister(dev);
	472	+
	473	+ /* Clear all CPU mappings pointing to this device */
	474	+ unmap_mapping_range(dev->anon_inode->i_mapping, 0, 0, 1);
472	475	}
473	476	EXPORT_SYMBOL(drm_dev_unplug);
474	477

drivers/gpu/drm/drm_edid.c+6−1

@@ -32,6 +32,7 @@ · 31 unmodified lines
32	32	#include <linux/i2c.h>
33	33	#include <linux/kernel.h>
34	34	#include <linux/module.h>
	35	+#include <linux/pci.h>
35	36	#include <linux/slab.h>
36	37	#include <linux/vga_switcheroo.h>
37	38
@@ -2075,9 +2076,13 @@ EXPORT_SYMBOL(drm_get_edid); · 2037 unmodified lines
2075	2076	struct edid drm_get_edid_switcheroo(struct drm_connector connector,
2076	2077	struct i2c_adapter *adapter)
2077	2078	{
2078		− struct pci_dev *pdev = connector->dev->pdev;
	2079	+ struct drm_device *dev = connector->dev;
	2080	+ struct pci_dev *pdev = to_pci_dev(dev->dev);
2079	2081	struct edid *edid;
2080	2082
	2083	+ if (drm_WARN_ON_ONCE(dev, !dev_is_pci(dev->dev)))
	2084	+ return NULL;
	2085	+
2081	2086	vga_switcheroo_lock_ddc(pdev);
2082	2087	edid = drm_get_edid(connector, adapter);
2083	2088	vga_switcheroo_unlock_ddc(pdev);

drivers/gpu/drm/drm_file.c+2−3

@@ -239,9 +239,6 @@ static void drm_events_release(struct drm_file *file_priv) · 238 unmodified lines
239	239	* before calling this.
240	240	*
241	241	* If NULL is passed, this is a no-op.
242		− *
243		− * RETURNS:
244		− * 0 on success, or error code on failure.
245	242	*/
246	243	void drm_file_free(struct drm_file *file)
247	244	{
@@ -370,6 +367,7 @@ static int drm_open_helper(struct file filp, struct drm_minor minor) · 122 unmodified lines
370	367	list_add(&priv->lhead, &dev->filelist);
371	368	mutex_unlock(&dev->filelist_mutex);
372	369
	370	+#ifdef CONFIG_DRM_LEGACY
373	371	#ifdef __alpha__
374	372	/*
375	373	* Default the hose
@@ -389,6 +387,7 @@ static int drm_open_helper(struct file filp, struct drm_minor minor) · 13 unmodified lines
389	387	dev->hose = b->sysdata;
390	388	}
391	389	}
	390	+#endif
392	391	#endif
393	392
394	393	return 0;

drivers/gpu/drm/drm_gem.c+10−9

@@ -1068,20 +1068,17 @@ int drm_gem_mmap_obj(struct drm_gem_object *obj, unsigned long obj_size, · 1067 unmodified lines
1068	1068	drm_gem_object_get(obj);
1069	1069
1070	1070	vma->vm_private_data = obj;
	1071	+ vma->vm_ops = obj->funcs->vm_ops;
1071	1072
1072	1073	if (obj->funcs->mmap) {
1073	1074	ret = obj->funcs->mmap(obj, vma);
1074		− if (ret) {
1075		− drm_gem_object_put(obj);
1076		− return ret;
1077		− }
	1075	+ if (ret)
	1076	+ goto err_drm_gem_object_put;
1078	1077	WARN_ON(!(vma->vm_flags & VM_DONTEXPAND));
1079	1078	} else {
1080		− if (obj->funcs->vm_ops)
1081		− vma->vm_ops = obj->funcs->vm_ops;
1082		− else {
1083		− drm_gem_object_put(obj);
1084		− return -EINVAL;
	1079	+ if (!vma->vm_ops) {
	1080	+ ret = -EINVAL;
	1081	+ goto err_drm_gem_object_put;
1085	1082	}
1086	1083
1087	1084	vma->vm_flags \|= VM_IO \| VM_PFNMAP \| VM_DONTEXPAND \| VM_DONTDUMP;
@@ -1090,6 +1087,10 @@ int drm_gem_mmap_obj(struct drm_gem_object *obj, unsigned long obj_size, · 2 unmodified lines
1090	1087	}
1091	1088
1092	1089	return 0;
	1090	+
	1091	+err_drm_gem_object_put:
	1092	+ drm_gem_object_put(obj);
	1093	+ return ret;
1093	1094	}
1094	1095	EXPORT_SYMBOL(drm_gem_mmap_obj);
1095	1096

drivers/gpu/drm/drm_irq.c+7−5

@@ -122,7 +122,7 @@ int drm_irq_install(struct drm_device *dev, int irq) · 121 unmodified lines
122	122	dev->driver->irq_preinstall(dev);
123	123
124	124	/* PCI devices require shared interrupts. */
125		− if (dev->pdev)
	125	+ if (dev_is_pci(dev->dev))
126	126	sh_flags = IRQF_SHARED;
127	127
128	128	ret = request_irq(irq, dev->driver->irq_handler,
@@ -140,7 +140,7 @@ int drm_irq_install(struct drm_device *dev, int irq) · 11 unmodified lines
140	140	if (ret < 0) {
141	141	dev->irq_enabled = false;
142	142	if (drm_core_check_feature(dev, DRIVER_LEGACY))
143		− vga_client_register(dev->pdev, NULL, NULL, NULL);
	143	+ vga_client_register(to_pci_dev(dev->dev), NULL, NULL, NULL);
144	144	free_irq(irq, dev);
145	145	} else {
146	146	dev->irq = irq;
@@ -203,7 +203,7 @@ int drm_irq_uninstall(struct drm_device *dev) · 56 unmodified lines
203	203	DRM_DEBUG("irq=%d\n", dev->irq);
204	204
205	205	if (drm_core_check_feature(dev, DRIVER_LEGACY))
206		− vga_client_register(dev->pdev, NULL, NULL, NULL);
	206	+ vga_client_register(to_pci_dev(dev->dev), NULL, NULL, NULL);
207	207
208	208	if (dev->driver->irq_uninstall)
209	209	dev->driver->irq_uninstall(dev);
@@ -252,6 +252,7 @@ int drm_legacy_irq_control(struct drm_device dev, void data, · 42 unmodified lines
252	252	{
253	253	struct drm_control *ctl = data;
254	254	int ret = 0, irq;
	255	+ struct pci_dev *pdev;
255	256
256	257	/* if we haven't irq we fallback for compatibility reasons -
257	258	* this used to be a separate function in drm_dma.h
@@ -262,12 +263,13 @@ int drm_legacy_irq_control(struct drm_device dev, void data, · 4 unmodified lines
262	263	if (!drm_core_check_feature(dev, DRIVER_LEGACY))
263	264	return 0;
264	265	/* UMS was only ever supported on pci devices. */
265		− if (WARN_ON(!dev->pdev))
	266	+ if (WARN_ON(!dev_is_pci(dev->dev)))
266	267	return -EINVAL;
267	268
268	269	switch (ctl->func) {
269	270	case DRM_INST_HANDLER:
270		− irq = dev->pdev->irq;
	271	+ pdev = to_pci_dev(dev->dev);
	272	+ irq = pdev->irq;
271	273
272	274	if (dev->if_version < DRM_IF_VERSION(1, 2) &&
273	275	ctl->irq != irq)

drivers/gpu/drm/drm_legacy.h+1−1

@@ -127,7 +127,7 @@ static inline void drm_legacy_master_rmmaps(struct drm_device *dev, · 126 unmodified lines
127	127	static inline void drm_legacy_rmmaps(struct drm_device *dev) {}
128	128	#endif
129	129
130		−#if IS_ENABLED(CONFIG_DRM_VM) && IS_ENABLED(CONFIG_DRM_LEGACY)
	130	+#if IS_ENABLED(CONFIG_DRM_LEGACY)
131	131	void drm_legacy_vma_flush(struct drm_device *d);
132	132	#else
133	133	static inline void drm_legacy_vma_flush(struct drm_device *d)

drivers/gpu/drm/drm_memory.c+0−51

@@ -37,7 +37,6 @@ · 36 unmodified lines
37	37	#include <linux/highmem.h>
38	38	#include <linux/pci.h>
39	39	#include <linux/vmalloc.h>
40		−#include <xen/xen.h>
41	40
42	41	#include <drm/drm_agpsupport.h>
43	42	#include <drm/drm_cache.h>
@@ -100,24 +99,6 @@ static void *agp_remap(unsigned long offset, unsigned long size, · 56 unmodified lines
100	99	return addr;
101	100	}
102	101
103		−/** Wrapper around agp_free_memory() */
104		−void drm_free_agp(struct agp_memory *handle, int pages)
105		−{
106		− agp_free_memory(handle);
107		−}
108		−
109		−/** Wrapper around agp_bind_memory() */
110		−int drm_bind_agp(struct agp_memory *handle, unsigned int start)
111		−{
112		− return agp_bind_memory(handle, start);
113		−}
114		−
115		−/** Wrapper around agp_unbind_memory() */
116		−int drm_unbind_agp(struct agp_memory *handle)
117		−{
118		− return agp_unbind_memory(handle);
119		−}
120		−
121	102	#else /* CONFIG_AGP */
122	103	static inline void *agp_remap(unsigned long offset, unsigned long size,
123	104	struct drm_device *dev)
@@ -156,35 +137,3 @@ void drm_legacy_ioremapfree(struct drm_local_map map, struct drm_device dev) · 32 unmodified lines
156	137	iounmap(map->handle);
157	138	}
158	139	EXPORT_SYMBOL(drm_legacy_ioremapfree);
159		−
160		−bool drm_need_swiotlb(int dma_bits)
161		−{
162		− struct resource *tmp;
163		− resource_size_t max_iomem = 0;
164		−
165		− /*
166		− * Xen paravirtual hosts require swiotlb regardless of requested dma
167		− * transfer size.
168		− *
169		− * NOTE: Really, what it requires is use of the dma_alloc_coherent
170		− * allocator used in ttm_dma_populate() instead of
171		− * ttm_populate_and_map_pages(), which bounce buffers so much in
172		− * Xen it leads to swiotlb buffer exhaustion.
173		− */
174		− if (xen_pv_domain())
175		− return true;
176		−
177		− /*
178		− * Enforce dma_alloc_coherent when memory encryption is active as well
179		− * for the same reasons as for Xen paravirtual hosts.
180		− */
181		− if (mem_encrypt_active())
182		− return true;
183		−
184		− for (tmp = iomem_resource.child; tmp; tmp = tmp->sibling) {
185		− max_iomem = max(max_iomem, tmp->end);
186		− }
187		−
188		− return max_iomem > ((u64)1 << dma_bits);
189		−}
190		−EXPORT_SYMBOL(drm_need_swiotlb);

drivers/gpu/drm/drm_modes.c+2−2

@@ -762,7 +762,7 @@ int drm_mode_vrefresh(const struct drm_display_mode *mode) · 761 unmodified lines
762	762	if (mode->htotal == 0 \|\| mode->vtotal == 0)
763	763	return 0;
764	764
765		− num = mode->clock * 1000;
	765	+ num = mode->clock;
766	766	den = mode->htotal * mode->vtotal;
767	767
768	768	if (mode->flags & DRM_MODE_FLAG_INTERLACE)
@@ -772,7 +772,7 @@ int drm_mode_vrefresh(const struct drm_display_mode *mode) · 3 unmodified lines
772	772	if (mode->vscan > 1)
773	773	den *= mode->vscan;
774	774
775		− return DIV_ROUND_CLOSEST(num, den);
	775	+ return DIV_ROUND_CLOSEST_ULL(mul_u32_u32(num, 1000), den);
776	776	}
777	777	EXPORT_SYMBOL(drm_mode_vrefresh);
778	778

drivers/gpu/drm/drm_pci.c+15−11

@@ -70,7 +70,7 @@ drm_dma_handle_t drm_pci_alloc(struct drm_device dev, size_t size, size_t ali · 69 unmodified lines
70	70	return NULL;
71	71
72	72	dmah->size = size;
73		− dmah->vaddr = dma_alloc_coherent(&dev->pdev->dev, size,
	73	+ dmah->vaddr = dma_alloc_coherent(dev->dev, size,
74	74	&dmah->busaddr,
75	75	GFP_KERNEL);
76	76
@@ -93,7 +93,7 @@ EXPORT_SYMBOL(drm_pci_alloc); · 16 unmodified lines
93	93	*/
94	94	void drm_pci_free(struct drm_device * dev, drm_dma_handle_t * dmah)
95	95	{
96		− dma_free_coherent(&dev->pdev->dev, dmah->size, dmah->vaddr,
	96	+ dma_free_coherent(dev->dev, dmah->size, dmah->vaddr,
97	97	dmah->busaddr);
98	98	kfree(dmah);
99	99	}
@@ -112,16 +112,18 @@ static int drm_get_pci_domain(struct drm_device *dev) · 12 unmodified lines
112	112	return 0;
113	113	#endif /* __alpha__ */
114	114
115		− return pci_domain_nr(dev->pdev->bus);
	115	+ return pci_domain_nr(to_pci_dev(dev->dev)->bus);
116	116	}
117	117
118	118	int drm_pci_set_busid(struct drm_device dev, struct drm_master master)
119	119	{
	120	+ struct pci_dev *pdev = to_pci_dev(dev->dev);
	121	+
120	122	master->unique = kasprintf(GFP_KERNEL, "pci:%04x:%02x:%02x.%d",
121	123	drm_get_pci_domain(dev),
122		− dev->pdev->bus->number,
123		− PCI_SLOT(dev->pdev->devfn),
124		− PCI_FUNC(dev->pdev->devfn));
	124	+ pdev->bus->number,
	125	+ PCI_SLOT(pdev->devfn),
	126	+ PCI_FUNC(pdev->devfn));
125	127	if (!master->unique)
126	128	return -ENOMEM;
127	129
@@ -131,12 +133,14 @@ int drm_pci_set_busid(struct drm_device dev, struct drm_master master) · 3 unmodified lines
131	133
132	134	static int drm_pci_irq_by_busid(struct drm_device dev, struct drm_irq_busid p)
133	135	{
	136	+ struct pci_dev *pdev = to_pci_dev(dev->dev);
	137	+
134	138	if ((p->busnum >> 8) != drm_get_pci_domain(dev) \|\|
135		− (p->busnum & 0xff) != dev->pdev->bus->number \|\|
136		− p->devnum != PCI_SLOT(dev->pdev->devfn) \|\| p->funcnum != PCI_FUNC(dev->pdev->devfn))
	139	+ (p->busnum & 0xff) != pdev->bus->number \|\|
	140	+ p->devnum != PCI_SLOT(pdev->devfn) \|\| p->funcnum != PCI_FUNC(pdev->devfn))
137	141	return -EINVAL;
138	142
139		− p->irq = dev->pdev->irq;
	143	+ p->irq = pdev->irq;
140	144
141	145	DRM_DEBUG("%d:%d:%d => IRQ %d\n", p->busnum, p->devnum, p->funcnum,
142	146	p->irq);
@@ -164,7 +168,7 @@ int drm_legacy_irq_by_busid(struct drm_device dev, void data, · 21 unmodified lines
164	168	return -EOPNOTSUPP;
165	169
166	170	/* UMS was only ever support on PCI devices. */
167		− if (WARN_ON(!dev->pdev))
	171	+ if (WARN_ON(!dev_is_pci(dev->dev)))
168	172	return -EINVAL;
169	173
170	174	if (!drm_core_check_feature(dev, DRIVER_HAVE_IRQ))
@@ -188,7 +192,7 @@ void drm_pci_agp_destroy(struct drm_device *dev) · 17 unmodified lines
188	192	static void drm_pci_agp_init(struct drm_device *dev)
189	193	{
190	194	if (drm_core_check_feature(dev, DRIVER_USE_AGP)) {
191		− if (pci_find_capability(dev->pdev, PCI_CAP_ID_AGP))
	195	+ if (pci_find_capability(to_pci_dev(dev->dev), PCI_CAP_ID_AGP))
192	196	dev->agp = drm_agp_init(dev);
193	197	if (dev->agp) {
194	198	dev->agp->agp_mtrr = arch_phys_wc_add(

drivers/gpu/drm/drm_prime.c+2−0

@@ -717,6 +717,8 @@ int drm_gem_prime_mmap(struct drm_gem_object obj, struct vm_area_struct vma) · 716 unmodified lines
717	717	vma->vm_pgoff += drm_vma_node_start(&obj->vma_node);
718	718
719	719	if (obj->funcs && obj->funcs->mmap) {
	720	+ vma->vm_ops = obj->funcs->vm_ops;
	721	+
720	722	ret = obj->funcs->mmap(obj, vma);
721	723	if (ret)
722	724	return ret;

drivers/gpu/drm/drm_vblank.c+1−1

@@ -74,7 +74,7 @@ · 73 unmodified lines
74	74	* \|↓↓↓↓↓↓↓↓↓↓↓↓↓↓↓↓↓↓↓↓↓↓↓↓↓↓↓↓↓↓↓↓↓↓↓↓↓↓↓↓\| updates the
75	75	* \| \| frame as it
76	76	* \| \| travels down
77		− * \| \| ("sacn out")
	77	+ * \| \| ("scan out")
78	78	* \| Old frame \|
79	79	* \| \|
80	80	* \| \|

drivers/gpu/drm/drm_vm.c+1−1

@@ -278,7 +278,7 @@ static void drm_vm_shm_close(struct vm_area_struct *vma) · 277 unmodified lines
278	278	case _DRM_SCATTER_GATHER:
279	279	break;
280	280	case _DRM_CONSISTENT:
281		− dma_free_coherent(&dev->pdev->dev,
	281	+ dma_free_coherent(dev->dev,
282	282	map->size,
283	283	map->handle,
284	284	map->offset);

drivers/gpu/drm/gma500/cdv_device.c+19−11

@@ -95,13 +95,14 @@ static u32 cdv_get_max_backlight(struct drm_device *dev) · 94 unmodified lines
95	95	static int cdv_get_brightness(struct backlight_device *bd)
96	96	{
97	97	struct drm_device *dev = bl_get_data(bd);
	98	+ struct pci_dev *pdev = to_pci_dev(dev->dev);
98	99	u32 val = REG_READ(BLC_PWM_CTL) & BACKLIGHT_DUTY_CYCLE_MASK;
99	100
100	101	if (cdv_backlight_combination_mode(dev)) {
101	102	u8 lbpc;
102	103
103	104	val &= ~1;
104		− pci_read_config_byte(dev->pdev, 0xF4, &lbpc);
	105	+ pci_read_config_byte(pdev, 0xF4, &lbpc);
105	106	val *= lbpc;
106	107	}
107	108	return (val * 100)/cdv_get_max_backlight(dev);
@@ -111,6 +112,7 @@ static int cdv_get_brightness(struct backlight_device *bd) · 3 unmodified lines
111	112	static int cdv_set_brightness(struct backlight_device *bd)
112	113	{
113	114	struct drm_device *dev = bl_get_data(bd);
	115	+ struct pci_dev *pdev = to_pci_dev(dev->dev);
114	116	int level = bd->props.brightness;
115	117	u32 blc_pwm_ctl;
116	118
@@ -128,7 +130,7 @@ static int cdv_set_brightness(struct backlight_device *bd) · 11 unmodified lines
128	130	lbpc = level * 0xfe / max + 1;
129	131	level /= lbpc;
130	132
131		− pci_write_config_byte(dev->pdev, 0xF4, lbpc);
	133	+ pci_write_config_byte(pdev, 0xF4, lbpc);
132	134	}
133	135
134	136	blc_pwm_ctl = REG_READ(BLC_PWM_CTL) & ~BACKLIGHT_DUTY_CYCLE_MASK;
@@ -205,8 +207,9 @@ static inline void CDV_MSG_WRITE32(int domain, uint port, uint offset, · 70 unmodified lines
205	207	static void cdv_init_pm(struct drm_device *dev)
206	208	{
207	209	struct drm_psb_private *dev_priv = dev->dev_private;
	210	+ struct pci_dev *pdev = to_pci_dev(dev->dev);
208	211	u32 pwr_cnt;
209		− int domain = pci_domain_nr(dev->pdev->bus);
	212	+ int domain = pci_domain_nr(pdev->bus);
210	213	int i;
211	214
212	215	dev_priv->apm_base = CDV_MSG_READ32(domain, PSB_PUNIT_PORT,
@@ -234,6 +237,8 @@ static void cdv_init_pm(struct drm_device *dev) · 21 unmodified lines
234	237
235	238	static void cdv_errata(struct drm_device *dev)
236	239	{
	240	+ struct pci_dev *pdev = to_pci_dev(dev->dev);
	241	+
237	242	/* Disable bonus launch.
238	243	* CPU and GPU competes for memory and display misses updates and
239	244	* flickers. Worst with dual core, dual displays.
@@ -242,7 +247,7 @@ static void cdv_errata(struct drm_device *dev) · 2 unmodified lines
242	247	* Bonus Launch to work around the issue, by degrading
243	248	* performance.
244	249	*/
245		− CDV_MSG_WRITE32(pci_domain_nr(dev->pdev->bus), 3, 0x30, 0x08027108);
	250	+ CDV_MSG_WRITE32(pci_domain_nr(pdev->bus), 3, 0x30, 0x08027108);
246	251	}
247	252
248	253	/**
@@ -255,12 +260,13 @@ static void cdv_errata(struct drm_device *dev) · 6 unmodified lines
255	260	static int cdv_save_display_registers(struct drm_device *dev)
256	261	{
257	262	struct drm_psb_private *dev_priv = dev->dev_private;
	263	+ struct pci_dev *pdev = to_pci_dev(dev->dev);
258	264	struct psb_save_area *regs = &dev_priv->regs;
259	265	struct drm_connector *connector;
260	266
261	267	dev_dbg(dev->dev, "Saving GPU registers.\n");
262	268
263		− pci_read_config_byte(dev->pdev, 0xF4, &regs->cdv.saveLBB);
	269	+ pci_read_config_byte(pdev, 0xF4, &regs->cdv.saveLBB);
264	270
265	271	regs->cdv.saveDSPCLK_GATE_D = REG_READ(DSPCLK_GATE_D);
266	272	regs->cdv.saveRAMCLK_GATE_D = REG_READ(RAMCLK_GATE_D);
@@ -309,11 +315,12 @@ static int cdv_save_display_registers(struct drm_device *dev) · 42 unmodified lines
309	315	static int cdv_restore_display_registers(struct drm_device *dev)
310	316	{
311	317	struct drm_psb_private *dev_priv = dev->dev_private;
	318	+ struct pci_dev *pdev = to_pci_dev(dev->dev);
312	319	struct psb_save_area *regs = &dev_priv->regs;
313	320	struct drm_connector *connector;
314	321	u32 temp;
315	322
316		− pci_write_config_byte(dev->pdev, 0xF4, regs->cdv.saveLBB);
	323	+ pci_write_config_byte(pdev, 0xF4, regs->cdv.saveLBB);
317	324
318	325	REG_WRITE(DSPCLK_GATE_D, regs->cdv.saveDSPCLK_GATE_D);
319	326	REG_WRITE(RAMCLK_GATE_D, regs->cdv.saveRAMCLK_GATE_D);
@@ -421,16 +428,16 @@ static int cdv_power_up(struct drm_device *dev) · 101 unmodified lines
421	428	static void cdv_hotplug_work_func(struct work_struct *work)
422	429	{
423	430	struct drm_psb_private *dev_priv = container_of(work, struct drm_psb_private,
424		− hotplug_work);
	431	+ hotplug_work);
425	432	struct drm_device *dev = dev_priv->dev;
426	433
427	434	/* Just fire off a uevent and let userspace tell us what to do */
428	435	drm_helper_hpd_irq_event(dev);
429		−}
	436	+}
430	437
431	438	/* The core driver has received a hotplug IRQ. We are in IRQ context
432	439	so extract the needed information and kick off queued processing */
433		−
	440	+
434	441	static int cdv_hotplug_event(struct drm_device *dev)
435	442	{
436	443	struct drm_psb_private *dev_priv = dev->dev_private;
@@ -449,7 +456,7 @@ static void cdv_hotplug_enable(struct drm_device *dev, bool on) · 12 unmodified lines
449	456	} else {
450	457	REG_WRITE(PORT_HOTPLUG_EN, 0);
451	458	REG_WRITE(PORT_HOTPLUG_STAT, REG_READ(PORT_HOTPLUG_STAT));
452		− }
	459	+ }
453	460	}
454	461
455	462	static const char *force_audio_names[] = {
@@ -568,9 +575,10 @@ static const struct psb_offset cdv_regmap[2] = { · 112 unmodified lines
568	575	static int cdv_chip_setup(struct drm_device *dev)
569	576	{
570	577	struct drm_psb_private *dev_priv = dev->dev_private;
	578	+ struct pci_dev *pdev = to_pci_dev(dev->dev);
571	579	INIT_WORK(&dev_priv->hotplug_work, cdv_hotplug_work_func);
572	580
573		− if (pci_enable_msi(dev->pdev))
	581	+ if (pci_enable_msi(pdev))
574	582	dev_warn(dev->dev, "Enabling MSI failed!\n");
575	583	dev_priv->regmap = cdv_regmap;
576	584	gma_get_core_freq(dev);

drivers/gpu/drm/gma500/cdv_intel_crt.c+2−3

@@ -127,7 +127,7 @@ static void cdv_intel_crt_mode_set(struct drm_encoder *encoder, · 126 unmodified lines
127	127	}
128	128
129	129
130		−/**
	130	+/*
131	131	* Uses CRT_HOTPLUG_EN and CRT_HOTPLUG_STAT to detect CRT presence.
132	132	*
133	133	* \return true if CRT is connected.
@@ -278,8 +278,7 @@ void cdv_intel_crt_init(struct drm_device *dev, · 144 unmodified lines
278	278	gma_encoder->ddc_bus = psb_intel_i2c_create(dev,
279	279	i2c_reg, "CRTDDC_A");
280	280	if (!gma_encoder->ddc_bus) {
281		− dev_printk(KERN_ERR, &dev->pdev->dev, "DDC bus registration "
282		− "failed.\n");
	281	+ dev_printk(KERN_ERR, dev->dev, "DDC bus registration failed.\n");
283	282	goto failed_ddc;
284	283	}
285	284

drivers/gpu/drm/gma500/cdv_intel_display.c+1−1

@@ -551,7 +551,7 @@ void cdv_update_wm(struct drm_device dev, struct drm_crtc crtc) · 550 unmodified lines
551	551	}
552	552	}
553	553
554		−/**
	554	+/*
555	555	* Return the pipe currently connected to the panel fitter,
556	556	* or -1 if the panel fitter is not present or not in use
557	557	*/

drivers/gpu/drm/gma500/cdv_intel_dp.c+2−2

@@ -306,7 +306,7 @@ static uint32_t dp_vswing_premph_table[] = { · 305 unmodified lines
306	306	};
307	307	/**
308	308	* is_edp - is the given port attached to an eDP panel (either CPU or PCH)
309		− * @intel_dp: DP struct
	309	+ * @encoder: GMA encoder struct
310	310	*
311	311	* If a CPU or PCH DP output is attached to an eDP panel, this function
312	312	* will return true, and false otherwise.
@@ -1687,7 +1687,7 @@ static enum drm_connector_status cdv_dp_detect(struct gma_encoder *encoder) · 1374 unmodified lines
1687	1687	return status;
1688	1688	}
1689	1689
1690		−/**
	1690	+/*
1691	1691	* Uses CRT_HOTPLUG_EN and CRT_HOTPLUG_STAT to detect DP connection.
1692	1692	*
1693	1693	* \return true if DP port is connected.

drivers/gpu/drm/gma500/cdv_intel_lvds.c+6−5

@@ -74,7 +74,7 @@ static u32 cdv_intel_lvds_get_max_backlight(struct drm_device *dev) · 73 unmodified lines
74	74	return retval;
75	75	}
76	76
77		−/**
	77	+/*
78	78	* Sets the backlight level.
79	79	*
80	80	* level backlight level, from 0 to cdv_intel_lvds_get_max_backlight().
@@ -99,7 +99,7 @@ static void cdv_intel_lvds_set_backlight(struct drm_device *dev, int level) · 18 unmodified lines
99	99	}
100	100	}
101	101
102		−/**
	102	+/*
103	103	* Sets the power state for the panel.
104	104	*/
105	105	static void cdv_intel_lvds_set_power(struct drm_device *dev,
@@ -291,7 +291,7 @@ static void cdv_intel_lvds_mode_set(struct drm_encoder *encoder, · 185 unmodified lines
291	291	REG_WRITE(PFIT_CONTROL, pfit_control);
292	292	}
293	293
294		−/**
	294	+/*
295	295	* Return the list of DDC modes if available, or the BIOS fixed mode otherwise.
296	296	*/
297	297	static int cdv_intel_lvds_get_modes(struct drm_connector *connector)
@@ -471,6 +471,7 @@ static bool lvds_is_present_in_vbt(struct drm_device *dev, · 173 unmodified lines
471	471	/**
472	472	* cdv_intel_lvds_init - setup LVDS connectors on this device
473	473	* @dev: drm device
	474	+ * @mode_dev: PSB mode device
474	475	*
475	476	* Create the connector, register the LVDS DDC bus, and try to figure out what
476	477	* modes we can display on the LVDS panel (if present).
@@ -554,7 +555,7 @@ void cdv_intel_lvds_init(struct drm_device *dev, · 77 unmodified lines
554	555	"LVDSBLC_B");
555	556	if (!gma_encoder->i2c_bus) {
556	557	dev_printk(KERN_ERR,
557		− &dev->pdev->dev, "I2C bus registration failed.\n");
	558	+ dev->dev, "I2C bus registration failed.\n");
558	559	goto failed_blc_i2c;
559	560	}
560	561	gma_encoder->i2c_bus->slave_addr = 0x2C;
@@ -575,7 +576,7 @@ void cdv_intel_lvds_init(struct drm_device *dev, · 14 unmodified lines
575	576	GPIOC,
576	577	"LVDSDDC_C");
577	578	if (!gma_encoder->ddc_bus) {
578		− dev_printk(KERN_ERR, &dev->pdev->dev,
	579	+ dev_printk(KERN_ERR, dev->dev,
579	580	"DDC bus registration " "failed.\n");
580	581	goto failed_ddc;
581	582	}

drivers/gpu/drm/gma500/framebuffer.c+8−7

@@ -159,7 +159,7 @@ static const struct fb_ops psbfb_unaccel_ops = { · 158 unmodified lines
159	159	* @dev: our DRM device
160	160	* @fb: framebuffer to set up
161	161	* @mode_cmd: mode description
162		− * @gt: backing object
	162	+ * @obj: backing object
163	163	*
164	164	* Configure and fill in the boilerplate for our frame buffer. Return
165	165	* 0 on success or an error code if we fail.
@@ -197,7 +197,7 @@ static int psb_framebuffer_init(struct drm_device *dev, · 31 unmodified lines
197	197	* psb_framebuffer_create - create a framebuffer backed by gt
198	198	* @dev: our DRM device
199	199	* @mode_cmd: the description of the requested mode
200		− * @gt: the backing object
	200	+ * @obj: the backing object
201	201	*
202	202	* Create a framebuffer object backed by the gt, and fill in the
203	203	* boilerplate required
@@ -252,7 +252,7 @@ static struct gtt_range psbfb_alloc(struct drm_device dev, int aligned_size) · 48 unmodified lines
252	252
253	253	/**
254	254	* psbfb_create - create a framebuffer
255		− * @fbdev: the framebuffer device
	255	+ * @fb_helper: the framebuffer helper
256	256	* @sizes: specification of the layout
257	257	*
258	258	* Create a framebuffer to the specifications provided
@@ -262,6 +262,7 @@ static int psbfb_create(struct drm_fb_helper *fb_helper, · 3 unmodified lines
262	262	{
263	263	struct drm_device *dev = fb_helper->dev;
264	264	struct drm_psb_private *dev_priv = dev->dev_private;
	265	+ struct pci_dev *pdev = to_pci_dev(dev->dev);
265	266	struct fb_info *info;
266	267	struct drm_framebuffer *fb;
267	268	struct drm_mode_fb_cmd2 mode_cmd;
@@ -325,8 +326,8 @@ static int psbfb_create(struct drm_fb_helper *fb_helper, · 57 unmodified lines
325	326
326	327	drm_fb_helper_fill_info(info, fb_helper, sizes);
327	328
328		− info->fix.mmio_start = pci_resource_start(dev->pdev, 0);
329		− info->fix.mmio_len = pci_resource_len(dev->pdev, 0);
	329	+ info->fix.mmio_start = pci_resource_start(pdev, 0);
	330	+ info->fix.mmio_len = pci_resource_len(pdev, 0);
330	331
331	332	/* Use default scratch pixmap (info->pixmap.flags = FB_PIXMAP_SYSTEM) */
332	333
@@ -529,6 +530,7 @@ void psb_modeset_init(struct drm_device *dev) · 196 unmodified lines
529	530	{
530	531	struct drm_psb_private *dev_priv = dev->dev_private;
531	532	struct psb_intel_mode_device *mode_dev = &dev_priv->mode_dev;
	533	+ struct pci_dev *pdev = to_pci_dev(dev->dev);
532	534	int i;
533	535
534	536	drm_mode_config_init(dev);
@@ -540,8 +542,7 @@ void psb_modeset_init(struct drm_device *dev) · 5 unmodified lines
540	542
541	543	/* set memory base */
542	544	/* Oaktrail and Poulsbo should use BAR 2*/
543		− pci_read_config_dword(dev->pdev, PSB_BSM, (u32 *)
544		− &(dev->mode_config.fb_base));
	545	+ pci_read_config_dword(pdev, PSB_BSM, (u32 *)&(dev->mode_config.fb_base));
545	546
546	547	/* num pipes is 2 for PSB but 1 for Mrst */
547	548	for (i = 0; i < dev_priv->num_pipe; i++)

drivers/gpu/drm/gma500/gem.c+4−2

@@ -16,6 +16,7 @@ · 15 unmodified lines
16	16	#include <drm/drm.h>
17	17	#include <drm/drm_vma_manager.h>
18	18
	19	+#include "gem.h"
19	20	#include "psb_drv.h"
20	21
21	22	static vm_fault_t psb_gem_fault(struct vm_fault *vmf);
@@ -49,6 +50,8 @@ const struct drm_gem_object_funcs psb_gem_object_funcs = { · 27 unmodified lines
49	50	* @dev: our device
50	51	* @size: the size requested
51	52	* @handlep: returned handle (opaque number)
	53	+ * @stolen: unused
	54	+ * @align: unused
52	55	*
53	56	* Create a GEM object, fill in the boilerplate and attach a handle to
54	57	* it so that userspace can speak about it. This does the core work
@@ -97,7 +100,7 @@ int psb_gem_create(struct drm_file file, struct drm_device dev, u64 size, · 42 unmodified lines
97	100
98	101	/**
99	102	* psb_gem_dumb_create - create a dumb buffer
100		− * @drm_file: our client file
	103	+ * @file: our client file
101	104	* @dev: our device
102	105	* @args: the requested arguments copied from userspace
103	106	*
@@ -116,7 +119,6 @@ int psb_gem_dumb_create(struct drm_file file, struct drm_device dev, · 12 unmodified lines
116	119
117	120	/**
118	121	* psb_gem_fault - pagefault handler for GEM objects
119		− * @vma: the VMA of the GEM object
120	122	* @vmf: fault detail
121	123	*
122	124	* Invoked when a fault occurs on an mmap of a GEM managed area. GEM

drivers/gpu/drm/gma500/gem.h+2−0

@@ -8,6 +8,8 @@ · 7 unmodified lines
8	8	#ifndef _GEM_H
9	9	#define _GEM_H
10	10
	11	+struct drm_device;
	12	+
11	13	extern const struct drm_gem_object_funcs psb_gem_object_funcs;
12	14
13	15	extern int psb_gem_create(struct drm_file file, struct drm_device dev,

drivers/gpu/drm/gma500/gma_device.c+3−1

@@ -6,12 +6,14 @@ · 5 unmodified lines
6	6	**************************************************************************/
7	7
8	8	#include "psb_drv.h"
	9	+#include "gma_device.h"
9	10
10	11	void gma_get_core_freq(struct drm_device *dev)
11	12	{
12	13	uint32_t clock;
	14	+ struct pci_dev *pdev = to_pci_dev(dev->dev);
13	15	struct pci_dev *pci_root =
14		− pci_get_domain_bus_and_slot(pci_domain_nr(dev->pdev->bus),
	16	+ pci_get_domain_bus_and_slot(pci_domain_nr(pdev->bus),
15	17	0, 0);
16	18	struct drm_psb_private *dev_priv = dev->dev_private;
17	19

drivers/gpu/drm/gma500/gma_display.c+6−6

@@ -20,7 +20,7 @@ · 19 unmodified lines
20	20	#include "psb_intel_drv.h"
21	21	#include "psb_intel_reg.h"
22	22
23		−/**
	23	+/*
24	24	* Returns whether any output on the specified pipe is of the specified type
25	25	*/
26	26	bool gma_pipe_has_type(struct drm_crtc *crtc, int type)
@@ -180,7 +180,7 @@ int gma_crtc_gamma_set(struct drm_crtc crtc, u16 red, u16 green, u16 blue, · 153 unmodified lines
180	180	return 0;
181	181	}
182	182
183		−/**
	183	+/*
184	184	* Sets the power management mode of the pipe and plane.
185	185	*
186	186	* This code should probably grow support for turning the cursor off and back
@@ -559,14 +559,14 @@ int gma_crtc_set_config(struct drm_mode_set *set, · 372 unmodified lines
559	559	if (!dev_priv->rpm_enabled)
560	560	return drm_crtc_helper_set_config(set, ctx);
561	561
562		− pm_runtime_forbid(&dev->pdev->dev);
	562	+ pm_runtime_forbid(dev->dev);
563	563	ret = drm_crtc_helper_set_config(set, ctx);
564		− pm_runtime_allow(&dev->pdev->dev);
	564	+ pm_runtime_allow(dev->dev);
565	565
566	566	return ret;
567	567	}
568	568
569		−/**
	569	+/*
570	570	* Save HW states of given crtc
571	571	*/
572	572	void gma_crtc_save(struct drm_crtc *crtc)
@@ -609,7 +609,7 @@ void gma_crtc_save(struct drm_crtc *crtc) · 36 unmodified lines
609	609	crtc_state->savePalette[i] = REG_READ(palette_reg + (i << 2));
610	610	}
611	611
612		−/**
	612	+/*
613	613	* Restore HW states of given crtc
614	614	*/
615	615	void gma_crtc_restore(struct drm_crtc *crtc)

drivers/gpu/drm/gma500/gtt.c+11−9

@@ -340,13 +340,14 @@ static void psb_gtt_alloc(struct drm_device *dev) · 339 unmodified lines
340	340	void psb_gtt_takedown(struct drm_device *dev)
341	341	{
342	342	struct drm_psb_private *dev_priv = dev->dev_private;
	343	+ struct pci_dev *pdev = to_pci_dev(dev->dev);
343	344
344	345	if (dev_priv->gtt_map) {
345	346	iounmap(dev_priv->gtt_map);
346	347	dev_priv->gtt_map = NULL;
347	348	}
348	349	if (dev_priv->gtt_initialized) {
349		− pci_write_config_word(dev->pdev, PSB_GMCH_CTRL,
	350	+ pci_write_config_word(pdev, PSB_GMCH_CTRL,
350	351	dev_priv->gmch_ctrl);
351	352	PSB_WVDC32(dev_priv->pge_ctl, PSB_PGETBL_CTL);
352	353	(void) PSB_RVDC32(PSB_PGETBL_CTL);
@@ -358,6 +359,7 @@ void psb_gtt_takedown(struct drm_device *dev) · 5 unmodified lines
358	359	int psb_gtt_init(struct drm_device *dev, int resume)
359	360	{
360	361	struct drm_psb_private *dev_priv = dev->dev_private;
	362	+ struct pci_dev *pdev = to_pci_dev(dev->dev);
361	363	unsigned gtt_pages;
362	364	unsigned long stolen_size, vram_stolen_size;
363	365	unsigned i, num_pages;
@@ -376,8 +378,8 @@ int psb_gtt_init(struct drm_device *dev, int resume) · 12 unmodified lines
376	378	pg = &dev_priv->gtt;
377	379
378	380	/* Enable the GTT */
379		− pci_read_config_word(dev->pdev, PSB_GMCH_CTRL, &dev_priv->gmch_ctrl);
380		− pci_write_config_word(dev->pdev, PSB_GMCH_CTRL,
	381	+ pci_read_config_word(pdev, PSB_GMCH_CTRL, &dev_priv->gmch_ctrl);
	382	+ pci_write_config_word(pdev, PSB_GMCH_CTRL,
381	383	dev_priv->gmch_ctrl \| _PSB_GMCH_ENABLED);
382	384
383	385	dev_priv->pge_ctl = PSB_RVDC32(PSB_PGETBL_CTL);
@@ -397,8 +399,8 @@ int psb_gtt_init(struct drm_device *dev, int resume) · 13 unmodified lines
397	399	*/
398	400	pg->mmu_gatt_start = 0xE0000000;
399	401
400		− pg->gtt_start = pci_resource_start(dev->pdev, PSB_GTT_RESOURCE);
401		− gtt_pages = pci_resource_len(dev->pdev, PSB_GTT_RESOURCE)
	402	+ pg->gtt_start = pci_resource_start(pdev, PSB_GTT_RESOURCE);
	403	+ gtt_pages = pci_resource_len(pdev, PSB_GTT_RESOURCE)
402	404	>> PAGE_SHIFT;
403	405	/* CDV doesn't report this. In which case the system has 64 gtt pages */
404	406	if (pg->gtt_start == 0 \|\| gtt_pages == 0) {
@@ -407,10 +409,10 @@ int psb_gtt_init(struct drm_device *dev, int resume) · 2 unmodified lines
407	409	pg->gtt_start = dev_priv->pge_ctl;
408	410	}
409	411
410		− pg->gatt_start = pci_resource_start(dev->pdev, PSB_GATT_RESOURCE);
411		− pg->gatt_pages = pci_resource_len(dev->pdev, PSB_GATT_RESOURCE)
	412	+ pg->gatt_start = pci_resource_start(pdev, PSB_GATT_RESOURCE);
	413	+ pg->gatt_pages = pci_resource_len(pdev, PSB_GATT_RESOURCE)
412	414	>> PAGE_SHIFT;
413		− dev_priv->gtt_mem = &dev->pdev->resource[PSB_GATT_RESOURCE];
	415	+ dev_priv->gtt_mem = &pdev->resource[PSB_GATT_RESOURCE];
414	416
415	417	if (pg->gatt_pages == 0 \|\| pg->gatt_start == 0) {
416	418	static struct resource fudge; /* Preferably peppermint */
@@ -431,7 +433,7 @@ int psb_gtt_init(struct drm_device *dev, int resume) · 14 unmodified lines
431	433	dev_priv->gtt_mem = &fudge;
432	434	}
433	435
434		− pci_read_config_dword(dev->pdev, PSB_BSM, &dev_priv->stolen_base);
	436	+ pci_read_config_dword(pdev, PSB_BSM, &dev_priv->stolen_base);
435	437	vram_stolen_size = pg->gtt_phys_start - dev_priv->stolen_base
436	438	- PAGE_SIZE;
437	439

drivers/gpu/drm/gma500/intel_bios.c+4−4

@@ -50,7 +50,7 @@ parse_edp(struct drm_psb_private dev_priv, struct bdb_header bdb) · 49 unmodified lines
50	50	uint8_t panel_type;
51	51
52	52	edp = find_section(bdb, BDB_EDP);
53		−
	53	+
54	54	dev_priv->edp.bpp = 18;
55	55	if (!edp) {
56	56	if (dev_priv->edp.support) {
@@ -80,7 +80,7 @@ parse_edp(struct drm_psb_private dev_priv, struct bdb_header bdb) · 23 unmodified lines
80	80	dev_priv->edp.pps = *edp_pps;
81	81
82	82	DRM_DEBUG_KMS("EDP timing in vbt t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
83		− dev_priv->edp.pps.t1_t3, dev_priv->edp.pps.t8,
	83	+ dev_priv->edp.pps.t1_t3, dev_priv->edp.pps.t8,
84	84	dev_priv->edp.pps.t9, dev_priv->edp.pps.t10,
85	85	dev_priv->edp.pps.t11_t12);
86	86
@@ -516,7 +516,7 @@ parse_device_mapping(struct drm_psb_private *dev_priv, · 429 unmodified lines
516	516	int psb_intel_init_bios(struct drm_device *dev)
517	517	{
518	518	struct drm_psb_private *dev_priv = dev->dev_private;
519		− struct pci_dev *pdev = dev->pdev;
	519	+ struct pci_dev *pdev = to_pci_dev(dev->dev);
520	520	struct vbt_header *vbt = NULL;
521	521	struct bdb_header *bdb = NULL;
522	522	u8 __iomem *bios = NULL;
@@ -574,7 +574,7 @@ int psb_intel_init_bios(struct drm_device *dev) · 51 unmodified lines
574	574	return 0;
575	575	}
576	576
577		−/**
	577	+/*
578	578	* Destroy and free VBT data
579	579	*/
580	580	void psb_intel_destroy_bios(struct drm_device *dev)

drivers/gpu/drm/gma500/intel_gmbus.c+2−2

@@ -196,7 +196,7 @@ intel_gpio_create(struct drm_psb_private *dev_priv, u32 pin) · 195 unmodified lines
196	196	"gma500 GPIO%c", "?BACDE?F"[pin]);
197	197	gpio->adapter.owner = THIS_MODULE;
198	198	gpio->adapter.algo_data = &gpio->algo;
199		− gpio->adapter.dev.parent = &dev_priv->dev->pdev->dev;
	199	+ gpio->adapter.dev.parent = dev_priv->dev->dev;
200	200	gpio->algo.setsda = set_data;
201	201	gpio->algo.setscl = set_clock;
202	202	gpio->algo.getsda = get_data;
@@ -417,7 +417,7 @@ int gma_intel_setup_gmbus(struct drm_device *dev) · 214 unmodified lines
417	417	"gma500 gmbus %s",
418	418	names[i]);
419	419
420		− bus->adapter.dev.parent = &dev->pdev->dev;
	420	+ bus->adapter.dev.parent = dev->dev;
421	421	bus->adapter.algo_data = dev_priv;
422	422
423	423	bus->adapter.algo = &gmbus_algorithm;

drivers/gpu/drm/gma500/intel_i2c.c+2−3

@@ -85,7 +85,6 @@ static void set_data(void *data, int state_high) · 84 unmodified lines
85	85	/**
86	86	* psb_intel_i2c_create - instantiate an Intel i2c bus using the specified GPIO reg
87	87	* @dev: DRM device
88		− * @output: driver specific output device
89	88	* @reg: GPIO reg to use
90	89	* @name: name for this bus
91	90	*
@@ -117,7 +116,7 @@ struct psb_intel_i2c_chan psb_intel_i2c_create(struct drm_device dev, · 25 unmodified lines
117	116	snprintf(chan->adapter.name, I2C_NAME_SIZE, "intel drm %s", name);
118	117	chan->adapter.owner = THIS_MODULE;
119	118	chan->adapter.algo_data = &chan->algo;
120		− chan->adapter.dev.parent = &dev->pdev->dev;
	119	+ chan->adapter.dev.parent = dev->dev;
121	120	chan->algo.setsda = set_data;
122	121	chan->algo.setscl = set_clock;
123	122	chan->algo.getsda = get_data;
@@ -145,7 +144,7 @@ out_free: · 21 unmodified lines
145	144
146	145	/**
147	146	* psb_intel_i2c_destroy - unregister and free i2c bus resources
148		− * @output: channel to free
	147	+ * @chan: channel to free
149	148	*
150	149	* Unregister the adapter from the i2c layer, then free the structure.
151	150	*/

drivers/gpu/drm/gma500/mdfld_device.c+3−1

@@ -523,7 +523,9 @@ static struct gpiod_lookup_table mdfld_dsi_pipe_gpio_table = { · 522 unmodified lines
523	523	static int mdfld_chip_setup(struct drm_device *dev)
524	524	{
525	525	struct drm_psb_private *dev_priv = dev->dev_private;
526		− if (pci_enable_msi(dev->pdev))
	526	+ struct pci_dev *pdev = to_pci_dev(dev->dev);
	527	+
	528	+ if (pci_enable_msi(pdev))
527	529	dev_warn(dev->dev, "Enabling MSI failed!\n");
528	530	dev_priv->regmap = mdfld_regmap;
529	531

drivers/gpu/drm/gma500/mdfld_dsi_dpi.c+4−4

@@ -138,7 +138,7 @@ static void dsi_set_pipe_plane_enable_state(struct drm_device *dev, · 137 unmodified lines
138	138	REG_WRITE(pipeconf_reg, BIT(31));
139	139
140	140	if (REG_BIT_WAIT(pipeconf_reg, 1, 30))
141		− dev_err(&dev->pdev->dev, "%s: Pipe enable timeout\n",
	141	+ dev_err(dev->dev, "%s: Pipe enable timeout\n",
142	142	__func__);
143	143
144	144	/Set up display plane /
@@ -165,11 +165,11 @@ static void dsi_set_pipe_plane_enable_state(struct drm_device *dev, · 20 unmodified lines
165	165	REG_FLD_MOD(pipeconf_reg, 0, 31, 31);
166	166
167	167	if (REG_BIT_WAIT(pipeconf_reg, 0, 30))
168		− dev_err(&dev->pdev->dev, "%s: Pipe disable timeout\n",
	168	+ dev_err(dev->dev, "%s: Pipe disable timeout\n",
169	169	__func__);
170	170
171	171	if (REG_BIT_WAIT(MIPI_GEN_FIFO_STAT_REG(pipe), 1, 28))
172		− dev_err(&dev->pdev->dev, "%s: FIFO not empty\n",
	172	+ dev_err(dev->dev, "%s: FIFO not empty\n",
173	173	__func__);
174	174	}
175	175	}
@@ -867,7 +867,7 @@ void mdfld_dsi_dpi_mode_set(struct drm_encoder *encoder, · 691 unmodified lines
867	867	REG_WRITE(MRST_DPLL_A, 0x80800000);
868	868
869	869	if (REG_BIT_WAIT(pipeconf_reg, 1, 29))
870		− dev_err(&dev->pdev->dev, "%s: DSI PLL lock timeout\n",
	870	+ dev_err(dev->dev, "%s: DSI PLL lock timeout\n",
871	871	__func__);
872	872
873	873	REG_WRITE(MIPI_DPHY_PARAM_REG(pipe), 0x2A0c6008);

drivers/gpu/drm/gma500/mdfld_dsi_output.c+2−2

@@ -63,7 +63,7 @@ static int __init parse_LABC_control(char *arg) · 62 unmodified lines
63	63	early_param("LABC", parse_LABC_control);
64	64	#endif
65	65
66		−/**
	66	+/*
67	67	* Check and see if the generic control or data buffer is empty and ready.
68	68	*/
69	69	void mdfld_dsi_gen_fifo_ready(struct drm_device *dev, u32 gen_fifo_stat_reg,
@@ -85,7 +85,7 @@ void mdfld_dsi_gen_fifo_ready(struct drm_device *dev, u32 gen_fifo_stat_reg, · 15 unmodified lines
85	85	gen_fifo_stat_reg);
86	86	}
87	87
88		−/**
	88	+/*
89	89	* Manage the DSI MIPI keyboard and display brightness.
90	90	* FIXME: this is exported to OSPM code. should work out an specific
91	91	* display interface to OSPM.

drivers/gpu/drm/gma500/mdfld_intel_display.c+3−3

@@ -95,7 +95,7 @@ void mdfldWaitForPipeEnable(struct drm_device *dev, int pipe) · 94 unmodified lines
95	95	}
96	96	}
97	97
98		−/**
	98	+/*
99	99	* Return the pipe currently connected to the panel fitter,
100	100	* or -1 if the panel fitter is not present or not in use
101	101	*/
@@ -263,7 +263,7 @@ void mdfld_disable_crtc(struct drm_device *dev, int pipe) · 161 unmodified lines
263	263
264	264	}
265	265
266		−/**
	266	+/*
267	267	* Sets the power management mode of the pipe and plane.
268	268	*
269	269	* This code should probably grow support for turning the cursor off and back
@@ -599,7 +599,7 @@ static void mdfld_clock(int refclk, struct mrst_clock_t *clock) · 329 unmodified lines
599	599	clock->dot = (refclk * clock->m) / clock->p1;
600	600	}
601	601
602		−/**
	602	+/*
603	603	* Returns a set of divisors for the desired target clock with the given refclk,
604	604	* or FALSE. Divisor values are the actual divisors for
605	605	*/

drivers/gpu/drm/gma500/mid_bios.c+6−3

@@ -19,8 +19,9 @@ · 18 unmodified lines
19	19	static void mid_get_fuse_settings(struct drm_device *dev)
20	20	{
21	21	struct drm_psb_private *dev_priv = dev->dev_private;
	22	+ struct pci_dev *pdev = to_pci_dev(dev->dev);
22	23	struct pci_dev *pci_root =
23		− pci_get_domain_bus_and_slot(pci_domain_nr(dev->pdev->bus),
	24	+ pci_get_domain_bus_and_slot(pci_domain_nr(pdev->bus),
24	25	0, 0);
25	26	uint32_t fuse_value = 0;
26	27	uint32_t fuse_value_tmp = 0;
@@ -93,7 +94,8 @@ static void mid_get_fuse_settings(struct drm_device *dev) · 66 unmodified lines
93	94	static void mid_get_pci_revID(struct drm_psb_private *dev_priv)
94	95	{
95	96	uint32_t platform_rev_id = 0;
96		− int domain = pci_domain_nr(dev_priv->dev->pdev->bus);
	97	+ struct pci_dev *pdev = to_pci_dev(dev_priv->dev->dev);
	98	+ int domain = pci_domain_nr(pdev->bus);
97	99	struct pci_dev *pci_gfx_root =
98	100	pci_get_domain_bus_and_slot(domain, 0, PCI_DEVFN(2, 0));
99	101
@@ -269,11 +271,12 @@ out: · 169 unmodified lines
269	271	static void mid_get_vbt_data(struct drm_psb_private *dev_priv)
270	272	{
271	273	struct drm_device *dev = dev_priv->dev;
	274	+ struct pci_dev *pdev = to_pci_dev(dev->dev);
272	275	u32 addr;
273	276	u8 __iomem *vbt_virtual;
274	277	struct mid_vbt_header vbt_header;
275	278	struct pci_dev *pci_gfx_root =
276		− pci_get_domain_bus_and_slot(pci_domain_nr(dev->pdev->bus),
	279	+ pci_get_domain_bus_and_slot(pci_domain_nr(pdev->bus),
277	280	0, PCI_DEVFN(2, 0));
278	281	int ret = -1;
279	282

drivers/gpu/drm/gma500/mmu.c+3−12

@@ -313,8 +313,8 @@ static struct psb_mmu_pt psb_mmu_alloc_pt(struct psb_mmu_pd pd) · 312 unmodified lines
313	313	return pt;
314	314	}
315	315
316		−struct psb_mmu_pt psb_mmu_pt_alloc_map_lock(struct psb_mmu_pd pd,
317		− unsigned long addr)
	316	+static struct psb_mmu_pt psb_mmu_pt_alloc_map_lock(struct psb_mmu_pd pd,
	317	+ unsigned long addr)
318	318	{
319	319	uint32_t index = psb_mmu_pd_index(addr);
320	320	struct psb_mmu_pt *pt;
@@ -416,15 +416,6 @@ struct psb_mmu_pd psb_mmu_get_default_pd(struct psb_mmu_driver driver) · 95 unmodified lines
416	416	return pd;
417	417	}
418	418
419		−/* Returns the physical address of the PD shared by sgx/msvdx */
420		−uint32_t psb_get_default_pd_addr(struct psb_mmu_driver *driver)
421		−{
422		− struct psb_mmu_pd *pd;
423		−
424		− pd = psb_mmu_get_default_pd(driver);
425		− return page_to_pfn(pd->p) << PAGE_SHIFT;
426		−}
427		−
428	419	void psb_mmu_driver_takedown(struct psb_mmu_driver *driver)
429	420	{
430	421	struct drm_device *dev = driver->dev;
@@ -690,7 +681,7 @@ out: · 259 unmodified lines
690	681	if (pd->hw_context != -1)
691	682	psb_mmu_flush(pd->driver);
692	683
693		− return 0;
	684	+ return ret;
694	685	}
695	686
696	687	int psb_mmu_insert_pages(struct psb_mmu_pd pd, struct page *pages,

drivers/gpu/drm/gma500/oaktrail_crtc.c+3−3

@@ -174,7 +174,7 @@ static bool mrst_sdvo_find_best_pll(const struct gma_limit_t *limit, · 173 unmodified lines
174	174	return min_error == 0;
175	175	}
176	176
177		−/**
	177	+/*
178	178	* Returns a set of divisors for the desired target clock with the given refclk,
179	179	* or FALSE. Divisor values are the actual divisors for
180	180	*/
@@ -205,7 +205,7 @@ static bool mrst_lvds_find_best_pll(const struct gma_limit_t *limit, · 24 unmodified lines
205	205	return err != target;
206	206	}
207	207
208		−/**
	208	+/*
209	209	* Sets the power management mode of the pipe and plane.
210	210	*
211	211	* This code should probably grow support for turning the cursor off and back
@@ -337,7 +337,7 @@ static void oaktrail_crtc_dpms(struct drm_crtc *crtc, int mode) · 125 unmodified lines
337	337	gma_power_end(dev);
338	338	}
339	339
340		−/**
	340	+/*
341	341	* Return the pipe currently connected to the panel fitter,
342	342	* or -1 if the panel fitter is not present or not in use
343	343	*/

drivers/gpu/drm/gma500/oaktrail_device.c+3−2

@@ -504,9 +504,10 @@ static const struct psb_offset oaktrail_regmap[2] = { · 503 unmodified lines
504	504	static int oaktrail_chip_setup(struct drm_device *dev)
505	505	{
506	506	struct drm_psb_private *dev_priv = dev->dev_private;
	507	+ struct pci_dev *pdev = to_pci_dev(dev->dev);
507	508	int ret;
508		−
509		− if (pci_enable_msi(dev->pdev))
	509	+
	510	+ if (pci_enable_msi(pdev))
510	511	dev_warn(dev->dev, "Enabling MSI failed!\n");
511	512
512	513	dev_priv->regmap = oaktrail_regmap;

drivers/gpu/drm/gma500/oaktrail_lvds.c+3−2

@@ -29,7 +29,7 @@ · 28 unmodified lines
29	29	#define MRST_BLC_MAX_PWM_REG_FREQ 0xFFFF
30	30	#define BRIGHTNESS_MAX_LEVEL 100
31	31
32		−/**
	32	+/*
33	33	* Sets the power state for the panel.
34	34	*/
35	35	static void oaktrail_lvds_set_power(struct drm_device *dev,
@@ -60,7 +60,7 @@ static void oaktrail_lvds_set_power(struct drm_device *dev, · 24 unmodified lines
60	60	pp_status = REG_READ(PP_STATUS);
61	61	} while (pp_status & PP_ON);
62	62	dev_priv->is_lvds_on = false;
63		− pm_request_idle(&dev->pdev->dev);
	63	+ pm_request_idle(dev->dev);
64	64	}
65	65	gma_power_end(dev);
66	66	}
@@ -282,6 +282,7 @@ static void oaktrail_lvds_get_configuration_mode(struct drm_device *dev, · 215 unmodified lines
282	282	/**
283	283	* oaktrail_lvds_init - setup LVDS connectors on this device
284	284	* @dev: drm device
	285	+ * @mode_dev: PSB mode device
285	286	*
286	287	* Create the connector, register the LVDS DDC bus, and try to figure out what
287	288	* modes we can display on the LVDS panel (if present).

drivers/gpu/drm/gma500/oaktrail_lvds_i2c.c+5−5

@@ -66,12 +66,12 @@ · 65 unmodified lines
66	66	static int get_clock(void *data)
67	67	{
68	68	struct psb_intel_i2c_chan *chan = data;
69		− u32 val, tmp;
	69	+ u32 val;
70	70
71	71	val = LPC_READ_REG(chan, RGIO);
72	72	val \|= GPIO_CLOCK;
73	73	LPC_WRITE_REG(chan, RGIO, val);
74		− tmp = LPC_READ_REG(chan, RGLVL);
	74	+ LPC_READ_REG(chan, RGLVL);
75	75	val = (LPC_READ_REG(chan, RGLVL) & GPIO_CLOCK) ? 1 : 0;
76	76
77	77	return val;
@@ -80,12 +80,12 @@ static int get_clock(void *data) · 2 unmodified lines
80	80	static int get_data(void *data)
81	81	{
82	82	struct psb_intel_i2c_chan *chan = data;
83		− u32 val, tmp;
	83	+ u32 val;
84	84
85	85	val = LPC_READ_REG(chan, RGIO);
86	86	val \|= GPIO_DATA;
87	87	LPC_WRITE_REG(chan, RGIO, val);
88		− tmp = LPC_READ_REG(chan, RGLVL);
	88	+ LPC_READ_REG(chan, RGLVL);
89	89	val = (LPC_READ_REG(chan, RGLVL) & GPIO_DATA) ? 1 : 0;
90	90
91	91	return val;
@@ -145,7 +145,7 @@ void oaktrail_lvds_i2c_init(struct drm_encoder *encoder) · 53 unmodified lines
145	145	strncpy(chan->adapter.name, "gma500 LPC", I2C_NAME_SIZE - 1);
146	146	chan->adapter.owner = THIS_MODULE;
147	147	chan->adapter.algo_data = &chan->algo;
148		− chan->adapter.dev.parent = &dev->pdev->dev;
	148	+ chan->adapter.dev.parent = dev->dev;
149	149	chan->algo.setsda = set_data;
150	150	chan->algo.setscl = set_clock;
151	151	chan->algo.getsda = get_data;

drivers/gpu/drm/gma500/opregion.c+2−1

@@ -305,12 +305,13 @@ void psb_intel_opregion_fini(struct drm_device *dev) · 304 unmodified lines
305	305	int psb_intel_opregion_setup(struct drm_device *dev)
306	306	{
307	307	struct drm_psb_private *dev_priv = dev->dev_private;
	308	+ struct pci_dev *pdev = to_pci_dev(dev->dev);
308	309	struct psb_intel_opregion *opregion = &dev_priv->opregion;
309	310	u32 opregion_phy, mboxes;
310	311	void __iomem *base;
311	312	int err = 0;
312	313
313		− pci_read_config_dword(dev->pdev, PCI_ASLS, &opregion_phy);
	314	+ pci_read_config_dword(pdev, PCI_ASLS, &opregion_phy);
314	315	if (opregion_phy == 0) {
315	316	DRM_DEBUG_DRIVER("ACPI Opregion not supported\n");
316	317	return -ENOTSUPP;

drivers/gpu/drm/gma500/power.c+11−10

@@ -70,8 +70,8 @@ void gma_power_init(struct drm_device *dev) · 69 unmodified lines
70	70	*/
71	71	void gma_power_uninit(struct drm_device *dev)
72	72	{
73		− pm_runtime_disable(&dev->pdev->dev);
74		− pm_runtime_set_suspended(&dev->pdev->dev);
	73	+ pm_runtime_disable(dev->dev);
	74	+ pm_runtime_set_suspended(dev->dev);
75	75	}
76	76
77	77	/**
@@ -93,6 +93,7 @@ static void gma_suspend_display(struct drm_device *dev) · 15 unmodified lines
93	93
94	94	/**
95	95	* gma_resume_display - resume display side logic
	96	+ * @pdev: PCI device
96	97	*
97	98	* Resume the display hardware restoring state and enabling
98	99	* as necessary.
@@ -146,7 +147,7 @@ static void gma_suspend_pci(struct pci_dev *pdev) · 47 unmodified lines
146	147
147	148	/**
148	149	* gma_resume_pci - resume helper
149		− * @dev: our PCI device
	150	+ * @pdev: our PCI device
150	151	*
151	152	* Perform the resume processing on our PCI device state - rewrite
152	153	* register state and re-enable the PCI device
@@ -178,8 +179,7 @@ static bool gma_resume_pci(struct pci_dev *pdev) · 25 unmodified lines
178	179
179	180	/**
180	181	* gma_power_suspend - bus callback for suspend
181		− * @pdev: our PCI device
182		− * @state: suspend type
	182	+ * @_dev: our device
183	183	*
184	184	* Called back by the PCI layer during a suspend of the system. We
185	185	* perform the necessary shut down steps and save enough state that
@@ -208,7 +208,7 @@ int gma_power_suspend(struct device *_dev) · 22 unmodified lines
208	208
209	209	/**
210	210	* gma_power_resume - resume power
211		− * @pdev: PCI device
	211	+ * @_dev: our device
212	212	*
213	213	* Resume the PCI side of the graphics and then the displays
214	214	*/
@@ -249,6 +249,7 @@ bool gma_power_is_on(struct drm_device *dev) · 34 unmodified lines
249	249	bool gma_power_begin(struct drm_device *dev, bool force_on)
250	250	{
251	251	struct drm_psb_private *dev_priv = dev->dev_private;
	252	+ struct pci_dev *pdev = to_pci_dev(dev->dev);
252	253	int ret;
253	254	unsigned long flags;
254	255
@@ -256,7 +257,7 @@ bool gma_power_begin(struct drm_device *dev, bool force_on) · 1 unmodified line
256	257	/* Power already on ? */
257	258	if (dev_priv->display_power) {
258	259	dev_priv->display_count++;
259		− pm_runtime_get(&dev->pdev->dev);
	260	+ pm_runtime_get(dev->dev);
260	261	spin_unlock_irqrestore(&power_ctrl_lock, flags);
261	262	return true;
262	263	}
@@ -264,11 +265,11 @@ bool gma_power_begin(struct drm_device *dev, bool force_on) · 1 unmodified line
264	265	goto out_false;
265	266
266	267	/* Ok power up needed */
267		− ret = gma_resume_pci(dev->pdev);
	268	+ ret = gma_resume_pci(pdev);
268	269	if (ret == 0) {
269	270	psb_irq_preinstall(dev);
270	271	psb_irq_postinstall(dev);
271		− pm_runtime_get(&dev->pdev->dev);
	272	+ pm_runtime_get(dev->dev);
272	273	dev_priv->display_count++;
273	274	spin_unlock_irqrestore(&power_ctrl_lock, flags);
274	275	return true;
@@ -293,7 +294,7 @@ void gma_power_end(struct drm_device *dev) · 18 unmodified lines
293	294	dev_priv->display_count--;
294	295	WARN_ON(dev_priv->display_count < 0);
295	296	spin_unlock_irqrestore(&power_ctrl_lock, flags);
296		− pm_runtime_put(&dev->pdev->dev);
	297	+ pm_runtime_put(dev->dev);
297	298	}
298	299
299	300	int psb_runtime_suspend(struct device *dev)

drivers/gpu/drm/gma500/psb_drv.c+8−8

@@ -208,6 +208,7 @@ static void psb_driver_unload(struct drm_device *dev) · 207 unmodified lines
208	208
209	209	static int psb_driver_load(struct drm_device *dev, unsigned long flags)
210	210	{
	211	+ struct pci_dev *pdev = to_pci_dev(dev->dev);
211	212	struct drm_psb_private *dev_priv;
212	213	unsigned long resource_start, resource_len;
213	214	unsigned long irqflags;
@@ -227,11 +228,11 @@ static int psb_driver_load(struct drm_device *dev, unsigned long flags) · 13 unmodified lines
227	228
228	229	pg = &dev_priv->gtt;
229	230
230		− pci_set_master(dev->pdev);
	231	+ pci_set_master(pdev);
231	232
232	233	dev_priv->num_pipe = dev_priv->ops->pipes;
233	234
234		− resource_start = pci_resource_start(dev->pdev, PSB_MMIO_RESOURCE);
	235	+ resource_start = pci_resource_start(pdev, PSB_MMIO_RESOURCE);
235	236
236	237	dev_priv->vdc_reg =
237	238	ioremap(resource_start + PSB_VDC_OFFSET, PSB_VDC_SIZE);
@@ -244,7 +245,7 @@ static int psb_driver_load(struct drm_device *dev, unsigned long flags) · 6 unmodified lines
244	245	goto out_err;
245	246
246	247	if (IS_MRST(dev)) {
247		− int domain = pci_domain_nr(dev->pdev->bus);
	248	+ int domain = pci_domain_nr(pdev->bus);
248	249
249	250	dev_priv->aux_pdev =
250	251	pci_get_domain_bus_and_slot(domain, 0,
@@ -361,7 +362,7 @@ static int psb_driver_load(struct drm_device *dev, unsigned long flags) · 110 unmodified lines
361	362	PSB_WVDC32(0xFFFFFFFF, PSB_INT_MASK_R);
362	363	spin_unlock_irqrestore(&dev_priv->irqmask_lock, irqflags);
363	364
364		− drm_irq_install(dev, dev->pdev->irq);
	365	+ drm_irq_install(dev, pdev->irq);
365	366
366	367	dev->max_vblank_count = 0xffffff; /* only 24 bits of frame count */
367	368
@@ -387,8 +388,8 @@ static int psb_driver_load(struct drm_device *dev, unsigned long flags) · 19 unmodified lines
387	388	psb_intel_opregion_enable_asle(dev);
388	389	#if 0
389	390	/* Enable runtime pm at last */
390		− pm_runtime_enable(&dev->pdev->dev);
391		− pm_runtime_set_active(&dev->pdev->dev);
	391	+ pm_runtime_enable(dev->dev);
	392	+ pm_runtime_set_active(dev->dev);
392	393	#endif
393	394	/* Intel drm driver load is done, continue doing pvr load */
394	395	return 0;
@@ -417,7 +418,7 @@ static long psb_unlocked_ioctl(struct file *filp, unsigned int cmd, · 22 unmodified lines
417	418
418	419	if (runtime_allowed == 1 && dev_priv->is_lvds_on) {
419	420	runtime_allowed++;
420		− pm_runtime_allow(&dev->pdev->dev);
	421	+ pm_runtime_allow(dev->dev);
421	422	dev_priv->rpm_enabled = 1;
422	423	}
423	424	return drm_ioctl(filp, cmd, arg);
@@ -439,7 +440,6 @@ static int psb_pci_probe(struct pci_dev pdev, const struct pci_device_id ent) · 15 unmodified lines
439	440	goto err_pci_disable_device;
440	441	}
441	442
442		− dev->pdev = pdev;
443	443	pci_set_drvdata(pdev, dev);
444	444
445	445	ret = psb_driver_load(dev, ent->driver_data);

drivers/gpu/drm/gma500/psb_drv.h+4−4

@@ -43,10 +43,10 @@ enum { · 42 unmodified lines
43	43	CHIP_MFLD_0130 = 3, /* Medfield */
44	44	};
45	45
46		−#define IS_PSB(dev) (((dev)->pdev->device & 0xfffe) == 0x8108)
47		−#define IS_MRST(dev) (((dev)->pdev->device & 0xfff0) == 0x4100)
48		−#define IS_MFLD(dev) (((dev)->pdev->device & 0xfff8) == 0x0130)
49		−#define IS_CDV(dev) (((dev)->pdev->device & 0xfff0) == 0x0be0)
	46	+#define IS_PSB(drm) ((to_pci_dev((drm)->dev)->device & 0xfffe) == 0x8108)
	47	+#define IS_MRST(drm) ((to_pci_dev((drm)->dev)->device & 0xfff0) == 0x4100)
	48	+#define IS_MFLD(drm) ((to_pci_dev((drm)->dev)->device & 0xfff8) == 0x0130)
	49	+#define IS_CDV(drm) ((to_pci_dev((drm)->dev)->device & 0xfff0) == 0x0be0)
50	50
51	51	/* Hardware offsets */
52	52	#define PSB_VDC_OFFSET 0x00000000

drivers/gpu/drm/gma500/psb_intel_display.c+1−1

@@ -71,7 +71,7 @@ static void psb_intel_clock(int refclk, struct gma_clock_t *clock) · 70 unmodified lines
71	71	clock->dot = clock->vco / clock->p;
72	72	}
73	73
74		−/**
	74	+/*
75	75	* Return the pipe currently connected to the panel fitter,
76	76	* or -1 if the panel fitter is not present or not in use
77	77	*/

drivers/gpu/drm/gma500/psb_intel_lvds.c+4−3

@@ -216,7 +216,7 @@ static void psb_intel_lvds_set_power(struct drm_device *dev, bool on) · 215 unmodified lines
216	216	dev_err(dev->dev, "set power, chip off!\n");
217	217	return;
218	218	}
219		−
	219	+
220	220	if (on) {
221	221	REG_WRITE(PP_CONTROL, REG_READ(PP_CONTROL) \|
222	222	POWER_TARGET_ON);
@@ -626,6 +626,7 @@ const struct drm_connector_funcs psb_intel_lvds_connector_funcs = { · 403 unmodified lines
626	626	/**
627	627	* psb_intel_lvds_init - setup LVDS connectors on this device
628	628	* @dev: drm device
	629	+ * @mode_dev: mode device
629	630	*
630	631	* Create the connector, register the LVDS DDC bus, and try to figure out what
631	632	* modes we can display on the LVDS panel (if present).
@@ -700,7 +701,7 @@ void psb_intel_lvds_init(struct drm_device *dev, · 68 unmodified lines
700	701	lvds_priv->i2c_bus = psb_intel_i2c_create(dev, GPIOB, "LVDSBLC_B");
701	702	if (!lvds_priv->i2c_bus) {
702	703	dev_printk(KERN_ERR,
703		− &dev->pdev->dev, "I2C bus registration failed.\n");
	704	+ dev->dev, "I2C bus registration failed.\n");
704	705	goto failed_blc_i2c;
705	706	}
706	707	lvds_priv->i2c_bus->slave_addr = 0x2C;
@@ -719,7 +720,7 @@ void psb_intel_lvds_init(struct drm_device *dev, · 12 unmodified lines
719	720	/* Set up the DDC bus. */
720	721	lvds_priv->ddc_bus = psb_intel_i2c_create(dev, GPIOC, "LVDSDDC_C");
721	722	if (!lvds_priv->ddc_bus) {
722		− dev_printk(KERN_ERR, &dev->pdev->dev,
	723	+ dev_printk(KERN_ERR, dev->dev,
723	724	"DDC bus registration " "failed.\n");
724	725	goto failed_ddc;
725	726	}

drivers/gpu/drm/gma500/psb_intel_modes.c+2−1

@@ -11,7 +11,7 @@ · 10 unmodified lines
11	11
12	12	/**
13	13	* psb_intel_ddc_probe
14		− *
	14	+ * @adapter: Associated I2C adaptor
15	15	*/
16	16	bool psb_intel_ddc_probe(struct i2c_adapter *adapter)
17	17	{
@@ -43,6 +43,7 @@ bool psb_intel_ddc_probe(struct i2c_adapter *adapter) · 25 unmodified lines
43	43	/**
44	44	* psb_intel_ddc_get_modes - get modelist from monitor
45	45	* @connector: DRM connector device to use
	46	+ * @adapter: Associated I2C adaptor
46	47	*
47	48	* Fetch the EDID information from @connector using the DDC bus.
48	49	*/

drivers/gpu/drm/gma500/psb_intel_sdvo.c+4−4

@@ -221,7 +221,7 @@ static bool · 220 unmodified lines
221	221	psb_intel_sdvo_create_enhance_property(struct psb_intel_sdvo *psb_intel_sdvo,
222	222	struct psb_intel_sdvo_connector *psb_intel_sdvo_connector);
223	223
224		−/**
	224	+/*
225	225	* Writes the SDVOB or SDVOC with the given value, but always writes both
226	226	* SDVOB and SDVOC to work around apparent hardware issues (according to
227	227	* comments in the BIOS).
@@ -588,7 +588,7 @@ static bool psb_intel_sdvo_set_target_input(struct psb_intel_sdvo *psb_intel_sdv · 360 unmodified lines
588	588	&targets, sizeof(targets));
589	589	}
590	590
591		−/**
	591	+/*
592	592	* Return whether each input is trained.
593	593	*
594	594	* This function is making an assumption about the layout of the response,
@@ -1818,7 +1818,7 @@ psb_intel_sdvo_guess_ddc_bus(struct psb_intel_sdvo *sdvo) · 1223 unmodified lines
1818	1818	#endif
1819	1819	}
1820	1820
1821		−/**
	1821	+/*
1822	1822	* Choose the appropriate DDC bus for control bus switch command for this
1823	1823	* SDVO output based on the controlled output.
1824	1824	*
@@ -2406,7 +2406,7 @@ psb_intel_sdvo_init_ddc_proxy(struct psb_intel_sdvo *sdvo, · 581 unmodified lines
2406	2406	sdvo->ddc.owner = THIS_MODULE;
2407	2407	sdvo->ddc.class = I2C_CLASS_DDC;
2408	2408	snprintf(sdvo->ddc.name, I2C_NAME_SIZE, "SDVO DDC proxy");
2409		− sdvo->ddc.dev.parent = &dev->pdev->dev;
	2409	+ sdvo->ddc.dev.parent = dev->dev;
2410	2410	sdvo->ddc.algo_data = sdvo;
2411	2411	sdvo->ddc.algo = &psb_intel_sdvo_ddc_proxy;
2412	2412

drivers/gpu/drm/gma500/psb_irq.c+1−2

@@ -126,9 +126,8 @@ static void mid_disable_pipe_event(struct drm_psb_private *dev_priv, int pipe) · 125 unmodified lines
126	126	}
127	127	}
128	128
129		−/**
	129	+/*
130	130	* Display controller interrupt handler for pipe event.
131		− *
132	131	*/
133	132	static void mid_pipe_event_handler(struct drm_device *dev, int pipe)
134	133	{

drivers/gpu/drm/gma500/tc35876x-dsi-lvds.c+18−18

@@ -454,13 +454,13 @@ static void tc35876x_brightness_init(struct drm_device *dev) · 453 unmodified lines
454	454	ret = intel_scu_ipc_ioread8(GPIOPWMCTRL, &pwmctrl);
455	455	if (ret \|\| pwmctrl != 0x01) {
456	456	if (ret)
457		− dev_err(&dev->pdev->dev, "GPIOPWMCTRL read failed\n");
	457	+ dev_err(dev->dev, "GPIOPWMCTRL read failed\n");
458	458	else
459		− dev_warn(&dev->pdev->dev, "GPIOPWMCTRL was not set to system clock (pwmctrl = 0x%02x)\n", pwmctrl);
	459	+ dev_warn(dev->dev, "GPIOPWMCTRL was not set to system clock (pwmctrl = 0x%02x)\n", pwmctrl);
460	460
461	461	ret = intel_scu_ipc_iowrite8(GPIOPWMCTRL, 0x01);
462	462	if (ret)
463		− dev_err(&dev->pdev->dev, "GPIOPWMCTRL set failed\n");
	463	+ dev_err(dev->dev, "GPIOPWMCTRL set failed\n");
464	464	}
465	465
466	466	clkdiv = calc_clkdiv(SYSTEMCLK, PWM_FREQUENCY);
@@ -470,9 +470,9 @@ static void tc35876x_brightness_init(struct drm_device *dev) · 3 unmodified lines
470	470	ret = intel_scu_ipc_iowrite8(PWM0CLKDIV0, clkdiv & 0xff);
471	471
472	472	if (ret)
473		− dev_err(&dev->pdev->dev, "PWM0CLKDIV set failed\n");
	473	+ dev_err(dev->dev, "PWM0CLKDIV set failed\n");
474	474	else
475		− dev_dbg(&dev->pdev->dev, "PWM0CLKDIV set to 0x%04x (%d Hz)\n",
	475	+ dev_dbg(dev->dev, "PWM0CLKDIV set to 0x%04x (%d Hz)\n",
476	476	clkdiv, PWM_FREQUENCY);
477	477	}
478	478
@@ -575,7 +575,7 @@ static struct drm_display_mode tc35876x_get_config_mode(struct drm_device dev) · 96 unmodified lines
575	575	{
576	576	struct drm_display_mode *mode;
577	577
578		− dev_dbg(&dev->pdev->dev, "%s\n", __func__);
	578	+ dev_dbg(dev->dev, "%s\n", __func__);
579	579
580	580	mode = kzalloc(sizeof(*mode), GFP_KERNEL);
581	581	if (!mode)
@@ -592,15 +592,15 @@ static struct drm_display_mode tc35876x_get_config_mode(struct drm_device dev) · 10 unmodified lines
592	592	mode->vtotal = 838;
593	593	mode->clock = 33324 << 1;
594	594
595		− dev_info(&dev->pdev->dev, "hdisplay(w) = %d\n", mode->hdisplay);
596		− dev_info(&dev->pdev->dev, "vdisplay(h) = %d\n", mode->vdisplay);
597		− dev_info(&dev->pdev->dev, "HSS = %d\n", mode->hsync_start);
598		− dev_info(&dev->pdev->dev, "HSE = %d\n", mode->hsync_end);
599		− dev_info(&dev->pdev->dev, "htotal = %d\n", mode->htotal);
600		− dev_info(&dev->pdev->dev, "VSS = %d\n", mode->vsync_start);
601		− dev_info(&dev->pdev->dev, "VSE = %d\n", mode->vsync_end);
602		− dev_info(&dev->pdev->dev, "vtotal = %d\n", mode->vtotal);
603		− dev_info(&dev->pdev->dev, "clock = %d\n", mode->clock);
	595	+ dev_info(dev->dev, "hdisplay(w) = %d\n", mode->hdisplay);
	596	+ dev_info(dev->dev, "vdisplay(h) = %d\n", mode->vdisplay);
	597	+ dev_info(dev->dev, "HSS = %d\n", mode->hsync_start);
	598	+ dev_info(dev->dev, "HSE = %d\n", mode->hsync_end);
	599	+ dev_info(dev->dev, "htotal = %d\n", mode->htotal);
	600	+ dev_info(dev->dev, "VSS = %d\n", mode->vsync_start);
	601	+ dev_info(dev->dev, "VSE = %d\n", mode->vsync_end);
	602	+ dev_info(dev->dev, "vtotal = %d\n", mode->vtotal);
	603	+ dev_info(dev->dev, "clock = %d\n", mode->clock);
604	604
605	605	drm_mode_set_name(mode);
606	606	drm_mode_set_crtcinfo(mode, 0);
@@ -775,19 +775,19 @@ void tc35876x_init(struct drm_device *dev) · 168 unmodified lines
775	775	{
776	776	int r;
777	777
778		− dev_dbg(&dev->pdev->dev, "%s\n", __func__);
	778	+ dev_dbg(dev->dev, "%s\n", __func__);
779	779
780	780	cmi_lcd_hack_create_device();
781	781
782	782	r = i2c_add_driver(&cmi_lcd_i2c_driver);
783	783	if (r < 0)
784		− dev_err(&dev->pdev->dev,
	784	+ dev_err(dev->dev,
785	785	"%s: i2c_add_driver() for %s failed (%d)\n",
786	786	__func__, cmi_lcd_i2c_driver.driver.name, r);
787	787
788	788	r = i2c_add_driver(&tc35876x_bridge_i2c_driver);
789	789	if (r < 0)
790		− dev_err(&dev->pdev->dev,
	790	+ dev_err(dev->dev,
791	791	"%s: i2c_add_driver() for %s failed (%d)\n",
792	792	__func__, tc35876x_bridge_i2c_driver.driver.name, r);
793	793

drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_drv.c+6−7

@@ -211,7 +211,7 @@ static void hibmc_hw_config(struct hibmc_drm_private *priv) · 210 unmodified lines
211	211	static int hibmc_hw_map(struct hibmc_drm_private *priv)
212	212	{
213	213	struct drm_device *dev = &priv->dev;
214		− struct pci_dev *pdev = dev->pdev;
	214	+ struct pci_dev *pdev = to_pci_dev(dev->dev);
215	215	resource_size_t addr, size, ioaddr, iosize;
216	216
217	217	ioaddr = pci_resource_start(pdev, 1);
@@ -255,13 +255,14 @@ static int hibmc_unload(struct drm_device *dev) · 37 unmodified lines
255	255	if (dev->irq_enabled)
256	256	drm_irq_uninstall(dev);
257	257
258		− pci_disable_msi(dev->pdev);
	258	+ pci_disable_msi(to_pci_dev(dev->dev));
259	259
260	260	return 0;
261	261	}
262	262
263	263	static int hibmc_load(struct drm_device *dev)
264	264	{
	265	+ struct pci_dev *pdev = to_pci_dev(dev->dev);
265	266	struct hibmc_drm_private *priv = to_hibmc_drm_private(dev);
266	267	int ret;
267	268
@@ -269,8 +270,7 @@ static int hibmc_load(struct drm_device *dev) · 1 unmodified line
269	270	if (ret)
270	271	goto err;
271	272
272		− ret = drmm_vram_helper_init(dev, pci_resource_start(dev->pdev, 0),
273		− priv->fb_size);
	273	+ ret = drmm_vram_helper_init(dev, pci_resource_start(pdev, 0), priv->fb_size);
274	274	if (ret) {
275	275	drm_err(dev, "Error initializing VRAM MM; %d\n", ret);
276	276	goto err;
@@ -286,11 +286,11 @@ static int hibmc_load(struct drm_device *dev) · 9 unmodified lines
286	286	goto err;
287	287	}
288	288
289		− ret = pci_enable_msi(dev->pdev);
	289	+ ret = pci_enable_msi(pdev);
290	290	if (ret) {
291	291	drm_warn(dev, "enabling MSI failed: %d\n", ret);
292	292	} else {
293		− ret = drm_irq_install(dev, dev->pdev->irq);
	293	+ ret = drm_irq_install(dev, pdev->irq);
294	294	if (ret)
295	295	drm_warn(dev, "install irq failed: %d\n", ret);
296	296	}
@@ -326,7 +326,6 @@ static int hibmc_pci_probe(struct pci_dev *pdev, · 29 unmodified lines
326	326	}
327	327
328	328	dev = &priv->dev;
329		− dev->pdev = pdev;
330	329	pci_set_drvdata(pdev, dev);
331	330
332	331	ret = pcim_enable_device(pdev);

drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_i2c.c+1−1

@@ -83,7 +83,7 @@ int hibmc_ddc_create(struct drm_device *drm_dev, · 82 unmodified lines
83	83	connector->adapter.owner = THIS_MODULE;
84	84	connector->adapter.class = I2C_CLASS_DDC;
85	85	snprintf(connector->adapter.name, I2C_NAME_SIZE, "HIS i2c bit bus");
86		− connector->adapter.dev.parent = &drm_dev->pdev->dev;
	86	+ connector->adapter.dev.parent = drm_dev->dev;
87	87	i2c_set_adapdata(&connector->adapter, connector);
88	88	connector->adapter.algo_data = &connector->bit_data;
89	89

drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_vdac.c+4−14

@@ -14,6 +14,7 @@ · 13 unmodified lines
14	14	#include <drm/drm_atomic_helper.h>
15	15	#include <drm/drm_probe_helper.h>
16	16	#include <drm/drm_print.h>
	17	+#include <drm/drm_simple_kms_helper.h>
17	18
18	19	#include "hibmc_drm_drv.h"
19	20	#include "hibmc_drm_regs.h"
@@ -42,12 +43,6 @@ out: · 22 unmodified lines
42	43	return count;
43	44	}
44	45
45		−static enum drm_mode_status hibmc_connector_mode_valid(struct drm_connector *connector,
46		− struct drm_display_mode *mode)
47		−{
48		− return MODE_OK;
49		−}
50		−
51	46	static void hibmc_connector_destroy(struct drm_connector *connector)
52	47	{
53	48	struct hibmc_connector *hibmc_connector = to_hibmc_connector(connector);
@@ -59,7 +54,6 @@ static void hibmc_connector_destroy(struct drm_connector *connector) · 5 unmodified lines
59	54	static const struct drm_connector_helper_funcs
60	55	hibmc_connector_helper_funcs = {
61	56	.get_modes = hibmc_connector_get_modes,
62		− .mode_valid = hibmc_connector_mode_valid,
63	57	};
64	58
65	59	static const struct drm_connector_funcs hibmc_connector_funcs = {
@@ -90,15 +84,12 @@ static const struct drm_encoder_helper_funcs hibmc_encoder_helper_funcs = { · 24 unmodified lines
90	84	.mode_set = hibmc_encoder_mode_set,
91	85	};
92	86
93		−static const struct drm_encoder_funcs hibmc_encoder_funcs = {
94		− .destroy = drm_encoder_cleanup,
95		−};
96		−
97	87	int hibmc_vdac_init(struct hibmc_drm_private *priv)
98	88	{
99	89	struct drm_device *dev = &priv->dev;
100	90	struct hibmc_connector *hibmc_connector = &priv->connector;
101	91	struct drm_encoder *encoder = &priv->encoder;
	92	+ struct drm_crtc *crtc = &priv->crtc;
102	93	struct drm_connector *connector = &hibmc_connector->base;
103	94	int ret;
104	95
@@ -108,9 +99,8 @@ int hibmc_vdac_init(struct hibmc_drm_private *priv) · 3 unmodified lines
108	99	return ret;
109	100	}
110	101
111		− encoder->possible_crtcs = 0x1;
112		− ret = drm_encoder_init(dev, encoder, &hibmc_encoder_funcs,
113		− DRM_MODE_ENCODER_DAC, NULL);
	102	+ encoder->possible_crtcs = drm_crtc_mask(crtc);
	103	+ ret = drm_simple_encoder_init(dev, encoder, DRM_MODE_ENCODER_DAC);
114	104	if (ret) {
115	105	drm_err(dev, "failed to init encoder: %d\n", ret);
116	106	return ret;

drivers/gpu/drm/mga/mga_ioc32.c+7−7

@@ -1,4 +1,4 @@
1		−/**
	1	+/*
2	2	* \file mga_ioc32.c
3	3	*
4	4	* 32-bit ioctl compatibility routines for the MGA DRM.
@@ -159,13 +159,13 @@ static struct { · 154 unmodified lines
159	159	};
160	160
161	161	/**
162		− * Called whenever a 32-bit process running under a 64-bit kernel
163		− * performs an ioctl on /dev/dri/card<n>.
	162	+ * mga_compat_ioctl - Called whenever a 32-bit process running under
	163	+ * a 64-bit kernel performs an ioctl on /dev/dri/card<n>.
164	164	*
165		− * \param filp file pointer.
166		− * \param cmd command.
167		− * \param arg user argument.
168		− * \return zero on success or negative number on failure.
	165	+ * @filp: file pointer.
	166	+ * @cmd: command.
	167	+ * @arg: user argument.
	168	+ * return: zero on success or negative number on failure.
169	169	*/
170	170	long mga_compat_ioctl(struct file *filp, unsigned int cmd, unsigned long arg)
171	171	{

drivers/gpu/drm/mgag200/mgag200_drv.c+11−9

@@ -47,10 +47,11 @@ static const struct drm_driver mgag200_driver = { · 46 unmodified lines
47	47	static bool mgag200_has_sgram(struct mga_device *mdev)
48	48	{
49	49	struct drm_device *dev = &mdev->base;
	50	+ struct pci_dev *pdev = to_pci_dev(dev->dev);
50	51	u32 option;
51	52	int ret;
52	53
53		− ret = pci_read_config_dword(dev->pdev, PCI_MGA_OPTION, &option);
	54	+ ret = pci_read_config_dword(pdev, PCI_MGA_OPTION, &option);
54	55	if (drm_WARN(dev, ret, "failed to read PCI config dword: %d\n", ret))
55	56	return false;
56	57
@@ -60,6 +61,7 @@ static bool mgag200_has_sgram(struct mga_device *mdev) · 3 unmodified lines
60	61	static int mgag200_regs_init(struct mga_device *mdev)
61	62	{
62	63	struct drm_device *dev = &mdev->base;
	64	+ struct pci_dev *pdev = to_pci_dev(dev->dev);
63	65	u32 option, option2;
64	66	u8 crtcext3;
65	67
@@ -99,13 +101,13 @@ static int mgag200_regs_init(struct mga_device *mdev) · 33 unmodified lines
99	101	}
100	102
101	103	if (option)
102		− pci_write_config_dword(dev->pdev, PCI_MGA_OPTION, option);
	104	+ pci_write_config_dword(pdev, PCI_MGA_OPTION, option);
103	105	if (option2)
104		− pci_write_config_dword(dev->pdev, PCI_MGA_OPTION2, option2);
	106	+ pci_write_config_dword(pdev, PCI_MGA_OPTION2, option2);
105	107
106	108	/* BAR 1 contains registers */
107		− mdev->rmmio_base = pci_resource_start(dev->pdev, 1);
108		− mdev->rmmio_size = pci_resource_len(dev->pdev, 1);
	109	+ mdev->rmmio_base = pci_resource_start(pdev, 1);
	110	+ mdev->rmmio_size = pci_resource_len(pdev, 1);
109	111
110	112	if (!devm_request_mem_region(dev->dev, mdev->rmmio_base,
111	113	mdev->rmmio_size, "mgadrmfb_mmio")) {
@@ -113,7 +115,7 @@ static int mgag200_regs_init(struct mga_device *mdev) · 1 unmodified line
113	115	return -ENOMEM;
114	116	}
115	117
116		− mdev->rmmio = pcim_iomap(dev->pdev, 1, 0);
	118	+ mdev->rmmio = pcim_iomap(pdev, 1, 0);
117	119	if (mdev->rmmio == NULL)
118	120	return -ENOMEM;
119	121
@@ -218,6 +220,7 @@ static void mgag200_g200_interpret_bios(struct mga_device *mdev, · 98 unmodified lines
218	220	static void mgag200_g200_init_refclk(struct mga_device *mdev)
219	221	{
220	222	struct drm_device *dev = &mdev->base;
	223	+ struct pci_dev *pdev = to_pci_dev(dev->dev);
221	224	unsigned char __iomem *rom;
222	225	unsigned char *bios;
223	226	size_t size;
@@ -226,7 +229,7 @@ static void mgag200_g200_init_refclk(struct mga_device *mdev) · 2 unmodified lines
226	229	mdev->model.g200.pclk_max = 230000;
227	230	mdev->model.g200.ref_clk = 27050;
228	231
229		− rom = pci_map_rom(dev->pdev, &size);
	232	+ rom = pci_map_rom(pdev, &size);
230	233	if (!rom)
231	234	return;
232	235
@@ -244,7 +247,7 @@ static void mgag200_g200_init_refclk(struct mga_device *mdev) · 11 unmodified lines
244	247
245	248	vfree(bios);
246	249	out:
247		− pci_unmap_rom(dev->pdev, rom);
	250	+ pci_unmap_rom(pdev, rom);
248	251	}
249	252
250	253	static void mgag200_g200se_init_unique_id(struct mga_device *mdev)
@@ -301,7 +304,6 @@ mgag200_device_create(struct pci_dev *pdev, unsigned long flags) · 50 unmodified lines
301	304	return mdev;
302	305	dev = &mdev->base;
303	306
304		− dev->pdev = pdev;
305	307	pci_set_drvdata(pdev, dev);
306	308
307	309	ret = mgag200_device_init(mdev, flags);

drivers/gpu/drm/mgag200/mgag200_i2c.c+1−1

@@ -126,7 +126,7 @@ struct mga_i2c_chan mgag200_i2c_create(struct drm_device dev) · 125 unmodified lines
126	126	i2c->clock = clock;
127	127	i2c->adapter.owner = THIS_MODULE;
128	128	i2c->adapter.class = I2C_CLASS_DDC;
129		− i2c->adapter.dev.parent = &dev->pdev->dev;
	129	+ i2c->adapter.dev.parent = dev->dev;
130	130	i2c->dev = dev;
131	131	i2c_set_adapdata(&i2c->adapter, i2c);
132	132	snprintf(i2c->adapter.name, sizeof(i2c->adapter.name), "mga i2c");

drivers/gpu/drm/mgag200/mgag200_mm.c+6−4

@@ -78,11 +78,12 @@ static size_t mgag200_probe_vram(struct mga_device mdev, void __iomem mem, · 77 unmodified lines
78	78	static void mgag200_mm_release(struct drm_device dev, void ptr)
79	79	{
80	80	struct mga_device *mdev = to_mga_device(dev);
	81	+ struct pci_dev *pdev = to_pci_dev(dev->dev);
81	82
82	83	mdev->vram_fb_available = 0;
83	84	iounmap(mdev->vram);
84		− arch_io_free_memtype_wc(pci_resource_start(dev->pdev, 0),
85		− pci_resource_len(dev->pdev, 0));
	85	+ arch_io_free_memtype_wc(pci_resource_start(pdev, 0),
	86	+ pci_resource_len(pdev, 0));
86	87	arch_phys_wc_del(mdev->fb_mtrr);
87	88	mdev->fb_mtrr = 0;
88	89	}
@@ -90,6 +91,7 @@ static void mgag200_mm_release(struct drm_device dev, void ptr) · 1 unmodified line
90	91	int mgag200_mm_init(struct mga_device *mdev)
91	92	{
92	93	struct drm_device *dev = &mdev->base;
	94	+ struct pci_dev *pdev = to_pci_dev(dev->dev);
93	95	u8 misc;
94	96	resource_size_t start, len;
95	97	int ret;
@@ -102,8 +104,8 @@ int mgag200_mm_init(struct mga_device *mdev) · 6 unmodified lines
102	104	WREG8(MGA_MISC_OUT, misc);
103	105
104	106	/* BAR 0 is VRAM */
105		− start = pci_resource_start(dev->pdev, 0);
106		− len = pci_resource_len(dev->pdev, 0);
	107	+ start = pci_resource_start(pdev, 0);
	108	+ len = pci_resource_len(pdev, 0);
107	109
108	110	if (!devm_request_mem_region(dev->dev, start, len, "mgadrmfb_vram")) {
109	111	drm_err(dev, "can't reserve VRAM\n");

drivers/gpu/drm/nouveau/dispnv04/arb.c+7−5

@@ -200,16 +200,17 @@ nv04_update_arb(struct drm_device *dev, int VClk, int bpp, · 199 unmodified lines
200	200	int MClk = nouveau_hw_get_clock(dev, PLL_MEMORY);
201	201	int NVClk = nouveau_hw_get_clock(dev, PLL_CORE);
202	202	uint32_t cfg1 = nvif_rd32(device, NV04_PFB_CFG1);
	203	+ struct pci_dev *pdev = to_pci_dev(dev->dev);
203	204
204	205	sim_data.pclk_khz = VClk;
205	206	sim_data.mclk_khz = MClk;
206	207	sim_data.nvclk_khz = NVClk;
207	208	sim_data.bpp = bpp;
208	209	sim_data.two_heads = nv_two_heads(dev);
209		− if ((dev->pdev->device & 0xffff) == 0x01a0 /CHIPSET_NFORCE/ \|\|
210		− (dev->pdev->device & 0xffff) == 0x01f0 /CHIPSET_NFORCE2/) {
	210	+ if ((pdev->device & 0xffff) == 0x01a0 /CHIPSET_NFORCE/ \|\|
	211	+ (pdev->device & 0xffff) == 0x01f0 /CHIPSET_NFORCE2/) {
211	212	uint32_t type;
212		− int domain = pci_domain_nr(dev->pdev->bus);
	213	+ int domain = pci_domain_nr(pdev->bus);
213	214
214	215	pci_read_config_dword(pci_get_domain_bus_and_slot(domain, 0, 1),
215	216	0x7c, &type);
@@ -251,11 +252,12 @@ void · 35 unmodified lines
251	252	nouveau_calc_arb(struct drm_device dev, int vclk, int bpp, int burst, int *lwm)
252	253	{
253	254	struct nouveau_drm *drm = nouveau_drm(dev);
	255	+ struct pci_dev *pdev = to_pci_dev(dev->dev);
254	256
255	257	if (drm->client.device.info.family < NV_DEVICE_INFO_V0_KELVIN)
256	258	nv04_update_arb(dev, vclk, bpp, burst, lwm);
257		− else if ((dev->pdev->device & 0xfff0) == 0x0240 /CHIPSET_C51/ \|\|
258		− (dev->pdev->device & 0xfff0) == 0x03d0 /CHIPSET_C512/) {
	259	+ else if ((pdev->device & 0xfff0) == 0x0240 /CHIPSET_C51/ \|\|
	260	+ (pdev->device & 0xfff0) == 0x03d0 /CHIPSET_C512/) {
259	261	*burst = 128;
260	262	*lwm = 0x0480;
261	263	} else

drivers/gpu/drm/nouveau/dispnv04/dfp.c+3−2

@@ -488,12 +488,13 @@ static void nv04_dfp_update_backlight(struct drm_encoder *encoder, int mode) · 487 unmodified lines
488	488	#ifdef __powerpc__
489	489	struct drm_device *dev = encoder->dev;
490	490	struct nvif_object *device = &nouveau_drm(dev)->client.device.object;
	491	+ struct pci_dev *pdev = to_pci_dev(dev->dev);
491	492
492	493	/* BIOS scripts usually take care of the backlight, thanks
493	494	* Apple for your consistency.
494	495	*/
495		− if (dev->pdev->device == 0x0174 \|\| dev->pdev->device == 0x0179 \|\|
496		− dev->pdev->device == 0x0189 \|\| dev->pdev->device == 0x0329) {
	496	+ if (pdev->device == 0x0174 \|\| pdev->device == 0x0179 \|\|
	497	+ pdev->device == 0x0189 \|\| pdev->device == 0x0329) {
497	498	if (mode == DRM_MODE_DPMS_ON) {
498	499	nvif_mask(device, NV_PBUS_DEBUG_DUALHEAD_CTL, 1 << 31, 1 << 31);
499	500	nvif_mask(device, NV_PCRTC_GPIO_EXT, 3, 1);

drivers/gpu/drm/nouveau/dispnv04/disp.h+8−6

@@ -130,7 +130,7 @@ static inline bool · 129 unmodified lines
130	130	nv_two_heads(struct drm_device *dev)
131	131	{
132	132	struct nouveau_drm *drm = nouveau_drm(dev);
133		− const int impl = dev->pdev->device & 0x0ff0;
	133	+ const int impl = to_pci_dev(dev->dev)->device & 0x0ff0;
134	134
135	135	if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_CELSIUS && impl != 0x0100 &&
136	136	impl != 0x0150 && impl != 0x01a0 && impl != 0x0200)
@@ -142,14 +142,14 @@ nv_two_heads(struct drm_device *dev) · 5 unmodified lines
142	142	static inline bool
143	143	nv_gf4_disp_arch(struct drm_device *dev)
144	144	{
145		− return nv_two_heads(dev) && (dev->pdev->device & 0x0ff0) != 0x0110;
	145	+ return nv_two_heads(dev) && (to_pci_dev(dev->dev)->device & 0x0ff0) != 0x0110;
146	146	}
147	147
148	148	static inline bool
149	149	nv_two_reg_pll(struct drm_device *dev)
150	150	{
151	151	struct nouveau_drm *drm = nouveau_drm(dev);
152		− const int impl = dev->pdev->device & 0x0ff0;
	152	+ const int impl = to_pci_dev(dev->dev)->device & 0x0ff0;
153	153
154	154	if (impl == 0x0310 \|\| impl == 0x0340 \|\| drm->client.device.info.family >= NV_DEVICE_INFO_V0_CURIE)
155	155	return true;
@@ -160,9 +160,11 @@ static inline bool · 4 unmodified lines
160	160	nv_match_device(struct drm_device *dev, unsigned device,
161	161	unsigned sub_vendor, unsigned sub_device)
162	162	{
163		− return dev->pdev->device == device &&
164		− dev->pdev->subsystem_vendor == sub_vendor &&
165		− dev->pdev->subsystem_device == sub_device;
	163	+ struct pci_dev *pdev = to_pci_dev(dev->dev);
	164	+
	165	+ return pdev->device == device &&
	166	+ pdev->subsystem_vendor == sub_vendor &&
	167	+ pdev->subsystem_device == sub_device;
166	168	}
167	169
168	170	#include <subdev/bios/init.h>

drivers/gpu/drm/nouveau/dispnv04/hw.c+6−4

@@ -214,14 +214,15 @@ nouveau_hw_pllvals_to_clk(struct nvkm_pll_vals *pv) · 213 unmodified lines
214	214	int
215	215	nouveau_hw_get_clock(struct drm_device *dev, enum nvbios_pll_type plltype)
216	216	{
	217	+ struct pci_dev *pdev = to_pci_dev(dev->dev);
217	218	struct nvkm_pll_vals pllvals;
218	219	int ret;
219	220	int domain;
220	221
221		− domain = pci_domain_nr(dev->pdev->bus);
	222	+ domain = pci_domain_nr(pdev->bus);
222	223
223	224	if (plltype == PLL_MEMORY &&
224		− (dev->pdev->device & 0x0ff0) == CHIPSET_NFORCE) {
	225	+ (pdev->device & 0x0ff0) == CHIPSET_NFORCE) {
225	226	uint32_t mpllP;
226	227	pci_read_config_dword(pci_get_domain_bus_and_slot(domain, 0, 3),
227	228	0x6c, &mpllP);
@@ -232,7 +233,7 @@ nouveau_hw_get_clock(struct drm_device *dev, enum nvbios_pll_type plltype) · 4 unmodified lines
232	233	return 400000 / mpllP;
233	234	} else
234	235	if (plltype == PLL_MEMORY &&
235		− (dev->pdev->device & 0xff0) == CHIPSET_NFORCE2) {
	236	+ (pdev->device & 0xff0) == CHIPSET_NFORCE2) {
236	237	uint32_t clock;
237	238
238	239	pci_read_config_dword(pci_get_domain_bus_and_slot(domain, 0, 5),
@@ -309,6 +310,7 @@ void · 70 unmodified lines
309	310	nouveau_hw_save_vga_fonts(struct drm_device *dev, bool save)
310	311	{
311	312	struct nouveau_drm *drm = nouveau_drm(dev);
	313	+ struct pci_dev *pdev = to_pci_dev(dev->dev);
312	314	uint8_t misc, gr4, gr5, gr6, seq2, seq4;
313	315	bool graphicsmode;
314	316	unsigned plane;
@@ -327,7 +329,7 @@ nouveau_hw_save_vga_fonts(struct drm_device *dev, bool save) · 12 unmodified lines
327	329	NV_INFO(drm, "%sing VGA fonts\n", save ? "Sav" : "Restor");
328	330
329	331	/* map first 64KiB of VRAM, holds VGA fonts etc */
330		− iovram = ioremap(pci_resource_start(dev->pdev, 1), 65536);
	332	+ iovram = ioremap(pci_resource_start(pdev, 1), 65536);
331	333	if (!iovram) {
332	334	NV_ERROR(drm, "Failed to map VRAM, "
333	335	"cannot save/restore VGA fonts.\n");

drivers/gpu/drm/nouveau/nouveau_abi16.c+4−3

@@ -181,6 +181,7 @@ nouveau_abi16_ioctl_getparam(ABI16_IOCTL_ARGS) · 180 unmodified lines
181	181	struct nvif_device *device = &drm->client.device;
182	182	struct nvkm_gr *gr = nvxx_gr(device);
183	183	struct drm_nouveau_getparam *getparam = data;
	184	+ struct pci_dev *pdev = to_pci_dev(dev->dev);
184	185
185	186	switch (getparam->param) {
186	187	case NOUVEAU_GETPARAM_CHIPSET_ID:
@@ -188,13 +189,13 @@ nouveau_abi16_ioctl_getparam(ABI16_IOCTL_ARGS) · 1 unmodified line
188	189	break;
189	190	case NOUVEAU_GETPARAM_PCI_VENDOR:
190	191	if (device->info.platform != NV_DEVICE_INFO_V0_SOC)
191		− getparam->value = dev->pdev->vendor;
	192	+ getparam->value = pdev->vendor;
192	193	else
193	194	getparam->value = 0;
194	195	break;
195	196	case NOUVEAU_GETPARAM_PCI_DEVICE:
196	197	if (device->info.platform != NV_DEVICE_INFO_V0_SOC)
197		− getparam->value = dev->pdev->device;
	198	+ getparam->value = pdev->device;
198	199	else
199	200	getparam->value = 0;
200	201	break;
@@ -205,7 +206,7 @@ nouveau_abi16_ioctl_getparam(ABI16_IOCTL_ARGS) · 4 unmodified lines
205	206	case NV_DEVICE_INFO_V0_PCIE: getparam->value = 2; break;
206	207	case NV_DEVICE_INFO_V0_SOC : getparam->value = 3; break;
207	208	case NV_DEVICE_INFO_V0_IGP :
208		− if (!pci_is_pcie(dev->pdev))
	209	+ if (!pci_is_pcie(pdev))
209	210	getparam->value = 1;
210	211	else
211	212	getparam->value = 2;

drivers/gpu/drm/nouveau/nouveau_acpi.c+1−1

@@ -377,7 +377,7 @@ nouveau_acpi_edid(struct drm_device dev, struct drm_connector connector) · 376 unmodified lines
377	377	return NULL;
378	378	}
379	379
380		− handle = ACPI_HANDLE(&dev->pdev->dev);
	380	+ handle = ACPI_HANDLE(dev->dev);
381	381	if (!handle)
382	382	return NULL;
383	383

drivers/gpu/drm/nouveau/nouveau_bios.c+8−3

@@ -110,6 +110,9 @@ static int call_lvds_manufacturer_script(struct drm_device *dev, struct dcb_outp · 109 unmodified lines
110	110	struct nvbios *bios = &drm->vbios;
111	111	uint8_t sub = bios->data[bios->fp.xlated_entry + script] + (bios->fp.link_c_increment && dcbent->or & DCB_OUTPUT_C ? 1 : 0);
112	112	uint16_t scriptofs = ROM16(bios->data[bios->init_script_tbls_ptr + sub * 2]);
	113	+#ifdef __powerpc__
	114	+ struct pci_dev *pdev = to_pci_dev(dev->dev);
	115	+#endif
113	116
114	117	if (!bios->fp.xlated_entry \|\| !sub \|\| !scriptofs)
115	118	return -EINVAL;
@@ -123,8 +126,8 @@ static int call_lvds_manufacturer_script(struct drm_device *dev, struct dcb_outp · 7 unmodified lines
123	126	#ifdef __powerpc__
124	127	/* Powerbook specific quirks */
125	128	if (script == LVDS_RESET &&
126		− (dev->pdev->device == 0x0179 \|\| dev->pdev->device == 0x0189 \|\|
127		− dev->pdev->device == 0x0329))
	129	+ (pdev->device == 0x0179 \|\| pdev->device == 0x0189 \|\|
	130	+ pdev->device == 0x0329))
128	131	nv_write_tmds(dev, dcbent->or, 0, 0x02, 0x72);
129	132	#endif
130	133
@@ -2080,11 +2083,13 @@ nouveau_bios_init(struct drm_device *dev) · 1949 unmodified lines
2080	2083	{
2081	2084	struct nouveau_drm *drm = nouveau_drm(dev);
2082	2085	struct nvbios *bios = &drm->vbios;
	2086	+ struct pci_dev *pdev;
2083	2087	int ret;
2084	2088
2085	2089	/* only relevant for PCI devices */
2086		− if (!dev->pdev)
	2090	+ if (!dev_is_pci(dev->dev))
2087	2091	return 0;
	2092	+ pdev = to_pci_dev(dev->dev);
2088	2093
2089	2094	if (!NVInitVBIOS(dev))
2090	2095	return -ENODEV;

drivers/gpu/drm/nouveau/nouveau_connector.c+6−4

@@ -411,6 +411,7 @@ static struct nouveau_encoder * · 410 unmodified lines
411	411	nouveau_connector_ddc_detect(struct drm_connector *connector)
412	412	{
413	413	struct drm_device *dev = connector->dev;
	414	+ struct pci_dev *pdev = to_pci_dev(dev->dev);
414	415	struct nouveau_encoder nv_encoder = NULL, found = NULL;
415	416	struct drm_encoder *encoder;
416	417	int ret;
@@ -438,11 +439,11 @@ nouveau_connector_ddc_detect(struct drm_connector *connector) · 21 unmodified lines
438	439	break;
439	440
440	441	if (switcheroo_ddc)
441		− vga_switcheroo_lock_ddc(dev->pdev);
	442	+ vga_switcheroo_lock_ddc(pdev);
442	443	if (nvkm_probe_i2c(nv_encoder->i2c, 0x50))
443	444	found = nv_encoder;
444	445	if (switcheroo_ddc)
445		− vga_switcheroo_unlock_ddc(dev->pdev);
	446	+ vga_switcheroo_unlock_ddc(pdev);
446	447
447	448	break;
448	449	}
@@ -490,6 +491,7 @@ nouveau_connector_set_encoder(struct drm_connector *connector, · 41 unmodified lines
490	491	struct nouveau_connector *nv_connector = nouveau_connector(connector);
491	492	struct nouveau_drm *drm = nouveau_drm(connector->dev);
492	493	struct drm_device *dev = connector->dev;
	494	+ struct pci_dev *pdev = to_pci_dev(dev->dev);
493	495
494	496	if (nv_connector->detected_encoder == nv_encoder)
495	497	return;
@@ -511,8 +513,8 @@ nouveau_connector_set_encoder(struct drm_connector *connector, · 15 unmodified lines
511	513	connector->doublescan_allowed = true;
512	514	if (drm->client.device.info.family == NV_DEVICE_INFO_V0_KELVIN \|\|
513	515	(drm->client.device.info.family == NV_DEVICE_INFO_V0_CELSIUS &&
514		− (dev->pdev->device & 0x0ff0) != 0x0100 &&
515		− (dev->pdev->device & 0x0ff0) != 0x0150))
	516	+ (pdev->device & 0x0ff0) != 0x0100 &&
	517	+ (pdev->device & 0x0ff0) != 0x0150))
516	518	/* HW is broken */
517	519	connector->interlace_allowed = false;
518	520	else

drivers/gpu/drm/nouveau/nouveau_drm.c+2−3

@@ -115,8 +115,8 @@ nouveau_platform_name(struct platform_device *platformdev) · 114 unmodified lines
115	115	static u64
116	116	nouveau_name(struct drm_device *dev)
117	117	{
118		− if (dev->pdev)
119		− return nouveau_pci_name(dev->pdev);
	118	+ if (dev_is_pci(dev->dev))
	119	+ return nouveau_pci_name(to_pci_dev(dev->dev));
120	120	else
121	121	return nouveau_platform_name(to_platform_device(dev->dev));
122	122	}
@@ -760,7 +760,6 @@ static int nouveau_drm_probe(struct pci_dev *pdev, · 637 unmodified lines
760	760	if (ret)
761	761	goto fail_drm;
762	762
763		− drm_dev->pdev = pdev;
764	763	pci_set_drvdata(pdev, drm_dev);
765	764
766	765	ret = nouveau_drm_device_init(drm_dev);

drivers/gpu/drm/nouveau/nouveau_fbcon.c+4−2

@@ -396,7 +396,9 @@ nouveau_fbcon_create(struct drm_fb_helper *helper, · 395 unmodified lines
396	396	NV_INFO(drm, "allocated %dx%d fb: 0x%llx, bo %p\n",
397	397	fb->width, fb->height, nvbo->offset, nvbo);
398	398
399		− vga_switcheroo_client_fb_set(dev->pdev, info);
	399	+ if (dev_is_pci(dev->dev))
	400	+ vga_switcheroo_client_fb_set(to_pci_dev(dev->dev), info);
	401	+
400	402	return 0;
401	403
402	404	out_unlock:
@@ -548,7 +550,7 @@ nouveau_fbcon_init(struct drm_device *dev) · 145 unmodified lines
548	550	int ret;
549	551
550	552	if (!dev->mode_config.num_crtc \|\|
551		− (dev->pdev->class >> 8) != PCI_CLASS_DISPLAY_VGA)
	553	+ (to_pci_dev(dev->dev)->class >> 8) != PCI_CLASS_DISPLAY_VGA)
552	554	return 0;
553	555
554	556	fbcon = kzalloc(sizeof(struct nouveau_fbdev), GFP_KERNEL);

drivers/gpu/drm/nouveau/nouveau_vga.c+12−8

@@ -87,18 +87,20 @@ nouveau_vga_init(struct nouveau_drm *drm) · 86 unmodified lines
87	87	{
88	88	struct drm_device *dev = drm->dev;
89	89	bool runtime = nouveau_pmops_runtime();
	90	+ struct pci_dev *pdev;
90	91
91	92	/* only relevant for PCI devices */
92		− if (!dev->pdev)
	93	+ if (!dev_is_pci(dev->dev))
93	94	return;
	95	+ pdev = to_pci_dev(dev->dev);
94	96
95		− vga_client_register(dev->pdev, dev, NULL, nouveau_vga_set_decode);
	97	+ vga_client_register(pdev, dev, NULL, nouveau_vga_set_decode);
96	98
97	99	/* don't register Thunderbolt eGPU with vga_switcheroo */
98		− if (pci_is_thunderbolt_attached(dev->pdev))
	100	+ if (pci_is_thunderbolt_attached(pdev))
99	101	return;
100	102
101		− vga_switcheroo_register_client(dev->pdev, &nouveau_switcheroo_ops, runtime);
	103	+ vga_switcheroo_register_client(pdev, &nouveau_switcheroo_ops, runtime);
102	104
103	105	if (runtime && nouveau_is_v1_dsm() && !nouveau_is_optimus())
104	106	vga_switcheroo_init_domain_pm_ops(drm->dev->dev, &drm->vga_pm_domain);
@@ -109,17 +111,19 @@ nouveau_vga_fini(struct nouveau_drm *drm) · 4 unmodified lines
109	111	{
110	112	struct drm_device *dev = drm->dev;
111	113	bool runtime = nouveau_pmops_runtime();
	114	+ struct pci_dev *pdev;
112	115
113	116	/* only relevant for PCI devices */
114		− if (!dev->pdev)
	117	+ if (!dev_is_pci(dev->dev))
115	118	return;
	119	+ pdev = to_pci_dev(dev->dev);
116	120
117		− vga_client_register(dev->pdev, NULL, NULL, NULL);
	121	+ vga_client_register(pdev, NULL, NULL, NULL);
118	122
119		− if (pci_is_thunderbolt_attached(dev->pdev))
	123	+ if (pci_is_thunderbolt_attached(pdev))
120	124	return;
121	125
122		− vga_switcheroo_unregister_client(dev->pdev);
	126	+ vga_switcheroo_unregister_client(pdev);
123	127	if (runtime && nouveau_is_v1_dsm() && !nouveau_is_optimus())
124	128	vga_switcheroo_fini_domain_pm_ops(drm->dev->dev);
125	129	}

drivers/gpu/drm/panel/panel-simple.c+2−0

@@ -2399,6 +2399,8 @@ static const struct panel_desc innolux_n116bge = { · 2398 unmodified lines
2399	2399	.width = 256,
2400	2400	.height = 144,
2401	2401	},
	2402	+ .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
	2403	+ .connector_type = DRM_MODE_CONNECTOR_eDP,
2402	2404	};
2403	2405
2404	2406	static const struct drm_display_mode innolux_n125hce_gn1_mode = {

drivers/gpu/drm/panfrost/panfrost_devfreq.c+1−0

@@ -76,6 +76,7 @@ static int panfrost_devfreq_get_dev_status(struct device *dev, · 75 unmodified lines
76	76	}
77	77
78	78	static struct devfreq_dev_profile panfrost_devfreq_profile = {
	79	+ .timer = DEVFREQ_TIMER_DELAYED,
79	80	.polling_ms = 50, /* ~3 frames */
80	81	.target = panfrost_devfreq_target,
81	82	.get_dev_status = panfrost_devfreq_get_dev_status,

drivers/gpu/drm/qxl/qxl_drv.c+1−1

@@ -163,7 +163,7 @@ DEFINE_DRM_GEM_FOPS(qxl_fops); · 162 unmodified lines
163	163
164	164	static int qxl_drm_freeze(struct drm_device *dev)
165	165	{
166		− struct pci_dev *pdev = dev->pdev;
	166	+ struct pci_dev *pdev = to_pci_dev(dev->dev);
167	167	struct qxl_device *qdev = to_qxl(dev);
168	168	int ret;
169	169

drivers/gpu/drm/qxl/qxl_ioctl.c+2−1

@@ -370,13 +370,14 @@ static int qxl_clientcap_ioctl(struct drm_device dev, void data, · 369 unmodified lines
370	370	struct drm_file *file_priv)
371	371	{
372	372	struct qxl_device *qdev = to_qxl(dev);
	373	+ struct pci_dev *pdev = to_pci_dev(dev->dev);
373	374	struct drm_qxl_clientcap *param = data;
374	375	int byte, idx;
375	376
376	377	byte = param->index / 8;
377	378	idx = param->index % 8;
378	379
379		− if (dev->pdev->revision < 4)
	380	+ if (pdev->revision < 4)
380	381	return -ENOSYS;
381	382
382	383	if (byte >= 58)

drivers/gpu/drm/qxl/qxl_irq.c+2−1

@@ -81,6 +81,7 @@ static void qxl_client_monitors_config_work_func(struct work_struct *work) · 80 unmodified lines
81	81
82	82	int qxl_irq_init(struct qxl_device *qdev)
83	83	{
	84	+ struct pci_dev *pdev = to_pci_dev(qdev->ddev.dev);
84	85	int ret;
85	86
86	87	init_waitqueue_head(&qdev->display_event);
@@ -93,7 +94,7 @@ int qxl_irq_init(struct qxl_device *qdev) · 6 unmodified lines
93	94	atomic_set(&qdev->irq_received_cursor, 0);
94	95	atomic_set(&qdev->irq_received_io_cmd, 0);
95	96	qdev->irq_received_error = 0;
96		− ret = drm_irq_install(&qdev->ddev, qdev->ddev.pdev->irq);
	97	+ ret = drm_irq_install(&qdev->ddev, pdev->irq);
97	98	qdev->ram_header->int_mask = QXL_INTERRUPT_MASK;
98	99	if (unlikely(ret != 0)) {
99	100	DRM_ERROR("Failed installing irq: %d\n", ret);

drivers/gpu/drm/qxl/qxl_kms.c+0−1

@@ -111,7 +111,6 @@ int qxl_device_init(struct qxl_device *qdev, · 110 unmodified lines
111	111	{
112	112	int r, sb;
113	113
114		− qdev->ddev.pdev = pdev;
115	114	pci_set_drvdata(pdev, &qdev->ddev);
116	115
117	116	mutex_init(&qdev->gem.mutex);

drivers/gpu/drm/r128/r128_ioc32.c+7−7

@@ -1,4 +1,4 @@
1		−/**
	1	+/*
2	2	* \file r128_ioc32.c
3	3	*
4	4	* 32-bit ioctl compatibility routines for the R128 DRM.
@@ -170,13 +170,13 @@ drm_ioctl_compat_t *r128_compat_ioctls[] = { · 165 unmodified lines
170	170	};
171	171
172	172	/**
173		− * Called whenever a 32-bit process running under a 64-bit kernel
174		− * performs an ioctl on /dev/dri/card<n>.
	173	+ * r128_compat_ioctl - Called whenever a 32-bit process running under
	174	+ * a 64-bit kernel performs an ioctl on /dev/dri/card<n>.
175	175	*
176		− * \param filp file pointer.
177		− * \param cmd command.
178		− * \param arg user argument.
179		− * \return zero on success or negative number on failure.
	176	+ * @filp: file pointer.
	177	+ * @cmd: command.
	178	+ * @arg: user argument.
	179	+ * return: zero on success or negative number on failure.
180	180	*/
181	181	long r128_compat_ioctl(struct file *filp, unsigned int cmd, unsigned long arg)
182	182	{

drivers/gpu/drm/radeon/atombios_encoders.c+3−3

@@ -2062,9 +2062,9 @@ atombios_apply_encoder_quirks(struct drm_encoder *encoder, · 2061 unmodified lines
2062	2062	struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
2063	2063
2064	2064	/* Funky macbooks */
2065		− if ((dev->pdev->device == 0x71C5) &&
2066		− (dev->pdev->subsystem_vendor == 0x106b) &&
2067		− (dev->pdev->subsystem_device == 0x0080)) {
	2065	+ if ((rdev->pdev->device == 0x71C5) &&
	2066	+ (rdev->pdev->subsystem_vendor == 0x106b) &&
	2067	+ (rdev->pdev->subsystem_device == 0x0080)) {
2068	2068	if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) {
2069	2069	uint32_t lvtma_bit_depth_control = RREG32(AVIVO_LVTMA_BIT_DEPTH_CONTROL);
2070	2070

drivers/gpu/drm/radeon/r100.c+13−14

@@ -2612,7 +2612,6 @@ int r100_asic_reset(struct radeon_device *rdev, bool hard) · 2611 unmodified lines
2612	2612
2613	2613	void r100_set_common_regs(struct radeon_device *rdev)
2614	2614	{
2615		− struct drm_device *dev = rdev->ddev;
2616	2615	bool force_dac2 = false;
2617	2616	u32 tmp;
2618	2617
@@ -2630,7 +2629,7 @@ void r100_set_common_regs(struct radeon_device *rdev) · 11 unmodified lines
2630	2629	* don't report it in the bios connector
2631	2630	* table.
2632	2631	*/
2633		− switch (dev->pdev->device) {
	2632	+ switch (rdev->pdev->device) {
2634	2633	/* RN50 */
2635	2634	case 0x515e:
2636	2635	case 0x5969:
@@ -2640,17 +2639,17 @@ void r100_set_common_regs(struct radeon_device *rdev) · 3 unmodified lines
2640	2639	case 0x5159:
2641	2640	case 0x515a:
2642	2641	/* DELL triple head servers */
2643		− if ((dev->pdev->subsystem_vendor == 0x1028 /* DELL */) &&
2644		− ((dev->pdev->subsystem_device == 0x016c) \|\|
2645		− (dev->pdev->subsystem_device == 0x016d) \|\|
2646		− (dev->pdev->subsystem_device == 0x016e) \|\|
2647		− (dev->pdev->subsystem_device == 0x016f) \|\|
2648		− (dev->pdev->subsystem_device == 0x0170) \|\|
2649		− (dev->pdev->subsystem_device == 0x017d) \|\|
2650		− (dev->pdev->subsystem_device == 0x017e) \|\|
2651		− (dev->pdev->subsystem_device == 0x0183) \|\|
2652		− (dev->pdev->subsystem_device == 0x018a) \|\|
2653		− (dev->pdev->subsystem_device == 0x019a)))
	2642	+ if ((rdev->pdev->subsystem_vendor == 0x1028 /* DELL */) &&
	2643	+ ((rdev->pdev->subsystem_device == 0x016c) \|\|
	2644	+ (rdev->pdev->subsystem_device == 0x016d) \|\|
	2645	+ (rdev->pdev->subsystem_device == 0x016e) \|\|
	2646	+ (rdev->pdev->subsystem_device == 0x016f) \|\|
	2647	+ (rdev->pdev->subsystem_device == 0x0170) \|\|
	2648	+ (rdev->pdev->subsystem_device == 0x017d) \|\|
	2649	+ (rdev->pdev->subsystem_device == 0x017e) \|\|
	2650	+ (rdev->pdev->subsystem_device == 0x0183) \|\|
	2651	+ (rdev->pdev->subsystem_device == 0x018a) \|\|
	2652	+ (rdev->pdev->subsystem_device == 0x019a)))
2654	2653	force_dac2 = true;
2655	2654	break;
2656	2655	}
@@ -2798,7 +2797,7 @@ void r100_vram_init_sizes(struct radeon_device *rdev) · 141 unmodified lines
2798	2797	rdev->mc.real_vram_size = 8192 * 1024;
2799	2798	WREG32(RADEON_CONFIG_MEMSIZE, rdev->mc.real_vram_size);
2800	2799	}
2801		− /* Fix for RN50, M6, M7 with 8/16/32(??) MBs of VRAM -
	2800	+ /* Fix for RN50, M6, M7 with 8/16/32(??) MBs of VRAM -
2802	2801	* Novell bug 204882 + along with lots of ubuntu ones
2803	2802	*/
2804	2803	if (rdev->mc.aper_size > config_aper_size)

drivers/gpu/drm/radeon/radeon.h+19−16

@@ -2313,6 +2313,9 @@ struct radeon_device { · 2312 unmodified lines
2313	2313	struct device *dev;
2314	2314	struct drm_device *ddev;
2315	2315	struct pci_dev *pdev;
	2316	+#ifdef __alpha__
	2317	+ struct pci_controller *hose;
	2318	+#endif
2316	2319	struct rw_semaphore exclusive_lock;
2317	2320	/* ASIC */
2318	2321	union radeon_asic_config config;
@@ -2622,14 +2625,14 @@ void r100_pll_errata_after_index(struct radeon_device *rdev); · 303 unmodified lines
2622	2625	(rdev->family == CHIP_RV410) \|\| \
2623	2626	(rdev->family == CHIP_RS400) \|\| \
2624	2627	(rdev->family == CHIP_RS480))
2625		−#define ASIC_IS_X2(rdev) ((rdev->ddev->pdev->device == 0x9441) \|\| \
2626		− (rdev->ddev->pdev->device == 0x9443) \|\| \
2627		− (rdev->ddev->pdev->device == 0x944B) \|\| \
2628		− (rdev->ddev->pdev->device == 0x9506) \|\| \
2629		− (rdev->ddev->pdev->device == 0x9509) \|\| \
2630		− (rdev->ddev->pdev->device == 0x950F) \|\| \
2631		− (rdev->ddev->pdev->device == 0x689C) \|\| \
2632		− (rdev->ddev->pdev->device == 0x689D))
	2628	+#define ASIC_IS_X2(rdev) ((rdev->pdev->device == 0x9441) \|\| \
	2629	+ (rdev->pdev->device == 0x9443) \|\| \
	2630	+ (rdev->pdev->device == 0x944B) \|\| \
	2631	+ (rdev->pdev->device == 0x9506) \|\| \
	2632	+ (rdev->pdev->device == 0x9509) \|\| \
	2633	+ (rdev->pdev->device == 0x950F) \|\| \
	2634	+ (rdev->pdev->device == 0x689C) \|\| \
	2635	+ (rdev->pdev->device == 0x689D))
2633	2636	#define ASIC_IS_AVIVO(rdev) ((rdev->family >= CHIP_RS600))
2634	2637	#define ASIC_IS_DCE2(rdev) ((rdev->family == CHIP_RS600) \|\| \
2635	2638	(rdev->family == CHIP_RS690) \|\| \
@@ -2652,14 +2655,14 @@ void r100_pll_errata_after_index(struct radeon_device *rdev); · 16 unmodified lines
2652	2655	#define ASIC_IS_DCE83(rdev) ((rdev->family == CHIP_KABINI) \|\| \
2653	2656	(rdev->family == CHIP_MULLINS))
2654	2657
2655		−#define ASIC_IS_LOMBOK(rdev) ((rdev->ddev->pdev->device == 0x6849) \|\| \
2656		− (rdev->ddev->pdev->device == 0x6850) \|\| \
2657		− (rdev->ddev->pdev->device == 0x6858) \|\| \
2658		− (rdev->ddev->pdev->device == 0x6859) \|\| \
2659		− (rdev->ddev->pdev->device == 0x6840) \|\| \
2660		− (rdev->ddev->pdev->device == 0x6841) \|\| \
2661		− (rdev->ddev->pdev->device == 0x6842) \|\| \
2662		− (rdev->ddev->pdev->device == 0x6843))
	2658	+#define ASIC_IS_LOMBOK(rdev) ((rdev->pdev->device == 0x6849) \|\| \
	2659	+ (rdev->pdev->device == 0x6850) \|\| \
	2660	+ (rdev->pdev->device == 0x6858) \|\| \
	2661	+ (rdev->pdev->device == 0x6859) \|\| \
	2662	+ (rdev->pdev->device == 0x6840) \|\| \
	2663	+ (rdev->pdev->device == 0x6841) \|\| \
	2664	+ (rdev->pdev->device == 0x6842) \|\| \
	2665	+ (rdev->pdev->device == 0x6843))
2663	2666
2664	2667	/*
2665	2668	* BIOS helpers.

drivers/gpu/drm/radeon/radeon_atombios.c+45−44

@@ -284,46 +284,47 @@ static bool radeon_atom_apply_quirks(struct drm_device *dev, · 283 unmodified lines
284	284	uint16_t *line_mux,
285	285	struct radeon_hpd *hpd)
286	286	{
	287	+ struct pci_dev *pdev = to_pci_dev(dev->dev);
287	288
288	289	/* Asus M2A-VM HDMI board lists the DVI port as HDMI */
289		− if ((dev->pdev->device == 0x791e) &&
290		− (dev->pdev->subsystem_vendor == 0x1043) &&
291		− (dev->pdev->subsystem_device == 0x826d)) {
	290	+ if ((pdev->device == 0x791e) &&
	291	+ (pdev->subsystem_vendor == 0x1043) &&
	292	+ (pdev->subsystem_device == 0x826d)) {
292	293	if ((*connector_type == DRM_MODE_CONNECTOR_HDMIA) &&
293	294	(supported_device == ATOM_DEVICE_DFP3_SUPPORT))
294	295	*connector_type = DRM_MODE_CONNECTOR_DVID;
295	296	}
296	297
297	298	/* Asrock RS600 board lists the DVI port as HDMI */
298		− if ((dev->pdev->device == 0x7941) &&
299		− (dev->pdev->subsystem_vendor == 0x1849) &&
300		− (dev->pdev->subsystem_device == 0x7941)) {
	299	+ if ((pdev->device == 0x7941) &&
	300	+ (pdev->subsystem_vendor == 0x1849) &&
	301	+ (pdev->subsystem_device == 0x7941)) {
301	302	if ((*connector_type == DRM_MODE_CONNECTOR_HDMIA) &&
302	303	(supported_device == ATOM_DEVICE_DFP3_SUPPORT))
303	304	*connector_type = DRM_MODE_CONNECTOR_DVID;
304	305	}
305	306
306	307	/* MSI K9A2GM V2/V3 board has no HDMI or DVI */
307		− if ((dev->pdev->device == 0x796e) &&
308		− (dev->pdev->subsystem_vendor == 0x1462) &&
309		− (dev->pdev->subsystem_device == 0x7302)) {
	308	+ if ((pdev->device == 0x796e) &&
	309	+ (pdev->subsystem_vendor == 0x1462) &&
	310	+ (pdev->subsystem_device == 0x7302)) {
310	311	if ((supported_device == ATOM_DEVICE_DFP2_SUPPORT) \|\|
311	312	(supported_device == ATOM_DEVICE_DFP3_SUPPORT))
312	313	return false;
313	314	}
314	315
315	316	/* a-bit f-i90hd - ciaranm on #radeonhd - this board has no DVI */
316		− if ((dev->pdev->device == 0x7941) &&
317		− (dev->pdev->subsystem_vendor == 0x147b) &&
318		− (dev->pdev->subsystem_device == 0x2412)) {
	317	+ if ((pdev->device == 0x7941) &&
	318	+ (pdev->subsystem_vendor == 0x147b) &&
	319	+ (pdev->subsystem_device == 0x2412)) {
319	320	if (*connector_type == DRM_MODE_CONNECTOR_DVII)
320	321	return false;
321	322	}
322	323
323	324	/* Falcon NW laptop lists vga ddc line for LVDS */
324		− if ((dev->pdev->device == 0x5653) &&
325		− (dev->pdev->subsystem_vendor == 0x1462) &&
326		− (dev->pdev->subsystem_device == 0x0291)) {
	325	+ if ((pdev->device == 0x5653) &&
	326	+ (pdev->subsystem_vendor == 0x1462) &&
	327	+ (pdev->subsystem_device == 0x0291)) {
327	328	if (*connector_type == DRM_MODE_CONNECTOR_LVDS) {
328	329	i2c_bus->valid = false;
329	330	*line_mux = 53;
@@ -331,26 +332,26 @@ static bool radeon_atom_apply_quirks(struct drm_device *dev, · 1 unmodified line
331	332	}
332	333
333	334	/* HIS X1300 is DVI+VGA, not DVI+DVI */
334		− if ((dev->pdev->device == 0x7146) &&
335		− (dev->pdev->subsystem_vendor == 0x17af) &&
336		− (dev->pdev->subsystem_device == 0x2058)) {
	335	+ if ((pdev->device == 0x7146) &&
	336	+ (pdev->subsystem_vendor == 0x17af) &&
	337	+ (pdev->subsystem_device == 0x2058)) {
337	338	if (supported_device == ATOM_DEVICE_DFP1_SUPPORT)
338	339	return false;
339	340	}
340	341
341	342	/* Gigabyte X1300 is DVI+VGA, not DVI+DVI */
342		− if ((dev->pdev->device == 0x7142) &&
343		− (dev->pdev->subsystem_vendor == 0x1458) &&
344		− (dev->pdev->subsystem_device == 0x2134)) {
	343	+ if ((pdev->device == 0x7142) &&
	344	+ (pdev->subsystem_vendor == 0x1458) &&
	345	+ (pdev->subsystem_device == 0x2134)) {
345	346	if (supported_device == ATOM_DEVICE_DFP1_SUPPORT)
346	347	return false;
347	348	}
348	349
349	350
350	351	/* Funky macbooks */
351		− if ((dev->pdev->device == 0x71C5) &&
352		− (dev->pdev->subsystem_vendor == 0x106b) &&
353		− (dev->pdev->subsystem_device == 0x0080)) {
	352	+ if ((pdev->device == 0x71C5) &&
	353	+ (pdev->subsystem_vendor == 0x106b) &&
	354	+ (pdev->subsystem_device == 0x0080)) {
354	355	if ((supported_device == ATOM_DEVICE_CRT1_SUPPORT) \|\|
355	356	(supported_device == ATOM_DEVICE_DFP2_SUPPORT))
356	357	return false;
@@ -366,27 +367,27 @@ static bool radeon_atom_apply_quirks(struct drm_device *dev, · 9 unmodified lines
366	367	}
367	368
368	369	/* ASUS HD 3600 XT board lists the DVI port as HDMI */
369		− if ((dev->pdev->device == 0x9598) &&
370		− (dev->pdev->subsystem_vendor == 0x1043) &&
371		− (dev->pdev->subsystem_device == 0x01da)) {
	370	+ if ((pdev->device == 0x9598) &&
	371	+ (pdev->subsystem_vendor == 0x1043) &&
	372	+ (pdev->subsystem_device == 0x01da)) {
372	373	if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) {
373	374	*connector_type = DRM_MODE_CONNECTOR_DVII;
374	375	}
375	376	}
376	377
377	378	/* ASUS HD 3600 board lists the DVI port as HDMI */
378		− if ((dev->pdev->device == 0x9598) &&
379		− (dev->pdev->subsystem_vendor == 0x1043) &&
380		− (dev->pdev->subsystem_device == 0x01e4)) {
	379	+ if ((pdev->device == 0x9598) &&
	380	+ (pdev->subsystem_vendor == 0x1043) &&
	381	+ (pdev->subsystem_device == 0x01e4)) {
381	382	if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) {
382	383	*connector_type = DRM_MODE_CONNECTOR_DVII;
383	384	}
384	385	}
385	386
386	387	/* ASUS HD 3450 board lists the DVI port as HDMI */
387		− if ((dev->pdev->device == 0x95C5) &&
388		− (dev->pdev->subsystem_vendor == 0x1043) &&
389		− (dev->pdev->subsystem_device == 0x01e2)) {
	388	+ if ((pdev->device == 0x95C5) &&
	389	+ (pdev->subsystem_vendor == 0x1043) &&
	390	+ (pdev->subsystem_device == 0x01e2)) {
390	391	if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) {
391	392	*connector_type = DRM_MODE_CONNECTOR_DVII;
392	393	}
@@ -411,9 +412,9 @@ static bool radeon_atom_apply_quirks(struct drm_device *dev, · 18 unmodified lines
411	412	* with different crtcs which isn't possible on the hardware
412	413	* side and leaves no crtcs for LVDS or VGA.
413	414	*/
414		− if (((dev->pdev->device == 0x95c4) \|\| (dev->pdev->device == 0x9591)) &&
415		− (dev->pdev->subsystem_vendor == 0x1025) &&
416		− (dev->pdev->subsystem_device == 0x013c)) {
	415	+ if (((pdev->device == 0x95c4) \|\| (pdev->device == 0x9591)) &&
	416	+ (pdev->subsystem_vendor == 0x1025) &&
	417	+ (pdev->subsystem_device == 0x013c)) {
417	418	if ((*connector_type == DRM_MODE_CONNECTOR_DVII) &&
418	419	(supported_device == ATOM_DEVICE_DFP1_SUPPORT)) {
419	420	/* actually it's a DVI-D port not DVI-I */
@@ -425,9 +426,9 @@ static bool radeon_atom_apply_quirks(struct drm_device *dev, · 5 unmodified lines
425	426	/* XFX Pine Group device rv730 reports no VGA DDC lines
426	427	* even though they are wired up to record 0x93
427	428	*/
428		− if ((dev->pdev->device == 0x9498) &&
429		− (dev->pdev->subsystem_vendor == 0x1682) &&
430		− (dev->pdev->subsystem_device == 0x2452) &&
	429	+ if ((pdev->device == 0x9498) &&
	430	+ (pdev->subsystem_vendor == 0x1682) &&
	431	+ (pdev->subsystem_device == 0x2452) &&
431	432	(i2c_bus->valid == false) &&
432	433	!(supported_device & (ATOM_DEVICE_TV_SUPPORT \| ATOM_DEVICE_CV_SUPPORT))) {
433	434	struct radeon_device *rdev = dev->dev_private;
@@ -435,11 +436,11 @@ static bool radeon_atom_apply_quirks(struct drm_device *dev, · 1 unmodified line
435	436	}
436	437
437	438	/* Fujitsu D3003-S2 board lists DVI-I as DVI-D and VGA */
438		− if (((dev->pdev->device == 0x9802) \|\|
439		− (dev->pdev->device == 0x9805) \|\|
440		− (dev->pdev->device == 0x9806)) &&
441		− (dev->pdev->subsystem_vendor == 0x1734) &&
442		− (dev->pdev->subsystem_device == 0x11bd)) {
	439	+ if (((pdev->device == 0x9802) \|\|
	440	+ (pdev->device == 0x9805) \|\|
	441	+ (pdev->device == 0x9806)) &&
	442	+ (pdev->subsystem_vendor == 0x1734) &&
	443	+ (pdev->subsystem_device == 0x11bd)) {
443	444	if (*connector_type == DRM_MODE_CONNECTOR_VGA) {
444	445	*connector_type = DRM_MODE_CONNECTOR_DVII;
445	446	*line_mux = 0x3103;

drivers/gpu/drm/radeon/radeon_bios.c+3−3

@@ -528,7 +528,7 @@ static bool legacy_read_disabled_bios(struct radeon_device *rdev) · 527 unmodified lines
528	528	crtc_ext_cntl = RREG32(RADEON_CRTC_EXT_CNTL);
529	529	fp2_gen_cntl = 0;
530	530
531		− if (rdev->ddev->pdev->device == PCI_DEVICE_ID_ATI_RADEON_QY) {
	531	+ if (rdev->pdev->device == PCI_DEVICE_ID_ATI_RADEON_QY) {
532	532	fp2_gen_cntl = RREG32(RADEON_FP2_GEN_CNTL);
533	533	}
534	534
@@ -565,7 +565,7 @@ static bool legacy_read_disabled_bios(struct radeon_device *rdev) · 30 unmodified lines
565	565	(RADEON_CRTC_SYNC_TRISTAT \|
566	566	RADEON_CRTC_DISPLAY_DIS)));
567	567
568		− if (rdev->ddev->pdev->device == PCI_DEVICE_ID_ATI_RADEON_QY) {
	568	+ if (rdev->pdev->device == PCI_DEVICE_ID_ATI_RADEON_QY) {
569	569	WREG32(RADEON_FP2_GEN_CNTL, (fp2_gen_cntl & ~RADEON_FP2_ON));
570	570	}
571	571
@@ -583,7 +583,7 @@ static bool legacy_read_disabled_bios(struct radeon_device *rdev) · 11 unmodified lines
583	583	WREG32(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl);
584	584	}
585	585	WREG32(RADEON_CRTC_EXT_CNTL, crtc_ext_cntl);
586		− if (rdev->ddev->pdev->device == PCI_DEVICE_ID_ATI_RADEON_QY) {
	586	+ if (rdev->pdev->device == PCI_DEVICE_ID_ATI_RADEON_QY) {
587	587	WREG32(RADEON_FP2_GEN_CNTL, fp2_gen_cntl);
588	588	}
589	589	return r;

drivers/gpu/drm/radeon/radeon_combios.c+29−26

@@ -894,13 +894,13 @@ struct radeon_encoder_primary_dac *radeon_combios_get_primary_dac_info(struct · 893 unmodified lines
894	894
895	895	/* quirks */
896	896	/* Radeon 7000 (RV100) */
897		− if (((dev->pdev->device == 0x5159) &&
898		− (dev->pdev->subsystem_vendor == 0x174B) &&
899		− (dev->pdev->subsystem_device == 0x7c28)) \|\|
	897	+ if (((rdev->pdev->device == 0x5159) &&
	898	+ (rdev->pdev->subsystem_vendor == 0x174B) &&
	899	+ (rdev->pdev->subsystem_device == 0x7c28)) \|\|
900	900	/* Radeon 9100 (R200) */
901		− ((dev->pdev->device == 0x514D) &&
902		− (dev->pdev->subsystem_vendor == 0x174B) &&
903		− (dev->pdev->subsystem_device == 0x7149))) {
	901	+ ((rdev->pdev->device == 0x514D) &&
	902	+ (rdev->pdev->subsystem_vendor == 0x174B) &&
	903	+ (rdev->pdev->subsystem_device == 0x7149))) {
904	904	/* vbios value is bad, use the default */
905	905	found = 0;
906	906	}
@@ -2221,20 +2221,21 @@ static bool radeon_apply_legacy_quirks(struct drm_device *dev, · 1314 unmodified lines
2221	2221	struct radeon_i2c_bus_rec *ddc_i2c,
2222	2222	struct radeon_hpd *hpd)
2223	2223	{
	2224	+ struct radeon_device *rdev = dev->dev_private;
2224	2225
2225	2226	/* Certain IBM chipset RN50s have a BIOS reporting two VGAs,
2226	2227	one with VGA DDC and one with CRT2 DDC. - kill the CRT2 DDC one */
2227		− if (dev->pdev->device == 0x515e &&
2228		− dev->pdev->subsystem_vendor == 0x1014) {
	2228	+ if (rdev->pdev->device == 0x515e &&
	2229	+ rdev->pdev->subsystem_vendor == 0x1014) {
2229	2230	if (*legacy_connector == CONNECTOR_CRT_LEGACY &&
2230	2231	ddc_i2c->mask_clk_reg == RADEON_GPIO_CRT2_DDC)
2231	2232	return false;
2232	2233	}
2233	2234
2234	2235	/* X300 card with extra non-existent DVI port */
2235		− if (dev->pdev->device == 0x5B60 &&
2236		− dev->pdev->subsystem_vendor == 0x17af &&
2237		− dev->pdev->subsystem_device == 0x201e && bios_index == 2) {
	2236	+ if (rdev->pdev->device == 0x5B60 &&
	2237	+ rdev->pdev->subsystem_vendor == 0x17af &&
	2238	+ rdev->pdev->subsystem_device == 0x201e && bios_index == 2) {
2238	2239	if (*legacy_connector == CONNECTOR_DVI_I_LEGACY)
2239	2240	return false;
2240	2241	}
@@ -2244,22 +2245,24 @@ static bool radeon_apply_legacy_quirks(struct drm_device *dev, · 3 unmodified lines
2244	2245
2245	2246	static bool radeon_apply_legacy_tv_quirks(struct drm_device *dev)
2246	2247	{
	2248	+ struct radeon_device *rdev = dev->dev_private;
	2249	+
2247	2250	/* Acer 5102 has non-existent TV port */
2248		− if (dev->pdev->device == 0x5975 &&
2249		− dev->pdev->subsystem_vendor == 0x1025 &&
2250		− dev->pdev->subsystem_device == 0x009f)
	2251	+ if (rdev->pdev->device == 0x5975 &&
	2252	+ rdev->pdev->subsystem_vendor == 0x1025 &&
	2253	+ rdev->pdev->subsystem_device == 0x009f)
2251	2254	return false;
2252	2255
2253	2256	/* HP dc5750 has non-existent TV port */
2254		− if (dev->pdev->device == 0x5974 &&
2255		− dev->pdev->subsystem_vendor == 0x103c &&
2256		− dev->pdev->subsystem_device == 0x280a)
	2257	+ if (rdev->pdev->device == 0x5974 &&
	2258	+ rdev->pdev->subsystem_vendor == 0x103c &&
	2259	+ rdev->pdev->subsystem_device == 0x280a)
2257	2260	return false;
2258	2261
2259	2262	/* MSI S270 has non-existent TV port */
2260		− if (dev->pdev->device == 0x5955 &&
2261		− dev->pdev->subsystem_vendor == 0x1462 &&
2262		− dev->pdev->subsystem_device == 0x0131)
	2263	+ if (rdev->pdev->device == 0x5955 &&
	2264	+ rdev->pdev->subsystem_vendor == 0x1462 &&
	2265	+ rdev->pdev->subsystem_device == 0x0131)
2263	2266	return false;
2264	2267
2265	2268	return true;
@@ -2413,9 +2416,9 @@ bool radeon_get_legacy_connector_info_from_bios(struct drm_device *dev) · 147 unmodified lines
2413	2416	/* RV100 board with external TDMS bit mis-set.
2414	2417	* Actually uses internal TMDS, clear the bit.
2415	2418	*/
2416		− if (dev->pdev->device == 0x5159 &&
2417		− dev->pdev->subsystem_vendor == 0x1014 &&
2418		− dev->pdev->subsystem_device == 0x029A) {
	2419	+ if (rdev->pdev->device == 0x5159 &&
	2420	+ rdev->pdev->subsystem_vendor == 0x1014 &&
	2421	+ rdev->pdev->subsystem_device == 0x029A) {
2419	2422	tmp &= ~(1 << 4);
2420	2423	}
2421	2424	if ((tmp >> 4) & 0x1) {
@@ -2707,9 +2710,9 @@ void radeon_combios_get_power_modes(struct radeon_device *rdev) · 285 unmodified lines
2707	2710	/* boards with a thermal chip, but no overdrive table */
2708	2711
2709	2712	/* Asus 9600xt has an f75375 on the monid bus */
2710		− if ((dev->pdev->device == 0x4152) &&
2711		− (dev->pdev->subsystem_vendor == 0x1043) &&
2712		− (dev->pdev->subsystem_device == 0xc002)) {
	2713	+ if ((rdev->pdev->device == 0x4152) &&
	2714	+ (rdev->pdev->subsystem_vendor == 0x1043) &&
	2715	+ (rdev->pdev->subsystem_device == 0xc002)) {
2713	2716	i2c_bus = combios_setup_i2c_bus(rdev, DDC_MONID, 0, 0);
2714	2717	rdev->pm.i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus);
2715	2718	if (rdev->pm.i2c_bus) {

drivers/gpu/drm/radeon/radeon_cs.c+1−2

@@ -130,8 +130,7 @@ static int radeon_cs_parser_relocs(struct radeon_cs_parser *p) · 129 unmodified lines
130	130	* IGP chips to avoid image corruptions
131	131	*/
132	132	if (p->ring == R600_RING_TYPE_UVD_INDEX &&
133		− (i <= 0 \|\| pci_find_capability(p->rdev->ddev->pdev,
134		− PCI_CAP_ID_AGP) \|\|
	133	+ (i <= 0 \|\| pci_find_capability(p->rdev->pdev, PCI_CAP_ID_AGP) \|\|
135	134	p->rdev->family == CHIP_RS780 \|\|
136	135	p->rdev->family == CHIP_RS880)) {
137	136

drivers/gpu/drm/radeon/radeon_device.c+10−7

@@ -1562,6 +1562,7 @@ int radeon_suspend_kms(struct drm_device *dev, bool suspend, · 1561 unmodified lines
1562	1562	bool fbcon, bool freeze)
1563	1563	{
1564	1564	struct radeon_device *rdev;
	1565	+ struct pci_dev *pdev;
1565	1566	struct drm_crtc *crtc;
1566	1567	struct drm_connector *connector;
1567	1568	int i, r;
@@ -1571,6 +1572,7 @@ int radeon_suspend_kms(struct drm_device *dev, bool suspend, · 3 unmodified lines
1571	1572	}
1572	1573
1573	1574	rdev = dev->dev_private;
	1575	+ pdev = to_pci_dev(dev->dev);
1574	1576
1575	1577	if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
1576	1578	return 0;
@@ -1636,14 +1638,14 @@ int radeon_suspend_kms(struct drm_device *dev, bool suspend, · 59 unmodified lines
1636	1638
1637	1639	radeon_agp_suspend(rdev);
1638	1640
1639		− pci_save_state(dev->pdev);
	1641	+ pci_save_state(pdev);
1640	1642	if (freeze && rdev->family >= CHIP_CEDAR && !(rdev->flags & RADEON_IS_IGP)) {
1641	1643	rdev->asic->asic_reset(rdev, true);
1642		− pci_restore_state(dev->pdev);
	1644	+ pci_restore_state(pdev);
1643	1645	} else if (suspend) {
1644	1646	/* Shut down the device */
1645		− pci_disable_device(dev->pdev);
1646		− pci_set_power_state(dev->pdev, PCI_D3hot);
	1647	+ pci_disable_device(pdev);
	1648	+ pci_set_power_state(pdev, PCI_D3hot);
1647	1649	}
1648	1650
1649	1651	if (fbcon) {
@@ -1665,6 +1667,7 @@ int radeon_resume_kms(struct drm_device *dev, bool resume, bool fbcon) · 15 unmodified lines
1665	1667	{
1666	1668	struct drm_connector *connector;
1667	1669	struct radeon_device *rdev = dev->dev_private;
	1670	+ struct pci_dev *pdev = to_pci_dev(dev->dev);
1668	1671	struct drm_crtc *crtc;
1669	1672	int r;
1670	1673
@@ -1675,9 +1678,9 @@ int radeon_resume_kms(struct drm_device *dev, bool resume, bool fbcon) · 4 unmodified lines
1675	1678	console_lock();
1676	1679	}
1677	1680	if (resume) {
1678		− pci_set_power_state(dev->pdev, PCI_D0);
1679		− pci_restore_state(dev->pdev);
1680		− if (pci_enable_device(dev->pdev)) {
	1681	+ pci_set_power_state(pdev, PCI_D0);
	1682	+ pci_restore_state(pdev);
	1683	+ if (pci_enable_device(pdev)) {
1681	1684	if (fbcon)
1682	1685	console_unlock();
1683	1686	return -1;

drivers/gpu/drm/radeon/radeon_display.c+1−1

@@ -1317,7 +1317,7 @@ radeon_user_framebuffer_create(struct drm_device *dev, · 1316 unmodified lines
1317	1317
1318	1318	obj = drm_gem_object_lookup(file_priv, mode_cmd->handles[0]);
1319	1319	if (obj == NULL) {
1320		− dev_err(&dev->pdev->dev, "No GEM object associated to handle 0x%08X, "
	1320	+ dev_err(dev->dev, "No GEM object associated to handle 0x%08X, "
1321	1321	"can't create framebuffer\n", mode_cmd->handles[0]);
1322	1322	return ERR_PTR(-ENOENT);
1323	1323	}

drivers/gpu/drm/radeon/radeon_drv.c+1−6

@@ -342,14 +342,9 @@ static int radeon_pci_probe(struct pci_dev *pdev, · 341 unmodified lines
342	342	if (ret)
343	343	goto err_free;
344	344
345		− dev->pdev = pdev;
346		−#ifdef __alpha__
347		− dev->hose = pdev->sysdata;
348		−#endif
349		−
350	345	pci_set_drvdata(pdev, dev);
351	346
352		− if (pci_find_capability(dev->pdev, PCI_CAP_ID_AGP))
	347	+ if (pci_find_capability(pdev, PCI_CAP_ID_AGP))
353	348	dev->agp = drm_agp_init(dev);
354	349	if (dev->agp) {
355	350	dev->agp->agp_mtrr = arch_phys_wc_add(

drivers/gpu/drm/radeon/radeon_fb.c+1−1

@@ -290,7 +290,7 @@ static int radeonfb_create(struct drm_fb_helper *helper, · 289 unmodified lines
290	290	DRM_INFO("fb depth is %d\n", fb->format->depth);
291	291	DRM_INFO(" pitch is %d\n", fb->pitches[0]);
292	292
293		− vga_switcheroo_client_fb_set(rdev->ddev->pdev, info);
	293	+ vga_switcheroo_client_fb_set(rdev->pdev, info);
294	294	return 0;
295	295
296	296	out:

drivers/gpu/drm/radeon/radeon_gem.c+3−3

@@ -651,7 +651,7 @@ int radeon_gem_va_ioctl(struct drm_device dev, void data, · 650 unmodified lines
651	651	}
652	652
653	653	if (args->offset < RADEON_VA_RESERVED_SIZE) {
654		− dev_err(&dev->pdev->dev,
	654	+ dev_err(dev->dev,
655	655	"offset 0x%lX is in reserved area 0x%X\n",
656	656	(unsigned long)args->offset,
657	657	RADEON_VA_RESERVED_SIZE);
@@ -665,7 +665,7 @@ int radeon_gem_va_ioctl(struct drm_device dev, void data, · 7 unmodified lines
665	665	*/
666	666	invalid_flags = RADEON_VM_PAGE_VALID \| RADEON_VM_PAGE_SYSTEM;
667	667	if ((args->flags & invalid_flags)) {
668		− dev_err(&dev->pdev->dev, "invalid flags 0x%08X vs 0x%08X\n",
	668	+ dev_err(dev->dev, "invalid flags 0x%08X vs 0x%08X\n",
669	669	args->flags, invalid_flags);
670	670	args->operation = RADEON_VA_RESULT_ERROR;
671	671	return -EINVAL;
@@ -676,7 +676,7 @@ int radeon_gem_va_ioctl(struct drm_device dev, void data, · 4 unmodified lines
676	676	case RADEON_VA_UNMAP:
677	677	break;
678	678	default:
679		− dev_err(&dev->pdev->dev, "unsupported operation %d\n",
	679	+ dev_err(dev->dev, "unsupported operation %d\n",
680	680	args->operation);
681	681	args->operation = RADEON_VA_RESULT_ERROR;
682	682	return -EINVAL;

drivers/gpu/drm/radeon/radeon_i2c.c+1−1

@@ -919,7 +919,7 @@ struct radeon_i2c_chan radeon_i2c_create(struct drm_device dev, · 918 unmodified lines
919	919	i2c->rec = *rec;
920	920	i2c->adapter.owner = THIS_MODULE;
921	921	i2c->adapter.class = I2C_CLASS_DDC;
922		− i2c->adapter.dev.parent = &dev->pdev->dev;
	922	+ i2c->adapter.dev.parent = dev->dev;
923	923	i2c->dev = dev;
924	924	i2c_set_adapdata(&i2c->adapter, i2c);
925	925	mutex_init(&i2c->mutex);

drivers/gpu/drm/radeon/radeon_irq_kms.c+1−1

@@ -314,7 +314,7 @@ int radeon_irq_kms_init(struct radeon_device *rdev) · 313 unmodified lines
314	314	INIT_WORK(&rdev->audio_work, r600_audio_update_hdmi);
315	315
316	316	rdev->irq.installed = true;
317		− r = drm_irq_install(rdev->ddev, rdev->ddev->pdev->irq);
	317	+ r = drm_irq_install(rdev->ddev, rdev->pdev->irq);
318	318	if (r) {
319	319	rdev->irq.installed = false;
320	320	flush_delayed_work(&rdev->hotplug_work);

drivers/gpu/drm/radeon/radeon_kms.c+14−10

@@ -76,7 +76,7 @@ void radeon_driver_unload_kms(struct drm_device *dev) · 75 unmodified lines
76	76	}
77	77
78	78	radeon_acpi_fini(rdev);
79		−
	79	+
80	80	radeon_modeset_fini(rdev);
81	81	radeon_device_fini(rdev);
82	82
@@ -105,6 +105,7 @@ done_free: · 22 unmodified lines
105	105	*/
106	106	int radeon_driver_load_kms(struct drm_device *dev, unsigned long flags)
107	107	{
	108	+ struct pci_dev *pdev = to_pci_dev(dev->dev);
108	109	struct radeon_device *rdev;
109	110	int r, acpi_status;
110	111
@@ -114,10 +115,14 @@ int radeon_driver_load_kms(struct drm_device *dev, unsigned long flags) · 3 unmodified lines
114	115	}
115	116	dev->dev_private = (void *)rdev;
116	117
	118	+#ifdef __alpha__
	119	+ rdev->hose = pdev->sysdata;
	120	+#endif
	121	+
117	122	/* update BUS flag */
118		− if (pci_find_capability(dev->pdev, PCI_CAP_ID_AGP)) {
	123	+ if (pci_find_capability(pdev, PCI_CAP_ID_AGP)) {
119	124	flags \|= RADEON_IS_AGP;
120		− } else if (pci_is_pcie(dev->pdev)) {
	125	+ } else if (pci_is_pcie(pdev)) {
121	126	flags \|= RADEON_IS_PCIE;
122	127	} else {
123	128	flags \|= RADEON_IS_PCI;
@@ -126,7 +131,7 @@ int radeon_driver_load_kms(struct drm_device *dev, unsigned long flags) · 2 unmodified lines
126	131	if ((radeon_runtime_pm != 0) &&
127	132	radeon_has_atpx() &&
128	133	((flags & RADEON_IS_IGP) == 0) &&
129		− !pci_is_thunderbolt_attached(dev->pdev))
	134	+ !pci_is_thunderbolt_attached(pdev))
130	135	flags \|= RADEON_IS_PX;
131	136
132	137	/* radeon_device_init should report only fatal error
@@ -135,9 +140,9 @@ int radeon_driver_load_kms(struct drm_device *dev, unsigned long flags) · 2 unmodified lines
135	140	* properly initialize the GPU MC controller and permit
136	141	* VRAM allocation
137	142	*/
138		− r = radeon_device_init(rdev, dev, dev->pdev, flags);
	143	+ r = radeon_device_init(rdev, dev, pdev, flags);
139	144	if (r) {
140		− dev_err(&dev->pdev->dev, "Fatal error during GPU init\n");
	145	+ dev_err(dev->dev, "Fatal error during GPU init\n");
141	146	goto out;
142	147	}
143	148
@@ -147,7 +152,7 @@ int radeon_driver_load_kms(struct drm_device *dev, unsigned long flags) · 3 unmodified lines
147	152	*/
148	153	r = radeon_modeset_init(rdev);
149	154	if (r)
150		− dev_err(&dev->pdev->dev, "Fatal error during modeset init\n");
	155	+ dev_err(dev->dev, "Fatal error during modeset init\n");
151	156
152	157	/* Call ACPI methods: require modeset init
153	158	* but failure is not fatal
@@ -155,8 +160,7 @@ int radeon_driver_load_kms(struct drm_device *dev, unsigned long flags) · 1 unmodified line
155	160	if (!r) {
156	161	acpi_status = radeon_acpi_init(rdev);
157	162	if (acpi_status)
158		− dev_dbg(&dev->pdev->dev,
159		− "Error during ACPI methods call\n");
	163	+ dev_dbg(dev->dev, "Error during ACPI methods call\n");
160	164	}
161	165
162	166	if (radeon_is_px(dev)) {
@@ -239,7 +243,7 @@ int radeon_info_ioctl(struct drm_device dev, void data, struct drm_file *filp) · 76 unmodified lines
239	243
240	244	switch (info->request) {
241	245	case RADEON_INFO_DEVICE_ID:
242		− *value = dev->pdev->device;
	246	+ *value = to_pci_dev(dev->dev)->device;
243	247	break;
244	248	case RADEON_INFO_NUM_GB_PIPES:
245	249	*value = rdev->num_gb_pipes;

drivers/gpu/drm/radeon/radeon_legacy_encoders.c+3−3

@@ -974,9 +974,9 @@ static void radeon_legacy_tmds_ext_mode_set(struct drm_encoder *encoder, · 973 unmodified lines
974	974
975	975	/* XXX: these are oem specific */
976	976	if (ASIC_IS_R300(rdev)) {
977		− if ((dev->pdev->device == 0x4850) &&
978		− (dev->pdev->subsystem_vendor == 0x1028) &&
979		− (dev->pdev->subsystem_device == 0x2001)) /* Dell Inspiron 8600 */
	977	+ if ((rdev->pdev->device == 0x4850) &&
	978	+ (rdev->pdev->subsystem_vendor == 0x1028) &&
	979	+ (rdev->pdev->subsystem_device == 0x2001)) /* Dell Inspiron 8600 */
980	980	fp2_gen_cntl \|= R300_FP2_DVO_CLOCK_MODE_SINGLE;
981	981	else
982	982	fp2_gen_cntl \|= RADEON_FP2_PAD_FLOP_EN \| R300_FP2_DVO_CLOCK_MODE_SINGLE;

drivers/gpu/drm/radeon/radeon_ttm.c+1−1

@@ -324,7 +324,7 @@ static int radeon_ttm_io_mem_reserve(struct ttm_bo_device *bdev, struct ttm_reso · 323 unmodified lines
324	324	* access, as done in ttm_bo_vm_fault().
325	325	*/
326	326	mem->bus.offset = (mem->bus.offset & 0x0ffffffffUL) +
327		− rdev->ddev->hose->dense_mem_base;
	327	+ rdev->hose->dense_mem_base;
328	328	#endif
329	329	break;
330	330	default:

drivers/gpu/drm/radeon/rs780_dpm.c+3−4

@@ -223,16 +223,15 @@ static void rs780_preset_starting_fbdiv(struct radeon_device *rdev) · 222 unmodified lines
223	223	static void rs780_voltage_scaling_init(struct radeon_device *rdev)
224	224	{
225	225	struct igp_power_info *pi = rs780_get_pi(rdev);
226		− struct drm_device *dev = rdev->ddev;
227	226	u32 fv_throt_pwm_fb_div_range[3];
228	227	u32 fv_throt_pwm_range[4];
229	228
230		− if (dev->pdev->device == 0x9614) {
	229	+ if (rdev->pdev->device == 0x9614) {
231	230	fv_throt_pwm_fb_div_range[0] = RS780D_FVTHROTPWMFBDIVRANGEREG0_DFLT;
232	231	fv_throt_pwm_fb_div_range[1] = RS780D_FVTHROTPWMFBDIVRANGEREG1_DFLT;
233	232	fv_throt_pwm_fb_div_range[2] = RS780D_FVTHROTPWMFBDIVRANGEREG2_DFLT;
234		− } else if ((dev->pdev->device == 0x9714) \|\|
235		− (dev->pdev->device == 0x9715)) {
	233	+ } else if ((rdev->pdev->device == 0x9714) \|\|
	234	+ (rdev->pdev->device == 0x9715)) {
236	235	fv_throt_pwm_fb_div_range[0] = RS880D_FVTHROTPWMFBDIVRANGEREG0_DFLT;
237	236	fv_throt_pwm_fb_div_range[1] = RS880D_FVTHROTPWMFBDIVRANGEREG1_DFLT;
238	237	fv_throt_pwm_fb_div_range[2] = RS880D_FVTHROTPWMFBDIVRANGEREG2_DFLT;

drivers/gpu/drm/scheduler/sched_main.c+3−0

@@ -899,6 +899,9 @@ void drm_sched_fini(struct drm_gpu_scheduler *sched) · 898 unmodified lines
899	899	if (sched->thread)
900	900	kthread_stop(sched->thread);
901	901
	902	+ /* Confirm no work left behind accessing device structures */
	903	+ cancel_delayed_work_sync(&sched->work_tdr);
	904	+
902	905	sched->ready = false;
903	906	}
904	907	EXPORT_SYMBOL(drm_sched_fini);

drivers/gpu/drm/sun4i/sun4i_tcon.c+2−19

@@ -569,30 +569,13 @@ static void sun4i_tcon0_mode_set_rgb(struct sun4i_tcon *tcon, · 568 unmodified lines
569	569	if (info->bus_flags & DRM_BUS_FLAG_DE_LOW)
570	570	val \|= SUN4I_TCON0_IO_POL_DE_NEGATIVE;
571	571
572		− /*
573		− * On A20 and similar SoCs, the only way to achieve Positive Edge
574		− * (Rising Edge), is setting dclk clock phase to 2/3(240°).
575		− * By default TCON works in Negative Edge(Falling Edge),
576		− * this is why phase is set to 0 in that case.
577		− * Unfortunately there's no way to logically invert dclk through
578		− * IO_POL register.
579		− * The only acceptable way to work, triple checked with scope,
580		− * is using clock phase set to 0° for Negative Edge and set to 240°
581		− * for Positive Edge.
582		− * On A33 and similar SoCs there would be a 90° phase option,
583		− * but it divides also dclk by 2.
584		− * Following code is a way to avoid quirks all around TCON
585		− * and DOTCLOCK drivers.
586		− */
587		− if (info->bus_flags & DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE)
588		− clk_set_phase(tcon->dclk, 240);
589		−
590	572	if (info->bus_flags & DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE)
591		− clk_set_phase(tcon->dclk, 0);
	573	+ val \|= SUN4I_TCON0_IO_POL_DCLK_DRIVE_NEGEDGE;
592	574
593	575	regmap_update_bits(tcon->regs, SUN4I_TCON0_IO_POL_REG,
594	576	SUN4I_TCON0_IO_POL_HSYNC_POSITIVE \|
595	577	SUN4I_TCON0_IO_POL_VSYNC_POSITIVE \|
	578	+ SUN4I_TCON0_IO_POL_DCLK_DRIVE_NEGEDGE \|
596	579	SUN4I_TCON0_IO_POL_DE_NEGATIVE,
597	580	val);
598	581

drivers/gpu/drm/sun4i/sun4i_tcon.h+1−0

@@ -113,6 +113,7 @@ · 112 unmodified lines
113	113	#define SUN4I_TCON0_IO_POL_REG 0x88
114	114	#define SUN4I_TCON0_IO_POL_DCLK_PHASE(phase) ((phase & 3) << 28)
115	115	#define SUN4I_TCON0_IO_POL_DE_NEGATIVE BIT(27)
	116	+#define SUN4I_TCON0_IO_POL_DCLK_DRIVE_NEGEDGE BIT(26)
116	117	#define SUN4I_TCON0_IO_POL_HSYNC_POSITIVE BIT(25)
117	118	#define SUN4I_TCON0_IO_POL_VSYNC_POSITIVE BIT(24)
118	119

drivers/gpu/drm/sun4i/sun8i_csc.c+44−65

@@ -46,33 +46,6 @@ static const u32 yuv2rgb[2][2][12] = { · 45 unmodified lines
46	46	},
47	47	};
48	48
49		−static const u32 yvu2rgb[2][2][12] = {
50		− [DRM_COLOR_YCBCR_LIMITED_RANGE] = {
51		− [DRM_COLOR_YCBCR_BT601] = {
52		− 0x000004A8, 0x00000662, 0x00000000, 0xFFFC8451,
53		− 0x000004A8, 0xFFFFFCC0, 0xFFFFFE6F, 0x00021E4D,
54		− 0x000004A8, 0x00000000, 0x00000811, 0xFFFBACA9,
55		− },
56		− [DRM_COLOR_YCBCR_BT709] = {
57		− 0x000004A8, 0x0000072B, 0x00000000, 0xFFFC1F99,
58		− 0x000004A8, 0xFFFFFDDF, 0xFFFFFF26, 0x00013383,
59		− 0x000004A8, 0x00000000, 0x00000873, 0xFFFB7BEF,
60		− }
61		− },
62		− [DRM_COLOR_YCBCR_FULL_RANGE] = {
63		− [DRM_COLOR_YCBCR_BT601] = {
64		− 0x00000400, 0x0000059B, 0x00000000, 0xFFFD322E,
65		− 0x00000400, 0xFFFFFD25, 0xFFFFFEA0, 0x00021DD5,
66		− 0x00000400, 0x00000000, 0x00000716, 0xFFFC74BD,
67		− },
68		− [DRM_COLOR_YCBCR_BT709] = {
69		− 0x00000400, 0x0000064C, 0x00000000, 0xFFFCD9B4,
70		− 0x00000400, 0xFFFFFE21, 0xFFFFFF41, 0x00014F96,
71		− 0x00000400, 0x00000000, 0x0000076C, 0xFFFC49EF,
72		− }
73		− },
74		−};
75		−
76	49	/*
77	50	* DE3 has a bit different CSC units. Factors are in two's complement format.
78	51	* First three factors in a row are multiplication factors which have 17 bits
@@ -96,7 +69,7 @@ static const u32 yvu2rgb[2][2][12] = { · 17 unmodified lines
96	69	* c20 c21 c22 [d2 const2]
97	70	*/
98	71
99		−static const u32 yuv2rgb_de3[2][2][12] = {
	72	+static const u32 yuv2rgb_de3[2][3][12] = {
100	73	[DRM_COLOR_YCBCR_LIMITED_RANGE] = {
101	74	[DRM_COLOR_YCBCR_BT601] = {
102	75	0x0002542A, 0x00000000, 0x0003312A, 0xFFC00000,
@@ -107,6 +80,11 @@ static const u32 yuv2rgb_de3[2][2][12] = { · 4 unmodified lines
107	80	0x0002542A, 0x00000000, 0x000395E2, 0xFFC00000,
108	81	0x0002542A, 0xFFFF92D2, 0xFFFEEF27, 0xFE000000,
109	82	0x0002542A, 0x0004398C, 0x00000000, 0xFE000000,
	83	+ },
	84	+ [DRM_COLOR_YCBCR_BT2020] = {
	85	+ 0x0002542A, 0x00000000, 0x00035B7B, 0xFFC00000,
	86	+ 0x0002542A, 0xFFFFA017, 0xFFFEB2FC, 0xFE000000,
	87	+ 0x0002542A, 0x00044896, 0x00000000, 0xFE000000,
110	88	}
111	89	},
112	90	[DRM_COLOR_YCBCR_FULL_RANGE] = {
@@ -119,33 +97,11 @@ static const u32 yuv2rgb_de3[2][2][12] = { · 6 unmodified lines
119	97	0x00020000, 0x00000000, 0x0003264C, 0x00000000,
120	98	0x00020000, 0xFFFFA018, 0xFFFF1053, 0xFE000000,
121	99	0x00020000, 0x0003B611, 0x00000000, 0xFE000000,
122		− }
123		− },
124		−};
125		−
126		−static const u32 yvu2rgb_de3[2][2][12] = {
127		− [DRM_COLOR_YCBCR_LIMITED_RANGE] = {
128		− [DRM_COLOR_YCBCR_BT601] = {
129		− 0x0002542A, 0x0003312A, 0x00000000, 0xFFC00000,
130		− 0x0002542A, 0xFFFE5FC3, 0xFFFF376B, 0xFE000000,
131		− 0x0002542A, 0x00000000, 0x000408D2, 0xFE000000,
132	100	},
133		− [DRM_COLOR_YCBCR_BT709] = {
134		− 0x0002542A, 0x000395E2, 0x00000000, 0xFFC00000,
135		− 0x0002542A, 0xFFFEEF27, 0xFFFF92D2, 0xFE000000,
136		− 0x0002542A, 0x00000000, 0x0004398C, 0xFE000000,
137		− }
138		− },
139		− [DRM_COLOR_YCBCR_FULL_RANGE] = {
140		− [DRM_COLOR_YCBCR_BT601] = {
141		− 0x00020000, 0x0002CDD2, 0x00000000, 0x00000000,
142		− 0x00020000, 0xFFFE925D, 0xFFFF4FCE, 0xFE000000,
143		− 0x00020000, 0x00000000, 0x00038B43, 0xFE000000,
144		− },
145		− [DRM_COLOR_YCBCR_BT709] = {
146		− 0x00020000, 0x0003264C, 0x00000000, 0x00000000,
147		− 0x00020000, 0xFFFF1053, 0xFFFFA018, 0xFE000000,
148		− 0x00020000, 0x00000000, 0x0003B611, 0xFE000000,
	101	+ [DRM_COLOR_YCBCR_BT2020] = {
	102	+ 0x00020000, 0x00000000, 0x0002F2FE, 0x00000000,
	103	+ 0x00020000, 0xFFFFABC0, 0xFFFEDB78, 0xFE000000,
	104	+ 0x00020000, 0x0003C346, 0x00000000, 0xFE000000,
149	105	}
150	106	},
151	107	};
@@ -157,21 +113,30 @@ static void sun8i_csc_set_coefficients(struct regmap *map, u32 base, · 5 unmodified lines
157	113	{
158	114	const u32 *table;
159	115	u32 base_reg;
	116	+ int i;
	117	+
	118	+ table = yuv2rgb[range][encoding];
160	119
161	120	switch (mode) {
162	121	case SUN8I_CSC_MODE_YUV2RGB:
163		− table = yuv2rgb[range][encoding];
	122	+ base_reg = SUN8I_CSC_COEFF(base, 0);
	123	+ regmap_bulk_write(map, base_reg, table, 12);
164	124	break;
165	125	case SUN8I_CSC_MODE_YVU2RGB:
166		− table = yvu2rgb[range][encoding];
	126	+ for (i = 0; i < 12; i++) {
	127	+ if ((i & 3) == 1)
	128	+ base_reg = SUN8I_CSC_COEFF(base, i + 1);
	129	+ else if ((i & 3) == 2)
	130	+ base_reg = SUN8I_CSC_COEFF(base, i - 1);
	131	+ else
	132	+ base_reg = SUN8I_CSC_COEFF(base, i);
	133	+ regmap_write(map, base_reg, table[i]);
	134	+ }
167	135	break;
168	136	default:
169	137	DRM_WARN("Wrong CSC mode specified.\n");
170	138	return;
171	139	}
172		−
173		− base_reg = SUN8I_CSC_COEFF(base, 0);
174		− regmap_bulk_write(map, base_reg, table, 12);
175	140	}
176	141
177	142	static void sun8i_de3_ccsc_set_coefficients(struct regmap *map, int layer,
@@ -180,22 +145,36 @@ static void sun8i_de3_ccsc_set_coefficients(struct regmap *map, int layer, · 2 unmodified lines
180	145	enum drm_color_range range)
181	146	{
182	147	const u32 *table;
183		− u32 base_reg;
	148	+ u32 addr;
	149	+ int i;
	150	+
	151	+ table = yuv2rgb_de3[range][encoding];
184	152
185	153	switch (mode) {
186	154	case SUN8I_CSC_MODE_YUV2RGB:
187		− table = yuv2rgb_de3[range][encoding];
	155	+ addr = SUN50I_MIXER_BLEND_CSC_COEFF(DE3_BLD_BASE, layer, 0);
	156	+ regmap_bulk_write(map, addr, table, 12);
188	157	break;
189	158	case SUN8I_CSC_MODE_YVU2RGB:
190		− table = yvu2rgb_de3[range][encoding];
	159	+ for (i = 0; i < 12; i++) {
	160	+ if ((i & 3) == 1)
	161	+ addr = SUN50I_MIXER_BLEND_CSC_COEFF(DE3_BLD_BASE,
	162	+ layer,
	163	+ i + 1);
	164	+ else if ((i & 3) == 2)
	165	+ addr = SUN50I_MIXER_BLEND_CSC_COEFF(DE3_BLD_BASE,
	166	+ layer,
	167	+ i - 1);
	168	+ else
	169	+ addr = SUN50I_MIXER_BLEND_CSC_COEFF(DE3_BLD_BASE,
	170	+ layer, i);
	171	+ regmap_write(map, addr, table[i]);
	172	+ }
191	173	break;
192	174	default:
193	175	DRM_WARN("Wrong CSC mode specified.\n");
194	176	return;
195	177	}
196		−
197		− base_reg = SUN50I_MIXER_BLEND_CSC_COEFF(DE3_BLD_BASE, layer, 0, 0);
198		− regmap_bulk_write(map, base_reg, table, 12);
199	178	}
200	179
201	180	static void sun8i_csc_enable(struct regmap *map, u32 base, bool enable)

drivers/gpu/drm/sun4i/sun8i_mixer.h+2−4

@@ -50,10 +50,8 @@ · 49 unmodified lines
50	50	#define SUN8I_MIXER_BLEND_CK_MIN(base, x) ((base) + 0xe0 + 0x04 * (x))
51	51	#define SUN8I_MIXER_BLEND_OUTCTL(base) ((base) + 0xfc)
52	52	#define SUN50I_MIXER_BLEND_CSC_CTL(base) ((base) + 0x100)
53		−#define SUN50I_MIXER_BLEND_CSC_COEFF(base, layer, x, y) \
54		− ((base) + 0x110 + (layer) * 0x30 + (x) * 0x10 + 4 * (y))
55		−#define SUN50I_MIXER_BLEND_CSC_CONST(base, layer, i) \
56		− ((base) + 0x110 + (layer) * 0x30 + (i) * 0x10 + 0x0c)
	53	+#define SUN50I_MIXER_BLEND_CSC_COEFF(base, layer, x) \
	54	+ ((base) + 0x110 + (layer) * 0x30 + (x) * 4)
57	55
58	56	#define SUN8I_MIXER_BLEND_PIPE_CTL_EN_MSK GENMASK(12, 8)
59	57	#define SUN8I_MIXER_BLEND_PIPE_CTL_EN(pipe) BIT(8 + pipe)

drivers/gpu/drm/sun4i/sun8i_vi_layer.c+2−0

@@ -543,6 +543,8 @@ struct sun8i_vi_layer sun8i_vi_layer_init_one(struct drm_device drm, · 542 unmodified lines
543	543
544	544	supported_encodings = BIT(DRM_COLOR_YCBCR_BT601) \|
545	545	BIT(DRM_COLOR_YCBCR_BT709);
	546	+ if (mixer->cfg->is_de3)
	547	+ supported_encodings \|= BIT(DRM_COLOR_YCBCR_BT2020);
546	548
547	549	supported_ranges = BIT(DRM_COLOR_YCBCR_LIMITED_RANGE) \|
548	550	BIT(DRM_COLOR_YCBCR_FULL_RANGE);

drivers/gpu/drm/tiny/cirrus.c+0−1

@@ -602,7 +602,6 @@ static int cirrus_pci_probe(struct pci_dev *pdev, · 601 unmodified lines
602	602
603	603	drm_mode_config_reset(dev);
604	604
605		− dev->pdev = pdev;
606	605	pci_set_drvdata(pdev, dev);
607	606	ret = drm_dev_register(dev, 0);
608	607	if (ret)

drivers/gpu/drm/ttm/ttm_bo.c+3−1

@@ -138,8 +138,10 @@ void ttm_bo_move_to_lru_tail(struct ttm_buffer_object *bo, · 137 unmodified lines
138	138
139	139	dma_resv_assert_held(bo->base.resv);
140	140
141		− if (bo->pin_count)
	141	+ if (bo->pin_count) {
	142	+ ttm_bo_del_from_lru(bo);
142	143	return;
	144	+ }
143	145
144	146	man = ttm_manager_type(bdev, mem->mem_type);
145	147	list_move_tail(&bo->lru, &man->lru[bo->priority]);

drivers/gpu/drm/v3d/v3d_drv.c+2−2

@@ -232,8 +232,8 @@ static int v3d_platform_drm_probe(struct platform_device *pdev) · 231 unmodified lines
232	232	return ret;
233	233
234	234	mmu_debug = V3D_READ(V3D_MMU_DEBUG_INFO);
235		− dev->coherent_dma_mask =
236		− DMA_BIT_MASK(30 + V3D_GET_FIELD(mmu_debug, V3D_MMU_PA_WIDTH));
	235	+ dma_set_mask_and_coherent(dev,
	236	+ DMA_BIT_MASK(30 + V3D_GET_FIELD(mmu_debug, V3D_MMU_PA_WIDTH)));
237	237	v3d->va_width = 30 + V3D_GET_FIELD(mmu_debug, V3D_MMU_VA_WIDTH);
238	238
239	239	ident1 = V3D_READ(V3D_HUB_IDENT1);

drivers/gpu/drm/v3d/v3d_irq.c+2−5

@@ -178,10 +178,7 @@ v3d_hub_irq(int irq, void *arg) · 177 unmodified lines
178	178	};
179	179	const char *client = "?";
180	180
181		− V3D_WRITE(V3D_MMU_CTL,
182		− V3D_READ(V3D_MMU_CTL) & (V3D_MMU_CTL_CAP_EXCEEDED \|
183		− V3D_MMU_CTL_PT_INVALID \|
184		− V3D_MMU_CTL_WRITE_VIOLATION));
	181	+ V3D_WRITE(V3D_MMU_CTL, V3D_READ(V3D_MMU_CTL));
185	182
186	183	if (v3d->ver >= 41) {
187	184	axi_id = axi_id >> 5;
@@ -217,7 +214,7 @@ v3d_irq_init(struct v3d_dev *v3d) · 29 unmodified lines
217	214	V3D_CORE_WRITE(core, V3D_CTL_INT_CLR, V3D_CORE_IRQS);
218	215	V3D_WRITE(V3D_HUB_INT_CLR, V3D_HUB_IRQS);
219	216
220		− irq1 = platform_get_irq(v3d_to_pdev(v3d), 1);
	217	+ irq1 = platform_get_irq_optional(v3d_to_pdev(v3d), 1);
221	218	if (irq1 == -EPROBE_DEFER)
222	219	return irq1;
223	220	if (irq1 > 0) {

drivers/gpu/drm/vboxvideo/vbox_drv.c+6−5

@@ -51,7 +51,6 @@ static int vbox_pci_probe(struct pci_dev pdev, const struct pci_device_id ent) · 50 unmodified lines
51	51	if (IS_ERR(vbox))
52	52	return PTR_ERR(vbox);
53	53
54		− vbox->ddev.pdev = pdev;
55	54	pci_set_drvdata(pdev, vbox);
56	55	mutex_init(&vbox->hw_mutex);
57	56
@@ -109,15 +108,16 @@ static void vbox_pci_remove(struct pci_dev *pdev) · 51 unmodified lines
109	108	static int vbox_pm_suspend(struct device *dev)
110	109	{
111	110	struct vbox_private *vbox = dev_get_drvdata(dev);
	111	+ struct pci_dev *pdev = to_pci_dev(dev);
112	112	int error;
113	113
114	114	error = drm_mode_config_helper_suspend(&vbox->ddev);
115	115	if (error)
116	116	return error;
117	117
118		− pci_save_state(vbox->ddev.pdev);
119		− pci_disable_device(vbox->ddev.pdev);
120		− pci_set_power_state(vbox->ddev.pdev, PCI_D3hot);
	118	+ pci_save_state(pdev);
	119	+ pci_disable_device(pdev);
	120	+ pci_set_power_state(pdev, PCI_D3hot);
121	121
122	122	return 0;
123	123	}
@@ -125,8 +125,9 @@ static int vbox_pm_suspend(struct device *dev) · 1 unmodified line
125	125	static int vbox_pm_resume(struct device *dev)
126	126	{
127	127	struct vbox_private *vbox = dev_get_drvdata(dev);
	128	+ struct pci_dev *pdev = to_pci_dev(dev);
128	129
129		− if (pci_enable_device(vbox->ddev.pdev))
	130	+ if (pci_enable_device(pdev))
130	131	return -EIO;
131	132
132	133	return drm_mode_config_helper_resume(&vbox->ddev);

drivers/gpu/drm/vboxvideo/vbox_irq.c+3−1

@@ -170,10 +170,12 @@ static void vbox_hotplug_worker(struct work_struct *work) · 169 unmodified lines
170	170
171	171	int vbox_irq_init(struct vbox_private *vbox)
172	172	{
	173	+ struct pci_dev *pdev = to_pci_dev(vbox->ddev.dev);
	174	+
173	175	INIT_WORK(&vbox->hotplug_work, vbox_hotplug_worker);
174	176	vbox_update_mode_hints(vbox);
175	177
176		− return drm_irq_install(&vbox->ddev, vbox->ddev.pdev->irq);
	178	+ return drm_irq_install(&vbox->ddev, pdev->irq);
177	179	}
178	180
179	181	void vbox_irq_fini(struct vbox_private *vbox)

drivers/gpu/drm/vboxvideo/vbox_main.c+6−2

@@ -8,7 +8,9 @@ · 7 unmodified lines
8	8	* Hans de Goede <hdegoede@redhat.com>
9	9	*/
10	10
	11	+#include <linux/pci.h>
11	12	#include <linux/vbox_err.h>
	13	+
12	14	#include <drm/drm_fb_helper.h>
13	15	#include <drm/drm_crtc_helper.h>
14	16	#include <drm/drm_damage_helper.h>
@@ -30,6 +32,7 @@ void vbox_report_caps(struct vbox_private *vbox) · 15 unmodified lines
30	32
31	33	static int vbox_accel_init(struct vbox_private *vbox)
32	34	{
	35	+ struct pci_dev *pdev = to_pci_dev(vbox->ddev.dev);
33	36	struct vbva_buffer *vbva;
34	37	unsigned int i;
35	38
@@ -41,7 +44,7 @@ static int vbox_accel_init(struct vbox_private *vbox) · 5 unmodified lines
41	44	/* Take a command buffer for each screen from the end of usable VRAM. */
42	45	vbox->available_vram_size -= vbox->num_crtcs * VBVA_MIN_BUFFER_SIZE;
43	46
44		− vbox->vbva_buffers = pci_iomap_range(vbox->ddev.pdev, 0,
	47	+ vbox->vbva_buffers = pci_iomap_range(pdev, 0,
45	48	vbox->available_vram_size,
46	49	vbox->num_crtcs *
47	50	VBVA_MIN_BUFFER_SIZE);
@@ -106,6 +109,7 @@ bool vbox_check_supported(u16 id) · 58 unmodified lines
106	109
107	110	int vbox_hw_init(struct vbox_private *vbox)
108	111	{
	112	+ struct pci_dev *pdev = to_pci_dev(vbox->ddev.dev);
109	113	int ret = -ENOMEM;
110	114
111	115	vbox->full_vram_size = inl(VBE_DISPI_IOPORT_DATA);
@@ -115,7 +119,7 @@ int vbox_hw_init(struct vbox_private *vbox) · 3 unmodified lines
115	119
116	120	/* Map guest-heap at end of vram */
117	121	vbox->guest_heap =
118		− pci_iomap_range(vbox->ddev.pdev, 0, GUEST_HEAP_OFFSET(vbox),
	122	+ pci_iomap_range(pdev, 0, GUEST_HEAP_OFFSET(vbox),
119	123	GUEST_HEAP_SIZE);
120	124	if (!vbox->guest_heap)
121	125	return -ENOMEM;

drivers/gpu/drm/vboxvideo/vbox_ttm.c+4−3

@@ -15,8 +15,9 @@ int vbox_mm_init(struct vbox_private *vbox) · 14 unmodified lines
15	15	struct drm_vram_mm *vmm;
16	16	int ret;
17	17	struct drm_device *dev = &vbox->ddev;
	18	+ struct pci_dev *pdev = to_pci_dev(dev->dev);
18	19
19		− vmm = drm_vram_helper_alloc_mm(dev, pci_resource_start(dev->pdev, 0),
	20	+ vmm = drm_vram_helper_alloc_mm(dev, pci_resource_start(pdev, 0),
20	21	vbox->available_vram_size);
21	22	if (IS_ERR(vmm)) {
22	23	ret = PTR_ERR(vmm);
@@ -24,8 +25,8 @@ int vbox_mm_init(struct vbox_private *vbox) · 1 unmodified line
24	25	return ret;
25	26	}
26	27
27		− vbox->fb_mtrr = arch_phys_wc_add(pci_resource_start(dev->pdev, 0),
28		− pci_resource_len(dev->pdev, 0));
	28	+ vbox->fb_mtrr = arch_phys_wc_add(pci_resource_start(pdev, 0),
	29	+ pci_resource_len(pdev, 0));
29	30	return 0;
30	31	}
31	32

drivers/gpu/drm/vc4/vc4_bo.c+19−92

@@ -21,7 +21,7 @@ · 20 unmodified lines
21	21	#include "vc4_drv.h"
22	22	#include "uapi/drm/vc4_drm.h"
23	23
24		−static vm_fault_t vc4_fault(struct vm_fault *vmf);
	24	+static const struct drm_gem_object_funcs vc4_gem_object_funcs;
25	25
26	26	static const char * const bo_type_names[] = {
27	27	"kernel",
@@ -376,20 +376,6 @@ out: · 348 unmodified lines
376	376	return bo;
377	377	}
378	378
379		−static const struct vm_operations_struct vc4_vm_ops = {
380		− .fault = vc4_fault,
381		− .open = drm_gem_vm_open,
382		− .close = drm_gem_vm_close,
383		−};
384		−
385		−static const struct drm_gem_object_funcs vc4_gem_object_funcs = {
386		− .free = vc4_free_object,
387		− .export = vc4_prime_export,
388		− .get_sg_table = drm_gem_cma_get_sg_table,
389		− .vmap = vc4_prime_vmap,
390		− .vm_ops = &vc4_vm_ops,
391		−};
392		−
393	379	/**
394	380	* vc4_create_object - Implementation of driver->gem_create_object.
395	381	* @dev: DRM device
@@ -538,7 +524,7 @@ static void vc4_bo_cache_free_old(struct drm_device *dev) · 142 unmodified lines
538	524	/* Called on the last userspace/kernel unreference of the BO. Returns
539	525	* it to the BO cache if possible, otherwise frees it.
540	526	*/
541		−void vc4_free_object(struct drm_gem_object *gem_bo)
	527	+static void vc4_free_object(struct drm_gem_object *gem_bo)
542	528	{
543	529	struct drm_device *dev = gem_bo->dev;
544	530	struct vc4_dev *vc4 = to_vc4_dev(dev);
@@ -673,7 +659,7 @@ static void vc4_bo_cache_time_timer(struct timer_list *t) · 128 unmodified lines
673	659	schedule_work(&vc4->bo_cache.time_work);
674	660	}
675	661
676		−struct dma_buf * vc4_prime_export(struct drm_gem_object *obj, int flags)
	662	+static struct dma_buf vc4_prime_export(struct drm_gem_object obj, int flags)
677	663	{
678	664	struct vc4_bo *bo = to_vc4_bo(obj);
679	665	struct dma_buf *dmabuf;
@@ -718,19 +704,9 @@ static vm_fault_t vc4_fault(struct vm_fault *vmf) · 38 unmodified lines
718	704	return VM_FAULT_SIGBUS;
719	705	}
720	706
721		−int vc4_mmap(struct file filp, struct vm_area_struct vma)
	707	+static int vc4_gem_object_mmap(struct drm_gem_object obj, struct vm_area_struct vma)
722	708	{
723		− struct drm_gem_object *gem_obj;
724		− unsigned long vm_pgoff;
725		− struct vc4_bo *bo;
726		− int ret;
727		−
728		− ret = drm_gem_mmap(filp, vma);
729		− if (ret)
730		− return ret;
731		−
732		− gem_obj = vma->vm_private_data;
733		− bo = to_vc4_bo(gem_obj);
	709	+ struct vc4_bo *bo = to_vc4_bo(obj);
734	710
735	711	if (bo->validated_shader && (vma->vm_flags & VM_WRITE)) {
736	712	DRM_DEBUG("mmaping of shader BOs for writing not allowed.\n");
@@ -744,72 +720,23 @@ int vc4_mmap(struct file filp, struct vm_area_struct vma) · 7 unmodified lines
744	720	return -EINVAL;
745	721	}
746	722
747		− /*
748		− * Clear the VM_PFNMAP flag that was set by drm_gem_mmap(), and set the
749		− * vm_pgoff (used as a fake buffer offset by DRM) to 0 as we want to map
750		− * the whole buffer.
751		− */
752		− vma->vm_flags &= ~VM_PFNMAP;
753		−
754		− /* This ->vm_pgoff dance is needed to make all parties happy:
755		− * - dma_mmap_wc() uses ->vm_pgoff as an offset within the allocated
756		− * mem-region, hence the need to set it to zero (the value set by
757		− * the DRM core is a virtual offset encoding the GEM object-id)
758		− * - the mmap() core logic needs ->vm_pgoff to be restored to its
759		− * initial value before returning from this function because it
760		− * encodes the offset of this GEM in the dev->anon_inode pseudo-file
761		− * and this information will be used when we invalidate userspace
762		− * mappings with drm_vma_node_unmap() (called from vc4_gem_purge()).
763		− */
764		− vm_pgoff = vma->vm_pgoff;
765		− vma->vm_pgoff = 0;
766		− ret = dma_mmap_wc(bo->base.base.dev->dev, vma, bo->base.vaddr,
767		− bo->base.paddr, vma->vm_end - vma->vm_start);
768		− vma->vm_pgoff = vm_pgoff;
769		−
770		− if (ret)
771		− drm_gem_vm_close(vma);
772		−
773		− return ret;
774		−}
775		−
776		−int vc4_prime_mmap(struct drm_gem_object obj, struct vm_area_struct vma)
777		−{
778		− struct vc4_bo *bo = to_vc4_bo(obj);
779		−
780		− if (bo->validated_shader && (vma->vm_flags & VM_WRITE)) {
781		− DRM_DEBUG("mmaping of shader BOs for writing not allowed.\n");
782		− return -EINVAL;
783		− }
784		−
785		− return drm_gem_prime_mmap(obj, vma);
	723	+ return drm_gem_cma_mmap(obj, vma);
786	724	}
787	725
788		−int vc4_prime_vmap(struct drm_gem_object obj, struct dma_buf_map map)
789		−{
790		− struct vc4_bo *bo = to_vc4_bo(obj);
791		−
792		− if (bo->validated_shader) {
793		− DRM_DEBUG("mmaping of shader BOs not allowed.\n");
794		− return -EINVAL;
795		− }
796		−
797		− return drm_gem_cma_vmap(obj, map);
798		−}
799		−
800		−struct drm_gem_object *
801		−vc4_prime_import_sg_table(struct drm_device *dev,
802		− struct dma_buf_attachment *attach,
803		− struct sg_table *sgt)
804		−{
805		− struct drm_gem_object *obj;
806		−
807		− obj = drm_gem_cma_prime_import_sg_table(dev, attach, sgt);
808		− if (IS_ERR(obj))
809		− return obj;
	726	+static const struct vm_operations_struct vc4_vm_ops = {
	727	+ .fault = vc4_fault,
	728	+ .open = drm_gem_vm_open,
	729	+ .close = drm_gem_vm_close,
	730	+};
810	731
811		− return obj;
812		−}
	732	+static const struct drm_gem_object_funcs vc4_gem_object_funcs = {
	733	+ .free = vc4_free_object,
	734	+ .export = vc4_prime_export,
	735	+ .get_sg_table = drm_gem_cma_get_sg_table,
	736	+ .vmap = drm_gem_cma_vmap,
	737	+ .mmap = vc4_gem_object_mmap,
	738	+ .vm_ops = &vc4_vm_ops,
	739	+};
813	740
814	741	static int vc4_grab_bin_bo(struct vc4_dev vc4, struct vc4_file vc4file)
815	742	{

drivers/gpu/drm/vc4/vc4_drv.c+2−17

@@ -140,17 +140,7 @@ static void vc4_close(struct drm_device dev, struct drm_file file) · 139 unmodified lines
140	140	kfree(vc4file);
141	141	}
142	142
143		−static const struct file_operations vc4_drm_fops = {
144		− .owner = THIS_MODULE,
145		− .open = drm_open,
146		− .release = drm_release,
147		− .unlocked_ioctl = drm_ioctl,
148		− .mmap = vc4_mmap,
149		− .poll = drm_poll,
150		− .read = drm_read,
151		− .compat_ioctl = drm_compat_ioctl,
152		− .llseek = noop_llseek,
153		−};
	143	+DEFINE_DRM_GEM_FOPS(vc4_drm_fops);
154	144
155	145	static const struct drm_ioctl_desc vc4_drm_ioctls[] = {
156	146	DRM_IOCTL_DEF_DRV(VC4_SUBMIT_CL, vc4_submit_cl_ioctl, DRM_RENDER_ALLOW),
@@ -190,12 +180,7 @@ static struct drm_driver vc4_drm_driver = { · 33 unmodified lines
190	180
191	181	.gem_create_object = vc4_create_object,
192	182
193		− .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
194		− .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
195		− .gem_prime_import_sg_table = vc4_prime_import_sg_table,
196		− .gem_prime_mmap = vc4_prime_mmap,
197		−
198		− .dumb_create = vc4_dumb_create,
	183	+ DRM_GEM_CMA_DRIVER_OPS_WITH_DUMB_CREATE(vc4_dumb_create),
199	184
200	185	.ioctls = vc4_drm_ioctls,
201	186	.num_ioctls = ARRAY_SIZE(vc4_drm_ioctls),

drivers/gpu/drm/vc4/vc4_drv.h+0−8

@@ -782,13 +782,11 @@ struct vc4_validated_shader_info { · 781 unmodified lines
782	782
783	783	/* vc4_bo.c */
784	784	struct drm_gem_object vc4_create_object(struct drm_device dev, size_t size);
785		−void vc4_free_object(struct drm_gem_object *gem_obj);
786	785	struct vc4_bo vc4_bo_create(struct drm_device dev, size_t size,
787	786	bool from_cache, enum vc4_kernel_bo_type type);
788	787	int vc4_dumb_create(struct drm_file *file_priv,
789	788	struct drm_device *dev,
790	789	struct drm_mode_create_dumb *args);
791		−struct dma_buf vc4_prime_export(struct drm_gem_object obj, int flags);
792	790	int vc4_create_bo_ioctl(struct drm_device dev, void data,
793	791	struct drm_file *file_priv);
794	792	int vc4_create_shader_bo_ioctl(struct drm_device dev, void data,
@@ -803,12 +801,6 @@ int vc4_get_hang_state_ioctl(struct drm_device dev, void data, · 8 unmodified lines
803	801	struct drm_file *file_priv);
804	802	int vc4_label_bo_ioctl(struct drm_device dev, void data,
805	803	struct drm_file *file_priv);
806		−int vc4_mmap(struct file filp, struct vm_area_struct vma);
807		−int vc4_prime_mmap(struct drm_gem_object obj, struct vm_area_struct vma);
808		−struct drm_gem_object vc4_prime_import_sg_table(struct drm_device dev,
809		− struct dma_buf_attachment *attach,
810		− struct sg_table *sgt);
811		−int vc4_prime_vmap(struct drm_gem_object obj, struct dma_buf_map map);
812	804	int vc4_bo_cache_init(struct drm_device *dev);
813	805	int vc4_bo_inc_usecnt(struct vc4_bo *bo);
814	806	void vc4_bo_dec_usecnt(struct vc4_bo *bo);

drivers/gpu/drm/virtio/virtgpu_drv.c+0−1

@@ -54,7 +54,6 @@ static int virtio_gpu_pci_quirk(struct drm_device dev, struct virtio_device vd · 53 unmodified lines
54	54	DRM_INFO("pci: %s detected at %s\n",
55	55	vga ? "virtio-vga" : "virtio-gpu-pci",
56	56	pname);
57		− dev->pdev = pdev;
58	57	if (vga)
59	58	drm_fb_helper_remove_conflicting_pci_framebuffers(pdev,
60	59	"virtiodrmfb");

drivers/gpu/drm/virtio/virtgpu_gem.c+5−3

@@ -39,9 +39,6 @@ static int virtio_gpu_gem_create(struct drm_file *file, · 38 unmodified lines
39	39	int ret;
40	40	u32 handle;
41	41
42		− if (vgdev->has_virgl_3d)
43		− virtio_gpu_create_context(dev, file);
44		−
45	42	ret = virtio_gpu_object_create(vgdev, params, &obj, NULL);
46	43	if (ret < 0)
47	44	return ret;
@@ -119,6 +116,11 @@ int virtio_gpu_gem_object_open(struct drm_gem_object *obj, · 71 unmodified lines
119	116	if (!vgdev->has_virgl_3d)
120	117	goto out_notify;
121	118
	119	+ /* the context might still be missing when the first ioctl is
	120	+ * DRM_IOCTL_MODE_CREATE_DUMB or DRM_IOCTL_PRIME_FD_TO_HANDLE
	121	+ */
	122	+ virtio_gpu_create_context(obj->dev, file);
	123	+
122	124	objs = virtio_gpu_array_alloc(1);
123	125	if (!objs)
124	126	return -ENOMEM;

drivers/gpu/drm/virtio/virtgpu_vram.c+1−0

@@ -69,6 +69,7 @@ static const struct drm_gem_object_funcs virtio_gpu_vram_funcs = { · 68 unmodified lines
69	69	.close = virtio_gpu_gem_object_close,
70	70	.free = virtio_gpu_vram_free,
71	71	.mmap = virtio_gpu_vram_mmap,
	72	+ .export = virtgpu_gem_prime_export,
72	73	};
73	74
74	75	bool virtio_gpu_is_vram(struct virtio_gpu_object *bo)

drivers/gpu/drm/vkms/vkms_drv.c+41−8

@@ -34,12 +34,16 @@ · 33 unmodified lines
34	34	#define DRIVER_MAJOR 1
35	35	#define DRIVER_MINOR 0
36	36
37		−static struct vkms_device *vkms_device;
	37	+static struct vkms_config *default_config;
38	38
39		−bool enable_cursor = true;
	39	+static bool enable_cursor = true;
40	40	module_param_named(enable_cursor, enable_cursor, bool, 0444);
41	41	MODULE_PARM_DESC(enable_cursor, "Enable/Disable cursor support");
42	42
	43	+static bool enable_writeback = true;
	44	+module_param_named(enable_writeback, enable_writeback, bool, 0444);
	45	+MODULE_PARM_DESC(enable_writeback, "Enable/Disable writeback connector support");
	46	+
43	47	DEFINE_DRM_GEM_FOPS(vkms_driver_fops);
44	48
45	49	static void vkms_release(struct drm_device *dev)
@@ -122,10 +126,11 @@ static int vkms_modeset_init(struct vkms_device *vkmsdev) · 76 unmodified lines
122	126	return vkms_output_init(vkmsdev, 0);
123	127	}
124	128
125		−static int __init vkms_init(void)
	129	+static int vkms_create(struct vkms_config *config)
126	130	{
127	131	int ret;
128	132	struct platform_device *pdev;
	133	+ struct vkms_device *vkms_device;
129	134
130	135	pdev = platform_device_register_simple(DRIVER_NAME, -1, NULL, 0);
131	136	if (IS_ERR(pdev))
@@ -143,6 +148,8 @@ static int __init vkms_init(void) · 11 unmodified lines
143	148	goto out_devres;
144	149	}
145	150	vkms_device->platform = pdev;
	151	+ vkms_device->config = config;
	152	+ config->dev = vkms_device;
146	153
147	154	ret = dma_coerce_mask_and_coherent(vkms_device->drm.dev,
148	155	DMA_BIT_MASK(64));
@@ -179,21 +186,47 @@ out_unregister: · 30 unmodified lines
179	186	return ret;
180	187	}
181	188
182		−static void __exit vkms_exit(void)
	189	+static int __init vkms_init(void)
	190	+{
	191	+ struct vkms_config *config;
	192	+
	193	+ config = kmalloc(sizeof(*config), GFP_KERNEL);
	194	+ if (!config)
	195	+ return -ENOMEM;
	196	+
	197	+ default_config = config;
	198	+
	199	+ config->cursor = enable_cursor;
	200	+ config->writeback = enable_writeback;
	201	+
	202	+ return vkms_create(config);
	203	+}
	204	+
	205	+static void vkms_destroy(struct vkms_config *config)
183	206	{
184	207	struct platform_device *pdev;
185	208
186		− if (!vkms_device) {
	209	+ if (!config->dev) {
187	210	DRM_INFO("vkms_device is NULL.\n");
188	211	return;
189	212	}
190	213
191		− pdev = vkms_device->platform;
	214	+ pdev = config->dev->platform;
192	215
193		− drm_dev_unregister(&vkms_device->drm);
194		− drm_atomic_helper_shutdown(&vkms_device->drm);
	216	+ drm_dev_unregister(&config->dev->drm);
	217	+ drm_atomic_helper_shutdown(&config->dev->drm);
195	218	devres_release_group(&pdev->dev, NULL);
196	219	platform_device_unregister(pdev);
	220	+
	221	+ config->dev = NULL;
	222	+}
	223	+
	224	+static void __exit vkms_exit(void)
	225	+{
	226	+ if (default_config->dev)
	227	+ vkms_destroy(default_config);
	228	+
	229	+ kfree(default_config);
197	230	}
198	231
199	232	module_init(vkms_init);

drivers/gpu/drm/vkms/vkms_drv.h+10−2

@@ -19,8 +19,6 @@ · 18 unmodified lines
19	19	#define XRES_MAX 8192
20	20	#define YRES_MAX 8192
21	21
22		−extern bool enable_cursor;
23		−
24	22	struct vkms_composer {
25	23	struct drm_framebuffer fb;
26	24	struct drm_rect src, dst;
@@ -82,10 +80,20 @@ struct vkms_output { · 55 unmodified lines
82	80	spinlock_t composer_lock;
83	81	};
84	82
	83	+struct vkms_device;
	84	+
	85	+struct vkms_config {
	86	+ bool writeback;
	87	+ bool cursor;
	88	+ /* only set when instantiated */
	89	+ struct vkms_device *dev;
	90	+};
	91	+
85	92	struct vkms_device {
86	93	struct drm_device drm;
87	94	struct platform_device *platform;
88	95	struct vkms_output output;
	96	+ const struct vkms_config *config;
89	97	};
90	98
91	99	#define drm_crtc_to_vkms_output(target) \

drivers/gpu/drm/vkms/vkms_output.c+8−5

@@ -41,12 +41,13 @@ int vkms_output_init(struct vkms_device *vkmsdev, int index) · 40 unmodified lines
41	41	struct drm_crtc *crtc = &output->crtc;
42	42	struct drm_plane primary, cursor = NULL;
43	43	int ret;
	44	+ int writeback;
44	45
45	46	primary = vkms_plane_init(vkmsdev, DRM_PLANE_TYPE_PRIMARY, index);
46	47	if (IS_ERR(primary))
47	48	return PTR_ERR(primary);
48	49
49		− if (enable_cursor) {
	50	+ if (vkmsdev->config->cursor) {
50	51	cursor = vkms_plane_init(vkmsdev, DRM_PLANE_TYPE_CURSOR, index);
51	52	if (IS_ERR(cursor)) {
52	53	ret = PTR_ERR(cursor);
@@ -80,9 +81,11 @@ int vkms_output_init(struct vkms_device *vkmsdev, int index) · 27 unmodified lines
80	81	goto err_attach;
81	82	}
82	83
83		− ret = vkms_enable_writeback_connector(vkmsdev);
84		− if (ret)
85		− DRM_ERROR("Failed to init writeback connector\n");
	84	+ if (vkmsdev->config->writeback) {
	85	+ writeback = vkms_enable_writeback_connector(vkmsdev);
	86	+ if (writeback)
	87	+ DRM_ERROR("Failed to init writeback connector\n");
	88	+ }
86	89
87	90	drm_mode_config_reset(dev);
88	91
@@ -98,7 +101,7 @@ err_connector: · 9 unmodified lines
98	101	drm_crtc_cleanup(crtc);
99	102
100	103	err_crtc:
101		− if (enable_cursor)
	104	+ if (vkmsdev->config->cursor)
102	105	drm_plane_cleanup(cursor);
103	106
104	107	err_cursor:

drivers/gpu/drm/vmwgfx/Makefile+3−3

@@ -1,9 +1,9 @@
1	1	# SPDX-License-Identifier: GPL-2.0
2	2	vmwgfx-y := vmwgfx_execbuf.o vmwgfx_gmr.o vmwgfx_kms.o vmwgfx_drv.o \
3	3	vmwgfx_fb.o vmwgfx_ioctl.o vmwgfx_resource.o vmwgfx_ttm_buffer.o \
4		− vmwgfx_fifo.o vmwgfx_irq.o vmwgfx_ldu.o vmwgfx_ttm_glue.o \
5		− vmwgfx_overlay.o vmwgfx_marker.o vmwgfx_gmrid_manager.o \
6		− vmwgfx_fence.o vmwgfx_bo.o vmwgfx_scrn.o vmwgfx_context.o \
	4	+ vmwgfx_cmd.o vmwgfx_irq.o vmwgfx_ldu.o vmwgfx_ttm_glue.o \
	5	+ vmwgfx_overlay.o vmwgfx_gmrid_manager.o vmwgfx_fence.o \
	6	+ vmwgfx_bo.o vmwgfx_scrn.o vmwgfx_context.o \
7	7	vmwgfx_surface.o vmwgfx_prime.o vmwgfx_mob.o vmwgfx_shader.o \
8	8	vmwgfx_cmdbuf_res.o vmwgfx_cmdbuf.o vmwgfx_stdu.o \
9	9	vmwgfx_cotable.o vmwgfx_so.o vmwgfx_binding.o vmwgfx_msg.o \

drivers/gpu/drm/vmwgfx/vmwgfx_binding.c+26−26

@@ -555,7 +555,7 @@ static int vmw_binding_scrub_shader(struct vmw_ctx_bindinfo *bi, bool rebind) · 554 unmodified lines
555	555	SVGA3dCmdSetShader body;
556	556	} *cmd;
557	557
558		− cmd = VMW_FIFO_RESERVE(dev_priv, sizeof(*cmd));
	558	+ cmd = VMW_CMD_RESERVE(dev_priv, sizeof(*cmd));
559	559	if (unlikely(cmd == NULL))
560	560	return -ENOMEM;
561	561
@@ -564,7 +564,7 @@ static int vmw_binding_scrub_shader(struct vmw_ctx_bindinfo *bi, bool rebind) · 2 unmodified lines
564	564	cmd->body.cid = bi->ctx->id;
565	565	cmd->body.type = binding->shader_slot + SVGA3D_SHADERTYPE_MIN;
566	566	cmd->body.shid = ((rebind) ? bi->res->id : SVGA3D_INVALID_ID);
567		− vmw_fifo_commit(dev_priv, sizeof(*cmd));
	567	+ vmw_cmd_commit(dev_priv, sizeof(*cmd));
568	568
569	569	return 0;
570	570	}
@@ -587,7 +587,7 @@ static int vmw_binding_scrub_render_target(struct vmw_ctx_bindinfo *bi, · 16 unmodified lines
587	587	SVGA3dCmdSetRenderTarget body;
588	588	} *cmd;
589	589
590		− cmd = VMW_FIFO_RESERVE(dev_priv, sizeof(*cmd));
	590	+ cmd = VMW_CMD_RESERVE(dev_priv, sizeof(*cmd));
591	591	if (unlikely(cmd == NULL))
592	592	return -ENOMEM;
593	593
@@ -598,7 +598,7 @@ static int vmw_binding_scrub_render_target(struct vmw_ctx_bindinfo *bi, · 4 unmodified lines
598	598	cmd->body.target.sid = ((rebind) ? bi->res->id : SVGA3D_INVALID_ID);
599	599	cmd->body.target.face = 0;
600	600	cmd->body.target.mipmap = 0;
601		− vmw_fifo_commit(dev_priv, sizeof(*cmd));
	601	+ vmw_cmd_commit(dev_priv, sizeof(*cmd));
602	602
603	603	return 0;
604	604	}
@@ -626,7 +626,7 @@ static int vmw_binding_scrub_texture(struct vmw_ctx_bindinfo *bi, · 21 unmodified lines
626	626	} body;
627	627	} *cmd;
628	628
629		− cmd = VMW_FIFO_RESERVE(dev_priv, sizeof(*cmd));
	629	+ cmd = VMW_CMD_RESERVE(dev_priv, sizeof(*cmd));
630	630	if (unlikely(cmd == NULL))
631	631	return -ENOMEM;
632	632
@@ -636,7 +636,7 @@ static int vmw_binding_scrub_texture(struct vmw_ctx_bindinfo *bi, · 3 unmodified lines
636	636	cmd->body.s1.stage = binding->texture_stage;
637	637	cmd->body.s1.name = SVGA3D_TS_BIND_TEXTURE;
638	638	cmd->body.s1.value = ((rebind) ? bi->res->id : SVGA3D_INVALID_ID);
639		− vmw_fifo_commit(dev_priv, sizeof(*cmd));
	639	+ vmw_cmd_commit(dev_priv, sizeof(*cmd));
640	640
641	641	return 0;
642	642	}
@@ -657,7 +657,7 @@ static int vmw_binding_scrub_dx_shader(struct vmw_ctx_bindinfo *bi, bool rebind) · 14 unmodified lines
657	657	SVGA3dCmdDXSetShader body;
658	658	} *cmd;
659	659
660		− cmd = VMW_FIFO_RESERVE_DX(dev_priv, sizeof(*cmd), bi->ctx->id);
	660	+ cmd = VMW_CMD_CTX_RESERVE(dev_priv, sizeof(*cmd), bi->ctx->id);
661	661	if (unlikely(cmd == NULL))
662	662	return -ENOMEM;
663	663
@@ -665,7 +665,7 @@ static int vmw_binding_scrub_dx_shader(struct vmw_ctx_bindinfo *bi, bool rebind) · 1 unmodified line
665	665	cmd->header.size = sizeof(cmd->body);
666	666	cmd->body.type = binding->shader_slot + SVGA3D_SHADERTYPE_MIN;
667	667	cmd->body.shaderId = ((rebind) ? bi->res->id : SVGA3D_INVALID_ID);
668		− vmw_fifo_commit(dev_priv, sizeof(*cmd));
	668	+ vmw_cmd_commit(dev_priv, sizeof(*cmd));
669	669
670	670	return 0;
671	671	}
@@ -686,7 +686,7 @@ static int vmw_binding_scrub_cb(struct vmw_ctx_bindinfo *bi, bool rebind) · 14 unmodified lines
686	686	SVGA3dCmdDXSetSingleConstantBuffer body;
687	687	} *cmd;
688	688
689		− cmd = VMW_FIFO_RESERVE_DX(dev_priv, sizeof(*cmd), bi->ctx->id);
	689	+ cmd = VMW_CMD_CTX_RESERVE(dev_priv, sizeof(*cmd), bi->ctx->id);
690	690	if (unlikely(cmd == NULL))
691	691	return -ENOMEM;
692	692
@@ -703,7 +703,7 @@ static int vmw_binding_scrub_cb(struct vmw_ctx_bindinfo *bi, bool rebind) · 10 unmodified lines
703	703	cmd->body.sizeInBytes = 0;
704	704	cmd->body.sid = SVGA3D_INVALID_ID;
705	705	}
706		− vmw_fifo_commit(dev_priv, sizeof(*cmd));
	706	+ vmw_cmd_commit(dev_priv, sizeof(*cmd));
707	707
708	708	return 0;
709	709	}
@@ -810,7 +810,7 @@ static int vmw_emit_set_sr(struct vmw_ctx_binding_state *cbs, · 100 unmodified lines
810	810
811	811	view_id_size = cbs->bind_cmd_count*sizeof(uint32);
812	812	cmd_size = sizeof(*cmd) + view_id_size;
813		− cmd = VMW_FIFO_RESERVE_DX(ctx->dev_priv, cmd_size, ctx->id);
	813	+ cmd = VMW_CMD_CTX_RESERVE(ctx->dev_priv, cmd_size, ctx->id);
814	814	if (unlikely(cmd == NULL))
815	815	return -ENOMEM;
816	816
@@ -821,7 +821,7 @@ static int vmw_emit_set_sr(struct vmw_ctx_binding_state *cbs, · 4 unmodified lines
821	821
822	822	memcpy(&cmd[1], cbs->bind_cmd_buffer, view_id_size);
823	823
824		− vmw_fifo_commit(ctx->dev_priv, cmd_size);
	824	+ vmw_cmd_commit(ctx->dev_priv, cmd_size);
825	825	bitmap_clear(cbs->per_shader[shader_slot].dirty_sr,
826	826	cbs->bind_first_slot, cbs->bind_cmd_count);
827	827
@@ -846,7 +846,7 @@ static int vmw_emit_set_rt(struct vmw_ctx_binding_state *cbs) · 18 unmodified lines
846	846	vmw_collect_view_ids(cbs, loc, SVGA3D_MAX_SIMULTANEOUS_RENDER_TARGETS);
847	847	view_id_size = cbs->bind_cmd_count*sizeof(uint32);
848	848	cmd_size = sizeof(*cmd) + view_id_size;
849		− cmd = VMW_FIFO_RESERVE_DX(ctx->dev_priv, cmd_size, ctx->id);
	849	+ cmd = VMW_CMD_CTX_RESERVE(ctx->dev_priv, cmd_size, ctx->id);
850	850	if (unlikely(cmd == NULL))
851	851	return -ENOMEM;
852	852
@@ -860,7 +860,7 @@ static int vmw_emit_set_rt(struct vmw_ctx_binding_state *cbs) · 7 unmodified lines
860	860
861	861	memcpy(&cmd[1], cbs->bind_cmd_buffer, view_id_size);
862	862
863		− vmw_fifo_commit(ctx->dev_priv, cmd_size);
	863	+ vmw_cmd_commit(ctx->dev_priv, cmd_size);
864	864
865	865	return 0;
866	866
@@ -930,7 +930,7 @@ static int vmw_emit_set_so_target(struct vmw_ctx_binding_state *cbs) · 63 unmodified lines
930	930
931	931	so_target_size = cbs->bind_cmd_count*sizeof(SVGA3dSoTarget);
932	932	cmd_size = sizeof(*cmd) + so_target_size;
933		− cmd = VMW_FIFO_RESERVE_DX(ctx->dev_priv, cmd_size, ctx->id);
	933	+ cmd = VMW_CMD_CTX_RESERVE(ctx->dev_priv, cmd_size, ctx->id);
934	934	if (unlikely(cmd == NULL))
935	935	return -ENOMEM;
936	936
@@ -938,7 +938,7 @@ static int vmw_emit_set_so_target(struct vmw_ctx_binding_state *cbs) · 1 unmodified line
938	938	cmd->header.size = sizeof(cmd->body) + so_target_size;
939	939	memcpy(&cmd[1], cbs->bind_cmd_buffer, so_target_size);
940	940
941		− vmw_fifo_commit(ctx->dev_priv, cmd_size);
	941	+ vmw_cmd_commit(ctx->dev_priv, cmd_size);
942	942
943	943	return 0;
944	944
@@ -1044,7 +1044,7 @@ static int vmw_emit_set_vb(struct vmw_ctx_binding_state *cbs) · 99 unmodified lines
1044	1044
1045	1045	set_vb_size = cbs->bind_cmd_count*sizeof(SVGA3dVertexBuffer);
1046	1046	cmd_size = sizeof(*cmd) + set_vb_size;
1047		− cmd = VMW_FIFO_RESERVE_DX(ctx->dev_priv, cmd_size, ctx->id);
	1047	+ cmd = VMW_CMD_CTX_RESERVE(ctx->dev_priv, cmd_size, ctx->id);
1048	1048	if (unlikely(cmd == NULL))
1049	1049	return -ENOMEM;
1050	1050
@@ -1054,7 +1054,7 @@ static int vmw_emit_set_vb(struct vmw_ctx_binding_state *cbs) · 3 unmodified lines
1054	1054
1055	1055	memcpy(&cmd[1], cbs->bind_cmd_buffer, set_vb_size);
1056	1056
1057		− vmw_fifo_commit(ctx->dev_priv, cmd_size);
	1057	+ vmw_cmd_commit(ctx->dev_priv, cmd_size);
1058	1058	bitmap_clear(cbs->dirty_vb,
1059	1059	cbs->bind_first_slot, cbs->bind_cmd_count);
1060	1060
@@ -1074,7 +1074,7 @@ static int vmw_emit_set_uav(struct vmw_ctx_binding_state *cbs) · 13 unmodified lines
1074	1074	vmw_collect_view_ids(cbs, loc, SVGA3D_MAX_UAVIEWS);
1075	1075	view_id_size = cbs->bind_cmd_count*sizeof(uint32);
1076	1076	cmd_size = sizeof(*cmd) + view_id_size;
1077		− cmd = VMW_FIFO_RESERVE_DX(ctx->dev_priv, cmd_size, ctx->id);
	1077	+ cmd = VMW_CMD_CTX_RESERVE(ctx->dev_priv, cmd_size, ctx->id);
1078	1078	if (!cmd)
1079	1079	return -ENOMEM;
1080	1080
@@ -1086,7 +1086,7 @@ static int vmw_emit_set_uav(struct vmw_ctx_binding_state *cbs) · 5 unmodified lines
1086	1086
1087	1087	memcpy(&cmd[1], cbs->bind_cmd_buffer, view_id_size);
1088	1088
1089		− vmw_fifo_commit(ctx->dev_priv, cmd_size);
	1089	+ vmw_cmd_commit(ctx->dev_priv, cmd_size);
1090	1090
1091	1091	return 0;
1092	1092	}
@@ -1104,7 +1104,7 @@ static int vmw_emit_set_cs_uav(struct vmw_ctx_binding_state *cbs) · 11 unmodified lines
1104	1104	vmw_collect_view_ids(cbs, loc, SVGA3D_MAX_UAVIEWS);
1105	1105	view_id_size = cbs->bind_cmd_count*sizeof(uint32);
1106	1106	cmd_size = sizeof(*cmd) + view_id_size;
1107		− cmd = VMW_FIFO_RESERVE_DX(ctx->dev_priv, cmd_size, ctx->id);
	1107	+ cmd = VMW_CMD_CTX_RESERVE(ctx->dev_priv, cmd_size, ctx->id);
1108	1108	if (!cmd)
1109	1109	return -ENOMEM;
1110	1110
@@ -1116,7 +1116,7 @@ static int vmw_emit_set_cs_uav(struct vmw_ctx_binding_state *cbs) · 5 unmodified lines
1116	1116
1117	1117	memcpy(&cmd[1], cbs->bind_cmd_buffer, view_id_size);
1118	1118
1119		− vmw_fifo_commit(ctx->dev_priv, cmd_size);
	1119	+ vmw_cmd_commit(ctx->dev_priv, cmd_size);
1120	1120
1121	1121	return 0;
1122	1122	}
@@ -1263,7 +1263,7 @@ static int vmw_binding_scrub_ib(struct vmw_ctx_bindinfo *bi, bool rebind) · 140 unmodified lines
1263	1263	SVGA3dCmdDXSetIndexBuffer body;
1264	1264	} *cmd;
1265	1265
1266		− cmd = VMW_FIFO_RESERVE_DX(dev_priv, sizeof(*cmd), bi->ctx->id);
	1266	+ cmd = VMW_CMD_CTX_RESERVE(dev_priv, sizeof(*cmd), bi->ctx->id);
1267	1267	if (unlikely(cmd == NULL))
1268	1268	return -ENOMEM;
1269	1269
@@ -1279,7 +1279,7 @@ static int vmw_binding_scrub_ib(struct vmw_ctx_bindinfo *bi, bool rebind) · 9 unmodified lines
1279	1279	cmd->body.offset = 0;
1280	1280	}
1281	1281
1282		− vmw_fifo_commit(dev_priv, sizeof(*cmd));
	1282	+ vmw_cmd_commit(dev_priv, sizeof(*cmd));
1283	1283
1284	1284	return 0;
1285	1285	}
@@ -1315,14 +1315,14 @@ static int vmw_binding_scrub_so(struct vmw_ctx_bindinfo *bi, bool rebind) · 29 unmodified lines
1315	1315	SVGA3dCmdDXSetStreamOutput body;
1316	1316	} *cmd;
1317	1317
1318		− cmd = VMW_FIFO_RESERVE_DX(dev_priv, sizeof(*cmd), bi->ctx->id);
	1318	+ cmd = VMW_CMD_CTX_RESERVE(dev_priv, sizeof(*cmd), bi->ctx->id);
1319	1319	if (!cmd)
1320	1320	return -ENOMEM;
1321	1321
1322	1322	cmd->header.id = SVGA_3D_CMD_DX_SET_STREAMOUTPUT;
1323	1323	cmd->header.size = sizeof(cmd->body);
1324	1324	cmd->body.soid = rebind ? bi->res->id : SVGA3D_INVALID_ID;
1325		− vmw_fifo_commit(dev_priv, sizeof(*cmd));
	1325	+ vmw_cmd_commit(dev_priv, sizeof(*cmd));
1326	1326
1327	1327	return 0;
1328	1328	}

drivers/gpu/drm/vmwgfx/vmwgfx_cmd.crenamed from drivers/gpu/drm/vmwgfx/vmwgfx_fifo.c+59−67

@@ -1,7 +1,7 @@
1	1	// SPDX-License-Identifier: GPL-2.0 OR MIT
2	2	/**************************************************************************
3	3	*
4		− * Copyright 2009-2015 VMware, Inc., Palo Alto, CA., USA
	4	+ * Copyright 2009-2020 VMware, Inc., Palo Alto, CA., USA
5	5	*
6	6	* Permission is hereby granted, free of charge, to any person obtaining a
7	7	* copy of this software and associated documentation files (the
@@ -36,9 +36,8 @@ struct vmw_temp_set_context { · 28 unmodified lines
36	36	SVGA3dCmdDXTempSetContext body;
37	37	};
38	38
39		−bool vmw_fifo_have_3d(struct vmw_private *dev_priv)
	39	+bool vmw_supports_3d(struct vmw_private *dev_priv)
40	40	{
41		− u32 *fifo_mem = dev_priv->mmio_virt;
42	41	uint32_t fifo_min, hwversion;
43	42	const struct vmw_fifo_state *fifo = &dev_priv->fifo;
44	43
@@ -62,15 +61,15 @@ bool vmw_fifo_have_3d(struct vmw_private *dev_priv) · 17 unmodified lines
62	61	if (!(dev_priv->capabilities & SVGA_CAP_EXTENDED_FIFO))
63	62	return false;
64	63
65		− fifo_min = vmw_mmio_read(fifo_mem + SVGA_FIFO_MIN);
	64	+ fifo_min = vmw_fifo_mem_read(dev_priv, SVGA_FIFO_MIN);
66	65	if (fifo_min <= SVGA_FIFO_3D_HWVERSION * sizeof(unsigned int))
67	66	return false;
68	67
69		− hwversion = vmw_mmio_read(fifo_mem +
70		− ((fifo->capabilities &
71		− SVGA_FIFO_CAP_3D_HWVERSION_REVISED) ?
72		− SVGA_FIFO_3D_HWVERSION_REVISED :
73		− SVGA_FIFO_3D_HWVERSION));
	68	+ hwversion = vmw_fifo_mem_read(dev_priv,
	69	+ ((fifo->capabilities &
	70	+ SVGA_FIFO_CAP_3D_HWVERSION_REVISED) ?
	71	+ SVGA_FIFO_3D_HWVERSION_REVISED :
	72	+ SVGA_FIFO_3D_HWVERSION));
74	73
75	74	if (hwversion == 0)
76	75	return false;
@@ -87,13 +86,12 @@ bool vmw_fifo_have_3d(struct vmw_private *dev_priv) · 10 unmodified lines
87	86
88	87	bool vmw_fifo_have_pitchlock(struct vmw_private *dev_priv)
89	88	{
90		− u32 *fifo_mem = dev_priv->mmio_virt;
91	89	uint32_t caps;
92	90
93	91	if (!(dev_priv->capabilities & SVGA_CAP_EXTENDED_FIFO))
94	92	return false;
95	93
96		− caps = vmw_mmio_read(fifo_mem + SVGA_FIFO_CAPABILITIES);
	94	+ caps = vmw_fifo_mem_read(dev_priv, SVGA_FIFO_CAPABILITIES);
97	95	if (caps & SVGA_FIFO_CAP_PITCHLOCK)
98	96	return true;
99	97
@@ -102,7 +100,6 @@ bool vmw_fifo_have_pitchlock(struct vmw_private *dev_priv) · 2 unmodified lines
102	100
103	101	int vmw_fifo_init(struct vmw_private dev_priv, struct vmw_fifo_state fifo)
104	102	{
105		− u32 *fifo_mem = dev_priv->mmio_virt;
106	103	uint32_t max;
107	104	uint32_t min;
108	105
@@ -129,6 +126,7 @@ int vmw_fifo_init(struct vmw_private dev_priv, struct vmw_fifo_state fifo) · 20 unmodified lines
129	126
130	127	vmw_write(dev_priv, SVGA_REG_ENABLE, SVGA_REG_ENABLE_ENABLE \|
131	128	SVGA_REG_ENABLE_HIDE);
	129	+
132	130	vmw_write(dev_priv, SVGA_REG_TRACES, 0);
133	131
134	132	min = 4;
@@ -139,19 +137,19 @@ int vmw_fifo_init(struct vmw_private dev_priv, struct vmw_fifo_state fifo) · 4 unmodified lines
139	137	if (min < PAGE_SIZE)
140	138	min = PAGE_SIZE;
141	139
142		− vmw_mmio_write(min, fifo_mem + SVGA_FIFO_MIN);
143		− vmw_mmio_write(dev_priv->mmio_size, fifo_mem + SVGA_FIFO_MAX);
	140	+ vmw_fifo_mem_write(dev_priv, SVGA_FIFO_MIN, min);
	141	+ vmw_fifo_mem_write(dev_priv, SVGA_FIFO_MAX, dev_priv->fifo_mem_size);
144	142	wmb();
145		− vmw_mmio_write(min, fifo_mem + SVGA_FIFO_NEXT_CMD);
146		− vmw_mmio_write(min, fifo_mem + SVGA_FIFO_STOP);
147		− vmw_mmio_write(0, fifo_mem + SVGA_FIFO_BUSY);
	143	+ vmw_fifo_mem_write(dev_priv, SVGA_FIFO_NEXT_CMD, min);
	144	+ vmw_fifo_mem_write(dev_priv, SVGA_FIFO_STOP, min);
	145	+ vmw_fifo_mem_write(dev_priv, SVGA_FIFO_BUSY, 0);
148	146	mb();
149	147
150	148	vmw_write(dev_priv, SVGA_REG_CONFIG_DONE, 1);
151	149
152		− max = vmw_mmio_read(fifo_mem + SVGA_FIFO_MAX);
153		− min = vmw_mmio_read(fifo_mem + SVGA_FIFO_MIN);
154		− fifo->capabilities = vmw_mmio_read(fifo_mem + SVGA_FIFO_CAPABILITIES);
	150	+ max = vmw_fifo_mem_read(dev_priv, SVGA_FIFO_MAX);
	151	+ min = vmw_fifo_mem_read(dev_priv, SVGA_FIFO_MIN);
	152	+ fifo->capabilities = vmw_fifo_mem_read(dev_priv, SVGA_FIFO_CAPABILITIES);
155	153
156	154	DRM_INFO("Fifo max 0x%08x min 0x%08x cap 0x%08x\n",
157	155	(unsigned int) max,
@@ -159,15 +157,14 @@ int vmw_fifo_init(struct vmw_private dev_priv, struct vmw_fifo_state fifo) · 1 unmodified line
159	157	(unsigned int) fifo->capabilities);
160	158
161	159	atomic_set(&dev_priv->marker_seq, dev_priv->last_read_seqno);
162		− vmw_mmio_write(dev_priv->last_read_seqno, fifo_mem + SVGA_FIFO_FENCE);
163		− vmw_marker_queue_init(&fifo->marker_queue);
	160	+ vmw_fifo_mem_write(dev_priv, SVGA_FIFO_FENCE, dev_priv->last_read_seqno);
164	161
165	162	return 0;
166	163	}
167	164
168	165	void vmw_fifo_ping_host(struct vmw_private *dev_priv, uint32_t reason)
169	166	{
170		− u32 *fifo_mem = dev_priv->mmio_virt;
	167	+ u32 *fifo_mem = dev_priv->fifo_mem;
171	168
172	169	if (cmpxchg(fifo_mem + SVGA_FIFO_BUSY, 0, 1) == 0)
173	170	vmw_write(dev_priv, SVGA_REG_SYNC, reason);
@@ -175,13 +172,11 @@ void vmw_fifo_ping_host(struct vmw_private *dev_priv, uint32_t reason) · 1 unmodified line
175	172
176	173	void vmw_fifo_release(struct vmw_private dev_priv, struct vmw_fifo_state fifo)
177	174	{
178		− u32 *fifo_mem = dev_priv->mmio_virt;
179		−
180	175	vmw_write(dev_priv, SVGA_REG_SYNC, SVGA_SYNC_GENERIC);
181	176	while (vmw_read(dev_priv, SVGA_REG_BUSY) != 0)
182	177	;
183	178
184		− dev_priv->last_read_seqno = vmw_mmio_read(fifo_mem + SVGA_FIFO_FENCE);
	179	+ dev_priv->last_read_seqno = vmw_fifo_mem_read(dev_priv, SVGA_FIFO_FENCE);
185	180
186	181	vmw_write(dev_priv, SVGA_REG_CONFIG_DONE,
187	182	dev_priv->config_done_state);
@@ -190,8 +185,6 @@ void vmw_fifo_release(struct vmw_private dev_priv, struct vmw_fifo_state fifo) · 2 unmodified lines
190	185	vmw_write(dev_priv, SVGA_REG_TRACES,
191	186	dev_priv->traces_state);
192	187
193		− vmw_marker_queue_takedown(&fifo->marker_queue);
194		−
195	188	if (likely(fifo->static_buffer != NULL)) {
196	189	vfree(fifo->static_buffer);
197	190	fifo->static_buffer = NULL;
@@ -205,11 +198,10 @@ void vmw_fifo_release(struct vmw_private dev_priv, struct vmw_fifo_state fifo) · 7 unmodified lines
205	198
206	199	static bool vmw_fifo_is_full(struct vmw_private *dev_priv, uint32_t bytes)
207	200	{
208		− u32 *fifo_mem = dev_priv->mmio_virt;
209		− uint32_t max = vmw_mmio_read(fifo_mem + SVGA_FIFO_MAX);
210		− uint32_t next_cmd = vmw_mmio_read(fifo_mem + SVGA_FIFO_NEXT_CMD);
211		− uint32_t min = vmw_mmio_read(fifo_mem + SVGA_FIFO_MIN);
212		− uint32_t stop = vmw_mmio_read(fifo_mem + SVGA_FIFO_STOP);
	201	+ uint32_t max = vmw_fifo_mem_read(dev_priv, SVGA_FIFO_MAX);
	202	+ uint32_t next_cmd = vmw_fifo_mem_read(dev_priv, SVGA_FIFO_NEXT_CMD);
	203	+ uint32_t min = vmw_fifo_mem_read(dev_priv, SVGA_FIFO_MIN);
	204	+ uint32_t stop = vmw_fifo_mem_read(dev_priv, SVGA_FIFO_STOP);
213	205
214	206	return ((max - next_cmd) + (stop - min) <= bytes);
215	207	}
@@ -298,7 +290,7 @@ static void vmw_local_fifo_reserve(struct vmw_private dev_priv, · 82 unmodified lines
298	290	uint32_t bytes)
299	291	{
300	292	struct vmw_fifo_state *fifo_state = &dev_priv->fifo;
301		− u32 *fifo_mem = dev_priv->mmio_virt;
	293	+ u32 *fifo_mem = dev_priv->fifo_mem;
302	294	uint32_t max;
303	295	uint32_t min;
304	296	uint32_t next_cmd;
@@ -306,9 +298,9 @@ static void vmw_local_fifo_reserve(struct vmw_private dev_priv, · 1 unmodified line
306	298	int ret;
307	299
308	300	mutex_lock(&fifo_state->fifo_mutex);
309		− max = vmw_mmio_read(fifo_mem + SVGA_FIFO_MAX);
310		− min = vmw_mmio_read(fifo_mem + SVGA_FIFO_MIN);
311		− next_cmd = vmw_mmio_read(fifo_mem + SVGA_FIFO_NEXT_CMD);
	301	+ max = vmw_fifo_mem_read(dev_priv, SVGA_FIFO_MAX);
	302	+ min = vmw_fifo_mem_read(dev_priv, SVGA_FIFO_MIN);
	303	+ next_cmd = vmw_fifo_mem_read(dev_priv, SVGA_FIFO_NEXT_CMD);
312	304
313	305	if (unlikely(bytes >= (max - min)))
314	306	goto out_err;
@@ -319,7 +311,7 @@ static void vmw_local_fifo_reserve(struct vmw_private dev_priv, · 4 unmodified lines
319	311	fifo_state->reserved_size = bytes;
320	312
321	313	while (1) {
322		− uint32_t stop = vmw_mmio_read(fifo_mem + SVGA_FIFO_STOP);
	314	+ uint32_t stop = vmw_fifo_mem_read(dev_priv, SVGA_FIFO_STOP);
323	315	bool need_bounce = false;
324	316	bool reserve_in_place = false;
325	317
@@ -353,8 +345,9 @@ static void vmw_local_fifo_reserve(struct vmw_private dev_priv, · 27 unmodified lines
353	345	fifo_state->using_bounce_buffer = false;
354	346
355	347	if (reserveable)
356		− vmw_mmio_write(bytes, fifo_mem +
357		− SVGA_FIFO_RESERVED);
	348	+ vmw_fifo_mem_write(dev_priv,
	349	+ SVGA_FIFO_RESERVED,
	350	+ bytes);
358	351	return (void __force *) (fifo_mem +
359	352	(next_cmd >> 2));
360	353	} else {
@@ -381,7 +374,7 @@ out_err: · 20 unmodified lines
381	374	return NULL;
382	375	}
383	376
384		−void vmw_fifo_reserve_dx(struct vmw_private dev_priv, uint32_t bytes,
	377	+void vmw_cmd_ctx_reserve(struct vmw_private dev_priv, uint32_t bytes,
385	378	int ctx_id)
386	379	{
387	380	void *ret;
@@ -402,10 +395,11 @@ void vmw_fifo_reserve_dx(struct vmw_private dev_priv, uint32_t bytes, · 14 unmodified lines
402	395	}
403	396
404	397	static void vmw_fifo_res_copy(struct vmw_fifo_state *fifo_state,
405		− u32 *fifo_mem,
	398	+ struct vmw_private *vmw,
406	399	uint32_t next_cmd,
407	400	uint32_t max, uint32_t min, uint32_t bytes)
408	401	{
	402	+ u32 *fifo_mem = vmw->fifo_mem;
409	403	uint32_t chunk_size = max - next_cmd;
410	404	uint32_t rest;
411	405	uint32_t *buffer = (fifo_state->dynamic_buffer != NULL) ?
@@ -414,7 +408,7 @@ static void vmw_fifo_res_copy(struct vmw_fifo_state *fifo_state, · 2 unmodified lines
414	408	if (bytes < chunk_size)
415	409	chunk_size = bytes;
416	410
417		− vmw_mmio_write(bytes, fifo_mem + SVGA_FIFO_RESERVED);
	411	+ vmw_fifo_mem_write(vmw, SVGA_FIFO_RESERVED, bytes);
418	412	mb();
419	413	memcpy(fifo_mem + (next_cmd >> 2), buffer, chunk_size);
420	414	rest = bytes - chunk_size;
@@ -423,7 +417,7 @@ static void vmw_fifo_res_copy(struct vmw_fifo_state *fifo_state, · 2 unmodified lines
423	417	}
424	418
425	419	static void vmw_fifo_slow_copy(struct vmw_fifo_state *fifo_state,
426		− u32 *fifo_mem,
	420	+ struct vmw_private *vmw,
427	421	uint32_t next_cmd,
428	422	uint32_t max, uint32_t min, uint32_t bytes)
429	423	{
@@ -431,12 +425,12 @@ static void vmw_fifo_slow_copy(struct vmw_fifo_state *fifo_state, · 1 unmodified line
431	425	fifo_state->dynamic_buffer : fifo_state->static_buffer;
432	426
433	427	while (bytes > 0) {
434		− vmw_mmio_write(*buffer++, fifo_mem + (next_cmd >> 2));
	428	+ vmw_fifo_mem_write(vmw, (next_cmd >> 2), *buffer++);
435	429	next_cmd += sizeof(uint32_t);
436	430	if (unlikely(next_cmd == max))
437	431	next_cmd = min;
438	432	mb();
439		− vmw_mmio_write(next_cmd, fifo_mem + SVGA_FIFO_NEXT_CMD);
	433	+ vmw_fifo_mem_write(vmw, SVGA_FIFO_NEXT_CMD, next_cmd);
440	434	mb();
441	435	bytes -= sizeof(uint32_t);
442	436	}
@@ -445,10 +439,9 @@ static void vmw_fifo_slow_copy(struct vmw_fifo_state *fifo_state, · 2 unmodified lines
445	439	static void vmw_local_fifo_commit(struct vmw_private *dev_priv, uint32_t bytes)
446	440	{
447	441	struct vmw_fifo_state *fifo_state = &dev_priv->fifo;
448		− u32 *fifo_mem = dev_priv->mmio_virt;
449		− uint32_t next_cmd = vmw_mmio_read(fifo_mem + SVGA_FIFO_NEXT_CMD);
450		− uint32_t max = vmw_mmio_read(fifo_mem + SVGA_FIFO_MAX);
451		− uint32_t min = vmw_mmio_read(fifo_mem + SVGA_FIFO_MIN);
	442	+ uint32_t next_cmd = vmw_fifo_mem_read(dev_priv, SVGA_FIFO_NEXT_CMD);
	443	+ uint32_t max = vmw_fifo_mem_read(dev_priv, SVGA_FIFO_MAX);
	444	+ uint32_t min = vmw_fifo_mem_read(dev_priv, SVGA_FIFO_MIN);
452	445	bool reserveable = fifo_state->capabilities & SVGA_FIFO_CAP_RESERVE;
453	446
454	447	if (fifo_state->dx)
@@ -462,10 +455,10 @@ static void vmw_local_fifo_commit(struct vmw_private *dev_priv, uint32_t bytes) · 7 unmodified lines
462	455
463	456	if (fifo_state->using_bounce_buffer) {
464	457	if (reserveable)
465		− vmw_fifo_res_copy(fifo_state, fifo_mem,
	458	+ vmw_fifo_res_copy(fifo_state, dev_priv,
466	459	next_cmd, max, min, bytes);
467	460	else
468		− vmw_fifo_slow_copy(fifo_state, fifo_mem,
	461	+ vmw_fifo_slow_copy(fifo_state, dev_priv,
469	462	next_cmd, max, min, bytes);
470	463
471	464	if (fifo_state->dynamic_buffer) {
@@ -481,18 +474,18 @@ static void vmw_local_fifo_commit(struct vmw_private *dev_priv, uint32_t bytes) · 9 unmodified lines
481	474	if (next_cmd >= max)
482	475	next_cmd -= max - min;
483	476	mb();
484		− vmw_mmio_write(next_cmd, fifo_mem + SVGA_FIFO_NEXT_CMD);
	477	+ vmw_fifo_mem_write(dev_priv, SVGA_FIFO_NEXT_CMD, next_cmd);
485	478	}
486	479
487	480	if (reserveable)
488		− vmw_mmio_write(0, fifo_mem + SVGA_FIFO_RESERVED);
	481	+ vmw_fifo_mem_write(dev_priv, SVGA_FIFO_RESERVED, 0);
489	482	mb();
490	483	up_write(&fifo_state->rwsem);
491	484	vmw_fifo_ping_host(dev_priv, SVGA_SYNC_GENERIC);
492	485	mutex_unlock(&fifo_state->fifo_mutex);
493	486	}
494	487
495		−void vmw_fifo_commit(struct vmw_private *dev_priv, uint32_t bytes)
	488	+void vmw_cmd_commit(struct vmw_private *dev_priv, uint32_t bytes)
496	489	{
497	490	if (dev_priv->cman)
498	491	vmw_cmdbuf_commit(dev_priv->cman, bytes, NULL, false);
@@ -507,7 +500,7 @@ void vmw_fifo_commit(struct vmw_private *dev_priv, uint32_t bytes) · 8 unmodified lines
507	500	* @dev_priv: Pointer to device private structure.
508	501	* @bytes: Number of bytes to commit.
509	502	*/
510		−void vmw_fifo_commit_flush(struct vmw_private *dev_priv, uint32_t bytes)
	503	+void vmw_cmd_commit_flush(struct vmw_private *dev_priv, uint32_t bytes)
511	504	{
512	505	if (dev_priv->cman)
513	506	vmw_cmdbuf_commit(dev_priv->cman, bytes, NULL, true);
@@ -522,7 +515,7 @@ void vmw_fifo_commit_flush(struct vmw_private *dev_priv, uint32_t bytes) · 8 unmodified lines
522	515	* @dev_priv: Pointer to device private structure.
523	516	* @interruptible: Whether to wait interruptible if function needs to sleep.
524	517	*/
525		−int vmw_fifo_flush(struct vmw_private *dev_priv, bool interruptible)
	518	+int vmw_cmd_flush(struct vmw_private *dev_priv, bool interruptible)
526	519	{
527	520	might_sleep();
528	521
@@ -532,7 +525,7 @@ int vmw_fifo_flush(struct vmw_private *dev_priv, bool interruptible) · 3 unmodified lines
532	525	return 0;
533	526	}
534	527
535		−int vmw_fifo_send_fence(struct vmw_private dev_priv, uint32_t seqno)
	528	+int vmw_cmd_send_fence(struct vmw_private dev_priv, uint32_t seqno)
536	529	{
537	530	struct vmw_fifo_state *fifo_state = &dev_priv->fifo;
538	531	struct svga_fifo_cmd_fence *cmd_fence;
@@ -540,7 +533,7 @@ int vmw_fifo_send_fence(struct vmw_private dev_priv, uint32_t seqno) · 1 unmodified line
540	533	int ret = 0;
541	534	uint32_t bytes = sizeof(u32) + sizeof(*cmd_fence);
542	535
543		− fm = VMW_FIFO_RESERVE(dev_priv, bytes);
	536	+ fm = VMW_CMD_RESERVE(dev_priv, bytes);
544	537	if (unlikely(fm == NULL)) {
545	538	*seqno = atomic_read(&dev_priv->marker_seq);
546	539	ret = -ENOMEM;
@@ -560,15 +553,14 @@ int vmw_fifo_send_fence(struct vmw_private dev_priv, uint32_t seqno) · 13 unmodified lines
560	553	* waiting code in vmwgfx_irq.c will emulate this.
561	554	*/
562	555
563		− vmw_fifo_commit(dev_priv, 0);
	556	+ vmw_cmd_commit(dev_priv, 0);
564	557	return 0;
565	558	}
566	559
567	560	*fm++ = SVGA_CMD_FENCE;
568	561	cmd_fence = (struct svga_fifo_cmd_fence *) fm;
569	562	cmd_fence->fence = *seqno;
570		− vmw_fifo_commit_flush(dev_priv, bytes);
571		− (void) vmw_marker_push(&fifo_state->marker_queue, *seqno);
	563	+ vmw_cmd_commit_flush(dev_priv, bytes);
572	564	vmw_update_seqno(dev_priv, fifo_state);
573	565
574	566	out_err:
@@ -599,7 +591,7 @@ static int vmw_fifo_emit_dummy_legacy_query(struct vmw_private *dev_priv, · 24 unmodified lines
599	591	SVGA3dCmdWaitForQuery body;
600	592	} *cmd;
601	593
602		− cmd = VMW_FIFO_RESERVE(dev_priv, sizeof(*cmd));
	594	+ cmd = VMW_CMD_RESERVE(dev_priv, sizeof(*cmd));
603	595	if (unlikely(cmd == NULL))
604	596	return -ENOMEM;
605	597
@@ -616,7 +608,7 @@ static int vmw_fifo_emit_dummy_legacy_query(struct vmw_private *dev_priv, · 10 unmodified lines
616	608	cmd->body.guestResult.offset = 0;
617	609	}
618	610
619		− vmw_fifo_commit(dev_priv, sizeof(*cmd));
	611	+ vmw_cmd_commit(dev_priv, sizeof(*cmd));
620	612
621	613	return 0;
622	614	}
@@ -645,7 +637,7 @@ static int vmw_fifo_emit_dummy_gb_query(struct vmw_private *dev_priv, · 22 unmodified lines
645	637	SVGA3dCmdWaitForGBQuery body;
646	638	} *cmd;
647	639
648		− cmd = VMW_FIFO_RESERVE(dev_priv, sizeof(*cmd));
	640	+ cmd = VMW_CMD_RESERVE(dev_priv, sizeof(*cmd));
649	641	if (unlikely(cmd == NULL))
650	642	return -ENOMEM;
651	643
@@ -657,7 +649,7 @@ static int vmw_fifo_emit_dummy_gb_query(struct vmw_private *dev_priv, · 5 unmodified lines
657	649	cmd->body.mobid = bo->mem.start;
658	650	cmd->body.offset = 0;
659	651
660		− vmw_fifo_commit(dev_priv, sizeof(*cmd));
	652	+ vmw_cmd_commit(dev_priv, sizeof(*cmd));
661	653
662	654	return 0;
663	655	}
@@ -681,7 +673,7 @@ static int vmw_fifo_emit_dummy_gb_query(struct vmw_private *dev_priv, · 17 unmodified lines
681	673	*
682	674	* Returns -ENOMEM on failure to reserve fifo space.
683	675	*/
684		−int vmw_fifo_emit_dummy_query(struct vmw_private *dev_priv,
	676	+int vmw_cmd_emit_dummy_query(struct vmw_private *dev_priv,
685	677	uint32_t cid)
686	678	{
687	679	if (dev_priv->has_mob)

drivers/gpu/drm/vmwgfx/vmwgfx_cmdbuf.c+9−13

@@ -610,7 +610,7 @@ static void vmw_cmdbuf_work_func(struct work_struct *work) · 609 unmodified lines
610	610
611	611	/* Send a new fence in case one was removed */
612	612	if (send_fence) {
613		− vmw_fifo_send_fence(man->dev_priv, &dummy);
	613	+ vmw_cmd_send_fence(man->dev_priv, &dummy);
614	614	wake_up_all(&man->idle_queue);
615	615	}
616	616
@@ -1208,18 +1208,14 @@ static int vmw_cmdbuf_startstop(struct vmw_cmdbuf_man *man, u32 context, · 591 unmodified lines
1208	1208	*
1209	1209	* @man: The command buffer manager.
1210	1210	* @size: The size of the main space pool.
1211		− * @default_size: The default size of the command buffer for small kernel
1212		− * submissions.
1213	1211	*
1214		− * Set the size and allocate the main command buffer space pool,
1215		− * as well as the default size of the command buffer for
1216		− * small kernel submissions. If successful, this enables large command
1217		− * submissions. Note that this function requires that rudimentary command
	1212	+ * Set the size and allocate the main command buffer space pool.
	1213	+ * If successful, this enables large command submissions.
	1214	+ * Note that this function requires that rudimentary command
1218	1215	* submission is already available and that the MOB memory manager is alive.
1219	1216	* Returns 0 on success. Negative error code on failure.
1220	1217	*/
1221		−int vmw_cmdbuf_set_pool_size(struct vmw_cmdbuf_man *man,
1222		− size_t size, size_t default_size)
	1218	+int vmw_cmdbuf_set_pool_size(struct vmw_cmdbuf_man *man, size_t size)
1223	1219	{
1224	1220	struct vmw_private *dev_priv = man->dev_priv;
1225	1221	bool dummy;
@@ -1230,7 +1226,7 @@ int vmw_cmdbuf_set_pool_size(struct vmw_cmdbuf_man *man, · 4 unmodified lines
1230	1226
1231	1227	/* First, try to allocate a huge chunk of DMA memory */
1232	1228	size = PAGE_ALIGN(size);
1233		− man->map = dma_alloc_coherent(&dev_priv->dev->pdev->dev, size,
	1229	+ man->map = dma_alloc_coherent(dev_priv->drm.dev, size,
1234	1230	&man->handle, GFP_KERNEL);
1235	1231	if (man->map) {
1236	1232	man->using_mob = false;
@@ -1313,7 +1309,7 @@ struct vmw_cmdbuf_man vmw_cmdbuf_man_create(struct vmw_private dev_priv) · 76 unmodified lines
1313	1309	man->num_contexts = (dev_priv->capabilities & SVGA_CAP_HP_CMD_QUEUE) ?
1314	1310	2 : 1;
1315	1311	man->headers = dma_pool_create("vmwgfx cmdbuf",
1316		− &dev_priv->dev->pdev->dev,
	1312	+ dev_priv->drm.dev,
1317	1313	sizeof(SVGACBHeader),
1318	1314	64, PAGE_SIZE);
1319	1315	if (!man->headers) {
@@ -1322,7 +1318,7 @@ struct vmw_cmdbuf_man vmw_cmdbuf_man_create(struct vmw_private dev_priv) · 2 unmodified lines
1322	1318	}
1323	1319
1324	1320	man->dheaders = dma_pool_create("vmwgfx inline cmdbuf",
1325		− &dev_priv->dev->pdev->dev,
	1321	+ dev_priv->drm.dev,
1326	1322	sizeof(struct vmw_cmdbuf_dheader),
1327	1323	64, PAGE_SIZE);
1328	1324	if (!man->dheaders) {
@@ -1387,7 +1383,7 @@ void vmw_cmdbuf_remove_pool(struct vmw_cmdbuf_man *man) · 58 unmodified lines
1387	1383	ttm_bo_put(man->cmd_space);
1388	1384	man->cmd_space = NULL;
1389	1385	} else {
1390		− dma_free_coherent(&man->dev_priv->dev->pdev->dev,
	1386	+ dma_free_coherent(man->dev_priv->drm.dev,
1391	1387	man->size, man->map, man->handle);
1392	1388	}
1393	1389	}

drivers/gpu/drm/vmwgfx/vmwgfx_context.c+20−20

@@ -163,7 +163,7 @@ static void vmw_hw_context_destroy(struct vmw_resource *res) · 162 unmodified lines
163	163	}
164	164
165	165	vmw_execbuf_release_pinned_bo(dev_priv);
166		− cmd = VMW_FIFO_RESERVE(dev_priv, sizeof(*cmd));
	166	+ cmd = VMW_CMD_RESERVE(dev_priv, sizeof(*cmd));
167	167	if (unlikely(cmd == NULL))
168	168	return;
169	169
@@ -171,7 +171,7 @@ static void vmw_hw_context_destroy(struct vmw_resource *res) · 1 unmodified line
171	171	cmd->header.size = sizeof(cmd->body);
172	172	cmd->body.cid = res->id;
173	173
174		− vmw_fifo_commit(dev_priv, sizeof(*cmd));
	174	+ vmw_cmd_commit(dev_priv, sizeof(*cmd));
175	175	vmw_fifo_resource_dec(dev_priv);
176	176	}
177	177
@@ -265,7 +265,7 @@ static int vmw_context_init(struct vmw_private *dev_priv, · 87 unmodified lines
265	265	return -ENOMEM;
266	266	}
267	267
268		− cmd = VMW_FIFO_RESERVE(dev_priv, sizeof(*cmd));
	268	+ cmd = VMW_CMD_RESERVE(dev_priv, sizeof(*cmd));
269	269	if (unlikely(cmd == NULL)) {
270	270	vmw_resource_unreference(&res);
271	271	return -ENOMEM;
@@ -275,7 +275,7 @@ static int vmw_context_init(struct vmw_private *dev_priv, · 3 unmodified lines
275	275	cmd->header.size = sizeof(cmd->body);
276	276	cmd->body.cid = res->id;
277	277
278		− vmw_fifo_commit(dev_priv, sizeof(*cmd));
	278	+ vmw_cmd_commit(dev_priv, sizeof(*cmd));
279	279	vmw_fifo_resource_inc(dev_priv);
280	280	res->hw_destroy = vmw_hw_context_destroy;
281	281	return 0;
@@ -316,7 +316,7 @@ static int vmw_gb_context_create(struct vmw_resource *res) · 34 unmodified lines
316	316	goto out_no_fifo;
317	317	}
318	318
319		− cmd = VMW_FIFO_RESERVE(dev_priv, sizeof(*cmd));
	319	+ cmd = VMW_CMD_RESERVE(dev_priv, sizeof(*cmd));
320	320	if (unlikely(cmd == NULL)) {
321	321	ret = -ENOMEM;
322	322	goto out_no_fifo;
@@ -325,7 +325,7 @@ static int vmw_gb_context_create(struct vmw_resource *res) · 2 unmodified lines
325	325	cmd->header.id = SVGA_3D_CMD_DEFINE_GB_CONTEXT;
326	326	cmd->header.size = sizeof(cmd->body);
327	327	cmd->body.cid = res->id;
328		− vmw_fifo_commit(dev_priv, sizeof(*cmd));
	328	+ vmw_cmd_commit(dev_priv, sizeof(*cmd));
329	329	vmw_fifo_resource_inc(dev_priv);
330	330
331	331	return 0;
@@ -348,7 +348,7 @@ static int vmw_gb_context_bind(struct vmw_resource *res, · 16 unmodified lines
348	348
349	349	BUG_ON(bo->mem.mem_type != VMW_PL_MOB);
350	350
351		− cmd = VMW_FIFO_RESERVE(dev_priv, sizeof(*cmd));
	351	+ cmd = VMW_CMD_RESERVE(dev_priv, sizeof(*cmd));
352	352	if (unlikely(cmd == NULL))
353	353	return -ENOMEM;
354	354
@@ -358,7 +358,7 @@ static int vmw_gb_context_bind(struct vmw_resource *res, · 3 unmodified lines
358	358	cmd->body.mobid = bo->mem.start;
359	359	cmd->body.validContents = res->backup_dirty;
360	360	res->backup_dirty = false;
361		− vmw_fifo_commit(dev_priv, sizeof(*cmd));
	361	+ vmw_cmd_commit(dev_priv, sizeof(*cmd));
362	362
363	363	return 0;
364	364	}
@@ -392,7 +392,7 @@ static int vmw_gb_context_unbind(struct vmw_resource *res, · 27 unmodified lines
392	392
393	393	submit_size = sizeof(cmd2) + (readback ? sizeof(cmd1) : 0);
394	394
395		− cmd = VMW_FIFO_RESERVE(dev_priv, submit_size);
	395	+ cmd = VMW_CMD_RESERVE(dev_priv, submit_size);
396	396	if (unlikely(cmd == NULL)) {
397	397	mutex_unlock(&dev_priv->binding_mutex);
398	398	return -ENOMEM;
@@ -411,7 +411,7 @@ static int vmw_gb_context_unbind(struct vmw_resource *res, · 12 unmodified lines
411	411	cmd2->body.cid = res->id;
412	412	cmd2->body.mobid = SVGA3D_INVALID_ID;
413	413
414		− vmw_fifo_commit(dev_priv, submit_size);
	414	+ vmw_cmd_commit(dev_priv, submit_size);
415	415	mutex_unlock(&dev_priv->binding_mutex);
416	416
417	417	/*
@@ -440,14 +440,14 @@ static int vmw_gb_context_destroy(struct vmw_resource *res) · 22 unmodified lines
440	440	if (likely(res->id == -1))
441	441	return 0;
442	442
443		− cmd = VMW_FIFO_RESERVE(dev_priv, sizeof(*cmd));
	443	+ cmd = VMW_CMD_RESERVE(dev_priv, sizeof(*cmd));
444	444	if (unlikely(cmd == NULL))
445	445	return -ENOMEM;
446	446
447	447	cmd->header.id = SVGA_3D_CMD_DESTROY_GB_CONTEXT;
448	448	cmd->header.size = sizeof(cmd->body);
449	449	cmd->body.cid = res->id;
450		− vmw_fifo_commit(dev_priv, sizeof(*cmd));
	450	+ vmw_cmd_commit(dev_priv, sizeof(*cmd));
451	451	if (dev_priv->query_cid == res->id)
452	452	dev_priv->query_cid_valid = false;
453	453	vmw_resource_release_id(res);
@@ -483,7 +483,7 @@ static int vmw_dx_context_create(struct vmw_resource *res) · 29 unmodified lines
483	483	goto out_no_fifo;
484	484	}
485	485
486		− cmd = VMW_FIFO_RESERVE(dev_priv, sizeof(*cmd));
	486	+ cmd = VMW_CMD_RESERVE(dev_priv, sizeof(*cmd));
487	487	if (unlikely(cmd == NULL)) {
488	488	ret = -ENOMEM;
489	489	goto out_no_fifo;
@@ -492,7 +492,7 @@ static int vmw_dx_context_create(struct vmw_resource *res) · 2 unmodified lines
492	492	cmd->header.id = SVGA_3D_CMD_DX_DEFINE_CONTEXT;
493	493	cmd->header.size = sizeof(cmd->body);
494	494	cmd->body.cid = res->id;
495		− vmw_fifo_commit(dev_priv, sizeof(*cmd));
	495	+ vmw_cmd_commit(dev_priv, sizeof(*cmd));
496	496	vmw_fifo_resource_inc(dev_priv);
497	497
498	498	return 0;
@@ -515,7 +515,7 @@ static int vmw_dx_context_bind(struct vmw_resource *res, · 16 unmodified lines
515	515
516	516	BUG_ON(bo->mem.mem_type != VMW_PL_MOB);
517	517
518		− cmd = VMW_FIFO_RESERVE(dev_priv, sizeof(*cmd));
	518	+ cmd = VMW_CMD_RESERVE(dev_priv, sizeof(*cmd));
519	519	if (unlikely(cmd == NULL))
520	520	return -ENOMEM;
521	521
@@ -525,7 +525,7 @@ static int vmw_dx_context_bind(struct vmw_resource *res, · 3 unmodified lines
525	525	cmd->body.mobid = bo->mem.start;
526	526	cmd->body.validContents = res->backup_dirty;
527	527	res->backup_dirty = false;
528		− vmw_fifo_commit(dev_priv, sizeof(*cmd));
	528	+ vmw_cmd_commit(dev_priv, sizeof(*cmd));
529	529
530	530
531	531	return 0;
@@ -608,7 +608,7 @@ static int vmw_dx_context_unbind(struct vmw_resource *res, · 76 unmodified lines
608	608
609	609	submit_size = sizeof(cmd2) + (readback ? sizeof(cmd1) : 0);
610	610
611		− cmd = VMW_FIFO_RESERVE(dev_priv, submit_size);
	611	+ cmd = VMW_CMD_RESERVE(dev_priv, submit_size);
612	612	if (unlikely(cmd == NULL)) {
613	613	mutex_unlock(&dev_priv->binding_mutex);
614	614	return -ENOMEM;
@@ -627,7 +627,7 @@ static int vmw_dx_context_unbind(struct vmw_resource *res, · 12 unmodified lines
627	627	cmd2->body.cid = res->id;
628	628	cmd2->body.mobid = SVGA3D_INVALID_ID;
629	629
630		− vmw_fifo_commit(dev_priv, submit_size);
	630	+ vmw_cmd_commit(dev_priv, submit_size);
631	631	mutex_unlock(&dev_priv->binding_mutex);
632	632
633	633	/*
@@ -656,14 +656,14 @@ static int vmw_dx_context_destroy(struct vmw_resource *res) · 22 unmodified lines
656	656	if (likely(res->id == -1))
657	657	return 0;
658	658
659		− cmd = VMW_FIFO_RESERVE(dev_priv, sizeof(*cmd));
	659	+ cmd = VMW_CMD_RESERVE(dev_priv, sizeof(*cmd));
660	660	if (unlikely(cmd == NULL))
661	661	return -ENOMEM;
662	662
663	663	cmd->header.id = SVGA_3D_CMD_DX_DESTROY_CONTEXT;
664	664	cmd->header.size = sizeof(cmd->body);
665	665	cmd->body.cid = res->id;
666		− vmw_fifo_commit(dev_priv, sizeof(*cmd));
	666	+ vmw_cmd_commit(dev_priv, sizeof(*cmd));
667	667	if (dev_priv->query_cid == res->id)
668	668	dev_priv->query_cid_valid = false;
669	669	vmw_resource_release_id(res);

drivers/gpu/drm/vmwgfx/vmwgfx_cotable.c+6−6

@@ -175,7 +175,7 @@ static int vmw_cotable_unscrub(struct vmw_resource *res) · 174 unmodified lines
175	175	WARN_ON_ONCE(bo->mem.mem_type != VMW_PL_MOB);
176	176	dma_resv_assert_held(bo->base.resv);
177	177
178		− cmd = VMW_FIFO_RESERVE(dev_priv, sizeof(*cmd));
	178	+ cmd = VMW_CMD_RESERVE(dev_priv, sizeof(*cmd));
179	179	if (!cmd)
180	180	return -ENOMEM;
181	181
@@ -188,7 +188,7 @@ static int vmw_cotable_unscrub(struct vmw_resource *res) · 6 unmodified lines
188	188	cmd->body.mobid = bo->mem.start;
189	189	cmd->body.validSizeInBytes = vcotbl->size_read_back;
190	190
191		− vmw_fifo_commit_flush(dev_priv, sizeof(*cmd));
	191	+ vmw_cmd_commit_flush(dev_priv, sizeof(*cmd));
192	192	vcotbl->scrubbed = false;
193	193
194	194	return 0;
@@ -263,7 +263,7 @@ int vmw_cotable_scrub(struct vmw_resource *res, bool readback) · 68 unmodified lines
263	263	if (readback)
264	264	submit_size += sizeof(*cmd0);
265	265
266		− cmd1 = VMW_FIFO_RESERVE(dev_priv, submit_size);
	266	+ cmd1 = VMW_CMD_RESERVE(dev_priv, submit_size);
267	267	if (!cmd1)
268	268	return -ENOMEM;
269	269
@@ -283,7 +283,7 @@ int vmw_cotable_scrub(struct vmw_resource *res, bool readback) · 13 unmodified lines
283	283	cmd1->body.type = vcotbl->type;
284	284	cmd1->body.mobid = SVGA3D_INVALID_ID;
285	285	cmd1->body.validSizeInBytes = 0;
286		− vmw_fifo_commit_flush(dev_priv, submit_size);
	286	+ vmw_cmd_commit_flush(dev_priv, submit_size);
287	287	vcotbl->scrubbed = true;
288	288
289	289	/* Trigger a create() on next validate. */
@@ -349,7 +349,7 @@ static int vmw_cotable_readback(struct vmw_resource *res) · 59 unmodified lines
349	349	struct vmw_fence_obj *fence;
350	350
351	351	if (!vcotbl->scrubbed) {
352		− cmd = VMW_FIFO_RESERVE(dev_priv, sizeof(*cmd));
	352	+ cmd = VMW_CMD_RESERVE(dev_priv, sizeof(*cmd));
353	353	if (!cmd)
354	354	return -ENOMEM;
355	355
@@ -358,7 +358,7 @@ static int vmw_cotable_readback(struct vmw_resource *res) · 2 unmodified lines
358	358	cmd->body.cid = vcotbl->ctx->id;
359	359	cmd->body.type = vcotbl->type;
360	360	vcotbl->size_read_back = res->backup_size;
361		− vmw_fifo_commit(dev_priv, sizeof(*cmd));
	361	+ vmw_cmd_commit(dev_priv, sizeof(*cmd));
362	362	}
363	363
364	364	(void) vmw_execbuf_fence_commands(NULL, dev_priv, &fence, NULL);

drivers/gpu/drm/vmwgfx/vmwgfx_drv.c+113−122

@@ -32,6 +32,7 @@ · 31 unmodified lines
32	32	#include <linux/mem_encrypt.h>
33	33
34	34	#include <drm/drm_drv.h>
	35	+#include <drm/drm_fb_helper.h>
35	36	#include <drm/drm_ioctl.h>
36	37	#include <drm/drm_sysfs.h>
37	38	#include <drm/ttm/ttm_bo_driver.h>
@@ -42,8 +43,6 @@ · 4 unmodified lines
42	43	#include "vmwgfx_drv.h"
43	44
44	45	#define VMWGFX_DRIVER_DESC "Linux drm driver for VMware graphics devices"
45		−#define VMWGFX_CHIP_SVGAII 0
46		−#define VMW_FB_RESERVATION 0
47	46
48	47	#define VMW_MIN_INITIAL_WIDTH 800
49	48	#define VMW_MIN_INITIAL_HEIGHT 600
@@ -252,8 +251,8 @@ static const struct drm_ioctl_desc vmw_ioctls[] = { · 202 unmodified lines
252	251	};
253	252
254	253	static const struct pci_device_id vmw_pci_id_list[] = {
255		− {0x15ad, 0x0405, PCI_ANY_ID, PCI_ANY_ID, 0, 0, VMWGFX_CHIP_SVGAII},
256		− {0, 0, 0}
	254	+ { PCI_DEVICE(0x15ad, VMWGFX_PCI_ID_SVGA2) },
	255	+ { }
257	256	};
258	257	MODULE_DEVICE_TABLE(pci, vmw_pci_id_list);
259	258
@@ -424,8 +423,7 @@ static int vmw_request_device_late(struct vmw_private *dev_priv) · 164 unmodified lines
424	423	}
425	424
426	425	if (dev_priv->cman) {
427		− ret = vmw_cmdbuf_set_pool_size(dev_priv->cman,
428		− 2564096, 24096);
	426	+ ret = vmw_cmdbuf_set_pool_size(dev_priv->cman, 256*4096);
429	427	if (ret) {
430	428	struct vmw_cmdbuf_man *man = dev_priv->cman;
431	429
@@ -608,7 +606,7 @@ static int vmw_dma_select_mode(struct vmw_private *dev_priv) · 176 unmodified lines
608	606	*/
609	607	static int vmw_dma_masks(struct vmw_private *dev_priv)
610	608	{
611		− struct drm_device *dev = dev_priv->dev;
	609	+ struct drm_device *dev = &dev_priv->drm;
612	610	int ret = 0;
613	611
614	612	ret = dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(64));
@@ -643,26 +641,83 @@ static void vmw_vram_manager_fini(struct vmw_private *dev_priv) · 28 unmodified lines
643	641	#endif
644	642	}
645	643
646		−static int vmw_driver_load(struct drm_device *dev, unsigned long chipset)
	644	+static int vmw_setup_pci_resources(struct vmw_private *dev,
	645	+ unsigned long pci_id)
647	646	{
648		− struct vmw_private *dev_priv;
	647	+ resource_size_t fifo_start;
	648	+ resource_size_t fifo_size;
649	649	int ret;
	650	+ struct pci_dev *pdev = to_pci_dev(dev->drm.dev);
	651	+
	652	+ pci_set_master(pdev);
	653	+
	654	+ ret = pci_request_regions(pdev, "vmwgfx probe");
	655	+ if (ret)
	656	+ return ret;
	657	+
	658	+ dev->io_start = pci_resource_start(pdev, 0);
	659	+ dev->vram_start = pci_resource_start(pdev, 1);
	660	+ dev->vram_size = pci_resource_len(pdev, 1);
	661	+ fifo_start = pci_resource_start(pdev, 2);
	662	+ fifo_size = pci_resource_len(pdev, 2);
	663	+
	664	+ DRM_INFO("FIFO at %pa size is %llu kiB\n",
	665	+ &fifo_start, (uint64_t)fifo_size / 1024);
	666	+ dev->fifo_mem = devm_memremap(dev->drm.dev,
	667	+ fifo_start,
	668	+ fifo_size,
	669	+ MEMREMAP_WB);
	670	+
	671	+ if (unlikely(dev->fifo_mem == NULL)) {
	672	+ DRM_ERROR("Failed mapping FIFO memory.\n");
	673	+ return -ENOMEM;
	674	+ }
	675	+
	676	+ /*
	677	+ * This is approximate size of the vram, the exact size will only
	678	+ * be known after we read SVGA_REG_VRAM_SIZE. The PCI resource
	679	+ * size will be equal to or bigger than the size reported by
	680	+ * SVGA_REG_VRAM_SIZE.
	681	+ */
	682	+ DRM_INFO("VRAM at %pa size is %llu kiB\n",
	683	+ &dev->vram_start, (uint64_t)dev->vram_size / 1024);
	684	+
	685	+ return 0;
	686	+}
	687	+
	688	+static int vmw_detect_version(struct vmw_private *dev)
	689	+{
650	690	uint32_t svga_id;
	691	+
	692	+ vmw_write(dev, SVGA_REG_ID, SVGA_ID_2);
	693	+ svga_id = vmw_read(dev, SVGA_REG_ID);
	694	+ if (svga_id != SVGA_ID_2) {
	695	+ DRM_ERROR("Unsupported SVGA ID 0x%x on chipset 0x%x\n",
	696	+ svga_id, dev->vmw_chipset);
	697	+ return -ENOSYS;
	698	+ }
	699	+ return 0;
	700	+}
	701	+
	702	+static int vmw_driver_load(struct vmw_private *dev_priv, u32 pci_id)
	703	+{
	704	+ int ret;
651	705	enum vmw_res_type i;
652	706	bool refuse_dma = false;
653	707	char host_log[100] = {0};
	708	+ struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev);
654	709
655		− dev_priv = kzalloc(sizeof(*dev_priv), GFP_KERNEL);
656		− if (unlikely(!dev_priv)) {
657		− DRM_ERROR("Failed allocating a device private struct.\n");
658		− return -ENOMEM;
659		− }
	710	+ dev_priv->vmw_chipset = pci_id;
	711	+ dev_priv->last_read_seqno = (uint32_t) -100;
	712	+ dev_priv->drm.dev_private = dev_priv;
660	713
661		− pci_set_master(dev->pdev);
	714	+ ret = vmw_setup_pci_resources(dev_priv, pci_id);
	715	+ if (ret)
	716	+ return ret;
	717	+ ret = vmw_detect_version(dev_priv);
	718	+ if (ret)
	719	+ return ret;
662	720
663		− dev_priv->dev = dev;
664		− dev_priv->vmw_chipset = chipset;
665		− dev_priv->last_read_seqno = (uint32_t) -100;
666	721	mutex_init(&dev_priv->cmdbuf_mutex);
667	722	mutex_init(&dev_priv->release_mutex);
668	723	mutex_init(&dev_priv->binding_mutex);
@@ -672,7 +727,6 @@ static int vmw_driver_load(struct drm_device *dev, unsigned long chipset) · 3 unmodified lines
672	727	spin_lock_init(&dev_priv->hw_lock);
673	728	spin_lock_init(&dev_priv->waiter_lock);
674	729	spin_lock_init(&dev_priv->cap_lock);
675		− spin_lock_init(&dev_priv->svga_lock);
676	730	spin_lock_init(&dev_priv->cursor_lock);
677	731
678	732	for (i = vmw_res_context; i < vmw_res_max; ++i) {
@@ -687,21 +741,10 @@ static int vmw_driver_load(struct drm_device *dev, unsigned long chipset) · 8 unmodified lines
687	741
688	742	dev_priv->used_memory_size = 0;
689	743
690		− dev_priv->io_start = pci_resource_start(dev->pdev, 0);
691		− dev_priv->vram_start = pci_resource_start(dev->pdev, 1);
692		− dev_priv->mmio_start = pci_resource_start(dev->pdev, 2);
693		−
694	744	dev_priv->assume_16bpp = !!vmw_assume_16bpp;
695	745
696	746	dev_priv->enable_fb = enable_fbdev;
697	747
698		− vmw_write(dev_priv, SVGA_REG_ID, SVGA_ID_2);
699		− svga_id = vmw_read(dev_priv, SVGA_REG_ID);
700		− if (svga_id != SVGA_ID_2) {
701		− ret = -ENOSYS;
702		− DRM_ERROR("Unsupported SVGA ID 0x%x\n", svga_id);
703		− goto out_err0;
704		− }
705	748
706	749	dev_priv->capabilities = vmw_read(dev_priv, SVGA_REG_CAPABILITIES);
707	750
@@ -719,7 +762,7 @@ static int vmw_driver_load(struct drm_device *dev, unsigned long chipset) · 11 unmodified lines
719	762	}
720	763
721	764	dev_priv->vram_size = vmw_read(dev_priv, SVGA_REG_VRAM_SIZE);
722		− dev_priv->mmio_size = vmw_read(dev_priv, SVGA_REG_MEM_SIZE);
	765	+ dev_priv->fifo_mem_size = vmw_read(dev_priv, SVGA_REG_MEM_SIZE);
723	766	dev_priv->fb_max_width = vmw_read(dev_priv, SVGA_REG_MAX_WIDTH);
724	767	dev_priv->fb_max_height = vmw_read(dev_priv, SVGA_REG_MAX_HEIGHT);
725	768
@@ -793,7 +836,7 @@ static int vmw_driver_load(struct drm_device *dev, unsigned long chipset) · 67 unmodified lines
793	836	if (unlikely(ret != 0))
794	837	goto out_err0;
795	838
796		− dma_set_max_seg_size(dev->dev, U32_MAX);
	839	+ dma_set_max_seg_size(dev_priv->drm.dev, U32_MAX);
797	840
798	841	if (dev_priv->capabilities & SVGA_CAP_GMR2) {
799	842	DRM_INFO("Max GMR ids is %u\n",
@@ -803,21 +846,8 @@ static int vmw_driver_load(struct drm_device *dev, unsigned long chipset) · 3 unmodified lines
803	846	DRM_INFO("Max dedicated hypervisor surface memory is %u kiB\n",
804	847	(unsigned)dev_priv->memory_size / 1024);
805	848	}
806		− DRM_INFO("Maximum display memory size is %u kiB\n",
807		− dev_priv->prim_bb_mem / 1024);
808		− DRM_INFO("VRAM at 0x%08x size is %u kiB\n",
809		− dev_priv->vram_start, dev_priv->vram_size / 1024);
810		− DRM_INFO("MMIO at 0x%08x size is %u kiB\n",
811		− dev_priv->mmio_start, dev_priv->mmio_size / 1024);
812		−
813		− dev_priv->mmio_virt = memremap(dev_priv->mmio_start,
814		− dev_priv->mmio_size, MEMREMAP_WB);
815		−
816		− if (unlikely(dev_priv->mmio_virt == NULL)) {
817		− ret = -ENOMEM;
818		− DRM_ERROR("Failed mapping MMIO.\n");
819		− goto out_err0;
820		− }
	849	+ DRM_INFO("Maximum display memory size is %llu kiB\n",
	850	+ (uint64_t)dev_priv->prim_bb_mem / 1024);
821	851
822	852	/* Need mmio memory to check for fifo pitchlock cap. */
823	853	if (!(dev_priv->capabilities & SVGA_CAP_DISPLAY_TOPOLOGY) &&
@@ -825,7 +855,7 @@ static int vmw_driver_load(struct drm_device *dev, unsigned long chipset) · 1 unmodified line
825	855	!vmw_fifo_have_pitchlock(dev_priv)) {
826	856	ret = -ENOSYS;
827	857	DRM_ERROR("Hardware has no pitchlock\n");
828		− goto out_err4;
	858	+ goto out_err0;
829	859	}
830	860
831	861	dev_priv->tdev = ttm_object_device_init(&ttm_mem_glob, 12,
@@ -834,29 +864,11 @@ static int vmw_driver_load(struct drm_device *dev, unsigned long chipset) · 2 unmodified lines
834	864	if (unlikely(dev_priv->tdev == NULL)) {
835	865	DRM_ERROR("Unable to initialize TTM object management.\n");
836	866	ret = -ENOMEM;
837		− goto out_err4;
838		− }
839		−
840		− dev->dev_private = dev_priv;
841		−
842		− ret = pci_request_regions(dev->pdev, "vmwgfx probe");
843		− dev_priv->stealth = (ret != 0);
844		− if (dev_priv->stealth) {
845		− /**
846		− * Request at least the mmio PCI resource.
847		− */
848		−
849		− DRM_INFO("It appears like vesafb is loaded. "
850		− "Ignore above error if any.\n");
851		− ret = pci_request_region(dev->pdev, 2, "vmwgfx stealth probe");
852		− if (unlikely(ret != 0)) {
853		− DRM_ERROR("Failed reserving the SVGA MMIO resource.\n");
854		− goto out_no_device;
855		− }
	867	+ goto out_err0;
856	868	}
857	869
858	870	if (dev_priv->capabilities & SVGA_CAP_IRQMASK) {
859		− ret = vmw_irq_install(dev, dev->pdev->irq);
	871	+ ret = vmw_irq_install(&dev_priv->drm, pdev->irq);
860	872	if (ret != 0) {
861	873	DRM_ERROR("Failed installing irq: %d\n", ret);
862	874	goto out_no_irq;
@@ -873,8 +885,8 @@ static int vmw_driver_load(struct drm_device *dev, unsigned long chipset) · 10 unmodified lines
873	885	DRM_FILE_PAGE_OFFSET_START,
874	886	DRM_FILE_PAGE_OFFSET_SIZE);
875	887	ret = ttm_bo_device_init(&dev_priv->bdev, &vmw_bo_driver,
876		− dev_priv->dev->dev,
877		− dev->anon_inode->i_mapping,
	888	+ dev_priv->drm.dev,
	889	+ dev_priv->drm.anon_inode->i_mapping,
878	890	&dev_priv->vma_manager,
879	891	dev_priv->map_mode == vmw_dma_alloc_coherent,
880	892	false);
@@ -954,7 +966,7 @@ static int vmw_driver_load(struct drm_device *dev, unsigned long chipset) · 73 unmodified lines
954	966	if (ret)
955	967	goto out_no_fifo;
956	968
957		− DRM_INFO("Atomic: %s\n", (dev->driver->driver_features & DRIVER_ATOMIC)
	969	+ DRM_INFO("Atomic: %s\n", (dev_priv->drm.driver->driver_features & DRIVER_ATOMIC)
958	970	? "yes." : "no.");
959	971	if (dev_priv->sm_type == VMW_SM_5)
960	972	DRM_INFO("SM5 support available.\n");
@@ -999,16 +1011,10 @@ out_no_bdev: · 38 unmodified lines
999	1011	vmw_fence_manager_takedown(dev_priv->fman);
1000	1012	out_no_fman:
1001	1013	if (dev_priv->capabilities & SVGA_CAP_IRQMASK)
1002		− vmw_irq_uninstall(dev_priv->dev);
	1014	+ vmw_irq_uninstall(&dev_priv->drm);
1003	1015	out_no_irq:
1004		− if (dev_priv->stealth)
1005		− pci_release_region(dev->pdev, 2);
1006		− else
1007		− pci_release_regions(dev->pdev);
1008		−out_no_device:
	1016	+ pci_release_regions(pdev);
1009	1017	ttm_object_device_release(&dev_priv->tdev);
1010		−out_err4:
1011		− memunmap(dev_priv->mmio_virt);
1012	1018	out_err0:
1013	1019	for (i = vmw_res_context; i < vmw_res_max; ++i)
1014	1020	idr_destroy(&dev_priv->res_idr[i]);
@@ -1022,6 +1028,7 @@ out_err0: · 7 unmodified lines
1022	1028	static void vmw_driver_unload(struct drm_device *dev)
1023	1029	{
1024	1030	struct vmw_private *dev_priv = vmw_priv(dev);
	1031	+ struct pci_dev *pdev = to_pci_dev(dev->dev);
1025	1032	enum vmw_res_type i;
1026	1033
1027	1034	unregister_pm_notifier(&dev_priv->pm_nb);
@@ -1051,14 +1058,10 @@ static void vmw_driver_unload(struct drm_device *dev) · 23 unmodified lines
1051	1058	vmw_release_device_late(dev_priv);
1052	1059	vmw_fence_manager_takedown(dev_priv->fman);
1053	1060	if (dev_priv->capabilities & SVGA_CAP_IRQMASK)
1054		− vmw_irq_uninstall(dev_priv->dev);
1055		− if (dev_priv->stealth)
1056		− pci_release_region(dev->pdev, 2);
1057		− else
1058		− pci_release_regions(dev->pdev);
	1061	+ vmw_irq_uninstall(&dev_priv->drm);
	1062	+ pci_release_regions(pdev);
1059	1063
1060	1064	ttm_object_device_release(&dev_priv->tdev);
1061		− memunmap(dev_priv->mmio_virt);
1062	1065	if (dev_priv->ctx.staged_bindings)
1063	1066	vmw_binding_state_free(dev_priv->ctx.staged_bindings);
1064	1067
@@ -1189,12 +1192,10 @@ static void __vmw_svga_enable(struct vmw_private *dev_priv) · 124 unmodified lines
1189	1192	{
1190	1193	struct ttm_resource_manager *man = ttm_manager_type(&dev_priv->bdev, TTM_PL_VRAM);
1191	1194
1192		− spin_lock(&dev_priv->svga_lock);
1193	1195	if (!ttm_resource_manager_used(man)) {
1194	1196	vmw_write(dev_priv, SVGA_REG_ENABLE, SVGA_REG_ENABLE);
1195	1197	ttm_resource_manager_set_used(man, true);
1196	1198	}
1197		− spin_unlock(&dev_priv->svga_lock);
1198	1199	}
1199	1200
1200	1201	/**
@@ -1220,14 +1221,12 @@ static void __vmw_svga_disable(struct vmw_private *dev_priv) · 19 unmodified lines
1220	1221	{
1221	1222	struct ttm_resource_manager *man = ttm_manager_type(&dev_priv->bdev, TTM_PL_VRAM);
1222	1223
1223		− spin_lock(&dev_priv->svga_lock);
1224	1224	if (ttm_resource_manager_used(man)) {
1225	1225	ttm_resource_manager_set_used(man, false);
1226	1226	vmw_write(dev_priv, SVGA_REG_ENABLE,
1227	1227	SVGA_REG_ENABLE_HIDE \|
1228	1228	SVGA_REG_ENABLE_ENABLE);
1229	1229	}
1230		− spin_unlock(&dev_priv->svga_lock);
1231	1230	}
1232	1231
1233	1232	/**
@@ -1252,19 +1251,16 @@ void vmw_svga_disable(struct vmw_private *dev_priv) · 18 unmodified lines
1252	1251	* to be inconsistent with the device, causing modesetting problems.
1253	1252	*
1254	1253	*/
1255		− vmw_kms_lost_device(dev_priv->dev);
	1254	+ vmw_kms_lost_device(&dev_priv->drm);
1256	1255	ttm_write_lock(&dev_priv->reservation_sem, false);
1257		− spin_lock(&dev_priv->svga_lock);
1258	1256	if (ttm_resource_manager_used(man)) {
1259		− ttm_resource_manager_set_used(man, false);
1260		− spin_unlock(&dev_priv->svga_lock);
1261	1257	if (ttm_resource_manager_evict_all(&dev_priv->bdev, man))
1262	1258	DRM_ERROR("Failed evicting VRAM buffers.\n");
	1259	+ ttm_resource_manager_set_used(man, false);
1263	1260	vmw_write(dev_priv, SVGA_REG_ENABLE,
1264	1261	SVGA_REG_ENABLE_HIDE \|
1265	1262	SVGA_REG_ENABLE_ENABLE);
1266		− } else
1267		− spin_unlock(&dev_priv->svga_lock);
	1263	+ }
1268	1264	ttm_write_unlock(&dev_priv->reservation_sem);
1269	1265	}
1270	1266
@@ -1274,8 +1270,6 @@ static void vmw_remove(struct pci_dev *pdev) · 3 unmodified lines
1274	1270
1275	1271	drm_dev_unregister(dev);
1276	1272	vmw_driver_unload(dev);
1277		− drm_dev_put(dev);
1278		− pci_disable_device(pdev);
1279	1273	}
1280	1274
1281	1275	static unsigned long
@@ -1376,7 +1370,7 @@ static int vmw_pm_freeze(struct device *kdev) · 94 unmodified lines
1376	1370	* No user-space processes should be running now.
1377	1371	*/
1378	1372	ttm_suspend_unlock(&dev_priv->reservation_sem);
1379		− ret = vmw_kms_suspend(dev_priv->dev);
	1373	+ ret = vmw_kms_suspend(&dev_priv->drm);
1380	1374	if (ret) {
1381	1375	ttm_suspend_lock(&dev_priv->reservation_sem);
1382	1376	DRM_ERROR("Failed to freeze modesetting.\n");
@@ -1408,7 +1402,7 @@ static int vmw_pm_freeze(struct device *kdev) · 25 unmodified lines
1408	1402
1409	1403	vmw_fence_fifo_down(dev_priv->fman);
1410	1404	__vmw_svga_disable(dev_priv);
1411		−
	1405	+
1412	1406	vmw_release_device_late(dev_priv);
1413	1407	return 0;
1414	1408	}
@@ -1437,7 +1431,7 @@ static int vmw_pm_restore(struct device *kdev) · 22 unmodified lines
1437	1431	dev_priv->suspend_locked = false;
1438	1432	ttm_suspend_unlock(&dev_priv->reservation_sem);
1439	1433	if (dev_priv->suspend_state)
1440		− vmw_kms_resume(dev_priv->dev);
	1434	+ vmw_kms_resume(&dev_priv->drm);
1441	1435
1442	1436	if (dev_priv->enable_fb)
1443	1437	vmw_fb_on(dev_priv);
@@ -1506,39 +1500,36 @@ static struct pci_driver vmw_pci_driver = { · 62 unmodified lines
1506	1500
1507	1501	static int vmw_probe(struct pci_dev pdev, const struct pci_device_id ent)
1508	1502	{
1509		− struct drm_device *dev;
	1503	+ struct vmw_private *vmw;
1510	1504	int ret;
1511	1505
1512		− ret = pci_enable_device(pdev);
	1506	+ ret = drm_fb_helper_remove_conflicting_pci_framebuffers(pdev, "svgadrmfb");
1513	1507	if (ret)
1514	1508	return ret;
1515	1509
1516		− dev = drm_dev_alloc(&driver, &pdev->dev);
1517		− if (IS_ERR(dev)) {
1518		− ret = PTR_ERR(dev);
1519		− goto err_pci_disable_device;
1520		− }
	1510	+ ret = pcim_enable_device(pdev);
	1511	+ if (ret)
	1512	+ return ret;
1521	1513
1522		− dev->pdev = pdev;
1523		− pci_set_drvdata(pdev, dev);
	1514	+ vmw = devm_drm_dev_alloc(&pdev->dev, &driver,
	1515	+ struct vmw_private, drm);
	1516	+ if (IS_ERR(vmw))
	1517	+ return PTR_ERR(vmw);
1524	1518
1525		− ret = vmw_driver_load(dev, ent->driver_data);
1526		− if (ret)
1527		− goto err_drm_dev_put;
	1519	+ vmw->drm.pdev = pdev;
	1520	+ pci_set_drvdata(pdev, &vmw->drm);
1528	1521
1529		− ret = drm_dev_register(dev, ent->driver_data);
	1522	+ ret = vmw_driver_load(vmw, ent->device);
1530	1523	if (ret)
1531		− goto err_vmw_driver_unload;
	1524	+ return ret;
1532	1525
1533		− return 0;
	1526	+ ret = drm_dev_register(&vmw->drm, 0);
	1527	+ if (ret) {
	1528	+ vmw_driver_unload(&vmw->drm);
	1529	+ return ret;
	1530	+ }
1534	1531
1535		−err_vmw_driver_unload:
1536		− vmw_driver_unload(dev);
1537		−err_drm_dev_put:
1538		− drm_dev_put(dev);
1539		−err_pci_disable_device:
1540		− pci_disable_device(pdev);
1541		− return ret;
	1532	+ return 0;
1542	1533	}
1543	1534
1544	1535	static int __init vmwgfx_init(void)

drivers/gpu/drm/vmwgfx/vmwgfx_drv.h+33−60

@@ -66,6 +66,8 @@ · 65 unmodified lines
66	66	#define VMWGFX_CMD_BOUNCE_INIT_SIZE 32768
67	67	#define VMWGFX_ENABLE_SCREEN_TARGET_OTABLE 1
68	68
	69	+#define VMWGFX_PCI_ID_SVGA2 0x0405
	70	+
69	71	/*
70	72	* Perhaps we should have sysfs entries for these.
71	73	*/
@@ -274,13 +276,6 @@ struct vmw_surface { · 202 unmodified lines
274	276	struct list_head view_list;
275	277	};
276	278
277		−struct vmw_marker_queue {
278		− struct list_head head;
279		− u64 lag;
280		− u64 lag_time;
281		− spinlock_t lock;
282		−};
283		−
284	279	struct vmw_fifo_state {
285	280	unsigned long reserved_size;
286	281	u32 *dynamic_buffer;
@@ -290,7 +285,6 @@ struct vmw_fifo_state { · 3 unmodified lines
290	285	uint32_t capabilities;
291	286	struct mutex fifo_mutex;
292	287	struct rw_semaphore rwsem;
293		− struct vmw_marker_queue marker_queue;
294	288	bool dx;
295	289	};
296	290
@@ -489,19 +483,19 @@ enum vmw_sm_type { · 192 unmodified lines
489	483	};
490	484
491	485	struct vmw_private {
	486	+ struct drm_device drm;
492	487	struct ttm_bo_device bdev;
493	488
494	489	struct vmw_fifo_state fifo;
495	490
496		− struct drm_device *dev;
497	491	struct drm_vma_offset_manager vma_manager;
498		− unsigned long vmw_chipset;
499		− unsigned int io_start;
500		− uint32_t vram_start;
501		− uint32_t vram_size;
502		− uint32_t prim_bb_mem;
503		− uint32_t mmio_start;
504		− uint32_t mmio_size;
	492	+ u32 vmw_chipset;
	493	+ resource_size_t io_start;
	494	+ resource_size_t vram_start;
	495	+ resource_size_t vram_size;
	496	+ resource_size_t prim_bb_mem;
	497	+ u32 *fifo_mem;
	498	+ resource_size_t fifo_mem_size;
505	499	uint32_t fb_max_width;
506	500	uint32_t fb_max_height;
507	501	uint32_t texture_max_width;
@@ -510,7 +504,6 @@ struct vmw_private { · 2 unmodified lines
510	504	uint32_t stdu_max_height;
511	505	uint32_t initial_width;
512	506	uint32_t initial_height;
513		− u32 *mmio_virt;
514	507	uint32_t capabilities;
515	508	uint32_t capabilities2;
516	509	uint32_t max_gmr_ids;
@@ -590,13 +583,7 @@ struct vmw_private { · 73 unmodified lines
590	583	struct mutex cmdbuf_mutex;
591	584	struct mutex binding_mutex;
592	585
593		− /**
594		− * Operating mode.
595		− */
596		−
597		− bool stealth;
598	586	bool enable_fb;
599		− spinlock_t svga_lock;
600	587
601	588	/**
602	589	* PM management.
@@ -966,30 +953,29 @@ extern int vmw_fifo_init(struct vmw_private *dev_priv, · 363 unmodified lines
966	953	extern void vmw_fifo_release(struct vmw_private *dev_priv,
967	954	struct vmw_fifo_state *fifo);
968	955	extern void *
969		−vmw_fifo_reserve_dx(struct vmw_private *dev_priv, uint32_t bytes, int ctx_id);
970		−extern void vmw_fifo_commit(struct vmw_private *dev_priv, uint32_t bytes);
971		−extern void vmw_fifo_commit_flush(struct vmw_private *dev_priv, uint32_t bytes);
972		−extern int vmw_fifo_send_fence(struct vmw_private *dev_priv,
973		− uint32_t *seqno);
	956	+vmw_cmd_ctx_reserve(struct vmw_private *dev_priv, uint32_t bytes, int ctx_id);
	957	+extern void vmw_cmd_commit(struct vmw_private *dev_priv, uint32_t bytes);
	958	+extern void vmw_cmd_commit_flush(struct vmw_private *dev_priv, uint32_t bytes);
	959	+extern int vmw_cmd_send_fence(struct vmw_private dev_priv, uint32_t seqno);
	960	+extern bool vmw_supports_3d(struct vmw_private *dev_priv);
974	961	extern void vmw_fifo_ping_host(struct vmw_private *dev_priv, uint32_t reason);
975		−extern bool vmw_fifo_have_3d(struct vmw_private *dev_priv);
976	962	extern bool vmw_fifo_have_pitchlock(struct vmw_private *dev_priv);
977		−extern int vmw_fifo_emit_dummy_query(struct vmw_private *dev_priv,
978		− uint32_t cid);
979		−extern int vmw_fifo_flush(struct vmw_private *dev_priv,
980		− bool interruptible);
	963	+extern int vmw_cmd_emit_dummy_query(struct vmw_private *dev_priv,
	964	+ uint32_t cid);
	965	+extern int vmw_cmd_flush(struct vmw_private *dev_priv,
	966	+ bool interruptible);
981	967
982		−#define VMW_FIFO_RESERVE_DX(__priv, __bytes, __ctx_id) \
	968	+#define VMW_CMD_CTX_RESERVE(__priv, __bytes, __ctx_id) \
983	969	({ \
984		− vmw_fifo_reserve_dx(__priv, __bytes, __ctx_id) ? : ({ \
	970	+ vmw_cmd_ctx_reserve(__priv, __bytes, __ctx_id) ? : ({ \
985	971	DRM_ERROR("FIFO reserve failed at %s for %u bytes\n", \
986	972	__func__, (unsigned int) __bytes); \
987	973	NULL; \
988	974	}); \
989	975	})
990	976
991		−#define VMW_FIFO_RESERVE(__priv, __bytes) \
992		− VMW_FIFO_RESERVE_DX(__priv, __bytes, SVGA3D_INVALID_ID)
	977	+#define VMW_CMD_RESERVE(__priv, __bytes) \
	978	+ VMW_CMD_CTX_RESERVE(__priv, __bytes, SVGA3D_INVALID_ID)
993	979
994	980	/**
995	981	* TTM glue - vmwgfx_ttm_glue.c
@@ -1124,19 +1110,6 @@ extern void vmw_generic_waiter_add(struct vmw_private *dev_priv, u32 flag, · 128 unmodified lines
1124	1110	extern void vmw_generic_waiter_remove(struct vmw_private *dev_priv,
1125	1111	u32 flag, int *waiter_count);
1126	1112
1127		−/**
1128		− * Rudimentary fence-like objects currently used only for throttling -
1129		− * vmwgfx_marker.c
1130		− */
1131		−
1132		−extern void vmw_marker_queue_init(struct vmw_marker_queue *queue);
1133		−extern void vmw_marker_queue_takedown(struct vmw_marker_queue *queue);
1134		−extern int vmw_marker_push(struct vmw_marker_queue *queue,
1135		− uint32_t seqno);
1136		−extern int vmw_marker_pull(struct vmw_marker_queue *queue,
1137		− uint32_t signaled_seqno);
1138		−extern int vmw_wait_lag(struct vmw_private *dev_priv,
1139		− struct vmw_marker_queue *queue, uint32_t us);
1140	1113
1141	1114	/**
1142	1115	* Kernel framebuffer - vmwgfx_fb.c
@@ -1410,8 +1383,7 @@ struct vmw_cmdbuf_header; · 267 unmodified lines
1410	1383
1411	1384	extern struct vmw_cmdbuf_man *
1412	1385	vmw_cmdbuf_man_create(struct vmw_private *dev_priv);
1413		−extern int vmw_cmdbuf_set_pool_size(struct vmw_cmdbuf_man *man,
1414		− size_t size, size_t default_size);
	1386	+extern int vmw_cmdbuf_set_pool_size(struct vmw_cmdbuf_man *man, size_t size);
1415	1387	extern void vmw_cmdbuf_remove_pool(struct vmw_cmdbuf_man *man);
1416	1388	extern void vmw_cmdbuf_man_destroy(struct vmw_cmdbuf_man *man);
1417	1389	extern int vmw_cmdbuf_idle(struct vmw_cmdbuf_man *man, bool interruptible,
@@ -1580,28 +1552,29 @@ static inline void vmw_fifo_resource_dec(struct vmw_private *dev_priv) · 162 unmodified lines
1580	1552	}
1581	1553
1582	1554	/**
1583		− * vmw_mmio_read - Perform a MMIO read from volatile memory
	1555	+ * vmw_fifo_mem_read - Perform a MMIO read from the fifo memory
1584	1556	*
1585		− * @addr: The address to read from
	1557	+ * @fifo_reg: The fifo register to read from
1586	1558	*
1587	1559	* This function is intended to be equivalent to ioread32() on
1588	1560	* memremap'd memory, but without byteswapping.
1589	1561	*/
1590		−static inline u32 vmw_mmio_read(u32 *addr)
	1562	+static inline u32 vmw_fifo_mem_read(struct vmw_private *vmw, uint32 fifo_reg)
1591	1563	{
1592		− return READ_ONCE(*addr);
	1564	+ return READ_ONCE(*(vmw->fifo_mem + fifo_reg));
1593	1565	}
1594	1566
1595	1567	/**
1596		− * vmw_mmio_write - Perform a MMIO write to volatile memory
	1568	+ * vmw_fifo_mem_write - Perform a MMIO write to volatile memory
1597	1569	*
1598		− * @addr: The address to write to
	1570	+ * @addr: The fifo register to write to
1599	1571	*
1600	1572	* This function is intended to be equivalent to iowrite32 on
1601	1573	* memremap'd memory, but without byteswapping.
1602	1574	*/
1603		−static inline void vmw_mmio_write(u32 value, u32 *addr)
	1575	+static inline void vmw_fifo_mem_write(struct vmw_private *vmw, u32 fifo_reg,
	1576	+ u32 value)
1604	1577	{
1605		− WRITE_ONCE(*addr, value);
	1578	+ WRITE_ONCE(*(vmw->fifo_mem + fifo_reg), value);
1606	1579	}
1607	1580	#endif

drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c+9−13

@@ -724,7 +724,7 @@ static int vmw_rebind_all_dx_query(struct vmw_resource *ctx_res) · 723 unmodified lines
724	724	if (!dx_query_mob \|\| dx_query_mob->dx_query_ctx)
725	725	return 0;
726	726
727		− cmd = VMW_FIFO_RESERVE_DX(dev_priv, sizeof(*cmd), ctx_res->id);
	727	+ cmd = VMW_CMD_CTX_RESERVE(dev_priv, sizeof(*cmd), ctx_res->id);
728	728	if (cmd == NULL)
729	729	return -ENOMEM;
730	730
@@ -732,7 +732,7 @@ static int vmw_rebind_all_dx_query(struct vmw_resource *ctx_res) · 1 unmodified line
732	732	cmd->header.size = sizeof(cmd->body);
733	733	cmd->body.cid = ctx_res->id;
734	734	cmd->body.mobid = dx_query_mob->base.mem.start;
735		− vmw_fifo_commit(dev_priv, sizeof(*cmd));
	735	+ vmw_cmd_commit(dev_priv, sizeof(*cmd));
736	736
737	737	vmw_context_bind_dx_query(ctx_res, dx_query_mob);
738	738
@@ -1100,7 +1100,7 @@ static void vmw_query_bo_switch_commit(struct vmw_private *dev_priv, · 361 unmodified lines
1100	1100	BUG_ON(!ctx_entry->valid);
1101	1101	ctx = ctx_entry->res;
1102	1102
1103		− ret = vmw_fifo_emit_dummy_query(dev_priv, ctx->id);
	1103	+ ret = vmw_cmd_emit_dummy_query(dev_priv, ctx->id);
1104	1104
1105	1105	if (unlikely(ret != 0))
1106	1106	VMW_DEBUG_USER("Out of fifo space for dummy query.\n");
@@ -3762,7 +3762,7 @@ int vmw_execbuf_fence_commands(struct drm_file *file_priv, · 2655 unmodified lines
3762	3762	/* p_handle implies file_priv. */
3763	3763	BUG_ON(p_handle != NULL && file_priv == NULL);
3764	3764
3765		− ret = vmw_fifo_send_fence(dev_priv, &sequence);
	3765	+ ret = vmw_cmd_send_fence(dev_priv, &sequence);
3766	3766	if (unlikely(ret != 0)) {
3767	3767	VMW_DEBUG_USER("Fence submission error. Syncing.\n");
3768	3768	synced = true;
@@ -3876,10 +3876,10 @@ static int vmw_execbuf_submit_fifo(struct vmw_private *dev_priv, · 107 unmodified lines
3876	3876	void *cmd;
3877	3877
3878	3878	if (sw_context->dx_ctx_node)
3879		− cmd = VMW_FIFO_RESERVE_DX(dev_priv, command_size,
	3879	+ cmd = VMW_CMD_CTX_RESERVE(dev_priv, command_size,
3880	3880	sw_context->dx_ctx_node->ctx->id);
3881	3881	else
3882		− cmd = VMW_FIFO_RESERVE(dev_priv, command_size);
	3882	+ cmd = VMW_CMD_RESERVE(dev_priv, command_size);
3883	3883
3884	3884	if (!cmd)
3885	3885	return -ENOMEM;
@@ -3888,7 +3888,7 @@ static int vmw_execbuf_submit_fifo(struct vmw_private *dev_priv, · 2 unmodified lines
3888	3888	memcpy(cmd, kernel_commands, command_size);
3889	3889	vmw_resource_relocations_apply(cmd, &sw_context->res_relocations);
3890	3890	vmw_resource_relocations_free(&sw_context->res_relocations);
3891		− vmw_fifo_commit(dev_priv, command_size);
	3891	+ vmw_cmd_commit(dev_priv, command_size);
3892	3892
3893	3893	return 0;
3894	3894	}
@@ -4046,11 +4046,7 @@ int vmw_execbuf_process(struct drm_file *file_priv, · 151 unmodified lines
4046	4046	}
4047	4047
4048	4048	if (throttle_us) {
4049		− ret = vmw_wait_lag(dev_priv, &dev_priv->fifo.marker_queue,
4050		− throttle_us);
4051		−
4052		− if (ret)
4053		− goto out_free_fence_fd;
	4049	+ VMW_DEBUG_USER("Throttling is no longer supported.\n");
4054	4050	}
4055	4051
4056	4052	kernel_commands = vmw_execbuf_cmdbuf(dev_priv, user_commands,
@@ -4329,7 +4325,7 @@ void __vmw_execbuf_release_pinned_bo(struct vmw_private *dev_priv, · 272 unmodified lines
4329	4325
4330	4326	if (dev_priv->query_cid_valid) {
4331	4327	BUG_ON(fence != NULL);
4332		− ret = vmw_fifo_emit_dummy_query(dev_priv, dev_priv->query_cid);
	4328	+ ret = vmw_cmd_emit_dummy_query(dev_priv, dev_priv->query_cid);
4333	4329	if (ret)
4334	4330	goto out_no_emit;
4335	4331	dev_priv->query_cid_valid = false;

drivers/gpu/drm/vmwgfx/vmwgfx_fb.c+6−6

@@ -258,7 +258,7 @@ out_unreserve: · 257 unmodified lines
258	258	if (w && h) {
259	259	WARN_ON_ONCE(par->set_fb->funcs->dirty(cur_fb, NULL, 0, 0,
260	260	&clip, 1));
261		− vmw_fifo_flush(vmw_priv, false);
	261	+ vmw_cmd_flush(vmw_priv, false);
262	262	}
263	263	out_unlock:
264	264	mutex_unlock(&par->bo_mutex);
@@ -481,7 +481,7 @@ static int vmw_fb_kms_detach(struct vmw_fb_par *par, · 216 unmodified lines
481	481	DRM_ERROR("Could not unset a mode.\n");
482	482	return ret;
483	483	}
484		− drm_mode_destroy(par->vmw_priv->dev, par->set_mode);
	484	+ drm_mode_destroy(&par->vmw_priv->drm, par->set_mode);
485	485	par->set_mode = NULL;
486	486	}
487	487
@@ -567,7 +567,7 @@ static int vmw_fb_set_par(struct fb_info *info) · 79 unmodified lines
567	567	struct drm_display_mode *mode;
568	568	int ret;
569	569
570		− mode = drm_mode_duplicate(vmw_priv->dev, &new_mode);
	570	+ mode = drm_mode_duplicate(&vmw_priv->drm, &new_mode);
571	571	if (!mode) {
572	572	DRM_ERROR("Could not create new fb mode.\n");
573	573	return -ENOMEM;
@@ -581,7 +581,7 @@ static int vmw_fb_set_par(struct fb_info *info) · 7 unmodified lines
581	581	mode->hdisplay *
582	582	DIV_ROUND_UP(var->bits_per_pixel, 8),
583	583	mode->vdisplay)) {
584		− drm_mode_destroy(vmw_priv->dev, mode);
	584	+ drm_mode_destroy(&vmw_priv->drm, mode);
585	585	return -EINVAL;
586	586	}
587	587
@@ -615,7 +615,7 @@ static int vmw_fb_set_par(struct fb_info *info) · 27 unmodified lines
615	615
616	616	out_unlock:
617	617	if (par->set_mode)
618		− drm_mode_destroy(vmw_priv->dev, par->set_mode);
	618	+ drm_mode_destroy(&vmw_priv->drm, par->set_mode);
619	619	par->set_mode = mode;
620	620
621	621	mutex_unlock(&par->bo_mutex);
@@ -638,7 +638,7 @@ static const struct fb_ops vmw_fb_ops = { · 16 unmodified lines
638	638
639	639	int vmw_fb_init(struct vmw_private *vmw_priv)
640	640	{
641		− struct device *device = &vmw_priv->dev->pdev->dev;
	641	+ struct device *device = vmw_priv->drm.dev;
642	642	struct vmw_fb_par *par;
643	643	struct fb_info *info;
644	644	unsigned fb_width, fb_height;

drivers/gpu/drm/vmwgfx/vmwgfx_fence.c+12−16

@@ -141,8 +141,7 @@ static bool vmw_fence_enable_signaling(struct dma_fence *f) · 140 unmodified lines
141	141	struct vmw_fence_manager *fman = fman_from_fence(fence);
142	142	struct vmw_private *dev_priv = fman->dev_priv;
143	143
144		− u32 *fifo_mem = dev_priv->mmio_virt;
145		− u32 seqno = vmw_mmio_read(fifo_mem + SVGA_FIFO_FENCE);
	144	+ u32 seqno = vmw_fifo_mem_read(dev_priv, SVGA_FIFO_FENCE);
146	145	if (seqno - fence->base.seqno < VMW_FENCE_WRAP)
147	146	return false;
148	147
@@ -401,14 +400,12 @@ static bool vmw_fence_goal_new_locked(struct vmw_fence_manager *fman, · 252 unmodified lines
401	400	u32 passed_seqno)
402	401	{
403	402	u32 goal_seqno;
404		− u32 *fifo_mem;
405	403	struct vmw_fence_obj *fence;
406	404
407	405	if (likely(!fman->seqno_valid))
408	406	return false;
409	407
410		− fifo_mem = fman->dev_priv->mmio_virt;
411		− goal_seqno = vmw_mmio_read(fifo_mem + SVGA_FIFO_FENCE_GOAL);
	408	+ goal_seqno = vmw_fifo_mem_read(fman->dev_priv, SVGA_FIFO_FENCE_GOAL);
412	409	if (likely(passed_seqno - goal_seqno >= VMW_FENCE_WRAP))
413	410	return false;
414	411
@@ -416,8 +413,9 @@ static bool vmw_fence_goal_new_locked(struct vmw_fence_manager *fman, · 1 unmodified line
416	413	list_for_each_entry(fence, &fman->fence_list, head) {
417	414	if (!list_empty(&fence->seq_passed_actions)) {
418	415	fman->seqno_valid = true;
419		− vmw_mmio_write(fence->base.seqno,
420		− fifo_mem + SVGA_FIFO_FENCE_GOAL);
	416	+ vmw_fifo_mem_write(fman->dev_priv,
	417	+ SVGA_FIFO_FENCE_GOAL,
	418	+ fence->base.seqno);
421	419	break;
422	420	}
423	421	}
@@ -445,18 +443,17 @@ static bool vmw_fence_goal_check_locked(struct vmw_fence_obj *fence) · 21 unmodified lines
445	443	{
446	444	struct vmw_fence_manager *fman = fman_from_fence(fence);
447	445	u32 goal_seqno;
448		− u32 *fifo_mem;
449	446
450	447	if (dma_fence_is_signaled_locked(&fence->base))
451	448	return false;
452	449
453		− fifo_mem = fman->dev_priv->mmio_virt;
454		− goal_seqno = vmw_mmio_read(fifo_mem + SVGA_FIFO_FENCE_GOAL);
	450	+ goal_seqno = vmw_fifo_mem_read(fman->dev_priv, SVGA_FIFO_FENCE_GOAL);
455	451	if (likely(fman->seqno_valid &&
456	452	goal_seqno - fence->base.seqno < VMW_FENCE_WRAP))
457	453	return false;
458	454
459		− vmw_mmio_write(fence->base.seqno, fifo_mem + SVGA_FIFO_FENCE_GOAL);
	455	+ vmw_fifo_mem_write(fman->dev_priv, SVGA_FIFO_FENCE_GOAL,
	456	+ fence->base.seqno);
460	457	fman->seqno_valid = true;
461	458
462	459	return true;
@@ -468,9 +465,8 @@ static void __vmw_fences_update(struct vmw_fence_manager *fman) · 5 unmodified lines
468	465	struct list_head action_list;
469	466	bool needs_rerun;
470	467	uint32_t seqno, new_seqno;
471		− u32 *fifo_mem = fman->dev_priv->mmio_virt;
472	468
473		− seqno = vmw_mmio_read(fifo_mem + SVGA_FIFO_FENCE);
	469	+ seqno = vmw_fifo_mem_read(fman->dev_priv, SVGA_FIFO_FENCE);
474	470	rerun:
475	471	list_for_each_entry_safe(fence, next_fence, &fman->fence_list, head) {
476	472	if (seqno - fence->base.seqno < VMW_FENCE_WRAP) {
@@ -492,7 +488,7 @@ rerun: · 15 unmodified lines
492	488
493	489	needs_rerun = vmw_fence_goal_new_locked(fman, seqno);
494	490	if (unlikely(needs_rerun)) {
495		− new_seqno = vmw_mmio_read(fifo_mem + SVGA_FIFO_FENCE);
	491	+ new_seqno = vmw_fifo_mem_read(fman->dev_priv, SVGA_FIFO_FENCE);
496	492	if (new_seqno != seqno) {
497	493	seqno = new_seqno;
498	494	goto rerun;
@@ -1033,7 +1029,7 @@ int vmw_event_fence_action_queue(struct drm_file *file_priv, · 534 unmodified lines
1033	1029	eaction->action.type = VMW_ACTION_EVENT;
1034	1030
1035	1031	eaction->fence = vmw_fence_obj_reference(fence);
1036		− eaction->dev = fman->dev_priv->dev;
	1032	+ eaction->dev = &fman->dev_priv->drm;
1037	1033	eaction->tv_sec = tv_sec;
1038	1034	eaction->tv_usec = tv_usec;
1039	1035
@@ -1055,7 +1051,7 @@ static int vmw_event_fence_action_create(struct drm_file *file_priv, · 15 unmodified lines
1055	1051	{
1056	1052	struct vmw_event_fence_pending *event;
1057	1053	struct vmw_fence_manager *fman = fman_from_fence(fence);
1058		− struct drm_device *dev = fman->dev_priv->dev;
	1054	+ struct drm_device *dev = &fman->dev_priv->drm;
1059	1055	int ret;
1060	1056
1061	1057	event = kzalloc(sizeof(*event), GFP_KERNEL);

drivers/gpu/drm/vmwgfx/vmwgfx_gmr.c+4−4

@@ -51,7 +51,7 @@ static int vmw_gmr2_bind(struct vmw_private *dev_priv, · 50 unmodified lines
51	51	uint32_t cmd_size = define_size + remap_size;
52	52	uint32_t i;
53	53
54		− cmd_orig = cmd = VMW_FIFO_RESERVE(dev_priv, cmd_size);
	54	+ cmd_orig = cmd = VMW_CMD_RESERVE(dev_priv, cmd_size);
55	55	if (unlikely(cmd == NULL))
56	56	return -ENOMEM;
57	57
@@ -98,7 +98,7 @@ static int vmw_gmr2_bind(struct vmw_private *dev_priv, · 40 unmodified lines
98	98
99	99	BUG_ON(cmd != cmd_orig + cmd_size / sizeof(*cmd));
100	100
101		− vmw_fifo_commit(dev_priv, cmd_size);
	101	+ vmw_cmd_commit(dev_priv, cmd_size);
102	102
103	103	return 0;
104	104	}
@@ -110,7 +110,7 @@ static void vmw_gmr2_unbind(struct vmw_private *dev_priv, · 5 unmodified lines
110	110	uint32_t define_size = sizeof(define_cmd) + 4;
111	111	uint32_t *cmd;
112	112
113		− cmd = VMW_FIFO_RESERVE(dev_priv, define_size);
	113	+ cmd = VMW_CMD_RESERVE(dev_priv, define_size);
114	114	if (unlikely(cmd == NULL))
115	115	return;
116	116
@@ -120,7 +120,7 @@ static void vmw_gmr2_unbind(struct vmw_private *dev_priv, · 3 unmodified lines
120	120	*cmd++ = SVGA_CMD_DEFINE_GMR2;
121	121	memcpy(cmd, &define_cmd, sizeof(define_cmd));
122	122
123		− vmw_fifo_commit(dev_priv, define_size);
	123	+ vmw_cmd_commit(dev_priv, define_size);
124	124	}
125	125
126	126

drivers/gpu/drm/vmwgfx/vmwgfx_ioctl.c+7−8

@@ -51,7 +51,7 @@ int vmw_getparam_ioctl(struct drm_device dev, void data, · 50 unmodified lines
51	51	param->value = vmw_overlay_num_free_overlays(dev_priv);
52	52	break;
53	53	case DRM_VMW_PARAM_3D:
54		− param->value = vmw_fifo_have_3d(dev_priv) ? 1 : 0;
	54	+ param->value = vmw_supports_3d(dev_priv) ? 1 : 0;
55	55	break;
56	56	case DRM_VMW_PARAM_HW_CAPS:
57	57	param->value = dev_priv->capabilities;
@@ -67,7 +67,6 @@ int vmw_getparam_ioctl(struct drm_device dev, void data, · 9 unmodified lines
67	67	break;
68	68	case DRM_VMW_PARAM_FIFO_HW_VERSION:
69	69	{
70		− u32 *fifo_mem = dev_priv->mmio_virt;
71	70	const struct vmw_fifo_state *fifo = &dev_priv->fifo;
72	71
73	72	if ((dev_priv->capabilities & SVGA_CAP_GBOBJECTS)) {
@@ -76,11 +75,11 @@ int vmw_getparam_ioctl(struct drm_device dev, void data, · 2 unmodified lines
76	75	}
77	76
78	77	param->value =
79		− vmw_mmio_read(fifo_mem +
80		− ((fifo->capabilities &
81		− SVGA_FIFO_CAP_3D_HWVERSION_REVISED) ?
82		− SVGA_FIFO_3D_HWVERSION_REVISED :
83		− SVGA_FIFO_3D_HWVERSION));
	78	+ vmw_fifo_mem_read(dev_priv,
	79	+ ((fifo->capabilities &
	80	+ SVGA_FIFO_CAP_3D_HWVERSION_REVISED) ?
	81	+ SVGA_FIFO_3D_HWVERSION_REVISED :
	82	+ SVGA_FIFO_3D_HWVERSION));
84	83	break;
85	84	}
86	85	case DRM_VMW_PARAM_MAX_SURF_MEMORY:
@@ -235,7 +234,7 @@ int vmw_get_cap_3d_ioctl(struct drm_device dev, void data, · 148 unmodified lines
235	234	if (unlikely(ret != 0))
236	235	goto out_err;
237	236	} else {
238		− fifo_mem = dev_priv->mmio_virt;
	237	+ fifo_mem = dev_priv->fifo_mem;
239	238	memcpy(bounce, &fifo_mem[SVGA_FIFO_3D_CAPS], size);
240	239	}
241	240

drivers/gpu/drm/vmwgfx/vmwgfx_irq.c+3−7

@@ -117,12 +117,10 @@ static bool vmw_fifo_idle(struct vmw_private *dev_priv, uint32_t seqno) · 116 unmodified lines
117	117	void vmw_update_seqno(struct vmw_private *dev_priv,
118	118	struct vmw_fifo_state *fifo_state)
119	119	{
120		− u32 *fifo_mem = dev_priv->mmio_virt;
121		− uint32_t seqno = vmw_mmio_read(fifo_mem + SVGA_FIFO_FENCE);
	120	+ uint32_t seqno = vmw_fifo_mem_read(dev_priv, SVGA_FIFO_FENCE);
122	121
123	122	if (dev_priv->last_read_seqno != seqno) {
124	123	dev_priv->last_read_seqno = seqno;
125		− vmw_marker_pull(&fifo_state->marker_queue, seqno);
126	124	vmw_fences_update(dev_priv->fman);
127	125	}
128	126	}
@@ -222,11 +220,9 @@ int vmw_fallback_wait(struct vmw_private *dev_priv, · 93 unmodified lines
222	220	}
223	221	}
224	222	finish_wait(&dev_priv->fence_queue, &__wait);
225		− if (ret == 0 && fifo_idle) {
226		− u32 *fifo_mem = dev_priv->mmio_virt;
	223	+ if (ret == 0 && fifo_idle)
	224	+ vmw_fifo_mem_write(dev_priv, SVGA_FIFO_FENCE, signal_seq);
227	225
228		− vmw_mmio_write(signal_seq, fifo_mem + SVGA_FIFO_FENCE);
229		− }
230	226	wake_up_all(&dev_priv->fence_queue);
231	227	out_err:
232	228	if (fifo_idle)

drivers/gpu/drm/vmwgfx/vmwgfx_kms.c+35−39

@@ -36,9 +36,6 @@ · 35 unmodified lines
36	36
37	37	#include "vmwgfx_kms.h"
38	38
39		−/* Might need a hrtimer here? */
40		−#define VMWGFX_PRESENT_RATE ((HZ / 60 > 0) ? HZ / 60 : 1)
41		−
42	39	void vmw_du_cleanup(struct vmw_display_unit *du)
43	40	{
44	41	drm_plane_cleanup(&du->primary);
@@ -68,7 +65,7 @@ static int vmw_cursor_update_image(struct vmw_private *dev_priv, · 23 unmodified lines
68	65	if (!image)
69	66	return -EINVAL;
70	67
71		− cmd = VMW_FIFO_RESERVE(dev_priv, cmd_size);
	68	+ cmd = VMW_CMD_RESERVE(dev_priv, cmd_size);
72	69	if (unlikely(cmd == NULL))
73	70	return -ENOMEM;
74	71
@@ -83,7 +80,7 @@ static int vmw_cursor_update_image(struct vmw_private *dev_priv, · 8 unmodified lines
83	80	cmd->cursor.hotspotX = hotspotX;
84	81	cmd->cursor.hotspotY = hotspotY;
85	82
86		− vmw_fifo_commit_flush(dev_priv, cmd_size);
	83	+ vmw_cmd_commit_flush(dev_priv, cmd_size);
87	84
88	85	return 0;
89	86	}
@@ -128,15 +125,14 @@ err_unreserve: · 38 unmodified lines
128	125	static void vmw_cursor_update_position(struct vmw_private *dev_priv,
129	126	bool show, int x, int y)
130	127	{
131		− u32 *fifo_mem = dev_priv->mmio_virt;
132	128	uint32_t count;
133	129
134	130	spin_lock(&dev_priv->cursor_lock);
135		− vmw_mmio_write(show ? 1 : 0, fifo_mem + SVGA_FIFO_CURSOR_ON);
136		− vmw_mmio_write(x, fifo_mem + SVGA_FIFO_CURSOR_X);
137		− vmw_mmio_write(y, fifo_mem + SVGA_FIFO_CURSOR_Y);
138		− count = vmw_mmio_read(fifo_mem + SVGA_FIFO_CURSOR_COUNT);
139		− vmw_mmio_write(++count, fifo_mem + SVGA_FIFO_CURSOR_COUNT);
	131	+ vmw_fifo_mem_write(dev_priv, SVGA_FIFO_CURSOR_ON, show ? 1 : 0);
	132	+ vmw_fifo_mem_write(dev_priv, SVGA_FIFO_CURSOR_X, x);
	133	+ vmw_fifo_mem_write(dev_priv, SVGA_FIFO_CURSOR_Y, y);
	134	+ count = vmw_fifo_mem_read(dev_priv, SVGA_FIFO_CURSOR_COUNT);
	135	+ vmw_fifo_mem_write(dev_priv, SVGA_FIFO_CURSOR_COUNT, ++count);
140	136	spin_unlock(&dev_priv->cursor_lock);
141	137	}
142	138
@@ -236,7 +232,7 @@ err_unreserve: · 93 unmodified lines
236	232	*/
237	233	void vmw_kms_legacy_hotspot_clear(struct vmw_private *dev_priv)
238	234	{
239		− struct drm_device *dev = dev_priv->dev;
	235	+ struct drm_device *dev = &dev_priv->drm;
240	236	struct vmw_display_unit *du;
241	237	struct drm_crtc *crtc;
242	238
@@ -252,7 +248,7 @@ void vmw_kms_legacy_hotspot_clear(struct vmw_private *dev_priv) · 9 unmodified lines
252	248
253	249	void vmw_kms_cursor_post_execbuf(struct vmw_private *dev_priv)
254	250	{
255		− struct drm_device *dev = dev_priv->dev;
	251	+ struct drm_device *dev = &dev_priv->drm;
256	252	struct vmw_display_unit *du;
257	253	struct drm_crtc *crtc;
258	254
@@ -891,7 +887,7 @@ static int vmw_kms_new_framebuffer_surface(struct vmw_private *dev_priv, · 632 unmodified lines
891	887	bool is_bo_proxy)
892	888
893	889	{
894		− struct drm_device *dev = dev_priv->dev;
	890	+ struct drm_device *dev = &dev_priv->drm;
895	891	struct vmw_framebuffer_surface *vfbs;
896	892	enum SVGA3dSurfaceFormat format;
897	893	int ret;
@@ -1003,11 +999,11 @@ static int vmw_framebuffer_bo_dirty(struct drm_framebuffer *framebuffer, · 105 unmodified lines
1003	999	struct drm_clip_rect norect;
1004	1000	int ret, increment = 1;
1005	1001
1006		− drm_modeset_lock_all(dev_priv->dev);
	1002	+ drm_modeset_lock_all(&dev_priv->drm);
1007	1003
1008	1004	ret = ttm_read_lock(&dev_priv->reservation_sem, true);
1009	1005	if (unlikely(ret != 0)) {
1010		− drm_modeset_unlock_all(dev_priv->dev);
	1006	+ drm_modeset_unlock_all(&dev_priv->drm);
1011	1007	return ret;
1012	1008	}
1013	1009
@@ -1033,10 +1029,10 @@ static int vmw_framebuffer_bo_dirty(struct drm_framebuffer *framebuffer, · 19 unmodified lines
1033	1029	break;
1034	1030	}
1035	1031
1036		− vmw_fifo_flush(dev_priv, false);
	1032	+ vmw_cmd_flush(dev_priv, false);
1037	1033	ttm_read_unlock(&dev_priv->reservation_sem);
1038	1034
1039		− drm_modeset_unlock_all(dev_priv->dev);
	1035	+ drm_modeset_unlock_all(&dev_priv->drm);
1040	1036
1041	1037	return ret;
1042	1038	}
@@ -1213,7 +1209,7 @@ static int vmw_kms_new_framebuffer_bo(struct vmw_private *dev_priv, · 170 unmodified lines
1213	1209	*mode_cmd)
1214	1210
1215	1211	{
1216		− struct drm_device *dev = dev_priv->dev;
	1212	+ struct drm_device *dev = &dev_priv->drm;
1217	1213	struct vmw_framebuffer_bo *vfbd;
1218	1214	unsigned int requested_size;
1219	1215	struct drm_format_name_buf format_name;
@@ -1319,7 +1315,7 @@ vmw_kms_new_framebuffer(struct vmw_private *dev_priv, · 99 unmodified lines
1319	1315	bo && only_2d &&
1320	1316	mode_cmd->width > 64 && /* Don't create a proxy for cursor */
1321	1317	dev_priv->active_display_unit == vmw_du_screen_target) {
1322		− ret = vmw_create_bo_proxy(dev_priv->dev, mode_cmd,
	1318	+ ret = vmw_create_bo_proxy(&dev_priv->drm, mode_cmd,
1323	1319	bo, &surface);
1324	1320	if (ret)
1325	1321	return ERR_PTR(ret);
@@ -1768,7 +1764,7 @@ int vmw_kms_present(struct vmw_private *dev_priv, · 442 unmodified lines
1768	1764	if (ret)
1769	1765	return ret;
1770	1766
1771		− vmw_fifo_flush(dev_priv, false);
	1767	+ vmw_cmd_flush(dev_priv, false);
1772	1768
1773	1769	return 0;
1774	1770	}
@@ -1780,7 +1776,7 @@ vmw_kms_create_hotplug_mode_update_property(struct vmw_private *dev_priv) · 5 unmodified lines
1780	1776	return;
1781	1777
1782	1778	dev_priv->hotplug_mode_update_property =
1783		− drm_property_create_range(dev_priv->dev,
	1779	+ drm_property_create_range(&dev_priv->drm,
1784	1780	DRM_MODE_PROP_IMMUTABLE,
1785	1781	"hotplug_mode_update", 0, 1);
1786	1782
@@ -1791,7 +1787,7 @@ vmw_kms_create_hotplug_mode_update_property(struct vmw_private *dev_priv) · 4 unmodified lines
1791	1787
1792	1788	int vmw_kms_init(struct vmw_private *dev_priv)
1793	1789	{
1794		− struct drm_device *dev = dev_priv->dev;
	1790	+ struct drm_device *dev = &dev_priv->drm;
1795	1791	int ret;
1796	1792
1797	1793	drm_mode_config_init(dev);
@@ -1823,7 +1819,7 @@ int vmw_kms_close(struct vmw_private *dev_priv) · 25 unmodified lines
1823	1819	* but since it destroys encoders and our destructor calls
1824	1820	* drm_encoder_cleanup which takes the lock we deadlock.
1825	1821	*/
1826		− drm_mode_config_cleanup(dev_priv->dev);
	1822	+ drm_mode_config_cleanup(&dev_priv->drm);
1827	1823	if (dev_priv->active_display_unit == vmw_du_legacy)
1828	1824	ret = vmw_kms_ldu_close_display(dev_priv);
1829	1825
@@ -1876,11 +1872,11 @@ int vmw_kms_write_svga(struct vmw_private *vmw_priv, · 46 unmodified lines
1876	1872	if (vmw_priv->capabilities & SVGA_CAP_PITCHLOCK)
1877	1873	vmw_write(vmw_priv, SVGA_REG_PITCHLOCK, pitch);
1878	1874	else if (vmw_fifo_have_pitchlock(vmw_priv))
1879		− vmw_mmio_write(pitch, vmw_priv->mmio_virt +
1880		− SVGA_FIFO_PITCHLOCK);
	1875	+ vmw_fifo_mem_write(vmw_priv, SVGA_FIFO_PITCHLOCK, pitch);
1881	1876	vmw_write(vmw_priv, SVGA_REG_WIDTH, width);
1882	1877	vmw_write(vmw_priv, SVGA_REG_HEIGHT, height);
1883		− vmw_write(vmw_priv, SVGA_REG_BITS_PER_PIXEL, bpp);
	1878	+ if ((vmw_priv->capabilities & SVGA_CAP_8BIT_EMULATION) != 0)
	1879	+ vmw_write(vmw_priv, SVGA_REG_BITS_PER_PIXEL, bpp);
1884	1880
1885	1881	if (vmw_read(vmw_priv, SVGA_REG_DEPTH) != depth) {
1886	1882	DRM_ERROR("Invalid depth %u for %u bpp, host expects %u\n",
@@ -1934,7 +1930,7 @@ void vmw_disable_vblank(struct drm_crtc *crtc) · 47 unmodified lines
1934	1930	static int vmw_du_update_layout(struct vmw_private *dev_priv,
1935	1931	unsigned int num_rects, struct drm_rect *rects)
1936	1932	{
1937		− struct drm_device *dev = dev_priv->dev;
	1933	+ struct drm_device *dev = &dev_priv->drm;
1938	1934	struct vmw_display_unit *du;
1939	1935	struct drm_connector *con;
1940	1936	struct drm_connector_list_iter conn_iter;
@@ -2366,7 +2362,7 @@ int vmw_kms_helper_dirty(struct vmw_private *dev_priv, · 425 unmodified lines
2366	2362	if (dirty->crtc) {
2367	2363	units[num_units++] = vmw_crtc_to_du(dirty->crtc);
2368	2364	} else {
2369		− list_for_each_entry(crtc, &dev_priv->dev->mode_config.crtc_list,
	2365	+ list_for_each_entry(crtc, &dev_priv->drm.mode_config.crtc_list,
2370	2366	head) {
2371	2367	struct drm_plane *plane = crtc->primary;
2372	2368
@@ -2386,7 +2382,7 @@ int vmw_kms_helper_dirty(struct vmw_private *dev_priv, · 13 unmodified lines
2386	2382
2387	2383	dirty->unit = unit;
2388	2384	if (dirty->fifo_reserve_size > 0) {
2389		− dirty->cmd = VMW_FIFO_RESERVE(dev_priv,
	2385	+ dirty->cmd = VMW_CMD_RESERVE(dev_priv,
2390	2386	dirty->fifo_reserve_size);
2391	2387	if (!dirty->cmd)
2392	2388	return -ENOMEM;
@@ -2520,7 +2516,7 @@ int vmw_kms_update_proxy(struct vmw_resource *res, · 127 unmodified lines
2520	2516	if (!clips)
2521	2517	return 0;
2522	2518
2523		− cmd = VMW_FIFO_RESERVE(dev_priv, sizeof(cmd) num_clips);
	2519	+ cmd = VMW_CMD_RESERVE(dev_priv, sizeof(cmd) num_clips);
2524	2520	if (!cmd)
2525	2521	return -ENOMEM;
2526	2522
@@ -2549,7 +2545,7 @@ int vmw_kms_update_proxy(struct vmw_resource *res, · 22 unmodified lines
2549	2545	copy_size += sizeof(*cmd);
2550	2546	}
2551	2547
2552		− vmw_fifo_commit(dev_priv, copy_size);
	2548	+ vmw_cmd_commit(dev_priv, copy_size);
2553	2549
2554	2550	return 0;
2555	2551	}
@@ -2568,8 +2564,8 @@ int vmw_kms_fbdev_init_data(struct vmw_private *dev_priv, · 12 unmodified lines
2568	2564	int i = 0;
2569	2565	int ret = 0;
2570	2566
2571		− mutex_lock(&dev_priv->dev->mode_config.mutex);
2572		− list_for_each_entry(con, &dev_priv->dev->mode_config.connector_list,
	2567	+ mutex_lock(&dev_priv->drm.mode_config.mutex);
	2568	+ list_for_each_entry(con, &dev_priv->drm.mode_config.connector_list,
2573	2569	head) {
2574	2570	if (i == unit)
2575	2571	break;
@@ -2577,7 +2573,7 @@ int vmw_kms_fbdev_init_data(struct vmw_private *dev_priv, · 1 unmodified line
2577	2573	++i;
2578	2574	}
2579	2575
2580		− if (&con->head == &dev_priv->dev->mode_config.connector_list) {
	2576	+ if (&con->head == &dev_priv->drm.mode_config.connector_list) {
2581	2577	DRM_ERROR("Could not find initial display unit.\n");
2582	2578	ret = -EINVAL;
2583	2579	goto out_unlock;
@@ -2611,7 +2607,7 @@ int vmw_kms_fbdev_init_data(struct vmw_private *dev_priv, · 27 unmodified lines
2611	2607	}
2612	2608
2613	2609	out_unlock:
2614		− mutex_unlock(&dev_priv->dev->mode_config.mutex);
	2610	+ mutex_unlock(&dev_priv->drm.mode_config.mutex);
2615	2611
2616	2612	return ret;
2617	2613	}
@@ -2631,7 +2627,7 @@ vmw_kms_create_implicit_placement_property(struct vmw_private *dev_priv) · 13 unmodified lines
2631	2627	return;
2632	2628
2633	2629	dev_priv->implicit_placement_property =
2634		− drm_property_create_range(dev_priv->dev,
	2630	+ drm_property_create_range(&dev_priv->drm,
2635	2631	DRM_MODE_PROP_IMMUTABLE,
2636	2632	"implicit_placement", 0, 1);
2637	2633	}
@@ -2752,7 +2748,7 @@ int vmw_du_helper_plane_update(struct vmw_du_update_plane *update) · 114 unmodified lines
2752	2748	goto out_unref;
2753	2749
2754	2750	reserved_size = update->calc_fifo_size(update, num_hits);
2755		− cmd_start = VMW_FIFO_RESERVE(update->dev_priv, reserved_size);
	2751	+ cmd_start = VMW_CMD_RESERVE(update->dev_priv, reserved_size);
2756	2752	if (!cmd_start) {
2757	2753	ret = -ENOMEM;
2758	2754	goto out_revert;
@@ -2801,7 +2797,7 @@ int vmw_du_helper_plane_update(struct vmw_du_update_plane *update) · 42 unmodified lines
2801	2797	if (reserved_size < submit_size)
2802	2798	submit_size = 0;
2803	2799
2804		− vmw_fifo_commit(update->dev_priv, submit_size);
	2800	+ vmw_cmd_commit(update->dev_priv, submit_size);
2805	2801
2806	2802	vmw_kms_helper_validation_finish(update->dev_priv, NULL, &val_ctx,
2807	2803	update->out_fence, NULL);

drivers/gpu/drm/vmwgfx/vmwgfx_ldu.c+4−5

@@ -125,7 +125,6 @@ static int vmw_ldu_commit_list(struct vmw_private *dev_priv) · 124 unmodified lines
125	125	vmw_write(dev_priv, SVGA_REG_DISPLAY_POSITION_Y, crtc->y);
126	126	vmw_write(dev_priv, SVGA_REG_DISPLAY_WIDTH, crtc->mode.hdisplay);
127	127	vmw_write(dev_priv, SVGA_REG_DISPLAY_HEIGHT, crtc->mode.vdisplay);
128		− vmw_write(dev_priv, SVGA_REG_DISPLAY_ID, SVGA_ID_INVALID);
129	128
130	129	i++;
131	130	}
@@ -355,7 +354,7 @@ static const struct drm_crtc_helper_funcs vmw_ldu_crtc_helper_funcs = { · 223 unmodified lines
355	354	static int vmw_ldu_init(struct vmw_private *dev_priv, unsigned unit)
356	355	{
357	356	struct vmw_legacy_display_unit *ldu;
358		− struct drm_device *dev = dev_priv->dev;
	357	+ struct drm_device *dev = &dev_priv->drm;
359	358	struct drm_connector *connector;
360	359	struct drm_encoder *encoder;
361	360	struct drm_plane primary, cursor;
@@ -479,7 +478,7 @@ err_free: · 117 unmodified lines
479	478
480	479	int vmw_kms_ldu_init_display(struct vmw_private *dev_priv)
481	480	{
482		− struct drm_device *dev = dev_priv->dev;
	481	+ struct drm_device *dev = &dev_priv->drm;
483	482	int i, ret;
484	483
485	484	if (dev_priv->ldu_priv) {
@@ -554,7 +553,7 @@ int vmw_kms_ldu_do_bo_dirty(struct vmw_private *dev_priv, · 68 unmodified lines
554	553	} *cmd;
555	554
556	555	fifo_size = sizeof(cmd) num_clips;
557		− cmd = VMW_FIFO_RESERVE(dev_priv, fifo_size);
	556	+ cmd = VMW_CMD_RESERVE(dev_priv, fifo_size);
558	557	if (unlikely(cmd == NULL))
559	558	return -ENOMEM;
560	559
@@ -567,6 +566,6 @@ int vmw_kms_ldu_do_bo_dirty(struct vmw_private *dev_priv, · 6 unmodified lines
567	566	cmd[i].body.height = clips->y2 - clips->y1;
568	567	}
569	568
570		− vmw_fifo_commit(dev_priv, fifo_size);
	569	+ vmw_cmd_commit(dev_priv, fifo_size);
571	570	return 0;
572	571	}

drivers/gpu/drm/vmwgfx/vmwgfx_marker.c+0−155

@@ -1,155 +0,0 @@
1		−// SPDX-License-Identifier: GPL-2.0 OR MIT
2		−/**************************************************************************
3		− *
4		− * Copyright 2010 VMware, Inc., Palo Alto, CA., USA
5		− *
6		− * Permission is hereby granted, free of charge, to any person obtaining a
7		− * copy of this software and associated documentation files (the
8		− * "Software"), to deal in the Software without restriction, including
9		− * without limitation the rights to use, copy, modify, merge, publish,
10		− * distribute, sub license, and/or sell copies of the Software, and to
11		− * permit persons to whom the Software is furnished to do so, subject to
12		− * the following conditions:
13		− *
14		− * The above copyright notice and this permission notice (including the
15		− * next paragraph) shall be included in all copies or substantial portions
16		− * of the Software.
17		− *
18		− * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19		− * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20		− * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
21		− * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
22		− * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
23		− * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
24		− * USE OR OTHER DEALINGS IN THE SOFTWARE.
25		− *
26		− **************************************************************************/
27		−
28		−
29		−#include "vmwgfx_drv.h"
30		−
31		−struct vmw_marker {
32		− struct list_head head;
33		− uint32_t seqno;
34		− u64 submitted;
35		−};
36		−
37		−void vmw_marker_queue_init(struct vmw_marker_queue *queue)
38		−{
39		− INIT_LIST_HEAD(&queue->head);
40		− queue->lag = 0;
41		− queue->lag_time = ktime_get_raw_ns();
42		− spin_lock_init(&queue->lock);
43		−}
44		−
45		−void vmw_marker_queue_takedown(struct vmw_marker_queue *queue)
46		−{
47		− struct vmw_marker marker, next;
48		−
49		− spin_lock(&queue->lock);
50		− list_for_each_entry_safe(marker, next, &queue->head, head) {
51		− kfree(marker);
52		− }
53		− spin_unlock(&queue->lock);
54		−}
55		−
56		−int vmw_marker_push(struct vmw_marker_queue *queue,
57		− uint32_t seqno)
58		−{
59		− struct vmw_marker marker = kmalloc(sizeof(marker), GFP_KERNEL);
60		−
61		− if (unlikely(!marker))
62		− return -ENOMEM;
63		−
64		− marker->seqno = seqno;
65		− marker->submitted = ktime_get_raw_ns();
66		− spin_lock(&queue->lock);
67		− list_add_tail(&marker->head, &queue->head);
68		− spin_unlock(&queue->lock);
69		−
70		− return 0;
71		−}
72		−
73		−int vmw_marker_pull(struct vmw_marker_queue *queue,
74		− uint32_t signaled_seqno)
75		−{
76		− struct vmw_marker marker, next;
77		− bool updated = false;
78		− u64 now;
79		−
80		− spin_lock(&queue->lock);
81		− now = ktime_get_raw_ns();
82		−
83		− if (list_empty(&queue->head)) {
84		− queue->lag = 0;
85		− queue->lag_time = now;
86		− updated = true;
87		− goto out_unlock;
88		− }
89		−
90		− list_for_each_entry_safe(marker, next, &queue->head, head) {
91		− if (signaled_seqno - marker->seqno > (1 << 30))
92		− continue;
93		−
94		− queue->lag = now - marker->submitted;
95		− queue->lag_time = now;
96		− updated = true;
97		− list_del(&marker->head);
98		− kfree(marker);
99		− }
100		−
101		−out_unlock:
102		− spin_unlock(&queue->lock);
103		−
104		− return (updated) ? 0 : -EBUSY;
105		−}
106		−
107		−static u64 vmw_fifo_lag(struct vmw_marker_queue *queue)
108		−{
109		− u64 now;
110		−
111		− spin_lock(&queue->lock);
112		− now = ktime_get_raw_ns();
113		− queue->lag += now - queue->lag_time;
114		− queue->lag_time = now;
115		− spin_unlock(&queue->lock);
116		− return queue->lag;
117		−}
118		−
119		−
120		−static bool vmw_lag_lt(struct vmw_marker_queue *queue,
121		− uint32_t us)
122		−{
123		− u64 cond = (u64) us * NSEC_PER_USEC;
124		−
125		− return vmw_fifo_lag(queue) <= cond;
126		−}
127		−
128		−int vmw_wait_lag(struct vmw_private *dev_priv,
129		− struct vmw_marker_queue *queue, uint32_t us)
130		−{
131		− struct vmw_marker *marker;
132		− uint32_t seqno;
133		− int ret;
134		−
135		− while (!vmw_lag_lt(queue, us)) {
136		− spin_lock(&queue->lock);
137		− if (list_empty(&queue->head))
138		− seqno = atomic_read(&dev_priv->marker_seq);
139		− else {
140		− marker = list_first_entry(&queue->head,
141		− struct vmw_marker, head);
142		− seqno = marker->seqno;
143		− }
144		− spin_unlock(&queue->lock);
145		−
146		− ret = vmw_wait_seqno(dev_priv, false, seqno, true,
147		− 3*HZ);
148		−
149		− if (unlikely(ret != 0))
150		− return ret;
151		−
152		− (void) vmw_marker_pull(queue, seqno);
153		− }
154		− return 0;
155		−}

drivers/gpu/drm/vmwgfx/vmwgfx_mob.c+8−8

@@ -148,7 +148,7 @@ static int vmw_setup_otable_base(struct vmw_private *dev_priv, · 147 unmodified lines
148	148	mob->pt_level += VMW_MOBFMT_PTDEPTH_1 - SVGA3D_MOBFMT_PTDEPTH_1;
149	149	}
150	150
151		− cmd = VMW_FIFO_RESERVE(dev_priv, sizeof(*cmd));
	151	+ cmd = VMW_CMD_RESERVE(dev_priv, sizeof(*cmd));
152	152	if (unlikely(cmd == NULL)) {
153	153	ret = -ENOMEM;
154	154	goto out_no_fifo;
@@ -170,7 +170,7 @@ static int vmw_setup_otable_base(struct vmw_private *dev_priv, · 15 unmodified lines
170	170	*/
171	171	BUG_ON(mob->pt_level == VMW_MOBFMT_PTDEPTH_2);
172	172
173		− vmw_fifo_commit(dev_priv, sizeof(*cmd));
	173	+ vmw_cmd_commit(dev_priv, sizeof(*cmd));
174	174	otable->page_table = mob;
175	175
176	176	return 0;
@@ -203,7 +203,7 @@ static void vmw_takedown_otable_base(struct vmw_private *dev_priv, · 26 unmodified lines
203	203	return;
204	204
205	205	bo = otable->page_table->pt_bo;
206		− cmd = VMW_FIFO_RESERVE(dev_priv, sizeof(*cmd));
	206	+ cmd = VMW_CMD_RESERVE(dev_priv, sizeof(*cmd));
207	207	if (unlikely(cmd == NULL))
208	208	return;
209	209
@@ -215,7 +215,7 @@ static void vmw_takedown_otable_base(struct vmw_private *dev_priv, · 5 unmodified lines
215	215	cmd->body.sizeInBytes = 0;
216	216	cmd->body.validSizeInBytes = 0;
217	217	cmd->body.ptDepth = SVGA3D_MOBFMT_INVALID;
218		− vmw_fifo_commit(dev_priv, sizeof(*cmd));
	218	+ vmw_cmd_commit(dev_priv, sizeof(*cmd));
219	219
220	220	if (bo) {
221	221	int ret;
@@ -558,12 +558,12 @@ void vmw_mob_unbind(struct vmw_private *dev_priv, · 336 unmodified lines
558	558	BUG_ON(ret != 0);
559	559	}
560	560
561		− cmd = VMW_FIFO_RESERVE(dev_priv, sizeof(*cmd));
	561	+ cmd = VMW_CMD_RESERVE(dev_priv, sizeof(*cmd));
562	562	if (cmd) {
563	563	cmd->header.id = SVGA_3D_CMD_DESTROY_GB_MOB;
564	564	cmd->header.size = sizeof(cmd->body);
565	565	cmd->body.mobid = mob->id;
566		− vmw_fifo_commit(dev_priv, sizeof(*cmd));
	566	+ vmw_cmd_commit(dev_priv, sizeof(*cmd));
567	567	}
568	568
569	569	if (bo) {
@@ -625,7 +625,7 @@ int vmw_mob_bind(struct vmw_private *dev_priv, · 55 unmodified lines
625	625
626	626	vmw_fifo_resource_inc(dev_priv);
627	627
628		− cmd = VMW_FIFO_RESERVE(dev_priv, sizeof(*cmd));
	628	+ cmd = VMW_CMD_RESERVE(dev_priv, sizeof(*cmd));
629	629	if (unlikely(cmd == NULL))
630	630	goto out_no_cmd_space;
631	631
@@ -636,7 +636,7 @@ int vmw_mob_bind(struct vmw_private *dev_priv, · 4 unmodified lines
636	636	cmd->body.base = mob->pt_root_page >> PAGE_SHIFT;
637	637	cmd->body.sizeInBytes = num_data_pages * PAGE_SIZE;
638	638
639		− vmw_fifo_commit(dev_priv, sizeof(*cmd));
	639	+ vmw_cmd_commit(dev_priv, sizeof(*cmd));
640	640
641	641	return 0;
642	642

drivers/gpu/drm/vmwgfx/vmwgfx_overlay.c+4−4

@@ -122,7 +122,7 @@ static int vmw_overlay_send_put(struct vmw_private *dev_priv, · 121 unmodified lines
122	122
123	123	fifo_size = sizeof(cmds) + sizeof(flush) + sizeof(items) num_items;
124	124
125		− cmds = VMW_FIFO_RESERVE(dev_priv, fifo_size);
	125	+ cmds = VMW_CMD_RESERVE(dev_priv, fifo_size);
126	126	/* hardware has hung, can't do anything here */
127	127	if (!cmds)
128	128	return -ENOMEM;
@@ -169,7 +169,7 @@ static int vmw_overlay_send_put(struct vmw_private *dev_priv, · 40 unmodified lines
169	169
170	170	fill_flush(flush, arg->stream_id);
171	171
172		− vmw_fifo_commit(dev_priv, fifo_size);
	172	+ vmw_cmd_commit(dev_priv, fifo_size);
173	173
174	174	return 0;
175	175	}
@@ -192,7 +192,7 @@ static int vmw_overlay_send_stop(struct vmw_private *dev_priv, · 16 unmodified lines
192	192	int ret;
193	193
194	194	for (;;) {
195		− cmds = VMW_FIFO_RESERVE(dev_priv, sizeof(*cmds));
	195	+ cmds = VMW_CMD_RESERVE(dev_priv, sizeof(*cmds));
196	196	if (cmds)
197	197	break;
198	198
@@ -211,7 +211,7 @@ static int vmw_overlay_send_stop(struct vmw_private *dev_priv, · 12 unmodified lines
211	211	cmds->body.items[0].value = false;
212	212	fill_flush(&cmds->flush, stream_id);
213	213
214		− vmw_fifo_commit(dev_priv, sizeof(*cmds));
	214	+ vmw_cmd_commit(dev_priv, sizeof(*cmds));
215	215
216	216	return 0;
217	217	}

drivers/gpu/drm/vmwgfx/vmwgfx_resource.c+2−2

@@ -827,7 +827,7 @@ int vmw_query_readback_all(struct vmw_buffer_object *dx_query_mob) · 826 unmodified lines
827	827	dx_query_ctx = dx_query_mob->dx_query_ctx;
828	828	dev_priv = dx_query_ctx->dev_priv;
829	829
830		− cmd = VMW_FIFO_RESERVE_DX(dev_priv, sizeof(*cmd), dx_query_ctx->id);
	830	+ cmd = VMW_CMD_CTX_RESERVE(dev_priv, sizeof(*cmd), dx_query_ctx->id);
831	831	if (unlikely(cmd == NULL))
832	832	return -ENOMEM;
833	833
@@ -835,7 +835,7 @@ int vmw_query_readback_all(struct vmw_buffer_object *dx_query_mob) · 1 unmodified line
835	835	cmd->header.size = sizeof(cmd->body);
836	836	cmd->body.cid = dx_query_ctx->id;
837	837
838		− vmw_fifo_commit(dev_priv, sizeof(*cmd));
	838	+ vmw_cmd_commit(dev_priv, sizeof(*cmd));
839	839
840	840	/* Triggers a rebind the next time affected context is bound */
841	841	dx_query_mob->dx_query_ctx = NULL;

drivers/gpu/drm/vmwgfx/vmwgfx_scrn.c+14−14

@@ -132,7 +132,7 @@ static int vmw_sou_fifo_create(struct vmw_private *dev_priv, · 131 unmodified lines
132	132	BUG_ON(!sou->buffer);
133	133
134	134	fifo_size = sizeof(*cmd);
135		− cmd = VMW_FIFO_RESERVE(dev_priv, fifo_size);
	135	+ cmd = VMW_CMD_RESERVE(dev_priv, fifo_size);
136	136	if (unlikely(cmd == NULL))
137	137	return -ENOMEM;
138	138
@@ -153,7 +153,7 @@ static int vmw_sou_fifo_create(struct vmw_private *dev_priv, · 14 unmodified lines
153	153	vmw_bo_get_guest_ptr(&sou->buffer->base, &cmd->obj.backingStore.ptr);
154	154	cmd->obj.backingStore.pitch = mode->hdisplay * 4;
155	155
156		− vmw_fifo_commit(dev_priv, fifo_size);
	156	+ vmw_cmd_commit(dev_priv, fifo_size);
157	157
158	158	sou->defined = true;
159	159
@@ -181,7 +181,7 @@ static int vmw_sou_fifo_destroy(struct vmw_private *dev_priv, · 21 unmodified lines
181	181	return 0;
182	182
183	183	fifo_size = sizeof(*cmd);
184		− cmd = VMW_FIFO_RESERVE(dev_priv, fifo_size);
	184	+ cmd = VMW_CMD_RESERVE(dev_priv, fifo_size);
185	185	if (unlikely(cmd == NULL))
186	186	return -ENOMEM;
187	187
@@ -189,7 +189,7 @@ static int vmw_sou_fifo_destroy(struct vmw_private *dev_priv, · 1 unmodified line
189	189	cmd->header.cmdType = SVGA_CMD_DESTROY_SCREEN;
190	190	cmd->body.screenId = sou->base.unit;
191	191
192		− vmw_fifo_commit(dev_priv, fifo_size);
	192	+ vmw_cmd_commit(dev_priv, fifo_size);
193	193
194	194	/* Force sync */
195	195	ret = vmw_fallback_wait(dev_priv, false, true, 0, false, 3*HZ);
@@ -829,7 +829,7 @@ static const struct drm_crtc_helper_funcs vmw_sou_crtc_helper_funcs = { · 633 unmodified lines
829	829	static int vmw_sou_init(struct vmw_private *dev_priv, unsigned unit)
830	830	{
831	831	struct vmw_screen_object_unit *sou;
832		− struct drm_device *dev = dev_priv->dev;
	832	+ struct drm_device *dev = &dev_priv->drm;
833	833	struct drm_connector *connector;
834	834	struct drm_encoder *encoder;
835	835	struct drm_plane primary, cursor;
@@ -946,7 +946,7 @@ err_free: · 110 unmodified lines
946	946
947	947	int vmw_kms_sou_init_display(struct vmw_private *dev_priv)
948	948	{
949		− struct drm_device *dev = dev_priv->dev;
	949	+ struct drm_device *dev = &dev_priv->drm;
950	950	int i, ret;
951	951
952	952	if (!(dev_priv->capabilities & SVGA_CAP_SCREEN_OBJECT_2)) {
@@ -992,7 +992,7 @@ static int do_bo_define_gmrfb(struct vmw_private *dev_priv, · 39 unmodified lines
992	992	if (depth == 32)
993	993	depth = 24;
994	994
995		− cmd = VMW_FIFO_RESERVE(dev_priv, sizeof(*cmd));
	995	+ cmd = VMW_CMD_RESERVE(dev_priv, sizeof(*cmd));
996	996	if (!cmd)
997	997	return -ENOMEM;
998	998
@@ -1003,7 +1003,7 @@ static int do_bo_define_gmrfb(struct vmw_private *dev_priv, · 4 unmodified lines
1003	1003	cmd->body.bytesPerLine = framebuffer->base.pitches[0];
1004	1004	/* Buffer is reserved in vram or GMR */
1005	1005	vmw_bo_get_guest_ptr(&buf->base, &cmd->body.ptr);
1006		− vmw_fifo_commit(dev_priv, sizeof(*cmd));
	1006	+ vmw_cmd_commit(dev_priv, sizeof(*cmd));
1007	1007
1008	1008	return 0;
1009	1009	}
@@ -1029,7 +1029,7 @@ static void vmw_sou_surface_fifo_commit(struct vmw_kms_dirty *dirty) · 19 unmodified lines
1029	1029	int i;
1030	1030
1031	1031	if (!dirty->num_hits) {
1032		− vmw_fifo_commit(dirty->dev_priv, 0);
	1032	+ vmw_cmd_commit(dirty->dev_priv, 0);
1033	1033	return;
1034	1034	}
1035	1035
@@ -1061,7 +1061,7 @@ static void vmw_sou_surface_fifo_commit(struct vmw_kms_dirty *dirty) · 25 unmodified lines
1061	1061	blit->bottom -= sdirty->top;
1062	1062	}
1063	1063
1064		− vmw_fifo_commit(dirty->dev_priv, region_size + sizeof(*cmd));
	1064	+ vmw_cmd_commit(dirty->dev_priv, region_size + sizeof(*cmd));
1065	1065
1066	1066	sdirty->left = sdirty->top = S32_MAX;
1067	1067	sdirty->right = sdirty->bottom = S32_MIN;
@@ -1185,11 +1185,11 @@ out_unref: · 117 unmodified lines
1185	1185	static void vmw_sou_bo_fifo_commit(struct vmw_kms_dirty *dirty)
1186	1186	{
1187	1187	if (!dirty->num_hits) {
1188		− vmw_fifo_commit(dirty->dev_priv, 0);
	1188	+ vmw_cmd_commit(dirty->dev_priv, 0);
1189	1189	return;
1190	1190	}
1191	1191
1192		− vmw_fifo_commit(dirty->dev_priv,
	1192	+ vmw_cmd_commit(dirty->dev_priv,
1193	1193	sizeof(struct vmw_kms_sou_bo_blit) *
1194	1194	dirty->num_hits);
1195	1195	}
@@ -1295,11 +1295,11 @@ out_unref: · 99 unmodified lines
1295	1295	static void vmw_sou_readback_fifo_commit(struct vmw_kms_dirty *dirty)
1296	1296	{
1297	1297	if (!dirty->num_hits) {
1298		− vmw_fifo_commit(dirty->dev_priv, 0);
	1298	+ vmw_cmd_commit(dirty->dev_priv, 0);
1299	1299	return;
1300	1300	}
1301	1301
1302		− vmw_fifo_commit(dirty->dev_priv,
	1302	+ vmw_cmd_commit(dirty->dev_priv,
1303	1303	sizeof(struct vmw_kms_sou_readback_blit) *
1304	1304	dirty->num_hits);
1305	1305	}

drivers/gpu/drm/vmwgfx/vmwgfx_shader.c+12−12

@@ -222,7 +222,7 @@ static int vmw_gb_shader_create(struct vmw_resource *res) · 221 unmodified lines
222	222	goto out_no_fifo;
223	223	}
224	224
225		− cmd = VMW_FIFO_RESERVE(dev_priv, sizeof(*cmd));
	225	+ cmd = VMW_CMD_RESERVE(dev_priv, sizeof(*cmd));
226	226	if (unlikely(cmd == NULL)) {
227	227	ret = -ENOMEM;
228	228	goto out_no_fifo;
@@ -233,7 +233,7 @@ static int vmw_gb_shader_create(struct vmw_resource *res) · 4 unmodified lines
233	233	cmd->body.shid = res->id;
234	234	cmd->body.type = shader->type;
235	235	cmd->body.sizeInBytes = shader->size;
236		− vmw_fifo_commit(dev_priv, sizeof(*cmd));
	236	+ vmw_cmd_commit(dev_priv, sizeof(*cmd));
237	237	vmw_fifo_resource_inc(dev_priv);
238	238
239	239	return 0;
@@ -256,7 +256,7 @@ static int vmw_gb_shader_bind(struct vmw_resource *res, · 16 unmodified lines
256	256
257	257	BUG_ON(bo->mem.mem_type != VMW_PL_MOB);
258	258
259		− cmd = VMW_FIFO_RESERVE(dev_priv, sizeof(*cmd));
	259	+ cmd = VMW_CMD_RESERVE(dev_priv, sizeof(*cmd));
260	260	if (unlikely(cmd == NULL))
261	261	return -ENOMEM;
262	262
@@ -266,7 +266,7 @@ static int vmw_gb_shader_bind(struct vmw_resource *res, · 3 unmodified lines
266	266	cmd->body.mobid = bo->mem.start;
267	267	cmd->body.offsetInBytes = res->backup_offset;
268	268	res->backup_dirty = false;
269		− vmw_fifo_commit(dev_priv, sizeof(*cmd));
	269	+ vmw_cmd_commit(dev_priv, sizeof(*cmd));
270	270
271	271	return 0;
272	272	}
@@ -284,7 +284,7 @@ static int vmw_gb_shader_unbind(struct vmw_resource *res, · 11 unmodified lines
284	284
285	285	BUG_ON(res->backup->base.mem.mem_type != VMW_PL_MOB);
286	286
287		− cmd = VMW_FIFO_RESERVE(dev_priv, sizeof(*cmd));
	287	+ cmd = VMW_CMD_RESERVE(dev_priv, sizeof(*cmd));
288	288	if (unlikely(cmd == NULL))
289	289	return -ENOMEM;
290	290
@@ -293,7 +293,7 @@ static int vmw_gb_shader_unbind(struct vmw_resource *res, · 2 unmodified lines
293	293	cmd->body.shid = res->id;
294	294	cmd->body.mobid = SVGA3D_INVALID_ID;
295	295	cmd->body.offsetInBytes = 0;
296		− vmw_fifo_commit(dev_priv, sizeof(*cmd));
	296	+ vmw_cmd_commit(dev_priv, sizeof(*cmd));
297	297
298	298	/*
299	299	* Create a fence object and fence the backup buffer.
@@ -324,7 +324,7 @@ static int vmw_gb_shader_destroy(struct vmw_resource *res) · 24 unmodified lines
324	324	mutex_lock(&dev_priv->binding_mutex);
325	325	vmw_binding_res_list_scrub(&res->binding_head);
326	326
327		− cmd = VMW_FIFO_RESERVE(dev_priv, sizeof(*cmd));
	327	+ cmd = VMW_CMD_RESERVE(dev_priv, sizeof(*cmd));
328	328	if (unlikely(cmd == NULL)) {
329	329	mutex_unlock(&dev_priv->binding_mutex);
330	330	return -ENOMEM;
@@ -333,7 +333,7 @@ static int vmw_gb_shader_destroy(struct vmw_resource *res) · 2 unmodified lines
333	333	cmd->header.id = SVGA_3D_CMD_DESTROY_GB_SHADER;
334	334	cmd->header.size = sizeof(cmd->body);
335	335	cmd->body.shid = res->id;
336		− vmw_fifo_commit(dev_priv, sizeof(*cmd));
	336	+ vmw_cmd_commit(dev_priv, sizeof(*cmd));
337	337	mutex_unlock(&dev_priv->binding_mutex);
338	338	vmw_resource_release_id(res);
339	339	vmw_fifo_resource_dec(dev_priv);
@@ -394,7 +394,7 @@ static int vmw_dx_shader_unscrub(struct vmw_resource *res) · 54 unmodified lines
394	394	if (!list_empty(&shader->cotable_head) \|\| !shader->committed)
395	395	return 0;
396	396
397		− cmd = VMW_FIFO_RESERVE_DX(dev_priv, sizeof(*cmd), shader->ctx->id);
	397	+ cmd = VMW_CMD_CTX_RESERVE(dev_priv, sizeof(*cmd), shader->ctx->id);
398	398	if (unlikely(cmd == NULL))
399	399	return -ENOMEM;
400	400
@@ -404,7 +404,7 @@ static int vmw_dx_shader_unscrub(struct vmw_resource *res) · 3 unmodified lines
404	404	cmd->body.shid = shader->id;
405	405	cmd->body.mobid = res->backup->base.mem.start;
406	406	cmd->body.offsetInBytes = res->backup_offset;
407		− vmw_fifo_commit(dev_priv, sizeof(*cmd));
	407	+ vmw_cmd_commit(dev_priv, sizeof(*cmd));
408	408
409	409	vmw_cotable_add_resource(shader->cotable, &shader->cotable_head);
410	410
@@ -481,7 +481,7 @@ static int vmw_dx_shader_scrub(struct vmw_resource *res) · 70 unmodified lines
481	481	return 0;
482	482
483	483	WARN_ON_ONCE(!shader->committed);
484		− cmd = VMW_FIFO_RESERVE(dev_priv, sizeof(*cmd));
	484	+ cmd = VMW_CMD_RESERVE(dev_priv, sizeof(*cmd));
485	485	if (unlikely(cmd == NULL))
486	486	return -ENOMEM;
487	487
@@ -491,7 +491,7 @@ static int vmw_dx_shader_scrub(struct vmw_resource *res) · 3 unmodified lines
491	491	cmd->body.shid = res->id;
492	492	cmd->body.mobid = SVGA3D_INVALID_ID;
493	493	cmd->body.offsetInBytes = 0;
494		− vmw_fifo_commit(dev_priv, sizeof(*cmd));
	494	+ vmw_cmd_commit(dev_priv, sizeof(*cmd));
495	495	res->id = -1;
496	496	list_del_init(&shader->cotable_head);
497	497

drivers/gpu/drm/vmwgfx/vmwgfx_so.c+4−4

@@ -170,7 +170,7 @@ static int vmw_view_create(struct vmw_resource *res) · 169 unmodified lines
170	170	return 0;
171	171	}
172	172
173		− cmd = VMW_FIFO_RESERVE_DX(res->dev_priv, view->cmd_size, view->ctx->id);
	173	+ cmd = VMW_CMD_CTX_RESERVE(res->dev_priv, view->cmd_size, view->ctx->id);
174	174	if (!cmd) {
175	175	mutex_unlock(&dev_priv->binding_mutex);
176	176	return -ENOMEM;
@@ -181,7 +181,7 @@ static int vmw_view_create(struct vmw_resource *res) · 4 unmodified lines
181	181	/* Sid may have changed due to surface eviction. */
182	182	WARN_ON(view->srf->id == SVGA3D_INVALID_ID);
183	183	cmd->body.sid = view->srf->id;
184		− vmw_fifo_commit(res->dev_priv, view->cmd_size);
	184	+ vmw_cmd_commit(res->dev_priv, view->cmd_size);
185	185	res->id = view->view_id;
186	186	list_add_tail(&view->srf_head, &srf->view_list);
187	187	vmw_cotable_add_resource(view->cotable, &view->cotable_head);
@@ -213,14 +213,14 @@ static int vmw_view_destroy(struct vmw_resource *res) · 25 unmodified lines
213	213	if (!view->committed \|\| res->id == -1)
214	214	return 0;
215	215
216		− cmd = VMW_FIFO_RESERVE_DX(dev_priv, sizeof(*cmd), view->ctx->id);
	216	+ cmd = VMW_CMD_CTX_RESERVE(dev_priv, sizeof(*cmd), view->ctx->id);
217	217	if (!cmd)
218	218	return -ENOMEM;
219	219
220	220	cmd->header.id = vmw_view_destroy_cmds[view->view_type];
221	221	cmd->header.size = sizeof(cmd->body);
222	222	cmd->body.view_id = view->view_id;
223		− vmw_fifo_commit(dev_priv, sizeof(*cmd));
	223	+ vmw_cmd_commit(dev_priv, sizeof(*cmd));
224	224	res->id = -1;
225	225	list_del_init(&view->cotable_head);
226	226	list_del_init(&view->srf_head);

drivers/gpu/drm/vmwgfx/vmwgfx_stdu.c+16−16

@@ -170,7 +170,7 @@ static int vmw_stdu_define_st(struct vmw_private *dev_priv, · 169 unmodified lines
170	170	SVGA3dCmdDefineGBScreenTarget body;
171	171	} *cmd;
172	172
173		− cmd = VMW_FIFO_RESERVE(dev_priv, sizeof(*cmd));
	173	+ cmd = VMW_CMD_RESERVE(dev_priv, sizeof(*cmd));
174	174	if (unlikely(cmd == NULL))
175	175	return -ENOMEM;
176	176
@@ -188,7 +188,7 @@ static int vmw_stdu_define_st(struct vmw_private *dev_priv, · 11 unmodified lines
188	188	stdu->base.set_gui_x = cmd->body.xRoot;
189	189	stdu->base.set_gui_y = cmd->body.yRoot;
190	190
191		− vmw_fifo_commit(dev_priv, sizeof(*cmd));
	191	+ vmw_cmd_commit(dev_priv, sizeof(*cmd));
192	192
193	193	stdu->defined = true;
194	194	stdu->display_width = mode->hdisplay;
@@ -229,7 +229,7 @@ static int vmw_stdu_bind_st(struct vmw_private *dev_priv, · 34 unmodified lines
229	229	memset(&image, 0, sizeof(image));
230	230	image.sid = res ? res->id : SVGA3D_INVALID_ID;
231	231
232		− cmd = VMW_FIFO_RESERVE(dev_priv, sizeof(*cmd));
	232	+ cmd = VMW_CMD_RESERVE(dev_priv, sizeof(*cmd));
233	233	if (unlikely(cmd == NULL))
234	234	return -ENOMEM;
235	235
@@ -239,7 +239,7 @@ static int vmw_stdu_bind_st(struct vmw_private *dev_priv, · 3 unmodified lines
239	239	cmd->body.stid = stdu->base.unit;
240	240	cmd->body.image = image;
241	241
242		− vmw_fifo_commit(dev_priv, sizeof(*cmd));
	242	+ vmw_cmd_commit(dev_priv, sizeof(*cmd));
243	243
244	244	return 0;
245	245	}
@@ -293,7 +293,7 @@ static int vmw_stdu_update_st(struct vmw_private *dev_priv, · 47 unmodified lines
293	293	return -EINVAL;
294	294	}
295	295
296		− cmd = VMW_FIFO_RESERVE(dev_priv, sizeof(*cmd));
	296	+ cmd = VMW_CMD_RESERVE(dev_priv, sizeof(*cmd));
297	297	if (unlikely(cmd == NULL))
298	298	return -ENOMEM;
299	299
@@ -301,7 +301,7 @@ static int vmw_stdu_update_st(struct vmw_private *dev_priv, · 1 unmodified line
301	301	0, stdu->display_width,
302	302	0, stdu->display_height);
303	303
304		− vmw_fifo_commit(dev_priv, sizeof(*cmd));
	304	+ vmw_cmd_commit(dev_priv, sizeof(*cmd));
305	305
306	306	return 0;
307	307	}
@@ -329,7 +329,7 @@ static int vmw_stdu_destroy_st(struct vmw_private *dev_priv, · 21 unmodified lines
329	329	if (unlikely(!stdu->defined))
330	330	return 0;
331	331
332		− cmd = VMW_FIFO_RESERVE(dev_priv, sizeof(*cmd));
	332	+ cmd = VMW_CMD_RESERVE(dev_priv, sizeof(*cmd));
333	333	if (unlikely(cmd == NULL))
334	334	return -ENOMEM;
335	335
@@ -338,7 +338,7 @@ static int vmw_stdu_destroy_st(struct vmw_private *dev_priv, · 2 unmodified lines
338	338
339	339	cmd->body.stid = stdu->base.unit;
340	340
341		− vmw_fifo_commit(dev_priv, sizeof(*cmd));
	341	+ vmw_cmd_commit(dev_priv, sizeof(*cmd));
342	342
343	343	/* Force sync */
344	344	ret = vmw_fallback_wait(dev_priv, false, true, 0, false, 3*HZ);
@@ -499,7 +499,7 @@ static void vmw_stdu_bo_fifo_commit(struct vmw_kms_dirty *dirty) · 154 unmodified lines
499	499	size_t blit_size = sizeof(blit) dirty->num_hits + sizeof(*suffix);
500	500
501	501	if (!dirty->num_hits) {
502		− vmw_fifo_commit(dirty->dev_priv, 0);
	502	+ vmw_cmd_commit(dirty->dev_priv, 0);
503	503	return;
504	504	}
505	505
@@ -522,7 +522,7 @@ static void vmw_stdu_bo_fifo_commit(struct vmw_kms_dirty *dirty) · 16 unmodified lines
522	522	ddirty->top, ddirty->bottom);
523	523	}
524	524
525		− vmw_fifo_commit(dirty->dev_priv, sizeof(*cmd) + blit_size);
	525	+ vmw_cmd_commit(dirty->dev_priv, sizeof(*cmd) + blit_size);
526	526
527	527	stdu->display_srf->res.res_dirty = true;
528	528	ddirty->left = ddirty->top = S32_MAX;
@@ -628,7 +628,7 @@ static void vmw_stdu_bo_cpu_commit(struct vmw_kms_dirty *dirty) · 99 unmodified lines
628	628
629	629
630	630	dev_priv = vmw_priv(stdu->base.crtc.dev);
631		− cmd = VMW_FIFO_RESERVE(dev_priv, sizeof(*cmd));
	631	+ cmd = VMW_CMD_RESERVE(dev_priv, sizeof(*cmd));
632	632	if (!cmd)
633	633	goto out_cleanup;
634	634
@@ -636,7 +636,7 @@ static void vmw_stdu_bo_cpu_commit(struct vmw_kms_dirty *dirty) · 1 unmodified line
636	636	region.x1, region.x2,
637	637	region.y1, region.y2);
638	638
639		− vmw_fifo_commit(dev_priv, sizeof(*cmd));
	639	+ vmw_cmd_commit(dev_priv, sizeof(*cmd));
640	640	}
641	641
642	642	out_cleanup:
@@ -795,7 +795,7 @@ static void vmw_kms_stdu_surface_fifo_commit(struct vmw_kms_dirty *dirty) · 152 unmodified lines
795	795	size_t commit_size;
796	796
797	797	if (!dirty->num_hits) {
798		− vmw_fifo_commit(dirty->dev_priv, 0);
	798	+ vmw_cmd_commit(dirty->dev_priv, 0);
799	799	return;
800	800	}
801	801
@@ -817,7 +817,7 @@ static void vmw_kms_stdu_surface_fifo_commit(struct vmw_kms_dirty *dirty) · 15 unmodified lines
817	817	vmw_stdu_populate_update(update, stdu->base.unit, sdirty->left,
818	818	sdirty->right, sdirty->top, sdirty->bottom);
819	819
820		− vmw_fifo_commit(dirty->dev_priv, commit_size);
	820	+ vmw_cmd_commit(dirty->dev_priv, commit_size);
821	821
822	822	sdirty->left = sdirty->top = S32_MAX;
823	823	sdirty->right = sdirty->bottom = S32_MIN;
@@ -1713,7 +1713,7 @@ static const struct drm_crtc_helper_funcs vmw_stdu_crtc_helper_funcs = { · 889 unmodified lines
1713	1713	static int vmw_stdu_init(struct vmw_private *dev_priv, unsigned unit)
1714	1714	{
1715	1715	struct vmw_screen_target_display_unit *stdu;
1716		− struct drm_device *dev = dev_priv->dev;
	1716	+ struct drm_device *dev = &dev_priv->drm;
1717	1717	struct drm_connector *connector;
1718	1718	struct drm_encoder *encoder;
1719	1719	struct drm_plane primary, cursor;
@@ -1861,7 +1861,7 @@ static void vmw_stdu_destroy(struct vmw_screen_target_display_unit *stdu) · 141 unmodified lines
1861	1861	*/
1862	1862	int vmw_kms_stdu_init_display(struct vmw_private *dev_priv)
1863	1863	{
1864		− struct drm_device *dev = dev_priv->dev;
	1864	+ struct drm_device *dev = &dev_priv->drm;
1865	1865	int i, ret;
1866	1866
1867	1867

drivers/gpu/drm/vmwgfx/vmwgfx_streamoutput.c+4−4

@@ -99,7 +99,7 @@ static int vmw_dx_streamoutput_unscrub(struct vmw_resource *res) · 98 unmodified lines
99	99	if (!list_empty(&so->cotable_head) \|\| !so->committed )
100	100	return 0;
101	101
102		− cmd = VMW_FIFO_RESERVE_DX(dev_priv, sizeof(*cmd), so->ctx->id);
	102	+ cmd = VMW_CMD_CTX_RESERVE(dev_priv, sizeof(*cmd), so->ctx->id);
103	103	if (!cmd)
104	104	return -ENOMEM;
105	105
@@ -109,7 +109,7 @@ static int vmw_dx_streamoutput_unscrub(struct vmw_resource *res) · 3 unmodified lines
109	109	cmd->body.mobid = res->backup->base.mem.start;
110	110	cmd->body.offsetInBytes = res->backup_offset;
111	111	cmd->body.sizeInBytes = so->size;
112		− vmw_fifo_commit(dev_priv, sizeof(*cmd));
	112	+ vmw_cmd_commit(dev_priv, sizeof(*cmd));
113	113
114	114	vmw_cotable_add_resource(so->cotable, &so->cotable_head);
115	115
@@ -172,7 +172,7 @@ static int vmw_dx_streamoutput_scrub(struct vmw_resource *res) · 56 unmodified lines
172	172
173	173	WARN_ON_ONCE(!so->committed);
174	174
175		− cmd = VMW_FIFO_RESERVE_DX(dev_priv, sizeof(*cmd), so->ctx->id);
	175	+ cmd = VMW_CMD_CTX_RESERVE(dev_priv, sizeof(*cmd), so->ctx->id);
176	176	if (!cmd)
177	177	return -ENOMEM;
178	178
@@ -182,7 +182,7 @@ static int vmw_dx_streamoutput_scrub(struct vmw_resource *res) · 3 unmodified lines
182	182	cmd->body.mobid = SVGA3D_INVALID_ID;
183	183	cmd->body.offsetInBytes = 0;
184	184	cmd->body.sizeInBytes = so->size;
185		− vmw_fifo_commit(dev_priv, sizeof(*cmd));
	185	+ vmw_cmd_commit(dev_priv, sizeof(*cmd));
186	186
187	187	res->id = -1;
188	188	list_del_init(&so->cotable_head);

drivers/gpu/drm/vmwgfx/vmwgfx_surface.c+20−20

@@ -372,12 +372,12 @@ static void vmw_hw_surface_destroy(struct vmw_resource *res) · 371 unmodified lines
372	372
373	373	if (res->id != -1) {
374	374
375		− cmd = VMW_FIFO_RESERVE(dev_priv, vmw_surface_destroy_size());
	375	+ cmd = VMW_CMD_RESERVE(dev_priv, vmw_surface_destroy_size());
376	376	if (unlikely(!cmd))
377	377	return;
378	378
379	379	vmw_surface_destroy_encode(res->id, cmd);
380		− vmw_fifo_commit(dev_priv, vmw_surface_destroy_size());
	380	+ vmw_cmd_commit(dev_priv, vmw_surface_destroy_size());
381	381
382	382	/*
383	383	* used_memory_size_atomic, or separate lock
@@ -440,14 +440,14 @@ static int vmw_legacy_srf_create(struct vmw_resource *res) · 56 unmodified lines
440	440	*/
441	441
442	442	submit_size = vmw_surface_define_size(srf);
443		− cmd = VMW_FIFO_RESERVE(dev_priv, submit_size);
	443	+ cmd = VMW_CMD_RESERVE(dev_priv, submit_size);
444	444	if (unlikely(!cmd)) {
445	445	ret = -ENOMEM;
446	446	goto out_no_fifo;
447	447	}
448	448
449	449	vmw_surface_define_encode(srf, cmd);
450		− vmw_fifo_commit(dev_priv, submit_size);
	450	+ vmw_cmd_commit(dev_priv, submit_size);
451	451	vmw_fifo_resource_inc(dev_priv);
452	452
453	453	/*
@@ -492,14 +492,14 @@ static int vmw_legacy_srf_dma(struct vmw_resource *res, · 38 unmodified lines
492	492
493	493	BUG_ON(!val_buf->bo);
494	494	submit_size = vmw_surface_dma_size(srf);
495		− cmd = VMW_FIFO_RESERVE(dev_priv, submit_size);
	495	+ cmd = VMW_CMD_RESERVE(dev_priv, submit_size);
496	496	if (unlikely(!cmd))
497	497	return -ENOMEM;
498	498
499	499	vmw_bo_get_guest_ptr(val_buf->bo, &ptr);
500	500	vmw_surface_dma_encode(srf, cmd, &ptr, bind);
501	501
502		− vmw_fifo_commit(dev_priv, submit_size);
	502	+ vmw_cmd_commit(dev_priv, submit_size);
503	503
504	504	/*
505	505	* Create a fence object and fence the backup buffer.
@@ -578,12 +578,12 @@ static int vmw_legacy_srf_destroy(struct vmw_resource *res) · 72 unmodified lines
578	578	*/
579	579
580	580	submit_size = vmw_surface_destroy_size();
581		− cmd = VMW_FIFO_RESERVE(dev_priv, submit_size);
	581	+ cmd = VMW_CMD_RESERVE(dev_priv, submit_size);
582	582	if (unlikely(!cmd))
583	583	return -ENOMEM;
584	584
585	585	vmw_surface_destroy_encode(res->id, cmd);
586		− vmw_fifo_commit(dev_priv, submit_size);
	586	+ vmw_cmd_commit(dev_priv, submit_size);
587	587
588	588	/*
589	589	* Surface memory usage accounting.
@@ -1121,7 +1121,7 @@ static int vmw_gb_surface_create(struct vmw_resource *res) · 531 unmodified lines
1121	1121	submit_len = sizeof(*cmd);
1122	1122	}
1123	1123
1124		− cmd = VMW_FIFO_RESERVE(dev_priv, submit_len);
	1124	+ cmd = VMW_CMD_RESERVE(dev_priv, submit_len);
1125	1125	cmd2 = (typeof(cmd2))cmd;
1126	1126	cmd3 = (typeof(cmd3))cmd;
1127	1127	cmd4 = (typeof(cmd4))cmd;
@@ -1188,7 +1188,7 @@ static int vmw_gb_surface_create(struct vmw_resource *res) · 60 unmodified lines
1188	1188	cmd->body.size.depth = metadata->base_size.depth;
1189	1189	}
1190	1190
1191		− vmw_fifo_commit(dev_priv, submit_len);
	1191	+ vmw_cmd_commit(dev_priv, submit_len);
1192	1192
1193	1193	return 0;
1194	1194
@@ -1219,7 +1219,7 @@ static int vmw_gb_surface_bind(struct vmw_resource *res, · 24 unmodified lines
1219	1219
1220	1220	submit_size = sizeof(cmd1) + (res->backup_dirty ? sizeof(cmd2) : 0);
1221	1221
1222		− cmd1 = VMW_FIFO_RESERVE(dev_priv, submit_size);
	1222	+ cmd1 = VMW_CMD_RESERVE(dev_priv, submit_size);
1223	1223	if (unlikely(!cmd1))
1224	1224	return -ENOMEM;
1225	1225
@@ -1233,7 +1233,7 @@ static int vmw_gb_surface_bind(struct vmw_resource *res, · 7 unmodified lines
1233	1233	cmd2->header.size = sizeof(cmd2->body);
1234	1234	cmd2->body.sid = res->id;
1235	1235	}
1236		− vmw_fifo_commit(dev_priv, submit_size);
	1236	+ vmw_cmd_commit(dev_priv, submit_size);
1237	1237
1238	1238	if (res->backup->dirty && res->backup_dirty) {
1239	1239	/* We've just made a full upload. Cear dirty regions. */
@@ -1272,7 +1272,7 @@ static int vmw_gb_surface_unbind(struct vmw_resource *res, · 32 unmodified lines
1272	1272	BUG_ON(bo->mem.mem_type != VMW_PL_MOB);
1273	1273
1274	1274	submit_size = sizeof(cmd3) + (readback ? sizeof(cmd1) : sizeof(*cmd2));
1275		− cmd = VMW_FIFO_RESERVE(dev_priv, submit_size);
	1275	+ cmd = VMW_CMD_RESERVE(dev_priv, submit_size);
1276	1276	if (unlikely(!cmd))
1277	1277	return -ENOMEM;
1278	1278
@@ -1295,7 +1295,7 @@ static int vmw_gb_surface_unbind(struct vmw_resource *res, · 16 unmodified lines
1295	1295	cmd3->body.sid = res->id;
1296	1296	cmd3->body.mobid = SVGA3D_INVALID_ID;
1297	1297
1298		− vmw_fifo_commit(dev_priv, submit_size);
	1298	+ vmw_cmd_commit(dev_priv, submit_size);
1299	1299
1300	1300	/*
1301	1301	* Create a fence object and fence the backup buffer.
@@ -1328,7 +1328,7 @@ static int vmw_gb_surface_destroy(struct vmw_resource *res) · 26 unmodified lines
1328	1328	vmw_view_surface_list_destroy(dev_priv, &srf->view_list);
1329	1329	vmw_binding_res_list_scrub(&res->binding_head);
1330	1330
1331		− cmd = VMW_FIFO_RESERVE(dev_priv, sizeof(*cmd));
	1331	+ cmd = VMW_CMD_RESERVE(dev_priv, sizeof(*cmd));
1332	1332	if (unlikely(!cmd)) {
1333	1333	mutex_unlock(&dev_priv->binding_mutex);
1334	1334	return -ENOMEM;
@@ -1337,7 +1337,7 @@ static int vmw_gb_surface_destroy(struct vmw_resource *res) · 2 unmodified lines
1337	1337	cmd->header.id = SVGA_3D_CMD_DESTROY_GB_SURFACE;
1338	1338	cmd->header.size = sizeof(cmd->body);
1339	1339	cmd->body.sid = res->id;
1340		− vmw_fifo_commit(dev_priv, sizeof(*cmd));
	1340	+ vmw_cmd_commit(dev_priv, sizeof(*cmd));
1341	1341	mutex_unlock(&dev_priv->binding_mutex);
1342	1342	vmw_resource_release_id(res);
1343	1343	vmw_fifo_resource_dec(dev_priv);
@@ -1895,7 +1895,7 @@ static int vmw_surface_dirty_sync(struct vmw_resource *res) · 551 unmodified lines
1895	1895	goto out;
1896	1896
1897	1897	alloc_size = num_dirty * ((has_dx) ? sizeof(cmd1) : sizeof(cmd2));
1898		− cmd = VMW_FIFO_RESERVE(dev_priv, alloc_size);
	1898	+ cmd = VMW_CMD_RESERVE(dev_priv, alloc_size);
1899	1899	if (!cmd)
1900	1900	return -ENOMEM;
1901	1901
@@ -1931,7 +1931,7 @@ static int vmw_surface_dirty_sync(struct vmw_resource *res) · 29 unmodified lines
1931	1931	}
1932	1932
1933	1933	}
1934		− vmw_fifo_commit(dev_priv, alloc_size);
	1934	+ vmw_cmd_commit(dev_priv, alloc_size);
1935	1935	out:
1936	1936	memset(&dirty->boxes[0], 0, sizeof(dirty->boxes[0]) *
1937	1937	dirty->num_subres);
@@ -2031,14 +2031,14 @@ static int vmw_surface_clean(struct vmw_resource *res) · 93 unmodified lines
2031	2031	} *cmd;
2032	2032
2033	2033	alloc_size = sizeof(*cmd);
2034		− cmd = VMW_FIFO_RESERVE(dev_priv, alloc_size);
	2034	+ cmd = VMW_CMD_RESERVE(dev_priv, alloc_size);
2035	2035	if (!cmd)
2036	2036	return -ENOMEM;
2037	2037
2038	2038	cmd->header.id = SVGA_3D_CMD_READBACK_GB_SURFACE;
2039	2039	cmd->header.size = sizeof(cmd->body);
2040	2040	cmd->body.sid = res->id;
2041		− vmw_fifo_commit(dev_priv, alloc_size);
	2041	+ vmw_cmd_commit(dev_priv, alloc_size);
2042	2042
2043	2043	return 0;
2044	2044	}

drivers/gpu/drm/vmwgfx/vmwgfx_ttm_buffer.c+3−3

@@ -309,7 +309,7 @@ void vmw_piter_start(struct vmw_piter viter, const struct vmw_sg_table vsgt, · 308 unmodified lines
309	309	*/
310	310	static void vmw_ttm_unmap_from_dma(struct vmw_ttm_tt *vmw_tt)
311	311	{
312		− struct device *dev = vmw_tt->dev_priv->dev->dev;
	312	+ struct device *dev = vmw_tt->dev_priv->drm.dev;
313	313
314	314	dma_unmap_sgtable(dev, &vmw_tt->sgt, DMA_BIDIRECTIONAL, 0);
315	315	vmw_tt->sgt.nents = vmw_tt->sgt.orig_nents;
@@ -330,7 +330,7 @@ static void vmw_ttm_unmap_from_dma(struct vmw_ttm_tt *vmw_tt) · 14 unmodified lines
330	330	*/
331	331	static int vmw_ttm_map_for_dma(struct vmw_ttm_tt *vmw_tt)
332	332	{
333		− struct device *dev = vmw_tt->dev_priv->dev->dev;
	333	+ struct device *dev = vmw_tt->dev_priv->drm.dev;
334	334
335	335	return dma_map_sgtable(dev, &vmw_tt->sgt, DMA_BIDIRECTIONAL, 0);
336	336	}
@@ -385,7 +385,7 @@ static int vmw_ttm_map_dma(struct vmw_ttm_tt *vmw_tt) · 48 unmodified lines
385	385	sg = __sg_alloc_table_from_pages(&vmw_tt->sgt, vsgt->pages,
386	386	vsgt->num_pages, 0,
387	387	(unsigned long) vsgt->num_pages << PAGE_SHIFT,
388		− dma_get_max_seg_size(dev_priv->dev->dev),
	388	+ dma_get_max_seg_size(dev_priv->drm.dev),
389	389	NULL, 0, GFP_KERNEL);
390	390	if (IS_ERR(sg)) {
391	391	ret = PTR_ERR(sg);

drivers/pci/pci.c+10−2

@@ -1644,7 +1644,7 @@ static void pci_restore_rebar_state(struct pci_dev *pdev) · 1643 unmodified lines
1644	1644	pci_read_config_dword(pdev, pos + PCI_REBAR_CTRL, &ctrl);
1645	1645	bar_idx = ctrl & PCI_REBAR_CTRL_BAR_IDX;
1646	1646	res = pdev->resource + bar_idx;
1647		− size = ilog2(resource_size(res)) - 20;
	1647	+ size = pci_rebar_bytes_to_size(resource_size(res));
1648	1648	ctrl &= ~PCI_REBAR_CTRL_BAR_SIZE;
1649	1649	ctrl \|= size << PCI_REBAR_CTRL_BAR_SHIFT;
1650	1650	pci_write_config_dword(pdev, pos + PCI_REBAR_CTRL, ctrl);
@@ -3603,8 +3603,16 @@ u32 pci_rebar_get_possible_sizes(struct pci_dev *pdev, int bar) · 1952 unmodified lines
3603	3603	return 0;
3604	3604
3605	3605	pci_read_config_dword(pdev, pos + PCI_REBAR_CAP, &cap);
3606		− return (cap & PCI_REBAR_CAP_SIZES) >> 4;
	3606	+ cap &= PCI_REBAR_CAP_SIZES;
	3607	+
	3608	+ /* Sapphire RX 5600 XT Pulse has an invalid cap dword for BAR 0 */
	3609	+ if (pdev->vendor == PCI_VENDOR_ID_ATI && pdev->device == 0x731f &&
	3610	+ bar == 0 && cap == 0x7000)
	3611	+ cap = 0x3f000;
	3612	+
	3613	+ return cap >> 4;
3607	3614	}
	3615	+EXPORT_SYMBOL(pci_rebar_get_possible_sizes);
3608	3616
3609	3617	/**
3610	3618	* pci_rebar_get_current_size - get the current size of a BAR

drivers/pci/pci.h+0−1

@@ -630,7 +630,6 @@ int acpi_get_rc_resources(struct device dev, const char hid, u16 segment, · 629 unmodified lines
630	630	struct resource *res);
631	631	#endif
632	632
633		−u32 pci_rebar_get_possible_sizes(struct pci_dev *pdev, int bar);
634	633	int pci_rebar_get_current_size(struct pci_dev *pdev, int bar);
635	634	int pci_rebar_set_size(struct pci_dev *pdev, int bar, int size);
636	635	static inline u64 pci_rebar_size_to_bytes(int size)

drivers/video/fbdev/omap2/omapfb/displays/Kconfig+1−0

@@ -43,6 +43,7 @@ config FB_OMAP2_PANEL_DPI · 42 unmodified lines
43	43	config FB_OMAP2_PANEL_DSI_CM
44	44	tristate "Generic DSI Command Mode Panel"
45	45	depends on BACKLIGHT_CLASS_DEVICE
	46	+ depends on DRM_PANEL_DSI_CM = n
46	47	help
47	48	Driver for generic DSI command mode panels.
48	49

include/drm/drm_agpsupport.h+0−18

@@ -28,10 +28,6 @@ struct drm_agp_head { · 27 unmodified lines
28	28
29	29	#if IS_ENABLED(CONFIG_AGP)
30	30
31		−void drm_free_agp(struct agp_memory * handle, int pages);
32		−int drm_bind_agp(struct agp_memory * handle, unsigned int start);
33		−int drm_unbind_agp(struct agp_memory * handle);
34		−
35	31	struct drm_agp_head drm_agp_init(struct drm_device dev);
36	32	void drm_legacy_agp_clear(struct drm_device *dev);
37	33	int drm_agp_acquire(struct drm_device *dev);
@@ -61,20 +57,6 @@ int drm_agp_bind_ioctl(struct drm_device dev, void data, · 23 unmodified lines
61	57
62	58	#else /* CONFIG_AGP */
63	59
64		−static inline void drm_free_agp(struct agp_memory * handle, int pages)
65		−{
66		−}
67		−
68		−static inline int drm_bind_agp(struct agp_memory * handle, unsigned int start)
69		−{
70		− return -ENODEV;
71		−}
72		−
73		−static inline int drm_unbind_agp(struct agp_memory * handle)
74		−{
75		− return -ENODEV;
76		−}
77		−
78	60	static inline struct drm_agp_head drm_agp_init(struct drm_device dev)
79	61	{
80	62	return NULL;

include/drm/drm_crtc.h+1−1

@@ -1232,7 +1232,7 @@ void __drmm_crtc_alloc_with_planes(struct drm_device dev, · 1231 unmodified lines
1232	1232	const char *name, ...);
1233	1233
1234	1234	/**
1235		− * drm_crtc_alloc_with_planes - Allocate and initialize a new CRTC object with
	1235	+ * drmm_crtc_alloc_with_planes - Allocate and initialize a new CRTC object with
1236	1236	* specified primary and cursor planes.
1237	1237	* @dev: DRM device
1238	1238	* @type: the type of the struct which contains struct &drm_crtc

include/drm/drm_device.h+5−4

@@ -282,10 +282,6 @@ struct drm_device { · 281 unmodified lines
282	282	/** @pdev: PCI device structure */
283	283	struct pci_dev *pdev;
284	284
285		−#ifdef __alpha__
286		− /** @hose: PCI hose, only used on ALPHA platforms. */
287		− struct pci_controller *hose;
288		−#endif
289	285	/** @num_crtcs: Number of CRTCs on this device */
290	286	unsigned int num_crtcs;
291	287
@@ -328,6 +324,11 @@ struct drm_device { · 36 unmodified lines
328	324	/* List of devices per driver for stealth attach cleanup */
329	325	struct list_head legacy_dev_list;
330	326
	327	+#ifdef __alpha__
	328	+ /** @hose: PCI hose, only used on ALPHA platforms. */
	329	+ struct pci_controller *hose;
	330	+#endif
	331	+
331	332	/* Context handle management - linked list of context handles */
332	333	struct list_head ctxlist;
333	334

include/drm/drm_mipi_dbi.h+1−1

@@ -172,7 +172,7 @@ int mipi_dbi_buf_copy(void dst, struct drm_framebuffer fb, · 171 unmodified lines
172	172	* mipi_dbi_command - MIPI DCS command with optional parameter(s)
173	173	* @dbi: MIPI DBI structure
174	174	* @cmd: Command
175		− * @seq...: Optional parameter(s)
	175	+ * @seq: Optional parameter(s)
176	176	*
177	177	* Send MIPI DCS command to the controller. Use mipi_dbi_command_read() for
178	178	* get/read.

include/drm/drm_property.h+1−1

@@ -114,7 +114,7 @@ struct drm_property { · 113 unmodified lines
114	114	* by the property. Bitmask properties are created using
115	115	* drm_property_create_bitmask().
116	116	*
117		− * DRM_MODE_PROB_OBJECT
	117	+ * DRM_MODE_PROP_OBJECT
118	118	* Object properties are used to link modeset objects. This is used
119	119	* extensively in the atomic support to create the display pipeline,
120	120	* by linking &drm_framebuffer to &drm_plane, &drm_plane to

include/drm/ttm/ttm_resource.h+4−0

@@ -190,6 +190,10 @@ struct ttm_resource { · 189 unmodified lines
190	190	static inline void
191	191	ttm_resource_manager_set_used(struct ttm_resource_manager *man, bool used)
192	192	{
	193	+ int i;
	194	+
	195	+ for (i = 0; i < TTM_MAX_BO_PRIORITY; i++)
	196	+ WARN_ON(!list_empty(&man->lru[i]));
193	197	man->use_type = used;
194	198	}
195	199

include/linux/dma-buf.h+6−0

@@ -154,6 +154,12 @@ struct dma_buf_ops { · 153 unmodified lines
154	154	* On failure, returns a negative error value wrapped into a pointer.
155	155	* May also return -EINTR when a signal was received while being
156	156	* blocked.
	157	+ *
	158	+ * Note that exporters should not try to cache the scatter list, or
	159	+ * return the same one for multiple calls. Caching is done either by the
	160	+ * DMA-BUF code (for non-dynamic importers) or the importer. Ownership
	161	+ * of the scatter list is transferred to the caller, and returned by
	162	+ * @unmap_dma_buf.
157	163	*/
158	164	struct sg_table * (map_dma_buf)(struct dma_buf_attachment ,
159	165	enum dma_data_direction);

include/linux/pci.h+9−0

@@ -1232,6 +1232,15 @@ void pci_update_resource(struct pci_dev *dev, int resno); · 1231 unmodified lines
1232	1232	int __must_check pci_assign_resource(struct pci_dev *dev, int i);
1233	1233	int __must_check pci_reassign_resource(struct pci_dev *dev, int i, resource_size_t add_size, resource_size_t align);
1234	1234	void pci_release_resource(struct pci_dev *dev, int resno);
	1235	+static inline int pci_rebar_bytes_to_size(u64 bytes)
	1236	+{
	1237	+ bytes = roundup_pow_of_two(bytes);
	1238	+
	1239	+ /* Return BAR size as defined in the resizable BAR specification */
	1240	+ return max(ilog2(bytes), 20) - 20;
	1241	+}
	1242	+
	1243	+u32 pci_rebar_get_possible_sizes(struct pci_dev *pdev, int bar);
1235	1244	int __must_check pci_resize_resource(struct pci_dev *dev, int i, int size);
1236	1245	int pci_select_bars(struct pci_dev *dev, unsigned long flags);
1237	1246	bool pci_device_is_present(struct pci_dev *pdev);

include/linux/vgaarb.h+3−3

@@ -121,9 +121,9 @@ extern struct pci_dev *vga_default_device(void); · 120 unmodified lines
121	121	extern void vga_set_default_device(struct pci_dev *pdev);
122	122	extern int vga_remove_vgacon(struct pci_dev *pdev);
123	123	#else
124		−static inline struct pci_dev *vga_default_device(void) { return NULL; };
125		−static inline void vga_set_default_device(struct pci_dev *pdev) { };
126		−static inline int vga_remove_vgacon(struct pci_dev *pdev) { return 0; };
	124	+static inline struct pci_dev *vga_default_device(void) { return NULL; }
	125	+static inline void vga_set_default_device(struct pci_dev *pdev) { }
	126	+static inline int vga_remove_vgacon(struct pci_dev *pdev) { return 0; }
127	127	#endif
128	128
129	129	/*

include/uapi/drm/drm_fourcc.h+2−2

@@ -1036,9 +1036,9 @@ drm_fourcc_canonicalize_nvidia_format_mod(__u64 modifier) · 1035 unmodified lines
1036	1036	* Not all combinations are valid, and different SoCs may support different
1037	1037	* combinations of layout and options.
1038	1038	*/
1039		−#define __fourcc_mod_amlogic_layout_mask 0xf
	1039	+#define __fourcc_mod_amlogic_layout_mask 0xff
1040	1040	#define __fourcc_mod_amlogic_options_shift 8
1041		−#define __fourcc_mod_amlogic_options_mask 0xf
	1041	+#define __fourcc_mod_amlogic_options_mask 0xff
1042	1042
1043	1043	#define DRM_FORMAT_MOD_AMLOGIC_FBC(__layout, __options) \
1044	1044	fourcc_mod_code(AMLOGIC, \