All device tree probing omap SoCs only have device drivers that are using Linux dmaengine API with the IRQENABLE_L1 interrupts. Only omap1 is still using old legacy dma. This means we can remove the legacy sdma interrupt handling for IRQENABLE_L0, and only rely on the dmaengine driver using IRQENABLE_L1. The legacy code still allocates the channels, but that will be deal with in the following patches.
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| @@ -129,7 +129,6 @@ · 128 unmodified lines | ||
| 129 | 129 | #define IS_WORD_16 BIT(0xd) |
| 130 | 130 | #define ENABLE_16XX_MODE BIT(0xe) |
| 131 | 131 | #define HS_CHANNELS_RESERVED BIT(0xf) |
| 132 | −#define DMA_ENGINE_HANDLE_IRQ BIT(0x10) | |
| 133 | 132 | |
| 134 | 133 | /* Defines for DMA Capabilities */ |
| 135 | 134 | #define DMA_HAS_TRANSPARENT_CAPS (0x1 << 18) |
| @@ -239,9 +238,6 @@ struct omap_dma_lch { · 103 unmodified lines | ||
| 239 | 238 | void (*callback)(int lch, u16 ch_status, void *data); |
| 240 | 239 | void *data; |
| 241 | 240 | long flags; |
| 242 | − /* required for Dynamic chaining */ | |
| 243 | − int prev_linked_ch; | |
| 244 | − int next_linked_ch; | |
| 245 | 241 | int state; |
| 246 | 242 | int chain_id; |
| 247 | 243 | int status; |