ASoC: adau1372: fixes after debugging custom board

Merge series from Maarten Zanders <maarten.zanders@mind.be>: A collection of fixes and improvements for the adau1372 driver.

Mark Brown committed 3 years ago

Commit 79dfd9d2 parents d067b33 cd887a7378 files · +39940 −38203Browse files

Unified · Split

378 files

CREDITS +5 −0
Documentation/dev-tools/kmsan.rst +1 −0
Documentation/devicetree/bindings/hwlock/qcom-hwspinlock.yaml +21 −8
Documentation/devicetree/bindings/net/engleder,tsnep.yaml +1 −1
Documentation/virt/kvm/devices/vm.rst +3 −0
MAINTAINERS +2 −5
Makefile +1 −1
arch/arm64/include/asm/cputype.h +1 −1
arch/arm64/include/asm/syscall_wrapper.h +1 −1
arch/arm64/kernel/efi.c +34 −18
arch/arm64/mm/pageattr.c +3 −2
arch/mips/alchemy/common/gpiolib.c +1 −1
arch/mips/boot/compressed/decompress.c +1 −0
arch/mips/include/asm/fw/fw.h +1 −1
arch/mips/kernel/jump_label.c +1 −1
arch/mips/kernel/relocate_kernel.S +5 −10
arch/mips/loongson64/reset.c +10 −0
arch/mips/pic32/pic32mzda/early_console.c +6 −7
arch/mips/pic32/pic32mzda/init.c +1 −1
arch/riscv/boot/dts/sifive/hifive-unleashed-a00.dts +38 −0
arch/riscv/kernel/process.c +2 −0
arch/riscv/kernel/setup.c +1 −0
arch/riscv/kernel/vdso/Makefile +4 −1
arch/riscv/kernel/vdso/vdso.lds.S +2 −0
arch/riscv/mm/init.c +0 −1
arch/s390/Kconfig +3 −3
arch/s390/Makefile +0 −2
arch/s390/boot/Makefile +1 −2
arch/s390/boot/startup.c +1 −2
arch/s390/configs/btf.config +1 −0
arch/s390/configs/debug_defconfig +32 −33
arch/s390/configs/defconfig +33 −34
arch/s390/configs/kasan.config +3 −0
arch/s390/configs/zfcpdump_defconfig +0 −1
arch/s390/kvm/kvm-s390.c +17 −9
arch/s390/kvm/kvm-s390.h +0 −1
arch/s390/kvm/pci.c +1 −1
arch/x86/hyperv/hv_init.c +10 −9
arch/x86/include/asm/kvm_host.h +6 −1
arch/x86/include/asm/spec-ctrl.h +5 −5
arch/x86/kernel/asm-offsets.c +0 −6
arch/x86/kernel/cpu/bugs.c +4 −11
arch/x86/kernel/traps.c +7 −0
arch/x86/kvm/.gitignore +2 −0
arch/x86/kvm/Makefile +12 −0
arch/x86/kvm/kvm-asm-offsets.c +29 −0
arch/x86/kvm/mmu/mmu.c +2 −2
arch/x86/kvm/pmu.c +1 −1
arch/x86/kvm/svm/pmu.c +4 −3
arch/x86/kvm/svm/sev.c +3 −3
arch/x86/kvm/svm/svm.c +36 −69
arch/x86/kvm/svm/svm.h +5 −6
arch/x86/kvm/svm/svm_ops.h +0 −5
arch/x86/kvm/svm/vmenter.S +209 −51
arch/x86/kvm/vmx/pmu_intel.c +2 −2
arch/x86/kvm/vmx/vmenter.S +1 −1
arch/x86/kvm/x86.c +10 −15
arch/x86/lib/usercopy.c +3 −0
arch/x86/mm/hugetlbpage.c +4 −0
block/bfq-cgroup.c +4 −0
block/sed-opal.c +28 −4
drivers/acpi/video_detect.c +32 −9
drivers/ata/libata-scsi.c +13 −0
drivers/ata/libata-transport.c +15 −4
drivers/clocksource/hyperv_timer.c +15 −14
drivers/dma/apple-admac.c +1 −1
drivers/dma/at_hdmac.c +60 −93
drivers/dma/at_hdmac_regs.h +5 −5
drivers/dma/idxd/cdev.c +18 −0
drivers/dma/idxd/device.c +17 −9
drivers/dma/idxd/idxd.h +32 −0
drivers/dma/idxd/init.c +2 −2
drivers/dma/idxd/sysfs.c +1 −1
drivers/dma/mv_xor_v2.c +1 −0
drivers/dma/pxa_dma.c +2 −2
drivers/dma/stm32-dma.c +6 −8
drivers/dma/stm32-mdma.c +1 −0
drivers/dma/ti/k3-udma-glue.c +3 −0
drivers/firmware/efi/libstub/Makefile +1 −1
drivers/firmware/efi/libstub/arm64-stub.c +16 −1
drivers/firmware/efi/libstub/efistub.h +28 −0
drivers/firmware/efi/libstub/smbios.c +48 −0
drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c +1 −0
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c +0 −26
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h +41 −0
drivers/gpu/drm/amd/amdgpu/amdgpu_vm_pt.c +2 −0
drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c +1 −1
drivers/gpu/drm/amd/amdkfd/kfd_chardev.c +15 −19
drivers/gpu/drm/amd/amdkfd/kfd_events.c +1 −2
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +4 −3
drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c +16 −16
drivers/gpu/drm/amd/display/dc/dc.h +1 −0
drivers/gpu/drm/amd/display/dc/dcn314/dcn314_dio_stream_encoder.c +18 −6
drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.c +1 −0
drivers/gpu/drm/amd/display/dc/dcn321/dcn321_resource.c +1 −0
drivers/gpu/drm/amd/display/dc/dml/dcn314/dcn314_fpu.c +2 −2
drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c +2 −0
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c +5 −0
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.h +3 −0
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c +11 −3
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.h +2 −1
drivers/gpu/drm/amd/display/dc/dml/dcn321/dcn321_fpu.c +2 −0
drivers/gpu/drm/amd/display/dc/dml/display_mode_structs.h +1 −0
drivers/gpu/drm/amd/display/dc/gpio/dcn32/hw_factory_dcn32.c +14 −0
drivers/gpu/drm/amd/display/dc/gpio/hw_ddc.c +6 −3
drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_thermal.c +12 −13
drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_4_ppsmc.h +7 −8
drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c +3 −1
drivers/gpu/drm/drm_panel_orientation_quirks.c +12 −0
drivers/gpu/drm/i915/display/intel_psr.c +4 −1
drivers/gpu/drm/i915/gem/i915_gem_dmabuf.c +2 −2
drivers/gpu/drm/i915/gem/i915_gem_shmem.c +2 −2
drivers/gpu/drm/i915/gem/i915_gem_userptr.c +3 −2
drivers/gpu/drm/panfrost/panfrost_mmu.c +10 −1
drivers/gpu/drm/rcar-du/Kconfig +9 −4
drivers/gpu/drm/vc4/vc4_drv.c +6 −1
drivers/gpu/drm/vc4/vc4_hdmi.c +36 −11
drivers/gpu/drm/vc4/vc4_hdmi.h +1 −0
drivers/hid/hid-asus.c +1 −3
drivers/hid/hid-hyperv.c +1 −1
drivers/hid/wacom_wac.c +6 −5
drivers/hv/hv_balloon.c +1 −1
drivers/hwspinlock/qcom_hwspinlock.c +32 −10
drivers/mmc/host/sdhci-brcmstb.c +2 −1
drivers/mmc/host/sdhci-cqhci.h +24 −0
drivers/mmc/host/sdhci-esdhc-imx.c +4 −3
drivers/mmc/host/sdhci-of-arasan.c +2 −1
drivers/mmc/host/sdhci-tegra.c +2 −1
drivers/mmc/host/sdhci_am654.c +4 −3
drivers/net/can/at91_can.c +1 −1
drivers/net/can/c_can/c_can_main.c +1 −1
drivers/net/can/can327.c +1 −1
drivers/net/can/cc770/cc770.c +1 −1
drivers/net/can/ctucanfd/ctucanfd_base.c +1 −1
drivers/net/can/dev/skb.c +1 −9
drivers/net/can/flexcan/flexcan-core.c +1 −1
drivers/net/can/grcan.c +1 −1
drivers/net/can/ifi_canfd/ifi_canfd.c +1 −1
drivers/net/can/janz-ican3.c +1 −1
drivers/net/can/kvaser_pciefd.c +1 −1
drivers/net/can/m_can/m_can.c +1 −1
drivers/net/can/mscan/mscan.c +1 −1
drivers/net/can/pch_can.c +1 −1
drivers/net/can/peak_canfd/peak_canfd.c +1 −1
drivers/net/can/rcar/rcar_can.c +1 −1
drivers/net/can/rcar/rcar_canfd.c +5 −10
drivers/net/can/sja1000/sja1000.c +1 −1
drivers/net/can/slcan/slcan-core.c +1 −1
drivers/net/can/softing/softing_main.c +1 −1
drivers/net/can/spi/hi311x.c +1 −1
drivers/net/can/spi/mcp251x.c +1 −1
drivers/net/can/spi/mcp251xfd/mcp251xfd-tx.c +1 −1
drivers/net/can/sun4i_can.c +1 −1
drivers/net/can/ti_hecc.c +1 −1
drivers/net/can/usb/ems_usb.c +1 −1
drivers/net/can/usb/esd_usb.c +1 −1
drivers/net/can/usb/etas_es58x/es58x_core.c +1 −1
drivers/net/can/usb/gs_usb.c +1 −1
drivers/net/can/usb/kvaser_usb/kvaser_usb_core.c +1 −1
drivers/net/can/usb/mcba_usb.c +1 −1
drivers/net/can/usb/peak_usb/pcan_usb_core.c +1 −1
drivers/net/can/usb/ucan.c +1 −1
drivers/net/can/usb/usb_8dev.c +1 −1
drivers/net/can/xilinx_can.c +1 −1
drivers/net/ethernet/apm/xgene/xgene_enet_main.c +3 −1
drivers/net/ethernet/aquantia/atlantic/aq_macsec.c +2 −0
drivers/net/ethernet/aquantia/atlantic/macsec/macsec_api.c +11 −7
drivers/net/ethernet/broadcom/Kconfig +1 −1
drivers/net/ethernet/broadcom/bnxt/bnxt.c +45 −9
drivers/net/ethernet/broadcom/bnxt/bnxt.h +1 −0
drivers/net/ethernet/broadcom/bnxt/bnxt_ethtool.c +1 −1
drivers/net/ethernet/broadcom/bnxt/bnxt_hwrm.c +2 −1
drivers/net/ethernet/chelsio/cxgb3/cxgb3_main.c +1 −0
drivers/net/ethernet/chelsio/cxgb4vf/cxgb4vf_main.c +1 −1
drivers/net/ethernet/freescale/fman/mac.c +9 −0
drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c +5 −3
drivers/net/ethernet/ibm/ibmveth.c +2 −1
drivers/net/ethernet/ibm/ibmveth.h +1 −0
drivers/net/ethernet/intel/iavf/iavf_virtchnl.c +2 −0
drivers/net/ethernet/intel/ice/ice_base.c +1 −1
drivers/net/ethernet/intel/ice/ice_lib.c +25 −0
drivers/net/ethernet/intel/ice/ice_lib.h +1 −0
drivers/net/ethernet/intel/ice/ice_vf_lib.c +4 −1
drivers/net/ethernet/marvell/mv643xx_eth.c +1 −0
drivers/net/ethernet/marvell/octeontx2/Kconfig +2 −0
drivers/net/ethernet/marvell/octeontx2/nic/otx2_common.c +1 −0
drivers/net/ethernet/marvell/octeontx2/nic/otx2_pf.c +105 −30
drivers/net/ethernet/marvell/octeontx2/nic/otx2_struct.h +57 −0
drivers/net/ethernet/marvell/octeontx2/nic/otx2_txrx.c +19 −13
drivers/net/ethernet/marvell/octeontx2/nic/otx2_txrx.h +1 −0
drivers/net/ethernet/marvell/prestera/prestera_rxtx.c +6 −1
drivers/net/ethernet/mediatek/mtk_star_emac.c +2 −0
drivers/net/ethernet/mellanox/mlx5/core/cmd.c +8 −3
drivers/net/ethernet/mellanox/mlx5/core/en/rep/bridge.c +31 −0
drivers/net/ethernet/mellanox/mlx5/core/en/tc/act/act.c +32 −60
drivers/net/ethernet/mellanox/mlx5/core/en/txrx.h +23 −1
drivers/net/ethernet/mellanox/mlx5/core/en/xdp.c +2 −2
drivers/net/ethernet/mellanox/mlx5/core/en_main.c +7 −0
drivers/net/ethernet/mellanox/mlx5/core/en_rx.c +14 −13
drivers/net/ethernet/mellanox/mlx5/core/en_tc.c +6 −8
drivers/net/ethernet/mellanox/mlx5/core/en_tx.c +5 −0
drivers/net/ethernet/mellanox/mlx5/core/eswitch.c +8 −6
drivers/net/ethernet/mellanox/mlx5/core/eswitch_offloads.c +3 −15
drivers/net/ethernet/mellanox/mlx5/core/eswitch_offloads_termtbl.c +8 −6
drivers/net/ethernet/mellanox/mlx5/core/fw_reset.c +2 −1
drivers/net/ethernet/neterion/s2io.c +20 −9
drivers/net/ethernet/ni/nixge.c +1 −0
drivers/net/ethernet/stmicro/stmmac/dwmac-intel.c +9 −2
drivers/net/ethernet/stmicro/stmmac/dwmac-loongson.c +31 −8
drivers/net/ethernet/stmicro/stmmac/dwmac-meson8b.c +3 −5
drivers/net/ethernet/sunplus/spl2sw_driver.c +0 −1
drivers/net/ethernet/ti/am65-cpsw-nuss.c +1 −1
drivers/net/ethernet/ti/cpsw.c +2 −0
drivers/net/ethernet/tundra/tsi108_eth.c +4 −1
drivers/net/hamradio/bpqether.c +1 −1
drivers/net/macsec.c +17 −33
drivers/net/macvlan.c +3 −1
drivers/net/phy/mscc/mscc_macsec.c +1 −0
drivers/net/tun.c +13 −5
drivers/net/wan/lapbether.c +2 −1
drivers/net/wireless/ath/ath11k/qmi.h +1 −1
drivers/net/wireless/ath/ath11k/reg.c +1 −5
drivers/net/wireless/broadcom/brcm80211/brcmfmac/fweh.c +4 −0
drivers/net/wireless/cisco/airo.c +14 −4
drivers/net/wireless/mac80211_hwsim.c +5 −0
drivers/net/wireless/ralink/rt2x00/rt2400pci.c +4 −4
drivers/net/wireless/ralink/rt2x00/rt2400pci.h +1 −1
drivers/net/wireless/ralink/rt2x00/rt2500pci.c +4 −4
drivers/net/wireless/ralink/rt2x00/rt2500pci.h +1 −1
drivers/net/wireless/ralink/rt2x00/rt2500usb.c +4 −4
drivers/net/wireless/ralink/rt2x00/rt2500usb.h +1 −1
drivers/net/wireless/ralink/rt2x00/rt2800lib.c +30 −30
drivers/net/wireless/ralink/rt2x00/rt2800lib.h +4 −4
drivers/net/wireless/ralink/rt2x00/rt2x00usb.c +3 −3
drivers/net/wireless/ralink/rt2x00/rt61pci.c +2 −2
drivers/net/wireless/ralink/rt2x00/rt61pci.h +1 −1
drivers/net/wireless/ralink/rt2x00/rt73usb.c +2 −2
drivers/net/wireless/ralink/rt2x00/rt73usb.h +1 −1
drivers/net/wwan/Kconfig +1 −1
drivers/net/wwan/iosm/iosm_ipc_coredump.c +1 −0
drivers/net/wwan/iosm/iosm_ipc_devlink.c +1 −0
drivers/net/wwan/iosm/iosm_ipc_imem_ops.c +8 −0
drivers/net/wwan/iosm/iosm_ipc_mux.h +1 −0
drivers/net/wwan/iosm/iosm_ipc_pcie.c +15 −3
drivers/net/wwan/iosm/iosm_ipc_wwan.c +7 −36
drivers/net/wwan/mhi_wwan_mbim.c +1 −0
drivers/nvme/host/core.c +1 −2
drivers/nvme/host/pci.c +0 −2
drivers/nvme/target/configfs.c +6 −2
drivers/pci/controller/pci-hyperv.c +16 −6
drivers/phy/qualcomm/phy-qcom-qmp-combo.c +1 −1
drivers/phy/ralink/phy-mt7621-pci.c +2 −1
drivers/phy/st/phy-stm32-usbphyc.c +2 −0
drivers/phy/sunplus/phy-sunplus-usb2.c +2 −2
drivers/phy/tegra/xusb.c +16 −4
drivers/platform/x86/hp-wmi.c +10 −2
drivers/platform/x86/ideapad-laptop.c +24 −1
drivers/platform/x86/intel/hid.c +3 −0
drivers/platform/x86/intel/pmt/class.c +30 −1
drivers/platform/x86/p2sb.c +6 −9
drivers/platform/x86/touchscreen_dmi.c +25 −0
drivers/s390/crypto/zcrypt_msgtype6.c +15 −6
drivers/scsi/ibmvscsi/ibmvfc.c +11 −3
drivers/scsi/scsi_debug.c +7 −0
drivers/scsi/scsi_transport_sas.c +9 −4
drivers/soundwire/intel.c +1 −0
drivers/soundwire/qcom.c +9 −0
drivers/spi/spi-amd.c +1 −1
drivers/spi/spi-intel.c +4 −4
drivers/spi/spi-meson-spicc.c +22 −2
drivers/spi/spi-mt65xx.c +13 −10
drivers/spi/spi-stm32.c +2 −1
drivers/spi/spi-tegra210-quad.c +6 −0
fs/btrfs/compression.c +8 −6
fs/btrfs/ctree.c +16 −0
fs/btrfs/ctree.h +7 −4
fs/btrfs/disk-io.c +3 −1
fs/btrfs/scrub.c +1 −8
fs/btrfs/tests/btrfs-tests.c +1 −1
fs/btrfs/volumes.c +29 −10
fs/btrfs/volumes.h +1 −1
fs/btrfs/zoned.c +40 −0
fs/btrfs/zoned.h +11 −0
fs/erofs/zdata.c +11 −7
fs/hugetlbfs/inode.c +6 −7
fs/nfsd/filecache.c +1 −0
fs/nfsd/nfs4state.c +1 −0
fs/nilfs2/segment.c +8 −7
fs/nilfs2/super.c +0 −2
fs/nilfs2/the_nilfs.c +0 −2
fs/udf/namei.c +1 −1
fs/userfaultfd.c +3 −0
include/asm-generic/hyperv-tlfs.h +9 −0
include/asm-generic/vmlinux.lds.h +1 −1
include/linux/can/dev.h +16 −0
include/linux/efi.h +1 −0
include/linux/maple_tree.h +7 −0
include/linux/skmsg.h +1 −1
include/linux/slab.h +0 −23
include/uapi/drm/panfrost_drm.h +1 −1
include/uapi/linux/audit.h +1 −1
include/uapi/linux/capability.h +1 −1
include/uapi/linux/idxd.h +1 −0
include/uapi/linux/in.h +1 −0
include/uapi/linux/io_uring.h +1 −1
io_uring/io_uring.c +8 −2
io_uring/kbuf.c +2 −0
io_uring/poll.c +19 −12
kernel/bpf/verifier.c +13 −4
lib/Kconfig.debug +5 −1
lib/Kconfig.kmsan +1 −0
lib/Makefile +1 −0
lib/maple_tree.c +40 −18
lib/test_maple_tree.c +1193 −36733
mm/damon/dbgfs.c +7 −0
mm/huge_memory.c +6 −3
mm/hugetlb.c +4 −0
mm/hugetlb_vmemmap.c +1 −0
mm/kmsan/kmsan.h +2 −0
mm/memory-failure.c +4 −1
mm/memremap.c +1 −0
mm/mmap.c +5 −1
mm/slab_common.c +4 −20
mm/userfaultfd.c +1 −1
net/can/af_can.c +2 −1
net/can/isotp.c +38 −33
net/can/j1939/main.c +3 −0
net/core/skbuff.c +19 −17
net/core/skmsg.c +2 −5
net/core/sock_map.c +4 −3
net/ipv4/tcp.c +1 −1
net/ipv4/tcp_bpf.c +5 −3
net/ipv6/addrlabel.c +1 −0
net/mac80211/main.c +6 −2
net/mac80211/mesh_pathtbl.c +1 −1
net/mac80211/s1g.c +3 −0
net/mac80211/tx.c +5 −0
net/mctp/af_mctp.c +3 −1
net/mctp/route.c +1 −1
net/netfilter/nf_tables_api.c +2 −1
net/netfilter/nfnetlink.c +1 −0
net/sctp/outqueue.c +8 −5
net/tipc/netlink_compat.c +1 −1
net/wireless/reg.c +9 −3
net/wireless/scan.c +3 −1
net/wireless/util.c +4 −2
scripts/min-tool-version.sh +1 −1
sound/arm/pxa2xx-ac97-lib.c +3 −1
sound/core/memalloc.c +8 −7
sound/hda/hdac_sysfs.c +3 −1
sound/pci/hda/hda_intel.c +7 −4
sound/pci/hda/patch_ca0132.c +1 −0
sound/pci/hda/patch_realtek.c +2 −0
sound/soc/codecs/adau1372.c +17 −14
sound/usb/card.c +20 −9
sound/usb/endpoint.c +2 −1
sound/usb/quirks-table.h +4 −0
sound/usb/quirks.c +6 −41
sound/usb/usbaudio.h +3 −0
tools/bpf/bpftool/common.c +3 −0
tools/include/uapi/linux/in.h +1 −0
tools/include/uapi/linux/stddef.h +47 −0
tools/kvm/kvm_stat/kvm_stat +83 −15
tools/perf/.gitignore +1 −0
tools/perf/tests/shell/test_brstack.sh +4 −1
tools/perf/util/parse-branch-options.c +3 −1
tools/perf/util/stat-display.c +4 −2
tools/testing/radix-tree/.gitignore +1 −0
tools/testing/radix-tree/Makefile +16 −3
tools/testing/radix-tree/generated/autoconf.h +1 −1
tools/testing/radix-tree/linux.c +4 −0
tools/testing/radix-tree/maple.c +35770 −0
tools/testing/selftests/bpf/verifier/ref_tracking.c +36 −0
tools/testing/selftests/net/io_uring_zerocopy_tx.sh +1 −1
tools/testing/selftests/net/udpgro.sh +2 −2
tools/testing/selftests/net/udpgro_bench.sh +1 −1
tools/testing/selftests/net/udpgro_frglist.sh +1 −1
tools/testing/selftests/netfilter/rpath.sh +8 −6

CREDITS+5−0

@@ -918,6 +918,11 @@ S: Ottawa, Ontario · 917 unmodified lines
918	918	S: K1N 6Z9
919	919	S: CANADA
920	920
	921	+N: Vivien Didelot
	922	+E: vivien.didelot@gmail.com
	923	+D: DSA framework and MV88E6XXX driver
	924	+S: Montreal, Quebec, Canada
	925	+
921	926	N: Jeff Dike
922	927	E: jdike@karaya.com
923	928	W: http://user-mode-linux.sourceforge.net

Documentation/dev-tools/kmsan.rst+1−0

@@ -67,6 +67,7 @@ uninitialized in the local variable, as well as the stack where the value was · 66 unmodified lines
67	67	copied to another memory location before use.
68	68
69	69	A use of uninitialized value ``v`` is reported by KMSAN in the following cases:
	70	+
70	71	- in a condition, e.g. ``if (v) { ... }``;
71	72	- in an indexing or pointer dereferencing, e.g. ``array[v]`` or ``*v``;
72	73	- when it is copied to userspace or hardware, e.g. ``copy_to_user(..., &v, ...)``;

Documentation/devicetree/bindings/hwlock/qcom-hwspinlock.yaml+21−8

@@ -15,9 +15,22 @@ description: · 14 unmodified lines
15	15
16	16	properties:
17	17	compatible:
18		− enum:
19		− - qcom,sfpb-mutex
20		− - qcom,tcsr-mutex
	18	+ oneOf:
	19	+ - enum:
	20	+ - qcom,sfpb-mutex
	21	+ - qcom,tcsr-mutex
	22	+ - items:
	23	+ - enum:
	24	+ - qcom,apq8084-tcsr-mutex
	25	+ - qcom,ipq6018-tcsr-mutex
	26	+ - qcom,msm8226-tcsr-mutex
	27	+ - qcom,msm8994-tcsr-mutex
	28	+ - const: qcom,tcsr-mutex
	29	+ - items:
	30	+ - enum:
	31	+ - qcom,msm8974-tcsr-mutex
	32	+ - const: qcom,tcsr-mutex
	33	+ - const: syscon
21	34
22	35	reg:
23	36	maxItems: 1
@@ -34,9 +47,9 @@ additionalProperties: false · 10 unmodified lines
34	47
35	48	examples:
36	49	- \|
37		− tcsr_mutex: hwlock@1f40000 {
38		− compatible = "qcom,tcsr-mutex";
39		− reg = <0x01f40000 0x40000>;
40		− #hwlock-cells = <1>;
41		− };
	50	+ hwlock@1f40000 {
	51	+ compatible = "qcom,tcsr-mutex";
	52	+ reg = <0x01f40000 0x40000>;
	53	+ #hwlock-cells = <1>;
	54	+ };
42	55	...

Documentation/devicetree/bindings/net/engleder,tsnep.yaml+1−1

@@ -47,7 +47,7 @@ properties: · 46 unmodified lines
47	47
48	48	nvmem-cells: true
49	49
50		− nvmem-cells-names: true
	50	+ nvmem-cell-names: true
51	51
52	52	phy-connection-type:
53	53	enum:

Documentation/virt/kvm/devices/vm.rst+3−0

@@ -215,6 +215,7 @@ KVM_S390_VM_TOD_EXT). · 214 unmodified lines
215	215	:Parameters: address of a buffer in user space to store the data (u8) to
216	216	:Returns: -EFAULT if the given address is not accessible from kernel space;
217	217	-EINVAL if setting the TOD clock extension to != 0 is not supported
	218	+ -EOPNOTSUPP for a PV guest (TOD managed by the ultravisor)
218	219
219	220	3.2. ATTRIBUTE: KVM_S390_VM_TOD_LOW
220	221	-----------------------------------
@@ -224,6 +225,7 @@ the POP (u64). · 3 unmodified lines
224	225
225	226	:Parameters: address of a buffer in user space to store the data (u64) to
226	227	:Returns: -EFAULT if the given address is not accessible from kernel space
	228	+ -EOPNOTSUPP for a PV guest (TOD managed by the ultravisor)
227	229
228	230	3.3. ATTRIBUTE: KVM_S390_VM_TOD_EXT
229	231	-----------------------------------
@@ -237,6 +239,7 @@ it, it is stored as 0 and not allowed to be set to a value != 0. · 7 unmodified lines
237	239	(kvm_s390_vm_tod_clock) to
238	240	:Returns: -EFAULT if the given address is not accessible from kernel space;
239	241	-EINVAL if setting the TOD clock extension to != 0 is not supported
	242	+ -EOPNOTSUPP for a PV guest (TOD managed by the ultravisor)
240	243
241	244	4. GROUP: KVM_S390_VM_CRYPTO
242	245	============================

MAINTAINERS+2−5

@@ -8602,8 +8602,8 @@ F: include/asm-generic/ · 8601 unmodified lines
8602	8602	F: include/uapi/asm-generic/
8603	8603
8604	8604	GENERIC PHY FRAMEWORK
8605		−M: Kishon Vijay Abraham I <kishon@ti.com>
8606	8605	M: Vinod Koul <vkoul@kernel.org>
	8606	+M: Kishon Vijay Abraham I <kishon@kernel.org>
8607	8607	L: linux-phy@lists.infradead.org
8608	8608	S: Supported
8609	8609	Q: https://patchwork.kernel.org/project/linux-phy/list/
@@ -9341,7 +9341,7 @@ S: Maintained · 731 unmodified lines
9341	9341	F: drivers/crypto/hisilicon/trng/trng.c
9342	9342
9343	9343	HISILICON V3XX SPI NOR FLASH Controller Driver
9344		−M: John Garry <john.garry@huawei.com>
	9344	+M: Jay Fang <f.fangjian@huawei.com>
9345	9345	S: Maintained
9346	9346	W: http://www.hisilicon.com
9347	9347	F: drivers/spi/spi-hisi-sfc-v3xx.c
@@ -9507,7 +9507,6 @@ F: drivers/media/i2c/hi847.c · 159 unmodified lines
9507	9507	Hyper-V/Azure CORE AND DRIVERS
9508	9508	M: "K. Y. Srinivasan" <kys@microsoft.com>
9509	9509	M: Haiyang Zhang <haiyangz@microsoft.com>
9510		−M: Stephen Hemminger <sthemmin@microsoft.com>
9511	9510	M: Wei Liu <wei.liu@kernel.org>
9512	9511	M: Dexuan Cui <decui@microsoft.com>
9513	9512	L: linux-hyperv@vger.kernel.org
@@ -12226,7 +12225,6 @@ F: arch/mips/boot/dts/img/pistachio* · 2712 unmodified lines
12226	12225
12227	12226	MARVELL 88E6XXX ETHERNET SWITCH FABRIC DRIVER
12228	12227	M: Andrew Lunn <andrew@lunn.ch>
12229		−M: Vivien Didelot <vivien.didelot@gmail.com>
12230	12228	L: netdev@vger.kernel.org
12231	12229	S: Maintained
12232	12230	F: Documentation/devicetree/bindings/net/dsa/marvell.txt
@@ -14324,7 +14322,6 @@ F: drivers/net/wireless/ · 2091 unmodified lines
14324	14322
14325	14323	NETWORKING [DSA]
14326	14324	M: Andrew Lunn <andrew@lunn.ch>
14327		−M: Vivien Didelot <vivien.didelot@gmail.com>
14328	14325	M: Florian Fainelli <f.fainelli@gmail.com>
14329	14326	M: Vladimir Oltean <olteanv@gmail.com>
14330	14327	S: Maintained

Makefile+1−1

@@ -2,7 +2,7 @@ · 1 unmodified line
2	2	VERSION = 6
3	3	PATCHLEVEL = 1
4	4	SUBLEVEL = 0
5		−EXTRAVERSION = -rc4
	5	+EXTRAVERSION = -rc5
6	6	NAME = Hurr durr I'ma ninja sloth
7	7
8	8	# DOCUMENTATION

arch/arm64/include/asm/cputype.h+1−1

@@ -41,7 +41,7 @@ · 40 unmodified lines
41	41	(((midr) & MIDR_IMPLEMENTOR_MASK) >> MIDR_IMPLEMENTOR_SHIFT)
42	42
43	43	#define MIDR_CPU_MODEL(imp, partnum) \
44		− (((imp) << MIDR_IMPLEMENTOR_SHIFT) \| \
	44	+ ((_AT(u32, imp) << MIDR_IMPLEMENTOR_SHIFT) \| \
45	45	(0xf << MIDR_ARCHITECTURE_SHIFT) \| \
46	46	((partnum) << MIDR_PARTNUM_SHIFT))
47	47

arch/arm64/include/asm/syscall_wrapper.h+1−1

@@ -8,7 +8,7 @@ · 7 unmodified lines
8	8	#ifndef __ASM_SYSCALL_WRAPPER_H
9	9	#define __ASM_SYSCALL_WRAPPER_H
10	10
11		−struct pt_regs;
	11	+#include <asm/ptrace.h>
12	12
13	13	#define SC_ARM64_REGS_TO_ARGS(x, ...) \
14	14	__MAP(x,__SC_ARGS \

arch/arm64/kernel/efi.c+34−18

@@ -13,6 +13,14 @@ · 12 unmodified lines
13	13
14	14	#include <asm/efi.h>
15	15
	16	+static bool region_is_misaligned(const efi_memory_desc_t *md)
	17	+{
	18	+ if (PAGE_SIZE == EFI_PAGE_SIZE)
	19	+ return false;
	20	+ return !PAGE_ALIGNED(md->phys_addr) \|\|
	21	+ !PAGE_ALIGNED(md->num_pages << EFI_PAGE_SHIFT);
	22	+}
	23	+
16	24	/*
17	25	* Only regions of type EFI_RUNTIME_SERVICES_CODE need to be
18	26	* executable, everything else can be mapped with the XN bits
@@ -26,14 +34,22 @@ static __init pteval_t create_mapping_protection(efi_memory_desc_t *md) · 7 unmodified lines
26	34	if (type == EFI_MEMORY_MAPPED_IO)
27	35	return PROT_DEVICE_nGnRE;
28	36
29		− if (WARN_ONCE(!PAGE_ALIGNED(md->phys_addr),
30		− "UEFI Runtime regions are not aligned to 64 KB -- buggy firmware?"))
	37	+ if (region_is_misaligned(md)) {
	38	+ static bool __initdata code_is_misaligned;
	39	+
31	40	/*
32		− * If the region is not aligned to the page size of the OS, we
33		− * can not use strict permissions, since that would also affect
34		− * the mapping attributes of the adjacent regions.
	41	+ * Regions that are not aligned to the OS page size cannot be
	42	+ * mapped with strict permissions, as those might interfere
	43	+ * with the permissions that are needed by the adjacent
	44	+ * region's mapping. However, if we haven't encountered any
	45	+ * misaligned runtime code regions so far, we can safely use
	46	+ * non-executable permissions for non-code regions.
35	47	*/
36		− return pgprot_val(PAGE_KERNEL_EXEC);
	48	+ code_is_misaligned \|= (type == EFI_RUNTIME_SERVICES_CODE);
	49	+
	50	+ return code_is_misaligned ? pgprot_val(PAGE_KERNEL_EXEC)
	51	+ : pgprot_val(PAGE_KERNEL);
	52	+ }
37	53
38	54	/* R-- */
39	55	if ((attr & (EFI_MEMORY_XP \| EFI_MEMORY_RO)) ==
@@ -64,19 +80,16 @@ int __init efi_create_mapping(struct mm_struct mm, efi_memory_desc_t md) · 24 unmodified lines
64	80	bool page_mappings_only = (md->type == EFI_RUNTIME_SERVICES_CODE \|\|
65	81	md->type == EFI_RUNTIME_SERVICES_DATA);
66	82
67		− if (!PAGE_ALIGNED(md->phys_addr) \|\|
68		− !PAGE_ALIGNED(md->num_pages << EFI_PAGE_SHIFT)) {
69		− /*
70		− * If the end address of this region is not aligned to page
71		− * size, the mapping is rounded up, and may end up sharing a
72		− * page frame with the next UEFI memory region. If we create
73		− * a block entry now, we may need to split it again when mapping
74		− * the next region, and support for that is going to be removed
75		− * from the MMU routines. So avoid block mappings altogether in
76		− * that case.
77		− */
	83	+ /*
	84	+ * If this region is not aligned to the page size used by the OS, the
	85	+ * mapping will be rounded outwards, and may end up sharing a page
	86	+ * frame with an adjacent runtime memory region. Given that the page
	87	+ * table descriptor covering the shared page will be rewritten when the
	88	+ * adjacent region gets mapped, we must avoid block mappings here so we
	89	+ * don't have to worry about splitting them when that happens.
	90	+ */
	91	+ if (region_is_misaligned(md))
78	92	page_mappings_only = true;
79		− }
80	93
81	94	create_pgd_mapping(mm, md->phys_addr, md->virt_addr,
82	95	md->num_pages << EFI_PAGE_SHIFT,
@@ -103,6 +116,9 @@ int __init efi_set_mapping_permissions(struct mm_struct *mm, · 20 unmodified lines
103	116	BUG_ON(md->type != EFI_RUNTIME_SERVICES_CODE &&
104	117	md->type != EFI_RUNTIME_SERVICES_DATA);
105	118
	119	+ if (region_is_misaligned(md))
	120	+ return 0;
	121	+
106	122	/*
107	123	* Calling apply_to_page_range() is only safe on regions that are
108	124	* guaranteed to be mapped down to pages. Since we are only called

arch/arm64/mm/pageattr.c+3−2

@@ -26,7 +26,7 @@ bool can_set_direct_map(void) · 25 unmodified lines
26	26	* mapped at page granularity, so that it is possible to
27	27	* protect/unprotect single pages.
28	28	*/
29		− return rodata_full \|\| debug_pagealloc_enabled() \|\|
	29	+ return (rodata_enabled && rodata_full) \|\| debug_pagealloc_enabled() \|\|
30	30	IS_ENABLED(CONFIG_KFENCE);
31	31	}
32	32
@@ -102,7 +102,8 @@ static int change_memory_common(unsigned long addr, int numpages, · 69 unmodified lines
102	102	* If we are manipulating read-only permissions, apply the same
103	103	* change to the linear mapping of the pages that back this VM area.
104	104	*/
105		− if (rodata_full && (pgprot_val(set_mask) == PTE_RDONLY \|\|
	105	+ if (rodata_enabled &&
	106	+ rodata_full && (pgprot_val(set_mask) == PTE_RDONLY \|\|
106	107	pgprot_val(clear_mask) == PTE_RDONLY)) {
107	108	for (i = 0; i < area->nr_pages; i++) {
108	109	__change_memory_common((u64)page_address(area->pages[i]),

arch/mips/alchemy/common/gpiolib.c+1−1

@@ -31,7 +31,7 @@ · 30 unmodified lines
31	31	#include <linux/init.h>
32	32	#include <linux/kernel.h>
33	33	#include <linux/types.h>
34		−#include <linux/gpio.h>
	34	+#include <linux/gpio/driver.h>
35	35	#include <asm/mach-au1x00/gpio-au1000.h>
36	36	#include <asm/mach-au1x00/gpio-au1300.h>
37	37

arch/mips/boot/compressed/decompress.c+1−0

@@ -9,6 +9,7 @@ · 8 unmodified lines
9	9
10	10	#define DISABLE_BRANCH_PROFILING
11	11
	12	+#define __NO_FORTIFY
12	13	#include <linux/types.h>
13	14	#include <linux/kernel.h>
14	15	#include <linux/string.h>

arch/mips/include/asm/fw/fw.h+1−1

@@ -26,6 +26,6 @@ extern char *fw_getcmdline(void); · 25 unmodified lines
26	26	extern void fw_meminit(void);
27	27	extern char fw_getenv(char name);
28	28	extern unsigned long fw_getenvl(char *name);
29		−extern void fw_init_early_console(char port);
	29	+extern void fw_init_early_console(void);
30	30
31	31	#endif /* __ASM_FW_H_ */

arch/mips/kernel/jump_label.c+1−1

@@ -56,7 +56,7 @@ void arch_jump_label_transform(struct jump_entry *e, · 55 unmodified lines
56	56	* The branch offset must fit in the instruction's 26
57	57	* bit field.
58	58	*/
59		− WARN_ON((offset >= BIT(25)) \|\|
	59	+ WARN_ON((offset >= (long)BIT(25)) \|\|
60	60	(offset < -(long)BIT(25)));
61	61
62	62	insn.j_format.opcode = bc6_op;

arch/mips/kernel/relocate_kernel.S+5−10

@@ -145,8 +145,7 @@ LEAF(kexec_smp_wait) · 144 unmodified lines
145	145	* kexec_args[0..3] are used to prepare register values.
146	146	*/
147	147
148		−kexec_args:
149		− EXPORT(kexec_args)
	148	+EXPORT(kexec_args)
150	149	arg0: PTR_WD 0x0
151	150	arg1: PTR_WD 0x0
152	151	arg2: PTR_WD 0x0
@@ -159,8 +158,7 @@ arg3: PTR_WD 0x0 · 6 unmodified lines
159	158	* their registers a0-a3. secondary_kexec_args[0..3] are used
160	159	* to prepare register values.
161	160	*/
162		−secondary_kexec_args:
163		− EXPORT(secondary_kexec_args)
	161	+EXPORT(secondary_kexec_args)
164	162	s_arg0: PTR_WD 0x0
165	163	s_arg1: PTR_WD 0x0
166	164	s_arg2: PTR_WD 0x0
@@ -171,19 +169,16 @@ kexec_flag: · 4 unmodified lines
171	169
172	170	#endif
173	171
174		−kexec_start_address:
175		− EXPORT(kexec_start_address)
	172	+EXPORT(kexec_start_address)
176	173	PTR_WD 0x0
177	174	.size kexec_start_address, PTRSIZE
178	175
179		−kexec_indirection_page:
180		− EXPORT(kexec_indirection_page)
	176	+EXPORT(kexec_indirection_page)
181	177	PTR_WD 0
182	178	.size kexec_indirection_page, PTRSIZE
183	179
184	180	relocate_new_kernel_end:
185	181
186		−relocate_new_kernel_size:
187		− EXPORT(relocate_new_kernel_size)
	182	+EXPORT(relocate_new_kernel_size)
188	183	PTR_WD relocate_new_kernel_end - relocate_new_kernel
189	184	.size relocate_new_kernel_size, PTRSIZE

arch/mips/loongson64/reset.c+10−0

@@ -16,6 +16,7 @@ · 15 unmodified lines
16	16	#include <asm/bootinfo.h>
17	17	#include <asm/idle.h>
18	18	#include <asm/reboot.h>
	19	+#include <asm/bug.h>
19	20
20	21	#include <loongson.h>
21	22	#include <boot_param.h>
@@ -159,8 +160,17 @@ static int __init mips_reboot_setup(void) · 137 unmodified lines
159	160
160	161	#ifdef CONFIG_KEXEC
161	162	kexec_argv = kmalloc(KEXEC_ARGV_SIZE, GFP_KERNEL);
	163	+ if (WARN_ON(!kexec_argv))
	164	+ return -ENOMEM;
	165	+
162	166	kdump_argv = kmalloc(KEXEC_ARGV_SIZE, GFP_KERNEL);
	167	+ if (WARN_ON(!kdump_argv))
	168	+ return -ENOMEM;
	169	+
163	170	kexec_envp = kmalloc(KEXEC_ENVP_SIZE, GFP_KERNEL);
	171	+ if (WARN_ON(!kexec_envp))
	172	+ return -ENOMEM;
	173	+
164	174	fw_arg1 = KEXEC_ARGV_ADDR;
165	175	memcpy(kexec_envp, (void *)fw_arg2, KEXEC_ENVP_SIZE);
166	176

arch/mips/pic32/pic32mzda/early_console.c+6−7

@@ -27,7 +27,7 @@ · 26 unmodified lines
27	27	#define U_BRG(x) (UART_BASE(x) + 0x40)
28	28
29	29	static void __iomem *uart_base;
30		−static char console_port = -1;
	30	+static int console_port = -1;
31	31
32	32	static int __init configure_uart_pins(int port)
33	33	{
@@ -47,7 +47,7 @@ static int __init configure_uart_pins(int port) · 13 unmodified lines
47	47	return 0;
48	48	}
49	49
50		−static void __init configure_uart(char port, int baud)
	50	+static void __init configure_uart(int port, int baud)
51	51	{
52	52	u32 pbclk;
53	53
@@ -60,7 +60,7 @@ static void __init configure_uart(char port, int baud) · 6 unmodified lines
60	60	uart_base + PIC32_SET(U_STA(port)));
61	61	}
62	62
63		−static void __init setup_early_console(char port, int baud)
	63	+static void __init setup_early_console(int port, int baud)
64	64	{
65	65	if (configure_uart_pins(port))
66	66	return;
@@ -130,16 +130,15 @@ _out: · 63 unmodified lines
130	130	return baud;
131	131	}
132	132
133		−void __init fw_init_early_console(char port)
	133	+void __init fw_init_early_console(void)
134	134	{
135	135	char *arch_cmdline = pic32_getcmdline();
136		− int baud = -1;
	136	+ int baud, port;
137	137
138	138	uart_base = ioremap(PIC32_BASE_UART, 0xc00);
139	139
140	140	baud = get_baud_from_cmdline(arch_cmdline);
141		− if (port == -1)
142		− port = get_port_from_cmdline(arch_cmdline);
	141	+ port = get_port_from_cmdline(arch_cmdline);
143	142
144	143	if (port == -1)
145	144	port = EARLY_CONSOLE_PORT;

arch/mips/pic32/pic32mzda/init.c+1−1

@@ -47,7 +47,7 @@ void __init plat_mem_setup(void) · 46 unmodified lines
47	47	strscpy(arcs_cmdline, boot_command_line, COMMAND_LINE_SIZE);
48	48
49	49	#ifdef CONFIG_EARLY_PRINTK
50		− fw_init_early_console(-1);
	50	+ fw_init_early_console();
51	51	#endif
52	52	pic32_config_init();
53	53	}

arch/riscv/boot/dts/sifive/hifive-unleashed-a00.dts+38−0

@@ -3,6 +3,8 @@ · 2 unmodified lines
3	3
4	4	#include "fu540-c000.dtsi"
5	5	#include <dt-bindings/gpio/gpio.h>
	6	+#include <dt-bindings/leds/common.h>
	7	+#include <dt-bindings/pwm/pwm.h>
6	8
7	9	/* Clock frequency (in Hz) of the PCB crystal for rtcclk */
8	10	#define RTCCLK_FREQ 1000000
@@ -42,6 +44,42 @@ · 33 unmodified lines
42	44	compatible = "gpio-restart";
43	45	gpios = <&gpio 10 GPIO_ACTIVE_LOW>;
44	46	};
	47	+
	48	+ led-controller {
	49	+ compatible = "pwm-leds";
	50	+
	51	+ led-d1 {
	52	+ pwms = <&pwm0 0 7812500 PWM_POLARITY_INVERTED>;
	53	+ active-low;
	54	+ color = <LED_COLOR_ID_GREEN>;
	55	+ max-brightness = <255>;
	56	+ label = "d1";
	57	+ };
	58	+
	59	+ led-d2 {
	60	+ pwms = <&pwm0 1 7812500 PWM_POLARITY_INVERTED>;
	61	+ active-low;
	62	+ color = <LED_COLOR_ID_GREEN>;
	63	+ max-brightness = <255>;
	64	+ label = "d2";
	65	+ };
	66	+
	67	+ led-d3 {
	68	+ pwms = <&pwm0 2 7812500 PWM_POLARITY_INVERTED>;
	69	+ active-low;
	70	+ color = <LED_COLOR_ID_GREEN>;
	71	+ max-brightness = <255>;
	72	+ label = "d3";
	73	+ };
	74	+
	75	+ led-d4 {
	76	+ pwms = <&pwm0 3 7812500 PWM_POLARITY_INVERTED>;
	77	+ active-low;
	78	+ color = <LED_COLOR_ID_GREEN>;
	79	+ max-brightness = <255>;
	80	+ label = "d4";
	81	+ };
	82	+ };
45	83	};
46	84
47	85	&uart0 {

arch/riscv/kernel/process.c+2−0

@@ -164,6 +164,8 @@ int copy_thread(struct task_struct p, const struct kernel_clone_args args) · 163 unmodified lines
164	164	unsigned long tls = args->tls;
165	165	struct pt_regs *childregs = task_pt_regs(p);
166	166
	167	+ memset(&p->thread.s, 0, sizeof(p->thread.s));
	168	+
167	169	/* p->thread holds context to be restored by __switch_to() */
168	170	if (unlikely(args->fn)) {
169	171	/* Kernel thread */

arch/riscv/kernel/setup.c+1−0

@@ -283,6 +283,7 @@ void __init setup_arch(char **cmdline_p) · 282 unmodified lines
283	283	else
284	284	pr_err("No DTB found in kernel mappings\n");
285	285	#endif
	286	+ early_init_fdt_scan_reserved_mem();
286	287	misc_mem_init();
287	288
288	289	init_resources();

arch/riscv/kernel/vdso/Makefile+4−1

@@ -28,9 +28,12 @@ obj-vdso := $(addprefix $(obj)/, $(obj-vdso)) · 27 unmodified lines
28	28
29	29	obj-y += vdso.o
30	30	CPPFLAGS_vdso.lds += -P -C -U$(ARCH)
	31	+ifneq ($(filter vgettimeofday, $(vdso-syms)),)
	32	+CPPFLAGS_vdso.lds += -DHAS_VGETTIMEOFDAY
	33	+endif
31	34
32	35	# Disable -pg to prevent insert call site
33		−CFLAGS_REMOVE_vgettimeofday.o = $(CC_FLAGS_FTRACE) -Os
	36	+CFLAGS_REMOVE_vgettimeofday.o = $(CC_FLAGS_FTRACE)
34	37
35	38	# Disable profiling and instrumentation for VDSO code
36	39	GCOV_PROFILE := n

arch/riscv/kernel/vdso/vdso.lds.S+2−0

@@ -68,9 +68,11 @@ VERSION · 67 unmodified lines
68	68	LINUX_4.15 {
69	69	global:
70	70	__vdso_rt_sigreturn;
	71	+#ifdef HAS_VGETTIMEOFDAY
71	72	__vdso_gettimeofday;
72	73	__vdso_clock_gettime;
73	74	__vdso_clock_getres;
	75	+#endif
74	76	__vdso_getcpu;
75	77	__vdso_flush_icache;
76	78	local: *;

arch/riscv/mm/init.c+0−1

@@ -262,7 +262,6 @@ static void __init setup_bootmem(void) · 261 unmodified lines
262	262	memblock_reserve(dtb_early_pa, fdt_totalsize(dtb_early_va));
263	263	}
264	264
265		− early_init_fdt_scan_reserved_mem();
266	265	dma_contiguous_reserve(dma32_phys_limit);
267	266	if (IS_ENABLED(CONFIG_64BIT))
268	267	hugetlb_cma_reserve(PUD_SHIFT - PAGE_SHIFT);

arch/s390/Kconfig+3−3

@@ -568,8 +568,7 @@ config EXPOLINE_FULL · 567 unmodified lines
568	568	endchoice
569	569
570	570	config RELOCATABLE
571		− bool "Build a relocatable kernel"
572		− default y
	571	+ def_bool y
573	572	help
574	573	This builds a kernel image that retains relocation information
575	574	so it can be loaded at an arbitrary address.
@@ -578,10 +577,11 @@ config RELOCATABLE · 2 unmodified lines
578	577	bootup process.
579	578	The relocations make the kernel image about 15% larger (compressed
580	579	10%), but are discarded at runtime.
	580	+ Note: this option exists only for documentation purposes, please do
	581	+ not remove it.
581	582
582	583	config RANDOMIZE_BASE
583	584	bool "Randomize the address of the kernel image (KASLR)"
584		− depends on RELOCATABLE
585	585	default y
586	586	help
587	587	In support of Kernel Address Space Layout Randomization (KASLR),

arch/s390/Makefile+0−2

@@ -14,10 +14,8 @@ KBUILD_AFLAGS_MODULE += -fPIC · 13 unmodified lines
14	14	KBUILD_CFLAGS_MODULE += -fPIC
15	15	KBUILD_AFLAGS += -m64
16	16	KBUILD_CFLAGS += -m64
17		−ifeq ($(CONFIG_RELOCATABLE),y)
18	17	KBUILD_CFLAGS += -fPIE
19	18	LDFLAGS_vmlinux := -pie
20		−endif
21	19	aflags_dwarf := -Wa,-gdwarf-2
22	20	KBUILD_AFLAGS_DECOMPRESSOR := $(CLANG_FLAGS) -m64 -D__ASSEMBLY__
23	21	ifndef CONFIG_AS_IS_LLVM

arch/s390/boot/Makefile+1−2

@@ -37,9 +37,8 @@ CFLAGS_sclp_early_core.o += -I$(srctree)/drivers/s390/char · 36 unmodified lines
37	37
38	38	obj-y := head.o als.o startup.o mem_detect.o ipl_parm.o ipl_report.o
39	39	obj-y += string.o ebcdic.o sclp_early_core.o mem.o ipl_vmparm.o cmdline.o
40		−obj-y += version.o pgm_check_info.o ctype.o ipl_data.o
	40	+obj-y += version.o pgm_check_info.o ctype.o ipl_data.o machine_kexec_reloc.o
41	41	obj-$(findstring y, $(CONFIG_PROTECTED_VIRTUALIZATION_GUEST) $(CONFIG_PGSTE)) += uv.o
42		−obj-$(CONFIG_RELOCATABLE) += machine_kexec_reloc.o
43	42	obj-$(CONFIG_RANDOMIZE_BASE) += kaslr.o
44	43	obj-y += $(if $(CONFIG_KERNEL_UNCOMPRESSED),,decompressor.o) info.o
45	44	obj-$(CONFIG_KERNEL_ZSTD) += clz_ctz.o

arch/s390/boot/startup.c+1−2

@@ -291,8 +291,7 @@ void startup_kernel(void) · 290 unmodified lines
291	291
292	292	clear_bss_section();
293	293	copy_bootdata();
294		− if (IS_ENABLED(CONFIG_RELOCATABLE))
295		− handle_relocs(__kaslr_offset);
	294	+ handle_relocs(__kaslr_offset);
296	295
297	296	if (__kaslr_offset) {
298	297	/*

arch/s390/configs/btf.config+1−0

@@ -0,0 +1 @@
	1	+CONFIG_DEBUG_INFO_BTF=y

arch/s390/configs/debug_defconfig+32−33

@@ -723,52 +723,42 @@ CONFIG_CRYPTO_ECDSA=m · 722 unmodified lines
723	723	CONFIG_CRYPTO_ECRDSA=m
724	724	CONFIG_CRYPTO_SM2=m
725	725	CONFIG_CRYPTO_CURVE25519=m
726		−CONFIG_CRYPTO_GCM=y
727		−CONFIG_CRYPTO_CHACHA20POLY1305=m
728		−CONFIG_CRYPTO_AEGIS128=m
729		−CONFIG_CRYPTO_SEQIV=y
730		−CONFIG_CRYPTO_CFB=m
731		−CONFIG_CRYPTO_LRW=m
732		−CONFIG_CRYPTO_PCBC=m
733		−CONFIG_CRYPTO_KEYWRAP=m
734		−CONFIG_CRYPTO_ADIANTUM=m
735		−CONFIG_CRYPTO_HCTR2=m
736		−CONFIG_CRYPTO_XCBC=m
737		−CONFIG_CRYPTO_VMAC=m
738		−CONFIG_CRYPTO_CRC32=m
739		−CONFIG_CRYPTO_CRC32_S390=y
740		−CONFIG_CRYPTO_MD4=m
741		−CONFIG_CRYPTO_MD5=y
742		−CONFIG_CRYPTO_MICHAEL_MIC=m
743		−CONFIG_CRYPTO_RMD160=m
744		−CONFIG_CRYPTO_SHA512_S390=m
745		−CONFIG_CRYPTO_SHA1_S390=m
746		−CONFIG_CRYPTO_SHA256_S390=m
747		−CONFIG_CRYPTO_SHA3=m
748		−CONFIG_CRYPTO_SHA3_256_S390=m
749		−CONFIG_CRYPTO_SHA3_512_S390=m
750		−CONFIG_CRYPTO_SM3_GENERIC=m
751		−CONFIG_CRYPTO_WP512=m
752		−CONFIG_CRYPTO_GHASH_S390=m
753	726	CONFIG_CRYPTO_AES_TI=m
754		−CONFIG_CRYPTO_AES_S390=m
755	727	CONFIG_CRYPTO_ANUBIS=m
756		−CONFIG_CRYPTO_ARC4=m
	728	+CONFIG_CRYPTO_ARIA=m
757	729	CONFIG_CRYPTO_BLOWFISH=m
758	730	CONFIG_CRYPTO_CAMELLIA=m
759	731	CONFIG_CRYPTO_CAST5=m
760	732	CONFIG_CRYPTO_CAST6=m
761	733	CONFIG_CRYPTO_DES=m
762		−CONFIG_CRYPTO_DES_S390=m
763	734	CONFIG_CRYPTO_FCRYPT=m
764	735	CONFIG_CRYPTO_KHAZAD=m
765		−CONFIG_CRYPTO_CHACHA_S390=m
766	736	CONFIG_CRYPTO_SEED=m
767		−CONFIG_CRYPTO_ARIA=m
768	737	CONFIG_CRYPTO_SERPENT=m
769	738	CONFIG_CRYPTO_SM4_GENERIC=m
770	739	CONFIG_CRYPTO_TEA=m
771	740	CONFIG_CRYPTO_TWOFISH=m
	741	+CONFIG_CRYPTO_ADIANTUM=m
	742	+CONFIG_CRYPTO_ARC4=m
	743	+CONFIG_CRYPTO_CFB=m
	744	+CONFIG_CRYPTO_HCTR2=m
	745	+CONFIG_CRYPTO_KEYWRAP=m
	746	+CONFIG_CRYPTO_LRW=m
	747	+CONFIG_CRYPTO_PCBC=m
	748	+CONFIG_CRYPTO_AEGIS128=m
	749	+CONFIG_CRYPTO_CHACHA20POLY1305=m
	750	+CONFIG_CRYPTO_GCM=y
	751	+CONFIG_CRYPTO_SEQIV=y
	752	+CONFIG_CRYPTO_MD4=m
	753	+CONFIG_CRYPTO_MD5=y
	754	+CONFIG_CRYPTO_MICHAEL_MIC=m
	755	+CONFIG_CRYPTO_RMD160=m
	756	+CONFIG_CRYPTO_SHA3=m
	757	+CONFIG_CRYPTO_SM3_GENERIC=m
	758	+CONFIG_CRYPTO_VMAC=m
	759	+CONFIG_CRYPTO_WP512=m
	760	+CONFIG_CRYPTO_XCBC=m
	761	+CONFIG_CRYPTO_CRC32=m
772	762	CONFIG_CRYPTO_842=m
773	763	CONFIG_CRYPTO_LZ4=m
774	764	CONFIG_CRYPTO_LZ4HC=m
@@ -779,6 +769,16 @@ CONFIG_CRYPTO_USER_API_SKCIPHER=m · 4 unmodified lines
779	769	CONFIG_CRYPTO_USER_API_RNG=m
780	770	CONFIG_CRYPTO_USER_API_AEAD=m
781	771	CONFIG_CRYPTO_STATS=y
	772	+CONFIG_CRYPTO_CRC32_S390=y
	773	+CONFIG_CRYPTO_SHA512_S390=m
	774	+CONFIG_CRYPTO_SHA1_S390=m
	775	+CONFIG_CRYPTO_SHA256_S390=m
	776	+CONFIG_CRYPTO_SHA3_256_S390=m
	777	+CONFIG_CRYPTO_SHA3_512_S390=m
	778	+CONFIG_CRYPTO_GHASH_S390=m
	779	+CONFIG_CRYPTO_AES_S390=m
	780	+CONFIG_CRYPTO_DES_S390=m
	781	+CONFIG_CRYPTO_CHACHA_S390=m
782	782	CONFIG_ZCRYPT=m
783	783	CONFIG_PKEY=m
784	784	CONFIG_CRYPTO_PAES_S390=m
@@ -797,7 +797,6 @@ CONFIG_CMA_SIZE_MBYTES=0 · 12 unmodified lines
797	797	CONFIG_PRINTK_TIME=y
798	798	CONFIG_DYNAMIC_DEBUG=y
799	799	CONFIG_DEBUG_INFO_DWARF4=y
800		−CONFIG_DEBUG_INFO_BTF=y
801	800	CONFIG_GDB_SCRIPTS=y
802	801	CONFIG_HEADERS_INSTALL=y
803	802	CONFIG_DEBUG_SECTION_MISMATCH=y

arch/s390/configs/defconfig+33−34

@@ -707,53 +707,43 @@ CONFIG_CRYPTO_ECDSA=m · 706 unmodified lines
707	707	CONFIG_CRYPTO_ECRDSA=m
708	708	CONFIG_CRYPTO_SM2=m
709	709	CONFIG_CRYPTO_CURVE25519=m
710		−CONFIG_CRYPTO_GCM=y
711		−CONFIG_CRYPTO_CHACHA20POLY1305=m
712		−CONFIG_CRYPTO_AEGIS128=m
713		−CONFIG_CRYPTO_SEQIV=y
714		−CONFIG_CRYPTO_CFB=m
715		−CONFIG_CRYPTO_LRW=m
716		−CONFIG_CRYPTO_OFB=m
717		−CONFIG_CRYPTO_PCBC=m
718		−CONFIG_CRYPTO_KEYWRAP=m
719		−CONFIG_CRYPTO_ADIANTUM=m
720		−CONFIG_CRYPTO_HCTR2=m
721		−CONFIG_CRYPTO_XCBC=m
722		−CONFIG_CRYPTO_VMAC=m
723		−CONFIG_CRYPTO_CRC32=m
724		−CONFIG_CRYPTO_CRC32_S390=y
725		−CONFIG_CRYPTO_MD4=m
726		−CONFIG_CRYPTO_MD5=y
727		−CONFIG_CRYPTO_MICHAEL_MIC=m
728		−CONFIG_CRYPTO_RMD160=m
729		−CONFIG_CRYPTO_SHA512_S390=m
730		−CONFIG_CRYPTO_SHA1_S390=m
731		−CONFIG_CRYPTO_SHA256_S390=m
732		−CONFIG_CRYPTO_SHA3=m
733		−CONFIG_CRYPTO_SHA3_256_S390=m
734		−CONFIG_CRYPTO_SHA3_512_S390=m
735		−CONFIG_CRYPTO_SM3_GENERIC=m
736		−CONFIG_CRYPTO_WP512=m
737		−CONFIG_CRYPTO_GHASH_S390=m
738	710	CONFIG_CRYPTO_AES_TI=m
739		−CONFIG_CRYPTO_AES_S390=m
740	711	CONFIG_CRYPTO_ANUBIS=m
741		−CONFIG_CRYPTO_ARC4=m
	712	+CONFIG_CRYPTO_ARIA=m
742	713	CONFIG_CRYPTO_BLOWFISH=m
743	714	CONFIG_CRYPTO_CAMELLIA=m
744	715	CONFIG_CRYPTO_CAST5=m
745	716	CONFIG_CRYPTO_CAST6=m
746	717	CONFIG_CRYPTO_DES=m
747		−CONFIG_CRYPTO_DES_S390=m
748	718	CONFIG_CRYPTO_FCRYPT=m
749	719	CONFIG_CRYPTO_KHAZAD=m
750		−CONFIG_CRYPTO_CHACHA_S390=m
751	720	CONFIG_CRYPTO_SEED=m
752		−CONFIG_CRYPTO_ARIA=m
753	721	CONFIG_CRYPTO_SERPENT=m
754	722	CONFIG_CRYPTO_SM4_GENERIC=m
755	723	CONFIG_CRYPTO_TEA=m
756	724	CONFIG_CRYPTO_TWOFISH=m
	725	+CONFIG_CRYPTO_ADIANTUM=m
	726	+CONFIG_CRYPTO_ARC4=m
	727	+CONFIG_CRYPTO_CFB=m
	728	+CONFIG_CRYPTO_HCTR2=m
	729	+CONFIG_CRYPTO_KEYWRAP=m
	730	+CONFIG_CRYPTO_LRW=m
	731	+CONFIG_CRYPTO_OFB=m
	732	+CONFIG_CRYPTO_PCBC=m
	733	+CONFIG_CRYPTO_AEGIS128=m
	734	+CONFIG_CRYPTO_CHACHA20POLY1305=m
	735	+CONFIG_CRYPTO_GCM=y
	736	+CONFIG_CRYPTO_SEQIV=y
	737	+CONFIG_CRYPTO_MD4=m
	738	+CONFIG_CRYPTO_MD5=y
	739	+CONFIG_CRYPTO_MICHAEL_MIC=m
	740	+CONFIG_CRYPTO_RMD160=m
	741	+CONFIG_CRYPTO_SHA3=m
	742	+CONFIG_CRYPTO_SM3_GENERIC=m
	743	+CONFIG_CRYPTO_VMAC=m
	744	+CONFIG_CRYPTO_WP512=m
	745	+CONFIG_CRYPTO_XCBC=m
	746	+CONFIG_CRYPTO_CRC32=m
757	747	CONFIG_CRYPTO_842=m
758	748	CONFIG_CRYPTO_LZ4=m
759	749	CONFIG_CRYPTO_LZ4HC=m
@@ -764,6 +754,16 @@ CONFIG_CRYPTO_USER_API_SKCIPHER=m · 4 unmodified lines
764	754	CONFIG_CRYPTO_USER_API_RNG=m
765	755	CONFIG_CRYPTO_USER_API_AEAD=m
766	756	CONFIG_CRYPTO_STATS=y
	757	+CONFIG_CRYPTO_CRC32_S390=y
	758	+CONFIG_CRYPTO_SHA512_S390=m
	759	+CONFIG_CRYPTO_SHA1_S390=m
	760	+CONFIG_CRYPTO_SHA256_S390=m
	761	+CONFIG_CRYPTO_SHA3_256_S390=m
	762	+CONFIG_CRYPTO_SHA3_512_S390=m
	763	+CONFIG_CRYPTO_GHASH_S390=m
	764	+CONFIG_CRYPTO_AES_S390=m
	765	+CONFIG_CRYPTO_DES_S390=m
	766	+CONFIG_CRYPTO_CHACHA_S390=m
767	767	CONFIG_ZCRYPT=m
768	768	CONFIG_PKEY=m
769	769	CONFIG_CRYPTO_PAES_S390=m
@@ -781,7 +781,6 @@ CONFIG_CMA_SIZE_MBYTES=0 · 11 unmodified lines
781	781	CONFIG_PRINTK_TIME=y
782	782	CONFIG_DYNAMIC_DEBUG=y
783	783	CONFIG_DEBUG_INFO_DWARF4=y
784		−CONFIG_DEBUG_INFO_BTF=y
785	784	CONFIG_GDB_SCRIPTS=y
786	785	CONFIG_DEBUG_SECTION_MISMATCH=y
787	786	CONFIG_MAGIC_SYSRQ=y

arch/s390/configs/kasan.config+3−0

@@ -0,0 +1,3 @@
	1	+CONFIG_KASAN=y
	2	+CONFIG_KASAN_INLINE=y
	3	+CONFIG_KASAN_VMALLOC=y

arch/s390/configs/zfcpdump_defconfig+0−1

@@ -74,7 +74,6 @@ CONFIG_PRINTK_TIME=y · 73 unmodified lines
74	74	# CONFIG_SYMBOLIC_ERRNAME is not set
75	75	CONFIG_DEBUG_KERNEL=y
76	76	CONFIG_DEBUG_INFO_DWARF4=y
77		−CONFIG_DEBUG_INFO_BTF=y
78	77	CONFIG_DEBUG_FS=y
79	78	CONFIG_PANIC_ON_OOPS=y
80	79	# CONFIG_SCHED_DEBUG is not set

arch/s390/kvm/kvm-s390.c+17−9

@@ -1207,6 +1207,8 @@ static int kvm_s390_vm_get_migration(struct kvm *kvm, · 1206 unmodified lines
1207	1207	return 0;
1208	1208	}
1209	1209
	1210	+static void __kvm_s390_set_tod_clock(struct kvm kvm, const struct kvm_s390_vm_tod_clock gtod);
	1211	+
1210	1212	static int kvm_s390_set_tod_ext(struct kvm kvm, struct kvm_device_attr attr)
1211	1213	{
1212	1214	struct kvm_s390_vm_tod_clock gtod;
@@ -1216,7 +1218,7 @@ static int kvm_s390_set_tod_ext(struct kvm kvm, struct kvm_device_attr attr) · 3 unmodified lines
1216	1218
1217	1219	if (!test_kvm_facility(kvm, 139) && gtod.epoch_idx)
1218	1220	return -EINVAL;
1219		− kvm_s390_set_tod_clock(kvm, &gtod);
	1221	+ __kvm_s390_set_tod_clock(kvm, &gtod);
1220	1222
1221	1223	VM_EVENT(kvm, 3, "SET: TOD extension: 0x%x, TOD base: 0x%llx",
1222	1224	gtod.epoch_idx, gtod.tod);
@@ -1247,7 +1249,7 @@ static int kvm_s390_set_tod_low(struct kvm kvm, struct kvm_device_attr attr) · 24 unmodified lines
1247	1249	sizeof(gtod.tod)))
1248	1250	return -EFAULT;
1249	1251
1250		− kvm_s390_set_tod_clock(kvm, &gtod);
	1252	+ __kvm_s390_set_tod_clock(kvm, &gtod);
1251	1253	VM_EVENT(kvm, 3, "SET: TOD base: 0x%llx", gtod.tod);
1252	1254	return 0;
1253	1255	}
@@ -1259,6 +1261,16 @@ static int kvm_s390_set_tod(struct kvm kvm, struct kvm_device_attr attr) · 5 unmodified lines
1259	1261	if (attr->flags)
1260	1262	return -EINVAL;
1261	1263
	1264	+ mutex_lock(&kvm->lock);
	1265	+ /*
	1266	+ * For protected guests, the TOD is managed by the ultravisor, so trying
	1267	+ * to change it will never bring the expected results.
	1268	+ */
	1269	+ if (kvm_s390_pv_is_protected(kvm)) {
	1270	+ ret = -EOPNOTSUPP;
	1271	+ goto out_unlock;
	1272	+ }
	1273	+
1262	1274	switch (attr->attr) {
1263	1275	case KVM_S390_VM_TOD_EXT:
1264	1276	ret = kvm_s390_set_tod_ext(kvm, attr);
@@ -1273,6 +1285,9 @@ static int kvm_s390_set_tod(struct kvm kvm, struct kvm_device_attr attr) · 8 unmodified lines
1273	1285	ret = -ENXIO;
1274	1286	break;
1275	1287	}
	1288	+
	1289	+out_unlock:
	1290	+ mutex_unlock(&kvm->lock);
1276	1291	return ret;
1277	1292	}
1278	1293
@@ -4377,13 +4392,6 @@ static void __kvm_s390_set_tod_clock(struct kvm *kvm, const struct kvm_s390_vm_t · 3098 unmodified lines
4377	4392	preempt_enable();
4378	4393	}
4379	4394
4380		−void kvm_s390_set_tod_clock(struct kvm kvm, const struct kvm_s390_vm_tod_clock gtod)
4381		−{
4382		− mutex_lock(&kvm->lock);
4383		− __kvm_s390_set_tod_clock(kvm, gtod);
4384		− mutex_unlock(&kvm->lock);
4385		−}
4386		−
4387	4395	int kvm_s390_try_set_tod_clock(struct kvm kvm, const struct kvm_s390_vm_tod_clock gtod)
4388	4396	{
4389	4397	if (!mutex_trylock(&kvm->lock))

arch/s390/kvm/kvm-s390.h+0−1

@@ -363,7 +363,6 @@ int kvm_s390_handle_sigp(struct kvm_vcpu *vcpu); · 362 unmodified lines
363	363	int kvm_s390_handle_sigp_pei(struct kvm_vcpu *vcpu);
364	364
365	365	/* implemented in kvm-s390.c */
366		−void kvm_s390_set_tod_clock(struct kvm kvm, const struct kvm_s390_vm_tod_clock gtod);
367	366	int kvm_s390_try_set_tod_clock(struct kvm kvm, const struct kvm_s390_vm_tod_clock gtod);
368	367	long kvm_arch_fault_in_page(struct kvm_vcpu *vcpu, gpa_t gpa, int writable);
369	368	int kvm_s390_store_status_unloaded(struct kvm_vcpu *vcpu, unsigned long addr);

arch/s390/kvm/pci.c+1−1

@@ -126,7 +126,7 @@ int kvm_s390_pci_aen_init(u8 nisc) · 125 unmodified lines
126	126	return -EPERM;
127	127
128	128	mutex_lock(&aift->aift_lock);
129		− aift->kzdev = kcalloc(ZPCI_NR_DEVICES, sizeof(struct kvm_zdev),
	129	+ aift->kzdev = kcalloc(ZPCI_NR_DEVICES, sizeof(struct kvm_zdev *),
130	130	GFP_KERNEL);
131	131	if (!aift->kzdev) {
132	132	rc = -ENOMEM;

arch/x86/hyperv/hv_init.c+10−9

@@ -444,7 +444,7 @@ void __init hyperv_init(void) · 443 unmodified lines
444	444
445	445	if (hv_root_partition) {
446	446	struct page *pg;
447		− void src, dst;
	447	+ void *src;
448	448
449	449	/*
450	450	* For the root partition, the hypervisor will set up its
@@ -459,13 +459,11 @@ void __init hyperv_init(void) · 8 unmodified lines
459	459	wrmsrl(HV_X64_MSR_HYPERCALL, hypercall_msr.as_uint64);
460	460
461	461	pg = vmalloc_to_page(hv_hypercall_pg);
462		− dst = kmap_local_page(pg);
463	462	src = memremap(hypercall_msr.guest_physical_address << PAGE_SHIFT, PAGE_SIZE,
464	463	MEMREMAP_WB);
465		− BUG_ON(!(src && dst));
466		− memcpy(dst, src, HV_HYP_PAGE_SIZE);
	464	+ BUG_ON(!src);
	465	+ memcpy_to_page(pg, 0, src, HV_HYP_PAGE_SIZE);
467	466	memunmap(src);
468		− kunmap_local(dst);
469	467	} else {
470	468	hypercall_msr.guest_physical_address = vmalloc_to_pfn(hv_hypercall_pg);
471	469	wrmsrl(HV_X64_MSR_HYPERCALL, hypercall_msr.as_uint64);
@@ -537,6 +535,7 @@ common_free: · 65 unmodified lines
537	535	void hyperv_cleanup(void)
538	536	{
539	537	union hv_x64_msr_hypercall_contents hypercall_msr;
	538	+ union hv_reference_tsc_msr tsc_msr;
540	539
541	540	unregister_syscore_ops(&hv_syscore_ops);
542	541
@@ -552,12 +551,14 @@ void hyperv_cleanup(void) · 9 unmodified lines
552	551	hv_hypercall_pg = NULL;
553	552
554	553	/* Reset the hypercall page */
555		− hypercall_msr.as_uint64 = 0;
556		− wrmsrl(HV_X64_MSR_HYPERCALL, hypercall_msr.as_uint64);
	554	+ hypercall_msr.as_uint64 = hv_get_register(HV_X64_MSR_HYPERCALL);
	555	+ hypercall_msr.enable = 0;
	556	+ hv_set_register(HV_X64_MSR_HYPERCALL, hypercall_msr.as_uint64);
557	557
558	558	/* Reset the TSC page */
559		− hypercall_msr.as_uint64 = 0;
560		− wrmsrl(HV_X64_MSR_REFERENCE_TSC, hypercall_msr.as_uint64);
	559	+ tsc_msr.as_uint64 = hv_get_register(HV_X64_MSR_REFERENCE_TSC);
	560	+ tsc_msr.enable = 0;
	561	+ hv_set_register(HV_X64_MSR_REFERENCE_TSC, tsc_msr.as_uint64);
561	562	}
562	563
563	564	void hyperv_report_panic(struct pt_regs *regs, long err, bool in_die)

arch/x86/include/asm/kvm_host.h+6−1

@@ -501,7 +501,12 @@ struct kvm_pmc { · 500 unmodified lines
501	501	bool intr;
502	502	};
503	503
	504	+/* More counters may conflict with other existing Architectural MSRs */
	505	+#define KVM_INTEL_PMC_MAX_GENERIC 8
	506	+#define MSR_ARCH_PERFMON_PERFCTR_MAX (MSR_ARCH_PERFMON_PERFCTR0 + KVM_INTEL_PMC_MAX_GENERIC - 1)
	507	+#define MSR_ARCH_PERFMON_EVENTSEL_MAX (MSR_ARCH_PERFMON_EVENTSEL0 + KVM_INTEL_PMC_MAX_GENERIC - 1)
504	508	#define KVM_PMC_MAX_FIXED 3
	509	+#define KVM_AMD_PMC_MAX_GENERIC 6
505	510	struct kvm_pmu {
506	511	unsigned nr_arch_gp_counters;
507	512	unsigned nr_arch_fixed_counters;
@@ -516,7 +521,7 @@ struct kvm_pmu { · 8 unmodified lines
516	521	u64 reserved_bits;
517	522	u64 raw_event_mask;
518	523	u8 version;
519		− struct kvm_pmc gp_counters[INTEL_PMC_MAX_GENERIC];
	524	+ struct kvm_pmc gp_counters[KVM_INTEL_PMC_MAX_GENERIC];
520	525	struct kvm_pmc fixed_counters[KVM_PMC_MAX_FIXED];
521	526	struct irq_work irq_work;
522	527	DECLARE_BITMAP(reprogram_pmi, X86_PMC_IDX_MAX);

arch/x86/include/asm/spec-ctrl.h+5−5

@@ -13,7 +13,7 @@ · 12 unmodified lines
13	13	* Takes the guest view of SPEC_CTRL MSR as a parameter and also
14	14	* the guest's version of VIRT_SPEC_CTRL, if emulated.
15	15	*/
16		−extern void x86_virt_spec_ctrl(u64 guest_spec_ctrl, u64 guest_virt_spec_ctrl, bool guest);
	16	+extern void x86_virt_spec_ctrl(u64 guest_virt_spec_ctrl, bool guest);
17	17
18	18	/**
19	19	* x86_spec_ctrl_set_guest - Set speculation control registers for the guest
@@ -24,9 +24,9 @@ extern void x86_virt_spec_ctrl(u64 guest_spec_ctrl, u64 guest_virt_spec_ctrl, bo · 4 unmodified lines
24	24	* Avoids writing to the MSR if the content/bits are the same
25	25	*/
26	26	static inline
27		−void x86_spec_ctrl_set_guest(u64 guest_spec_ctrl, u64 guest_virt_spec_ctrl)
	27	+void x86_spec_ctrl_set_guest(u64 guest_virt_spec_ctrl)
28	28	{
29		− x86_virt_spec_ctrl(guest_spec_ctrl, guest_virt_spec_ctrl, true);
	29	+ x86_virt_spec_ctrl(guest_virt_spec_ctrl, true);
30	30	}
31	31
32	32	/**
@@ -38,9 +38,9 @@ void x86_spec_ctrl_set_guest(u64 guest_spec_ctrl, u64 guest_virt_spec_ctrl) · 5 unmodified lines
38	38	* Avoids writing to the MSR if the content/bits are the same
39	39	*/
40	40	static inline
41		−void x86_spec_ctrl_restore_host(u64 guest_spec_ctrl, u64 guest_virt_spec_ctrl)
	41	+void x86_spec_ctrl_restore_host(u64 guest_virt_spec_ctrl)
42	42	{
43		− x86_virt_spec_ctrl(guest_spec_ctrl, guest_virt_spec_ctrl, false);
	43	+ x86_virt_spec_ctrl(guest_virt_spec_ctrl, false);
44	44	}
45	45
46	46	/* AMD specific Speculative Store Bypass MSR data */

arch/x86/kernel/asm-offsets.c+0−6

@@ -19,7 +19,6 @@ · 18 unmodified lines
19	19	#include <asm/suspend.h>
20	20	#include <asm/tlbflush.h>
21	21	#include <asm/tdx.h>
22		−#include "../kvm/vmx/vmx.h"
23	22
24	23	#ifdef CONFIG_XEN
25	24	#include <xen/interface/xen.h>
@@ -108,9 +107,4 @@ static void __used common(void) · 82 unmodified lines
108	107	OFFSET(TSS_sp0, tss_struct, x86_tss.sp0);
109	108	OFFSET(TSS_sp1, tss_struct, x86_tss.sp1);
110	109	OFFSET(TSS_sp2, tss_struct, x86_tss.sp2);
111		−
112		− if (IS_ENABLED(CONFIG_KVM_INTEL)) {
113		− BLANK();
114		− OFFSET(VMX_spec_ctrl, vcpu_vmx, spec_ctrl);
115		− }
116	110	}

arch/x86/kernel/cpu/bugs.c+4−11

@@ -196,22 +196,15 @@ void __init check_bugs(void) · 195 unmodified lines
196	196	}
197	197
198	198	/*
199		− * NOTE: This function is only called for SVM. VMX spec_ctrl handling is
200		− * done in vmenter.S.
	199	+ * NOTE: This function is only called for SVM, since Intel uses
	200	+ * MSR_IA32_SPEC_CTRL for SSBD.
201	201	*/
202	202	void
203		−x86_virt_spec_ctrl(u64 guest_spec_ctrl, u64 guest_virt_spec_ctrl, bool setguest)
	203	+x86_virt_spec_ctrl(u64 guest_virt_spec_ctrl, bool setguest)
204	204	{
205		− u64 msrval, guestval = guest_spec_ctrl, hostval = spec_ctrl_current();
	205	+ u64 guestval, hostval;
206	206	struct thread_info *ti = current_thread_info();
207	207
208		− if (static_cpu_has(X86_FEATURE_MSR_SPEC_CTRL)) {
209		− if (hostval != guestval) {
210		− msrval = setguest ? guestval : hostval;
211		− wrmsrl(MSR_IA32_SPEC_CTRL, msrval);
212		− }
213		− }
214		−
215	208	/*
216	209	* If SSBD is not handled in MSR_SPEC_CTRL on AMD, update
217	210	* MSR_AMD64_L2_CFG or MSR_VIRT_SPEC_CTRL if supported.

arch/x86/kernel/traps.c+7−0

@@ -15,6 +15,7 @@ · 14 unmodified lines
15	15	#include <linux/context_tracking.h>
16	16	#include <linux/interrupt.h>
17	17	#include <linux/kallsyms.h>
	18	+#include <linux/kmsan.h>
18	19	#include <linux/spinlock.h>
19	20	#include <linux/kprobes.h>
20	21	#include <linux/uaccess.h>
@@ -301,6 +302,12 @@ static noinstr bool handle_bug(struct pt_regs *regs) · 280 unmodified lines
301	302	{
302	303	bool handled = false;
303	304
	305	+ /*
	306	+ * Normally @regs are unpoisoned by irqentry_enter(), but handle_bug()
	307	+ * is a rare case that uses @regs without passing them to
	308	+ * irqentry_enter().
	309	+ */
	310	+ kmsan_unpoison_entry_regs(regs);
304	311	if (!is_valid_bugaddr(regs->ip))
305	312	return handled;
306	313

arch/x86/kvm/.gitignore+2−0

@@ -0,0 +1,2 @@
	1	+/kvm-asm-offsets.s
	2	+/kvm-asm-offsets.h

arch/x86/kvm/Makefile+12−0

@@ -34,3 +34,15 @@ endif · 33 unmodified lines
34	34	obj-$(CONFIG_KVM) += kvm.o
35	35	obj-$(CONFIG_KVM_INTEL) += kvm-intel.o
36	36	obj-$(CONFIG_KVM_AMD) += kvm-amd.o
	37	+
	38	+AFLAGS_svm/vmenter.o := -iquote $(obj)
	39	+$(obj)/svm/vmenter.o: $(obj)/kvm-asm-offsets.h
	40	+
	41	+AFLAGS_vmx/vmenter.o := -iquote $(obj)
	42	+$(obj)/vmx/vmenter.o: $(obj)/kvm-asm-offsets.h
	43	+
	44	+$(obj)/kvm-asm-offsets.h: $(obj)/kvm-asm-offsets.s FORCE
	45	+ $(call filechk,offsets,__KVM_ASM_OFFSETS_H__)
	46	+
	47	+targets += kvm-asm-offsets.s
	48	+clean-files += kvm-asm-offsets.h

arch/x86/kvm/kvm-asm-offsets.c+29−0

@@ -0,0 +1,29 @@
	1	+// SPDX-License-Identifier: GPL-2.0
	2	+/*
	3	+ * Generate definitions needed by assembly language modules.
	4	+ * This code generates raw asm output which is post-processed to extract
	5	+ * and format the required data.
	6	+ */
	7	+#define COMPILE_OFFSETS
	8	+
	9	+#include <linux/kbuild.h>
	10	+#include "vmx/vmx.h"
	11	+#include "svm/svm.h"
	12	+
	13	+static void __used common(void)
	14	+{
	15	+ if (IS_ENABLED(CONFIG_KVM_AMD)) {
	16	+ BLANK();
	17	+ OFFSET(SVM_vcpu_arch_regs, vcpu_svm, vcpu.arch.regs);
	18	+ OFFSET(SVM_current_vmcb, vcpu_svm, current_vmcb);
	19	+ OFFSET(SVM_spec_ctrl, vcpu_svm, spec_ctrl);
	20	+ OFFSET(SVM_vmcb01, vcpu_svm, vmcb01);
	21	+ OFFSET(KVM_VMCB_pa, kvm_vmcb_info, pa);
	22	+ OFFSET(SD_save_area_pa, svm_cpu_data, save_area_pa);
	23	+ }
	24	+
	25	+ if (IS_ENABLED(CONFIG_KVM_INTEL)) {
	26	+ BLANK();
	27	+ OFFSET(VMX_spec_ctrl, vcpu_vmx, spec_ctrl);
	28	+ }
	29	+}

arch/x86/kvm/mmu/mmu.c+2−2

@@ -6056,7 +6056,7 @@ void kvm_zap_gfn_range(struct kvm *kvm, gfn_t gfn_start, gfn_t gfn_end) · 6055 unmodified lines
6056	6056
6057	6057	write_lock(&kvm->mmu_lock);
6058	6058
6059		− kvm_mmu_invalidate_begin(kvm, gfn_start, gfn_end);
	6059	+ kvm_mmu_invalidate_begin(kvm, 0, -1ul);
6060	6060
6061	6061	flush = kvm_rmap_zap_gfn_range(kvm, gfn_start, gfn_end);
6062	6062
@@ -6070,7 +6070,7 @@ void kvm_zap_gfn_range(struct kvm *kvm, gfn_t gfn_start, gfn_t gfn_end) · 7 unmodified lines
6070	6070	kvm_flush_remote_tlbs_with_address(kvm, gfn_start,
6071	6071	gfn_end - gfn_start);
6072	6072
6073		− kvm_mmu_invalidate_end(kvm, gfn_start, gfn_end);
	6073	+ kvm_mmu_invalidate_end(kvm, 0, -1ul);
6074	6074
6075	6075	write_unlock(&kvm->mmu_lock);
6076	6076	}

arch/x86/kvm/pmu.c+1−1

@@ -56,7 +56,7 @@ static const struct x86_cpu_id vmx_icl_pebs_cpu[] = { · 55 unmodified lines
56	56	* code. Each pmc, stored in kvm_pmc.idx field, is unique across
57	57	* all perf counters (both gp and fixed). The mapping relationship
58	58	* between pmc and perf counters is as the following:
59		− * * Intel: [0 .. INTEL_PMC_MAX_GENERIC-1] <=> gp counters
	59	+ * * Intel: [0 .. KVM_INTEL_PMC_MAX_GENERIC-1] <=> gp counters
60	60	* [INTEL_PMC_IDX_FIXED .. INTEL_PMC_IDX_FIXED + 2] <=> fixed
61	61	* * AMD: [0 .. AMD64_NUM_COUNTERS-1] and, for families 15H
62	62	* and later, [0 .. AMD64_NUM_COUNTERS_CORE-1] <=> gp counters

arch/x86/kvm/svm/pmu.c+4−3

@@ -192,9 +192,10 @@ static void amd_pmu_init(struct kvm_vcpu *vcpu) · 191 unmodified lines
192	192	struct kvm_pmu *pmu = vcpu_to_pmu(vcpu);
193	193	int i;
194	194
195		− BUILD_BUG_ON(AMD64_NUM_COUNTERS_CORE > INTEL_PMC_MAX_GENERIC);
	195	+ BUILD_BUG_ON(KVM_AMD_PMC_MAX_GENERIC > AMD64_NUM_COUNTERS_CORE);
	196	+ BUILD_BUG_ON(KVM_AMD_PMC_MAX_GENERIC > INTEL_PMC_MAX_GENERIC);
196	197
197		− for (i = 0; i < AMD64_NUM_COUNTERS_CORE ; i++) {
	198	+ for (i = 0; i < KVM_AMD_PMC_MAX_GENERIC ; i++) {
198	199	pmu->gp_counters[i].type = KVM_PMC_GP;
199	200	pmu->gp_counters[i].vcpu = vcpu;
200	201	pmu->gp_counters[i].idx = i;
@@ -207,7 +208,7 @@ static void amd_pmu_reset(struct kvm_vcpu *vcpu) · 6 unmodified lines
207	208	struct kvm_pmu *pmu = vcpu_to_pmu(vcpu);
208	209	int i;
209	210
210		− for (i = 0; i < AMD64_NUM_COUNTERS_CORE; i++) {
	211	+ for (i = 0; i < KVM_AMD_PMC_MAX_GENERIC; i++) {
211	212	struct kvm_pmc *pmc = &pmu->gp_counters[i];
212	213
213	214	pmc_stop_counter(pmc);

arch/x86/kvm/svm/sev.c+3−3

@@ -196,7 +196,7 @@ static void sev_asid_free(struct kvm_sev_info *sev) · 195 unmodified lines
196	196	__set_bit(sev->asid, sev_reclaim_asid_bitmap);
197	197
198	198	for_each_possible_cpu(cpu) {
199		− sd = per_cpu(svm_data, cpu);
	199	+ sd = per_cpu_ptr(&svm_data, cpu);
200	200	sd->sev_vmcbs[sev->asid] = NULL;
201	201	}
202	202
@@ -605,7 +605,7 @@ static int sev_es_sync_vmsa(struct vcpu_svm *svm) · 402 unmodified lines
605	605	save->dr6 = svm->vcpu.arch.dr6;
606	606
607	607	pr_debug("Virtual Machine Save Area (VMSA):\n");
608		− print_hex_dump(KERN_CONT, "", DUMP_PREFIX_NONE, 16, 1, save, sizeof(*save), false);
	608	+ print_hex_dump_debug("", DUMP_PREFIX_NONE, 16, 1, save, sizeof(*save), false);
609	609
610	610	return 0;
611	611	}
@@ -2600,7 +2600,7 @@ void sev_es_unmap_ghcb(struct vcpu_svm *svm) · 1988 unmodified lines
2600	2600
2601	2601	void pre_sev_run(struct vcpu_svm *svm, int cpu)
2602	2602	{
2603		− struct svm_cpu_data *sd = per_cpu(svm_data, cpu);
	2603	+ struct svm_cpu_data *sd = per_cpu_ptr(&svm_data, cpu);
2604	2604	int asid = sev_get_asid(svm->vcpu.kvm);
2605	2605
2606	2606	/* Assign the asid allocated with this SEV guest */

arch/x86/kvm/svm/svm.c+36−69

@@ -245,7 +245,7 @@ struct kvm_ldttss_desc { · 244 unmodified lines
245	245	u32 zero1;
246	246	} __attribute__((packed));
247	247
248		−DEFINE_PER_CPU(struct svm_cpu_data *, svm_data);
	248	+DEFINE_PER_CPU(struct svm_cpu_data, svm_data);
249	249
250	250	/*
251	251	* Only MSR_TSC_AUX is switched via the user return hook. EFER is switched via
@@ -581,12 +581,7 @@ static int svm_hardware_enable(void) · 329 unmodified lines
581	581	pr_err("%s: err EOPNOTSUPP on %d\n", __func__, me);
582	582	return -EINVAL;
583	583	}
584		− sd = per_cpu(svm_data, me);
585		− if (!sd) {
586		− pr_err("%s: svm_data is NULL on %d\n", __func__, me);
587		− return -EINVAL;
588		− }
589		−
	584	+ sd = per_cpu_ptr(&svm_data, me);
590	585	sd->asid_generation = 1;
591	586	sd->max_asid = cpuid_ebx(SVM_CPUID_FUNC) - 1;
592	587	sd->next_asid = sd->max_asid + 1;
@@ -597,7 +592,7 @@ static int svm_hardware_enable(void) · 4 unmodified lines
597	592
598	593	wrmsrl(MSR_EFER, efer \| EFER_SVME);
599	594
600		− wrmsrl(MSR_VM_HSAVE_PA, __sme_page_pa(sd->save_area));
	595	+ wrmsrl(MSR_VM_HSAVE_PA, sd->save_area_pa);
601	596
602	597	if (static_cpu_has(X86_FEATURE_TSCRATEMSR)) {
603	598	/*
@@ -646,42 +641,37 @@ static int svm_hardware_enable(void) · 42 unmodified lines
646	641
647	642	static void svm_cpu_uninit(int cpu)
648	643	{
649		− struct svm_cpu_data *sd = per_cpu(svm_data, cpu);
	644	+ struct svm_cpu_data *sd = per_cpu_ptr(&svm_data, cpu);
650	645
651		− if (!sd)
	646	+ if (!sd->save_area)
652	647	return;
653	648
654		− per_cpu(svm_data, cpu) = NULL;
655	649	kfree(sd->sev_vmcbs);
656	650	__free_page(sd->save_area);
657		− kfree(sd);
	651	+ sd->save_area_pa = 0;
	652	+ sd->save_area = NULL;
658	653	}
659	654
660	655	static int svm_cpu_init(int cpu)
661	656	{
662		− struct svm_cpu_data *sd;
	657	+ struct svm_cpu_data *sd = per_cpu_ptr(&svm_data, cpu);
663	658	int ret = -ENOMEM;
664	659
665		− sd = kzalloc(sizeof(struct svm_cpu_data), GFP_KERNEL);
666		− if (!sd)
667		− return ret;
668		− sd->cpu = cpu;
	660	+ memset(sd, 0, sizeof(struct svm_cpu_data));
669	661	sd->save_area = alloc_page(GFP_KERNEL \| __GFP_ZERO);
670	662	if (!sd->save_area)
671		− goto free_cpu_data;
	663	+ return ret;
672	664
673	665	ret = sev_cpu_init(sd);
674	666	if (ret)
675	667	goto free_save_area;
676	668
677		− per_cpu(svm_data, cpu) = sd;
678		−
	669	+ sd->save_area_pa = __sme_page_pa(sd->save_area);
679	670	return 0;
680	671
681	672	free_save_area:
682	673	__free_page(sd->save_area);
683		−free_cpu_data:
684		− kfree(sd);
	674	+ sd->save_area = NULL;
685	675	return ret;
686	676
687	677	}
@@ -730,6 +720,15 @@ static bool msr_write_intercepted(struct kvm_vcpu *vcpu, u32 msr) · 42 unmodified lines
730	720	u32 offset;
731	721	u32 *msrpm;
732	722
	723	+ /*
	724	+ * For non-nested case:
	725	+ * If the L01 MSR bitmap does not intercept the MSR, then we need to
	726	+ * save it.
	727	+ *
	728	+ * For nested case:
	729	+ * If the L02 MSR bitmap does not intercept the MSR, then we need to
	730	+ * save it.
	731	+ */
733	732	msrpm = is_guest_mode(vcpu) ? to_svm(vcpu)->nested.msrpm:
734	733	to_svm(vcpu)->msrpm;
735	734
@@ -1425,7 +1424,7 @@ static void svm_clear_current_vmcb(struct vmcb *vmcb) · 689 unmodified lines
1425	1424	int i;
1426	1425
1427	1426	for_each_online_cpu(i)
1428		− cmpxchg(&per_cpu(svm_data, i)->current_vmcb, vmcb, NULL);
	1427	+ cmpxchg(per_cpu_ptr(&svm_data.current_vmcb, i), vmcb, NULL);
1429	1428	}
1430	1429
1431	1430	static void svm_vcpu_free(struct kvm_vcpu *vcpu)
@@ -1450,7 +1449,7 @@ static void svm_vcpu_free(struct kvm_vcpu *vcpu) · 18 unmodified lines
1450	1449	static void svm_prepare_switch_to_guest(struct kvm_vcpu *vcpu)
1451	1450	{
1452	1451	struct vcpu_svm *svm = to_svm(vcpu);
1453		− struct svm_cpu_data *sd = per_cpu(svm_data, vcpu->cpu);
	1452	+ struct svm_cpu_data *sd = per_cpu_ptr(&svm_data, vcpu->cpu);
1454	1453
1455	1454	if (sev_es_guest(vcpu->kvm))
1456	1455	sev_es_unmap_ghcb(svm);
@@ -1462,7 +1461,7 @@ static void svm_prepare_switch_to_guest(struct kvm_vcpu *vcpu) · 5 unmodified lines
1462	1461	* Save additional host state that will be restored on VMEXIT (sev-es)
1463	1462	* or subsequent vmload of host save area.
1464	1463	*/
1465		− vmsave(__sme_page_pa(sd->save_area));
	1464	+ vmsave(sd->save_area_pa);
1466	1465	if (sev_es_guest(vcpu->kvm)) {
1467	1466	struct sev_es_save_area *hostsa;
1468	1467	hostsa = (struct sev_es_save_area *)(page_address(sd->save_area) + 0x400);
@@ -1487,7 +1486,7 @@ static void svm_prepare_host_switch(struct kvm_vcpu *vcpu) · 18 unmodified lines
1487	1486	static void svm_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
1488	1487	{
1489	1488	struct vcpu_svm *svm = to_svm(vcpu);
1490		− struct svm_cpu_data *sd = per_cpu(svm_data, cpu);
	1489	+ struct svm_cpu_data *sd = per_cpu_ptr(&svm_data, cpu);
1491	1490
1492	1491	if (sd->current_vmcb != svm->vmcb) {
1493	1492	sd->current_vmcb = svm->vmcb;
@@ -3443,7 +3442,7 @@ static int svm_handle_exit(struct kvm_vcpu *vcpu, fastpath_t exit_fastpath) · 1949 unmodified lines
3443	3442
3444	3443	static void reload_tss(struct kvm_vcpu *vcpu)
3445	3444	{
3446		− struct svm_cpu_data *sd = per_cpu(svm_data, vcpu->cpu);
	3445	+ struct svm_cpu_data *sd = per_cpu_ptr(&svm_data, vcpu->cpu);
3447	3446
3448	3447	sd->tss_desc->type = 9; /* available 32/64-bit TSS */
3449	3448	load_TR_desc();
@@ -3451,7 +3450,7 @@ static void reload_tss(struct kvm_vcpu *vcpu) · 1 unmodified line
3451	3450
3452	3451	static void pre_svm_run(struct kvm_vcpu *vcpu)
3453	3452	{
3454		− struct svm_cpu_data *sd = per_cpu(svm_data, vcpu->cpu);
	3453	+ struct svm_cpu_data *sd = per_cpu_ptr(&svm_data, vcpu->cpu);
3455	3454	struct vcpu_svm *svm = to_svm(vcpu);
3456	3455
3457	3456	/*
@@ -3911,30 +3910,16 @@ static fastpath_t svm_exit_handlers_fastpath(struct kvm_vcpu *vcpu) · 453 unmodified lines
3911	3910	return EXIT_FASTPATH_NONE;
3912	3911	}
3913	3912
3914		−static noinstr void svm_vcpu_enter_exit(struct kvm_vcpu *vcpu)
	3913	+static noinstr void svm_vcpu_enter_exit(struct kvm_vcpu *vcpu, bool spec_ctrl_intercepted)
3915	3914	{
3916	3915	struct vcpu_svm *svm = to_svm(vcpu);
3917		− unsigned long vmcb_pa = svm->current_vmcb->pa;
3918	3916
3919	3917	guest_state_enter_irqoff();
3920	3918
3921		− if (sev_es_guest(vcpu->kvm)) {
3922		− __svm_sev_es_vcpu_run(vmcb_pa);
3923		− } else {
3924		− struct svm_cpu_data *sd = per_cpu(svm_data, vcpu->cpu);
3925		−
3926		− /*
3927		− * Use a single vmcb (vmcb01 because it's always valid) for
3928		− * context switching guest state via VMLOAD/VMSAVE, that way
3929		− * the state doesn't need to be copied between vmcb01 and
3930		− * vmcb02 when switching vmcbs for nested virtualization.
3931		− */
3932		− vmload(svm->vmcb01.pa);
3933		− __svm_vcpu_run(vmcb_pa, (unsigned long *)&vcpu->arch.regs);
3934		− vmsave(svm->vmcb01.pa);
3935		−
3936		− vmload(__sme_page_pa(sd->save_area));
3937		− }
	3919	+ if (sev_es_guest(vcpu->kvm))
	3920	+ __svm_sev_es_vcpu_run(svm, spec_ctrl_intercepted);
	3921	+ else
	3922	+ __svm_vcpu_run(svm, spec_ctrl_intercepted);
3938	3923
3939	3924	guest_state_exit_irqoff();
3940	3925	}
@@ -3942,6 +3927,7 @@ static noinstr void svm_vcpu_enter_exit(struct kvm_vcpu *vcpu) · 1 unmodified line
3942	3927	static __no_kcsan fastpath_t svm_vcpu_run(struct kvm_vcpu *vcpu)
3943	3928	{
3944	3929	struct vcpu_svm *svm = to_svm(vcpu);
	3930	+ bool spec_ctrl_intercepted = msr_write_intercepted(vcpu, MSR_IA32_SPEC_CTRL);
3945	3931
3946	3932	trace_kvm_entry(vcpu);
3947	3933
@@ -3998,34 +3984,15 @@ static __no_kcsan fastpath_t svm_vcpu_run(struct kvm_vcpu *vcpu) · 50 unmodified lines
3998	3984	* being speculatively taken.
3999	3985	*/
4000	3986	if (!static_cpu_has(X86_FEATURE_V_SPEC_CTRL))
4001		− x86_spec_ctrl_set_guest(svm->spec_ctrl, svm->virt_spec_ctrl);
	3987	+ x86_spec_ctrl_set_guest(svm->virt_spec_ctrl);
4002	3988
4003		− svm_vcpu_enter_exit(vcpu);
4004		−
4005		− /*
4006		− * We do not use IBRS in the kernel. If this vCPU has used the
4007		− * SPEC_CTRL MSR it may have left it on; save the value and
4008		− * turn it off. This is much more efficient than blindly adding
4009		− * it to the atomic save/restore list. Especially as the former
4010		− * (Saving guest MSRs on vmexit) doesn't even exist in KVM.
4011		− *
4012		− * For non-nested case:
4013		− * If the L01 MSR bitmap does not intercept the MSR, then we need to
4014		− * save it.
4015		− *
4016		− * For nested case:
4017		− * If the L02 MSR bitmap does not intercept the MSR, then we need to
4018		− * save it.
4019		− */
4020		− if (!static_cpu_has(X86_FEATURE_V_SPEC_CTRL) &&
4021		− unlikely(!msr_write_intercepted(vcpu, MSR_IA32_SPEC_CTRL)))
4022		− svm->spec_ctrl = native_read_msr(MSR_IA32_SPEC_CTRL);
	3989	+ svm_vcpu_enter_exit(vcpu, spec_ctrl_intercepted);
4023	3990
4024	3991	if (!sev_es_guest(vcpu->kvm))
4025	3992	reload_tss(vcpu);
4026	3993
4027	3994	if (!static_cpu_has(X86_FEATURE_V_SPEC_CTRL))
4028		− x86_spec_ctrl_restore_host(svm->spec_ctrl, svm->virt_spec_ctrl);
	3995	+ x86_spec_ctrl_restore_host(svm->virt_spec_ctrl);
4029	3996
4030	3997	if (!sev_es_guest(vcpu->kvm)) {
4031	3998	vcpu->arch.cr2 = svm->vmcb->save.cr2;

arch/x86/kvm/svm/svm.h+5−6

@@ -209,7 +209,6 @@ struct vcpu_svm { · 208 unmodified lines
209	209	struct vmcb *vmcb;
210	210	struct kvm_vmcb_info vmcb01;
211	211	struct kvm_vmcb_info *current_vmcb;
212		− struct svm_cpu_data *svm_data;
213	212	u32 asid;
214	213	u32 sysenter_esp_hi;
215	214	u32 sysenter_eip_hi;
@@ -281,8 +280,6 @@ struct vcpu_svm { · 65 unmodified lines
281	280	};
282	281
283	282	struct svm_cpu_data {
284		− int cpu;
285		−
286	283	u64 asid_generation;
287	284	u32 max_asid;
288	285	u32 next_asid;
@@ -290,13 +287,15 @@ struct svm_cpu_data { · 1 unmodified line
290	287	struct kvm_ldttss_desc *tss_desc;
291	288
292	289	struct page *save_area;
	290	+ unsigned long save_area_pa;
	291	+
293	292	struct vmcb *current_vmcb;
294	293
295	294	/* index = sev_asid, value = vmcb pointer */
296	295	struct vmcb **sev_vmcbs;
297	296	};
298	297
299		−DECLARE_PER_CPU(struct svm_cpu_data *, svm_data);
	298	+DECLARE_PER_CPU(struct svm_cpu_data, svm_data);
300	299
301	300	void recalc_intercepts(struct vcpu_svm *svm);
302	301
@@ -683,7 +682,7 @@ void sev_es_unmap_ghcb(struct vcpu_svm *svm); · 380 unmodified lines
683	682
684	683	/* vmenter.S */
685	684
686		−void __svm_sev_es_vcpu_run(unsigned long vmcb_pa);
687		−void __svm_vcpu_run(unsigned long vmcb_pa, unsigned long *regs);
	685	+void __svm_sev_es_vcpu_run(struct vcpu_svm *svm, bool spec_ctrl_intercepted);
	686	+void __svm_vcpu_run(struct vcpu_svm *svm, bool spec_ctrl_intercepted);
688	687
689	688	#endif

arch/x86/kvm/svm/svm_ops.h+0−5

@@ -61,9 +61,4 @@ static __always_inline void vmsave(unsigned long pa) · 60 unmodified lines
61	61	svm_asm1(vmsave, "a" (pa), "memory");
62	62	}
63	63
64		−static __always_inline void vmload(unsigned long pa)
65		−{
66		− svm_asm1(vmload, "a" (pa), "memory");
67		−}
68		−
69	64	#endif /* __KVM_X86_SVM_OPS_H */

arch/x86/kvm/svm/vmenter.S+209−51

@@ -4,35 +4,97 @@ · 3 unmodified lines
4	4	#include <asm/bitsperlong.h>
5	5	#include <asm/kvm_vcpu_regs.h>
6	6	#include <asm/nospec-branch.h>
	7	+#include "kvm-asm-offsets.h"
7	8
8	9	#define WORD_SIZE (BITS_PER_LONG / 8)
9	10
10	11	/* Intentionally omit RAX as it's context switched by hardware */
11		−#define VCPU_RCX __VCPU_REGS_RCX * WORD_SIZE
12		−#define VCPU_RDX __VCPU_REGS_RDX * WORD_SIZE
13		−#define VCPU_RBX __VCPU_REGS_RBX * WORD_SIZE
	12	+#define VCPU_RCX (SVM_vcpu_arch_regs + __VCPU_REGS_RCX * WORD_SIZE)
	13	+#define VCPU_RDX (SVM_vcpu_arch_regs + __VCPU_REGS_RDX * WORD_SIZE)
	14	+#define VCPU_RBX (SVM_vcpu_arch_regs + __VCPU_REGS_RBX * WORD_SIZE)
14	15	/* Intentionally omit RSP as it's context switched by hardware */
15		−#define VCPU_RBP __VCPU_REGS_RBP * WORD_SIZE
16		−#define VCPU_RSI __VCPU_REGS_RSI * WORD_SIZE
17		−#define VCPU_RDI __VCPU_REGS_RDI * WORD_SIZE
	16	+#define VCPU_RBP (SVM_vcpu_arch_regs + __VCPU_REGS_RBP * WORD_SIZE)
	17	+#define VCPU_RSI (SVM_vcpu_arch_regs + __VCPU_REGS_RSI * WORD_SIZE)
	18	+#define VCPU_RDI (SVM_vcpu_arch_regs + __VCPU_REGS_RDI * WORD_SIZE)
18	19
19	20	#ifdef CONFIG_X86_64
20		−#define VCPU_R8 __VCPU_REGS_R8 * WORD_SIZE
21		−#define VCPU_R9 __VCPU_REGS_R9 * WORD_SIZE
22		−#define VCPU_R10 __VCPU_REGS_R10 * WORD_SIZE
23		−#define VCPU_R11 __VCPU_REGS_R11 * WORD_SIZE
24		−#define VCPU_R12 __VCPU_REGS_R12 * WORD_SIZE
25		−#define VCPU_R13 __VCPU_REGS_R13 * WORD_SIZE
26		−#define VCPU_R14 __VCPU_REGS_R14 * WORD_SIZE
27		−#define VCPU_R15 __VCPU_REGS_R15 * WORD_SIZE
	21	+#define VCPU_R8 (SVM_vcpu_arch_regs + __VCPU_REGS_R8 * WORD_SIZE)
	22	+#define VCPU_R9 (SVM_vcpu_arch_regs + __VCPU_REGS_R9 * WORD_SIZE)
	23	+#define VCPU_R10 (SVM_vcpu_arch_regs + __VCPU_REGS_R10 * WORD_SIZE)
	24	+#define VCPU_R11 (SVM_vcpu_arch_regs + __VCPU_REGS_R11 * WORD_SIZE)
	25	+#define VCPU_R12 (SVM_vcpu_arch_regs + __VCPU_REGS_R12 * WORD_SIZE)
	26	+#define VCPU_R13 (SVM_vcpu_arch_regs + __VCPU_REGS_R13 * WORD_SIZE)
	27	+#define VCPU_R14 (SVM_vcpu_arch_regs + __VCPU_REGS_R14 * WORD_SIZE)
	28	+#define VCPU_R15 (SVM_vcpu_arch_regs + __VCPU_REGS_R15 * WORD_SIZE)
28	29	#endif
29	30
	31	+#define SVM_vmcb01_pa (SVM_vmcb01 + KVM_VMCB_pa)
	32	+
30	33	.section .noinstr.text, "ax"
31	34
	35	+.macro RESTORE_GUEST_SPEC_CTRL
	36	+ /* No need to do anything if SPEC_CTRL is unset or V_SPEC_CTRL is set */
	37	+ ALTERNATIVE_2 "", \
	38	+ "jmp 800f", X86_FEATURE_MSR_SPEC_CTRL, \
	39	+ "", X86_FEATURE_V_SPEC_CTRL
	40	+801:
	41	+.endm
	42	+.macro RESTORE_GUEST_SPEC_CTRL_BODY
	43	+800:
	44	+ /*
	45	+ * SPEC_CTRL handling: if the guest's SPEC_CTRL value differs from the
	46	+ * host's, write the MSR. This is kept out-of-line so that the common
	47	+ * case does not have to jump.
	48	+ *
	49	+ * IMPORTANT: To avoid RSB underflow attacks and any other nastiness,
	50	+ * there must not be any returns or indirect branches between this code
	51	+ * and vmentry.
	52	+ */
	53	+ movl SVM_spec_ctrl(%_ASM_DI), %eax
	54	+ cmp PER_CPU_VAR(x86_spec_ctrl_current), %eax
	55	+ je 801b
	56	+ mov $MSR_IA32_SPEC_CTRL, %ecx
	57	+ xor %edx, %edx
	58	+ wrmsr
	59	+ jmp 801b
	60	+.endm
	61	+
	62	+.macro RESTORE_HOST_SPEC_CTRL
	63	+ /* No need to do anything if SPEC_CTRL is unset or V_SPEC_CTRL is set */
	64	+ ALTERNATIVE_2 "", \
	65	+ "jmp 900f", X86_FEATURE_MSR_SPEC_CTRL, \
	66	+ "", X86_FEATURE_V_SPEC_CTRL
	67	+901:
	68	+.endm
	69	+.macro RESTORE_HOST_SPEC_CTRL_BODY
	70	+900:
	71	+ /* Same for after vmexit. */
	72	+ mov $MSR_IA32_SPEC_CTRL, %ecx
	73	+
	74	+ /*
	75	+ * Load the value that the guest had written into MSR_IA32_SPEC_CTRL,
	76	+ * if it was not intercepted during guest execution.
	77	+ */
	78	+ cmpb $0, (%_ASM_SP)
	79	+ jnz 998f
	80	+ rdmsr
	81	+ movl %eax, SVM_spec_ctrl(%_ASM_DI)
	82	+998:
	83	+
	84	+ /* Now restore the host value of the MSR if different from the guest's. */
	85	+ movl PER_CPU_VAR(x86_spec_ctrl_current), %eax
	86	+ cmp SVM_spec_ctrl(%_ASM_DI), %eax
	87	+ je 901b
	88	+ xor %edx, %edx
	89	+ wrmsr
	90	+ jmp 901b
	91	+.endm
	92	+
	93	+
32	94	/**
33	95	* __svm_vcpu_run - Run a vCPU via a transition to SVM guest mode
34		− * @vmcb_pa: unsigned long
35		− * @regs: unsigned long * (to guest registers)
	96	+ * @svm: struct vcpu_svm *
	97	+ * @spec_ctrl_intercepted: bool
36	98	*/
37	99	SYM_FUNC_START(__svm_vcpu_run)
38	100	push %_ASM_BP
@@ -47,49 +109,71 @@ SYM_FUNC_START(__svm_vcpu_run) · 8 unmodified lines
47	109	#endif
48	110	push %_ASM_BX
49	111
50		− /* Save @regs. */
	112	+ /*
	113	+ * Save variables needed after vmexit on the stack, in inverse
	114	+ * order compared to when they are needed.
	115	+ */
	116	+
	117	+ /* Accessed directly from the stack in RESTORE_HOST_SPEC_CTRL. */
51	118	push %_ASM_ARG2
52	119
53		− /* Save @vmcb. */
	120	+ /* Needed to restore access to percpu variables. */
	121	+ __ASM_SIZE(push) PER_CPU_VAR(svm_data + SD_save_area_pa)
	122	+
	123	+ /* Finally save @svm. */
54	124	push %_ASM_ARG1
55	125
56		− /* Move @regs to RAX. */
57		− mov %_ASM_ARG2, %_ASM_AX
	126	+.ifnc _ASM_ARG1, _ASM_DI
	127	+ /*
	128	+ * Stash @svm in RDI early. On 32-bit, arguments are in RAX, RCX
	129	+ * and RDX which are clobbered by RESTORE_GUEST_SPEC_CTRL.
	130	+ */
	131	+ mov %_ASM_ARG1, %_ASM_DI
	132	+.endif
	133	+
	134	+ /* Clobbers RAX, RCX, RDX. */
	135	+ RESTORE_GUEST_SPEC_CTRL
	136	+
	137	+ /*
	138	+ * Use a single vmcb (vmcb01 because it's always valid) for
	139	+ * context switching guest state via VMLOAD/VMSAVE, that way
	140	+ * the state doesn't need to be copied between vmcb01 and
	141	+ * vmcb02 when switching vmcbs for nested virtualization.
	142	+ */
	143	+ mov SVM_vmcb01_pa(%_ASM_DI), %_ASM_AX
	144	+1: vmload %_ASM_AX
	145	+2:
	146	+
	147	+ /* Get svm->current_vmcb->pa into RAX. */
	148	+ mov SVM_current_vmcb(%_ASM_DI), %_ASM_AX
	149	+ mov KVM_VMCB_pa(%_ASM_AX), %_ASM_AX
58	150
59	151	/* Load guest registers. */
60		− mov VCPU_RCX(%_ASM_AX), %_ASM_CX
61		− mov VCPU_RDX(%_ASM_AX), %_ASM_DX
62		− mov VCPU_RBX(%_ASM_AX), %_ASM_BX
63		− mov VCPU_RBP(%_ASM_AX), %_ASM_BP
64		− mov VCPU_RSI(%_ASM_AX), %_ASM_SI
65		− mov VCPU_RDI(%_ASM_AX), %_ASM_DI
	152	+ mov VCPU_RCX(%_ASM_DI), %_ASM_CX
	153	+ mov VCPU_RDX(%_ASM_DI), %_ASM_DX
	154	+ mov VCPU_RBX(%_ASM_DI), %_ASM_BX
	155	+ mov VCPU_RBP(%_ASM_DI), %_ASM_BP
	156	+ mov VCPU_RSI(%_ASM_DI), %_ASM_SI
66	157	#ifdef CONFIG_X86_64
67		− mov VCPU_R8 (%_ASM_AX), %r8
68		− mov VCPU_R9 (%_ASM_AX), %r9
69		− mov VCPU_R10(%_ASM_AX), %r10
70		− mov VCPU_R11(%_ASM_AX), %r11
71		− mov VCPU_R12(%_ASM_AX), %r12
72		− mov VCPU_R13(%_ASM_AX), %r13
73		− mov VCPU_R14(%_ASM_AX), %r14
74		− mov VCPU_R15(%_ASM_AX), %r15
	158	+ mov VCPU_R8 (%_ASM_DI), %r8
	159	+ mov VCPU_R9 (%_ASM_DI), %r9
	160	+ mov VCPU_R10(%_ASM_DI), %r10
	161	+ mov VCPU_R11(%_ASM_DI), %r11
	162	+ mov VCPU_R12(%_ASM_DI), %r12
	163	+ mov VCPU_R13(%_ASM_DI), %r13
	164	+ mov VCPU_R14(%_ASM_DI), %r14
	165	+ mov VCPU_R15(%_ASM_DI), %r15
75	166	#endif
76		−
77		− /* "POP" @vmcb to RAX. */
78		− pop %_ASM_AX
	167	+ mov VCPU_RDI(%_ASM_DI), %_ASM_DI
79	168
80	169	/* Enter guest mode */
81	170	sti
82	171
83		−1: vmrun %_ASM_AX
84		−
85		−2: cli
86		−
87		−#ifdef CONFIG_RETPOLINE
88		− /* IMPORTANT: Stuff the RSB immediately after VM-Exit, before RET! */
89		− FILL_RETURN_BUFFER %_ASM_AX, RSB_CLEAR_LOOPS, X86_FEATURE_RETPOLINE
90		−#endif
	172	+3: vmrun %_ASM_AX
	173	+4:
	174	+ cli
91	175
92		− /* "POP" @regs to RAX. */
	176	+ /* Pop @svm to RAX while it's the only available register. */
93	177	pop %_ASM_AX
94	178
95	179	/* Save all guest registers. */
@@ -110,6 +194,26 @@ SYM_FUNC_START(__svm_vcpu_run) · 14 unmodified lines
110	194	mov %r15, VCPU_R15(%_ASM_AX)
111	195	#endif
112	196
	197	+ /* @svm can stay in RDI from now on. */
	198	+ mov %_ASM_AX, %_ASM_DI
	199	+
	200	+ mov SVM_vmcb01_pa(%_ASM_DI), %_ASM_AX
	201	+5: vmsave %_ASM_AX
	202	+6:
	203	+
	204	+ /* Restores GSBASE among other things, allowing access to percpu data. */
	205	+ pop %_ASM_AX
	206	+7: vmload %_ASM_AX
	207	+8:
	208	+
	209	+#ifdef CONFIG_RETPOLINE
	210	+ /* IMPORTANT: Stuff the RSB immediately after VM-Exit, before RET! */
	211	+ FILL_RETURN_BUFFER %_ASM_AX, RSB_CLEAR_LOOPS, X86_FEATURE_RETPOLINE
	212	+#endif
	213	+
	214	+ /* Clobbers RAX, RCX, RDX. */
	215	+ RESTORE_HOST_SPEC_CTRL
	216	+
113	217	/*
114	218	* Mitigate RETBleed for AMD/Hygon Zen uarch. RET should be
115	219	* untrained as soon as we exit the VM and are back to the
@@ -145,6 +249,9 @@ SYM_FUNC_START(__svm_vcpu_run) · 29 unmodified lines
145	249	xor %r15d, %r15d
146	250	#endif
147	251
	252	+ /* "Pop" @spec_ctrl_intercepted. */
	253	+ pop %_ASM_BX
	254	+
148	255	pop %_ASM_BX
149	256
150	257	#ifdef CONFIG_X86_64
@@ -159,17 +266,33 @@ SYM_FUNC_START(__svm_vcpu_run) · 8 unmodified lines
159	266	pop %_ASM_BP
160	267	RET
161	268
162		−3: cmpb $0, kvm_rebooting
	269	+ RESTORE_GUEST_SPEC_CTRL_BODY
	270	+ RESTORE_HOST_SPEC_CTRL_BODY
	271	+
	272	+10: cmpb $0, kvm_rebooting
163	273	jne 2b
164	274	ud2
	275	+30: cmpb $0, kvm_rebooting
	276	+ jne 4b
	277	+ ud2
	278	+50: cmpb $0, kvm_rebooting
	279	+ jne 6b
	280	+ ud2
	281	+70: cmpb $0, kvm_rebooting
	282	+ jne 8b
	283	+ ud2
165	284
166		− _ASM_EXTABLE(1b, 3b)
	285	+ _ASM_EXTABLE(1b, 10b)
	286	+ _ASM_EXTABLE(3b, 30b)
	287	+ _ASM_EXTABLE(5b, 50b)
	288	+ _ASM_EXTABLE(7b, 70b)
167	289
168	290	SYM_FUNC_END(__svm_vcpu_run)
169	291
170	292	/**
171	293	* __svm_sev_es_vcpu_run - Run a SEV-ES vCPU via a transition to SVM guest mode
172		− * @vmcb_pa: unsigned long
	294	+ * @svm: struct vcpu_svm *
	295	+ * @spec_ctrl_intercepted: bool
173	296	*/
174	297	SYM_FUNC_START(__svm_sev_es_vcpu_run)
175	298	push %_ASM_BP
@@ -184,8 +307,31 @@ SYM_FUNC_START(__svm_sev_es_vcpu_run) · 8 unmodified lines
184	307	#endif
185	308	push %_ASM_BX
186	309
187		− /* Move @vmcb to RAX. */
188		− mov %_ASM_ARG1, %_ASM_AX
	310	+ /*
	311	+ * Save variables needed after vmexit on the stack, in inverse
	312	+ * order compared to when they are needed.
	313	+ */
	314	+
	315	+ /* Accessed directly from the stack in RESTORE_HOST_SPEC_CTRL. */
	316	+ push %_ASM_ARG2
	317	+
	318	+ /* Save @svm. */
	319	+ push %_ASM_ARG1
	320	+
	321	+.ifnc _ASM_ARG1, _ASM_DI
	322	+ /*
	323	+ * Stash @svm in RDI early. On 32-bit, arguments are in RAX, RCX
	324	+ * and RDX which are clobbered by RESTORE_GUEST_SPEC_CTRL.
	325	+ */
	326	+ mov %_ASM_ARG1, %_ASM_DI
	327	+.endif
	328	+
	329	+ /* Clobbers RAX, RCX, RDX. */
	330	+ RESTORE_GUEST_SPEC_CTRL
	331	+
	332	+ /* Get svm->current_vmcb->pa into RAX. */
	333	+ mov SVM_current_vmcb(%_ASM_DI), %_ASM_AX
	334	+ mov KVM_VMCB_pa(%_ASM_AX), %_ASM_AX
189	335
190	336	/* Enter guest mode */
191	337	sti
@@ -194,11 +340,17 @@ SYM_FUNC_START(__svm_sev_es_vcpu_run) · 2 unmodified lines
194	340
195	341	2: cli
196	342
	343	+ /* Pop @svm to RDI, guest registers have been saved already. */
	344	+ pop %_ASM_DI
	345	+
197	346	#ifdef CONFIG_RETPOLINE
198	347	/* IMPORTANT: Stuff the RSB immediately after VM-Exit, before RET! */
199	348	FILL_RETURN_BUFFER %_ASM_AX, RSB_CLEAR_LOOPS, X86_FEATURE_RETPOLINE
200	349	#endif
201	350
	351	+ /* Clobbers RAX, RCX, RDX. */
	352	+ RESTORE_HOST_SPEC_CTRL
	353	+
202	354	/*
203	355	* Mitigate RETBleed for AMD/Hygon Zen uarch. RET should be
204	356	* untrained as soon as we exit the VM and are back to the
@@ -208,6 +360,9 @@ SYM_FUNC_START(__svm_sev_es_vcpu_run) · 3 unmodified lines
208	360	*/
209	361	UNTRAIN_RET
210	362
	363	+ /* "Pop" @spec_ctrl_intercepted. */
	364	+ pop %_ASM_BX
	365	+
211	366	pop %_ASM_BX
212	367
213	368	#ifdef CONFIG_X86_64
@@ -222,6 +377,9 @@ SYM_FUNC_START(__svm_sev_es_vcpu_run) · 8 unmodified lines
222	377	pop %_ASM_BP
223	378	RET
224	379
	380	+ RESTORE_GUEST_SPEC_CTRL_BODY
	381	+ RESTORE_HOST_SPEC_CTRL_BODY
	382	+
225	383	3: cmpb $0, kvm_rebooting
226	384	jne 2b
227	385	ud2

arch/x86/kvm/vmx/pmu_intel.c+2−2

@@ -617,7 +617,7 @@ static void intel_pmu_init(struct kvm_vcpu *vcpu) · 616 unmodified lines
617	617	struct kvm_pmu *pmu = vcpu_to_pmu(vcpu);
618	618	struct lbr_desc *lbr_desc = vcpu_to_lbr_desc(vcpu);
619	619
620		− for (i = 0; i < INTEL_PMC_MAX_GENERIC; i++) {
	620	+ for (i = 0; i < KVM_INTEL_PMC_MAX_GENERIC; i++) {
621	621	pmu->gp_counters[i].type = KVM_PMC_GP;
622	622	pmu->gp_counters[i].vcpu = vcpu;
623	623	pmu->gp_counters[i].idx = i;
@@ -643,7 +643,7 @@ static void intel_pmu_reset(struct kvm_vcpu *vcpu) · 19 unmodified lines
643	643	struct kvm_pmc *pmc = NULL;
644	644	int i;
645	645
646		− for (i = 0; i < INTEL_PMC_MAX_GENERIC; i++) {
	646	+ for (i = 0; i < KVM_INTEL_PMC_MAX_GENERIC; i++) {
647	647	pmc = &pmu->gp_counters[i];
648	648
649	649	pmc_stop_counter(pmc);

arch/x86/kvm/vmx/vmenter.S+1−1

@@ -1,12 +1,12 @@
1	1	/* SPDX-License-Identifier: GPL-2.0 */
2	2	#include <linux/linkage.h>
3	3	#include <asm/asm.h>
4		−#include <asm/asm-offsets.h>
5	4	#include <asm/bitsperlong.h>
6	5	#include <asm/kvm_vcpu_regs.h>
7	6	#include <asm/nospec-branch.h>
8	7	#include <asm/percpu.h>
9	8	#include <asm/segment.h>
	9	+#include "kvm-asm-offsets.h"
10	10	#include "run_flags.h"
11	11
12	12	#define WORD_SIZE (BITS_PER_LONG / 8)

arch/x86/kvm/x86.c+10−15

@@ -1438,32 +1438,27 @@ static const u32 msrs_to_save_all[] = { · 1437 unmodified lines
1438	1438	MSR_ARCH_PERFMON_FIXED_CTR0 + 2,
1439	1439	MSR_CORE_PERF_FIXED_CTR_CTRL, MSR_CORE_PERF_GLOBAL_STATUS,
1440	1440	MSR_CORE_PERF_GLOBAL_CTRL, MSR_CORE_PERF_GLOBAL_OVF_CTRL,
	1441	+ MSR_IA32_PEBS_ENABLE, MSR_IA32_DS_AREA, MSR_PEBS_DATA_CFG,
	1442	+
	1443	+ /* This part of MSRs should match KVM_INTEL_PMC_MAX_GENERIC. */
1441	1444	MSR_ARCH_PERFMON_PERFCTR0, MSR_ARCH_PERFMON_PERFCTR1,
1442	1445	MSR_ARCH_PERFMON_PERFCTR0 + 2, MSR_ARCH_PERFMON_PERFCTR0 + 3,
1443	1446	MSR_ARCH_PERFMON_PERFCTR0 + 4, MSR_ARCH_PERFMON_PERFCTR0 + 5,
1444	1447	MSR_ARCH_PERFMON_PERFCTR0 + 6, MSR_ARCH_PERFMON_PERFCTR0 + 7,
1445		− MSR_ARCH_PERFMON_PERFCTR0 + 8, MSR_ARCH_PERFMON_PERFCTR0 + 9,
1446		− MSR_ARCH_PERFMON_PERFCTR0 + 10, MSR_ARCH_PERFMON_PERFCTR0 + 11,
1447		− MSR_ARCH_PERFMON_PERFCTR0 + 12, MSR_ARCH_PERFMON_PERFCTR0 + 13,
1448		− MSR_ARCH_PERFMON_PERFCTR0 + 14, MSR_ARCH_PERFMON_PERFCTR0 + 15,
1449		− MSR_ARCH_PERFMON_PERFCTR0 + 16, MSR_ARCH_PERFMON_PERFCTR0 + 17,
1450	1448	MSR_ARCH_PERFMON_EVENTSEL0, MSR_ARCH_PERFMON_EVENTSEL1,
1451	1449	MSR_ARCH_PERFMON_EVENTSEL0 + 2, MSR_ARCH_PERFMON_EVENTSEL0 + 3,
1452	1450	MSR_ARCH_PERFMON_EVENTSEL0 + 4, MSR_ARCH_PERFMON_EVENTSEL0 + 5,
1453	1451	MSR_ARCH_PERFMON_EVENTSEL0 + 6, MSR_ARCH_PERFMON_EVENTSEL0 + 7,
1454		− MSR_ARCH_PERFMON_EVENTSEL0 + 8, MSR_ARCH_PERFMON_EVENTSEL0 + 9,
1455		− MSR_ARCH_PERFMON_EVENTSEL0 + 10, MSR_ARCH_PERFMON_EVENTSEL0 + 11,
1456		− MSR_ARCH_PERFMON_EVENTSEL0 + 12, MSR_ARCH_PERFMON_EVENTSEL0 + 13,
1457		− MSR_ARCH_PERFMON_EVENTSEL0 + 14, MSR_ARCH_PERFMON_EVENTSEL0 + 15,
1458		− MSR_ARCH_PERFMON_EVENTSEL0 + 16, MSR_ARCH_PERFMON_EVENTSEL0 + 17,
1459		− MSR_IA32_PEBS_ENABLE, MSR_IA32_DS_AREA, MSR_PEBS_DATA_CFG,
1460	1452
1461	1453	MSR_K7_EVNTSEL0, MSR_K7_EVNTSEL1, MSR_K7_EVNTSEL2, MSR_K7_EVNTSEL3,
1462	1454	MSR_K7_PERFCTR0, MSR_K7_PERFCTR1, MSR_K7_PERFCTR2, MSR_K7_PERFCTR3,
	1455	+
	1456	+ /* This part of MSRs should match KVM_AMD_PMC_MAX_GENERIC. */
1463	1457	MSR_F15H_PERF_CTL0, MSR_F15H_PERF_CTL1, MSR_F15H_PERF_CTL2,
1464	1458	MSR_F15H_PERF_CTL3, MSR_F15H_PERF_CTL4, MSR_F15H_PERF_CTL5,
1465	1459	MSR_F15H_PERF_CTR0, MSR_F15H_PERF_CTR1, MSR_F15H_PERF_CTR2,
1466	1460	MSR_F15H_PERF_CTR3, MSR_F15H_PERF_CTR4, MSR_F15H_PERF_CTR5,
	1461	+
1467	1462	MSR_IA32_XFD, MSR_IA32_XFD_ERR,
1468	1463	};
1469	1464
@@ -7041,14 +7036,14 @@ static void kvm_init_msr_list(void) · 5571 unmodified lines
7041	7036	intel_pt_validate_hw_cap(PT_CAP_num_address_ranges) * 2)
7042	7037	continue;
7043	7038	break;
7044		− case MSR_ARCH_PERFMON_PERFCTR0 ... MSR_ARCH_PERFMON_PERFCTR0 + 17:
	7039	+ case MSR_ARCH_PERFMON_PERFCTR0 ... MSR_ARCH_PERFMON_PERFCTR_MAX:
7045	7040	if (msrs_to_save_all[i] - MSR_ARCH_PERFMON_PERFCTR0 >=
7046		− min(INTEL_PMC_MAX_GENERIC, kvm_pmu_cap.num_counters_gp))
	7041	+ min(KVM_INTEL_PMC_MAX_GENERIC, kvm_pmu_cap.num_counters_gp))
7047	7042	continue;
7048	7043	break;
7049		− case MSR_ARCH_PERFMON_EVENTSEL0 ... MSR_ARCH_PERFMON_EVENTSEL0 + 17:
	7044	+ case MSR_ARCH_PERFMON_EVENTSEL0 ... MSR_ARCH_PERFMON_EVENTSEL_MAX:
7050	7045	if (msrs_to_save_all[i] - MSR_ARCH_PERFMON_EVENTSEL0 >=
7051		− min(INTEL_PMC_MAX_GENERIC, kvm_pmu_cap.num_counters_gp))
	7046	+ min(KVM_INTEL_PMC_MAX_GENERIC, kvm_pmu_cap.num_counters_gp))
7052	7047	continue;
7053	7048	break;
7054	7049	case MSR_IA32_XFD:

arch/x86/lib/usercopy.c+3−0

@@ -6,6 +6,7 @@ · 5 unmodified lines
6	6
7	7	#include <linux/uaccess.h>
8	8	#include <linux/export.h>
	9	+#include <linux/instrumented.h>
9	10
10	11	#include <asm/tlbflush.h>
11	12
@@ -44,7 +45,9 @@ copy_from_user_nmi(void to, const void __user from, unsigned long n) · 32 unmodified lines
44	45	* called from other contexts.
45	46	*/
46	47	pagefault_disable();
	48	+ instrument_copy_from_user_before(to, from, n);
47	49	ret = raw_copy_from_user(to, from, n);
	50	+ instrument_copy_from_user_after(to, from, n, ret);
48	51	pagefault_enable();
49	52
50	53	return ret;

arch/x86/mm/hugetlbpage.c+4−0

@@ -37,8 +37,12 @@ int pmd_huge(pmd_t pmd) · 36 unmodified lines
37	37	*/
38	38	int pud_huge(pud_t pud)
39	39	{
	40	+#if CONFIG_PGTABLE_LEVELS > 2
40	41	return !pud_none(pud) &&
41	42	(pud_val(pud) & (_PAGE_PRESENT\|_PAGE_PSE)) != _PAGE_PRESENT;
	43	+#else
	44	+ return 0;
	45	+#endif
42	46	}
43	47
44	48	#ifdef CONFIG_HUGETLB_PAGE

block/bfq-cgroup.c+4−0

@@ -610,6 +610,10 @@ struct bfq_group bfq_bio_bfqg(struct bfq_data bfqd, struct bio *bio) · 609 unmodified lines
610	610	struct bfq_group *bfqg;
611	611
612	612	while (blkg) {
	613	+ if (!blkg->online) {
	614	+ blkg = blkg->parent;
	615	+ continue;
	616	+ }
613	617	bfqg = blkg_to_bfqg(blkg);
614	618	if (bfqg->online) {
615	619	bio_associate_blkg_from_css(bio, &blkg->blkcg->css);

block/sed-opal.c+28−4

@@ -87,8 +87,8 @@ struct opal_dev { · 86 unmodified lines
87	87	u64 lowest_lba;
88	88
89	89	size_t pos;
90		− u8 cmd[IO_BUFFER_LENGTH];
91		− u8 resp[IO_BUFFER_LENGTH];
	90	+ u8 *cmd;
	91	+ u8 *resp;
92	92
93	93	struct parsed_resp parsed;
94	94	size_t prev_d_len;
@@ -2175,6 +2175,8 @@ void free_opal_dev(struct opal_dev *dev) · 2080 unmodified lines
2175	2175	return;
2176	2176
2177	2177	clean_opal_dev(dev);
	2178	+ kfree(dev->resp);
	2179	+ kfree(dev->cmd);
2178	2180	kfree(dev);
2179	2181	}
2180	2182	EXPORT_SYMBOL(free_opal_dev);
@@ -2187,6 +2189,18 @@ struct opal_dev init_opal_dev(void data, sec_send_recv *send_recv) · 6 unmodified lines
2187	2189	if (!dev)
2188	2190	return NULL;
2189	2191
	2192	+ /*
	2193	+ * Presumably DMA-able buffers must be cache-aligned. Kmalloc makes
	2194	+ * sure the allocated buffer is DMA-safe in that regard.
	2195	+ */
	2196	+ dev->cmd = kmalloc(IO_BUFFER_LENGTH, GFP_KERNEL);
	2197	+ if (!dev->cmd)
	2198	+ goto err_free_dev;
	2199	+
	2200	+ dev->resp = kmalloc(IO_BUFFER_LENGTH, GFP_KERNEL);
	2201	+ if (!dev->resp)
	2202	+ goto err_free_cmd;
	2203	+
2190	2204	INIT_LIST_HEAD(&dev->unlk_lst);
2191	2205	mutex_init(&dev->dev_lock);
2192	2206	dev->flags = 0;
@@ -2194,11 +2208,21 @@ struct opal_dev init_opal_dev(void data, sec_send_recv *send_recv) · 1 unmodified line
2194	2208	dev->send_recv = send_recv;
2195	2209	if (check_opal_support(dev) != 0) {
2196	2210	pr_debug("Opal is not supported on this device\n");
2197		− kfree(dev);
2198		− return NULL;
	2211	+ goto err_free_resp;
2199	2212	}
2200	2213
2201	2214	return dev;
	2215	+
	2216	+err_free_resp:
	2217	+ kfree(dev->resp);
	2218	+
	2219	+err_free_cmd:
	2220	+ kfree(dev->cmd);
	2221	+
	2222	+err_free_dev:
	2223	+ kfree(dev);
	2224	+
	2225	+ return NULL;
2202	2226	}
2203	2227	EXPORT_SYMBOL(init_opal_dev);
2204	2228

drivers/acpi/video_detect.c+32−9

@@ -645,6 +645,20 @@ static const struct dmi_system_id video_detect_dmi_table[] = { · 644 unmodified lines
645	645	},
646	646	},
647	647
	648	+ /*
	649	+ * Models which have nvidia-ec-wmi support, but should not use it.
	650	+ * Note this indicates a likely firmware bug on these models and should
	651	+ * be revisited if/when Linux gets support for dynamic mux mode.
	652	+ */
	653	+ {
	654	+ .callback = video_detect_force_native,
	655	+ /* Dell G15 5515 */
	656	+ .matches = {
	657	+ DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
	658	+ DMI_MATCH(DMI_PRODUCT_NAME, "Dell G15 5515"),
	659	+ },
	660	+ },
	661	+
648	662	/*
649	663	* Desktops which falsely report a backlight and which our heuristics
650	664	* for this do not catch.
@@ -670,7 +684,7 @@ static const struct dmi_system_id video_detect_dmi_table[] = { · 19 unmodified lines
670	684
671	685	static bool google_cros_ec_present(void)
672	686	{
673		− return acpi_dev_found("GOOG0004");
	687	+ return acpi_dev_found("GOOG0004") \|\| acpi_dev_found("GOOG000C");
674	688	}
675	689
676	690	/*
@@ -718,6 +732,10 @@ static enum acpi_backlight_type __acpi_video_get_backlight_type(bool native) · 41 unmodified lines
718	732	if (apple_gmux_present())
719	733	return acpi_backlight_apple_gmux;
720	734
	735	+ /* Chromebooks should always prefer native backlight control. */
	736	+ if (google_cros_ec_present() && native_available)
	737	+ return acpi_backlight_native;
	738	+
721	739	/* On systems with ACPI video use either native or ACPI video. */
722	740	if (video_caps & ACPI_VIDEO_BACKLIGHT) {
723	741	/*
@@ -735,13 +753,6 @@ static enum acpi_backlight_type __acpi_video_get_backlight_type(bool native) · 11 unmodified lines
735	753	return acpi_backlight_video;
736	754	}
737	755
738		− /*
739		− * Chromebooks that don't have backlight handle in ACPI table
740		− * are supposed to use native backlight if it's available.
741		− */
742		− if (google_cros_ec_present() && native_available)
743		− return acpi_backlight_native;
744		−
745	756	/* No ACPI video (old hw), use vendor specific fw methods. */
746	757	return acpi_backlight_vendor;
747	758	}
@@ -754,6 +765,18 @@ EXPORT_SYMBOL(acpi_video_get_backlight_type); · 6 unmodified lines
754	765
755	766	bool acpi_video_backlight_use_native(void)
756	767	{
757		− return __acpi_video_get_backlight_type(true) == acpi_backlight_native;
	768	+ /*
	769	+ * Call __acpi_video_get_backlight_type() to let it know that
	770	+ * a native backlight is available.
	771	+ */
	772	+ __acpi_video_get_backlight_type(true);
	773	+
	774	+ /*
	775	+ * For now just always return true. There is a whole bunch of laptop
	776	+ * models where (video_caps & ACPI_VIDEO_BACKLIGHT) is false causing
	777	+ * __acpi_video_get_backlight_type() to return vendor, while these
	778	+ * models only have a native backlight control.
	779	+ */
	780	+ return true;
758	781	}
759	782	EXPORT_SYMBOL(acpi_video_backlight_use_native);

drivers/ata/libata-scsi.c+13−0

@@ -3264,6 +3264,7 @@ static unsigned int ata_scsiop_maint_in(struct ata_scsi_args args, u8 rbuf) · 3263 unmodified lines
3264	3264	case REPORT_LUNS:
3265	3265	case REQUEST_SENSE:
3266	3266	case SYNCHRONIZE_CACHE:
	3267	+ case SYNCHRONIZE_CACHE_16:
3267	3268	case REZERO_UNIT:
3268	3269	case SEEK_6:
3269	3270	case SEEK_10:
@@ -3922,6 +3923,7 @@ static inline ata_xlat_func_t ata_get_xlat_func(struct ata_device *dev, u8 cmd) · 652 unmodified lines
3922	3923	return ata_scsi_write_same_xlat;
3923	3924
3924	3925	case SYNCHRONIZE_CACHE:
	3926	+ case SYNCHRONIZE_CACHE_16:
3925	3927	if (ata_try_flush_cache(dev))
3926	3928	return ata_scsi_flush_xlat;
3927	3929	break;
@@ -3962,9 +3964,19 @@ static inline ata_xlat_func_t ata_get_xlat_func(struct ata_device *dev, u8 cmd) · 34 unmodified lines
3962	3964
3963	3965	int __ata_scsi_queuecmd(struct scsi_cmnd scmd, struct ata_device dev)
3964	3966	{
	3967	+ struct ata_port *ap = dev->link->ap;
3965	3968	u8 scsi_op = scmd->cmnd[0];
3966	3969	ata_xlat_func_t xlat_func;
3967	3970
	3971	+ /*
	3972	+ * scsi_queue_rq() will defer commands if scsi_host_in_recovery().
	3973	+ * However, this check is done without holding the ap->lock (a libata
	3974	+ * specific lock), so we can have received an error irq since then,
	3975	+ * therefore we must check if EH is pending, while holding ap->lock.
	3976	+ */
	3977	+ if (ap->pflags & (ATA_PFLAG_EH_PENDING \| ATA_PFLAG_EH_IN_PROGRESS))
	3978	+ return SCSI_MLQUEUE_DEVICE_BUSY;
	3979	+
3968	3980	if (unlikely(!scmd->cmd_len))
3969	3981	goto bad_cdb_len;
3970	3982
@@ -4145,6 +4157,7 @@ void ata_scsi_simulate(struct ata_device dev, struct scsi_cmnd cmd) · 174 unmodified lines
4145	4157	* turning this into a no-op.
4146	4158	*/
4147	4159	case SYNCHRONIZE_CACHE:
	4160	+ case SYNCHRONIZE_CACHE_16:
4148	4161	fallthrough;
4149	4162
4150	4163	/* no-op's, complete with success */

drivers/ata/libata-transport.c+15−4

@@ -301,7 +301,9 @@ int ata_tport_add(struct device *parent, · 300 unmodified lines
301	301	pm_runtime_enable(dev);
302	302	pm_runtime_forbid(dev);
303	303
304		− transport_add_device(dev);
	304	+ error = transport_add_device(dev);
	305	+ if (error)
	306	+ goto tport_transport_add_err;
305	307	transport_configure_device(dev);
306	308
307	309	error = ata_tlink_add(&ap->link);
@@ -312,12 +314,12 @@ int ata_tport_add(struct device *parent, · 4 unmodified lines
312	314
313	315	tport_link_err:
314	316	transport_remove_device(dev);
	317	+ tport_transport_add_err:
315	318	device_del(dev);
316	319
317	320	tport_err:
318	321	transport_destroy_device(dev);
319	322	put_device(dev);
320		− ata_host_put(ap->host);
321	323	return error;
322	324	}
323	325
@@ -456,7 +458,9 @@ int ata_tlink_add(struct ata_link *link) · 132 unmodified lines
456	458	goto tlink_err;
457	459	}
458	460
459		− transport_add_device(dev);
	461	+ error = transport_add_device(dev);
	462	+ if (error)
	463	+ goto tlink_transport_err;
460	464	transport_configure_device(dev);
461	465
462	466	ata_for_each_dev(ata_dev, link, ALL) {
@@ -471,6 +475,7 @@ int ata_tlink_add(struct ata_link *link) · 8 unmodified lines
471	475	ata_tdev_delete(ata_dev);
472	476	}
473	477	transport_remove_device(dev);
	478	+ tlink_transport_err:
474	479	device_del(dev);
475	480	tlink_err:
476	481	transport_destroy_device(dev);
@@ -708,7 +713,13 @@ static int ata_tdev_add(struct ata_device *ata_dev) · 231 unmodified lines
708	713	return error;
709	714	}
710	715
711		− transport_add_device(dev);
	716	+ error = transport_add_device(dev);
	717	+ if (error) {
	718	+ device_del(dev);
	719	+ ata_tdev_free(ata_dev);
	720	+ return error;
	721	+ }
	722	+
712	723	transport_configure_device(dev);
713	724	return 0;
714	725	}

drivers/clocksource/hyperv_timer.c+15−14

@@ -21,6 +21,7 @@ · 20 unmodified lines
21	21	#include <linux/interrupt.h>
22	22	#include <linux/irq.h>
23	23	#include <linux/acpi.h>
	24	+#include <linux/hyperv.h>
24	25	#include <clocksource/hyperv_timer.h>
25	26	#include <asm/hyperv-tlfs.h>
26	27	#include <asm/mshyperv.h>
@@ -395,25 +396,25 @@ static u64 notrace read_hv_sched_clock_tsc(void) · 368 unmodified lines
395	396
396	397	static void suspend_hv_clock_tsc(struct clocksource *arg)
397	398	{
398		− u64 tsc_msr;
	399	+ union hv_reference_tsc_msr tsc_msr;
399	400
400	401	/* Disable the TSC page */
401		− tsc_msr = hv_get_register(HV_REGISTER_REFERENCE_TSC);
402		− tsc_msr &= ~BIT_ULL(0);
403		− hv_set_register(HV_REGISTER_REFERENCE_TSC, tsc_msr);
	402	+ tsc_msr.as_uint64 = hv_get_register(HV_REGISTER_REFERENCE_TSC);
	403	+ tsc_msr.enable = 0;
	404	+ hv_set_register(HV_REGISTER_REFERENCE_TSC, tsc_msr.as_uint64);
404	405	}
405	406
406	407
407	408	static void resume_hv_clock_tsc(struct clocksource *arg)
408	409	{
409	410	phys_addr_t phys_addr = virt_to_phys(&tsc_pg);
410		− u64 tsc_msr;
	411	+ union hv_reference_tsc_msr tsc_msr;
411	412
412	413	/* Re-enable the TSC page */
413		− tsc_msr = hv_get_register(HV_REGISTER_REFERENCE_TSC);
414		− tsc_msr &= GENMASK_ULL(11, 0);
415		− tsc_msr \|= BIT_ULL(0) \| (u64)phys_addr;
416		− hv_set_register(HV_REGISTER_REFERENCE_TSC, tsc_msr);
	414	+ tsc_msr.as_uint64 = hv_get_register(HV_REGISTER_REFERENCE_TSC);
	415	+ tsc_msr.enable = 1;
	416	+ tsc_msr.pfn = HVPFN_DOWN(phys_addr);
	417	+ hv_set_register(HV_REGISTER_REFERENCE_TSC, tsc_msr.as_uint64);
417	418	}
418	419
419	420	#ifdef HAVE_VDSO_CLOCKMODE_HVCLOCK
@@ -495,7 +496,7 @@ static __always_inline void hv_setup_sched_clock(void *sched_clock) {} · 75 unmodified lines
495	496
496	497	static bool __init hv_init_tsc_clocksource(void)
497	498	{
498		− u64 tsc_msr;
	499	+ union hv_reference_tsc_msr tsc_msr;
499	500	phys_addr_t phys_addr;
500	501
501	502	if (!(ms_hyperv.features & HV_MSR_REFERENCE_TSC_AVAILABLE))
@@ -530,10 +531,10 @@ static bool __init hv_init_tsc_clocksource(void) · 28 unmodified lines
530	531	* (which already has at least the low 12 bits set to zero since
531	532	* it is page aligned). Also set the "enable" bit, which is bit 0.
532	533	*/
533		− tsc_msr = hv_get_register(HV_REGISTER_REFERENCE_TSC);
534		− tsc_msr &= GENMASK_ULL(11, 0);
535		− tsc_msr = tsc_msr \| 0x1 \| (u64)phys_addr;
536		− hv_set_register(HV_REGISTER_REFERENCE_TSC, tsc_msr);
	534	+ tsc_msr.as_uint64 = hv_get_register(HV_REGISTER_REFERENCE_TSC);
	535	+ tsc_msr.enable = 1;
	536	+ tsc_msr.pfn = HVPFN_DOWN(phys_addr);
	537	+ hv_set_register(HV_REGISTER_REFERENCE_TSC, tsc_msr.as_uint64);
537	538
538	539	clocksource_register_hz(&hyperv_cs_tsc, NSEC_PER_SEC/100);
539	540

drivers/dma/apple-admac.c+1−1

@@ -493,7 +493,7 @@ static struct dma_chan admac_dma_of_xlate(struct of_phandle_args dma_spec, · 492 unmodified lines
493	493	return NULL;
494	494	}
495	495
496		− return &ad->channels[index].chan;
	496	+ return dma_get_slave_channel(&ad->channels[index].chan);
497	497	}
498	498
499	499	static int admac_drain_reports(struct admac_data *ad, int channo)

drivers/dma/at_hdmac.c+60−93

@@ -256,6 +256,8 @@ static void atc_dostart(struct at_dma_chan atchan, struct at_desc first) · 255 unmodified lines
256	256	ATC_SPIP_BOUNDARY(first->boundary));
257	257	channel_writel(atchan, DPIP, ATC_DPIP_HOLE(first->dst_hole) \|
258	258	ATC_DPIP_BOUNDARY(first->boundary));
	259	+ /* Don't allow CPU to reorder channel enable. */
	260	+ wmb();
259	261	dma_writel(atdma, CHER, atchan->mask);
260	262
261	263	vdbg_dump_regs(atchan);
@@ -316,7 +318,8 @@ static int atc_get_bytes_left(struct dma_chan *chan, dma_cookie_t cookie) · 54 unmodified lines
316	318	struct at_desc *desc_first = atc_first_active(atchan);
317	319	struct at_desc *desc;
318	320	int ret;
319		− u32 ctrla, dscr, trials;
	321	+ u32 ctrla, dscr;
	322	+ unsigned int i;
320	323
321	324	/*
322	325	* If the cookie doesn't match to the currently running transfer then
@@ -386,7 +389,7 @@ static int atc_get_bytes_left(struct dma_chan *chan, dma_cookie_t cookie) · 63 unmodified lines
386	389	dscr = channel_readl(atchan, DSCR);
387	390	rmb(); /* ensure DSCR is read before CTRLA */
388	391	ctrla = channel_readl(atchan, CTRLA);
389		− for (trials = 0; trials < ATC_MAX_DSCR_TRIALS; ++trials) {
	392	+ for (i = 0; i < ATC_MAX_DSCR_TRIALS; ++i) {
390	393	u32 new_dscr;
391	394
392	395	rmb(); /* ensure DSCR is read after CTRLA */
@@ -412,7 +415,7 @@ static int atc_get_bytes_left(struct dma_chan *chan, dma_cookie_t cookie) · 19 unmodified lines
412	415	rmb(); /* ensure DSCR is read before CTRLA */
413	416	ctrla = channel_readl(atchan, CTRLA);
414	417	}
415		− if (unlikely(trials >= ATC_MAX_DSCR_TRIALS))
	418	+ if (unlikely(i == ATC_MAX_DSCR_TRIALS))
416	419	return -ETIMEDOUT;
417	420
418	421	/* for the first descriptor we can be more accurate */
@@ -462,18 +465,6 @@ atc_chain_complete(struct at_dma_chan atchan, struct at_desc desc) · 43 unmodified lines
462	465	if (!atc_chan_is_cyclic(atchan))
463	466	dma_cookie_complete(txd);
464	467
465		− /* If the transfer was a memset, free our temporary buffer */
466		− if (desc->memset_buffer) {
467		− dma_pool_free(atdma->memset_pool, desc->memset_vaddr,
468		− desc->memset_paddr);
469		− desc->memset_buffer = false;
470		− }
471		−
472		− /* move children to free_list */
473		− list_splice_init(&desc->tx_list, &atchan->free_list);
474		− /* move myself to free_list */
475		− list_move(&desc->desc_node, &atchan->free_list);
476		−
477	468	spin_unlock_irqrestore(&atchan->lock, flags);
478	469
479	470	dma_descriptor_unmap(txd);
@@ -483,42 +474,20 @@ atc_chain_complete(struct at_dma_chan atchan, struct at_desc desc) · 3 unmodified lines
483	474	dmaengine_desc_get_callback_invoke(txd, NULL);
484	475
485	476	dma_run_dependencies(txd);
486		−}
487		−
488		−/**
489		− * atc_complete_all - finish work for all transactions
490		− * @atchan: channel to complete transactions for
491		− *
492		− * Eventually submit queued descriptors if any
493		− *
494		− * Assume channel is idle while calling this function
495		− * Called with atchan->lock held and bh disabled
496		− */
497		−static void atc_complete_all(struct at_dma_chan *atchan)
498		−{
499		− struct at_desc desc, _desc;
500		− LIST_HEAD(list);
501		− unsigned long flags;
502		−
503		− dev_vdbg(chan2dev(&atchan->chan_common), "complete all\n");
504	477
505	478	spin_lock_irqsave(&atchan->lock, flags);
506		−
507		− /*
508		− * Submit queued descriptors ASAP, i.e. before we go through
509		− * the completed ones.
510		− */
511		− if (!list_empty(&atchan->queue))
512		− atc_dostart(atchan, atc_first_queued(atchan));
513		− /* empty active_list now it is completed */
514		− list_splice_init(&atchan->active_list, &list);
515		− /* empty queue list by moving descriptors (if any) to active_list */
516		− list_splice_init(&atchan->queue, &atchan->active_list);
517		−
	479	+ /* move children to free_list */
	480	+ list_splice_init(&desc->tx_list, &atchan->free_list);
	481	+ /* add myself to free_list */
	482	+ list_add(&desc->desc_node, &atchan->free_list);
518	483	spin_unlock_irqrestore(&atchan->lock, flags);
519	484
520		− list_for_each_entry_safe(desc, _desc, &list, desc_node)
521		− atc_chain_complete(atchan, desc);
	485	+ /* If the transfer was a memset, free our temporary buffer */
	486	+ if (desc->memset_buffer) {
	487	+ dma_pool_free(atdma->memset_pool, desc->memset_vaddr,
	488	+ desc->memset_paddr);
	489	+ desc->memset_buffer = false;
	490	+ }
522	491	}
523	492
524	493	/**
@@ -527,26 +496,28 @@ static void atc_complete_all(struct at_dma_chan *atchan) · 2 unmodified lines
527	496	*/
528	497	static void atc_advance_work(struct at_dma_chan *atchan)
529	498	{
	499	+ struct at_desc *desc;
530	500	unsigned long flags;
531		− int ret;
532	501
533	502	dev_vdbg(chan2dev(&atchan->chan_common), "advance_work\n");
534	503
535	504	spin_lock_irqsave(&atchan->lock, flags);
536		− ret = atc_chan_is_enabled(atchan);
537		− spin_unlock_irqrestore(&atchan->lock, flags);
538		− if (ret)
539		− return;
540		−
541		− if (list_empty(&atchan->active_list) \|\|
542		− list_is_singular(&atchan->active_list))
543		− return atc_complete_all(atchan);
	505	+ if (atc_chan_is_enabled(atchan) \|\| list_empty(&atchan->active_list))
	506	+ return spin_unlock_irqrestore(&atchan->lock, flags);
544	507
545		− atc_chain_complete(atchan, atc_first_active(atchan));
	508	+ desc = atc_first_active(atchan);
	509	+ /* Remove the transfer node from the active list. */
	510	+ list_del_init(&desc->desc_node);
	511	+ spin_unlock_irqrestore(&atchan->lock, flags);
	512	+ atc_chain_complete(atchan, desc);
546	513
547	514	/* advance work */
548	515	spin_lock_irqsave(&atchan->lock, flags);
549		− atc_dostart(atchan, atc_first_active(atchan));
	516	+ if (!list_empty(&atchan->active_list)) {
	517	+ desc = atc_first_queued(atchan);
	518	+ list_move_tail(&desc->desc_node, &atchan->active_list);
	519	+ atc_dostart(atchan, desc);
	520	+ }
550	521	spin_unlock_irqrestore(&atchan->lock, flags);
551	522	}
552	523
@@ -558,6 +529,7 @@ static void atc_advance_work(struct at_dma_chan *atchan) · 5 unmodified lines
558	529	static void atc_handle_error(struct at_dma_chan *atchan)
559	530	{
560	531	struct at_desc *bad_desc;
	532	+ struct at_desc *desc;
561	533	struct at_desc *child;
562	534	unsigned long flags;
563	535
@@ -570,13 +542,12 @@ static void atc_handle_error(struct at_dma_chan *atchan) · 6 unmodified lines
570	542	bad_desc = atc_first_active(atchan);
571	543	list_del_init(&bad_desc->desc_node);
572	544
573		− /* As we are stopped, take advantage to push queued descriptors
574		− * in active_list */
575		− list_splice_init(&atchan->queue, atchan->active_list.prev);
576		−
577	545	/* Try to restart the controller */
578		− if (!list_empty(&atchan->active_list))
579		− atc_dostart(atchan, atc_first_active(atchan));
	546	+ if (!list_empty(&atchan->active_list)) {
	547	+ desc = atc_first_queued(atchan);
	548	+ list_move_tail(&desc->desc_node, &atchan->active_list);
	549	+ atc_dostart(atchan, desc);
	550	+ }
580	551
581	552	/*
582	553	* KERN_CRITICAL may seem harsh, but since this only happens
@@ -691,19 +662,11 @@ static dma_cookie_t atc_tx_submit(struct dma_async_tx_descriptor *tx) · 108 unmodified lines
691	662	spin_lock_irqsave(&atchan->lock, flags);
692	663	cookie = dma_cookie_assign(tx);
693	664
694		− if (list_empty(&atchan->active_list)) {
695		− dev_vdbg(chan2dev(tx->chan), "tx_submit: started %u\n",
696		− desc->txd.cookie);
697		− atc_dostart(atchan, desc);
698		− list_add_tail(&desc->desc_node, &atchan->active_list);
699		− } else {
700		− dev_vdbg(chan2dev(tx->chan), "tx_submit: queued %u\n",
701		− desc->txd.cookie);
702		− list_add_tail(&desc->desc_node, &atchan->queue);
703		− }
704		−
	665	+ list_add_tail(&desc->desc_node, &atchan->queue);
705	666	spin_unlock_irqrestore(&atchan->lock, flags);
706	667
	668	+ dev_vdbg(chan2dev(tx->chan), "tx_submit: queued %u\n",
	669	+ desc->txd.cookie);
707	670	return cookie;
708	671	}
709	672
@@ -1445,11 +1408,8 @@ static int atc_terminate_all(struct dma_chan *chan) · 735 unmodified lines
1445	1408	struct at_dma_chan *atchan = to_at_dma_chan(chan);
1446	1409	struct at_dma *atdma = to_at_dma(chan->device);
1447	1410	int chan_id = atchan->chan_common.chan_id;
1448		− struct at_desc desc, _desc;
1449	1411	unsigned long flags;
1450	1412
1451		− LIST_HEAD(list);
1452		−
1453	1413	dev_vdbg(chan2dev(chan), "%s\n", __func__);
1454	1414
1455	1415	/*
@@ -1468,19 +1428,15 @@ static int atc_terminate_all(struct dma_chan *chan) · 12 unmodified lines
1468	1428	cpu_relax();
1469	1429
1470	1430	/* active_list entries will end up before queued entries */
1471		− list_splice_init(&atchan->queue, &list);
1472		− list_splice_init(&atchan->active_list, &list);
1473		−
1474		− spin_unlock_irqrestore(&atchan->lock, flags);
1475		−
1476		− /* Flush all pending and queued descriptors */
1477		− list_for_each_entry_safe(desc, _desc, &list, desc_node)
1478		− atc_chain_complete(atchan, desc);
	1431	+ list_splice_tail_init(&atchan->queue, &atchan->free_list);
	1432	+ list_splice_tail_init(&atchan->active_list, &atchan->free_list);
1479	1433
1480	1434	clear_bit(ATC_IS_PAUSED, &atchan->status);
1481	1435	/* if channel dedicated to cyclic operations, free it */
1482	1436	clear_bit(ATC_IS_CYCLIC, &atchan->status);
1483	1437
	1438	+ spin_unlock_irqrestore(&atchan->lock, flags);
	1439	+
1484	1440	return 0;
1485	1441	}
1486	1442
@@ -1535,20 +1491,26 @@ atc_tx_status(struct dma_chan *chan, · 48 unmodified lines
1535	1491	}
1536	1492
1537	1493	/**
1538		− * atc_issue_pending - try to finish work
	1494	+ * atc_issue_pending - takes the first transaction descriptor in the pending
	1495	+ * queue and starts the transfer.
1539	1496	* @chan: target DMA channel
1540	1497	*/
1541	1498	static void atc_issue_pending(struct dma_chan *chan)
1542	1499	{
1543		− struct at_dma_chan *atchan = to_at_dma_chan(chan);
	1500	+ struct at_dma_chan *atchan = to_at_dma_chan(chan);
	1501	+ struct at_desc *desc;
	1502	+ unsigned long flags;
1544	1503
1545	1504	dev_vdbg(chan2dev(chan), "issue_pending\n");
1546	1505
1547		− /* Not needed for cyclic transfers */
1548		− if (atc_chan_is_cyclic(atchan))
1549		− return;
	1506	+ spin_lock_irqsave(&atchan->lock, flags);
	1507	+ if (atc_chan_is_enabled(atchan) \|\| list_empty(&atchan->queue))
	1508	+ return spin_unlock_irqrestore(&atchan->lock, flags);
1550	1509
1551		− atc_advance_work(atchan);
	1510	+ desc = atc_first_queued(atchan);
	1511	+ list_move_tail(&desc->desc_node, &atchan->active_list);
	1512	+ atc_dostart(atchan, desc);
	1513	+ spin_unlock_irqrestore(&atchan->lock, flags);
1552	1514	}
1553	1515
1554	1516	/**
@@ -1966,7 +1928,11 @@ static int __init at_dma_probe(struct platform_device *pdev) · 411 unmodified lines
1966	1928	dma_has_cap(DMA_SLAVE, atdma->dma_common.cap_mask) ? "slave " : "",
1967	1929	plat_dat->nr_channels);
1968	1930
1969		− dma_async_device_register(&atdma->dma_common);
	1931	+ err = dma_async_device_register(&atdma->dma_common);
	1932	+ if (err) {
	1933	+ dev_err(&pdev->dev, "Unable to register: %d.\n", err);
	1934	+ goto err_dma_async_device_register;
	1935	+ }
1970	1936
1971	1937	/*
1972	1938	* Do not return an error if the dmac node is not present in order to
@@ -1986,6 +1952,7 @@ static int __init at_dma_probe(struct platform_device *pdev) · 13 unmodified lines
1986	1952
1987	1953	err_of_dma_controller_register:
1988	1954	dma_async_device_unregister(&atdma->dma_common);
	1955	+err_dma_async_device_register:
1989	1956	dma_pool_destroy(atdma->memset_pool);
1990	1957	err_memset_pool_create:
1991	1958	dma_pool_destroy(atdma->dma_desc_pool);

drivers/dma/at_hdmac_regs.h+5−5

@@ -186,13 +186,13 @@ · 185 unmodified lines
186	186	/* LLI == Linked List Item; aka DMA buffer descriptor */
187	187	struct at_lli {
188	188	/* values that are not changed by hardware */
189		− dma_addr_t saddr;
190		− dma_addr_t daddr;
	189	+ u32 saddr;
	190	+ u32 daddr;
191	191	/* value that may get written back: */
192		− u32 ctrla;
	192	+ u32 ctrla;
193	193	/* more values that are not changed by hardware */
194		− u32 ctrlb;
195		− dma_addr_t dscr; /* chain to next lli */
	194	+ u32 ctrlb;
	195	+ u32 dscr; /* chain to next lli */
196	196	};
197	197
198	198	/**

drivers/dma/idxd/cdev.c+18−0

@@ -312,6 +312,24 @@ static int idxd_user_drv_probe(struct idxd_dev *idxd_dev) · 311 unmodified lines
312	312	if (idxd->state != IDXD_DEV_ENABLED)
313	313	return -ENXIO;
314	314
	315	+ /*
	316	+ * User type WQ is enabled only when SVA is enabled for two reasons:
	317	+ * - If no IOMMU or IOMMU Passthrough without SVA, userspace
	318	+ * can directly access physical address through the WQ.
	319	+ * - The IDXD cdev driver does not provide any ways to pin
	320	+ * user pages and translate the address from user VA to IOVA or
	321	+ * PA without IOMMU SVA. Therefore the application has no way
	322	+ * to instruct the device to perform DMA function. This makes
	323	+ * the cdev not usable for normal application usage.
	324	+ */
	325	+ if (!device_user_pasid_enabled(idxd)) {
	326	+ idxd->cmd_status = IDXD_SCMD_WQ_USER_NO_IOMMU;
	327	+ dev_dbg(&idxd->pdev->dev,
	328	+ "User type WQ cannot be enabled without SVA.\n");
	329	+
	330	+ return -EOPNOTSUPP;
	331	+ }
	332	+
315	333	mutex_lock(&wq->wq_lock);
316	334	wq->type = IDXD_WQT_USER;
317	335	rc = drv_enable_wq(wq);

drivers/dma/idxd/device.c+17−9

@@ -390,7 +390,7 @@ static void idxd_wq_disable_cleanup(struct idxd_wq *wq) · 389 unmodified lines
390	390	clear_bit(WQ_FLAG_ATS_DISABLE, &wq->flags);
391	391	memset(wq->name, 0, WQ_NAME_SIZE);
392	392	wq->max_xfer_bytes = WQ_DEFAULT_MAX_XFER;
393		− wq->max_batch_size = WQ_DEFAULT_MAX_BATCH;
	393	+ idxd_wq_set_max_batch_size(idxd->data->type, wq, WQ_DEFAULT_MAX_BATCH);
394	394	if (wq->opcap_bmap)
395	395	bitmap_copy(wq->opcap_bmap, idxd->opcap_bmap, IDXD_MAX_OPCAP_BITS);
396	396	}
@@ -730,13 +730,21 @@ static void idxd_device_wqs_clear_state(struct idxd_device *idxd) · 333 unmodified lines
730	730
731	731	void idxd_device_clear_state(struct idxd_device *idxd)
732	732	{
733		− if (!test_bit(IDXD_FLAG_CONFIGURABLE, &idxd->flags))
734		− return;
	733	+ /* IDXD is always disabled. Other states are cleared only when IDXD is configurable. */
	734	+ if (test_bit(IDXD_FLAG_CONFIGURABLE, &idxd->flags)) {
	735	+ /*
	736	+ * Clearing wq state is protected by wq lock.
	737	+ * So no need to be protected by device lock.
	738	+ */
	739	+ idxd_device_wqs_clear_state(idxd);
	740	+
	741	+ spin_lock(&idxd->dev_lock);
	742	+ idxd_groups_clear_state(idxd);
	743	+ idxd_engines_clear_state(idxd);
	744	+ } else {
	745	+ spin_lock(&idxd->dev_lock);
	746	+ }
735	747
736		− idxd_device_wqs_clear_state(idxd);
737		− spin_lock(&idxd->dev_lock);
738		− idxd_groups_clear_state(idxd);
739		− idxd_engines_clear_state(idxd);
740	748	idxd->state = IDXD_DEV_DISABLED;
741	749	spin_unlock(&idxd->dev_lock);
742	750	}
@@ -869,7 +877,7 @@ static int idxd_wq_config_write(struct idxd_wq *wq) · 126 unmodified lines
869	877
870	878	/* bytes 12-15 */
871	879	wq->wqcfg->max_xfer_shift = ilog2(wq->max_xfer_bytes);
872		− wq->wqcfg->max_batch_shift = ilog2(wq->max_batch_size);
	880	+ idxd_wqcfg_set_max_batch_shift(idxd->data->type, wq->wqcfg, ilog2(wq->max_batch_size));
873	881
874	882	/* bytes 32-63 */
875	883	if (idxd->hw.wq_cap.op_config && wq->opcap_bmap) {
@@ -1051,7 +1059,7 @@ static int idxd_wq_load_config(struct idxd_wq *wq) · 175 unmodified lines
1051	1059	wq->priority = wq->wqcfg->priority;
1052	1060
1053	1061	wq->max_xfer_bytes = 1ULL << wq->wqcfg->max_xfer_shift;
1054		− wq->max_batch_size = 1ULL << wq->wqcfg->max_batch_shift;
	1062	+ idxd_wq_set_max_batch_size(idxd->data->type, wq, 1U << wq->wqcfg->max_batch_shift);
1055	1063
1056	1064	for (i = 0; i < WQCFG_STRIDES(idxd); i++) {
1057	1065	wqcfg_offset = WQCFG_OFFSET(idxd, wq->id, i);

drivers/dma/idxd/idxd.h+32−0

@@ -548,6 +548,38 @@ static inline int idxd_wq_refcount(struct idxd_wq *wq) · 547 unmodified lines
548	548	return wq->client_count;
549	549	};
550	550
	551	+/*
	552	+ * Intel IAA does not support batch processing.
	553	+ * The max batch size of device, max batch size of wq and
	554	+ * max batch shift of wqcfg should be always 0 on IAA.
	555	+ */
	556	+static inline void idxd_set_max_batch_size(int idxd_type, struct idxd_device *idxd,
	557	+ u32 max_batch_size)
	558	+{
	559	+ if (idxd_type == IDXD_TYPE_IAX)
	560	+ idxd->max_batch_size = 0;
	561	+ else
	562	+ idxd->max_batch_size = max_batch_size;
	563	+}
	564	+
	565	+static inline void idxd_wq_set_max_batch_size(int idxd_type, struct idxd_wq *wq,
	566	+ u32 max_batch_size)
	567	+{
	568	+ if (idxd_type == IDXD_TYPE_IAX)
	569	+ wq->max_batch_size = 0;
	570	+ else
	571	+ wq->max_batch_size = max_batch_size;
	572	+}
	573	+
	574	+static inline void idxd_wqcfg_set_max_batch_shift(int idxd_type, union wqcfg *wqcfg,
	575	+ u32 max_batch_shift)
	576	+{
	577	+ if (idxd_type == IDXD_TYPE_IAX)
	578	+ wqcfg->max_batch_shift = 0;
	579	+ else
	580	+ wqcfg->max_batch_shift = max_batch_shift;
	581	+}
	582	+
551	583	int __must_check __idxd_driver_register(struct idxd_device_driver *idxd_drv,
552	584	struct module module, const char mod_name);
553	585	#define idxd_driver_register(driver) \

drivers/dma/idxd/init.c+2−2

@@ -183,7 +183,7 @@ static int idxd_setup_wqs(struct idxd_device *idxd) · 182 unmodified lines
183	183	init_completion(&wq->wq_dead);
184	184	init_completion(&wq->wq_resurrect);
185	185	wq->max_xfer_bytes = WQ_DEFAULT_MAX_XFER;
186		− wq->max_batch_size = WQ_DEFAULT_MAX_BATCH;
	186	+ idxd_wq_set_max_batch_size(idxd->data->type, wq, WQ_DEFAULT_MAX_BATCH);
187	187	wq->enqcmds_retries = IDXD_ENQCMDS_RETRIES;
188	188	wq->wqcfg = kzalloc_node(idxd->wqcfg_size, GFP_KERNEL, dev_to_node(dev));
189	189	if (!wq->wqcfg) {
@@ -418,7 +418,7 @@ static void idxd_read_caps(struct idxd_device *idxd) · 228 unmodified lines
418	418
419	419	idxd->max_xfer_bytes = 1ULL << idxd->hw.gen_cap.max_xfer_shift;
420	420	dev_dbg(dev, "max xfer size: %llu bytes\n", idxd->max_xfer_bytes);
421		− idxd->max_batch_size = 1U << idxd->hw.gen_cap.max_batch_shift;
	421	+ idxd_set_max_batch_size(idxd->data->type, idxd, 1U << idxd->hw.gen_cap.max_batch_shift);
422	422	dev_dbg(dev, "max batch size: %u\n", idxd->max_batch_size);
423	423	if (idxd->hw.gen_cap.config_en)
424	424	set_bit(IDXD_FLAG_CONFIGURABLE, &idxd->flags);

drivers/dma/idxd/sysfs.c+1−1

@@ -1046,7 +1046,7 @@ static ssize_t wq_max_batch_size_store(struct device *dev, struct device_attribu · 1045 unmodified lines
1046	1046	if (batch_size > idxd->max_batch_size)
1047	1047	return -EINVAL;
1048	1048
1049		− wq->max_batch_size = (u32)batch_size;
	1049	+ idxd_wq_set_max_batch_size(idxd->data->type, wq, (u32)batch_size);
1050	1050
1051	1051	return count;
1052	1052	}

drivers/dma/mv_xor_v2.c+1−0

@@ -893,6 +893,7 @@ static int mv_xor_v2_remove(struct platform_device *pdev) · 892 unmodified lines
893	893	tasklet_kill(&xor_dev->irq_tasklet);
894	894
895	895	clk_disable_unprepare(xor_dev->clk);
	896	+ clk_disable_unprepare(xor_dev->reg_clk);
896	897
897	898	return 0;
898	899	}

drivers/dma/pxa_dma.c+2−2

@@ -1247,14 +1247,14 @@ static int pxad_init_phys(struct platform_device *op, · 1246 unmodified lines
1247	1247	return -ENOMEM;
1248	1248
1249	1249	for (i = 0; i < nb_phy_chans; i++)
1250		− if (platform_get_irq(op, i) > 0)
	1250	+ if (platform_get_irq_optional(op, i) > 0)
1251	1251	nr_irq++;
1252	1252
1253	1253	for (i = 0; i < nb_phy_chans; i++) {
1254	1254	phy = &pdev->phys[i];
1255	1255	phy->base = pdev->base;
1256	1256	phy->idx = i;
1257		− irq = platform_get_irq(op, i);
	1257	+ irq = platform_get_irq_optional(op, i);
1258	1258	if ((nr_irq > 1) && (irq > 0))
1259	1259	ret = devm_request_irq(&op->dev, irq,
1260	1260	pxad_chan_handler,

drivers/dma/stm32-dma.c+6−8

@@ -675,6 +675,8 @@ static void stm32_dma_handle_chan_paused(struct stm32_dma_chan *chan) · 674 unmodified lines
675	675
676	676	chan->chan_reg.dma_sndtr = stm32_dma_read(dmadev, STM32_DMA_SNDTR(chan->id));
677	677
	678	+ chan->status = DMA_PAUSED;
	679	+
678	680	dev_dbg(chan2dev(chan), "vchan %pK: paused\n", &chan->vchan);
679	681	}
680	682
@@ -789,9 +791,7 @@ static irqreturn_t stm32_dma_chan_irq(int irq, void *devid) · 108 unmodified lines
789	791	if (status & STM32_DMA_TCI) {
790	792	stm32_dma_irq_clear(chan, STM32_DMA_TCI);
791	793	if (scr & STM32_DMA_SCR_TCIE) {
792		− if (chan->status == DMA_PAUSED && !(scr & STM32_DMA_SCR_EN))
793		− stm32_dma_handle_chan_paused(chan);
794		− else
	794	+ if (chan->status != DMA_PAUSED)
795	795	stm32_dma_handle_chan_done(chan, scr);
796	796	}
797	797	status &= ~STM32_DMA_TCI;
@@ -838,13 +838,11 @@ static int stm32_dma_pause(struct dma_chan *c) · 40 unmodified lines
838	838	return -EPERM;
839	839
840	840	spin_lock_irqsave(&chan->vchan.lock, flags);
	841	+
841	842	ret = stm32_dma_disable_chan(chan);
842		− /*
843		− * A transfer complete flag is set to indicate the end of transfer due to the stream
844		− * interruption, so wait for interrupt
845		− */
846	843	if (!ret)
847		− chan->status = DMA_PAUSED;
	844	+ stm32_dma_handle_chan_paused(chan);
	845	+
848	846	spin_unlock_irqrestore(&chan->vchan.lock, flags);
849	847
850	848	return ret;

drivers/dma/stm32-mdma.c+1−0

@@ -1539,6 +1539,7 @@ static struct dma_chan stm32_mdma_of_xlate(struct of_phandle_args dma_spec, · 1538 unmodified lines
1539	1539	return NULL;
1540	1540	}
1541	1541
	1542	+ memset(&config, 0, sizeof(config));
1542	1543	config.request = dma_spec->args[0];
1543	1544	config.priority_level = dma_spec->args[1];
1544	1545	config.transfer_config = dma_spec->args[2];

drivers/dma/ti/k3-udma-glue.c+3−0

@@ -299,6 +299,7 @@ struct k3_udma_glue_tx_channel k3_udma_glue_request_tx_chn(struct device dev, · 298 unmodified lines
299	299	ret = device_register(&tx_chn->common.chan_dev);
300	300	if (ret) {
301	301	dev_err(dev, "Channel Device registration failed %d\n", ret);
	302	+ put_device(&tx_chn->common.chan_dev);
302	303	tx_chn->common.chan_dev.parent = NULL;
303	304	goto err;
304	305	}
@@ -917,6 +918,7 @@ k3_udma_glue_request_rx_chn_priv(struct device dev, const char name, · 612 unmodified lines
917	918	ret = device_register(&rx_chn->common.chan_dev);
918	919	if (ret) {
919	920	dev_err(dev, "Channel Device registration failed %d\n", ret);
	921	+ put_device(&rx_chn->common.chan_dev);
920	922	rx_chn->common.chan_dev.parent = NULL;
921	923	goto err;
922	924	}
@@ -1048,6 +1050,7 @@ k3_udma_glue_request_remote_rx_chn(struct device dev, const char name, · 125 unmodified lines
1048	1050	ret = device_register(&rx_chn->common.chan_dev);
1049	1051	if (ret) {
1050	1052	dev_err(dev, "Channel Device registration failed %d\n", ret);
	1053	+ put_device(&rx_chn->common.chan_dev);
1051	1054	rx_chn->common.chan_dev.parent = NULL;
1052	1055	goto err;
1053	1056	}

drivers/firmware/efi/libstub/Makefile+1−1

@@ -82,7 +82,7 @@ $(obj)/lib-%.o: $(srctree)/lib/%.c FORCE · 81 unmodified lines
82	82	lib-$(CONFIG_EFI_GENERIC_STUB) += efi-stub.o string.o intrinsics.o systable.o
83	83
84	84	lib-$(CONFIG_ARM) += arm32-stub.o
85		−lib-$(CONFIG_ARM64) += arm64-stub.o
	85	+lib-$(CONFIG_ARM64) += arm64-stub.o smbios.o
86	86	lib-$(CONFIG_X86) += x86-stub.o
87	87	lib-$(CONFIG_RISCV) += riscv-stub.o
88	88	lib-$(CONFIG_LOONGARCH) += loongarch-stub.o

drivers/firmware/efi/libstub/arm64-stub.c+16−1

@@ -15,6 +15,21 @@ · 14 unmodified lines
15	15
16	16	#include "efistub.h"
17	17
	18	+static bool system_needs_vamap(void)
	19	+{
	20	+ const u8 *type1_family = efi_get_smbios_string(1, family);
	21	+
	22	+ /*
	23	+ * Ampere Altra machines crash in SetTime() if SetVirtualAddressMap()
	24	+ * has not been called prior.
	25	+ */
	26	+ if (!type1_family \|\| strcmp(type1_family, "Altra"))
	27	+ return false;
	28	+
	29	+ efi_warn("Working around broken SetVirtualAddressMap()\n");
	30	+ return true;
	31	+}
	32	+
18	33	efi_status_t check_platform_features(void)
19	34	{
20	35	u64 tg;
@@ -24,7 +39,7 @@ efi_status_t check_platform_features(void) · 3 unmodified lines
24	39	* UEFI runtime regions 1:1 and so calling SetVirtualAddressMap() is
25	40	* unnecessary.
26	41	*/
27		− if (VA_BITS_MIN >= 48)
	42	+ if (VA_BITS_MIN >= 48 && !system_needs_vamap())
28	43	efi_novamap = true;
29	44
30	45	/* UEFI mandates support for 4 KB granularity, no need to check */

drivers/firmware/efi/libstub/efistub.h+28−0

@@ -975,4 +975,32 @@ efi_enable_reset_attack_mitigation(void) { } · 974 unmodified lines
975	975
976	976	void efi_retrieve_tpm2_eventlog(void);
977	977
	978	+struct efi_smbios_record {
	979	+ u8 type;
	980	+ u8 length;
	981	+ u16 handle;
	982	+};
	983	+
	984	+struct efi_smbios_type1_record {
	985	+ struct efi_smbios_record header;
	986	+
	987	+ u8 manufacturer;
	988	+ u8 product_name;
	989	+ u8 version;
	990	+ u8 serial_number;
	991	+ efi_guid_t uuid;
	992	+ u8 wakeup_type;
	993	+ u8 sku_number;
	994	+ u8 family;
	995	+};
	996	+
	997	+#define efi_get_smbios_string(__type, __name) ({ \
	998	+ int size = sizeof(struct efi_smbios_type ## __type ## _record); \
	999	+ int off = offsetof(struct efi_smbios_type ## __type ## _record, \
	1000	+ __name); \
	1001	+ __efi_get_smbios_string(__type, off, size); \
	1002	+})
	1003	+
	1004	+const u8 *__efi_get_smbios_string(u8 type, int offset, int recsize);
	1005	+
978	1006	#endif

drivers/firmware/efi/libstub/smbios.c+48−0

@@ -0,0 +1,48 @@
	1	+// SPDX-License-Identifier: GPL-2.0-only
	2	+// Copyright 2022 Google LLC
	3	+// Author: Ard Biesheuvel <ardb@google.com>
	4	+
	5	+#include <linux/efi.h>
	6	+
	7	+#include "efistub.h"
	8	+
	9	+typedef struct efi_smbios_protocol efi_smbios_protocol_t;
	10	+
	11	+struct efi_smbios_protocol {
	12	+ efi_status_t (__efiapi add)(efi_smbios_protocol_t , efi_handle_t,
	13	+ u16 , struct efi_smbios_record );
	14	+ efi_status_t (__efiapi update_string)(efi_smbios_protocol_t , u16 *,
	15	+ unsigned long , u8 );
	16	+ efi_status_t (__efiapi remove)(efi_smbios_protocol_t , u16);
	17	+ efi_status_t (__efiapi get_next)(efi_smbios_protocol_t , u16 , u8 ,
	18	+ struct efi_smbios_record **,
	19	+ efi_handle_t *);
	20	+
	21	+ u8 major_version;
	22	+ u8 minor_version;
	23	+};
	24	+
	25	+const u8 *__efi_get_smbios_string(u8 type, int offset, int recsize)
	26	+{
	27	+ struct efi_smbios_record *record;
	28	+ efi_smbios_protocol_t *smbios;
	29	+ efi_status_t status;
	30	+ u16 handle = 0xfffe;
	31	+ const u8 *strtable;
	32	+
	33	+ status = efi_bs_call(locate_protocol, &EFI_SMBIOS_PROTOCOL_GUID, NULL,
	34	+ (void **)&smbios) ?:
	35	+ efi_call_proto(smbios, get_next, &handle, &type, &record, NULL);
	36	+ if (status != EFI_SUCCESS)
	37	+ return NULL;
	38	+
	39	+ strtable = (u8 *)record + recsize;
	40	+ for (int i = 1; i < ((u8 *)record)[offset]; i++) {
	41	+ int len = strlen(strtable);
	42	+
	43	+ if (!len)
	44	+ return NULL;
	45	+ strtable += len + 1;
	46	+ }
	47	+ return strtable;
	48	+}

drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c+1−0

@@ -992,6 +992,7 @@ out_free_user_pages: · 991 unmodified lines
992	992	kvfree(e->user_pages);
993	993	e->user_pages = NULL;
994	994	}
	995	+ mutex_unlock(&p->bo_list->bo_list_mutex);
995	996	return r;
996	997	}
997	998

drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c+0−26

@@ -143,32 +143,6 @@ int amdgpu_vm_set_pasid(struct amdgpu_device adev, struct amdgpu_vm vm, · 142 unmodified lines
143	143	return 0;
144	144	}
145	145
146		−/*
147		− * vm eviction_lock can be taken in MMU notifiers. Make sure no reclaim-FS
148		− * happens while holding this lock anywhere to prevent deadlocks when
149		− * an MMU notifier runs in reclaim-FS context.
150		− */
151		−static inline void amdgpu_vm_eviction_lock(struct amdgpu_vm *vm)
152		−{
153		− mutex_lock(&vm->eviction_lock);
154		− vm->saved_flags = memalloc_noreclaim_save();
155		−}
156		−
157		−static inline int amdgpu_vm_eviction_trylock(struct amdgpu_vm *vm)
158		−{
159		− if (mutex_trylock(&vm->eviction_lock)) {
160		− vm->saved_flags = memalloc_noreclaim_save();
161		− return 1;
162		− }
163		− return 0;
164		−}
165		−
166		−static inline void amdgpu_vm_eviction_unlock(struct amdgpu_vm *vm)
167		−{
168		− memalloc_noreclaim_restore(vm->saved_flags);
169		− mutex_unlock(&vm->eviction_lock);
170		−}
171		−
172	146	/**
173	147	* amdgpu_vm_bo_evicted - vm_bo is evicted
174	148	*

drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h+41−0

@@ -492,7 +492,48 @@ void amdgpu_debugfs_vm_bo_info(struct amdgpu_vm vm, struct seq_file m); · 491 unmodified lines
492	492	*/
493	493	static inline uint64_t amdgpu_vm_tlb_seq(struct amdgpu_vm *vm)
494	494	{
	495	+ unsigned long flags;
	496	+ spinlock_t *lock;
	497	+
	498	+ /*
	499	+ * Workaround to stop racing between the fence signaling and handling
	500	+ * the cb. The lock is static after initially setting it up, just make
	501	+ * sure that the dma_fence structure isn't freed up.
	502	+ */
	503	+ rcu_read_lock();
	504	+ lock = vm->last_tlb_flush->lock;
	505	+ rcu_read_unlock();
	506	+
	507	+ spin_lock_irqsave(lock, flags);
	508	+ spin_unlock_irqrestore(lock, flags);
	509	+
495	510	return atomic64_read(&vm->tlb_seq);
496	511	}
497	512
	513	+/*
	514	+ * vm eviction_lock can be taken in MMU notifiers. Make sure no reclaim-FS
	515	+ * happens while holding this lock anywhere to prevent deadlocks when
	516	+ * an MMU notifier runs in reclaim-FS context.
	517	+ */
	518	+static inline void amdgpu_vm_eviction_lock(struct amdgpu_vm *vm)
	519	+{
	520	+ mutex_lock(&vm->eviction_lock);
	521	+ vm->saved_flags = memalloc_noreclaim_save();
	522	+}
	523	+
	524	+static inline bool amdgpu_vm_eviction_trylock(struct amdgpu_vm *vm)
	525	+{
	526	+ if (mutex_trylock(&vm->eviction_lock)) {
	527	+ vm->saved_flags = memalloc_noreclaim_save();
	528	+ return true;
	529	+ }
	530	+ return false;
	531	+}
	532	+
	533	+static inline void amdgpu_vm_eviction_unlock(struct amdgpu_vm *vm)
	534	+{
	535	+ memalloc_noreclaim_restore(vm->saved_flags);
	536	+ mutex_unlock(&vm->eviction_lock);
	537	+}
	538	+
498	539	#endif

drivers/gpu/drm/amd/amdgpu/amdgpu_vm_pt.c+2−0

@@ -597,7 +597,9 @@ static int amdgpu_vm_pt_alloc(struct amdgpu_device *adev, · 596 unmodified lines
597	597	if (entry->bo)
598	598	return 0;
599	599
	600	+ amdgpu_vm_eviction_unlock(vm);
600	601	r = amdgpu_vm_pt_create(adev, vm, cursor->level, immediate, &pt);
	602	+ amdgpu_vm_eviction_lock(vm);
601	603	if (r)
602	604	return r;
603	605

drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c+1−1

@@ -435,7 +435,7 @@ static int amdgpu_vram_mgr_new(struct ttm_resource_manager *man, · 434 unmodified lines
435	435	if (place->flags & TTM_PL_FLAG_TOPDOWN)
436	436	vres->flags \|= DRM_BUDDY_TOPDOWN_ALLOCATION;
437	437
438		− if (fpfn \|\| lpfn != man->size)
	438	+ if (fpfn \|\| lpfn != mgr->mm.size)
439	439	/* Allocate blocks in desired range */
440	440	vres->flags \|= DRM_BUDDY_RANGE_ALLOCATION;
441	441

drivers/gpu/drm/amd/amdkfd/kfd_chardev.c+15−19

@@ -1950,7 +1950,7 @@ static int criu_checkpoint(struct file *filep, · 1949 unmodified lines
1950	1950	{
1951	1951	int ret;
1952	1952	uint32_t num_devices, num_bos, num_objects;
1953		− uint64_t priv_size, priv_offset = 0;
	1953	+ uint64_t priv_size, priv_offset = 0, bo_priv_offset;
1954	1954
1955	1955	if (!args->devices \|\| !args->bos \|\| !args->priv_data)
1956	1956	return -EINVAL;
@@ -1994,38 +1994,34 @@ static int criu_checkpoint(struct file *filep, · 37 unmodified lines
1994	1994	if (ret)
1995	1995	goto exit_unlock;
1996	1996
1997		− ret = criu_checkpoint_bos(p, num_bos, (uint8_t __user *)args->bos,
1998		− (uint8_t __user *)args->priv_data, &priv_offset);
1999		− if (ret)
2000		− goto exit_unlock;
	1997	+ /* Leave room for BOs in the private data. They need to be restored
	1998	+ * before events, but we checkpoint them last to simplify the error
	1999	+ * handling.
	2000	+ */
	2001	+ bo_priv_offset = priv_offset;
	2002	+ priv_offset += num_bos * sizeof(struct kfd_criu_bo_priv_data);
2001	2003
2002	2004	if (num_objects) {
2003	2005	ret = kfd_criu_checkpoint_queues(p, (uint8_t __user *)args->priv_data,
2004	2006	&priv_offset);
2005	2007	if (ret)
2006		− goto close_bo_fds;
	2008	+ goto exit_unlock;
2007	2009
2008	2010	ret = kfd_criu_checkpoint_events(p, (uint8_t __user *)args->priv_data,
2009	2011	&priv_offset);
2010	2012	if (ret)
2011		− goto close_bo_fds;
	2013	+ goto exit_unlock;
2012	2014
2013	2015	ret = kfd_criu_checkpoint_svm(p, (uint8_t __user *)args->priv_data, &priv_offset);
2014	2016	if (ret)
2015		− goto close_bo_fds;
	2017	+ goto exit_unlock;
2016	2018	}
2017	2019
2018		−close_bo_fds:
2019		− if (ret) {
2020		− /* If IOCTL returns err, user assumes all FDs opened in criu_dump_bos are closed */
2021		− uint32_t i;
2022		− struct kfd_criu_bo_bucket bo_buckets = (struct kfd_criu_bo_bucket ) args->bos;
2023		−
2024		− for (i = 0; i < num_bos; i++) {
2025		− if (bo_buckets[i].alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_VRAM)
2026		− close_fd(bo_buckets[i].dmabuf_fd);
2027		− }
2028		− }
	2020	+ /* This must be the last thing in this function that can fail.
	2021	+ * Otherwise we leak dmabuf file descriptors.
	2022	+ */
	2023	+ ret = criu_checkpoint_bos(p, num_bos, (uint8_t __user *)args->bos,
	2024	+ (uint8_t __user *)args->priv_data, &bo_priv_offset);
2029	2025
2030	2026	exit_unlock:
2031	2027	mutex_unlock(&p->mutex);

drivers/gpu/drm/amd/amdkfd/kfd_events.c+1−2

@@ -506,6 +506,7 @@ int kfd_criu_restore_event(struct file *devkfd, · 505 unmodified lines
506	506	ret = create_other_event(p, ev, &ev_priv->event_id);
507	507	break;
508	508	}
	509	+ mutex_unlock(&p->event_mutex);
509	510
510	511	exit:
511	512	if (ret)
@@ -513,8 +514,6 @@ exit: · 1 unmodified line
513	514
514	515	kfree(ev_priv);
515	516
516		− mutex_unlock(&p->event_mutex);
517		−
518	517	return ret;
519	518	}
520	519

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c+4−3

@@ -7622,9 +7622,10 @@ static void amdgpu_dm_commit_planes(struct drm_atomic_state *state, · 7621 unmodified lines
7622	7622	bundle->surface_updates[planes_count].plane_info =
7623	7623	&bundle->plane_infos[planes_count];
7624	7624
7625		− fill_dc_dirty_rects(plane, old_plane_state, new_plane_state,
7626		− new_crtc_state,
7627		− &bundle->flip_addrs[planes_count]);
	7625	+ if (acrtc_state->stream->link->psr_settings.psr_feature_enabled)
	7626	+ fill_dc_dirty_rects(plane, old_plane_state,
	7627	+ new_plane_state, new_crtc_state,
	7628	+ &bundle->flip_addrs[planes_count]);
7628	7629
7629	7630	/*
7630	7631	* Only allow immediate flips for fast updates that don't

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c+16−16

@@ -363,32 +363,32 @@ static struct wm_table ddr5_wm_table = { · 362 unmodified lines
363	363	.wm_inst = WM_A,
364	364	.wm_type = WM_TYPE_PSTATE_CHG,
365	365	.pstate_latency_us = 11.72,
366		− .sr_exit_time_us = 9,
367		− .sr_enter_plus_exit_time_us = 11,
	366	+ .sr_exit_time_us = 12.5,
	367	+ .sr_enter_plus_exit_time_us = 14.5,
368	368	.valid = true,
369	369	},
370	370	{
371	371	.wm_inst = WM_B,
372	372	.wm_type = WM_TYPE_PSTATE_CHG,
373	373	.pstate_latency_us = 11.72,
374		− .sr_exit_time_us = 9,
375		− .sr_enter_plus_exit_time_us = 11,
	374	+ .sr_exit_time_us = 12.5,
	375	+ .sr_enter_plus_exit_time_us = 14.5,
376	376	.valid = true,
377	377	},
378	378	{
379	379	.wm_inst = WM_C,
380	380	.wm_type = WM_TYPE_PSTATE_CHG,
381	381	.pstate_latency_us = 11.72,
382		− .sr_exit_time_us = 9,
383		− .sr_enter_plus_exit_time_us = 11,
	382	+ .sr_exit_time_us = 12.5,
	383	+ .sr_enter_plus_exit_time_us = 14.5,
384	384	.valid = true,
385	385	},
386	386	{
387	387	.wm_inst = WM_D,
388	388	.wm_type = WM_TYPE_PSTATE_CHG,
389	389	.pstate_latency_us = 11.72,
390		− .sr_exit_time_us = 9,
391		− .sr_enter_plus_exit_time_us = 11,
	390	+ .sr_exit_time_us = 12.5,
	391	+ .sr_enter_plus_exit_time_us = 14.5,
392	392	.valid = true,
393	393	},
394	394	}
@@ -400,32 +400,32 @@ static struct wm_table lpddr5_wm_table = { · 5 unmodified lines
400	400	.wm_inst = WM_A,
401	401	.wm_type = WM_TYPE_PSTATE_CHG,
402	402	.pstate_latency_us = 11.65333,
403		− .sr_exit_time_us = 11.5,
404		− .sr_enter_plus_exit_time_us = 14.5,
	403	+ .sr_exit_time_us = 16.5,
	404	+ .sr_enter_plus_exit_time_us = 18.5,
405	405	.valid = true,
406	406	},
407	407	{
408	408	.wm_inst = WM_B,
409	409	.wm_type = WM_TYPE_PSTATE_CHG,
410	410	.pstate_latency_us = 11.65333,
411		− .sr_exit_time_us = 11.5,
412		− .sr_enter_plus_exit_time_us = 14.5,
	411	+ .sr_exit_time_us = 16.5,
	412	+ .sr_enter_plus_exit_time_us = 18.5,
413	413	.valid = true,
414	414	},
415	415	{
416	416	.wm_inst = WM_C,
417	417	.wm_type = WM_TYPE_PSTATE_CHG,
418	418	.pstate_latency_us = 11.65333,
419		− .sr_exit_time_us = 11.5,
420		− .sr_enter_plus_exit_time_us = 14.5,
	419	+ .sr_exit_time_us = 16.5,
	420	+ .sr_enter_plus_exit_time_us = 18.5,
421	421	.valid = true,
422	422	},
423	423	{
424	424	.wm_inst = WM_D,
425	425	.wm_type = WM_TYPE_PSTATE_CHG,
426	426	.pstate_latency_us = 11.65333,
427		− .sr_exit_time_us = 11.5,
428		− .sr_enter_plus_exit_time_us = 14.5,
	427	+ .sr_exit_time_us = 16.5,
	428	+ .sr_enter_plus_exit_time_us = 18.5,
429	429	.valid = true,
430	430	},
431	431	}

drivers/gpu/drm/amd/display/dc/dc.h+1−0

@@ -853,6 +853,7 @@ struct dc_debug_options { · 852 unmodified lines
853	853	bool enable_dp_dig_pixel_rate_div_policy;
854	854	enum lttpr_mode lttpr_mode_override;
855	855	unsigned int dsc_delay_factor_wa_x1000;
	856	+ unsigned int min_prefetch_in_strobe_ns;
856	857	};
857	858
858	859	struct gpu_info_soc_bounding_box_v1_0;

drivers/gpu/drm/amd/display/dc/dcn314/dcn314_dio_stream_encoder.c+18−6

@@ -49,18 +49,30 @@ · 48 unmodified lines
49	49	#define CTX \
50	50	enc1->base.ctx
51	51
	52	+static void enc314_reset_fifo(struct stream_encoder *enc, bool reset)
	53	+{
	54	+ struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
	55	+ uint32_t reset_val = reset ? 1 : 0;
	56	+ uint32_t is_symclk_on;
	57	+
	58	+ REG_UPDATE(DIG_FIFO_CTRL0, DIG_FIFO_RESET, reset_val);
	59	+ REG_GET(DIG_FE_CNTL, DIG_SYMCLK_FE_ON, &is_symclk_on);
	60	+
	61	+ if (is_symclk_on)
	62	+ REG_WAIT(DIG_FIFO_CTRL0, DIG_FIFO_RESET_DONE, reset_val, 10, 5000);
	63	+ else
	64	+ udelay(10);
	65	+}
52	66
53	67	static void enc314_enable_fifo(struct stream_encoder *enc)
54	68	{
55	69	struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
56	70
57		− /* TODO: Confirm if we need to wait for DIG_SYMCLK_FE_ON */
58		− REG_WAIT(DIG_FE_CNTL, DIG_SYMCLK_FE_ON, 1, 10, 5000);
59	71	REG_UPDATE(DIG_FIFO_CTRL0, DIG_FIFO_READ_START_LEVEL, 0x7);
60		− REG_UPDATE(DIG_FIFO_CTRL0, DIG_FIFO_RESET, 1);
61		− REG_WAIT(DIG_FIFO_CTRL0, DIG_FIFO_RESET_DONE, 1, 10, 5000);
62		− REG_UPDATE(DIG_FIFO_CTRL0, DIG_FIFO_RESET, 0);
63		− REG_WAIT(DIG_FIFO_CTRL0, DIG_FIFO_RESET_DONE, 0, 10, 5000);
	72	+
	73	+ enc314_reset_fifo(enc, true);
	74	+ enc314_reset_fifo(enc, false);
	75	+
64	76	REG_UPDATE(DIG_FIFO_CTRL0, DIG_FIFO_ENABLE, 1);
65	77	}
66	78

drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.c+1−0

@@ -724,6 +724,7 @@ static const struct dc_debug_options debug_defaults_drv = { · 723 unmodified lines
724	724	.enable_dp_dig_pixel_rate_div_policy = 1,
725	725	.allow_sw_cursor_fallback = false,
726	726	.alloc_extra_way_for_cursor = true,
	727	+ .min_prefetch_in_strobe_ns = 60000, // 60us
727	728	};
728	729
729	730	static const struct dc_debug_options debug_defaults_diags = {

drivers/gpu/drm/amd/display/dc/dcn321/dcn321_resource.c+1−0

@@ -722,6 +722,7 @@ static const struct dc_debug_options debug_defaults_drv = { · 721 unmodified lines
722	722	.enable_dp_dig_pixel_rate_div_policy = 1,
723	723	.allow_sw_cursor_fallback = false,
724	724	.alloc_extra_way_for_cursor = true,
	725	+ .min_prefetch_in_strobe_ns = 60000, // 60us
725	726	};
726	727
727	728	static const struct dc_debug_options debug_defaults_diags = {

drivers/gpu/drm/amd/display/dc/dml/dcn314/dcn314_fpu.c+2−2

@@ -146,8 +146,8 @@ struct _vcs_dpi_soc_bounding_box_st dcn3_14_soc = { · 145 unmodified lines
146	146	},
147	147	},
148	148	.num_states = 5,
149		− .sr_exit_time_us = 9.0,
150		− .sr_enter_plus_exit_time_us = 11.0,
	149	+ .sr_exit_time_us = 16.5,
	150	+ .sr_enter_plus_exit_time_us = 18.5,
151	151	.sr_exit_z8_time_us = 442.0,
152	152	.sr_enter_plus_exit_z8_time_us = 560.0,
153	153	.writeback_latency_us = 12.0,

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c+2−0

@@ -2364,6 +2364,8 @@ void dcn32_update_bw_bounding_box_fpu(struct dc dc, struct clk_bw_params bw_pa · 2363 unmodified lines
2364	2364	/* DML DSC delay factor workaround */
2365	2365	dcn3_2_ip.dsc_delay_factor_wa = dc->debug.dsc_delay_factor_wa_x1000 / 1000.0;
2366	2366
	2367	+ dcn3_2_ip.min_prefetch_in_strobe_us = dc->debug.min_prefetch_in_strobe_ns / 1000.0;
	2368	+
2367	2369	/* Override dispclk_dppclk_vco_speed_mhz from Clk Mgr */
2368	2370	dcn3_2_soc.dispclk_dppclk_vco_speed_mhz = dc->clk_mgr->dentist_vco_freq_khz / 1000.0;
2369	2371	dc->dml.soc.dispclk_dppclk_vco_speed_mhz = dc->clk_mgr->dentist_vco_freq_khz / 1000.0;

drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c+5−0

@@ -786,6 +786,8 @@ static void DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerforman · 785 unmodified lines
786	786	v->SwathHeightY[k],
787	787	v->SwathHeightC[k],
788	788	TWait,
	789	+ v->DRAMSpeedPerState[mode_lib->vba.VoltageLevel] <= MEM_STROBE_FREQ_MHZ ?
	790	+ mode_lib->vba.ip.min_prefetch_in_strobe_us : 0,
789	791	/* Output */
790	792	&v->DSTXAfterScaler[k],
791	793	&v->DSTYAfterScaler[k],
@@ -3192,6 +3194,7 @@ void dml32_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l · 2400 unmodified lines
3192	3194	mode_lib->vba.FCLKChangeLatency, mode_lib->vba.UrgLatency[i],
3193	3195	mode_lib->vba.SREnterPlusExitTime);
3194	3196
	3197	+ memset(&v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull, 0, sizeof(DmlPipe));
3195	3198	v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.myPipe.Dppclk = mode_lib->vba.RequiredDPPCLK[i][j][k];
3196	3199	v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.myPipe.Dispclk = mode_lib->vba.RequiredDISPCLK[i][j];
3197	3200	v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.myPipe.PixelClock = mode_lib->vba.PixelClock[k];
@@ -3244,6 +3247,8 @@ void dml32_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l · 46 unmodified lines
3244	3247	v->swath_width_chroma_ub_this_state[k],
3245	3248	v->SwathHeightYThisState[k],
3246	3249	v->SwathHeightCThisState[k], v->TWait,
	3250	+ v->DRAMSpeedPerState[i] <= MEM_STROBE_FREQ_MHZ ?
	3251	+ mode_lib->vba.ip.min_prefetch_in_strobe_us : 0,
3247	3252
3248	3253	/* Output */
3249	3254	&v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.DSTXAfterScaler[k],

drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.h+3−0

@@ -49,6 +49,9 @@ · 48 unmodified lines
49	49	#define BPP_INVALID 0
50	50	#define BPP_BLENDED_PIPE 0xffffffff
51	51
	52	+#define MEM_STROBE_FREQ_MHZ 1600
	53	+#define MEM_STROBE_MAX_DELIVERY_TIME_US 60.0
	54	+
52	55	struct display_mode_lib;
53	56
54	57	void dml32_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_lib);

drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c+11−3

@@ -3417,6 +3417,7 @@ bool dml32_CalculatePrefetchSchedule( · 3416 unmodified lines
3417	3417	unsigned int SwathHeightY,
3418	3418	unsigned int SwathHeightC,
3419	3419	double TWait,
	3420	+ double TPreReq,
3420	3421	/* Output */
3421	3422	double *DSTXAfterScaler,
3422	3423	double *DSTYAfterScaler,
@@ -3474,6 +3475,7 @@ bool dml32_CalculatePrefetchSchedule( · 51 unmodified lines
3474	3475	double min_Lsw;
3475	3476	double Tsw_est1 = 0;
3476	3477	double Tsw_est3 = 0;
	3478	+ double TPreMargin = 0;
3477	3479
3478	3480	if (v->GPUVMEnable == true && v->HostVMEnable == true)
3479	3481	HostVMDynamicLevelsTrips = v->HostVMMaxNonCachedPageTableLevels;
@@ -3699,6 +3701,8 @@ bool dml32_CalculatePrefetchSchedule( · 219 unmodified lines
3699	3701
3700	3702	dst_y_prefetch_equ = dml_floor(4.0 * (dst_y_prefetch_equ + 0.125), 1) / 4.0;
3701	3703	Tpre_rounded = dst_y_prefetch_equ * LineTime;
	3704	+
	3705	+ TPreMargin = Tpre_rounded - TPreReq;
3702	3706	#ifdef __DML_VBA_DEBUG__
3703	3707	dml_print("DML::%s: dst_y_prefetch_equ: %f (after round)\n", __func__, dst_y_prefetch_equ);
3704	3708	dml_print("DML::%s: LineTime: %f\n", __func__, LineTime);
@@ -3726,7 +3730,7 @@ bool dml32_CalculatePrefetchSchedule( · 21 unmodified lines
3726	3730	*VRatioPrefetchY = 0;
3727	3731	*VRatioPrefetchC = 0;
3728	3732	*RequiredPrefetchPixDataBWLuma = 0;
3729		− if (dst_y_prefetch_equ > 1) {
	3733	+ if (dst_y_prefetch_equ > 1 && TPreMargin > 0.0) {
3730	3734	double PrefetchBandwidth1;
3731	3735	double PrefetchBandwidth2;
3732	3736	double PrefetchBandwidth3;
@@ -3872,7 +3876,11 @@ bool dml32_CalculatePrefetchSchedule( · 139 unmodified lines
3872	3876	}
3873	3877
3874	3878	if (dst_y_prefetch_oto < dst_y_prefetch_equ) {
3875		− *DestinationLinesForPrefetch = dst_y_prefetch_oto;
	3879	+ if (dst_y_prefetch_oto * LineTime < TPreReq) {
	3880	+ *DestinationLinesForPrefetch = dst_y_prefetch_equ;
	3881	+ } else {
	3882	+ *DestinationLinesForPrefetch = dst_y_prefetch_oto;
	3883	+ }
3876	3884	TimeForFetchingMetaPTE = Tvm_oto;
3877	3885	TimeForFetchingRowInVBlank = Tr0_oto;
3878	3886	*PrefetchBandwidth = prefetch_bw_oto;
@@ -4397,7 +4405,7 @@ void dml32_CalculateWatermarksMALLUseAndDRAMSpeedChangeSupport( · 518 unmodified lines
4397	4405
4398	4406	if (v->NumberOfActiveSurfaces > 1) {
4399	4407	ActiveClockChangeLatencyHidingY = ActiveClockChangeLatencyHidingY
4400		− - (1 - 1 / v->NumberOfActiveSurfaces) * SwathHeightY[k] * v->HTotal[k]
	4408	+ - (1.0 - 1.0 / v->NumberOfActiveSurfaces) * SwathHeightY[k] * v->HTotal[k]
4401	4409	/ v->PixelClock[k] / v->VRatio[k];
4402	4410	}
4403	4411

drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.h+2−1

@@ -30,7 +30,7 @@ · 29 unmodified lines
30	30	#include "os_types.h"
31	31	#include "../dc_features.h"
32	32	#include "../display_mode_structs.h"
33		−#include "dml/display_mode_vba.h"
	33	+#include "../display_mode_vba.h"
34	34
35	35	unsigned int dml32_dscceComputeDelay(
36	36	unsigned int bpc,
@@ -743,6 +743,7 @@ bool dml32_CalculatePrefetchSchedule( · 706 unmodified lines
743	743	unsigned int SwathHeightY,
744	744	unsigned int SwathHeightC,
745	745	double TWait,
	746	+ double TPreReq,
746	747	/* Output */
747	748	double *DSTXAfterScaler,
748	749	double *DSTYAfterScaler,

drivers/gpu/drm/amd/display/dc/dml/dcn321/dcn321_fpu.c+2−0

@@ -544,6 +544,8 @@ void dcn321_update_bw_bounding_box_fpu(struct dc dc, struct clk_bw_params bw_p · 543 unmodified lines
544	544	/* DML DSC delay factor workaround */
545	545	dcn3_21_ip.dsc_delay_factor_wa = dc->debug.dsc_delay_factor_wa_x1000 / 1000.0;
546	546
	547	+ dcn3_21_ip.min_prefetch_in_strobe_us = dc->debug.min_prefetch_in_strobe_ns / 1000.0;
	548	+
547	549	/* Override dispclk_dppclk_vco_speed_mhz from Clk Mgr */
548	550	dcn3_21_soc.dispclk_dppclk_vco_speed_mhz = dc->clk_mgr->dentist_vco_freq_khz / 1000.0;
549	551	dc->dml.soc.dispclk_dppclk_vco_speed_mhz = dc->clk_mgr->dentist_vco_freq_khz / 1000.0;

drivers/gpu/drm/amd/display/dc/dml/display_mode_structs.h+1−0

@@ -367,6 +367,7 @@ struct _vcs_dpi_ip_params_st { · 366 unmodified lines
367	367
368	368	/* DM workarounds */
369	369	double dsc_delay_factor_wa; // TODO: Remove after implementing root cause fix
	370	+ double min_prefetch_in_strobe_us;
370	371	};
371	372
372	373	struct _vcs_dpi_display_xfc_params_st {

drivers/gpu/drm/amd/display/dc/gpio/dcn32/hw_factory_dcn32.c+14−0

@@ -107,6 +107,13 @@ static const struct ddc_registers ddc_data_regs_dcn[] = { · 106 unmodified lines
107	107	ddc_data_regs_dcn2(3),
108	108	ddc_data_regs_dcn2(4),
109	109	ddc_data_regs_dcn2(5),
	110	+ {
	111	+ // add a dummy entry for cases no such port
	112	+ {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,},
	113	+ .ddc_setup = 0,
	114	+ .phy_aux_cntl = 0,
	115	+ .dc_gpio_aux_ctrl_5 = 0
	116	+ },
110	117	{
111	118	DDC_GPIO_VGA_REG_LIST(DATA),
112	119	.ddc_setup = 0,
@@ -121,6 +128,13 @@ static const struct ddc_registers ddc_clk_regs_dcn[] = { · 8 unmodified lines
121	128	ddc_clk_regs_dcn2(3),
122	129	ddc_clk_regs_dcn2(4),
123	130	ddc_clk_regs_dcn2(5),
	131	+ {
	132	+ // add a dummy entry for cases no such port
	133	+ {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,},
	134	+ .ddc_setup = 0,
	135	+ .phy_aux_cntl = 0,
	136	+ .dc_gpio_aux_ctrl_5 = 0
	137	+ },
124	138	{
125	139	DDC_GPIO_VGA_REG_LIST(CLK),
126	140	.ddc_setup = 0,

drivers/gpu/drm/amd/display/dc/gpio/hw_ddc.c+6−3

@@ -94,11 +94,14 @@ static enum gpio_result set_config( · 93 unmodified lines
94	94	* is required for detection of AUX mode */
95	95	if (hw_gpio->base.en != GPIO_DDC_LINE_VIP_PAD) {
96	96	if (!ddc_data_pd_en \|\| !ddc_clk_pd_en) {
97		−
98		− REG_SET_2(gpio.MASK_reg, regval,
	97	+ if (hw_gpio->base.en == GPIO_DDC_LINE_DDC_VGA) {
	98	+ // bit 4 of mask has different usage in some cases
	99	+ REG_SET(gpio.MASK_reg, regval, DC_GPIO_DDC1DATA_PD_EN, 1);
	100	+ } else {
	101	+ REG_SET_2(gpio.MASK_reg, regval,
99	102	DC_GPIO_DDC1DATA_PD_EN, 1,
100	103	DC_GPIO_DDC1CLK_PD_EN, 1);
101		−
	104	+ }
102	105	if (config_data->type ==
103	106	GPIO_CONFIG_TYPE_I2C_AUX_DUAL_MODE)
104	107	msleep(3);

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_thermal.c+12−13

@@ -67,22 +67,21 @@ int vega10_fan_ctrl_get_fan_speed_info(struct pp_hwmgr *hwmgr, · 66 unmodified lines
67	67	int vega10_fan_ctrl_get_fan_speed_pwm(struct pp_hwmgr *hwmgr,
68	68	uint32_t *speed)
69	69	{
70		− uint32_t current_rpm;
71		− uint32_t percent = 0;
72		−
73		− if (hwmgr->thermal_controller.fanInfo.bNoFan)
74		− return 0;
	70	+ struct amdgpu_device *adev = hwmgr->adev;
	71	+ uint32_t duty100, duty;
	72	+ uint64_t tmp64;
75	73
76		− if (vega10_get_current_rpm(hwmgr, &current_rpm))
77		− return -1;
	74	+ duty100 = REG_GET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL1),
	75	+ CG_FDO_CTRL1, FMAX_DUTY100);
	76	+ duty = REG_GET_FIELD(RREG32_SOC15(THM, 0, mmCG_THERMAL_STATUS),
	77	+ CG_THERMAL_STATUS, FDO_PWM_DUTY);
78	78
79		− if (hwmgr->thermal_controller.
80		− advanceFanControlParameters.usMaxFanRPM != 0)
81		− percent = current_rpm * 255 /
82		− hwmgr->thermal_controller.
83		− advanceFanControlParameters.usMaxFanRPM;
	79	+ if (!duty100)
	80	+ return -EINVAL;
84	81
85		− *speed = MIN(percent, 255);
	82	+ tmp64 = (uint64_t)duty * 255;
	83	+ do_div(tmp64, duty100);
	84	+ *speed = MIN((uint32_t)tmp64, 255);
86	85
87	86	return 0;
88	87	}

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_4_ppsmc.h+7−8

@@ -54,14 +54,14 @@ · 53 unmodified lines
54	54	#define PPSMC_MSG_TestMessage 0x01 ///< To check if PMFW is alive and responding. Requirement specified by PMFW team
55	55	#define PPSMC_MSG_GetPmfwVersion 0x02 ///< Get PMFW version
56	56	#define PPSMC_MSG_GetDriverIfVersion 0x03 ///< Get PMFW_DRIVER_IF version
57		−#define PPSMC_MSG_EnableGfxOff 0x04 ///< Enable GFXOFF
58		−#define PPSMC_MSG_DisableGfxOff 0x05 ///< Disable GFXOFF
	57	+#define PPSMC_MSG_SPARE0 0x04 ///< SPARE
	58	+#define PPSMC_MSG_SPARE1 0x05 ///< SPARE
59	59	#define PPSMC_MSG_PowerDownVcn 0x06 ///< Power down VCN
60	60	#define PPSMC_MSG_PowerUpVcn 0x07 ///< Power up VCN; VCN is power gated by default
61	61	#define PPSMC_MSG_SetHardMinVcn 0x08 ///< For wireless display
62	62	#define PPSMC_MSG_SetSoftMinGfxclk 0x09 ///< Set SoftMin for GFXCLK, argument is frequency in MHz
63		−#define PPSMC_MSG_ActiveProcessNotify 0x0A ///< Needs update
64		−#define PPSMC_MSG_ForcePowerDownGfx 0x0B ///< Force power down GFX, i.e. enter GFXOFF
	63	+#define PPSMC_MSG_SPARE2 0x0A ///< SPARE
	64	+#define PPSMC_MSG_SPARE3 0x0B ///< SPARE
65	65	#define PPSMC_MSG_PrepareMp1ForUnload 0x0C ///< Prepare PMFW for GFX driver unload
66	66	#define PPSMC_MSG_SetDriverDramAddrHigh 0x0D ///< Set high 32 bits of DRAM address for Driver table transfer
67	67	#define PPSMC_MSG_SetDriverDramAddrLow 0x0E ///< Set low 32 bits of DRAM address for Driver table transfer
@@ -73,8 +73,7 @@ · 5 unmodified lines
73	73	#define PPSMC_MSG_SetSoftMinFclk 0x14 ///< Set hard min for FCLK
74	74	#define PPSMC_MSG_SetSoftMinVcn 0x15 ///< Set soft min for VCN clocks (VCLK and DCLK)
75	75
76		−
77		−#define PPSMC_MSG_EnableGfxImu 0x16 ///< Needs update
	76	+#define PPSMC_MSG_EnableGfxImu 0x16 ///< Enable GFX IMU
78	77
79	78	#define PPSMC_MSG_GetGfxclkFrequency 0x17 ///< Get GFX clock frequency
80	79	#define PPSMC_MSG_GetFclkFrequency 0x18 ///< Get FCLK frequency
@@ -102,8 +101,8 @@ · 21 unmodified lines
102	101	#define PPSMC_MSG_SetHardMinIspxclkByFreq 0x2C ///< Set HardMin by frequency for ISPXCLK
103	102	#define PPSMC_MSG_PowerDownUmsch 0x2D ///< Power down VCN.UMSCH (aka VSCH) scheduler
104	103	#define PPSMC_MSG_PowerUpUmsch 0x2E ///< Power up VCN.UMSCH (aka VSCH) scheduler
105		−#define PPSMC_Message_IspStutterOn_MmhubPgDis 0x2F ///< ISP StutterOn mmHub PgDis
106		−#define PPSMC_Message_IspStutterOff_MmhubPgEn 0x30 ///< ISP StufferOff mmHub PgEn
	104	+#define PPSMC_MSG_IspStutterOn_MmhubPgDis 0x2F ///< ISP StutterOn mmHub PgDis
	105	+#define PPSMC_MSG_IspStutterOff_MmhubPgEn 0x30 ///< ISP StufferOff mmHub PgEn
107	106
108	107	#define PPSMC_Message_Count 0x31 ///< Total number of PPSMC messages
109	108	/** @}*/

drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c+3−1

@@ -377,7 +377,9 @@ static void sienna_cichlid_check_bxco_support(struct smu_context *smu) · 376 unmodified lines
377	377	if (((adev->pdev->device == 0x73A1) &&
378	378	(adev->pdev->revision == 0x00)) \|\|
379	379	((adev->pdev->device == 0x73BF) &&
380		− (adev->pdev->revision == 0xCF)))
	380	+ (adev->pdev->revision == 0xCF)) \|\|
	381	+ ((adev->pdev->device == 0x7422) &&
	382	+ (adev->pdev->revision == 0x00)))
381	383	smu_baco->platform_support = false;
382	384
383	385	}

drivers/gpu/drm/drm_panel_orientation_quirks.c+12−0

@@ -134,6 +134,12 @@ static const struct dmi_system_id orientation_data[] = { · 133 unmodified lines
134	134	DMI_EXACT_MATCH(DMI_PRODUCT_NAME, "One S1003"),
135	135	},
136	136	.driver_data = (void *)&lcd800x1280_rightside_up,
	137	+ }, { /* Acer Switch V 10 (SW5-017) */
	138	+ .matches = {
	139	+ DMI_EXACT_MATCH(DMI_SYS_VENDOR, "Acer"),
	140	+ DMI_EXACT_MATCH(DMI_PRODUCT_NAME, "SW5-017"),
	141	+ },
	142	+ .driver_data = (void *)&lcd800x1280_rightside_up,
137	143	}, { /* Anbernic Win600 */
138	144	.matches = {
139	145	DMI_EXACT_MATCH(DMI_BOARD_VENDOR, "Anbernic"),
@@ -319,6 +325,12 @@ static const struct dmi_system_id orientation_data[] = { · 179 unmodified lines
319	325	DMI_MATCH(DMI_BIOS_VERSION, "BLADE_21"),
320	326	},
321	327	.driver_data = (void *)&lcd1200x1920_rightside_up,
	328	+ }, { /* Nanote UMPC-01 */
	329	+ .matches = {
	330	+ DMI_MATCH(DMI_SYS_VENDOR, "RWC CO.,LTD"),
	331	+ DMI_MATCH(DMI_PRODUCT_NAME, "UMPC-01"),
	332	+ },
	333	+ .driver_data = (void *)&lcd1200x1920_rightside_up,
322	334	}, { /* OneGX1 Pro */
323	335	.matches = {
324	336	DMI_EXACT_MATCH(DMI_SYS_VENDOR, "SYSTEM_MANUFACTURER"),

drivers/gpu/drm/i915/display/intel_psr.c+4−1

@@ -2201,8 +2201,11 @@ static void _psr_invalidate_handle(struct intel_dp *intel_dp) · 2200 unmodified lines
2201	2201	if (intel_dp->psr.psr2_sel_fetch_enabled) {
2202	2202	u32 val;
2203	2203
2204		− if (intel_dp->psr.psr2_sel_fetch_cff_enabled)
	2204	+ if (intel_dp->psr.psr2_sel_fetch_cff_enabled) {
	2205	+ /* Send one update otherwise lag is observed in screen */
	2206	+ intel_de_write(dev_priv, CURSURFLIVE(intel_dp->psr.pipe), 0);
2205	2207	return;
	2208	+ }
2206	2209
2207	2210	val = man_trk_ctl_enable_bit_get(dev_priv) \|
2208	2211	man_trk_ctl_partial_frame_bit_get(dev_priv) \|

drivers/gpu/drm/i915/gem/i915_gem_dmabuf.c+2−2

@@ -40,13 +40,13 @@ static struct sg_table i915_gem_map_dma_buf(struct dma_buf_attachment attachme · 39 unmodified lines
40	40	goto err;
41	41	}
42	42
43		− ret = sg_alloc_table(st, obj->mm.pages->nents, GFP_KERNEL);
	43	+ ret = sg_alloc_table(st, obj->mm.pages->orig_nents, GFP_KERNEL);
44	44	if (ret)
45	45	goto err_free;
46	46
47	47	src = obj->mm.pages->sgl;
48	48	dst = st->sgl;
49		− for (i = 0; i < obj->mm.pages->nents; i++) {
	49	+ for (i = 0; i < obj->mm.pages->orig_nents; i++) {
50	50	sg_set_page(dst, sg_page(src), src->length, 0);
51	51	dst = sg_next(dst);
52	52	src = sg_next(src);

drivers/gpu/drm/i915/gem/i915_gem_shmem.c+2−2

@@ -369,14 +369,14 @@ __i915_gem_object_release_shmem(struct drm_i915_gem_object *obj, · 368 unmodified lines
369	369
370	370	__start_cpu_write(obj);
371	371	/*
372		− * On non-LLC platforms, force the flush-on-acquire if this is ever
	372	+ * On non-LLC igfx platforms, force the flush-on-acquire if this is ever
373	373	* swapped-in. Our async flush path is not trust worthy enough yet(and
374	374	* happens in the wrong order), and with some tricks it's conceivable
375	375	* for userspace to change the cache-level to I915_CACHE_NONE after the
376	376	* pages are swapped-in, and since execbuf binds the object before doing
377	377	* the async flush, we have a race window.
378	378	*/
379		− if (!HAS_LLC(i915))
	379	+ if (!HAS_LLC(i915) && !IS_DGFX(i915))
380	380	obj->cache_dirty = true;
381	381	}
382	382

drivers/gpu/drm/i915/gem/i915_gem_userptr.c+3−2

@@ -428,9 +428,10 @@ probe_range(struct mm_struct *mm, unsigned long addr, unsigned long len) · 427 unmodified lines
428	428	{
429	429	VMA_ITERATOR(vmi, mm, addr);
430	430	struct vm_area_struct *vma;
	431	+ unsigned long end = addr + len;
431	432
432	433	mmap_read_lock(mm);
433		− for_each_vma_range(vmi, vma, addr + len) {
	434	+ for_each_vma_range(vmi, vma, end) {
434	435	/* Check for holes, note that we also update the addr below */
435	436	if (vma->vm_start > addr)
436	437	break;
@@ -442,7 +443,7 @@ probe_range(struct mm_struct *mm, unsigned long addr, unsigned long len) · 5 unmodified lines
442	443	}
443	444	mmap_read_unlock(mm);
444	445
445		− if (vma)
	446	+ if (vma \|\| addr < end)
446	447	return -EFAULT;
447	448	return 0;
448	449	}

drivers/gpu/drm/panfrost/panfrost_mmu.c+10−1

@@ -250,13 +250,22 @@ void panfrost_mmu_reset(struct panfrost_device *pfdev) · 249 unmodified lines
250	250
251	251	static size_t get_pgsize(u64 addr, size_t size, size_t *count)
252	252	{
	253	+ /*
	254	+ * io-pgtable only operates on multiple pages within a single table
	255	+ * entry, so we need to split at boundaries of the table size, i.e.
	256	+ * the next block size up. The distance from address A to the next
	257	+ * boundary of block size B is logically B - A % B, but in unsigned
	258	+ * two's complement where B is a power of two we get the equivalence
	259	+ * B - A % B == (B - A) % B == (n * B - A) % B, and choose n = 0 :)
	260	+ */
253	261	size_t blk_offset = -addr % SZ_2M;
254	262
255	263	if (blk_offset \|\| size < SZ_2M) {
256	264	*count = min_not_zero(blk_offset, size) / SZ_4K;
257	265	return SZ_4K;
258	266	}
259		− *count = size / SZ_2M;
	267	+ blk_offset = -addr % SZ_1G ?: SZ_1G;
	268	+ *count = min(blk_offset, size) / SZ_2M;
260	269	return SZ_2M;
261	270	}
262	271

drivers/gpu/drm/rcar-du/Kconfig+9−4

@@ -44,13 +44,18 @@ config DRM_RCAR_LVDS · 43 unmodified lines
44	44	select OF_FLATTREE
45	45	select OF_OVERLAY
46	46
47		−config DRM_RCAR_MIPI_DSI
48		− tristate "R-Car DU MIPI DSI Encoder Support"
49		− depends on DRM && DRM_BRIDGE && OF
50		− select DRM_MIPI_DSI
	47	+config DRM_RCAR_USE_MIPI_DSI
	48	+ bool "R-Car DU MIPI DSI Encoder Support"
	49	+ depends on DRM_BRIDGE && OF
	50	+ default DRM_RCAR_DU
51	51	help
52	52	Enable support for the R-Car Display Unit embedded MIPI DSI encoders.
53	53
	54	+config DRM_RCAR_MIPI_DSI
	55	+ def_tristate DRM_RCAR_DU
	56	+ depends on DRM_RCAR_USE_MIPI_DSI
	57	+ select DRM_MIPI_DSI
	58	+
54	59	config DRM_RCAR_VSP
55	60	bool "R-Car DU VSP Compositor Support" if ARM
56	61	default y if ARM64

drivers/gpu/drm/vc4/vc4_drv.c+6−1

@@ -476,7 +476,12 @@ static int __init vc4_drm_register(void) · 475 unmodified lines
476	476	if (ret)
477	477	return ret;
478	478
479		− return platform_driver_register(&vc4_platform_driver);
	479	+ ret = platform_driver_register(&vc4_platform_driver);
	480	+ if (ret)
	481	+ platform_unregister_drivers(component_drivers,
	482	+ ARRAY_SIZE(component_drivers));
	483	+
	484	+ return ret;
480	485	}
481	486
482	487	static void __exit vc4_drm_unregister(void)

drivers/gpu/drm/vc4/vc4_hdmi.c+36−11

@@ -349,27 +349,40 @@ static int vc4_hdmi_reset_link(struct drm_connector *connector, · 348 unmodified lines
349	349	if (!crtc_state->active)
350	350	return 0;
351	351
352		− if (!vc4_hdmi_supports_scrambling(encoder))
	352	+ mutex_lock(&vc4_hdmi->mutex);
	353	+
	354	+ if (!vc4_hdmi_supports_scrambling(encoder)) {
	355	+ mutex_unlock(&vc4_hdmi->mutex);
353	356	return 0;
	357	+ }
354	358
355	359	scrambling_needed = vc4_hdmi_mode_needs_scrambling(&vc4_hdmi->saved_adjusted_mode,
356	360	vc4_hdmi->output_bpc,
357	361	vc4_hdmi->output_format);
358		− if (!scrambling_needed)
	362	+ if (!scrambling_needed) {
	363	+ mutex_unlock(&vc4_hdmi->mutex);
359	364	return 0;
	365	+ }
360	366
361	367	if (conn_state->commit &&
362		− !try_wait_for_completion(&conn_state->commit->hw_done))
	368	+ !try_wait_for_completion(&conn_state->commit->hw_done)) {
	369	+ mutex_unlock(&vc4_hdmi->mutex);
363	370	return 0;
	371	+ }
364	372
365	373	ret = drm_scdc_readb(connector->ddc, SCDC_TMDS_CONFIG, &config);
366	374	if (ret < 0) {
367	375	drm_err(drm, "Failed to read TMDS config: %d\n", ret);
	376	+ mutex_unlock(&vc4_hdmi->mutex);
368	377	return 0;
369	378	}
370	379
371		− if (!!(config & SCDC_SCRAMBLING_ENABLE) == scrambling_needed)
	380	+ if (!!(config & SCDC_SCRAMBLING_ENABLE) == scrambling_needed) {
	381	+ mutex_unlock(&vc4_hdmi->mutex);
372	382	return 0;
	383	+ }
	384	+
	385	+ mutex_unlock(&vc4_hdmi->mutex);
373	386
374	387	/*
375	388	* HDMI 2.0 says that one should not send scrambled data
@@ -397,9 +410,8 @@ static void vc4_hdmi_handle_hotplug(struct vc4_hdmi *vc4_hdmi, · 21 unmodified lines
397	410	* .adap_enable, which leads to that funtion being called with
398	411	* our mutex held.
399	412	*
400		− * A similar situation occurs with
401		− * drm_atomic_helper_connector_hdmi_reset_link() that will call
402		− * into our KMS hooks if the scrambling was enabled.
	413	+ * A similar situation occurs with vc4_hdmi_reset_link() that
	414	+ * will call into our KMS hooks if the scrambling was enabled.
403	415	*
404	416	* Concurrency isn't an issue at the moment since we don't share
405	417	* any state with any of the other frameworks so we can ignore
@@ -3160,9 +3172,16 @@ static int vc4_hdmi_init_resources(struct drm_device *drm, · 2754 unmodified lines
3160	3172	DRM_ERROR("Failed to get HDMI state machine clock\n");
3161	3173	return PTR_ERR(vc4_hdmi->hsm_clock);
3162	3174	}
	3175	+
3163	3176	vc4_hdmi->audio_clock = vc4_hdmi->hsm_clock;
3164	3177	vc4_hdmi->cec_clock = vc4_hdmi->hsm_clock;
3165	3178
	3179	+ vc4_hdmi->hsm_rpm_clock = devm_clk_get(dev, "hdmi");
	3180	+ if (IS_ERR(vc4_hdmi->hsm_rpm_clock)) {
	3181	+ DRM_ERROR("Failed to get HDMI state machine clock\n");
	3182	+ return PTR_ERR(vc4_hdmi->hsm_rpm_clock);
	3183	+ }
	3184	+
3166	3185	return 0;
3167	3186	}
3168	3187
@@ -3245,6 +3264,12 @@ static int vc5_hdmi_init_resources(struct drm_device *drm, · 76 unmodified lines
3245	3264	return PTR_ERR(vc4_hdmi->hsm_clock);
3246	3265	}
3247	3266
	3267	+ vc4_hdmi->hsm_rpm_clock = devm_clk_get(dev, "hdmi");
	3268	+ if (IS_ERR(vc4_hdmi->hsm_rpm_clock)) {
	3269	+ DRM_ERROR("Failed to get HDMI state machine clock\n");
	3270	+ return PTR_ERR(vc4_hdmi->hsm_rpm_clock);
	3271	+ }
	3272	+
3248	3273	vc4_hdmi->pixel_bvb_clock = devm_clk_get(dev, "bvb");
3249	3274	if (IS_ERR(vc4_hdmi->pixel_bvb_clock)) {
3250	3275	DRM_ERROR("Failed to get pixel bvb clock\n");
@@ -3308,7 +3333,7 @@ static int vc4_hdmi_runtime_suspend(struct device *dev) · 57 unmodified lines
3308	3333	{
3309	3334	struct vc4_hdmi *vc4_hdmi = dev_get_drvdata(dev);
3310	3335
3311		− clk_disable_unprepare(vc4_hdmi->hsm_clock);
	3336	+ clk_disable_unprepare(vc4_hdmi->hsm_rpm_clock);
3312	3337
3313	3338	return 0;
3314	3339	}
@@ -3326,11 +3351,11 @@ static int vc4_hdmi_runtime_resume(struct device *dev) · 11 unmodified lines
3326	3351	* its frequency while the power domain is active so that it
3327	3352	* keeps its rate.
3328	3353	*/
3329		− ret = clk_set_min_rate(vc4_hdmi->hsm_clock, HSM_MIN_CLOCK_FREQ);
	3354	+ ret = clk_set_min_rate(vc4_hdmi->hsm_rpm_clock, HSM_MIN_CLOCK_FREQ);
3330	3355	if (ret)
3331	3356	return ret;
3332	3357
3333		− ret = clk_prepare_enable(vc4_hdmi->hsm_clock);
	3358	+ ret = clk_prepare_enable(vc4_hdmi->hsm_rpm_clock);
3334	3359	if (ret)
3335	3360	return ret;
3336	3361
@@ -3343,7 +3368,7 @@ static int vc4_hdmi_runtime_resume(struct device *dev) · 6 unmodified lines
3343	3368	* case, it will lead to a silent CPU stall. Let's make sure we
3344	3369	* prevent such a case.
3345	3370	*/
3346		− rate = clk_get_rate(vc4_hdmi->hsm_clock);
	3371	+ rate = clk_get_rate(vc4_hdmi->hsm_rpm_clock);
3347	3372	if (!rate) {
3348	3373	ret = -EINVAL;
3349	3374	goto err_disable_clk;

drivers/gpu/drm/vc4/vc4_hdmi.h+1−0

@@ -172,6 +172,7 @@ struct vc4_hdmi { · 171 unmodified lines
172	172	struct clk *cec_clock;
173	173	struct clk *pixel_clock;
174	174	struct clk *hsm_clock;
	175	+ struct clk *hsm_rpm_clock;
175	176	struct clk *audio_clock;
176	177	struct clk *pixel_bvb_clock;
177	178

drivers/hid/hid-asus.c+1−3

@@ -219,14 +219,13 @@ static void asus_report_tool_width(struct asus_drvdata *drvdat) · 218 unmodified lines
219	219	{
220	220	struct input_mt *mt = drvdat->input->mt;
221	221	struct input_mt_slot *oldest;
222		− int oldid, count, i;
	222	+ int oldid, i;
223	223
224	224	if (drvdat->tp->contact_size < 5)
225	225	return;
226	226
227	227	oldest = NULL;
228	228	oldid = mt->trkid;
229		− count = 0;
230	229
231	230	for (i = 0; i < mt->num_slots; ++i) {
232	231	struct input_mt_slot *ps = &mt->slots[i];
@@ -238,7 +237,6 @@ static void asus_report_tool_width(struct asus_drvdata *drvdat) · 5 unmodified lines
238	237	oldest = ps;
239	238	oldid = id;
240	239	}
241		− count++;
242	240	}
243	241
244	242	if (oldest) {

drivers/hid/hid-hyperv.c+1−1

@@ -499,7 +499,7 @@ static int mousevsc_probe(struct hv_device *device, · 498 unmodified lines
499	499
500	500	ret = hid_add_device(hid_dev);
501	501	if (ret)
502		− goto probe_err1;
	502	+ goto probe_err2;
503	503
504	504
505	505	ret = hid_parse(hid_dev);

drivers/hid/wacom_wac.c+6−5

@@ -2520,11 +2520,12 @@ static void wacom_wac_pen_report(struct hid_device *hdev, · 2519 unmodified lines
2520	2520
2521	2521	if (!delay_pen_events(wacom_wac) && wacom_wac->tool[0]) {
2522	2522	int id = wacom_wac->id[0];
2523		− if (wacom_wac->features.quirks & WACOM_QUIRK_PEN_BUTTON3 &&
2524		− wacom_wac->hid_data.barrelswitch & wacom_wac->hid_data.barrelswitch2) {
2525		− wacom_wac->hid_data.barrelswitch = 0;
2526		− wacom_wac->hid_data.barrelswitch2 = 0;
2527		− wacom_wac->hid_data.barrelswitch3 = 1;
	2523	+ if (wacom_wac->features.quirks & WACOM_QUIRK_PEN_BUTTON3) {
	2524	+ int sw_state = wacom_wac->hid_data.barrelswitch \|
	2525	+ (wacom_wac->hid_data.barrelswitch2 << 1);
	2526	+ wacom_wac->hid_data.barrelswitch = sw_state == 1;
	2527	+ wacom_wac->hid_data.barrelswitch2 = sw_state == 2;
	2528	+ wacom_wac->hid_data.barrelswitch3 = sw_state == 3;
2528	2529	}
2529	2530	input_report_key(input, BTN_STYLUS, wacom_wac->hid_data.barrelswitch);
2530	2531	input_report_key(input, BTN_STYLUS2, wacom_wac->hid_data.barrelswitch2);

drivers/hv/hv_balloon.c+1−1

@@ -905,7 +905,7 @@ static unsigned long handle_pg_range(unsigned long pg_start, · 904 unmodified lines
905	905	* We have some residual hot add range
906	906	* that needs to be hot added; hot add
907	907	* it now. Hot add a multiple of
908		− * of HA_CHUNK that fully covers the pages
	908	+ * HA_CHUNK that fully covers the pages
909	909	* we have.
910	910	*/
911	911	size = (has->end_pfn - has->ha_end_pfn);

drivers/hwspinlock/qcom_hwspinlock.c+32−10

@@ -22,6 +22,7 @@ · 21 unmodified lines
22	22	struct qcom_hwspinlock_of_data {
23	23	u32 offset;
24	24	u32 stride;
	25	+ const struct regmap_config *regmap_config;
25	26	};
26	27
27	28	static int qcom_hwspinlock_trylock(struct hwspinlock *lock)
@@ -73,15 +74,42 @@ static const struct qcom_hwspinlock_of_data of_sfpb_mutex = { · 45 unmodified lines
73	74	.stride = 0x4,
74	75	};
75	76
76		−/* All modern platform has offset 0 and stride of 4k */
	77	+static const struct regmap_config tcsr_msm8226_mutex_config = {
	78	+ .reg_bits = 32,
	79	+ .reg_stride = 4,
	80	+ .val_bits = 32,
	81	+ .max_register = 0x1000,
	82	+ .fast_io = true,
	83	+};
	84	+
	85	+static const struct qcom_hwspinlock_of_data of_msm8226_tcsr_mutex = {
	86	+ .offset = 0,
	87	+ .stride = 0x80,
	88	+ .regmap_config = &tcsr_msm8226_mutex_config,
	89	+};
	90	+
	91	+static const struct regmap_config tcsr_mutex_config = {
	92	+ .reg_bits = 32,
	93	+ .reg_stride = 4,
	94	+ .val_bits = 32,
	95	+ .max_register = 0x20000,
	96	+ .fast_io = true,
	97	+};
	98	+
77	99	static const struct qcom_hwspinlock_of_data of_tcsr_mutex = {
78	100	.offset = 0,
79	101	.stride = 0x1000,
	102	+ .regmap_config = &tcsr_mutex_config,
80	103	};
81	104
82	105	static const struct of_device_id qcom_hwspinlock_of_match[] = {
83	106	{ .compatible = "qcom,sfpb-mutex", .data = &of_sfpb_mutex },
84	107	{ .compatible = "qcom,tcsr-mutex", .data = &of_tcsr_mutex },
	108	+ { .compatible = "qcom,apq8084-tcsr-mutex", .data = &of_msm8226_tcsr_mutex },
	109	+ { .compatible = "qcom,ipq6018-tcsr-mutex", .data = &of_msm8226_tcsr_mutex },
	110	+ { .compatible = "qcom,msm8226-tcsr-mutex", .data = &of_msm8226_tcsr_mutex },
	111	+ { .compatible = "qcom,msm8974-tcsr-mutex", .data = &of_msm8226_tcsr_mutex },
	112	+ { .compatible = "qcom,msm8994-tcsr-mutex", .data = &of_msm8226_tcsr_mutex },
85	113	{ }
86	114	};
87	115	MODULE_DEVICE_TABLE(of, qcom_hwspinlock_of_match);
@@ -117,14 +145,6 @@ static struct regmap qcom_hwspinlock_probe_syscon(struct platform_device pdev, · 29 unmodified lines
117	145	return regmap;
118	146	}
119	147
120		−static const struct regmap_config tcsr_mutex_config = {
121		− .reg_bits = 32,
122		− .reg_stride = 4,
123		− .val_bits = 32,
124		− .max_register = 0x40000,
125		− .fast_io = true,
126		−};
127		−
128	148	static struct regmap qcom_hwspinlock_probe_mmio(struct platform_device pdev,
129	149	u32 offset, u32 stride)
130	150	{
@@ -133,6 +153,8 @@ static struct regmap qcom_hwspinlock_probe_mmio(struct platform_device pdev, · 2 unmodified lines
133	153	void __iomem *base;
134	154
135	155	data = of_device_get_match_data(dev);
	156	+ if (!data->regmap_config)
	157	+ return ERR_PTR(-EINVAL);
136	158
137	159	*offset = data->offset;
138	160	*stride = data->stride;
@@ -141,7 +163,7 @@ static struct regmap qcom_hwspinlock_probe_mmio(struct platform_device pdev, · 2 unmodified lines
141	163	if (IS_ERR(base))
142	164	return ERR_CAST(base);
143	165
144		− return devm_regmap_init_mmio(dev, base, &tcsr_mutex_config);
	166	+ return devm_regmap_init_mmio(dev, base, data->regmap_config);
145	167	}
146	168
147	169	static int qcom_hwspinlock_probe(struct platform_device *pdev)

drivers/mmc/host/sdhci-brcmstb.c+2−1

@@ -12,6 +12,7 @@ · 11 unmodified lines
12	12	#include <linux/bitops.h>
13	13	#include <linux/delay.h>
14	14
	15	+#include "sdhci-cqhci.h"
15	16	#include "sdhci-pltfm.h"
16	17	#include "cqhci.h"
17	18
@@ -55,7 +56,7 @@ static void brcmstb_reset(struct sdhci_host *host, u8 mask) · 37 unmodified lines
55	56	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
56	57	struct sdhci_brcmstb_priv *priv = sdhci_pltfm_priv(pltfm_host);
57	58
58		− sdhci_reset(host, mask);
	59	+ sdhci_and_cqhci_reset(host, mask);
59	60
60	61	/* Reset will clear this, so re-enable it */
61	62	if (priv->flags & BRCMSTB_PRIV_FLAGS_GATE_CLOCK)

drivers/mmc/host/sdhci-cqhci.h+24−0

@@ -0,0 +1,24 @@
	1	+/* SPDX-License-Identifier: GPL-2.0-only */
	2	+/*
	3	+ * Copyright 2022 The Chromium OS Authors
	4	+ *
	5	+ * Support that applies to the combination of SDHCI and CQHCI, while not
	6	+ * expressing a dependency between the two modules.
	7	+ */
	8	+
	9	+#ifndef __MMC_HOST_SDHCI_CQHCI_H__
	10	+#define __MMC_HOST_SDHCI_CQHCI_H__
	11	+
	12	+#include "cqhci.h"
	13	+#include "sdhci.h"
	14	+
	15	+static inline void sdhci_and_cqhci_reset(struct sdhci_host *host, u8 mask)
	16	+{
	17	+ if ((host->mmc->caps2 & MMC_CAP2_CQE) && (mask & SDHCI_RESET_ALL) &&
	18	+ host->mmc->cqe_private)
	19	+ cqhci_deactivate(host->mmc);
	20	+
	21	+ sdhci_reset(host, mask);
	22	+}
	23	+
	24	+#endif /* __MMC_HOST_SDHCI_CQHCI_H__ */

drivers/mmc/host/sdhci-esdhc-imx.c+4−3

@@ -25,6 +25,7 @@ · 24 unmodified lines
25	25	#include <linux/of_device.h>
26	26	#include <linux/pinctrl/consumer.h>
27	27	#include <linux/pm_runtime.h>
	28	+#include "sdhci-cqhci.h"
28	29	#include "sdhci-pltfm.h"
29	30	#include "sdhci-esdhc.h"
30	31	#include "cqhci.h"
@@ -1288,7 +1289,7 @@ static void esdhc_set_uhs_signaling(struct sdhci_host *host, unsigned timing) · 1257 unmodified lines
1288	1289
1289	1290	static void esdhc_reset(struct sdhci_host *host, u8 mask)
1290	1291	{
1291		− sdhci_reset(host, mask);
	1292	+ sdhci_and_cqhci_reset(host, mask);
1292	1293
1293	1294	sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
1294	1295	sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
@@ -1671,14 +1672,14 @@ static int sdhci_esdhc_imx_probe(struct platform_device *pdev) · 376 unmodified lines
1671	1672	if (imx_data->socdata->flags & ESDHC_FLAG_ERR004536)
1672	1673	host->quirks \|= SDHCI_QUIRK_BROKEN_ADMA;
1673	1674
1674		− if (host->caps & MMC_CAP_8_BIT_DATA &&
	1675	+ if (host->mmc->caps & MMC_CAP_8_BIT_DATA &&
1675	1676	imx_data->socdata->flags & ESDHC_FLAG_HS400)
1676	1677	host->mmc->caps2 \|= MMC_CAP2_HS400;
1677	1678
1678	1679	if (imx_data->socdata->flags & ESDHC_FLAG_BROKEN_AUTO_CMD23)
1679	1680	host->quirks2 \|= SDHCI_QUIRK2_ACMD23_BROKEN;
1680	1681
1681		− if (host->caps & MMC_CAP_8_BIT_DATA &&
	1682	+ if (host->mmc->caps & MMC_CAP_8_BIT_DATA &&
1682	1683	imx_data->socdata->flags & ESDHC_FLAG_HS400_ES) {
1683	1684	host->mmc->caps2 \|= MMC_CAP2_HS400_ES;
1684	1685	host->mmc_host_ops.hs400_enhanced_strobe =

drivers/mmc/host/sdhci-of-arasan.c+2−1

@@ -25,6 +25,7 @@ · 24 unmodified lines
25	25	#include <linux/firmware/xlnx-zynqmp.h>
26	26
27	27	#include "cqhci.h"
	28	+#include "sdhci-cqhci.h"
28	29	#include "sdhci-pltfm.h"
29	30
30	31	#define SDHCI_ARASAN_VENDOR_REGISTER 0x78
@@ -366,7 +367,7 @@ static void sdhci_arasan_reset(struct sdhci_host *host, u8 mask) · 335 unmodified lines
366	367	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
367	368	struct sdhci_arasan_data *sdhci_arasan = sdhci_pltfm_priv(pltfm_host);
368	369
369		− sdhci_reset(host, mask);
	370	+ sdhci_and_cqhci_reset(host, mask);
370	371
371	372	if (sdhci_arasan->quirks & SDHCI_ARASAN_QUIRK_FORCE_CDTEST) {
372	373	ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);

drivers/mmc/host/sdhci-tegra.c+2−1

@@ -28,6 +28,7 @@ · 27 unmodified lines
28	28
29	29	#include <soc/tegra/common.h>
30	30
	31	+#include "sdhci-cqhci.h"
31	32	#include "sdhci-pltfm.h"
32	33	#include "cqhci.h"
33	34
@@ -367,7 +368,7 @@ static void tegra_sdhci_reset(struct sdhci_host *host, u8 mask) · 333 unmodified lines
367	368	const struct sdhci_tegra_soc_data *soc_data = tegra_host->soc_data;
368	369	u32 misc_ctrl, clk_ctrl, pad_ctrl;
369	370
370		− sdhci_reset(host, mask);
	371	+ sdhci_and_cqhci_reset(host, mask);
371	372
372	373	if (!(mask & SDHCI_RESET_ALL))
373	374	return;

drivers/mmc/host/sdhci_am654.c+4−3

@@ -15,6 +15,7 @@ · 14 unmodified lines
15	15	#include <linux/sys_soc.h>
16	16
17	17	#include "cqhci.h"
	18	+#include "sdhci-cqhci.h"
18	19	#include "sdhci-pltfm.h"
19	20
20	21	/* CTL_CFG Registers */
@@ -378,7 +379,7 @@ static void sdhci_am654_reset(struct sdhci_host *host, u8 mask) · 357 unmodified lines
378	379	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
379	380	struct sdhci_am654_data *sdhci_am654 = sdhci_pltfm_priv(pltfm_host);
380	381
381		− sdhci_reset(host, mask);
	382	+ sdhci_and_cqhci_reset(host, mask);
382	383
383	384	if (sdhci_am654->quirks & SDHCI_AM654_QUIRK_FORCE_CDTEST) {
384	385	ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
@@ -464,7 +465,7 @@ static struct sdhci_ops sdhci_am654_ops = { · 79 unmodified lines
464	465	.set_clock = sdhci_am654_set_clock,
465	466	.write_b = sdhci_am654_write_b,
466	467	.irq = sdhci_am654_cqhci_irq,
467		− .reset = sdhci_reset,
	468	+ .reset = sdhci_and_cqhci_reset,
468	469	};
469	470
470	471	static const struct sdhci_pltfm_data sdhci_am654_pdata = {
@@ -494,7 +495,7 @@ static struct sdhci_ops sdhci_j721e_8bit_ops = { · 23 unmodified lines
494	495	.set_clock = sdhci_am654_set_clock,
495	496	.write_b = sdhci_am654_write_b,
496	497	.irq = sdhci_am654_cqhci_irq,
497		− .reset = sdhci_reset,
	498	+ .reset = sdhci_and_cqhci_reset,
498	499	};
499	500
500	501	static const struct sdhci_pltfm_data sdhci_j721e_8bit_pdata = {

drivers/net/can/at91_can.c+1−1

@@ -452,7 +452,7 @@ static netdev_tx_t at91_start_xmit(struct sk_buff skb, struct net_device dev) · 451 unmodified lines
452	452	unsigned int mb, prio;
453	453	u32 reg_mid, reg_mcr;
454	454
455		− if (can_dropped_invalid_skb(dev, skb))
	455	+ if (can_dev_dropped_skb(dev, skb))
456	456	return NETDEV_TX_OK;
457	457
458	458	mb = get_tx_next_mb(priv);

drivers/net/can/c_can/c_can_main.c+1−1

@@ -457,7 +457,7 @@ static netdev_tx_t c_can_start_xmit(struct sk_buff *skb, · 456 unmodified lines
457	457	struct c_can_tx_ring *tx_ring = &priv->tx;
458	458	u32 idx, obj, cmd = IF_COMM_TX;
459	459
460		− if (can_dropped_invalid_skb(dev, skb))
	460	+ if (can_dev_dropped_skb(dev, skb))
461	461	return NETDEV_TX_OK;
462	462
463	463	if (c_can_tx_busy(priv, tx_ring))

drivers/net/can/can327.c+1−1

@@ -813,7 +813,7 @@ static netdev_tx_t can327_netdev_start_xmit(struct sk_buff *skb, · 812 unmodified lines
813	813	struct can327 *elm = netdev_priv(dev);
814	814	struct can_frame frame = (struct can_frame )skb->data;
815	815
816		− if (can_dropped_invalid_skb(dev, skb))
	816	+ if (can_dev_dropped_skb(dev, skb))
817	817	return NETDEV_TX_OK;
818	818
819	819	/* We shouldn't get here after a hardware fault:

drivers/net/can/cc770/cc770.c+1−1

@@ -429,7 +429,7 @@ static netdev_tx_t cc770_start_xmit(struct sk_buff skb, struct net_device dev) · 428 unmodified lines
429	429	struct cc770_priv *priv = netdev_priv(dev);
430	430	unsigned int mo = obj2msgobj(CC770_OBJ_TX);
431	431
432		− if (can_dropped_invalid_skb(dev, skb))
	432	+ if (can_dev_dropped_skb(dev, skb))
433	433	return NETDEV_TX_OK;
434	434
435	435	netif_stop_queue(dev);

drivers/net/can/ctucanfd/ctucanfd_base.c+1−1

@@ -600,7 +600,7 @@ static netdev_tx_t ctucan_start_xmit(struct sk_buff skb, struct net_device nde · 599 unmodified lines
600	600	bool ok;
601	601	unsigned long flags;
602	602
603		− if (can_dropped_invalid_skb(ndev, skb))
	603	+ if (can_dev_dropped_skb(ndev, skb))
604	604	return NETDEV_TX_OK;
605	605
606	606	if (unlikely(!CTU_CAN_FD_TXTNF(priv))) {

drivers/net/can/dev/skb.c+1−9

@@ -5,7 +5,6 @@ · 4 unmodified lines
5	5	*/
6	6
7	7	#include <linux/can/dev.h>
8		−#include <linux/can/netlink.h>
9	8	#include <linux/module.h>
10	9
11	10	#define MOD_DESC "CAN device driver interface"
@@ -337,8 +336,6 @@ static bool can_skb_headroom_valid(struct net_device dev, struct sk_buff skb) · 325 unmodified lines
337	336	/* Drop a given socketbuffer if it does not contain a valid CAN frame. */
338	337	bool can_dropped_invalid_skb(struct net_device dev, struct sk_buff skb)
339	338	{
340		− struct can_priv *priv = netdev_priv(dev);
341		−
342	339	switch (ntohs(skb->protocol)) {
343	340	case ETH_P_CAN:
344	341	if (!can_is_can_skb(skb))
@@ -359,13 +356,8 @@ bool can_dropped_invalid_skb(struct net_device dev, struct sk_buff skb) · 14 unmodified lines
359	356	goto inval_skb;
360	357	}
361	358
362		− if (!can_skb_headroom_valid(dev, skb)) {
	359	+ if (!can_skb_headroom_valid(dev, skb))
363	360	goto inval_skb;
364		− } else if (priv->ctrlmode & CAN_CTRLMODE_LISTENONLY) {
365		− netdev_info_once(dev,
366		− "interface in listen only mode, dropping skb\n");
367		− goto inval_skb;
368		− }
369	361
370	362	return false;
371	363

drivers/net/can/flexcan/flexcan-core.c+1−1

@@ -742,7 +742,7 @@ static netdev_tx_t flexcan_start_xmit(struct sk_buff skb, struct net_device de · 741 unmodified lines
742	742	u32 ctrl = FLEXCAN_MB_CODE_TX_DATA \| ((can_fd_len2dlc(cfd->len)) << 16);
743	743	int i;
744	744
745		− if (can_dropped_invalid_skb(dev, skb))
	745	+ if (can_dev_dropped_skb(dev, skb))
746	746	return NETDEV_TX_OK;
747	747
748	748	netif_stop_queue(dev);

drivers/net/can/grcan.c+1−1

@@ -1345,7 +1345,7 @@ static netdev_tx_t grcan_start_xmit(struct sk_buff *skb, · 1344 unmodified lines
1345	1345	unsigned long flags;
1346	1346	u32 oneshotmode = priv->can.ctrlmode & CAN_CTRLMODE_ONE_SHOT;
1347	1347
1348		− if (can_dropped_invalid_skb(dev, skb))
	1348	+ if (can_dev_dropped_skb(dev, skb))
1349	1349	return NETDEV_TX_OK;
1350	1350
1351	1351	/* Trying to transmit in silent mode will generate error interrupts, but

drivers/net/can/ifi_canfd/ifi_canfd.c+1−1

@@ -860,7 +860,7 @@ static netdev_tx_t ifi_canfd_start_xmit(struct sk_buff *skb, · 859 unmodified lines
860	860	u32 txst, txid, txdlc;
861	861	int i;
862	862
863		− if (can_dropped_invalid_skb(ndev, skb))
	863	+ if (can_dev_dropped_skb(ndev, skb))
864	864	return NETDEV_TX_OK;
865	865
866	866	/* Check if the TX buffer is full */

drivers/net/can/janz-ican3.c+1−1

@@ -1693,7 +1693,7 @@ static netdev_tx_t ican3_xmit(struct sk_buff skb, struct net_device ndev) · 1692 unmodified lines
1693	1693	void __iomem *desc_addr;
1694	1694	unsigned long flags;
1695	1695
1696		− if (can_dropped_invalid_skb(ndev, skb))
	1696	+ if (can_dev_dropped_skb(ndev, skb))
1697	1697	return NETDEV_TX_OK;
1698	1698
1699	1699	spin_lock_irqsave(&mod->lock, flags);

drivers/net/can/kvaser_pciefd.c+1−1

@@ -772,7 +772,7 @@ static netdev_tx_t kvaser_pciefd_start_xmit(struct sk_buff *skb, · 771 unmodified lines
772	772	int nwords;
773	773	u8 count;
774	774
775		− if (can_dropped_invalid_skb(netdev, skb))
	775	+ if (can_dev_dropped_skb(netdev, skb))
776	776	return NETDEV_TX_OK;
777	777
778	778	nwords = kvaser_pciefd_prepare_tx_packet(&packet, can, skb);

drivers/net/can/m_can/m_can.c+1−1

@@ -1721,7 +1721,7 @@ static netdev_tx_t m_can_start_xmit(struct sk_buff *skb, · 1720 unmodified lines
1721	1721	{
1722	1722	struct m_can_classdev *cdev = netdev_priv(dev);
1723	1723
1724		− if (can_dropped_invalid_skb(dev, skb))
	1724	+ if (can_dev_dropped_skb(dev, skb))
1725	1725	return NETDEV_TX_OK;
1726	1726
1727	1727	if (cdev->is_peripheral) {

drivers/net/can/mscan/mscan.c+1−1

@@ -191,7 +191,7 @@ static netdev_tx_t mscan_start_xmit(struct sk_buff skb, struct net_device dev) · 190 unmodified lines
191	191	int i, rtr, buf_id;
192	192	u32 can_id;
193	193
194		− if (can_dropped_invalid_skb(dev, skb))
	194	+ if (can_dev_dropped_skb(dev, skb))
195	195	return NETDEV_TX_OK;
196	196
197	197	out_8(&regs->cantier, 0);

drivers/net/can/pch_can.c+1−1

@@ -882,7 +882,7 @@ static netdev_tx_t pch_xmit(struct sk_buff skb, struct net_device ndev) · 881 unmodified lines
882	882	int i;
883	883	u32 id2;
884	884
885		− if (can_dropped_invalid_skb(ndev, skb))
	885	+ if (can_dev_dropped_skb(ndev, skb))
886	886	return NETDEV_TX_OK;
887	887
888	888	tx_obj_no = priv->tx_obj;

drivers/net/can/peak_canfd/peak_canfd.c+1−1

@@ -651,7 +651,7 @@ static netdev_tx_t peak_canfd_start_xmit(struct sk_buff *skb, · 650 unmodified lines
651	651	int room_left;
652	652	u8 len;
653	653
654		− if (can_dropped_invalid_skb(ndev, skb))
	654	+ if (can_dev_dropped_skb(ndev, skb))
655	655	return NETDEV_TX_OK;
656	656
657	657	msg_size = ALIGN(sizeof(*msg) + cf->len, 4);

drivers/net/can/rcar/rcar_can.c+1−1

@@ -590,7 +590,7 @@ static netdev_tx_t rcar_can_start_xmit(struct sk_buff *skb, · 589 unmodified lines
590	590	struct can_frame cf = (struct can_frame )skb->data;
591	591	u32 data, i;
592	592
593		− if (can_dropped_invalid_skb(ndev, skb))
	593	+ if (can_dev_dropped_skb(ndev, skb))
594	594	return NETDEV_TX_OK;
595	595
596	596	if (cf->can_id & CAN_EFF_FLAG) /* Extended frame format */

drivers/net/can/rcar/rcar_canfd.c+5−10

@@ -81,8 +81,7 @@ enum rcanfd_chip_id { · 80 unmodified lines
81	81
82	82	/* RSCFDnCFDGERFL / RSCFDnGERFL */
83	83	#define RCANFD_GERFL_EEF0_7 GENMASK(23, 16)
84		−#define RCANFD_GERFL_EEF1 BIT(17)
85		−#define RCANFD_GERFL_EEF0 BIT(16)
	84	+#define RCANFD_GERFL_EEF(ch) BIT(16 + (ch))
86	85	#define RCANFD_GERFL_CMPOF BIT(3) /* CAN FD only */
87	86	#define RCANFD_GERFL_THLES BIT(2)
88	87	#define RCANFD_GERFL_MES BIT(1)
@@ -90,7 +89,7 @@ enum rcanfd_chip_id { · 1 unmodified line
90	89
91	90	#define RCANFD_GERFL_ERR(gpriv, x) \
92	91	((x) & (reg_v3u(gpriv, RCANFD_GERFL_EEF0_7, \
93		− RCANFD_GERFL_EEF0 \| RCANFD_GERFL_EEF1) \| \
	92	+ RCANFD_GERFL_EEF(0) \| RCANFD_GERFL_EEF(1)) \| \
94	93	RCANFD_GERFL_MES \| \
95	94	((gpriv)->fdmode ? RCANFD_GERFL_CMPOF : 0)))
96	95
@@ -936,12 +935,8 @@ static void rcar_canfd_global_error(struct net_device *ndev) · 839 unmodified lines
936	935	u32 ridx = ch + RCANFD_RFFIFO_IDX;
937	936
938	937	gerfl = rcar_canfd_read(priv->base, RCANFD_GERFL);
939		− if ((gerfl & RCANFD_GERFL_EEF0) && (ch == 0)) {
940		− netdev_dbg(ndev, "Ch0: ECC Error flag\n");
941		− stats->tx_dropped++;
942		− }
943		− if ((gerfl & RCANFD_GERFL_EEF1) && (ch == 1)) {
944		− netdev_dbg(ndev, "Ch1: ECC Error flag\n");
	938	+ if (gerfl & RCANFD_GERFL_EEF(ch)) {
	939	+ netdev_dbg(ndev, "Ch%u: ECC Error flag\n", ch);
945	940	stats->tx_dropped++;
946	941	}
947	942	if (gerfl & RCANFD_GERFL_MES) {
@@ -1481,7 +1476,7 @@ static netdev_tx_t rcar_canfd_start_xmit(struct sk_buff *skb, · 533 unmodified lines
1481	1476	unsigned long flags;
1482	1477	u32 ch = priv->channel;
1483	1478
1484		− if (can_dropped_invalid_skb(ndev, skb))
	1479	+ if (can_dev_dropped_skb(ndev, skb))
1485	1480	return NETDEV_TX_OK;
1486	1481
1487	1482	if (cf->can_id & CAN_EFF_FLAG) {

drivers/net/can/sja1000/sja1000.c+1−1

@@ -291,7 +291,7 @@ static netdev_tx_t sja1000_start_xmit(struct sk_buff *skb, · 290 unmodified lines
291	291	u8 cmd_reg_val = 0x00;
292	292	int i;
293	293
294		− if (can_dropped_invalid_skb(dev, skb))
	294	+ if (can_dev_dropped_skb(dev, skb))
295	295	return NETDEV_TX_OK;
296	296
297	297	netif_stop_queue(dev);

drivers/net/can/slcan/slcan-core.c+1−1

@@ -594,7 +594,7 @@ static netdev_tx_t slcan_netdev_xmit(struct sk_buff *skb, · 593 unmodified lines
594	594	{
595	595	struct slcan *sl = netdev_priv(dev);
596	596
597		− if (can_dropped_invalid_skb(dev, skb))
	597	+ if (can_dev_dropped_skb(dev, skb))
598	598	return NETDEV_TX_OK;
599	599
600	600	spin_lock(&sl->lock);

drivers/net/can/softing/softing_main.c+1−1

@@ -60,7 +60,7 @@ static netdev_tx_t softing_netdev_start_xmit(struct sk_buff *skb, · 59 unmodified lines
60	60	struct can_frame cf = (struct can_frame )skb->data;
61	61	uint8_t buf[DPRAM_TX_SIZE];
62	62
63		− if (can_dropped_invalid_skb(dev, skb))
	63	+ if (can_dev_dropped_skb(dev, skb))
64	64	return NETDEV_TX_OK;
65	65
66	66	spin_lock(&card->spin);

drivers/net/can/spi/hi311x.c+1−1

@@ -373,7 +373,7 @@ static netdev_tx_t hi3110_hard_start_xmit(struct sk_buff *skb, · 372 unmodified lines
373	373	return NETDEV_TX_BUSY;
374	374	}
375	375
376		− if (can_dropped_invalid_skb(net, skb))
	376	+ if (can_dev_dropped_skb(net, skb))
377	377	return NETDEV_TX_OK;
378	378
379	379	netif_stop_queue(net);

drivers/net/can/spi/mcp251x.c+1−1

@@ -789,7 +789,7 @@ static netdev_tx_t mcp251x_hard_start_xmit(struct sk_buff *skb, · 788 unmodified lines
789	789	return NETDEV_TX_BUSY;
790	790	}
791	791
792		− if (can_dropped_invalid_skb(net, skb))
	792	+ if (can_dev_dropped_skb(net, skb))
793	793	return NETDEV_TX_OK;
794	794
795	795	netif_stop_queue(net);

drivers/net/can/spi/mcp251xfd/mcp251xfd-tx.c+1−1

@@ -172,7 +172,7 @@ netdev_tx_t mcp251xfd_start_xmit(struct sk_buff *skb, · 171 unmodified lines
172	172	u8 tx_head;
173	173	int err;
174	174
175		− if (can_dropped_invalid_skb(ndev, skb))
	175	+ if (can_dev_dropped_skb(ndev, skb))
176	176	return NETDEV_TX_OK;
177	177
178	178	if (mcp251xfd_tx_busy(priv, tx_ring))

drivers/net/can/sun4i_can.c+1−1

@@ -429,7 +429,7 @@ static netdev_tx_t sun4ican_start_xmit(struct sk_buff skb, struct net_device d · 428 unmodified lines
429	429	canid_t id;
430	430	int i;
431	431
432		− if (can_dropped_invalid_skb(dev, skb))
	432	+ if (can_dev_dropped_skb(dev, skb))
433	433	return NETDEV_TX_OK;
434	434
435	435	netif_stop_queue(dev);

drivers/net/can/ti_hecc.c+1−1

@@ -470,7 +470,7 @@ static netdev_tx_t ti_hecc_xmit(struct sk_buff skb, struct net_device ndev) · 469 unmodified lines
470	470	u32 mbxno, mbx_mask, data;
471	471	unsigned long flags;
472	472
473		− if (can_dropped_invalid_skb(ndev, skb))
	473	+ if (can_dev_dropped_skb(ndev, skb))
474	474	return NETDEV_TX_OK;
475	475
476	476	mbxno = get_tx_head_mb(priv);

drivers/net/can/usb/ems_usb.c+1−1

@@ -747,7 +747,7 @@ static netdev_tx_t ems_usb_start_xmit(struct sk_buff skb, struct net_device ne · 746 unmodified lines
747	747	size_t size = CPC_HEADER_SIZE + CPC_MSG_HEADER_LEN
748	748	+ sizeof(struct cpc_can_msg);
749	749
750		− if (can_dropped_invalid_skb(netdev, skb))
	750	+ if (can_dev_dropped_skb(netdev, skb))
751	751	return NETDEV_TX_OK;
752	752
753	753	/* create a URB, and a buffer for it, and copy the data to the URB */

drivers/net/can/usb/esd_usb.c+1−1

@@ -725,7 +725,7 @@ static netdev_tx_t esd_usb_start_xmit(struct sk_buff *skb, · 724 unmodified lines
725	725	int ret = NETDEV_TX_OK;
726	726	size_t size = sizeof(struct esd_usb_msg);
727	727
728		− if (can_dropped_invalid_skb(netdev, skb))
	728	+ if (can_dev_dropped_skb(netdev, skb))
729	729	return NETDEV_TX_OK;
730	730
731	731	/* create a URB, and a buffer for it, and copy the data to the URB */

drivers/net/can/usb/etas_es58x/es58x_core.c+1−1

@@ -1913,7 +1913,7 @@ static netdev_tx_t es58x_start_xmit(struct sk_buff *skb, · 1912 unmodified lines
1913	1913	unsigned int frame_len;
1914	1914	int ret;
1915	1915
1916		− if (can_dropped_invalid_skb(netdev, skb)) {
	1916	+ if (can_dev_dropped_skb(netdev, skb)) {
1917	1917	if (priv->tx_urb)
1918	1918	goto xmit_commit;
1919	1919	return NETDEV_TX_OK;

drivers/net/can/usb/gs_usb.c+1−1

@@ -723,7 +723,7 @@ static netdev_tx_t gs_can_start_xmit(struct sk_buff *skb, · 722 unmodified lines
723	723	unsigned int idx;
724	724	struct gs_tx_context *txc;
725	725
726		− if (can_dropped_invalid_skb(netdev, skb))
	726	+ if (can_dev_dropped_skb(netdev, skb))
727	727	return NETDEV_TX_OK;
728	728
729	729	/* find an empty context to keep track of transmission */

drivers/net/can/usb/kvaser_usb/kvaser_usb_core.c+1−1

@@ -570,7 +570,7 @@ static netdev_tx_t kvaser_usb_start_xmit(struct sk_buff *skb, · 569 unmodified lines
570	570	unsigned int i;
571	571	unsigned long flags;
572	572
573		− if (can_dropped_invalid_skb(netdev, skb))
	573	+ if (can_dev_dropped_skb(netdev, skb))
574	574	return NETDEV_TX_OK;
575	575
576	576	urb = usb_alloc_urb(0, GFP_ATOMIC);

drivers/net/can/usb/mcba_usb.c+1−1

@@ -311,7 +311,7 @@ static netdev_tx_t mcba_usb_start_xmit(struct sk_buff *skb, · 310 unmodified lines
311	311	.cmd_id = MBCA_CMD_TRANSMIT_MESSAGE_EV
312	312	};
313	313
314		− if (can_dropped_invalid_skb(netdev, skb))
	314	+ if (can_dev_dropped_skb(netdev, skb))
315	315	return NETDEV_TX_OK;
316	316
317	317	ctx = mcba_usb_get_free_ctx(priv, cf);

drivers/net/can/usb/peak_usb/pcan_usb_core.c+1−1

@@ -351,7 +351,7 @@ static netdev_tx_t peak_usb_ndo_start_xmit(struct sk_buff *skb, · 350 unmodified lines
351	351	int i, err;
352	352	size_t size = dev->adapter->tx_buffer_size;
353	353
354		− if (can_dropped_invalid_skb(netdev, skb))
	354	+ if (can_dev_dropped_skb(netdev, skb))
355	355	return NETDEV_TX_OK;
356	356
357	357	for (i = 0; i < PCAN_USB_MAX_TX_URBS; i++)

drivers/net/can/usb/ucan.c+1−1

@@ -1120,7 +1120,7 @@ static netdev_tx_t ucan_start_xmit(struct sk_buff *skb, · 1119 unmodified lines
1120	1120	struct can_frame cf = (struct can_frame )skb->data;
1121	1121
1122	1122	/* check skb */
1123		− if (can_dropped_invalid_skb(netdev, skb))
	1123	+ if (can_dev_dropped_skb(netdev, skb))
1124	1124	return NETDEV_TX_OK;
1125	1125
1126	1126	/* allocate a context and slow down tx path, if fifo state is low */

drivers/net/can/usb/usb_8dev.c+1−1

@@ -602,7 +602,7 @@ static netdev_tx_t usb_8dev_start_xmit(struct sk_buff *skb, · 601 unmodified lines
602	602	int i, err;
603	603	size_t size = sizeof(struct usb_8dev_tx_msg);
604	604
605		− if (can_dropped_invalid_skb(netdev, skb))
	605	+ if (can_dev_dropped_skb(netdev, skb))
606	606	return NETDEV_TX_OK;
607	607
608	608	/* create a URB, and a buffer for it, and copy the data to the URB */

drivers/net/can/xilinx_can.c+1−1

@@ -743,7 +743,7 @@ static netdev_tx_t xcan_start_xmit(struct sk_buff skb, struct net_device ndev) · 742 unmodified lines
743	743	struct xcan_priv *priv = netdev_priv(ndev);
744	744	int ret;
745	745
746		− if (can_dropped_invalid_skb(ndev, skb))
	746	+ if (can_dev_dropped_skb(ndev, skb))
747	747	return NETDEV_TX_OK;
748	748
749	749	if (priv->devtype.flags & XCAN_FLAG_TX_MAILBOXES)

drivers/net/ethernet/apm/xgene/xgene_enet_main.c+3−1

@@ -1004,8 +1004,10 @@ static int xgene_enet_open(struct net_device *ndev) · 1003 unmodified lines
1004	1004
1005	1005	xgene_enet_napi_enable(pdata);
1006	1006	ret = xgene_enet_register_irq(ndev);
1007		− if (ret)
	1007	+ if (ret) {
	1008	+ xgene_enet_napi_disable(pdata);
1008	1009	return ret;
	1010	+ }
1009	1011
1010	1012	if (ndev->phydev) {
1011	1013	phy_start(ndev->phydev);

drivers/net/ethernet/aquantia/atlantic/aq_macsec.c+2−0

@@ -570,6 +570,7 @@ static int aq_update_txsa(struct aq_nic_s *nic, const unsigned int sc_idx, · 569 unmodified lines
570	570
571	571	ret = aq_mss_set_egress_sakey_record(hw, &key_rec, sa_idx);
572	572
	573	+ memzero_explicit(&key_rec, sizeof(key_rec));
573	574	return ret;
574	575	}
575	576
@@ -899,6 +900,7 @@ static int aq_update_rxsa(struct aq_nic_s *nic, const unsigned int sc_idx, · 323 unmodified lines
899	900
900	901	ret = aq_mss_set_ingress_sakey_record(hw, &sa_key_record, sa_idx);
901	902
	903	+ memzero_explicit(&sa_key_record, sizeof(sa_key_record));
902	904	return ret;
903	905	}
904	906

drivers/net/ethernet/aquantia/atlantic/macsec/macsec_api.c+11−7

@@ -757,6 +757,7 @@ set_ingress_sakey_record(struct aq_hw_s *hw, · 756 unmodified lines
757	757	u16 table_index)
758	758	{
759	759	u16 packed_record[18];
	760	+ int ret;
760	761
761	762	if (table_index >= NUMROWS_INGRESSSAKEYRECORD)
762	763	return -EINVAL;
@@ -789,9 +790,12 @@ set_ingress_sakey_record(struct aq_hw_s *hw, · 26 unmodified lines
789	790
790	791	packed_record[16] = rec->key_len & 0x3;
791	792
792		− return set_raw_ingress_record(hw, packed_record, 18, 2,
793		− ROWOFFSET_INGRESSSAKEYRECORD +
794		− table_index);
	793	+ ret = set_raw_ingress_record(hw, packed_record, 18, 2,
	794	+ ROWOFFSET_INGRESSSAKEYRECORD +
	795	+ table_index);
	796	+
	797	+ memzero_explicit(packed_record, sizeof(packed_record));
	798	+ return ret;
795	799	}
796	800
797	801	int aq_mss_set_ingress_sakey_record(struct aq_hw_s *hw,
@@ -1739,14 +1743,14 @@ static int set_egress_sakey_record(struct aq_hw_s *hw, · 941 unmodified lines
1739	1743	ret = set_raw_egress_record(hw, packed_record, 8, 2,
1740	1744	ROWOFFSET_EGRESSSAKEYRECORD + table_index);
1741	1745	if (unlikely(ret))
1742		− return ret;
	1746	+ goto clear_key;
1743	1747	ret = set_raw_egress_record(hw, packed_record + 8, 8, 2,
1744	1748	ROWOFFSET_EGRESSSAKEYRECORD + table_index -
1745	1749	32);
1746		− if (unlikely(ret))
1747		− return ret;
1748	1750
1749		− return 0;
	1751	+clear_key:
	1752	+ memzero_explicit(packed_record, sizeof(packed_record));
	1753	+ return ret;
1750	1754	}
1751	1755
1752	1756	int aq_mss_set_egress_sakey_record(struct aq_hw_s *hw,

drivers/net/ethernet/broadcom/Kconfig+1−1

@@ -77,7 +77,7 @@ config BCMGENET · 76 unmodified lines
77	77	select BCM7XXX_PHY
78	78	select MDIO_BCM_UNIMAC
79	79	select DIMLIB
80		− select BROADCOM_PHY if ARCH_BCM2835
	80	+ select BROADCOM_PHY if (ARCH_BCM2835 && PTP_1588_CLOCK_OPTIONAL)
81	81	help
82	82	This driver supports the built-in Ethernet MACs found in the
83	83	Broadcom BCM7xxx Set Top Box family chipset.

drivers/net/ethernet/broadcom/bnxt/bnxt.c+45−9

@@ -9983,17 +9983,12 @@ static int bnxt_try_recover_fw(struct bnxt *bp) · 9982 unmodified lines
9983	9983	return -ENODEV;
9984	9984	}
9985	9985
9986		−int bnxt_cancel_reservations(struct bnxt *bp, bool fw_reset)
	9986	+static void bnxt_clear_reservations(struct bnxt *bp, bool fw_reset)
9987	9987	{
9988	9988	struct bnxt_hw_resc *hw_resc = &bp->hw_resc;
9989		− int rc;
9990	9989
9991	9990	if (!BNXT_NEW_RM(bp))
9992		− return 0; /* no resource reservations required */
9993		−
9994		− rc = bnxt_hwrm_func_resc_qcaps(bp, true);
9995		− if (rc)
9996		− netdev_err(bp->dev, "resc_qcaps failed\n");
	9991	+ return; /* no resource reservations required */
9997	9992
9998	9993	hw_resc->resv_cp_rings = 0;
9999	9994	hw_resc->resv_stat_ctxs = 0;
@@ -10006,6 +10001,20 @@ int bnxt_cancel_reservations(struct bnxt *bp, bool fw_reset) · 6 unmodified lines
10006	10001	bp->tx_nr_rings = 0;
10007	10002	bp->rx_nr_rings = 0;
10008	10003	}
	10004	+}
	10005	+
	10006	+int bnxt_cancel_reservations(struct bnxt *bp, bool fw_reset)
	10007	+{
	10008	+ int rc;
	10009	+
	10010	+ if (!BNXT_NEW_RM(bp))
	10011	+ return 0; /* no resource reservations required */
	10012	+
	10013	+ rc = bnxt_hwrm_func_resc_qcaps(bp, true);
	10014	+ if (rc)
	10015	+ netdev_err(bp->dev, "resc_qcaps failed\n");
	10016	+
	10017	+ bnxt_clear_reservations(bp, fw_reset);
10009	10018
10010	10019	return rc;
10011	10020	}
@@ -12894,8 +12903,8 @@ static int bnxt_rx_flow_steer(struct net_device dev, const struct sk_buff skb, · 2882 unmodified lines
12894	12903	rcu_read_lock();
12895	12904	hlist_for_each_entry_rcu(fltr, head, hash) {
12896	12905	if (bnxt_fltr_match(fltr, new_fltr)) {
	12906	+ rc = fltr->sw_id;
12897	12907	rcu_read_unlock();
12898		− rc = 0;
12899	12908	goto err_free;
12900	12909	}
12901	12910	}
@@ -13913,7 +13922,9 @@ static pci_ers_result_t bnxt_io_slot_reset(struct pci_dev *pdev) · 1011 unmodified lines
13913	13922	pci_ers_result_t result = PCI_ERS_RESULT_DISCONNECT;
13914	13923	struct net_device *netdev = pci_get_drvdata(pdev);
13915	13924	struct bnxt *bp = netdev_priv(netdev);
13916		− int err = 0, off;
	13925	+ int retry = 0;
	13926	+ int err = 0;
	13927	+ int off;
13917	13928
13918	13929	netdev_info(bp->dev, "PCI Slot Reset\n");
13919	13930
@@ -13941,11 +13952,36 @@ static pci_ers_result_t bnxt_io_slot_reset(struct pci_dev *pdev) · 21 unmodified lines
13941	13952	pci_restore_state(pdev);
13942	13953	pci_save_state(pdev);
13943	13954
	13955	+ bnxt_inv_fw_health_reg(bp);
	13956	+ bnxt_try_map_fw_health_reg(bp);
	13957	+
	13958	+ /* In some PCIe AER scenarios, firmware may take up to
	13959	+ * 10 seconds to become ready in the worst case.
	13960	+ */
	13961	+ do {
	13962	+ err = bnxt_try_recover_fw(bp);
	13963	+ if (!err)
	13964	+ break;
	13965	+ retry++;
	13966	+ } while (retry < BNXT_FW_SLOT_RESET_RETRY);
	13967	+
	13968	+ if (err) {
	13969	+ dev_err(&pdev->dev, "Firmware not ready\n");
	13970	+ goto reset_exit;
	13971	+ }
	13972	+
13944	13973	err = bnxt_hwrm_func_reset(bp);
13945	13974	if (!err)
13946	13975	result = PCI_ERS_RESULT_RECOVERED;
	13976	+
	13977	+ bnxt_ulp_irq_stop(bp);
	13978	+ bnxt_clear_int_mode(bp);
	13979	+ err = bnxt_init_int_mode(bp);
	13980	+ bnxt_ulp_irq_restart(bp, err);
13947	13981	}
13948	13982
	13983	+reset_exit:
	13984	+ bnxt_clear_reservations(bp, true);
13949	13985	rtnl_unlock();
13950	13986
13951	13987	return result;

drivers/net/ethernet/broadcom/bnxt/bnxt.h+1−0

@@ -1621,6 +1621,7 @@ struct bnxt_fw_health { · 1620 unmodified lines
1621	1621
1622	1622	#define BNXT_FW_RETRY 5
1623	1623	#define BNXT_FW_IF_RETRY 10
	1624	+#define BNXT_FW_SLOT_RESET_RETRY 4
1624	1625
1625	1626	enum board_idx {
1626	1627	BCM57301,

drivers/net/ethernet/broadcom/bnxt/bnxt_ethtool.c+1−1

@@ -162,7 +162,7 @@ static int bnxt_set_coalesce(struct net_device *dev, · 161 unmodified lines
162	162	}
163	163
164	164	reset_coalesce:
165		− if (netif_running(dev)) {
	165	+ if (test_bit(BNXT_STATE_OPEN, &bp->state)) {
166	166	if (update_stats) {
167	167	rc = bnxt_close_nic(bp, true, false);
168	168	if (!rc)

drivers/net/ethernet/broadcom/bnxt/bnxt_hwrm.c+2−1

@@ -476,7 +476,8 @@ static int __hwrm_send(struct bnxt bp, struct bnxt_hwrm_ctx ctx) · 475 unmodified lines
476	476	memset(ctx->resp, 0, PAGE_SIZE);
477	477
478	478	req_type = le16_to_cpu(ctx->req->req_type);
479		− if (BNXT_NO_FW_ACCESS(bp) && req_type != HWRM_FUNC_RESET) {
	479	+ if (BNXT_NO_FW_ACCESS(bp) &&
	480	+ (req_type != HWRM_FUNC_RESET && req_type != HWRM_VER_GET)) {
480	481	netdev_dbg(bp->dev, "hwrm req_type 0x%x skipped, FW channel down\n",
481	482	req_type);
482	483	goto exit;

drivers/net/ethernet/chelsio/cxgb3/cxgb3_main.c+1−0

@@ -1301,6 +1301,7 @@ static int cxgb_up(struct adapter *adap) · 1300 unmodified lines
1301	1301	if (ret < 0) {
1302	1302	CH_ERR(adap, "failed to bind qsets, err %d\n", ret);
1303	1303	t3_intr_disable(adap);
	1304	+ quiesce_rx(adap);
1304	1305	free_irq_resources(adap);
1305	1306	err = ret;
1306	1307	goto out;

drivers/net/ethernet/chelsio/cxgb4vf/cxgb4vf_main.c+1−1

@@ -858,7 +858,7 @@ static int cxgb4vf_open(struct net_device *dev) · 857 unmodified lines
858	858	*/
859	859	err = t4vf_update_port_info(pi);
860	860	if (err < 0)
861		− return err;
	861	+ goto err_unwind;
862	862
863	863	/*
864	864	* Note that this interface is up and start everything up ...

drivers/net/ethernet/freescale/fman/mac.c+9−0

@@ -487,12 +487,21 @@ _return_of_node_put: · 486 unmodified lines
487	487	return err;
488	488	}
489	489
	490	+static int mac_remove(struct platform_device *pdev)
	491	+{
	492	+ struct mac_device *mac_dev = platform_get_drvdata(pdev);
	493	+
	494	+ platform_device_unregister(mac_dev->priv->eth_dev);
	495	+ return 0;
	496	+}
	497	+
490	498	static struct platform_driver mac_driver = {
491	499	.driver = {
492	500	.name = KBUILD_MODNAME,
493	501	.of_match_table = mac_match,
494	502	},
495	503	.probe = mac_probe,
	504	+ .remove = mac_remove,
496	505	};
497	506
498	507	builtin_platform_driver(mac_driver);

drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c+5−3

@@ -12984,14 +12984,16 @@ static void hclge_clean_vport_config(struct hnae3_ae_dev *ae_dev, int num_vfs) · 12983 unmodified lines
12984	12984	static int hclge_get_dscp_prio(struct hnae3_handle h, u8 dscp, u8 tc_mode,
12985	12985	u8 *priority)
12986	12986	{
	12987	+ struct hclge_vport *vport = hclge_get_vport(h);
	12988	+
12987	12989	if (dscp >= HNAE3_MAX_DSCP)
12988	12990	return -EINVAL;
12989	12991
12990	12992	if (tc_mode)
12991		− *tc_mode = h->kinfo.tc_map_mode;
	12993	+ *tc_mode = vport->nic.kinfo.tc_map_mode;
12992	12994	if (priority)
12993		− *priority = h->kinfo.dscp_prio[dscp] == HNAE3_PRIO_ID_INVALID ? 0 :
12994		− h->kinfo.dscp_prio[dscp];
	12995	+ *priority = vport->nic.kinfo.dscp_prio[dscp] == HNAE3_PRIO_ID_INVALID ? 0 :
	12996	+ vport->nic.kinfo.dscp_prio[dscp];
12995	12997
12996	12998	return 0;
12997	12999	}

drivers/net/ethernet/ibm/ibmveth.c+2−1

@@ -1757,7 +1757,8 @@ static int ibmveth_probe(struct vio_dev dev, const struct vio_device_id id) · 1756 unmodified lines
1757	1757	kobject_uevent(kobj, KOBJ_ADD);
1758	1758	}
1759	1759
1760		− rc = netif_set_real_num_tx_queues(netdev, ibmveth_real_max_tx_queues());
	1760	+ rc = netif_set_real_num_tx_queues(netdev, min(num_online_cpus(),
	1761	+ IBMVETH_DEFAULT_QUEUES));
1761	1762	if (rc) {
1762	1763	netdev_dbg(netdev, "failed to set number of tx queues rc=%d\n",
1763	1764	rc);

drivers/net/ethernet/ibm/ibmveth.h+1−0

@@ -100,6 +100,7 @@ static inline long h_illan_attributes(unsigned long unit_address, · 99 unmodified lines
100	100	#define IBMVETH_MAX_BUF_SIZE (1024 * 128)
101	101	#define IBMVETH_MAX_TX_BUF_SIZE (1024 * 64)
102	102	#define IBMVETH_MAX_QUEUES 16U
	103	+#define IBMVETH_DEFAULT_QUEUES 8U
103	104
104	105	static int pool_size[] = { 512, 1024 * 2, 1024 * 16, 1024 * 32, 1024 * 64 };
105	106	static int pool_count[] = { 256, 512, 256, 256, 256 };

drivers/net/ethernet/intel/iavf/iavf_virtchnl.c+2−0

@@ -2438,6 +2438,8 @@ void iavf_virtchnl_completion(struct iavf_adapter *adapter, · 2437 unmodified lines
2438	2438	list_for_each_entry(f, &adapter->vlan_filter_list, list) {
2439	2439	if (f->is_new_vlan) {
2440	2440	f->is_new_vlan = false;
	2441	+ if (!f->vlan.vid)
	2442	+ continue;
2441	2443	if (f->vlan.tpid == ETH_P_8021Q)
2442	2444	set_bit(f->vlan.vid,
2443	2445	adapter->vsi.active_cvlans);

drivers/net/ethernet/intel/ice/ice_base.c+1−1

@@ -958,7 +958,7 @@ ice_vsi_stop_tx_ring(struct ice_vsi *vsi, enum ice_disq_rst_src rst_src, · 957 unmodified lines
958	958	* associated to the queue to schedule NAPI handler
959	959	*/
960	960	q_vector = ring->q_vector;
961		− if (q_vector)
	961	+ if (q_vector && !(vsi->vf && ice_is_vf_disabled(vsi->vf)))
962	962	ice_trigger_sw_intr(hw, q_vector);
963	963
964	964	status = ice_dis_vsi_txq(vsi->port_info, txq_meta->vsi_idx,

drivers/net/ethernet/intel/ice/ice_lib.c+25−0

@@ -2239,6 +2239,31 @@ int ice_vsi_stop_xdp_tx_rings(struct ice_vsi *vsi) · 2238 unmodified lines
2239	2239	return ice_vsi_stop_tx_rings(vsi, ICE_NO_RESET, 0, vsi->xdp_rings, vsi->num_xdp_txq);
2240	2240	}
2241	2241
	2242	+/**
	2243	+ * ice_vsi_is_rx_queue_active
	2244	+ * @vsi: the VSI being configured
	2245	+ *
	2246	+ * Return true if at least one queue is active.
	2247	+ */
	2248	+bool ice_vsi_is_rx_queue_active(struct ice_vsi *vsi)
	2249	+{
	2250	+ struct ice_pf *pf = vsi->back;
	2251	+ struct ice_hw *hw = &pf->hw;
	2252	+ int i;
	2253	+
	2254	+ ice_for_each_rxq(vsi, i) {
	2255	+ u32 rx_reg;
	2256	+ int pf_q;
	2257	+
	2258	+ pf_q = vsi->rxq_map[i];
	2259	+ rx_reg = rd32(hw, QRX_CTRL(pf_q));
	2260	+ if (rx_reg & QRX_CTRL_QENA_STAT_M)
	2261	+ return true;
	2262	+ }
	2263	+
	2264	+ return false;
	2265	+}
	2266	+
2242	2267	/**
2243	2268	* ice_vsi_is_vlan_pruning_ena - check if VLAN pruning is enabled or not
2244	2269	* @vsi: VSI to check whether or not VLAN pruning is enabled.

drivers/net/ethernet/intel/ice/ice_lib.h+1−0

@@ -129,4 +129,5 @@ u16 ice_vsi_num_non_zero_vlans(struct ice_vsi *vsi); · 128 unmodified lines
129	129	bool ice_is_feature_supported(struct ice_pf *pf, enum ice_feature f);
130	130	void ice_clear_feature_support(struct ice_pf *pf, enum ice_feature f);
131	131	void ice_init_feature_support(struct ice_pf *pf);
	132	+bool ice_vsi_is_rx_queue_active(struct ice_vsi *vsi);
132	133	#endif /* !_ICE_LIB_H_ */

drivers/net/ethernet/intel/ice/ice_vf_lib.c+4−1

@@ -576,7 +576,10 @@ int ice_reset_vf(struct ice_vf *vf, u32 flags) · 575 unmodified lines
576	576	return -EINVAL;
577	577	}
578	578	ice_vsi_stop_lan_tx_rings(vsi, ICE_NO_RESET, vf->vf_id);
579		− ice_vsi_stop_all_rx_rings(vsi);
	579	+
	580	+ if (ice_vsi_is_rx_queue_active(vsi))
	581	+ ice_vsi_stop_all_rx_rings(vsi);
	582	+
580	583	dev_dbg(dev, "VF is already disabled, there is no need for resetting it, telling VM, all is fine %d\n",
581	584	vf->vf_id);
582	585	return 0;

drivers/net/ethernet/marvell/mv643xx_eth.c+1−0

@@ -2481,6 +2481,7 @@ out_free: · 2480 unmodified lines
2481	2481	for (i = 0; i < mp->rxq_count; i++)
2482	2482	rxq_deinit(mp->rxq + i);
2483	2483	out:
	2484	+ napi_disable(&mp->napi);
2484	2485	free_irq(dev->irq, dev);
2485	2486
2486	2487	return err;

drivers/net/ethernet/marvell/octeontx2/Kconfig+2−0

@@ -32,10 +32,12 @@ config OCTEONTX2_PF · 31 unmodified lines
32	32	tristate "Marvell OcteonTX2 NIC Physical Function driver"
33	33	select OCTEONTX2_MBOX
34	34	select NET_DEVLINK
	35	+ depends on MACSEC \|\| !MACSEC
35	36	depends on (64BIT && COMPILE_TEST) \|\| ARM64
36	37	select DIMLIB
37	38	depends on PCI
38	39	depends on PTP_1588_CLOCK_OPTIONAL
	40	+ depends on MACSEC \|\| !MACSEC
39	41	help
40	42	This driver supports Marvell's OcteonTX2 NIC physical function.
41	43

drivers/net/ethernet/marvell/octeontx2/nic/otx2_common.c+1−0

@@ -898,6 +898,7 @@ static int otx2_sq_init(struct otx2_nic *pfvf, u16 qidx, u16 sqb_aura) · 897 unmodified lines
898	898	}
899	899
900	900	sq->head = 0;
	901	+ sq->cons_head = 0;
901	902	sq->sqe_per_sqb = (pfvf->hw.sqb_size / sq->sqe_size) - 1;
902	903	sq->num_sqbs = (qset->sqe_cnt + sq->sqe_per_sqb) / sq->sqe_per_sqb;
903	904	/* Set SQE threshold to 10% of total SQEs */

drivers/net/ethernet/marvell/octeontx2/nic/otx2_pf.c+105−30

@@ -15,6 +15,7 @@ · 14 unmodified lines
15	15	#include <net/ip.h>
16	16	#include <linux/bpf.h>
17	17	#include <linux/bpf_trace.h>
	18	+#include <linux/bitfield.h>
18	19
19	20	#include "otx2_reg.h"
20	21	#include "otx2_common.h"
@@ -1171,6 +1172,59 @@ int otx2_set_real_num_queues(struct net_device *netdev, · 1150 unmodified lines
1171	1172	}
1172	1173	EXPORT_SYMBOL(otx2_set_real_num_queues);
1173	1174
	1175	+static char *nix_sqoperr_e_str[NIX_SQOPERR_MAX] = {
	1176	+ "NIX_SQOPERR_OOR",
	1177	+ "NIX_SQOPERR_CTX_FAULT",
	1178	+ "NIX_SQOPERR_CTX_POISON",
	1179	+ "NIX_SQOPERR_DISABLED",
	1180	+ "NIX_SQOPERR_SIZE_ERR",
	1181	+ "NIX_SQOPERR_OFLOW",
	1182	+ "NIX_SQOPERR_SQB_NULL",
	1183	+ "NIX_SQOPERR_SQB_FAULT",
	1184	+ "NIX_SQOPERR_SQE_SZ_ZERO",
	1185	+};
	1186	+
	1187	+static char *nix_mnqerr_e_str[NIX_MNQERR_MAX] = {
	1188	+ "NIX_MNQERR_SQ_CTX_FAULT",
	1189	+ "NIX_MNQERR_SQ_CTX_POISON",
	1190	+ "NIX_MNQERR_SQB_FAULT",
	1191	+ "NIX_MNQERR_SQB_POISON",
	1192	+ "NIX_MNQERR_TOTAL_ERR",
	1193	+ "NIX_MNQERR_LSO_ERR",
	1194	+ "NIX_MNQERR_CQ_QUERY_ERR",
	1195	+ "NIX_MNQERR_MAX_SQE_SIZE_ERR",
	1196	+ "NIX_MNQERR_MAXLEN_ERR",
	1197	+ "NIX_MNQERR_SQE_SIZEM1_ZERO",
	1198	+};
	1199	+
	1200	+static char *nix_snd_status_e_str[NIX_SND_STATUS_MAX] = {
	1201	+ "NIX_SND_STATUS_GOOD",
	1202	+ "NIX_SND_STATUS_SQ_CTX_FAULT",
	1203	+ "NIX_SND_STATUS_SQ_CTX_POISON",
	1204	+ "NIX_SND_STATUS_SQB_FAULT",
	1205	+ "NIX_SND_STATUS_SQB_POISON",
	1206	+ "NIX_SND_STATUS_HDR_ERR",
	1207	+ "NIX_SND_STATUS_EXT_ERR",
	1208	+ "NIX_SND_STATUS_JUMP_FAULT",
	1209	+ "NIX_SND_STATUS_JUMP_POISON",
	1210	+ "NIX_SND_STATUS_CRC_ERR",
	1211	+ "NIX_SND_STATUS_IMM_ERR",
	1212	+ "NIX_SND_STATUS_SG_ERR",
	1213	+ "NIX_SND_STATUS_MEM_ERR",
	1214	+ "NIX_SND_STATUS_INVALID_SUBDC",
	1215	+ "NIX_SND_STATUS_SUBDC_ORDER_ERR",
	1216	+ "NIX_SND_STATUS_DATA_FAULT",
	1217	+ "NIX_SND_STATUS_DATA_POISON",
	1218	+ "NIX_SND_STATUS_NPC_DROP_ACTION",
	1219	+ "NIX_SND_STATUS_LOCK_VIOL",
	1220	+ "NIX_SND_STATUS_NPC_UCAST_CHAN_ERR",
	1221	+ "NIX_SND_STATUS_NPC_MCAST_CHAN_ERR",
	1222	+ "NIX_SND_STATUS_NPC_MCAST_ABORT",
	1223	+ "NIX_SND_STATUS_NPC_VTAG_PTR_ERR",
	1224	+ "NIX_SND_STATUS_NPC_VTAG_SIZE_ERR",
	1225	+ "NIX_SND_STATUS_SEND_STATS_ERR",
	1226	+};
	1227	+
1174	1228	static irqreturn_t otx2_q_intr_handler(int irq, void *data)
1175	1229	{
1176	1230	struct otx2_nic *pf = data;
@@ -1204,46 +1258,67 @@ static irqreturn_t otx2_q_intr_handler(int irq, void *data) · 27 unmodified lines
1204	1258
1205	1259	/* SQ */
1206	1260	for (qidx = 0; qidx < pf->hw.tot_tx_queues; qidx++) {
	1261	+ u64 sq_op_err_dbg, mnq_err_dbg, snd_err_dbg;
	1262	+ u8 sq_op_err_code, mnq_err_code, snd_err_code;
	1263	+
	1264	+ /* Below debug registers captures first errors corresponding to
	1265	+ * those registers. We don't have to check against SQ qid as
	1266	+ * these are fatal errors.
	1267	+ */
	1268	+
1207	1269	ptr = otx2_get_regaddr(pf, NIX_LF_SQ_OP_INT);
1208	1270	val = otx2_atomic64_add((qidx << 44), ptr);
1209	1271	otx2_write64(pf, NIX_LF_SQ_OP_INT, (qidx << 44) \|
1210	1272	(val & NIX_SQINT_BITS));
1211	1273
1212		− if (!(val & (NIX_SQINT_BITS \| BIT_ULL(42))))
1213		− continue;
1214		−
1215	1274	if (val & BIT_ULL(42)) {
1216	1275	netdev_err(pf->netdev, "SQ%lld: error reading NIX_LF_SQ_OP_INT, NIX_LF_ERR_INT 0x%llx\n",
1217	1276	qidx, otx2_read64(pf, NIX_LF_ERR_INT));
1218		− } else {
1219		− if (val & BIT_ULL(NIX_SQINT_LMT_ERR)) {
1220		− netdev_err(pf->netdev, "SQ%lld: LMT store error NIX_LF_SQ_OP_ERR_DBG:0x%llx",
1221		− qidx,
1222		− otx2_read64(pf,
1223		− NIX_LF_SQ_OP_ERR_DBG));
1224		− otx2_write64(pf, NIX_LF_SQ_OP_ERR_DBG,
1225		− BIT_ULL(44));
1226		− }
1227		− if (val & BIT_ULL(NIX_SQINT_MNQ_ERR)) {
1228		− netdev_err(pf->netdev, "SQ%lld: Meta-descriptor enqueue error NIX_LF_MNQ_ERR_DGB:0x%llx\n",
1229		− qidx,
1230		− otx2_read64(pf, NIX_LF_MNQ_ERR_DBG));
1231		− otx2_write64(pf, NIX_LF_MNQ_ERR_DBG,
1232		− BIT_ULL(44));
1233		− }
1234		− if (val & BIT_ULL(NIX_SQINT_SEND_ERR)) {
1235		− netdev_err(pf->netdev, "SQ%lld: Send error, NIX_LF_SEND_ERR_DBG 0x%llx",
1236		− qidx,
1237		− otx2_read64(pf,
1238		− NIX_LF_SEND_ERR_DBG));
1239		− otx2_write64(pf, NIX_LF_SEND_ERR_DBG,
1240		− BIT_ULL(44));
1241		− }
1242		− if (val & BIT_ULL(NIX_SQINT_SQB_ALLOC_FAIL))
1243		− netdev_err(pf->netdev, "SQ%lld: SQB allocation failed",
1244		− qidx);
	1277	+ goto done;
1245	1278	}
1246	1279
	1280	+ sq_op_err_dbg = otx2_read64(pf, NIX_LF_SQ_OP_ERR_DBG);
	1281	+ if (!(sq_op_err_dbg & BIT(44)))
	1282	+ goto chk_mnq_err_dbg;
	1283	+
	1284	+ sq_op_err_code = FIELD_GET(GENMASK(7, 0), sq_op_err_dbg);
	1285	+ netdev_err(pf->netdev, "SQ%lld: NIX_LF_SQ_OP_ERR_DBG(%llx) err=%s\n",
	1286	+ qidx, sq_op_err_dbg, nix_sqoperr_e_str[sq_op_err_code]);
	1287	+
	1288	+ otx2_write64(pf, NIX_LF_SQ_OP_ERR_DBG, BIT_ULL(44));
	1289	+
	1290	+ if (sq_op_err_code == NIX_SQOPERR_SQB_NULL)
	1291	+ goto chk_mnq_err_dbg;
	1292	+
	1293	+ /* Err is not NIX_SQOPERR_SQB_NULL, call aq function to read SQ structure.
	1294	+ * TODO: But we are in irq context. How to call mbox functions which does sleep
	1295	+ */
	1296	+
	1297	+chk_mnq_err_dbg:
	1298	+ mnq_err_dbg = otx2_read64(pf, NIX_LF_MNQ_ERR_DBG);
	1299	+ if (!(mnq_err_dbg & BIT(44)))
	1300	+ goto chk_snd_err_dbg;
	1301	+
	1302	+ mnq_err_code = FIELD_GET(GENMASK(7, 0), mnq_err_dbg);
	1303	+ netdev_err(pf->netdev, "SQ%lld: NIX_LF_MNQ_ERR_DBG(%llx) err=%s\n",
	1304	+ qidx, mnq_err_dbg, nix_mnqerr_e_str[mnq_err_code]);
	1305	+ otx2_write64(pf, NIX_LF_MNQ_ERR_DBG, BIT_ULL(44));
	1306	+
	1307	+chk_snd_err_dbg:
	1308	+ snd_err_dbg = otx2_read64(pf, NIX_LF_SEND_ERR_DBG);
	1309	+ if (snd_err_dbg & BIT(44)) {
	1310	+ snd_err_code = FIELD_GET(GENMASK(7, 0), snd_err_dbg);
	1311	+ netdev_err(pf->netdev, "SQ%lld: NIX_LF_SND_ERR_DBG:0x%llx err=%s\n",
	1312	+ qidx, snd_err_dbg, nix_snd_status_e_str[snd_err_code]);
	1313	+ otx2_write64(pf, NIX_LF_SEND_ERR_DBG, BIT_ULL(44));
	1314	+ }
	1315	+
	1316	+done:
	1317	+ /* Print values and reset */
	1318	+ if (val & BIT_ULL(NIX_SQINT_SQB_ALLOC_FAIL))
	1319	+ netdev_err(pf->netdev, "SQ%lld: SQB allocation failed",
	1320	+ qidx);
	1321	+
1247	1322	schedule_work(&pf->reset_task);
1248	1323	}
1249	1324

drivers/net/ethernet/marvell/octeontx2/nic/otx2_struct.h+57−0

@@ -281,4 +281,61 @@ enum nix_sqint_e { · 280 unmodified lines
281	281	BIT_ULL(NIX_SQINT_SEND_ERR) \| \
282	282	BIT_ULL(NIX_SQINT_SQB_ALLOC_FAIL))
283	283
	284	+enum nix_sqoperr_e {
	285	+ NIX_SQOPERR_OOR = 0,
	286	+ NIX_SQOPERR_CTX_FAULT = 1,
	287	+ NIX_SQOPERR_CTX_POISON = 2,
	288	+ NIX_SQOPERR_DISABLED = 3,
	289	+ NIX_SQOPERR_SIZE_ERR = 4,
	290	+ NIX_SQOPERR_OFLOW = 5,
	291	+ NIX_SQOPERR_SQB_NULL = 6,
	292	+ NIX_SQOPERR_SQB_FAULT = 7,
	293	+ NIX_SQOPERR_SQE_SZ_ZERO = 8,
	294	+ NIX_SQOPERR_MAX,
	295	+};
	296	+
	297	+enum nix_mnqerr_e {
	298	+ NIX_MNQERR_SQ_CTX_FAULT = 0,
	299	+ NIX_MNQERR_SQ_CTX_POISON = 1,
	300	+ NIX_MNQERR_SQB_FAULT = 2,
	301	+ NIX_MNQERR_SQB_POISON = 3,
	302	+ NIX_MNQERR_TOTAL_ERR = 4,
	303	+ NIX_MNQERR_LSO_ERR = 5,
	304	+ NIX_MNQERR_CQ_QUERY_ERR = 6,
	305	+ NIX_MNQERR_MAX_SQE_SIZE_ERR = 7,
	306	+ NIX_MNQERR_MAXLEN_ERR = 8,
	307	+ NIX_MNQERR_SQE_SIZEM1_ZERO = 9,
	308	+ NIX_MNQERR_MAX,
	309	+};
	310	+
	311	+enum nix_snd_status_e {
	312	+ NIX_SND_STATUS_GOOD = 0x0,
	313	+ NIX_SND_STATUS_SQ_CTX_FAULT = 0x1,
	314	+ NIX_SND_STATUS_SQ_CTX_POISON = 0x2,
	315	+ NIX_SND_STATUS_SQB_FAULT = 0x3,
	316	+ NIX_SND_STATUS_SQB_POISON = 0x4,
	317	+ NIX_SND_STATUS_HDR_ERR = 0x5,
	318	+ NIX_SND_STATUS_EXT_ERR = 0x6,
	319	+ NIX_SND_STATUS_JUMP_FAULT = 0x7,
	320	+ NIX_SND_STATUS_JUMP_POISON = 0x8,
	321	+ NIX_SND_STATUS_CRC_ERR = 0x9,
	322	+ NIX_SND_STATUS_IMM_ERR = 0x10,
	323	+ NIX_SND_STATUS_SG_ERR = 0x11,
	324	+ NIX_SND_STATUS_MEM_ERR = 0x12,
	325	+ NIX_SND_STATUS_INVALID_SUBDC = 0x13,
	326	+ NIX_SND_STATUS_SUBDC_ORDER_ERR = 0x14,
	327	+ NIX_SND_STATUS_DATA_FAULT = 0x15,
	328	+ NIX_SND_STATUS_DATA_POISON = 0x16,
	329	+ NIX_SND_STATUS_NPC_DROP_ACTION = 0x17,
	330	+ NIX_SND_STATUS_LOCK_VIOL = 0x18,
	331	+ NIX_SND_STATUS_NPC_UCAST_CHAN_ERR = 0x19,
	332	+ NIX_SND_STATUS_NPC_MCAST_CHAN_ERR = 0x20,
	333	+ NIX_SND_STATUS_NPC_MCAST_ABORT = 0x21,
	334	+ NIX_SND_STATUS_NPC_VTAG_PTR_ERR = 0x22,
	335	+ NIX_SND_STATUS_NPC_VTAG_SIZE_ERR = 0x23,
	336	+ NIX_SND_STATUS_SEND_MEM_FAULT = 0x24,
	337	+ NIX_SND_STATUS_SEND_STATS_ERR = 0x25,
	338	+ NIX_SND_STATUS_MAX,
	339	+};
	340	+
284	341	#endif /* OTX2_STRUCT_H */

drivers/net/ethernet/marvell/octeontx2/nic/otx2_txrx.c+19−13

@@ -441,6 +441,7 @@ static int otx2_tx_napi_handler(struct otx2_nic *pfvf, · 440 unmodified lines
441	441	struct otx2_cq_queue *cq, int budget)
442	442	{
443	443	int tx_pkts = 0, tx_bytes = 0, qidx;
	444	+ struct otx2_snd_queue *sq;
444	445	struct nix_cqe_tx_s *cqe;
445	446	int processed_cqe = 0;
446	447
@@ -451,6 +452,9 @@ static int otx2_tx_napi_handler(struct otx2_nic *pfvf, · 4 unmodified lines
451	452	return 0;
452	453
453	454	process_cqe:
	455	+ qidx = cq->cq_idx - pfvf->hw.rx_queues;
	456	+ sq = &pfvf->qset.sq[qidx];
	457	+
454	458	while (likely(processed_cqe < budget) && cq->pend_cqe) {
455	459	cqe = (struct nix_cqe_tx_s *)otx2_get_next_cqe(cq);
456	460	if (unlikely(!cqe)) {
@@ -458,18 +462,20 @@ process_cqe: · 1 unmodified line
458	462	return 0;
459	463	break;
460	464	}
	465	+
461	466	if (cq->cq_type == CQ_XDP) {
462		− qidx = cq->cq_idx - pfvf->hw.rx_queues;
463		− otx2_xdp_snd_pkt_handler(pfvf, &pfvf->qset.sq[qidx],
464		− cqe);
	467	+ otx2_xdp_snd_pkt_handler(pfvf, sq, cqe);
465	468	} else {
466		− otx2_snd_pkt_handler(pfvf, cq,
467		− &pfvf->qset.sq[cq->cint_idx],
468		− cqe, budget, &tx_pkts, &tx_bytes);
	469	+ otx2_snd_pkt_handler(pfvf, cq, sq, cqe, budget,
	470	+ &tx_pkts, &tx_bytes);
469	471	}
	472	+
470	473	cqe->hdr.cqe_type = NIX_XQE_TYPE_INVALID;
471	474	processed_cqe++;
472	475	cq->pend_cqe--;
	476	+
	477	+ sq->cons_head++;
	478	+ sq->cons_head &= (sq->sqe_cnt - 1);
473	479	}
474	480
475	481	/* Free CQEs to HW */
@@ -1072,17 +1078,17 @@ bool otx2_sq_append_skb(struct net_device netdev, struct otx2_snd_queue sq, · 596 unmodified lines
1072	1078	{
1073	1079	struct netdev_queue *txq = netdev_get_tx_queue(netdev, qidx);
1074	1080	struct otx2_nic *pfvf = netdev_priv(netdev);
1075		− int offset, num_segs, free_sqe;
	1081	+ int offset, num_segs, free_desc;
1076	1082	struct nix_sqe_hdr_s *sqe_hdr;
1077	1083
1078		− /* Check if there is room for new SQE.
1079		− * 'Num of SQBs freed to SQ's pool - SQ's Aura count'
1080		− * will give free SQE count.
	1084	+ /* Check if there is enough room between producer
	1085	+ * and consumer index.
1081	1086	*/
1082		− free_sqe = (sq->num_sqbs - sq->aura_fc_addr) sq->sqe_per_sqb;
	1087	+ free_desc = (sq->cons_head - sq->head - 1 + sq->sqe_cnt) & (sq->sqe_cnt - 1);
	1088	+ if (free_desc < sq->sqe_thresh)
	1089	+ return false;
1083	1090
1084		− if (free_sqe < sq->sqe_thresh \|\|
1085		− free_sqe < otx2_get_sqe_count(pfvf, skb))
	1091	+ if (free_desc < otx2_get_sqe_count(pfvf, skb))
1086	1092	return false;
1087	1093
1088	1094	num_segs = skb_shinfo(skb)->nr_frags + 1;

drivers/net/ethernet/marvell/octeontx2/nic/otx2_txrx.h+1−0

@@ -79,6 +79,7 @@ struct sg_list { · 78 unmodified lines
79	79	struct otx2_snd_queue {
80	80	u8 aura_id;
81	81	u16 head;
	82	+ u16 cons_head;
82	83	u16 sqe_size;
83	84	u32 sqe_cnt;
84	85	u16 num_sqbs;

drivers/net/ethernet/marvell/prestera/prestera_rxtx.c+6−1

@@ -776,6 +776,7 @@ tx_done: · 775 unmodified lines
776	776	int prestera_rxtx_switch_init(struct prestera_switch *sw)
777	777	{
778	778	struct prestera_rxtx *rxtx;
	779	+ int err;
779	780
780	781	rxtx = kzalloc(sizeof(*rxtx), GFP_KERNEL);
781	782	if (!rxtx)
@@ -783,7 +784,11 @@ int prestera_rxtx_switch_init(struct prestera_switch *sw) · 1 unmodified line
783	784
784	785	sw->rxtx = rxtx;
785	786
786		− return prestera_sdma_switch_init(sw);
	787	+ err = prestera_sdma_switch_init(sw);
	788	+ if (err)
	789	+ kfree(rxtx);
	790	+
	791	+ return err;
787	792	}
788	793
789	794	void prestera_rxtx_switch_fini(struct prestera_switch *sw)

drivers/net/ethernet/mediatek/mtk_star_emac.c+2−0

@@ -1026,6 +1026,8 @@ static int mtk_star_enable(struct net_device *ndev) · 1025 unmodified lines
1026	1026	return 0;
1027	1027
1028	1028	err_free_irq:
	1029	+ napi_disable(&priv->rx_napi);
	1030	+ napi_disable(&priv->tx_napi);
1029	1031	free_irq(ndev->irq, ndev);
1030	1032	err_free_skbs:
1031	1033	mtk_star_free_rx_skbs(priv);

drivers/net/ethernet/mellanox/mlx5/core/cmd.c+8−3

@@ -1770,12 +1770,17 @@ void mlx5_cmd_flush(struct mlx5_core_dev *dev) · 1769 unmodified lines
1770	1770	struct mlx5_cmd *cmd = &dev->cmd;
1771	1771	int i;
1772	1772
1773		− for (i = 0; i < cmd->max_reg_cmds; i++)
1774		− while (down_trylock(&cmd->sem))
	1773	+ for (i = 0; i < cmd->max_reg_cmds; i++) {
	1774	+ while (down_trylock(&cmd->sem)) {
1775	1775	mlx5_cmd_trigger_completions(dev);
	1776	+ cond_resched();
	1777	+ }
	1778	+ }
1776	1779
1777		− while (down_trylock(&cmd->pages_sem))
	1780	+ while (down_trylock(&cmd->pages_sem)) {
1778	1781	mlx5_cmd_trigger_completions(dev);
	1782	+ cond_resched();
	1783	+ }
1779	1784
1780	1785	/* Unlock cmdif */
1781	1786	up(&cmd->pages_sem);

drivers/net/ethernet/mellanox/mlx5/core/en/rep/bridge.c+31−0

@@ -164,6 +164,36 @@ static int mlx5_esw_bridge_port_changeupper(struct notifier_block nb, void ptr · 163 unmodified lines
164	164	return err;
165	165	}
166	166
	167	+static int
	168	+mlx5_esw_bridge_changeupper_validate_netdev(void *ptr)
	169	+{
	170	+ struct net_device *dev = netdev_notifier_info_to_dev(ptr);
	171	+ struct netdev_notifier_changeupper_info *info = ptr;
	172	+ struct net_device *upper = info->upper_dev;
	173	+ struct net_device *lower;
	174	+ struct list_head *iter;
	175	+
	176	+ if (!netif_is_bridge_master(upper) \|\| !netif_is_lag_master(dev))
	177	+ return 0;
	178	+
	179	+ netdev_for_each_lower_dev(dev, lower, iter) {
	180	+ struct mlx5_core_dev *mdev;
	181	+ struct mlx5e_priv *priv;
	182	+
	183	+ if (!mlx5e_eswitch_rep(lower))
	184	+ continue;
	185	+
	186	+ priv = netdev_priv(lower);
	187	+ mdev = priv->mdev;
	188	+ if (!mlx5_lag_is_active(mdev))
	189	+ return -EAGAIN;
	190	+ if (!mlx5_lag_is_shared_fdb(mdev))
	191	+ return -EOPNOTSUPP;
	192	+ }
	193	+
	194	+ return 0;
	195	+}
	196	+
167	197	static int mlx5_esw_bridge_switchdev_port_event(struct notifier_block *nb,
168	198	unsigned long event, void *ptr)
169	199	{
@@ -171,6 +201,7 @@ static int mlx5_esw_bridge_switchdev_port_event(struct notifier_block *nb, · 1 unmodified line
171	201
172	202	switch (event) {
173	203	case NETDEV_PRECHANGEUPPER:
	204	+ err = mlx5_esw_bridge_changeupper_validate_netdev(ptr);
174	205	break;
175	206
176	207	case NETDEV_CHANGEUPPER:

drivers/net/ethernet/mellanox/mlx5/core/en/tc/act/act.c+32−60

@@ -6,70 +6,42 @@ · 5 unmodified lines
6	6	#include "en/tc_priv.h"
7	7	#include "mlx5_core.h"
8	8
9		−/* Must be aligned with enum flow_action_id. */
10	9	static struct mlx5e_tc_act *tc_acts_fdb[NUM_FLOW_ACTIONS] = {
11		− &mlx5e_tc_act_accept,
12		− &mlx5e_tc_act_drop,
13		− &mlx5e_tc_act_trap,
14		− &mlx5e_tc_act_goto,
15		− &mlx5e_tc_act_mirred,
16		− &mlx5e_tc_act_mirred,
17		− &mlx5e_tc_act_redirect_ingress,
18		− NULL, /* FLOW_ACTION_MIRRED_INGRESS, */
19		− &mlx5e_tc_act_vlan,
20		− &mlx5e_tc_act_vlan,
21		− &mlx5e_tc_act_vlan_mangle,
22		− &mlx5e_tc_act_tun_encap,
23		− &mlx5e_tc_act_tun_decap,
24		− &mlx5e_tc_act_pedit,
25		− &mlx5e_tc_act_pedit,
26		− &mlx5e_tc_act_csum,
27		− NULL, /* FLOW_ACTION_MARK, */
28		− &mlx5e_tc_act_ptype,
29		− NULL, /* FLOW_ACTION_PRIORITY, */
30		− NULL, /* FLOW_ACTION_WAKE, */
31		− NULL, /* FLOW_ACTION_QUEUE, */
32		− &mlx5e_tc_act_sample,
33		− &mlx5e_tc_act_police,
34		− &mlx5e_tc_act_ct,
35		− NULL, /* FLOW_ACTION_CT_METADATA, */
36		− &mlx5e_tc_act_mpls_push,
37		− &mlx5e_tc_act_mpls_pop,
38		− NULL, /* FLOW_ACTION_MPLS_MANGLE, */
39		− NULL, /* FLOW_ACTION_GATE, */
40		− NULL, /* FLOW_ACTION_PPPOE_PUSH, */
41		− NULL, /* FLOW_ACTION_JUMP, */
42		− NULL, /* FLOW_ACTION_PIPE, */
43		− &mlx5e_tc_act_vlan,
44		− &mlx5e_tc_act_vlan,
	10	+ [FLOW_ACTION_ACCEPT] = &mlx5e_tc_act_accept,
	11	+ [FLOW_ACTION_DROP] = &mlx5e_tc_act_drop,
	12	+ [FLOW_ACTION_TRAP] = &mlx5e_tc_act_trap,
	13	+ [FLOW_ACTION_GOTO] = &mlx5e_tc_act_goto,
	14	+ [FLOW_ACTION_REDIRECT] = &mlx5e_tc_act_mirred,
	15	+ [FLOW_ACTION_MIRRED] = &mlx5e_tc_act_mirred,
	16	+ [FLOW_ACTION_REDIRECT_INGRESS] = &mlx5e_tc_act_redirect_ingress,
	17	+ [FLOW_ACTION_VLAN_PUSH] = &mlx5e_tc_act_vlan,
	18	+ [FLOW_ACTION_VLAN_POP] = &mlx5e_tc_act_vlan,
	19	+ [FLOW_ACTION_VLAN_MANGLE] = &mlx5e_tc_act_vlan_mangle,
	20	+ [FLOW_ACTION_TUNNEL_ENCAP] = &mlx5e_tc_act_tun_encap,
	21	+ [FLOW_ACTION_TUNNEL_DECAP] = &mlx5e_tc_act_tun_decap,
	22	+ [FLOW_ACTION_MANGLE] = &mlx5e_tc_act_pedit,
	23	+ [FLOW_ACTION_ADD] = &mlx5e_tc_act_pedit,
	24	+ [FLOW_ACTION_CSUM] = &mlx5e_tc_act_csum,
	25	+ [FLOW_ACTION_PTYPE] = &mlx5e_tc_act_ptype,
	26	+ [FLOW_ACTION_SAMPLE] = &mlx5e_tc_act_sample,
	27	+ [FLOW_ACTION_POLICE] = &mlx5e_tc_act_police,
	28	+ [FLOW_ACTION_CT] = &mlx5e_tc_act_ct,
	29	+ [FLOW_ACTION_MPLS_PUSH] = &mlx5e_tc_act_mpls_push,
	30	+ [FLOW_ACTION_MPLS_POP] = &mlx5e_tc_act_mpls_pop,
	31	+ [FLOW_ACTION_VLAN_PUSH_ETH] = &mlx5e_tc_act_vlan,
	32	+ [FLOW_ACTION_VLAN_POP_ETH] = &mlx5e_tc_act_vlan,
45	33	};
46	34
47		−/* Must be aligned with enum flow_action_id. */
48	35	static struct mlx5e_tc_act *tc_acts_nic[NUM_FLOW_ACTIONS] = {
49		− &mlx5e_tc_act_accept,
50		− &mlx5e_tc_act_drop,
51		− NULL, /* FLOW_ACTION_TRAP, */
52		− &mlx5e_tc_act_goto,
53		− &mlx5e_tc_act_mirred_nic,
54		− NULL, /* FLOW_ACTION_MIRRED, */
55		− NULL, /* FLOW_ACTION_REDIRECT_INGRESS, */
56		− NULL, /* FLOW_ACTION_MIRRED_INGRESS, */
57		− NULL, /* FLOW_ACTION_VLAN_PUSH, */
58		− NULL, /* FLOW_ACTION_VLAN_POP, */
59		− NULL, /* FLOW_ACTION_VLAN_MANGLE, */
60		− NULL, /* FLOW_ACTION_TUNNEL_ENCAP, */
61		− NULL, /* FLOW_ACTION_TUNNEL_DECAP, */
62		− &mlx5e_tc_act_pedit,
63		− &mlx5e_tc_act_pedit,
64		− &mlx5e_tc_act_csum,
65		− &mlx5e_tc_act_mark,
66		− NULL, /* FLOW_ACTION_PTYPE, */
67		− NULL, /* FLOW_ACTION_PRIORITY, */
68		− NULL, /* FLOW_ACTION_WAKE, */
69		− NULL, /* FLOW_ACTION_QUEUE, */
70		− NULL, /* FLOW_ACTION_SAMPLE, */
71		− NULL, /* FLOW_ACTION_POLICE, */
72		− &mlx5e_tc_act_ct,
	36	+ [FLOW_ACTION_ACCEPT] = &mlx5e_tc_act_accept,
	37	+ [FLOW_ACTION_DROP] = &mlx5e_tc_act_drop,
	38	+ [FLOW_ACTION_GOTO] = &mlx5e_tc_act_goto,
	39	+ [FLOW_ACTION_REDIRECT] = &mlx5e_tc_act_mirred_nic,
	40	+ [FLOW_ACTION_MANGLE] = &mlx5e_tc_act_pedit,
	41	+ [FLOW_ACTION_ADD] = &mlx5e_tc_act_pedit,
	42	+ [FLOW_ACTION_CSUM] = &mlx5e_tc_act_csum,
	43	+ [FLOW_ACTION_MARK] = &mlx5e_tc_act_mark,
	44	+ [FLOW_ACTION_CT] = &mlx5e_tc_act_ct,
73	45	};
74	46
75	47	/**

drivers/net/ethernet/mellanox/mlx5/core/en/txrx.h+23−1

@@ -11,6 +11,27 @@ · 10 unmodified lines
11	11
12	12	#define INL_HDR_START_SZ (sizeof(((struct mlx5_wqe_eth_seg *)NULL)->inline_hdr.start))
13	13
	14	+/* IPSEC inline data includes:
	15	+ * 1. ESP trailer: up to 255 bytes of padding, 1 byte for pad length, 1 byte for
	16	+ * next header.
	17	+ * 2. ESP authentication data: 16 bytes for ICV.
	18	+ */
	19	+#define MLX5E_MAX_TX_IPSEC_DS DIV_ROUND_UP(sizeof(struct mlx5_wqe_inline_seg) + \
	20	+ 255 + 1 + 1 + 16, MLX5_SEND_WQE_DS)
	21	+
	22	+/* 366 should be big enough to cover all L2, L3 and L4 headers with possible
	23	+ * encapsulations.
	24	+ */
	25	+#define MLX5E_MAX_TX_INLINE_DS DIV_ROUND_UP(366 - INL_HDR_START_SZ + VLAN_HLEN, \
	26	+ MLX5_SEND_WQE_DS)
	27	+
	28	+/* Sync the calculation with mlx5e_sq_calc_wqe_attr. */
	29	+#define MLX5E_MAX_TX_WQEBBS DIV_ROUND_UP(MLX5E_TX_WQE_EMPTY_DS_COUNT + \
	30	+ MLX5E_MAX_TX_INLINE_DS + \
	31	+ MLX5E_MAX_TX_IPSEC_DS + \
	32	+ MAX_SKB_FRAGS + 1, \
	33	+ MLX5_SEND_WQEBB_NUM_DS)
	34	+
14	35	#define MLX5E_RX_ERR_CQE(cqe) (get_cqe_opcode(cqe) != MLX5_CQE_RESP_SEND)
15	36
16	37	static inline
@@ -424,6 +445,8 @@ mlx5e_set_eseg_swp(struct sk_buff skb, struct mlx5_wqe_eth_seg eseg, · 407 unmodified lines
424	445
425	446	static inline u16 mlx5e_stop_room_for_wqe(struct mlx5_core_dev *mdev, u16 wqe_size)
426	447	{
	448	+ WARN_ON_ONCE(PAGE_SIZE / MLX5_SEND_WQE_BB < mlx5e_get_max_sq_wqebbs(mdev));
	449	+
427	450	/* A WQE must not cross the page boundary, hence two conditions:
428	451	* 1. Its size must not exceed the page size.
429	452	* 2. If the WQE size is X, and the space remaining in a page is less
@@ -436,7 +459,6 @@ static inline u16 mlx5e_stop_room_for_wqe(struct mlx5_core_dev *mdev, u16 wqe_si · 6 unmodified lines
436	459	"wqe_size %u is greater than max SQ WQEBBs %u",
437	460	wqe_size, mlx5e_get_max_sq_wqebbs(mdev));
438	461
439		−
440	462	return MLX5E_STOP_ROOM(wqe_size);
441	463	}
442	464

drivers/net/ethernet/mellanox/mlx5/core/en/xdp.c+2−2

@@ -117,7 +117,7 @@ mlx5e_xmit_xdp_buff(struct mlx5e_xdpsq sq, struct mlx5e_rq rq, · 116 unmodified lines
117	117	xdpi.page.rq = rq;
118	118
119	119	dma_addr = page_pool_get_dma_addr(page) + (xdpf->data - (void *)xdpf);
120		− dma_sync_single_for_device(sq->pdev, dma_addr, xdptxd.len, DMA_TO_DEVICE);
	120	+ dma_sync_single_for_device(sq->pdev, dma_addr, xdptxd.len, DMA_BIDIRECTIONAL);
121	121
122	122	if (unlikely(xdp_frame_has_frags(xdpf))) {
123	123	sinfo = xdp_get_shared_info_from_frame(xdpf);
@@ -131,7 +131,7 @@ mlx5e_xmit_xdp_buff(struct mlx5e_xdpsq sq, struct mlx5e_rq rq, · 7 unmodified lines
131	131	skb_frag_off(frag);
132	132	len = skb_frag_size(frag);
133	133	dma_sync_single_for_device(sq->pdev, addr, len,
134		− DMA_TO_DEVICE);
	134	+ DMA_BIDIRECTIONAL);
135	135	}
136	136	}
137	137

drivers/net/ethernet/mellanox/mlx5/core/en_main.c+7−0

@@ -5694,6 +5694,13 @@ int mlx5e_attach_netdev(struct mlx5e_priv *priv) · 5693 unmodified lines
5694	5694	mlx5e_fs_set_state_destroy(priv->fs,
5695	5695	!test_bit(MLX5E_STATE_DESTROYING, &priv->state));
5696	5696
	5697	+ /* Validate the max_wqe_size_sq capability. */
	5698	+ if (WARN_ON_ONCE(mlx5e_get_max_sq_wqebbs(priv->mdev) < MLX5E_MAX_TX_WQEBBS)) {
	5699	+ mlx5_core_warn(priv->mdev, "MLX5E: Max SQ WQEBBs firmware capability: %u, needed %lu\n",
	5700	+ mlx5e_get_max_sq_wqebbs(priv->mdev), MLX5E_MAX_TX_WQEBBS);
	5701	+ return -EIO;
	5702	+ }
	5703	+
5697	5704	/* max number of channels may have changed */
5698	5705	max_nch = mlx5e_calc_max_nch(priv->mdev, priv->netdev, profile);
5699	5706	if (priv->channels.params.num_channels > max_nch) {

drivers/net/ethernet/mellanox/mlx5/core/en_rx.c+14−13

@@ -266,7 +266,7 @@ static inline bool mlx5e_rx_cache_get(struct mlx5e_rq *rq, union mlx5e_alloc_uni · 265 unmodified lines
266	266
267	267	addr = page_pool_get_dma_addr(au->page);
268	268	/* Non-XSK always uses PAGE_SIZE. */
269		− dma_sync_single_for_device(rq->pdev, addr, PAGE_SIZE, DMA_FROM_DEVICE);
	269	+ dma_sync_single_for_device(rq->pdev, addr, PAGE_SIZE, rq->buff.map_dir);
270	270	return true;
271	271	}
272	272
@@ -282,8 +282,7 @@ static inline int mlx5e_page_alloc_pool(struct mlx5e_rq *rq, union mlx5e_alloc_u · 9 unmodified lines
282	282	return -ENOMEM;
283	283
284	284	/* Non-XSK always uses PAGE_SIZE. */
285		− addr = dma_map_page_attrs(rq->pdev, au->page, 0, PAGE_SIZE,
286		− rq->buff.map_dir, DMA_ATTR_SKIP_CPU_SYNC);
	285	+ addr = dma_map_page(rq->pdev, au->page, 0, PAGE_SIZE, rq->buff.map_dir);
287	286	if (unlikely(dma_mapping_error(rq->pdev, addr))) {
288	287	page_pool_recycle_direct(rq->page_pool, au->page);
289	288	au->page = NULL;
@@ -427,14 +426,15 @@ mlx5e_add_skb_frag(struct mlx5e_rq rq, struct sk_buff skb, · 137 unmodified lines
427	426	{
428	427	dma_addr_t addr = page_pool_get_dma_addr(au->page);
429	428
430		− dma_sync_single_for_cpu(rq->pdev, addr + frag_offset, len, DMA_FROM_DEVICE);
	429	+ dma_sync_single_for_cpu(rq->pdev, addr + frag_offset, len,
	430	+ rq->buff.map_dir);
431	431	page_ref_inc(au->page);
432	432	skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags,
433	433	au->page, frag_offset, len, truesize);
434	434	}
435	435
436	436	static inline void
437		−mlx5e_copy_skb_header(struct device pdev, struct sk_buff skb,
	437	+mlx5e_copy_skb_header(struct mlx5e_rq rq, struct sk_buff skb,
438	438	struct page *page, dma_addr_t addr,
439	439	int offset_from, int dma_offset, u32 headlen)
440	440	{
@@ -442,7 +442,8 @@ mlx5e_copy_skb_header(struct device pdev, struct sk_buff skb, · 1 unmodified line
442	442	/* Aligning len to sizeof(long) optimizes memcpy performance */
443	443	unsigned int len = ALIGN(headlen, sizeof(long));
444	444
445		− dma_sync_single_for_cpu(pdev, addr + dma_offset, len, DMA_FROM_DEVICE);
	445	+ dma_sync_single_for_cpu(rq->pdev, addr + dma_offset, len,
	446	+ rq->buff.map_dir);
446	447	skb_copy_to_linear_data(skb, from, len);
447	448	}
448	449
@@ -1538,7 +1539,7 @@ mlx5e_skb_from_cqe_linear(struct mlx5e_rq rq, struct mlx5e_wqe_frag_info wi, · 1089 unmodified lines
1538	1539
1539	1540	addr = page_pool_get_dma_addr(au->page);
1540	1541	dma_sync_single_range_for_cpu(rq->pdev, addr, wi->offset,
1541		− frag_size, DMA_FROM_DEVICE);
	1542	+ frag_size, rq->buff.map_dir);
1542	1543	net_prefetch(data);
1543	1544
1544	1545	prog = rcu_dereference(rq->xdp_prog);
@@ -1587,7 +1588,7 @@ mlx5e_skb_from_cqe_nonlinear(struct mlx5e_rq rq, struct mlx5e_wqe_frag_info wi · 42 unmodified lines
1587	1588
1588	1589	addr = page_pool_get_dma_addr(au->page);
1589	1590	dma_sync_single_range_for_cpu(rq->pdev, addr, wi->offset,
1590		− rq->buff.frame0_sz, DMA_FROM_DEVICE);
	1591	+ rq->buff.frame0_sz, rq->buff.map_dir);
1591	1592	net_prefetchw(va); /* xdp_frame data area */
1592	1593	net_prefetch(va + rx_headroom);
1593	1594
@@ -1608,7 +1609,7 @@ mlx5e_skb_from_cqe_nonlinear(struct mlx5e_rq rq, struct mlx5e_wqe_frag_info wi · 14 unmodified lines
1608	1609
1609	1610	addr = page_pool_get_dma_addr(au->page);
1610	1611	dma_sync_single_for_cpu(rq->pdev, addr + wi->offset,
1611		− frag_consumed_bytes, DMA_FROM_DEVICE);
	1612	+ frag_consumed_bytes, rq->buff.map_dir);
1612	1613
1613	1614	if (!xdp_buff_has_frags(&xdp)) {
1614	1615	/* Init on the first fragment to avoid cold cache access
@@ -1905,7 +1906,7 @@ mlx5e_skb_from_cqe_mpwrq_nonlinear(struct mlx5e_rq rq, struct mlx5e_mpw_info w · 290 unmodified lines
1905	1906	mlx5e_fill_skb_data(skb, rq, au, byte_cnt, frag_offset);
1906	1907	/* copy header */
1907	1908	addr = page_pool_get_dma_addr(head_au->page);
1908		− mlx5e_copy_skb_header(rq->pdev, skb, head_au->page, addr,
	1909	+ mlx5e_copy_skb_header(rq, skb, head_au->page, addr,
1909	1910	head_offset, head_offset, headlen);
1910	1911	/* skb linear part was allocated with headlen and aligned to long */
1911	1912	skb->tail += headlen;
@@ -1939,7 +1940,7 @@ mlx5e_skb_from_cqe_mpwrq_linear(struct mlx5e_rq rq, struct mlx5e_mpw_info wi, · 27 unmodified lines
1939	1940
1940	1941	addr = page_pool_get_dma_addr(au->page);
1941	1942	dma_sync_single_range_for_cpu(rq->pdev, addr, head_offset,
1942		− frag_size, DMA_FROM_DEVICE);
	1943	+ frag_size, rq->buff.map_dir);
1943	1944	net_prefetch(data);
1944	1945
1945	1946	prog = rcu_dereference(rq->xdp_prog);
@@ -1987,7 +1988,7 @@ mlx5e_skb_from_cqe_shampo(struct mlx5e_rq rq, struct mlx5e_mpw_info wi, · 41 unmodified lines
1987	1988
1988	1989	if (likely(frag_size <= BIT(MLX5E_SHAMPO_LOG_MAX_HEADER_ENTRY_SIZE))) {
1989	1990	/* build SKB around header */
1990		− dma_sync_single_range_for_cpu(rq->pdev, head->addr, 0, frag_size, DMA_FROM_DEVICE);
	1991	+ dma_sync_single_range_for_cpu(rq->pdev, head->addr, 0, frag_size, rq->buff.map_dir);
1991	1992	prefetchw(hdr);
1992	1993	prefetch(data);
1993	1994	skb = mlx5e_build_linear_skb(rq, hdr, frag_size, rx_headroom, head_size, 0);
@@ -2009,7 +2010,7 @@ mlx5e_skb_from_cqe_shampo(struct mlx5e_rq rq, struct mlx5e_mpw_info wi, · 15 unmodified lines
2009	2010	}
2010	2011
2011	2012	prefetchw(skb->data);
2012		− mlx5e_copy_skb_header(rq->pdev, skb, head->page, head->addr,
	2013	+ mlx5e_copy_skb_header(rq, skb, head->page, head->addr,
2013	2014	head_offset + rx_headroom,
2014	2015	rx_headroom, head_size);
2015	2016	/* skb linear part was allocated with headlen and aligned to long */

drivers/net/ethernet/mellanox/mlx5/core/en_tc.c+6−8

@@ -3633,10 +3633,14 @@ mlx5e_clone_flow_attr_for_post_act(struct mlx5_flow_attr *attr, · 3632 unmodified lines
3633	3633	attr2->action = 0;
3634	3634	attr2->flags = 0;
3635	3635	attr2->parse_attr = parse_attr;
3636		− attr2->esw_attr->out_count = 0;
3637		− attr2->esw_attr->split_count = 0;
3638	3636	attr2->dest_chain = 0;
3639	3637	attr2->dest_ft = NULL;
	3638	+
	3639	+ if (ns_type == MLX5_FLOW_NAMESPACE_FDB) {
	3640	+ attr2->esw_attr->out_count = 0;
	3641	+ attr2->esw_attr->split_count = 0;
	3642	+ }
	3643	+
3640	3644	return attr2;
3641	3645	}
3642	3646
@@ -4758,12 +4762,6 @@ int mlx5e_policer_validate(const struct flow_action *action, · 1115 unmodified lines
4758	4762	return -EOPNOTSUPP;
4759	4763	}
4760	4764
4761		− if (act->police.rate_pkt_ps) {
4762		− NL_SET_ERR_MSG_MOD(extack,
4763		− "QoS offload not support packets per second");
4764		− return -EOPNOTSUPP;
4765		− }
4766		−
4767	4765	return 0;
4768	4766	}
4769	4767

drivers/net/ethernet/mellanox/mlx5/core/en_tx.c+5−0

@@ -305,6 +305,8 @@ static void mlx5e_sq_calc_wqe_attr(struct sk_buff *skb, const struct mlx5e_tx_at · 304 unmodified lines
305	305	u16 ds_cnt_inl = 0;
306	306	u16 ds_cnt_ids = 0;
307	307
	308	+ /* Sync the calculation with MLX5E_MAX_TX_WQEBBS. */
	309	+
308	310	if (attr->insz)
309	311	ds_cnt_ids = DIV_ROUND_UP(sizeof(struct mlx5_wqe_inline_seg) + attr->insz,
310	312	MLX5_SEND_WQE_DS);
@@ -317,6 +319,9 @@ static void mlx5e_sq_calc_wqe_attr(struct sk_buff *skb, const struct mlx5e_tx_at · 6 unmodified lines
317	319	inl += VLAN_HLEN;
318	320
319	321	ds_cnt_inl = DIV_ROUND_UP(inl, MLX5_SEND_WQE_DS);
	322	+ if (WARN_ON_ONCE(ds_cnt_inl > MLX5E_MAX_TX_INLINE_DS))
	323	+ netdev_warn(skb->dev, "ds_cnt_inl = %u > max %u\n", ds_cnt_inl,
	324	+ (u16)MLX5E_MAX_TX_INLINE_DS);
320	325	ds_cnt += ds_cnt_inl;
321	326	}
322	327

drivers/net/ethernet/mellanox/mlx5/core/eswitch.c+8−6

@@ -1387,12 +1387,14 @@ void mlx5_eswitch_disable_locked(struct mlx5_eswitch *esw) · 1386 unmodified lines
1387	1387	esw->mode == MLX5_ESWITCH_LEGACY ? "LEGACY" : "OFFLOADS",
1388	1388	esw->esw_funcs.num_vfs, esw->enabled_vports);
1389	1389
1390		− esw->fdb_table.flags &= ~MLX5_ESW_FDB_CREATED;
1391		− if (esw->mode == MLX5_ESWITCH_OFFLOADS)
1392		− esw_offloads_disable(esw);
1393		− else if (esw->mode == MLX5_ESWITCH_LEGACY)
1394		− esw_legacy_disable(esw);
1395		− mlx5_esw_acls_ns_cleanup(esw);
	1390	+ if (esw->fdb_table.flags & MLX5_ESW_FDB_CREATED) {
	1391	+ esw->fdb_table.flags &= ~MLX5_ESW_FDB_CREATED;
	1392	+ if (esw->mode == MLX5_ESWITCH_OFFLOADS)
	1393	+ esw_offloads_disable(esw);
	1394	+ else if (esw->mode == MLX5_ESWITCH_LEGACY)
	1395	+ esw_legacy_disable(esw);
	1396	+ mlx5_esw_acls_ns_cleanup(esw);
	1397	+ }
1396	1398
1397	1399	if (esw->mode == MLX5_ESWITCH_OFFLOADS)
1398	1400	devl_rate_nodes_destroy(devlink);

drivers/net/ethernet/mellanox/mlx5/core/eswitch_offloads.c+3−15

@@ -2310,7 +2310,7 @@ out_free: · 2309 unmodified lines
2310	2310	static int esw_offloads_start(struct mlx5_eswitch *esw,
2311	2311	struct netlink_ext_ack *extack)
2312	2312	{
2313		− int err, err1;
	2313	+ int err;
2314	2314
2315	2315	esw->mode = MLX5_ESWITCH_OFFLOADS;
2316	2316	err = mlx5_eswitch_enable_locked(esw, esw->dev->priv.sriov.num_vfs);
@@ -2318,11 +2318,6 @@ static int esw_offloads_start(struct mlx5_eswitch *esw, · 1 unmodified line
2318	2318	NL_SET_ERR_MSG_MOD(extack,
2319	2319	"Failed setting eswitch to offloads");
2320	2320	esw->mode = MLX5_ESWITCH_LEGACY;
2321		− err1 = mlx5_eswitch_enable_locked(esw, MLX5_ESWITCH_IGNORE_NUM_VFS);
2322		− if (err1) {
2323		− NL_SET_ERR_MSG_MOD(extack,
2324		− "Failed setting eswitch back to legacy");
2325		− }
2326	2321	mlx5_rescan_drivers(esw->dev);
2327	2322	}
2328	2323	if (esw->offloads.inline_mode == MLX5_INLINE_MODE_NONE) {
@@ -3389,19 +3384,12 @@ err_metadata: · 1060 unmodified lines
3389	3384	static int esw_offloads_stop(struct mlx5_eswitch *esw,
3390	3385	struct netlink_ext_ack *extack)
3391	3386	{
3392		− int err, err1;
	3387	+ int err;
3393	3388
3394	3389	esw->mode = MLX5_ESWITCH_LEGACY;
3395	3390	err = mlx5_eswitch_enable_locked(esw, MLX5_ESWITCH_IGNORE_NUM_VFS);
3396		− if (err) {
	3391	+ if (err)
3397	3392	NL_SET_ERR_MSG_MOD(extack, "Failed setting eswitch to legacy");
3398		− esw->mode = MLX5_ESWITCH_OFFLOADS;
3399		− err1 = mlx5_eswitch_enable_locked(esw, MLX5_ESWITCH_IGNORE_NUM_VFS);
3400		− if (err1) {
3401		− NL_SET_ERR_MSG_MOD(extack,
3402		− "Failed setting eswitch back to offloads");
3403		− }
3404		− }
3405	3393
3406	3394	return err;
3407	3395	}

drivers/net/ethernet/mellanox/mlx5/core/eswitch_offloads_termtbl.c+8−6

@@ -30,9 +30,9 @@ mlx5_eswitch_termtbl_hash(struct mlx5_flow_act *flow_act, · 29 unmodified lines
30	30	sizeof(dest->vport.num), hash);
31	31	hash = jhash((const void *)&dest->vport.vhca_id,
32	32	sizeof(dest->vport.num), hash);
33		− if (dest->vport.pkt_reformat)
34		− hash = jhash(dest->vport.pkt_reformat,
35		− sizeof(*dest->vport.pkt_reformat),
	33	+ if (flow_act->pkt_reformat)
	34	+ hash = jhash(flow_act->pkt_reformat,
	35	+ sizeof(*flow_act->pkt_reformat),
36	36	hash);
37	37	return hash;
38	38	}
@@ -53,9 +53,11 @@ mlx5_eswitch_termtbl_cmp(struct mlx5_flow_act *flow_act1, · 14 unmodified lines
53	53	if (ret)
54	54	return ret;
55	55
56		− return dest1->vport.pkt_reformat && dest2->vport.pkt_reformat ?
57		− memcmp(dest1->vport.pkt_reformat, dest2->vport.pkt_reformat,
58		− sizeof(*dest1->vport.pkt_reformat)) : 0;
	56	+ if (flow_act1->pkt_reformat && flow_act2->pkt_reformat)
	57	+ return memcmp(flow_act1->pkt_reformat, flow_act2->pkt_reformat,
	58	+ sizeof(*flow_act1->pkt_reformat));
	59	+
	60	+ return !(flow_act1->pkt_reformat == flow_act2->pkt_reformat);
59	61	}
60	62
61	63	static int

drivers/net/ethernet/mellanox/mlx5/core/fw_reset.c+2−1

@@ -152,7 +152,8 @@ static void mlx5_fw_reset_complete_reload(struct mlx5_core_dev *dev) · 151 unmodified lines
152	152	mlx5_unload_one(dev);
153	153	if (mlx5_health_wait_pci_up(dev))
154	154	mlx5_core_err(dev, "reset reload flow aborted, PCI reads still not working\n");
155		− mlx5_load_one(dev, false);
	155	+ else
	156	+ mlx5_load_one(dev, false);
156	157	devlink_remote_reload_actions_performed(priv_to_devlink(dev), 0,
157	158	BIT(DEVLINK_RELOAD_ACTION_DRIVER_REINIT) \|
158	159	BIT(DEVLINK_RELOAD_ACTION_FW_ACTIVATE));

drivers/net/ethernet/neterion/s2io.c+20−9

@@ -7128,9 +7128,8 @@ static int s2io_card_up(struct s2io_nic *sp) · 7127 unmodified lines
7128	7128	if (ret) {
7129	7129	DBG_PRINT(ERR_DBG, "%s: Out of memory in Open\n",
7130	7130	dev->name);
7131		− s2io_reset(sp);
7132		− free_rx_buffers(sp);
7133		− return -ENOMEM;
	7131	+ ret = -ENOMEM;
	7132	+ goto err_fill_buff;
7134	7133	}
7135	7134	DBG_PRINT(INFO_DBG, "Buf in ring:%d is %d:\n", i,
7136	7135	ring->rx_bufs_left);
@@ -7168,18 +7167,16 @@ static int s2io_card_up(struct s2io_nic *sp) · 31 unmodified lines
7168	7167	/* Enable Rx Traffic and interrupts on the NIC */
7169	7168	if (start_nic(sp)) {
7170	7169	DBG_PRINT(ERR_DBG, "%s: Starting NIC failed\n", dev->name);
7171		− s2io_reset(sp);
7172		− free_rx_buffers(sp);
7173		− return -ENODEV;
	7170	+ ret = -ENODEV;
	7171	+ goto err_out;
7174	7172	}
7175	7173
7176	7174	/* Add interrupt service routine */
7177	7175	if (s2io_add_isr(sp) != 0) {
7178	7176	if (sp->config.intr_type == MSI_X)
7179	7177	s2io_rem_isr(sp);
7180		− s2io_reset(sp);
7181		− free_rx_buffers(sp);
7182		− return -ENODEV;
	7178	+ ret = -ENODEV;
	7179	+ goto err_out;
7183	7180	}
7184	7181
7185	7182	timer_setup(&sp->alarm_timer, s2io_alarm_handle, 0);
@@ -7199,6 +7196,20 @@ static int s2io_card_up(struct s2io_nic *sp) · 13 unmodified lines
7199	7196	}
7200	7197
7201	7198	return 0;
	7199	+
	7200	+err_out:
	7201	+ if (config->napi) {
	7202	+ if (config->intr_type == MSI_X) {
	7203	+ for (i = 0; i < sp->config.rx_ring_num; i++)
	7204	+ napi_disable(&sp->mac_control.rings[i].napi);
	7205	+ } else {
	7206	+ napi_disable(&sp->napi);
	7207	+ }
	7208	+ }
	7209	+err_fill_buff:
	7210	+ s2io_reset(sp);
	7211	+ free_rx_buffers(sp);
	7212	+ return ret;
7202	7213	}
7203	7214
7204	7215	/**

drivers/net/ethernet/ni/nixge.c+1−0

@@ -900,6 +900,7 @@ static int nixge_open(struct net_device *ndev) · 899 unmodified lines
900	900	err_rx_irq:
901	901	free_irq(priv->tx_irq, ndev);
902	902	err_tx_irq:
	903	+ napi_disable(&priv->napi);
903	904	phy_stop(phy);
904	905	phy_disconnect(phy);
905	906	tasklet_kill(&priv->dma_err_tasklet);

drivers/net/ethernet/stmicro/stmmac/dwmac-intel.c+9−2

@@ -629,7 +629,6 @@ static int ehl_common_data(struct pci_dev *pdev, · 628 unmodified lines
629	629	{
630	630	plat->rx_queues_to_use = 8;
631	631	plat->tx_queues_to_use = 8;
632		− plat->clk_ptp_rate = 200000000;
633	632	plat->use_phy_wol = 1;
634	633
635	634	plat->safety_feat_cfg->tsoee = 1;
@@ -654,6 +653,8 @@ static int ehl_sgmii_data(struct pci_dev *pdev, · 18 unmodified lines
654	653	plat->serdes_powerup = intel_serdes_powerup;
655	654	plat->serdes_powerdown = intel_serdes_powerdown;
656	655
	656	+ plat->clk_ptp_rate = 204800000;
	657	+
657	658	return ehl_common_data(pdev, plat);
658	659	}
659	660
@@ -667,6 +668,8 @@ static int ehl_rgmii_data(struct pci_dev *pdev, · 7 unmodified lines
667	668	plat->bus_id = 1;
668	669	plat->phy_interface = PHY_INTERFACE_MODE_RGMII;
669	670
	671	+ plat->clk_ptp_rate = 204800000;
	672	+
670	673	return ehl_common_data(pdev, plat);
671	674	}
672	675
@@ -683,6 +686,8 @@ static int ehl_pse0_common_data(struct pci_dev *pdev, · 10 unmodified lines
683	686	plat->bus_id = 2;
684	687	plat->addr64 = 32;
685	688
	689	+ plat->clk_ptp_rate = 200000000;
	690	+
686	691	intel_mgbe_pse_crossts_adj(intel_priv, EHL_PSE_ART_MHZ);
687	692
688	693	return ehl_common_data(pdev, plat);
@@ -722,6 +727,8 @@ static int ehl_pse1_common_data(struct pci_dev *pdev, · 33 unmodified lines
722	727	plat->bus_id = 3;
723	728	plat->addr64 = 32;
724	729
	730	+ plat->clk_ptp_rate = 200000000;
	731	+
725	732	intel_mgbe_pse_crossts_adj(intel_priv, EHL_PSE_ART_MHZ);
726	733
727	734	return ehl_common_data(pdev, plat);
@@ -757,7 +764,7 @@ static int tgl_common_data(struct pci_dev *pdev, · 29 unmodified lines
757	764	{
758	765	plat->rx_queues_to_use = 6;
759	766	plat->tx_queues_to_use = 4;
760		− plat->clk_ptp_rate = 200000000;
	767	+ plat->clk_ptp_rate = 204800000;
761	768	plat->speed_mode_2500 = intel_speed_mode_2500;
762	769
763	770	plat->safety_feat_cfg->tsoee = 1;

drivers/net/ethernet/stmicro/stmmac/dwmac-loongson.c+31−8

@@ -75,20 +75,24 @@ static int loongson_dwmac_probe(struct pci_dev *pdev, const struct pci_device_id · 74 unmodified lines
75	75	plat->mdio_bus_data = devm_kzalloc(&pdev->dev,
76	76	sizeof(*plat->mdio_bus_data),
77	77	GFP_KERNEL);
78		− if (!plat->mdio_bus_data)
79		− return -ENOMEM;
	78	+ if (!plat->mdio_bus_data) {
	79	+ ret = -ENOMEM;
	80	+ goto err_put_node;
	81	+ }
80	82	plat->mdio_bus_data->needs_reset = true;
81	83	}
82	84
83	85	plat->dma_cfg = devm_kzalloc(&pdev->dev, sizeof(*plat->dma_cfg), GFP_KERNEL);
84		− if (!plat->dma_cfg)
85		− return -ENOMEM;
	86	+ if (!plat->dma_cfg) {
	87	+ ret = -ENOMEM;
	88	+ goto err_put_node;
	89	+ }
86	90
87	91	/* Enable pci device */
88	92	ret = pci_enable_device(pdev);
89	93	if (ret) {
90	94	dev_err(&pdev->dev, "%s: ERROR: failed to enable device\n", __func__);
91		− return ret;
	95	+ goto err_put_node;
92	96	}
93	97
94	98	/* Get the base address of device */
@@ -97,7 +101,7 @@ static int loongson_dwmac_probe(struct pci_dev *pdev, const struct pci_device_id · 2 unmodified lines
97	101	continue;
98	102	ret = pcim_iomap_regions(pdev, BIT(0), pci_name(pdev));
99	103	if (ret)
100		− return ret;
	104	+ goto err_disable_device;
101	105	break;
102	106	}
103	107
@@ -108,7 +112,8 @@ static int loongson_dwmac_probe(struct pci_dev *pdev, const struct pci_device_id · 4 unmodified lines
108	112	phy_mode = device_get_phy_mode(&pdev->dev);
109	113	if (phy_mode < 0) {
110	114	dev_err(&pdev->dev, "phy_mode not found\n");
111		− return phy_mode;
	115	+ ret = phy_mode;
	116	+ goto err_disable_device;
112	117	}
113	118
114	119	plat->phy_interface = phy_mode;
@@ -125,6 +130,7 @@ static int loongson_dwmac_probe(struct pci_dev *pdev, const struct pci_device_id · 10 unmodified lines
125	130	if (res.irq < 0) {
126	131	dev_err(&pdev->dev, "IRQ macirq not found\n");
127	132	ret = -ENODEV;
	133	+ goto err_disable_msi;
128	134	}
129	135
130	136	res.wol_irq = of_irq_get_byname(np, "eth_wake_irq");
@@ -137,15 +143,31 @@ static int loongson_dwmac_probe(struct pci_dev *pdev, const struct pci_device_id · 6 unmodified lines
137	143	if (res.lpi_irq < 0) {
138	144	dev_err(&pdev->dev, "IRQ eth_lpi not found\n");
139	145	ret = -ENODEV;
	146	+ goto err_disable_msi;
140	147	}
141	148
142		− return stmmac_dvr_probe(&pdev->dev, plat, &res);
	149	+ ret = stmmac_dvr_probe(&pdev->dev, plat, &res);
	150	+ if (ret)
	151	+ goto err_disable_msi;
	152	+
	153	+ return ret;
	154	+
	155	+err_disable_msi:
	156	+ pci_disable_msi(pdev);
	157	+err_disable_device:
	158	+ pci_disable_device(pdev);
	159	+err_put_node:
	160	+ of_node_put(plat->mdio_node);
	161	+ return ret;
143	162	}
144	163
145	164	static void loongson_dwmac_remove(struct pci_dev *pdev)
146	165	{
	166	+ struct net_device *ndev = dev_get_drvdata(&pdev->dev);
	167	+ struct stmmac_priv *priv = netdev_priv(ndev);
147	168	int i;
148	169
	170	+ of_node_put(priv->plat->mdio_node);
149	171	stmmac_dvr_remove(&pdev->dev);
150	172
151	173	for (i = 0; i < PCI_STD_NUM_BARS; i++) {
@@ -155,6 +177,7 @@ static void loongson_dwmac_remove(struct pci_dev *pdev) · 3 unmodified lines
155	177	break;
156	178	}
157	179
	180	+ pci_disable_msi(pdev);
158	181	pci_disable_device(pdev);
159	182	}
160	183

drivers/net/ethernet/stmicro/stmmac/dwmac-meson8b.c+3−5

@@ -272,11 +272,9 @@ static int meson8b_devm_clk_prepare_enable(struct meson8b_dwmac *dwmac, · 271 unmodified lines
272	272	if (ret)
273	273	return ret;
274	274
275		− devm_add_action_or_reset(dwmac->dev,
276		− (void()(void ))clk_disable_unprepare,
277		− dwmac->rgmii_tx_clk);
278		−
279		− return 0;
	275	+ return devm_add_action_or_reset(dwmac->dev,
	276	+ (void()(void ))clk_disable_unprepare,
	277	+ clk);
280	278	}
281	279
282	280	static int meson8b_init_rgmii_delays(struct meson8b_dwmac *dwmac)

drivers/net/ethernet/sunplus/spl2sw_driver.c+0−1

@@ -287,7 +287,6 @@ static u32 spl2sw_init_netdev(struct platform_device pdev, u8 mac_addr, · 286 unmodified lines
287	287	if (ret) {
288	288	dev_err(&pdev->dev, "Failed to register net device \"%s\"!\n",
289	289	ndev->name);
290		− free_netdev(ndev);
291	290	*r_ndev = NULL;
292	291	return ret;
293	292	}

drivers/net/ethernet/ti/am65-cpsw-nuss.c+1−1

@@ -2823,7 +2823,6 @@ static int am65_cpsw_nuss_remove(struct platform_device *pdev) · 2822 unmodified lines
2823	2823	if (ret < 0)
2824	2824	return ret;
2825	2825
2826		− am65_cpsw_nuss_phylink_cleanup(common);
2827	2826	am65_cpsw_unregister_devlink(common);
2828	2827	am65_cpsw_unregister_notifiers(common);
2829	2828
@@ -2831,6 +2830,7 @@ static int am65_cpsw_nuss_remove(struct platform_device *pdev) · 1 unmodified line
2831	2830	* dma_deconfigure(dev) before devres_release_all(dev)
2832	2831	*/
2833	2832	am65_cpsw_nuss_cleanup_ndev(common);
	2833	+ am65_cpsw_nuss_phylink_cleanup(common);
2834	2834
2835	2835	of_platform_device_destroy(common->mdio_dev, NULL);
2836	2836

drivers/net/ethernet/ti/cpsw.c+2−0

@@ -854,6 +854,8 @@ static int cpsw_ndo_open(struct net_device *ndev) · 853 unmodified lines
854	854
855	855	err_cleanup:
856	856	if (!cpsw->usage_count) {
	857	+ napi_disable(&cpsw->napi_rx);
	858	+ napi_disable(&cpsw->napi_tx);
857	859	cpdma_ctlr_stop(cpsw->dma);
858	860	cpsw_destroy_xdp_rxqs(cpsw);
859	861	}

drivers/net/ethernet/tundra/tsi108_eth.c+4−1

@@ -1290,12 +1290,15 @@ static int tsi108_open(struct net_device *dev) · 1289 unmodified lines
1290	1290
1291	1291	data->rxring = dma_alloc_coherent(&data->pdev->dev, rxring_size,
1292	1292	&data->rxdma, GFP_KERNEL);
1293		− if (!data->rxring)
	1293	+ if (!data->rxring) {
	1294	+ free_irq(data->irq_num, dev);
1294	1295	return -ENOMEM;
	1296	+ }
1295	1297
1296	1298	data->txring = dma_alloc_coherent(&data->pdev->dev, txring_size,
1297	1299	&data->txdma, GFP_KERNEL);
1298	1300	if (!data->txring) {
	1301	+ free_irq(data->irq_num, dev);
1299	1302	dma_free_coherent(&data->pdev->dev, rxring_size, data->rxring,
1300	1303	data->rxdma);
1301	1304	return -ENOMEM;

drivers/net/hamradio/bpqether.c+1−1

@@ -533,7 +533,7 @@ static int bpq_device_event(struct notifier_block *this, · 532 unmodified lines
533	533	if (!net_eq(dev_net(dev), &init_net))
534	534	return NOTIFY_DONE;
535	535
536		− if (!dev_is_ethdev(dev))
	536	+ if (!dev_is_ethdev(dev) && !bpq_get_ax25_dev(dev))
537	537	return NOTIFY_DONE;
538	538
539	539	switch (event) {

drivers/net/macsec.c+17−33

@@ -1413,7 +1413,8 @@ static struct macsec_rx_sc del_rx_sc(struct macsec_secy secy, sci_t sci) · 1412 unmodified lines
1413	1413	return NULL;
1414	1414	}
1415	1415
1416		−static struct macsec_rx_sc create_rx_sc(struct net_device dev, sci_t sci)
	1416	+static struct macsec_rx_sc create_rx_sc(struct net_device dev, sci_t sci,
	1417	+ bool active)
1417	1418	{
1418	1419	struct macsec_rx_sc *rx_sc;
1419	1420	struct macsec_dev *macsec;
@@ -1437,7 +1438,7 @@ static struct macsec_rx_sc create_rx_sc(struct net_device dev, sci_t sci) · 17 unmodified lines
1437	1438	}
1438	1439
1439	1440	rx_sc->sci = sci;
1440		− rx_sc->active = true;
	1441	+ rx_sc->active = active;
1441	1442	refcount_set(&rx_sc->refcnt, 1);
1442	1443
1443	1444	secy = &macsec_priv(dev)->secy;
@@ -1838,6 +1839,7 @@ static int macsec_add_rxsa(struct sk_buff skb, struct genl_info info) · 394 unmodified lines
1838	1839	secy->key_len);
1839	1840
1840	1841	err = macsec_offload(ops->mdo_add_rxsa, &ctx);
	1842	+ memzero_explicit(ctx.sa.key, secy->key_len);
1841	1843	if (err)
1842	1844	goto cleanup;
1843	1845	}
@@ -1876,7 +1878,7 @@ static int macsec_add_rxsc(struct sk_buff skb, struct genl_info info) · 32 unmodified lines
1876	1878	struct macsec_rx_sc *rx_sc;
1877	1879	struct nlattr *tb_rxsc[MACSEC_RXSC_ATTR_MAX + 1];
1878	1880	struct macsec_secy *secy;
1879		− bool was_active;
	1881	+ bool active = true;
1880	1882	int ret;
1881	1883
1882	1884	if (!attrs[MACSEC_ATTR_IFINDEX])
@@ -1898,16 +1900,15 @@ static int macsec_add_rxsc(struct sk_buff skb, struct genl_info info) · 15 unmodified lines
1898	1900	secy = &macsec_priv(dev)->secy;
1899	1901	sci = nla_get_sci(tb_rxsc[MACSEC_RXSC_ATTR_SCI]);
1900	1902
1901		− rx_sc = create_rx_sc(dev, sci);
	1903	+ if (tb_rxsc[MACSEC_RXSC_ATTR_ACTIVE])
	1904	+ active = nla_get_u8(tb_rxsc[MACSEC_RXSC_ATTR_ACTIVE]);
	1905	+
	1906	+ rx_sc = create_rx_sc(dev, sci, active);
1902	1907	if (IS_ERR(rx_sc)) {
1903	1908	rtnl_unlock();
1904	1909	return PTR_ERR(rx_sc);
1905	1910	}
1906	1911
1907		− was_active = rx_sc->active;
1908		− if (tb_rxsc[MACSEC_RXSC_ATTR_ACTIVE])
1909		− rx_sc->active = !!nla_get_u8(tb_rxsc[MACSEC_RXSC_ATTR_ACTIVE]);
1910		−
1911	1912	if (macsec_is_offloaded(netdev_priv(dev))) {
1912	1913	const struct macsec_ops *ops;
1913	1914	struct macsec_context ctx;
@@ -1931,7 +1932,8 @@ static int macsec_add_rxsc(struct sk_buff skb, struct genl_info info) · 17 unmodified lines
1931	1932	return 0;
1932	1933
1933	1934	cleanup:
1934		− rx_sc->active = was_active;
	1935	+ del_rx_sc(secy, sci);
	1936	+ free_rx_sc(rx_sc);
1935	1937	rtnl_unlock();
1936	1938	return ret;
1937	1939	}
@@ -2080,6 +2082,7 @@ static int macsec_add_txsa(struct sk_buff skb, struct genl_info info) · 142 unmodified lines
2080	2082	secy->key_len);
2081	2083
2082	2084	err = macsec_offload(ops->mdo_add_txsa, &ctx);
	2085	+ memzero_explicit(ctx.sa.key, secy->key_len);
2083	2086	if (err)
2084	2087	goto cleanup;
2085	2088	}
@@ -2570,7 +2573,7 @@ static bool macsec_is_configured(struct macsec_dev *macsec) · 484 unmodified lines
2570	2573	struct macsec_tx_sc *tx_sc = &secy->tx_sc;
2571	2574	int i;
2572	2575
2573		− if (secy->n_rx_sc > 0)
	2576	+ if (secy->rx_sc)
2574	2577	return true;
2575	2578
2576	2579	for (i = 0; i < MACSEC_NUM_AN; i++)
@@ -2654,11 +2657,6 @@ static int macsec_upd_offload(struct sk_buff skb, struct genl_info info) · 77 unmodified lines
2654	2657	if (ret)
2655	2658	goto rollback;
2656	2659
2657		− /* Force features update, since they are different for SW MACSec and
2658		− * HW offloading cases.
2659		− */
2660		− netdev_update_features(dev);
2661		−
2662	2660	rtnl_unlock();
2663	2661	return 0;
2664	2662
@@ -3432,16 +3430,9 @@ static netdev_tx_t macsec_start_xmit(struct sk_buff *skb, · 767 unmodified lines
3432	3430	return ret;
3433	3431	}
3434	3432
3435		−#define SW_MACSEC_FEATURES \
	3433	+#define MACSEC_FEATURES \
3436	3434	(NETIF_F_SG \| NETIF_F_HIGHDMA \| NETIF_F_FRAGLIST)
3437	3435
3438		−/* If h/w offloading is enabled, use real device features save for
3439		− * VLAN_FEATURES - they require additional ops
3440		− * HW_MACSEC - no reason to report it
3441		− */
3442		−#define REAL_DEV_FEATURES(dev) \
3443		− ((dev)->features & ~(NETIF_F_VLAN_FEATURES \| NETIF_F_HW_MACSEC))
3444		−
3445	3436	static int macsec_dev_init(struct net_device *dev)
3446	3437	{
3447	3438	struct macsec_dev *macsec = macsec_priv(dev);
@@ -3458,12 +3449,8 @@ static int macsec_dev_init(struct net_device *dev) · 10 unmodified lines
3458	3449	return err;
3459	3450	}
3460	3451
3461		− if (macsec_is_offloaded(macsec)) {
3462		− dev->features = REAL_DEV_FEATURES(real_dev);
3463		− } else {
3464		− dev->features = real_dev->features & SW_MACSEC_FEATURES;
3465		− dev->features \|= NETIF_F_LLTX \| NETIF_F_GSO_SOFTWARE;
3466		− }
	3452	+ dev->features = real_dev->features & MACSEC_FEATURES;
	3453	+ dev->features \|= NETIF_F_LLTX \| NETIF_F_GSO_SOFTWARE;
3467	3454
3468	3455	dev->needed_headroom = real_dev->needed_headroom +
3469	3456	MACSEC_NEEDED_HEADROOM;
@@ -3495,10 +3482,7 @@ static netdev_features_t macsec_fix_features(struct net_device *dev, · 25 unmodified lines
3495	3482	struct macsec_dev *macsec = macsec_priv(dev);
3496	3483	struct net_device *real_dev = macsec->real_dev;
3497	3484
3498		− if (macsec_is_offloaded(macsec))
3499		− return REAL_DEV_FEATURES(real_dev);
3500		−
3501		− features &= (real_dev->features & SW_MACSEC_FEATURES) \|
	3485	+ features &= (real_dev->features & MACSEC_FEATURES) \|
3502	3486	NETIF_F_GSO_SOFTWARE \| NETIF_F_SOFT_FEATURES;
3503	3487	features \|= NETIF_F_LLTX;
3504	3488

drivers/net/macvlan.c+3−1

@@ -1533,8 +1533,10 @@ destroy_macvlan_port: · 1532 unmodified lines
1533	1533	/* the macvlan port may be freed by macvlan_uninit when fail to register.
1534	1534	* so we destroy the macvlan port only when it's valid.
1535	1535	*/
1536		− if (create && macvlan_port_get_rtnl(lowerdev))
	1536	+ if (create && macvlan_port_get_rtnl(lowerdev)) {
	1537	+ macvlan_flush_sources(port, vlan);
1537	1538	macvlan_port_destroy(port->dev);
	1539	+ }
1538	1540	return err;
1539	1541	}
1540	1542	EXPORT_SYMBOL_GPL(macvlan_common_newlink);

drivers/net/phy/mscc/mscc_macsec.c+1−0

@@ -632,6 +632,7 @@ static void vsc8584_macsec_free_flow(struct vsc8531_private *priv, · 631 unmodified lines
632	632
633	633	list_del(&flow->list);
634	634	clear_bit(flow->index, bitmap);
	635	+ memzero_explicit(flow->key, sizeof(flow->key));
635	636	kfree(flow);
636	637	}
637	638

drivers/net/tun.c+13−5

@@ -1967,17 +1967,25 @@ drop: · 1966 unmodified lines
1967	1967	skb_headlen(skb));
1968	1968
1969	1969	if (unlikely(headlen > skb_headlen(skb))) {
	1970	+ WARN_ON_ONCE(1);
	1971	+ err = -ENOMEM;
1970	1972	dev_core_stats_rx_dropped_inc(tun->dev);
	1973	+napi_busy:
1971	1974	napi_free_frags(&tfile->napi);
1972	1975	rcu_read_unlock();
1973	1976	mutex_unlock(&tfile->napi_mutex);
1974		− WARN_ON(1);
1975		− return -ENOMEM;
	1977	+ return err;
1976	1978	}
1977	1979
1978		− local_bh_disable();
1979		− napi_gro_frags(&tfile->napi);
1980		− local_bh_enable();
	1980	+ if (likely(napi_schedule_prep(&tfile->napi))) {
	1981	+ local_bh_disable();
	1982	+ napi_gro_frags(&tfile->napi);
	1983	+ napi_complete(&tfile->napi);
	1984	+ local_bh_enable();
	1985	+ } else {
	1986	+ err = -EBUSY;
	1987	+ goto napi_busy;
	1988	+ }
1981	1989	mutex_unlock(&tfile->napi_mutex);
1982	1990	} else if (tfile->napi_enabled) {
1983	1991	struct sk_buff_head *queue = &tfile->sk.sk_write_queue;

drivers/net/wan/lapbether.c+2−1

@@ -325,6 +325,7 @@ static int lapbeth_open(struct net_device *dev) · 324 unmodified lines
325	325
326	326	err = lapb_register(dev, &lapbeth_callbacks);
327	327	if (err != LAPB_OK) {
	328	+ napi_disable(&lapbeth->napi);
328	329	pr_err("lapb_register error: %d\n", err);
329	330	return -ENODEV;
330	331	}
@@ -446,7 +447,7 @@ static int lapbeth_device_event(struct notifier_block *this, · 115 unmodified lines
446	447	if (dev_net(dev) != &init_net)
447	448	return NOTIFY_DONE;
448	449
449		− if (!dev_is_ethdev(dev))
	450	+ if (!dev_is_ethdev(dev) && !lapbeth_get_x25_dev(dev))
450	451	return NOTIFY_DONE;
451	452
452	453	switch (event) {

drivers/net/wireless/ath/ath11k/qmi.h+1−1

@@ -27,7 +27,7 @@ · 26 unmodified lines
27	27	#define ATH11K_QMI_WLANFW_MAX_NUM_MEM_SEG_V01 52
28	28	#define ATH11K_QMI_CALDB_SIZE 0x480000
29	29	#define ATH11K_QMI_BDF_EXT_STR_LENGTH 0x20
30		−#define ATH11K_QMI_FW_MEM_REQ_SEGMENT_CNT 3
	30	+#define ATH11K_QMI_FW_MEM_REQ_SEGMENT_CNT 5
31	31
32	32	#define QMI_WLFW_REQUEST_MEM_IND_V01 0x0035
33	33	#define QMI_WLFW_FW_MEM_READY_IND_V01 0x0037

drivers/net/wireless/ath/ath11k/reg.c+1−5

@@ -287,11 +287,7 @@ int ath11k_regd_update(struct ath11k *ar) · 286 unmodified lines
287	287	goto err;
288	288	}
289	289
290		− rtnl_lock();
291		− wiphy_lock(ar->hw->wiphy);
292		− ret = regulatory_set_wiphy_regd_sync(ar->hw->wiphy, regd_copy);
293		− wiphy_unlock(ar->hw->wiphy);
294		− rtnl_unlock();
	290	+ ret = regulatory_set_wiphy_regd(ar->hw->wiphy, regd_copy);
295	291
296	292	kfree(regd_copy);
297	293

drivers/net/wireless/broadcom/brcm80211/brcmfmac/fweh.c+4−0

@@ -228,6 +228,10 @@ static void brcmf_fweh_event_worker(struct work_struct *work) · 227 unmodified lines
228	228	brcmf_fweh_event_name(event->code), event->code,
229	229	event->emsg.ifidx, event->emsg.bsscfgidx,
230	230	event->emsg.addr);
	231	+ if (event->emsg.bsscfgidx >= BRCMF_MAX_IFS) {
	232	+ bphy_err(drvr, "invalid bsscfg index: %u\n", event->emsg.bsscfgidx);
	233	+ goto event_free;
	234	+ }
231	235
232	236	/* convert event message */
233	237	emsg_be = &event->emsg;

drivers/net/wireless/cisco/airo.c+14−4

@@ -5232,7 +5232,7 @@ static int get_wep_tx_idx(struct airo_info *ai) · 5231 unmodified lines
5232	5232	return -1;
5233	5233	}
5234	5234
5235		−static int set_wep_key(struct airo_info ai, u16 index, const char key,
	5235	+static int set_wep_key(struct airo_info ai, u16 index, const u8 key,
5236	5236	u16 keylen, int perm, int lock)
5237	5237	{
5238	5238	static const unsigned char macaddr[ETH_ALEN] = { 0x01, 0, 0, 0, 0, 0 };
@@ -5283,7 +5283,7 @@ static void proc_wepkey_on_close(struct inode inode, struct file file) · 44 unmodified lines
5283	5283	struct net_device *dev = pde_data(inode);
5284	5284	struct airo_info *ai = dev->ml_priv;
5285	5285	int i, rc;
5286		− char key[16];
	5286	+ u8 key[16];
5287	5287	u16 index = 0;
5288	5288	int j = 0;
5289	5289
@@ -5311,12 +5311,22 @@ static void proc_wepkey_on_close(struct inode inode, struct file file) · 21 unmodified lines
5311	5311	}
5312	5312
5313	5313	for (i = 0; i < 16*3 && data->wbuffer[i+j]; i++) {
	5314	+ int val;
	5315	+
	5316	+ if (i % 3 == 2)
	5317	+ continue;
	5318	+
	5319	+ val = hex_to_bin(data->wbuffer[i+j]);
	5320	+ if (val < 0) {
	5321	+ airo_print_err(ai->dev->name, "WebKey passed invalid key hex");
	5322	+ return;
	5323	+ }
5314	5324	switch(i%3) {
5315	5325	case 0:
5316		− key[i/3] = hex_to_bin(data->wbuffer[i+j])<<4;
	5326	+ key[i/3] = (u8)val << 4;
5317	5327	break;
5318	5328	case 1:
5319		− key[i/3] \|= hex_to_bin(data->wbuffer[i+j]);
	5329	+ key[i/3] \|= (u8)val;
5320	5330	break;
5321	5331	}
5322	5332	}

drivers/net/wireless/mac80211_hwsim.c+5−0

@@ -910,6 +910,7 @@ static void hwsim_send_nullfunc(struct mac80211_hwsim_data data, u8 mac, · 909 unmodified lines
910	910	struct hwsim_vif_priv vp = (void )vif->drv_priv;
911	911	struct sk_buff *skb;
912	912	struct ieee80211_hdr *hdr;
	913	+ struct ieee80211_tx_info *cb;
913	914
914	915	if (!vp->assoc)
915	916	return;
@@ -931,6 +932,10 @@ static void hwsim_send_nullfunc(struct mac80211_hwsim_data data, u8 mac, · 15 unmodified lines
931	932	memcpy(hdr->addr2, mac, ETH_ALEN);
932	933	memcpy(hdr->addr3, vp->bssid, ETH_ALEN);
933	934
	935	+ cb = IEEE80211_SKB_CB(skb);
	936	+ cb->control.rates[0].count = 1;
	937	+ cb->control.rates[1].idx = -1;
	938	+
934	939	rcu_read_lock();
935	940	mac80211_hwsim_tx_frame(data->hw, skb,
936	941	rcu_dereference(vif->bss_conf.chanctx_conf)->def.chan);

drivers/net/wireless/ralink/rt2x00/rt2400pci.c+4−4

@@ -1023,9 +1023,9 @@ static int rt2400pci_set_state(struct rt2x00_dev *rt2x00dev, · 1022 unmodified lines
1023	1023	{
1024	1024	u32 reg, reg2;
1025	1025	unsigned int i;
1026		− char put_to_sleep;
1027		− char bbp_state;
1028		− char rf_state;
	1026	+ bool put_to_sleep;
	1027	+ u8 bbp_state;
	1028	+ u8 rf_state;
1029	1029
1030	1030	put_to_sleep = (state != STATE_AWAKE);
1031	1031
@@ -1561,7 +1561,7 @@ static int rt2400pci_probe_hw_mode(struct rt2x00_dev *rt2x00dev) · 529 unmodified lines
1561	1561	{
1562	1562	struct hw_mode_spec *spec = &rt2x00dev->spec;
1563	1563	struct channel_info *info;
1564		− char *tx_power;
	1564	+ u8 *tx_power;
1565	1565	unsigned int i;
1566	1566
1567	1567	/*

drivers/net/wireless/ralink/rt2x00/rt2400pci.h+1−1

@@ -939,7 +939,7 @@ · 938 unmodified lines
939	939	#define DEFAULT_TXPOWER 39
940	940
941	941	#define __CLAMP_TX(__txpower) \
942		− clamp_t(char, (__txpower), MIN_TXPOWER, MAX_TXPOWER)
	942	+ clamp_t(u8, (__txpower), MIN_TXPOWER, MAX_TXPOWER)
943	943
944	944	#define TXPOWER_FROM_DEV(__txpower) \
945	945	((__CLAMP_TX(__txpower) - MAX_TXPOWER) + MIN_TXPOWER)

drivers/net/wireless/ralink/rt2x00/rt2500pci.c+4−4

@@ -1176,9 +1176,9 @@ static int rt2500pci_set_state(struct rt2x00_dev *rt2x00dev, · 1175 unmodified lines
1176	1176	{
1177	1177	u32 reg, reg2;
1178	1178	unsigned int i;
1179		− char put_to_sleep;
1180		− char bbp_state;
1181		− char rf_state;
	1179	+ bool put_to_sleep;
	1180	+ u8 bbp_state;
	1181	+ u8 rf_state;
1182	1182
1183	1183	put_to_sleep = (state != STATE_AWAKE);
1184	1184
@@ -1856,7 +1856,7 @@ static int rt2500pci_probe_hw_mode(struct rt2x00_dev *rt2x00dev) · 671 unmodified lines
1856	1856	{
1857	1857	struct hw_mode_spec *spec = &rt2x00dev->spec;
1858	1858	struct channel_info *info;
1859		− char *tx_power;
	1859	+ u8 *tx_power;
1860	1860	unsigned int i;
1861	1861
1862	1862	/*

drivers/net/wireless/ralink/rt2x00/rt2500pci.h+1−1

@@ -1219,6 +1219,6 @@ · 1218 unmodified lines
1219	1219	(((u8)(__txpower)) > MAX_TXPOWER) ? DEFAULT_TXPOWER : (__txpower)
1220	1220
1221	1221	#define TXPOWER_TO_DEV(__txpower) \
1222		− clamp_t(char, __txpower, MIN_TXPOWER, MAX_TXPOWER)
	1222	+ clamp_t(u8, __txpower, MIN_TXPOWER, MAX_TXPOWER)
1223	1223
1224	1224	#endif /* RT2500PCI_H */

drivers/net/wireless/ralink/rt2x00/rt2500usb.c+4−4

@@ -984,9 +984,9 @@ static int rt2500usb_set_state(struct rt2x00_dev *rt2x00dev, · 983 unmodified lines
984	984	u16 reg;
985	985	u16 reg2;
986	986	unsigned int i;
987		− char put_to_sleep;
988		− char bbp_state;
989		− char rf_state;
	987	+ bool put_to_sleep;
	988	+ u8 bbp_state;
	989	+ u8 rf_state;
990	990
991	991	put_to_sleep = (state != STATE_AWAKE);
992	992
@@ -1663,7 +1663,7 @@ static int rt2500usb_probe_hw_mode(struct rt2x00_dev *rt2x00dev) · 670 unmodified lines
1663	1663	{
1664	1664	struct hw_mode_spec *spec = &rt2x00dev->spec;
1665	1665	struct channel_info *info;
1666		− char *tx_power;
	1666	+ u8 *tx_power;
1667	1667	unsigned int i;
1668	1668
1669	1669	/*

drivers/net/wireless/ralink/rt2x00/rt2500usb.h+1−1

@@ -839,6 +839,6 @@ · 838 unmodified lines
839	839	(((u8)(__txpower)) > MAX_TXPOWER) ? DEFAULT_TXPOWER : (__txpower)
840	840
841	841	#define TXPOWER_TO_DEV(__txpower) \
842		− clamp_t(char, __txpower, MIN_TXPOWER, MAX_TXPOWER)
	842	+ clamp_t(u8, __txpower, MIN_TXPOWER, MAX_TXPOWER)
843	843
844	844	#endif /* RT2500USB_H */

drivers/net/wireless/ralink/rt2x00/rt2800lib.c+30−30

@@ -3372,10 +3372,10 @@ static void rt2800_config_channel_rf53xx(struct rt2x00_dev *rt2x00dev, · 3371 unmodified lines
3372	3372	if (rt2x00_has_cap_bt_coexist(rt2x00dev)) {
3373	3373	if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F)) {
3374	3374	/* r55/r59 value array of channel 1~14 */
3375		− static const char r55_bt_rev[] = {0x83, 0x83,
	3375	+ static const u8 r55_bt_rev[] = {0x83, 0x83,
3376	3376	0x83, 0x73, 0x73, 0x63, 0x53, 0x53,
3377	3377	0x53, 0x43, 0x43, 0x43, 0x43, 0x43};
3378		− static const char r59_bt_rev[] = {0x0e, 0x0e,
	3378	+ static const u8 r59_bt_rev[] = {0x0e, 0x0e,
3379	3379	0x0e, 0x0e, 0x0e, 0x0b, 0x0a, 0x09,
3380	3380	0x07, 0x07, 0x07, 0x07, 0x07, 0x07};
3381	3381
@@ -3384,7 +3384,7 @@ static void rt2800_config_channel_rf53xx(struct rt2x00_dev *rt2x00dev, · 2 unmodified lines
3384	3384	rt2800_rfcsr_write(rt2x00dev, 59,
3385	3385	r59_bt_rev[idx]);
3386	3386	} else {
3387		− static const char r59_bt[] = {0x8b, 0x8b, 0x8b,
	3387	+ static const u8 r59_bt[] = {0x8b, 0x8b, 0x8b,
3388	3388	0x8b, 0x8b, 0x8b, 0x8b, 0x8a, 0x89,
3389	3389	0x88, 0x88, 0x86, 0x85, 0x84};
3390	3390
@@ -3392,10 +3392,10 @@ static void rt2800_config_channel_rf53xx(struct rt2x00_dev *rt2x00dev, · 1 unmodified line
3392	3392	}
3393	3393	} else {
3394	3394	if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F)) {
3395		− static const char r55_nonbt_rev[] = {0x23, 0x23,
	3395	+ static const u8 r55_nonbt_rev[] = {0x23, 0x23,
3396	3396	0x23, 0x23, 0x13, 0x13, 0x03, 0x03,
3397	3397	0x03, 0x03, 0x03, 0x03, 0x03, 0x03};
3398		− static const char r59_nonbt_rev[] = {0x07, 0x07,
	3398	+ static const u8 r59_nonbt_rev[] = {0x07, 0x07,
3399	3399	0x07, 0x07, 0x07, 0x07, 0x07, 0x07,
3400	3400	0x07, 0x07, 0x06, 0x05, 0x04, 0x04};
3401	3401
@@ -3406,14 +3406,14 @@ static void rt2800_config_channel_rf53xx(struct rt2x00_dev *rt2x00dev, · 4 unmodified lines
3406	3406	} else if (rt2x00_rt(rt2x00dev, RT5390) \|\|
3407	3407	rt2x00_rt(rt2x00dev, RT5392) \|\|
3408	3408	rt2x00_rt(rt2x00dev, RT6352)) {
3409		− static const char r59_non_bt[] = {0x8f, 0x8f,
	3409	+ static const u8 r59_non_bt[] = {0x8f, 0x8f,
3410	3410	0x8f, 0x8f, 0x8f, 0x8f, 0x8f, 0x8d,
3411	3411	0x8a, 0x88, 0x88, 0x87, 0x87, 0x86};
3412	3412
3413	3413	rt2800_rfcsr_write(rt2x00dev, 59,
3414	3414	r59_non_bt[idx]);
3415	3415	} else if (rt2x00_rt(rt2x00dev, RT5350)) {
3416		− static const char r59_non_bt[] = {0x0b, 0x0b,
	3416	+ static const u8 r59_non_bt[] = {0x0b, 0x0b,
3417	3417	0x0b, 0x0b, 0x0b, 0x0b, 0x0b, 0x0a,
3418	3418	0x0a, 0x09, 0x08, 0x07, 0x07, 0x06};
3419	3419
@@ -4035,23 +4035,23 @@ static void rt2800_iq_calibrate(struct rt2x00_dev *rt2x00dev, int channel) · 615 unmodified lines
4035	4035	rt2800_bbp_write(rt2x00dev, 159, cal != 0xff ? cal : 0);
4036	4036	}
4037	4037
4038		−static char rt2800_txpower_to_dev(struct rt2x00_dev *rt2x00dev,
	4038	+static s8 rt2800_txpower_to_dev(struct rt2x00_dev *rt2x00dev,
4039	4039	unsigned int channel,
4040		− char txpower)
	4040	+ s8 txpower)
4041	4041	{
4042	4042	if (rt2x00_rt(rt2x00dev, RT3593) \|\|
4043	4043	rt2x00_rt(rt2x00dev, RT3883))
4044	4044	txpower = rt2x00_get_field8(txpower, EEPROM_TXPOWER_ALC);
4045	4045
4046	4046	if (channel <= 14)
4047		− return clamp_t(char, txpower, MIN_G_TXPOWER, MAX_G_TXPOWER);
	4047	+ return clamp_t(s8, txpower, MIN_G_TXPOWER, MAX_G_TXPOWER);
4048	4048
4049	4049	if (rt2x00_rt(rt2x00dev, RT3593) \|\|
4050	4050	rt2x00_rt(rt2x00dev, RT3883))
4051		− return clamp_t(char, txpower, MIN_A_TXPOWER_3593,
	4051	+ return clamp_t(s8, txpower, MIN_A_TXPOWER_3593,
4052	4052	MAX_A_TXPOWER_3593);
4053	4053	else
4054		− return clamp_t(char, txpower, MIN_A_TXPOWER, MAX_A_TXPOWER);
	4054	+ return clamp_t(s8, txpower, MIN_A_TXPOWER, MAX_A_TXPOWER);
4055	4055	}
4056	4056
4057	4057	static void rt3883_bbp_adjust(struct rt2x00_dev *rt2x00dev,
@@ -8530,7 +8530,7 @@ static void rt2800_r_calibration(struct rt2x00_dev *rt2x00dev) · 4472 unmodified lines
8530	8530	u8 bytevalue = 0;
8531	8531	int rcalcode;
8532	8532	u8 r_cal_code = 0;
8533		− char d1 = 0, d2 = 0;
	8533	+ s8 d1 = 0, d2 = 0;
8534	8534	u8 rfvalue;
8535	8535	u32 MAC_RF_BYPASS0, MAC_RF_CONTROL0, MAC_PWR_PIN_CFG;
8536	8536	u32 maccfg;
@@ -8591,7 +8591,7 @@ static void rt2800_r_calibration(struct rt2x00_dev *rt2x00dev) · 54 unmodified lines
8591	8591	if (bytevalue > 128)
8592	8592	d1 = bytevalue - 256;
8593	8593	else
8594		− d1 = (char)bytevalue;
	8594	+ d1 = (s8)bytevalue;
8595	8595	rt2800_bbp_write(rt2x00dev, 22, 0x0);
8596	8596	rt2800_rfcsr_write_bank(rt2x00dev, 0, 35, 0x01);
8597	8597
@@ -8601,7 +8601,7 @@ static void rt2800_r_calibration(struct rt2x00_dev *rt2x00dev) · 3 unmodified lines
8601	8601	if (bytevalue > 128)
8602	8602	d2 = bytevalue - 256;
8603	8603	else
8604		− d2 = (char)bytevalue;
	8604	+ d2 = (s8)bytevalue;
8605	8605	rt2800_bbp_write(rt2x00dev, 22, 0x0);
8606	8606
8607	8607	rcalcode = rt2800_calcrcalibrationcode(rt2x00dev, d1, d2);
@@ -8703,7 +8703,7 @@ static void rt2800_rxdcoc_calibration(struct rt2x00_dev *rt2x00dev) · 95 unmodified lines
8703	8703	static u32 rt2800_do_sqrt_accumulation(u32 si)
8704	8704	{
8705	8705	u32 root, root_pre, bit;
8706		− char i;
	8706	+ s8 i;
8707	8707
8708	8708	bit = 1 << 15;
8709	8709	root = 0;
@@ -9330,11 +9330,11 @@ static void rt2800_loft_search(struct rt2x00_dev *rt2x00dev, u8 ch_idx, · 620 unmodified lines
9330	9330	u8 alc_idx, u8 dc_result[][RF_ALC_NUM][2])
9331	9331	{
9332	9332	u32 p0 = 0, p1 = 0, pf = 0;
9333		− char idx0 = 0, idx1 = 0;
	9333	+ s8 idx0 = 0, idx1 = 0;
9334	9334	u8 idxf[] = {0x00, 0x00};
9335	9335	u8 ibit = 0x20;
9336	9336	u8 iorq;
9337		− char bidx;
	9337	+ s8 bidx;
9338	9338
9339	9339	rt2800_bbp_write(rt2x00dev, 158, 0xb0);
9340	9340	rt2800_bbp_write(rt2x00dev, 159, 0x80);
@@ -9384,17 +9384,17 @@ static void rt2800_loft_search(struct rt2x00_dev *rt2x00dev, u8 ch_idx, · 43 unmodified lines
9384	9384	static void rt2800_iq_search(struct rt2x00_dev rt2x00dev, u8 ch_idx, u8 ges, u8 *pes)
9385	9385	{
9386	9386	u32 p0 = 0, p1 = 0, pf = 0;
9387		− char perr = 0, gerr = 0, iq_err = 0;
9388		− char pef = 0, gef = 0;
9389		− char psta, pend;
9390		− char gsta, gend;
	9387	+ s8 perr = 0, gerr = 0, iq_err = 0;
	9388	+ s8 pef = 0, gef = 0;
	9389	+ s8 psta, pend;
	9390	+ s8 gsta, gend;
9391	9391
9392	9392	u8 ibit = 0x20;
9393	9393	u8 first_search = 0x00, touch_neg_max = 0x00;
9394		− char idx0 = 0, idx1 = 0;
	9394	+ s8 idx0 = 0, idx1 = 0;
9395	9395	u8 gop;
9396	9396	u8 bbp = 0;
9397		− char bidx;
	9397	+ s8 bidx;
9398	9398
9399	9399	for (bidx = 5; bidx >= 1; bidx--) {
9400	9400	for (gop = 0; gop < 2; gop++) {
@@ -10043,11 +10043,11 @@ static int rt2800_rf_lp_config(struct rt2x00_dev *rt2x00dev, bool btxcal) · 642 unmodified lines
10043	10043	return 0;
10044	10044	}
10045	10045
10046		−static char rt2800_lp_tx_filter_bw_cal(struct rt2x00_dev *rt2x00dev)
	10046	+static s8 rt2800_lp_tx_filter_bw_cal(struct rt2x00_dev *rt2x00dev)
10047	10047	{
10048	10048	unsigned int cnt;
10049	10049	u8 bbp_val;
10050		− char cal_val;
	10050	+ s8 cal_val;
10051	10051
10052	10052	rt2800_bbp_dcoc_write(rt2x00dev, 0, 0x82);
10053	10053
@@ -10079,7 +10079,7 @@ static void rt2800_bw_filter_calibration(struct rt2x00_dev *rt2x00dev, · 25 unmodified lines
10079	10079	u8 rx_filter_target_20m = 0x27, rx_filter_target_40m = 0x31;
10080	10080	int loop = 0, is_ht40, cnt;
10081	10081	u8 bbp_val, rf_val;
10082		− char cal_r32_init, cal_r32_val, cal_diff;
	10082	+ s8 cal_r32_init, cal_r32_val, cal_diff;
10083	10083	u8 saverfb5r00, saverfb5r01, saverfb5r03, saverfb5r04, saverfb5r05;
10084	10084	u8 saverfb5r06, saverfb5r07;
10085	10085	u8 saverfb5r08, saverfb5r17, saverfb5r18, saverfb5r19, saverfb5r20;
@@ -11550,9 +11550,9 @@ static int rt2800_probe_hw_mode(struct rt2x00_dev *rt2x00dev) · 1464 unmodified lines
11550	11550	{
11551	11551	struct hw_mode_spec *spec = &rt2x00dev->spec;
11552	11552	struct channel_info *info;
11553		− char *default_power1;
11554		− char *default_power2;
11555		− char *default_power3;
	11553	+ s8 *default_power1;
	11554	+ s8 *default_power2;
	11555	+ s8 *default_power3;
11556	11556	unsigned int i, tx_chains, rx_chains;
11557	11557	u32 reg;
11558	11558

drivers/net/wireless/ralink/rt2x00/rt2800lib.h+4−4

@@ -32,10 +32,10 @@ struct rf_reg_pair { · 31 unmodified lines
32	32	struct rt2800_drv_data {
33	33	u8 calibration_bw20;
34	34	u8 calibration_bw40;
35		− char rx_calibration_bw20;
36		− char rx_calibration_bw40;
37		− char tx_calibration_bw20;
38		− char tx_calibration_bw40;
	35	+ s8 rx_calibration_bw20;
	36	+ s8 rx_calibration_bw40;
	37	+ s8 tx_calibration_bw20;
	38	+ s8 tx_calibration_bw40;
39	39	u8 bbp25;
40	40	u8 bbp26;
41	41	u8 txmixer_gain_24g;

drivers/net/wireless/ralink/rt2x00/rt2x00usb.c+3−3

@@ -117,12 +117,12 @@ int rt2x00usb_vendor_request_buff(struct rt2x00_dev *rt2x00dev, · 116 unmodified lines
117	117	const u16 buffer_length)
118	118	{
119	119	int status = 0;
120		− unsigned char *tb;
	120	+ u8 *tb;
121	121	u16 off, len, bsize;
122	122
123	123	mutex_lock(&rt2x00dev->csr_mutex);
124	124
125		− tb = (char *)buffer;
	125	+ tb = (u8 *)buffer;
126	126	off = offset;
127	127	len = buffer_length;
128	128	while (len && !status) {
@@ -215,7 +215,7 @@ void rt2x00usb_register_read_async(struct rt2x00_dev *rt2x00dev, · 86 unmodified lines
215	215	rd->cr.wLength = cpu_to_le16(sizeof(u32));
216	216
217	217	usb_fill_control_urb(urb, usb_dev, usb_rcvctrlpipe(usb_dev, 0),
218		− (unsigned char *)(&rd->cr), &rd->reg, sizeof(rd->reg),
	218	+ (u8 *)(&rd->cr), &rd->reg, sizeof(rd->reg),
219	219	rt2x00usb_register_read_async_cb, rd);
220	220	usb_anchor_urb(urb, rt2x00dev->anchor);
221	221	if (usb_submit_urb(urb, GFP_ATOMIC) < 0) {

drivers/net/wireless/ralink/rt2x00/rt61pci.c+2−2

@@ -1709,7 +1709,7 @@ static int rt61pci_set_state(struct rt2x00_dev *rt2x00dev, enum dev_state state) · 1708 unmodified lines
1709	1709	{
1710	1710	u32 reg, reg2;
1711	1711	unsigned int i;
1712		− char put_to_sleep;
	1712	+ bool put_to_sleep;
1713	1713
1714	1714	put_to_sleep = (state != STATE_AWAKE);
1715	1715
@@ -2656,7 +2656,7 @@ static int rt61pci_probe_hw_mode(struct rt2x00_dev *rt2x00dev) · 940 unmodified lines
2656	2656	{
2657	2657	struct hw_mode_spec *spec = &rt2x00dev->spec;
2658	2658	struct channel_info *info;
2659		− char *tx_power;
	2659	+ u8 *tx_power;
2660	2660	unsigned int i;
2661	2661
2662	2662	/*

drivers/net/wireless/ralink/rt2x00/rt61pci.h+1−1

@@ -1484,6 +1484,6 @@ struct hw_pairwise_ta_entry { · 1483 unmodified lines
1484	1484	(((u8)(__txpower)) > MAX_TXPOWER) ? DEFAULT_TXPOWER : (__txpower)
1485	1485
1486	1486	#define TXPOWER_TO_DEV(__txpower) \
1487		− clamp_t(char, __txpower, MIN_TXPOWER, MAX_TXPOWER)
	1487	+ clamp_t(u8, __txpower, MIN_TXPOWER, MAX_TXPOWER)
1488	1488
1489	1489	#endif /* RT61PCI_H */

drivers/net/wireless/ralink/rt2x00/rt73usb.c+2−2

@@ -1378,7 +1378,7 @@ static int rt73usb_set_state(struct rt2x00_dev *rt2x00dev, enum dev_state state) · 1377 unmodified lines
1378	1378	{
1379	1379	u32 reg, reg2;
1380	1380	unsigned int i;
1381		− char put_to_sleep;
	1381	+ bool put_to_sleep;
1382	1382
1383	1383	put_to_sleep = (state != STATE_AWAKE);
1384	1384
@@ -2090,7 +2090,7 @@ static int rt73usb_probe_hw_mode(struct rt2x00_dev *rt2x00dev) · 705 unmodified lines
2090	2090	{
2091	2091	struct hw_mode_spec *spec = &rt2x00dev->spec;
2092	2092	struct channel_info *info;
2093		− char *tx_power;
	2093	+ u8 *tx_power;
2094	2094	unsigned int i;
2095	2095
2096	2096	/*

drivers/net/wireless/ralink/rt2x00/rt73usb.h+1−1

@@ -1063,6 +1063,6 @@ struct hw_pairwise_ta_entry { · 1062 unmodified lines
1063	1063	(((u8)(__txpower)) > MAX_TXPOWER) ? DEFAULT_TXPOWER : (__txpower)
1064	1064
1065	1065	#define TXPOWER_TO_DEV(__txpower) \
1066		− clamp_t(char, __txpower, MIN_TXPOWER, MAX_TXPOWER)
	1066	+ clamp_t(u8, __txpower, MIN_TXPOWER, MAX_TXPOWER)
1067	1067
1068	1068	#endif /* RT73USB_H */

drivers/net/wwan/Kconfig+1−1

@@ -94,7 +94,7 @@ config RPMSG_WWAN_CTRL · 93 unmodified lines
94	94
95	95	config IOSM
96	96	tristate "IOSM Driver for Intel M.2 WWAN Device"
97		− depends on INTEL_IOMMU
	97	+ depends on PCI
98	98	select NET_DEVLINK
99	99	select RELAY if WWAN_DEBUGFS
100	100	help

drivers/net/wwan/iosm/iosm_ipc_coredump.c+1−0

@@ -2,6 +2,7 @@ · 1 unmodified line
2	2	/*
3	3	* Copyright (C) 2020-2021 Intel Corporation.
4	4	*/
	5	+#include <linux/vmalloc.h>
5	6
6	7	#include "iosm_ipc_coredump.h"
7	8

drivers/net/wwan/iosm/iosm_ipc_devlink.c+1−0

@@ -2,6 +2,7 @@ · 1 unmodified line
2	2	/*
3	3	* Copyright (C) 2020-2021 Intel Corporation.
4	4	*/
	5	+#include <linux/vmalloc.h>
5	6
6	7	#include "iosm_ipc_chnl_cfg.h"
7	8	#include "iosm_ipc_coredump.h"

drivers/net/wwan/iosm/iosm_ipc_imem_ops.c+8−0

@@ -91,6 +91,14 @@ void ipc_imem_wwan_channel_init(struct iosm_imem *ipc_imem, · 90 unmodified lines
91	91	}
92	92
93	93	ipc_chnl_cfg_get(&chnl_cfg, ipc_imem->nr_of_channels);
	94	+
	95	+ if (ipc_imem->mmio->mux_protocol == MUX_AGGREGATION &&
	96	+ ipc_imem->nr_of_channels == IPC_MEM_IP_CHL_ID_0) {
	97	+ chnl_cfg.ul_nr_of_entries = IPC_MEM_MAX_TDS_MUX_AGGR_UL;
	98	+ chnl_cfg.dl_nr_of_entries = IPC_MEM_MAX_TDS_MUX_AGGR_DL;
	99	+ chnl_cfg.dl_buf_size = IPC_MEM_MAX_ADB_BUF_SIZE;
	100	+ }
	101	+
94	102	ipc_imem_channel_init(ipc_imem, IPC_CTYPE_WWAN, chnl_cfg,
95	103	IRQ_MOD_OFF);
96	104

drivers/net/wwan/iosm/iosm_ipc_mux.h+1−0

@@ -10,6 +10,7 @@ · 9 unmodified lines
10	10
11	11	#define IPC_MEM_MAX_UL_DG_ENTRIES 100
12	12	#define IPC_MEM_MAX_TDS_MUX_AGGR_UL 60
	13	+#define IPC_MEM_MAX_TDS_MUX_AGGR_DL 60
13	14
14	15	#define IPC_MEM_MAX_ADB_BUF_SIZE (16 * 1024)
15	16	#define IPC_MEM_MAX_UL_ADB_BUF_SIZE IPC_MEM_MAX_ADB_BUF_SIZE

drivers/net/wwan/iosm/iosm_ipc_pcie.c+15−3

@@ -232,6 +232,7 @@ static void ipc_pcie_config_init(struct iosm_pcie *ipc_pcie) · 231 unmodified lines
232	232	*/
233	233	static enum ipc_pcie_sleep_state ipc_pcie_read_bios_cfg(struct device *dev)
234	234	{
	235	+ enum ipc_pcie_sleep_state sleep_state = IPC_PCIE_D0L12;
235	236	union acpi_object *object;
236	237	acpi_handle handle_acpi;
237	238
@@ -242,18 +243,23 @@ static enum ipc_pcie_sleep_state ipc_pcie_read_bios_cfg(struct device *dev) · 4 unmodified lines
242	243	}
243	244
244	245	object = acpi_evaluate_dsm(handle_acpi, &wwan_acpi_guid, 0, 3, NULL);
	246	+ if (!object)
	247	+ goto default_ret;
	248	+
	249	+ if (object->integer.value == 3)
	250	+ sleep_state = IPC_PCIE_D3L2;
245	251
246		− if (object && object->integer.value == 3)
247		− return IPC_PCIE_D3L2;
	252	+ kfree(object);
248	253
249	254	default_ret:
250		− return IPC_PCIE_D0L12;
	255	+ return sleep_state;
251	256	}
252	257
253	258	static int ipc_pcie_probe(struct pci_dev *pci,
254	259	const struct pci_device_id *pci_id)
255	260	{
256	261	struct iosm_pcie ipc_pcie = kzalloc(sizeof(ipc_pcie), GFP_KERNEL);
	262	+ int ret;
257	263
258	264	pr_debug("Probing device 0x%X from the vendor 0x%X", pci_id->device,
259	265	pci_id->vendor);
@@ -286,6 +292,12 @@ static int ipc_pcie_probe(struct pci_dev *pci, · 26 unmodified lines
286	292	goto pci_enable_fail;
287	293	}
288	294
	295	+ ret = dma_set_mask(ipc_pcie->dev, DMA_BIT_MASK(64));
	296	+ if (ret) {
	297	+ dev_err(ipc_pcie->dev, "Could not set PCI DMA mask: %d", ret);
	298	+ return ret;
	299	+ }
	300	+
289	301	ipc_pcie_config_aspm(ipc_pcie);
290	302	dev_dbg(ipc_pcie->dev, "PCIe device enabled.");
291	303

drivers/net/wwan/iosm/iosm_ipc_wwan.c+7−36

@@ -40,13 +40,11 @@ struct iosm_netdev_priv { · 39 unmodified lines
40	40	* @ipc_imem: Pointer to imem data-struct
41	41	* @sub_netlist: List of active netdevs
42	42	* @dev: Pointer device structure
43		− * @if_mutex: Mutex used for add and remove interface id
44	43	*/
45	44	struct iosm_wwan {
46	45	struct iosm_imem *ipc_imem;
47	46	struct iosm_netdev_priv __rcu *sub_netlist[IP_MUX_SESSION_END + 1];
48	47	struct device *dev;
49		− struct mutex if_mutex; /* Mutex used for add and remove interface id */
50	48	};
51	49
52	50	/* Bring-up the wwan net link */
@@ -55,14 +53,11 @@ static int ipc_wwan_link_open(struct net_device *netdev) · 2 unmodified lines
55	53	struct iosm_netdev_priv *priv = wwan_netdev_drvpriv(netdev);
56	54	struct iosm_wwan *ipc_wwan = priv->ipc_wwan;
57	55	int if_id = priv->if_id;
58		− int ret;
59	56
60	57	if (if_id < IP_MUX_SESSION_START \|\|
61	58	if_id >= ARRAY_SIZE(ipc_wwan->sub_netlist))
62	59	return -EINVAL;
63	60
64		− mutex_lock(&ipc_wwan->if_mutex);
65		−
66	61	/* get channel id */
67	62	priv->ch_id = ipc_imem_sys_wwan_open(ipc_wwan->ipc_imem, if_id);
68	63
@@ -70,8 +65,7 @@ static int ipc_wwan_link_open(struct net_device *netdev) · 1 unmodified line
70	65	dev_err(ipc_wwan->dev,
71	66	"cannot connect wwan0 & id %d to the IPC mem layer",
72	67	if_id);
73		− ret = -ENODEV;
74		− goto out;
	68	+ return -ENODEV;
75	69	}
76	70
77	71	/* enable tx path, DL data may follow */
@@ -80,10 +74,7 @@ static int ipc_wwan_link_open(struct net_device *netdev) · 2 unmodified lines
80	74	dev_dbg(ipc_wwan->dev, "Channel id %d allocated to if_id %d",
81	75	priv->ch_id, priv->if_id);
82	76
83		− ret = 0;
84		−out:
85		− mutex_unlock(&ipc_wwan->if_mutex);
86		− return ret;
	77	+ return 0;
87	78	}
88	79
89	80	/* Bring-down the wwan net link */
@@ -93,11 +84,9 @@ static int ipc_wwan_link_stop(struct net_device *netdev) · 3 unmodified lines
93	84
94	85	netif_stop_queue(netdev);
95	86
96		− mutex_lock(&priv->ipc_wwan->if_mutex);
97	87	ipc_imem_sys_wwan_close(priv->ipc_wwan->ipc_imem, priv->if_id,
98	88	priv->ch_id);
99	89	priv->ch_id = -1;
100		− mutex_unlock(&priv->ipc_wwan->if_mutex);
101	90
102	91	return 0;
103	92	}
@@ -168,6 +157,7 @@ static void ipc_wwan_setup(struct net_device *iosm_dev) · 64 unmodified lines
168	157	iosm_dev->max_mtu = ETH_MAX_MTU;
169	158
170	159	iosm_dev->flags = IFF_POINTOPOINT \| IFF_NOARP;
	160	+ iosm_dev->needs_free_netdev = true;
171	161
172	162	iosm_dev->netdev_ops = &ipc_inm_ops;
173	163	}
@@ -189,26 +179,17 @@ static int ipc_wwan_newlink(void ctxt, struct net_device dev, · 15 unmodified lines
189	179	priv->netdev = dev;
190	180	priv->ipc_wwan = ipc_wwan;
191	181
192		− mutex_lock(&ipc_wwan->if_mutex);
193		− if (rcu_access_pointer(ipc_wwan->sub_netlist[if_id])) {
194		− err = -EBUSY;
195		− goto out_unlock;
196		− }
	182	+ if (rcu_access_pointer(ipc_wwan->sub_netlist[if_id]))
	183	+ return -EBUSY;
197	184
198	185	err = register_netdevice(dev);
199	186	if (err)
200		− goto out_unlock;
	187	+ return err;
201	188
202	189	rcu_assign_pointer(ipc_wwan->sub_netlist[if_id], priv);
203		− mutex_unlock(&ipc_wwan->if_mutex);
204		−
205	190	netif_device_attach(dev);
206	191
207	192	return 0;
208		−
209		−out_unlock:
210		− mutex_unlock(&ipc_wwan->if_mutex);
211		− return err;
212	193	}
213	194
214	195	static void ipc_wwan_dellink(void ctxt, struct net_device dev,
@@ -222,17 +203,12 @@ static void ipc_wwan_dellink(void ctxt, struct net_device dev, · 7 unmodified lines
222	203	if_id >= ARRAY_SIZE(ipc_wwan->sub_netlist)))
223	204	return;
224	205
225		− mutex_lock(&ipc_wwan->if_mutex);
226		−
227	206	if (WARN_ON(rcu_access_pointer(ipc_wwan->sub_netlist[if_id]) != priv))
228		− goto unlock;
	207	+ return;
229	208
230	209	RCU_INIT_POINTER(ipc_wwan->sub_netlist[if_id], NULL);
231	210	/* unregistering includes synchronize_net() */
232	211	unregister_netdevice_queue(dev, head);
233		−
234		−unlock:
235		− mutex_unlock(&ipc_wwan->if_mutex);
236	212	}
237	213
238	214	static const struct wwan_ops iosm_wwan_ops = {
@@ -323,12 +299,9 @@ struct iosm_wwan ipc_wwan_init(struct iosm_imem ipc_imem, struct device *dev) · 84 unmodified lines
323	299	ipc_wwan->dev = dev;
324	300	ipc_wwan->ipc_imem = ipc_imem;
325	301
326		− mutex_init(&ipc_wwan->if_mutex);
327		−
328	302	/* WWAN core will create a netdev for the default IP MUX channel */
329	303	if (wwan_register_ops(ipc_wwan->dev, &iosm_wwan_ops, ipc_wwan,
330	304	IP_MUX_SESSION_DEFAULT)) {
331		− mutex_destroy(&ipc_wwan->if_mutex);
332	305	kfree(ipc_wwan);
333	306	return NULL;
334	307	}
@@ -341,7 +314,5 @@ void ipc_wwan_deinit(struct iosm_wwan *ipc_wwan) · 6 unmodified lines
341	314	/* This call will remove all child netdev(s) */
342	315	wwan_unregister_ops(ipc_wwan->dev);
343	316
344		− mutex_destroy(&ipc_wwan->if_mutex);
345		−
346	317	kfree(ipc_wwan);
347	318	}

drivers/net/wwan/mhi_wwan_mbim.c+1−0

@@ -582,6 +582,7 @@ static void mhi_mbim_setup(struct net_device *ndev) · 581 unmodified lines
582	582	ndev->min_mtu = ETH_MIN_MTU;
583	583	ndev->max_mtu = MHI_MAX_BUF_SZ - ndev->needed_headroom;
584	584	ndev->tx_queue_len = 1000;
	585	+ ndev->needs_free_netdev = true;
585	586	}
586	587
587	588	static const struct wwan_ops mhi_mbim_wwan_ops = {

drivers/nvme/host/core.c+1−2

@@ -675,6 +675,7 @@ void nvme_init_request(struct request req, struct nvme_command cmd) · 674 unmodified lines
675	675	if (req->mq_hctx->type == HCTX_TYPE_POLL)
676	676	req->cmd_flags \|= REQ_POLLED;
677	677	nvme_clear_nvme_request(req);
	678	+ req->rq_flags \|= RQF_QUIET;
678	679	memcpy(nvme_req(req)->cmd, cmd, sizeof(*cmd));
679	680	}
680	681	EXPORT_SYMBOL_GPL(nvme_init_request);
@@ -1037,7 +1038,6 @@ int __nvme_submit_sync_cmd(struct request_queue q, struct nvme_command cmd, · 356 unmodified lines
1037	1038	goto out;
1038	1039	}
1039	1040
1040		− req->rq_flags \|= RQF_QUIET;
1041	1041	ret = nvme_execute_rq(req, at_head);
1042	1042	if (result && ret >= 0)
1043	1043	*result = nvme_req(req)->result;
@@ -1227,7 +1227,6 @@ static void nvme_keep_alive_work(struct work_struct *work) · 183 unmodified lines
1227	1227	rq->timeout = ctrl->kato * HZ;
1228	1228	rq->end_io = nvme_keep_alive_end_io;
1229	1229	rq->end_io_data = ctrl;
1230		− rq->rq_flags \|= RQF_QUIET;
1231	1230	blk_execute_rq_nowait(rq, false);
1232	1231	}
1233	1232

drivers/nvme/host/pci.c+0−2

@@ -1436,7 +1436,6 @@ static enum blk_eh_timer_return nvme_timeout(struct request *req) · 1435 unmodified lines
1436	1436
1437	1437	abort_req->end_io = abort_endio;
1438	1438	abort_req->end_io_data = NULL;
1439		− abort_req->rq_flags \|= RQF_QUIET;
1440	1439	blk_execute_rq_nowait(abort_req, false);
1441	1440
1442	1441	/*
@@ -2490,7 +2489,6 @@ static int nvme_delete_queue(struct nvme_queue *nvmeq, u8 opcode) · 1047 unmodified lines
2490	2489	req->end_io_data = nvmeq;
2491	2490
2492	2491	init_completion(&nvmeq->delete_done);
2493		− req->rq_flags \|= RQF_QUIET;
2494	2492	blk_execute_rq_nowait(req, false);
2495	2493	return 0;
2496	2494	}

drivers/nvme/target/configfs.c+6−2

@@ -1215,6 +1215,7 @@ static ssize_t nvmet_subsys_attr_model_store_locked(struct nvmet_subsys *subsys, · 1214 unmodified lines
1215	1215	const char *page, size_t count)
1216	1216	{
1217	1217	int pos = 0, len;
	1218	+ char *val;
1218	1219
1219	1220	if (subsys->subsys_discovered) {
1220	1221	pr_err("Can't set model number. %s is already assigned\n",
@@ -1237,9 +1238,11 @@ static ssize_t nvmet_subsys_attr_model_store_locked(struct nvmet_subsys *subsys, · 16 unmodified lines
1237	1238	return -EINVAL;
1238	1239	}
1239	1240
1240		− subsys->model_number = kmemdup_nul(page, len, GFP_KERNEL);
1241		− if (!subsys->model_number)
	1241	+ val = kmemdup_nul(page, len, GFP_KERNEL);
	1242	+ if (!val)
1242	1243	return -ENOMEM;
	1244	+ kfree(subsys->model_number);
	1245	+ subsys->model_number = val;
1243	1246	return count;
1244	1247	}
1245	1248
@@ -1836,6 +1839,7 @@ static void nvmet_host_release(struct config_item *item) · 590 unmodified lines
1836	1839
1837	1840	#ifdef CONFIG_NVME_TARGET_AUTH
1838	1841	kfree(host->dhchap_secret);
	1842	+ kfree(host->dhchap_ctrl_secret);
1839	1843	#endif
1840	1844	kfree(host);
1841	1845	}

drivers/pci/controller/pci-hyperv.c+16−6

@@ -1614,7 +1614,7 @@ out: · 1613 unmodified lines
1614	1614
1615	1615	static u32 hv_compose_msi_req_v1(
1616	1616	struct pci_create_interrupt int_pkt, const struct cpumask affinity,
1617		− u32 slot, u8 vector, u8 vector_count)
	1617	+ u32 slot, u8 vector, u16 vector_count)
1618	1618	{
1619	1619	int_pkt->message_type.type = PCI_CREATE_INTERRUPT_MESSAGE;
1620	1620	int_pkt->wslot.slot = slot;
@@ -1642,7 +1642,7 @@ static int hv_compose_msi_req_get_cpu(const struct cpumask *affinity) · 21 unmodified lines
1642	1642
1643	1643	static u32 hv_compose_msi_req_v2(
1644	1644	struct pci_create_interrupt2 int_pkt, const struct cpumask affinity,
1645		− u32 slot, u8 vector, u8 vector_count)
	1645	+ u32 slot, u8 vector, u16 vector_count)
1646	1646	{
1647	1647	int cpu;
1648	1648
@@ -1661,7 +1661,7 @@ static u32 hv_compose_msi_req_v2( · 12 unmodified lines
1661	1661
1662	1662	static u32 hv_compose_msi_req_v3(
1663	1663	struct pci_create_interrupt3 int_pkt, const struct cpumask affinity,
1664		− u32 slot, u32 vector, u8 vector_count)
	1664	+ u32 slot, u32 vector, u16 vector_count)
1665	1665	{
1666	1666	int cpu;
1667	1667
@@ -1701,7 +1701,12 @@ static void hv_compose_msi_msg(struct irq_data data, struct msi_msg msg) · 33 unmodified lines
1701	1701	struct compose_comp_ctxt comp;
1702	1702	struct tran_int_desc *int_desc;
1703	1703	struct msi_desc *msi_desc;
1704		− u8 vector, vector_count;
	1704	+ /*
	1705	+ * vector_count should be u16: see hv_msi_desc, hv_msi_desc2
	1706	+ * and hv_msi_desc3. vector must be u32: see hv_msi_desc3.
	1707	+ */
	1708	+ u16 vector_count;
	1709	+ u32 vector;
1705	1710	struct {
1706	1711	struct pci_packet pci_pkt;
1707	1712	union {
@@ -1767,6 +1772,11 @@ static void hv_compose_msi_msg(struct irq_data data, struct msi_msg msg) · 59 unmodified lines
1767	1772	vector_count = 1;
1768	1773	}
1769	1774
	1775	+ /*
	1776	+ * hv_compose_msi_req_v1 and v2 are for x86 only, meaning 'vector'
	1777	+ * can't exceed u8. Cast 'vector' down to u8 for v1/v2 explicitly
	1778	+ * for better readability.
	1779	+ */
1770	1780	memset(&ctxt, 0, sizeof(ctxt));
1771	1781	init_completion(&comp.comp_pkt.host_event);
1772	1782	ctxt.pci_pkt.completion_func = hv_pci_compose_compl;
@@ -1777,7 +1787,7 @@ static void hv_compose_msi_msg(struct irq_data data, struct msi_msg msg) · 4 unmodified lines
1777	1787	size = hv_compose_msi_req_v1(&ctxt.int_pkts.v1,
1778	1788	dest,
1779	1789	hpdev->desc.win_slot.slot,
1780		− vector,
	1790	+ (u8)vector,
1781	1791	vector_count);
1782	1792	break;
1783	1793
@@ -1786,7 +1796,7 @@ static void hv_compose_msi_msg(struct irq_data data, struct msi_msg msg) · 2 unmodified lines
1786	1796	size = hv_compose_msi_req_v2(&ctxt.int_pkts.v2,
1787	1797	dest,
1788	1798	hpdev->desc.win_slot.slot,
1789		− vector,
	1799	+ (u8)vector,
1790	1800	vector_count);
1791	1801	break;
1792	1802

drivers/phy/qualcomm/phy-qcom-qmp-combo.c+1−1

@@ -2240,7 +2240,7 @@ static void qmp_combo_enable_autonomous_mode(struct qmp_phy *qphy) · 2239 unmodified lines
2240	2240	static void qmp_combo_disable_autonomous_mode(struct qmp_phy *qphy)
2241	2241	{
2242	2242	const struct qmp_phy_cfg *cfg = qphy->cfg;
2243		− void __iomem *pcs_usb = qphy->pcs_usb ?: qphy->pcs_usb;
	2243	+ void __iomem *pcs_usb = qphy->pcs_usb ?: qphy->pcs;
2244	2244	void __iomem *pcs_misc = qphy->pcs_misc;
2245	2245
2246	2246	/* Disable i/o clamp_n on resume for normal mode */

drivers/phy/ralink/phy-mt7621-pci.c+2−1

@@ -280,7 +280,8 @@ static struct phy mt7621_pcie_phy_of_xlate(struct device dev, · 279 unmodified lines
280	280	}
281	281
282	282	static const struct soc_device_attribute mt7621_pci_quirks_match[] = {
283		− { .soc_id = "mt7621", .revision = "E2" }
	283	+ { .soc_id = "mt7621", .revision = "E2" },
	284	+ { /* sentinel */ }
284	285	};
285	286
286	287	static const struct regmap_config mt7621_pci_phy_regmap_config = {

drivers/phy/st/phy-stm32-usbphyc.c+2−0

@@ -710,6 +710,8 @@ static int stm32_usbphyc_probe(struct platform_device *pdev) · 709 unmodified lines
710	710	ret = of_property_read_u32(child, "reg", &index);
711	711	if (ret \|\| index > usbphyc->nphys) {
712	712	dev_err(&phy->dev, "invalid reg property: %d\n", ret);
	713	+ if (!ret)
	714	+ ret = -EINVAL;
713	715	goto put_child;
714	716	}
715	717

drivers/phy/sunplus/phy-sunplus-usb2.c+2−2

@@ -256,8 +256,8 @@ static int sp_usb_phy_probe(struct platform_device *pdev) · 255 unmodified lines
256	256	usbphy->moon4_res_mem = platform_get_resource_byname(pdev, IORESOURCE_MEM, "moon4");
257	257	usbphy->moon4_regs = devm_ioremap(&pdev->dev, usbphy->moon4_res_mem->start,
258	258	resource_size(usbphy->moon4_res_mem));
259		− if (IS_ERR(usbphy->moon4_regs))
260		− return PTR_ERR(usbphy->moon4_regs);
	259	+ if (!usbphy->moon4_regs)
	260	+ return -ENOMEM;
261	261
262	262	usbphy->phy_clk = devm_clk_get(&pdev->dev, NULL);
263	263	if (IS_ERR(usbphy->phy_clk))

drivers/phy/tegra/xusb.c+16−4

@@ -1461,8 +1461,14 @@ EXPORT_SYMBOL_GPL(tegra_phy_xusb_utmi_port_reset); · 1460 unmodified lines
1461	1461
1462	1462	void tegra_phy_xusb_utmi_pad_power_on(struct phy *phy)
1463	1463	{
1464		− struct tegra_xusb_lane *lane = phy_get_drvdata(phy);
1465		− struct tegra_xusb_padctl *padctl = lane->pad->padctl;
	1464	+ struct tegra_xusb_lane *lane;
	1465	+ struct tegra_xusb_padctl *padctl;
	1466	+
	1467	+ if (!phy)
	1468	+ return;
	1469	+
	1470	+ lane = phy_get_drvdata(phy);
	1471	+ padctl = lane->pad->padctl;
1466	1472
1467	1473	if (padctl->soc->ops->utmi_pad_power_on)
1468	1474	padctl->soc->ops->utmi_pad_power_on(phy);
@@ -1471,8 +1477,14 @@ EXPORT_SYMBOL_GPL(tegra_phy_xusb_utmi_pad_power_on); · 2 unmodified lines
1471	1477
1472	1478	void tegra_phy_xusb_utmi_pad_power_down(struct phy *phy)
1473	1479	{
1474		− struct tegra_xusb_lane *lane = phy_get_drvdata(phy);
1475		− struct tegra_xusb_padctl *padctl = lane->pad->padctl;
	1480	+ struct tegra_xusb_lane *lane;
	1481	+ struct tegra_xusb_padctl *padctl;
	1482	+
	1483	+ if (!phy)
	1484	+ return;
	1485	+
	1486	+ lane = phy_get_drvdata(phy);
	1487	+ padctl = lane->pad->padctl;
1476	1488
1477	1489	if (padctl->soc->ops->utmi_pad_power_down)
1478	1490	padctl->soc->ops->utmi_pad_power_down(phy);

drivers/platform/x86/hp-wmi.c+10−2

@@ -1300,8 +1300,16 @@ static int __init hp_wmi_bios_setup(struct platform_device *device) · 1299 unmodified lines
1300	1300	wwan_rfkill = NULL;
1301	1301	rfkill2_count = 0;
1302	1302
1303		− if (hp_wmi_rfkill_setup(device))
1304		− hp_wmi_rfkill2_setup(device);
	1303	+ /*
	1304	+ * In pre-2009 BIOS, command 1Bh return 0x4 to indicate that
	1305	+ * BIOS no longer controls the power for the wireless
	1306	+ * devices. All features supported by this command will no
	1307	+ * longer be supported.
	1308	+ */
	1309	+ if (!hp_wmi_bios_2009_later()) {
	1310	+ if (hp_wmi_rfkill_setup(device))
	1311	+ hp_wmi_rfkill2_setup(device);
	1312	+ }
1305	1313
1306	1314	err = hp_wmi_hwmon_init();
1307	1315

drivers/platform/x86/ideapad-laptop.c+24−1

@@ -1533,6 +1533,24 @@ static const struct dmi_system_id hw_rfkill_list[] = { · 1532 unmodified lines
1533	1533	{}
1534	1534	};
1535	1535
	1536	+static const struct dmi_system_id no_touchpad_switch_list[] = {
	1537	+ {
	1538	+ .ident = "Lenovo Yoga 3 Pro 1370",
	1539	+ .matches = {
	1540	+ DMI_MATCH(DMI_SYS_VENDOR, "LENOVO"),
	1541	+ DMI_MATCH(DMI_PRODUCT_VERSION, "Lenovo YOGA 3"),
	1542	+ },
	1543	+ },
	1544	+ {
	1545	+ .ident = "ZhaoYang K4e-IML",
	1546	+ .matches = {
	1547	+ DMI_MATCH(DMI_SYS_VENDOR, "LENOVO"),
	1548	+ DMI_MATCH(DMI_PRODUCT_VERSION, "ZhaoYang K4e-IML"),
	1549	+ },
	1550	+ },
	1551	+ {}
	1552	+};
	1553	+
1536	1554	static void ideapad_check_features(struct ideapad_private *priv)
1537	1555	{
1538	1556	acpi_handle handle = priv->adev->handle;
@@ -1541,7 +1559,12 @@ static void ideapad_check_features(struct ideapad_private *priv) · 2 unmodified lines
1541	1559	priv->features.hw_rfkill_switch = dmi_check_system(hw_rfkill_list);
1542	1560
1543	1561	/* Most ideapads with ELAN0634 touchpad don't use EC touchpad switch */
1544		− priv->features.touchpad_ctrl_via_ec = !acpi_dev_present("ELAN0634", NULL, -1);
	1562	+ if (acpi_dev_present("ELAN0634", NULL, -1))
	1563	+ priv->features.touchpad_ctrl_via_ec = 0;
	1564	+ else if (dmi_check_system(no_touchpad_switch_list))
	1565	+ priv->features.touchpad_ctrl_via_ec = 0;
	1566	+ else
	1567	+ priv->features.touchpad_ctrl_via_ec = 1;
1545	1568
1546	1569	if (!read_ec_data(handle, VPCCMD_R_FAN, &val))
1547	1570	priv->features.fan_mode = true;

drivers/platform/x86/intel/hid.c+3−0

@@ -27,6 +27,9 @@ static const struct acpi_device_id intel_hid_ids[] = { · 26 unmodified lines
27	27	{"INTC1051", 0},
28	28	{"INTC1054", 0},
29	29	{"INTC1070", 0},
	30	+ {"INTC1076", 0},
	31	+ {"INTC1077", 0},
	32	+ {"INTC1078", 0},
30	33	{"", 0},
31	34	};
32	35	MODULE_DEVICE_TABLE(acpi, intel_hid_ids);

drivers/platform/x86/intel/pmt/class.c+30−1

@@ -9,6 +9,7 @@ · 8 unmodified lines
9	9	*/
10	10
11	11	#include <linux/kernel.h>
	12	+#include <linux/io-64-nonatomic-lo-hi.h>
12	13	#include <linux/module.h>
13	14	#include <linux/mm.h>
14	15	#include <linux/pci.h>
@@ -19,6 +20,7 @@ · 4 unmodified lines
19	20	#define PMT_XA_START 0
20	21	#define PMT_XA_MAX INT_MAX
21	22	#define PMT_XA_LIMIT XA_LIMIT(PMT_XA_START, PMT_XA_MAX)
	23	+#define GUID_SPR_PUNIT 0x9956f43f
22	24
23	25	bool intel_pmt_is_early_client_hw(struct device *dev)
24	26	{
@@ -33,6 +35,29 @@ bool intel_pmt_is_early_client_hw(struct device *dev) · 8 unmodified lines
33	35	}
34	36	EXPORT_SYMBOL_GPL(intel_pmt_is_early_client_hw);
35	37
	38	+static inline int
	39	+pmt_memcpy64_fromio(void to, const u64 __iomem from, size_t count)
	40	+{
	41	+ int i, remain;
	42	+ u64 *buf = to;
	43	+
	44	+ if (!IS_ALIGNED((unsigned long)from, 8))
	45	+ return -EFAULT;
	46	+
	47	+ for (i = 0; i < count/8; i++)
	48	+ buf[i] = readq(&from[i]);
	49	+
	50	+ /* Copy any remaining bytes */
	51	+ remain = count % 8;
	52	+ if (remain) {
	53	+ u64 tmp = readq(&from[i]);
	54	+
	55	+ memcpy(&buf[i], &tmp, remain);
	56	+ }
	57	+
	58	+ return count;
	59	+}
	60	+
36	61	/*
37	62	* sysfs
38	63	*/
@@ -54,7 +79,11 @@ intel_pmt_read(struct file filp, struct kobject kobj, · 15 unmodified lines
54	79	if (count > entry->size - off)
55	80	count = entry->size - off;
56	81
57		− memcpy_fromio(buf, entry->base + off, count);
	82	+ if (entry->guid == GUID_SPR_PUNIT)
	83	+ /* PUNIT on SPR only supports aligned 64-bit read */
	84	+ count = pmt_memcpy64_fromio(buf, entry->base + off, count);
	85	+ else
	86	+ memcpy_fromio(buf, entry->base + off, count);
58	87
59	88	return count;
60	89	}

drivers/platform/x86/p2sb.c+6−9

@@ -19,26 +19,23 @@ · 18 unmodified lines
19	19	#define P2SBC 0xe0
20	20	#define P2SBC_HIDE BIT(8)
21	21
	22	+#define P2SB_DEVFN_DEFAULT PCI_DEVFN(31, 1)
	23	+
22	24	static const struct x86_cpu_id p2sb_cpu_ids[] = {
23	25	X86_MATCH_INTEL_FAM6_MODEL(ATOM_GOLDMONT, PCI_DEVFN(13, 0)),
24		− X86_MATCH_INTEL_FAM6_MODEL(ATOM_GOLDMONT_D, PCI_DEVFN(31, 1)),
25		− X86_MATCH_INTEL_FAM6_MODEL(ATOM_SILVERMONT_D, PCI_DEVFN(31, 1)),
26		− X86_MATCH_INTEL_FAM6_MODEL(KABYLAKE, PCI_DEVFN(31, 1)),
27		− X86_MATCH_INTEL_FAM6_MODEL(KABYLAKE_L, PCI_DEVFN(31, 1)),
28		− X86_MATCH_INTEL_FAM6_MODEL(SKYLAKE, PCI_DEVFN(31, 1)),
29		− X86_MATCH_INTEL_FAM6_MODEL(SKYLAKE_L, PCI_DEVFN(31, 1)),
30	26	{}
31	27	};
32	28
33	29	static int p2sb_get_devfn(unsigned int *devfn)
34	30	{
	31	+ unsigned int fn = P2SB_DEVFN_DEFAULT;
35	32	const struct x86_cpu_id *id;
36	33
37	34	id = x86_match_cpu(p2sb_cpu_ids);
38		− if (!id)
39		− return -ENODEV;
	35	+ if (id)
	36	+ fn = (unsigned int)id->driver_data;
40	37
41		− *devfn = (unsigned int)id->driver_data;
	38	+ *devfn = fn;
42	39	return 0;
43	40	}
44	41

drivers/platform/x86/touchscreen_dmi.c+25−0

@@ -770,6 +770,22 @@ static const struct ts_dmi_data predia_basic_data = { · 769 unmodified lines
770	770	.properties = predia_basic_props,
771	771	};
772	772
	773	+static const struct property_entry rca_cambio_w101_v2_props[] = {
	774	+ PROPERTY_ENTRY_U32("touchscreen-min-x", 4),
	775	+ PROPERTY_ENTRY_U32("touchscreen-min-y", 20),
	776	+ PROPERTY_ENTRY_U32("touchscreen-size-x", 1644),
	777	+ PROPERTY_ENTRY_U32("touchscreen-size-y", 874),
	778	+ PROPERTY_ENTRY_BOOL("touchscreen-swapped-x-y"),
	779	+ PROPERTY_ENTRY_STRING("firmware-name", "gsl1680-rca-cambio-w101-v2.fw"),
	780	+ PROPERTY_ENTRY_U32("silead,max-fingers", 10),
	781	+ { }
	782	+};
	783	+
	784	+static const struct ts_dmi_data rca_cambio_w101_v2_data = {
	785	+ .acpi_name = "MSSL1680:00",
	786	+ .properties = rca_cambio_w101_v2_props,
	787	+};
	788	+
773	789	static const struct property_entry rwc_nanote_p8_props[] = {
774	790	PROPERTY_ENTRY_U32("touchscreen-min-y", 46),
775	791	PROPERTY_ENTRY_U32("touchscreen-size-x", 1728),
@@ -1409,6 +1425,15 @@ const struct dmi_system_id touchscreen_dmi_table[] = { · 633 unmodified lines
1409	1425	DMI_EXACT_MATCH(DMI_BOARD_NAME, "0E57"),
1410	1426	},
1411	1427	},
	1428	+ {
	1429	+ /* RCA Cambio W101 v2 */
	1430	+ /* https://github.com/onitake/gsl-firmware/discussions/193 */
	1431	+ .driver_data = (void *)&rca_cambio_w101_v2_data,
	1432	+ .matches = {
	1433	+ DMI_MATCH(DMI_SYS_VENDOR, "RCA"),
	1434	+ DMI_MATCH(DMI_PRODUCT_NAME, "W101SA23T1"),
	1435	+ },
	1436	+ },
1412	1437	{
1413	1438	/* RWC NANOTE P8 */
1414	1439	.driver_data = (void *)&rwc_nanote_p8_data,

drivers/s390/crypto/zcrypt_msgtype6.c+15−6

@@ -342,7 +342,10 @@ static int xcrb_msg_to_type6cprb_msgx(bool userspace, struct ap_message *ap_msg, · 341 unmodified lines
342	342	};
343	343	struct {
344	344	struct type6_hdr hdr;
345		− struct CPRBX cprbx;
	345	+ union {
	346	+ struct CPRBX cprbx;
	347	+ DECLARE_FLEX_ARRAY(u8, userdata);
	348	+ };
346	349	} __packed * msg = ap_msg->msg;
347	350
348	351	int rcblen = CEIL4(xcrb->request_control_blk_length);
@@ -403,7 +406,8 @@ static int xcrb_msg_to_type6cprb_msgx(bool userspace, struct ap_message *ap_msg, · 54 unmodified lines
403	406	msg->hdr.fromcardlen2 = xcrb->reply_data_length;
404	407
405	408	/* prepare CPRB */
406		− if (z_copy_from_user(userspace, &msg->cprbx, xcrb->request_control_blk_addr,
	409	+ if (z_copy_from_user(userspace, msg->userdata,
	410	+ xcrb->request_control_blk_addr,
407	411	xcrb->request_control_blk_length))
408	412	return -EFAULT;
409	413	if (msg->cprbx.cprb_len + sizeof(msg->hdr.function_code) >
@@ -469,9 +473,14 @@ static int xcrb_msg_to_type6_ep11cprb_msgx(bool userspace, struct ap_message *ap · 59 unmodified lines
469	473
470	474	struct {
471	475	struct type6_hdr hdr;
472		− struct ep11_cprb cprbx;
473		− unsigned char pld_tag; /* fixed value 0x30 */
474		− unsigned char pld_lenfmt; /* payload length format */
	476	+ union {
	477	+ struct {
	478	+ struct ep11_cprb cprbx;
	479	+ unsigned char pld_tag; /* fixed value 0x30 */
	480	+ unsigned char pld_lenfmt; /* length format */
	481	+ } __packed;
	482	+ DECLARE_FLEX_ARRAY(u8, userdata);
	483	+ };
475	484	} __packed * msg = ap_msg->msg;
476	485
477	486	struct pld_hdr {
@@ -500,7 +509,7 @@ static int xcrb_msg_to_type6_ep11cprb_msgx(bool userspace, struct ap_message *ap · 22 unmodified lines
500	509	msg->hdr.fromcardlen1 = xcrb->resp_len;
501	510
502	511	/* Import CPRB data from the ioctl input parameter */
503		− if (z_copy_from_user(userspace, &msg->cprbx.cprb_len,
	512	+ if (z_copy_from_user(userspace, msg->userdata,
504	513	(char __force __user *)xcrb->req, xcrb->req_len)) {
505	514	return -EFAULT;
506	515	}

drivers/scsi/ibmvscsi/ibmvfc.c+11−3

@@ -708,8 +708,13 @@ static void ibmvfc_init_host(struct ibmvfc_host *vhost) · 707 unmodified lines
708	708	memset(vhost->async_crq.msgs.async, 0, PAGE_SIZE);
709	709	vhost->async_crq.cur = 0;
710	710
711		− list_for_each_entry(tgt, &vhost->targets, queue)
712		− ibmvfc_del_tgt(tgt);
	711	+ list_for_each_entry(tgt, &vhost->targets, queue) {
	712	+ if (vhost->client_migrated)
	713	+ tgt->need_login = 1;
	714	+ else
	715	+ ibmvfc_del_tgt(tgt);
	716	+ }
	717	+
713	718	scsi_block_requests(vhost->host);
714	719	ibmvfc_set_host_action(vhost, IBMVFC_HOST_ACTION_INIT);
715	720	vhost->job_step = ibmvfc_npiv_login;
@@ -3235,9 +3240,12 @@ static void ibmvfc_handle_crq(struct ibmvfc_crq crq, struct ibmvfc_host vhost, · 2519 unmodified lines
3235	3240	/* We need to re-setup the interpartition connection */
3236	3241	dev_info(vhost->dev, "Partition migrated, Re-enabling adapter\n");
3237	3242	vhost->client_migrated = 1;
	3243	+
	3244	+ scsi_block_requests(vhost->host);
3238	3245	ibmvfc_purge_requests(vhost, DID_REQUEUE);
3239		− ibmvfc_link_down(vhost, IBMVFC_LINK_DOWN);
	3246	+ ibmvfc_set_host_state(vhost, IBMVFC_LINK_DOWN);
3240	3247	ibmvfc_set_host_action(vhost, IBMVFC_HOST_ACTION_REENABLE);
	3248	+ wake_up(&vhost->work_wait_q);
3241	3249	} else if (crq->format == IBMVFC_PARTNER_FAILED \|\| crq->format == IBMVFC_PARTNER_DEREGISTER) {
3242	3250	dev_err(vhost->dev, "Host partner adapter deregistered or failed (rc=%d)\n", crq->format);
3243	3251	ibmvfc_purge_requests(vhost, DID_ERROR);

drivers/scsi/scsi_debug.c+7−0

@@ -1899,6 +1899,13 @@ static int resp_readcap16(struct scsi_cmnd *scp, · 1898 unmodified lines
1899	1899	arr[14] \|= 0x40;
1900	1900	}
1901	1901
	1902	+ /*
	1903	+ * Since the scsi_debug READ CAPACITY implementation always reports the
	1904	+ * total disk capacity, set RC BASIS = 1 for host-managed ZBC devices.
	1905	+ */
	1906	+ if (devip->zmodel == BLK_ZONED_HM)
	1907	+ arr[12] \|= 1 << 4;
	1908	+
1902	1909	arr[15] = sdebug_lowest_aligned & 0xff;
1903	1910
1904	1911	if (have_dif_prot) {

drivers/scsi/scsi_transport_sas.c+9−4

@@ -722,12 +722,17 @@ int sas_phy_add(struct sas_phy *phy) · 721 unmodified lines
722	722	int error;
723	723
724	724	error = device_add(&phy->dev);
725		− if (!error) {
726		− transport_add_device(&phy->dev);
727		− transport_configure_device(&phy->dev);
	725	+ if (error)
	726	+ return error;
	727	+
	728	+ error = transport_add_device(&phy->dev);
	729	+ if (error) {
	730	+ device_del(&phy->dev);
	731	+ return error;
728	732	}
	733	+ transport_configure_device(&phy->dev);
729	734
730		− return error;
	735	+ return 0;
731	736	}
732	737	EXPORT_SYMBOL(sas_phy_add);
733	738

drivers/soundwire/intel.c+1−0

@@ -1513,6 +1513,7 @@ static int intel_link_probe(struct auxiliary_device *auxdev, · 1512 unmodified lines
1513	1513
1514	1514	bus->link_id = auxdev->id;
1515	1515	bus->dev_num_ida_min = INTEL_DEV_NUM_IDA_MIN;
	1516	+ bus->clk_stop_timeout = 1;
1516	1517
1517	1518	sdw_cdns_probe(cdns);
1518	1519

drivers/soundwire/qcom.c+9−0

@@ -344,6 +344,9 @@ static int qcom_swrm_cmd_fifo_wr_cmd(struct qcom_swrm_ctrl *swrm, u8 cmd_data, · 343 unmodified lines
344	344	if (swrm_wait_for_wr_fifo_avail(swrm))
345	345	return SDW_CMD_FAIL_OTHER;
346	346
	347	+ if (cmd_id == SWR_BROADCAST_CMD_ID)
	348	+ reinit_completion(&swrm->broadcast);
	349	+
347	350	/* Its assumed that write is okay as we do not get any status back */
348	351	swrm->reg_write(swrm, SWRM_CMD_FIFO_WR_CMD, val);
349	352
@@ -377,6 +380,12 @@ static int qcom_swrm_cmd_fifo_rd_cmd(struct qcom_swrm_ctrl *swrm, · 27 unmodified lines
377	380
378	381	val = swrm_get_packed_reg_val(&swrm->rcmd_id, len, dev_addr, reg_addr);
379	382
	383	+ /*
	384	+ * Check for outstanding cmd wrt. write fifo depth to avoid
	385	+ * overflow as read will also increase write fifo cnt.
	386	+ */
	387	+ swrm_wait_for_wr_fifo_avail(swrm);
	388	+
380	389	/* wait for FIFO RD to complete to avoid overflow */
381	390	usleep_range(100, 105);
382	391	swrm->reg_write(swrm, SWRM_CMD_FIFO_RD_CMD, val);

drivers/spi/spi-amd.c+1−1

@@ -65,7 +65,7 @@ enum amd_spi_speed { · 64 unmodified lines
65	65	F_16_66MHz,
66	66	F_100MHz,
67	67	F_800KHz,
68		− SPI_SPD7,
	68	+ SPI_SPD7 = 0x7,
69	69	F_50MHz = 0x4,
70	70	F_4MHz = 0x32,
71	71	F_3_17MHz = 0x3F

drivers/spi/spi-intel.c+4−4

@@ -52,17 +52,17 @@ · 51 unmodified lines
52	52	#define FRACC 0x50
53	53
54	54	#define FREG(n) (0x54 + ((n) * 4))
55		−#define FREG_BASE_MASK 0x3fff
	55	+#define FREG_BASE_MASK GENMASK(14, 0)
56	56	#define FREG_LIMIT_SHIFT 16
57		−#define FREG_LIMIT_MASK (0x03fff << FREG_LIMIT_SHIFT)
	57	+#define FREG_LIMIT_MASK GENMASK(30, 16)
58	58
59	59	/* Offset is from @ispi->pregs */
60	60	#define PR(n) ((n) * 4)
61	61	#define PR_WPE BIT(31)
62	62	#define PR_LIMIT_SHIFT 16
63		−#define PR_LIMIT_MASK (0x3fff << PR_LIMIT_SHIFT)
	63	+#define PR_LIMIT_MASK GENMASK(30, 16)
64	64	#define PR_RPE BIT(15)
65		−#define PR_BASE_MASK 0x3fff
	65	+#define PR_BASE_MASK GENMASK(14, 0)
66	66
67	67	/* Offsets are from @ispi->sregs */
68	68	#define SSFSTS_CTL 0x00

drivers/spi/spi-meson-spicc.c+22−2

@@ -160,6 +160,7 @@ struct meson_spicc_device { · 159 unmodified lines
160	160	struct clk *clk;
161	161	struct spi_message *message;
162	162	struct spi_transfer *xfer;
	163	+ struct completion done;
163	164	const struct meson_spicc_data *data;
164	165	u8 *tx_buf;
165	166	u8 *rx_buf;
@@ -282,7 +283,7 @@ static irqreturn_t meson_spicc_irq(int irq, void *data) · 116 unmodified lines
282	283	/* Disable all IRQs */
283	284	writel(0, spicc->base + SPICC_INTREG);
284	285
285		− spi_finalize_current_transfer(spicc->master);
	286	+ complete(&spicc->done);
286	287
287	288	return IRQ_HANDLED;
288	289	}
@@ -386,6 +387,7 @@ static int meson_spicc_transfer_one(struct spi_master *master, · 97 unmodified lines
386	387	struct spi_transfer *xfer)
387	388	{
388	389	struct meson_spicc_device *spicc = spi_master_get_devdata(master);
	390	+ uint64_t timeout;
389	391
390	392	/* Store current transfer */
391	393	spicc->xfer = xfer;
@@ -410,13 +412,29 @@ static int meson_spicc_transfer_one(struct spi_master *master, · 18 unmodified lines
410	412	/* Setup burst */
411	413	meson_spicc_setup_burst(spicc);
412	414
	415	+ /* Setup wait for completion */
	416	+ reinit_completion(&spicc->done);
	417	+
	418	+ /* For each byte we wait for 8 cycles of the SPI clock */
	419	+ timeout = 8LL * MSEC_PER_SEC * xfer->len;
	420	+ do_div(timeout, xfer->speed_hz);
	421	+
	422	+ /* Add 10us delay between each fifo bursts */
	423	+ timeout += ((xfer->len >> 4) * 10) / MSEC_PER_SEC;
	424	+
	425	+ /* Increase it twice and add 200 ms tolerance */
	426	+ timeout += timeout + 200;
	427	+
413	428	/* Start burst */
414	429	writel_bits_relaxed(SPICC_XCH, SPICC_XCH, spicc->base + SPICC_CONREG);
415	430
416	431	/* Enable interrupts */
417	432	writel_relaxed(SPICC_TC_EN, spicc->base + SPICC_INTREG);
418	433
419		− return 1;
	434	+ if (!wait_for_completion_timeout(&spicc->done, msecs_to_jiffies(timeout)))
	435	+ return -ETIMEDOUT;
	436	+
	437	+ return 0;
420	438	}
421	439
422	440	static int meson_spicc_prepare_message(struct spi_master *master,
@@ -743,6 +761,8 @@ static int meson_spicc_probe(struct platform_device *pdev) · 320 unmodified lines
743	761	spicc->pdev = pdev;
744	762	platform_set_drvdata(pdev, spicc);
745	763
	764	+ init_completion(&spicc->done);
	765	+
746	766	spicc->base = devm_platform_ioremap_resource(pdev, 0);
747	767	if (IS_ERR(spicc->base)) {
748	768	dev_err(&pdev->dev, "io resource mapping failed\n");

drivers/spi/spi-mt65xx.c+13−10

@@ -551,14 +551,17 @@ static void mtk_spi_enable_transfer(struct spi_master *master) · 550 unmodified lines
551	551	writel(cmd, mdata->base + SPI_CMD_REG);
552	552	}
553	553
554		−static int mtk_spi_get_mult_delta(u32 xfer_len)
	554	+static int mtk_spi_get_mult_delta(struct mtk_spi *mdata, u32 xfer_len)
555	555	{
556		− u32 mult_delta;
	556	+ u32 mult_delta = 0;
557	557
558		− if (xfer_len > MTK_SPI_PACKET_SIZE)
559		− mult_delta = xfer_len % MTK_SPI_PACKET_SIZE;
560		− else
561		− mult_delta = 0;
	558	+ if (mdata->dev_comp->ipm_design) {
	559	+ if (xfer_len > MTK_SPI_IPM_PACKET_SIZE)
	560	+ mult_delta = xfer_len % MTK_SPI_IPM_PACKET_SIZE;
	561	+ } else {
	562	+ if (xfer_len > MTK_SPI_PACKET_SIZE)
	563	+ mult_delta = xfer_len % MTK_SPI_PACKET_SIZE;
	564	+ }
562	565
563	566	return mult_delta;
564	567	}
@@ -570,22 +573,22 @@ static void mtk_spi_update_mdata_len(struct spi_master *master) · 5 unmodified lines
570	573
571	574	if (mdata->tx_sgl_len && mdata->rx_sgl_len) {
572	575	if (mdata->tx_sgl_len > mdata->rx_sgl_len) {
573		− mult_delta = mtk_spi_get_mult_delta(mdata->rx_sgl_len);
	576	+ mult_delta = mtk_spi_get_mult_delta(mdata, mdata->rx_sgl_len);
574	577	mdata->xfer_len = mdata->rx_sgl_len - mult_delta;
575	578	mdata->rx_sgl_len = mult_delta;
576	579	mdata->tx_sgl_len -= mdata->xfer_len;
577	580	} else {
578		− mult_delta = mtk_spi_get_mult_delta(mdata->tx_sgl_len);
	581	+ mult_delta = mtk_spi_get_mult_delta(mdata, mdata->tx_sgl_len);
579	582	mdata->xfer_len = mdata->tx_sgl_len - mult_delta;
580	583	mdata->tx_sgl_len = mult_delta;
581	584	mdata->rx_sgl_len -= mdata->xfer_len;
582	585	}
583	586	} else if (mdata->tx_sgl_len) {
584		− mult_delta = mtk_spi_get_mult_delta(mdata->tx_sgl_len);
	587	+ mult_delta = mtk_spi_get_mult_delta(mdata, mdata->tx_sgl_len);
585	588	mdata->xfer_len = mdata->tx_sgl_len - mult_delta;
586	589	mdata->tx_sgl_len = mult_delta;
587	590	} else if (mdata->rx_sgl_len) {
588		− mult_delta = mtk_spi_get_mult_delta(mdata->rx_sgl_len);
	591	+ mult_delta = mtk_spi_get_mult_delta(mdata, mdata->rx_sgl_len);
589	592	mdata->xfer_len = mdata->rx_sgl_len - mult_delta;
590	593	mdata->rx_sgl_len = mult_delta;
591	594	}

drivers/spi/spi-stm32.c+2−1

@@ -434,7 +434,7 @@ static int stm32_spi_prepare_mbr(struct stm32_spi *spi, u32 speed_hz, · 433 unmodified lines
434	434	u32 div, mbrdiv;
435	435
436	436	/* Ensure spi->clk_rate is even */
437		− div = DIV_ROUND_UP(spi->clk_rate & ~0x1, speed_hz);
	437	+ div = DIV_ROUND_CLOSEST(spi->clk_rate & ~0x1, speed_hz);
438	438
439	439	/*
440	440	* SPI framework set xfer->speed_hz to master->max_speed_hz if
@@ -886,6 +886,7 @@ static irqreturn_t stm32h7_spi_irq_thread(int irq, void *dev_id) · 445 unmodified lines
886	886	static DEFINE_RATELIMIT_STATE(rs,
887	887	DEFAULT_RATELIMIT_INTERVAL * 10,
888	888	1);
	889	+ ratelimit_set_flags(&rs, RATELIMIT_MSG_ON_RELEASE);
889	890	if (__ratelimit(&rs))
890	891	dev_dbg_ratelimited(spi->dev, "Communication suspended\n");
891	892	if (!spi->cur_usedma && (spi->rx_buf && (spi->rx_len > 0)))

drivers/spi/spi-tegra210-quad.c+6−0

@@ -720,6 +720,9 @@ static int tegra_qspi_start_cpu_based_transfer(struct tegra_qspi *qspi, struct s · 719 unmodified lines
720	720
721	721	static void tegra_qspi_deinit_dma(struct tegra_qspi *tqspi)
722	722	{
	723	+ if (!tqspi->soc_data->has_dma)
	724	+ return;
	725	+
723	726	if (tqspi->tx_dma_buf) {
724	727	dma_free_coherent(tqspi->dev, tqspi->dma_buf_size,
725	728	tqspi->tx_dma_buf, tqspi->tx_dma_phys);
@@ -750,6 +753,9 @@ static int tegra_qspi_init_dma(struct tegra_qspi *tqspi) · 24 unmodified lines
750	753	u32 *dma_buf;
751	754	int err;
752	755
	756	+ if (!tqspi->soc_data->has_dma)
	757	+ return 0;
	758	+
753	759	dma_chan = dma_request_chan(tqspi->dev, "rx");
754	760	if (IS_ERR(dma_chan)) {
755	761	err = PTR_ERR(dma_chan);

fs/btrfs/compression.c+8−6

@@ -512,7 +512,7 @@ static u64 bio_end_offset(struct bio *bio) · 511 unmodified lines
512	512	static noinline int add_ra_bio_pages(struct inode *inode,
513	513	u64 compressed_end,
514	514	struct compressed_bio *cb,
515		− unsigned long *pflags)
	515	+ int memstall, unsigned long pflags)
516	516	{
517	517	struct btrfs_fs_info *fs_info = btrfs_sb(inode->i_sb);
518	518	unsigned long end_index;
@@ -581,8 +581,10 @@ static noinline int add_ra_bio_pages(struct inode *inode, · 62 unmodified lines
581	581	continue;
582	582	}
583	583
584		− if (PageWorkingset(page))
	584	+ if (!*memstall && PageWorkingset(page)) {
585	585	psi_memstall_enter(pflags);
	586	+ *memstall = 1;
	587	+ }
586	588
587	589	ret = set_page_extent_mapped(page);
588	590	if (ret < 0) {
@@ -670,8 +672,8 @@ void btrfs_submit_compressed_read(struct inode inode, struct bio bio, · 81 unmodified lines
670	672	u64 em_len;
671	673	u64 em_start;
672	674	struct extent_map *em;
673		− /* Initialize to 1 to make skip psi_memstall_leave unless needed */
674		− unsigned long pflags = 1;
	675	+ unsigned long pflags;
	676	+ int memstall = 0;
675	677	blk_status_t ret;
676	678	int ret2;
677	679	int i;
@@ -727,7 +729,7 @@ void btrfs_submit_compressed_read(struct inode inode, struct bio bio, · 49 unmodified lines
727	729	goto fail;
728	730	}
729	731
730		− add_ra_bio_pages(inode, em_start + em_len, cb, &pflags);
	732	+ add_ra_bio_pages(inode, em_start + em_len, cb, &memstall, &pflags);
731	733
732	734	/* include any pages we added in add_ra-bio_pages */
733	735	cb->len = bio->bi_iter.bi_size;
@@ -807,7 +809,7 @@ void btrfs_submit_compressed_read(struct inode inode, struct bio bio, · 73 unmodified lines
807	809	}
808	810	}
809	811
810		− if (!pflags)
	812	+ if (memstall)
811	813	psi_memstall_leave(&pflags);
812	814
813	815	if (refcount_dec_and_test(&cb->pending_ios))

fs/btrfs/ctree.c+16−0

@@ -113,6 +113,22 @@ noinline void btrfs_release_path(struct btrfs_path *p) · 112 unmodified lines
113	113	}
114	114	}
115	115
	116	+/*
	117	+ * We want the transaction abort to print stack trace only for errors where the
	118	+ * cause could be a bug, eg. due to ENOSPC, and not for common errors that are
	119	+ * caused by external factors.
	120	+ */
	121	+bool __cold abort_should_print_stack(int errno)
	122	+{
	123	+ switch (errno) {
	124	+ case -EIO:
	125	+ case -EROFS:
	126	+ case -ENOMEM:
	127	+ return false;
	128	+ }
	129	+ return true;
	130	+}
	131	+
116	132	/*
117	133	* safely gets a reference on the root node of a tree. A lock
118	134	* is not taken, so a concurrent writer may put a different node

fs/btrfs/ctree.h+7−4

@@ -3796,9 +3796,11 @@ void __btrfs_abort_transaction(struct btrfs_trans_handle *trans, · 3795 unmodified lines
3796	3796	const char *function,
3797	3797	unsigned int line, int errno, bool first_hit);
3798	3798
	3799	+bool __cold abort_should_print_stack(int errno);
	3800	+
3799	3801	/*
3800	3802	* Call btrfs_abort_transaction as early as possible when an error condition is
3801		− * detected, that way the exact line number is reported.
	3803	+ * detected, that way the exact stack trace is reported for some errors.
3802	3804	*/
3803	3805	#define btrfs_abort_transaction(trans, errno) \
3804	3806	do { \
@@ -3807,10 +3809,11 @@ do { \ · 2 unmodified lines
3807	3809	if (!test_and_set_bit(BTRFS_FS_STATE_TRANS_ABORTED, \
3808	3810	&((trans)->fs_info->fs_state))) { \
3809	3811	first = true; \
3810		− if ((errno) != -EIO && (errno) != -EROFS) { \
3811		− WARN(1, KERN_DEBUG \
	3812	+ if (WARN(abort_should_print_stack(errno), \
	3813	+ KERN_DEBUG \
3812	3814	"BTRFS: Transaction aborted (error %d)\n", \
3813		− (errno)); \
	3815	+ (errno))) { \
	3816	+ /* Stack trace printed. */ \
3814	3817	} else { \
3815	3818	btrfs_debug((trans)->fs_info, \
3816	3819	"Transaction aborted (error %d)", \

fs/btrfs/disk-io.c+3−1

@@ -2551,7 +2551,9 @@ static int btrfs_read_roots(struct btrfs_fs_info *fs_info) · 2550 unmodified lines
2551	2551	fs_info->dev_root = root;
2552	2552	}
2553	2553	/* Initialize fs_info for all devices in any case */
2554		− btrfs_init_devices_late(fs_info);
	2554	+ ret = btrfs_init_devices_late(fs_info);
	2555	+ if (ret)
	2556	+ goto out;
2555	2557
2556	2558	/*
2557	2559	* This tree can share blocks with some other fs tree during relocation

fs/btrfs/scrub.c+1−8

@@ -2672,17 +2672,11 @@ static int scrub_extent(struct scrub_ctx sctx, struct map_lookup map, · 2671 unmodified lines
2672	2672	u8 csum[BTRFS_CSUM_SIZE];
2673	2673	u32 blocksize;
2674	2674
2675		− /*
2676		− * Block size determines how many scrub_block will be allocated. Here
2677		− * we use BTRFS_STRIPE_LEN (64KiB) as default limit, so we won't
2678		− * allocate too many scrub_block, while still won't cause too large
2679		− * bios for large extents.
2680		− */
2681	2675	if (flags & BTRFS_EXTENT_FLAG_DATA) {
2682	2676	if (map->type & BTRFS_BLOCK_GROUP_RAID56_MASK)
2683	2677	blocksize = map->stripe_len;
2684	2678	else
2685		− blocksize = BTRFS_STRIPE_LEN;
	2679	+ blocksize = sctx->fs_info->sectorsize;
2686	2680	spin_lock(&sctx->stat_lock);
2687	2681	sctx->stat.data_extents_scrubbed++;
2688	2682	sctx->stat.data_bytes_scrubbed += len;
@@ -3917,7 +3911,6 @@ int scrub_enumerate_chunks(struct scrub_ctx *sctx, · 1228 unmodified lines
3917	3911
3918	3912	if (sctx->is_dev_replace && btrfs_is_zoned(fs_info)) {
3919	3913	if (!test_bit(BLOCK_GROUP_FLAG_TO_COPY, &cache->runtime_flags)) {
3920		− spin_unlock(&cache->lock);
3921	3914	btrfs_put_block_group(cache);
3922	3915	goto skip;
3923	3916	}

fs/btrfs/tests/btrfs-tests.c+1−1

@@ -200,7 +200,7 @@ void btrfs_free_dummy_fs_info(struct btrfs_fs_info *fs_info) · 199 unmodified lines
200	200
201	201	void btrfs_free_dummy_root(struct btrfs_root *root)
202	202	{
203		− if (!root)
	203	+ if (IS_ERR_OR_NULL(root))
204	204	return;
205	205	/* Will be freed by btrfs_free_fs_roots */
206	206	if (WARN_ON(test_bit(BTRFS_ROOT_IN_RADIX, &root->state)))

fs/btrfs/volumes.c+29−10

@@ -1011,6 +1011,18 @@ static struct btrfs_fs_devices clone_fs_devices(struct btrfs_fs_devices orig) · 1010 unmodified lines
1011	1011	rcu_assign_pointer(device->name, name);
1012	1012	}
1013	1013
	1014	+ if (orig_dev->zone_info) {
	1015	+ struct btrfs_zoned_device_info *zone_info;
	1016	+
	1017	+ zone_info = btrfs_clone_dev_zone_info(orig_dev);
	1018	+ if (!zone_info) {
	1019	+ btrfs_free_device(device);
	1020	+ ret = -ENOMEM;
	1021	+ goto error;
	1022	+ }
	1023	+ device->zone_info = zone_info;
	1024	+ }
	1025	+
1014	1026	list_add(&device->dev_list, &fs_devices->devices);
1015	1027	device->fs_devices = fs_devices;
1016	1028	fs_devices->num_devices++;
@@ -6918,18 +6930,18 @@ static bool dev_args_match_fs_devices(const struct btrfs_dev_lookup_args *args, · 5901 unmodified lines
6918	6930	static bool dev_args_match_device(const struct btrfs_dev_lookup_args *args,
6919	6931	const struct btrfs_device *device)
6920	6932	{
6921		− ASSERT((args->devid != (u64)-1) \|\| args->missing);
	6933	+ if (args->missing) {
	6934	+ if (test_bit(BTRFS_DEV_STATE_IN_FS_METADATA, &device->dev_state) &&
	6935	+ !device->bdev)
	6936	+ return true;
	6937	+ return false;
	6938	+ }
6922	6939
6923		− if ((args->devid != (u64)-1) && device->devid != args->devid)
	6940	+ if (device->devid != args->devid)
6924	6941	return false;
6925	6942	if (args->uuid && memcmp(device->uuid, args->uuid, BTRFS_UUID_SIZE) != 0)
6926	6943	return false;
6927		− if (!args->missing)
6928		− return true;
6929		− if (test_bit(BTRFS_DEV_STATE_IN_FS_METADATA, &device->dev_state) &&
6930		− !device->bdev)
6931		− return true;
6932		− return false;
	6944	+ return true;
6933	6945	}
6934	6946
6935	6947	/*
@@ -7744,10 +7756,11 @@ error: · 808 unmodified lines
7744	7756	return ret;
7745	7757	}
7746	7758
7747		−void btrfs_init_devices_late(struct btrfs_fs_info *fs_info)
	7759	+int btrfs_init_devices_late(struct btrfs_fs_info *fs_info)
7748	7760	{
7749	7761	struct btrfs_fs_devices fs_devices = fs_info->fs_devices, seed_devs;
7750	7762	struct btrfs_device *device;
	7763	+ int ret = 0;
7751	7764
7752	7765	fs_devices->fs_info = fs_info;
7753	7766
@@ -7756,12 +7769,18 @@ void btrfs_init_devices_late(struct btrfs_fs_info *fs_info) · 2 unmodified lines
7756	7769	device->fs_info = fs_info;
7757	7770
7758	7771	list_for_each_entry(seed_devs, &fs_devices->seed_list, seed_list) {
7759		− list_for_each_entry(device, &seed_devs->devices, dev_list)
	7772	+ list_for_each_entry(device, &seed_devs->devices, dev_list) {
7760	7773	device->fs_info = fs_info;
	7774	+ ret = btrfs_get_dev_zone_info(device, false);
	7775	+ if (ret)
	7776	+ break;
	7777	+ }
7761	7778
7762	7779	seed_devs->fs_info = fs_info;
7763	7780	}
7764	7781	mutex_unlock(&fs_devices->device_list_mutex);
	7782	+
	7783	+ return ret;
7765	7784	}
7766	7785
7767	7786	static u64 btrfs_dev_stats_value(const struct extent_buffer *eb,

fs/btrfs/volumes.h+1−1

@@ -671,7 +671,7 @@ int find_free_dev_extent(struct btrfs_device *device, u64 num_bytes, · 670 unmodified lines
671	671	void btrfs_dev_stat_inc_and_print(struct btrfs_device *dev, int index);
672	672	int btrfs_get_dev_stats(struct btrfs_fs_info *fs_info,
673	673	struct btrfs_ioctl_get_dev_stats *stats);
674		−void btrfs_init_devices_late(struct btrfs_fs_info *fs_info);
	674	+int btrfs_init_devices_late(struct btrfs_fs_info *fs_info);
675	675	int btrfs_init_dev_stats(struct btrfs_fs_info *fs_info);
676	676	int btrfs_run_dev_stats(struct btrfs_trans_handle *trans);
677	677	void btrfs_rm_dev_replace_remove_srcdev(struct btrfs_device *srcdev);

fs/btrfs/zoned.c+40−0

@@ -639,6 +639,46 @@ void btrfs_destroy_dev_zone_info(struct btrfs_device *device) · 638 unmodified lines
639	639	device->zone_info = NULL;
640	640	}
641	641
	642	+struct btrfs_zoned_device_info btrfs_clone_dev_zone_info(struct btrfs_device orig_dev)
	643	+{
	644	+ struct btrfs_zoned_device_info *zone_info;
	645	+
	646	+ zone_info = kmemdup(orig_dev->zone_info, sizeof(*zone_info), GFP_KERNEL);
	647	+ if (!zone_info)
	648	+ return NULL;
	649	+
	650	+ zone_info->seq_zones = bitmap_zalloc(zone_info->nr_zones, GFP_KERNEL);
	651	+ if (!zone_info->seq_zones)
	652	+ goto out;
	653	+
	654	+ bitmap_copy(zone_info->seq_zones, orig_dev->zone_info->seq_zones,
	655	+ zone_info->nr_zones);
	656	+
	657	+ zone_info->empty_zones = bitmap_zalloc(zone_info->nr_zones, GFP_KERNEL);
	658	+ if (!zone_info->empty_zones)
	659	+ goto out;
	660	+
	661	+ bitmap_copy(zone_info->empty_zones, orig_dev->zone_info->empty_zones,
	662	+ zone_info->nr_zones);
	663	+
	664	+ zone_info->active_zones = bitmap_zalloc(zone_info->nr_zones, GFP_KERNEL);
	665	+ if (!zone_info->active_zones)
	666	+ goto out;
	667	+
	668	+ bitmap_copy(zone_info->active_zones, orig_dev->zone_info->active_zones,
	669	+ zone_info->nr_zones);
	670	+ zone_info->zone_cache = NULL;
	671	+
	672	+ return zone_info;
	673	+
	674	+out:
	675	+ bitmap_free(zone_info->seq_zones);
	676	+ bitmap_free(zone_info->empty_zones);
	677	+ bitmap_free(zone_info->active_zones);
	678	+ kfree(zone_info);
	679	+ return NULL;
	680	+}
	681	+
642	682	int btrfs_get_dev_zone(struct btrfs_device *device, u64 pos,
643	683	struct blk_zone *zone)
644	684	{

fs/btrfs/zoned.h+11−0

@@ -36,6 +36,7 @@ int btrfs_get_dev_zone(struct btrfs_device *device, u64 pos, · 35 unmodified lines
36	36	int btrfs_get_dev_zone_info_all_devices(struct btrfs_fs_info *fs_info);
37	37	int btrfs_get_dev_zone_info(struct btrfs_device *device, bool populate_cache);
38	38	void btrfs_destroy_dev_zone_info(struct btrfs_device *device);
	39	+struct btrfs_zoned_device_info btrfs_clone_dev_zone_info(struct btrfs_device orig_dev);
39	40	int btrfs_check_zoned_mode(struct btrfs_fs_info *fs_info);
40	41	int btrfs_check_mountopts_zoned(struct btrfs_fs_info *info);
41	42	int btrfs_sb_log_location_bdev(struct block_device *bdev, int mirror, int rw,
@@ -103,6 +104,16 @@ static inline int btrfs_get_dev_zone_info(struct btrfs_device *device, · 61 unmodified lines
103	104
104	105	static inline void btrfs_destroy_dev_zone_info(struct btrfs_device *device) { }
105	106
	107	+/*
	108	+ * In case the kernel is compiled without CONFIG_BLK_DEV_ZONED we'll never call
	109	+ * into btrfs_clone_dev_zone_info() so it's safe to return NULL here.
	110	+ */
	111	+static inline struct btrfs_zoned_device_info *btrfs_clone_dev_zone_info(
	112	+ struct btrfs_device *orig_dev)
	113	+{
	114	+ return NULL;
	115	+}
	116	+
106	117	static inline int btrfs_check_zoned_mode(const struct btrfs_fs_info *fs_info)
107	118	{
108	119	if (!btrfs_is_zoned(fs_info))

fs/erofs/zdata.c+11−7

@@ -1412,8 +1412,8 @@ static void z_erofs_submit_queue(struct z_erofs_decompress_frontend *f, · 1411 unmodified lines
1412	1412	struct block_device *last_bdev;
1413	1413	unsigned int nr_bios = 0;
1414	1414	struct bio *bio = NULL;
1415		− /* initialize to 1 to make skip psi_memstall_leave unless needed */
1416		− unsigned long pflags = 1;
	1415	+ unsigned long pflags;
	1416	+ int memstall = 0;
1417	1417
1418	1418	bi_private = jobqueueset_init(sb, q, fgq, force_fg);
1419	1419	qtail[JQ_BYPASS] = &q[JQ_BYPASS]->head;
@@ -1463,14 +1463,18 @@ static void z_erofs_submit_queue(struct z_erofs_decompress_frontend *f, · 43 unmodified lines
1463	1463	if (bio && (cur != last_index + 1 \|\|
1464	1464	last_bdev != mdev.m_bdev)) {
1465	1465	submit_bio_retry:
1466		− if (!pflags)
1467		− psi_memstall_leave(&pflags);
1468	1466	submit_bio(bio);
	1467	+ if (memstall) {
	1468	+ psi_memstall_leave(&pflags);
	1469	+ memstall = 0;
	1470	+ }
1469	1471	bio = NULL;
1470	1472	}
1471	1473
1472		− if (unlikely(PageWorkingset(page)))
	1474	+ if (unlikely(PageWorkingset(page)) && !memstall) {
1473	1475	psi_memstall_enter(&pflags);
	1476	+ memstall = 1;
	1477	+ }
1474	1478
1475	1479	if (!bio) {
1476	1480	bio = bio_alloc(mdev.m_bdev, BIO_MAX_VECS,
@@ -1500,9 +1504,9 @@ submit_bio_retry: · 23 unmodified lines
1500	1504	} while (owned_head != Z_EROFS_PCLUSTER_TAIL);
1501	1505
1502	1506	if (bio) {
1503		− if (!pflags)
1504		− psi_memstall_leave(&pflags);
1505	1507	submit_bio(bio);
	1508	+ if (memstall)
	1509	+ psi_memstall_leave(&pflags);
1506	1510	}
1507	1511
1508	1512	/*

fs/hugetlbfs/inode.c+6−7

@@ -328,6 +328,12 @@ static ssize_t hugetlbfs_read_iter(struct kiocb iocb, struct iov_iter to) · 327 unmodified lines
328	328	} else {
329	329	unlock_page(page);
330	330
	331	+ if (PageHWPoison(page)) {
	332	+ put_page(page);
	333	+ retval = -EIO;
	334	+ break;
	335	+ }
	336	+
331	337	/*
332	338	* We have the page, copy it to user space buffer.
333	339	*/
@@ -1111,13 +1117,6 @@ static int hugetlbfs_migrate_folio(struct address_space *mapping, · 777 unmodified lines
1111	1117	static int hugetlbfs_error_remove_page(struct address_space *mapping,
1112	1118	struct page *page)
1113	1119	{
1114		− struct inode *inode = mapping->host;
1115		− pgoff_t index = page->index;
1116		−
1117		− hugetlb_delete_from_page_cache(page);
1118		− if (unlikely(hugetlb_unreserve_pages(inode, index, index + 1, 1)))
1119		− hugetlb_fix_reserve_counts(inode);
1120		−
1121	1120	return 0;
1122	1121	}
1123	1122

fs/nfsd/filecache.c+1−0

@@ -1076,6 +1076,7 @@ retry: · 1075 unmodified lines
1076	1076	goto open_file;
1077	1077
1078	1078	nfsd_file_slab_free(&nf->nf_rcu);
	1079	+ nf = NULL;
1079	1080	if (ret == -EEXIST)
1080	1081	goto retry;
1081	1082	trace_nfsd_file_insert_err(rqstp, key.inode, may_flags, ret);

fs/nfsd/nfs4state.c+1−0

@@ -5382,6 +5382,7 @@ nfsd4_verify_deleg_dentry(struct nfsd4_open open, struct nfs4_file fp, · 5381 unmodified lines
5382	5382	if (err)
5383	5383	return -EAGAIN;
5384	5384
	5385	+ exp_put(exp);
5385	5386	dput(child);
5386	5387	if (child != file_dentry(fp->fi_deleg_file->nf_file))
5387	5388	return -EAGAIN;

fs/nilfs2/segment.c+8−7

@@ -317,7 +317,7 @@ void nilfs_relax_pressure_in_lock(struct super_block *sb) · 316 unmodified lines
317	317	struct the_nilfs *nilfs = sb->s_fs_info;
318	318	struct nilfs_sc_info *sci = nilfs->ns_writer;
319	319
320		− if (!sci \|\| !sci->sc_flush_request)
	320	+ if (sb_rdonly(sb) \|\| unlikely(!sci) \|\| !sci->sc_flush_request)
321	321	return;
322	322
323	323	set_bit(NILFS_SC_PRIOR_FLUSH, &sci->sc_flags);
@@ -2242,7 +2242,7 @@ int nilfs_construct_segment(struct super_block *sb) · 1918 unmodified lines
2242	2242	struct nilfs_sc_info *sci = nilfs->ns_writer;
2243	2243	struct nilfs_transaction_info *ti;
2244	2244
2245		− if (!sci)
	2245	+ if (sb_rdonly(sb) \|\| unlikely(!sci))
2246	2246	return -EROFS;
2247	2247
2248	2248	/* A call inside transactions causes a deadlock. */
@@ -2280,7 +2280,7 @@ int nilfs_construct_dsync_segment(struct super_block sb, struct inode inode, · 31 unmodified lines
2280	2280	struct nilfs_transaction_info ti;
2281	2281	int err = 0;
2282	2282
2283		− if (!sci)
	2283	+ if (sb_rdonly(sb) \|\| unlikely(!sci))
2284	2284	return -EROFS;
2285	2285
2286	2286	nilfs_transaction_lock(sb, &ti, 0);
@@ -2776,11 +2776,12 @@ int nilfs_attach_log_writer(struct super_block sb, struct nilfs_root root) · 489 unmodified lines
2776	2776
2777	2777	if (nilfs->ns_writer) {
2778	2778	/*
2779		− * This happens if the filesystem was remounted
2780		− * read/write after nilfs_error degenerated it into a
2781		− * read-only mount.
	2779	+ * This happens if the filesystem is made read-only by
	2780	+ * __nilfs_error or nilfs_remount and then remounted
	2781	+ * read/write. In these cases, reuse the existing
	2782	+ * writer.
2782	2783	*/
2783		− nilfs_detach_log_writer(sb);
	2784	+ return 0;
2784	2785	}
2785	2786
2786	2787	nilfs->ns_writer = nilfs_segctor_new(sb, root);

fs/nilfs2/super.c+0−2

@@ -1133,8 +1133,6 @@ static int nilfs_remount(struct super_block sb, int flags, char *data) · 1132 unmodified lines
1133	1133	if ((bool)(*flags & SB_RDONLY) == sb_rdonly(sb))
1134	1134	goto out;
1135	1135	if (*flags & SB_RDONLY) {
1136		− /* Shutting down log writer */
1137		− nilfs_detach_log_writer(sb);
1138	1136	sb->s_flags \|= SB_RDONLY;
1139	1137
1140	1138	/*

fs/nilfs2/the_nilfs.c+0−2

@@ -690,9 +690,7 @@ int nilfs_count_free_blocks(struct the_nilfs nilfs, sector_t nblocks) · 689 unmodified lines
690	690	{
691	691	unsigned long ncleansegs;
692	692
693		− down_read(&NILFS_MDT(nilfs->ns_dat)->mi_sem);
694	693	ncleansegs = nilfs_sufile_get_ncleansegs(nilfs->ns_sufile);
695		− up_read(&NILFS_MDT(nilfs->ns_dat)->mi_sem);
696	694	nblocks = (sector_t)ncleansegs nilfs->ns_blocks_per_segment;
697	695	return 0;
698	696	}

fs/udf/namei.c+1−1

@@ -240,7 +240,7 @@ static struct fileIdentDesc udf_find_entry(struct inode dir, · 239 unmodified lines
240	240	poffset - lfi);
241	241	else {
242	242	if (!copy_name) {
243		− copy_name = kmalloc(UDF_NAME_LEN,
	243	+ copy_name = kmalloc(UDF_NAME_LEN_CS0,
244	244	GFP_NOFS);
245	245	if (!copy_name) {
246	246	fi = ERR_PTR(-ENOMEM);

fs/userfaultfd.c+3−0

@@ -1630,17 +1630,20 @@ static int userfaultfd_unregister(struct userfaultfd_ctx *ctx, · 1629 unmodified lines
1630	1630	NULL_VM_UFFD_CTX, anon_vma_name(vma));
1631	1631	if (prev) {
1632	1632	vma = prev;
	1633	+ mas_pause(&mas);
1633	1634	goto next;
1634	1635	}
1635	1636	if (vma->vm_start < start) {
1636	1637	ret = split_vma(mm, vma, start, 1);
1637	1638	if (ret)
1638	1639	break;
	1640	+ mas_pause(&mas);
1639	1641	}
1640	1642	if (vma->vm_end > end) {
1641	1643	ret = split_vma(mm, vma, end, 0);
1642	1644	if (ret)
1643	1645	break;
	1646	+ mas_pause(&mas);
1644	1647	}
1645	1648	next:
1646	1649	/*

include/asm-generic/hyperv-tlfs.h+9−0

@@ -102,6 +102,15 @@ struct ms_hyperv_tsc_page { · 101 unmodified lines
102	102	volatile s64 tsc_offset;
103	103	} __packed;
104	104
	105	+union hv_reference_tsc_msr {
	106	+ u64 as_uint64;
	107	+ struct {
	108	+ u64 enable:1;
	109	+ u64 reserved:11;
	110	+ u64 pfn:52;
	111	+ } __packed;
	112	+};
	113	+
105	114	/*
106	115	* The guest OS needs to register the guest ID with the hypervisor.
107	116	* The guest ID is a 64 bit entity and the structure of this ID is

include/asm-generic/vmlinux.lds.h+1−1

@@ -347,6 +347,7 @@ · 346 unmodified lines
347	347	#define DATA_DATA \
348	348	*(.xiptext) \
349	349	*(DATA_MAIN) \
	350	+ *(.data..decrypted) \
350	351	*(.ref.data) \
351	352	(.data..shared_aligned) / percpu related */ \
352	353	MEM_KEEP(init.data*) \
@@ -995,7 +996,6 @@ · 642 unmodified lines
995	996	#ifdef CONFIG_AMD_MEM_ENCRYPT
996	997	#define PERCPU_DECRYPTED_SECTION \
997	998	. = ALIGN(PAGE_SIZE); \
998		− *(.data..decrypted) \
999	999	*(.data..percpu..decrypted) \
1000	1000	. = ALIGN(PAGE_SIZE);
1001	1001	#else

include/linux/can/dev.h+16−0

@@ -152,6 +152,22 @@ static inline bool can_is_canxl_dev_mtu(unsigned int mtu) · 151 unmodified lines
152	152	return (mtu >= CANXL_MIN_MTU && mtu <= CANXL_MAX_MTU);
153	153	}
154	154
	155	+/* drop skb if it does not contain a valid CAN frame for sending */
	156	+static inline bool can_dev_dropped_skb(struct net_device dev, struct sk_buff skb)
	157	+{
	158	+ struct can_priv *priv = netdev_priv(dev);
	159	+
	160	+ if (priv->ctrlmode & CAN_CTRLMODE_LISTENONLY) {
	161	+ netdev_info_once(dev,
	162	+ "interface in listen only mode, dropping skb\n");
	163	+ kfree_skb(skb);
	164	+ dev->stats.tx_dropped++;
	165	+ return true;
	166	+ }
	167	+
	168	+ return can_dropped_invalid_skb(dev, skb);
	169	+}
	170	+
155	171	void can_setup(struct net_device *dev);
156	172
157	173	struct net_device *alloc_candev_mqs(int sizeof_priv, unsigned int echo_skb_max,

include/linux/efi.h+1−0

@@ -389,6 +389,7 @@ void efi_native_runtime_setup(void); · 388 unmodified lines
389	389	#define EFI_LOAD_FILE2_PROTOCOL_GUID EFI_GUID(0x4006c0c1, 0xfcb3, 0x403e, 0x99, 0x6d, 0x4a, 0x6c, 0x87, 0x24, 0xe0, 0x6d)
390	390	#define EFI_RT_PROPERTIES_TABLE_GUID EFI_GUID(0xeb66918a, 0x7eef, 0x402a, 0x84, 0x2e, 0x93, 0x1d, 0x21, 0xc3, 0x8a, 0xe9)
391	391	#define EFI_DXE_SERVICES_TABLE_GUID EFI_GUID(0x05ad34ba, 0x6f02, 0x4214, 0x95, 0x2e, 0x4d, 0xa0, 0x39, 0x8e, 0x2b, 0xb9)
	392	+#define EFI_SMBIOS_PROTOCOL_GUID EFI_GUID(0x03583ff6, 0xcb36, 0x4940, 0x94, 0x7e, 0xb9, 0xb3, 0x9f, 0x4a, 0xfa, 0xf7)
392	393
393	394	#define EFI_IMAGE_SECURITY_DATABASE_GUID EFI_GUID(0xd719b2cb, 0x3d3a, 0x4596, 0xa3, 0xbc, 0xda, 0xd0, 0x0e, 0x67, 0x65, 0x6f)
394	395	#define EFI_SHIM_LOCK_GUID EFI_GUID(0x605dab50, 0xe046, 0x4300, 0xab, 0xb6, 0x3d, 0xd8, 0x10, 0xdd, 0x8b, 0x23)

include/linux/maple_tree.h+7−0

@@ -638,6 +638,12 @@ static inline void mt_set_in_rcu(struct maple_tree *mt) · 637 unmodified lines
638	638	}
639	639	}
640	640
	641	+static inline unsigned int mt_height(const struct maple_tree *mt)
	642	+
	643	+{
	644	+ return (mt->ma_flags & MT_FLAGS_HEIGHT_MASK) >> MT_FLAGS_HEIGHT_OFFSET;
	645	+}
	646	+
641	647	void mt_find(struct maple_tree mt, unsigned long *index, unsigned long max);
642	648	void mt_find_after(struct maple_tree mt, unsigned long *index,
643	649	unsigned long max);
@@ -664,6 +670,7 @@ extern atomic_t maple_tree_tests_passed; · 20 unmodified lines
664	670
665	671	void mt_dump(const struct maple_tree *mt);
666	672	void mt_validate(struct maple_tree *mt);
	673	+void mt_cache_shrink(void);
667	674	#define MT_BUG_ON(__tree, __x) do { \
668	675	atomic_inc(&maple_tree_tests_run); \
669	676	if (__x) { \

include/linux/skmsg.h+1−1

@@ -376,7 +376,7 @@ static inline void sk_psock_report_error(struct sk_psock *psock, int err) · 375 unmodified lines
376	376	}
377	377
378	378	struct sk_psock sk_psock_init(struct sock sk, int node);
379		−void sk_psock_stop(struct sk_psock *psock, bool wait);
	379	+void sk_psock_stop(struct sk_psock *psock);
380	380
381	381	#if IS_ENABLED(CONFIG_BPF_STREAM_PARSER)
382	382	int sk_psock_init_strp(struct sock sk, struct sk_psock psock);

include/linux/slab.h+0−23

@@ -470,35 +470,12 @@ void *__kmalloc_node(size_t size, gfp_t flags, int node) __assume_kmalloc_alignm · 469 unmodified lines
470	470	void kmem_cache_alloc_node(struct kmem_cache s, gfp_t flags, int node) __assume_slab_alignment
471	471	__malloc;
472	472
473		−#ifdef CONFIG_TRACING
474	473	void kmalloc_trace(struct kmem_cache s, gfp_t flags, size_t size)
475	474	__assume_kmalloc_alignment __alloc_size(3);
476	475
477	476	void kmalloc_node_trace(struct kmem_cache s, gfp_t gfpflags,
478	477	int node, size_t size) __assume_kmalloc_alignment
479	478	__alloc_size(4);
480		−#else /* CONFIG_TRACING */
481		−/* Save a function call when CONFIG_TRACING=n */
482		−static __always_inline __alloc_size(3)
483		−void kmalloc_trace(struct kmem_cache s, gfp_t flags, size_t size)
484		−{
485		− void *ret = kmem_cache_alloc(s, flags);
486		−
487		− ret = kasan_kmalloc(s, ret, size, flags);
488		− return ret;
489		−}
490		−
491		−static __always_inline __alloc_size(4)
492		−void kmalloc_node_trace(struct kmem_cache s, gfp_t gfpflags,
493		− int node, size_t size)
494		−{
495		− void *ret = kmem_cache_alloc_node(s, gfpflags, node);
496		−
497		− ret = kasan_kmalloc(s, ret, size, gfpflags);
498		− return ret;
499		−}
500		−#endif /* CONFIG_TRACING */
501		−
502	479	void *kmalloc_large(size_t size, gfp_t flags) __assume_page_alignment
503	480	__alloc_size(1);
504	481

include/uapi/drm/panfrost_drm.h+1−1

@@ -254,7 +254,7 @@ struct panfrost_dump_object_header { · 253 unmodified lines
254	254	__u64 nbos;
255	255	} reghdr;
256	256
257		− struct pan_bomap_hdr {
	257	+ struct {
258	258	__u32 valid;
259	259	__u64 iova;
260	260	__u32 data[2];

include/uapi/linux/audit.h+1−1

@@ -187,7 +187,7 @@ · 186 unmodified lines
187	187	#define AUDIT_MAX_KEY_LEN 256
188	188	#define AUDIT_BITMASK_SIZE 64
189	189	#define AUDIT_WORD(nr) ((__u32)((nr)/32))
190		−#define AUDIT_BIT(nr) (1 << ((nr) - AUDIT_WORD(nr)*32))
	190	+#define AUDIT_BIT(nr) (1U << ((nr) - AUDIT_WORD(nr)*32))
191	191
192	192	#define AUDIT_SYSCALL_CLASSES 16
193	193	#define AUDIT_CLASS_DIR_WRITE 0

include/uapi/linux/capability.h+1−1

@@ -426,7 +426,7 @@ struct vfs_ns_cap_data { · 425 unmodified lines
426	426	*/
427	427
428	428	#define CAP_TO_INDEX(x) ((x) >> 5) /* 1 << 5 == bits in __u32 */
429		−#define CAP_TO_MASK(x) (1 << ((x) & 31)) /* mask for indexed __u32 */
	429	+#define CAP_TO_MASK(x) (1U << ((x) & 31)) /* mask for indexed __u32 */
430	430
431	431
432	432	#endif /* _UAPI_LINUX_CAPABILITY_H */

include/uapi/linux/idxd.h+1−0

@@ -29,6 +29,7 @@ enum idxd_scmd_stat { · 28 unmodified lines
29	29	IDXD_SCMD_WQ_NO_SIZE = 0x800e0000,
30	30	IDXD_SCMD_WQ_NO_PRIV = 0x800f0000,
31	31	IDXD_SCMD_WQ_IRQ_ERR = 0x80100000,
	32	+ IDXD_SCMD_WQ_USER_NO_IOMMU = 0x80110000,
32	33	};
33	34
34	35	#define IDXD_SCMD_SOFTERR_MASK 0x80000000

include/uapi/linux/in.h+1−0

@@ -20,6 +20,7 @@ · 19 unmodified lines
20	20	#define _UAPI_LINUX_IN_H
21	21
22	22	#include <linux/types.h>
	23	+#include <linux/stddef.h>
23	24	#include <linux/libc-compat.h>
24	25	#include <linux/socket.h>
25	26

include/uapi/linux/io_uring.h+1−1

@@ -222,7 +222,7 @@ enum io_uring_op { · 221 unmodified lines
222	222
223	223	/*
224	224	* sqe->uring_cmd_flags
225		− * IORING_URING_CMD_FIXED use registered buffer; pass thig flag
	225	+ * IORING_URING_CMD_FIXED use registered buffer; pass this flag
226	226	* along with setting sqe->buf_index.
227	227	*/
228	228	#define IORING_URING_CMD_FIXED (1U << 0)

io_uring/io_uring.c+8−2

@@ -176,6 +176,11 @@ static inline unsigned int __io_cqring_events(struct io_ring_ctx *ctx) · 175 unmodified lines
176	176	return ctx->cached_cq_tail - READ_ONCE(ctx->rings->cq.head);
177	177	}
178	178
	179	+static inline unsigned int __io_cqring_events_user(struct io_ring_ctx *ctx)
	180	+{
	181	+ return READ_ONCE(ctx->rings->cq.tail) - READ_ONCE(ctx->rings->cq.head);
	182	+}
	183	+
179	184	static bool io_match_linked(struct io_kiocb *head)
180	185	{
181	186	struct io_kiocb *req;
@@ -2315,7 +2320,7 @@ static inline bool io_has_work(struct io_ring_ctx *ctx) · 2133 unmodified lines
2315	2320	static inline bool io_should_wake(struct io_wait_queue *iowq)
2316	2321	{
2317	2322	struct io_ring_ctx *ctx = iowq->ctx;
2318		− int dist = ctx->cached_cq_tail - (int) iowq->cq_tail;
	2323	+ int dist = READ_ONCE(ctx->rings->cq.tail) - (int) iowq->cq_tail;
2319	2324
2320	2325	/*
2321	2326	* Wake up if we have enough events, or if a timeout occurred since we
@@ -2399,7 +2404,8 @@ static int io_cqring_wait(struct io_ring_ctx *ctx, int min_events, · 77 unmodified lines
2399	2404	return ret;
2400	2405	io_cqring_overflow_flush(ctx);
2401	2406
2402		− if (io_cqring_events(ctx) >= min_events)
	2407	+ /* if user messes with these they will just get an early return */
	2408	+ if (__io_cqring_events_user(ctx) >= min_events)
2403	2409	return 0;
2404	2410	} while (ret > 0);
2405	2411

io_uring/kbuf.c+2−0

@@ -346,6 +346,8 @@ int io_provide_buffers_prep(struct io_kiocb req, const struct io_uring_sqe sqe · 345 unmodified lines
346	346	tmp = READ_ONCE(sqe->off);
347	347	if (tmp > USHRT_MAX)
348	348	return -E2BIG;
	349	+ if (tmp + p->nbufs >= USHRT_MAX)
	350	+ return -EINVAL;
349	351	p->bid = tmp;
350	352	return 0;
351	353	}

io_uring/poll.c+19−12

@@ -116,6 +116,8 @@ static void io_poll_req_insert_locked(struct io_kiocb *req) · 115 unmodified lines
116	116	struct io_hash_table *table = &req->ctx->cancel_table_locked;
117	117	u32 index = hash_long(req->cqe.user_data, table->hash_bits);
118	118
	119	+ lockdep_assert_held(&req->ctx->uring_lock);
	120	+
119	121	hlist_add_head(&req->hash_node, &table->hbs[index].list);
120	122	}
121	123
@@ -394,7 +396,8 @@ static int io_poll_wake(struct wait_queue_entry *wait, unsigned mode, int sync, · 272 unmodified lines
394	396	return 1;
395	397	}
396	398
397		−static void io_poll_double_prepare(struct io_kiocb *req)
	399	+/* fails only when polling is already completing by the first entry */
	400	+static bool io_poll_double_prepare(struct io_kiocb *req)
398	401	{
399	402	struct wait_queue_head *head;
400	403	struct io_poll *poll = io_poll_get_single(req);
@@ -403,20 +406,20 @@ static void io_poll_double_prepare(struct io_kiocb *req) · 2 unmodified lines
403	406	rcu_read_lock();
404	407	head = smp_load_acquire(&poll->head);
405	408	/*
406		− * poll arm may not hold ownership and so race with
407		− * io_poll_wake() by modifying req->flags. There is only one
408		− * poll entry queued, serialise with it by taking its head lock.
	409	+ * poll arm might not hold ownership and so race for req->flags with
	410	+ * io_poll_wake(). There is only one poll entry queued, serialise with
	411	+ * it by taking its head lock. As we're still arming the tw hanlder
	412	+ * is not going to be run, so there are no races with it.
409	413	*/
410		− if (head)
	414	+ if (head) {
411	415	spin_lock_irq(&head->lock);
412		−
413		− req->flags \|= REQ_F_DOUBLE_POLL;
414		− if (req->opcode == IORING_OP_POLL_ADD)
415		− req->flags \|= REQ_F_ASYNC_DATA;
416		−
417		− if (head)
	416	+ req->flags \|= REQ_F_DOUBLE_POLL;
	417	+ if (req->opcode == IORING_OP_POLL_ADD)
	418	+ req->flags \|= REQ_F_ASYNC_DATA;
418	419	spin_unlock_irq(&head->lock);
	420	+ }
419	421	rcu_read_unlock();
	422	+ return !!head;
420	423	}
421	424
422	425	static void __io_queue_proc(struct io_poll poll, struct io_poll_table pt,
@@ -454,7 +457,11 @@ static void __io_queue_proc(struct io_poll poll, struct io_poll_table pt, · 31 unmodified lines
454	457	/* mark as double wq entry */
455	458	wqe_private \|= IO_WQE_F_DOUBLE;
456	459	io_init_poll_iocb(poll, first->events, first->wait.func);
457		− io_poll_double_prepare(req);
	460	+ if (!io_poll_double_prepare(req)) {
	461	+ /* the request is completing, just back off */
	462	+ kfree(poll);
	463	+ return;
	464	+ }
458	465	*poll_ptr = poll;
459	466	} else {
460	467	/* fine to modify, there is no poll queued to race with us */

kernel/bpf/verifier.c+13−4

@@ -1027,12 +1027,17 @@ out: · 1026 unmodified lines
1027	1027	*/
1028	1028	static void realloc_array(void arr, size_t old_n, size_t new_n, size_t size)
1029	1029	{
	1030	+ void *new_arr;
	1031	+
1030	1032	if (!new_n \|\| old_n == new_n)
1031	1033	goto out;
1032	1034
1033		− arr = krealloc_array(arr, new_n, size, GFP_KERNEL);
1034		− if (!arr)
	1035	+ new_arr = krealloc_array(arr, new_n, size, GFP_KERNEL);
	1036	+ if (!new_arr) {
	1037	+ kfree(arr);
1035	1038	return NULL;
	1039	+ }
	1040	+ arr = new_arr;
1036	1041
1037	1042	if (new_n > old_n)
1038	1043	memset(arr + old_n * size, 0, (new_n - old_n) * size);
@@ -6618,8 +6623,12 @@ static int release_reference(struct bpf_verifier_env *env, · 5579 unmodified lines
6618	6623	return err;
6619	6624
6620	6625	bpf_for_each_reg_in_vstate(env->cur_state, state, reg, ({
6621		− if (reg->ref_obj_id == ref_obj_id)
6622		− __mark_reg_unknown(env, reg);
	6626	+ if (reg->ref_obj_id == ref_obj_id) {
	6627	+ if (!env->allow_ptr_leaks)
	6628	+ __mark_reg_not_init(env, reg);
	6629	+ else
	6630	+ __mark_reg_unknown(env, reg);
	6631	+ }
6623	6632	}));
6624	6633
6625	6634	return 0;

lib/Kconfig.debug+5−1

@@ -395,12 +395,12 @@ endif # DEBUG_INFO · 394 unmodified lines
395	395	config FRAME_WARN
396	396	int "Warn for stack frames larger than"
397	397	range 0 8192
	398	+ default 0 if KMSAN
398	399	default 2048 if GCC_PLUGIN_LATENT_ENTROPY
399	400	default 2048 if PARISC
400	401	default 1536 if (!64BIT && XTENSA)
401	402	default 1024 if !64BIT
402	403	default 2048 if 64BIT
403		− default 0 if KMSAN
404	404	help
405	405	Tell the compiler to warn at build time for stack frames larger than this.
406	406	Setting this too low will cause a lot of warnings.
@@ -2241,6 +2241,10 @@ config TEST_UUID · 1834 unmodified lines
2241	2241	config TEST_XARRAY
2242	2242	tristate "Test the XArray code at runtime"
2243	2243
	2244	+config TEST_MAPLE_TREE
	2245	+ select DEBUG_MAPLE_TREE
	2246	+ tristate "Test the Maple Tree code at runtime"
	2247	+
2244	2248	config TEST_RHASHTABLE
2245	2249	tristate "Perform selftest on resizable hash table"
2246	2250	help

lib/Kconfig.kmsan+1−0

@@ -12,6 +12,7 @@ config KMSAN · 11 unmodified lines
12	12	bool "KMSAN: detector of uninitialized values use"
13	13	depends on HAVE_ARCH_KMSAN && HAVE_KMSAN_COMPILER
14	14	depends on SLUB && DEBUG_KERNEL && !KASAN && !KCSAN
	15	+ depends on !PREEMPT_RT
15	16	select STACKDEPOT
16	17	select STACKDEPOT_ALWAYS_INIT
17	18	help

lib/Makefile+1−0

@@ -85,6 +85,7 @@ obj-$(CONFIG_TEST_BITMAP) += test_bitmap.o · 84 unmodified lines
85	85	obj-$(CONFIG_TEST_STRSCPY) += test_strscpy.o
86	86	obj-$(CONFIG_TEST_UUID) += test_uuid.o
87	87	obj-$(CONFIG_TEST_XARRAY) += test_xarray.o
	88	+obj-$(CONFIG_TEST_MAPLE_TREE) += test_maple_tree.o
88	89	obj-$(CONFIG_TEST_PARMAN) += test_parman.o
89	90	obj-$(CONFIG_TEST_KMOD) += test_kmod.o
90	91	obj-$(CONFIG_TEST_DEBUG_VIRTUAL) += test_debug_virtual.o

lib/maple_tree.c+40−18

@@ -183,10 +183,6 @@ static void ma_free_rcu(struct maple_node *node) · 182 unmodified lines
183	183	call_rcu(&node->rcu, mt_free_rcu);
184	184	}
185	185
186		−static unsigned int mt_height(const struct maple_tree *mt)
187		−{
188		− return (mt->ma_flags & MT_FLAGS_HEIGHT_MASK) >> MT_FLAGS_HEIGHT_OFFSET;
189		−}
190	186
191	187	static void mas_set_height(struct ma_state *mas)
192	188	{
@@ -1209,7 +1205,6 @@ done: · 1016 unmodified lines
1209	1205	static inline void mas_alloc_nodes(struct ma_state *mas, gfp_t gfp)
1210	1206	{
1211	1207	struct maple_alloc *node;
1212		− struct maple_alloc **nodep = &mas->alloc;
1213	1208	unsigned long allocated = mas_allocated(mas);
1214	1209	unsigned long success = allocated;
1215	1210	unsigned int requested = mas_alloc_req(mas);
@@ -1263,8 +1258,7 @@ static inline void mas_alloc_nodes(struct ma_state *mas, gfp_t gfp) · 47 unmodified lines
1263	1258	node->node_count--;
1264	1259
1265	1260	success += count;
1266		− nodep = &node->slot[0];
1267		− node = *nodep;
	1261	+ node = node->slot[0];
1268	1262	requested -= count;
1269	1263	}
1270	1264	mas->alloc->total = success;
@@ -1357,6 +1351,7 @@ static inline struct maple_enode mas_start(struct ma_state mas) · 86 unmodified lines
1357	1351	root = mas_root(mas);
1358	1352	/* Tree with nodes */
1359	1353	if (likely(xa_is_node(root))) {
	1354	+ mas->depth = 1;
1360	1355	mas->node = mte_safe_root(root);
1361	1356	return NULL;
1362	1357	}
@@ -3608,8 +3603,7 @@ static inline int mas_commit_b_node(struct ma_wr_state *wr_mas, · 2245 unmodified lines
3608	3603	node = mas_pop_node(wr_mas->mas);
3609	3604	node->parent = mas_mn(wr_mas->mas)->parent;
3610	3605	wr_mas->mas->node = mt_mk_node(node, b_type);
3611		− mab_mas_cp(b_node, 0, b_end, wr_mas->mas, true);
3612		−
	3606	+ mab_mas_cp(b_node, 0, b_end, wr_mas->mas, false);
3613	3607	mas_replace(wr_mas->mas, false);
3614	3608	reuse_node:
3615	3609	mas_update_gap(wr_mas->mas);
@@ -3733,7 +3727,6 @@ static bool mas_is_span_wr(struct ma_wr_state *wr_mas) · 117 unmodified lines
3733	3727
3734	3728	static inline void mas_wr_walk_descend(struct ma_wr_state *wr_mas)
3735	3729	{
3736		− wr_mas->mas->depth++;
3737	3730	wr_mas->type = mte_node_type(wr_mas->mas->node);
3738	3731	mas_wr_node_walk(wr_mas);
3739	3732	wr_mas->slots = ma_slots(wr_mas->node, wr_mas->type);
@@ -3745,6 +3738,7 @@ static inline void mas_wr_walk_traverse(struct ma_wr_state *wr_mas) · 5 unmodified lines
3745	3738	wr_mas->mas->min = wr_mas->r_min;
3746	3739	wr_mas->mas->node = wr_mas->content;
3747	3740	wr_mas->mas->offset = 0;
	3741	+ wr_mas->mas->depth++;
3748	3742	}
3749	3743	/*
3750	3744	* mas_wr_walk() - Walk the tree for a write.
@@ -4970,8 +4964,9 @@ static inline bool mas_anode_descend(struct ma_state *mas, unsigned long size) · 1219 unmodified lines
4970	4964	{
4971	4965	enum maple_type type = mte_node_type(mas->node);
4972	4966	unsigned long pivot, min, gap = 0;
4973		− unsigned char count, offset;
4974		− unsigned long gaps = NULL, pivots = ma_pivots(mas_mn(mas), type);
	4967	+ unsigned char offset;
	4968	+ unsigned long *gaps;
	4969	+ unsigned long *pivots = ma_pivots(mas_mn(mas), type);
4975	4970	void __rcu **slots = ma_slots(mas_mn(mas), type);
4976	4971	bool found = false;
4977	4972
@@ -4982,9 +4977,8 @@ static inline bool mas_anode_descend(struct ma_state *mas, unsigned long size) · 4 unmodified lines
4982	4977
4983	4978	gaps = ma_gaps(mte_to_node(mas->node), type);
4984	4979	offset = mas->offset;
4985		− count = mt_slots[type];
4986	4980	min = mas_safe_min(mas, pivots, offset);
4987		− for (; offset < count; offset++) {
	4981	+ for (; offset < mt_slots[type]; offset++) {
4988	4982	pivot = mas_safe_pivot(mas, pivots, offset, type);
4989	4983	if (offset && !pivot)
4990	4984	break;
@@ -5010,8 +5004,6 @@ static inline bool mas_anode_descend(struct ma_state *mas, unsigned long size) · 19 unmodified lines
5010	5004	mas->min = min;
5011	5005	mas->max = pivot;
5012	5006	offset = 0;
5013		− type = mte_node_type(mas->node);
5014		− count = mt_slots[type];
5015	5007	break;
5016	5008	}
5017	5009	}
@@ -5065,6 +5057,7 @@ retry: · 47 unmodified lines
5065	5057
5066	5058	return entry;
5067	5059	}
	5060	+EXPORT_SYMBOL_GPL(mas_walk);
5068	5061
5069	5062	static inline bool mas_rewind_node(struct ma_state *mas)
5070	5063	{
@@ -5276,6 +5269,7 @@ int mas_empty_area(struct ma_state *mas, unsigned long min, · 205 unmodified lines
5276	5269	mas->last = mas->index + size - 1;
5277	5270	return 0;
5278	5271	}
	5272	+EXPORT_SYMBOL_GPL(mas_empty_area);
5279	5273
5280	5274	/*
5281	5275	* mas_empty_area_rev() - Get the highest address within the range that is
@@ -5339,6 +5333,7 @@ int mas_empty_area_rev(struct ma_state *mas, unsigned long min, · 57 unmodified lines
5339	5333	mas->index = mas->last - size + 1;
5340	5334	return 0;
5341	5335	}
	5336	+EXPORT_SYMBOL_GPL(mas_empty_area_rev);
5342	5337
5343	5338	static inline int mas_alloc(struct ma_state mas, void entry,
5344	5339	unsigned long size, unsigned long *index)
@@ -5660,6 +5655,7 @@ void mas_store(struct ma_state mas, void *entry) · 315 unmodified lines
5660	5655	mas_wr_store_entry(&wr_mas);
5661	5656	return wr_mas.content;
5662	5657	}
	5658	+EXPORT_SYMBOL_GPL(mas_store);
5663	5659
5664	5660	/**
5665	5661	* mas_store_gfp() - Store a value into the tree.
@@ -5686,6 +5682,7 @@ retry: · 20 unmodified lines
5686	5682
5687	5683	return 0;
5688	5684	}
	5685	+EXPORT_SYMBOL_GPL(mas_store_gfp);
5689	5686
5690	5687	/**
5691	5688	* mas_store_prealloc() - Store a value into the tree using memory
@@ -5703,6 +5700,7 @@ void mas_store_prealloc(struct ma_state mas, void entry) · 11 unmodified lines
5703	5700	BUG_ON(mas_is_err(mas));
5704	5701	mas_destroy(mas);
5705	5702	}
	5703	+EXPORT_SYMBOL_GPL(mas_store_prealloc);
5706	5704
5707	5705	/**
5708	5706	* mas_preallocate() - Preallocate enough nodes for a store operation
@@ -5772,6 +5770,7 @@ void mas_destroy(struct ma_state *mas) · 63 unmodified lines
5772	5770	}
5773	5771	mas->alloc = NULL;
5774	5772	}
	5773	+EXPORT_SYMBOL_GPL(mas_destroy);
5775	5774
5776	5775	/*
5777	5776	* mas_expected_entries() - Set the expected number of entries that will be inserted.
@@ -5833,6 +5832,7 @@ int mas_expected_entries(struct ma_state *mas, unsigned long nr_entries) · 55 unmodified lines
5833	5832	return ret;
5834	5833
5835	5834	}
	5835	+EXPORT_SYMBOL_GPL(mas_expected_entries);
5836	5836
5837	5837	/**
5838	5838	* mas_next() - Get the next entry.
@@ -6013,6 +6013,7 @@ void mas_find(struct ma_state mas, unsigned long max) · 174 unmodified lines
6013	6013	/* Retries on dead nodes handled by mas_next_entry */
6014	6014	return mas_next_entry(mas, max);
6015	6015	}
	6016	+EXPORT_SYMBOL_GPL(mas_find);
6016	6017
6017	6018	/**
6018	6019	* mas_find_rev: On the first call, find the first non-null entry at or below
@@ -6059,7 +6060,7 @@ void mas_find_rev(struct ma_state mas, unsigned long min) · 40 unmodified lines
6059	6060	/* Retries on dead nodes handled by mas_next_entry */
6060	6061	return mas_prev_entry(mas, min);
6061	6062	}
6062		−EXPORT_SYMBOL_GPL(mas_find);
	6063	+EXPORT_SYMBOL_GPL(mas_find_rev);
6063	6064
6064	6065	/**
6065	6066	* mas_erase() - Find the range in which index resides and erase the entire
@@ -6541,8 +6542,27 @@ static inline int mas_dead_node(struct ma_state *mas, unsigned long index) · 475 unmodified lines
6541	6542	mas_rewalk(mas, index);
6542	6543	return 1;
6543	6544	}
6544		−#endif /* not defined __KERNEL__ */
6545	6545
	6546	+void mt_cache_shrink(void)
	6547	+{
	6548	+}
	6549	+#else
	6550	+/*
	6551	+ * mt_cache_shrink() - For testing, don't use this.
	6552	+ *
	6553	+ * Certain testcases can trigger an OOM when combined with other memory
	6554	+ * debugging configuration options. This function is used to reduce the
	6555	+ * possibility of an out of memory even due to kmem_cache objects remaining
	6556	+ * around for longer than usual.
	6557	+ */
	6558	+void mt_cache_shrink(void)
	6559	+{
	6560	+ kmem_cache_shrink(maple_node_cache);
	6561	+
	6562	+}
	6563	+EXPORT_SYMBOL_GPL(mt_cache_shrink);
	6564	+
	6565	+#endif /* not defined __KERNEL__ */
6546	6566	/*
6547	6567	* mas_get_slot() - Get the entry in the maple state node stored at @offset.
6548	6568	* @mas: The maple state
@@ -6816,6 +6836,7 @@ void mt_dump(const struct maple_tree *mt) · 267 unmodified lines
6816	6836	else if (entry)
6817	6837	mt_dump_node(mt, entry, 0, mt_max[mte_node_type(entry)], 0);
6818	6838	}
	6839	+EXPORT_SYMBOL_GPL(mt_dump);
6819	6840
6820	6841	/*
6821	6842	* Calculate the maximum gap in a node and check if that's what is reported in
@@ -7126,5 +7147,6 @@ done: · 304 unmodified lines
7126	7147	rcu_read_unlock();
7127	7148
7128	7149	}
	7150	+EXPORT_SYMBOL_GPL(mt_validate);
7129	7151
7130	7152	#endif /* CONFIG_DEBUG_MAPLE_TREE */

lib/test_maple_tree.c+1193−36733

@@ -1,24 +1,35 @@
1	1	// SPDX-License-Identifier: GPL-2.0+
2	2	/*
3	3	* test_maple_tree.c: Test the maple tree API
4		− * Copyright (c) 2018 Liam R. Howlett
	4	+ * Copyright (c) 2018-2022 Oracle Corporation
5	5	* Author: Liam R. Howlett <Liam.Howlett@Oracle.com>
	6	+ *
	7	+ * Any tests that only require the interface of the tree.
6	8	*/
7	9
8	10	#include <linux/maple_tree.h>
9	11	#include <linux/module.h>
10		−#include <stdlib.h>
11		−#include <time.h>
12	12
13	13	#define MTREE_ALLOC_MAX 0x2000000000000Ul
	14	+#ifndef CONFIG_DEBUG_MAPLE_TREE
14	15	#define CONFIG_DEBUG_MAPLE_TREE
	16	+#endif
15	17	#define CONFIG_MAPLE_SEARCH
	18	+#define MAPLE_32BIT (MAPLE_NODE_SLOTS > 31)
	19	+
16	20	/* #define BENCH_SLOT_STORE */
17	21	/* #define BENCH_NODE_STORE */
18	22	/* #define BENCH_AWALK */
19	23	/* #define BENCH_WALK */
20	24	/* #define BENCH_MT_FOR_EACH */
21	25	/* #define BENCH_FORK */
	26	+
	27	+#ifdef __KERNEL__
	28	+#define mt_set_non_kernel(x) do {} while (0)
	29	+#define mt_zero_nr_tallocated(x) do {} while (0)
	30	+#else
	31	+#define cond_resched() do {} while (0)
	32	+#endif
22	33	static
23	34	int mtree_insert_index(struct maple_tree *mt, unsigned long index, gfp_t gfp)
24	35	{
@@ -65,6 +76,7 @@ static void mtree_test_erase(struct maple_tree mt, unsigned long index) · 40 unmodified lines
65	76	return mtree_erase(mt, index);
66	77	}
67	78
	79	+#if defined(CONFIG_64BIT)
68	80	static noinline void check_mtree_alloc_range(struct maple_tree *mt,
69	81	unsigned long start, unsigned long end, unsigned long size,
70	82	unsigned long expected, int eret, void *ptr)
@@ -98,6 +110,7 @@ static noinline void check_mtree_alloc_rrange(struct maple_tree *mt, · 27 unmodified lines
98	110
99	111	MT_BUG_ON(mt, result != expected);
100	112	}
	113	+#endif
101	114
102	115	static noinline void check_load(struct maple_tree *mt, unsigned long index,
103	116	void *ptr)
@@ -150,12 +163,6 @@ static noinline void check_insert(struct maple_tree *mt, unsigned long index, · 46 unmodified lines
150	163	MT_BUG_ON(mt, ret != 0);
151	164	}
152	165
153		−static noinline void check_erase(struct maple_tree *mt, unsigned long index,
154		− void *ptr)
155		−{
156		− MT_BUG_ON(mt, mtree_test_erase(mt, index) != ptr);
157		−}
158		−
159	166	static noinline void check_dup_insert(struct maple_tree *mt,
160	167	unsigned long index, void *ptr)
161	168	{
@@ -172,41 +179,6 @@ void check_index_load(struct maple_tree *mt, unsigned long index) · 10 unmodified lines
172	179	return check_load(mt, index, xa_mk_value(index & LONG_MAX));
173	180	}
174	181
175		−static noinline void check_nomem(struct maple_tree *mt)
176		−{
177		− MA_STATE(ms, mt, 1, 1);
178		−
179		− MT_BUG_ON(mt, !mtree_empty(mt));
180		− /* Ensure no bypassing of allocation failures */
181		− mt_set_non_kernel(0);
182		−
183		− /* Storing something at 1 requires memory allocation */
184		− MT_BUG_ON(mt, mtree_insert(mt, 1, &ms, GFP_ATOMIC) != -ENOMEM);
185		− /* Storing something at 0 does not */
186		− MT_BUG_ON(mt, mtree_insert(mt, 0, &ms, GFP_ATOMIC) != 0);
187		−
188		− /*
189		− * Simulate two threads racing; the first one fails to allocate
190		− * memory to insert an entry at 1, then the second one succeeds
191		− * in allocating memory to insert an entry at 2. The first one
192		− * then needs to free the node it allocated. LeakSanitizer will
193		− * notice this, as will the 'nr_allocated' debugging aid in the
194		− * userspace test suite.
195		− */
196		− mtree_lock(mt);
197		− mas_store(&ms, &ms); /* insert 1 -> &ms, fails. */
198		− MT_BUG_ON(mt, ms.node != MA_ERROR(-ENOMEM));
199		− mas_nomem(&ms, GFP_KERNEL); /* Node allocated in here. */
200		− MT_BUG_ON(mt, ms.node != MAS_START);
201		− mtree_unlock(mt);
202		− MT_BUG_ON(mt, mtree_insert(mt, 2, mt, GFP_KERNEL) != 0);
203		− mtree_lock(mt);
204		− mas_store(&ms, &ms); /* insert 1 -> &ms */
205		− mas_nomem(&ms, GFP_KERNEL); /* Node allocated in here. */
206		− mtree_unlock(mt);
207		− mtree_destroy(mt);
208		−}
209		−
210	182	static inline int not_empty(struct maple_node *node)
211	183	{
212	184	int i;
@@ -221,350 +193,6 @@ static inline int not_empty(struct maple_node *node) · 8 unmodified lines
221	193	return 0;
222	194	}
223	195
224		−static noinline void check_new_node(struct maple_tree *mt)
225		−{
226		−
227		− struct maple_node mn, mn2, *mn3;
228		− struct maple_alloc *smn;
229		− struct maple_node *nodes[100];
230		− int i, j, total;
231		−
232		− MA_STATE(mas, mt, 0, 0);
233		−
234		− /* Try allocating 3 nodes */
235		− mtree_lock(mt);
236		− /* request 3 nodes to be allocated. */
237		− mas_node_count(&mas, 3);
238		− /* Allocation request of 3. */
239		− MT_BUG_ON(mt, mas_alloc_req(&mas) != 3);
240		− /* Allocate failed. */
241		− MT_BUG_ON(mt, mas.node != MA_ERROR(-ENOMEM));
242		− MT_BUG_ON(mt, !mas_nomem(&mas, GFP_KERNEL));
243		−
244		− MT_BUG_ON(mt, mas_allocated(&mas) != 3);
245		− mn = mas_pop_node(&mas);
246		− MT_BUG_ON(mt, not_empty(mn));
247		− MT_BUG_ON(mt, mn == NULL);
248		− MT_BUG_ON(mt, mas.alloc == NULL);
249		− MT_BUG_ON(mt, mas.alloc->slot[0] == NULL);
250		− mas_push_node(&mas, mn);
251		− mas_nomem(&mas, GFP_KERNEL); /* free */
252		− mtree_unlock(mt);
253		−
254		−
255		− /* Try allocating 1 node, then 2 more */
256		− mtree_lock(mt);
257		− /* Set allocation request to 1. */
258		− mas_set_alloc_req(&mas, 1);
259		− /* Check Allocation request of 1. */
260		− MT_BUG_ON(mt, mas_alloc_req(&mas) != 1);
261		− mas_set_err(&mas, -ENOMEM);
262		− /* Validate allocation request. */
263		− MT_BUG_ON(mt, !mas_nomem(&mas, GFP_KERNEL));
264		− /* Eat the requested node. */
265		− mn = mas_pop_node(&mas);
266		− MT_BUG_ON(mt, not_empty(mn));
267		− MT_BUG_ON(mt, mn == NULL);
268		− MT_BUG_ON(mt, mn->slot[0] != NULL);
269		− MT_BUG_ON(mt, mn->slot[1] != NULL);
270		− MT_BUG_ON(mt, mas_allocated(&mas) != 0);
271		−
272		− ma_free_rcu(mn);
273		− mas.node = MAS_START;
274		− mas_nomem(&mas, GFP_KERNEL);
275		− /* Allocate 3 nodes, will fail. */
276		− mas_node_count(&mas, 3);
277		− /* Drop the lock and allocate 3 nodes. */
278		− mas_nomem(&mas, GFP_KERNEL);
279		− /* Ensure 3 are allocated. */
280		− MT_BUG_ON(mt, mas_allocated(&mas) != 3);
281		− /* Allocation request of 0. */
282		− MT_BUG_ON(mt, mas_alloc_req(&mas) != 0);
283		−
284		− MT_BUG_ON(mt, mas.alloc == NULL);
285		− MT_BUG_ON(mt, mas.alloc->slot[0] == NULL);
286		− MT_BUG_ON(mt, mas.alloc->slot[1] == NULL);
287		− /* Ensure we counted 3. */
288		− MT_BUG_ON(mt, mas_allocated(&mas) != 3);
289		− /* Free. */
290		− mas_nomem(&mas, GFP_KERNEL);
291		−
292		− /* Set allocation request to 1. */
293		− mas_set_alloc_req(&mas, 1);
294		− MT_BUG_ON(mt, mas_alloc_req(&mas) != 1);
295		− mas_set_err(&mas, -ENOMEM);
296		− /* Validate allocation request. */
297		− MT_BUG_ON(mt, !mas_nomem(&mas, GFP_KERNEL));
298		− MT_BUG_ON(mt, mas_allocated(&mas) != 1);
299		− /* Check the node is only one node. */
300		− mn = mas_pop_node(&mas);
301		− MT_BUG_ON(mt, not_empty(mn));
302		− MT_BUG_ON(mt, mas_allocated(&mas) != 0);
303		− MT_BUG_ON(mt, mn == NULL);
304		− MT_BUG_ON(mt, mn->slot[0] != NULL);
305		− MT_BUG_ON(mt, mn->slot[1] != NULL);
306		− MT_BUG_ON(mt, mas_allocated(&mas) != 0);
307		− mas_push_node(&mas, mn);
308		− MT_BUG_ON(mt, mas_allocated(&mas) != 1);
309		− MT_BUG_ON(mt, mas.alloc->node_count);
310		−
311		− mas_set_alloc_req(&mas, 2); /* request 2 more. */
312		− MT_BUG_ON(mt, mas_alloc_req(&mas) != 2);
313		− mas_set_err(&mas, -ENOMEM);
314		− MT_BUG_ON(mt, !mas_nomem(&mas, GFP_KERNEL));
315		− MT_BUG_ON(mt, mas_allocated(&mas) != 3);
316		− MT_BUG_ON(mt, mas.alloc == NULL);
317		− MT_BUG_ON(mt, mas.alloc->slot[0] == NULL);
318		− MT_BUG_ON(mt, mas.alloc->slot[1] == NULL);
319		− for (i = 2; i >= 0; i--) {
320		− mn = mas_pop_node(&mas);
321		− MT_BUG_ON(mt, mas_allocated(&mas) != i);
322		− MT_BUG_ON(mt, !mn);
323		− MT_BUG_ON(mt, not_empty(mn));
324		− ma_free_rcu(mn);
325		− }
326		−
327		− total = 64;
328		− mas_set_alloc_req(&mas, total); /* request 2 more. */
329		− MT_BUG_ON(mt, mas_alloc_req(&mas) != total);
330		− mas_set_err(&mas, -ENOMEM);
331		− MT_BUG_ON(mt, !mas_nomem(&mas, GFP_KERNEL));
332		− for (i = total; i > 0; i--) {
333		− unsigned int e = 0; /* expected node_count */
334		−
335		− if (i >= 35)
336		− e = i - 35;
337		− else if (i >= 5)
338		− e = i - 5;
339		− else if (i >= 2)
340		− e = i - 2;
341		− MT_BUG_ON(mt, mas.alloc->node_count != e);
342		− mn = mas_pop_node(&mas);
343		− MT_BUG_ON(mt, not_empty(mn));
344		− MT_BUG_ON(mt, mas_allocated(&mas) != i - 1);
345		− MT_BUG_ON(mt, !mn);
346		− ma_free_rcu(mn);
347		− }
348		−
349		− total = 100;
350		− for (i = 1; i < total; i++) {
351		− mas_set_alloc_req(&mas, i);
352		− mas_set_err(&mas, -ENOMEM);
353		− MT_BUG_ON(mt, !mas_nomem(&mas, GFP_KERNEL));
354		− for (j = i; j > 0; j--) {
355		− mn = mas_pop_node(&mas);
356		− MT_BUG_ON(mt, mas_allocated(&mas) != j - 1);
357		− MT_BUG_ON(mt, !mn);
358		− MT_BUG_ON(mt, not_empty(mn));
359		− mas_push_node(&mas, mn);
360		− MT_BUG_ON(mt, mas_allocated(&mas) != j);
361		− mn = mas_pop_node(&mas);
362		− MT_BUG_ON(mt, not_empty(mn));
363		− MT_BUG_ON(mt, mas_allocated(&mas) != j - 1);
364		− ma_free_rcu(mn);
365		− }
366		− MT_BUG_ON(mt, mas_allocated(&mas) != 0);
367		−
368		− mas_set_alloc_req(&mas, i);
369		− mas_set_err(&mas, -ENOMEM);
370		− MT_BUG_ON(mt, !mas_nomem(&mas, GFP_KERNEL));
371		− for (j = 0; j <= i/2; j++) {
372		− MT_BUG_ON(mt, mas_allocated(&mas) != i - j);
373		− nodes[j] = mas_pop_node(&mas);
374		− MT_BUG_ON(mt, mas_allocated(&mas) != i - j - 1);
375		− }
376		−
377		− while (j) {
378		− j--;
379		− mas_push_node(&mas, nodes[j]);
380		− MT_BUG_ON(mt, mas_allocated(&mas) != i - j);
381		− }
382		− MT_BUG_ON(mt, mas_allocated(&mas) != i);
383		− for (j = 0; j <= i/2; j++) {
384		− MT_BUG_ON(mt, mas_allocated(&mas) != i - j);
385		− mn = mas_pop_node(&mas);
386		− MT_BUG_ON(mt, not_empty(mn));
387		− ma_free_rcu(mn);
388		− MT_BUG_ON(mt, mas_allocated(&mas) != i - j - 1);
389		− }
390		− MT_BUG_ON(mt, mas_nomem(&mas, GFP_KERNEL));
391		−
392		− }
393		−
394		− /* Set allocation request. */
395		− total = 500;
396		− mas_node_count(&mas, total);
397		− /* Drop the lock and allocate the nodes. */
398		− mas_nomem(&mas, GFP_KERNEL);
399		− MT_BUG_ON(mt, !mas.alloc);
400		− i = 1;
401		− smn = mas.alloc;
402		− while (i < total) {
403		− for (j = 0; j < MAPLE_ALLOC_SLOTS; j++) {
404		− i++;
405		− MT_BUG_ON(mt, !smn->slot[j]);
406		− if (i == total)
407		− break;
408		− }
409		− smn = smn->slot[0]; /* next. */
410		− }
411		− MT_BUG_ON(mt, mas_allocated(&mas) != total);
412		− mas_nomem(&mas, GFP_KERNEL); /* Free. */
413		−
414		− MT_BUG_ON(mt, mas_allocated(&mas) != 0);
415		− for (i = 1; i < 128; i++) {
416		− mas_node_count(&mas, i); /* Request */
417		− mas_nomem(&mas, GFP_KERNEL); /* Fill request */
418		− MT_BUG_ON(mt, mas_allocated(&mas) != i); /* check request filled */
419		− for (j = i; j > 0; j--) { /Free the requests /
420		− mn = mas_pop_node(&mas); /* get the next node. */
421		− MT_BUG_ON(mt, mn == NULL);
422		− MT_BUG_ON(mt, not_empty(mn));
423		− ma_free_rcu(mn);
424		− }
425		− MT_BUG_ON(mt, mas_allocated(&mas) != 0);
426		− }
427		−
428		− for (i = 1; i < MAPLE_NODE_MASK + 1; i++) {
429		− MA_STATE(mas2, mt, 0, 0);
430		− mas_node_count(&mas, i); /* Request */
431		− mas_nomem(&mas, GFP_KERNEL); /* Fill request */
432		− MT_BUG_ON(mt, mas_allocated(&mas) != i); /* check request filled */
433		− for (j = 1; j <= i; j++) { /* Move the allocations to mas2 */
434		− mn = mas_pop_node(&mas); /* get the next node. */
435		− MT_BUG_ON(mt, mn == NULL);
436		− MT_BUG_ON(mt, not_empty(mn));
437		− mas_push_node(&mas2, mn);
438		− MT_BUG_ON(mt, mas_allocated(&mas2) != j);
439		− }
440		− MT_BUG_ON(mt, mas_allocated(&mas) != 0);
441		− MT_BUG_ON(mt, mas_allocated(&mas2) != i);
442		−
443		− for (j = i; j > 0; j--) { /Free the requests /
444		− MT_BUG_ON(mt, mas_allocated(&mas2) != j);
445		− mn = mas_pop_node(&mas2); /* get the next node. */
446		− MT_BUG_ON(mt, mn == NULL);
447		− MT_BUG_ON(mt, not_empty(mn));
448		− ma_free_rcu(mn);
449		− }
450		− MT_BUG_ON(mt, mas_allocated(&mas2) != 0);
451		− }
452		−
453		−
454		− MT_BUG_ON(mt, mas_allocated(&mas) != 0);
455		− mas_node_count(&mas, MAPLE_ALLOC_SLOTS + 1); /* Request */
456		− MT_BUG_ON(mt, mas.node != MA_ERROR(-ENOMEM));
457		− MT_BUG_ON(mt, !mas_nomem(&mas, GFP_KERNEL));
458		− MT_BUG_ON(mt, mas_allocated(&mas) != MAPLE_ALLOC_SLOTS + 1);
459		− MT_BUG_ON(mt, mas.alloc->node_count != MAPLE_ALLOC_SLOTS - 1);
460		−
461		− mn = mas_pop_node(&mas); /* get the next node. */
462		− MT_BUG_ON(mt, mn == NULL);
463		− MT_BUG_ON(mt, not_empty(mn));
464		− MT_BUG_ON(mt, mas_allocated(&mas) != MAPLE_ALLOC_SLOTS);
465		− MT_BUG_ON(mt, mas.alloc->node_count != MAPLE_ALLOC_SLOTS - 2);
466		−
467		− mas_push_node(&mas, mn);
468		− MT_BUG_ON(mt, mas_allocated(&mas) != MAPLE_ALLOC_SLOTS + 1);
469		− MT_BUG_ON(mt, mas.alloc->node_count != MAPLE_ALLOC_SLOTS - 1);
470		−
471		− /* Check the limit of pop/push/pop */
472		− mas_node_count(&mas, MAPLE_ALLOC_SLOTS + 2); /* Request */
473		− MT_BUG_ON(mt, mas_alloc_req(&mas) != 1);
474		− MT_BUG_ON(mt, mas.node != MA_ERROR(-ENOMEM));
475		− MT_BUG_ON(mt, !mas_nomem(&mas, GFP_KERNEL));
476		− MT_BUG_ON(mt, mas_alloc_req(&mas));
477		− MT_BUG_ON(mt, mas.alloc->node_count);
478		− MT_BUG_ON(mt, mas_allocated(&mas) != MAPLE_ALLOC_SLOTS + 2);
479		− mn = mas_pop_node(&mas);
480		− MT_BUG_ON(mt, not_empty(mn));
481		− MT_BUG_ON(mt, mas_allocated(&mas) != MAPLE_ALLOC_SLOTS + 1);
482		− MT_BUG_ON(mt, mas.alloc->node_count != MAPLE_ALLOC_SLOTS - 1);
483		− mas_push_node(&mas, mn);
484		− MT_BUG_ON(mt, mas.alloc->node_count);
485		− MT_BUG_ON(mt, mas_allocated(&mas) != MAPLE_ALLOC_SLOTS + 2);
486		− mn = mas_pop_node(&mas);
487		− MT_BUG_ON(mt, not_empty(mn));
488		− ma_free_rcu(mn);
489		− for (i = 1; i <= MAPLE_ALLOC_SLOTS + 1; i++) {
490		− mn = mas_pop_node(&mas);
491		− MT_BUG_ON(mt, not_empty(mn));
492		− ma_free_rcu(mn);
493		− }
494		− MT_BUG_ON(mt, mas_allocated(&mas) != 0);
495		−
496		−
497		− for (i = 3; i < MAPLE_NODE_MASK * 3; i++) {
498		− mas.node = MA_ERROR(-ENOMEM);
499		− mas_node_count(&mas, i); /* Request */
500		− mas_nomem(&mas, GFP_KERNEL); /* Fill request */
501		− mn = mas_pop_node(&mas); /* get the next node. */
502		− mas_push_node(&mas, mn); /* put it back */
503		− mas_destroy(&mas);
504		−
505		− mas.node = MA_ERROR(-ENOMEM);
506		− mas_node_count(&mas, i); /* Request */
507		− mas_nomem(&mas, GFP_KERNEL); /* Fill request */
508		− mn = mas_pop_node(&mas); /* get the next node. */
509		− mn2 = mas_pop_node(&mas); /* get the next node. */
510		− mas_push_node(&mas, mn); /* put them back */
511		− mas_push_node(&mas, mn2);
512		− mas_destroy(&mas);
513		−
514		− mas.node = MA_ERROR(-ENOMEM);
515		− mas_node_count(&mas, i); /* Request */
516		− mas_nomem(&mas, GFP_KERNEL); /* Fill request */
517		− mn = mas_pop_node(&mas); /* get the next node. */
518		− mn2 = mas_pop_node(&mas); /* get the next node. */
519		− mn3 = mas_pop_node(&mas); /* get the next node. */
520		− mas_push_node(&mas, mn); /* put them back */
521		− mas_push_node(&mas, mn2);
522		− mas_push_node(&mas, mn3);
523		− mas_destroy(&mas);
524		−
525		− mas.node = MA_ERROR(-ENOMEM);
526		− mas_node_count(&mas, i); /* Request */
527		− mas_nomem(&mas, GFP_KERNEL); /* Fill request */
528		− mn = mas_pop_node(&mas); /* get the next node. */
529		− ma_free_rcu(mn);
530		− mas_destroy(&mas);
531		−
532		− mas.node = MA_ERROR(-ENOMEM);
533		− mas_node_count(&mas, i); /* Request */
534		− mas_nomem(&mas, GFP_KERNEL); /* Fill request */
535		− mn = mas_pop_node(&mas); /* get the next node. */
536		− ma_free_rcu(mn);
537		− mn = mas_pop_node(&mas); /* get the next node. */
538		− ma_free_rcu(mn);
539		− mn = mas_pop_node(&mas); /* get the next node. */
540		− ma_free_rcu(mn);
541		− mas_destroy(&mas);
542		− }
543		−
544		− mas.node = MA_ERROR(-ENOMEM);
545		− mas_node_count(&mas, 5); /* Request */
546		− mas_nomem(&mas, GFP_KERNEL); /* Fill request */
547		− MT_BUG_ON(mt, mas_allocated(&mas) != 5);
548		− mas.node = MA_ERROR(-ENOMEM);
549		− mas_node_count(&mas, 10); /* Request */
550		− mas_nomem(&mas, GFP_KERNEL); /* Fill request */
551		− mas.node = MAS_START;
552		− MT_BUG_ON(mt, mas_allocated(&mas) != 10);
553		− mas_destroy(&mas);
554		−
555		− mas.node = MA_ERROR(-ENOMEM);
556		− mas_node_count(&mas, MAPLE_ALLOC_SLOTS - 1); /* Request */
557		− mas_nomem(&mas, GFP_KERNEL); /* Fill request */
558		− MT_BUG_ON(mt, mas_allocated(&mas) != MAPLE_ALLOC_SLOTS - 1);
559		− mas.node = MA_ERROR(-ENOMEM);
560		− mas_node_count(&mas, 10 + MAPLE_ALLOC_SLOTS - 1); /* Request */
561		− mas_nomem(&mas, GFP_KERNEL); /* Fill request */
562		− mas.node = MAS_START;
563		− MT_BUG_ON(mt, mas_allocated(&mas) != 10 + MAPLE_ALLOC_SLOTS - 1);
564		− mas_destroy(&mas);
565		−
566		− mtree_unlock(mt);
567		−}
568	196
569	197	static noinline void check_rev_seq(struct maple_tree *mt, unsigned long max,
570	198	bool verbose)
@@ -588,6 +216,7 @@ static noinline void check_rev_seq(struct maple_tree *mt, unsigned long max, · 17 unmodified lines
588	216	}
589	217	check_load(mt, max + 1, NULL);
590	218
	219	+#ifndef __KERNEL__
591	220	if (verbose) {
592	221	rcu_barrier();
593	222	mt_dump(mt);
@@ -595,6 +224,7 @@ static noinline void check_rev_seq(struct maple_tree *mt, unsigned long max, · 1 unmodified line
595	224	__func__, max, mt_get_alloc_size()/1024, mt_nr_allocated(),
596	225	mt_nr_tallocated());
597	226	}
	227	+#endif
598	228	}
599	229
600	230	static noinline void check_seq(struct maple_tree *mt, unsigned long max,
@@ -614,6 +244,8 @@ static noinline void check_seq(struct maple_tree *mt, unsigned long max, · 13 unmodified lines
614	244	MT_BUG_ON(mt, !mt_height(mt));
615	245	check_load(mt, i + 1, NULL);
616	246	}
	247	+
	248	+#ifndef __KERNEL__
617	249	if (verbose) {
618	250	rcu_barrier();
619	251	mt_dump(mt);
@@ -621,6 +253,7 @@ static noinline void check_seq(struct maple_tree *mt, unsigned long max, · 1 unmodified line
621	253	max, mt_get_alloc_size()/1024, mt_nr_allocated(),
622	254	mt_nr_tallocated());
623	255	}
	256	+#endif
624	257	}
625	258
626	259	static noinline void check_lb_not_empty(struct maple_tree *mt)
@@ -651,10 +284,15 @@ static noinline void check_lower_bound_split(struct maple_tree *mt) · 24 unmodified lines
651	284	static noinline void check_upper_bound_split(struct maple_tree *mt)
652	285	{
653	286	unsigned long i, j;
654		− unsigned long huge = 4000UL * 1000 * 1000;
	287	+ unsigned long huge;
655	288
656	289	MT_BUG_ON(mt, !mtree_empty(mt));
657	290
	291	+ if (MAPLE_32BIT)
	292	+ huge = 2147483647UL;
	293	+ else
	294	+ huge = 4000UL * 1000 * 1000;
	295	+
658	296	i = 4096;
659	297	while (i < huge) {
660	298	check_insert(mt, i, (void *) i);
@@ -687,6 +325,7 @@ static noinline void check_rev_find(struct maple_tree *mt) · 26 unmodified lines
687	325	mtree_store_range(mt, i10, i10 + 5,
688	326	xa_mk_value(i), GFP_KERNEL);
689	327
	328	+ rcu_read_lock();
690	329	mas_set(&mas, 1000);
691	330	val = mas_find_rev(&mas, 1000);
692	331	MT_BUG_ON(mt, val != xa_mk_value(100));
@@ -712,13 +351,15 @@ static noinline void check_rev_find(struct maple_tree *mt) · 19 unmodified lines
712	351	MT_BUG_ON(mt, val != xa_mk_value(0));
713	352	val = mas_find_rev(&mas, 0);
714	353	MT_BUG_ON(mt, val != NULL);
	354	+ rcu_read_unlock();
715	355	}
716	356
717	357	static noinline void check_find(struct maple_tree *mt)
718	358	{
719	359	unsigned long val = 0;
720		− unsigned long count = 20;
	360	+ unsigned long count;
721	361	unsigned long max;
	362	+ unsigned long top;
722	363	unsigned long last = 0, index = 0;
723	364	void entry, entry2;
724	365
@@ -727,6 +368,18 @@ static noinline void check_find(struct maple_tree *mt) · 2 unmodified lines
727	368	/* Insert 0. */
728	369	MT_BUG_ON(mt, mtree_insert_index(mt, val++, GFP_KERNEL));
729	370
	371	+#if defined(CONFIG_64BIT)
	372	+ top = 4398046511104UL;
	373	+#else
	374	+ top = ULONG_MAX;
	375	+#endif
	376	+
	377	+ if (MAPLE_32BIT) {
	378	+ count = 15;
	379	+ } else {
	380	+ count = 20;
	381	+ }
	382	+
730	383	for (int i = 0; i <= count; i++) {
731	384	if (val != 64)
732	385	MT_BUG_ON(mt, mtree_insert_index(mt, val, GFP_KERNEL));
@@ -805,12 +458,17 @@ static noinline void check_find(struct maple_tree *mt) · 72 unmodified lines
805	458	index = 0;
806	459	MT_BUG_ON(mt, mtree_insert_index(mt, ULONG_MAX, GFP_KERNEL));
807	460	mt_for_each(mt, entry, index, ULONG_MAX) {
808		− if (val == 4398046511104)
809		− MT_BUG_ON(mt, entry !=
810		− xa_mk_value(ULONG_MAX & LONG_MAX));
	461	+ if (val == top)
	462	+ MT_BUG_ON(mt, entry != xa_mk_value(LONG_MAX));
811	463	else
812	464	MT_BUG_ON(mt, xa_mk_value(val) != entry);
813		− val <<= 2;
	465	+
	466	+ /* Workaround for 32bit */
	467	+ if ((val << 2) < val)
	468	+ val = ULONG_MAX;
	469	+ else
	470	+ val <<= 2;
	471	+
814	472	if (val == 64) /* Skip zero entry. */
815	473	val <<= 2;
816	474	/* For zero check. */
@@ -842,11 +500,16 @@ static noinline void check_find(struct maple_tree *mt) · 25 unmodified lines
842	500	mas_for_each(&mas, entry, ULONG_MAX) {
843	501	if (val == 64)
844	502	MT_BUG_ON(mt, entry != XA_ZERO_ENTRY);
845		− else if (val == 4398046511104)
846		− MT_BUG_ON(mt, entry != xa_mk_value(ULONG_MAX & LONG_MAX));
	503	+ else if (val == top)
	504	+ MT_BUG_ON(mt, entry != xa_mk_value(LONG_MAX));
847	505	else
848	506	MT_BUG_ON(mt, xa_mk_value(val) != entry);
849		− val <<= 2;
	507	+
	508	+ /* Workaround for 32bit */
	509	+ if ((val << 2) < val)
	510	+ val = ULONG_MAX;
	511	+ else
	512	+ val <<= 2;
850	513
851	514	/* For zero check. */
852	515	if (!val)
@@ -951,36548 +614,1350 @@ static noinline void check_find_2(struct maple_tree *mt) · 98 unmodified lines
951	614	/MT_BUG_ON(mt, !mtree_empty(mt)); /
952	615	}
953	616
954		−#define erase_ptr(i) entry[i%2]
955		−#define erase_check_load(mt, i) check_load(mt, set[i], entry[i%2])
956		−#define erase_check_insert(mt, i) check_insert(mt, set[i], entry[i%2])
957		−#define erase_check_erase(mt, i) check_erase(mt, set[i], entry[i%2])
958	617
959		−static noinline void check_erase_testset(struct maple_tree *mt)
	618	+#if defined(CONFIG_64BIT)
	619	+static noinline void check_alloc_rev_range(struct maple_tree *mt)
960	620	{
961		− unsigned long set[] = { 5015, 5014, 5017, 25, 1000,
962		− 1001, 1002, 1003, 1005, 0,
963		− 6003, 6002, 6008, 6012, 6015,
964		− 7003, 7002, 7008, 7012, 7015,
965		− 8003, 8002, 8008, 8012, 8015,
966		− 9003, 9002, 9008, 9012, 9015,
967		− 10003, 10002, 10008, 10012, 10015,
968		− 11003, 11002, 11008, 11012, 11015,
969		− 12003, 12002, 12008, 12012, 12015,
970		− 13003, 13002, 13008, 13012, 13015,
971		− 14003, 14002, 14008, 14012, 14015,
972		− 15003, 15002, 15008, 15012, 15015,
973		− };
974		−
975		−
976		− void *ptr = &set;
977		− void *entry[2] = { ptr, mt };
978		− void *root_node;
979		−
980		−
981		− rcu_register_thread();
982		− mt_set_in_rcu(mt);
983		− for (int i = 0; i < 4; i++)
984		− erase_check_insert(mt, i);
985		− for (int i = 0; i < 4; i++)
986		− erase_check_load(mt, i);
987		−
988		− mt_set_non_kernel(2);
989		− erase_check_erase(mt, 1);
990		− erase_check_load(mt, 0);
991		− check_load(mt, set[1], NULL);
992		− for (int i = 2; i < 4; i++)
993		− erase_check_load(mt, i);
994		−
995		−
996		− erase_check_erase(mt, 2);
997		− erase_check_load(mt, 0);
998		− check_load(mt, set[1], NULL);
999		− check_load(mt, set[2], NULL);
1000		−
1001		− erase_check_insert(mt, 1);
1002		− erase_check_insert(mt, 2);
1003		−
1004		− for (int i = 0; i < 4; i++)
1005		− erase_check_load(mt, i);
1006		−
1007		− /* Check erase and load without an allocation. */
1008		− erase_check_load(mt, 3);
1009		− erase_check_erase(mt, 1);
1010		− erase_check_load(mt, 0);
1011		− check_load(mt, set[1], NULL);
1012		− for (int i = 2; i < 4; i++)
1013		− erase_check_load(mt, i);
1014		−
1015	621	/*
1016		− * Set the newly erased node. This will produce a different allocated
1017		− * node to avoid busy slots.
	622	+ * Generated by:
	623	+ * cat /proc/self/maps \| awk '{print $1}'\|
	624	+ * awk -F "-" '{printf "0x%s, 0x%s, ", $1, $2}'
1018	625	*/
1019		− root_node = mt->ma_root;
1020		− erase_check_insert(mt, 1);
1021		−
1022		− erase_check_load(mt, 0);
1023		− check_load(mt, 5016, NULL);
1024		− erase_check_load(mt, 1);
1025		− check_load(mt, 5013, NULL);
1026		− erase_check_load(mt, 2);
1027		− check_load(mt, 5018, NULL);
1028		− erase_check_load(mt, 3);
1029		−
1030		− erase_check_erase(mt, 2); /* erase 5017 to check append */
1031		− erase_check_load(mt, 0);
1032		− check_load(mt, 5016, NULL);
1033		− erase_check_load(mt, 1);
1034		− check_load(mt, 5013, NULL);
1035		− check_load(mt, set[2], NULL);
1036		− check_load(mt, 5018, NULL);
1037		−
1038		− erase_check_load(mt, 3);
1039		−
1040		− root_node = mt->ma_root;
1041		− erase_check_insert(mt, 2);
1042		−
1043		− erase_check_load(mt, 0);
1044		− check_load(mt, 5016, NULL);
1045		− erase_check_load(mt, 1);
1046		− check_load(mt, 5013, NULL);
1047		− erase_check_load(mt, 2);
1048		− check_load(mt, 5018, NULL);
1049		− erase_check_load(mt, 3);
1050	626
1051		− mt_set_non_kernel(1);
1052		− erase_check_erase(mt, 2); /* erase 5017 to check append */
1053		− erase_check_load(mt, 0);
1054		− check_load(mt, 5016, NULL);
1055		− check_load(mt, set[2], NULL);
1056		− erase_check_erase(mt, 0); /* erase 5015 to check append */
1057		− check_load(mt, set[0], NULL);
1058		− check_load(mt, 5016, NULL);
1059		− erase_check_insert(mt, 4); /* 1000 < Should not split. */
1060		− check_load(mt, set[0], NULL);
1061		− check_load(mt, 5016, NULL);
1062		− erase_check_load(mt, 1);
1063		− check_load(mt, 5013, NULL);
1064		− check_load(mt, set[2], NULL);
1065		− check_load(mt, 5018, NULL);
1066		− erase_check_load(mt, 4);
1067		− check_load(mt, 999, NULL);
1068		− check_load(mt, 1001, NULL);
1069		− erase_check_load(mt, 4);
1070		− if (mt_in_rcu(mt))
1071		− MT_BUG_ON(mt, root_node == mt->ma_root);
1072		− else
1073		− MT_BUG_ON(mt, root_node != mt->ma_root);
	627	+ unsigned long range[] = {
	628	+ /* Inclusive , Exclusive. */
	629	+ 0x565234af2000, 0x565234af4000,
	630	+ 0x565234af4000, 0x565234af9000,
	631	+ 0x565234af9000, 0x565234afb000,
	632	+ 0x565234afc000, 0x565234afd000,
	633	+ 0x565234afd000, 0x565234afe000,
	634	+ 0x565235def000, 0x565235e10000,
	635	+ 0x7f36d4bfd000, 0x7f36d4ee2000,
	636	+ 0x7f36d4ee2000, 0x7f36d4f04000,
	637	+ 0x7f36d4f04000, 0x7f36d504c000,
	638	+ 0x7f36d504c000, 0x7f36d5098000,
	639	+ 0x7f36d5098000, 0x7f36d5099000,
	640	+ 0x7f36d5099000, 0x7f36d509d000,
	641	+ 0x7f36d509d000, 0x7f36d509f000,
	642	+ 0x7f36d509f000, 0x7f36d50a5000,
	643	+ 0x7f36d50b9000, 0x7f36d50db000,
	644	+ 0x7f36d50db000, 0x7f36d50dc000,
	645	+ 0x7f36d50dc000, 0x7f36d50fa000,
	646	+ 0x7f36d50fa000, 0x7f36d5102000,
	647	+ 0x7f36d5102000, 0x7f36d5103000,
	648	+ 0x7f36d5103000, 0x7f36d5104000,
	649	+ 0x7f36d5104000, 0x7f36d5105000,
	650	+ 0x7fff5876b000, 0x7fff5878d000,
	651	+ 0x7fff5878e000, 0x7fff58791000,
	652	+ 0x7fff58791000, 0x7fff58793000,
	653	+ };
1074	654
1075		− /* Should not have split. */
1076		− MT_BUG_ON(mt, !mte_is_leaf(mt->ma_root));
	655	+ unsigned long holes[] = {
	656	+ /*
	657	+ * Note: start of hole is INCLUSIVE
	658	+ * end of hole is EXCLUSIVE
	659	+ * (opposite of the above table.)
	660	+ * Start of hole, end of hole, size of hole (+1)
	661	+ */
	662	+ 0x565234afb000, 0x565234afc000, 0x1000,
	663	+ 0x565234afe000, 0x565235def000, 0x12F1000,
	664	+ 0x565235e10000, 0x7f36d4bfd000, 0x28E49EDED000,
	665	+ };
1077	666
	667	+ /*
	668	+ * req_range consists of 4 values.
	669	+ * 1. min index
	670	+ * 2. max index
	671	+ * 3. size
	672	+ * 4. number that should be returned.
	673	+ * 5. return value
	674	+ */
	675	+ unsigned long req_range[] = {
	676	+ 0x565234af9000, /* Min */
	677	+ 0x7fff58791000, /* Max */
	678	+ 0x1000, /* Size */
	679	+ 0x7fff5878d << 12, /* First rev hole of size 0x1000 */
	680	+ 0, /* Return value success. */
1078	681
1079		− /* Coalesce testing */
1080		− erase_check_insert(mt, 0);
1081		− erase_check_insert(mt, 2);
	682	+ 0x0, /* Min */
	683	+ 0x565234AF1 << 12, /* Max */
	684	+ 0x3000, /* Size */
	685	+ 0x565234AEE << 12, /* max - 3. */
	686	+ 0, /* Return value success. */
1082	687
1083		− for (int i = 5; i < 25; i++) {
1084		− erase_check_insert(mt, i);
1085		− for (int j = i; j >= 0; j--)
1086		− erase_check_load(mt, j);
1087		− }
	688	+ 0x0, /* Min */
	689	+ -1, /* Max */
	690	+ 0x1000, /* Size */
	691	+ 562949953421311 << 12,/* First rev hole of size 0x1000 */
	692	+ 0, /* Return value success. */
1088	693
1089		− erase_check_erase(mt, 14); /6015 /
1090		− for (int i = 0; i < 25; i++) {
1091		− if (i == 14)
1092		− check_load(mt, set[i], NULL);
1093		− else
1094		− erase_check_load(mt, i);
1095		− }
1096		− erase_check_erase(mt, 16); /7002 /
1097		− for (int i = 0; i < 25; i++) {
1098		− if (i == 16 \|\| i == 14)
1099		− check_load(mt, set[i], NULL);
1100		− else
1101		− erase_check_load(mt, i);
1102		− }
	694	+ 0x0, /* Min */
	695	+ 0x7F36D510A << 12, /* Max */
	696	+ 0x4000, /* Size */
	697	+ 0x7F36D5106 << 12, /* First rev hole of size 0x4000 */
	698	+ 0, /* Return value success. */
1103	699
	700	+ /* Ascend test. */
	701	+ 0x0,
	702	+ 34148798629 << 12,
	703	+ 19 << 12,
	704	+ 34148797418 << 12,
	705	+ 0x0,
1104	706
1105		− mt_set_non_kernel(1);
1106		− erase_check_erase(mt, 13); /6012 /
1107		− for (int i = 0; i < 25; i++) {
1108		− if (i == 16 \|\| i == 14 \|\| i == 13)
1109		− check_load(mt, set[i], NULL);
1110		− else
1111		− erase_check_load(mt, i);
1112		− }
	707	+ /* Too big test. */
	708	+ 0x0,
	709	+ 18446744073709551615UL,
	710	+ 562915594369134UL << 12,
	711	+ 0x0,
	712	+ -EBUSY,
1113	713
1114		− erase_check_erase(mt, 15); /7003 /
1115		− for (int i = 0; i < 25; i++) {
1116		− if (i <= 16 && i >= 13)
1117		− check_load(mt, set[i], NULL);
1118		− else
1119		− erase_check_load(mt, i);
1120		− }
	714	+ };
1121	715
1122		− mt_set_non_kernel(2);
1123		− erase_check_erase(mt, 17); /7008 should* cause coalesce. */
1124		− for (int i = 0; i < 25; i++) {
1125		− if (i <= 17 && i >= 13)
1126		− check_load(mt, set[i], NULL);
1127		− else
1128		− erase_check_load(mt, i);
1129		− }
	716	+ int i, range_count = ARRAY_SIZE(range);
	717	+ int req_range_count = ARRAY_SIZE(req_range);
	718	+ unsigned long min = 0;
1130	719
1131		− erase_check_erase(mt, 18); /7012 /
1132		− for (int i = 0; i < 25; i++) {
1133		− if (i <= 18 && i >= 13)
1134		− check_load(mt, set[i], NULL);
1135		− else
1136		− erase_check_load(mt, i);
1137		− }
	720	+ MA_STATE(mas, mt, 0, 0);
1138	721
1139		− mt_set_non_kernel(2);
1140		− erase_check_erase(mt, 19); /7015 /
1141		− for (int i = 0; i < 25; i++) {
1142		− if (i <= 19 && i >= 13)
1143		− check_load(mt, set[i], NULL);
1144		− else
1145		− erase_check_load(mt, i);
1146		− }
	722	+ mtree_store_range(mt, MTREE_ALLOC_MAX, ULONG_MAX, XA_ZERO_ENTRY,
	723	+ GFP_KERNEL);
	724	+#define DEBUG_REV_RANGE 0
	725	+ for (i = 0; i < range_count; i += 2) {
	726	+ /* Inclusive, Inclusive (with the -1) */
1147	727
1148		− erase_check_erase(mt, 20); /8003 /
1149		− for (int i = 0; i < 25; i++) {
1150		− if (i <= 20 && i >= 13)
1151		− check_load(mt, set[i], NULL);
1152		− else
1153		− erase_check_load(mt, i);
	728	+#if DEBUG_REV_RANGE
	729	+ pr_debug("\t%s: Insert %lu-%lu\n", __func__, range[i] >> 12,
	730	+ (range[i + 1] >> 12) - 1);
	731	+#endif
	732	+ check_insert_range(mt, range[i] >> 12, (range[i + 1] >> 12) - 1,
	733	+ xa_mk_value(range[i] >> 12), 0);
	734	+ mt_validate(mt);
1154	735	}
1155	736
1156		− erase_check_erase(mt, 21); /8002 /
1157		− for (int i = 0; i < 25; i++) {
1158		− if (i <= 21 && i >= 13)
1159		− check_load(mt, set[i], NULL);
1160		− else
1161		− erase_check_load(mt, i);
1162		− }
1163	737
1164		− mt_set_non_kernel(2);
1165		− erase_check_erase(mt, 22); /8008 /
1166		− for (int i = 0; i < 25; i++) {
1167		− if (i <= 22 && i >= 13)
1168		− check_load(mt, set[i], NULL);
1169		− else
1170		− erase_check_load(mt, i);
	738	+ mas_lock(&mas);
	739	+ for (i = 0; i < ARRAY_SIZE(holes); i += 3) {
	740	+#if DEBUG_REV_RANGE
	741	+ pr_debug("Search from %lu-%lu for gap %lu should be at %lu\n",
	742	+ min, holes[i+1]>>12, holes[i+2]>>12,
	743	+ holes[i] >> 12);
	744	+#endif
	745	+ MT_BUG_ON(mt, mas_empty_area_rev(&mas, min,
	746	+ holes[i+1] >> 12,
	747	+ holes[i+2] >> 12));
	748	+#if DEBUG_REV_RANGE
	749	+ pr_debug("Found %lu %lu\n", mas.index, mas.last);
	750	+ pr_debug("gap %lu %lu\n", (holes[i] >> 12),
	751	+ (holes[i+1] >> 12));
	752	+#endif
	753	+ MT_BUG_ON(mt, mas.last + 1 != (holes[i+1] >> 12));
	754	+ MT_BUG_ON(mt, mas.index != (holes[i+1] >> 12) - (holes[i+2] >> 12));
	755	+ min = holes[i+1] >> 12;
	756	+ mas_reset(&mas);
1171	757	}
1172		− for (int i = 23; i < 25; i++)
1173		− erase_check_erase(mt, i);
1174	758
1175		− for (int i = 0; i < 25; i++) {
1176		− if (i <= 25 && i >= 13)
1177		− check_load(mt, set[i], NULL);
1178		− else
1179		− erase_check_load(mt, i);
	759	+ mas_unlock(&mas);
	760	+ for (i = 0; i < req_range_count; i += 5) {
	761	+#if DEBUG_REV_RANGE
	762	+ pr_debug("\tReverse request between %lu-%lu size %lu, should get %lu\n",
	763	+ req_range[i] >> 12,
	764	+ (req_range[i + 1] >> 12) - 1,
	765	+ req_range[i+2] >> 12,
	766	+ req_range[i+3] >> 12);
	767	+#endif
	768	+ check_mtree_alloc_rrange(mt,
	769	+ req_range[i] >> 12, /* start */
	770	+ req_range[i+1] >> 12, /* end */
	771	+ req_range[i+2] >> 12, /* size */
	772	+ req_range[i+3] >> 12, /* expected address */
	773	+ req_range[i+4], /* expected return */
	774	+ xa_mk_value(req_range[i] >> 12)); /* pointer */
	775	+ mt_validate(mt);
1180	776	}
1181	777
1182		− /* Shrinking tree test. */
	778	+ mt_set_non_kernel(1);
	779	+ mtree_erase(mt, 34148798727); /* create a deleted range. */
	780	+ check_mtree_alloc_rrange(mt, 0, 34359052173, 210253414,
	781	+ 34148798725, 0, mt);
1183	782
1184		− for (int i = 13; i < ARRAY_SIZE(set); i++)
1185		− erase_check_insert(mt, i);
	783	+ mtree_destroy(mt);
	784	+}
1186	785
1187		− mt_set_non_kernel(99);
1188		− for (int i = 18; i < ARRAY_SIZE(set); i++) {
1189		− erase_check_erase(mt, i);
1190		− for (int j = 0; j < ARRAY_SIZE(set); j++) {
1191		− if (j < 18 \|\| j > i)
1192		− erase_check_load(mt, j);
1193		− else
1194		− check_load(mt, set[j], NULL);
1195		− }
1196		− }
1197		− mt_set_non_kernel(35);
1198		− for (int i = 0; i < 18; i++) {
1199		− erase_check_erase(mt, i);
1200		− for (int j = 0; j < ARRAY_SIZE(set); j++) {
1201		− if (j < 18 && j > i)
1202		− erase_check_load(mt, j);
1203		− else
1204		− check_load(mt, set[j], NULL);
1205		− }
1206		− }
1207		− erase_check_insert(mt, 8);
1208		− erase_check_insert(mt, 9);
1209		− erase_check_erase(mt, 8);
1210		− rcu_unregister_thread();
1211		−}
1212		−
1213		−#define erase_check_store_range(mt, a, i, ptr) mtree_test_store_range(mt, \
1214		− a[(i)], a[(i + 1)], ptr)
1215		−#define STORE 1
1216		−#define SNULL 2
1217		−#define ERASE 3
1218		−#define ec_type_str(x) \
1219		− (((x) == STORE) ? \
1220		− "STORE" : \
1221		− (((x) == SNULL) ? \
1222		− "SNULL" : "ERASE") \
1223		− )
1224		−#define check_erase2_debug 0
1225		−void mas_next(struct ma_state mas, unsigned long max);
1226		−
1227		−/* Calculate the overwritten entries. */
1228		−int mas_ce2_over_count(struct ma_state mas_start, struct ma_state mas_end,
1229		− void *s_entry, unsigned long s_min,
1230		− void *e_entry, unsigned long e_max,
1231		− unsigned long *set, int i, bool null_entry)
1232		−{
1233		− int count = 0, span = 0;
1234		− unsigned long retry = 0;
1235		− void *entry;
1236		− struct ma_state tmp;
1237		−
1238		−
1239		− /* count slots */
1240		− memcpy(&tmp, mas_start, sizeof(tmp));
1241		− entry = mas_next(&tmp, mas_end->last);
1242		− while (entry) {
1243		− BUG_ON(retry > 50); /* stop infinite retry on testing. */
1244		− if (xa_is_zero(s_entry)) {
1245		− retry++;
1246		− continue;
1247		− }
1248		− count++;
1249		− span++;
1250		− entry = mas_next(&tmp, mas_end->last);
1251		− }
1252		−
1253		− if (null_entry) {
1254		− /* Check splitting end. */
1255		− if (e_entry && (e_max > mas_end->last))
1256		− count--;
1257		−
1258		− /* check overwrite of entire start */
1259		− if (s_entry && (s_min == mas_start->index))
1260		− count++;
1261		− } else { /* !null_entry (store) */
1262		− bool esplit = e_max > mas_end->last;
1263		− bool ssplit = s_min != mas_start->index;
1264		−
1265		− if (s_entry && e_entry) {
1266		− if (esplit && ssplit)
1267		− count--;
1268		− else if (ssplit)
1269		− count--;
1270		− else if (esplit) {
1271		− if (span)
1272		− count--;
1273		− }
1274		− } else if (s_entry && !e_entry) {
1275		− if (ssplit)
1276		− count--;
1277		− } else if (!s_entry && e_entry) {
1278		− if (esplit)
1279		− count--;
1280		− count--;
1281		− } else {
1282		− count--;
1283		− }
1284		− }
1285		− return count;
1286		−}
1287		−
1288		−/*
1289		− * mas_node_walk() - Walk a maple node to offset of the index.
1290		− * @mas: The maple state
1291		− * @type: The maple node type
1292		− * @*range_min: Pointer to store the minimum range of the offset
1293		− * @*range_max: Pointer to store the maximum range of the offset
1294		− *
1295		− * The offset will be stored in the maple state.
1296		− *
1297		− */
1298		−static inline void mas_node_walk(struct ma_state mas, struct maple_node node,
1299		− enum maple_type type, unsigned long *range_min,
1300		− unsigned long *range_max)
1301		−
1302		−{
1303		− unsigned long *pivots;
1304		− unsigned char count;
1305		− unsigned long prev, max;
1306		− unsigned char offset;
1307		− unsigned long index;
1308		−
1309		− if (unlikely(ma_is_dense(type))) {
1310		− (range_max) = (range_min) = mas->index;
1311		− if (unlikely(ma_dead_node(node)))
1312		− return;
1313		−
1314		− mas->offset = mas->index = mas->min;
1315		− return;
1316		− }
1317		−
1318		− pivots = ma_pivots(node, type);
1319		− max = pivots[0];
1320		− if (unlikely(ma_dead_node(node)))
1321		− return;
1322		−
1323		− offset = 0;
1324		− prev = mas->min;
1325		− index = mas->index;
1326		− if (unlikely(index <= max))
1327		− goto offset_zero;
1328		−
1329		− count = mt_pivots[type];
1330		− while (++offset < count) {
1331		− prev = max;
1332		− max = pivots[offset];
1333		− if (unlikely(ma_dead_node(node)))
1334		− return;
1335		−
1336		− if (index <= max)
1337		− goto offset_found;
1338		− else if (unlikely(!max))
1339		− goto mas_max;
1340		− }
1341		−
1342		− prev = max;
1343		−mas_max:
1344		− max = mas->max;
1345		−offset_found:
1346		− prev++;
1347		−offset_zero:
1348		− mas->offset = offset;
1349		− if (ma_is_leaf(type)) {
1350		− *range_max = max;
1351		− *range_min = prev;
1352		− } else {
1353		− mas->max = max;
1354		− mas->min = prev;
1355		− }
1356		−}
1357		−
1358		−/*
1359		− * mas_descend_walk(): Locates a value and sets the mas->node and slot
1360		− * accordingly. range_min and range_max are set to the range which the entry is
1361		− * valid.
1362		− * @mas: The maple state
1363		− * @*range_min: A pointer to store the minimum of the range
1364		− * @*range_max: A pointer to store the maximum of the range
1365		− *
1366		− * Check mas->node is still valid on return of any value.
1367		− *
1368		− * Return: true if pointing to a valid node and offset. False otherwise.
1369		− */
1370		−static inline bool mas_descend_walk(struct ma_state *mas,
1371		− unsigned long range_min, unsigned long range_max)
1372		−{
1373		− struct maple_enode *next;
1374		− struct maple_node *node;
1375		− enum maple_type type;
1376		−
1377		− next = mas->node;
1378		− while (true) {
1379		− node = mte_to_node(next);
1380		− type = mte_node_type(next);
1381		− mas_node_walk(mas, node, type, range_min, range_max);
1382		− next = mas_slot(mas, ma_slots(node, type), mas->offset);
1383		− if (unlikely(ma_dead_node(node)))
1384		− return false;
1385		−
1386		− if (unlikely(ma_is_leaf(type)))
1387		− return true;
1388		−
1389		− /* Descend. */
1390		− mas->node = next;
1391		− }
1392		− return false;
1393		−}
1394		−
1395		−/*
1396		− * mas_tree_walk() - Walk to @mas->index and set the range values.
1397		− * @mas: The maple state.
1398		− * @*range_min: The minimum range to be set.
1399		− * @*range_max: The maximum range to be set.
1400		− *
1401		− * Ranges are only valid if there is a valid entry at @mas->index.
1402		− *
1403		− * Return: True if a value exists, false otherwise.
1404		− */
1405		−static inline bool mas_tree_walk(struct ma_state mas, unsigned long range_min,
1406		− unsigned long *range_max)
	786	+static noinline void check_alloc_range(struct maple_tree *mt)
1407	787	{
1408		− bool ret;
1409		−
1410		−retry:
1411		− ret = false;
1412		− mas_start(mas);
1413		− if (mas_is_none(mas))
1414		− goto not_found;
1415		−
1416		− if (mas_is_ptr(mas)) {
1417		− range_min = range_max = 0;
1418		− if (!mas->index)
1419		− return true;
1420		−
1421		− goto not_found;
1422		− }
1423		−
1424		− ret = mas_descend_walk(mas, range_min, range_max);
1425		− if (unlikely(mte_dead_node(mas->node))) {
1426		− mas->node = MAS_START;
1427		− goto retry;
1428		− }
1429		−
1430		− return ret;
	788	+ /*
	789	+ * Generated by:
	790	+ * cat /proc/self/maps\|awk '{print $1}'\|
	791	+ * awk -F "-" '{printf "0x%s, 0x%s, ", $1, $2}'
	792	+ */
1431	793
1432		−not_found:
1433		− mas->offset = MAPLE_NODE_SLOTS;
1434		− return false;
1435		−}
	794	+ unsigned long range[] = {
	795	+ /* Inclusive , Exclusive. */
	796	+ 0x565234af2000, 0x565234af4000,
	797	+ 0x565234af4000, 0x565234af9000,
	798	+ 0x565234af9000, 0x565234afb000,
	799	+ 0x565234afc000, 0x565234afd000,
	800	+ 0x565234afd000, 0x565234afe000,
	801	+ 0x565235def000, 0x565235e10000,
	802	+ 0x7f36d4bfd000, 0x7f36d4ee2000,
	803	+ 0x7f36d4ee2000, 0x7f36d4f04000,
	804	+ 0x7f36d4f04000, 0x7f36d504c000,
	805	+ 0x7f36d504c000, 0x7f36d5098000,
	806	+ 0x7f36d5098000, 0x7f36d5099000,
	807	+ 0x7f36d5099000, 0x7f36d509d000,
	808	+ 0x7f36d509d000, 0x7f36d509f000,
	809	+ 0x7f36d509f000, 0x7f36d50a5000,
	810	+ 0x7f36d50b9000, 0x7f36d50db000,
	811	+ 0x7f36d50db000, 0x7f36d50dc000,
	812	+ 0x7f36d50dc000, 0x7f36d50fa000,
	813	+ 0x7f36d50fa000, 0x7f36d5102000,
	814	+ 0x7f36d5102000, 0x7f36d5103000,
	815	+ 0x7f36d5103000, 0x7f36d5104000,
	816	+ 0x7f36d5104000, 0x7f36d5105000,
	817	+ 0x7fff5876b000, 0x7fff5878d000,
	818	+ 0x7fff5878e000, 0x7fff58791000,
	819	+ 0x7fff58791000, 0x7fff58793000,
	820	+ };
	821	+ unsigned long holes[] = {
	822	+ /* Start of hole, end of hole, size of hole (+1) */
	823	+ 0x565234afb000, 0x565234afc000, 0x1000,
	824	+ 0x565234afe000, 0x565235def000, 0x12F1000,
	825	+ 0x565235e10000, 0x7f36d4bfd000, 0x28E49EDED000,
	826	+ };
1436	827
1437		−static inline void mas_range_load(struct ma_state mas,
1438		− unsigned long range_min, unsigned long range_max)
	828	+ /*
	829	+ * req_range consists of 4 values.
	830	+ * 1. min index
	831	+ * 2. max index
	832	+ * 3. size
	833	+ * 4. number that should be returned.
	834	+ * 5. return value
	835	+ */
	836	+ unsigned long req_range[] = {
	837	+ 0x565234af9000, /* Min */
	838	+ 0x7fff58791000, /* Max */
	839	+ 0x1000, /* Size */
	840	+ 0x565234afb000, /* First hole in our data of size 1000. */
	841	+ 0, /* Return value success. */
1439	842
1440		−{
1441		− void *entry = NULL;
1442		− unsigned long index = mas->index;
	843	+ 0x0, /* Min */
	844	+ 0x7fff58791000, /* Max */
	845	+ 0x1F00, /* Size */
	846	+ 0x0, /* First hole in our data of size 2000. */
	847	+ 0, /* Return value success. */
1443	848
1444		− if (mas_is_none(mas) \|\| mas_is_paused(mas))
1445		− mas->node = MAS_START;
1446		−retry:
1447		− if (mas_tree_walk(mas, range_min, range_max))
1448		− if (unlikely(mas->node == MAS_ROOT))
1449		− return mas_root(mas);
	849	+ /* Test ascend. */
	850	+ 34148797436 << 12, /* Min */
	851	+ 0x7fff587AF000, /* Max */
	852	+ 0x3000, /* Size */
	853	+ 34148798629 << 12, /* Expected location */
	854	+ 0, /* Return value success. */
1450	855
1451		− if (likely(mas->offset != MAPLE_NODE_SLOTS))
1452		− entry = mas_get_slot(mas, mas->offset);
	856	+ /* Test failing. */
	857	+ 34148798623 << 12, /* Min */
	858	+ 34148798683 << 12, /* Max */
	859	+ 0x15000, /* Size */
	860	+ 0, /* Expected location */
	861	+ -EBUSY, /* Return value failed. */
1453	862
1454		− if (mas_dead_node(mas, index))
1455		− goto retry;
	863	+ /* Test filling entire gap. */
	864	+ 34148798623 << 12, /* Min */
	865	+ 0x7fff587AF000, /* Max */
	866	+ 0x10000, /* Size */
	867	+ 34148798632 << 12, /* Expected location */
	868	+ 0, /* Return value success. */
1456	869
1457		− return entry;
1458		−}
1459		−static noinline void check_erase2_testset(struct maple_tree *mt,
1460		− unsigned long *set, unsigned long size)
1461		−{
1462		− int entry_count = 0;
1463		− int check = 0;
1464		− void *foo;
1465		− unsigned long addr = 0;
1466		− void s_entry = NULL, e_entry = NULL;
	870	+ /* Test walking off the end of root. */
	871	+ 0, /* Min */
	872	+ -1, /* Max */
	873	+ -1, /* Size */
	874	+ 0, /* Expected location */
	875	+ -EBUSY, /* Return value failure. */
1467	876
	877	+ /* Test looking for too large a hole across entire range. */
	878	+ 0, /* Min */
	879	+ -1, /* Max */
	880	+ 4503599618982063UL << 12, /* Size */
	881	+ 34359052178 << 12, /* Expected location */
	882	+ -EBUSY, /* Return failure. */
	883	+ };
	884	+ int i, range_count = ARRAY_SIZE(range);
	885	+ int req_range_count = ARRAY_SIZE(req_range);
	886	+ unsigned long min = 0x565234af2000;
1468	887	MA_STATE(mas, mt, 0, 0);
1469	888
1470		− for (int i = 0; i < size; i += 3) {
1471		− unsigned long s_min, s_max;
1472		− unsigned long e_min, e_max;
1473		− void *value = NULL;
1474		−
1475		− MA_STATE(mas_start, mt, set[i+1], set[i+1]);
1476		− MA_STATE(mas_end, mt, set[i+2], set[i+2]);
1477		− mt_set_non_kernel(127);
1478		−#if check_erase2_debug
1479		− pr_err("%s: %d %s %lu - %lu\n", __func__, i,
1480		− ec_type_str(set[i]),
1481		− set[i+1], set[i+2]);
1482		−#endif
1483		− s_entry = mas_range_load(&mas_start, &s_min, &s_max);
1484		− e_entry = mas_range_load(&mas_end, &e_min, &e_max);
1485		−
1486		− switch (set[i]) {
1487		− case SNULL:
1488		− if ((s_min == set[i+1]) && (s_max == set[i+2])) {
1489		− if (s_entry)
1490		− entry_count--;
1491		− } else if ((s_min != set[i+1]) && (s_max != set[i+2])) {
1492		− entry_count++;
1493		− } else if ((mas_start.node != mas_end.node) \|\|
1494		− (mas_start.offset != mas_end.offset)) {
1495		− entry_count -=
1496		− mas_ce2_over_count(&mas_start, &mas_end,
1497		− s_entry, s_min,
1498		− e_entry, e_max, set, i,
1499		− true);
1500		− }
1501		−
1502		−
1503		− erase_check_store_range(mt, set, i + 1, value);
1504		− break;
1505		− case STORE:
1506		− value = xa_mk_value(set[i + 1]);
1507		− if (mas_start.offset > mt_slot_count(mas_start.node)) {
1508		− entry_count++; /* appending an entry. */
1509		− } else if ((s_min == e_min) && (s_max == e_max)) {
1510		− if (!entry_count)
1511		− entry_count++;
1512		−
1513		− else if (s_entry) {
1514		− if (e_max > mas_end.last)
1515		− entry_count++;
1516		−
1517		− if (s_min < mas_start.index)
1518		− entry_count++;
1519		−
1520		− } else {
1521		− entry_count++;
1522		− }
1523		− } else {
1524		− entry_count -=
1525		− mas_ce2_over_count(&mas_start, &mas_end,
1526		− s_entry, s_min,
1527		− e_entry, e_max, set, i,
1528		− false);
1529		− }
1530		−
1531		− erase_check_store_range(mt, set, i + 1, value);
1532		− break;
1533		− case ERASE:
1534		− if (!s_entry)
1535		− break;
1536		− check_erase(mt, set[i+1], xa_mk_value(set[i+1]));
1537		− entry_count--;
1538		− break;
1539		− }
1540		− mt_validate(mt);
1541		− if (entry_count)
1542		− MT_BUG_ON(mt, !mt_height(mt));
1543		−#if check_erase2_debug > 1
	889	+ mtree_store_range(mt, MTREE_ALLOC_MAX, ULONG_MAX, XA_ZERO_ENTRY,
	890	+ GFP_KERNEL);
	891	+ for (i = 0; i < range_count; i += 2) {
	892	+#define DEBUG_ALLOC_RANGE 0
	893	+#if DEBUG_ALLOC_RANGE
	894	+ pr_debug("\tInsert %lu-%lu\n", range[i] >> 12,
	895	+ (range[i + 1] >> 12) - 1);
1544	896	mt_dump(mt);
1545	897	#endif
1546		−#if check_erase2_debug
1547		− pr_err("Done\n");
1548		−#endif
	898	+ check_insert_range(mt, range[i] >> 12, (range[i + 1] >> 12) - 1,
	899	+ xa_mk_value(range[i] >> 12), 0);
	900	+ mt_validate(mt);
	901	+ }
1549	902
1550		− check = 0;
1551		− addr = 0;
1552		− mt_for_each(mt, foo, addr, ULONG_MAX) {
1553		− check++;
1554		−#if check_erase2_debug > 2
1555		− pr_err("mt: %lu -> %p (%d)\n", addr+1, foo, check);
1556		−#endif
1557		− if (check > entry_count)
1558		− break;
1559		− }
1560	903
1561		−#if check_erase2_debug > 2
1562		− pr_err("mt_for_each %d and count %d\n", check, entry_count);
1563		−#endif
1564	904
1565		− MT_BUG_ON(mt, check != entry_count);
	905	+ mas_lock(&mas);
	906	+ for (i = 0; i < ARRAY_SIZE(holes); i += 3) {
1566	907
1567		− check = 0;
1568		− addr = 0;
	908	+#if DEBUG_ALLOC_RANGE
	909	+ pr_debug("\tGet empty %lu-%lu size %lu (%lx-%lx)\n", min >> 12,
	910	+ holes[i+1] >> 12, holes[i+2] >> 12,
	911	+ min, holes[i+1]);
	912	+#endif
	913	+ MT_BUG_ON(mt, mas_empty_area(&mas, min >> 12,
	914	+ holes[i+1] >> 12,
	915	+ holes[i+2] >> 12));
	916	+ MT_BUG_ON(mt, mas.index != holes[i] >> 12);
	917	+ min = holes[i+1];
1569	918	mas_reset(&mas);
1570		− mas.index = 0;
1571		− rcu_read_lock();
1572		− mas_for_each(&mas, foo, ULONG_MAX) {
1573		− if (xa_is_zero(foo)) {
1574		− if (addr == mas.index) {
1575		− mt_dump(mas.tree);
1576		− pr_err("retry failed %lu - %lu\n",
1577		− mas.index, mas.last);
1578		− MT_BUG_ON(mt, 1);
1579		− }
1580		− addr = mas.index;
1581		− continue;
1582		− }
1583		−#if check_erase2_debug > 2
1584		− pr_err("mas: %lu -> %p\n", mas.index, foo);
	919	+ }
	920	+ mas_unlock(&mas);
	921	+ for (i = 0; i < req_range_count; i += 5) {
	922	+#if DEBUG_ALLOC_RANGE
	923	+ pr_debug("\tTest %d: %lu-%lu size %lu expected %lu (%lu-%lu)\n",
	924	+ i/5, req_range[i] >> 12, req_range[i + 1] >> 12,
	925	+ req_range[i + 2] >> 12, req_range[i + 3] >> 12,
	926	+ req_range[i], req_range[i+1]);
1585	927	#endif
1586		− check++;
1587		− if (check > entry_count)
1588		− break;
1589		− }
1590		− rcu_read_unlock();
1591		−#if check_erase2_debug > 2
1592		− pr_err("mas_for_each %d and count %d\n", check, entry_count);
	928	+ check_mtree_alloc_range(mt,
	929	+ req_range[i] >> 12, /* start */
	930	+ req_range[i+1] >> 12, /* end */
	931	+ req_range[i+2] >> 12, /* size */
	932	+ req_range[i+3] >> 12, /* expected address */
	933	+ req_range[i+4], /* expected return */
	934	+ xa_mk_value(req_range[i] >> 12)); /* pointer */
1593	935	mt_validate(mt);
	936	+#if DEBUG_ALLOC_RANGE
	937	+ mt_dump(mt);
1594	938	#endif
1595		−
1596		− MT_BUG_ON(mt, check != entry_count);
1597		−
1598		− MT_BUG_ON(mt, mtree_load(mas.tree, 0) != NULL);
1599	939	}
1600		−}
1601	940
	941	+ mtree_destroy(mt);
	942	+}
	943	+#endif
1602	944
1603		−/* These tests were pulled from kvm tests. */
1604		−static noinline void check_erase2_sets(struct maple_tree *mt)
	945	+static noinline void check_ranges(struct maple_tree *mt)
1605	946	{
1606		− void *entry;
1607		− unsigned long start = 0;
1608		− unsigned long set[] = {
1609		−STORE, 140737488347136, 140737488351231,
1610		−STORE, 140721266458624, 140737488351231,
1611		−ERASE, 140721266458624, 140737488351231,
1612		−STORE, 140721266458624, 140721266462719,
1613		−STORE, 94735788949504, 94735789121535,
1614		−ERASE, 94735788949504, 94735789121535,
1615		−STORE, 94735788949504, 94735788965887,
1616		−STORE, 94735788965888, 94735789121535,
1617		−ERASE, 94735788965888, 94735789121535,
1618		−STORE, 94735788965888, 94735789068287,
1619		−STORE, 94735789068288, 94735789109247,
1620		−STORE, 94735789109248, 94735789121535,
1621		−STORE, 140253902692352, 140253902864383,
1622		−ERASE, 140253902692352, 140253902864383,
1623		−STORE, 140253902692352, 140253902696447,
1624		−STORE, 140253902696448, 140253902864383,
1625		− };
1626		− unsigned long set2[] = {
1627		−STORE, 140737488347136, 140737488351231,
1628		−STORE, 140735933583360, 140737488351231,
1629		−ERASE, 140735933583360, 140737488351231,
1630		−STORE, 140735933583360, 140735933587455,
1631		−STORE, 94811003260928, 94811003432959,
1632		−ERASE, 94811003260928, 94811003432959,
1633		−STORE, 94811003260928, 94811003277311,
1634		−STORE, 94811003277312, 94811003432959,
1635		−ERASE, 94811003277312, 94811003432959,
1636		−STORE, 94811003277312, 94811003379711,
1637		−STORE, 94811003379712, 94811003420671,
1638		−STORE, 94811003420672, 94811003432959,
1639		−STORE, 140277094653952, 140277094825983,
1640		−ERASE, 140277094653952, 140277094825983,
1641		−STORE, 140277094653952, 140277094658047,
1642		−STORE, 140277094658048, 140277094825983,
1643		−ERASE, 140277094658048, 140277094825983,
1644		−STORE, 140277094658048, 140277094780927,
1645		−STORE, 140277094780928, 140277094813695,
1646		−STORE, 140277094813696, 140277094821887,
1647		−STORE, 140277094821888, 140277094825983,
1648		−STORE, 140735933906944, 140735933911039,
1649		− };
1650		− unsigned long set3[] = {
1651		−STORE, 140737488347136, 140737488351231,
1652		−STORE, 140735790264320, 140737488351231,
1653		−ERASE, 140735790264320, 140737488351231,
1654		−STORE, 140735790264320, 140735790268415,
1655		−STORE, 94016597282816, 94016597454847,
1656		−ERASE, 94016597282816, 94016597454847,
1657		−STORE, 94016597282816, 94016597299199,
1658		−STORE, 94016597299200, 94016597454847,
1659		−ERASE, 94016597299200, 94016597454847,
1660		−STORE, 94016597299200, 94016597401599,
1661		−STORE, 94016597401600, 94016597442559,
1662		−STORE, 94016597442560, 94016597454847,
1663		−STORE, 140496959283200, 140496959455231,
1664		−ERASE, 140496959283200, 140496959455231,
1665		−STORE, 140496959283200, 140496959287295,
1666		−STORE, 140496959287296, 140496959455231,
1667		−ERASE, 140496959287296, 140496959455231,
1668		−STORE, 140496959287296, 140496959410175,
1669		−STORE, 140496959410176, 140496959442943,
1670		−STORE, 140496959442944, 140496959451135,
1671		−STORE, 140496959451136, 140496959455231,
1672		−STORE, 140735791718400, 140735791722495,
1673		−STORE, 140735791706112, 140735791718399,
1674		−STORE, 47135835713536, 47135835721727,
1675		−STORE, 47135835721728, 47135835729919,
1676		−STORE, 47135835729920, 47135835893759,
1677		−ERASE, 47135835729920, 47135835893759,
1678		−STORE, 47135835729920, 47135835742207,
1679		−STORE, 47135835742208, 47135835893759,
1680		−STORE, 47135835840512, 47135835893759,
1681		−STORE, 47135835742208, 47135835840511,
1682		−ERASE, 47135835742208, 47135835840511,
1683		−STORE, 47135835742208, 47135835840511,
1684		−STORE, 47135835885568, 47135835893759,
1685		−STORE, 47135835840512, 47135835885567,
1686		−ERASE, 47135835840512, 47135835885567,
1687		−STORE, 47135835840512, 47135835893759,
1688		−ERASE, 47135835840512, 47135835893759,
1689		−STORE, 47135835840512, 47135835885567,
1690		−STORE, 47135835885568, 47135835893759,
1691		− };
1692		−
1693		− unsigned long set4[] = {
1694		−STORE, 140737488347136, 140737488351231,
1695		−STORE, 140728251703296, 140737488351231,
1696		−ERASE, 140728251703296, 140737488351231,
1697		−STORE, 140728251703296, 140728251707391,
1698		−STORE, 94668429205504, 94668429377535,
1699		−ERASE, 94668429205504, 94668429377535,
1700		−STORE, 94668429205504, 94668429221887,
1701		−STORE, 94668429221888, 94668429377535,
1702		−ERASE, 94668429221888, 94668429377535,
1703		−STORE, 94668429221888, 94668429324287,
1704		−STORE, 94668429324288, 94668429365247,
1705		−STORE, 94668429365248, 94668429377535,
1706		−STORE, 47646523273216, 47646523445247,
1707		−ERASE, 47646523273216, 47646523445247,
1708		−STORE, 47646523273216, 47646523277311,
1709		−STORE, 47646523277312, 47646523445247,
1710		−ERASE, 47646523277312, 47646523445247,
1711		−STORE, 47646523277312, 47646523400191,
1712		− };
1713		−
1714		− unsigned long set5[] = {
1715		−STORE, 140737488347136, 140737488351231,
1716		−STORE, 140726874062848, 140737488351231,
1717		−ERASE, 140726874062848, 140737488351231,
1718		−STORE, 140726874062848, 140726874066943,
1719		−STORE, 94248892870656, 94248893042687,
1720		−ERASE, 94248892870656, 94248893042687,
1721		−STORE, 94248892870656, 94248892887039,
1722		−STORE, 94248892887040, 94248893042687,
1723		−ERASE, 94248892887040, 94248893042687,
1724		−STORE, 94248892887040, 94248892989439,
1725		−STORE, 94248892989440, 94248893030399,
1726		−STORE, 94248893030400, 94248893042687,
1727		−STORE, 47884786266112, 47884786438143,
1728		−ERASE, 47884786266112, 47884786438143,
1729		−STORE, 47884786266112, 47884786270207,
1730		−STORE, 47884786270208, 47884786438143,
1731		−ERASE, 47884786270208, 47884786438143,
1732		−STORE, 47884786270208, 47884786393087,
1733		−STORE, 47884786393088, 47884786425855,
1734		−STORE, 47884786425856, 47884786434047,
1735		−STORE, 47884786434048, 47884786438143,
1736		−STORE, 140726874513408, 140726874517503,
1737		−STORE, 140726874501120, 140726874513407,
1738		−STORE, 47884786438144, 47884786446335,
1739		−STORE, 47884786446336, 47884786454527,
1740		−STORE, 47884786454528, 47884786618367,
1741		−ERASE, 47884786454528, 47884786618367,
1742		−STORE, 47884786454528, 47884786466815,
1743		−STORE, 47884786466816, 47884786618367,
1744		−STORE, 47884786565120, 47884786618367,
1745		−STORE, 47884786466816, 47884786565119,
1746		−ERASE, 47884786466816, 47884786565119,
1747		−STORE, 47884786466816, 47884786565119,
1748		−STORE, 47884786610176, 47884786618367,
1749		−STORE, 47884786565120, 47884786610175,
1750		−ERASE, 47884786565120, 47884786610175,
1751		−STORE, 47884786565120, 47884786618367,
1752		−ERASE, 47884786565120, 47884786618367,
1753		−STORE, 47884786565120, 47884786610175,
1754		−STORE, 47884786610176, 47884786618367,
1755		−ERASE, 47884786610176, 47884786618367,
1756		−STORE, 47884786610176, 47884786618367,
1757		−STORE, 47884786618368, 47884789669887,
1758		−STORE, 47884787163136, 47884789669887,
1759		−STORE, 47884786618368, 47884787163135,
1760		−ERASE, 47884787163136, 47884789669887,
1761		−STORE, 47884787163136, 47884789448703,
1762		−STORE, 47884789448704, 47884789669887,
1763		−STORE, 47884788858880, 47884789448703,
1764		−STORE, 47884787163136, 47884788858879,
1765		−ERASE, 47884787163136, 47884788858879,
1766		−STORE, 47884787163136, 47884788858879,
1767		−STORE, 47884789444608, 47884789448703,
1768		−STORE, 47884788858880, 47884789444607,
1769		−ERASE, 47884788858880, 47884789444607,
1770		−STORE, 47884788858880, 47884789444607,
1771		−STORE, 47884789653504, 47884789669887,
1772		−STORE, 47884789448704, 47884789653503,
1773		−ERASE, 47884789448704, 47884789653503,
1774		−STORE, 47884789448704, 47884789653503,
1775		−ERASE, 47884789653504, 47884789669887,
1776		−STORE, 47884789653504, 47884789669887,
1777		−STORE, 47884789669888, 47884791508991,
1778		−STORE, 47884789809152, 47884791508991,
1779		−STORE, 47884789669888, 47884789809151,
1780		−ERASE, 47884789809152, 47884791508991,
1781		−STORE, 47884789809152, 47884791468031,
1782		−STORE, 47884791468032, 47884791508991,
1783		−STORE, 47884791152640, 47884791468031,
1784		−STORE, 47884789809152, 47884791152639,
1785		−ERASE, 47884789809152, 47884791152639,
1786		−STORE, 47884789809152, 47884791152639,
1787		−STORE, 47884791463936, 47884791468031,
1788		−STORE, 47884791152640, 47884791463935,
1789		−ERASE, 47884791152640, 47884791463935,
1790		−STORE, 47884791152640, 47884791463935,
1791		−STORE, 47884791492608, 47884791508991,
1792		−STORE, 47884791468032, 47884791492607,
1793		−ERASE, 47884791468032, 47884791492607,
1794		−STORE, 47884791468032, 47884791492607,
1795		−ERASE, 47884791492608, 47884791508991,
1796		−STORE, 47884791492608, 47884791508991,
1797		−STORE, 47884791508992, 47884791644159,
1798		−ERASE, 47884791508992, 47884791644159,
1799		−STORE, 47884791508992, 47884791533567,
1800		−STORE, 47884791533568, 47884791644159,
1801		−STORE, 47884791595008, 47884791644159,
1802		−STORE, 47884791533568, 47884791595007,
1803		−ERASE, 47884791533568, 47884791595007,
1804		−STORE, 47884791533568, 47884791595007,
1805		−STORE, 47884791619584, 47884791644159,
1806		−STORE, 47884791595008, 47884791619583,
1807		−ERASE, 47884791595008, 47884791619583,
1808		−STORE, 47884791595008, 47884791644159,
1809		−ERASE, 47884791595008, 47884791644159,
1810		−STORE, 47884791595008, 47884791619583,
1811		−STORE, 47884791619584, 47884791644159,
1812		−STORE, 47884791627776, 47884791644159,
1813		−STORE, 47884791619584, 47884791627775,
1814		−ERASE, 47884791619584, 47884791627775,
1815		−STORE, 47884791619584, 47884791627775,
1816		−ERASE, 47884791627776, 47884791644159,
1817		−STORE, 47884791627776, 47884791644159,
1818		−STORE, 47884791644160, 47884791664639,
1819		−ERASE, 47884791644160, 47884791664639,
1820		−STORE, 47884791644160, 47884791648255,
1821		−STORE, 47884791648256, 47884791664639,
1822		−STORE, 47884791652352, 47884791664639,
1823		−STORE, 47884791648256, 47884791652351,
1824		−ERASE, 47884791648256, 47884791652351,
1825		−STORE, 47884791648256, 47884791652351,
1826		−STORE, 47884791656448, 47884791664639,
1827		−STORE, 47884791652352, 47884791656447,
1828		−ERASE, 47884791652352, 47884791656447,
1829		−STORE, 47884791652352, 47884791664639,
1830		−ERASE, 47884791652352, 47884791664639,
1831		−STORE, 47884791652352, 47884791656447,
1832		−STORE, 47884791656448, 47884791664639,
1833		−ERASE, 47884791656448, 47884791664639,
1834		−STORE, 47884791656448, 47884791664639,
1835		−STORE, 47884791664640, 47884791672831,
1836		−ERASE, 47884791468032, 47884791492607,
1837		−STORE, 47884791468032, 47884791484415,
1838		−STORE, 47884791484416, 47884791492607,
1839		−ERASE, 47884791656448, 47884791664639,
1840		−STORE, 47884791656448, 47884791660543,
1841		−STORE, 47884791660544, 47884791664639,
1842		−ERASE, 47884791619584, 47884791627775,
1843		−STORE, 47884791619584, 47884791623679,
1844		−STORE, 47884791623680, 47884791627775,
1845		− };
	947	+ int i, val, val2;
	948	+ unsigned long r[] = {
	949	+ 10, 15,
	950	+ 20, 25,
	951	+ 17, 22, /* Overlaps previous range. */
	952	+ 9, 1000, /* Huge. */
	953	+ 100, 200,
	954	+ 45, 168,
	955	+ 118, 128,
	956	+ };
1846	957
1847		− unsigned long set6[] = {
1848		−STORE, 140737488347136, 140737488351231,
1849		−STORE, 140722999021568, 140737488351231,
1850		−ERASE, 140722999021568, 140737488351231,
1851		−STORE, 140722999021568, 140722999025663,
1852		−STORE, 94901500268544, 94901500440575,
1853		−ERASE, 94901500268544, 94901500440575,
1854		−STORE, 94901500268544, 94901500284927,
1855		−STORE, 94901500284928, 94901500440575,
1856		−ERASE, 94901500284928, 94901500440575,
1857		−STORE, 94901500284928, 94901500387327,
1858		−STORE, 94901500387328, 94901500428287,
1859		−STORE, 94901500428288, 94901500440575,
1860		−STORE, 47430426660864, 47430426832895,
1861		−ERASE, 47430426660864, 47430426832895,
1862		−STORE, 47430426660864, 47430426664959,
1863		−STORE, 47430426664960, 47430426832895,
1864		−ERASE, 47430426664960, 47430426832895,
1865		−STORE, 47430426664960, 47430426787839,
1866		−STORE, 47430426787840, 47430426820607,
1867		−STORE, 47430426820608, 47430426828799,
1868		−STORE, 47430426828800, 47430426832895,
1869		−STORE, 140722999115776, 140722999119871,
1870		−STORE, 140722999103488, 140722999115775,
1871		−STORE, 47430426832896, 47430426841087,
1872		−STORE, 47430426841088, 47430426849279,
1873		−STORE, 47430426849280, 47430427013119,
1874		−ERASE, 47430426849280, 47430427013119,
1875		−STORE, 47430426849280, 47430426861567,
1876		−STORE, 47430426861568, 47430427013119,
1877		−STORE, 47430426959872, 47430427013119,
1878		−STORE, 47430426861568, 47430426959871,
1879		−ERASE, 47430426861568, 47430426959871,
1880		−STORE, 47430426861568, 47430426959871,
1881		−STORE, 47430427004928, 47430427013119,
1882		−STORE, 47430426959872, 47430427004927,
1883		−ERASE, 47430426959872, 47430427004927,
1884		−STORE, 47430426959872, 47430427013119,
1885		−ERASE, 47430426959872, 47430427013119,
1886		−STORE, 47430426959872, 47430427004927,
1887		−STORE, 47430427004928, 47430427013119,
1888		−ERASE, 47430427004928, 47430427013119,
1889		−STORE, 47430427004928, 47430427013119,
1890		−STORE, 47430427013120, 47430430064639,
1891		−STORE, 47430427557888, 47430430064639,
1892		−STORE, 47430427013120, 47430427557887,
1893		−ERASE, 47430427557888, 47430430064639,
1894		−STORE, 47430427557888, 47430429843455,
1895		−STORE, 47430429843456, 47430430064639,
1896		−STORE, 47430429253632, 47430429843455,
1897		−STORE, 47430427557888, 47430429253631,
1898		−ERASE, 47430427557888, 47430429253631,
1899		−STORE, 47430427557888, 47430429253631,
1900		−STORE, 47430429839360, 47430429843455,
1901		−STORE, 47430429253632, 47430429839359,
1902		−ERASE, 47430429253632, 47430429839359,
1903		−STORE, 47430429253632, 47430429839359,
1904		−STORE, 47430430048256, 47430430064639,
1905		−STORE, 47430429843456, 47430430048255,
1906		−ERASE, 47430429843456, 47430430048255,
1907		−STORE, 47430429843456, 47430430048255,
1908		−ERASE, 47430430048256, 47430430064639,
1909		−STORE, 47430430048256, 47430430064639,
1910		−STORE, 47430430064640, 47430431903743,
1911		−STORE, 47430430203904, 47430431903743,
1912		−STORE, 47430430064640, 47430430203903,
1913		−ERASE, 47430430203904, 47430431903743,
1914		−STORE, 47430430203904, 47430431862783,
1915		−STORE, 47430431862784, 47430431903743,
1916		−STORE, 47430431547392, 47430431862783,
1917		−STORE, 47430430203904, 47430431547391,
1918		−ERASE, 47430430203904, 47430431547391,
1919		−STORE, 47430430203904, 47430431547391,
1920		−STORE, 47430431858688, 47430431862783,
1921		−STORE, 47430431547392, 47430431858687,
1922		−ERASE, 47430431547392, 47430431858687,
1923		−STORE, 47430431547392, 47430431858687,
1924		−STORE, 47430431887360, 47430431903743,
1925		−STORE, 47430431862784, 47430431887359,
1926		−ERASE, 47430431862784, 47430431887359,
1927		−STORE, 47430431862784, 47430431887359,
1928		−ERASE, 47430431887360, 47430431903743,
1929		−STORE, 47430431887360, 47430431903743,
1930		−STORE, 47430431903744, 47430432038911,
1931		−ERASE, 47430431903744, 47430432038911,
1932		−STORE, 47430431903744, 47430431928319,
1933		−STORE, 47430431928320, 47430432038911,
1934		−STORE, 47430431989760, 47430432038911,
1935		−STORE, 47430431928320, 47430431989759,
1936		−ERASE, 47430431928320, 47430431989759,
1937		−STORE, 47430431928320, 47430431989759,
1938		−STORE, 47430432014336, 47430432038911,
1939		−STORE, 47430431989760, 47430432014335,
1940		−ERASE, 47430431989760, 47430432014335,
1941		−STORE, 47430431989760, 47430432038911,
1942		−ERASE, 47430431989760, 47430432038911,
1943		−STORE, 47430431989760, 47430432014335,
1944		−STORE, 47430432014336, 47430432038911,
1945		−STORE, 47430432022528, 47430432038911,
1946		−STORE, 47430432014336, 47430432022527,
1947		−ERASE, 47430432014336, 47430432022527,
1948		−STORE, 47430432014336, 47430432022527,
1949		−ERASE, 47430432022528, 47430432038911,
1950		−STORE, 47430432022528, 47430432038911,
1951		−STORE, 47430432038912, 47430432059391,
1952		−ERASE, 47430432038912, 47430432059391,
1953		−STORE, 47430432038912, 47430432043007,
1954		−STORE, 47430432043008, 47430432059391,
1955		−STORE, 47430432047104, 47430432059391,
1956		−STORE, 47430432043008, 47430432047103,
1957		−ERASE, 47430432043008, 47430432047103,
1958		−STORE, 47430432043008, 47430432047103,
1959		−STORE, 47430432051200, 47430432059391,
1960		−STORE, 47430432047104, 47430432051199,
1961		−ERASE, 47430432047104, 47430432051199,
1962		−STORE, 47430432047104, 47430432059391,
1963		−ERASE, 47430432047104, 47430432059391,
1964		−STORE, 47430432047104, 47430432051199,
1965		−STORE, 47430432051200, 47430432059391,
1966		−ERASE, 47430432051200, 47430432059391,
1967		−STORE, 47430432051200, 47430432059391,
1968		−STORE, 47430432059392, 47430432067583,
1969		−ERASE, 47430431862784, 47430431887359,
1970		−STORE, 47430431862784, 47430431879167,
1971		−STORE, 47430431879168, 47430431887359,
1972		−ERASE, 47430432051200, 47430432059391,
1973		−STORE, 47430432051200, 47430432055295,
1974		−STORE, 47430432055296, 47430432059391,
1975		−ERASE, 47430432014336, 47430432022527,
1976		−STORE, 47430432014336, 47430432018431,
1977		−STORE, 47430432018432, 47430432022527,
1978		− };
1979		− unsigned long set7[] = {
1980		−STORE, 140737488347136, 140737488351231,
1981		−STORE, 140729808330752, 140737488351231,
1982		−ERASE, 140729808330752, 140737488351231,
1983		−STORE, 140729808330752, 140729808334847,
1984		−STORE, 94629632020480, 94629632192511,
1985		−ERASE, 94629632020480, 94629632192511,
1986		−STORE, 94629632020480, 94629632036863,
1987		−STORE, 94629632036864, 94629632192511,
1988		−ERASE, 94629632036864, 94629632192511,
1989		−STORE, 94629632036864, 94629632139263,
1990		−STORE, 94629632139264, 94629632180223,
1991		−STORE, 94629632180224, 94629632192511,
1992		−STORE, 47439981776896, 47439981948927,
1993		−ERASE, 47439981776896, 47439981948927,
1994		−STORE, 47439981776896, 47439981780991,
1995		−STORE, 47439981780992, 47439981948927,
1996		−ERASE, 47439981780992, 47439981948927,
1997		−STORE, 47439981780992, 47439981903871,
1998		−STORE, 47439981903872, 47439981936639,
1999		−STORE, 47439981936640, 47439981944831,
2000		−STORE, 47439981944832, 47439981948927,
2001		−STORE, 140729808474112, 140729808478207,
2002		−STORE, 140729808461824, 140729808474111,
2003		−STORE, 47439981948928, 47439981957119,
2004		−STORE, 47439981957120, 47439981965311,
2005		−STORE, 47439981965312, 47439982129151,
2006		−ERASE, 47439981965312, 47439982129151,
2007		−STORE, 47439981965312, 47439981977599,
2008		−STORE, 47439981977600, 47439982129151,
2009		−STORE, 47439982075904, 47439982129151,
2010		−STORE, 47439981977600, 47439982075903,
2011		−ERASE, 47439981977600, 47439982075903,
2012		−STORE, 47439981977600, 47439982075903,
2013		−STORE, 47439982120960, 47439982129151,
2014		−STORE, 47439982075904, 47439982120959,
2015		−ERASE, 47439982075904, 47439982120959,
2016		−STORE, 47439982075904, 47439982129151,
2017		−ERASE, 47439982075904, 47439982129151,
2018		−STORE, 47439982075904, 47439982120959,
2019		−STORE, 47439982120960, 47439982129151,
2020		−ERASE, 47439982120960, 47439982129151,
2021		−STORE, 47439982120960, 47439982129151,
2022		−STORE, 47439982129152, 47439985180671,
2023		−STORE, 47439982673920, 47439985180671,
2024		−STORE, 47439982129152, 47439982673919,
2025		−ERASE, 47439982673920, 47439985180671,
2026		−STORE, 47439982673920, 47439984959487,
2027		−STORE, 47439984959488, 47439985180671,
2028		−STORE, 47439984369664, 47439984959487,
2029		−STORE, 47439982673920, 47439984369663,
2030		−ERASE, 47439982673920, 47439984369663,
2031		−STORE, 47439982673920, 47439984369663,
2032		−STORE, 47439984955392, 47439984959487,
2033		−STORE, 47439984369664, 47439984955391,
2034		−ERASE, 47439984369664, 47439984955391,
2035		−STORE, 47439984369664, 47439984955391,
2036		−STORE, 47439985164288, 47439985180671,
2037		−STORE, 47439984959488, 47439985164287,
2038		−ERASE, 47439984959488, 47439985164287,
2039		−STORE, 47439984959488, 47439985164287,
2040		−ERASE, 47439985164288, 47439985180671,
2041		−STORE, 47439985164288, 47439985180671,
2042		−STORE, 47439985180672, 47439987019775,
2043		−STORE, 47439985319936, 47439987019775,
2044		−STORE, 47439985180672, 47439985319935,
2045		−ERASE, 47439985319936, 47439987019775,
2046		−STORE, 47439985319936, 47439986978815,
2047		−STORE, 47439986978816, 47439987019775,
2048		−STORE, 47439986663424, 47439986978815,
2049		−STORE, 47439985319936, 47439986663423,
2050		−ERASE, 47439985319936, 47439986663423,
2051		−STORE, 47439985319936, 47439986663423,
2052		−STORE, 47439986974720, 47439986978815,
2053		−STORE, 47439986663424, 47439986974719,
2054		−ERASE, 47439986663424, 47439986974719,
2055		−STORE, 47439986663424, 47439986974719,
2056		−STORE, 47439987003392, 47439987019775,
2057		−STORE, 47439986978816, 47439987003391,
2058		−ERASE, 47439986978816, 47439987003391,
2059		−STORE, 47439986978816, 47439987003391,
2060		−ERASE, 47439987003392, 47439987019775,
2061		−STORE, 47439987003392, 47439987019775,
2062		−STORE, 47439987019776, 47439987154943,
2063		−ERASE, 47439987019776, 47439987154943,
2064		−STORE, 47439987019776, 47439987044351,
2065		−STORE, 47439987044352, 47439987154943,
2066		−STORE, 47439987105792, 47439987154943,
2067		−STORE, 47439987044352, 47439987105791,
2068		−ERASE, 47439987044352, 47439987105791,
2069		−STORE, 47439987044352, 47439987105791,
2070		−STORE, 47439987130368, 47439987154943,
2071		−STORE, 47439987105792, 47439987130367,
2072		−ERASE, 47439987105792, 47439987130367,
2073		−STORE, 47439987105792, 47439987154943,
2074		−ERASE, 47439987105792, 47439987154943,
2075		−STORE, 47439987105792, 47439987130367,
2076		−STORE, 47439987130368, 47439987154943,
2077		−STORE, 47439987138560, 47439987154943,
2078		−STORE, 47439987130368, 47439987138559,
2079		−ERASE, 47439987130368, 47439987138559,
2080		−STORE, 47439987130368, 47439987138559,
2081		−ERASE, 47439987138560, 47439987154943,
2082		−STORE, 47439987138560, 47439987154943,
2083		−STORE, 47439987154944, 47439987175423,
2084		−ERASE, 47439987154944, 47439987175423,
2085		−STORE, 47439987154944, 47439987159039,
2086		−STORE, 47439987159040, 47439987175423,
2087		−STORE, 47439987163136, 47439987175423,
2088		−STORE, 47439987159040, 47439987163135,
2089		−ERASE, 47439987159040, 47439987163135,
2090		−STORE, 47439987159040, 47439987163135,
2091		−STORE, 47439987167232, 47439987175423,
2092		−STORE, 47439987163136, 47439987167231,
2093		−ERASE, 47439987163136, 47439987167231,
2094		−STORE, 47439987163136, 47439987175423,
2095		−ERASE, 47439987163136, 47439987175423,
2096		−STORE, 47439987163136, 47439987167231,
2097		−STORE, 47439987167232, 47439987175423,
2098		−ERASE, 47439987167232, 47439987175423,
2099		−STORE, 47439987167232, 47439987175423,
2100		−STORE, 47439987175424, 47439987183615,
2101		−ERASE, 47439986978816, 47439987003391,
2102		−STORE, 47439986978816, 47439986995199,
2103		−STORE, 47439986995200, 47439987003391,
2104		−ERASE, 47439987167232, 47439987175423,
2105		−STORE, 47439987167232, 47439987171327,
2106		−STORE, 47439987171328, 47439987175423,
2107		−ERASE, 47439987130368, 47439987138559,
2108		−STORE, 47439987130368, 47439987134463,
2109		−STORE, 47439987134464, 47439987138559,
2110		− };
2111		− unsigned long set8[] = {
2112		−STORE, 140737488347136, 140737488351231,
2113		−STORE, 140722482974720, 140737488351231,
2114		−ERASE, 140722482974720, 140737488351231,
2115		−STORE, 140722482974720, 140722482978815,
2116		−STORE, 94121505034240, 94121505206271,
2117		−ERASE, 94121505034240, 94121505206271,
2118		−STORE, 94121505034240, 94121505050623,
2119		−STORE, 94121505050624, 94121505206271,
2120		−ERASE, 94121505050624, 94121505206271,
2121		−STORE, 94121505050624, 94121505153023,
2122		−STORE, 94121505153024, 94121505193983,
2123		−STORE, 94121505193984, 94121505206271,
2124		−STORE, 47708483284992, 47708483457023,
2125		−ERASE, 47708483284992, 47708483457023,
2126		−STORE, 47708483284992, 47708483289087,
2127		−STORE, 47708483289088, 47708483457023,
2128		−ERASE, 47708483289088, 47708483457023,
2129		−STORE, 47708483289088, 47708483411967,
2130		−STORE, 47708483411968, 47708483444735,
2131		−STORE, 47708483444736, 47708483452927,
2132		−STORE, 47708483452928, 47708483457023,
2133		−STORE, 140722483142656, 140722483146751,
2134		−STORE, 140722483130368, 140722483142655,
2135		−STORE, 47708483457024, 47708483465215,
2136		−STORE, 47708483465216, 47708483473407,
2137		−STORE, 47708483473408, 47708483637247,
2138		−ERASE, 47708483473408, 47708483637247,
2139		−STORE, 47708483473408, 47708483485695,
2140		−STORE, 47708483485696, 47708483637247,
2141		−STORE, 47708483584000, 47708483637247,
2142		−STORE, 47708483485696, 47708483583999,
2143		−ERASE, 47708483485696, 47708483583999,
2144		−STORE, 47708483485696, 47708483583999,
2145		−STORE, 47708483629056, 47708483637247,
2146		−STORE, 47708483584000, 47708483629055,
2147		−ERASE, 47708483584000, 47708483629055,
2148		−STORE, 47708483584000, 47708483637247,
2149		−ERASE, 47708483584000, 47708483637247,
2150		−STORE, 47708483584000, 47708483629055,
2151		−STORE, 47708483629056, 47708483637247,
2152		−ERASE, 47708483629056, 47708483637247,
2153		−STORE, 47708483629056, 47708483637247,
2154		−STORE, 47708483637248, 47708486688767,
2155		−STORE, 47708484182016, 47708486688767,
2156		−STORE, 47708483637248, 47708484182015,
2157		−ERASE, 47708484182016, 47708486688767,
2158		−STORE, 47708484182016, 47708486467583,
2159		−STORE, 47708486467584, 47708486688767,
2160		−STORE, 47708485877760, 47708486467583,
2161		−STORE, 47708484182016, 47708485877759,
2162		−ERASE, 47708484182016, 47708485877759,
2163		−STORE, 47708484182016, 47708485877759,
2164		−STORE, 47708486463488, 47708486467583,
2165		−STORE, 47708485877760, 47708486463487,
2166		−ERASE, 47708485877760, 47708486463487,
2167		−STORE, 47708485877760, 47708486463487,
2168		−STORE, 47708486672384, 47708486688767,
2169		−STORE, 47708486467584, 47708486672383,
2170		−ERASE, 47708486467584, 47708486672383,
2171		−STORE, 47708486467584, 47708486672383,
2172		−ERASE, 47708486672384, 47708486688767,
2173		−STORE, 47708486672384, 47708486688767,
2174		−STORE, 47708486688768, 47708488527871,
2175		−STORE, 47708486828032, 47708488527871,
2176		−STORE, 47708486688768, 47708486828031,
2177		−ERASE, 47708486828032, 47708488527871,
2178		−STORE, 47708486828032, 47708488486911,
2179		−STORE, 47708488486912, 47708488527871,
2180		−STORE, 47708488171520, 47708488486911,
2181		−STORE, 47708486828032, 47708488171519,
2182		−ERASE, 47708486828032, 47708488171519,
2183		−STORE, 47708486828032, 47708488171519,
2184		−STORE, 47708488482816, 47708488486911,
2185		−STORE, 47708488171520, 47708488482815,
2186		−ERASE, 47708488171520, 47708488482815,
2187		−STORE, 47708488171520, 47708488482815,
2188		−STORE, 47708488511488, 47708488527871,
2189		−STORE, 47708488486912, 47708488511487,
2190		−ERASE, 47708488486912, 47708488511487,
2191		−STORE, 47708488486912, 47708488511487,
2192		−ERASE, 47708488511488, 47708488527871,
2193		−STORE, 47708488511488, 47708488527871,
2194		−STORE, 47708488527872, 47708488663039,
2195		−ERASE, 47708488527872, 47708488663039,
2196		−STORE, 47708488527872, 47708488552447,
2197		−STORE, 47708488552448, 47708488663039,
2198		−STORE, 47708488613888, 47708488663039,
2199		−STORE, 47708488552448, 47708488613887,
2200		−ERASE, 47708488552448, 47708488613887,
2201		−STORE, 47708488552448, 47708488613887,
2202		−STORE, 47708488638464, 47708488663039,
2203		−STORE, 47708488613888, 47708488638463,
2204		−ERASE, 47708488613888, 47708488638463,
2205		−STORE, 47708488613888, 47708488663039,
2206		−ERASE, 47708488613888, 47708488663039,
2207		−STORE, 47708488613888, 47708488638463,
2208		−STORE, 47708488638464, 47708488663039,
2209		−STORE, 47708488646656, 47708488663039,
2210		−STORE, 47708488638464, 47708488646655,
2211		−ERASE, 47708488638464, 47708488646655,
2212		−STORE, 47708488638464, 47708488646655,
2213		−ERASE, 47708488646656, 47708488663039,
2214		−STORE, 47708488646656, 47708488663039,
2215		−STORE, 47708488663040, 47708488683519,
2216		−ERASE, 47708488663040, 47708488683519,
2217		−STORE, 47708488663040, 47708488667135,
2218		−STORE, 47708488667136, 47708488683519,
2219		−STORE, 47708488671232, 47708488683519,
2220		−STORE, 47708488667136, 47708488671231,
2221		−ERASE, 47708488667136, 47708488671231,
2222		−STORE, 47708488667136, 47708488671231,
2223		−STORE, 47708488675328, 47708488683519,
2224		−STORE, 47708488671232, 47708488675327,
2225		−ERASE, 47708488671232, 47708488675327,
2226		−STORE, 47708488671232, 47708488683519,
2227		−ERASE, 47708488671232, 47708488683519,
2228		−STORE, 47708488671232, 47708488675327,
2229		−STORE, 47708488675328, 47708488683519,
2230		−ERASE, 47708488675328, 47708488683519,
2231		−STORE, 47708488675328, 47708488683519,
2232		−STORE, 47708488683520, 47708488691711,
2233		−ERASE, 47708488486912, 47708488511487,
2234		−STORE, 47708488486912, 47708488503295,
2235		−STORE, 47708488503296, 47708488511487,
2236		−ERASE, 47708488675328, 47708488683519,
2237		−STORE, 47708488675328, 47708488679423,
2238		−STORE, 47708488679424, 47708488683519,
2239		−ERASE, 47708488638464, 47708488646655,
2240		−STORE, 47708488638464, 47708488642559,
2241		−STORE, 47708488642560, 47708488646655,
2242		− };
	958	+ MT_BUG_ON(mt, !mtree_empty(mt));
	959	+ check_insert_range(mt, r[0], r[1], xa_mk_value(r[0]), 0);
	960	+ check_insert_range(mt, r[2], r[3], xa_mk_value(r[2]), 0);
	961	+ check_insert_range(mt, r[4], r[5], xa_mk_value(r[4]), -EEXIST);
	962	+ MT_BUG_ON(mt, !mt_height(mt));
	963	+ /* Store */
	964	+ check_store_range(mt, r[4], r[5], xa_mk_value(r[4]), 0);
	965	+ check_store_range(mt, r[6], r[7], xa_mk_value(r[6]), 0);
	966	+ check_store_range(mt, r[8], r[9], xa_mk_value(r[8]), 0);
	967	+ MT_BUG_ON(mt, !mt_height(mt));
	968	+ mtree_destroy(mt);
	969	+ MT_BUG_ON(mt, mt_height(mt));
2243	970
2244		− unsigned long set9[] = {
2245		−STORE, 140737488347136, 140737488351231,
2246		−STORE, 140736427839488, 140737488351231,
2247		−ERASE, 140736427839488, 140736427839488,
2248		−STORE, 140736427839488, 140736427843583,
2249		−STORE, 94071213395968, 94071213567999,
2250		−ERASE, 94071213395968, 94071213395968,
2251		−STORE, 94071213395968, 94071213412351,
2252		−STORE, 94071213412352, 94071213567999,
2253		−ERASE, 94071213412352, 94071213412352,
2254		−STORE, 94071213412352, 94071213514751,
2255		−STORE, 94071213514752, 94071213555711,
2256		−STORE, 94071213555712, 94071213567999,
2257		−STORE, 139968410644480, 139968410816511,
2258		−ERASE, 139968410644480, 139968410644480,
2259		−STORE, 139968410644480, 139968410648575,
2260		−STORE, 139968410648576, 139968410816511,
2261		−ERASE, 139968410648576, 139968410648576,
2262		−STORE, 139968410648576, 139968410771455,
2263		−STORE, 139968410771456, 139968410804223,
2264		−STORE, 139968410804224, 139968410812415,
2265		−STORE, 139968410812416, 139968410816511,
2266		−STORE, 140736429277184, 140736429281279,
2267		−STORE, 140736429264896, 140736429277183,
2268		−STORE, 47664384352256, 47664384360447,
2269		−STORE, 47664384360448, 47664384368639,
2270		−STORE, 47664384368640, 47664384532479,
2271		−ERASE, 47664384368640, 47664384368640,
2272		−STORE, 47664384368640, 47664384380927,
2273		−STORE, 47664384380928, 47664384532479,
2274		−STORE, 47664384479232, 47664384532479,
2275		−STORE, 47664384380928, 47664384479231,
2276		−ERASE, 47664384380928, 47664384380928,
2277		−STORE, 47664384380928, 47664384479231,
2278		−STORE, 47664384524288, 47664384532479,
2279		−STORE, 47664384479232, 47664384524287,
2280		−ERASE, 47664384479232, 47664384479232,
2281		−STORE, 47664384479232, 47664384532479,
2282		−ERASE, 47664384479232, 47664384479232,
2283		−STORE, 47664384479232, 47664384524287,
2284		−STORE, 47664384524288, 47664384532479,
2285		−ERASE, 47664384524288, 47664384524288,
2286		−STORE, 47664384524288, 47664384532479,
2287		−STORE, 47664384532480, 47664387583999,
2288		−STORE, 47664385077248, 47664387583999,
2289		−STORE, 47664384532480, 47664385077247,
2290		−ERASE, 47664385077248, 47664385077248,
2291		−STORE, 47664385077248, 47664387362815,
2292		−STORE, 47664387362816, 47664387583999,
2293		−STORE, 47664386772992, 47664387362815,
2294		−STORE, 47664385077248, 47664386772991,
2295		−ERASE, 47664385077248, 47664385077248,
2296		−STORE, 47664385077248, 47664386772991,
2297		−STORE, 47664387358720, 47664387362815,
2298		−STORE, 47664386772992, 47664387358719,
2299		−ERASE, 47664386772992, 47664386772992,
2300		−STORE, 47664386772992, 47664387358719,
2301		−STORE, 47664387567616, 47664387583999,
2302		−STORE, 47664387362816, 47664387567615,
2303		−ERASE, 47664387362816, 47664387362816,
2304		−STORE, 47664387362816, 47664387567615,
2305		−ERASE, 47664387567616, 47664387567616,
2306		−STORE, 47664387567616, 47664387583999,
2307		−STORE, 47664387584000, 47664389423103,
2308		−STORE, 47664387723264, 47664389423103,
2309		−STORE, 47664387584000, 47664387723263,
2310		−ERASE, 47664387723264, 47664387723264,
2311		−STORE, 47664387723264, 47664389382143,
2312		−STORE, 47664389382144, 47664389423103,
2313		−STORE, 47664389066752, 47664389382143,
2314		−STORE, 47664387723264, 47664389066751,
2315		−ERASE, 47664387723264, 47664387723264,
2316		−STORE, 47664387723264, 47664389066751,
2317		−STORE, 47664389378048, 47664389382143,
2318		−STORE, 47664389066752, 47664389378047,
2319		−ERASE, 47664389066752, 47664389066752,
2320		−STORE, 47664389066752, 47664389378047,
2321		−STORE, 47664389406720, 47664389423103,
2322		−STORE, 47664389382144, 47664389406719,
2323		−ERASE, 47664389382144, 47664389382144,
2324		−STORE, 47664389382144, 47664389406719,
2325		−ERASE, 47664389406720, 47664389406720,
2326		−STORE, 47664389406720, 47664389423103,
2327		−STORE, 47664389423104, 47664389558271,
2328		−ERASE, 47664389423104, 47664389423104,
2329		−STORE, 47664389423104, 47664389447679,
2330		−STORE, 47664389447680, 47664389558271,
2331		−STORE, 47664389509120, 47664389558271,
2332		−STORE, 47664389447680, 47664389509119,
2333		−ERASE, 47664389447680, 47664389447680,
2334		−STORE, 47664389447680, 47664389509119,
2335		−STORE, 47664389533696, 47664389558271,
2336		−STORE, 47664389509120, 47664389533695,
2337		−ERASE, 47664389509120, 47664389509120,
2338		−STORE, 47664389509120, 47664389558271,
2339		−ERASE, 47664389509120, 47664389509120,
2340		−STORE, 47664389509120, 47664389533695,
2341		−STORE, 47664389533696, 47664389558271,
2342		−STORE, 47664389541888, 47664389558271,
2343		−STORE, 47664389533696, 47664389541887,
2344		−ERASE, 47664389533696, 47664389533696,
2345		−STORE, 47664389533696, 47664389541887,
2346		−ERASE, 47664389541888, 47664389541888,
2347		−STORE, 47664389541888, 47664389558271,
2348		−STORE, 47664389558272, 47664389578751,
2349		−ERASE, 47664389558272, 47664389558272,
2350		−STORE, 47664389558272, 47664389562367,
2351		−STORE, 47664389562368, 47664389578751,
2352		−STORE, 47664389566464, 47664389578751,
2353		−STORE, 47664389562368, 47664389566463,
2354		−ERASE, 47664389562368, 47664389562368,
2355		−STORE, 47664389562368, 47664389566463,
2356		−STORE, 47664389570560, 47664389578751,
2357		−STORE, 47664389566464, 47664389570559,
2358		−ERASE, 47664389566464, 47664389566464,
2359		−STORE, 47664389566464, 47664389578751,
2360		−ERASE, 47664389566464, 47664389566464,
2361		−STORE, 47664389566464, 47664389570559,
2362		−STORE, 47664389570560, 47664389578751,
2363		−ERASE, 47664389570560, 47664389570560,
2364		−STORE, 47664389570560, 47664389578751,
2365		−STORE, 47664389578752, 47664389586943,
2366		−ERASE, 47664389382144, 47664389382144,
2367		−STORE, 47664389382144, 47664389398527,
2368		−STORE, 47664389398528, 47664389406719,
2369		−ERASE, 47664389570560, 47664389570560,
2370		−STORE, 47664389570560, 47664389574655,
2371		−STORE, 47664389574656, 47664389578751,
2372		−ERASE, 47664389533696, 47664389533696,
2373		−STORE, 47664389533696, 47664389537791,
2374		−STORE, 47664389537792, 47664389541887,
2375		−ERASE, 47664387362816, 47664387362816,
2376		−STORE, 47664387362816, 47664387559423,
2377		−STORE, 47664387559424, 47664387567615,
2378		−ERASE, 47664384524288, 47664384524288,
2379		−STORE, 47664384524288, 47664384528383,
2380		−STORE, 47664384528384, 47664384532479,
2381		−ERASE, 94071213555712, 94071213555712,
2382		−STORE, 94071213555712, 94071213563903,
2383		−STORE, 94071213563904, 94071213567999,
2384		−ERASE, 139968410804224, 139968410804224,
2385		−STORE, 139968410804224, 139968410808319,
2386		−STORE, 139968410808320, 139968410812415,
2387		−ERASE, 47664384352256, 47664384352256,
2388		−STORE, 94071244402688, 94071244537855,
2389		−STORE, 140737488347136, 140737488351231,
2390		−STORE, 140728271503360, 140737488351231,
2391		−ERASE, 140728271503360, 140728271503360,
2392		−STORE, 140728271503360, 140728271507455,
2393		−STORE, 94410361982976, 94410362155007,
2394		−ERASE, 94410361982976, 94410361982976,
2395		−STORE, 94410361982976, 94410361999359,
2396		−STORE, 94410361999360, 94410362155007,
2397		−ERASE, 94410361999360, 94410361999360,
2398		−STORE, 94410361999360, 94410362101759,
2399		−STORE, 94410362101760, 94410362142719,
2400		−STORE, 94410362142720, 94410362155007,
2401		−STORE, 140351953997824, 140351954169855,
2402		−ERASE, 140351953997824, 140351953997824,
2403		−STORE, 140351953997824, 140351954001919,
2404		−STORE, 140351954001920, 140351954169855,
2405		−ERASE, 140351954001920, 140351954001920,
2406		−STORE, 140351954001920, 140351954124799,
2407		−STORE, 140351954124800, 140351954157567,
2408		−STORE, 140351954157568, 140351954165759,
2409		−STORE, 140351954165760, 140351954169855,
2410		−STORE, 140728272429056, 140728272433151,
2411		−STORE, 140728272416768, 140728272429055,
2412		−STORE, 47280840998912, 47280841007103,
2413		−STORE, 47280841007104, 47280841015295,
2414		−STORE, 47280841015296, 47280841179135,
2415		−ERASE, 47280841015296, 47280841015296,
2416		−STORE, 47280841015296, 47280841027583,
2417		−STORE, 47280841027584, 47280841179135,
2418		−STORE, 47280841125888, 47280841179135,
2419		−STORE, 47280841027584, 47280841125887,
2420		−ERASE, 47280841027584, 47280841027584,
2421		−STORE, 47280841027584, 47280841125887,
2422		−STORE, 47280841170944, 47280841179135,
2423		−STORE, 47280841125888, 47280841170943,
2424		−ERASE, 47280841125888, 47280841125888,
2425		−STORE, 47280841125888, 47280841179135,
2426		−ERASE, 47280841125888, 47280841125888,
2427		−STORE, 47280841125888, 47280841170943,
2428		−STORE, 47280841170944, 47280841179135,
2429		−ERASE, 47280841170944, 47280841170944,
2430		−STORE, 47280841170944, 47280841179135,
2431		−STORE, 47280841179136, 47280844230655,
2432		−STORE, 47280841723904, 47280844230655,
2433		−STORE, 47280841179136, 47280841723903,
2434		−ERASE, 47280841723904, 47280841723904,
2435		−STORE, 47280841723904, 47280844009471,
2436		−STORE, 47280844009472, 47280844230655,
2437		−STORE, 47280843419648, 47280844009471,
2438		−STORE, 47280841723904, 47280843419647,
2439		−ERASE, 47280841723904, 47280841723904,
2440		−STORE, 47280841723904, 47280843419647,
2441		−STORE, 47280844005376, 47280844009471,
2442		−STORE, 47280843419648, 47280844005375,
2443		−ERASE, 47280843419648, 47280843419648,
2444		−STORE, 47280843419648, 47280844005375,
2445		−STORE, 47280844214272, 47280844230655,
2446		−STORE, 47280844009472, 47280844214271,
2447		−ERASE, 47280844009472, 47280844009472,
2448		−STORE, 47280844009472, 47280844214271,
2449		−ERASE, 47280844214272, 47280844214272,
2450		−STORE, 47280844214272, 47280844230655,
2451		−STORE, 47280844230656, 47280846069759,
2452		−STORE, 47280844369920, 47280846069759,
2453		−STORE, 47280844230656, 47280844369919,
2454		−ERASE, 47280844369920, 47280844369920,
2455		−STORE, 47280844369920, 47280846028799,
2456		−STORE, 47280846028800, 47280846069759,
2457		−STORE, 47280845713408, 47280846028799,
2458		−STORE, 47280844369920, 47280845713407,
2459		−ERASE, 47280844369920, 47280844369920,
2460		−STORE, 47280844369920, 47280845713407,
2461		−STORE, 47280846024704, 47280846028799,
2462		−STORE, 47280845713408, 47280846024703,
2463		−ERASE, 47280845713408, 47280845713408,
2464		−STORE, 47280845713408, 47280846024703,
2465		−STORE, 47280846053376, 47280846069759,
2466		−STORE, 47280846028800, 47280846053375,
2467		−ERASE, 47280846028800, 47280846028800,
2468		−STORE, 47280846028800, 47280846053375,
2469		−ERASE, 47280846053376, 47280846053376,
2470		−STORE, 47280846053376, 47280846069759,
2471		−STORE, 47280846069760, 47280846204927,
2472		−ERASE, 47280846069760, 47280846069760,
2473		−STORE, 47280846069760, 47280846094335,
2474		−STORE, 47280846094336, 47280846204927,
2475		−STORE, 47280846155776, 47280846204927,
2476		−STORE, 47280846094336, 47280846155775,
2477		−ERASE, 47280846094336, 47280846094336,
2478		−STORE, 47280846094336, 47280846155775,
2479		−STORE, 47280846180352, 47280846204927,
2480		−STORE, 47280846155776, 47280846180351,
2481		−ERASE, 47280846155776, 47280846155776,
2482		−STORE, 47280846155776, 47280846204927,
2483		−ERASE, 47280846155776, 47280846155776,
2484		−STORE, 47280846155776, 47280846180351,
2485		−STORE, 47280846180352, 47280846204927,
2486		−STORE, 47280846188544, 47280846204927,
2487		−STORE, 47280846180352, 47280846188543,
2488		−ERASE, 47280846180352, 47280846180352,
2489		−STORE, 47280846180352, 47280846188543,
2490		−ERASE, 47280846188544, 47280846188544,
2491		−STORE, 47280846188544, 47280846204927,
2492		−STORE, 47280846204928, 47280846225407,
2493		−ERASE, 47280846204928, 47280846204928,
2494		−STORE, 47280846204928, 47280846209023,
2495		−STORE, 47280846209024, 47280846225407,
2496		−STORE, 47280846213120, 47280846225407,
2497		−STORE, 47280846209024, 47280846213119,
2498		−ERASE, 47280846209024, 47280846209024,
2499		−STORE, 47280846209024, 47280846213119,
2500		−STORE, 47280846217216, 47280846225407,
2501		−STORE, 47280846213120, 47280846217215,
2502		−ERASE, 47280846213120, 47280846213120,
2503		−STORE, 47280846213120, 47280846225407,
2504		−ERASE, 47280846213120, 47280846213120,
2505		−STORE, 47280846213120, 47280846217215,
2506		−STORE, 47280846217216, 47280846225407,
2507		−ERASE, 47280846217216, 47280846217216,
2508		−STORE, 47280846217216, 47280846225407,
2509		−STORE, 47280846225408, 47280846233599,
2510		−ERASE, 47280846028800, 47280846028800,
2511		−STORE, 47280846028800, 47280846045183,
2512		−STORE, 47280846045184, 47280846053375,
2513		−ERASE, 47280846217216, 47280846217216,
2514		−STORE, 47280846217216, 47280846221311,
2515		−STORE, 47280846221312, 47280846225407,
2516		−ERASE, 47280846180352, 47280846180352,
2517		−STORE, 47280846180352, 47280846184447,
2518		−STORE, 47280846184448, 47280846188543,
2519		−ERASE, 47280844009472, 47280844009472,
2520		−STORE, 47280844009472, 47280844206079,
2521		−STORE, 47280844206080, 47280844214271,
2522		−ERASE, 47280841170944, 47280841170944,
2523		−STORE, 47280841170944, 47280841175039,
2524		−STORE, 47280841175040, 47280841179135,
2525		−ERASE, 94410362142720, 94410362142720,
2526		−STORE, 94410362142720, 94410362150911,
2527		−STORE, 94410362150912, 94410362155007,
2528		−ERASE, 140351954157568, 140351954157568,
2529		−STORE, 140351954157568, 140351954161663,
2530		−STORE, 140351954161664, 140351954165759,
2531		−ERASE, 47280840998912, 47280840998912,
2532		−STORE, 94410379456512, 94410379591679,
2533		−STORE, 140737488347136, 140737488351231,
2534		−STORE, 140732946362368, 140737488351231,
2535		−ERASE, 140732946362368, 140732946362368,
2536		−STORE, 140732946362368, 140732946366463,
2537		−STORE, 94352937934848, 94352938106879,
2538		−ERASE, 94352937934848, 94352937934848,
2539		−STORE, 94352937934848, 94352937951231,
2540		−STORE, 94352937951232, 94352938106879,
2541		−ERASE, 94352937951232, 94352937951232,
2542		−STORE, 94352937951232, 94352938053631,
2543		−STORE, 94352938053632, 94352938094591,
2544		−STORE, 94352938094592, 94352938106879,
2545		−STORE, 140595518742528, 140595518914559,
2546		−ERASE, 140595518742528, 140595518742528,
2547		−STORE, 140595518742528, 140595518746623,
2548		−STORE, 140595518746624, 140595518914559,
2549		−ERASE, 140595518746624, 140595518746624,
2550		−STORE, 140595518746624, 140595518869503,
2551		−STORE, 140595518869504, 140595518902271,
2552		−STORE, 140595518902272, 140595518910463,
2553		−STORE, 140595518910464, 140595518914559,
2554		−STORE, 140732947468288, 140732947472383,
2555		−STORE, 140732947456000, 140732947468287,
2556		−STORE, 47037276254208, 47037276262399,
2557		−STORE, 47037276262400, 47037276270591,
2558		−STORE, 47037276270592, 47037276434431,
2559		−ERASE, 47037276270592, 47037276270592,
2560		−STORE, 47037276270592, 47037276282879,
2561		−STORE, 47037276282880, 47037276434431,
2562		−STORE, 47037276381184, 47037276434431,
2563		−STORE, 47037276282880, 47037276381183,
2564		−ERASE, 47037276282880, 47037276282880,
2565		−STORE, 47037276282880, 47037276381183,
2566		−STORE, 47037276426240, 47037276434431,
2567		−STORE, 47037276381184, 47037276426239,
2568		−ERASE, 47037276381184, 47037276381184,
2569		−STORE, 47037276381184, 47037276434431,
2570		−ERASE, 47037276381184, 47037276381184,
2571		−STORE, 47037276381184, 47037276426239,
2572		−STORE, 47037276426240, 47037276434431,
2573		−ERASE, 47037276426240, 47037276426240,
2574		−STORE, 47037276426240, 47037276434431,
2575		−STORE, 47037276434432, 47037279485951,
2576		−STORE, 47037276979200, 47037279485951,
2577		−STORE, 47037276434432, 47037276979199,
2578		−ERASE, 47037276979200, 47037276979200,
2579		−STORE, 47037276979200, 47037279264767,
2580		−STORE, 47037279264768, 47037279485951,
2581		−STORE, 47037278674944, 47037279264767,
2582		−STORE, 47037276979200, 47037278674943,
2583		−ERASE, 47037276979200, 47037276979200,
2584		−STORE, 47037276979200, 47037278674943,
2585		−STORE, 47037279260672, 47037279264767,
2586		−STORE, 47037278674944, 47037279260671,
2587		−ERASE, 47037278674944, 47037278674944,
2588		−STORE, 47037278674944, 47037279260671,
2589		−STORE, 47037279469568, 47037279485951,
2590		−STORE, 47037279264768, 47037279469567,
2591		−ERASE, 47037279264768, 47037279264768,
2592		−STORE, 47037279264768, 47037279469567,
2593		−ERASE, 47037279469568, 47037279469568,
2594		−STORE, 47037279469568, 47037279485951,
2595		−STORE, 47037279485952, 47037281325055,
2596		−STORE, 47037279625216, 47037281325055,
2597		−STORE, 47037279485952, 47037279625215,
2598		−ERASE, 47037279625216, 47037279625216,
2599		−STORE, 47037279625216, 47037281284095,
2600		−STORE, 47037281284096, 47037281325055,
2601		−STORE, 47037280968704, 47037281284095,
2602		−STORE, 47037279625216, 47037280968703,
2603		−ERASE, 47037279625216, 47037279625216,
2604		−STORE, 47037279625216, 47037280968703,
2605		−STORE, 47037281280000, 47037281284095,
2606		−STORE, 47037280968704, 47037281279999,
2607		−ERASE, 47037280968704, 47037280968704,
2608		−STORE, 47037280968704, 47037281279999,
2609		−STORE, 47037281308672, 47037281325055,
2610		−STORE, 47037281284096, 47037281308671,
2611		−ERASE, 47037281284096, 47037281284096,
2612		−STORE, 47037281284096, 47037281308671,
2613		−ERASE, 47037281308672, 47037281308672,
2614		−STORE, 47037281308672, 47037281325055,
2615		−STORE, 47037281325056, 47037281460223,
2616		−ERASE, 47037281325056, 47037281325056,
2617		−STORE, 47037281325056, 47037281349631,
2618		−STORE, 47037281349632, 47037281460223,
2619		−STORE, 47037281411072, 47037281460223,
2620		−STORE, 47037281349632, 47037281411071,
2621		−ERASE, 47037281349632, 47037281349632,
2622		−STORE, 47037281349632, 47037281411071,
2623		−STORE, 47037281435648, 47037281460223,
2624		−STORE, 47037281411072, 47037281435647,
2625		−ERASE, 47037281411072, 47037281411072,
2626		−STORE, 47037281411072, 47037281460223,
2627		−ERASE, 47037281411072, 47037281411072,
2628		−STORE, 47037281411072, 47037281435647,
2629		−STORE, 47037281435648, 47037281460223,
2630		−STORE, 47037281443840, 47037281460223,
2631		−STORE, 47037281435648, 47037281443839,
2632		−ERASE, 47037281435648, 47037281435648,
2633		−STORE, 47037281435648, 47037281443839,
2634		−ERASE, 47037281443840, 47037281443840,
2635		−STORE, 47037281443840, 47037281460223,
2636		−STORE, 47037281460224, 47037281480703,
2637		−ERASE, 47037281460224, 47037281460224,
2638		−STORE, 47037281460224, 47037281464319,
2639		−STORE, 47037281464320, 47037281480703,
2640		−STORE, 47037281468416, 47037281480703,
2641		−STORE, 47037281464320, 47037281468415,
2642		−ERASE, 47037281464320, 47037281464320,
2643		−STORE, 47037281464320, 47037281468415,
2644		−STORE, 47037281472512, 47037281480703,
2645		−STORE, 47037281468416, 47037281472511,
2646		−ERASE, 47037281468416, 47037281468416,
2647		−STORE, 47037281468416, 47037281480703,
2648		−ERASE, 47037281468416, 47037281468416,
2649		−STORE, 47037281468416, 47037281472511,
2650		−STORE, 47037281472512, 47037281480703,
2651		−ERASE, 47037281472512, 47037281472512,
2652		−STORE, 47037281472512, 47037281480703,
2653		−STORE, 47037281480704, 47037281488895,
2654		−ERASE, 47037281284096, 47037281284096,
2655		−STORE, 47037281284096, 47037281300479,
2656		−STORE, 47037281300480, 47037281308671,
2657		−ERASE, 47037281472512, 47037281472512,
2658		−STORE, 47037281472512, 47037281476607,
2659		−STORE, 47037281476608, 47037281480703,
2660		−ERASE, 47037281435648, 47037281435648,
2661		−STORE, 47037281435648, 47037281439743,
2662		−STORE, 47037281439744, 47037281443839,
2663		−ERASE, 47037279264768, 47037279264768,
2664		−STORE, 47037279264768, 47037279461375,
2665		−STORE, 47037279461376, 47037279469567,
2666		−ERASE, 47037276426240, 47037276426240,
2667		−STORE, 47037276426240, 47037276430335,
2668		−STORE, 47037276430336, 47037276434431,
2669		−ERASE, 94352938094592, 94352938094592,
2670		−STORE, 94352938094592, 94352938102783,
2671		−STORE, 94352938102784, 94352938106879,
2672		−ERASE, 140595518902272, 140595518902272,
2673		−STORE, 140595518902272, 140595518906367,
2674		−STORE, 140595518906368, 140595518910463,
2675		−ERASE, 47037276254208, 47037276254208,
2676		−STORE, 94352938438656, 94352938573823,
2677		−STORE, 140737488347136, 140737488351231,
2678		−STORE, 140733506027520, 140737488351231,
2679		−ERASE, 140733506027520, 140733506027520,
2680		−STORE, 140733506027520, 140733506031615,
2681		−STORE, 94150123073536, 94150123245567,
2682		−ERASE, 94150123073536, 94150123073536,
2683		−STORE, 94150123073536, 94150123089919,
2684		−STORE, 94150123089920, 94150123245567,
2685		−ERASE, 94150123089920, 94150123089920,
2686		−STORE, 94150123089920, 94150123192319,
2687		−STORE, 94150123192320, 94150123233279,
2688		−STORE, 94150123233280, 94150123245567,
2689		−STORE, 140081290375168, 140081290547199,
2690		−ERASE, 140081290375168, 140081290375168,
2691		−STORE, 140081290375168, 140081290379263,
2692		−STORE, 140081290379264, 140081290547199,
2693		−ERASE, 140081290379264, 140081290379264,
2694		−STORE, 140081290379264, 140081290502143,
2695		−STORE, 140081290502144, 140081290534911,
2696		−STORE, 140081290534912, 140081290543103,
2697		−STORE, 140081290543104, 140081290547199,
2698		−STORE, 140733506707456, 140733506711551,
2699		−STORE, 140733506695168, 140733506707455,
2700		−STORE, 47551504621568, 47551504629759,
2701		−STORE, 47551504629760, 47551504637951,
2702		−STORE, 47551504637952, 47551504801791,
2703		−ERASE, 47551504637952, 47551504637952,
2704		−STORE, 47551504637952, 47551504650239,
2705		−STORE, 47551504650240, 47551504801791,
2706		−STORE, 47551504748544, 47551504801791,
2707		−STORE, 47551504650240, 47551504748543,
2708		−ERASE, 47551504650240, 47551504650240,
2709		−STORE, 47551504650240, 47551504748543,
2710		−STORE, 47551504793600, 47551504801791,
2711		−STORE, 47551504748544, 47551504793599,
2712		−ERASE, 47551504748544, 47551504748544,
2713		−STORE, 47551504748544, 47551504801791,
2714		−ERASE, 47551504748544, 47551504748544,
2715		−STORE, 47551504748544, 47551504793599,
2716		−STORE, 47551504793600, 47551504801791,
2717		−ERASE, 47551504793600, 47551504793600,
2718		−STORE, 47551504793600, 47551504801791,
2719		−STORE, 47551504801792, 47551507853311,
2720		−STORE, 47551505346560, 47551507853311,
2721		−STORE, 47551504801792, 47551505346559,
2722		−ERASE, 47551505346560, 47551505346560,
2723		−STORE, 47551505346560, 47551507632127,
2724		−STORE, 47551507632128, 47551507853311,
2725		−STORE, 47551507042304, 47551507632127,
2726		−STORE, 47551505346560, 47551507042303,
2727		−ERASE, 47551505346560, 47551505346560,
2728		−STORE, 47551505346560, 47551507042303,
2729		−STORE, 47551507628032, 47551507632127,
2730		−STORE, 47551507042304, 47551507628031,
2731		−ERASE, 47551507042304, 47551507042304,
2732		−STORE, 47551507042304, 47551507628031,
2733		−STORE, 47551507836928, 47551507853311,
2734		−STORE, 47551507632128, 47551507836927,
2735		−ERASE, 47551507632128, 47551507632128,
2736		−STORE, 47551507632128, 47551507836927,
2737		−ERASE, 47551507836928, 47551507836928,
2738		−STORE, 47551507836928, 47551507853311,
2739		−STORE, 47551507853312, 47551509692415,
2740		−STORE, 47551507992576, 47551509692415,
2741		−STORE, 47551507853312, 47551507992575,
2742		−ERASE, 47551507992576, 47551507992576,
2743		−STORE, 47551507992576, 47551509651455,
2744		−STORE, 47551509651456, 47551509692415,
2745		−STORE, 47551509336064, 47551509651455,
2746		−STORE, 47551507992576, 47551509336063,
2747		−ERASE, 47551507992576, 47551507992576,
2748		−STORE, 47551507992576, 47551509336063,
2749		−STORE, 47551509647360, 47551509651455,
2750		−STORE, 47551509336064, 47551509647359,
2751		−ERASE, 47551509336064, 47551509336064,
2752		−STORE, 47551509336064, 47551509647359,
2753		−STORE, 47551509676032, 47551509692415,
2754		−STORE, 47551509651456, 47551509676031,
2755		−ERASE, 47551509651456, 47551509651456,
2756		−STORE, 47551509651456, 47551509676031,
2757		−ERASE, 47551509676032, 47551509676032,
2758		−STORE, 47551509676032, 47551509692415,
2759		−STORE, 47551509692416, 47551509827583,
2760		−ERASE, 47551509692416, 47551509692416,
2761		−STORE, 47551509692416, 47551509716991,
2762		−STORE, 47551509716992, 47551509827583,
2763		−STORE, 47551509778432, 47551509827583,
2764		−STORE, 47551509716992, 47551509778431,
2765		−ERASE, 47551509716992, 47551509716992,
2766		−STORE, 47551509716992, 47551509778431,
2767		−STORE, 47551509803008, 47551509827583,
2768		−STORE, 47551509778432, 47551509803007,
2769		−ERASE, 47551509778432, 47551509778432,
2770		−STORE, 47551509778432, 47551509827583,
2771		−ERASE, 47551509778432, 47551509778432,
2772		−STORE, 47551509778432, 47551509803007,
2773		−STORE, 47551509803008, 47551509827583,
2774		−STORE, 47551509811200, 47551509827583,
2775		−STORE, 47551509803008, 47551509811199,
2776		−ERASE, 47551509803008, 47551509803008,
2777		−STORE, 47551509803008, 47551509811199,
2778		−ERASE, 47551509811200, 47551509811200,
2779		−STORE, 47551509811200, 47551509827583,
2780		−STORE, 47551509827584, 47551509848063,
2781		−ERASE, 47551509827584, 47551509827584,
2782		−STORE, 47551509827584, 47551509831679,
2783		−STORE, 47551509831680, 47551509848063,
2784		−STORE, 47551509835776, 47551509848063,
2785		−STORE, 47551509831680, 47551509835775,
2786		−ERASE, 47551509831680, 47551509831680,
2787		−STORE, 47551509831680, 47551509835775,
2788		−STORE, 47551509839872, 47551509848063,
2789		−STORE, 47551509835776, 47551509839871,
2790		−ERASE, 47551509835776, 47551509835776,
2791		−STORE, 47551509835776, 47551509848063,
2792		−ERASE, 47551509835776, 47551509835776,
2793		−STORE, 47551509835776, 47551509839871,
2794		−STORE, 47551509839872, 47551509848063,
2795		−ERASE, 47551509839872, 47551509839872,
2796		−STORE, 47551509839872, 47551509848063,
2797		−STORE, 47551509848064, 47551509856255,
2798		−ERASE, 47551509651456, 47551509651456,
2799		−STORE, 47551509651456, 47551509667839,
2800		−STORE, 47551509667840, 47551509676031,
2801		−ERASE, 47551509839872, 47551509839872,
2802		−STORE, 47551509839872, 47551509843967,
2803		−STORE, 47551509843968, 47551509848063,
2804		−ERASE, 47551509803008, 47551509803008,
2805		−STORE, 47551509803008, 47551509807103,
2806		−STORE, 47551509807104, 47551509811199,
2807		−ERASE, 47551507632128, 47551507632128,
2808		−STORE, 47551507632128, 47551507828735,
2809		−STORE, 47551507828736, 47551507836927,
2810		−ERASE, 47551504793600, 47551504793600,
2811		−STORE, 47551504793600, 47551504797695,
2812		−STORE, 47551504797696, 47551504801791,
2813		−ERASE, 94150123233280, 94150123233280,
2814		−STORE, 94150123233280, 94150123241471,
2815		−STORE, 94150123241472, 94150123245567,
2816		−ERASE, 140081290534912, 140081290534912,
2817		−STORE, 140081290534912, 140081290539007,
2818		−STORE, 140081290539008, 140081290543103,
2819		−ERASE, 47551504621568, 47551504621568,
2820		−STORE, 94150148112384, 94150148247551,
2821		−STORE, 140737488347136, 140737488351231,
2822		−STORE, 140734389334016, 140737488351231,
2823		−ERASE, 140734389334016, 140734389334016,
2824		−STORE, 140734389334016, 140734389338111,
2825		−STORE, 94844636606464, 94844636778495,
2826		−ERASE, 94844636606464, 94844636606464,
2827		−STORE, 94844636606464, 94844636622847,
2828		−STORE, 94844636622848, 94844636778495,
2829		−ERASE, 94844636622848, 94844636622848,
2830		−STORE, 94844636622848, 94844636725247,
2831		−STORE, 94844636725248, 94844636766207,
2832		−STORE, 94844636766208, 94844636778495,
2833		−STORE, 139922765217792, 139922765389823,
2834		−ERASE, 139922765217792, 139922765217792,
2835		−STORE, 139922765217792, 139922765221887,
2836		−STORE, 139922765221888, 139922765389823,
2837		−ERASE, 139922765221888, 139922765221888,
2838		−STORE, 139922765221888, 139922765344767,
2839		−STORE, 139922765344768, 139922765377535,
2840		−STORE, 139922765377536, 139922765385727,
2841		−STORE, 139922765385728, 139922765389823,
2842		−STORE, 140734389678080, 140734389682175,
2843		−STORE, 140734389665792, 140734389678079,
2844		−STORE, 47710029778944, 47710029787135,
2845		−STORE, 47710029787136, 47710029795327,
2846		−STORE, 47710029795328, 47710029959167,
2847		−ERASE, 47710029795328, 47710029795328,
2848		−STORE, 47710029795328, 47710029807615,
2849		−STORE, 47710029807616, 47710029959167,
2850		−STORE, 47710029905920, 47710029959167,
2851		−STORE, 47710029807616, 47710029905919,
2852		−ERASE, 47710029807616, 47710029807616,
2853		−STORE, 47710029807616, 47710029905919,
2854		−STORE, 47710029950976, 47710029959167,
2855		−STORE, 47710029905920, 47710029950975,
2856		−ERASE, 47710029905920, 47710029905920,
2857		−STORE, 47710029905920, 47710029959167,
2858		−ERASE, 47710029905920, 47710029905920,
2859		−STORE, 47710029905920, 47710029950975,
2860		−STORE, 47710029950976, 47710029959167,
2861		−ERASE, 47710029950976, 47710029950976,
2862		−STORE, 47710029950976, 47710029959167,
2863		−STORE, 47710029959168, 47710033010687,
2864		−STORE, 47710030503936, 47710033010687,
2865		−STORE, 47710029959168, 47710030503935,
2866		−ERASE, 47710030503936, 47710030503936,
2867		−STORE, 47710030503936, 47710032789503,
2868		−STORE, 47710032789504, 47710033010687,
2869		−STORE, 47710032199680, 47710032789503,
2870		−STORE, 47710030503936, 47710032199679,
2871		−ERASE, 47710030503936, 47710030503936,
2872		−STORE, 47710030503936, 47710032199679,
2873		−STORE, 47710032785408, 47710032789503,
2874		−STORE, 47710032199680, 47710032785407,
2875		−ERASE, 47710032199680, 47710032199680,
2876		−STORE, 47710032199680, 47710032785407,
2877		−STORE, 47710032994304, 47710033010687,
2878		−STORE, 47710032789504, 47710032994303,
2879		−ERASE, 47710032789504, 47710032789504,
2880		−STORE, 47710032789504, 47710032994303,
2881		−ERASE, 47710032994304, 47710032994304,
2882		−STORE, 47710032994304, 47710033010687,
2883		−STORE, 47710033010688, 47710034849791,
2884		−STORE, 47710033149952, 47710034849791,
2885		−STORE, 47710033010688, 47710033149951,
2886		−ERASE, 47710033149952, 47710033149952,
2887		−STORE, 47710033149952, 47710034808831,
2888		−STORE, 47710034808832, 47710034849791,
2889		−STORE, 47710034493440, 47710034808831,
2890		−STORE, 47710033149952, 47710034493439,
2891		−ERASE, 47710033149952, 47710033149952,
2892		−STORE, 47710033149952, 47710034493439,
2893		−STORE, 47710034804736, 47710034808831,
2894		−STORE, 47710034493440, 47710034804735,
2895		−ERASE, 47710034493440, 47710034493440,
2896		−STORE, 47710034493440, 47710034804735,
2897		−STORE, 47710034833408, 47710034849791,
2898		−STORE, 47710034808832, 47710034833407,
2899		−ERASE, 47710034808832, 47710034808832,
2900		−STORE, 47710034808832, 47710034833407,
2901		−ERASE, 47710034833408, 47710034833408,
2902		−STORE, 47710034833408, 47710034849791,
2903		−STORE, 47710034849792, 47710034984959,
2904		−ERASE, 47710034849792, 47710034849792,
2905		−STORE, 47710034849792, 47710034874367,
2906		−STORE, 47710034874368, 47710034984959,
2907		−STORE, 47710034935808, 47710034984959,
2908		−STORE, 47710034874368, 47710034935807,
2909		−ERASE, 47710034874368, 47710034874368,
2910		−STORE, 47710034874368, 47710034935807,
2911		−STORE, 47710034960384, 47710034984959,
2912		−STORE, 47710034935808, 47710034960383,
2913		−ERASE, 47710034935808, 47710034935808,
2914		−STORE, 47710034935808, 47710034984959,
2915		−ERASE, 47710034935808, 47710034935808,
2916		−STORE, 47710034935808, 47710034960383,
2917		−STORE, 47710034960384, 47710034984959,
2918		−STORE, 47710034968576, 47710034984959,
2919		−STORE, 47710034960384, 47710034968575,
2920		−ERASE, 47710034960384, 47710034960384,
2921		−STORE, 47710034960384, 47710034968575,
2922		−ERASE, 47710034968576, 47710034968576,
2923		−STORE, 47710034968576, 47710034984959,
2924		−STORE, 47710034984960, 47710035005439,
2925		−ERASE, 47710034984960, 47710034984960,
2926		−STORE, 47710034984960, 47710034989055,
2927		−STORE, 47710034989056, 47710035005439,
2928		−STORE, 47710034993152, 47710035005439,
2929		−STORE, 47710034989056, 47710034993151,
2930		−ERASE, 47710034989056, 47710034989056,
2931		−STORE, 47710034989056, 47710034993151,
2932		−STORE, 47710034997248, 47710035005439,
2933		−STORE, 47710034993152, 47710034997247,
2934		−ERASE, 47710034993152, 47710034993152,
2935		−STORE, 47710034993152, 47710035005439,
2936		−ERASE, 47710034993152, 47710034993152,
2937		−STORE, 47710034993152, 47710034997247,
2938		−STORE, 47710034997248, 47710035005439,
2939		−ERASE, 47710034997248, 47710034997248,
2940		−STORE, 47710034997248, 47710035005439,
2941		−STORE, 47710035005440, 47710035013631,
2942		−ERASE, 47710034808832, 47710034808832,
2943		−STORE, 47710034808832, 47710034825215,
2944		−STORE, 47710034825216, 47710034833407,
2945		−ERASE, 47710034997248, 47710034997248,
2946		−STORE, 47710034997248, 47710035001343,
2947		−STORE, 47710035001344, 47710035005439,
2948		−ERASE, 47710034960384, 47710034960384,
2949		−STORE, 47710034960384, 47710034964479,
2950		−STORE, 47710034964480, 47710034968575,
2951		−ERASE, 47710032789504, 47710032789504,
2952		−STORE, 47710032789504, 47710032986111,
2953		−STORE, 47710032986112, 47710032994303,
2954		−ERASE, 47710029950976, 47710029950976,
2955		−STORE, 47710029950976, 47710029955071,
2956		−STORE, 47710029955072, 47710029959167,
2957		−ERASE, 94844636766208, 94844636766208,
2958		−STORE, 94844636766208, 94844636774399,
2959		−STORE, 94844636774400, 94844636778495,
2960		−ERASE, 139922765377536, 139922765377536,
2961		−STORE, 139922765377536, 139922765381631,
2962		−STORE, 139922765381632, 139922765385727,
2963		−ERASE, 47710029778944, 47710029778944,
2964		−STORE, 94844641775616, 94844641910783,
2965		−STORE, 140737488347136, 140737488351231,
2966		−STORE, 140732213886976, 140737488351231,
2967		−ERASE, 140732213886976, 140732213886976,
2968		−STORE, 140732213886976, 140732213891071,
2969		−STORE, 94240508887040, 94240509059071,
2970		−ERASE, 94240508887040, 94240508887040,
2971		−STORE, 94240508887040, 94240508903423,
2972		−STORE, 94240508903424, 94240509059071,
2973		−ERASE, 94240508903424, 94240508903424,
2974		−STORE, 94240508903424, 94240509005823,
2975		−STORE, 94240509005824, 94240509046783,
2976		−STORE, 94240509046784, 94240509059071,
2977		−STORE, 140275106516992, 140275106689023,
2978		−ERASE, 140275106516992, 140275106516992,
2979		−STORE, 140275106516992, 140275106521087,
2980		−STORE, 140275106521088, 140275106689023,
2981		−ERASE, 140275106521088, 140275106521088,
2982		−STORE, 140275106521088, 140275106643967,
2983		−STORE, 140275106643968, 140275106676735,
2984		−STORE, 140275106676736, 140275106684927,
2985		−STORE, 140275106684928, 140275106689023,
2986		−STORE, 140732213977088, 140732213981183,
2987		−STORE, 140732213964800, 140732213977087,
2988		−STORE, 47357688479744, 47357688487935,
2989		−STORE, 47357688487936, 47357688496127,
2990		−STORE, 47357688496128, 47357688659967,
2991		−ERASE, 47357688496128, 47357688496128,
2992		−STORE, 47357688496128, 47357688508415,
2993		−STORE, 47357688508416, 47357688659967,
2994		−STORE, 47357688606720, 47357688659967,
2995		−STORE, 47357688508416, 47357688606719,
2996		−ERASE, 47357688508416, 47357688508416,
2997		−STORE, 47357688508416, 47357688606719,
2998		−STORE, 47357688651776, 47357688659967,
2999		−STORE, 47357688606720, 47357688651775,
3000		−ERASE, 47357688606720, 47357688606720,
3001		−STORE, 47357688606720, 47357688659967,
3002		−ERASE, 47357688606720, 47357688606720,
3003		−STORE, 47357688606720, 47357688651775,
3004		−STORE, 47357688651776, 47357688659967,
3005		−ERASE, 47357688651776, 47357688651776,
3006		−STORE, 47357688651776, 47357688659967,
3007		−STORE, 47357688659968, 47357691711487,
3008		−STORE, 47357689204736, 47357691711487,
3009		−STORE, 47357688659968, 47357689204735,
3010		−ERASE, 47357689204736, 47357689204736,
3011		−STORE, 47357689204736, 47357691490303,
3012		−STORE, 47357691490304, 47357691711487,
3013		−STORE, 47357690900480, 47357691490303,
3014		−STORE, 47357689204736, 47357690900479,
3015		−ERASE, 47357689204736, 47357689204736,
3016		−STORE, 47357689204736, 47357690900479,
3017		−STORE, 47357691486208, 47357691490303,
3018		−STORE, 47357690900480, 47357691486207,
3019		−ERASE, 47357690900480, 47357690900480,
3020		−STORE, 47357690900480, 47357691486207,
3021		−STORE, 47357691695104, 47357691711487,
3022		−STORE, 47357691490304, 47357691695103,
3023		−ERASE, 47357691490304, 47357691490304,
3024		−STORE, 47357691490304, 47357691695103,
3025		−ERASE, 47357691695104, 47357691695104,
3026		−STORE, 47357691695104, 47357691711487,
3027		−STORE, 47357691711488, 47357693550591,
3028		−STORE, 47357691850752, 47357693550591,
3029		−STORE, 47357691711488, 47357691850751,
3030		−ERASE, 47357691850752, 47357691850752,
3031		−STORE, 47357691850752, 47357693509631,
3032		−STORE, 47357693509632, 47357693550591,
3033		−STORE, 47357693194240, 47357693509631,
3034		−STORE, 47357691850752, 47357693194239,
3035		−ERASE, 47357691850752, 47357691850752,
3036		−STORE, 47357691850752, 47357693194239,
3037		−STORE, 47357693505536, 47357693509631,
3038		−STORE, 47357693194240, 47357693505535,
3039		−ERASE, 47357693194240, 47357693194240,
3040		−STORE, 47357693194240, 47357693505535,
3041		−STORE, 47357693534208, 47357693550591,
3042		−STORE, 47357693509632, 47357693534207,
3043		−ERASE, 47357693509632, 47357693509632,
3044		−STORE, 47357693509632, 47357693534207,
3045		−ERASE, 47357693534208, 47357693534208,
3046		−STORE, 47357693534208, 47357693550591,
3047		−STORE, 47357693550592, 47357693685759,
3048		−ERASE, 47357693550592, 47357693550592,
3049		−STORE, 47357693550592, 47357693575167,
3050		−STORE, 47357693575168, 47357693685759,
3051		−STORE, 47357693636608, 47357693685759,
3052		−STORE, 47357693575168, 47357693636607,
3053		−ERASE, 47357693575168, 47357693575168,
3054		−STORE, 47357693575168, 47357693636607,
3055		−STORE, 47357693661184, 47357693685759,
3056		−STORE, 47357693636608, 47357693661183,
3057		−ERASE, 47357693636608, 47357693636608,
3058		−STORE, 47357693636608, 47357693685759,
3059		−ERASE, 47357693636608, 47357693636608,
3060		−STORE, 47357693636608, 47357693661183,
3061		−STORE, 47357693661184, 47357693685759,
3062		−STORE, 47357693669376, 47357693685759,
3063		−STORE, 47357693661184, 47357693669375,
3064		−ERASE, 47357693661184, 47357693661184,
3065		−STORE, 47357693661184, 47357693669375,
3066		−ERASE, 47357693669376, 47357693669376,
3067		−STORE, 47357693669376, 47357693685759,
3068		−STORE, 47357693685760, 47357693706239,
3069		−ERASE, 47357693685760, 47357693685760,
3070		−STORE, 47357693685760, 47357693689855,
3071		−STORE, 47357693689856, 47357693706239,
3072		−STORE, 47357693693952, 47357693706239,
3073		−STORE, 47357693689856, 47357693693951,
3074		−ERASE, 47357693689856, 47357693689856,
3075		−STORE, 47357693689856, 47357693693951,
3076		−STORE, 47357693698048, 47357693706239,
3077		−STORE, 47357693693952, 47357693698047,
3078		−ERASE, 47357693693952, 47357693693952,
3079		−STORE, 47357693693952, 47357693706239,
3080		−ERASE, 47357693693952, 47357693693952,
3081		−STORE, 47357693693952, 47357693698047,
3082		−STORE, 47357693698048, 47357693706239,
3083		−ERASE, 47357693698048, 47357693698048,
3084		−STORE, 47357693698048, 47357693706239,
3085		−STORE, 47357693706240, 47357693714431,
3086		−ERASE, 47357693509632, 47357693509632,
3087		−STORE, 47357693509632, 47357693526015,
3088		−STORE, 47357693526016, 47357693534207,
3089		−ERASE, 47357693698048, 47357693698048,
3090		−STORE, 47357693698048, 47357693702143,
3091		−STORE, 47357693702144, 47357693706239,
3092		−ERASE, 47357693661184, 47357693661184,
3093		−STORE, 47357693661184, 47357693665279,
3094		−STORE, 47357693665280, 47357693669375,
3095		−ERASE, 47357691490304, 47357691490304,
3096		−STORE, 47357691490304, 47357691686911,
3097		−STORE, 47357691686912, 47357691695103,
3098		−ERASE, 47357688651776, 47357688651776,
3099		−STORE, 47357688651776, 47357688655871,
3100		−STORE, 47357688655872, 47357688659967,
3101		−ERASE, 94240509046784, 94240509046784,
3102		−STORE, 94240509046784, 94240509054975,
3103		−STORE, 94240509054976, 94240509059071,
3104		−ERASE, 140275106676736, 140275106676736,
3105		−STORE, 140275106676736, 140275106680831,
3106		−STORE, 140275106680832, 140275106684927,
3107		−ERASE, 47357688479744, 47357688479744,
3108		−STORE, 94240518361088, 94240518496255,
3109		−STORE, 140737488347136, 140737488351231,
3110		−STORE, 140732688277504, 140737488351231,
3111		−ERASE, 140732688277504, 140732688277504,
3112		−STORE, 140732688277504, 140732688281599,
3113		−STORE, 94629171351552, 94629172064255,
3114		−ERASE, 94629171351552, 94629171351552,
3115		−STORE, 94629171351552, 94629171400703,
3116		−STORE, 94629171400704, 94629172064255,
3117		−ERASE, 94629171400704, 94629171400704,
3118		−STORE, 94629171400704, 94629171945471,
3119		−STORE, 94629171945472, 94629172043775,
3120		−STORE, 94629172043776, 94629172064255,
3121		−STORE, 139770707644416, 139770707816447,
3122		−ERASE, 139770707644416, 139770707644416,
3123		−STORE, 139770707644416, 139770707648511,
3124		−STORE, 139770707648512, 139770707816447,
3125		−ERASE, 139770707648512, 139770707648512,
3126		−STORE, 139770707648512, 139770707771391,
3127		−STORE, 139770707771392, 139770707804159,
3128		−STORE, 139770707804160, 139770707812351,
3129		−STORE, 139770707812352, 139770707816447,
3130		−STORE, 140732689121280, 140732689125375,
3131		−STORE, 140732689108992, 140732689121279,
3132		−STORE, 47862087352320, 47862087360511,
3133		−STORE, 47862087360512, 47862087368703,
3134		−STORE, 47862087368704, 47862087475199,
3135		−STORE, 47862087385088, 47862087475199,
3136		−STORE, 47862087368704, 47862087385087,
3137		−ERASE, 47862087385088, 47862087385088,
3138		−STORE, 47862087385088, 47862087458815,
3139		−STORE, 47862087458816, 47862087475199,
3140		−STORE, 47862087438336, 47862087458815,
3141		−STORE, 47862087385088, 47862087438335,
3142		−ERASE, 47862087385088, 47862087385088,
3143		−STORE, 47862087385088, 47862087438335,
3144		−STORE, 47862087454720, 47862087458815,
3145		−STORE, 47862087438336, 47862087454719,
3146		−ERASE, 47862087438336, 47862087438336,
3147		−STORE, 47862087438336, 47862087454719,
3148		−STORE, 47862087467008, 47862087475199,
3149		−STORE, 47862087458816, 47862087467007,
3150		−ERASE, 47862087458816, 47862087458816,
3151		−STORE, 47862087458816, 47862087467007,
3152		−ERASE, 47862087467008, 47862087467008,
3153		−STORE, 47862087467008, 47862087475199,
3154		−STORE, 47862087475200, 47862089314303,
3155		−STORE, 47862087614464, 47862089314303,
3156		−STORE, 47862087475200, 47862087614463,
3157		−ERASE, 47862087614464, 47862087614464,
3158		−STORE, 47862087614464, 47862089273343,
3159		−STORE, 47862089273344, 47862089314303,
3160		−STORE, 47862088957952, 47862089273343,
3161		−STORE, 47862087614464, 47862088957951,
3162		−ERASE, 47862087614464, 47862087614464,
3163		−STORE, 47862087614464, 47862088957951,
3164		−STORE, 47862089269248, 47862089273343,
3165		−STORE, 47862088957952, 47862089269247,
3166		−ERASE, 47862088957952, 47862088957952,
3167		−STORE, 47862088957952, 47862089269247,
3168		−STORE, 47862089297920, 47862089314303,
3169		−STORE, 47862089273344, 47862089297919,
3170		−ERASE, 47862089273344, 47862089273344,
3171		−STORE, 47862089273344, 47862089297919,
3172		−ERASE, 47862089297920, 47862089297920,
3173		−STORE, 47862089297920, 47862089314303,
3174		−STORE, 47862089297920, 47862089326591,
3175		−ERASE, 47862089273344, 47862089273344,
3176		−STORE, 47862089273344, 47862089289727,
3177		−STORE, 47862089289728, 47862089297919,
3178		−ERASE, 47862087458816, 47862087458816,
3179		−STORE, 47862087458816, 47862087462911,
3180		−STORE, 47862087462912, 47862087467007,
3181		−ERASE, 94629172043776, 94629172043776,
3182		−STORE, 94629172043776, 94629172060159,
3183		−STORE, 94629172060160, 94629172064255,
3184		−ERASE, 139770707804160, 139770707804160,
3185		−STORE, 139770707804160, 139770707808255,
3186		−STORE, 139770707808256, 139770707812351,
3187		−ERASE, 47862087352320, 47862087352320,
3188		−STORE, 94629197533184, 94629197668351,
3189		−STORE, 140737488347136, 140737488351231,
3190		−STORE, 140727540711424, 140737488351231,
3191		−ERASE, 140727540711424, 140727540711424,
3192		−STORE, 140727540711424, 140727540715519,
3193		−STORE, 94299865313280, 94299866025983,
3194		−ERASE, 94299865313280, 94299865313280,
3195		−STORE, 94299865313280, 94299865362431,
3196		−STORE, 94299865362432, 94299866025983,
3197		−ERASE, 94299865362432, 94299865362432,
3198		−STORE, 94299865362432, 94299865907199,
3199		−STORE, 94299865907200, 94299866005503,
3200		−STORE, 94299866005504, 94299866025983,
3201		−STORE, 140680268763136, 140680268935167,
3202		−ERASE, 140680268763136, 140680268763136,
3203		−STORE, 140680268763136, 140680268767231,
3204		−STORE, 140680268767232, 140680268935167,
3205		−ERASE, 140680268767232, 140680268767232,
3206		−STORE, 140680268767232, 140680268890111,
3207		−STORE, 140680268890112, 140680268922879,
3208		−STORE, 140680268922880, 140680268931071,
3209		−STORE, 140680268931072, 140680268935167,
3210		−STORE, 140727541424128, 140727541428223,
3211		−STORE, 140727541411840, 140727541424127,
3212		−STORE, 46952526233600, 46952526241791,
3213		−STORE, 46952526241792, 46952526249983,
3214		−STORE, 46952526249984, 46952526356479,
3215		−STORE, 46952526266368, 46952526356479,
3216		−STORE, 46952526249984, 46952526266367,
3217		−ERASE, 46952526266368, 46952526266368,
3218		−STORE, 46952526266368, 46952526340095,
3219		−STORE, 46952526340096, 46952526356479,
3220		−STORE, 46952526319616, 46952526340095,
3221		−STORE, 46952526266368, 46952526319615,
3222		−ERASE, 46952526266368, 46952526266368,
3223		−STORE, 46952526266368, 46952526319615,
3224		−STORE, 46952526336000, 46952526340095,
3225		−STORE, 46952526319616, 46952526335999,
3226		−ERASE, 46952526319616, 46952526319616,
3227		−STORE, 46952526319616, 46952526335999,
3228		−STORE, 46952526348288, 46952526356479,
3229		−STORE, 46952526340096, 46952526348287,
3230		−ERASE, 46952526340096, 46952526340096,
3231		−STORE, 46952526340096, 46952526348287,
3232		−ERASE, 46952526348288, 46952526348288,
3233		−STORE, 46952526348288, 46952526356479,
3234		−STORE, 46952526356480, 46952528195583,
3235		−STORE, 46952526495744, 46952528195583,
3236		−STORE, 46952526356480, 46952526495743,
3237		−ERASE, 46952526495744, 46952526495744,
3238		−STORE, 46952526495744, 46952528154623,
3239		−STORE, 46952528154624, 46952528195583,
3240		−STORE, 46952527839232, 46952528154623,
3241		−STORE, 46952526495744, 46952527839231,
3242		−ERASE, 46952526495744, 46952526495744,
3243		−STORE, 46952526495744, 46952527839231,
3244		−STORE, 46952528150528, 46952528154623,
3245		−STORE, 46952527839232, 46952528150527,
3246		−ERASE, 46952527839232, 46952527839232,
3247		−STORE, 46952527839232, 46952528150527,
3248		−STORE, 46952528179200, 46952528195583,
3249		−STORE, 46952528154624, 46952528179199,
3250		−ERASE, 46952528154624, 46952528154624,
3251		−STORE, 46952528154624, 46952528179199,
3252		−ERASE, 46952528179200, 46952528179200,
3253		−STORE, 46952528179200, 46952528195583,
3254		−STORE, 46952528179200, 46952528207871,
3255		−ERASE, 46952528154624, 46952528154624,
3256		−STORE, 46952528154624, 46952528171007,
3257		−STORE, 46952528171008, 46952528179199,
3258		−ERASE, 46952526340096, 46952526340096,
3259		−STORE, 46952526340096, 46952526344191,
3260		−STORE, 46952526344192, 46952526348287,
3261		−ERASE, 94299866005504, 94299866005504,
3262		−STORE, 94299866005504, 94299866021887,
3263		−STORE, 94299866021888, 94299866025983,
3264		−ERASE, 140680268922880, 140680268922880,
3265		−STORE, 140680268922880, 140680268926975,
3266		−STORE, 140680268926976, 140680268931071,
3267		−ERASE, 46952526233600, 46952526233600,
3268		−STORE, 140737488347136, 140737488351231,
3269		−STORE, 140722874793984, 140737488351231,
3270		−ERASE, 140722874793984, 140722874793984,
3271		−STORE, 140722874793984, 140722874798079,
3272		−STORE, 94448916213760, 94448916926463,
3273		−ERASE, 94448916213760, 94448916213760,
3274		−STORE, 94448916213760, 94448916262911,
3275		−STORE, 94448916262912, 94448916926463,
3276		−ERASE, 94448916262912, 94448916262912,
3277		−STORE, 94448916262912, 94448916807679,
3278		−STORE, 94448916807680, 94448916905983,
3279		−STORE, 94448916905984, 94448916926463,
3280		−STORE, 140389117046784, 140389117218815,
3281		−ERASE, 140389117046784, 140389117046784,
3282		−STORE, 140389117046784, 140389117050879,
3283		−STORE, 140389117050880, 140389117218815,
3284		−ERASE, 140389117050880, 140389117050880,
3285		−STORE, 140389117050880, 140389117173759,
3286		−STORE, 140389117173760, 140389117206527,
3287		−STORE, 140389117206528, 140389117214719,
3288		−STORE, 140389117214720, 140389117218815,
3289		−STORE, 140722875297792, 140722875301887,
3290		−STORE, 140722875285504, 140722875297791,
3291		−STORE, 47243677949952, 47243677958143,
3292		−STORE, 47243677958144, 47243677966335,
3293		−STORE, 47243677966336, 47243678072831,
3294		−STORE, 47243677982720, 47243678072831,
3295		−STORE, 47243677966336, 47243677982719,
3296		−ERASE, 47243677982720, 47243677982720,
3297		−STORE, 47243677982720, 47243678056447,
3298		−STORE, 47243678056448, 47243678072831,
3299		−STORE, 47243678035968, 47243678056447,
3300		−STORE, 47243677982720, 47243678035967,
3301		−ERASE, 47243677982720, 47243677982720,
3302		−STORE, 47243677982720, 47243678035967,
3303		−STORE, 47243678052352, 47243678056447,
3304		−STORE, 47243678035968, 47243678052351,
3305		−ERASE, 47243678035968, 47243678035968,
3306		−STORE, 47243678035968, 47243678052351,
3307		−STORE, 47243678064640, 47243678072831,
3308		−STORE, 47243678056448, 47243678064639,
3309		−ERASE, 47243678056448, 47243678056448,
3310		−STORE, 47243678056448, 47243678064639,
3311		−ERASE, 47243678064640, 47243678064640,
3312		−STORE, 47243678064640, 47243678072831,
3313		−STORE, 47243678072832, 47243679911935,
3314		−STORE, 47243678212096, 47243679911935,
3315		−STORE, 47243678072832, 47243678212095,
3316		−ERASE, 47243678212096, 47243678212096,
3317		−STORE, 47243678212096, 47243679870975,
3318		−STORE, 47243679870976, 47243679911935,
3319		−STORE, 47243679555584, 47243679870975,
3320		−STORE, 47243678212096, 47243679555583,
3321		−ERASE, 47243678212096, 47243678212096,
3322		−STORE, 47243678212096, 47243679555583,
3323		−STORE, 47243679866880, 47243679870975,
3324		−STORE, 47243679555584, 47243679866879,
3325		−ERASE, 47243679555584, 47243679555584,
3326		−STORE, 47243679555584, 47243679866879,
3327		−STORE, 47243679895552, 47243679911935,
3328		−STORE, 47243679870976, 47243679895551,
3329		−ERASE, 47243679870976, 47243679870976,
3330		−STORE, 47243679870976, 47243679895551,
3331		−ERASE, 47243679895552, 47243679895552,
3332		−STORE, 47243679895552, 47243679911935,
3333		−STORE, 47243679895552, 47243679924223,
3334		−ERASE, 47243679870976, 47243679870976,
3335		−STORE, 47243679870976, 47243679887359,
3336		−STORE, 47243679887360, 47243679895551,
3337		−ERASE, 47243678056448, 47243678056448,
3338		−STORE, 47243678056448, 47243678060543,
3339		−STORE, 47243678060544, 47243678064639,
3340		−ERASE, 94448916905984, 94448916905984,
3341		−STORE, 94448916905984, 94448916922367,
3342		−STORE, 94448916922368, 94448916926463,
3343		−ERASE, 140389117206528, 140389117206528,
3344		−STORE, 140389117206528, 140389117210623,
3345		−STORE, 140389117210624, 140389117214719,
3346		−ERASE, 47243677949952, 47243677949952,
3347		−STORE, 140737488347136, 140737488351231,
3348		−STORE, 140733068505088, 140737488351231,
3349		−ERASE, 140733068505088, 140733068505088,
3350		−STORE, 140733068505088, 140733068509183,
3351		−STORE, 94207145750528, 94207146463231,
3352		−ERASE, 94207145750528, 94207145750528,
3353		−STORE, 94207145750528, 94207145799679,
3354		−STORE, 94207145799680, 94207146463231,
3355		−ERASE, 94207145799680, 94207145799680,
3356		−STORE, 94207145799680, 94207146344447,
3357		−STORE, 94207146344448, 94207146442751,
3358		−STORE, 94207146442752, 94207146463231,
3359		−STORE, 140684504911872, 140684505083903,
3360		−ERASE, 140684504911872, 140684504911872,
3361		−STORE, 140684504911872, 140684504915967,
3362		−STORE, 140684504915968, 140684505083903,
3363		−ERASE, 140684504915968, 140684504915968,
3364		−STORE, 140684504915968, 140684505038847,
3365		−STORE, 140684505038848, 140684505071615,
3366		−STORE, 140684505071616, 140684505079807,
3367		−STORE, 140684505079808, 140684505083903,
3368		−STORE, 140733068607488, 140733068611583,
3369		−STORE, 140733068595200, 140733068607487,
3370		−STORE, 46948290084864, 46948290093055,
3371		−STORE, 46948290093056, 46948290101247,
3372		−STORE, 46948290101248, 46948290207743,
3373		−STORE, 46948290117632, 46948290207743,
3374		−STORE, 46948290101248, 46948290117631,
3375		−ERASE, 46948290117632, 46948290117632,
3376		−STORE, 46948290117632, 46948290191359,
3377		−STORE, 46948290191360, 46948290207743,
3378		−STORE, 46948290170880, 46948290191359,
3379		−STORE, 46948290117632, 46948290170879,
3380		−ERASE, 46948290117632, 46948290117632,
3381		−STORE, 46948290117632, 46948290170879,
3382		−STORE, 46948290187264, 46948290191359,
3383		−STORE, 46948290170880, 46948290187263,
3384		−ERASE, 46948290170880, 46948290170880,
3385		−STORE, 46948290170880, 46948290187263,
3386		−STORE, 46948290199552, 46948290207743,
3387		−STORE, 46948290191360, 46948290199551,
3388		−ERASE, 46948290191360, 46948290191360,
3389		−STORE, 46948290191360, 46948290199551,
3390		−ERASE, 46948290199552, 46948290199552,
3391		−STORE, 46948290199552, 46948290207743,
3392		−STORE, 46948290207744, 46948292046847,
3393		−STORE, 46948290347008, 46948292046847,
3394		−STORE, 46948290207744, 46948290347007,
3395		−ERASE, 46948290347008, 46948290347008,
3396		−STORE, 46948290347008, 46948292005887,
3397		−STORE, 46948292005888, 46948292046847,
3398		−STORE, 46948291690496, 46948292005887,
3399		−STORE, 46948290347008, 46948291690495,
3400		−ERASE, 46948290347008, 46948290347008,
3401		−STORE, 46948290347008, 46948291690495,
3402		−STORE, 46948292001792, 46948292005887,
3403		−STORE, 46948291690496, 46948292001791,
3404		−ERASE, 46948291690496, 46948291690496,
3405		−STORE, 46948291690496, 46948292001791,
3406		−STORE, 46948292030464, 46948292046847,
3407		−STORE, 46948292005888, 46948292030463,
3408		−ERASE, 46948292005888, 46948292005888,
3409		−STORE, 46948292005888, 46948292030463,
3410		−ERASE, 46948292030464, 46948292030464,
3411		−STORE, 46948292030464, 46948292046847,
3412		−STORE, 46948292030464, 46948292059135,
3413		−ERASE, 46948292005888, 46948292005888,
3414		−STORE, 46948292005888, 46948292022271,
3415		−STORE, 46948292022272, 46948292030463,
3416		−ERASE, 46948290191360, 46948290191360,
3417		−STORE, 46948290191360, 46948290195455,
3418		−STORE, 46948290195456, 46948290199551,
3419		−ERASE, 94207146442752, 94207146442752,
3420		−STORE, 94207146442752, 94207146459135,
3421		−STORE, 94207146459136, 94207146463231,
3422		−ERASE, 140684505071616, 140684505071616,
3423		−STORE, 140684505071616, 140684505075711,
3424		−STORE, 140684505075712, 140684505079807,
3425		−ERASE, 46948290084864, 46948290084864,
3426		−STORE, 140737488347136, 140737488351231,
3427		−STORE, 140726367158272, 140737488351231,
3428		−ERASE, 140726367158272, 140726367158272,
3429		−STORE, 140726367158272, 140726367162367,
3430		−STORE, 94436124106752, 94436124819455,
3431		−ERASE, 94436124106752, 94436124106752,
3432		−STORE, 94436124106752, 94436124155903,
3433		−STORE, 94436124155904, 94436124819455,
3434		−ERASE, 94436124155904, 94436124155904,
3435		−STORE, 94436124155904, 94436124700671,
3436		−STORE, 94436124700672, 94436124798975,
3437		−STORE, 94436124798976, 94436124819455,
3438		−STORE, 140049025044480, 140049025216511,
3439		−ERASE, 140049025044480, 140049025044480,
3440		−STORE, 140049025044480, 140049025048575,
3441		−STORE, 140049025048576, 140049025216511,
3442		−ERASE, 140049025048576, 140049025048576,
3443		−STORE, 140049025048576, 140049025171455,
3444		−STORE, 140049025171456, 140049025204223,
3445		−STORE, 140049025204224, 140049025212415,
3446		−STORE, 140049025212416, 140049025216511,
3447		−STORE, 140726367256576, 140726367260671,
3448		−STORE, 140726367244288, 140726367256575,
3449		−STORE, 47583769952256, 47583769960447,
3450		−STORE, 47583769960448, 47583769968639,
3451		−STORE, 47583769968640, 47583770075135,
3452		−STORE, 47583769985024, 47583770075135,
3453		−STORE, 47583769968640, 47583769985023,
3454		−ERASE, 47583769985024, 47583769985024,
3455		−STORE, 47583769985024, 47583770058751,
3456		−STORE, 47583770058752, 47583770075135,
3457		−STORE, 47583770038272, 47583770058751,
3458		−STORE, 47583769985024, 47583770038271,
3459		−ERASE, 47583769985024, 47583769985024,
3460		−STORE, 47583769985024, 47583770038271,
3461		−STORE, 47583770054656, 47583770058751,
3462		−STORE, 47583770038272, 47583770054655,
3463		−ERASE, 47583770038272, 47583770038272,
3464		−STORE, 47583770038272, 47583770054655,
3465		−STORE, 47583770066944, 47583770075135,
3466		−STORE, 47583770058752, 47583770066943,
3467		−ERASE, 47583770058752, 47583770058752,
3468		−STORE, 47583770058752, 47583770066943,
3469		−ERASE, 47583770066944, 47583770066944,
3470		−STORE, 47583770066944, 47583770075135,
3471		−STORE, 47583770075136, 47583771914239,
3472		−STORE, 47583770214400, 47583771914239,
3473		−STORE, 47583770075136, 47583770214399,
3474		−ERASE, 47583770214400, 47583770214400,
3475		−STORE, 47583770214400, 47583771873279,
3476		−STORE, 47583771873280, 47583771914239,
3477		−STORE, 47583771557888, 47583771873279,
3478		−STORE, 47583770214400, 47583771557887,
3479		−ERASE, 47583770214400, 47583770214400,
3480		−STORE, 47583770214400, 47583771557887,
3481		−STORE, 47583771869184, 47583771873279,
3482		−STORE, 47583771557888, 47583771869183,
3483		−ERASE, 47583771557888, 47583771557888,
3484		−STORE, 47583771557888, 47583771869183,
3485		−STORE, 47583771897856, 47583771914239,
3486		−STORE, 47583771873280, 47583771897855,
3487		−ERASE, 47583771873280, 47583771873280,
3488		−STORE, 47583771873280, 47583771897855,
3489		−ERASE, 47583771897856, 47583771897856,
3490		−STORE, 47583771897856, 47583771914239,
3491		−STORE, 47583771897856, 47583771926527,
3492		−ERASE, 47583771873280, 47583771873280,
3493		−STORE, 47583771873280, 47583771889663,
3494		−STORE, 47583771889664, 47583771897855,
3495		−ERASE, 47583770058752, 47583770058752,
3496		−STORE, 47583770058752, 47583770062847,
3497		−STORE, 47583770062848, 47583770066943,
3498		−ERASE, 94436124798976, 94436124798976,
3499		−STORE, 94436124798976, 94436124815359,
3500		−STORE, 94436124815360, 94436124819455,
3501		−ERASE, 140049025204224, 140049025204224,
3502		−STORE, 140049025204224, 140049025208319,
3503		−STORE, 140049025208320, 140049025212415,
3504		−ERASE, 47583769952256, 47583769952256,
3505		−STORE, 140737488347136, 140737488351231,
3506		−STORE, 140727116099584, 140737488351231,
3507		−ERASE, 140727116099584, 140727116099584,
3508		−STORE, 140727116099584, 140727116103679,
3509		−STORE, 94166319734784, 94166320447487,
3510		−ERASE, 94166319734784, 94166319734784,
3511		−STORE, 94166319734784, 94166319783935,
3512		−STORE, 94166319783936, 94166320447487,
3513		−ERASE, 94166319783936, 94166319783936,
3514		−STORE, 94166319783936, 94166320328703,
3515		−STORE, 94166320328704, 94166320427007,
3516		−STORE, 94166320427008, 94166320447487,
3517		−STORE, 139976559542272, 139976559714303,
3518		−ERASE, 139976559542272, 139976559542272,
3519		−STORE, 139976559542272, 139976559546367,
3520		−STORE, 139976559546368, 139976559714303,
3521		−ERASE, 139976559546368, 139976559546368,
3522		−STORE, 139976559546368, 139976559669247,
3523		−STORE, 139976559669248, 139976559702015,
3524		−STORE, 139976559702016, 139976559710207,
3525		−STORE, 139976559710208, 139976559714303,
3526		−STORE, 140727116222464, 140727116226559,
3527		−STORE, 140727116210176, 140727116222463,
3528		−STORE, 47656235454464, 47656235462655,
3529		−STORE, 47656235462656, 47656235470847,
3530		−STORE, 47656235470848, 47656235577343,
3531		−STORE, 47656235487232, 47656235577343,
3532		−STORE, 47656235470848, 47656235487231,
3533		−ERASE, 47656235487232, 47656235487232,
3534		−STORE, 47656235487232, 47656235560959,
3535		−STORE, 47656235560960, 47656235577343,
3536		−STORE, 47656235540480, 47656235560959,
3537		−STORE, 47656235487232, 47656235540479,
3538		−ERASE, 47656235487232, 47656235487232,
3539		−STORE, 47656235487232, 47656235540479,
3540		−STORE, 47656235556864, 47656235560959,
3541		−STORE, 47656235540480, 47656235556863,
3542		−ERASE, 47656235540480, 47656235540480,
3543		−STORE, 47656235540480, 47656235556863,
3544		−STORE, 47656235569152, 47656235577343,
3545		−STORE, 47656235560960, 47656235569151,
3546		−ERASE, 47656235560960, 47656235560960,
3547		−STORE, 47656235560960, 47656235569151,
3548		−ERASE, 47656235569152, 47656235569152,
3549		−STORE, 47656235569152, 47656235577343,
3550		−STORE, 47656235577344, 47656237416447,
3551		−STORE, 47656235716608, 47656237416447,
3552		−STORE, 47656235577344, 47656235716607,
3553		−ERASE, 47656235716608, 47656235716608,
3554		−STORE, 47656235716608, 47656237375487,
3555		−STORE, 47656237375488, 47656237416447,
3556		−STORE, 47656237060096, 47656237375487,
3557		−STORE, 47656235716608, 47656237060095,
3558		−ERASE, 47656235716608, 47656235716608,
3559		−STORE, 47656235716608, 47656237060095,
3560		−STORE, 47656237371392, 47656237375487,
3561		−STORE, 47656237060096, 47656237371391,
3562		−ERASE, 47656237060096, 47656237060096,
3563		−STORE, 47656237060096, 47656237371391,
3564		−STORE, 47656237400064, 47656237416447,
3565		−STORE, 47656237375488, 47656237400063,
3566		−ERASE, 47656237375488, 47656237375488,
3567		−STORE, 47656237375488, 47656237400063,
3568		−ERASE, 47656237400064, 47656237400064,
3569		−STORE, 47656237400064, 47656237416447,
3570		−STORE, 47656237400064, 47656237428735,
3571		−ERASE, 47656237375488, 47656237375488,
3572		−STORE, 47656237375488, 47656237391871,
3573		−STORE, 47656237391872, 47656237400063,
3574		−ERASE, 47656235560960, 47656235560960,
3575		−STORE, 47656235560960, 47656235565055,
3576		−STORE, 47656235565056, 47656235569151,
3577		−ERASE, 94166320427008, 94166320427008,
3578		−STORE, 94166320427008, 94166320443391,
3579		−STORE, 94166320443392, 94166320447487,
3580		−ERASE, 139976559702016, 139976559702016,
3581		−STORE, 139976559702016, 139976559706111,
3582		−STORE, 139976559706112, 139976559710207,
3583		−ERASE, 47656235454464, 47656235454464,
3584		−STORE, 94166332153856, 94166332289023,
3585		−STORE, 140737488347136, 140737488351231,
3586		−STORE, 140726412816384, 140737488351231,
3587		−ERASE, 140726412816384, 140726412816384,
3588		−STORE, 140726412816384, 140726412820479,
3589		−STORE, 94094884507648, 94094885220351,
3590		−ERASE, 94094884507648, 94094884507648,
3591		−STORE, 94094884507648, 94094884556799,
3592		−STORE, 94094884556800, 94094885220351,
3593		−ERASE, 94094884556800, 94094884556800,
3594		−STORE, 94094884556800, 94094885101567,
3595		−STORE, 94094885101568, 94094885199871,
3596		−STORE, 94094885199872, 94094885220351,
3597		−STORE, 139773773938688, 139773774110719,
3598		−ERASE, 139773773938688, 139773773938688,
3599		−STORE, 139773773938688, 139773773942783,
3600		−STORE, 139773773942784, 139773774110719,
3601		−ERASE, 139773773942784, 139773773942784,
3602		−STORE, 139773773942784, 139773774065663,
3603		−STORE, 139773774065664, 139773774098431,
3604		−STORE, 139773774098432, 139773774106623,
3605		−STORE, 139773774106624, 139773774110719,
3606		−STORE, 140726412963840, 140726412967935,
3607		−STORE, 140726412951552, 140726412963839,
3608		−STORE, 47859021058048, 47859021066239,
3609		−STORE, 47859021066240, 47859021074431,
3610		−STORE, 47859021074432, 47859021180927,
3611		−STORE, 47859021090816, 47859021180927,
3612		−STORE, 47859021074432, 47859021090815,
3613		−ERASE, 47859021090816, 47859021090816,
3614		−STORE, 47859021090816, 47859021164543,
3615		−STORE, 47859021164544, 47859021180927,
3616		−STORE, 47859021144064, 47859021164543,
3617		−STORE, 47859021090816, 47859021144063,
3618		−ERASE, 47859021090816, 47859021090816,
3619		−STORE, 47859021090816, 47859021144063,
3620		−STORE, 47859021160448, 47859021164543,
3621		−STORE, 47859021144064, 47859021160447,
3622		−ERASE, 47859021144064, 47859021144064,
3623		−STORE, 47859021144064, 47859021160447,
3624		−STORE, 47859021172736, 47859021180927,
3625		−STORE, 47859021164544, 47859021172735,
3626		−ERASE, 47859021164544, 47859021164544,
3627		−STORE, 47859021164544, 47859021172735,
3628		−ERASE, 47859021172736, 47859021172736,
3629		−STORE, 47859021172736, 47859021180927,
3630		−STORE, 47859021180928, 47859023020031,
3631		−STORE, 47859021320192, 47859023020031,
3632		−STORE, 47859021180928, 47859021320191,
3633		−ERASE, 47859021320192, 47859021320192,
3634		−STORE, 47859021320192, 47859022979071,
3635		−STORE, 47859022979072, 47859023020031,
3636		−STORE, 47859022663680, 47859022979071,
3637		−STORE, 47859021320192, 47859022663679,
3638		−ERASE, 47859021320192, 47859021320192,
3639		−STORE, 47859021320192, 47859022663679,
3640		−STORE, 47859022974976, 47859022979071,
3641		−STORE, 47859022663680, 47859022974975,
3642		−ERASE, 47859022663680, 47859022663680,
3643		−STORE, 47859022663680, 47859022974975,
3644		−STORE, 47859023003648, 47859023020031,
3645		−STORE, 47859022979072, 47859023003647,
3646		−ERASE, 47859022979072, 47859022979072,
3647		−STORE, 47859022979072, 47859023003647,
3648		−ERASE, 47859023003648, 47859023003648,
3649		−STORE, 47859023003648, 47859023020031,
3650		−STORE, 47859023003648, 47859023032319,
3651		−ERASE, 47859022979072, 47859022979072,
3652		−STORE, 47859022979072, 47859022995455,
3653		−STORE, 47859022995456, 47859023003647,
3654		−ERASE, 47859021164544, 47859021164544,
3655		−STORE, 47859021164544, 47859021168639,
3656		−STORE, 47859021168640, 47859021172735,
3657		−ERASE, 94094885199872, 94094885199872,
3658		−STORE, 94094885199872, 94094885216255,
3659		−STORE, 94094885216256, 94094885220351,
3660		−ERASE, 139773774098432, 139773774098432,
3661		−STORE, 139773774098432, 139773774102527,
3662		−STORE, 139773774102528, 139773774106623,
3663		−ERASE, 47859021058048, 47859021058048,
3664		−STORE, 94094901108736, 94094901243903,
3665		−STORE, 140737488347136, 140737488351231,
3666		−STORE, 140736567963648, 140737488351231,
3667		−ERASE, 140736567963648, 140736567963648,
3668		−STORE, 140736567963648, 140736567967743,
3669		−STORE, 94924425748480, 94924426461183,
3670		−ERASE, 94924425748480, 94924425748480,
3671		−STORE, 94924425748480, 94924425797631,
3672		−STORE, 94924425797632, 94924426461183,
3673		−ERASE, 94924425797632, 94924425797632,
3674		−STORE, 94924425797632, 94924426342399,
3675		−STORE, 94924426342400, 94924426440703,
3676		−STORE, 94924426440704, 94924426461183,
3677		−STORE, 140042126319616, 140042126491647,
3678		−ERASE, 140042126319616, 140042126319616,
3679		−STORE, 140042126319616, 140042126323711,
3680		−STORE, 140042126323712, 140042126491647,
3681		−ERASE, 140042126323712, 140042126323712,
3682		−STORE, 140042126323712, 140042126446591,
3683		−STORE, 140042126446592, 140042126479359,
3684		−STORE, 140042126479360, 140042126487551,
3685		−STORE, 140042126487552, 140042126491647,
3686		−STORE, 140736568672256, 140736568676351,
3687		−STORE, 140736568659968, 140736568672255,
3688		−STORE, 47590668677120, 47590668685311,
3689		−STORE, 47590668685312, 47590668693503,
3690		−STORE, 47590668693504, 47590668799999,
3691		−STORE, 47590668709888, 47590668799999,
3692		−STORE, 47590668693504, 47590668709887,
3693		−ERASE, 47590668709888, 47590668709888,
3694		−STORE, 47590668709888, 47590668783615,
3695		−STORE, 47590668783616, 47590668799999,
3696		−STORE, 47590668763136, 47590668783615,
3697		−STORE, 47590668709888, 47590668763135,
3698		−ERASE, 47590668709888, 47590668709888,
3699		−STORE, 47590668709888, 47590668763135,
3700		−STORE, 47590668779520, 47590668783615,
3701		−STORE, 47590668763136, 47590668779519,
3702		−ERASE, 47590668763136, 47590668763136,
3703		−STORE, 47590668763136, 47590668779519,
3704		−STORE, 47590668791808, 47590668799999,
3705		−STORE, 47590668783616, 47590668791807,
3706		−ERASE, 47590668783616, 47590668783616,
3707		−STORE, 47590668783616, 47590668791807,
3708		−ERASE, 47590668791808, 47590668791808,
3709		−STORE, 47590668791808, 47590668799999,
3710		−STORE, 47590668800000, 47590670639103,
3711		−STORE, 47590668939264, 47590670639103,
3712		−STORE, 47590668800000, 47590668939263,
3713		−ERASE, 47590668939264, 47590668939264,
3714		−STORE, 47590668939264, 47590670598143,
3715		−STORE, 47590670598144, 47590670639103,
3716		−STORE, 47590670282752, 47590670598143,
3717		−STORE, 47590668939264, 47590670282751,
3718		−ERASE, 47590668939264, 47590668939264,
3719		−STORE, 47590668939264, 47590670282751,
3720		−STORE, 47590670594048, 47590670598143,
3721		−STORE, 47590670282752, 47590670594047,
3722		−ERASE, 47590670282752, 47590670282752,
3723		−STORE, 47590670282752, 47590670594047,
3724		−STORE, 47590670622720, 47590670639103,
3725		−STORE, 47590670598144, 47590670622719,
3726		−ERASE, 47590670598144, 47590670598144,
3727		−STORE, 47590670598144, 47590670622719,
3728		−ERASE, 47590670622720, 47590670622720,
3729		−STORE, 47590670622720, 47590670639103,
3730		−STORE, 47590670622720, 47590670651391,
3731		−ERASE, 47590670598144, 47590670598144,
3732		−STORE, 47590670598144, 47590670614527,
3733		−STORE, 47590670614528, 47590670622719,
3734		−ERASE, 47590668783616, 47590668783616,
3735		−STORE, 47590668783616, 47590668787711,
3736		−STORE, 47590668787712, 47590668791807,
3737		−ERASE, 94924426440704, 94924426440704,
3738		−STORE, 94924426440704, 94924426457087,
3739		−STORE, 94924426457088, 94924426461183,
3740		−ERASE, 140042126479360, 140042126479360,
3741		−STORE, 140042126479360, 140042126483455,
3742		−STORE, 140042126483456, 140042126487551,
3743		−ERASE, 47590668677120, 47590668677120,
3744		−STORE, 140737488347136, 140737488351231,
3745		−STORE, 140733281439744, 140737488351231,
3746		−ERASE, 140733281439744, 140733281439744,
3747		−STORE, 140733281439744, 140733281443839,
3748		−STORE, 94490667069440, 94490667782143,
3749		−ERASE, 94490667069440, 94490667069440,
3750		−STORE, 94490667069440, 94490667118591,
3751		−STORE, 94490667118592, 94490667782143,
3752		−ERASE, 94490667118592, 94490667118592,
3753		−STORE, 94490667118592, 94490667663359,
3754		−STORE, 94490667663360, 94490667761663,
3755		−STORE, 94490667761664, 94490667782143,
3756		−STORE, 139878215118848, 139878215290879,
3757		−ERASE, 139878215118848, 139878215118848,
3758		−STORE, 139878215118848, 139878215122943,
3759		−STORE, 139878215122944, 139878215290879,
3760		−ERASE, 139878215122944, 139878215122944,
3761		−STORE, 139878215122944, 139878215245823,
3762		−STORE, 139878215245824, 139878215278591,
3763		−STORE, 139878215278592, 139878215286783,
3764		−STORE, 139878215286784, 139878215290879,
3765		−STORE, 140733281464320, 140733281468415,
3766		−STORE, 140733281452032, 140733281464319,
3767		−STORE, 47754579877888, 47754579886079,
3768		−STORE, 47754579886080, 47754579894271,
3769		−STORE, 47754579894272, 47754580000767,
3770		−STORE, 47754579910656, 47754580000767,
3771		−STORE, 47754579894272, 47754579910655,
3772		−ERASE, 47754579910656, 47754579910656,
3773		−STORE, 47754579910656, 47754579984383,
3774		−STORE, 47754579984384, 47754580000767,
3775		−STORE, 47754579963904, 47754579984383,
3776		−STORE, 47754579910656, 47754579963903,
3777		−ERASE, 47754579910656, 47754579910656,
3778		−STORE, 47754579910656, 47754579963903,
3779		−STORE, 47754579980288, 47754579984383,
3780		−STORE, 47754579963904, 47754579980287,
3781		−ERASE, 47754579963904, 47754579963904,
3782		−STORE, 47754579963904, 47754579980287,
3783		−STORE, 47754579992576, 47754580000767,
3784		−STORE, 47754579984384, 47754579992575,
3785		−ERASE, 47754579984384, 47754579984384,
3786		−STORE, 47754579984384, 47754579992575,
3787		−ERASE, 47754579992576, 47754579992576,
3788		−STORE, 47754579992576, 47754580000767,
3789		−STORE, 47754580000768, 47754581839871,
3790		−STORE, 47754580140032, 47754581839871,
3791		−STORE, 47754580000768, 47754580140031,
3792		−ERASE, 47754580140032, 47754580140032,
3793		−STORE, 47754580140032, 47754581798911,
3794		−STORE, 47754581798912, 47754581839871,
3795		−STORE, 47754581483520, 47754581798911,
3796		−STORE, 47754580140032, 47754581483519,
3797		−ERASE, 47754580140032, 47754580140032,
3798		−STORE, 47754580140032, 47754581483519,
3799		−STORE, 47754581794816, 47754581798911,
3800		−STORE, 47754581483520, 47754581794815,
3801		−ERASE, 47754581483520, 47754581483520,
3802		−STORE, 47754581483520, 47754581794815,
3803		−STORE, 47754581823488, 47754581839871,
3804		−STORE, 47754581798912, 47754581823487,
3805		−ERASE, 47754581798912, 47754581798912,
3806		−STORE, 47754581798912, 47754581823487,
3807		−ERASE, 47754581823488, 47754581823488,
3808		−STORE, 47754581823488, 47754581839871,
3809		−STORE, 47754581823488, 47754581852159,
3810		−ERASE, 47754581798912, 47754581798912,
3811		−STORE, 47754581798912, 47754581815295,
3812		−STORE, 47754581815296, 47754581823487,
3813		−ERASE, 47754579984384, 47754579984384,
3814		−STORE, 47754579984384, 47754579988479,
3815		−STORE, 47754579988480, 47754579992575,
3816		−ERASE, 94490667761664, 94490667761664,
3817		−STORE, 94490667761664, 94490667778047,
3818		−STORE, 94490667778048, 94490667782143,
3819		−ERASE, 139878215278592, 139878215278592,
3820		−STORE, 139878215278592, 139878215282687,
3821		−STORE, 139878215282688, 139878215286783,
3822		−ERASE, 47754579877888, 47754579877888,
3823		−STORE, 94490669649920, 94490669785087,
3824		−STORE, 140737488347136, 140737488351231,
3825		−STORE, 140735382188032, 140737488351231,
3826		−ERASE, 140735382188032, 140735382188032,
3827		−STORE, 140735382188032, 140735382192127,
3828		−STORE, 94150181302272, 94150182014975,
3829		−ERASE, 94150181302272, 94150181302272,
3830		−STORE, 94150181302272, 94150181351423,
3831		−STORE, 94150181351424, 94150182014975,
3832		−ERASE, 94150181351424, 94150181351424,
3833		−STORE, 94150181351424, 94150181896191,
3834		−STORE, 94150181896192, 94150181994495,
3835		−STORE, 94150181994496, 94150182014975,
3836		−STORE, 139679752458240, 139679752630271,
3837		−ERASE, 139679752458240, 139679752458240,
3838		−STORE, 139679752458240, 139679752462335,
3839		−STORE, 139679752462336, 139679752630271,
3840		−ERASE, 139679752462336, 139679752462336,
3841		−STORE, 139679752462336, 139679752585215,
3842		−STORE, 139679752585216, 139679752617983,
3843		−STORE, 139679752617984, 139679752626175,
3844		−STORE, 139679752626176, 139679752630271,
3845		−STORE, 140735382536192, 140735382540287,
3846		−STORE, 140735382523904, 140735382536191,
3847		−STORE, 47953042538496, 47953042546687,
3848		−STORE, 47953042546688, 47953042554879,
3849		−STORE, 47953042554880, 47953042661375,
3850		−STORE, 47953042571264, 47953042661375,
3851		−STORE, 47953042554880, 47953042571263,
3852		−ERASE, 47953042571264, 47953042571264,
3853		−STORE, 47953042571264, 47953042644991,
3854		−STORE, 47953042644992, 47953042661375,
3855		−STORE, 47953042624512, 47953042644991,
3856		−STORE, 47953042571264, 47953042624511,
3857		−ERASE, 47953042571264, 47953042571264,
3858		−STORE, 47953042571264, 47953042624511,
3859		−STORE, 47953042640896, 47953042644991,
3860		−STORE, 47953042624512, 47953042640895,
3861		−ERASE, 47953042624512, 47953042624512,
3862		−STORE, 47953042624512, 47953042640895,
3863		−STORE, 47953042653184, 47953042661375,
3864		−STORE, 47953042644992, 47953042653183,
3865		−ERASE, 47953042644992, 47953042644992,
3866		−STORE, 47953042644992, 47953042653183,
3867		−ERASE, 47953042653184, 47953042653184,
3868		−STORE, 47953042653184, 47953042661375,
3869		−STORE, 47953042661376, 47953044500479,
3870		−STORE, 47953042800640, 47953044500479,
3871		−STORE, 47953042661376, 47953042800639,
3872		−ERASE, 47953042800640, 47953042800640,
3873		−STORE, 47953042800640, 47953044459519,
3874		−STORE, 47953044459520, 47953044500479,
3875		−STORE, 47953044144128, 47953044459519,
3876		−STORE, 47953042800640, 47953044144127,
3877		−ERASE, 47953042800640, 47953042800640,
3878		−STORE, 47953042800640, 47953044144127,
3879		−STORE, 47953044455424, 47953044459519,
3880		−STORE, 47953044144128, 47953044455423,
3881		−ERASE, 47953044144128, 47953044144128,
3882		−STORE, 47953044144128, 47953044455423,
3883		−STORE, 47953044484096, 47953044500479,
3884		−STORE, 47953044459520, 47953044484095,
3885		−ERASE, 47953044459520, 47953044459520,
3886		−STORE, 47953044459520, 47953044484095,
3887		−ERASE, 47953044484096, 47953044484096,
3888		−STORE, 47953044484096, 47953044500479,
3889		−STORE, 47953044484096, 47953044512767,
3890		−ERASE, 47953044459520, 47953044459520,
3891		−STORE, 47953044459520, 47953044475903,
3892		−STORE, 47953044475904, 47953044484095,
3893		−ERASE, 47953042644992, 47953042644992,
3894		−STORE, 47953042644992, 47953042649087,
3895		−STORE, 47953042649088, 47953042653183,
3896		−ERASE, 94150181994496, 94150181994496,
3897		−STORE, 94150181994496, 94150182010879,
3898		−STORE, 94150182010880, 94150182014975,
3899		−ERASE, 139679752617984, 139679752617984,
3900		−STORE, 139679752617984, 139679752622079,
3901		−STORE, 139679752622080, 139679752626175,
3902		−ERASE, 47953042538496, 47953042538496,
3903		−STORE, 140737488347136, 140737488351231,
3904		−STORE, 140737044123648, 140737488351231,
3905		−ERASE, 140737044123648, 140737044123648,
3906		−STORE, 140737044123648, 140737044127743,
3907		−STORE, 94425324294144, 94425325006847,
3908		−ERASE, 94425324294144, 94425324294144,
3909		−STORE, 94425324294144, 94425324343295,
3910		−STORE, 94425324343296, 94425325006847,
3911		−ERASE, 94425324343296, 94425324343296,
3912		−STORE, 94425324343296, 94425324888063,
3913		−STORE, 94425324888064, 94425324986367,
3914		−STORE, 94425324986368, 94425325006847,
3915		−STORE, 140382015016960, 140382015188991,
3916		−ERASE, 140382015016960, 140382015016960,
3917		−STORE, 140382015016960, 140382015021055,
3918		−STORE, 140382015021056, 140382015188991,
3919		−ERASE, 140382015021056, 140382015021056,
3920		−STORE, 140382015021056, 140382015143935,
3921		−STORE, 140382015143936, 140382015176703,
3922		−STORE, 140382015176704, 140382015184895,
3923		−STORE, 140382015184896, 140382015188991,
3924		−STORE, 140737045585920, 140737045590015,
3925		−STORE, 140737045573632, 140737045585919,
3926		−STORE, 47250779979776, 47250779987967,
3927		−STORE, 47250779987968, 47250779996159,
3928		−STORE, 47250779996160, 47250780102655,
3929		−STORE, 47250780012544, 47250780102655,
3930		−STORE, 47250779996160, 47250780012543,
3931		−ERASE, 47250780012544, 47250780012544,
3932		−STORE, 47250780012544, 47250780086271,
3933		−STORE, 47250780086272, 47250780102655,
3934		−STORE, 47250780065792, 47250780086271,
3935		−STORE, 47250780012544, 47250780065791,
3936		−ERASE, 47250780012544, 47250780012544,
3937		−STORE, 47250780012544, 47250780065791,
3938		−STORE, 47250780082176, 47250780086271,
3939		−STORE, 47250780065792, 47250780082175,
3940		−ERASE, 47250780065792, 47250780065792,
3941		−STORE, 47250780065792, 47250780082175,
3942		−STORE, 47250780094464, 47250780102655,
3943		−STORE, 47250780086272, 47250780094463,
3944		−ERASE, 47250780086272, 47250780086272,
3945		−STORE, 47250780086272, 47250780094463,
3946		−ERASE, 47250780094464, 47250780094464,
3947		−STORE, 47250780094464, 47250780102655,
3948		−STORE, 47250780102656, 47250781941759,
3949		−STORE, 47250780241920, 47250781941759,
3950		−STORE, 47250780102656, 47250780241919,
3951		−ERASE, 47250780241920, 47250780241920,
3952		−STORE, 47250780241920, 47250781900799,
3953		−STORE, 47250781900800, 47250781941759,
3954		−STORE, 47250781585408, 47250781900799,
3955		−STORE, 47250780241920, 47250781585407,
3956		−ERASE, 47250780241920, 47250780241920,
3957		−STORE, 47250780241920, 47250781585407,
3958		−STORE, 47250781896704, 47250781900799,
3959		−STORE, 47250781585408, 47250781896703,
3960		−ERASE, 47250781585408, 47250781585408,
3961		−STORE, 47250781585408, 47250781896703,
3962		−STORE, 47250781925376, 47250781941759,
3963		−STORE, 47250781900800, 47250781925375,
3964		−ERASE, 47250781900800, 47250781900800,
3965		−STORE, 47250781900800, 47250781925375,
3966		−ERASE, 47250781925376, 47250781925376,
3967		−STORE, 47250781925376, 47250781941759,
3968		−STORE, 47250781925376, 47250781954047,
3969		−ERASE, 47250781900800, 47250781900800,
3970		−STORE, 47250781900800, 47250781917183,
3971		−STORE, 47250781917184, 47250781925375,
3972		−ERASE, 47250780086272, 47250780086272,
3973		−STORE, 47250780086272, 47250780090367,
3974		−STORE, 47250780090368, 47250780094463,
3975		−ERASE, 94425324986368, 94425324986368,
3976		−STORE, 94425324986368, 94425325002751,
3977		−STORE, 94425325002752, 94425325006847,
3978		−ERASE, 140382015176704, 140382015176704,
3979		−STORE, 140382015176704, 140382015180799,
3980		−STORE, 140382015180800, 140382015184895,
3981		−ERASE, 47250779979776, 47250779979776,
3982		−STORE, 94425351438336, 94425351573503,
3983		−STORE, 140737488347136, 140737488351231,
3984		−STORE, 140736801144832, 140737488351231,
3985		−ERASE, 140736801144832, 140736801144832,
3986		−STORE, 140736801144832, 140736801148927,
3987		−STORE, 94629429358592, 94629430071295,
3988		−ERASE, 94629429358592, 94629429358592,
3989		−STORE, 94629429358592, 94629429407743,
3990		−STORE, 94629429407744, 94629430071295,
3991		−ERASE, 94629429407744, 94629429407744,
3992		−STORE, 94629429407744, 94629429952511,
3993		−STORE, 94629429952512, 94629430050815,
3994		−STORE, 94629430050816, 94629430071295,
3995		−STORE, 139801685483520, 139801685655551,
3996		−ERASE, 139801685483520, 139801685483520,
3997		−STORE, 139801685483520, 139801685487615,
3998		−STORE, 139801685487616, 139801685655551,
3999		−ERASE, 139801685487616, 139801685487616,
4000		−STORE, 139801685487616, 139801685610495,
4001		−STORE, 139801685610496, 139801685643263,
4002		−STORE, 139801685643264, 139801685651455,
4003		−STORE, 139801685651456, 139801685655551,
4004		−STORE, 140736801198080, 140736801202175,
4005		−STORE, 140736801185792, 140736801198079,
4006		−STORE, 47831109513216, 47831109521407,
4007		−STORE, 47831109521408, 47831109529599,
4008		−STORE, 47831109529600, 47831109636095,
4009		−STORE, 47831109545984, 47831109636095,
4010		−STORE, 47831109529600, 47831109545983,
4011		−ERASE, 47831109545984, 47831109545984,
4012		−STORE, 47831109545984, 47831109619711,
4013		−STORE, 47831109619712, 47831109636095,
4014		−STORE, 47831109599232, 47831109619711,
4015		−STORE, 47831109545984, 47831109599231,
4016		−ERASE, 47831109545984, 47831109545984,
4017		−STORE, 47831109545984, 47831109599231,
4018		−STORE, 47831109615616, 47831109619711,
4019		−STORE, 47831109599232, 47831109615615,
4020		−ERASE, 47831109599232, 47831109599232,
4021		−STORE, 47831109599232, 47831109615615,
4022		−STORE, 47831109627904, 47831109636095,
4023		−STORE, 47831109619712, 47831109627903,
4024		−ERASE, 47831109619712, 47831109619712,
4025		−STORE, 47831109619712, 47831109627903,
4026		−ERASE, 47831109627904, 47831109627904,
4027		−STORE, 47831109627904, 47831109636095,
4028		−STORE, 47831109636096, 47831111475199,
4029		−STORE, 47831109775360, 47831111475199,
4030		−STORE, 47831109636096, 47831109775359,
4031		−ERASE, 47831109775360, 47831109775360,
4032		−STORE, 47831109775360, 47831111434239,
4033		−STORE, 47831111434240, 47831111475199,
4034		−STORE, 47831111118848, 47831111434239,
4035		−STORE, 47831109775360, 47831111118847,
4036		−ERASE, 47831109775360, 47831109775360,
4037		−STORE, 47831109775360, 47831111118847,
4038		−STORE, 47831111430144, 47831111434239,
4039		−STORE, 47831111118848, 47831111430143,
4040		−ERASE, 47831111118848, 47831111118848,
4041		−STORE, 47831111118848, 47831111430143,
4042		−STORE, 47831111458816, 47831111475199,
4043		−STORE, 47831111434240, 47831111458815,
4044		−ERASE, 47831111434240, 47831111434240,
4045		−STORE, 47831111434240, 47831111458815,
4046		−ERASE, 47831111458816, 47831111458816,
4047		−STORE, 47831111458816, 47831111475199,
4048		−STORE, 47831111458816, 47831111487487,
4049		−ERASE, 47831111434240, 47831111434240,
4050		−STORE, 47831111434240, 47831111450623,
4051		−STORE, 47831111450624, 47831111458815,
4052		−ERASE, 47831109619712, 47831109619712,
4053		−STORE, 47831109619712, 47831109623807,
4054		−STORE, 47831109623808, 47831109627903,
4055		−ERASE, 94629430050816, 94629430050816,
4056		−STORE, 94629430050816, 94629430067199,
4057		−STORE, 94629430067200, 94629430071295,
4058		−ERASE, 139801685643264, 139801685643264,
4059		−STORE, 139801685643264, 139801685647359,
4060		−STORE, 139801685647360, 139801685651455,
4061		−ERASE, 47831109513216, 47831109513216,
4062		−STORE, 140737488347136, 140737488351231,
4063		−STORE, 140729419612160, 140737488351231,
4064		−ERASE, 140729419612160, 140729419612160,
4065		−STORE, 140729419612160, 140729419616255,
4066		−STORE, 94443354148864, 94443354861567,
4067		−ERASE, 94443354148864, 94443354148864,
4068		−STORE, 94443354148864, 94443354198015,
4069		−STORE, 94443354198016, 94443354861567,
4070		−ERASE, 94443354198016, 94443354198016,
4071		−STORE, 94443354198016, 94443354742783,
4072		−STORE, 94443354742784, 94443354841087,
4073		−STORE, 94443354841088, 94443354861567,
4074		−STORE, 139741700038656, 139741700210687,
4075		−ERASE, 139741700038656, 139741700038656,
4076		−STORE, 139741700038656, 139741700042751,
4077		−STORE, 139741700042752, 139741700210687,
4078		−ERASE, 139741700042752, 139741700042752,
4079		−STORE, 139741700042752, 139741700165631,
4080		−STORE, 139741700165632, 139741700198399,
4081		−STORE, 139741700198400, 139741700206591,
4082		−STORE, 139741700206592, 139741700210687,
4083		−STORE, 140729420574720, 140729420578815,
4084		−STORE, 140729420562432, 140729420574719,
4085		−STORE, 47891094958080, 47891094966271,
4086		−STORE, 47891094966272, 47891094974463,
4087		−STORE, 47891094974464, 47891095080959,
4088		−STORE, 47891094990848, 47891095080959,
4089		−STORE, 47891094974464, 47891094990847,
4090		−ERASE, 47891094990848, 47891094990848,
4091		−STORE, 47891094990848, 47891095064575,
4092		−STORE, 47891095064576, 47891095080959,
4093		−STORE, 47891095044096, 47891095064575,
4094		−STORE, 47891094990848, 47891095044095,
4095		−ERASE, 47891094990848, 47891094990848,
4096		−STORE, 47891094990848, 47891095044095,
4097		−STORE, 47891095060480, 47891095064575,
4098		−STORE, 47891095044096, 47891095060479,
4099		−ERASE, 47891095044096, 47891095044096,
4100		−STORE, 47891095044096, 47891095060479,
4101		−STORE, 47891095072768, 47891095080959,
4102		−STORE, 47891095064576, 47891095072767,
4103		−ERASE, 47891095064576, 47891095064576,
4104		−STORE, 47891095064576, 47891095072767,
4105		−ERASE, 47891095072768, 47891095072768,
4106		−STORE, 47891095072768, 47891095080959,
4107		−STORE, 47891095080960, 47891096920063,
4108		−STORE, 47891095220224, 47891096920063,
4109		−STORE, 47891095080960, 47891095220223,
4110		−ERASE, 47891095220224, 47891095220224,
4111		−STORE, 47891095220224, 47891096879103,
4112		−STORE, 47891096879104, 47891096920063,
4113		−STORE, 47891096563712, 47891096879103,
4114		−STORE, 47891095220224, 47891096563711,
4115		−ERASE, 47891095220224, 47891095220224,
4116		−STORE, 47891095220224, 47891096563711,
4117		−STORE, 47891096875008, 47891096879103,
4118		−STORE, 47891096563712, 47891096875007,
4119		−ERASE, 47891096563712, 47891096563712,
4120		−STORE, 47891096563712, 47891096875007,
4121		−STORE, 47891096903680, 47891096920063,
4122		−STORE, 47891096879104, 47891096903679,
4123		−ERASE, 47891096879104, 47891096879104,
4124		−STORE, 47891096879104, 47891096903679,
4125		−ERASE, 47891096903680, 47891096903680,
4126		−STORE, 47891096903680, 47891096920063,
4127		−STORE, 47891096903680, 47891096932351,
4128		−ERASE, 47891096879104, 47891096879104,
4129		−STORE, 47891096879104, 47891096895487,
4130		−STORE, 47891096895488, 47891096903679,
4131		−ERASE, 47891095064576, 47891095064576,
4132		−STORE, 47891095064576, 47891095068671,
4133		−STORE, 47891095068672, 47891095072767,
4134		−ERASE, 94443354841088, 94443354841088,
4135		−STORE, 94443354841088, 94443354857471,
4136		−STORE, 94443354857472, 94443354861567,
4137		−ERASE, 139741700198400, 139741700198400,
4138		−STORE, 139741700198400, 139741700202495,
4139		−STORE, 139741700202496, 139741700206591,
4140		−ERASE, 47891094958080, 47891094958080,
4141		−STORE, 94443360825344, 94443360960511,
4142		−STORE, 140737488347136, 140737488351231,
4143		−STORE, 140722961661952, 140737488351231,
4144		−ERASE, 140722961661952, 140722961661952,
4145		−STORE, 140722961661952, 140722961666047,
4146		−STORE, 94878388944896, 94878389657599,
4147		−ERASE, 94878388944896, 94878388944896,
4148		−STORE, 94878388944896, 94878388994047,
4149		−STORE, 94878388994048, 94878389657599,
4150		−ERASE, 94878388994048, 94878388994048,
4151		−STORE, 94878388994048, 94878389538815,
4152		−STORE, 94878389538816, 94878389637119,
4153		−STORE, 94878389637120, 94878389657599,
4154		−STORE, 140210690056192, 140210690228223,
4155		−ERASE, 140210690056192, 140210690056192,
4156		−STORE, 140210690056192, 140210690060287,
4157		−STORE, 140210690060288, 140210690228223,
4158		−ERASE, 140210690060288, 140210690060288,
4159		−STORE, 140210690060288, 140210690183167,
4160		−STORE, 140210690183168, 140210690215935,
4161		−STORE, 140210690215936, 140210690224127,
4162		−STORE, 140210690224128, 140210690228223,
4163		−STORE, 140722963148800, 140722963152895,
4164		−STORE, 140722963136512, 140722963148799,
4165		−STORE, 47422104940544, 47422104948735,
4166		−STORE, 47422104948736, 47422104956927,
4167		−STORE, 47422104956928, 47422105063423,
4168		−STORE, 47422104973312, 47422105063423,
4169		−STORE, 47422104956928, 47422104973311,
4170		−ERASE, 47422104973312, 47422104973312,
4171		−STORE, 47422104973312, 47422105047039,
4172		−STORE, 47422105047040, 47422105063423,
4173		−STORE, 47422105026560, 47422105047039,
4174		−STORE, 47422104973312, 47422105026559,
4175		−ERASE, 47422104973312, 47422104973312,
4176		−STORE, 47422104973312, 47422105026559,
4177		−STORE, 47422105042944, 47422105047039,
4178		−STORE, 47422105026560, 47422105042943,
4179		−ERASE, 47422105026560, 47422105026560,
4180		−STORE, 47422105026560, 47422105042943,
4181		−STORE, 47422105055232, 47422105063423,
4182		−STORE, 47422105047040, 47422105055231,
4183		−ERASE, 47422105047040, 47422105047040,
4184		−STORE, 47422105047040, 47422105055231,
4185		−ERASE, 47422105055232, 47422105055232,
4186		−STORE, 47422105055232, 47422105063423,
4187		−STORE, 47422105063424, 47422106902527,
4188		−STORE, 47422105202688, 47422106902527,
4189		−STORE, 47422105063424, 47422105202687,
4190		−ERASE, 47422105202688, 47422105202688,
4191		−STORE, 47422105202688, 47422106861567,
4192		−STORE, 47422106861568, 47422106902527,
4193		−STORE, 47422106546176, 47422106861567,
4194		−STORE, 47422105202688, 47422106546175,
4195		−ERASE, 47422105202688, 47422105202688,
4196		−STORE, 47422105202688, 47422106546175,
4197		−STORE, 47422106857472, 47422106861567,
4198		−STORE, 47422106546176, 47422106857471,
4199		−ERASE, 47422106546176, 47422106546176,
4200		−STORE, 47422106546176, 47422106857471,
4201		−STORE, 47422106886144, 47422106902527,
4202		−STORE, 47422106861568, 47422106886143,
4203		−ERASE, 47422106861568, 47422106861568,
4204		−STORE, 47422106861568, 47422106886143,
4205		−ERASE, 47422106886144, 47422106886144,
4206		−STORE, 47422106886144, 47422106902527,
4207		−STORE, 47422106886144, 47422106914815,
4208		−ERASE, 47422106861568, 47422106861568,
4209		−STORE, 47422106861568, 47422106877951,
4210		−STORE, 47422106877952, 47422106886143,
4211		−ERASE, 47422105047040, 47422105047040,
4212		−STORE, 47422105047040, 47422105051135,
4213		−STORE, 47422105051136, 47422105055231,
4214		−ERASE, 94878389637120, 94878389637120,
4215		−STORE, 94878389637120, 94878389653503,
4216		−STORE, 94878389653504, 94878389657599,
4217		−ERASE, 140210690215936, 140210690215936,
4218		−STORE, 140210690215936, 140210690220031,
4219		−STORE, 140210690220032, 140210690224127,
4220		−ERASE, 47422104940544, 47422104940544,
4221		−STORE, 140737488347136, 140737488351231,
4222		−STORE, 140727690309632, 140737488351231,
4223		−ERASE, 140727690309632, 140727690309632,
4224		−STORE, 140727690309632, 140727690313727,
4225		−STORE, 94121892208640, 94121892921343,
4226		−ERASE, 94121892208640, 94121892208640,
4227		−STORE, 94121892208640, 94121892257791,
4228		−STORE, 94121892257792, 94121892921343,
4229		−ERASE, 94121892257792, 94121892257792,
4230		−STORE, 94121892257792, 94121892802559,
4231		−STORE, 94121892802560, 94121892900863,
4232		−STORE, 94121892900864, 94121892921343,
4233		−STORE, 140662438326272, 140662438498303,
4234		−ERASE, 140662438326272, 140662438326272,
4235		−STORE, 140662438326272, 140662438330367,
4236		−STORE, 140662438330368, 140662438498303,
4237		−ERASE, 140662438330368, 140662438330368,
4238		−STORE, 140662438330368, 140662438453247,
4239		−STORE, 140662438453248, 140662438486015,
4240		−STORE, 140662438486016, 140662438494207,
4241		−STORE, 140662438494208, 140662438498303,
4242		−STORE, 140727690379264, 140727690383359,
4243		−STORE, 140727690366976, 140727690379263,
4244		−STORE, 46970356670464, 46970356678655,
4245		−STORE, 46970356678656, 46970356686847,
4246		−STORE, 46970356686848, 46970356793343,
4247		−STORE, 46970356703232, 46970356793343,
4248		−STORE, 46970356686848, 46970356703231,
4249		−ERASE, 46970356703232, 46970356703232,
4250		−STORE, 46970356703232, 46970356776959,
4251		−STORE, 46970356776960, 46970356793343,
4252		−STORE, 46970356756480, 46970356776959,
4253		−STORE, 46970356703232, 46970356756479,
4254		−ERASE, 46970356703232, 46970356703232,
4255		−STORE, 46970356703232, 46970356756479,
4256		−STORE, 46970356772864, 46970356776959,
4257		−STORE, 46970356756480, 46970356772863,
4258		−ERASE, 46970356756480, 46970356756480,
4259		−STORE, 46970356756480, 46970356772863,
4260		−STORE, 46970356785152, 46970356793343,
4261		−STORE, 46970356776960, 46970356785151,
4262		−ERASE, 46970356776960, 46970356776960,
4263		−STORE, 46970356776960, 46970356785151,
4264		−ERASE, 46970356785152, 46970356785152,
4265		−STORE, 46970356785152, 46970356793343,
4266		−STORE, 46970356793344, 46970358632447,
4267		−STORE, 46970356932608, 46970358632447,
4268		−STORE, 46970356793344, 46970356932607,
4269		−ERASE, 46970356932608, 46970356932608,
4270		−STORE, 46970356932608, 46970358591487,
4271		−STORE, 46970358591488, 46970358632447,
4272		−STORE, 46970358276096, 46970358591487,
4273		−STORE, 46970356932608, 46970358276095,
4274		−ERASE, 46970356932608, 46970356932608,
4275		−STORE, 46970356932608, 46970358276095,
4276		−STORE, 46970358587392, 46970358591487,
4277		−STORE, 46970358276096, 46970358587391,
4278		−ERASE, 46970358276096, 46970358276096,
4279		−STORE, 46970358276096, 46970358587391,
4280		−STORE, 46970358616064, 46970358632447,
4281		−STORE, 46970358591488, 46970358616063,
4282		−ERASE, 46970358591488, 46970358591488,
4283		−STORE, 46970358591488, 46970358616063,
4284		−ERASE, 46970358616064, 46970358616064,
4285		−STORE, 46970358616064, 46970358632447,
4286		−STORE, 46970358616064, 46970358644735,
4287		−ERASE, 46970358591488, 46970358591488,
4288		−STORE, 46970358591488, 46970358607871,
4289		−STORE, 46970358607872, 46970358616063,
4290		−ERASE, 46970356776960, 46970356776960,
4291		−STORE, 46970356776960, 46970356781055,
4292		−STORE, 46970356781056, 46970356785151,
4293		−ERASE, 94121892900864, 94121892900864,
4294		−STORE, 94121892900864, 94121892917247,
4295		−STORE, 94121892917248, 94121892921343,
4296		−ERASE, 140662438486016, 140662438486016,
4297		−STORE, 140662438486016, 140662438490111,
4298		−STORE, 140662438490112, 140662438494207,
4299		−ERASE, 46970356670464, 46970356670464,
4300		−STORE, 94121898610688, 94121898745855,
4301		−STORE, 140737488347136, 140737488351231,
4302		−STORE, 140737189351424, 140737488351231,
4303		−ERASE, 140737189351424, 140737189351424,
4304		−STORE, 140737189351424, 140737189355519,
4305		−STORE, 93847948832768, 93847949545471,
4306		−ERASE, 93847948832768, 93847948832768,
4307		−STORE, 93847948832768, 93847948881919,
4308		−STORE, 93847948881920, 93847949545471,
4309		−ERASE, 93847948881920, 93847948881920,
4310		−STORE, 93847948881920, 93847949426687,
4311		−STORE, 93847949426688, 93847949524991,
4312		−STORE, 93847949524992, 93847949545471,
4313		−STORE, 139698989985792, 139698990157823,
4314		−ERASE, 139698989985792, 139698989985792,
4315		−STORE, 139698989985792, 139698989989887,
4316		−STORE, 139698989989888, 139698990157823,
4317		−ERASE, 139698989989888, 139698989989888,
4318		−STORE, 139698989989888, 139698990112767,
4319		−STORE, 139698990112768, 139698990145535,
4320		−STORE, 139698990145536, 139698990153727,
4321		−STORE, 139698990153728, 139698990157823,
4322		−STORE, 140737189744640, 140737189748735,
4323		−STORE, 140737189732352, 140737189744639,
4324		−STORE, 47933805010944, 47933805019135,
4325		−STORE, 47933805019136, 47933805027327,
4326		−STORE, 47933805027328, 47933805133823,
4327		−STORE, 47933805043712, 47933805133823,
4328		−STORE, 47933805027328, 47933805043711,
4329		−ERASE, 47933805043712, 47933805043712,
4330		−STORE, 47933805043712, 47933805117439,
4331		−STORE, 47933805117440, 47933805133823,
4332		−STORE, 47933805096960, 47933805117439,
4333		−STORE, 47933805043712, 47933805096959,
4334		−ERASE, 47933805043712, 47933805043712,
4335		−STORE, 47933805043712, 47933805096959,
4336		−STORE, 47933805113344, 47933805117439,
4337		−STORE, 47933805096960, 47933805113343,
4338		−ERASE, 47933805096960, 47933805096960,
4339		−STORE, 47933805096960, 47933805113343,
4340		−STORE, 47933805125632, 47933805133823,
4341		−STORE, 47933805117440, 47933805125631,
4342		−ERASE, 47933805117440, 47933805117440,
4343		−STORE, 47933805117440, 47933805125631,
4344		−ERASE, 47933805125632, 47933805125632,
4345		−STORE, 47933805125632, 47933805133823,
4346		−STORE, 47933805133824, 47933806972927,
4347		−STORE, 47933805273088, 47933806972927,
4348		−STORE, 47933805133824, 47933805273087,
4349		−ERASE, 47933805273088, 47933805273088,
4350		−STORE, 47933805273088, 47933806931967,
4351		−STORE, 47933806931968, 47933806972927,
4352		−STORE, 47933806616576, 47933806931967,
4353		−STORE, 47933805273088, 47933806616575,
4354		−ERASE, 47933805273088, 47933805273088,
4355		−STORE, 47933805273088, 47933806616575,
4356		−STORE, 47933806927872, 47933806931967,
4357		−STORE, 47933806616576, 47933806927871,
4358		−ERASE, 47933806616576, 47933806616576,
4359		−STORE, 47933806616576, 47933806927871,
4360		−STORE, 47933806956544, 47933806972927,
4361		−STORE, 47933806931968, 47933806956543,
4362		−ERASE, 47933806931968, 47933806931968,
4363		−STORE, 47933806931968, 47933806956543,
4364		−ERASE, 47933806956544, 47933806956544,
4365		−STORE, 47933806956544, 47933806972927,
4366		−STORE, 47933806956544, 47933806985215,
4367		−ERASE, 47933806931968, 47933806931968,
4368		−STORE, 47933806931968, 47933806948351,
4369		−STORE, 47933806948352, 47933806956543,
4370		−ERASE, 47933805117440, 47933805117440,
4371		−STORE, 47933805117440, 47933805121535,
4372		−STORE, 47933805121536, 47933805125631,
4373		−ERASE, 93847949524992, 93847949524992,
4374		−STORE, 93847949524992, 93847949541375,
4375		−STORE, 93847949541376, 93847949545471,
4376		−ERASE, 139698990145536, 139698990145536,
4377		−STORE, 139698990145536, 139698990149631,
4378		−STORE, 139698990149632, 139698990153727,
4379		−ERASE, 47933805010944, 47933805010944,
4380		−STORE, 140737488347136, 140737488351231,
4381		−STORE, 140725553991680, 140737488351231,
4382		−ERASE, 140725553991680, 140725553991680,
4383		−STORE, 140725553991680, 140725553995775,
4384		−STORE, 93980056248320, 93980056961023,
4385		−ERASE, 93980056248320, 93980056248320,
4386		−STORE, 93980056248320, 93980056297471,
4387		−STORE, 93980056297472, 93980056961023,
4388		−ERASE, 93980056297472, 93980056297472,
4389		−STORE, 93980056297472, 93980056842239,
4390		−STORE, 93980056842240, 93980056940543,
4391		−STORE, 93980056940544, 93980056961023,
4392		−STORE, 140146588971008, 140146589143039,
4393		−ERASE, 140146588971008, 140146588971008,
4394		−STORE, 140146588971008, 140146588975103,
4395		−STORE, 140146588975104, 140146589143039,
4396		−ERASE, 140146588975104, 140146588975104,
4397		−STORE, 140146588975104, 140146589097983,
4398		−STORE, 140146589097984, 140146589130751,
4399		−STORE, 140146589130752, 140146589138943,
4400		−STORE, 140146589138944, 140146589143039,
4401		−STORE, 140725554860032, 140725554864127,
4402		−STORE, 140725554847744, 140725554860031,
4403		−STORE, 47486206025728, 47486206033919,
4404		−STORE, 47486206033920, 47486206042111,
4405		−STORE, 47486206042112, 47486206148607,
4406		−STORE, 47486206058496, 47486206148607,
4407		−STORE, 47486206042112, 47486206058495,
4408		−ERASE, 47486206058496, 47486206058496,
4409		−STORE, 47486206058496, 47486206132223,
4410		−STORE, 47486206132224, 47486206148607,
4411		−STORE, 47486206111744, 47486206132223,
4412		−STORE, 47486206058496, 47486206111743,
4413		−ERASE, 47486206058496, 47486206058496,
4414		−STORE, 47486206058496, 47486206111743,
4415		−STORE, 47486206128128, 47486206132223,
4416		−STORE, 47486206111744, 47486206128127,
4417		−ERASE, 47486206111744, 47486206111744,
4418		−STORE, 47486206111744, 47486206128127,
4419		−STORE, 47486206140416, 47486206148607,
4420		−STORE, 47486206132224, 47486206140415,
4421		−ERASE, 47486206132224, 47486206132224,
4422		−STORE, 47486206132224, 47486206140415,
4423		−ERASE, 47486206140416, 47486206140416,
4424		−STORE, 47486206140416, 47486206148607,
4425		−STORE, 47486206148608, 47486207987711,
4426		−STORE, 47486206287872, 47486207987711,
4427		−STORE, 47486206148608, 47486206287871,
4428		−ERASE, 47486206287872, 47486206287872,
4429		−STORE, 47486206287872, 47486207946751,
4430		−STORE, 47486207946752, 47486207987711,
4431		−STORE, 47486207631360, 47486207946751,
4432		−STORE, 47486206287872, 47486207631359,
4433		−ERASE, 47486206287872, 47486206287872,
4434		−STORE, 47486206287872, 47486207631359,
4435		−STORE, 47486207942656, 47486207946751,
4436		−STORE, 47486207631360, 47486207942655,
4437		−ERASE, 47486207631360, 47486207631360,
4438		−STORE, 47486207631360, 47486207942655,
4439		−STORE, 47486207971328, 47486207987711,
4440		−STORE, 47486207946752, 47486207971327,
4441		−ERASE, 47486207946752, 47486207946752,
4442		−STORE, 47486207946752, 47486207971327,
4443		−ERASE, 47486207971328, 47486207971328,
4444		−STORE, 47486207971328, 47486207987711,
4445		−STORE, 47486207971328, 47486207999999,
4446		−ERASE, 47486207946752, 47486207946752,
4447		−STORE, 47486207946752, 47486207963135,
4448		−STORE, 47486207963136, 47486207971327,
4449		−ERASE, 47486206132224, 47486206132224,
4450		−STORE, 47486206132224, 47486206136319,
4451		−STORE, 47486206136320, 47486206140415,
4452		−ERASE, 93980056940544, 93980056940544,
4453		−STORE, 93980056940544, 93980056956927,
4454		−STORE, 93980056956928, 93980056961023,
4455		−ERASE, 140146589130752, 140146589130752,
4456		−STORE, 140146589130752, 140146589134847,
4457		−STORE, 140146589134848, 140146589138943,
4458		−ERASE, 47486206025728, 47486206025728,
4459		−STORE, 93980070006784, 93980070141951,
4460		−STORE, 140737488347136, 140737488351231,
4461		−STORE, 140727334776832, 140737488351231,
4462		−ERASE, 140727334776832, 140727334776832,
4463		−STORE, 140727334776832, 140727334780927,
4464		−STORE, 94049747247104, 94049747959807,
4465		−ERASE, 94049747247104, 94049747247104,
4466		−STORE, 94049747247104, 94049747296255,
4467		−STORE, 94049747296256, 94049747959807,
4468		−ERASE, 94049747296256, 94049747296256,
4469		−STORE, 94049747296256, 94049747841023,
4470		−STORE, 94049747841024, 94049747939327,
4471		−STORE, 94049747939328, 94049747959807,
4472		−STORE, 140227307216896, 140227307388927,
4473		−ERASE, 140227307216896, 140227307216896,
4474		−STORE, 140227307216896, 140227307220991,
4475		−STORE, 140227307220992, 140227307388927,
4476		−ERASE, 140227307220992, 140227307220992,
4477		−STORE, 140227307220992, 140227307343871,
4478		−STORE, 140227307343872, 140227307376639,
4479		−STORE, 140227307376640, 140227307384831,
4480		−STORE, 140227307384832, 140227307388927,
4481		−STORE, 140727335337984, 140727335342079,
4482		−STORE, 140727335325696, 140727335337983,
4483		−STORE, 47405487779840, 47405487788031,
4484		−STORE, 47405487788032, 47405487796223,
4485		−STORE, 47405487796224, 47405487902719,
4486		−STORE, 47405487812608, 47405487902719,
4487		−STORE, 47405487796224, 47405487812607,
4488		−ERASE, 47405487812608, 47405487812608,
4489		−STORE, 47405487812608, 47405487886335,
4490		−STORE, 47405487886336, 47405487902719,
4491		−STORE, 47405487865856, 47405487886335,
4492		−STORE, 47405487812608, 47405487865855,
4493		−ERASE, 47405487812608, 47405487812608,
4494		−STORE, 47405487812608, 47405487865855,
4495		−STORE, 47405487882240, 47405487886335,
4496		−STORE, 47405487865856, 47405487882239,
4497		−ERASE, 47405487865856, 47405487865856,
4498		−STORE, 47405487865856, 47405487882239,
4499		−STORE, 47405487894528, 47405487902719,
4500		−STORE, 47405487886336, 47405487894527,
4501		−ERASE, 47405487886336, 47405487886336,
4502		−STORE, 47405487886336, 47405487894527,
4503		−ERASE, 47405487894528, 47405487894528,
4504		−STORE, 47405487894528, 47405487902719,
4505		−STORE, 47405487902720, 47405489741823,
4506		−STORE, 47405488041984, 47405489741823,
4507		−STORE, 47405487902720, 47405488041983,
4508		−ERASE, 47405488041984, 47405488041984,
4509		−STORE, 47405488041984, 47405489700863,
4510		−STORE, 47405489700864, 47405489741823,
4511		−STORE, 47405489385472, 47405489700863,
4512		−STORE, 47405488041984, 47405489385471,
4513		−ERASE, 47405488041984, 47405488041984,
4514		−STORE, 47405488041984, 47405489385471,
4515		−STORE, 47405489696768, 47405489700863,
4516		−STORE, 47405489385472, 47405489696767,
4517		−ERASE, 47405489385472, 47405489385472,
4518		−STORE, 47405489385472, 47405489696767,
4519		−STORE, 47405489725440, 47405489741823,
4520		−STORE, 47405489700864, 47405489725439,
4521		−ERASE, 47405489700864, 47405489700864,
4522		−STORE, 47405489700864, 47405489725439,
4523		−ERASE, 47405489725440, 47405489725440,
4524		−STORE, 47405489725440, 47405489741823,
4525		−STORE, 47405489725440, 47405489754111,
4526		−ERASE, 47405489700864, 47405489700864,
4527		−STORE, 47405489700864, 47405489717247,
4528		−STORE, 47405489717248, 47405489725439,
4529		−ERASE, 47405487886336, 47405487886336,
4530		−STORE, 47405487886336, 47405487890431,
4531		−STORE, 47405487890432, 47405487894527,
4532		−ERASE, 94049747939328, 94049747939328,
4533		−STORE, 94049747939328, 94049747955711,
4534		−STORE, 94049747955712, 94049747959807,
4535		−ERASE, 140227307376640, 140227307376640,
4536		−STORE, 140227307376640, 140227307380735,
4537		−STORE, 140227307380736, 140227307384831,
4538		−ERASE, 47405487779840, 47405487779840,
4539		−STORE, 94049758810112, 94049758945279,
4540		−STORE, 140737488347136, 140737488351231,
4541		−STORE, 140727079718912, 140737488351231,
4542		−ERASE, 140727079718912, 140727079718912,
4543		−STORE, 140727079718912, 140727079723007,
4544		−STORE, 94250996527104, 94250997239807,
4545		−ERASE, 94250996527104, 94250996527104,
4546		−STORE, 94250996527104, 94250996576255,
4547		−STORE, 94250996576256, 94250997239807,
4548		−ERASE, 94250996576256, 94250996576256,
4549		−STORE, 94250996576256, 94250997121023,
4550		−STORE, 94250997121024, 94250997219327,
4551		−STORE, 94250997219328, 94250997239807,
4552		−STORE, 140060022587392, 140060022759423,
4553		−ERASE, 140060022587392, 140060022587392,
4554		−STORE, 140060022587392, 140060022591487,
4555		−STORE, 140060022591488, 140060022759423,
4556		−ERASE, 140060022591488, 140060022591488,
4557		−STORE, 140060022591488, 140060022714367,
4558		−STORE, 140060022714368, 140060022747135,
4559		−STORE, 140060022747136, 140060022755327,
4560		−STORE, 140060022755328, 140060022759423,
4561		−STORE, 140727079788544, 140727079792639,
4562		−STORE, 140727079776256, 140727079788543,
4563		−/* this next one caused issues when lowering the efficiency */
4564		−STORE, 47572772409344, 47572772417535,
4565		−STORE, 47572772417536, 47572772425727,
4566		−STORE, 47572772425728, 47572772532223,
4567		−STORE, 47572772442112, 47572772532223,
4568		−STORE, 47572772425728, 47572772442111,
4569		−ERASE, 47572772442112, 47572772442112,
4570		−STORE, 47572772442112, 47572772515839,
4571		−STORE, 47572772515840, 47572772532223,
4572		−STORE, 47572772495360, 47572772515839,
4573		−STORE, 47572772442112, 47572772495359,
4574		−ERASE, 47572772442112, 47572772442112,
4575		−STORE, 47572772442112, 47572772495359,
4576		−STORE, 47572772511744, 47572772515839,
4577		−STORE, 47572772495360, 47572772511743,
4578		−ERASE, 47572772495360, 47572772495360,
4579		−STORE, 47572772495360, 47572772511743,
4580		−STORE, 47572772524032, 47572772532223,
4581		−STORE, 47572772515840, 47572772524031,
4582		−ERASE, 47572772515840, 47572772515840,
4583		−STORE, 47572772515840, 47572772524031,
4584		−ERASE, 47572772524032, 47572772524032,
4585		−STORE, 47572772524032, 47572772532223,
4586		−STORE, 47572772532224, 47572774371327,
4587		−STORE, 47572772671488, 47572774371327,
4588		−STORE, 47572772532224, 47572772671487,
4589		−ERASE, 47572772671488, 47572772671488,
4590		−STORE, 47572772671488, 47572774330367,
4591		−STORE, 47572774330368, 47572774371327,
4592		−STORE, 47572774014976, 47572774330367,
4593		−STORE, 47572772671488, 47572774014975,
4594		−ERASE, 47572772671488, 47572772671488,
4595		−STORE, 47572772671488, 47572774014975,
4596		−STORE, 47572774326272, 47572774330367,
4597		−STORE, 47572774014976, 47572774326271,
4598		−ERASE, 47572774014976, 47572774014976,
4599		−STORE, 47572774014976, 47572774326271,
4600		−STORE, 47572774354944, 47572774371327,
4601		−STORE, 47572774330368, 47572774354943,
4602		−ERASE, 47572774330368, 47572774330368,
4603		−STORE, 47572774330368, 47572774354943,
4604		−ERASE, 47572774354944, 47572774354944,
4605		−STORE, 47572774354944, 47572774371327,
4606		−STORE, 47572774354944, 47572774383615,
4607		−ERASE, 47572774330368, 47572774330368,
4608		−STORE, 47572774330368, 47572774346751,
4609		−STORE, 47572774346752, 47572774354943,
4610		−ERASE, 47572772515840, 47572772515840,
4611		−STORE, 47572772515840, 47572772519935,
4612		−STORE, 47572772519936, 47572772524031,
4613		−ERASE, 94250997219328, 94250997219328,
4614		−STORE, 94250997219328, 94250997235711,
4615		−STORE, 94250997235712, 94250997239807,
4616		−ERASE, 140060022747136, 140060022747136,
4617		−STORE, 140060022747136, 140060022751231,
4618		−STORE, 140060022751232, 140060022755327,
4619		−ERASE, 47572772409344, 47572772409344,
4620		−STORE, 94251018305536, 94251018440703,
4621		−STORE, 140737488347136, 140737488351231,
4622		−STORE, 140730012389376, 140737488351231,
4623		−ERASE, 140730012389376, 140730012389376,
4624		−STORE, 140730012389376, 140730012393471,
4625		−STORE, 94382607675392, 94382607695871,
4626		−ERASE, 94382607675392, 94382607675392,
4627		−STORE, 94382607675392, 94382607679487,
4628		−STORE, 94382607679488, 94382607695871,
4629		−ERASE, 94382607679488, 94382607679488,
4630		−STORE, 94382607679488, 94382607683583,
4631		−STORE, 94382607683584, 94382607687679,
4632		−STORE, 94382607687680, 94382607695871,
4633		−STORE, 140252451454976, 140252451627007,
4634		−ERASE, 140252451454976, 140252451454976,
4635		−STORE, 140252451454976, 140252451459071,
4636		−STORE, 140252451459072, 140252451627007,
4637		−ERASE, 140252451459072, 140252451459072,
4638		−STORE, 140252451459072, 140252451581951,
4639		−STORE, 140252451581952, 140252451614719,
4640		−STORE, 140252451614720, 140252451622911,
4641		−STORE, 140252451622912, 140252451627007,
4642		−STORE, 140730013548544, 140730013552639,
4643		−STORE, 140730013536256, 140730013548543,
4644		−STORE, 47380343541760, 47380343549951,
4645		−STORE, 47380343549952, 47380343558143,
4646		−STORE, 47380343558144, 47380345397247,
4647		−STORE, 47380343697408, 47380345397247,
4648		−STORE, 47380343558144, 47380343697407,
4649		−ERASE, 47380343697408, 47380343697408,
4650		−STORE, 47380343697408, 47380345356287,
4651		−STORE, 47380345356288, 47380345397247,
4652		−STORE, 47380345040896, 47380345356287,
4653		−STORE, 47380343697408, 47380345040895,
4654		−ERASE, 47380343697408, 47380343697408,
4655		−STORE, 47380343697408, 47380345040895,
4656		−STORE, 47380345352192, 47380345356287,
4657		−STORE, 47380345040896, 47380345352191,
4658		−ERASE, 47380345040896, 47380345040896,
4659		−STORE, 47380345040896, 47380345352191,
4660		−STORE, 47380345380864, 47380345397247,
4661		−STORE, 47380345356288, 47380345380863,
4662		−ERASE, 47380345356288, 47380345356288,
4663		−STORE, 47380345356288, 47380345380863,
4664		−ERASE, 47380345380864, 47380345380864,
4665		−STORE, 47380345380864, 47380345397247,
4666		−ERASE, 47380345356288, 47380345356288,
4667		−STORE, 47380345356288, 47380345372671,
4668		−STORE, 47380345372672, 47380345380863,
4669		−ERASE, 94382607687680, 94382607687680,
4670		−STORE, 94382607687680, 94382607691775,
4671		−STORE, 94382607691776, 94382607695871,
4672		−ERASE, 140252451614720, 140252451614720,
4673		−STORE, 140252451614720, 140252451618815,
4674		−STORE, 140252451618816, 140252451622911,
4675		−ERASE, 47380343541760, 47380343541760,
4676		−STORE, 94382626803712, 94382626938879,
4677		−STORE, 140737488347136, 140737488351231,
4678		−STORE, 140730900271104, 140737488351231,
4679		−ERASE, 140730900271104, 140730900271104,
4680		−STORE, 140730900271104, 140730900275199,
4681		−STORE, 93855478120448, 93855478337535,
4682		−ERASE, 93855478120448, 93855478120448,
4683		−STORE, 93855478120448, 93855478198271,
4684		−STORE, 93855478198272, 93855478337535,
4685		−ERASE, 93855478198272, 93855478198272,
4686		−STORE, 93855478198272, 93855478243327,
4687		−STORE, 93855478243328, 93855478288383,
4688		−STORE, 93855478288384, 93855478337535,
4689		−STORE, 140092686573568, 140092686745599,
4690		−ERASE, 140092686573568, 140092686573568,
4691		−STORE, 140092686573568, 140092686577663,
4692		−STORE, 140092686577664, 140092686745599,
4693		−ERASE, 140092686577664, 140092686577664,
4694		−STORE, 140092686577664, 140092686700543,
4695		−STORE, 140092686700544, 140092686733311,
4696		−STORE, 140092686733312, 140092686741503,
4697		−STORE, 140092686741504, 140092686745599,
4698		−STORE, 140730900537344, 140730900541439,
4699		−STORE, 140730900525056, 140730900537343,
4700		−STORE, 47540108423168, 47540108431359,
4701		−STORE, 47540108431360, 47540108439551,
4702		−STORE, 47540108439552, 47540110278655,
4703		−STORE, 47540108578816, 47540110278655,
4704		−STORE, 47540108439552, 47540108578815,
4705		−ERASE, 47540108578816, 47540108578816,
4706		−STORE, 47540108578816, 47540110237695,
4707		−STORE, 47540110237696, 47540110278655,
4708		−STORE, 47540109922304, 47540110237695,
4709		−STORE, 47540108578816, 47540109922303,
4710		−ERASE, 47540108578816, 47540108578816,
4711		−STORE, 47540108578816, 47540109922303,
4712		−STORE, 47540110233600, 47540110237695,
4713		−STORE, 47540109922304, 47540110233599,
4714		−ERASE, 47540109922304, 47540109922304,
4715		−STORE, 47540109922304, 47540110233599,
4716		−STORE, 47540110262272, 47540110278655,
4717		−STORE, 47540110237696, 47540110262271,
4718		−ERASE, 47540110237696, 47540110237696,
4719		−STORE, 47540110237696, 47540110262271,
4720		−ERASE, 47540110262272, 47540110262272,
4721		−STORE, 47540110262272, 47540110278655,
4722		−ERASE, 47540110237696, 47540110237696,
4723		−STORE, 47540110237696, 47540110254079,
4724		−STORE, 47540110254080, 47540110262271,
4725		−ERASE, 93855478288384, 93855478288384,
4726		−STORE, 93855478288384, 93855478333439,
4727		−STORE, 93855478333440, 93855478337535,
4728		−ERASE, 140092686733312, 140092686733312,
4729		−STORE, 140092686733312, 140092686737407,
4730		−STORE, 140092686737408, 140092686741503,
4731		−ERASE, 47540108423168, 47540108423168,
4732		−STORE, 93855492222976, 93855492358143,
4733		−STORE, 93855492222976, 93855492493311,
4734		−STORE, 140737488347136, 140737488351231,
4735		−STORE, 140733498146816, 140737488351231,
4736		−ERASE, 140733498146816, 140733498146816,
4737		−STORE, 140733498146816, 140733498150911,
4738		−STORE, 94170739654656, 94170740367359,
4739		−ERASE, 94170739654656, 94170739654656,
4740		−STORE, 94170739654656, 94170739703807,
4741		−STORE, 94170739703808, 94170740367359,
4742		−ERASE, 94170739703808, 94170739703808,
4743		−STORE, 94170739703808, 94170740248575,
4744		−STORE, 94170740248576, 94170740346879,
4745		−STORE, 94170740346880, 94170740367359,
4746		−STORE, 140024788877312, 140024789049343,
4747		−ERASE, 140024788877312, 140024788877312,
4748		−STORE, 140024788877312, 140024788881407,
4749		−STORE, 140024788881408, 140024789049343,
4750		−ERASE, 140024788881408, 140024788881408,
4751		−STORE, 140024788881408, 140024789004287,
4752		−STORE, 140024789004288, 140024789037055,
4753		−STORE, 140024789037056, 140024789045247,
4754		−STORE, 140024789045248, 140024789049343,
4755		−STORE, 140733499023360, 140733499027455,
4756		−STORE, 140733499011072, 140733499023359,
4757		−STORE, 47608006119424, 47608006127615,
4758		−STORE, 47608006127616, 47608006135807,
4759		−STORE, 47608006135808, 47608006242303,
4760		−STORE, 47608006152192, 47608006242303,
4761		−STORE, 47608006135808, 47608006152191,
4762		−ERASE, 47608006152192, 47608006152192,
4763		−STORE, 47608006152192, 47608006225919,
4764		−STORE, 47608006225920, 47608006242303,
4765		−STORE, 47608006205440, 47608006225919,
4766		−STORE, 47608006152192, 47608006205439,
4767		−ERASE, 47608006152192, 47608006152192,
4768		−STORE, 47608006152192, 47608006205439,
4769		−STORE, 47608006221824, 47608006225919,
4770		−STORE, 47608006205440, 47608006221823,
4771		−ERASE, 47608006205440, 47608006205440,
4772		−STORE, 47608006205440, 47608006221823,
4773		−STORE, 47608006234112, 47608006242303,
4774		−STORE, 47608006225920, 47608006234111,
4775		−ERASE, 47608006225920, 47608006225920,
4776		−STORE, 47608006225920, 47608006234111,
4777		−ERASE, 47608006234112, 47608006234112,
4778		−STORE, 47608006234112, 47608006242303,
4779		−STORE, 47608006242304, 47608008081407,
4780		−STORE, 47608006381568, 47608008081407,
4781		−STORE, 47608006242304, 47608006381567,
4782		−ERASE, 47608006381568, 47608006381568,
4783		−STORE, 47608006381568, 47608008040447,
4784		−STORE, 47608008040448, 47608008081407,
4785		−STORE, 47608007725056, 47608008040447,
4786		−STORE, 47608006381568, 47608007725055,
4787		−ERASE, 47608006381568, 47608006381568,
4788		−STORE, 47608006381568, 47608007725055,
4789		−STORE, 47608008036352, 47608008040447,
4790		−STORE, 47608007725056, 47608008036351,
4791		−ERASE, 47608007725056, 47608007725056,
4792		−STORE, 47608007725056, 47608008036351,
4793		−STORE, 47608008065024, 47608008081407,
4794		−STORE, 47608008040448, 47608008065023,
4795		−ERASE, 47608008040448, 47608008040448,
4796		−STORE, 47608008040448, 47608008065023,
4797		−ERASE, 47608008065024, 47608008065024,
4798		−STORE, 47608008065024, 47608008081407,
4799		−STORE, 47608008065024, 47608008093695,
4800		−ERASE, 47608008040448, 47608008040448,
4801		−STORE, 47608008040448, 47608008056831,
4802		−STORE, 47608008056832, 47608008065023,
4803		−ERASE, 47608006225920, 47608006225920,
4804		−STORE, 47608006225920, 47608006230015,
4805		−STORE, 47608006230016, 47608006234111,
4806		−ERASE, 94170740346880, 94170740346880,
4807		−STORE, 94170740346880, 94170740363263,
4808		−STORE, 94170740363264, 94170740367359,
4809		−ERASE, 140024789037056, 140024789037056,
4810		−STORE, 140024789037056, 140024789041151,
4811		−STORE, 140024789041152, 140024789045247,
4812		−ERASE, 47608006119424, 47608006119424,
4813		−STORE, 140737488347136, 140737488351231,
4814		−STORE, 140730264326144, 140737488351231,
4815		−ERASE, 140730264326144, 140730264326144,
4816		−STORE, 140730264326144, 140730264330239,
4817		−STORE, 94653216407552, 94653217120255,
4818		−ERASE, 94653216407552, 94653216407552,
4819		−STORE, 94653216407552, 94653216456703,
4820		−STORE, 94653216456704, 94653217120255,
4821		−ERASE, 94653216456704, 94653216456704,
4822		−STORE, 94653216456704, 94653217001471,
4823		−STORE, 94653217001472, 94653217099775,
4824		−STORE, 94653217099776, 94653217120255,
4825		−STORE, 140103617011712, 140103617183743,
4826		−ERASE, 140103617011712, 140103617011712,
4827		−STORE, 140103617011712, 140103617015807,
4828		−STORE, 140103617015808, 140103617183743,
4829		−ERASE, 140103617015808, 140103617015808,
4830		−STORE, 140103617015808, 140103617138687,
4831		−STORE, 140103617138688, 140103617171455,
4832		−STORE, 140103617171456, 140103617179647,
4833		−STORE, 140103617179648, 140103617183743,
4834		−STORE, 140730265427968, 140730265432063,
4835		−STORE, 140730265415680, 140730265427967,
4836		−STORE, 47529177985024, 47529177993215,
4837		−STORE, 47529177993216, 47529178001407,
4838		−STORE, 47529178001408, 47529178107903,
4839		−STORE, 47529178017792, 47529178107903,
4840		−STORE, 47529178001408, 47529178017791,
4841		−ERASE, 47529178017792, 47529178017792,
4842		−STORE, 47529178017792, 47529178091519,
4843		−STORE, 47529178091520, 47529178107903,
4844		−STORE, 47529178071040, 47529178091519,
4845		−STORE, 47529178017792, 47529178071039,
4846		−ERASE, 47529178017792, 47529178017792,
4847		−STORE, 47529178017792, 47529178071039,
4848		−STORE, 47529178087424, 47529178091519,
4849		−STORE, 47529178071040, 47529178087423,
4850		−ERASE, 47529178071040, 47529178071040,
4851		−STORE, 47529178071040, 47529178087423,
4852		−STORE, 47529178099712, 47529178107903,
4853		−STORE, 47529178091520, 47529178099711,
4854		−ERASE, 47529178091520, 47529178091520,
4855		−STORE, 47529178091520, 47529178099711,
4856		−ERASE, 47529178099712, 47529178099712,
4857		−STORE, 47529178099712, 47529178107903,
4858		−STORE, 47529178107904, 47529179947007,
4859		−STORE, 47529178247168, 47529179947007,
4860		−STORE, 47529178107904, 47529178247167,
4861		−ERASE, 47529178247168, 47529178247168,
4862		−STORE, 47529178247168, 47529179906047,
4863		−STORE, 47529179906048, 47529179947007,
4864		−STORE, 47529179590656, 47529179906047,
4865		−STORE, 47529178247168, 47529179590655,
4866		−ERASE, 47529178247168, 47529178247168,
4867		−STORE, 47529178247168, 47529179590655,
4868		−STORE, 47529179901952, 47529179906047,
4869		−STORE, 47529179590656, 47529179901951,
4870		−ERASE, 47529179590656, 47529179590656,
4871		−STORE, 47529179590656, 47529179901951,
4872		−STORE, 47529179930624, 47529179947007,
4873		−STORE, 47529179906048, 47529179930623,
4874		−ERASE, 47529179906048, 47529179906048,
4875		−STORE, 47529179906048, 47529179930623,
4876		−ERASE, 47529179930624, 47529179930624,
4877		−STORE, 47529179930624, 47529179947007,
4878		−STORE, 47529179930624, 47529179959295,
4879		−ERASE, 47529179906048, 47529179906048,
4880		−STORE, 47529179906048, 47529179922431,
4881		−STORE, 47529179922432, 47529179930623,
4882		−ERASE, 47529178091520, 47529178091520,
4883		−STORE, 47529178091520, 47529178095615,
4884		−STORE, 47529178095616, 47529178099711,
4885		−ERASE, 94653217099776, 94653217099776,
4886		−STORE, 94653217099776, 94653217116159,
4887		−STORE, 94653217116160, 94653217120255,
4888		−ERASE, 140103617171456, 140103617171456,
4889		−STORE, 140103617171456, 140103617175551,
4890		−STORE, 140103617175552, 140103617179647,
4891		−ERASE, 47529177985024, 47529177985024,
4892		−STORE, 94653241135104, 94653241270271,
4893		−STORE, 140737488347136, 140737488351231,
4894		−STORE, 140736284549120, 140737488351231,
4895		−ERASE, 140736284549120, 140736284549120,
4896		−STORE, 140736284549120, 140736284553215,
4897		−STORE, 93963663822848, 93963664506879,
4898		−ERASE, 93963663822848, 93963663822848,
4899		−STORE, 93963663822848, 93963663884287,
4900		−STORE, 93963663884288, 93963664506879,
4901		−ERASE, 93963663884288, 93963663884288,
4902		−STORE, 93963663884288, 93963664240639,
4903		−STORE, 93963664240640, 93963664379903,
4904		−STORE, 93963664379904, 93963664506879,
4905		−STORE, 140450188439552, 140450188611583,
4906		−ERASE, 140450188439552, 140450188439552,
4907		−STORE, 140450188439552, 140450188443647,
4908		−STORE, 140450188443648, 140450188611583,
4909		−ERASE, 140450188443648, 140450188443648,
4910		−STORE, 140450188443648, 140450188566527,
4911		−STORE, 140450188566528, 140450188599295,
4912		−STORE, 140450188599296, 140450188607487,
4913		−STORE, 140450188607488, 140450188611583,
4914		−STORE, 140736284577792, 140736284581887,
4915		−STORE, 140736284565504, 140736284577791,
4916		−STORE, 47182606557184, 47182606565375,
4917		−STORE, 47182606565376, 47182606573567,
4918		−STORE, 47182606573568, 47182608412671,
4919		−STORE, 47182606712832, 47182608412671,
4920		−STORE, 47182606573568, 47182606712831,
4921		−ERASE, 47182606712832, 47182606712832,
4922		−STORE, 47182606712832, 47182608371711,
4923		−STORE, 47182608371712, 47182608412671,
4924		−STORE, 47182608056320, 47182608371711,
4925		−STORE, 47182606712832, 47182608056319,
4926		−ERASE, 47182606712832, 47182606712832,
4927		−STORE, 47182606712832, 47182608056319,
4928		−STORE, 47182608367616, 47182608371711,
4929		−STORE, 47182608056320, 47182608367615,
4930		−ERASE, 47182608056320, 47182608056320,
4931		−STORE, 47182608056320, 47182608367615,
4932		−STORE, 47182608396288, 47182608412671,
4933		−STORE, 47182608371712, 47182608396287,
4934		−ERASE, 47182608371712, 47182608371712,
4935		−STORE, 47182608371712, 47182608396287,
4936		−ERASE, 47182608396288, 47182608396288,
4937		−STORE, 47182608396288, 47182608412671,
4938		−STORE, 47182608412672, 47182608523263,
4939		−STORE, 47182608429056, 47182608523263,
4940		−STORE, 47182608412672, 47182608429055,
4941		−ERASE, 47182608429056, 47182608429056,
4942		−STORE, 47182608429056, 47182608515071,
4943		−STORE, 47182608515072, 47182608523263,
4944		−STORE, 47182608490496, 47182608515071,
4945		−STORE, 47182608429056, 47182608490495,
4946		−ERASE, 47182608429056, 47182608429056,
4947		−STORE, 47182608429056, 47182608490495,
4948		−STORE, 47182608510976, 47182608515071,
4949		−STORE, 47182608490496, 47182608510975,
4950		−ERASE, 47182608490496, 47182608490496,
4951		−STORE, 47182608490496, 47182608510975,
4952		−ERASE, 47182608515072, 47182608515072,
4953		−STORE, 47182608515072, 47182608523263,
4954		−STORE, 47182608523264, 47182608568319,
4955		−ERASE, 47182608523264, 47182608523264,
4956		−STORE, 47182608523264, 47182608531455,
4957		−STORE, 47182608531456, 47182608568319,
4958		−STORE, 47182608551936, 47182608568319,
4959		−STORE, 47182608531456, 47182608551935,
4960		−ERASE, 47182608531456, 47182608531456,
4961		−STORE, 47182608531456, 47182608551935,
4962		−STORE, 47182608560128, 47182608568319,
4963		−STORE, 47182608551936, 47182608560127,
4964		−ERASE, 47182608551936, 47182608551936,
4965		−STORE, 47182608551936, 47182608568319,
4966		−ERASE, 47182608551936, 47182608551936,
4967		−STORE, 47182608551936, 47182608560127,
4968		−STORE, 47182608560128, 47182608568319,
4969		−ERASE, 47182608560128, 47182608560128,
4970		−STORE, 47182608560128, 47182608568319,
4971		−STORE, 47182608568320, 47182608916479,
4972		−STORE, 47182608609280, 47182608916479,
4973		−STORE, 47182608568320, 47182608609279,
4974		−ERASE, 47182608609280, 47182608609280,
4975		−STORE, 47182608609280, 47182608891903,
4976		−STORE, 47182608891904, 47182608916479,
4977		−STORE, 47182608822272, 47182608891903,
4978		−STORE, 47182608609280, 47182608822271,
4979		−ERASE, 47182608609280, 47182608609280,
4980		−STORE, 47182608609280, 47182608822271,
4981		−STORE, 47182608887808, 47182608891903,
4982		−STORE, 47182608822272, 47182608887807,
4983		−ERASE, 47182608822272, 47182608822272,
4984		−STORE, 47182608822272, 47182608887807,
4985		−ERASE, 47182608891904, 47182608891904,
4986		−STORE, 47182608891904, 47182608916479,
4987		−STORE, 47182608916480, 47182611177471,
4988		−STORE, 47182609068032, 47182611177471,
4989		−STORE, 47182608916480, 47182609068031,
4990		−ERASE, 47182609068032, 47182609068032,
4991		−STORE, 47182609068032, 47182611161087,
4992		−STORE, 47182611161088, 47182611177471,
4993		−STORE, 47182611169280, 47182611177471,
4994		−STORE, 47182611161088, 47182611169279,
4995		−ERASE, 47182611161088, 47182611161088,
4996		−STORE, 47182611161088, 47182611169279,
4997		−ERASE, 47182611169280, 47182611169280,
4998		−STORE, 47182611169280, 47182611177471,
4999		−STORE, 47182611177472, 47182611312639,
5000		−ERASE, 47182611177472, 47182611177472,
5001		−STORE, 47182611177472, 47182611202047,
5002		−STORE, 47182611202048, 47182611312639,
5003		−STORE, 47182611263488, 47182611312639,
5004		−STORE, 47182611202048, 47182611263487,
5005		−ERASE, 47182611202048, 47182611202048,
5006		−STORE, 47182611202048, 47182611263487,
5007		−STORE, 47182611288064, 47182611312639,
5008		−STORE, 47182611263488, 47182611288063,
5009		−ERASE, 47182611263488, 47182611263488,
5010		−STORE, 47182611263488, 47182611312639,
5011		−ERASE, 47182611263488, 47182611263488,
5012		−STORE, 47182611263488, 47182611288063,
5013		−STORE, 47182611288064, 47182611312639,
5014		−STORE, 47182611296256, 47182611312639,
5015		−STORE, 47182611288064, 47182611296255,
5016		−ERASE, 47182611288064, 47182611288064,
5017		−STORE, 47182611288064, 47182611296255,
5018		−ERASE, 47182611296256, 47182611296256,
5019		−STORE, 47182611296256, 47182611312639,
5020		−STORE, 47182611296256, 47182611320831,
5021		−STORE, 47182611320832, 47182611484671,
5022		−ERASE, 47182611320832, 47182611320832,
5023		−STORE, 47182611320832, 47182611333119,
5024		−STORE, 47182611333120, 47182611484671,
5025		−STORE, 47182611431424, 47182611484671,
5026		−STORE, 47182611333120, 47182611431423,
5027		−ERASE, 47182611333120, 47182611333120,
5028		−STORE, 47182611333120, 47182611431423,
5029		−STORE, 47182611476480, 47182611484671,
5030		−STORE, 47182611431424, 47182611476479,
5031		−ERASE, 47182611431424, 47182611431424,
5032		−STORE, 47182611431424, 47182611484671,
5033		−ERASE, 47182611431424, 47182611431424,
5034		−STORE, 47182611431424, 47182611476479,
5035		−STORE, 47182611476480, 47182611484671,
5036		−ERASE, 47182611476480, 47182611476480,
5037		−STORE, 47182611476480, 47182611484671,
5038		−STORE, 47182611484672, 47182612082687,
5039		−STORE, 47182611603456, 47182612082687,
5040		−STORE, 47182611484672, 47182611603455,
5041		−ERASE, 47182611603456, 47182611603456,
5042		−STORE, 47182611603456, 47182612029439,
5043		−STORE, 47182612029440, 47182612082687,
5044		−STORE, 47182611918848, 47182612029439,
5045		−STORE, 47182611603456, 47182611918847,
5046		−ERASE, 47182611603456, 47182611603456,
5047		−STORE, 47182611603456, 47182611918847,
5048		−STORE, 47182612025344, 47182612029439,
5049		−STORE, 47182611918848, 47182612025343,
5050		−ERASE, 47182611918848, 47182611918848,
5051		−STORE, 47182611918848, 47182612025343,

33494 more lines aren’t shown here.

mm/damon/dbgfs.c+7−0

@@ -890,6 +890,7 @@ out: · 889 unmodified lines
890	890	static int dbgfs_rm_context(char *name)
891	891	{
892	892	struct dentry root, dir, **new_dirs;
	893	+ struct inode *inode;
893	894	struct damon_ctx **new_ctxs;
894	895	int i, j;
895	896	int ret = 0;
@@ -905,6 +906,12 @@ static int dbgfs_rm_context(char *name) · 9 unmodified lines
905	906	if (!dir)
906	907	return -ENOENT;
907	908
	909	+ inode = d_inode(dir);
	910	+ if (!S_ISDIR(inode->i_mode)) {
	911	+ ret = -EINVAL;
	912	+ goto out_dput;
	913	+ }
	914	+
908	915	new_dirs = kmalloc_array(dbgfs_nr_ctxs - 1, sizeof(*dbgfs_dirs),
909	916	GFP_KERNEL);
910	917	if (!new_dirs) {

mm/huge_memory.c+6−3

@@ -2206,9 +2206,12 @@ static void __split_huge_pmd_locked(struct vm_area_struct vma, pmd_t pmd, · 2205 unmodified lines
2206	2206	entry = pte_wrprotect(entry);
2207	2207	if (!young)
2208	2208	entry = pte_mkold(entry);
2209		− /* NOTE: this may set soft-dirty too on some archs */
2210		− if (dirty)
2211		− entry = pte_mkdirty(entry);
	2209	+ /*
	2210	+ * NOTE: we don't do pte_mkdirty when dirty==true
	2211	+ * because it breaks sparc64 which can sigsegv
	2212	+ * random process. Need to revisit when we figure
	2213	+ * out what is special with sparc64.
	2214	+ */
2212	2215	if (soft_dirty)
2213	2216	entry = pte_mksoft_dirty(entry);
2214	2217	if (uffd_wp)

mm/hugetlb.c+4−0

@@ -6111,6 +6111,10 @@ int hugetlb_mcopy_atomic_pte(struct mm_struct *dst_mm, · 6110 unmodified lines
6111	6111
6112	6112	ptl = huge_pte_lock(h, dst_mm, dst_pte);
6113	6113
	6114	+ ret = -EIO;
	6115	+ if (PageHWPoison(page))
	6116	+ goto out_release_unlock;
	6117	+
6114	6118	/*
6115	6119	* We allow to overwrite a pte marker: consider when both MISSING\|WP
6116	6120	* registered, we firstly wr-protect a none pte which has no page cache

mm/hugetlb_vmemmap.c+1−0

@@ -11,6 +11,7 @@ · 10 unmodified lines
11	11	#define pr_fmt(fmt) "HugeTLB: " fmt
12	12
13	13	#include <linux/pgtable.h>
	14	+#include <linux/moduleparam.h>
14	15	#include <linux/bootmem_info.h>
15	16	#include <asm/pgalloc.h>
16	17	#include <asm/tlbflush.h>

mm/kmsan/kmsan.h+2−0

@@ -124,6 +124,8 @@ static __always_inline bool kmsan_in_runtime(void) · 123 unmodified lines
124	124	{
125	125	if ((hardirq_count() >> HARDIRQ_SHIFT) > 1)
126	126	return true;
	127	+ if (in_nmi())
	128	+ return true;
127	129	return kmsan_get_context()->kmsan_in_runtime;
128	130	}
129	131

mm/memory-failure.c+4−1

@@ -1080,6 +1080,7 @@ static int me_huge_page(struct page_state ps, struct page p) · 1079 unmodified lines
1080	1080	int res;
1081	1081	struct page *hpage = compound_head(p);
1082	1082	struct address_space *mapping;
	1083	+ bool extra_pins = false;
1083	1084
1084	1085	if (!PageHuge(hpage))
1085	1086	return MF_DELAYED;
@@ -1087,6 +1088,8 @@ static int me_huge_page(struct page_state ps, struct page p) · 1 unmodified line
1087	1088	mapping = page_mapping(hpage);
1088	1089	if (mapping) {
1089	1090	res = truncate_error_page(hpage, page_to_pfn(p), mapping);
	1091	+ /* The page is kept in page cache. */
	1092	+ extra_pins = true;
1090	1093	unlock_page(hpage);
1091	1094	} else {
1092	1095	unlock_page(hpage);
@@ -1104,7 +1107,7 @@ static int me_huge_page(struct page_state ps, struct page p) · 11 unmodified lines
1104	1107	}
1105	1108	}
1106	1109
1107		− if (has_extra_refcount(ps, p, false))
	1110	+ if (has_extra_refcount(ps, p, extra_pins))
1108	1111	res = MF_FAILED;
1109	1112
1110	1113	return res;

mm/memremap.c+1−0

@@ -335,6 +335,7 @@ void memremap_pages(struct dev_pagemap pgmap, int nid) · 334 unmodified lines
335	335	WARN(1, "File system DAX not supported\n");
336	336	return ERR_PTR(-EINVAL);
337	337	}
	338	+ params.pgprot = pgprot_decrypted(params.pgprot);
338	339	break;
339	340	case MEMORY_DEVICE_GENERIC:
340	341	break;

mm/mmap.c+5−1

@@ -2674,6 +2674,8 @@ cannot_expand: · 2673 unmodified lines
2674	2674	error = -EINVAL;
2675	2675	if (file)
2676	2676	goto close_and_free_vma;
	2677	+ else if (vma->vm_file)
	2678	+ goto unmap_and_free_vma;
2677	2679	else
2678	2680	goto free_vma;
2679	2681	}
@@ -2682,6 +2684,8 @@ cannot_expand: · 2 unmodified lines
2682	2684	error = -ENOMEM;
2683	2685	if (file)
2684	2686	goto close_and_free_vma;
	2687	+ else if (vma->vm_file)
	2688	+ goto unmap_and_free_vma;
2685	2689	else
2686	2690	goto free_vma;
2687	2691	}
@@ -2751,7 +2755,7 @@ unmap_and_free_vma: · 63 unmodified lines
2751	2755
2752	2756	/* Undo any partial mapping done by a device driver. */
2753	2757	unmap_region(mm, mas.tree, vma, prev, next, vma->vm_start, vma->vm_end);
2754		− if (vm_flags & VM_SHARED)
	2758	+ if (file && (vm_flags & VM_SHARED))
2755	2759	mapping_unmap_writable(file->f_mapping);
2756	2760	free_vma:
2757	2761	vm_area_free(vma);

mm/slab_common.c+4−20

@@ -941,7 +941,7 @@ void *__do_kmalloc_node(size_t size, gfp_t flags, int node, unsigned long caller · 940 unmodified lines
941	941
942	942	if (unlikely(size > KMALLOC_MAX_CACHE_SIZE)) {
943	943	ret = __kmalloc_large_node(size, flags, node);
944		− trace_kmalloc(_RET_IP_, ret, size,
	944	+ trace_kmalloc(caller, ret, size,
945	945	PAGE_SIZE << get_order(size), flags, node);
946	946	return ret;
947	947	}
@@ -953,7 +953,7 @@ void *__do_kmalloc_node(size_t size, gfp_t flags, int node, unsigned long caller · 5 unmodified lines
953	953
954	954	ret = __kmem_cache_alloc_node(s, flags, node, size, caller);
955	955	ret = kasan_kmalloc(s, ret, size, flags);
956		− trace_kmalloc(_RET_IP_, ret, size, s->size, flags, node);
	956	+ trace_kmalloc(caller, ret, size, s->size, flags, node);
957	957	return ret;
958	958	}
959	959
@@ -1010,7 +1010,7 @@ EXPORT_SYMBOL(kfree); · 50 unmodified lines
1010	1010
1011	1011	/**
1012	1012	* __ksize -- Report full size of underlying allocation
1013		− * @objp: pointer to the object
	1013	+ * @object: pointer to the object
1014	1014	*
1015	1015	* This should only be used internally to query the true size of allocations.
1016	1016	* It is not meant to be a way to discover the usable size of an allocation
@@ -1018,7 +1018,7 @@ EXPORT_SYMBOL(kfree); · 1 unmodified line
1018	1018	* the originally requested allocation size may trigger KASAN, UBSAN_BOUNDS,
1019	1019	* and/or FORTIFY_SOURCE.
1020	1020	*
1021		− * Return: size of the actual memory used by @objp in bytes
	1021	+ * Return: size of the actual memory used by @object in bytes
1022	1022	*/
1023	1023	size_t __ksize(const void *object)
1024	1024	{
@@ -1040,7 +1040,6 @@ size_t __ksize(const void *object) · 15 unmodified lines
1040	1040	return slab_ksize(folio_slab(folio)->slab_cache);
1041	1041	}
1042	1042
1043		−#ifdef CONFIG_TRACING
1044	1043	void kmalloc_trace(struct kmem_cache s, gfp_t gfpflags, size_t size)
1045	1044	{
1046	1045	void *ret = __kmem_cache_alloc_node(s, gfpflags, NUMA_NO_NODE,
@@ -1064,7 +1063,6 @@ void kmalloc_node_trace(struct kmem_cache s, gfp_t gfpflags, · 17 unmodified lines
1064	1063	return ret;
1065	1064	}
1066	1065	EXPORT_SYMBOL(kmalloc_node_trace);
1067		−#endif /* !CONFIG_TRACING */
1068	1066	#endif /* !CONFIG_SLOB */
1069	1067
1070	1068	gfp_t kmalloc_fix_flags(gfp_t flags)
@@ -1411,20 +1409,6 @@ void kfree_sensitive(const void *p) · 340 unmodified lines
1411	1409	}
1412	1410	EXPORT_SYMBOL(kfree_sensitive);
1413	1411
1414		−/**
1415		− * ksize - get the actual amount of memory allocated for a given object
1416		− * @objp: Pointer to the object
1417		− *
1418		− * kmalloc may internally round up allocations and return more memory
1419		− * than requested. ksize() can be used to determine the actual amount of
1420		− * memory allocated. The caller may use this additional memory, even though
1421		− * a smaller amount of memory was initially specified with the kmalloc call.
1422		− * The caller must guarantee that objp points to a valid object previously
1423		− * allocated with either kmalloc() or kmem_cache_alloc(). The object
1424		− * must not be freed during the duration of the call.
1425		− *
1426		− * Return: size of the actual memory used by @objp in bytes
1427		− */
1428	1412	size_t ksize(const void *objp)
1429	1413	{
1430	1414	size_t size;

mm/userfaultfd.c+1−1

@@ -64,7 +64,7 @@ int mfill_atomic_install_pte(struct mm_struct dst_mm, pmd_t dst_pmd, · 63 unmodified lines
64	64	pte_t _dst_pte, *dst_pte;
65	65	bool writable = dst_vma->vm_flags & VM_WRITE;
66	66	bool vm_shared = dst_vma->vm_flags & VM_SHARED;
67		− bool page_in_cache = page->mapping;
	67	+ bool page_in_cache = page_mapping(page);
68	68	spinlock_t *ptl;
69	69	struct inode *inode;
70	70	pgoff_t offset, max_off;

net/can/af_can.c+2−1

@@ -450,7 +450,7 @@ int can_rx_register(struct net net, struct net_device dev, canid_t can_id, · 449 unmodified lines
450	450
451	451	/* insert new receiver (dev,canid,mask) -> (func,data) */
452	452
453		− if (dev && dev->type != ARPHRD_CAN)
	453	+ if (dev && (dev->type != ARPHRD_CAN \|\| !can_get_ml_priv(dev)))
454	454	return -ENODEV;
455	455
456	456	if (dev && !net_eq(net, dev_net(dev)))
@@ -902,6 +902,7 @@ out_pernet: · 445 unmodified lines
902	902	static __exit void can_exit(void)
903	903	{
904	904	/* protocol unregister */
	905	+ dev_remove_pack(&canxl_packet);
905	906	dev_remove_pack(&canfd_packet);
906	907	dev_remove_pack(&can_packet);
907	908	sock_unregister(PF_CAN);

net/can/isotp.c+38−33

@@ -111,6 +111,9 @@ MODULE_ALIAS("can-proto-6"); · 110 unmodified lines
111	111	#define ISOTP_FC_WT 1 /* wait */
112	112	#define ISOTP_FC_OVFLW 2 /* overflow */
113	113
	114	+#define ISOTP_FC_TIMEOUT 1 /* 1 sec */
	115	+#define ISOTP_ECHO_TIMEOUT 2 /* 2 secs */
	116	+
114	117	enum {
115	118	ISOTP_IDLE = 0,
116	119	ISOTP_WAIT_FIRST_FC,
@@ -258,7 +261,8 @@ static int isotp_send_fc(struct sock *sk, int ae, u8 flowstatus) · 141 unmodified lines
258	261	so->lastrxcf_tstamp = ktime_set(0, 0);
259	262
260	263	/* start rx timeout watchdog */
261		− hrtimer_start(&so->rxtimer, ktime_set(1, 0), HRTIMER_MODE_REL_SOFT);
	264	+ hrtimer_start(&so->rxtimer, ktime_set(ISOTP_FC_TIMEOUT, 0),
	265	+ HRTIMER_MODE_REL_SOFT);
262	266	return 0;
263	267	}
264	268
@@ -344,6 +348,8 @@ static int check_pad(struct isotp_sock so, struct canfd_frame cf, · 79 unmodified lines
344	348	return 0;
345	349	}
346	350
	351	+static void isotp_send_cframe(struct isotp_sock *so);
	352	+
347	353	static int isotp_rcv_fc(struct isotp_sock so, struct canfd_frame cf, int ae)
348	354	{
349	355	struct sock *sk = &so->sk;
@@ -398,14 +404,15 @@ static int isotp_rcv_fc(struct isotp_sock so, struct canfd_frame cf, int ae) · 48 unmodified lines
398	404	case ISOTP_FC_CTS:
399	405	so->tx.bs = 0;
400	406	so->tx.state = ISOTP_SENDING;
401		− /* start cyclic timer for sending CF frame */
402		− hrtimer_start(&so->txtimer, so->tx_gap,
	407	+ /* send CF frame and enable echo timeout handling */
	408	+ hrtimer_start(&so->txtimer, ktime_set(ISOTP_ECHO_TIMEOUT, 0),
403	409	HRTIMER_MODE_REL_SOFT);
	410	+ isotp_send_cframe(so);
404	411	break;
405	412
406	413	case ISOTP_FC_WT:
407	414	/* start timer to wait for next FC frame */
408		− hrtimer_start(&so->txtimer, ktime_set(1, 0),
	415	+ hrtimer_start(&so->txtimer, ktime_set(ISOTP_FC_TIMEOUT, 0),
409	416	HRTIMER_MODE_REL_SOFT);
410	417	break;
411	418
@@ -600,7 +607,7 @@ static int isotp_rcv_cf(struct sock sk, struct canfd_frame cf, int ae, · 188 unmodified lines
600	607	/* perform blocksize handling, if enabled */
601	608	if (!so->rxfc.bs \|\| ++so->rx.bs < so->rxfc.bs) {
602	609	/* start rx timeout watchdog */
603		− hrtimer_start(&so->rxtimer, ktime_set(1, 0),
	610	+ hrtimer_start(&so->rxtimer, ktime_set(ISOTP_FC_TIMEOUT, 0),
604	611	HRTIMER_MODE_REL_SOFT);
605	612	return 0;
606	613	}
@@ -829,7 +836,7 @@ static void isotp_rcv_echo(struct sk_buff skb, void data) · 222 unmodified lines
829	836	struct isotp_sock *so = isotp_sk(sk);
830	837	struct canfd_frame cf = (struct canfd_frame )skb->data;
831	838
832		− /* only handle my own local echo skb's */
	839	+ /* only handle my own local echo CF/SF skb's (no FF!) */
833	840	if (skb->sk != sk \|\| so->cfecho != (u32 )cf->data)
834	841	return;
835	842
@@ -849,13 +856,16 @@ static void isotp_rcv_echo(struct sk_buff skb, void data) · 13 unmodified lines
849	856	if (so->txfc.bs && so->tx.bs >= so->txfc.bs) {
850	857	/* stop and wait for FC with timeout */
851	858	so->tx.state = ISOTP_WAIT_FC;
852		− hrtimer_start(&so->txtimer, ktime_set(1, 0),
	859	+ hrtimer_start(&so->txtimer, ktime_set(ISOTP_FC_TIMEOUT, 0),
853	860	HRTIMER_MODE_REL_SOFT);
854	861	return;
855	862	}
856	863
857	864	/* no gap between data frames needed => use burst mode */
858	865	if (!so->tx_gap) {
	866	+ /* enable echo timeout handling */
	867	+ hrtimer_start(&so->txtimer, ktime_set(ISOTP_ECHO_TIMEOUT, 0),
	868	+ HRTIMER_MODE_REL_SOFT);
859	869	isotp_send_cframe(so);
860	870	return;
861	871	}
@@ -879,7 +889,7 @@ static enum hrtimer_restart isotp_tx_timer_handler(struct hrtimer *hrtimer) · 17 unmodified lines
879	889	/* start timeout for unlikely lost echo skb */
880	890	hrtimer_set_expires(&so->txtimer,
881	891	ktime_add(ktime_get(),
882		− ktime_set(2, 0)));
	892	+ ktime_set(ISOTP_ECHO_TIMEOUT, 0)));
883	893	restart = HRTIMER_RESTART;
884	894
885	895	/* push out the next consecutive frame */
@@ -907,7 +917,8 @@ static enum hrtimer_restart isotp_tx_timer_handler(struct hrtimer *hrtimer) · 21 unmodified lines
907	917	break;
908	918
909	919	default:
910		− WARN_ON_ONCE(1);
	920	+ WARN_ONCE(1, "can-isotp: tx timer state %08X cfecho %08X\n",
	921	+ so->tx.state, so->cfecho);
911	922	}
912	923
913	924	return restart;
@@ -923,7 +934,7 @@ static int isotp_sendmsg(struct socket sock, struct msghdr msg, size_t size) · 9 unmodified lines
923	934	struct canfd_frame *cf;
924	935	int ae = (so->opt.flags & CAN_ISOTP_EXTEND_ADDR) ? 1 : 0;
925	936	int wait_tx_done = (so->opt.flags & CAN_ISOTP_WAIT_TX_DONE) ? 1 : 0;
926		− s64 hrtimer_sec = 0;
	937	+ s64 hrtimer_sec = ISOTP_ECHO_TIMEOUT;
927	938	int off;
928	939	int err;
929	940
@@ -942,6 +953,8 @@ static int isotp_sendmsg(struct socket sock, struct msghdr msg, size_t size) · 12 unmodified lines
942	953	err = wait_event_interruptible(so->wait, so->tx.state == ISOTP_IDLE);
943	954	if (err)
944	955	goto err_out;
	956	+
	957	+ so->tx.state = ISOTP_SENDING;
945	958	}
946	959
947	960	if (!size \|\| size > MAX_MSG_LENGTH) {
@@ -986,6 +999,10 @@ static int isotp_sendmsg(struct socket sock, struct msghdr msg, size_t size) · 38 unmodified lines
986	999	cf = (struct canfd_frame *)skb->data;
987	1000	skb_put_zero(skb, so->ll.mtu);
988	1001
	1002	+ /* cfecho should have been zero'ed by init / former isotp_rcv_echo() */
	1003	+ if (so->cfecho)
	1004	+ pr_notice_once("can-isotp: uninit cfecho %08X\n", so->cfecho);
	1005	+
989	1006	/* check for single frame transmission depending on TX_DL */
990	1007	if (size <= so->tx.ll_dl - SF_PCI_SZ4 - ae - off) {
991	1008	/* The message size generally fits into a SingleFrame - good.
@@ -1011,11 +1028,8 @@ static int isotp_sendmsg(struct socket sock, struct msghdr msg, size_t size) · 19 unmodified lines
1011	1028	else
1012	1029	cf->data[ae] \|= size;
1013	1030
1014		− so->tx.state = ISOTP_IDLE;
1015		− wake_up_interruptible(&so->wait);
1016		−
1017		− /* don't enable wait queue for a single frame transmission */
1018		− wait_tx_done = 0;
	1031	+ /* set CF echo tag for isotp_rcv_echo() (SF-mode) */
	1032	+ so->cfecho = (u32 )cf->data;
1019	1033	} else {
1020	1034	/* send first frame */
1021	1035
@@ -1031,31 +1045,23 @@ static int isotp_sendmsg(struct socket sock, struct msghdr msg, size_t size) · 9 unmodified lines
1031	1045	/* disable wait for FCs due to activated block size */
1032	1046	so->txfc.bs = 0;
1033	1047
1034		− /* cfecho should have been zero'ed by init */
1035		− if (so->cfecho)
1036		− pr_notice_once("can-isotp: no fc cfecho %08X\n",
1037		− so->cfecho);
1038		−
1039		− /* set consecutive frame echo tag */
	1048	+ /* set CF echo tag for isotp_rcv_echo() (CF-mode) */
1040	1049	so->cfecho = (u32 )cf->data;
1041		−
1042		− /* switch directly to ISOTP_SENDING state */
1043		− so->tx.state = ISOTP_SENDING;
1044		−
1045		− /* start timeout for unlikely lost echo skb */
1046		− hrtimer_sec = 2;
1047	1050	} else {
1048	1051	/* standard flow control check */
1049	1052	so->tx.state = ISOTP_WAIT_FIRST_FC;
1050	1053
1051	1054	/* start timeout for FC */
1052		− hrtimer_sec = 1;
1053		− }
	1055	+ hrtimer_sec = ISOTP_FC_TIMEOUT;
1054	1056
1055		− hrtimer_start(&so->txtimer, ktime_set(hrtimer_sec, 0),
1056		− HRTIMER_MODE_REL_SOFT);
	1057	+ /* no CF echo tag for isotp_rcv_echo() (FF-mode) */
	1058	+ so->cfecho = 0;
	1059	+ }
1057	1060	}
1058	1061
	1062	+ hrtimer_start(&so->txtimer, ktime_set(hrtimer_sec, 0),
	1063	+ HRTIMER_MODE_REL_SOFT);
	1064	+
1059	1065	/* send the first or only CAN frame */
1060	1066	cf->flags = so->ll.tx_flags;
1061	1067
@@ -1068,8 +1074,7 @@ static int isotp_sendmsg(struct socket sock, struct msghdr msg, size_t size) · 6 unmodified lines
1068	1074	__func__, ERR_PTR(err));
1069	1075
1070	1076	/* no transmission -> no timeout monitoring */
1071		− if (hrtimer_sec)
1072		− hrtimer_cancel(&so->txtimer);
	1077	+ hrtimer_cancel(&so->txtimer);
1073	1078
1074	1079	/* reset consecutive frame echo tag */
1075	1080	so->cfecho = 0;

net/can/j1939/main.c+3−0

@@ -336,6 +336,9 @@ int j1939_send_one(struct j1939_priv priv, struct sk_buff skb) · 335 unmodified lines
336	336	/* re-claim the CAN_HDR from the SKB */
337	337	cf = skb_push(skb, J1939_CAN_HDR);
338	338
	339	+ /* initialize header structure */
	340	+ memset(cf, 0, J1939_CAN_HDR);
	341	+
339	342	/* make it a full can frame again */
340	343	skb_put(skb, J1939_CAN_FTR + (8 - dlc));
341	344

net/core/skbuff.c+19−17

@@ -4134,23 +4134,25 @@ struct sk_buff skb_segment(struct sk_buff head_skb, · 4133 unmodified lines
4134	4134	int i = 0;
4135	4135	int pos;
4136	4136
4137		− if (list_skb && !list_skb->head_frag && skb_headlen(list_skb) &&
4138		− (skb_shinfo(head_skb)->gso_type & SKB_GSO_DODGY)) {
4139		− /* gso_size is untrusted, and we have a frag_list with a linear
4140		− * non head_frag head.
4141		− *
4142		− * (we assume checking the first list_skb member suffices;
4143		− * i.e if either of the list_skb members have non head_frag
4144		− * head, then the first one has too).
4145		− *
4146		− * If head_skb's headlen does not fit requested gso_size, it
4147		− * means that the frag_list members do NOT terminate on exact
4148		− * gso_size boundaries. Hence we cannot perform skb_frag_t page
4149		− * sharing. Therefore we must fallback to copying the frag_list
4150		− * skbs; we do so by disabling SG.
4151		− */
4152		− if (mss != GSO_BY_FRAGS && mss != skb_headlen(head_skb))
4153		− features &= ~NETIF_F_SG;
	4137	+ if ((skb_shinfo(head_skb)->gso_type & SKB_GSO_DODGY) &&
	4138	+ mss != GSO_BY_FRAGS && mss != skb_headlen(head_skb)) {
	4139	+ struct sk_buff *check_skb;
	4140	+
	4141	+ for (check_skb = list_skb; check_skb; check_skb = check_skb->next) {
	4142	+ if (skb_headlen(check_skb) && !check_skb->head_frag) {
	4143	+ /* gso_size is untrusted, and we have a frag_list with
	4144	+ * a linear non head_frag item.
	4145	+ *
	4146	+ * If head_skb's headlen does not fit requested gso_size,
	4147	+ * it means that the frag_list members do NOT terminate
	4148	+ * on exact gso_size boundaries. Hence we cannot perform
	4149	+ * skb_frag_t page sharing. Therefore we must fallback to
	4150	+ * copying the frag_list skbs; we do so by disabling SG.
	4151	+ */
	4152	+ features &= ~NETIF_F_SG;
	4153	+ break;
	4154	+ }
	4155	+ }
4154	4156	}
4155	4157
4156	4158	__skb_push(head_skb, doffset);

net/core/skmsg.c+2−5

@@ -803,16 +803,13 @@ static void sk_psock_link_destroy(struct sk_psock *psock) · 802 unmodified lines
803	803	}
804	804	}
805	805
806		−void sk_psock_stop(struct sk_psock *psock, bool wait)
	806	+void sk_psock_stop(struct sk_psock *psock)
807	807	{
808	808	spin_lock_bh(&psock->ingress_lock);
809	809	sk_psock_clear_state(psock, SK_PSOCK_TX_ENABLED);
810	810	sk_psock_cork_free(psock);
811	811	__sk_psock_zap_ingress(psock);
812	812	spin_unlock_bh(&psock->ingress_lock);
813		−
814		− if (wait)
815		− cancel_work_sync(&psock->work);
816	813	}
817	814
818	815	static void sk_psock_done_strp(struct sk_psock *psock);
@@ -850,7 +847,7 @@ void sk_psock_drop(struct sock sk, struct sk_psock psock) · 31 unmodified lines
850	847	sk_psock_stop_verdict(sk, psock);
851	848	write_unlock_bh(&sk->sk_callback_lock);
852	849
853		− sk_psock_stop(psock, false);
	850	+ sk_psock_stop(psock);
854	851
855	852	INIT_RCU_WORK(&psock->rwork, sk_psock_destroy);
856	853	queue_rcu_work(system_wq, &psock->rwork);

net/core/sock_map.c+4−3

@@ -1596,7 +1596,7 @@ void sock_map_destroy(struct sock *sk) · 1595 unmodified lines
1596	1596	saved_destroy = psock->saved_destroy;
1597	1597	sock_map_remove_links(sk, psock);
1598	1598	rcu_read_unlock();
1599		− sk_psock_stop(psock, false);
	1599	+ sk_psock_stop(psock);
1600	1600	sk_psock_put(sk, psock);
1601	1601	saved_destroy(sk);
1602	1602	}
@@ -1619,9 +1619,10 @@ void sock_map_close(struct sock *sk, long timeout) · 16 unmodified lines
1619	1619	saved_close = psock->saved_close;
1620	1620	sock_map_remove_links(sk, psock);
1621	1621	rcu_read_unlock();
1622		− sk_psock_stop(psock, true);
1623		− sk_psock_put(sk, psock);
	1622	+ sk_psock_stop(psock);
1624	1623	release_sock(sk);
	1624	+ cancel_work_sync(&psock->work);
	1625	+ sk_psock_put(sk, psock);
1625	1626	saved_close(sk, timeout);
1626	1627	}
1627	1628	EXPORT_SYMBOL_GPL(sock_map_close);

net/ipv4/tcp.c+1−1

@@ -3647,7 +3647,7 @@ int do_tcp_setsockopt(struct sock *sk, int level, int optname, · 3646 unmodified lines
3647	3647	case TCP_REPAIR_OPTIONS:
3648	3648	if (!tp->repair)
3649	3649	err = -EINVAL;
3650		− else if (sk->sk_state == TCP_ESTABLISHED)
	3650	+ else if (sk->sk_state == TCP_ESTABLISHED && !tp->bytes_sent)
3651	3651	err = tcp_repair_options_est(sk, optval, optlen);
3652	3652	else
3653	3653	err = -EPERM;

net/ipv4/tcp_bpf.c+5−3

@@ -278,7 +278,7 @@ static int tcp_bpf_send_verdict(struct sock sk, struct sk_psock psock, · 277 unmodified lines
278	278	{
279	279	bool cork = false, enospc = sk_msg_full(msg);
280	280	struct sock *sk_redir;
281		− u32 tosend, delta = 0;
	281	+ u32 tosend, origsize, sent, delta = 0;
282	282	u32 eval = __SK_NONE;
283	283	int ret;
284	284
@@ -333,10 +333,12 @@ more_data: · 48 unmodified lines
333	333	cork = true;
334	334	psock->cork = NULL;
335	335	}
336		− sk_msg_return(sk, msg, msg->sg.size);
	336	+ sk_msg_return(sk, msg, tosend);
337	337	release_sock(sk);
338	338
	339	+ origsize = msg->sg.size;
339	340	ret = tcp_bpf_sendmsg_redir(sk_redir, msg, tosend, flags);
	341	+ sent = origsize - msg->sg.size;
340	342
341	343	if (eval == __SK_REDIRECT)
342	344	sock_put(sk_redir);
@@ -375,7 +377,7 @@ more_data: · 32 unmodified lines
375	377	msg->sg.data[msg->sg.start].page_link &&
376	378	msg->sg.data[msg->sg.start].length) {
377	379	if (eval == __SK_REDIRECT)
378		− sk_mem_charge(sk, msg->sg.size);
	380	+ sk_mem_charge(sk, tosend - sent);
379	381	goto more_data;
380	382	}
381	383	}

net/ipv6/addrlabel.c+1−0

@@ -437,6 +437,7 @@ static void ip6addrlbl_putmsg(struct nlmsghdr *nlh, · 436 unmodified lines
437	437	{
438	438	struct ifaddrlblmsg *ifal = nlmsg_data(nlh);
439	439	ifal->ifal_family = AF_INET6;
	440	+ ifal->__ifal_reserved = 0;
440	441	ifal->ifal_prefixlen = prefixlen;
441	442	ifal->ifal_flags = 0;
442	443	ifal->ifal_index = ifindex;

net/mac80211/main.c+6−2

@@ -1439,8 +1439,10 @@ int ieee80211_register_hw(struct ieee80211_hw *hw) · 1438 unmodified lines
1439	1439	ieee80211_led_exit(local);
1440	1440	destroy_workqueue(local->workqueue);
1441	1441	fail_workqueue:
1442		− if (local->wiphy_ciphers_allocated)
	1442	+ if (local->wiphy_ciphers_allocated) {
1443	1443	kfree(local->hw.wiphy->cipher_suites);
	1444	+ local->wiphy_ciphers_allocated = false;
	1445	+ }
1444	1446	kfree(local->int_scan_req);
1445	1447	return result;
1446	1448	}
@@ -1508,8 +1510,10 @@ void ieee80211_free_hw(struct ieee80211_hw *hw) · 61 unmodified lines
1508	1510	mutex_destroy(&local->iflist_mtx);
1509	1511	mutex_destroy(&local->mtx);
1510	1512
1511		− if (local->wiphy_ciphers_allocated)
	1513	+ if (local->wiphy_ciphers_allocated) {
1512	1514	kfree(local->hw.wiphy->cipher_suites);
	1515	+ local->wiphy_ciphers_allocated = false;
	1516	+ }
1513	1517
1514	1518	idr_for_each(&local->ack_status_frames,
1515	1519	ieee80211_free_ack_frame, NULL);

net/mac80211/mesh_pathtbl.c+1−1

@@ -710,7 +710,7 @@ int mesh_path_send_to_gates(struct mesh_path *mpath) · 709 unmodified lines
710	710	void mesh_path_discard_frame(struct ieee80211_sub_if_data *sdata,
711	711	struct sk_buff *skb)
712	712	{
713		− kfree_skb(skb);
	713	+ ieee80211_free_txskb(&sdata->local->hw, skb);
714	714	sdata->u.mesh.mshstats.dropped_frames_no_route++;
715	715	}
716	716

net/mac80211/s1g.c+3−0

@@ -112,6 +112,9 @@ ieee80211_s1g_rx_twt_setup(struct ieee80211_sub_if_data *sdata, · 111 unmodified lines
112	112	goto out;
113	113	}
114	114
	115	+ /* TWT Information not supported yet */
	116	+ twt->control \|= IEEE80211_TWT_CONTROL_RX_DISABLED;
	117	+
115	118	drv_add_twt_setup(sdata->local, sdata, &sta->sta, twt);
116	119	out:
117	120	ieee80211_s1g_send_twt_setup(sdata, mgmt->sa, sdata->vif.addr, twt);

net/mac80211/tx.c+5−0

@@ -4418,6 +4418,11 @@ netdev_tx_t ieee80211_subif_start_xmit(struct sk_buff *skb, · 4417 unmodified lines
4418	4418	if (likely(!is_multicast_ether_addr(eth->h_dest)))
4419	4419	goto normal;
4420	4420
	4421	+ if (unlikely(!ieee80211_sdata_running(sdata))) {
	4422	+ kfree_skb(skb);
	4423	+ return NETDEV_TX_OK;
	4424	+ }
	4425	+
4421	4426	if (unlikely(ieee80211_multicast_to_unicast(skb, dev))) {
4422	4427	struct sk_buff_head queue;
4423	4428

net/mctp/af_mctp.c+3−1

@@ -665,12 +665,14 @@ static __init int mctp_init(void) · 664 unmodified lines
665	665
666	666	rc = mctp_neigh_init();
667	667	if (rc)
668		− goto err_unreg_proto;
	668	+ goto err_unreg_routes;
669	669
670	670	mctp_device_init();
671	671
672	672	return 0;
673	673
	674	+err_unreg_routes:
	675	+ mctp_routes_exit();
674	676	err_unreg_proto:
675	677	proto_unregister(&mctp_proto);
676	678	err_unreg_sock:

net/mctp/route.c+1−1

@@ -1400,7 +1400,7 @@ int __init mctp_routes_init(void) · 1399 unmodified lines
1400	1400	return register_pernet_subsys(&mctp_net_ops);
1401	1401	}
1402	1402
1403		−void __exit mctp_routes_exit(void)
	1403	+void mctp_routes_exit(void)
1404	1404	{
1405	1405	unregister_pernet_subsys(&mctp_net_ops);
1406	1406	rtnl_unregister(PF_MCTP, RTM_DELROUTE);

net/netfilter/nf_tables_api.c+2−1

@@ -10090,7 +10090,8 @@ static void __net_exit nf_tables_exit_net(struct net *net) · 10089 unmodified lines
10090	10090	struct nftables_pernet *nft_net = nft_pernet(net);
10091	10091
10092	10092	mutex_lock(&nft_net->commit_mutex);
10093		− if (!list_empty(&nft_net->commit_list))
	10093	+ if (!list_empty(&nft_net->commit_list) \|\|
	10094	+ !list_empty(&nft_net->module_list))
10094	10095	__nf_tables_abort(net, NFNL_ABORT_NONE);
10095	10096	__nft_release_tables(net);
10096	10097	mutex_unlock(&nft_net->commit_mutex);

net/netfilter/nfnetlink.c+1−0

@@ -294,6 +294,7 @@ replay: · 293 unmodified lines
294	294	nfnl_lock(subsys_id);
295	295	if (nfnl_dereference_protected(subsys_id) != ss \|\|
296	296	nfnetlink_find_client(type, ss) != nc) {
	297	+ nfnl_unlock(subsys_id);
297	298	err = -EAGAIN;
298	299	break;
299	300	}

net/sctp/outqueue.c+8−5

@@ -384,6 +384,7 @@ static int sctp_prsctp_prune_unsent(struct sctp_association *asoc, · 383 unmodified lines
384	384	{
385	385	struct sctp_outq *q = &asoc->outqueue;
386	386	struct sctp_chunk chk, temp;
	387	+ struct sctp_stream_out *sout;
387	388
388	389	q->sched->unsched_all(&asoc->stream);
389	390
@@ -398,12 +399,14 @@ static int sctp_prsctp_prune_unsent(struct sctp_association *asoc, · 8 unmodified lines
398	399	sctp_sched_dequeue_common(q, chk);
399	400	asoc->sent_cnt_removable--;
400	401	asoc->abandoned_unsent[SCTP_PR_INDEX(PRIO)]++;
401		− if (chk->sinfo.sinfo_stream < asoc->stream.outcnt) {
402		− struct sctp_stream_out *streamout =
403		− SCTP_SO(&asoc->stream, chk->sinfo.sinfo_stream);
404	402
405		− streamout->ext->abandoned_unsent[SCTP_PR_INDEX(PRIO)]++;
406		− }
	403	+ sout = SCTP_SO(&asoc->stream, chk->sinfo.sinfo_stream);
	404	+ sout->ext->abandoned_unsent[SCTP_PR_INDEX(PRIO)]++;
	405	+
	406	+ /* clear out_curr if all frag chunks are pruned */
	407	+ if (asoc->stream.out_curr == sout &&
	408	+ list_is_last(&chk->frag_list, &chk->msg->chunks))
	409	+ asoc->stream.out_curr = NULL;
407	410
408	411	msg_len -= chk->skb->truesize + sizeof(struct sctp_chunk);
409	412	sctp_chunk_free(chk);

net/tipc/netlink_compat.c+1−1

@@ -880,7 +880,7 @@ static int tipc_nl_compat_name_table_dump_header(struct tipc_nl_compat_msg *msg) · 879 unmodified lines
880	880	};
881	881
882	882	ntq = (struct tipc_name_table_query *)TLV_DATA(msg->req);
883		− if (TLV_GET_DATA_LEN(msg->req) < sizeof(struct tipc_name_table_query))
	883	+ if (TLV_GET_DATA_LEN(msg->req) < (int)sizeof(struct tipc_name_table_query))
884	884	return -EINVAL;
885	885
886	886	depth = ntohl(ntq->depth);

net/wireless/reg.c+9−3

@@ -1084,6 +1084,8 @@ MODULE_FIRMWARE("regulatory.db"); · 1083 unmodified lines
1084	1084
1085	1085	static int query_regdb_file(const char *alpha2)
1086	1086	{
	1087	+ int err;
	1088	+
1087	1089	ASSERT_RTNL();
1088	1090
1089	1091	if (regdb)
@@ -1093,9 +1095,13 @@ static int query_regdb_file(const char *alpha2) · 3 unmodified lines
1093	1095	if (!alpha2)
1094	1096	return -ENOMEM;
1095	1097
1096		− return request_firmware_nowait(THIS_MODULE, true, "regulatory.db",
1097		− &reg_pdev->dev, GFP_KERNEL,
1098		− (void *)alpha2, regdb_fw_cb);
	1098	+ err = request_firmware_nowait(THIS_MODULE, true, "regulatory.db",
	1099	+ &reg_pdev->dev, GFP_KERNEL,
	1100	+ (void *)alpha2, regdb_fw_cb);
	1101	+ if (err)
	1102	+ kfree(alpha2);
	1103	+
	1104	+ return err;
1099	1105	}
1100	1106
1101	1107	int reg_reload_regdb(void)

net/wireless/scan.c+3−1

@@ -1674,7 +1674,9 @@ cfg80211_update_known_bss(struct cfg80211_registered_device *rdev, · 1673 unmodified lines
1674	1674	if (old == rcu_access_pointer(known->pub.ies))
1675	1675	rcu_assign_pointer(known->pub.ies, new->pub.beacon_ies);
1676	1676
1677		− cfg80211_update_hidden_bsses(known, new->pub.beacon_ies, old);
	1677	+ cfg80211_update_hidden_bsses(known,
	1678	+ rcu_access_pointer(new->pub.beacon_ies),
	1679	+ old);
1678	1680
1679	1681	if (old)
1680	1682	kfree_rcu((struct cfg80211_bss_ies *)old, rcu_head);

net/wireless/util.c+4−2

@@ -1557,10 +1557,12 @@ static u32 cfg80211_calculate_bitrate_eht(struct rate_info *rate) · 1556 unmodified lines
1557	1557	tmp = result;
1558	1558	tmp *= SCALE;
1559	1559	do_div(tmp, mcs_divisors[rate->mcs]);
1560		− result = tmp;
1561	1560
1562	1561	/* and take NSS */
1563		− result = (result * rate->nss) / 8;
	1562	+ tmp *= rate->nss;
	1563	+ do_div(tmp, 8);
	1564	+
	1565	+ result = tmp;
1564	1566
1565	1567	return result / 10000;
1566	1568	}

scripts/min-tool-version.sh+1−1

@@ -25,7 +25,7 @@ icc) · 24 unmodified lines
25	25	;;
26	26	llvm)
27	27	if [ "$SRCARCH" = s390 ]; then
28		− echo 14.0.0
	28	+ echo 15.0.0
29	29	else
30	30	echo 11.0.0
31	31	fi

sound/arm/pxa2xx-ac97-lib.c+3−1

@@ -402,8 +402,10 @@ int pxa2xx_ac97_hw_probe(struct platform_device *dev) · 401 unmodified lines
402	402	goto err_clk2;
403	403
404	404	irq = platform_get_irq(dev, 0);
405		− if (!irq)
	405	+ if (irq < 0) {
	406	+ ret = irq;
406	407	goto err_irq;
	408	+ }
407	409
408	410	ret = request_irq(irq, pxa2xx_ac97_irq, 0, "AC97", NULL);
409	411	if (ret < 0)

sound/core/memalloc.c+8−7

@@ -9,6 +9,7 @@ · 8 unmodified lines
9	9	#include <linux/slab.h>
10	10	#include <linux/mm.h>
11	11	#include <linux/dma-mapping.h>
	12	+#include <linux/dma-map-ops.h>
12	13	#include <linux/genalloc.h>
13	14	#include <linux/highmem.h>
14	15	#include <linux/vmalloc.h>
@@ -543,17 +544,17 @@ static void snd_dma_noncontig_alloc(struct snd_dma_buffer dmab, size_t size) · 528 unmodified lines
543	544
544	545	sgt = dma_alloc_noncontiguous(dmab->dev.dev, size, dmab->dev.dir,
545	546	DEFAULT_GFP, 0);
546		− if (!sgt) {
547	547	#ifdef CONFIG_SND_DMA_SGBUF
	548	+ if (!sgt && !get_dma_ops(dmab->dev.dev)) {
548	549	if (dmab->dev.type == SNDRV_DMA_TYPE_DEV_WC_SG)
549	550	dmab->dev.type = SNDRV_DMA_TYPE_DEV_WC_SG_FALLBACK;
550	551	else
551	552	dmab->dev.type = SNDRV_DMA_TYPE_DEV_SG_FALLBACK;
552	553	return snd_dma_sg_fallback_alloc(dmab, size);
553		−#else
554		− return NULL;
555		−#endif
556	554	}
	555	+#endif
	556	+ if (!sgt)
	557	+ return NULL;
557	558
558	559	dmab->dev.need_sync = dma_need_sync(dmab->dev.dev,
559	560	sg_dma_address(sgt->sgl));
@@ -857,7 +858,7 @@ static const struct snd_malloc_ops snd_dma_noncoherent_ops = { · 297 unmodified lines
857	858	/*
858	859	* Entry points
859	860	*/
860		−static const struct snd_malloc_ops *dma_ops[] = {
	861	+static const struct snd_malloc_ops *snd_dma_ops[] = {
861	862	[SNDRV_DMA_TYPE_CONTINUOUS] = &snd_dma_continuous_ops,
862	863	[SNDRV_DMA_TYPE_VMALLOC] = &snd_dma_vmalloc_ops,
863	864	#ifdef CONFIG_HAS_DMA
@@ -883,7 +884,7 @@ static const struct snd_malloc_ops snd_dma_get_ops(struct snd_dma_buffer dmab) · 19 unmodified lines
883	884	if (WARN_ON_ONCE(!dmab))
884	885	return NULL;
885	886	if (WARN_ON_ONCE(dmab->dev.type <= SNDRV_DMA_TYPE_UNKNOWN \|\|
886		− dmab->dev.type >= ARRAY_SIZE(dma_ops)))
	887	+ dmab->dev.type >= ARRAY_SIZE(snd_dma_ops)))
887	888	return NULL;
888		− return dma_ops[dmab->dev.type];
	889	+ return snd_dma_ops[dmab->dev.type];
889	890	}

sound/hda/hdac_sysfs.c+3−1

@@ -346,8 +346,10 @@ static int add_widget_node(struct kobject *parent, hda_nid_t nid, · 345 unmodified lines
346	346	return -ENOMEM;
347	347	kobject_init(kobj, &widget_ktype);
348	348	err = kobject_add(kobj, parent, "%02x", nid);
349		− if (err < 0)
	349	+ if (err < 0) {
	350	+ kobject_put(kobj);
350	351	return err;
	352	+ }
351	353	err = sysfs_create_group(kobj, group);
352	354	if (err < 0) {
353	355	kobject_put(kobj);

sound/pci/hda/hda_intel.c+7−4

@@ -485,8 +485,8 @@ static int intel_ml_lctl_set_power(struct azx *chip, int state) · 484 unmodified lines
485	485	int timeout;
486	486
487	487	/*
488		− * the codecs are sharing the first link setting by default
489		− * If other links are enabled for stream, they need similar fix
	488	+ * Changes to LCTL.SCF are only needed for the first multi-link dealing
	489	+ * with external codecs
490	490	*/
491	491	val = readl(bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL);
492	492	val &= ~AZX_ML_LCTL_SPA;
@@ -513,7 +513,7 @@ static void intel_init_lctl(struct azx *chip) · 20 unmodified lines
513	513
514	514	/* 0. check lctl register value is correct or not */
515	515	val = readl(bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL);
516		− /* if SCF is already set, let's use it */
	516	+ /* only perform additional configurations if the SCF is initially based on 6MHz */
517	517	if ((val & AZX_ML_LCTL_SCF) != 0)
518	518	return;
519	519
@@ -531,7 +531,7 @@ static void intel_init_lctl(struct azx *chip) · 11 unmodified lines
531	531	if (ret)
532	532	goto set_spa;
533	533
534		− /* 2. update SCF to select a properly audio clock*/
	534	+ /* 2. update SCF to select an audio clock different from 6MHz */
535	535	val &= ~AZX_ML_LCTL_SCF;
536	536	val \|= intel_get_lctl_scf(chip);
537	537	writel(val, bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL);
@@ -2711,6 +2711,9 @@ static const struct pci_device_id azx_ids[] = { · 2173 unmodified lines
2711	2711	{ PCI_DEVICE(0x1002, 0xab28),
2712	2712	.driver_data = AZX_DRIVER_ATIHDMI_NS \| AZX_DCAPS_PRESET_ATI_HDMI_NS \|
2713	2713	AZX_DCAPS_PM_RUNTIME },
	2714	+ { PCI_DEVICE(0x1002, 0xab30),
	2715	+ .driver_data = AZX_DRIVER_ATIHDMI_NS \| AZX_DCAPS_PRESET_ATI_HDMI_NS \|
	2716	+ AZX_DCAPS_PM_RUNTIME },
2714	2717	{ PCI_DEVICE(0x1002, 0xab38),
2715	2718	.driver_data = AZX_DRIVER_ATIHDMI_NS \| AZX_DCAPS_PRESET_ATI_HDMI_NS \|
2716	2719	AZX_DCAPS_PM_RUNTIME },

sound/pci/hda/patch_ca0132.c+1−0

@@ -1306,6 +1306,7 @@ static const struct snd_pci_quirk ca0132_quirks[] = { · 1305 unmodified lines
1306	1306	SND_PCI_QUIRK(0x1458, 0xA026, "Gigabyte G1.Sniper Z97", QUIRK_R3DI),
1307	1307	SND_PCI_QUIRK(0x1458, 0xA036, "Gigabyte GA-Z170X-Gaming 7", QUIRK_R3DI),
1308	1308	SND_PCI_QUIRK(0x3842, 0x1038, "EVGA X99 Classified", QUIRK_R3DI),
	1309	+ SND_PCI_QUIRK(0x3842, 0x1055, "EVGA Z390 DARK", QUIRK_R3DI),
1309	1310	SND_PCI_QUIRK(0x1102, 0x0013, "Recon3D", QUIRK_R3D),
1310	1311	SND_PCI_QUIRK(0x1102, 0x0018, "Recon3D", QUIRK_R3D),
1311	1312	SND_PCI_QUIRK(0x1102, 0x0051, "Sound Blaster AE-5", QUIRK_AE5),

sound/pci/hda/patch_realtek.c+2−0

@@ -9404,6 +9404,7 @@ static const struct snd_pci_quirk alc269_fixup_tbl[] = { · 9403 unmodified lines
9404	9404	SND_PCI_QUIRK(0x1043, 0x1e8e, "ASUS Zephyrus G15", ALC289_FIXUP_ASUS_GA401),
9405	9405	SND_PCI_QUIRK(0x1043, 0x1c52, "ASUS Zephyrus G15 2022", ALC289_FIXUP_ASUS_GA401),
9406	9406	SND_PCI_QUIRK(0x1043, 0x1f11, "ASUS Zephyrus G14", ALC289_FIXUP_ASUS_GA401),
	9407	+ SND_PCI_QUIRK(0x1043, 0x1f12, "ASUS UM5302", ALC287_FIXUP_CS35L41_I2C_2),
9407	9408	SND_PCI_QUIRK(0x1043, 0x1f92, "ASUS ROG Flow X16", ALC289_FIXUP_ASUS_GA401),
9408	9409	SND_PCI_QUIRK(0x1043, 0x3030, "ASUS ZN270IE", ALC256_FIXUP_ASUS_AIO_GPIO2),
9409	9410	SND_PCI_QUIRK(0x1043, 0x831a, "ASUS P901", ALC269_FIXUP_STEREO_DMIC),
@@ -9608,6 +9609,7 @@ static const struct snd_pci_quirk alc269_fixup_tbl[] = { · 198 unmodified lines
9608	9609	SND_PCI_QUIRK(0x17aa, 0x511f, "Thinkpad", ALC298_FIXUP_TPT470_DOCK),
9609	9610	SND_PCI_QUIRK(0x17aa, 0x9e54, "LENOVO NB", ALC269_FIXUP_LENOVO_EAPD),
9610	9611	SND_PCI_QUIRK(0x1849, 0x1233, "ASRock NUC Box 1100", ALC233_FIXUP_NO_AUDIO_JACK),
	9612	+ SND_PCI_QUIRK(0x1849, 0xa233, "Positivo Master C6300", ALC269_FIXUP_HEADSET_MIC),
9611	9613	SND_PCI_QUIRK(0x19e5, 0x3204, "Huawei MACH-WX9", ALC256_FIXUP_HUAWEI_MACH_WX9_PINS),
9612	9614	SND_PCI_QUIRK(0x19e5, 0x320f, "Huawei WRT-WX9 ", ALC256_FIXUP_ASUS_MIC_NO_PRESENCE),
9613	9615	SND_PCI_QUIRK(0x1b35, 0x1235, "CZC B20", ALC269_FIXUP_CZC_B20),

sound/soc/codecs/adau1372.c+17−14

@@ -24,7 +24,6 @@ · 23 unmodified lines
24	24	#include "adau-utils.h"
25	25
26	26	struct adau1372 {
27		− struct clk *clk;
28	27	struct regmap *regmap;
29	28	void (switch_mode)(struct device dev);
30	29	bool use_pll;
@@ -206,10 +205,10 @@ static const struct snd_kcontrol_new adau1372_controls[] = { · 175 unmodified lines
206	205	2, 1, 0, adau1372_pga_boost_tlv),
207	206	SOC_SINGLE_TLV("PGA 3 Boost Capture Volume", ADAU1372_REG_PGA_BOOST,
208	207	3, 1, 0, adau1372_pga_boost_tlv),
209		− SOC_SINGLE("PGA 0 Capture Switch", ADAU1372_REG_PGA_CTRL(0), 7, 1, 1),
210		− SOC_SINGLE("PGA 1 Capture Switch", ADAU1372_REG_PGA_CTRL(1), 7, 1, 1),
211		− SOC_SINGLE("PGA 2 Capture Switch", ADAU1372_REG_PGA_CTRL(2), 7, 1, 1),
212		− SOC_SINGLE("PGA 3 Capture Switch", ADAU1372_REG_PGA_CTRL(3), 7, 1, 1),
	208	+ SOC_SINGLE("PGA 0 Capture Switch", ADAU1372_REG_PGA_CTRL(0), 7, 1, 0),
	209	+ SOC_SINGLE("PGA 1 Capture Switch", ADAU1372_REG_PGA_CTRL(1), 7, 1, 0),
	210	+ SOC_SINGLE("PGA 2 Capture Switch", ADAU1372_REG_PGA_CTRL(2), 7, 1, 0),
	211	+ SOC_SINGLE("PGA 3 Capture Switch", ADAU1372_REG_PGA_CTRL(3), 7, 1, 0),
213	212
214	213	SOC_SINGLE_TLV("DAC 0 Playback Volume", ADAU1372_REG_DAC_VOL(0),
215	214	0, 0xff, 1, adau1372_digital_tlv),
@@ -369,10 +368,10 @@ static const struct snd_soc_dapm_widget adau1372_dapm_widgets[] = { · 153 unmodified lines
369	368	SND_SOC_DAPM_SUPPLY("MICBIAS0", ADAU1372_REG_MICBIAS, 4, 0, NULL, 0),
370	369	SND_SOC_DAPM_SUPPLY("MICBIAS1", ADAU1372_REG_MICBIAS, 5, 0, NULL, 0),
371	370
372		− SND_SOC_DAPM_PGA("PGA0", ADAU1372_REG_PGA_CTRL(0), 6, 0, NULL, 0),
373		− SND_SOC_DAPM_PGA("PGA1", ADAU1372_REG_PGA_CTRL(1), 6, 0, NULL, 0),
374		− SND_SOC_DAPM_PGA("PGA2", ADAU1372_REG_PGA_CTRL(2), 6, 0, NULL, 0),
375		− SND_SOC_DAPM_PGA("PGA3", ADAU1372_REG_PGA_CTRL(3), 6, 0, NULL, 0),
	371	+ SND_SOC_DAPM_PGA("PGA0", ADAU1372_REG_PGA_CTRL(0), 6, 1, NULL, 0),
	372	+ SND_SOC_DAPM_PGA("PGA1", ADAU1372_REG_PGA_CTRL(1), 6, 1, NULL, 0),
	373	+ SND_SOC_DAPM_PGA("PGA2", ADAU1372_REG_PGA_CTRL(2), 6, 1, NULL, 0),
	374	+ SND_SOC_DAPM_PGA("PGA3", ADAU1372_REG_PGA_CTRL(3), 6, 1, NULL, 0),
376	375	SND_SOC_DAPM_ADC("ADC0", NULL, ADAU1372_REG_ADC_CTRL2, 0, 0),
377	376	SND_SOC_DAPM_ADC("ADC1", NULL, ADAU1372_REG_ADC_CTRL2, 1, 0),
378	377	SND_SOC_DAPM_ADC("ADC2", NULL, ADAU1372_REG_ADC_CTRL3, 0, 0),
@@ -662,6 +661,7 @@ static int adau1372_hw_params(struct snd_pcm_substream *substream, · 283 unmodified lines
662	661	case 16:
663	662	sai1 = ADAU1372_SAI1_BCLKRATE;
664	663	break;
	664	+ case 24:
665	665	case 32:
666	666	sai1 = 0;
667	667	break;
@@ -699,6 +699,7 @@ static int adau1372_set_tdm_slot(struct snd_soc_dai *dai, unsigned int tx_mask, · 31 unmodified lines
699	699	case 16:
700	700	sai1 = ADAU1372_SAI1_BCLK_TDMC;
701	701	break;
	702	+ case 24:
702	703	case 32:
703	704	sai1 = 0;
704	705	break;
@@ -869,7 +870,9 @@ static const struct snd_soc_dai_ops adau1372_dai_ops = { · 164 unmodified lines
869	870	.startup = adau1372_startup,
870	871	};
871	872
872		−#define ADAU1372_FORMATS (SNDRV_PCM_FMTBIT_S16_LE \| SNDRV_PCM_FMTBIT_S32_LE)
	873	+#define ADAU1372_FORMATS (SNDRV_PCM_FMTBIT_S16_LE \| \
	874	+ SNDRV_PCM_FMTBIT_S24_LE \| \
	875	+ SNDRV_PCM_FMTBIT_S32_LE)
873	876
874	877	static struct snd_soc_dai_driver adau1372_dai_driver = {
875	878	.name = "adau1372",
@@ -924,9 +927,9 @@ int adau1372_probe(struct device dev, struct regmap regmap, · 48 unmodified lines
924	927	if (!adau1372)
925	928	return -ENOMEM;
926	929
927		− adau1372->clk = devm_clk_get(dev, "mclk");
928		− if (IS_ERR(adau1372->clk))
929		− return PTR_ERR(adau1372->clk);
	930	+ adau1372->mclk = devm_clk_get(dev, "mclk");
	931	+ if (IS_ERR(adau1372->mclk))
	932	+ return PTR_ERR(adau1372->mclk);
930	933
931	934	adau1372->pd_gpio = devm_gpiod_get_optional(dev, "powerdown", GPIOD_OUT_HIGH);
932	935	if (IS_ERR(adau1372->pd_gpio))
@@ -946,7 +949,7 @@ int adau1372_probe(struct device dev, struct regmap regmap, · 13 unmodified lines
946	949	* 12.288MHz. Automatically choose a valid configuration from the
947	950	* external clock.
948	951	*/
949		− rate = clk_get_rate(adau1372->clk);
	952	+ rate = clk_get_rate(adau1372->mclk);
950	953
951	954	switch (rate) {
952	955	case 12288000:

sound/usb/card.c+20−9

@@ -742,6 +742,18 @@ get_alias_quirk(struct usb_device *dev, unsigned int id) · 741 unmodified lines
742	742	return NULL;
743	743	}
744	744
	745	+/* register card if we reach to the last interface or to the specified
	746	+ * one given via option
	747	+ */
	748	+static int try_to_register_card(struct snd_usb_audio *chip, int ifnum)
	749	+{
	750	+ if (check_delayed_register_option(chip) == ifnum \|\|
	751	+ chip->last_iface == ifnum \|\|
	752	+ usb_interface_claimed(usb_ifnum_to_if(chip->dev, chip->last_iface)))
	753	+ return snd_card_register(chip->card);
	754	+ return 0;
	755	+}
	756	+
745	757	/*
746	758	* probe the active usb device
747	759	*
@@ -880,15 +892,9 @@ static int usb_audio_probe(struct usb_interface *intf, · 132 unmodified lines
880	892	chip->need_delayed_register = false; /* clear again */
881	893	}
882	894
883		− /* register card if we reach to the last interface or to the specified
884		− * one given via option
885		− */
886		− if (check_delayed_register_option(chip) == ifnum \|\|
887		− usb_interface_claimed(usb_ifnum_to_if(dev, chip->last_iface))) {
888		− err = snd_card_register(chip->card);
889		− if (err < 0)
890		− goto __error;
891		− }
	895	+ err = try_to_register_card(chip, ifnum);
	896	+ if (err < 0)
	897	+ goto __error_no_register;
892	898
893	899	if (chip->quirk_flags & QUIRK_FLAG_SHARE_MEDIA_DEVICE) {
894	900	/* don't want to fail when snd_media_device_create() fails */
@@ -907,6 +913,11 @@ static int usb_audio_probe(struct usb_interface *intf, · 12 unmodified lines
907	913	return 0;
908	914
909	915	__error:
	916	+ /* in the case of error in secondary interface, still try to register */
	917	+ if (chip)
	918	+ try_to_register_card(chip, ifnum);
	919	+
	920	+ __error_no_register:
910	921	if (chip) {
911	922	/* chip->active is inside the chip->card object,
912	923	* decrement before memory is possibly returned.

sound/usb/endpoint.c+2−1

@@ -931,7 +931,8 @@ void snd_usb_endpoint_close(struct snd_usb_audio *chip, · 930 unmodified lines
931	931	usb_audio_dbg(chip, "Closing EP 0x%x (count %d)\n",
932	932	ep->ep_num, ep->opened);
933	933
934		− if (!--ep->iface_ref->opened)
	934	+ if (!--ep->iface_ref->opened &&
	935	+ !(chip->quirk_flags & QUIRK_FLAG_IFACE_SKIP_CLOSE))
935	936	endpoint_set_interface(chip, ep, false);
936	937
937	938	if (!--ep->opened) {

sound/usb/quirks-table.h+4−0

@@ -2049,6 +2049,10 @@ YAMAHA_DEVICE(0x7010, "UB99"), · 2048 unmodified lines
2049	2049	}
2050	2050	}
2051	2051	},
	2052	+{
	2053	+ /* M-Audio Micro */
	2054	+ USB_DEVICE_VENDOR_SPEC(0x0763, 0x201a),
	2055	+},
2052	2056	{
2053	2057	USB_DEVICE_VENDOR_SPEC(0x0763, 0x2030),
2054	2058	.driver_info = (unsigned long) &(const struct snd_usb_audio_quirk) {

sound/usb/quirks.c+6−41

@@ -376,7 +376,8 @@ static int create_auto_midi_quirk(struct snd_usb_audio *chip, · 375 unmodified lines
376	376
377	377	static int create_autodetect_quirk(struct snd_usb_audio *chip,
378	378	struct usb_interface *iface,
379		− struct usb_driver *driver)
	379	+ struct usb_driver *driver,
	380	+ const struct snd_usb_audio_quirk *quirk)
380	381	{
381	382	int err;
382	383
@@ -386,45 +387,6 @@ static int create_autodetect_quirk(struct snd_usb_audio *chip, · 3 unmodified lines
386	387	return err;
387	388	}
388	389
389		−static int create_autodetect_quirks(struct snd_usb_audio *chip,
390		− struct usb_interface *iface,
391		− struct usb_driver *driver,
392		− const struct snd_usb_audio_quirk *quirk)
393		−{
394		− int probed_ifnum = get_iface_desc(iface->altsetting)->bInterfaceNumber;
395		− int ifcount, ifnum, err;
396		−
397		− err = create_autodetect_quirk(chip, iface, driver);
398		− if (err < 0)
399		− return err;
400		−
401		− /*
402		− * ALSA PCM playback/capture devices cannot be registered in two steps,
403		− * so we have to claim the other corresponding interface here.
404		− */
405		− ifcount = chip->dev->actconfig->desc.bNumInterfaces;
406		− for (ifnum = 0; ifnum < ifcount; ifnum++) {
407		− if (ifnum == probed_ifnum \|\| quirk->ifnum >= 0)
408		− continue;
409		− iface = usb_ifnum_to_if(chip->dev, ifnum);
410		− if (!iface \|\|
411		− usb_interface_claimed(iface) \|\|
412		− get_iface_desc(iface->altsetting)->bInterfaceClass !=
413		− USB_CLASS_VENDOR_SPEC)
414		− continue;
415		−
416		− err = create_autodetect_quirk(chip, iface, driver);
417		− if (err >= 0) {
418		− err = usb_driver_claim_interface(driver, iface,
419		− USB_AUDIO_IFACE_UNUSED);
420		− if (err < 0)
421		− return err;
422		− }
423		− }
424		−
425		− return 0;
426		−}
427		−
428	390	/*
429	391	* Create a stream for an Edirol UA-700/UA-25/UA-4FX interface.
430	392	* The only way to detect the sample rate is by looking at wMaxPacketSize.
@@ -554,7 +516,7 @@ int snd_usb_create_quirk(struct snd_usb_audio *chip, · 123 unmodified lines
554	516	static const quirk_func_t quirk_funcs[] = {
555	517	[QUIRK_IGNORE_INTERFACE] = ignore_interface_quirk,
556	518	[QUIRK_COMPOSITE] = create_composite_quirk,
557		− [QUIRK_AUTODETECT] = create_autodetect_quirks,
	519	+ [QUIRK_AUTODETECT] = create_autodetect_quirk,
558	520	[QUIRK_MIDI_STANDARD_INTERFACE] = create_any_midi_quirk,
559	521	[QUIRK_MIDI_FIXED_ENDPOINT] = create_any_midi_quirk,
560	522	[QUIRK_MIDI_YAMAHA] = create_any_midi_quirk,
@@ -1913,6 +1875,7 @@ u64 snd_usb_interface_dsd_format_quirks(struct snd_usb_audio *chip, · 1352 unmodified lines
1913	1875	/* XMOS based USB DACs */
1914	1876	switch (chip->usb_id) {
1915	1877	case USB_ID(0x1511, 0x0037): /* AURALiC VEGA */
	1878	+ case USB_ID(0x21ed, 0xd75a): /* Accuphase DAC-60 option card */
1916	1879	case USB_ID(0x2522, 0x0012): /* LH Labs VI DAC Infinity */
1917	1880	case USB_ID(0x2772, 0x0230): /* Pro-Ject Pre Box S2 Digital */
1918	1881	if (fp->altsetting == 2)
@@ -2185,6 +2148,8 @@ static const struct usb_audio_quirk_flags_table quirk_flags_table[] = { · 266 unmodified lines
2185	2148	QUIRK_FLAG_GENERIC_IMPLICIT_FB),
2186	2149	DEVICE_FLG(0x2b53, 0x0031, /* Fiero SC-01 (firmware v1.1.0) */
2187	2150	QUIRK_FLAG_GENERIC_IMPLICIT_FB),
	2151	+ DEVICE_FLG(0x0525, 0xa4ad, /* Hamedal C20 usb camero */
	2152	+ QUIRK_FLAG_IFACE_SKIP_CLOSE),
2188	2153
2189	2154	/* Vendor matches */
2190	2155	VENDOR_FLG(0x045e, /* MS Lifecam */

sound/usb/usbaudio.h+3−0

@@ -170,6 +170,8 @@ extern bool snd_usb_skip_validation; · 169 unmodified lines
170	170	* Apply the generic implicit feedback sync mode (same as implicit_fb=1 option)
171	171	* QUIRK_FLAG_SKIP_IMPLICIT_FB
172	172	* Don't apply implicit feedback sync mode
	173	+ * QUIRK_FLAG_IFACE_SKIP_CLOSE
	174	+ * Don't closed interface during setting sample rate
173	175	*/
174	176
175	177	#define QUIRK_FLAG_GET_SAMPLE_RATE (1U << 0)
@@ -191,5 +193,6 @@ extern bool snd_usb_skip_validation; · 15 unmodified lines
191	193	#define QUIRK_FLAG_SET_IFACE_FIRST (1U << 16)
192	194	#define QUIRK_FLAG_GENERIC_IMPLICIT_FB (1U << 17)
193	195	#define QUIRK_FLAG_SKIP_IMPLICIT_FB (1U << 18)
	196	+#define QUIRK_FLAG_IFACE_SKIP_CLOSE (1U << 19)
194	197
195	198	#endif /* __USBAUDIO_H */

tools/bpf/bpftool/common.c+3−0

@@ -300,6 +300,9 @@ int do_pin_any(int argc, char *argv, int (get_fd)(int , char **)) · 299 unmodified lines
300	300	int err;
301	301	int fd;
302	302
	303	+ if (!REQ_ARGS(3))
	304	+ return -EINVAL;
	305	+
303	306	fd = get_fd(&argc, &argv);
304	307	if (fd < 0)
305	308	return fd;

tools/include/uapi/linux/in.h+1−0

@@ -20,6 +20,7 @@ · 19 unmodified lines
20	20	#define _UAPI_LINUX_IN_H
21	21
22	22	#include <linux/types.h>
	23	+#include <linux/stddef.h>
23	24	#include <linux/libc-compat.h>
24	25	#include <linux/socket.h>
25	26

tools/include/uapi/linux/stddef.h+47−0

@@ -0,0 +1,47 @@
	1	+/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
	2	+#ifndef _LINUX_STDDEF_H
	3	+#define _LINUX_STDDEF_H
	4	+
	5	+
	6	+
	7	+#ifndef __always_inline
	8	+#define __always_inline __inline__
	9	+#endif
	10	+
	11	+/**
	12	+ * __struct_group() - Create a mirrored named and anonyomous struct
	13	+ *
	14	+ * @TAG: The tag name for the named sub-struct (usually empty)
	15	+ * @NAME: The identifier name of the mirrored sub-struct
	16	+ * @ATTRS: Any struct attributes (usually empty)
	17	+ * @MEMBERS: The member declarations for the mirrored structs
	18	+ *
	19	+ * Used to create an anonymous union of two structs with identical layout
	20	+ * and size: one anonymous and one named. The former's members can be used
	21	+ * normally without sub-struct naming, and the latter can be used to
	22	+ * reason about the start, end, and size of the group of struct members.
	23	+ * The named struct can also be explicitly tagged for layer reuse, as well
	24	+ * as both having struct attributes appended.
	25	+ */
	26	+#define __struct_group(TAG, NAME, ATTRS, MEMBERS...) \
	27	+ union { \
	28	+ struct { MEMBERS } ATTRS; \
	29	+ struct TAG { MEMBERS } ATTRS NAME; \
	30	+ }
	31	+
	32	+/**
	33	+ * __DECLARE_FLEX_ARRAY() - Declare a flexible array usable in a union
	34	+ *
	35	+ * @TYPE: The type of each flexible array element
	36	+ * @NAME: The name of the flexible array member
	37	+ *
	38	+ * In order to have a flexible array member in a union or alone in a
	39	+ * struct, it needs to be wrapped in an anonymous struct with at least 1
	40	+ * named member, but that member can be empty.
	41	+ */
	42	+#define __DECLARE_FLEX_ARRAY(TYPE, NAME) \
	43	+ struct { \
	44	+ struct { } __empty_ ## NAME; \
	45	+ TYPE NAME[]; \
	46	+ }
	47	+#endif

tools/kvm/kvm_stat/kvm_stat+83−15

@@ -41,11 +41,14 @@ VMX_EXIT_REASONS = { · 40 unmodified lines
41	41	'EXCEPTION_NMI': 0,
42	42	'EXTERNAL_INTERRUPT': 1,
43	43	'TRIPLE_FAULT': 2,
44		− 'PENDING_INTERRUPT': 7,
	44	+ 'INIT_SIGNAL': 3,
	45	+ 'SIPI_SIGNAL': 4,
	46	+ 'INTERRUPT_WINDOW': 7,
45	47	'NMI_WINDOW': 8,
46	48	'TASK_SWITCH': 9,
47	49	'CPUID': 10,
48	50	'HLT': 12,
	51	+ 'INVD': 13,
49	52	'INVLPG': 14,
50	53	'RDPMC': 15,
51	54	'RDTSC': 16,
@@ -65,26 +68,48 @@ VMX_EXIT_REASONS = { · 13 unmodified lines
65	68	'MSR_READ': 31,
66	69	'MSR_WRITE': 32,
67	70	'INVALID_STATE': 33,
	71	+ 'MSR_LOAD_FAIL': 34,
68	72	'MWAIT_INSTRUCTION': 36,
	73	+ 'MONITOR_TRAP_FLAG': 37,
69	74	'MONITOR_INSTRUCTION': 39,
70	75	'PAUSE_INSTRUCTION': 40,
71	76	'MCE_DURING_VMENTRY': 41,
72	77	'TPR_BELOW_THRESHOLD': 43,
73	78	'APIC_ACCESS': 44,
	79	+ 'EOI_INDUCED': 45,
	80	+ 'GDTR_IDTR': 46,
	81	+ 'LDTR_TR': 47,
74	82	'EPT_VIOLATION': 48,
75	83	'EPT_MISCONFIG': 49,
	84	+ 'INVEPT': 50,
	85	+ 'RDTSCP': 51,
	86	+ 'PREEMPTION_TIMER': 52,
	87	+ 'INVVPID': 53,
76	88	'WBINVD': 54,
77	89	'XSETBV': 55,
78	90	'APIC_WRITE': 56,
	91	+ 'RDRAND': 57,
79	92	'INVPCID': 58,
	93	+ 'VMFUNC': 59,
	94	+ 'ENCLS': 60,
	95	+ 'RDSEED': 61,
	96	+ 'PML_FULL': 62,
	97	+ 'XSAVES': 63,
	98	+ 'XRSTORS': 64,
	99	+ 'UMWAIT': 67,
	100	+ 'TPAUSE': 68,
	101	+ 'BUS_LOCK': 74,
	102	+ 'NOTIFY': 75,
80	103	}
81	104
82	105	SVM_EXIT_REASONS = {
83	106	'READ_CR0': 0x000,
	107	+ 'READ_CR2': 0x002,
84	108	'READ_CR3': 0x003,
85	109	'READ_CR4': 0x004,
86	110	'READ_CR8': 0x008,
87	111	'WRITE_CR0': 0x010,
	112	+ 'WRITE_CR2': 0x012,
88	113	'WRITE_CR3': 0x013,
89	114	'WRITE_CR4': 0x014,
90	115	'WRITE_CR8': 0x018,
@@ -105,6 +130,7 @@ SVM_EXIT_REASONS = { · 14 unmodified lines
105	130	'WRITE_DR6': 0x036,
106	131	'WRITE_DR7': 0x037,
107	132	'EXCP_BASE': 0x040,
	133	+ 'LAST_EXCP': 0x05f,
108	134	'INTR': 0x060,
109	135	'NMI': 0x061,
110	136	'SMI': 0x062,
@@ -151,21 +177,45 @@ SVM_EXIT_REASONS = { · 40 unmodified lines
151	177	'MWAIT': 0x08b,
152	178	'MWAIT_COND': 0x08c,
153	179	'XSETBV': 0x08d,
	180	+ 'RDPRU': 0x08e,
	181	+ 'EFER_WRITE_TRAP': 0x08f,
	182	+ 'CR0_WRITE_TRAP': 0x090,
	183	+ 'CR1_WRITE_TRAP': 0x091,
	184	+ 'CR2_WRITE_TRAP': 0x092,
	185	+ 'CR3_WRITE_TRAP': 0x093,
	186	+ 'CR4_WRITE_TRAP': 0x094,
	187	+ 'CR5_WRITE_TRAP': 0x095,
	188	+ 'CR6_WRITE_TRAP': 0x096,
	189	+ 'CR7_WRITE_TRAP': 0x097,
	190	+ 'CR8_WRITE_TRAP': 0x098,
	191	+ 'CR9_WRITE_TRAP': 0x099,
	192	+ 'CR10_WRITE_TRAP': 0x09a,
	193	+ 'CR11_WRITE_TRAP': 0x09b,
	194	+ 'CR12_WRITE_TRAP': 0x09c,
	195	+ 'CR13_WRITE_TRAP': 0x09d,
	196	+ 'CR14_WRITE_TRAP': 0x09e,
	197	+ 'CR15_WRITE_TRAP': 0x09f,
	198	+ 'INVPCID': 0x0a2,
154	199	'NPF': 0x400,
	200	+ 'AVIC_INCOMPLETE_IPI': 0x401,
	201	+ 'AVIC_UNACCELERATED_ACCESS': 0x402,
	202	+ 'VMGEXIT': 0x403,
155	203	}
156	204
157		−# EC definition of HSR (from arch/arm64/include/asm/kvm_arm.h)
	205	+# EC definition of HSR (from arch/arm64/include/asm/esr.h)
158	206	AARCH64_EXIT_REASONS = {
159	207	'UNKNOWN': 0x00,
160		− 'WFI': 0x01,
	208	+ 'WFx': 0x01,
161	209	'CP15_32': 0x03,
162	210	'CP15_64': 0x04,
163	211	'CP14_MR': 0x05,
164	212	'CP14_LS': 0x06,
165	213	'FP_ASIMD': 0x07,
166	214	'CP10_ID': 0x08,
	215	+ 'PAC': 0x09,
167	216	'CP14_64': 0x0C,
168		− 'ILL_ISS': 0x0E,
	217	+ 'BTI': 0x0D,
	218	+ 'ILL': 0x0E,
169	219	'SVC32': 0x11,
170	220	'HVC32': 0x12,
171	221	'SMC32': 0x13,
@@ -173,21 +223,26 @@ AARCH64_EXIT_REASONS = { · 1 unmodified line
173	223	'HVC64': 0x16,
174	224	'SMC64': 0x17,
175	225	'SYS64': 0x18,
176		− 'IABT': 0x20,
177		− 'IABT_HYP': 0x21,
	226	+ 'SVE': 0x19,
	227	+ 'ERET': 0x1A,
	228	+ 'FPAC': 0x1C,
	229	+ 'SME': 0x1D,
	230	+ 'IMP_DEF': 0x1F,
	231	+ 'IABT_LOW': 0x20,
	232	+ 'IABT_CUR': 0x21,
178	233	'PC_ALIGN': 0x22,
179		− 'DABT': 0x24,
180		− 'DABT_HYP': 0x25,
	234	+ 'DABT_LOW': 0x24,
	235	+ 'DABT_CUR': 0x25,
181	236	'SP_ALIGN': 0x26,
182	237	'FP_EXC32': 0x28,
183	238	'FP_EXC64': 0x2C,
184	239	'SERROR': 0x2F,
185		− 'BREAKPT': 0x30,
186		− 'BREAKPT_HYP': 0x31,
187		− 'SOFTSTP': 0x32,
188		− 'SOFTSTP_HYP': 0x33,
189		− 'WATCHPT': 0x34,
190		− 'WATCHPT_HYP': 0x35,
	240	+ 'BREAKPT_LOW': 0x30,
	241	+ 'BREAKPT_CUR': 0x31,
	242	+ 'SOFTSTP_LOW': 0x32,
	243	+ 'SOFTSTP_CUR': 0x33,
	244	+ 'WATCHPT_LOW': 0x34,
	245	+ 'WATCHPT_CUR': 0x35,
191	246	'BKPT32': 0x38,
192	247	'VECTOR32': 0x3A,
193	248	'BRK64': 0x3C,
@@ -220,6 +275,19 @@ USERSPACE_EXIT_REASONS = { · 26 unmodified lines
220	275	'S390_TSCH': 22,
221	276	'EPR': 23,
222	277	'SYSTEM_EVENT': 24,
	278	+ 'S390_STSI': 25,
	279	+ 'IOAPIC_EOI': 26,
	280	+ 'HYPERV': 27,
	281	+ 'ARM_NISV': 28,
	282	+ 'X86_RDMSR': 29,
	283	+ 'X86_WRMSR': 30,
	284	+ 'DIRTY_RING_FULL': 31,
	285	+ 'AP_RESET_HOLD': 32,
	286	+ 'X86_BUS_LOCK': 33,
	287	+ 'XEN': 34,
	288	+ 'RISCV_SBI': 35,
	289	+ 'RISCV_CSR': 36,
	290	+ 'NOTIFY': 37,
223	291	}
224	292
225	293	IOCTL_NUMBERS = {
@@ -1756,7 +1824,7 @@ def assign_globals(): · 1530 unmodified lines
1756	1824
1757	1825	debugfs = ''
1758	1826	for line in open('/proc/mounts'):
1759		− if line.split(' ')[0] == 'debugfs':
	1827	+ if line.split(' ')[2] == 'debugfs':
1760	1828	debugfs = line.split(' ')[1]
1761	1829	break
1762	1830	if debugfs == '':

tools/perf/.gitignore+1−0

@@ -4,6 +4,7 @@ PERF-GUI-VARS · 3 unmodified lines
4	4	PERF-VERSION-FILE
5	5	FEATURE-DUMP
6	6	perf
	7	+!include/perf/
7	8	perf-read-vdso32
8	9	perf-read-vdsox32
9	10	perf-help

tools/perf/tests/shell/test_brstack.sh+4−1

@@ -13,7 +13,10 @@ fi · 12 unmodified lines
13	13
14	14	# skip the test if the hardware doesn't support branch stack sampling
15	15	# and if the architecture doesn't support filter types: any,save_type,u
16		−perf record -b -o- -B --branch-filter any,save_type,u true > /dev/null 2>&1 \|\| exit 2
	16	+if ! perf record -o- --no-buildid --branch-filter any,save_type,u -- true > /dev/null 2>&1 ; then
	17	+ echo "skip: system doesn't support filter types: any,save_type,u"
	18	+ exit 2
	19	+fi
17	20
18	21	TMPDIR=$(mktemp -d /tmp/__perf_test.program.XXXXX)
19	22

tools/perf/util/parse-branch-options.c+3−1

@@ -102,8 +102,10 @@ parse_branch_stack(const struct option opt, const char str, int unset) · 101 unmodified lines
102	102	/*
103	103	* cannot set it twice, -b + --branch-filter for instance
104	104	*/
105		− if (*mode)
	105	+ if (*mode) {
	106	+ pr_err("Error: Can't use --branch-any (-b) with --branch-filter (-j).\n");
106	107	return -1;
	108	+ }
107	109
108	110	return parse_branch_str(str, mode);
109	111	}

tools/perf/util/stat-display.c+4−2

@@ -273,7 +273,7 @@ static void new_line_csv(struct perf_stat_config config, void ctx) · 272 unmodified lines
273	273
274	274	fputc('\n', os->fh);
275	275	if (os->prefix)
276		− fprintf(os->fh, "%s%s", os->prefix, config->csv_sep);
	276	+ fprintf(os->fh, "%s", os->prefix);
277	277	aggr_printout(config, os->evsel, os->id, os->nr);
278	278	for (i = 0; i < os->nfields; i++)
279	279	fputs(config->csv_sep, os->fh);
@@ -559,7 +559,7 @@ static void printout(struct perf_stat_config *config, struct aggr_cpu_id id, int · 279 unmodified lines
559	559	[AGGR_CORE] = 2,
560	560	[AGGR_THREAD] = 1,
561	561	[AGGR_UNSET] = 0,
562		− [AGGR_NODE] = 0,
	562	+ [AGGR_NODE] = 1,
563	563	};
564	564
565	565	pm = config->metric_only ? print_metric_only_csv : print_metric_csv;
@@ -1124,6 +1124,7 @@ static int aggr_header_lens[] = { · 558 unmodified lines
1124	1124	[AGGR_SOCKET] = 12,
1125	1125	[AGGR_NONE] = 6,
1126	1126	[AGGR_THREAD] = 24,
	1127	+ [AGGR_NODE] = 6,
1127	1128	[AGGR_GLOBAL] = 0,
1128	1129	};
1129	1130
@@ -1133,6 +1134,7 @@ static const char *aggr_header_csv[] = { · 3 unmodified lines
1133	1134	[AGGR_SOCKET] = "socket,cpus",
1134	1135	[AGGR_NONE] = "cpu,",
1135	1136	[AGGR_THREAD] = "comm-pid,",
	1137	+ [AGGR_NODE] = "node,",
1136	1138	[AGGR_GLOBAL] = ""
1137	1139	};
1138	1140

tools/testing/radix-tree/.gitignore+1−0

@@ -1,4 +1,5 @@
1	1	# SPDX-License-Identifier: GPL-2.0-only
	2	+generated/bit-length.h
2	3	generated/map-shift.h
3	4	idr.c
4	5	idr-test

tools/testing/radix-tree/Makefile+16−3

@@ -18,9 +18,14 @@ endif · 17 unmodified lines
18	18	ifeq ($(BUILD), 32)
19	19	CFLAGS += -m32
20	20	LDFLAGS += -m32
	21	+LONG_BIT := 32
21	22	endif
22	23
23		−targets: generated/map-shift.h $(TARGETS)
	24	+ifndef LONG_BIT
	25	+LONG_BIT := $(shell getconf LONG_BIT)
	26	+endif
	27	+
	28	+targets: generated/map-shift.h generated/bit-length.h $(TARGETS)
24	29
25	30	main: $(OFILES)
26	31
@@ -34,11 +39,11 @@ maple: $(CORE_OFILES) · 7 unmodified lines
34	39	multiorder: multiorder.o $(CORE_OFILES)
35	40
36	41	clean:
37		− $(RM) $(TARGETS) *.o radix-tree.c idr.c generated/map-shift.h
	42	+ $(RM) $(TARGETS) *.o radix-tree.c idr.c generated/map-shift.h generated/bit-length.h
38	43
39	44	vpath %.c ../../lib
40	45
41		−$(OFILES): Makefile .h /*.h generated/map-shift.h \
	46	+$(OFILES): Makefile .h /*.h generated/map-shift.h generated/bit-length.h \
42	47	../../include/linux/*.h \
43	48	../../include/asm/*.h \
44	49	../../../include/linux/xarray.h \
@@ -61,3 +66,11 @@ generated/map-shift.h: · 16 unmodified lines
61	66	echo "#define XA_CHUNK_SHIFT $(SHIFT)" > \
62	67	generated/map-shift.h; \
63	68	fi
	69	+
	70	+generated/bit-length.h: FORCE
	71	+ @if ! grep -qws CONFIG_$(LONG_BIT)BIT generated/bit-length.h; then \
	72	+ echo "Generating $@"; \
	73	+ echo "#define CONFIG_$(LONG_BIT)BIT 1" > $@; \
	74	+ fi
	75	+
	76	+FORCE: ;

tools/testing/radix-tree/generated/autoconf.h+1−1

@@ -1,2 +1,2 @@
	1	+#include "bit-length.h"
1	2	#define CONFIG_XARRAY_MULTI 1
2		−#define CONFIG_64BIT 1

tools/testing/radix-tree/linux.c+4−0

@@ -129,6 +129,10 @@ void kmem_cache_free_bulk(struct kmem_cache cachep, size_t size, void *list) · 128 unmodified lines
129	129	pthread_mutex_unlock(&cachep->lock);
130	130	}
131	131
	132	+void kmem_cache_shrink(struct kmem_cache *cachep)
	133	+{
	134	+}
	135	+
132	136	int kmem_cache_alloc_bulk(struct kmem_cache *cachep, gfp_t gfp, size_t size,
133	137	void **p)
134	138	{

tools/testing/radix-tree/maple.c+35770−0

@@ -2,11 +2,17 @@ · 1 unmodified line
2	2	/*
3	3	* maple_tree.c: Userspace shim for maple tree test-suite
4	4	* Copyright (c) 2018 Liam R. Howlett <Liam.Howlett@Oracle.com>
	5	+ *
	6	+ * Any tests that require internal knowledge of the tree or threads and other
	7	+ * difficult to handle in kernel tests.
5	8	*/
6	9
7	10	#define CONFIG_DEBUG_MAPLE_TREE
8	11	#define CONFIG_MAPLE_SEARCH
	12	+#define MAPLE_32BIT (MAPLE_NODE_SLOTS > 31)
9	13	#include "test.h"
	14	+#include <stdlib.h>
	15	+#include <time.h>
10	16
11	17	#define module_init(x)
12	18	#define module_exit(x)
@@ -18,6 +24,35717 @@ · 5 unmodified lines
18	24	#undef CONFIG_DEBUG_MAPLE_TREE
19	25	#include "../../../lib/test_maple_tree.c"
20	26
	27	+#define RCU_RANGE_COUNT 1000
	28	+#define RCU_MT_BUG_ON(test, y) {if (y) { test->stop = true; } MT_BUG_ON(test->mt, y); }
	29	+
	30	+struct rcu_test_struct2 {
	31	+ struct maple_tree *mt;
	32	+
	33	+ bool start;
	34	+ bool stop;
	35	+ unsigned int thread_count;
	36	+
	37	+ unsigned int seen_toggle;
	38	+ unsigned int seen_added;
	39	+ unsigned int seen_modified;
	40	+ unsigned int seen_deleted;
	41	+ int pause;
	42	+
	43	+ unsigned long index[RCU_RANGE_COUNT];
	44	+ unsigned long last[RCU_RANGE_COUNT];
	45	+};
	46	+
	47	+struct rcu_reader_struct {
	48	+ unsigned int id;
	49	+ int mod;
	50	+ int del;
	51	+ int flip;
	52	+ int add;
	53	+ int next;
	54	+ struct rcu_test_struct2 *test;
	55	+};
	56	+
	57	+/*
	58	+ * check_new_node() - Check the creation of new nodes and error path
	59	+ * verification.
	60	+ */
	61	+static noinline void check_new_node(struct maple_tree *mt)
	62	+{
	63	+
	64	+ struct maple_node mn, mn2, *mn3;
	65	+ struct maple_alloc *smn;
	66	+ struct maple_node *nodes[100];
	67	+ int i, j, total;
	68	+
	69	+ MA_STATE(mas, mt, 0, 0);
	70	+
	71	+ /* Try allocating 3 nodes */
	72	+ mtree_lock(mt);
	73	+ mt_set_non_kernel(0);
	74	+ /* request 3 nodes to be allocated. */
	75	+ mas_node_count(&mas, 3);
	76	+ /* Allocation request of 3. */
	77	+ MT_BUG_ON(mt, mas_alloc_req(&mas) != 3);
	78	+ /* Allocate failed. */
	79	+ MT_BUG_ON(mt, mas.node != MA_ERROR(-ENOMEM));
	80	+ MT_BUG_ON(mt, !mas_nomem(&mas, GFP_KERNEL));
	81	+
	82	+ MT_BUG_ON(mt, mas_allocated(&mas) != 3);
	83	+ mn = mas_pop_node(&mas);
	84	+ MT_BUG_ON(mt, not_empty(mn));
	85	+ MT_BUG_ON(mt, mn == NULL);
	86	+ MT_BUG_ON(mt, mas.alloc == NULL);
	87	+ MT_BUG_ON(mt, mas.alloc->slot[0] == NULL);
	88	+ mas_push_node(&mas, mn);
	89	+ mas_nomem(&mas, GFP_KERNEL); /* free */
	90	+ mtree_unlock(mt);
	91	+
	92	+
	93	+ /* Try allocating 1 node, then 2 more */
	94	+ mtree_lock(mt);
	95	+ /* Set allocation request to 1. */
	96	+ mas_set_alloc_req(&mas, 1);
	97	+ /* Check Allocation request of 1. */
	98	+ MT_BUG_ON(mt, mas_alloc_req(&mas) != 1);
	99	+ mas_set_err(&mas, -ENOMEM);
	100	+ /* Validate allocation request. */
	101	+ MT_BUG_ON(mt, !mas_nomem(&mas, GFP_KERNEL));
	102	+ /* Eat the requested node. */
	103	+ mn = mas_pop_node(&mas);
	104	+ MT_BUG_ON(mt, not_empty(mn));
	105	+ MT_BUG_ON(mt, mn == NULL);
	106	+ MT_BUG_ON(mt, mn->slot[0] != NULL);
	107	+ MT_BUG_ON(mt, mn->slot[1] != NULL);
	108	+ MT_BUG_ON(mt, mas_allocated(&mas) != 0);
	109	+
	110	+ ma_free_rcu(mn);
	111	+ mas.node = MAS_START;
	112	+ mas_nomem(&mas, GFP_KERNEL);
	113	+ /* Allocate 3 nodes, will fail. */
	114	+ mas_node_count(&mas, 3);
	115	+ /* Drop the lock and allocate 3 nodes. */
	116	+ mas_nomem(&mas, GFP_KERNEL);
	117	+ /* Ensure 3 are allocated. */
	118	+ MT_BUG_ON(mt, mas_allocated(&mas) != 3);
	119	+ /* Allocation request of 0. */
	120	+ MT_BUG_ON(mt, mas_alloc_req(&mas) != 0);
	121	+
	122	+ MT_BUG_ON(mt, mas.alloc == NULL);
	123	+ MT_BUG_ON(mt, mas.alloc->slot[0] == NULL);
	124	+ MT_BUG_ON(mt, mas.alloc->slot[1] == NULL);
	125	+ /* Ensure we counted 3. */
	126	+ MT_BUG_ON(mt, mas_allocated(&mas) != 3);
	127	+ /* Free. */
	128	+ mas_nomem(&mas, GFP_KERNEL);
	129	+
	130	+ /* Set allocation request to 1. */
	131	+ mas_set_alloc_req(&mas, 1);
	132	+ MT_BUG_ON(mt, mas_alloc_req(&mas) != 1);
	133	+ mas_set_err(&mas, -ENOMEM);
	134	+ /* Validate allocation request. */
	135	+ MT_BUG_ON(mt, !mas_nomem(&mas, GFP_KERNEL));
	136	+ MT_BUG_ON(mt, mas_allocated(&mas) != 1);
	137	+ /* Check the node is only one node. */
	138	+ mn = mas_pop_node(&mas);
	139	+ MT_BUG_ON(mt, not_empty(mn));
	140	+ MT_BUG_ON(mt, mas_allocated(&mas) != 0);
	141	+ MT_BUG_ON(mt, mn == NULL);
	142	+ MT_BUG_ON(mt, mn->slot[0] != NULL);
	143	+ MT_BUG_ON(mt, mn->slot[1] != NULL);
	144	+ MT_BUG_ON(mt, mas_allocated(&mas) != 0);
	145	+ mas_push_node(&mas, mn);
	146	+ MT_BUG_ON(mt, mas_allocated(&mas) != 1);
	147	+ MT_BUG_ON(mt, mas.alloc->node_count);
	148	+
	149	+ mas_set_alloc_req(&mas, 2); /* request 2 more. */
	150	+ MT_BUG_ON(mt, mas_alloc_req(&mas) != 2);
	151	+ mas_set_err(&mas, -ENOMEM);
	152	+ MT_BUG_ON(mt, !mas_nomem(&mas, GFP_KERNEL));
	153	+ MT_BUG_ON(mt, mas_allocated(&mas) != 3);
	154	+ MT_BUG_ON(mt, mas.alloc == NULL);
	155	+ MT_BUG_ON(mt, mas.alloc->slot[0] == NULL);
	156	+ MT_BUG_ON(mt, mas.alloc->slot[1] == NULL);
	157	+ for (i = 2; i >= 0; i--) {
	158	+ mn = mas_pop_node(&mas);
	159	+ MT_BUG_ON(mt, mas_allocated(&mas) != i);
	160	+ MT_BUG_ON(mt, !mn);
	161	+ MT_BUG_ON(mt, not_empty(mn));
	162	+ ma_free_rcu(mn);
	163	+ }
	164	+
	165	+ total = 64;
	166	+ mas_set_alloc_req(&mas, total); /* request 2 more. */
	167	+ MT_BUG_ON(mt, mas_alloc_req(&mas) != total);
	168	+ mas_set_err(&mas, -ENOMEM);
	169	+ MT_BUG_ON(mt, !mas_nomem(&mas, GFP_KERNEL));
	170	+ for (i = total; i > 0; i--) {
	171	+ unsigned int e = 0; /* expected node_count */
	172	+
	173	+ if (!MAPLE_32BIT) {
	174	+ if (i >= 35)
	175	+ e = i - 35;
	176	+ else if (i >= 5)
	177	+ e = i - 5;
	178	+ else if (i >= 2)
	179	+ e = i - 2;
	180	+ } else {
	181	+ if (i >= 4)
	182	+ e = i - 4;
	183	+ else if (i == 3)
	184	+ e = i - 2;
	185	+ else
	186	+ e = 0;
	187	+ }
	188	+
	189	+ MT_BUG_ON(mt, mas.alloc->node_count != e);
	190	+ mn = mas_pop_node(&mas);
	191	+ MT_BUG_ON(mt, not_empty(mn));
	192	+ MT_BUG_ON(mt, mas_allocated(&mas) != i - 1);
	193	+ MT_BUG_ON(mt, !mn);
	194	+ ma_free_rcu(mn);
	195	+ }
	196	+
	197	+ total = 100;
	198	+ for (i = 1; i < total; i++) {
	199	+ mas_set_alloc_req(&mas, i);
	200	+ mas_set_err(&mas, -ENOMEM);
	201	+ MT_BUG_ON(mt, !mas_nomem(&mas, GFP_KERNEL));
	202	+ for (j = i; j > 0; j--) {
	203	+ mn = mas_pop_node(&mas);
	204	+ MT_BUG_ON(mt, mas_allocated(&mas) != j - 1);
	205	+ MT_BUG_ON(mt, !mn);
	206	+ MT_BUG_ON(mt, not_empty(mn));
	207	+ mas_push_node(&mas, mn);
	208	+ MT_BUG_ON(mt, mas_allocated(&mas) != j);
	209	+ mn = mas_pop_node(&mas);
	210	+ MT_BUG_ON(mt, not_empty(mn));
	211	+ MT_BUG_ON(mt, mas_allocated(&mas) != j - 1);
	212	+ ma_free_rcu(mn);
	213	+ }
	214	+ MT_BUG_ON(mt, mas_allocated(&mas) != 0);
	215	+
	216	+ mas_set_alloc_req(&mas, i);
	217	+ mas_set_err(&mas, -ENOMEM);
	218	+ MT_BUG_ON(mt, !mas_nomem(&mas, GFP_KERNEL));
	219	+ for (j = 0; j <= i/2; j++) {
	220	+ MT_BUG_ON(mt, mas_allocated(&mas) != i - j);
	221	+ nodes[j] = mas_pop_node(&mas);
	222	+ MT_BUG_ON(mt, mas_allocated(&mas) != i - j - 1);
	223	+ }
	224	+
	225	+ while (j) {
	226	+ j--;
	227	+ mas_push_node(&mas, nodes[j]);
	228	+ MT_BUG_ON(mt, mas_allocated(&mas) != i - j);
	229	+ }
	230	+ MT_BUG_ON(mt, mas_allocated(&mas) != i);
	231	+ for (j = 0; j <= i/2; j++) {
	232	+ MT_BUG_ON(mt, mas_allocated(&mas) != i - j);
	233	+ mn = mas_pop_node(&mas);
	234	+ MT_BUG_ON(mt, not_empty(mn));
	235	+ ma_free_rcu(mn);
	236	+ MT_BUG_ON(mt, mas_allocated(&mas) != i - j - 1);
	237	+ }
	238	+ MT_BUG_ON(mt, mas_nomem(&mas, GFP_KERNEL));
	239	+
	240	+ }
	241	+
	242	+ /* Set allocation request. */
	243	+ total = 500;
	244	+ mas_node_count(&mas, total);
	245	+ /* Drop the lock and allocate the nodes. */
	246	+ mas_nomem(&mas, GFP_KERNEL);
	247	+ MT_BUG_ON(mt, !mas.alloc);
	248	+ i = 1;
	249	+ smn = mas.alloc;
	250	+ while (i < total) {
	251	+ for (j = 0; j < MAPLE_ALLOC_SLOTS; j++) {
	252	+ i++;
	253	+ MT_BUG_ON(mt, !smn->slot[j]);
	254	+ if (i == total)
	255	+ break;
	256	+ }
	257	+ smn = smn->slot[0]; /* next. */
	258	+ }
	259	+ MT_BUG_ON(mt, mas_allocated(&mas) != total);
	260	+ mas_nomem(&mas, GFP_KERNEL); /* Free. */
	261	+
	262	+ MT_BUG_ON(mt, mas_allocated(&mas) != 0);
	263	+ for (i = 1; i < 128; i++) {
	264	+ mas_node_count(&mas, i); /* Request */
	265	+ mas_nomem(&mas, GFP_KERNEL); /* Fill request */
	266	+ MT_BUG_ON(mt, mas_allocated(&mas) != i); /* check request filled */
	267	+ for (j = i; j > 0; j--) { /Free the requests /
	268	+ mn = mas_pop_node(&mas); /* get the next node. */
	269	+ MT_BUG_ON(mt, mn == NULL);
	270	+ MT_BUG_ON(mt, not_empty(mn));
	271	+ ma_free_rcu(mn);
	272	+ }
	273	+ MT_BUG_ON(mt, mas_allocated(&mas) != 0);
	274	+ }
	275	+
	276	+ for (i = 1; i < MAPLE_NODE_MASK + 1; i++) {
	277	+ MA_STATE(mas2, mt, 0, 0);
	278	+ mas_node_count(&mas, i); /* Request */
	279	+ mas_nomem(&mas, GFP_KERNEL); /* Fill request */
	280	+ MT_BUG_ON(mt, mas_allocated(&mas) != i); /* check request filled */
	281	+ for (j = 1; j <= i; j++) { /* Move the allocations to mas2 */
	282	+ mn = mas_pop_node(&mas); /* get the next node. */
	283	+ MT_BUG_ON(mt, mn == NULL);
	284	+ MT_BUG_ON(mt, not_empty(mn));
	285	+ mas_push_node(&mas2, mn);
	286	+ MT_BUG_ON(mt, mas_allocated(&mas2) != j);
	287	+ }
	288	+ MT_BUG_ON(mt, mas_allocated(&mas) != 0);
	289	+ MT_BUG_ON(mt, mas_allocated(&mas2) != i);
	290	+
	291	+ for (j = i; j > 0; j--) { /Free the requests /
	292	+ MT_BUG_ON(mt, mas_allocated(&mas2) != j);
	293	+ mn = mas_pop_node(&mas2); /* get the next node. */
	294	+ MT_BUG_ON(mt, mn == NULL);
	295	+ MT_BUG_ON(mt, not_empty(mn));
	296	+ ma_free_rcu(mn);
	297	+ }
	298	+ MT_BUG_ON(mt, mas_allocated(&mas2) != 0);
	299	+ }
	300	+
	301	+
	302	+ MT_BUG_ON(mt, mas_allocated(&mas) != 0);
	303	+ mas_node_count(&mas, MAPLE_ALLOC_SLOTS + 1); /* Request */
	304	+ MT_BUG_ON(mt, mas.node != MA_ERROR(-ENOMEM));
	305	+ MT_BUG_ON(mt, !mas_nomem(&mas, GFP_KERNEL));
	306	+ MT_BUG_ON(mt, mas_allocated(&mas) != MAPLE_ALLOC_SLOTS + 1);
	307	+ MT_BUG_ON(mt, mas.alloc->node_count != MAPLE_ALLOC_SLOTS - 1);
	308	+
	309	+ mn = mas_pop_node(&mas); /* get the next node. */
	310	+ MT_BUG_ON(mt, mn == NULL);
	311	+ MT_BUG_ON(mt, not_empty(mn));
	312	+ MT_BUG_ON(mt, mas_allocated(&mas) != MAPLE_ALLOC_SLOTS);
	313	+ MT_BUG_ON(mt, mas.alloc->node_count != MAPLE_ALLOC_SLOTS - 2);
	314	+
	315	+ mas_push_node(&mas, mn);
	316	+ MT_BUG_ON(mt, mas_allocated(&mas) != MAPLE_ALLOC_SLOTS + 1);
	317	+ MT_BUG_ON(mt, mas.alloc->node_count != MAPLE_ALLOC_SLOTS - 1);
	318	+
	319	+ /* Check the limit of pop/push/pop */
	320	+ mas_node_count(&mas, MAPLE_ALLOC_SLOTS + 2); /* Request */
	321	+ MT_BUG_ON(mt, mas_alloc_req(&mas) != 1);
	322	+ MT_BUG_ON(mt, mas.node != MA_ERROR(-ENOMEM));
	323	+ MT_BUG_ON(mt, !mas_nomem(&mas, GFP_KERNEL));
	324	+ MT_BUG_ON(mt, mas_alloc_req(&mas));
	325	+ MT_BUG_ON(mt, mas.alloc->node_count);
	326	+ MT_BUG_ON(mt, mas_allocated(&mas) != MAPLE_ALLOC_SLOTS + 2);
	327	+ mn = mas_pop_node(&mas);
	328	+ MT_BUG_ON(mt, not_empty(mn));
	329	+ MT_BUG_ON(mt, mas_allocated(&mas) != MAPLE_ALLOC_SLOTS + 1);
	330	+ MT_BUG_ON(mt, mas.alloc->node_count != MAPLE_ALLOC_SLOTS - 1);
	331	+ mas_push_node(&mas, mn);
	332	+ MT_BUG_ON(mt, mas.alloc->node_count);
	333	+ MT_BUG_ON(mt, mas_allocated(&mas) != MAPLE_ALLOC_SLOTS + 2);
	334	+ mn = mas_pop_node(&mas);
	335	+ MT_BUG_ON(mt, not_empty(mn));
	336	+ ma_free_rcu(mn);
	337	+ for (i = 1; i <= MAPLE_ALLOC_SLOTS + 1; i++) {
	338	+ mn = mas_pop_node(&mas);
	339	+ MT_BUG_ON(mt, not_empty(mn));
	340	+ ma_free_rcu(mn);
	341	+ }
	342	+ MT_BUG_ON(mt, mas_allocated(&mas) != 0);
	343	+
	344	+
	345	+ for (i = 3; i < MAPLE_NODE_MASK * 3; i++) {
	346	+ mas.node = MA_ERROR(-ENOMEM);
	347	+ mas_node_count(&mas, i); /* Request */
	348	+ mas_nomem(&mas, GFP_KERNEL); /* Fill request */
	349	+ mn = mas_pop_node(&mas); /* get the next node. */
	350	+ mas_push_node(&mas, mn); /* put it back */
	351	+ mas_destroy(&mas);
	352	+
	353	+ mas.node = MA_ERROR(-ENOMEM);
	354	+ mas_node_count(&mas, i); /* Request */
	355	+ mas_nomem(&mas, GFP_KERNEL); /* Fill request */
	356	+ mn = mas_pop_node(&mas); /* get the next node. */
	357	+ mn2 = mas_pop_node(&mas); /* get the next node. */
	358	+ mas_push_node(&mas, mn); /* put them back */
	359	+ mas_push_node(&mas, mn2);
	360	+ mas_destroy(&mas);
	361	+
	362	+ mas.node = MA_ERROR(-ENOMEM);
	363	+ mas_node_count(&mas, i); /* Request */
	364	+ mas_nomem(&mas, GFP_KERNEL); /* Fill request */
	365	+ mn = mas_pop_node(&mas); /* get the next node. */
	366	+ mn2 = mas_pop_node(&mas); /* get the next node. */
	367	+ mn3 = mas_pop_node(&mas); /* get the next node. */
	368	+ mas_push_node(&mas, mn); /* put them back */
	369	+ mas_push_node(&mas, mn2);
	370	+ mas_push_node(&mas, mn3);
	371	+ mas_destroy(&mas);
	372	+
	373	+ mas.node = MA_ERROR(-ENOMEM);
	374	+ mas_node_count(&mas, i); /* Request */
	375	+ mas_nomem(&mas, GFP_KERNEL); /* Fill request */
	376	+ mn = mas_pop_node(&mas); /* get the next node. */
	377	+ ma_free_rcu(mn);
	378	+ mas_destroy(&mas);
	379	+
	380	+ mas.node = MA_ERROR(-ENOMEM);
	381	+ mas_node_count(&mas, i); /* Request */
	382	+ mas_nomem(&mas, GFP_KERNEL); /* Fill request */
	383	+ mn = mas_pop_node(&mas); /* get the next node. */
	384	+ ma_free_rcu(mn);
	385	+ mn = mas_pop_node(&mas); /* get the next node. */
	386	+ ma_free_rcu(mn);
	387	+ mn = mas_pop_node(&mas); /* get the next node. */
	388	+ ma_free_rcu(mn);
	389	+ mas_destroy(&mas);
	390	+ }
	391	+
	392	+ mas.node = MA_ERROR(-ENOMEM);
	393	+ mas_node_count(&mas, 5); /* Request */
	394	+ mas_nomem(&mas, GFP_KERNEL); /* Fill request */
	395	+ MT_BUG_ON(mt, mas_allocated(&mas) != 5);
	396	+ mas.node = MA_ERROR(-ENOMEM);
	397	+ mas_node_count(&mas, 10); /* Request */
	398	+ mas_nomem(&mas, GFP_KERNEL); /* Fill request */
	399	+ mas.node = MAS_START;
	400	+ MT_BUG_ON(mt, mas_allocated(&mas) != 10);
	401	+ mas_destroy(&mas);
	402	+
	403	+ mas.node = MA_ERROR(-ENOMEM);
	404	+ mas_node_count(&mas, MAPLE_ALLOC_SLOTS - 1); /* Request */
	405	+ mas_nomem(&mas, GFP_KERNEL); /* Fill request */
	406	+ MT_BUG_ON(mt, mas_allocated(&mas) != MAPLE_ALLOC_SLOTS - 1);
	407	+ mas.node = MA_ERROR(-ENOMEM);
	408	+ mas_node_count(&mas, 10 + MAPLE_ALLOC_SLOTS - 1); /* Request */
	409	+ mas_nomem(&mas, GFP_KERNEL); /* Fill request */
	410	+ mas.node = MAS_START;
	411	+ MT_BUG_ON(mt, mas_allocated(&mas) != 10 + MAPLE_ALLOC_SLOTS - 1);
	412	+ mas_destroy(&mas);
	413	+
	414	+ mtree_unlock(mt);
	415	+}
	416	+
	417	+/*
	418	+ * Check erasing including RCU.
	419	+ */
	420	+static noinline void check_erase(struct maple_tree *mt, unsigned long index,
	421	+ void *ptr)
	422	+{
	423	+ MT_BUG_ON(mt, mtree_test_erase(mt, index) != ptr);
	424	+}
	425	+
	426	+#define erase_check_load(mt, i) check_load(mt, set[i], entry[i%2])
	427	+#define erase_check_insert(mt, i) check_insert(mt, set[i], entry[i%2])
	428	+#define erase_check_erase(mt, i) check_erase(mt, set[i], entry[i%2])
	429	+
	430	+static noinline void check_erase_testset(struct maple_tree *mt)
	431	+{
	432	+ unsigned long set[] = { 5015, 5014, 5017, 25, 1000,
	433	+ 1001, 1002, 1003, 1005, 0,
	434	+ 6003, 6002, 6008, 6012, 6015,
	435	+ 7003, 7002, 7008, 7012, 7015,
	436	+ 8003, 8002, 8008, 8012, 8015,
	437	+ 9003, 9002, 9008, 9012, 9015,
	438	+ 10003, 10002, 10008, 10012, 10015,
	439	+ 11003, 11002, 11008, 11012, 11015,
	440	+ 12003, 12002, 12008, 12012, 12015,
	441	+ 13003, 13002, 13008, 13012, 13015,
	442	+ 14003, 14002, 14008, 14012, 14015,
	443	+ 15003, 15002, 15008, 15012, 15015,
	444	+ };
	445	+
	446	+
	447	+ void *ptr = &set;
	448	+ void *entry[2] = { ptr, mt };
	449	+ void *root_node;
	450	+
	451	+
	452	+ rcu_register_thread();
	453	+ mt_set_in_rcu(mt);
	454	+ for (int i = 0; i < 4; i++)
	455	+ erase_check_insert(mt, i);
	456	+ for (int i = 0; i < 4; i++)
	457	+ erase_check_load(mt, i);
	458	+
	459	+ mt_set_non_kernel(2);
	460	+ erase_check_erase(mt, 1);
	461	+ erase_check_load(mt, 0);
	462	+ check_load(mt, set[1], NULL);
	463	+ for (int i = 2; i < 4; i++)
	464	+ erase_check_load(mt, i);
	465	+
	466	+
	467	+ erase_check_erase(mt, 2);
	468	+ erase_check_load(mt, 0);
	469	+ check_load(mt, set[1], NULL);
	470	+ check_load(mt, set[2], NULL);
	471	+
	472	+ erase_check_insert(mt, 1);
	473	+ erase_check_insert(mt, 2);
	474	+
	475	+ for (int i = 0; i < 4; i++)
	476	+ erase_check_load(mt, i);
	477	+
	478	+ /* Check erase and load without an allocation. */
	479	+ erase_check_load(mt, 3);
	480	+ erase_check_erase(mt, 1);
	481	+ erase_check_load(mt, 0);
	482	+ check_load(mt, set[1], NULL);
	483	+ for (int i = 2; i < 4; i++)
	484	+ erase_check_load(mt, i);
	485	+
	486	+ /*
	487	+ * Set the newly erased node. This will produce a different allocated
	488	+ * node to avoid busy slots.
	489	+ */
	490	+ root_node = mt->ma_root;
	491	+ erase_check_insert(mt, 1);
	492	+
	493	+ erase_check_load(mt, 0);
	494	+ check_load(mt, 5016, NULL);
	495	+ erase_check_load(mt, 1);
	496	+ check_load(mt, 5013, NULL);
	497	+ erase_check_load(mt, 2);
	498	+ check_load(mt, 5018, NULL);
	499	+ erase_check_load(mt, 3);
	500	+
	501	+ erase_check_erase(mt, 2); /* erase 5017 to check append */
	502	+ erase_check_load(mt, 0);
	503	+ check_load(mt, 5016, NULL);
	504	+ erase_check_load(mt, 1);
	505	+ check_load(mt, 5013, NULL);
	506	+ check_load(mt, set[2], NULL);
	507	+ check_load(mt, 5018, NULL);
	508	+
	509	+ erase_check_load(mt, 3);
	510	+
	511	+ root_node = mt->ma_root;
	512	+ erase_check_insert(mt, 2);
	513	+
	514	+ erase_check_load(mt, 0);
	515	+ check_load(mt, 5016, NULL);
	516	+ erase_check_load(mt, 1);
	517	+ check_load(mt, 5013, NULL);
	518	+ erase_check_load(mt, 2);
	519	+ check_load(mt, 5018, NULL);
	520	+ erase_check_load(mt, 3);
	521	+
	522	+ mt_set_non_kernel(1);
	523	+ erase_check_erase(mt, 2); /* erase 5017 to check append */
	524	+ erase_check_load(mt, 0);
	525	+ check_load(mt, 5016, NULL);
	526	+ check_load(mt, set[2], NULL);
	527	+ erase_check_erase(mt, 0); /* erase 5015 to check append */
	528	+ check_load(mt, set[0], NULL);
	529	+ check_load(mt, 5016, NULL);
	530	+ erase_check_insert(mt, 4); /* 1000 < Should not split. */
	531	+ check_load(mt, set[0], NULL);
	532	+ check_load(mt, 5016, NULL);
	533	+ erase_check_load(mt, 1);
	534	+ check_load(mt, 5013, NULL);
	535	+ check_load(mt, set[2], NULL);
	536	+ check_load(mt, 5018, NULL);
	537	+ erase_check_load(mt, 4);
	538	+ check_load(mt, 999, NULL);
	539	+ check_load(mt, 1001, NULL);
	540	+ erase_check_load(mt, 4);
	541	+ if (mt_in_rcu(mt))
	542	+ MT_BUG_ON(mt, root_node == mt->ma_root);
	543	+ else
	544	+ MT_BUG_ON(mt, root_node != mt->ma_root);
	545	+
	546	+ /* Should not have split. */
	547	+ MT_BUG_ON(mt, !mte_is_leaf(mt->ma_root));
	548	+
	549	+
	550	+ /* Coalesce testing */
	551	+ erase_check_insert(mt, 0);
	552	+ erase_check_insert(mt, 2);
	553	+
	554	+ for (int i = 5; i < 25; i++) {
	555	+ erase_check_insert(mt, i);
	556	+ for (int j = i; j >= 0; j--)
	557	+ erase_check_load(mt, j);
	558	+ }
	559	+
	560	+ erase_check_erase(mt, 14); /6015 /
	561	+ for (int i = 0; i < 25; i++) {
	562	+ if (i == 14)
	563	+ check_load(mt, set[i], NULL);
	564	+ else
	565	+ erase_check_load(mt, i);
	566	+ }
	567	+ erase_check_erase(mt, 16); /7002 /
	568	+ for (int i = 0; i < 25; i++) {
	569	+ if (i == 16 \|\| i == 14)
	570	+ check_load(mt, set[i], NULL);
	571	+ else
	572	+ erase_check_load(mt, i);
	573	+ }
	574	+
	575	+
	576	+ mt_set_non_kernel(1);
	577	+ erase_check_erase(mt, 13); /6012 /
	578	+ for (int i = 0; i < 25; i++) {
	579	+ if (i == 16 \|\| i == 14 \|\| i == 13)
	580	+ check_load(mt, set[i], NULL);
	581	+ else
	582	+ erase_check_load(mt, i);
	583	+ }
	584	+
	585	+ erase_check_erase(mt, 15); /7003 /
	586	+ for (int i = 0; i < 25; i++) {
	587	+ if (i <= 16 && i >= 13)
	588	+ check_load(mt, set[i], NULL);
	589	+ else
	590	+ erase_check_load(mt, i);
	591	+ }
	592	+
	593	+ mt_set_non_kernel(2);
	594	+ erase_check_erase(mt, 17); /7008 should* cause coalesce. */
	595	+ for (int i = 0; i < 25; i++) {
	596	+ if (i <= 17 && i >= 13)
	597	+ check_load(mt, set[i], NULL);
	598	+ else
	599	+ erase_check_load(mt, i);
	600	+ }
	601	+
	602	+ erase_check_erase(mt, 18); /7012 /
	603	+ for (int i = 0; i < 25; i++) {
	604	+ if (i <= 18 && i >= 13)
	605	+ check_load(mt, set[i], NULL);
	606	+ else
	607	+ erase_check_load(mt, i);
	608	+ }
	609	+
	610	+ mt_set_non_kernel(2);
	611	+ erase_check_erase(mt, 19); /7015 /
	612	+ for (int i = 0; i < 25; i++) {
	613	+ if (i <= 19 && i >= 13)
	614	+ check_load(mt, set[i], NULL);
	615	+ else
	616	+ erase_check_load(mt, i);
	617	+ }
	618	+
	619	+ erase_check_erase(mt, 20); /8003 /
	620	+ for (int i = 0; i < 25; i++) {
	621	+ if (i <= 20 && i >= 13)
	622	+ check_load(mt, set[i], NULL);
	623	+ else
	624	+ erase_check_load(mt, i);
	625	+ }
	626	+
	627	+ erase_check_erase(mt, 21); /8002 /
	628	+ for (int i = 0; i < 25; i++) {
	629	+ if (i <= 21 && i >= 13)
	630	+ check_load(mt, set[i], NULL);
	631	+ else
	632	+ erase_check_load(mt, i);
	633	+ }
	634	+
	635	+ mt_set_non_kernel(2);
	636	+ erase_check_erase(mt, 22); /8008 /
	637	+ for (int i = 0; i < 25; i++) {
	638	+ if (i <= 22 && i >= 13)
	639	+ check_load(mt, set[i], NULL);
	640	+ else
	641	+ erase_check_load(mt, i);
	642	+ }
	643	+ for (int i = 23; i < 25; i++)
	644	+ erase_check_erase(mt, i);
	645	+
	646	+ for (int i = 0; i < 25; i++) {
	647	+ if (i <= 25 && i >= 13)
	648	+ check_load(mt, set[i], NULL);
	649	+ else
	650	+ erase_check_load(mt, i);
	651	+ }
	652	+
	653	+ /* Shrinking tree test. */
	654	+
	655	+ for (int i = 13; i < ARRAY_SIZE(set); i++)
	656	+ erase_check_insert(mt, i);
	657	+
	658	+ mt_set_non_kernel(99);
	659	+ for (int i = 18; i < ARRAY_SIZE(set); i++) {
	660	+ erase_check_erase(mt, i);
	661	+ for (int j = 0; j < ARRAY_SIZE(set); j++) {
	662	+ if (j < 18 \|\| j > i)
	663	+ erase_check_load(mt, j);
	664	+ else
	665	+ check_load(mt, set[j], NULL);
	666	+ }
	667	+ }
	668	+ mt_set_non_kernel(35);
	669	+ for (int i = 0; i < 18; i++) {
	670	+ erase_check_erase(mt, i);
	671	+ for (int j = 0; j < ARRAY_SIZE(set); j++) {
	672	+ if (j < 18 && j > i)
	673	+ erase_check_load(mt, j);
	674	+ else
	675	+ check_load(mt, set[j], NULL);
	676	+ }
	677	+ }
	678	+ erase_check_insert(mt, 8);
	679	+ erase_check_insert(mt, 9);
	680	+ erase_check_erase(mt, 8);
	681	+ rcu_unregister_thread();
	682	+}
	683	+
	684	+/* End of erase testing */
	685	+
	686	+/* VM Generated Crashes - uses its own tree walk for verification */
	687	+#define erase_check_store_range(mt, a, i, ptr) mtree_test_store_range(mt, \
	688	+ a[(i)], a[(i + 1)], ptr)
	689	+#define STORE 1
	690	+#define SNULL 2
	691	+#define ERASE 3
	692	+#define ec_type_str(x) \
	693	+ (((x) == STORE) ? \
	694	+ "STORE" : \
	695	+ (((x) == SNULL) ? \
	696	+ "SNULL" : "ERASE") \
	697	+ )
	698	+#define check_erase2_debug 0
	699	+
	700	+/* Calculate the overwritten entries. */
	701	+int mas_ce2_over_count(struct ma_state mas_start, struct ma_state mas_end,
	702	+ void *s_entry, unsigned long s_min,
	703	+ void *e_entry, unsigned long e_max,
	704	+ unsigned long *set, int i, bool null_entry)
	705	+{
	706	+ int count = 0, span = 0;
	707	+ unsigned long retry = 0;
	708	+ void *entry;
	709	+ struct ma_state tmp;
	710	+
	711	+
	712	+ /* count slots */
	713	+ memcpy(&tmp, mas_start, sizeof(tmp));
	714	+ entry = mas_next(&tmp, mas_end->last);
	715	+ while (entry) {
	716	+ BUG_ON(retry > 50); /* stop infinite retry on testing. */
	717	+ if (xa_is_zero(s_entry)) {
	718	+ retry++;
	719	+ continue;
	720	+ }
	721	+ count++;
	722	+ span++;
	723	+ entry = mas_next(&tmp, mas_end->last);
	724	+ }
	725	+
	726	+ if (null_entry) {
	727	+ /* Check splitting end. */
	728	+ if (e_entry && (e_max > mas_end->last))
	729	+ count--;
	730	+
	731	+ /* check overwrite of entire start */
	732	+ if (s_entry && (s_min == mas_start->index))
	733	+ count++;
	734	+ } else { /* !null_entry (store) */
	735	+ bool esplit = e_max > mas_end->last;
	736	+ bool ssplit = s_min != mas_start->index;
	737	+
	738	+ if (s_entry && e_entry) {
	739	+ if (esplit && ssplit)
	740	+ count--;
	741	+ else if (ssplit)
	742	+ count--;
	743	+ else if (esplit) {
	744	+ if (span)
	745	+ count--;
	746	+ }
	747	+ } else if (s_entry && !e_entry) {
	748	+ if (ssplit)
	749	+ count--;
	750	+ } else if (!s_entry && e_entry) {
	751	+ if (esplit)
	752	+ count--;
	753	+ count--;
	754	+ } else {
	755	+ count--;
	756	+ }
	757	+ }
	758	+ return count;
	759	+}
	760	+
	761	+/*
	762	+ * mas_node_walk() - Walk a maple node to offset of the index.
	763	+ * @mas: The maple state
	764	+ * @type: The maple node type
	765	+ * @*range_min: Pointer to store the minimum range of the offset
	766	+ * @*range_max: Pointer to store the maximum range of the offset
	767	+ *
	768	+ * The offset will be stored in the maple state.
	769	+ *
	770	+ */
	771	+static inline void mas_node_walk(struct ma_state mas, struct maple_node node,
	772	+ enum maple_type type, unsigned long *range_min,
	773	+ unsigned long *range_max)
	774	+
	775	+{
	776	+ unsigned long *pivots;
	777	+ unsigned char count;
	778	+ unsigned long prev, max;
	779	+ unsigned char offset;
	780	+ unsigned long index;
	781	+
	782	+ if (unlikely(ma_is_dense(type))) {
	783	+ (range_max) = (range_min) = mas->index;
	784	+ if (unlikely(ma_dead_node(node)))
	785	+ return;
	786	+
	787	+ mas->offset = mas->index = mas->min;
	788	+ return;
	789	+ }
	790	+
	791	+ pivots = ma_pivots(node, type);
	792	+ max = pivots[0];
	793	+ if (unlikely(ma_dead_node(node)))
	794	+ return;
	795	+
	796	+ offset = 0;
	797	+ prev = mas->min;
	798	+ index = mas->index;
	799	+ if (unlikely(index <= max))
	800	+ goto offset_zero;
	801	+
	802	+ count = mt_pivots[type];
	803	+ while (++offset < count) {
	804	+ prev = max;
	805	+ max = pivots[offset];
	806	+ if (unlikely(ma_dead_node(node)))
	807	+ return;
	808	+
	809	+ if (index <= max)
	810	+ goto offset_found;
	811	+ else if (unlikely(!max))
	812	+ goto mas_max;
	813	+ }
	814	+
	815	+ prev = max;
	816	+mas_max:
	817	+ max = mas->max;
	818	+offset_found:
	819	+ prev++;
	820	+offset_zero:
	821	+ mas->offset = offset;
	822	+ if (ma_is_leaf(type)) {
	823	+ *range_max = max;
	824	+ *range_min = prev;
	825	+ } else {
	826	+ mas->max = max;
	827	+ mas->min = prev;
	828	+ }
	829	+}
	830	+
	831	+/*
	832	+ * mas_descend_walk(): Locates a value and sets the mas->node and slot
	833	+ * accordingly. range_min and range_max are set to the range which the entry is
	834	+ * valid.
	835	+ * @mas: The maple state
	836	+ * @*range_min: A pointer to store the minimum of the range
	837	+ * @*range_max: A pointer to store the maximum of the range
	838	+ *
	839	+ * Check mas->node is still valid on return of any value.
	840	+ *
	841	+ * Return: true if pointing to a valid node and offset. False otherwise.
	842	+ */
	843	+static inline bool mas_descend_walk(struct ma_state *mas,
	844	+ unsigned long range_min, unsigned long range_max)
	845	+{
	846	+ struct maple_enode *next;
	847	+ struct maple_node *node;
	848	+ enum maple_type type;
	849	+
	850	+ next = mas->node;
	851	+ while (true) {
	852	+ node = mte_to_node(next);
	853	+ type = mte_node_type(next);
	854	+ mas_node_walk(mas, node, type, range_min, range_max);
	855	+ next = mas_slot(mas, ma_slots(node, type), mas->offset);
	856	+ if (unlikely(ma_dead_node(node)))
	857	+ return false;
	858	+
	859	+ if (unlikely(ma_is_leaf(type)))
	860	+ return true;
	861	+
	862	+ /* Descend. */
	863	+ mas->node = next;
	864	+ }
	865	+ return false;
	866	+}
	867	+
	868	+/*
	869	+ * mas_tree_walk() - Walk to @mas->index and set the range values.
	870	+ * @mas: The maple state.
	871	+ * @*range_min: The minimum range to be set.
	872	+ * @*range_max: The maximum range to be set.
	873	+ *
	874	+ * Ranges are only valid if there is a valid entry at @mas->index.
	875	+ *
	876	+ * Return: True if a value exists, false otherwise.
	877	+ */
	878	+static inline bool mas_tree_walk(struct ma_state mas, unsigned long range_min,
	879	+ unsigned long *range_max)
	880	+{
	881	+ bool ret;
	882	+
	883	+retry:
	884	+ ret = false;
	885	+ mas_start(mas);
	886	+ if (mas_is_none(mas))
	887	+ goto not_found;
	888	+
	889	+ if (mas_is_ptr(mas)) {
	890	+ range_min = range_max = 0;
	891	+ if (!mas->index)
	892	+ return true;
	893	+
	894	+ goto not_found;
	895	+ }
	896	+
	897	+ ret = mas_descend_walk(mas, range_min, range_max);
	898	+ if (unlikely(mte_dead_node(mas->node))) {
	899	+ mas->node = MAS_START;
	900	+ goto retry;
	901	+ }
	902	+
	903	+ return ret;
	904	+
	905	+not_found:
	906	+ mas->offset = MAPLE_NODE_SLOTS;
	907	+ return false;
	908	+}
	909	+
	910	+static inline void mas_range_load(struct ma_state mas,
	911	+ unsigned long range_min, unsigned long range_max)
	912	+
	913	+{
	914	+ void *entry = NULL;
	915	+ unsigned long index = mas->index;
	916	+
	917	+ if (mas_is_none(mas) \|\| mas_is_paused(mas))
	918	+ mas->node = MAS_START;
	919	+retry:
	920	+ if (mas_tree_walk(mas, range_min, range_max))
	921	+ if (unlikely(mas->node == MAS_ROOT))
	922	+ return mas_root(mas);
	923	+
	924	+ if (likely(mas->offset != MAPLE_NODE_SLOTS))
	925	+ entry = mas_get_slot(mas, mas->offset);
	926	+
	927	+ if (mas_dead_node(mas, index))
	928	+ goto retry;
	929	+
	930	+ return entry;
	931	+}
	932	+
	933	+#if defined(CONFIG_64BIT)
	934	+static noinline void check_erase2_testset(struct maple_tree *mt,
	935	+ unsigned long *set, unsigned long size)
	936	+{
	937	+ int entry_count = 0;
	938	+ int check = 0;
	939	+ void *foo;
	940	+ unsigned long addr = 0;
	941	+ void s_entry = NULL, e_entry = NULL;
	942	+
	943	+ MA_STATE(mas, mt, 0, 0);
	944	+
	945	+ for (int i = 0; i < size; i += 3) {
	946	+ unsigned long s_min, s_max;
	947	+ unsigned long e_min, e_max;
	948	+ void *value = NULL;
	949	+
	950	+ MA_STATE(mas_start, mt, set[i+1], set[i+1]);
	951	+ MA_STATE(mas_end, mt, set[i+2], set[i+2]);
	952	+ mt_set_non_kernel(127);
	953	+#if check_erase2_debug
	954	+ pr_err("%s: %d %s %lu - %lu\n", __func__, i,
	955	+ ec_type_str(set[i]),
	956	+ set[i+1], set[i+2]);
	957	+#endif
	958	+ s_entry = mas_range_load(&mas_start, &s_min, &s_max);
	959	+ e_entry = mas_range_load(&mas_end, &e_min, &e_max);
	960	+
	961	+ switch (set[i]) {
	962	+ case SNULL:
	963	+ if ((s_min == set[i+1]) && (s_max == set[i+2])) {
	964	+ if (s_entry)
	965	+ entry_count--;
	966	+ } else if ((s_min != set[i+1]) && (s_max != set[i+2])) {
	967	+ entry_count++;
	968	+ } else if ((mas_start.node != mas_end.node) \|\|
	969	+ (mas_start.offset != mas_end.offset)) {
	970	+ entry_count -=
	971	+ mas_ce2_over_count(&mas_start, &mas_end,
	972	+ s_entry, s_min,
	973	+ e_entry, e_max, set, i,
	974	+ true);
	975	+ }
	976	+
	977	+
	978	+ erase_check_store_range(mt, set, i + 1, value);
	979	+ break;
	980	+ case STORE:
	981	+ value = xa_mk_value(set[i + 1]);
	982	+ if (mas_start.offset > mt_slot_count(mas_start.node)) {
	983	+ entry_count++; /* appending an entry. */
	984	+ } else if ((s_min == e_min) && (s_max == e_max)) {
	985	+ if (!entry_count)
	986	+ entry_count++;
	987	+
	988	+ else if (s_entry) {
	989	+ if (e_max > mas_end.last)
	990	+ entry_count++;
	991	+
	992	+ if (s_min < mas_start.index)
	993	+ entry_count++;
	994	+
	995	+ } else {
	996	+ entry_count++;
	997	+ }
	998	+ } else {
	999	+ entry_count -=
	1000	+ mas_ce2_over_count(&mas_start, &mas_end,
	1001	+ s_entry, s_min,
	1002	+ e_entry, e_max, set, i,
	1003	+ false);
	1004	+ }
	1005	+
	1006	+ erase_check_store_range(mt, set, i + 1, value);
	1007	+ break;
	1008	+ case ERASE:
	1009	+ if (!s_entry)
	1010	+ break;
	1011	+ check_erase(mt, set[i+1], xa_mk_value(set[i+1]));
	1012	+ entry_count--;
	1013	+ break;
	1014	+ }
	1015	+ mt_validate(mt);
	1016	+ if (entry_count)
	1017	+ MT_BUG_ON(mt, !mt_height(mt));
	1018	+#if check_erase2_debug > 1
	1019	+ mt_dump(mt);
	1020	+#endif
	1021	+#if check_erase2_debug
	1022	+ pr_err("Done\n");
	1023	+#endif
	1024	+
	1025	+ check = 0;
	1026	+ addr = 0;
	1027	+ mt_for_each(mt, foo, addr, ULONG_MAX) {
	1028	+ check++;
	1029	+#if check_erase2_debug > 2
	1030	+ pr_err("mt: %lu -> %p (%d)\n", addr+1, foo, check);
	1031	+#endif
	1032	+ if (check > entry_count)
	1033	+ break;
	1034	+ }
	1035	+
	1036	+#if check_erase2_debug > 2
	1037	+ pr_err("mt_for_each %d and count %d\n", check, entry_count);
	1038	+#endif
	1039	+
	1040	+ MT_BUG_ON(mt, check != entry_count);
	1041	+
	1042	+ check = 0;
	1043	+ addr = 0;
	1044	+ mas_reset(&mas);
	1045	+ mas.index = 0;
	1046	+ rcu_read_lock();
	1047	+ mas_for_each(&mas, foo, ULONG_MAX) {
	1048	+ if (xa_is_zero(foo)) {
	1049	+ if (addr == mas.index) {
	1050	+ mt_dump(mas.tree);
	1051	+ pr_err("retry failed %lu - %lu\n",
	1052	+ mas.index, mas.last);
	1053	+ MT_BUG_ON(mt, 1);
	1054	+ }
	1055	+ addr = mas.index;
	1056	+ continue;
	1057	+ }
	1058	+#if check_erase2_debug > 2
	1059	+ pr_err("mas: %lu -> %p\n", mas.index, foo);
	1060	+#endif
	1061	+ check++;
	1062	+ if (check > entry_count)
	1063	+ break;
	1064	+ }
	1065	+ rcu_read_unlock();
	1066	+#if check_erase2_debug > 2
	1067	+ pr_err("mas_for_each %d and count %d\n", check, entry_count);
	1068	+ mt_validate(mt);
	1069	+#endif
	1070	+
	1071	+ MT_BUG_ON(mt, check != entry_count);
	1072	+
	1073	+ MT_BUG_ON(mt, mtree_load(mas.tree, 0) != NULL);
	1074	+ }
	1075	+}
	1076	+
	1077	+
	1078	+/* These tests were pulled from KVM tree modifications which failed. */
	1079	+static noinline void check_erase2_sets(struct maple_tree *mt)
	1080	+{
	1081	+ void *entry;
	1082	+ unsigned long start = 0;
	1083	+ unsigned long set[] = {
	1084	+STORE, 140737488347136, 140737488351231,
	1085	+STORE, 140721266458624, 140737488351231,
	1086	+ERASE, 140721266458624, 140737488351231,
	1087	+STORE, 140721266458624, 140721266462719,
	1088	+STORE, 94735788949504, 94735789121535,
	1089	+ERASE, 94735788949504, 94735789121535,
	1090	+STORE, 94735788949504, 94735788965887,
	1091	+STORE, 94735788965888, 94735789121535,
	1092	+ERASE, 94735788965888, 94735789121535,
	1093	+STORE, 94735788965888, 94735789068287,
	1094	+STORE, 94735789068288, 94735789109247,
	1095	+STORE, 94735789109248, 94735789121535,
	1096	+STORE, 140253902692352, 140253902864383,
	1097	+ERASE, 140253902692352, 140253902864383,
	1098	+STORE, 140253902692352, 140253902696447,
	1099	+STORE, 140253902696448, 140253902864383,
	1100	+ };
	1101	+ unsigned long set2[] = {
	1102	+STORE, 140737488347136, 140737488351231,
	1103	+STORE, 140735933583360, 140737488351231,
	1104	+ERASE, 140735933583360, 140737488351231,
	1105	+STORE, 140735933583360, 140735933587455,
	1106	+STORE, 94811003260928, 94811003432959,
	1107	+ERASE, 94811003260928, 94811003432959,
	1108	+STORE, 94811003260928, 94811003277311,
	1109	+STORE, 94811003277312, 94811003432959,
	1110	+ERASE, 94811003277312, 94811003432959,
	1111	+STORE, 94811003277312, 94811003379711,
	1112	+STORE, 94811003379712, 94811003420671,
	1113	+STORE, 94811003420672, 94811003432959,
	1114	+STORE, 140277094653952, 140277094825983,
	1115	+ERASE, 140277094653952, 140277094825983,
	1116	+STORE, 140277094653952, 140277094658047,
	1117	+STORE, 140277094658048, 140277094825983,
	1118	+ERASE, 140277094658048, 140277094825983,
	1119	+STORE, 140277094658048, 140277094780927,
	1120	+STORE, 140277094780928, 140277094813695,
	1121	+STORE, 140277094813696, 140277094821887,
	1122	+STORE, 140277094821888, 140277094825983,
	1123	+STORE, 140735933906944, 140735933911039,
	1124	+ };
	1125	+ unsigned long set3[] = {
	1126	+STORE, 140737488347136, 140737488351231,
	1127	+STORE, 140735790264320, 140737488351231,
	1128	+ERASE, 140735790264320, 140737488351231,
	1129	+STORE, 140735790264320, 140735790268415,
	1130	+STORE, 94016597282816, 94016597454847,
	1131	+ERASE, 94016597282816, 94016597454847,
	1132	+STORE, 94016597282816, 94016597299199,
	1133	+STORE, 94016597299200, 94016597454847,
	1134	+ERASE, 94016597299200, 94016597454847,
	1135	+STORE, 94016597299200, 94016597401599,
	1136	+STORE, 94016597401600, 94016597442559,
	1137	+STORE, 94016597442560, 94016597454847,
	1138	+STORE, 140496959283200, 140496959455231,
	1139	+ERASE, 140496959283200, 140496959455231,
	1140	+STORE, 140496959283200, 140496959287295,
	1141	+STORE, 140496959287296, 140496959455231,
	1142	+ERASE, 140496959287296, 140496959455231,
	1143	+STORE, 140496959287296, 140496959410175,
	1144	+STORE, 140496959410176, 140496959442943,
	1145	+STORE, 140496959442944, 140496959451135,
	1146	+STORE, 140496959451136, 140496959455231,
	1147	+STORE, 140735791718400, 140735791722495,
	1148	+STORE, 140735791706112, 140735791718399,
	1149	+STORE, 47135835713536, 47135835721727,
	1150	+STORE, 47135835721728, 47135835729919,
	1151	+STORE, 47135835729920, 47135835893759,
	1152	+ERASE, 47135835729920, 47135835893759,
	1153	+STORE, 47135835729920, 47135835742207,
	1154	+STORE, 47135835742208, 47135835893759,
	1155	+STORE, 47135835840512, 47135835893759,
	1156	+STORE, 47135835742208, 47135835840511,
	1157	+ERASE, 47135835742208, 47135835840511,
	1158	+STORE, 47135835742208, 47135835840511,
	1159	+STORE, 47135835885568, 47135835893759,
	1160	+STORE, 47135835840512, 47135835885567,
	1161	+ERASE, 47135835840512, 47135835885567,
	1162	+STORE, 47135835840512, 47135835893759,
	1163	+ERASE, 47135835840512, 47135835893759,
	1164	+STORE, 47135835840512, 47135835885567,
	1165	+STORE, 47135835885568, 47135835893759,
	1166	+ };
	1167	+
	1168	+ unsigned long set4[] = {
	1169	+STORE, 140737488347136, 140737488351231,
	1170	+STORE, 140728251703296, 140737488351231,
	1171	+ERASE, 140728251703296, 140737488351231,
	1172	+STORE, 140728251703296, 140728251707391,
	1173	+STORE, 94668429205504, 94668429377535,
	1174	+ERASE, 94668429205504, 94668429377535,
	1175	+STORE, 94668429205504, 94668429221887,
	1176	+STORE, 94668429221888, 94668429377535,
	1177	+ERASE, 94668429221888, 94668429377535,
	1178	+STORE, 94668429221888, 94668429324287,
	1179	+STORE, 94668429324288, 94668429365247,
	1180	+STORE, 94668429365248, 94668429377535,
	1181	+STORE, 47646523273216, 47646523445247,
	1182	+ERASE, 47646523273216, 47646523445247,
	1183	+STORE, 47646523273216, 47646523277311,
	1184	+STORE, 47646523277312, 47646523445247,
	1185	+ERASE, 47646523277312, 47646523445247,
	1186	+STORE, 47646523277312, 47646523400191,
	1187	+ };
	1188	+
	1189	+ unsigned long set5[] = {
	1190	+STORE, 140737488347136, 140737488351231,
	1191	+STORE, 140726874062848, 140737488351231,
	1192	+ERASE, 140726874062848, 140737488351231,
	1193	+STORE, 140726874062848, 140726874066943,
	1194	+STORE, 94248892870656, 94248893042687,
	1195	+ERASE, 94248892870656, 94248893042687,
	1196	+STORE, 94248892870656, 94248892887039,
	1197	+STORE, 94248892887040, 94248893042687,
	1198	+ERASE, 94248892887040, 94248893042687,
	1199	+STORE, 94248892887040, 94248892989439,
	1200	+STORE, 94248892989440, 94248893030399,
	1201	+STORE, 94248893030400, 94248893042687,
	1202	+STORE, 47884786266112, 47884786438143,
	1203	+ERASE, 47884786266112, 47884786438143,
	1204	+STORE, 47884786266112, 47884786270207,
	1205	+STORE, 47884786270208, 47884786438143,
	1206	+ERASE, 47884786270208, 47884786438143,
	1207	+STORE, 47884786270208, 47884786393087,
	1208	+STORE, 47884786393088, 47884786425855,
	1209	+STORE, 47884786425856, 47884786434047,
	1210	+STORE, 47884786434048, 47884786438143,
	1211	+STORE, 140726874513408, 140726874517503,
	1212	+STORE, 140726874501120, 140726874513407,
	1213	+STORE, 47884786438144, 47884786446335,
	1214	+STORE, 47884786446336, 47884786454527,
	1215	+STORE, 47884786454528, 47884786618367,
	1216	+ERASE, 47884786454528, 47884786618367,
	1217	+STORE, 47884786454528, 47884786466815,
	1218	+STORE, 47884786466816, 47884786618367,
	1219	+STORE, 47884786565120, 47884786618367,
	1220	+STORE, 47884786466816, 47884786565119,
	1221	+ERASE, 47884786466816, 47884786565119,
	1222	+STORE, 47884786466816, 47884786565119,
	1223	+STORE, 47884786610176, 47884786618367,
	1224	+STORE, 47884786565120, 47884786610175,
	1225	+ERASE, 47884786565120, 47884786610175,
	1226	+STORE, 47884786565120, 47884786618367,
	1227	+ERASE, 47884786565120, 47884786618367,
	1228	+STORE, 47884786565120, 47884786610175,
	1229	+STORE, 47884786610176, 47884786618367,
	1230	+ERASE, 47884786610176, 47884786618367,
	1231	+STORE, 47884786610176, 47884786618367,
	1232	+STORE, 47884786618368, 47884789669887,
	1233	+STORE, 47884787163136, 47884789669887,
	1234	+STORE, 47884786618368, 47884787163135,
	1235	+ERASE, 47884787163136, 47884789669887,
	1236	+STORE, 47884787163136, 47884789448703,
	1237	+STORE, 47884789448704, 47884789669887,
	1238	+STORE, 47884788858880, 47884789448703,
	1239	+STORE, 47884787163136, 47884788858879,
	1240	+ERASE, 47884787163136, 47884788858879,
	1241	+STORE, 47884787163136, 47884788858879,
	1242	+STORE, 47884789444608, 47884789448703,
	1243	+STORE, 47884788858880, 47884789444607,
	1244	+ERASE, 47884788858880, 47884789444607,
	1245	+STORE, 47884788858880, 47884789444607,
	1246	+STORE, 47884789653504, 47884789669887,
	1247	+STORE, 47884789448704, 47884789653503,
	1248	+ERASE, 47884789448704, 47884789653503,
	1249	+STORE, 47884789448704, 47884789653503,
	1250	+ERASE, 47884789653504, 47884789669887,
	1251	+STORE, 47884789653504, 47884789669887,
	1252	+STORE, 47884789669888, 47884791508991,
	1253	+STORE, 47884789809152, 47884791508991,
	1254	+STORE, 47884789669888, 47884789809151,
	1255	+ERASE, 47884789809152, 47884791508991,
	1256	+STORE, 47884789809152, 47884791468031,
	1257	+STORE, 47884791468032, 47884791508991,
	1258	+STORE, 47884791152640, 47884791468031,
	1259	+STORE, 47884789809152, 47884791152639,
	1260	+ERASE, 47884789809152, 47884791152639,
	1261	+STORE, 47884789809152, 47884791152639,
	1262	+STORE, 47884791463936, 47884791468031,
	1263	+STORE, 47884791152640, 47884791463935,
	1264	+ERASE, 47884791152640, 47884791463935,
	1265	+STORE, 47884791152640, 47884791463935,
	1266	+STORE, 47884791492608, 47884791508991,
	1267	+STORE, 47884791468032, 47884791492607,
	1268	+ERASE, 47884791468032, 47884791492607,
	1269	+STORE, 47884791468032, 47884791492607,
	1270	+ERASE, 47884791492608, 47884791508991,
	1271	+STORE, 47884791492608, 47884791508991,
	1272	+STORE, 47884791508992, 47884791644159,
	1273	+ERASE, 47884791508992, 47884791644159,
	1274	+STORE, 47884791508992, 47884791533567,
	1275	+STORE, 47884791533568, 47884791644159,
	1276	+STORE, 47884791595008, 47884791644159,
	1277	+STORE, 47884791533568, 47884791595007,
	1278	+ERASE, 47884791533568, 47884791595007,
	1279	+STORE, 47884791533568, 47884791595007,
	1280	+STORE, 47884791619584, 47884791644159,
	1281	+STORE, 47884791595008, 47884791619583,
	1282	+ERASE, 47884791595008, 47884791619583,
	1283	+STORE, 47884791595008, 47884791644159,
	1284	+ERASE, 47884791595008, 47884791644159,
	1285	+STORE, 47884791595008, 47884791619583,
	1286	+STORE, 47884791619584, 47884791644159,
	1287	+STORE, 47884791627776, 47884791644159,
	1288	+STORE, 47884791619584, 47884791627775,
	1289	+ERASE, 47884791619584, 47884791627775,
	1290	+STORE, 47884791619584, 47884791627775,
	1291	+ERASE, 47884791627776, 47884791644159,
	1292	+STORE, 47884791627776, 47884791644159,
	1293	+STORE, 47884791644160, 47884791664639,
	1294	+ERASE, 47884791644160, 47884791664639,
	1295	+STORE, 47884791644160, 47884791648255,
	1296	+STORE, 47884791648256, 47884791664639,
	1297	+STORE, 47884791652352, 47884791664639,
	1298	+STORE, 47884791648256, 47884791652351,
	1299	+ERASE, 47884791648256, 47884791652351,
	1300	+STORE, 47884791648256, 47884791652351,
	1301	+STORE, 47884791656448, 47884791664639,
	1302	+STORE, 47884791652352, 47884791656447,
	1303	+ERASE, 47884791652352, 47884791656447,
	1304	+STORE, 47884791652352, 47884791664639,
	1305	+ERASE, 47884791652352, 47884791664639,
	1306	+STORE, 47884791652352, 47884791656447,
	1307	+STORE, 47884791656448, 47884791664639,
	1308	+ERASE, 47884791656448, 47884791664639,
	1309	+STORE, 47884791656448, 47884791664639,
	1310	+STORE, 47884791664640, 47884791672831,
	1311	+ERASE, 47884791468032, 47884791492607,
	1312	+STORE, 47884791468032, 47884791484415,
	1313	+STORE, 47884791484416, 47884791492607,
	1314	+ERASE, 47884791656448, 47884791664639,
	1315	+STORE, 47884791656448, 47884791660543,
	1316	+STORE, 47884791660544, 47884791664639,
	1317	+ERASE, 47884791619584, 47884791627775,
	1318	+STORE, 47884791619584, 47884791623679,
	1319	+STORE, 47884791623680, 47884791627775,
	1320	+ };
	1321	+
	1322	+ unsigned long set6[] = {
	1323	+STORE, 140737488347136, 140737488351231,
	1324	+STORE, 140722999021568, 140737488351231,
	1325	+ERASE, 140722999021568, 140737488351231,
	1326	+STORE, 140722999021568, 140722999025663,
	1327	+STORE, 94901500268544, 94901500440575,
	1328	+ERASE, 94901500268544, 94901500440575,
	1329	+STORE, 94901500268544, 94901500284927,
	1330	+STORE, 94901500284928, 94901500440575,
	1331	+ERASE, 94901500284928, 94901500440575,
	1332	+STORE, 94901500284928, 94901500387327,
	1333	+STORE, 94901500387328, 94901500428287,
	1334	+STORE, 94901500428288, 94901500440575,
	1335	+STORE, 47430426660864, 47430426832895,
	1336	+ERASE, 47430426660864, 47430426832895,
	1337	+STORE, 47430426660864, 47430426664959,
	1338	+STORE, 47430426664960, 47430426832895,
	1339	+ERASE, 47430426664960, 47430426832895,
	1340	+STORE, 47430426664960, 47430426787839,
	1341	+STORE, 47430426787840, 47430426820607,
	1342	+STORE, 47430426820608, 47430426828799,
	1343	+STORE, 47430426828800, 47430426832895,
	1344	+STORE, 140722999115776, 140722999119871,
	1345	+STORE, 140722999103488, 140722999115775,
	1346	+STORE, 47430426832896, 47430426841087,
	1347	+STORE, 47430426841088, 47430426849279,
	1348	+STORE, 47430426849280, 47430427013119,
	1349	+ERASE, 47430426849280, 47430427013119,
	1350	+STORE, 47430426849280, 47430426861567,
	1351	+STORE, 47430426861568, 47430427013119,
	1352	+STORE, 47430426959872, 47430427013119,
	1353	+STORE, 47430426861568, 47430426959871,
	1354	+ERASE, 47430426861568, 47430426959871,
	1355	+STORE, 47430426861568, 47430426959871,
	1356	+STORE, 47430427004928, 47430427013119,
	1357	+STORE, 47430426959872, 47430427004927,
	1358	+ERASE, 47430426959872, 47430427004927,
	1359	+STORE, 47430426959872, 47430427013119,
	1360	+ERASE, 47430426959872, 47430427013119,
	1361	+STORE, 47430426959872, 47430427004927,
	1362	+STORE, 47430427004928, 47430427013119,
	1363	+ERASE, 47430427004928, 47430427013119,
	1364	+STORE, 47430427004928, 47430427013119,
	1365	+STORE, 47430427013120, 47430430064639,
	1366	+STORE, 47430427557888, 47430430064639,
	1367	+STORE, 47430427013120, 47430427557887,
	1368	+ERASE, 47430427557888, 47430430064639,
	1369	+STORE, 47430427557888, 47430429843455,
	1370	+STORE, 47430429843456, 47430430064639,
	1371	+STORE, 47430429253632, 47430429843455,
	1372	+STORE, 47430427557888, 47430429253631,
	1373	+ERASE, 47430427557888, 47430429253631,
	1374	+STORE, 47430427557888, 47430429253631,
	1375	+STORE, 47430429839360, 47430429843455,
	1376	+STORE, 47430429253632, 47430429839359,
	1377	+ERASE, 47430429253632, 47430429839359,
	1378	+STORE, 47430429253632, 47430429839359,
	1379	+STORE, 47430430048256, 47430430064639,
	1380	+STORE, 47430429843456, 47430430048255,
	1381	+ERASE, 47430429843456, 47430430048255,
	1382	+STORE, 47430429843456, 47430430048255,
	1383	+ERASE, 47430430048256, 47430430064639,
	1384	+STORE, 47430430048256, 47430430064639,
	1385	+STORE, 47430430064640, 47430431903743,
	1386	+STORE, 47430430203904, 47430431903743,
	1387	+STORE, 47430430064640, 47430430203903,
	1388	+ERASE, 47430430203904, 47430431903743,
	1389	+STORE, 47430430203904, 47430431862783,
	1390	+STORE, 47430431862784, 47430431903743,
	1391	+STORE, 47430431547392, 47430431862783,
	1392	+STORE, 47430430203904, 47430431547391,
	1393	+ERASE, 47430430203904, 47430431547391,
	1394	+STORE, 47430430203904, 47430431547391,
	1395	+STORE, 47430431858688, 47430431862783,
	1396	+STORE, 47430431547392, 47430431858687,
	1397	+ERASE, 47430431547392, 47430431858687,
	1398	+STORE, 47430431547392, 47430431858687,
	1399	+STORE, 47430431887360, 47430431903743,
	1400	+STORE, 47430431862784, 47430431887359,
	1401	+ERASE, 47430431862784, 47430431887359,
	1402	+STORE, 47430431862784, 47430431887359,
	1403	+ERASE, 47430431887360, 47430431903743,
	1404	+STORE, 47430431887360, 47430431903743,
	1405	+STORE, 47430431903744, 47430432038911,
	1406	+ERASE, 47430431903744, 47430432038911,
	1407	+STORE, 47430431903744, 47430431928319,
	1408	+STORE, 47430431928320, 47430432038911,
	1409	+STORE, 47430431989760, 47430432038911,
	1410	+STORE, 47430431928320, 47430431989759,
	1411	+ERASE, 47430431928320, 47430431989759,
	1412	+STORE, 47430431928320, 47430431989759,
	1413	+STORE, 47430432014336, 47430432038911,
	1414	+STORE, 47430431989760, 47430432014335,
	1415	+ERASE, 47430431989760, 47430432014335,
	1416	+STORE, 47430431989760, 47430432038911,
	1417	+ERASE, 47430431989760, 47430432038911,
	1418	+STORE, 47430431989760, 47430432014335,
	1419	+STORE, 47430432014336, 47430432038911,
	1420	+STORE, 47430432022528, 47430432038911,
	1421	+STORE, 47430432014336, 47430432022527,
	1422	+ERASE, 47430432014336, 47430432022527,
	1423	+STORE, 47430432014336, 47430432022527,
	1424	+ERASE, 47430432022528, 47430432038911,
	1425	+STORE, 47430432022528, 47430432038911,
	1426	+STORE, 47430432038912, 47430432059391,
	1427	+ERASE, 47430432038912, 47430432059391,
	1428	+STORE, 47430432038912, 47430432043007,
	1429	+STORE, 47430432043008, 47430432059391,
	1430	+STORE, 47430432047104, 47430432059391,
	1431	+STORE, 47430432043008, 47430432047103,
	1432	+ERASE, 47430432043008, 47430432047103,
	1433	+STORE, 47430432043008, 47430432047103,
	1434	+STORE, 47430432051200, 47430432059391,
	1435	+STORE, 47430432047104, 47430432051199,
	1436	+ERASE, 47430432047104, 47430432051199,
	1437	+STORE, 47430432047104, 47430432059391,
	1438	+ERASE, 47430432047104, 47430432059391,
	1439	+STORE, 47430432047104, 47430432051199,
	1440	+STORE, 47430432051200, 47430432059391,
	1441	+ERASE, 47430432051200, 47430432059391,
	1442	+STORE, 47430432051200, 47430432059391,
	1443	+STORE, 47430432059392, 47430432067583,
	1444	+ERASE, 47430431862784, 47430431887359,
	1445	+STORE, 47430431862784, 47430431879167,
	1446	+STORE, 47430431879168, 47430431887359,
	1447	+ERASE, 47430432051200, 47430432059391,
	1448	+STORE, 47430432051200, 47430432055295,
	1449	+STORE, 47430432055296, 47430432059391,
	1450	+ERASE, 47430432014336, 47430432022527,
	1451	+STORE, 47430432014336, 47430432018431,
	1452	+STORE, 47430432018432, 47430432022527,
	1453	+ };
	1454	+ unsigned long set7[] = {
	1455	+STORE, 140737488347136, 140737488351231,
	1456	+STORE, 140729808330752, 140737488351231,
	1457	+ERASE, 140729808330752, 140737488351231,
	1458	+STORE, 140729808330752, 140729808334847,
	1459	+STORE, 94629632020480, 94629632192511,
	1460	+ERASE, 94629632020480, 94629632192511,
	1461	+STORE, 94629632020480, 94629632036863,
	1462	+STORE, 94629632036864, 94629632192511,
	1463	+ERASE, 94629632036864, 94629632192511,
	1464	+STORE, 94629632036864, 94629632139263,
	1465	+STORE, 94629632139264, 94629632180223,
	1466	+STORE, 94629632180224, 94629632192511,
	1467	+STORE, 47439981776896, 47439981948927,
	1468	+ERASE, 47439981776896, 47439981948927,
	1469	+STORE, 47439981776896, 47439981780991,
	1470	+STORE, 47439981780992, 47439981948927,
	1471	+ERASE, 47439981780992, 47439981948927,
	1472	+STORE, 47439981780992, 47439981903871,
	1473	+STORE, 47439981903872, 47439981936639,
	1474	+STORE, 47439981936640, 47439981944831,
	1475	+STORE, 47439981944832, 47439981948927,
	1476	+STORE, 140729808474112, 140729808478207,
	1477	+STORE, 140729808461824, 140729808474111,
	1478	+STORE, 47439981948928, 47439981957119,
	1479	+STORE, 47439981957120, 47439981965311,
	1480	+STORE, 47439981965312, 47439982129151,
	1481	+ERASE, 47439981965312, 47439982129151,
	1482	+STORE, 47439981965312, 47439981977599,
	1483	+STORE, 47439981977600, 47439982129151,
	1484	+STORE, 47439982075904, 47439982129151,
	1485	+STORE, 47439981977600, 47439982075903,
	1486	+ERASE, 47439981977600, 47439982075903,
	1487	+STORE, 47439981977600, 47439982075903,
	1488	+STORE, 47439982120960, 47439982129151,
	1489	+STORE, 47439982075904, 47439982120959,
	1490	+ERASE, 47439982075904, 47439982120959,
	1491	+STORE, 47439982075904, 47439982129151,
	1492	+ERASE, 47439982075904, 47439982129151,
	1493	+STORE, 47439982075904, 47439982120959,
	1494	+STORE, 47439982120960, 47439982129151,
	1495	+ERASE, 47439982120960, 47439982129151,
	1496	+STORE, 47439982120960, 47439982129151,
	1497	+STORE, 47439982129152, 47439985180671,
	1498	+STORE, 47439982673920, 47439985180671,
	1499	+STORE, 47439982129152, 47439982673919,
	1500	+ERASE, 47439982673920, 47439985180671,
	1501	+STORE, 47439982673920, 47439984959487,
	1502	+STORE, 47439984959488, 47439985180671,
	1503	+STORE, 47439984369664, 47439984959487,
	1504	+STORE, 47439982673920, 47439984369663,
	1505	+ERASE, 47439982673920, 47439984369663,
	1506	+STORE, 47439982673920, 47439984369663,
	1507	+STORE, 47439984955392, 47439984959487,
	1508	+STORE, 47439984369664, 47439984955391,
	1509	+ERASE, 47439984369664, 47439984955391,
	1510	+STORE, 47439984369664, 47439984955391,
	1511	+STORE, 47439985164288, 47439985180671,
	1512	+STORE, 47439984959488, 47439985164287,
	1513	+ERASE, 47439984959488, 47439985164287,
	1514	+STORE, 47439984959488, 47439985164287,
	1515	+ERASE, 47439985164288, 47439985180671,
	1516	+STORE, 47439985164288, 47439985180671,
	1517	+STORE, 47439985180672, 47439987019775,
	1518	+STORE, 47439985319936, 47439987019775,
	1519	+STORE, 47439985180672, 47439985319935,
	1520	+ERASE, 47439985319936, 47439987019775,
	1521	+STORE, 47439985319936, 47439986978815,
	1522	+STORE, 47439986978816, 47439987019775,
	1523	+STORE, 47439986663424, 47439986978815,
	1524	+STORE, 47439985319936, 47439986663423,
	1525	+ERASE, 47439985319936, 47439986663423,
	1526	+STORE, 47439985319936, 47439986663423,
	1527	+STORE, 47439986974720, 47439986978815,
	1528	+STORE, 47439986663424, 47439986974719,
	1529	+ERASE, 47439986663424, 47439986974719,
	1530	+STORE, 47439986663424, 47439986974719,
	1531	+STORE, 47439987003392, 47439987019775,
	1532	+STORE, 47439986978816, 47439987003391,
	1533	+ERASE, 47439986978816, 47439987003391,
	1534	+STORE, 47439986978816, 47439987003391,
	1535	+ERASE, 47439987003392, 47439987019775,
	1536	+STORE, 47439987003392, 47439987019775,
	1537	+STORE, 47439987019776, 47439987154943,
	1538	+ERASE, 47439987019776, 47439987154943,
	1539	+STORE, 47439987019776, 47439987044351,
	1540	+STORE, 47439987044352, 47439987154943,
	1541	+STORE, 47439987105792, 47439987154943,
	1542	+STORE, 47439987044352, 47439987105791,
	1543	+ERASE, 47439987044352, 47439987105791,
	1544	+STORE, 47439987044352, 47439987105791,
	1545	+STORE, 47439987130368, 47439987154943,
	1546	+STORE, 47439987105792, 47439987130367,
	1547	+ERASE, 47439987105792, 47439987130367,
	1548	+STORE, 47439987105792, 47439987154943,
	1549	+ERASE, 47439987105792, 47439987154943,
	1550	+STORE, 47439987105792, 47439987130367,
	1551	+STORE, 47439987130368, 47439987154943,
	1552	+STORE, 47439987138560, 47439987154943,
	1553	+STORE, 47439987130368, 47439987138559,
	1554	+ERASE, 47439987130368, 47439987138559,
	1555	+STORE, 47439987130368, 47439987138559,
	1556	+ERASE, 47439987138560, 47439987154943,
	1557	+STORE, 47439987138560, 47439987154943,
	1558	+STORE, 47439987154944, 47439987175423,
	1559	+ERASE, 47439987154944, 47439987175423,
	1560	+STORE, 47439987154944, 47439987159039,
	1561	+STORE, 47439987159040, 47439987175423,
	1562	+STORE, 47439987163136, 47439987175423,
	1563	+STORE, 47439987159040, 47439987163135,
	1564	+ERASE, 47439987159040, 47439987163135,
	1565	+STORE, 47439987159040, 47439987163135,
	1566	+STORE, 47439987167232, 47439987175423,
	1567	+STORE, 47439987163136, 47439987167231,
	1568	+ERASE, 47439987163136, 47439987167231,
	1569	+STORE, 47439987163136, 47439987175423,
	1570	+ERASE, 47439987163136, 47439987175423,
	1571	+STORE, 47439987163136, 47439987167231,
	1572	+STORE, 47439987167232, 47439987175423,
	1573	+ERASE, 47439987167232, 47439987175423,
	1574	+STORE, 47439987167232, 47439987175423,
	1575	+STORE, 47439987175424, 47439987183615,
	1576	+ERASE, 47439986978816, 47439987003391,
	1577	+STORE, 47439986978816, 47439986995199,
	1578	+STORE, 47439986995200, 47439987003391,
	1579	+ERASE, 47439987167232, 47439987175423,
	1580	+STORE, 47439987167232, 47439987171327,
	1581	+STORE, 47439987171328, 47439987175423,
	1582	+ERASE, 47439987130368, 47439987138559,
	1583	+STORE, 47439987130368, 47439987134463,
	1584	+STORE, 47439987134464, 47439987138559,
	1585	+ };
	1586	+ unsigned long set8[] = {
	1587	+STORE, 140737488347136, 140737488351231,
	1588	+STORE, 140722482974720, 140737488351231,
	1589	+ERASE, 140722482974720, 140737488351231,
	1590	+STORE, 140722482974720, 140722482978815,
	1591	+STORE, 94121505034240, 94121505206271,
	1592	+ERASE, 94121505034240, 94121505206271,
	1593	+STORE, 94121505034240, 94121505050623,
	1594	+STORE, 94121505050624, 94121505206271,
	1595	+ERASE, 94121505050624, 94121505206271,
	1596	+STORE, 94121505050624, 94121505153023,
	1597	+STORE, 94121505153024, 94121505193983,
	1598	+STORE, 94121505193984, 94121505206271,
	1599	+STORE, 47708483284992, 47708483457023,
	1600	+ERASE, 47708483284992, 47708483457023,
	1601	+STORE, 47708483284992, 47708483289087,
	1602	+STORE, 47708483289088, 47708483457023,
	1603	+ERASE, 47708483289088, 47708483457023,
	1604	+STORE, 47708483289088, 47708483411967,
	1605	+STORE, 47708483411968, 47708483444735,
	1606	+STORE, 47708483444736, 47708483452927,
	1607	+STORE, 47708483452928, 47708483457023,
	1608	+STORE, 140722483142656, 140722483146751,
	1609	+STORE, 140722483130368, 140722483142655,
	1610	+STORE, 47708483457024, 47708483465215,
	1611	+STORE, 47708483465216, 47708483473407,
	1612	+STORE, 47708483473408, 47708483637247,
	1613	+ERASE, 47708483473408, 47708483637247,
	1614	+STORE, 47708483473408, 47708483485695,
	1615	+STORE, 47708483485696, 47708483637247,
	1616	+STORE, 47708483584000, 47708483637247,
	1617	+STORE, 47708483485696, 47708483583999,
	1618	+ERASE, 47708483485696, 47708483583999,
	1619	+STORE, 47708483485696, 47708483583999,
	1620	+STORE, 47708483629056, 47708483637247,
	1621	+STORE, 47708483584000, 47708483629055,
	1622	+ERASE, 47708483584000, 47708483629055,
	1623	+STORE, 47708483584000, 47708483637247,
	1624	+ERASE, 47708483584000, 47708483637247,
	1625	+STORE, 47708483584000, 47708483629055,
	1626	+STORE, 47708483629056, 47708483637247,
	1627	+ERASE, 47708483629056, 47708483637247,
	1628	+STORE, 47708483629056, 47708483637247,
	1629	+STORE, 47708483637248, 47708486688767,
	1630	+STORE, 47708484182016, 47708486688767,
	1631	+STORE, 47708483637248, 47708484182015,
	1632	+ERASE, 47708484182016, 47708486688767,
	1633	+STORE, 47708484182016, 47708486467583,
	1634	+STORE, 47708486467584, 47708486688767,
	1635	+STORE, 47708485877760, 47708486467583,
	1636	+STORE, 47708484182016, 47708485877759,
	1637	+ERASE, 47708484182016, 47708485877759,
	1638	+STORE, 47708484182016, 47708485877759,
	1639	+STORE, 47708486463488, 47708486467583,
	1640	+STORE, 47708485877760, 47708486463487,
	1641	+ERASE, 47708485877760, 47708486463487,
	1642	+STORE, 47708485877760, 47708486463487,
	1643	+STORE, 47708486672384, 47708486688767,
	1644	+STORE, 47708486467584, 47708486672383,
	1645	+ERASE, 47708486467584, 47708486672383,
	1646	+STORE, 47708486467584, 47708486672383,
	1647	+ERASE, 47708486672384, 47708486688767,
	1648	+STORE, 47708486672384, 47708486688767,
	1649	+STORE, 47708486688768, 47708488527871,
	1650	+STORE, 47708486828032, 47708488527871,
	1651	+STORE, 47708486688768, 47708486828031,
	1652	+ERASE, 47708486828032, 47708488527871,
	1653	+STORE, 47708486828032, 47708488486911,
	1654	+STORE, 47708488486912, 47708488527871,
	1655	+STORE, 47708488171520, 47708488486911,
	1656	+STORE, 47708486828032, 47708488171519,
	1657	+ERASE, 47708486828032, 47708488171519,
	1658	+STORE, 47708486828032, 47708488171519,
	1659	+STORE, 47708488482816, 47708488486911,
	1660	+STORE, 47708488171520, 47708488482815,
	1661	+ERASE, 47708488171520, 47708488482815,
	1662	+STORE, 47708488171520, 47708488482815,
	1663	+STORE, 47708488511488, 47708488527871,
	1664	+STORE, 47708488486912, 47708488511487,
	1665	+ERASE, 47708488486912, 47708488511487,
	1666	+STORE, 47708488486912, 47708488511487,
	1667	+ERASE, 47708488511488, 47708488527871,
	1668	+STORE, 47708488511488, 47708488527871,
	1669	+STORE, 47708488527872, 47708488663039,
	1670	+ERASE, 47708488527872, 47708488663039,
	1671	+STORE, 47708488527872, 47708488552447,
	1672	+STORE, 47708488552448, 47708488663039,
	1673	+STORE, 47708488613888, 47708488663039,
	1674	+STORE, 47708488552448, 47708488613887,
	1675	+ERASE, 47708488552448, 47708488613887,
	1676	+STORE, 47708488552448, 47708488613887,
	1677	+STORE, 47708488638464, 47708488663039,
	1678	+STORE, 47708488613888, 47708488638463,
	1679	+ERASE, 47708488613888, 47708488638463,
	1680	+STORE, 47708488613888, 47708488663039,
	1681	+ERASE, 47708488613888, 47708488663039,
	1682	+STORE, 47708488613888, 47708488638463,
	1683	+STORE, 47708488638464, 47708488663039,
	1684	+STORE, 47708488646656, 47708488663039,
	1685	+STORE, 47708488638464, 47708488646655,
	1686	+ERASE, 47708488638464, 47708488646655,
	1687	+STORE, 47708488638464, 47708488646655,
	1688	+ERASE, 47708488646656, 47708488663039,
	1689	+STORE, 47708488646656, 47708488663039,
	1690	+STORE, 47708488663040, 47708488683519,
	1691	+ERASE, 47708488663040, 47708488683519,
	1692	+STORE, 47708488663040, 47708488667135,
	1693	+STORE, 47708488667136, 47708488683519,
	1694	+STORE, 47708488671232, 47708488683519,
	1695	+STORE, 47708488667136, 47708488671231,
	1696	+ERASE, 47708488667136, 47708488671231,
	1697	+STORE, 47708488667136, 47708488671231,
	1698	+STORE, 47708488675328, 47708488683519,
	1699	+STORE, 47708488671232, 47708488675327,
	1700	+ERASE, 47708488671232, 47708488675327,
	1701	+STORE, 47708488671232, 47708488683519,
	1702	+ERASE, 47708488671232, 47708488683519,
	1703	+STORE, 47708488671232, 47708488675327,
	1704	+STORE, 47708488675328, 47708488683519,
	1705	+ERASE, 47708488675328, 47708488683519,
	1706	+STORE, 47708488675328, 47708488683519,
	1707	+STORE, 47708488683520, 47708488691711,
	1708	+ERASE, 47708488486912, 47708488511487,
	1709	+STORE, 47708488486912, 47708488503295,
	1710	+STORE, 47708488503296, 47708488511487,
	1711	+ERASE, 47708488675328, 47708488683519,
	1712	+STORE, 47708488675328, 47708488679423,
	1713	+STORE, 47708488679424, 47708488683519,
	1714	+ERASE, 47708488638464, 47708488646655,
	1715	+STORE, 47708488638464, 47708488642559,
	1716	+STORE, 47708488642560, 47708488646655,
	1717	+ };
	1718	+
	1719	+ unsigned long set9[] = {
	1720	+STORE, 140737488347136, 140737488351231,
	1721	+STORE, 140736427839488, 140737488351231,
	1722	+ERASE, 140736427839488, 140736427839488,
	1723	+STORE, 140736427839488, 140736427843583,
	1724	+STORE, 94071213395968, 94071213567999,
	1725	+ERASE, 94071213395968, 94071213395968,
	1726	+STORE, 94071213395968, 94071213412351,
	1727	+STORE, 94071213412352, 94071213567999,
	1728	+ERASE, 94071213412352, 94071213412352,
	1729	+STORE, 94071213412352, 94071213514751,
	1730	+STORE, 94071213514752, 94071213555711,
	1731	+STORE, 94071213555712, 94071213567999,
	1732	+STORE, 139968410644480, 139968410816511,
	1733	+ERASE, 139968410644480, 139968410644480,
	1734	+STORE, 139968410644480, 139968410648575,
	1735	+STORE, 139968410648576, 139968410816511,
	1736	+ERASE, 139968410648576, 139968410648576,
	1737	+STORE, 139968410648576, 139968410771455,
	1738	+STORE, 139968410771456, 139968410804223,
	1739	+STORE, 139968410804224, 139968410812415,
	1740	+STORE, 139968410812416, 139968410816511,
	1741	+STORE, 140736429277184, 140736429281279,
	1742	+STORE, 140736429264896, 140736429277183,
	1743	+STORE, 47664384352256, 47664384360447,
	1744	+STORE, 47664384360448, 47664384368639,
	1745	+STORE, 47664384368640, 47664384532479,
	1746	+ERASE, 47664384368640, 47664384368640,
	1747	+STORE, 47664384368640, 47664384380927,
	1748	+STORE, 47664384380928, 47664384532479,
	1749	+STORE, 47664384479232, 47664384532479,
	1750	+STORE, 47664384380928, 47664384479231,
	1751	+ERASE, 47664384380928, 47664384380928,
	1752	+STORE, 47664384380928, 47664384479231,
	1753	+STORE, 47664384524288, 47664384532479,
	1754	+STORE, 47664384479232, 47664384524287,
	1755	+ERASE, 47664384479232, 47664384479232,
	1756	+STORE, 47664384479232, 47664384532479,
	1757	+ERASE, 47664384479232, 47664384479232,
	1758	+STORE, 47664384479232, 47664384524287,
	1759	+STORE, 47664384524288, 47664384532479,
	1760	+ERASE, 47664384524288, 47664384524288,
	1761	+STORE, 47664384524288, 47664384532479,
	1762	+STORE, 47664384532480, 47664387583999,
	1763	+STORE, 47664385077248, 47664387583999,
	1764	+STORE, 47664384532480, 47664385077247,
	1765	+ERASE, 47664385077248, 47664385077248,
	1766	+STORE, 47664385077248, 47664387362815,
	1767	+STORE, 47664387362816, 47664387583999,
	1768	+STORE, 47664386772992, 47664387362815,
	1769	+STORE, 47664385077248, 47664386772991,
	1770	+ERASE, 47664385077248, 47664385077248,
	1771	+STORE, 47664385077248, 47664386772991,
	1772	+STORE, 47664387358720, 47664387362815,
	1773	+STORE, 47664386772992, 47664387358719,
	1774	+ERASE, 47664386772992, 47664386772992,
	1775	+STORE, 47664386772992, 47664387358719,
	1776	+STORE, 47664387567616, 47664387583999,
	1777	+STORE, 47664387362816, 47664387567615,
	1778	+ERASE, 47664387362816, 47664387362816,
	1779	+STORE, 47664387362816, 47664387567615,
	1780	+ERASE, 47664387567616, 47664387567616,
	1781	+STORE, 47664387567616, 47664387583999,
	1782	+STORE, 47664387584000, 47664389423103,
	1783	+STORE, 47664387723264, 47664389423103,
	1784	+STORE, 47664387584000, 47664387723263,
	1785	+ERASE, 47664387723264, 47664387723264,
	1786	+STORE, 47664387723264, 47664389382143,
	1787	+STORE, 47664389382144, 47664389423103,
	1788	+STORE, 47664389066752, 47664389382143,
	1789	+STORE, 47664387723264, 47664389066751,
	1790	+ERASE, 47664387723264, 47664387723264,
	1791	+STORE, 47664387723264, 47664389066751,
	1792	+STORE, 47664389378048, 47664389382143,
	1793	+STORE, 47664389066752, 47664389378047,
	1794	+ERASE, 47664389066752, 47664389066752,
	1795	+STORE, 47664389066752, 47664389378047,
	1796	+STORE, 47664389406720, 47664389423103,
	1797	+STORE, 47664389382144, 47664389406719,
	1798	+ERASE, 47664389382144, 47664389382144,
	1799	+STORE, 47664389382144, 47664389406719,
	1800	+ERASE, 47664389406720, 47664389406720,
	1801	+STORE, 47664389406720, 47664389423103,
	1802	+STORE, 47664389423104, 47664389558271,
	1803	+ERASE, 47664389423104, 47664389423104,
	1804	+STORE, 47664389423104, 47664389447679,
	1805	+STORE, 47664389447680, 47664389558271,
	1806	+STORE, 47664389509120, 47664389558271,
	1807	+STORE, 47664389447680, 47664389509119,
	1808	+ERASE, 47664389447680, 47664389447680,
	1809	+STORE, 47664389447680, 47664389509119,
	1810	+STORE, 47664389533696, 47664389558271,
	1811	+STORE, 47664389509120, 47664389533695,
	1812	+ERASE, 47664389509120, 47664389509120,
	1813	+STORE, 47664389509120, 47664389558271,
	1814	+ERASE, 47664389509120, 47664389509120,
	1815	+STORE, 47664389509120, 47664389533695,
	1816	+STORE, 47664389533696, 47664389558271,
	1817	+STORE, 47664389541888, 47664389558271,
	1818	+STORE, 47664389533696, 47664389541887,
	1819	+ERASE, 47664389533696, 47664389533696,
	1820	+STORE, 47664389533696, 47664389541887,
	1821	+ERASE, 47664389541888, 47664389541888,
	1822	+STORE, 47664389541888, 47664389558271,
	1823	+STORE, 47664389558272, 47664389578751,
	1824	+ERASE, 47664389558272, 47664389558272,
	1825	+STORE, 47664389558272, 47664389562367,
	1826	+STORE, 47664389562368, 47664389578751,
	1827	+STORE, 47664389566464, 47664389578751,
	1828	+STORE, 47664389562368, 47664389566463,
	1829	+ERASE, 47664389562368, 47664389562368,
	1830	+STORE, 47664389562368, 47664389566463,
	1831	+STORE, 47664389570560, 47664389578751,
	1832	+STORE, 47664389566464, 47664389570559,
	1833	+ERASE, 47664389566464, 47664389566464,
	1834	+STORE, 47664389566464, 47664389578751,
	1835	+ERASE, 47664389566464, 47664389566464,
	1836	+STORE, 47664389566464, 47664389570559,
	1837	+STORE, 47664389570560, 47664389578751,
	1838	+ERASE, 47664389570560, 47664389570560,
	1839	+STORE, 47664389570560, 47664389578751,
	1840	+STORE, 47664389578752, 47664389586943,
	1841	+ERASE, 47664389382144, 47664389382144,
	1842	+STORE, 47664389382144, 47664389398527,
	1843	+STORE, 47664389398528, 47664389406719,
	1844	+ERASE, 47664389570560, 47664389570560,
	1845	+STORE, 47664389570560, 47664389574655,
	1846	+STORE, 47664389574656, 47664389578751,
	1847	+ERASE, 47664389533696, 47664389533696,
	1848	+STORE, 47664389533696, 47664389537791,
	1849	+STORE, 47664389537792, 47664389541887,
	1850	+ERASE, 47664387362816, 47664387362816,
	1851	+STORE, 47664387362816, 47664387559423,
	1852	+STORE, 47664387559424, 47664387567615,
	1853	+ERASE, 47664384524288, 47664384524288,
	1854	+STORE, 47664384524288, 47664384528383,
	1855	+STORE, 47664384528384, 47664384532479,
	1856	+ERASE, 94071213555712, 94071213555712,
	1857	+STORE, 94071213555712, 94071213563903,
	1858	+STORE, 94071213563904, 94071213567999,
	1859	+ERASE, 139968410804224, 139968410804224,
	1860	+STORE, 139968410804224, 139968410808319,
	1861	+STORE, 139968410808320, 139968410812415,
	1862	+ERASE, 47664384352256, 47664384352256,
	1863	+STORE, 94071244402688, 94071244537855,
	1864	+STORE, 140737488347136, 140737488351231,
	1865	+STORE, 140728271503360, 140737488351231,
	1866	+ERASE, 140728271503360, 140728271503360,
	1867	+STORE, 140728271503360, 140728271507455,
	1868	+STORE, 94410361982976, 94410362155007,
	1869	+ERASE, 94410361982976, 94410361982976,
	1870	+STORE, 94410361982976, 94410361999359,
	1871	+STORE, 94410361999360, 94410362155007,
	1872	+ERASE, 94410361999360, 94410361999360,
	1873	+STORE, 94410361999360, 94410362101759,
	1874	+STORE, 94410362101760, 94410362142719,
	1875	+STORE, 94410362142720, 94410362155007,
	1876	+STORE, 140351953997824, 140351954169855,
	1877	+ERASE, 140351953997824, 140351953997824,
	1878	+STORE, 140351953997824, 140351954001919,
	1879	+STORE, 140351954001920, 140351954169855,
	1880	+ERASE, 140351954001920, 140351954001920,
	1881	+STORE, 140351954001920, 140351954124799,
	1882	+STORE, 140351954124800, 140351954157567,
	1883	+STORE, 140351954157568, 140351954165759,
	1884	+STORE, 140351954165760, 140351954169855,
	1885	+STORE, 140728272429056, 140728272433151,
	1886	+STORE, 140728272416768, 140728272429055,
	1887	+STORE, 47280840998912, 47280841007103,
	1888	+STORE, 47280841007104, 47280841015295,
	1889	+STORE, 47280841015296, 47280841179135,
	1890	+ERASE, 47280841015296, 47280841015296,
	1891	+STORE, 47280841015296, 47280841027583,
	1892	+STORE, 47280841027584, 47280841179135,
	1893	+STORE, 47280841125888, 47280841179135,
	1894	+STORE, 47280841027584, 47280841125887,
	1895	+ERASE, 47280841027584, 47280841027584,
	1896	+STORE, 47280841027584, 47280841125887,
	1897	+STORE, 47280841170944, 47280841179135,
	1898	+STORE, 47280841125888, 47280841170943,
	1899	+ERASE, 47280841125888, 47280841125888,
	1900	+STORE, 47280841125888, 47280841179135,
	1901	+ERASE, 47280841125888, 47280841125888,
	1902	+STORE, 47280841125888, 47280841170943,
	1903	+STORE, 47280841170944, 47280841179135,
	1904	+ERASE, 47280841170944, 47280841170944,
	1905	+STORE, 47280841170944, 47280841179135,
	1906	+STORE, 47280841179136, 47280844230655,
	1907	+STORE, 47280841723904, 47280844230655,
	1908	+STORE, 47280841179136, 47280841723903,
	1909	+ERASE, 47280841723904, 47280841723904,
	1910	+STORE, 47280841723904, 47280844009471,
	1911	+STORE, 47280844009472, 47280844230655,
	1912	+STORE, 47280843419648, 47280844009471,
	1913	+STORE, 47280841723904, 47280843419647,
	1914	+ERASE, 47280841723904, 47280841723904,
	1915	+STORE, 47280841723904, 47280843419647,
	1916	+STORE, 47280844005376, 47280844009471,
	1917	+STORE, 47280843419648, 47280844005375,
	1918	+ERASE, 47280843419648, 47280843419648,
	1919	+STORE, 47280843419648, 47280844005375,
	1920	+STORE, 47280844214272, 47280844230655,
	1921	+STORE, 47280844009472, 47280844214271,
	1922	+ERASE, 47280844009472, 47280844009472,
	1923	+STORE, 47280844009472, 47280844214271,
	1924	+ERASE, 47280844214272, 47280844214272,
	1925	+STORE, 47280844214272, 47280844230655,
	1926	+STORE, 47280844230656, 47280846069759,
	1927	+STORE, 47280844369920, 47280846069759,
	1928	+STORE, 47280844230656, 47280844369919,
	1929	+ERASE, 47280844369920, 47280844369920,
	1930	+STORE, 47280844369920, 47280846028799,
	1931	+STORE, 47280846028800, 47280846069759,
	1932	+STORE, 47280845713408, 47280846028799,
	1933	+STORE, 47280844369920, 47280845713407,
	1934	+ERASE, 47280844369920, 47280844369920,
	1935	+STORE, 47280844369920, 47280845713407,
	1936	+STORE, 47280846024704, 47280846028799,
	1937	+STORE, 47280845713408, 47280846024703,
	1938	+ERASE, 47280845713408, 47280845713408,
	1939	+STORE, 47280845713408, 47280846024703,
	1940	+STORE, 47280846053376, 47280846069759,
	1941	+STORE, 47280846028800, 47280846053375,
	1942	+ERASE, 47280846028800, 47280846028800,
	1943	+STORE, 47280846028800, 47280846053375,
	1944	+ERASE, 47280846053376, 47280846053376,
	1945	+STORE, 47280846053376, 47280846069759,
	1946	+STORE, 47280846069760, 47280846204927,
	1947	+ERASE, 47280846069760, 47280846069760,
	1948	+STORE, 47280846069760, 47280846094335,
	1949	+STORE, 47280846094336, 47280846204927,
	1950	+STORE, 47280846155776, 47280846204927,
	1951	+STORE, 47280846094336, 47280846155775,
	1952	+ERASE, 47280846094336, 47280846094336,
	1953	+STORE, 47280846094336, 47280846155775,
	1954	+STORE, 47280846180352, 47280846204927,
	1955	+STORE, 47280846155776, 47280846180351,
	1956	+ERASE, 47280846155776, 47280846155776,
	1957	+STORE, 47280846155776, 47280846204927,
	1958	+ERASE, 47280846155776, 47280846155776,
	1959	+STORE, 47280846155776, 47280846180351,
	1960	+STORE, 47280846180352, 47280846204927,
	1961	+STORE, 47280846188544, 47280846204927,
	1962	+STORE, 47280846180352, 47280846188543,
	1963	+ERASE, 47280846180352, 47280846180352,
	1964	+STORE, 47280846180352, 47280846188543,
	1965	+ERASE, 47280846188544, 47280846188544,
	1966	+STORE, 47280846188544, 47280846204927,
	1967	+STORE, 47280846204928, 47280846225407,
	1968	+ERASE, 47280846204928, 47280846204928,
	1969	+STORE, 47280846204928, 47280846209023,
	1970	+STORE, 47280846209024, 47280846225407,
	1971	+STORE, 47280846213120, 47280846225407,
	1972	+STORE, 47280846209024, 47280846213119,
	1973	+ERASE, 47280846209024, 47280846209024,
	1974	+STORE, 47280846209024, 47280846213119,
	1975	+STORE, 47280846217216, 47280846225407,
	1976	+STORE, 47280846213120, 47280846217215,
	1977	+ERASE, 47280846213120, 47280846213120,
	1978	+STORE, 47280846213120, 47280846225407,
	1979	+ERASE, 47280846213120, 47280846213120,
	1980	+STORE, 47280846213120, 47280846217215,
	1981	+STORE, 47280846217216, 47280846225407,
	1982	+ERASE, 47280846217216, 47280846217216,
	1983	+STORE, 47280846217216, 47280846225407,
	1984	+STORE, 47280846225408, 47280846233599,
	1985	+ERASE, 47280846028800, 47280846028800,
	1986	+STORE, 47280846028800, 47280846045183,
	1987	+STORE, 47280846045184, 47280846053375,
	1988	+ERASE, 47280846217216, 47280846217216,
	1989	+STORE, 47280846217216, 47280846221311,
	1990	+STORE, 47280846221312, 47280846225407,
	1991	+ERASE, 47280846180352, 47280846180352,
	1992	+STORE, 47280846180352, 47280846184447,
	1993	+STORE, 47280846184448, 47280846188543,
	1994	+ERASE, 47280844009472, 47280844009472,
	1995	+STORE, 47280844009472, 47280844206079,
	1996	+STORE, 47280844206080, 47280844214271,
	1997	+ERASE, 47280841170944, 47280841170944,
	1998	+STORE, 47280841170944, 47280841175039,
	1999	+STORE, 47280841175040, 47280841179135,
	2000	+ERASE, 94410362142720, 94410362142720,
	2001	+STORE, 94410362142720, 94410362150911,
	2002	+STORE, 94410362150912, 94410362155007,
	2003	+ERASE, 140351954157568, 140351954157568,
	2004	+STORE, 140351954157568, 140351954161663,
	2005	+STORE, 140351954161664, 140351954165759,
	2006	+ERASE, 47280840998912, 47280840998912,
	2007	+STORE, 94410379456512, 94410379591679,
	2008	+STORE, 140737488347136, 140737488351231,
	2009	+STORE, 140732946362368, 140737488351231,
	2010	+ERASE, 140732946362368, 140732946362368,
	2011	+STORE, 140732946362368, 140732946366463,
	2012	+STORE, 94352937934848, 94352938106879,
	2013	+ERASE, 94352937934848, 94352937934848,
	2014	+STORE, 94352937934848, 94352937951231,
	2015	+STORE, 94352937951232, 94352938106879,
	2016	+ERASE, 94352937951232, 94352937951232,
	2017	+STORE, 94352937951232, 94352938053631,
	2018	+STORE, 94352938053632, 94352938094591,
	2019	+STORE, 94352938094592, 94352938106879,
	2020	+STORE, 140595518742528, 140595518914559,
	2021	+ERASE, 140595518742528, 140595518742528,
	2022	+STORE, 140595518742528, 140595518746623,
	2023	+STORE, 140595518746624, 140595518914559,
	2024	+ERASE, 140595518746624, 140595518746624,
	2025	+STORE, 140595518746624, 140595518869503,
	2026	+STORE, 140595518869504, 140595518902271,
	2027	+STORE, 140595518902272, 140595518910463,
	2028	+STORE, 140595518910464, 140595518914559,
	2029	+STORE, 140732947468288, 140732947472383,
	2030	+STORE, 140732947456000, 140732947468287,
	2031	+STORE, 47037276254208, 47037276262399,
	2032	+STORE, 47037276262400, 47037276270591,
	2033	+STORE, 47037276270592, 47037276434431,
	2034	+ERASE, 47037276270592, 47037276270592,
	2035	+STORE, 47037276270592, 47037276282879,
	2036	+STORE, 47037276282880, 47037276434431,
	2037	+STORE, 47037276381184, 47037276434431,
	2038	+STORE, 47037276282880, 47037276381183,
	2039	+ERASE, 47037276282880, 47037276282880,
	2040	+STORE, 47037276282880, 47037276381183,
	2041	+STORE, 47037276426240, 47037276434431,
	2042	+STORE, 47037276381184, 47037276426239,
	2043	+ERASE, 47037276381184, 47037276381184,
	2044	+STORE, 47037276381184, 47037276434431,
	2045	+ERASE, 47037276381184, 47037276381184,
	2046	+STORE, 47037276381184, 47037276426239,
	2047	+STORE, 47037276426240, 47037276434431,
	2048	+ERASE, 47037276426240, 47037276426240,
	2049	+STORE, 47037276426240, 47037276434431,
	2050	+STORE, 47037276434432, 47037279485951,
	2051	+STORE, 47037276979200, 47037279485951,
	2052	+STORE, 47037276434432, 47037276979199,
	2053	+ERASE, 47037276979200, 47037276979200,
	2054	+STORE, 47037276979200, 47037279264767,
	2055	+STORE, 47037279264768, 47037279485951,
	2056	+STORE, 47037278674944, 47037279264767,
	2057	+STORE, 47037276979200, 47037278674943,
	2058	+ERASE, 47037276979200, 47037276979200,
	2059	+STORE, 47037276979200, 47037278674943,
	2060	+STORE, 47037279260672, 47037279264767,
	2061	+STORE, 47037278674944, 47037279260671,
	2062	+ERASE, 47037278674944, 47037278674944,
	2063	+STORE, 47037278674944, 47037279260671,
	2064	+STORE, 47037279469568, 47037279485951,
	2065	+STORE, 47037279264768, 47037279469567,
	2066	+ERASE, 47037279264768, 47037279264768,
	2067	+STORE, 47037279264768, 47037279469567,
	2068	+ERASE, 47037279469568, 47037279469568,
	2069	+STORE, 47037279469568, 47037279485951,
	2070	+STORE, 47037279485952, 47037281325055,
	2071	+STORE, 47037279625216, 47037281325055,
	2072	+STORE, 47037279485952, 47037279625215,
	2073	+ERASE, 47037279625216, 47037279625216,
	2074	+STORE, 47037279625216, 47037281284095,
	2075	+STORE, 47037281284096, 47037281325055,
	2076	+STORE, 47037280968704, 47037281284095,
	2077	+STORE, 47037279625216, 47037280968703,
	2078	+ERASE, 47037279625216, 47037279625216,
	2079	+STORE, 47037279625216, 47037280968703,
	2080	+STORE, 47037281280000, 47037281284095,
	2081	+STORE, 47037280968704, 47037281279999,
	2082	+ERASE, 47037280968704, 47037280968704,
	2083	+STORE, 47037280968704, 47037281279999,
	2084	+STORE, 47037281308672, 47037281325055,
	2085	+STORE, 47037281284096, 47037281308671,
	2086	+ERASE, 47037281284096, 47037281284096,
	2087	+STORE, 47037281284096, 47037281308671,
	2088	+ERASE, 47037281308672, 47037281308672,
	2089	+STORE, 47037281308672, 47037281325055,
	2090	+STORE, 47037281325056, 47037281460223,
	2091	+ERASE, 47037281325056, 47037281325056,
	2092	+STORE, 47037281325056, 47037281349631,
	2093	+STORE, 47037281349632, 47037281460223,
	2094	+STORE, 47037281411072, 47037281460223,
	2095	+STORE, 47037281349632, 47037281411071,
	2096	+ERASE, 47037281349632, 47037281349632,
	2097	+STORE, 47037281349632, 47037281411071,
	2098	+STORE, 47037281435648, 47037281460223,
	2099	+STORE, 47037281411072, 47037281435647,
	2100	+ERASE, 47037281411072, 47037281411072,
	2101	+STORE, 47037281411072, 47037281460223,
	2102	+ERASE, 47037281411072, 47037281411072,
	2103	+STORE, 47037281411072, 47037281435647,
	2104	+STORE, 47037281435648, 47037281460223,
	2105	+STORE, 47037281443840, 47037281460223,
	2106	+STORE, 47037281435648, 47037281443839,
	2107	+ERASE, 47037281435648, 47037281435648,
	2108	+STORE, 47037281435648, 47037281443839,
	2109	+ERASE, 47037281443840, 47037281443840,
	2110	+STORE, 47037281443840, 47037281460223,
	2111	+STORE, 47037281460224, 47037281480703,
	2112	+ERASE, 47037281460224, 47037281460224,
	2113	+STORE, 47037281460224, 47037281464319,
	2114	+STORE, 47037281464320, 47037281480703,
	2115	+STORE, 47037281468416, 47037281480703,
	2116	+STORE, 47037281464320, 47037281468415,
	2117	+ERASE, 47037281464320, 47037281464320,
	2118	+STORE, 47037281464320, 47037281468415,
	2119	+STORE, 47037281472512, 47037281480703,
	2120	+STORE, 47037281468416, 47037281472511,
	2121	+ERASE, 47037281468416, 47037281468416,
	2122	+STORE, 47037281468416, 47037281480703,
	2123	+ERASE, 47037281468416, 47037281468416,
	2124	+STORE, 47037281468416, 47037281472511,
	2125	+STORE, 47037281472512, 47037281480703,
	2126	+ERASE, 47037281472512, 47037281472512,
	2127	+STORE, 47037281472512, 47037281480703,
	2128	+STORE, 47037281480704, 47037281488895,
	2129	+ERASE, 47037281284096, 47037281284096,
	2130	+STORE, 47037281284096, 47037281300479,
	2131	+STORE, 47037281300480, 47037281308671,
	2132	+ERASE, 47037281472512, 47037281472512,
	2133	+STORE, 47037281472512, 47037281476607,
	2134	+STORE, 47037281476608, 47037281480703,
	2135	+ERASE, 47037281435648, 47037281435648,
	2136	+STORE, 47037281435648, 47037281439743,
	2137	+STORE, 47037281439744, 47037281443839,
	2138	+ERASE, 47037279264768, 47037279264768,
	2139	+STORE, 47037279264768, 47037279461375,
	2140	+STORE, 47037279461376, 47037279469567,
	2141	+ERASE, 47037276426240, 47037276426240,
	2142	+STORE, 47037276426240, 47037276430335,
	2143	+STORE, 47037276430336, 47037276434431,
	2144	+ERASE, 94352938094592, 94352938094592,
	2145	+STORE, 94352938094592, 94352938102783,
	2146	+STORE, 94352938102784, 94352938106879,
	2147	+ERASE, 140595518902272, 140595518902272,
	2148	+STORE, 140595518902272, 140595518906367,
	2149	+STORE, 140595518906368, 140595518910463,
	2150	+ERASE, 47037276254208, 47037276254208,
	2151	+STORE, 94352938438656, 94352938573823,
	2152	+STORE, 140737488347136, 140737488351231,
	2153	+STORE, 140733506027520, 140737488351231,
	2154	+ERASE, 140733506027520, 140733506027520,
	2155	+STORE, 140733506027520, 140733506031615,
	2156	+STORE, 94150123073536, 94150123245567,
	2157	+ERASE, 94150123073536, 94150123073536,
	2158	+STORE, 94150123073536, 94150123089919,
	2159	+STORE, 94150123089920, 94150123245567,
	2160	+ERASE, 94150123089920, 94150123089920,
	2161	+STORE, 94150123089920, 94150123192319,
	2162	+STORE, 94150123192320, 94150123233279,
	2163	+STORE, 94150123233280, 94150123245567,
	2164	+STORE, 140081290375168, 140081290547199,
	2165	+ERASE, 140081290375168, 140081290375168,
	2166	+STORE, 140081290375168, 140081290379263,
	2167	+STORE, 140081290379264, 140081290547199,
	2168	+ERASE, 140081290379264, 140081290379264,
	2169	+STORE, 140081290379264, 140081290502143,
	2170	+STORE, 140081290502144, 140081290534911,
	2171	+STORE, 140081290534912, 140081290543103,
	2172	+STORE, 140081290543104, 140081290547199,
	2173	+STORE, 140733506707456, 140733506711551,
	2174	+STORE, 140733506695168, 140733506707455,
	2175	+STORE, 47551504621568, 47551504629759,
	2176	+STORE, 47551504629760, 47551504637951,
	2177	+STORE, 47551504637952, 47551504801791,
	2178	+ERASE, 47551504637952, 47551504637952,
	2179	+STORE, 47551504637952, 47551504650239,
	2180	+STORE, 47551504650240, 47551504801791,
	2181	+STORE, 47551504748544, 47551504801791,
	2182	+STORE, 47551504650240, 47551504748543,
	2183	+ERASE, 47551504650240, 47551504650240,
	2184	+STORE, 47551504650240, 47551504748543,
	2185	+STORE, 47551504793600, 47551504801791,
	2186	+STORE, 47551504748544, 47551504793599,
	2187	+ERASE, 47551504748544, 47551504748544,
	2188	+STORE, 47551504748544, 47551504801791,
	2189	+ERASE, 47551504748544, 47551504748544,
	2190	+STORE, 47551504748544, 47551504793599,
	2191	+STORE, 47551504793600, 47551504801791,
	2192	+ERASE, 47551504793600, 47551504793600,
	2193	+STORE, 47551504793600, 47551504801791,
	2194	+STORE, 47551504801792, 47551507853311,
	2195	+STORE, 47551505346560, 47551507853311,
	2196	+STORE, 47551504801792, 47551505346559,
	2197	+ERASE, 47551505346560, 47551505346560,
	2198	+STORE, 47551505346560, 47551507632127,
	2199	+STORE, 47551507632128, 47551507853311,
	2200	+STORE, 47551507042304, 47551507632127,
	2201	+STORE, 47551505346560, 47551507042303,
	2202	+ERASE, 47551505346560, 47551505346560,
	2203	+STORE, 47551505346560, 47551507042303,
	2204	+STORE, 47551507628032, 47551507632127,
	2205	+STORE, 47551507042304, 47551507628031,
	2206	+ERASE, 47551507042304, 47551507042304,
	2207	+STORE, 47551507042304, 47551507628031,
	2208	+STORE, 47551507836928, 47551507853311,
	2209	+STORE, 47551507632128, 47551507836927,
	2210	+ERASE, 47551507632128, 47551507632128,
	2211	+STORE, 47551507632128, 47551507836927,
	2212	+ERASE, 47551507836928, 47551507836928,
	2213	+STORE, 47551507836928, 47551507853311,
	2214	+STORE, 47551507853312, 47551509692415,
	2215	+STORE, 47551507992576, 47551509692415,
	2216	+STORE, 47551507853312, 47551507992575,
	2217	+ERASE, 47551507992576, 47551507992576,
	2218	+STORE, 47551507992576, 47551509651455,
	2219	+STORE, 47551509651456, 47551509692415,
	2220	+STORE, 47551509336064, 47551509651455,
	2221	+STORE, 47551507992576, 47551509336063,
	2222	+ERASE, 47551507992576, 47551507992576,
	2223	+STORE, 47551507992576, 47551509336063,
	2224	+STORE, 47551509647360, 47551509651455,
	2225	+STORE, 47551509336064, 47551509647359,
	2226	+ERASE, 47551509336064, 47551509336064,
	2227	+STORE, 47551509336064, 47551509647359,
	2228	+STORE, 47551509676032, 47551509692415,
	2229	+STORE, 47551509651456, 47551509676031,
	2230	+ERASE, 47551509651456, 47551509651456,
	2231	+STORE, 47551509651456, 47551509676031,
	2232	+ERASE, 47551509676032, 47551509676032,
	2233	+STORE, 47551509676032, 47551509692415,
	2234	+STORE, 47551509692416, 47551509827583,
	2235	+ERASE, 47551509692416, 47551509692416,
	2236	+STORE, 47551509692416, 47551509716991,
	2237	+STORE, 47551509716992, 47551509827583,
	2238	+STORE, 47551509778432, 47551509827583,
	2239	+STORE, 47551509716992, 47551509778431,
	2240	+ERASE, 47551509716992, 47551509716992,
	2241	+STORE, 47551509716992, 47551509778431,
	2242	+STORE, 47551509803008, 47551509827583,
	2243	+STORE, 47551509778432, 47551509803007,
	2244	+ERASE, 47551509778432, 47551509778432,
	2245	+STORE, 47551509778432, 47551509827583,
	2246	+ERASE, 47551509778432, 47551509778432,
	2247	+STORE, 47551509778432, 47551509803007,
	2248	+STORE, 47551509803008, 47551509827583,
	2249	+STORE, 47551509811200, 47551509827583,
	2250	+STORE, 47551509803008, 47551509811199,
	2251	+ERASE, 47551509803008, 47551509803008,
	2252	+STORE, 47551509803008, 47551509811199,
	2253	+ERASE, 47551509811200, 47551509811200,
	2254	+STORE, 47551509811200, 47551509827583,
	2255	+STORE, 47551509827584, 47551509848063,
	2256	+ERASE, 47551509827584, 47551509827584,
	2257	+STORE, 47551509827584, 47551509831679,
	2258	+STORE, 47551509831680, 47551509848063,
	2259	+STORE, 47551509835776, 47551509848063,
	2260	+STORE, 47551509831680, 47551509835775,
	2261	+ERASE, 47551509831680, 47551509831680,
	2262	+STORE, 47551509831680, 47551509835775,
	2263	+STORE, 47551509839872, 47551509848063,
	2264	+STORE, 47551509835776, 47551509839871,
	2265	+ERASE, 47551509835776, 47551509835776,
	2266	+STORE, 47551509835776, 47551509848063,
	2267	+ERASE, 47551509835776, 47551509835776,
	2268	+STORE, 47551509835776, 47551509839871,
	2269	+STORE, 47551509839872, 47551509848063,
	2270	+ERASE, 47551509839872, 47551509839872,
	2271	+STORE, 47551509839872, 47551509848063,
	2272	+STORE, 47551509848064, 47551509856255,
	2273	+ERASE, 47551509651456, 47551509651456,
	2274	+STORE, 47551509651456, 47551509667839,
	2275	+STORE, 47551509667840, 47551509676031,
	2276	+ERASE, 47551509839872, 47551509839872,
	2277	+STORE, 47551509839872, 47551509843967,
	2278	+STORE, 47551509843968, 47551509848063,
	2279	+ERASE, 47551509803008, 47551509803008,
	2280	+STORE, 47551509803008, 47551509807103,
	2281	+STORE, 47551509807104, 47551509811199,
	2282	+ERASE, 47551507632128, 47551507632128,
	2283	+STORE, 47551507632128, 47551507828735,
	2284	+STORE, 47551507828736, 47551507836927,
	2285	+ERASE, 47551504793600, 47551504793600,
	2286	+STORE, 47551504793600, 47551504797695,
	2287	+STORE, 47551504797696, 47551504801791,
	2288	+ERASE, 94150123233280, 94150123233280,
	2289	+STORE, 94150123233280, 94150123241471,
	2290	+STORE, 94150123241472, 94150123245567,
	2291	+ERASE, 140081290534912, 140081290534912,
	2292	+STORE, 140081290534912, 140081290539007,
	2293	+STORE, 140081290539008, 140081290543103,
	2294	+ERASE, 47551504621568, 47551504621568,
	2295	+STORE, 94150148112384, 94150148247551,
	2296	+STORE, 140737488347136, 140737488351231,
	2297	+STORE, 140734389334016, 140737488351231,
	2298	+ERASE, 140734389334016, 140734389334016,
	2299	+STORE, 140734389334016, 140734389338111,
	2300	+STORE, 94844636606464, 94844636778495,
	2301	+ERASE, 94844636606464, 94844636606464,
	2302	+STORE, 94844636606464, 94844636622847,
	2303	+STORE, 94844636622848, 94844636778495,
	2304	+ERASE, 94844636622848, 94844636622848,
	2305	+STORE, 94844636622848, 94844636725247,
	2306	+STORE, 94844636725248, 94844636766207,
	2307	+STORE, 94844636766208, 94844636778495,
	2308	+STORE, 139922765217792, 139922765389823,
	2309	+ERASE, 139922765217792, 139922765217792,
	2310	+STORE, 139922765217792, 139922765221887,
	2311	+STORE, 139922765221888, 139922765389823,
	2312	+ERASE, 139922765221888, 139922765221888,
	2313	+STORE, 139922765221888, 139922765344767,
	2314	+STORE, 139922765344768, 139922765377535,
	2315	+STORE, 139922765377536, 139922765385727,
	2316	+STORE, 139922765385728, 139922765389823,
	2317	+STORE, 140734389678080, 140734389682175,
	2318	+STORE, 140734389665792, 140734389678079,
	2319	+STORE, 47710029778944, 47710029787135,
	2320	+STORE, 47710029787136, 47710029795327,
	2321	+STORE, 47710029795328, 47710029959167,
	2322	+ERASE, 47710029795328, 47710029795328,
	2323	+STORE, 47710029795328, 47710029807615,
	2324	+STORE, 47710029807616, 47710029959167,
	2325	+STORE, 47710029905920, 47710029959167,
	2326	+STORE, 47710029807616, 47710029905919,
	2327	+ERASE, 47710029807616, 47710029807616,
	2328	+STORE, 47710029807616, 47710029905919,
	2329	+STORE, 47710029950976, 47710029959167,
	2330	+STORE, 47710029905920, 47710029950975,
	2331	+ERASE, 47710029905920, 47710029905920,
	2332	+STORE, 47710029905920, 47710029959167,
	2333	+ERASE, 47710029905920, 47710029905920,
	2334	+STORE, 47710029905920, 47710029950975,
	2335	+STORE, 47710029950976, 47710029959167,
	2336	+ERASE, 47710029950976, 47710029950976,
	2337	+STORE, 47710029950976, 47710029959167,
	2338	+STORE, 47710029959168, 47710033010687,
	2339	+STORE, 47710030503936, 47710033010687,
	2340	+STORE, 47710029959168, 47710030503935,
	2341	+ERASE, 47710030503936, 47710030503936,
	2342	+STORE, 47710030503936, 47710032789503,
	2343	+STORE, 47710032789504, 47710033010687,
	2344	+STORE, 47710032199680, 47710032789503,
	2345	+STORE, 47710030503936, 47710032199679,
	2346	+ERASE, 47710030503936, 47710030503936,
	2347	+STORE, 47710030503936, 47710032199679,
	2348	+STORE, 47710032785408, 47710032789503,
	2349	+STORE, 47710032199680, 47710032785407,
	2350	+ERASE, 47710032199680, 47710032199680,
	2351	+STORE, 47710032199680, 47710032785407,
	2352	+STORE, 47710032994304, 47710033010687,
	2353	+STORE, 47710032789504, 47710032994303,
	2354	+ERASE, 47710032789504, 47710032789504,
	2355	+STORE, 47710032789504, 47710032994303,
	2356	+ERASE, 47710032994304, 47710032994304,
	2357	+STORE, 47710032994304, 47710033010687,
	2358	+STORE, 47710033010688, 47710034849791,
	2359	+STORE, 47710033149952, 47710034849791,
	2360	+STORE, 47710033010688, 47710033149951,
	2361	+ERASE, 47710033149952, 47710033149952,
	2362	+STORE, 47710033149952, 47710034808831,
	2363	+STORE, 47710034808832, 47710034849791,
	2364	+STORE, 47710034493440, 47710034808831,
	2365	+STORE, 47710033149952, 47710034493439,
	2366	+ERASE, 47710033149952, 47710033149952,
	2367	+STORE, 47710033149952, 47710034493439,
	2368	+STORE, 47710034804736, 47710034808831,
	2369	+STORE, 47710034493440, 47710034804735,
	2370	+ERASE, 47710034493440, 47710034493440,
	2371	+STORE, 47710034493440, 47710034804735,
	2372	+STORE, 47710034833408, 47710034849791,
	2373	+STORE, 47710034808832, 47710034833407,
	2374	+ERASE, 47710034808832, 47710034808832,
	2375	+STORE, 47710034808832, 47710034833407,
	2376	+ERASE, 47710034833408, 47710034833408,
	2377	+STORE, 47710034833408, 47710034849791,
	2378	+STORE, 47710034849792, 47710034984959,
	2379	+ERASE, 47710034849792, 47710034849792,
	2380	+STORE, 47710034849792, 47710034874367,
	2381	+STORE, 47710034874368, 47710034984959,
	2382	+STORE, 47710034935808, 47710034984959,
	2383	+STORE, 47710034874368, 47710034935807,
	2384	+ERASE, 47710034874368, 47710034874368,
	2385	+STORE, 47710034874368, 47710034935807,
	2386	+STORE, 47710034960384, 47710034984959,
	2387	+STORE, 47710034935808, 47710034960383,
	2388	+ERASE, 47710034935808, 47710034935808,
	2389	+STORE, 47710034935808, 47710034984959,
	2390	+ERASE, 47710034935808, 47710034935808,
	2391	+STORE, 47710034935808, 47710034960383,
	2392	+STORE, 47710034960384, 47710034984959,
	2393	+STORE, 47710034968576, 47710034984959,
	2394	+STORE, 47710034960384, 47710034968575,
	2395	+ERASE, 47710034960384, 47710034960384,
	2396	+STORE, 47710034960384, 47710034968575,
	2397	+ERASE, 47710034968576, 47710034968576,
	2398	+STORE, 47710034968576, 47710034984959,
	2399	+STORE, 47710034984960, 47710035005439,
	2400	+ERASE, 47710034984960, 47710034984960,
	2401	+STORE, 47710034984960, 47710034989055,
	2402	+STORE, 47710034989056, 47710035005439,
	2403	+STORE, 47710034993152, 47710035005439,
	2404	+STORE, 47710034989056, 47710034993151,
	2405	+ERASE, 47710034989056, 47710034989056,
	2406	+STORE, 47710034989056, 47710034993151,
	2407	+STORE, 47710034997248, 47710035005439,
	2408	+STORE, 47710034993152, 47710034997247,
	2409	+ERASE, 47710034993152, 47710034993152,
	2410	+STORE, 47710034993152, 47710035005439,
	2411	+ERASE, 47710034993152, 47710034993152,
	2412	+STORE, 47710034993152, 47710034997247,
	2413	+STORE, 47710034997248, 47710035005439,
	2414	+ERASE, 47710034997248, 47710034997248,
	2415	+STORE, 47710034997248, 47710035005439,
	2416	+STORE, 47710035005440, 47710035013631,
	2417	+ERASE, 47710034808832, 47710034808832,
	2418	+STORE, 47710034808832, 47710034825215,
	2419	+STORE, 47710034825216, 47710034833407,
	2420	+ERASE, 47710034997248, 47710034997248,
	2421	+STORE, 47710034997248, 47710035001343,
	2422	+STORE, 47710035001344, 47710035005439,
	2423	+ERASE, 47710034960384, 47710034960384,
	2424	+STORE, 47710034960384, 47710034964479,
	2425	+STORE, 47710034964480, 47710034968575,
	2426	+ERASE, 47710032789504, 47710032789504,
	2427	+STORE, 47710032789504, 47710032986111,
	2428	+STORE, 47710032986112, 47710032994303,
	2429	+ERASE, 47710029950976, 47710029950976,
	2430	+STORE, 47710029950976, 47710029955071,
	2431	+STORE, 47710029955072, 47710029959167,
	2432	+ERASE, 94844636766208, 94844636766208,
	2433	+STORE, 94844636766208, 94844636774399,
	2434	+STORE, 94844636774400, 94844636778495,
	2435	+ERASE, 139922765377536, 139922765377536,
	2436	+STORE, 139922765377536, 139922765381631,
	2437	+STORE, 139922765381632, 139922765385727,
	2438	+ERASE, 47710029778944, 47710029778944,
	2439	+STORE, 94844641775616, 94844641910783,
	2440	+STORE, 140737488347136, 140737488351231,
	2441	+STORE, 140732213886976, 140737488351231,
	2442	+ERASE, 140732213886976, 140732213886976,
	2443	+STORE, 140732213886976, 140732213891071,
	2444	+STORE, 94240508887040, 94240509059071,
	2445	+ERASE, 94240508887040, 94240508887040,
	2446	+STORE, 94240508887040, 94240508903423,
	2447	+STORE, 94240508903424, 94240509059071,
	2448	+ERASE, 94240508903424, 94240508903424,
	2449	+STORE, 94240508903424, 94240509005823,
	2450	+STORE, 94240509005824, 94240509046783,
	2451	+STORE, 94240509046784, 94240509059071,
	2452	+STORE, 140275106516992, 140275106689023,
	2453	+ERASE, 140275106516992, 140275106516992,
	2454	+STORE, 140275106516992, 140275106521087,
	2455	+STORE, 140275106521088, 140275106689023,
	2456	+ERASE, 140275106521088, 140275106521088,
	2457	+STORE, 140275106521088, 140275106643967,
	2458	+STORE, 140275106643968, 140275106676735,
	2459	+STORE, 140275106676736, 140275106684927,
	2460	+STORE, 140275106684928, 140275106689023,
	2461	+STORE, 140732213977088, 140732213981183,
	2462	+STORE, 140732213964800, 140732213977087,
	2463	+STORE, 47357688479744, 47357688487935,
	2464	+STORE, 47357688487936, 47357688496127,
	2465	+STORE, 47357688496128, 47357688659967,
	2466	+ERASE, 47357688496128, 47357688496128,
	2467	+STORE, 47357688496128, 47357688508415,
	2468	+STORE, 47357688508416, 47357688659967,
	2469	+STORE, 47357688606720, 47357688659967,
	2470	+STORE, 47357688508416, 47357688606719,
	2471	+ERASE, 47357688508416, 47357688508416,
	2472	+STORE, 47357688508416, 47357688606719,
	2473	+STORE, 47357688651776, 47357688659967,
	2474	+STORE, 47357688606720, 47357688651775,
	2475	+ERASE, 47357688606720, 47357688606720,
	2476	+STORE, 47357688606720, 47357688659967,
	2477	+ERASE, 47357688606720, 47357688606720,
	2478	+STORE, 47357688606720, 47357688651775,
	2479	+STORE, 47357688651776, 47357688659967,
	2480	+ERASE, 47357688651776, 47357688651776,
	2481	+STORE, 47357688651776, 47357688659967,
	2482	+STORE, 47357688659968, 47357691711487,
	2483	+STORE, 47357689204736, 47357691711487,
	2484	+STORE, 47357688659968, 47357689204735,
	2485	+ERASE, 47357689204736, 47357689204736,
	2486	+STORE, 47357689204736, 47357691490303,
	2487	+STORE, 47357691490304, 47357691711487,
	2488	+STORE, 47357690900480, 47357691490303,
	2489	+STORE, 47357689204736, 47357690900479,
	2490	+ERASE, 47357689204736, 47357689204736,
	2491	+STORE, 47357689204736, 47357690900479,
	2492	+STORE, 47357691486208, 47357691490303,
	2493	+STORE, 47357690900480, 47357691486207,
	2494	+ERASE, 47357690900480, 47357690900480,
	2495	+STORE, 47357690900480, 47357691486207,
	2496	+STORE, 47357691695104, 47357691711487,
	2497	+STORE, 47357691490304, 47357691695103,
	2498	+ERASE, 47357691490304, 47357691490304,
	2499	+STORE, 47357691490304, 47357691695103,
	2500	+ERASE, 47357691695104, 47357691695104,
	2501	+STORE, 47357691695104, 47357691711487,
	2502	+STORE, 47357691711488, 47357693550591,
	2503	+STORE, 47357691850752, 47357693550591,
	2504	+STORE, 47357691711488, 47357691850751,
	2505	+ERASE, 47357691850752, 47357691850752,
	2506	+STORE, 47357691850752, 47357693509631,
	2507	+STORE, 47357693509632, 47357693550591,
	2508	+STORE, 47357693194240, 47357693509631,
	2509	+STORE, 47357691850752, 47357693194239,
	2510	+ERASE, 47357691850752, 47357691850752,
	2511	+STORE, 47357691850752, 47357693194239,
	2512	+STORE, 47357693505536, 47357693509631,
	2513	+STORE, 47357693194240, 47357693505535,
	2514	+ERASE, 47357693194240, 47357693194240,
	2515	+STORE, 47357693194240, 47357693505535,
	2516	+STORE, 47357693534208, 47357693550591,
	2517	+STORE, 47357693509632, 47357693534207,
	2518	+ERASE, 47357693509632, 47357693509632,
	2519	+STORE, 47357693509632, 47357693534207,
	2520	+ERASE, 47357693534208, 47357693534208,
	2521	+STORE, 47357693534208, 47357693550591,
	2522	+STORE, 47357693550592, 47357693685759,
	2523	+ERASE, 47357693550592, 47357693550592,
	2524	+STORE, 47357693550592, 47357693575167,
	2525	+STORE, 47357693575168, 47357693685759,
	2526	+STORE, 47357693636608, 47357693685759,
	2527	+STORE, 47357693575168, 47357693636607,
	2528	+ERASE, 47357693575168, 47357693575168,
	2529	+STORE, 47357693575168, 47357693636607,
	2530	+STORE, 47357693661184, 47357693685759,
	2531	+STORE, 47357693636608, 47357693661183,
	2532	+ERASE, 47357693636608, 47357693636608,
	2533	+STORE, 47357693636608, 47357693685759,
	2534	+ERASE, 47357693636608, 47357693636608,
	2535	+STORE, 47357693636608, 47357693661183,
	2536	+STORE, 47357693661184, 47357693685759,
	2537	+STORE, 47357693669376, 47357693685759,
	2538	+STORE, 47357693661184, 47357693669375,
	2539	+ERASE, 47357693661184, 47357693661184,
	2540	+STORE, 47357693661184, 47357693669375,
	2541	+ERASE, 47357693669376, 47357693669376,
	2542	+STORE, 47357693669376, 47357693685759,
	2543	+STORE, 47357693685760, 47357693706239,
	2544	+ERASE, 47357693685760, 47357693685760,
	2545	+STORE, 47357693685760, 47357693689855,
	2546	+STORE, 47357693689856, 47357693706239,
	2547	+STORE, 47357693693952, 47357693706239,
	2548	+STORE, 47357693689856, 47357693693951,
	2549	+ERASE, 47357693689856, 47357693689856,
	2550	+STORE, 47357693689856, 47357693693951,
	2551	+STORE, 47357693698048, 47357693706239,
	2552	+STORE, 47357693693952, 47357693698047,
	2553	+ERASE, 47357693693952, 47357693693952,
	2554	+STORE, 47357693693952, 47357693706239,
	2555	+ERASE, 47357693693952, 47357693693952,
	2556	+STORE, 47357693693952, 47357693698047,
	2557	+STORE, 47357693698048, 47357693706239,
	2558	+ERASE, 47357693698048, 47357693698048,
	2559	+STORE, 47357693698048, 47357693706239,
	2560	+STORE, 47357693706240, 47357693714431,
	2561	+ERASE, 47357693509632, 47357693509632,
	2562	+STORE, 47357693509632, 47357693526015,
	2563	+STORE, 47357693526016, 47357693534207,
	2564	+ERASE, 47357693698048, 47357693698048,
	2565	+STORE, 47357693698048, 47357693702143,
	2566	+STORE, 47357693702144, 47357693706239,
	2567	+ERASE, 47357693661184, 47357693661184,
	2568	+STORE, 47357693661184, 47357693665279,
	2569	+STORE, 47357693665280, 47357693669375,
	2570	+ERASE, 47357691490304, 47357691490304,
	2571	+STORE, 47357691490304, 47357691686911,
	2572	+STORE, 47357691686912, 47357691695103,
	2573	+ERASE, 47357688651776, 47357688651776,
	2574	+STORE, 47357688651776, 47357688655871,
	2575	+STORE, 47357688655872, 47357688659967,
	2576	+ERASE, 94240509046784, 94240509046784,
	2577	+STORE, 94240509046784, 94240509054975,
	2578	+STORE, 94240509054976, 94240509059071,
	2579	+ERASE, 140275106676736, 140275106676736,
	2580	+STORE, 140275106676736, 140275106680831,
	2581	+STORE, 140275106680832, 140275106684927,
	2582	+ERASE, 47357688479744, 47357688479744,
	2583	+STORE, 94240518361088, 94240518496255,
	2584	+STORE, 140737488347136, 140737488351231,
	2585	+STORE, 140732688277504, 140737488351231,
	2586	+ERASE, 140732688277504, 140732688277504,
	2587	+STORE, 140732688277504, 140732688281599,
	2588	+STORE, 94629171351552, 94629172064255,
	2589	+ERASE, 94629171351552, 94629171351552,
	2590	+STORE, 94629171351552, 94629171400703,
	2591	+STORE, 94629171400704, 94629172064255,
	2592	+ERASE, 94629171400704, 94629171400704,
	2593	+STORE, 94629171400704, 94629171945471,
	2594	+STORE, 94629171945472, 94629172043775,
	2595	+STORE, 94629172043776, 94629172064255,
	2596	+STORE, 139770707644416, 139770707816447,
	2597	+ERASE, 139770707644416, 139770707644416,
	2598	+STORE, 139770707644416, 139770707648511,
	2599	+STORE, 139770707648512, 139770707816447,
	2600	+ERASE, 139770707648512, 139770707648512,
	2601	+STORE, 139770707648512, 139770707771391,
	2602	+STORE, 139770707771392, 139770707804159,
	2603	+STORE, 139770707804160, 139770707812351,
	2604	+STORE, 139770707812352, 139770707816447,
	2605	+STORE, 140732689121280, 140732689125375,
	2606	+STORE, 140732689108992, 140732689121279,
	2607	+STORE, 47862087352320, 47862087360511,
	2608	+STORE, 47862087360512, 47862087368703,
	2609	+STORE, 47862087368704, 47862087475199,
	2610	+STORE, 47862087385088, 47862087475199,
	2611	+STORE, 47862087368704, 47862087385087,
	2612	+ERASE, 47862087385088, 47862087385088,
	2613	+STORE, 47862087385088, 47862087458815,
	2614	+STORE, 47862087458816, 47862087475199,
	2615	+STORE, 47862087438336, 47862087458815,
	2616	+STORE, 47862087385088, 47862087438335,
	2617	+ERASE, 47862087385088, 47862087385088,
	2618	+STORE, 47862087385088, 47862087438335,
	2619	+STORE, 47862087454720, 47862087458815,
	2620	+STORE, 47862087438336, 47862087454719,
	2621	+ERASE, 47862087438336, 47862087438336,
	2622	+STORE, 47862087438336, 47862087454719,
	2623	+STORE, 47862087467008, 47862087475199,
	2624	+STORE, 47862087458816, 47862087467007,
	2625	+ERASE, 47862087458816, 47862087458816,
	2626	+STORE, 47862087458816, 47862087467007,
	2627	+ERASE, 47862087467008, 47862087467008,
	2628	+STORE, 47862087467008, 47862087475199,
	2629	+STORE, 47862087475200, 47862089314303,
	2630	+STORE, 47862087614464, 47862089314303,
	2631	+STORE, 47862087475200, 47862087614463,
	2632	+ERASE, 47862087614464, 47862087614464,
	2633	+STORE, 47862087614464, 47862089273343,
	2634	+STORE, 47862089273344, 47862089314303,
	2635	+STORE, 47862088957952, 47862089273343,
	2636	+STORE, 47862087614464, 47862088957951,
	2637	+ERASE, 47862087614464, 47862087614464,
	2638	+STORE, 47862087614464, 47862088957951,
	2639	+STORE, 47862089269248, 47862089273343,
	2640	+STORE, 47862088957952, 47862089269247,
	2641	+ERASE, 47862088957952, 47862088957952,
	2642	+STORE, 47862088957952, 47862089269247,
	2643	+STORE, 47862089297920, 47862089314303,
	2644	+STORE, 47862089273344, 47862089297919,
	2645	+ERASE, 47862089273344, 47862089273344,
	2646	+STORE, 47862089273344, 47862089297919,
	2647	+ERASE, 47862089297920, 47862089297920,
	2648	+STORE, 47862089297920, 47862089314303,
	2649	+STORE, 47862089297920, 47862089326591,
	2650	+ERASE, 47862089273344, 47862089273344,
	2651	+STORE, 47862089273344, 47862089289727,
	2652	+STORE, 47862089289728, 47862089297919,
	2653	+ERASE, 47862087458816, 47862087458816,
	2654	+STORE, 47862087458816, 47862087462911,
	2655	+STORE, 47862087462912, 47862087467007,
	2656	+ERASE, 94629172043776, 94629172043776,
	2657	+STORE, 94629172043776, 94629172060159,
	2658	+STORE, 94629172060160, 94629172064255,
	2659	+ERASE, 139770707804160, 139770707804160,
	2660	+STORE, 139770707804160, 139770707808255,
	2661	+STORE, 139770707808256, 139770707812351,
	2662	+ERASE, 47862087352320, 47862087352320,
	2663	+STORE, 94629197533184, 94629197668351,
	2664	+STORE, 140737488347136, 140737488351231,
	2665	+STORE, 140727540711424, 140737488351231,
	2666	+ERASE, 140727540711424, 140727540711424,
	2667	+STORE, 140727540711424, 140727540715519,
	2668	+STORE, 94299865313280, 94299866025983,
	2669	+ERASE, 94299865313280, 94299865313280,
	2670	+STORE, 94299865313280, 94299865362431,
	2671	+STORE, 94299865362432, 94299866025983,
	2672	+ERASE, 94299865362432, 94299865362432,
	2673	+STORE, 94299865362432, 94299865907199,
	2674	+STORE, 94299865907200, 94299866005503,
	2675	+STORE, 94299866005504, 94299866025983,
	2676	+STORE, 140680268763136, 140680268935167,
	2677	+ERASE, 140680268763136, 140680268763136,
	2678	+STORE, 140680268763136, 140680268767231,
	2679	+STORE, 140680268767232, 140680268935167,
	2680	+ERASE, 140680268767232, 140680268767232,
	2681	+STORE, 140680268767232, 140680268890111,
	2682	+STORE, 140680268890112, 140680268922879,
	2683	+STORE, 140680268922880, 140680268931071,
	2684	+STORE, 140680268931072, 140680268935167,
	2685	+STORE, 140727541424128, 140727541428223,
	2686	+STORE, 140727541411840, 140727541424127,
	2687	+STORE, 46952526233600, 46952526241791,
	2688	+STORE, 46952526241792, 46952526249983,
	2689	+STORE, 46952526249984, 46952526356479,
	2690	+STORE, 46952526266368, 46952526356479,
	2691	+STORE, 46952526249984, 46952526266367,
	2692	+ERASE, 46952526266368, 46952526266368,
	2693	+STORE, 46952526266368, 46952526340095,
	2694	+STORE, 46952526340096, 46952526356479,
	2695	+STORE, 46952526319616, 46952526340095,
	2696	+STORE, 46952526266368, 46952526319615,
	2697	+ERASE, 46952526266368, 46952526266368,
	2698	+STORE, 46952526266368, 46952526319615,
	2699	+STORE, 46952526336000, 46952526340095,
	2700	+STORE, 46952526319616, 46952526335999,
	2701	+ERASE, 46952526319616, 46952526319616,
	2702	+STORE, 46952526319616, 46952526335999,
	2703	+STORE, 46952526348288, 46952526356479,
	2704	+STORE, 46952526340096, 46952526348287,
	2705	+ERASE, 46952526340096, 46952526340096,
	2706	+STORE, 46952526340096, 46952526348287,
	2707	+ERASE, 46952526348288, 46952526348288,
	2708	+STORE, 46952526348288, 46952526356479,
	2709	+STORE, 46952526356480, 46952528195583,
	2710	+STORE, 46952526495744, 46952528195583,
	2711	+STORE, 46952526356480, 46952526495743,
	2712	+ERASE, 46952526495744, 46952526495744,
	2713	+STORE, 46952526495744, 46952528154623,
	2714	+STORE, 46952528154624, 46952528195583,
	2715	+STORE, 46952527839232, 46952528154623,
	2716	+STORE, 46952526495744, 46952527839231,
	2717	+ERASE, 46952526495744, 46952526495744,
	2718	+STORE, 46952526495744, 46952527839231,
	2719	+STORE, 46952528150528, 46952528154623,
	2720	+STORE, 46952527839232, 46952528150527,
	2721	+ERASE, 46952527839232, 46952527839232,
	2722	+STORE, 46952527839232, 46952528150527,
	2723	+STORE, 46952528179200, 46952528195583,
	2724	+STORE, 46952528154624, 46952528179199,
	2725	+ERASE, 46952528154624, 46952528154624,
	2726	+STORE, 46952528154624, 46952528179199,
	2727	+ERASE, 46952528179200, 46952528179200,
	2728	+STORE, 46952528179200, 46952528195583,
	2729	+STORE, 46952528179200, 46952528207871,
	2730	+ERASE, 46952528154624, 46952528154624,
	2731	+STORE, 46952528154624, 46952528171007,
	2732	+STORE, 46952528171008, 46952528179199,
	2733	+ERASE, 46952526340096, 46952526340096,
	2734	+STORE, 46952526340096, 46952526344191,
	2735	+STORE, 46952526344192, 46952526348287,
	2736	+ERASE, 94299866005504, 94299866005504,
	2737	+STORE, 94299866005504, 94299866021887,
	2738	+STORE, 94299866021888, 94299866025983,
	2739	+ERASE, 140680268922880, 140680268922880,
	2740	+STORE, 140680268922880, 140680268926975,
	2741	+STORE, 140680268926976, 140680268931071,
	2742	+ERASE, 46952526233600, 46952526233600,
	2743	+STORE, 140737488347136, 140737488351231,
	2744	+STORE, 140722874793984, 140737488351231,
	2745	+ERASE, 140722874793984, 140722874793984,
	2746	+STORE, 140722874793984, 140722874798079,
	2747	+STORE, 94448916213760, 94448916926463,
	2748	+ERASE, 94448916213760, 94448916213760,
	2749	+STORE, 94448916213760, 94448916262911,
	2750	+STORE, 94448916262912, 94448916926463,
	2751	+ERASE, 94448916262912, 94448916262912,
	2752	+STORE, 94448916262912, 94448916807679,
	2753	+STORE, 94448916807680, 94448916905983,
	2754	+STORE, 94448916905984, 94448916926463,
	2755	+STORE, 140389117046784, 140389117218815,
	2756	+ERASE, 140389117046784, 140389117046784,
	2757	+STORE, 140389117046784, 140389117050879,
	2758	+STORE, 140389117050880, 140389117218815,
	2759	+ERASE, 140389117050880, 140389117050880,
	2760	+STORE, 140389117050880, 140389117173759,
	2761	+STORE, 140389117173760, 140389117206527,
	2762	+STORE, 140389117206528, 140389117214719,
	2763	+STORE, 140389117214720, 140389117218815,
	2764	+STORE, 140722875297792, 140722875301887,
	2765	+STORE, 140722875285504, 140722875297791,
	2766	+STORE, 47243677949952, 47243677958143,
	2767	+STORE, 47243677958144, 47243677966335,
	2768	+STORE, 47243677966336, 47243678072831,
	2769	+STORE, 47243677982720, 47243678072831,
	2770	+STORE, 47243677966336, 47243677982719,
	2771	+ERASE, 47243677982720, 47243677982720,
	2772	+STORE, 47243677982720, 47243678056447,
	2773	+STORE, 47243678056448, 47243678072831,
	2774	+STORE, 47243678035968, 47243678056447,
	2775	+STORE, 47243677982720, 47243678035967,
	2776	+ERASE, 47243677982720, 47243677982720,
	2777	+STORE, 47243677982720, 47243678035967,
	2778	+STORE, 47243678052352, 47243678056447,
	2779	+STORE, 47243678035968, 47243678052351,
	2780	+ERASE, 47243678035968, 47243678035968,
	2781	+STORE, 47243678035968, 47243678052351,
	2782	+STORE, 47243678064640, 47243678072831,
	2783	+STORE, 47243678056448, 47243678064639,
	2784	+ERASE, 47243678056448, 47243678056448,
	2785	+STORE, 47243678056448, 47243678064639,
	2786	+ERASE, 47243678064640, 47243678064640,
	2787	+STORE, 47243678064640, 47243678072831,
	2788	+STORE, 47243678072832, 47243679911935,
	2789	+STORE, 47243678212096, 47243679911935,
	2790	+STORE, 47243678072832, 47243678212095,
	2791	+ERASE, 47243678212096, 47243678212096,
	2792	+STORE, 47243678212096, 47243679870975,
	2793	+STORE, 47243679870976, 47243679911935,
	2794	+STORE, 47243679555584, 47243679870975,
	2795	+STORE, 47243678212096, 47243679555583,
	2796	+ERASE, 47243678212096, 47243678212096,
	2797	+STORE, 47243678212096, 47243679555583,
	2798	+STORE, 47243679866880, 47243679870975,
	2799	+STORE, 47243679555584, 47243679866879,
	2800	+ERASE, 47243679555584, 47243679555584,
	2801	+STORE, 47243679555584, 47243679866879,
	2802	+STORE, 47243679895552, 47243679911935,
	2803	+STORE, 47243679870976, 47243679895551,
	2804	+ERASE, 47243679870976, 47243679870976,
	2805	+STORE, 47243679870976, 47243679895551,
	2806	+ERASE, 47243679895552, 47243679895552,
	2807	+STORE, 47243679895552, 47243679911935,
	2808	+STORE, 47243679895552, 47243679924223,
	2809	+ERASE, 47243679870976, 47243679870976,
	2810	+STORE, 47243679870976, 47243679887359,
	2811	+STORE, 47243679887360, 47243679895551,
	2812	+ERASE, 47243678056448, 47243678056448,
	2813	+STORE, 47243678056448, 47243678060543,
	2814	+STORE, 47243678060544, 47243678064639,
	2815	+ERASE, 94448916905984, 94448916905984,
	2816	+STORE, 94448916905984, 94448916922367,
	2817	+STORE, 94448916922368, 94448916926463,
	2818	+ERASE, 140389117206528, 140389117206528,
	2819	+STORE, 140389117206528, 140389117210623,
	2820	+STORE, 140389117210624, 140389117214719,
	2821	+ERASE, 47243677949952, 47243677949952,
	2822	+STORE, 140737488347136, 140737488351231,
	2823	+STORE, 140733068505088, 140737488351231,
	2824	+ERASE, 140733068505088, 140733068505088,
	2825	+STORE, 140733068505088, 140733068509183,
	2826	+STORE, 94207145750528, 94207146463231,
	2827	+ERASE, 94207145750528, 94207145750528,
	2828	+STORE, 94207145750528, 94207145799679,
	2829	+STORE, 94207145799680, 94207146463231,
	2830	+ERASE, 94207145799680, 94207145799680,
	2831	+STORE, 94207145799680, 94207146344447,
	2832	+STORE, 94207146344448, 94207146442751,
	2833	+STORE, 94207146442752, 94207146463231,
	2834	+STORE, 140684504911872, 140684505083903,
	2835	+ERASE, 140684504911872, 140684504911872,
	2836	+STORE, 140684504911872, 140684504915967,
	2837	+STORE, 140684504915968, 140684505083903,
	2838	+ERASE, 140684504915968, 140684504915968,
	2839	+STORE, 140684504915968, 140684505038847,
	2840	+STORE, 140684505038848, 140684505071615,
	2841	+STORE, 140684505071616, 140684505079807,
	2842	+STORE, 140684505079808, 140684505083903,
	2843	+STORE, 140733068607488, 140733068611583,
	2844	+STORE, 140733068595200, 140733068607487,
	2845	+STORE, 46948290084864, 46948290093055,
	2846	+STORE, 46948290093056, 46948290101247,
	2847	+STORE, 46948290101248, 46948290207743,
	2848	+STORE, 46948290117632, 46948290207743,
	2849	+STORE, 46948290101248, 46948290117631,
	2850	+ERASE, 46948290117632, 46948290117632,
	2851	+STORE, 46948290117632, 46948290191359,
	2852	+STORE, 46948290191360, 46948290207743,
	2853	+STORE, 46948290170880, 46948290191359,
	2854	+STORE, 46948290117632, 46948290170879,
	2855	+ERASE, 46948290117632, 46948290117632,
	2856	+STORE, 46948290117632, 46948290170879,
	2857	+STORE, 46948290187264, 46948290191359,
	2858	+STORE, 46948290170880, 46948290187263,
	2859	+ERASE, 46948290170880, 46948290170880,
	2860	+STORE, 46948290170880, 46948290187263,
	2861	+STORE, 46948290199552, 46948290207743,
	2862	+STORE, 46948290191360, 46948290199551,
	2863	+ERASE, 46948290191360, 46948290191360,
	2864	+STORE, 46948290191360, 46948290199551,
	2865	+ERASE, 46948290199552, 46948290199552,
	2866	+STORE, 46948290199552, 46948290207743,
	2867	+STORE, 46948290207744, 46948292046847,
	2868	+STORE, 46948290347008, 46948292046847,
	2869	+STORE, 46948290207744, 46948290347007,
	2870	+ERASE, 46948290347008, 46948290347008,
	2871	+STORE, 46948290347008, 46948292005887,
	2872	+STORE, 46948292005888, 46948292046847,
	2873	+STORE, 46948291690496, 46948292005887,
	2874	+STORE, 46948290347008, 46948291690495,
	2875	+ERASE, 46948290347008, 46948290347008,
	2876	+STORE, 46948290347008, 46948291690495,
	2877	+STORE, 46948292001792, 46948292005887,
	2878	+STORE, 46948291690496, 46948292001791,
	2879	+ERASE, 46948291690496, 46948291690496,
	2880	+STORE, 46948291690496, 46948292001791,
	2881	+STORE, 46948292030464, 46948292046847,
	2882	+STORE, 46948292005888, 46948292030463,
	2883	+ERASE, 46948292005888, 46948292005888,
	2884	+STORE, 46948292005888, 46948292030463,
	2885	+ERASE, 46948292030464, 46948292030464,
	2886	+STORE, 46948292030464, 46948292046847,
	2887	+STORE, 46948292030464, 46948292059135,
	2888	+ERASE, 46948292005888, 46948292005888,
	2889	+STORE, 46948292005888, 46948292022271,
	2890	+STORE, 46948292022272, 46948292030463,
	2891	+ERASE, 46948290191360, 46948290191360,
	2892	+STORE, 46948290191360, 46948290195455,
	2893	+STORE, 46948290195456, 46948290199551,
	2894	+ERASE, 94207146442752, 94207146442752,
	2895	+STORE, 94207146442752, 94207146459135,
	2896	+STORE, 94207146459136, 94207146463231,
	2897	+ERASE, 140684505071616, 140684505071616,
	2898	+STORE, 140684505071616, 140684505075711,
	2899	+STORE, 140684505075712, 140684505079807,
	2900	+ERASE, 46948290084864, 46948290084864,
	2901	+STORE, 140737488347136, 140737488351231,
	2902	+STORE, 140726367158272, 140737488351231,
	2903	+ERASE, 140726367158272, 140726367158272,
	2904	+STORE, 140726367158272, 140726367162367,
	2905	+STORE, 94436124106752, 94436124819455,
	2906	+ERASE, 94436124106752, 94436124106752,
	2907	+STORE, 94436124106752, 94436124155903,
	2908	+STORE, 94436124155904, 94436124819455,
	2909	+ERASE, 94436124155904, 94436124155904,
	2910	+STORE, 94436124155904, 94436124700671,
	2911	+STORE, 94436124700672, 94436124798975,
	2912	+STORE, 94436124798976, 94436124819455,
	2913	+STORE, 140049025044480, 140049025216511,
	2914	+ERASE, 140049025044480, 140049025044480,
	2915	+STORE, 140049025044480, 140049025048575,
	2916	+STORE, 140049025048576, 140049025216511,
	2917	+ERASE, 140049025048576, 140049025048576,
	2918	+STORE, 140049025048576, 140049025171455,
	2919	+STORE, 140049025171456, 140049025204223,
	2920	+STORE, 140049025204224, 140049025212415,
	2921	+STORE, 140049025212416, 140049025216511,
	2922	+STORE, 140726367256576, 140726367260671,
	2923	+STORE, 140726367244288, 140726367256575,
	2924	+STORE, 47583769952256, 47583769960447,
	2925	+STORE, 47583769960448, 47583769968639,
	2926	+STORE, 47583769968640, 47583770075135,
	2927	+STORE, 47583769985024, 47583770075135,
	2928	+STORE, 47583769968640, 47583769985023,
	2929	+ERASE, 47583769985024, 47583769985024,
	2930	+STORE, 47583769985024, 47583770058751,
	2931	+STORE, 47583770058752, 47583770075135,
	2932	+STORE, 47583770038272, 47583770058751,
	2933	+STORE, 47583769985024, 47583770038271,
	2934	+ERASE, 47583769985024, 47583769985024,
	2935	+STORE, 47583769985024, 47583770038271,
	2936	+STORE, 47583770054656, 47583770058751,
	2937	+STORE, 47583770038272, 47583770054655,
	2938	+ERASE, 47583770038272, 47583770038272,
	2939	+STORE, 47583770038272, 47583770054655,
	2940	+STORE, 47583770066944, 47583770075135,
	2941	+STORE, 47583770058752, 47583770066943,
	2942	+ERASE, 47583770058752, 47583770058752,
	2943	+STORE, 47583770058752, 47583770066943,
	2944	+ERASE, 47583770066944, 47583770066944,
	2945	+STORE, 47583770066944, 47583770075135,
	2946	+STORE, 47583770075136, 47583771914239,
	2947	+STORE, 47583770214400, 47583771914239,
	2948	+STORE, 47583770075136, 47583770214399,
	2949	+ERASE, 47583770214400, 47583770214400,
	2950	+STORE, 47583770214400, 47583771873279,
	2951	+STORE, 47583771873280, 47583771914239,
	2952	+STORE, 47583771557888, 47583771873279,
	2953	+STORE, 47583770214400, 47583771557887,
	2954	+ERASE, 47583770214400, 47583770214400,
	2955	+STORE, 47583770214400, 47583771557887,
	2956	+STORE, 47583771869184, 47583771873279,
	2957	+STORE, 47583771557888, 47583771869183,
	2958	+ERASE, 47583771557888, 47583771557888,
	2959	+STORE, 47583771557888, 47583771869183,
	2960	+STORE, 47583771897856, 47583771914239,
	2961	+STORE, 47583771873280, 47583771897855,
	2962	+ERASE, 47583771873280, 47583771873280,
	2963	+STORE, 47583771873280, 47583771897855,
	2964	+ERASE, 47583771897856, 47583771897856,
	2965	+STORE, 47583771897856, 47583771914239,
	2966	+STORE, 47583771897856, 47583771926527,
	2967	+ERASE, 47583771873280, 47583771873280,
	2968	+STORE, 47583771873280, 47583771889663,
	2969	+STORE, 47583771889664, 47583771897855,
	2970	+ERASE, 47583770058752, 47583770058752,
	2971	+STORE, 47583770058752, 47583770062847,
	2972	+STORE, 47583770062848, 47583770066943,
	2973	+ERASE, 94436124798976, 94436124798976,
	2974	+STORE, 94436124798976, 94436124815359,
	2975	+STORE, 94436124815360, 94436124819455,
	2976	+ERASE, 140049025204224, 140049025204224,
	2977	+STORE, 140049025204224, 140049025208319,
	2978	+STORE, 140049025208320, 140049025212415,
	2979	+ERASE, 47583769952256, 47583769952256,
	2980	+STORE, 140737488347136, 140737488351231,
	2981	+STORE, 140727116099584, 140737488351231,
	2982	+ERASE, 140727116099584, 140727116099584,
	2983	+STORE, 140727116099584, 140727116103679,
	2984	+STORE, 94166319734784, 94166320447487,
	2985	+ERASE, 94166319734784, 94166319734784,
	2986	+STORE, 94166319734784, 94166319783935,
	2987	+STORE, 94166319783936, 94166320447487,
	2988	+ERASE, 94166319783936, 94166319783936,
	2989	+STORE, 94166319783936, 94166320328703,
	2990	+STORE, 94166320328704, 94166320427007,
	2991	+STORE, 94166320427008, 94166320447487,
	2992	+STORE, 139976559542272, 139976559714303,
	2993	+ERASE, 139976559542272, 139976559542272,
	2994	+STORE, 139976559542272, 139976559546367,
	2995	+STORE, 139976559546368, 139976559714303,
	2996	+ERASE, 139976559546368, 139976559546368,
	2997	+STORE, 139976559546368, 139976559669247,
	2998	+STORE, 139976559669248, 139976559702015,
	2999	+STORE, 139976559702016, 139976559710207,
	3000	+STORE, 139976559710208, 139976559714303,
	3001	+STORE, 140727116222464, 140727116226559,
	3002	+STORE, 140727116210176, 140727116222463,
	3003	+STORE, 47656235454464, 47656235462655,
	3004	+STORE, 47656235462656, 47656235470847,
	3005	+STORE, 47656235470848, 47656235577343,
	3006	+STORE, 47656235487232, 47656235577343,
	3007	+STORE, 47656235470848, 47656235487231,
	3008	+ERASE, 47656235487232, 47656235487232,
	3009	+STORE, 47656235487232, 47656235560959,
	3010	+STORE, 47656235560960, 47656235577343,
	3011	+STORE, 47656235540480, 47656235560959,
	3012	+STORE, 47656235487232, 47656235540479,
	3013	+ERASE, 47656235487232, 47656235487232,
	3014	+STORE, 47656235487232, 47656235540479,
	3015	+STORE, 47656235556864, 47656235560959,
	3016	+STORE, 47656235540480, 47656235556863,
	3017	+ERASE, 47656235540480, 47656235540480,
	3018	+STORE, 47656235540480, 47656235556863,
	3019	+STORE, 47656235569152, 47656235577343,
	3020	+STORE, 47656235560960, 47656235569151,
	3021	+ERASE, 47656235560960, 47656235560960,
	3022	+STORE, 47656235560960, 47656235569151,
	3023	+ERASE, 47656235569152, 47656235569152,
	3024	+STORE, 47656235569152, 47656235577343,
	3025	+STORE, 47656235577344, 47656237416447,
	3026	+STORE, 47656235716608, 47656237416447,
	3027	+STORE, 47656235577344, 47656235716607,
	3028	+ERASE, 47656235716608, 47656235716608,
	3029	+STORE, 47656235716608, 47656237375487,
	3030	+STORE, 47656237375488, 47656237416447,
	3031	+STORE, 47656237060096, 47656237375487,
	3032	+STORE, 47656235716608, 47656237060095,
	3033	+ERASE, 47656235716608, 47656235716608,
	3034	+STORE, 47656235716608, 47656237060095,
	3035	+STORE, 47656237371392, 47656237375487,
	3036	+STORE, 47656237060096, 47656237371391,
	3037	+ERASE, 47656237060096, 47656237060096,
	3038	+STORE, 47656237060096, 47656237371391,
	3039	+STORE, 47656237400064, 47656237416447,
	3040	+STORE, 47656237375488, 47656237400063,
	3041	+ERASE, 47656237375488, 47656237375488,
	3042	+STORE, 47656237375488, 47656237400063,
	3043	+ERASE, 47656237400064, 47656237400064,
	3044	+STORE, 47656237400064, 47656237416447,
	3045	+STORE, 47656237400064, 47656237428735,
	3046	+ERASE, 47656237375488, 47656237375488,
	3047	+STORE, 47656237375488, 47656237391871,
	3048	+STORE, 47656237391872, 47656237400063,
	3049	+ERASE, 47656235560960, 47656235560960,
	3050	+STORE, 47656235560960, 47656235565055,
	3051	+STORE, 47656235565056, 47656235569151,
	3052	+ERASE, 94166320427008, 94166320427008,
	3053	+STORE, 94166320427008, 94166320443391,
	3054	+STORE, 94166320443392, 94166320447487,
	3055	+ERASE, 139976559702016, 139976559702016,
	3056	+STORE, 139976559702016, 139976559706111,
	3057	+STORE, 139976559706112, 139976559710207,
	3058	+ERASE, 47656235454464, 47656235454464,
	3059	+STORE, 94166332153856, 94166332289023,
	3060	+STORE, 140737488347136, 140737488351231,
	3061	+STORE, 140726412816384, 140737488351231,
	3062	+ERASE, 140726412816384, 140726412816384,
	3063	+STORE, 140726412816384, 140726412820479,
	3064	+STORE, 94094884507648, 94094885220351,
	3065	+ERASE, 94094884507648, 94094884507648,
	3066	+STORE, 94094884507648, 94094884556799,
	3067	+STORE, 94094884556800, 94094885220351,
	3068	+ERASE, 94094884556800, 94094884556800,
	3069	+STORE, 94094884556800, 94094885101567,
	3070	+STORE, 94094885101568, 94094885199871,
	3071	+STORE, 94094885199872, 94094885220351,
	3072	+STORE, 139773773938688, 139773774110719,
	3073	+ERASE, 139773773938688, 139773773938688,
	3074	+STORE, 139773773938688, 139773773942783,
	3075	+STORE, 139773773942784, 139773774110719,
	3076	+ERASE, 139773773942784, 139773773942784,
	3077	+STORE, 139773773942784, 139773774065663,
	3078	+STORE, 139773774065664, 139773774098431,
	3079	+STORE, 139773774098432, 139773774106623,
	3080	+STORE, 139773774106624, 139773774110719,
	3081	+STORE, 140726412963840, 140726412967935,
	3082	+STORE, 140726412951552, 140726412963839,
	3083	+STORE, 47859021058048, 47859021066239,
	3084	+STORE, 47859021066240, 47859021074431,
	3085	+STORE, 47859021074432, 47859021180927,
	3086	+STORE, 47859021090816, 47859021180927,
	3087	+STORE, 47859021074432, 47859021090815,
	3088	+ERASE, 47859021090816, 47859021090816,
	3089	+STORE, 47859021090816, 47859021164543,
	3090	+STORE, 47859021164544, 47859021180927,
	3091	+STORE, 47859021144064, 47859021164543,
	3092	+STORE, 47859021090816, 47859021144063,
	3093	+ERASE, 47859021090816, 47859021090816,
	3094	+STORE, 47859021090816, 47859021144063,
	3095	+STORE, 47859021160448, 47859021164543,
	3096	+STORE, 47859021144064, 47859021160447,
	3097	+ERASE, 47859021144064, 47859021144064,
	3098	+STORE, 47859021144064, 47859021160447,
	3099	+STORE, 47859021172736, 47859021180927,
	3100	+STORE, 47859021164544, 47859021172735,
	3101	+ERASE, 47859021164544, 47859021164544,
	3102	+STORE, 47859021164544, 47859021172735,
	3103	+ERASE, 47859021172736, 47859021172736,
	3104	+STORE, 47859021172736, 47859021180927,
	3105	+STORE, 47859021180928, 47859023020031,
	3106	+STORE, 47859021320192, 47859023020031,
	3107	+STORE, 47859021180928, 47859021320191,
	3108	+ERASE, 47859021320192, 47859021320192,
	3109	+STORE, 47859021320192, 47859022979071,
	3110	+STORE, 47859022979072, 47859023020031,
	3111	+STORE, 47859022663680, 47859022979071,
	3112	+STORE, 47859021320192, 47859022663679,
	3113	+ERASE, 47859021320192, 47859021320192,
	3114	+STORE, 47859021320192, 47859022663679,
	3115	+STORE, 47859022974976, 47859022979071,
	3116	+STORE, 47859022663680, 47859022974975,
	3117	+ERASE, 47859022663680, 47859022663680,
	3118	+STORE, 47859022663680, 47859022974975,
	3119	+STORE, 47859023003648, 47859023020031,
	3120	+STORE, 47859022979072, 47859023003647,
	3121	+ERASE, 47859022979072, 47859022979072,
	3122	+STORE, 47859022979072, 47859023003647,
	3123	+ERASE, 47859023003648, 47859023003648,
	3124	+STORE, 47859023003648, 47859023020031,
	3125	+STORE, 47859023003648, 47859023032319,
	3126	+ERASE, 47859022979072, 47859022979072,
	3127	+STORE, 47859022979072, 47859022995455,
	3128	+STORE, 47859022995456, 47859023003647,
	3129	+ERASE, 47859021164544, 47859021164544,
	3130	+STORE, 47859021164544, 47859021168639,
	3131	+STORE, 47859021168640, 47859021172735,
	3132	+ERASE, 94094885199872, 94094885199872,
	3133	+STORE, 94094885199872, 94094885216255,
	3134	+STORE, 94094885216256, 94094885220351,
	3135	+ERASE, 139773774098432, 139773774098432,
	3136	+STORE, 139773774098432, 139773774102527,
	3137	+STORE, 139773774102528, 139773774106623,
	3138	+ERASE, 47859021058048, 47859021058048,
	3139	+STORE, 94094901108736, 94094901243903,
	3140	+STORE, 140737488347136, 140737488351231,
	3141	+STORE, 140736567963648, 140737488351231,
	3142	+ERASE, 140736567963648, 140736567963648,
	3143	+STORE, 140736567963648, 140736567967743,
	3144	+STORE, 94924425748480, 94924426461183,
	3145	+ERASE, 94924425748480, 94924425748480,
	3146	+STORE, 94924425748480, 94924425797631,
	3147	+STORE, 94924425797632, 94924426461183,
	3148	+ERASE, 94924425797632, 94924425797632,
	3149	+STORE, 94924425797632, 94924426342399,
	3150	+STORE, 94924426342400, 94924426440703,
	3151	+STORE, 94924426440704, 94924426461183,
	3152	+STORE, 140042126319616, 140042126491647,
	3153	+ERASE, 140042126319616, 140042126319616,
	3154	+STORE, 140042126319616, 140042126323711,
	3155	+STORE, 140042126323712, 140042126491647,
	3156	+ERASE, 140042126323712, 140042126323712,
	3157	+STORE, 140042126323712, 140042126446591,
	3158	+STORE, 140042126446592, 140042126479359,
	3159	+STORE, 140042126479360, 140042126487551,
	3160	+STORE, 140042126487552, 140042126491647,
	3161	+STORE, 140736568672256, 140736568676351,
	3162	+STORE, 140736568659968, 140736568672255,
	3163	+STORE, 47590668677120, 47590668685311,
	3164	+STORE, 47590668685312, 47590668693503,
	3165	+STORE, 47590668693504, 47590668799999,
	3166	+STORE, 47590668709888, 47590668799999,
	3167	+STORE, 47590668693504, 47590668709887,
	3168	+ERASE, 47590668709888, 47590668709888,
	3169	+STORE, 47590668709888, 47590668783615,
	3170	+STORE, 47590668783616, 47590668799999,
	3171	+STORE, 47590668763136, 47590668783615,
	3172	+STORE, 47590668709888, 47590668763135,
	3173	+ERASE, 47590668709888, 47590668709888,
	3174	+STORE, 47590668709888, 47590668763135,
	3175	+STORE, 47590668779520, 47590668783615,
	3176	+STORE, 47590668763136, 47590668779519,
	3177	+ERASE, 47590668763136, 47590668763136,
	3178	+STORE, 47590668763136, 47590668779519,
	3179	+STORE, 47590668791808, 47590668799999,
	3180	+STORE, 47590668783616, 47590668791807,
	3181	+ERASE, 47590668783616, 47590668783616,
	3182	+STORE, 47590668783616, 47590668791807,
	3183	+ERASE, 47590668791808, 47590668791808,
	3184	+STORE, 47590668791808, 47590668799999,
	3185	+STORE, 47590668800000, 47590670639103,
	3186	+STORE, 47590668939264, 47590670639103,
	3187	+STORE, 47590668800000, 47590668939263,
	3188	+ERASE, 47590668939264, 47590668939264,
	3189	+STORE, 47590668939264, 47590670598143,
	3190	+STORE, 47590670598144, 47590670639103,
	3191	+STORE, 47590670282752, 47590670598143,
	3192	+STORE, 47590668939264, 47590670282751,
	3193	+ERASE, 47590668939264, 47590668939264,
	3194	+STORE, 47590668939264, 47590670282751,
	3195	+STORE, 47590670594048, 47590670598143,
	3196	+STORE, 47590670282752, 47590670594047,
	3197	+ERASE, 47590670282752, 47590670282752,
	3198	+STORE, 47590670282752, 47590670594047,
	3199	+STORE, 47590670622720, 47590670639103,
	3200	+STORE, 47590670598144, 47590670622719,
	3201	+ERASE, 47590670598144, 47590670598144,
	3202	+STORE, 47590670598144, 47590670622719,
	3203	+ERASE, 47590670622720, 47590670622720,
	3204	+STORE, 47590670622720, 47590670639103,
	3205	+STORE, 47590670622720, 47590670651391,
	3206	+ERASE, 47590670598144, 47590670598144,
	3207	+STORE, 47590670598144, 47590670614527,
	3208	+STORE, 47590670614528, 47590670622719,
	3209	+ERASE, 47590668783616, 47590668783616,
	3210	+STORE, 47590668783616, 47590668787711,
	3211	+STORE, 47590668787712, 47590668791807,
	3212	+ERASE, 94924426440704, 94924426440704,
	3213	+STORE, 94924426440704, 94924426457087,
	3214	+STORE, 94924426457088, 94924426461183,
	3215	+ERASE, 140042126479360, 140042126479360,
	3216	+STORE, 140042126479360, 140042126483455,
	3217	+STORE, 140042126483456, 140042126487551,
	3218	+ERASE, 47590668677120, 47590668677120,
	3219	+STORE, 140737488347136, 140737488351231,
	3220	+STORE, 140733281439744, 140737488351231,
	3221	+ERASE, 140733281439744, 140733281439744,
	3222	+STORE, 140733281439744, 140733281443839,
	3223	+STORE, 94490667069440, 94490667782143,
	3224	+ERASE, 94490667069440, 94490667069440,
	3225	+STORE, 94490667069440, 94490667118591,
	3226	+STORE, 94490667118592, 94490667782143,
	3227	+ERASE, 94490667118592, 94490667118592,
	3228	+STORE, 94490667118592, 94490667663359,
	3229	+STORE, 94490667663360, 94490667761663,
	3230	+STORE, 94490667761664, 94490667782143,
	3231	+STORE, 139878215118848, 139878215290879,
	3232	+ERASE, 139878215118848, 139878215118848,
	3233	+STORE, 139878215118848, 139878215122943,
	3234	+STORE, 139878215122944, 139878215290879,
	3235	+ERASE, 139878215122944, 139878215122944,
	3236	+STORE, 139878215122944, 139878215245823,
	3237	+STORE, 139878215245824, 139878215278591,
	3238	+STORE, 139878215278592, 139878215286783,
	3239	+STORE, 139878215286784, 139878215290879,
	3240	+STORE, 140733281464320, 140733281468415,
	3241	+STORE, 140733281452032, 140733281464319,
	3242	+STORE, 47754579877888, 47754579886079,
	3243	+STORE, 47754579886080, 47754579894271,
	3244	+STORE, 47754579894272, 47754580000767,
	3245	+STORE, 47754579910656, 47754580000767,
	3246	+STORE, 47754579894272, 47754579910655,
	3247	+ERASE, 47754579910656, 47754579910656,
	3248	+STORE, 47754579910656, 47754579984383,
	3249	+STORE, 47754579984384, 47754580000767,
	3250	+STORE, 47754579963904, 47754579984383,
	3251	+STORE, 47754579910656, 47754579963903,
	3252	+ERASE, 47754579910656, 47754579910656,
	3253	+STORE, 47754579910656, 47754579963903,
	3254	+STORE, 47754579980288, 47754579984383,
	3255	+STORE, 47754579963904, 47754579980287,
	3256	+ERASE, 47754579963904, 47754579963904,
	3257	+STORE, 47754579963904, 47754579980287,
	3258	+STORE, 47754579992576, 47754580000767,
	3259	+STORE, 47754579984384, 47754579992575,
	3260	+ERASE, 47754579984384, 47754579984384,
	3261	+STORE, 47754579984384, 47754579992575,
	3262	+ERASE, 47754579992576, 47754579992576,
	3263	+STORE, 47754579992576, 47754580000767,
	3264	+STORE, 47754580000768, 47754581839871,
	3265	+STORE, 47754580140032, 47754581839871,
	3266	+STORE, 47754580000768, 47754580140031,
	3267	+ERASE, 47754580140032, 47754580140032,
	3268	+STORE, 47754580140032, 47754581798911,
	3269	+STORE, 47754581798912, 47754581839871,
	3270	+STORE, 47754581483520, 47754581798911,
	3271	+STORE, 47754580140032, 47754581483519,
	3272	+ERASE, 47754580140032, 47754580140032,
	3273	+STORE, 47754580140032, 47754581483519,
	3274	+STORE, 47754581794816, 47754581798911,
	3275	+STORE, 47754581483520, 47754581794815,
	3276	+ERASE, 47754581483520, 47754581483520,
	3277	+STORE, 47754581483520, 47754581794815,
	3278	+STORE, 47754581823488, 47754581839871,
	3279	+STORE, 47754581798912, 47754581823487,
	3280	+ERASE, 47754581798912, 47754581798912,
	3281	+STORE, 47754581798912, 47754581823487,
	3282	+ERASE, 47754581823488, 47754581823488,
	3283	+STORE, 47754581823488, 47754581839871,
	3284	+STORE, 47754581823488, 47754581852159,
	3285	+ERASE, 47754581798912, 47754581798912,
	3286	+STORE, 47754581798912, 47754581815295,
	3287	+STORE, 47754581815296, 47754581823487,
	3288	+ERASE, 47754579984384, 47754579984384,
	3289	+STORE, 47754579984384, 47754579988479,
	3290	+STORE, 47754579988480, 47754579992575,
	3291	+ERASE, 94490667761664, 94490667761664,
	3292	+STORE, 94490667761664, 94490667778047,
	3293	+STORE, 94490667778048, 94490667782143,
	3294	+ERASE, 139878215278592, 139878215278592,
	3295	+STORE, 139878215278592, 139878215282687,
	3296	+STORE, 139878215282688, 139878215286783,
	3297	+ERASE, 47754579877888, 47754579877888,
	3298	+STORE, 94490669649920, 94490669785087,
	3299	+STORE, 140737488347136, 140737488351231,
	3300	+STORE, 140735382188032, 140737488351231,
	3301	+ERASE, 140735382188032, 140735382188032,
	3302	+STORE, 140735382188032, 140735382192127,
	3303	+STORE, 94150181302272, 94150182014975,
	3304	+ERASE, 94150181302272, 94150181302272,
	3305	+STORE, 94150181302272, 94150181351423,
	3306	+STORE, 94150181351424, 94150182014975,
	3307	+ERASE, 94150181351424, 94150181351424,
	3308	+STORE, 94150181351424, 94150181896191,
	3309	+STORE, 94150181896192, 94150181994495,
	3310	+STORE, 94150181994496, 94150182014975,
	3311	+STORE, 139679752458240, 139679752630271,
	3312	+ERASE, 139679752458240, 139679752458240,
	3313	+STORE, 139679752458240, 139679752462335,
	3314	+STORE, 139679752462336, 139679752630271,
	3315	+ERASE, 139679752462336, 139679752462336,
	3316	+STORE, 139679752462336, 139679752585215,
	3317	+STORE, 139679752585216, 139679752617983,
	3318	+STORE, 139679752617984, 139679752626175,
	3319	+STORE, 139679752626176, 139679752630271,
	3320	+STORE, 140735382536192, 140735382540287,
	3321	+STORE, 140735382523904, 140735382536191,
	3322	+STORE, 47953042538496, 47953042546687,
	3323	+STORE, 47953042546688, 47953042554879,
	3324	+STORE, 47953042554880, 47953042661375,
	3325	+STORE, 47953042571264, 47953042661375,
	3326	+STORE, 47953042554880, 47953042571263,
	3327	+ERASE, 47953042571264, 47953042571264,
	3328	+STORE, 47953042571264, 47953042644991,
	3329	+STORE, 47953042644992, 47953042661375,
	3330	+STORE, 47953042624512, 47953042644991,
	3331	+STORE, 47953042571264, 47953042624511,
	3332	+ERASE, 47953042571264, 47953042571264,
	3333	+STORE, 47953042571264, 47953042624511,
	3334	+STORE, 47953042640896, 47953042644991,
	3335	+STORE, 47953042624512, 47953042640895,
	3336	+ERASE, 47953042624512, 47953042624512,
	3337	+STORE, 47953042624512, 47953042640895,
	3338	+STORE, 47953042653184, 47953042661375,
	3339	+STORE, 47953042644992, 47953042653183,
	3340	+ERASE, 47953042644992, 47953042644992,
	3341	+STORE, 47953042644992, 47953042653183,
	3342	+ERASE, 47953042653184, 47953042653184,
	3343	+STORE, 47953042653184, 47953042661375,
	3344	+STORE, 47953042661376, 47953044500479,
	3345	+STORE, 47953042800640, 47953044500479,
	3346	+STORE, 47953042661376, 47953042800639,
	3347	+ERASE, 47953042800640, 47953042800640,
	3348	+STORE, 47953042800640, 47953044459519,
	3349	+STORE, 47953044459520, 47953044500479,
	3350	+STORE, 47953044144128, 47953044459519,
	3351	+STORE, 47953042800640, 47953044144127,
	3352	+ERASE, 47953042800640, 47953042800640,
	3353	+STORE, 47953042800640, 47953044144127,
	3354	+STORE, 47953044455424, 47953044459519,
	3355	+STORE, 47953044144128, 47953044455423,
	3356	+ERASE, 47953044144128, 47953044144128,
	3357	+STORE, 47953044144128, 47953044455423,
	3358	+STORE, 47953044484096, 47953044500479,
	3359	+STORE, 47953044459520, 47953044484095,
	3360	+ERASE, 47953044459520, 47953044459520,
	3361	+STORE, 47953044459520, 47953044484095,
	3362	+ERASE, 47953044484096, 47953044484096,
	3363	+STORE, 47953044484096, 47953044500479,
	3364	+STORE, 47953044484096, 47953044512767,
	3365	+ERASE, 47953044459520, 47953044459520,
	3366	+STORE, 47953044459520, 47953044475903,
	3367	+STORE, 47953044475904, 47953044484095,
	3368	+ERASE, 47953042644992, 47953042644992,
	3369	+STORE, 47953042644992, 47953042649087,
	3370	+STORE, 47953042649088, 47953042653183,
	3371	+ERASE, 94150181994496, 94150181994496,
	3372	+STORE, 94150181994496, 94150182010879,
	3373	+STORE, 94150182010880, 94150182014975,
	3374	+ERASE, 139679752617984, 139679752617984,
	3375	+STORE, 139679752617984, 139679752622079,
	3376	+STORE, 139679752622080, 139679752626175,
	3377	+ERASE, 47953042538496, 47953042538496,
	3378	+STORE, 140737488347136, 140737488351231,
	3379	+STORE, 140737044123648, 140737488351231,
	3380	+ERASE, 140737044123648, 140737044123648,
	3381	+STORE, 140737044123648, 140737044127743,
	3382	+STORE, 94425324294144, 94425325006847,
	3383	+ERASE, 94425324294144, 94425324294144,
	3384	+STORE, 94425324294144, 94425324343295,
	3385	+STORE, 94425324343296, 94425325006847,
	3386	+ERASE, 94425324343296, 94425324343296,
	3387	+STORE, 94425324343296, 94425324888063,
	3388	+STORE, 94425324888064, 94425324986367,
	3389	+STORE, 94425324986368, 94425325006847,
	3390	+STORE, 140382015016960, 140382015188991,
	3391	+ERASE, 140382015016960, 140382015016960,
	3392	+STORE, 140382015016960, 140382015021055,
	3393	+STORE, 140382015021056, 140382015188991,
	3394	+ERASE, 140382015021056, 140382015021056,
	3395	+STORE, 140382015021056, 140382015143935,
	3396	+STORE, 140382015143936, 140382015176703,
	3397	+STORE, 140382015176704, 140382015184895,
	3398	+STORE, 140382015184896, 140382015188991,
	3399	+STORE, 140737045585920, 140737045590015,
	3400	+STORE, 140737045573632, 140737045585919,
	3401	+STORE, 47250779979776, 47250779987967,
	3402	+STORE, 47250779987968, 47250779996159,
	3403	+STORE, 47250779996160, 47250780102655,
	3404	+STORE, 47250780012544, 47250780102655,
	3405	+STORE, 47250779996160, 47250780012543,
	3406	+ERASE, 47250780012544, 47250780012544,
	3407	+STORE, 47250780012544, 47250780086271,
	3408	+STORE, 47250780086272, 47250780102655,
	3409	+STORE, 47250780065792, 47250780086271,
	3410	+STORE, 47250780012544, 47250780065791,
	3411	+ERASE, 47250780012544, 47250780012544,
	3412	+STORE, 47250780012544, 47250780065791,
	3413	+STORE, 47250780082176, 47250780086271,
	3414	+STORE, 47250780065792, 47250780082175,
	3415	+ERASE, 47250780065792, 47250780065792,
	3416	+STORE, 47250780065792, 47250780082175,
	3417	+STORE, 47250780094464, 47250780102655,
	3418	+STORE, 47250780086272, 47250780094463,
	3419	+ERASE, 47250780086272, 47250780086272,
	3420	+STORE, 47250780086272, 47250780094463,
	3421	+ERASE, 47250780094464, 47250780094464,
	3422	+STORE, 47250780094464, 47250780102655,
	3423	+STORE, 47250780102656, 47250781941759,
	3424	+STORE, 47250780241920, 47250781941759,
	3425	+STORE, 47250780102656, 47250780241919,
	3426	+ERASE, 47250780241920, 47250780241920,
	3427	+STORE, 47250780241920, 47250781900799,
	3428	+STORE, 47250781900800, 47250781941759,
	3429	+STORE, 47250781585408, 47250781900799,
	3430	+STORE, 47250780241920, 47250781585407,
	3431	+ERASE, 47250780241920, 47250780241920,
	3432	+STORE, 47250780241920, 47250781585407,
	3433	+STORE, 47250781896704, 47250781900799,
	3434	+STORE, 47250781585408, 47250781896703,
	3435	+ERASE, 47250781585408, 47250781585408,
	3436	+STORE, 47250781585408, 47250781896703,
	3437	+STORE, 47250781925376, 47250781941759,
	3438	+STORE, 47250781900800, 47250781925375,
	3439	+ERASE, 47250781900800, 47250781900800,
	3440	+STORE, 47250781900800, 47250781925375,
	3441	+ERASE, 47250781925376, 47250781925376,
	3442	+STORE, 47250781925376, 47250781941759,
	3443	+STORE, 47250781925376, 47250781954047,
	3444	+ERASE, 47250781900800, 47250781900800,
	3445	+STORE, 47250781900800, 47250781917183,
	3446	+STORE, 47250781917184, 47250781925375,
	3447	+ERASE, 47250780086272, 47250780086272,
	3448	+STORE, 47250780086272, 47250780090367,
	3449	+STORE, 47250780090368, 47250780094463,
	3450	+ERASE, 94425324986368, 94425324986368,
	3451	+STORE, 94425324986368, 94425325002751,
	3452	+STORE, 94425325002752, 94425325006847,
	3453	+ERASE, 140382015176704, 140382015176704,
	3454	+STORE, 140382015176704, 140382015180799,
	3455	+STORE, 140382015180800, 140382015184895,
	3456	+ERASE, 47250779979776, 47250779979776,
	3457	+STORE, 94425351438336, 94425351573503,
	3458	+STORE, 140737488347136, 140737488351231,
	3459	+STORE, 140736801144832, 140737488351231,
	3460	+ERASE, 140736801144832, 140736801144832,
	3461	+STORE, 140736801144832, 140736801148927,
	3462	+STORE, 94629429358592, 94629430071295,
	3463	+ERASE, 94629429358592, 94629429358592,
	3464	+STORE, 94629429358592, 94629429407743,
	3465	+STORE, 94629429407744, 94629430071295,
	3466	+ERASE, 94629429407744, 94629429407744,
	3467	+STORE, 94629429407744, 94629429952511,
	3468	+STORE, 94629429952512, 94629430050815,
	3469	+STORE, 94629430050816, 94629430071295,
	3470	+STORE, 139801685483520, 139801685655551,
	3471	+ERASE, 139801685483520, 139801685483520,
	3472	+STORE, 139801685483520, 139801685487615,
	3473	+STORE, 139801685487616, 139801685655551,
	3474	+ERASE, 139801685487616, 139801685487616,
	3475	+STORE, 139801685487616, 139801685610495,
	3476	+STORE, 139801685610496, 139801685643263,
	3477	+STORE, 139801685643264, 139801685651455,
	3478	+STORE, 139801685651456, 139801685655551,
	3479	+STORE, 140736801198080, 140736801202175,
	3480	+STORE, 140736801185792, 140736801198079,
	3481	+STORE, 47831109513216, 47831109521407,
	3482	+STORE, 47831109521408, 47831109529599,
	3483	+STORE, 47831109529600, 47831109636095,
	3484	+STORE, 47831109545984, 47831109636095,
	3485	+STORE, 47831109529600, 47831109545983,
	3486	+ERASE, 47831109545984, 47831109545984,
	3487	+STORE, 47831109545984, 47831109619711,
	3488	+STORE, 47831109619712, 47831109636095,
	3489	+STORE, 47831109599232, 47831109619711,
	3490	+STORE, 47831109545984, 47831109599231,
	3491	+ERASE, 47831109545984, 47831109545984,
	3492	+STORE, 47831109545984, 47831109599231,
	3493	+STORE, 47831109615616, 47831109619711,
	3494	+STORE, 47831109599232, 47831109615615,
	3495	+ERASE, 47831109599232, 47831109599232,
	3496	+STORE, 47831109599232, 47831109615615,
	3497	+STORE, 47831109627904, 47831109636095,
	3498	+STORE, 47831109619712, 47831109627903,
	3499	+ERASE, 47831109619712, 47831109619712,
	3500	+STORE, 47831109619712, 47831109627903,
	3501	+ERASE, 47831109627904, 47831109627904,
	3502	+STORE, 47831109627904, 47831109636095,
	3503	+STORE, 47831109636096, 47831111475199,
	3504	+STORE, 47831109775360, 47831111475199,
	3505	+STORE, 47831109636096, 47831109775359,
	3506	+ERASE, 47831109775360, 47831109775360,
	3507	+STORE, 47831109775360, 47831111434239,
	3508	+STORE, 47831111434240, 47831111475199,
	3509	+STORE, 47831111118848, 47831111434239,
	3510	+STORE, 47831109775360, 47831111118847,
	3511	+ERASE, 47831109775360, 47831109775360,
	3512	+STORE, 47831109775360, 47831111118847,
	3513	+STORE, 47831111430144, 47831111434239,
	3514	+STORE, 47831111118848, 47831111430143,
	3515	+ERASE, 47831111118848, 47831111118848,
	3516	+STORE, 47831111118848, 47831111430143,
	3517	+STORE, 47831111458816, 47831111475199,
	3518	+STORE, 47831111434240, 47831111458815,
	3519	+ERASE, 47831111434240, 47831111434240,
	3520	+STORE, 47831111434240, 47831111458815,
	3521	+ERASE, 47831111458816, 47831111458816,
	3522	+STORE, 47831111458816, 47831111475199,
	3523	+STORE, 47831111458816, 47831111487487,
	3524	+ERASE, 47831111434240, 47831111434240,
	3525	+STORE, 47831111434240, 47831111450623,
	3526	+STORE, 47831111450624, 47831111458815,
	3527	+ERASE, 47831109619712, 47831109619712,
	3528	+STORE, 47831109619712, 47831109623807,
	3529	+STORE, 47831109623808, 47831109627903,
	3530	+ERASE, 94629430050816, 94629430050816,
	3531	+STORE, 94629430050816, 94629430067199,
	3532	+STORE, 94629430067200, 94629430071295,
	3533	+ERASE, 139801685643264, 139801685643264,
	3534	+STORE, 139801685643264, 139801685647359,
	3535	+STORE, 139801685647360, 139801685651455,
	3536	+ERASE, 47831109513216, 47831109513216,
	3537	+STORE, 140737488347136, 140737488351231,
	3538	+STORE, 140729419612160, 140737488351231,
	3539	+ERASE, 140729419612160, 140729419612160,
	3540	+STORE, 140729419612160, 140729419616255,
	3541	+STORE, 94443354148864, 94443354861567,
	3542	+ERASE, 94443354148864, 94443354148864,
	3543	+STORE, 94443354148864, 94443354198015,
	3544	+STORE, 94443354198016, 94443354861567,
	3545	+ERASE, 94443354198016, 94443354198016,
	3546	+STORE, 94443354198016, 94443354742783,
	3547	+STORE, 94443354742784, 94443354841087,
	3548	+STORE, 94443354841088, 94443354861567,
	3549	+STORE, 139741700038656, 139741700210687,
	3550	+ERASE, 139741700038656, 139741700038656,
	3551	+STORE, 139741700038656, 139741700042751,
	3552	+STORE, 139741700042752, 139741700210687,
	3553	+ERASE, 139741700042752, 139741700042752,
	3554	+STORE, 139741700042752, 139741700165631,
	3555	+STORE, 139741700165632, 139741700198399,
	3556	+STORE, 139741700198400, 139741700206591,
	3557	+STORE, 139741700206592, 139741700210687,
	3558	+STORE, 140729420574720, 140729420578815,
	3559	+STORE, 140729420562432, 140729420574719,
	3560	+STORE, 47891094958080, 47891094966271,
	3561	+STORE, 47891094966272, 47891094974463,
	3562	+STORE, 47891094974464, 47891095080959,
	3563	+STORE, 47891094990848, 47891095080959,
	3564	+STORE, 47891094974464, 47891094990847,
	3565	+ERASE, 47891094990848, 47891094990848,
	3566	+STORE, 47891094990848, 47891095064575,
	3567	+STORE, 47891095064576, 47891095080959,
	3568	+STORE, 47891095044096, 47891095064575,
	3569	+STORE, 47891094990848, 47891095044095,
	3570	+ERASE, 47891094990848, 47891094990848,
	3571	+STORE, 47891094990848, 47891095044095,
	3572	+STORE, 47891095060480, 47891095064575,
	3573	+STORE, 47891095044096, 47891095060479,
	3574	+ERASE, 47891095044096, 47891095044096,
	3575	+STORE, 47891095044096, 47891095060479,
	3576	+STORE, 47891095072768, 47891095080959,
	3577	+STORE, 47891095064576, 47891095072767,
	3578	+ERASE, 47891095064576, 47891095064576,
	3579	+STORE, 47891095064576, 47891095072767,
	3580	+ERASE, 47891095072768, 47891095072768,
	3581	+STORE, 47891095072768, 47891095080959,
	3582	+STORE, 47891095080960, 47891096920063,
	3583	+STORE, 47891095220224, 47891096920063,
	3584	+STORE, 47891095080960, 47891095220223,
	3585	+ERASE, 47891095220224, 47891095220224,
	3586	+STORE, 47891095220224, 47891096879103,
	3587	+STORE, 47891096879104, 47891096920063,
	3588	+STORE, 47891096563712, 47891096879103,
	3589	+STORE, 47891095220224, 47891096563711,
	3590	+ERASE, 47891095220224, 47891095220224,
	3591	+STORE, 47891095220224, 47891096563711,
	3592	+STORE, 47891096875008, 47891096879103,
	3593	+STORE, 47891096563712, 47891096875007,
	3594	+ERASE, 47891096563712, 47891096563712,
	3595	+STORE, 47891096563712, 47891096875007,
	3596	+STORE, 47891096903680, 47891096920063,
	3597	+STORE, 47891096879104, 47891096903679,
	3598	+ERASE, 47891096879104, 47891096879104,
	3599	+STORE, 47891096879104, 47891096903679,
	3600	+ERASE, 47891096903680, 47891096903680,
	3601	+STORE, 47891096903680, 47891096920063,
	3602	+STORE, 47891096903680, 47891096932351,
	3603	+ERASE, 47891096879104, 47891096879104,
	3604	+STORE, 47891096879104, 47891096895487,
	3605	+STORE, 47891096895488, 47891096903679,
	3606	+ERASE, 47891095064576, 47891095064576,
	3607	+STORE, 47891095064576, 47891095068671,
	3608	+STORE, 47891095068672, 47891095072767,
	3609	+ERASE, 94443354841088, 94443354841088,
	3610	+STORE, 94443354841088, 94443354857471,
	3611	+STORE, 94443354857472, 94443354861567,
	3612	+ERASE, 139741700198400, 139741700198400,
	3613	+STORE, 139741700198400, 139741700202495,
	3614	+STORE, 139741700202496, 139741700206591,
	3615	+ERASE, 47891094958080, 47891094958080,
	3616	+STORE, 94443360825344, 94443360960511,
	3617	+STORE, 140737488347136, 140737488351231,
	3618	+STORE, 140722961661952, 140737488351231,
	3619	+ERASE, 140722961661952, 140722961661952,
	3620	+STORE, 140722961661952, 140722961666047,
	3621	+STORE, 94878388944896, 94878389657599,
	3622	+ERASE, 94878388944896, 94878388944896,
	3623	+STORE, 94878388944896, 94878388994047,
	3624	+STORE, 94878388994048, 94878389657599,
	3625	+ERASE, 94878388994048, 94878388994048,
	3626	+STORE, 94878388994048, 94878389538815,
	3627	+STORE, 94878389538816, 94878389637119,
	3628	+STORE, 94878389637120, 94878389657599,
	3629	+STORE, 140210690056192, 140210690228223,
	3630	+ERASE, 140210690056192, 140210690056192,
	3631	+STORE, 140210690056192, 140210690060287,
	3632	+STORE, 140210690060288, 140210690228223,
	3633	+ERASE, 140210690060288, 140210690060288,
	3634	+STORE, 140210690060288, 140210690183167,
	3635	+STORE, 140210690183168, 140210690215935,
	3636	+STORE, 140210690215936, 140210690224127,
	3637	+STORE, 140210690224128, 140210690228223,
	3638	+STORE, 140722963148800, 140722963152895,
	3639	+STORE, 140722963136512, 140722963148799,
	3640	+STORE, 47422104940544, 47422104948735,
	3641	+STORE, 47422104948736, 47422104956927,
	3642	+STORE, 47422104956928, 47422105063423,
	3643	+STORE, 47422104973312, 47422105063423,
	3644	+STORE, 47422104956928, 47422104973311,
	3645	+ERASE, 47422104973312, 47422104973312,
	3646	+STORE, 47422104973312, 47422105047039,
	3647	+STORE, 47422105047040, 47422105063423,
	3648	+STORE, 47422105026560, 47422105047039,
	3649	+STORE, 47422104973312, 47422105026559,
	3650	+ERASE, 47422104973312, 47422104973312,
	3651	+STORE, 47422104973312, 47422105026559,
	3652	+STORE, 47422105042944, 47422105047039,
	3653	+STORE, 47422105026560, 47422105042943,
	3654	+ERASE, 47422105026560, 47422105026560,
	3655	+STORE, 47422105026560, 47422105042943,
	3656	+STORE, 47422105055232, 47422105063423,
	3657	+STORE, 47422105047040, 47422105055231,
	3658	+ERASE, 47422105047040, 47422105047040,
	3659	+STORE, 47422105047040, 47422105055231,
	3660	+ERASE, 47422105055232, 47422105055232,
	3661	+STORE, 47422105055232, 47422105063423,
	3662	+STORE, 47422105063424, 47422106902527,
	3663	+STORE, 47422105202688, 47422106902527,
	3664	+STORE, 47422105063424, 47422105202687,
	3665	+ERASE, 47422105202688, 47422105202688,
	3666	+STORE, 47422105202688, 47422106861567,
	3667	+STORE, 47422106861568, 47422106902527,
	3668	+STORE, 47422106546176, 47422106861567,
	3669	+STORE, 47422105202688, 47422106546175,
	3670	+ERASE, 47422105202688, 47422105202688,
	3671	+STORE, 47422105202688, 47422106546175,
	3672	+STORE, 47422106857472, 47422106861567,
	3673	+STORE, 47422106546176, 47422106857471,
	3674	+ERASE, 47422106546176, 47422106546176,
	3675	+STORE, 47422106546176, 47422106857471,
	3676	+STORE, 47422106886144, 47422106902527,
	3677	+STORE, 47422106861568, 47422106886143,
	3678	+ERASE, 47422106861568, 47422106861568,
	3679	+STORE, 47422106861568, 47422106886143,
	3680	+ERASE, 47422106886144, 47422106886144,
	3681	+STORE, 47422106886144, 47422106902527,
	3682	+STORE, 47422106886144, 47422106914815,
	3683	+ERASE, 47422106861568, 47422106861568,
	3684	+STORE, 47422106861568, 47422106877951,
	3685	+STORE, 47422106877952, 47422106886143,
	3686	+ERASE, 47422105047040, 47422105047040,
	3687	+STORE, 47422105047040, 47422105051135,
	3688	+STORE, 47422105051136, 47422105055231,
	3689	+ERASE, 94878389637120, 94878389637120,
	3690	+STORE, 94878389637120, 94878389653503,
	3691	+STORE, 94878389653504, 94878389657599,
	3692	+ERASE, 140210690215936, 140210690215936,
	3693	+STORE, 140210690215936, 140210690220031,
	3694	+STORE, 140210690220032, 140210690224127,
	3695	+ERASE, 47422104940544, 47422104940544,
	3696	+STORE, 140737488347136, 140737488351231,
	3697	+STORE, 140727690309632, 140737488351231,
	3698	+ERASE, 140727690309632, 140727690309632,
	3699	+STORE, 140727690309632, 140727690313727,
	3700	+STORE, 94121892208640, 94121892921343,
	3701	+ERASE, 94121892208640, 94121892208640,
	3702	+STORE, 94121892208640, 94121892257791,
	3703	+STORE, 94121892257792, 94121892921343,
	3704	+ERASE, 94121892257792, 94121892257792,
	3705	+STORE, 94121892257792, 94121892802559,
	3706	+STORE, 94121892802560, 94121892900863,
	3707	+STORE, 94121892900864, 94121892921343,
	3708	+STORE, 140662438326272, 140662438498303,
	3709	+ERASE, 140662438326272, 140662438326272,
	3710	+STORE, 140662438326272, 140662438330367,
	3711	+STORE, 140662438330368, 140662438498303,
	3712	+ERASE, 140662438330368, 140662438330368,
	3713	+STORE, 140662438330368, 140662438453247,
	3714	+STORE, 140662438453248, 140662438486015,
	3715	+STORE, 140662438486016, 140662438494207,
	3716	+STORE, 140662438494208, 140662438498303,
	3717	+STORE, 140727690379264, 140727690383359,
	3718	+STORE, 140727690366976, 140727690379263,
	3719	+STORE, 46970356670464, 46970356678655,
	3720	+STORE, 46970356678656, 46970356686847,
	3721	+STORE, 46970356686848, 46970356793343,
	3722	+STORE, 46970356703232, 46970356793343,
	3723	+STORE, 46970356686848, 46970356703231,
	3724	+ERASE, 46970356703232, 46970356703232,
	3725	+STORE, 46970356703232, 46970356776959,
	3726	+STORE, 46970356776960, 46970356793343,
	3727	+STORE, 46970356756480, 46970356776959,
	3728	+STORE, 46970356703232, 46970356756479,
	3729	+ERASE, 46970356703232, 46970356703232,
	3730	+STORE, 46970356703232, 46970356756479,
	3731	+STORE, 46970356772864, 46970356776959,
	3732	+STORE, 46970356756480, 46970356772863,
	3733	+ERASE, 46970356756480, 46970356756480,
	3734	+STORE, 46970356756480, 46970356772863,
	3735	+STORE, 46970356785152, 46970356793343,
	3736	+STORE, 46970356776960, 46970356785151,
	3737	+ERASE, 46970356776960, 46970356776960,
	3738	+STORE, 46970356776960, 46970356785151,
	3739	+ERASE, 46970356785152, 46970356785152,
	3740	+STORE, 46970356785152, 46970356793343,
	3741	+STORE, 46970356793344, 46970358632447,
	3742	+STORE, 46970356932608, 46970358632447,
	3743	+STORE, 46970356793344, 46970356932607,
	3744	+ERASE, 46970356932608, 46970356932608,
	3745	+STORE, 46970356932608, 46970358591487,
	3746	+STORE, 46970358591488, 46970358632447,
	3747	+STORE, 46970358276096, 46970358591487,
	3748	+STORE, 46970356932608, 46970358276095,
	3749	+ERASE, 46970356932608, 46970356932608,
	3750	+STORE, 46970356932608, 46970358276095,
	3751	+STORE, 46970358587392, 46970358591487,
	3752	+STORE, 46970358276096, 46970358587391,
	3753	+ERASE, 46970358276096, 46970358276096,
	3754	+STORE, 46970358276096, 46970358587391,
	3755	+STORE, 46970358616064, 46970358632447,
	3756	+STORE, 46970358591488, 46970358616063,
	3757	+ERASE, 46970358591488, 46970358591488,
	3758	+STORE, 46970358591488, 46970358616063,
	3759	+ERASE, 46970358616064, 46970358616064,
	3760	+STORE, 46970358616064, 46970358632447,
	3761	+STORE, 46970358616064, 46970358644735,
	3762	+ERASE, 46970358591488, 46970358591488,
	3763	+STORE, 46970358591488, 46970358607871,
	3764	+STORE, 46970358607872, 46970358616063,
	3765	+ERASE, 46970356776960, 46970356776960,
	3766	+STORE, 46970356776960, 46970356781055,
	3767	+STORE, 46970356781056, 46970356785151,
	3768	+ERASE, 94121892900864, 94121892900864,
	3769	+STORE, 94121892900864, 94121892917247,
	3770	+STORE, 94121892917248, 94121892921343,
	3771	+ERASE, 140662438486016, 140662438486016,
	3772	+STORE, 140662438486016, 140662438490111,
	3773	+STORE, 140662438490112, 140662438494207,
	3774	+ERASE, 46970356670464, 46970356670464,
	3775	+STORE, 94121898610688, 94121898745855,
	3776	+STORE, 140737488347136, 140737488351231,
	3777	+STORE, 140737189351424, 140737488351231,
	3778	+ERASE, 140737189351424, 140737189351424,
	3779	+STORE, 140737189351424, 140737189355519,
	3780	+STORE, 93847948832768, 93847949545471,
	3781	+ERASE, 93847948832768, 93847948832768,
	3782	+STORE, 93847948832768, 93847948881919,
	3783	+STORE, 93847948881920, 93847949545471,
	3784	+ERASE, 93847948881920, 93847948881920,
	3785	+STORE, 93847948881920, 93847949426687,
	3786	+STORE, 93847949426688, 93847949524991,
	3787	+STORE, 93847949524992, 93847949545471,
	3788	+STORE, 139698989985792, 139698990157823,
	3789	+ERASE, 139698989985792, 139698989985792,
	3790	+STORE, 139698989985792, 139698989989887,
	3791	+STORE, 139698989989888, 139698990157823,
	3792	+ERASE, 139698989989888, 139698989989888,
	3793	+STORE, 139698989989888, 139698990112767,
	3794	+STORE, 139698990112768, 139698990145535,
	3795	+STORE, 139698990145536, 139698990153727,
	3796	+STORE, 139698990153728, 139698990157823,
	3797	+STORE, 140737189744640, 140737189748735,
	3798	+STORE, 140737189732352, 140737189744639,
	3799	+STORE, 47933805010944, 47933805019135,
	3800	+STORE, 47933805019136, 47933805027327,
	3801	+STORE, 47933805027328, 47933805133823,
	3802	+STORE, 47933805043712, 47933805133823,
	3803	+STORE, 47933805027328, 47933805043711,
	3804	+ERASE, 47933805043712, 47933805043712,
	3805	+STORE, 47933805043712, 47933805117439,
	3806	+STORE, 47933805117440, 47933805133823,
	3807	+STORE, 47933805096960, 47933805117439,
	3808	+STORE, 47933805043712, 47933805096959,
	3809	+ERASE, 47933805043712, 47933805043712,
	3810	+STORE, 47933805043712, 47933805096959,
	3811	+STORE, 47933805113344, 47933805117439,
	3812	+STORE, 47933805096960, 47933805113343,
	3813	+ERASE, 47933805096960, 47933805096960,
	3814	+STORE, 47933805096960, 47933805113343,
	3815	+STORE, 47933805125632, 47933805133823,
	3816	+STORE, 47933805117440, 47933805125631,
	3817	+ERASE, 47933805117440, 47933805117440,
	3818	+STORE, 47933805117440, 47933805125631,
	3819	+ERASE, 47933805125632, 47933805125632,
	3820	+STORE, 47933805125632, 47933805133823,
	3821	+STORE, 47933805133824, 47933806972927,
	3822	+STORE, 47933805273088, 47933806972927,
	3823	+STORE, 47933805133824, 47933805273087,
	3824	+ERASE, 47933805273088, 47933805273088,
	3825	+STORE, 47933805273088, 47933806931967,
	3826	+STORE, 47933806931968, 47933806972927,
	3827	+STORE, 47933806616576, 47933806931967,
	3828	+STORE, 47933805273088, 47933806616575,
	3829	+ERASE, 47933805273088, 47933805273088,
	3830	+STORE, 47933805273088, 47933806616575,
	3831	+STORE, 47933806927872, 47933806931967,
	3832	+STORE, 47933806616576, 47933806927871,
	3833	+ERASE, 47933806616576, 47933806616576,
	3834	+STORE, 47933806616576, 47933806927871,
	3835	+STORE, 47933806956544, 47933806972927,
	3836	+STORE, 47933806931968, 47933806956543,
	3837	+ERASE, 47933806931968, 47933806931968,
	3838	+STORE, 47933806931968, 47933806956543,
	3839	+ERASE, 47933806956544, 47933806956544,
	3840	+STORE, 47933806956544, 47933806972927,
	3841	+STORE, 47933806956544, 47933806985215,
	3842	+ERASE, 47933806931968, 47933806931968,
	3843	+STORE, 47933806931968, 47933806948351,
	3844	+STORE, 47933806948352, 47933806956543,
	3845	+ERASE, 47933805117440, 47933805117440,
	3846	+STORE, 47933805117440, 47933805121535,
	3847	+STORE, 47933805121536, 47933805125631,
	3848	+ERASE, 93847949524992, 93847949524992,
	3849	+STORE, 93847949524992, 93847949541375,
	3850	+STORE, 93847949541376, 93847949545471,
	3851	+ERASE, 139698990145536, 139698990145536,
	3852	+STORE, 139698990145536, 139698990149631,
	3853	+STORE, 139698990149632, 139698990153727,
	3854	+ERASE, 47933805010944, 47933805010944,
	3855	+STORE, 140737488347136, 140737488351231,
	3856	+STORE, 140725553991680, 140737488351231,
	3857	+ERASE, 140725553991680, 140725553991680,
	3858	+STORE, 140725553991680, 140725553995775,
	3859	+STORE, 93980056248320, 93980056961023,
	3860	+ERASE, 93980056248320, 93980056248320,
	3861	+STORE, 93980056248320, 93980056297471,
	3862	+STORE, 93980056297472, 93980056961023,
	3863	+ERASE, 93980056297472, 93980056297472,
	3864	+STORE, 93980056297472, 93980056842239,
	3865	+STORE, 93980056842240, 93980056940543,
	3866	+STORE, 93980056940544, 93980056961023,
	3867	+STORE, 140146588971008, 140146589143039,
	3868	+ERASE, 140146588971008, 140146588971008,
	3869	+STORE, 140146588971008, 140146588975103,
	3870	+STORE, 140146588975104, 140146589143039,
	3871	+ERASE, 140146588975104, 140146588975104,
	3872	+STORE, 140146588975104, 140146589097983,
	3873	+STORE, 140146589097984, 140146589130751,
	3874	+STORE, 140146589130752, 140146589138943,
	3875	+STORE, 140146589138944, 140146589143039,
	3876	+STORE, 140725554860032, 140725554864127,
	3877	+STORE, 140725554847744, 140725554860031,
	3878	+STORE, 47486206025728, 47486206033919,
	3879	+STORE, 47486206033920, 47486206042111,
	3880	+STORE, 47486206042112, 47486206148607,
	3881	+STORE, 47486206058496, 47486206148607,
	3882	+STORE, 47486206042112, 47486206058495,
	3883	+ERASE, 47486206058496, 47486206058496,
	3884	+STORE, 47486206058496, 47486206132223,
	3885	+STORE, 47486206132224, 47486206148607,
	3886	+STORE, 47486206111744, 47486206132223,
	3887	+STORE, 47486206058496, 47486206111743,
	3888	+ERASE, 47486206058496, 47486206058496,
	3889	+STORE, 47486206058496, 47486206111743,
	3890	+STORE, 47486206128128, 47486206132223,
	3891	+STORE, 47486206111744, 47486206128127,
	3892	+ERASE, 47486206111744, 47486206111744,
	3893	+STORE, 47486206111744, 47486206128127,
	3894	+STORE, 47486206140416, 47486206148607,
	3895	+STORE, 47486206132224, 47486206140415,
	3896	+ERASE, 47486206132224, 47486206132224,
	3897	+STORE, 47486206132224, 47486206140415,
	3898	+ERASE, 47486206140416, 47486206140416,
	3899	+STORE, 47486206140416, 47486206148607,
	3900	+STORE, 47486206148608, 47486207987711,
	3901	+STORE, 47486206287872, 47486207987711,
	3902	+STORE, 47486206148608, 47486206287871,
	3903	+ERASE, 47486206287872, 47486206287872,
	3904	+STORE, 47486206287872, 47486207946751,
	3905	+STORE, 47486207946752, 47486207987711,
	3906	+STORE, 47486207631360, 47486207946751,
	3907	+STORE, 47486206287872, 47486207631359,
	3908	+ERASE, 47486206287872, 47486206287872,
	3909	+STORE, 47486206287872, 47486207631359,
	3910	+STORE, 47486207942656, 47486207946751,
	3911	+STORE, 47486207631360, 47486207942655,
	3912	+ERASE, 47486207631360, 47486207631360,
	3913	+STORE, 47486207631360, 47486207942655,
	3914	+STORE, 47486207971328, 47486207987711,
	3915	+STORE, 47486207946752, 47486207971327,
	3916	+ERASE, 47486207946752, 47486207946752,
	3917	+STORE, 47486207946752, 47486207971327,
	3918	+ERASE, 47486207971328, 47486207971328,
	3919	+STORE, 47486207971328, 47486207987711,
	3920	+STORE, 47486207971328, 47486207999999,
	3921	+ERASE, 47486207946752, 47486207946752,
	3922	+STORE, 47486207946752, 47486207963135,
	3923	+STORE, 47486207963136, 47486207971327,
	3924	+ERASE, 47486206132224, 47486206132224,
	3925	+STORE, 47486206132224, 47486206136319,
	3926	+STORE, 47486206136320, 47486206140415,
	3927	+ERASE, 93980056940544, 93980056940544,
	3928	+STORE, 93980056940544, 93980056956927,
	3929	+STORE, 93980056956928, 93980056961023,
	3930	+ERASE, 140146589130752, 140146589130752,
	3931	+STORE, 140146589130752, 140146589134847,
	3932	+STORE, 140146589134848, 140146589138943,
	3933	+ERASE, 47486206025728, 47486206025728,
	3934	+STORE, 93980070006784, 93980070141951,
	3935	+STORE, 140737488347136, 140737488351231,
	3936	+STORE, 140727334776832, 140737488351231,
	3937	+ERASE, 140727334776832, 140727334776832,
	3938	+STORE, 140727334776832, 140727334780927,
	3939	+STORE, 94049747247104, 94049747959807,
	3940	+ERASE, 94049747247104, 94049747247104,
	3941	+STORE, 94049747247104, 94049747296255,
	3942	+STORE, 94049747296256, 94049747959807,
	3943	+ERASE, 94049747296256, 94049747296256,
	3944	+STORE, 94049747296256, 94049747841023,
	3945	+STORE, 94049747841024, 94049747939327,
	3946	+STORE, 94049747939328, 94049747959807,
	3947	+STORE, 140227307216896, 140227307388927,
	3948	+ERASE, 140227307216896, 140227307216896,
	3949	+STORE, 140227307216896, 140227307220991,
	3950	+STORE, 140227307220992, 140227307388927,
	3951	+ERASE, 140227307220992, 140227307220992,
	3952	+STORE, 140227307220992, 140227307343871,
	3953	+STORE, 140227307343872, 140227307376639,
	3954	+STORE, 140227307376640, 140227307384831,
	3955	+STORE, 140227307384832, 140227307388927,
	3956	+STORE, 140727335337984, 140727335342079,
	3957	+STORE, 140727335325696, 140727335337983,
	3958	+STORE, 47405487779840, 47405487788031,
	3959	+STORE, 47405487788032, 47405487796223,
	3960	+STORE, 47405487796224, 47405487902719,
	3961	+STORE, 47405487812608, 47405487902719,
	3962	+STORE, 47405487796224, 47405487812607,
	3963	+ERASE, 47405487812608, 47405487812608,
	3964	+STORE, 47405487812608, 47405487886335,
	3965	+STORE, 47405487886336, 47405487902719,
	3966	+STORE, 47405487865856, 47405487886335,
	3967	+STORE, 47405487812608, 47405487865855,
	3968	+ERASE, 47405487812608, 47405487812608,
	3969	+STORE, 47405487812608, 47405487865855,
	3970	+STORE, 47405487882240, 47405487886335,
	3971	+STORE, 47405487865856, 47405487882239,
	3972	+ERASE, 47405487865856, 47405487865856,
	3973	+STORE, 47405487865856, 47405487882239,
	3974	+STORE, 47405487894528, 47405487902719,
	3975	+STORE, 47405487886336, 47405487894527,
	3976	+ERASE, 47405487886336, 47405487886336,
	3977	+STORE, 47405487886336, 47405487894527,
	3978	+ERASE, 47405487894528, 47405487894528,
	3979	+STORE, 47405487894528, 47405487902719,
	3980	+STORE, 47405487902720, 47405489741823,
	3981	+STORE, 47405488041984, 47405489741823,
	3982	+STORE, 47405487902720, 47405488041983,
	3983	+ERASE, 47405488041984, 47405488041984,
	3984	+STORE, 47405488041984, 47405489700863,
	3985	+STORE, 47405489700864, 47405489741823,
	3986	+STORE, 47405489385472, 47405489700863,
	3987	+STORE, 47405488041984, 47405489385471,
	3988	+ERASE, 47405488041984, 47405488041984,
	3989	+STORE, 47405488041984, 47405489385471,
	3990	+STORE, 47405489696768, 47405489700863,
	3991	+STORE, 47405489385472, 47405489696767,
	3992	+ERASE, 47405489385472, 47405489385472,
	3993	+STORE, 47405489385472, 47405489696767,
	3994	+STORE, 47405489725440, 47405489741823,
	3995	+STORE, 47405489700864, 47405489725439,
	3996	+ERASE, 47405489700864, 47405489700864,
	3997	+STORE, 47405489700864, 47405489725439,
	3998	+ERASE, 47405489725440, 47405489725440,
	3999	+STORE, 47405489725440, 47405489741823,
	4000	+STORE, 47405489725440, 47405489754111,
	4001	+ERASE, 47405489700864, 47405489700864,
	4002	+STORE, 47405489700864, 47405489717247,
	4003	+STORE, 47405489717248, 47405489725439,
	4004	+ERASE, 47405487886336, 47405487886336,
	4005	+STORE, 47405487886336, 47405487890431,
	4006	+STORE, 47405487890432, 47405487894527,
	4007	+ERASE, 94049747939328, 94049747939328,
	4008	+STORE, 94049747939328, 94049747955711,
	4009	+STORE, 94049747955712, 94049747959807,
	4010	+ERASE, 140227307376640, 140227307376640,
	4011	+STORE, 140227307376640, 140227307380735,
	4012	+STORE, 140227307380736, 140227307384831,
	4013	+ERASE, 47405487779840, 47405487779840,
	4014	+STORE, 94049758810112, 94049758945279,
	4015	+STORE, 140737488347136, 140737488351231,
	4016	+STORE, 140727079718912, 140737488351231,
	4017	+ERASE, 140727079718912, 140727079718912,
	4018	+STORE, 140727079718912, 140727079723007,
	4019	+STORE, 94250996527104, 94250997239807,
	4020	+ERASE, 94250996527104, 94250996527104,
	4021	+STORE, 94250996527104, 94250996576255,
	4022	+STORE, 94250996576256, 94250997239807,
	4023	+ERASE, 94250996576256, 94250996576256,
	4024	+STORE, 94250996576256, 94250997121023,
	4025	+STORE, 94250997121024, 94250997219327,
	4026	+STORE, 94250997219328, 94250997239807,
	4027	+STORE, 140060022587392, 140060022759423,
	4028	+ERASE, 140060022587392, 140060022587392,
	4029	+STORE, 140060022587392, 140060022591487,
	4030	+STORE, 140060022591488, 140060022759423,
	4031	+ERASE, 140060022591488, 140060022591488,
	4032	+STORE, 140060022591488, 140060022714367,
	4033	+STORE, 140060022714368, 140060022747135,
	4034	+STORE, 140060022747136, 140060022755327,
	4035	+STORE, 140060022755328, 140060022759423,
	4036	+STORE, 140727079788544, 140727079792639,
	4037	+STORE, 140727079776256, 140727079788543,
	4038	+/* this next one caused issues when lowering the efficiency */
	4039	+STORE, 47572772409344, 47572772417535,
	4040	+STORE, 47572772417536, 47572772425727,
	4041	+STORE, 47572772425728, 47572772532223,
	4042	+STORE, 47572772442112, 47572772532223,
	4043	+STORE, 47572772425728, 47572772442111,
	4044	+ERASE, 47572772442112, 47572772442112,
	4045	+STORE, 47572772442112, 47572772515839,
	4046	+STORE, 47572772515840, 47572772532223,
	4047	+STORE, 47572772495360, 47572772515839,
	4048	+STORE, 47572772442112, 47572772495359,
	4049	+ERASE, 47572772442112, 47572772442112,
	4050	+STORE, 47572772442112, 47572772495359,
	4051	+STORE, 47572772511744, 47572772515839,
	4052	+STORE, 47572772495360, 47572772511743,
	4053	+ERASE, 47572772495360, 47572772495360,
	4054	+STORE, 47572772495360, 47572772511743,
	4055	+STORE, 47572772524032, 47572772532223,
	4056	+STORE, 47572772515840, 47572772524031,
	4057	+ERASE, 47572772515840, 47572772515840,
	4058	+STORE, 47572772515840, 47572772524031,
	4059	+ERASE, 47572772524032, 47572772524032,
	4060	+STORE, 47572772524032, 47572772532223,
	4061	+STORE, 47572772532224, 47572774371327,
	4062	+STORE, 47572772671488, 47572774371327,
	4063	+STORE, 47572772532224, 47572772671487,
	4064	+ERASE, 47572772671488, 47572772671488,
	4065	+STORE, 47572772671488, 47572774330367,
	4066	+STORE, 47572774330368, 47572774371327,
	4067	+STORE, 47572774014976, 47572774330367,
	4068	+STORE, 47572772671488, 47572774014975,
	4069	+ERASE, 47572772671488, 47572772671488,
	4070	+STORE, 47572772671488, 47572774014975,
	4071	+STORE, 47572774326272, 47572774330367,
	4072	+STORE, 47572774014976, 47572774326271,
	4073	+ERASE, 47572774014976, 47572774014976,
	4074	+STORE, 47572774014976, 47572774326271,
	4075	+STORE, 47572774354944, 47572774371327,
	4076	+STORE, 47572774330368, 47572774354943,
	4077	+ERASE, 47572774330368, 47572774330368,
	4078	+STORE, 47572774330368, 47572774354943,
	4079	+ERASE, 47572774354944, 47572774354944,
	4080	+STORE, 47572774354944, 47572774371327,
	4081	+STORE, 47572774354944, 47572774383615,
	4082	+ERASE, 47572774330368, 47572774330368,
	4083	+STORE, 47572774330368, 47572774346751,
	4084	+STORE, 47572774346752, 47572774354943,
	4085	+ERASE, 47572772515840, 47572772515840,
	4086	+STORE, 47572772515840, 47572772519935,
	4087	+STORE, 47572772519936, 47572772524031,
	4088	+ERASE, 94250997219328, 94250997219328,
	4089	+STORE, 94250997219328, 94250997235711,
	4090	+STORE, 94250997235712, 94250997239807,
	4091	+ERASE, 140060022747136, 140060022747136,
	4092	+STORE, 140060022747136, 140060022751231,
	4093	+STORE, 140060022751232, 140060022755327,
	4094	+ERASE, 47572772409344, 47572772409344,
	4095	+STORE, 94251018305536, 94251018440703,
	4096	+STORE, 140737488347136, 140737488351231,
	4097	+STORE, 140730012389376, 140737488351231,
	4098	+ERASE, 140730012389376, 140730012389376,
	4099	+STORE, 140730012389376, 140730012393471,
	4100	+STORE, 94382607675392, 94382607695871,
	4101	+ERASE, 94382607675392, 94382607675392,
	4102	+STORE, 94382607675392, 94382607679487,
	4103	+STORE, 94382607679488, 94382607695871,
	4104	+ERASE, 94382607679488, 94382607679488,
	4105	+STORE, 94382607679488, 94382607683583,
	4106	+STORE, 94382607683584, 94382607687679,
	4107	+STORE, 94382607687680, 94382607695871,
	4108	+STORE, 140252451454976, 140252451627007,
	4109	+ERASE, 140252451454976, 140252451454976,
	4110	+STORE, 140252451454976, 140252451459071,
	4111	+STORE, 140252451459072, 140252451627007,
	4112	+ERASE, 140252451459072, 140252451459072,
	4113	+STORE, 140252451459072, 140252451581951,
	4114	+STORE, 140252451581952, 140252451614719,
	4115	+STORE, 140252451614720, 140252451622911,
	4116	+STORE, 140252451622912, 140252451627007,
	4117	+STORE, 140730013548544, 140730013552639,
	4118	+STORE, 140730013536256, 140730013548543,
	4119	+STORE, 47380343541760, 47380343549951,
	4120	+STORE, 47380343549952, 47380343558143,
	4121	+STORE, 47380343558144, 47380345397247,
	4122	+STORE, 47380343697408, 47380345397247,
	4123	+STORE, 47380343558144, 47380343697407,
	4124	+ERASE, 47380343697408, 47380343697408,
	4125	+STORE, 47380343697408, 47380345356287,
	4126	+STORE, 47380345356288, 47380345397247,
	4127	+STORE, 47380345040896, 47380345356287,
	4128	+STORE, 47380343697408, 47380345040895,
	4129	+ERASE, 47380343697408, 47380343697408,
	4130	+STORE, 47380343697408, 47380345040895,
	4131	+STORE, 47380345352192, 47380345356287,
	4132	+STORE, 47380345040896, 47380345352191,
	4133	+ERASE, 47380345040896, 47380345040896,
	4134	+STORE, 47380345040896, 47380345352191,
	4135	+STORE, 47380345380864, 47380345397247,
	4136	+STORE, 47380345356288, 47380345380863,
	4137	+ERASE, 47380345356288, 47380345356288,
	4138	+STORE, 47380345356288, 47380345380863,
	4139	+ERASE, 47380345380864, 47380345380864,
	4140	+STORE, 47380345380864, 47380345397247,
	4141	+ERASE, 47380345356288, 47380345356288,
	4142	+STORE, 47380345356288, 47380345372671,
	4143	+STORE, 47380345372672, 47380345380863,
	4144	+ERASE, 94382607687680, 94382607687680,
	4145	+STORE, 94382607687680, 94382607691775,
	4146	+STORE, 94382607691776, 94382607695871,
	4147	+ERASE, 140252451614720, 140252451614720,
	4148	+STORE, 140252451614720, 140252451618815,
	4149	+STORE, 140252451618816, 140252451622911,
	4150	+ERASE, 47380343541760, 47380343541760,
	4151	+STORE, 94382626803712, 94382626938879,
	4152	+STORE, 140737488347136, 140737488351231,
	4153	+STORE, 140730900271104, 140737488351231,
	4154	+ERASE, 140730900271104, 140730900271104,
	4155	+STORE, 140730900271104, 140730900275199,
	4156	+STORE, 93855478120448, 93855478337535,
	4157	+ERASE, 93855478120448, 93855478120448,
	4158	+STORE, 93855478120448, 93855478198271,
	4159	+STORE, 93855478198272, 93855478337535,
	4160	+ERASE, 93855478198272, 93855478198272,
	4161	+STORE, 93855478198272, 93855478243327,
	4162	+STORE, 93855478243328, 93855478288383,
	4163	+STORE, 93855478288384, 93855478337535,
	4164	+STORE, 140092686573568, 140092686745599,
	4165	+ERASE, 140092686573568, 140092686573568,
	4166	+STORE, 140092686573568, 140092686577663,
	4167	+STORE, 140092686577664, 140092686745599,
	4168	+ERASE, 140092686577664, 140092686577664,
	4169	+STORE, 140092686577664, 140092686700543,
	4170	+STORE, 140092686700544, 140092686733311,
	4171	+STORE, 140092686733312, 140092686741503,
	4172	+STORE, 140092686741504, 140092686745599,
	4173	+STORE, 140730900537344, 140730900541439,
	4174	+STORE, 140730900525056, 140730900537343,
	4175	+STORE, 47540108423168, 47540108431359,
	4176	+STORE, 47540108431360, 47540108439551,
	4177	+STORE, 47540108439552, 47540110278655,
	4178	+STORE, 47540108578816, 47540110278655,
	4179	+STORE, 47540108439552, 47540108578815,
	4180	+ERASE, 47540108578816, 47540108578816,
	4181	+STORE, 47540108578816, 47540110237695,
	4182	+STORE, 47540110237696, 47540110278655,
	4183	+STORE, 47540109922304, 47540110237695,
	4184	+STORE, 47540108578816, 47540109922303,
	4185	+ERASE, 47540108578816, 47540108578816,
	4186	+STORE, 47540108578816, 47540109922303,
	4187	+STORE, 47540110233600, 47540110237695,
	4188	+STORE, 47540109922304, 47540110233599,
	4189	+ERASE, 47540109922304, 47540109922304,
	4190	+STORE, 47540109922304, 47540110233599,
	4191	+STORE, 47540110262272, 47540110278655,
	4192	+STORE, 47540110237696, 47540110262271,
	4193	+ERASE, 47540110237696, 47540110237696,
	4194	+STORE, 47540110237696, 47540110262271,
	4195	+ERASE, 47540110262272, 47540110262272,
	4196	+STORE, 47540110262272, 47540110278655,
	4197	+ERASE, 47540110237696, 47540110237696,
	4198	+STORE, 47540110237696, 47540110254079,
	4199	+STORE, 47540110254080, 47540110262271,
	4200	+ERASE, 93855478288384, 93855478288384,
	4201	+STORE, 93855478288384, 93855478333439,
	4202	+STORE, 93855478333440, 93855478337535,
	4203	+ERASE, 140092686733312, 140092686733312,
	4204	+STORE, 140092686733312, 140092686737407,
	4205	+STORE, 140092686737408, 140092686741503,
	4206	+ERASE, 47540108423168, 47540108423168,
	4207	+STORE, 93855492222976, 93855492358143,
	4208	+STORE, 93855492222976, 93855492493311,
	4209	+STORE, 140737488347136, 140737488351231,
	4210	+STORE, 140733498146816, 140737488351231,
	4211	+ERASE, 140733498146816, 140733498146816,
	4212	+STORE, 140733498146816, 140733498150911,
	4213	+STORE, 94170739654656, 94170740367359,
	4214	+ERASE, 94170739654656, 94170739654656,
	4215	+STORE, 94170739654656, 94170739703807,
	4216	+STORE, 94170739703808, 94170740367359,
	4217	+ERASE, 94170739703808, 94170739703808,
	4218	+STORE, 94170739703808, 94170740248575,
	4219	+STORE, 94170740248576, 94170740346879,
	4220	+STORE, 94170740346880, 94170740367359,
	4221	+STORE, 140024788877312, 140024789049343,
	4222	+ERASE, 140024788877312, 140024788877312,
	4223	+STORE, 140024788877312, 140024788881407,
	4224	+STORE, 140024788881408, 140024789049343,
	4225	+ERASE, 140024788881408, 140024788881408,
	4226	+STORE, 140024788881408, 140024789004287,
	4227	+STORE, 140024789004288, 140024789037055,
	4228	+STORE, 140024789037056, 140024789045247,
	4229	+STORE, 140024789045248, 140024789049343,
	4230	+STORE, 140733499023360, 140733499027455,
	4231	+STORE, 140733499011072, 140733499023359,
	4232	+STORE, 47608006119424, 47608006127615,
	4233	+STORE, 47608006127616, 47608006135807,
	4234	+STORE, 47608006135808, 47608006242303,
	4235	+STORE, 47608006152192, 47608006242303,
	4236	+STORE, 47608006135808, 47608006152191,
	4237	+ERASE, 47608006152192, 47608006152192,
	4238	+STORE, 47608006152192, 47608006225919,
	4239	+STORE, 47608006225920, 47608006242303,
	4240	+STORE, 47608006205440, 47608006225919,
	4241	+STORE, 47608006152192, 47608006205439,
	4242	+ERASE, 47608006152192, 47608006152192,
	4243	+STORE, 47608006152192, 47608006205439,
	4244	+STORE, 47608006221824, 47608006225919,
	4245	+STORE, 47608006205440, 47608006221823,
	4246	+ERASE, 47608006205440, 47608006205440,
	4247	+STORE, 47608006205440, 47608006221823,
	4248	+STORE, 47608006234112, 47608006242303,
	4249	+STORE, 47608006225920, 47608006234111,
	4250	+ERASE, 47608006225920, 47608006225920,
	4251	+STORE, 47608006225920, 47608006234111,
	4252	+ERASE, 47608006234112, 47608006234112,
	4253	+STORE, 47608006234112, 47608006242303,
	4254	+STORE, 47608006242304, 47608008081407,
	4255	+STORE, 47608006381568, 47608008081407,
	4256	+STORE, 47608006242304, 47608006381567,
	4257	+ERASE, 47608006381568, 47608006381568,
	4258	+STORE, 47608006381568, 47608008040447,
	4259	+STORE, 47608008040448, 47608008081407,
	4260	+STORE, 47608007725056, 47608008040447,
	4261	+STORE, 47608006381568, 47608007725055,
	4262	+ERASE, 47608006381568, 47608006381568,
	4263	+STORE, 47608006381568, 47608007725055,
	4264	+STORE, 47608008036352, 47608008040447,
	4265	+STORE, 47608007725056, 47608008036351,
	4266	+ERASE, 47608007725056, 47608007725056,
	4267	+STORE, 47608007725056, 47608008036351,
	4268	+STORE, 47608008065024, 47608008081407,
	4269	+STORE, 47608008040448, 47608008065023,
	4270	+ERASE, 47608008040448, 47608008040448,
	4271	+STORE, 47608008040448, 47608008065023,
	4272	+ERASE, 47608008065024, 47608008065024,
	4273	+STORE, 47608008065024, 47608008081407,
	4274	+STORE, 47608008065024, 47608008093695,
	4275	+ERASE, 47608008040448, 47608008040448,
	4276	+STORE, 47608008040448, 47608008056831,
	4277	+STORE, 47608008056832, 47608008065023,
	4278	+ERASE, 47608006225920, 47608006225920,
	4279	+STORE, 47608006225920, 47608006230015,
	4280	+STORE, 47608006230016, 47608006234111,
	4281	+ERASE, 94170740346880, 94170740346880,
	4282	+STORE, 94170740346880, 94170740363263,
	4283	+STORE, 94170740363264, 94170740367359,
	4284	+ERASE, 140024789037056, 140024789037056,
	4285	+STORE, 140024789037056, 140024789041151,
	4286	+STORE, 140024789041152, 140024789045247,
	4287	+ERASE, 47608006119424, 47608006119424,
	4288	+STORE, 140737488347136, 140737488351231,
	4289	+STORE, 140730264326144, 140737488351231,
	4290	+ERASE, 140730264326144, 140730264326144,
	4291	+STORE, 140730264326144, 140730264330239,
	4292	+STORE, 94653216407552, 94653217120255,
	4293	+ERASE, 94653216407552, 94653216407552,
	4294	+STORE, 94653216407552, 94653216456703,
	4295	+STORE, 94653216456704, 94653217120255,
	4296	+ERASE, 94653216456704, 94653216456704,
	4297	+STORE, 94653216456704, 94653217001471,
	4298	+STORE, 94653217001472, 94653217099775,
	4299	+STORE, 94653217099776, 94653217120255,
	4300	+STORE, 140103617011712, 140103617183743,
	4301	+ERASE, 140103617011712, 140103617011712,
	4302	+STORE, 140103617011712, 140103617015807,
	4303	+STORE, 140103617015808, 140103617183743,
	4304	+ERASE, 140103617015808, 140103617015808,
	4305	+STORE, 140103617015808, 140103617138687,
	4306	+STORE, 140103617138688, 140103617171455,
	4307	+STORE, 140103617171456, 140103617179647,
	4308	+STORE, 140103617179648, 140103617183743,
	4309	+STORE, 140730265427968, 140730265432063,
	4310	+STORE, 140730265415680, 140730265427967,
	4311	+STORE, 47529177985024, 47529177993215,
	4312	+STORE, 47529177993216, 47529178001407,
	4313	+STORE, 47529178001408, 47529178107903,
	4314	+STORE, 47529178017792, 47529178107903,
	4315	+STORE, 47529178001408, 47529178017791,
	4316	+ERASE, 47529178017792, 47529178017792,
	4317	+STORE, 47529178017792, 47529178091519,
	4318	+STORE, 47529178091520, 47529178107903,
	4319	+STORE, 47529178071040, 47529178091519,
	4320	+STORE, 47529178017792, 47529178071039,
	4321	+ERASE, 47529178017792, 47529178017792,
	4322	+STORE, 47529178017792, 47529178071039,
	4323	+STORE, 47529178087424, 47529178091519,
	4324	+STORE, 47529178071040, 47529178087423,
	4325	+ERASE, 47529178071040, 47529178071040,
	4326	+STORE, 47529178071040, 47529178087423,
	4327	+STORE, 47529178099712, 47529178107903,
	4328	+STORE, 47529178091520, 47529178099711,
	4329	+ERASE, 47529178091520, 47529178091520,
	4330	+STORE, 47529178091520, 47529178099711,
	4331	+ERASE, 47529178099712, 47529178099712,
	4332	+STORE, 47529178099712, 47529178107903,
	4333	+STORE, 47529178107904, 47529179947007,
	4334	+STORE, 47529178247168, 47529179947007,
	4335	+STORE, 47529178107904, 47529178247167,
	4336	+ERASE, 47529178247168, 47529178247168,
	4337	+STORE, 47529178247168, 47529179906047,
	4338	+STORE, 47529179906048, 47529179947007,
	4339	+STORE, 47529179590656, 47529179906047,
	4340	+STORE, 47529178247168, 47529179590655,
	4341	+ERASE, 47529178247168, 47529178247168,
	4342	+STORE, 47529178247168, 47529179590655,
	4343	+STORE, 47529179901952, 47529179906047,
	4344	+STORE, 47529179590656, 47529179901951,
	4345	+ERASE, 47529179590656, 47529179590656,
	4346	+STORE, 47529179590656, 47529179901951,
	4347	+STORE, 47529179930624, 47529179947007,
	4348	+STORE, 47529179906048, 47529179930623,
	4349	+ERASE, 47529179906048, 47529179906048,
	4350	+STORE, 47529179906048, 47529179930623,
	4351	+ERASE, 47529179930624, 47529179930624,
	4352	+STORE, 47529179930624, 47529179947007,
	4353	+STORE, 47529179930624, 47529179959295,
	4354	+ERASE, 47529179906048, 47529179906048,
	4355	+STORE, 47529179906048, 47529179922431,
	4356	+STORE, 47529179922432, 47529179930623,
	4357	+ERASE, 47529178091520, 47529178091520,
	4358	+STORE, 47529178091520, 47529178095615,
	4359	+STORE, 47529178095616, 47529178099711,
	4360	+ERASE, 94653217099776, 94653217099776,
	4361	+STORE, 94653217099776, 94653217116159,
	4362	+STORE, 94653217116160, 94653217120255,
	4363	+ERASE, 140103617171456, 140103617171456,
	4364	+STORE, 140103617171456, 140103617175551,
	4365	+STORE, 140103617175552, 140103617179647,
	4366	+ERASE, 47529177985024, 47529177985024,
	4367	+STORE, 94653241135104, 94653241270271,
	4368	+STORE, 140737488347136, 140737488351231,
	4369	+STORE, 140736284549120, 140737488351231,
	4370	+ERASE, 140736284549120, 140736284549120,
	4371	+STORE, 140736284549120, 140736284553215,
	4372	+STORE, 93963663822848, 93963664506879,
	4373	+ERASE, 93963663822848, 93963663822848,
	4374	+STORE, 93963663822848, 93963663884287,
	4375	+STORE, 93963663884288, 93963664506879,
	4376	+ERASE, 93963663884288, 93963663884288,
	4377	+STORE, 93963663884288, 93963664240639,
	4378	+STORE, 93963664240640, 93963664379903,
	4379	+STORE, 93963664379904, 93963664506879,
	4380	+STORE, 140450188439552, 140450188611583,
	4381	+ERASE, 140450188439552, 140450188439552,
	4382	+STORE, 140450188439552, 140450188443647,
	4383	+STORE, 140450188443648, 140450188611583,
	4384	+ERASE, 140450188443648, 140450188443648,
	4385	+STORE, 140450188443648, 140450188566527,
	4386	+STORE, 140450188566528, 140450188599295,
	4387	+STORE, 140450188599296, 140450188607487,
	4388	+STORE, 140450188607488, 140450188611583,
	4389	+STORE, 140736284577792, 140736284581887,
	4390	+STORE, 140736284565504, 140736284577791,
	4391	+STORE, 47182606557184, 47182606565375,
	4392	+STORE, 47182606565376, 47182606573567,
	4393	+STORE, 47182606573568, 47182608412671,
	4394	+STORE, 47182606712832, 47182608412671,
	4395	+STORE, 47182606573568, 47182606712831,
	4396	+ERASE, 47182606712832, 47182606712832,
	4397	+STORE, 47182606712832, 47182608371711,
	4398	+STORE, 47182608371712, 47182608412671,
	4399	+STORE, 47182608056320, 47182608371711,
	4400	+STORE, 47182606712832, 47182608056319,
	4401	+ERASE, 47182606712832, 47182606712832,
	4402	+STORE, 47182606712832, 47182608056319,
	4403	+STORE, 47182608367616, 47182608371711,
	4404	+STORE, 47182608056320, 47182608367615,
	4405	+ERASE, 47182608056320, 47182608056320,
	4406	+STORE, 47182608056320, 47182608367615,
	4407	+STORE, 47182608396288, 47182608412671,
	4408	+STORE, 47182608371712, 47182608396287,
	4409	+ERASE, 47182608371712, 47182608371712,
	4410	+STORE, 47182608371712, 47182608396287,
	4411	+ERASE, 47182608396288, 47182608396288,
	4412	+STORE, 47182608396288, 47182608412671,
	4413	+STORE, 47182608412672, 47182608523263,
	4414	+STORE, 47182608429056, 47182608523263,
	4415	+STORE, 47182608412672, 47182608429055,
	4416	+ERASE, 47182608429056, 47182608429056,
	4417	+STORE, 47182608429056, 47182608515071,
	4418	+STORE, 47182608515072, 47182608523263,
	4419	+STORE, 47182608490496, 47182608515071,
	4420	+STORE, 47182608429056, 47182608490495,
	4421	+ERASE, 47182608429056, 47182608429056,
	4422	+STORE, 47182608429056, 47182608490495,
	4423	+STORE, 47182608510976, 47182608515071,
	4424	+STORE, 47182608490496, 47182608510975,
	4425	+ERASE, 47182608490496, 47182608490496,
	4426	+STORE, 47182608490496, 47182608510975,
	4427	+ERASE, 47182608515072, 47182608515072,
	4428	+STORE, 47182608515072, 47182608523263,
	4429	+STORE, 47182608523264, 47182608568319,
	4430	+ERASE, 47182608523264, 47182608523264,
	4431	+STORE, 47182608523264, 47182608531455,
	4432	+STORE, 47182608531456, 47182608568319,
	4433	+STORE, 47182608551936, 47182608568319,
	4434	+STORE, 47182608531456, 47182608551935,
	4435	+ERASE, 47182608531456, 47182608531456,
	4436	+STORE, 47182608531456, 47182608551935,
	4437	+STORE, 47182608560128, 47182608568319,
	4438	+STORE, 47182608551936, 47182608560127,
	4439	+ERASE, 47182608551936, 47182608551936,
	4440	+STORE, 47182608551936, 47182608568319,
	4441	+ERASE, 47182608551936, 47182608551936,
	4442	+STORE, 47182608551936, 47182608560127,
	4443	+STORE, 47182608560128, 47182608568319,
	4444	+ERASE, 47182608560128, 47182608560128,
	4445	+STORE, 47182608560128, 47182608568319,
	4446	+STORE, 47182608568320, 47182608916479,
	4447	+STORE, 47182608609280, 47182608916479,
	4448	+STORE, 47182608568320, 47182608609279,
	4449	+ERASE, 47182608609280, 47182608609280,
	4450	+STORE, 47182608609280, 47182608891903,
	4451	+STORE, 47182608891904, 47182608916479,
	4452	+STORE, 47182608822272, 47182608891903,
	4453	+STORE, 47182608609280, 47182608822271,
	4454	+ERASE, 47182608609280, 47182608609280,
	4455	+STORE, 47182608609280, 47182608822271,
	4456	+STORE, 47182608887808, 47182608891903,
	4457	+STORE, 47182608822272, 47182608887807,
	4458	+ERASE, 47182608822272, 47182608822272,
	4459	+STORE, 47182608822272, 47182608887807,
	4460	+ERASE, 47182608891904, 47182608891904,
	4461	+STORE, 47182608891904, 47182608916479,
	4462	+STORE, 47182608916480, 47182611177471,
	4463	+STORE, 47182609068032, 47182611177471,
	4464	+STORE, 47182608916480, 47182609068031,
	4465	+ERASE, 47182609068032, 47182609068032,
	4466	+STORE, 47182609068032, 47182611161087,
	4467	+STORE, 47182611161088, 47182611177471,
	4468	+STORE, 47182611169280, 47182611177471,
	4469	+STORE, 47182611161088, 47182611169279,
	4470	+ERASE, 47182611161088, 47182611161088,
	4471	+STORE, 47182611161088, 47182611169279,
	4472	+ERASE, 47182611169280, 47182611169280,
	4473	+STORE, 47182611169280, 47182611177471,
	4474	+STORE, 47182611177472, 47182611312639,
	4475	+ERASE, 47182611177472, 47182611177472,
	4476	+STORE, 47182611177472, 47182611202047,
	4477	+STORE, 47182611202048, 47182611312639,
	4478	+STORE, 47182611263488, 47182611312639,
	4479	+STORE, 47182611202048, 47182611263487,
	4480	+ERASE, 47182611202048, 47182611202048,
	4481	+STORE, 47182611202048, 47182611263487,
	4482	+STORE, 47182611288064, 47182611312639,
	4483	+STORE, 47182611263488, 47182611288063,
	4484	+ERASE, 47182611263488, 47182611263488,
	4485	+STORE, 47182611263488, 47182611312639,
	4486	+ERASE, 47182611263488, 47182611263488,
	4487	+STORE, 47182611263488, 47182611288063,
	4488	+STORE, 47182611288064, 47182611312639,
	4489	+STORE, 47182611296256, 47182611312639,
	4490	+STORE, 47182611288064, 47182611296255,
	4491	+ERASE, 47182611288064, 47182611288064,
	4492	+STORE, 47182611288064, 47182611296255,
	4493	+ERASE, 47182611296256, 47182611296256,
	4494	+STORE, 47182611296256, 47182611312639,
	4495	+STORE, 47182611296256, 47182611320831,
	4496	+STORE, 47182611320832, 47182611484671,
	4497	+ERASE, 47182611320832, 47182611320832,
	4498	+STORE, 47182611320832, 47182611333119,
	4499	+STORE, 47182611333120, 47182611484671,
	4500	+STORE, 47182611431424, 47182611484671,
	4501	+STORE, 47182611333120, 47182611431423,
	4502	+ERASE, 47182611333120, 47182611333120,
	4503	+STORE, 47182611333120, 47182611431423,
	4504	+STORE, 47182611476480, 47182611484671,
	4505	+STORE, 47182611431424, 47182611476479,
	4506	+ERASE, 47182611431424, 47182611431424,
	4507	+STORE, 47182611431424, 47182611484671,
	4508	+ERASE, 47182611431424, 47182611431424,
	4509	+STORE, 47182611431424, 47182611476479,
	4510	+STORE, 47182611476480, 47182611484671,
	4511	+ERASE, 47182611476480, 47182611476480,
	4512	+STORE, 47182611476480, 47182611484671,
	4513	+STORE, 47182611484672, 47182612082687,
	4514	+STORE, 47182611603456, 47182612082687,
	4515	+STORE, 47182611484672, 47182611603455,
	4516	+ERASE, 47182611603456, 47182611603456,
	4517	+STORE, 47182611603456, 47182612029439,
	4518	+STORE, 47182612029440, 47182612082687,
	4519	+STORE, 47182611918848, 47182612029439,
	4520	+STORE, 47182611603456, 47182611918847,
	4521	+ERASE, 47182611603456, 47182611603456,
	4522	+STORE, 47182611603456, 47182611918847,
	4523	+STORE, 47182612025344, 47182612029439,
	4524	+STORE, 47182611918848, 47182612025343,
	4525	+ERASE, 47182611918848, 47182611918848,
	4526	+STORE, 47182611918848, 47182612025343,
	4527	+ERASE, 47182612029440, 47182612029440,
	4528	+STORE, 47182612029440, 47182612082687,
	4529	+STORE, 47182612082688, 47182615134207,
	4530	+STORE, 47182612627456, 47182615134207,
	4531	+STORE, 47182612082688, 47182612627455,
	4532	+ERASE, 47182612627456, 47182612627456,
	4533	+STORE, 47182612627456, 47182614913023,
	4534	+STORE, 47182614913024, 47182615134207,
	4535	+STORE, 47182614323200, 47182614913023,
	4536	+STORE, 47182612627456, 47182614323199,
	4537	+ERASE, 47182612627456, 47182612627456,
	4538	+STORE, 47182612627456, 47182614323199,
	4539	+STORE, 47182614908928, 47182614913023,
	4540	+STORE, 47182614323200, 47182614908927,
	4541	+ERASE, 47182614323200, 47182614323200,
	4542	+STORE, 47182614323200, 47182614908927,
	4543	+STORE, 47182615117824, 47182615134207,
	4544	+STORE, 47182614913024, 47182615117823,
	4545	+ERASE, 47182614913024, 47182614913024,
	4546	+STORE, 47182614913024, 47182615117823,
	4547	+ERASE, 47182615117824, 47182615117824,
	4548	+STORE, 47182615117824, 47182615134207,
	4549	+STORE, 47182615134208, 47182615166975,
	4550	+ERASE, 47182615134208, 47182615134208,
	4551	+STORE, 47182615134208, 47182615142399,
	4552	+STORE, 47182615142400, 47182615166975,
	4553	+STORE, 47182615154688, 47182615166975,
	4554	+STORE, 47182615142400, 47182615154687,
	4555	+ERASE, 47182615142400, 47182615142400,
	4556	+STORE, 47182615142400, 47182615154687,
	4557	+STORE, 47182615158784, 47182615166975,
	4558	+STORE, 47182615154688, 47182615158783,
	4559	+ERASE, 47182615154688, 47182615154688,
	4560	+STORE, 47182615154688, 47182615166975,
	4561	+ERASE, 47182615154688, 47182615154688,
	4562	+STORE, 47182615154688, 47182615158783,
	4563	+STORE, 47182615158784, 47182615166975,
	4564	+ERASE, 47182615158784, 47182615158784,
	4565	+STORE, 47182615158784, 47182615166975,
	4566	+STORE, 47182615166976, 47182615203839,
	4567	+ERASE, 47182615166976, 47182615166976,
	4568	+STORE, 47182615166976, 47182615175167,
	4569	+STORE, 47182615175168, 47182615203839,
	4570	+STORE, 47182615191552, 47182615203839,
	4571	+STORE, 47182615175168, 47182615191551,
	4572	+ERASE, 47182615175168, 47182615175168,
	4573	+STORE, 47182615175168, 47182615191551,
	4574	+STORE, 47182615195648, 47182615203839,
	4575	+STORE, 47182615191552, 47182615195647,
	4576	+ERASE, 47182615191552, 47182615191552,
	4577	+STORE, 47182615191552, 47182615203839,
	4578	+ERASE, 47182615191552, 47182615191552,
	4579	+STORE, 47182615191552, 47182615195647,
	4580	+STORE, 47182615195648, 47182615203839,
	4581	+ERASE, 47182615195648, 47182615195648,
	4582	+STORE, 47182615195648, 47182615203839,
	4583	+STORE, 47182615203840, 47182615678975,
	4584	+ERASE, 47182615203840, 47182615203840,
	4585	+STORE, 47182615203840, 47182615212031,
	4586	+STORE, 47182615212032, 47182615678975,
	4587	+STORE, 47182615547904, 47182615678975,
	4588	+STORE, 47182615212032, 47182615547903,
	4589	+ERASE, 47182615212032, 47182615212032,
	4590	+STORE, 47182615212032, 47182615547903,
	4591	+STORE, 47182615670784, 47182615678975,
	4592	+STORE, 47182615547904, 47182615670783,
	4593	+ERASE, 47182615547904, 47182615547904,
	4594	+STORE, 47182615547904, 47182615678975,
	4595	+ERASE, 47182615547904, 47182615547904,
	4596	+STORE, 47182615547904, 47182615670783,
	4597	+STORE, 47182615670784, 47182615678975,
	4598	+ERASE, 47182615670784, 47182615670784,
	4599	+STORE, 47182615670784, 47182615678975,
	4600	+STORE, 47182615678976, 47182615687167,
	4601	+STORE, 47182615687168, 47182615707647,
	4602	+ERASE, 47182615687168, 47182615687168,
	4603	+STORE, 47182615687168, 47182615691263,
	4604	+STORE, 47182615691264, 47182615707647,
	4605	+STORE, 47182615695360, 47182615707647,
	4606	+STORE, 47182615691264, 47182615695359,
	4607	+ERASE, 47182615691264, 47182615691264,
	4608	+STORE, 47182615691264, 47182615695359,
	4609	+STORE, 47182615699456, 47182615707647,
	4610	+STORE, 47182615695360, 47182615699455,
	4611	+ERASE, 47182615695360, 47182615695360,
	4612	+STORE, 47182615695360, 47182615707647,
	4613	+ERASE, 47182615695360, 47182615695360,
	4614	+STORE, 47182615695360, 47182615699455,
	4615	+STORE, 47182615699456, 47182615707647,
	4616	+ERASE, 47182615699456, 47182615699456,
	4617	+STORE, 47182615699456, 47182615707647,
	4618	+STORE, 47182615707648, 47182615715839,
	4619	+ERASE, 47182608371712, 47182608371712,
	4620	+STORE, 47182608371712, 47182608388095,
	4621	+STORE, 47182608388096, 47182608396287,
	4622	+ERASE, 47182615699456, 47182615699456,
	4623	+STORE, 47182615699456, 47182615703551,
	4624	+STORE, 47182615703552, 47182615707647,
	4625	+ERASE, 47182611288064, 47182611288064,
	4626	+STORE, 47182611288064, 47182611292159,
	4627	+STORE, 47182611292160, 47182611296255,
	4628	+ERASE, 47182615670784, 47182615670784,
	4629	+STORE, 47182615670784, 47182615674879,
	4630	+STORE, 47182615674880, 47182615678975,
	4631	+ERASE, 47182615195648, 47182615195648,
	4632	+STORE, 47182615195648, 47182615199743,
	4633	+STORE, 47182615199744, 47182615203839,
	4634	+ERASE, 47182615158784, 47182615158784,
	4635	+STORE, 47182615158784, 47182615162879,
	4636	+STORE, 47182615162880, 47182615166975,
	4637	+ERASE, 47182614913024, 47182614913024,
	4638	+STORE, 47182614913024, 47182615109631,
	4639	+STORE, 47182615109632, 47182615117823,
	4640	+ERASE, 47182612029440, 47182612029440,
	4641	+STORE, 47182612029440, 47182612066303,
	4642	+STORE, 47182612066304, 47182612082687,
	4643	+ERASE, 47182611476480, 47182611476480,
	4644	+STORE, 47182611476480, 47182611480575,
	4645	+STORE, 47182611480576, 47182611484671,
	4646	+ERASE, 47182611161088, 47182611161088,
	4647	+STORE, 47182611161088, 47182611165183,
	4648	+STORE, 47182611165184, 47182611169279,
	4649	+ERASE, 47182608891904, 47182608891904,
	4650	+STORE, 47182608891904, 47182608912383,
	4651	+STORE, 47182608912384, 47182608916479,
	4652	+ERASE, 47182608560128, 47182608560128,
	4653	+STORE, 47182608560128, 47182608564223,
	4654	+STORE, 47182608564224, 47182608568319,
	4655	+ERASE, 47182608515072, 47182608515072,
	4656	+STORE, 47182608515072, 47182608519167,
	4657	+STORE, 47182608519168, 47182608523263,
	4658	+ERASE, 93963664379904, 93963664379904,
	4659	+STORE, 93963664379904, 93963664502783,
	4660	+STORE, 93963664502784, 93963664506879,
	4661	+ERASE, 140450188599296, 140450188599296,
	4662	+STORE, 140450188599296, 140450188603391,
	4663	+STORE, 140450188603392, 140450188607487,
	4664	+ERASE, 47182606557184, 47182606557184,
	4665	+STORE, 93963694723072, 93963694858239,
	4666	+STORE, 140737488347136, 140737488351231,
	4667	+STORE, 140730313261056, 140737488351231,
	4668	+ERASE, 140730313261056, 140730313261056,
	4669	+STORE, 140730313261056, 140730313265151,
	4670	+STORE, 94386579017728, 94386579697663,
	4671	+ERASE, 94386579017728, 94386579017728,
	4672	+STORE, 94386579017728, 94386579083263,
	4673	+STORE, 94386579083264, 94386579697663,
	4674	+ERASE, 94386579083264, 94386579083264,
	4675	+STORE, 94386579083264, 94386579431423,
	4676	+STORE, 94386579431424, 94386579570687,
	4677	+STORE, 94386579570688, 94386579697663,
	4678	+STORE, 140124810838016, 140124811010047,
	4679	+ERASE, 140124810838016, 140124810838016,
	4680	+STORE, 140124810838016, 140124810842111,
	4681	+STORE, 140124810842112, 140124811010047,
	4682	+ERASE, 140124810842112, 140124810842112,
	4683	+STORE, 140124810842112, 140124810964991,
	4684	+STORE, 140124810964992, 140124810997759,
	4685	+STORE, 140124810997760, 140124811005951,
	4686	+STORE, 140124811005952, 140124811010047,
	4687	+STORE, 140730313601024, 140730313605119,
	4688	+STORE, 140730313588736, 140730313601023,
	4689	+STORE, 47507984158720, 47507984166911,
	4690	+STORE, 47507984166912, 47507984175103,
	4691	+STORE, 47507984175104, 47507986014207,
	4692	+STORE, 47507984314368, 47507986014207,
	4693	+STORE, 47507984175104, 47507984314367,
	4694	+ERASE, 47507984314368, 47507984314368,
	4695	+STORE, 47507984314368, 47507985973247,
	4696	+STORE, 47507985973248, 47507986014207,

31104 more lines aren’t shown here.

tools/testing/selftests/bpf/verifier/ref_tracking.c+36−0

This diff is large: its 40 lines aren’t shown here.

tools/testing/selftests/net/io_uring_zerocopy_tx.sh+1−1

This diff is large: its 9 lines aren’t shown here.

tools/testing/selftests/net/udpgro.sh+2−2

This diff is large: its 18 lines aren’t shown here.

tools/testing/selftests/net/udpgro_bench.sh+1−1

This diff is large: its 9 lines aren’t shown here.

tools/testing/selftests/net/udpgro_frglist.sh+1−1

This diff is large: its 9 lines aren’t shown here.

tools/testing/selftests/netfilter/rpath.sh+8−6

This diff is large: its 35 lines aren’t shown here.