History

Merge branch 'mlx5-next' of https://git.kernel.org/pub/scm/linux/kernel/git/mellanox/linux

Leon Romanovsky says: ==================== Mellanox shared branch that includes: * Removal of FPGA TLS code https://lore.kernel.org/all/cover.1649073691.git.leonro@nvidia.com Mellanox INNOVA TLS cards are EOL in May, 2018 [1]. As such, the code is unmaintained, untested and not in-use by any upstream/distro oriented customers. In order to reduce code complexity, drop the kernel code, clean build config options and delete useless kTLS vs. TLS separation. [1] https://network.nvidia.com/related-docs/eol/LCR-000286.pdf * Removal of FPGA IPsec code https://lore.kernel.org/all/cover.1649232994.git.leonro@nvidia.com Together with FPGA TLS, the IPsec went to EOL state in the November of 2019 [1]. Exactly like FPGA TLS, no active customers exist for this upstream code and all the complexity around that area can be deleted. [2] https://network.nvidia.com/related-docs/eol/LCR-000535.pdf * Fix to undefined behavior from Borislav https://lore.kernel.org/all/20220405151517.29753-11-bp@alien8.de ==================== * 'mlx5-next' of https://git.kernel.org/pub/scm/linux/kernel/git/mellanox/linux: net/mlx5: Remove not-implemented IPsec capabilities net/mlx5: Remove ipsec_ops function table net/mlx5: Reduce kconfig complexity while building crypto support net/mlx5: Move IPsec file to relevant directory net/mlx5: Remove not-needed IPsec config net/mlx5: Align flow steering allocation namespace to common style net/mlx5: Unify device IPsec capabilities check net/mlx5: Remove useless IPsec device checks net/mlx5: Remove ipsec vs. ipsec offload file separation RDMA/core: Delete IPsec flow action logic from the core RDMA/mlx5: Drop crypto flow steering API RDMA/mlx5: Delete never supported IPsec flow action net/mlx5: Remove FPGA ipsec specific statistics net/mlx5: Remove XFRM no_trailer flag net/mlx5: Remove not-used IDA field from IPsec struct net/mlx5: Delete metadata handling logic net/mlx5_fpga: Drop INNOVA IPsec support IB/mlx5: Fix undefined behavior due to shift overflowing the constant net/mlx5: Cleanup kTLS function names and their exposure net/mlx5: Remove tls vs. ktls separation as it is the same net/mlx5: Remove indirection in TLS build net/mlx5: Reliably return TLS device capabilities net/mlx5_fpga: Drop INNOVA TLS support

Jason Gunthorpe committed 4 years ago

Commit 7bf53232 parents 6f4f5cf 298428754 files · +364 −5354Browse files

Showing the changes to include (5 of 54 files). Show all

Unified · Split

5 files
  1. include/linux/mlx5/accel.h +16 −19
  2. include/linux/mlx5/driver.h +0 −3
  3. include/linux/mlx5/mlx5_ifc_fpga.h +0 −211
  4. include/linux/mlx5/port.h +1 −1
  5. include/rdma/ib_verbs.h +0 −8
include/linux/mlx5/accel.h+16−19
@@ -111,46 +111,43 @@ struct mlx5_accel_esp_xfrm { · 110 unmodified lines
111111 struct mlx5_accel_esp_xfrm_attrs attrs;
112112 };
113113
114−enum {
115− MLX5_ACCEL_XFRM_FLAG_REQUIRE_METADATA = 1UL << 0,
116−};
117−
118114 enum mlx5_accel_ipsec_cap {
119115 MLX5_ACCEL_IPSEC_CAP_DEVICE = 1 << 0,
120− MLX5_ACCEL_IPSEC_CAP_REQUIRED_METADATA = 1 << 1,
121− MLX5_ACCEL_IPSEC_CAP_ESP = 1 << 2,
122− MLX5_ACCEL_IPSEC_CAP_IPV6 = 1 << 3,
123− MLX5_ACCEL_IPSEC_CAP_LSO = 1 << 4,
124− MLX5_ACCEL_IPSEC_CAP_RX_NO_TRAILER = 1 << 5,
125− MLX5_ACCEL_IPSEC_CAP_ESN = 1 << 6,
126− MLX5_ACCEL_IPSEC_CAP_TX_IV_IS_ESN = 1 << 7,
116+ MLX5_ACCEL_IPSEC_CAP_ESP = 1 << 1,
117+ MLX5_ACCEL_IPSEC_CAP_IPV6 = 1 << 2,
118+ MLX5_ACCEL_IPSEC_CAP_LSO = 1 << 3,
119+ MLX5_ACCEL_IPSEC_CAP_ESN = 1 << 4,
127120 };
128121
129−#ifdef CONFIG_MLX5_ACCEL
122+#ifdef CONFIG_MLX5_EN_IPSEC
130123
131−u32 mlx5_accel_ipsec_device_caps(struct mlx5_core_dev *mdev);
124+u32 mlx5_ipsec_device_caps(struct mlx5_core_dev *mdev);
132125
133126 struct mlx5_accel_esp_xfrm *
134127 mlx5_accel_esp_create_xfrm(struct mlx5_core_dev *mdev,
135− const struct mlx5_accel_esp_xfrm_attrs *attrs,
136− u32 flags);
128+ const struct mlx5_accel_esp_xfrm_attrs *attrs);
137129 void mlx5_accel_esp_destroy_xfrm(struct mlx5_accel_esp_xfrm *xfrm);
138130 int mlx5_accel_esp_modify_xfrm(struct mlx5_accel_esp_xfrm *xfrm,
139131 const struct mlx5_accel_esp_xfrm_attrs *attrs);
140132
141133 #else
142134
143−static inline u32 mlx5_accel_ipsec_device_caps(struct mlx5_core_dev *mdev) { return 0; }
135+static inline u32 mlx5_ipsec_device_caps(struct mlx5_core_dev *mdev)
136+{
137+ return 0;
138+}
144139
145140 static inline struct mlx5_accel_esp_xfrm *
146141 mlx5_accel_esp_create_xfrm(struct mlx5_core_dev *mdev,
147− const struct mlx5_accel_esp_xfrm_attrs *attrs,
148− u32 flags) { return ERR_PTR(-EOPNOTSUPP); }
142+ const struct mlx5_accel_esp_xfrm_attrs *attrs)
143+{
144+ return ERR_PTR(-EOPNOTSUPP);
145+}
149146 static inline void
150147 mlx5_accel_esp_destroy_xfrm(struct mlx5_accel_esp_xfrm *xfrm) {}
151148 static inline int
152149 mlx5_accel_esp_modify_xfrm(struct mlx5_accel_esp_xfrm *xfrm,
153150 const struct mlx5_accel_esp_xfrm_attrs *attrs) { return -EOPNOTSUPP; }
154151
155−#endif /* CONFIG_MLX5_ACCEL */
152+#endif /* CONFIG_MLX5_EN_IPSEC */
156153 #endif /* __MLX5_ACCEL_H__ */
include/linux/mlx5/driver.h+0−3
@@ -777,9 +777,6 @@ struct mlx5_core_dev { · 776 unmodified lines
777777 } roce;
778778 #ifdef CONFIG_MLX5_FPGA
779779 struct mlx5_fpga_device *fpga;
780−#endif
781−#ifdef CONFIG_MLX5_ACCEL
782− const struct mlx5_accel_ipsec_ops *ipsec_ops;
783780 #endif
784781 struct mlx5_clock clock;
785782 struct mlx5_ib_clock_info *clock_info;
include/linux/mlx5/mlx5_ifc_fpga.h+0−211
@@ -54,7 +54,6 @@ enum { · 53 unmodified lines
5454
5555 enum {
5656 MLX5_FPGA_CAP_SANDBOX_PRODUCT_ID_IPSEC = 0x2,
57− MLX5_FPGA_CAP_SANDBOX_PRODUCT_ID_TLS = 0x3,
5857 };
5958
6059 struct mlx5_ifc_fpga_shell_caps_bits {
@@ -387,89 +386,6 @@ struct mlx5_ifc_fpga_destroy_qp_out_bits { · 326 unmodified lines
387386 u8 reserved_at_40[0x40];
388387 };
389388
390−struct mlx5_ifc_tls_extended_cap_bits {
391− u8 aes_gcm_128[0x1];
392− u8 aes_gcm_256[0x1];
393− u8 reserved_at_2[0x1e];
394− u8 reserved_at_20[0x20];
395− u8 context_capacity_total[0x20];
396− u8 context_capacity_rx[0x20];
397− u8 context_capacity_tx[0x20];
398− u8 reserved_at_a0[0x10];
399− u8 tls_counter_size[0x10];
400− u8 tls_counters_addr_low[0x20];
401− u8 tls_counters_addr_high[0x20];
402− u8 rx[0x1];
403− u8 tx[0x1];
404− u8 tls_v12[0x1];
405− u8 tls_v13[0x1];
406− u8 lro[0x1];
407− u8 ipv6[0x1];
408− u8 reserved_at_106[0x1a];
409−};
410−
411−struct mlx5_ifc_ipsec_extended_cap_bits {
412− u8 encapsulation[0x20];
413−
414− u8 reserved_0[0x12];
415− u8 v2_command[0x1];
416− u8 udp_encap[0x1];
417− u8 rx_no_trailer[0x1];
418− u8 ipv4_fragment[0x1];
419− u8 ipv6[0x1];
420− u8 esn[0x1];
421− u8 lso[0x1];
422− u8 transport_and_tunnel_mode[0x1];
423− u8 tunnel_mode[0x1];
424− u8 transport_mode[0x1];
425− u8 ah_esp[0x1];
426− u8 esp[0x1];
427− u8 ah[0x1];
428− u8 ipv4_options[0x1];
429−
430− u8 auth_alg[0x20];
431−
432− u8 enc_alg[0x20];
433−
434− u8 sa_cap[0x20];
435−
436− u8 reserved_1[0x10];
437− u8 number_of_ipsec_counters[0x10];
438−
439− u8 ipsec_counters_addr_low[0x20];
440− u8 ipsec_counters_addr_high[0x20];
441−};
442−
443−struct mlx5_ifc_ipsec_counters_bits {
444− u8 dec_in_packets[0x40];
445−
446− u8 dec_out_packets[0x40];
447−
448− u8 dec_bypass_packets[0x40];
449−
450− u8 enc_in_packets[0x40];
451−
452− u8 enc_out_packets[0x40];
453−
454− u8 enc_bypass_packets[0x40];
455−
456− u8 drop_dec_packets[0x40];
457−
458− u8 failed_auth_dec_packets[0x40];
459−
460− u8 drop_enc_packets[0x40];
461−
462− u8 success_add_sa[0x40];
463−
464− u8 fail_add_sa[0x40];
465−
466− u8 success_delete_sa[0x40];
467−
468− u8 fail_delete_sa[0x40];
469−
470− u8 dropped_cmd[0x40];
471−};
472−
473389 enum {
474390 MLX5_FPGA_QP_ERROR_EVENT_SYNDROME_RETRY_COUNTER_EXPIRED = 0x1,
475391 MLX5_FPGA_QP_ERROR_EVENT_SYNDROME_RNR_EXPIRED = 0x2,
@@ -486,131 +402,4 @@ struct mlx5_ifc_fpga_qp_error_event_bits { · 10 unmodified lines
486402 u8 reserved_at_c0[0x8];
487403 u8 fpga_qpn[0x18];
488404 };
489−enum mlx5_ifc_fpga_ipsec_response_syndrome {
490− MLX5_FPGA_IPSEC_RESPONSE_SUCCESS = 0,
491− MLX5_FPGA_IPSEC_RESPONSE_ILLEGAL_REQUEST = 1,
492− MLX5_FPGA_IPSEC_RESPONSE_SADB_ISSUE = 2,
493− MLX5_FPGA_IPSEC_RESPONSE_WRITE_RESPONSE_ISSUE = 3,
494−};
495−
496−struct mlx5_ifc_fpga_ipsec_cmd_resp {
497− __be32 syndrome;
498− union {
499− __be32 sw_sa_handle;
500− __be32 flags;
501− };
502− u8 reserved[24];
503−} __packed;
504−
505−enum mlx5_ifc_fpga_ipsec_cmd_opcode {
506− MLX5_FPGA_IPSEC_CMD_OP_ADD_SA = 0,
507− MLX5_FPGA_IPSEC_CMD_OP_DEL_SA = 1,
508− MLX5_FPGA_IPSEC_CMD_OP_ADD_SA_V2 = 2,
509− MLX5_FPGA_IPSEC_CMD_OP_DEL_SA_V2 = 3,
510− MLX5_FPGA_IPSEC_CMD_OP_MOD_SA_V2 = 4,
511− MLX5_FPGA_IPSEC_CMD_OP_SET_CAP = 5,
512−};
513−
514−enum mlx5_ifc_fpga_ipsec_cap {
515− MLX5_FPGA_IPSEC_CAP_NO_TRAILER = BIT(0),
516−};
517−
518−struct mlx5_ifc_fpga_ipsec_cmd_cap {
519− __be32 cmd;
520− __be32 flags;
521− u8 reserved[24];
522−} __packed;
523−
524−enum mlx5_ifc_fpga_ipsec_sa_flags {
525− MLX5_FPGA_IPSEC_SA_ESN_EN = BIT(0),
526− MLX5_FPGA_IPSEC_SA_ESN_OVERLAP = BIT(1),
527− MLX5_FPGA_IPSEC_SA_IPV6 = BIT(2),
528− MLX5_FPGA_IPSEC_SA_DIR_SX = BIT(3),
529− MLX5_FPGA_IPSEC_SA_SPI_EN = BIT(4),
530− MLX5_FPGA_IPSEC_SA_SA_VALID = BIT(5),
531− MLX5_FPGA_IPSEC_SA_IP_ESP = BIT(6),
532− MLX5_FPGA_IPSEC_SA_IP_AH = BIT(7),
533−};
534−
535−enum mlx5_ifc_fpga_ipsec_sa_enc_mode {
536− MLX5_FPGA_IPSEC_SA_ENC_MODE_NONE = 0,
537− MLX5_FPGA_IPSEC_SA_ENC_MODE_AES_GCM_128_AUTH_128 = 1,
538− MLX5_FPGA_IPSEC_SA_ENC_MODE_AES_GCM_256_AUTH_128 = 3,
539−};
540−
541−struct mlx5_ifc_fpga_ipsec_sa_v1 {
542− __be32 cmd;
543− u8 key_enc[32];
544− u8 key_auth[32];
545− __be32 sip[4];
546− __be32 dip[4];
547− union {
548− struct {
549− __be32 reserved;
550− u8 salt_iv[8];
551− __be32 salt;
552− } __packed gcm;
553− struct {
554− u8 salt[16];
555− } __packed cbc;
556− };
557− __be32 spi;
558− __be32 sw_sa_handle;
559− __be16 tfclen;
560− u8 enc_mode;
561− u8 reserved1[2];
562− u8 flags;
563− u8 reserved2[2];
564−};
565−
566−struct mlx5_ifc_fpga_ipsec_sa {
567− struct mlx5_ifc_fpga_ipsec_sa_v1 ipsec_sa_v1;
568− __be16 udp_sp;
569− __be16 udp_dp;
570− u8 reserved1[4];
571− __be32 esn;
572− __be16 vid; /* only 12 bits, rest is reserved */
573− __be16 reserved2;
574−} __packed;
575−
576−enum fpga_tls_cmds {
577− CMD_SETUP_STREAM = 0x1001,
578− CMD_TEARDOWN_STREAM = 0x1002,
579− CMD_RESYNC_RX = 0x1003,
580−};
581−
582−#define MLX5_TLS_1_2 (0)
583−
584−#define MLX5_TLS_ALG_AES_GCM_128 (0)
585−#define MLX5_TLS_ALG_AES_GCM_256 (1)
586−
587−struct mlx5_ifc_tls_cmd_bits {
588− u8 command_type[0x20];
589− u8 ipv6[0x1];
590− u8 direction_sx[0x1];
591− u8 tls_version[0x2];
592− u8 reserved[0x1c];
593− u8 swid[0x20];
594− u8 src_port[0x10];
595− u8 dst_port[0x10];
596− union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits src_ipv4_src_ipv6;
597− union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits dst_ipv4_dst_ipv6;
598− u8 tls_rcd_sn[0x40];
599− u8 tcp_sn[0x20];
600− u8 tls_implicit_iv[0x20];
601− u8 tls_xor_iv[0x40];
602− u8 encryption_key[0x100];
603− u8 alg[4];
604− u8 reserved2[0x1c];
605− u8 reserved3[0x4a0];
606−};
607−
608−struct mlx5_ifc_tls_resp_bits {
609− u8 syndrome[0x20];
610− u8 stream_id[0x20];
611− u8 reserved[0x40];
612−};
613−
614−#define MLX5_TLS_COMMAND_SIZE (0x100)
615−
616405 #endif /* MLX5_IFC_FPGA_H */
include/linux/mlx5/port.h+1−1
@@ -141,7 +141,7 @@ enum mlx5_ptys_width { · 140 unmodified lines
141141 MLX5_PTYS_WIDTH_12X = 1 << 4,
142142 };
143143
144−#define MLX5E_PROT_MASK(link_mode) (1 << link_mode)
144+#define MLX5E_PROT_MASK(link_mode) (1U << link_mode)
145145 #define MLX5_GET_ETH_PROTO(reg, out, ext, field) \
146146 (ext ? MLX5_GET(reg, out, ext_##field) : \
147147 MLX5_GET(reg, out, field))
include/rdma/ib_verbs.h+0−8
@@ -2515,15 +2515,7 @@ struct ib_device_ops { · 2514 unmodified lines
25152515 struct ib_flow_attr *flow_attr,
25162516 struct ib_udata *udata);
25172517 int (*destroy_flow)(struct ib_flow *flow_id);
2518− struct ib_flow_action *(*create_flow_action_esp)(
2519− struct ib_device *device,
2520− const struct ib_flow_action_attrs_esp *attr,
2521− struct uverbs_attr_bundle *attrs);
25222518 int (*destroy_flow_action)(struct ib_flow_action *action);
2523− int (*modify_flow_action_esp)(
2524− struct ib_flow_action *action,
2525− const struct ib_flow_action_attrs_esp *attr,
2526− struct uverbs_attr_bundle *attrs);
25272519 int (*set_vf_link_state)(struct ib_device *device, int vf, u32 port,
25282520 int state);
25292521 int (*get_vf_config)(struct ib_device *device, int vf, u32 port,