Pull drm updates from Dave Airlie: "Lots of stuff all over, some new AMD IP support and gang submit support. i915 has further DG2 and Meteorlake pieces, and a bunch of i915 display refactoring. msm has a shrinker rework. There are also a bunch of conversions to use kunit. This has two external pieces, some MEI changes needed for future Intel discrete GPUs. These should be acked by Greg. There is also a cross maintainer shared tree with some backlight rework from Hans in here. Core: - convert selftests to kunit - managed init for more objects - move to idr_init_base - rename fb and gem cma helpers to dma - hide unregistered connectors from getconnector ioctl - DSC passthrough aux support - backlight handling improvements - add dma_resv_assert_held to vmap/vunmap edid: - move luminance calculation to core fbdev: - fix aperture helper usage fourcc: - add more format helpers - add DRM_FORMAT_Cxx, DRM_FORMAT_Rxx, DRM_FORMAT_Dxx - add packed AYUV8888, XYUV8888 - add some kunit tests ttm: - allow bos without backing store - rewrite placement to use intersect/compatible functions dma-buf: - docs update - improve signalling when debugging udmabuf: - fix failure path GPF dp: - drop dp/mst legacy code - atomic mst state support - audio infoframe packing panel: - Samsung LTL101AL01 - B120XAN01.0 - R140NWF5 RH - DMT028VGHMCMI-1A T - AUO B133UAN02.1 - IVO M133NW4J-R3 - Innolux N120ACA-EA1 amdgpu: - Gang submit support - Mode2 reset for RDNA2 - New IP support: DCN 3.1.4, 3.2 SMU 13.x NBIO 7.7 GC 11.x PSP 13.x SDMA 6.x GMC 11.x - DSC passthrough support - PSP fixes for TA support - vangogh GFXOFF stats - clang fixes - gang submit CS cleanup prep work - fix VRAM eviction issues amdkfd: - GC 10.3 IP ISA fixes - fix CRIU regression - CPU fault on COW mapping fixes i915: - align fw versioning with kernel practices - add display substruct to i915 private - add initial runtime info to driver info - split out HDCP and backlight registers - MEI XeHP SDV GSC support - add per-gt sysfs defaults - TLB invalidation improvements - Disable PCI BAR resize on 32-bit - GuC firmware updates and compat changes - GuC log timestamp translation - DG2 preemption workaround changes - DG2 improved HDMI pixel clocks support - PCI BAR sanity checks - Enable DC5 on DG2 - DG2 DMC fw bumped - ADL-S PCI ID added - Meteorlake enablement - Rename ggtt_view to gtt_view - host RPS fixes - release mmaps on rpm suspend on discrete - clocking and dpll refactoring - VBT definitions and parsing updates - SKL watermark code extracted to separate file - allow seamless M/N changes on eDP panels - BUG_ON removal and cleanups msm: - DPU: simplified VBIF configuration cleanup CTL interfaces - DSI: removed unused msm_display_dsc_config struct switch regulator calls to new API switched to PANEL_BRIDGE for direct attached panels - DSI_PHY: convert drivers to parent_hws - DP: cleanup pixel_rate handling - HDMI: turned hdmi-phy-8996 into OF clk provider - misc dt-bindings fixes - choose eDP as primary display if it's available - support getting interconnects from either the mdss or the mdp5/dpu device nodes - gem: Shrinker + LRU re-work: - adds a shared GEM LRU+shrinker helper and moves msm over to that - reduce lock contention between retire and submit by avoiding the need to acquire obj lock in retire path (and instead using resv seeing obj's busyness in the shrinker - fix reclaim vs submit issues - GEM fault injection for triggering userspace error paths - Map/unmap optimization - Improved robustness for a6xx GPU recovery virtio: - improve error and edge conditions handling - convert to use managed helpers - stop exposing LINEAR modifier mgag200: - split modeset handling per model udl: - suspend/disconnect handling improvements vc4: - rework HDMI power up - depend on PM - better unplugging support ast: - resolution handling improvements ingenic: - add JZ4760(B) support - avoid a modeset when sharpness property is unchanged - use the new PM ops it6505: - power seq and clock updates ssd130x: - regmap bulk write - use atomic helpers instead of simple helpers via: - rename via_drv to via_dri1, consolidate all code. radeon: - drop DP MST experimental support - delayed work flush fix - use time_after ti-sn65dsi86: - DP support mediatek: - MT8195 DP support - drop of_gpio header - remove unneeded result - small DP code improvements vkms: - RGB565, XRGB64 and ARGB64 support sun4i: - tv: convert to atomic rcar-du: - Synopsys DW HDMI bridge DT bindings update exynos: - use drm_display_info.is_hdmi - correct return of mixer_mode_valid and hdmi_mode_valid omap: - refcounting fix rockchip: - RK3568 support - RK3399 gamma support" * tag 'drm-next-2022-10-05' of git://anongit.freedesktop.org/drm/drm: (1374 commits) drm/amdkfd: Fix UBSAN shift-out-of-bounds warning drm/amdkfd: Track unified memory when switching xnack mode drm/amdgpu: Enable sram on vcn_4_0_2 drm/amdgpu: Enable VCN DPG for GC11_0_1 drm/msm: Fix build break with recent mm tree drm/panel: simple: Use dev_err_probe() to simplify code drm/panel: panel-edp: Use dev_err_probe() to simplify code drm/panel: simple: Add Multi-Inno Technology MI0800FT-9 dt-bindings: display: simple: Add Multi-Inno Technology MI0800FT-9 panel drm/amdgpu: correct the memcpy size for ip discovery firmware drm/amdgpu: Skip put_reset_domain if it doesn't exist drm/amdgpu: remove switch from amdgpu_gmc_noretry_set drm/amdgpu: Fix mc_umc_status used uninitialized warning drm/amd/display: Prevent OTG shutdown during PSR SU drm/amdgpu: add page retirement handling for CPU RAS drm/amdgpu: use RAS error address convert api in mca notifier drm/amdgpu: support to convert dedicated umc mca address drm/amdgpu: export umc error address convert interface drm/amdgpu: fix sdma v4 init microcode error drm/amd/display: fix array-bounds error in dc_stream_remove_writeback() ...
Unified · Split
| @@ -24,6 +24,15 @@ properties: · 23 unmodified lines | ||
| 24 | 24 | maxItems: 1 |
| 25 | 25 | description: virtual channel number of a DSI peripheral |
| 26 | 26 | |
| 27 | + clock-names: | |
| 28 | + const: refclk | |
| 29 | + | |
| 30 | + clocks: | |
| 31 | + maxItems: 1 | |
| 32 | + description: | | |
| 33 | + Optional external clock connected to REF_CLK input. | |
| 34 | + The clock rate must be in 10..154 MHz range. | |
| 35 | + | |
| 27 | 36 | enable-gpios: |
| 28 | 37 | description: Bridge EN pin, chip is reset when EN is low. |
| 29 | 38 | |
| @@ -38,6 +38,9 @@ properties: · 37 unmodified lines | ||
| 38 | 38 | clock-names: |
| 39 | 39 | maxItems: 2 |
| 40 | 40 | |
| 41 | + resets: | |
| 42 | + maxItems: 1 | |
| 43 | + | |
| 41 | 44 | ports: |
| 42 | 45 | $ref: /schemas/graph.yaml#/properties/ports |
| 43 | 46 | |
| @@ -67,6 +70,7 @@ required: · 23 unmodified lines | ||
| 67 | 70 | - reg |
| 68 | 71 | - clocks |
| 69 | 72 | - clock-names |
| 73 | + - resets | |
| 70 | 74 | - interrupts |
| 71 | 75 | - ports |
| 72 | 76 | |
| @@ -85,6 +89,7 @@ examples: · 12 unmodified lines | ||
| 85 | 89 | clocks = <&cpg CPG_CORE R8A7795_CLK_S0D4>, <&cpg CPG_MOD 729>; |
| 86 | 90 | clock-names = "iahb", "isfr"; |
| 87 | 91 | power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; |
| 92 | + resets = <&cpg 729>; | |
| 88 | 93 | |
| 89 | 94 | ports { |
| 90 | 95 | #address-cells = <1>; |
| @@ -17,6 +17,8 @@ properties: · 16 unmodified lines | ||
| 17 | 17 | enum: |
| 18 | 18 | - ingenic,jz4740-lcd |
| 19 | 19 | - ingenic,jz4725b-lcd |
| 20 | + - ingenic,jz4760-lcd | |
| 21 | + - ingenic,jz4760b-lcd | |
| 20 | 22 | - ingenic,jz4770-lcd |
| 21 | 23 | - ingenic,jz4780-lcd |
| 22 | 24 | |
| @@ -0,0 +1,116 @@ | ||
| 1 | +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) | |
| 2 | +%YAML 1.2 | |
| 3 | +--- | |
| 4 | +$id: http://devicetree.org/schemas/display/mediatek/mediatek,dp.yaml# | |
| 5 | +$schema: http://devicetree.org/meta-schemas/core.yaml# | |
| 6 | + | |
| 7 | +title: MediaTek Display Port Controller | |
| 8 | + | |
| 9 | +maintainers: | |
| 10 | + - Chun-Kuang Hu <chunkuang.hu@kernel.org> | |
| 11 | + - Jitao shi <jitao.shi@mediatek.com> | |
| 12 | + | |
| 13 | +description: | | |
| 14 | + MediaTek DP and eDP are different hardwares and there are some features | |
| 15 | + which are not supported for eDP. For example, audio is not supported for | |
| 16 | + eDP. Therefore, we need to use two different compatibles to describe them. | |
| 17 | + In addition, We just need to enable the power domain of DP, so the clock | |
| 18 | + of DP is generated by itself and we are not using other PLL to generate | |
| 19 | + clocks. | |
| 20 | + | |
| 21 | +properties: | |
| 22 | + compatible: | |
| 23 | + enum: | |
| 24 | + - mediatek,mt8195-dp-tx | |
| 25 | + - mediatek,mt8195-edp-tx | |
| 26 | + | |
| 27 | + reg: | |
| 28 | + maxItems: 1 | |
| 29 | + | |
| 30 | + nvmem-cells: | |
| 31 | + maxItems: 1 | |
| 32 | + description: efuse data for display port calibration | |
| 33 | + | |
| 34 | + nvmem-cell-names: | |
| 35 | + const: dp_calibration_data | |
| 36 | + | |
| 37 | + power-domains: | |
| 38 | + maxItems: 1 | |
| 39 | + | |
| 40 | + interrupts: | |
| 41 | + maxItems: 1 | |
| 42 | + | |
| 43 | + ports: | |
| 44 | + $ref: /schemas/graph.yaml#/properties/ports | |
| 45 | + properties: | |
| 46 | + port@0: | |
| 47 | + $ref: /schemas/graph.yaml#/properties/port | |
| 48 | + description: Input endpoint of the controller, usually dp_intf | |
| 49 | + | |
| 50 | + port@1: | |
| 51 | + $ref: /schemas/graph.yaml#/$defs/port-base | |
| 52 | + unevaluatedProperties: false | |
| 53 | + description: Output endpoint of the controller | |
| 54 | + properties: | |
| 55 | + endpoint: | |
| 56 | + $ref: /schemas/media/video-interfaces.yaml# | |
| 57 | + unevaluatedProperties: false | |
| 58 | + properties: | |
| 59 | + data-lanes: | |
| 60 | + description: | | |
| 61 | + number of lanes supported by the hardware. | |
| 62 | + The possible values: | |
| 63 | + 0 - For 1 lane enabled in IP. | |
| 64 | + 0 1 - For 2 lanes enabled in IP. | |
| 65 | + 0 1 2 3 - For 4 lanes enabled in IP. | |
| 66 | + minItems: 1 | |
| 67 | + maxItems: 4 | |
| 68 | + required: | |
| 69 | + - data-lanes | |
| 70 | + | |
| 71 | + required: | |
| 72 | + - port@0 | |
| 73 | + - port@1 | |
| 74 | + | |
| 75 | + max-linkrate-mhz: | |
| 76 | + enum: [ 1620, 2700, 5400, 8100 ] | |
| 77 | + description: maximum link rate supported by the hardware. | |
| 78 | + | |
| 79 | +required: | |
| 80 | + - compatible | |
| 81 | + - reg | |
| 82 | + - interrupts | |
| 83 | + - ports | |
| 84 | + - max-linkrate-mhz | |
| 85 | + | |
| 86 | +additionalProperties: false | |
| 87 | + | |
| 88 | +examples: | |
| 89 | + - | | |
| 90 | + #include <dt-bindings/interrupt-controller/arm-gic.h> | |
| 91 | + #include <dt-bindings/power/mt8195-power.h> | |
| 92 | + dptx@1c600000 { | |
| 93 | + compatible = "mediatek,mt8195-dp-tx"; | |
| 94 | + reg = <0x1c600000 0x8000>; | |
| 95 | + power-domains = <&spm MT8195_POWER_DOMAIN_DP_TX>; | |
| 96 | + interrupts = <GIC_SPI 458 IRQ_TYPE_LEVEL_HIGH 0>; | |
| 97 | + max-linkrate-mhz = <8100>; | |
| 98 | + | |
| 99 | + ports { | |
| 100 | + #address-cells = <1>; | |
| 101 | + #size-cells = <0>; | |
| 102 | + | |
| 103 | + port@0 { | |
| 104 | + reg = <0>; | |
| 105 | + dptx_in: endpoint { | |
| 106 | + remote-endpoint = <&dp_intf0_out>; | |
| 107 | + }; | |
| 108 | + }; | |
| 109 | + port@1 { | |
| 110 | + reg = <1>; | |
| 111 | + dptx_out: endpoint { | |
| 112 | + data-lanes = <0 1 2 3>; | |
| 113 | + }; | |
| 114 | + }; | |
| 115 | + }; | |
| 116 | + }; | |
| @@ -24,6 +24,7 @@ properties: · 23 unmodified lines | ||
| 24 | 24 | - qcom,sm8350-dp |
| 25 | 25 | |
| 26 | 26 | reg: |
| 27 | + minItems: 4 | |
| 27 | 28 | items: |
| 28 | 29 | - description: ahb register block |
| 29 | 30 | - description: aux register block |
| @@ -70,14 +71,28 @@ properties: · 40 unmodified lines | ||
| 70 | 71 | operating-points-v2: |
| 71 | 72 | maxItems: 1 |
| 72 | 73 | |
| 74 | + opp-table: true | |
| 75 | + | |
| 73 | 76 | power-domains: |
| 74 | 77 | maxItems: 1 |
| 75 | 78 | |
| 79 | + aux-bus: | |
| 80 | + $ref: /schemas/display/dp-aux-bus.yaml# | |
| 81 | + | |
| 82 | + data-lanes: | |
| 83 | + $ref: /schemas/types.yaml#/definitions/uint32-array | |
| 84 | + minItems: 1 | |
| 85 | + maxItems: 4 | |
| 86 | + items: | |
| 87 | + maximum: 3 | |
| 88 | + | |
| 76 | 89 | "#sound-dai-cells": |
| 77 | 90 | const: 0 |
| 78 | 91 | |
| 79 | − vdda-0p9-supply: true | |
| 80 | − vdda-1p2-supply: true | |
| 92 | + vdda-0p9-supply: | |
| 93 | + deprecated: true | |
| 94 | + vdda-1p2-supply: | |
| 95 | + deprecated: true | |
| 81 | 96 | |
| 82 | 97 | ports: |
| 83 | 98 | $ref: /schemas/graph.yaml#/properties/ports |
| @@ -98,10 +113,33 @@ required: · 14 unmodified lines | ||
| 98 | 113 | - clock-names |
| 99 | 114 | - phys |
| 100 | 115 | - phy-names |
| 101 | − - "#sound-dai-cells" | |
| 102 | 116 | - power-domains |
| 103 | 117 | - ports |
| 104 | 118 | |
| 119 | +allOf: | |
| 120 | + # AUX BUS does not exist on DP controllers | |
| 121 | + # Audio output also is present only on DP output | |
| 122 | + # p1 regions is present on DP, but not on eDP | |
| 123 | + - if: | |
| 124 | + properties: | |
| 125 | + compatible: | |
| 126 | + contains: | |
| 127 | + enum: | |
| 128 | + - qcom,sc7280-edp | |
| 129 | + - qcom,sc8180x-edp | |
| 130 | + then: | |
| 131 | + properties: | |
| 132 | + "#sound-dai-cells": false | |
| 133 | + reg: | |
| 134 | + maxItems: 4 | |
| 135 | + else: | |
| 136 | + properties: | |
| 137 | + aux-bus: false | |
| 138 | + reg: | |
| 139 | + minItems: 5 | |
| 140 | + required: | |
| 141 | + - "#sound-dai-cells" | |
| 142 | + | |
| 105 | 143 | additionalProperties: false |
| 106 | 144 | |
| 107 | 145 | examples: |
| @@ -140,9 +178,6 @@ examples: · 32 unmodified lines | ||
| 140 | 178 | |
| 141 | 179 | power-domains = <&rpmhpd SC7180_CX>; |
| 142 | 180 | |
| 143 | − vdda-0p9-supply = <&vdda_usb_ss_dp_core>; | |
| 144 | − vdda-1p2-supply = <&vdda_usb_ss_dp_1p2>; | |
| 145 | − | |
| 146 | 181 | ports { |
| 147 | 182 | #address-cells = <1>; |
| 148 | 183 | #size-cells = <0>; |
| @@ -62,6 +62,7 @@ patternProperties: · 61 unmodified lines | ||
| 62 | 62 | "^display-controller@[0-9a-f]+$": |
| 63 | 63 | type: object |
| 64 | 64 | description: Node containing the properties of DPU. |
| 65 | + additionalProperties: false | |
| 65 | 66 | |
| 66 | 67 | properties: |
| 67 | 68 | compatible: |
| @@ -105,6 +106,9 @@ patternProperties: · 37 unmodified lines | ||
| 105 | 106 | maxItems: 1 |
| 106 | 107 | |
| 107 | 108 | operating-points-v2: true |
| 109 | + opp-table: | |
| 110 | + type: object | |
| 111 | + | |
| 108 | 112 | ports: |
| 109 | 113 | $ref: /schemas/graph.yaml#/properties/ports |
| 110 | 114 | description: | |
| @@ -74,6 +74,7 @@ patternProperties: · 73 unmodified lines | ||
| 74 | 74 | "^display-controller@[0-9a-f]+$": |
| 75 | 75 | type: object |
| 76 | 76 | description: Node containing the properties of DPU. |
| 77 | + additionalProperties: false | |
| 77 | 78 | |
| 78 | 79 | properties: |
| 79 | 80 | compatible: |
| @@ -113,6 +114,8 @@ patternProperties: · 33 unmodified lines | ||
| 113 | 114 | maxItems: 1 |
| 114 | 115 | |
| 115 | 116 | operating-points-v2: true |
| 117 | + opp-table: | |
| 118 | + type: object | |
| 116 | 119 | |
| 117 | 120 | ports: |
| 118 | 121 | $ref: /schemas/graph.yaml#/properties/ports |
| @@ -73,6 +73,7 @@ patternProperties: · 72 unmodified lines | ||
| 73 | 73 | "^display-controller@[0-9a-f]+$": |
| 74 | 74 | type: object |
| 75 | 75 | description: Node containing the properties of DPU. |
| 76 | + additionalProperties: false | |
| 76 | 77 | |
| 77 | 78 | properties: |
| 78 | 79 | compatible: |
| @@ -114,6 +115,8 @@ patternProperties: · 35 unmodified lines | ||
| 114 | 115 | maxItems: 1 |
| 115 | 116 | |
| 116 | 117 | operating-points-v2: true |
| 118 | + opp-table: | |
| 119 | + type: object | |
| 117 | 120 | |
| 118 | 121 | ports: |
| 119 | 122 | $ref: /schemas/graph.yaml#/properties/ports |
| @@ -72,6 +72,7 @@ patternProperties: · 71 unmodified lines | ||
| 72 | 72 | "^display-controller@[0-9a-f]+$": |
| 73 | 73 | type: object |
| 74 | 74 | description: Node containing the properties of DPU. |
| 75 | + additionalProperties: false | |
| 75 | 76 | |
| 76 | 77 | properties: |
| 77 | 78 | compatible: |
| @@ -112,6 +113,8 @@ patternProperties: · 34 unmodified lines | ||
| 112 | 113 | maxItems: 1 |
| 113 | 114 | |
| 114 | 115 | operating-points-v2: true |
| 116 | + opp-table: | |
| 117 | + type: object | |
| 115 | 118 | |
| 116 | 119 | ports: |
| 117 | 120 | $ref: /schemas/graph.yaml#/properties/ports |
| @@ -65,6 +65,7 @@ patternProperties: · 64 unmodified lines | ||
| 65 | 65 | "^display-controller@[0-9a-f]+$": |
| 66 | 66 | type: object |
| 67 | 67 | description: Node containing the properties of DPU. |
| 68 | + additionalProperties: false | |
| 68 | 69 | |
| 69 | 70 | properties: |
| 70 | 71 | compatible: |
| @@ -102,6 +103,9 @@ patternProperties: · 31 unmodified lines | ||
| 102 | 103 | maxItems: 1 |
| 103 | 104 | |
| 104 | 105 | operating-points-v2: true |
| 106 | + opp-table: | |
| 107 | + type: object | |
| 108 | + | |
| 105 | 109 | ports: |
| 106 | 110 | $ref: /schemas/graph.yaml#/properties/ports |
| 107 | 111 | description: | |
| @@ -20,35 +20,24 @@ description: | · 19 unmodified lines | ||
| 20 | 20 | properties: |
| 21 | 21 | compatible: |
| 22 | 22 | items: |
| 23 | − - enum: | |
| 24 | − - qcom,adreno-gmu-630.2 | |
| 23 | + - pattern: '^qcom,adreno-gmu-6[0-9][0-9]\.[0-9]$' | |
| 25 | 24 | - const: qcom,adreno-gmu |
| 26 | 25 | |
| 27 | 26 | reg: |
| 28 | − items: | |
| 29 | − - description: Core GMU registers | |
| 30 | − - description: GMU PDC registers | |
| 31 | − - description: GMU PDC sequence registers | |
| 27 | + minItems: 3 | |
| 28 | + maxItems: 4 | |
| 32 | 29 | |
| 33 | 30 | reg-names: |
| 34 | − items: | |
| 35 | − - const: gmu | |
| 36 | − - const: gmu_pdc | |
| 37 | − - const: gmu_pdc_seq | |
| 31 | + minItems: 3 | |
| 32 | + maxItems: 4 | |
| 38 | 33 | |
| 39 | 34 | clocks: |
| 40 | − items: | |
| 41 | − - description: GMU clock | |
| 42 | − - description: GPU CX clock | |
| 43 | − - description: GPU AXI clock | |
| 44 | − - description: GPU MEMNOC clock | |
| 35 | + minItems: 4 | |
| 36 | + maxItems: 7 | |
| 45 | 37 | |
| 46 | 38 | clock-names: |
| 47 | − items: | |
| 48 | − - const: gmu | |
| 49 | − - const: cxo | |
| 50 | − - const: axi | |
| 51 | − - const: memnoc | |
| 39 | + minItems: 4 | |
| 40 | + maxItems: 7 | |
| 52 | 41 | |
| 53 | 42 | interrupts: |
| 54 | 43 | items: |
| @@ -76,6 +65,9 @@ properties: · 21 unmodified lines | ||
| 76 | 65 | |
| 77 | 66 | operating-points-v2: true |
| 78 | 67 | |
| 68 | + opp-table: | |
| 69 | + type: object | |
| 70 | + | |
| 79 | 71 | required: |
| 80 | 72 | - compatible |
| 81 | 73 | - reg |
| @@ -91,6 +83,140 @@ required: · 9 unmodified lines | ||
| 91 | 83 | |
| 92 | 84 | additionalProperties: false |
| 93 | 85 | |
| 86 | +allOf: | |
| 87 | + - if: | |
| 88 | + properties: | |
| 89 | + compatible: | |
| 90 | + contains: | |
| 91 | + enum: | |
| 92 | + - qcom,adreno-gmu-618.0 | |
| 93 | + - qcom,adreno-gmu-630.2 | |
| 94 | + then: | |
| 95 | + properties: | |
| 96 | + reg: | |
| 97 | + items: | |
| 98 | + - description: Core GMU registers | |
| 99 | + - description: GMU PDC registers | |
| 100 | + - description: GMU PDC sequence registers | |
| 101 | + reg-names: | |
| 102 | + items: | |
| 103 | + - const: gmu | |
| 104 | + - const: gmu_pdc | |
| 105 | + - const: gmu_pdc_seq | |
| 106 | + clocks: | |
| 107 | + items: | |
| 108 | + - description: GMU clock | |
| 109 | + - description: GPU CX clock | |
| 110 | + - description: GPU AXI clock | |
| 111 | + - description: GPU MEMNOC clock | |
| 112 | + clock-names: | |
| 113 | + items: | |
| 114 | + - const: gmu | |
| 115 | + - const: cxo | |
| 116 | + - const: axi | |
| 117 | + - const: memnoc | |
| 118 | + | |
| 119 | + - if: | |
| 120 | + properties: | |
| 121 | + compatible: | |
| 122 | + contains: | |
| 123 | + enum: | |
| 124 | + - qcom,adreno-gmu-635.0 | |
| 125 | + then: | |
| 126 | + properties: | |
| 127 | + reg: | |
| 128 | + items: | |
| 129 | + - description: Core GMU registers | |
| 130 | + - description: Resource controller registers | |
| 131 | + - description: GMU PDC registers | |
| 132 | + reg-names: | |
| 133 | + items: | |
| 134 | + - const: gmu | |
| 135 | + - const: rscc | |
| 136 | + - const: gmu_pdc | |
| 137 | + clocks: | |
| 138 | + items: | |
| 139 | + - description: GMU clock | |
| 140 | + - description: GPU CX clock | |
| 141 | + - description: GPU AXI clock | |
| 142 | + - description: GPU MEMNOC clock | |
| 143 | + - description: GPU AHB clock | |
| 144 | + - description: GPU HUB CX clock | |
| 145 | + - description: GPU SMMU vote clock | |
| 146 | + clock-names: | |
| 147 | + items: | |
| 148 | + - const: gmu | |
| 149 | + - const: cxo | |
| 150 | + - const: axi | |
| 151 | + - const: memnoc | |
| 152 | + - const: ahb | |
| 153 | + - const: hub | |
| 154 | + - const: smmu_vote | |
| 155 | + | |
| 156 | + - if: | |
| 157 | + properties: | |
| 158 | + compatible: | |
| 159 | + contains: | |
| 160 | + enum: | |
| 161 | + - qcom,adreno-gmu-640.1 | |
| 162 | + then: | |
| 163 | + properties: | |
| 164 | + reg: | |
| 165 | + items: | |
| 166 | + - description: Core GMU registers | |
| 167 | + - description: GMU PDC registers | |
| 168 | + - description: GMU PDC sequence registers | |
| 169 | + reg-names: | |
| 170 | + items: | |
| 171 | + - const: gmu | |
| 172 | + - const: gmu_pdc | |
| 173 | + - const: gmu_pdc_seq | |
| 174 | + | |
| 175 | + - if: | |
| 176 | + properties: | |
| 177 | + compatible: | |
| 178 | + contains: | |
| 179 | + enum: | |
| 180 | + - qcom,adreno-gmu-650.2 | |
| 181 | + then: | |
| 182 | + properties: | |
| 183 | + reg: | |
| 184 | + items: | |
| 185 | + - description: Core GMU registers | |
| 186 | + - description: Resource controller registers | |
| 187 | + - description: GMU PDC registers | |
| 188 | + - description: GMU PDC sequence registers | |
| 189 | + reg-names: | |
| 190 | + items: | |
| 191 | + - const: gmu | |
| 192 | + - const: rscc | |
| 193 | + - const: gmu_pdc | |
| 194 | + - const: gmu_pdc_seq | |
| 195 | + | |
| 196 | + - if: | |
| 197 | + properties: | |
| 198 | + compatible: | |
| 199 | + contains: | |
| 200 | + enum: | |
| 201 | + - qcom,adreno-gmu-640.1 | |
| 202 | + - qcom,adreno-gmu-650.2 | |
| 203 | + then: | |
| 204 | + properties: | |
| 205 | + clocks: | |
| 206 | + items: | |
| 207 | + - description: GPU AHB clock | |
| 208 | + - description: GMU clock | |
| 209 | + - description: GPU CX clock | |
| 210 | + - description: GPU AXI clock | |
| 211 | + - description: GPU MEMNOC clock | |
| 212 | + clock-names: | |
| 213 | + items: | |
| 214 | + - const: ahb | |
| 215 | + - const: gmu | |
| 216 | + - const: cxo | |
| 217 | + - const: axi | |
| 218 | + - const: memnoc | |
| 219 | + | |
| 94 | 220 | examples: |
| 95 | 221 | - | |
| 96 | 222 | #include <dt-bindings/clock/qcom,gpucc-sdm845.h> |
| @@ -58,7 +58,8 @@ properties: · 57 unmodified lines | ||
| 58 | 58 | - const: ocmem |
| 59 | 59 | |
| 60 | 60 | iommus: |
| 61 | − maxItems: 1 | |
| 61 | + minItems: 1 | |
| 62 | + maxItems: 64 | |
| 62 | 63 | |
| 63 | 64 | sram: |
| 64 | 65 | $ref: /schemas/types.yaml#/definitions/phandle-array |
| @@ -36,7 +36,7 @@ properties: · 35 unmodified lines | ||
| 36 | 36 | maxItems: 1 |
| 37 | 37 | |
| 38 | 38 | iommus: |
| 39 | − maxItems: 1 | |
| 39 | + maxItems: 4 | |
| 40 | 40 | |
| 41 | 41 | ports: |
| 42 | 42 | $ref: /schemas/graph.yaml#/properties/ports |
| @@ -234,6 +234,8 @@ properties: · 233 unmodified lines | ||
| 234 | 234 | - mitsubishi,aa070mc01-ca1 |
| 235 | 235 | # Multi-Inno Technology Co.,Ltd MI0700S4T-6 7" 800x480 TFT Resistive Touch Module |
| 236 | 236 | - multi-inno,mi0700s4t-6 |
| 237 | + # Multi-Inno Technology Co.,Ltd MI0800FT-9 8" 800x600 TFT Resistive Touch Module | |
| 238 | + - multi-inno,mi0800ft-9 | |
| 237 | 239 | # Multi-Inno Technology Co.,Ltd MI1010AIT-1CP 10.1" 1280x800 LVDS IPS Cap Touch Mod. |
| 238 | 240 | - multi-inno,mi1010ait-1cp |
| 239 | 241 | # NEC LCD Technologies, Ltd. 12.1" WXGA (1280x800) LVDS TFT LCD panel |
| @@ -280,6 +282,8 @@ properties: · 40 unmodified lines | ||
| 280 | 282 | - samsung,atna33xc20 |
| 281 | 283 | # Samsung 12.2" (2560x1600 pixels) TFT LCD panel |
| 282 | 284 | - samsung,lsn122dl01-c01 |
| 285 | + # Samsung Electronics 10.1" WXGA (1280x800) TFT LCD panel | |
| 286 | + - samsung,ltl101al01 | |
| 283 | 287 | # Samsung Electronics 10.1" WSVGA TFT LCD panel |
| 284 | 288 | - samsung,ltn101nt05 |
| 285 | 289 | # Samsung Electronics 14" WXGA (1366x768) TFT LCD panel |
| @@ -17,6 +17,9 @@ description: | · 16 unmodified lines | ||
| 17 | 17 | Techstar TS8550B is 480x854, 2-lane MIPI DSI LCD panel which has |
| 18 | 18 | inbuilt ST7701 chip. |
| 19 | 19 | |
| 20 | + Densitron DMT028VGHMCMI-1A is 480x640, 2-lane MIPI DSI LCD panel | |
| 21 | + which has built-in ST7701 chip. | |
| 22 | + | |
| 20 | 23 | allOf: |
| 21 | 24 | - $ref: panel-common.yaml# |
| 22 | 25 | |
| @@ -24,6 +27,7 @@ properties: · 1 unmodified line | ||
| 24 | 27 | compatible: |
| 25 | 28 | items: |
| 26 | 29 | - enum: |
| 30 | + - densitron,dmt028vghmcmi-1a | |
| 27 | 31 | - techstar,ts8550b |
| 28 | 32 | - const: sitronix,st7701 |
| 29 | 33 | |
| @@ -8,6 +8,7 @@ Required properties: · 7 unmodified lines | ||
| 8 | 8 | "rockchip,px30-mipi-dsi", "snps,dw-mipi-dsi" |
| 9 | 9 | "rockchip,rk3288-mipi-dsi", "snps,dw-mipi-dsi" |
| 10 | 10 | "rockchip,rk3399-mipi-dsi", "snps,dw-mipi-dsi" |
| 11 | + "rockchip,rk3568-mipi-dsi", "snps,dw-mipi-dsi" | |
| 11 | 12 | - reg: Represent the physical address range of the controller. |
| 12 | 13 | - interrupts: Represent the controller's interrupt to the CPU(s). |
| 13 | 14 | - clocks, clock-names: Phandles to the controller's pll reference |
| @@ -28,12 +28,15 @@ properties: · 27 unmodified lines | ||
| 28 | 28 | - const: hdmi_phy |
| 29 | 29 | |
| 30 | 30 | clocks: |
| 31 | − maxItems: 2 | |
| 31 | + minItems: 2 | |
| 32 | + maxItems: 3 | |
| 32 | 33 | |
| 33 | 34 | clock-names: |
| 35 | + minItems: 2 | |
| 34 | 36 | items: |
| 35 | 37 | - const: iface |
| 36 | 38 | - const: ref |
| 39 | + - const: xo | |
| 37 | 40 | |
| 38 | 41 | power-domains: |
| 39 | 42 | maxItems: 1 |
| @@ -44,6 +47,9 @@ properties: · 4 unmodified lines | ||
| 44 | 47 | vddio-supply: |
| 45 | 48 | description: phandle to VDD I/O supply regulator |
| 46 | 49 | |
| 50 | + '#clock-cells': | |
| 51 | + const: 0 | |
| 52 | + | |
| 47 | 53 | '#phy-cells': |
| 48 | 54 | const: 0 |
| 49 | 55 | |
| @@ -75,9 +81,12 @@ examples: · 25 unmodified lines | ||
| 75 | 81 | "hdmi_phy"; |
| 76 | 82 | |
| 77 | 83 | clocks = <&mmcc 116>, |
| 78 | − <&gcc 214>; | |
| 84 | + <&gcc 214>, | |
| 85 | + <&xo_board>; | |
| 79 | 86 | clock-names = "iface", |
| 80 | − "ref"; | |
| 87 | + "ref", | |
| 88 | + "xo"; | |
| 89 | + #clock-cells = <0>; | |
| 81 | 90 | #phy-cells = <0>; |
| 82 | 91 | |
| 83 | 92 | vddio-supply = <&vreg_l12a_1p8>; |
| @@ -0,0 +1,8 @@ | ||
| 1 | +Product Name, Code Reference, DCN/DCE version, GC version, VCE/UVD/VCN version, SDMA version | |
| 2 | +Radeon R* Graphics, CARRIZO/STONEY, DCE 11, 8, VCE 3 / UVD 6, 3 | |
| 3 | +Ryzen 3000 series / AMD Ryzen Embedded V1*/R1* with Radeon Vega Gfx, RAVEN/PICASSO, DCN 1.0, 9.1.0, VCN 1.0, 4.1.0 | |
| 4 | +Ryzen 4000 series, RENOIR, DCN 2.1, 9.3, VCN 2.2, 4.1.2 | |
| 5 | +Ryzen 3000 series / AMD Ryzen Embedded V1*/R1* with Radeon Vega Gfx, RAVEN2, DCN 1.0, 9.2.2, VCN 1.0.1, 4.1.1 | |
| 6 | +SteamDeck, VANGOGH, DCN 3.0.1, 10.3.1, VCN 3.1.0, 5.2.1 | |
| 7 | +Ryzen 5000 series, GREEN SARDINE, DCN 2.1, 9.3, VCN 2.2, 4.1.1 | |
| 8 | +Ryzen 6000 Zen, YELLOW CARP, 3.1.2, 10.3.3, VCN 3.1.1, 5.2.3 | |
| @@ -0,0 +1,24 @@ | ||
| 1 | +Product Name, Code Reference, DCN/DCE version, GC version, VCN version, SDMA version | |
| 2 | +AMD Radeon (TM) HD 8500M/ 8600M /M200 /M320 /M330 /M335 Series, HAINAN, --, 6, --, -- | |
| 3 | +AMD Radeon HD 7800 /7900 /FireGL Series, TAHITI, DCE 6, 6, VCE 1 / UVD 3, -- | |
| 4 | +AMD Radeon R7 (TM|HD) M265 /M370 /8500M /8600 /8700 /8700M, OLAND, DCE 6, 6, VCE 1 / UVD 3, -- | |
| 5 | +AMD Radeon (TM) (HD|R7) 7800 /7970 /8800 /8970 /370/ Series, PITCAIRN, DCE 6, 6, VCE 1 / UVD 3, -- | |
| 6 | +AMD Radeon (TM|R7|R9|HD) E8860 /M360 /7700 /7800 /8800 /9000(M) /W4100 Series, VERDE, DCE 6, 6, VCE 1 / UVD 3, -- | |
| 7 | +AMD Radeon HD M280X /M380 /7700 /8950 /W5100, BONAIRE, DCE 8, 7, VCE 2 / UVD 4.2, 1 | |
| 8 | +AMD Radeon (R9|TM) 200 /390 /W8100 /W9100 Series, HAWAII, DCE 8, 7, VCE 2 / UVD 4.2, 1 | |
| 9 | +AMD Radeon (TM) R(5|7) M315 /M340 /M360, TOPAZ, *, 8, --, 2 | |
| 10 | +AMD Radeon (TM) R9 200 /380 /W7100 /S7150 /M390 /M395 Series, TONGA, DCE 10, 8, VCE 3 / UVD 5, 3 | |
| 11 | +AMD Radeon (FirePro) (TM) R9 Fury Series, FIJI, DCE 10, 8, VCE 3 / UVD 6, 3 | |
| 12 | +Radeon RX 470 /480 /570 /580 /590 Series - AMD Radeon (TM) (Pro WX) 5100 /E9390 /E9560 /E9565 /V7350 /7100 /P30PH, POLARIS10, DCE 11.2, 8, VCE 3.4 / UVD 6.3, 3 | |
| 13 | +Radeon (TM) (RX|Pro WX) E9260 /460 /V5300X /550 /560(X) Series, POLARIS11, DCE 11.2, 8, VCE 3.4 / UVD 6.3, 3 | |
| 14 | +Radeon (RX/Pro) 500 /540(X) /550 /640 /WX2100 /WX3100 /WX200 Series, POLARIS12, DCE 11.2, 8, VCE 3.4 / UVD 6.3, 3 | |
| 15 | +Radeon (RX|TM) (PRO|WX) Vega /MI25 /V320 /V340L /8200 /9100 /SSG MxGPU, VEGA10, DCE 12, 9.0.1, VCE 4.0.0 / UVD 7.0.0, 4.0.0 | |
| 16 | +AMD Radeon (Pro) VII /MI50 /MI60, VEGA20, DCE 12, 9.4.0, VCE 4.1.0 / UVD 7.2.0, 4.2.0 | |
| 17 | +MI100, ARCTURUS, *, 9.4.1, VCN 2.5.0, 4.2.2 | |
| 18 | +MI200, ALDEBARAN, *, 9.4.2, VCN 2.6.0, 4.4.0 | |
| 19 | +AMD Radeon (RX|Pro) 5600(M|XT) /5700 (M|XT|XTB) /W5700, NAVI10, DCN 2.0.0, 10.1.10, VCN 2.0.0, 5.0.0 | |
| 20 | +AMD Radeon (Pro) 5300 /5500XTB/5500(XT|M) /W5500M /W5500, NAVI14, DCN 2.0.0, 10.1.1, VCN 2.0.2, 5.0.2 | |
| 21 | +AMD Radeon RX 6800(XT) /6900(XT) /W6800, SIENNA_CICHLID, DCN 3.0.0, 10.3.0, VCN 3.0.0, 5.2.0 | |
| 22 | +AMD Radeon RX 6700 XT / 6800M / 6700M, NAVY_FLOUNDER, DCN 3.0.0, 10.3.2, VCN 3.0.0, 5.2.2 | |
| 23 | +AMD Radeon RX 6600(XT) /6600M /W6600 /W6600M, DIMGREY_CAVEFISH, DCN 3.0.2, 10.3.4, VCN 3.0.16, 5.2.4 | |
| 24 | +AMD Radeon RX 6500M /6300M /W6500M /W6300M, BEIGE_GOBY, DCN 3.0.3, 10.3.5, VCN 3.0.33, 5.2.5 | |
| @@ -170,7 +170,7 @@ consider asking in the amdgfx and update this page. · 169 unmodified lines | ||
| 170 | 170 | MC |
| 171 | 171 | Memory Controller |
| 172 | 172 | |
| 173 | − MPC | |
| 173 | + MPC/MPCC | |
| 174 | 174 | Multiple pipes and plane combine |
| 175 | 175 | |
| 176 | 176 | MPO |
| @@ -124,6 +124,65 @@ depth format), bit-depth reduction/dithering would kick in. In OPP, we would · 123 unmodified lines | ||
| 124 | 124 | also apply a regamma function to introduce the gamma removed earlier back. |
| 125 | 125 | Eventually, we output data in integer format at DIO. |
| 126 | 126 | |
| 127 | +AMD Hardware Pipeline | |
| 128 | +--------------------- | |
| 129 | + | |
| 130 | +When discussing graphics on Linux, the **pipeline** term can sometimes be | |
| 131 | +overloaded with multiple meanings, so it is important to define what we mean | |
| 132 | +when we say **pipeline**. In the DCN driver, we use the term **hardware | |
| 133 | +pipeline** or **pipeline** or just **pipe** as an abstraction to indicate a | |
| 134 | +sequence of DCN blocks instantiated to address some specific configuration. DC | |
| 135 | +core treats DCN blocks as individual resources, meaning we can build a pipeline | |
| 136 | +by taking resources for all individual hardware blocks to compose one pipeline. | |
| 137 | +In actuality, we can't connect an arbitrary block from one pipe to a block from | |
| 138 | +another pipe; they are routed linearly, except for DSC, which can be | |
| 139 | +arbitrarily assigned as needed. We have this pipeline concept for trying to | |
| 140 | +optimize bandwidth utilization. | |
| 141 | + | |
| 142 | +.. kernel-figure:: pipeline_4k_no_split.svg | |
| 143 | + | |
| 144 | +Additionally, let's take a look at parts of the DTN log (see | |
| 145 | +'Documentation/gpu/amdgpu/display/dc-debug.rst' for more information) since | |
| 146 | +this log can help us to see part of this pipeline behavior in real-time:: | |
| 147 | + | |
| 148 | + HUBP: format addr_hi width height ... | |
| 149 | + [ 0]: 8h 81h 3840 2160 | |
| 150 | + [ 1]: 0h 0h 0 0 | |
| 151 | + [ 2]: 0h 0h 0 0 | |
| 152 | + [ 3]: 0h 0h 0 0 | |
| 153 | + [ 4]: 0h 0h 0 0 | |
| 154 | + ... | |
| 155 | + MPCC: OPP DPP ... | |
| 156 | + [ 0]: 0h 0h ... | |
| 157 | + | |
| 158 | +The first thing to notice from the diagram and DTN log it is the fact that we | |
| 159 | +have different clock domains for each part of the DCN blocks. In this example, | |
| 160 | +we have just a single **pipeline** where the data flows from DCHUB to DIO, as | |
| 161 | +we intuitively expect. Nonetheless, DCN is flexible, as mentioned before, and | |
| 162 | +we can split this single pipe differently, as described in the below diagram: | |
| 163 | + | |
| 164 | +.. kernel-figure:: pipeline_4k_split.svg | |
| 165 | + | |
| 166 | +Now, if we inspect the DTN log again we can see some interesting changes:: | |
| 167 | + | |
| 168 | + HUBP: format addr_hi width height ... | |
| 169 | + [ 0]: 8h 81h 1920 2160 ... | |
| 170 | + ... | |
| 171 | + [ 4]: 0h 0h 0 0 ... | |
| 172 | + [ 5]: 8h 81h 1920 2160 ... | |
| 173 | + ... | |
| 174 | + MPCC: OPP DPP ... | |
| 175 | + [ 0]: 0h 0h ... | |
| 176 | + [ 5]: 0h 5h ... | |
| 177 | + | |
| 178 | +From the above example, we now split the display pipeline into two vertical | |
| 179 | +parts of 1920x2160 (i.e., 3440x2160), and as a result, we could reduce the | |
| 180 | +clock frequency in the DPP part. This is not only useful for saving power but | |
| 181 | +also to better handle the required throughput. The idea to keep in mind here is | |
| 182 | +that the pipe configuration can vary a lot according to the display | |
| 183 | +configuration, and it is the DML's responsibility to set up all required | |
| 184 | +configuration parameters for multiple scenarios supported by our hardware. | |
| 185 | + | |
| 127 | 186 | Global Sync |
| 128 | 187 | ----------- |
| 129 | 188 | |
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| 1151 | + style="font-size:18.6667px;text-align:center;text-anchor:middle">Shaper LUT</tspan><tspan | |
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| 1156 | + id="tspan222533">RAM</tspan></text> | |
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| 1167 | + style="font-size:18.6667px;text-align:center;text-anchor:middle">3D LUT</tspan><tspan | |
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| 1172 | + id="tspan221121">RAM</tspan></text> | |
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| 1205 | + style="font-size:18.6667px;text-align:center;text-anchor:middle">Gamma</tspan><tspan | |
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| 1209 | + style="font-size:18.6667px;text-align:center;text-anchor:middle" | |
| 1210 | + id="tspan197733">RAM</tspan></text> | |
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| 1239 | + style="font-size:18.6667px;text-align:center;text-anchor:middle">Shaper LUT</tspan><tspan | |
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| 1243 | + style="font-size:18.6667px;text-align:center;text-anchor:middle" | |
| 1244 | + id="tspan222533">RAM</tspan></text> | |
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| @@ -40,3 +40,144 @@ Atomic Implementation · 39 unmodified lines | ||
| 40 | 40 | |
| 41 | 41 | .. kernel-doc:: drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c |
| 42 | 42 | :functions: amdgpu_dm_atomic_check amdgpu_dm_atomic_commit_tail |
| 43 | + | |
| 44 | +Color Management Properties | |
| 45 | +=========================== | |
| 46 | + | |
| 47 | +.. kernel-doc:: drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c | |
| 48 | + :doc: overview | |
| 49 | + | |
| 50 | +.. kernel-doc:: drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c | |
| 51 | + :internal: | |
| 52 | + | |
| 53 | + | |
| 54 | +DC Color Capabilities between DCN generations | |
| 55 | +--------------------------------------------- | |
| 56 | + | |
| 57 | +DRM/KMS framework defines three CRTC color correction properties: degamma, | |
| 58 | +color transformation matrix (CTM) and gamma, and two properties for degamma and | |
| 59 | +gamma LUT sizes. AMD DC programs some of the color correction features | |
| 60 | +pre-blending but DRM/KMS has not per-plane color correction properties. | |
| 61 | + | |
| 62 | +In general, the DRM CRTC color properties are programmed to DC, as follows: | |
| 63 | +CRTC gamma after blending, and CRTC degamma pre-blending. Although CTM is | |
| 64 | +programmed after blending, it is mapped to DPP hw blocks (pre-blending). Other | |
| 65 | +color caps available in the hw is not currently exposed by DRM interface and | |
| 66 | +are bypassed. | |
| 67 | + | |
| 68 | +.. kernel-doc:: drivers/gpu/drm/amd/display/dc/dc.h | |
| 69 | + :doc: color-management-caps | |
| 70 | + | |
| 71 | +.. kernel-doc:: drivers/gpu/drm/amd/display/dc/dc.h | |
| 72 | + :internal: | |
| 73 | + | |
| 74 | +The color pipeline has undergone major changes between DCN hardware | |
| 75 | +generations. What's possible to do before and after blending depends on | |
| 76 | +hardware capabilities, as illustrated below by the DCN 2.0 and DCN 3.0 families | |
| 77 | +schemas. | |
| 78 | + | |
| 79 | +**DCN 2.0 family color caps and mapping** | |
| 80 | + | |
| 81 | +.. kernel-figure:: dcn2_cm_drm_current.svg | |
| 82 | + | |
| 83 | +**DCN 3.0 family color caps and mapping** | |
| 84 | + | |
| 85 | +.. kernel-figure:: dcn3_cm_drm_current.svg | |
| 86 | + | |
| 87 | +Blend Mode Properties | |
| 88 | +===================== | |
| 89 | + | |
| 90 | +Pixel blend mode is a DRM plane composition property of :c:type:`drm_plane` used to | |
| 91 | +describes how pixels from a foreground plane (fg) are composited with the | |
| 92 | +background plane (bg). Here, we present main concepts of DRM blend mode to help | |
| 93 | +to understand how this property is mapped to AMD DC interface. See more about | |
| 94 | +this DRM property and the alpha blending equations in :ref:`DRM Plane | |
| 95 | +Composition Properties <plane_composition_properties>`. | |
| 96 | + | |
| 97 | +Basically, a blend mode sets the alpha blending equation for plane | |
| 98 | +composition that fits the mode in which the alpha channel affects the state of | |
| 99 | +pixel color values and, therefore, the resulted pixel color. For | |
| 100 | +example, consider the following elements of the alpha blending equation: | |
| 101 | + | |
| 102 | +- *fg.rgb*: Each of the RGB component values from the foreground's pixel. | |
| 103 | +- *fg.alpha*: Alpha component value from the foreground's pixel. | |
| 104 | +- *bg.rgb*: Each of the RGB component values from the background. | |
| 105 | +- *plane_alpha*: Plane alpha value set by the **plane "alpha" property**, see | |
| 106 | + more in :ref:`DRM Plane Composition Properties <plane_composition_properties>`. | |
| 107 | + | |
| 108 | +in the basic alpha blending equation:: | |
| 109 | + | |
| 110 | + out.rgb = alpha * fg.rgb + (1 - alpha) * bg.rgb | |
| 111 | + | |
| 112 | +the alpha channel value of each pixel in a plane is ignored and only the plane | |
| 113 | +alpha affects the resulted pixel color values. | |
| 114 | + | |
| 115 | +DRM has three blend mode to define the blend formula in the plane composition: | |
| 116 | + | |
| 117 | +* **None**: Blend formula that ignores the pixel alpha. | |
| 118 | + | |
| 119 | +* **Pre-multiplied**: Blend formula that assumes the pixel color values in a | |
| 120 | + plane was already pre-multiplied by its own alpha channel before storage. | |
| 121 | + | |
| 122 | +* **Coverage**: Blend formula that assumes the pixel color values were not | |
| 123 | + pre-multiplied with the alpha channel values. | |
| 124 | + | |
| 125 | +and pre-multiplied is the default pixel blend mode, that means, when no blend | |
| 126 | +mode property is created or defined, DRM considers the plane's pixels has | |
| 127 | +pre-multiplied color values. On IGT GPU tools, the kms_plane_alpha_blend test | |
| 128 | +provides a set of subtests to verify plane alpha and blend mode properties. | |
| 129 | + | |
| 130 | +The DRM blend mode and its elements are then mapped by AMDGPU display manager | |
| 131 | +(DM) to program the blending configuration of the Multiple Pipe/Plane Combined | |
| 132 | +(MPC), as follows: | |
| 133 | + | |
| 134 | +.. kernel-doc:: drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h | |
| 135 | + :doc: mpc-overview | |
| 136 | + | |
| 137 | +.. kernel-doc:: drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h | |
| 138 | + :functions: mpcc_blnd_cfg | |
| 139 | + | |
| 140 | +Therefore, the blending configuration for a single MPCC instance on the MPC | |
| 141 | +tree is defined by :c:type:`mpcc_blnd_cfg`, where | |
| 142 | +:c:type:`pre_multiplied_alpha` is the alpha pre-multiplied mode flag used to | |
| 143 | +set :c:type:`MPCC_ALPHA_MULTIPLIED_MODE`. It controls whether alpha is | |
| 144 | +multiplied (true/false), being only true for DRM pre-multiplied blend mode. | |
| 145 | +:c:type:`mpcc_alpha_blend_mode` defines the alpha blend mode regarding pixel | |
| 146 | +alpha and plane alpha values. It sets one of the three modes for | |
| 147 | +:c:type:`MPCC_ALPHA_BLND_MODE`, as described below. | |
| 148 | + | |
| 149 | +.. kernel-doc:: drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h | |
| 150 | + :functions: mpcc_alpha_blend_mode | |
| 151 | + | |
| 152 | +DM then maps the elements of `enum mpcc_alpha_blend_mode` to those in the DRM | |
| 153 | +blend formula, as follows: | |
| 154 | + | |
| 155 | +* *MPC pixel alpha* matches *DRM fg.alpha* as the alpha component value | |
| 156 | + from the plane's pixel | |
| 157 | +* *MPC global alpha* matches *DRM plane_alpha* when the pixel alpha should | |
| 158 | + be ignored and, therefore, pixel values are not pre-multiplied | |
| 159 | +* *MPC global gain* assumes *MPC global alpha* value when both *DRM | |
| 160 | + fg.alpha* and *DRM plane_alpha* participate in the blend equation | |
| 161 | + | |
| 162 | +In short, *fg.alpha* is ignored by selecting | |
| 163 | +:c:type:`MPCC_ALPHA_BLEND_MODE_GLOBAL_ALPHA`. On the other hand, (plane_alpha * | |
| 164 | +fg.alpha) component becomes available by selecting | |
| 165 | +:c:type:`MPCC_ALPHA_BLEND_MODE_PER_PIXEL_ALPHA_COMBINED_GLOBAL_GAIN`. And the | |
| 166 | +:c:type:`MPCC_ALPHA_MULTIPLIED_MODE` defines if the pixel color values are | |
| 167 | +pre-multiplied by alpha or not. | |
| 168 | + | |
| 169 | +Blend configuration flow | |
| 170 | +------------------------ | |
| 171 | + | |
| 172 | +The alpha blending equation is configured from DRM to DC interface by the | |
| 173 | +following path: | |
| 174 | + | |
| 175 | +1. When updating a :c:type:`drm_plane_state <drm_plane_state>`, DM calls | |
| 176 | + :c:type:`fill_blending_from_plane_state()` that maps | |
| 177 | + :c:type:`drm_plane_state <drm_plane_state>` attributes to | |
| 178 | + :c:type:`dc_plane_info <dc_plane_info>` struct to be handled in the | |
| 179 | + OS-agnostic component (DC). | |
| 180 | + | |
| 181 | +2. On DC interface, :c:type:`struct mpcc_blnd_cfg <mpcc_blnd_cfg>` programs the | |
| 182 | + MPCC blend configuration considering the :c:type:`dc_plane_info | |
| 183 | + <dc_plane_info>` input from DPP. | |
| @@ -28,4 +28,5 @@ table of content: · 27 unmodified lines | ||
| 28 | 28 | display-manager.rst |
| 29 | 29 | dc-debug.rst |
| 30 | 30 | dcn-overview.rst |
| 31 | + mpo-overview.rst | |
| 31 | 32 | dc-glossary.rst |
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| @@ -0,0 +1,242 @@ | ||
| 1 | +======================== | |
| 2 | +Multiplane Overlay (MPO) | |
| 3 | +======================== | |
| 4 | + | |
| 5 | +.. note:: You will get more from this page if you have already read the | |
| 6 | + 'Documentation/gpu/amdgpu/display/dcn-overview.rst'. | |
| 7 | + | |
| 8 | + | |
| 9 | +Multiplane Overlay (MPO) allows for multiple framebuffers to be composited via | |
| 10 | +fixed-function hardware in the display controller rather than using graphics or | |
| 11 | +compute shaders for composition. This can yield some power savings if it means | |
| 12 | +the graphics/compute pipelines can be put into low-power states. In summary, | |
| 13 | +MPO can bring the following benefits: | |
| 14 | + | |
| 15 | +* Decreased GPU and CPU workload - no composition shaders needed, no extra | |
| 16 | + buffer copy needed, GPU can remain idle. | |
| 17 | +* Plane independent page flips - No need to be tied to global compositor | |
| 18 | + page-flip present rate, reduced latency, independent timing. | |
| 19 | + | |
| 20 | +.. note:: Keep in mind that MPO is all about power-saving; if you want to learn | |
| 21 | + more about power-save in the display context, check the link: | |
| 22 | + `Power <https://gitlab.freedesktop.org/pq/color-and-hdr/-/blob/main/doc/power.rst>`__. | |
| 23 | + | |
| 24 | +Multiplane Overlay is only available using the DRM atomic model. The atomic | |
| 25 | +model only uses a single userspace IOCTL for configuring the display hardware | |
| 26 | +(modesetting, page-flipping, etc) - drmModeAtomicCommit. To query hardware | |
| 27 | +resources and limitations userspace also calls into drmModeGetResources which | |
| 28 | +reports back the number of planes, CRTCs, and connectors. There are three types | |
| 29 | +of DRM planes that the driver can register and work with: | |
| 30 | + | |
| 31 | +* ``DRM_PLANE_TYPE_PRIMARY``: Primary planes represent a "main" plane for a | |
| 32 | + CRTC, primary planes are the planes operated upon by CRTC modesetting and | |
| 33 | + flipping operations. | |
| 34 | +* ``DRM_PLANE_TYPE_CURSOR``: Cursor planes represent a "cursor" plane for a | |
| 35 | + CRTC. Cursor planes are the planes operated upon by the cursor IOCTLs | |
| 36 | +* ``DRM_PLANE_TYPE_OVERLAY``: Overlay planes represent all non-primary, | |
| 37 | + non-cursor planes. Some drivers refer to these types of planes as "sprites" | |
| 38 | + internally. | |
| 39 | + | |
| 40 | +To illustrate how it works, let's take a look at a device that exposes the | |
| 41 | +following planes to userspace: | |
| 42 | + | |
| 43 | +* 4 Primary planes (1 per CRTC). | |
| 44 | +* 4 Cursor planes (1 per CRTC). | |
| 45 | +* 1 Overlay plane (shared among CRTCs). | |
| 46 | + | |
| 47 | +.. note:: Keep in mind that different ASICs might expose other numbers of | |
| 48 | + planes. | |
| 49 | + | |
| 50 | +For this hardware example, we have 4 pipes (if you don't know what AMD pipe | |
| 51 | +means, look at 'Documentation/gpu/amdgpu/display/dcn-overview.rst', section | |
| 52 | +"AMD Hardware Pipeline"). Typically most AMD devices operate in a pipe-split | |
| 53 | +configuration for optimal single display output (e.g., 2 pipes per plane). | |
| 54 | + | |
| 55 | +A typical MPO configuration from userspace - 1 primary + 1 overlay on a single | |
| 56 | +display - will see 4 pipes in use, 2 per plane. | |
| 57 | + | |
| 58 | +At least 1 pipe must be used per plane (primary and overlay), so for this | |
| 59 | +hypothetical hardware that we are using as an example, we have an absolute | |
| 60 | +limit of 4 planes across all CRTCs. Atomic commits will be rejected for display | |
| 61 | +configurations using more than 4 planes. Again, it is important to stress that | |
| 62 | +every DCN has different restrictions; here, we are just trying to provide the | |
| 63 | +concept idea. | |
| 64 | + | |
| 65 | +Plane Restrictions | |
| 66 | +================== | |
| 67 | + | |
| 68 | +AMDGPU imposes restrictions on the use of DRM planes in the driver. | |
| 69 | + | |
| 70 | +Atomic commits will be rejected for commits which do not follow these | |
| 71 | +restrictions: | |
| 72 | + | |
| 73 | +* Overlay planes must be in ARGB8888 or XRGB8888 format | |
| 74 | +* Planes cannot be placed outside of the CRTC destination rectangle | |
| 75 | +* Planes cannot be downscaled more than 1/4x of their original size | |
| 76 | +* Planes cannot be upscaled more than 16x of their original size | |
| 77 | + | |
| 78 | +Not every property is available on every plane: | |
| 79 | + | |
| 80 | +* Only primary planes have color-space and non-RGB format support | |
| 81 | +* Only overlay planes have alpha blending support | |
| 82 | + | |
| 83 | +Cursor Restrictions | |
| 84 | +=================== | |
| 85 | + | |
| 86 | +Before we start to describe some restrictions around cursor and MPO, see the | |
| 87 | +below image: | |
| 88 | + | |
| 89 | +.. kernel-figure:: mpo-cursor.svg | |
| 90 | + | |
| 91 | +The image on the left side represents how DRM expects the cursor and planes to | |
| 92 | +be blended. However, AMD hardware handles cursors differently, as you can see | |
| 93 | +on the right side; basically, our cursor cannot be drawn outside its associated | |
| 94 | +plane as it is being treated as part of the plane. Another consequence of that | |
| 95 | +is that cursors inherit the color and scale from the plane. | |
| 96 | + | |
| 97 | +As a result of the above behavior, do not use legacy API to set up the cursor | |
| 98 | +plane when working with MPO; otherwise, you might encounter unexpected | |
| 99 | +behavior. | |
| 100 | + | |
| 101 | +In short, AMD HW has no dedicated cursor planes. A cursor is attached to | |
| 102 | +another plane and therefore inherits any scaling or color processing from its | |
| 103 | +parent plane. | |
| 104 | + | |
| 105 | +Use Cases | |
| 106 | +========= | |
| 107 | + | |
| 108 | +Picture-in-Picture (PIP) playback - Underlay strategy | |
| 109 | +----------------------------------------------------- | |
| 110 | + | |
| 111 | +Video playback should be done using the "primary plane as underlay" MPO | |
| 112 | +strategy. This is a 2 planes configuration: | |
| 113 | + | |
| 114 | +* 1 YUV DRM Primary Plane (e.g. NV12 Video) | |
| 115 | +* 1 RGBA DRM Overlay Plane (e.g. ARGB8888 desktop). The compositor should | |
| 116 | + prepare the framebuffers for the planes as follows: | |
| 117 | + - The overlay plane contains general desktop UI, video player controls, and video subtitles | |
| 118 | + - Primary plane contains one or more videos | |
| 119 | + | |
| 120 | +.. note:: Keep in mind that we could extend this configuration to more planes, | |
| 121 | + but that is currently not supported by our driver yet (maybe if we have a | |
| 122 | + userspace request in the future, we can change that). | |
| 123 | + | |
| 124 | +See below a single-video example: | |
| 125 | + | |
| 126 | +.. kernel-figure:: single-display-mpo.svg | |
| 127 | + | |
| 128 | +.. note:: We could extend this behavior to more planes, but that is currently | |
| 129 | + not supported by our driver. | |
| 130 | + | |
| 131 | +The video buffer should be used directly for the primary plane. The video can | |
| 132 | +be scaled and positioned for the desktop using the properties: CRTC_X, CRTC_Y, | |
| 133 | +CRTC_W, and CRTC_H. The primary plane should also have the color encoding and | |
| 134 | +color range properties set based on the source content: | |
| 135 | + | |
| 136 | +* ``COLOR_RANGE``, ``COLOR_ENCODING`` | |
| 137 | + | |
| 138 | +The overlay plane should be the native size of the CRTC. The compositor must | |
| 139 | +draw a transparent cutout for where the video should be placed on the desktop | |
| 140 | +(i.e., set the alpha to zero). The primary plane video will be visible through | |
| 141 | +the underlay. The overlay plane's buffer may remain static while the primary | |
| 142 | +plane's framebuffer is used for standard double-buffered playback. | |
| 143 | + | |
| 144 | +The compositor should create a YUV buffer matching the native size of the CRTC. | |
| 145 | +Each video buffer should be composited onto this YUV buffer for direct YUV | |
| 146 | +scanout. The primary plane should have the color encoding and color range | |
| 147 | +properties set based on the source content: ``COLOR_RANGE``, | |
| 148 | +``COLOR_ENCODING``. However, be mindful that the source color space and | |
| 149 | +encoding match for each video since it affect the entire plane. | |
| 150 | + | |
| 151 | +The overlay plane should be the native size of the CRTC. The compositor must | |
| 152 | +draw a transparent cutout for where each video should be placed on the desktop | |
| 153 | +(i.e., set the alpha to zero). The primary plane videos will be visible through | |
| 154 | +the underlay. The overlay plane's buffer may remain static while compositing | |
| 155 | +operations for video playback will be done on the video buffer. | |
| 156 | + | |
| 157 | +This kernel interface is validated using IGT GPU Tools. The following tests can | |
| 158 | +be run to validate positioning, blending, scaling under a variety of sequences | |
| 159 | +and interactions with operations such as DPMS and S3: | |
| 160 | + | |
| 161 | +- ``kms_plane@plane-panning-bottom-right-pipe-*-planes`` | |
| 162 | +- ``kms_plane@plane-panning-bottom-right-suspend-pipe-*-`` | |
| 163 | +- ``kms_plane@plane-panning-top-left-pipe-*-`` | |
| 164 | +- ``kms_plane@plane-position-covered-pipe-*-`` | |
| 165 | +- ``kms_plane@plane-position-hole-dpms-pipe-*-`` | |
| 166 | +- ``kms_plane@plane-position-hole-pipe-*-`` | |
| 167 | +- ``kms_plane_multiple@atomic-pipe-*-tiling-`` | |
| 168 | +- ``kms_plane_scaling@pipe-*-plane-scaling`` | |
| 169 | +- ``kms_plane_alpha_blend@pipe-*-alpha-basic`` | |
| 170 | +- ``kms_plane_alpha_blend@pipe-*-alpha-transparant-fb`` | |
| 171 | +- ``kms_plane_alpha_blend@pipe-*-alpha-opaque-fb`` | |
| 172 | +- ``kms_plane_alpha_blend@pipe-*-constant-alpha-min`` | |
| 173 | +- ``kms_plane_alpha_blend@pipe-*-constant-alpha-mid`` | |
| 174 | +- ``kms_plane_alpha_blend@pipe-*-constant-alpha-max`` | |
| 175 | + | |
| 176 | +Multiple Display MPO | |
| 177 | +-------------------- | |
| 178 | + | |
| 179 | +AMDGPU supports display MPO when using multiple displays; however, this feature | |
| 180 | +behavior heavily relies on the compositor implementation. Keep in mind that | |
| 181 | +usespace can define different policies. For example, some OSes can use MPO to | |
| 182 | +protect the plane that handles the video playback; notice that we don't have | |
| 183 | +many limitations for a single display. Nonetheless, this manipulation can have | |
| 184 | +many more restrictions for a multi-display scenario. The below example shows a | |
| 185 | +video playback in the middle of two displays, and it is up to the compositor to | |
| 186 | +define a policy on how to handle it: | |
| 187 | + | |
| 188 | +.. kernel-figure:: multi-display-hdcp-mpo.svg | |
| 189 | + | |
| 190 | +Let's discuss some of the hardware limitations we have when dealing with | |
| 191 | +multi-display with MPO. | |
| 192 | + | |
| 193 | +Limitations | |
| 194 | +~~~~~~~~~~~ | |
| 195 | + | |
| 196 | +For simplicity's sake, for discussing the hardware limitation, this | |
| 197 | +documentation supposes an example where we have two displays and video playback | |
| 198 | +that will be moved around different displays. | |
| 199 | + | |
| 200 | +* **Hardware limitations** | |
| 201 | + | |
| 202 | +From the DCN overview page, each display requires at least one pipe and each | |
| 203 | +MPO plane needs another pipe. As a result, when the video is in the middle of | |
| 204 | +the two displays, we need to use 2 pipes. See the example below where we avoid | |
| 205 | +pipe split: | |
| 206 | + | |
| 207 | +- 1 display (1 pipe) + MPO (1 pipe), we will use two pipes | |
| 208 | +- 2 displays (2 pipes) + MPO (1-2 pipes); we will use 4 pipes. MPO in the | |
| 209 | + middle of both displays needs 2 pipes. | |
| 210 | +- 3 Displays (3 pipes) + MPO (1-2 pipes), we need 5 pipes. | |
| 211 | + | |
| 212 | +If we use MPO with multiple displays, the userspace has to decide to enable | |
| 213 | +multiple MPO by the price of limiting the number of external displays supported | |
| 214 | +or disable it in favor of multiple displays; it is a policy decision. For | |
| 215 | +example: | |
| 216 | + | |
| 217 | +* When ASIC has 3 pipes, AMD hardware can NOT support 2 displays with MPO | |
| 218 | +* When ASIC has 4 pipes, AMD hardware can NOT support 3 displays with MPO | |
| 219 | + | |
| 220 | +Let's briefly explore how userspace can handle these two display configurations | |
| 221 | +on an ASIC that only supports three pipes. We can have: | |
| 222 | + | |
| 223 | +.. kernel-figure:: multi-display-hdcp-mpo-less-pipe-ex.svg | |
| 224 | + | |
| 225 | +- Total pipes are 3 | |
| 226 | +- User lights up 2 displays (2 out of 3 pipes are used) | |
| 227 | +- User launches video (1 pipe used for MPO) | |
| 228 | +- Now, if the user moves the video in the middle of 2 displays, one part of the | |
| 229 | + video won't be MPO since we have used 3/3 pipes. | |
| 230 | + | |
| 231 | +* **Scaling limitation** | |
| 232 | + | |
| 233 | +MPO cannot handle scaling less than 0.25 and more than x16. For example: | |
| 234 | + | |
| 235 | +If 4k video (3840x2160) is playing in windowed mode, the physical size of the | |
| 236 | +window cannot be smaller than (960x540). | |
| 237 | + | |
| 238 | +.. note:: These scaling limitations might vary from ASIC to ASIC. | |
| 239 | + | |
| 240 | +* **Size Limitation** | |
| 241 | + | |
| 242 | +The minimum MPO size is 12px. | |
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| @@ -32,6 +32,23 @@ unique_id · 31 unmodified lines | ||
| 32 | 32 | .. kernel-doc:: drivers/gpu/drm/amd/pm/amdgpu_pm.c |
| 33 | 33 | :doc: unique_id |
| 34 | 34 | |
| 35 | +Accelerated Processing Units (APU) Info | |
| 36 | +--------------------------------------- | |
| 37 | + | |
| 38 | +.. csv-table:: | |
| 39 | + :header-rows: 1 | |
| 40 | + :widths: 3, 2, 2, 1, 1, 1 | |
| 41 | + :file: ./apu-asic-info-table.csv | |
| 42 | + | |
| 43 | +Discrete GPU Info | |
| 44 | +----------------- | |
| 45 | + | |
| 46 | +.. csv-table:: | |
| 47 | + :header-rows: 1 | |
| 48 | + :widths: 3, 2, 2, 1, 1, 1 | |
| 49 | + :file: ./dgpu-asic-info-table.csv | |
| 50 | + | |
| 51 | + | |
| 35 | 52 | GPU Memory Usage Information |
| 36 | 53 | ============================ |
| 37 | 54 | |
| @@ -72,7 +72,8 @@ card's RLC (RunList Controller) firmware powers off the gfx engine · 71 unmodified lines | ||
| 72 | 72 | dynamically when there is no workload on gfx or compute pipes. GFXOFF is on by |
| 73 | 73 | default on supported GPUs. |
| 74 | 74 | |
| 75 | −Userspace can interact with GFXOFF through a debugfs interface: | |
| 75 | +Userspace can interact with GFXOFF through a debugfs interface (all values in | |
| 76 | +`uint32_t`, unless otherwise noted): | |
| 76 | 77 | |
| 77 | 78 | ``amdgpu_gfxoff`` |
| 78 | 79 | ----------------- |
| @@ -104,3 +105,18 @@ Read it to check current GFXOFF's status of a GPU:: · 25 unmodified lines | ||
| 104 | 105 | If GFXOFF is enabled, the value will be transitioning around [0, 3], always |
| 105 | 106 | getting into 0 when possible. When it's disabled, it's always at 2. Returns |
| 106 | 107 | ``-EINVAL`` if it's not supported. |
| 108 | + | |
| 109 | +``amdgpu_gfxoff_count`` | |
| 110 | +----------------------- | |
| 111 | + | |
| 112 | +Read it to get the total GFXOFF entry count at the time of query since system | |
| 113 | +power-up. The value is an `uint64_t` type, however, due to firmware limitations, | |
| 114 | +it can currently overflow as an `uint32_t`. *Only supported in vangogh* | |
| 115 | + | |
| 116 | +``amdgpu_gfxoff_residency`` | |
| 117 | +--------------------------- | |
| 118 | + | |
| 119 | +Write 1 to amdgpu_gfxoff_residency to start logging, and 0 to stop. Read it to | |
| 120 | +get average GFXOFF residency % multiplied by 100 during the last logging | |
| 121 | +interval. E.g. a value of 7854 means 78.54% of the time in the last logging | |
| 122 | +interval the GPU was in GFXOFF mode. *Only supported in vangogh* | |
| @@ -122,13 +122,13 @@ format Helper Functions Reference · 121 unmodified lines | ||
| 122 | 122 | .. kernel-doc:: drivers/gpu/drm/drm_format_helper.c |
| 123 | 123 | :export: |
| 124 | 124 | |
| 125 | −Framebuffer CMA Helper Functions Reference | |
| 125 | +Framebuffer DMA Helper Functions Reference | |
| 126 | 126 | ========================================== |
| 127 | 127 | |
| 128 | −.. kernel-doc:: drivers/gpu/drm/drm_fb_cma_helper.c | |
| 129 | − :doc: framebuffer cma helper functions | |
| 128 | +.. kernel-doc:: drivers/gpu/drm/drm_fb_dma_helper.c | |
| 129 | + :doc: framebuffer dma helper functions | |
| 130 | 130 | |
| 131 | −.. kernel-doc:: drivers/gpu/drm/drm_fb_cma_helper.c | |
| 131 | +.. kernel-doc:: drivers/gpu/drm/drm_fb_dma_helper.c | |
| 132 | 132 | :export: |
| 133 | 133 | |
| 134 | 134 | Framebuffer GEM Helper Reference |
| @@ -532,6 +532,8 @@ Standard Plane Properties · 531 unmodified lines | ||
| 532 | 532 | .. kernel-doc:: drivers/gpu/drm/drm_plane.c |
| 533 | 533 | :doc: standard plane properties |
| 534 | 534 | |
| 535 | +.. _plane_composition_properties: | |
| 536 | + | |
| 535 | 537 | Plane Composition Properties |
| 536 | 538 | ---------------------------- |
| 537 | 539 | |
| @@ -300,12 +300,12 @@ Drivers that want to map the GEM object upfront instead of handling page · 299 unmodified lines | ||
| 300 | 300 | faults can implement their own mmap file operation handler. |
| 301 | 301 | |
| 302 | 302 | For platforms without MMU the GEM core provides a helper method |
| 303 | −drm_gem_cma_get_unmapped_area(). The mmap() routines will call this to get a | |
| 303 | +drm_gem_dma_get_unmapped_area(). The mmap() routines will call this to get a | |
| 304 | 304 | proposed address for the mapping. |
| 305 | 305 | |
| 306 | −To use drm_gem_cma_get_unmapped_area(), drivers must fill the struct | |
| 306 | +To use drm_gem_dma_get_unmapped_area(), drivers must fill the struct | |
| 307 | 307 | :c:type:`struct file_operations <file_operations>` get_unmapped_area field with |
| 308 | −a pointer on drm_gem_cma_get_unmapped_area(). | |
| 308 | +a pointer on drm_gem_dma_get_unmapped_area(). | |
| 309 | 309 | |
| 310 | 310 | More detailed information about get_unmapped_area can be found in |
| 311 | 311 | Documentation/admin-guide/mm/nommu-mmap.rst |
| @@ -355,16 +355,16 @@ GEM Function Reference · 43 unmodified lines | ||
| 355 | 355 | .. kernel-doc:: drivers/gpu/drm/drm_gem.c |
| 356 | 356 | :export: |
| 357 | 357 | |
| 358 | −GEM CMA Helper Functions Reference | |
| 358 | +GEM DMA Helper Functions Reference | |
| 359 | 359 | ---------------------------------- |
| 360 | 360 | |
| 361 | −.. kernel-doc:: drivers/gpu/drm/drm_gem_cma_helper.c | |
| 362 | − :doc: cma helpers | |
| 361 | +.. kernel-doc:: drivers/gpu/drm/drm_gem_dma_helper.c | |
| 362 | + :doc: dma helpers | |
| 363 | 363 | |
| 364 | −.. kernel-doc:: include/drm/drm_gem_cma_helper.h | |
| 364 | +.. kernel-doc:: include/drm/drm_gem_dma_helper.h | |
| 365 | 365 | :internal: |
| 366 | 366 | |
| 367 | −.. kernel-doc:: drivers/gpu/drm/drm_gem_cma_helper.c | |
| 367 | +.. kernel-doc:: drivers/gpu/drm/drm_gem_dma_helper.c | |
| 368 | 368 | :export: |
| 369 | 369 | |
| 370 | 370 | GEM SHMEM Helper Function Reference |
| @@ -322,18 +322,6 @@ Contact: Daniel Vetter, Noralf Tronnes · 321 unmodified lines | ||
| 322 | 322 | |
| 323 | 323 | Level: Advanced |
| 324 | 324 | |
| 325 | −idr_init_base() | |
| 326 | −--------------- | |
| 327 | − | |
| 328 | −DRM core&drivers uses a lot of idr (integer lookup directories) for mapping | |
| 329 | −userspace IDs to internal objects, and in most places ID=0 means NULL and hence | |
| 330 | −is never used. Switching to idr_init_base() for these would make the idr more | |
| 331 | −efficient. | |
| 332 | − | |
| 333 | −Contact: Daniel Vetter | |
| 334 | − | |
| 335 | −Level: Starter | |
| 336 | − | |
| 337 | 325 | struct drm_gem_object_funcs |
| 338 | 326 | --------------------------- |
| 339 | 327 | |
| @@ -343,19 +331,6 @@ converted, except for struct drm_driver.gem_prime_mmap. · 3 unmodified lines | ||
| 343 | 331 | |
| 344 | 332 | Level: Intermediate |
| 345 | 333 | |
| 346 | −Rename CMA helpers to DMA helpers | |
| 347 | −--------------------------------- | |
| 348 | − | |
| 349 | −CMA (standing for contiguous memory allocator) is really a bit an accident of | |
| 350 | −what these were used for first, a much better name would be DMA helpers. In the | |
| 351 | −text these should even be called coherent DMA memory helpers (so maybe CDM, but | |
| 352 | −no one knows what that means) since underneath they just use dma_alloc_coherent. | |
| 353 | − | |
| 354 | −Contact: Laurent Pinchart, Daniel Vetter | |
| 355 | − | |
| 356 | −Level: Intermediate (mostly because it is a huge tasks without good partial | |
| 357 | −milestones, not technically itself that challenging) | |
| 358 | − | |
| 359 | 334 | connector register/unregister fixes |
| 360 | 335 | ----------------------------------- |
| 361 | 336 | |
| @@ -617,17 +592,6 @@ Contact: Javier Martinez Canillas <javierm@redhat.com> · 255 unmodified lines | ||
| 617 | 592 | |
| 618 | 593 | Level: Intermediate |
| 619 | 594 | |
| 620 | −Convert Kernel Selftests (kselftest) to KUnit tests when appropriate | |
| 621 | −-------------------------------------------------------------------- | |
| 622 | − | |
| 623 | −Many of the `Kselftest <https://www.kernel.org/doc/html/latest/dev-tools/kselftest.html>`_ | |
| 624 | −tests in DRM could be converted to Kunit tests instead, since that framework | |
| 625 | −is more suitable for unit testing. | |
| 626 | − | |
| 627 | −Contact: Javier Martinez Canillas <javierm@redhat.com> | |
| 628 | − | |
| 629 | −Level: Starter | |
| 630 | − | |
| 631 | 595 | Enable trinity for DRM |
| 632 | 596 | ---------------------- |
| 633 | 597 | |
| @@ -118,15 +118,10 @@ Add Plane Features · 117 unmodified lines | ||
| 118 | 118 | |
| 119 | 119 | There's lots of plane features we could add support for: |
| 120 | 120 | |
| 121 | −- Clearing primary plane: clear primary plane before plane composition (at the | |
| 122 | − start) for correctness of pixel blend ops. It also guarantees alpha channel | |
| 123 | − is cleared in the target buffer for stable crc. [Good to get started] | |
| 124 | − | |
| 125 | 121 | - ARGB format on primary plane: blend the primary plane into background with |
| 126 | 122 | translucent alpha. |
| 127 | 123 | |
| 128 | −- Support when the primary plane isn't exactly matching the output size: blend | |
| 129 | − the primary plane into the black background. | |
| 124 | +- Add background color KMS property[Good to get started]. | |
| 130 | 125 | |
| 131 | 126 | - Full alpha blending on all planes. |
| 132 | 127 | |
| @@ -6431,6 +6431,11 @@ S: Maintained · 6430 unmodified lines | ||
| 6431 | 6431 | F: Documentation/devicetree/bindings/display/panel/feiyang,fy07024di26a30d.yaml |
| 6432 | 6432 | F: drivers/gpu/drm/panel/panel-feiyang-fy07024di26a30d.c |
| 6433 | 6433 | |
| 6434 | +DRM DRIVER FOR GENERIC EDP PANELS | |
| 6435 | +R: Douglas Anderson <dianders@chromium.org> | |
| 6436 | +F: Documentation/devicetree/bindings/display/panel/panel-edp.yaml | |
| 6437 | +F: drivers/gpu/drm/panel/panel-edp.c | |
| 6438 | + | |
| 6434 | 6439 | DRM DRIVER FOR GENERIC USB DISPLAY |
| 6435 | 6440 | M: Noralf Trønnes <noralf@tronnes.org> |
| 6436 | 6441 | S: Maintained |
| @@ -136,6 +136,10 @@ struct dma_fence *dma_fence_get_stub(void) · 135 unmodified lines | ||
| 136 | 136 | &dma_fence_stub_ops, |
| 137 | 137 | &dma_fence_stub_lock, |
| 138 | 138 | 0, 0); |
| 139 | + | |
| 140 | + set_bit(DMA_FENCE_FLAG_ENABLE_SIGNAL_BIT, | |
| 141 | + &dma_fence_stub.flags); | |
| 142 | + | |
| 139 | 143 | dma_fence_signal_locked(&dma_fence_stub); |
| 140 | 144 | } |
| 141 | 145 | spin_unlock(&dma_fence_stub_lock); |
| @@ -161,6 +165,10 @@ struct dma_fence *dma_fence_allocate_private_stub(void) · 19 unmodified lines | ||
| 161 | 165 | &dma_fence_stub_ops, |
| 162 | 166 | &dma_fence_stub_lock, |
| 163 | 167 | 0, 0); |
| 168 | + | |
| 169 | + set_bit(DMA_FENCE_FLAG_ENABLE_SIGNAL_BIT, | |
| 170 | + &dma_fence_stub.flags); | |
| 171 | + | |
| 164 | 172 | dma_fence_signal(fence); |
| 165 | 173 | |
| 166 | 174 | return fence; |
| @@ -500,6 +508,8 @@ dma_fence_wait_timeout(struct dma_fence *fence, bool intr, signed long timeout) · 333 unmodified lines | ||
| 500 | 508 | |
| 501 | 509 | __dma_fence_might_wait(); |
| 502 | 510 | |
| 511 | + dma_fence_enable_sw_signaling(fence); | |
| 512 | + | |
| 503 | 513 | trace_dma_fence_wait_start(fence); |
| 504 | 514 | if (fence->ops->wait) |
| 505 | 515 | ret = fence->ops->wait(fence, intr, timeout); |
| @@ -601,9 +611,6 @@ void dma_fence_enable_sw_signaling(struct dma_fence *fence) · 95 unmodified lines | ||
| 601 | 611 | { |
| 602 | 612 | unsigned long flags; |
| 603 | 613 | |
| 604 | − if (test_bit(DMA_FENCE_FLAG_SIGNALED_BIT, &fence->flags)) | |
| 605 | − return; | |
| 606 | − | |
| 607 | 614 | spin_lock_irqsave(fence->lock, flags); |
| 608 | 615 | __dma_fence_enable_signaling(fence); |
| 609 | 616 | spin_unlock_irqrestore(fence->lock, flags); |
| @@ -756,19 +763,16 @@ dma_fence_default_wait(struct dma_fence *fence, bool intr, signed long timeout) · 146 unmodified lines | ||
| 756 | 763 | unsigned long flags; |
| 757 | 764 | signed long ret = timeout ? timeout : 1; |
| 758 | 765 | |
| 759 | − if (test_bit(DMA_FENCE_FLAG_SIGNALED_BIT, &fence->flags)) | |
| 760 | − return ret; | |
| 761 | − | |
| 762 | 766 | spin_lock_irqsave(fence->lock, flags); |
| 763 | 767 | |
| 768 | + if (test_bit(DMA_FENCE_FLAG_SIGNALED_BIT, &fence->flags)) | |
| 769 | + goto out; | |
| 770 | + | |
| 764 | 771 | if (intr && signal_pending(current)) { |
| 765 | 772 | ret = -ERESTARTSYS; |
| 766 | 773 | goto out; |
| 767 | 774 | } |
| 768 | 775 | |
| 769 | − if (!__dma_fence_enable_signaling(fence)) | |
| 770 | − goto out; | |
| 771 | − | |
| 772 | 776 | if (!timeout) { |
| 773 | 777 | ret = 0; |
| 774 | 778 | goto out; |
| @@ -87,6 +87,8 @@ static int sanitycheck(void *arg) · 86 unmodified lines | ||
| 87 | 87 | if (!chain) |
| 88 | 88 | err = -ENOMEM; |
| 89 | 89 | |
| 90 | + dma_fence_enable_sw_signaling(chain); | |
| 91 | + | |
| 90 | 92 | dma_fence_signal(f); |
| 91 | 93 | dma_fence_put(f); |
| 92 | 94 | |
| @@ -143,6 +145,8 @@ static int fence_chains_init(struct fence_chains *fc, unsigned int count, · 50 unmodified lines | ||
| 143 | 145 | } |
| 144 | 146 | |
| 145 | 147 | fc->tail = fc->chains[i]; |
| 148 | + | |
| 149 | + dma_fence_enable_sw_signaling(fc->chains[i]); | |
| 146 | 150 | } |
| 147 | 151 | |
| 148 | 152 | fc->chain_length = i; |
| @@ -102,6 +102,8 @@ static int sanitycheck(void *arg) · 101 unmodified lines | ||
| 102 | 102 | if (!f) |
| 103 | 103 | return -ENOMEM; |
| 104 | 104 | |
| 105 | + dma_fence_enable_sw_signaling(f); | |
| 106 | + | |
| 105 | 107 | array = mock_array(1, f); |
| 106 | 108 | if (!array) |
| 107 | 109 | return -ENOMEM; |
| @@ -124,12 +126,16 @@ static int unwrap_array(void *arg) · 16 unmodified lines | ||
| 124 | 126 | if (!f1) |
| 125 | 127 | return -ENOMEM; |
| 126 | 128 | |
| 129 | + dma_fence_enable_sw_signaling(f1); | |
| 130 | + | |
| 127 | 131 | f2 = mock_fence(); |
| 128 | 132 | if (!f2) { |
| 129 | 133 | dma_fence_put(f1); |
| 130 | 134 | return -ENOMEM; |
| 131 | 135 | } |
| 132 | 136 | |
| 137 | + dma_fence_enable_sw_signaling(f2); | |
| 138 | + | |
| 133 | 139 | array = mock_array(2, f1, f2); |
| 134 | 140 | if (!array) |
| 135 | 141 | return -ENOMEM; |
| @@ -164,12 +170,16 @@ static int unwrap_chain(void *arg) · 28 unmodified lines | ||
| 164 | 170 | if (!f1) |
| 165 | 171 | return -ENOMEM; |
| 166 | 172 | |
| 173 | + dma_fence_enable_sw_signaling(f1); | |
| 174 | + | |
| 167 | 175 | f2 = mock_fence(); |
| 168 | 176 | if (!f2) { |
| 169 | 177 | dma_fence_put(f1); |
| 170 | 178 | return -ENOMEM; |
| 171 | 179 | } |
| 172 | 180 | |
| 181 | + dma_fence_enable_sw_signaling(f2); | |
| 182 | + | |
| 173 | 183 | chain = mock_chain(f1, f2); |
| 174 | 184 | if (!chain) |
| 175 | 185 | return -ENOMEM; |
| @@ -204,12 +214,16 @@ static int unwrap_chain_array(void *arg) · 28 unmodified lines | ||
| 204 | 214 | if (!f1) |
| 205 | 215 | return -ENOMEM; |
| 206 | 216 | |
| 217 | + dma_fence_enable_sw_signaling(f1); | |
| 218 | + | |
| 207 | 219 | f2 = mock_fence(); |
| 208 | 220 | if (!f2) { |
| 209 | 221 | dma_fence_put(f1); |
| 210 | 222 | return -ENOMEM; |
| 211 | 223 | } |
| 212 | 224 | |
| 225 | + dma_fence_enable_sw_signaling(f2); | |
| 226 | + | |
| 213 | 227 | array = mock_array(2, f1, f2); |
| 214 | 228 | if (!array) |
| 215 | 229 | return -ENOMEM; |
| @@ -248,12 +262,16 @@ static int unwrap_merge(void *arg) · 32 unmodified lines | ||
| 248 | 262 | if (!f1) |
| 249 | 263 | return -ENOMEM; |
| 250 | 264 | |
| 265 | + dma_fence_enable_sw_signaling(f1); | |
| 266 | + | |
| 251 | 267 | f2 = mock_fence(); |
| 252 | 268 | if (!f2) { |
| 253 | 269 | err = -ENOMEM; |
| 254 | 270 | goto error_put_f1; |
| 255 | 271 | } |
| 256 | 272 | |
| 273 | + dma_fence_enable_sw_signaling(f2); | |
| 274 | + | |
| 257 | 275 | f3 = dma_fence_unwrap_merge(f1, f2); |
| 258 | 276 | if (!f3) { |
| 259 | 277 | err = -ENOMEM; |
| @@ -296,10 +314,14 @@ static int unwrap_merge_complex(void *arg) · 36 unmodified lines | ||
| 296 | 314 | if (!f1) |
| 297 | 315 | return -ENOMEM; |
| 298 | 316 | |
| 317 | + dma_fence_enable_sw_signaling(f1); | |
| 318 | + | |
| 299 | 319 | f2 = mock_fence(); |
| 300 | 320 | if (!f2) |
| 301 | 321 | goto error_put_f1; |
| 302 | 322 | |
| 323 | + dma_fence_enable_sw_signaling(f2); | |
| 324 | + | |
| 303 | 325 | f3 = dma_fence_unwrap_merge(f1, f2); |
| 304 | 326 | if (!f3) |
| 305 | 327 | goto error_put_f2; |
| @@ -102,6 +102,8 @@ static int sanitycheck(void *arg) · 101 unmodified lines | ||
| 102 | 102 | if (!f) |
| 103 | 103 | return -ENOMEM; |
| 104 | 104 | |
| 105 | + dma_fence_enable_sw_signaling(f); | |
| 106 | + | |
| 105 | 107 | dma_fence_signal(f); |
| 106 | 108 | dma_fence_put(f); |
| 107 | 109 | |
| @@ -117,6 +119,8 @@ static int test_signaling(void *arg) · 9 unmodified lines | ||
| 117 | 119 | if (!f) |
| 118 | 120 | return -ENOMEM; |
| 119 | 121 | |
| 122 | + dma_fence_enable_sw_signaling(f); | |
| 123 | + | |
| 120 | 124 | if (dma_fence_is_signaled(f)) { |
| 121 | 125 | pr_err("Fence unexpectedly signaled on creation\n"); |
| 122 | 126 | goto err_free; |
| @@ -190,6 +194,8 @@ static int test_late_add_callback(void *arg) · 67 unmodified lines | ||
| 190 | 194 | if (!f) |
| 191 | 195 | return -ENOMEM; |
| 192 | 196 | |
| 197 | + dma_fence_enable_sw_signaling(f); | |
| 198 | + | |
| 193 | 199 | dma_fence_signal(f); |
| 194 | 200 | |
| 195 | 201 | if (!dma_fence_add_callback(f, &cb.cb, simple_callback)) { |
| @@ -282,6 +288,8 @@ static int test_status(void *arg) · 86 unmodified lines | ||
| 282 | 288 | if (!f) |
| 283 | 289 | return -ENOMEM; |
| 284 | 290 | |
| 291 | + dma_fence_enable_sw_signaling(f); | |
| 292 | + | |
| 285 | 293 | if (dma_fence_get_status(f)) { |
| 286 | 294 | pr_err("Fence unexpectedly has signaled status on creation\n"); |
| 287 | 295 | goto err_free; |
| @@ -308,6 +316,8 @@ static int test_error(void *arg) · 20 unmodified lines | ||
| 308 | 316 | if (!f) |
| 309 | 317 | return -ENOMEM; |
| 310 | 318 | |
| 319 | + dma_fence_enable_sw_signaling(f); | |
| 320 | + | |
| 311 | 321 | dma_fence_set_error(f, -EIO); |
| 312 | 322 | |
| 313 | 323 | if (dma_fence_get_status(f)) { |
| @@ -337,6 +347,8 @@ static int test_wait(void *arg) · 23 unmodified lines | ||
| 337 | 347 | if (!f) |
| 338 | 348 | return -ENOMEM; |
| 339 | 349 | |
| 350 | + dma_fence_enable_sw_signaling(f); | |
| 351 | + | |
| 340 | 352 | if (dma_fence_wait_timeout(f, false, 0) != -ETIME) { |
| 341 | 353 | pr_err("Wait reported complete before being signaled\n"); |
| 342 | 354 | goto err_free; |
| @@ -379,6 +391,8 @@ static int test_wait_timeout(void *arg) · 36 unmodified lines | ||
| 379 | 391 | if (!wt.f) |
| 380 | 392 | return -ENOMEM; |
| 381 | 393 | |
| 394 | + dma_fence_enable_sw_signaling(wt.f); | |
| 395 | + | |
| 382 | 396 | if (dma_fence_wait_timeout(wt.f, false, 1) != -ETIME) { |
| 383 | 397 | pr_err("Wait reported complete before being signaled\n"); |
| 384 | 398 | goto err_free; |
| @@ -458,6 +472,8 @@ static int thread_signal_callback(void *arg) · 73 unmodified lines | ||
| 458 | 472 | break; |
| 459 | 473 | } |
| 460 | 474 | |
| 475 | + dma_fence_enable_sw_signaling(f1); | |
| 476 | + | |
| 461 | 477 | rcu_assign_pointer(t->fences[t->id], f1); |
| 462 | 478 | smp_wmb(); |
| 463 | 479 | |
| @@ -45,6 +45,8 @@ static int sanitycheck(void *arg) · 44 unmodified lines | ||
| 45 | 45 | if (!f) |
| 46 | 46 | return -ENOMEM; |
| 47 | 47 | |
| 48 | + dma_fence_enable_sw_signaling(f); | |
| 49 | + | |
| 48 | 50 | dma_fence_signal(f); |
| 49 | 51 | dma_fence_put(f); |
| 50 | 52 | |
| @@ -69,6 +71,8 @@ static int test_signaling(void *arg) · 18 unmodified lines | ||
| 69 | 71 | if (!f) |
| 70 | 72 | return -ENOMEM; |
| 71 | 73 | |
| 74 | + dma_fence_enable_sw_signaling(f); | |
| 75 | + | |
| 72 | 76 | dma_resv_init(&resv); |
| 73 | 77 | r = dma_resv_lock(&resv, NULL); |
| 74 | 78 | if (r) { |
| @@ -114,6 +118,8 @@ static int test_for_each(void *arg) · 39 unmodified lines | ||
| 114 | 118 | if (!f) |
| 115 | 119 | return -ENOMEM; |
| 116 | 120 | |
| 121 | + dma_fence_enable_sw_signaling(f); | |
| 122 | + | |
| 117 | 123 | dma_resv_init(&resv); |
| 118 | 124 | r = dma_resv_lock(&resv, NULL); |
| 119 | 125 | if (r) { |
| @@ -173,6 +179,8 @@ static int test_for_each_unlocked(void *arg) · 53 unmodified lines | ||
| 173 | 179 | if (!f) |
| 174 | 180 | return -ENOMEM; |
| 175 | 181 | |
| 182 | + dma_fence_enable_sw_signaling(f); | |
| 183 | + | |
| 176 | 184 | dma_resv_init(&resv); |
| 177 | 185 | r = dma_resv_lock(&resv, NULL); |
| 178 | 186 | if (r) { |
| @@ -244,6 +252,8 @@ static int test_get_fences(void *arg) · 65 unmodified lines | ||
| 244 | 252 | if (!f) |
| 245 | 253 | return -ENOMEM; |
| 246 | 254 | |
| 255 | + dma_fence_enable_sw_signaling(f); | |
| 256 | + | |
| 247 | 257 | dma_resv_init(&resv); |
| 248 | 258 | r = dma_resv_lock(&resv, NULL); |
| 249 | 259 | if (r) { |
| @@ -132,7 +132,7 @@ EXPORT_SYMBOL(sync_file_get_fence); · 131 unmodified lines | ||
| 132 | 132 | char *sync_file_get_name(struct sync_file *sync_file, char *buf, int len) |
| 133 | 133 | { |
| 134 | 134 | if (sync_file->user_name[0]) { |
| 135 | − strlcpy(buf, sync_file->user_name, len); | |
| 135 | + strscpy(buf, sync_file->user_name, len); | |
| 136 | 136 | } else { |
| 137 | 137 | struct dma_fence *fence = sync_file->fence; |
| 138 | 138 | |
| @@ -172,7 +172,7 @@ static struct sync_file *sync_file_merge(const char *name, struct sync_file *a, · 33 unmodified lines | ||
| 172 | 172 | return NULL; |
| 173 | 173 | } |
| 174 | 174 | sync_file->fence = fence; |
| 175 | − strlcpy(sync_file->user_name, name, sizeof(sync_file->user_name)); | |
| 175 | + strscpy(sync_file->user_name, name, sizeof(sync_file->user_name)); | |
| 176 | 176 | return sync_file; |
| 177 | 177 | } |
| 178 | 178 | |
| @@ -262,9 +262,9 @@ err_put_fd: · 83 unmodified lines | ||
| 262 | 262 | static int sync_fill_fence_info(struct dma_fence *fence, |
| 263 | 263 | struct sync_fence_info *info) |
| 264 | 264 | { |
| 265 | − strlcpy(info->obj_name, fence->ops->get_timeline_name(fence), | |
| 265 | + strscpy(info->obj_name, fence->ops->get_timeline_name(fence), | |
| 266 | 266 | sizeof(info->obj_name)); |
| 267 | − strlcpy(info->driver_name, fence->ops->get_driver_name(fence), | |
| 267 | + strscpy(info->driver_name, fence->ops->get_driver_name(fence), | |
| 268 | 268 | sizeof(info->driver_name)); |
| 269 | 269 | |
| 270 | 270 | info->status = dma_fence_get_status(fence); |
| @@ -124,17 +124,20 @@ static int begin_cpu_udmabuf(struct dma_buf *buf, · 123 unmodified lines | ||
| 124 | 124 | { |
| 125 | 125 | struct udmabuf *ubuf = buf->priv; |
| 126 | 126 | struct device *dev = ubuf->device->this_device; |
| 127 | + int ret = 0; | |
| 127 | 128 | |
| 128 | 129 | if (!ubuf->sg) { |
| 129 | 130 | ubuf->sg = get_sg_table(dev, buf, direction); |
| 130 | − if (IS_ERR(ubuf->sg)) | |
| 131 | − return PTR_ERR(ubuf->sg); | |
| 131 | + if (IS_ERR(ubuf->sg)) { | |
| 132 | + ret = PTR_ERR(ubuf->sg); | |
| 133 | + ubuf->sg = NULL; | |
| 134 | + } | |
| 132 | 135 | } else { |
| 133 | 136 | dma_sync_sg_for_cpu(dev, ubuf->sg->sgl, ubuf->sg->nents, |
| 134 | 137 | direction); |
| 135 | 138 | } |
| 136 | 139 | |
| 137 | − return 0; | |
| 140 | + return ret; | |
| 138 | 141 | } |
| 139 | 142 | |
| 140 | 143 | static int end_cpu_udmabuf(struct dma_buf *buf, |
| @@ -94,6 +94,10 @@ static __init int sysfb_init(void) · 93 unmodified lines | ||
| 94 | 94 | name = "efi-framebuffer"; |
| 95 | 95 | else if (si->orig_video_isVGA == VIDEO_TYPE_VLFB) |
| 96 | 96 | name = "vesa-framebuffer"; |
| 97 | + else if (si->orig_video_isVGA == VIDEO_TYPE_VGAC) | |
| 98 | + name = "vga-framebuffer"; | |
| 99 | + else if (si->orig_video_isVGA == VIDEO_TYPE_EGAC) | |
| 100 | + name = "ega-framebuffer"; | |
| 97 | 101 | else |
| 98 | 102 | name = "platform-framebuffer"; |
| 99 | 103 | |
| @@ -31,6 +31,7 @@ menuconfig DRM · 30 unmodified lines | ||
| 31 | 31 | config DRM_MIPI_DBI |
| 32 | 32 | tristate |
| 33 | 33 | depends on DRM |
| 34 | + select DRM_KMS_HELPER | |
| 34 | 35 | |
| 35 | 36 | config DRM_MIPI_DSI |
| 36 | 37 | bool |
| @@ -50,10 +51,9 @@ config DRM_DEBUG_MM · 13 unmodified lines | ||
| 50 | 51 | |
| 51 | 52 | If in doubt, say "N". |
| 52 | 53 | |
| 53 | −config DRM_DEBUG_SELFTEST | |
| 54 | − tristate "kselftests for DRM" | |
| 55 | − depends on DRM | |
| 56 | − depends on DEBUG_KERNEL | |
| 54 | +config DRM_KUNIT_TEST | |
| 55 | + tristate "KUnit tests for DRM" if !KUNIT_ALL_TESTS | |
| 56 | + depends on DRM && KUNIT | |
| 57 | 57 | select PRIME_NUMBERS |
| 58 | 58 | select DRM_DISPLAY_DP_HELPER |
| 59 | 59 | select DRM_DISPLAY_HELPER |
| @@ -61,19 +61,6 @@ config DRM_DEBUG_SELFTEST · 1 unmodified line | ||
| 61 | 61 | select DRM_KMS_HELPER |
| 62 | 62 | select DRM_BUDDY |
| 63 | 63 | select DRM_EXPORT_FOR_TESTS if m |
| 64 | − default n | |
| 65 | − help | |
| 66 | − This option provides kernel modules that can be used to run | |
| 67 | − various selftests on parts of the DRM api. This option is not | |
| 68 | − useful for distributions or general kernels, but only for kernel | |
| 69 | − developers working on DRM and associated drivers. | |
| 70 | − | |
| 71 | − If in doubt, say "N". | |
| 72 | − | |
| 73 | −config DRM_KUNIT_TEST | |
| 74 | − tristate "KUnit tests for DRM" if !KUNIT_ALL_TESTS | |
| 75 | − depends on DRM && KUNIT=y | |
| 76 | − select DRM_KMS_HELPER | |
| 77 | 64 | default KUNIT_ALL_TESTS |
| 78 | 65 | help |
| 79 | 66 | This builds unit tests for DRM. This option is not useful for |
| @@ -214,11 +201,11 @@ config DRM_TTM_HELPER · 134 unmodified lines | ||
| 214 | 201 | help |
| 215 | 202 | Helpers for ttm-based gem objects |
| 216 | 203 | |
| 217 | −config DRM_GEM_CMA_HELPER | |
| 204 | +config DRM_GEM_DMA_HELPER | |
| 218 | 205 | tristate |
| 219 | 206 | depends on DRM |
| 220 | 207 | help |
| 221 | − Choose this if you need the GEM CMA helper functions | |
| 208 | + Choose this if you need the GEM DMA helper functions | |
| 222 | 209 | |
| 223 | 210 | config DRM_GEM_SHMEM_HELPER |
| 224 | 211 | tristate |
| @@ -40,9 +40,9 @@ obj-$(CONFIG_DRM_PANEL_ORIENTATION_QUIRKS) += drm_panel_orientation_quirks.o · 39 unmodified lines | ||
| 40 | 40 | |
| 41 | 41 | obj-$(CONFIG_DRM_BUDDY) += drm_buddy.o |
| 42 | 42 | |
| 43 | −drm_cma_helper-y := drm_gem_cma_helper.o | |
| 44 | −drm_cma_helper-$(CONFIG_DRM_KMS_HELPER) += drm_fb_cma_helper.o | |
| 45 | −obj-$(CONFIG_DRM_GEM_CMA_HELPER) += drm_cma_helper.o | |
| 43 | +drm_dma_helper-y := drm_gem_dma_helper.o | |
| 44 | +drm_dma_helper-$(CONFIG_DRM_KMS_HELPER) += drm_fb_dma_helper.o | |
| 45 | +obj-$(CONFIG_DRM_GEM_DMA_HELPER) += drm_dma_helper.o | |
| 46 | 46 | |
| 47 | 47 | drm_shmem_helper-y := drm_gem_shmem_helper.o |
| 48 | 48 | obj-$(CONFIG_DRM_GEM_SHMEM_HELPER) += drm_shmem_helper.o |
| @@ -75,7 +75,6 @@ obj-$(CONFIG_DRM_KMS_HELPER) += drm_kms_helper.o · 26 unmodified lines | ||
| 75 | 75 | # Drivers and the rest |
| 76 | 76 | # |
| 77 | 77 | |
| 78 | −obj-$(CONFIG_DRM_DEBUG_SELFTEST) += selftests/ | |
| 79 | 78 | obj-$(CONFIG_DRM_KUNIT_TEST) += tests/ |
| 80 | 79 | |
| 81 | 80 | obj-$(CONFIG_DRM_MIPI_DBI) += drm_mipi_dbi.o |
| @@ -75,7 +75,7 @@ amdgpu-y += \ · 74 unmodified lines | ||
| 75 | 75 | vi.o mxgpu_vi.o nbio_v6_1.o soc15.o emu_soc.o mxgpu_ai.o nbio_v7_0.o vega10_reg_init.o \ |
| 76 | 76 | vega20_reg_init.o nbio_v7_4.o nbio_v2_3.o nv.o arct_reg_init.o mxgpu_nv.o \ |
| 77 | 77 | nbio_v7_2.o hdp_v4_0.o hdp_v5_0.o aldebaran_reg_init.o aldebaran.o soc21.o \ |
| 78 | − nbio_v4_3.o hdp_v6_0.o nbio_v7_7.o hdp_v5_2.o lsdma_v6_0.o | |
| 78 | + sienna_cichlid.o nbio_v4_3.o hdp_v6_0.o nbio_v7_7.o hdp_v5_2.o lsdma_v6_0.o | |
| 79 | 79 | |
| 80 | 80 | # add DF block |
| 81 | 81 | amdgpu-y += \ |
| @@ -89,7 +89,7 @@ amdgpu-y += \ · 7 unmodified lines | ||
| 89 | 89 | gfxhub_v1_0.o mmhub_v1_0.o gmc_v9_0.o gfxhub_v1_1.o mmhub_v9_4.o \ |
| 90 | 90 | gfxhub_v2_0.o mmhub_v2_0.o gmc_v10_0.o gfxhub_v2_1.o mmhub_v2_3.o \ |
| 91 | 91 | mmhub_v1_7.o gfxhub_v3_0.o mmhub_v3_0.o mmhub_v3_0_2.o gmc_v11_0.o \ |
| 92 | − mmhub_v3_0_1.o | |
| 92 | + mmhub_v3_0_1.o gfxhub_v3_0_3.o | |
| 93 | 93 | |
| 94 | 94 | # add UMC block |
| 95 | 95 | amdgpu-y += \ |
| @@ -134,7 +134,8 @@ amdgpu-y += \ · 38 unmodified lines | ||
| 134 | 134 | gfx_v9_4_2.o \ |
| 135 | 135 | gfx_v10_0.o \ |
| 136 | 136 | imu_v11_0.o \ |
| 137 | − gfx_v11_0.o | |
| 137 | + gfx_v11_0.o \ | |
| 138 | + imu_v11_0_3.o | |
| 138 | 139 | |
| 139 | 140 | # add async DMA block |
| 140 | 141 | amdgpu-y += \ |
| @@ -274,6 +274,9 @@ extern int amdgpu_vcnfw_log; · 273 unmodified lines | ||
| 274 | 274 | #define AMDGPU_RESET_VCE (1 << 13) |
| 275 | 275 | #define AMDGPU_RESET_VCE1 (1 << 14) |
| 276 | 276 | |
| 277 | +#define AMDGPU_RESET_LEVEL_SOFT_RECOVERY (1 << 0) | |
| 278 | +#define AMDGPU_RESET_LEVEL_MODE2 (1 << 1) | |
| 279 | + | |
| 277 | 280 | /* max cursor sizes (in pixels) */ |
| 278 | 281 | #define CIK_CURSOR_WIDTH 128 |
| 279 | 282 | #define CIK_CURSOR_HEIGHT 128 |
| @@ -882,6 +885,7 @@ struct amdgpu_device { · 602 unmodified lines | ||
| 882 | 885 | u64 fence_context; |
| 883 | 886 | unsigned num_rings; |
| 884 | 887 | struct amdgpu_ring *rings[AMDGPU_MAX_RINGS]; |
| 888 | + struct dma_fence __rcu *gang_submit; | |
| 885 | 889 | bool ib_pool_ready; |
| 886 | 890 | struct amdgpu_sa_manager ib_pools[AMDGPU_IB_POOL_MAX]; |
| 887 | 891 | struct amdgpu_sched gpu_sched[AMDGPU_HW_IP_NUM][AMDGPU_RING_PRIO_MAX]; |
| @@ -1060,6 +1064,9 @@ struct amdgpu_device { · 172 unmodified lines | ||
| 1060 | 1064 | uint32_t scpm_status; |
| 1061 | 1065 | |
| 1062 | 1066 | struct work_struct reset_work; |
| 1067 | + | |
| 1068 | + uint32_t amdgpu_reset_level_mask; | |
| 1069 | + bool job_hang; | |
| 1063 | 1070 | }; |
| 1064 | 1071 | |
| 1065 | 1072 | static inline struct amdgpu_device *drm_to_adev(struct drm_device *ddev) |
| @@ -1288,6 +1295,8 @@ u32 amdgpu_device_pcie_port_rreg(struct amdgpu_device *adev, · 222 unmodified lines | ||
| 1288 | 1295 | u32 reg); |
| 1289 | 1296 | void amdgpu_device_pcie_port_wreg(struct amdgpu_device *adev, |
| 1290 | 1297 | u32 reg, u32 v); |
| 1298 | +struct dma_fence *amdgpu_device_switch_gang(struct amdgpu_device *adev, | |
| 1299 | + struct dma_fence *gang); | |
| 1291 | 1300 | |
| 1292 | 1301 | /* atpx handler */ |
| 1293 | 1302 | #if defined(CONFIG_VGA_SWITCHEROO) |
| @@ -1,3 +1,4 @@ | ||
| 1 | +// SPDX-License-Identifier: MIT | |
| 1 | 2 | /* |
| 2 | 3 | * Copyright 2012 Advanced Micro Devices, Inc. |
| 3 | 4 | * |
| @@ -849,6 +850,7 @@ int amdgpu_acpi_init(struct amdgpu_device *adev) · 845 unmodified lines | ||
| 849 | 850 | if (amdgpu_device_has_dc_support(adev)) { |
| 850 | 851 | #if defined(CONFIG_DRM_AMD_DC) |
| 851 | 852 | struct amdgpu_display_manager *dm = &adev->dm; |
| 853 | + | |
| 852 | 854 | if (dm->backlight_dev[0]) |
| 853 | 855 | atif->bd = dm->backlight_dev[0]; |
| 854 | 856 | #endif |
| @@ -863,6 +865,7 @@ int amdgpu_acpi_init(struct amdgpu_device *adev) · 8 unmodified lines | ||
| 863 | 865 | if ((enc->devices & (ATOM_DEVICE_LCD_SUPPORT)) && |
| 864 | 866 | enc->enc_priv) { |
| 865 | 867 | struct amdgpu_encoder_atom_dig *dig = enc->enc_priv; |
| 868 | + | |
| 866 | 869 | if (dig->bl_dev) { |
| 867 | 870 | atif->bd = dig->bl_dev; |
| 868 | 871 | break; |
| @@ -919,9 +922,9 @@ static bool amdgpu_atif_pci_probe_handle(struct pci_dev *pdev) · 50 unmodified lines | ||
| 919 | 922 | return false; |
| 920 | 923 | |
| 921 | 924 | status = acpi_get_handle(dhandle, "ATIF", &atif_handle); |
| 922 | − if (ACPI_FAILURE(status)) { | |
| 925 | + if (ACPI_FAILURE(status)) | |
| 923 | 926 | return false; |
| 924 | − } | |
| 927 | + | |
| 925 | 928 | amdgpu_acpi_priv.atif.handle = atif_handle; |
| 926 | 929 | acpi_get_name(amdgpu_acpi_priv.atif.handle, ACPI_FULL_PATHNAME, &buffer); |
| 927 | 930 | DRM_DEBUG_DRIVER("Found ATIF handle %s\n", acpi_method_name); |
| @@ -954,9 +957,9 @@ static bool amdgpu_atcs_pci_probe_handle(struct pci_dev *pdev) · 26 unmodified lines | ||
| 954 | 957 | return false; |
| 955 | 958 | |
| 956 | 959 | status = acpi_get_handle(dhandle, "ATCS", &atcs_handle); |
| 957 | − if (ACPI_FAILURE(status)) { | |
| 960 | + if (ACPI_FAILURE(status)) | |
| 958 | 961 | return false; |
| 959 | − } | |
| 962 | + | |
| 960 | 963 | amdgpu_acpi_priv.atcs.handle = atcs_handle; |
| 961 | 964 | acpi_get_name(amdgpu_acpi_priv.atcs.handle, ACPI_FULL_PATHNAME, &buffer); |
| 962 | 965 | DRM_DEBUG_DRIVER("Found ATCS handle %s\n", acpi_method_name); |
| @@ -1070,6 +1073,12 @@ bool amdgpu_acpi_is_s0ix_active(struct amdgpu_device *adev) · 107 unmodified lines | ||
| 1070 | 1073 | (pm_suspend_target_state != PM_SUSPEND_TO_IDLE)) |
| 1071 | 1074 | return false; |
| 1072 | 1075 | |
| 1076 | + /* | |
| 1077 | + * If ACPI_FADT_LOW_POWER_S0 is not set in the FADT, it is generally | |
| 1078 | + * risky to do any special firmware-related preparations for entering | |
| 1079 | + * S0ix even though the system is suspending to idle, so return false | |
| 1080 | + * in that case. | |
| 1081 | + */ | |
| 1073 | 1082 | if (!(acpi_gbl_FADT.flags & ACPI_FADT_LOW_POWER_S0)) { |
| 1074 | 1083 | dev_warn_once(adev->dev, |
| 1075 | 1084 | "Power consumption will be higher as BIOS has not been configured for suspend-to-idle.\n" |
| @@ -1,3 +1,4 @@ | ||
| 1 | +// SPDX-License-Identifier: MIT | |
| 1 | 2 | /* |
| 2 | 3 | * Copyright 2014 Advanced Micro Devices, Inc. |
| 3 | 4 | * |
| @@ -130,11 +131,13 @@ static void amdgpu_amdkfd_reset_work(struct work_struct *work) · 126 unmodified lines | ||
| 130 | 131 | kfd.reset_work); |
| 131 | 132 | |
| 132 | 133 | struct amdgpu_reset_context reset_context; |
| 134 | + | |
| 133 | 135 | memset(&reset_context, 0, sizeof(reset_context)); |
| 134 | 136 | |
| 135 | 137 | reset_context.method = AMD_RESET_METHOD_NONE; |
| 136 | 138 | reset_context.reset_req_dev = adev; |
| 137 | 139 | clear_bit(AMDGPU_NEED_FULL_RESET, &reset_context.flags); |
| 140 | + clear_bit(AMDGPU_SKIP_MODE2_RESET, &reset_context.flags); | |
| 138 | 141 | |
| 139 | 142 | amdgpu_device_gpu_recover(adev, NULL, &reset_context); |
| 140 | 143 | } |
| @@ -683,6 +686,7 @@ int amdgpu_amdkfd_submit_ib(struct amdgpu_device *adev, · 542 unmodified lines | ||
| 683 | 686 | ib->length_dw = ib_len; |
| 684 | 687 | /* This works for NO_HWS. TODO: need to handle without knowing VMID */ |
| 685 | 688 | job->vmid = vmid; |
| 689 | + job->num_ibs = 1; | |
| 686 | 690 | |
| 687 | 691 | ret = amdgpu_ib_schedule(ring, 1, ib, job, &f); |
| 688 | 692 | |
| @@ -752,11 +756,7 @@ void amdgpu_amdkfd_ras_poison_consumption_handler(struct amdgpu_device *adev, bo · 63 unmodified lines | ||
| 752 | 756 | { |
| 753 | 757 | struct ras_err_data err_data = {0, 0, 0, NULL}; |
| 754 | 758 | |
| 755 | − /* CPU MCA will handle page retirement if connected_to_cpu is 1 */ | |
| 756 | − if (!adev->gmc.xgmi.connected_to_cpu) | |
| 757 | − amdgpu_umc_poison_handler(adev, &err_data, reset); | |
| 758 | − else if (reset) | |
| 759 | − amdgpu_amdkfd_gpu_reset(adev); | |
| 759 | + amdgpu_umc_poison_handler(adev, &err_data, reset); | |
| 760 | 760 | } |
| 761 | 761 | |
| 762 | 762 | bool amdgpu_amdkfd_ras_query_utcl2_poison_status(struct amdgpu_device *adev) |
| @@ -1,3 +1,4 @@ | ||
| 1 | +// SPDX-License-Identifier: MIT | |
| 1 | 2 | /* |
| 2 | 3 | * Copyright 2014-2018 Advanced Micro Devices, Inc. |
| 3 | 4 | * |
| @@ -297,7 +298,7 @@ static int amdgpu_amdkfd_remove_eviction_fence(struct amdgpu_bo *bo, · 293 unmodified lines | ||
| 297 | 298 | */ |
| 298 | 299 | replacement = dma_fence_get_stub(); |
| 299 | 300 | dma_resv_replace_fences(bo->tbo.base.resv, ef->base.context, |
| 300 | − replacement, DMA_RESV_USAGE_READ); | |
| 301 | + replacement, DMA_RESV_USAGE_BOOKKEEP); | |
| 301 | 302 | dma_fence_put(replacement); |
| 302 | 303 | return 0; |
| 303 | 304 | } |
| @@ -1390,8 +1391,9 @@ static int init_kfd_vm(struct amdgpu_vm *vm, void **process_info, · 1086 unmodified lines | ||
| 1390 | 1391 | ret = dma_resv_reserve_fences(vm->root.bo->tbo.base.resv, 1); |
| 1391 | 1392 | if (ret) |
| 1392 | 1393 | goto reserve_shared_fail; |
| 1393 | − amdgpu_bo_fence(vm->root.bo, | |
| 1394 | − &vm->process_info->eviction_fence->base, true); | |
| 1394 | + dma_resv_add_fence(vm->root.bo->tbo.base.resv, | |
| 1395 | + &vm->process_info->eviction_fence->base, | |
| 1396 | + DMA_RESV_USAGE_BOOKKEEP); | |
| 1395 | 1397 | amdgpu_bo_unreserve(vm->root.bo); |
| 1396 | 1398 | |
| 1397 | 1399 | /* Update process info */ |
| @@ -1612,6 +1614,7 @@ size_t amdgpu_amdkfd_get_available_memory(struct amdgpu_device *adev) · 214 unmodified lines | ||
| 1612 | 1614 | uint64_t reserved_for_pt = |
| 1613 | 1615 | ESTIMATE_PT_SIZE(amdgpu_amdkfd_total_mem_size); |
| 1614 | 1616 | size_t available; |
| 1617 | + | |
| 1615 | 1618 | spin_lock(&kfd_mem_limit.mem_limit_lock); |
| 1616 | 1619 | available = adev->gmc.real_vram_size |
| 1617 | 1620 | - adev->kfd.vram_used_aligned |
| @@ -1987,9 +1990,9 @@ int amdgpu_amdkfd_gpuvm_map_memory_to_gpu( · 369 unmodified lines | ||
| 1987 | 1990 | } |
| 1988 | 1991 | |
| 1989 | 1992 | if (!amdgpu_ttm_tt_get_usermm(bo->tbo.ttm) && !bo->tbo.pin_count) |
| 1990 | − amdgpu_bo_fence(bo, | |
| 1991 | − &avm->process_info->eviction_fence->base, | |
| 1992 | − true); | |
| 1993 | + dma_resv_add_fence(bo->tbo.base.resv, | |
| 1994 | + &avm->process_info->eviction_fence->base, | |
| 1995 | + DMA_RESV_USAGE_BOOKKEEP); | |
| 1993 | 1996 | ret = unreserve_bo_and_vms(&ctx, false, false); |
| 1994 | 1997 | |
| 1995 | 1998 | goto out; |
| @@ -2216,7 +2219,7 @@ int amdgpu_amdkfd_gpuvm_get_vm_fault_info(struct amdgpu_device *adev, · 220 unmodified lines | ||
| 2216 | 2219 | { |
| 2217 | 2220 | if (atomic_read(&adev->gmc.vm_fault_info_updated) == 1) { |
| 2218 | 2221 | *mem = *adev->gmc.vm_fault_info; |
| 2219 | − mb(); | |
| 2222 | + mb(); /* make sure read happened */ | |
| 2220 | 2223 | atomic_set(&adev->gmc.vm_fault_info_updated, 0); |
| 2221 | 2224 | } |
| 2222 | 2225 | return 0; |
| @@ -2758,15 +2761,18 @@ int amdgpu_amdkfd_gpuvm_restore_process_bos(void *info, struct dma_fence **ef) · 535 unmodified lines | ||
| 2758 | 2761 | if (mem->bo->tbo.pin_count) |
| 2759 | 2762 | continue; |
| 2760 | 2763 | |
| 2761 | − amdgpu_bo_fence(mem->bo, | |
| 2762 | − &process_info->eviction_fence->base, true); | |
| 2764 | + dma_resv_add_fence(mem->bo->tbo.base.resv, | |
| 2765 | + &process_info->eviction_fence->base, | |
| 2766 | + DMA_RESV_USAGE_BOOKKEEP); | |
| 2763 | 2767 | } |
| 2764 | 2768 | /* Attach eviction fence to PD / PT BOs */ |
| 2765 | 2769 | list_for_each_entry(peer_vm, &process_info->vm_list_head, |
| 2766 | 2770 | vm_list_node) { |
| 2767 | 2771 | struct amdgpu_bo *bo = peer_vm->root.bo; |
| 2768 | 2772 | |
| 2769 | − amdgpu_bo_fence(bo, &process_info->eviction_fence->base, true); | |
| 2773 | + dma_resv_add_fence(bo->tbo.base.resv, | |
| 2774 | + &process_info->eviction_fence->base, | |
| 2775 | + DMA_RESV_USAGE_BOOKKEEP); | |
| 2770 | 2776 | } |
| 2771 | 2777 | |
| 2772 | 2778 | validate_map_fail: |
| @@ -2820,7 +2826,9 @@ int amdgpu_amdkfd_add_gws_to_process(void *info, void *gws, struct kgd_mem **mem · 47 unmodified lines | ||
| 2820 | 2826 | ret = dma_resv_reserve_fences(gws_bo->tbo.base.resv, 1); |
| 2821 | 2827 | if (ret) |
| 2822 | 2828 | goto reserve_shared_fail; |
| 2823 | − amdgpu_bo_fence(gws_bo, &process_info->eviction_fence->base, true); | |
| 2829 | + dma_resv_add_fence(gws_bo->tbo.base.resv, | |
| 2830 | + &process_info->eviction_fence->base, | |
| 2831 | + DMA_RESV_USAGE_BOOKKEEP); | |
| 2824 | 2832 | amdgpu_bo_unreserve(gws_bo); |
| 2825 | 2833 | mutex_unlock(&(*mem)->process_info->lock); |
| 2826 | 2834 | |
| @@ -1674,10 +1674,12 @@ amdgpu_connector_add(struct amdgpu_device *adev, · 1673 unmodified lines | ||
| 1674 | 1674 | adev->mode_info.dither_property, |
| 1675 | 1675 | AMDGPU_FMT_DITHER_DISABLE); |
| 1676 | 1676 | |
| 1677 | − if (amdgpu_audio != 0) | |
| 1677 | + if (amdgpu_audio != 0) { | |
| 1678 | 1678 | drm_object_attach_property(&amdgpu_connector->base.base, |
| 1679 | 1679 | adev->mode_info.audio_property, |
| 1680 | 1680 | AMDGPU_AUDIO_AUTO); |
| 1681 | + amdgpu_connector->audio = AMDGPU_AUDIO_AUTO; | |
| 1682 | + } | |
| 1681 | 1683 | |
| 1682 | 1684 | subpixel_order = SubPixelHorizontalRGB; |
| 1683 | 1685 | connector->interlace_allowed = true; |
| @@ -1799,6 +1801,7 @@ amdgpu_connector_add(struct amdgpu_device *adev, · 115 unmodified lines | ||
| 1799 | 1801 | drm_object_attach_property(&amdgpu_connector->base.base, |
| 1800 | 1802 | adev->mode_info.audio_property, |
| 1801 | 1803 | AMDGPU_AUDIO_AUTO); |
| 1804 | + amdgpu_connector->audio = AMDGPU_AUDIO_AUTO; | |
| 1802 | 1805 | } |
| 1803 | 1806 | drm_object_attach_property(&amdgpu_connector->base.base, |
| 1804 | 1807 | adev->mode_info.dither_property, |
| @@ -1852,6 +1855,7 @@ amdgpu_connector_add(struct amdgpu_device *adev, · 47 unmodified lines | ||
| 1852 | 1855 | drm_object_attach_property(&amdgpu_connector->base.base, |
| 1853 | 1856 | adev->mode_info.audio_property, |
| 1854 | 1857 | AMDGPU_AUDIO_AUTO); |
| 1858 | + amdgpu_connector->audio = AMDGPU_AUDIO_AUTO; | |
| 1855 | 1859 | } |
| 1856 | 1860 | drm_object_attach_property(&amdgpu_connector->base.base, |
| 1857 | 1861 | adev->mode_info.dither_property, |
| @@ -1902,6 +1906,7 @@ amdgpu_connector_add(struct amdgpu_device *adev, · 44 unmodified lines | ||
| 1902 | 1906 | drm_object_attach_property(&amdgpu_connector->base.base, |
| 1903 | 1907 | adev->mode_info.audio_property, |
| 1904 | 1908 | AMDGPU_AUDIO_AUTO); |
| 1909 | + amdgpu_connector->audio = AMDGPU_AUDIO_AUTO; | |
| 1905 | 1910 | } |
| 1906 | 1911 | drm_object_attach_property(&amdgpu_connector->base.base, |
| 1907 | 1912 | adev->mode_info.dither_property, |
| @@ -39,9 +39,82 @@ · 38 unmodified lines | ||
| 39 | 39 | #include "amdgpu_gem.h" |
| 40 | 40 | #include "amdgpu_ras.h" |
| 41 | 41 | |
| 42 | −static int amdgpu_cs_user_fence_chunk(struct amdgpu_cs_parser *p, | |
| 43 | − struct drm_amdgpu_cs_chunk_fence *data, | |
| 44 | − uint32_t *offset) | |
| 42 | +static int amdgpu_cs_parser_init(struct amdgpu_cs_parser *p, | |
| 43 | + struct amdgpu_device *adev, | |
| 44 | + struct drm_file *filp, | |
| 45 | + union drm_amdgpu_cs *cs) | |
| 46 | +{ | |
| 47 | + struct amdgpu_fpriv *fpriv = filp->driver_priv; | |
| 48 | + | |
| 49 | + if (cs->in.num_chunks == 0) | |
| 50 | + return -EINVAL; | |
| 51 | + | |
| 52 | + memset(p, 0, sizeof(*p)); | |
| 53 | + p->adev = adev; | |
| 54 | + p->filp = filp; | |
| 55 | + | |
| 56 | + p->ctx = amdgpu_ctx_get(fpriv, cs->in.ctx_id); | |
| 57 | + if (!p->ctx) | |
| 58 | + return -EINVAL; | |
| 59 | + | |
| 60 | + if (atomic_read(&p->ctx->guilty)) { | |
| 61 | + amdgpu_ctx_put(p->ctx); | |
| 62 | + return -ECANCELED; | |
| 63 | + } | |
| 64 | + return 0; | |
| 65 | +} | |
| 66 | + | |
| 67 | +static int amdgpu_cs_job_idx(struct amdgpu_cs_parser *p, | |
| 68 | + struct drm_amdgpu_cs_chunk_ib *chunk_ib) | |
| 69 | +{ | |
| 70 | + struct drm_sched_entity *entity; | |
| 71 | + unsigned int i; | |
| 72 | + int r; | |
| 73 | + | |
| 74 | + r = amdgpu_ctx_get_entity(p->ctx, chunk_ib->ip_type, | |
| 75 | + chunk_ib->ip_instance, | |
| 76 | + chunk_ib->ring, &entity); | |
| 77 | + if (r) | |
| 78 | + return r; | |
| 79 | + | |
| 80 | + /* | |
| 81 | + * Abort if there is no run queue associated with this entity. | |
| 82 | + * Possibly because of disabled HW IP. | |
| 83 | + */ | |
| 84 | + if (entity->rq == NULL) | |
| 85 | + return -EINVAL; | |
| 86 | + | |
| 87 | + /* Check if we can add this IB to some existing job */ | |
| 88 | + for (i = 0; i < p->gang_size; ++i) | |
| 89 | + if (p->entities[i] == entity) | |
| 90 | + return i; | |
| 91 | + | |
| 92 | + /* If not increase the gang size if possible */ | |
| 93 | + if (i == AMDGPU_CS_GANG_SIZE) | |
| 94 | + return -EINVAL; | |
| 95 | + | |
| 96 | + p->entities[i] = entity; | |
| 97 | + p->gang_size = i + 1; | |
| 98 | + return i; | |
| 99 | +} | |
| 100 | + | |
| 101 | +static int amdgpu_cs_p1_ib(struct amdgpu_cs_parser *p, | |
| 102 | + struct drm_amdgpu_cs_chunk_ib *chunk_ib, | |
| 103 | + unsigned int *num_ibs) | |
| 104 | +{ | |
| 105 | + int r; | |
| 106 | + | |
| 107 | + r = amdgpu_cs_job_idx(p, chunk_ib); | |
| 108 | + if (r < 0) | |
| 109 | + return r; | |
| 110 | + | |
| 111 | + ++(num_ibs[r]); | |
| 112 | + return 0; | |
| 113 | +} | |
| 114 | + | |
| 115 | +static int amdgpu_cs_p1_user_fence(struct amdgpu_cs_parser *p, | |
| 116 | + struct drm_amdgpu_cs_chunk_fence *data, | |
| 117 | + uint32_t *offset) | |
| 45 | 118 | { |
| 46 | 119 | struct drm_gem_object *gobj; |
| 47 | 120 | struct amdgpu_bo *bo; |
| @@ -80,11 +153,11 @@ error_unref: · 32 unmodified lines | ||
| 80 | 153 | return r; |
| 81 | 154 | } |
| 82 | 155 | |
| 83 | −static int amdgpu_cs_bo_handles_chunk(struct amdgpu_cs_parser *p, | |
| 84 | − struct drm_amdgpu_bo_list_in *data) | |
| 156 | +static int amdgpu_cs_p1_bo_handles(struct amdgpu_cs_parser *p, | |
| 157 | + struct drm_amdgpu_bo_list_in *data) | |
| 85 | 158 | { |
| 159 | + struct drm_amdgpu_bo_list_entry *info; | |
| 86 | 160 | int r; |
| 87 | − struct drm_amdgpu_bo_list_entry *info = NULL; | |
| 88 | 161 | |
| 89 | 162 | r = amdgpu_bo_create_list_entry_array(data, &info); |
| 90 | 163 | if (r) |
| @@ -104,38 +177,25 @@ error_free: · 13 unmodified lines | ||
| 104 | 177 | return r; |
| 105 | 178 | } |
| 106 | 179 | |
| 107 | −static int amdgpu_cs_parser_init(struct amdgpu_cs_parser *p, union drm_amdgpu_cs *cs) | |
| 180 | +/* Copy the data from userspace and go over it the first time */ | |
| 181 | +static int amdgpu_cs_pass1(struct amdgpu_cs_parser *p, | |
| 182 | + union drm_amdgpu_cs *cs) | |
| 108 | 183 | { |
| 109 | 184 | struct amdgpu_fpriv *fpriv = p->filp->driver_priv; |
| 185 | + unsigned int num_ibs[AMDGPU_CS_GANG_SIZE] = { }; | |
| 110 | 186 | struct amdgpu_vm *vm = &fpriv->vm; |
| 111 | 187 | uint64_t *chunk_array_user; |
| 112 | 188 | uint64_t *chunk_array; |
| 113 | − unsigned size, num_ibs = 0; | |
| 114 | 189 | uint32_t uf_offset = 0; |
| 115 | − int i; | |
| 190 | + unsigned int size; | |
| 116 | 191 | int ret; |
| 192 | + int i; | |
| 117 | 193 | |
| 118 | − if (cs->in.num_chunks == 0) | |
| 119 | − return -EINVAL; | |
| 120 | − | |
| 121 | − chunk_array = kvmalloc_array(cs->in.num_chunks, sizeof(uint64_t), GFP_KERNEL); | |
| 194 | + chunk_array = kvmalloc_array(cs->in.num_chunks, sizeof(uint64_t), | |
| 195 | + GFP_KERNEL); | |
| 122 | 196 | if (!chunk_array) |
| 123 | 197 | return -ENOMEM; |
| 124 | 198 | |
| 125 | − p->ctx = amdgpu_ctx_get(fpriv, cs->in.ctx_id); | |
| 126 | − if (!p->ctx) { | |
| 127 | − ret = -EINVAL; | |
| 128 | − goto free_chunk; | |
| 129 | − } | |
| 130 | − | |
| 131 | − mutex_lock(&p->ctx->lock); | |
| 132 | − | |
| 133 | − /* skip guilty context job */ | |
| 134 | − if (atomic_read(&p->ctx->guilty) == 1) { | |
| 135 | − ret = -ECANCELED; | |
| 136 | − goto free_chunk; | |
| 137 | − } | |
| 138 | − | |
| 139 | 199 | /* get chunks */ |
| 140 | 200 | chunk_array_user = u64_to_user_ptr(cs->in.chunks); |
| 141 | 201 | if (copy_from_user(chunk_array, chunk_array_user, |
| @@ -170,7 +230,8 @@ static int amdgpu_cs_parser_init(struct amdgpu_cs_parser *p, union drm_amdgpu_cs · 28 unmodified lines | ||
| 170 | 230 | size = p->chunks[i].length_dw; |
| 171 | 231 | cdata = u64_to_user_ptr(user_chunk.chunk_data); |
| 172 | 232 | |
| 173 | − p->chunks[i].kdata = kvmalloc_array(size, sizeof(uint32_t), GFP_KERNEL); | |
| 233 | + p->chunks[i].kdata = kvmalloc_array(size, sizeof(uint32_t), | |
| 234 | + GFP_KERNEL); | |
| 174 | 235 | if (p->chunks[i].kdata == NULL) { |
| 175 | 236 | ret = -ENOMEM; |
| 176 | 237 | i--; |
| @@ -182,36 +243,35 @@ static int amdgpu_cs_parser_init(struct amdgpu_cs_parser *p, union drm_amdgpu_cs · 5 unmodified lines | ||
| 182 | 243 | goto free_partial_kdata; |
| 183 | 244 | } |
| 184 | 245 | |
| 246 | + /* Assume the worst on the following checks */ | |
| 247 | + ret = -EINVAL; | |
| 185 | 248 | switch (p->chunks[i].chunk_id) { |
| 186 | 249 | case AMDGPU_CHUNK_ID_IB: |
| 187 | − ++num_ibs; | |
| 250 | + if (size < sizeof(struct drm_amdgpu_cs_chunk_ib)) | |
| 251 | + goto free_partial_kdata; | |
| 252 | + | |
| 253 | + ret = amdgpu_cs_p1_ib(p, p->chunks[i].kdata, num_ibs); | |
| 254 | + if (ret) | |
| 255 | + goto free_partial_kdata; | |
| 188 | 256 | break; |
| 189 | 257 | |
| 190 | 258 | case AMDGPU_CHUNK_ID_FENCE: |
| 191 | − size = sizeof(struct drm_amdgpu_cs_chunk_fence); | |
| 192 | − if (p->chunks[i].length_dw * sizeof(uint32_t) < size) { | |
| 193 | − ret = -EINVAL; | |
| 259 | + if (size < sizeof(struct drm_amdgpu_cs_chunk_fence)) | |
| 194 | 260 | goto free_partial_kdata; |
| 195 | − } | |
| 196 | 261 | |
| 197 | − ret = amdgpu_cs_user_fence_chunk(p, p->chunks[i].kdata, | |
| 198 | − &uf_offset); | |
| 262 | + ret = amdgpu_cs_p1_user_fence(p, p->chunks[i].kdata, | |
| 263 | + &uf_offset); | |
| 199 | 264 | if (ret) |
| 200 | 265 | goto free_partial_kdata; |
| 201 | − | |
| 202 | 266 | break; |
| 203 | 267 | |
| 204 | 268 | case AMDGPU_CHUNK_ID_BO_HANDLES: |
| 205 | − size = sizeof(struct drm_amdgpu_bo_list_in); | |
| 206 | − if (p->chunks[i].length_dw * sizeof(uint32_t) < size) { | |
| 207 | − ret = -EINVAL; | |
| 269 | + if (size < sizeof(struct drm_amdgpu_bo_list_in)) | |
| 208 | 270 | goto free_partial_kdata; |
| 209 | − } | |
| 210 | 271 | |
| 211 | − ret = amdgpu_cs_bo_handles_chunk(p, p->chunks[i].kdata); | |
| 272 | + ret = amdgpu_cs_p1_bo_handles(p, p->chunks[i].kdata); | |
| 212 | 273 | if (ret) |
| 213 | 274 | goto free_partial_kdata; |
| 214 | − | |
| 215 | 275 | break; |
| 216 | 276 | |
| 217 | 277 | case AMDGPU_CHUNK_ID_DEPENDENCIES: |
| @@ -223,22 +283,32 @@ static int amdgpu_cs_parser_init(struct amdgpu_cs_parser *p, union drm_amdgpu_cs · 5 unmodified lines | ||
| 223 | 283 | break; |
| 224 | 284 | |
| 225 | 285 | default: |
| 226 | − ret = -EINVAL; | |
| 227 | 286 | goto free_partial_kdata; |
| 228 | 287 | } |
| 229 | 288 | } |
| 230 | 289 | |
| 231 | − ret = amdgpu_job_alloc(p->adev, num_ibs, &p->job, vm); | |
| 232 | − if (ret) | |
| 233 | − goto free_all_kdata; | |
| 290 | + if (!p->gang_size) | |
| 291 | + return -EINVAL; | |
| 292 | + | |
| 293 | + for (i = 0; i < p->gang_size; ++i) { | |
| 294 | + ret = amdgpu_job_alloc(p->adev, num_ibs[i], &p->jobs[i], vm); | |
| 295 | + if (ret) | |
| 296 | + goto free_all_kdata; | |
| 297 | + | |
| 298 | + ret = drm_sched_job_init(&p->jobs[i]->base, p->entities[i], | |
| 299 | + &fpriv->vm); | |
| 300 | + if (ret) | |
| 301 | + goto free_all_kdata; | |
| 302 | + } | |
| 303 | + p->gang_leader = p->jobs[p->gang_size - 1]; | |
| 234 | 304 | |
| 235 | − if (p->ctx->vram_lost_counter != p->job->vram_lost_counter) { | |
| 305 | + if (p->ctx->vram_lost_counter != p->gang_leader->vram_lost_counter) { | |
| 236 | 306 | ret = -ECANCELED; |
| 237 | 307 | goto free_all_kdata; |
| 238 | 308 | } |
| 239 | 309 | |
| 240 | 310 | if (p->uf_entry.tv.bo) |
| 241 | − p->job->uf_addr = uf_offset; | |
| 311 | + p->gang_leader->uf_addr = uf_offset; | |
| 242 | 312 | kvfree(chunk_array); |
| 243 | 313 | |
| 244 | 314 | /* Use this opportunity to fill in task info for the vm */ |
| @@ -260,943 +330,880 @@ free_chunk: · 15 unmodified lines | ||
| 260 | 330 | return ret; |
| 261 | 331 | } |
| 262 | 332 | |
| 263 | −/* Convert microseconds to bytes. */ | |
| 264 | −static u64 us_to_bytes(struct amdgpu_device *adev, s64 us) | |
| 333 | +static int amdgpu_cs_p2_ib(struct amdgpu_cs_parser *p, | |
| 334 | + struct amdgpu_cs_chunk *chunk, | |
| 335 | + unsigned int *ce_preempt, | |
| 336 | + unsigned int *de_preempt) | |
| 265 | 337 | { |
| 266 | − if (us <= 0 || !adev->mm_stats.log2_max_MBps) | |
| 267 | − return 0; | |
| 338 | + struct drm_amdgpu_cs_chunk_ib *chunk_ib = chunk->kdata; | |
| 339 | + struct amdgpu_fpriv *fpriv = p->filp->driver_priv; | |
| 340 | + struct amdgpu_vm *vm = &fpriv->vm; | |
| 341 | + struct amdgpu_ring *ring; | |
| 342 | + struct amdgpu_job *job; | |
| 343 | + struct amdgpu_ib *ib; | |
| 344 | + int r; | |
| 268 | 345 | |
| 269 | − /* Since accum_us is incremented by a million per second, just | |
| 270 | − * multiply it by the number of MB/s to get the number of bytes. | |
| 271 | − */ | |
| 272 | − return us << adev->mm_stats.log2_max_MBps; | |
| 273 | −} | |
| 346 | + r = amdgpu_cs_job_idx(p, chunk_ib); | |
| 347 | + if (r < 0) | |
| 348 | + return r; | |
| 274 | 349 | |
| 275 | −static s64 bytes_to_us(struct amdgpu_device *adev, u64 bytes) | |
| 276 | −{ | |
| 277 | − if (!adev->mm_stats.log2_max_MBps) | |
| 278 | − return 0; | |
| 350 | + job = p->jobs[r]; | |
| 351 | + ring = amdgpu_job_ring(job); | |
| 352 | + ib = &job->ibs[job->num_ibs++]; | |
| 279 | 353 | |
| 280 | − return bytes >> adev->mm_stats.log2_max_MBps; | |
| 281 | −} | |
| 354 | + /* MM engine doesn't support user fences */ | |
| 355 | + if (p->uf_entry.tv.bo && ring->funcs->no_user_fence) | |
| 356 | + return -EINVAL; | |
| 282 | 357 | |
| 283 | −/* Returns how many bytes TTM can move right now. If no bytes can be moved, | |
| 284 | − * it returns 0. If it returns non-zero, it's OK to move at least one buffer, | |
| 285 | − * which means it can go over the threshold once. If that happens, the driver | |
| 286 | − * will be in debt and no other buffer migrations can be done until that debt | |
| 287 | − * is repaid. | |
| 288 | − * | |
| 289 | − * This approach allows moving a buffer of any size (it's important to allow | |
| 290 | − * that). | |
| 291 | − * | |
| 292 | − * The currency is simply time in microseconds and it increases as the clock | |
| 293 | − * ticks. The accumulated microseconds (us) are converted to bytes and | |
| 294 | − * returned. | |
| 295 | − */ | |
| 296 | −static void amdgpu_cs_get_threshold_for_moves(struct amdgpu_device *adev, | |
| 297 | − u64 *max_bytes, | |
| 298 | − u64 *max_vis_bytes) | |
| 299 | −{ | |
| 300 | − s64 time_us, increment_us; | |
| 301 | − u64 free_vram, total_vram, used_vram; | |
| 302 | − /* Allow a maximum of 200 accumulated ms. This is basically per-IB | |
| 303 | − * throttling. | |
| 304 | − * | |
| 305 | − * It means that in order to get full max MBps, at least 5 IBs per | |
| 306 | − * second must be submitted and not more than 200ms apart from each | |
| 307 | − * other. | |
| 308 | − */ | |
| 309 | − const s64 us_upper_bound = 200000; | |
| 358 | + if (chunk_ib->ip_type == AMDGPU_HW_IP_GFX && | |
| 359 | + chunk_ib->flags & AMDGPU_IB_FLAG_PREEMPT) { | |
| 360 | + if (chunk_ib->flags & AMDGPU_IB_FLAG_CE) | |
| 361 | + (*ce_preempt)++; | |
| 362 | + else | |
| 363 | + (*de_preempt)++; | |
| 310 | 364 | |
| 311 | − if (!adev->mm_stats.log2_max_MBps) { | |
| 312 | − *max_bytes = 0; | |
| 313 | − *max_vis_bytes = 0; | |
| 314 | − return; | |
| 365 | + /* Each GFX command submit allows only 1 IB max | |
| 366 | + * preemptible for CE & DE */ | |
| 367 | + if (*ce_preempt > 1 || *de_preempt > 1) | |
| 368 | + return -EINVAL; | |
| 315 | 369 | } |
| 316 | 370 | |
| 317 | − total_vram = adev->gmc.real_vram_size - atomic64_read(&adev->vram_pin_size); | |
| 318 | − used_vram = ttm_resource_manager_usage(&adev->mman.vram_mgr.manager); | |
| 319 | − free_vram = used_vram >= total_vram ? 0 : total_vram - used_vram; | |
| 371 | + if (chunk_ib->flags & AMDGPU_IB_FLAG_PREAMBLE) | |
| 372 | + job->preamble_status |= AMDGPU_PREAMBLE_IB_PRESENT; | |
| 320 | 373 | |
| 321 | − spin_lock(&adev->mm_stats.lock); | |
| 374 | + r = amdgpu_ib_get(p->adev, vm, ring->funcs->parse_cs ? | |
| 375 | + chunk_ib->ib_bytes : 0, | |
| 376 | + AMDGPU_IB_POOL_DELAYED, ib); | |
| 377 | + if (r) { | |
| 378 | + DRM_ERROR("Failed to get ib !\n"); | |
| 379 | + return r; | |
| 380 | + } | |
| 322 | 381 | |
| 323 | − /* Increase the amount of accumulated us. */ | |
| 324 | − time_us = ktime_to_us(ktime_get()); | |
| 325 | − increment_us = time_us - adev->mm_stats.last_update_us; | |
| 326 | − adev->mm_stats.last_update_us = time_us; | |
| 327 | − adev->mm_stats.accum_us = min(adev->mm_stats.accum_us + increment_us, | |
| 328 | − us_upper_bound); | |
| 382 | + ib->gpu_addr = chunk_ib->va_start; | |
| 383 | + ib->length_dw = chunk_ib->ib_bytes / 4; | |
| 384 | + ib->flags = chunk_ib->flags; | |
| 385 | + return 0; | |
| 386 | +} | |
| 329 | 387 | |
| 330 | − /* This prevents the short period of low performance when the VRAM | |
| 331 | − * usage is low and the driver is in debt or doesn't have enough | |
| 332 | − * accumulated us to fill VRAM quickly. | |
| 333 | − * | |
| 334 | − * The situation can occur in these cases: | |
| 335 | − * - a lot of VRAM is freed by userspace | |
| 336 | − * - the presence of a big buffer causes a lot of evictions | |
| 337 | − * (solution: split buffers into smaller ones) | |
| 338 | − * | |
| 339 | − * If 128 MB or 1/8th of VRAM is free, start filling it now by setting | |
| 340 | − * accum_us to a positive number. | |
| 341 | − */ | |
| 342 | − if (free_vram >= 128 * 1024 * 1024 || free_vram >= total_vram / 8) { | |
| 343 | − s64 min_us; | |
| 388 | +static int amdgpu_cs_p2_dependencies(struct amdgpu_cs_parser *p, | |
| 389 | + struct amdgpu_cs_chunk *chunk) | |
| 390 | +{ | |
| 391 | + struct drm_amdgpu_cs_chunk_dep *deps = chunk->kdata; | |
| 392 | + struct amdgpu_fpriv *fpriv = p->filp->driver_priv; | |
| 393 | + unsigned num_deps; | |
| 394 | + int i, r; | |
| 344 | 395 | |
| 345 | − /* Be more aggressive on dGPUs. Try to fill a portion of free | |
| 346 | − * VRAM now. | |
| 347 | − */ | |
| 348 | − if (!(adev->flags & AMD_IS_APU)) | |
| 349 | − min_us = bytes_to_us(adev, free_vram / 4); | |
| 350 | − else | |
| 351 | − min_us = 0; /* Reset accum_us on APUs. */ | |
| 396 | + num_deps = chunk->length_dw * 4 / | |
| 397 | + sizeof(struct drm_amdgpu_cs_chunk_dep); | |
| 352 | 398 | |
| 353 | − adev->mm_stats.accum_us = max(min_us, adev->mm_stats.accum_us); | |
| 354 | − } | |
| 399 | + for (i = 0; i < num_deps; ++i) { | |
| 400 | + struct amdgpu_ctx *ctx; | |
| 401 | + struct drm_sched_entity *entity; | |
| 402 | + struct dma_fence *fence; | |
| 355 | 403 | |
| 356 | − /* This is set to 0 if the driver is in debt to disallow (optional) | |
| 357 | − * buffer moves. | |
| 358 | − */ | |
| 359 | − *max_bytes = us_to_bytes(adev, adev->mm_stats.accum_us); | |
| 404 | + ctx = amdgpu_ctx_get(fpriv, deps[i].ctx_id); | |
| 405 | + if (ctx == NULL) | |
| 406 | + return -EINVAL; | |
| 360 | 407 | |
| 361 | − /* Do the same for visible VRAM if half of it is free */ | |
| 362 | − if (!amdgpu_gmc_vram_full_visible(&adev->gmc)) { | |
| 363 | − u64 total_vis_vram = adev->gmc.visible_vram_size; | |
| 364 | − u64 used_vis_vram = | |
| 365 | − amdgpu_vram_mgr_vis_usage(&adev->mman.vram_mgr); | |
| 408 | + r = amdgpu_ctx_get_entity(ctx, deps[i].ip_type, | |
| 409 | + deps[i].ip_instance, | |
| 410 | + deps[i].ring, &entity); | |
| 411 | + if (r) { | |
| 412 | + amdgpu_ctx_put(ctx); | |
| 413 | + return r; | |
| 414 | + } | |
| 366 | 415 | |
| 367 | − if (used_vis_vram < total_vis_vram) { | |
| 368 | − u64 free_vis_vram = total_vis_vram - used_vis_vram; | |
| 369 | − adev->mm_stats.accum_us_vis = min(adev->mm_stats.accum_us_vis + | |
| 370 | − increment_us, us_upper_bound); | |
| 416 | + fence = amdgpu_ctx_get_fence(ctx, entity, deps[i].handle); | |
| 417 | + amdgpu_ctx_put(ctx); | |
| 371 | 418 | |
| 372 | − if (free_vis_vram >= total_vis_vram / 2) | |
| 373 | − adev->mm_stats.accum_us_vis = | |
| 374 | − max(bytes_to_us(adev, free_vis_vram / 2), | |
| 375 | − adev->mm_stats.accum_us_vis); | |
| 376 | − } | |
| 419 | + if (IS_ERR(fence)) | |
| 420 | + return PTR_ERR(fence); | |
| 421 | + else if (!fence) | |
| 422 | + continue; | |
| 377 | 423 | |
| 378 | − *max_vis_bytes = us_to_bytes(adev, adev->mm_stats.accum_us_vis); | |
| 379 | − } else { | |
| 380 | − *max_vis_bytes = 0; | |
| 381 | − } | |
| 424 | + if (chunk->chunk_id == AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES) { | |
| 425 | + struct drm_sched_fence *s_fence; | |
| 426 | + struct dma_fence *old = fence; | |
| 382 | 427 | |
| 383 | − spin_unlock(&adev->mm_stats.lock); | |
| 384 | −} | |
| 428 | + s_fence = to_drm_sched_fence(fence); | |
| 429 | + fence = dma_fence_get(&s_fence->scheduled); | |
| 430 | + dma_fence_put(old); | |
| 431 | + } | |
| 385 | 432 | |
| 386 | −/* Report how many bytes have really been moved for the last command | |
| 387 | − * submission. This can result in a debt that can stop buffer migrations | |
| 388 | − * temporarily. | |
| 389 | − */ | |
| 390 | −void amdgpu_cs_report_moved_bytes(struct amdgpu_device *adev, u64 num_bytes, | |
| 391 | − u64 num_vis_bytes) | |
| 392 | −{ | |
| 393 | − spin_lock(&adev->mm_stats.lock); | |
| 394 | − adev->mm_stats.accum_us -= bytes_to_us(adev, num_bytes); | |
| 395 | − adev->mm_stats.accum_us_vis -= bytes_to_us(adev, num_vis_bytes); | |
| 396 | − spin_unlock(&adev->mm_stats.lock); | |
| 433 | + r = amdgpu_sync_fence(&p->gang_leader->sync, fence); | |
| 434 | + dma_fence_put(fence); | |
| 435 | + if (r) | |
| 436 | + return r; | |
| 437 | + } | |
| 438 | + return 0; | |
| 397 | 439 | } |
| 398 | 440 | |
| 399 | −static int amdgpu_cs_bo_validate(void *param, struct amdgpu_bo *bo) | |
| 441 | +static int amdgpu_syncobj_lookup_and_add(struct amdgpu_cs_parser *p, | |
| 442 | + uint32_t handle, u64 point, | |
| 443 | + u64 flags) | |
| 400 | 444 | { |
| 401 | − struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev); | |
| 402 | − struct amdgpu_cs_parser *p = param; | |
| 403 | − struct ttm_operation_ctx ctx = { | |
| 404 | − .interruptible = true, | |
| 405 | − .no_wait_gpu = false, | |
| 406 | − .resv = bo->tbo.base.resv | |
| 407 | − }; | |
| 408 | − uint32_t domain; | |
| 445 | + struct dma_fence *fence; | |
| 409 | 446 | int r; |
| 410 | 447 | |
| 411 | − if (bo->tbo.pin_count) | |
| 412 | − return 0; | |
| 448 | + r = drm_syncobj_find_fence(p->filp, handle, point, flags, &fence); | |
| 449 | + if (r) { | |
| 450 | + DRM_ERROR("syncobj %u failed to find fence @ %llu (%d)!\n", | |
| 451 | + handle, point, r); | |
| 452 | + return r; | |
| 453 | + } | |
| 413 | 454 | |
| 414 | − /* Don't move this buffer if we have depleted our allowance | |
| 415 | − * to move it. Don't move anything if the threshold is zero. | |
| 416 | − */ | |
| 417 | − if (p->bytes_moved < p->bytes_moved_threshold && | |
| 418 | − (!bo->tbo.base.dma_buf || | |
| 419 | − list_empty(&bo->tbo.base.dma_buf->attachments))) { | |
| 420 | − if (!amdgpu_gmc_vram_full_visible(&adev->gmc) && | |
| 421 | − (bo->flags & AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED)) { | |
| 422 | − /* And don't move a CPU_ACCESS_REQUIRED BO to limited | |
| 423 | − * visible VRAM if we've depleted our allowance to do | |
| 424 | − * that. | |
| 425 | − */ | |
| 426 | − if (p->bytes_moved_vis < p->bytes_moved_vis_threshold) | |
| 427 | − domain = bo->preferred_domains; | |
| 428 | − else | |
| 429 | − domain = bo->allowed_domains; | |
| 430 | − } else { | |
| 431 | − domain = bo->preferred_domains; | |
| 432 | − } | |
| 433 | − } else { | |
| 434 | − domain = bo->allowed_domains; | |
| 435 | − } | |
| 436 | − | |
| 437 | −retry: | |
| 438 | − amdgpu_bo_placement_from_domain(bo, domain); | |
| 439 | − r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx); | |
| 440 | − | |
| 441 | − p->bytes_moved += ctx.bytes_moved; | |
| 442 | − if (!amdgpu_gmc_vram_full_visible(&adev->gmc) && | |
| 443 | − amdgpu_bo_in_cpu_visible_vram(bo)) | |
| 444 | − p->bytes_moved_vis += ctx.bytes_moved; | |
| 445 | − | |
| 446 | − if (unlikely(r == -ENOMEM) && domain != bo->allowed_domains) { | |
| 447 | − domain = bo->allowed_domains; | |
| 448 | − goto retry; | |
| 449 | − } | |
| 455 | + r = amdgpu_sync_fence(&p->gang_leader->sync, fence); | |
| 456 | + dma_fence_put(fence); | |
| 450 | 457 | |
| 451 | 458 | return r; |
| 452 | 459 | } |
| 453 | 460 | |
| 454 | −static int amdgpu_cs_list_validate(struct amdgpu_cs_parser *p, | |
| 455 | − struct list_head *validated) | |
| 461 | +static int amdgpu_cs_p2_syncobj_in(struct amdgpu_cs_parser *p, | |
| 462 | + struct amdgpu_cs_chunk *chunk) | |
| 456 | 463 | { |
| 457 | − struct ttm_operation_ctx ctx = { true, false }; | |
| 458 | − struct amdgpu_bo_list_entry *lobj; | |
| 459 | − int r; | |
| 460 | − | |
| 461 | − list_for_each_entry(lobj, validated, tv.head) { | |
| 462 | − struct amdgpu_bo *bo = ttm_to_amdgpu_bo(lobj->tv.bo); | |
| 463 | − struct mm_struct *usermm; | |
| 464 | − | |
| 465 | − usermm = amdgpu_ttm_tt_get_usermm(bo->tbo.ttm); | |
| 466 | − if (usermm && usermm != current->mm) | |
| 467 | − return -EPERM; | |
| 468 | − | |
| 469 | − if (amdgpu_ttm_tt_is_userptr(bo->tbo.ttm) && | |
| 470 | − lobj->user_invalidated && lobj->user_pages) { | |
| 471 | − amdgpu_bo_placement_from_domain(bo, | |
| 472 | − AMDGPU_GEM_DOMAIN_CPU); | |
| 473 | − r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx); | |
| 474 | − if (r) | |
| 475 | − return r; | |
| 476 | − | |
| 477 | − amdgpu_ttm_tt_set_user_pages(bo->tbo.ttm, | |
| 478 | − lobj->user_pages); | |
| 479 | − } | |
| 464 | + struct drm_amdgpu_cs_chunk_sem *deps = chunk->kdata; | |
| 465 | + unsigned num_deps; | |
| 466 | + int i, r; | |
| 480 | 467 | |
| 481 | − r = amdgpu_cs_bo_validate(p, bo); | |
| 468 | + num_deps = chunk->length_dw * 4 / | |
| 469 | + sizeof(struct drm_amdgpu_cs_chunk_sem); | |
| 470 | + for (i = 0; i < num_deps; ++i) { | |
| 471 | + r = amdgpu_syncobj_lookup_and_add(p, deps[i].handle, 0, 0); | |
| 482 | 472 | if (r) |
| 483 | 473 | return r; |
| 484 | − | |
| 485 | − kvfree(lobj->user_pages); | |
| 486 | − lobj->user_pages = NULL; | |
| 487 | 474 | } |
| 475 | + | |
| 488 | 476 | return 0; |
| 489 | 477 | } |
| 490 | 478 | |
| 491 | −static int amdgpu_cs_parser_bos(struct amdgpu_cs_parser *p, | |
| 492 | − union drm_amdgpu_cs *cs) | |
| 479 | +static int amdgpu_cs_p2_syncobj_timeline_wait(struct amdgpu_cs_parser *p, | |
| 480 | + struct amdgpu_cs_chunk *chunk) | |
| 493 | 481 | { |
| 494 | − struct amdgpu_fpriv *fpriv = p->filp->driver_priv; | |
| 495 | − struct amdgpu_vm *vm = &fpriv->vm; | |
| 496 | − struct amdgpu_bo_list_entry *e; | |
| 497 | − struct list_head duplicates; | |
| 498 | − struct amdgpu_bo *gds; | |
| 499 | − struct amdgpu_bo *gws; | |
| 500 | − struct amdgpu_bo *oa; | |
| 501 | − int r; | |
| 502 | − | |
| 503 | − INIT_LIST_HEAD(&p->validated); | |
| 504 | − | |
| 505 | − /* p->bo_list could already be assigned if AMDGPU_CHUNK_ID_BO_HANDLES is present */ | |
| 506 | − if (cs->in.bo_list_handle) { | |
| 507 | − if (p->bo_list) | |
| 508 | − return -EINVAL; | |
| 482 | + struct drm_amdgpu_cs_chunk_syncobj *syncobj_deps = chunk->kdata; | |
| 483 | + unsigned num_deps; | |
| 484 | + int i, r; | |
| 509 | 485 | |
| 510 | − r = amdgpu_bo_list_get(fpriv, cs->in.bo_list_handle, | |
| 511 | − &p->bo_list); | |
| 512 | − if (r) | |
| 513 | − return r; | |
| 514 | − } else if (!p->bo_list) { | |
| 515 | − /* Create a empty bo_list when no handle is provided */ | |
| 516 | − r = amdgpu_bo_list_create(p->adev, p->filp, NULL, 0, | |
| 517 | − &p->bo_list); | |
| 486 | + num_deps = chunk->length_dw * 4 / | |
| 487 | + sizeof(struct drm_amdgpu_cs_chunk_syncobj); | |
| 488 | + for (i = 0; i < num_deps; ++i) { | |
| 489 | + r = amdgpu_syncobj_lookup_and_add(p, syncobj_deps[i].handle, | |
| 490 | + syncobj_deps[i].point, | |
| 491 | + syncobj_deps[i].flags); | |
| 518 | 492 | if (r) |
| 519 | 493 | return r; |
| 520 | 494 | } |
| 521 | 495 | |
| 522 | − mutex_lock(&p->bo_list->bo_list_mutex); | |
| 523 | − | |
| 524 | − /* One for TTM and one for the CS job */ | |
| 525 | − amdgpu_bo_list_for_each_entry(e, p->bo_list) | |
| 526 | − e->tv.num_shared = 2; | |
| 527 | − | |
| 528 | − amdgpu_bo_list_get_list(p->bo_list, &p->validated); | |
| 496 | + return 0; | |
| 497 | +} | |
| 529 | 498 | |
| 530 | − INIT_LIST_HEAD(&duplicates); | |
| 531 | − amdgpu_vm_get_pd_bo(&fpriv->vm, &p->validated, &p->vm_pd); | |
| 499 | +static int amdgpu_cs_p2_syncobj_out(struct amdgpu_cs_parser *p, | |
| 500 | + struct amdgpu_cs_chunk *chunk) | |
| 501 | +{ | |
| 502 | + struct drm_amdgpu_cs_chunk_sem *deps = chunk->kdata; | |
| 503 | + unsigned num_deps; | |
| 504 | + int i; | |
| 532 | 505 | |
| 533 | − if (p->uf_entry.tv.bo && !ttm_to_amdgpu_bo(p->uf_entry.tv.bo)->parent) | |
| 534 | − list_add(&p->uf_entry.tv.head, &p->validated); | |
| 506 | + num_deps = chunk->length_dw * 4 / | |
| 507 | + sizeof(struct drm_amdgpu_cs_chunk_sem); | |
| 535 | 508 | |
| 536 | − /* Get userptr backing pages. If pages are updated after registered | |
| 537 | − * in amdgpu_gem_userptr_ioctl(), amdgpu_cs_list_validate() will do | |
| 538 | − * amdgpu_ttm_backend_bind() to flush and invalidate new pages | |
| 539 | − */ | |
| 540 | − amdgpu_bo_list_for_each_userptr_entry(e, p->bo_list) { | |
| 541 | − struct amdgpu_bo *bo = ttm_to_amdgpu_bo(e->tv.bo); | |
| 542 | − bool userpage_invalidated = false; | |
| 543 | − int i; | |
| 509 | + if (p->post_deps) | |
| 510 | + return -EINVAL; | |
| 544 | 511 | |
| 545 | − e->user_pages = kvmalloc_array(bo->tbo.ttm->num_pages, | |
| 546 | − sizeof(struct page *), | |
| 547 | − GFP_KERNEL | __GFP_ZERO); | |
| 548 | − if (!e->user_pages) { | |
| 549 | − DRM_ERROR("kvmalloc_array failure\n"); | |
| 550 | − r = -ENOMEM; | |
| 551 | − goto out_free_user_pages; | |
| 552 | − } | |
| 512 | + p->post_deps = kmalloc_array(num_deps, sizeof(*p->post_deps), | |
| 513 | + GFP_KERNEL); | |
| 514 | + p->num_post_deps = 0; | |
| 553 | 515 | |
| 554 | − r = amdgpu_ttm_tt_get_user_pages(bo, e->user_pages); | |
| 555 | − if (r) { | |
| 556 | − kvfree(e->user_pages); | |
| 557 | − e->user_pages = NULL; | |
| 558 | − goto out_free_user_pages; | |
| 559 | − } | |
| 516 | + if (!p->post_deps) | |
| 517 | + return -ENOMEM; | |
| 560 | 518 | |
| 561 | − for (i = 0; i < bo->tbo.ttm->num_pages; i++) { | |
| 562 | − if (bo->tbo.ttm->pages[i] != e->user_pages[i]) { | |
| 563 | − userpage_invalidated = true; | |
| 564 | − break; | |
| 565 | − } | |
| 566 | − } | |
| 567 | − e->user_invalidated = userpage_invalidated; | |
| 568 | − } | |
| 569 | 519 | |
| 570 | − r = ttm_eu_reserve_buffers(&p->ticket, &p->validated, true, | |
| 571 | − &duplicates); | |
| 572 | − if (unlikely(r != 0)) { | |
| 573 | − if (r != -ERESTARTSYS) | |
| 574 | − DRM_ERROR("ttm_eu_reserve_buffers failed.\n"); | |
| 575 | − goto out_free_user_pages; | |
| 520 | + for (i = 0; i < num_deps; ++i) { | |
| 521 | + p->post_deps[i].syncobj = | |
| 522 | + drm_syncobj_find(p->filp, deps[i].handle); | |
| 523 | + if (!p->post_deps[i].syncobj) | |
| 524 | + return -EINVAL; | |
| 525 | + p->post_deps[i].chain = NULL; | |
| 526 | + p->post_deps[i].point = 0; | |
| 527 | + p->num_post_deps++; | |
| 576 | 528 | } |
| 577 | 529 | |
| 578 | − amdgpu_bo_list_for_each_entry(e, p->bo_list) { | |
| 579 | − struct amdgpu_bo *bo = ttm_to_amdgpu_bo(e->tv.bo); | |
| 580 | − | |
| 581 | − e->bo_va = amdgpu_vm_bo_find(vm, bo); | |
| 582 | − } | |
| 530 | + return 0; | |
| 531 | +} | |
| 583 | 532 | |
| 584 | − /* Move fence waiting after getting reservation lock of | |
| 585 | − * PD root. Then there is no need on a ctx mutex lock. | |
| 586 | − */ | |
| 587 | − r = amdgpu_ctx_wait_prev_fence(p->ctx, p->entity); | |
| 588 | − if (unlikely(r != 0)) { | |
| 589 | − if (r != -ERESTARTSYS) | |
| 590 | − DRM_ERROR("amdgpu_ctx_wait_prev_fence failed.\n"); | |
| 591 | − goto error_validate; | |
| 592 | − } | |
| 533 | +static int amdgpu_cs_p2_syncobj_timeline_signal(struct amdgpu_cs_parser *p, | |
| 534 | + struct amdgpu_cs_chunk *chunk) | |
| 535 | +{ | |
| 536 | + struct drm_amdgpu_cs_chunk_syncobj *syncobj_deps = chunk->kdata; | |
| 537 | + unsigned num_deps; | |
| 538 | + int i; | |
| 593 | 539 | |
| 594 | − amdgpu_cs_get_threshold_for_moves(p->adev, &p->bytes_moved_threshold, | |
| 595 | − &p->bytes_moved_vis_threshold); | |
| 596 | − p->bytes_moved = 0; | |
| 597 | − p->bytes_moved_vis = 0; | |
| 540 | + num_deps = chunk->length_dw * 4 / | |
| 541 | + sizeof(struct drm_amdgpu_cs_chunk_syncobj); | |
| 598 | 542 | |
| 599 | − r = amdgpu_vm_validate_pt_bos(p->adev, &fpriv->vm, | |
| 600 | − amdgpu_cs_bo_validate, p); | |
| 601 | − if (r) { | |
| 602 | − DRM_ERROR("amdgpu_vm_validate_pt_bos() failed.\n"); | |
| 603 | − goto error_validate; | |
| 604 | − } | |
| 543 | + if (p->post_deps) | |
| 544 | + return -EINVAL; | |
| 605 | 545 | |
| 606 | − r = amdgpu_cs_list_validate(p, &duplicates); | |
| 607 | − if (r) | |
| 608 | − goto error_validate; | |
| 546 | + p->post_deps = kmalloc_array(num_deps, sizeof(*p->post_deps), | |
| 547 | + GFP_KERNEL); | |
| 548 | + p->num_post_deps = 0; | |
| 609 | 549 | |
| 610 | − r = amdgpu_cs_list_validate(p, &p->validated); | |
| 611 | − if (r) | |
| 612 | − goto error_validate; | |
| 550 | + if (!p->post_deps) | |
| 551 | + return -ENOMEM; | |
| 613 | 552 | |
| 614 | − amdgpu_cs_report_moved_bytes(p->adev, p->bytes_moved, | |
| 615 | − p->bytes_moved_vis); | |
| 553 | + for (i = 0; i < num_deps; ++i) { | |
| 554 | + struct amdgpu_cs_post_dep *dep = &p->post_deps[i]; | |
| 616 | 555 | |
| 617 | − gds = p->bo_list->gds_obj; | |
| 618 | − gws = p->bo_list->gws_obj; | |
| 619 | − oa = p->bo_list->oa_obj; | |
| 556 | + dep->chain = NULL; | |
| 557 | + if (syncobj_deps[i].point) { | |
| 558 | + dep->chain = dma_fence_chain_alloc(); | |
| 559 | + if (!dep->chain) | |
| 560 | + return -ENOMEM; | |
| 561 | + } | |
| 620 | 562 | |
| 621 | − if (gds) { | |
| 622 | − p->job->gds_base = amdgpu_bo_gpu_offset(gds) >> PAGE_SHIFT; | |
| 623 | − p->job->gds_size = amdgpu_bo_size(gds) >> PAGE_SHIFT; | |
| 624 | − } | |
| 625 | − if (gws) { | |
| 626 | − p->job->gws_base = amdgpu_bo_gpu_offset(gws) >> PAGE_SHIFT; | |
| 627 | − p->job->gws_size = amdgpu_bo_size(gws) >> PAGE_SHIFT; | |
| 628 | − } | |
| 629 | − if (oa) { | |
| 630 | − p->job->oa_base = amdgpu_bo_gpu_offset(oa) >> PAGE_SHIFT; | |
| 631 | − p->job->oa_size = amdgpu_bo_size(oa) >> PAGE_SHIFT; | |
| 563 | + dep->syncobj = drm_syncobj_find(p->filp, | |
| 564 | + syncobj_deps[i].handle); | |
| 565 | + if (!dep->syncobj) { | |
| 566 | + dma_fence_chain_free(dep->chain); | |
| 567 | + return -EINVAL; | |
| 568 | + } | |
| 569 | + dep->point = syncobj_deps[i].point; | |
| 570 | + p->num_post_deps++; | |
| 632 | 571 | } |
| 633 | 572 | |
| 634 | − if (!r && p->uf_entry.tv.bo) { | |
| 635 | − struct amdgpu_bo *uf = ttm_to_amdgpu_bo(p->uf_entry.tv.bo); | |
| 573 | + return 0; | |
| 574 | +} | |
| 636 | 575 | |
| 637 | − r = amdgpu_ttm_alloc_gart(&uf->tbo); | |
| 638 | − p->job->uf_addr += amdgpu_bo_gpu_offset(uf); | |
| 639 | − } | |
| 576 | +static int amdgpu_cs_pass2(struct amdgpu_cs_parser *p) | |
| 577 | +{ | |
| 578 | + unsigned int ce_preempt = 0, de_preempt = 0; | |
| 579 | + int i, r; | |
| 640 | 580 | |
| 641 | −error_validate: | |
| 642 | − if (r) | |
| 643 | − ttm_eu_backoff_reservation(&p->ticket, &p->validated); | |
| 581 | + for (i = 0; i < p->nchunks; ++i) { | |
| 582 | + struct amdgpu_cs_chunk *chunk; | |
| 644 | 583 | |
| 645 | −out_free_user_pages: | |
| 646 | − if (r) { | |
| 647 | − amdgpu_bo_list_for_each_userptr_entry(e, p->bo_list) { | |
| 648 | − struct amdgpu_bo *bo = ttm_to_amdgpu_bo(e->tv.bo); | |
| 584 | + chunk = &p->chunks[i]; | |
| 649 | 585 | |
| 650 | − if (!e->user_pages) | |
| 651 | − continue; | |
| 652 | − amdgpu_ttm_tt_get_user_pages_done(bo->tbo.ttm); | |
| 653 | − kvfree(e->user_pages); | |
| 654 | − e->user_pages = NULL; | |
| 586 | + switch (chunk->chunk_id) { | |
| 587 | + case AMDGPU_CHUNK_ID_IB: | |
| 588 | + r = amdgpu_cs_p2_ib(p, chunk, &ce_preempt, &de_preempt); | |
| 589 | + if (r) | |
| 590 | + return r; | |
| 591 | + break; | |
| 592 | + case AMDGPU_CHUNK_ID_DEPENDENCIES: | |
| 593 | + case AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES: | |
| 594 | + r = amdgpu_cs_p2_dependencies(p, chunk); | |
| 595 | + if (r) | |
| 596 | + return r; | |
| 597 | + break; | |
| 598 | + case AMDGPU_CHUNK_ID_SYNCOBJ_IN: | |
| 599 | + r = amdgpu_cs_p2_syncobj_in(p, chunk); | |
| 600 | + if (r) | |
| 601 | + return r; | |
| 602 | + break; | |
| 603 | + case AMDGPU_CHUNK_ID_SYNCOBJ_OUT: | |
| 604 | + r = amdgpu_cs_p2_syncobj_out(p, chunk); | |
| 605 | + if (r) | |
| 606 | + return r; | |
| 607 | + break; | |
| 608 | + case AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_WAIT: | |
| 609 | + r = amdgpu_cs_p2_syncobj_timeline_wait(p, chunk); | |
| 610 | + if (r) | |
| 611 | + return r; | |
| 612 | + break; | |
| 613 | + case AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_SIGNAL: | |
| 614 | + r = amdgpu_cs_p2_syncobj_timeline_signal(p, chunk); | |
| 615 | + if (r) | |
| 616 | + return r; | |
| 617 | + break; | |
| 655 | 618 | } |
| 656 | − mutex_unlock(&p->bo_list->bo_list_mutex); | |
| 657 | 619 | } |
| 658 | − return r; | |
| 620 | + | |
| 621 | + return 0; | |
| 659 | 622 | } |
| 660 | 623 | |
| 661 | −static int amdgpu_cs_sync_rings(struct amdgpu_cs_parser *p) | |
| 624 | +/* Convert microseconds to bytes. */ | |
| 625 | +static u64 us_to_bytes(struct amdgpu_device *adev, s64 us) | |
| 662 | 626 | { |
| 663 | − struct amdgpu_fpriv *fpriv = p->filp->driver_priv; | |
| 664 | − struct amdgpu_bo_list_entry *e; | |
| 665 | − int r; | |
| 627 | + if (us <= 0 || !adev->mm_stats.log2_max_MBps) | |
| 628 | + return 0; | |
| 666 | 629 | |
| 667 | − list_for_each_entry(e, &p->validated, tv.head) { | |
| 668 | − struct amdgpu_bo *bo = ttm_to_amdgpu_bo(e->tv.bo); | |
| 669 | − struct dma_resv *resv = bo->tbo.base.resv; | |
| 670 | − enum amdgpu_sync_mode sync_mode; | |
| 630 | + /* Since accum_us is incremented by a million per second, just | |
| 631 | + * multiply it by the number of MB/s to get the number of bytes. | |
| 632 | + */ | |
| 633 | + return us << adev->mm_stats.log2_max_MBps; | |
| 634 | +} | |
| 671 | 635 | |
| 672 | − sync_mode = amdgpu_bo_explicit_sync(bo) ? | |
| 673 | − AMDGPU_SYNC_EXPLICIT : AMDGPU_SYNC_NE_OWNER; | |
| 674 | − r = amdgpu_sync_resv(p->adev, &p->job->sync, resv, sync_mode, | |
| 675 | − &fpriv->vm); | |
| 676 | − if (r) | |
| 677 | − return r; | |
| 678 | − } | |
| 679 | − return 0; | |
| 636 | +static s64 bytes_to_us(struct amdgpu_device *adev, u64 bytes) | |
| 637 | +{ | |
| 638 | + if (!adev->mm_stats.log2_max_MBps) | |
| 639 | + return 0; | |
| 640 | + | |
| 641 | + return bytes >> adev->mm_stats.log2_max_MBps; | |
| 680 | 642 | } |
| 681 | 643 | |
| 682 | −/** | |
| 683 | − * amdgpu_cs_parser_fini() - clean parser states | |
| 684 | − * @parser: parser structure holding parsing context. | |
| 685 | − * @error: error number | |
| 686 | − * @backoff: indicator to backoff the reservation | |
| 644 | +/* Returns how many bytes TTM can move right now. If no bytes can be moved, | |
| 645 | + * it returns 0. If it returns non-zero, it's OK to move at least one buffer, | |
| 646 | + * which means it can go over the threshold once. If that happens, the driver | |
| 647 | + * will be in debt and no other buffer migrations can be done until that debt | |
| 648 | + * is repaid. | |
| 649 | + * | |
| 650 | + * This approach allows moving a buffer of any size (it's important to allow | |
| 651 | + * that). | |
| 687 | 652 | * |
| 688 | − * If error is set then unvalidate buffer, otherwise just free memory | |
| 689 | − * used by parsing context. | |
| 690 | − **/ | |
| 691 | −static void amdgpu_cs_parser_fini(struct amdgpu_cs_parser *parser, int error, | |
| 692 | − bool backoff) | |
| 653 | + * The currency is simply time in microseconds and it increases as the clock | |
| 654 | + * ticks. The accumulated microseconds (us) are converted to bytes and | |
| 655 | + * returned. | |
| 656 | + */ | |
| 657 | +static void amdgpu_cs_get_threshold_for_moves(struct amdgpu_device *adev, | |
| 658 | + u64 *max_bytes, | |
| 659 | + u64 *max_vis_bytes) | |
| 693 | 660 | { |
| 694 | − unsigned i; | |
| 661 | + s64 time_us, increment_us; | |
| 662 | + u64 free_vram, total_vram, used_vram; | |
| 663 | + /* Allow a maximum of 200 accumulated ms. This is basically per-IB | |
| 664 | + * throttling. | |
| 665 | + * | |
| 666 | + * It means that in order to get full max MBps, at least 5 IBs per | |
| 667 | + * second must be submitted and not more than 200ms apart from each | |
| 668 | + * other. | |
| 669 | + */ | |
| 670 | + const s64 us_upper_bound = 200000; | |
| 695 | 671 | |
| 696 | − if (error && backoff) { | |
| 697 | − ttm_eu_backoff_reservation(&parser->ticket, | |
| 698 | − &parser->validated); | |
| 699 | − mutex_unlock(&parser->bo_list->bo_list_mutex); | |
| 672 | + if (!adev->mm_stats.log2_max_MBps) { | |
| 673 | + *max_bytes = 0; | |
| 674 | + *max_vis_bytes = 0; | |
| 675 | + return; | |
| 700 | 676 | } |
| 701 | 677 | |
| 702 | − for (i = 0; i < parser->num_post_deps; i++) { | |
| 703 | − drm_syncobj_put(parser->post_deps[i].syncobj); | |
| 704 | − kfree(parser->post_deps[i].chain); | |
| 705 | − } | |
| 706 | − kfree(parser->post_deps); | |
| 678 | + total_vram = adev->gmc.real_vram_size - atomic64_read(&adev->vram_pin_size); | |
| 679 | + used_vram = ttm_resource_manager_usage(&adev->mman.vram_mgr.manager); | |
| 680 | + free_vram = used_vram >= total_vram ? 0 : total_vram - used_vram; | |
| 707 | 681 | |
| 708 | − dma_fence_put(parser->fence); | |
| 682 | + spin_lock(&adev->mm_stats.lock); | |
| 709 | 683 | |
| 710 | − if (parser->ctx) { | |
| 711 | − mutex_unlock(&parser->ctx->lock); | |
| 712 | − amdgpu_ctx_put(parser->ctx); | |
| 684 | + /* Increase the amount of accumulated us. */ | |
| 685 | + time_us = ktime_to_us(ktime_get()); | |
| 686 | + increment_us = time_us - adev->mm_stats.last_update_us; | |
| 687 | + adev->mm_stats.last_update_us = time_us; | |
| 688 | + adev->mm_stats.accum_us = min(adev->mm_stats.accum_us + increment_us, | |
| 689 | + us_upper_bound); | |
| 690 | + | |
| 691 | + /* This prevents the short period of low performance when the VRAM | |
| 692 | + * usage is low and the driver is in debt or doesn't have enough | |
| 693 | + * accumulated us to fill VRAM quickly. | |
| 694 | + * | |
| 695 | + * The situation can occur in these cases: | |
| 696 | + * - a lot of VRAM is freed by userspace | |
| 697 | + * - the presence of a big buffer causes a lot of evictions | |
| 698 | + * (solution: split buffers into smaller ones) | |
| 699 | + * | |
| 700 | + * If 128 MB or 1/8th of VRAM is free, start filling it now by setting | |
| 701 | + * accum_us to a positive number. | |
| 702 | + */ | |
| 703 | + if (free_vram >= 128 * 1024 * 1024 || free_vram >= total_vram / 8) { | |
| 704 | + s64 min_us; | |
| 705 | + | |
| 706 | + /* Be more aggressive on dGPUs. Try to fill a portion of free | |
| 707 | + * VRAM now. | |
| 708 | + */ | |
| 709 | + if (!(adev->flags & AMD_IS_APU)) | |
| 710 | + min_us = bytes_to_us(adev, free_vram / 4); | |
| 711 | + else | |
| 712 | + min_us = 0; /* Reset accum_us on APUs. */ | |
| 713 | + | |
| 714 | + adev->mm_stats.accum_us = max(min_us, adev->mm_stats.accum_us); | |
| 713 | 715 | } |
| 714 | − if (parser->bo_list) | |
| 715 | − amdgpu_bo_list_put(parser->bo_list); | |
| 716 | 716 | |
| 717 | − for (i = 0; i < parser->nchunks; i++) | |
| 718 | − kvfree(parser->chunks[i].kdata); | |
| 719 | − kvfree(parser->chunks); | |
| 720 | − if (parser->job) | |
| 721 | − amdgpu_job_free(parser->job); | |
| 722 | − if (parser->uf_entry.tv.bo) { | |
| 723 | − struct amdgpu_bo *uf = ttm_to_amdgpu_bo(parser->uf_entry.tv.bo); | |
| 717 | + /* This is set to 0 if the driver is in debt to disallow (optional) | |
| 718 | + * buffer moves. | |
| 719 | + */ | |
| 720 | + *max_bytes = us_to_bytes(adev, adev->mm_stats.accum_us); | |
| 724 | 721 | |
| 725 | − amdgpu_bo_unref(&uf); | |
| 722 | + /* Do the same for visible VRAM if half of it is free */ | |
| 723 | + if (!amdgpu_gmc_vram_full_visible(&adev->gmc)) { | |
| 724 | + u64 total_vis_vram = adev->gmc.visible_vram_size; | |
| 725 | + u64 used_vis_vram = | |
| 726 | + amdgpu_vram_mgr_vis_usage(&adev->mman.vram_mgr); | |
| 727 | + | |
| 728 | + if (used_vis_vram < total_vis_vram) { | |
| 729 | + u64 free_vis_vram = total_vis_vram - used_vis_vram; | |
| 730 | + adev->mm_stats.accum_us_vis = min(adev->mm_stats.accum_us_vis + | |
| 731 | + increment_us, us_upper_bound); | |
| 732 | + | |
| 733 | + if (free_vis_vram >= total_vis_vram / 2) | |
| 734 | + adev->mm_stats.accum_us_vis = | |
| 735 | + max(bytes_to_us(adev, free_vis_vram / 2), | |
| 736 | + adev->mm_stats.accum_us_vis); | |
| 737 | + } | |
| 738 | + | |
| 739 | + *max_vis_bytes = us_to_bytes(adev, adev->mm_stats.accum_us_vis); | |
| 740 | + } else { | |
| 741 | + *max_vis_bytes = 0; | |
| 726 | 742 | } |
| 743 | + | |
| 744 | + spin_unlock(&adev->mm_stats.lock); | |
| 727 | 745 | } |
| 728 | 746 | |
| 729 | −static int amdgpu_cs_vm_handling(struct amdgpu_cs_parser *p) | |
| 747 | +/* Report how many bytes have really been moved for the last command | |
| 748 | + * submission. This can result in a debt that can stop buffer migrations | |
| 749 | + * temporarily. | |
| 750 | + */ | |
| 751 | +void amdgpu_cs_report_moved_bytes(struct amdgpu_device *adev, u64 num_bytes, | |
| 752 | + u64 num_vis_bytes) | |
| 730 | 753 | { |
| 731 | − struct amdgpu_ring *ring = to_amdgpu_ring(p->entity->rq->sched); | |
| 732 | − struct amdgpu_fpriv *fpriv = p->filp->driver_priv; | |
| 733 | − struct amdgpu_device *adev = p->adev; | |
| 734 | − struct amdgpu_vm *vm = &fpriv->vm; | |
| 735 | − struct amdgpu_bo_list_entry *e; | |
| 736 | − struct amdgpu_bo_va *bo_va; | |
| 737 | − struct amdgpu_bo *bo; | |
| 738 | − int r; | |
| 754 | + spin_lock(&adev->mm_stats.lock); | |
| 755 | + adev->mm_stats.accum_us -= bytes_to_us(adev, num_bytes); | |
| 756 | + adev->mm_stats.accum_us_vis -= bytes_to_us(adev, num_vis_bytes); | |
| 757 | + spin_unlock(&adev->mm_stats.lock); | |
| 758 | +} | |
| 739 | 759 | |
| 740 | − /* Only for UVD/VCE VM emulation */ | |
| 741 | − if (ring->funcs->parse_cs || ring->funcs->patch_cs_in_place) { | |
| 742 | − unsigned i, j; | |
| 743 | − | |
| 744 | − for (i = 0, j = 0; i < p->nchunks && j < p->job->num_ibs; i++) { | |
| 745 | − struct drm_amdgpu_cs_chunk_ib *chunk_ib; | |
| 746 | − struct amdgpu_bo_va_mapping *m; | |
| 747 | − struct amdgpu_bo *aobj = NULL; | |
| 748 | − struct amdgpu_cs_chunk *chunk; | |
| 749 | − uint64_t offset, va_start; | |
| 750 | − struct amdgpu_ib *ib; | |
| 751 | − uint8_t *kptr; | |
| 752 | − | |
| 753 | − chunk = &p->chunks[i]; | |
| 754 | − ib = &p->job->ibs[j]; | |
| 755 | − chunk_ib = chunk->kdata; | |
| 756 | − | |
| 757 | − if (chunk->chunk_id != AMDGPU_CHUNK_ID_IB) | |
| 758 | − continue; | |
| 760 | +static int amdgpu_cs_bo_validate(void *param, struct amdgpu_bo *bo) | |
| 761 | +{ | |
| 762 | + struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev); | |
| 763 | + struct amdgpu_cs_parser *p = param; | |
| 764 | + struct ttm_operation_ctx ctx = { | |
| 765 | + .interruptible = true, | |
| 766 | + .no_wait_gpu = false, | |
| 767 | + .resv = bo->tbo.base.resv | |
| 768 | + }; | |
| 769 | + uint32_t domain; | |
| 770 | + int r; | |
| 759 | 771 | |
| 760 | − va_start = chunk_ib->va_start & AMDGPU_GMC_HOLE_MASK; | |
| 761 | − r = amdgpu_cs_find_mapping(p, va_start, &aobj, &m); | |
| 762 | − if (r) { | |
| 763 | − DRM_ERROR("IB va_start is invalid\n"); | |
| 764 | − return r; | |
| 765 | − } | |
| 772 | + if (bo->tbo.pin_count) | |
| 773 | + return 0; | |
| 766 | 774 | |
| 767 | − if ((va_start + chunk_ib->ib_bytes) > | |
| 768 | − (m->last + 1) * AMDGPU_GPU_PAGE_SIZE) { | |
| 769 | − DRM_ERROR("IB va_start+ib_bytes is invalid\n"); | |
| 770 | − return -EINVAL; | |
| 771 | − } | |
| 775 | + /* Don't move this buffer if we have depleted our allowance | |
| 776 | + * to move it. Don't move anything if the threshold is zero. | |
| 777 | + */ | |
| 778 | + if (p->bytes_moved < p->bytes_moved_threshold && | |
| 779 | + (!bo->tbo.base.dma_buf || | |
| 780 | + list_empty(&bo->tbo.base.dma_buf->attachments))) { | |
| 781 | + if (!amdgpu_gmc_vram_full_visible(&adev->gmc) && | |
| 782 | + (bo->flags & AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED)) { | |
| 783 | + /* And don't move a CPU_ACCESS_REQUIRED BO to limited | |
| 784 | + * visible VRAM if we've depleted our allowance to do | |
| 785 | + * that. | |
| 786 | + */ | |
| 787 | + if (p->bytes_moved_vis < p->bytes_moved_vis_threshold) | |
| 788 | + domain = bo->preferred_domains; | |
| 789 | + else | |
| 790 | + domain = bo->allowed_domains; | |
| 791 | + } else { | |
| 792 | + domain = bo->preferred_domains; | |
| 793 | + } | |
| 794 | + } else { | |
| 795 | + domain = bo->allowed_domains; | |
| 796 | + } | |
| 772 | 797 | |
| 773 | − /* the IB should be reserved at this point */ | |
| 774 | − r = amdgpu_bo_kmap(aobj, (void **)&kptr); | |
| 775 | − if (r) { | |
| 776 | − return r; | |
| 777 | − } | |
| 798 | +retry: | |
| 799 | + amdgpu_bo_placement_from_domain(bo, domain); | |
| 800 | + r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx); | |
| 778 | 801 | |
| 779 | − offset = m->start * AMDGPU_GPU_PAGE_SIZE; | |
| 780 | − kptr += va_start - offset; | |
| 781 | − | |
| 782 | − if (ring->funcs->parse_cs) { | |
| 783 | − memcpy(ib->ptr, kptr, chunk_ib->ib_bytes); | |
| 784 | − amdgpu_bo_kunmap(aobj); | |
| 785 | − | |
| 786 | − r = amdgpu_ring_parse_cs(ring, p, p->job, ib); | |
| 787 | − if (r) | |
| 788 | − return r; | |
| 789 | − } else { | |
| 790 | − ib->ptr = (uint32_t *)kptr; | |
| 791 | − r = amdgpu_ring_patch_cs_in_place(ring, p, p->job, ib); | |
| 792 | − amdgpu_bo_kunmap(aobj); | |
| 793 | − if (r) | |
| 794 | − return r; | |
| 795 | − } | |
| 802 | + p->bytes_moved += ctx.bytes_moved; | |
| 803 | + if (!amdgpu_gmc_vram_full_visible(&adev->gmc) && | |
| 804 | + amdgpu_bo_in_cpu_visible_vram(bo)) | |
| 805 | + p->bytes_moved_vis += ctx.bytes_moved; | |
| 796 | 806 | |
| 797 | − j++; | |
| 798 | − } | |
| 807 | + if (unlikely(r == -ENOMEM) && domain != bo->allowed_domains) { | |
| 808 | + domain = bo->allowed_domains; | |
| 809 | + goto retry; | |
| 799 | 810 | } |
| 800 | 811 | |
| 801 | − if (!p->job->vm) | |
| 802 | − return amdgpu_cs_sync_rings(p); | |
| 812 | + return r; | |
| 813 | +} | |
| 803 | 814 | |
| 815 | +static int amdgpu_cs_list_validate(struct amdgpu_cs_parser *p, | |
| 816 | + struct list_head *validated) | |
| 817 | +{ | |
| 818 | + struct ttm_operation_ctx ctx = { true, false }; | |
| 819 | + struct amdgpu_bo_list_entry *lobj; | |
| 820 | + int r; | |
| 804 | 821 | |
| 805 | − r = amdgpu_vm_clear_freed(adev, vm, NULL); | |
| 806 | − if (r) | |
| 807 | − return r; | |
| 822 | + list_for_each_entry(lobj, validated, tv.head) { | |
| 823 | + struct amdgpu_bo *bo = ttm_to_amdgpu_bo(lobj->tv.bo); | |
| 824 | + struct mm_struct *usermm; | |
| 808 | 825 | |
| 809 | − r = amdgpu_vm_bo_update(adev, fpriv->prt_va, false); | |
| 810 | − if (r) | |
| 811 | − return r; | |
| 826 | + usermm = amdgpu_ttm_tt_get_usermm(bo->tbo.ttm); | |
| 827 | + if (usermm && usermm != current->mm) | |
| 828 | + return -EPERM; | |
| 812 | 829 | |
| 813 | − r = amdgpu_sync_fence(&p->job->sync, fpriv->prt_va->last_pt_update); | |
| 814 | − if (r) | |
| 815 | − return r; | |
| 830 | + if (amdgpu_ttm_tt_is_userptr(bo->tbo.ttm) && | |
| 831 | + lobj->user_invalidated && lobj->user_pages) { | |
| 832 | + amdgpu_bo_placement_from_domain(bo, | |
| 833 | + AMDGPU_GEM_DOMAIN_CPU); | |
| 834 | + r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx); | |
| 835 | + if (r) | |
| 836 | + return r; | |
| 816 | 837 | |
| 817 | − if (amdgpu_mcbp || amdgpu_sriov_vf(adev)) { | |
| 818 | − bo_va = fpriv->csa_va; | |
| 819 | − BUG_ON(!bo_va); | |
| 820 | − r = amdgpu_vm_bo_update(adev, bo_va, false); | |
| 821 | − if (r) | |
| 822 | − return r; | |
| 838 | + amdgpu_ttm_tt_set_user_pages(bo->tbo.ttm, | |
| 839 | + lobj->user_pages); | |
| 840 | + } | |
| 823 | 841 | |
| 824 | − r = amdgpu_sync_fence(&p->job->sync, bo_va->last_pt_update); | |
| 842 | + r = amdgpu_cs_bo_validate(p, bo); | |
| 825 | 843 | if (r) |
| 826 | 844 | return r; |
| 845 | + | |
| 846 | + kvfree(lobj->user_pages); | |
| 847 | + lobj->user_pages = NULL; | |
| 827 | 848 | } |
| 849 | + return 0; | |
| 850 | +} | |
| 828 | 851 | |
| 829 | − amdgpu_bo_list_for_each_entry(e, p->bo_list) { | |
| 830 | − /* ignore duplicates */ | |
| 831 | − bo = ttm_to_amdgpu_bo(e->tv.bo); | |
| 832 | − if (!bo) | |
| 833 | − continue; | |
| 852 | +static int amdgpu_cs_parser_bos(struct amdgpu_cs_parser *p, | |
| 853 | + union drm_amdgpu_cs *cs) | |
| 854 | +{ | |
| 855 | + struct amdgpu_fpriv *fpriv = p->filp->driver_priv; | |
| 856 | + struct amdgpu_vm *vm = &fpriv->vm; | |
| 857 | + struct amdgpu_bo_list_entry *e; | |
| 858 | + struct list_head duplicates; | |
| 859 | + unsigned int i; | |
| 860 | + int r; | |
| 834 | 861 | |
| 835 | − bo_va = e->bo_va; | |
| 836 | − if (bo_va == NULL) | |
| 837 | − continue; | |
| 862 | + INIT_LIST_HEAD(&p->validated); | |
| 838 | 863 | |
| 839 | − r = amdgpu_vm_bo_update(adev, bo_va, false); | |
| 864 | + /* p->bo_list could already be assigned if AMDGPU_CHUNK_ID_BO_HANDLES is present */ | |
| 865 | + if (cs->in.bo_list_handle) { | |
| 866 | + if (p->bo_list) | |
| 867 | + return -EINVAL; | |
| 868 | + | |
| 869 | + r = amdgpu_bo_list_get(fpriv, cs->in.bo_list_handle, | |
| 870 | + &p->bo_list); | |
| 840 | 871 | if (r) |
| 841 | 872 | return r; |
| 842 | − | |
| 843 | − r = amdgpu_sync_fence(&p->job->sync, bo_va->last_pt_update); | |
| 873 | + } else if (!p->bo_list) { | |
| 874 | + /* Create a empty bo_list when no handle is provided */ | |
| 875 | + r = amdgpu_bo_list_create(p->adev, p->filp, NULL, 0, | |
| 876 | + &p->bo_list); | |
| 844 | 877 | if (r) |
| 845 | 878 | return r; |
| 846 | 879 | } |
| 847 | 880 | |
| 848 | − r = amdgpu_vm_handle_moved(adev, vm); | |
| 849 | − if (r) | |
| 850 | − return r; | |
| 881 | + mutex_lock(&p->bo_list->bo_list_mutex); | |
| 851 | 882 | |
| 852 | − r = amdgpu_vm_update_pdes(adev, vm, false); | |
| 853 | − if (r) | |
| 854 | − return r; | |
| 883 | + /* One for TTM and one for the CS job */ | |
| 884 | + amdgpu_bo_list_for_each_entry(e, p->bo_list) | |
| 885 | + e->tv.num_shared = 2; | |
| 855 | 886 | |
| 856 | − r = amdgpu_sync_fence(&p->job->sync, vm->last_update); | |
| 857 | − if (r) | |
| 858 | − return r; | |
| 887 | + amdgpu_bo_list_get_list(p->bo_list, &p->validated); | |
| 859 | 888 | |
| 860 | − p->job->vm_pd_addr = amdgpu_gmc_pd_addr(vm->root.bo); | |
| 889 | + INIT_LIST_HEAD(&duplicates); | |
| 890 | + amdgpu_vm_get_pd_bo(&fpriv->vm, &p->validated, &p->vm_pd); | |
| 861 | 891 | |
| 862 | − if (amdgpu_vm_debug) { | |
| 863 | − /* Invalidate all BOs to test for userspace bugs */ | |
| 864 | − amdgpu_bo_list_for_each_entry(e, p->bo_list) { | |
| 865 | − struct amdgpu_bo *bo = ttm_to_amdgpu_bo(e->tv.bo); | |
| 892 | + if (p->uf_entry.tv.bo && !ttm_to_amdgpu_bo(p->uf_entry.tv.bo)->parent) | |
| 893 | + list_add(&p->uf_entry.tv.head, &p->validated); | |
| 866 | 894 | |
| 867 | − /* ignore duplicates */ | |
| 868 | − if (!bo) | |
| 869 | − continue; | |
| 895 | + /* Get userptr backing pages. If pages are updated after registered | |
| 896 | + * in amdgpu_gem_userptr_ioctl(), amdgpu_cs_list_validate() will do | |
| 897 | + * amdgpu_ttm_backend_bind() to flush and invalidate new pages | |
| 898 | + */ | |
| 899 | + amdgpu_bo_list_for_each_userptr_entry(e, p->bo_list) { | |
| 900 | + struct amdgpu_bo *bo = ttm_to_amdgpu_bo(e->tv.bo); | |
| 901 | + bool userpage_invalidated = false; | |
| 902 | + int i; | |
| 870 | 903 | |
| 871 | − amdgpu_vm_bo_invalidate(adev, bo, false); | |
| 904 | + e->user_pages = kvmalloc_array(bo->tbo.ttm->num_pages, | |
| 905 | + sizeof(struct page *), | |
| 906 | + GFP_KERNEL | __GFP_ZERO); | |
| 907 | + if (!e->user_pages) { | |
| 908 | + DRM_ERROR("kvmalloc_array failure\n"); | |
| 909 | + r = -ENOMEM; | |
| 910 | + goto out_free_user_pages; | |
| 872 | 911 | } |
| 873 | − } | |
| 874 | − | |
| 875 | − return amdgpu_cs_sync_rings(p); | |
| 876 | −} | |
| 877 | − | |
| 878 | −static int amdgpu_cs_ib_fill(struct amdgpu_device *adev, | |
| 879 | − struct amdgpu_cs_parser *parser) | |
| 880 | −{ | |
| 881 | − struct amdgpu_fpriv *fpriv = parser->filp->driver_priv; | |
| 882 | − struct amdgpu_vm *vm = &fpriv->vm; | |
| 883 | − int r, ce_preempt = 0, de_preempt = 0; | |
| 884 | − struct amdgpu_ring *ring; | |
| 885 | − int i, j; | |
| 886 | − | |
| 887 | − for (i = 0, j = 0; i < parser->nchunks && j < parser->job->num_ibs; i++) { | |
| 888 | − struct amdgpu_cs_chunk *chunk; | |
| 889 | − struct amdgpu_ib *ib; | |
| 890 | − struct drm_amdgpu_cs_chunk_ib *chunk_ib; | |
| 891 | − struct drm_sched_entity *entity; | |
| 892 | 912 | |
| 893 | − chunk = &parser->chunks[i]; | |
| 894 | − ib = &parser->job->ibs[j]; | |
| 895 | − chunk_ib = (struct drm_amdgpu_cs_chunk_ib *)chunk->kdata; | |
| 896 | − | |
| 897 | − if (chunk->chunk_id != AMDGPU_CHUNK_ID_IB) | |
| 898 | − continue; | |
| 913 | + r = amdgpu_ttm_tt_get_user_pages(bo, e->user_pages); | |
| 914 | + if (r) { | |
| 915 | + kvfree(e->user_pages); | |
| 916 | + e->user_pages = NULL; | |
| 917 | + goto out_free_user_pages; | |
| 918 | + } | |
| 899 | 919 | |
| 900 | − if (chunk_ib->ip_type == AMDGPU_HW_IP_GFX && | |
| 901 | − (amdgpu_mcbp || amdgpu_sriov_vf(adev))) { | |
| 902 | − if (chunk_ib->flags & AMDGPU_IB_FLAG_PREEMPT) { | |
| 903 | − if (chunk_ib->flags & AMDGPU_IB_FLAG_CE) | |
| 904 | − ce_preempt++; | |
| 905 | − else | |
| 906 | − de_preempt++; | |
| 920 | + for (i = 0; i < bo->tbo.ttm->num_pages; i++) { | |
| 921 | + if (bo->tbo.ttm->pages[i] != e->user_pages[i]) { | |
| 922 | + userpage_invalidated = true; | |
| 923 | + break; | |
| 907 | 924 | } |
| 908 | − | |
| 909 | − /* each GFX command submit allows 0 or 1 IB preemptible for CE & DE */ | |
| 910 | − if (ce_preempt > 1 || de_preempt > 1) | |
| 911 | − return -EINVAL; | |
| 912 | 925 | } |
| 926 | + e->user_invalidated = userpage_invalidated; | |
| 927 | + } | |
| 913 | 928 | |
| 914 | − r = amdgpu_ctx_get_entity(parser->ctx, chunk_ib->ip_type, | |
| 915 | − chunk_ib->ip_instance, chunk_ib->ring, | |
| 916 | − &entity); | |
| 917 | − if (r) | |
| 918 | − return r; | |
| 919 | − | |
| 920 | − if (chunk_ib->flags & AMDGPU_IB_FLAG_PREAMBLE) | |
| 921 | − parser->job->preamble_status |= | |
| 922 | − AMDGPU_PREAMBLE_IB_PRESENT; | |
| 923 | − | |
| 924 | − if (parser->entity && parser->entity != entity) | |
| 925 | − return -EINVAL; | |
| 926 | − | |
| 927 | − /* Return if there is no run queue associated with this entity. | |
| 928 | − * Possibly because of disabled HW IP*/ | |
| 929 | − if (entity->rq == NULL) | |
| 930 | − return -EINVAL; | |
| 931 | − | |
| 932 | − parser->entity = entity; | |
| 933 | − | |
| 934 | − ring = to_amdgpu_ring(entity->rq->sched); | |
| 935 | − r = amdgpu_ib_get(adev, vm, ring->funcs->parse_cs ? | |
| 936 | − chunk_ib->ib_bytes : 0, | |
| 937 | − AMDGPU_IB_POOL_DELAYED, ib); | |
| 938 | − if (r) { | |
| 939 | − DRM_ERROR("Failed to get ib !\n"); | |
| 940 | − return r; | |
| 941 | − } | |
| 929 | + r = ttm_eu_reserve_buffers(&p->ticket, &p->validated, true, | |
| 930 | + &duplicates); | |
| 931 | + if (unlikely(r != 0)) { | |
| 932 | + if (r != -ERESTARTSYS) | |
| 933 | + DRM_ERROR("ttm_eu_reserve_buffers failed.\n"); | |
| 934 | + goto out_free_user_pages; | |
| 935 | + } | |
| 942 | 936 | |
| 943 | − ib->gpu_addr = chunk_ib->va_start; | |
| 944 | − ib->length_dw = chunk_ib->ib_bytes / 4; | |
| 945 | − ib->flags = chunk_ib->flags; | |
| 937 | + amdgpu_bo_list_for_each_entry(e, p->bo_list) { | |
| 938 | + struct amdgpu_bo *bo = ttm_to_amdgpu_bo(e->tv.bo); | |
| 946 | 939 | |
| 947 | − j++; | |
| 940 | + e->bo_va = amdgpu_vm_bo_find(vm, bo); | |
| 948 | 941 | } |
| 949 | 942 | |
| 950 | − /* MM engine doesn't support user fences */ | |
| 951 | − ring = to_amdgpu_ring(parser->entity->rq->sched); | |
| 952 | − if (parser->job->uf_addr && ring->funcs->no_user_fence) | |
| 953 | − return -EINVAL; | |
| 943 | + amdgpu_cs_get_threshold_for_moves(p->adev, &p->bytes_moved_threshold, | |
| 944 | + &p->bytes_moved_vis_threshold); | |
| 945 | + p->bytes_moved = 0; | |
| 946 | + p->bytes_moved_vis = 0; | |
| 954 | 947 | |
| 955 | − return 0; | |
| 956 | −} | |
| 948 | + r = amdgpu_vm_validate_pt_bos(p->adev, &fpriv->vm, | |
| 949 | + amdgpu_cs_bo_validate, p); | |
| 950 | + if (r) { | |
| 951 | + DRM_ERROR("amdgpu_vm_validate_pt_bos() failed.\n"); | |
| 952 | + goto error_validate; | |
| 953 | + } | |
| 957 | 954 | |
| 958 | −static int amdgpu_cs_process_fence_dep(struct amdgpu_cs_parser *p, | |
| 959 | − struct amdgpu_cs_chunk *chunk) | |
| 960 | −{ | |
| 961 | − struct amdgpu_fpriv *fpriv = p->filp->driver_priv; | |
| 962 | − unsigned num_deps; | |
| 963 | − int i, r; | |
| 964 | − struct drm_amdgpu_cs_chunk_dep *deps; | |
| 955 | + r = amdgpu_cs_list_validate(p, &duplicates); | |
| 956 | + if (r) | |
| 957 | + goto error_validate; | |
| 965 | 958 | |
| 966 | − deps = (struct drm_amdgpu_cs_chunk_dep *)chunk->kdata; | |
| 967 | − num_deps = chunk->length_dw * 4 / | |
| 968 | − sizeof(struct drm_amdgpu_cs_chunk_dep); | |
| 959 | + r = amdgpu_cs_list_validate(p, &p->validated); | |
| 960 | + if (r) | |
| 961 | + goto error_validate; | |
| 969 | 962 | |
| 970 | − for (i = 0; i < num_deps; ++i) { | |
| 971 | − struct amdgpu_ctx *ctx; | |
| 972 | − struct drm_sched_entity *entity; | |
| 973 | − struct dma_fence *fence; | |
| 963 | + if (p->uf_entry.tv.bo) { | |
| 964 | + struct amdgpu_bo *uf = ttm_to_amdgpu_bo(p->uf_entry.tv.bo); | |
| 974 | 965 | |
| 975 | − ctx = amdgpu_ctx_get(fpriv, deps[i].ctx_id); | |
| 976 | − if (ctx == NULL) | |
| 977 | − return -EINVAL; | |
| 966 | + r = amdgpu_ttm_alloc_gart(&uf->tbo); | |
| 967 | + if (r) | |
| 968 | + goto error_validate; | |
| 978 | 969 | |
| 979 | − r = amdgpu_ctx_get_entity(ctx, deps[i].ip_type, | |
| 980 | − deps[i].ip_instance, | |
| 981 | − deps[i].ring, &entity); | |
| 982 | − if (r) { | |
| 983 | − amdgpu_ctx_put(ctx); | |
| 984 | − return r; | |
| 985 | − } | |
| 970 | + p->gang_leader->uf_addr += amdgpu_bo_gpu_offset(uf); | |
| 971 | + } | |
| 986 | 972 | |
| 987 | − fence = amdgpu_ctx_get_fence(ctx, entity, deps[i].handle); | |
| 988 | − amdgpu_ctx_put(ctx); | |
| 973 | + amdgpu_cs_report_moved_bytes(p->adev, p->bytes_moved, | |
| 974 | + p->bytes_moved_vis); | |
| 989 | 975 | |
| 990 | − if (IS_ERR(fence)) | |
| 991 | − return PTR_ERR(fence); | |
| 992 | − else if (!fence) | |
| 993 | − continue; | |
| 976 | + for (i = 0; i < p->gang_size; ++i) | |
| 977 | + amdgpu_job_set_resources(p->jobs[i], p->bo_list->gds_obj, | |
| 978 | + p->bo_list->gws_obj, | |
| 979 | + p->bo_list->oa_obj); | |
| 980 | + return 0; | |
| 994 | 981 | |
| 995 | − if (chunk->chunk_id == AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES) { | |
| 996 | − struct drm_sched_fence *s_fence; | |
| 997 | − struct dma_fence *old = fence; | |
| 982 | +error_validate: | |
| 983 | + ttm_eu_backoff_reservation(&p->ticket, &p->validated); | |
| 998 | 984 | |
| 999 | − s_fence = to_drm_sched_fence(fence); | |
| 1000 | − fence = dma_fence_get(&s_fence->scheduled); | |
| 1001 | − dma_fence_put(old); | |
| 1002 | − } | |
| 985 | +out_free_user_pages: | |
| 986 | + amdgpu_bo_list_for_each_userptr_entry(e, p->bo_list) { | |
| 987 | + struct amdgpu_bo *bo = ttm_to_amdgpu_bo(e->tv.bo); | |
| 1003 | 988 | |
| 1004 | − r = amdgpu_sync_fence(&p->job->sync, fence); | |
| 1005 | − dma_fence_put(fence); | |
| 1006 | − if (r) | |
| 1007 | − return r; | |
| 989 | + if (!e->user_pages) | |
| 990 | + continue; | |
| 991 | + amdgpu_ttm_tt_get_user_pages_done(bo->tbo.ttm); | |
| 992 | + kvfree(e->user_pages); | |
| 993 | + e->user_pages = NULL; | |
| 1008 | 994 | } |
| 1009 | − return 0; | |
| 995 | + return r; | |
| 1010 | 996 | } |
| 1011 | 997 | |
| 1012 | −static int amdgpu_syncobj_lookup_and_add_to_sync(struct amdgpu_cs_parser *p, | |
| 1013 | − uint32_t handle, u64 point, | |
| 1014 | − u64 flags) | |
| 998 | +static void trace_amdgpu_cs_ibs(struct amdgpu_cs_parser *p) | |
| 1015 | 999 | { |
| 1016 | − struct dma_fence *fence; | |
| 1017 | − int r; | |
| 1000 | + int i, j; | |
| 1018 | 1001 | |
| 1019 | − r = drm_syncobj_find_fence(p->filp, handle, point, flags, &fence); | |
| 1020 | − if (r) { | |
| 1021 | − DRM_ERROR("syncobj %u failed to find fence @ %llu (%d)!\n", | |
| 1022 | − handle, point, r); | |
| 1023 | − return r; | |
| 1024 | − } | |
| 1002 | + if (!trace_amdgpu_cs_enabled()) | |
| 1003 | + return; | |
| 1025 | 1004 | |
| 1026 | − r = amdgpu_sync_fence(&p->job->sync, fence); | |
| 1027 | − dma_fence_put(fence); | |
| 1005 | + for (i = 0; i < p->gang_size; ++i) { | |
| 1006 | + struct amdgpu_job *job = p->jobs[i]; | |
| 1028 | 1007 | |
| 1029 | − return r; | |
| 1008 | + for (j = 0; j < job->num_ibs; ++j) | |
| 1009 | + trace_amdgpu_cs(p, job, &job->ibs[j]); | |
| 1010 | + } | |
| 1030 | 1011 | } |
| 1031 | 1012 | |
| 1032 | −static int amdgpu_cs_process_syncobj_in_dep(struct amdgpu_cs_parser *p, | |
| 1033 | − struct amdgpu_cs_chunk *chunk) | |
| 1013 | +static int amdgpu_cs_patch_ibs(struct amdgpu_cs_parser *p, | |
| 1014 | + struct amdgpu_job *job) | |
| 1034 | 1015 | { |
| 1035 | − struct drm_amdgpu_cs_chunk_sem *deps; | |
| 1036 | − unsigned num_deps; | |
| 1037 | − int i, r; | |
| 1016 | + struct amdgpu_ring *ring = amdgpu_job_ring(job); | |
| 1017 | + unsigned int i; | |
| 1018 | + int r; | |
| 1038 | 1019 | |
| 1039 | − deps = (struct drm_amdgpu_cs_chunk_sem *)chunk->kdata; | |
| 1040 | − num_deps = chunk->length_dw * 4 / | |
| 1041 | − sizeof(struct drm_amdgpu_cs_chunk_sem); | |
| 1042 | − for (i = 0; i < num_deps; ++i) { | |
| 1043 | − r = amdgpu_syncobj_lookup_and_add_to_sync(p, deps[i].handle, | |
| 1044 | − 0, 0); | |
| 1045 | − if (r) | |
| 1020 | + /* Only for UVD/VCE VM emulation */ | |
| 1021 | + if (!ring->funcs->parse_cs && !ring->funcs->patch_cs_in_place) | |
| 1022 | + return 0; | |
| 1023 | + | |
| 1024 | + for (i = 0; i < job->num_ibs; ++i) { | |
| 1025 | + struct amdgpu_ib *ib = &job->ibs[i]; | |
| 1026 | + struct amdgpu_bo_va_mapping *m; | |
| 1027 | + struct amdgpu_bo *aobj; | |
| 1028 | + uint64_t va_start; | |
| 1029 | + uint8_t *kptr; | |
| 1030 | + | |
| 1031 | + va_start = ib->gpu_addr & AMDGPU_GMC_HOLE_MASK; | |
| 1032 | + r = amdgpu_cs_find_mapping(p, va_start, &aobj, &m); | |
| 1033 | + if (r) { | |
| 1034 | + DRM_ERROR("IB va_start is invalid\n"); | |
| 1046 | 1035 | return r; |
| 1036 | + } | |
| 1037 | + | |
| 1038 | + if ((va_start + ib->length_dw * 4) > | |
| 1039 | + (m->last + 1) * AMDGPU_GPU_PAGE_SIZE) { | |
| 1040 | + DRM_ERROR("IB va_start+ib_bytes is invalid\n"); | |
| 1041 | + return -EINVAL; | |
| 1042 | + } | |
| 1043 | + | |
| 1044 | + /* the IB should be reserved at this point */ | |
| 1045 | + r = amdgpu_bo_kmap(aobj, (void **)&kptr); | |
| 1046 | + if (r) { | |
| 1047 | + return r; | |
| 1048 | + } | |
| 1049 | + | |
| 1050 | + kptr += va_start - (m->start * AMDGPU_GPU_PAGE_SIZE); | |
| 1051 | + | |
| 1052 | + if (ring->funcs->parse_cs) { | |
| 1053 | + memcpy(ib->ptr, kptr, ib->length_dw * 4); | |
| 1054 | + amdgpu_bo_kunmap(aobj); | |
| 1055 | + | |
| 1056 | + r = amdgpu_ring_parse_cs(ring, p, job, ib); | |
| 1057 | + if (r) | |
| 1058 | + return r; | |
| 1059 | + } else { | |
| 1060 | + ib->ptr = (uint32_t *)kptr; | |
| 1061 | + r = amdgpu_ring_patch_cs_in_place(ring, p, job, ib); | |
| 1062 | + amdgpu_bo_kunmap(aobj); | |
| 1063 | + if (r) | |
| 1064 | + return r; | |
| 1065 | + } | |
| 1047 | 1066 | } |
| 1048 | 1067 | |
| 1049 | 1068 | return 0; |
| 1050 | 1069 | } |
| 1051 | 1070 | |
| 1052 | − | |
| 1053 | −static int amdgpu_cs_process_syncobj_timeline_in_dep(struct amdgpu_cs_parser *p, | |
| 1054 | − struct amdgpu_cs_chunk *chunk) | |
| 1071 | +static int amdgpu_cs_patch_jobs(struct amdgpu_cs_parser *p) | |
| 1055 | 1072 | { |
| 1056 | − struct drm_amdgpu_cs_chunk_syncobj *syncobj_deps; | |
| 1057 | − unsigned num_deps; | |
| 1058 | − int i, r; | |
| 1073 | + unsigned int i; | |
| 1074 | + int r; | |
| 1059 | 1075 | |
| 1060 | − syncobj_deps = (struct drm_amdgpu_cs_chunk_syncobj *)chunk->kdata; | |
| 1061 | − num_deps = chunk->length_dw * 4 / | |
| 1062 | − sizeof(struct drm_amdgpu_cs_chunk_syncobj); | |
| 1063 | − for (i = 0; i < num_deps; ++i) { | |
| 1064 | − r = amdgpu_syncobj_lookup_and_add_to_sync(p, | |
| 1065 | − syncobj_deps[i].handle, | |
| 1066 | − syncobj_deps[i].point, | |
| 1067 | − syncobj_deps[i].flags); | |
| 1076 | + for (i = 0; i < p->gang_size; ++i) { | |
| 1077 | + r = amdgpu_cs_patch_ibs(p, p->jobs[i]); | |
| 1068 | 1078 | if (r) |
| 1069 | 1079 | return r; |
| 1070 | 1080 | } |
| 1071 | − | |
| 1072 | 1081 | return 0; |
| 1073 | 1082 | } |
| 1074 | 1083 | |
| 1075 | −static int amdgpu_cs_process_syncobj_out_dep(struct amdgpu_cs_parser *p, | |
| 1076 | − struct amdgpu_cs_chunk *chunk) | |
| 1084 | +static int amdgpu_cs_vm_handling(struct amdgpu_cs_parser *p) | |
| 1077 | 1085 | { |
| 1078 | − struct drm_amdgpu_cs_chunk_sem *deps; | |
| 1079 | − unsigned num_deps; | |
| 1080 | − int i; | |
| 1081 | − | |
| 1082 | − deps = (struct drm_amdgpu_cs_chunk_sem *)chunk->kdata; | |
| 1083 | − num_deps = chunk->length_dw * 4 / | |
| 1084 | − sizeof(struct drm_amdgpu_cs_chunk_sem); | |
| 1086 | + struct amdgpu_fpriv *fpriv = p->filp->driver_priv; | |
| 1087 | + struct amdgpu_job *job = p->gang_leader; | |
| 1088 | + struct amdgpu_device *adev = p->adev; | |
| 1089 | + struct amdgpu_vm *vm = &fpriv->vm; | |
| 1090 | + struct amdgpu_bo_list_entry *e; | |
| 1091 | + struct amdgpu_bo_va *bo_va; | |
| 1092 | + struct amdgpu_bo *bo; | |
| 1093 | + unsigned int i; | |
| 1094 | + int r; | |
| 1085 | 1095 | |
| 1086 | − if (p->post_deps) | |
| 1087 | − return -EINVAL; | |
| 1096 | + r = amdgpu_vm_clear_freed(adev, vm, NULL); | |
| 1097 | + if (r) | |
| 1098 | + return r; | |
| 1088 | 1099 | |
| 1089 | − p->post_deps = kmalloc_array(num_deps, sizeof(*p->post_deps), | |
| 1090 | − GFP_KERNEL); | |
| 1091 | − p->num_post_deps = 0; | |
| 1100 | + r = amdgpu_vm_bo_update(adev, fpriv->prt_va, false); | |
| 1101 | + if (r) | |
| 1102 | + return r; | |
| 1092 | 1103 | |
| 1093 | − if (!p->post_deps) | |
| 1094 | − return -ENOMEM; | |
| 1104 | + r = amdgpu_sync_fence(&job->sync, fpriv->prt_va->last_pt_update); | |
| 1105 | + if (r) | |
| 1106 | + return r; | |
| 1095 | 1107 | |
| 1108 | + if (fpriv->csa_va) { | |
| 1109 | + bo_va = fpriv->csa_va; | |
| 1110 | + BUG_ON(!bo_va); | |
| 1111 | + r = amdgpu_vm_bo_update(adev, bo_va, false); | |
| 1112 | + if (r) | |
| 1113 | + return r; | |
| 1096 | 1114 | |
| 1097 | − for (i = 0; i < num_deps; ++i) { | |
| 1098 | − p->post_deps[i].syncobj = | |
| 1099 | − drm_syncobj_find(p->filp, deps[i].handle); | |
| 1100 | − if (!p->post_deps[i].syncobj) | |
| 1101 | − return -EINVAL; | |
| 1102 | − p->post_deps[i].chain = NULL; | |
| 1103 | − p->post_deps[i].point = 0; | |
| 1104 | − p->num_post_deps++; | |
| 1115 | + r = amdgpu_sync_fence(&job->sync, bo_va->last_pt_update); | |
| 1116 | + if (r) | |
| 1117 | + return r; | |
| 1105 | 1118 | } |
| 1106 | 1119 | |
| 1107 | − return 0; | |
| 1108 | −} | |
| 1120 | + amdgpu_bo_list_for_each_entry(e, p->bo_list) { | |
| 1121 | + /* ignore duplicates */ | |
| 1122 | + bo = ttm_to_amdgpu_bo(e->tv.bo); | |
| 1123 | + if (!bo) | |
| 1124 | + continue; | |
| 1109 | 1125 | |
| 1126 | + bo_va = e->bo_va; | |
| 1127 | + if (bo_va == NULL) | |
| 1128 | + continue; | |
| 1110 | 1129 | |
| 1111 | −static int amdgpu_cs_process_syncobj_timeline_out_dep(struct amdgpu_cs_parser *p, | |
| 1112 | − struct amdgpu_cs_chunk *chunk) | |
| 1113 | −{ | |
| 1114 | − struct drm_amdgpu_cs_chunk_syncobj *syncobj_deps; | |
| 1115 | − unsigned num_deps; | |
| 1116 | − int i; | |
| 1130 | + r = amdgpu_vm_bo_update(adev, bo_va, false); | |
| 1131 | + if (r) | |
| 1132 | + return r; | |
| 1117 | 1133 | |
| 1118 | − syncobj_deps = (struct drm_amdgpu_cs_chunk_syncobj *)chunk->kdata; | |
| 1119 | − num_deps = chunk->length_dw * 4 / | |
| 1120 | − sizeof(struct drm_amdgpu_cs_chunk_syncobj); | |
| 1134 | + r = amdgpu_sync_fence(&job->sync, bo_va->last_pt_update); | |
| 1135 | + if (r) | |
| 1136 | + return r; | |
| 1137 | + } | |
| 1121 | 1138 | |
| 1122 | − if (p->post_deps) | |
| 1123 | − return -EINVAL; | |
| 1139 | + r = amdgpu_vm_handle_moved(adev, vm); | |
| 1140 | + if (r) | |
| 1141 | + return r; | |
| 1124 | 1142 | |
| 1125 | − p->post_deps = kmalloc_array(num_deps, sizeof(*p->post_deps), | |
| 1126 | − GFP_KERNEL); | |
| 1127 | − p->num_post_deps = 0; | |
| 1143 | + r = amdgpu_vm_update_pdes(adev, vm, false); | |
| 1144 | + if (r) | |
| 1145 | + return r; | |
| 1128 | 1146 | |
| 1129 | − if (!p->post_deps) | |
| 1130 | − return -ENOMEM; | |
| 1147 | + r = amdgpu_sync_fence(&job->sync, vm->last_update); | |
| 1148 | + if (r) | |
| 1149 | + return r; | |
| 1131 | 1150 | |
| 1132 | − for (i = 0; i < num_deps; ++i) { | |
| 1133 | − struct amdgpu_cs_post_dep *dep = &p->post_deps[i]; | |
| 1151 | + for (i = 0; i < p->gang_size; ++i) { | |
| 1152 | + job = p->jobs[i]; | |
| 1134 | 1153 | |
| 1135 | − dep->chain = NULL; | |
| 1136 | − if (syncobj_deps[i].point) { | |
| 1137 | − dep->chain = dma_fence_chain_alloc(); | |
| 1138 | − if (!dep->chain) | |
| 1139 | − return -ENOMEM; | |
| 1140 | − } | |
| 1154 | + if (!job->vm) | |
| 1155 | + continue; | |
| 1141 | 1156 | |
| 1142 | − dep->syncobj = drm_syncobj_find(p->filp, | |
| 1143 | − syncobj_deps[i].handle); | |
| 1144 | − if (!dep->syncobj) { | |
| 1145 | − dma_fence_chain_free(dep->chain); | |
| 1146 | − return -EINVAL; | |
| 1157 | + job->vm_pd_addr = amdgpu_gmc_pd_addr(vm->root.bo); | |
| 1158 | + } | |
| 1159 | + | |
| 1160 | + if (amdgpu_vm_debug) { | |
| 1161 | + /* Invalidate all BOs to test for userspace bugs */ | |
| 1162 | + amdgpu_bo_list_for_each_entry(e, p->bo_list) { | |
| 1163 | + struct amdgpu_bo *bo = ttm_to_amdgpu_bo(e->tv.bo); | |
| 1164 | + | |
| 1165 | + /* ignore duplicates */ | |
| 1166 | + if (!bo) | |
| 1167 | + continue; | |
| 1168 | + | |
| 1169 | + amdgpu_vm_bo_invalidate(adev, bo, false); | |
| 1147 | 1170 | } |
| 1148 | − dep->point = syncobj_deps[i].point; | |
| 1149 | − p->num_post_deps++; | |
| 1150 | 1171 | } |
| 1151 | 1172 | |
| 1152 | 1173 | return 0; |
| 1153 | 1174 | } |
| 1154 | 1175 | |
| 1155 | −static int amdgpu_cs_dependencies(struct amdgpu_device *adev, | |
| 1156 | − struct amdgpu_cs_parser *p) | |
| 1176 | +static int amdgpu_cs_sync_rings(struct amdgpu_cs_parser *p) | |
| 1157 | 1177 | { |
| 1158 | − int i, r; | |
| 1159 | − | |
| 1160 | − /* TODO: Investigate why we still need the context lock */ | |
| 1161 | − mutex_unlock(&p->ctx->lock); | |
| 1178 | + struct amdgpu_fpriv *fpriv = p->filp->driver_priv; | |
| 1179 | + struct amdgpu_job *leader = p->gang_leader; | |
| 1180 | + struct amdgpu_bo_list_entry *e; | |
| 1181 | + unsigned int i; | |
| 1182 | + int r; | |
| 1162 | 1183 | |
| 1163 | − for (i = 0; i < p->nchunks; ++i) { | |
| 1164 | − struct amdgpu_cs_chunk *chunk; | |
| 1184 | + list_for_each_entry(e, &p->validated, tv.head) { | |
| 1185 | + struct amdgpu_bo *bo = ttm_to_amdgpu_bo(e->tv.bo); | |
| 1186 | + struct dma_resv *resv = bo->tbo.base.resv; | |
| 1187 | + enum amdgpu_sync_mode sync_mode; | |
| 1165 | 1188 | |
| 1166 | − chunk = &p->chunks[i]; | |
| 1189 | + sync_mode = amdgpu_bo_explicit_sync(bo) ? | |
| 1190 | + AMDGPU_SYNC_EXPLICIT : AMDGPU_SYNC_NE_OWNER; | |
| 1191 | + r = amdgpu_sync_resv(p->adev, &leader->sync, resv, sync_mode, | |
| 1192 | + &fpriv->vm); | |
| 1193 | + if (r) | |
| 1194 | + return r; | |
| 1195 | + } | |
| 1167 | 1196 | |
| 1168 | − switch (chunk->chunk_id) { | |
| 1169 | − case AMDGPU_CHUNK_ID_DEPENDENCIES: | |
| 1170 | − case AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES: | |
| 1171 | − r = amdgpu_cs_process_fence_dep(p, chunk); | |
| 1172 | − if (r) | |
| 1173 | − goto out; | |
| 1174 | − break; | |
| 1175 | − case AMDGPU_CHUNK_ID_SYNCOBJ_IN: | |
| 1176 | − r = amdgpu_cs_process_syncobj_in_dep(p, chunk); | |
| 1177 | − if (r) | |
| 1178 | − goto out; | |
| 1179 | − break; | |
| 1180 | − case AMDGPU_CHUNK_ID_SYNCOBJ_OUT: | |
| 1181 | − r = amdgpu_cs_process_syncobj_out_dep(p, chunk); | |
| 1182 | − if (r) | |
| 1183 | − goto out; | |
| 1184 | − break; | |
| 1185 | − case AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_WAIT: | |
| 1186 | − r = amdgpu_cs_process_syncobj_timeline_in_dep(p, chunk); | |
| 1187 | − if (r) | |
| 1188 | − goto out; | |
| 1189 | − break; | |
| 1190 | − case AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_SIGNAL: | |
| 1191 | − r = amdgpu_cs_process_syncobj_timeline_out_dep(p, chunk); | |
| 1192 | − if (r) | |
| 1193 | − goto out; | |
| 1194 | − break; | |
| 1195 | − } | |
| 1197 | + for (i = 0; i < p->gang_size - 1; ++i) { | |
| 1198 | + r = amdgpu_sync_clone(&leader->sync, &p->jobs[i]->sync); | |
| 1199 | + if (r) | |
| 1200 | + return r; | |
| 1196 | 1201 | } |
| 1197 | 1202 | |
| 1198 | −out: | |
| 1199 | − mutex_lock(&p->ctx->lock); | |
| 1203 | + r = amdgpu_ctx_wait_prev_fence(p->ctx, p->entities[p->gang_size - 1]); | |
| 1204 | + if (r && r != -ERESTARTSYS) | |
| 1205 | + DRM_ERROR("amdgpu_ctx_wait_prev_fence failed.\n"); | |
| 1206 | + | |
| 1200 | 1207 | return r; |
| 1201 | 1208 | } |
| 1202 | 1209 | |
| @@ -1221,20 +1228,28 @@ static int amdgpu_cs_submit(struct amdgpu_cs_parser *p, · 18 unmodified lines | ||
| 1221 | 1228 | union drm_amdgpu_cs *cs) |
| 1222 | 1229 | { |
| 1223 | 1230 | struct amdgpu_fpriv *fpriv = p->filp->driver_priv; |
| 1224 | − struct drm_sched_entity *entity = p->entity; | |
| 1231 | + struct amdgpu_job *leader = p->gang_leader; | |
| 1225 | 1232 | struct amdgpu_bo_list_entry *e; |
| 1226 | − struct amdgpu_job *job; | |
| 1233 | + unsigned int i; | |
| 1227 | 1234 | uint64_t seq; |
| 1228 | 1235 | int r; |
| 1229 | 1236 | |
| 1230 | − job = p->job; | |
| 1231 | − p->job = NULL; | |
| 1237 | + for (i = 0; i < p->gang_size; ++i) | |
| 1238 | + drm_sched_job_arm(&p->jobs[i]->base); | |
| 1232 | 1239 | |
| 1233 | − r = drm_sched_job_init(&job->base, entity, &fpriv->vm); | |
| 1234 | − if (r) | |
| 1235 | − goto error_unlock; | |
| 1240 | + for (i = 0; i < (p->gang_size - 1); ++i) { | |
| 1241 | + struct dma_fence *fence; | |
| 1242 | + | |
| 1243 | + fence = &p->jobs[i]->base.s_fence->scheduled; | |
| 1244 | + r = amdgpu_sync_fence(&leader->sync, fence); | |
| 1245 | + if (r) | |
| 1246 | + goto error_cleanup; | |
| 1247 | + } | |
| 1236 | 1248 | |
| 1237 | − drm_sched_job_arm(&job->base); | |
| 1249 | + if (p->gang_size > 1) { | |
| 1250 | + for (i = 0; i < p->gang_size; ++i) | |
| 1251 | + amdgpu_job_set_gang_leader(p->jobs[i], leader); | |
| 1252 | + } | |
| 1238 | 1253 | |
| 1239 | 1254 | /* No memory allocation is allowed while holding the notifier lock. |
| 1240 | 1255 | * The lock is held until amdgpu_cs_submit is finished and fence is |
| @@ -1245,6 +1260,7 @@ static int amdgpu_cs_submit(struct amdgpu_cs_parser *p, · 4 unmodified lines | ||
| 1245 | 1260 | /* If userptr are invalidated after amdgpu_cs_parser_bos(), return |
| 1246 | 1261 | * -EAGAIN, drmIoctl in libdrm will restart the amdgpu_cs_ioctl. |
| 1247 | 1262 | */ |
| 1263 | + r = 0; | |
| 1248 | 1264 | amdgpu_bo_list_for_each_userptr_entry(e, p->bo_list) { |
| 1249 | 1265 | struct amdgpu_bo *bo = ttm_to_amdgpu_bo(e->tv.bo); |
| 1250 | 1266 | |
| @@ -1252,67 +1268,96 @@ static int amdgpu_cs_submit(struct amdgpu_cs_parser *p, · 1 unmodified line | ||
| 1252 | 1268 | } |
| 1253 | 1269 | if (r) { |
| 1254 | 1270 | r = -EAGAIN; |
| 1255 | − goto error_abort; | |
| 1271 | + goto error_unlock; | |
| 1256 | 1272 | } |
| 1257 | 1273 | |
| 1258 | − p->fence = dma_fence_get(&job->base.s_fence->finished); | |
| 1274 | + p->fence = dma_fence_get(&leader->base.s_fence->finished); | |
| 1275 | + list_for_each_entry(e, &p->validated, tv.head) { | |
| 1276 | + | |
| 1277 | + /* Everybody except for the gang leader uses READ */ | |
| 1278 | + for (i = 0; i < (p->gang_size - 1); ++i) { | |
| 1279 | + dma_resv_add_fence(e->tv.bo->base.resv, | |
| 1280 | + &p->jobs[i]->base.s_fence->finished, | |
| 1281 | + DMA_RESV_USAGE_READ); | |
| 1282 | + } | |
| 1283 | + | |
| 1284 | + /* The gang leader is remembered as writer */ | |
| 1285 | + e->tv.num_shared = 0; | |
| 1286 | + } | |
| 1259 | 1287 | |
| 1260 | − seq = amdgpu_ctx_add_fence(p->ctx, entity, p->fence); | |
| 1288 | + seq = amdgpu_ctx_add_fence(p->ctx, p->entities[p->gang_size - 1], | |
| 1289 | + p->fence); | |
| 1261 | 1290 | amdgpu_cs_post_dependencies(p); |
| 1262 | 1291 | |
| 1263 | − if ((job->preamble_status & AMDGPU_PREAMBLE_IB_PRESENT) && | |
| 1292 | + if ((leader->preamble_status & AMDGPU_PREAMBLE_IB_PRESENT) && | |
| 1264 | 1293 | !p->ctx->preamble_presented) { |
| 1265 | − job->preamble_status |= AMDGPU_PREAMBLE_IB_PRESENT_FIRST; | |
| 1294 | + leader->preamble_status |= AMDGPU_PREAMBLE_IB_PRESENT_FIRST; | |
| 1266 | 1295 | p->ctx->preamble_presented = true; |
| 1267 | 1296 | } |
| 1268 | 1297 | |
| 1269 | 1298 | cs->out.handle = seq; |
| 1270 | − job->uf_sequence = seq; | |
| 1299 | + leader->uf_sequence = seq; | |
| 1271 | 1300 | |
| 1272 | − amdgpu_job_free_resources(job); | |
| 1273 | − | |
| 1274 | − trace_amdgpu_cs_ioctl(job); | |
| 1275 | 1301 | amdgpu_vm_bo_trace_cs(&fpriv->vm, &p->ticket); |
| 1276 | − drm_sched_entity_push_job(&job->base); | |
| 1302 | + for (i = 0; i < p->gang_size; ++i) { | |
| 1303 | + amdgpu_job_free_resources(p->jobs[i]); | |
| 1304 | + trace_amdgpu_cs_ioctl(p->jobs[i]); | |
| 1305 | + drm_sched_entity_push_job(&p->jobs[i]->base); | |
| 1306 | + p->jobs[i] = NULL; | |
| 1307 | + } | |
| 1277 | 1308 | |
| 1278 | 1309 | amdgpu_vm_move_to_lru_tail(p->adev, &fpriv->vm); |
| 1279 | − | |
| 1280 | − /* Make sure all BOs are remembered as writers */ | |
| 1281 | − amdgpu_bo_list_for_each_entry(e, p->bo_list) | |
| 1282 | − e->tv.num_shared = 0; | |
| 1283 | − | |
| 1284 | 1310 | ttm_eu_fence_buffer_objects(&p->ticket, &p->validated, p->fence); |
| 1311 | + | |
| 1285 | 1312 | mutex_unlock(&p->adev->notifier_lock); |
| 1286 | 1313 | mutex_unlock(&p->bo_list->bo_list_mutex); |
| 1287 | − | |
| 1288 | 1314 | return 0; |
| 1289 | 1315 | |
| 1290 | −error_abort: | |
| 1291 | − drm_sched_job_cleanup(&job->base); | |
| 1316 | +error_unlock: | |
| 1292 | 1317 | mutex_unlock(&p->adev->notifier_lock); |
| 1293 | 1318 | |
| 1294 | −error_unlock: | |
| 1295 | − amdgpu_job_free(job); | |
| 1319 | +error_cleanup: | |
| 1320 | + for (i = 0; i < p->gang_size; ++i) | |
| 1321 | + drm_sched_job_cleanup(&p->jobs[i]->base); | |
| 1296 | 1322 | return r; |
| 1297 | 1323 | } |
| 1298 | 1324 | |
| 1299 | −static void trace_amdgpu_cs_ibs(struct amdgpu_cs_parser *parser) | |
| 1325 | +/* Cleanup the parser structure */ | |
| 1326 | +static void amdgpu_cs_parser_fini(struct amdgpu_cs_parser *parser) | |
| 1300 | 1327 | { |
| 1301 | − int i; | |
| 1328 | + unsigned i; | |
| 1302 | 1329 | |
| 1303 | − if (!trace_amdgpu_cs_enabled()) | |
| 1304 | − return; | |
| 1330 | + for (i = 0; i < parser->num_post_deps; i++) { | |
| 1331 | + drm_syncobj_put(parser->post_deps[i].syncobj); | |
| 1332 | + kfree(parser->post_deps[i].chain); | |
| 1333 | + } | |
| 1334 | + kfree(parser->post_deps); | |
| 1335 | + | |
| 1336 | + dma_fence_put(parser->fence); | |
| 1337 | + | |
| 1338 | + if (parser->ctx) | |
| 1339 | + amdgpu_ctx_put(parser->ctx); | |
| 1340 | + if (parser->bo_list) | |
| 1341 | + amdgpu_bo_list_put(parser->bo_list); | |
| 1342 | + | |
| 1343 | + for (i = 0; i < parser->nchunks; i++) | |
| 1344 | + kvfree(parser->chunks[i].kdata); | |
| 1345 | + kvfree(parser->chunks); | |
| 1346 | + for (i = 0; i < parser->gang_size; ++i) { | |
| 1347 | + if (parser->jobs[i]) | |
| 1348 | + amdgpu_job_free(parser->jobs[i]); | |
| 1349 | + } | |
| 1350 | + if (parser->uf_entry.tv.bo) { | |
| 1351 | + struct amdgpu_bo *uf = ttm_to_amdgpu_bo(parser->uf_entry.tv.bo); | |
| 1305 | 1352 | |
| 1306 | − for (i = 0; i < parser->job->num_ibs; i++) | |
| 1307 | − trace_amdgpu_cs(parser, i); | |
| 1353 | + amdgpu_bo_unref(&uf); | |
| 1354 | + } | |
| 1308 | 1355 | } |
| 1309 | 1356 | |
| 1310 | 1357 | int amdgpu_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp) |
| 1311 | 1358 | { |
| 1312 | 1359 | struct amdgpu_device *adev = drm_to_adev(dev); |
| 1313 | − union drm_amdgpu_cs *cs = data; | |
| 1314 | − struct amdgpu_cs_parser parser = {}; | |
| 1315 | − bool reserved_buffers = false; | |
| 1360 | + struct amdgpu_cs_parser parser; | |
| 1316 | 1361 | int r; |
| 1317 | 1362 | |
| 1318 | 1363 | if (amdgpu_ras_intr_triggered()) |
| @@ -1321,25 +1366,20 @@ int amdgpu_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp) · 2 unmodified lines | ||
| 1321 | 1366 | if (!adev->accel_working) |
| 1322 | 1367 | return -EBUSY; |
| 1323 | 1368 | |
| 1324 | − parser.adev = adev; | |
| 1325 | − parser.filp = filp; | |
| 1326 | − | |
| 1327 | − r = amdgpu_cs_parser_init(&parser, data); | |
| 1369 | + r = amdgpu_cs_parser_init(&parser, adev, filp, data); | |
| 1328 | 1370 | if (r) { |
| 1329 | 1371 | if (printk_ratelimit()) |
| 1330 | 1372 | DRM_ERROR("Failed to initialize parser %d!\n", r); |
| 1331 | − goto out; | |
| 1373 | + return r; | |
| 1332 | 1374 | } |
| 1333 | 1375 | |
| 1334 | − r = amdgpu_cs_ib_fill(adev, &parser); | |
| 1376 | + r = amdgpu_cs_pass1(&parser, data); | |
| 1335 | 1377 | if (r) |
| 1336 | − goto out; | |
| 1378 | + goto error_fini; | |
| 1337 | 1379 | |
| 1338 | − r = amdgpu_cs_dependencies(adev, &parser); | |
| 1339 | − if (r) { | |
| 1340 | − DRM_ERROR("Failed in the dependencies handling %d!\n", r); | |
| 1341 | − goto out; | |
| 1342 | − } | |
| 1380 | + r = amdgpu_cs_pass2(&parser); | |
| 1381 | + if (r) | |
| 1382 | + goto error_fini; | |
| 1343 | 1383 | |
| 1344 | 1384 | r = amdgpu_cs_parser_bos(&parser, data); |
| 1345 | 1385 | if (r) { |
| @@ -1347,22 +1387,36 @@ int amdgpu_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp) · 1 unmodified line | ||
| 1347 | 1387 | DRM_ERROR("Not enough memory for command submission!\n"); |
| 1348 | 1388 | else if (r != -ERESTARTSYS && r != -EAGAIN) |
| 1349 | 1389 | DRM_ERROR("Failed to process the buffer list %d!\n", r); |
| 1350 | − goto out; | |
| 1390 | + goto error_fini; | |
| 1351 | 1391 | } |
| 1352 | 1392 | |
| 1353 | − reserved_buffers = true; | |
| 1393 | + r = amdgpu_cs_patch_jobs(&parser); | |
| 1394 | + if (r) | |
| 1395 | + goto error_backoff; | |
| 1396 | + | |
| 1397 | + r = amdgpu_cs_vm_handling(&parser); | |
| 1398 | + if (r) | |
| 1399 | + goto error_backoff; | |
| 1400 | + | |
| 1401 | + r = amdgpu_cs_sync_rings(&parser); | |
| 1402 | + if (r) | |
| 1403 | + goto error_backoff; | |
| 1354 | 1404 | |
| 1355 | 1405 | trace_amdgpu_cs_ibs(&parser); |
| 1356 | 1406 | |
| 1357 | − r = amdgpu_cs_vm_handling(&parser); | |
| 1407 | + r = amdgpu_cs_submit(&parser, data); | |
| 1358 | 1408 | if (r) |
| 1359 | − goto out; | |
| 1409 | + goto error_backoff; | |
| 1360 | 1410 | |
| 1361 | − r = amdgpu_cs_submit(&parser, cs); | |
| 1411 | + amdgpu_cs_parser_fini(&parser); | |
| 1412 | + return 0; | |
| 1362 | 1413 | |
| 1363 | −out: | |
| 1364 | − amdgpu_cs_parser_fini(&parser, r, reserved_buffers); | |
| 1414 | +error_backoff: | |
| 1415 | + ttm_eu_backoff_reservation(&parser.ticket, &parser.validated); | |
| 1416 | + mutex_unlock(&parser.bo_list->bo_list_mutex); | |
| 1365 | 1417 | |
| 1418 | +error_fini: | |
| 1419 | + amdgpu_cs_parser_fini(&parser); | |
| 1366 | 1420 | return r; |
| 1367 | 1421 | } |
| 1368 | 1422 | |
| @@ -27,6 +27,8 @@ · 26 unmodified lines | ||
| 27 | 27 | #include "amdgpu_bo_list.h" |
| 28 | 28 | #include "amdgpu_ring.h" |
| 29 | 29 | |
| 30 | +#define AMDGPU_CS_GANG_SIZE 4 | |
| 31 | + | |
| 30 | 32 | struct amdgpu_bo_va_mapping; |
| 31 | 33 | |
| 32 | 34 | struct amdgpu_cs_chunk { |
| @@ -50,9 +52,11 @@ struct amdgpu_cs_parser { · 17 unmodified lines | ||
| 50 | 52 | unsigned nchunks; |
| 51 | 53 | struct amdgpu_cs_chunk *chunks; |
| 52 | 54 | |
| 53 | − /* scheduler job object */ | |
| 54 | − struct amdgpu_job *job; | |
| 55 | − struct drm_sched_entity *entity; | |
| 55 | + /* scheduler job objects */ | |
| 56 | + unsigned int gang_size; | |
| 57 | + struct drm_sched_entity *entities[AMDGPU_CS_GANG_SIZE]; | |
| 58 | + struct amdgpu_job *jobs[AMDGPU_CS_GANG_SIZE]; | |
| 59 | + struct amdgpu_job *gang_leader; | |
| 56 | 60 | |
| 57 | 61 | /* buffer objects */ |
| 58 | 62 | struct ww_acquire_ctx ticket; |
| @@ -315,7 +315,6 @@ static int amdgpu_ctx_init(struct amdgpu_ctx_mgr *mgr, int32_t priority, · 314 unmodified lines | ||
| 315 | 315 | kref_init(&ctx->refcount); |
| 316 | 316 | ctx->mgr = mgr; |
| 317 | 317 | spin_lock_init(&ctx->ring_lock); |
| 318 | − mutex_init(&ctx->lock); | |
| 319 | 318 | |
| 320 | 319 | ctx->reset_counter = atomic_read(&mgr->adev->gpu_reset_counter); |
| 321 | 320 | ctx->reset_counter_query = ctx->reset_counter; |
| @@ -402,12 +401,11 @@ static void amdgpu_ctx_fini(struct kref *ref) · 80 unmodified lines | ||
| 402 | 401 | } |
| 403 | 402 | } |
| 404 | 403 | |
| 405 | − if (drm_dev_enter(&adev->ddev, &idx)) { | |
| 404 | + if (drm_dev_enter(adev_to_drm(adev), &idx)) { | |
| 406 | 405 | amdgpu_ctx_set_stable_pstate(ctx, ctx->stable_pstate); |
| 407 | 406 | drm_dev_exit(idx); |
| 408 | 407 | } |
| 409 | 408 | |
| 410 | − mutex_destroy(&ctx->lock); | |
| 411 | 409 | kfree(ctx); |
| 412 | 410 | } |
| 413 | 411 | |
| @@ -848,7 +846,7 @@ void amdgpu_ctx_mgr_init(struct amdgpu_ctx_mgr *mgr, · 434 unmodified lines | ||
| 848 | 846 | |
| 849 | 847 | mgr->adev = adev; |
| 850 | 848 | mutex_init(&mgr->lock); |
| 851 | − idr_init(&mgr->ctx_handles); | |
| 849 | + idr_init_base(&mgr->ctx_handles, 1); | |
| 852 | 850 | |
| 853 | 851 | for (i = 0; i < AMDGPU_HW_IP_NUM; ++i) |
| 854 | 852 | atomic64_set(&mgr->time_spend[i], 0); |
| @@ -53,7 +53,6 @@ struct amdgpu_ctx { · 52 unmodified lines | ||
| 53 | 53 | bool preamble_presented; |
| 54 | 54 | int32_t init_priority; |
| 55 | 55 | int32_t override_priority; |
| 56 | − struct mutex lock; | |
| 57 | 56 | atomic_t guilty; |
| 58 | 57 | unsigned long ras_counter_ce; |
| 59 | 58 | unsigned long ras_counter_ue; |
| @@ -1042,6 +1042,157 @@ err: · 1041 unmodified lines | ||
| 1042 | 1042 | return r; |
| 1043 | 1043 | } |
| 1044 | 1044 | |
| 1045 | +/** | |
| 1046 | + * amdgpu_debugfs_gfxoff_residency_read - Read GFXOFF residency | |
| 1047 | + * | |
| 1048 | + * @f: open file handle | |
| 1049 | + * @buf: User buffer to store read data in | |
| 1050 | + * @size: Number of bytes to read | |
| 1051 | + * @pos: Offset to seek to | |
| 1052 | + * | |
| 1053 | + * Read the last residency value logged. It doesn't auto update, one needs to | |
| 1054 | + * stop logging before getting the current value. | |
| 1055 | + */ | |
| 1056 | +static ssize_t amdgpu_debugfs_gfxoff_residency_read(struct file *f, char __user *buf, | |
| 1057 | + size_t size, loff_t *pos) | |
| 1058 | +{ | |
| 1059 | + struct amdgpu_device *adev = file_inode(f)->i_private; | |
| 1060 | + ssize_t result = 0; | |
| 1061 | + int r; | |
| 1062 | + | |
| 1063 | + if (size & 0x3 || *pos & 0x3) | |
| 1064 | + return -EINVAL; | |
| 1065 | + | |
| 1066 | + r = pm_runtime_get_sync(adev_to_drm(adev)->dev); | |
| 1067 | + if (r < 0) { | |
| 1068 | + pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); | |
| 1069 | + return r; | |
| 1070 | + } | |
| 1071 | + | |
| 1072 | + while (size) { | |
| 1073 | + uint32_t value; | |
| 1074 | + | |
| 1075 | + r = amdgpu_get_gfx_off_residency(adev, &value); | |
| 1076 | + if (r) | |
| 1077 | + goto out; | |
| 1078 | + | |
| 1079 | + r = put_user(value, (uint32_t *)buf); | |
| 1080 | + if (r) | |
| 1081 | + goto out; | |
| 1082 | + | |
| 1083 | + result += 4; | |
| 1084 | + buf += 4; | |
| 1085 | + *pos += 4; | |
| 1086 | + size -= 4; | |
| 1087 | + } | |
| 1088 | + | |
| 1089 | + r = result; | |
| 1090 | +out: | |
| 1091 | + pm_runtime_mark_last_busy(adev_to_drm(adev)->dev); | |
| 1092 | + pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); | |
| 1093 | + | |
| 1094 | + return r; | |
| 1095 | +} | |
| 1096 | + | |
| 1097 | +/** | |
| 1098 | + * amdgpu_debugfs_gfxoff_residency_write - Log GFXOFF Residency | |
| 1099 | + * | |
| 1100 | + * @f: open file handle | |
| 1101 | + * @buf: User buffer to write data from | |
| 1102 | + * @size: Number of bytes to write | |
| 1103 | + * @pos: Offset to seek to | |
| 1104 | + * | |
| 1105 | + * Write a 32-bit non-zero to start logging; write a 32-bit zero to stop | |
| 1106 | + */ | |
| 1107 | +static ssize_t amdgpu_debugfs_gfxoff_residency_write(struct file *f, const char __user *buf, | |
| 1108 | + size_t size, loff_t *pos) | |
| 1109 | +{ | |
| 1110 | + struct amdgpu_device *adev = file_inode(f)->i_private; | |
| 1111 | + ssize_t result = 0; | |
| 1112 | + int r; | |
| 1113 | + | |
| 1114 | + if (size & 0x3 || *pos & 0x3) | |
| 1115 | + return -EINVAL; | |
| 1116 | + | |
| 1117 | + r = pm_runtime_get_sync(adev_to_drm(adev)->dev); | |
| 1118 | + if (r < 0) { | |
| 1119 | + pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); | |
| 1120 | + return r; | |
| 1121 | + } | |
| 1122 | + | |
| 1123 | + while (size) { | |
| 1124 | + u32 value; | |
| 1125 | + | |
| 1126 | + r = get_user(value, (uint32_t *)buf); | |
| 1127 | + if (r) | |
| 1128 | + goto out; | |
| 1129 | + | |
| 1130 | + amdgpu_set_gfx_off_residency(adev, value ? true : false); | |
| 1131 | + | |
| 1132 | + result += 4; | |
| 1133 | + buf += 4; | |
| 1134 | + *pos += 4; | |
| 1135 | + size -= 4; | |
| 1136 | + } | |
| 1137 | + | |
| 1138 | + r = result; | |
| 1139 | +out: | |
| 1140 | + pm_runtime_mark_last_busy(adev_to_drm(adev)->dev); | |
| 1141 | + pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); | |
| 1142 | + | |
| 1143 | + return r; | |
| 1144 | +} | |
| 1145 | + | |
| 1146 | + | |
| 1147 | +/** | |
| 1148 | + * amdgpu_debugfs_gfxoff_count_read - Read GFXOFF entry count | |
| 1149 | + * | |
| 1150 | + * @f: open file handle | |
| 1151 | + * @buf: User buffer to store read data in | |
| 1152 | + * @size: Number of bytes to read | |
| 1153 | + * @pos: Offset to seek to | |
| 1154 | + */ | |
| 1155 | +static ssize_t amdgpu_debugfs_gfxoff_count_read(struct file *f, char __user *buf, | |
| 1156 | + size_t size, loff_t *pos) | |
| 1157 | +{ | |
| 1158 | + struct amdgpu_device *adev = file_inode(f)->i_private; | |
| 1159 | + ssize_t result = 0; | |
| 1160 | + int r; | |
| 1161 | + | |
| 1162 | + if (size & 0x3 || *pos & 0x3) | |
| 1163 | + return -EINVAL; | |
| 1164 | + | |
| 1165 | + r = pm_runtime_get_sync(adev_to_drm(adev)->dev); | |
| 1166 | + if (r < 0) { | |
| 1167 | + pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); | |
| 1168 | + return r; | |
| 1169 | + } | |
| 1170 | + | |
| 1171 | + while (size) { | |
| 1172 | + u64 value = 0; | |
| 1173 | + | |
| 1174 | + r = amdgpu_get_gfx_off_entrycount(adev, &value); | |
| 1175 | + if (r) | |
| 1176 | + goto out; | |
| 1177 | + | |
| 1178 | + r = put_user(value, (u64 *)buf); | |
| 1179 | + if (r) | |
| 1180 | + goto out; | |
| 1181 | + | |
| 1182 | + result += 4; | |
| 1183 | + buf += 4; | |
| 1184 | + *pos += 4; | |
| 1185 | + size -= 4; | |
| 1186 | + } | |
| 1187 | + | |
| 1188 | + r = result; | |
| 1189 | +out: | |
| 1190 | + pm_runtime_mark_last_busy(adev_to_drm(adev)->dev); | |
| 1191 | + pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); | |
| 1192 | + | |
| 1193 | + return r; | |
| 1194 | +} | |
| 1195 | + | |
| 1045 | 1196 | /** |
| 1046 | 1197 | * amdgpu_debugfs_gfxoff_write - Enable/disable GFXOFF |
| 1047 | 1198 | * |
| @@ -1249,6 +1400,19 @@ static const struct file_operations amdgpu_debugfs_gfxoff_status_fops = { · 201 unmodified lines | ||
| 1249 | 1400 | .llseek = default_llseek |
| 1250 | 1401 | }; |
| 1251 | 1402 | |
| 1403 | +static const struct file_operations amdgpu_debugfs_gfxoff_count_fops = { | |
| 1404 | + .owner = THIS_MODULE, | |
| 1405 | + .read = amdgpu_debugfs_gfxoff_count_read, | |
| 1406 | + .llseek = default_llseek | |
| 1407 | +}; | |
| 1408 | + | |
| 1409 | +static const struct file_operations amdgpu_debugfs_gfxoff_residency_fops = { | |
| 1410 | + .owner = THIS_MODULE, | |
| 1411 | + .read = amdgpu_debugfs_gfxoff_residency_read, | |
| 1412 | + .write = amdgpu_debugfs_gfxoff_residency_write, | |
| 1413 | + .llseek = default_llseek | |
| 1414 | +}; | |
| 1415 | + | |
| 1252 | 1416 | static const struct file_operations *debugfs_regs[] = { |
| 1253 | 1417 | &amdgpu_debugfs_regs_fops, |
| 1254 | 1418 | &amdgpu_debugfs_regs2_fops, |
| @@ -1261,6 +1425,8 @@ static const struct file_operations *debugfs_regs[] = { · 6 unmodified lines | ||
| 1261 | 1425 | &amdgpu_debugfs_gpr_fops, |
| 1262 | 1426 | &amdgpu_debugfs_gfxoff_fops, |
| 1263 | 1427 | &amdgpu_debugfs_gfxoff_status_fops, |
| 1428 | + &amdgpu_debugfs_gfxoff_count_fops, | |
| 1429 | + &amdgpu_debugfs_gfxoff_residency_fops, | |
| 1264 | 1430 | }; |
| 1265 | 1431 | |
| 1266 | 1432 | static const char *debugfs_regs_names[] = { |
| @@ -1275,6 +1441,8 @@ static const char *debugfs_regs_names[] = { · 8 unmodified lines | ||
| 1275 | 1441 | "amdgpu_gpr", |
| 1276 | 1442 | "amdgpu_gfxoff", |
| 1277 | 1443 | "amdgpu_gfxoff_status", |
| 1444 | + "amdgpu_gfxoff_count", | |
| 1445 | + "amdgpu_gfxoff_residency", | |
| 1278 | 1446 | }; |
| 1279 | 1447 | |
| 1280 | 1448 | /** |
| @@ -1786,6 +1954,8 @@ int amdgpu_debugfs_init(struct amdgpu_device *adev) · 505 unmodified lines | ||
| 1786 | 1954 | return PTR_ERR(ent); |
| 1787 | 1955 | } |
| 1788 | 1956 | |
| 1957 | + debugfs_create_u32("amdgpu_reset_level", 0600, root, &adev->amdgpu_reset_level_mask); | |
| 1958 | + | |
| 1789 | 1959 | /* Register debugfs entries for amdgpu_ttm */ |
| 1790 | 1960 | amdgpu_ttm_debugfs_init(adev); |
| 1791 | 1961 | amdgpu_debugfs_pm_init(adev); |
| @@ -2459,19 +2459,21 @@ static int amdgpu_device_ip_init(struct amdgpu_device *adev) · 2458 unmodified lines | ||
| 2459 | 2459 | */ |
| 2460 | 2460 | if (adev->gmc.xgmi.num_physical_nodes > 1) { |
| 2461 | 2461 | if (amdgpu_xgmi_add_device(adev) == 0) { |
| 2462 | − struct amdgpu_hive_info *hive = amdgpu_get_xgmi_hive(adev); | |
| 2462 | + if (!amdgpu_sriov_vf(adev)) { | |
| 2463 | + struct amdgpu_hive_info *hive = amdgpu_get_xgmi_hive(adev); | |
| 2463 | 2464 | |
| 2464 | − if (!hive->reset_domain || | |
| 2465 | − !amdgpu_reset_get_reset_domain(hive->reset_domain)) { | |
| 2466 | − r = -ENOENT; | |
| 2465 | + if (!hive->reset_domain || | |
| 2466 | + !amdgpu_reset_get_reset_domain(hive->reset_domain)) { | |
| 2467 | + r = -ENOENT; | |
| 2468 | + amdgpu_put_xgmi_hive(hive); | |
| 2469 | + goto init_failed; | |
| 2470 | + } | |
| 2471 | + | |
| 2472 | + /* Drop the early temporary reset domain we created for device */ | |
| 2473 | + amdgpu_reset_put_reset_domain(adev->reset_domain); | |
| 2474 | + adev->reset_domain = hive->reset_domain; | |
| 2467 | 2475 | amdgpu_put_xgmi_hive(hive); |
| 2468 | − goto init_failed; | |
| 2469 | 2476 | } |
| 2470 | − | |
| 2471 | − /* Drop the early temporary reset domain we created for device */ | |
| 2472 | − amdgpu_reset_put_reset_domain(adev->reset_domain); | |
| 2473 | − adev->reset_domain = hive->reset_domain; | |
| 2474 | − amdgpu_put_xgmi_hive(hive); | |
| 2475 | 2477 | } |
| 2476 | 2478 | } |
| 2477 | 2479 | |
| @@ -3510,6 +3512,7 @@ int amdgpu_device_init(struct amdgpu_device *adev, · 1032 unmodified lines | ||
| 3510 | 3512 | adev->gmc.gart_size = 512 * 1024 * 1024; |
| 3511 | 3513 | adev->accel_working = false; |
| 3512 | 3514 | adev->num_rings = 0; |
| 3515 | + RCU_INIT_POINTER(adev->gang_submit, dma_fence_get_stub()); | |
| 3513 | 3516 | adev->mman.buffer_funcs = NULL; |
| 3514 | 3517 | adev->mman.buffer_funcs_ring = NULL; |
| 3515 | 3518 | adev->vm_manager.vm_pte_funcs = NULL; |
| @@ -3588,6 +3591,8 @@ int amdgpu_device_init(struct amdgpu_device *adev, · 72 unmodified lines | ||
| 3588 | 3591 | INIT_WORK(&adev->xgmi_reset_work, amdgpu_device_xgmi_reset_func); |
| 3589 | 3592 | |
| 3590 | 3593 | adev->gfx.gfx_off_req_count = 1; |
| 3594 | + adev->gfx.gfx_off_residency = 0; | |
| 3595 | + adev->gfx.gfx_off_entrycount = 0; | |
| 3591 | 3596 | adev->pm.ac_power = power_supply_is_system_supplied() > 0; |
| 3592 | 3597 | |
| 3593 | 3598 | atomic_set(&adev->throttling_logging_enabled, 1); |
| @@ -3976,8 +3981,7 @@ void amdgpu_device_fini_hw(struct amdgpu_device *adev) · 382 unmodified lines | ||
| 3976 | 3981 | |
| 3977 | 3982 | amdgpu_gart_dummy_page_fini(adev); |
| 3978 | 3983 | |
| 3979 | − if (drm_dev_is_unplugged(adev_to_drm(adev))) | |
| 3980 | − amdgpu_device_unmap_mmio(adev); | |
| 3984 | + amdgpu_device_unmap_mmio(adev); | |
| 3981 | 3985 | |
| 3982 | 3986 | } |
| 3983 | 3987 | |
| @@ -3990,6 +3994,7 @@ void amdgpu_device_fini_sw(struct amdgpu_device *adev) · 6 unmodified lines | ||
| 3990 | 3994 | release_firmware(adev->firmware.gpu_info_fw); |
| 3991 | 3995 | adev->firmware.gpu_info_fw = NULL; |
| 3992 | 3996 | adev->accel_working = false; |
| 3997 | + dma_fence_put(rcu_dereference_protected(adev->gang_submit, true)); | |
| 3993 | 3998 | |
| 3994 | 3999 | amdgpu_reset_fini(adev); |
| 3995 | 4000 | |
| @@ -4542,14 +4547,15 @@ bool amdgpu_device_has_job_running(struct amdgpu_device *adev) · 546 unmodified lines | ||
| 4542 | 4547 | */ |
| 4543 | 4548 | bool amdgpu_device_should_recover_gpu(struct amdgpu_device *adev) |
| 4544 | 4549 | { |
| 4545 | − if (!amdgpu_device_ip_check_soft_reset(adev)) { | |
| 4546 | − dev_info(adev->dev, "Timeout, but no hardware hang detected.\n"); | |
| 4547 | − return false; | |
| 4548 | − } | |
| 4549 | 4550 | |
| 4550 | 4551 | if (amdgpu_gpu_recovery == 0) |
| 4551 | 4552 | goto disabled; |
| 4552 | 4553 | |
| 4554 | + if (!amdgpu_device_ip_check_soft_reset(adev)) { | |
| 4555 | + dev_info(adev->dev,"Timeout, but no hardware hang detected.\n"); | |
| 4556 | + return false; | |
| 4557 | + } | |
| 4558 | + | |
| 4553 | 4559 | if (amdgpu_sriov_vf(adev)) |
| 4554 | 4560 | return true; |
| 4555 | 4561 | |
| @@ -4674,7 +4680,7 @@ int amdgpu_device_pre_asic_reset(struct amdgpu_device *adev, · 118 unmodified lines | ||
| 4674 | 4680 | if (!need_full_reset) |
| 4675 | 4681 | need_full_reset = amdgpu_device_ip_need_full_reset(adev); |
| 4676 | 4682 | |
| 4677 | − if (!need_full_reset) { | |
| 4683 | + if (!need_full_reset && amdgpu_gpu_recovery) { | |
| 4678 | 4684 | amdgpu_device_ip_pre_soft_reset(adev); |
| 4679 | 4685 | r = amdgpu_device_ip_soft_reset(adev); |
| 4680 | 4686 | amdgpu_device_ip_post_soft_reset(adev); |
| @@ -4770,6 +4776,7 @@ int amdgpu_do_asic_reset(struct list_head *device_list_handle, · 89 unmodified lines | ||
| 4770 | 4776 | struct amdgpu_device *tmp_adev = NULL; |
| 4771 | 4777 | bool need_full_reset, skip_hw_reset, vram_lost = false; |
| 4772 | 4778 | int r = 0; |
| 4779 | + bool gpu_reset_for_dev_remove = 0; | |
| 4773 | 4780 | |
| 4774 | 4781 | /* Try reset handler method first */ |
| 4775 | 4782 | tmp_adev = list_first_entry(device_list_handle, struct amdgpu_device, |
| @@ -4789,6 +4796,10 @@ int amdgpu_do_asic_reset(struct list_head *device_list_handle, · 13 unmodified lines | ||
| 4789 | 4796 | test_bit(AMDGPU_NEED_FULL_RESET, &reset_context->flags); |
| 4790 | 4797 | skip_hw_reset = test_bit(AMDGPU_SKIP_HW_RESET, &reset_context->flags); |
| 4791 | 4798 | |
| 4799 | + gpu_reset_for_dev_remove = | |
| 4800 | + test_bit(AMDGPU_RESET_FOR_DEVICE_REMOVE, &reset_context->flags) && | |
| 4801 | + test_bit(AMDGPU_NEED_FULL_RESET, &reset_context->flags); | |
| 4802 | + | |
| 4792 | 4803 | /* |
| 4793 | 4804 | * ASIC reset has to be done on all XGMI hive nodes ASAP |
| 4794 | 4805 | * to allow proper links negotiation in FW (within 1 sec) |
| @@ -4833,6 +4844,18 @@ int amdgpu_do_asic_reset(struct list_head *device_list_handle, · 38 unmodified lines | ||
| 4833 | 4844 | amdgpu_ras_intr_cleared(); |
| 4834 | 4845 | } |
| 4835 | 4846 | |
| 4847 | + /* Since the mode1 reset affects base ip blocks, the | |
| 4848 | + * phase1 ip blocks need to be resumed. Otherwise there | |
| 4849 | + * will be a BIOS signature error and the psp bootloader | |
| 4850 | + * can't load kdb on the next amdgpu install. | |
| 4851 | + */ | |
| 4852 | + if (gpu_reset_for_dev_remove) { | |
| 4853 | + list_for_each_entry(tmp_adev, device_list_handle, reset_list) | |
| 4854 | + amdgpu_device_ip_resume_phase1(tmp_adev); | |
| 4855 | + | |
| 4856 | + goto end; | |
| 4857 | + } | |
| 4858 | + | |
| 4836 | 4859 | list_for_each_entry(tmp_adev, device_list_handle, reset_list) { |
| 4837 | 4860 | if (need_full_reset) { |
| 4838 | 4861 | /* post card */ |
| @@ -5072,6 +5095,7 @@ static void amdgpu_device_recheck_guilty_jobs( · 233 unmodified lines | ||
| 5072 | 5095 | |
| 5073 | 5096 | /* set guilty */ |
| 5074 | 5097 | drm_sched_increase_karma(s_job); |
| 5098 | + amdgpu_reset_prepare_hwcontext(adev, reset_context); | |
| 5075 | 5099 | retry: |
| 5076 | 5100 | /* do hw reset */ |
| 5077 | 5101 | if (amdgpu_sriov_vf(adev)) { |
| @@ -5154,6 +5178,11 @@ int amdgpu_device_gpu_recover(struct amdgpu_device *adev, · 76 unmodified lines | ||
| 5154 | 5178 | bool need_emergency_restart = false; |
| 5155 | 5179 | bool audio_suspended = false; |
| 5156 | 5180 | int tmp_vram_lost_counter; |
| 5181 | + bool gpu_reset_for_dev_remove = false; | |
| 5182 | + | |
| 5183 | + gpu_reset_for_dev_remove = | |
| 5184 | + test_bit(AMDGPU_RESET_FOR_DEVICE_REMOVE, &reset_context->flags) && | |
| 5185 | + test_bit(AMDGPU_NEED_FULL_RESET, &reset_context->flags); | |
| 5157 | 5186 | |
| 5158 | 5187 | /* |
| 5159 | 5188 | * Special case: RAS triggered and full reset isn't supported |
| @@ -5181,6 +5210,7 @@ int amdgpu_device_gpu_recover(struct amdgpu_device *adev, · 21 unmodified lines | ||
| 5181 | 5210 | |
| 5182 | 5211 | reset_context->job = job; |
| 5183 | 5212 | reset_context->hive = hive; |
| 5213 | + | |
| 5184 | 5214 | /* |
| 5185 | 5215 | * Build list of devices to reset. |
| 5186 | 5216 | * In case we are in XGMI hive mode, resort the device list |
| @@ -5188,8 +5218,11 @@ int amdgpu_device_gpu_recover(struct amdgpu_device *adev, · 1 unmodified line | ||
| 5188 | 5218 | */ |
| 5189 | 5219 | INIT_LIST_HEAD(&device_list); |
| 5190 | 5220 | if (!amdgpu_sriov_vf(adev) && (adev->gmc.xgmi.num_physical_nodes > 1)) { |
| 5191 | − list_for_each_entry(tmp_adev, &hive->device_list, gmc.xgmi.head) | |
| 5221 | + list_for_each_entry(tmp_adev, &hive->device_list, gmc.xgmi.head) { | |
| 5192 | 5222 | list_add_tail(&tmp_adev->reset_list, &device_list); |
| 5223 | + if (gpu_reset_for_dev_remove && adev->shutdown) | |
| 5224 | + tmp_adev->shutdown = true; | |
| 5225 | + } | |
| 5193 | 5226 | if (!list_is_first(&adev->reset_list, &device_list)) |
| 5194 | 5227 | list_rotate_to_front(&adev->reset_list, &device_list); |
| 5195 | 5228 | device_list_handle = &device_list; |
| @@ -5272,6 +5305,10 @@ int amdgpu_device_gpu_recover(struct amdgpu_device *adev, · 76 unmodified lines | ||
| 5272 | 5305 | |
| 5273 | 5306 | retry: /* Rest of adevs pre asic reset from XGMI hive. */ |
| 5274 | 5307 | list_for_each_entry(tmp_adev, device_list_handle, reset_list) { |
| 5308 | + if (gpu_reset_for_dev_remove) { | |
| 5309 | + /* Workaroud for ASICs need to disable SMC first */ | |
| 5310 | + amdgpu_device_smu_fini_early(tmp_adev); | |
| 5311 | + } | |
| 5275 | 5312 | r = amdgpu_device_pre_asic_reset(tmp_adev, reset_context); |
| 5276 | 5313 | /*TODO Should we stop ?*/ |
| 5277 | 5314 | if (r) { |
| @@ -5300,8 +5337,14 @@ retry: /* Rest of adevs pre asic reset from XGMI hive. */ · 22 unmodified lines | ||
| 5300 | 5337 | amdgpu_ras_resume(adev); |
| 5301 | 5338 | } else { |
| 5302 | 5339 | r = amdgpu_do_asic_reset(device_list_handle, reset_context); |
| 5303 | − if (r && r == -EAGAIN) | |
| 5340 | + if (r && r == -EAGAIN) { | |
| 5341 | + set_bit(AMDGPU_SKIP_MODE2_RESET, &reset_context->flags); | |
| 5342 | + adev->asic_reset_res = 0; | |
| 5304 | 5343 | goto retry; |
| 5344 | + } | |
| 5345 | + | |
| 5346 | + if (!r && gpu_reset_for_dev_remove) | |
| 5347 | + goto recover_end; | |
| 5305 | 5348 | } |
| 5306 | 5349 | |
| 5307 | 5350 | skip_hw_reset: |
| @@ -5375,6 +5418,7 @@ skip_sched_resume: · 67 unmodified lines | ||
| 5375 | 5418 | amdgpu_device_unset_mp1_state(tmp_adev); |
| 5376 | 5419 | } |
| 5377 | 5420 | |
| 5421 | +recover_end: | |
| 5378 | 5422 | tmp_adev = list_first_entry(device_list_handle, struct amdgpu_device, |
| 5379 | 5423 | reset_list); |
| 5380 | 5424 | amdgpu_device_unlock_reset_domain(tmp_adev->reset_domain); |
| @@ -5557,9 +5601,9 @@ bool amdgpu_device_is_peer_accessible(struct amdgpu_device *adev, · 176 unmodified lines | ||
| 5557 | 5601 | ~*peer_adev->dev->dma_mask : ~((1ULL << 32) - 1); |
| 5558 | 5602 | resource_size_t aper_limit = |
| 5559 | 5603 | adev->gmc.aper_base + adev->gmc.aper_size - 1; |
| 5560 | − bool p2p_access = !adev->gmc.xgmi.connected_to_cpu && | |
| 5561 | − !(pci_p2pdma_distance_many(adev->pdev, | |
| 5562 | − &peer_adev->dev, 1, true) < 0); | |
| 5604 | + bool p2p_access = | |
| 5605 | + !adev->gmc.xgmi.connected_to_cpu && | |
| 5606 | + !(pci_p2pdma_distance(adev->pdev, peer_adev->dev, false) < 0); | |
| 5563 | 5607 | |
| 5564 | 5608 | return pcie_p2p && p2p_access && (adev->gmc.visible_vram_size && |
| 5565 | 5609 | adev->gmc.real_vram_size == adev->gmc.visible_vram_size && |
| @@ -5733,6 +5777,7 @@ pci_ers_result_t amdgpu_pci_slot_reset(struct pci_dev *pdev) · 167 unmodified lines | ||
| 5733 | 5777 | reset_context.reset_req_dev = adev; |
| 5734 | 5778 | set_bit(AMDGPU_NEED_FULL_RESET, &reset_context.flags); |
| 5735 | 5779 | set_bit(AMDGPU_SKIP_HW_RESET, &reset_context.flags); |
| 5780 | + set_bit(AMDGPU_SKIP_MODE2_RESET, &reset_context.flags); | |
| 5736 | 5781 | |
| 5737 | 5782 | adev->no_hw_access = true; |
| 5738 | 5783 | r = amdgpu_device_pre_asic_reset(adev, &reset_context); |
| @@ -5942,3 +5987,36 @@ void amdgpu_device_pcie_port_wreg(struct amdgpu_device *adev, · 203 unmodified lines | ||
| 5942 | 5987 | (void)RREG32(data); |
| 5943 | 5988 | spin_unlock_irqrestore(&adev->pcie_idx_lock, flags); |
| 5944 | 5989 | } |
| 5990 | + | |
| 5991 | +/** | |
| 5992 | + * amdgpu_device_switch_gang - switch to a new gang | |
| 5993 | + * @adev: amdgpu_device pointer | |
| 5994 | + * @gang: the gang to switch to | |
| 5995 | + * | |
| 5996 | + * Try to switch to a new gang. | |
| 5997 | + * Returns: NULL if we switched to the new gang or a reference to the current | |
| 5998 | + * gang leader. | |
| 5999 | + */ | |
| 6000 | +struct dma_fence *amdgpu_device_switch_gang(struct amdgpu_device *adev, | |
| 6001 | + struct dma_fence *gang) | |
| 6002 | +{ | |
| 6003 | + struct dma_fence *old = NULL; | |
| 6004 | + | |
| 6005 | + do { | |
| 6006 | + dma_fence_put(old); | |
| 6007 | + rcu_read_lock(); | |
| 6008 | + old = dma_fence_get_rcu_safe(&adev->gang_submit); | |
| 6009 | + rcu_read_unlock(); | |
| 6010 | + | |
| 6011 | + if (old == gang) | |
| 6012 | + break; | |
| 6013 | + | |
| 6014 | + if (!dma_fence_is_signaled(old)) | |
| 6015 | + return old; | |
| 6016 | + | |
| 6017 | + } while (cmpxchg((struct dma_fence __force **)&adev->gang_submit, | |
| 6018 | + old, gang) != old); | |
| 6019 | + | |
| 6020 | + dma_fence_put(old); | |
| 6021 | + return NULL; | |
| 6022 | +} | |
| @@ -229,7 +229,7 @@ static int amdgpu_discovery_read_binary_from_file(struct amdgpu_device *adev, ui · 228 unmodified lines | ||
| 229 | 229 | return r; |
| 230 | 230 | } |
| 231 | 231 | |
| 232 | − memcpy((u8 *)binary, (u8 *)fw->data, adev->mman.discovery_tmr_size); | |
| 232 | + memcpy((u8 *)binary, (u8 *)fw->data, fw->size); | |
| 233 | 233 | release_firmware(fw); |
| 234 | 234 | |
| 235 | 235 | return 0; |
| @@ -1506,6 +1506,7 @@ static int amdgpu_discovery_set_common_ip_blocks(struct amdgpu_device *adev) · 1270 unmodified lines | ||
| 1506 | 1506 | case IP_VERSION(11, 0, 0): |
| 1507 | 1507 | case IP_VERSION(11, 0, 1): |
| 1508 | 1508 | case IP_VERSION(11, 0, 2): |
| 1509 | + case IP_VERSION(11, 0, 3): | |
| 1509 | 1510 | amdgpu_device_ip_block_add(adev, &soc21_common_ip_block); |
| 1510 | 1511 | break; |
| 1511 | 1512 | default: |
| @@ -1549,6 +1550,7 @@ static int amdgpu_discovery_set_gmc_ip_blocks(struct amdgpu_device *adev) · 37 unmodified lines | ||
| 1549 | 1550 | case IP_VERSION(11, 0, 0): |
| 1550 | 1551 | case IP_VERSION(11, 0, 1): |
| 1551 | 1552 | case IP_VERSION(11, 0, 2): |
| 1553 | + case IP_VERSION(11, 0, 3): | |
| 1552 | 1554 | amdgpu_device_ip_block_add(adev, &gmc_v11_0_ip_block); |
| 1553 | 1555 | break; |
| 1554 | 1556 | default: |
| @@ -1633,6 +1635,7 @@ static int amdgpu_discovery_set_psp_ip_blocks(struct amdgpu_device *adev) · 78 unmodified lines | ||
| 1633 | 1635 | case IP_VERSION(13, 0, 5): |
| 1634 | 1636 | case IP_VERSION(13, 0, 7): |
| 1635 | 1637 | case IP_VERSION(13, 0, 8): |
| 1638 | + case IP_VERSION(13, 0, 10): | |
| 1636 | 1639 | amdgpu_device_ip_block_add(adev, &psp_v13_0_ip_block); |
| 1637 | 1640 | break; |
| 1638 | 1641 | case IP_VERSION(13, 0, 4): |
| @@ -1682,6 +1685,7 @@ static int amdgpu_discovery_set_smu_ip_blocks(struct amdgpu_device *adev) · 43 unmodified lines | ||
| 1682 | 1685 | case IP_VERSION(13, 0, 5): |
| 1683 | 1686 | case IP_VERSION(13, 0, 7): |
| 1684 | 1687 | case IP_VERSION(13, 0, 8): |
| 1688 | + case IP_VERSION(13, 0, 10): | |
| 1685 | 1689 | amdgpu_device_ip_block_add(adev, &smu_v13_0_ip_block); |
| 1686 | 1690 | break; |
| 1687 | 1691 | default: |
| @@ -1780,6 +1784,7 @@ static int amdgpu_discovery_set_gc_ip_blocks(struct amdgpu_device *adev) · 92 unmodified lines | ||
| 1780 | 1784 | case IP_VERSION(11, 0, 0): |
| 1781 | 1785 | case IP_VERSION(11, 0, 1): |
| 1782 | 1786 | case IP_VERSION(11, 0, 2): |
| 1787 | + case IP_VERSION(11, 0, 3): | |
| 1783 | 1788 | amdgpu_device_ip_block_add(adev, &gfx_v11_0_ip_block); |
| 1784 | 1789 | break; |
| 1785 | 1790 | default: |
| @@ -1823,6 +1828,7 @@ static int amdgpu_discovery_set_sdma_ip_blocks(struct amdgpu_device *adev) · 37 unmodified lines | ||
| 1823 | 1828 | case IP_VERSION(6, 0, 0): |
| 1824 | 1829 | case IP_VERSION(6, 0, 1): |
| 1825 | 1830 | case IP_VERSION(6, 0, 2): |
| 1831 | + case IP_VERSION(6, 0, 3): | |
| 1826 | 1832 | amdgpu_device_ip_block_add(adev, &sdma_v6_0_ip_block); |
| 1827 | 1833 | break; |
| 1828 | 1834 | default: |
| @@ -1903,7 +1909,8 @@ static int amdgpu_discovery_set_mm_ip_blocks(struct amdgpu_device *adev) · 74 unmodified lines | ||
| 1903 | 1909 | case IP_VERSION(4, 0, 2): |
| 1904 | 1910 | case IP_VERSION(4, 0, 4): |
| 1905 | 1911 | amdgpu_device_ip_block_add(adev, &vcn_v4_0_ip_block); |
| 1906 | − amdgpu_device_ip_block_add(adev, &jpeg_v4_0_ip_block); | |
| 1912 | + if (!amdgpu_sriov_vf(adev)) | |
| 1913 | + amdgpu_device_ip_block_add(adev, &jpeg_v4_0_ip_block); | |
| 1907 | 1914 | break; |
| 1908 | 1915 | default: |
| 1909 | 1916 | dev_err(adev->dev, |
| @@ -1940,6 +1947,7 @@ static int amdgpu_discovery_set_mes_ip_blocks(struct amdgpu_device *adev) · 30 unmodified lines | ||
| 1940 | 1947 | case IP_VERSION(11, 0, 0): |
| 1941 | 1948 | case IP_VERSION(11, 0, 1): |
| 1942 | 1949 | case IP_VERSION(11, 0, 2): |
| 1950 | + case IP_VERSION(11, 0, 3): | |
| 1943 | 1951 | amdgpu_device_ip_block_add(adev, &mes_v11_0_ip_block); |
| 1944 | 1952 | adev->enable_mes = true; |
| 1945 | 1953 | adev->enable_mes_kiq = true; |
| @@ -2165,6 +2173,7 @@ int amdgpu_discovery_set_ip_blocks(struct amdgpu_device *adev) · 219 unmodified lines | ||
| 2165 | 2173 | break; |
| 2166 | 2174 | case IP_VERSION(11, 0, 0): |
| 2167 | 2175 | case IP_VERSION(11, 0, 2): |
| 2176 | + case IP_VERSION(11, 0, 3): | |
| 2168 | 2177 | adev->family = AMDGPU_FAMILY_GC_11_0_0; |
| 2169 | 2178 | break; |
| 2170 | 2179 | case IP_VERSION(11, 0, 1): |
| @@ -2234,7 +2243,10 @@ int amdgpu_discovery_set_ip_blocks(struct amdgpu_device *adev) · 63 unmodified lines | ||
| 2234 | 2243 | break; |
| 2235 | 2244 | case IP_VERSION(4, 3, 0): |
| 2236 | 2245 | case IP_VERSION(4, 3, 1): |
| 2237 | − adev->nbio.funcs = &nbio_v4_3_funcs; | |
| 2246 | + if (amdgpu_sriov_vf(adev)) | |
| 2247 | + adev->nbio.funcs = &nbio_v4_3_sriov_funcs; | |
| 2248 | + else | |
| 2249 | + adev->nbio.funcs = &nbio_v4_3_funcs; | |
| 2238 | 2250 | adev->nbio.hdp_flush_reg = &nbio_v4_3_hdp_flush_reg; |
| 2239 | 2251 | break; |
| 2240 | 2252 | case IP_VERSION(7, 7, 0): |
| @@ -2332,6 +2344,7 @@ int amdgpu_discovery_set_ip_blocks(struct amdgpu_device *adev) · 91 unmodified lines | ||
| 2332 | 2344 | case IP_VERSION(6, 0, 0): |
| 2333 | 2345 | case IP_VERSION(6, 0, 1): |
| 2334 | 2346 | case IP_VERSION(6, 0, 2): |
| 2347 | + case IP_VERSION(6, 0, 3): | |
| 2335 | 2348 | adev->lsdma.funcs = &lsdma_v6_0_funcs; |
| 2336 | 2349 | break; |
| 2337 | 2350 | default: |
| @@ -58,7 +58,7 @@ static int amdgpu_dma_buf_attach(struct dma_buf *dmabuf, · 57 unmodified lines | ||
| 58 | 58 | struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev); |
| 59 | 59 | int r; |
| 60 | 60 | |
| 61 | − if (pci_p2pdma_distance_many(adev->pdev, &attach->dev, 1, true) < 0) | |
| 61 | + if (pci_p2pdma_distance(adev->pdev, attach->dev, false) < 0) | |
| 62 | 62 | attach->peer2peer = false; |
| 63 | 63 | |
| 64 | 64 | r = pm_runtime_get_sync(adev_to_drm(adev)->dev); |
| @@ -102,9 +102,10 @@ · 101 unmodified lines | ||
| 102 | 102 | * - 3.46.0 - To enable hot plug amdgpu tests in libdrm |
| 103 | 103 | * - 3.47.0 - Add AMDGPU_GEM_CREATE_DISCARDABLE and AMDGPU_VM_NOALLOC flags |
| 104 | 104 | * - 3.48.0 - Add IP discovery version info to HW INFO |
| 105 | + * 3.49.0 - Add gang submit into CS IOCTL | |
| 105 | 106 | */ |
| 106 | 107 | #define KMS_DRIVER_MAJOR 3 |
| 107 | −#define KMS_DRIVER_MINOR 48 | |
| 108 | +#define KMS_DRIVER_MINOR 49 | |
| 108 | 109 | #define KMS_DRIVER_PATCHLEVEL 0 |
| 109 | 110 | |
| 110 | 111 | int amdgpu_vram_limit; |
| @@ -2181,15 +2182,46 @@ amdgpu_pci_remove(struct pci_dev *pdev) · 2070 unmodified lines | ||
| 2181 | 2182 | struct drm_device *dev = pci_get_drvdata(pdev); |
| 2182 | 2183 | struct amdgpu_device *adev = drm_to_adev(dev); |
| 2183 | 2184 | |
| 2184 | − drm_dev_unplug(dev); | |
| 2185 | − | |
| 2186 | 2185 | if (adev->pm.rpm_mode != AMDGPU_RUNPM_NONE) { |
| 2187 | 2186 | pm_runtime_get_sync(dev->dev); |
| 2188 | 2187 | pm_runtime_forbid(dev->dev); |
| 2189 | 2188 | } |
| 2190 | 2189 | |
| 2190 | + if (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(13, 0, 2)) { | |
| 2191 | + bool need_to_reset_gpu = false; | |
| 2192 | + | |
| 2193 | + if (adev->gmc.xgmi.num_physical_nodes > 1) { | |
| 2194 | + struct amdgpu_hive_info *hive; | |
| 2195 | + | |
| 2196 | + hive = amdgpu_get_xgmi_hive(adev); | |
| 2197 | + if (hive->device_remove_count == 0) | |
| 2198 | + need_to_reset_gpu = true; | |
| 2199 | + hive->device_remove_count++; | |
| 2200 | + amdgpu_put_xgmi_hive(hive); | |
| 2201 | + } else { | |
| 2202 | + need_to_reset_gpu = true; | |
| 2203 | + } | |
| 2204 | + | |
| 2205 | + /* Workaround for ASICs need to reset SMU. | |
| 2206 | + * Called only when the first device is removed. | |
| 2207 | + */ | |
| 2208 | + if (need_to_reset_gpu) { | |
| 2209 | + struct amdgpu_reset_context reset_context; | |
| 2210 | + | |
| 2211 | + adev->shutdown = true; | |
| 2212 | + memset(&reset_context, 0, sizeof(reset_context)); | |
| 2213 | + reset_context.method = AMD_RESET_METHOD_NONE; | |
| 2214 | + reset_context.reset_req_dev = adev; | |
| 2215 | + set_bit(AMDGPU_NEED_FULL_RESET, &reset_context.flags); | |
| 2216 | + set_bit(AMDGPU_RESET_FOR_DEVICE_REMOVE, &reset_context.flags); | |
| 2217 | + amdgpu_device_gpu_recover(adev, NULL, &reset_context); | |
| 2218 | + } | |
| 2219 | + } | |
| 2220 | + | |
| 2191 | 2221 | amdgpu_driver_unload_kms(dev); |
| 2192 | 2222 | |
| 2223 | + drm_dev_unplug(dev); | |
| 2224 | + | |
| 2193 | 2225 | /* |
| 2194 | 2226 | * Flush any in flight DMA operations from device. |
| 2195 | 2227 | * Clear the Bus Master Enable bit and then wait on the PCIe Device |
| @@ -2563,8 +2595,11 @@ static int amdgpu_pmops_runtime_resume(struct device *dev) · 367 unmodified lines | ||
| 2563 | 2595 | amdgpu_device_baco_exit(drm_dev); |
| 2564 | 2596 | } |
| 2565 | 2597 | ret = amdgpu_device_resume(drm_dev, false); |
| 2566 | − if (ret) | |
| 2598 | + if (ret) { | |
| 2599 | + if (amdgpu_device_supports_px(drm_dev)) | |
| 2600 | + pci_disable_device(pdev); | |
| 2567 | 2601 | return ret; |
| 2602 | + } | |
| 2568 | 2603 | |
| 2569 | 2604 | if (amdgpu_device_supports_px(drm_dev)) |
| 2570 | 2605 | drm_dev->switch_power_state = DRM_SWITCH_POWER_ON; |
| @@ -23,6 +23,7 @@ · 22 unmodified lines | ||
| 23 | 23 | * |
| 24 | 24 | */ |
| 25 | 25 | |
| 26 | +#include <linux/firmware.h> | |
| 26 | 27 | #include "amdgpu.h" |
| 27 | 28 | #include "amdgpu_gfx.h" |
| 28 | 29 | #include "amdgpu_rlc.h" |
| @@ -477,7 +478,7 @@ int amdgpu_gfx_disable_kcq(struct amdgpu_device *adev) · 448 unmodified lines | ||
| 477 | 478 | kiq->pmf->kiq_unmap_queues(kiq_ring, &adev->gfx.compute_ring[i], |
| 478 | 479 | RESET_QUEUES, 0, 0); |
| 479 | 480 | |
| 480 | − if (adev->gfx.kiq.ring.sched.ready) | |
| 481 | + if (adev->gfx.kiq.ring.sched.ready && !adev->job_hang) | |
| 481 | 482 | r = amdgpu_ring_test_helper(kiq_ring); |
| 482 | 483 | spin_unlock(&adev->gfx.kiq.ring_lock); |
| 483 | 484 | |
| @@ -610,6 +611,45 @@ unlock: · 126 unmodified lines | ||
| 610 | 611 | mutex_unlock(&adev->gfx.gfx_off_mutex); |
| 611 | 612 | } |
| 612 | 613 | |
| 614 | +int amdgpu_set_gfx_off_residency(struct amdgpu_device *adev, bool value) | |
| 615 | +{ | |
| 616 | + int r = 0; | |
| 617 | + | |
| 618 | + mutex_lock(&adev->gfx.gfx_off_mutex); | |
| 619 | + | |
| 620 | + r = amdgpu_dpm_set_residency_gfxoff(adev, value); | |
| 621 | + | |
| 622 | + mutex_unlock(&adev->gfx.gfx_off_mutex); | |
| 623 | + | |
| 624 | + return r; | |
| 625 | +} | |
| 626 | + | |
| 627 | +int amdgpu_get_gfx_off_residency(struct amdgpu_device *adev, u32 *value) | |
| 628 | +{ | |
| 629 | + int r = 0; | |
| 630 | + | |
| 631 | + mutex_lock(&adev->gfx.gfx_off_mutex); | |
| 632 | + | |
| 633 | + r = amdgpu_dpm_get_residency_gfxoff(adev, value); | |
| 634 | + | |
| 635 | + mutex_unlock(&adev->gfx.gfx_off_mutex); | |
| 636 | + | |
| 637 | + return r; | |
| 638 | +} | |
| 639 | + | |
| 640 | +int amdgpu_get_gfx_off_entrycount(struct amdgpu_device *adev, u64 *value) | |
| 641 | +{ | |
| 642 | + int r = 0; | |
| 643 | + | |
| 644 | + mutex_lock(&adev->gfx.gfx_off_mutex); | |
| 645 | + | |
| 646 | + r = amdgpu_dpm_get_entrycount_gfxoff(adev, value); | |
| 647 | + | |
| 648 | + mutex_unlock(&adev->gfx.gfx_off_mutex); | |
| 649 | + | |
| 650 | + return r; | |
| 651 | +} | |
| 652 | + | |
| 613 | 653 | int amdgpu_get_gfx_off_status(struct amdgpu_device *adev, uint32_t *value) |
| 614 | 654 | { |
| 615 | 655 | |
| @@ -826,3 +866,142 @@ int amdgpu_gfx_get_num_kcq(struct amdgpu_device *adev) · 210 unmodified lines | ||
| 826 | 866 | } |
| 827 | 867 | return amdgpu_num_kcq; |
| 828 | 868 | } |
| 869 | + | |
| 870 | +void amdgpu_gfx_cp_init_microcode(struct amdgpu_device *adev, | |
| 871 | + uint32_t ucode_id) | |
| 872 | +{ | |
| 873 | + const struct gfx_firmware_header_v1_0 *cp_hdr; | |
| 874 | + const struct gfx_firmware_header_v2_0 *cp_hdr_v2_0; | |
| 875 | + struct amdgpu_firmware_info *info = NULL; | |
| 876 | + const struct firmware *ucode_fw; | |
| 877 | + unsigned int fw_size; | |
| 878 | + | |
| 879 | + switch (ucode_id) { | |
| 880 | + case AMDGPU_UCODE_ID_CP_PFP: | |
| 881 | + cp_hdr = (const struct gfx_firmware_header_v1_0 *) | |
| 882 | + adev->gfx.pfp_fw->data; | |
| 883 | + adev->gfx.pfp_fw_version = | |
| 884 | + le32_to_cpu(cp_hdr->header.ucode_version); | |
| 885 | + adev->gfx.pfp_feature_version = | |
| 886 | + le32_to_cpu(cp_hdr->ucode_feature_version); | |
| 887 | + ucode_fw = adev->gfx.pfp_fw; | |
| 888 | + fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes); | |
| 889 | + break; | |
| 890 | + case AMDGPU_UCODE_ID_CP_RS64_PFP: | |
| 891 | + cp_hdr_v2_0 = (const struct gfx_firmware_header_v2_0 *) | |
| 892 | + adev->gfx.pfp_fw->data; | |
| 893 | + adev->gfx.pfp_fw_version = | |
| 894 | + le32_to_cpu(cp_hdr_v2_0->header.ucode_version); | |
| 895 | + adev->gfx.pfp_feature_version = | |
| 896 | + le32_to_cpu(cp_hdr_v2_0->ucode_feature_version); | |
| 897 | + ucode_fw = adev->gfx.pfp_fw; | |
| 898 | + fw_size = le32_to_cpu(cp_hdr_v2_0->ucode_size_bytes); | |
| 899 | + break; | |
| 900 | + case AMDGPU_UCODE_ID_CP_RS64_PFP_P0_STACK: | |
| 901 | + case AMDGPU_UCODE_ID_CP_RS64_PFP_P1_STACK: | |
| 902 | + cp_hdr_v2_0 = (const struct gfx_firmware_header_v2_0 *) | |
| 903 | + adev->gfx.pfp_fw->data; | |
| 904 | + ucode_fw = adev->gfx.pfp_fw; | |
| 905 | + fw_size = le32_to_cpu(cp_hdr_v2_0->data_size_bytes); | |
| 906 | + break; | |
| 907 | + case AMDGPU_UCODE_ID_CP_ME: | |
| 908 | + cp_hdr = (const struct gfx_firmware_header_v1_0 *) | |
| 909 | + adev->gfx.me_fw->data; | |
| 910 | + adev->gfx.me_fw_version = | |
| 911 | + le32_to_cpu(cp_hdr->header.ucode_version); | |
| 912 | + adev->gfx.me_feature_version = | |
| 913 | + le32_to_cpu(cp_hdr->ucode_feature_version); | |
| 914 | + ucode_fw = adev->gfx.me_fw; | |
| 915 | + fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes); | |
| 916 | + break; | |
| 917 | + case AMDGPU_UCODE_ID_CP_RS64_ME: | |
| 918 | + cp_hdr_v2_0 = (const struct gfx_firmware_header_v2_0 *) | |
| 919 | + adev->gfx.me_fw->data; | |
| 920 | + adev->gfx.me_fw_version = | |
| 921 | + le32_to_cpu(cp_hdr_v2_0->header.ucode_version); | |
| 922 | + adev->gfx.me_feature_version = | |
| 923 | + le32_to_cpu(cp_hdr_v2_0->ucode_feature_version); | |
| 924 | + ucode_fw = adev->gfx.me_fw; | |
| 925 | + fw_size = le32_to_cpu(cp_hdr_v2_0->ucode_size_bytes); | |
| 926 | + break; | |
| 927 | + case AMDGPU_UCODE_ID_CP_RS64_ME_P0_STACK: | |
| 928 | + case AMDGPU_UCODE_ID_CP_RS64_ME_P1_STACK: | |
| 929 | + cp_hdr_v2_0 = (const struct gfx_firmware_header_v2_0 *) | |
| 930 | + adev->gfx.me_fw->data; | |
| 931 | + ucode_fw = adev->gfx.me_fw; | |
| 932 | + fw_size = le32_to_cpu(cp_hdr_v2_0->data_size_bytes); | |
| 933 | + break; | |
| 934 | + case AMDGPU_UCODE_ID_CP_CE: | |
| 935 | + cp_hdr = (const struct gfx_firmware_header_v1_0 *) | |
| 936 | + adev->gfx.ce_fw->data; | |
| 937 | + adev->gfx.ce_fw_version = | |
| 938 | + le32_to_cpu(cp_hdr->header.ucode_version); | |
| 939 | + adev->gfx.ce_feature_version = | |
| 940 | + le32_to_cpu(cp_hdr->ucode_feature_version); | |
| 941 | + ucode_fw = adev->gfx.ce_fw; | |
| 942 | + fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes); | |
| 943 | + break; | |
| 944 | + case AMDGPU_UCODE_ID_CP_MEC1: | |
| 945 | + cp_hdr = (const struct gfx_firmware_header_v1_0 *) | |
| 946 | + adev->gfx.mec_fw->data; | |
| 947 | + adev->gfx.mec_fw_version = | |
| 948 | + le32_to_cpu(cp_hdr->header.ucode_version); | |
| 949 | + adev->gfx.mec_feature_version = | |
| 950 | + le32_to_cpu(cp_hdr->ucode_feature_version); | |
| 951 | + ucode_fw = adev->gfx.mec_fw; | |
| 952 | + fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes) - | |
| 953 | + le32_to_cpu(cp_hdr->jt_size) * 4; | |
| 954 | + break; | |
| 955 | + case AMDGPU_UCODE_ID_CP_MEC1_JT: | |
| 956 | + cp_hdr = (const struct gfx_firmware_header_v1_0 *) | |
| 957 | + adev->gfx.mec_fw->data; | |
| 958 | + ucode_fw = adev->gfx.mec_fw; | |
| 959 | + fw_size = le32_to_cpu(cp_hdr->jt_size) * 4; | |
| 960 | + break; | |
| 961 | + case AMDGPU_UCODE_ID_CP_MEC2: | |
| 962 | + cp_hdr = (const struct gfx_firmware_header_v1_0 *) | |
| 963 | + adev->gfx.mec2_fw->data; | |
| 964 | + adev->gfx.mec2_fw_version = | |
| 965 | + le32_to_cpu(cp_hdr->header.ucode_version); | |
| 966 | + adev->gfx.mec2_feature_version = | |
| 967 | + le32_to_cpu(cp_hdr->ucode_feature_version); | |
| 968 | + ucode_fw = adev->gfx.mec2_fw; | |
| 969 | + fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes) - | |
| 970 | + le32_to_cpu(cp_hdr->jt_size) * 4; | |
| 971 | + break; | |
| 972 | + case AMDGPU_UCODE_ID_CP_MEC2_JT: | |
| 973 | + cp_hdr = (const struct gfx_firmware_header_v1_0 *) | |
| 974 | + adev->gfx.mec2_fw->data; | |
| 975 | + ucode_fw = adev->gfx.mec2_fw; | |
| 976 | + fw_size = le32_to_cpu(cp_hdr->jt_size) * 4; | |
| 977 | + break; | |
| 978 | + case AMDGPU_UCODE_ID_CP_RS64_MEC: | |
| 979 | + cp_hdr_v2_0 = (const struct gfx_firmware_header_v2_0 *) | |
| 980 | + adev->gfx.mec_fw->data; | |
| 981 | + adev->gfx.mec_fw_version = | |
| 982 | + le32_to_cpu(cp_hdr_v2_0->header.ucode_version); | |
| 983 | + adev->gfx.mec_feature_version = | |
| 984 | + le32_to_cpu(cp_hdr_v2_0->ucode_feature_version); | |
| 985 | + ucode_fw = adev->gfx.mec_fw; | |
| 986 | + fw_size = le32_to_cpu(cp_hdr_v2_0->ucode_size_bytes); | |
| 987 | + break; | |
| 988 | + case AMDGPU_UCODE_ID_CP_RS64_MEC_P0_STACK: | |
| 989 | + case AMDGPU_UCODE_ID_CP_RS64_MEC_P1_STACK: | |
| 990 | + case AMDGPU_UCODE_ID_CP_RS64_MEC_P2_STACK: | |
| 991 | + case AMDGPU_UCODE_ID_CP_RS64_MEC_P3_STACK: | |
| 992 | + cp_hdr_v2_0 = (const struct gfx_firmware_header_v2_0 *) | |
| 993 | + adev->gfx.mec_fw->data; | |
| 994 | + ucode_fw = adev->gfx.mec_fw; | |
| 995 | + fw_size = le32_to_cpu(cp_hdr_v2_0->data_size_bytes); | |
| 996 | + break; | |
| 997 | + default: | |
| 998 | + break; | |
| 999 | + } | |
| 1000 | + | |
| 1001 | + if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { | |
| 1002 | + info = &adev->firmware.ucode[ucode_id]; | |
| 1003 | + info->ucode_id = ucode_id; | |
| 1004 | + info->fw = ucode_fw; | |
| 1005 | + adev->firmware.fw_size += ALIGN(fw_size, PAGE_SIZE); | |
| 1006 | + } | |
| 1007 | +} | |
| @@ -336,10 +336,12 @@ struct amdgpu_gfx { · 335 unmodified lines | ||
| 336 | 336 | uint32_t srbm_soft_reset; |
| 337 | 337 | |
| 338 | 338 | /* gfx off */ |
| 339 | − bool gfx_off_state; /* true: enabled, false: disabled */ | |
| 340 | − struct mutex gfx_off_mutex; | |
| 341 | − uint32_t gfx_off_req_count; /* default 1, enable gfx off: dec 1, disable gfx off: add 1 */ | |
| 342 | − struct delayed_work gfx_off_delay_work; | |
| 339 | + bool gfx_off_state; /* true: enabled, false: disabled */ | |
| 340 | + struct mutex gfx_off_mutex; /* mutex to change gfxoff state */ | |
| 341 | + uint32_t gfx_off_req_count; /* default 1, enable gfx off: dec 1, disable gfx off: add 1 */ | |
| 342 | + struct delayed_work gfx_off_delay_work; /* async work to set gfx block off */ | |
| 343 | + uint32_t gfx_off_residency; /* last logged residency */ | |
| 344 | + uint64_t gfx_off_entrycount; /* count of times GPU has get into GFXOFF state */ | |
| 343 | 345 | |
| 344 | 346 | /* pipe reservation */ |
| 345 | 347 | struct mutex pipe_reserve_mutex; |
| @@ -411,6 +413,10 @@ bool amdgpu_gfx_is_me_queue_enabled(struct amdgpu_device *adev, int me, · 65 unmodified lines | ||
| 411 | 413 | void amdgpu_gfx_off_ctrl(struct amdgpu_device *adev, bool enable); |
| 412 | 414 | int amdgpu_get_gfx_off_status(struct amdgpu_device *adev, uint32_t *value); |
| 413 | 415 | int amdgpu_gfx_ras_late_init(struct amdgpu_device *adev, struct ras_common_if *ras_block); |
| 416 | +void amdgpu_gfx_ras_fini(struct amdgpu_device *adev); | |
| 417 | +int amdgpu_get_gfx_off_entrycount(struct amdgpu_device *adev, u64 *value); | |
| 418 | +int amdgpu_get_gfx_off_residency(struct amdgpu_device *adev, u32 *residency); | |
| 419 | +int amdgpu_set_gfx_off_residency(struct amdgpu_device *adev, bool value); | |
| 414 | 420 | int amdgpu_gfx_process_ras_data_cb(struct amdgpu_device *adev, |
| 415 | 421 | void *err_data, |
| 416 | 422 | struct amdgpu_iv_entry *entry); |
| @@ -420,4 +426,6 @@ int amdgpu_gfx_cp_ecc_error_irq(struct amdgpu_device *adev, · 3 unmodified lines | ||
| 420 | 426 | uint32_t amdgpu_kiq_rreg(struct amdgpu_device *adev, uint32_t reg); |
| 421 | 427 | void amdgpu_kiq_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v); |
| 422 | 428 | int amdgpu_gfx_get_num_kcq(struct amdgpu_device *adev); |
| 429 | +void amdgpu_gfx_cp_init_microcode(struct amdgpu_device *adev, uint32_t ucode_id); | |
| 430 | + | |
| 423 | 431 | #endif |
| @@ -35,6 +35,9 @@ struct amdgpu_gfxhub_funcs { · 34 unmodified lines | ||
| 35 | 35 | void (*init)(struct amdgpu_device *adev); |
| 36 | 36 | int (*get_xgmi_info)(struct amdgpu_device *adev); |
| 37 | 37 | void (*utcl2_harvest)(struct amdgpu_device *adev); |
| 38 | + void (*mode2_save_regs)(struct amdgpu_device *adev); | |
| 39 | + void (*mode2_restore_regs)(struct amdgpu_device *adev); | |
| 40 | + void (*halt)(struct amdgpu_device *adev); | |
| 38 | 41 | }; |
| 39 | 42 | |
| 40 | 43 | struct amdgpu_gfxhub { |
| @@ -572,45 +572,15 @@ void amdgpu_gmc_tmz_set(struct amdgpu_device *adev) · 571 unmodified lines | ||
| 572 | 572 | void amdgpu_gmc_noretry_set(struct amdgpu_device *adev) |
| 573 | 573 | { |
| 574 | 574 | struct amdgpu_gmc *gmc = &adev->gmc; |
| 575 | − | |
| 576 | − switch (adev->ip_versions[GC_HWIP][0]) { | |
| 577 | − case IP_VERSION(9, 0, 1): | |
| 578 | − case IP_VERSION(9, 3, 0): | |
| 579 | − case IP_VERSION(9, 4, 0): | |
| 580 | − case IP_VERSION(9, 4, 1): | |
| 581 | − case IP_VERSION(9, 4, 2): | |
| 582 | − case IP_VERSION(10, 3, 3): | |
| 583 | − case IP_VERSION(10, 3, 4): | |
| 584 | − case IP_VERSION(10, 3, 5): | |
| 585 | − case IP_VERSION(10, 3, 6): | |
| 586 | − case IP_VERSION(10, 3, 7): | |
| 587 | − /* | |
| 588 | − * noretry = 0 will cause kfd page fault tests fail | |
| 589 | − * for some ASICs, so set default to 1 for these ASICs. | |
| 590 | − */ | |
| 591 | − if (amdgpu_noretry == -1) | |
| 592 | − gmc->noretry = 1; | |
| 593 | − else | |
| 594 | − gmc->noretry = amdgpu_noretry; | |
| 595 | − break; | |
| 596 | − default: | |
| 597 | − /* Raven currently has issues with noretry | |
| 598 | − * regardless of what we decide for other | |
| 599 | − * asics, we should leave raven with | |
| 600 | − * noretry = 0 until we root cause the | |
| 601 | − * issues. | |
| 602 | − * | |
| 603 | − * default this to 0 for now, but we may want | |
| 604 | − * to change this in the future for certain | |
| 605 | − * GPUs as it can increase performance in | |
| 606 | − * certain cases. | |
| 607 | − */ | |
| 608 | − if (amdgpu_noretry == -1) | |
| 609 | − gmc->noretry = 0; | |
| 610 | − else | |
| 611 | − gmc->noretry = amdgpu_noretry; | |
| 612 | − break; | |
| 613 | − } | |
| 575 | + uint32_t gc_ver = adev->ip_versions[GC_HWIP][0]; | |
| 576 | + bool noretry_default = (gc_ver == IP_VERSION(9, 0, 1) || | |
| 577 | + gc_ver == IP_VERSION(9, 3, 0) || | |
| 578 | + gc_ver == IP_VERSION(9, 4, 0) || | |
| 579 | + gc_ver == IP_VERSION(9, 4, 1) || | |
| 580 | + gc_ver == IP_VERSION(9, 4, 2) || | |
| 581 | + gc_ver >= IP_VERSION(10, 3, 0)); | |
| 582 | + | |
| 583 | + gmc->noretry = (amdgpu_noretry == -1) ? noretry_default : amdgpu_noretry; | |
| 614 | 584 | } |
| 615 | 585 | |
| 616 | 586 | void amdgpu_gmc_set_vm_fault_masks(struct amdgpu_device *adev, int hub_type, |
| @@ -264,6 +264,32 @@ struct amdgpu_gmc { · 263 unmodified lines | ||
| 264 | 264 | u64 mall_size; |
| 265 | 265 | /* number of UMC instances */ |
| 266 | 266 | int num_umc; |
| 267 | + /* mode2 save restore */ | |
| 268 | + u64 VM_L2_CNTL; | |
| 269 | + u64 VM_L2_CNTL2; | |
| 270 | + u64 VM_DUMMY_PAGE_FAULT_CNTL; | |
| 271 | + u64 VM_DUMMY_PAGE_FAULT_ADDR_LO32; | |
| 272 | + u64 VM_DUMMY_PAGE_FAULT_ADDR_HI32; | |
| 273 | + u64 VM_L2_PROTECTION_FAULT_CNTL; | |
| 274 | + u64 VM_L2_PROTECTION_FAULT_CNTL2; | |
| 275 | + u64 VM_L2_PROTECTION_FAULT_MM_CNTL3; | |
| 276 | + u64 VM_L2_PROTECTION_FAULT_MM_CNTL4; | |
| 277 | + u64 VM_L2_PROTECTION_FAULT_ADDR_LO32; | |
| 278 | + u64 VM_L2_PROTECTION_FAULT_ADDR_HI32; | |
| 279 | + u64 VM_DEBUG; | |
| 280 | + u64 VM_L2_MM_GROUP_RT_CLASSES; | |
| 281 | + u64 VM_L2_BANK_SELECT_RESERVED_CID; | |
| 282 | + u64 VM_L2_BANK_SELECT_RESERVED_CID2; | |
| 283 | + u64 VM_L2_CACHE_PARITY_CNTL; | |
| 284 | + u64 VM_L2_IH_LOG_CNTL; | |
| 285 | + u64 VM_CONTEXT_CNTL[16]; | |
| 286 | + u64 VM_CONTEXT_PAGE_TABLE_BASE_ADDR_LO32[16]; | |
| 287 | + u64 VM_CONTEXT_PAGE_TABLE_BASE_ADDR_HI32[16]; | |
| 288 | + u64 VM_CONTEXT_PAGE_TABLE_START_ADDR_LO32[16]; | |
| 289 | + u64 VM_CONTEXT_PAGE_TABLE_START_ADDR_HI32[16]; | |
| 290 | + u64 VM_CONTEXT_PAGE_TABLE_END_ADDR_LO32[16]; | |
| 291 | + u64 VM_CONTEXT_PAGE_TABLE_END_ADDR_HI32[16]; | |
| 292 | + u64 MC_VM_MX_L1_TLB_CNTL; | |
| 267 | 293 | }; |
| 268 | 294 | |
| 269 | 295 | #define amdgpu_gmc_flush_gpu_tlb(adev, vmid, vmhub, type) ((adev)->gmc.gmc_funcs->flush_gpu_tlb((adev), (vmid), (vmhub), (type))) |
| @@ -204,6 +204,42 @@ void amdgpu_gtt_mgr_recover(struct amdgpu_gtt_mgr *mgr) · 203 unmodified lines | ||
| 204 | 204 | amdgpu_gart_invalidate_tlb(adev); |
| 205 | 205 | } |
| 206 | 206 | |
| 207 | +/** | |
| 208 | + * amdgpu_gtt_mgr_intersects - test for intersection | |
| 209 | + * | |
| 210 | + * @man: Our manager object | |
| 211 | + * @res: The resource to test | |
| 212 | + * @place: The place for the new allocation | |
| 213 | + * @size: The size of the new allocation | |
| 214 | + * | |
| 215 | + * Simplified intersection test, only interesting if we need GART or not. | |
| 216 | + */ | |
| 217 | +static bool amdgpu_gtt_mgr_intersects(struct ttm_resource_manager *man, | |
| 218 | + struct ttm_resource *res, | |
| 219 | + const struct ttm_place *place, | |
| 220 | + size_t size) | |
| 221 | +{ | |
| 222 | + return !place->lpfn || amdgpu_gtt_mgr_has_gart_addr(res); | |
| 223 | +} | |
| 224 | + | |
| 225 | +/** | |
| 226 | + * amdgpu_gtt_mgr_compatible - test for compatibility | |
| 227 | + * | |
| 228 | + * @man: Our manager object | |
| 229 | + * @res: The resource to test | |
| 230 | + * @place: The place for the new allocation | |
| 231 | + * @size: The size of the new allocation | |
| 232 | + * | |
| 233 | + * Simplified compatibility test. | |
| 234 | + */ | |
| 235 | +static bool amdgpu_gtt_mgr_compatible(struct ttm_resource_manager *man, | |
| 236 | + struct ttm_resource *res, | |
| 237 | + const struct ttm_place *place, | |
| 238 | + size_t size) | |
| 239 | +{ | |
| 240 | + return !place->lpfn || amdgpu_gtt_mgr_has_gart_addr(res); | |
| 241 | +} | |
| 242 | + | |
| 207 | 243 | /** |
| 208 | 244 | * amdgpu_gtt_mgr_debug - dump VRAM table |
| 209 | 245 | * |
| @@ -225,6 +261,8 @@ static void amdgpu_gtt_mgr_debug(struct ttm_resource_manager *man, · 15 unmodified lines | ||
| 225 | 261 | static const struct ttm_resource_manager_func amdgpu_gtt_mgr_func = { |
| 226 | 262 | .alloc = amdgpu_gtt_mgr_new, |
| 227 | 263 | .free = amdgpu_gtt_mgr_del, |
| 264 | + .intersects = amdgpu_gtt_mgr_intersects, | |
| 265 | + .compatible = amdgpu_gtt_mgr_compatible, | |
| 228 | 266 | .debug = amdgpu_gtt_mgr_debug |
| 229 | 267 | }; |
| 230 | 268 | |
| @@ -49,6 +49,7 @@ static enum drm_gpu_sched_stat amdgpu_job_timedout(struct drm_sched_job *s_job) · 48 unmodified lines | ||
| 49 | 49 | } |
| 50 | 50 | |
| 51 | 51 | memset(&ti, 0, sizeof(struct amdgpu_task_info)); |
| 52 | + adev->job_hang = true; | |
| 52 | 53 | |
| 53 | 54 | if (amdgpu_gpu_recovery && |
| 54 | 55 | amdgpu_ring_soft_recovery(ring, job->vmid, s_job->s_fence->parent)) { |
| @@ -71,6 +72,7 @@ static enum drm_gpu_sched_stat amdgpu_job_timedout(struct drm_sched_job *s_job) · 16 unmodified lines | ||
| 71 | 72 | reset_context.method = AMD_RESET_METHOD_NONE; |
| 72 | 73 | reset_context.reset_req_dev = adev; |
| 73 | 74 | clear_bit(AMDGPU_NEED_FULL_RESET, &reset_context.flags); |
| 75 | + clear_bit(AMDGPU_SKIP_MODE2_RESET, &reset_context.flags); | |
| 74 | 76 | |
| 75 | 77 | r = amdgpu_device_gpu_recover(ring->adev, job, &reset_context); |
| 76 | 78 | if (r) |
| @@ -82,6 +84,7 @@ static enum drm_gpu_sched_stat amdgpu_job_timedout(struct drm_sched_job *s_job) · 5 unmodified lines | ||
| 82 | 84 | } |
| 83 | 85 | |
| 84 | 86 | exit: |
| 87 | + adev->job_hang = false; | |
| 85 | 88 | drm_dev_exit(idx); |
| 86 | 89 | return DRM_GPU_SCHED_STAT_NOMINAL; |
| 87 | 90 | } |
| @@ -102,7 +105,6 @@ int amdgpu_job_alloc(struct amdgpu_device *adev, unsigned num_ibs, · 14 unmodified lines | ||
| 102 | 105 | */ |
| 103 | 106 | (*job)->base.sched = &adev->rings[0]->sched; |
| 104 | 107 | (*job)->vm = vm; |
| 105 | − (*job)->num_ibs = num_ibs; | |
| 106 | 108 | |
| 107 | 109 | amdgpu_sync_create(&(*job)->sync); |
| 108 | 110 | amdgpu_sync_create(&(*job)->sched_sync); |
| @@ -122,6 +124,7 @@ int amdgpu_job_alloc_with_ib(struct amdgpu_device *adev, unsigned size, · 13 unmodified lines | ||
| 122 | 124 | if (r) |
| 123 | 125 | return r; |
| 124 | 126 | |
| 127 | + (*job)->num_ibs = 1; | |
| 125 | 128 | r = amdgpu_ib_get(adev, NULL, size, pool_type, &(*job)->ibs[0]); |
| 126 | 129 | if (r) |
| 127 | 130 | kfree(*job); |
| @@ -129,6 +132,23 @@ int amdgpu_job_alloc_with_ib(struct amdgpu_device *adev, unsigned size, · 1 unmodified line | ||
| 129 | 132 | return r; |
| 130 | 133 | } |
| 131 | 134 | |
| 135 | +void amdgpu_job_set_resources(struct amdgpu_job *job, struct amdgpu_bo *gds, | |
| 136 | + struct amdgpu_bo *gws, struct amdgpu_bo *oa) | |
| 137 | +{ | |
| 138 | + if (gds) { | |
| 139 | + job->gds_base = amdgpu_bo_gpu_offset(gds) >> PAGE_SHIFT; | |
| 140 | + job->gds_size = amdgpu_bo_size(gds) >> PAGE_SHIFT; | |
| 141 | + } | |
| 142 | + if (gws) { | |
| 143 | + job->gws_base = amdgpu_bo_gpu_offset(gws) >> PAGE_SHIFT; | |
| 144 | + job->gws_size = amdgpu_bo_size(gws) >> PAGE_SHIFT; | |
| 145 | + } | |
| 146 | + if (oa) { | |
| 147 | + job->oa_base = amdgpu_bo_gpu_offset(oa) >> PAGE_SHIFT; | |
| 148 | + job->oa_size = amdgpu_bo_size(oa) >> PAGE_SHIFT; | |
| 149 | + } | |
| 150 | +} | |
| 151 | + | |
| 132 | 152 | void amdgpu_job_free_resources(struct amdgpu_job *job) |
| 133 | 153 | { |
| 134 | 154 | struct amdgpu_ring *ring = to_amdgpu_ring(job->base.sched); |
| @@ -153,11 +173,29 @@ static void amdgpu_job_free_cb(struct drm_sched_job *s_job) · 18 unmodified lines | ||
| 153 | 173 | dma_fence_put(&job->hw_fence); |
| 154 | 174 | } |
| 155 | 175 | |
| 176 | +void amdgpu_job_set_gang_leader(struct amdgpu_job *job, | |
| 177 | + struct amdgpu_job *leader) | |
| 178 | +{ | |
| 179 | + struct dma_fence *fence = &leader->base.s_fence->scheduled; | |
| 180 | + | |
| 181 | + WARN_ON(job->gang_submit); | |
| 182 | + | |
| 183 | + /* | |
| 184 | + * Don't add a reference when we are the gang leader to avoid circle | |
| 185 | + * dependency. | |
| 186 | + */ | |
| 187 | + if (job != leader) | |
| 188 | + dma_fence_get(fence); | |
| 189 | + job->gang_submit = fence; | |
| 190 | +} | |
| 191 | + | |
| 156 | 192 | void amdgpu_job_free(struct amdgpu_job *job) |
| 157 | 193 | { |
| 158 | 194 | amdgpu_job_free_resources(job); |
| 159 | 195 | amdgpu_sync_free(&job->sync); |
| 160 | 196 | amdgpu_sync_free(&job->sched_sync); |
| 197 | + if (job->gang_submit != &job->base.s_fence->scheduled) | |
| 198 | + dma_fence_put(job->gang_submit); | |
| 161 | 199 | |
| 162 | 200 | if (!job->hw_fence.ops) |
| 163 | 201 | kfree(job); |
| @@ -227,12 +265,16 @@ static struct dma_fence *amdgpu_job_dependency(struct drm_sched_job *sched_job, · 63 unmodified lines | ||
| 227 | 265 | fence = amdgpu_sync_get_fence(&job->sync); |
| 228 | 266 | } |
| 229 | 267 | |
| 268 | + if (!fence && job->gang_submit) | |
| 269 | + fence = amdgpu_device_switch_gang(ring->adev, job->gang_submit); | |
| 270 | + | |
| 230 | 271 | return fence; |
| 231 | 272 | } |
| 232 | 273 | |
| 233 | 274 | static struct dma_fence *amdgpu_job_run(struct drm_sched_job *sched_job) |
| 234 | 275 | { |
| 235 | 276 | struct amdgpu_ring *ring = to_amdgpu_ring(sched_job->sched); |
| 277 | + struct amdgpu_device *adev = ring->adev; | |
| 236 | 278 | struct dma_fence *fence = NULL, *finished; |
| 237 | 279 | struct amdgpu_job *job; |
| 238 | 280 | int r = 0; |
| @@ -244,8 +286,10 @@ static struct dma_fence *amdgpu_job_run(struct drm_sched_job *sched_job) · 5 unmodified lines | ||
| 244 | 286 | |
| 245 | 287 | trace_amdgpu_sched_run_job(job); |
| 246 | 288 | |
| 247 | − if (job->vram_lost_counter != atomic_read(&ring->adev->vram_lost_counter)) | |
| 248 | − dma_fence_set_error(finished, -ECANCELED);/* skip IB as well if VRAM lost */ | |
| 289 | + /* Skip job if VRAM is lost and never resubmit gangs */ | |
| 290 | + if (job->vram_lost_counter != atomic_read(&adev->vram_lost_counter) || | |
| 291 | + (job->job_run_counter && job->gang_submit)) | |
| 292 | + dma_fence_set_error(finished, -ECANCELED); | |
| 249 | 293 | |
| 250 | 294 | if (finished->error < 0) { |
| 251 | 295 | DRM_INFO("Skip scheduling IBs!\n"); |
| @@ -50,6 +50,7 @@ struct amdgpu_job { · 49 unmodified lines | ||
| 50 | 50 | struct amdgpu_sync sync; |
| 51 | 51 | struct amdgpu_sync sched_sync; |
| 52 | 52 | struct dma_fence hw_fence; |
| 53 | + struct dma_fence *gang_submit; | |
| 53 | 54 | uint32_t preamble_status; |
| 54 | 55 | uint32_t preemption_status; |
| 55 | 56 | bool vm_needs_flush; |
| @@ -72,11 +73,20 @@ struct amdgpu_job { · 16 unmodified lines | ||
| 72 | 73 | struct amdgpu_ib ibs[]; |
| 73 | 74 | }; |
| 74 | 75 | |
| 76 | +static inline struct amdgpu_ring *amdgpu_job_ring(struct amdgpu_job *job) | |
| 77 | +{ | |
| 78 | + return to_amdgpu_ring(job->base.entity->rq->sched); | |
| 79 | +} | |
| 80 | + | |
| 75 | 81 | int amdgpu_job_alloc(struct amdgpu_device *adev, unsigned num_ibs, |
| 76 | 82 | struct amdgpu_job **job, struct amdgpu_vm *vm); |
| 77 | 83 | int amdgpu_job_alloc_with_ib(struct amdgpu_device *adev, unsigned size, |
| 78 | 84 | enum amdgpu_ib_pool_type pool, struct amdgpu_job **job); |
| 85 | +void amdgpu_job_set_resources(struct amdgpu_job *job, struct amdgpu_bo *gds, | |
| 86 | + struct amdgpu_bo *gws, struct amdgpu_bo *oa); | |
| 79 | 87 | void amdgpu_job_free_resources(struct amdgpu_job *job); |
| 88 | +void amdgpu_job_set_gang_leader(struct amdgpu_job *job, | |
| 89 | + struct amdgpu_job *leader); | |
| 80 | 90 | void amdgpu_job_free(struct amdgpu_job *job); |
| 81 | 91 | int amdgpu_job_submit(struct amdgpu_job *job, struct drm_sched_entity *entity, |
| 82 | 92 | void *owner, struct dma_fence **f); |
| @@ -247,6 +247,14 @@ static int amdgpu_firmware_info(struct drm_amdgpu_info_firmware *fw_info, · 246 unmodified lines | ||
| 247 | 247 | fw_info->ver = adev->gfx.rlc_srls_fw_version; |
| 248 | 248 | fw_info->feature = adev->gfx.rlc_srls_feature_version; |
| 249 | 249 | break; |
| 250 | + case AMDGPU_INFO_FW_GFX_RLCP: | |
| 251 | + fw_info->ver = adev->gfx.rlcp_ucode_version; | |
| 252 | + fw_info->feature = adev->gfx.rlcp_ucode_feature_version; | |
| 253 | + break; | |
| 254 | + case AMDGPU_INFO_FW_GFX_RLCV: | |
| 255 | + fw_info->ver = adev->gfx.rlcv_ucode_version; | |
| 256 | + fw_info->feature = adev->gfx.rlcv_ucode_feature_version; | |
| 257 | + break; | |
| 250 | 258 | case AMDGPU_INFO_FW_GFX_MEC: |
| 251 | 259 | if (query_fw->index == 0) { |
| 252 | 260 | fw_info->ver = adev->gfx.mec_fw_version; |
| @@ -328,6 +336,14 @@ static int amdgpu_firmware_info(struct drm_amdgpu_info_firmware *fw_info, · 75 unmodified lines | ||
| 328 | 336 | fw_info->ver = adev->psp.cap_fw_version; |
| 329 | 337 | fw_info->feature = adev->psp.cap_feature_version; |
| 330 | 338 | break; |
| 339 | + case AMDGPU_INFO_FW_MES_KIQ: | |
| 340 | + fw_info->ver = adev->mes.ucode_fw_version[0]; | |
| 341 | + fw_info->feature = 0; | |
| 342 | + break; | |
| 343 | + case AMDGPU_INFO_FW_MES: | |
| 344 | + fw_info->ver = adev->mes.ucode_fw_version[1]; | |
| 345 | + fw_info->feature = 0; | |
| 346 | + break; | |
| 331 | 347 | default: |
| 332 | 348 | return -EINVAL; |
| 333 | 349 | } |
| @@ -1160,7 +1176,7 @@ int amdgpu_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv) · 826 unmodified lines | ||
| 1160 | 1176 | } |
| 1161 | 1177 | |
| 1162 | 1178 | mutex_init(&fpriv->bo_list_lock); |
| 1163 | − idr_init(&fpriv->bo_list_handles); | |
| 1179 | + idr_init_base(&fpriv->bo_list_handles, 1); | |
| 1164 | 1180 | |
| 1165 | 1181 | amdgpu_ctx_mgr_init(&fpriv->ctx_mgr, adev); |
| 1166 | 1182 | |
| @@ -1469,6 +1485,22 @@ static int amdgpu_debugfs_firmware_info_show(struct seq_file *m, void *unused) · 302 unmodified lines | ||
| 1469 | 1485 | seq_printf(m, "RLC SRLS feature version: %u, firmware version: 0x%08x\n", |
| 1470 | 1486 | fw_info.feature, fw_info.ver); |
| 1471 | 1487 | |
| 1488 | + /* RLCP */ | |
| 1489 | + query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLCP; | |
| 1490 | + ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); | |
| 1491 | + if (ret) | |
| 1492 | + return ret; | |
| 1493 | + seq_printf(m, "RLCP feature version: %u, firmware version: 0x%08x\n", | |
| 1494 | + fw_info.feature, fw_info.ver); | |
| 1495 | + | |
| 1496 | + /* RLCV */ | |
| 1497 | + query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLCV; | |
| 1498 | + ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); | |
| 1499 | + if (ret) | |
| 1500 | + return ret; | |
| 1501 | + seq_printf(m, "RLCV feature version: %u, firmware version: 0x%08x\n", | |
| 1502 | + fw_info.feature, fw_info.ver); | |
| 1503 | + | |
| 1472 | 1504 | /* MEC */ |
| 1473 | 1505 | query_fw.fw_type = AMDGPU_INFO_FW_GFX_MEC; |
| 1474 | 1506 | query_fw.index = 0; |
| @@ -1581,6 +1613,22 @@ static int amdgpu_debugfs_firmware_info_show(struct seq_file *m, void *unused) · 106 unmodified lines | ||
| 1581 | 1613 | fw_info.feature, fw_info.ver); |
| 1582 | 1614 | } |
| 1583 | 1615 | |
| 1616 | + /* MES_KIQ */ | |
| 1617 | + query_fw.fw_type = AMDGPU_INFO_FW_MES_KIQ; | |
| 1618 | + ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); | |
| 1619 | + if (ret) | |
| 1620 | + return ret; | |
| 1621 | + seq_printf(m, "MES_KIQ feature version: %u, firmware version: 0x%08x\n", | |
| 1622 | + fw_info.feature, fw_info.ver); | |
| 1623 | + | |
| 1624 | + /* MES */ | |
| 1625 | + query_fw.fw_type = AMDGPU_INFO_FW_MES; | |
| 1626 | + ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); | |
| 1627 | + if (ret) | |
| 1628 | + return ret; | |
| 1629 | + seq_printf(m, "MES feature version: %u, firmware version: 0x%08x\n", | |
| 1630 | + fw_info.feature, fw_info.ver); | |
| 1631 | + | |
| 1584 | 1632 | seq_printf(m, "VBIOS version: %s\n", ctx->vbios_version); |
| 1585 | 1633 | |
| 1586 | 1634 | return 0; |
| @@ -38,7 +38,6 @@ · 37 unmodified lines | ||
| 38 | 38 | #include <drm/drm_crtc_helper.h> |
| 39 | 39 | #include <drm/drm_fb_helper.h> |
| 40 | 40 | #include <drm/drm_framebuffer.h> |
| 41 | −#include <drm/drm_plane_helper.h> | |
| 42 | 41 | #include <drm/drm_probe_helper.h> |
| 43 | 42 | #include <linux/i2c.h> |
| 44 | 43 | #include <linux/i2c-algo-bit.h> |
| @@ -591,7 +591,7 @@ int amdgpu_bo_create(struct amdgpu_device *adev, · 590 unmodified lines | ||
| 591 | 591 | if (!bp->destroy) |
| 592 | 592 | bp->destroy = &amdgpu_bo_destroy; |
| 593 | 593 | |
| 594 | − r = ttm_bo_init_reserved(&adev->mman.bdev, &bo->tbo, size, bp->type, | |
| 594 | + r = ttm_bo_init_reserved(&adev->mman.bdev, &bo->tbo, bp->type, | |
| 595 | 595 | &bo->placement, page_align, &ctx, NULL, |
| 596 | 596 | bp->resv, bp->destroy); |
| 597 | 597 | if (unlikely(r != 0)) |
| @@ -1309,7 +1309,7 @@ void amdgpu_bo_release_notify(struct ttm_buffer_object *bo) · 711 unmodified lines | ||
| 1309 | 1309 | if (bo->base.resv == &bo->base._resv) |
| 1310 | 1310 | amdgpu_amdkfd_remove_fence_on_pt_pd_bos(abo); |
| 1311 | 1311 | |
| 1312 | − if (bo->resource->mem_type != TTM_PL_VRAM || | |
| 1312 | + if (!bo->resource || bo->resource->mem_type != TTM_PL_VRAM || | |
| 1313 | 1313 | !(abo->flags & AMDGPU_GEM_CREATE_VRAM_WIPE_ON_RELEASE) || |
| 1314 | 1314 | adev->in_suspend || adev->shutdown) |
| 1315 | 1315 | return; |
| @@ -138,6 +138,7 @@ static int psp_early_init(void *handle) · 137 unmodified lines | ||
| 138 | 138 | case IP_VERSION(13, 0, 3): |
| 139 | 139 | case IP_VERSION(13, 0, 5): |
| 140 | 140 | case IP_VERSION(13, 0, 8): |
| 141 | + case IP_VERSION(13, 0, 10): | |
| 141 | 142 | psp_v13_0_set_psp_funcs(psp); |
| 142 | 143 | psp->autoload_supported = true; |
| 143 | 144 | break; |
| @@ -327,23 +328,32 @@ static int psp_init_sriov_microcode(struct psp_context *psp) · 183 unmodified lines | ||
| 327 | 328 | |
| 328 | 329 | switch (adev->ip_versions[MP0_HWIP][0]) { |
| 329 | 330 | case IP_VERSION(9, 0, 0): |
| 331 | + adev->virt.autoload_ucode_id = AMDGPU_UCODE_ID_CP_MEC2; | |
| 330 | 332 | ret = psp_init_cap_microcode(psp, "vega10"); |
| 331 | 333 | break; |
| 332 | 334 | case IP_VERSION(11, 0, 9): |
| 335 | + adev->virt.autoload_ucode_id = AMDGPU_UCODE_ID_CP_MEC2; | |
| 333 | 336 | ret = psp_init_cap_microcode(psp, "navi12"); |
| 334 | 337 | break; |
| 335 | 338 | case IP_VERSION(11, 0, 7): |
| 339 | + adev->virt.autoload_ucode_id = AMDGPU_UCODE_ID_CP_MEC2; | |
| 336 | 340 | ret = psp_init_cap_microcode(psp, "sienna_cichlid"); |
| 337 | 341 | break; |
| 338 | 342 | case IP_VERSION(13, 0, 2): |
| 343 | + adev->virt.autoload_ucode_id = AMDGPU_UCODE_ID_CP_MEC2; | |
| 339 | 344 | ret = psp_init_cap_microcode(psp, "aldebaran"); |
| 340 | 345 | ret &= psp_init_ta_microcode(psp, "aldebaran"); |
| 341 | 346 | break; |
| 347 | + case IP_VERSION(13, 0, 0): | |
| 348 | + adev->virt.autoload_ucode_id = 0; | |
| 349 | + break; | |
| 350 | + case IP_VERSION(13, 0, 10): | |
| 351 | + adev->virt.autoload_ucode_id = AMDGPU_UCODE_ID_CP_MES1_DATA; | |
| 352 | + break; | |
| 342 | 353 | default: |
| 343 | 354 | BUG(); |
| 344 | 355 | break; |
| 345 | 356 | } |
| 346 | − | |
| 347 | 357 | return ret; |
| 348 | 358 | } |
| 349 | 359 | |
| @@ -501,6 +511,11 @@ static int psp_sw_fini(void *handle) · 151 unmodified lines | ||
| 501 | 511 | kfree(cmd); |
| 502 | 512 | cmd = NULL; |
| 503 | 513 | |
| 514 | + if (psp->km_ring.ring_mem) | |
| 515 | + amdgpu_bo_free_kernel(&adev->firmware.rbuf, | |
| 516 | + &psp->km_ring.ring_mem_mc_addr, | |
| 517 | + (void **)&psp->km_ring.ring_mem); | |
| 518 | + | |
| 504 | 519 | amdgpu_bo_free_kernel(&psp->fw_pri_bo, |
| 505 | 520 | &psp->fw_pri_mc_addr, &psp->fw_pri_buf); |
| 506 | 521 | amdgpu_bo_free_kernel(&psp->fence_buf_bo, |
| @@ -769,6 +784,7 @@ static bool psp_skip_tmr(struct psp_context *psp) · 262 unmodified lines | ||
| 769 | 784 | case IP_VERSION(11, 0, 9): |
| 770 | 785 | case IP_VERSION(11, 0, 7): |
| 771 | 786 | case IP_VERSION(13, 0, 2): |
| 787 | + case IP_VERSION(13, 0, 10): | |
| 772 | 788 | return true; |
| 773 | 789 | default: |
| 774 | 790 | return false; |
| @@ -815,7 +831,7 @@ static int psp_tmr_unload(struct psp_context *psp) · 40 unmodified lines | ||
| 815 | 831 | struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp); |
| 816 | 832 | |
| 817 | 833 | psp_prep_tmr_unload_cmd_buf(psp, cmd); |
| 818 | − DRM_INFO("free PSP TMR buffer\n"); | |
| 834 | + dev_info(psp->adev->dev, "free PSP TMR buffer\n"); | |
| 819 | 835 | |
| 820 | 836 | ret = psp_cmd_submit_buf(psp, NULL, cmd, |
| 821 | 837 | psp->fence_buf_mc_addr); |
| @@ -2044,6 +2060,15 @@ static int psp_hw_start(struct psp_context *psp) · 1222 unmodified lines | ||
| 2044 | 2060 | } |
| 2045 | 2061 | } |
| 2046 | 2062 | |
| 2063 | + if ((is_psp_fw_valid(psp->ras_drv)) && | |
| 2064 | + (psp->funcs->bootloader_load_ras_drv != NULL)) { | |
| 2065 | + ret = psp_bootloader_load_ras_drv(psp); | |
| 2066 | + if (ret) { | |
| 2067 | + DRM_ERROR("PSP load ras_drv failed!\n"); | |
| 2068 | + return ret; | |
| 2069 | + } | |
| 2070 | + } | |
| 2071 | + | |
| 2047 | 2072 | if ((is_psp_fw_valid(psp->sos)) && |
| 2048 | 2073 | (psp->funcs->bootloader_load_sos != NULL)) { |
| 2049 | 2074 | ret = psp_bootloader_load_sos(psp); |
| @@ -2414,20 +2439,7 @@ static bool fw_load_skip_check(struct psp_context *psp, · 364 unmodified lines | ||
| 2414 | 2439 | return true; |
| 2415 | 2440 | |
| 2416 | 2441 | if (amdgpu_sriov_vf(psp->adev) && |
| 2417 | − (ucode->ucode_id == AMDGPU_UCODE_ID_SDMA0 | |
| 2418 | − || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA1 | |
| 2419 | − || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA2 | |
| 2420 | − || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA3 | |
| 2421 | − || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA4 | |
| 2422 | − || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA5 | |
| 2423 | − || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA6 | |
| 2424 | − || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA7 | |
| 2425 | − || ucode->ucode_id == AMDGPU_UCODE_ID_RLC_G | |
| 2426 | − || ucode->ucode_id == AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL | |
| 2427 | − || ucode->ucode_id == AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM | |
| 2428 | − || ucode->ucode_id == AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM | |
| 2429 | − || ucode->ucode_id == AMDGPU_UCODE_ID_SMC)) | |
| 2430 | − /*skip ucode loading in SRIOV VF */ | |
| 2442 | + amdgpu_virt_fw_load_skip_check(psp->adev, ucode->ucode_id)) | |
| 2431 | 2443 | return true; |
| 2432 | 2444 | |
| 2433 | 2445 | if (psp->autoload_supported && |
| @@ -2501,7 +2513,7 @@ static int psp_load_non_psp_fw(struct psp_context *psp) · 67 unmodified lines | ||
| 2501 | 2513 | |
| 2502 | 2514 | /* Start rlc autoload after psp recieved all the gfx firmware */ |
| 2503 | 2515 | if (psp->autoload_supported && ucode->ucode_id == (amdgpu_sriov_vf(adev) ? |
| 2504 | − AMDGPU_UCODE_ID_CP_MEC2 : AMDGPU_UCODE_ID_RLC_G)) { | |
| 2516 | + adev->virt.autoload_ucode_id : AMDGPU_UCODE_ID_RLC_G)) { | |
| 2505 | 2517 | ret = psp_rlc_autoload_start(psp); |
| 2506 | 2518 | if (ret) { |
| 2507 | 2519 | DRM_ERROR("Failed to start rlc autoload\n"); |
| @@ -3042,6 +3054,12 @@ static int parse_sos_bin_descriptor(struct psp_context *psp, · 534 unmodified lines | ||
| 3042 | 3054 | psp->dbg_drv.size_bytes = le32_to_cpu(desc->size_bytes); |
| 3043 | 3055 | psp->dbg_drv.start_addr = ucode_start_addr; |
| 3044 | 3056 | break; |
| 3057 | + case PSP_FW_TYPE_PSP_RAS_DRV: | |
| 3058 | + psp->ras_drv.fw_version = le32_to_cpu(desc->fw_version); | |
| 3059 | + psp->ras_drv.feature_version = le32_to_cpu(desc->fw_version); | |
| 3060 | + psp->ras_drv.size_bytes = le32_to_cpu(desc->size_bytes); | |
| 3061 | + psp->ras_drv.start_addr = ucode_start_addr; | |
| 3062 | + break; | |
| 3045 | 3063 | default: |
| 3046 | 3064 | dev_warn(psp->adev->dev, "Unsupported PSP FW type: %d\n", desc->fw_type); |
| 3047 | 3065 | break; |
| @@ -72,6 +72,7 @@ enum psp_bootloader_cmd { · 71 unmodified lines | ||
| 72 | 72 | PSP_BL__LOAD_SOCDRV = 0xB0000, |
| 73 | 73 | PSP_BL__LOAD_DBGDRV = 0xC0000, |
| 74 | 74 | PSP_BL__LOAD_INTFDRV = 0xD0000, |
| 75 | + PSP_BL__LOAD_RASDRV = 0xE0000, | |
| 75 | 76 | PSP_BL__DRAM_LONG_TRAIN = 0x100000, |
| 76 | 77 | PSP_BL__DRAM_SHORT_TRAIN = 0x200000, |
| 77 | 78 | PSP_BL__LOAD_TOS_SPL_TABLE = 0x10000000, |
| @@ -115,6 +116,7 @@ struct psp_funcs · 37 unmodified lines | ||
| 115 | 116 | int (*bootloader_load_soc_drv)(struct psp_context *psp); |
| 116 | 117 | int (*bootloader_load_intf_drv)(struct psp_context *psp); |
| 117 | 118 | int (*bootloader_load_dbg_drv)(struct psp_context *psp); |
| 119 | + int (*bootloader_load_ras_drv)(struct psp_context *psp); | |
| 118 | 120 | int (*bootloader_load_sos)(struct psp_context *psp); |
| 119 | 121 | int (*ring_init)(struct psp_context *psp, enum psp_ring_type ring_type); |
| 120 | 122 | int (*ring_create)(struct psp_context *psp, |
| @@ -324,6 +326,7 @@ struct psp_context · 203 unmodified lines | ||
| 324 | 326 | struct psp_bin_desc soc_drv; |
| 325 | 327 | struct psp_bin_desc intf_drv; |
| 326 | 328 | struct psp_bin_desc dbg_drv; |
| 329 | + struct psp_bin_desc ras_drv; | |
| 327 | 330 | |
| 328 | 331 | /* tmr buffer */ |
| 329 | 332 | struct amdgpu_bo *tmr_bo; |
| @@ -404,6 +407,9 @@ struct amdgpu_psp_funcs { · 74 unmodified lines | ||
| 404 | 407 | ((psp)->funcs->bootloader_load_intf_drv ? (psp)->funcs->bootloader_load_intf_drv((psp)) : 0) |
| 405 | 408 | #define psp_bootloader_load_dbg_drv(psp) \ |
| 406 | 409 | ((psp)->funcs->bootloader_load_dbg_drv ? (psp)->funcs->bootloader_load_dbg_drv((psp)) : 0) |
| 410 | +#define psp_bootloader_load_ras_drv(psp) \ | |
| 411 | + ((psp)->funcs->bootloader_load_ras_drv ? \ | |
| 412 | + (psp)->funcs->bootloader_load_ras_drv((psp)) : 0) | |
| 407 | 413 | #define psp_bootloader_load_sos(psp) \ |
| 408 | 414 | ((psp)->funcs->bootloader_load_sos ? (psp)->funcs->bootloader_load_sos((psp)) : 0) |
| 409 | 415 | #define psp_smu_reload_quirk(psp) \ |
| @@ -1950,6 +1950,7 @@ static void amdgpu_ras_do_recovery(struct work_struct *work) · 1949 unmodified lines | ||
| 1950 | 1950 | reset_context.method = AMD_RESET_METHOD_NONE; |
| 1951 | 1951 | reset_context.reset_req_dev = adev; |
| 1952 | 1952 | clear_bit(AMDGPU_NEED_FULL_RESET, &reset_context.flags); |
| 1953 | + clear_bit(AMDGPU_SKIP_MODE2_RESET, &reset_context.flags); | |
| 1953 | 1954 | |
| 1954 | 1955 | amdgpu_device_gpu_recover(ras->adev, NULL, &reset_context); |
| 1955 | 1956 | } |
| @@ -2719,7 +2720,8 @@ int amdgpu_ras_pre_fini(struct amdgpu_device *adev) · 763 unmodified lines | ||
| 2719 | 2720 | |
| 2720 | 2721 | |
| 2721 | 2722 | /* Need disable ras on all IPs here before ip [hw/sw]fini */ |
| 2722 | − amdgpu_ras_disable_all_features(adev, 0); | |
| 2723 | + if (con->features) | |
| 2724 | + amdgpu_ras_disable_all_features(adev, 0); | |
| 2723 | 2725 | amdgpu_ras_recovery_fini(adev); |
| 2724 | 2726 | return 0; |
| 2725 | 2727 | } |
| @@ -2832,11 +2834,8 @@ static int amdgpu_bad_page_notifier(struct notifier_block *nb, · 106 unmodified lines | ||
| 2832 | 2834 | struct mce *m = (struct mce *)data; |
| 2833 | 2835 | struct amdgpu_device *adev = NULL; |
| 2834 | 2836 | uint32_t gpu_id = 0; |
| 2835 | − uint32_t umc_inst = 0; | |
| 2836 | − uint32_t ch_inst, channel_index = 0; | |
| 2837 | + uint32_t umc_inst = 0, ch_inst = 0; | |
| 2837 | 2838 | struct ras_err_data err_data = {0, 0, 0, NULL}; |
| 2838 | − struct eeprom_table_record err_rec; | |
| 2839 | − uint64_t retired_page; | |
| 2840 | 2839 | |
| 2841 | 2840 | /* |
| 2842 | 2841 | * If the error was generated in UMC_V2, which belongs to GPU UMCs, |
| @@ -2875,21 +2874,22 @@ static int amdgpu_bad_page_notifier(struct notifier_block *nb, · 32 unmodified lines | ||
| 2875 | 2874 | dev_info(adev->dev, "Uncorrectable error detected in UMC inst: %d, chan_idx: %d", |
| 2876 | 2875 | umc_inst, ch_inst); |
| 2877 | 2876 | |
| 2877 | + err_data.err_addr = | |
| 2878 | + kcalloc(adev->umc.max_ras_err_cnt_per_query, | |
| 2879 | + sizeof(struct eeprom_table_record), GFP_KERNEL); | |
| 2880 | + if(!err_data.err_addr) { | |
| 2881 | + dev_warn(adev->dev, "Failed to alloc memory for " | |
| 2882 | + "umc error address record in mca notifier!\n"); | |
| 2883 | + return NOTIFY_DONE; | |
| 2884 | + } | |
| 2885 | + | |
| 2878 | 2886 | /* |
| 2879 | 2887 | * Translate UMC channel address to Physical address |
| 2880 | 2888 | */ |
| 2881 | − channel_index = | |
| 2882 | − adev->umc.channel_idx_tbl[umc_inst * adev->umc.channel_inst_num | |
| 2883 | − + ch_inst]; | |
| 2884 | − | |
| 2885 | − retired_page = ADDR_OF_8KB_BLOCK(m->addr) | | |
| 2886 | − ADDR_OF_256B_BLOCK(channel_index) | | |
| 2887 | − OFFSET_IN_256B_BLOCK(m->addr); | |
| 2888 | − | |
| 2889 | − memset(&err_rec, 0x0, sizeof(struct eeprom_table_record)); | |
| 2890 | − err_data.err_addr = &err_rec; | |
| 2891 | − amdgpu_umc_fill_error_record(&err_data, m->addr, | |
| 2892 | − retired_page, channel_index, umc_inst); | |
| 2889 | + if (adev->umc.ras && | |
| 2890 | + adev->umc.ras->convert_ras_error_address) | |
| 2891 | + adev->umc.ras->convert_ras_error_address(adev, | |
| 2892 | + &err_data, 0, ch_inst, umc_inst, m->addr); | |
| 2893 | 2893 | |
| 2894 | 2894 | if (amdgpu_bad_page_threshold != 0) { |
| 2895 | 2895 | amdgpu_ras_add_bad_pages(adev, err_data.err_addr, |
| @@ -2897,6 +2897,7 @@ static int amdgpu_bad_page_notifier(struct notifier_block *nb, · 1 unmodified line | ||
| 2897 | 2897 | amdgpu_ras_save_bad_pages(adev); |
| 2898 | 2898 | } |
| 2899 | 2899 | |
| 2900 | + kfree(err_data.err_addr); | |
| 2900 | 2901 | return NOTIFY_OK; |
| 2901 | 2902 | } |
| 2902 | 2903 | |
| @@ -38,6 +38,7 @@ · 37 unmodified lines | ||
| 38 | 38 | #define EEPROM_I2C_MADDR_ARCTURUS_D342 0x0 |
| 39 | 39 | #define EEPROM_I2C_MADDR_SIENNA_CICHLID 0x0 |
| 40 | 40 | #define EEPROM_I2C_MADDR_ALDEBARAN 0x0 |
| 41 | +#define EEPROM_I2C_MADDR_SMU_13_0_0 (0x54UL << 16) | |
| 41 | 42 | |
| 42 | 43 | /* |
| 43 | 44 | * The 2 macros bellow represent the actual size in bytes that |
| @@ -156,6 +157,15 @@ static bool __get_eeprom_i2c_addr(struct amdgpu_device *adev, · 112 unmodified lines | ||
| 156 | 157 | return false; |
| 157 | 158 | } |
| 158 | 159 | |
| 160 | + switch (adev->ip_versions[MP1_HWIP][0]) { | |
| 161 | + case IP_VERSION(13, 0, 0): | |
| 162 | + control->i2c_address = EEPROM_I2C_MADDR_SMU_13_0_0; | |
| 163 | + break; | |
| 164 | + | |
| 165 | + default: | |
| 166 | + break; | |
| 167 | + } | |
| 168 | + | |
| 159 | 169 | return true; |
| 160 | 170 | } |
| 161 | 171 | |
| @@ -23,6 +23,7 @@ · 22 unmodified lines | ||
| 23 | 23 | |
| 24 | 24 | #include "amdgpu_reset.h" |
| 25 | 25 | #include "aldebaran.h" |
| 26 | +#include "sienna_cichlid.h" | |
| 26 | 27 | |
| 27 | 28 | int amdgpu_reset_add_handler(struct amdgpu_reset_control *reset_ctl, |
| 28 | 29 | struct amdgpu_reset_handler *handler) |
| @@ -36,10 +37,15 @@ int amdgpu_reset_init(struct amdgpu_device *adev) · 7 unmodified lines | ||
| 36 | 37 | { |
| 37 | 38 | int ret = 0; |
| 38 | 39 | |
| 40 | + adev->amdgpu_reset_level_mask = 0x1; | |
| 41 | + | |
| 39 | 42 | switch (adev->ip_versions[MP1_HWIP][0]) { |
| 40 | 43 | case IP_VERSION(13, 0, 2): |
| 41 | 44 | ret = aldebaran_reset_init(adev); |
| 42 | 45 | break; |
| 46 | + case IP_VERSION(11, 0, 7): | |
| 47 | + ret = sienna_cichlid_reset_init(adev); | |
| 48 | + break; | |
| 43 | 49 | default: |
| 44 | 50 | break; |
| 45 | 51 | } |
| @@ -55,6 +61,9 @@ int amdgpu_reset_fini(struct amdgpu_device *adev) · 9 unmodified lines | ||
| 55 | 61 | case IP_VERSION(13, 0, 2): |
| 56 | 62 | ret = aldebaran_reset_fini(adev); |
| 57 | 63 | break; |
| 64 | + case IP_VERSION(11, 0, 7): | |
| 65 | + ret = sienna_cichlid_reset_fini(adev); | |
| 66 | + break; | |
| 58 | 67 | default: |
| 59 | 68 | break; |
| 60 | 69 | } |
| @@ -67,6 +76,12 @@ int amdgpu_reset_prepare_hwcontext(struct amdgpu_device *adev, · 6 unmodified lines | ||
| 67 | 76 | { |
| 68 | 77 | struct amdgpu_reset_handler *reset_handler = NULL; |
| 69 | 78 | |
| 79 | + if (!(adev->amdgpu_reset_level_mask & AMDGPU_RESET_LEVEL_MODE2)) | |
| 80 | + return -ENOSYS; | |
| 81 | + | |
| 82 | + if (test_bit(AMDGPU_SKIP_MODE2_RESET, &reset_context->flags)) | |
| 83 | + return -ENOSYS; | |
| 84 | + | |
| 70 | 85 | if (adev->reset_cntl && adev->reset_cntl->get_reset_handler) |
| 71 | 86 | reset_handler = adev->reset_cntl->get_reset_handler( |
| 72 | 87 | adev->reset_cntl, reset_context); |
| @@ -83,6 +98,12 @@ int amdgpu_reset_perform_reset(struct amdgpu_device *adev, · 10 unmodified lines | ||
| 83 | 98 | int ret; |
| 84 | 99 | struct amdgpu_reset_handler *reset_handler = NULL; |
| 85 | 100 | |
| 101 | + if (!(adev->amdgpu_reset_level_mask & AMDGPU_RESET_LEVEL_MODE2)) | |
| 102 | + return -ENOSYS; | |
| 103 | + | |
| 104 | + if (test_bit(AMDGPU_SKIP_MODE2_RESET, &reset_context->flags)) | |
| 105 | + return -ENOSYS; | |
| 106 | + | |
| 86 | 107 | if (adev->reset_cntl) |
| 87 | 108 | reset_handler = adev->reset_cntl->get_reset_handler( |
| 88 | 109 | adev->reset_cntl, reset_context); |
| @@ -30,6 +30,8 @@ enum AMDGPU_RESET_FLAGS { · 29 unmodified lines | ||
| 30 | 30 | |
| 31 | 31 | AMDGPU_NEED_FULL_RESET = 0, |
| 32 | 32 | AMDGPU_SKIP_HW_RESET = 1, |
| 33 | + AMDGPU_SKIP_MODE2_RESET = 2, | |
| 34 | + AMDGPU_RESET_FOR_DEVICE_REMOVE = 3, | |
| 33 | 35 | }; |
| 34 | 36 | |
| 35 | 37 | struct amdgpu_reset_context { |
| @@ -111,7 +113,8 @@ static inline bool amdgpu_reset_get_reset_domain(struct amdgpu_reset_domain *dom · 75 unmodified lines | ||
| 111 | 113 | |
| 112 | 114 | static inline void amdgpu_reset_put_reset_domain(struct amdgpu_reset_domain *domain) |
| 113 | 115 | { |
| 114 | − kref_put(&domain->refcount, amdgpu_reset_destroy_reset_domain); | |
| 116 | + if (domain) | |
| 117 | + kref_put(&domain->refcount, amdgpu_reset_destroy_reset_domain); | |
| 115 | 118 | } |
| 116 | 119 | |
| 117 | 120 | static inline bool amdgpu_reset_domain_schedule(struct amdgpu_reset_domain *domain, |
| @@ -405,6 +405,9 @@ bool amdgpu_ring_soft_recovery(struct amdgpu_ring *ring, unsigned int vmid, · 404 unmodified lines | ||
| 405 | 405 | { |
| 406 | 406 | ktime_t deadline = ktime_add_us(ktime_get(), 10000); |
| 407 | 407 | |
| 408 | + if (!(ring->adev->amdgpu_reset_level_mask & AMDGPU_RESET_LEVEL_SOFT_RECOVERY)) | |
| 409 | + return false; | |
| 410 | + | |
| 408 | 411 | if (amdgpu_sriov_vf(ring->adev) || !ring->funcs->soft_recovery || !fence) |
| 409 | 412 | return false; |
| 410 | 413 | |
| @@ -359,6 +359,14 @@ static void amdgpu_gfx_rlc_init_microcode_v2_1(struct amdgpu_device *adev) · 358 unmodified lines | ||
| 359 | 359 | le32_to_cpu(rlc_hdr->reg_list_format_direct_reg_list_length); |
| 360 | 360 | |
| 361 | 361 | if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { |
| 362 | + if (adev->gfx.rlc.save_restore_list_cntl_size_bytes) { | |
| 363 | + info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL]; | |
| 364 | + info->ucode_id = AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL; | |
| 365 | + info->fw = adev->gfx.rlc_fw; | |
| 366 | + adev->firmware.fw_size += | |
| 367 | + ALIGN(adev->gfx.rlc.save_restore_list_cntl_size_bytes, PAGE_SIZE); | |
| 368 | + } | |
| 369 | + | |
| 362 | 370 | if (adev->gfx.rlc.save_restore_list_gpm_size_bytes) { |
| 363 | 371 | info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM]; |
| 364 | 372 | info->ucode_id = AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM; |
| @@ -21,6 +21,7 @@ · 20 unmodified lines | ||
| 21 | 21 | * |
| 22 | 22 | */ |
| 23 | 23 | |
| 24 | +#include <linux/firmware.h> | |
| 24 | 25 | #include "amdgpu.h" |
| 25 | 26 | #include "amdgpu_sdma.h" |
| 26 | 27 | #include "amdgpu_ras.h" |
| @@ -150,3 +151,135 @@ int amdgpu_sdma_process_ecc_irq(struct amdgpu_device *adev, · 123 unmodified lines | ||
| 150 | 151 | amdgpu_ras_interrupt_dispatch(adev, &ih_data); |
| 151 | 152 | return 0; |
| 152 | 153 | } |
| 154 | + | |
| 155 | +static int amdgpu_sdma_init_inst_ctx(struct amdgpu_sdma_instance *sdma_inst) | |
| 156 | +{ | |
| 157 | + int err = 0; | |
| 158 | + uint16_t version_major; | |
| 159 | + const struct common_firmware_header *header = NULL; | |
| 160 | + const struct sdma_firmware_header_v1_0 *hdr; | |
| 161 | + const struct sdma_firmware_header_v2_0 *hdr_v2; | |
| 162 | + | |
| 163 | + err = amdgpu_ucode_validate(sdma_inst->fw); | |
| 164 | + if (err) | |
| 165 | + return err; | |
| 166 | + | |
| 167 | + header = (const struct common_firmware_header *) | |
| 168 | + sdma_inst->fw->data; | |
| 169 | + version_major = le16_to_cpu(header->header_version_major); | |
| 170 | + | |
| 171 | + switch (version_major) { | |
| 172 | + case 1: | |
| 173 | + hdr = (const struct sdma_firmware_header_v1_0 *)sdma_inst->fw->data; | |
| 174 | + sdma_inst->fw_version = le32_to_cpu(hdr->header.ucode_version); | |
| 175 | + sdma_inst->feature_version = le32_to_cpu(hdr->ucode_feature_version); | |
| 176 | + break; | |
| 177 | + case 2: | |
| 178 | + hdr_v2 = (const struct sdma_firmware_header_v2_0 *)sdma_inst->fw->data; | |
| 179 | + sdma_inst->fw_version = le32_to_cpu(hdr_v2->header.ucode_version); | |
| 180 | + sdma_inst->feature_version = le32_to_cpu(hdr_v2->ucode_feature_version); | |
| 181 | + break; | |
| 182 | + default: | |
| 183 | + return -EINVAL; | |
| 184 | + } | |
| 185 | + | |
| 186 | + if (sdma_inst->feature_version >= 20) | |
| 187 | + sdma_inst->burst_nop = true; | |
| 188 | + | |
| 189 | + return 0; | |
| 190 | +} | |
| 191 | + | |
| 192 | +void amdgpu_sdma_destroy_inst_ctx(struct amdgpu_device *adev, | |
| 193 | + bool duplicate) | |
| 194 | +{ | |
| 195 | + int i; | |
| 196 | + | |
| 197 | + for (i = 0; i < adev->sdma.num_instances; i++) { | |
| 198 | + release_firmware(adev->sdma.instance[i].fw); | |
| 199 | + if (duplicate) | |
| 200 | + break; | |
| 201 | + } | |
| 202 | + | |
| 203 | + memset((void *)adev->sdma.instance, 0, | |
| 204 | + sizeof(struct amdgpu_sdma_instance) * AMDGPU_MAX_SDMA_INSTANCES); | |
| 205 | +} | |
| 206 | + | |
| 207 | +int amdgpu_sdma_init_microcode(struct amdgpu_device *adev, | |
| 208 | + char *fw_name, u32 instance, | |
| 209 | + bool duplicate) | |
| 210 | +{ | |
| 211 | + struct amdgpu_firmware_info *info = NULL; | |
| 212 | + const struct common_firmware_header *header = NULL; | |
| 213 | + int err = 0, i; | |
| 214 | + const struct sdma_firmware_header_v2_0 *sdma_hdr; | |
| 215 | + uint16_t version_major; | |
| 216 | + | |
| 217 | + err = request_firmware(&adev->sdma.instance[instance].fw, fw_name, adev->dev); | |
| 218 | + if (err) | |
| 219 | + goto out; | |
| 220 | + | |
| 221 | + header = (const struct common_firmware_header *) | |
| 222 | + adev->sdma.instance[instance].fw->data; | |
| 223 | + version_major = le16_to_cpu(header->header_version_major); | |
| 224 | + | |
| 225 | + if ((duplicate && instance) || (!duplicate && version_major > 1)) | |
| 226 | + return -EINVAL; | |
| 227 | + | |
| 228 | + err = amdgpu_sdma_init_inst_ctx(&adev->sdma.instance[instance]); | |
| 229 | + if (err) | |
| 230 | + goto out; | |
| 231 | + | |
| 232 | + if (duplicate) { | |
| 233 | + for (i = 1; i < adev->sdma.num_instances; i++) | |
| 234 | + memcpy((void *)&adev->sdma.instance[i], | |
| 235 | + (void *)&adev->sdma.instance[0], | |
| 236 | + sizeof(struct amdgpu_sdma_instance)); | |
| 237 | + } | |
| 238 | + | |
| 239 | + if (amdgpu_sriov_vf(adev)) | |
| 240 | + return 0; | |
| 241 | + | |
| 242 | + DRM_DEBUG("psp_load == '%s'\n", | |
| 243 | + adev->firmware.load_type == AMDGPU_FW_LOAD_PSP ? "true" : "false"); | |
| 244 | + | |
| 245 | + if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { | |
| 246 | + switch (version_major) { | |
| 247 | + case 1: | |
| 248 | + for (i = 0; i < adev->sdma.num_instances; i++) { | |
| 249 | + if (!duplicate && (instance != i)) | |
| 250 | + continue; | |
| 251 | + else { | |
| 252 | + info = &adev->firmware.ucode[AMDGPU_UCODE_ID_SDMA0 + i]; | |
| 253 | + info->ucode_id = AMDGPU_UCODE_ID_SDMA0 + i; | |
| 254 | + info->fw = adev->sdma.instance[i].fw; | |
| 255 | + adev->firmware.fw_size += | |
| 256 | + ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE); | |
| 257 | + } | |
| 258 | + } | |
| 259 | + break; | |
| 260 | + case 2: | |
| 261 | + sdma_hdr = (const struct sdma_firmware_header_v2_0 *) | |
| 262 | + adev->sdma.instance[0].fw->data; | |
| 263 | + info = &adev->firmware.ucode[AMDGPU_UCODE_ID_SDMA_UCODE_TH0]; | |
| 264 | + info->ucode_id = AMDGPU_UCODE_ID_SDMA_UCODE_TH0; | |
| 265 | + info->fw = adev->sdma.instance[0].fw; | |
| 266 | + adev->firmware.fw_size += | |
| 267 | + ALIGN(le32_to_cpu(sdma_hdr->ctx_ucode_size_bytes), PAGE_SIZE); | |
| 268 | + info = &adev->firmware.ucode[AMDGPU_UCODE_ID_SDMA_UCODE_TH1]; | |
| 269 | + info->ucode_id = AMDGPU_UCODE_ID_SDMA_UCODE_TH1; | |
| 270 | + info->fw = adev->sdma.instance[0].fw; | |
| 271 | + adev->firmware.fw_size += | |
| 272 | + ALIGN(le32_to_cpu(sdma_hdr->ctl_ucode_size_bytes), PAGE_SIZE); | |
| 273 | + break; | |
| 274 | + default: | |
| 275 | + return -EINVAL; | |
| 276 | + } | |
| 277 | + } | |
| 278 | + | |
| 279 | +out: | |
| 280 | + if (err) { | |
| 281 | + DRM_ERROR("SDMA: Failed to init firmware \"%s\"\n", fw_name); | |
| 282 | + amdgpu_sdma_destroy_inst_ctx(adev, duplicate); | |
| 283 | + } | |
| 284 | + return err; | |
| 285 | +} | |
| @@ -124,4 +124,8 @@ int amdgpu_sdma_process_ras_data_cb(struct amdgpu_device *adev, · 123 unmodified lines | ||
| 124 | 124 | int amdgpu_sdma_process_ecc_irq(struct amdgpu_device *adev, |
| 125 | 125 | struct amdgpu_irq_src *source, |
| 126 | 126 | struct amdgpu_iv_entry *entry); |
| 127 | +int amdgpu_sdma_init_microcode(struct amdgpu_device *adev, | |
| 128 | + char *fw_name, u32 instance, bool duplicate); | |
| 129 | +void amdgpu_sdma_destroy_inst_ctx(struct amdgpu_device *adev, | |
| 130 | + bool duplicate); | |
| 127 | 131 | #endif |
| @@ -1,3 +1,4 @@ | ||
| 1 | +// SPDX-License-Identifier: MIT | |
| 1 | 2 | /* |
| 2 | 3 | * Copyright 2014 Advanced Micro Devices, Inc. |
| 3 | 4 | * All Rights Reserved. |
| @@ -315,6 +316,7 @@ struct dma_fence *amdgpu_sync_get_fence(struct amdgpu_sync *sync) · 311 unmodified lines | ||
| 315 | 316 | struct hlist_node *tmp; |
| 316 | 317 | struct dma_fence *f; |
| 317 | 318 | int i; |
| 319 | + | |
| 318 | 320 | hash_for_each_safe(sync->fences, i, tmp, e, node) { |
| 319 | 321 | |
| 320 | 322 | f = e->fence; |
| @@ -392,7 +394,7 @@ void amdgpu_sync_free(struct amdgpu_sync *sync) · 71 unmodified lines | ||
| 392 | 394 | { |
| 393 | 395 | struct amdgpu_sync_entry *e; |
| 394 | 396 | struct hlist_node *tmp; |
| 395 | − unsigned i; | |
| 397 | + unsigned int i; | |
| 396 | 398 | |
| 397 | 399 | hash_for_each_safe(sync->fences, i, tmp, e, node) { |
| 398 | 400 | hash_del(&e->node); |
| @@ -140,8 +140,10 @@ TRACE_EVENT(amdgpu_bo_create, · 139 unmodified lines | ||
| 140 | 140 | ); |
| 141 | 141 | |
| 142 | 142 | TRACE_EVENT(amdgpu_cs, |
| 143 | − TP_PROTO(struct amdgpu_cs_parser *p, int i), | |
| 144 | − TP_ARGS(p, i), | |
| 143 | + TP_PROTO(struct amdgpu_cs_parser *p, | |
| 144 | + struct amdgpu_job *job, | |
| 145 | + struct amdgpu_ib *ib), | |
| 146 | + TP_ARGS(p, job, ib), | |
| 145 | 147 | TP_STRUCT__entry( |
| 146 | 148 | __field(struct amdgpu_bo_list *, bo_list) |
| 147 | 149 | __field(u32, ring) |
| @@ -151,10 +153,10 @@ TRACE_EVENT(amdgpu_cs, · 3 unmodified lines | ||
| 151 | 153 | |
| 152 | 154 | TP_fast_assign( |
| 153 | 155 | __entry->bo_list = p->bo_list; |
| 154 | − __entry->ring = to_amdgpu_ring(p->entity->rq->sched)->idx; | |
| 155 | − __entry->dw = p->job->ibs[i].length_dw; | |
| 156 | + __entry->ring = to_amdgpu_ring(job->base.sched)->idx; | |
| 157 | + __entry->dw = ib->length_dw; | |
| 156 | 158 | __entry->fences = amdgpu_fence_count_emitted( |
| 157 | − to_amdgpu_ring(p->entity->rq->sched)); | |
| 159 | + to_amdgpu_ring(job->base.sched)); | |
| 158 | 160 | ), |
| 159 | 161 | TP_printk("bo_list=%p, ring=%u, dw=%u, fences=%u", |
| 160 | 162 | __entry->bo_list, __entry->ring, __entry->dw, |
| @@ -471,7 +471,8 @@ static int amdgpu_bo_move(struct ttm_buffer_object *bo, bool evict, · 470 unmodified lines | ||
| 471 | 471 | |
| 472 | 472 | adev = amdgpu_ttm_adev(bo->bdev); |
| 473 | 473 | |
| 474 | − if (old_mem->mem_type == TTM_PL_SYSTEM && bo->ttm == NULL) { | |
| 474 | + if (!old_mem || (old_mem->mem_type == TTM_PL_SYSTEM && | |
| 475 | + bo->ttm == NULL)) { | |
| 475 | 476 | ttm_bo_move_null(bo, new_mem); |
| 476 | 477 | goto out; |
| 477 | 478 | } |
| @@ -1329,11 +1330,12 @@ uint64_t amdgpu_ttm_tt_pte_flags(struct amdgpu_device *adev, struct ttm_tt *ttm, · 851 unmodified lines | ||
| 1329 | 1330 | static bool amdgpu_ttm_bo_eviction_valuable(struct ttm_buffer_object *bo, |
| 1330 | 1331 | const struct ttm_place *place) |
| 1331 | 1332 | { |
| 1332 | − unsigned long num_pages = bo->resource->num_pages; | |
| 1333 | 1333 | struct dma_resv_iter resv_cursor; |
| 1334 | − struct amdgpu_res_cursor cursor; | |
| 1335 | 1334 | struct dma_fence *f; |
| 1336 | 1335 | |
| 1336 | + if (!amdgpu_bo_is_amdgpu_bo(bo)) | |
| 1337 | + return ttm_bo_eviction_valuable(bo, place); | |
| 1338 | + | |
| 1337 | 1339 | /* Swapout? */ |
| 1338 | 1340 | if (bo->resource->mem_type == TTM_PL_SYSTEM) |
| 1339 | 1341 | return true; |
| @@ -1352,40 +1354,20 @@ static bool amdgpu_ttm_bo_eviction_valuable(struct ttm_buffer_object *bo, · 12 unmodified lines | ||
| 1352 | 1354 | return false; |
| 1353 | 1355 | } |
| 1354 | 1356 | |
| 1355 | − switch (bo->resource->mem_type) { | |
| 1356 | − case AMDGPU_PL_PREEMPT: | |
| 1357 | − /* Preemptible BOs don't own system resources managed by the | |
| 1358 | − * driver (pages, VRAM, GART space). They point to resources | |
| 1359 | − * owned by someone else (e.g. pageable memory in user mode | |
| 1360 | − * or a DMABuf). They are used in a preemptible context so we | |
| 1361 | − * can guarantee no deadlocks and good QoS in case of MMU | |
| 1362 | − * notifiers or DMABuf move notifiers from the resource owner. | |
| 1363 | − */ | |
| 1357 | + /* Preemptible BOs don't own system resources managed by the | |
| 1358 | + * driver (pages, VRAM, GART space). They point to resources | |
| 1359 | + * owned by someone else (e.g. pageable memory in user mode | |
| 1360 | + * or a DMABuf). They are used in a preemptible context so we | |
| 1361 | + * can guarantee no deadlocks and good QoS in case of MMU | |
| 1362 | + * notifiers or DMABuf move notifiers from the resource owner. | |
| 1363 | + */ | |
| 1364 | + if (bo->resource->mem_type == AMDGPU_PL_PREEMPT) | |
| 1364 | 1365 | return false; |
| 1365 | − case TTM_PL_TT: | |
| 1366 | − if (amdgpu_bo_is_amdgpu_bo(bo) && | |
| 1367 | − amdgpu_bo_encrypted(ttm_to_amdgpu_bo(bo))) | |
| 1368 | − return false; | |
| 1369 | − return true; | |
| 1370 | 1366 | |
| 1371 | − case TTM_PL_VRAM: | |
| 1372 | − /* Check each drm MM node individually */ | |
| 1373 | − amdgpu_res_first(bo->resource, 0, (u64)num_pages << PAGE_SHIFT, | |
| 1374 | − &cursor); | |
| 1375 | − while (cursor.remaining) { | |
| 1376 | − if (place->fpfn < PFN_DOWN(cursor.start + cursor.size) | |
| 1377 | − && !(place->lpfn && | |
| 1378 | − place->lpfn <= PFN_DOWN(cursor.start))) | |
| 1379 | − return true; | |
| 1380 | − | |
| 1381 | − amdgpu_res_next(&cursor, cursor.size); | |
| 1382 | − } | |
| 1367 | + if (bo->resource->mem_type == TTM_PL_TT && | |
| 1368 | + amdgpu_bo_encrypted(ttm_to_amdgpu_bo(bo))) | |
| 1383 | 1369 | return false; |
| 1384 | 1370 | |
| 1385 | − default: | |
| 1386 | − break; | |
| 1387 | − } | |
| 1388 | − | |
| 1389 | 1371 | return ttm_bo_eviction_valuable(bo, place); |
| 1390 | 1372 | } |
| 1391 | 1373 | |
| @@ -164,70 +164,138 @@ void amdgpu_ucode_print_rlc_hdr(const struct common_firmware_header *hdr) · 163 unmodified lines | ||
| 164 | 164 | } else if (version_major == 2) { |
| 165 | 165 | const struct rlc_firmware_header_v2_0 *rlc_hdr = |
| 166 | 166 | container_of(hdr, struct rlc_firmware_header_v2_0, header); |
| 167 | + const struct rlc_firmware_header_v2_1 *rlc_hdr_v2_1 = | |
| 168 | + container_of(rlc_hdr, struct rlc_firmware_header_v2_1, v2_0); | |
| 169 | + const struct rlc_firmware_header_v2_2 *rlc_hdr_v2_2 = | |
| 170 | + container_of(rlc_hdr_v2_1, struct rlc_firmware_header_v2_2, v2_1); | |
| 171 | + const struct rlc_firmware_header_v2_3 *rlc_hdr_v2_3 = | |
| 172 | + container_of(rlc_hdr_v2_2, struct rlc_firmware_header_v2_3, v2_2); | |
| 173 | + const struct rlc_firmware_header_v2_4 *rlc_hdr_v2_4 = | |
| 174 | + container_of(rlc_hdr_v2_3, struct rlc_firmware_header_v2_4, v2_3); | |
| 167 | 175 | |
| 168 | − DRM_DEBUG("ucode_feature_version: %u\n", | |
| 169 | − le32_to_cpu(rlc_hdr->ucode_feature_version)); | |
| 170 | − DRM_DEBUG("jt_offset: %u\n", le32_to_cpu(rlc_hdr->jt_offset)); | |
| 171 | − DRM_DEBUG("jt_size: %u\n", le32_to_cpu(rlc_hdr->jt_size)); | |
| 172 | − DRM_DEBUG("save_and_restore_offset: %u\n", | |
| 173 | − le32_to_cpu(rlc_hdr->save_and_restore_offset)); | |
| 174 | − DRM_DEBUG("clear_state_descriptor_offset: %u\n", | |
| 175 | − le32_to_cpu(rlc_hdr->clear_state_descriptor_offset)); | |
| 176 | − DRM_DEBUG("avail_scratch_ram_locations: %u\n", | |
| 177 | − le32_to_cpu(rlc_hdr->avail_scratch_ram_locations)); | |
| 178 | − DRM_DEBUG("reg_restore_list_size: %u\n", | |
| 179 | − le32_to_cpu(rlc_hdr->reg_restore_list_size)); | |
| 180 | − DRM_DEBUG("reg_list_format_start: %u\n", | |
| 181 | − le32_to_cpu(rlc_hdr->reg_list_format_start)); | |
| 182 | − DRM_DEBUG("reg_list_format_separate_start: %u\n", | |
| 183 | − le32_to_cpu(rlc_hdr->reg_list_format_separate_start)); | |
| 184 | − DRM_DEBUG("starting_offsets_start: %u\n", | |
| 185 | − le32_to_cpu(rlc_hdr->starting_offsets_start)); | |
| 186 | − DRM_DEBUG("reg_list_format_size_bytes: %u\n", | |
| 187 | − le32_to_cpu(rlc_hdr->reg_list_format_size_bytes)); | |
| 188 | − DRM_DEBUG("reg_list_format_array_offset_bytes: %u\n", | |
| 189 | − le32_to_cpu(rlc_hdr->reg_list_format_array_offset_bytes)); | |
| 190 | − DRM_DEBUG("reg_list_size_bytes: %u\n", | |
| 191 | − le32_to_cpu(rlc_hdr->reg_list_size_bytes)); | |
| 192 | − DRM_DEBUG("reg_list_array_offset_bytes: %u\n", | |
| 193 | − le32_to_cpu(rlc_hdr->reg_list_array_offset_bytes)); | |
| 194 | − DRM_DEBUG("reg_list_format_separate_size_bytes: %u\n", | |
| 195 | − le32_to_cpu(rlc_hdr->reg_list_format_separate_size_bytes)); | |
| 196 | − DRM_DEBUG("reg_list_format_separate_array_offset_bytes: %u\n", | |
| 197 | − le32_to_cpu(rlc_hdr->reg_list_format_separate_array_offset_bytes)); | |
| 198 | − DRM_DEBUG("reg_list_separate_size_bytes: %u\n", | |
| 199 | − le32_to_cpu(rlc_hdr->reg_list_separate_size_bytes)); | |
| 200 | − DRM_DEBUG("reg_list_separate_array_offset_bytes: %u\n", | |
| 201 | − le32_to_cpu(rlc_hdr->reg_list_separate_array_offset_bytes)); | |
| 202 | − if (version_minor == 1) { | |
| 203 | − const struct rlc_firmware_header_v2_1 *v2_1 = | |
| 204 | − container_of(rlc_hdr, struct rlc_firmware_header_v2_1, v2_0); | |
| 176 | + switch (version_minor) { | |
| 177 | + case 0: | |
| 178 | + /* rlc_hdr v2_0 */ | |
| 179 | + DRM_DEBUG("ucode_feature_version: %u\n", | |
| 180 | + le32_to_cpu(rlc_hdr->ucode_feature_version)); | |
| 181 | + DRM_DEBUG("jt_offset: %u\n", le32_to_cpu(rlc_hdr->jt_offset)); | |
| 182 | + DRM_DEBUG("jt_size: %u\n", le32_to_cpu(rlc_hdr->jt_size)); | |
| 183 | + DRM_DEBUG("save_and_restore_offset: %u\n", | |
| 184 | + le32_to_cpu(rlc_hdr->save_and_restore_offset)); | |
| 185 | + DRM_DEBUG("clear_state_descriptor_offset: %u\n", | |
| 186 | + le32_to_cpu(rlc_hdr->clear_state_descriptor_offset)); | |
| 187 | + DRM_DEBUG("avail_scratch_ram_locations: %u\n", | |
| 188 | + le32_to_cpu(rlc_hdr->avail_scratch_ram_locations)); | |
| 189 | + DRM_DEBUG("reg_restore_list_size: %u\n", | |
| 190 | + le32_to_cpu(rlc_hdr->reg_restore_list_size)); | |
| 191 | + DRM_DEBUG("reg_list_format_start: %u\n", | |
| 192 | + le32_to_cpu(rlc_hdr->reg_list_format_start)); | |
| 193 | + DRM_DEBUG("reg_list_format_separate_start: %u\n", | |
| 194 | + le32_to_cpu(rlc_hdr->reg_list_format_separate_start)); | |
| 195 | + DRM_DEBUG("starting_offsets_start: %u\n", | |
| 196 | + le32_to_cpu(rlc_hdr->starting_offsets_start)); | |
| 197 | + DRM_DEBUG("reg_list_format_size_bytes: %u\n", | |
| 198 | + le32_to_cpu(rlc_hdr->reg_list_format_size_bytes)); | |
| 199 | + DRM_DEBUG("reg_list_format_array_offset_bytes: %u\n", | |
| 200 | + le32_to_cpu(rlc_hdr->reg_list_format_array_offset_bytes)); | |
| 201 | + DRM_DEBUG("reg_list_size_bytes: %u\n", | |
| 202 | + le32_to_cpu(rlc_hdr->reg_list_size_bytes)); | |
| 203 | + DRM_DEBUG("reg_list_array_offset_bytes: %u\n", | |
| 204 | + le32_to_cpu(rlc_hdr->reg_list_array_offset_bytes)); | |
| 205 | + DRM_DEBUG("reg_list_format_separate_size_bytes: %u\n", | |
| 206 | + le32_to_cpu(rlc_hdr->reg_list_format_separate_size_bytes)); | |
| 207 | + DRM_DEBUG("reg_list_format_separate_array_offset_bytes: %u\n", | |
| 208 | + le32_to_cpu(rlc_hdr->reg_list_format_separate_array_offset_bytes)); | |
| 209 | + DRM_DEBUG("reg_list_separate_size_bytes: %u\n", | |
| 210 | + le32_to_cpu(rlc_hdr->reg_list_separate_size_bytes)); | |
| 211 | + DRM_DEBUG("reg_list_separate_array_offset_bytes: %u\n", | |
| 212 | + le32_to_cpu(rlc_hdr->reg_list_separate_array_offset_bytes)); | |
| 213 | + break; | |
| 214 | + case 1: | |
| 215 | + /* rlc_hdr v2_1 */ | |
| 205 | 216 | DRM_DEBUG("reg_list_format_direct_reg_list_length: %u\n", |
| 206 | − le32_to_cpu(v2_1->reg_list_format_direct_reg_list_length)); | |
| 217 | + le32_to_cpu(rlc_hdr_v2_1->reg_list_format_direct_reg_list_length)); | |
| 207 | 218 | DRM_DEBUG("save_restore_list_cntl_ucode_ver: %u\n", |
| 208 | − le32_to_cpu(v2_1->save_restore_list_cntl_ucode_ver)); | |
| 219 | + le32_to_cpu(rlc_hdr_v2_1->save_restore_list_cntl_ucode_ver)); | |
| 209 | 220 | DRM_DEBUG("save_restore_list_cntl_feature_ver: %u\n", |
| 210 | − le32_to_cpu(v2_1->save_restore_list_cntl_feature_ver)); | |
| 221 | + le32_to_cpu(rlc_hdr_v2_1->save_restore_list_cntl_feature_ver)); | |
| 211 | 222 | DRM_DEBUG("save_restore_list_cntl_size_bytes %u\n", |
| 212 | − le32_to_cpu(v2_1->save_restore_list_cntl_size_bytes)); | |
| 223 | + le32_to_cpu(rlc_hdr_v2_1->save_restore_list_cntl_size_bytes)); | |
| 213 | 224 | DRM_DEBUG("save_restore_list_cntl_offset_bytes: %u\n", |
| 214 | − le32_to_cpu(v2_1->save_restore_list_cntl_offset_bytes)); | |
| 225 | + le32_to_cpu(rlc_hdr_v2_1->save_restore_list_cntl_offset_bytes)); | |
| 215 | 226 | DRM_DEBUG("save_restore_list_gpm_ucode_ver: %u\n", |
| 216 | − le32_to_cpu(v2_1->save_restore_list_gpm_ucode_ver)); | |
| 227 | + le32_to_cpu(rlc_hdr_v2_1->save_restore_list_gpm_ucode_ver)); | |
| 217 | 228 | DRM_DEBUG("save_restore_list_gpm_feature_ver: %u\n", |
| 218 | − le32_to_cpu(v2_1->save_restore_list_gpm_feature_ver)); | |
| 229 | + le32_to_cpu(rlc_hdr_v2_1->save_restore_list_gpm_feature_ver)); | |
| 219 | 230 | DRM_DEBUG("save_restore_list_gpm_size_bytes %u\n", |
| 220 | − le32_to_cpu(v2_1->save_restore_list_gpm_size_bytes)); | |
| 231 | + le32_to_cpu(rlc_hdr_v2_1->save_restore_list_gpm_size_bytes)); | |
| 221 | 232 | DRM_DEBUG("save_restore_list_gpm_offset_bytes: %u\n", |
| 222 | − le32_to_cpu(v2_1->save_restore_list_gpm_offset_bytes)); | |
| 233 | + le32_to_cpu(rlc_hdr_v2_1->save_restore_list_gpm_offset_bytes)); | |
| 223 | 234 | DRM_DEBUG("save_restore_list_srm_ucode_ver: %u\n", |
| 224 | − le32_to_cpu(v2_1->save_restore_list_srm_ucode_ver)); | |
| 235 | + le32_to_cpu(rlc_hdr_v2_1->save_restore_list_srm_ucode_ver)); | |
| 225 | 236 | DRM_DEBUG("save_restore_list_srm_feature_ver: %u\n", |
| 226 | − le32_to_cpu(v2_1->save_restore_list_srm_feature_ver)); | |
| 237 | + le32_to_cpu(rlc_hdr_v2_1->save_restore_list_srm_feature_ver)); | |
| 227 | 238 | DRM_DEBUG("save_restore_list_srm_size_bytes %u\n", |
| 228 | − le32_to_cpu(v2_1->save_restore_list_srm_size_bytes)); | |
| 239 | + le32_to_cpu(rlc_hdr_v2_1->save_restore_list_srm_size_bytes)); | |
| 229 | 240 | DRM_DEBUG("save_restore_list_srm_offset_bytes: %u\n", |
| 230 | − le32_to_cpu(v2_1->save_restore_list_srm_offset_bytes)); | |
| 241 | + le32_to_cpu(rlc_hdr_v2_1->save_restore_list_srm_offset_bytes)); | |
| 242 | + break; | |
| 243 | + case 2: | |
| 244 | + /* rlc_hdr v2_2 */ | |
| 245 | + DRM_DEBUG("rlc_iram_ucode_size_bytes: %u\n", | |
| 246 | + le32_to_cpu(rlc_hdr_v2_2->rlc_iram_ucode_size_bytes)); | |
| 247 | + DRM_DEBUG("rlc_iram_ucode_offset_bytes: %u\n", | |
| 248 | + le32_to_cpu(rlc_hdr_v2_2->rlc_iram_ucode_offset_bytes)); | |
| 249 | + DRM_DEBUG("rlc_dram_ucode_size_bytes: %u\n", | |
| 250 | + le32_to_cpu(rlc_hdr_v2_2->rlc_dram_ucode_size_bytes)); | |
| 251 | + DRM_DEBUG("rlc_dram_ucode_offset_bytes: %u\n", | |
| 252 | + le32_to_cpu(rlc_hdr_v2_2->rlc_dram_ucode_offset_bytes)); | |
| 253 | + break; | |
| 254 | + case 3: | |
| 255 | + /* rlc_hdr v2_3 */ | |
| 256 | + DRM_DEBUG("rlcp_ucode_version: %u\n", | |
| 257 | + le32_to_cpu(rlc_hdr_v2_3->rlcp_ucode_version)); | |
| 258 | + DRM_DEBUG("rlcp_ucode_feature_version: %u\n", | |
| 259 | + le32_to_cpu(rlc_hdr_v2_3->rlcp_ucode_feature_version)); | |
| 260 | + DRM_DEBUG("rlcp_ucode_size_bytes: %u\n", | |
| 261 | + le32_to_cpu(rlc_hdr_v2_3->rlcp_ucode_size_bytes)); | |
| 262 | + DRM_DEBUG("rlcp_ucode_offset_bytes: %u\n", | |
| 263 | + le32_to_cpu(rlc_hdr_v2_3->rlcp_ucode_offset_bytes)); | |
| 264 | + DRM_DEBUG("rlcv_ucode_version: %u\n", | |
| 265 | + le32_to_cpu(rlc_hdr_v2_3->rlcv_ucode_version)); | |
| 266 | + DRM_DEBUG("rlcv_ucode_feature_version: %u\n", | |
| 267 | + le32_to_cpu(rlc_hdr_v2_3->rlcv_ucode_feature_version)); | |
| 268 | + DRM_DEBUG("rlcv_ucode_size_bytes: %u\n", | |
| 269 | + le32_to_cpu(rlc_hdr_v2_3->rlcv_ucode_size_bytes)); | |
| 270 | + DRM_DEBUG("rlcv_ucode_offset_bytes: %u\n", | |
| 271 | + le32_to_cpu(rlc_hdr_v2_3->rlcv_ucode_offset_bytes)); | |
| 272 | + break; | |
| 273 | + case 4: | |
| 274 | + /* rlc_hdr v2_4 */ | |
| 275 | + DRM_DEBUG("global_tap_delays_ucode_size_bytes :%u\n", | |
| 276 | + le32_to_cpu(rlc_hdr_v2_4->global_tap_delays_ucode_size_bytes)); | |
| 277 | + DRM_DEBUG("global_tap_delays_ucode_offset_bytes: %u\n", | |
| 278 | + le32_to_cpu(rlc_hdr_v2_4->global_tap_delays_ucode_offset_bytes)); | |
| 279 | + DRM_DEBUG("se0_tap_delays_ucode_size_bytes :%u\n", | |
| 280 | + le32_to_cpu(rlc_hdr_v2_4->se0_tap_delays_ucode_size_bytes)); | |
| 281 | + DRM_DEBUG("se0_tap_delays_ucode_offset_bytes: %u\n", | |
| 282 | + le32_to_cpu(rlc_hdr_v2_4->se0_tap_delays_ucode_offset_bytes)); | |
| 283 | + DRM_DEBUG("se1_tap_delays_ucode_size_bytes :%u\n", | |
| 284 | + le32_to_cpu(rlc_hdr_v2_4->se1_tap_delays_ucode_size_bytes)); | |
| 285 | + DRM_DEBUG("se1_tap_delays_ucode_offset_bytes: %u\n", | |
| 286 | + le32_to_cpu(rlc_hdr_v2_4->se1_tap_delays_ucode_offset_bytes)); | |
| 287 | + DRM_DEBUG("se2_tap_delays_ucode_size_bytes :%u\n", | |
| 288 | + le32_to_cpu(rlc_hdr_v2_4->se2_tap_delays_ucode_size_bytes)); | |
| 289 | + DRM_DEBUG("se2_tap_delays_ucode_offset_bytes: %u\n", | |
| 290 | + le32_to_cpu(rlc_hdr_v2_4->se2_tap_delays_ucode_offset_bytes)); | |
| 291 | + DRM_DEBUG("se3_tap_delays_ucode_size_bytes :%u\n", | |
| 292 | + le32_to_cpu(rlc_hdr_v2_4->se3_tap_delays_ucode_size_bytes)); | |
| 293 | + DRM_DEBUG("se3_tap_delays_ucode_offset_bytes: %u\n", | |
| 294 | + le32_to_cpu(rlc_hdr_v2_4->se3_tap_delays_ucode_offset_bytes)); | |
| 295 | + break; | |
| 296 | + default: | |
| 297 | + DRM_ERROR("Unknown RLC v2 ucode: v2.%u\n", version_minor); | |
| 298 | + break; | |
| 231 | 299 | } |
| 232 | 300 | } else { |
| 233 | 301 | DRM_ERROR("Unknown RLC ucode version: %u.%u\n", version_major, version_minor); |
| @@ -124,6 +124,7 @@ enum psp_fw_type { · 123 unmodified lines | ||
| 124 | 124 | PSP_FW_TYPE_PSP_SOC_DRV, |
| 125 | 125 | PSP_FW_TYPE_PSP_INTF_DRV, |
| 126 | 126 | PSP_FW_TYPE_PSP_DBG_DRV, |
| 127 | + PSP_FW_TYPE_PSP_RAS_DRV, | |
| 127 | 128 | }; |
| 128 | 129 | |
| 129 | 130 | /* version_major=2, version_minor=0 */ |
| @@ -22,6 +22,8 @@ · 21 unmodified lines | ||
| 22 | 22 | #define __AMDGPU_UMC_H__ |
| 23 | 23 | #include "amdgpu_ras.h" |
| 24 | 24 | |
| 25 | +#define UMC_INVALID_ADDR 0x1ULL | |
| 26 | + | |
| 25 | 27 | /* |
| 26 | 28 | * (addr / 256) * 4096, the higher 26 bits in ErrorAddr |
| 27 | 29 | * is the index of 4KB block |
| @@ -51,6 +53,10 @@ struct amdgpu_umc_ras { · 23 unmodified lines | ||
| 51 | 53 | struct amdgpu_ras_block_object ras_block; |
| 52 | 54 | void (*err_cnt_init)(struct amdgpu_device *adev); |
| 53 | 55 | bool (*query_ras_poison_mode)(struct amdgpu_device *adev); |
| 56 | + void (*convert_ras_error_address)(struct amdgpu_device *adev, | |
| 57 | + struct ras_err_data *err_data, | |
| 58 | + uint32_t umc_reg_offset, uint32_t ch_inst, | |
| 59 | + uint32_t umc_inst, uint64_t mca_addr); | |
| 54 | 60 | void (*ecc_info_query_ras_error_count)(struct amdgpu_device *adev, |
| 55 | 61 | void *ras_error_status); |
| 56 | 62 | void (*ecc_info_query_ras_error_address)(struct amdgpu_device *adev, |
| @@ -161,6 +161,8 @@ · 160 unmodified lines | ||
| 161 | 161 | #define AMDGPU_VCN_SW_RING_FLAG (1 << 9) |
| 162 | 162 | #define AMDGPU_VCN_FW_LOGGING_FLAG (1 << 10) |
| 163 | 163 | #define AMDGPU_VCN_SMU_VERSION_INFO_FLAG (1 << 11) |
| 164 | +#define AMDGPU_VCN_SMU_DPM_INTERFACE_FLAG (1 << 11) | |
| 165 | +#define AMDGPU_VCN_VF_RB_SETUP_FLAG (1 << 14) | |
| 164 | 166 | |
| 165 | 167 | #define AMDGPU_VCN_IB_FLAG_DECODE_BUFFER 0x00000001 |
| 166 | 168 | #define AMDGPU_VCN_CMD_FLAG_MSG_BUFFER 0x00000001 |
| @@ -170,6 +172,9 @@ · 3 unmodified lines | ||
| 170 | 172 | #define VCN_CODEC_DISABLE_MASK_HEVC (1 << 2) |
| 171 | 173 | #define VCN_CODEC_DISABLE_MASK_H264 (1 << 3) |
| 172 | 174 | |
| 175 | +#define AMDGPU_VCN_SMU_DPM_INTERFACE_DGPU (0) | |
| 176 | +#define AMDGPU_VCN_SMU_DPM_INTERFACE_APU (1) | |
| 177 | + | |
| 173 | 178 | enum fw_queue_mode { |
| 174 | 179 | FW_QUEUE_RING_RESET = 1, |
| 175 | 180 | FW_QUEUE_DPG_HOLD_OFF = 2, |
| @@ -317,12 +322,26 @@ struct amdgpu_fw_shared { · 141 unmodified lines | ||
| 317 | 322 | struct amdgpu_fw_shared_smu_interface_info smu_interface_info; |
| 318 | 323 | }; |
| 319 | 324 | |
| 325 | +struct amdgpu_fw_shared_rb_setup { | |
| 326 | + uint32_t is_rb_enabled_flags; | |
| 327 | + uint32_t rb_addr_lo; | |
| 328 | + uint32_t rb_addr_hi; | |
| 329 | + uint32_t rb_size; | |
| 330 | + uint32_t rb4_addr_lo; | |
| 331 | + uint32_t rb4_addr_hi; | |
| 332 | + uint32_t rb4_size; | |
| 333 | + uint32_t reserved[6]; | |
| 334 | +}; | |
| 335 | + | |
| 320 | 336 | struct amdgpu_vcn4_fw_shared { |
| 321 | 337 | uint32_t present_flag_0; |
| 322 | 338 | uint8_t pad[12]; |
| 323 | 339 | struct amdgpu_fw_shared_unified_queue_struct sq; |
| 324 | 340 | uint8_t pad1[8]; |
| 325 | 341 | struct amdgpu_fw_shared_fw_logging fw_log; |
| 342 | + uint8_t pad2[20]; | |
| 343 | + struct amdgpu_fw_shared_rb_setup rb_setup; | |
| 344 | + struct amdgpu_fw_shared_smu_interface_info smu_dpm_interface; | |
| 326 | 345 | }; |
| 327 | 346 | |
| 328 | 347 | struct amdgpu_vcn_fwlog { |
| @@ -690,7 +690,6 @@ void amdgpu_virt_exchange_data(struct amdgpu_device *adev) · 689 unmodified lines | ||
| 690 | 690 | } |
| 691 | 691 | } |
| 692 | 692 | |
| 693 | − | |
| 694 | 693 | void amdgpu_detect_virtualization(struct amdgpu_device *adev) |
| 695 | 694 | { |
| 696 | 695 | uint32_t reg; |
| @@ -707,6 +706,7 @@ void amdgpu_detect_virtualization(struct amdgpu_device *adev) · 10 unmodified lines | ||
| 707 | 706 | case CHIP_SIENNA_CICHLID: |
| 708 | 707 | case CHIP_ARCTURUS: |
| 709 | 708 | case CHIP_ALDEBARAN: |
| 709 | + case CHIP_IP_DISCOVERY: | |
| 710 | 710 | reg = RREG32(mmRCC_IOV_FUNC_IDENTIFIER); |
| 711 | 711 | break; |
| 712 | 712 | default: /* other chip doesn't support SRIOV */ |
| @@ -750,6 +750,7 @@ void amdgpu_detect_virtualization(struct amdgpu_device *adev) · 37 unmodified lines | ||
| 750 | 750 | case CHIP_NAVI10: |
| 751 | 751 | case CHIP_NAVI12: |
| 752 | 752 | case CHIP_SIENNA_CICHLID: |
| 753 | + case CHIP_IP_DISCOVERY: | |
| 753 | 754 | nv_set_virt_ops(adev); |
| 754 | 755 | /* try send GPU_INIT_DATA request to host */ |
| 755 | 756 | amdgpu_virt_request_init_data(adev); |
| @@ -807,6 +808,60 @@ enum amdgpu_sriov_vf_mode amdgpu_virt_get_sriov_vf_mode(struct amdgpu_device *ad · 51 unmodified lines | ||
| 807 | 808 | return mode; |
| 808 | 809 | } |
| 809 | 810 | |
| 811 | +bool amdgpu_virt_fw_load_skip_check(struct amdgpu_device *adev, uint32_t ucode_id) | |
| 812 | +{ | |
| 813 | + switch (adev->ip_versions[MP0_HWIP][0]) { | |
| 814 | + case IP_VERSION(13, 0, 0): | |
| 815 | + /* no vf autoload, white list */ | |
| 816 | + if (ucode_id == AMDGPU_UCODE_ID_VCN1 || | |
| 817 | + ucode_id == AMDGPU_UCODE_ID_VCN) | |
| 818 | + return false; | |
| 819 | + else | |
| 820 | + return true; | |
| 821 | + case IP_VERSION(13, 0, 10): | |
| 822 | + /* white list */ | |
| 823 | + if (ucode_id == AMDGPU_UCODE_ID_CAP | |
| 824 | + || ucode_id == AMDGPU_UCODE_ID_CP_RS64_PFP | |
| 825 | + || ucode_id == AMDGPU_UCODE_ID_CP_RS64_ME | |
| 826 | + || ucode_id == AMDGPU_UCODE_ID_CP_RS64_MEC | |
| 827 | + || ucode_id == AMDGPU_UCODE_ID_CP_RS64_PFP_P0_STACK | |
| 828 | + || ucode_id == AMDGPU_UCODE_ID_CP_RS64_PFP_P1_STACK | |
| 829 | + || ucode_id == AMDGPU_UCODE_ID_CP_RS64_ME_P0_STACK | |
| 830 | + || ucode_id == AMDGPU_UCODE_ID_CP_RS64_ME_P1_STACK | |
| 831 | + || ucode_id == AMDGPU_UCODE_ID_CP_RS64_MEC_P0_STACK | |
| 832 | + || ucode_id == AMDGPU_UCODE_ID_CP_RS64_MEC_P1_STACK | |
| 833 | + || ucode_id == AMDGPU_UCODE_ID_CP_RS64_MEC_P2_STACK | |
| 834 | + || ucode_id == AMDGPU_UCODE_ID_CP_RS64_MEC_P3_STACK | |
| 835 | + || ucode_id == AMDGPU_UCODE_ID_CP_MES | |
| 836 | + || ucode_id == AMDGPU_UCODE_ID_CP_MES_DATA | |
| 837 | + || ucode_id == AMDGPU_UCODE_ID_CP_MES1 | |
| 838 | + || ucode_id == AMDGPU_UCODE_ID_CP_MES1_DATA | |
| 839 | + || ucode_id == AMDGPU_UCODE_ID_VCN1 | |
| 840 | + || ucode_id == AMDGPU_UCODE_ID_VCN) | |
| 841 | + return false; | |
| 842 | + else | |
| 843 | + return true; | |
| 844 | + default: | |
| 845 | + /* lagacy black list */ | |
| 846 | + if (ucode_id == AMDGPU_UCODE_ID_SDMA0 | |
| 847 | + || ucode_id == AMDGPU_UCODE_ID_SDMA1 | |
| 848 | + || ucode_id == AMDGPU_UCODE_ID_SDMA2 | |
| 849 | + || ucode_id == AMDGPU_UCODE_ID_SDMA3 | |
| 850 | + || ucode_id == AMDGPU_UCODE_ID_SDMA4 | |
| 851 | + || ucode_id == AMDGPU_UCODE_ID_SDMA5 | |
| 852 | + || ucode_id == AMDGPU_UCODE_ID_SDMA6 | |
| 853 | + || ucode_id == AMDGPU_UCODE_ID_SDMA7 | |
| 854 | + || ucode_id == AMDGPU_UCODE_ID_RLC_G | |
| 855 | + || ucode_id == AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL | |
| 856 | + || ucode_id == AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM | |
| 857 | + || ucode_id == AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM | |
| 858 | + || ucode_id == AMDGPU_UCODE_ID_SMC) | |
| 859 | + return true; | |
| 860 | + else | |
| 861 | + return false; | |
| 862 | + } | |
| 863 | +} | |
| 864 | + | |
| 810 | 865 | void amdgpu_virt_update_sriov_video_codec(struct amdgpu_device *adev, |
| 811 | 866 | struct amdgpu_video_codec_info *encode, uint32_t encode_array_size, |
| 812 | 867 | struct amdgpu_video_codec_info *decode, uint32_t decode_array_size) |
| @@ -253,6 +253,9 @@ struct amdgpu_virt { · 252 unmodified lines | ||
| 253 | 253 | uint32_t decode_max_frame_pixels; |
| 254 | 254 | uint32_t encode_max_dimension_pixels; |
| 255 | 255 | uint32_t encode_max_frame_pixels; |
| 256 | + | |
| 257 | + /* the ucode id to signal the autoload */ | |
| 258 | + uint32_t autoload_ucode_id; | |
| 256 | 259 | }; |
| 257 | 260 | |
| 258 | 261 | struct amdgpu_video_codec_info; |
| @@ -343,4 +346,6 @@ void amdgpu_sriov_wreg(struct amdgpu_device *adev, · 84 unmodified lines | ||
| 343 | 346 | u32 acc_flags, u32 hwip); |
| 344 | 347 | u32 amdgpu_sriov_rreg(struct amdgpu_device *adev, |
| 345 | 348 | u32 offset, u32 acc_flags, u32 hwip); |
| 349 | +bool amdgpu_virt_fw_load_skip_check(struct amdgpu_device *adev, | |
| 350 | + uint32_t ucode_id); | |
| 346 | 351 | #endif |
| @@ -282,8 +282,8 @@ static int amdgpu_vkms_plane_atomic_check(struct drm_plane *plane, · 281 unmodified lines | ||
| 282 | 282 | return PTR_ERR(crtc_state); |
| 283 | 283 | |
| 284 | 284 | ret = drm_atomic_helper_check_plane_state(new_plane_state, crtc_state, |
| 285 | − DRM_PLANE_HELPER_NO_SCALING, | |
| 286 | − DRM_PLANE_HELPER_NO_SCALING, | |
| 285 | + DRM_PLANE_NO_SCALING, | |
| 286 | + DRM_PLANE_NO_SCALING, | |
| 287 | 287 | false, true); |
| 288 | 288 | if (ret != 0) |
| 289 | 289 | return ret; |
| @@ -183,10 +183,12 @@ static void amdgpu_vm_bo_evicted(struct amdgpu_vm_bo_base *vm_bo) · 182 unmodified lines | ||
| 183 | 183 | struct amdgpu_bo *bo = vm_bo->bo; |
| 184 | 184 | |
| 185 | 185 | vm_bo->moved = true; |
| 186 | + spin_lock(&vm_bo->vm->status_lock); | |
| 186 | 187 | if (bo->tbo.type == ttm_bo_type_kernel) |
| 187 | 188 | list_move(&vm_bo->vm_status, &vm->evicted); |
| 188 | 189 | else |
| 189 | 190 | list_move_tail(&vm_bo->vm_status, &vm->evicted); |
| 191 | + spin_unlock(&vm_bo->vm->status_lock); | |
| 190 | 192 | } |
| 191 | 193 | /** |
| 192 | 194 | * amdgpu_vm_bo_moved - vm_bo is moved |
| @@ -198,7 +200,9 @@ static void amdgpu_vm_bo_evicted(struct amdgpu_vm_bo_base *vm_bo) · 5 unmodified lines | ||
| 198 | 200 | */ |
| 199 | 201 | static void amdgpu_vm_bo_moved(struct amdgpu_vm_bo_base *vm_bo) |
| 200 | 202 | { |
| 203 | + spin_lock(&vm_bo->vm->status_lock); | |
| 201 | 204 | list_move(&vm_bo->vm_status, &vm_bo->vm->moved); |
| 205 | + spin_unlock(&vm_bo->vm->status_lock); | |
| 202 | 206 | } |
| 203 | 207 | |
| 204 | 208 | /** |
| @@ -211,7 +215,9 @@ static void amdgpu_vm_bo_moved(struct amdgpu_vm_bo_base *vm_bo) · 6 unmodified lines | ||
| 211 | 215 | */ |
| 212 | 216 | static void amdgpu_vm_bo_idle(struct amdgpu_vm_bo_base *vm_bo) |
| 213 | 217 | { |
| 218 | + spin_lock(&vm_bo->vm->status_lock); | |
| 214 | 219 | list_move(&vm_bo->vm_status, &vm_bo->vm->idle); |
| 220 | + spin_unlock(&vm_bo->vm->status_lock); | |
| 215 | 221 | vm_bo->moved = false; |
| 216 | 222 | } |
| 217 | 223 | |
| @@ -225,9 +231,9 @@ static void amdgpu_vm_bo_idle(struct amdgpu_vm_bo_base *vm_bo) · 7 unmodified lines | ||
| 225 | 231 | */ |
| 226 | 232 | static void amdgpu_vm_bo_invalidated(struct amdgpu_vm_bo_base *vm_bo) |
| 227 | 233 | { |
| 228 | − spin_lock(&vm_bo->vm->invalidated_lock); | |
| 234 | + spin_lock(&vm_bo->vm->status_lock); | |
| 229 | 235 | list_move(&vm_bo->vm_status, &vm_bo->vm->invalidated); |
| 230 | − spin_unlock(&vm_bo->vm->invalidated_lock); | |
| 236 | + spin_unlock(&vm_bo->vm->status_lock); | |
| 231 | 237 | } |
| 232 | 238 | |
| 233 | 239 | /** |
| @@ -240,10 +246,13 @@ static void amdgpu_vm_bo_invalidated(struct amdgpu_vm_bo_base *vm_bo) · 6 unmodified lines | ||
| 240 | 246 | */ |
| 241 | 247 | static void amdgpu_vm_bo_relocated(struct amdgpu_vm_bo_base *vm_bo) |
| 242 | 248 | { |
| 243 | − if (vm_bo->bo->parent) | |
| 249 | + if (vm_bo->bo->parent) { | |
| 250 | + spin_lock(&vm_bo->vm->status_lock); | |
| 244 | 251 | list_move(&vm_bo->vm_status, &vm_bo->vm->relocated); |
| 245 | − else | |
| 252 | + spin_unlock(&vm_bo->vm->status_lock); | |
| 253 | + } else { | |
| 246 | 254 | amdgpu_vm_bo_idle(vm_bo); |
| 255 | + } | |
| 247 | 256 | } |
| 248 | 257 | |
| 249 | 258 | /** |
| @@ -256,9 +265,9 @@ static void amdgpu_vm_bo_relocated(struct amdgpu_vm_bo_base *vm_bo) · 6 unmodified lines | ||
| 256 | 265 | */ |
| 257 | 266 | static void amdgpu_vm_bo_done(struct amdgpu_vm_bo_base *vm_bo) |
| 258 | 267 | { |
| 259 | − spin_lock(&vm_bo->vm->invalidated_lock); | |
| 268 | + spin_lock(&vm_bo->vm->status_lock); | |
| 260 | 269 | list_move(&vm_bo->vm_status, &vm_bo->vm->done); |
| 261 | − spin_unlock(&vm_bo->vm->invalidated_lock); | |
| 270 | + spin_unlock(&vm_bo->vm->status_lock); | |
| 262 | 271 | } |
| 263 | 272 | |
| 264 | 273 | /** |
| @@ -363,12 +372,20 @@ int amdgpu_vm_validate_pt_bos(struct amdgpu_device *adev, struct amdgpu_vm *vm, · 98 unmodified lines | ||
| 363 | 372 | int (*validate)(void *p, struct amdgpu_bo *bo), |
| 364 | 373 | void *param) |
| 365 | 374 | { |
| 366 | − struct amdgpu_vm_bo_base *bo_base, *tmp; | |
| 375 | + struct amdgpu_vm_bo_base *bo_base; | |
| 376 | + struct amdgpu_bo *shadow; | |
| 377 | + struct amdgpu_bo *bo; | |
| 367 | 378 | int r; |
| 368 | 379 | |
| 369 | − list_for_each_entry_safe(bo_base, tmp, &vm->evicted, vm_status) { | |
| 370 | − struct amdgpu_bo *bo = bo_base->bo; | |
| 371 | − struct amdgpu_bo *shadow = amdgpu_bo_shadowed(bo); | |
| 380 | + spin_lock(&vm->status_lock); | |
| 381 | + while (!list_empty(&vm->evicted)) { | |
| 382 | + bo_base = list_first_entry(&vm->evicted, | |
| 383 | + struct amdgpu_vm_bo_base, | |
| 384 | + vm_status); | |
| 385 | + spin_unlock(&vm->status_lock); | |
| 386 | + | |
| 387 | + bo = bo_base->bo; | |
| 388 | + shadow = amdgpu_bo_shadowed(bo); | |
| 372 | 389 | |
| 373 | 390 | r = validate(param, bo); |
| 374 | 391 | if (r) |
| @@ -385,7 +402,9 @@ int amdgpu_vm_validate_pt_bos(struct amdgpu_device *adev, struct amdgpu_vm *vm, · 10 unmodified lines | ||
| 385 | 402 | vm->update_funcs->map_table(to_amdgpu_bo_vm(bo)); |
| 386 | 403 | amdgpu_vm_bo_relocated(bo_base); |
| 387 | 404 | } |
| 405 | + spin_lock(&vm->status_lock); | |
| 388 | 406 | } |
| 407 | + spin_unlock(&vm->status_lock); | |
| 389 | 408 | |
| 390 | 409 | amdgpu_vm_eviction_lock(vm); |
| 391 | 410 | vm->evicting = false; |
| @@ -406,13 +425,18 @@ int amdgpu_vm_validate_pt_bos(struct amdgpu_device *adev, struct amdgpu_vm *vm, · 14 unmodified lines | ||
| 406 | 425 | */ |
| 407 | 426 | bool amdgpu_vm_ready(struct amdgpu_vm *vm) |
| 408 | 427 | { |
| 428 | + bool empty; | |
| 409 | 429 | bool ret; |
| 410 | 430 | |
| 411 | 431 | amdgpu_vm_eviction_lock(vm); |
| 412 | 432 | ret = !vm->evicting; |
| 413 | 433 | amdgpu_vm_eviction_unlock(vm); |
| 414 | 434 | |
| 415 | − return ret && list_empty(&vm->evicted); | |
| 435 | + spin_lock(&vm->status_lock); | |
| 436 | + empty = list_empty(&vm->evicted); | |
| 437 | + spin_unlock(&vm->status_lock); | |
| 438 | + | |
| 439 | + return ret && empty; | |
| 416 | 440 | } |
| 417 | 441 | |
| 418 | 442 | /** |
| @@ -680,9 +704,14 @@ int amdgpu_vm_update_pdes(struct amdgpu_device *adev, · 261 unmodified lines | ||
| 680 | 704 | struct amdgpu_vm_update_params params; |
| 681 | 705 | struct amdgpu_vm_bo_base *entry; |
| 682 | 706 | bool flush_tlb_needed = false; |
| 707 | + LIST_HEAD(relocated); | |
| 683 | 708 | int r, idx; |
| 684 | 709 | |
| 685 | − if (list_empty(&vm->relocated)) | |
| 710 | + spin_lock(&vm->status_lock); | |
| 711 | + list_splice_init(&vm->relocated, &relocated); | |
| 712 | + spin_unlock(&vm->status_lock); | |
| 713 | + | |
| 714 | + if (list_empty(&relocated)) | |
| 686 | 715 | return 0; |
| 687 | 716 | |
| 688 | 717 | if (!drm_dev_enter(adev_to_drm(adev), &idx)) |
| @@ -697,7 +726,7 @@ int amdgpu_vm_update_pdes(struct amdgpu_device *adev, · 8 unmodified lines | ||
| 697 | 726 | if (r) |
| 698 | 727 | goto error; |
| 699 | 728 | |
| 700 | − list_for_each_entry(entry, &vm->relocated, vm_status) { | |
| 729 | + list_for_each_entry(entry, &relocated, vm_status) { | |
| 701 | 730 | /* vm_flush_needed after updating moved PDEs */ |
| 702 | 731 | flush_tlb_needed |= entry->moved; |
| 703 | 732 | |
| @@ -713,9 +742,8 @@ int amdgpu_vm_update_pdes(struct amdgpu_device *adev, · 9 unmodified lines | ||
| 713 | 742 | if (flush_tlb_needed) |
| 714 | 743 | atomic64_inc(&vm->tlb_seq); |
| 715 | 744 | |
| 716 | − while (!list_empty(&vm->relocated)) { | |
| 717 | − entry = list_first_entry(&vm->relocated, | |
| 718 | − struct amdgpu_vm_bo_base, | |
| 745 | + while (!list_empty(&relocated)) { | |
| 746 | + entry = list_first_entry(&relocated, struct amdgpu_vm_bo_base, | |
| 719 | 747 | vm_status); |
| 720 | 748 | amdgpu_vm_bo_idle(entry); |
| 721 | 749 | } |
| @@ -912,6 +940,7 @@ void amdgpu_vm_get_memory(struct amdgpu_vm *vm, uint64_t *vram_mem, · 190 unmodified lines | ||
| 912 | 940 | { |
| 913 | 941 | struct amdgpu_bo_va *bo_va, *tmp; |
| 914 | 942 | |
| 943 | + spin_lock(&vm->status_lock); | |
| 915 | 944 | list_for_each_entry_safe(bo_va, tmp, &vm->idle, base.vm_status) { |
| 916 | 945 | if (!bo_va->base.bo) |
| 917 | 946 | continue; |
| @@ -936,7 +965,6 @@ void amdgpu_vm_get_memory(struct amdgpu_vm *vm, uint64_t *vram_mem, · 18 unmodified lines | ||
| 936 | 965 | amdgpu_bo_get_memory(bo_va->base.bo, vram_mem, |
| 937 | 966 | gtt_mem, cpu_mem); |
| 938 | 967 | } |
| 939 | − spin_lock(&vm->invalidated_lock); | |
| 940 | 968 | list_for_each_entry_safe(bo_va, tmp, &vm->invalidated, base.vm_status) { |
| 941 | 969 | if (!bo_va->base.bo) |
| 942 | 970 | continue; |
| @@ -949,7 +977,7 @@ void amdgpu_vm_get_memory(struct amdgpu_vm *vm, uint64_t *vram_mem, · 6 unmodified lines | ||
| 949 | 977 | amdgpu_bo_get_memory(bo_va->base.bo, vram_mem, |
| 950 | 978 | gtt_mem, cpu_mem); |
| 951 | 979 | } |
| 952 | − spin_unlock(&vm->invalidated_lock); | |
| 980 | + spin_unlock(&vm->status_lock); | |
| 953 | 981 | } |
| 954 | 982 | /** |
| 955 | 983 | * amdgpu_vm_bo_update - update all BO mappings in the vm page table |
| @@ -1278,24 +1306,29 @@ int amdgpu_vm_clear_freed(struct amdgpu_device *adev, · 322 unmodified lines | ||
| 1278 | 1306 | int amdgpu_vm_handle_moved(struct amdgpu_device *adev, |
| 1279 | 1307 | struct amdgpu_vm *vm) |
| 1280 | 1308 | { |
| 1281 | − struct amdgpu_bo_va *bo_va, *tmp; | |
| 1309 | + struct amdgpu_bo_va *bo_va; | |
| 1282 | 1310 | struct dma_resv *resv; |
| 1283 | 1311 | bool clear; |
| 1284 | 1312 | int r; |
| 1285 | 1313 | |
| 1286 | − list_for_each_entry_safe(bo_va, tmp, &vm->moved, base.vm_status) { | |
| 1314 | + spin_lock(&vm->status_lock); | |
| 1315 | + while (!list_empty(&vm->moved)) { | |
| 1316 | + bo_va = list_first_entry(&vm->moved, struct amdgpu_bo_va, | |
| 1317 | + base.vm_status); | |
| 1318 | + spin_unlock(&vm->status_lock); | |
| 1319 | + | |
| 1287 | 1320 | /* Per VM BOs never need to bo cleared in the page tables */ |
| 1288 | 1321 | r = amdgpu_vm_bo_update(adev, bo_va, false); |
| 1289 | 1322 | if (r) |
| 1290 | 1323 | return r; |
| 1324 | + spin_lock(&vm->status_lock); | |
| 1291 | 1325 | } |
| 1292 | 1326 | |
| 1293 | − spin_lock(&vm->invalidated_lock); | |
| 1294 | 1327 | while (!list_empty(&vm->invalidated)) { |
| 1295 | 1328 | bo_va = list_first_entry(&vm->invalidated, struct amdgpu_bo_va, |
| 1296 | 1329 | base.vm_status); |
| 1297 | 1330 | resv = bo_va->base.bo->tbo.base.resv; |
| 1298 | − spin_unlock(&vm->invalidated_lock); | |
| 1331 | + spin_unlock(&vm->status_lock); | |
| 1299 | 1332 | |
| 1300 | 1333 | /* Try to reserve the BO to avoid clearing its ptes */ |
| 1301 | 1334 | if (!amdgpu_vm_debug && dma_resv_trylock(resv)) |
| @@ -1310,9 +1343,9 @@ int amdgpu_vm_handle_moved(struct amdgpu_device *adev, · 8 unmodified lines | ||
| 1310 | 1343 | |
| 1311 | 1344 | if (!clear) |
| 1312 | 1345 | dma_resv_unlock(resv); |
| 1313 | − spin_lock(&vm->invalidated_lock); | |
| 1346 | + spin_lock(&vm->status_lock); | |
| 1314 | 1347 | } |
| 1315 | − spin_unlock(&vm->invalidated_lock); | |
| 1348 | + spin_unlock(&vm->status_lock); | |
| 1316 | 1349 | |
| 1317 | 1350 | return 0; |
| 1318 | 1351 | } |
| @@ -1387,7 +1420,7 @@ static void amdgpu_vm_bo_insert_map(struct amdgpu_device *adev, · 68 unmodified lines | ||
| 1387 | 1420 | |
| 1388 | 1421 | if (bo && bo->tbo.base.resv == vm->root.bo->tbo.base.resv && |
| 1389 | 1422 | !bo_va->base.moved) { |
| 1390 | − list_move(&bo_va->base.vm_status, &vm->moved); | |
| 1423 | + amdgpu_vm_bo_moved(&bo_va->base); | |
| 1391 | 1424 | } |
| 1392 | 1425 | trace_amdgpu_vm_bo_map(bo_va, mapping); |
| 1393 | 1426 | } |
| @@ -1763,9 +1796,9 @@ void amdgpu_vm_bo_del(struct amdgpu_device *adev, · 369 unmodified lines | ||
| 1763 | 1796 | } |
| 1764 | 1797 | } |
| 1765 | 1798 | |
| 1766 | − spin_lock(&vm->invalidated_lock); | |
| 1799 | + spin_lock(&vm->status_lock); | |
| 1767 | 1800 | list_del(&bo_va->base.vm_status); |
| 1768 | − spin_unlock(&vm->invalidated_lock); | |
| 1801 | + spin_unlock(&vm->status_lock); | |
| 1769 | 1802 | |
| 1770 | 1803 | list_for_each_entry_safe(mapping, next, &bo_va->valids, list) { |
| 1771 | 1804 | list_del(&mapping->list); |
| @@ -2019,9 +2052,11 @@ int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm) · 247 unmodified lines | ||
| 2019 | 2052 | INIT_LIST_HEAD(&vm->moved); |
| 2020 | 2053 | INIT_LIST_HEAD(&vm->idle); |
| 2021 | 2054 | INIT_LIST_HEAD(&vm->invalidated); |
| 2022 | − spin_lock_init(&vm->invalidated_lock); | |
| 2055 | + spin_lock_init(&vm->status_lock); | |
| 2023 | 2056 | INIT_LIST_HEAD(&vm->freed); |
| 2024 | 2057 | INIT_LIST_HEAD(&vm->done); |
| 2058 | + INIT_LIST_HEAD(&vm->pt_freed); | |
| 2059 | + INIT_WORK(&vm->pt_free_work, amdgpu_vm_pt_free_work); | |
| 2025 | 2060 | |
| 2026 | 2061 | /* create scheduler entities for page table updates */ |
| 2027 | 2062 | r = drm_sched_entity_init(&vm->immediate, DRM_SCHED_PRIORITY_NORMAL, |
| @@ -2223,6 +2258,8 @@ void amdgpu_vm_fini(struct amdgpu_device *adev, struct amdgpu_vm *vm) · 195 unmodified lines | ||
| 2223 | 2258 | |
| 2224 | 2259 | amdgpu_amdkfd_gpuvm_destroy_cb(adev, vm); |
| 2225 | 2260 | |
| 2261 | + flush_work(&vm->pt_free_work); | |
| 2262 | + | |
| 2226 | 2263 | root = amdgpu_bo_ref(vm->root.bo); |
| 2227 | 2264 | amdgpu_bo_reserve(root, true); |
| 2228 | 2265 | amdgpu_vm_set_pasid(adev, vm, 0); |
| @@ -2547,6 +2584,7 @@ void amdgpu_debugfs_vm_bo_info(struct amdgpu_vm *vm, struct seq_file *m) · 318 unmodified lines | ||
| 2547 | 2584 | unsigned int total_done_objs = 0; |
| 2548 | 2585 | unsigned int id = 0; |
| 2549 | 2586 | |
| 2587 | + spin_lock(&vm->status_lock); | |
| 2550 | 2588 | seq_puts(m, "\tIdle BOs:\n"); |
| 2551 | 2589 | list_for_each_entry_safe(bo_va, tmp, &vm->idle, base.vm_status) { |
| 2552 | 2590 | if (!bo_va->base.bo) |
| @@ -2584,7 +2622,6 @@ void amdgpu_debugfs_vm_bo_info(struct amdgpu_vm *vm, struct seq_file *m) · 31 unmodified lines | ||
| 2584 | 2622 | id = 0; |
| 2585 | 2623 | |
| 2586 | 2624 | seq_puts(m, "\tInvalidated BOs:\n"); |
| 2587 | − spin_lock(&vm->invalidated_lock); | |
| 2588 | 2625 | list_for_each_entry_safe(bo_va, tmp, &vm->invalidated, base.vm_status) { |
| 2589 | 2626 | if (!bo_va->base.bo) |
| 2590 | 2627 | continue; |
| @@ -2599,7 +2636,7 @@ void amdgpu_debugfs_vm_bo_info(struct amdgpu_vm *vm, struct seq_file *m) · 8 unmodified lines | ||
| 2599 | 2636 | continue; |
| 2600 | 2637 | total_done += amdgpu_bo_print_info(id++, bo_va->base.bo, m); |
| 2601 | 2638 | } |
| 2602 | − spin_unlock(&vm->invalidated_lock); | |
| 2639 | + spin_unlock(&vm->status_lock); | |
| 2603 | 2640 | total_done_objs = id; |
| 2604 | 2641 | |
| 2605 | 2642 | seq_printf(m, "\tTotal idle size: %12lld\tobjs:\t%d\n", total_idle, |
| @@ -254,6 +254,9 @@ struct amdgpu_vm { · 253 unmodified lines | ||
| 254 | 254 | bool evicting; |
| 255 | 255 | unsigned int saved_flags; |
| 256 | 256 | |
| 257 | + /* Lock to protect vm_bo add/del/move on all lists of vm */ | |
| 258 | + spinlock_t status_lock; | |
| 259 | + | |
| 257 | 260 | /* BOs who needs a validation */ |
| 258 | 261 | struct list_head evicted; |
| 259 | 262 | |
| @@ -268,7 +271,6 @@ struct amdgpu_vm { · 8 unmodified lines | ||
| 268 | 271 | |
| 269 | 272 | /* regular invalidated BOs, but not yet updated in the PT */ |
| 270 | 273 | struct list_head invalidated; |
| 271 | − spinlock_t invalidated_lock; | |
| 272 | 274 | |
| 273 | 275 | /* BO mappings freed, but not yet updated in the PT */ |
| 274 | 276 | struct list_head freed; |
| @@ -276,6 +278,10 @@ struct amdgpu_vm { · 1 unmodified line | ||
| 276 | 278 | /* BOs which are invalidated, has been updated in the PTs */ |
| 277 | 279 | struct list_head done; |
| 278 | 280 | |
| 281 | + /* PT BOs scheduled to free and fill with zero if vm_resv is not hold */ | |
| 282 | + struct list_head pt_freed; | |
| 283 | + struct work_struct pt_free_work; | |
| 284 | + | |
| 279 | 285 | /* contains the page directory */ |
| 280 | 286 | struct amdgpu_vm_bo_base root; |
| 281 | 287 | struct dma_fence *last_update; |
| @@ -471,6 +477,7 @@ int amdgpu_vm_pde_update(struct amdgpu_vm_update_params *params, · 189 unmodified lines | ||
| 471 | 477 | int amdgpu_vm_ptes_update(struct amdgpu_vm_update_params *params, |
| 472 | 478 | uint64_t start, uint64_t end, |
| 473 | 479 | uint64_t dst, uint64_t flags); |
| 480 | +void amdgpu_vm_pt_free_work(struct work_struct *work); | |
| 474 | 481 | |
| 475 | 482 | #if defined(CONFIG_DEBUG_FS) |
| 476 | 483 | void amdgpu_debugfs_vm_bo_info(struct amdgpu_vm *vm, struct seq_file *m); |
| @@ -637,10 +637,34 @@ static void amdgpu_vm_pt_free(struct amdgpu_vm_bo_base *entry) · 636 unmodified lines | ||
| 637 | 637 | } |
| 638 | 638 | ttm_bo_set_bulk_move(&entry->bo->tbo, NULL); |
| 639 | 639 | entry->bo->vm_bo = NULL; |
| 640 | + | |
| 641 | + spin_lock(&entry->vm->status_lock); | |
| 640 | 642 | list_del(&entry->vm_status); |
| 643 | + spin_unlock(&entry->vm->status_lock); | |
| 641 | 644 | amdgpu_bo_unref(&entry->bo); |
| 642 | 645 | } |
| 643 | 646 | |
| 647 | +void amdgpu_vm_pt_free_work(struct work_struct *work) | |
| 648 | +{ | |
| 649 | + struct amdgpu_vm_bo_base *entry, *next; | |
| 650 | + struct amdgpu_vm *vm; | |
| 651 | + LIST_HEAD(pt_freed); | |
| 652 | + | |
| 653 | + vm = container_of(work, struct amdgpu_vm, pt_free_work); | |
| 654 | + | |
| 655 | + spin_lock(&vm->status_lock); | |
| 656 | + list_splice_init(&vm->pt_freed, &pt_freed); | |
| 657 | + spin_unlock(&vm->status_lock); | |
| 658 | + | |
| 659 | + /* flush_work in amdgpu_vm_fini ensure vm->root.bo is valid. */ | |
| 660 | + amdgpu_bo_reserve(vm->root.bo, true); | |
| 661 | + | |
| 662 | + list_for_each_entry_safe(entry, next, &pt_freed, vm_status) | |
| 663 | + amdgpu_vm_pt_free(entry); | |
| 664 | + | |
| 665 | + amdgpu_bo_unreserve(vm->root.bo); | |
| 666 | +} | |
| 667 | + | |
| 644 | 668 | /** |
| 645 | 669 | * amdgpu_vm_pt_free_dfs - free PD/PT levels |
| 646 | 670 | * |
| @@ -652,11 +676,24 @@ static void amdgpu_vm_pt_free(struct amdgpu_vm_bo_base *entry) · 5 unmodified lines | ||
| 652 | 676 | */ |
| 653 | 677 | static void amdgpu_vm_pt_free_dfs(struct amdgpu_device *adev, |
| 654 | 678 | struct amdgpu_vm *vm, |
| 655 | − struct amdgpu_vm_pt_cursor *start) | |
| 679 | + struct amdgpu_vm_pt_cursor *start, | |
| 680 | + bool unlocked) | |
| 656 | 681 | { |
| 657 | 682 | struct amdgpu_vm_pt_cursor cursor; |
| 658 | 683 | struct amdgpu_vm_bo_base *entry; |
| 659 | 684 | |
| 685 | + if (unlocked) { | |
| 686 | + spin_lock(&vm->status_lock); | |
| 687 | + for_each_amdgpu_vm_pt_dfs_safe(adev, vm, start, cursor, entry) | |
| 688 | + list_move(&entry->vm_status, &vm->pt_freed); | |
| 689 | + | |
| 690 | + if (start) | |
| 691 | + list_move(&start->entry->vm_status, &vm->pt_freed); | |
| 692 | + spin_unlock(&vm->status_lock); | |
| 693 | + schedule_work(&vm->pt_free_work); | |
| 694 | + return; | |
| 695 | + } | |
| 696 | + | |
| 660 | 697 | for_each_amdgpu_vm_pt_dfs_safe(adev, vm, start, cursor, entry) |
| 661 | 698 | amdgpu_vm_pt_free(entry); |
| 662 | 699 | |
| @@ -673,7 +710,7 @@ static void amdgpu_vm_pt_free_dfs(struct amdgpu_device *adev, · 10 unmodified lines | ||
| 673 | 710 | */ |
| 674 | 711 | void amdgpu_vm_pt_free_root(struct amdgpu_device *adev, struct amdgpu_vm *vm) |
| 675 | 712 | { |
| 676 | − amdgpu_vm_pt_free_dfs(adev, vm, NULL); | |
| 713 | + amdgpu_vm_pt_free_dfs(adev, vm, NULL, false); | |
| 677 | 714 | } |
| 678 | 715 | |
| 679 | 716 | /** |
| @@ -966,7 +1003,8 @@ int amdgpu_vm_ptes_update(struct amdgpu_vm_update_params *params, · 286 unmodified lines | ||
| 966 | 1003 | if (cursor.entry->bo) { |
| 967 | 1004 | params->table_freed = true; |
| 968 | 1005 | amdgpu_vm_pt_free_dfs(adev, params->vm, |
| 969 | − &cursor); | |
| 1006 | + &cursor, | |
| 1007 | + params->unlocked); | |
| 970 | 1008 | } |
| 971 | 1009 | amdgpu_vm_pt_next(adev, &cursor); |
| 972 | 1010 | } |
| @@ -112,7 +112,8 @@ static int amdgpu_vm_sdma_commit(struct amdgpu_vm_update_params *p, · 111 unmodified lines | ||
| 112 | 112 | swap(p->vm->last_unlocked, tmp); |
| 113 | 113 | dma_fence_put(tmp); |
| 114 | 114 | } else { |
| 115 | − amdgpu_bo_fence(p->vm->root.bo, f, true); | |
| 115 | + dma_resv_add_fence(p->vm->root.bo->tbo.base.resv, f, | |
| 116 | + DMA_RESV_USAGE_BOOKKEEP); | |
| 116 | 117 | } |
| 117 | 118 | |
| 118 | 119 | if (fence && !p->immediate) |
| @@ -211,12 +212,15 @@ static int amdgpu_vm_sdma_update(struct amdgpu_vm_update_params *p, · 92 unmodified lines | ||
| 211 | 212 | int r; |
| 212 | 213 | |
| 213 | 214 | /* Wait for PD/PT moves to be completed */ |
| 214 | − dma_resv_for_each_fence(&cursor, bo->tbo.base.resv, | |
| 215 | − DMA_RESV_USAGE_KERNEL, fence) { | |
| 215 | + dma_resv_iter_begin(&cursor, bo->tbo.base.resv, DMA_RESV_USAGE_KERNEL); | |
| 216 | + dma_resv_for_each_fence_unlocked(&cursor, fence) { | |
| 216 | 217 | r = amdgpu_sync_fence(&p->job->sync, fence); |
| 217 | − if (r) | |
| 218 | + if (r) { | |
| 219 | + dma_resv_iter_end(&cursor); | |
| 218 | 220 | return r; |
| 221 | + } | |
| 219 | 222 | } |
| 223 | + dma_resv_iter_end(&cursor); | |
| 220 | 224 | |
| 221 | 225 | do { |
| 222 | 226 | ndw = p->num_dw_left; |
| @@ -720,6 +720,72 @@ uint64_t amdgpu_vram_mgr_vis_usage(struct amdgpu_vram_mgr *mgr) · 719 unmodified lines | ||
| 720 | 720 | return atomic64_read(&mgr->vis_usage); |
| 721 | 721 | } |
| 722 | 722 | |
| 723 | +/** | |
| 724 | + * amdgpu_vram_mgr_intersects - test each drm buddy block for intersection | |
| 725 | + * | |
| 726 | + * @man: TTM memory type manager | |
| 727 | + * @res: The resource to test | |
| 728 | + * @place: The place to test against | |
| 729 | + * @size: Size of the new allocation | |
| 730 | + * | |
| 731 | + * Test each drm buddy block for intersection for eviction decision. | |
| 732 | + */ | |
| 733 | +static bool amdgpu_vram_mgr_intersects(struct ttm_resource_manager *man, | |
| 734 | + struct ttm_resource *res, | |
| 735 | + const struct ttm_place *place, | |
| 736 | + size_t size) | |
| 737 | +{ | |
| 738 | + struct amdgpu_vram_mgr_resource *mgr = to_amdgpu_vram_mgr_resource(res); | |
| 739 | + struct drm_buddy_block *block; | |
| 740 | + | |
| 741 | + /* Check each drm buddy block individually */ | |
| 742 | + list_for_each_entry(block, &mgr->blocks, link) { | |
| 743 | + unsigned long fpfn = | |
| 744 | + amdgpu_vram_mgr_block_start(block) >> PAGE_SHIFT; | |
| 745 | + unsigned long lpfn = fpfn + | |
| 746 | + (amdgpu_vram_mgr_block_size(block) >> PAGE_SHIFT); | |
| 747 | + | |
| 748 | + if (place->fpfn < lpfn && | |
| 749 | + (!place->lpfn || place->lpfn > fpfn)) | |
| 750 | + return true; | |
| 751 | + } | |
| 752 | + | |
| 753 | + return false; | |
| 754 | +} | |
| 755 | + | |
| 756 | +/** | |
| 757 | + * amdgpu_vram_mgr_compatible - test each drm buddy block for compatibility | |
| 758 | + * | |
| 759 | + * @man: TTM memory type manager | |
| 760 | + * @res: The resource to test | |
| 761 | + * @place: The place to test against | |
| 762 | + * @size: Size of the new allocation | |
| 763 | + * | |
| 764 | + * Test each drm buddy block for placement compatibility. | |
| 765 | + */ | |
| 766 | +static bool amdgpu_vram_mgr_compatible(struct ttm_resource_manager *man, | |
| 767 | + struct ttm_resource *res, | |
| 768 | + const struct ttm_place *place, | |
| 769 | + size_t size) | |
| 770 | +{ | |
| 771 | + struct amdgpu_vram_mgr_resource *mgr = to_amdgpu_vram_mgr_resource(res); | |
| 772 | + struct drm_buddy_block *block; | |
| 773 | + | |
| 774 | + /* Check each drm buddy block individually */ | |
| 775 | + list_for_each_entry(block, &mgr->blocks, link) { | |
| 776 | + unsigned long fpfn = | |
| 777 | + amdgpu_vram_mgr_block_start(block) >> PAGE_SHIFT; | |
| 778 | + unsigned long lpfn = fpfn + | |
| 779 | + (amdgpu_vram_mgr_block_size(block) >> PAGE_SHIFT); | |
| 780 | + | |
| 781 | + if (fpfn < place->fpfn || | |
| 782 | + (place->lpfn && lpfn > place->lpfn)) | |
| 783 | + return false; | |
| 784 | + } | |
| 785 | + | |
| 786 | + return true; | |
| 787 | +} | |
| 788 | + | |
| 723 | 789 | /** |
| 724 | 790 | * amdgpu_vram_mgr_debug - dump VRAM table |
| 725 | 791 | * |
| @@ -753,6 +819,8 @@ static void amdgpu_vram_mgr_debug(struct ttm_resource_manager *man, · 27 unmodified lines | ||
| 753 | 819 | static const struct ttm_resource_manager_func amdgpu_vram_mgr_func = { |
| 754 | 820 | .alloc = amdgpu_vram_mgr_new, |
| 755 | 821 | .free = amdgpu_vram_mgr_del, |
| 822 | + .intersects = amdgpu_vram_mgr_intersects, | |
| 823 | + .compatible = amdgpu_vram_mgr_compatible, | |
| 756 | 824 | .debug = amdgpu_vram_mgr_debug |
| 757 | 825 | }; |
| 758 | 826 | |
| @@ -391,13 +391,21 @@ struct amdgpu_hive_info *amdgpu_get_xgmi_hive(struct amdgpu_device *adev) · 390 unmodified lines | ||
| 391 | 391 | goto pro_end; |
| 392 | 392 | } |
| 393 | 393 | |
| 394 | + /** | |
| 395 | + * Only init hive->reset_domain for none SRIOV configuration. For SRIOV, | |
| 396 | + * Host driver decide how to reset the GPU either through FLR or chain reset. | |
| 397 | + * Guest side will get individual notifications from the host for the FLR | |
| 398 | + * if necessary. | |
| 399 | + */ | |
| 400 | + if (!amdgpu_sriov_vf(adev)) { | |
| 394 | 401 | /** |
| 395 | 402 | * Avoid recreating reset domain when hive is reconstructed for the case |
| 396 | − * of reset the devices in the XGMI hive during probe for SRIOV | |
| 403 | + * of reset the devices in the XGMI hive during probe for passthrough GPU | |
| 397 | 404 | * See https://www.spinics.net/lists/amd-gfx/msg58836.html |
| 398 | 405 | */ |
| 399 | − if (adev->reset_domain->type != XGMI_HIVE) { | |
| 400 | − hive->reset_domain = amdgpu_reset_create_reset_domain(XGMI_HIVE, "amdgpu-reset-hive"); | |
| 406 | + if (adev->reset_domain->type != XGMI_HIVE) { | |
| 407 | + hive->reset_domain = | |
| 408 | + amdgpu_reset_create_reset_domain(XGMI_HIVE, "amdgpu-reset-hive"); | |
| 401 | 409 | if (!hive->reset_domain) { |
| 402 | 410 | dev_err(adev->dev, "XGMI: failed initializing reset domain for xgmi hive\n"); |
| 403 | 411 | ret = -ENOMEM; |
| @@ -406,9 +414,10 @@ struct amdgpu_hive_info *amdgpu_get_xgmi_hive(struct amdgpu_device *adev) · 2 unmodified lines | ||
| 406 | 414 | hive = NULL; |
| 407 | 415 | goto pro_end; |
| 408 | 416 | } |
| 409 | − } else { | |
| 410 | − amdgpu_reset_get_reset_domain(adev->reset_domain); | |
| 411 | − hive->reset_domain = adev->reset_domain; | |
| 417 | + } else { | |
| 418 | + amdgpu_reset_get_reset_domain(adev->reset_domain); | |
| 419 | + hive->reset_domain = adev->reset_domain; | |
| 420 | + } | |
| 412 | 421 | } |
| 413 | 422 | |
| 414 | 423 | hive->hive_id = adev->gmc.xgmi.hive_id; |
| @@ -504,6 +513,9 @@ int amdgpu_xgmi_update_topology(struct amdgpu_hive_info *hive, struct amdgpu_dev · 89 unmodified lines | ||
| 504 | 513 | { |
| 505 | 514 | int ret; |
| 506 | 515 | |
| 516 | + if (amdgpu_sriov_vf(adev)) | |
| 517 | + return 0; | |
| 518 | + | |
| 507 | 519 | /* Each psp need to set the latest topology */ |
| 508 | 520 | ret = psp_xgmi_set_topology_info(&adev->psp, |
| 509 | 521 | atomic_read(&hive->number_devices), |
| @@ -43,6 +43,7 @@ struct amdgpu_hive_info { · 42 unmodified lines | ||
| 43 | 43 | } pstate; |
| 44 | 44 | |
| 45 | 45 | struct amdgpu_reset_domain *reset_domain; |
| 46 | + uint32_t device_remove_count; | |
| 46 | 47 | }; |
| 47 | 48 | |
| 48 | 49 | struct amdgpu_pcs_ras_field { |
| @@ -3943,56 +3943,6 @@ static void gfx_v10_0_check_fw_write_wait(struct amdgpu_device *adev) · 3942 unmodified lines | ||
| 3943 | 3943 | DRM_WARN_ONCE("CP firmware version too old, please update!"); |
| 3944 | 3944 | } |
| 3945 | 3945 | |
| 3946 | − | |
| 3947 | −static void gfx_v10_0_init_rlc_ext_microcode(struct amdgpu_device *adev) | |
| 3948 | −{ | |
| 3949 | − const struct rlc_firmware_header_v2_1 *rlc_hdr; | |
| 3950 | − | |
| 3951 | − rlc_hdr = (const struct rlc_firmware_header_v2_1 *)adev->gfx.rlc_fw->data; | |
| 3952 | − adev->gfx.rlc_srlc_fw_version = le32_to_cpu(rlc_hdr->save_restore_list_cntl_ucode_ver); | |
| 3953 | − adev->gfx.rlc_srlc_feature_version = le32_to_cpu(rlc_hdr->save_restore_list_cntl_feature_ver); | |
| 3954 | − adev->gfx.rlc.save_restore_list_cntl_size_bytes = le32_to_cpu(rlc_hdr->save_restore_list_cntl_size_bytes); | |
| 3955 | − adev->gfx.rlc.save_restore_list_cntl = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->save_restore_list_cntl_offset_bytes); | |
| 3956 | − adev->gfx.rlc_srlg_fw_version = le32_to_cpu(rlc_hdr->save_restore_list_gpm_ucode_ver); | |
| 3957 | − adev->gfx.rlc_srlg_feature_version = le32_to_cpu(rlc_hdr->save_restore_list_gpm_feature_ver); | |
| 3958 | − adev->gfx.rlc.save_restore_list_gpm_size_bytes = le32_to_cpu(rlc_hdr->save_restore_list_gpm_size_bytes); | |
| 3959 | − adev->gfx.rlc.save_restore_list_gpm = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->save_restore_list_gpm_offset_bytes); | |
| 3960 | − adev->gfx.rlc_srls_fw_version = le32_to_cpu(rlc_hdr->save_restore_list_srm_ucode_ver); | |
| 3961 | − adev->gfx.rlc_srls_feature_version = le32_to_cpu(rlc_hdr->save_restore_list_srm_feature_ver); | |
| 3962 | − adev->gfx.rlc.save_restore_list_srm_size_bytes = le32_to_cpu(rlc_hdr->save_restore_list_srm_size_bytes); | |
| 3963 | − adev->gfx.rlc.save_restore_list_srm = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->save_restore_list_srm_offset_bytes); | |
| 3964 | − adev->gfx.rlc.reg_list_format_direct_reg_list_length = | |
| 3965 | − le32_to_cpu(rlc_hdr->reg_list_format_direct_reg_list_length); | |
| 3966 | −} | |
| 3967 | − | |
| 3968 | −static void gfx_v10_0_init_rlc_iram_dram_microcode(struct amdgpu_device *adev) | |
| 3969 | −{ | |
| 3970 | − const struct rlc_firmware_header_v2_2 *rlc_hdr; | |
| 3971 | − | |
| 3972 | − rlc_hdr = (const struct rlc_firmware_header_v2_2 *)adev->gfx.rlc_fw->data; | |
| 3973 | − adev->gfx.rlc.rlc_iram_ucode_size_bytes = le32_to_cpu(rlc_hdr->rlc_iram_ucode_size_bytes); | |
| 3974 | − adev->gfx.rlc.rlc_iram_ucode = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->rlc_iram_ucode_offset_bytes); | |
| 3975 | − adev->gfx.rlc.rlc_dram_ucode_size_bytes = le32_to_cpu(rlc_hdr->rlc_dram_ucode_size_bytes); | |
| 3976 | − adev->gfx.rlc.rlc_dram_ucode = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->rlc_dram_ucode_offset_bytes); | |
| 3977 | −} | |
| 3978 | − | |
| 3979 | −static void gfx_v10_0_init_tap_delays_microcode(struct amdgpu_device *adev) | |
| 3980 | −{ | |
| 3981 | − const struct rlc_firmware_header_v2_4 *rlc_hdr; | |
| 3982 | − | |
| 3983 | − rlc_hdr = (const struct rlc_firmware_header_v2_4 *)adev->gfx.rlc_fw->data; | |
| 3984 | − adev->gfx.rlc.global_tap_delays_ucode_size_bytes = le32_to_cpu(rlc_hdr->global_tap_delays_ucode_size_bytes); | |
| 3985 | − adev->gfx.rlc.global_tap_delays_ucode = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->global_tap_delays_ucode_offset_bytes); | |
| 3986 | − adev->gfx.rlc.se0_tap_delays_ucode_size_bytes = le32_to_cpu(rlc_hdr->se0_tap_delays_ucode_size_bytes); | |
| 3987 | − adev->gfx.rlc.se0_tap_delays_ucode = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->se0_tap_delays_ucode_offset_bytes); | |
| 3988 | − adev->gfx.rlc.se1_tap_delays_ucode_size_bytes = le32_to_cpu(rlc_hdr->se1_tap_delays_ucode_size_bytes); | |
| 3989 | − adev->gfx.rlc.se1_tap_delays_ucode = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->se1_tap_delays_ucode_offset_bytes); | |
| 3990 | − adev->gfx.rlc.se2_tap_delays_ucode_size_bytes = le32_to_cpu(rlc_hdr->se2_tap_delays_ucode_size_bytes); | |
| 3991 | − adev->gfx.rlc.se2_tap_delays_ucode = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->se2_tap_delays_ucode_offset_bytes); | |
| 3992 | − adev->gfx.rlc.se3_tap_delays_ucode_size_bytes = le32_to_cpu(rlc_hdr->se3_tap_delays_ucode_size_bytes); | |
| 3993 | − adev->gfx.rlc.se3_tap_delays_ucode = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->se3_tap_delays_ucode_offset_bytes); | |
| 3994 | −} | |
| 3995 | − | |
| 3996 | 3946 | static bool gfx_v10_0_navi10_gfxoff_should_enable(struct amdgpu_device *adev) |
| 3997 | 3947 | { |
| 3998 | 3948 | bool ret = false; |
| @@ -4028,12 +3978,7 @@ static int gfx_v10_0_init_microcode(struct amdgpu_device *adev) · 29 unmodified lines | ||
| 4028 | 3978 | char fw_name[40]; |
| 4029 | 3979 | char *wks = ""; |
| 4030 | 3980 | int err; |
| 4031 | − struct amdgpu_firmware_info *info = NULL; | |
| 4032 | − const struct common_firmware_header *header = NULL; | |
| 4033 | − const struct gfx_firmware_header_v1_0 *cp_hdr; | |
| 4034 | 3981 | const struct rlc_firmware_header_v2_0 *rlc_hdr; |
| 4035 | − unsigned int *tmp = NULL; | |
| 4036 | − unsigned int i = 0; | |
| 4037 | 3982 | uint16_t version_major; |
| 4038 | 3983 | uint16_t version_minor; |
| 4039 | 3984 | |
| @@ -4091,9 +4036,7 @@ static int gfx_v10_0_init_microcode(struct amdgpu_device *adev) · 51 unmodified lines | ||
| 4091 | 4036 | err = amdgpu_ucode_validate(adev->gfx.pfp_fw); |
| 4092 | 4037 | if (err) |
| 4093 | 4038 | goto out; |
| 4094 | − cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data; | |
| 4095 | − adev->gfx.pfp_fw_version = le32_to_cpu(cp_hdr->header.ucode_version); | |
| 4096 | − adev->gfx.pfp_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version); | |
| 4039 | + amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_PFP); | |
| 4097 | 4040 | |
| 4098 | 4041 | snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_me%s.bin", chip_name, wks); |
| 4099 | 4042 | err = request_firmware(&adev->gfx.me_fw, fw_name, adev->dev); |
| @@ -4102,9 +4045,7 @@ static int gfx_v10_0_init_microcode(struct amdgpu_device *adev) · 2 unmodified lines | ||
| 4102 | 4045 | err = amdgpu_ucode_validate(adev->gfx.me_fw); |
| 4103 | 4046 | if (err) |
| 4104 | 4047 | goto out; |
| 4105 | − cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data; | |
| 4106 | − adev->gfx.me_fw_version = le32_to_cpu(cp_hdr->header.ucode_version); | |
| 4107 | − adev->gfx.me_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version); | |
| 4048 | + amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_ME); | |
| 4108 | 4049 | |
| 4109 | 4050 | snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ce%s.bin", chip_name, wks); |
| 4110 | 4051 | err = request_firmware(&adev->gfx.ce_fw, fw_name, adev->dev); |
| @@ -4113,69 +4054,27 @@ static int gfx_v10_0_init_microcode(struct amdgpu_device *adev) · 2 unmodified lines | ||
| 4113 | 4054 | err = amdgpu_ucode_validate(adev->gfx.ce_fw); |
| 4114 | 4055 | if (err) |
| 4115 | 4056 | goto out; |
| 4116 | − cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data; | |
| 4117 | − adev->gfx.ce_fw_version = le32_to_cpu(cp_hdr->header.ucode_version); | |
| 4118 | − adev->gfx.ce_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version); | |
| 4057 | + amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_CE); | |
| 4119 | 4058 | |
| 4120 | 4059 | if (!amdgpu_sriov_vf(adev)) { |
| 4121 | 4060 | snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_rlc.bin", chip_name); |
| 4122 | 4061 | err = request_firmware(&adev->gfx.rlc_fw, fw_name, adev->dev); |
| 4123 | 4062 | if (err) |
| 4124 | 4063 | goto out; |
| 4064 | + /* don't check this. There are apparently firmwares in the wild with | |
| 4065 | + * incorrect size in the header | |
| 4066 | + */ | |
| 4125 | 4067 | err = amdgpu_ucode_validate(adev->gfx.rlc_fw); |
| 4068 | + if (err) | |
| 4069 | + dev_dbg(adev->dev, | |
| 4070 | + "gfx10: amdgpu_ucode_validate() failed \"%s\"\n", | |
| 4071 | + fw_name); | |
| 4126 | 4072 | rlc_hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data; |
| 4127 | 4073 | version_major = le16_to_cpu(rlc_hdr->header.header_version_major); |
| 4128 | 4074 | version_minor = le16_to_cpu(rlc_hdr->header.header_version_minor); |
| 4129 | − | |
| 4130 | − adev->gfx.rlc_fw_version = le32_to_cpu(rlc_hdr->header.ucode_version); | |
| 4131 | − adev->gfx.rlc_feature_version = le32_to_cpu(rlc_hdr->ucode_feature_version); | |
| 4132 | − adev->gfx.rlc.save_and_restore_offset = | |
| 4133 | − le32_to_cpu(rlc_hdr->save_and_restore_offset); | |
| 4134 | − adev->gfx.rlc.clear_state_descriptor_offset = | |
| 4135 | − le32_to_cpu(rlc_hdr->clear_state_descriptor_offset); | |
| 4136 | − adev->gfx.rlc.avail_scratch_ram_locations = | |
| 4137 | − le32_to_cpu(rlc_hdr->avail_scratch_ram_locations); | |
| 4138 | − adev->gfx.rlc.reg_restore_list_size = | |
| 4139 | − le32_to_cpu(rlc_hdr->reg_restore_list_size); | |
| 4140 | − adev->gfx.rlc.reg_list_format_start = | |
| 4141 | − le32_to_cpu(rlc_hdr->reg_list_format_start); | |
| 4142 | − adev->gfx.rlc.reg_list_format_separate_start = | |
| 4143 | − le32_to_cpu(rlc_hdr->reg_list_format_separate_start); | |
| 4144 | − adev->gfx.rlc.starting_offsets_start = | |
| 4145 | − le32_to_cpu(rlc_hdr->starting_offsets_start); | |
| 4146 | − adev->gfx.rlc.reg_list_format_size_bytes = | |
| 4147 | − le32_to_cpu(rlc_hdr->reg_list_format_size_bytes); | |
| 4148 | − adev->gfx.rlc.reg_list_size_bytes = | |
| 4149 | − le32_to_cpu(rlc_hdr->reg_list_size_bytes); | |
| 4150 | − adev->gfx.rlc.register_list_format = | |
| 4151 | − kmalloc(adev->gfx.rlc.reg_list_format_size_bytes + | |
| 4152 | − adev->gfx.rlc.reg_list_size_bytes, GFP_KERNEL); | |
| 4153 | − if (!adev->gfx.rlc.register_list_format) { | |
| 4154 | − err = -ENOMEM; | |
| 4075 | + err = amdgpu_gfx_rlc_init_microcode(adev, version_major, version_minor); | |
| 4076 | + if (err) | |
| 4155 | 4077 | goto out; |
| 4156 | − } | |
| 4157 | − | |
| 4158 | − tmp = (unsigned int *)((uintptr_t)rlc_hdr + | |
| 4159 | − le32_to_cpu(rlc_hdr->reg_list_format_array_offset_bytes)); | |
| 4160 | − for (i = 0 ; i < (rlc_hdr->reg_list_format_size_bytes >> 2); i++) | |
| 4161 | − adev->gfx.rlc.register_list_format[i] = le32_to_cpu(tmp[i]); | |
| 4162 | − | |
| 4163 | − adev->gfx.rlc.register_restore = adev->gfx.rlc.register_list_format + i; | |
| 4164 | − | |
| 4165 | − tmp = (unsigned int *)((uintptr_t)rlc_hdr + | |
| 4166 | − le32_to_cpu(rlc_hdr->reg_list_array_offset_bytes)); | |
| 4167 | − for (i = 0 ; i < (rlc_hdr->reg_list_size_bytes >> 2); i++) | |
| 4168 | − adev->gfx.rlc.register_restore[i] = le32_to_cpu(tmp[i]); | |
| 4169 | − | |
| 4170 | − if (version_major == 2) { | |
| 4171 | − if (version_minor >= 1) | |
| 4172 | − gfx_v10_0_init_rlc_ext_microcode(adev); | |
| 4173 | − if (version_minor >= 2) | |
| 4174 | − gfx_v10_0_init_rlc_iram_dram_microcode(adev); | |
| 4175 | − if (version_minor == 4) { | |
| 4176 | − gfx_v10_0_init_tap_delays_microcode(adev); | |
| 4177 | − } | |
| 4178 | − } | |
| 4179 | 4078 | } |
| 4180 | 4079 | |
| 4181 | 4080 | snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec%s.bin", chip_name, wks); |
| @@ -4185,9 +4084,8 @@ static int gfx_v10_0_init_microcode(struct amdgpu_device *adev) · 3 unmodified lines | ||
| 4185 | 4084 | err = amdgpu_ucode_validate(adev->gfx.mec_fw); |
| 4186 | 4085 | if (err) |
| 4187 | 4086 | goto out; |
| 4188 | − cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data; | |
| 4189 | − adev->gfx.mec_fw_version = le32_to_cpu(cp_hdr->header.ucode_version); | |
| 4190 | − adev->gfx.mec_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version); | |
| 4087 | + amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_MEC1); | |
| 4088 | + amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_MEC1_JT); | |
| 4191 | 4089 | |
| 4192 | 4090 | snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec2%s.bin", chip_name, wks); |
| 4193 | 4091 | err = request_firmware(&adev->gfx.mec2_fw, fw_name, adev->dev); |
| @@ -4195,164 +4093,18 @@ static int gfx_v10_0_init_microcode(struct amdgpu_device *adev) · 1 unmodified line | ||
| 4195 | 4093 | err = amdgpu_ucode_validate(adev->gfx.mec2_fw); |
| 4196 | 4094 | if (err) |
| 4197 | 4095 | goto out; |
| 4198 | − cp_hdr = (const struct gfx_firmware_header_v1_0 *) | |
| 4199 | − adev->gfx.mec2_fw->data; | |
| 4200 | − adev->gfx.mec2_fw_version = | |
| 4201 | − le32_to_cpu(cp_hdr->header.ucode_version); | |
| 4202 | − adev->gfx.mec2_feature_version = | |
| 4203 | − le32_to_cpu(cp_hdr->ucode_feature_version); | |
| 4096 | + amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_MEC2); | |
| 4097 | + amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_MEC2_JT); | |
| 4204 | 4098 | } else { |
| 4205 | 4099 | err = 0; |
| 4206 | 4100 | adev->gfx.mec2_fw = NULL; |
| 4207 | 4101 | } |
| 4208 | 4102 | |
| 4209 | − if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { | |
| 4210 | − info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_PFP]; | |
| 4211 | − info->ucode_id = AMDGPU_UCODE_ID_CP_PFP; | |
| 4212 | − info->fw = adev->gfx.pfp_fw; | |
| 4213 | − header = (const struct common_firmware_header *)info->fw->data; | |
| 4214 | − adev->firmware.fw_size += | |
| 4215 | − ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE); | |
| 4216 | − | |
| 4217 | − info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_ME]; | |
| 4218 | − info->ucode_id = AMDGPU_UCODE_ID_CP_ME; | |
| 4219 | − info->fw = adev->gfx.me_fw; | |
| 4220 | − header = (const struct common_firmware_header *)info->fw->data; | |
| 4221 | − adev->firmware.fw_size += | |
| 4222 | − ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE); | |
| 4223 | − | |
| 4224 | − info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_CE]; | |
| 4225 | − info->ucode_id = AMDGPU_UCODE_ID_CP_CE; | |
| 4226 | − info->fw = adev->gfx.ce_fw; | |
| 4227 | − header = (const struct common_firmware_header *)info->fw->data; | |
| 4228 | − adev->firmware.fw_size += | |
| 4229 | − ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE); | |
| 4230 | − | |
| 4231 | − info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_G]; | |
| 4232 | − info->ucode_id = AMDGPU_UCODE_ID_RLC_G; | |
| 4233 | − info->fw = adev->gfx.rlc_fw; | |
| 4234 | − if (info->fw) { | |
| 4235 | − header = (const struct common_firmware_header *)info->fw->data; | |
| 4236 | − adev->firmware.fw_size += | |
| 4237 | − ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE); | |
| 4238 | − } | |
| 4239 | − if (adev->gfx.rlc.save_restore_list_cntl_size_bytes && | |
| 4240 | − adev->gfx.rlc.save_restore_list_gpm_size_bytes && | |
| 4241 | − adev->gfx.rlc.save_restore_list_srm_size_bytes) { | |
| 4242 | − info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL]; | |
| 4243 | − info->ucode_id = AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL; | |
| 4244 | − info->fw = adev->gfx.rlc_fw; | |
| 4245 | − adev->firmware.fw_size += | |
| 4246 | − ALIGN(adev->gfx.rlc.save_restore_list_cntl_size_bytes, PAGE_SIZE); | |
| 4247 | − | |
| 4248 | − info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM]; | |
| 4249 | − info->ucode_id = AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM; | |
| 4250 | − info->fw = adev->gfx.rlc_fw; | |
| 4251 | − adev->firmware.fw_size += | |
| 4252 | − ALIGN(adev->gfx.rlc.save_restore_list_gpm_size_bytes, PAGE_SIZE); | |
| 4253 | − | |
| 4254 | − info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM]; | |
| 4255 | − info->ucode_id = AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM; | |
| 4256 | − info->fw = adev->gfx.rlc_fw; | |
| 4257 | − adev->firmware.fw_size += | |
| 4258 | − ALIGN(adev->gfx.rlc.save_restore_list_srm_size_bytes, PAGE_SIZE); | |
| 4259 | − | |
| 4260 | − if (adev->gfx.rlc.rlc_iram_ucode_size_bytes && | |
| 4261 | − adev->gfx.rlc.rlc_dram_ucode_size_bytes) { | |
| 4262 | − info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_IRAM]; | |
| 4263 | − info->ucode_id = AMDGPU_UCODE_ID_RLC_IRAM; | |
| 4264 | − info->fw = adev->gfx.rlc_fw; | |
| 4265 | − adev->firmware.fw_size += | |
| 4266 | − ALIGN(adev->gfx.rlc.rlc_iram_ucode_size_bytes, PAGE_SIZE); | |
| 4267 | − | |
| 4268 | − info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_DRAM]; | |
| 4269 | − info->ucode_id = AMDGPU_UCODE_ID_RLC_DRAM; | |
| 4270 | − info->fw = adev->gfx.rlc_fw; | |
| 4271 | − adev->firmware.fw_size += | |
| 4272 | − ALIGN(adev->gfx.rlc.rlc_dram_ucode_size_bytes, PAGE_SIZE); | |
| 4273 | − } | |
| 4274 | − | |
| 4275 | − } | |
| 4276 | − | |
| 4277 | − if (adev->gfx.rlc.global_tap_delays_ucode_size_bytes) { | |
| 4278 | − info = &adev->firmware.ucode[AMDGPU_UCODE_ID_GLOBAL_TAP_DELAYS]; | |
| 4279 | − info->ucode_id = AMDGPU_UCODE_ID_GLOBAL_TAP_DELAYS; | |
| 4280 | − info->fw = adev->gfx.rlc_fw; | |
| 4281 | − adev->firmware.fw_size += | |
| 4282 | − ALIGN(adev->gfx.rlc.global_tap_delays_ucode_size_bytes, PAGE_SIZE); | |
| 4283 | − } | |
| 4284 | − | |
| 4285 | − if (adev->gfx.rlc.se0_tap_delays_ucode_size_bytes) { | |
| 4286 | − info = &adev->firmware.ucode[AMDGPU_UCODE_ID_SE0_TAP_DELAYS]; | |
| 4287 | − info->ucode_id = AMDGPU_UCODE_ID_SE0_TAP_DELAYS; | |
| 4288 | − info->fw = adev->gfx.rlc_fw; | |
| 4289 | − adev->firmware.fw_size += | |
| 4290 | − ALIGN(adev->gfx.rlc.se0_tap_delays_ucode_size_bytes, PAGE_SIZE); | |
| 4291 | − } | |
| 4292 | − | |
| 4293 | − if (adev->gfx.rlc.se1_tap_delays_ucode_size_bytes) { | |
| 4294 | − info = &adev->firmware.ucode[AMDGPU_UCODE_ID_SE1_TAP_DELAYS]; | |
| 4295 | − info->ucode_id = AMDGPU_UCODE_ID_SE1_TAP_DELAYS; | |
| 4296 | − info->fw = adev->gfx.rlc_fw; | |
| 4297 | − adev->firmware.fw_size += | |
| 4298 | − ALIGN(adev->gfx.rlc.se1_tap_delays_ucode_size_bytes, PAGE_SIZE); | |
| 4299 | − } | |
| 4300 | − | |
| 4301 | − if (adev->gfx.rlc.se2_tap_delays_ucode_size_bytes) { | |
| 4302 | − info = &adev->firmware.ucode[AMDGPU_UCODE_ID_SE2_TAP_DELAYS]; | |
| 4303 | − info->ucode_id = AMDGPU_UCODE_ID_SE2_TAP_DELAYS; | |
| 4304 | − info->fw = adev->gfx.rlc_fw; | |
| 4305 | − adev->firmware.fw_size += | |
| 4306 | − ALIGN(adev->gfx.rlc.se2_tap_delays_ucode_size_bytes, PAGE_SIZE); | |
| 4307 | − } | |
| 4308 | − | |
| 4309 | − if (adev->gfx.rlc.se3_tap_delays_ucode_size_bytes) { | |
| 4310 | − info = &adev->firmware.ucode[AMDGPU_UCODE_ID_SE3_TAP_DELAYS]; | |
| 4311 | − info->ucode_id = AMDGPU_UCODE_ID_SE3_TAP_DELAYS; | |
| 4312 | − info->fw = adev->gfx.rlc_fw; | |
| 4313 | − adev->firmware.fw_size += | |
| 4314 | − ALIGN(adev->gfx.rlc.se3_tap_delays_ucode_size_bytes, PAGE_SIZE); | |
| 4315 | − } | |
| 4316 | − | |
| 4317 | − info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC1]; | |
| 4318 | − info->ucode_id = AMDGPU_UCODE_ID_CP_MEC1; | |
| 4319 | − info->fw = adev->gfx.mec_fw; | |
| 4320 | − header = (const struct common_firmware_header *)info->fw->data; | |
| 4321 | − cp_hdr = (const struct gfx_firmware_header_v1_0 *)info->fw->data; | |
| 4322 | − adev->firmware.fw_size += | |
| 4323 | − ALIGN(le32_to_cpu(header->ucode_size_bytes) - | |
| 4324 | − le32_to_cpu(cp_hdr->jt_size) * 4, PAGE_SIZE); | |
| 4325 | − | |
| 4326 | − info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC1_JT]; | |
| 4327 | − info->ucode_id = AMDGPU_UCODE_ID_CP_MEC1_JT; | |
| 4328 | − info->fw = adev->gfx.mec_fw; | |
| 4329 | − adev->firmware.fw_size += | |
| 4330 | − ALIGN(le32_to_cpu(cp_hdr->jt_size) * 4, PAGE_SIZE); | |
| 4331 | − | |
| 4332 | − if (adev->gfx.mec2_fw) { | |
| 4333 | − info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC2]; | |
| 4334 | − info->ucode_id = AMDGPU_UCODE_ID_CP_MEC2; | |
| 4335 | − info->fw = adev->gfx.mec2_fw; | |
| 4336 | − header = (const struct common_firmware_header *)info->fw->data; | |
| 4337 | − cp_hdr = (const struct gfx_firmware_header_v1_0 *)info->fw->data; | |
| 4338 | − adev->firmware.fw_size += | |
| 4339 | − ALIGN(le32_to_cpu(header->ucode_size_bytes) - | |
| 4340 | − le32_to_cpu(cp_hdr->jt_size) * 4, | |
| 4341 | − PAGE_SIZE); | |
| 4342 | − info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC2_JT]; | |
| 4343 | − info->ucode_id = AMDGPU_UCODE_ID_CP_MEC2_JT; | |
| 4344 | − info->fw = adev->gfx.mec2_fw; | |
| 4345 | − adev->firmware.fw_size += | |
| 4346 | − ALIGN(le32_to_cpu(cp_hdr->jt_size) * 4, | |
| 4347 | − PAGE_SIZE); | |
| 4348 | − } | |
| 4349 | − } | |
| 4350 | − | |
| 4351 | 4103 | gfx_v10_0_check_fw_write_wait(adev); |
| 4352 | 4104 | out: |
| 4353 | 4105 | if (err) { |
| 4354 | 4106 | dev_err(adev->dev, |
| 4355 | − "gfx10: Failed to load firmware \"%s\"\n", | |
| 4107 | + "gfx10: Failed to init firmware \"%s\"\n", | |
| 4356 | 4108 | fw_name); |
| 4357 | 4109 | release_firmware(adev->gfx.pfp_fw); |
| 4358 | 4110 | adev->gfx.pfp_fw = NULL; |
| @@ -5981,6 +5733,9 @@ static int gfx_v10_0_cp_gfx_enable(struct amdgpu_device *adev, bool enable) · 1622 unmodified lines | ||
| 5981 | 5733 | WREG32_SOC15(GC, 0, mmCP_ME_CNTL, tmp); |
| 5982 | 5734 | } |
| 5983 | 5735 | |
| 5736 | + if (adev->job_hang && !enable) | |
| 5737 | + return 0; | |
| 5738 | + | |
| 5984 | 5739 | for (i = 0; i < adev->usec_timeout; i++) { |
| 5985 | 5740 | if (RREG32_SOC15(GC, 0, mmCP_STAT) == 0) |
| 5986 | 5741 | break; |
| @@ -7579,8 +7334,10 @@ static int gfx_v10_0_kiq_disable_kgq(struct amdgpu_device *adev) · 1592 unmodified lines | ||
| 7579 | 7334 | for (i = 0; i < adev->gfx.num_gfx_rings; i++) |
| 7580 | 7335 | kiq->pmf->kiq_unmap_queues(kiq_ring, &adev->gfx.gfx_ring[i], |
| 7581 | 7336 | PREEMPT_QUEUES, 0, 0); |
| 7582 | − | |
| 7583 | − return amdgpu_ring_test_helper(kiq_ring); | |
| 7337 | + if (!adev->job_hang) | |
| 7338 | + return amdgpu_ring_test_helper(kiq_ring); | |
| 7339 | + else | |
| 7340 | + return 0; | |
| 7584 | 7341 | } |
| 7585 | 7342 | #endif |
| 7586 | 7343 | |
| @@ -73,21 +73,10 @@ MODULE_FIRMWARE("amdgpu/gc_11_0_2_pfp.bin"); · 72 unmodified lines | ||
| 73 | 73 | MODULE_FIRMWARE("amdgpu/gc_11_0_2_me.bin"); |
| 74 | 74 | MODULE_FIRMWARE("amdgpu/gc_11_0_2_mec.bin"); |
| 75 | 75 | MODULE_FIRMWARE("amdgpu/gc_11_0_2_rlc.bin"); |
| 76 | − | |
| 77 | −static const struct soc15_reg_golden golden_settings_gc_11_0[] = | |
| 78 | −{ | |
| 79 | − /* Pending on emulation bring up */ | |
| 80 | −}; | |
| 81 | − | |
| 82 | −static const struct soc15_reg_golden golden_settings_gc_11_0_0[] = | |
| 83 | −{ | |
| 84 | − /* Pending on emulation bring up */ | |
| 85 | −}; | |
| 86 | − | |
| 87 | −static const struct soc15_reg_golden golden_settings_gc_rlc_spm_11_0[] = | |
| 88 | −{ | |
| 89 | − /* Pending on emulation bring up */ | |
| 90 | −}; | |
| 76 | +MODULE_FIRMWARE("amdgpu/gc_11_0_3_pfp.bin"); | |
| 77 | +MODULE_FIRMWARE("amdgpu/gc_11_0_3_me.bin"); | |
| 78 | +MODULE_FIRMWARE("amdgpu/gc_11_0_3_mec.bin"); | |
| 79 | +MODULE_FIRMWARE("amdgpu/gc_11_0_3_rlc.bin"); | |
| 91 | 80 | |
| 92 | 81 | static const struct soc15_reg_golden golden_settings_gc_11_0_1[] = |
| 93 | 82 | { |
| @@ -269,34 +258,10 @@ static void gfx_v11_0_set_kiq_pm4_funcs(struct amdgpu_device *adev) · 175 unmodified lines | ||
| 269 | 258 | adev->gfx.kiq.pmf = &gfx_v11_0_kiq_pm4_funcs; |
| 270 | 259 | } |
| 271 | 260 | |
| 272 | −static void gfx_v11_0_init_spm_golden_registers(struct amdgpu_device *adev) | |
| 273 | −{ | |
| 274 | − switch (adev->ip_versions[GC_HWIP][0]) { | |
| 275 | − case IP_VERSION(11, 0, 0): | |
| 276 | − soc15_program_register_sequence(adev, | |
| 277 | − golden_settings_gc_rlc_spm_11_0, | |
| 278 | − (const u32)ARRAY_SIZE(golden_settings_gc_rlc_spm_11_0)); | |
| 279 | − break; | |
| 280 | − default: | |
| 281 | − break; | |
| 282 | − } | |
| 283 | −} | |
| 284 | − | |
| 285 | 261 | static void gfx_v11_0_init_golden_registers(struct amdgpu_device *adev) |
| 286 | 262 | { |
| 287 | 263 | switch (adev->ip_versions[GC_HWIP][0]) { |
| 288 | − case IP_VERSION(11, 0, 0): | |
| 289 | − soc15_program_register_sequence(adev, | |
| 290 | − golden_settings_gc_11_0, | |
| 291 | − (const u32)ARRAY_SIZE(golden_settings_gc_11_0)); | |
| 292 | − soc15_program_register_sequence(adev, | |
| 293 | − golden_settings_gc_11_0_0, | |
| 294 | − (const u32)ARRAY_SIZE(golden_settings_gc_11_0_0)); | |
| 295 | − break; | |
| 296 | 264 | case IP_VERSION(11, 0, 1): |
| 297 | − soc15_program_register_sequence(adev, | |
| 298 | − golden_settings_gc_11_0, | |
| 299 | − (const u32)ARRAY_SIZE(golden_settings_gc_11_0)); | |
| 300 | 265 | soc15_program_register_sequence(adev, |
| 301 | 266 | golden_settings_gc_11_0_1, |
| 302 | 267 | (const u32)ARRAY_SIZE(golden_settings_gc_11_0_1)); |
| @@ -304,7 +269,6 @@ static void gfx_v11_0_init_golden_registers(struct amdgpu_device *adev) · 1 unmodified line | ||
| 304 | 269 | default: |
| 305 | 270 | break; |
| 306 | 271 | } |
| 307 | − gfx_v11_0_init_spm_golden_registers(adev); | |
| 308 | 272 | } |
| 309 | 273 | |
| 310 | 274 | static void gfx_v11_0_write_data_to_reg(struct amdgpu_ring *ring, int eng_sel, |
| @@ -479,10 +443,6 @@ static int gfx_v11_0_init_microcode(struct amdgpu_device *adev) · 168 unmodified lines | ||
| 479 | 443 | char fw_name[40]; |
| 480 | 444 | char ucode_prefix[30]; |
| 481 | 445 | int err; |
| 482 | − struct amdgpu_firmware_info *info = NULL; | |
| 483 | − const struct common_firmware_header *header = NULL; | |
| 484 | − const struct gfx_firmware_header_v1_0 *cp_hdr; | |
| 485 | − const struct gfx_firmware_header_v2_0 *cp_hdr_v2_0; | |
| 486 | 446 | const struct rlc_firmware_header_v2_0 *rlc_hdr; |
| 487 | 447 | uint16_t version_major; |
| 488 | 448 | uint16_t version_minor; |
| @@ -504,14 +464,11 @@ static int gfx_v11_0_init_microcode(struct amdgpu_device *adev) · 15 unmodified lines | ||
| 504 | 464 | adev->gfx.pfp_fw->data, 2, 0); |
| 505 | 465 | if (adev->gfx.rs64_enable) { |
| 506 | 466 | dev_info(adev->dev, "CP RS64 enable\n"); |
| 507 | − cp_hdr_v2_0 = (const struct gfx_firmware_header_v2_0 *)adev->gfx.pfp_fw->data; | |
| 508 | − adev->gfx.pfp_fw_version = le32_to_cpu(cp_hdr_v2_0->header.ucode_version); | |
| 509 | − adev->gfx.pfp_feature_version = le32_to_cpu(cp_hdr_v2_0->ucode_feature_version); | |
| 510 | − | |
| 467 | + amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_PFP); | |
| 468 | + amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_PFP_P0_STACK); | |
| 469 | + amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_PFP_P1_STACK); | |
| 511 | 470 | } else { |
| 512 | − cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data; | |
| 513 | − adev->gfx.pfp_fw_version = le32_to_cpu(cp_hdr->header.ucode_version); | |
| 514 | − adev->gfx.pfp_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version); | |
| 471 | + amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_PFP); | |
| 515 | 472 | } |
| 516 | 473 | |
| 517 | 474 | snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_me.bin", ucode_prefix); |
| @@ -522,14 +479,11 @@ static int gfx_v11_0_init_microcode(struct amdgpu_device *adev) · 4 unmodified lines | ||
| 522 | 479 | if (err) |
| 523 | 480 | goto out; |
| 524 | 481 | if (adev->gfx.rs64_enable) { |
| 525 | − cp_hdr_v2_0 = (const struct gfx_firmware_header_v2_0 *)adev->gfx.me_fw->data; | |
| 526 | − adev->gfx.me_fw_version = le32_to_cpu(cp_hdr_v2_0->header.ucode_version); | |
| 527 | − adev->gfx.me_feature_version = le32_to_cpu(cp_hdr_v2_0->ucode_feature_version); | |
| 528 | − | |
| 482 | + amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_ME); | |
| 483 | + amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_ME_P0_STACK); | |
| 484 | + amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_ME_P1_STACK); | |
| 529 | 485 | } else { |
| 530 | − cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data; | |
| 531 | − adev->gfx.me_fw_version = le32_to_cpu(cp_hdr->header.ucode_version); | |
| 532 | − adev->gfx.me_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version); | |
| 486 | + amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_ME); | |
| 533 | 487 | } |
| 534 | 488 | |
| 535 | 489 | if (!amdgpu_sriov_vf(adev)) { |
| @@ -556,136 +510,23 @@ static int gfx_v11_0_init_microcode(struct amdgpu_device *adev) · 20 unmodified lines | ||
| 556 | 510 | if (err) |
| 557 | 511 | goto out; |
| 558 | 512 | if (adev->gfx.rs64_enable) { |
| 559 | − cp_hdr_v2_0 = (const struct gfx_firmware_header_v2_0 *)adev->gfx.mec_fw->data; | |
| 560 | − adev->gfx.mec_fw_version = le32_to_cpu(cp_hdr_v2_0->header.ucode_version); | |
| 561 | − adev->gfx.mec_feature_version = le32_to_cpu(cp_hdr_v2_0->ucode_feature_version); | |
| 562 | − | |
| 513 | + amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_MEC); | |
| 514 | + amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_MEC_P0_STACK); | |
| 515 | + amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_MEC_P1_STACK); | |
| 516 | + amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_MEC_P2_STACK); | |
| 517 | + amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_MEC_P3_STACK); | |
| 563 | 518 | } else { |
| 564 | − cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data; | |
| 565 | − adev->gfx.mec_fw_version = le32_to_cpu(cp_hdr->header.ucode_version); | |
| 566 | − adev->gfx.mec_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version); | |
| 519 | + amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_MEC1); | |
| 520 | + amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_MEC1_JT); | |
| 567 | 521 | } |
| 568 | 522 | |
| 569 | 523 | /* only one MEC for gfx 11.0.0. */ |
| 570 | 524 | adev->gfx.mec2_fw = NULL; |
| 571 | 525 | |
| 572 | − if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { | |
| 573 | − if (adev->gfx.rs64_enable) { | |
| 574 | − cp_hdr_v2_0 = (const struct gfx_firmware_header_v2_0 *)adev->gfx.pfp_fw->data; | |
| 575 | − info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_RS64_PFP]; | |
| 576 | − info->ucode_id = AMDGPU_UCODE_ID_CP_RS64_PFP; | |
| 577 | − info->fw = adev->gfx.pfp_fw; | |
| 578 | − header = (const struct common_firmware_header *)info->fw->data; | |
| 579 | − adev->firmware.fw_size += | |
| 580 | − ALIGN(le32_to_cpu(cp_hdr_v2_0->ucode_size_bytes), PAGE_SIZE); | |
| 581 | − | |
| 582 | − info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_RS64_PFP_P0_STACK]; | |
| 583 | − info->ucode_id = AMDGPU_UCODE_ID_CP_RS64_PFP_P0_STACK; | |
| 584 | − info->fw = adev->gfx.pfp_fw; | |
| 585 | − header = (const struct common_firmware_header *)info->fw->data; | |
| 586 | − adev->firmware.fw_size += | |
| 587 | − ALIGN(le32_to_cpu(cp_hdr_v2_0->data_size_bytes), PAGE_SIZE); | |
| 588 | − | |
| 589 | − info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_RS64_PFP_P1_STACK]; | |
| 590 | − info->ucode_id = AMDGPU_UCODE_ID_CP_RS64_PFP_P1_STACK; | |
| 591 | − info->fw = adev->gfx.pfp_fw; | |
| 592 | − header = (const struct common_firmware_header *)info->fw->data; | |
| 593 | − adev->firmware.fw_size += | |
| 594 | − ALIGN(le32_to_cpu(cp_hdr_v2_0->data_size_bytes), PAGE_SIZE); | |
| 595 | − | |
| 596 | − cp_hdr_v2_0 = (const struct gfx_firmware_header_v2_0 *)adev->gfx.me_fw->data; | |
| 597 | − info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_RS64_ME]; | |
| 598 | − info->ucode_id = AMDGPU_UCODE_ID_CP_RS64_ME; | |
| 599 | − info->fw = adev->gfx.me_fw; | |
| 600 | − header = (const struct common_firmware_header *)info->fw->data; | |
| 601 | − adev->firmware.fw_size += | |
| 602 | − ALIGN(le32_to_cpu(cp_hdr_v2_0->ucode_size_bytes), PAGE_SIZE); | |
| 603 | − | |
| 604 | − info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_RS64_ME_P0_STACK]; | |
| 605 | − info->ucode_id = AMDGPU_UCODE_ID_CP_RS64_ME_P0_STACK; | |
| 606 | − info->fw = adev->gfx.me_fw; | |
| 607 | − header = (const struct common_firmware_header *)info->fw->data; | |
| 608 | − adev->firmware.fw_size += | |
| 609 | − ALIGN(le32_to_cpu(cp_hdr_v2_0->data_size_bytes), PAGE_SIZE); | |
| 610 | − | |
| 611 | − info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_RS64_ME_P1_STACK]; | |
| 612 | − info->ucode_id = AMDGPU_UCODE_ID_CP_RS64_ME_P1_STACK; | |
| 613 | − info->fw = adev->gfx.me_fw; | |
| 614 | − header = (const struct common_firmware_header *)info->fw->data; | |
| 615 | − adev->firmware.fw_size += | |
| 616 | − ALIGN(le32_to_cpu(cp_hdr_v2_0->data_size_bytes), PAGE_SIZE); | |
| 617 | − | |
| 618 | − cp_hdr_v2_0 = (const struct gfx_firmware_header_v2_0 *)adev->gfx.mec_fw->data; | |
| 619 | − info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_RS64_MEC]; | |
| 620 | − info->ucode_id = AMDGPU_UCODE_ID_CP_RS64_MEC; | |
| 621 | − info->fw = adev->gfx.mec_fw; | |
| 622 | − header = (const struct common_firmware_header *)info->fw->data; | |
| 623 | − adev->firmware.fw_size += | |
| 624 | − ALIGN(le32_to_cpu(cp_hdr_v2_0->ucode_size_bytes), PAGE_SIZE); | |
| 625 | − | |
| 626 | − info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_RS64_MEC_P0_STACK]; | |
| 627 | − info->ucode_id = AMDGPU_UCODE_ID_CP_RS64_MEC_P0_STACK; | |
| 628 | − info->fw = adev->gfx.mec_fw; | |
| 629 | − header = (const struct common_firmware_header *)info->fw->data; | |
| 630 | − adev->firmware.fw_size += | |
| 631 | − ALIGN(le32_to_cpu(cp_hdr_v2_0->data_size_bytes), PAGE_SIZE); | |
| 632 | − | |
| 633 | − info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_RS64_MEC_P1_STACK]; | |
| 634 | − info->ucode_id = AMDGPU_UCODE_ID_CP_RS64_MEC_P1_STACK; | |
| 635 | − info->fw = adev->gfx.mec_fw; | |
| 636 | − header = (const struct common_firmware_header *)info->fw->data; | |
| 637 | − adev->firmware.fw_size += | |
| 638 | − ALIGN(le32_to_cpu(cp_hdr_v2_0->data_size_bytes), PAGE_SIZE); | |
| 639 | − | |
| 640 | − info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_RS64_MEC_P2_STACK]; | |
| 641 | − info->ucode_id = AMDGPU_UCODE_ID_CP_RS64_MEC_P2_STACK; | |
| 642 | − info->fw = adev->gfx.mec_fw; | |
| 643 | − header = (const struct common_firmware_header *)info->fw->data; | |
| 644 | − adev->firmware.fw_size += | |
| 645 | − ALIGN(le32_to_cpu(cp_hdr_v2_0->data_size_bytes), PAGE_SIZE); | |
| 646 | − | |
| 647 | − info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_RS64_MEC_P3_STACK]; | |
| 648 | − info->ucode_id = AMDGPU_UCODE_ID_CP_RS64_MEC_P3_STACK; | |
| 649 | − info->fw = adev->gfx.mec_fw; | |
| 650 | − header = (const struct common_firmware_header *)info->fw->data; | |
| 651 | − adev->firmware.fw_size += | |
| 652 | − ALIGN(le32_to_cpu(cp_hdr_v2_0->data_size_bytes), PAGE_SIZE); | |
| 653 | − } else { | |
| 654 | − info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_PFP]; | |
| 655 | − info->ucode_id = AMDGPU_UCODE_ID_CP_PFP; | |
| 656 | − info->fw = adev->gfx.pfp_fw; | |
| 657 | − header = (const struct common_firmware_header *)info->fw->data; | |
| 658 | − adev->firmware.fw_size += | |
| 659 | − ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE); | |
| 660 | − | |
| 661 | − info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_ME]; | |
| 662 | − info->ucode_id = AMDGPU_UCODE_ID_CP_ME; | |
| 663 | − info->fw = adev->gfx.me_fw; | |
| 664 | − header = (const struct common_firmware_header *)info->fw->data; | |
| 665 | − adev->firmware.fw_size += | |
| 666 | − ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE); | |
| 667 | − | |
| 668 | − info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC1]; | |
| 669 | − info->ucode_id = AMDGPU_UCODE_ID_CP_MEC1; | |
| 670 | − info->fw = adev->gfx.mec_fw; | |
| 671 | − header = (const struct common_firmware_header *)info->fw->data; | |
| 672 | − cp_hdr = (const struct gfx_firmware_header_v1_0 *)info->fw->data; | |
| 673 | − adev->firmware.fw_size += | |
| 674 | − ALIGN(le32_to_cpu(header->ucode_size_bytes) - | |
| 675 | − le32_to_cpu(cp_hdr->jt_size) * 4, PAGE_SIZE); | |
| 676 | − | |
| 677 | − info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC1_JT]; | |
| 678 | − info->ucode_id = AMDGPU_UCODE_ID_CP_MEC1_JT; | |
| 679 | − info->fw = adev->gfx.mec_fw; | |
| 680 | − adev->firmware.fw_size += | |
| 681 | − ALIGN(le32_to_cpu(cp_hdr->jt_size) * 4, PAGE_SIZE); | |
| 682 | − } | |
| 683 | − } | |
| 684 | − | |
| 685 | 526 | out: |
| 686 | 527 | if (err) { |
| 687 | 528 | dev_err(adev->dev, |
| 688 | − "gfx11: Failed to load firmware \"%s\"\n", | |
| 529 | + "gfx11: Failed to init firmware \"%s\"\n", | |
| 689 | 530 | fw_name); |
| 690 | 531 | release_firmware(adev->gfx.pfp_fw); |
| 691 | 532 | adev->gfx.pfp_fw = NULL; |
| @@ -997,7 +838,6 @@ static const struct amdgpu_gfx_funcs gfx_v11_0_gfx_funcs = { · 305 unmodified lines | ||
| 997 | 838 | .read_wave_sgprs = &gfx_v11_0_read_wave_sgprs, |
| 998 | 839 | .read_wave_vgprs = &gfx_v11_0_read_wave_vgprs, |
| 999 | 840 | .select_me_pipe_q = &gfx_v11_0_select_me_pipe_q, |
| 1000 | − .init_spm_golden = &gfx_v11_0_init_spm_golden_registers, | |
| 1001 | 841 | .update_perfmon_mgcg = &gfx_v11_0_update_perf_clk, |
| 1002 | 842 | }; |
| 1003 | 843 | |
| @@ -1008,6 +848,7 @@ static int gfx_v11_0_gpu_early_init(struct amdgpu_device *adev) · 4 unmodified lines | ||
| 1008 | 848 | switch (adev->ip_versions[GC_HWIP][0]) { |
| 1009 | 849 | case IP_VERSION(11, 0, 0): |
| 1010 | 850 | case IP_VERSION(11, 0, 2): |
| 851 | + case IP_VERSION(11, 0, 3): | |
| 1011 | 852 | adev->gfx.config.max_hw_contexts = 8; |
| 1012 | 853 | adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; |
| 1013 | 854 | adev->gfx.config.sc_prim_fifo_size_backend = 0x100; |
| @@ -1443,6 +1284,7 @@ static int gfx_v11_0_sw_init(void *handle) · 429 unmodified lines | ||
| 1443 | 1284 | case IP_VERSION(11, 0, 0): |
| 1444 | 1285 | case IP_VERSION(11, 0, 1): |
| 1445 | 1286 | case IP_VERSION(11, 0, 2): |
| 1287 | + case IP_VERSION(11, 0, 3): | |
| 1446 | 1288 | adev->gfx.me.num_me = 1; |
| 1447 | 1289 | adev->gfx.me.num_pipe_per_me = 1; |
| 1448 | 1290 | adev->gfx.me.num_queue_per_pipe = 1; |
| @@ -2617,6 +2459,21 @@ static void gfx_v11_0_config_gfx_rs64(struct amdgpu_device *adev) · 1168 unmodified lines | ||
| 2617 | 2459 | mec_hdr->ucode_start_addr_hi >> 2); |
| 2618 | 2460 | } |
| 2619 | 2461 | soc21_grbm_select(adev, 0, 0, 0, 0); |
| 2462 | + | |
| 2463 | + /* reset mec pipe */ | |
| 2464 | + tmp = RREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL); | |
| 2465 | + tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE0_RESET, 1); | |
| 2466 | + tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE1_RESET, 1); | |
| 2467 | + tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE2_RESET, 1); | |
| 2468 | + tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE3_RESET, 1); | |
| 2469 | + WREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL, tmp); | |
| 2470 | + | |
| 2471 | + /* clear mec pipe reset */ | |
| 2472 | + tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE0_RESET, 0); | |
| 2473 | + tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE1_RESET, 0); | |
| 2474 | + tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE2_RESET, 0); | |
| 2475 | + tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE3_RESET, 0); | |
| 2476 | + WREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL, tmp); | |
| 2620 | 2477 | } |
| 2621 | 2478 | |
| 2622 | 2479 | static int gfx_v11_0_wait_for_rlc_autoload_complete(struct amdgpu_device *adev) |
| @@ -126,6 +126,8 @@ MODULE_FIRMWARE("amdgpu/green_sardine_rlc.bin"); · 125 unmodified lines | ||
| 126 | 126 | MODULE_FIRMWARE("amdgpu/aldebaran_mec.bin"); |
| 127 | 127 | MODULE_FIRMWARE("amdgpu/aldebaran_mec2.bin"); |
| 128 | 128 | MODULE_FIRMWARE("amdgpu/aldebaran_rlc.bin"); |
| 129 | +MODULE_FIRMWARE("amdgpu/aldebaran_sjt_mec.bin"); | |
| 130 | +MODULE_FIRMWARE("amdgpu/aldebaran_sjt_mec2.bin"); | |
| 129 | 131 | |
| 130 | 132 | #define mmTCP_CHAN_STEER_0_ARCT 0x0b03 |
| 131 | 133 | #define mmTCP_CHAN_STEER_0_ARCT_BASE_IDX 0 |
| @@ -1089,27 +1091,6 @@ static void gfx_v9_0_free_microcode(struct amdgpu_device *adev) · 957 unmodified lines | ||
| 1089 | 1091 | kfree(adev->gfx.rlc.register_list_format); |
| 1090 | 1092 | } |
| 1091 | 1093 | |
| 1092 | −static void gfx_v9_0_init_rlc_ext_microcode(struct amdgpu_device *adev) | |
| 1093 | −{ | |
| 1094 | − const struct rlc_firmware_header_v2_1 *rlc_hdr; | |
| 1095 | − | |
| 1096 | − rlc_hdr = (const struct rlc_firmware_header_v2_1 *)adev->gfx.rlc_fw->data; | |
| 1097 | − adev->gfx.rlc_srlc_fw_version = le32_to_cpu(rlc_hdr->save_restore_list_cntl_ucode_ver); | |
| 1098 | − adev->gfx.rlc_srlc_feature_version = le32_to_cpu(rlc_hdr->save_restore_list_cntl_feature_ver); | |
| 1099 | − adev->gfx.rlc.save_restore_list_cntl_size_bytes = le32_to_cpu(rlc_hdr->save_restore_list_cntl_size_bytes); | |
| 1100 | − adev->gfx.rlc.save_restore_list_cntl = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->save_restore_list_cntl_offset_bytes); | |
| 1101 | − adev->gfx.rlc_srlg_fw_version = le32_to_cpu(rlc_hdr->save_restore_list_gpm_ucode_ver); | |
| 1102 | − adev->gfx.rlc_srlg_feature_version = le32_to_cpu(rlc_hdr->save_restore_list_gpm_feature_ver); | |
| 1103 | − adev->gfx.rlc.save_restore_list_gpm_size_bytes = le32_to_cpu(rlc_hdr->save_restore_list_gpm_size_bytes); | |
| 1104 | − adev->gfx.rlc.save_restore_list_gpm = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->save_restore_list_gpm_offset_bytes); | |
| 1105 | − adev->gfx.rlc_srls_fw_version = le32_to_cpu(rlc_hdr->save_restore_list_srm_ucode_ver); | |
| 1106 | − adev->gfx.rlc_srls_feature_version = le32_to_cpu(rlc_hdr->save_restore_list_srm_feature_ver); | |
| 1107 | − adev->gfx.rlc.save_restore_list_srm_size_bytes = le32_to_cpu(rlc_hdr->save_restore_list_srm_size_bytes); | |
| 1108 | − adev->gfx.rlc.save_restore_list_srm = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->save_restore_list_srm_offset_bytes); | |
| 1109 | − adev->gfx.rlc.reg_list_format_direct_reg_list_length = | |
| 1110 | − le32_to_cpu(rlc_hdr->reg_list_format_direct_reg_list_length); | |
| 1111 | −} | |
| 1112 | − | |
| 1113 | 1094 | static void gfx_v9_0_check_fw_write_wait(struct amdgpu_device *adev) |
| 1114 | 1095 | { |
| 1115 | 1096 | adev->gfx.me_fw_write_wait = false; |
| @@ -1271,9 +1252,6 @@ static int gfx_v9_0_init_cp_gfx_microcode(struct amdgpu_device *adev, · 155 unmodified lines | ||
| 1271 | 1252 | { |
| 1272 | 1253 | char fw_name[30]; |
| 1273 | 1254 | int err; |
| 1274 | − struct amdgpu_firmware_info *info = NULL; | |
| 1275 | − const struct common_firmware_header *header = NULL; | |
| 1276 | − const struct gfx_firmware_header_v1_0 *cp_hdr; | |
| 1277 | 1255 | |
| 1278 | 1256 | snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_pfp.bin", chip_name); |
| 1279 | 1257 | err = request_firmware(&adev->gfx.pfp_fw, fw_name, adev->dev); |
| @@ -1282,9 +1260,7 @@ static int gfx_v9_0_init_cp_gfx_microcode(struct amdgpu_device *adev, · 2 unmodified lines | ||
| 1282 | 1260 | err = amdgpu_ucode_validate(adev->gfx.pfp_fw); |
| 1283 | 1261 | if (err) |
| 1284 | 1262 | goto out; |
| 1285 | − cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data; | |
| 1286 | − adev->gfx.pfp_fw_version = le32_to_cpu(cp_hdr->header.ucode_version); | |
| 1287 | − adev->gfx.pfp_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version); | |
| 1263 | + amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_PFP); | |
| 1288 | 1264 | |
| 1289 | 1265 | snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_me.bin", chip_name); |
| 1290 | 1266 | err = request_firmware(&adev->gfx.me_fw, fw_name, adev->dev); |
| @@ -1293,9 +1269,7 @@ static int gfx_v9_0_init_cp_gfx_microcode(struct amdgpu_device *adev, · 2 unmodified lines | ||
| 1293 | 1269 | err = amdgpu_ucode_validate(adev->gfx.me_fw); |
| 1294 | 1270 | if (err) |
| 1295 | 1271 | goto out; |
| 1296 | − cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data; | |
| 1297 | − adev->gfx.me_fw_version = le32_to_cpu(cp_hdr->header.ucode_version); | |
| 1298 | − adev->gfx.me_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version); | |
| 1272 | + amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_ME); | |
| 1299 | 1273 | |
| 1300 | 1274 | snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ce.bin", chip_name); |
| 1301 | 1275 | err = request_firmware(&adev->gfx.ce_fw, fw_name, adev->dev); |
| @@ -1304,37 +1278,12 @@ static int gfx_v9_0_init_cp_gfx_microcode(struct amdgpu_device *adev, · 2 unmodified lines | ||
| 1304 | 1278 | err = amdgpu_ucode_validate(adev->gfx.ce_fw); |
| 1305 | 1279 | if (err) |
| 1306 | 1280 | goto out; |
| 1307 | − cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data; | |
| 1308 | − adev->gfx.ce_fw_version = le32_to_cpu(cp_hdr->header.ucode_version); | |
| 1309 | − adev->gfx.ce_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version); | |
| 1310 | − | |
| 1311 | − if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { | |
| 1312 | − info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_PFP]; | |
| 1313 | − info->ucode_id = AMDGPU_UCODE_ID_CP_PFP; | |
| 1314 | − info->fw = adev->gfx.pfp_fw; | |
| 1315 | − header = (const struct common_firmware_header *)info->fw->data; | |
| 1316 | − adev->firmware.fw_size += | |
| 1317 | − ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE); | |
| 1318 | − | |
| 1319 | − info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_ME]; | |
| 1320 | − info->ucode_id = AMDGPU_UCODE_ID_CP_ME; | |
| 1321 | − info->fw = adev->gfx.me_fw; | |
| 1322 | − header = (const struct common_firmware_header *)info->fw->data; | |
| 1323 | − adev->firmware.fw_size += | |
| 1324 | − ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE); | |
| 1325 | − | |
| 1326 | − info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_CE]; | |
| 1327 | − info->ucode_id = AMDGPU_UCODE_ID_CP_CE; | |
| 1328 | − info->fw = adev->gfx.ce_fw; | |
| 1329 | − header = (const struct common_firmware_header *)info->fw->data; | |
| 1330 | − adev->firmware.fw_size += | |
| 1331 | − ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE); | |
| 1332 | − } | |
| 1281 | + amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_CE); | |
| 1333 | 1282 | |
| 1334 | 1283 | out: |
| 1335 | 1284 | if (err) { |
| 1336 | 1285 | dev_err(adev->dev, |
| 1337 | − "gfx9: Failed to load firmware \"%s\"\n", | |
| 1286 | + "gfx9: Failed to init firmware \"%s\"\n", | |
| 1338 | 1287 | fw_name); |
| 1339 | 1288 | release_firmware(adev->gfx.pfp_fw); |
| 1340 | 1289 | adev->gfx.pfp_fw = NULL; |
| @@ -1351,11 +1300,7 @@ static int gfx_v9_0_init_rlc_microcode(struct amdgpu_device *adev, · 10 unmodified lines | ||
| 1351 | 1300 | { |
| 1352 | 1301 | char fw_name[30]; |
| 1353 | 1302 | int err; |
| 1354 | − struct amdgpu_firmware_info *info = NULL; | |
| 1355 | − const struct common_firmware_header *header = NULL; | |
| 1356 | 1303 | const struct rlc_firmware_header_v2_0 *rlc_hdr; |
| 1357 | − unsigned int *tmp = NULL; | |
| 1358 | − unsigned int i = 0; | |
| 1359 | 1304 | uint16_t version_major; |
| 1360 | 1305 | uint16_t version_minor; |
| 1361 | 1306 | uint32_t smu_version; |
| @@ -1384,92 +1329,17 @@ static int gfx_v9_0_init_rlc_microcode(struct amdgpu_device *adev, · 22 unmodified lines | ||
| 1384 | 1329 | if (err) |
| 1385 | 1330 | goto out; |
| 1386 | 1331 | err = amdgpu_ucode_validate(adev->gfx.rlc_fw); |
| 1332 | + if (err) | |
| 1333 | + goto out; | |
| 1387 | 1334 | rlc_hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data; |
| 1388 | 1335 | |
| 1389 | 1336 | version_major = le16_to_cpu(rlc_hdr->header.header_version_major); |
| 1390 | 1337 | version_minor = le16_to_cpu(rlc_hdr->header.header_version_minor); |
| 1391 | − if (version_major == 2 && version_minor == 1) | |
| 1392 | − adev->gfx.rlc.is_rlc_v2_1 = true; | |
| 1393 | − | |
| 1394 | − adev->gfx.rlc_fw_version = le32_to_cpu(rlc_hdr->header.ucode_version); | |
| 1395 | − adev->gfx.rlc_feature_version = le32_to_cpu(rlc_hdr->ucode_feature_version); | |
| 1396 | − adev->gfx.rlc.save_and_restore_offset = | |
| 1397 | − le32_to_cpu(rlc_hdr->save_and_restore_offset); | |
| 1398 | − adev->gfx.rlc.clear_state_descriptor_offset = | |
| 1399 | − le32_to_cpu(rlc_hdr->clear_state_descriptor_offset); | |
| 1400 | − adev->gfx.rlc.avail_scratch_ram_locations = | |
| 1401 | − le32_to_cpu(rlc_hdr->avail_scratch_ram_locations); | |
| 1402 | − adev->gfx.rlc.reg_restore_list_size = | |
| 1403 | − le32_to_cpu(rlc_hdr->reg_restore_list_size); | |
| 1404 | − adev->gfx.rlc.reg_list_format_start = | |
| 1405 | − le32_to_cpu(rlc_hdr->reg_list_format_start); | |
| 1406 | − adev->gfx.rlc.reg_list_format_separate_start = | |
| 1407 | − le32_to_cpu(rlc_hdr->reg_list_format_separate_start); | |
| 1408 | − adev->gfx.rlc.starting_offsets_start = | |
| 1409 | − le32_to_cpu(rlc_hdr->starting_offsets_start); | |
| 1410 | − adev->gfx.rlc.reg_list_format_size_bytes = | |
| 1411 | − le32_to_cpu(rlc_hdr->reg_list_format_size_bytes); | |
| 1412 | − adev->gfx.rlc.reg_list_size_bytes = | |
| 1413 | − le32_to_cpu(rlc_hdr->reg_list_size_bytes); | |
| 1414 | − adev->gfx.rlc.register_list_format = | |
| 1415 | − kmalloc(adev->gfx.rlc.reg_list_format_size_bytes + | |
| 1416 | − adev->gfx.rlc.reg_list_size_bytes, GFP_KERNEL); | |
| 1417 | − if (!adev->gfx.rlc.register_list_format) { | |
| 1418 | − err = -ENOMEM; | |
| 1419 | − goto out; | |
| 1420 | − } | |
| 1421 | − | |
| 1422 | − tmp = (unsigned int *)((uintptr_t)rlc_hdr + | |
| 1423 | − le32_to_cpu(rlc_hdr->reg_list_format_array_offset_bytes)); | |
| 1424 | − for (i = 0 ; i < (adev->gfx.rlc.reg_list_format_size_bytes >> 2); i++) | |
| 1425 | − adev->gfx.rlc.register_list_format[i] = le32_to_cpu(tmp[i]); | |
| 1426 | − | |
| 1427 | − adev->gfx.rlc.register_restore = adev->gfx.rlc.register_list_format + i; | |
| 1428 | − | |
| 1429 | − tmp = (unsigned int *)((uintptr_t)rlc_hdr + | |
| 1430 | − le32_to_cpu(rlc_hdr->reg_list_array_offset_bytes)); | |
| 1431 | − for (i = 0 ; i < (adev->gfx.rlc.reg_list_size_bytes >> 2); i++) | |
| 1432 | − adev->gfx.rlc.register_restore[i] = le32_to_cpu(tmp[i]); | |
| 1433 | − | |
| 1434 | − if (adev->gfx.rlc.is_rlc_v2_1) | |
| 1435 | − gfx_v9_0_init_rlc_ext_microcode(adev); | |
| 1436 | − | |
| 1437 | − if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { | |
| 1438 | − info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_G]; | |
| 1439 | − info->ucode_id = AMDGPU_UCODE_ID_RLC_G; | |
| 1440 | − info->fw = adev->gfx.rlc_fw; | |
| 1441 | − header = (const struct common_firmware_header *)info->fw->data; | |
| 1442 | − adev->firmware.fw_size += | |
| 1443 | − ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE); | |
| 1444 | − | |
| 1445 | − if (adev->gfx.rlc.is_rlc_v2_1 && | |
| 1446 | − adev->gfx.rlc.save_restore_list_cntl_size_bytes && | |
| 1447 | − adev->gfx.rlc.save_restore_list_gpm_size_bytes && | |
| 1448 | − adev->gfx.rlc.save_restore_list_srm_size_bytes) { | |
| 1449 | − info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL]; | |
| 1450 | − info->ucode_id = AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL; | |
| 1451 | − info->fw = adev->gfx.rlc_fw; | |
| 1452 | − adev->firmware.fw_size += | |
| 1453 | − ALIGN(adev->gfx.rlc.save_restore_list_cntl_size_bytes, PAGE_SIZE); | |
| 1454 | − | |
| 1455 | − info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM]; | |
| 1456 | − info->ucode_id = AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM; | |
| 1457 | − info->fw = adev->gfx.rlc_fw; | |
| 1458 | − adev->firmware.fw_size += | |
| 1459 | − ALIGN(adev->gfx.rlc.save_restore_list_gpm_size_bytes, PAGE_SIZE); | |
| 1460 | − | |
| 1461 | − info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM]; | |
| 1462 | − info->ucode_id = AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM; | |
| 1463 | − info->fw = adev->gfx.rlc_fw; | |
| 1464 | − adev->firmware.fw_size += | |
| 1465 | − ALIGN(adev->gfx.rlc.save_restore_list_srm_size_bytes, PAGE_SIZE); | |
| 1466 | − } | |
| 1467 | − } | |
| 1468 | − | |
| 1338 | + err = amdgpu_gfx_rlc_init_microcode(adev, version_major, version_minor); | |
| 1469 | 1339 | out: |
| 1470 | 1340 | if (err) { |
| 1471 | 1341 | dev_err(adev->dev, |
| 1472 | − "gfx9: Failed to load firmware \"%s\"\n", | |
| 1342 | + "gfx9: Failed to init firmware \"%s\"\n", | |
| 1473 | 1343 | fw_name); |
| 1474 | 1344 | release_firmware(adev->gfx.rlc_fw); |
| 1475 | 1345 | adev->gfx.rlc_fw = NULL; |
| @@ -1492,35 +1362,34 @@ static int gfx_v9_0_init_cp_compute_microcode(struct amdgpu_device *adev, · 16 unmodified lines | ||
| 1492 | 1362 | { |
| 1493 | 1363 | char fw_name[30]; |
| 1494 | 1364 | int err; |
| 1495 | − struct amdgpu_firmware_info *info = NULL; | |
| 1496 | − const struct common_firmware_header *header = NULL; | |
| 1497 | − const struct gfx_firmware_header_v1_0 *cp_hdr; | |
| 1498 | 1365 | |
| 1499 | − snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec.bin", chip_name); | |
| 1366 | + if (amdgpu_sriov_vf(adev) && (adev->asic_type == CHIP_ALDEBARAN)) | |
| 1367 | + snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sjt_mec.bin", chip_name); | |
| 1368 | + else | |
| 1369 | + snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec.bin", chip_name); | |
| 1370 | + | |
| 1500 | 1371 | err = request_firmware(&adev->gfx.mec_fw, fw_name, adev->dev); |
| 1501 | 1372 | if (err) |
| 1502 | 1373 | goto out; |
| 1503 | 1374 | err = amdgpu_ucode_validate(adev->gfx.mec_fw); |
| 1504 | 1375 | if (err) |
| 1505 | 1376 | goto out; |
| 1506 | − cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data; | |
| 1507 | − adev->gfx.mec_fw_version = le32_to_cpu(cp_hdr->header.ucode_version); | |
| 1508 | − adev->gfx.mec_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version); | |
| 1509 | − | |
| 1377 | + amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_MEC1); | |
| 1378 | + amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_MEC1_JT); | |
| 1510 | 1379 | |
| 1511 | 1380 | if (gfx_v9_0_load_mec2_fw_bin_support(adev)) { |
| 1512 | − snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec2.bin", chip_name); | |
| 1381 | + if (amdgpu_sriov_vf(adev) && (adev->asic_type == CHIP_ALDEBARAN)) | |
| 1382 | + snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sjt_mec2.bin", chip_name); | |
| 1383 | + else | |
| 1384 | + snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec2.bin", chip_name); | |
| 1385 | + | |
| 1513 | 1386 | err = request_firmware(&adev->gfx.mec2_fw, fw_name, adev->dev); |
| 1514 | 1387 | if (!err) { |
| 1515 | 1388 | err = amdgpu_ucode_validate(adev->gfx.mec2_fw); |
| 1516 | 1389 | if (err) |
| 1517 | 1390 | goto out; |
| 1518 | − cp_hdr = (const struct gfx_firmware_header_v1_0 *) | |
| 1519 | − adev->gfx.mec2_fw->data; | |
| 1520 | − adev->gfx.mec2_fw_version = | |
| 1521 | − le32_to_cpu(cp_hdr->header.ucode_version); | |
| 1522 | − adev->gfx.mec2_feature_version = | |
| 1523 | − le32_to_cpu(cp_hdr->ucode_feature_version); | |
| 1391 | + amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_MEC2); | |
| 1392 | + amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_MEC2_JT); | |
| 1524 | 1393 | } else { |
| 1525 | 1394 | err = 0; |
| 1526 | 1395 | adev->gfx.mec2_fw = NULL; |
| @@ -1530,49 +1399,12 @@ static int gfx_v9_0_init_cp_compute_microcode(struct amdgpu_device *adev, · 3 unmodified lines | ||
| 1530 | 1399 | adev->gfx.mec2_feature_version = adev->gfx.mec_feature_version; |
| 1531 | 1400 | } |
| 1532 | 1401 | |
| 1533 | − if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { | |
| 1534 | − info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC1]; | |
| 1535 | − info->ucode_id = AMDGPU_UCODE_ID_CP_MEC1; | |
| 1536 | − info->fw = adev->gfx.mec_fw; | |
| 1537 | − header = (const struct common_firmware_header *)info->fw->data; | |
| 1538 | − cp_hdr = (const struct gfx_firmware_header_v1_0 *)info->fw->data; | |
| 1539 | − adev->firmware.fw_size += | |
| 1540 | − ALIGN(le32_to_cpu(header->ucode_size_bytes) - le32_to_cpu(cp_hdr->jt_size) * 4, PAGE_SIZE); | |
| 1541 | − | |
| 1542 | − info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC1_JT]; | |
| 1543 | − info->ucode_id = AMDGPU_UCODE_ID_CP_MEC1_JT; | |
| 1544 | − info->fw = adev->gfx.mec_fw; | |
| 1545 | − adev->firmware.fw_size += | |
| 1546 | − ALIGN(le32_to_cpu(cp_hdr->jt_size) * 4, PAGE_SIZE); | |
| 1547 | − | |
| 1548 | − if (adev->gfx.mec2_fw) { | |
| 1549 | − info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC2]; | |
| 1550 | − info->ucode_id = AMDGPU_UCODE_ID_CP_MEC2; | |
| 1551 | − info->fw = adev->gfx.mec2_fw; | |
| 1552 | − header = (const struct common_firmware_header *)info->fw->data; | |
| 1553 | − cp_hdr = (const struct gfx_firmware_header_v1_0 *)info->fw->data; | |
| 1554 | − adev->firmware.fw_size += | |
| 1555 | − ALIGN(le32_to_cpu(header->ucode_size_bytes) - le32_to_cpu(cp_hdr->jt_size) * 4, PAGE_SIZE); | |
| 1556 | − | |
| 1557 | − /* TODO: Determine if MEC2 JT FW loading can be removed | |
| 1558 | − for all GFX V9 asic and above */ | |
| 1559 | − if (gfx_v9_0_load_mec2_fw_bin_support(adev)) { | |
| 1560 | − info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC2_JT]; | |
| 1561 | − info->ucode_id = AMDGPU_UCODE_ID_CP_MEC2_JT; | |
| 1562 | − info->fw = adev->gfx.mec2_fw; | |
| 1563 | − adev->firmware.fw_size += | |
| 1564 | − ALIGN(le32_to_cpu(cp_hdr->jt_size) * 4, | |
| 1565 | − PAGE_SIZE); | |
| 1566 | − } | |
| 1567 | − } | |
| 1568 | − } | |
| 1569 | − | |
| 1570 | 1402 | out: |
| 1571 | 1403 | gfx_v9_0_check_if_need_gfxoff(adev); |
| 1572 | 1404 | gfx_v9_0_check_fw_write_wait(adev); |
| 1573 | 1405 | if (err) { |
| 1574 | 1406 | dev_err(adev->dev, |
| 1575 | − "gfx9: Failed to load firmware \"%s\"\n", | |
| 1407 | + "gfx9: Failed to init firmware \"%s\"\n", | |
| 1576 | 1408 | fw_name); |
| 1577 | 1409 | release_firmware(adev->gfx.mec_fw); |
| 1578 | 1410 | adev->gfx.mec_fw = NULL; |
| @@ -576,6 +576,111 @@ static void gfxhub_v2_1_utcl2_harvest(struct amdgpu_device *adev) · 575 unmodified lines | ||
| 576 | 576 | } |
| 577 | 577 | } |
| 578 | 578 | |
| 579 | +static void gfxhub_v2_1_save_regs(struct amdgpu_device *adev) | |
| 580 | +{ | |
| 581 | + int i; | |
| 582 | + adev->gmc.VM_L2_CNTL = RREG32_SOC15(GC, 0, mmGCVM_L2_CNTL); | |
| 583 | + adev->gmc.VM_L2_CNTL2 = RREG32_SOC15(GC, 0, mmGCVM_L2_CNTL2); | |
| 584 | + adev->gmc.VM_DUMMY_PAGE_FAULT_CNTL = RREG32_SOC15(GC, 0, mmGCVM_DUMMY_PAGE_FAULT_CNTL); | |
| 585 | + adev->gmc.VM_DUMMY_PAGE_FAULT_ADDR_LO32 = RREG32_SOC15(GC, 0, mmGCVM_DUMMY_PAGE_FAULT_ADDR_LO32); | |
| 586 | + adev->gmc.VM_DUMMY_PAGE_FAULT_ADDR_HI32 = RREG32_SOC15(GC, 0, mmGCVM_DUMMY_PAGE_FAULT_ADDR_HI32); | |
| 587 | + adev->gmc.VM_L2_PROTECTION_FAULT_CNTL = RREG32_SOC15(GC, 0, mmGCVM_L2_PROTECTION_FAULT_CNTL); | |
| 588 | + adev->gmc.VM_L2_PROTECTION_FAULT_CNTL2 = RREG32_SOC15(GC, 0, mmGCVM_L2_PROTECTION_FAULT_CNTL2); | |
| 589 | + adev->gmc.VM_L2_PROTECTION_FAULT_MM_CNTL3 = RREG32_SOC15(GC, 0, mmGCVM_L2_PROTECTION_FAULT_MM_CNTL3); | |
| 590 | + adev->gmc.VM_L2_PROTECTION_FAULT_MM_CNTL4 = RREG32_SOC15(GC, 0, mmGCVM_L2_PROTECTION_FAULT_MM_CNTL4); | |
| 591 | + adev->gmc.VM_L2_PROTECTION_FAULT_ADDR_LO32 = RREG32_SOC15(GC, 0, mmGCVM_L2_PROTECTION_FAULT_ADDR_LO32); | |
| 592 | + adev->gmc.VM_L2_PROTECTION_FAULT_ADDR_HI32 = RREG32_SOC15(GC, 0, mmGCVM_L2_PROTECTION_FAULT_ADDR_HI32); | |
| 593 | + adev->gmc.VM_DEBUG = RREG32_SOC15(GC, 0, mmGCVM_DEBUG); | |
| 594 | + adev->gmc.VM_L2_MM_GROUP_RT_CLASSES = RREG32_SOC15(GC, 0, mmGCVM_L2_MM_GROUP_RT_CLASSES); | |
| 595 | + adev->gmc.VM_L2_BANK_SELECT_RESERVED_CID = RREG32_SOC15(GC, 0, mmGCVM_L2_BANK_SELECT_RESERVED_CID); | |
| 596 | + adev->gmc.VM_L2_BANK_SELECT_RESERVED_CID2 = RREG32_SOC15(GC, 0, mmGCVM_L2_BANK_SELECT_RESERVED_CID2); | |
| 597 | + adev->gmc.VM_L2_CACHE_PARITY_CNTL = RREG32_SOC15(GC, 0, mmGCVM_L2_CACHE_PARITY_CNTL); | |
| 598 | + adev->gmc.VM_L2_IH_LOG_CNTL = RREG32_SOC15(GC, 0, mmGCVM_L2_IH_LOG_CNTL); | |
| 599 | + | |
| 600 | + for (i = 0; i <= 15; i++) { | |
| 601 | + adev->gmc.VM_CONTEXT_CNTL[i] = RREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT0_CNTL, i); | |
| 602 | + adev->gmc.VM_CONTEXT_PAGE_TABLE_BASE_ADDR_LO32[i] = RREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32, i * 2); | |
| 603 | + adev->gmc.VM_CONTEXT_PAGE_TABLE_BASE_ADDR_HI32[i] = RREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32, i * 2); | |
| 604 | + adev->gmc.VM_CONTEXT_PAGE_TABLE_START_ADDR_LO32[i] = RREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32, i * 2); | |
| 605 | + adev->gmc.VM_CONTEXT_PAGE_TABLE_START_ADDR_HI32[i] = RREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32, i * 2); | |
| 606 | + adev->gmc.VM_CONTEXT_PAGE_TABLE_END_ADDR_LO32[i] = RREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32, i * 2); | |
| 607 | + adev->gmc.VM_CONTEXT_PAGE_TABLE_END_ADDR_HI32[i] = RREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32, i * 2); | |
| 608 | + } | |
| 609 | + | |
| 610 | + adev->gmc.MC_VM_MX_L1_TLB_CNTL = RREG32_SOC15(GC, 0, mmGCMC_VM_MX_L1_TLB_CNTL); | |
| 611 | +} | |
| 612 | + | |
| 613 | +static void gfxhub_v2_1_restore_regs(struct amdgpu_device *adev) | |
| 614 | +{ | |
| 615 | + int i; | |
| 616 | + WREG32_SOC15(GC, 0, mmGCVM_L2_CNTL, adev->gmc.VM_L2_CNTL); | |
| 617 | + WREG32_SOC15(GC, 0, mmGCVM_L2_CNTL2, adev->gmc.VM_L2_CNTL2); | |
| 618 | + WREG32_SOC15(GC, 0, mmGCVM_DUMMY_PAGE_FAULT_CNTL, adev->gmc.VM_DUMMY_PAGE_FAULT_CNTL); | |
| 619 | + WREG32_SOC15(GC, 0, mmGCVM_DUMMY_PAGE_FAULT_ADDR_LO32, adev->gmc.VM_DUMMY_PAGE_FAULT_ADDR_LO32); | |
| 620 | + WREG32_SOC15(GC, 0, mmGCVM_DUMMY_PAGE_FAULT_ADDR_HI32, adev->gmc.VM_DUMMY_PAGE_FAULT_ADDR_HI32); | |
| 621 | + WREG32_SOC15(GC, 0, mmGCVM_L2_PROTECTION_FAULT_CNTL, adev->gmc.VM_L2_PROTECTION_FAULT_CNTL); | |
| 622 | + WREG32_SOC15(GC, 0, mmGCVM_L2_PROTECTION_FAULT_CNTL2, adev->gmc.VM_L2_PROTECTION_FAULT_CNTL2); | |
| 623 | + WREG32_SOC15(GC, 0, mmGCVM_L2_PROTECTION_FAULT_MM_CNTL3, adev->gmc.VM_L2_PROTECTION_FAULT_MM_CNTL3); | |
| 624 | + WREG32_SOC15(GC, 0, mmGCVM_L2_PROTECTION_FAULT_MM_CNTL4, adev->gmc.VM_L2_PROTECTION_FAULT_MM_CNTL4); | |
| 625 | + WREG32_SOC15(GC, 0, mmGCVM_L2_PROTECTION_FAULT_ADDR_LO32, adev->gmc.VM_L2_PROTECTION_FAULT_ADDR_LO32); | |
| 626 | + WREG32_SOC15(GC, 0, mmGCVM_L2_PROTECTION_FAULT_ADDR_HI32, adev->gmc.VM_L2_PROTECTION_FAULT_ADDR_HI32); | |
| 627 | + WREG32_SOC15(GC, 0, mmGCVM_DEBUG, adev->gmc.VM_DEBUG); | |
| 628 | + WREG32_SOC15(GC, 0, mmGCVM_L2_MM_GROUP_RT_CLASSES, adev->gmc.VM_L2_MM_GROUP_RT_CLASSES); | |
| 629 | + WREG32_SOC15(GC, 0, mmGCVM_L2_BANK_SELECT_RESERVED_CID, adev->gmc.VM_L2_BANK_SELECT_RESERVED_CID); | |
| 630 | + WREG32_SOC15(GC, 0, mmGCVM_L2_BANK_SELECT_RESERVED_CID2, adev->gmc.VM_L2_BANK_SELECT_RESERVED_CID2); | |
| 631 | + WREG32_SOC15(GC, 0, mmGCVM_L2_CACHE_PARITY_CNTL, adev->gmc.VM_L2_CACHE_PARITY_CNTL); | |
| 632 | + WREG32_SOC15(GC, 0, mmGCVM_L2_IH_LOG_CNTL, adev->gmc.VM_L2_IH_LOG_CNTL); | |
| 633 | + | |
| 634 | + for (i = 0; i <= 15; i++) { | |
| 635 | + WREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT0_CNTL, i, adev->gmc.VM_CONTEXT_CNTL[i]); | |
| 636 | + WREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32, i * 2, adev->gmc.VM_CONTEXT_PAGE_TABLE_BASE_ADDR_LO32[i]); | |
| 637 | + WREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32, i * 2, adev->gmc.VM_CONTEXT_PAGE_TABLE_BASE_ADDR_HI32[i]); | |
| 638 | + WREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32, i * 2, adev->gmc.VM_CONTEXT_PAGE_TABLE_START_ADDR_LO32[i]); | |
| 639 | + WREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32, i * 2, adev->gmc.VM_CONTEXT_PAGE_TABLE_START_ADDR_HI32[i]); | |
| 640 | + WREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32, i * 2, adev->gmc.VM_CONTEXT_PAGE_TABLE_END_ADDR_LO32[i]); | |
| 641 | + WREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32, i * 2, adev->gmc.VM_CONTEXT_PAGE_TABLE_END_ADDR_HI32[i]); | |
| 642 | + } | |
| 643 | + | |
| 644 | + WREG32_SOC15(GC, 0, mmGCMC_VM_FB_LOCATION_BASE, adev->gmc.vram_start >> 24); | |
| 645 | + WREG32_SOC15(GC, 0, mmGCMC_VM_FB_LOCATION_TOP, adev->gmc.vram_end >> 24); | |
| 646 | + WREG32_SOC15(GC, 0, mmGCMC_VM_MX_L1_TLB_CNTL, adev->gmc.MC_VM_MX_L1_TLB_CNTL); | |
| 647 | +} | |
| 648 | + | |
| 649 | +static void gfxhub_v2_1_halt(struct amdgpu_device *adev) | |
| 650 | +{ | |
| 651 | + struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB_0]; | |
| 652 | + int i; | |
| 653 | + uint32_t tmp; | |
| 654 | + int time = 1000; | |
| 655 | + | |
| 656 | + gfxhub_v2_1_set_fault_enable_default(adev, false); | |
| 657 | + | |
| 658 | + for (i = 0; i <= 14; i++) { | |
| 659 | + WREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32, | |
| 660 | + i * hub->ctx_addr_distance, ~0); | |
| 661 | + WREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32, | |
| 662 | + i * hub->ctx_addr_distance, ~0); | |
| 663 | + WREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32, | |
| 664 | + i * hub->ctx_addr_distance, | |
| 665 | + 0); | |
| 666 | + WREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32, | |
| 667 | + i * hub->ctx_addr_distance, | |
| 668 | + 0); | |
| 669 | + } | |
| 670 | + tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS2); | |
| 671 | + while ((tmp & (GRBM_STATUS2__EA_BUSY_MASK | | |
| 672 | + GRBM_STATUS2__EA_LINK_BUSY_MASK)) != 0 && | |
| 673 | + time) { | |
| 674 | + udelay(100); | |
| 675 | + time--; | |
| 676 | + tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS2); | |
| 677 | + } | |
| 678 | + | |
| 679 | + if (!time) { | |
| 680 | + DRM_WARN("failed to wait for GRBM(EA) idle\n"); | |
| 681 | + } | |
| 682 | +} | |
| 683 | + | |
| 579 | 684 | const struct amdgpu_gfxhub_funcs gfxhub_v2_1_funcs = { |
| 580 | 685 | .get_fb_location = gfxhub_v2_1_get_fb_location, |
| 581 | 686 | .get_mc_fb_offset = gfxhub_v2_1_get_mc_fb_offset, |
| @@ -586,4 +691,7 @@ const struct amdgpu_gfxhub_funcs gfxhub_v2_1_funcs = { · 4 unmodified lines | ||
| 586 | 691 | .init = gfxhub_v2_1_init, |
| 587 | 692 | .get_xgmi_info = gfxhub_v2_1_get_xgmi_info, |
| 588 | 693 | .utcl2_harvest = gfxhub_v2_1_utcl2_harvest, |
| 694 | + .mode2_save_regs = gfxhub_v2_1_save_regs, | |
| 695 | + .mode2_restore_regs = gfxhub_v2_1_restore_regs, | |
| 696 | + .halt = gfxhub_v2_1_halt, | |
| 589 | 697 | }; |
| @@ -0,0 +1,511 @@ | ||
| 1 | +/* | |
| 2 | + * Copyright 2022 Advanced Micro Devices, Inc. | |
| 3 | + * | |
| 4 | + * Permission is hereby granted, free of charge, to any person obtaining a | |
| 5 | + * copy of this software and associated documentation files (the "Software"), | |
| 6 | + * to deal in the Software without restriction, including without limitation | |
| 7 | + * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
| 8 | + * and/or sell copies of the Software, and to permit persons to whom the | |
| 9 | + * Software is furnished to do so, subject to the following conditions: | |
| 10 | + * | |
| 11 | + * The above copyright notice and this permission notice shall be included in | |
| 12 | + * all copies or substantial portions of the Software. | |
| 13 | + * | |
| 14 | + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
| 15 | + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
| 16 | + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
| 17 | + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
| 18 | + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
| 19 | + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
| 20 | + * OTHER DEALINGS IN THE SOFTWARE. | |
| 21 | + * | |
| 22 | + */ | |
| 23 | + | |
| 24 | +#include "amdgpu.h" | |
| 25 | +#include "gfxhub_v3_0_3.h" | |
| 26 | + | |
| 27 | +#include "gc/gc_11_0_3_offset.h" | |
| 28 | +#include "gc/gc_11_0_3_sh_mask.h" | |
| 29 | +#include "navi10_enum.h" | |
| 30 | +#include "soc15_common.h" | |
| 31 | + | |
| 32 | +#define regGCVM_L2_CNTL3_DEFAULT 0x80100007 | |
| 33 | +#define regGCVM_L2_CNTL4_DEFAULT 0x000000c1 | |
| 34 | +#define regGCVM_L2_CNTL5_DEFAULT 0x00003fe0 | |
| 35 | + | |
| 36 | +static const char *gfxhub_client_ids[] = { | |
| 37 | + "CB/DB", | |
| 38 | + "Reserved", | |
| 39 | + "GE1", | |
| 40 | + "GE2", | |
| 41 | + "CPF", | |
| 42 | + "CPC", | |
| 43 | + "CPG", | |
| 44 | + "RLC", | |
| 45 | + "TCP", | |
| 46 | + "SQC (inst)", | |
| 47 | + "SQC (data)", | |
| 48 | + "SQG", | |
| 49 | + "Reserved", | |
| 50 | + "SDMA0", | |
| 51 | + "SDMA1", | |
| 52 | + "GCR", | |
| 53 | + "SDMA2", | |
| 54 | + "SDMA3", | |
| 55 | +}; | |
| 56 | + | |
| 57 | +static uint32_t gfxhub_v3_0_3_get_invalidate_req(unsigned int vmid, | |
| 58 | + uint32_t flush_type) | |
| 59 | +{ | |
| 60 | + u32 req = 0; | |
| 61 | + | |
| 62 | + /* invalidate using legacy mode on vmid*/ | |
| 63 | + req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, | |
| 64 | + PER_VMID_INVALIDATE_REQ, 1 << vmid); | |
| 65 | + req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, FLUSH_TYPE, flush_type); | |
| 66 | + req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PTES, 1); | |
| 67 | + req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE0, 1); | |
| 68 | + req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE1, 1); | |
| 69 | + req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE2, 1); | |
| 70 | + req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, INVALIDATE_L1_PTES, 1); | |
| 71 | + req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, | |
| 72 | + CLEAR_PROTECTION_FAULT_STATUS_ADDR, 0); | |
| 73 | + | |
| 74 | + return req; | |
| 75 | +} | |
| 76 | + | |
| 77 | +static void | |
| 78 | +gfxhub_v3_0_3_print_l2_protection_fault_status(struct amdgpu_device *adev, | |
| 79 | + uint32_t status) | |
| 80 | +{ | |
| 81 | + u32 cid = REG_GET_FIELD(status, | |
| 82 | + GCVM_L2_PROTECTION_FAULT_STATUS, CID); | |
| 83 | + | |
| 84 | + dev_err(adev->dev, | |
| 85 | + "GCVM_L2_PROTECTION_FAULT_STATUS:0x%08X\n", | |
| 86 | + status); | |
| 87 | + dev_err(adev->dev, "\t Faulty UTCL2 client ID: %s (0x%x)\n", | |
| 88 | + cid >= ARRAY_SIZE(gfxhub_client_ids) ? "unknown" : gfxhub_client_ids[cid], | |
| 89 | + cid); | |
| 90 | + dev_err(adev->dev, "\t MORE_FAULTS: 0x%lx\n", | |
| 91 | + REG_GET_FIELD(status, | |
| 92 | + GCVM_L2_PROTECTION_FAULT_STATUS, MORE_FAULTS)); | |
| 93 | + dev_err(adev->dev, "\t WALKER_ERROR: 0x%lx\n", | |
| 94 | + REG_GET_FIELD(status, | |
| 95 | + GCVM_L2_PROTECTION_FAULT_STATUS, WALKER_ERROR)); | |
| 96 | + dev_err(adev->dev, "\t PERMISSION_FAULTS: 0x%lx\n", | |
| 97 | + REG_GET_FIELD(status, | |
| 98 | + GCVM_L2_PROTECTION_FAULT_STATUS, PERMISSION_FAULTS)); | |
| 99 | + dev_err(adev->dev, "\t MAPPING_ERROR: 0x%lx\n", | |
| 100 | + REG_GET_FIELD(status, | |
| 101 | + GCVM_L2_PROTECTION_FAULT_STATUS, MAPPING_ERROR)); | |
| 102 | + dev_err(adev->dev, "\t RW: 0x%lx\n", | |
| 103 | + REG_GET_FIELD(status, | |
| 104 | + GCVM_L2_PROTECTION_FAULT_STATUS, RW)); | |
| 105 | +} | |
| 106 | + | |
| 107 | +static u64 gfxhub_v3_0_3_get_fb_location(struct amdgpu_device *adev) | |
| 108 | +{ | |
| 109 | + u64 base = RREG32_SOC15(GC, 0, regGCMC_VM_FB_LOCATION_BASE); | |
| 110 | + | |
| 111 | + base &= GCMC_VM_FB_LOCATION_BASE__FB_BASE_MASK; | |
| 112 | + base <<= 24; | |
| 113 | + | |
| 114 | + return base; | |
| 115 | +} | |
| 116 | + | |
| 117 | +static u64 gfxhub_v3_0_3_get_mc_fb_offset(struct amdgpu_device *adev) | |
| 118 | +{ | |
| 119 | + return (u64)RREG32_SOC15(GC, 0, regGCMC_VM_FB_OFFSET) << 24; | |
| 120 | +} | |
| 121 | + | |
| 122 | +static void gfxhub_v3_0_3_setup_vm_pt_regs(struct amdgpu_device *adev, uint32_t vmid, | |
| 123 | + uint64_t page_table_base) | |
| 124 | +{ | |
| 125 | + struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB_0]; | |
| 126 | + | |
| 127 | + WREG32_SOC15_OFFSET(GC, 0, regGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32, | |
| 128 | + hub->ctx_addr_distance * vmid, | |
| 129 | + lower_32_bits(page_table_base)); | |
| 130 | + | |
| 131 | + WREG32_SOC15_OFFSET(GC, 0, regGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32, | |
| 132 | + hub->ctx_addr_distance * vmid, | |
| 133 | + upper_32_bits(page_table_base)); | |
| 134 | +} | |
| 135 | + | |
| 136 | +static void gfxhub_v3_0_3_init_gart_aperture_regs(struct amdgpu_device *adev) | |
| 137 | +{ | |
| 138 | + uint64_t pt_base = amdgpu_gmc_pd_addr(adev->gart.bo); | |
| 139 | + | |
| 140 | + gfxhub_v3_0_3_setup_vm_pt_regs(adev, 0, pt_base); | |
| 141 | + | |
| 142 | + WREG32_SOC15(GC, 0, regGCVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32, | |
| 143 | + (u32)(adev->gmc.gart_start >> 12)); | |
| 144 | + WREG32_SOC15(GC, 0, regGCVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32, | |
| 145 | + (u32)(adev->gmc.gart_start >> 44)); | |
| 146 | + | |
| 147 | + WREG32_SOC15(GC, 0, regGCVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32, | |
| 148 | + (u32)(adev->gmc.gart_end >> 12)); | |
| 149 | + WREG32_SOC15(GC, 0, regGCVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32, | |
| 150 | + (u32)(adev->gmc.gart_end >> 44)); | |
| 151 | +} | |
| 152 | + | |
| 153 | +static void gfxhub_v3_0_3_init_system_aperture_regs(struct amdgpu_device *adev) | |
| 154 | +{ | |
| 155 | + uint64_t value; | |
| 156 | + | |
| 157 | + /* Disable AGP. */ | |
| 158 | + WREG32_SOC15(GC, 0, regGCMC_VM_AGP_BASE, 0); | |
| 159 | + WREG32_SOC15(GC, 0, regGCMC_VM_AGP_TOP, 0); | |
| 160 | + WREG32_SOC15(GC, 0, regGCMC_VM_AGP_BOT, 0x00FFFFFF); | |
| 161 | + | |
| 162 | + /* Program the system aperture low logical page number. */ | |
| 163 | + WREG32_SOC15(GC, 0, regGCMC_VM_SYSTEM_APERTURE_LOW_ADDR, | |
| 164 | + adev->gmc.vram_start >> 18); | |
| 165 | + WREG32_SOC15(GC, 0, regGCMC_VM_SYSTEM_APERTURE_HIGH_ADDR, | |
| 166 | + adev->gmc.vram_end >> 18); | |
| 167 | + | |
| 168 | + /* Set default page address. */ | |
| 169 | + value = adev->vram_scratch.gpu_addr - adev->gmc.vram_start | |
| 170 | + + adev->vm_manager.vram_base_offset; | |
| 171 | + WREG32_SOC15(GC, 0, regGCMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB, | |
| 172 | + (u32)(value >> 12)); | |
| 173 | + WREG32_SOC15(GC, 0, regGCMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB, | |
| 174 | + (u32)(value >> 44)); | |
| 175 | + | |
| 176 | + /* Program "protection fault". */ | |
| 177 | + WREG32_SOC15(GC, 0, regGCVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32, | |
| 178 | + (u32)(adev->dummy_page_addr >> 12)); | |
| 179 | + WREG32_SOC15(GC, 0, regGCVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32, | |
| 180 | + (u32)((u64)adev->dummy_page_addr >> 44)); | |
| 181 | + | |
| 182 | + WREG32_FIELD15_PREREG(GC, 0, GCVM_L2_PROTECTION_FAULT_CNTL2, | |
| 183 | + ACTIVE_PAGE_MIGRATION_PTE_READ_RETRY, 1); | |
| 184 | +} | |
| 185 | + | |
| 186 | + | |
| 187 | +static void gfxhub_v3_0_3_init_tlb_regs(struct amdgpu_device *adev) | |
| 188 | +{ | |
| 189 | + uint32_t tmp; | |
| 190 | + | |
| 191 | + /* Setup TLB control */ | |
| 192 | + tmp = RREG32_SOC15(GC, 0, regGCMC_VM_MX_L1_TLB_CNTL); | |
| 193 | + | |
| 194 | + tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1); | |
| 195 | + tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3); | |
| 196 | + tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, | |
| 197 | + ENABLE_ADVANCED_DRIVER_MODEL, 1); | |
| 198 | + tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, | |
| 199 | + SYSTEM_APERTURE_UNMAPPED_ACCESS, 0); | |
| 200 | + tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, ECO_BITS, 0); | |
| 201 | + tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, | |
| 202 | + MTYPE, MTYPE_UC); /* UC, uncached */ | |
| 203 | + | |
| 204 | + WREG32_SOC15(GC, 0, regGCMC_VM_MX_L1_TLB_CNTL, tmp); | |
| 205 | +} | |
| 206 | + | |
| 207 | +static void gfxhub_v3_0_3_init_cache_regs(struct amdgpu_device *adev) | |
| 208 | +{ | |
| 209 | + uint32_t tmp; | |
| 210 | + | |
| 211 | + /* These registers are not accessible to VF-SRIOV. | |
| 212 | + * The PF will program them instead. | |
| 213 | + */ | |
| 214 | + if (amdgpu_sriov_vf(adev)) | |
| 215 | + return; | |
| 216 | + | |
| 217 | + /* Setup L2 cache */ | |
| 218 | + tmp = RREG32_SOC15(GC, 0, regGCVM_L2_CNTL); | |
| 219 | + tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, ENABLE_L2_CACHE, 1); | |
| 220 | + tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING, 0); | |
| 221 | + tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, | |
| 222 | + ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY, 1); | |
| 223 | + /* XXX for emulation, Refer to closed source code.*/ | |
| 224 | + tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, | |
| 225 | + L2_PDE0_CACHE_TAG_GENERATION_MODE, 0); | |
| 226 | + tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, PDE_FAULT_CLASSIFICATION, 0); | |
| 227 | + tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, CONTEXT1_IDENTITY_ACCESS_MODE, 1); | |
| 228 | + tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, IDENTITY_MODE_FRAGMENT_SIZE, 0); | |
| 229 | + WREG32_SOC15(GC, 0, regGCVM_L2_CNTL, tmp); | |
| 230 | + | |
| 231 | + tmp = RREG32_SOC15(GC, 0, regGCVM_L2_CNTL2); | |
| 232 | + tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1); | |
| 233 | + tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL2, INVALIDATE_L2_CACHE, 1); | |
| 234 | + WREG32_SOC15(GC, 0, regGCVM_L2_CNTL2, tmp); | |
| 235 | + | |
| 236 | + tmp = regGCVM_L2_CNTL3_DEFAULT; | |
| 237 | + if (adev->gmc.translate_further) { | |
| 238 | + tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL3, BANK_SELECT, 12); | |
| 239 | + tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL3, | |
| 240 | + L2_CACHE_BIGK_FRAGMENT_SIZE, 9); | |
| 241 | + } else { | |
| 242 | + tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL3, BANK_SELECT, 9); | |
| 243 | + tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL3, | |
| 244 | + L2_CACHE_BIGK_FRAGMENT_SIZE, 6); | |
| 245 | + } | |
| 246 | + WREG32_SOC15(GC, 0, regGCVM_L2_CNTL3, tmp); | |
| 247 | + | |
| 248 | + tmp = regGCVM_L2_CNTL4_DEFAULT; | |
| 249 | + tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL4, VMC_TAP_PDE_REQUEST_PHYSICAL, 0); | |
| 250 | + tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL4, VMC_TAP_PTE_REQUEST_PHYSICAL, 0); | |
| 251 | + WREG32_SOC15(GC, 0, regGCVM_L2_CNTL4, tmp); | |
| 252 | + | |
| 253 | + tmp = regGCVM_L2_CNTL5_DEFAULT; | |
| 254 | + tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL5, L2_CACHE_SMALLK_FRAGMENT_SIZE, 0); | |
| 255 | + WREG32_SOC15(GC, 0, regGCVM_L2_CNTL5, tmp); | |
| 256 | +} | |
| 257 | + | |
| 258 | +static void gfxhub_v3_0_3_enable_system_domain(struct amdgpu_device *adev) | |
| 259 | +{ | |
| 260 | + uint32_t tmp; | |
| 261 | + | |
| 262 | + tmp = RREG32_SOC15(GC, 0, regGCVM_CONTEXT0_CNTL); | |
| 263 | + tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1); | |
| 264 | + tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, 0); | |
| 265 | + tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT0_CNTL, | |
| 266 | + RETRY_PERMISSION_OR_INVALID_PAGE_FAULT, 0); | |
| 267 | + WREG32_SOC15(GC, 0, regGCVM_CONTEXT0_CNTL, tmp); | |
| 268 | +} | |
| 269 | + | |
| 270 | +static void gfxhub_v3_0_3_disable_identity_aperture(struct amdgpu_device *adev) | |
| 271 | +{ | |
| 272 | + /* These registers are not accessible to VF-SRIOV. | |
| 273 | + * The PF will program them instead. | |
| 274 | + */ | |
| 275 | + if (amdgpu_sriov_vf(adev)) | |
| 276 | + return; | |
| 277 | + | |
| 278 | + WREG32_SOC15(GC, 0, regGCVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32, | |
| 279 | + 0xFFFFFFFF); | |
| 280 | + WREG32_SOC15(GC, 0, regGCVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32, | |
| 281 | + 0x0000000F); | |
| 282 | + | |
| 283 | + WREG32_SOC15(GC, 0, regGCVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32, | |
| 284 | + 0); | |
| 285 | + WREG32_SOC15(GC, 0, regGCVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32, | |
| 286 | + 0); | |
| 287 | + | |
| 288 | + WREG32_SOC15(GC, 0, regGCVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32, 0); | |
| 289 | + WREG32_SOC15(GC, 0, regGCVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32, 0); | |
| 290 | + | |
| 291 | +} | |
| 292 | + | |
| 293 | +static void gfxhub_v3_0_3_setup_vmid_config(struct amdgpu_device *adev) | |
| 294 | +{ | |
| 295 | + struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB_0]; | |
| 296 | + int i; | |
| 297 | + uint32_t tmp; | |
| 298 | + | |
| 299 | + for (i = 0; i <= 14; i++) { | |
| 300 | + tmp = RREG32_SOC15_OFFSET(GC, 0, regGCVM_CONTEXT1_CNTL, i); | |
| 301 | + tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1); | |
| 302 | + tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH, | |
| 303 | + adev->vm_manager.num_level); | |
| 304 | + tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, | |
| 305 | + RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1); | |
| 306 | + tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, | |
| 307 | + DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1); | |
| 308 | + tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, | |
| 309 | + PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, 1); | |
| 310 | + tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, | |
| 311 | + VALID_PROTECTION_FAULT_ENABLE_DEFAULT, 1); | |
| 312 | + tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, | |
| 313 | + READ_PROTECTION_FAULT_ENABLE_DEFAULT, 1); | |
| 314 | + tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, | |
| 315 | + WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, 1); | |
| 316 | + tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, | |
| 317 | + EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, 1); | |
| 318 | + tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, | |
| 319 | + PAGE_TABLE_BLOCK_SIZE, | |
| 320 | + adev->vm_manager.block_size - 9); | |
| 321 | + /* Send no-retry XNACK on fault to suppress VM fault storm. */ | |
| 322 | + tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, | |
| 323 | + RETRY_PERMISSION_OR_INVALID_PAGE_FAULT, | |
| 324 | + !amdgpu_noretry); | |
| 325 | + WREG32_SOC15_OFFSET(GC, 0, regGCVM_CONTEXT1_CNTL, | |
| 326 | + i * hub->ctx_distance, tmp); | |
| 327 | + WREG32_SOC15_OFFSET(GC, 0, regGCVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32, | |
| 328 | + i * hub->ctx_addr_distance, 0); | |
| 329 | + WREG32_SOC15_OFFSET(GC, 0, regGCVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32, | |
| 330 | + i * hub->ctx_addr_distance, 0); | |
| 331 | + WREG32_SOC15_OFFSET(GC, 0, regGCVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32, | |
| 332 | + i * hub->ctx_addr_distance, | |
| 333 | + lower_32_bits(adev->vm_manager.max_pfn - 1)); | |
| 334 | + WREG32_SOC15_OFFSET(GC, 0, regGCVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32, | |
| 335 | + i * hub->ctx_addr_distance, | |
| 336 | + upper_32_bits(adev->vm_manager.max_pfn - 1)); | |
| 337 | + } | |
| 338 | + | |
| 339 | + hub->vm_cntx_cntl = tmp; | |
| 340 | +} | |
| 341 | + | |
| 342 | +static void gfxhub_v3_0_3_program_invalidation(struct amdgpu_device *adev) | |
| 343 | +{ | |
| 344 | + struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB_0]; | |
| 345 | + unsigned i; | |
| 346 | + | |
| 347 | + for (i = 0 ; i < 18; ++i) { | |
| 348 | + WREG32_SOC15_OFFSET(GC, 0, regGCVM_INVALIDATE_ENG0_ADDR_RANGE_LO32, | |
| 349 | + i * hub->eng_addr_distance, 0xffffffff); | |
| 350 | + WREG32_SOC15_OFFSET(GC, 0, regGCVM_INVALIDATE_ENG0_ADDR_RANGE_HI32, | |
| 351 | + i * hub->eng_addr_distance, 0x1f); | |
| 352 | + } | |
| 353 | +} | |
| 354 | + | |
| 355 | +static int gfxhub_v3_0_3_gart_enable(struct amdgpu_device *adev) | |
| 356 | +{ | |
| 357 | + if (amdgpu_sriov_vf(adev)) { | |
| 358 | + /* | |
| 359 | + * GCMC_VM_FB_LOCATION_BASE/TOP is NULL for VF, becuase they are | |
| 360 | + * VF copy registers so vbios post doesn't program them, for | |
| 361 | + * SRIOV driver need to program them | |
| 362 | + */ | |
| 363 | + WREG32_SOC15(GC, 0, regGCMC_VM_FB_LOCATION_BASE, | |
| 364 | + adev->gmc.vram_start >> 24); | |
| 365 | + WREG32_SOC15(GC, 0, regGCMC_VM_FB_LOCATION_TOP, | |
| 366 | + adev->gmc.vram_end >> 24); | |
| 367 | + } | |
| 368 | + | |
| 369 | + /* GART Enable. */ | |
| 370 | + gfxhub_v3_0_3_init_gart_aperture_regs(adev); | |
| 371 | + gfxhub_v3_0_3_init_system_aperture_regs(adev); | |
| 372 | + gfxhub_v3_0_3_init_tlb_regs(adev); | |
| 373 | + gfxhub_v3_0_3_init_cache_regs(adev); | |
| 374 | + | |
| 375 | + gfxhub_v3_0_3_enable_system_domain(adev); | |
| 376 | + gfxhub_v3_0_3_disable_identity_aperture(adev); | |
| 377 | + gfxhub_v3_0_3_setup_vmid_config(adev); | |
| 378 | + gfxhub_v3_0_3_program_invalidation(adev); | |
| 379 | + | |
| 380 | + return 0; | |
| 381 | +} | |
| 382 | + | |
| 383 | +static void gfxhub_v3_0_3_gart_disable(struct amdgpu_device *adev) | |
| 384 | +{ | |
| 385 | + struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB_0]; | |
| 386 | + u32 tmp; | |
| 387 | + u32 i; | |
| 388 | + | |
| 389 | + /* Disable all tables */ | |
| 390 | + for (i = 0; i < 16; i++) | |
| 391 | + WREG32_SOC15_OFFSET(GC, 0, regGCVM_CONTEXT0_CNTL, | |
| 392 | + i * hub->ctx_distance, 0); | |
| 393 | + | |
| 394 | + /* Setup TLB control */ | |
| 395 | + tmp = RREG32_SOC15(GC, 0, regGCMC_VM_MX_L1_TLB_CNTL); | |
| 396 | + tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0); | |
| 397 | + tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, | |
| 398 | + ENABLE_ADVANCED_DRIVER_MODEL, 0); | |
| 399 | + WREG32_SOC15(GC, 0, regGCMC_VM_MX_L1_TLB_CNTL, tmp); | |
| 400 | + | |
| 401 | + /* Setup L2 cache */ | |
| 402 | + WREG32_FIELD15_PREREG(GC, 0, GCVM_L2_CNTL, ENABLE_L2_CACHE, 0); | |
| 403 | + WREG32_SOC15(GC, 0, regGCVM_L2_CNTL3, 0); | |
| 404 | +} | |
| 405 | + | |
| 406 | +/** | |
| 407 | + * gfxhub_v3_0_3_set_fault_enable_default - update GART/VM fault handling | |
| 408 | + * | |
| 409 | + * @adev: amdgpu_device pointer | |
| 410 | + * @value: true redirects VM faults to the default page | |
| 411 | + */ | |
| 412 | +static void gfxhub_v3_0_3_set_fault_enable_default(struct amdgpu_device *adev, | |
| 413 | + bool value) | |
| 414 | +{ | |
| 415 | + u32 tmp; | |
| 416 | + | |
| 417 | + /* These registers are not accessible to VF-SRIOV. | |
| 418 | + * The PF will program them instead. | |
| 419 | + */ | |
| 420 | + if (amdgpu_sriov_vf(adev)) | |
| 421 | + return; | |
| 422 | + | |
| 423 | + tmp = RREG32_SOC15(GC, 0, regGCVM_L2_PROTECTION_FAULT_CNTL); | |
| 424 | + tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL, | |
| 425 | + RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, value); | |
| 426 | + tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL, | |
| 427 | + PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, value); | |
| 428 | + tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL, | |
| 429 | + PDE1_PROTECTION_FAULT_ENABLE_DEFAULT, value); | |
| 430 | + tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL, | |
| 431 | + PDE2_PROTECTION_FAULT_ENABLE_DEFAULT, value); | |
| 432 | + tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL, | |
| 433 | + TRANSLATE_FURTHER_PROTECTION_FAULT_ENABLE_DEFAULT, | |
| 434 | + value); | |
| 435 | + tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL, | |
| 436 | + NACK_PROTECTION_FAULT_ENABLE_DEFAULT, value); | |
| 437 | + tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL, | |
| 438 | + DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, value); | |
| 439 | + tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL, | |
| 440 | + VALID_PROTECTION_FAULT_ENABLE_DEFAULT, value); | |
| 441 | + tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL, | |
| 442 | + READ_PROTECTION_FAULT_ENABLE_DEFAULT, value); | |
| 443 | + tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL, | |
| 444 | + WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, value); | |
| 445 | + tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL, | |
| 446 | + EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, value); | |
| 447 | + if (!value) { | |
| 448 | + tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL, | |
| 449 | + CRASH_ON_NO_RETRY_FAULT, 1); | |
| 450 | + tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL, | |
| 451 | + CRASH_ON_RETRY_FAULT, 1); | |
| 452 | + } | |
| 453 | + WREG32_SOC15(GC, 0, regGCVM_L2_PROTECTION_FAULT_CNTL, tmp); | |
| 454 | +} | |
| 455 | + | |
| 456 | +static const struct amdgpu_vmhub_funcs gfxhub_v3_0_3_vmhub_funcs = { | |
| 457 | + .print_l2_protection_fault_status = gfxhub_v3_0_3_print_l2_protection_fault_status, | |
| 458 | + .get_invalidate_req = gfxhub_v3_0_3_get_invalidate_req, | |
| 459 | +}; | |
| 460 | + | |
| 461 | +static void gfxhub_v3_0_3_init(struct amdgpu_device *adev) | |
| 462 | +{ | |
| 463 | + struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB_0]; | |
| 464 | + | |
| 465 | + hub->ctx0_ptb_addr_lo32 = | |
| 466 | + SOC15_REG_OFFSET(GC, 0, | |
| 467 | + regGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32); | |
| 468 | + hub->ctx0_ptb_addr_hi32 = | |
| 469 | + SOC15_REG_OFFSET(GC, 0, | |
| 470 | + regGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32); | |
| 471 | + hub->vm_inv_eng0_sem = | |
| 472 | + SOC15_REG_OFFSET(GC, 0, regGCVM_INVALIDATE_ENG0_SEM); | |
| 473 | + hub->vm_inv_eng0_req = | |
| 474 | + SOC15_REG_OFFSET(GC, 0, regGCVM_INVALIDATE_ENG0_REQ); | |
| 475 | + hub->vm_inv_eng0_ack = | |
| 476 | + SOC15_REG_OFFSET(GC, 0, regGCVM_INVALIDATE_ENG0_ACK); | |
| 477 | + hub->vm_context0_cntl = | |
| 478 | + SOC15_REG_OFFSET(GC, 0, regGCVM_CONTEXT0_CNTL); | |
| 479 | + hub->vm_l2_pro_fault_status = | |
| 480 | + SOC15_REG_OFFSET(GC, 0, regGCVM_L2_PROTECTION_FAULT_STATUS); | |
| 481 | + hub->vm_l2_pro_fault_cntl = | |
| 482 | + SOC15_REG_OFFSET(GC, 0, regGCVM_L2_PROTECTION_FAULT_CNTL); | |
| 483 | + | |
| 484 | + hub->ctx_distance = regGCVM_CONTEXT1_CNTL - regGCVM_CONTEXT0_CNTL; | |
| 485 | + hub->ctx_addr_distance = regGCVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32 - | |
| 486 | + regGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32; | |
| 487 | + hub->eng_distance = regGCVM_INVALIDATE_ENG1_REQ - | |
| 488 | + regGCVM_INVALIDATE_ENG0_REQ; | |
| 489 | + hub->eng_addr_distance = regGCVM_INVALIDATE_ENG1_ADDR_RANGE_LO32 - | |
| 490 | + regGCVM_INVALIDATE_ENG0_ADDR_RANGE_LO32; | |
| 491 | + | |
| 492 | + hub->vm_cntx_cntl_vm_fault = GCVM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | | |
| 493 | + GCVM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | | |
| 494 | + GCVM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | | |
| 495 | + GCVM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | | |
| 496 | + GCVM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | | |
| 497 | + GCVM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | | |
| 498 | + GCVM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK; | |
| 499 | + | |
| 500 | + hub->vmhub_funcs = &gfxhub_v3_0_3_vmhub_funcs; | |
| 501 | +} | |
| 502 | + | |
| 503 | +const struct amdgpu_gfxhub_funcs gfxhub_v3_0_3_funcs = { | |
| 504 | + .get_fb_location = gfxhub_v3_0_3_get_fb_location, | |
| 505 | + .get_mc_fb_offset = gfxhub_v3_0_3_get_mc_fb_offset, | |
| 506 | + .setup_vm_pt_regs = gfxhub_v3_0_3_setup_vm_pt_regs, | |
| 507 | + .gart_enable = gfxhub_v3_0_3_gart_enable, | |
| 508 | + .gart_disable = gfxhub_v3_0_3_gart_disable, | |
| 509 | + .set_fault_enable_default = gfxhub_v3_0_3_set_fault_enable_default, | |
| 510 | + .init = gfxhub_v3_0_3_init, | |
| 511 | +}; | |
| @@ -0,0 +1,29 @@ | ||
| 1 | +/* | |
| 2 | + * Copyright 2022 Advanced Micro Devices, Inc. | |
| 3 | + * | |
| 4 | + * Permission is hereby granted, free of charge, to any person obtaining a | |
| 5 | + * copy of this software and associated documentation files (the "Software"), | |
| 6 | + * to deal in the Software without restriction, including without limitation | |
| 7 | + * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
| 8 | + * and/or sell copies of the Software, and to permit persons to whom the | |
| 9 | + * Software is furnished to do so, subject to the following conditions: | |
| 10 | + * | |
| 11 | + * The above copyright notice and this permission notice shall be included in | |
| 12 | + * all copies or substantial portions of the Software. | |
| 13 | + * | |
| 14 | + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
| 15 | + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
| 16 | + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
| 17 | + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
| 18 | + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
| 19 | + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
| 20 | + * OTHER DEALINGS IN THE SOFTWARE. | |
| 21 | + * | |
| 22 | + */ | |
| 23 | + | |
| 24 | +#ifndef __GFXHUB_V3_0_3_H__ | |
| 25 | +#define __GFXHUB_V3_0_3_H__ | |
| 26 | + | |
| 27 | +extern const struct amdgpu_gfxhub_funcs gfxhub_v3_0_3_funcs; | |
| 28 | + | |
| 29 | +#endif | |
| @@ -39,6 +39,7 @@ · 38 unmodified lines | ||
| 39 | 39 | #include "soc15_common.h" |
| 40 | 40 | #include "nbio_v4_3.h" |
| 41 | 41 | #include "gfxhub_v3_0.h" |
| 42 | +#include "gfxhub_v3_0_3.h" | |
| 42 | 43 | #include "mmhub_v3_0.h" |
| 43 | 44 | #include "mmhub_v3_0_1.h" |
| 44 | 45 | #include "mmhub_v3_0_2.h" |
| @@ -233,7 +234,8 @@ static void gmc_v11_0_flush_vm_hub(struct amdgpu_device *adev, uint32_t vmid, · 188 unmodified lines | ||
| 233 | 234 | |
| 234 | 235 | /* Issue additional private vm invalidation to MMHUB */ |
| 235 | 236 | if ((vmhub != AMDGPU_GFXHUB_0) && |
| 236 | − (hub->vm_l2_bank_select_reserved_cid2)) { | |
| 237 | + (hub->vm_l2_bank_select_reserved_cid2) && | |
| 238 | + !amdgpu_sriov_vf(adev)) { | |
| 237 | 239 | inv_req = RREG32_NO_KIQ(hub->vm_l2_bank_select_reserved_cid2); |
| 238 | 240 | /* bit 25: RSERVED_CACHE_PRIVATE_INVALIDATION */ |
| 239 | 241 | inv_req |= (1 << 25); |
| @@ -590,7 +592,14 @@ static void gmc_v11_0_set_mmhub_funcs(struct amdgpu_device *adev) · 350 unmodified lines | ||
| 590 | 592 | |
| 591 | 593 | static void gmc_v11_0_set_gfxhub_funcs(struct amdgpu_device *adev) |
| 592 | 594 | { |
| 593 | − adev->gfxhub.funcs = &gfxhub_v3_0_funcs; | |
| 595 | + switch (adev->ip_versions[GC_HWIP][0]) { | |
| 596 | + case IP_VERSION(11, 0, 3): | |
| 597 | + adev->gfxhub.funcs = &gfxhub_v3_0_3_funcs; | |
| 598 | + break; | |
| 599 | + default: | |
| 600 | + adev->gfxhub.funcs = &gfxhub_v3_0_funcs; | |
| 601 | + break; | |
| 602 | + } | |
| 594 | 603 | } |
| 595 | 604 | |
| 596 | 605 | static int gmc_v11_0_early_init(void *handle) |
| @@ -640,7 +649,10 @@ static void gmc_v11_0_vram_gtt_location(struct amdgpu_device *adev, · 43 unmodified lines | ||
| 640 | 649 | amdgpu_gmc_gart_location(adev, mc); |
| 641 | 650 | |
| 642 | 651 | /* base offset of vram pages */ |
| 643 | − adev->vm_manager.vram_base_offset = adev->mmhub.funcs->get_mc_fb_offset(adev); | |
| 652 | + if (amdgpu_sriov_vf(adev)) | |
| 653 | + adev->vm_manager.vram_base_offset = 0; | |
| 654 | + else | |
| 655 | + adev->vm_manager.vram_base_offset = adev->mmhub.funcs->get_mc_fb_offset(adev); | |
| 644 | 656 | } |
| 645 | 657 | |
| 646 | 658 | /** |
| @@ -732,6 +744,7 @@ static int gmc_v11_0_sw_init(void *handle) · 85 unmodified lines | ||
| 732 | 744 | case IP_VERSION(11, 0, 0): |
| 733 | 745 | case IP_VERSION(11, 0, 1): |
| 734 | 746 | case IP_VERSION(11, 0, 2): |
| 747 | + case IP_VERSION(11, 0, 3): | |
| 735 | 748 | adev->num_vmhubs = 2; |
| 736 | 749 | /* |
| 737 | 750 | * To fulfill 4-level page support, |
| @@ -105,7 +105,13 @@ force_update_wptr_for_self_int(struct amdgpu_device *adev, · 104 unmodified lines | ||
| 105 | 105 | ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL_RING1, |
| 106 | 106 | RB_USED_INT_THRESHOLD, threshold); |
| 107 | 107 | |
| 108 | − WREG32_SOC15(OSSSYS, 0, regIH_RB_CNTL_RING1, ih_rb_cntl); | |
| 108 | + if (amdgpu_sriov_vf(adev) && amdgpu_sriov_reg_indirect_ih(adev)) { | |
| 109 | + if (psp_reg_program(&adev->psp, PSP_REG_IH_RB_CNTL_RING1, ih_rb_cntl)) | |
| 110 | + return; | |
| 111 | + } else { | |
| 112 | + WREG32_SOC15(OSSSYS, 0, regIH_RB_CNTL_RING1, ih_rb_cntl); | |
| 113 | + } | |
| 114 | + | |
| 109 | 115 | WREG32_SOC15(OSSSYS, 0, regIH_CNTL2, ih_cntl); |
| 110 | 116 | } |
| 111 | 117 | |
| @@ -132,7 +138,13 @@ static int ih_v6_0_toggle_ring_interrupts(struct amdgpu_device *adev, · 20 unmodified lines | ||
| 132 | 138 | /* enable_intr field is only valid in ring0 */ |
| 133 | 139 | if (ih == &adev->irq.ih) |
| 134 | 140 | tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, ENABLE_INTR, (enable ? 1 : 0)); |
| 135 | − WREG32(ih_regs->ih_rb_cntl, tmp); | |
| 141 | + | |
| 142 | + if (amdgpu_sriov_vf(adev) && amdgpu_sriov_reg_indirect_ih(adev)) { | |
| 143 | + if (psp_reg_program(&adev->psp, ih_regs->psp_reg_id, tmp)) | |
| 144 | + return -ETIMEDOUT; | |
| 145 | + } else { | |
| 146 | + WREG32(ih_regs->ih_rb_cntl, tmp); | |
| 147 | + } | |
| 136 | 148 | |
| 137 | 149 | if (enable) { |
| 138 | 150 | ih->enabled = true; |
| @@ -242,7 +254,15 @@ static int ih_v6_0_enable_ring(struct amdgpu_device *adev, · 103 unmodified lines | ||
| 242 | 254 | tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_ENABLE, 0); |
| 243 | 255 | tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, RB_FULL_DRAIN_ENABLE, 1); |
| 244 | 256 | } |
| 245 | − WREG32(ih_regs->ih_rb_cntl, tmp); | |
| 257 | + | |
| 258 | + if (amdgpu_sriov_vf(adev) && amdgpu_sriov_reg_indirect_ih(adev)) { | |
| 259 | + if (psp_reg_program(&adev->psp, ih_regs->psp_reg_id, tmp)) { | |
| 260 | + DRM_ERROR("PSP program IH_RB_CNTL failed!\n"); | |
| 261 | + return -ETIMEDOUT; | |
| 262 | + } | |
| 263 | + } else { | |
| 264 | + WREG32(ih_regs->ih_rb_cntl, tmp); | |
| 265 | + } | |
| 246 | 266 | |
| 247 | 267 | if (ih == &adev->irq.ih) { |
| 248 | 268 | /* set the ih ring 0 writeback address whether it's enabled or not */ |
| @@ -26,12 +26,15 @@ · 25 unmodified lines | ||
| 26 | 26 | #include "amdgpu_imu.h" |
| 27 | 27 | #include "amdgpu_dpm.h" |
| 28 | 28 | |
| 29 | +#include "imu_v11_0_3.h" | |
| 30 | + | |
| 29 | 31 | #include "gc/gc_11_0_0_offset.h" |
| 30 | 32 | #include "gc/gc_11_0_0_sh_mask.h" |
| 31 | 33 | |
| 32 | 34 | MODULE_FIRMWARE("amdgpu/gc_11_0_0_imu.bin"); |
| 33 | 35 | MODULE_FIRMWARE("amdgpu/gc_11_0_1_imu.bin"); |
| 34 | 36 | MODULE_FIRMWARE("amdgpu/gc_11_0_2_imu.bin"); |
| 37 | +MODULE_FIRMWARE("amdgpu/gc_11_0_3_imu.bin"); | |
| 35 | 38 | |
| 36 | 39 | static int imu_v11_0_init_microcode(struct amdgpu_device *adev) |
| 37 | 40 | { |
| @@ -360,6 +363,9 @@ static void imu_v11_0_program_rlc_ram(struct amdgpu_device *adev) · 322 unmodified lines | ||
| 360 | 363 | program_imu_rlc_ram(adev, imu_rlc_ram_golden_11_0_2, |
| 361 | 364 | (const u32)ARRAY_SIZE(imu_rlc_ram_golden_11_0_2)); |
| 362 | 365 | break; |
| 366 | + case IP_VERSION(11, 0, 3): | |
| 367 | + imu_v11_0_3_program_rlc_ram(adev); | |
| 368 | + break; | |
| 363 | 369 | default: |
| 364 | 370 | BUG(); |
| 365 | 371 | break; |
| @@ -0,0 +1,145 @@ | ||
| 1 | +/* | |
| 2 | + * Copyright 2022 Advanced Micro Devices, Inc. | |
| 3 | + * | |
| 4 | + * Permission is hereby granted, free of charge, to any person obtaining a | |
| 5 | + * copy of this software and associated documentation files (the "Software"), | |
| 6 | + * to deal in the Software without restriction, including without limitation | |
| 7 | + * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
| 8 | + * and/or sell copies of the Software, and to permit persons to whom the | |
| 9 | + * Software is furnished to do so, subject to the following conditions: | |
| 10 | + * | |
| 11 | + * The above copyright notice and this permission notice shall be included in | |
| 12 | + * all copies or substantial portions of the Software. | |
| 13 | + * | |
| 14 | + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
| 15 | + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
| 16 | + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
| 17 | + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
| 18 | + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
| 19 | + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
| 20 | + * OTHER DEALINGS IN THE SOFTWARE. | |
| 21 | + * | |
| 22 | + */ | |
| 23 | +#include "amdgpu.h" | |
| 24 | +#include "amdgpu_imu.h" | |
| 25 | +#include "imu_v11_0_3.h" | |
| 26 | + | |
| 27 | +#include "gc/gc_11_0_3_offset.h" | |
| 28 | +#include "gc/gc_11_0_3_sh_mask.h" | |
| 29 | + | |
| 30 | +static const struct imu_rlc_ram_golden imu_rlc_ram_golden_11_0_3[] = { | |
| 31 | + IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGUS_IO_RD_COMBINE_FLUSH, 0x00055555, 0xe0000000), | |
| 32 | + IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGUS_IO_WR_COMBINE_FLUSH, 0x00055555, 0xe0000000), | |
| 33 | + IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGUS_DRAM_COMBINE_FLUSH, 0x00555555, 0xe0000000), | |
| 34 | + IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGUS_MISC2, 0x00001ffe, 0xe0000000), | |
| 35 | + IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGUS_SDP_CREDITS, 0x003f3fff, 0xe0000000), | |
| 36 | + IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGUS_SDP_TAG_RESERVE1, 0x00000000, 0xe0000000), | |
| 37 | + IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGUS_SDP_VCC_RESERVE0, 0x00041000, 0xe0000000), | |
| 38 | + IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGUS_SDP_VCC_RESERVE1, 0x00000000, 0xe0000000), | |
| 39 | + IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGUS_SDP_VCD_RESERVE0, 0x00040000, 0xe0000000), | |
| 40 | + IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGUS_SDP_VCD_RESERVE1, 0x00000000, 0xe0000000), | |
| 41 | + IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGUS_MISC, 0x00000017, 0xe0000000), | |
| 42 | + IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGUS_SDP_ENABLE, 0x00000001, 0xe0000000), | |
| 43 | + IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCEA_SDP_CREDITS, 0x003f3fbf, 0xe0000000), | |
| 44 | + IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCEA_SDP_TAG_RESERVE0, 0x10200800, 0xe0000000), | |
| 45 | + IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCEA_SDP_TAG_RESERVE1, 0x00000088, 0xe0000000), | |
| 46 | + IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCEA_SDP_VCC_RESERVE0, 0x1d041040, 0xe0000000), | |
| 47 | + IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCEA_SDP_VCC_RESERVE1, 0x80000000, 0xe0000000), | |
| 48 | + IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCEA_SDP_IO_PRIORITY, 0x88888888, 0xe0000000), | |
| 49 | + IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCEA_MAM_CTRL, 0x0000d800, 0xe0000000), | |
| 50 | + IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCEA_SDP_ARB_FINAL, 0x000007ff, 0xe0000000), | |
| 51 | + IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCEA_DRAM_PAGE_BURST, 0x20080200, 0xe0000000), | |
| 52 | + IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCEA_SDP_ENABLE, 0x00000001, 0xe0000000), | |
| 53 | + IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCVM_L2_PROTECTION_FAULT_CNTL2, 0x00020000, 0xe0000000), | |
| 54 | + IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCMC_VM_APT_CNTL, 0x0000000c, 0xe0000000), | |
| 55 | + IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCMC_VM_CACHEABLE_DRAM_ADDRESS_END, 0x000fffff, 0xe0000000), | |
| 56 | + IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCEA_MISC, 0x0c48bff0, 0xe0000000), | |
| 57 | + IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regCC_GC_SA_UNIT_DISABLE, 0x00fffc01, 0xe0000000), | |
| 58 | + IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regCC_GC_PRIM_CONFIG, 0x000fffe1, 0xe0000000), | |
| 59 | + IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regCC_RB_BACKEND_DISABLE, 0xffffff01, 0xe0000000), | |
| 60 | + IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regCC_GC_SHADER_ARRAY_CONFIG, 0xfffe0001, 0x40000000), | |
| 61 | + IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regCC_GC_SHADER_ARRAY_CONFIG, 0xfffe0001, 0x42000000), | |
| 62 | + IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regCC_GC_SHADER_ARRAY_CONFIG, 0xffff0001, 0x44000000), | |
| 63 | + IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regCC_GC_SHADER_ARRAY_CONFIG, 0xffff0001, 0x46000000), | |
| 64 | + IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regCC_GC_SHADER_ARRAY_CONFIG, 0xffff0001, 0x48000000), | |
| 65 | + IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regCC_GC_SHADER_ARRAY_CONFIG, 0xffff0001, 0x4A000000), | |
| 66 | + IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regCGTS_TCC_DISABLE, 0x00000001, 0x00000000), | |
| 67 | + IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regCC_GC_SHADER_RATE_CONFIG, 0x00000001, 0x00000000), | |
| 68 | + IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regCC_GC_EDC_CONFIG, 0x00000001, 0x00000000), | |
| 69 | + IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCMC_VM_MX_L1_TLB_CNTL, 0x00000500, 0xe0000000), | |
| 70 | + IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCMC_VM_SYSTEM_APERTURE_LOW_ADDR, 0x00000001, 0xe0000000), | |
| 71 | + IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCMC_VM_SYSTEM_APERTURE_HIGH_ADDR, 0x00000000, 0xe0000000), | |
| 72 | + IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCMC_VM_LOCAL_FB_ADDRESS_START, 0x00000000, 0xe0000000), | |
| 73 | + IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCMC_VM_LOCAL_FB_ADDRESS_END, 0x000005ff, 0xe0000000), | |
| 74 | + IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCMC_VM_FB_LOCATION_BASE, 0x00006000, 0xe0000000), | |
| 75 | + IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCMC_VM_FB_LOCATION_TOP, 0x000065ff, 0xe0000000), | |
| 76 | + IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCVM_CONTEXT0_CNTL, 0x00000000, 0xe0000000), | |
| 77 | + IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCVM_CONTEXT1_CNTL, 0x00000000, 0xe0000000), | |
| 78 | + IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCMC_VM_NB_TOP_OF_DRAM_SLOT1, 0xff800000, 0xe0000000), | |
| 79 | + IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCMC_VM_NB_LOWER_TOP_OF_DRAM2, 0x00000001, 0xe0000000), | |
| 80 | + IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCMC_VM_NB_UPPER_TOP_OF_DRAM2, 0x00000fff, 0xe0000000), | |
| 81 | + IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCVM_L2_PROTECTION_FAULT_CNTL, 0x00001ffc, 0xe0000000), | |
| 82 | + IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCMC_VM_MX_L1_TLB_CNTL, 0x00000551, 0xe0000000), | |
| 83 | + IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCVM_L2_CNTL, 0x00080603, 0xe0000000), | |
| 84 | + IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCVM_L2_CNTL2, 0x00000003, 0xe0000000), | |
| 85 | + IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCVM_L2_CNTL3, 0x00100003, 0xe0000000), | |
| 86 | + IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCVM_L2_CNTL5, 0x00003fe0, 0xe0000000), | |
| 87 | + IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCVM_CONTEXT0_CNTL, 0x00000001, 0xe0000000), | |
| 88 | + IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCVM_L2_CONTEXT0_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES, 0x00000c00, 0xe0000000), | |
| 89 | + IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCVM_CONTEXT1_CNTL, 0x00000001, 0xe0000000), | |
| 90 | + IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCVM_L2_CONTEXT1_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES, 0x00000c00, 0xe0000000), | |
| 91 | + IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGB_ADDR_CONFIG, 0x00000444, 0xe0000000), | |
| 92 | + IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGL2_PIPE_STEER_0, 0x54105410, 0xe0000000), | |
| 93 | + IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGL2_PIPE_STEER_2, 0x76323276, 0xe0000000), | |
| 94 | + IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGB_ADDR_CONFIG, 0x00000244, 0xe0000000), | |
| 95 | + IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCUTCL2_HARVEST_BYPASS_GROUPS, 0x00000006, 0xe0000000), | |
| 96 | + IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCMC_VM_APT_CNTL, 0x0000000c, 0xe0000000), | |
| 97 | + IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCMC_VM_AGP_BASE, 0x00000000, 0xe0000000), | |
| 98 | + IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCMC_VM_AGP_BOT, 0x00000002, 0xe0000000), | |
| 99 | + IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCMC_VM_AGP_TOP, 0x00000000, 0xe0000000), | |
| 100 | + IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCVM_L2_PROTECTION_FAULT_CNTL2, 0x00020000, 0xe0000000), | |
| 101 | + IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regSDMA0_UCODE_SELFLOAD_CONTROL, 0x00000210, 0xe0000000), | |
| 102 | + IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regSDMA1_UCODE_SELFLOAD_CONTROL, 0x00000210, 0xe0000000), | |
| 103 | + IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regCPC_PSP_DEBUG, CPC_PSP_DEBUG__GPA_OVERRIDE_MASK, 0xe0000000), | |
| 104 | + IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regCPG_PSP_DEBUG, CPG_PSP_DEBUG__GPA_OVERRIDE_MASK, 0xe0000000), | |
| 105 | +}; | |
| 106 | + | |
| 107 | +static void program_rlc_ram_register_setting(struct amdgpu_device *adev, | |
| 108 | + const struct imu_rlc_ram_golden *regs, | |
| 109 | + const u32 array_size) | |
| 110 | +{ | |
| 111 | + const struct imu_rlc_ram_golden *entry; | |
| 112 | + u32 reg, data; | |
| 113 | + int i; | |
| 114 | + | |
| 115 | + for (i = 0; i < array_size; ++i) { | |
| 116 | + entry = ®s[i]; | |
| 117 | + reg = adev->reg_offset[entry->hwip][entry->instance][entry->segment] + entry->reg; | |
| 118 | + reg |= entry->addr_mask; | |
| 119 | + | |
| 120 | + data = entry->data; | |
| 121 | + if (entry->reg == regGCMC_VM_AGP_BASE) | |
| 122 | + data = 0x00ffffff; | |
| 123 | + else if (entry->reg == regGCMC_VM_AGP_TOP) | |
| 124 | + data = 0x0; | |
| 125 | + else if (entry->reg == regGCMC_VM_FB_LOCATION_BASE) | |
| 126 | + data = adev->gmc.vram_start >> 24; | |
| 127 | + else if (entry->reg == regGCMC_VM_FB_LOCATION_TOP) | |
| 128 | + data = adev->gmc.vram_end >> 24; | |
| 129 | + | |
| 130 | + WREG32_SOC15(GC, 0, regGFX_IMU_RLC_RAM_ADDR_HIGH, 0); | |
| 131 | + WREG32_SOC15(GC, 0, regGFX_IMU_RLC_RAM_ADDR_LOW, reg); | |
| 132 | + WREG32_SOC15(GC, 0, regGFX_IMU_RLC_RAM_DATA, data); | |
| 133 | + } | |
| 134 | + //Indicate the latest entry | |
| 135 | + WREG32_SOC15(GC, 0, regGFX_IMU_RLC_RAM_ADDR_HIGH, 0); | |
| 136 | + WREG32_SOC15(GC, 0, regGFX_IMU_RLC_RAM_ADDR_LOW, 0); | |
| 137 | + WREG32_SOC15(GC, 0, regGFX_IMU_RLC_RAM_DATA, 0); | |
| 138 | +} | |
| 139 | + | |
| 140 | +void imu_v11_0_3_program_rlc_ram(struct amdgpu_device *adev) | |
| 141 | +{ | |
| 142 | + program_rlc_ram_register_setting(adev, | |
| 143 | + imu_rlc_ram_golden_11_0_3, | |
| 144 | + (const u32)ARRAY_SIZE(imu_rlc_ram_golden_11_0_3)); | |
| 145 | +} | |
| @@ -0,0 +1,29 @@ | ||
| 1 | +/* | |
| 2 | + * Copyright 2022 Advanced Micro Devices, Inc. | |
| 3 | + * | |
| 4 | + * Permission is hereby granted, free of charge, to any person obtaining a | |
| 5 | + * copy of this software and associated documentation files (the "Software"), | |
| 6 | + * to deal in the Software without restriction, including without limitation | |
| 7 | + * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
| 8 | + * and/or sell copies of the Software, and to permit persons to whom the | |
| 9 | + * Software is furnished to do so, subject to the following conditions: | |
| 10 | + * | |
| 11 | + * The above copyright notice and this permission notice shall be included in | |
| 12 | + * all copies or substantial portions of the Software. | |
| 13 | + * | |
| 14 | + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
| 15 | + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
| 16 | + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
| 17 | + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
| 18 | + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
| 19 | + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
| 20 | + * OTHER DEALINGS IN THE SOFTWARE. | |
| 21 | + * | |
| 22 | + */ | |
| 23 | + | |
| 24 | +#ifndef __IMU_V11_0_3_H__ | |
| 25 | +#define __IMU_V11_0_3_H__ | |
| 26 | + | |
| 27 | +void imu_v11_0_3_program_rlc_ram(struct amdgpu_device *adev); | |
| 28 | + | |
| 29 | +#endif | |
| @@ -38,6 +38,8 @@ MODULE_FIRMWARE("amdgpu/gc_11_0_1_mes.bin"); · 37 unmodified lines | ||
| 38 | 38 | MODULE_FIRMWARE("amdgpu/gc_11_0_1_mes1.bin"); |
| 39 | 39 | MODULE_FIRMWARE("amdgpu/gc_11_0_2_mes.bin"); |
| 40 | 40 | MODULE_FIRMWARE("amdgpu/gc_11_0_2_mes1.bin"); |
| 41 | +MODULE_FIRMWARE("amdgpu/gc_11_0_3_mes.bin"); | |
| 42 | +MODULE_FIRMWARE("amdgpu/gc_11_0_3_mes1.bin"); | |
| 41 | 43 | |
| 42 | 44 | static int mes_v11_0_hw_fini(void *handle); |
| 43 | 45 | static int mes_v11_0_kiq_hw_init(struct amdgpu_device *adev); |
| @@ -189,6 +191,15 @@ static int mes_v11_0_add_hw_queue(struct amdgpu_mes *mes, · 145 unmodified lines | ||
| 189 | 191 | mes_add_queue_pkt.is_aql_queue = input->is_aql_queue; |
| 190 | 192 | mes_add_queue_pkt.gds_size = input->queue_size; |
| 191 | 193 | |
| 194 | + if (!(((adev->mes.sched_version & AMDGPU_MES_VERSION_MASK) >= 4) && | |
| 195 | + (adev->ip_versions[GC_HWIP][0] >= IP_VERSION(11, 0, 0)) && | |
| 196 | + (adev->ip_versions[GC_HWIP][0] <= IP_VERSION(11, 0, 3)))) | |
| 197 | + mes_add_queue_pkt.trap_en = 1; | |
| 198 | + | |
| 199 | + /* For KFD, gds_size is re-used for queue size (needed in MES for AQL queues) */ | |
| 200 | + mes_add_queue_pkt.is_aql_queue = input->is_aql_queue; | |
| 201 | + mes_add_queue_pkt.gds_size = input->queue_size; | |
| 202 | + | |
| 192 | 203 | return mes_v11_0_submit_pkt_and_poll_completion(mes, |
| 193 | 204 | &mes_add_queue_pkt, sizeof(mes_add_queue_pkt), |
| 194 | 205 | offsetof(union MESAPI__ADD_QUEUE, api_status)); |
| @@ -169,17 +169,17 @@ static void mmhub_v3_0_init_system_aperture_regs(struct amdgpu_device *adev) · 168 unmodified lines | ||
| 169 | 169 | uint64_t value; |
| 170 | 170 | uint32_t tmp; |
| 171 | 171 | |
| 172 | − /* Disable AGP. */ | |
| 173 | − WREG32_SOC15(MMHUB, 0, regMMMC_VM_AGP_BASE, 0); | |
| 174 | − WREG32_SOC15(MMHUB, 0, regMMMC_VM_AGP_TOP, 0); | |
| 175 | − WREG32_SOC15(MMHUB, 0, regMMMC_VM_AGP_BOT, 0x00FFFFFF); | |
| 176 | − | |
| 177 | 172 | if (!amdgpu_sriov_vf(adev)) { |
| 178 | 173 | /* |
| 179 | 174 | * the new L1 policy will block SRIOV guest from writing |
| 180 | 175 | * these regs, and they will be programed at host. |
| 181 | 176 | * so skip programing these regs. |
| 182 | 177 | */ |
| 178 | + /* Disable AGP. */ | |
| 179 | + WREG32_SOC15(MMHUB, 0, regMMMC_VM_AGP_BASE, 0); | |
| 180 | + WREG32_SOC15(MMHUB, 0, regMMMC_VM_AGP_TOP, 0); | |
| 181 | + WREG32_SOC15(MMHUB, 0, regMMMC_VM_AGP_BOT, 0x00FFFFFF); | |
| 182 | + | |
| 183 | 183 | /* Program the system aperture low logical page number. */ |
| 184 | 184 | WREG32_SOC15(MMHUB, 0, regMMMC_VM_SYSTEM_APERTURE_LOW_ADDR, |
| 185 | 185 | adev->gmc.vram_start >> 18); |
| @@ -0,0 +1,140 @@ | ||
| 1 | +/* | |
| 2 | + * Copyright 2022 Advanced Micro Devices, Inc. | |
| 3 | + * | |
| 4 | + * Permission is hereby granted, free of charge, to any person obtaining a | |
| 5 | + * copy of this software and associated documentation files (the "Software"), | |
| 6 | + * to deal in the Software without restriction, including without limitation | |
| 7 | + * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
| 8 | + * and/or sell copies of the Software, and to permit persons to whom the | |
| 9 | + * Software is furnished to do so, subject to the following conditions: | |
| 10 | + * | |
| 11 | + * The above copyright notice and this permission notice shall be included in | |
| 12 | + * all copies or substantial portions of the Software. | |
| 13 | + * | |
| 14 | + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
| 15 | + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
| 16 | + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
| 17 | + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
| 18 | + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
| 19 | + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
| 20 | + * OTHER DEALINGS IN THE SOFTWARE. | |
| 21 | + * | |
| 22 | + */ | |
| 23 | + | |
| 24 | +#ifndef __MMSCH_V4_0_H__ | |
| 25 | +#define __MMSCH_V4_0_H__ | |
| 26 | + | |
| 27 | +#include "amdgpu_vcn.h" | |
| 28 | + | |
| 29 | +#define MMSCH_VERSION_MAJOR 4 | |
| 30 | +#define MMSCH_VERSION_MINOR 0 | |
| 31 | +#define MMSCH_VERSION (MMSCH_VERSION_MAJOR << 16 | MMSCH_VERSION_MINOR) | |
| 32 | + | |
| 33 | +#define RB_ENABLED (1 << 0) | |
| 34 | +#define RB4_ENABLED (1 << 1) | |
| 35 | +#define MMSCH_DOORBELL_OFFSET 0x8 | |
| 36 | + | |
| 37 | +#define MMSCH_VF_ENGINE_STATUS__PASS 0x1 | |
| 38 | + | |
| 39 | +#define MMSCH_VF_MAILBOX_RESP__OK 0x1 | |
| 40 | +#define MMSCH_VF_MAILBOX_RESP__INCOMPLETE 0x2 | |
| 41 | + | |
| 42 | +enum mmsch_v4_0_command_type { | |
| 43 | + MMSCH_COMMAND__DIRECT_REG_WRITE = 0, | |
| 44 | + MMSCH_COMMAND__DIRECT_REG_POLLING = 2, | |
| 45 | + MMSCH_COMMAND__DIRECT_REG_READ_MODIFY_WRITE = 3, | |
| 46 | + MMSCH_COMMAND__INDIRECT_REG_WRITE = 8, | |
| 47 | + MMSCH_COMMAND__END = 0xf | |
| 48 | +}; | |
| 49 | + | |
| 50 | +struct mmsch_v4_0_table_info { | |
| 51 | + uint32_t init_status; | |
| 52 | + uint32_t table_offset; | |
| 53 | + uint32_t table_size; | |
| 54 | +}; | |
| 55 | + | |
| 56 | +struct mmsch_v4_0_init_header { | |
| 57 | + uint32_t version; | |
| 58 | + uint32_t total_size; | |
| 59 | + struct mmsch_v4_0_table_info inst[AMDGPU_MAX_VCN_INSTANCES]; | |
| 60 | + struct mmsch_v4_0_table_info jpegdec; | |
| 61 | +}; | |
| 62 | + | |
| 63 | +struct mmsch_v4_0_cmd_direct_reg_header { | |
| 64 | + uint32_t reg_offset : 28; | |
| 65 | + uint32_t command_type : 4; | |
| 66 | +}; | |
| 67 | + | |
| 68 | +struct mmsch_v4_0_cmd_indirect_reg_header { | |
| 69 | + uint32_t reg_offset : 20; | |
| 70 | + uint32_t reg_idx_space : 8; | |
| 71 | + uint32_t command_type : 4; | |
| 72 | +}; | |
| 73 | + | |
| 74 | +struct mmsch_v4_0_cmd_direct_write { | |
| 75 | + struct mmsch_v4_0_cmd_direct_reg_header cmd_header; | |
| 76 | + uint32_t reg_value; | |
| 77 | +}; | |
| 78 | + | |
| 79 | +struct mmsch_v4_0_cmd_direct_read_modify_write { | |
| 80 | + struct mmsch_v4_0_cmd_direct_reg_header cmd_header; | |
| 81 | + uint32_t write_data; | |
| 82 | + uint32_t mask_value; | |
| 83 | +}; | |
| 84 | + | |
| 85 | +struct mmsch_v4_0_cmd_direct_polling { | |
| 86 | + struct mmsch_v4_0_cmd_direct_reg_header cmd_header; | |
| 87 | + uint32_t mask_value; | |
| 88 | + uint32_t wait_value; | |
| 89 | +}; | |
| 90 | + | |
| 91 | +struct mmsch_v4_0_cmd_end { | |
| 92 | + struct mmsch_v4_0_cmd_direct_reg_header cmd_header; | |
| 93 | +}; | |
| 94 | + | |
| 95 | +struct mmsch_v4_0_cmd_indirect_write { | |
| 96 | + struct mmsch_v4_0_cmd_indirect_reg_header cmd_header; | |
| 97 | + uint32_t reg_value; | |
| 98 | +}; | |
| 99 | + | |
| 100 | +#define MMSCH_V4_0_INSERT_DIRECT_RD_MOD_WT(reg, mask, data) { \ | |
| 101 | + size = sizeof(struct mmsch_v4_0_cmd_direct_read_modify_write); \ | |
| 102 | + size_dw = size / 4; \ | |
| 103 | + direct_rd_mod_wt.cmd_header.reg_offset = reg; \ | |
| 104 | + direct_rd_mod_wt.mask_value = mask; \ | |
| 105 | + direct_rd_mod_wt.write_data = data; \ | |
| 106 | + memcpy((void *)table_loc, &direct_rd_mod_wt, size); \ | |
| 107 | + table_loc += size_dw; \ | |
| 108 | + table_size += size_dw; \ | |
| 109 | +} | |
| 110 | + | |
| 111 | +#define MMSCH_V4_0_INSERT_DIRECT_WT(reg, value) { \ | |
| 112 | + size = sizeof(struct mmsch_v4_0_cmd_direct_write); \ | |
| 113 | + size_dw = size / 4; \ | |
| 114 | + direct_wt.cmd_header.reg_offset = reg; \ | |
| 115 | + direct_wt.reg_value = value; \ | |
| 116 | + memcpy((void *)table_loc, &direct_wt, size); \ | |
| 117 | + table_loc += size_dw; \ | |
| 118 | + table_size += size_dw; \ | |
| 119 | +} | |
| 120 | + | |
| 121 | +#define MMSCH_V4_0_INSERT_DIRECT_POLL(reg, mask, wait) { \ | |
| 122 | + size = sizeof(struct mmsch_v4_0_cmd_direct_polling); \ | |
| 123 | + size_dw = size / 4; \ | |
| 124 | + direct_poll.cmd_header.reg_offset = reg; \ | |
| 125 | + direct_poll.mask_value = mask; \ | |
| 126 | + direct_poll.wait_value = wait; \ | |
| 127 | + memcpy((void *)table_loc, &direct_poll, size); \ | |
| 128 | + table_loc += size_dw; \ | |
| 129 | + table_size += size_dw; \ | |
| 130 | +} | |
| 131 | + | |
| 132 | +#define MMSCH_V4_0_INSERT_END() { \ | |
| 133 | + size = sizeof(struct mmsch_v4_0_cmd_end); \ | |
| 134 | + size_dw = size / 4; \ | |
| 135 | + memcpy((void *)table_loc, &end, size); \ | |
| 136 | + table_loc += size_dw; \ | |
| 137 | + table_size += size_dw; \ | |
| 138 | +} | |
| 139 | + | |
| 140 | +#endif | |
| @@ -290,6 +290,7 @@ flr_done: · 289 unmodified lines | ||
| 290 | 290 | reset_context.method = AMD_RESET_METHOD_NONE; |
| 291 | 291 | reset_context.reset_req_dev = adev; |
| 292 | 292 | clear_bit(AMDGPU_NEED_FULL_RESET, &reset_context.flags); |
| 293 | + clear_bit(AMDGPU_SKIP_MODE2_RESET, &reset_context.flags); | |
| 293 | 294 | |
| 294 | 295 | amdgpu_device_gpu_recover(adev, NULL, &reset_context); |
| 295 | 296 | } |
| @@ -317,6 +317,7 @@ flr_done: · 316 unmodified lines | ||
| 317 | 317 | reset_context.method = AMD_RESET_METHOD_NONE; |
| 318 | 318 | reset_context.reset_req_dev = adev; |
| 319 | 319 | clear_bit(AMDGPU_NEED_FULL_RESET, &reset_context.flags); |
| 320 | + clear_bit(AMDGPU_SKIP_MODE2_RESET, &reset_context.flags); | |
| 320 | 321 | |
| 321 | 322 | amdgpu_device_gpu_recover(adev, NULL, &reset_context); |
| 322 | 323 | } |
| @@ -529,6 +529,7 @@ static void xgpu_vi_mailbox_flr_work(struct work_struct *work) · 528 unmodified lines | ||
| 529 | 529 | reset_context.method = AMD_RESET_METHOD_NONE; |
| 530 | 530 | reset_context.reset_req_dev = adev; |
| 531 | 531 | clear_bit(AMDGPU_NEED_FULL_RESET, &reset_context.flags); |
| 532 | + clear_bit(AMDGPU_SKIP_MODE2_RESET, &reset_context.flags); | |
| 532 | 533 | |
| 533 | 534 | amdgpu_device_gpu_recover(adev, NULL, &reset_context); |
| 534 | 535 | } |
| @@ -488,3 +488,47 @@ const struct amdgpu_nbio_funcs nbio_v4_3_funcs = { · 487 unmodified lines | ||
| 488 | 488 | .get_rom_offset = nbio_v4_3_get_rom_offset, |
| 489 | 489 | .program_aspm = nbio_v4_3_program_aspm, |
| 490 | 490 | }; |
| 491 | + | |
| 492 | + | |
| 493 | +static void nbio_v4_3_sriov_ih_doorbell_range(struct amdgpu_device *adev, | |
| 494 | + bool use_doorbell, int doorbell_index) | |
| 495 | +{ | |
| 496 | +} | |
| 497 | + | |
| 498 | +static void nbio_v4_3_sriov_sdma_doorbell_range(struct amdgpu_device *adev, int instance, | |
| 499 | + bool use_doorbell, int doorbell_index, | |
| 500 | + int doorbell_size) | |
| 501 | +{ | |
| 502 | +} | |
| 503 | + | |
| 504 | +static void nbio_v4_3_sriov_vcn_doorbell_range(struct amdgpu_device *adev, bool use_doorbell, | |
| 505 | + int doorbell_index, int instance) | |
| 506 | +{ | |
| 507 | +} | |
| 508 | + | |
| 509 | +static void nbio_v4_3_sriov_gc_doorbell_init(struct amdgpu_device *adev) | |
| 510 | +{ | |
| 511 | +} | |
| 512 | + | |
| 513 | +const struct amdgpu_nbio_funcs nbio_v4_3_sriov_funcs = { | |
| 514 | + .get_hdp_flush_req_offset = nbio_v4_3_get_hdp_flush_req_offset, | |
| 515 | + .get_hdp_flush_done_offset = nbio_v4_3_get_hdp_flush_done_offset, | |
| 516 | + .get_pcie_index_offset = nbio_v4_3_get_pcie_index_offset, | |
| 517 | + .get_pcie_data_offset = nbio_v4_3_get_pcie_data_offset, | |
| 518 | + .get_rev_id = nbio_v4_3_get_rev_id, | |
| 519 | + .mc_access_enable = nbio_v4_3_mc_access_enable, | |
| 520 | + .get_memsize = nbio_v4_3_get_memsize, | |
| 521 | + .sdma_doorbell_range = nbio_v4_3_sriov_sdma_doorbell_range, | |
| 522 | + .vcn_doorbell_range = nbio_v4_3_sriov_vcn_doorbell_range, | |
| 523 | + .gc_doorbell_init = nbio_v4_3_sriov_gc_doorbell_init, | |
| 524 | + .enable_doorbell_aperture = nbio_v4_3_enable_doorbell_aperture, | |
| 525 | + .enable_doorbell_selfring_aperture = nbio_v4_3_enable_doorbell_selfring_aperture, | |
| 526 | + .ih_doorbell_range = nbio_v4_3_sriov_ih_doorbell_range, | |
| 527 | + .update_medium_grain_clock_gating = nbio_v4_3_update_medium_grain_clock_gating, | |
| 528 | + .update_medium_grain_light_sleep = nbio_v4_3_update_medium_grain_light_sleep, | |
| 529 | + .get_clockgating_state = nbio_v4_3_get_clockgating_state, | |
| 530 | + .ih_control = nbio_v4_3_ih_control, | |
| 531 | + .init_registers = nbio_v4_3_init_registers, | |
| 532 | + .remap_hdp_registers = nbio_v4_3_remap_hdp_registers, | |
| 533 | + .get_rom_offset = nbio_v4_3_get_rom_offset, | |
| 534 | +}; | |
| @@ -28,5 +28,6 @@ · 27 unmodified lines | ||
| 28 | 28 | |
| 29 | 29 | extern const struct nbio_hdp_flush_reg nbio_v4_3_hdp_flush_reg; |
| 30 | 30 | extern const struct amdgpu_nbio_funcs nbio_v4_3_funcs; |
| 31 | +extern const struct amdgpu_nbio_funcs nbio_v4_3_sriov_funcs; | |
| 31 | 32 | |
| 32 | 33 | #endif |
| @@ -44,6 +44,7 @@ MODULE_FIRMWARE("amdgpu/psp_13_0_0_sos.bin"); · 43 unmodified lines | ||
| 44 | 44 | MODULE_FIRMWARE("amdgpu/psp_13_0_0_ta.bin"); |
| 45 | 45 | MODULE_FIRMWARE("amdgpu/psp_13_0_7_sos.bin"); |
| 46 | 46 | MODULE_FIRMWARE("amdgpu/psp_13_0_7_ta.bin"); |
| 47 | +MODULE_FIRMWARE("amdgpu/psp_13_0_10_sos.bin"); | |
| 47 | 48 | |
| 48 | 49 | /* For large FW files the time to complete can be very long */ |
| 49 | 50 | #define USBC_PD_POLLING_LIMIT_S 240 |
| @@ -109,6 +110,7 @@ static int psp_v13_0_init_microcode(struct psp_context *psp) · 59 unmodified lines | ||
| 109 | 110 | break; |
| 110 | 111 | case IP_VERSION(13, 0, 0): |
| 111 | 112 | case IP_VERSION(13, 0, 7): |
| 113 | + case IP_VERSION(13, 0, 10): | |
| 112 | 114 | err = psp_init_sos_microcode(psp, chip_name); |
| 113 | 115 | if (err) |
| 114 | 116 | return err; |
| @@ -222,6 +224,12 @@ static int psp_v13_0_bootloader_load_dbg_drv(struct psp_context *psp) · 107 unmodified lines | ||
| 222 | 224 | return psp_v13_0_bootloader_load_component(psp, &psp->dbg_drv, PSP_BL__LOAD_DBGDRV); |
| 223 | 225 | } |
| 224 | 226 | |
| 227 | +static int psp_v13_0_bootloader_load_ras_drv(struct psp_context *psp) | |
| 228 | +{ | |
| 229 | + return psp_v13_0_bootloader_load_component(psp, &psp->ras_drv, PSP_BL__LOAD_RASDRV); | |
| 230 | +} | |
| 231 | + | |
| 232 | + | |
| 225 | 233 | static int psp_v13_0_bootloader_load_sos(struct psp_context *psp) |
| 226 | 234 | { |
| 227 | 235 | int ret; |
| @@ -718,6 +726,7 @@ static const struct psp_funcs psp_v13_0_funcs = { · 490 unmodified lines | ||
| 718 | 726 | .bootloader_load_soc_drv = psp_v13_0_bootloader_load_soc_drv, |
| 719 | 727 | .bootloader_load_intf_drv = psp_v13_0_bootloader_load_intf_drv, |
| 720 | 728 | .bootloader_load_dbg_drv = psp_v13_0_bootloader_load_dbg_drv, |
| 729 | + .bootloader_load_ras_drv = psp_v13_0_bootloader_load_ras_drv, | |
| 721 | 730 | .bootloader_load_sos = psp_v13_0_bootloader_load_sos, |
| 722 | 731 | .ring_init = psp_v13_0_ring_init, |
| 723 | 732 | .ring_create = psp_v13_0_ring_create, |
| @@ -561,44 +561,6 @@ static void sdma_v4_0_setup_ulv(struct amdgpu_device *adev) · 560 unmodified lines | ||
| 561 | 561 | } |
| 562 | 562 | } |
| 563 | 563 | |
| 564 | −static int sdma_v4_0_init_inst_ctx(struct amdgpu_sdma_instance *sdma_inst) | |
| 565 | −{ | |
| 566 | − int err = 0; | |
| 567 | − const struct sdma_firmware_header_v1_0 *hdr; | |
| 568 | − | |
| 569 | − err = amdgpu_ucode_validate(sdma_inst->fw); | |
| 570 | − if (err) | |
| 571 | − return err; | |
| 572 | − | |
| 573 | − hdr = (const struct sdma_firmware_header_v1_0 *)sdma_inst->fw->data; | |
| 574 | − sdma_inst->fw_version = le32_to_cpu(hdr->header.ucode_version); | |
| 575 | − sdma_inst->feature_version = le32_to_cpu(hdr->ucode_feature_version); | |
| 576 | − | |
| 577 | − if (sdma_inst->feature_version >= 20) | |
| 578 | − sdma_inst->burst_nop = true; | |
| 579 | − | |
| 580 | − return 0; | |
| 581 | −} | |
| 582 | − | |
| 583 | −static void sdma_v4_0_destroy_inst_ctx(struct amdgpu_device *adev) | |
| 584 | −{ | |
| 585 | − int i; | |
| 586 | − | |
| 587 | − for (i = 0; i < adev->sdma.num_instances; i++) { | |
| 588 | − release_firmware(adev->sdma.instance[i].fw); | |
| 589 | − adev->sdma.instance[i].fw = NULL; | |
| 590 | − | |
| 591 | − /* arcturus shares the same FW memory across | |
| 592 | − all SDMA isntances */ | |
| 593 | − if (adev->ip_versions[SDMA0_HWIP][0] == IP_VERSION(4, 2, 2) || | |
| 594 | − adev->ip_versions[SDMA0_HWIP][0] == IP_VERSION(4, 4, 0)) | |
| 595 | − break; | |
| 596 | − } | |
| 597 | − | |
| 598 | − memset((void *)adev->sdma.instance, 0, | |
| 599 | − sizeof(struct amdgpu_sdma_instance) * AMDGPU_MAX_SDMA_INSTANCES); | |
| 600 | −} | |
| 601 | − | |
| 602 | 564 | /** |
| 603 | 565 | * sdma_v4_0_init_microcode - load ucode images from disk |
| 604 | 566 | * |
| @@ -615,9 +577,7 @@ static int sdma_v4_0_init_microcode(struct amdgpu_device *adev) · 10 unmodified lines | ||
| 615 | 577 | { |
| 616 | 578 | const char *chip_name; |
| 617 | 579 | char fw_name[30]; |
| 618 | − int err = 0, i; | |
| 619 | − struct amdgpu_firmware_info *info = NULL; | |
| 620 | − const struct common_firmware_header *header = NULL; | |
| 580 | + int ret, i; | |
| 621 | 581 | |
| 622 | 582 | DRM_DEBUG("\n"); |
| 623 | 583 | |
| @@ -656,58 +616,25 @@ static int sdma_v4_0_init_microcode(struct amdgpu_device *adev) · 32 unmodified lines | ||
| 656 | 616 | BUG(); |
| 657 | 617 | } |
| 658 | 618 | |
| 659 | − snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sdma.bin", chip_name); | |
| 660 | − | |
| 661 | − err = request_firmware(&adev->sdma.instance[0].fw, fw_name, adev->dev); | |
| 662 | − if (err) | |
| 663 | − goto out; | |
| 664 | − | |
| 665 | − err = sdma_v4_0_init_inst_ctx(&adev->sdma.instance[0]); | |
| 666 | − if (err) | |
| 667 | − goto out; | |
| 668 | − | |
| 669 | − for (i = 1; i < adev->sdma.num_instances; i++) { | |
| 619 | + for (i = 0; i < adev->sdma.num_instances; i++) { | |
| 620 | + if (i == 0) | |
| 621 | + snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sdma.bin", chip_name); | |
| 622 | + else | |
| 623 | + snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sdma%d.bin", chip_name, i); | |
| 670 | 624 | if (adev->ip_versions[SDMA0_HWIP][0] == IP_VERSION(4, 2, 2) || |
| 671 | 625 | adev->ip_versions[SDMA0_HWIP][0] == IP_VERSION(4, 4, 0)) { |
| 672 | 626 | /* Acturus & Aldebaran will leverage the same FW memory |
| 673 | 627 | for every SDMA instance */ |
| 674 | − memcpy((void *)&adev->sdma.instance[i], | |
| 675 | − (void *)&adev->sdma.instance[0], | |
| 676 | − sizeof(struct amdgpu_sdma_instance)); | |
| 677 | − } | |
| 678 | − else { | |
| 679 | − snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sdma%d.bin", chip_name, i); | |
| 680 | − | |
| 681 | − err = request_firmware(&adev->sdma.instance[i].fw, fw_name, adev->dev); | |
| 682 | − if (err) | |
| 683 | − goto out; | |
| 684 | − | |
| 685 | − err = sdma_v4_0_init_inst_ctx(&adev->sdma.instance[i]); | |
| 686 | − if (err) | |
| 687 | − goto out; | |
| 688 | − } | |
| 689 | − } | |
| 690 | − | |
| 691 | − DRM_DEBUG("psp_load == '%s'\n", | |
| 692 | − adev->firmware.load_type == AMDGPU_FW_LOAD_PSP ? "true" : "false"); | |
| 693 | − | |
| 694 | − if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { | |
| 695 | − for (i = 0; i < adev->sdma.num_instances; i++) { | |
| 696 | − info = &adev->firmware.ucode[AMDGPU_UCODE_ID_SDMA0 + i]; | |
| 697 | − info->ucode_id = AMDGPU_UCODE_ID_SDMA0 + i; | |
| 698 | − info->fw = adev->sdma.instance[i].fw; | |
| 699 | − header = (const struct common_firmware_header *)info->fw->data; | |
| 700 | − adev->firmware.fw_size += | |
| 701 | − ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE); | |
| 628 | + ret = amdgpu_sdma_init_microcode(adev, fw_name, 0, true); | |
| 629 | + break; | |
| 630 | + } else { | |
| 631 | + ret = amdgpu_sdma_init_microcode(adev, fw_name, i, false); | |
| 632 | + if (ret) | |
| 633 | + return ret; | |
| 702 | 634 | } |
| 703 | 635 | } |
| 704 | 636 | |
| 705 | −out: | |
| 706 | − if (err) { | |
| 707 | − DRM_ERROR("sdma_v4_0: Failed to load firmware \"%s\"\n", fw_name); | |
| 708 | − sdma_v4_0_destroy_inst_ctx(adev); | |
| 709 | − } | |
| 710 | − return err; | |
| 637 | + return ret; | |
| 711 | 638 | } |
| 712 | 639 | |
| 713 | 640 | /** |
| @@ -2000,14 +1927,17 @@ static int sdma_v4_0_sw_fini(void *handle) · 1286 unmodified lines | ||
| 2000 | 1927 | amdgpu_ring_fini(&adev->sdma.instance[i].page); |
| 2001 | 1928 | } |
| 2002 | 1929 | |
| 2003 | − sdma_v4_0_destroy_inst_ctx(adev); | |
| 1930 | + if (adev->ip_versions[SDMA0_HWIP][0] == IP_VERSION(4, 2, 0) || | |
| 1931 | + adev->ip_versions[SDMA0_HWIP][0] == IP_VERSION(4, 4, 0)) | |
| 1932 | + amdgpu_sdma_destroy_inst_ctx(adev, true); | |
| 1933 | + else | |
| 1934 | + amdgpu_sdma_destroy_inst_ctx(adev, false); | |
| 2004 | 1935 | |
| 2005 | 1936 | return 0; |
| 2006 | 1937 | } |
| 2007 | 1938 | |
| 2008 | 1939 | static int sdma_v4_0_hw_init(void *handle) |
| 2009 | 1940 | { |
| 2010 | − int r; | |
| 2011 | 1941 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
| 2012 | 1942 | |
| 2013 | 1943 | if (adev->flags & AMD_IS_APU) |
| @@ -2016,9 +1946,7 @@ static int sdma_v4_0_hw_init(void *handle) · 2 unmodified lines | ||
| 2016 | 1946 | if (!amdgpu_sriov_vf(adev)) |
| 2017 | 1947 | sdma_v4_0_init_golden_registers(adev); |
| 2018 | 1948 | |
| 2019 | − r = sdma_v4_0_start(adev); | |
| 2020 | − | |
| 2021 | − return r; | |
| 1949 | + return sdma_v4_0_start(adev); | |
| 2022 | 1950 | } |
| 2023 | 1951 | |
| 2024 | 1952 | static int sdma_v4_0_hw_fini(void *handle) |
| @@ -240,10 +240,7 @@ static int sdma_v5_0_init_microcode(struct amdgpu_device *adev) · 239 unmodified lines | ||
| 240 | 240 | { |
| 241 | 241 | const char *chip_name; |
| 242 | 242 | char fw_name[40]; |
| 243 | − int err = 0, i; | |
| 244 | − struct amdgpu_firmware_info *info = NULL; | |
| 245 | − const struct common_firmware_header *header = NULL; | |
| 246 | − const struct sdma_firmware_header_v1_0 *hdr; | |
| 243 | + int ret, i; | |
| 247 | 244 | |
| 248 | 245 | if (amdgpu_sriov_vf(adev) && (adev->ip_versions[SDMA0_HWIP][0] == IP_VERSION(5, 0, 5))) |
| 249 | 246 | return 0; |
| @@ -272,38 +269,12 @@ static int sdma_v5_0_init_microcode(struct amdgpu_device *adev) · 22 unmodified lines | ||
| 272 | 269 | snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sdma.bin", chip_name); |
| 273 | 270 | else |
| 274 | 271 | snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sdma1.bin", chip_name); |
| 275 | − err = request_firmware(&adev->sdma.instance[i].fw, fw_name, adev->dev); | |
| 276 | − if (err) | |
| 277 | − goto out; | |
| 278 | − err = amdgpu_ucode_validate(adev->sdma.instance[i].fw); | |
| 279 | − if (err) | |
| 280 | − goto out; | |
| 281 | − hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma.instance[i].fw->data; | |
| 282 | − adev->sdma.instance[i].fw_version = le32_to_cpu(hdr->header.ucode_version); | |
| 283 | − adev->sdma.instance[i].feature_version = le32_to_cpu(hdr->ucode_feature_version); | |
| 284 | − if (adev->sdma.instance[i].feature_version >= 20) | |
| 285 | − adev->sdma.instance[i].burst_nop = true; | |
| 286 | − DRM_DEBUG("psp_load == '%s'\n", | |
| 287 | − adev->firmware.load_type == AMDGPU_FW_LOAD_PSP ? "true" : "false"); | |
| 288 | − | |
| 289 | − if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { | |
| 290 | − info = &adev->firmware.ucode[AMDGPU_UCODE_ID_SDMA0 + i]; | |
| 291 | − info->ucode_id = AMDGPU_UCODE_ID_SDMA0 + i; | |
| 292 | − info->fw = adev->sdma.instance[i].fw; | |
| 293 | − header = (const struct common_firmware_header *)info->fw->data; | |
| 294 | − adev->firmware.fw_size += | |
| 295 | − ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE); | |
| 296 | − } | |
| 297 | − } | |
| 298 | −out: | |
| 299 | − if (err) { | |
| 300 | − DRM_ERROR("sdma_v5_0: Failed to load firmware \"%s\"\n", fw_name); | |
| 301 | − for (i = 0; i < adev->sdma.num_instances; i++) { | |
| 302 | − release_firmware(adev->sdma.instance[i].fw); | |
| 303 | − adev->sdma.instance[i].fw = NULL; | |
| 304 | − } | |
| 272 | + ret = amdgpu_sdma_init_microcode(adev, fw_name, i, false); | |
| 273 | + if (ret) | |
| 274 | + return ret; | |
| 305 | 275 | } |
| 306 | − return err; | |
| 276 | + | |
| 277 | + return ret; | |
| 307 | 278 | } |
| 308 | 279 | |
| 309 | 280 | static unsigned sdma_v5_0_ring_init_cond_exec(struct amdgpu_ring *ring) |
| @@ -1465,12 +1436,10 @@ static int sdma_v5_0_sw_fini(void *handle) · 1155 unmodified lines | ||
| 1465 | 1436 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
| 1466 | 1437 | int i; |
| 1467 | 1438 | |
| 1468 | − for (i = 0; i < adev->sdma.num_instances; i++) { | |
| 1469 | − release_firmware(adev->sdma.instance[i].fw); | |
| 1470 | − adev->sdma.instance[i].fw = NULL; | |
| 1471 | − | |
| 1439 | + for (i = 0; i < adev->sdma.num_instances; i++) | |
| 1472 | 1440 | amdgpu_ring_fini(&adev->sdma.instance[i].ring); |
| 1473 | − } | |
| 1441 | + | |
| 1442 | + amdgpu_sdma_destroy_inst_ctx(adev, false); | |
| 1474 | 1443 | |
| 1475 | 1444 | return 0; |
| 1476 | 1445 | } |
| @@ -89,33 +89,6 @@ static u32 sdma_v5_2_get_reg_offset(struct amdgpu_device *adev, u32 instance, u3 · 88 unmodified lines | ||
| 89 | 89 | return base + internal_offset; |
| 90 | 90 | } |
| 91 | 91 | |
| 92 | −static int sdma_v5_2_init_inst_ctx(struct amdgpu_sdma_instance *sdma_inst) | |
| 93 | −{ | |
| 94 | − int err = 0; | |
| 95 | − const struct sdma_firmware_header_v1_0 *hdr; | |
| 96 | − | |
| 97 | − err = amdgpu_ucode_validate(sdma_inst->fw); | |
| 98 | − if (err) | |
| 99 | − return err; | |
| 100 | − | |
| 101 | − hdr = (const struct sdma_firmware_header_v1_0 *)sdma_inst->fw->data; | |
| 102 | − sdma_inst->fw_version = le32_to_cpu(hdr->header.ucode_version); | |
| 103 | − sdma_inst->feature_version = le32_to_cpu(hdr->ucode_feature_version); | |
| 104 | − | |
| 105 | − if (sdma_inst->feature_version >= 20) | |
| 106 | − sdma_inst->burst_nop = true; | |
| 107 | − | |
| 108 | − return 0; | |
| 109 | −} | |
| 110 | − | |
| 111 | −static void sdma_v5_2_destroy_inst_ctx(struct amdgpu_device *adev) | |
| 112 | −{ | |
| 113 | − release_firmware(adev->sdma.instance[0].fw); | |
| 114 | − | |
| 115 | − memset((void *)adev->sdma.instance, 0, | |
| 116 | − sizeof(struct amdgpu_sdma_instance) * AMDGPU_MAX_SDMA_INSTANCES); | |
| 117 | −} | |
| 118 | − | |
| 119 | 92 | /** |
| 120 | 93 | * sdma_v5_2_init_microcode - load ucode images from disk |
| 121 | 94 | * |
| @@ -132,9 +105,6 @@ static int sdma_v5_2_init_microcode(struct amdgpu_device *adev) · 10 unmodified lines | ||
| 132 | 105 | { |
| 133 | 106 | const char *chip_name; |
| 134 | 107 | char fw_name[40]; |
| 135 | − int err = 0, i; | |
| 136 | − struct amdgpu_firmware_info *info = NULL; | |
| 137 | − const struct common_firmware_header *header = NULL; | |
| 138 | 108 | |
| 139 | 109 | DRM_DEBUG("\n"); |
| 140 | 110 | |
| @@ -169,42 +139,7 @@ static int sdma_v5_2_init_microcode(struct amdgpu_device *adev) · 28 unmodified lines | ||
| 169 | 139 | |
| 170 | 140 | snprintf(fw_name, sizeof(fw_name), "amdgpu/%s.bin", chip_name); |
| 171 | 141 | |
| 172 | − err = request_firmware(&adev->sdma.instance[0].fw, fw_name, adev->dev); | |
| 173 | − if (err) | |
| 174 | − goto out; | |
| 175 | − | |
| 176 | − err = sdma_v5_2_init_inst_ctx(&adev->sdma.instance[0]); | |
| 177 | − if (err) | |
| 178 | − goto out; | |
| 179 | − | |
| 180 | − for (i = 1; i < adev->sdma.num_instances; i++) | |
| 181 | − memcpy((void *)&adev->sdma.instance[i], | |
| 182 | − (void *)&adev->sdma.instance[0], | |
| 183 | − sizeof(struct amdgpu_sdma_instance)); | |
| 184 | − | |
| 185 | − if (amdgpu_sriov_vf(adev) && (adev->ip_versions[SDMA0_HWIP][0] == IP_VERSION(5, 2, 0))) | |
| 186 | − return 0; | |
| 187 | − | |
| 188 | − DRM_DEBUG("psp_load == '%s'\n", | |
| 189 | − adev->firmware.load_type == AMDGPU_FW_LOAD_PSP ? "true" : "false"); | |
| 190 | − | |
| 191 | − if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { | |
| 192 | − for (i = 0; i < adev->sdma.num_instances; i++) { | |
| 193 | − info = &adev->firmware.ucode[AMDGPU_UCODE_ID_SDMA0 + i]; | |
| 194 | − info->ucode_id = AMDGPU_UCODE_ID_SDMA0 + i; | |
| 195 | − info->fw = adev->sdma.instance[i].fw; | |
| 196 | − header = (const struct common_firmware_header *)info->fw->data; | |
| 197 | − adev->firmware.fw_size += | |
| 198 | − ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE); | |
| 199 | − } | |
| 200 | − } | |
| 201 | − | |
| 202 | −out: | |
| 203 | − if (err) { | |
| 204 | − DRM_ERROR("sdma_v5_2: Failed to load firmware \"%s\"\n", fw_name); | |
| 205 | − sdma_v5_2_destroy_inst_ctx(adev); | |
| 206 | − } | |
| 207 | − return err; | |
| 142 | + return amdgpu_sdma_init_microcode(adev, fw_name, 0, true); | |
| 208 | 143 | } |
| 209 | 144 | |
| 210 | 145 | static unsigned sdma_v5_2_ring_init_cond_exec(struct amdgpu_ring *ring) |
| @@ -1406,19 +1341,16 @@ static int sdma_v5_2_sw_fini(void *handle) · 1195 unmodified lines | ||
| 1406 | 1341 | for (i = 0; i < adev->sdma.num_instances; i++) |
| 1407 | 1342 | amdgpu_ring_fini(&adev->sdma.instance[i].ring); |
| 1408 | 1343 | |
| 1409 | − sdma_v5_2_destroy_inst_ctx(adev); | |
| 1344 | + amdgpu_sdma_destroy_inst_ctx(adev, true); | |
| 1410 | 1345 | |
| 1411 | 1346 | return 0; |
| 1412 | 1347 | } |
| 1413 | 1348 | |
| 1414 | 1349 | static int sdma_v5_2_hw_init(void *handle) |
| 1415 | 1350 | { |
| 1416 | − int r; | |
| 1417 | 1351 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
| 1418 | 1352 | |
| 1419 | − r = sdma_v5_2_start(adev); | |
| 1420 | − | |
| 1421 | − return r; | |
| 1353 | + return sdma_v5_2_start(adev); | |
| 1422 | 1354 | } |
| 1423 | 1355 | |
| 1424 | 1356 | static int sdma_v5_2_hw_fini(void *handle) |
| @@ -47,6 +47,7 @@ · 46 unmodified lines | ||
| 47 | 47 | MODULE_FIRMWARE("amdgpu/sdma_6_0_0.bin"); |
| 48 | 48 | MODULE_FIRMWARE("amdgpu/sdma_6_0_1.bin"); |
| 49 | 49 | MODULE_FIRMWARE("amdgpu/sdma_6_0_2.bin"); |
| 50 | +MODULE_FIRMWARE("amdgpu/sdma_6_0_3.bin"); | |
| 50 | 51 | |
| 51 | 52 | #define SDMA1_REG_OFFSET 0x600 |
| 52 | 53 | #define SDMA0_HYP_DEC_REG_START 0x5880 |
| @@ -77,33 +78,6 @@ static u32 sdma_v6_0_get_reg_offset(struct amdgpu_device *adev, u32 instance, u3 · 24 unmodified lines | ||
| 77 | 78 | return base + internal_offset; |
| 78 | 79 | } |
| 79 | 80 | |
| 80 | −static int sdma_v6_0_init_inst_ctx(struct amdgpu_sdma_instance *sdma_inst) | |
| 81 | −{ | |
| 82 | − int err = 0; | |
| 83 | − const struct sdma_firmware_header_v2_0 *hdr; | |
| 84 | − | |
| 85 | − err = amdgpu_ucode_validate(sdma_inst->fw); | |
| 86 | − if (err) | |
| 87 | − return err; | |
| 88 | − | |
| 89 | − hdr = (const struct sdma_firmware_header_v2_0 *)sdma_inst->fw->data; | |
| 90 | − sdma_inst->fw_version = le32_to_cpu(hdr->header.ucode_version); | |
| 91 | − sdma_inst->feature_version = le32_to_cpu(hdr->ucode_feature_version); | |
| 92 | − | |
| 93 | − if (sdma_inst->feature_version >= 20) | |
| 94 | − sdma_inst->burst_nop = true; | |
| 95 | − | |
| 96 | − return 0; | |
| 97 | −} | |
| 98 | − | |
| 99 | −static void sdma_v6_0_destroy_inst_ctx(struct amdgpu_device *adev) | |
| 100 | −{ | |
| 101 | − release_firmware(adev->sdma.instance[0].fw); | |
| 102 | − | |
| 103 | − memset((void*)adev->sdma.instance, 0, | |
| 104 | − sizeof(struct amdgpu_sdma_instance) * AMDGPU_MAX_SDMA_INSTANCES); | |
| 105 | −} | |
| 106 | − | |
| 107 | 81 | /** |
| 108 | 82 | * sdma_v6_0_init_microcode - load ucode images from disk |
| 109 | 83 | * |
| @@ -113,16 +87,10 @@ static void sdma_v6_0_destroy_inst_ctx(struct amdgpu_device *adev) · 3 unmodified lines | ||
| 113 | 87 | * the driver (not loaded into hw). |
| 114 | 88 | * Returns 0 on success, error on failure. |
| 115 | 89 | */ |
| 116 | − | |
| 117 | −// emulation only, won't work on real chip | |
| 118 | −// sdma 6.0.0 real chip need to use PSP to load firmware | |
| 119 | 90 | static int sdma_v6_0_init_microcode(struct amdgpu_device *adev) |
| 120 | 91 | { |
| 121 | 92 | char fw_name[30]; |
| 122 | 93 | char ucode_prefix[30]; |
| 123 | − int err = 0, i; | |
| 124 | − struct amdgpu_firmware_info *info = NULL; | |
| 125 | − const struct sdma_firmware_header_v2_0 *sdma_hdr; | |
| 126 | 94 | |
| 127 | 95 | DRM_DEBUG("\n"); |
| 128 | 96 | |
| @@ -130,43 +98,7 @@ static int sdma_v6_0_init_microcode(struct amdgpu_device *adev) · 1 unmodified line | ||
| 130 | 98 | |
| 131 | 99 | snprintf(fw_name, sizeof(fw_name), "amdgpu/%s.bin", ucode_prefix); |
| 132 | 100 | |
| 133 | − err = request_firmware(&adev->sdma.instance[0].fw, fw_name, adev->dev); | |
| 134 | − if (err) | |
| 135 | − goto out; | |
| 136 | − | |
| 137 | − err = sdma_v6_0_init_inst_ctx(&adev->sdma.instance[0]); | |
| 138 | − if (err) | |
| 139 | − goto out; | |
| 140 | − | |
| 141 | − for (i = 1; i < adev->sdma.num_instances; i++) { | |
| 142 | − memcpy((void*)&adev->sdma.instance[i], | |
| 143 | − (void*)&adev->sdma.instance[0], | |
| 144 | − sizeof(struct amdgpu_sdma_instance)); | |
| 145 | − } | |
| 146 | − | |
| 147 | − DRM_DEBUG("psp_load == '%s'\n", | |
| 148 | − adev->firmware.load_type == AMDGPU_FW_LOAD_PSP ? "true" : "false"); | |
| 149 | − | |
| 150 | − if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { | |
| 151 | − sdma_hdr = (const struct sdma_firmware_header_v2_0 *)adev->sdma.instance[0].fw->data; | |
| 152 | − info = &adev->firmware.ucode[AMDGPU_UCODE_ID_SDMA_UCODE_TH0]; | |
| 153 | − info->ucode_id = AMDGPU_UCODE_ID_SDMA_UCODE_TH0; | |
| 154 | − info->fw = adev->sdma.instance[0].fw; | |
| 155 | − adev->firmware.fw_size += | |
| 156 | − ALIGN(le32_to_cpu(sdma_hdr->ctx_ucode_size_bytes), PAGE_SIZE); | |
| 157 | − info = &adev->firmware.ucode[AMDGPU_UCODE_ID_SDMA_UCODE_TH1]; | |
| 158 | − info->ucode_id = AMDGPU_UCODE_ID_SDMA_UCODE_TH1; | |
| 159 | − info->fw = adev->sdma.instance[0].fw; | |
| 160 | − adev->firmware.fw_size += | |
| 161 | − ALIGN(le32_to_cpu(sdma_hdr->ctl_ucode_size_bytes), PAGE_SIZE); | |
| 162 | − } | |
| 163 | − | |
| 164 | −out: | |
| 165 | − if (err) { | |
| 166 | − DRM_ERROR("sdma_v6_0: Failed to load firmware \"%s\"\n", fw_name); | |
| 167 | − sdma_v6_0_destroy_inst_ctx(adev); | |
| 168 | − } | |
| 169 | − return err; | |
| 101 | + return amdgpu_sdma_init_microcode(adev, fw_name, 0, true); | |
| 170 | 102 | } |
| 171 | 103 | |
| 172 | 104 | static unsigned sdma_v6_0_ring_init_cond_exec(struct amdgpu_ring *ring) |
| @@ -559,7 +491,8 @@ static int sdma_v6_0_gfx_resume(struct amdgpu_device *adev) · 386 unmodified lines | ||
| 559 | 491 | for (i = 0; i < adev->sdma.num_instances; i++) { |
| 560 | 492 | ring = &adev->sdma.instance[i].ring; |
| 561 | 493 | |
| 562 | − WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_SEM_WAIT_FAIL_TIMER_CNTL), 0); | |
| 494 | + if (!amdgpu_sriov_vf(adev)) | |
| 495 | + WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_SEM_WAIT_FAIL_TIMER_CNTL), 0); | |
| 563 | 496 | |
| 564 | 497 | /* Set ring buffer size in dwords */ |
| 565 | 498 | rb_bufsz = order_base_2(ring->ring_size / 4); |
| @@ -593,7 +526,10 @@ static int sdma_v6_0_gfx_resume(struct amdgpu_device *adev) · 27 unmodified lines | ||
| 593 | 526 | lower_32_bits(ring->rptr_gpu_addr) & 0xFFFFFFFC); |
| 594 | 527 | |
| 595 | 528 | rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_QUEUE0_RB_CNTL, RPTR_WRITEBACK_ENABLE, 1); |
| 596 | − rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_QUEUE0_RB_CNTL, WPTR_POLL_ENABLE, 0); | |
| 529 | + if (amdgpu_sriov_vf(adev)) | |
| 530 | + rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_QUEUE0_RB_CNTL, WPTR_POLL_ENABLE, 1); | |
| 531 | + else | |
| 532 | + rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_QUEUE0_RB_CNTL, WPTR_POLL_ENABLE, 0); | |
| 597 | 533 | rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_QUEUE0_RB_CNTL, F32_WPTR_POLL_ENABLE, 1); |
| 598 | 534 | |
| 599 | 535 | WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_BASE), ring->gpu_addr >> 8); |
| @@ -1365,19 +1301,16 @@ static int sdma_v6_0_sw_fini(void *handle) · 765 unmodified lines | ||
| 1365 | 1301 | for (i = 0; i < adev->sdma.num_instances; i++) |
| 1366 | 1302 | amdgpu_ring_fini(&adev->sdma.instance[i].ring); |
| 1367 | 1303 | |
| 1368 | − sdma_v6_0_destroy_inst_ctx(adev); | |
| 1304 | + amdgpu_sdma_destroy_inst_ctx(adev, true); | |
| 1369 | 1305 | |
| 1370 | 1306 | return 0; |
| 1371 | 1307 | } |
| 1372 | 1308 | |
| 1373 | 1309 | static int sdma_v6_0_hw_init(void *handle) |
| 1374 | 1310 | { |
| 1375 | − int r; | |
| 1376 | 1311 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
| 1377 | 1312 | |
| 1378 | − r = sdma_v6_0_start(adev); | |
| 1379 | − | |
| 1380 | − return r; | |
| 1313 | + return sdma_v6_0_start(adev); | |
| 1381 | 1314 | } |
| 1382 | 1315 | |
| 1383 | 1316 | static int sdma_v6_0_hw_fini(void *handle) |
| @@ -0,0 +1,303 @@ | ||
| 1 | +/* | |
| 2 | + * Copyright 2021 Advanced Micro Devices, Inc. | |
| 3 | + * | |
| 4 | + * Permission is hereby granted, free of charge, to any person obtaining a | |
| 5 | + * copy of this software and associated documentation files (the "Software"), | |
| 6 | + * to deal in the Software without restriction, including without limitation | |
| 7 | + * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
| 8 | + * and/or sell copies of the Software, and to permit persons to whom the | |
| 9 | + * Software is furnished to do so, subject to the following conditions: | |
| 10 | + * | |
| 11 | + * The above copyright notice and this permission notice shall be included in | |
| 12 | + * all copies or substantial portions of the Software. | |
| 13 | + * | |
| 14 | + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
| 15 | + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
| 16 | + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
| 17 | + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
| 18 | + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
| 19 | + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
| 20 | + * OTHER DEALINGS IN THE SOFTWARE. | |
| 21 | + * | |
| 22 | + */ | |
| 23 | + | |
| 24 | +#include "sienna_cichlid.h" | |
| 25 | +#include "amdgpu_reset.h" | |
| 26 | +#include "amdgpu_amdkfd.h" | |
| 27 | +#include "amdgpu_dpm.h" | |
| 28 | +#include "amdgpu_job.h" | |
| 29 | +#include "amdgpu_ring.h" | |
| 30 | +#include "amdgpu_ras.h" | |
| 31 | +#include "amdgpu_psp.h" | |
| 32 | +#include "amdgpu_xgmi.h" | |
| 33 | + | |
| 34 | +static struct amdgpu_reset_handler * | |
| 35 | +sienna_cichlid_get_reset_handler(struct amdgpu_reset_control *reset_ctl, | |
| 36 | + struct amdgpu_reset_context *reset_context) | |
| 37 | +{ | |
| 38 | + struct amdgpu_reset_handler *handler; | |
| 39 | + struct amdgpu_device *adev = (struct amdgpu_device *)reset_ctl->handle; | |
| 40 | + | |
| 41 | + if (reset_context->method != AMD_RESET_METHOD_NONE) { | |
| 42 | + list_for_each_entry(handler, &reset_ctl->reset_handlers, | |
| 43 | + handler_list) { | |
| 44 | + if (handler->reset_method == reset_context->method) | |
| 45 | + return handler; | |
| 46 | + } | |
| 47 | + } else { | |
| 48 | + list_for_each_entry(handler, &reset_ctl->reset_handlers, | |
| 49 | + handler_list) { | |
| 50 | + if (handler->reset_method == AMD_RESET_METHOD_MODE2 && | |
| 51 | + adev->pm.fw_version >= 0x3a5500 && | |
| 52 | + !amdgpu_sriov_vf(adev)) { | |
| 53 | + reset_context->method = AMD_RESET_METHOD_MODE2; | |
| 54 | + return handler; | |
| 55 | + } | |
| 56 | + } | |
| 57 | + } | |
| 58 | + | |
| 59 | + return NULL; | |
| 60 | +} | |
| 61 | + | |
| 62 | +static int sienna_cichlid_mode2_suspend_ip(struct amdgpu_device *adev) | |
| 63 | +{ | |
| 64 | + int r, i; | |
| 65 | + | |
| 66 | + amdgpu_device_set_pg_state(adev, AMD_PG_STATE_UNGATE); | |
| 67 | + amdgpu_device_set_cg_state(adev, AMD_CG_STATE_UNGATE); | |
| 68 | + | |
| 69 | + for (i = adev->num_ip_blocks - 1; i >= 0; i--) { | |
| 70 | + if (!(adev->ip_blocks[i].version->type == | |
| 71 | + AMD_IP_BLOCK_TYPE_GFX || | |
| 72 | + adev->ip_blocks[i].version->type == | |
| 73 | + AMD_IP_BLOCK_TYPE_SDMA)) | |
| 74 | + continue; | |
| 75 | + | |
| 76 | + r = adev->ip_blocks[i].version->funcs->suspend(adev); | |
| 77 | + | |
| 78 | + if (r) { | |
| 79 | + dev_err(adev->dev, | |
| 80 | + "suspend of IP block <%s> failed %d\n", | |
| 81 | + adev->ip_blocks[i].version->funcs->name, r); | |
| 82 | + return r; | |
| 83 | + } | |
| 84 | + adev->ip_blocks[i].status.hw = false; | |
| 85 | + } | |
| 86 | + | |
| 87 | + return r; | |
| 88 | +} | |
| 89 | + | |
| 90 | +static int | |
| 91 | +sienna_cichlid_mode2_prepare_hwcontext(struct amdgpu_reset_control *reset_ctl, | |
| 92 | + struct amdgpu_reset_context *reset_context) | |
| 93 | +{ | |
| 94 | + int r = 0; | |
| 95 | + struct amdgpu_device *adev = (struct amdgpu_device *)reset_ctl->handle; | |
| 96 | + | |
| 97 | + if (!amdgpu_sriov_vf(adev)) { | |
| 98 | + if (adev->gfxhub.funcs->mode2_save_regs) | |
| 99 | + adev->gfxhub.funcs->mode2_save_regs(adev); | |
| 100 | + if (adev->gfxhub.funcs->halt) | |
| 101 | + adev->gfxhub.funcs->halt(adev); | |
| 102 | + r = sienna_cichlid_mode2_suspend_ip(adev); | |
| 103 | + } | |
| 104 | + | |
| 105 | + return r; | |
| 106 | +} | |
| 107 | + | |
| 108 | +static void sienna_cichlid_async_reset(struct work_struct *work) | |
| 109 | +{ | |
| 110 | + struct amdgpu_reset_handler *handler; | |
| 111 | + struct amdgpu_reset_control *reset_ctl = | |
| 112 | + container_of(work, struct amdgpu_reset_control, reset_work); | |
| 113 | + struct amdgpu_device *adev = (struct amdgpu_device *)reset_ctl->handle; | |
| 114 | + | |
| 115 | + list_for_each_entry(handler, &reset_ctl->reset_handlers, | |
| 116 | + handler_list) { | |
| 117 | + if (handler->reset_method == reset_ctl->active_reset) { | |
| 118 | + dev_dbg(adev->dev, "Resetting device\n"); | |
| 119 | + handler->do_reset(adev); | |
| 120 | + break; | |
| 121 | + } | |
| 122 | + } | |
| 123 | +} | |
| 124 | + | |
| 125 | +static int sienna_cichlid_mode2_reset(struct amdgpu_device *adev) | |
| 126 | +{ | |
| 127 | + /* disable BM */ | |
| 128 | + pci_clear_master(adev->pdev); | |
| 129 | + return amdgpu_dpm_mode2_reset(adev); | |
| 130 | +} | |
| 131 | + | |
| 132 | +static int | |
| 133 | +sienna_cichlid_mode2_perform_reset(struct amdgpu_reset_control *reset_ctl, | |
| 134 | + struct amdgpu_reset_context *reset_context) | |
| 135 | +{ | |
| 136 | + struct amdgpu_device *adev = (struct amdgpu_device *)reset_ctl->handle; | |
| 137 | + int r; | |
| 138 | + | |
| 139 | + r = sienna_cichlid_mode2_reset(adev); | |
| 140 | + if (r) { | |
| 141 | + dev_err(adev->dev, | |
| 142 | + "ASIC reset failed with error, %d ", r); | |
| 143 | + } | |
| 144 | + return r; | |
| 145 | +} | |
| 146 | + | |
| 147 | +static int sienna_cichlid_mode2_restore_ip(struct amdgpu_device *adev) | |
| 148 | +{ | |
| 149 | + int i, r; | |
| 150 | + struct psp_context *psp = &adev->psp; | |
| 151 | + | |
| 152 | + r = psp_rlc_autoload_start(psp); | |
| 153 | + if (r) { | |
| 154 | + dev_err(adev->dev, "Failed to start rlc autoload\n"); | |
| 155 | + return r; | |
| 156 | + } | |
| 157 | + | |
| 158 | + /* Reinit GFXHUB */ | |
| 159 | + if (adev->gfxhub.funcs->mode2_restore_regs) | |
| 160 | + adev->gfxhub.funcs->mode2_restore_regs(adev); | |
| 161 | + adev->gfxhub.funcs->init(adev); | |
| 162 | + r = adev->gfxhub.funcs->gart_enable(adev); | |
| 163 | + if (r) { | |
| 164 | + dev_err(adev->dev, "GFXHUB gart reenable failed after reset\n"); | |
| 165 | + return r; | |
| 166 | + } | |
| 167 | + | |
| 168 | + for (i = 0; i < adev->num_ip_blocks; i++) { | |
| 169 | + if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_IH) { | |
| 170 | + r = adev->ip_blocks[i].version->funcs->resume(adev); | |
| 171 | + if (r) { | |
| 172 | + dev_err(adev->dev, | |
| 173 | + "resume of IP block <%s> failed %d\n", | |
| 174 | + adev->ip_blocks[i].version->funcs->name, r); | |
| 175 | + return r; | |
| 176 | + } | |
| 177 | + | |
| 178 | + adev->ip_blocks[i].status.hw = true; | |
| 179 | + } | |
| 180 | + } | |
| 181 | + | |
| 182 | + for (i = 0; i < adev->num_ip_blocks; i++) { | |
| 183 | + if (!(adev->ip_blocks[i].version->type == | |
| 184 | + AMD_IP_BLOCK_TYPE_GFX || | |
| 185 | + adev->ip_blocks[i].version->type == | |
| 186 | + AMD_IP_BLOCK_TYPE_SDMA)) | |
| 187 | + continue; | |
| 188 | + r = adev->ip_blocks[i].version->funcs->resume(adev); | |
| 189 | + if (r) { | |
| 190 | + dev_err(adev->dev, | |
| 191 | + "resume of IP block <%s> failed %d\n", | |
| 192 | + adev->ip_blocks[i].version->funcs->name, r); | |
| 193 | + return r; | |
| 194 | + } | |
| 195 | + | |
| 196 | + adev->ip_blocks[i].status.hw = true; | |
| 197 | + } | |
| 198 | + | |
| 199 | + for (i = 0; i < adev->num_ip_blocks; i++) { | |
| 200 | + if (!(adev->ip_blocks[i].version->type == | |
| 201 | + AMD_IP_BLOCK_TYPE_GFX || | |
| 202 | + adev->ip_blocks[i].version->type == | |
| 203 | + AMD_IP_BLOCK_TYPE_SDMA)) | |
| 204 | + continue; | |
| 205 | + | |
| 206 | + if (adev->ip_blocks[i].version->funcs->late_init) { | |
| 207 | + r = adev->ip_blocks[i].version->funcs->late_init( | |
| 208 | + (void *)adev); | |
| 209 | + if (r) { | |
| 210 | + dev_err(adev->dev, | |
| 211 | + "late_init of IP block <%s> failed %d after reset\n", | |
| 212 | + adev->ip_blocks[i].version->funcs->name, | |
| 213 | + r); | |
| 214 | + return r; | |
| 215 | + } | |
| 216 | + } | |
| 217 | + adev->ip_blocks[i].status.late_initialized = true; | |
| 218 | + } | |
| 219 | + | |
| 220 | + amdgpu_device_set_cg_state(adev, AMD_CG_STATE_GATE); | |
| 221 | + amdgpu_device_set_pg_state(adev, AMD_PG_STATE_GATE); | |
| 222 | + | |
| 223 | + return r; | |
| 224 | +} | |
| 225 | + | |
| 226 | +static int | |
| 227 | +sienna_cichlid_mode2_restore_hwcontext(struct amdgpu_reset_control *reset_ctl, | |
| 228 | + struct amdgpu_reset_context *reset_context) | |
| 229 | +{ | |
| 230 | + int r; | |
| 231 | + struct amdgpu_device *tmp_adev = (struct amdgpu_device *)reset_ctl->handle; | |
| 232 | + | |
| 233 | + dev_info(tmp_adev->dev, | |
| 234 | + "GPU reset succeeded, trying to resume\n"); | |
| 235 | + r = sienna_cichlid_mode2_restore_ip(tmp_adev); | |
| 236 | + if (r) | |
| 237 | + goto end; | |
| 238 | + | |
| 239 | + /* | |
| 240 | + * Add this ASIC as tracked as reset was already | |
| 241 | + * complete successfully. | |
| 242 | + */ | |
| 243 | + amdgpu_register_gpu_instance(tmp_adev); | |
| 244 | + | |
| 245 | + /* Resume RAS */ | |
| 246 | + amdgpu_ras_resume(tmp_adev); | |
| 247 | + | |
| 248 | + amdgpu_irq_gpu_reset_resume_helper(tmp_adev); | |
| 249 | + | |
| 250 | + r = amdgpu_ib_ring_tests(tmp_adev); | |
| 251 | + if (r) { | |
| 252 | + dev_err(tmp_adev->dev, | |
| 253 | + "ib ring test failed (%d).\n", r); | |
| 254 | + r = -EAGAIN; | |
| 255 | + goto end; | |
| 256 | + } | |
| 257 | + | |
| 258 | +end: | |
| 259 | + if (r) | |
| 260 | + return -EAGAIN; | |
| 261 | + else | |
| 262 | + return r; | |
| 263 | +} | |
| 264 | + | |
| 265 | +static struct amdgpu_reset_handler sienna_cichlid_mode2_handler = { | |
| 266 | + .reset_method = AMD_RESET_METHOD_MODE2, | |
| 267 | + .prepare_env = NULL, | |
| 268 | + .prepare_hwcontext = sienna_cichlid_mode2_prepare_hwcontext, | |
| 269 | + .perform_reset = sienna_cichlid_mode2_perform_reset, | |
| 270 | + .restore_hwcontext = sienna_cichlid_mode2_restore_hwcontext, | |
| 271 | + .restore_env = NULL, | |
| 272 | + .do_reset = sienna_cichlid_mode2_reset, | |
| 273 | +}; | |
| 274 | + | |
| 275 | +int sienna_cichlid_reset_init(struct amdgpu_device *adev) | |
| 276 | +{ | |
| 277 | + struct amdgpu_reset_control *reset_ctl; | |
| 278 | + | |
| 279 | + reset_ctl = kzalloc(sizeof(*reset_ctl), GFP_KERNEL); | |
| 280 | + if (!reset_ctl) | |
| 281 | + return -ENOMEM; | |
| 282 | + | |
| 283 | + reset_ctl->handle = adev; | |
| 284 | + reset_ctl->async_reset = sienna_cichlid_async_reset; | |
| 285 | + reset_ctl->active_reset = AMD_RESET_METHOD_NONE; | |
| 286 | + reset_ctl->get_reset_handler = sienna_cichlid_get_reset_handler; | |
| 287 | + | |
| 288 | + INIT_LIST_HEAD(&reset_ctl->reset_handlers); | |
| 289 | + INIT_WORK(&reset_ctl->reset_work, reset_ctl->async_reset); | |
| 290 | + /* Only mode2 is handled through reset control now */ | |
| 291 | + amdgpu_reset_add_handler(reset_ctl, &sienna_cichlid_mode2_handler); | |
| 292 | + | |
| 293 | + adev->reset_cntl = reset_ctl; | |
| 294 | + | |
| 295 | + return 0; | |
| 296 | +} | |
| 297 | + | |
| 298 | +int sienna_cichlid_reset_fini(struct amdgpu_device *adev) | |
| 299 | +{ | |
| 300 | + kfree(adev->reset_cntl); | |
| 301 | + adev->reset_cntl = NULL; | |
| 302 | + return 0; | |
| 303 | +} | |
| @@ -1,5 +1,5 @@ | ||
| 1 | 1 | /* |
| 2 | − * Copyright 2015 Advanced Micro Devices, Inc. | |
| 2 | + * Copyright 2021 Advanced Micro Devices, Inc. | |
| 3 | 3 | * |
| 4 | 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 5 | 5 | * copy of this software and associated documentation files (the "Software"), |
| @@ -19,16 +19,14 @@ · 13 unmodified lines | ||
| 19 | 19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
| 20 | 20 | * OTHER DEALINGS IN THE SOFTWARE. |
| 21 | 21 | * |
| 22 | − * Authors: AMD | |
| 23 | − * | |
| 24 | 22 | */ |
| 25 | 23 | |
| 26 | −#ifndef DML_WRAPPER_H_ | |
| 27 | −#define DML_WRAPPER_H_ | |
| 24 | +#ifndef __SIENNA_CICHLID_H__ | |
| 25 | +#define __SIENNA_CICHLID_H__ | |
| 28 | 26 | |
| 29 | −#include "dc.h" | |
| 30 | −#include "dml/display_mode_vba.h" | |
| 27 | +#include "amdgpu.h" | |
| 31 | 28 | |
| 32 | −bool dml_validate(struct dc *dc, struct dc_state *context, bool fast_validate); | |
| 29 | +int sienna_cichlid_reset_init(struct amdgpu_device *adev); | |
| 30 | +int sienna_cichlid_reset_fini(struct amdgpu_device *adev); | |
| 33 | 31 | |
| 34 | 32 | #endif |
| @@ -179,7 +179,7 @@ void soc21_grbm_select(struct amdgpu_device *adev, · 178 unmodified lines | ||
| 179 | 179 | grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, VMID, vmid); |
| 180 | 180 | grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, QUEUEID, queue); |
| 181 | 181 | |
| 182 | − WREG32(SOC15_REG_OFFSET(GC, 0, regGRBM_GFX_CNTL), grbm_gfx_cntl); | |
| 182 | + WREG32_SOC15(GC, 0, regGRBM_GFX_CNTL, grbm_gfx_cntl); | |
| 183 | 183 | } |
| 184 | 184 | |
| 185 | 185 | static void soc21_vga_set_state(struct amdgpu_device *adev, bool state) |
| @@ -583,6 +583,10 @@ static int soc21_common_early_init(void *handle) · 397 unmodified lines | ||
| 583 | 583 | AMD_PG_SUPPORT_JPEG | |
| 584 | 584 | AMD_PG_SUPPORT_ATHUB | |
| 585 | 585 | AMD_PG_SUPPORT_MMHUB; |
| 586 | + if (amdgpu_sriov_vf(adev)) { | |
| 587 | + adev->cg_flags = 0; | |
| 588 | + adev->pg_flags = 0; | |
| 589 | + } | |
| 586 | 590 | adev->external_rev_id = adev->rev_id + 0x1; // TODO: need update |
| 587 | 591 | break; |
| 588 | 592 | case IP_VERSION(11, 0, 2): |
| @@ -629,6 +633,19 @@ static int soc21_common_early_init(void *handle) · 40 unmodified lines | ||
| 629 | 633 | AMD_PG_SUPPORT_JPEG; |
| 630 | 634 | adev->external_rev_id = adev->rev_id + 0x1; |
| 631 | 635 | break; |
| 636 | + case IP_VERSION(11, 0, 3): | |
| 637 | + adev->cg_flags = AMD_CG_SUPPORT_VCN_MGCG | | |
| 638 | + AMD_CG_SUPPORT_JPEG_MGCG; | |
| 639 | + adev->pg_flags = AMD_PG_SUPPORT_VCN | | |
| 640 | + AMD_PG_SUPPORT_VCN_DPG | | |
| 641 | + AMD_PG_SUPPORT_JPEG; | |
| 642 | + if (amdgpu_sriov_vf(adev)) { | |
| 643 | + /* hypervisor control CG and PG enablement */ | |
| 644 | + adev->cg_flags = 0; | |
| 645 | + adev->pg_flags = 0; | |
| 646 | + } | |
| 647 | + adev->external_rev_id = adev->rev_id + 0x20; | |
| 648 | + break; | |
| 632 | 649 | default: |
| 633 | 650 | /* FIXME: not supported yet */ |
| 634 | 651 | return -EINVAL; |
| @@ -452,41 +452,47 @@ static void umc_v6_7_query_ras_error_count(struct amdgpu_device *adev, · 451 unmodified lines | ||
| 452 | 452 | |
| 453 | 453 | static void umc_v6_7_query_error_address(struct amdgpu_device *adev, |
| 454 | 454 | struct ras_err_data *err_data, |
| 455 | − uint32_t umc_reg_offset, | |
| 456 | − uint32_t ch_inst, | |
| 457 | − uint32_t umc_inst) | |
| 455 | + uint32_t umc_reg_offset, uint32_t ch_inst, | |
| 456 | + uint32_t umc_inst, uint64_t mca_addr) | |
| 458 | 457 | { |
| 459 | 458 | uint32_t mc_umc_status_addr; |
| 460 | 459 | uint32_t channel_index; |
| 461 | − uint64_t mc_umc_status, mc_umc_addrt0; | |
| 460 | + uint64_t mc_umc_status = 0, mc_umc_addrt0; | |
| 462 | 461 | uint64_t err_addr, soc_pa, retired_page, column; |
| 463 | 462 | |
| 464 | − mc_umc_status_addr = | |
| 465 | − SOC15_REG_OFFSET(UMC, 0, regMCA_UMC_UMC0_MCUMC_STATUST0); | |
| 466 | − mc_umc_addrt0 = | |
| 467 | − SOC15_REG_OFFSET(UMC, 0, regMCA_UMC_UMC0_MCUMC_ADDRT0); | |
| 463 | + if (mca_addr == UMC_INVALID_ADDR) { | |
| 464 | + mc_umc_status_addr = | |
| 465 | + SOC15_REG_OFFSET(UMC, 0, regMCA_UMC_UMC0_MCUMC_STATUST0); | |
| 466 | + mc_umc_addrt0 = | |
| 467 | + SOC15_REG_OFFSET(UMC, 0, regMCA_UMC_UMC0_MCUMC_ADDRT0); | |
| 468 | 468 | |
| 469 | − mc_umc_status = RREG64_PCIE((mc_umc_status_addr + umc_reg_offset) * 4); | |
| 469 | + mc_umc_status = RREG64_PCIE((mc_umc_status_addr + umc_reg_offset) * 4); | |
| 470 | 470 | |
| 471 | − if (mc_umc_status == 0) | |
| 472 | − return; | |
| 471 | + if (mc_umc_status == 0) | |
| 472 | + return; | |
| 473 | 473 | |
| 474 | − if (!err_data->err_addr) { | |
| 475 | − /* clear umc status */ | |
| 476 | − WREG64_PCIE((mc_umc_status_addr + umc_reg_offset) * 4, 0x0ULL); | |
| 477 | − return; | |
| 474 | + if (!err_data->err_addr) { | |
| 475 | + /* clear umc status */ | |
| 476 | + WREG64_PCIE((mc_umc_status_addr + umc_reg_offset) * 4, 0x0ULL); | |
| 477 | + return; | |
| 478 | + } | |
| 478 | 479 | } |
| 479 | 480 | |
| 480 | 481 | channel_index = |
| 481 | 482 | adev->umc.channel_idx_tbl[umc_inst * adev->umc.channel_inst_num + ch_inst]; |
| 482 | 483 | |
| 483 | 484 | /* calculate error address if ue/ce error is detected */ |
| 484 | − if (REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, Val) == 1 && | |
| 485 | + if ((REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, Val) == 1 && | |
| 485 | 486 | (REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, UECC) == 1 || |
| 486 | − REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, CECC) == 1)) { | |
| 487 | − | |
| 488 | − err_addr = RREG64_PCIE((mc_umc_addrt0 + umc_reg_offset) * 4); | |
| 489 | − err_addr = REG_GET_FIELD(err_addr, MCA_UMC_UMC0_MCUMC_ADDRT0, ErrorAddr); | |
| 487 | + REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, CECC) == 1)) || | |
| 488 | + mca_addr != UMC_INVALID_ADDR) { | |
| 489 | + if (mca_addr == UMC_INVALID_ADDR) { | |
| 490 | + err_addr = RREG64_PCIE((mc_umc_addrt0 + umc_reg_offset) * 4); | |
| 491 | + err_addr = | |
| 492 | + REG_GET_FIELD(err_addr, MCA_UMC_UMC0_MCUMC_ADDRT0, ErrorAddr); | |
| 493 | + } else { | |
| 494 | + err_addr = mca_addr; | |
| 495 | + } | |
| 490 | 496 | |
| 491 | 497 | /* translate umc channel address to soc pa, 3 parts are included */ |
| 492 | 498 | soc_pa = ADDR_OF_8KB_BLOCK(err_addr) | |
| @@ -501,7 +507,8 @@ static void umc_v6_7_query_error_address(struct amdgpu_device *adev, · 8 unmodified lines | ||
| 501 | 507 | |
| 502 | 508 | /* we only save ue error information currently, ce is skipped */ |
| 503 | 509 | if (REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, UECC) |
| 504 | − == 1) { | |
| 510 | + == 1 || | |
| 511 | + mca_addr != UMC_INVALID_ADDR) { | |
| 505 | 512 | /* loop for all possibilities of [C4 C3 C2] */ |
| 506 | 513 | for (column = 0; column < UMC_V6_7_NA_MAP_PA_NUM; column++) { |
| 507 | 514 | retired_page = soc_pa | (column << UMC_V6_7_PA_C2_BIT); |
| @@ -519,7 +526,8 @@ static void umc_v6_7_query_error_address(struct amdgpu_device *adev, · 11 unmodified lines | ||
| 519 | 526 | } |
| 520 | 527 | |
| 521 | 528 | /* clear umc status */ |
| 522 | − WREG64_PCIE((mc_umc_status_addr + umc_reg_offset) * 4, 0x0ULL); | |
| 529 | + if (mca_addr == UMC_INVALID_ADDR) | |
| 530 | + WREG64_PCIE((mc_umc_status_addr + umc_reg_offset) * 4, 0x0ULL); | |
| 523 | 531 | } |
| 524 | 532 | |
| 525 | 533 | static void umc_v6_7_query_ras_error_address(struct amdgpu_device *adev, |
| @@ -540,9 +548,8 @@ static void umc_v6_7_query_ras_error_address(struct amdgpu_device *adev, · 14 unmodified lines | ||
| 540 | 548 | ch_inst); |
| 541 | 549 | umc_v6_7_query_error_address(adev, |
| 542 | 550 | err_data, |
| 543 | − umc_reg_offset, | |
| 544 | − ch_inst, | |
| 545 | − umc_inst); | |
| 551 | + umc_reg_offset, ch_inst, | |
| 552 | + umc_inst, UMC_INVALID_ADDR); | |
| 546 | 553 | } |
| 547 | 554 | } |
| 548 | 555 | |
| @@ -583,4 +590,5 @@ struct amdgpu_umc_ras umc_v6_7_ras = { · 34 unmodified lines | ||
| 583 | 590 | .query_ras_poison_mode = umc_v6_7_query_ras_poison_mode, |
| 584 | 591 | .ecc_info_query_ras_error_count = umc_v6_7_ecc_info_query_ras_error_count, |
| 585 | 592 | .ecc_info_query_ras_error_address = umc_v6_7_ecc_info_query_ras_error_address, |
| 593 | + .convert_ras_error_address = umc_v6_7_query_error_address, | |
| 586 | 594 | }; |
| @@ -101,22 +101,16 @@ static void umc_v8_10_query_correctable_error_count(struct amdgpu_device *adev, · 100 unmodified lines | ||
| 101 | 101 | uint32_t umc_reg_offset, |
| 102 | 102 | unsigned long *error_count) |
| 103 | 103 | { |
| 104 | − uint32_t ecc_err_cnt, ecc_err_cnt_addr; | |
| 105 | 104 | uint64_t mc_umc_status; |
| 106 | 105 | uint32_t mc_umc_status_addr; |
| 107 | 106 | |
| 108 | 107 | /* UMC 8_10 registers */ |
| 109 | − ecc_err_cnt_addr = | |
| 110 | − SOC15_REG_OFFSET(UMC, 0, regUMCCH0_0_GeccErrCnt); | |
| 111 | 108 | mc_umc_status_addr = |
| 112 | 109 | SOC15_REG_OFFSET(UMC, 0, regMCA_UMC_UMC0_MCUMC_STATUST0); |
| 113 | 110 | |
| 114 | − ecc_err_cnt = RREG32_PCIE((ecc_err_cnt_addr + umc_reg_offset) * 4); | |
| 115 | − *error_count += | |
| 116 | − (REG_GET_FIELD(ecc_err_cnt, UMCCH0_0_GeccErrCnt, GeccErrCnt) - | |
| 117 | − UMC_V8_10_CE_CNT_INIT); | |
| 118 | − | |
| 119 | − /* Check for SRAM correctable error, MCUMC_STATUS is a 64 bit register */ | |
| 111 | + /* Rely on MCUMC_STATUS for correctable error counter | |
| 112 | + * MCUMC_STATUS is a 64 bit register | |
| 113 | + */ | |
| 120 | 114 | mc_umc_status = RREG64_PCIE((mc_umc_status_addr + umc_reg_offset) * 4); |
| 121 | 115 | if (REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, Val) == 1 && |
| 122 | 116 | REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, CECC) == 1) |
| @@ -1761,21 +1761,23 @@ static const struct amdgpu_ring_funcs vcn_v3_0_dec_sw_ring_vm_funcs = { · 1760 unmodified lines | ||
| 1761 | 1761 | .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper, |
| 1762 | 1762 | }; |
| 1763 | 1763 | |
| 1764 | −static int vcn_v3_0_limit_sched(struct amdgpu_cs_parser *p) | |
| 1764 | +static int vcn_v3_0_limit_sched(struct amdgpu_cs_parser *p, | |
| 1765 | + struct amdgpu_job *job) | |
| 1765 | 1766 | { |
| 1766 | 1767 | struct drm_gpu_scheduler **scheds; |
| 1767 | 1768 | |
| 1768 | 1769 | /* The create msg must be in the first IB submitted */ |
| 1769 | − if (atomic_read(&p->entity->fence_seq)) | |
| 1770 | + if (atomic_read(&job->base.entity->fence_seq)) | |
| 1770 | 1771 | return -EINVAL; |
| 1771 | 1772 | |
| 1772 | 1773 | scheds = p->adev->gpu_sched[AMDGPU_HW_IP_VCN_DEC] |
| 1773 | 1774 | [AMDGPU_RING_PRIO_DEFAULT].sched; |
| 1774 | − drm_sched_entity_modify_sched(p->entity, scheds, 1); | |
| 1775 | + drm_sched_entity_modify_sched(job->base.entity, scheds, 1); | |
| 1775 | 1776 | return 0; |
| 1776 | 1777 | } |
| 1777 | 1778 | |
| 1778 | −static int vcn_v3_0_dec_msg(struct amdgpu_cs_parser *p, uint64_t addr) | |
| 1779 | +static int vcn_v3_0_dec_msg(struct amdgpu_cs_parser *p, struct amdgpu_job *job, | |
| 1780 | + uint64_t addr) | |
| 1779 | 1781 | { |
| 1780 | 1782 | struct ttm_operation_ctx ctx = { false, false }; |
| 1781 | 1783 | struct amdgpu_bo_va_mapping *map; |
| @@ -1846,7 +1848,7 @@ static int vcn_v3_0_dec_msg(struct amdgpu_cs_parser *p, uint64_t addr) · 64 unmodified lines | ||
| 1846 | 1848 | if (create[0] == 0x7 || create[0] == 0x10 || create[0] == 0x11) |
| 1847 | 1849 | continue; |
| 1848 | 1850 | |
| 1849 | − r = vcn_v3_0_limit_sched(p); | |
| 1851 | + r = vcn_v3_0_limit_sched(p, job); | |
| 1850 | 1852 | if (r) |
| 1851 | 1853 | goto out; |
| 1852 | 1854 | } |
| @@ -1860,7 +1862,7 @@ static int vcn_v3_0_ring_patch_cs_in_place(struct amdgpu_cs_parser *p, · 7 unmodified lines | ||
| 1860 | 1862 | struct amdgpu_job *job, |
| 1861 | 1863 | struct amdgpu_ib *ib) |
| 1862 | 1864 | { |
| 1863 | − struct amdgpu_ring *ring = to_amdgpu_ring(p->entity->rq->sched); | |
| 1865 | + struct amdgpu_ring *ring = amdgpu_job_ring(job); | |
| 1864 | 1866 | uint32_t msg_lo = 0, msg_hi = 0; |
| 1865 | 1867 | unsigned i; |
| 1866 | 1868 | int r; |
| @@ -1879,7 +1881,8 @@ static int vcn_v3_0_ring_patch_cs_in_place(struct amdgpu_cs_parser *p, · 12 unmodified lines | ||
| 1879 | 1881 | msg_hi = val; |
| 1880 | 1882 | } else if (reg == PACKET0(p->adev->vcn.internal.cmd, 0) && |
| 1881 | 1883 | val == 0) { |
| 1882 | − r = vcn_v3_0_dec_msg(p, ((u64)msg_hi) << 32 | msg_lo); | |
| 1884 | + r = vcn_v3_0_dec_msg(p, job, | |
| 1885 | + ((u64)msg_hi) << 32 | msg_lo); | |
| 1883 | 1886 | if (r) |
| 1884 | 1887 | return r; |
| 1885 | 1888 | } |
| @@ -30,6 +30,7 @@ · 29 unmodified lines | ||
| 30 | 30 | #include "soc15d.h" |
| 31 | 31 | #include "soc15_hw_ip.h" |
| 32 | 32 | #include "vcn_v2_0.h" |
| 33 | +#include "mmsch_v4_0.h" | |
| 33 | 34 | |
| 34 | 35 | #include "vcn/vcn_4_0_0_offset.h" |
| 35 | 36 | #include "vcn/vcn_4_0_0_sh_mask.h" |
| @@ -45,6 +46,8 @@ · 9 unmodified lines | ||
| 45 | 46 | #define VCN_VID_SOC_ADDRESS_2_0 0x1fb00 |
| 46 | 47 | #define VCN1_VID_SOC_ADDRESS_3_0 0x48300 |
| 47 | 48 | |
| 49 | +#define VCN_HARVEST_MMSCH 0 | |
| 50 | + | |
| 48 | 51 | #define RDECODE_MSG_CREATE 0x00000000 |
| 49 | 52 | #define RDECODE_MESSAGE_CREATE 0x00000001 |
| 50 | 53 | |
| @@ -53,12 +56,14 @@ static int amdgpu_ih_clientid_vcns[] = { · 2 unmodified lines | ||
| 53 | 56 | SOC15_IH_CLIENTID_VCN1 |
| 54 | 57 | }; |
| 55 | 58 | |
| 59 | +static int vcn_v4_0_start_sriov(struct amdgpu_device *adev); | |
| 56 | 60 | static void vcn_v4_0_set_unified_ring_funcs(struct amdgpu_device *adev); |
| 57 | 61 | static void vcn_v4_0_set_irq_funcs(struct amdgpu_device *adev); |
| 58 | 62 | static int vcn_v4_0_set_powergating_state(void *handle, |
| 59 | 63 | enum amd_powergating_state state); |
| 60 | 64 | static int vcn_v4_0_pause_dpg_mode(struct amdgpu_device *adev, |
| 61 | 65 | int inst_idx, struct dpg_pause_state *new_state); |
| 66 | +static void vcn_v4_0_unified_ring_set_wptr(struct amdgpu_ring *ring); | |
| 62 | 67 | |
| 63 | 68 | /** |
| 64 | 69 | * vcn_v4_0_early_init - set function pointers |
| @@ -71,6 +76,9 @@ static int vcn_v4_0_early_init(void *handle) · 6 unmodified lines | ||
| 71 | 76 | { |
| 72 | 77 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
| 73 | 78 | |
| 79 | + if (amdgpu_sriov_vf(adev)) | |
| 80 | + adev->vcn.harvest_config = VCN_HARVEST_MMSCH; | |
| 81 | + | |
| 74 | 82 | /* re-use enc ring as unified ring */ |
| 75 | 83 | adev->vcn.num_enc_rings = 1; |
| 76 | 84 | |
| @@ -92,6 +100,7 @@ static int vcn_v4_0_sw_init(void *handle) · 15 unmodified lines | ||
| 92 | 100 | struct amdgpu_ring *ring; |
| 93 | 101 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
| 94 | 102 | int i, r; |
| 103 | + int vcn_doorbell_index = 0; | |
| 95 | 104 | |
| 96 | 105 | r = amdgpu_vcn_sw_init(adev); |
| 97 | 106 | if (r) |
| @@ -103,6 +112,12 @@ static int vcn_v4_0_sw_init(void *handle) · 5 unmodified lines | ||
| 103 | 112 | if (r) |
| 104 | 113 | return r; |
| 105 | 114 | |
| 115 | + if (amdgpu_sriov_vf(adev)) { | |
| 116 | + vcn_doorbell_index = adev->doorbell_index.vcn.vcn_ring0_1 - MMSCH_DOORBELL_OFFSET; | |
| 117 | + /* get DWORD offset */ | |
| 118 | + vcn_doorbell_index = vcn_doorbell_index << 1; | |
| 119 | + } | |
| 120 | + | |
| 106 | 121 | for (i = 0; i < adev->vcn.num_vcn_inst; i++) { |
| 107 | 122 | volatile struct amdgpu_vcn4_fw_shared *fw_shared; |
| 108 | 123 | |
| @@ -119,7 +134,10 @@ static int vcn_v4_0_sw_init(void *handle) · 10 unmodified lines | ||
| 119 | 134 | |
| 120 | 135 | ring = &adev->vcn.inst[i].ring_enc[0]; |
| 121 | 136 | ring->use_doorbell = true; |
| 122 | − ring->doorbell_index = (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 2 + 8 * i; | |
| 137 | + if (amdgpu_sriov_vf(adev)) | |
| 138 | + ring->doorbell_index = vcn_doorbell_index + i * (adev->vcn.num_enc_rings + 1) + 1; | |
| 139 | + else | |
| 140 | + ring->doorbell_index = (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 2 + 8 * i; | |
| 123 | 141 | |
| 124 | 142 | sprintf(ring->name, "vcn_unified_%d", i); |
| 125 | 143 | |
| @@ -132,10 +150,23 @@ static int vcn_v4_0_sw_init(void *handle) · 6 unmodified lines | ||
| 132 | 150 | fw_shared->present_flag_0 = cpu_to_le32(AMDGPU_FW_SHARED_FLAG_0_UNIFIED_QUEUE); |
| 133 | 151 | fw_shared->sq.is_enabled = 1; |
| 134 | 152 | |
| 153 | + fw_shared->present_flag_0 |= cpu_to_le32(AMDGPU_VCN_SMU_DPM_INTERFACE_FLAG); | |
| 154 | + fw_shared->smu_dpm_interface.smu_interface_type = (adev->flags & AMD_IS_APU) ? | |
| 155 | + AMDGPU_VCN_SMU_DPM_INTERFACE_APU : AMDGPU_VCN_SMU_DPM_INTERFACE_DGPU; | |
| 156 | + | |
| 157 | + if (amdgpu_sriov_vf(adev)) | |
| 158 | + fw_shared->present_flag_0 |= cpu_to_le32(AMDGPU_VCN_VF_RB_SETUP_FLAG); | |
| 159 | + | |
| 135 | 160 | if (amdgpu_vcnfw_log) |
| 136 | 161 | amdgpu_vcn_fwlog_init(&adev->vcn.inst[i]); |
| 137 | 162 | } |
| 138 | 163 | |
| 164 | + if (amdgpu_sriov_vf(adev)) { | |
| 165 | + r = amdgpu_virt_alloc_mm_table(adev); | |
| 166 | + if (r) | |
| 167 | + return r; | |
| 168 | + } | |
| 169 | + | |
| 139 | 170 | if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) |
| 140 | 171 | adev->vcn.pause_dpg_mode = vcn_v4_0_pause_dpg_mode; |
| 141 | 172 | |
| @@ -169,6 +200,9 @@ static int vcn_v4_0_sw_fini(void *handle) · 27 unmodified lines | ||
| 169 | 200 | drm_dev_exit(idx); |
| 170 | 201 | } |
| 171 | 202 | |
| 203 | + if (amdgpu_sriov_vf(adev)) | |
| 204 | + amdgpu_virt_free_mm_table(adev); | |
| 205 | + | |
| 172 | 206 | r = amdgpu_vcn_suspend(adev); |
| 173 | 207 | if (r) |
| 174 | 208 | return r; |
| @@ -191,18 +225,42 @@ static int vcn_v4_0_hw_init(void *handle) · 16 unmodified lines | ||
| 191 | 225 | struct amdgpu_ring *ring; |
| 192 | 226 | int i, r; |
| 193 | 227 | |
| 194 | − for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { | |
| 195 | − if (adev->vcn.harvest_config & (1 << i)) | |
| 196 | − continue; | |
| 228 | + if (amdgpu_sriov_vf(adev)) { | |
| 229 | + r = vcn_v4_0_start_sriov(adev); | |
| 230 | + if (r) | |
| 231 | + goto done; | |
| 197 | 232 | |
| 198 | − ring = &adev->vcn.inst[i].ring_enc[0]; | |
| 233 | + for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { | |
| 234 | + if (adev->vcn.harvest_config & (1 << i)) | |
| 235 | + continue; | |
| 199 | 236 | |
| 200 | − adev->nbio.funcs->vcn_doorbell_range(adev, ring->use_doorbell, | |
| 201 | − ((adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 8 * i), i); | |
| 237 | + ring = &adev->vcn.inst[i].ring_enc[0]; | |
| 238 | + if (amdgpu_vcn_is_disabled_vcn(adev, VCN_ENCODE_RING, i)) { | |
| 239 | + ring->sched.ready = false; | |
| 240 | + ring->no_scheduler = true; | |
| 241 | + dev_info(adev->dev, "ring %s is disabled by hypervisor\n", ring->name); | |
| 242 | + } else { | |
| 243 | + ring->wptr = 0; | |
| 244 | + ring->wptr_old = 0; | |
| 245 | + vcn_v4_0_unified_ring_set_wptr(ring); | |
| 246 | + ring->sched.ready = true; | |
| 247 | + } | |
| 248 | + } | |
| 249 | + } else { | |
| 250 | + for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { | |
| 251 | + if (adev->vcn.harvest_config & (1 << i)) | |
| 252 | + continue; | |
| 202 | 253 | |
| 203 | − r = amdgpu_ring_test_helper(ring); | |
| 204 | − if (r) | |
| 205 | − goto done; | |
| 254 | + ring = &adev->vcn.inst[i].ring_enc[0]; | |
| 255 | + | |
| 256 | + adev->nbio.funcs->vcn_doorbell_range(adev, ring->use_doorbell, | |
| 257 | + ((adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 8 * i), i); | |
| 258 | + | |
| 259 | + r = amdgpu_ring_test_helper(ring); | |
| 260 | + if (r) | |
| 261 | + goto done; | |
| 262 | + | |
| 263 | + } | |
| 206 | 264 | } |
| 207 | 265 | |
| 208 | 266 | done: |
| @@ -230,12 +288,14 @@ static int vcn_v4_0_hw_fini(void *handle) · 21 unmodified lines | ||
| 230 | 288 | for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { |
| 231 | 289 | if (adev->vcn.harvest_config & (1 << i)) |
| 232 | 290 | continue; |
| 233 | − | |
| 234 | − if ((adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) || | |
| 291 | + if (!amdgpu_sriov_vf(adev)) { | |
| 292 | + if ((adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) || | |
| 235 | 293 | (adev->vcn.cur_state != AMD_PG_STATE_GATE && |
| 236 | 294 | RREG32_SOC15(VCN, i, regUVD_STATUS))) { |
| 237 | 295 | vcn_v4_0_set_powergating_state(adev, AMD_PG_STATE_GATE); |
| 296 | + } | |
| 238 | 297 | } |
| 298 | + | |
| 239 | 299 | } |
| 240 | 300 | |
| 241 | 301 | return 0; |
| @@ -1107,6 +1167,214 @@ static int vcn_v4_0_start(struct amdgpu_device *adev) · 865 unmodified lines | ||
| 1107 | 1167 | return 0; |
| 1108 | 1168 | } |
| 1109 | 1169 | |
| 1170 | +static int vcn_v4_0_start_sriov(struct amdgpu_device *adev) | |
| 1171 | +{ | |
| 1172 | + int i; | |
| 1173 | + struct amdgpu_ring *ring_enc; | |
| 1174 | + uint64_t cache_addr; | |
| 1175 | + uint64_t rb_enc_addr; | |
| 1176 | + uint64_t ctx_addr; | |
| 1177 | + uint32_t param, resp, expected; | |
| 1178 | + uint32_t offset, cache_size; | |
| 1179 | + uint32_t tmp, timeout; | |
| 1180 | + | |
| 1181 | + struct amdgpu_mm_table *table = &adev->virt.mm_table; | |
| 1182 | + uint32_t *table_loc; | |
| 1183 | + uint32_t table_size; | |
| 1184 | + uint32_t size, size_dw; | |
| 1185 | + uint32_t init_status; | |
| 1186 | + uint32_t enabled_vcn; | |
| 1187 | + | |
| 1188 | + struct mmsch_v4_0_cmd_direct_write | |
| 1189 | + direct_wt = { {0} }; | |
| 1190 | + struct mmsch_v4_0_cmd_direct_read_modify_write | |
| 1191 | + direct_rd_mod_wt = { {0} }; | |
| 1192 | + struct mmsch_v4_0_cmd_end end = { {0} }; | |
| 1193 | + struct mmsch_v4_0_init_header header; | |
| 1194 | + | |
| 1195 | + volatile struct amdgpu_vcn4_fw_shared *fw_shared; | |
| 1196 | + volatile struct amdgpu_fw_shared_rb_setup *rb_setup; | |
| 1197 | + | |
| 1198 | + direct_wt.cmd_header.command_type = | |
| 1199 | + MMSCH_COMMAND__DIRECT_REG_WRITE; | |
| 1200 | + direct_rd_mod_wt.cmd_header.command_type = | |
| 1201 | + MMSCH_COMMAND__DIRECT_REG_READ_MODIFY_WRITE; | |
| 1202 | + end.cmd_header.command_type = | |
| 1203 | + MMSCH_COMMAND__END; | |
| 1204 | + | |
| 1205 | + header.version = MMSCH_VERSION; | |
| 1206 | + header.total_size = sizeof(struct mmsch_v4_0_init_header) >> 2; | |
| 1207 | + for (i = 0; i < AMDGPU_MAX_VCN_INSTANCES; i++) { | |
| 1208 | + header.inst[i].init_status = 0; | |
| 1209 | + header.inst[i].table_offset = 0; | |
| 1210 | + header.inst[i].table_size = 0; | |
| 1211 | + } | |
| 1212 | + | |
| 1213 | + table_loc = (uint32_t *)table->cpu_addr; | |
| 1214 | + table_loc += header.total_size; | |
| 1215 | + for (i = 0; i < adev->vcn.num_vcn_inst; i++) { | |
| 1216 | + if (adev->vcn.harvest_config & (1 << i)) | |
| 1217 | + continue; | |
| 1218 | + | |
| 1219 | + table_size = 0; | |
| 1220 | + | |
| 1221 | + MMSCH_V4_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(VCN, i, | |
| 1222 | + regUVD_STATUS), | |
| 1223 | + ~UVD_STATUS__UVD_BUSY, UVD_STATUS__UVD_BUSY); | |
| 1224 | + | |
| 1225 | + cache_size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.fw->size + 4); | |
| 1226 | + | |
| 1227 | + if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { | |
| 1228 | + MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, | |
| 1229 | + regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), | |
| 1230 | + adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + i].tmr_mc_addr_lo); | |
| 1231 | + MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, | |
| 1232 | + regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), | |
| 1233 | + adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + i].tmr_mc_addr_hi); | |
| 1234 | + offset = 0; | |
| 1235 | + MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, | |
| 1236 | + regUVD_VCPU_CACHE_OFFSET0), | |
| 1237 | + 0); | |
| 1238 | + } else { | |
| 1239 | + MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, | |
| 1240 | + regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), | |
| 1241 | + lower_32_bits(adev->vcn.inst[i].gpu_addr)); | |
| 1242 | + MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, | |
| 1243 | + regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), | |
| 1244 | + upper_32_bits(adev->vcn.inst[i].gpu_addr)); | |
| 1245 | + offset = cache_size; | |
| 1246 | + MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, | |
| 1247 | + regUVD_VCPU_CACHE_OFFSET0), | |
| 1248 | + AMDGPU_UVD_FIRMWARE_OFFSET >> 3); | |
| 1249 | + } | |
| 1250 | + | |
| 1251 | + MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, | |
| 1252 | + regUVD_VCPU_CACHE_SIZE0), | |
| 1253 | + cache_size); | |
| 1254 | + | |
| 1255 | + cache_addr = adev->vcn.inst[i].gpu_addr + offset; | |
| 1256 | + MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, | |
| 1257 | + regUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW), | |
| 1258 | + lower_32_bits(cache_addr)); | |
| 1259 | + MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, | |
| 1260 | + regUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH), | |
| 1261 | + upper_32_bits(cache_addr)); | |
| 1262 | + MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, | |
| 1263 | + regUVD_VCPU_CACHE_OFFSET1), | |
| 1264 | + 0); | |
| 1265 | + MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, | |
| 1266 | + regUVD_VCPU_CACHE_SIZE1), | |
| 1267 | + AMDGPU_VCN_STACK_SIZE); | |
| 1268 | + | |
| 1269 | + cache_addr = adev->vcn.inst[i].gpu_addr + offset + | |
| 1270 | + AMDGPU_VCN_STACK_SIZE; | |
| 1271 | + MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, | |
| 1272 | + regUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW), | |
| 1273 | + lower_32_bits(cache_addr)); | |
| 1274 | + MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, | |
| 1275 | + regUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH), | |
| 1276 | + upper_32_bits(cache_addr)); | |
| 1277 | + MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, | |
| 1278 | + regUVD_VCPU_CACHE_OFFSET2), | |
| 1279 | + 0); | |
| 1280 | + MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, | |
| 1281 | + regUVD_VCPU_CACHE_SIZE2), | |
| 1282 | + AMDGPU_VCN_CONTEXT_SIZE); | |
| 1283 | + | |
| 1284 | + fw_shared = adev->vcn.inst[i].fw_shared.cpu_addr; | |
| 1285 | + rb_setup = &fw_shared->rb_setup; | |
| 1286 | + | |
| 1287 | + ring_enc = &adev->vcn.inst[i].ring_enc[0]; | |
| 1288 | + ring_enc->wptr = 0; | |
| 1289 | + rb_enc_addr = ring_enc->gpu_addr; | |
| 1290 | + | |
| 1291 | + rb_setup->is_rb_enabled_flags |= RB_ENABLED; | |
| 1292 | + rb_setup->rb_addr_lo = lower_32_bits(rb_enc_addr); | |
| 1293 | + rb_setup->rb_addr_hi = upper_32_bits(rb_enc_addr); | |
| 1294 | + rb_setup->rb_size = ring_enc->ring_size / 4; | |
| 1295 | + fw_shared->present_flag_0 |= cpu_to_le32(AMDGPU_VCN_VF_RB_SETUP_FLAG); | |
| 1296 | + | |
| 1297 | + MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, | |
| 1298 | + regUVD_LMI_VCPU_NC0_64BIT_BAR_LOW), | |
| 1299 | + lower_32_bits(adev->vcn.inst[i].fw_shared.gpu_addr)); | |
| 1300 | + MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, | |
| 1301 | + regUVD_LMI_VCPU_NC0_64BIT_BAR_HIGH), | |
| 1302 | + upper_32_bits(adev->vcn.inst[i].fw_shared.gpu_addr)); | |
| 1303 | + MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, | |
| 1304 | + regUVD_VCPU_NONCACHE_SIZE0), | |
| 1305 | + AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_vcn4_fw_shared))); | |
| 1306 | + | |
| 1307 | + /* add end packet */ | |
| 1308 | + MMSCH_V4_0_INSERT_END(); | |
| 1309 | + | |
| 1310 | + /* refine header */ | |
| 1311 | + header.inst[i].init_status = 0; | |
| 1312 | + header.inst[i].table_offset = header.total_size; | |
| 1313 | + header.inst[i].table_size = table_size; | |
| 1314 | + header.total_size += table_size; | |
| 1315 | + } | |
| 1316 | + | |
| 1317 | + /* Update init table header in memory */ | |
| 1318 | + size = sizeof(struct mmsch_v4_0_init_header); | |
| 1319 | + table_loc = (uint32_t *)table->cpu_addr; | |
| 1320 | + memcpy((void *)table_loc, &header, size); | |
| 1321 | + | |
| 1322 | + /* message MMSCH (in VCN[0]) to initialize this client | |
| 1323 | + * 1, write to mmsch_vf_ctx_addr_lo/hi register with GPU mc addr | |
| 1324 | + * of memory descriptor location | |
| 1325 | + */ | |
| 1326 | + ctx_addr = table->gpu_addr; | |
| 1327 | + WREG32_SOC15(VCN, 0, regMMSCH_VF_CTX_ADDR_LO, lower_32_bits(ctx_addr)); | |
| 1328 | + WREG32_SOC15(VCN, 0, regMMSCH_VF_CTX_ADDR_HI, upper_32_bits(ctx_addr)); | |
| 1329 | + | |
| 1330 | + /* 2, update vmid of descriptor */ | |
| 1331 | + tmp = RREG32_SOC15(VCN, 0, regMMSCH_VF_VMID); | |
| 1332 | + tmp &= ~MMSCH_VF_VMID__VF_CTX_VMID_MASK; | |
| 1333 | + /* use domain0 for MM scheduler */ | |
| 1334 | + tmp |= (0 << MMSCH_VF_VMID__VF_CTX_VMID__SHIFT); | |
| 1335 | + WREG32_SOC15(VCN, 0, regMMSCH_VF_VMID, tmp); | |
| 1336 | + | |
| 1337 | + /* 3, notify mmsch about the size of this descriptor */ | |
| 1338 | + size = header.total_size; | |
| 1339 | + WREG32_SOC15(VCN, 0, regMMSCH_VF_CTX_SIZE, size); | |
| 1340 | + | |
| 1341 | + /* 4, set resp to zero */ | |
| 1342 | + WREG32_SOC15(VCN, 0, regMMSCH_VF_MAILBOX_RESP, 0); | |
| 1343 | + | |
| 1344 | + /* 5, kick off the initialization and wait until | |
| 1345 | + * MMSCH_VF_MAILBOX_RESP becomes non-zero | |
| 1346 | + */ | |
| 1347 | + param = 0x00000001; | |
| 1348 | + WREG32_SOC15(VCN, 0, regMMSCH_VF_MAILBOX_HOST, param); | |
| 1349 | + tmp = 0; | |
| 1350 | + timeout = 1000; | |
| 1351 | + resp = 0; | |
| 1352 | + expected = MMSCH_VF_MAILBOX_RESP__OK; | |
| 1353 | + while (resp != expected) { | |
| 1354 | + resp = RREG32_SOC15(VCN, 0, regMMSCH_VF_MAILBOX_RESP); | |
| 1355 | + if (resp != 0) | |
| 1356 | + break; | |
| 1357 | + | |
| 1358 | + udelay(10); | |
| 1359 | + tmp = tmp + 10; | |
| 1360 | + if (tmp >= timeout) { | |
| 1361 | + DRM_ERROR("failed to init MMSCH. TIME-OUT after %d usec"\ | |
| 1362 | + " waiting for regMMSCH_VF_MAILBOX_RESP "\ | |
| 1363 | + "(expected=0x%08x, readback=0x%08x)\n", | |
| 1364 | + tmp, expected, resp); | |
| 1365 | + return -EBUSY; | |
| 1366 | + } | |
| 1367 | + } | |
| 1368 | + enabled_vcn = amdgpu_vcn_is_disabled_vcn(adev, VCN_DECODE_RING, 0) ? 1 : 0; | |
| 1369 | + init_status = ((struct mmsch_v4_0_init_header *)(table_loc))->inst[enabled_vcn].init_status; | |
| 1370 | + if (resp != expected && resp != MMSCH_VF_MAILBOX_RESP__INCOMPLETE | |
| 1371 | + && init_status != MMSCH_VF_ENGINE_STATUS__PASS) | |
| 1372 | + DRM_ERROR("MMSCH init status is incorrect! readback=0x%08x, header init "\ | |
| 1373 | + "status for VCN%x: 0x%x\n", resp, enabled_vcn, init_status); | |
| 1374 | + | |
| 1375 | + return 0; | |
| 1376 | +} | |
| 1377 | + | |
| 1110 | 1378 | /** |
| 1111 | 1379 | * vcn_v4_0_stop_dpg_mode - VCN stop with dpg mode |
| 1112 | 1380 | * |
| @@ -1327,21 +1595,23 @@ static void vcn_v4_0_unified_ring_set_wptr(struct amdgpu_ring *ring) · 214 unmodified lines | ||
| 1327 | 1595 | } |
| 1328 | 1596 | } |
| 1329 | 1597 | |
| 1330 | −static int vcn_v4_0_limit_sched(struct amdgpu_cs_parser *p) | |
| 1598 | +static int vcn_v4_0_limit_sched(struct amdgpu_cs_parser *p, | |
| 1599 | + struct amdgpu_job *job) | |
| 1331 | 1600 | { |
| 1332 | 1601 | struct drm_gpu_scheduler **scheds; |
| 1333 | 1602 | |
| 1334 | 1603 | /* The create msg must be in the first IB submitted */ |
| 1335 | − if (atomic_read(&p->entity->fence_seq)) | |
| 1604 | + if (atomic_read(&job->base.entity->fence_seq)) | |
| 1336 | 1605 | return -EINVAL; |
| 1337 | 1606 | |
| 1338 | 1607 | scheds = p->adev->gpu_sched[AMDGPU_HW_IP_VCN_ENC] |
| 1339 | 1608 | [AMDGPU_RING_PRIO_0].sched; |
| 1340 | − drm_sched_entity_modify_sched(p->entity, scheds, 1); | |
| 1609 | + drm_sched_entity_modify_sched(job->base.entity, scheds, 1); | |
| 1341 | 1610 | return 0; |
| 1342 | 1611 | } |
| 1343 | 1612 | |
| 1344 | −static int vcn_v4_0_dec_msg(struct amdgpu_cs_parser *p, uint64_t addr) | |
| 1613 | +static int vcn_v4_0_dec_msg(struct amdgpu_cs_parser *p, struct amdgpu_job *job, | |
| 1614 | + uint64_t addr) | |
| 1345 | 1615 | { |
| 1346 | 1616 | struct ttm_operation_ctx ctx = { false, false }; |
| 1347 | 1617 | struct amdgpu_bo_va_mapping *map; |
| @@ -1412,7 +1682,7 @@ static int vcn_v4_0_dec_msg(struct amdgpu_cs_parser *p, uint64_t addr) · 64 unmodified lines | ||
| 1412 | 1682 | if (create[0] == 0x7 || create[0] == 0x10 || create[0] == 0x11) |
| 1413 | 1683 | continue; |
| 1414 | 1684 | |
| 1415 | − r = vcn_v4_0_limit_sched(p); | |
| 1685 | + r = vcn_v4_0_limit_sched(p, job); | |
| 1416 | 1686 | if (r) |
| 1417 | 1687 | goto out; |
| 1418 | 1688 | } |
| @@ -1425,32 +1695,34 @@ out: · 6 unmodified lines | ||
| 1425 | 1695 | #define RADEON_VCN_ENGINE_TYPE_DECODE (0x00000003) |
| 1426 | 1696 | |
| 1427 | 1697 | static int vcn_v4_0_ring_patch_cs_in_place(struct amdgpu_cs_parser *p, |
| 1428 | − struct amdgpu_job *job, | |
| 1429 | − struct amdgpu_ib *ib) | |
| 1698 | + struct amdgpu_job *job, | |
| 1699 | + struct amdgpu_ib *ib) | |
| 1430 | 1700 | { |
| 1431 | − struct amdgpu_ring *ring = to_amdgpu_ring(p->entity->rq->sched); | |
| 1432 | − struct amdgpu_vcn_decode_buffer *decode_buffer = NULL; | |
| 1701 | + struct amdgpu_ring *ring = amdgpu_job_ring(job); | |
| 1702 | + struct amdgpu_vcn_decode_buffer *decode_buffer; | |
| 1703 | + uint64_t addr; | |
| 1433 | 1704 | uint32_t val; |
| 1434 | − int r = 0; | |
| 1435 | 1705 | |
| 1436 | 1706 | /* The first instance can decode anything */ |
| 1437 | 1707 | if (!ring->me) |
| 1438 | − return r; | |
| 1708 | + return 0; | |
| 1439 | 1709 | |
| 1440 | 1710 | /* unified queue ib header has 8 double words. */ |
| 1441 | 1711 | if (ib->length_dw < 8) |
| 1442 | − return r; | |
| 1712 | + return 0; | |
| 1443 | 1713 | |
| 1444 | 1714 | val = amdgpu_ib_get_value(ib, 6); //RADEON_VCN_ENGINE_TYPE |
| 1715 | + if (val != RADEON_VCN_ENGINE_TYPE_DECODE) | |
| 1716 | + return 0; | |
| 1445 | 1717 | |
| 1446 | − if (val == RADEON_VCN_ENGINE_TYPE_DECODE) { | |
| 1447 | − decode_buffer = (struct amdgpu_vcn_decode_buffer *)&ib->ptr[10]; | |
| 1718 | + decode_buffer = (struct amdgpu_vcn_decode_buffer *)&ib->ptr[10]; | |
| 1448 | 1719 | |
| 1449 | − if (decode_buffer->valid_buf_flag & 0x1) | |
| 1450 | − r = vcn_v4_0_dec_msg(p, ((u64)decode_buffer->msg_buffer_address_hi) << 32 | | |
| 1451 | − decode_buffer->msg_buffer_address_lo); | |
| 1452 | − } | |
| 1453 | − return r; | |
| 1720 | + if (!(decode_buffer->valid_buf_flag & 0x1)) | |
| 1721 | + return 0; | |
| 1722 | + | |
| 1723 | + addr = ((u64)decode_buffer->msg_buffer_address_hi) << 32 | | |
| 1724 | + decode_buffer->msg_buffer_address_lo; | |
| 1725 | + return vcn_v4_0_dec_msg(p, job, addr); | |
| 1454 | 1726 | } |
| 1455 | 1727 | |
| 1456 | 1728 | static const struct amdgpu_ring_funcs vcn_v4_0_unified_ring_vm_funcs = { |
| @@ -1596,6 +1868,15 @@ static int vcn_v4_0_set_powergating_state(void *handle, enum amd_powergating_sta · 139 unmodified lines | ||
| 1596 | 1868 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
| 1597 | 1869 | int ret; |
| 1598 | 1870 | |
| 1871 | + /* for SRIOV, guest should not control VCN Power-gating | |
| 1872 | + * MMSCH FW should control Power-gating and clock-gating | |
| 1873 | + * guest should avoid touching CGC and PG | |
| 1874 | + */ | |
| 1875 | + if (amdgpu_sriov_vf(adev)) { | |
| 1876 | + adev->vcn.cur_state = AMD_PG_STATE_UNGATE; | |
| 1877 | + return 0; | |
| 1878 | + } | |
| 1879 | + | |
| 1599 | 1880 | if(state == adev->vcn.cur_state) |
| 1600 | 1881 | return 0; |
| 1601 | 1882 | |
| @@ -742,7 +742,7 @@ static const uint32_t cwsr_trap_nv1x_hex[] = { · 741 unmodified lines | ||
| 742 | 742 | 0xbf88fffe, 0x877aff7f, |
| 743 | 743 | 0x04000000, 0x8f7a857a, |
| 744 | 744 | 0x886d7a6d, 0xb97b02dc, |
| 745 | − 0x8f7b997b, 0xb97a2a05, | |
| 745 | + 0x8f7b997b, 0xb97a3a05, | |
| 746 | 746 | 0x807a817a, 0xbf0d997b, |
| 747 | 747 | 0xbf850002, 0x8f7a897a, |
| 748 | 748 | 0xbf820001, 0x8f7a8a7a, |
| @@ -819,7 +819,7 @@ static const uint32_t cwsr_trap_nv1x_hex[] = { · 70 unmodified lines | ||
| 819 | 819 | 0xbefe037c, 0xbefc0370, |
| 820 | 820 | 0xf4611c7a, 0xf8000000, |
| 821 | 821 | 0x80708470, 0xbefc037e, |
| 822 | − 0xb9702a05, 0x80708170, | |
| 822 | + 0xb9703a05, 0x80708170, | |
| 823 | 823 | 0xbf0d9973, 0xbf850002, |
| 824 | 824 | 0x8f708970, 0xbf820001, |
| 825 | 825 | 0x8f708a70, 0xb97a1e06, |
| @@ -1069,7 +1069,7 @@ static const uint32_t cwsr_trap_nv1x_hex[] = { · 243 unmodified lines | ||
| 1069 | 1069 | 0xb9f9f816, 0x876f7bff, |
| 1070 | 1070 | 0xfffff800, 0x906f8b6f, |
| 1071 | 1071 | 0xb9efa2c3, 0xb9f3f801, |
| 1072 | − 0xb96e2a05, 0x806e816e, | |
| 1072 | + 0xb96e3a05, 0x806e816e, | |
| 1073 | 1073 | 0xbf0d9972, 0xbf850002, |
| 1074 | 1074 | 0x8f6e896e, 0xbf820001, |
| 1075 | 1075 | 0x8f6e8a6e, 0xb96f1e06, |
| @@ -2114,7 +2114,7 @@ static const uint32_t cwsr_trap_gfx10_hex[] = { · 1038 unmodified lines | ||
| 2114 | 2114 | 0x007a0000, 0x7e000280, |
| 2115 | 2115 | 0xbefe037a, 0xbeff037b, |
| 2116 | 2116 | 0xb97b02dc, 0x8f7b997b, |
| 2117 | − 0xb97a2a05, 0x807a817a, | |
| 2117 | + 0xb97a3a05, 0x807a817a, | |
| 2118 | 2118 | 0xbf0d997b, 0xbf850002, |
| 2119 | 2119 | 0x8f7a897a, 0xbf820001, |
| 2120 | 2120 | 0x8f7a8a7a, 0xb97b1e06, |
| @@ -2157,7 +2157,7 @@ static const uint32_t cwsr_trap_gfx10_hex[] = { · 36 unmodified lines | ||
| 2157 | 2157 | 0x01000000, 0xe0704100, |
| 2158 | 2158 | 0x705d0100, 0xe0704200, |
| 2159 | 2159 | 0x705d0200, 0xe0704300, |
| 2160 | − 0x705d0300, 0xb9702a05, | |
| 2160 | + 0x705d0300, 0xb9703a05, | |
| 2161 | 2161 | 0x80708170, 0xbf0d9973, |
| 2162 | 2162 | 0xbf850002, 0x8f708970, |
| 2163 | 2163 | 0xbf820001, 0x8f708a70, |
| @@ -2189,7 +2189,7 @@ static const uint32_t cwsr_trap_gfx10_hex[] = { · 25 unmodified lines | ||
| 2189 | 2189 | 0xbefe03ff, 0x0000ffff, |
| 2190 | 2190 | 0xbeff0380, 0xe0704000, |
| 2191 | 2191 | 0x705d0200, 0xbefe03c1, |
| 2192 | − 0xb9702a05, 0x80708170, | |
| 2192 | + 0xb9703a05, 0x80708170, | |
| 2193 | 2193 | 0xbf0d9973, 0xbf850002, |
| 2194 | 2194 | 0x8f708970, 0xbf820001, |
| 2195 | 2195 | 0x8f708a70, 0xb97a1e06, |
| @@ -2475,7 +2475,7 @@ static const uint32_t cwsr_trap_gfx10_hex[] = { · 279 unmodified lines | ||
| 2475 | 2475 | 0xb9ef4803, 0x876f7bff, |
| 2476 | 2476 | 0xfffff800, 0x906f8b6f, |
| 2477 | 2477 | 0xb9efa2c3, 0xb9f3f801, |
| 2478 | − 0xb96e2a05, 0x806e816e, | |
| 2478 | + 0xb96e3a05, 0x806e816e, | |
| 2479 | 2479 | 0xbf0d9972, 0xbf850002, |
| 2480 | 2480 | 0x8f6e896e, 0xbf820001, |
| 2481 | 2481 | 0x8f6e8a6e, 0xb96f1e06, |
| @@ -2494,438 +2494,441 @@ static const uint32_t cwsr_trap_gfx10_hex[] = { · 12 unmodified lines | ||
| 2494 | 2494 | 0xbf9f0000, 0xbf9f0000, |
| 2495 | 2495 | 0xbf9f0000, 0x00000000, |
| 2496 | 2496 | }; |
| 2497 | − | |
| 2498 | 2497 | static const uint32_t cwsr_trap_gfx11_hex[] = { |
| 2499 | − 0xbfa00001, 0xbfa0021b, | |
| 2498 | + 0xbfa00001, 0xbfa0021e, | |
| 2500 | 2499 | 0xb0804006, 0xb8f8f802, |
| 2501 | − 0x91788678, 0xb8fbf803, | |
| 2502 | − 0x8b6eff78, 0x00002000, | |
| 2503 | − 0xbfa10009, 0x8b6eff6d, | |
| 2504 | − 0x00ff0000, 0xbfa2001e, | |
| 2505 | − 0x8b6eff7b, 0x00000400, | |
| 2506 | − 0xbfa20041, 0xbf830010, | |
| 2507 | − 0xb8fbf803, 0xbfa0fffa, | |
| 2508 | − 0x8b6eff7b, 0x00000900, | |
| 2509 | − 0xbfa20015, 0x8b6eff7b, | |
| 2510 | − 0x000071ff, 0xbfa10008, | |
| 2511 | − 0x8b6fff7b, 0x00007080, | |
| 2512 | − 0xbfa10001, 0xbeee1287, | |
| 2513 | − 0xb8eff801, 0x846e8c6e, | |
| 2514 | − 0x8b6e6f6e, 0xbfa2000a, | |
| 2500 | + 0x9178ff78, 0x00020006, | |
| 2501 | + 0xb8fbf803, 0xbf0d9f6d, | |
| 2502 | + 0xbfa20006, 0x8b6eff78, | |
| 2503 | + 0x00002000, 0xbfa10009, | |
| 2515 | 2504 | 0x8b6eff6d, 0x00ff0000, |
| 2516 | − 0xbfa20007, 0xb8eef801, | |
| 2517 | − 0x8b6eff6e, 0x00000800, | |
| 2518 | − 0xbfa20003, 0x8b6eff7b, | |
| 2519 | − 0x00000400, 0xbfa20026, | |
| 2520 | − 0xbefa4d82, 0xbf89fc07, | |
| 2521 | − 0x84fa887a, 0xf4005bbd, | |
| 2522 | − 0xf8000010, 0xbf89fc07, | |
| 2523 | − 0x846e976e, 0x9177ff77, | |
| 2524 | − 0x00800000, 0x8c776e77, | |
| 2525 | − 0xf4045bbd, 0xf8000000, | |
| 2526 | − 0xbf89fc07, 0xf4045ebd, | |
| 2527 | − 0xf8000008, 0xbf89fc07, | |
| 2528 | − 0x8bee6e6e, 0xbfa10001, | |
| 2529 | − 0xbe80486e, 0x8b6eff6d, | |
| 2530 | − 0x01ff0000, 0xbfa20005, | |
| 2531 | − 0x8c78ff78, 0x00002000, | |
| 2532 | − 0x80ec886c, 0x82ed806d, | |
| 2533 | − 0xbfa00005, 0x8b6eff6d, | |
| 2534 | − 0x01000000, 0xbfa20002, | |
| 2535 | − 0x806c846c, 0x826d806d, | |
| 2536 | − 0x8b6dff6d, 0x0000ffff, | |
| 2537 | − 0x8bfe7e7e, 0x8bea6a6a, | |
| 2538 | − 0xb978f802, 0xbe804a6c, | |
| 2539 | − 0x8b6dff6d, 0x0000ffff, | |
| 2540 | − 0xbefa0080, 0xb97a0283, | |
| 2541 | − 0xbeee007e, 0xbeef007f, | |
| 2542 | − 0xbefe0180, 0xbefe4d84, | |
| 2543 | − 0xbf89fc07, 0x8b7aff7f, | |
| 2544 | − 0x04000000, 0x847a857a, | |
| 2545 | − 0x8c6d7a6d, 0xbefa007e, | |
| 2546 | − 0x8b7bff7f, 0x0000ffff, | |
| 2547 | − 0xbefe00c1, 0xbeff00c1, | |
| 2548 | − 0xdca6c000, 0x007a0000, | |
| 2549 | − 0x7e000280, 0xbefe007a, | |
| 2550 | − 0xbeff007b, 0xb8fb02dc, | |
| 2551 | − 0x847b997b, 0xb8fa3b05, | |
| 2552 | − 0x807a817a, 0xbf0d997b, | |
| 2553 | − 0xbfa20002, 0x847a897a, | |
| 2554 | − 0xbfa00001, 0x847a8a7a, | |
| 2555 | − 0xb8fb1e06, 0x847b8a7b, | |
| 2556 | − 0x807a7b7a, 0x8b7bff7f, | |
| 2557 | − 0x0000ffff, 0x807aff7a, | |
| 2558 | − 0x00000200, 0x807a7e7a, | |
| 2559 | − 0x827b807b, 0xd7610000, | |
| 2560 | − 0x00010870, 0xd7610000, | |
| 2561 | − 0x00010a71, 0xd7610000, | |
| 2562 | − 0x00010c72, 0xd7610000, | |
| 2563 | − 0x00010e73, 0xd7610000, | |
| 2564 | − 0x00011074, 0xd7610000, | |
| 2565 | − 0x00011275, 0xd7610000, | |
| 2566 | − 0x00011476, 0xd7610000, | |
| 2567 | − 0x00011677, 0xd7610000, | |
| 2568 | − 0x00011a79, 0xd7610000, | |
| 2569 | − 0x00011c7e, 0xd7610000, | |
| 2570 | − 0x00011e7f, 0xbefe00ff, | |
| 2571 | − 0x00003fff, 0xbeff0080, | |
| 2572 | − 0xdca6c040, 0x007a0000, | |
| 2573 | − 0xd760007a, 0x00011d00, | |
| 2574 | − 0xd760007b, 0x00011f00, | |
| 2505 | + 0xbfa2001e, 0x8b6eff7b, | |
| 2506 | + 0x00000400, 0xbfa20041, | |
| 2507 | + 0xbf830010, 0xb8fbf803, | |
| 2508 | + 0xbfa0fffa, 0x8b6eff7b, | |
| 2509 | + 0x00000900, 0xbfa20015, | |
| 2510 | + 0x8b6eff7b, 0x000071ff, | |
| 2511 | + 0xbfa10008, 0x8b6fff7b, | |
| 2512 | + 0x00007080, 0xbfa10001, | |
| 2513 | + 0xbeee1287, 0xb8eff801, | |
| 2514 | + 0x846e8c6e, 0x8b6e6f6e, | |
| 2515 | + 0xbfa2000a, 0x8b6eff6d, | |
| 2516 | + 0x00ff0000, 0xbfa20007, | |
| 2517 | + 0xb8eef801, 0x8b6eff6e, | |
| 2518 | + 0x00000800, 0xbfa20003, | |
| 2519 | + 0x8b6eff7b, 0x00000400, | |
| 2520 | + 0xbfa20026, 0xbefa4d82, | |
| 2521 | + 0xbf89fc07, 0x84fa887a, | |
| 2522 | + 0xf4005bbd, 0xf8000010, | |
| 2523 | + 0xbf89fc07, 0x846e976e, | |
| 2524 | + 0x9177ff77, 0x00800000, | |
| 2525 | + 0x8c776e77, 0xf4045bbd, | |
| 2526 | + 0xf8000000, 0xbf89fc07, | |
| 2527 | + 0xf4045ebd, 0xf8000008, | |
| 2528 | + 0xbf89fc07, 0x8bee6e6e, | |
| 2529 | + 0xbfa10001, 0xbe80486e, | |
| 2530 | + 0x8b6eff6d, 0x01ff0000, | |
| 2531 | + 0xbfa20005, 0x8c78ff78, | |
| 2532 | + 0x00002000, 0x80ec886c, | |
| 2533 | + 0x82ed806d, 0xbfa00005, | |
| 2534 | + 0x8b6eff6d, 0x01000000, | |
| 2535 | + 0xbfa20002, 0x806c846c, | |
| 2536 | + 0x826d806d, 0x8b6dff6d, | |
| 2537 | + 0x0000ffff, 0x8bfe7e7e, | |
| 2538 | + 0x8bea6a6a, 0xb978f802, | |
| 2539 | + 0xbe804a6c, 0x8b6dff6d, | |
| 2540 | + 0x0000ffff, 0xbefa0080, | |
| 2541 | + 0xb97a0283, 0xbeee007e, | |
| 2542 | + 0xbeef007f, 0xbefe0180, | |
| 2543 | + 0xbefe4d84, 0xbf89fc07, | |
| 2544 | + 0x8b7aff7f, 0x04000000, | |
| 2545 | + 0x847a857a, 0x8c6d7a6d, | |
| 2546 | + 0xbefa007e, 0x8b7bff7f, | |
| 2547 | + 0x0000ffff, 0xbefe00c1, | |
| 2548 | + 0xbeff00c1, 0xdca6c000, | |
| 2549 | + 0x007a0000, 0x7e000280, | |
| 2575 | 2550 | 0xbefe007a, 0xbeff007b, |
| 2576 | − 0xbef4007e, 0x8b75ff7f, | |
| 2577 | − 0x0000ffff, 0x8c75ff75, | |
| 2578 | − 0x00040000, 0xbef60080, | |
| 2579 | − 0xbef700ff, 0x10807fac, | |
| 2580 | − 0xbef1007d, 0xbef00080, | |
| 2581 | − 0xb8f302dc, 0x84739973, | |
| 2582 | − 0xbefe00c1, 0x857d9973, | |
| 2583 | − 0x8b7d817d, 0xbf06817d, | |
| 2584 | − 0xbfa20002, 0xbeff0080, | |
| 2585 | − 0xbfa00002, 0xbeff00c1, | |
| 2586 | − 0xbfa00009, 0xbef600ff, | |
| 2587 | − 0x01000000, 0xe0685080, | |
| 2588 | − 0x701d0100, 0xe0685100, | |
| 2589 | − 0x701d0200, 0xe0685180, | |
| 2590 | − 0x701d0300, 0xbfa00008, | |
| 2551 | + 0xb8fb02dc, 0x847b997b, | |
| 2552 | + 0xb8fa3b05, 0x807a817a, | |
| 2553 | + 0xbf0d997b, 0xbfa20002, | |
| 2554 | + 0x847a897a, 0xbfa00001, | |
| 2555 | + 0x847a8a7a, 0xb8fb1e06, | |
| 2556 | + 0x847b8a7b, 0x807a7b7a, | |
| 2557 | + 0x8b7bff7f, 0x0000ffff, | |
| 2558 | + 0x807aff7a, 0x00000200, | |
| 2559 | + 0x807a7e7a, 0x827b807b, | |
| 2560 | + 0xd7610000, 0x00010870, | |
| 2561 | + 0xd7610000, 0x00010a71, | |
| 2562 | + 0xd7610000, 0x00010c72, | |
| 2563 | + 0xd7610000, 0x00010e73, | |
| 2564 | + 0xd7610000, 0x00011074, | |
| 2565 | + 0xd7610000, 0x00011275, | |
| 2566 | + 0xd7610000, 0x00011476, | |
| 2567 | + 0xd7610000, 0x00011677, | |
| 2568 | + 0xd7610000, 0x00011a79, | |
| 2569 | + 0xd7610000, 0x00011c7e, | |
| 2570 | + 0xd7610000, 0x00011e7f, | |
| 2571 | + 0xbefe00ff, 0x00003fff, | |
| 2572 | + 0xbeff0080, 0xdca6c040, | |
| 2573 | + 0x007a0000, 0xd760007a, | |
| 2574 | + 0x00011d00, 0xd760007b, | |
| 2575 | + 0x00011f00, 0xbefe007a, | |
| 2576 | + 0xbeff007b, 0xbef4007e, | |
| 2577 | + 0x8b75ff7f, 0x0000ffff, | |
| 2578 | + 0x8c75ff75, 0x00040000, | |
| 2579 | + 0xbef60080, 0xbef700ff, | |
| 2580 | + 0x10807fac, 0xbef1007d, | |
| 2581 | + 0xbef00080, 0xb8f302dc, | |
| 2582 | + 0x84739973, 0xbefe00c1, | |
| 2583 | + 0x857d9973, 0x8b7d817d, | |
| 2584 | + 0xbf06817d, 0xbfa20002, | |
| 2585 | + 0xbeff0080, 0xbfa00002, | |
| 2586 | + 0xbeff00c1, 0xbfa00009, | |
| 2591 | 2587 | 0xbef600ff, 0x01000000, |
| 2592 | − 0xe0685100, 0x701d0100, | |
| 2593 | − 0xe0685200, 0x701d0200, | |
| 2594 | − 0xe0685300, 0x701d0300, | |
| 2588 | + 0xe0685080, 0x701d0100, | |
| 2589 | + 0xe0685100, 0x701d0200, | |
| 2590 | + 0xe0685180, 0x701d0300, | |
| 2591 | + 0xbfa00008, 0xbef600ff, | |
| 2592 | + 0x01000000, 0xe0685100, | |
| 2593 | + 0x701d0100, 0xe0685200, | |
| 2594 | + 0x701d0200, 0xe0685300, | |
| 2595 | + 0x701d0300, 0xb8f03b05, | |
| 2596 | + 0x80708170, 0xbf0d9973, | |
| 2597 | + 0xbfa20002, 0x84708970, | |
| 2598 | + 0xbfa00001, 0x84708a70, | |
| 2599 | + 0xb8fa1e06, 0x847a8a7a, | |
| 2600 | + 0x80707a70, 0x8070ff70, | |
| 2601 | + 0x00000200, 0xbef600ff, | |
| 2602 | + 0x01000000, 0x7e000280, | |
| 2603 | + 0x7e020280, 0x7e040280, | |
| 2604 | + 0xbefd0080, 0xd7610002, | |
| 2605 | + 0x0000fa71, 0x807d817d, | |
| 2606 | + 0xd7610002, 0x0000fa6c, | |
| 2607 | + 0x807d817d, 0x917aff6d, | |
| 2608 | + 0x80000000, 0xd7610002, | |
| 2609 | + 0x0000fa7a, 0x807d817d, | |
| 2610 | + 0xd7610002, 0x0000fa6e, | |
| 2611 | + 0x807d817d, 0xd7610002, | |
| 2612 | + 0x0000fa6f, 0x807d817d, | |
| 2613 | + 0xd7610002, 0x0000fa78, | |
| 2614 | + 0x807d817d, 0xb8faf803, | |
| 2615 | + 0xd7610002, 0x0000fa7a, | |
| 2616 | + 0x807d817d, 0xd7610002, | |
| 2617 | + 0x0000fa7b, 0x807d817d, | |
| 2618 | + 0xb8f1f801, 0xd7610002, | |
| 2619 | + 0x0000fa71, 0x807d817d, | |
| 2620 | + 0xb8f1f814, 0xd7610002, | |
| 2621 | + 0x0000fa71, 0x807d817d, | |
| 2622 | + 0xb8f1f815, 0xd7610002, | |
| 2623 | + 0x0000fa71, 0x807d817d, | |
| 2624 | + 0xbefe00ff, 0x0000ffff, | |
| 2625 | + 0xbeff0080, 0xe0685000, | |
| 2626 | + 0x701d0200, 0xbefe00c1, | |
| 2595 | 2627 | 0xb8f03b05, 0x80708170, |
| 2596 | 2628 | 0xbf0d9973, 0xbfa20002, |
| 2597 | 2629 | 0x84708970, 0xbfa00001, |
| 2598 | 2630 | 0x84708a70, 0xb8fa1e06, |
| 2599 | 2631 | 0x847a8a7a, 0x80707a70, |
| 2600 | − 0x8070ff70, 0x00000200, | |
| 2601 | 2632 | 0xbef600ff, 0x01000000, |
| 2602 | − 0x7e000280, 0x7e020280, | |
| 2603 | − 0x7e040280, 0xbefd0080, | |
| 2604 | − 0xd7610002, 0x0000fa71, | |
| 2605 | − 0x807d817d, 0xd7610002, | |
| 2606 | − 0x0000fa6c, 0x807d817d, | |
| 2607 | − 0x917aff6d, 0x80000000, | |
| 2608 | − 0xd7610002, 0x0000fa7a, | |
| 2609 | − 0x807d817d, 0xd7610002, | |
| 2610 | − 0x0000fa6e, 0x807d817d, | |
| 2611 | − 0xd7610002, 0x0000fa6f, | |
| 2612 | − 0x807d817d, 0xd7610002, | |
| 2613 | − 0x0000fa78, 0x807d817d, | |
| 2614 | − 0xb8faf803, 0xd7610002, | |
| 2615 | − 0x0000fa7a, 0x807d817d, | |
| 2616 | − 0xd7610002, 0x0000fa7b, | |
| 2617 | − 0x807d817d, 0xb8f1f801, | |
| 2618 | − 0xd7610002, 0x0000fa71, | |
| 2619 | − 0x807d817d, 0xb8f1f814, | |
| 2620 | − 0xd7610002, 0x0000fa71, | |
| 2621 | − 0x807d817d, 0xb8f1f815, | |
| 2622 | − 0xd7610002, 0x0000fa71, | |
| 2623 | − 0x807d817d, 0xbefe00ff, | |
| 2624 | − 0x0000ffff, 0xbeff0080, | |
| 2625 | − 0xe0685000, 0x701d0200, | |
| 2626 | − 0xbefe00c1, 0xb8f03b05, | |
| 2627 | − 0x80708170, 0xbf0d9973, | |
| 2628 | − 0xbfa20002, 0x84708970, | |
| 2629 | − 0xbfa00001, 0x84708a70, | |
| 2630 | − 0xb8fa1e06, 0x847a8a7a, | |
| 2631 | − 0x80707a70, 0xbef600ff, | |
| 2632 | − 0x01000000, 0xbef90080, | |
| 2633 | − 0xbefd0080, 0xbf800000, | |
| 2634 | − 0xbe804100, 0xbe824102, | |
| 2635 | − 0xbe844104, 0xbe864106, | |
| 2636 | − 0xbe884108, 0xbe8a410a, | |
| 2637 | − 0xbe8c410c, 0xbe8e410e, | |
| 2638 | − 0xd7610002, 0x0000f200, | |
| 2639 | − 0x80798179, 0xd7610002, | |
| 2640 | − 0x0000f201, 0x80798179, | |
| 2641 | − 0xd7610002, 0x0000f202, | |
| 2642 | − 0x80798179, 0xd7610002, | |
| 2643 | − 0x0000f203, 0x80798179, | |
| 2644 | − 0xd7610002, 0x0000f204, | |
| 2633 | + 0xbef90080, 0xbefd0080, | |
| 2634 | + 0xbf800000, 0xbe804100, | |
| 2635 | + 0xbe824102, 0xbe844104, | |
| 2636 | + 0xbe864106, 0xbe884108, | |
| 2637 | + 0xbe8a410a, 0xbe8c410c, | |
| 2638 | + 0xbe8e410e, 0xd7610002, | |
| 2639 | + 0x0000f200, 0x80798179, | |
| 2640 | + 0xd7610002, 0x0000f201, | |
| 2645 | 2641 | 0x80798179, 0xd7610002, |
| 2646 | − 0x0000f205, 0x80798179, | |
| 2647 | − 0xd7610002, 0x0000f206, | |
| 2642 | + 0x0000f202, 0x80798179, | |
| 2643 | + 0xd7610002, 0x0000f203, | |
| 2648 | 2644 | 0x80798179, 0xd7610002, |
| 2649 | − 0x0000f207, 0x80798179, | |
| 2650 | − 0xd7610002, 0x0000f208, | |
| 2645 | + 0x0000f204, 0x80798179, | |
| 2646 | + 0xd7610002, 0x0000f205, | |
| 2651 | 2647 | 0x80798179, 0xd7610002, |
| 2652 | − 0x0000f209, 0x80798179, | |
| 2653 | − 0xd7610002, 0x0000f20a, | |
| 2648 | + 0x0000f206, 0x80798179, | |
| 2649 | + 0xd7610002, 0x0000f207, | |
| 2654 | 2650 | 0x80798179, 0xd7610002, |
| 2655 | − 0x0000f20b, 0x80798179, | |
| 2656 | − 0xd7610002, 0x0000f20c, | |
| 2651 | + 0x0000f208, 0x80798179, | |
| 2652 | + 0xd7610002, 0x0000f209, | |
| 2657 | 2653 | 0x80798179, 0xd7610002, |
| 2658 | − 0x0000f20d, 0x80798179, | |
| 2659 | − 0xd7610002, 0x0000f20e, | |
| 2654 | + 0x0000f20a, 0x80798179, | |
| 2655 | + 0xd7610002, 0x0000f20b, | |
| 2660 | 2656 | 0x80798179, 0xd7610002, |
| 2661 | − 0x0000f20f, 0x80798179, | |
| 2662 | − 0xbf06a079, 0xbfa10006, | |
| 2663 | − 0xe0685000, 0x701d0200, | |
| 2664 | − 0x8070ff70, 0x00000080, | |
| 2665 | − 0xbef90080, 0x7e040280, | |
| 2666 | − 0x807d907d, 0xbf0aff7d, | |
| 2667 | − 0x00000060, 0xbfa2ffbc, | |
| 2668 | − 0xbe804100, 0xbe824102, | |
| 2669 | − 0xbe844104, 0xbe864106, | |
| 2670 | − 0xbe884108, 0xbe8a410a, | |
| 2671 | − 0xd7610002, 0x0000f200, | |
| 2657 | + 0x0000f20c, 0x80798179, | |
| 2658 | + 0xd7610002, 0x0000f20d, | |
| 2672 | 2659 | 0x80798179, 0xd7610002, |
| 2673 | − 0x0000f201, 0x80798179, | |
| 2674 | − 0xd7610002, 0x0000f202, | |
| 2660 | + 0x0000f20e, 0x80798179, | |
| 2661 | + 0xd7610002, 0x0000f20f, | |
| 2662 | + 0x80798179, 0xbf06a079, | |
| 2663 | + 0xbfa10006, 0xe0685000, | |
| 2664 | + 0x701d0200, 0x8070ff70, | |
| 2665 | + 0x00000080, 0xbef90080, | |
| 2666 | + 0x7e040280, 0x807d907d, | |
| 2667 | + 0xbf0aff7d, 0x00000060, | |
| 2668 | + 0xbfa2ffbc, 0xbe804100, | |
| 2669 | + 0xbe824102, 0xbe844104, | |
| 2670 | + 0xbe864106, 0xbe884108, | |
| 2671 | + 0xbe8a410a, 0xd7610002, | |
| 2672 | + 0x0000f200, 0x80798179, | |
| 2673 | + 0xd7610002, 0x0000f201, | |
| 2675 | 2674 | 0x80798179, 0xd7610002, |
| 2676 | − 0x0000f203, 0x80798179, | |
| 2677 | − 0xd7610002, 0x0000f204, | |
| 2675 | + 0x0000f202, 0x80798179, | |
| 2676 | + 0xd7610002, 0x0000f203, | |
| 2678 | 2677 | 0x80798179, 0xd7610002, |
| 2679 | − 0x0000f205, 0x80798179, | |
| 2680 | − 0xd7610002, 0x0000f206, | |
| 2678 | + 0x0000f204, 0x80798179, | |
| 2679 | + 0xd7610002, 0x0000f205, | |
| 2681 | 2680 | 0x80798179, 0xd7610002, |
| 2682 | − 0x0000f207, 0x80798179, | |
| 2683 | − 0xd7610002, 0x0000f208, | |
| 2681 | + 0x0000f206, 0x80798179, | |
| 2682 | + 0xd7610002, 0x0000f207, | |
| 2684 | 2683 | 0x80798179, 0xd7610002, |
| 2685 | − 0x0000f209, 0x80798179, | |
| 2686 | − 0xd7610002, 0x0000f20a, | |
| 2684 | + 0x0000f208, 0x80798179, | |
| 2685 | + 0xd7610002, 0x0000f209, | |
| 2687 | 2686 | 0x80798179, 0xd7610002, |
| 2688 | − 0x0000f20b, 0x80798179, | |
| 2689 | − 0xe0685000, 0x701d0200, | |
| 2687 | + 0x0000f20a, 0x80798179, | |
| 2688 | + 0xd7610002, 0x0000f20b, | |
| 2689 | + 0x80798179, 0xe0685000, | |
| 2690 | + 0x701d0200, 0xbefe00c1, | |
| 2691 | + 0x857d9973, 0x8b7d817d, | |
| 2692 | + 0xbf06817d, 0xbfa20002, | |
| 2693 | + 0xbeff0080, 0xbfa00001, | |
| 2694 | + 0xbeff00c1, 0xb8fb4306, | |
| 2695 | + 0x8b7bc17b, 0xbfa10044, | |
| 2696 | + 0xbfbd0000, 0x8b7aff6d, | |
| 2697 | + 0x80000000, 0xbfa10040, | |
| 2698 | + 0x847b867b, 0x847b827b, | |
| 2699 | + 0xbef6007b, 0xb8f03b05, | |
| 2700 | + 0x80708170, 0xbf0d9973, | |
| 2701 | + 0xbfa20002, 0x84708970, | |
| 2702 | + 0xbfa00001, 0x84708a70, | |
| 2703 | + 0xb8fa1e06, 0x847a8a7a, | |
| 2704 | + 0x80707a70, 0x8070ff70, | |
| 2705 | + 0x00000200, 0x8070ff70, | |
| 2706 | + 0x00000080, 0xbef600ff, | |
| 2707 | + 0x01000000, 0xd71f0000, | |
| 2708 | + 0x000100c1, 0xd7200000, | |
| 2709 | + 0x000200c1, 0x16000084, | |
| 2710 | + 0x857d9973, 0x8b7d817d, | |
| 2711 | + 0xbf06817d, 0xbefd0080, | |
| 2712 | + 0xbfa20012, 0xbe8300ff, | |
| 2713 | + 0x00000080, 0xbf800000, | |
| 2714 | + 0xbf800000, 0xbf800000, | |
| 2715 | + 0xd8d80000, 0x01000000, | |
| 2716 | + 0xbf890000, 0xe0685000, | |
| 2717 | + 0x701d0100, 0x807d037d, | |
| 2718 | + 0x80700370, 0xd5250000, | |
| 2719 | + 0x0001ff00, 0x00000080, | |
| 2720 | + 0xbf0a7b7d, 0xbfa2fff4, | |
| 2721 | + 0xbfa00011, 0xbe8300ff, | |
| 2722 | + 0x00000100, 0xbf800000, | |
| 2723 | + 0xbf800000, 0xbf800000, | |
| 2724 | + 0xd8d80000, 0x01000000, | |
| 2725 | + 0xbf890000, 0xe0685000, | |
| 2726 | + 0x701d0100, 0x807d037d, | |
| 2727 | + 0x80700370, 0xd5250000, | |
| 2728 | + 0x0001ff00, 0x00000100, | |
| 2729 | + 0xbf0a7b7d, 0xbfa2fff4, | |
| 2690 | 2730 | 0xbefe00c1, 0x857d9973, |
| 2691 | 2731 | 0x8b7d817d, 0xbf06817d, |
| 2692 | − 0xbfa20002, 0xbeff0080, | |
| 2693 | − 0xbfa00001, 0xbeff00c1, | |
| 2694 | − 0xb8fb4306, 0x8b7bc17b, | |
| 2695 | − 0xbfa10044, 0xbfbd0000, | |
| 2696 | − 0x8b7aff6d, 0x80000000, | |
| 2697 | − 0xbfa10040, 0x847b867b, | |
| 2698 | − 0x847b827b, 0xbef6007b, | |
| 2699 | − 0xb8f03b05, 0x80708170, | |
| 2700 | − 0xbf0d9973, 0xbfa20002, | |
| 2701 | − 0x84708970, 0xbfa00001, | |
| 2702 | − 0x84708a70, 0xb8fa1e06, | |
| 2703 | − 0x847a8a7a, 0x80707a70, | |
| 2704 | − 0x8070ff70, 0x00000200, | |
| 2705 | − 0x8070ff70, 0x00000080, | |
| 2706 | − 0xbef600ff, 0x01000000, | |
| 2707 | − 0xd71f0000, 0x000100c1, | |
| 2708 | − 0xd7200000, 0x000200c1, | |
| 2709 | − 0x16000084, 0x857d9973, | |
| 2732 | + 0xbfa20004, 0xbef000ff, | |
| 2733 | + 0x00000200, 0xbeff0080, | |
| 2734 | + 0xbfa00003, 0xbef000ff, | |
| 2735 | + 0x00000400, 0xbeff00c1, | |
| 2736 | + 0xb8fb3b05, 0x807b817b, | |
| 2737 | + 0x847b827b, 0x857d9973, | |
| 2710 | 2738 | 0x8b7d817d, 0xbf06817d, |
| 2711 | − 0xbefd0080, 0xbfa20012, | |
| 2712 | − 0xbe8300ff, 0x00000080, | |
| 2713 | − 0xbf800000, 0xbf800000, | |
| 2714 | − 0xbf800000, 0xd8d80000, | |
| 2715 | − 0x01000000, 0xbf890000, | |
| 2716 | − 0xe0685000, 0x701d0100, | |
| 2717 | − 0x807d037d, 0x80700370, | |
| 2718 | − 0xd5250000, 0x0001ff00, | |
| 2719 | − 0x00000080, 0xbf0a7b7d, | |
| 2720 | − 0xbfa2fff4, 0xbfa00011, | |
| 2721 | − 0xbe8300ff, 0x00000100, | |
| 2722 | − 0xbf800000, 0xbf800000, | |
| 2723 | − 0xbf800000, 0xd8d80000, | |
| 2724 | − 0x01000000, 0xbf890000, | |
| 2725 | − 0xe0685000, 0x701d0100, | |
| 2726 | − 0x807d037d, 0x80700370, | |
| 2727 | − 0xd5250000, 0x0001ff00, | |
| 2728 | − 0x00000100, 0xbf0a7b7d, | |
| 2729 | − 0xbfa2fff4, 0xbefe00c1, | |
| 2730 | − 0x857d9973, 0x8b7d817d, | |
| 2731 | − 0xbf06817d, 0xbfa20004, | |
| 2732 | − 0xbef000ff, 0x00000200, | |
| 2733 | − 0xbeff0080, 0xbfa00003, | |
| 2734 | − 0xbef000ff, 0x00000400, | |
| 2735 | − 0xbeff00c1, 0xb8fb3b05, | |
| 2736 | − 0x807b817b, 0x847b827b, | |
| 2737 | − 0x857d9973, 0x8b7d817d, | |
| 2738 | − 0xbf06817d, 0xbfa20017, | |
| 2739 | + 0xbfa20017, 0xbef600ff, | |
| 2740 | + 0x01000000, 0xbefd0084, | |
| 2741 | + 0xbf0a7b7d, 0xbfa10037, | |
| 2742 | + 0x7e008700, 0x7e028701, | |
| 2743 | + 0x7e048702, 0x7e068703, | |
| 2744 | + 0xe0685000, 0x701d0000, | |
| 2745 | + 0xe0685080, 0x701d0100, | |
| 2746 | + 0xe0685100, 0x701d0200, | |
| 2747 | + 0xe0685180, 0x701d0300, | |
| 2748 | + 0x807d847d, 0x8070ff70, | |
| 2749 | + 0x00000200, 0xbf0a7b7d, | |
| 2750 | + 0xbfa2ffef, 0xbfa00025, | |
| 2739 | 2751 | 0xbef600ff, 0x01000000, |
| 2740 | 2752 | 0xbefd0084, 0xbf0a7b7d, |
| 2741 | − 0xbfa10037, 0x7e008700, | |
| 2753 | + 0xbfa10011, 0x7e008700, | |
| 2742 | 2754 | 0x7e028701, 0x7e048702, |
| 2743 | 2755 | 0x7e068703, 0xe0685000, |
| 2744 | − 0x701d0000, 0xe0685080, | |
| 2745 | − 0x701d0100, 0xe0685100, | |
| 2746 | − 0x701d0200, 0xe0685180, | |
| 2756 | + 0x701d0000, 0xe0685100, | |
| 2757 | + 0x701d0100, 0xe0685200, | |
| 2758 | + 0x701d0200, 0xe0685300, | |
| 2747 | 2759 | 0x701d0300, 0x807d847d, |
| 2748 | − 0x8070ff70, 0x00000200, | |
| 2760 | + 0x8070ff70, 0x00000400, | |
| 2749 | 2761 | 0xbf0a7b7d, 0xbfa2ffef, |
| 2750 | − 0xbfa00025, 0xbef600ff, | |
| 2751 | − 0x01000000, 0xbefd0084, | |
| 2752 | − 0xbf0a7b7d, 0xbfa10011, | |
| 2753 | − 0x7e008700, 0x7e028701, | |
| 2754 | − 0x7e048702, 0x7e068703, | |
| 2762 | + 0xb8fb1e06, 0x8b7bc17b, | |
| 2763 | + 0xbfa1000c, 0x847b837b, | |
| 2764 | + 0x807b7d7b, 0xbefe00c1, | |
| 2765 | + 0xbeff0080, 0x7e008700, | |
| 2755 | 2766 | 0xe0685000, 0x701d0000, |
| 2756 | − 0xe0685100, 0x701d0100, | |
| 2757 | − 0xe0685200, 0x701d0200, | |
| 2758 | − 0xe0685300, 0x701d0300, | |
| 2759 | − 0x807d847d, 0x8070ff70, | |
| 2760 | − 0x00000400, 0xbf0a7b7d, | |
| 2761 | − 0xbfa2ffef, 0xb8fb1e06, | |
| 2762 | − 0x8b7bc17b, 0xbfa1000c, | |
| 2763 | − 0x847b837b, 0x807b7d7b, | |
| 2764 | − 0xbefe00c1, 0xbeff0080, | |
| 2765 | − 0x7e008700, 0xe0685000, | |
| 2766 | − 0x701d0000, 0x807d817d, | |
| 2767 | − 0x8070ff70, 0x00000080, | |
| 2768 | − 0xbf0a7b7d, 0xbfa2fff8, | |
| 2769 | − 0xbfa00141, 0xbef4007e, | |
| 2770 | − 0x8b75ff7f, 0x0000ffff, | |
| 2771 | − 0x8c75ff75, 0x00040000, | |
| 2772 | − 0xbef60080, 0xbef700ff, | |
| 2773 | − 0x10807fac, 0xb8f202dc, | |
| 2774 | − 0x84729972, 0x8b6eff7f, | |
| 2775 | − 0x04000000, 0xbfa1003a, | |
| 2767 | + 0x807d817d, 0x8070ff70, | |
| 2768 | + 0x00000080, 0xbf0a7b7d, | |
| 2769 | + 0xbfa2fff8, 0xbfa00146, | |
| 2770 | + 0xbef4007e, 0x8b75ff7f, | |
| 2771 | + 0x0000ffff, 0x8c75ff75, | |
| 2772 | + 0x00040000, 0xbef60080, | |
| 2773 | + 0xbef700ff, 0x10807fac, | |
| 2774 | + 0xb8f202dc, 0x84729972, | |
| 2775 | + 0x8b6eff7f, 0x04000000, | |
| 2776 | + 0xbfa1003a, 0xbefe00c1, | |
| 2777 | + 0x857d9972, 0x8b7d817d, | |
| 2778 | + 0xbf06817d, 0xbfa20002, | |
| 2779 | + 0xbeff0080, 0xbfa00001, | |
| 2780 | + 0xbeff00c1, 0xb8ef4306, | |
| 2781 | + 0x8b6fc16f, 0xbfa1002f, | |
| 2782 | + 0x846f866f, 0x846f826f, | |
| 2783 | + 0xbef6006f, 0xb8f83b05, | |
| 2784 | + 0x80788178, 0xbf0d9972, | |
| 2785 | + 0xbfa20002, 0x84788978, | |
| 2786 | + 0xbfa00001, 0x84788a78, | |
| 2787 | + 0xb8ee1e06, 0x846e8a6e, | |
| 2788 | + 0x80786e78, 0x8078ff78, | |
| 2789 | + 0x00000200, 0x8078ff78, | |
| 2790 | + 0x00000080, 0xbef600ff, | |
| 2791 | + 0x01000000, 0x857d9972, | |
| 2792 | + 0x8b7d817d, 0xbf06817d, | |
| 2793 | + 0xbefd0080, 0xbfa2000c, | |
| 2794 | + 0xe0500000, 0x781d0000, | |
| 2795 | + 0xbf8903f7, 0xdac00000, | |
| 2796 | + 0x00000000, 0x807dff7d, | |
| 2797 | + 0x00000080, 0x8078ff78, | |
| 2798 | + 0x00000080, 0xbf0a6f7d, | |
| 2799 | + 0xbfa2fff5, 0xbfa0000b, | |
| 2800 | + 0xe0500000, 0x781d0000, | |
| 2801 | + 0xbf8903f7, 0xdac00000, | |
| 2802 | + 0x00000000, 0x807dff7d, | |
| 2803 | + 0x00000100, 0x8078ff78, | |
| 2804 | + 0x00000100, 0xbf0a6f7d, | |
| 2805 | + 0xbfa2fff5, 0xbef80080, | |
| 2776 | 2806 | 0xbefe00c1, 0x857d9972, |
| 2777 | 2807 | 0x8b7d817d, 0xbf06817d, |
| 2778 | 2808 | 0xbfa20002, 0xbeff0080, |
| 2779 | 2809 | 0xbfa00001, 0xbeff00c1, |
| 2780 | − 0xb8ef4306, 0x8b6fc16f, | |
| 2781 | − 0xbfa1002f, 0x846f866f, | |
| 2782 | − 0x846f826f, 0xbef6006f, | |
| 2783 | − 0xb8f83b05, 0x80788178, | |
| 2784 | − 0xbf0d9972, 0xbfa20002, | |
| 2785 | − 0x84788978, 0xbfa00001, | |
| 2786 | − 0x84788a78, 0xb8ee1e06, | |
| 2787 | − 0x846e8a6e, 0x80786e78, | |
| 2810 | + 0xb8ef3b05, 0x806f816f, | |
| 2811 | + 0x846f826f, 0x857d9972, | |
| 2812 | + 0x8b7d817d, 0xbf06817d, | |
| 2813 | + 0xbfa20024, 0xbef600ff, | |
| 2814 | + 0x01000000, 0xbeee0078, | |
| 2788 | 2815 | 0x8078ff78, 0x00000200, |
| 2789 | − 0x8078ff78, 0x00000080, | |
| 2790 | − 0xbef600ff, 0x01000000, | |
| 2791 | − 0x857d9972, 0x8b7d817d, | |
| 2792 | − 0xbf06817d, 0xbefd0080, | |
| 2793 | − 0xbfa2000c, 0xe0500000, | |
| 2794 | − 0x781d0000, 0xbf8903f7, | |
| 2795 | − 0xdac00000, 0x00000000, | |
| 2796 | − 0x807dff7d, 0x00000080, | |
| 2797 | − 0x8078ff78, 0x00000080, | |
| 2798 | − 0xbf0a6f7d, 0xbfa2fff5, | |
| 2799 | − 0xbfa0000b, 0xe0500000, | |
| 2800 | − 0x781d0000, 0xbf8903f7, | |
| 2801 | − 0xdac00000, 0x00000000, | |
| 2802 | − 0x807dff7d, 0x00000100, | |
| 2803 | − 0x8078ff78, 0x00000100, | |
| 2804 | − 0xbf0a6f7d, 0xbfa2fff5, | |
| 2805 | − 0xbef80080, 0xbefe00c1, | |
| 2806 | − 0x857d9972, 0x8b7d817d, | |
| 2807 | − 0xbf06817d, 0xbfa20002, | |
| 2808 | − 0xbeff0080, 0xbfa00001, | |
| 2809 | − 0xbeff00c1, 0xb8ef3b05, | |
| 2810 | − 0x806f816f, 0x846f826f, | |
| 2811 | − 0x857d9972, 0x8b7d817d, | |
| 2812 | − 0xbf06817d, 0xbfa20024, | |
| 2813 | − 0xbef600ff, 0x01000000, | |
| 2814 | − 0xbeee0078, 0x8078ff78, | |
| 2815 | − 0x00000200, 0xbefd0084, | |
| 2816 | − 0xbf0a6f7d, 0xbfa10050, | |
| 2816 | + 0xbefd0084, 0xbf0a6f7d, | |
| 2817 | + 0xbfa10050, 0xe0505000, | |
| 2818 | + 0x781d0000, 0xe0505080, | |
| 2819 | + 0x781d0100, 0xe0505100, | |
| 2820 | + 0x781d0200, 0xe0505180, | |
| 2821 | + 0x781d0300, 0xbf8903f7, | |
| 2822 | + 0x7e008500, 0x7e028501, | |
| 2823 | + 0x7e048502, 0x7e068503, | |
| 2824 | + 0x807d847d, 0x8078ff78, | |
| 2825 | + 0x00000200, 0xbf0a6f7d, | |
| 2826 | + 0xbfa2ffee, 0xe0505000, | |
| 2827 | + 0x6e1d0000, 0xe0505080, | |
| 2828 | + 0x6e1d0100, 0xe0505100, | |
| 2829 | + 0x6e1d0200, 0xe0505180, | |
| 2830 | + 0x6e1d0300, 0xbf8903f7, | |
| 2831 | + 0xbfa00034, 0xbef600ff, | |
| 2832 | + 0x01000000, 0xbeee0078, | |
| 2833 | + 0x8078ff78, 0x00000400, | |
| 2834 | + 0xbefd0084, 0xbf0a6f7d, | |
| 2835 | + 0xbfa10012, 0xe0505000, | |
| 2836 | + 0x781d0000, 0xe0505100, | |
| 2837 | + 0x781d0100, 0xe0505200, | |
| 2838 | + 0x781d0200, 0xe0505300, | |
| 2839 | + 0x781d0300, 0xbf8903f7, | |
| 2840 | + 0x7e008500, 0x7e028501, | |
| 2841 | + 0x7e048502, 0x7e068503, | |
| 2842 | + 0x807d847d, 0x8078ff78, | |
| 2843 | + 0x00000400, 0xbf0a6f7d, | |
| 2844 | + 0xbfa2ffee, 0xb8ef1e06, | |
| 2845 | + 0x8b6fc16f, 0xbfa1000e, | |
| 2846 | + 0x846f836f, 0x806f7d6f, | |
| 2847 | + 0xbefe00c1, 0xbeff0080, | |
| 2817 | 2848 | 0xe0505000, 0x781d0000, |
| 2818 | − 0xe0505080, 0x781d0100, | |
| 2819 | − 0xe0505100, 0x781d0200, | |
| 2820 | − 0xe0505180, 0x781d0300, | |
| 2821 | 2849 | 0xbf8903f7, 0x7e008500, |
| 2822 | − 0x7e028501, 0x7e048502, | |
| 2823 | − 0x7e068503, 0x807d847d, | |
| 2824 | − 0x8078ff78, 0x00000200, | |
| 2825 | − 0xbf0a6f7d, 0xbfa2ffee, | |
| 2850 | + 0x807d817d, 0x8078ff78, | |
| 2851 | + 0x00000080, 0xbf0a6f7d, | |
| 2852 | + 0xbfa2fff7, 0xbeff00c1, | |
| 2826 | 2853 | 0xe0505000, 0x6e1d0000, |
| 2827 | − 0xe0505080, 0x6e1d0100, | |
| 2828 | − 0xe0505100, 0x6e1d0200, | |
| 2829 | − 0xe0505180, 0x6e1d0300, | |
| 2830 | − 0xbf8903f7, 0xbfa00034, | |
| 2831 | − 0xbef600ff, 0x01000000, | |
| 2832 | − 0xbeee0078, 0x8078ff78, | |
| 2833 | − 0x00000400, 0xbefd0084, | |
| 2834 | − 0xbf0a6f7d, 0xbfa10012, | |
| 2835 | − 0xe0505000, 0x781d0000, | |
| 2836 | − 0xe0505100, 0x781d0100, | |
| 2837 | − 0xe0505200, 0x781d0200, | |
| 2838 | − 0xe0505300, 0x781d0300, | |
| 2839 | − 0xbf8903f7, 0x7e008500, | |
| 2840 | − 0x7e028501, 0x7e048502, | |
| 2841 | − 0x7e068503, 0x807d847d, | |
| 2842 | − 0x8078ff78, 0x00000400, | |
| 2843 | − 0xbf0a6f7d, 0xbfa2ffee, | |
| 2844 | − 0xb8ef1e06, 0x8b6fc16f, | |
| 2845 | − 0xbfa1000e, 0x846f836f, | |
| 2846 | − 0x806f7d6f, 0xbefe00c1, | |
| 2847 | − 0xbeff0080, 0xe0505000, | |
| 2848 | − 0x781d0000, 0xbf8903f7, | |
| 2849 | − 0x7e008500, 0x807d817d, | |
| 2850 | − 0x8078ff78, 0x00000080, | |
| 2851 | − 0xbf0a6f7d, 0xbfa2fff7, | |
| 2852 | − 0xbeff00c1, 0xe0505000, | |
| 2853 | − 0x6e1d0000, 0xe0505100, | |
| 2854 | − 0x6e1d0100, 0xe0505200, | |
| 2855 | − 0x6e1d0200, 0xe0505300, | |
| 2856 | − 0x6e1d0300, 0xbf8903f7, | |
| 2854 | + 0xe0505100, 0x6e1d0100, | |
| 2855 | + 0xe0505200, 0x6e1d0200, | |
| 2856 | + 0xe0505300, 0x6e1d0300, | |
| 2857 | + 0xbf8903f7, 0xb8f83b05, | |
| 2858 | + 0x80788178, 0xbf0d9972, | |
| 2859 | + 0xbfa20002, 0x84788978, | |
| 2860 | + 0xbfa00001, 0x84788a78, | |
| 2861 | + 0xb8ee1e06, 0x846e8a6e, | |
| 2862 | + 0x80786e78, 0x8078ff78, | |
| 2863 | + 0x00000200, 0x80f8ff78, | |
| 2864 | + 0x00000050, 0xbef600ff, | |
| 2865 | + 0x01000000, 0xbefd00ff, | |
| 2866 | + 0x0000006c, 0x80f89078, | |
| 2867 | + 0xf428403a, 0xf0000000, | |
| 2868 | + 0xbf89fc07, 0x80fd847d, | |
| 2869 | + 0xbf800000, 0xbe804300, | |
| 2870 | + 0xbe824302, 0x80f8a078, | |
| 2871 | + 0xf42c403a, 0xf0000000, | |
| 2872 | + 0xbf89fc07, 0x80fd887d, | |
| 2873 | + 0xbf800000, 0xbe804300, | |
| 2874 | + 0xbe824302, 0xbe844304, | |
| 2875 | + 0xbe864306, 0x80f8c078, | |
| 2876 | + 0xf430403a, 0xf0000000, | |
| 2877 | + 0xbf89fc07, 0x80fd907d, | |
| 2878 | + 0xbf800000, 0xbe804300, | |
| 2879 | + 0xbe824302, 0xbe844304, | |
| 2880 | + 0xbe864306, 0xbe884308, | |
| 2881 | + 0xbe8a430a, 0xbe8c430c, | |
| 2882 | + 0xbe8e430e, 0xbf06807d, | |
| 2883 | + 0xbfa1fff0, 0xb980f801, | |
| 2884 | + 0x00000000, 0xbfbd0000, | |
| 2857 | 2885 | 0xb8f83b05, 0x80788178, |
| 2858 | 2886 | 0xbf0d9972, 0xbfa20002, |
| 2859 | 2887 | 0x84788978, 0xbfa00001, |
| 2860 | 2888 | 0x84788a78, 0xb8ee1e06, |
| 2861 | 2889 | 0x846e8a6e, 0x80786e78, |
| 2862 | 2890 | 0x8078ff78, 0x00000200, |
| 2863 | − 0x80f8ff78, 0x00000050, | |
| 2864 | 2891 | 0xbef600ff, 0x01000000, |
| 2865 | − 0xbefd00ff, 0x0000006c, | |
| 2866 | − 0x80f89078, 0xf428403a, | |
| 2867 | − 0xf0000000, 0xbf89fc07, | |
| 2868 | − 0x80fd847d, 0xbf800000, | |
| 2869 | − 0xbe804300, 0xbe824302, | |
| 2870 | − 0x80f8a078, 0xf42c403a, | |
| 2871 | − 0xf0000000, 0xbf89fc07, | |
| 2872 | − 0x80fd887d, 0xbf800000, | |
| 2873 | − 0xbe804300, 0xbe824302, | |
| 2874 | − 0xbe844304, 0xbe864306, | |
| 2875 | − 0x80f8c078, 0xf430403a, | |
| 2876 | − 0xf0000000, 0xbf89fc07, | |
| 2877 | − 0x80fd907d, 0xbf800000, | |
| 2878 | − 0xbe804300, 0xbe824302, | |
| 2879 | − 0xbe844304, 0xbe864306, | |
| 2880 | − 0xbe884308, 0xbe8a430a, | |
| 2881 | − 0xbe8c430c, 0xbe8e430e, | |
| 2882 | − 0xbf06807d, 0xbfa1fff0, | |
| 2883 | − 0xb980f801, 0x00000000, | |
| 2884 | − 0xbfbd0000, 0xb8f83b05, | |
| 2885 | − 0x80788178, 0xbf0d9972, | |
| 2886 | − 0xbfa20002, 0x84788978, | |
| 2887 | − 0xbfa00001, 0x84788a78, | |
| 2888 | − 0xb8ee1e06, 0x846e8a6e, | |
| 2889 | − 0x80786e78, 0x8078ff78, | |
| 2890 | − 0x00000200, 0xbef600ff, | |
| 2891 | − 0x01000000, 0xf4205bfa, | |
| 2892 | + 0xf4205bfa, 0xf0000000, | |
| 2893 | + 0x80788478, 0xf4205b3a, | |
| 2892 | 2894 | 0xf0000000, 0x80788478, |
| 2893 | − 0xf4205b3a, 0xf0000000, | |
| 2894 | − 0x80788478, 0xf4205b7a, | |
| 2895 | + 0xf4205b7a, 0xf0000000, | |
| 2896 | + 0x80788478, 0xf4205c3a, | |
| 2895 | 2897 | 0xf0000000, 0x80788478, |
| 2896 | − 0xf4205c3a, 0xf0000000, | |
| 2897 | − 0x80788478, 0xf4205c7a, | |
| 2898 | + 0xf4205c7a, 0xf0000000, | |
| 2899 | + 0x80788478, 0xf4205eba, | |
| 2898 | 2900 | 0xf0000000, 0x80788478, |
| 2899 | − 0xf4205eba, 0xf0000000, | |
| 2900 | − 0x80788478, 0xf4205efa, | |
| 2901 | + 0xf4205efa, 0xf0000000, | |
| 2902 | + 0x80788478, 0xf4205e7a, | |
| 2901 | 2903 | 0xf0000000, 0x80788478, |
| 2902 | − 0xf4205e7a, 0xf0000000, | |
| 2903 | − 0x80788478, 0xf4205cfa, | |
| 2904 | + 0xf4205cfa, 0xf0000000, | |
| 2905 | + 0x80788478, 0xf4205bba, | |
| 2904 | 2906 | 0xf0000000, 0x80788478, |
| 2907 | + 0xbf89fc07, 0xb96ef814, | |
| 2905 | 2908 | 0xf4205bba, 0xf0000000, |
| 2906 | 2909 | 0x80788478, 0xbf89fc07, |
| 2907 | − 0xb96ef814, 0xf4205bba, | |
| 2908 | − 0xf0000000, 0x80788478, | |
| 2909 | − 0xbf89fc07, 0xb96ef815, | |
| 2910 | − 0xbefd006f, 0xbefe0070, | |
| 2911 | − 0xbeff0071, 0x8b6f7bff, | |
| 2912 | − 0x000003ff, 0xb96f4803, | |
| 2913 | − 0x8b6f7bff, 0xfffff800, | |
| 2914 | − 0x856f8b6f, 0xb96fa2c3, | |
| 2915 | − 0xb973f801, 0xb8ee3b05, | |
| 2916 | − 0x806e816e, 0xbf0d9972, | |
| 2917 | − 0xbfa20002, 0x846e896e, | |
| 2918 | − 0xbfa00001, 0x846e8a6e, | |
| 2919 | − 0xb8ef1e06, 0x846f8a6f, | |
| 2920 | − 0x806e6f6e, 0x806eff6e, | |
| 2921 | − 0x00000200, 0x806e746e, | |
| 2922 | − 0x826f8075, 0x8b6fff6f, | |
| 2923 | − 0x0000ffff, 0xf4085c37, | |
| 2924 | − 0xf8000050, 0xf4085d37, | |
| 2925 | − 0xf8000060, 0xf4005e77, | |
| 2926 | − 0xf8000074, 0xbf89fc07, | |
| 2927 | − 0x8b6dff6d, 0x0000ffff, | |
| 2928 | − 0x8bfe7e7e, 0x8bea6a6a, | |
| 2910 | + 0xb96ef815, 0xbefd006f, | |
| 2911 | + 0xbefe0070, 0xbeff0071, | |
| 2912 | + 0x8b6f7bff, 0x000003ff, | |
| 2913 | + 0xb96f4803, 0x8b6f7bff, | |
| 2914 | + 0xfffff800, 0x856f8b6f, | |
| 2915 | + 0xb96fa2c3, 0xb973f801, | |
| 2916 | + 0xb8ee3b05, 0x806e816e, | |
| 2917 | + 0xbf0d9972, 0xbfa20002, | |
| 2918 | + 0x846e896e, 0xbfa00001, | |
| 2919 | + 0x846e8a6e, 0xb8ef1e06, | |
| 2920 | + 0x846f8a6f, 0x806e6f6e, | |
| 2921 | + 0x806eff6e, 0x00000200, | |
| 2922 | + 0x806e746e, 0x826f8075, | |
| 2923 | + 0x8b6fff6f, 0x0000ffff, | |
| 2924 | + 0xf4085c37, 0xf8000050, | |
| 2925 | + 0xf4085d37, 0xf8000060, | |
| 2926 | + 0xf4005e77, 0xf8000074, | |
| 2927 | + 0xbf89fc07, 0x8b6dff6d, | |
| 2928 | + 0x0000ffff, 0x8bfe7e7e, | |
| 2929 | + 0x8bea6a6a, 0xb8eef802, | |
| 2930 | + 0xbf0d866e, 0xbfa20002, | |
| 2931 | + 0xb97af802, 0xbe80486c, | |
| 2929 | 2932 | 0xb97af802, 0xbe804a6c, |
| 2930 | 2933 | 0xbfb00000, 0xbf9f0000, |
| 2931 | 2934 | 0xbf9f0000, 0xbf9f0000, |
| @@ -43,12 +43,14 @@ · 42 unmodified lines | ||
| 43 | 43 | #define HAVE_XNACK (ASIC_FAMILY < CHIP_SIENNA_CICHLID) |
| 44 | 44 | #define HAVE_SENDMSG_RTN (ASIC_FAMILY >= CHIP_PLUM_BONITO) |
| 45 | 45 | #define HAVE_BUFFER_LDS_LOAD (ASIC_FAMILY < CHIP_PLUM_BONITO) |
| 46 | +#define SW_SA_TRAP (ASIC_FAMILY >= CHIP_PLUM_BONITO) | |
| 46 | 47 | |
| 47 | 48 | var SINGLE_STEP_MISSED_WORKAROUND = 1 //workaround for lost MODE.DEBUG_EN exception when SAVECTX raised |
| 48 | 49 | |
| 49 | 50 | var SQ_WAVE_STATUS_SPI_PRIO_MASK = 0x00000006 |
| 50 | 51 | var SQ_WAVE_STATUS_HALT_MASK = 0x2000 |
| 51 | 52 | var SQ_WAVE_STATUS_ECC_ERR_MASK = 0x20000 |
| 53 | +var SQ_WAVE_STATUS_TRAP_EN_SHIFT = 6 | |
| 52 | 54 | |
| 53 | 55 | var SQ_WAVE_LDS_ALLOC_LDS_SIZE_SHIFT = 12 |
| 54 | 56 | var SQ_WAVE_LDS_ALLOC_LDS_SIZE_SIZE = 9 |
| @@ -183,6 +185,13 @@ L_SKIP_RESTORE: · 128 unmodified lines | ||
| 183 | 185 | |
| 184 | 186 | s_getreg_b32 s_save_trapsts, hwreg(HW_REG_TRAPSTS) |
| 185 | 187 | |
| 188 | +#if SW_SA_TRAP | |
| 189 | + // If ttmp1[31] is set then trap may occur early. | |
| 190 | + // Spin wait until SAVECTX exception is raised. | |
| 191 | + s_bitcmp1_b32 s_save_pc_hi, 31 | |
| 192 | + s_cbranch_scc1 L_CHECK_SAVE | |
| 193 | +#endif | |
| 194 | + | |
| 186 | 195 | s_and_b32 ttmp2, s_save_status, SQ_WAVE_STATUS_HALT_MASK |
| 187 | 196 | s_cbranch_scc0 L_NOT_HALTED |
| 188 | 197 | |
| @@ -1061,8 +1070,20 @@ L_RESTORE_HWREG: · 872 unmodified lines | ||
| 1061 | 1070 | s_and_b32 s_restore_pc_hi, s_restore_pc_hi, 0x0000ffff //pc[47:32] //Do it here in order not to affect STATUS |
| 1062 | 1071 | s_and_b64 exec, exec, exec // Restore STATUS.EXECZ, not writable by s_setreg_b32 |
| 1063 | 1072 | s_and_b64 vcc, vcc, vcc // Restore STATUS.VCCZ, not writable by s_setreg_b32 |
| 1073 | + | |
| 1074 | +#if SW_SA_TRAP | |
| 1075 | + // If traps are enabled then return to the shader with PRIV=0. | |
| 1076 | + // Otherwise retain PRIV=1 for subsequent context save requests. | |
| 1077 | + s_getreg_b32 s_restore_tmp, hwreg(HW_REG_STATUS) | |
| 1078 | + s_bitcmp1_b32 s_restore_tmp, SQ_WAVE_STATUS_TRAP_EN_SHIFT | |
| 1079 | + s_cbranch_scc1 L_RETURN_WITHOUT_PRIV | |
| 1080 | + | |
| 1064 | 1081 | s_setreg_b32 hwreg(HW_REG_STATUS), s_restore_status // SCC is included, which is changed by previous salu |
| 1082 | + s_setpc_b64 [s_restore_pc_lo, s_restore_pc_hi] | |
| 1083 | +L_RETURN_WITHOUT_PRIV: | |
| 1084 | +#endif | |
| 1065 | 1085 | |
| 1086 | + s_setreg_b32 hwreg(HW_REG_STATUS), s_restore_status // SCC is included, which is changed by previous salu | |
| 1066 | 1087 | s_rfe_b64 s_restore_pc_lo //Return to the main shader program and resume execution |
| 1067 | 1088 | |
| 1068 | 1089 | L_END_PGM: |
| @@ -327,6 +327,12 @@ static int kfd_ioctl_create_queue(struct file *filep, struct kfd_process *p, · 326 unmodified lines | ||
| 327 | 327 | goto err_bind_process; |
| 328 | 328 | } |
| 329 | 329 | |
| 330 | + if (!pdd->doorbell_index && | |
| 331 | + kfd_alloc_process_doorbells(dev, &pdd->doorbell_index) < 0) { | |
| 332 | + err = -ENOMEM; | |
| 333 | + goto err_alloc_doorbells; | |
| 334 | + } | |
| 335 | + | |
| 330 | 336 | /* Starting with GFX11, wptr BOs must be mapped to GART for MES to determine work |
| 331 | 337 | * on unmapped queues for usermode queue oversubscription (no aggregated doorbell) |
| 332 | 338 | */ |
| @@ -404,6 +410,7 @@ err_create_queue: · 71 unmodified lines | ||
| 404 | 410 | if (wptr_bo) |
| 405 | 411 | amdgpu_amdkfd_free_gtt_mem(dev->adev, wptr_bo); |
| 406 | 412 | err_wptr_map_gart: |
| 413 | +err_alloc_doorbells: | |
| 407 | 414 | err_bind_process: |
| 408 | 415 | err_pdd: |
| 409 | 416 | mutex_unlock(&p->mutex); |
| @@ -869,14 +876,11 @@ static int kfd_ioctl_wait_events(struct file *filp, struct kfd_process *p, · 459 unmodified lines | ||
| 869 | 876 | void *data) |
| 870 | 877 | { |
| 871 | 878 | struct kfd_ioctl_wait_events_args *args = data; |
| 872 | − int err; | |
| 873 | 879 | |
| 874 | − err = kfd_wait_on_events(p, args->num_events, | |
| 880 | + return kfd_wait_on_events(p, args->num_events, | |
| 875 | 881 | (void __user *)args->events_ptr, |
| 876 | 882 | (args->wait_for_all != 0), |
| 877 | 883 | &args->timeout, &args->wait_result); |
| 878 | − | |
| 879 | − return err; | |
| 880 | 884 | } |
| 881 | 885 | static int kfd_ioctl_set_scratch_backing_va(struct file *filep, |
| 882 | 886 | struct kfd_process *p, void *data) |
| @@ -1092,6 +1096,10 @@ static int kfd_ioctl_alloc_memory_of_gpu(struct file *filep, · 209 unmodified lines | ||
| 1092 | 1096 | goto err_unlock; |
| 1093 | 1097 | } |
| 1094 | 1098 | offset = kfd_get_process_doorbells(pdd); |
| 1099 | + if (!offset) { | |
| 1100 | + err = -ENOMEM; | |
| 1101 | + goto err_unlock; | |
| 1102 | + } | |
| 1095 | 1103 | } else if (flags & KFD_IOC_ALLOC_MEM_FLAGS_MMIO_REMAP) { |
| 1096 | 1104 | if (args->size != PAGE_SIZE) { |
| 1097 | 1105 | err = -EINVAL; |
| @@ -1576,6 +1584,8 @@ static int kfd_ioctl_smi_events(struct file *filep, · 478 unmodified lines | ||
| 1576 | 1584 | return kfd_smi_event_open(pdd->dev, &args->anon_fd); |
| 1577 | 1585 | } |
| 1578 | 1586 | |
| 1587 | +#if IS_ENABLED(CONFIG_HSA_AMD_SVM) | |
| 1588 | + | |
| 1579 | 1589 | static int kfd_ioctl_set_xnack_mode(struct file *filep, |
| 1580 | 1590 | struct kfd_process *p, void *data) |
| 1581 | 1591 | { |
| @@ -1586,22 +1596,29 @@ static int kfd_ioctl_set_xnack_mode(struct file *filep, · 4 unmodified lines | ||
| 1586 | 1596 | if (args->xnack_enabled >= 0) { |
| 1587 | 1597 | if (!list_empty(&p->pqm.queues)) { |
| 1588 | 1598 | pr_debug("Process has user queues running\n"); |
| 1589 | − mutex_unlock(&p->mutex); | |
| 1590 | − return -EBUSY; | |
| 1599 | + r = -EBUSY; | |
| 1600 | + goto out_unlock; | |
| 1591 | 1601 | } |
| 1592 | − if (args->xnack_enabled && !kfd_process_xnack_mode(p, true)) | |
| 1602 | + | |
| 1603 | + if (p->xnack_enabled == args->xnack_enabled) | |
| 1604 | + goto out_unlock; | |
| 1605 | + | |
| 1606 | + if (args->xnack_enabled && !kfd_process_xnack_mode(p, true)) { | |
| 1593 | 1607 | r = -EPERM; |
| 1594 | − else | |
| 1595 | − p->xnack_enabled = args->xnack_enabled; | |
| 1608 | + goto out_unlock; | |
| 1609 | + } | |
| 1610 | + | |
| 1611 | + r = svm_range_switch_xnack_reserve_mem(p, args->xnack_enabled); | |
| 1596 | 1612 | } else { |
| 1597 | 1613 | args->xnack_enabled = p->xnack_enabled; |
| 1598 | 1614 | } |
| 1615 | + | |
| 1616 | +out_unlock: | |
| 1599 | 1617 | mutex_unlock(&p->mutex); |
| 1600 | 1618 | |
| 1601 | 1619 | return r; |
| 1602 | 1620 | } |
| 1603 | 1621 | |
| 1604 | −#if IS_ENABLED(CONFIG_HSA_AMD_SVM) | |
| 1605 | 1622 | static int kfd_ioctl_svm(struct file *filep, struct kfd_process *p, void *data) |
| 1606 | 1623 | { |
| 1607 | 1624 | struct kfd_ioctl_svm_args *args = data; |
| @@ -1621,6 +1638,11 @@ static int kfd_ioctl_svm(struct file *filep, struct kfd_process *p, void *data) · 13 unmodified lines | ||
| 1621 | 1638 | return r; |
| 1622 | 1639 | } |
| 1623 | 1640 | #else |
| 1641 | +static int kfd_ioctl_set_xnack_mode(struct file *filep, | |
| 1642 | + struct kfd_process *p, void *data) | |
| 1643 | +{ | |
| 1644 | + return -EPERM; | |
| 1645 | +} | |
| 1624 | 1646 | static int kfd_ioctl_svm(struct file *filep, struct kfd_process *p, void *data) |
| 1625 | 1647 | { |
| 1626 | 1648 | return -EPERM; |
| @@ -2145,6 +2167,12 @@ static int criu_restore_devices(struct kfd_process *p, · 518 unmodified lines | ||
| 2145 | 2167 | ret = PTR_ERR(pdd); |
| 2146 | 2168 | goto exit; |
| 2147 | 2169 | } |
| 2170 | + | |
| 2171 | + if (!pdd->doorbell_index && | |
| 2172 | + kfd_alloc_process_doorbells(pdd->dev, &pdd->doorbell_index) < 0) { | |
| 2173 | + ret = -ENOMEM; | |
| 2174 | + goto exit; | |
| 2175 | + } | |
| 2148 | 2176 | } |
| 2149 | 2177 | |
| 2150 | 2178 | /* |
| @@ -2173,6 +2201,8 @@ static int criu_restore_memory_of_gpu(struct kfd_process_device *pdd, · 22 unmodified lines | ||
| 2173 | 2201 | return -EINVAL; |
| 2174 | 2202 | |
| 2175 | 2203 | offset = kfd_get_process_doorbells(pdd); |
| 2204 | + if (!offset) | |
| 2205 | + return -ENOMEM; | |
| 2176 | 2206 | } else if (bo_bucket->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_MMIO_REMAP) { |
| 2177 | 2207 | /* MMIO BOs need remapped bus address */ |
| 2178 | 2208 | if (bo_bucket->size != PAGE_SIZE) { |
| @@ -2847,7 +2877,6 @@ static int kfd_mmio_mmap(struct kfd_dev *dev, struct kfd_process *process, · 668 unmodified lines | ||
| 2847 | 2877 | struct vm_area_struct *vma) |
| 2848 | 2878 | { |
| 2849 | 2879 | phys_addr_t address; |
| 2850 | − int ret; | |
| 2851 | 2880 | |
| 2852 | 2881 | if (vma->vm_end - vma->vm_start != PAGE_SIZE) |
| 2853 | 2882 | return -EINVAL; |
| @@ -2867,12 +2896,11 @@ static int kfd_mmio_mmap(struct kfd_dev *dev, struct kfd_process *process, · 13 unmodified lines | ||
| 2867 | 2896 | process->pasid, (unsigned long long) vma->vm_start, |
| 2868 | 2897 | address, vma->vm_flags, PAGE_SIZE); |
| 2869 | 2898 | |
| 2870 | − ret = io_remap_pfn_range(vma, | |
| 2899 | + return io_remap_pfn_range(vma, | |
| 2871 | 2900 | vma->vm_start, |
| 2872 | 2901 | address >> PAGE_SHIFT, |
| 2873 | 2902 | PAGE_SIZE, |
| 2874 | 2903 | vma->vm_page_prot); |
| 2875 | − return ret; | |
| 2876 | 2904 | } |
| 2877 | 2905 | |
| 2878 | 2906 | |
| @@ -1522,6 +1522,7 @@ static int kfd_fill_gpu_cache_info(struct kfd_dev *kdev, · 1521 unmodified lines | ||
| 1522 | 1522 | case IP_VERSION(11, 0, 0): |
| 1523 | 1523 | case IP_VERSION(11, 0, 1): |
| 1524 | 1524 | case IP_VERSION(11, 0, 2): |
| 1525 | + case IP_VERSION(11, 0, 3): | |
| 1525 | 1526 | pcache_info = cache_info; |
| 1526 | 1527 | num_of_cache_types = |
| 1527 | 1528 | kfd_fill_gpu_cache_info_from_gfx_config(kdev, pcache_info); |
| @@ -2283,7 +2284,7 @@ static int kfd_create_vcrat_image_gpu(void *pcrat_image, · 755 unmodified lines | ||
| 2283 | 2284 | |
| 2284 | 2285 | /* Fill in Subtype: IO_LINKS |
| 2285 | 2286 | * Only direct links are added here which is Link from GPU to |
| 2286 | − * to its NUMA node. Indirect links are added by userspace. | |
| 2287 | + * its NUMA node. Indirect links are added by userspace. | |
| 2287 | 2288 | */ |
| 2288 | 2289 | sub_type_hdr = (typeof(sub_type_hdr))((char *)sub_type_hdr + |
| 2289 | 2290 | cache_mem_filled); |
| @@ -91,6 +91,7 @@ static void kfd_device_info_set_sdma_info(struct kfd_dev *kfd) · 90 unmodified lines | ||
| 91 | 91 | case IP_VERSION(6, 0, 0): |
| 92 | 92 | case IP_VERSION(6, 0, 1): |
| 93 | 93 | case IP_VERSION(6, 0, 2): |
| 94 | + case IP_VERSION(6, 0, 3): | |
| 94 | 95 | kfd->device_info.num_sdma_queues_per_engine = 8; |
| 95 | 96 | break; |
| 96 | 97 | default: |
| @@ -103,6 +104,7 @@ static void kfd_device_info_set_sdma_info(struct kfd_dev *kfd) · 6 unmodified lines | ||
| 103 | 104 | switch (sdma_version) { |
| 104 | 105 | case IP_VERSION(6, 0, 0): |
| 105 | 106 | case IP_VERSION(6, 0, 2): |
| 107 | + case IP_VERSION(6, 0, 3): | |
| 106 | 108 | /* Reserve 1 for paging and 1 for gfx */ |
| 107 | 109 | kfd->device_info.num_reserved_sdma_queues_per_engine = 2; |
| 108 | 110 | /* BIT(0)=engine-0 queue-0; BIT(1)=engine-1 queue-0; BIT(2)=engine-0 queue-1; ... */ |
| @@ -150,6 +152,7 @@ static void kfd_device_info_set_event_interrupt_class(struct kfd_dev *kfd) · 41 unmodified lines | ||
| 150 | 152 | case IP_VERSION(11, 0, 0): |
| 151 | 153 | case IP_VERSION(11, 0, 1): |
| 152 | 154 | case IP_VERSION(11, 0, 2): |
| 155 | + case IP_VERSION(11, 0, 3): | |
| 153 | 156 | kfd->device_info.event_interrupt_class = &event_interrupt_class_v11; |
| 154 | 157 | break; |
| 155 | 158 | default: |
| @@ -399,6 +402,11 @@ struct kfd_dev *kgd2kfd_probe(struct amdgpu_device *adev, bool vf) · 243 unmodified lines | ||
| 399 | 402 | gfx_target_version = 110002; |
| 400 | 403 | f2g = &gfx_v11_kfd2kgd; |
| 401 | 404 | break; |
| 405 | + case IP_VERSION(11, 0, 3): | |
| 406 | + /* Note: Compiler version is 11.0.1 while HW version is 11.0.3 */ | |
| 407 | + gfx_target_version = 110001; | |
| 408 | + f2g = &gfx_v11_kfd2kgd; | |
| 409 | + break; | |
| 402 | 410 | default: |
| 403 | 411 | break; |
| 404 | 412 | } |
| @@ -1242,6 +1242,24 @@ static void init_interrupts(struct device_queue_manager *dqm) · 1241 unmodified lines | ||
| 1242 | 1242 | dqm->dev->kfd2kgd->init_interrupts(dqm->dev->adev, i); |
| 1243 | 1243 | } |
| 1244 | 1244 | |
| 1245 | +static void init_sdma_bitmaps(struct device_queue_manager *dqm) | |
| 1246 | +{ | |
| 1247 | + unsigned int num_sdma_queues = | |
| 1248 | + min_t(unsigned int, sizeof(dqm->sdma_bitmap)*8, | |
| 1249 | + get_num_sdma_queues(dqm)); | |
| 1250 | + unsigned int num_xgmi_sdma_queues = | |
| 1251 | + min_t(unsigned int, sizeof(dqm->xgmi_sdma_bitmap)*8, | |
| 1252 | + get_num_xgmi_sdma_queues(dqm)); | |
| 1253 | + | |
| 1254 | + if (num_sdma_queues) | |
| 1255 | + dqm->sdma_bitmap = GENMASK_ULL(num_sdma_queues-1, 0); | |
| 1256 | + if (num_xgmi_sdma_queues) | |
| 1257 | + dqm->xgmi_sdma_bitmap = GENMASK_ULL(num_xgmi_sdma_queues-1, 0); | |
| 1258 | + | |
| 1259 | + dqm->sdma_bitmap &= ~get_reserved_sdma_queues_bitmap(dqm); | |
| 1260 | + pr_info("sdma_bitmap: %llx\n", dqm->sdma_bitmap); | |
| 1261 | +} | |
| 1262 | + | |
| 1245 | 1263 | static int initialize_nocpsch(struct device_queue_manager *dqm) |
| 1246 | 1264 | { |
| 1247 | 1265 | int pipe, queue; |
| @@ -1270,11 +1288,7 @@ static int initialize_nocpsch(struct device_queue_manager *dqm) · 22 unmodified lines | ||
| 1270 | 1288 | |
| 1271 | 1289 | memset(dqm->vmid_pasid, 0, sizeof(dqm->vmid_pasid)); |
| 1272 | 1290 | |
| 1273 | − dqm->sdma_bitmap = ~0ULL >> (64 - get_num_sdma_queues(dqm)); | |
| 1274 | − dqm->sdma_bitmap &= ~(get_reserved_sdma_queues_bitmap(dqm)); | |
| 1275 | − pr_info("sdma_bitmap: %llx\n", dqm->sdma_bitmap); | |
| 1276 | − | |
| 1277 | − dqm->xgmi_sdma_bitmap = ~0ULL >> (64 - get_num_xgmi_sdma_queues(dqm)); | |
| 1291 | + init_sdma_bitmaps(dqm); | |
| 1278 | 1292 | |
| 1279 | 1293 | return 0; |
| 1280 | 1294 | } |
| @@ -1452,9 +1466,6 @@ static int set_sched_resources(struct device_queue_manager *dqm) · 171 unmodified lines | ||
| 1452 | 1466 | |
| 1453 | 1467 | static int initialize_cpsch(struct device_queue_manager *dqm) |
| 1454 | 1468 | { |
| 1455 | − uint64_t num_sdma_queues; | |
| 1456 | − uint64_t num_xgmi_sdma_queues; | |
| 1457 | − | |
| 1458 | 1469 | pr_debug("num of pipes: %d\n", get_pipes_per_mec(dqm)); |
| 1459 | 1470 | |
| 1460 | 1471 | mutex_init(&dqm->lock_hidden); |
| @@ -1463,24 +1474,10 @@ static int initialize_cpsch(struct device_queue_manager *dqm) · 2 unmodified lines | ||
| 1463 | 1474 | dqm->active_cp_queue_count = 0; |
| 1464 | 1475 | dqm->gws_queue_count = 0; |
| 1465 | 1476 | dqm->active_runlist = false; |
| 1466 | − | |
| 1467 | − num_sdma_queues = get_num_sdma_queues(dqm); | |
| 1468 | − if (num_sdma_queues >= BITS_PER_TYPE(dqm->sdma_bitmap)) | |
| 1469 | − dqm->sdma_bitmap = ULLONG_MAX; | |
| 1470 | − else | |
| 1471 | − dqm->sdma_bitmap = (BIT_ULL(num_sdma_queues) - 1); | |
| 1472 | − | |
| 1473 | − dqm->sdma_bitmap &= ~(get_reserved_sdma_queues_bitmap(dqm)); | |
| 1474 | − pr_info("sdma_bitmap: %llx\n", dqm->sdma_bitmap); | |
| 1475 | − | |
| 1476 | − num_xgmi_sdma_queues = get_num_xgmi_sdma_queues(dqm); | |
| 1477 | − if (num_xgmi_sdma_queues >= BITS_PER_TYPE(dqm->xgmi_sdma_bitmap)) | |
| 1478 | − dqm->xgmi_sdma_bitmap = ULLONG_MAX; | |
| 1479 | − else | |
| 1480 | − dqm->xgmi_sdma_bitmap = (BIT_ULL(num_xgmi_sdma_queues) - 1); | |
| 1481 | − | |
| 1482 | 1477 | INIT_WORK(&dqm->hw_exception_work, kfd_process_hw_exception); |
| 1483 | 1478 | |
| 1479 | + init_sdma_bitmaps(dqm); | |
| 1480 | + | |
| 1484 | 1481 | return 0; |
| 1485 | 1482 | } |
| 1486 | 1483 | |
| @@ -157,6 +157,8 @@ int kfd_doorbell_mmap(struct kfd_dev *dev, struct kfd_process *process, · 156 unmodified lines | ||
| 157 | 157 | |
| 158 | 158 | /* Calculate physical address of doorbell */ |
| 159 | 159 | address = kfd_get_process_doorbells(pdd); |
| 160 | + if (!address) | |
| 161 | + return -ENOMEM; | |
| 160 | 162 | vma->vm_flags |= VM_IO | VM_DONTCOPY | VM_DONTEXPAND | VM_NORESERVE | |
| 161 | 163 | VM_DONTDUMP | VM_PFNMAP; |
| 162 | 164 | |
| @@ -275,6 +277,13 @@ uint64_t kfd_get_number_elems(struct kfd_dev *kfd) · 112 unmodified lines | ||
| 275 | 277 | |
| 276 | 278 | phys_addr_t kfd_get_process_doorbells(struct kfd_process_device *pdd) |
| 277 | 279 | { |
| 280 | + if (!pdd->doorbell_index) { | |
| 281 | + int r = kfd_alloc_process_doorbells(pdd->dev, | |
| 282 | + &pdd->doorbell_index); | |
| 283 | + if (r) | |
| 284 | + return 0; | |
| 285 | + } | |
| 286 | + | |
| 278 | 287 | return pdd->dev->doorbell_base + |
| 279 | 288 | pdd->doorbell_index * kfd_doorbell_process_slice(pdd->dev); |
| 280 | 289 | } |
| @@ -294,6 +303,9 @@ int kfd_alloc_process_doorbells(struct kfd_dev *kfd, unsigned int *doorbell_inde · 13 unmodified lines | ||
| 294 | 303 | if (r > 0) |
| 295 | 304 | *doorbell_index = r; |
| 296 | 305 | |
| 306 | + if (r < 0) | |
| 307 | + pr_err("Failed to allocate process doorbells\n"); | |
| 308 | + | |
| 297 | 309 | return r; |
| 298 | 310 | } |
| 299 | 311 | |
| @@ -322,12 +322,13 @@ svm_migrate_copy_to_vram(struct amdgpu_device *adev, struct svm_range *prange, · 321 unmodified lines | ||
| 322 | 322 | for (i = j = 0; i < npages; i++) { |
| 323 | 323 | struct page *spage; |
| 324 | 324 | |
| 325 | + dst[i] = cursor.start + (j << PAGE_SHIFT); | |
| 326 | + migrate->dst[i] = svm_migrate_addr_to_pfn(adev, dst[i]); | |
| 327 | + svm_migrate_get_vram_page(prange, migrate->dst[i]); | |
| 328 | + migrate->dst[i] = migrate_pfn(migrate->dst[i]); | |
| 329 | + | |
| 325 | 330 | spage = migrate_pfn_to_page(migrate->src[i]); |
| 326 | 331 | if (spage && !is_zone_device_page(spage)) { |
| 327 | − dst[i] = cursor.start + (j << PAGE_SHIFT); | |
| 328 | − migrate->dst[i] = svm_migrate_addr_to_pfn(adev, dst[i]); | |
| 329 | − svm_migrate_get_vram_page(prange, migrate->dst[i]); | |
| 330 | − migrate->dst[i] = migrate_pfn(migrate->dst[i]); | |
| 331 | 332 | src[i] = dma_map_page(dev, spage, 0, PAGE_SIZE, |
| 332 | 333 | DMA_TO_DEVICE); |
| 333 | 334 | r = dma_mapping_error(dev, src[i]); |
| @@ -522,9 +523,6 @@ svm_migrate_ram_to_vram(struct svm_range *prange, uint32_t best_loc, · 188 unmodified lines | ||
| 522 | 523 | pr_debug("svms 0x%p [0x%lx 0x%lx] to gpu 0x%x\n", prange->svms, |
| 523 | 524 | prange->start, prange->last, best_loc); |
| 524 | 525 | |
| 525 | − /* FIXME: workaround for page locking bug with invalid pages */ | |
| 526 | − svm_range_prefault(prange, mm, SVM_ADEV_PGMAP_OWNER(adev)); | |
| 527 | − | |
| 528 | 526 | start = prange->start << PAGE_SHIFT; |
| 529 | 527 | end = (prange->last + 1) << PAGE_SHIFT; |
| 530 | 528 | |
| @@ -886,7 +884,7 @@ svm_migrate_to_vram(struct svm_range *prange, uint32_t best_loc, · 355 unmodified lines | ||
| 886 | 884 | static vm_fault_t svm_migrate_to_ram(struct vm_fault *vmf) |
| 887 | 885 | { |
| 888 | 886 | unsigned long addr = vmf->address; |
| 889 | − struct vm_area_struct *vma; | |
| 887 | + struct svm_range_bo *svm_bo; | |
| 890 | 888 | enum svm_work_list_ops op; |
| 891 | 889 | struct svm_range *parent; |
| 892 | 890 | struct svm_range *prange; |
| @@ -894,29 +892,42 @@ static vm_fault_t svm_migrate_to_ram(struct vm_fault *vmf) · 1 unmodified line | ||
| 894 | 892 | struct mm_struct *mm; |
| 895 | 893 | int r = 0; |
| 896 | 894 | |
| 897 | − vma = vmf->vma; | |
| 898 | − mm = vma->vm_mm; | |
| 895 | + svm_bo = vmf->page->zone_device_data; | |
| 896 | + if (!svm_bo) { | |
| 897 | + pr_debug("failed get device page at addr 0x%lx\n", addr); | |
| 898 | + return VM_FAULT_SIGBUS; | |
| 899 | + } | |
| 900 | + if (!mmget_not_zero(svm_bo->eviction_fence->mm)) { | |
| 901 | + pr_debug("addr 0x%lx of process mm is destroyed\n", addr); | |
| 902 | + return VM_FAULT_SIGBUS; | |
| 903 | + } | |
| 904 | + | |
| 905 | + mm = svm_bo->eviction_fence->mm; | |
| 906 | + if (mm != vmf->vma->vm_mm) | |
| 907 | + pr_debug("addr 0x%lx is COW mapping in child process\n", addr); | |
| 899 | 908 | |
| 900 | − p = kfd_lookup_process_by_mm(vma->vm_mm); | |
| 909 | + p = kfd_lookup_process_by_mm(mm); | |
| 901 | 910 | if (!p) { |
| 902 | 911 | pr_debug("failed find process at fault address 0x%lx\n", addr); |
| 903 | − return VM_FAULT_SIGBUS; | |
| 912 | + r = VM_FAULT_SIGBUS; | |
| 913 | + goto out_mmput; | |
| 904 | 914 | } |
| 905 | 915 | if (READ_ONCE(p->svms.faulting_task) == current) { |
| 906 | 916 | pr_debug("skipping ram migration\n"); |
| 907 | − kfd_unref_process(p); | |
| 908 | − return 0; | |
| 917 | + r = 0; | |
| 918 | + goto out_unref_process; | |
| 909 | 919 | } |
| 910 | − addr >>= PAGE_SHIFT; | |
| 920 | + | |
| 911 | 921 | pr_debug("CPU page fault svms 0x%p address 0x%lx\n", &p->svms, addr); |
| 922 | + addr >>= PAGE_SHIFT; | |
| 912 | 923 | |
| 913 | 924 | mutex_lock(&p->svms.lock); |
| 914 | 925 | |
| 915 | 926 | prange = svm_range_from_addr(&p->svms, addr, &parent); |
| 916 | 927 | if (!prange) { |
| 917 | − pr_debug("cannot find svm range at 0x%lx\n", addr); | |
| 928 | + pr_debug("failed get range svms 0x%p addr 0x%lx\n", &p->svms, addr); | |
| 918 | 929 | r = -EFAULT; |
| 919 | − goto out; | |
| 930 | + goto out_unlock_svms; | |
| 920 | 931 | } |
| 921 | 932 | |
| 922 | 933 | mutex_lock(&parent->migrate_mutex); |
| @@ -938,10 +949,11 @@ static vm_fault_t svm_migrate_to_ram(struct vm_fault *vmf) · 15 unmodified lines | ||
| 938 | 949 | goto out_unlock_prange; |
| 939 | 950 | } |
| 940 | 951 | |
| 941 | − r = svm_migrate_vram_to_ram(prange, mm, KFD_MIGRATE_TRIGGER_PAGEFAULT_CPU); | |
| 952 | + r = svm_migrate_vram_to_ram(prange, vmf->vma->vm_mm, | |
| 953 | + KFD_MIGRATE_TRIGGER_PAGEFAULT_CPU); | |
| 942 | 954 | if (r) |
| 943 | − pr_debug("failed %d migrate 0x%p [0x%lx 0x%lx] to ram\n", r, | |
| 944 | − prange, prange->start, prange->last); | |
| 955 | + pr_debug("failed %d migrate svms 0x%p range 0x%p [0x%lx 0x%lx]\n", | |
| 956 | + r, prange->svms, prange, prange->start, prange->last); | |
| 945 | 957 | |
| 946 | 958 | /* xnack on, update mapping on GPUs with ACCESS_IN_PLACE */ |
| 947 | 959 | if (p->xnack_enabled && parent == prange) |
| @@ -955,9 +967,12 @@ out_unlock_prange: · 7 unmodified lines | ||
| 955 | 967 | if (prange != parent) |
| 956 | 968 | mutex_unlock(&prange->migrate_mutex); |
| 957 | 969 | mutex_unlock(&parent->migrate_mutex); |
| 958 | −out: | |
| 970 | +out_unlock_svms: | |
| 959 | 971 | mutex_unlock(&p->svms.lock); |
| 972 | +out_unref_process: | |
| 960 | 973 | kfd_unref_process(p); |
| 974 | +out_mmput: | |
| 975 | + mmput(mm); | |
| 961 | 976 | |
| 962 | 977 | pr_debug("CPU fault svms 0x%p address 0x%lx done\n", &p->svms, addr); |
| 963 | 978 | |
| @@ -181,14 +181,6 @@ static int load_mqd(struct mqd_manager *mm, void *mqd, · 180 unmodified lines | ||
| 181 | 181 | return r; |
| 182 | 182 | } |
| 183 | 183 | |
| 184 | −static int hiq_load_mqd_kiq(struct mqd_manager *mm, void *mqd, | |
| 185 | − uint32_t pipe_id, uint32_t queue_id, | |
| 186 | − struct queue_properties *p, struct mm_struct *mms) | |
| 187 | −{ | |
| 188 | − return mm->dev->kfd2kgd->hiq_mqd_load(mm->dev->adev, mqd, pipe_id, | |
| 189 | − queue_id, p->doorbell_off); | |
| 190 | −} | |
| 191 | − | |
| 192 | 184 | static void update_mqd(struct mqd_manager *mm, void *mqd, |
| 193 | 185 | struct queue_properties *q, |
| 194 | 186 | struct mqd_update_info *minfo) |
| @@ -260,31 +252,6 @@ static uint32_t read_doorbell_id(void *mqd) · 65 unmodified lines | ||
| 260 | 252 | return m->queue_doorbell_id0; |
| 261 | 253 | } |
| 262 | 254 | |
| 263 | −static int destroy_mqd(struct mqd_manager *mm, void *mqd, | |
| 264 | − enum kfd_preempt_type type, | |
| 265 | − unsigned int timeout, uint32_t pipe_id, | |
| 266 | − uint32_t queue_id) | |
| 267 | −{ | |
| 268 | − return mm->dev->kfd2kgd->hqd_destroy | |
| 269 | − (mm->dev->adev, mqd, type, timeout, | |
| 270 | − pipe_id, queue_id); | |
| 271 | −} | |
| 272 | − | |
| 273 | −static void free_mqd(struct mqd_manager *mm, void *mqd, | |
| 274 | − struct kfd_mem_obj *mqd_mem_obj) | |
| 275 | −{ | |
| 276 | − kfd_gtt_sa_free(mm->dev, mqd_mem_obj); | |
| 277 | −} | |
| 278 | − | |
| 279 | −static bool is_occupied(struct mqd_manager *mm, void *mqd, | |
| 280 | − uint64_t queue_address, uint32_t pipe_id, | |
| 281 | − uint32_t queue_id) | |
| 282 | −{ | |
| 283 | − return mm->dev->kfd2kgd->hqd_is_occupied( | |
| 284 | − mm->dev->adev, queue_address, | |
| 285 | − pipe_id, queue_id); | |
| 286 | −} | |
| 287 | − | |
| 288 | 255 | static int get_wave_state(struct mqd_manager *mm, void *mqd, |
| 289 | 256 | void __user *ctl_stack, |
| 290 | 257 | u32 *ctl_stack_used_size, |
| @@ -353,15 +320,6 @@ static void init_mqd_sdma(struct mqd_manager *mm, void **mqd, · 62 unmodified lines | ||
| 353 | 320 | mm->update_mqd(mm, m, q, NULL); |
| 354 | 321 | } |
| 355 | 322 | |
| 356 | −static int load_mqd_sdma(struct mqd_manager *mm, void *mqd, | |
| 357 | − uint32_t pipe_id, uint32_t queue_id, | |
| 358 | − struct queue_properties *p, struct mm_struct *mms) | |
| 359 | −{ | |
| 360 | − return mm->dev->kfd2kgd->hqd_sdma_load(mm->dev->adev, mqd, | |
| 361 | − (uint32_t __user *)p->write_ptr, | |
| 362 | − mms); | |
| 363 | −} | |
| 364 | − | |
| 365 | 323 | #define SDMA_RLC_DUMMY_DEFAULT 0xf |
| 366 | 324 | |
| 367 | 325 | static void update_mqd_sdma(struct mqd_manager *mm, void *mqd, |
| @@ -393,25 +351,6 @@ static void update_mqd_sdma(struct mqd_manager *mm, void *mqd, · 25 unmodified lines | ||
| 393 | 351 | q->is_active = QUEUE_IS_ACTIVE(*q); |
| 394 | 352 | } |
| 395 | 353 | |
| 396 | −/* | |
| 397 | − * * preempt type here is ignored because there is only one way | |
| 398 | − * * to preempt sdma queue | |
| 399 | − */ | |
| 400 | −static int destroy_mqd_sdma(struct mqd_manager *mm, void *mqd, | |
| 401 | − enum kfd_preempt_type type, | |
| 402 | − unsigned int timeout, uint32_t pipe_id, | |
| 403 | − uint32_t queue_id) | |
| 404 | −{ | |
| 405 | − return mm->dev->kfd2kgd->hqd_sdma_destroy(mm->dev->adev, mqd, timeout); | |
| 406 | −} | |
| 407 | − | |
| 408 | −static bool is_occupied_sdma(struct mqd_manager *mm, void *mqd, | |
| 409 | − uint64_t queue_address, uint32_t pipe_id, | |
| 410 | − uint32_t queue_id) | |
| 411 | −{ | |
| 412 | − return mm->dev->kfd2kgd->hqd_sdma_is_occupied(mm->dev->adev, mqd); | |
| 413 | −} | |
| 414 | − | |
| 415 | 354 | #if defined(CONFIG_DEBUG_FS) |
| 416 | 355 | |
| 417 | 356 | static int debugfs_show_mqd(struct seq_file *m, void *data) |
| @@ -449,11 +388,11 @@ struct mqd_manager *mqd_manager_init_v11(enum KFD_MQD_TYPE type, · 31 unmodified lines | ||
| 449 | 388 | pr_debug("%s@%i\n", __func__, __LINE__); |
| 450 | 389 | mqd->allocate_mqd = allocate_mqd; |
| 451 | 390 | mqd->init_mqd = init_mqd; |
| 452 | − mqd->free_mqd = free_mqd; | |
| 391 | + mqd->free_mqd = kfd_free_mqd_cp; | |
| 453 | 392 | mqd->load_mqd = load_mqd; |
| 454 | 393 | mqd->update_mqd = update_mqd; |
| 455 | − mqd->destroy_mqd = destroy_mqd; | |
| 456 | − mqd->is_occupied = is_occupied; | |
| 394 | + mqd->destroy_mqd = kfd_destroy_mqd_cp; | |
| 395 | + mqd->is_occupied = kfd_is_occupied_cp; | |
| 457 | 396 | mqd->mqd_size = sizeof(struct v11_compute_mqd); |
| 458 | 397 | mqd->get_wave_state = get_wave_state; |
| 459 | 398 | #if defined(CONFIG_DEBUG_FS) |
| @@ -466,10 +405,10 @@ struct mqd_manager *mqd_manager_init_v11(enum KFD_MQD_TYPE type, · 6 unmodified lines | ||
| 466 | 405 | mqd->allocate_mqd = allocate_hiq_mqd; |
| 467 | 406 | mqd->init_mqd = init_mqd_hiq; |
| 468 | 407 | mqd->free_mqd = free_mqd_hiq_sdma; |
| 469 | − mqd->load_mqd = hiq_load_mqd_kiq; | |
| 408 | + mqd->load_mqd = kfd_hiq_load_mqd_kiq; | |
| 470 | 409 | mqd->update_mqd = update_mqd; |
| 471 | − mqd->destroy_mqd = destroy_mqd; | |
| 472 | − mqd->is_occupied = is_occupied; | |
| 410 | + mqd->destroy_mqd = kfd_destroy_mqd_cp; | |
| 411 | + mqd->is_occupied = kfd_is_occupied_cp; | |
| 473 | 412 | mqd->mqd_size = sizeof(struct v11_compute_mqd); |
| 474 | 413 | #if defined(CONFIG_DEBUG_FS) |
| 475 | 414 | mqd->debugfs_show_mqd = debugfs_show_mqd; |
| @@ -480,11 +419,11 @@ struct mqd_manager *mqd_manager_init_v11(enum KFD_MQD_TYPE type, · 4 unmodified lines | ||
| 480 | 419 | case KFD_MQD_TYPE_DIQ: |
| 481 | 420 | mqd->allocate_mqd = allocate_mqd; |
| 482 | 421 | mqd->init_mqd = init_mqd_hiq; |
| 483 | − mqd->free_mqd = free_mqd; | |
| 422 | + mqd->free_mqd = kfd_free_mqd_cp; | |
| 484 | 423 | mqd->load_mqd = load_mqd; |
| 485 | 424 | mqd->update_mqd = update_mqd; |
| 486 | − mqd->destroy_mqd = destroy_mqd; | |
| 487 | − mqd->is_occupied = is_occupied; | |
| 425 | + mqd->destroy_mqd = kfd_destroy_mqd_cp; | |
| 426 | + mqd->is_occupied = kfd_is_occupied_cp; | |
| 488 | 427 | mqd->mqd_size = sizeof(struct v11_compute_mqd); |
| 489 | 428 | #if defined(CONFIG_DEBUG_FS) |
| 490 | 429 | mqd->debugfs_show_mqd = debugfs_show_mqd; |
| @@ -495,10 +434,10 @@ struct mqd_manager *mqd_manager_init_v11(enum KFD_MQD_TYPE type, · 4 unmodified lines | ||
| 495 | 434 | mqd->allocate_mqd = allocate_sdma_mqd; |
| 496 | 435 | mqd->init_mqd = init_mqd_sdma; |
| 497 | 436 | mqd->free_mqd = free_mqd_hiq_sdma; |
| 498 | − mqd->load_mqd = load_mqd_sdma; | |
| 437 | + mqd->load_mqd = kfd_load_mqd_sdma; | |
| 499 | 438 | mqd->update_mqd = update_mqd_sdma; |
| 500 | − mqd->destroy_mqd = destroy_mqd_sdma; | |
| 501 | − mqd->is_occupied = is_occupied_sdma; | |
| 439 | + mqd->destroy_mqd = kfd_destroy_mqd_sdma; | |
| 440 | + mqd->is_occupied = kfd_is_occupied_sdma; | |
| 502 | 441 | mqd->mqd_size = sizeof(struct v11_sdma_mqd); |
| 503 | 442 | #if defined(CONFIG_DEBUG_FS) |
| 504 | 443 | mqd->debugfs_show_mqd = debugfs_show_mqd_sdma; |
| @@ -1499,11 +1499,6 @@ struct kfd_process_device *kfd_create_process_device_data(struct kfd_dev *dev, · 1498 unmodified lines | ||
| 1499 | 1499 | if (!pdd) |
| 1500 | 1500 | return NULL; |
| 1501 | 1501 | |
| 1502 | − if (kfd_alloc_process_doorbells(dev, &pdd->doorbell_index) < 0) { | |
| 1503 | − pr_err("Failed to alloc doorbell for pdd\n"); | |
| 1504 | − goto err_free_pdd; | |
| 1505 | − } | |
| 1506 | − | |
| 1507 | 1502 | if (init_doorbell_bitmap(&pdd->qpd, dev)) { |
| 1508 | 1503 | pr_err("Failed to init doorbell for process\n"); |
| 1509 | 1504 | goto err_free_pdd; |
| @@ -857,6 +857,13 @@ int kfd_criu_restore_queue(struct kfd_process *p, · 856 unmodified lines | ||
| 857 | 857 | ret = -EINVAL; |
| 858 | 858 | goto exit; |
| 859 | 859 | } |
| 860 | + | |
| 861 | + if (!pdd->doorbell_index && | |
| 862 | + kfd_alloc_process_doorbells(pdd->dev, &pdd->doorbell_index) < 0) { | |
| 863 | + ret = -ENOMEM; | |
| 864 | + goto exit; | |
| 865 | + } | |
| 866 | + | |
| 860 | 867 | /* data stored in this order: mqd, ctl_stack */ |
| 861 | 868 | mqd = q_extra_data; |
| 862 | 869 | ctl_stack = mqd + q_data->mqd_size; |
| @@ -278,7 +278,7 @@ static void svm_range_free(struct svm_range *prange, bool update_mem_usage) · 277 unmodified lines | ||
| 278 | 278 | svm_range_free_dma_mappings(prange); |
| 279 | 279 | |
| 280 | 280 | if (update_mem_usage && !p->xnack_enabled) { |
| 281 | − pr_debug("unreserve mem limit: %lld\n", size); | |
| 281 | + pr_debug("unreserve prange 0x%p size: 0x%llx\n", prange, size); | |
| 282 | 282 | amdgpu_amdkfd_unreserve_mem_limit(NULL, size, |
| 283 | 283 | KFD_IOC_ALLOC_MEM_FLAGS_USERPTR); |
| 284 | 284 | } |
| @@ -2956,6 +2956,64 @@ out: · 2671 unmodified lines | ||
| 2956 | 2956 | return r; |
| 2957 | 2957 | } |
| 2958 | 2958 | |
| 2959 | +int | |
| 2960 | +svm_range_switch_xnack_reserve_mem(struct kfd_process *p, bool xnack_enabled) | |
| 2961 | +{ | |
| 2962 | + struct svm_range *prange, *pchild; | |
| 2963 | + uint64_t reserved_size = 0; | |
| 2964 | + uint64_t size; | |
| 2965 | + int r = 0; | |
| 2966 | + | |
| 2967 | + pr_debug("switching xnack from %d to %d\n", p->xnack_enabled, xnack_enabled); | |
| 2968 | + | |
| 2969 | + mutex_lock(&p->svms.lock); | |
| 2970 | + | |
| 2971 | + list_for_each_entry(prange, &p->svms.list, list) { | |
| 2972 | + svm_range_lock(prange); | |
| 2973 | + list_for_each_entry(pchild, &prange->child_list, child_list) { | |
| 2974 | + size = (pchild->last - pchild->start + 1) << PAGE_SHIFT; | |
| 2975 | + if (xnack_enabled) { | |
| 2976 | + amdgpu_amdkfd_unreserve_mem_limit(NULL, size, | |
| 2977 | + KFD_IOC_ALLOC_MEM_FLAGS_USERPTR); | |
| 2978 | + } else { | |
| 2979 | + r = amdgpu_amdkfd_reserve_mem_limit(NULL, size, | |
| 2980 | + KFD_IOC_ALLOC_MEM_FLAGS_USERPTR); | |
| 2981 | + if (r) | |
| 2982 | + goto out_unlock; | |
| 2983 | + reserved_size += size; | |
| 2984 | + } | |
| 2985 | + } | |
| 2986 | + | |
| 2987 | + size = (prange->last - prange->start + 1) << PAGE_SHIFT; | |
| 2988 | + if (xnack_enabled) { | |
| 2989 | + amdgpu_amdkfd_unreserve_mem_limit(NULL, size, | |
| 2990 | + KFD_IOC_ALLOC_MEM_FLAGS_USERPTR); | |
| 2991 | + } else { | |
| 2992 | + r = amdgpu_amdkfd_reserve_mem_limit(NULL, size, | |
| 2993 | + KFD_IOC_ALLOC_MEM_FLAGS_USERPTR); | |
| 2994 | + if (r) | |
| 2995 | + goto out_unlock; | |
| 2996 | + reserved_size += size; | |
| 2997 | + } | |
| 2998 | +out_unlock: | |
| 2999 | + svm_range_unlock(prange); | |
| 3000 | + if (r) | |
| 3001 | + break; | |
| 3002 | + } | |
| 3003 | + | |
| 3004 | + if (r) | |
| 3005 | + amdgpu_amdkfd_unreserve_mem_limit(NULL, reserved_size, | |
| 3006 | + KFD_IOC_ALLOC_MEM_FLAGS_USERPTR); | |
| 3007 | + else | |
| 3008 | + /* Change xnack mode must be inside svms lock, to avoid race with | |
| 3009 | + * svm_range_deferred_list_work unreserve memory in parallel. | |
| 3010 | + */ | |
| 3011 | + p->xnack_enabled = xnack_enabled; | |
| 3012 | + | |
| 3013 | + mutex_unlock(&p->svms.lock); | |
| 3014 | + return r; | |
| 3015 | +} | |
| 3016 | + | |
| 2959 | 3017 | void svm_range_list_fini(struct kfd_process *p) |
| 2960 | 3018 | { |
| 2961 | 3019 | struct svm_range *prange; |
| @@ -3181,28 +3239,6 @@ out: · 219 unmodified lines | ||
| 3181 | 3239 | return best_loc; |
| 3182 | 3240 | } |
| 3183 | 3241 | |
| 3184 | −/* FIXME: This is a workaround for page locking bug when some pages are | |
| 3185 | − * invalid during migration to VRAM | |
| 3186 | − */ | |
| 3187 | −void svm_range_prefault(struct svm_range *prange, struct mm_struct *mm, | |
| 3188 | − void *owner) | |
| 3189 | −{ | |
| 3190 | − struct hmm_range *hmm_range; | |
| 3191 | − int r; | |
| 3192 | − | |
| 3193 | − if (prange->validated_once) | |
| 3194 | − return; | |
| 3195 | − | |
| 3196 | − r = amdgpu_hmm_range_get_pages(&prange->notifier, mm, NULL, | |
| 3197 | − prange->start << PAGE_SHIFT, | |
| 3198 | − prange->npages, &hmm_range, | |
| 3199 | − false, true, owner); | |
| 3200 | − if (!r) { | |
| 3201 | − amdgpu_hmm_range_get_pages_done(hmm_range); | |
| 3202 | − prange->validated_once = true; | |
| 3203 | − } | |
| 3204 | −} | |
| 3205 | − | |
| 3206 | 3242 | /* svm_range_trigger_migration - start page migration if prefetch loc changed |
| 3207 | 3243 | * @mm: current process mm_struct |
| 3208 | 3244 | * @prange: svm range structure |
| @@ -181,8 +181,6 @@ void schedule_deferred_list_work(struct svm_range_list *svms); · 180 unmodified lines | ||
| 181 | 181 | void svm_range_dma_unmap(struct device *dev, dma_addr_t *dma_addr, |
| 182 | 182 | unsigned long offset, unsigned long npages); |
| 183 | 183 | void svm_range_free_dma_mappings(struct svm_range *prange); |
| 184 | −void svm_range_prefault(struct svm_range *prange, struct mm_struct *mm, | |
| 185 | − void *owner); | |
| 186 | 184 | int svm_range_get_info(struct kfd_process *p, uint32_t *num_svm_ranges, |
| 187 | 185 | uint64_t *svm_priv_data_size); |
| 188 | 186 | int kfd_criu_checkpoint_svm(struct kfd_process *p, |
| @@ -205,6 +203,7 @@ void svm_range_list_lock_and_flush_work(struct svm_range_list *svms, struct mm_s · 16 unmodified lines | ||
| 205 | 203 | void svm_range_bo_unref_async(struct svm_range_bo *svm_bo); |
| 206 | 204 | |
| 207 | 205 | void svm_range_set_max_pages(struct amdgpu_device *adev); |
| 206 | +int svm_range_switch_xnack_reserve_mem(struct kfd_process *p, bool xnack_enabled); | |
| 208 | 207 | |
| 209 | 208 | #else |
| 210 | 209 | |
| @@ -28,7 +28,6 @@ config DRM_AMD_DC_SI · 27 unmodified lines | ||
| 28 | 28 | bool "AMD DC support for Southern Islands ASICs" |
| 29 | 29 | depends on DRM_AMDGPU_SI |
| 30 | 30 | depends on DRM_AMD_DC |
| 31 | − default n | |
| 32 | 31 | help |
| 33 | 32 | Choose this option to enable new AMD DC support for SI asics |
| 34 | 33 | by default. This includes Tahiti, Pitcairn, Cape Verde, Oland. |
| @@ -43,7 +42,6 @@ config DEBUG_KERNEL_DC · 8 unmodified lines | ||
| 43 | 42 | |
| 44 | 43 | config DRM_AMD_SECURE_DISPLAY |
| 45 | 44 | bool "Enable secure display support" |
| 46 | − default n | |
| 47 | 45 | depends on DEBUG_FS |
| 48 | 46 | depends on DRM_AMD_DC_DCN |
| 49 | 47 | help |
| @@ -88,6 +88,7 @@ · 87 unmodified lines | ||
| 88 | 88 | #include <drm/drm_vblank.h> |
| 89 | 89 | #include <drm/drm_audio_component.h> |
| 90 | 90 | #include <drm/drm_gem_atomic_helper.h> |
| 91 | +#include <drm/drm_plane_helper.h> | |
| 91 | 92 | |
| 92 | 93 | #include <acpi/video.h> |
| 93 | 94 | |
| @@ -99,8 +100,6 @@ · 5 unmodified lines | ||
| 99 | 100 | #include "soc15_common.h" |
| 100 | 101 | #include "vega10_ip_offset.h" |
| 101 | 102 | |
| 102 | −#include "soc15_common.h" | |
| 103 | − | |
| 104 | 103 | #include "gc/gc_11_0_0_offset.h" |
| 105 | 104 | #include "gc/gc_11_0_0_sh_mask.h" |
| 106 | 105 | |
| @@ -1297,13 +1296,21 @@ static struct hpd_rx_irq_offload_work_queue *hpd_rx_irq_create_workqueue(struct · 1190 unmodified lines | ||
| 1297 | 1296 | |
| 1298 | 1297 | if (hpd_rx_offload_wq[i].wq == NULL) { |
| 1299 | 1298 | DRM_ERROR("create amdgpu_dm_hpd_rx_offload_wq fail!"); |
| 1300 | − return NULL; | |
| 1299 | + goto out_err; | |
| 1301 | 1300 | } |
| 1302 | 1301 | |
| 1303 | 1302 | spin_lock_init(&hpd_rx_offload_wq[i].offload_lock); |
| 1304 | 1303 | } |
| 1305 | 1304 | |
| 1306 | 1305 | return hpd_rx_offload_wq; |
| 1306 | + | |
| 1307 | +out_err: | |
| 1308 | + for (i = 0; i < max_caps; i++) { | |
| 1309 | + if (hpd_rx_offload_wq[i].wq) | |
| 1310 | + destroy_workqueue(hpd_rx_offload_wq[i].wq); | |
| 1311 | + } | |
| 1312 | + kfree(hpd_rx_offload_wq); | |
| 1313 | + return NULL; | |
| 1307 | 1314 | } |
| 1308 | 1315 | |
| 1309 | 1316 | struct amdgpu_stutter_quirk { |
| @@ -1531,7 +1538,6 @@ static int amdgpu_dm_init(struct amdgpu_device *adev) · 221 unmodified lines | ||
| 1531 | 1538 | |
| 1532 | 1539 | if (amdgpu_dc_debug_mask & DC_DISABLE_DSC) { |
| 1533 | 1540 | adev->dm.dc->debug.disable_dsc = true; |
| 1534 | − adev->dm.dc->debug.disable_dsc_edp = true; | |
| 1535 | 1541 | } |
| 1536 | 1542 | |
| 1537 | 1543 | if (amdgpu_dc_debug_mask & DC_DISABLE_CLOCK_GATING) |
| @@ -2809,20 +2815,18 @@ static const struct drm_mode_config_funcs amdgpu_dm_mode_funcs = { · 1271 unmodified lines | ||
| 2809 | 2815 | }; |
| 2810 | 2816 | |
| 2811 | 2817 | static struct drm_mode_config_helper_funcs amdgpu_dm_mode_config_helperfuncs = { |
| 2812 | − .atomic_commit_tail = amdgpu_dm_atomic_commit_tail | |
| 2818 | + .atomic_commit_tail = amdgpu_dm_atomic_commit_tail, | |
| 2819 | + .atomic_commit_setup = drm_dp_mst_atomic_setup_commit, | |
| 2813 | 2820 | }; |
| 2814 | 2821 | |
| 2815 | 2822 | static void update_connector_ext_caps(struct amdgpu_dm_connector *aconnector) |
| 2816 | 2823 | { |
| 2817 | − u32 max_avg, min_cll, max, min, q, r; | |
| 2818 | 2824 | struct amdgpu_dm_backlight_caps *caps; |
| 2819 | 2825 | struct amdgpu_display_manager *dm; |
| 2820 | 2826 | struct drm_connector *conn_base; |
| 2821 | 2827 | struct amdgpu_device *adev; |
| 2822 | 2828 | struct dc_link *link = NULL; |
| 2823 | − static const u8 pre_computed_values[] = { | |
| 2824 | − 50, 51, 52, 53, 55, 56, 57, 58, 59, 61, 62, 63, 65, 66, 68, 69, | |
| 2825 | − 71, 72, 74, 75, 77, 79, 81, 82, 84, 86, 88, 90, 92, 94, 96, 98}; | |
| 2829 | + struct drm_luminance_range_info *luminance_range; | |
| 2826 | 2830 | int i; |
| 2827 | 2831 | |
| 2828 | 2832 | if (!aconnector || !aconnector->dc_link) |
| @@ -2844,8 +2848,6 @@ static void update_connector_ext_caps(struct amdgpu_dm_connector *aconnector) · 15 unmodified lines | ||
| 2844 | 2848 | caps = &dm->backlight_caps[i]; |
| 2845 | 2849 | caps->ext_caps = &aconnector->dc_link->dpcd_sink_ext_caps; |
| 2846 | 2850 | caps->aux_support = false; |
| 2847 | − max_avg = conn_base->hdr_sink_metadata.hdmi_type1.max_fall; | |
| 2848 | − min_cll = conn_base->hdr_sink_metadata.hdmi_type1.min_cll; | |
| 2849 | 2851 | |
| 2850 | 2852 | if (caps->ext_caps->bits.oled == 1 /*|| |
| 2851 | 2853 | caps->ext_caps->bits.sdr_aux_backlight_control == 1 || |
| @@ -2857,31 +2859,9 @@ static void update_connector_ext_caps(struct amdgpu_dm_connector *aconnector) · 5 unmodified lines | ||
| 2857 | 2859 | else if (amdgpu_backlight == 1) |
| 2858 | 2860 | caps->aux_support = true; |
| 2859 | 2861 | |
| 2860 | − /* From the specification (CTA-861-G), for calculating the maximum | |
| 2861 | − * luminance we need to use: | |
| 2862 | − * Luminance = 50*2**(CV/32) | |
| 2863 | − * Where CV is a one-byte value. | |
| 2864 | − * For calculating this expression we may need float point precision; | |
| 2865 | − * to avoid this complexity level, we take advantage that CV is divided | |
| 2866 | − * by a constant. From the Euclids division algorithm, we know that CV | |
| 2867 | − * can be written as: CV = 32*q + r. Next, we replace CV in the | |
| 2868 | − * Luminance expression and get 50*(2**q)*(2**(r/32)), hence we just | |
| 2869 | − * need to pre-compute the value of r/32. For pre-computing the values | |
| 2870 | − * We just used the following Ruby line: | |
| 2871 | − * (0...32).each {|cv| puts (50*2**(cv/32.0)).round} | |
| 2872 | − * The results of the above expressions can be verified at | |
| 2873 | − * pre_computed_values. | |
| 2874 | − */ | |
| 2875 | − q = max_avg >> 5; | |
| 2876 | − r = max_avg % 32; | |
| 2877 | − max = (1 << q) * pre_computed_values[r]; | |
| 2878 | − | |
| 2879 | − // min luminance: maxLum * (CV/255)^2 / 100 | |
| 2880 | − q = DIV_ROUND_CLOSEST(min_cll, 255); | |
| 2881 | − min = max * DIV_ROUND_CLOSEST((q * q), 100); | |
| 2882 | − | |
| 2883 | − caps->aux_max_input_signal = max; | |
| 2884 | − caps->aux_min_input_signal = min; | |
| 2862 | + luminance_range = &conn_base->display_info.luminance_range; | |
| 2863 | + caps->aux_min_input_signal = luminance_range->min_luminance; | |
| 2864 | + caps->aux_max_input_signal = luminance_range->max_luminance; | |
| 2885 | 2865 | } |
| 2886 | 2866 | |
| 2887 | 2867 | void amdgpu_dm_update_connector_after_detect( |
| @@ -5638,7 +5618,8 @@ static void apply_dsc_policy_for_stream(struct amdgpu_dm_connector *aconnector, · 2750 unmodified lines | ||
| 5638 | 5618 | dc_dsc_policy_set_enable_dsc_when_not_needed( |
| 5639 | 5619 | aconnector->dsc_settings.dsc_force_enable == DSC_CLK_FORCE_ENABLE); |
| 5640 | 5620 | |
| 5641 | − if (aconnector->dc_link && sink->sink_signal == SIGNAL_TYPE_EDP && !dc->debug.disable_dsc_edp && | |
| 5621 | + if (aconnector->dc_link && sink->sink_signal == SIGNAL_TYPE_EDP && | |
| 5622 | + !aconnector->dc_link->panel_config.dsc.disable_dsc_edp && | |
| 5642 | 5623 | dc->caps.edp_dsc_support && aconnector->dsc_settings.dsc_force_enable != DSC_CLK_FORCE_DISABLE) { |
| 5643 | 5624 | |
| 5644 | 5625 | apply_dsc_policy_for_edp(aconnector, sink, stream, dsc_caps, max_dsc_target_bpp_limit_override); |
| @@ -6330,10 +6311,17 @@ amdgpu_dm_connector_atomic_check(struct drm_connector *conn, · 685 unmodified lines | ||
| 6330 | 6311 | drm_atomic_get_old_connector_state(state, conn); |
| 6331 | 6312 | struct drm_crtc *crtc = new_con_state->crtc; |
| 6332 | 6313 | struct drm_crtc_state *new_crtc_state; |
| 6314 | + struct amdgpu_dm_connector *aconn = to_amdgpu_dm_connector(conn); | |
| 6333 | 6315 | int ret; |
| 6334 | 6316 | |
| 6335 | 6317 | trace_amdgpu_dm_connector_atomic_check(new_con_state); |
| 6336 | 6318 | |
| 6319 | + if (conn->connector_type == DRM_MODE_CONNECTOR_DisplayPort) { | |
| 6320 | + ret = drm_dp_mst_root_conn_atomic_check(new_con_state, &aconn->mst_mgr); | |
| 6321 | + if (ret < 0) | |
| 6322 | + return ret; | |
| 6323 | + } | |
| 6324 | + | |
| 6337 | 6325 | if (!crtc) |
| 6338 | 6326 | return 0; |
| 6339 | 6327 | |
| @@ -6417,6 +6405,7 @@ static int dm_encoder_helper_atomic_check(struct drm_encoder *encoder, · 77 unmodified lines | ||
| 6417 | 6405 | const struct drm_display_mode *adjusted_mode = &crtc_state->adjusted_mode; |
| 6418 | 6406 | struct drm_dp_mst_topology_mgr *mst_mgr; |
| 6419 | 6407 | struct drm_dp_mst_port *mst_port; |
| 6408 | + struct drm_dp_mst_topology_state *mst_state; | |
| 6420 | 6409 | enum dc_color_depth color_depth; |
| 6421 | 6410 | int clock, bpp = 0; |
| 6422 | 6411 | bool is_y420 = false; |
| @@ -6430,6 +6419,13 @@ static int dm_encoder_helper_atomic_check(struct drm_encoder *encoder, · 7 unmodified lines | ||
| 6430 | 6419 | if (!crtc_state->connectors_changed && !crtc_state->mode_changed) |
| 6431 | 6420 | return 0; |
| 6432 | 6421 | |
| 6422 | + mst_state = drm_atomic_get_mst_topology_state(state, mst_mgr); | |
| 6423 | + if (IS_ERR(mst_state)) | |
| 6424 | + return PTR_ERR(mst_state); | |
| 6425 | + | |
| 6426 | + if (!mst_state->pbn_div) | |
| 6427 | + mst_state->pbn_div = dm_mst_get_pbn_divider(aconnector->mst_port->dc_link); | |
| 6428 | + | |
| 6433 | 6429 | if (!state->duplicated) { |
| 6434 | 6430 | int max_bpc = conn_state->max_requested_bpc; |
| 6435 | 6431 | is_y420 = drm_mode_is_420_also(&connector->display_info, adjusted_mode) && |
| @@ -6441,11 +6437,10 @@ static int dm_encoder_helper_atomic_check(struct drm_encoder *encoder, · 5 unmodified lines | ||
| 6441 | 6437 | clock = adjusted_mode->clock; |
| 6442 | 6438 | dm_new_connector_state->pbn = drm_dp_calc_pbn_mode(clock, bpp, false); |
| 6443 | 6439 | } |
| 6444 | − dm_new_connector_state->vcpi_slots = drm_dp_atomic_find_vcpi_slots(state, | |
| 6445 | − mst_mgr, | |
| 6446 | − mst_port, | |
| 6447 | − dm_new_connector_state->pbn, | |
| 6448 | − dm_mst_get_pbn_divider(aconnector->dc_link)); | |
| 6440 | + | |
| 6441 | + dm_new_connector_state->vcpi_slots = | |
| 6442 | + drm_dp_atomic_find_time_slots(state, mst_mgr, mst_port, | |
| 6443 | + dm_new_connector_state->pbn); | |
| 6449 | 6444 | if (dm_new_connector_state->vcpi_slots < 0) { |
| 6450 | 6445 | DRM_DEBUG_ATOMIC("failed finding vcpi slots: %d\n", (int)dm_new_connector_state->vcpi_slots); |
| 6451 | 6446 | return dm_new_connector_state->vcpi_slots; |
| @@ -6515,18 +6510,12 @@ static int dm_update_mst_vcpi_slots_for_dsc(struct drm_atomic_state *state, · 63 unmodified lines | ||
| 6515 | 6510 | dm_conn_state->pbn = pbn; |
| 6516 | 6511 | dm_conn_state->vcpi_slots = slot_num; |
| 6517 | 6512 | |
| 6518 | − drm_dp_mst_atomic_enable_dsc(state, | |
| 6519 | − aconnector->port, | |
| 6520 | − dm_conn_state->pbn, | |
| 6521 | − 0, | |
| 6513 | + drm_dp_mst_atomic_enable_dsc(state, aconnector->port, dm_conn_state->pbn, | |
| 6522 | 6514 | false); |
| 6523 | 6515 | continue; |
| 6524 | 6516 | } |
| 6525 | 6517 | |
| 6526 | − vcpi = drm_dp_mst_atomic_enable_dsc(state, | |
| 6527 | − aconnector->port, | |
| 6528 | − pbn, pbn_div, | |
| 6529 | − true); | |
| 6518 | + vcpi = drm_dp_mst_atomic_enable_dsc(state, aconnector->port, pbn, true); | |
| 6530 | 6519 | if (vcpi < 0) |
| 6531 | 6520 | return vcpi; |
| 6532 | 6521 | |
| @@ -7396,11 +7385,6 @@ static void update_freesync_state_on_stream( · 863 unmodified lines | ||
| 7396 | 7385 | &vrr_infopacket, |
| 7397 | 7386 | pack_sdp_v1_3); |
| 7398 | 7387 | |
| 7399 | − new_crtc_state->freesync_timing_changed |= | |
| 7400 | − (memcmp(&acrtc->dm_irq_params.vrr_params.adjust, | |
| 7401 | − &vrr_params.adjust, | |
| 7402 | − sizeof(vrr_params.adjust)) != 0); | |
| 7403 | − | |
| 7404 | 7388 | new_crtc_state->freesync_vrr_info_changed |= |
| 7405 | 7389 | (memcmp(&new_crtc_state->vrr_infopacket, |
| 7406 | 7390 | &vrr_infopacket, |
| @@ -7409,7 +7393,6 @@ static void update_freesync_state_on_stream( · 2 unmodified lines | ||
| 7409 | 7393 | acrtc->dm_irq_params.vrr_params = vrr_params; |
| 7410 | 7394 | new_crtc_state->vrr_infopacket = vrr_infopacket; |
| 7411 | 7395 | |
| 7412 | − new_stream->adjust = acrtc->dm_irq_params.vrr_params.adjust; | |
| 7413 | 7396 | new_stream->vrr_infopacket = vrr_infopacket; |
| 7414 | 7397 | |
| 7415 | 7398 | if (new_crtc_state->freesync_vrr_info_changed) |
| @@ -7472,10 +7455,6 @@ static void update_stream_irq_parameters( · 56 unmodified lines | ||
| 7472 | 7455 | new_stream, |
| 7473 | 7456 | &config, &vrr_params); |
| 7474 | 7457 | |
| 7475 | − new_crtc_state->freesync_timing_changed |= | |
| 7476 | − (memcmp(&acrtc->dm_irq_params.vrr_params.adjust, | |
| 7477 | − &vrr_params.adjust, sizeof(vrr_params.adjust)) != 0); | |
| 7478 | − | |
| 7479 | 7458 | new_crtc_state->freesync_config = config; |
| 7480 | 7459 | /* Copy state for access from DM IRQ handler */ |
| 7481 | 7460 | acrtc->dm_irq_params.freesync_config = config; |
| @@ -8001,6 +7980,7 @@ static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state) · 519 unmodified lines | ||
| 8001 | 7980 | DRM_ERROR("Waiting for fences timed out!"); |
| 8002 | 7981 | |
| 8003 | 7982 | drm_atomic_helper_update_legacy_modeset_state(dev, state); |
| 7983 | + drm_dp_mst_atomic_wait_for_dependencies(state); | |
| 8004 | 7984 | |
| 8005 | 7985 | dm_state = dm_atomic_get_new_state(state); |
| 8006 | 7986 | if (dm_state && dm_state->context) { |
| @@ -8399,7 +8379,6 @@ static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state) · 392 unmodified lines | ||
| 8399 | 8379 | dc_release_state(dc_state_temp); |
| 8400 | 8380 | } |
| 8401 | 8381 | |
| 8402 | − | |
| 8403 | 8382 | static int dm_force_atomic_commit(struct drm_connector *connector) |
| 8404 | 8383 | { |
| 8405 | 8384 | int ret = 0; |
| @@ -9330,6 +9309,7 @@ static int add_affected_mst_dsc_crtcs(struct drm_atomic_state *state, struct drm · 924 unmodified lines | ||
| 9330 | 9309 | |
| 9331 | 9310 | /** |
| 9332 | 9311 | * amdgpu_dm_atomic_check() - Atomic check implementation for AMDgpu DM. |
| 9312 | + * | |
| 9333 | 9313 | * @dev: The DRM device |
| 9334 | 9314 | * @state: The atomic state to commit |
| 9335 | 9315 | * |
| @@ -9370,8 +9350,6 @@ static int amdgpu_dm_atomic_check(struct drm_device *dev, · 34 unmodified lines | ||
| 9370 | 9350 | struct dm_crtc_state *dm_old_crtc_state, *dm_new_crtc_state; |
| 9371 | 9351 | #if defined(CONFIG_DRM_AMD_DC_DCN) |
| 9372 | 9352 | struct dsc_mst_fairness_vars vars[MAX_PIPES]; |
| 9373 | − struct drm_dp_mst_topology_state *mst_state; | |
| 9374 | − struct drm_dp_mst_topology_mgr *mgr; | |
| 9375 | 9353 | #endif |
| 9376 | 9354 | |
| 9377 | 9355 | trace_amdgpu_dm_atomic_check_begin(state); |
| @@ -9388,9 +9366,6 @@ static int amdgpu_dm_atomic_check(struct drm_device *dev, · 10 unmodified lines | ||
| 9388 | 9366 | struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state); |
| 9389 | 9367 | |
| 9390 | 9368 | /* Skip connectors that are disabled or part of modeset already. */ |
| 9391 | − if (!old_con_state->crtc && !new_con_state->crtc) | |
| 9392 | − continue; | |
| 9393 | − | |
| 9394 | 9369 | if (!new_con_state->crtc) |
| 9395 | 9370 | continue; |
| 9396 | 9371 | |
| @@ -9618,33 +9593,6 @@ static int amdgpu_dm_atomic_check(struct drm_device *dev, · 221 unmodified lines | ||
| 9618 | 9593 | lock_and_validation_needed = true; |
| 9619 | 9594 | } |
| 9620 | 9595 | |
| 9621 | −#if defined(CONFIG_DRM_AMD_DC_DCN) | |
| 9622 | − /* set the slot info for each mst_state based on the link encoding format */ | |
| 9623 | − for_each_new_mst_mgr_in_state(state, mgr, mst_state, i) { | |
| 9624 | − struct amdgpu_dm_connector *aconnector; | |
| 9625 | − struct drm_connector *connector; | |
| 9626 | − struct drm_connector_list_iter iter; | |
| 9627 | − u8 link_coding_cap; | |
| 9628 | − | |
| 9629 | − if (!mgr->mst_state ) | |
| 9630 | − continue; | |
| 9631 | − | |
| 9632 | − drm_connector_list_iter_begin(dev, &iter); | |
| 9633 | − drm_for_each_connector_iter(connector, &iter) { | |
| 9634 | − int id = connector->index; | |
| 9635 | − | |
| 9636 | − if (id == mst_state->mgr->conn_base_id) { | |
| 9637 | − aconnector = to_amdgpu_dm_connector(connector); | |
| 9638 | − link_coding_cap = dc_link_dp_mst_decide_link_encoding_format(aconnector->dc_link); | |
| 9639 | − drm_dp_mst_update_slots(mst_state, link_coding_cap); | |
| 9640 | − | |
| 9641 | − break; | |
| 9642 | − } | |
| 9643 | − } | |
| 9644 | − drm_connector_list_iter_end(&iter); | |
| 9645 | − | |
| 9646 | − } | |
| 9647 | −#endif | |
| 9648 | 9596 | /** |
| 9649 | 9597 | * Streams and planes are reset when there are changes that affect |
| 9650 | 9598 | * bandwidth. Anything that affects bandwidth needs to go through |
| @@ -9952,8 +9900,19 @@ static int parse_hdmi_amd_vsdb(struct amdgpu_dm_connector *aconnector, · 301 unmodified lines | ||
| 9952 | 9900 | return valid_vsdb_found ? i : -ENODEV; |
| 9953 | 9901 | } |
| 9954 | 9902 | |
| 9903 | +/** | |
| 9904 | + * amdgpu_dm_update_freesync_caps - Update Freesync capabilities | |
| 9905 | + * | |
| 9906 | + * @connector: Connector to query. | |
| 9907 | + * @edid: EDID from monitor | |
| 9908 | + * | |
| 9909 | + * Amdgpu supports Freesync in DP and HDMI displays, and it is required to keep | |
| 9910 | + * track of some of the display information in the internal data struct used by | |
| 9911 | + * amdgpu_dm. This function checks which type of connector we need to set the | |
| 9912 | + * FreeSync parameters. | |
| 9913 | + */ | |
| 9955 | 9914 | void amdgpu_dm_update_freesync_caps(struct drm_connector *connector, |
| 9956 | − struct edid *edid) | |
| 9915 | + struct edid *edid) | |
| 9957 | 9916 | { |
| 9958 | 9917 | int i = 0; |
| 9959 | 9918 | struct detailed_timing *timing; |
| @@ -9966,8 +9925,8 @@ void amdgpu_dm_update_freesync_caps(struct drm_connector *connector, · 6 unmodified lines | ||
| 9966 | 9925 | |
| 9967 | 9926 | struct drm_device *dev = connector->dev; |
| 9968 | 9927 | struct amdgpu_device *adev = drm_to_adev(dev); |
| 9969 | − bool freesync_capable = false; | |
| 9970 | 9928 | struct amdgpu_hdmi_vsdb_info vsdb_info = {0}; |
| 9929 | + bool freesync_capable = false; | |
| 9971 | 9930 | |
| 9972 | 9931 | if (!connector->state) { |
| 9973 | 9932 | DRM_ERROR("%s - Connector has no state", __func__); |
| @@ -9996,7 +9955,6 @@ void amdgpu_dm_update_freesync_caps(struct drm_connector *connector, · 22 unmodified lines | ||
| 9996 | 9955 | if (!adev->dm.freesync_module) |
| 9997 | 9956 | goto update; |
| 9998 | 9957 | |
| 9999 | − | |
| 10000 | 9958 | if (sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT |
| 10001 | 9959 | || sink->sink_signal == SIGNAL_TYPE_EDP) { |
| 10002 | 9960 | bool edid_check_required = false; |
| @@ -598,6 +598,10 @@ struct amdgpu_dm_connector { · 597 unmodified lines | ||
| 598 | 598 | * The 'current' sink is in dc_link->sink. */ |
| 599 | 599 | struct dc_sink *dc_sink; |
| 600 | 600 | struct dc_link *dc_link; |
| 601 | + | |
| 602 | + /** | |
| 603 | + * @dc_em_sink: Reference to the emulated (virtual) sink. | |
| 604 | + */ | |
| 601 | 605 | struct dc_sink *dc_em_sink; |
| 602 | 606 | |
| 603 | 607 | /* DM only */ |
| @@ -610,7 +614,16 @@ struct amdgpu_dm_connector { · 6 unmodified lines | ||
| 610 | 614 | struct amdgpu_i2c_adapter *i2c; |
| 611 | 615 | |
| 612 | 616 | /* Monitor range limits */ |
| 613 | − int min_vfreq ; | |
| 617 | + /** | |
| 618 | + * @min_vfreq: Minimal frequency supported by the display in Hz. This | |
| 619 | + * value is set to zero when there is no FreeSync support. | |
| 620 | + */ | |
| 621 | + int min_vfreq; | |
| 622 | + | |
| 623 | + /** | |
| 624 | + * @max_vfreq: Maximum frequency supported by the display in Hz. This | |
| 625 | + * value is set to zero when there is no FreeSync support. | |
| 626 | + */ | |
| 614 | 627 | int max_vfreq ; |
| 615 | 628 | int pixel_clock_mhz; |
| 616 | 629 | |
| @@ -668,7 +681,6 @@ struct dm_crtc_state { · 51 unmodified lines | ||
| 668 | 681 | |
| 669 | 682 | int crc_skip_count; |
| 670 | 683 | |
| 671 | − bool freesync_timing_changed; | |
| 672 | 684 | bool freesync_vrr_info_changed; |
| 673 | 685 | |
| 674 | 686 | bool dsc_force_changed; |
| @@ -705,11 +717,34 @@ struct dm_connector_state { · 30 unmodified lines | ||
| 705 | 717 | uint64_t pbn; |
| 706 | 718 | }; |
| 707 | 719 | |
| 720 | +/** | |
| 721 | + * struct amdgpu_hdmi_vsdb_info - Keep track of the VSDB info | |
| 722 | + * | |
| 723 | + * AMDGPU supports FreeSync over HDMI by using the VSDB section, and this | |
| 724 | + * struct is useful to keep track of the display-specific information about | |
| 725 | + * FreeSync. | |
| 726 | + */ | |
| 708 | 727 | struct amdgpu_hdmi_vsdb_info { |
| 709 | − unsigned int amd_vsdb_version; /* VSDB version, should be used to determine which VSIF to send */ | |
| 710 | − bool freesync_supported; /* FreeSync Supported */ | |
| 711 | − unsigned int min_refresh_rate_hz; /* FreeSync Minimum Refresh Rate in Hz */ | |
| 712 | − unsigned int max_refresh_rate_hz; /* FreeSync Maximum Refresh Rate in Hz */ | |
| 728 | + /** | |
| 729 | + * @amd_vsdb_version: Vendor Specific Data Block Version, should be | |
| 730 | + * used to determine which Vendor Specific InfoFrame (VSIF) to send. | |
| 731 | + */ | |
| 732 | + unsigned int amd_vsdb_version; | |
| 733 | + | |
| 734 | + /** | |
| 735 | + * @freesync_supported: FreeSync Supported. | |
| 736 | + */ | |
| 737 | + bool freesync_supported; | |
| 738 | + | |
| 739 | + /** | |
| 740 | + * @min_refresh_rate_hz: FreeSync Minimum Refresh Rate in Hz. | |
| 741 | + */ | |
| 742 | + unsigned int min_refresh_rate_hz; | |
| 743 | + | |
| 744 | + /** | |
| 745 | + * @max_refresh_rate_hz: FreeSync Maximum Refresh Rate in Hz | |
| 746 | + */ | |
| 747 | + unsigned int max_refresh_rate_hz; | |
| 713 | 748 | }; |
| 714 | 749 | |
| 715 | 750 | |
| @@ -29,7 +29,9 @@ · 28 unmodified lines | ||
| 29 | 29 | #include "modules/color/color_gamma.h" |
| 30 | 30 | #include "basics/conversion.h" |
| 31 | 31 | |
| 32 | −/* | |
| 32 | +/** | |
| 33 | + * DOC: overview | |
| 34 | + * | |
| 33 | 35 | * The DC interface to HW gives us the following color management blocks |
| 34 | 36 | * per pipe (surface): |
| 35 | 37 | * |
| @@ -71,8 +73,8 @@ · 35 unmodified lines | ||
| 71 | 73 | |
| 72 | 74 | #define MAX_DRM_LUT_VALUE 0xFFFF |
| 73 | 75 | |
| 74 | −/* | |
| 75 | − * Initialize the color module. | |
| 76 | +/** | |
| 77 | + * amdgpu_dm_init_color_mod - Initialize the color module. | |
| 76 | 78 | * |
| 77 | 79 | * We're not using the full color module, only certain components. |
| 78 | 80 | * Only call setup functions for components that we need. |
| @@ -82,7 +84,14 @@ void amdgpu_dm_init_color_mod(void) · 3 unmodified lines | ||
| 82 | 84 | setup_x_points_distribution(); |
| 83 | 85 | } |
| 84 | 86 | |
| 85 | −/* Extracts the DRM lut and lut size from a blob. */ | |
| 87 | +/** | |
| 88 | + * __extract_blob_lut - Extracts the DRM lut and lut size from a blob. | |
| 89 | + * @blob: DRM color mgmt property blob | |
| 90 | + * @size: lut size | |
| 91 | + * | |
| 92 | + * Returns: | |
| 93 | + * DRM LUT or NULL | |
| 94 | + */ | |
| 86 | 95 | static const struct drm_color_lut * |
| 87 | 96 | __extract_blob_lut(const struct drm_property_blob *blob, uint32_t *size) |
| 88 | 97 | { |
| @@ -90,13 +99,18 @@ __extract_blob_lut(const struct drm_property_blob *blob, uint32_t *size) · 1 unmodified line | ||
| 90 | 99 | return blob ? (struct drm_color_lut *)blob->data : NULL; |
| 91 | 100 | } |
| 92 | 101 | |
| 93 | −/* | |
| 94 | − * Return true if the given lut is a linear mapping of values, i.e. it acts | |
| 95 | − * like a bypass LUT. | |
| 102 | +/** | |
| 103 | + * __is_lut_linear - check if the given lut is a linear mapping of values | |
| 104 | + * @lut: given lut to check values | |
| 105 | + * @size: lut size | |
| 96 | 106 | * |
| 97 | 107 | * It is considered linear if the lut represents: |
| 98 | − * f(a) = (0xFF00/MAX_COLOR_LUT_ENTRIES-1)a; for integer a in | |
| 99 | − * [0, MAX_COLOR_LUT_ENTRIES) | |
| 108 | + * f(a) = (0xFF00/MAX_COLOR_LUT_ENTRIES-1)a; for integer a in [0, | |
| 109 | + * MAX_COLOR_LUT_ENTRIES) | |
| 110 | + * | |
| 111 | + * Returns: | |
| 112 | + * True if the given lut is a linear mapping of values, i.e. it acts like a | |
| 113 | + * bypass LUT. Otherwise, false. | |
| 100 | 114 | */ |
| 101 | 115 | static bool __is_lut_linear(const struct drm_color_lut *lut, uint32_t size) |
| 102 | 116 | { |
| @@ -119,9 +133,13 @@ static bool __is_lut_linear(const struct drm_color_lut *lut, uint32_t size) · 16 unmodified lines | ||
| 119 | 133 | return true; |
| 120 | 134 | } |
| 121 | 135 | |
| 122 | −/* | |
| 123 | − * Convert the drm_color_lut to dc_gamma. The conversion depends on the size | |
| 124 | − * of the lut - whether or not it's legacy. | |
| 136 | +/** | |
| 137 | + * __drm_lut_to_dc_gamma - convert the drm_color_lut to dc_gamma. | |
| 138 | + * @lut: DRM lookup table for color conversion | |
| 139 | + * @gamma: DC gamma to set entries | |
| 140 | + * @is_legacy: legacy or atomic gamma | |
| 141 | + * | |
| 142 | + * The conversion depends on the size of the lut - whether or not it's legacy. | |
| 125 | 143 | */ |
| 126 | 144 | static void __drm_lut_to_dc_gamma(const struct drm_color_lut *lut, |
| 127 | 145 | struct dc_gamma *gamma, bool is_legacy) |
| @@ -154,8 +172,11 @@ static void __drm_lut_to_dc_gamma(const struct drm_color_lut *lut, · 26 unmodified lines | ||
| 154 | 172 | } |
| 155 | 173 | } |
| 156 | 174 | |
| 157 | −/* | |
| 158 | − * Converts a DRM CTM to a DC CSC float matrix. | |
| 175 | +/** | |
| 176 | + * __drm_ctm_to_dc_matrix - converts a DRM CTM to a DC CSC float matrix | |
| 177 | + * @ctm: DRM color transformation matrix | |
| 178 | + * @matrix: DC CSC float matrix | |
| 179 | + * | |
| 159 | 180 | * The matrix needs to be a 3x4 (12 entry) matrix. |
| 160 | 181 | */ |
| 161 | 182 | static void __drm_ctm_to_dc_matrix(const struct drm_color_ctm *ctm, |
| @@ -189,7 +210,18 @@ static void __drm_ctm_to_dc_matrix(const struct drm_color_ctm *ctm, · 27 unmodified lines | ||
| 189 | 210 | } |
| 190 | 211 | } |
| 191 | 212 | |
| 192 | −/* Calculates the legacy transfer function - only for sRGB input space. */ | |
| 213 | +/** | |
| 214 | + * __set_legacy_tf - Calculates the legacy transfer function | |
| 215 | + * @func: transfer function | |
| 216 | + * @lut: lookup table that defines the color space | |
| 217 | + * @lut_size: size of respective lut | |
| 218 | + * @has_rom: if ROM can be used for hardcoded curve | |
| 219 | + * | |
| 220 | + * Only for sRGB input space | |
| 221 | + * | |
| 222 | + * Returns: | |
| 223 | + * 0 in case of success, -ENOMEM if fails | |
| 224 | + */ | |
| 193 | 225 | static int __set_legacy_tf(struct dc_transfer_func *func, |
| 194 | 226 | const struct drm_color_lut *lut, uint32_t lut_size, |
| 195 | 227 | bool has_rom) |
| @@ -218,7 +250,16 @@ static int __set_legacy_tf(struct dc_transfer_func *func, · 22 unmodified lines | ||
| 218 | 250 | return res ? 0 : -ENOMEM; |
| 219 | 251 | } |
| 220 | 252 | |
| 221 | −/* Calculates the output transfer function based on expected input space. */ | |
| 253 | +/** | |
| 254 | + * __set_output_tf - calculates the output transfer function based on expected input space. | |
| 255 | + * @func: transfer function | |
| 256 | + * @lut: lookup table that defines the color space | |
| 257 | + * @lut_size: size of respective lut | |
| 258 | + * @has_rom: if ROM can be used for hardcoded curve | |
| 259 | + * | |
| 260 | + * Returns: | |
| 261 | + * 0 in case of success. -ENOMEM if fails. | |
| 262 | + */ | |
| 222 | 263 | static int __set_output_tf(struct dc_transfer_func *func, |
| 223 | 264 | const struct drm_color_lut *lut, uint32_t lut_size, |
| 224 | 265 | bool has_rom) |
| @@ -262,7 +303,16 @@ static int __set_output_tf(struct dc_transfer_func *func, · 37 unmodified lines | ||
| 262 | 303 | return res ? 0 : -ENOMEM; |
| 263 | 304 | } |
| 264 | 305 | |
| 265 | −/* Caculates the input transfer function based on expected input space. */ | |
| 306 | +/** | |
| 307 | + * __set_input_tf - calculates the input transfer function based on expected | |
| 308 | + * input space. | |
| 309 | + * @func: transfer function | |
| 310 | + * @lut: lookup table that defines the color space | |
| 311 | + * @lut_size: size of respective lut. | |
| 312 | + * | |
| 313 | + * Returns: | |
| 314 | + * 0 in case of success. -ENOMEM if fails. | |
| 315 | + */ | |
| 266 | 316 | static int __set_input_tf(struct dc_transfer_func *func, |
| 267 | 317 | const struct drm_color_lut *lut, uint32_t lut_size) |
| 268 | 318 | { |
| @@ -285,13 +335,14 @@ static int __set_input_tf(struct dc_transfer_func *func, · 16 unmodified lines | ||
| 285 | 335 | } |
| 286 | 336 | |
| 287 | 337 | /** |
| 288 | − * amdgpu_dm_verify_lut_sizes | |
| 338 | + * amdgpu_dm_verify_lut_sizes - verifies if DRM luts match the hw supported sizes | |
| 289 | 339 | * @crtc_state: the DRM CRTC state |
| 290 | 340 | * |
| 291 | − * Verifies that the Degamma and Gamma LUTs attached to the |crtc_state| are of | |
| 292 | − * the expected size. | |
| 341 | + * Verifies that the Degamma and Gamma LUTs attached to the &crtc_state | |
| 342 | + * are of the expected size. | |
| 293 | 343 | * |
| 294 | − * Returns 0 on success. | |
| 344 | + * Returns: | |
| 345 | + * 0 on success. -EINVAL if any lut sizes are invalid. | |
| 295 | 346 | */ |
| 296 | 347 | int amdgpu_dm_verify_lut_sizes(const struct drm_crtc_state *crtc_state) |
| 297 | 348 | { |
| @@ -327,9 +378,9 @@ int amdgpu_dm_verify_lut_sizes(const struct drm_crtc_state *crtc_state) · 29 unmodified lines | ||
| 327 | 378 | * of the HW blocks as long as the CRTC CTM always comes before the |
| 328 | 379 | * CRTC RGM and after the CRTC DGM. |
| 329 | 380 | * |
| 330 | − * The CRTC RGM block will be placed in the RGM LUT block if it is non-linear. | |
| 331 | − * The CRTC DGM block will be placed in the DGM LUT block if it is non-linear. | |
| 332 | − * The CRTC CTM will be placed in the gamut remap block if it is non-linear. | |
| 381 | + * - The CRTC RGM block will be placed in the RGM LUT block if it is non-linear. | |
| 382 | + * - The CRTC DGM block will be placed in the DGM LUT block if it is non-linear. | |
| 383 | + * - The CRTC CTM will be placed in the gamut remap block if it is non-linear. | |
| 333 | 384 | * |
| 334 | 385 | * The RGM block is typically more fully featured and accurate across |
| 335 | 386 | * all ASICs - DCE can't support a custom non-linear CRTC DGM. |
| @@ -338,7 +389,8 @@ int amdgpu_dm_verify_lut_sizes(const struct drm_crtc_state *crtc_state) · 2 unmodified lines | ||
| 338 | 389 | * management at once we have to either restrict the usage of CRTC properties |
| 339 | 390 | * or blend adjustments together. |
| 340 | 391 | * |
| 341 | − * Returns 0 on success. | |
| 392 | + * Returns: | |
| 393 | + * 0 on success. Error code if setup fails. | |
| 342 | 394 | */ |
| 343 | 395 | int amdgpu_dm_update_crtc_color_mgmt(struct dm_crtc_state *crtc) |
| 344 | 396 | { |
| @@ -393,7 +445,7 @@ int amdgpu_dm_update_crtc_color_mgmt(struct dm_crtc_state *crtc) · 48 unmodified lines | ||
| 393 | 445 | if (r) |
| 394 | 446 | return r; |
| 395 | 447 | } else if (has_regamma) { |
| 396 | − /* CRTC RGM goes into RGM LUT. */ | |
| 448 | + /* If atomic regamma, CRTC RGM goes into RGM LUT. */ | |
| 397 | 449 | stream->out_transfer_func->type = TF_TYPE_DISTRIBUTED_POINTS; |
| 398 | 450 | stream->out_transfer_func->tf = TRANSFER_FUNCTION_LINEAR; |
| 399 | 451 | |
| @@ -450,9 +502,10 @@ int amdgpu_dm_update_crtc_color_mgmt(struct dm_crtc_state *crtc) · 50 unmodified lines | ||
| 450 | 502 | * |
| 451 | 503 | * Update the underlying dc_stream_state's input transfer function (ITF) in |
| 452 | 504 | * preparation for hardware commit. The transfer function used depends on |
| 453 | − * the prepartion done on the stream for color management. | |
| 505 | + * the preparation done on the stream for color management. | |
| 454 | 506 | * |
| 455 | − * Returns 0 on success. | |
| 507 | + * Returns: | |
| 508 | + * 0 on success. -ENOMEM if mem allocation fails. | |
| 456 | 509 | */ |
| 457 | 510 | int amdgpu_dm_update_plane_color_mgmt(struct dm_crtc_state *crtc, |
| 458 | 511 | struct dc_plane_state *dc_plane_state) |
| @@ -27,6 +27,7 @@ · 26 unmodified lines | ||
| 27 | 27 | #include <linux/acpi.h> |
| 28 | 28 | #include <linux/i2c.h> |
| 29 | 29 | |
| 30 | +#include <drm/drm_atomic.h> | |
| 30 | 31 | #include <drm/drm_probe_helper.h> |
| 31 | 32 | #include <drm/amdgpu_drm.h> |
| 32 | 33 | #include <drm/drm_edid.h> |
| @@ -153,41 +154,28 @@ enum dc_edid_status dm_helpers_parse_edid_caps( · 120 unmodified lines | ||
| 153 | 154 | return result; |
| 154 | 155 | } |
| 155 | 156 | |
| 156 | −static void get_payload_table( | |
| 157 | − struct amdgpu_dm_connector *aconnector, | |
| 158 | − struct dp_mst_stream_allocation_table *proposed_table) | |
| 157 | +static void | |
| 158 | +fill_dc_mst_payload_table_from_drm(struct drm_dp_mst_topology_state *mst_state, | |
| 159 | + struct amdgpu_dm_connector *aconnector, | |
| 160 | + struct dc_dp_mst_stream_allocation_table *table) | |
| 159 | 161 | { |
| 160 | − int i; | |
| 161 | − struct drm_dp_mst_topology_mgr *mst_mgr = | |
| 162 | − &aconnector->mst_port->mst_mgr; | |
| 163 | − | |
| 164 | − mutex_lock(&mst_mgr->payload_lock); | |
| 165 | − | |
| 166 | − proposed_table->stream_count = 0; | |
| 167 | − | |
| 168 | − /* number of active streams */ | |
| 169 | − for (i = 0; i < mst_mgr->max_payloads; i++) { | |
| 170 | − if (mst_mgr->payloads[i].num_slots == 0) | |
| 171 | − break; /* end of vcp_id table */ | |
| 172 | − | |
| 173 | − ASSERT(mst_mgr->payloads[i].payload_state != | |
| 174 | − DP_PAYLOAD_DELETE_LOCAL); | |
| 175 | − | |
| 176 | − if (mst_mgr->payloads[i].payload_state == DP_PAYLOAD_LOCAL || | |
| 177 | − mst_mgr->payloads[i].payload_state == | |
| 178 | − DP_PAYLOAD_REMOTE) { | |
| 179 | − | |
| 180 | − struct dp_mst_stream_allocation *sa = | |
| 181 | − &proposed_table->stream_allocations[ | |
| 182 | − proposed_table->stream_count]; | |
| 183 | − | |
| 184 | − sa->slot_count = mst_mgr->payloads[i].num_slots; | |
| 185 | − sa->vcp_id = mst_mgr->proposed_vcpis[i]->vcpi; | |
| 186 | − proposed_table->stream_count++; | |
| 187 | − } | |
| 162 | + struct dc_dp_mst_stream_allocation_table new_table = { 0 }; | |
| 163 | + struct dc_dp_mst_stream_allocation *sa; | |
| 164 | + struct drm_dp_mst_atomic_payload *payload; | |
| 165 | + | |
| 166 | + /* Fill payload info*/ | |
| 167 | + list_for_each_entry(payload, &mst_state->payloads, next) { | |
| 168 | + if (payload->delete) | |
| 169 | + continue; | |
| 170 | + | |
| 171 | + sa = &new_table.stream_allocations[new_table.stream_count]; | |
| 172 | + sa->slot_count = payload->time_slots; | |
| 173 | + sa->vcp_id = payload->vcpi; | |
| 174 | + new_table.stream_count++; | |
| 188 | 175 | } |
| 189 | 176 | |
| 190 | − mutex_unlock(&mst_mgr->payload_lock); | |
| 177 | + /* Overwrite the old table */ | |
| 178 | + *table = new_table; | |
| 191 | 179 | } |
| 192 | 180 | |
| 193 | 181 | void dm_helpers_dp_update_branch_info( |
| @@ -201,15 +189,13 @@ void dm_helpers_dp_update_branch_info( · 7 unmodified lines | ||
| 201 | 189 | bool dm_helpers_dp_mst_write_payload_allocation_table( |
| 202 | 190 | struct dc_context *ctx, |
| 203 | 191 | const struct dc_stream_state *stream, |
| 204 | − struct dp_mst_stream_allocation_table *proposed_table, | |
| 192 | + struct dc_dp_mst_stream_allocation_table *proposed_table, | |
| 205 | 193 | bool enable) |
| 206 | 194 | { |
| 207 | 195 | struct amdgpu_dm_connector *aconnector; |
| 208 | − struct dm_connector_state *dm_conn_state; | |
| 196 | + struct drm_dp_mst_topology_state *mst_state; | |
| 197 | + struct drm_dp_mst_atomic_payload *payload; | |
| 209 | 198 | struct drm_dp_mst_topology_mgr *mst_mgr; |
| 210 | − struct drm_dp_mst_port *mst_port; | |
| 211 | − bool ret; | |
| 212 | − u8 link_coding_cap = DP_8b_10b_ENCODING; | |
| 213 | 199 | |
| 214 | 200 | aconnector = (struct amdgpu_dm_connector *)stream->dm_stream_context; |
| 215 | 201 | /* Accessing the connector state is required for vcpi_slots allocation |
| @@ -220,40 +206,21 @@ bool dm_helpers_dp_mst_write_payload_allocation_table( · 4 unmodified lines | ||
| 220 | 206 | if (!aconnector || !aconnector->mst_port) |
| 221 | 207 | return false; |
| 222 | 208 | |
| 223 | − dm_conn_state = to_dm_connector_state(aconnector->base.state); | |
| 224 | − | |
| 225 | 209 | mst_mgr = &aconnector->mst_port->mst_mgr; |
| 226 | − | |
| 227 | − if (!mst_mgr->mst_state) | |
| 228 | − return false; | |
| 229 | − | |
| 230 | − mst_port = aconnector->port; | |
| 231 | − | |
| 232 | −#if defined(CONFIG_DRM_AMD_DC_DCN) | |
| 233 | − link_coding_cap = dc_link_dp_mst_decide_link_encoding_format(aconnector->dc_link); | |
| 234 | −#endif | |
| 235 | − | |
| 236 | − if (enable) { | |
| 237 | − | |
| 238 | − ret = drm_dp_mst_allocate_vcpi(mst_mgr, mst_port, | |
| 239 | − dm_conn_state->pbn, | |
| 240 | − dm_conn_state->vcpi_slots); | |
| 241 | − if (!ret) | |
| 242 | − return false; | |
| 243 | − | |
| 244 | − } else { | |
| 245 | − drm_dp_mst_reset_vcpi_slots(mst_mgr, mst_port); | |
| 246 | − } | |
| 210 | + mst_state = to_drm_dp_mst_topology_state(mst_mgr->base.state); | |
| 247 | 211 | |
| 248 | 212 | /* It's OK for this to fail */ |
| 249 | − drm_dp_update_payload_part1(mst_mgr, (link_coding_cap == DP_CAP_ANSI_128B132B) ? 0:1); | |
| 213 | + payload = drm_atomic_get_mst_payload_state(mst_state, aconnector->port); | |
| 214 | + if (enable) | |
| 215 | + drm_dp_add_payload_part1(mst_mgr, mst_state, payload); | |
| 216 | + else | |
| 217 | + drm_dp_remove_payload(mst_mgr, mst_state, payload); | |
| 250 | 218 | |
| 251 | 219 | /* mst_mgr->->payloads are VC payload notify MST branch using DPCD or |
| 252 | 220 | * AUX message. The sequence is slot 1-63 allocated sequence for each |
| 253 | 221 | * stream. AMD ASIC stream slot allocation should follow the same |
| 254 | 222 | * sequence. copy DRM MST allocation to dc */ |
| 255 | − | |
| 256 | − get_payload_table(aconnector, proposed_table); | |
| 223 | + fill_dc_mst_payload_table_from_drm(mst_state, aconnector, proposed_table); | |
| 257 | 224 | |
| 258 | 225 | return true; |
| 259 | 226 | } |
| @@ -310,8 +277,9 @@ bool dm_helpers_dp_mst_send_payload_allocation( · 50 unmodified lines | ||
| 310 | 277 | bool enable) |
| 311 | 278 | { |
| 312 | 279 | struct amdgpu_dm_connector *aconnector; |
| 280 | + struct drm_dp_mst_topology_state *mst_state; | |
| 313 | 281 | struct drm_dp_mst_topology_mgr *mst_mgr; |
| 314 | − struct drm_dp_mst_port *mst_port; | |
| 282 | + struct drm_dp_mst_atomic_payload *payload; | |
| 315 | 283 | enum mst_progress_status set_flag = MST_ALLOCATE_NEW_PAYLOAD; |
| 316 | 284 | enum mst_progress_status clr_flag = MST_CLEAR_ALLOCATED_PAYLOAD; |
| 317 | 285 | |
| @@ -320,19 +288,16 @@ bool dm_helpers_dp_mst_send_payload_allocation( · 2 unmodified lines | ||
| 320 | 288 | if (!aconnector || !aconnector->mst_port) |
| 321 | 289 | return false; |
| 322 | 290 | |
| 323 | − mst_port = aconnector->port; | |
| 324 | − | |
| 325 | 291 | mst_mgr = &aconnector->mst_port->mst_mgr; |
| 292 | + mst_state = to_drm_dp_mst_topology_state(mst_mgr->base.state); | |
| 326 | 293 | |
| 327 | − if (!mst_mgr->mst_state) | |
| 328 | − return false; | |
| 329 | − | |
| 294 | + payload = drm_atomic_get_mst_payload_state(mst_state, aconnector->port); | |
| 330 | 295 | if (!enable) { |
| 331 | 296 | set_flag = MST_CLEAR_ALLOCATED_PAYLOAD; |
| 332 | 297 | clr_flag = MST_ALLOCATE_NEW_PAYLOAD; |
| 333 | 298 | } |
| 334 | 299 | |
| 335 | − if (drm_dp_update_payload_part2(mst_mgr)) { | |
| 300 | + if (enable && drm_dp_add_payload_part2(mst_mgr, mst_state->base.state, payload)) { | |
| 336 | 301 | amdgpu_dm_set_mst_status(&aconnector->mst_status, |
| 337 | 302 | set_flag, false); |
| 338 | 303 | } else { |
| @@ -342,9 +307,6 @@ bool dm_helpers_dp_mst_send_payload_allocation( · 3 unmodified lines | ||
| 342 | 307 | clr_flag, false); |
| 343 | 308 | } |
| 344 | 309 | |
| 345 | − if (!enable) | |
| 346 | − drm_dp_mst_deallocate_vcpi(mst_mgr, mst_port); | |
| 347 | − | |
| 348 | 310 | return true; |
| 349 | 311 | } |
| 350 | 312 | |
| @@ -729,8 +691,14 @@ bool dm_helpers_dp_write_dsc_enable( · 378 unmodified lines | ||
| 729 | 691 | const struct dc_stream_state *stream, |
| 730 | 692 | bool enable) |
| 731 | 693 | { |
| 732 | − uint8_t enable_dsc = enable ? 1 : 0; | |
| 694 | + static const uint8_t DSC_DISABLE; | |
| 695 | + static const uint8_t DSC_DECODING = 0x01; | |
| 696 | + static const uint8_t DSC_PASSTHROUGH = 0x02; | |
| 697 | + | |
| 733 | 698 | struct amdgpu_dm_connector *aconnector; |
| 699 | + struct drm_dp_mst_port *port; | |
| 700 | + uint8_t enable_dsc = enable ? DSC_DECODING : DSC_DISABLE; | |
| 701 | + uint8_t enable_passthrough = enable ? DSC_PASSTHROUGH : DSC_DISABLE; | |
| 734 | 702 | uint8_t ret = 0; |
| 735 | 703 | |
| 736 | 704 | if (!stream) |
| @@ -750,8 +718,39 @@ bool dm_helpers_dp_write_dsc_enable( · 13 unmodified lines | ||
| 750 | 718 | aconnector->dsc_aux, stream, enable_dsc); |
| 751 | 719 | #endif |
| 752 | 720 | |
| 753 | − ret = drm_dp_dpcd_write(aconnector->dsc_aux, DP_DSC_ENABLE, &enable_dsc, 1); | |
| 754 | − DC_LOG_DC("Send DSC %s to MST RX\n", enable_dsc ? "enable" : "disable"); | |
| 721 | + port = aconnector->port; | |
| 722 | + | |
| 723 | + if (enable) { | |
| 724 | + if (port->passthrough_aux) { | |
| 725 | + ret = drm_dp_dpcd_write(port->passthrough_aux, | |
| 726 | + DP_DSC_ENABLE, | |
| 727 | + &enable_passthrough, 1); | |
| 728 | + DC_LOG_DC("Sent DSC pass-through enable to virtual dpcd port, ret = %u\n", | |
| 729 | + ret); | |
| 730 | + } | |
| 731 | + | |
| 732 | + ret = drm_dp_dpcd_write(aconnector->dsc_aux, | |
| 733 | + DP_DSC_ENABLE, &enable_dsc, 1); | |
| 734 | + DC_LOG_DC("Sent DSC decoding enable to %s port, ret = %u\n", | |
| 735 | + (port->passthrough_aux) ? "remote RX" : | |
| 736 | + "virtual dpcd", | |
| 737 | + ret); | |
| 738 | + } else { | |
| 739 | + ret = drm_dp_dpcd_write(aconnector->dsc_aux, | |
| 740 | + DP_DSC_ENABLE, &enable_dsc, 1); | |
| 741 | + DC_LOG_DC("Sent DSC decoding disable to %s port, ret = %u\n", | |
| 742 | + (port->passthrough_aux) ? "remote RX" : | |
| 743 | + "virtual dpcd", | |
| 744 | + ret); | |
| 745 | + | |
| 746 | + if (port->passthrough_aux) { | |
| 747 | + ret = drm_dp_dpcd_write(port->passthrough_aux, | |
| 748 | + DP_DSC_ENABLE, | |
| 749 | + &enable_passthrough, 1); | |
| 750 | + DC_LOG_DC("Sent DSC pass-through disable to virtual dpcd port, ret = %u\n", | |
| 751 | + ret); | |
| 752 | + } | |
| 753 | + } | |
| 755 | 754 | } |
| 756 | 755 | |
| 757 | 756 | if (stream->signal == SIGNAL_TYPE_DISPLAY_PORT || stream->signal == SIGNAL_TYPE_EDP) { |
| @@ -768,7 +767,7 @@ bool dm_helpers_dp_write_dsc_enable( · 10 unmodified lines | ||
| 768 | 767 | #endif |
| 769 | 768 | } |
| 770 | 769 | |
| 771 | − return (ret > 0); | |
| 770 | + return ret; | |
| 772 | 771 | } |
| 773 | 772 | |
| 774 | 773 | bool dm_helpers_is_dp_sink_present(struct dc_link *link) |
| @@ -879,6 +878,34 @@ void dm_helpers_smu_timeout(struct dc_context *ctx, unsigned int msg_id, unsigne · 104 unmodified lines | ||
| 879 | 878 | //amdgpu_device_gpu_recover(dc_context->driver-context, NULL); |
| 880 | 879 | } |
| 881 | 880 | |
| 881 | +void dm_helpers_init_panel_settings( | |
| 882 | + struct dc_context *ctx, | |
| 883 | + struct dc_panel_config *panel_config, | |
| 884 | + struct dc_sink *sink) | |
| 885 | +{ | |
| 886 | + // Extra Panel Power Sequence | |
| 887 | + panel_config->pps.extra_t3_ms = sink->edid_caps.panel_patch.extra_t3_ms; | |
| 888 | + panel_config->pps.extra_t7_ms = sink->edid_caps.panel_patch.extra_t7_ms; | |
| 889 | + panel_config->pps.extra_delay_backlight_off = sink->edid_caps.panel_patch.extra_delay_backlight_off; | |
| 890 | + panel_config->pps.extra_post_t7_ms = 0; | |
| 891 | + panel_config->pps.extra_pre_t11_ms = 0; | |
| 892 | + panel_config->pps.extra_t12_ms = sink->edid_caps.panel_patch.extra_t12_ms; | |
| 893 | + panel_config->pps.extra_post_OUI_ms = 0; | |
| 894 | + // Feature DSC | |
| 895 | + panel_config->dsc.disable_dsc_edp = false; | |
| 896 | + panel_config->dsc.force_dsc_edp_policy = 0; | |
| 897 | +} | |
| 898 | + | |
| 899 | +void dm_helpers_override_panel_settings( | |
| 900 | + struct dc_context *ctx, | |
| 901 | + struct dc_panel_config *panel_config) | |
| 902 | +{ | |
| 903 | + // Feature DSC | |
| 904 | + if (amdgpu_dc_debug_mask & DC_DISABLE_DSC) { | |
| 905 | + panel_config->dsc.disable_dsc_edp = true; | |
| 906 | + } | |
| 907 | +} | |
| 908 | + | |
| 882 | 909 | void *dm_helpers_allocate_gpu_mem( |
| 883 | 910 | struct dc_context *ctx, |
| 884 | 911 | enum dc_gpu_mem_alloc_type type, |
| @@ -36,6 +36,7 @@ · 35 unmodified lines | ||
| 36 | 36 | #include "dm_helpers.h" |
| 37 | 37 | |
| 38 | 38 | #include "dc_link_ddc.h" |
| 39 | +#include "dc_link_dp.h" | |
| 39 | 40 | #include "ddc_service_types.h" |
| 40 | 41 | #include "dpcd_defs.h" |
| 41 | 42 | |
| @@ -447,34 +448,13 @@ dm_dp_mst_detect(struct drm_connector *connector, · 405 unmodified lines | ||
| 447 | 448 | } |
| 448 | 449 | |
| 449 | 450 | static int dm_dp_mst_atomic_check(struct drm_connector *connector, |
| 450 | − struct drm_atomic_state *state) | |
| 451 | + struct drm_atomic_state *state) | |
| 451 | 452 | { |
| 452 | − struct drm_connector_state *new_conn_state = | |
| 453 | − drm_atomic_get_new_connector_state(state, connector); | |
| 454 | − struct drm_connector_state *old_conn_state = | |
| 455 | − drm_atomic_get_old_connector_state(state, connector); | |
| 456 | 453 | struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); |
| 457 | − struct drm_crtc_state *new_crtc_state; | |
| 458 | − struct drm_dp_mst_topology_mgr *mst_mgr; | |
| 459 | − struct drm_dp_mst_port *mst_port; | |
| 454 | + struct drm_dp_mst_topology_mgr *mst_mgr = &aconnector->mst_port->mst_mgr; | |
| 455 | + struct drm_dp_mst_port *mst_port = aconnector->port; | |
| 460 | 456 | |
| 461 | − mst_port = aconnector->port; | |
| 462 | − mst_mgr = &aconnector->mst_port->mst_mgr; | |
| 463 | − | |
| 464 | − if (!old_conn_state->crtc) | |
| 465 | − return 0; | |
| 466 | − | |
| 467 | − if (new_conn_state->crtc) { | |
| 468 | − new_crtc_state = drm_atomic_get_new_crtc_state(state, new_conn_state->crtc); | |
| 469 | − if (!new_crtc_state || | |
| 470 | − !drm_atomic_crtc_needs_modeset(new_crtc_state) || | |
| 471 | − new_crtc_state->enable) | |
| 472 | − return 0; | |
| 473 | − } | |
| 474 | − | |
| 475 | − return drm_dp_atomic_release_vcpi_slots(state, | |
| 476 | − mst_mgr, | |
| 477 | − mst_port); | |
| 457 | + return drm_dp_atomic_release_time_slots(state, mst_mgr, mst_port); | |
| 478 | 458 | } |
| 479 | 459 | |
| 480 | 460 | static const struct drm_connector_helper_funcs dm_dp_mst_connector_helper_funcs = { |
| @@ -618,15 +598,8 @@ void amdgpu_dm_initialize_dp_connector(struct amdgpu_display_manager *dm, · 137 unmodified lines | ||
| 618 | 598 | |
| 619 | 599 | dc_link_dp_get_max_link_enc_cap(aconnector->dc_link, &max_link_enc_cap); |
| 620 | 600 | aconnector->mst_mgr.cbs = &dm_mst_cbs; |
| 621 | − drm_dp_mst_topology_mgr_init( | |
| 622 | − &aconnector->mst_mgr, | |
| 623 | − adev_to_drm(dm->adev), | |
| 624 | − &aconnector->dm_dp_aux.aux, | |
| 625 | − 16, | |
| 626 | − 4, | |
| 627 | − max_link_enc_cap.lane_count, | |
| 628 | − drm_dp_bw_code_to_link_rate(max_link_enc_cap.link_rate), | |
| 629 | − aconnector->connector_id); | |
| 601 | + drm_dp_mst_topology_mgr_init(&aconnector->mst_mgr, adev_to_drm(dm->adev), | |
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