Pull drm updates from Dave Airlie: "Lots of stuff all over, some new AMD IP support and gang submit support. i915 has further DG2 and Meteorlake pieces, and a bunch of i915 display refactoring. msm has a shrinker rework. There are also a bunch of conversions to use kunit. This has two external pieces, some MEI changes needed for future Intel discrete GPUs. These should be acked by Greg. There is also a cross maintainer shared tree with some backlight rework from Hans in here. Core: - convert selftests to kunit - managed init for more objects - move to idr_init_base - rename fb and gem cma helpers to dma - hide unregistered connectors from getconnector ioctl - DSC passthrough aux support - backlight handling improvements - add dma_resv_assert_held to vmap/vunmap edid: - move luminance calculation to core fbdev: - fix aperture helper usage fourcc: - add more format helpers - add DRM_FORMAT_Cxx, DRM_FORMAT_Rxx, DRM_FORMAT_Dxx - add packed AYUV8888, XYUV8888 - add some kunit tests ttm: - allow bos without backing store - rewrite placement to use intersect/compatible functions dma-buf: - docs update - improve signalling when debugging udmabuf: - fix failure path GPF dp: - drop dp/mst legacy code - atomic mst state support - audio infoframe packing panel: - Samsung LTL101AL01 - B120XAN01.0 - R140NWF5 RH - DMT028VGHMCMI-1A T - AUO B133UAN02.1 - IVO M133NW4J-R3 - Innolux N120ACA-EA1 amdgpu: - Gang submit support - Mode2 reset for RDNA2 - New IP support: DCN 3.1.4, 3.2 SMU 13.x NBIO 7.7 GC 11.x PSP 13.x SDMA 6.x GMC 11.x - DSC passthrough support - PSP fixes for TA support - vangogh GFXOFF stats - clang fixes - gang submit CS cleanup prep work - fix VRAM eviction issues amdkfd: - GC 10.3 IP ISA fixes - fix CRIU regression - CPU fault on COW mapping fixes i915: - align fw versioning with kernel practices - add display substruct to i915 private - add initial runtime info to driver info - split out HDCP and backlight registers - MEI XeHP SDV GSC support - add per-gt sysfs defaults - TLB invalidation improvements - Disable PCI BAR resize on 32-bit - GuC firmware updates and compat changes - GuC log timestamp translation - DG2 preemption workaround changes - DG2 improved HDMI pixel clocks support - PCI BAR sanity checks - Enable DC5 on DG2 - DG2 DMC fw bumped - ADL-S PCI ID added - Meteorlake enablement - Rename ggtt_view to gtt_view - host RPS fixes - release mmaps on rpm suspend on discrete - clocking and dpll refactoring - VBT definitions and parsing updates - SKL watermark code extracted to separate file - allow seamless M/N changes on eDP panels - BUG_ON removal and cleanups msm: - DPU: simplified VBIF configuration cleanup CTL interfaces - DSI: removed unused msm_display_dsc_config struct switch regulator calls to new API switched to PANEL_BRIDGE for direct attached panels - DSI_PHY: convert drivers to parent_hws - DP: cleanup pixel_rate handling - HDMI: turned hdmi-phy-8996 into OF clk provider - misc dt-bindings fixes - choose eDP as primary display if it's available - support getting interconnects from either the mdss or the mdp5/dpu device nodes - gem: Shrinker + LRU re-work: - adds a shared GEM LRU+shrinker helper and moves msm over to that - reduce lock contention between retire and submit by avoiding the need to acquire obj lock in retire path (and instead using resv seeing obj's busyness in the shrinker - fix reclaim vs submit issues - GEM fault injection for triggering userspace error paths - Map/unmap optimization - Improved robustness for a6xx GPU recovery virtio: - improve error and edge conditions handling - convert to use managed helpers - stop exposing LINEAR modifier mgag200: - split modeset handling per model udl: - suspend/disconnect handling improvements vc4: - rework HDMI power up - depend on PM - better unplugging support ast: - resolution handling improvements ingenic: - add JZ4760(B) support - avoid a modeset when sharpness property is unchanged - use the new PM ops it6505: - power seq and clock updates ssd130x: - regmap bulk write - use atomic helpers instead of simple helpers via: - rename via_drv to via_dri1, consolidate all code. radeon: - drop DP MST experimental support - delayed work flush fix - use time_after ti-sn65dsi86: - DP support mediatek: - MT8195 DP support - drop of_gpio header - remove unneeded result - small DP code improvements vkms: - RGB565, XRGB64 and ARGB64 support sun4i: - tv: convert to atomic rcar-du: - Synopsys DW HDMI bridge DT bindings update exynos: - use drm_display_info.is_hdmi - correct return of mixer_mode_valid and hdmi_mode_valid omap: - refcounting fix rockchip: - RK3568 support - RK3399 gamma support" * tag 'drm-next-2022-10-05' of git://anongit.freedesktop.org/drm/drm: (1374 commits) drm/amdkfd: Fix UBSAN shift-out-of-bounds warning drm/amdkfd: Track unified memory when switching xnack mode drm/amdgpu: Enable sram on vcn_4_0_2 drm/amdgpu: Enable VCN DPG for GC11_0_1 drm/msm: Fix build break with recent mm tree drm/panel: simple: Use dev_err_probe() to simplify code drm/panel: panel-edp: Use dev_err_probe() to simplify code drm/panel: simple: Add Multi-Inno Technology MI0800FT-9 dt-bindings: display: simple: Add Multi-Inno Technology MI0800FT-9 panel drm/amdgpu: correct the memcpy size for ip discovery firmware drm/amdgpu: Skip put_reset_domain if it doesn't exist drm/amdgpu: remove switch from amdgpu_gmc_noretry_set drm/amdgpu: Fix mc_umc_status used uninitialized warning drm/amd/display: Prevent OTG shutdown during PSR SU drm/amdgpu: add page retirement handling for CPU RAS drm/amdgpu: use RAS error address convert api in mca notifier drm/amdgpu: support to convert dedicated umc mca address drm/amdgpu: export umc error address convert interface drm/amdgpu: fix sdma v4 init microcode error drm/amd/display: fix array-bounds error in dc_stream_remove_writeback() ...
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| @@ -755,6 +755,14 @@ struct drm_amdgpu_cs_chunk_data { · 754 unmodified lines | ||
| 755 | 755 | #define AMDGPU_INFO_FW_TOC 0x15 |
| 756 | 756 | /* Subquery id: Query CAP firmware version */ |
| 757 | 757 | #define AMDGPU_INFO_FW_CAP 0x16 |
| 758 | + /* Subquery id: Query GFX RLCP firmware version */ | |
| 759 | + #define AMDGPU_INFO_FW_GFX_RLCP 0x17 | |
| 760 | + /* Subquery id: Query GFX RLCV firmware version */ | |
| 761 | + #define AMDGPU_INFO_FW_GFX_RLCV 0x18 | |
| 762 | + /* Subquery id: Query MES_KIQ firmware version */ | |
| 763 | + #define AMDGPU_INFO_FW_MES_KIQ 0x19 | |
| 764 | + /* Subquery id: Query MES firmware version */ | |
| 765 | + #define AMDGPU_INFO_FW_MES 0x1a | |
| 758 | 766 | |
| 759 | 767 | /* number of bytes moved for TTM migration */ |
| 760 | 768 | #define AMDGPU_INFO_NUM_BYTES_MOVED 0x0f |
| @@ -99,18 +99,42 @@ extern "C" { · 98 unmodified lines | ||
| 99 | 99 | #define DRM_FORMAT_INVALID 0 |
| 100 | 100 | |
| 101 | 101 | /* color index */ |
| 102 | +#define DRM_FORMAT_C1 fourcc_code('C', '1', ' ', ' ') /* [7:0] C0:C1:C2:C3:C4:C5:C6:C7 1:1:1:1:1:1:1:1 eight pixels/byte */ | |
| 103 | +#define DRM_FORMAT_C2 fourcc_code('C', '2', ' ', ' ') /* [7:0] C0:C1:C2:C3 2:2:2:2 four pixels/byte */ | |
| 104 | +#define DRM_FORMAT_C4 fourcc_code('C', '4', ' ', ' ') /* [7:0] C0:C1 4:4 two pixels/byte */ | |
| 102 | 105 | #define DRM_FORMAT_C8 fourcc_code('C', '8', ' ', ' ') /* [7:0] C */ |
| 103 | 106 | |
| 104 | −/* 8 bpp Red */ | |
| 107 | +/* 1 bpp Darkness (inverse relationship between channel value and brightness) */ | |
| 108 | +#define DRM_FORMAT_D1 fourcc_code('D', '1', ' ', ' ') /* [7:0] D0:D1:D2:D3:D4:D5:D6:D7 1:1:1:1:1:1:1:1 eight pixels/byte */ | |
| 109 | + | |
| 110 | +/* 2 bpp Darkness (inverse relationship between channel value and brightness) */ | |
| 111 | +#define DRM_FORMAT_D2 fourcc_code('D', '2', ' ', ' ') /* [7:0] D0:D1:D2:D3 2:2:2:2 four pixels/byte */ | |
| 112 | + | |
| 113 | +/* 4 bpp Darkness (inverse relationship between channel value and brightness) */ | |
| 114 | +#define DRM_FORMAT_D4 fourcc_code('D', '4', ' ', ' ') /* [7:0] D0:D1 4:4 two pixels/byte */ | |
| 115 | + | |
| 116 | +/* 8 bpp Darkness (inverse relationship between channel value and brightness) */ | |
| 117 | +#define DRM_FORMAT_D8 fourcc_code('D', '8', ' ', ' ') /* [7:0] D */ | |
| 118 | + | |
| 119 | +/* 1 bpp Red (direct relationship between channel value and brightness) */ | |
| 120 | +#define DRM_FORMAT_R1 fourcc_code('R', '1', ' ', ' ') /* [7:0] R0:R1:R2:R3:R4:R5:R6:R7 1:1:1:1:1:1:1:1 eight pixels/byte */ | |
| 121 | + | |
| 122 | +/* 2 bpp Red (direct relationship between channel value and brightness) */ | |
| 123 | +#define DRM_FORMAT_R2 fourcc_code('R', '2', ' ', ' ') /* [7:0] R0:R1:R2:R3 2:2:2:2 four pixels/byte */ | |
| 124 | + | |
| 125 | +/* 4 bpp Red (direct relationship between channel value and brightness) */ | |
| 126 | +#define DRM_FORMAT_R4 fourcc_code('R', '4', ' ', ' ') /* [7:0] R0:R1 4:4 two pixels/byte */ | |
| 127 | + | |
| 128 | +/* 8 bpp Red (direct relationship between channel value and brightness) */ | |
| 105 | 129 | #define DRM_FORMAT_R8 fourcc_code('R', '8', ' ', ' ') /* [7:0] R */ |
| 106 | 130 | |
| 107 | −/* 10 bpp Red */ | |
| 131 | +/* 10 bpp Red (direct relationship between channel value and brightness) */ | |
| 108 | 132 | #define DRM_FORMAT_R10 fourcc_code('R', '1', '0', ' ') /* [15:0] x:R 6:10 little endian */ |
| 109 | 133 | |
| 110 | −/* 12 bpp Red */ | |
| 134 | +/* 12 bpp Red (direct relationship between channel value and brightness) */ | |
| 111 | 135 | #define DRM_FORMAT_R12 fourcc_code('R', '1', '2', ' ') /* [15:0] x:R 4:12 little endian */ |
| 112 | 136 | |
| 113 | −/* 16 bpp Red */ | |
| 137 | +/* 16 bpp Red (direct relationship between channel value and brightness) */ | |
| 114 | 138 | #define DRM_FORMAT_R16 fourcc_code('R', '1', '6', ' ') /* [15:0] R little endian */ |
| 115 | 139 | |
| 116 | 140 | /* 16 bpp RG */ |
| @@ -205,7 +229,9 @@ extern "C" { · 88 unmodified lines | ||
| 205 | 229 | #define DRM_FORMAT_VYUY fourcc_code('V', 'Y', 'U', 'Y') /* [31:0] Y1:Cb0:Y0:Cr0 8:8:8:8 little endian */ |
| 206 | 230 | |
| 207 | 231 | #define DRM_FORMAT_AYUV fourcc_code('A', 'Y', 'U', 'V') /* [31:0] A:Y:Cb:Cr 8:8:8:8 little endian */ |
| 232 | +#define DRM_FORMAT_AVUY8888 fourcc_code('A', 'V', 'U', 'Y') /* [31:0] A:Cr:Cb:Y 8:8:8:8 little endian */ | |
| 208 | 233 | #define DRM_FORMAT_XYUV8888 fourcc_code('X', 'Y', 'U', 'V') /* [31:0] X:Y:Cb:Cr 8:8:8:8 little endian */ |
| 234 | +#define DRM_FORMAT_XVUY8888 fourcc_code('X', 'V', 'U', 'Y') /* [31:0] X:Cr:Cb:Y 8:8:8:8 little endian */ | |
| 209 | 235 | #define DRM_FORMAT_VUY888 fourcc_code('V', 'U', '2', '4') /* [23:0] Cr:Cb:Y 8:8:8 little endian */ |
| 210 | 236 | #define DRM_FORMAT_VUY101010 fourcc_code('V', 'U', '3', '0') /* Y followed by U then V, 10:10:10. Non-linear modifier only */ |
| 211 | 237 | |
| @@ -675,11 +675,11 @@ struct drm_mode_fb_cmd { · 674 unmodified lines | ||
| 675 | 675 | * fetch metadata about an existing frame-buffer. |
| 676 | 676 | * |
| 677 | 677 | * In case of planar formats, this struct allows up to 4 buffer objects with |
| 678 | − * offsets and pitches per plane. The pitch and offset order is dictated by the | |
| 679 | − * format FourCC as defined by ``drm_fourcc.h``, e.g. NV12 is described as: | |
| 678 | + * offsets and pitches per plane. The pitch and offset order are dictated by | |
| 679 | + * the format FourCC as defined by ``drm_fourcc.h``, e.g. NV12 is described as: | |
| 680 | 680 | * |
| 681 | − * YUV 4:2:0 image with a plane of 8 bit Y samples followed by an | |
| 682 | − * interleaved U/V plane containing 8 bit 2x2 subsampled colour difference | |
| 681 | + * YUV 4:2:0 image with a plane of 8-bit Y samples followed by an | |
| 682 | + * interleaved U/V plane containing 8-bit 2x2 subsampled colour difference | |
| 683 | 683 | * samples. |
| 684 | 684 | * |
| 685 | 685 | * So it would consist of a Y plane at ``offsets[0]`` and a UV plane at |
| @@ -224,6 +224,53 @@ struct drm_panfrost_madvise { · 223 unmodified lines | ||
| 224 | 224 | __u32 retained; /* out, whether backing store still exists */ |
| 225 | 225 | }; |
| 226 | 226 | |
| 227 | +/* Definitions for coredump decoding in user space */ | |
| 228 | +#define PANFROSTDUMP_MAJOR 1 | |
| 229 | +#define PANFROSTDUMP_MINOR 0 | |
| 230 | + | |
| 231 | +#define PANFROSTDUMP_MAGIC 0x464E4150 /* PANF */ | |
| 232 | + | |
| 233 | +#define PANFROSTDUMP_BUF_REG 0 | |
| 234 | +#define PANFROSTDUMP_BUF_BOMAP (PANFROSTDUMP_BUF_REG + 1) | |
| 235 | +#define PANFROSTDUMP_BUF_BO (PANFROSTDUMP_BUF_BOMAP + 1) | |
| 236 | +#define PANFROSTDUMP_BUF_TRAILER (PANFROSTDUMP_BUF_BO + 1) | |
| 237 | + | |
| 238 | +struct panfrost_dump_object_header { | |
| 239 | + __le32 magic; | |
| 240 | + __le32 type; | |
| 241 | + __le32 file_size; | |
| 242 | + __le32 file_offset; | |
| 243 | + | |
| 244 | + union { | |
| 245 | + struct pan_reg_hdr { | |
| 246 | + __le64 jc; | |
| 247 | + __le32 gpu_id; | |
| 248 | + __le32 major; | |
| 249 | + __le32 minor; | |
| 250 | + __le64 nbos; | |
| 251 | + } reghdr; | |
| 252 | + | |
| 253 | + struct pan_bomap_hdr { | |
| 254 | + __le32 valid; | |
| 255 | + __le64 iova; | |
| 256 | + __le32 data[2]; | |
| 257 | + } bomap; | |
| 258 | + | |
| 259 | + /* | |
| 260 | + * Force same size in case we want to expand the header | |
| 261 | + * with new fields and also keep it 512-byte aligned | |
| 262 | + */ | |
| 263 | + | |
| 264 | + __le32 sizer[496]; | |
| 265 | + }; | |
| 266 | +}; | |
| 267 | + | |
| 268 | +/* Registers object, an array of these */ | |
| 269 | +struct panfrost_dump_registers { | |
| 270 | + __le32 reg; | |
| 271 | + __le32 value; | |
| 272 | +}; | |
| 273 | + | |
| 227 | 274 | #if defined(__cplusplus) |
| 228 | 275 | } |
| 229 | 276 | #endif |