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Merge tag 'qcom-arm64-fixes-for-5.19' of git://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into arm/fixes

Qualcomm ARM64 DT fixes for v5.19 This removes duplicate includes in the sc7180-trogdor files, which accidentally ended up disabling nodes intended to be enabled. It corrects identifiers for CPU6/7 on MSM8994. On SM8450 the UFS node's interconnects property is updated to match the #interconnect-cells, avoiding sync_state issues and the GIC ITS is defined, to correct the references from the PCIe nodes. On SDM845 the display subsystem's AHB clock is corrected and on msm8992 devices, the supplies for lvs 1 and 2 are correctly specified. Lastly, a welcome addition of Konrad as reviewer for the Qualcomm SoC. * tag 'qcom-arm64-fixes-for-5.19' of git://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux: arm64: dts: qcom: msm8992-*: Fix vdd_lvs1_2-supply typo MAINTAINERS: Add myself as a reviewer for Qualcomm ARM/64 support arm64: dts: qcom: sdm845: use dispcc AHB clock for mdss node arm64: dts: qcom: sm8450 add ITS device tree node arm64: dts: qcom: msm8994: Fix CPU6/7 reg values arm64: dts: qcom: sm8450: fix interconnects property of UFS node arm64: dts: qcom: Remove duplicate sc7180-trogdor include on lazor/homestar

Arnd Bergmann committed 4 years ago

Commit 7ecd8a72 parents f99d621 5fb77958 files · +20 −9Browse files

Unified · Split

8 files
  1. MAINTAINERS +1 −0
  2. arch/arm64/boot/dts/qcom/msm8992-lg-bullhead.dtsi +1 −1
  3. arch/arm64/boot/dts/qcom/msm8992-xiaomi-libra.dts +1 −1
  4. arch/arm64/boot/dts/qcom/msm8994.dtsi +2 −2
  5. arch/arm64/boot/dts/qcom/sc7180-trogdor-homestar.dtsi +1 −1
  6. arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor.dtsi +1 −1
  7. arch/arm64/boot/dts/qcom/sdm845.dtsi +1 −1
  8. arch/arm64/boot/dts/qcom/sm8450.dtsi +12 −2
MAINTAINERS+1−0
@@ -2540,6 +2540,7 @@ W: http://www.armlinux.org.uk/ · 2539 unmodified lines
2540ARM/QUALCOMM SUPPORT2540ARM/QUALCOMM SUPPORT
2541M: Andy Gross <agross@kernel.org>2541M: Andy Gross <agross@kernel.org>
2542M: Bjorn Andersson <bjorn.andersson@linaro.org>2542M: Bjorn Andersson <bjorn.andersson@linaro.org>
2543R: Konrad Dybcio <konrad.dybcio@somainline.org>
2543L: linux-arm-msm@vger.kernel.org2544L: linux-arm-msm@vger.kernel.org
2544S: Maintained2545S: Maintained
2545T: git git://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux.git2546T: git git://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux.git
arch/arm64/boot/dts/qcom/msm8992-lg-bullhead.dtsi+1−1
@@ -74,7 +74,7 @@ · 73 unmodified lines
74 vdd_l17_29-supply = <&vph_pwr>;74 vdd_l17_29-supply = <&vph_pwr>;
75 vdd_l20_21-supply = <&vph_pwr>;75 vdd_l20_21-supply = <&vph_pwr>;
76 vdd_l25-supply = <&pm8994_s5>;76 vdd_l25-supply = <&pm8994_s5>;
77 vdd_lvs1_2 = <&pm8994_s4>;77 vdd_lvs1_2-supply = <&pm8994_s4>;
78 78
79 /* S1, S2, S6 and S12 are managed by RPMPD */79 /* S1, S2, S6 and S12 are managed by RPMPD */
80 80
arch/arm64/boot/dts/qcom/msm8992-xiaomi-libra.dts+1−1
@@ -171,7 +171,7 @@ · 170 unmodified lines
171 vdd_l17_29-supply = <&vph_pwr>;171 vdd_l17_29-supply = <&vph_pwr>;
172 vdd_l20_21-supply = <&vph_pwr>;172 vdd_l20_21-supply = <&vph_pwr>;
173 vdd_l25-supply = <&pm8994_s5>;173 vdd_l25-supply = <&pm8994_s5>;
174 vdd_lvs1_2 = <&pm8994_s4>;174 vdd_lvs1_2-supply = <&pm8994_s4>;
175 175
176 /* S1, S2, S6 and S12 are managed by RPMPD */176 /* S1, S2, S6 and S12 are managed by RPMPD */
177 177
arch/arm64/boot/dts/qcom/msm8994.dtsi+2−2
@@ -100,7 +100,7 @@ · 99 unmodified lines
100 CPU6: cpu@102 {100 CPU6: cpu@102 {
101 device_type = "cpu";101 device_type = "cpu";
102 compatible = "arm,cortex-a57";102 compatible = "arm,cortex-a57";
103 reg = <0x0 0x101>;103 reg = <0x0 0x102>;
104 enable-method = "psci";104 enable-method = "psci";
105 next-level-cache = <&L2_1>;105 next-level-cache = <&L2_1>;
106 };106 };
@@ -108,7 +108,7 @@ · 1 unmodified line
108 CPU7: cpu@103 {108 CPU7: cpu@103 {
109 device_type = "cpu";109 device_type = "cpu";
110 compatible = "arm,cortex-a57";110 compatible = "arm,cortex-a57";
111 reg = <0x0 0x101>;111 reg = <0x0 0x103>;
112 enable-method = "psci";112 enable-method = "psci";
113 next-level-cache = <&L2_1>;113 next-level-cache = <&L2_1>;
114 };114 };
arch/arm64/boot/dts/qcom/sc7180-trogdor-homestar.dtsi+1−1
@@ -5,7 +5,7 @@ · 4 unmodified lines
5 * Copyright 2021 Google LLC.5 * Copyright 2021 Google LLC.
6 */6 */
7 7
8#include "sc7180-trogdor.dtsi"8/* This file must be included after sc7180-trogdor.dtsi */
9 9
10/ {10/ {
11 /* BOARD-SPECIFIC TOP LEVEL NODES */11 /* BOARD-SPECIFIC TOP LEVEL NODES */
arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor.dtsi+1−1
@@ -5,7 +5,7 @@ · 4 unmodified lines
5 * Copyright 2020 Google LLC.5 * Copyright 2020 Google LLC.
6 */6 */
7 7
8#include "sc7180-trogdor.dtsi"8/* This file must be included after sc7180-trogdor.dtsi */
9 9
10&ap_sar_sensor {10&ap_sar_sensor {
11 semtech,cs0-ground;11 semtech,cs0-ground;
arch/arm64/boot/dts/qcom/sdm845.dtsi+1−1
@@ -4244,7 +4244,7 @@ · 4243 unmodified lines
4244 4244
4245 power-domains = <&dispcc MDSS_GDSC>;4245 power-domains = <&dispcc MDSS_GDSC>;
4246 4246
4247 clocks = <&gcc GCC_DISP_AHB_CLK>,4247 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
4248 <&dispcc DISP_CC_MDSS_MDP_CLK>;4248 <&dispcc DISP_CC_MDSS_MDP_CLK>;
4249 clock-names = "iface", "core";4249 clock-names = "iface", "core";
4250 4250
arch/arm64/boot/dts/qcom/sm8450.dtsi+12−2
@@ -2853,6 +2853,16 @@ · 2852 unmodified lines
2853 reg = <0x0 0x17100000 0x0 0x10000>, /* GICD */2853 reg = <0x0 0x17100000 0x0 0x10000>, /* GICD */
2854 <0x0 0x17180000 0x0 0x200000>; /* GICR * 8 */2854 <0x0 0x17180000 0x0 0x200000>; /* GICR * 8 */
2855 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;2855 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
2856 #address-cells = <2>;
2857 #size-cells = <2>;
2858 ranges;
2859
2860 gic_its: msi-controller@17140000 {
2861 compatible = "arm,gic-v3-its";
2862 reg = <0x0 0x17140000 0x0 0x20000>;
2863 msi-controller;
2864 #msi-cells = <1>;
2865 };
2856 };2866 };
2857 2867
2858 timer@17420000 {2868 timer@17420000 {
@@ -3037,8 +3047,8 @@ · 178 unmodified lines
3037 3047
3038 iommus = <&apps_smmu 0xe0 0x0>;3048 iommus = <&apps_smmu 0xe0 0x0>;
3039 3049
3040 interconnects = <&aggre1_noc MASTER_UFS_MEM &mc_virt SLAVE_EBI1>,3050 interconnects = <&aggre1_noc MASTER_UFS_MEM 0 &mc_virt SLAVE_EBI1 0>,
3041 <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_UFS_MEM_CFG>;3051 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_UFS_MEM_CFG 0>;
3042 interconnect-names = "ufs-ddr", "cpu-ufs";3052 interconnect-names = "ufs-ddr", "cpu-ufs";
3043 clock-names =3053 clock-names =
3044 "core_clk",3054 "core_clk",