Need to sync some header include that propagated through drm-intel-next. v2: After some changes in drm/drm-next
Unified · Split
| @@ -32,8 +32,6 @@ properties: · 31 unmodified lines | ||
| 32 | 32 | - innolux,hj110iz-01a |
| 33 | 33 | # STARRY 2081101QFH032011-53G 10.1" WUXGA TFT LCD panel |
| 34 | 34 | - starry,2081101qfh032011-53g |
| 35 | − # STARRY himax83102-j02 10.51" WUXGA TFT LCD panel | |
| 36 | − - starry,himax83102-j02 | |
| 37 | 35 | # STARRY ili9882t 10.51" WUXGA TFT LCD panel |
| 38 | 36 | - starry,ili9882t |
| 39 | 37 | |
| @@ -0,0 +1,77 @@ | ||
| 1 | +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) | |
| 2 | +%YAML 1.2 | |
| 3 | +--- | |
| 4 | +$id: http://devicetree.org/schemas/display/panel/himax,hx83102.yaml# | |
| 5 | +$schema: http://devicetree.org/meta-schemas/core.yaml# | |
| 6 | + | |
| 7 | +title: Himax HX83102 MIPI-DSI LCD panel controller | |
| 8 | + | |
| 9 | +maintainers: | |
| 10 | + - Cong Yang <yangcong5@huaqin.corp-partner.google.com> | |
| 11 | + | |
| 12 | +allOf: | |
| 13 | + - $ref: panel-common.yaml# | |
| 14 | + | |
| 15 | +properties: | |
| 16 | + compatible: | |
| 17 | + items: | |
| 18 | + - enum: | |
| 19 | + # Boe nv110wum-l60 11.0" WUXGA TFT LCD panel | |
| 20 | + - boe,nv110wum-l60 | |
| 21 | + # IVO t109nw41 11.0" WUXGA TFT LCD panel | |
| 22 | + - ivo,t109nw41 | |
| 23 | + # STARRY himax83102-j02 10.51" WUXGA TFT LCD panel | |
| 24 | + - starry,himax83102-j02 | |
| 25 | + - const: himax,hx83102 | |
| 26 | + | |
| 27 | + reg: | |
| 28 | + description: the virtual channel number of a DSI peripheral | |
| 29 | + | |
| 30 | + enable-gpios: | |
| 31 | + description: a GPIO spec for the enable pin | |
| 32 | + | |
| 33 | + pp1800-supply: | |
| 34 | + description: core voltage supply | |
| 35 | + | |
| 36 | + avdd-supply: | |
| 37 | + description: phandle of the regulator that provides positive voltage | |
| 38 | + | |
| 39 | + avee-supply: | |
| 40 | + description: phandle of the regulator that provides negative voltage | |
| 41 | + | |
| 42 | + backlight: true | |
| 43 | + port: true | |
| 44 | + rotation: true | |
| 45 | + | |
| 46 | +required: | |
| 47 | + - compatible | |
| 48 | + - reg | |
| 49 | + - enable-gpios | |
| 50 | + - pp1800-supply | |
| 51 | + - avdd-supply | |
| 52 | + - avee-supply | |
| 53 | + | |
| 54 | +additionalProperties: false | |
| 55 | + | |
| 56 | +examples: | |
| 57 | + - | | |
| 58 | + dsi { | |
| 59 | + #address-cells = <1>; | |
| 60 | + #size-cells = <0>; | |
| 61 | + panel@0 { | |
| 62 | + compatible = "starry,himax83102-j02", "himax,hx83102"; | |
| 63 | + reg = <0>; | |
| 64 | + enable-gpios = <&pio 45 0>; | |
| 65 | + avdd-supply = <&ppvarn_lcd>; | |
| 66 | + avee-supply = <&ppvarp_lcd>; | |
| 67 | + pp1800-supply = <&pp1800_lcd>; | |
| 68 | + backlight = <&backlight_lcd0>; | |
| 69 | + port { | |
| 70 | + panel_in: endpoint { | |
| 71 | + remote-endpoint = <&dsi_out>; | |
| 72 | + }; | |
| 73 | + }; | |
| 74 | + }; | |
| 75 | + }; | |
| 76 | + | |
| 77 | +... | |
| @@ -0,0 +1,117 @@ | ||
| 1 | +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) | |
| 2 | +%YAML 1.2 | |
| 3 | +--- | |
| 4 | +$id: http://devicetree.org/schemas/display/panel/panel-edp-legacy.yaml# | |
| 5 | +$schema: http://devicetree.org/meta-schemas/core.yaml# | |
| 6 | + | |
| 7 | +title: Legacy eDP panels from before the "edp-panel" compatible | |
| 8 | + | |
| 9 | +maintainers: | |
| 10 | + - Douglas Anderson <dianders@chromium.org> | |
| 11 | + | |
| 12 | +description: | | |
| 13 | + This binding file is a collection of eDP panels from before the generic | |
| 14 | + "edp-panel" compatible was introduced. It is kept around to support old | |
| 15 | + dts files. The only reason one might add a new panel here instead of using | |
| 16 | + the generic "edp-panel" is if it needed to be used on an eDP controller | |
| 17 | + that doesn't support the generic "edp-panel" compatible, but it should be | |
| 18 | + a strong preference to add the generic "edp-panel" compatible instead. | |
| 19 | + | |
| 20 | +allOf: | |
| 21 | + - $ref: panel-common.yaml# | |
| 22 | + | |
| 23 | +properties: | |
| 24 | + compatible: | |
| 25 | + enum: | |
| 26 | + # compatible must be listed in alphabetical order, ordered by compatible. | |
| 27 | + # The description in the comment is mandatory for each compatible. | |
| 28 | + | |
| 29 | + # AU Optronics Corporation 10.1" WSVGA TFT LCD panel | |
| 30 | + - auo,b101ean01 | |
| 31 | + # AUO B116XAK01 eDP TFT LCD panel | |
| 32 | + - auo,b116xa01 | |
| 33 | + # AU Optronics Corporation 13.3" FHD (1920x1080) color TFT-LCD panel | |
| 34 | + - auo,b133htn01 | |
| 35 | + # AU Optronics Corporation 13.3" WXGA (1366x768) TFT LCD panel | |
| 36 | + - auo,b133xtn01 | |
| 37 | + # BOE OPTOELECTRONICS TECHNOLOGY 10.1" WXGA TFT LCD panel | |
| 38 | + - boe,nv101wxmn51 | |
| 39 | + # BOE NV133FHM-N61 13.3" FHD (1920x1080) TFT LCD Panel | |
| 40 | + - boe,nv110wtm-n61 | |
| 41 | + # BOE NV110WTM-N61 11.0" 2160x1440 TFT LCD Panel | |
| 42 | + - boe,nv133fhm-n61 | |
| 43 | + # BOE NV133FHM-N62 13.3" FHD (1920x1080) TFT LCD Panel | |
| 44 | + - boe,nv133fhm-n62 | |
| 45 | + # BOE NV140FHM-N49 14.0" FHD a-Si FT panel | |
| 46 | + - boe,nv140fhmn49 | |
| 47 | + # Innolux Corporation 11.6" WXGA (1366x768) TFT LCD panel | |
| 48 | + - innolux,n116bca-ea1 | |
| 49 | + # Innolux Corporation 11.6" WXGA (1366x768) TFT LCD panel | |
| 50 | + - innolux,n116bge | |
| 51 | + # InnoLux 13.3" FHD (1920x1080) eDP TFT LCD panel | |
| 52 | + - innolux,n125hce-gn1 | |
| 53 | + # Innolux P120ZDG-BF1 12.02 inch eDP 2K display panel | |
| 54 | + - innolux,p120zdg-bf1 | |
| 55 | + # King & Display KD116N21-30NV-A010 eDP TFT LCD panel | |
| 56 | + - kingdisplay,kd116n21-30nv-a010 | |
| 57 | + # LG LP079QX1-SP0V 7.9" (1536x2048 pixels) TFT LCD panel | |
| 58 | + - lg,lp079qx1-sp0v | |
| 59 | + # LG 9.7" (2048x1536 pixels) TFT LCD panel | |
| 60 | + - lg,lp097qx1-spa1 | |
| 61 | + # LG 12.0" (1920x1280 pixels) TFT LCD panel | |
| 62 | + - lg,lp120up1 | |
| 63 | + # LG 12.9" (2560x1700 pixels) TFT LCD panel | |
| 64 | + - lg,lp129qe | |
| 65 | + # NewEast Optoelectronics CO., LTD WJFH116008A eDP TFT LCD panel | |
| 66 | + - neweast,wjfh116008a | |
| 67 | + # Samsung 12.2" (2560x1600 pixels) TFT LCD panel | |
| 68 | + - samsung,lsn122dl01-c01 | |
| 69 | + # Samsung Electronics 14" WXGA (1366x768) TFT LCD panel | |
| 70 | + - samsung,ltn140at29-301 | |
| 71 | + # Sharp LD-D5116Z01B 12.3" WUXGA+ eDP panel | |
| 72 | + - sharp,ld-d5116z01b | |
| 73 | + # Sharp 12.3" (2400x1600 pixels) TFT LCD panel | |
| 74 | + - sharp,lq123p1jx31 | |
| 75 | + | |
| 76 | + backlight: true | |
| 77 | + ddc-i2c-bus: true | |
| 78 | + enable-gpios: true | |
| 79 | + panel-timing: true | |
| 80 | + port: true | |
| 81 | + power-supply: true | |
| 82 | + no-hpd: true | |
| 83 | + hpd-gpios: true | |
| 84 | + | |
| 85 | +additionalProperties: false | |
| 86 | + | |
| 87 | +required: | |
| 88 | + - compatible | |
| 89 | + - power-supply | |
| 90 | + | |
| 91 | +examples: | |
| 92 | + - | | |
| 93 | + panel: panel { | |
| 94 | + compatible = "innolux,n116bge"; | |
| 95 | + power-supply = <&panel_regulator>; | |
| 96 | + backlight = <&backlight>; | |
| 97 | + | |
| 98 | + panel-timing { | |
| 99 | + clock-frequency = <74250000>; | |
| 100 | + hactive = <1366>; | |
| 101 | + hfront-porch = <136>; | |
| 102 | + hback-porch = <60>; | |
| 103 | + hsync-len = <30>; | |
| 104 | + hsync-active = <0>; | |
| 105 | + vactive = <768>; | |
| 106 | + vfront-porch = <8>; | |
| 107 | + vback-porch = <12>; | |
| 108 | + vsync-len = <12>; | |
| 109 | + vsync-active = <0>; | |
| 110 | + }; | |
| 111 | + | |
| 112 | + port { | |
| 113 | + panel_in_edp: endpoint { | |
| 114 | + remote-endpoint = <&edp_out_panel>; | |
| 115 | + }; | |
| 116 | + }; | |
| 117 | + }; | |
| @@ -50,6 +50,12 @@ description: | · 49 unmodified lines | ||
| 50 | 50 | | Command or data | |
| 51 | 51 | |<D7><D6><D5><D4><D3><D2><D1><D0>| |
| 52 | 52 | |
| 53 | + The standard defines one pixel format for type C: RGB111. The industry | |
| 54 | + however has decided to provide the type A/B interface pixel formats also on | |
| 55 | + the Type C interface and most common among these are RGB565 and RGB666. | |
| 56 | + The MIPI DCS command set_address_mode (36h) has one bit that controls RGB/BGR | |
| 57 | + order. This gives each supported RGB format a BGR variant. | |
| 58 | + | |
| 53 | 59 | The panel resolution is specified using the panel-timing node properties |
| 54 | 60 | hactive (width) and vactive (height). The other mandatory panel-timing |
| 55 | 61 | properties should be set to zero except clock-frequency which can be |
| @@ -93,6 +99,28 @@ properties: · 37 unmodified lines | ||
| 93 | 99 | |
| 94 | 100 | spi-3wire: true |
| 95 | 101 | |
| 102 | + format: | |
| 103 | + description: > | |
| 104 | + Pixel format in bit order as going on the wire: | |
| 105 | + * `x2r1g1b1r1g1b1` - RGB111, 2 pixels per byte | |
| 106 | + * `x2b1g1r1b1g1r1` - BGR111, 2 pixels per byte | |
| 107 | + * `x1r1g1b1x1r1g1b1` - RGB111, 2 pixels per byte | |
| 108 | + * `x1b1g1r1x1b1g1r1` - BGR111, 2 pixels per byte | |
| 109 | + * `r5g6b5` - RGB565, 2 bytes | |
| 110 | + * `b5g6r5` - BGR565, 2 bytes | |
| 111 | + * `r6x2g6x2b6x2` - RGB666, 3 bytes | |
| 112 | + * `b6x2g6x2r6x2` - BGR666, 3 bytes | |
| 113 | + enum: | |
| 114 | + - x2r1g1b1r1g1b1 | |
| 115 | + - x2b1g1r1b1g1r1 | |
| 116 | + - x1r1g1b1x1r1g1b1 | |
| 117 | + - x1b1g1r1x1b1g1r1 | |
| 118 | + - r5g6b5 | |
| 119 | + - b5g6r5 | |
| 120 | + - r6x2g6x2b6x2 | |
| 121 | + - b6x2g6x2r6x2 | |
| 122 | + default: r5g6b5 | |
| 123 | + | |
| 96 | 124 | required: |
| 97 | 125 | - compatible |
| 98 | 126 | - reg |
| @@ -119,6 +147,8 @@ examples: · 20 unmodified lines | ||
| 119 | 147 | reset-gpios = <&gpio 25 GPIO_ACTIVE_HIGH>; |
| 120 | 148 | write-only; |
| 121 | 149 | |
| 150 | + format = "r5g6b5"; | |
| 151 | + | |
| 122 | 152 | backlight = <&backlight>; |
| 123 | 153 | |
| 124 | 154 | width-mm = <35>; |
| @@ -41,6 +41,12 @@ properties: · 40 unmodified lines | ||
| 41 | 41 | - auo,g190ean01 |
| 42 | 42 | # Kaohsiung Opto-Electronics Inc. 10.1" WUXGA (1920 x 1200) LVDS TFT LCD panel |
| 43 | 43 | - koe,tx26d202vm0bwa |
| 44 | + # Lincoln Technology Solutions, LCD185-101CT 10.1" TFT 1920x1200 | |
| 45 | + - lincolntech,lcd185-101ct | |
| 46 | + # Microtips Technology MF-101HIEBCAF0 10.1" WUXGA (1920x1200) TFT LCD panel | |
| 47 | + - microtips,mf-101hiebcaf0 | |
| 48 | + # Microtips Technology MF-103HIEB0GA0 10.25" 1920x720 TFT LCD panel | |
| 49 | + - microtips,mf-103hieb0ga0 | |
| 44 | 50 | # NLT Technologies, Ltd. 15.6" FHD (1920x1080) LVDS TFT LCD panel |
| 45 | 51 | - nlt,nl192108ac18-02d |
| 46 | 52 | |
| @@ -41,22 +41,10 @@ properties: · 40 unmodified lines | ||
| 41 | 41 | - ampire,am800600p5tmqw-tb8h |
| 42 | 42 | # AU Optronics Corporation 10.1" WSVGA TFT LCD panel |
| 43 | 43 | - auo,b101aw03 |
| 44 | − # AU Optronics Corporation 10.1" WSVGA TFT LCD panel | |
| 45 | − - auo,b101ean01 | |
| 46 | 44 | # AU Optronics Corporation 10.1" WXGA TFT LCD panel |
| 47 | 45 | - auo,b101xtn01 |
| 48 | − # AUO B116XAK01 eDP TFT LCD panel | |
| 49 | − - auo,b116xa01 | |
| 50 | 46 | # AU Optronics Corporation 11.6" HD (1366x768) color TFT-LCD panel |
| 51 | 47 | - auo,b116xw03 |
| 52 | − # AU Optronics Corporation 13.3" FHD (1920x1080) color TFT-LCD panel | |
| 53 | − - auo,b133han05 | |
| 54 | − # AU Optronics Corporation 13.3" FHD (1920x1080) color TFT-LCD panel | |
| 55 | − - auo,b133htn01 | |
| 56 | − # AU Optronics Corporation 13.3" WXGA (1366x768) TFT LCD panel | |
| 57 | − - auo,b133xtn01 | |
| 58 | − # AU Optronics Corporation 14.0" FHD (1920x1080) color TFT-LCD panel | |
| 59 | − - auo,b140han06 | |
| 60 | 48 | # AU Optronics Corporation 7.0" FHD (800 x 480) TFT LCD panel |
| 61 | 49 | - auo,g070vvn01 |
| 62 | 50 | # AU Optronics Corporation 10.1" (1280x800) color TFT LCD panel |
| @@ -81,16 +69,6 @@ properties: · 18 unmodified lines | ||
| 81 | 69 | - boe,ev121wxm-n10-1850 |
| 82 | 70 | # BOE HV070WSA-100 7.01" WSVGA TFT LCD panel |
| 83 | 71 | - boe,hv070wsa-100 |
| 84 | − # BOE OPTOELECTRONICS TECHNOLOGY 10.1" WXGA TFT LCD panel | |
| 85 | − - boe,nv101wxmn51 | |
| 86 | − # BOE NV133FHM-N61 13.3" FHD (1920x1080) TFT LCD Panel | |
| 87 | − - boe,nv110wtm-n61 | |
| 88 | − # BOE NV110WTM-N61 11.0" 2160x1440 TFT LCD Panel | |
| 89 | − - boe,nv133fhm-n61 | |
| 90 | − # BOE NV133FHM-N62 13.3" FHD (1920x1080) TFT LCD Panel | |
| 91 | − - boe,nv133fhm-n62 | |
| 92 | − # BOE NV140FHM-N49 14.0" FHD a-Si FT panel | |
| 93 | − - boe,nv140fhmn49 | |
| 94 | 72 | # Crystal Clear Technology CMT430B19N00 4.3" 480x272 TFT-LCD panel |
| 95 | 73 | - cct,cmt430b19n00 |
| 96 | 74 | # CDTech(H.K.) Electronics Limited 4.3" 480x272 color TFT-LCD panel |
| @@ -172,8 +150,6 @@ properties: · 75 unmodified lines | ||
| 172 | 150 | - hannstar,hsd100pxn1 |
| 173 | 151 | # Hitachi Ltd. Corporation 9" WVGA (800x480) TFT LCD panel |
| 174 | 152 | - hit,tx23d38vm0caa |
| 175 | − # InfoVision Optoelectronics M133NWF4 R0 13.3" FHD (1920x1080) TFT LCD panel | |
| 176 | − - ivo,m133nwf4-r0 | |
| 177 | 153 | # Innolux AT043TN24 4.3" WQVGA TFT LCD panel |
| 178 | 154 | - innolux,at043tn24 |
| 179 | 155 | # Innolux AT070TN92 7.0" WQVGA TFT LCD panel |
| @@ -192,22 +168,12 @@ properties: · 12 unmodified lines | ||
| 192 | 168 | - innolux,g121x1-l03 |
| 193 | 169 | # Innolux Corporation 12.1" G121XCE-L01 XGA (1024x768) TFT LCD panel |
| 194 | 170 | - innolux,g121xce-l01 |
| 195 | − # Innolux Corporation 11.6" WXGA (1366x768) TFT LCD panel | |
| 196 | − - innolux,n116bca-ea1 | |
| 197 | − # Innolux Corporation 11.6" WXGA (1366x768) TFT LCD panel | |
| 198 | − - innolux,n116bge | |
| 199 | − # InnoLux 13.3" FHD (1920x1080) eDP TFT LCD panel | |
| 200 | − - innolux,n125hce-gn1 | |
| 201 | 171 | # InnoLux 15.6" FHD (1920x1080) TFT LCD panel |
| 202 | 172 | - innolux,g156hce-l01 |
| 203 | 173 | # InnoLux 15.6" WXGA TFT LCD panel |
| 204 | 174 | - innolux,n156bge-l21 |
| 205 | − # Innolux P120ZDG-BF1 12.02 inch eDP 2K display panel | |
| 206 | − - innolux,p120zdg-bf1 | |
| 207 | 175 | # Innolux Corporation 7.0" WSVGA (1024x600) TFT LCD panel |
| 208 | 176 | - innolux,zj070na-01p |
| 209 | − # King & Display KD116N21-30NV-A010 eDP TFT LCD panel | |
| 210 | − - kingdisplay,kd116n21-30nv-a010 | |
| 211 | 177 | # Kaohsiung Opto-Electronics Inc. 5.7" QVGA (320 x 240) TFT LCD panel |
| 212 | 178 | - koe,tx14d24vm1bpa |
| 213 | 179 | # Kaohsiung Opto-Electronics. TX31D200VM0BAA 12.3" HSXGA LVDS panel |
| @@ -220,14 +186,6 @@ properties: · 6 unmodified lines | ||
| 220 | 186 | - lemaker,bl035-rgb-002 |
| 221 | 187 | # LG 7" (800x480 pixels) TFT LCD panel |
| 222 | 188 | - lg,lb070wv8 |
| 223 | − # LG LP079QX1-SP0V 7.9" (1536x2048 pixels) TFT LCD panel | |
| 224 | − - lg,lp079qx1-sp0v | |
| 225 | − # LG 9.7" (2048x1536 pixels) TFT LCD panel | |
| 226 | − - lg,lp097qx1-spa1 | |
| 227 | − # LG 12.0" (1920x1280 pixels) TFT LCD panel | |
| 228 | − - lg,lp120up1 | |
| 229 | − # LG 12.9" (2560x1700 pixels) TFT LCD panel | |
| 230 | − - lg,lp129qe | |
| 231 | 189 | # Logic Technologies LT161010-2NHC 7" WVGA TFT Cap Touch Module |
| 232 | 190 | - logictechno,lt161010-2nhc |
| 233 | 191 | # Logic Technologies LT161010-2NHR 7" WVGA TFT Resistive Touch Module |
| @@ -254,8 +212,6 @@ properties: · 20 unmodified lines | ||
| 254 | 212 | - nec,nl4827hc19-05b |
| 255 | 213 | # Netron-DY E231732 7.0" WSVGA TFT LCD panel |
| 256 | 214 | - netron-dy,e231732 |
| 257 | − # NewEast Optoelectronics CO., LTD WJFH116008A eDP TFT LCD panel | |
| 258 | − - neweast,wjfh116008a | |
| 259 | 215 | # Newhaven Display International 480 x 272 TFT LCD panel |
| 260 | 216 | - newhaven,nhd-4.3-480272ef-atxl |
| 261 | 217 | # New Vision Display 7.0" 800 RGB x 480 TFT LCD panel |
| @@ -280,6 +236,8 @@ properties: · 18 unmodified lines | ||
| 280 | 236 | - powertip,ph128800t006-zhc01 |
| 281 | 237 | # POWERTIP PH800480T013-IDF2 7.0" WVGA TFT LCD panel |
| 282 | 238 | - powertip,ph800480t013-idf02 |
| 239 | + # PrimeView PM070WL4 7.0" 800x480 TFT LCD panel | |
| 240 | + - primeview,pm070wl4 | |
| 283 | 241 | # QiaoDian XianShi Corporation 4"3 TFT LCD panel |
| 284 | 242 | - qiaodian,qd43003c0-40 |
| 285 | 243 | # Shenzhen QiShenglong Industrialist Co., Ltd. Gopher 2b 4.3" 480(RGB)x272 TFT LCD panel |
| @@ -290,16 +248,10 @@ properties: · 4 unmodified lines | ||
| 290 | 248 | - rocktech,rk070er9427 |
| 291 | 249 | # Rocktech Display Ltd. RK043FN48H 4.3" 480x272 LCD-TFT panel |
| 292 | 250 | - rocktech,rk043fn48h |
| 293 | − # Samsung 13.3" FHD (1920x1080 pixels) eDP AMOLED panel | |
| 294 | − - samsung,atna33xc20 | |
| 295 | − # Samsung 12.2" (2560x1600 pixels) TFT LCD panel | |
| 296 | − - samsung,lsn122dl01-c01 | |
| 297 | 251 | # Samsung Electronics 10.1" WXGA (1280x800) TFT LCD panel |
| 298 | 252 | - samsung,ltl101al01 |
| 299 | 253 | # Samsung Electronics 10.1" WSVGA TFT LCD panel |
| 300 | 254 | - samsung,ltn101nt05 |
| 301 | − # Samsung Electronics 14" WXGA (1366x768) TFT LCD panel | |
| 302 | − - samsung,ltn140at29-301 | |
| 303 | 255 | # Satoz SAT050AT40H12R2 5.0" WVGA TFT LCD panel |
| 304 | 256 | - satoz,sat050at40h12r2 |
| 305 | 257 | # Sharp LQ035Q7DB03 3.5" QVGA TFT LCD panel |
| @@ -308,18 +260,12 @@ properties: · 2 unmodified lines | ||
| 308 | 260 | - sharp,lq070y3dg3b |
| 309 | 261 | # Sharp Display Corp. LQ101K1LY04 10.07" WXGA TFT LCD panel |
| 310 | 262 | - sharp,lq101k1ly04 |
| 311 | − # Sharp 12.3" (2400x1600 pixels) TFT LCD panel | |
| 312 | − - sharp,lq123p1jx31 | |
| 313 | − # Sharp 14" (1920x1080 pixels) TFT LCD panel | |
| 314 | − - sharp,lq140m1jw46 | |
| 315 | 263 | # Sharp LS020B1DD01D 2.0" HQVGA TFT LCD panel |
| 316 | 264 | - sharp,ls020b1dd01d |
| 317 | 265 | # Shelly SCA07010-BFN-LNN 7.0" WVGA TFT LCD panel |
| 318 | 266 | - shelly,sca07010-bfn-lnn |
| 319 | 267 | # Starry KR070PE2T 7" WVGA TFT LCD panel |
| 320 | 268 | - starry,kr070pe2t |
| 321 | − # Starry 12.2" (1920x1200 pixels) TFT LCD panel | |
| 322 | − - starry,kr122ea0sra | |
| 323 | 269 | # Startek KD070WVFPA043-C069A 7" TFT LCD panel |
| 324 | 270 | - startek,kd070wvfpa |
| 325 | 271 | # Team Source Display Technology TST043015CMHX 4.3" WQVGA TFT LCD panel |
| @@ -0,0 +1,95 @@ | ||
| 1 | +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) | |
| 2 | +%YAML 1.2 | |
| 3 | +--- | |
| 4 | +$id: http://devicetree.org/schemas/display/panel/samsung,atna33xc20.yaml# | |
| 5 | +$schema: http://devicetree.org/meta-schemas/core.yaml# | |
| 6 | + | |
| 7 | +title: Samsung 13.3" FHD (1920x1080 pixels) eDP AMOLED panel | |
| 8 | + | |
| 9 | +maintainers: | |
| 10 | + - Douglas Anderson <dianders@chromium.org> | |
| 11 | + | |
| 12 | +allOf: | |
| 13 | + - $ref: panel-common.yaml# | |
| 14 | + | |
| 15 | +properties: | |
| 16 | + compatible: | |
| 17 | + const: samsung,atna33xc20 | |
| 18 | + | |
| 19 | + enable-gpios: true | |
| 20 | + port: true | |
| 21 | + power-supply: true | |
| 22 | + no-hpd: true | |
| 23 | + hpd-gpios: true | |
| 24 | + | |
| 25 | +additionalProperties: false | |
| 26 | + | |
| 27 | +required: | |
| 28 | + - compatible | |
| 29 | + - enable-gpios | |
| 30 | + - power-supply | |
| 31 | + | |
| 32 | +examples: | |
| 33 | + - | | |
| 34 | + #include <dt-bindings/clock/qcom,rpmh.h> | |
| 35 | + #include <dt-bindings/gpio/gpio.h> | |
| 36 | + #include <dt-bindings/interrupt-controller/irq.h> | |
| 37 | + | |
| 38 | + i2c { | |
| 39 | + #address-cells = <1>; | |
| 40 | + #size-cells = <0>; | |
| 41 | + | |
| 42 | + bridge@2d { | |
| 43 | + compatible = "ti,sn65dsi86"; | |
| 44 | + reg = <0x2d>; | |
| 45 | + | |
| 46 | + interrupt-parent = <&tlmm>; | |
| 47 | + interrupts = <10 IRQ_TYPE_LEVEL_HIGH>; | |
| 48 | + | |
| 49 | + enable-gpios = <&tlmm 102 GPIO_ACTIVE_HIGH>; | |
| 50 | + | |
| 51 | + vpll-supply = <&src_pp1800_s4a>; | |
| 52 | + vccio-supply = <&src_pp1800_s4a>; | |
| 53 | + vcca-supply = <&src_pp1200_l2a>; | |
| 54 | + vcc-supply = <&src_pp1200_l2a>; | |
| 55 | + | |
| 56 | + clocks = <&rpmhcc RPMH_LN_BB_CLK2>; | |
| 57 | + clock-names = "refclk"; | |
| 58 | + | |
| 59 | + no-hpd; | |
| 60 | + | |
| 61 | + ports { | |
| 62 | + #address-cells = <1>; | |
| 63 | + #size-cells = <0>; | |
| 64 | + | |
| 65 | + port@0 { | |
| 66 | + reg = <0>; | |
| 67 | + endpoint { | |
| 68 | + remote-endpoint = <&dsi0_out>; | |
| 69 | + }; | |
| 70 | + }; | |
| 71 | + | |
| 72 | + port@1 { | |
| 73 | + reg = <1>; | |
| 74 | + sn65dsi86_out: endpoint { | |
| 75 | + remote-endpoint = <&panel_in_edp>; | |
| 76 | + }; | |
| 77 | + }; | |
| 78 | + }; | |
| 79 | + | |
| 80 | + aux-bus { | |
| 81 | + panel { | |
| 82 | + compatible = "samsung,atna33xc20"; | |
| 83 | + enable-gpios = <&tlmm 12 GPIO_ACTIVE_HIGH>; | |
| 84 | + power-supply = <&pp3300_dx_edp>; | |
| 85 | + hpd-gpios = <&sn65dsi86_bridge 2 GPIO_ACTIVE_HIGH>; | |
| 86 | + | |
| 87 | + port { | |
| 88 | + panel_in_edp: endpoint { | |
| 89 | + remote-endpoint = <&sn65dsi86_out>; | |
| 90 | + }; | |
| 91 | + }; | |
| 92 | + }; | |
| 93 | + }; | |
| 94 | + }; | |
| 95 | + }; | |
| @@ -1,30 +0,0 @@ | ||
| 1 | −# SPDX-License-Identifier: GPL-2.0 | |
| 2 | −%YAML 1.2 | |
| 3 | −--- | |
| 4 | −$id: http://devicetree.org/schemas/display/panel/sharp,ld-d5116z01b.yaml# | |
| 5 | −$schema: http://devicetree.org/meta-schemas/core.yaml# | |
| 6 | − | |
| 7 | −title: Sharp LD-D5116Z01B 12.3" WUXGA+ eDP panel | |
| 8 | − | |
| 9 | −maintainers: | |
| 10 | − - Jeffrey Hugo <jeffrey.l.hugo@gmail.com> | |
| 11 | − | |
| 12 | −allOf: | |
| 13 | − - $ref: panel-common.yaml# | |
| 14 | − | |
| 15 | −properties: | |
| 16 | − compatible: | |
| 17 | − const: sharp,ld-d5116z01b | |
| 18 | − | |
| 19 | − power-supply: true | |
| 20 | − backlight: true | |
| 21 | − port: true | |
| 22 | − no-hpd: true | |
| 23 | − | |
| 24 | −additionalProperties: false | |
| 25 | − | |
| 26 | −required: | |
| 27 | − - compatible | |
| 28 | − - power-supply | |
| 29 | − | |
| 30 | −... | |
| @@ -0,0 +1,60 @@ | ||
| 1 | +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) | |
| 2 | +%YAML 1.2 | |
| 3 | +--- | |
| 4 | +$id: http://devicetree.org/schemas/display/panel/wl-355608-a8.yaml# | |
| 5 | +$schema: http://devicetree.org/meta-schemas/core.yaml# | |
| 6 | + | |
| 7 | +title: WL-355608-A8 3.5" (640x480 pixels) 24-bit IPS LCD panel | |
| 8 | + | |
| 9 | +maintainers: | |
| 10 | + - Ryan Walklin <ryan@testtoast.com> | |
| 11 | + | |
| 12 | +allOf: | |
| 13 | + - $ref: panel-common.yaml# | |
| 14 | + - $ref: /schemas/spi/spi-peripheral-props.yaml# | |
| 15 | + | |
| 16 | +properties: | |
| 17 | + compatible: | |
| 18 | + const: wl-355608-a8 | |
| 19 | + | |
| 20 | + reg: | |
| 21 | + maxItems: 1 | |
| 22 | + | |
| 23 | + spi-3wire: true | |
| 24 | + | |
| 25 | +required: | |
| 26 | + - compatible | |
| 27 | + - reg | |
| 28 | + - port | |
| 29 | + - power-supply | |
| 30 | + - reset-gpios | |
| 31 | + | |
| 32 | +unevaluatedProperties: false | |
| 33 | + | |
| 34 | +examples: | |
| 35 | + - | | |
| 36 | + #include <dt-bindings/gpio/gpio.h> | |
| 37 | + | |
| 38 | + spi { | |
| 39 | + #address-cells = <1>; | |
| 40 | + #size-cells = <0>; | |
| 41 | + | |
| 42 | + panel@0 { | |
| 43 | + compatible = "wl-355608-a8"; | |
| 44 | + reg = <0>; | |
| 45 | + | |
| 46 | + spi-3wire; | |
| 47 | + spi-max-frequency = <3125000>; | |
| 48 | + | |
| 49 | + reset-gpios = <&pio 8 14 GPIO_ACTIVE_LOW>; // PI14 | |
| 50 | + | |
| 51 | + backlight = <&backlight>; | |
| 52 | + power-supply = <®_lcd>; | |
| 53 | + | |
| 54 | + port { | |
| 55 | + endpoint { | |
| 56 | + remote-endpoint = <&tcon_lcd0_out_lcd>; | |
| 57 | + }; | |
| 58 | + }; | |
| 59 | + }; | |
| 60 | + }; | |
| @@ -15,6 +15,7 @@ properties: · 14 unmodified lines | ||
| 15 | 15 | items: |
| 16 | 16 | - enum: |
| 17 | 17 | - rockchip,px30-mipi-dsi |
| 18 | + - rockchip,rk3128-mipi-dsi | |
| 18 | 19 | - rockchip,rk3288-mipi-dsi |
| 19 | 20 | - rockchip,rk3399-mipi-dsi |
| 20 | 21 | - rockchip,rk3568-mipi-dsi |
| @@ -77,6 +78,7 @@ allOf: · 56 unmodified lines | ||
| 77 | 78 | contains: |
| 78 | 79 | enum: |
| 79 | 80 | - rockchip,px30-mipi-dsi |
| 81 | + - rockchip,rk3128-mipi-dsi | |
| 80 | 82 | - rockchip,rk3568-mipi-dsi |
| 81 | 83 | - rockchip,rv1126-mipi-dsi |
| 82 | 84 | |
| @@ -34,6 +34,7 @@ properties: · 33 unmodified lines | ||
| 34 | 34 | - const: arm,mali-valhall-jm # Mali Valhall GPU model/revision is fully discoverable |
| 35 | 35 | - items: |
| 36 | 36 | - enum: |
| 37 | + - mediatek,mt8188-mali | |
| 37 | 38 | - mediatek,mt8192-mali |
| 38 | 39 | - const: arm,mali-valhall-jm # Mali Valhall GPU model/revision is fully discoverable |
| 39 | 40 | |
| @@ -195,7 +196,9 @@ allOf: · 155 unmodified lines | ||
| 195 | 196 | properties: |
| 196 | 197 | compatible: |
| 197 | 198 | contains: |
| 198 | − const: mediatek,mt8183b-mali | |
| 199 | + enum: | |
| 200 | + - mediatek,mt8183b-mali | |
| 201 | + - mediatek,mt8188-mali | |
| 199 | 202 | then: |
| 200 | 203 | properties: |
| 201 | 204 | power-domains: |
| @@ -820,6 +820,8 @@ patternProperties: · 819 unmodified lines | ||
| 820 | 820 | description: Lichee Pi |
| 821 | 821 | "^linaro,.*": |
| 822 | 822 | description: Linaro Limited |
| 823 | + "^lincolntech,.*": | |
| 824 | + description: Lincoln Technology Solutions | |
| 823 | 825 | "^lineartechnology,.*": |
| 824 | 826 | description: Linear Technology |
| 825 | 827 | "^linksprite,.*": |
| @@ -924,6 +926,8 @@ patternProperties: · 98 unmodified lines | ||
| 924 | 926 | description: Microsoft Corporation |
| 925 | 927 | "^microsys,.*": |
| 926 | 928 | description: MicroSys Electronics GmbH |
| 929 | + "^microtips,.*": | |
| 930 | + description: Microtips Technology USA | |
| 927 | 931 | "^mikroe,.*": |
| 928 | 932 | description: MikroElektronika d.o.o. |
| 929 | 933 | "^mikrotik,.*": |
| @@ -1160,6 +1164,8 @@ patternProperties: · 230 unmodified lines | ||
| 1160 | 1164 | description: PowerVR (deprecated, use img) |
| 1161 | 1165 | "^powkiddy,.*": |
| 1162 | 1166 | description: Powkiddy |
| 1167 | + "^primeview,.*": | |
| 1168 | + description: Prime View International (PVI) | |
| 1163 | 1169 | "^primux,.*": |
| 1164 | 1170 | description: Primux Trading, S.L. |
| 1165 | 1171 | "^probox2,.*": |
| @@ -57,8 +57,8 @@ is larger than the driver minor, the DRM_IOCTL_SET_VERSION call will · 56 unmodified lines | ||
| 57 | 57 | return an error. Otherwise the driver's set_version() method will be |
| 58 | 58 | called with the requested version. |
| 59 | 59 | |
| 60 | −Name, Description and Date | |
| 61 | −~~~~~~~~~~~~~~~~~~~~~~~~~~ | |
| 60 | +Name and Description | |
| 61 | +~~~~~~~~~~~~~~~~~~~~ | |
| 62 | 62 | |
| 63 | 63 | char \*name; char \*desc; char \*date; |
| 64 | 64 | The driver name is printed to the kernel log at initialization time, |
| @@ -69,12 +69,6 @@ The driver description is a purely informative string passed to · 4 unmodified lines | ||
| 69 | 69 | userspace through the DRM_IOCTL_VERSION ioctl and otherwise unused by |
| 70 | 70 | the kernel. |
| 71 | 71 | |
| 72 | −The driver date, formatted as YYYYMMDD, is meant to identify the date of | |
| 73 | −the latest modification to the driver. However, as most drivers fail to | |
| 74 | −update it, its value is mostly useless. The DRM core prints it to the | |
| 75 | −kernel log at initialization time and passes it to userspace through the | |
| 76 | −DRM_IOCTL_VERSION ioctl. | |
| 77 | − | |
| 78 | 72 | Module Initialization |
| 79 | 73 | --------------------- |
| 80 | 74 | |
| @@ -110,15 +110,21 @@ fbdev Helper Functions Reference · 109 unmodified lines | ||
| 110 | 110 | .. kernel-doc:: drivers/gpu/drm/drm_fb_helper.c |
| 111 | 111 | :doc: fbdev helpers |
| 112 | 112 | |
| 113 | +.. kernel-doc:: drivers/gpu/drm/drm_fbdev_dma.c | |
| 114 | + :export: | |
| 115 | + | |
| 116 | +.. kernel-doc:: drivers/gpu/drm/drm_fbdev_shmem.c | |
| 117 | + :export: | |
| 118 | + | |
| 119 | +.. kernel-doc:: drivers/gpu/drm/drm_fbdev_ttm.c | |
| 120 | + :export: | |
| 121 | + | |
| 113 | 122 | .. kernel-doc:: include/drm/drm_fb_helper.h |
| 114 | 123 | :internal: |
| 115 | 124 | |
| 116 | 125 | .. kernel-doc:: drivers/gpu/drm/drm_fb_helper.c |
| 117 | 126 | :export: |
| 118 | 127 | |
| 119 | −.. kernel-doc:: drivers/gpu/drm/drm_fbdev_generic.c | |
| 120 | − :export: | |
| 121 | − | |
| 122 | 128 | format Helper Functions Reference |
| 123 | 129 | ================================= |
| 124 | 130 | |
| @@ -150,7 +150,7 @@ High Definition Audio · 149 unmodified lines | ||
| 150 | 150 | .. kernel-doc:: drivers/gpu/drm/i915/display/intel_audio.c |
| 151 | 151 | :internal: |
| 152 | 152 | |
| 153 | −.. kernel-doc:: include/drm/i915_component.h | |
| 153 | +.. kernel-doc:: include/drm/intel/i915_component.h | |
| 154 | 154 | :internal: |
| 155 | 155 | |
| 156 | 156 | Intel HDMI LPE Audio Support |
| @@ -210,9 +210,6 @@ DMC wakelock support · 53 unmodified lines | ||
| 210 | 210 | .. kernel-doc:: drivers/gpu/drm/i915/display/intel_dmc_wl.c |
| 211 | 211 | :doc: DMC wakelock support |
| 212 | 212 | |
| 213 | −.. kernel-doc:: drivers/gpu/drm/i915/display/intel_dmc_wl.c | |
| 214 | − :internal: | |
| 215 | − | |
| 216 | 213 | Video BIOS Table (VBT) |
| 217 | 214 | ---------------------- |
| 218 | 215 | |
| @@ -17,7 +17,6 @@ Owner Module/Drivers,Group,Property Name,Type,Property Values,Object attached,De · 16 unmodified lines | ||
| 17 | 17 | ,Virtual GPU,“suggested X”,RANGE,"Min=0, Max=0xffffffff",Connector,property to suggest an X offset for a connector |
| 18 | 18 | ,,“suggested Y”,RANGE,"Min=0, Max=0xffffffff",Connector,property to suggest an Y offset for a connector |
| 19 | 19 | ,Optional,"""aspect ratio""",ENUM,"{ ""None"", ""4:3"", ""16:9"" }",Connector,TDB |
| 20 | −i915,Generic,"""Broadcast RGB""",ENUM,"{ ""Automatic"", ""Full"", ""Limited 16:235"" }",Connector,"When this property is set to Limited 16:235 and CTM is set, the hardware will be programmed with the result of the multiplication of CTM by the limited range matrix to ensure the pixels normally in the range 0..1.0 are remapped to the range 16/255..235/255." | |
| 21 | 20 | ,,“audio”,ENUM,"{ ""force-dvi"", ""off"", ""auto"", ""on"" }",Connector,TBD |
| 22 | 21 | ,SDVO-TV,“mode”,ENUM,"{ ""NTSC_M"", ""NTSC_J"", ""NTSC_443"", ""PAL_B"" } etc.",Connector,TBD |
| 23 | 22 | ,,"""left_margin""",RANGE,"Min=0, Max= SDVO dependent",Connector,TBD |
| @@ -38,7 +37,6 @@ i915,Generic,"""Broadcast RGB""",ENUM,"{ ""Automatic"", ""Full"", ""Limited 16:2 · 14 unmodified lines | ||
| 38 | 37 | ,,“dot_crawl”,RANGE,"Min=0, Max=1",Connector,TBD |
| 39 | 38 | ,SDVO-TV/LVDS,“brightness”,RANGE,"Min=0, Max= SDVO dependent",Connector,TBD |
| 40 | 39 | CDV gma-500,Generic,"""Broadcast RGB""",ENUM,"{ “Full”, “Limited 16:235” }",Connector,TBD |
| 41 | −,,"""Broadcast RGB""",ENUM,"{ “off”, “auto”, “on” }",Connector,TBD | |
| 42 | 40 | Poulsbo,Generic,“backlight”,RANGE,"Min=0, Max=100",Connector,TBD |
| 43 | 41 | ,SDVO-TV,“mode”,ENUM,"{ ""NTSC_M"", ""NTSC_J"", ""NTSC_443"", ""PAL_B"" } etc.",Connector,TBD |
| 44 | 42 | ,,"""left_margin""",RANGE,"Min=0, Max= SDVO dependent",Connector,TBD |
| @@ -243,19 +243,6 @@ Contact: Maintainer of the driver you plan to convert · 242 unmodified lines | ||
| 243 | 243 | |
| 244 | 244 | Level: Intermediate |
| 245 | 245 | |
| 246 | −Convert drivers to use drm_fbdev_generic_setup() | |
| 247 | −------------------------------------------------ | |
| 248 | − | |
| 249 | −Most drivers can use drm_fbdev_generic_setup(). Driver have to implement | |
| 250 | −atomic modesetting and GEM vmap support. Historically, generic fbdev emulation | |
| 251 | −expected the framebuffer in system memory or system-like memory. By employing | |
| 252 | −struct iosys_map, drivers with frambuffers in I/O memory can be supported | |
| 253 | −as well. | |
| 254 | − | |
| 255 | −Contact: Maintainer of the driver you plan to convert | |
| 256 | − | |
| 257 | −Level: Intermediate | |
| 258 | − | |
| 259 | 246 | Reimplement functions in drm_fbdev_fb_ops without fbdev |
| 260 | 247 | ------------------------------------------------------- |
| 261 | 248 | |
| @@ -482,30 +469,53 @@ Contact: Thomas Zimmermann <tzimmermann@suse.de> · 220 unmodified lines | ||
| 482 | 469 | |
| 483 | 470 | Level: Starter |
| 484 | 471 | |
| 485 | −Clean up checks for already prepared/enabled in panels | |
| 486 | −------------------------------------------------------ | |
| 472 | +Remove disable/unprepare in remove/shutdown in panel-simple and panel-edp | |
| 473 | +------------------------------------------------------------------------- | |
| 474 | + | |
| 475 | +As of commit d2aacaf07395 ("drm/panel: Check for already prepared/enabled in | |
| 476 | +drm_panel"), we have a check in the drm_panel core to make sure nobody | |
| 477 | +double-calls prepare/enable/disable/unprepare. Eventually that should probably | |
| 478 | +be turned into a WARN_ON() or somehow made louder, but right now we actually | |
| 479 | +expect it to trigger and so we don't want it to be too loud. | |
| 480 | + | |
| 481 | +Specifically, that warning will trigger for panel-edp and panel-simple at | |
| 482 | +shutdown time because those panels hardcode a call to drm_panel_disable() | |
| 483 | +and drm_panel_unprepare() at shutdown and remove time that they call regardless | |
| 484 | +of panel state. On systems with a properly coded DRM modeset driver that | |
| 485 | +calls drm_atomic_helper_shutdown() this is pretty much guaranteed to cause | |
| 486 | +the warning to fire. | |
| 487 | + | |
| 488 | +Unfortunately we can't safely remove the calls in panel-edp and panel-simple | |
| 489 | +until we're sure that all DRM modeset drivers that are used with those panels | |
| 490 | +properly call drm_atomic_helper_shutdown(). This TODO item is to validate | |
| 491 | +that all DRM modeset drivers used with panel-edp and panel-simple properly | |
| 492 | +call drm_atomic_helper_shutdown() and then remove the calls to | |
| 493 | +disable/unprepare from those panels. Alternatively, this TODO item could be | |
| 494 | +removed by convincing stakeholders that those calls are fine and downgrading | |
| 495 | +the error message in drm_panel_disable() / drm_panel_unprepare() to a | |
| 496 | +debug-level message. | |
| 487 | 497 | |
| 488 | −In a whole pile of panel drivers, we have code to make the | |
| 489 | −prepare/unprepare/enable/disable callbacks behave as no-ops if they've already | |
| 490 | −been called. To get some idea of the duplicated code, try:: | |
| 498 | +Contact: Douglas Anderson <dianders@chromium.org> | |
| 491 | 499 | |
| 492 | − git grep 'if.*>prepared' -- drivers/gpu/drm/panel | |
| 493 | − git grep 'if.*>enabled' -- drivers/gpu/drm/panel | |
| 500 | +Level: Intermediate | |
| 494 | 501 | |
| 495 | −In the patch ("drm/panel: Check for already prepared/enabled in drm_panel") | |
| 496 | −we've moved this check to the core. Now we can most definitely remove the | |
| 497 | −check from the individual panels and save a pile of code. | |
| 502 | +Transition away from using mipi_dsi_*_write_seq() | |
| 503 | +------------------------------------------------- | |
| 498 | 504 | |
| 499 | −In adition to removing the check from the individual panels, it is believed | |
| 500 | −that even the core shouldn't need this check and that should be considered | |
| 501 | −an error if other code ever relies on this check. The check in the core | |
| 502 | −currently prints a warning whenever something is relying on this check with | |
| 503 | −dev_warn(). After a little while, we likely want to promote this to a | |
| 504 | −WARN(1) to help encourage folks not to rely on this behavior. | |
| 505 | +The macros mipi_dsi_generic_write_seq() and mipi_dsi_dcs_write_seq() are | |
| 506 | +non-intuitive because, if there are errors, they return out of the *caller's* | |
| 507 | +function. We should move all callers to use mipi_dsi_generic_write_seq_multi() | |
| 508 | +and mipi_dsi_dcs_write_seq_multi() macros instead. | |
| 509 | + | |
| 510 | +Once all callers are transitioned, the macros and the functions that they call, | |
| 511 | +mipi_dsi_generic_write_chatty() and mipi_dsi_dcs_write_buffer_chatty(), can | |
| 512 | +probably be removed. Alternatively, if people feel like the _multi() variants | |
| 513 | +are overkill for some use cases, we could keep the mipi_dsi_*_write_seq() | |
| 514 | +variants but change them not to return out of the caller. | |
| 505 | 515 | |
| 506 | 516 | Contact: Douglas Anderson <dianders@chromium.org> |
| 507 | 517 | |
| 508 | −Level: Starter/Intermediate | |
| 518 | +Level: Starter | |
| 509 | 519 | |
| 510 | 520 | |
| 511 | 521 | Core refactorings |
| @@ -6909,7 +6909,7 @@ DRM DRIVER FOR LG SW43408 PANELS · 6908 unmodified lines | ||
| 6909 | 6909 | M: Sumit Semwal <sumit.semwal@linaro.org> |
| 6910 | 6910 | M: Caleb Connolly <caleb.connolly@linaro.org> |
| 6911 | 6911 | S: Maintained |
| 6912 | −T: git git://anongit.freedesktop.org/drm/drm-misc | |
| 6912 | +T: git https://gitlab.freedesktop.org/drm/misc/kernel.git | |
| 6913 | 6913 | F: Documentation/devicetree/bindings/display/panel/lg,sw43408.yaml |
| 6914 | 6914 | F: drivers/gpu/drm/panel/panel-lg-sw43408.c |
| 6915 | 6915 | |
| @@ -7196,6 +7196,7 @@ L: dri-devel@lists.freedesktop.org · 280 unmodified lines | ||
| 7196 | 7196 | S: Maintained |
| 7197 | 7197 | T: git https://gitlab.freedesktop.org/drm/misc/kernel.git |
| 7198 | 7198 | F: Documentation/gpu/vkms.rst |
| 7199 | +F: drivers/gpu/drm/ci/xfails/vkms* | |
| 7199 | 7200 | F: drivers/gpu/drm/vkms/ |
| 7200 | 7201 | |
| 7201 | 7202 | DRM DRIVER FOR VIRTUALBOX VIRTUAL GPU |
| @@ -7566,7 +7567,6 @@ F: include/drm/gpu_scheduler.h · 364 unmodified lines | ||
| 7566 | 7567 | DRM PANEL DRIVERS |
| 7567 | 7568 | M: Neil Armstrong <neil.armstrong@linaro.org> |
| 7568 | 7569 | R: Jessica Zhang <quic_jesszhan@quicinc.com> |
| 7569 | −R: Sam Ravnborg <sam@ravnborg.org> | |
| 7570 | 7570 | L: dri-devel@lists.freedesktop.org |
| 7571 | 7571 | S: Maintained |
| 7572 | 7572 | T: git https://gitlab.freedesktop.org/drm/misc/kernel.git |
| @@ -11012,6 +11012,7 @@ S: Supported · 3439 unmodified lines | ||
| 11012 | 11012 | F: drivers/gpu/drm/i915/display/ |
| 11013 | 11013 | F: drivers/gpu/drm/xe/display/ |
| 11014 | 11014 | F: drivers/gpu/drm/xe/compat-i915-headers |
| 11015 | +F: include/drm/intel/ | |
| 11015 | 11016 | |
| 11016 | 11017 | INTEL DRM I915 DRIVER (Meteor Lake, DG2 and older excluding Poulsbo, Moorestown and derivative) |
| 11017 | 11018 | M: Jani Nikula <jani.nikula@linux.intel.com> |
| @@ -11024,12 +11025,12 @@ W: https://drm.pages.freedesktop.org/intel-docs/ · 6 unmodified lines | ||
| 11024 | 11025 | Q: http://patchwork.freedesktop.org/project/intel-gfx/ |
| 11025 | 11026 | B: https://drm.pages.freedesktop.org/intel-docs/how-to-file-i915-bugs.html |
| 11026 | 11027 | C: irc://irc.oftc.net/intel-gfx |
| 11027 | −T: git git://anongit.freedesktop.org/drm-intel | |
| 11028 | +T: git https://gitlab.freedesktop.org/drm/i915/kernel.git | |
| 11028 | 11029 | F: Documentation/ABI/testing/sysfs-driver-intel-i915-hwmon |
| 11029 | 11030 | F: Documentation/gpu/i915.rst |
| 11030 | 11031 | F: drivers/gpu/drm/ci/xfails/i915* |
| 11031 | 11032 | F: drivers/gpu/drm/i915/ |
| 11032 | −F: include/drm/i915* | |
| 11033 | +F: include/drm/intel/ | |
| 11033 | 11034 | F: include/uapi/drm/i915_drm.h |
| 11034 | 11035 | |
| 11035 | 11036 | INTEL DRM XE DRIVER (Lunar Lake and newer) |
| @@ -11045,7 +11046,7 @@ T: git https://gitlab.freedesktop.org/drm/xe/kernel.git · 9 unmodified lines | ||
| 11045 | 11046 | F: Documentation/ABI/testing/sysfs-driver-intel-xe-hwmon |
| 11046 | 11047 | F: Documentation/gpu/xe/ |
| 11047 | 11048 | F: drivers/gpu/drm/xe/ |
| 11048 | −F: include/drm/xe* | |
| 11049 | +F: include/drm/intel/ | |
| 11049 | 11050 | F: include/uapi/drm/xe_drm.h |
| 11050 | 11051 | |
| 11051 | 11052 | INTEL ETHERNET DRIVERS |
| @@ -17,8 +17,8 @@ · 16 unmodified lines | ||
| 17 | 17 | #include <linux/bcma/bcma.h> |
| 18 | 18 | #include <linux/bcma/bcma_regs.h> |
| 19 | 19 | #include <linux/platform_data/x86/apple.h> |
| 20 | −#include <drm/i915_drm.h> | |
| 21 | −#include <drm/i915_pciids.h> | |
| 20 | +#include <drm/intel/i915_drm.h> | |
| 21 | +#include <drm/intel/i915_pciids.h> | |
| 22 | 22 | #include <asm/pci-direct.h> |
| 23 | 23 | #include <asm/dma.h> |
| 24 | 24 | #include <asm/io_apic.h> |
| @@ -518,47 +518,46 @@ static const struct intel_early_ops gen11_early_ops __initconst = { · 493 unmodified lines | ||
| 518 | 518 | |
| 519 | 519 | /* Intel integrated GPUs for which we need to reserve "stolen memory" */ |
| 520 | 520 | static const struct pci_device_id intel_early_ids[] __initconst = { |
| 521 | − INTEL_I830_IDS(&i830_early_ops), | |
| 522 | − INTEL_I845G_IDS(&i845_early_ops), | |
| 523 | − INTEL_I85X_IDS(&i85x_early_ops), | |
| 524 | − INTEL_I865G_IDS(&i865_early_ops), | |
| 525 | − INTEL_I915G_IDS(&gen3_early_ops), | |
| 526 | − INTEL_I915GM_IDS(&gen3_early_ops), | |
| 527 | − INTEL_I945G_IDS(&gen3_early_ops), | |
| 528 | − INTEL_I945GM_IDS(&gen3_early_ops), | |
| 529 | − INTEL_VLV_IDS(&gen6_early_ops), | |
| 530 | − INTEL_PINEVIEW_G_IDS(&gen3_early_ops), | |
| 531 | − INTEL_PINEVIEW_M_IDS(&gen3_early_ops), | |
| 532 | − INTEL_I965G_IDS(&gen3_early_ops), | |
| 533 | − INTEL_G33_IDS(&gen3_early_ops), | |
| 534 | − INTEL_I965GM_IDS(&gen3_early_ops), | |
| 535 | − INTEL_GM45_IDS(&gen3_early_ops), | |
| 536 | − INTEL_G45_IDS(&gen3_early_ops), | |
| 537 | − INTEL_IRONLAKE_D_IDS(&gen3_early_ops), | |
| 538 | − INTEL_IRONLAKE_M_IDS(&gen3_early_ops), | |
| 539 | − INTEL_SNB_D_IDS(&gen6_early_ops), | |
| 540 | − INTEL_SNB_M_IDS(&gen6_early_ops), | |
| 541 | − INTEL_IVB_M_IDS(&gen6_early_ops), | |
| 542 | − INTEL_IVB_D_IDS(&gen6_early_ops), | |
| 543 | − INTEL_HSW_IDS(&gen6_early_ops), | |
| 544 | − INTEL_BDW_IDS(&gen8_early_ops), | |
| 545 | − INTEL_CHV_IDS(&chv_early_ops), | |
| 546 | − INTEL_SKL_IDS(&gen9_early_ops), | |
| 547 | − INTEL_BXT_IDS(&gen9_early_ops), | |
| 548 | − INTEL_KBL_IDS(&gen9_early_ops), | |
| 549 | − INTEL_CFL_IDS(&gen9_early_ops), | |
| 550 | − INTEL_GLK_IDS(&gen9_early_ops), | |
| 551 | − INTEL_CNL_IDS(&gen9_early_ops), | |
| 552 | − INTEL_ICL_11_IDS(&gen11_early_ops), | |
| 553 | − INTEL_EHL_IDS(&gen11_early_ops), | |
| 554 | − INTEL_JSL_IDS(&gen11_early_ops), | |
| 555 | − INTEL_TGL_12_IDS(&gen11_early_ops), | |
| 556 | − INTEL_RKL_IDS(&gen11_early_ops), | |
| 557 | − INTEL_ADLS_IDS(&gen11_early_ops), | |
| 558 | − INTEL_ADLP_IDS(&gen11_early_ops), | |
| 559 | − INTEL_ADLN_IDS(&gen11_early_ops), | |
| 560 | − INTEL_RPLS_IDS(&gen11_early_ops), | |
| 561 | − INTEL_RPLP_IDS(&gen11_early_ops), | |
| 521 | + INTEL_I830_IDS(INTEL_VGA_DEVICE, &i830_early_ops), | |
| 522 | + INTEL_I845G_IDS(INTEL_VGA_DEVICE, &i845_early_ops), | |
| 523 | + INTEL_I85X_IDS(INTEL_VGA_DEVICE, &i85x_early_ops), | |
| 524 | + INTEL_I865G_IDS(INTEL_VGA_DEVICE, &i865_early_ops), | |
| 525 | + INTEL_I915G_IDS(INTEL_VGA_DEVICE, &gen3_early_ops), | |
| 526 | + INTEL_I915GM_IDS(INTEL_VGA_DEVICE, &gen3_early_ops), | |
| 527 | + INTEL_I945G_IDS(INTEL_VGA_DEVICE, &gen3_early_ops), | |
| 528 | + INTEL_I945GM_IDS(INTEL_VGA_DEVICE, &gen3_early_ops), | |
| 529 | + INTEL_VLV_IDS(INTEL_VGA_DEVICE, &gen6_early_ops), | |
| 530 | + INTEL_PNV_IDS(INTEL_VGA_DEVICE, &gen3_early_ops), | |
| 531 | + INTEL_I965G_IDS(INTEL_VGA_DEVICE, &gen3_early_ops), | |
| 532 | + INTEL_G33_IDS(INTEL_VGA_DEVICE, &gen3_early_ops), | |
| 533 | + INTEL_I965GM_IDS(INTEL_VGA_DEVICE, &gen3_early_ops), | |
| 534 | + INTEL_GM45_IDS(INTEL_VGA_DEVICE, &gen3_early_ops), | |
| 535 | + INTEL_G45_IDS(INTEL_VGA_DEVICE, &gen3_early_ops), | |
| 536 | + INTEL_ILK_IDS(INTEL_VGA_DEVICE, &gen3_early_ops), | |
| 537 | + INTEL_SNB_IDS(INTEL_VGA_DEVICE, &gen6_early_ops), | |
| 538 | + INTEL_IVB_IDS(INTEL_VGA_DEVICE, &gen6_early_ops), | |
| 539 | + INTEL_HSW_IDS(INTEL_VGA_DEVICE, &gen6_early_ops), | |
| 540 | + INTEL_BDW_IDS(INTEL_VGA_DEVICE, &gen8_early_ops), | |
| 541 | + INTEL_CHV_IDS(INTEL_VGA_DEVICE, &chv_early_ops), | |
| 542 | + INTEL_SKL_IDS(INTEL_VGA_DEVICE, &gen9_early_ops), | |
| 543 | + INTEL_BXT_IDS(INTEL_VGA_DEVICE, &gen9_early_ops), | |
| 544 | + INTEL_KBL_IDS(INTEL_VGA_DEVICE, &gen9_early_ops), | |
| 545 | + INTEL_CFL_IDS(INTEL_VGA_DEVICE, &gen9_early_ops), | |
| 546 | + INTEL_WHL_IDS(INTEL_VGA_DEVICE, &gen9_early_ops), | |
| 547 | + INTEL_CML_IDS(INTEL_VGA_DEVICE, &gen9_early_ops), | |
| 548 | + INTEL_GLK_IDS(INTEL_VGA_DEVICE, &gen9_early_ops), | |
| 549 | + INTEL_CNL_IDS(INTEL_VGA_DEVICE, &gen9_early_ops), | |
| 550 | + INTEL_ICL_IDS(INTEL_VGA_DEVICE, &gen11_early_ops), | |
| 551 | + INTEL_EHL_IDS(INTEL_VGA_DEVICE, &gen11_early_ops), | |
| 552 | + INTEL_JSL_IDS(INTEL_VGA_DEVICE, &gen11_early_ops), | |
| 553 | + INTEL_TGL_IDS(INTEL_VGA_DEVICE, &gen11_early_ops), | |
| 554 | + INTEL_RKL_IDS(INTEL_VGA_DEVICE, &gen11_early_ops), | |
| 555 | + INTEL_ADLS_IDS(INTEL_VGA_DEVICE, &gen11_early_ops), | |
| 556 | + INTEL_ADLP_IDS(INTEL_VGA_DEVICE, &gen11_early_ops), | |
| 557 | + INTEL_ADLN_IDS(INTEL_VGA_DEVICE, &gen11_early_ops), | |
| 558 | + INTEL_RPLS_IDS(INTEL_VGA_DEVICE, &gen11_early_ops), | |
| 559 | + INTEL_RPLU_IDS(INTEL_VGA_DEVICE, &gen11_early_ops), | |
| 560 | + INTEL_RPLP_IDS(INTEL_VGA_DEVICE, &gen11_early_ops), | |
| 562 | 561 | }; |
| 563 | 562 | |
| 564 | 563 | struct resource intel_graphics_stolen_res __ro_after_init = DEFINE_RES_MEM(0, 0); |
| @@ -1,19 +1,22 @@ | ||
| 1 | 1 | # SPDX-License-Identifier: GPL-2.0-only |
| 2 | −# Copyright (C) 2023 Intel Corporation | |
| 2 | +# Copyright (C) 2023-2024 Intel Corporation | |
| 3 | 3 | |
| 4 | 4 | intel_vpu-y := \ |
| 5 | 5 | ivpu_drv.o \ |
| 6 | 6 | ivpu_fw.o \ |
| 7 | 7 | ivpu_fw_log.o \ |
| 8 | 8 | ivpu_gem.o \ |
| 9 | − ivpu_hw_37xx.o \ | |
| 10 | − ivpu_hw_40xx.o \ | |
| 9 | + ivpu_hw.o \ | |
| 10 | + ivpu_hw_btrs.o \ | |
| 11 | + ivpu_hw_ip.o \ | |
| 11 | 12 | ivpu_ipc.o \ |
| 12 | 13 | ivpu_job.o \ |
| 13 | 14 | ivpu_jsm_msg.o \ |
| 14 | 15 | ivpu_mmu.o \ |
| 15 | 16 | ivpu_mmu_context.o \ |
| 16 | − ivpu_pm.o | |
| 17 | + ivpu_ms.o \ | |
| 18 | + ivpu_pm.o \ | |
| 19 | + ivpu_sysfs.o | |
| 17 | 20 | |
| 18 | 21 | intel_vpu-$(CONFIG_DEBUG_FS) += ivpu_debugfs.o |
| 19 | 22 | |
| @@ -1,6 +1,6 @@ | ||
| 1 | 1 | // SPDX-License-Identifier: GPL-2.0-only |
| 2 | 2 | /* |
| 3 | − * Copyright (C) 2020-2023 Intel Corporation | |
| 3 | + * Copyright (C) 2020-2024 Intel Corporation | |
| 4 | 4 | */ |
| 5 | 5 | |
| 6 | 6 | #include <linux/debugfs.h> |
| @@ -145,6 +145,30 @@ static const struct file_operations dvfs_mode_fops = { · 138 unmodified lines | ||
| 145 | 145 | .write = dvfs_mode_fops_write, |
| 146 | 146 | }; |
| 147 | 147 | |
| 148 | +static ssize_t | |
| 149 | +fw_dyndbg_fops_write(struct file *file, const char __user *user_buf, size_t size, loff_t *pos) | |
| 150 | +{ | |
| 151 | + struct ivpu_device *vdev = file->private_data; | |
| 152 | + char buffer[VPU_DYNDBG_CMD_MAX_LEN] = {}; | |
| 153 | + int ret; | |
| 154 | + | |
| 155 | + if (size >= VPU_DYNDBG_CMD_MAX_LEN) | |
| 156 | + return -EINVAL; | |
| 157 | + | |
| 158 | + ret = strncpy_from_user(buffer, user_buf, size); | |
| 159 | + if (ret < 0) | |
| 160 | + return ret; | |
| 161 | + | |
| 162 | + ivpu_jsm_dyndbg_control(vdev, buffer, size); | |
| 163 | + return size; | |
| 164 | +} | |
| 165 | + | |
| 166 | +static const struct file_operations fw_dyndbg_fops = { | |
| 167 | + .owner = THIS_MODULE, | |
| 168 | + .open = simple_open, | |
| 169 | + .write = fw_dyndbg_fops_write, | |
| 170 | +}; | |
| 171 | + | |
| 148 | 172 | static int fw_log_show(struct seq_file *s, void *v) |
| 149 | 173 | { |
| 150 | 174 | struct ivpu_device *vdev = s->private; |
| @@ -335,6 +359,61 @@ static const struct file_operations ivpu_reset_engine_fops = { · 184 unmodified lines | ||
| 335 | 359 | .write = ivpu_reset_engine_fn, |
| 336 | 360 | }; |
| 337 | 361 | |
| 362 | +static ssize_t | |
| 363 | +ivpu_resume_engine_fn(struct file *file, const char __user *user_buf, size_t size, loff_t *pos) | |
| 364 | +{ | |
| 365 | + struct ivpu_device *vdev = file->private_data; | |
| 366 | + | |
| 367 | + if (!size) | |
| 368 | + return -EINVAL; | |
| 369 | + | |
| 370 | + if (ivpu_jsm_hws_resume_engine(vdev, DRM_IVPU_ENGINE_COMPUTE)) | |
| 371 | + return -ENODEV; | |
| 372 | + if (ivpu_jsm_hws_resume_engine(vdev, DRM_IVPU_ENGINE_COPY)) | |
| 373 | + return -ENODEV; | |
| 374 | + | |
| 375 | + return size; | |
| 376 | +} | |
| 377 | + | |
| 378 | +static const struct file_operations ivpu_resume_engine_fops = { | |
| 379 | + .owner = THIS_MODULE, | |
| 380 | + .open = simple_open, | |
| 381 | + .write = ivpu_resume_engine_fn, | |
| 382 | +}; | |
| 383 | + | |
| 384 | +static int dct_active_get(void *data, u64 *active_percent) | |
| 385 | +{ | |
| 386 | + struct ivpu_device *vdev = data; | |
| 387 | + | |
| 388 | + *active_percent = vdev->pm->dct_active_percent; | |
| 389 | + | |
| 390 | + return 0; | |
| 391 | +} | |
| 392 | + | |
| 393 | +static int dct_active_set(void *data, u64 active_percent) | |
| 394 | +{ | |
| 395 | + struct ivpu_device *vdev = data; | |
| 396 | + int ret; | |
| 397 | + | |
| 398 | + if (active_percent > 100) | |
| 399 | + return -EINVAL; | |
| 400 | + | |
| 401 | + ret = ivpu_rpm_get(vdev); | |
| 402 | + if (ret) | |
| 403 | + return ret; | |
| 404 | + | |
| 405 | + if (active_percent) | |
| 406 | + ret = ivpu_pm_dct_enable(vdev, active_percent); | |
| 407 | + else | |
| 408 | + ret = ivpu_pm_dct_disable(vdev); | |
| 409 | + | |
| 410 | + ivpu_rpm_put(vdev); | |
| 411 | + | |
| 412 | + return ret; | |
| 413 | +} | |
| 414 | + | |
| 415 | +DEFINE_DEBUGFS_ATTRIBUTE(ivpu_dct_fops, dct_active_get, dct_active_set, "%llu\n"); | |
| 416 | + | |
| 338 | 417 | void ivpu_debugfs_init(struct ivpu_device *vdev) |
| 339 | 418 | { |
| 340 | 419 | struct dentry *debugfs_root = vdev->drm.debugfs_root; |
| @@ -347,6 +426,8 @@ void ivpu_debugfs_init(struct ivpu_device *vdev) · 6 unmodified lines | ||
| 347 | 426 | debugfs_create_file("dvfs_mode", 0200, debugfs_root, vdev, |
| 348 | 427 | &dvfs_mode_fops); |
| 349 | 428 | |
| 429 | + debugfs_create_file("fw_dyndbg", 0200, debugfs_root, vdev, | |
| 430 | + &fw_dyndbg_fops); | |
| 350 | 431 | debugfs_create_file("fw_log", 0644, debugfs_root, vdev, |
| 351 | 432 | &fw_log_fops); |
| 352 | 433 | debugfs_create_file("fw_trace_destination_mask", 0200, debugfs_root, vdev, |
| @@ -358,8 +439,12 @@ void ivpu_debugfs_init(struct ivpu_device *vdev) · 5 unmodified lines | ||
| 358 | 439 | |
| 359 | 440 | debugfs_create_file("reset_engine", 0200, debugfs_root, vdev, |
| 360 | 441 | &ivpu_reset_engine_fops); |
| 442 | + debugfs_create_file("resume_engine", 0200, debugfs_root, vdev, | |
| 443 | + &ivpu_resume_engine_fops); | |
| 361 | 444 | |
| 362 | − if (ivpu_hw_gen(vdev) >= IVPU_HW_40XX) | |
| 445 | + if (ivpu_hw_ip_gen(vdev) >= IVPU_HW_IP_40XX) { | |
| 363 | 446 | debugfs_create_file("fw_profiling_freq_drive", 0200, |
| 364 | 447 | debugfs_root, vdev, &fw_profiling_freq_fops); |
| 448 | + debugfs_create_file("dct", 0644, debugfs_root, vdev, &ivpu_dct_fops); | |
| 449 | + } | |
| 365 | 450 | } |
| @@ -26,7 +26,9 @@ · 25 unmodified lines | ||
| 26 | 26 | #include "ivpu_jsm_msg.h" |
| 27 | 27 | #include "ivpu_mmu.h" |
| 28 | 28 | #include "ivpu_mmu_context.h" |
| 29 | +#include "ivpu_ms.h" | |
| 29 | 30 | #include "ivpu_pm.h" |
| 31 | +#include "ivpu_sysfs.h" | |
| 30 | 32 | |
| 31 | 33 | #ifndef DRIVER_VERSION_STR |
| 32 | 34 | #define DRIVER_VERSION_STR __stringify(DRM_IVPU_DRIVER_MAJOR) "." \ |
| @@ -51,10 +53,18 @@ u8 ivpu_pll_max_ratio = U8_MAX; · 18 unmodified lines | ||
| 51 | 53 | module_param_named(pll_max_ratio, ivpu_pll_max_ratio, byte, 0644); |
| 52 | 54 | MODULE_PARM_DESC(pll_max_ratio, "Maximum PLL ratio used to set NPU frequency"); |
| 53 | 55 | |
| 56 | +int ivpu_sched_mode; | |
| 57 | +module_param_named(sched_mode, ivpu_sched_mode, int, 0444); | |
| 58 | +MODULE_PARM_DESC(sched_mode, "Scheduler mode: 0 - Default scheduler, 1 - Force HW scheduler"); | |
| 59 | + | |
| 54 | 60 | bool ivpu_disable_mmu_cont_pages; |
| 55 | −module_param_named(disable_mmu_cont_pages, ivpu_disable_mmu_cont_pages, bool, 0644); | |
| 61 | +module_param_named(disable_mmu_cont_pages, ivpu_disable_mmu_cont_pages, bool, 0444); | |
| 56 | 62 | MODULE_PARM_DESC(disable_mmu_cont_pages, "Disable MMU contiguous pages optimization"); |
| 57 | 63 | |
| 64 | +bool ivpu_force_snoop; | |
| 65 | +module_param_named(force_snoop, ivpu_force_snoop, bool, 0444); | |
| 66 | +MODULE_PARM_DESC(force_snoop, "Force snooping for NPU host memory access"); | |
| 67 | + | |
| 58 | 68 | struct ivpu_file_priv *ivpu_file_priv_get(struct ivpu_file_priv *file_priv) |
| 59 | 69 | { |
| 60 | 70 | struct ivpu_device *vdev = file_priv->vdev; |
| @@ -74,7 +84,6 @@ static void file_priv_unbind(struct ivpu_device *vdev, struct ivpu_file_priv *fi · 13 unmodified lines | ||
| 74 | 84 | ivpu_dbg(vdev, FILE, "file_priv unbind: ctx %u\n", file_priv->ctx.id); |
| 75 | 85 | |
| 76 | 86 | ivpu_cmdq_release_all_locked(file_priv); |
| 77 | − ivpu_jsm_context_release(vdev, file_priv->ctx.id); | |
| 78 | 87 | ivpu_bo_unbind_all_bos_from_context(vdev, &file_priv->ctx); |
| 79 | 88 | ivpu_mmu_user_context_fini(vdev, &file_priv->ctx); |
| 80 | 89 | file_priv->bound = false; |
| @@ -97,6 +106,7 @@ static void file_priv_release(struct kref *ref) · 16 unmodified lines | ||
| 97 | 106 | mutex_unlock(&vdev->context_list_lock); |
| 98 | 107 | pm_runtime_put_autosuspend(vdev->drm.dev); |
| 99 | 108 | |
| 109 | + mutex_destroy(&file_priv->ms_lock); | |
| 100 | 110 | mutex_destroy(&file_priv->lock); |
| 101 | 111 | kfree(file_priv); |
| 102 | 112 | } |
| @@ -119,7 +129,7 @@ static int ivpu_get_capabilities(struct ivpu_device *vdev, struct drm_ivpu_param · 16 unmodified lines | ||
| 119 | 129 | { |
| 120 | 130 | switch (args->index) { |
| 121 | 131 | case DRM_IVPU_CAP_METRIC_STREAMER: |
| 122 | − args->value = 0; | |
| 132 | + args->value = 1; | |
| 123 | 133 | break; |
| 124 | 134 | case DRM_IVPU_CAP_DMA_MEMORY_RANGE: |
| 125 | 135 | args->value = 1; |
| @@ -228,10 +238,13 @@ static int ivpu_open(struct drm_device *dev, struct drm_file *file) · 102 unmodified lines | ||
| 228 | 238 | goto err_dev_exit; |
| 229 | 239 | } |
| 230 | 240 | |
| 241 | + INIT_LIST_HEAD(&file_priv->ms_instance_list); | |
| 242 | + | |
| 231 | 243 | file_priv->vdev = vdev; |
| 232 | 244 | file_priv->bound = true; |
| 233 | 245 | kref_init(&file_priv->ref); |
| 234 | 246 | mutex_init(&file_priv->lock); |
| 247 | + mutex_init(&file_priv->ms_lock); | |
| 235 | 248 | |
| 236 | 249 | mutex_lock(&vdev->context_list_lock); |
| 237 | 250 | |
| @@ -260,6 +273,7 @@ err_xa_erase: · 22 unmodified lines | ||
| 260 | 273 | xa_erase_irq(&vdev->context_xa, ctx_id); |
| 261 | 274 | err_unlock: |
| 262 | 275 | mutex_unlock(&vdev->context_list_lock); |
| 276 | + mutex_destroy(&file_priv->ms_lock); | |
| 263 | 277 | mutex_destroy(&file_priv->lock); |
| 264 | 278 | kfree(file_priv); |
| 265 | 279 | err_dev_exit: |
| @@ -275,6 +289,7 @@ static void ivpu_postclose(struct drm_device *dev, struct drm_file *file) · 9 unmodified lines | ||
| 275 | 289 | ivpu_dbg(vdev, FILE, "file_priv close: ctx %u process %s pid %d\n", |
| 276 | 290 | file_priv->ctx.id, current->comm, task_pid_nr(current)); |
| 277 | 291 | |
| 292 | + ivpu_ms_cleanup(file_priv); | |
| 278 | 293 | ivpu_file_priv_put(&file_priv); |
| 279 | 294 | } |
| 280 | 295 | |
| @@ -285,6 +300,10 @@ static const struct drm_ioctl_desc ivpu_drm_ioctls[] = { · 4 unmodified lines | ||
| 285 | 300 | DRM_IOCTL_DEF_DRV(IVPU_BO_INFO, ivpu_bo_info_ioctl, 0), |
| 286 | 301 | DRM_IOCTL_DEF_DRV(IVPU_SUBMIT, ivpu_submit_ioctl, 0), |
| 287 | 302 | DRM_IOCTL_DEF_DRV(IVPU_BO_WAIT, ivpu_bo_wait_ioctl, 0), |
| 303 | + DRM_IOCTL_DEF_DRV(IVPU_METRIC_STREAMER_START, ivpu_ms_start_ioctl, 0), | |
| 304 | + DRM_IOCTL_DEF_DRV(IVPU_METRIC_STREAMER_GET_DATA, ivpu_ms_get_data_ioctl, 0), | |
| 305 | + DRM_IOCTL_DEF_DRV(IVPU_METRIC_STREAMER_STOP, ivpu_ms_stop_ioctl, 0), | |
| 306 | + DRM_IOCTL_DEF_DRV(IVPU_METRIC_STREAMER_GET_INFO, ivpu_ms_get_info_ioctl, 0), | |
| 288 | 307 | }; |
| 289 | 308 | |
| 290 | 309 | static int ivpu_wait_for_ready(struct ivpu_device *vdev) |
| @@ -301,7 +320,7 @@ static int ivpu_wait_for_ready(struct ivpu_device *vdev) · 10 unmodified lines | ||
| 301 | 320 | |
| 302 | 321 | timeout = jiffies + msecs_to_jiffies(vdev->timeout.boot); |
| 303 | 322 | while (1) { |
| 304 | − ivpu_ipc_irq_handler(vdev, NULL); | |
| 323 | + ivpu_ipc_irq_handler(vdev); | |
| 305 | 324 | ret = ivpu_ipc_receive(vdev, &cons, &ipc_hdr, NULL, 0); |
| 306 | 325 | if (ret != -ETIMEDOUT || time_after_eq(jiffies, timeout)) |
| 307 | 326 | break; |
| @@ -323,6 +342,21 @@ static int ivpu_wait_for_ready(struct ivpu_device *vdev) · 15 unmodified lines | ||
| 323 | 342 | return ret; |
| 324 | 343 | } |
| 325 | 344 | |
| 345 | +static int ivpu_hw_sched_init(struct ivpu_device *vdev) | |
| 346 | +{ | |
| 347 | + int ret = 0; | |
| 348 | + | |
| 349 | + if (vdev->hw->sched_mode == VPU_SCHEDULING_MODE_HW) { | |
| 350 | + ret = ivpu_jsm_hws_setup_priority_bands(vdev); | |
| 351 | + if (ret) { | |
| 352 | + ivpu_err(vdev, "Failed to enable hw scheduler: %d", ret); | |
| 353 | + return ret; | |
| 354 | + } | |
| 355 | + } | |
| 356 | + | |
| 357 | + return ret; | |
| 358 | +} | |
| 359 | + | |
| 326 | 360 | /** |
| 327 | 361 | * ivpu_boot() - Start VPU firmware |
| 328 | 362 | * @vdev: VPU device |
| @@ -356,6 +390,15 @@ int ivpu_boot(struct ivpu_device *vdev) · 27 unmodified lines | ||
| 356 | 390 | enable_irq(vdev->irq); |
| 357 | 391 | ivpu_hw_irq_enable(vdev); |
| 358 | 392 | ivpu_ipc_enable(vdev); |
| 393 | + | |
| 394 | + if (ivpu_fw_is_cold_boot(vdev)) { | |
| 395 | + ret = ivpu_pm_dct_init(vdev); | |
| 396 | + if (ret) | |
| 397 | + return ret; | |
| 398 | + | |
| 399 | + return ivpu_hw_sched_init(vdev); | |
| 400 | + } | |
| 401 | + | |
| 359 | 402 | return 0; |
| 360 | 403 | } |
| 361 | 404 | |
| @@ -408,11 +451,52 @@ static const struct drm_driver driver = { · 46 unmodified lines | ||
| 408 | 451 | .minor = DRM_IVPU_DRIVER_MINOR, |
| 409 | 452 | }; |
| 410 | 453 | |
| 454 | +static void ivpu_context_abort_invalid(struct ivpu_device *vdev) | |
| 455 | +{ | |
| 456 | + struct ivpu_file_priv *file_priv; | |
| 457 | + unsigned long ctx_id; | |
| 458 | + | |
| 459 | + mutex_lock(&vdev->context_list_lock); | |
| 460 | + | |
| 461 | + xa_for_each(&vdev->context_xa, ctx_id, file_priv) { | |
| 462 | + if (!file_priv->has_mmu_faults || file_priv->aborted) | |
| 463 | + continue; | |
| 464 | + | |
| 465 | + mutex_lock(&file_priv->lock); | |
| 466 | + ivpu_context_abort_locked(file_priv); | |
| 467 | + file_priv->aborted = true; | |
| 468 | + mutex_unlock(&file_priv->lock); | |
| 469 | + } | |
| 470 | + | |
| 471 | + mutex_unlock(&vdev->context_list_lock); | |
| 472 | +} | |
| 473 | + | |
| 411 | 474 | static irqreturn_t ivpu_irq_thread_handler(int irq, void *arg) |
| 412 | 475 | { |
| 413 | 476 | struct ivpu_device *vdev = arg; |
| 477 | + u8 irq_src; | |
| 478 | + | |
| 479 | + if (kfifo_is_empty(&vdev->hw->irq.fifo)) | |
| 480 | + return IRQ_NONE; | |
| 414 | 481 | |
| 415 | − return ivpu_ipc_irq_thread_handler(vdev); | |
| 482 | + while (kfifo_get(&vdev->hw->irq.fifo, &irq_src)) { | |
| 483 | + switch (irq_src) { | |
| 484 | + case IVPU_HW_IRQ_SRC_IPC: | |
| 485 | + ivpu_ipc_irq_thread_handler(vdev); | |
| 486 | + break; | |
| 487 | + case IVPU_HW_IRQ_SRC_MMU_EVTQ: | |
| 488 | + ivpu_context_abort_invalid(vdev); | |
| 489 | + break; | |
| 490 | + case IVPU_HW_IRQ_SRC_DCT: | |
| 491 | + ivpu_pm_dct_irq_thread_handler(vdev); | |
| 492 | + break; | |
| 493 | + default: | |
| 494 | + ivpu_err_ratelimited(vdev, "Unknown IRQ source: %u\n", irq_src); | |
| 495 | + break; | |
| 496 | + } | |
| 497 | + } | |
| 498 | + | |
| 499 | + return IRQ_HANDLED; | |
| 416 | 500 | } |
| 417 | 501 | |
| 418 | 502 | static int ivpu_irq_init(struct ivpu_device *vdev) |
| @@ -426,9 +510,11 @@ static int ivpu_irq_init(struct ivpu_device *vdev) · 7 unmodified lines | ||
| 426 | 510 | return ret; |
| 427 | 511 | } |
| 428 | 512 | |
| 513 | + ivpu_irq_handlers_init(vdev); | |
| 514 | + | |
| 429 | 515 | vdev->irq = pci_irq_vector(pdev, 0); |
| 430 | 516 | |
| 431 | − ret = devm_request_threaded_irq(vdev->drm.dev, vdev->irq, vdev->hw->ops->irq_handler, | |
| 517 | + ret = devm_request_threaded_irq(vdev->drm.dev, vdev->irq, ivpu_hw_irq_handler, | |
| 432 | 518 | ivpu_irq_thread_handler, IRQF_NO_AUTOEN, DRIVER_NAME, vdev); |
| 433 | 519 | if (ret) |
| 434 | 520 | ivpu_err(vdev, "Failed to request an IRQ %d\n", ret); |
| @@ -505,13 +591,10 @@ static int ivpu_dev_init(struct ivpu_device *vdev) · 70 unmodified lines | ||
| 505 | 591 | if (!vdev->pm) |
| 506 | 592 | return -ENOMEM; |
| 507 | 593 | |
| 508 | − if (ivpu_hw_gen(vdev) >= IVPU_HW_40XX) { | |
| 509 | − vdev->hw->ops = &ivpu_hw_40xx_ops; | |
| 594 | + if (ivpu_hw_ip_gen(vdev) >= IVPU_HW_IP_40XX) | |
| 510 | 595 | vdev->hw->dma_bits = 48; |
| 511 | − } else { | |
| 512 | − vdev->hw->ops = &ivpu_hw_37xx_ops; | |
| 596 | + else | |
| 513 | 597 | vdev->hw->dma_bits = 38; |
| 514 | − } | |
| 515 | 598 | |
| 516 | 599 | vdev->platform = IVPU_PLATFORM_INVALID; |
| 517 | 600 | vdev->context_xa_limit.min = IVPU_USER_CONTEXT_MIN_SSID; |
| @@ -540,7 +623,7 @@ static int ivpu_dev_init(struct ivpu_device *vdev) · 22 unmodified lines | ||
| 540 | 623 | goto err_xa_destroy; |
| 541 | 624 | |
| 542 | 625 | /* Init basic HW info based on buttress registers which are accessible before power up */ |
| 543 | − ret = ivpu_hw_info_init(vdev); | |
| 626 | + ret = ivpu_hw_init(vdev); | |
| 544 | 627 | if (ret) |
| 545 | 628 | goto err_xa_destroy; |
| 546 | 629 | |
| @@ -612,13 +695,14 @@ static void ivpu_bo_unbind_all_user_contexts(struct ivpu_device *vdev) · 65 unmodified lines | ||
| 612 | 695 | |
| 613 | 696 | static void ivpu_dev_fini(struct ivpu_device *vdev) |
| 614 | 697 | { |
| 698 | + ivpu_jobs_abort_all(vdev); | |
| 699 | + ivpu_pm_cancel_recovery(vdev); | |
| 615 | 700 | ivpu_pm_disable(vdev); |
| 616 | 701 | ivpu_prepare_for_reset(vdev); |
| 617 | 702 | ivpu_shutdown(vdev); |
| 618 | 703 | |
| 619 | − ivpu_jobs_abort_all(vdev); | |
| 704 | + ivpu_ms_cleanup_all(vdev); | |
| 620 | 705 | ivpu_job_done_consumer_fini(vdev); |
| 621 | − ivpu_pm_cancel_recovery(vdev); | |
| 622 | 706 | ivpu_bo_unbind_all_user_contexts(vdev); |
| 623 | 707 | |
| 624 | 708 | ivpu_ipc_fini(vdev); |
| @@ -658,6 +742,7 @@ static int ivpu_probe(struct pci_dev *pdev, const struct pci_device_id *id) · 33 unmodified lines | ||
| 658 | 742 | return ret; |
| 659 | 743 | |
| 660 | 744 | ivpu_debugfs_init(vdev); |
| 745 | + ivpu_sysfs_init(vdev); | |
| 661 | 746 | |
| 662 | 747 | ret = drm_dev_register(&vdev->drm, 0); |
| 663 | 748 | if (ret) { |
| @@ -27,8 +27,15 @@ · 26 unmodified lines | ||
| 27 | 27 | #define PCI_DEVICE_ID_ARL 0xad1d |
| 28 | 28 | #define PCI_DEVICE_ID_LNL 0x643e |
| 29 | 29 | |
| 30 | −#define IVPU_HW_37XX 37 | |
| 31 | −#define IVPU_HW_40XX 40 | |
| 30 | +#define IVPU_HW_IP_37XX 37 | |
| 31 | +#define IVPU_HW_IP_40XX 40 | |
| 32 | +#define IVPU_HW_IP_50XX 50 | |
| 33 | +#define IVPU_HW_IP_60XX 60 | |
| 34 | + | |
| 35 | +#define IVPU_HW_IP_REV_LNL_B0 4 | |
| 36 | + | |
| 37 | +#define IVPU_HW_BTRS_MTL 1 | |
| 38 | +#define IVPU_HW_BTRS_LNL 2 | |
| 32 | 39 | |
| 33 | 40 | #define IVPU_GLOBAL_CONTEXT_MMU_SSID 0 |
| 34 | 41 | /* SSID 1 is used by the VPU to represent reserved context */ |
| @@ -39,7 +46,11 @@ · 4 unmodified lines | ||
| 39 | 46 | #define IVPU_MIN_DB 1 |
| 40 | 47 | #define IVPU_MAX_DB 255 |
| 41 | 48 | |
| 42 | −#define IVPU_NUM_ENGINES 2 | |
| 49 | +#define IVPU_NUM_ENGINES 2 | |
| 50 | +#define IVPU_NUM_PRIORITIES 4 | |
| 51 | +#define IVPU_NUM_CMDQS_PER_CTX (IVPU_NUM_ENGINES * IVPU_NUM_PRIORITIES) | |
| 52 | + | |
| 53 | +#define IVPU_CMDQ_INDEX(engine, priority) ((engine) * IVPU_NUM_PRIORITIES + (priority)) | |
| 43 | 54 | |
| 44 | 55 | #define IVPU_PLATFORM_SILICON 0 |
| 45 | 56 | #define IVPU_PLATFORM_SIMICS 2 |
| @@ -93,6 +104,7 @@ struct ivpu_wa_table { · 47 unmodified lines | ||
| 93 | 104 | bool interrupt_clear_with_0; |
| 94 | 105 | bool disable_clock_relinquish; |
| 95 | 106 | bool disable_d0i3_msg; |
| 107 | + bool wp0_during_power_up; | |
| 96 | 108 | }; |
| 97 | 109 | |
| 98 | 110 | struct ivpu_hw_info; |
| @@ -131,11 +143,13 @@ struct ivpu_device { · 32 unmodified lines | ||
| 131 | 143 | |
| 132 | 144 | atomic64_t unique_id_counter; |
| 133 | 145 | |
| 146 | + ktime_t busy_start_ts; | |
| 147 | + ktime_t busy_time; | |
| 148 | + | |
| 134 | 149 | struct { |
| 135 | 150 | int boot; |
| 136 | 151 | int jsm; |
| 137 | 152 | int tdr; |
| 138 | − int reschedule_suspend; | |
| 139 | 153 | int autosuspend; |
| 140 | 154 | int d0i3_entry_msg; |
| 141 | 155 | } timeout; |
| @@ -149,22 +163,31 @@ struct ivpu_file_priv { · 7 unmodified lines | ||
| 149 | 163 | struct kref ref; |
| 150 | 164 | struct ivpu_device *vdev; |
| 151 | 165 | struct mutex lock; /* Protects cmdq */ |
| 152 | − struct ivpu_cmdq *cmdq[IVPU_NUM_ENGINES]; | |
| 166 | + struct ivpu_cmdq *cmdq[IVPU_NUM_CMDQS_PER_CTX]; | |
| 153 | 167 | struct ivpu_mmu_context ctx; |
| 168 | + struct mutex ms_lock; /* Protects ms_instance_list, ms_info_bo */ | |
| 169 | + struct list_head ms_instance_list; | |
| 170 | + struct ivpu_bo *ms_info_bo; | |
| 154 | 171 | bool has_mmu_faults; |
| 155 | 172 | bool bound; |
| 173 | + bool aborted; | |
| 156 | 174 | }; |
| 157 | 175 | |
| 158 | 176 | extern int ivpu_dbg_mask; |
| 159 | 177 | extern u8 ivpu_pll_min_ratio; |
| 160 | 178 | extern u8 ivpu_pll_max_ratio; |
| 179 | +extern int ivpu_sched_mode; | |
| 161 | 180 | extern bool ivpu_disable_mmu_cont_pages; |
| 181 | +extern bool ivpu_force_snoop; | |
| 162 | 182 | |
| 163 | 183 | #define IVPU_TEST_MODE_FW_TEST BIT(0) |
| 164 | 184 | #define IVPU_TEST_MODE_NULL_HW BIT(1) |
| 165 | 185 | #define IVPU_TEST_MODE_NULL_SUBMISSION BIT(2) |
| 166 | 186 | #define IVPU_TEST_MODE_D0I3_MSG_DISABLE BIT(4) |
| 167 | 187 | #define IVPU_TEST_MODE_D0I3_MSG_ENABLE BIT(5) |
| 188 | +#define IVPU_TEST_MODE_PREEMPTION_DISABLE BIT(6) | |
| 189 | +#define IVPU_TEST_MODE_HWS_EXTRA_EVENTS BIT(7) | |
| 190 | +#define IVPU_TEST_MODE_DISABLE_TIMEOUTS BIT(8) | |
| 168 | 191 | extern int ivpu_test_mode; |
| 169 | 192 | |
| 170 | 193 | struct ivpu_file_priv *ivpu_file_priv_get(struct ivpu_file_priv *file_priv); |
| @@ -184,16 +207,32 @@ static inline u16 ivpu_device_id(struct ivpu_device *vdev) · 13 unmodified lines | ||
| 184 | 207 | return to_pci_dev(vdev->drm.dev)->device; |
| 185 | 208 | } |
| 186 | 209 | |
| 187 | −static inline int ivpu_hw_gen(struct ivpu_device *vdev) | |
| 210 | +static inline int ivpu_hw_ip_gen(struct ivpu_device *vdev) | |
| 188 | 211 | { |
| 189 | 212 | switch (ivpu_device_id(vdev)) { |
| 190 | 213 | case PCI_DEVICE_ID_MTL: |
| 191 | 214 | case PCI_DEVICE_ID_ARL: |
| 192 | − return IVPU_HW_37XX; | |
| 215 | + return IVPU_HW_IP_37XX; | |
| 193 | 216 | case PCI_DEVICE_ID_LNL: |
| 194 | − return IVPU_HW_40XX; | |
| 217 | + return IVPU_HW_IP_40XX; | |
| 195 | 218 | default: |
| 196 | − ivpu_err(vdev, "Unknown NPU device\n"); | |
| 219 | + dump_stack(); | |
| 220 | + ivpu_err(vdev, "Unknown NPU IP generation\n"); | |
| 221 | + return 0; | |
| 222 | + } | |
| 223 | +} | |
| 224 | + | |
| 225 | +static inline int ivpu_hw_btrs_gen(struct ivpu_device *vdev) | |
| 226 | +{ | |
| 227 | + switch (ivpu_device_id(vdev)) { | |
| 228 | + case PCI_DEVICE_ID_MTL: | |
| 229 | + case PCI_DEVICE_ID_ARL: | |
| 230 | + return IVPU_HW_BTRS_MTL; | |
| 231 | + case PCI_DEVICE_ID_LNL: | |
| 232 | + return IVPU_HW_BTRS_LNL; | |
| 233 | + default: | |
| 234 | + dump_stack(); | |
| 235 | + ivpu_err(vdev, "Unknown buttress generation\n"); | |
| 197 | 236 | return 0; |
| 198 | 237 | } |
| 199 | 238 | } |
| @@ -231,4 +270,9 @@ static inline bool ivpu_is_fpga(struct ivpu_device *vdev) · 31 unmodified lines | ||
| 231 | 270 | return ivpu_get_platform(vdev) == IVPU_PLATFORM_FPGA; |
| 232 | 271 | } |
| 233 | 272 | |
| 273 | +static inline bool ivpu_is_force_snoop_enabled(struct ivpu_device *vdev) | |
| 274 | +{ | |
| 275 | + return ivpu_force_snoop; | |
| 276 | +} | |
| 277 | + | |
| 234 | 278 | #endif /* __IVPU_DRV_H__ */ |
| @@ -1,6 +1,6 @@ | ||
| 1 | 1 | // SPDX-License-Identifier: GPL-2.0-only |
| 2 | 2 | /* |
| 3 | − * Copyright (C) 2020-2023 Intel Corporation | |
| 3 | + * Copyright (C) 2020-2024 Intel Corporation | |
| 4 | 4 | */ |
| 5 | 5 | |
| 6 | 6 | #include <linux/firmware.h> |
| @@ -44,6 +44,8 @@ · 37 unmodified lines | ||
| 44 | 44 | #define IVPU_FW_CHECK_API_VER_LT(vdev, fw_hdr, name, major, minor) \ |
| 45 | 45 | ivpu_fw_check_api_ver_lt(vdev, fw_hdr, #name, VPU_##name##_API_VER_INDEX, major, minor) |
| 46 | 46 | |
| 47 | +#define IVPU_FOCUS_PRESENT_TIMER_MS 1000 | |
| 48 | + | |
| 47 | 49 | static char *ivpu_firmware; |
| 48 | 50 | module_param_named_unsafe(firmware, ivpu_firmware, charp, 0644); |
| 49 | 51 | MODULE_PARM_DESC(firmware, "NPU firmware binary in /lib/firmware/.."); |
| @@ -52,10 +54,10 @@ static struct { · 2 unmodified lines | ||
| 52 | 54 | int gen; |
| 53 | 55 | const char *name; |
| 54 | 56 | } fw_names[] = { |
| 55 | − { IVPU_HW_37XX, "vpu_37xx.bin" }, | |
| 56 | − { IVPU_HW_37XX, "intel/vpu/vpu_37xx_v0.0.bin" }, | |
| 57 | − { IVPU_HW_40XX, "vpu_40xx.bin" }, | |
| 58 | − { IVPU_HW_40XX, "intel/vpu/vpu_40xx_v0.0.bin" }, | |
| 57 | + { IVPU_HW_IP_37XX, "vpu_37xx.bin" }, | |
| 58 | + { IVPU_HW_IP_37XX, "intel/vpu/vpu_37xx_v0.0.bin" }, | |
| 59 | + { IVPU_HW_IP_40XX, "vpu_40xx.bin" }, | |
| 60 | + { IVPU_HW_IP_40XX, "intel/vpu/vpu_40xx_v0.0.bin" }, | |
| 59 | 61 | }; |
| 60 | 62 | |
| 61 | 63 | static int ivpu_fw_request(struct ivpu_device *vdev) |
| @@ -71,7 +73,7 @@ static int ivpu_fw_request(struct ivpu_device *vdev) · 9 unmodified lines | ||
| 71 | 73 | } |
| 72 | 74 | |
| 73 | 75 | for (i = 0; i < ARRAY_SIZE(fw_names); i++) { |
| 74 | − if (fw_names[i].gen != ivpu_hw_gen(vdev)) | |
| 76 | + if (fw_names[i].gen != ivpu_hw_ip_gen(vdev)) | |
| 75 | 77 | continue; |
| 76 | 78 | |
| 77 | 79 | ret = firmware_request_nowarn(&vdev->fw->file, fw_names[i].name, vdev->drm.dev); |
| @@ -121,6 +123,14 @@ ivpu_fw_check_api_ver_lt(struct ivpu_device *vdev, const struct vpu_firmware_hea · 43 unmodified lines | ||
| 121 | 123 | return false; |
| 122 | 124 | } |
| 123 | 125 | |
| 126 | +static bool is_within_range(u64 addr, size_t size, u64 range_start, size_t range_size) | |
| 127 | +{ | |
| 128 | + if (addr < range_start || addr + size > range_start + range_size) | |
| 129 | + return false; | |
| 130 | + | |
| 131 | + return true; | |
| 132 | +} | |
| 133 | + | |
| 124 | 134 | static int ivpu_fw_parse(struct ivpu_device *vdev) |
| 125 | 135 | { |
| 126 | 136 | struct ivpu_fw_info *fw = vdev->fw; |
| @@ -200,10 +210,27 @@ static int ivpu_fw_parse(struct ivpu_device *vdev) · 73 unmodified lines | ||
| 200 | 210 | |
| 201 | 211 | fw->dvfs_mode = 0; |
| 202 | 212 | |
| 213 | + fw->primary_preempt_buf_size = fw_hdr->preemption_buffer_1_size; | |
| 214 | + fw->secondary_preempt_buf_size = fw_hdr->preemption_buffer_2_size; | |
| 215 | + | |
| 216 | + if (fw_hdr->ro_section_start_address && !is_within_range(fw_hdr->ro_section_start_address, | |
| 217 | + fw_hdr->ro_section_size, | |
| 218 | + fw_hdr->image_load_address, | |
| 219 | + fw_hdr->image_size)) { | |
| 220 | + ivpu_err(vdev, "Invalid read-only section: start address 0x%llx, size %u\n", | |
| 221 | + fw_hdr->ro_section_start_address, fw_hdr->ro_section_size); | |
| 222 | + return -EINVAL; | |
| 223 | + } | |
| 224 | + | |
| 225 | + fw->read_only_addr = fw_hdr->ro_section_start_address; | |
| 226 | + fw->read_only_size = fw_hdr->ro_section_size; | |
| 227 | + | |
| 203 | 228 | ivpu_dbg(vdev, FW_BOOT, "Size: file %lu image %u runtime %u shavenn %u\n", |
| 204 | 229 | fw->file->size, fw->image_size, fw->runtime_size, fw->shave_nn_size); |
| 205 | 230 | ivpu_dbg(vdev, FW_BOOT, "Address: runtime 0x%llx, load 0x%llx, entry point 0x%llx\n", |
| 206 | 231 | fw->runtime_addr, image_load_addr, fw->entry_point); |
| 232 | + ivpu_dbg(vdev, FW_BOOT, "Read-only section: address 0x%llx, size %u\n", | |
| 233 | + fw->read_only_addr, fw->read_only_size); | |
| 207 | 234 | |
| 208 | 235 | return 0; |
| 209 | 236 | } |
| @@ -241,7 +268,7 @@ static int ivpu_fw_update_global_range(struct ivpu_device *vdev) · 31 unmodified lines | ||
| 241 | 268 | return -EINVAL; |
| 242 | 269 | } |
| 243 | 270 | |
| 244 | − ivpu_hw_init_range(&vdev->hw->ranges.global, start, size); | |
| 271 | + ivpu_hw_range_init(&vdev->hw->ranges.global, start, size); | |
| 245 | 272 | return 0; |
| 246 | 273 | } |
| 247 | 274 | |
| @@ -265,6 +292,13 @@ static int ivpu_fw_mem_init(struct ivpu_device *vdev) · 17 unmodified lines | ||
| 265 | 292 | return -ENOMEM; |
| 266 | 293 | } |
| 267 | 294 | |
| 295 | + ret = ivpu_mmu_context_set_pages_ro(vdev, &vdev->gctx, fw->read_only_addr, | |
| 296 | + fw->read_only_size); | |
| 297 | + if (ret) { | |
| 298 | + ivpu_err(vdev, "Failed to set firmware image read-only\n"); | |
| 299 | + goto err_free_fw_mem; | |
| 300 | + } | |
| 301 | + | |
| 268 | 302 | fw->mem_log_crit = ivpu_bo_create_global(vdev, IVPU_FW_CRITICAL_BUFFER_SIZE, |
| 269 | 303 | DRM_IVPU_BO_CACHED | DRM_IVPU_BO_MAPPABLE); |
| 270 | 304 | if (!fw->mem_log_crit) { |
| @@ -464,6 +498,8 @@ static void ivpu_fw_boot_params_print(struct ivpu_device *vdev, struct vpu_boot_ · 193 unmodified lines | ||
| 464 | 498 | boot_params->punit_telemetry_sram_size); |
| 465 | 499 | ivpu_dbg(vdev, FW_BOOT, "boot_params.vpu_telemetry_enable = 0x%x\n", |
| 466 | 500 | boot_params->vpu_telemetry_enable); |
| 501 | + ivpu_dbg(vdev, FW_BOOT, "boot_params.vpu_scheduling_mode = 0x%x\n", | |
| 502 | + boot_params->vpu_scheduling_mode); | |
| 467 | 503 | ivpu_dbg(vdev, FW_BOOT, "boot_params.dvfs_mode = %u\n", |
| 468 | 504 | boot_params->dvfs_mode); |
| 469 | 505 | ivpu_dbg(vdev, FW_BOOT, "boot_params.d0i3_delayed_entry = %d\n", |
| @@ -504,7 +540,7 @@ void ivpu_fw_boot_params_setup(struct ivpu_device *vdev, struct vpu_boot_params · 34 unmodified lines | ||
| 504 | 540 | |
| 505 | 541 | boot_params->magic = VPU_BOOT_PARAMS_MAGIC; |
| 506 | 542 | boot_params->vpu_id = to_pci_dev(vdev->drm.dev)->bus->number; |
| 507 | − boot_params->frequency = ivpu_hw_reg_pll_freq_get(vdev); | |
| 543 | + boot_params->frequency = ivpu_hw_pll_freq_get(vdev); | |
| 508 | 544 | |
| 509 | 545 | /* |
| 510 | 546 | * This param is a debug firmware feature. It switches default clock |
| @@ -561,9 +597,12 @@ void ivpu_fw_boot_params_setup(struct ivpu_device *vdev, struct vpu_boot_params · 50 unmodified lines | ||
| 561 | 597 | boot_params->verbose_tracing_buff_addr = vdev->fw->mem_log_verb->vpu_addr; |
| 562 | 598 | boot_params->verbose_tracing_buff_size = ivpu_bo_size(vdev->fw->mem_log_verb); |
| 563 | 599 | |
| 564 | − boot_params->punit_telemetry_sram_base = ivpu_hw_reg_telemetry_offset_get(vdev); | |
| 565 | − boot_params->punit_telemetry_sram_size = ivpu_hw_reg_telemetry_size_get(vdev); | |
| 566 | − boot_params->vpu_telemetry_enable = ivpu_hw_reg_telemetry_enable_get(vdev); | |
| 600 | + boot_params->punit_telemetry_sram_base = ivpu_hw_telemetry_offset_get(vdev); | |
| 601 | + boot_params->punit_telemetry_sram_size = ivpu_hw_telemetry_size_get(vdev); | |
| 602 | + boot_params->vpu_telemetry_enable = ivpu_hw_telemetry_enable_get(vdev); | |
| 603 | + boot_params->vpu_scheduling_mode = vdev->hw->sched_mode; | |
| 604 | + if (vdev->hw->sched_mode == VPU_SCHEDULING_MODE_HW) | |
| 605 | + boot_params->vpu_focus_present_timer_ms = IVPU_FOCUS_PRESENT_TIMER_MS; | |
| 567 | 606 | boot_params->dvfs_mode = vdev->fw->dvfs_mode; |
| 568 | 607 | if (!IVPU_WA(disable_d0i3_msg)) |
| 569 | 608 | boot_params->d0i3_delayed_entry = 1; |
| @@ -28,6 +28,10 @@ struct ivpu_fw_info { · 27 unmodified lines | ||
| 28 | 28 | u32 trace_destination_mask; |
| 29 | 29 | u64 trace_hw_component_mask; |
| 30 | 30 | u32 dvfs_mode; |
| 31 | + u32 primary_preempt_buf_size; | |
| 32 | + u32 secondary_preempt_buf_size; | |
| 33 | + u64 read_only_addr; | |
| 34 | + u32 read_only_size; | |
| 31 | 35 | }; |
| 32 | 36 | |
| 33 | 37 | int ivpu_fw_init(struct ivpu_device *vdev); |
| @@ -60,14 +60,17 @@ static inline u32 ivpu_bo_cache_mode(struct ivpu_bo *bo) · 59 unmodified lines | ||
| 60 | 60 | return bo->flags & DRM_IVPU_BO_CACHE_MASK; |
| 61 | 61 | } |
| 62 | 62 | |
| 63 | −static inline bool ivpu_bo_is_snooped(struct ivpu_bo *bo) | |
| 63 | +static inline struct ivpu_device *ivpu_bo_to_vdev(struct ivpu_bo *bo) | |
| 64 | 64 | { |
| 65 | − return ivpu_bo_cache_mode(bo) == DRM_IVPU_BO_CACHED; | |
| 65 | + return to_ivpu_device(bo->base.base.dev); | |
| 66 | 66 | } |
| 67 | 67 | |
| 68 | −static inline struct ivpu_device *ivpu_bo_to_vdev(struct ivpu_bo *bo) | |
| 68 | +static inline bool ivpu_bo_is_snooped(struct ivpu_bo *bo) | |
| 69 | 69 | { |
| 70 | − return to_ivpu_device(bo->base.base.dev); | |
| 70 | + if (ivpu_is_force_snoop_enabled(ivpu_bo_to_vdev(bo))) | |
| 71 | + return true; | |
| 72 | + | |
| 73 | + return ivpu_bo_cache_mode(bo) == DRM_IVPU_BO_CACHED; | |
| 71 | 74 | } |
| 72 | 75 | |
| 73 | 76 | static inline void *ivpu_to_cpu_addr(struct ivpu_bo *bo, u32 vpu_addr) |
| @@ -0,0 +1,331 @@ | ||
| 1 | +// SPDX-License-Identifier: GPL-2.0-only | |
| 2 | +/* | |
| 3 | + * Copyright (C) 2020 - 2024 Intel Corporation | |
| 4 | + */ | |
| 5 | + | |
| 6 | +#include "ivpu_drv.h" | |
| 7 | +#include "ivpu_hw.h" | |
| 8 | +#include "ivpu_hw_btrs.h" | |
| 9 | +#include "ivpu_hw_ip.h" | |
| 10 | + | |
| 11 | +#include <linux/dmi.h> | |
| 12 | + | |
| 13 | +static char *platform_to_str(u32 platform) | |
| 14 | +{ | |
| 15 | + switch (platform) { | |
| 16 | + case IVPU_PLATFORM_SILICON: | |
| 17 | + return "SILICON"; | |
| 18 | + case IVPU_PLATFORM_SIMICS: | |
| 19 | + return "SIMICS"; | |
| 20 | + case IVPU_PLATFORM_FPGA: | |
| 21 | + return "FPGA"; | |
| 22 | + default: | |
| 23 | + return "Invalid platform"; | |
| 24 | + } | |
| 25 | +} | |
| 26 | + | |
| 27 | +static const struct dmi_system_id dmi_platform_simulation[] = { | |
| 28 | + { | |
| 29 | + .ident = "Intel Simics", | |
| 30 | + .matches = { | |
| 31 | + DMI_MATCH(DMI_BOARD_NAME, "lnlrvp"), | |
| 32 | + DMI_MATCH(DMI_BOARD_VERSION, "1.0"), | |
| 33 | + DMI_MATCH(DMI_BOARD_SERIAL, "123456789"), | |
| 34 | + }, | |
| 35 | + }, | |
| 36 | + { | |
| 37 | + .ident = "Intel Simics", | |
| 38 | + .matches = { | |
| 39 | + DMI_MATCH(DMI_BOARD_NAME, "Simics"), | |
| 40 | + }, | |
| 41 | + }, | |
| 42 | + { } | |
| 43 | +}; | |
| 44 | + | |
| 45 | +static void platform_init(struct ivpu_device *vdev) | |
| 46 | +{ | |
| 47 | + if (dmi_check_system(dmi_platform_simulation)) | |
| 48 | + vdev->platform = IVPU_PLATFORM_SIMICS; | |
| 49 | + else | |
| 50 | + vdev->platform = IVPU_PLATFORM_SILICON; | |
| 51 | + | |
| 52 | + ivpu_dbg(vdev, MISC, "Platform type: %s (%d)\n", | |
| 53 | + platform_to_str(vdev->platform), vdev->platform); | |
| 54 | +} | |
| 55 | + | |
| 56 | +static void wa_init(struct ivpu_device *vdev) | |
| 57 | +{ | |
| 58 | + vdev->wa.punit_disabled = ivpu_is_fpga(vdev); | |
| 59 | + vdev->wa.clear_runtime_mem = false; | |
| 60 | + | |
| 61 | + if (ivpu_hw_btrs_gen(vdev) == IVPU_HW_BTRS_MTL) | |
| 62 | + vdev->wa.interrupt_clear_with_0 = ivpu_hw_btrs_irqs_clear_with_0_mtl(vdev); | |
| 63 | + | |
| 64 | + if (ivpu_device_id(vdev) == PCI_DEVICE_ID_LNL && | |
| 65 | + ivpu_revision(vdev) < IVPU_HW_IP_REV_LNL_B0) | |
| 66 | + vdev->wa.disable_clock_relinquish = true; | |
| 67 | + | |
| 68 | + if (ivpu_hw_ip_gen(vdev) == IVPU_HW_IP_37XX) | |
| 69 | + vdev->wa.wp0_during_power_up = true; | |
| 70 | + | |
| 71 | + IVPU_PRINT_WA(punit_disabled); | |
| 72 | + IVPU_PRINT_WA(clear_runtime_mem); | |
| 73 | + IVPU_PRINT_WA(interrupt_clear_with_0); | |
| 74 | + IVPU_PRINT_WA(disable_clock_relinquish); | |
| 75 | + IVPU_PRINT_WA(wp0_during_power_up); | |
| 76 | +} | |
| 77 | + | |
| 78 | +static void timeouts_init(struct ivpu_device *vdev) | |
| 79 | +{ | |
| 80 | + if (ivpu_test_mode & IVPU_TEST_MODE_DISABLE_TIMEOUTS) { | |
| 81 | + vdev->timeout.boot = -1; | |
| 82 | + vdev->timeout.jsm = -1; | |
| 83 | + vdev->timeout.tdr = -1; | |
| 84 | + vdev->timeout.autosuspend = -1; | |
| 85 | + vdev->timeout.d0i3_entry_msg = -1; | |
| 86 | + } else if (ivpu_is_fpga(vdev)) { | |
| 87 | + vdev->timeout.boot = 100000; | |
| 88 | + vdev->timeout.jsm = 50000; | |
| 89 | + vdev->timeout.tdr = 2000000; | |
| 90 | + vdev->timeout.autosuspend = -1; | |
| 91 | + vdev->timeout.d0i3_entry_msg = 500; | |
| 92 | + } else if (ivpu_is_simics(vdev)) { | |
| 93 | + vdev->timeout.boot = 50; | |
| 94 | + vdev->timeout.jsm = 500; | |
| 95 | + vdev->timeout.tdr = 10000; | |
| 96 | + vdev->timeout.autosuspend = -1; | |
| 97 | + vdev->timeout.d0i3_entry_msg = 100; | |
| 98 | + } else { | |
| 99 | + vdev->timeout.boot = 1000; | |
| 100 | + vdev->timeout.jsm = 500; | |
| 101 | + vdev->timeout.tdr = 2000; | |
| 102 | + if (ivpu_hw_ip_gen(vdev) == IVPU_HW_IP_37XX) | |
| 103 | + vdev->timeout.autosuspend = 10; | |
| 104 | + else | |
| 105 | + vdev->timeout.autosuspend = 100; | |
| 106 | + vdev->timeout.d0i3_entry_msg = 5; | |
| 107 | + } | |
| 108 | +} | |
| 109 | + | |
| 110 | +static void memory_ranges_init(struct ivpu_device *vdev) | |
| 111 | +{ | |
| 112 | + if (ivpu_hw_ip_gen(vdev) == IVPU_HW_IP_37XX) { | |
| 113 | + ivpu_hw_range_init(&vdev->hw->ranges.global, 0x80000000, SZ_512M); | |
| 114 | + ivpu_hw_range_init(&vdev->hw->ranges.user, 0xc0000000, 255 * SZ_1M); | |
| 115 | + ivpu_hw_range_init(&vdev->hw->ranges.shave, 0x180000000, SZ_2G); | |
| 116 | + ivpu_hw_range_init(&vdev->hw->ranges.dma, 0x200000000, SZ_8G); | |
| 117 | + } else { | |
| 118 | + ivpu_hw_range_init(&vdev->hw->ranges.global, 0x80000000, SZ_512M); | |
| 119 | + ivpu_hw_range_init(&vdev->hw->ranges.user, 0x80000000, SZ_256M); | |
| 120 | + ivpu_hw_range_init(&vdev->hw->ranges.shave, 0x80000000 + SZ_256M, SZ_2G - SZ_256M); | |
| 121 | + ivpu_hw_range_init(&vdev->hw->ranges.dma, 0x200000000, SZ_8G); | |
| 122 | + } | |
| 123 | +} | |
| 124 | + | |
| 125 | +static int wp_enable(struct ivpu_device *vdev) | |
| 126 | +{ | |
| 127 | + return ivpu_hw_btrs_wp_drive(vdev, true); | |
| 128 | +} | |
| 129 | + | |
| 130 | +static int wp_disable(struct ivpu_device *vdev) | |
| 131 | +{ | |
| 132 | + return ivpu_hw_btrs_wp_drive(vdev, false); | |
| 133 | +} | |
| 134 | + | |
| 135 | +int ivpu_hw_power_up(struct ivpu_device *vdev) | |
| 136 | +{ | |
| 137 | + int ret; | |
| 138 | + | |
| 139 | + if (IVPU_WA(wp0_during_power_up)) { | |
| 140 | + /* WP requests may fail when powering down, so issue WP 0 here */ | |
| 141 | + ret = wp_disable(vdev); | |
| 142 | + if (ret) | |
| 143 | + ivpu_warn(vdev, "Failed to disable workpoint: %d\n", ret); | |
| 144 | + } | |
| 145 | + | |
| 146 | + ret = ivpu_hw_btrs_d0i3_disable(vdev); | |
| 147 | + if (ret) | |
| 148 | + ivpu_warn(vdev, "Failed to disable D0I3: %d\n", ret); | |
| 149 | + | |
| 150 | + ret = wp_enable(vdev); | |
| 151 | + if (ret) { | |
| 152 | + ivpu_err(vdev, "Failed to enable workpoint: %d\n", ret); | |
| 153 | + return ret; | |
| 154 | + } | |
| 155 | + | |
| 156 | + if (ivpu_hw_btrs_gen(vdev) >= IVPU_HW_BTRS_LNL) { | |
| 157 | + if (IVPU_WA(disable_clock_relinquish)) | |
| 158 | + ivpu_hw_btrs_clock_relinquish_disable_lnl(vdev); | |
| 159 | + ivpu_hw_btrs_profiling_freq_reg_set_lnl(vdev); | |
| 160 | + ivpu_hw_btrs_ats_print_lnl(vdev); | |
| 161 | + } | |
| 162 | + | |
| 163 | + ret = ivpu_hw_ip_host_ss_configure(vdev); | |
| 164 | + if (ret) { | |
| 165 | + ivpu_err(vdev, "Failed to configure host SS: %d\n", ret); | |
| 166 | + return ret; | |
| 167 | + } | |
| 168 | + | |
| 169 | + ivpu_hw_ip_idle_gen_disable(vdev); | |
| 170 | + | |
| 171 | + ret = ivpu_hw_btrs_wait_for_clock_res_own_ack(vdev); | |
| 172 | + if (ret) { | |
| 173 | + ivpu_err(vdev, "Timed out waiting for clock resource own ACK\n"); | |
| 174 | + return ret; | |
| 175 | + } | |
| 176 | + | |
| 177 | + ret = ivpu_hw_ip_pwr_domain_enable(vdev); | |
| 178 | + if (ret) { | |
| 179 | + ivpu_err(vdev, "Failed to enable power domain: %d\n", ret); | |
| 180 | + return ret; | |
| 181 | + } | |
| 182 | + | |
| 183 | + ret = ivpu_hw_ip_host_ss_axi_enable(vdev); | |
| 184 | + if (ret) { | |
| 185 | + ivpu_err(vdev, "Failed to enable AXI: %d\n", ret); | |
| 186 | + return ret; | |
| 187 | + } | |
| 188 | + | |
| 189 | + if (ivpu_hw_btrs_gen(vdev) == IVPU_HW_BTRS_LNL) | |
| 190 | + ivpu_hw_btrs_set_port_arbitration_weights_lnl(vdev); | |
| 191 | + | |
| 192 | + ret = ivpu_hw_ip_top_noc_enable(vdev); | |
| 193 | + if (ret) | |
| 194 | + ivpu_err(vdev, "Failed to enable TOP NOC: %d\n", ret); | |
| 195 | + | |
| 196 | + return ret; | |
| 197 | +} | |
| 198 | + | |
| 199 | +static void save_d0i3_entry_timestamp(struct ivpu_device *vdev) | |
| 200 | +{ | |
| 201 | + vdev->hw->d0i3_entry_host_ts = ktime_get_boottime(); | |
| 202 | + vdev->hw->d0i3_entry_vpu_ts = ivpu_hw_ip_read_perf_timer_counter(vdev); | |
| 203 | +} | |
| 204 | + | |
| 205 | +int ivpu_hw_reset(struct ivpu_device *vdev) | |
| 206 | +{ | |
| 207 | + int ret = 0; | |
| 208 | + | |
| 209 | + if (ivpu_hw_btrs_ip_reset(vdev)) { | |
| 210 | + ivpu_err(vdev, "Failed to reset NPU IP\n"); | |
| 211 | + ret = -EIO; | |
| 212 | + } | |
| 213 | + | |
| 214 | + if (wp_disable(vdev)) { | |
| 215 | + ivpu_err(vdev, "Failed to disable workpoint\n"); | |
| 216 | + ret = -EIO; | |
| 217 | + } | |
| 218 | + | |
| 219 | + return ret; | |
| 220 | +} | |
| 221 | + | |
| 222 | +int ivpu_hw_power_down(struct ivpu_device *vdev) | |
| 223 | +{ | |
| 224 | + int ret = 0; | |
| 225 | + | |
| 226 | + save_d0i3_entry_timestamp(vdev); | |
| 227 | + | |
| 228 | + if (!ivpu_hw_is_idle(vdev)) | |
| 229 | + ivpu_warn(vdev, "NPU not idle during power down\n"); | |
| 230 | + | |
| 231 | + if (ivpu_hw_reset(vdev)) { | |
| 232 | + ivpu_err(vdev, "Failed to reset NPU\n"); | |
| 233 | + ret = -EIO; | |
| 234 | + } | |
| 235 | + | |
| 236 | + if (ivpu_hw_btrs_d0i3_enable(vdev)) { | |
| 237 | + ivpu_err(vdev, "Failed to enter D0I3\n"); | |
| 238 | + ret = -EIO; | |
| 239 | + } | |
| 240 | + | |
| 241 | + return ret; | |
| 242 | +} | |
| 243 | + | |
| 244 | +int ivpu_hw_init(struct ivpu_device *vdev) | |
| 245 | +{ | |
| 246 | + ivpu_hw_btrs_info_init(vdev); | |
| 247 | + ivpu_hw_btrs_freq_ratios_init(vdev); | |
| 248 | + memory_ranges_init(vdev); | |
| 249 | + platform_init(vdev); | |
| 250 | + wa_init(vdev); | |
| 251 | + timeouts_init(vdev); | |
| 252 | + | |
| 253 | + return 0; | |
| 254 | +} | |
| 255 | + | |
| 256 | +int ivpu_hw_boot_fw(struct ivpu_device *vdev) | |
| 257 | +{ | |
| 258 | + int ret; | |
| 259 | + | |
| 260 | + ivpu_hw_ip_snoop_disable(vdev); | |
| 261 | + ivpu_hw_ip_tbu_mmu_enable(vdev); | |
| 262 | + ret = ivpu_hw_ip_soc_cpu_boot(vdev); | |
| 263 | + if (ret) | |
| 264 | + ivpu_err(vdev, "Failed to boot SOC CPU: %d\n", ret); | |
| 265 | + | |
| 266 | + return ret; | |
| 267 | +} | |
| 268 | + | |
| 269 | +void ivpu_hw_profiling_freq_drive(struct ivpu_device *vdev, bool enable) | |
| 270 | +{ | |
| 271 | + if (ivpu_hw_ip_gen(vdev) == IVPU_HW_IP_37XX) { | |
| 272 | + vdev->hw->pll.profiling_freq = PLL_PROFILING_FREQ_DEFAULT; | |
| 273 | + return; | |
| 274 | + } | |
| 275 | + | |
| 276 | + if (enable) | |
| 277 | + vdev->hw->pll.profiling_freq = PLL_PROFILING_FREQ_HIGH; | |
| 278 | + else | |
| 279 | + vdev->hw->pll.profiling_freq = PLL_PROFILING_FREQ_DEFAULT; | |
| 280 | +} | |
| 281 | + | |
| 282 | +void ivpu_irq_handlers_init(struct ivpu_device *vdev) | |
| 283 | +{ | |
| 284 | + INIT_KFIFO(vdev->hw->irq.fifo); | |
| 285 | + | |
| 286 | + if (ivpu_hw_ip_gen(vdev) == IVPU_HW_IP_37XX) | |
| 287 | + vdev->hw->irq.ip_irq_handler = ivpu_hw_ip_irq_handler_37xx; | |
| 288 | + else | |
| 289 | + vdev->hw->irq.ip_irq_handler = ivpu_hw_ip_irq_handler_40xx; | |
| 290 | + | |
| 291 | + if (ivpu_hw_btrs_gen(vdev) == IVPU_HW_BTRS_MTL) | |
| 292 | + vdev->hw->irq.btrs_irq_handler = ivpu_hw_btrs_irq_handler_mtl; | |
| 293 | + else | |
| 294 | + vdev->hw->irq.btrs_irq_handler = ivpu_hw_btrs_irq_handler_lnl; | |
| 295 | +} | |
| 296 | + | |
| 297 | +void ivpu_hw_irq_enable(struct ivpu_device *vdev) | |
| 298 | +{ | |
| 299 | + kfifo_reset(&vdev->hw->irq.fifo); | |
| 300 | + ivpu_hw_ip_irq_enable(vdev); | |
| 301 | + ivpu_hw_btrs_irq_enable(vdev); | |
| 302 | +} | |
| 303 | + | |
| 304 | +void ivpu_hw_irq_disable(struct ivpu_device *vdev) | |
| 305 | +{ | |
| 306 | + ivpu_hw_btrs_irq_disable(vdev); | |
| 307 | + ivpu_hw_ip_irq_disable(vdev); | |
| 308 | +} | |
| 309 | + | |
| 310 | +irqreturn_t ivpu_hw_irq_handler(int irq, void *ptr) | |
| 311 | +{ | |
| 312 | + struct ivpu_device *vdev = ptr; | |
| 313 | + bool ip_handled, btrs_handled; | |
| 314 | + | |
| 315 | + ivpu_hw_btrs_global_int_disable(vdev); | |
| 316 | + | |
| 317 | + btrs_handled = ivpu_hw_btrs_irq_handler(vdev, irq); | |
| 318 | + if (!ivpu_hw_is_idle((vdev)) || !btrs_handled) | |
| 319 | + ip_handled = ivpu_hw_ip_irq_handler(vdev, irq); | |
| 320 | + else | |
| 321 | + ip_handled = false; | |
| 322 | + | |
| 323 | + /* Re-enable global interrupts to re-trigger MSI for pending interrupts */ | |
| 324 | + ivpu_hw_btrs_global_int_enable(vdev); | |
| 325 | + | |
| 326 | + if (!kfifo_is_empty(&vdev->hw->irq.fifo)) | |
| 327 | + return IRQ_WAKE_THREAD; | |
| 328 | + if (ip_handled || btrs_handled) | |
| 329 | + return IRQ_HANDLED; | |
| 330 | + return IRQ_NONE; | |
| 331 | +} | |
| @@ -1,39 +1,22 @@ | ||
| 1 | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
| 2 | 2 | /* |
| 3 | − * Copyright (C) 2020-2023 Intel Corporation | |
| 3 | + * Copyright (C) 2020-2024 Intel Corporation | |
| 4 | 4 | */ |
| 5 | 5 | |
| 6 | 6 | #ifndef __IVPU_HW_H__ |
| 7 | 7 | #define __IVPU_HW_H__ |
| 8 | 8 | |
| 9 | +#include <linux/kfifo.h> | |
| 10 | + | |
| 9 | 11 | #include "ivpu_drv.h" |
| 12 | +#include "ivpu_hw_btrs.h" | |
| 13 | +#include "ivpu_hw_ip.h" | |
| 10 | 14 | |
| 11 | −struct ivpu_hw_ops { | |
| 12 | − int (*info_init)(struct ivpu_device *vdev); | |
| 13 | − int (*power_up)(struct ivpu_device *vdev); | |
| 14 | − int (*boot_fw)(struct ivpu_device *vdev); | |
| 15 | − int (*power_down)(struct ivpu_device *vdev); | |
| 16 | − int (*reset)(struct ivpu_device *vdev); | |
| 17 | − bool (*is_idle)(struct ivpu_device *vdev); | |
| 18 | − int (*wait_for_idle)(struct ivpu_device *vdev); | |
| 19 | − void (*wdt_disable)(struct ivpu_device *vdev); | |
| 20 | − void (*diagnose_failure)(struct ivpu_device *vdev); | |
| 21 | − u32 (*profiling_freq_get)(struct ivpu_device *vdev); | |
| 22 | − void (*profiling_freq_drive)(struct ivpu_device *vdev, bool enable); | |
| 23 | − u32 (*reg_pll_freq_get)(struct ivpu_device *vdev); | |
| 24 | − u32 (*ratio_to_freq)(struct ivpu_device *vdev, u32 ratio); | |
| 25 | − u32 (*reg_telemetry_offset_get)(struct ivpu_device *vdev); | |
| 26 | − u32 (*reg_telemetry_size_get)(struct ivpu_device *vdev); | |
| 27 | − u32 (*reg_telemetry_enable_get)(struct ivpu_device *vdev); | |
| 28 | − void (*reg_db_set)(struct ivpu_device *vdev, u32 db_id); | |
| 29 | − u32 (*reg_ipc_rx_addr_get)(struct ivpu_device *vdev); | |
| 30 | − u32 (*reg_ipc_rx_count_get)(struct ivpu_device *vdev); | |
| 31 | − void (*reg_ipc_tx_set)(struct ivpu_device *vdev, u32 vpu_addr); | |
| 32 | − void (*irq_clear)(struct ivpu_device *vdev); | |
| 33 | − void (*irq_enable)(struct ivpu_device *vdev); | |
| 34 | − void (*irq_disable)(struct ivpu_device *vdev); | |
| 35 | − irqreturn_t (*irq_handler)(int irq, void *ptr); | |
| 36 | −}; | |
| 15 | +#define IVPU_HW_IRQ_FIFO_LENGTH 1024 | |
| 16 | + | |
| 17 | +#define IVPU_HW_IRQ_SRC_IPC 1 | |
| 18 | +#define IVPU_HW_IRQ_SRC_MMU_EVTQ 2 | |
| 19 | +#define IVPU_HW_IRQ_SRC_DCT 3 | |
| 37 | 20 | |
| 38 | 21 | struct ivpu_addr_range { |
| 39 | 22 | resource_size_t start; |
| @@ -41,7 +24,11 @@ struct ivpu_addr_range { · 1 unmodified line | ||
| 41 | 24 | }; |
| 42 | 25 | |
| 43 | 26 | struct ivpu_hw_info { |
| 44 | − const struct ivpu_hw_ops *ops; | |
| 27 | + struct { | |
| 28 | + bool (*btrs_irq_handler)(struct ivpu_device *vdev, int irq); | |
| 29 | + bool (*ip_irq_handler)(struct ivpu_device *vdev, int irq); | |
| 30 | + DECLARE_KFIFO(fifo, u8, IVPU_HW_IRQ_FIFO_LENGTH); | |
| 31 | + } irq; | |
| 45 | 32 | struct { |
| 46 | 33 | struct ivpu_addr_range global; |
| 47 | 34 | struct ivpu_addr_range user; |
| @@ -59,6 +46,7 @@ struct ivpu_hw_info { · 11 unmodified lines | ||
| 59 | 46 | u32 profiling_freq; |
| 60 | 47 | } pll; |
| 61 | 48 | u32 tile_fuse; |
| 49 | + u32 sched_mode; | |
| 62 | 50 | u32 sku; |
| 63 | 51 | u16 config; |
| 64 | 52 | int dma_bits; |
| @@ -66,140 +54,107 @@ struct ivpu_hw_info { · 1 unmodified line | ||
| 66 | 54 | u64 d0i3_entry_vpu_ts; |
| 67 | 55 | }; |
| 68 | 56 | |
| 69 | −extern const struct ivpu_hw_ops ivpu_hw_37xx_ops; | |
| 70 | −extern const struct ivpu_hw_ops ivpu_hw_40xx_ops; | |
| 71 | − | |
| 72 | −static inline int ivpu_hw_info_init(struct ivpu_device *vdev) | |
| 73 | −{ | |
| 74 | − return vdev->hw->ops->info_init(vdev); | |
| 75 | −}; | |
| 76 | − | |
| 77 | −static inline int ivpu_hw_power_up(struct ivpu_device *vdev) | |
| 78 | −{ | |
| 79 | − ivpu_dbg(vdev, PM, "HW power up\n"); | |
| 57 | +int ivpu_hw_init(struct ivpu_device *vdev); | |
| 58 | +int ivpu_hw_power_up(struct ivpu_device *vdev); | |
| 59 | +int ivpu_hw_power_down(struct ivpu_device *vdev); | |
| 60 | +int ivpu_hw_reset(struct ivpu_device *vdev); | |
| 61 | +int ivpu_hw_boot_fw(struct ivpu_device *vdev); | |
| 62 | +void ivpu_hw_profiling_freq_drive(struct ivpu_device *vdev, bool enable); | |
| 63 | +void ivpu_irq_handlers_init(struct ivpu_device *vdev); | |
| 64 | +void ivpu_hw_irq_enable(struct ivpu_device *vdev); | |
| 65 | +void ivpu_hw_irq_disable(struct ivpu_device *vdev); | |
| 66 | +irqreturn_t ivpu_hw_irq_handler(int irq, void *ptr); | |
| 80 | 67 | |
| 81 | − return vdev->hw->ops->power_up(vdev); | |
| 82 | −}; | |
| 83 | − | |
| 84 | −static inline int ivpu_hw_boot_fw(struct ivpu_device *vdev) | |
| 85 | −{ | |
| 86 | − return vdev->hw->ops->boot_fw(vdev); | |
| 87 | −}; | |
| 88 | − | |
| 89 | −static inline bool ivpu_hw_is_idle(struct ivpu_device *vdev) | |
| 90 | −{ | |
| 91 | − return vdev->hw->ops->is_idle(vdev); | |
| 92 | −}; | |
| 93 | − | |
| 94 | −static inline int ivpu_hw_wait_for_idle(struct ivpu_device *vdev) | |
| 68 | +static inline u32 ivpu_hw_btrs_irq_handler(struct ivpu_device *vdev, int irq) | |
| 95 | 69 | { |
| 96 | − return vdev->hw->ops->wait_for_idle(vdev); | |
| 97 | −}; | |
| 98 | − | |
| 99 | −static inline int ivpu_hw_power_down(struct ivpu_device *vdev) | |
| 100 | −{ | |
| 101 | − ivpu_dbg(vdev, PM, "HW power down\n"); | |
| 102 | − | |
| 103 | − return vdev->hw->ops->power_down(vdev); | |
| 104 | −}; | |
| 105 | − | |
| 106 | −static inline int ivpu_hw_reset(struct ivpu_device *vdev) | |
| 107 | −{ | |
| 108 | − ivpu_dbg(vdev, PM, "HW reset\n"); | |
| 109 | − | |
| 110 | − return vdev->hw->ops->reset(vdev); | |
| 111 | −}; | |
| 112 | − | |
| 113 | −static inline void ivpu_hw_wdt_disable(struct ivpu_device *vdev) | |
| 114 | −{ | |
| 115 | − vdev->hw->ops->wdt_disable(vdev); | |
| 116 | −}; | |
| 70 | + return vdev->hw->irq.btrs_irq_handler(vdev, irq); | |
| 71 | +} | |
| 117 | 72 | |
| 118 | −static inline u32 ivpu_hw_profiling_freq_get(struct ivpu_device *vdev) | |
| 73 | +static inline u32 ivpu_hw_ip_irq_handler(struct ivpu_device *vdev, int irq) | |
| 119 | 74 | { |
| 120 | − return vdev->hw->ops->profiling_freq_get(vdev); | |
| 121 | −}; | |
| 75 | + return vdev->hw->irq.ip_irq_handler(vdev, irq); | |
| 76 | +} | |
| 122 | 77 | |
| 123 | −static inline void ivpu_hw_profiling_freq_drive(struct ivpu_device *vdev, bool enable) | |
| 78 | +static inline void ivpu_hw_range_init(struct ivpu_addr_range *range, u64 start, u64 size) | |
| 124 | 79 | { |
| 125 | − return vdev->hw->ops->profiling_freq_drive(vdev, enable); | |
| 126 | −}; | |
| 80 | + range->start = start; | |
| 81 | + range->end = start + size; | |
| 82 | +} | |
| 127 | 83 | |
| 128 | −/* Register indirect accesses */ | |
| 129 | −static inline u32 ivpu_hw_reg_pll_freq_get(struct ivpu_device *vdev) | |
| 84 | +static inline u64 ivpu_hw_range_size(const struct ivpu_addr_range *range) | |
| 130 | 85 | { |
| 131 | − return vdev->hw->ops->reg_pll_freq_get(vdev); | |
| 132 | −}; | |
| 86 | + return range->end - range->start; | |
| 87 | +} | |
| 133 | 88 | |
| 134 | 89 | static inline u32 ivpu_hw_ratio_to_freq(struct ivpu_device *vdev, u32 ratio) |
| 135 | 90 | { |
| 136 | − return vdev->hw->ops->ratio_to_freq(vdev, ratio); | |
| 91 | + return ivpu_hw_btrs_ratio_to_freq(vdev, ratio); | |
| 137 | 92 | } |
| 138 | 93 | |
| 139 | −static inline u32 ivpu_hw_reg_telemetry_offset_get(struct ivpu_device *vdev) | |
| 94 | +static inline void ivpu_hw_irq_clear(struct ivpu_device *vdev) | |
| 140 | 95 | { |
| 141 | − return vdev->hw->ops->reg_telemetry_offset_get(vdev); | |
| 142 | −}; | |
| 96 | + ivpu_hw_ip_irq_clear(vdev); | |
| 97 | +} | |
| 143 | 98 | |
| 144 | −static inline u32 ivpu_hw_reg_telemetry_size_get(struct ivpu_device *vdev) | |
| 99 | +static inline u32 ivpu_hw_pll_freq_get(struct ivpu_device *vdev) | |
| 145 | 100 | { |
| 146 | − return vdev->hw->ops->reg_telemetry_size_get(vdev); | |
| 147 | −}; | |
| 101 | + return ivpu_hw_btrs_pll_freq_get(vdev); | |
| 102 | +} | |
| 148 | 103 | |
| 149 | −static inline u32 ivpu_hw_reg_telemetry_enable_get(struct ivpu_device *vdev) | |
| 104 | +static inline u32 ivpu_hw_profiling_freq_get(struct ivpu_device *vdev) | |
| 150 | 105 | { |
| 151 | − return vdev->hw->ops->reg_telemetry_enable_get(vdev); | |
| 152 | −}; | |
| 106 | + return vdev->hw->pll.profiling_freq; | |
| 107 | +} | |
| 153 | 108 | |
| 154 | −static inline void ivpu_hw_reg_db_set(struct ivpu_device *vdev, u32 db_id) | |
| 109 | +static inline void ivpu_hw_diagnose_failure(struct ivpu_device *vdev) | |
| 155 | 110 | { |
| 156 | − vdev->hw->ops->reg_db_set(vdev, db_id); | |
| 157 | −}; | |
| 111 | + ivpu_hw_ip_diagnose_failure(vdev); | |
| 112 | + ivpu_hw_btrs_diagnose_failure(vdev); | |
| 113 | +} | |
| 158 | 114 | |
| 159 | −static inline u32 ivpu_hw_reg_ipc_rx_addr_get(struct ivpu_device *vdev) | |
| 115 | +static inline u32 ivpu_hw_telemetry_offset_get(struct ivpu_device *vdev) | |
| 160 | 116 | { |
| 161 | − return vdev->hw->ops->reg_ipc_rx_addr_get(vdev); | |
| 162 | −}; | |
| 117 | + return ivpu_hw_btrs_telemetry_offset_get(vdev); | |
| 118 | +} | |
| 163 | 119 | |
| 164 | −static inline u32 ivpu_hw_reg_ipc_rx_count_get(struct ivpu_device *vdev) | |
| 120 | +static inline u32 ivpu_hw_telemetry_size_get(struct ivpu_device *vdev) | |
| 165 | 121 | { |
| 166 | − return vdev->hw->ops->reg_ipc_rx_count_get(vdev); | |
| 167 | −}; | |
| 122 | + return ivpu_hw_btrs_telemetry_size_get(vdev); | |
| 123 | +} | |
| 168 | 124 | |
| 169 | −static inline void ivpu_hw_reg_ipc_tx_set(struct ivpu_device *vdev, u32 vpu_addr) | |
| 125 | +static inline u32 ivpu_hw_telemetry_enable_get(struct ivpu_device *vdev) | |
| 170 | 126 | { |
| 171 | − vdev->hw->ops->reg_ipc_tx_set(vdev, vpu_addr); | |
| 172 | −}; | |
| 127 | + return ivpu_hw_btrs_telemetry_enable_get(vdev); | |
| 128 | +} | |
| 173 | 129 | |
| 174 | −static inline void ivpu_hw_irq_clear(struct ivpu_device *vdev) | |
| 130 | +static inline bool ivpu_hw_is_idle(struct ivpu_device *vdev) | |
| 175 | 131 | { |
| 176 | − vdev->hw->ops->irq_clear(vdev); | |
| 177 | −}; | |
| 132 | + return ivpu_hw_btrs_is_idle(vdev); | |
| 133 | +} | |
| 178 | 134 | |
| 179 | −static inline void ivpu_hw_irq_enable(struct ivpu_device *vdev) | |
| 135 | +static inline int ivpu_hw_wait_for_idle(struct ivpu_device *vdev) | |
| 180 | 136 | { |
| 181 | − vdev->hw->ops->irq_enable(vdev); | |
| 182 | −}; | |
| 137 | + return ivpu_hw_btrs_wait_for_idle(vdev); | |
| 138 | +} | |
| 183 | 139 | |
| 184 | −static inline void ivpu_hw_irq_disable(struct ivpu_device *vdev) | |
| 140 | +static inline void ivpu_hw_ipc_tx_set(struct ivpu_device *vdev, u32 vpu_addr) | |
| 185 | 141 | { |
| 186 | − vdev->hw->ops->irq_disable(vdev); | |
| 187 | −}; | |
| 142 | + ivpu_hw_ip_ipc_tx_set(vdev, vpu_addr); | |
| 143 | +} | |
| 188 | 144 | |
| 189 | −static inline void ivpu_hw_init_range(struct ivpu_addr_range *range, u64 start, u64 size) | |
| 145 | +static inline void ivpu_hw_db_set(struct ivpu_device *vdev, u32 db_id) | |
| 190 | 146 | { |
| 191 | − range->start = start; | |
| 192 | − range->end = start + size; | |
| 147 | + ivpu_hw_ip_db_set(vdev, db_id); | |
| 193 | 148 | } |
| 194 | 149 | |
| 195 | −static inline u64 ivpu_hw_range_size(const struct ivpu_addr_range *range) | |
| 150 | +static inline u32 ivpu_hw_ipc_rx_addr_get(struct ivpu_device *vdev) | |
| 196 | 151 | { |
| 197 | − return range->end - range->start; | |
| 152 | + return ivpu_hw_ip_ipc_rx_addr_get(vdev); | |
| 198 | 153 | } |
| 199 | 154 | |
| 200 | −static inline void ivpu_hw_diagnose_failure(struct ivpu_device *vdev) | |
| 155 | +static inline u32 ivpu_hw_ipc_rx_count_get(struct ivpu_device *vdev) | |
| 201 | 156 | { |
| 202 | − vdev->hw->ops->diagnose_failure(vdev); | |
| 157 | + return ivpu_hw_ip_ipc_rx_count_get(vdev); | |
| 203 | 158 | } |
| 204 | 159 | |
| 205 | 160 | #endif /* __IVPU_HW_H__ */ |
| @@ -1,1065 +0,0 @@ | ||
| 1 | −// SPDX-License-Identifier: GPL-2.0-only | |
| 2 | −/* | |
| 3 | − * Copyright (C) 2020-2024 Intel Corporation | |
| 4 | − */ | |
| 5 | − | |
| 6 | −#include "ivpu_drv.h" | |
| 7 | −#include "ivpu_fw.h" | |
| 8 | −#include "ivpu_hw_37xx_reg.h" | |
| 9 | −#include "ivpu_hw_reg_io.h" | |
| 10 | −#include "ivpu_hw.h" | |
| 11 | −#include "ivpu_ipc.h" | |
| 12 | −#include "ivpu_mmu.h" | |
| 13 | −#include "ivpu_pm.h" | |
| 14 | − | |
| 15 | −#define TILE_FUSE_ENABLE_BOTH 0x0 | |
| 16 | −#define TILE_SKU_BOTH 0x3630 | |
| 17 | − | |
| 18 | −/* Work point configuration values */ | |
| 19 | −#define CONFIG_1_TILE 0x01 | |
| 20 | −#define CONFIG_2_TILE 0x02 | |
| 21 | −#define PLL_RATIO_5_3 0x01 | |
| 22 | −#define PLL_RATIO_4_3 0x02 | |
| 23 | −#define WP_CONFIG(tile, ratio) (((tile) << 8) | (ratio)) | |
| 24 | −#define WP_CONFIG_1_TILE_5_3_RATIO WP_CONFIG(CONFIG_1_TILE, PLL_RATIO_5_3) | |
| 25 | −#define WP_CONFIG_1_TILE_4_3_RATIO WP_CONFIG(CONFIG_1_TILE, PLL_RATIO_4_3) | |
| 26 | −#define WP_CONFIG_2_TILE_5_3_RATIO WP_CONFIG(CONFIG_2_TILE, PLL_RATIO_5_3) | |
| 27 | −#define WP_CONFIG_2_TILE_4_3_RATIO WP_CONFIG(CONFIG_2_TILE, PLL_RATIO_4_3) | |
| 28 | −#define WP_CONFIG_0_TILE_PLL_OFF WP_CONFIG(0, 0) | |
| 29 | − | |
| 30 | −#define PLL_REF_CLK_FREQ (50 * 1000000) | |
| 31 | −#define PLL_SIMULATION_FREQ (10 * 1000000) | |
| 32 | −#define PLL_PROF_CLK_FREQ (38400 * 1000) | |
| 33 | −#define PLL_DEFAULT_EPP_VALUE 0x80 | |
| 34 | − | |
| 35 | −#define TIM_SAFE_ENABLE 0xf1d0dead | |
| 36 | −#define TIM_WATCHDOG_RESET_VALUE 0xffffffff | |
| 37 | − | |
| 38 | −#define TIMEOUT_US (150 * USEC_PER_MSEC) | |
| 39 | −#define PWR_ISLAND_STATUS_TIMEOUT_US (5 * USEC_PER_MSEC) | |
| 40 | −#define PLL_TIMEOUT_US (1500 * USEC_PER_MSEC) | |
| 41 | −#define IDLE_TIMEOUT_US (5 * USEC_PER_MSEC) | |
| 42 | − | |
| 43 | −#define ICB_0_IRQ_MASK ((REG_FLD(VPU_37XX_HOST_SS_ICB_STATUS_0, HOST_IPC_FIFO_INT)) | \ | |
| 44 | − (REG_FLD(VPU_37XX_HOST_SS_ICB_STATUS_0, MMU_IRQ_0_INT)) | \ | |
| 45 | − (REG_FLD(VPU_37XX_HOST_SS_ICB_STATUS_0, MMU_IRQ_1_INT)) | \ | |
| 46 | − (REG_FLD(VPU_37XX_HOST_SS_ICB_STATUS_0, MMU_IRQ_2_INT)) | \ | |
| 47 | − (REG_FLD(VPU_37XX_HOST_SS_ICB_STATUS_0, NOC_FIREWALL_INT)) | \ | |
| 48 | − (REG_FLD(VPU_37XX_HOST_SS_ICB_STATUS_0, CPU_INT_REDIRECT_0_INT)) | \ | |
| 49 | − (REG_FLD(VPU_37XX_HOST_SS_ICB_STATUS_0, CPU_INT_REDIRECT_1_INT))) | |
| 50 | − | |
| 51 | −#define ICB_1_IRQ_MASK ((REG_FLD(VPU_37XX_HOST_SS_ICB_STATUS_1, CPU_INT_REDIRECT_2_INT)) | \ | |
| 52 | − (REG_FLD(VPU_37XX_HOST_SS_ICB_STATUS_1, CPU_INT_REDIRECT_3_INT)) | \ | |
| 53 | − (REG_FLD(VPU_37XX_HOST_SS_ICB_STATUS_1, CPU_INT_REDIRECT_4_INT))) | |
| 54 | − | |
| 55 | −#define ICB_0_1_IRQ_MASK ((((u64)ICB_1_IRQ_MASK) << 32) | ICB_0_IRQ_MASK) | |
| 56 | − | |
| 57 | −#define BUTTRESS_IRQ_MASK ((REG_FLD(VPU_37XX_BUTTRESS_INTERRUPT_STAT, ATS_ERR)) | \ | |
| 58 | − (REG_FLD(VPU_37XX_BUTTRESS_INTERRUPT_STAT, UFI_ERR))) | |
| 59 | − | |
| 60 | −#define BUTTRESS_ALL_IRQ_MASK (BUTTRESS_IRQ_MASK | \ | |
| 61 | − (REG_FLD(VPU_37XX_BUTTRESS_INTERRUPT_STAT, FREQ_CHANGE))) | |
| 62 | − | |
| 63 | −#define BUTTRESS_IRQ_ENABLE_MASK ((u32)~BUTTRESS_IRQ_MASK) | |
| 64 | −#define BUTTRESS_IRQ_DISABLE_MASK ((u32)-1) | |
| 65 | − | |
| 66 | −#define ITF_FIREWALL_VIOLATION_MASK ((REG_FLD(VPU_37XX_HOST_SS_FW_SOC_IRQ_EN, CSS_ROM_CMX)) | \ | |
| 67 | − (REG_FLD(VPU_37XX_HOST_SS_FW_SOC_IRQ_EN, CSS_DBG)) | \ | |
| 68 | − (REG_FLD(VPU_37XX_HOST_SS_FW_SOC_IRQ_EN, CSS_CTRL)) | \ | |
| 69 | − (REG_FLD(VPU_37XX_HOST_SS_FW_SOC_IRQ_EN, DEC400)) | \ | |
| 70 | − (REG_FLD(VPU_37XX_HOST_SS_FW_SOC_IRQ_EN, MSS_NCE)) | \ | |
| 71 | − (REG_FLD(VPU_37XX_HOST_SS_FW_SOC_IRQ_EN, MSS_MBI)) | \ | |
| 72 | − (REG_FLD(VPU_37XX_HOST_SS_FW_SOC_IRQ_EN, MSS_MBI_CMX))) | |
| 73 | − | |
| 74 | −static void ivpu_hw_wa_init(struct ivpu_device *vdev) | |
| 75 | −{ | |
| 76 | − vdev->wa.punit_disabled = false; | |
| 77 | − vdev->wa.clear_runtime_mem = false; | |
| 78 | − | |
| 79 | − REGB_WR32(VPU_37XX_BUTTRESS_INTERRUPT_STAT, BUTTRESS_ALL_IRQ_MASK); | |
| 80 | − if (REGB_RD32(VPU_37XX_BUTTRESS_INTERRUPT_STAT) == BUTTRESS_ALL_IRQ_MASK) { | |
| 81 | − /* Writing 1s does not clear the interrupt status register */ | |
| 82 | − vdev->wa.interrupt_clear_with_0 = true; | |
| 83 | − REGB_WR32(VPU_37XX_BUTTRESS_INTERRUPT_STAT, 0x0); | |
| 84 | − } | |
| 85 | − | |
| 86 | − IVPU_PRINT_WA(punit_disabled); | |
| 87 | − IVPU_PRINT_WA(clear_runtime_mem); | |
| 88 | − IVPU_PRINT_WA(interrupt_clear_with_0); | |
| 89 | −} | |
| 90 | − | |
| 91 | −static void ivpu_hw_timeouts_init(struct ivpu_device *vdev) | |
| 92 | −{ | |
| 93 | − vdev->timeout.boot = 1000; | |
| 94 | − vdev->timeout.jsm = 500; | |
| 95 | − vdev->timeout.tdr = 2000; | |
| 96 | − vdev->timeout.reschedule_suspend = 10; | |
| 97 | − vdev->timeout.autosuspend = 10; | |
| 98 | − vdev->timeout.d0i3_entry_msg = 5; | |
| 99 | −} | |
| 100 | − | |
| 101 | −static int ivpu_pll_wait_for_cmd_send(struct ivpu_device *vdev) | |
| 102 | −{ | |
| 103 | − return REGB_POLL_FLD(VPU_37XX_BUTTRESS_WP_REQ_CMD, SEND, 0, PLL_TIMEOUT_US); | |
| 104 | −} | |
| 105 | − | |
| 106 | −/* Send KMD initiated workpoint change */ | |
| 107 | −static int ivpu_pll_cmd_send(struct ivpu_device *vdev, u16 min_ratio, u16 max_ratio, | |
| 108 | − u16 target_ratio, u16 config) | |
| 109 | −{ | |
| 110 | − int ret; | |
| 111 | − u32 val; | |
| 112 | − | |
| 113 | − ret = ivpu_pll_wait_for_cmd_send(vdev); | |
| 114 | − if (ret) { | |
| 115 | − ivpu_err(vdev, "Failed to sync before WP request: %d\n", ret); | |
| 116 | − return ret; | |
| 117 | − } | |
| 118 | − | |
| 119 | − val = REGB_RD32(VPU_37XX_BUTTRESS_WP_REQ_PAYLOAD0); | |
| 120 | − val = REG_SET_FLD_NUM(VPU_37XX_BUTTRESS_WP_REQ_PAYLOAD0, MIN_RATIO, min_ratio, val); | |
| 121 | − val = REG_SET_FLD_NUM(VPU_37XX_BUTTRESS_WP_REQ_PAYLOAD0, MAX_RATIO, max_ratio, val); | |
| 122 | − REGB_WR32(VPU_37XX_BUTTRESS_WP_REQ_PAYLOAD0, val); | |
| 123 | − | |
| 124 | − val = REGB_RD32(VPU_37XX_BUTTRESS_WP_REQ_PAYLOAD1); | |
| 125 | − val = REG_SET_FLD_NUM(VPU_37XX_BUTTRESS_WP_REQ_PAYLOAD1, TARGET_RATIO, target_ratio, val); | |
| 126 | − val = REG_SET_FLD_NUM(VPU_37XX_BUTTRESS_WP_REQ_PAYLOAD1, EPP, PLL_DEFAULT_EPP_VALUE, val); | |
| 127 | − REGB_WR32(VPU_37XX_BUTTRESS_WP_REQ_PAYLOAD1, val); | |
| 128 | − | |
| 129 | − val = REGB_RD32(VPU_37XX_BUTTRESS_WP_REQ_PAYLOAD2); | |
| 130 | − val = REG_SET_FLD_NUM(VPU_37XX_BUTTRESS_WP_REQ_PAYLOAD2, CONFIG, config, val); | |
| 131 | − REGB_WR32(VPU_37XX_BUTTRESS_WP_REQ_PAYLOAD2, val); | |
| 132 | − | |
| 133 | − val = REGB_RD32(VPU_37XX_BUTTRESS_WP_REQ_CMD); | |
| 134 | − val = REG_SET_FLD(VPU_37XX_BUTTRESS_WP_REQ_CMD, SEND, val); | |
| 135 | − REGB_WR32(VPU_37XX_BUTTRESS_WP_REQ_CMD, val); | |
| 136 | − | |
| 137 | − ret = ivpu_pll_wait_for_cmd_send(vdev); | |
| 138 | − if (ret) | |
| 139 | − ivpu_err(vdev, "Failed to sync after WP request: %d\n", ret); | |
| 140 | − | |
| 141 | − return ret; | |
| 142 | −} | |
| 143 | − | |
| 144 | −static int ivpu_pll_wait_for_lock(struct ivpu_device *vdev, bool enable) | |
| 145 | −{ | |
| 146 | − u32 exp_val = enable ? 0x1 : 0x0; | |
| 147 | − | |
| 148 | − if (IVPU_WA(punit_disabled)) | |
| 149 | − return 0; | |
| 150 | − | |
| 151 | − return REGB_POLL_FLD(VPU_37XX_BUTTRESS_PLL_STATUS, LOCK, exp_val, PLL_TIMEOUT_US); | |
| 152 | −} | |
| 153 | − | |
| 154 | −static int ivpu_pll_wait_for_status_ready(struct ivpu_device *vdev) | |
| 155 | −{ | |
| 156 | − if (IVPU_WA(punit_disabled)) | |
| 157 | − return 0; | |
| 158 | − | |
| 159 | − return REGB_POLL_FLD(VPU_37XX_BUTTRESS_VPU_STATUS, READY, 1, PLL_TIMEOUT_US); | |
| 160 | −} | |
| 161 | − | |
| 162 | −static void ivpu_pll_init_frequency_ratios(struct ivpu_device *vdev) | |
| 163 | −{ | |
| 164 | − struct ivpu_hw_info *hw = vdev->hw; | |
| 165 | − u8 fuse_min_ratio, fuse_max_ratio, fuse_pn_ratio; | |
| 166 | − u32 fmin_fuse, fmax_fuse; | |
| 167 | − | |
| 168 | − fmin_fuse = REGB_RD32(VPU_37XX_BUTTRESS_FMIN_FUSE); | |
| 169 | − fuse_min_ratio = REG_GET_FLD(VPU_37XX_BUTTRESS_FMIN_FUSE, MIN_RATIO, fmin_fuse); | |
| 170 | − fuse_pn_ratio = REG_GET_FLD(VPU_37XX_BUTTRESS_FMIN_FUSE, PN_RATIO, fmin_fuse); | |
| 171 | − | |
| 172 | − fmax_fuse = REGB_RD32(VPU_37XX_BUTTRESS_FMAX_FUSE); | |
| 173 | − fuse_max_ratio = REG_GET_FLD(VPU_37XX_BUTTRESS_FMAX_FUSE, MAX_RATIO, fmax_fuse); | |
| 174 | − | |
| 175 | − hw->pll.min_ratio = clamp_t(u8, ivpu_pll_min_ratio, fuse_min_ratio, fuse_max_ratio); | |
| 176 | − hw->pll.max_ratio = clamp_t(u8, ivpu_pll_max_ratio, hw->pll.min_ratio, fuse_max_ratio); | |
| 177 | − hw->pll.pn_ratio = clamp_t(u8, fuse_pn_ratio, hw->pll.min_ratio, hw->pll.max_ratio); | |
| 178 | −} | |
| 179 | − | |
| 180 | −static int ivpu_hw_37xx_wait_for_vpuip_bar(struct ivpu_device *vdev) | |
| 181 | −{ | |
| 182 | − return REGV_POLL_FLD(VPU_37XX_HOST_SS_CPR_RST_CLR, AON, 0, 100); | |
| 183 | −} | |
| 184 | − | |
| 185 | −static int ivpu_pll_drive(struct ivpu_device *vdev, bool enable) | |
| 186 | −{ | |
| 187 | − struct ivpu_hw_info *hw = vdev->hw; | |
| 188 | − u16 target_ratio; | |
| 189 | − u16 config; | |
| 190 | − int ret; | |
| 191 | − | |
| 192 | − if (IVPU_WA(punit_disabled)) { | |
| 193 | − ivpu_dbg(vdev, PM, "Skipping PLL request\n"); | |
| 194 | − return 0; | |
| 195 | − } | |
| 196 | − | |
| 197 | − if (enable) { | |
| 198 | − target_ratio = hw->pll.pn_ratio; | |
| 199 | − config = hw->config; | |
| 200 | − } else { | |
| 201 | − target_ratio = 0; | |
| 202 | − config = 0; | |
| 203 | − } | |
| 204 | − | |
| 205 | − ivpu_dbg(vdev, PM, "PLL workpoint request: config 0x%04x pll ratio 0x%x\n", | |
| 206 | − config, target_ratio); | |
| 207 | − | |
| 208 | − ret = ivpu_pll_cmd_send(vdev, hw->pll.min_ratio, hw->pll.max_ratio, target_ratio, config); | |
| 209 | − if (ret) { | |
| 210 | − ivpu_err(vdev, "Failed to send PLL workpoint request: %d\n", ret); | |
| 211 | − return ret; | |
| 212 | − } | |
| 213 | − | |
| 214 | − ret = ivpu_pll_wait_for_lock(vdev, enable); | |
| 215 | − if (ret) { | |
| 216 | − ivpu_err(vdev, "Timed out waiting for PLL lock\n"); | |
| 217 | − return ret; | |
| 218 | − } | |
| 219 | − | |
| 220 | − if (enable) { | |
| 221 | − ret = ivpu_pll_wait_for_status_ready(vdev); | |
| 222 | − if (ret) { | |
| 223 | − ivpu_err(vdev, "Timed out waiting for PLL ready status\n"); | |
| 224 | − return ret; | |
| 225 | − } | |
| 226 | − | |
| 227 | − ret = ivpu_hw_37xx_wait_for_vpuip_bar(vdev); | |
| 228 | − if (ret) { | |
| 229 | − ivpu_err(vdev, "Timed out waiting for NPU IP bar\n"); | |
| 230 | − return ret; | |
| 231 | − } | |
| 232 | − } | |
| 233 | − | |
| 234 | − return 0; | |
| 235 | −} | |
| 236 | − | |
| 237 | −static int ivpu_pll_enable(struct ivpu_device *vdev) | |
| 238 | −{ | |
| 239 | − return ivpu_pll_drive(vdev, true); | |
| 240 | −} | |
| 241 | − | |
| 242 | −static int ivpu_pll_disable(struct ivpu_device *vdev) | |
| 243 | −{ | |
| 244 | − return ivpu_pll_drive(vdev, false); | |
| 245 | −} | |
| 246 | − | |
| 247 | −static void ivpu_boot_host_ss_rst_clr_assert(struct ivpu_device *vdev) | |
| 248 | −{ | |
| 249 | − u32 val = 0; | |
| 250 | − | |
| 251 | − val = REG_SET_FLD(VPU_37XX_HOST_SS_CPR_RST_CLR, TOP_NOC, val); | |
| 252 | − val = REG_SET_FLD(VPU_37XX_HOST_SS_CPR_RST_CLR, DSS_MAS, val); | |
| 253 | − val = REG_SET_FLD(VPU_37XX_HOST_SS_CPR_RST_CLR, MSS_MAS, val); | |
| 254 | − | |
| 255 | − REGV_WR32(VPU_37XX_HOST_SS_CPR_RST_CLR, val); | |
| 256 | −} | |
| 257 | − | |
| 258 | −static void ivpu_boot_host_ss_rst_drive(struct ivpu_device *vdev, bool enable) | |
| 259 | −{ | |
| 260 | − u32 val = REGV_RD32(VPU_37XX_HOST_SS_CPR_RST_SET); | |
| 261 | − | |
| 262 | − if (enable) { | |
| 263 | − val = REG_SET_FLD(VPU_37XX_HOST_SS_CPR_RST_SET, TOP_NOC, val); | |
| 264 | − val = REG_SET_FLD(VPU_37XX_HOST_SS_CPR_RST_SET, DSS_MAS, val); | |
| 265 | − val = REG_SET_FLD(VPU_37XX_HOST_SS_CPR_RST_SET, MSS_MAS, val); | |
| 266 | − } else { | |
| 267 | − val = REG_CLR_FLD(VPU_37XX_HOST_SS_CPR_RST_SET, TOP_NOC, val); | |
| 268 | − val = REG_CLR_FLD(VPU_37XX_HOST_SS_CPR_RST_SET, DSS_MAS, val); | |
| 269 | − val = REG_CLR_FLD(VPU_37XX_HOST_SS_CPR_RST_SET, MSS_MAS, val); | |
| 270 | − } | |
| 271 | − | |
| 272 | − REGV_WR32(VPU_37XX_HOST_SS_CPR_RST_SET, val); | |
| 273 | −} | |
| 274 | − | |
| 275 | −static void ivpu_boot_host_ss_clk_drive(struct ivpu_device *vdev, bool enable) | |
| 276 | −{ | |
| 277 | − u32 val = REGV_RD32(VPU_37XX_HOST_SS_CPR_CLK_SET); | |
| 278 | − | |
| 279 | − if (enable) { | |
| 280 | − val = REG_SET_FLD(VPU_37XX_HOST_SS_CPR_CLK_SET, TOP_NOC, val); | |
| 281 | − val = REG_SET_FLD(VPU_37XX_HOST_SS_CPR_CLK_SET, DSS_MAS, val); | |
| 282 | − val = REG_SET_FLD(VPU_37XX_HOST_SS_CPR_CLK_SET, MSS_MAS, val); | |
| 283 | − } else { | |
| 284 | − val = REG_CLR_FLD(VPU_37XX_HOST_SS_CPR_CLK_SET, TOP_NOC, val); | |
| 285 | − val = REG_CLR_FLD(VPU_37XX_HOST_SS_CPR_CLK_SET, DSS_MAS, val); | |
| 286 | − val = REG_CLR_FLD(VPU_37XX_HOST_SS_CPR_CLK_SET, MSS_MAS, val); | |
| 287 | − } | |
| 288 | − | |
| 289 | − REGV_WR32(VPU_37XX_HOST_SS_CPR_CLK_SET, val); | |
| 290 | −} | |
| 291 | − | |
| 292 | −static int ivpu_boot_noc_qreqn_check(struct ivpu_device *vdev, u32 exp_val) | |
| 293 | −{ | |
| 294 | − u32 val = REGV_RD32(VPU_37XX_HOST_SS_NOC_QREQN); | |
| 295 | − | |
| 296 | − if (!REG_TEST_FLD_NUM(VPU_37XX_HOST_SS_NOC_QREQN, TOP_SOCMMIO, exp_val, val)) | |
| 297 | − return -EIO; | |
| 298 | − | |
| 299 | − return 0; | |
| 300 | −} | |
| 301 | − | |
| 302 | −static int ivpu_boot_noc_qacceptn_check(struct ivpu_device *vdev, u32 exp_val) | |
| 303 | −{ | |
| 304 | − u32 val = REGV_RD32(VPU_37XX_HOST_SS_NOC_QACCEPTN); | |
| 305 | − | |
| 306 | − if (!REG_TEST_FLD_NUM(VPU_37XX_HOST_SS_NOC_QACCEPTN, TOP_SOCMMIO, exp_val, val)) | |
| 307 | − return -EIO; | |
| 308 | − | |
| 309 | − return 0; | |
| 310 | −} | |
| 311 | − | |
| 312 | −static int ivpu_boot_noc_qdeny_check(struct ivpu_device *vdev, u32 exp_val) | |
| 313 | −{ | |
| 314 | − u32 val = REGV_RD32(VPU_37XX_HOST_SS_NOC_QDENY); | |
| 315 | − | |
| 316 | − if (!REG_TEST_FLD_NUM(VPU_37XX_HOST_SS_NOC_QDENY, TOP_SOCMMIO, exp_val, val)) | |
| 317 | − return -EIO; | |
| 318 | − | |
| 319 | − return 0; | |
| 320 | −} | |
| 321 | − | |
| 322 | −static int ivpu_boot_top_noc_qrenqn_check(struct ivpu_device *vdev, u32 exp_val) | |
| 323 | −{ | |
| 324 | − u32 val = REGV_RD32(VPU_37XX_TOP_NOC_QREQN); | |
| 325 | − | |
| 326 | − if (!REG_TEST_FLD_NUM(VPU_37XX_TOP_NOC_QREQN, CPU_CTRL, exp_val, val) || | |
| 327 | − !REG_TEST_FLD_NUM(VPU_37XX_TOP_NOC_QREQN, HOSTIF_L2CACHE, exp_val, val)) | |
| 328 | − return -EIO; | |
| 329 | − | |
| 330 | − return 0; | |
| 331 | −} | |
| 332 | − | |
| 333 | −static int ivpu_boot_top_noc_qacceptn_check(struct ivpu_device *vdev, u32 exp_val) | |
| 334 | −{ | |
| 335 | − u32 val = REGV_RD32(VPU_37XX_TOP_NOC_QACCEPTN); | |
| 336 | − | |
| 337 | − if (!REG_TEST_FLD_NUM(VPU_37XX_TOP_NOC_QACCEPTN, CPU_CTRL, exp_val, val) || | |
| 338 | − !REG_TEST_FLD_NUM(VPU_37XX_TOP_NOC_QACCEPTN, HOSTIF_L2CACHE, exp_val, val)) | |
| 339 | − return -EIO; | |
| 340 | − | |
| 341 | − return 0; | |
| 342 | −} | |
| 343 | − | |
| 344 | −static int ivpu_boot_top_noc_qdeny_check(struct ivpu_device *vdev, u32 exp_val) | |
| 345 | −{ | |
| 346 | − u32 val = REGV_RD32(VPU_37XX_TOP_NOC_QDENY); | |
| 347 | − | |
| 348 | − if (!REG_TEST_FLD_NUM(VPU_37XX_TOP_NOC_QDENY, CPU_CTRL, exp_val, val) || | |
| 349 | − !REG_TEST_FLD_NUM(VPU_37XX_TOP_NOC_QDENY, HOSTIF_L2CACHE, exp_val, val)) | |
| 350 | − return -EIO; | |
| 351 | − | |
| 352 | − return 0; | |
| 353 | −} | |
| 354 | − | |
| 355 | −static int ivpu_boot_host_ss_configure(struct ivpu_device *vdev) | |
| 356 | −{ | |
| 357 | − ivpu_boot_host_ss_rst_clr_assert(vdev); | |
| 358 | − | |
| 359 | − return ivpu_boot_noc_qreqn_check(vdev, 0x0); | |
| 360 | −} | |
| 361 | − | |
| 362 | −static void ivpu_boot_vpu_idle_gen_disable(struct ivpu_device *vdev) | |
| 363 | −{ | |
| 364 | − REGV_WR32(VPU_37XX_HOST_SS_AON_VPU_IDLE_GEN, 0x0); | |
| 365 | −} | |
| 366 | − | |
| 367 | −static int ivpu_boot_host_ss_axi_drive(struct ivpu_device *vdev, bool enable) | |
| 368 | −{ | |
| 369 | − int ret; | |
| 370 | − u32 val; | |
| 371 | − | |
| 372 | − val = REGV_RD32(VPU_37XX_HOST_SS_NOC_QREQN); | |
| 373 | − if (enable) | |
| 374 | − val = REG_SET_FLD(VPU_37XX_HOST_SS_NOC_QREQN, TOP_SOCMMIO, val); | |
| 375 | − else | |
| 376 | − val = REG_CLR_FLD(VPU_37XX_HOST_SS_NOC_QREQN, TOP_SOCMMIO, val); | |
| 377 | − REGV_WR32(VPU_37XX_HOST_SS_NOC_QREQN, val); | |
| 378 | − | |
| 379 | − ret = ivpu_boot_noc_qacceptn_check(vdev, enable ? 0x1 : 0x0); | |
| 380 | − if (ret) { | |
| 381 | − ivpu_err(vdev, "Failed qacceptn check: %d\n", ret); | |
| 382 | − return ret; | |
| 383 | − } | |
| 384 | − | |
| 385 | − ret = ivpu_boot_noc_qdeny_check(vdev, 0x0); | |
| 386 | − if (ret) | |
| 387 | − ivpu_err(vdev, "Failed qdeny check: %d\n", ret); | |
| 388 | − | |
| 389 | − return ret; | |
| 390 | −} | |
| 391 | − | |
| 392 | −static int ivpu_boot_host_ss_axi_enable(struct ivpu_device *vdev) | |
| 393 | −{ | |
| 394 | − return ivpu_boot_host_ss_axi_drive(vdev, true); | |
| 395 | −} | |
| 396 | − | |
| 397 | −static int ivpu_boot_host_ss_top_noc_drive(struct ivpu_device *vdev, bool enable) | |
| 398 | −{ | |
| 399 | − int ret; | |
| 400 | − u32 val; | |
| 401 | − | |
| 402 | − val = REGV_RD32(VPU_37XX_TOP_NOC_QREQN); | |
| 403 | − if (enable) { | |
| 404 | − val = REG_SET_FLD(VPU_37XX_TOP_NOC_QREQN, CPU_CTRL, val); | |
| 405 | − val = REG_SET_FLD(VPU_37XX_TOP_NOC_QREQN, HOSTIF_L2CACHE, val); | |
| 406 | − } else { | |
| 407 | − val = REG_CLR_FLD(VPU_37XX_TOP_NOC_QREQN, CPU_CTRL, val); | |
| 408 | − val = REG_CLR_FLD(VPU_37XX_TOP_NOC_QREQN, HOSTIF_L2CACHE, val); | |
| 409 | − } | |
| 410 | − REGV_WR32(VPU_37XX_TOP_NOC_QREQN, val); | |
| 411 | − | |
| 412 | − ret = ivpu_boot_top_noc_qacceptn_check(vdev, enable ? 0x1 : 0x0); | |
| 413 | − if (ret) { | |
| 414 | − ivpu_err(vdev, "Failed qacceptn check: %d\n", ret); | |
| 415 | − return ret; | |
| 416 | − } | |
| 417 | − | |
| 418 | − ret = ivpu_boot_top_noc_qdeny_check(vdev, 0x0); | |
| 419 | − if (ret) | |
| 420 | − ivpu_err(vdev, "Failed qdeny check: %d\n", ret); | |
| 421 | − | |
| 422 | − return ret; | |
| 423 | −} | |
| 424 | − | |
| 425 | −static int ivpu_boot_host_ss_top_noc_enable(struct ivpu_device *vdev) | |
| 426 | −{ | |
| 427 | − return ivpu_boot_host_ss_top_noc_drive(vdev, true); | |
| 428 | −} | |
| 429 | − | |
| 430 | −static void ivpu_boot_pwr_island_trickle_drive(struct ivpu_device *vdev, bool enable) | |
| 431 | −{ | |
| 432 | − u32 val = REGV_RD32(VPU_37XX_HOST_SS_AON_PWR_ISLAND_TRICKLE_EN0); | |
| 433 | − | |
| 434 | − if (enable) | |
| 435 | − val = REG_SET_FLD(VPU_37XX_HOST_SS_AON_PWR_ISLAND_TRICKLE_EN0, MSS_CPU, val); | |
| 436 | − else | |
| 437 | − val = REG_CLR_FLD(VPU_37XX_HOST_SS_AON_PWR_ISLAND_TRICKLE_EN0, MSS_CPU, val); | |
| 438 | − | |
| 439 | − REGV_WR32(VPU_37XX_HOST_SS_AON_PWR_ISLAND_TRICKLE_EN0, val); | |
| 440 | −} | |
| 441 | − | |
| 442 | −static void ivpu_boot_pwr_island_drive(struct ivpu_device *vdev, bool enable) | |
| 443 | −{ | |
| 444 | − u32 val = REGV_RD32(VPU_37XX_HOST_SS_AON_PWR_ISLAND_EN0); | |
| 445 | − | |
| 446 | − if (enable) | |
| 447 | − val = REG_SET_FLD(VPU_37XX_HOST_SS_AON_PWR_ISLAND_EN0, MSS_CPU, val); | |
| 448 | − else | |
| 449 | − val = REG_CLR_FLD(VPU_37XX_HOST_SS_AON_PWR_ISLAND_EN0, MSS_CPU, val); | |
| 450 | − | |
| 451 | − REGV_WR32(VPU_37XX_HOST_SS_AON_PWR_ISLAND_EN0, val); | |
| 452 | −} | |
| 453 | − | |
| 454 | −static int ivpu_boot_wait_for_pwr_island_status(struct ivpu_device *vdev, u32 exp_val) | |
| 455 | −{ | |
| 456 | − return REGV_POLL_FLD(VPU_37XX_HOST_SS_AON_PWR_ISLAND_STATUS0, MSS_CPU, | |
| 457 | − exp_val, PWR_ISLAND_STATUS_TIMEOUT_US); | |
| 458 | −} | |
| 459 | − | |
| 460 | −static void ivpu_boot_pwr_island_isolation_drive(struct ivpu_device *vdev, bool enable) | |
| 461 | −{ | |
| 462 | − u32 val = REGV_RD32(VPU_37XX_HOST_SS_AON_PWR_ISO_EN0); | |
| 463 | − | |
| 464 | − if (enable) | |
| 465 | − val = REG_SET_FLD(VPU_37XX_HOST_SS_AON_PWR_ISO_EN0, MSS_CPU, val); | |
| 466 | − else | |
| 467 | − val = REG_CLR_FLD(VPU_37XX_HOST_SS_AON_PWR_ISO_EN0, MSS_CPU, val); | |
| 468 | − | |
| 469 | − REGV_WR32(VPU_37XX_HOST_SS_AON_PWR_ISO_EN0, val); | |
| 470 | −} | |
| 471 | − | |
| 472 | −static void ivpu_boot_dpu_active_drive(struct ivpu_device *vdev, bool enable) | |
| 473 | −{ | |
| 474 | − u32 val = REGV_RD32(VPU_37XX_HOST_SS_AON_DPU_ACTIVE); | |
| 475 | − | |
| 476 | − if (enable) | |
| 477 | − val = REG_SET_FLD(VPU_37XX_HOST_SS_AON_DPU_ACTIVE, DPU_ACTIVE, val); | |
| 478 | − else | |
| 479 | − val = REG_CLR_FLD(VPU_37XX_HOST_SS_AON_DPU_ACTIVE, DPU_ACTIVE, val); | |
| 480 | − | |
| 481 | − REGV_WR32(VPU_37XX_HOST_SS_AON_DPU_ACTIVE, val); | |
| 482 | −} | |
| 483 | − | |
| 484 | −static int ivpu_boot_pwr_domain_enable(struct ivpu_device *vdev) | |
| 485 | −{ | |
| 486 | − int ret; | |
| 487 | − | |
| 488 | − ivpu_boot_pwr_island_trickle_drive(vdev, true); | |
| 489 | − ivpu_boot_pwr_island_drive(vdev, true); | |
| 490 | − | |
| 491 | − ret = ivpu_boot_wait_for_pwr_island_status(vdev, 0x1); | |
| 492 | − if (ret) { | |
| 493 | − ivpu_err(vdev, "Timed out waiting for power island status\n"); | |
| 494 | − return ret; | |
| 495 | − } | |
| 496 | − | |
| 497 | − ret = ivpu_boot_top_noc_qrenqn_check(vdev, 0x0); | |
| 498 | − if (ret) { | |
| 499 | − ivpu_err(vdev, "Failed qrenqn check %d\n", ret); | |
| 500 | − return ret; | |
| 501 | − } | |
| 502 | − | |
| 503 | − ivpu_boot_host_ss_clk_drive(vdev, true); | |
| 504 | − ivpu_boot_pwr_island_isolation_drive(vdev, false); | |
| 505 | − ivpu_boot_host_ss_rst_drive(vdev, true); | |
| 506 | − ivpu_boot_dpu_active_drive(vdev, true); | |
| 507 | − | |
| 508 | − return ret; | |
| 509 | −} | |
| 510 | − | |
| 511 | −static void ivpu_boot_no_snoop_enable(struct ivpu_device *vdev) | |
| 512 | −{ | |
| 513 | − u32 val = REGV_RD32(VPU_37XX_HOST_IF_TCU_PTW_OVERRIDES); | |
| 514 | − | |
| 515 | − val = REG_SET_FLD(VPU_37XX_HOST_IF_TCU_PTW_OVERRIDES, NOSNOOP_OVERRIDE_EN, val); | |
| 516 | − val = REG_CLR_FLD(VPU_37XX_HOST_IF_TCU_PTW_OVERRIDES, AW_NOSNOOP_OVERRIDE, val); | |
| 517 | − val = REG_SET_FLD(VPU_37XX_HOST_IF_TCU_PTW_OVERRIDES, AR_NOSNOOP_OVERRIDE, val); | |
| 518 | − | |
| 519 | − REGV_WR32(VPU_37XX_HOST_IF_TCU_PTW_OVERRIDES, val); | |
| 520 | −} | |
| 521 | − | |
| 522 | −static void ivpu_boot_tbu_mmu_enable(struct ivpu_device *vdev) | |
| 523 | −{ | |
| 524 | − u32 val = REGV_RD32(VPU_37XX_HOST_IF_TBU_MMUSSIDV); | |
| 525 | − | |
| 526 | − val = REG_SET_FLD(VPU_37XX_HOST_IF_TBU_MMUSSIDV, TBU0_AWMMUSSIDV, val); | |
| 527 | − val = REG_SET_FLD(VPU_37XX_HOST_IF_TBU_MMUSSIDV, TBU0_ARMMUSSIDV, val); | |
| 528 | − val = REG_SET_FLD(VPU_37XX_HOST_IF_TBU_MMUSSIDV, TBU2_AWMMUSSIDV, val); | |
| 529 | − val = REG_SET_FLD(VPU_37XX_HOST_IF_TBU_MMUSSIDV, TBU2_ARMMUSSIDV, val); | |
| 530 | − | |
| 531 | − REGV_WR32(VPU_37XX_HOST_IF_TBU_MMUSSIDV, val); | |
| 532 | −} | |
| 533 | − | |
| 534 | −static void ivpu_boot_soc_cpu_boot(struct ivpu_device *vdev) | |
| 535 | −{ | |
| 536 | − u32 val; | |
| 537 | − | |
| 538 | − val = REGV_RD32(VPU_37XX_CPU_SS_MSSCPU_CPR_LEON_RT_VEC); | |
| 539 | − val = REG_SET_FLD(VPU_37XX_CPU_SS_MSSCPU_CPR_LEON_RT_VEC, IRQI_RSTRUN0, val); | |
| 540 | − | |
| 541 | − val = REG_CLR_FLD(VPU_37XX_CPU_SS_MSSCPU_CPR_LEON_RT_VEC, IRQI_RSTVEC, val); | |
| 542 | − REGV_WR32(VPU_37XX_CPU_SS_MSSCPU_CPR_LEON_RT_VEC, val); | |
| 543 | − | |
| 544 | − val = REG_SET_FLD(VPU_37XX_CPU_SS_MSSCPU_CPR_LEON_RT_VEC, IRQI_RESUME0, val); | |
| 545 | − REGV_WR32(VPU_37XX_CPU_SS_MSSCPU_CPR_LEON_RT_VEC, val); | |
| 546 | − | |
| 547 | − val = REG_CLR_FLD(VPU_37XX_CPU_SS_MSSCPU_CPR_LEON_RT_VEC, IRQI_RESUME0, val); | |
| 548 | − REGV_WR32(VPU_37XX_CPU_SS_MSSCPU_CPR_LEON_RT_VEC, val); | |
| 549 | − | |
| 550 | − val = vdev->fw->entry_point >> 9; | |
| 551 | − REGV_WR32(VPU_37XX_HOST_SS_LOADING_ADDRESS_LO, val); | |
| 552 | − | |
| 553 | − val = REG_SET_FLD(VPU_37XX_HOST_SS_LOADING_ADDRESS_LO, DONE, val); | |
| 554 | − REGV_WR32(VPU_37XX_HOST_SS_LOADING_ADDRESS_LO, val); | |
| 555 | − | |
| 556 | − ivpu_dbg(vdev, PM, "Booting firmware, mode: %s\n", | |
| 557 | − vdev->fw->entry_point == vdev->fw->cold_boot_entry_point ? "cold boot" : "resume"); | |
| 558 | −} | |
| 559 | − | |
| 560 | −static int ivpu_boot_d0i3_drive(struct ivpu_device *vdev, bool enable) | |
| 561 | −{ | |
| 562 | − int ret; | |
| 563 | − u32 val; | |
| 564 | − | |
| 565 | − ret = REGB_POLL_FLD(VPU_37XX_BUTTRESS_VPU_D0I3_CONTROL, INPROGRESS, 0, TIMEOUT_US); | |
| 566 | − if (ret) { | |
| 567 | − ivpu_err(vdev, "Failed to sync before D0i3 transition: %d\n", ret); | |
| 568 | − return ret; | |
| 569 | − } | |
| 570 | − | |
| 571 | − val = REGB_RD32(VPU_37XX_BUTTRESS_VPU_D0I3_CONTROL); | |
| 572 | − if (enable) | |
| 573 | − val = REG_SET_FLD(VPU_37XX_BUTTRESS_VPU_D0I3_CONTROL, I3, val); | |
| 574 | − else | |
| 575 | − val = REG_CLR_FLD(VPU_37XX_BUTTRESS_VPU_D0I3_CONTROL, I3, val); | |
| 576 | − REGB_WR32(VPU_37XX_BUTTRESS_VPU_D0I3_CONTROL, val); | |
| 577 | − | |
| 578 | − ret = REGB_POLL_FLD(VPU_37XX_BUTTRESS_VPU_D0I3_CONTROL, INPROGRESS, 0, TIMEOUT_US); | |
| 579 | − if (ret) | |
| 580 | − ivpu_err(vdev, "Failed to sync after D0i3 transition: %d\n", ret); | |
| 581 | − | |
| 582 | − return ret; | |
| 583 | −} | |
| 584 | − | |
| 585 | −static int ivpu_hw_37xx_info_init(struct ivpu_device *vdev) | |
| 586 | −{ | |
| 587 | − struct ivpu_hw_info *hw = vdev->hw; | |
| 588 | − | |
| 589 | − hw->tile_fuse = TILE_FUSE_ENABLE_BOTH; | |
| 590 | − hw->sku = TILE_SKU_BOTH; | |
| 591 | − hw->config = WP_CONFIG_2_TILE_4_3_RATIO; | |
| 592 | − | |
| 593 | − ivpu_pll_init_frequency_ratios(vdev); | |
| 594 | − | |
| 595 | − ivpu_hw_init_range(&hw->ranges.global, 0x80000000, SZ_512M); | |
| 596 | − ivpu_hw_init_range(&hw->ranges.user, 0xc0000000, 255 * SZ_1M); | |
| 597 | − ivpu_hw_init_range(&hw->ranges.shave, 0x180000000, SZ_2G); | |
| 598 | − ivpu_hw_init_range(&hw->ranges.dma, 0x200000000, SZ_8G); | |
| 599 | − | |
| 600 | − vdev->platform = IVPU_PLATFORM_SILICON; | |
| 601 | − ivpu_hw_wa_init(vdev); | |
| 602 | − ivpu_hw_timeouts_init(vdev); | |
| 603 | − | |
| 604 | − return 0; | |
| 605 | −} | |
| 606 | − | |
| 607 | −static int ivpu_hw_37xx_ip_reset(struct ivpu_device *vdev) | |
| 608 | −{ | |
| 609 | − int ret; | |
| 610 | − u32 val; | |
| 611 | − | |
| 612 | − if (IVPU_WA(punit_disabled)) | |
| 613 | − return 0; | |
| 614 | − | |
| 615 | − ret = REGB_POLL_FLD(VPU_37XX_BUTTRESS_VPU_IP_RESET, TRIGGER, 0, TIMEOUT_US); | |
| 616 | − if (ret) { | |
| 617 | − ivpu_err(vdev, "Timed out waiting for TRIGGER bit\n"); | |
| 618 | − return ret; | |
| 619 | − } | |
| 620 | − | |
| 621 | − val = REGB_RD32(VPU_37XX_BUTTRESS_VPU_IP_RESET); | |
| 622 | − val = REG_SET_FLD(VPU_37XX_BUTTRESS_VPU_IP_RESET, TRIGGER, val); | |
| 623 | − REGB_WR32(VPU_37XX_BUTTRESS_VPU_IP_RESET, val); | |
| 624 | − | |
| 625 | − ret = REGB_POLL_FLD(VPU_37XX_BUTTRESS_VPU_IP_RESET, TRIGGER, 0, TIMEOUT_US); | |
| 626 | − if (ret) | |
| 627 | − ivpu_err(vdev, "Timed out waiting for RESET completion\n"); | |
| 628 | − | |
| 629 | − return ret; | |
| 630 | −} | |
| 631 | − | |
| 632 | −static int ivpu_hw_37xx_reset(struct ivpu_device *vdev) | |
| 633 | −{ | |
| 634 | − int ret = 0; | |
| 635 | − | |
| 636 | − if (ivpu_hw_37xx_ip_reset(vdev)) { | |
| 637 | − ivpu_err(vdev, "Failed to reset NPU\n"); | |
| 638 | − ret = -EIO; | |
| 639 | − } | |
| 640 | − | |
| 641 | − if (ivpu_pll_disable(vdev)) { | |
| 642 | − ivpu_err(vdev, "Failed to disable PLL\n"); | |
| 643 | − ret = -EIO; | |
| 644 | − } | |
| 645 | − | |
| 646 | − return ret; | |
| 647 | −} | |
| 648 | − | |
| 649 | −static int ivpu_hw_37xx_d0i3_enable(struct ivpu_device *vdev) | |
| 650 | −{ | |
| 651 | − int ret; | |
| 652 | − | |
| 653 | − ret = ivpu_boot_d0i3_drive(vdev, true); | |
| 654 | − if (ret) | |
| 655 | − ivpu_err(vdev, "Failed to enable D0i3: %d\n", ret); | |
| 656 | − | |
| 657 | − udelay(5); /* VPU requires 5 us to complete the transition */ | |
| 658 | − | |
| 659 | − return ret; | |
| 660 | −} | |
| 661 | − | |
| 662 | −static int ivpu_hw_37xx_d0i3_disable(struct ivpu_device *vdev) | |
| 663 | −{ | |
| 664 | − int ret; | |
| 665 | − | |
| 666 | − ret = ivpu_boot_d0i3_drive(vdev, false); | |
| 667 | − if (ret) | |
| 668 | − ivpu_err(vdev, "Failed to disable D0i3: %d\n", ret); | |
| 669 | − | |
| 670 | − return ret; | |
| 671 | −} | |
| 672 | − | |
| 673 | −static int ivpu_hw_37xx_power_up(struct ivpu_device *vdev) | |
| 674 | −{ | |
| 675 | − int ret; | |
| 676 | − | |
| 677 | − /* PLL requests may fail when powering down, so issue WP 0 here */ | |
| 678 | − ret = ivpu_pll_disable(vdev); | |
| 679 | − if (ret) | |
| 680 | − ivpu_warn(vdev, "Failed to disable PLL: %d\n", ret); | |
| 681 | − | |
| 682 | − ret = ivpu_hw_37xx_d0i3_disable(vdev); | |
| 683 | − if (ret) | |
| 684 | − ivpu_warn(vdev, "Failed to disable D0I3: %d\n", ret); | |
| 685 | − | |
| 686 | − ret = ivpu_pll_enable(vdev); | |
| 687 | − if (ret) { | |
| 688 | − ivpu_err(vdev, "Failed to enable PLL: %d\n", ret); | |
| 689 | − return ret; | |
| 690 | − } | |
| 691 | − | |
| 692 | − ret = ivpu_boot_host_ss_configure(vdev); | |
| 693 | − if (ret) { | |
| 694 | − ivpu_err(vdev, "Failed to configure host SS: %d\n", ret); | |
| 695 | − return ret; | |
| 696 | − } | |
| 697 | − | |
| 698 | − /* | |
| 699 | − * The control circuitry for vpu_idle indication logic powers up active. | |
| 700 | − * To ensure unnecessary low power mode signal from LRT during bring up, | |
| 701 | − * KMD disables the circuitry prior to bringing up the Main Power island. | |
| 702 | − */ | |
| 703 | − ivpu_boot_vpu_idle_gen_disable(vdev); | |
| 704 | − | |
| 705 | − ret = ivpu_boot_pwr_domain_enable(vdev); | |
| 706 | − if (ret) { | |
| 707 | − ivpu_err(vdev, "Failed to enable power domain: %d\n", ret); | |
| 708 | − return ret; | |
| 709 | − } | |
| 710 | − | |
| 711 | − ret = ivpu_boot_host_ss_axi_enable(vdev); | |
| 712 | − if (ret) { | |
| 713 | − ivpu_err(vdev, "Failed to enable AXI: %d\n", ret); | |
| 714 | − return ret; | |
| 715 | − } | |
| 716 | − | |
| 717 | − ret = ivpu_boot_host_ss_top_noc_enable(vdev); | |
| 718 | − if (ret) | |
| 719 | − ivpu_err(vdev, "Failed to enable TOP NOC: %d\n", ret); | |
| 720 | − | |
| 721 | − return ret; | |
| 722 | −} | |
| 723 | − | |
| 724 | −static int ivpu_hw_37xx_boot_fw(struct ivpu_device *vdev) | |
| 725 | −{ | |
| 726 | − ivpu_boot_no_snoop_enable(vdev); | |
| 727 | − ivpu_boot_tbu_mmu_enable(vdev); | |
| 728 | − ivpu_boot_soc_cpu_boot(vdev); | |
| 729 | − | |
| 730 | − return 0; | |
| 731 | −} | |
| 732 | − | |
| 733 | −static bool ivpu_hw_37xx_is_idle(struct ivpu_device *vdev) | |
| 734 | −{ | |
| 735 | − u32 val; | |
| 736 | − | |
| 737 | − if (IVPU_WA(punit_disabled)) | |
| 738 | − return true; | |
| 739 | − | |
| 740 | − val = REGB_RD32(VPU_37XX_BUTTRESS_VPU_STATUS); | |
| 741 | − return REG_TEST_FLD(VPU_37XX_BUTTRESS_VPU_STATUS, READY, val) && | |
| 742 | − REG_TEST_FLD(VPU_37XX_BUTTRESS_VPU_STATUS, IDLE, val); | |
| 743 | −} | |
| 744 | − | |
| 745 | −static int ivpu_hw_37xx_wait_for_idle(struct ivpu_device *vdev) | |
| 746 | −{ | |
| 747 | − return REGB_POLL_FLD(VPU_37XX_BUTTRESS_VPU_STATUS, IDLE, 0x1, IDLE_TIMEOUT_US); | |
| 748 | −} | |
| 749 | − | |
| 750 | −static void ivpu_hw_37xx_save_d0i3_entry_timestamp(struct ivpu_device *vdev) | |
| 751 | −{ | |
| 752 | − vdev->hw->d0i3_entry_host_ts = ktime_get_boottime(); | |
| 753 | − vdev->hw->d0i3_entry_vpu_ts = REGV_RD64(VPU_37XX_CPU_SS_TIM_PERF_FREE_CNT); | |
| 754 | −} | |
| 755 | − | |
| 756 | −static int ivpu_hw_37xx_power_down(struct ivpu_device *vdev) | |
| 757 | −{ | |
| 758 | − int ret = 0; | |
| 759 | − | |
| 760 | − ivpu_hw_37xx_save_d0i3_entry_timestamp(vdev); | |
| 761 | − | |
| 762 | − if (!ivpu_hw_37xx_is_idle(vdev)) | |
| 763 | − ivpu_warn(vdev, "NPU not idle during power down\n"); | |
| 764 | − | |
| 765 | − if (ivpu_hw_37xx_reset(vdev)) { | |
| 766 | − ivpu_err(vdev, "Failed to reset NPU\n"); | |
| 767 | − ret = -EIO; | |
| 768 | − } | |
| 769 | − | |
| 770 | − if (ivpu_hw_37xx_d0i3_enable(vdev)) { | |
| 771 | − ivpu_err(vdev, "Failed to enter D0I3\n"); | |
| 772 | − ret = -EIO; | |
| 773 | − } | |
| 774 | − | |
| 775 | − return ret; | |
| 776 | −} | |
| 777 | − | |
| 778 | −static void ivpu_hw_37xx_wdt_disable(struct ivpu_device *vdev) | |
| 779 | −{ | |
| 780 | − u32 val; | |
| 781 | − | |
| 782 | − /* Enable writing and set non-zero WDT value */ | |
| 783 | − REGV_WR32(VPU_37XX_CPU_SS_TIM_SAFE, TIM_SAFE_ENABLE); | |
| 784 | − REGV_WR32(VPU_37XX_CPU_SS_TIM_WATCHDOG, TIM_WATCHDOG_RESET_VALUE); | |
| 785 | − | |
| 786 | − /* Enable writing and disable watchdog timer */ | |
| 787 | − REGV_WR32(VPU_37XX_CPU_SS_TIM_SAFE, TIM_SAFE_ENABLE); | |
| 788 | − REGV_WR32(VPU_37XX_CPU_SS_TIM_WDOG_EN, 0); | |
| 789 | − | |
| 790 | − /* Now clear the timeout interrupt */ | |
| 791 | − val = REGV_RD32(VPU_37XX_CPU_SS_TIM_GEN_CONFIG); | |
| 792 | − val = REG_CLR_FLD(VPU_37XX_CPU_SS_TIM_GEN_CONFIG, WDOG_TO_INT_CLR, val); | |
| 793 | − REGV_WR32(VPU_37XX_CPU_SS_TIM_GEN_CONFIG, val); | |
| 794 | −} | |
| 795 | − | |
| 796 | −static u32 ivpu_hw_37xx_profiling_freq_get(struct ivpu_device *vdev) | |
| 797 | −{ | |
| 798 | − return PLL_PROF_CLK_FREQ; | |
| 799 | −} | |
| 800 | − | |
| 801 | −static void ivpu_hw_37xx_profiling_freq_drive(struct ivpu_device *vdev, bool enable) | |
| 802 | −{ | |
| 803 | − /* Profiling freq - is a debug feature. Unavailable on VPU 37XX. */ | |
| 804 | −} | |
| 805 | − | |
| 806 | −static u32 ivpu_hw_37xx_ratio_to_freq(struct ivpu_device *vdev, u32 ratio) | |
| 807 | −{ | |
| 808 | − u32 pll_clock = PLL_REF_CLK_FREQ * ratio; | |
| 809 | − u32 cpu_clock; | |
| 810 | − | |
| 811 | − if ((vdev->hw->config & 0xff) == PLL_RATIO_4_3) | |
| 812 | − cpu_clock = pll_clock * 2 / 4; | |
| 813 | − else | |
| 814 | − cpu_clock = pll_clock * 2 / 5; | |
| 815 | − | |
| 816 | − return cpu_clock; | |
| 817 | −} | |
| 818 | − | |
| 819 | −/* Register indirect accesses */ | |
| 820 | −static u32 ivpu_hw_37xx_reg_pll_freq_get(struct ivpu_device *vdev) | |
| 821 | −{ | |
| 822 | − u32 pll_curr_ratio; | |
| 823 | − | |
| 824 | − pll_curr_ratio = REGB_RD32(VPU_37XX_BUTTRESS_CURRENT_PLL); | |
| 825 | − pll_curr_ratio &= VPU_37XX_BUTTRESS_CURRENT_PLL_RATIO_MASK; | |
| 826 | − | |
| 827 | − if (!ivpu_is_silicon(vdev)) | |
| 828 | − return PLL_SIMULATION_FREQ; | |
| 829 | − | |
| 830 | − return ivpu_hw_37xx_ratio_to_freq(vdev, pll_curr_ratio); | |
| 831 | −} | |
| 832 | − | |
| 833 | −static u32 ivpu_hw_37xx_reg_telemetry_offset_get(struct ivpu_device *vdev) | |
| 834 | −{ | |
| 835 | − return REGB_RD32(VPU_37XX_BUTTRESS_VPU_TELEMETRY_OFFSET); | |
| 836 | −} | |
| 837 | − | |
| 838 | −static u32 ivpu_hw_37xx_reg_telemetry_size_get(struct ivpu_device *vdev) | |
| 839 | −{ | |
| 840 | − return REGB_RD32(VPU_37XX_BUTTRESS_VPU_TELEMETRY_SIZE); | |
| 841 | −} | |
| 842 | − | |
| 843 | −static u32 ivpu_hw_37xx_reg_telemetry_enable_get(struct ivpu_device *vdev) | |
| 844 | −{ | |
| 845 | − return REGB_RD32(VPU_37XX_BUTTRESS_VPU_TELEMETRY_ENABLE); | |
| 846 | −} | |
| 847 | − | |
| 848 | −static void ivpu_hw_37xx_reg_db_set(struct ivpu_device *vdev, u32 db_id) | |
| 849 | −{ | |
| 850 | − u32 reg_stride = VPU_37XX_CPU_SS_DOORBELL_1 - VPU_37XX_CPU_SS_DOORBELL_0; | |
| 851 | − u32 val = REG_FLD(VPU_37XX_CPU_SS_DOORBELL_0, SET); | |
| 852 | − | |
| 853 | − REGV_WR32I(VPU_37XX_CPU_SS_DOORBELL_0, reg_stride, db_id, val); | |
| 854 | −} | |
| 855 | − | |
| 856 | −static u32 ivpu_hw_37xx_reg_ipc_rx_addr_get(struct ivpu_device *vdev) | |
| 857 | −{ | |
| 858 | − return REGV_RD32(VPU_37XX_HOST_SS_TIM_IPC_FIFO_ATM); | |
| 859 | −} | |
| 860 | − | |
| 861 | −static u32 ivpu_hw_37xx_reg_ipc_rx_count_get(struct ivpu_device *vdev) | |
| 862 | −{ | |
| 863 | − u32 count = REGV_RD32_SILENT(VPU_37XX_HOST_SS_TIM_IPC_FIFO_STAT); | |
| 864 | − | |
| 865 | − return REG_GET_FLD(VPU_37XX_HOST_SS_TIM_IPC_FIFO_STAT, FILL_LEVEL, count); | |
| 866 | −} | |
| 867 | − | |
| 868 | −static void ivpu_hw_37xx_reg_ipc_tx_set(struct ivpu_device *vdev, u32 vpu_addr) | |
| 869 | −{ | |
| 870 | − REGV_WR32(VPU_37XX_CPU_SS_TIM_IPC_FIFO, vpu_addr); | |
| 871 | −} | |
| 872 | − | |
| 873 | −static void ivpu_hw_37xx_irq_clear(struct ivpu_device *vdev) | |
| 874 | −{ | |
| 875 | − REGV_WR64(VPU_37XX_HOST_SS_ICB_CLEAR_0, ICB_0_1_IRQ_MASK); | |
| 876 | −} | |
| 877 | − | |
| 878 | −static void ivpu_hw_37xx_irq_enable(struct ivpu_device *vdev) | |
| 879 | −{ | |
| 880 | − REGV_WR32(VPU_37XX_HOST_SS_FW_SOC_IRQ_EN, ITF_FIREWALL_VIOLATION_MASK); | |
| 881 | − REGV_WR64(VPU_37XX_HOST_SS_ICB_ENABLE_0, ICB_0_1_IRQ_MASK); | |
| 882 | − REGB_WR32(VPU_37XX_BUTTRESS_LOCAL_INT_MASK, BUTTRESS_IRQ_ENABLE_MASK); | |
| 883 | − REGB_WR32(VPU_37XX_BUTTRESS_GLOBAL_INT_MASK, 0x0); | |
| 884 | −} | |
| 885 | − | |
| 886 | −static void ivpu_hw_37xx_irq_disable(struct ivpu_device *vdev) | |
| 887 | −{ | |
| 888 | − REGB_WR32(VPU_37XX_BUTTRESS_GLOBAL_INT_MASK, 0x1); | |
| 889 | − REGB_WR32(VPU_37XX_BUTTRESS_LOCAL_INT_MASK, BUTTRESS_IRQ_DISABLE_MASK); | |
| 890 | − REGV_WR64(VPU_37XX_HOST_SS_ICB_ENABLE_0, 0x0ull); | |
| 891 | − REGV_WR32(VPU_37XX_HOST_SS_FW_SOC_IRQ_EN, 0x0); | |
| 892 | −} | |
| 893 | − | |
| 894 | −static void ivpu_hw_37xx_irq_wdt_nce_handler(struct ivpu_device *vdev) | |
| 895 | −{ | |
| 896 | − ivpu_pm_trigger_recovery(vdev, "WDT NCE IRQ"); | |
| 897 | −} | |
| 898 | − | |
| 899 | −static void ivpu_hw_37xx_irq_wdt_mss_handler(struct ivpu_device *vdev) | |
| 900 | −{ | |
| 901 | − ivpu_hw_wdt_disable(vdev); | |
| 902 | − ivpu_pm_trigger_recovery(vdev, "WDT MSS IRQ"); | |
| 903 | −} | |
| 904 | − | |
| 905 | −static void ivpu_hw_37xx_irq_noc_firewall_handler(struct ivpu_device *vdev) | |
| 906 | −{ | |
| 907 | − ivpu_pm_trigger_recovery(vdev, "NOC Firewall IRQ"); | |
| 908 | −} | |
| 909 | − | |
| 910 | −/* Handler for IRQs from VPU core (irqV) */ | |
| 911 | −static bool ivpu_hw_37xx_irqv_handler(struct ivpu_device *vdev, int irq, bool *wake_thread) | |
| 912 | −{ | |
| 913 | − u32 status = REGV_RD32(VPU_37XX_HOST_SS_ICB_STATUS_0) & ICB_0_IRQ_MASK; | |
| 914 | − | |
| 915 | − if (!status) | |
| 916 | − return false; | |
| 917 | − | |
| 918 | − REGV_WR32(VPU_37XX_HOST_SS_ICB_CLEAR_0, status); | |
| 919 | − | |
| 920 | − if (REG_TEST_FLD(VPU_37XX_HOST_SS_ICB_STATUS_0, MMU_IRQ_0_INT, status)) | |
| 921 | − ivpu_mmu_irq_evtq_handler(vdev); | |
| 922 | − | |
| 923 | − if (REG_TEST_FLD(VPU_37XX_HOST_SS_ICB_STATUS_0, HOST_IPC_FIFO_INT, status)) | |
| 924 | − ivpu_ipc_irq_handler(vdev, wake_thread); | |
| 925 | − | |
| 926 | − if (REG_TEST_FLD(VPU_37XX_HOST_SS_ICB_STATUS_0, MMU_IRQ_1_INT, status)) | |
| 927 | − ivpu_dbg(vdev, IRQ, "MMU sync complete\n"); | |
| 928 | − | |
| 929 | − if (REG_TEST_FLD(VPU_37XX_HOST_SS_ICB_STATUS_0, MMU_IRQ_2_INT, status)) | |
| 930 | − ivpu_mmu_irq_gerr_handler(vdev); | |
| 931 | − | |
| 932 | − if (REG_TEST_FLD(VPU_37XX_HOST_SS_ICB_STATUS_0, CPU_INT_REDIRECT_0_INT, status)) | |
| 933 | − ivpu_hw_37xx_irq_wdt_mss_handler(vdev); | |
| 934 | − | |
| 935 | − if (REG_TEST_FLD(VPU_37XX_HOST_SS_ICB_STATUS_0, CPU_INT_REDIRECT_1_INT, status)) | |
| 936 | − ivpu_hw_37xx_irq_wdt_nce_handler(vdev); | |
| 937 | − | |
| 938 | − if (REG_TEST_FLD(VPU_37XX_HOST_SS_ICB_STATUS_0, NOC_FIREWALL_INT, status)) | |
| 939 | − ivpu_hw_37xx_irq_noc_firewall_handler(vdev); | |
| 940 | − | |
| 941 | − return true; | |
| 942 | −} | |
| 943 | − | |
| 944 | −/* Handler for IRQs from Buttress core (irqB) */ | |
| 945 | −static bool ivpu_hw_37xx_irqb_handler(struct ivpu_device *vdev, int irq) | |
| 946 | −{ | |
| 947 | − u32 status = REGB_RD32(VPU_37XX_BUTTRESS_INTERRUPT_STAT) & BUTTRESS_IRQ_MASK; | |
| 948 | − bool schedule_recovery = false; | |
| 949 | − | |
| 950 | − if (!status) | |
| 951 | − return false; | |
| 952 | − | |
| 953 | − if (REG_TEST_FLD(VPU_37XX_BUTTRESS_INTERRUPT_STAT, FREQ_CHANGE, status)) | |
| 954 | − ivpu_dbg(vdev, IRQ, "FREQ_CHANGE irq: %08x", | |
| 955 | − REGB_RD32(VPU_37XX_BUTTRESS_CURRENT_PLL)); | |
| 956 | − | |
| 957 | − if (REG_TEST_FLD(VPU_37XX_BUTTRESS_INTERRUPT_STAT, ATS_ERR, status)) { | |
| 958 | − ivpu_err(vdev, "ATS_ERR irq 0x%016llx", REGB_RD64(VPU_37XX_BUTTRESS_ATS_ERR_LOG_0)); | |
| 959 | − REGB_WR32(VPU_37XX_BUTTRESS_ATS_ERR_CLEAR, 0x1); | |
| 960 | − schedule_recovery = true; | |
| 961 | − } | |
| 962 | − | |
| 963 | − if (REG_TEST_FLD(VPU_37XX_BUTTRESS_INTERRUPT_STAT, UFI_ERR, status)) { | |
| 964 | − u32 ufi_log = REGB_RD32(VPU_37XX_BUTTRESS_UFI_ERR_LOG); | |
| 965 | − | |
| 966 | − ivpu_err(vdev, "UFI_ERR irq (0x%08x) opcode: 0x%02lx axi_id: 0x%02lx cq_id: 0x%03lx", | |
| 967 | − ufi_log, REG_GET_FLD(VPU_37XX_BUTTRESS_UFI_ERR_LOG, OPCODE, ufi_log), | |
| 968 | − REG_GET_FLD(VPU_37XX_BUTTRESS_UFI_ERR_LOG, AXI_ID, ufi_log), | |
| 969 | − REG_GET_FLD(VPU_37XX_BUTTRESS_UFI_ERR_LOG, CQ_ID, ufi_log)); | |
| 970 | − REGB_WR32(VPU_37XX_BUTTRESS_UFI_ERR_CLEAR, 0x1); | |
| 971 | − schedule_recovery = true; | |
| 972 | − } | |
| 973 | − | |
| 974 | − /* This must be done after interrupts are cleared at the source. */ | |
| 975 | − if (IVPU_WA(interrupt_clear_with_0)) | |
| 976 | − /* | |
| 977 | − * Writing 1 triggers an interrupt, so we can't perform read update write. | |
| 978 | − * Clear local interrupt status by writing 0 to all bits. | |
| 979 | − */ | |
| 980 | − REGB_WR32(VPU_37XX_BUTTRESS_INTERRUPT_STAT, 0x0); | |
| 981 | − else | |
| 982 | − REGB_WR32(VPU_37XX_BUTTRESS_INTERRUPT_STAT, status); | |
| 983 | − | |
| 984 | − if (schedule_recovery) | |
| 985 | − ivpu_pm_trigger_recovery(vdev, "Buttress IRQ"); | |
| 986 | − | |
| 987 | − return true; | |
| 988 | −} | |
| 989 | − | |
| 990 | −static irqreturn_t ivpu_hw_37xx_irq_handler(int irq, void *ptr) | |
| 991 | −{ | |
| 992 | − struct ivpu_device *vdev = ptr; | |
| 993 | − bool irqv_handled, irqb_handled, wake_thread = false; | |
| 994 | − | |
| 995 | − REGB_WR32(VPU_37XX_BUTTRESS_GLOBAL_INT_MASK, 0x1); | |
| 996 | − | |
| 997 | − irqv_handled = ivpu_hw_37xx_irqv_handler(vdev, irq, &wake_thread); | |
| 998 | − irqb_handled = ivpu_hw_37xx_irqb_handler(vdev, irq); | |
| 999 | − | |
| 1000 | − /* Re-enable global interrupts to re-trigger MSI for pending interrupts */ | |
| 1001 | − REGB_WR32(VPU_37XX_BUTTRESS_GLOBAL_INT_MASK, 0x0); | |
| 1002 | − | |
| 1003 | − if (wake_thread) | |
| 1004 | − return IRQ_WAKE_THREAD; | |
| 1005 | − if (irqv_handled || irqb_handled) | |
| 1006 | − return IRQ_HANDLED; | |
| 1007 | − return IRQ_NONE; | |
| 1008 | −} | |
| 1009 | − | |
| 1010 | −static void ivpu_hw_37xx_diagnose_failure(struct ivpu_device *vdev) | |
| 1011 | −{ | |
| 1012 | − u32 irqv = REGV_RD32(VPU_37XX_HOST_SS_ICB_STATUS_0) & ICB_0_IRQ_MASK; | |
| 1013 | − u32 irqb = REGB_RD32(VPU_37XX_BUTTRESS_INTERRUPT_STAT) & BUTTRESS_IRQ_MASK; | |
| 1014 | − | |
| 1015 | − if (ivpu_hw_37xx_reg_ipc_rx_count_get(vdev)) | |
| 1016 | − ivpu_err(vdev, "IPC FIFO queue not empty, missed IPC IRQ"); | |
| 1017 | − | |
| 1018 | − if (REG_TEST_FLD(VPU_37XX_HOST_SS_ICB_STATUS_0, CPU_INT_REDIRECT_0_INT, irqv)) | |
| 1019 | − ivpu_err(vdev, "WDT MSS timeout detected\n"); | |
| 1020 | − | |
| 1021 | − if (REG_TEST_FLD(VPU_37XX_HOST_SS_ICB_STATUS_0, CPU_INT_REDIRECT_1_INT, irqv)) | |
| 1022 | − ivpu_err(vdev, "WDT NCE timeout detected\n"); | |
| 1023 | − | |
| 1024 | − if (REG_TEST_FLD(VPU_37XX_HOST_SS_ICB_STATUS_0, NOC_FIREWALL_INT, irqv)) | |
| 1025 | − ivpu_err(vdev, "NOC Firewall irq detected\n"); | |
| 1026 | − | |
| 1027 | − if (REG_TEST_FLD(VPU_37XX_BUTTRESS_INTERRUPT_STAT, ATS_ERR, irqb)) | |
| 1028 | − ivpu_err(vdev, "ATS_ERR irq 0x%016llx", REGB_RD64(VPU_37XX_BUTTRESS_ATS_ERR_LOG_0)); | |
| 1029 | − | |
| 1030 | − if (REG_TEST_FLD(VPU_37XX_BUTTRESS_INTERRUPT_STAT, UFI_ERR, irqb)) { | |
| 1031 | − u32 ufi_log = REGB_RD32(VPU_37XX_BUTTRESS_UFI_ERR_LOG); | |
| 1032 | − | |
| 1033 | − ivpu_err(vdev, "UFI_ERR irq (0x%08x) opcode: 0x%02lx axi_id: 0x%02lx cq_id: 0x%03lx", | |
| 1034 | − ufi_log, REG_GET_FLD(VPU_37XX_BUTTRESS_UFI_ERR_LOG, OPCODE, ufi_log), | |
| 1035 | − REG_GET_FLD(VPU_37XX_BUTTRESS_UFI_ERR_LOG, AXI_ID, ufi_log), | |
| 1036 | − REG_GET_FLD(VPU_37XX_BUTTRESS_UFI_ERR_LOG, CQ_ID, ufi_log)); | |
| 1037 | − } | |
| 1038 | −} | |
| 1039 | − | |
| 1040 | −const struct ivpu_hw_ops ivpu_hw_37xx_ops = { | |
| 1041 | − .info_init = ivpu_hw_37xx_info_init, | |
| 1042 | − .power_up = ivpu_hw_37xx_power_up, | |
| 1043 | − .is_idle = ivpu_hw_37xx_is_idle, | |
| 1044 | − .wait_for_idle = ivpu_hw_37xx_wait_for_idle, | |
| 1045 | − .power_down = ivpu_hw_37xx_power_down, | |
| 1046 | − .reset = ivpu_hw_37xx_reset, | |
| 1047 | − .boot_fw = ivpu_hw_37xx_boot_fw, | |
| 1048 | − .wdt_disable = ivpu_hw_37xx_wdt_disable, | |
| 1049 | − .diagnose_failure = ivpu_hw_37xx_diagnose_failure, | |
| 1050 | − .profiling_freq_get = ivpu_hw_37xx_profiling_freq_get, | |
| 1051 | − .profiling_freq_drive = ivpu_hw_37xx_profiling_freq_drive, | |
| 1052 | − .reg_pll_freq_get = ivpu_hw_37xx_reg_pll_freq_get, | |
| 1053 | − .ratio_to_freq = ivpu_hw_37xx_ratio_to_freq, | |
| 1054 | − .reg_telemetry_offset_get = ivpu_hw_37xx_reg_telemetry_offset_get, | |
| 1055 | − .reg_telemetry_size_get = ivpu_hw_37xx_reg_telemetry_size_get, | |
| 1056 | − .reg_telemetry_enable_get = ivpu_hw_37xx_reg_telemetry_enable_get, | |
| 1057 | − .reg_db_set = ivpu_hw_37xx_reg_db_set, | |
| 1058 | − .reg_ipc_rx_addr_get = ivpu_hw_37xx_reg_ipc_rx_addr_get, | |
| 1059 | − .reg_ipc_rx_count_get = ivpu_hw_37xx_reg_ipc_rx_count_get, | |
| 1060 | − .reg_ipc_tx_set = ivpu_hw_37xx_reg_ipc_tx_set, | |
| 1061 | − .irq_clear = ivpu_hw_37xx_irq_clear, | |
| 1062 | − .irq_enable = ivpu_hw_37xx_irq_enable, | |
| 1063 | − .irq_disable = ivpu_hw_37xx_irq_disable, | |
| 1064 | − .irq_handler = ivpu_hw_37xx_irq_handler, | |
| 1065 | −}; | |
| @@ -8,78 +8,6 @@ · 7 unmodified lines | ||
| 8 | 8 | |
| 9 | 9 | #include <linux/bits.h> |
| 10 | 10 | |
| 11 | −#define VPU_37XX_BUTTRESS_INTERRUPT_TYPE 0x00000000u | |
| 12 | − | |
| 13 | −#define VPU_37XX_BUTTRESS_INTERRUPT_STAT 0x00000004u | |
| 14 | −#define VPU_37XX_BUTTRESS_INTERRUPT_STAT_FREQ_CHANGE_MASK BIT_MASK(0) | |
| 15 | −#define VPU_37XX_BUTTRESS_INTERRUPT_STAT_ATS_ERR_MASK BIT_MASK(1) | |
| 16 | −#define VPU_37XX_BUTTRESS_INTERRUPT_STAT_UFI_ERR_MASK BIT_MASK(2) | |
| 17 | − | |
| 18 | −#define VPU_37XX_BUTTRESS_WP_REQ_PAYLOAD0 0x00000008u | |
| 19 | −#define VPU_37XX_BUTTRESS_WP_REQ_PAYLOAD0_MIN_RATIO_MASK GENMASK(15, 0) | |
| 20 | −#define VPU_37XX_BUTTRESS_WP_REQ_PAYLOAD0_MAX_RATIO_MASK GENMASK(31, 16) | |
| 21 | − | |
| 22 | −#define VPU_37XX_BUTTRESS_WP_REQ_PAYLOAD1 0x0000000cu | |
| 23 | −#define VPU_37XX_BUTTRESS_WP_REQ_PAYLOAD1_TARGET_RATIO_MASK GENMASK(15, 0) | |
| 24 | −#define VPU_37XX_BUTTRESS_WP_REQ_PAYLOAD1_EPP_MASK GENMASK(31, 16) | |
| 25 | − | |
| 26 | −#define VPU_37XX_BUTTRESS_WP_REQ_PAYLOAD2 0x00000010u | |
| 27 | −#define VPU_37XX_BUTTRESS_WP_REQ_PAYLOAD2_CONFIG_MASK GENMASK(15, 0) | |
| 28 | − | |
| 29 | −#define VPU_37XX_BUTTRESS_WP_REQ_CMD 0x00000014u | |
| 30 | −#define VPU_37XX_BUTTRESS_WP_REQ_CMD_SEND_MASK BIT_MASK(0) | |
| 31 | − | |
| 32 | −#define VPU_37XX_BUTTRESS_WP_DOWNLOAD 0x00000018u | |
| 33 | −#define VPU_37XX_BUTTRESS_WP_DOWNLOAD_TARGET_RATIO_MASK GENMASK(15, 0) | |
| 34 | − | |
| 35 | −#define VPU_37XX_BUTTRESS_CURRENT_PLL 0x0000001cu | |
| 36 | −#define VPU_37XX_BUTTRESS_CURRENT_PLL_RATIO_MASK GENMASK(15, 0) | |
| 37 | − | |
| 38 | −#define VPU_37XX_BUTTRESS_PLL_ENABLE 0x00000020u | |
| 39 | − | |
| 40 | −#define VPU_37XX_BUTTRESS_FMIN_FUSE 0x00000024u | |
| 41 | −#define VPU_37XX_BUTTRESS_FMIN_FUSE_MIN_RATIO_MASK GENMASK(7, 0) | |
| 42 | −#define VPU_37XX_BUTTRESS_FMIN_FUSE_PN_RATIO_MASK GENMASK(15, 8) | |
| 43 | − | |
| 44 | −#define VPU_37XX_BUTTRESS_FMAX_FUSE 0x00000028u | |
| 45 | −#define VPU_37XX_BUTTRESS_FMAX_FUSE_MAX_RATIO_MASK GENMASK(7, 0) | |
| 46 | − | |
| 47 | −#define VPU_37XX_BUTTRESS_TILE_FUSE 0x0000002cu | |
| 48 | −#define VPU_37XX_BUTTRESS_TILE_FUSE_VALID_MASK BIT_MASK(0) | |
| 49 | −#define VPU_37XX_BUTTRESS_TILE_FUSE_SKU_MASK GENMASK(3, 2) | |
| 50 | − | |
| 51 | −#define VPU_37XX_BUTTRESS_LOCAL_INT_MASK 0x00000030u | |
| 52 | −#define VPU_37XX_BUTTRESS_GLOBAL_INT_MASK 0x00000034u | |
| 53 | − | |
| 54 | −#define VPU_37XX_BUTTRESS_PLL_STATUS 0x00000040u | |
| 55 | −#define VPU_37XX_BUTTRESS_PLL_STATUS_LOCK_MASK BIT_MASK(1) | |
| 56 | − | |
| 57 | −#define VPU_37XX_BUTTRESS_VPU_STATUS 0x00000044u | |
| 58 | −#define VPU_37XX_BUTTRESS_VPU_STATUS_READY_MASK BIT_MASK(0) | |
| 59 | −#define VPU_37XX_BUTTRESS_VPU_STATUS_IDLE_MASK BIT_MASK(1) | |
| 60 | − | |
| 61 | −#define VPU_37XX_BUTTRESS_VPU_D0I3_CONTROL 0x00000060u | |
| 62 | −#define VPU_37XX_BUTTRESS_VPU_D0I3_CONTROL_INPROGRESS_MASK BIT_MASK(0) | |
| 63 | −#define VPU_37XX_BUTTRESS_VPU_D0I3_CONTROL_I3_MASK BIT_MASK(2) | |
| 64 | − | |
| 65 | −#define VPU_37XX_BUTTRESS_VPU_IP_RESET 0x00000050u | |
| 66 | −#define VPU_37XX_BUTTRESS_VPU_IP_RESET_TRIGGER_MASK BIT_MASK(0) | |
| 67 | − | |
| 68 | −#define VPU_37XX_BUTTRESS_VPU_TELEMETRY_OFFSET 0x00000080u | |
| 69 | −#define VPU_37XX_BUTTRESS_VPU_TELEMETRY_SIZE 0x00000084u | |
| 70 | −#define VPU_37XX_BUTTRESS_VPU_TELEMETRY_ENABLE 0x00000088u | |
| 71 | − | |
| 72 | −#define VPU_37XX_BUTTRESS_ATS_ERR_LOG_0 0x000000a0u | |
| 73 | −#define VPU_37XX_BUTTRESS_ATS_ERR_LOG_1 0x000000a4u | |
| 74 | −#define VPU_37XX_BUTTRESS_ATS_ERR_CLEAR 0x000000a8u | |
| 75 | − | |
| 76 | −#define VPU_37XX_BUTTRESS_UFI_ERR_LOG 0x000000b0u | |
| 77 | −#define VPU_37XX_BUTTRESS_UFI_ERR_LOG_CQ_ID_MASK GENMASK(11, 0) | |
| 78 | −#define VPU_37XX_BUTTRESS_UFI_ERR_LOG_AXI_ID_MASK GENMASK(19, 12) | |
| 79 | −#define VPU_37XX_BUTTRESS_UFI_ERR_LOG_OPCODE_MASK GENMASK(24, 20) | |
| 80 | − | |
| 81 | −#define VPU_37XX_BUTTRESS_UFI_ERR_CLEAR 0x000000b4u | |
| 82 | − | |
| 83 | 11 | #define VPU_37XX_HOST_SS_CPR_CLK_SET 0x00000084u |
| 84 | 12 | #define VPU_37XX_HOST_SS_CPR_CLK_SET_TOP_NOC_MASK BIT_MASK(1) |
| 85 | 13 | #define VPU_37XX_HOST_SS_CPR_CLK_SET_DSS_MAS_MASK BIT_MASK(10) |
| @@ -1,1250 +0,0 @@ | ||
| 1 | −// SPDX-License-Identifier: GPL-2.0-only | |
| 2 | −/* | |
| 3 | − * Copyright (C) 2020-2023 Intel Corporation | |
| 4 | − */ | |
| 5 | − | |
| 6 | −#include "ivpu_drv.h" | |
| 7 | −#include "ivpu_fw.h" | |
| 8 | −#include "ivpu_hw.h" | |
| 9 | −#include "ivpu_hw_40xx_reg.h" | |
| 10 | −#include "ivpu_hw_reg_io.h" | |
| 11 | −#include "ivpu_ipc.h" | |
| 12 | −#include "ivpu_mmu.h" | |
| 13 | −#include "ivpu_pm.h" | |
| 14 | − | |
| 15 | −#include <linux/dmi.h> | |
| 16 | − | |
| 17 | −#define TILE_MAX_NUM 6 | |
| 18 | −#define TILE_MAX_MASK 0x3f | |
| 19 | − | |
| 20 | −#define LNL_HW_ID 0x4040 | |
| 21 | − | |
| 22 | −#define SKU_TILE_SHIFT 0u | |
| 23 | −#define SKU_TILE_MASK 0x0000ffffu | |
| 24 | −#define SKU_HW_ID_SHIFT 16u | |
| 25 | −#define SKU_HW_ID_MASK 0xffff0000u | |
| 26 | − | |
| 27 | −#define PLL_CONFIG_DEFAULT 0x0 | |
| 28 | −#define PLL_CDYN_DEFAULT 0x80 | |
| 29 | −#define PLL_EPP_DEFAULT 0x80 | |
| 30 | −#define PLL_REF_CLK_FREQ (50 * 1000000) | |
| 31 | −#define PLL_RATIO_TO_FREQ(x) ((x) * PLL_REF_CLK_FREQ) | |
| 32 | − | |
| 33 | −#define PLL_PROFILING_FREQ_DEFAULT 38400000 | |
| 34 | −#define PLL_PROFILING_FREQ_HIGH 400000000 | |
| 35 | − | |
| 36 | −#define TIM_SAFE_ENABLE 0xf1d0dead | |
| 37 | −#define TIM_WATCHDOG_RESET_VALUE 0xffffffff | |
| 38 | − | |
| 39 | −#define TIMEOUT_US (150 * USEC_PER_MSEC) | |
| 40 | −#define PWR_ISLAND_STATUS_TIMEOUT_US (5 * USEC_PER_MSEC) | |
| 41 | −#define PLL_TIMEOUT_US (1500 * USEC_PER_MSEC) | |
| 42 | −#define IDLE_TIMEOUT_US (5 * USEC_PER_MSEC) | |
| 43 | − | |
| 44 | −#define WEIGHTS_DEFAULT 0xf711f711u | |
| 45 | −#define WEIGHTS_ATS_DEFAULT 0x0000f711u | |
| 46 | − | |
| 47 | −#define ICB_0_IRQ_MASK ((REG_FLD(VPU_40XX_HOST_SS_ICB_STATUS_0, HOST_IPC_FIFO_INT)) | \ | |
| 48 | − (REG_FLD(VPU_40XX_HOST_SS_ICB_STATUS_0, MMU_IRQ_0_INT)) | \ | |
| 49 | − (REG_FLD(VPU_40XX_HOST_SS_ICB_STATUS_0, MMU_IRQ_1_INT)) | \ | |
| 50 | − (REG_FLD(VPU_40XX_HOST_SS_ICB_STATUS_0, MMU_IRQ_2_INT)) | \ | |
| 51 | − (REG_FLD(VPU_40XX_HOST_SS_ICB_STATUS_0, NOC_FIREWALL_INT)) | \ | |
| 52 | − (REG_FLD(VPU_40XX_HOST_SS_ICB_STATUS_0, CPU_INT_REDIRECT_0_INT)) | \ | |
| 53 | − (REG_FLD(VPU_40XX_HOST_SS_ICB_STATUS_0, CPU_INT_REDIRECT_1_INT))) | |
| 54 | − | |
| 55 | −#define ICB_1_IRQ_MASK ((REG_FLD(VPU_40XX_HOST_SS_ICB_STATUS_1, CPU_INT_REDIRECT_2_INT)) | \ | |
| 56 | − (REG_FLD(VPU_40XX_HOST_SS_ICB_STATUS_1, CPU_INT_REDIRECT_3_INT)) | \ | |
| 57 | − (REG_FLD(VPU_40XX_HOST_SS_ICB_STATUS_1, CPU_INT_REDIRECT_4_INT))) | |
| 58 | − | |
| 59 | −#define ICB_0_1_IRQ_MASK ((((u64)ICB_1_IRQ_MASK) << 32) | ICB_0_IRQ_MASK) | |
| 60 | − | |
| 61 | −#define BUTTRESS_IRQ_MASK ((REG_FLD(VPU_40XX_BUTTRESS_INTERRUPT_STAT, ATS_ERR)) | \ | |
| 62 | − (REG_FLD(VPU_40XX_BUTTRESS_INTERRUPT_STAT, CFI0_ERR)) | \ | |
| 63 | − (REG_FLD(VPU_40XX_BUTTRESS_INTERRUPT_STAT, CFI1_ERR)) | \ | |
| 64 | − (REG_FLD(VPU_40XX_BUTTRESS_INTERRUPT_STAT, IMR0_ERR)) | \ | |
| 65 | − (REG_FLD(VPU_40XX_BUTTRESS_INTERRUPT_STAT, IMR1_ERR)) | \ | |
| 66 | − (REG_FLD(VPU_40XX_BUTTRESS_INTERRUPT_STAT, SURV_ERR))) | |
| 67 | − | |
| 68 | −#define BUTTRESS_IRQ_ENABLE_MASK ((u32)~BUTTRESS_IRQ_MASK) | |
| 69 | −#define BUTTRESS_IRQ_DISABLE_MASK ((u32)-1) | |
| 70 | − | |
| 71 | −#define ITF_FIREWALL_VIOLATION_MASK ((REG_FLD(VPU_40XX_HOST_SS_FW_SOC_IRQ_EN, CSS_ROM_CMX)) | \ | |
| 72 | − (REG_FLD(VPU_40XX_HOST_SS_FW_SOC_IRQ_EN, CSS_DBG)) | \ | |
| 73 | − (REG_FLD(VPU_40XX_HOST_SS_FW_SOC_IRQ_EN, CSS_CTRL)) | \ | |
| 74 | − (REG_FLD(VPU_40XX_HOST_SS_FW_SOC_IRQ_EN, DEC400)) | \ | |
| 75 | − (REG_FLD(VPU_40XX_HOST_SS_FW_SOC_IRQ_EN, MSS_NCE)) | \ | |
| 76 | − (REG_FLD(VPU_40XX_HOST_SS_FW_SOC_IRQ_EN, MSS_MBI)) | \ | |
| 77 | − (REG_FLD(VPU_40XX_HOST_SS_FW_SOC_IRQ_EN, MSS_MBI_CMX))) | |
| 78 | − | |
| 79 | −static char *ivpu_platform_to_str(u32 platform) | |
| 80 | −{ | |
| 81 | − switch (platform) { | |
| 82 | − case IVPU_PLATFORM_SILICON: | |
| 83 | − return "SILICON"; | |
| 84 | − case IVPU_PLATFORM_SIMICS: | |
| 85 | − return "SIMICS"; | |
| 86 | − case IVPU_PLATFORM_FPGA: | |
| 87 | − return "FPGA"; | |
| 88 | − default: | |
| 89 | − return "Invalid platform"; | |
| 90 | − } | |
| 91 | −} | |
| 92 | − | |
| 93 | −static const struct dmi_system_id ivpu_dmi_platform_simulation[] = { | |
| 94 | − { | |
| 95 | − .ident = "Intel Simics", | |
| 96 | − .matches = { | |
| 97 | − DMI_MATCH(DMI_BOARD_NAME, "lnlrvp"), | |
| 98 | − DMI_MATCH(DMI_BOARD_VERSION, "1.0"), | |
| 99 | − DMI_MATCH(DMI_BOARD_SERIAL, "123456789"), | |
| 100 | − }, | |
| 101 | − }, | |
| 102 | − { | |
| 103 | − .ident = "Intel Simics", | |
| 104 | − .matches = { | |
| 105 | − DMI_MATCH(DMI_BOARD_NAME, "Simics"), | |
| 106 | − }, | |
| 107 | − }, | |
| 108 | − { } | |
| 109 | −}; | |
| 110 | − | |
| 111 | −static void ivpu_hw_read_platform(struct ivpu_device *vdev) | |
| 112 | −{ | |
| 113 | − if (dmi_check_system(ivpu_dmi_platform_simulation)) | |
| 114 | − vdev->platform = IVPU_PLATFORM_SIMICS; | |
| 115 | − else | |
| 116 | − vdev->platform = IVPU_PLATFORM_SILICON; | |
| 117 | − | |
| 118 | − ivpu_dbg(vdev, MISC, "Platform type: %s (%d)\n", | |
| 119 | − ivpu_platform_to_str(vdev->platform), vdev->platform); | |
| 120 | −} | |
| 121 | − | |
| 122 | −static void ivpu_hw_wa_init(struct ivpu_device *vdev) | |
| 123 | −{ | |
| 124 | − vdev->wa.punit_disabled = ivpu_is_fpga(vdev); | |
| 125 | − vdev->wa.clear_runtime_mem = false; | |
| 126 | − | |
| 127 | − if (ivpu_hw_gen(vdev) == IVPU_HW_40XX) | |
| 128 | − vdev->wa.disable_clock_relinquish = true; | |
| 129 | − | |
| 130 | − IVPU_PRINT_WA(punit_disabled); | |
| 131 | − IVPU_PRINT_WA(clear_runtime_mem); | |
| 132 | − IVPU_PRINT_WA(disable_clock_relinquish); | |
| 133 | −} | |
| 134 | − | |
| 135 | −static void ivpu_hw_timeouts_init(struct ivpu_device *vdev) | |
| 136 | −{ | |
| 137 | − if (ivpu_is_fpga(vdev)) { | |
| 138 | − vdev->timeout.boot = 100000; | |
| 139 | − vdev->timeout.jsm = 50000; | |
| 140 | − vdev->timeout.tdr = 2000000; | |
| 141 | − vdev->timeout.reschedule_suspend = 1000; | |
| 142 | − vdev->timeout.autosuspend = -1; | |
| 143 | − vdev->timeout.d0i3_entry_msg = 500; | |
| 144 | − } else if (ivpu_is_simics(vdev)) { | |
| 145 | − vdev->timeout.boot = 50; | |
| 146 | − vdev->timeout.jsm = 500; | |
| 147 | − vdev->timeout.tdr = 10000; | |
| 148 | − vdev->timeout.reschedule_suspend = 10; | |
| 149 | − vdev->timeout.autosuspend = -1; | |
| 150 | − vdev->timeout.d0i3_entry_msg = 100; | |
| 151 | − } else { | |
| 152 | − vdev->timeout.boot = 1000; | |
| 153 | − vdev->timeout.jsm = 500; | |
| 154 | − vdev->timeout.tdr = 2000; | |
| 155 | − vdev->timeout.reschedule_suspend = 10; | |
| 156 | − vdev->timeout.autosuspend = 10; | |
| 157 | − vdev->timeout.d0i3_entry_msg = 5; | |
| 158 | − } | |
| 159 | −} | |
| 160 | − | |
| 161 | −static int ivpu_pll_wait_for_cmd_send(struct ivpu_device *vdev) | |
| 162 | −{ | |
| 163 | − return REGB_POLL_FLD(VPU_40XX_BUTTRESS_WP_REQ_CMD, SEND, 0, PLL_TIMEOUT_US); | |
| 164 | −} | |
| 165 | − | |
| 166 | −static int ivpu_pll_cmd_send(struct ivpu_device *vdev, u16 min_ratio, u16 max_ratio, | |
| 167 | − u16 target_ratio, u16 epp, u16 config, u16 cdyn) | |
| 168 | −{ | |
| 169 | − int ret; | |
| 170 | − u32 val; | |
| 171 | − | |
| 172 | − ret = ivpu_pll_wait_for_cmd_send(vdev); | |
| 173 | − if (ret) { | |
| 174 | − ivpu_err(vdev, "Failed to sync before WP request: %d\n", ret); | |
| 175 | − return ret; | |
| 176 | − } | |
| 177 | − | |
| 178 | − val = REGB_RD32(VPU_40XX_BUTTRESS_WP_REQ_PAYLOAD0); | |
| 179 | − val = REG_SET_FLD_NUM(VPU_40XX_BUTTRESS_WP_REQ_PAYLOAD0, MIN_RATIO, min_ratio, val); | |
| 180 | − val = REG_SET_FLD_NUM(VPU_40XX_BUTTRESS_WP_REQ_PAYLOAD0, MAX_RATIO, max_ratio, val); | |
| 181 | − REGB_WR32(VPU_40XX_BUTTRESS_WP_REQ_PAYLOAD0, val); | |
| 182 | − | |
| 183 | − val = REGB_RD32(VPU_40XX_BUTTRESS_WP_REQ_PAYLOAD1); | |
| 184 | − val = REG_SET_FLD_NUM(VPU_40XX_BUTTRESS_WP_REQ_PAYLOAD1, TARGET_RATIO, target_ratio, val); | |
| 185 | − val = REG_SET_FLD_NUM(VPU_40XX_BUTTRESS_WP_REQ_PAYLOAD1, EPP, epp, val); | |
| 186 | − REGB_WR32(VPU_40XX_BUTTRESS_WP_REQ_PAYLOAD1, val); | |
| 187 | − | |
| 188 | − val = REGB_RD32(VPU_40XX_BUTTRESS_WP_REQ_PAYLOAD2); | |
| 189 | − val = REG_SET_FLD_NUM(VPU_40XX_BUTTRESS_WP_REQ_PAYLOAD2, CONFIG, config, val); | |
| 190 | − val = REG_SET_FLD_NUM(VPU_40XX_BUTTRESS_WP_REQ_PAYLOAD2, CDYN, cdyn, val); | |
| 191 | − REGB_WR32(VPU_40XX_BUTTRESS_WP_REQ_PAYLOAD2, val); | |
| 192 | − | |
| 193 | − val = REGB_RD32(VPU_40XX_BUTTRESS_WP_REQ_CMD); | |
| 194 | − val = REG_SET_FLD(VPU_40XX_BUTTRESS_WP_REQ_CMD, SEND, val); | |
| 195 | − REGB_WR32(VPU_40XX_BUTTRESS_WP_REQ_CMD, val); | |
| 196 | − | |
| 197 | − ret = ivpu_pll_wait_for_cmd_send(vdev); | |
| 198 | − if (ret) | |
| 199 | − ivpu_err(vdev, "Failed to sync after WP request: %d\n", ret); | |
| 200 | − | |
| 201 | − return ret; | |
| 202 | −} | |
| 203 | − | |
| 204 | −static int ivpu_pll_wait_for_status_ready(struct ivpu_device *vdev) | |
| 205 | −{ | |
| 206 | − return REGB_POLL_FLD(VPU_40XX_BUTTRESS_VPU_STATUS, READY, 1, PLL_TIMEOUT_US); | |
| 207 | −} | |
| 208 | − | |
| 209 | −static int ivpu_wait_for_clock_own_resource_ack(struct ivpu_device *vdev) | |
| 210 | −{ | |
| 211 | − if (ivpu_is_simics(vdev)) | |
| 212 | − return 0; | |
| 213 | − | |
| 214 | − return REGB_POLL_FLD(VPU_40XX_BUTTRESS_VPU_STATUS, CLOCK_RESOURCE_OWN_ACK, 1, TIMEOUT_US); | |
| 215 | −} | |
| 216 | − | |
| 217 | −static void ivpu_pll_init_frequency_ratios(struct ivpu_device *vdev) | |
| 218 | −{ | |
| 219 | − struct ivpu_hw_info *hw = vdev->hw; | |
| 220 | − u8 fuse_min_ratio, fuse_pn_ratio, fuse_max_ratio; | |
| 221 | − u32 fmin_fuse, fmax_fuse; | |
| 222 | − | |
| 223 | − fmin_fuse = REGB_RD32(VPU_40XX_BUTTRESS_FMIN_FUSE); | |
| 224 | − fuse_min_ratio = REG_GET_FLD(VPU_40XX_BUTTRESS_FMIN_FUSE, MIN_RATIO, fmin_fuse); | |
| 225 | − fuse_pn_ratio = REG_GET_FLD(VPU_40XX_BUTTRESS_FMIN_FUSE, PN_RATIO, fmin_fuse); | |
| 226 | − | |
| 227 | − fmax_fuse = REGB_RD32(VPU_40XX_BUTTRESS_FMAX_FUSE); | |
| 228 | − fuse_max_ratio = REG_GET_FLD(VPU_40XX_BUTTRESS_FMAX_FUSE, MAX_RATIO, fmax_fuse); | |
| 229 | − | |
| 230 | − hw->pll.min_ratio = clamp_t(u8, ivpu_pll_min_ratio, fuse_min_ratio, fuse_max_ratio); | |
| 231 | − hw->pll.max_ratio = clamp_t(u8, ivpu_pll_max_ratio, hw->pll.min_ratio, fuse_max_ratio); | |
| 232 | − hw->pll.pn_ratio = clamp_t(u8, fuse_pn_ratio, hw->pll.min_ratio, hw->pll.max_ratio); | |
| 233 | −} | |
| 234 | − | |
| 235 | −static int ivpu_pll_drive(struct ivpu_device *vdev, bool enable) | |
| 236 | −{ | |
| 237 | − u16 config = enable ? PLL_CONFIG_DEFAULT : 0; | |
| 238 | − u16 cdyn = enable ? PLL_CDYN_DEFAULT : 0; | |
| 239 | − u16 epp = enable ? PLL_EPP_DEFAULT : 0; | |
| 240 | − struct ivpu_hw_info *hw = vdev->hw; | |
| 241 | − u16 target_ratio = hw->pll.pn_ratio; | |
| 242 | − int ret; | |
| 243 | − | |
| 244 | − ivpu_dbg(vdev, PM, "PLL workpoint request: %u Hz, epp: 0x%x, config: 0x%x, cdyn: 0x%x\n", | |
| 245 | − PLL_RATIO_TO_FREQ(target_ratio), epp, config, cdyn); | |
| 246 | − | |
| 247 | − ret = ivpu_pll_cmd_send(vdev, hw->pll.min_ratio, hw->pll.max_ratio, | |
| 248 | − target_ratio, epp, config, cdyn); | |
| 249 | − if (ret) { | |
| 250 | − ivpu_err(vdev, "Failed to send PLL workpoint request: %d\n", ret); | |
| 251 | − return ret; | |
| 252 | − } | |
| 253 | − | |
| 254 | − if (enable) { | |
| 255 | − ret = ivpu_pll_wait_for_status_ready(vdev); | |
| 256 | − if (ret) { | |
| 257 | − ivpu_err(vdev, "Timed out waiting for PLL ready status\n"); | |
| 258 | − return ret; | |
| 259 | − } | |
| 260 | − } | |
| 261 | − | |
| 262 | − return 0; | |
| 263 | −} | |
| 264 | − | |
| 265 | −static int ivpu_pll_enable(struct ivpu_device *vdev) | |
| 266 | −{ | |
| 267 | − return ivpu_pll_drive(vdev, true); | |
| 268 | −} | |
| 269 | − | |
| 270 | −static int ivpu_pll_disable(struct ivpu_device *vdev) | |
| 271 | −{ | |
| 272 | − return ivpu_pll_drive(vdev, false); | |
| 273 | −} | |
| 274 | − | |
| 275 | −static void ivpu_boot_host_ss_rst_drive(struct ivpu_device *vdev, bool enable) | |
| 276 | −{ | |
| 277 | − u32 val = REGV_RD32(VPU_40XX_HOST_SS_CPR_RST_EN); | |
| 278 | − | |
| 279 | − if (enable) { | |
| 280 | − val = REG_SET_FLD(VPU_40XX_HOST_SS_CPR_RST_EN, TOP_NOC, val); | |
| 281 | − val = REG_SET_FLD(VPU_40XX_HOST_SS_CPR_RST_EN, DSS_MAS, val); | |
| 282 | − val = REG_SET_FLD(VPU_40XX_HOST_SS_CPR_RST_EN, CSS_MAS, val); | |
| 283 | − } else { | |
| 284 | − val = REG_CLR_FLD(VPU_40XX_HOST_SS_CPR_RST_EN, TOP_NOC, val); | |
| 285 | − val = REG_CLR_FLD(VPU_40XX_HOST_SS_CPR_RST_EN, DSS_MAS, val); | |
| 286 | − val = REG_CLR_FLD(VPU_40XX_HOST_SS_CPR_RST_EN, CSS_MAS, val); | |
| 287 | − } | |
| 288 | − | |
| 289 | − REGV_WR32(VPU_40XX_HOST_SS_CPR_RST_EN, val); | |
| 290 | −} | |
| 291 | − | |
| 292 | −static void ivpu_boot_host_ss_clk_drive(struct ivpu_device *vdev, bool enable) | |
| 293 | −{ | |
| 294 | − u32 val = REGV_RD32(VPU_40XX_HOST_SS_CPR_CLK_EN); | |
| 295 | − | |
| 296 | − if (enable) { | |
| 297 | − val = REG_SET_FLD(VPU_40XX_HOST_SS_CPR_CLK_EN, TOP_NOC, val); | |
| 298 | − val = REG_SET_FLD(VPU_40XX_HOST_SS_CPR_CLK_EN, DSS_MAS, val); | |
| 299 | − val = REG_SET_FLD(VPU_40XX_HOST_SS_CPR_CLK_EN, CSS_MAS, val); | |
| 300 | − } else { | |
| 301 | − val = REG_CLR_FLD(VPU_40XX_HOST_SS_CPR_CLK_EN, TOP_NOC, val); | |
| 302 | − val = REG_CLR_FLD(VPU_40XX_HOST_SS_CPR_CLK_EN, DSS_MAS, val); | |
| 303 | − val = REG_CLR_FLD(VPU_40XX_HOST_SS_CPR_CLK_EN, CSS_MAS, val); | |
| 304 | − } | |
| 305 | − | |
| 306 | − REGV_WR32(VPU_40XX_HOST_SS_CPR_CLK_EN, val); | |
| 307 | −} | |
| 308 | − | |
| 309 | −static int ivpu_boot_noc_qreqn_check(struct ivpu_device *vdev, u32 exp_val) | |
| 310 | −{ | |
| 311 | − u32 val = REGV_RD32(VPU_40XX_HOST_SS_NOC_QREQN); | |
| 312 | − | |
| 313 | − if (!REG_TEST_FLD_NUM(VPU_40XX_HOST_SS_NOC_QREQN, TOP_SOCMMIO, exp_val, val)) | |
| 314 | − return -EIO; | |
| 315 | − | |
| 316 | − return 0; | |
| 317 | −} | |
| 318 | − | |
| 319 | −static int ivpu_boot_noc_qacceptn_check(struct ivpu_device *vdev, u32 exp_val) | |
| 320 | −{ | |
| 321 | − u32 val = REGV_RD32(VPU_40XX_HOST_SS_NOC_QACCEPTN); | |
| 322 | − | |
| 323 | − if (!REG_TEST_FLD_NUM(VPU_40XX_HOST_SS_NOC_QACCEPTN, TOP_SOCMMIO, exp_val, val)) | |
| 324 | − return -EIO; | |
| 325 | − | |
| 326 | − return 0; | |
| 327 | −} | |
| 328 | − | |
| 329 | −static int ivpu_boot_noc_qdeny_check(struct ivpu_device *vdev, u32 exp_val) | |
| 330 | −{ | |
| 331 | − u32 val = REGV_RD32(VPU_40XX_HOST_SS_NOC_QDENY); | |
| 332 | − | |
| 333 | − if (!REG_TEST_FLD_NUM(VPU_40XX_HOST_SS_NOC_QDENY, TOP_SOCMMIO, exp_val, val)) | |
| 334 | − return -EIO; | |
| 335 | − | |
| 336 | − return 0; | |
| 337 | −} | |
| 338 | − | |
| 339 | −static int ivpu_boot_top_noc_qrenqn_check(struct ivpu_device *vdev, u32 exp_val) | |
| 340 | −{ | |
| 341 | − u32 val = REGV_RD32(VPU_40XX_TOP_NOC_QREQN); | |
| 342 | − | |
| 343 | − if (!REG_TEST_FLD_NUM(VPU_40XX_TOP_NOC_QREQN, CPU_CTRL, exp_val, val) || | |
| 344 | − !REG_TEST_FLD_NUM(VPU_40XX_TOP_NOC_QREQN, HOSTIF_L2CACHE, exp_val, val)) | |
| 345 | − return -EIO; | |
| 346 | − | |
| 347 | − return 0; | |
| 348 | −} | |
| 349 | − | |
| 350 | −static int ivpu_boot_top_noc_qacceptn_check(struct ivpu_device *vdev, u32 exp_val) | |
| 351 | −{ | |
| 352 | − u32 val = REGV_RD32(VPU_40XX_TOP_NOC_QACCEPTN); | |
| 353 | − | |
| 354 | − if (!REG_TEST_FLD_NUM(VPU_40XX_TOP_NOC_QACCEPTN, CPU_CTRL, exp_val, val) || | |
| 355 | − !REG_TEST_FLD_NUM(VPU_40XX_TOP_NOC_QACCEPTN, HOSTIF_L2CACHE, exp_val, val)) | |
| 356 | − return -EIO; | |
| 357 | − | |
| 358 | − return 0; | |
| 359 | −} | |
| 360 | − | |
| 361 | −static int ivpu_boot_top_noc_qdeny_check(struct ivpu_device *vdev, u32 exp_val) | |
| 362 | −{ | |
| 363 | − u32 val = REGV_RD32(VPU_40XX_TOP_NOC_QDENY); | |
| 364 | − | |
| 365 | − if (!REG_TEST_FLD_NUM(VPU_40XX_TOP_NOC_QDENY, CPU_CTRL, exp_val, val) || | |
| 366 | − !REG_TEST_FLD_NUM(VPU_40XX_TOP_NOC_QDENY, HOSTIF_L2CACHE, exp_val, val)) | |
| 367 | − return -EIO; | |
| 368 | − | |
| 369 | − return 0; | |
| 370 | −} | |
| 371 | − | |
| 372 | −static void ivpu_boot_idle_gen_drive(struct ivpu_device *vdev, bool enable) | |
| 373 | −{ | |
| 374 | − u32 val = REGV_RD32(VPU_40XX_HOST_SS_AON_IDLE_GEN); | |
| 375 | − | |
| 376 | − if (enable) | |
| 377 | − val = REG_SET_FLD(VPU_40XX_HOST_SS_AON_IDLE_GEN, EN, val); | |
| 378 | − else | |
| 379 | − val = REG_CLR_FLD(VPU_40XX_HOST_SS_AON_IDLE_GEN, EN, val); | |
| 380 | − | |
| 381 | − REGV_WR32(VPU_40XX_HOST_SS_AON_IDLE_GEN, val); | |
| 382 | −} | |
| 383 | − | |
| 384 | −static int ivpu_boot_host_ss_check(struct ivpu_device *vdev) | |
| 385 | −{ | |
| 386 | − int ret; | |
| 387 | − | |
| 388 | − ret = ivpu_boot_noc_qreqn_check(vdev, 0x0); | |
| 389 | − if (ret) { | |
| 390 | − ivpu_err(vdev, "Failed qreqn check: %d\n", ret); | |
| 391 | − return ret; | |
| 392 | − } | |
| 393 | − | |
| 394 | − ret = ivpu_boot_noc_qacceptn_check(vdev, 0x0); | |
| 395 | − if (ret) { | |
| 396 | − ivpu_err(vdev, "Failed qacceptn check: %d\n", ret); | |
| 397 | − return ret; | |
| 398 | − } | |
| 399 | − | |
| 400 | − ret = ivpu_boot_noc_qdeny_check(vdev, 0x0); | |
| 401 | − if (ret) | |
| 402 | − ivpu_err(vdev, "Failed qdeny check %d\n", ret); | |
| 403 | − | |
| 404 | − return ret; | |
| 405 | −} | |
| 406 | − | |
| 407 | −static int ivpu_boot_host_ss_axi_drive(struct ivpu_device *vdev, bool enable) | |
| 408 | −{ | |
| 409 | − int ret; | |
| 410 | − u32 val; | |
| 411 | − | |
| 412 | − val = REGV_RD32(VPU_40XX_HOST_SS_NOC_QREQN); | |
| 413 | − if (enable) | |
| 414 | − val = REG_SET_FLD(VPU_40XX_HOST_SS_NOC_QREQN, TOP_SOCMMIO, val); | |
| 415 | − else | |
| 416 | − val = REG_CLR_FLD(VPU_40XX_HOST_SS_NOC_QREQN, TOP_SOCMMIO, val); | |
| 417 | − REGV_WR32(VPU_40XX_HOST_SS_NOC_QREQN, val); | |
| 418 | − | |
| 419 | − ret = ivpu_boot_noc_qacceptn_check(vdev, enable ? 0x1 : 0x0); | |
| 420 | − if (ret) { | |
| 421 | − ivpu_err(vdev, "Failed qacceptn check: %d\n", ret); | |
| 422 | − return ret; | |
| 423 | − } | |
| 424 | − | |
| 425 | − ret = ivpu_boot_noc_qdeny_check(vdev, 0x0); | |
| 426 | − if (ret) { | |
| 427 | − ivpu_err(vdev, "Failed qdeny check: %d\n", ret); | |
| 428 | − return ret; | |
| 429 | − } | |
| 430 | − | |
| 431 | − if (enable) { | |
| 432 | − REGB_WR32(VPU_40XX_BUTTRESS_PORT_ARBITRATION_WEIGHTS, WEIGHTS_DEFAULT); | |
| 433 | − REGB_WR32(VPU_40XX_BUTTRESS_PORT_ARBITRATION_WEIGHTS_ATS, WEIGHTS_ATS_DEFAULT); | |
| 434 | − } | |
| 435 | − | |
| 436 | − return ret; | |
| 437 | −} | |
| 438 | − | |
| 439 | −static int ivpu_boot_host_ss_axi_enable(struct ivpu_device *vdev) | |
| 440 | −{ | |
| 441 | − return ivpu_boot_host_ss_axi_drive(vdev, true); | |
| 442 | −} | |
| 443 | − | |
| 444 | −static int ivpu_boot_host_ss_top_noc_drive(struct ivpu_device *vdev, bool enable) | |
| 445 | −{ | |
| 446 | − int ret; | |
| 447 | − u32 val; | |
| 448 | − | |
| 449 | − val = REGV_RD32(VPU_40XX_TOP_NOC_QREQN); | |
| 450 | − if (enable) { | |
| 451 | − val = REG_SET_FLD(VPU_40XX_TOP_NOC_QREQN, CPU_CTRL, val); | |
| 452 | − val = REG_SET_FLD(VPU_40XX_TOP_NOC_QREQN, HOSTIF_L2CACHE, val); | |
| 453 | − } else { | |
| 454 | − val = REG_CLR_FLD(VPU_40XX_TOP_NOC_QREQN, CPU_CTRL, val); | |
| 455 | − val = REG_CLR_FLD(VPU_40XX_TOP_NOC_QREQN, HOSTIF_L2CACHE, val); | |
| 456 | − } | |
| 457 | − REGV_WR32(VPU_40XX_TOP_NOC_QREQN, val); | |
| 458 | − | |
| 459 | − ret = ivpu_boot_top_noc_qacceptn_check(vdev, enable ? 0x1 : 0x0); | |
| 460 | − if (ret) { | |
| 461 | − ivpu_err(vdev, "Failed qacceptn check: %d\n", ret); | |
| 462 | − return ret; | |
| 463 | − } | |
| 464 | − | |
| 465 | − ret = ivpu_boot_top_noc_qdeny_check(vdev, 0x0); | |
| 466 | − if (ret) | |
| 467 | − ivpu_err(vdev, "Failed qdeny check: %d\n", ret); | |
| 468 | − | |
| 469 | − return ret; | |
| 470 | −} | |
| 471 | − | |
| 472 | −static int ivpu_boot_host_ss_top_noc_enable(struct ivpu_device *vdev) | |
| 473 | −{ | |
| 474 | − return ivpu_boot_host_ss_top_noc_drive(vdev, true); | |
| 475 | −} | |
| 476 | − | |
| 477 | −static void ivpu_boot_pwr_island_trickle_drive(struct ivpu_device *vdev, bool enable) | |
| 478 | −{ | |
| 479 | − u32 val = REGV_RD32(VPU_40XX_HOST_SS_AON_PWR_ISLAND_TRICKLE_EN0); | |
| 480 | − | |
| 481 | − if (enable) | |
| 482 | − val = REG_SET_FLD(VPU_40XX_HOST_SS_AON_PWR_ISLAND_TRICKLE_EN0, CSS_CPU, val); | |
| 483 | − else | |
| 484 | − val = REG_CLR_FLD(VPU_40XX_HOST_SS_AON_PWR_ISLAND_TRICKLE_EN0, CSS_CPU, val); | |
| 485 | − | |
| 486 | − REGV_WR32(VPU_40XX_HOST_SS_AON_PWR_ISLAND_TRICKLE_EN0, val); | |
| 487 | − | |
| 488 | − if (enable) | |
| 489 | − ndelay(500); | |
| 490 | −} | |
| 491 | − | |
| 492 | −static void ivpu_boot_pwr_island_drive(struct ivpu_device *vdev, bool enable) | |
| 493 | −{ | |
| 494 | − u32 val = REGV_RD32(VPU_40XX_HOST_SS_AON_PWR_ISLAND_EN0); | |
| 495 | − | |
| 496 | − if (enable) | |
| 497 | − val = REG_SET_FLD(VPU_40XX_HOST_SS_AON_PWR_ISLAND_EN0, CSS_CPU, val); | |
| 498 | − else | |
| 499 | − val = REG_CLR_FLD(VPU_40XX_HOST_SS_AON_PWR_ISLAND_EN0, CSS_CPU, val); | |
| 500 | − | |
| 501 | − REGV_WR32(VPU_40XX_HOST_SS_AON_PWR_ISLAND_EN0, val); | |
| 502 | − | |
| 503 | − if (!enable) | |
| 504 | − ndelay(500); | |
| 505 | −} | |
| 506 | − | |
| 507 | −static int ivpu_boot_wait_for_pwr_island_status(struct ivpu_device *vdev, u32 exp_val) | |
| 508 | −{ | |
| 509 | − if (ivpu_is_fpga(vdev)) | |
| 510 | − return 0; | |
| 511 | − | |
| 512 | − return REGV_POLL_FLD(VPU_40XX_HOST_SS_AON_PWR_ISLAND_STATUS0, CSS_CPU, | |
| 513 | − exp_val, PWR_ISLAND_STATUS_TIMEOUT_US); | |
| 514 | −} | |
| 515 | − | |
| 516 | −static void ivpu_boot_pwr_island_isolation_drive(struct ivpu_device *vdev, bool enable) | |
| 517 | −{ | |
| 518 | − u32 val = REGV_RD32(VPU_40XX_HOST_SS_AON_PWR_ISO_EN0); | |
| 519 | − | |
| 520 | − if (enable) | |
| 521 | − val = REG_SET_FLD(VPU_40XX_HOST_SS_AON_PWR_ISO_EN0, CSS_CPU, val); | |
| 522 | − else | |
| 523 | − val = REG_CLR_FLD(VPU_40XX_HOST_SS_AON_PWR_ISO_EN0, CSS_CPU, val); | |
| 524 | − | |
| 525 | − REGV_WR32(VPU_40XX_HOST_SS_AON_PWR_ISO_EN0, val); | |
| 526 | −} | |
| 527 | − | |
| 528 | −static void ivpu_boot_no_snoop_enable(struct ivpu_device *vdev) | |
| 529 | −{ | |
| 530 | − u32 val = REGV_RD32(VPU_40XX_HOST_IF_TCU_PTW_OVERRIDES); | |
| 531 | − | |
| 532 | − val = REG_SET_FLD(VPU_40XX_HOST_IF_TCU_PTW_OVERRIDES, SNOOP_OVERRIDE_EN, val); | |
| 533 | − val = REG_SET_FLD(VPU_40XX_HOST_IF_TCU_PTW_OVERRIDES, AW_SNOOP_OVERRIDE, val); | |
| 534 | − val = REG_CLR_FLD(VPU_40XX_HOST_IF_TCU_PTW_OVERRIDES, AR_SNOOP_OVERRIDE, val); | |
| 535 | − | |
| 536 | − REGV_WR32(VPU_40XX_HOST_IF_TCU_PTW_OVERRIDES, val); | |
| 537 | −} | |
| 538 | − | |
| 539 | −static void ivpu_boot_tbu_mmu_enable(struct ivpu_device *vdev) | |
| 540 | −{ | |
| 541 | − u32 val = REGV_RD32(VPU_40XX_HOST_IF_TBU_MMUSSIDV); | |
| 542 | − | |
| 543 | − val = REG_SET_FLD(VPU_40XX_HOST_IF_TBU_MMUSSIDV, TBU0_AWMMUSSIDV, val); | |
| 544 | − val = REG_SET_FLD(VPU_40XX_HOST_IF_TBU_MMUSSIDV, TBU0_ARMMUSSIDV, val); | |
| 545 | − val = REG_SET_FLD(VPU_40XX_HOST_IF_TBU_MMUSSIDV, TBU1_AWMMUSSIDV, val); | |
| 546 | − val = REG_SET_FLD(VPU_40XX_HOST_IF_TBU_MMUSSIDV, TBU1_ARMMUSSIDV, val); | |
| 547 | − val = REG_SET_FLD(VPU_40XX_HOST_IF_TBU_MMUSSIDV, TBU2_AWMMUSSIDV, val); | |
| 548 | − val = REG_SET_FLD(VPU_40XX_HOST_IF_TBU_MMUSSIDV, TBU2_ARMMUSSIDV, val); | |
| 549 | − | |
| 550 | − REGV_WR32(VPU_40XX_HOST_IF_TBU_MMUSSIDV, val); | |
| 551 | −} | |
| 552 | − | |
| 553 | −static int ivpu_boot_cpu_noc_qacceptn_check(struct ivpu_device *vdev, u32 exp_val) | |
| 554 | −{ | |
| 555 | − u32 val = REGV_RD32(VPU_40XX_CPU_SS_CPR_NOC_QACCEPTN); | |
| 556 | − | |
| 557 | − if (!REG_TEST_FLD_NUM(VPU_40XX_CPU_SS_CPR_NOC_QACCEPTN, TOP_MMIO, exp_val, val)) | |
| 558 | − return -EIO; | |
| 559 | − | |
| 560 | − return 0; | |
| 561 | −} | |
| 562 | − | |
| 563 | −static int ivpu_boot_cpu_noc_qdeny_check(struct ivpu_device *vdev, u32 exp_val) | |
| 564 | −{ | |
| 565 | − u32 val = REGV_RD32(VPU_40XX_CPU_SS_CPR_NOC_QDENY); | |
| 566 | − | |
| 567 | − if (!REG_TEST_FLD_NUM(VPU_40XX_CPU_SS_CPR_NOC_QDENY, TOP_MMIO, exp_val, val)) | |
| 568 | − return -EIO; | |
| 569 | − | |
| 570 | − return 0; | |
| 571 | −} | |
| 572 | − | |
| 573 | −static int ivpu_boot_pwr_domain_enable(struct ivpu_device *vdev) | |
| 574 | −{ | |
| 575 | − int ret; | |
| 576 | − | |
| 577 | − ret = ivpu_wait_for_clock_own_resource_ack(vdev); | |
| 578 | − if (ret) { | |
| 579 | − ivpu_err(vdev, "Timed out waiting for clock own resource ACK\n"); | |
| 580 | − return ret; | |
| 581 | − } | |
| 582 | − | |
| 583 | − ivpu_boot_pwr_island_trickle_drive(vdev, true); | |
| 584 | − ivpu_boot_pwr_island_drive(vdev, true); | |
| 585 | − | |
| 586 | − ret = ivpu_boot_wait_for_pwr_island_status(vdev, 0x1); | |
| 587 | − if (ret) { | |
| 588 | − ivpu_err(vdev, "Timed out waiting for power island status\n"); | |
| 589 | − return ret; | |
| 590 | − } | |
| 591 | − | |
| 592 | − ret = ivpu_boot_top_noc_qrenqn_check(vdev, 0x0); | |
| 593 | − if (ret) { | |
| 594 | − ivpu_err(vdev, "Failed qrenqn check %d\n", ret); | |
| 595 | − return ret; | |
| 596 | − } | |
| 597 | − | |
| 598 | − ivpu_boot_host_ss_clk_drive(vdev, true); | |
| 599 | − ivpu_boot_host_ss_rst_drive(vdev, true); | |
| 600 | − ivpu_boot_pwr_island_isolation_drive(vdev, false); | |
| 601 | − | |
| 602 | − return ret; | |
| 603 | −} | |
| 604 | − | |
| 605 | −static int ivpu_boot_soc_cpu_drive(struct ivpu_device *vdev, bool enable) | |
| 606 | −{ | |
| 607 | − int ret; | |
| 608 | − u32 val; | |
| 609 | − | |
| 610 | − val = REGV_RD32(VPU_40XX_CPU_SS_CPR_NOC_QREQN); | |
| 611 | − if (enable) | |
| 612 | − val = REG_SET_FLD(VPU_40XX_CPU_SS_CPR_NOC_QREQN, TOP_MMIO, val); | |
| 613 | − else | |
| 614 | − val = REG_CLR_FLD(VPU_40XX_CPU_SS_CPR_NOC_QREQN, TOP_MMIO, val); | |
| 615 | − REGV_WR32(VPU_40XX_CPU_SS_CPR_NOC_QREQN, val); | |
| 616 | − | |
| 617 | − ret = ivpu_boot_cpu_noc_qacceptn_check(vdev, enable ? 0x1 : 0x0); | |
| 618 | − if (ret) { | |
| 619 | − ivpu_err(vdev, "Failed qacceptn check: %d\n", ret); | |
| 620 | − return ret; | |
| 621 | − } | |
| 622 | − | |
| 623 | − ret = ivpu_boot_cpu_noc_qdeny_check(vdev, 0x0); | |
| 624 | − if (ret) | |
| 625 | − ivpu_err(vdev, "Failed qdeny check: %d\n", ret); | |
| 626 | − | |
| 627 | − return ret; | |
| 628 | −} | |
| 629 | − | |
| 630 | −static int ivpu_boot_soc_cpu_enable(struct ivpu_device *vdev) | |
| 631 | −{ | |
| 632 | − return ivpu_boot_soc_cpu_drive(vdev, true); | |
| 633 | −} | |
| 634 | − | |
| 635 | −static int ivpu_boot_soc_cpu_boot(struct ivpu_device *vdev) | |
| 636 | −{ | |
| 637 | − int ret; | |
| 638 | − u32 val; | |
| 639 | − u64 val64; | |
| 640 | − | |
| 641 | − ret = ivpu_boot_soc_cpu_enable(vdev); | |
| 642 | − if (ret) { | |
| 643 | − ivpu_err(vdev, "Failed to enable SOC CPU: %d\n", ret); | |
| 644 | − return ret; | |
| 645 | − } | |
| 646 | − | |
| 647 | − val64 = vdev->fw->entry_point; | |
| 648 | − val64 <<= ffs(VPU_40XX_HOST_SS_VERIFICATION_ADDRESS_LO_IMAGE_LOCATION_MASK) - 1; | |
| 649 | − REGV_WR64(VPU_40XX_HOST_SS_VERIFICATION_ADDRESS_LO, val64); | |
| 650 | − | |
| 651 | − val = REGV_RD32(VPU_40XX_HOST_SS_VERIFICATION_ADDRESS_LO); | |
| 652 | − val = REG_SET_FLD(VPU_40XX_HOST_SS_VERIFICATION_ADDRESS_LO, DONE, val); | |
| 653 | − REGV_WR32(VPU_40XX_HOST_SS_VERIFICATION_ADDRESS_LO, val); | |
| 654 | − | |
| 655 | − ivpu_dbg(vdev, PM, "Booting firmware, mode: %s\n", | |
| 656 | − ivpu_fw_is_cold_boot(vdev) ? "cold boot" : "resume"); | |
| 657 | − | |
| 658 | − return 0; | |
| 659 | −} | |
| 660 | − | |
| 661 | −static int ivpu_boot_d0i3_drive(struct ivpu_device *vdev, bool enable) | |
| 662 | −{ | |
| 663 | − int ret; | |
| 664 | − u32 val; | |
| 665 | − | |
| 666 | − ret = REGB_POLL_FLD(VPU_40XX_BUTTRESS_D0I3_CONTROL, INPROGRESS, 0, TIMEOUT_US); | |
| 667 | − if (ret) { | |
| 668 | − ivpu_err(vdev, "Failed to sync before D0i3 transition: %d\n", ret); | |
| 669 | − return ret; | |
| 670 | − } | |
| 671 | − | |
| 672 | − val = REGB_RD32(VPU_40XX_BUTTRESS_D0I3_CONTROL); | |
| 673 | − if (enable) | |
| 674 | − val = REG_SET_FLD(VPU_40XX_BUTTRESS_D0I3_CONTROL, I3, val); | |
| 675 | − else | |
| 676 | − val = REG_CLR_FLD(VPU_40XX_BUTTRESS_D0I3_CONTROL, I3, val); | |
| 677 | − REGB_WR32(VPU_40XX_BUTTRESS_D0I3_CONTROL, val); | |
| 678 | − | |
| 679 | − ret = REGB_POLL_FLD(VPU_40XX_BUTTRESS_D0I3_CONTROL, INPROGRESS, 0, TIMEOUT_US); | |
| 680 | − if (ret) { | |
| 681 | − ivpu_err(vdev, "Failed to sync after D0i3 transition: %d\n", ret); | |
| 682 | − return ret; | |
| 683 | − } | |
| 684 | − | |
| 685 | − return 0; | |
| 686 | −} | |
| 687 | − | |
| 688 | −static bool ivpu_tile_disable_check(u32 config) | |
| 689 | −{ | |
| 690 | − /* Allowed values: 0 or one bit from range 0-5 (6 tiles) */ | |
| 691 | − if (config == 0) | |
| 692 | − return true; | |
| 693 | − | |
| 694 | − if (config > BIT(TILE_MAX_NUM - 1)) | |
| 695 | − return false; | |
| 696 | − | |
| 697 | − if ((config & (config - 1)) == 0) | |
| 698 | − return true; | |
| 699 | − | |
| 700 | − return false; | |
| 701 | −} | |
| 702 | − | |
| 703 | −static int ivpu_hw_40xx_info_init(struct ivpu_device *vdev) | |
| 704 | −{ | |
| 705 | − struct ivpu_hw_info *hw = vdev->hw; | |
| 706 | − u32 tile_disable; | |
| 707 | − u32 fuse; | |
| 708 | − | |
| 709 | − fuse = REGB_RD32(VPU_40XX_BUTTRESS_TILE_FUSE); | |
| 710 | − if (!REG_TEST_FLD(VPU_40XX_BUTTRESS_TILE_FUSE, VALID, fuse)) { | |
| 711 | − ivpu_err(vdev, "Fuse: invalid (0x%x)\n", fuse); | |
| 712 | − return -EIO; | |
| 713 | − } | |
| 714 | − | |
| 715 | − tile_disable = REG_GET_FLD(VPU_40XX_BUTTRESS_TILE_FUSE, CONFIG, fuse); | |
| 716 | − if (!ivpu_tile_disable_check(tile_disable)) { | |
| 717 | − ivpu_err(vdev, "Fuse: Invalid tile disable config (0x%x)\n", tile_disable); | |
| 718 | − return -EIO; | |
| 719 | − } | |
| 720 | − | |
| 721 | − if (tile_disable) | |
| 722 | − ivpu_dbg(vdev, MISC, "Fuse: %d tiles enabled. Tile number %d disabled\n", | |
| 723 | − TILE_MAX_NUM - 1, ffs(tile_disable) - 1); | |
| 724 | − else | |
| 725 | − ivpu_dbg(vdev, MISC, "Fuse: All %d tiles enabled\n", TILE_MAX_NUM); | |
| 726 | − | |
| 727 | − hw->tile_fuse = tile_disable; | |
| 728 | − hw->pll.profiling_freq = PLL_PROFILING_FREQ_DEFAULT; | |
| 729 | − | |
| 730 | − ivpu_pll_init_frequency_ratios(vdev); | |
| 731 | − | |
| 732 | − ivpu_hw_init_range(&vdev->hw->ranges.global, 0x80000000, SZ_512M); | |
| 733 | − ivpu_hw_init_range(&vdev->hw->ranges.user, 0x80000000, SZ_256M); | |
| 734 | − ivpu_hw_init_range(&vdev->hw->ranges.shave, 0x80000000 + SZ_256M, SZ_2G - SZ_256M); | |
| 735 | − ivpu_hw_init_range(&vdev->hw->ranges.dma, 0x200000000, SZ_8G); | |
| 736 | − | |
| 737 | − ivpu_hw_read_platform(vdev); | |
| 738 | − ivpu_hw_wa_init(vdev); | |
| 739 | − ivpu_hw_timeouts_init(vdev); | |
| 740 | − | |
| 741 | − return 0; | |
| 742 | −} | |
| 743 | − | |
| 744 | −static int ivpu_hw_40xx_ip_reset(struct ivpu_device *vdev) | |
| 745 | −{ | |
| 746 | − int ret; | |
| 747 | − u32 val; | |
| 748 | − | |
| 749 | − ret = REGB_POLL_FLD(VPU_40XX_BUTTRESS_IP_RESET, TRIGGER, 0, TIMEOUT_US); | |
| 750 | − if (ret) { | |
| 751 | − ivpu_err(vdev, "Wait for *_TRIGGER timed out\n"); | |
| 752 | − return ret; | |
| 753 | − } | |
| 754 | − | |
| 755 | − val = REGB_RD32(VPU_40XX_BUTTRESS_IP_RESET); | |
| 756 | − val = REG_SET_FLD(VPU_40XX_BUTTRESS_IP_RESET, TRIGGER, val); | |
| 757 | − REGB_WR32(VPU_40XX_BUTTRESS_IP_RESET, val); | |
| 758 | − | |
| 759 | − ret = REGB_POLL_FLD(VPU_40XX_BUTTRESS_IP_RESET, TRIGGER, 0, TIMEOUT_US); | |
| 760 | − if (ret) | |
| 761 | − ivpu_err(vdev, "Timed out waiting for RESET completion\n"); | |
| 762 | − | |
| 763 | − return ret; | |
| 764 | −} | |
| 765 | − | |
| 766 | −static int ivpu_hw_40xx_reset(struct ivpu_device *vdev) | |
| 767 | −{ | |
| 768 | − int ret = 0; | |
| 769 | − | |
| 770 | − if (ivpu_hw_40xx_ip_reset(vdev)) { | |
| 771 | − ivpu_err(vdev, "Failed to reset NPU IP\n"); | |
| 772 | − ret = -EIO; | |
| 773 | − } | |
| 774 | − | |
| 775 | − if (ivpu_pll_disable(vdev)) { | |
| 776 | − ivpu_err(vdev, "Failed to disable PLL\n"); | |
| 777 | − ret = -EIO; | |
| 778 | − } | |
| 779 | − | |
| 780 | − return ret; | |
| 781 | −} | |
| 782 | − | |
| 783 | −static int ivpu_hw_40xx_d0i3_enable(struct ivpu_device *vdev) | |
| 784 | −{ | |
| 785 | − int ret; | |
| 786 | − | |
| 787 | − if (IVPU_WA(punit_disabled)) | |
| 788 | − return 0; | |
| 789 | − | |
| 790 | − ret = ivpu_boot_d0i3_drive(vdev, true); | |
| 791 | − if (ret) | |
| 792 | − ivpu_err(vdev, "Failed to enable D0i3: %d\n", ret); | |
| 793 | − | |
| 794 | − udelay(5); /* VPU requires 5 us to complete the transition */ | |
| 795 | − | |
| 796 | − return ret; | |
| 797 | −} | |
| 798 | − | |
| 799 | −static int ivpu_hw_40xx_d0i3_disable(struct ivpu_device *vdev) | |
| 800 | −{ | |
| 801 | − int ret; | |
| 802 | − | |
| 803 | − if (IVPU_WA(punit_disabled)) | |
| 804 | − return 0; | |
| 805 | − | |
| 806 | − ret = ivpu_boot_d0i3_drive(vdev, false); | |
| 807 | − if (ret) | |
| 808 | − ivpu_err(vdev, "Failed to disable D0i3: %d\n", ret); | |
| 809 | − | |
| 810 | − return ret; | |
| 811 | −} | |
| 812 | − | |
| 813 | −static void ivpu_hw_40xx_profiling_freq_reg_set(struct ivpu_device *vdev) | |
| 814 | −{ | |
| 815 | − u32 val = REGB_RD32(VPU_40XX_BUTTRESS_VPU_STATUS); | |
| 816 | − | |
| 817 | − if (vdev->hw->pll.profiling_freq == PLL_PROFILING_FREQ_DEFAULT) | |
| 818 | − val = REG_CLR_FLD(VPU_40XX_BUTTRESS_VPU_STATUS, PERF_CLK, val); | |
| 819 | − else | |
| 820 | − val = REG_SET_FLD(VPU_40XX_BUTTRESS_VPU_STATUS, PERF_CLK, val); | |
| 821 | − | |
| 822 | − REGB_WR32(VPU_40XX_BUTTRESS_VPU_STATUS, val); | |
| 823 | −} | |
| 824 | − | |
| 825 | −static void ivpu_hw_40xx_ats_print(struct ivpu_device *vdev) | |
| 826 | −{ | |
| 827 | − ivpu_dbg(vdev, MISC, "Buttress ATS: %s\n", | |
| 828 | − REGB_RD32(VPU_40XX_BUTTRESS_HM_ATS) ? "Enable" : "Disable"); | |
| 829 | −} | |
| 830 | − | |
| 831 | −static void ivpu_hw_40xx_clock_relinquish_disable(struct ivpu_device *vdev) | |
| 832 | −{ | |
| 833 | − u32 val = REGB_RD32(VPU_40XX_BUTTRESS_VPU_STATUS); | |
| 834 | − | |
| 835 | − val = REG_SET_FLD(VPU_40XX_BUTTRESS_VPU_STATUS, DISABLE_CLK_RELINQUISH, val); | |
| 836 | − REGB_WR32(VPU_40XX_BUTTRESS_VPU_STATUS, val); | |
| 837 | −} | |
| 838 | − | |
| 839 | −static int ivpu_hw_40xx_power_up(struct ivpu_device *vdev) | |
| 840 | −{ | |
| 841 | − int ret; | |
| 842 | − | |
| 843 | − ret = ivpu_hw_40xx_d0i3_disable(vdev); | |
| 844 | − if (ret) | |
| 845 | − ivpu_warn(vdev, "Failed to disable D0I3: %d\n", ret); | |
| 846 | − | |
| 847 | − ret = ivpu_pll_enable(vdev); | |
| 848 | − if (ret) { | |
| 849 | − ivpu_err(vdev, "Failed to enable PLL: %d\n", ret); | |
| 850 | − return ret; | |
| 851 | − } | |
| 852 | − | |
| 853 | − if (IVPU_WA(disable_clock_relinquish)) | |
| 854 | − ivpu_hw_40xx_clock_relinquish_disable(vdev); | |
| 855 | − ivpu_hw_40xx_profiling_freq_reg_set(vdev); | |
| 856 | − ivpu_hw_40xx_ats_print(vdev); | |
| 857 | − | |
| 858 | − ret = ivpu_boot_host_ss_check(vdev); | |
| 859 | − if (ret) { | |
| 860 | − ivpu_err(vdev, "Failed to configure host SS: %d\n", ret); | |
| 861 | − return ret; | |
| 862 | − } | |
| 863 | − | |
| 864 | − ivpu_boot_idle_gen_drive(vdev, false); | |
| 865 | − | |
| 866 | − ret = ivpu_boot_pwr_domain_enable(vdev); | |
| 867 | − if (ret) { | |
| 868 | − ivpu_err(vdev, "Failed to enable power domain: %d\n", ret); | |
| 869 | − return ret; | |
| 870 | − } | |
| 871 | − | |
| 872 | − ret = ivpu_boot_host_ss_axi_enable(vdev); | |
| 873 | − if (ret) { | |
| 874 | − ivpu_err(vdev, "Failed to enable AXI: %d\n", ret); | |
| 875 | − return ret; | |
| 876 | − } | |
| 877 | − | |
| 878 | − ret = ivpu_boot_host_ss_top_noc_enable(vdev); | |
| 879 | − if (ret) | |
| 880 | − ivpu_err(vdev, "Failed to enable TOP NOC: %d\n", ret); | |
| 881 | − | |
| 882 | − return ret; | |
| 883 | −} | |
| 884 | − | |
| 885 | −static int ivpu_hw_40xx_boot_fw(struct ivpu_device *vdev) | |
| 886 | −{ | |
| 887 | − int ret; | |
| 888 | − | |
| 889 | − ivpu_boot_no_snoop_enable(vdev); | |
| 890 | − ivpu_boot_tbu_mmu_enable(vdev); | |
| 891 | − | |
| 892 | − ret = ivpu_boot_soc_cpu_boot(vdev); | |
| 893 | − if (ret) | |
| 894 | − ivpu_err(vdev, "Failed to boot SOC CPU: %d\n", ret); | |
| 895 | − | |
| 896 | − return ret; | |
| 897 | −} | |
| 898 | − | |
| 899 | −static bool ivpu_hw_40xx_is_idle(struct ivpu_device *vdev) | |
| 900 | −{ | |
| 901 | − u32 val; | |
| 902 | − | |
| 903 | − if (IVPU_WA(punit_disabled)) | |
| 904 | − return true; | |
| 905 | − | |
| 906 | − val = REGB_RD32(VPU_40XX_BUTTRESS_VPU_STATUS); | |
| 907 | − return REG_TEST_FLD(VPU_40XX_BUTTRESS_VPU_STATUS, READY, val) && | |
| 908 | − REG_TEST_FLD(VPU_40XX_BUTTRESS_VPU_STATUS, IDLE, val); | |
| 909 | −} | |
| 910 | − | |
| 911 | −static int ivpu_hw_40xx_wait_for_idle(struct ivpu_device *vdev) | |
| 912 | −{ | |
| 913 | − return REGB_POLL_FLD(VPU_40XX_BUTTRESS_VPU_STATUS, IDLE, 0x1, IDLE_TIMEOUT_US); | |
| 914 | −} | |
| 915 | − | |
| 916 | −static void ivpu_hw_40xx_save_d0i3_entry_timestamp(struct ivpu_device *vdev) | |
| 917 | −{ | |
| 918 | − vdev->hw->d0i3_entry_host_ts = ktime_get_boottime(); | |
| 919 | − vdev->hw->d0i3_entry_vpu_ts = REGV_RD64(VPU_40XX_CPU_SS_TIM_PERF_EXT_FREE_CNT); | |
| 920 | −} | |
| 921 | − | |
| 922 | −static int ivpu_hw_40xx_power_down(struct ivpu_device *vdev) | |
| 923 | −{ | |
| 924 | − int ret = 0; | |
| 925 | − | |
| 926 | − ivpu_hw_40xx_save_d0i3_entry_timestamp(vdev); | |
| 927 | − | |
| 928 | − if (!ivpu_hw_40xx_is_idle(vdev) && ivpu_hw_40xx_ip_reset(vdev)) | |
| 929 | − ivpu_warn(vdev, "Failed to reset the NPU\n"); | |
| 930 | − | |
| 931 | − if (ivpu_pll_disable(vdev)) { | |
| 932 | − ivpu_err(vdev, "Failed to disable PLL\n"); | |
| 933 | − ret = -EIO; | |
| 934 | − } | |
| 935 | − | |
| 936 | − if (ivpu_hw_40xx_d0i3_enable(vdev)) { | |
| 937 | − ivpu_err(vdev, "Failed to enter D0I3\n"); | |
| 938 | − ret = -EIO; | |
| 939 | − } | |
| 940 | − | |
| 941 | − return ret; | |
| 942 | −} | |
| 943 | − | |
| 944 | −static void ivpu_hw_40xx_wdt_disable(struct ivpu_device *vdev) | |
| 945 | −{ | |
| 946 | − u32 val; | |
| 947 | − | |
| 948 | − REGV_WR32(VPU_40XX_CPU_SS_TIM_SAFE, TIM_SAFE_ENABLE); | |
| 949 | − REGV_WR32(VPU_40XX_CPU_SS_TIM_WATCHDOG, TIM_WATCHDOG_RESET_VALUE); | |
| 950 | − | |
| 951 | − REGV_WR32(VPU_40XX_CPU_SS_TIM_SAFE, TIM_SAFE_ENABLE); | |
| 952 | − REGV_WR32(VPU_40XX_CPU_SS_TIM_WDOG_EN, 0); | |
| 953 | − | |
| 954 | − val = REGV_RD32(VPU_40XX_CPU_SS_TIM_GEN_CONFIG); | |
| 955 | − val = REG_CLR_FLD(VPU_40XX_CPU_SS_TIM_GEN_CONFIG, WDOG_TO_INT_CLR, val); | |
| 956 | − REGV_WR32(VPU_40XX_CPU_SS_TIM_GEN_CONFIG, val); | |
| 957 | −} | |
| 958 | − | |
| 959 | −static u32 ivpu_hw_40xx_profiling_freq_get(struct ivpu_device *vdev) | |
| 960 | −{ | |
| 961 | − return vdev->hw->pll.profiling_freq; | |
| 962 | −} | |
| 963 | − | |
| 964 | −static void ivpu_hw_40xx_profiling_freq_drive(struct ivpu_device *vdev, bool enable) | |
| 965 | −{ | |
| 966 | − if (enable) | |
| 967 | − vdev->hw->pll.profiling_freq = PLL_PROFILING_FREQ_HIGH; | |
| 968 | − else | |
| 969 | − vdev->hw->pll.profiling_freq = PLL_PROFILING_FREQ_DEFAULT; | |
| 970 | −} | |
| 971 | − | |
| 972 | −/* Register indirect accesses */ | |
| 973 | −static u32 ivpu_hw_40xx_reg_pll_freq_get(struct ivpu_device *vdev) | |
| 974 | −{ | |
| 975 | − u32 pll_curr_ratio; | |
| 976 | − | |
| 977 | − pll_curr_ratio = REGB_RD32(VPU_40XX_BUTTRESS_PLL_FREQ); | |
| 978 | − pll_curr_ratio &= VPU_40XX_BUTTRESS_PLL_FREQ_RATIO_MASK; | |
| 979 | − | |
| 980 | − return PLL_RATIO_TO_FREQ(pll_curr_ratio); | |
| 981 | −} | |
| 982 | − | |
| 983 | −static u32 ivpu_hw_40xx_ratio_to_freq(struct ivpu_device *vdev, u32 ratio) | |
| 984 | −{ | |
| 985 | − return PLL_RATIO_TO_FREQ(ratio); | |
| 986 | −} | |
| 987 | − | |
| 988 | −static u32 ivpu_hw_40xx_reg_telemetry_offset_get(struct ivpu_device *vdev) | |
| 989 | −{ | |
| 990 | − return REGB_RD32(VPU_40XX_BUTTRESS_VPU_TELEMETRY_OFFSET); | |
| 991 | −} | |
| 992 | − | |
| 993 | −static u32 ivpu_hw_40xx_reg_telemetry_size_get(struct ivpu_device *vdev) | |
| 994 | −{ | |
| 995 | − return REGB_RD32(VPU_40XX_BUTTRESS_VPU_TELEMETRY_SIZE); | |
| 996 | −} | |
| 997 | − | |
| 998 | −static u32 ivpu_hw_40xx_reg_telemetry_enable_get(struct ivpu_device *vdev) | |
| 999 | −{ | |
| 1000 | − return REGB_RD32(VPU_40XX_BUTTRESS_VPU_TELEMETRY_ENABLE); | |
| 1001 | −} | |
| 1002 | − | |
| 1003 | −static void ivpu_hw_40xx_reg_db_set(struct ivpu_device *vdev, u32 db_id) | |
| 1004 | −{ | |
| 1005 | − u32 reg_stride = VPU_40XX_CPU_SS_DOORBELL_1 - VPU_40XX_CPU_SS_DOORBELL_0; | |
| 1006 | − u32 val = REG_FLD(VPU_40XX_CPU_SS_DOORBELL_0, SET); | |
| 1007 | − | |
| 1008 | − REGV_WR32I(VPU_40XX_CPU_SS_DOORBELL_0, reg_stride, db_id, val); | |
| 1009 | −} | |
| 1010 | − | |
| 1011 | −static u32 ivpu_hw_40xx_reg_ipc_rx_addr_get(struct ivpu_device *vdev) | |
| 1012 | −{ | |
| 1013 | − return REGV_RD32(VPU_40XX_HOST_SS_TIM_IPC_FIFO_ATM); | |
| 1014 | −} | |
| 1015 | − | |
| 1016 | −static u32 ivpu_hw_40xx_reg_ipc_rx_count_get(struct ivpu_device *vdev) | |
| 1017 | −{ | |
| 1018 | − u32 count = REGV_RD32_SILENT(VPU_40XX_HOST_SS_TIM_IPC_FIFO_STAT); | |
| 1019 | − | |
| 1020 | − return REG_GET_FLD(VPU_40XX_HOST_SS_TIM_IPC_FIFO_STAT, FILL_LEVEL, count); | |
| 1021 | −} | |
| 1022 | − | |
| 1023 | −static void ivpu_hw_40xx_reg_ipc_tx_set(struct ivpu_device *vdev, u32 vpu_addr) | |
| 1024 | −{ | |
| 1025 | − REGV_WR32(VPU_40XX_CPU_SS_TIM_IPC_FIFO, vpu_addr); | |
| 1026 | −} | |
| 1027 | − | |
| 1028 | −static void ivpu_hw_40xx_irq_clear(struct ivpu_device *vdev) | |
| 1029 | −{ | |
| 1030 | − REGV_WR64(VPU_40XX_HOST_SS_ICB_CLEAR_0, ICB_0_1_IRQ_MASK); | |
| 1031 | −} | |
| 1032 | − | |
| 1033 | −static void ivpu_hw_40xx_irq_enable(struct ivpu_device *vdev) | |
| 1034 | −{ | |
| 1035 | − REGV_WR32(VPU_40XX_HOST_SS_FW_SOC_IRQ_EN, ITF_FIREWALL_VIOLATION_MASK); | |
| 1036 | − REGV_WR64(VPU_40XX_HOST_SS_ICB_ENABLE_0, ICB_0_1_IRQ_MASK); | |
| 1037 | − REGB_WR32(VPU_40XX_BUTTRESS_LOCAL_INT_MASK, BUTTRESS_IRQ_ENABLE_MASK); | |
| 1038 | − REGB_WR32(VPU_40XX_BUTTRESS_GLOBAL_INT_MASK, 0x0); | |
| 1039 | −} | |
| 1040 | − | |
| 1041 | −static void ivpu_hw_40xx_irq_disable(struct ivpu_device *vdev) | |
| 1042 | −{ | |
| 1043 | − REGB_WR32(VPU_40XX_BUTTRESS_GLOBAL_INT_MASK, 0x1); | |
| 1044 | − REGB_WR32(VPU_40XX_BUTTRESS_LOCAL_INT_MASK, BUTTRESS_IRQ_DISABLE_MASK); | |
| 1045 | − REGV_WR64(VPU_40XX_HOST_SS_ICB_ENABLE_0, 0x0ull); | |
| 1046 | − REGV_WR32(VPU_40XX_HOST_SS_FW_SOC_IRQ_EN, 0x0ul); | |
| 1047 | −} | |
| 1048 | − | |
| 1049 | −static void ivpu_hw_40xx_irq_wdt_nce_handler(struct ivpu_device *vdev) | |
| 1050 | −{ | |
| 1051 | − /* TODO: For LNN hang consider engine reset instead of full recovery */ | |
| 1052 | − ivpu_pm_trigger_recovery(vdev, "WDT NCE IRQ"); | |
| 1053 | −} | |
| 1054 | − | |
| 1055 | −static void ivpu_hw_40xx_irq_wdt_mss_handler(struct ivpu_device *vdev) | |
| 1056 | −{ | |
| 1057 | − ivpu_hw_wdt_disable(vdev); | |
| 1058 | − ivpu_pm_trigger_recovery(vdev, "WDT MSS IRQ"); | |
| 1059 | −} | |
| 1060 | − | |
| 1061 | −static void ivpu_hw_40xx_irq_noc_firewall_handler(struct ivpu_device *vdev) | |
| 1062 | −{ | |
| 1063 | − ivpu_pm_trigger_recovery(vdev, "NOC Firewall IRQ"); | |
| 1064 | −} | |
| 1065 | − | |
| 1066 | −/* Handler for IRQs from VPU core (irqV) */ | |
| 1067 | −static bool ivpu_hw_40xx_irqv_handler(struct ivpu_device *vdev, int irq, bool *wake_thread) | |
| 1068 | −{ | |
| 1069 | − u32 status = REGV_RD32(VPU_40XX_HOST_SS_ICB_STATUS_0) & ICB_0_IRQ_MASK; | |
| 1070 | − | |
| 1071 | − if (!status) | |
| 1072 | − return false; | |
| 1073 | − | |
| 1074 | − REGV_WR32(VPU_40XX_HOST_SS_ICB_CLEAR_0, status); | |
| 1075 | − | |
| 1076 | − if (REG_TEST_FLD(VPU_40XX_HOST_SS_ICB_STATUS_0, MMU_IRQ_0_INT, status)) | |
| 1077 | − ivpu_mmu_irq_evtq_handler(vdev); | |
| 1078 | − | |
| 1079 | − if (REG_TEST_FLD(VPU_40XX_HOST_SS_ICB_STATUS_0, HOST_IPC_FIFO_INT, status)) | |
| 1080 | − ivpu_ipc_irq_handler(vdev, wake_thread); | |
| 1081 | − | |
| 1082 | − if (REG_TEST_FLD(VPU_40XX_HOST_SS_ICB_STATUS_0, MMU_IRQ_1_INT, status)) | |
| 1083 | − ivpu_dbg(vdev, IRQ, "MMU sync complete\n"); | |
| 1084 | − | |
| 1085 | − if (REG_TEST_FLD(VPU_40XX_HOST_SS_ICB_STATUS_0, MMU_IRQ_2_INT, status)) | |
| 1086 | − ivpu_mmu_irq_gerr_handler(vdev); | |
| 1087 | − | |
| 1088 | − if (REG_TEST_FLD(VPU_40XX_HOST_SS_ICB_STATUS_0, CPU_INT_REDIRECT_0_INT, status)) | |
| 1089 | − ivpu_hw_40xx_irq_wdt_mss_handler(vdev); | |
| 1090 | − | |
| 1091 | − if (REG_TEST_FLD(VPU_40XX_HOST_SS_ICB_STATUS_0, CPU_INT_REDIRECT_1_INT, status)) | |
| 1092 | − ivpu_hw_40xx_irq_wdt_nce_handler(vdev); | |
| 1093 | − | |
| 1094 | − if (REG_TEST_FLD(VPU_40XX_HOST_SS_ICB_STATUS_0, NOC_FIREWALL_INT, status)) | |
| 1095 | − ivpu_hw_40xx_irq_noc_firewall_handler(vdev); | |
| 1096 | − | |
| 1097 | − return true; | |
| 1098 | −} | |
| 1099 | − | |
| 1100 | −/* Handler for IRQs from Buttress core (irqB) */ | |
| 1101 | −static bool ivpu_hw_40xx_irqb_handler(struct ivpu_device *vdev, int irq) | |
| 1102 | −{ | |
| 1103 | − bool schedule_recovery = false; | |
| 1104 | − u32 status = REGB_RD32(VPU_40XX_BUTTRESS_INTERRUPT_STAT) & BUTTRESS_IRQ_MASK; | |
| 1105 | − | |
| 1106 | − if (!status) | |
| 1107 | − return false; | |
| 1108 | − | |
| 1109 | − if (REG_TEST_FLD(VPU_40XX_BUTTRESS_INTERRUPT_STAT, FREQ_CHANGE, status)) | |
| 1110 | − ivpu_dbg(vdev, IRQ, "FREQ_CHANGE"); | |
| 1111 | − | |
| 1112 | − if (REG_TEST_FLD(VPU_40XX_BUTTRESS_INTERRUPT_STAT, ATS_ERR, status)) { | |
| 1113 | − ivpu_err(vdev, "ATS_ERR LOG1 0x%08x ATS_ERR_LOG2 0x%08x\n", | |
| 1114 | − REGB_RD32(VPU_40XX_BUTTRESS_ATS_ERR_LOG1), | |
| 1115 | − REGB_RD32(VPU_40XX_BUTTRESS_ATS_ERR_LOG2)); | |
| 1116 | − REGB_WR32(VPU_40XX_BUTTRESS_ATS_ERR_CLEAR, 0x1); | |
| 1117 | − schedule_recovery = true; | |
| 1118 | − } | |
| 1119 | − | |
| 1120 | − if (REG_TEST_FLD(VPU_40XX_BUTTRESS_INTERRUPT_STAT, CFI0_ERR, status)) { | |
| 1121 | − ivpu_err(vdev, "CFI0_ERR 0x%08x", REGB_RD32(VPU_40XX_BUTTRESS_CFI0_ERR_LOG)); | |
| 1122 | − REGB_WR32(VPU_40XX_BUTTRESS_CFI0_ERR_CLEAR, 0x1); | |
| 1123 | − schedule_recovery = true; | |
| 1124 | − } | |
| 1125 | − | |
| 1126 | − if (REG_TEST_FLD(VPU_40XX_BUTTRESS_INTERRUPT_STAT, CFI1_ERR, status)) { | |
| 1127 | − ivpu_err(vdev, "CFI1_ERR 0x%08x", REGB_RD32(VPU_40XX_BUTTRESS_CFI1_ERR_LOG)); | |
| 1128 | − REGB_WR32(VPU_40XX_BUTTRESS_CFI1_ERR_CLEAR, 0x1); | |
| 1129 | − schedule_recovery = true; | |
| 1130 | − } | |
| 1131 | − | |
| 1132 | − if (REG_TEST_FLD(VPU_40XX_BUTTRESS_INTERRUPT_STAT, IMR0_ERR, status)) { | |
| 1133 | − ivpu_err(vdev, "IMR_ERR_CFI0 LOW: 0x%08x HIGH: 0x%08x", | |
| 1134 | − REGB_RD32(VPU_40XX_BUTTRESS_IMR_ERR_CFI0_LOW), | |
| 1135 | − REGB_RD32(VPU_40XX_BUTTRESS_IMR_ERR_CFI0_HIGH)); | |
| 1136 | − REGB_WR32(VPU_40XX_BUTTRESS_IMR_ERR_CFI0_CLEAR, 0x1); | |
| 1137 | − schedule_recovery = true; | |
| 1138 | − } | |
| 1139 | − | |
| 1140 | − if (REG_TEST_FLD(VPU_40XX_BUTTRESS_INTERRUPT_STAT, IMR1_ERR, status)) { | |
| 1141 | − ivpu_err(vdev, "IMR_ERR_CFI1 LOW: 0x%08x HIGH: 0x%08x", | |
| 1142 | − REGB_RD32(VPU_40XX_BUTTRESS_IMR_ERR_CFI1_LOW), | |
| 1143 | − REGB_RD32(VPU_40XX_BUTTRESS_IMR_ERR_CFI1_HIGH)); | |
| 1144 | − REGB_WR32(VPU_40XX_BUTTRESS_IMR_ERR_CFI1_CLEAR, 0x1); | |
| 1145 | − schedule_recovery = true; | |
| 1146 | − } | |
| 1147 | − | |
| 1148 | − if (REG_TEST_FLD(VPU_40XX_BUTTRESS_INTERRUPT_STAT, SURV_ERR, status)) { | |
| 1149 | − ivpu_err(vdev, "Survivability error detected\n"); | |
| 1150 | − schedule_recovery = true; | |
| 1151 | − } | |
| 1152 | − | |
| 1153 | − /* This must be done after interrupts are cleared at the source. */ | |
| 1154 | − REGB_WR32(VPU_40XX_BUTTRESS_INTERRUPT_STAT, status); | |
| 1155 | − | |
| 1156 | − if (schedule_recovery) | |
| 1157 | − ivpu_pm_trigger_recovery(vdev, "Buttress IRQ"); | |
| 1158 | − | |
| 1159 | − return true; | |
| 1160 | −} | |
| 1161 | − | |
| 1162 | −static irqreturn_t ivpu_hw_40xx_irq_handler(int irq, void *ptr) | |
| 1163 | −{ | |
| 1164 | − bool irqv_handled, irqb_handled, wake_thread = false; | |
| 1165 | − struct ivpu_device *vdev = ptr; | |
| 1166 | − | |
| 1167 | − REGB_WR32(VPU_40XX_BUTTRESS_GLOBAL_INT_MASK, 0x1); | |
| 1168 | − | |
| 1169 | − irqv_handled = ivpu_hw_40xx_irqv_handler(vdev, irq, &wake_thread); | |
| 1170 | − irqb_handled = ivpu_hw_40xx_irqb_handler(vdev, irq); | |
| 1171 | − | |
| 1172 | − /* Re-enable global interrupts to re-trigger MSI for pending interrupts */ | |
| 1173 | − REGB_WR32(VPU_40XX_BUTTRESS_GLOBAL_INT_MASK, 0x0); | |
| 1174 | − | |
| 1175 | − if (wake_thread) | |
| 1176 | − return IRQ_WAKE_THREAD; | |
| 1177 | − if (irqv_handled || irqb_handled) | |
| 1178 | − return IRQ_HANDLED; | |
| 1179 | − return IRQ_NONE; | |
| 1180 | −} | |
| 1181 | − | |
| 1182 | −static void ivpu_hw_40xx_diagnose_failure(struct ivpu_device *vdev) | |
| 1183 | −{ | |
| 1184 | − u32 irqv = REGV_RD32(VPU_40XX_HOST_SS_ICB_STATUS_0) & ICB_0_IRQ_MASK; | |
| 1185 | − u32 irqb = REGB_RD32(VPU_40XX_BUTTRESS_INTERRUPT_STAT) & BUTTRESS_IRQ_MASK; | |
| 1186 | − | |
| 1187 | − if (ivpu_hw_40xx_reg_ipc_rx_count_get(vdev)) | |
| 1188 | − ivpu_err(vdev, "IPC FIFO queue not empty, missed IPC IRQ"); | |
| 1189 | − | |
| 1190 | − if (REG_TEST_FLD(VPU_40XX_HOST_SS_ICB_STATUS_0, CPU_INT_REDIRECT_0_INT, irqv)) | |
| 1191 | − ivpu_err(vdev, "WDT MSS timeout detected\n"); | |
| 1192 | − | |
| 1193 | − if (REG_TEST_FLD(VPU_40XX_HOST_SS_ICB_STATUS_0, CPU_INT_REDIRECT_1_INT, irqv)) | |
| 1194 | − ivpu_err(vdev, "WDT NCE timeout detected\n"); | |
| 1195 | − | |
| 1196 | − if (REG_TEST_FLD(VPU_40XX_HOST_SS_ICB_STATUS_0, NOC_FIREWALL_INT, irqv)) | |
| 1197 | − ivpu_err(vdev, "NOC Firewall irq detected\n"); | |
| 1198 | − | |
| 1199 | − if (REG_TEST_FLD(VPU_40XX_BUTTRESS_INTERRUPT_STAT, ATS_ERR, irqb)) { | |
| 1200 | − ivpu_err(vdev, "ATS_ERR_LOG1 0x%08x ATS_ERR_LOG2 0x%08x\n", | |
| 1201 | − REGB_RD32(VPU_40XX_BUTTRESS_ATS_ERR_LOG1), | |
| 1202 | − REGB_RD32(VPU_40XX_BUTTRESS_ATS_ERR_LOG2)); | |
| 1203 | − } | |
| 1204 | − | |
| 1205 | − if (REG_TEST_FLD(VPU_40XX_BUTTRESS_INTERRUPT_STAT, CFI0_ERR, irqb)) | |
| 1206 | − ivpu_err(vdev, "CFI0_ERR_LOG 0x%08x\n", REGB_RD32(VPU_40XX_BUTTRESS_CFI0_ERR_LOG)); | |
| 1207 | − | |
| 1208 | − if (REG_TEST_FLD(VPU_40XX_BUTTRESS_INTERRUPT_STAT, CFI1_ERR, irqb)) | |
| 1209 | − ivpu_err(vdev, "CFI1_ERR_LOG 0x%08x\n", REGB_RD32(VPU_40XX_BUTTRESS_CFI1_ERR_LOG)); | |
| 1210 | − | |
| 1211 | − if (REG_TEST_FLD(VPU_40XX_BUTTRESS_INTERRUPT_STAT, IMR0_ERR, irqb)) | |
| 1212 | − ivpu_err(vdev, "IMR_ERR_CFI0 LOW: 0x%08x HIGH: 0x%08x\n", | |
| 1213 | − REGB_RD32(VPU_40XX_BUTTRESS_IMR_ERR_CFI0_LOW), | |
| 1214 | − REGB_RD32(VPU_40XX_BUTTRESS_IMR_ERR_CFI0_HIGH)); | |
| 1215 | − | |
| 1216 | − if (REG_TEST_FLD(VPU_40XX_BUTTRESS_INTERRUPT_STAT, IMR1_ERR, irqb)) | |
| 1217 | − ivpu_err(vdev, "IMR_ERR_CFI1 LOW: 0x%08x HIGH: 0x%08x\n", | |
| 1218 | − REGB_RD32(VPU_40XX_BUTTRESS_IMR_ERR_CFI1_LOW), | |
| 1219 | − REGB_RD32(VPU_40XX_BUTTRESS_IMR_ERR_CFI1_HIGH)); | |
| 1220 | − | |
| 1221 | − if (REG_TEST_FLD(VPU_40XX_BUTTRESS_INTERRUPT_STAT, SURV_ERR, irqb)) | |
| 1222 | − ivpu_err(vdev, "Survivability error detected\n"); | |
| 1223 | −} | |
| 1224 | − | |
| 1225 | −const struct ivpu_hw_ops ivpu_hw_40xx_ops = { | |
| 1226 | − .info_init = ivpu_hw_40xx_info_init, | |
| 1227 | − .power_up = ivpu_hw_40xx_power_up, | |
| 1228 | − .is_idle = ivpu_hw_40xx_is_idle, | |
| 1229 | − .wait_for_idle = ivpu_hw_40xx_wait_for_idle, | |
| 1230 | − .power_down = ivpu_hw_40xx_power_down, | |
| 1231 | − .reset = ivpu_hw_40xx_reset, | |
| 1232 | − .boot_fw = ivpu_hw_40xx_boot_fw, | |
| 1233 | − .wdt_disable = ivpu_hw_40xx_wdt_disable, | |
| 1234 | − .diagnose_failure = ivpu_hw_40xx_diagnose_failure, | |
| 1235 | − .profiling_freq_get = ivpu_hw_40xx_profiling_freq_get, | |
| 1236 | − .profiling_freq_drive = ivpu_hw_40xx_profiling_freq_drive, | |
| 1237 | − .reg_pll_freq_get = ivpu_hw_40xx_reg_pll_freq_get, | |
| 1238 | − .ratio_to_freq = ivpu_hw_40xx_ratio_to_freq, | |
| 1239 | − .reg_telemetry_offset_get = ivpu_hw_40xx_reg_telemetry_offset_get, | |
| 1240 | − .reg_telemetry_size_get = ivpu_hw_40xx_reg_telemetry_size_get, | |
| 1241 | − .reg_telemetry_enable_get = ivpu_hw_40xx_reg_telemetry_enable_get, | |
| 1242 | − .reg_db_set = ivpu_hw_40xx_reg_db_set, | |
| 1243 | − .reg_ipc_rx_addr_get = ivpu_hw_40xx_reg_ipc_rx_addr_get, | |
| 1244 | − .reg_ipc_rx_count_get = ivpu_hw_40xx_reg_ipc_rx_count_get, | |
| 1245 | − .reg_ipc_tx_set = ivpu_hw_40xx_reg_ipc_tx_set, | |
| 1246 | − .irq_clear = ivpu_hw_40xx_irq_clear, | |
| 1247 | − .irq_enable = ivpu_hw_40xx_irq_enable, | |
| 1248 | − .irq_disable = ivpu_hw_40xx_irq_disable, | |
| 1249 | − .irq_handler = ivpu_hw_40xx_irq_handler, | |
| 1250 | −}; | |
| @@ -8,91 +8,6 @@ · 7 unmodified lines | ||
| 8 | 8 | |
| 9 | 9 | #include <linux/bits.h> |
| 10 | 10 | |
| 11 | −#define VPU_40XX_BUTTRESS_INTERRUPT_STAT 0x00000000u | |
| 12 | −#define VPU_40XX_BUTTRESS_INTERRUPT_STAT_FREQ_CHANGE_MASK BIT_MASK(0) | |
| 13 | −#define VPU_40XX_BUTTRESS_INTERRUPT_STAT_ATS_ERR_MASK BIT_MASK(1) | |
| 14 | −#define VPU_40XX_BUTTRESS_INTERRUPT_STAT_CFI0_ERR_MASK BIT_MASK(2) | |
| 15 | −#define VPU_40XX_BUTTRESS_INTERRUPT_STAT_CFI1_ERR_MASK BIT_MASK(3) | |
| 16 | −#define VPU_40XX_BUTTRESS_INTERRUPT_STAT_IMR0_ERR_MASK BIT_MASK(4) | |
| 17 | −#define VPU_40XX_BUTTRESS_INTERRUPT_STAT_IMR1_ERR_MASK BIT_MASK(5) | |
| 18 | −#define VPU_40XX_BUTTRESS_INTERRUPT_STAT_SURV_ERR_MASK BIT_MASK(6) | |
| 19 | − | |
| 20 | −#define VPU_40XX_BUTTRESS_LOCAL_INT_MASK 0x00000004u | |
| 21 | −#define VPU_40XX_BUTTRESS_GLOBAL_INT_MASK 0x00000008u | |
| 22 | − | |
| 23 | −#define VPU_40XX_BUTTRESS_HM_ATS 0x0000000cu | |
| 24 | − | |
| 25 | −#define VPU_40XX_BUTTRESS_ATS_ERR_LOG1 0x00000010u | |
| 26 | −#define VPU_40XX_BUTTRESS_ATS_ERR_LOG2 0x00000014u | |
| 27 | −#define VPU_40XX_BUTTRESS_ATS_ERR_CLEAR 0x00000018u | |
| 28 | − | |
| 29 | −#define VPU_40XX_BUTTRESS_CFI0_ERR_LOG 0x0000001cu | |
| 30 | −#define VPU_40XX_BUTTRESS_CFI0_ERR_CLEAR 0x00000020u | |
| 31 | − | |
| 32 | −#define VPU_40XX_BUTTRESS_PORT_ARBITRATION_WEIGHTS_ATS 0x00000024u | |
| 33 | − | |
| 34 | −#define VPU_40XX_BUTTRESS_CFI1_ERR_LOG 0x00000040u | |
| 35 | −#define VPU_40XX_BUTTRESS_CFI1_ERR_CLEAR 0x00000044u | |
| 36 | − | |
| 37 | −#define VPU_40XX_BUTTRESS_IMR_ERR_CFI0_LOW 0x00000048u | |
| 38 | −#define VPU_40XX_BUTTRESS_IMR_ERR_CFI0_HIGH 0x0000004cu | |
| 39 | −#define VPU_40XX_BUTTRESS_IMR_ERR_CFI0_CLEAR 0x00000050u | |
| 40 | − | |
| 41 | −#define VPU_40XX_BUTTRESS_PORT_ARBITRATION_WEIGHTS 0x00000054u | |
| 42 | − | |
| 43 | −#define VPU_40XX_BUTTRESS_IMR_ERR_CFI1_LOW 0x00000058u | |
| 44 | −#define VPU_40XX_BUTTRESS_IMR_ERR_CFI1_HIGH 0x0000005cu | |
| 45 | −#define VPU_40XX_BUTTRESS_IMR_ERR_CFI1_CLEAR 0x00000060u | |
| 46 | − | |
| 47 | −#define VPU_40XX_BUTTRESS_WP_REQ_PAYLOAD0 0x00000130u | |
| 48 | −#define VPU_40XX_BUTTRESS_WP_REQ_PAYLOAD0_MIN_RATIO_MASK GENMASK(15, 0) | |
| 49 | −#define VPU_40XX_BUTTRESS_WP_REQ_PAYLOAD0_MAX_RATIO_MASK GENMASK(31, 16) | |
| 50 | − | |
| 51 | −#define VPU_40XX_BUTTRESS_WP_REQ_PAYLOAD1 0x00000134u | |
| 52 | −#define VPU_40XX_BUTTRESS_WP_REQ_PAYLOAD1_TARGET_RATIO_MASK GENMASK(15, 0) | |
| 53 | −#define VPU_40XX_BUTTRESS_WP_REQ_PAYLOAD1_EPP_MASK GENMASK(31, 16) | |
| 54 | − | |
| 55 | −#define VPU_40XX_BUTTRESS_WP_REQ_PAYLOAD2 0x00000138u | |
| 56 | −#define VPU_40XX_BUTTRESS_WP_REQ_PAYLOAD2_CONFIG_MASK GENMASK(15, 0) | |
| 57 | −#define VPU_40XX_BUTTRESS_WP_REQ_PAYLOAD2_CDYN_MASK GENMASK(31, 16) | |
| 58 | − | |
| 59 | −#define VPU_40XX_BUTTRESS_WP_REQ_CMD 0x0000013cu | |
| 60 | −#define VPU_40XX_BUTTRESS_WP_REQ_CMD_SEND_MASK BIT_MASK(0) | |
| 61 | − | |
| 62 | −#define VPU_40XX_BUTTRESS_PLL_FREQ 0x00000148u | |
| 63 | −#define VPU_40XX_BUTTRESS_PLL_FREQ_RATIO_MASK GENMASK(15, 0) | |
| 64 | − | |
| 65 | −#define VPU_40XX_BUTTRESS_TILE_FUSE 0x00000150u | |
| 66 | −#define VPU_40XX_BUTTRESS_TILE_FUSE_VALID_MASK BIT_MASK(0) | |
| 67 | −#define VPU_40XX_BUTTRESS_TILE_FUSE_CONFIG_MASK GENMASK(6, 1) | |
| 68 | − | |
| 69 | −#define VPU_40XX_BUTTRESS_VPU_STATUS 0x00000154u | |
| 70 | −#define VPU_40XX_BUTTRESS_VPU_STATUS_READY_MASK BIT_MASK(0) | |
| 71 | −#define VPU_40XX_BUTTRESS_VPU_STATUS_IDLE_MASK BIT_MASK(1) | |
| 72 | −#define VPU_40XX_BUTTRESS_VPU_STATUS_DUP_IDLE_MASK BIT_MASK(2) | |
| 73 | −#define VPU_40XX_BUTTRESS_VPU_STATUS_CLOCK_RESOURCE_OWN_ACK_MASK BIT_MASK(6) | |
| 74 | −#define VPU_40XX_BUTTRESS_VPU_STATUS_POWER_RESOURCE_OWN_ACK_MASK BIT_MASK(7) | |
| 75 | −#define VPU_40XX_BUTTRESS_VPU_STATUS_PERF_CLK_MASK BIT_MASK(11) | |
| 76 | −#define VPU_40XX_BUTTRESS_VPU_STATUS_DISABLE_CLK_RELINQUISH_MASK BIT_MASK(12) | |
| 77 | − | |
| 78 | −#define VPU_40XX_BUTTRESS_IP_RESET 0x00000160u | |
| 79 | −#define VPU_40XX_BUTTRESS_IP_RESET_TRIGGER_MASK BIT_MASK(0) | |
| 80 | − | |
| 81 | −#define VPU_40XX_BUTTRESS_D0I3_CONTROL 0x00000164u | |
| 82 | −#define VPU_40XX_BUTTRESS_D0I3_CONTROL_INPROGRESS_MASK BIT_MASK(0) | |
| 83 | −#define VPU_40XX_BUTTRESS_D0I3_CONTROL_I3_MASK BIT_MASK(2) | |
| 84 | − | |
| 85 | −#define VPU_40XX_BUTTRESS_VPU_TELEMETRY_OFFSET 0x00000168u | |
| 86 | −#define VPU_40XX_BUTTRESS_VPU_TELEMETRY_SIZE 0x0000016cu | |
| 87 | −#define VPU_40XX_BUTTRESS_VPU_TELEMETRY_ENABLE 0x00000170u | |
| 88 | − | |
| 89 | −#define VPU_40XX_BUTTRESS_FMIN_FUSE 0x00000174u | |
| 90 | −#define VPU_40XX_BUTTRESS_FMIN_FUSE_MIN_RATIO_MASK GENMASK(7, 0) | |
| 91 | −#define VPU_40XX_BUTTRESS_FMIN_FUSE_PN_RATIO_MASK GENMASK(15, 8) | |
| 92 | − | |
| 93 | −#define VPU_40XX_BUTTRESS_FMAX_FUSE 0x00000178u | |
| 94 | −#define VPU_40XX_BUTTRESS_FMAX_FUSE_MAX_RATIO_MASK GENMASK(7, 0) | |
| 95 | − | |
| 96 | 11 | #define VPU_40XX_HOST_SS_CPR_CLK_EN 0x00000080u |
| 97 | 12 | #define VPU_40XX_HOST_SS_CPR_CLK_EN_TOP_NOC_MASK BIT_MASK(1) |
| 98 | 13 | #define VPU_40XX_HOST_SS_CPR_CLK_EN_DSS_MAS_MASK BIT_MASK(10) |
| @@ -198,6 +113,12 @@ · 99 unmodified lines | ||
| 198 | 113 | #define VPU_40XX_HOST_SS_AON_PWR_ISLAND_STATUS0 0x0003002cu |
| 199 | 114 | #define VPU_40XX_HOST_SS_AON_PWR_ISLAND_STATUS0_CSS_CPU_MASK BIT_MASK(3) |
| 200 | 115 | |
| 116 | +#define VPU_50XX_HOST_SS_AON_PWR_ISLAND_EN_POST_DLY 0x00030068u | |
| 117 | +#define VPU_50XX_HOST_SS_AON_PWR_ISLAND_EN_POST_DLY_POST_DLY_MASK GENMASK(7, 0) | |
| 118 | + | |
| 119 | +#define VPU_50XX_HOST_SS_AON_PWR_ISLAND_STATUS_DLY 0x0003006cu | |
| 120 | +#define VPU_50XX_HOST_SS_AON_PWR_ISLAND_STATUS_DLY_STATUS_DLY_MASK GENMASK(7, 0) | |
| 121 | + | |
| 201 | 122 | #define VPU_40XX_HOST_SS_AON_IDLE_GEN 0x00030200u |
| 202 | 123 | #define VPU_40XX_HOST_SS_AON_IDLE_GEN_EN_MASK BIT_MASK(0) |
| 203 | 124 | #define VPU_40XX_HOST_SS_AON_IDLE_GEN_HW_PG_EN_MASK BIT_MASK(1) |
| @@ -205,6 +126,9 @@ · 1 unmodified line | ||
| 205 | 126 | #define VPU_40XX_HOST_SS_AON_DPU_ACTIVE 0x00030204u |
| 206 | 127 | #define VPU_40XX_HOST_SS_AON_DPU_ACTIVE_DPU_ACTIVE_MASK BIT_MASK(0) |
| 207 | 128 | |
| 129 | +#define VPU_50XX_HOST_SS_AON_FABRIC_REQ_OVERRIDE 0x00030210u | |
| 130 | +#define VPU_50XX_HOST_SS_AON_FABRIC_REQ_OVERRIDE_REQ_OVERRIDE_MASK BIT_MASK(0) | |
| 131 | + | |
| 208 | 132 | #define VPU_40XX_HOST_SS_VERIFICATION_ADDRESS_LO 0x00040040u |
| 209 | 133 | #define VPU_40XX_HOST_SS_VERIFICATION_ADDRESS_LO_DONE_MASK BIT_MASK(0) |
| 210 | 134 | #define VPU_40XX_HOST_SS_VERIFICATION_ADDRESS_LO_IOSF_RS_ID_MASK GENMASK(2, 1) |
| @@ -0,0 +1,905 @@ | ||
| 1 | +// SPDX-License-Identifier: GPL-2.0-only | |
| 2 | +/* | |
| 3 | + * Copyright (C) 2020-2024 Intel Corporation | |
| 4 | + */ | |
| 5 | + | |
| 6 | +#include "ivpu_drv.h" | |
| 7 | +#include "ivpu_hw.h" | |
| 8 | +#include "ivpu_hw_btrs.h" | |
| 9 | +#include "ivpu_hw_btrs_lnl_reg.h" | |
| 10 | +#include "ivpu_hw_btrs_mtl_reg.h" | |
| 11 | +#include "ivpu_hw_reg_io.h" | |
| 12 | +#include "ivpu_pm.h" | |
| 13 | + | |
| 14 | +#define BTRS_MTL_IRQ_MASK ((REG_FLD(VPU_HW_BTRS_MTL_INTERRUPT_STAT, ATS_ERR)) | \ | |
| 15 | + (REG_FLD(VPU_HW_BTRS_MTL_INTERRUPT_STAT, UFI_ERR))) | |
| 16 | + | |
| 17 | +#define BTRS_LNL_IRQ_MASK ((REG_FLD(VPU_HW_BTRS_LNL_INTERRUPT_STAT, ATS_ERR)) | \ | |
| 18 | + (REG_FLD(VPU_HW_BTRS_LNL_INTERRUPT_STAT, CFI0_ERR)) | \ | |
| 19 | + (REG_FLD(VPU_HW_BTRS_LNL_INTERRUPT_STAT, CFI1_ERR)) | \ | |
| 20 | + (REG_FLD(VPU_HW_BTRS_LNL_INTERRUPT_STAT, IMR0_ERR)) | \ | |
| 21 | + (REG_FLD(VPU_HW_BTRS_LNL_INTERRUPT_STAT, IMR1_ERR)) | \ | |
| 22 | + (REG_FLD(VPU_HW_BTRS_LNL_INTERRUPT_STAT, SURV_ERR))) | |
| 23 | + | |
| 24 | +#define BTRS_MTL_ALL_IRQ_MASK (BTRS_MTL_IRQ_MASK | (REG_FLD(VPU_HW_BTRS_MTL_INTERRUPT_STAT, \ | |
| 25 | + FREQ_CHANGE))) | |
| 26 | + | |
| 27 | +#define BTRS_IRQ_DISABLE_MASK ((u32)-1) | |
| 28 | + | |
| 29 | +#define BTRS_LNL_ALL_IRQ_MASK ((u32)-1) | |
| 30 | + | |
| 31 | +#define BTRS_MTL_WP_CONFIG_1_TILE_5_3_RATIO WP_CONFIG(MTL_CONFIG_1_TILE, MTL_PLL_RATIO_5_3) | |
| 32 | +#define BTRS_MTL_WP_CONFIG_1_TILE_4_3_RATIO WP_CONFIG(MTL_CONFIG_1_TILE, MTL_PLL_RATIO_4_3) | |
| 33 | +#define BTRS_MTL_WP_CONFIG_2_TILE_5_3_RATIO WP_CONFIG(MTL_CONFIG_2_TILE, MTL_PLL_RATIO_5_3) | |
| 34 | +#define BTRS_MTL_WP_CONFIG_2_TILE_4_3_RATIO WP_CONFIG(MTL_CONFIG_2_TILE, MTL_PLL_RATIO_4_3) | |
| 35 | +#define BTRS_MTL_WP_CONFIG_0_TILE_PLL_OFF WP_CONFIG(0, 0) | |
| 36 | + | |
| 37 | +#define PLL_CDYN_DEFAULT 0x80 | |
| 38 | +#define PLL_EPP_DEFAULT 0x80 | |
| 39 | +#define PLL_CONFIG_DEFAULT 0x0 | |
| 40 | +#define PLL_SIMULATION_FREQ 10000000 | |
| 41 | +#define PLL_REF_CLK_FREQ 50000000 | |
| 42 | +#define PLL_TIMEOUT_US (1500 * USEC_PER_MSEC) | |
| 43 | +#define IDLE_TIMEOUT_US (5 * USEC_PER_MSEC) | |
| 44 | +#define TIMEOUT_US (150 * USEC_PER_MSEC) | |
| 45 | + | |
| 46 | +/* Work point configuration values */ | |
| 47 | +#define WP_CONFIG(tile, ratio) (((tile) << 8) | (ratio)) | |
| 48 | +#define MTL_CONFIG_1_TILE 0x01 | |
| 49 | +#define MTL_CONFIG_2_TILE 0x02 | |
| 50 | +#define MTL_PLL_RATIO_5_3 0x01 | |
| 51 | +#define MTL_PLL_RATIO_4_3 0x02 | |
| 52 | +#define BTRS_MTL_TILE_FUSE_ENABLE_BOTH 0x0 | |
| 53 | +#define BTRS_MTL_TILE_SKU_BOTH 0x3630 | |
| 54 | + | |
| 55 | +#define BTRS_LNL_TILE_MAX_NUM 6 | |
| 56 | +#define BTRS_LNL_TILE_MAX_MASK 0x3f | |
| 57 | + | |
| 58 | +#define WEIGHTS_DEFAULT 0xf711f711u | |
| 59 | +#define WEIGHTS_ATS_DEFAULT 0x0000f711u | |
| 60 | + | |
| 61 | +#define DCT_REQ 0x2 | |
| 62 | +#define DCT_ENABLE 0x1 | |
| 63 | +#define DCT_DISABLE 0x0 | |
| 64 | + | |
| 65 | +int ivpu_hw_btrs_irqs_clear_with_0_mtl(struct ivpu_device *vdev) | |
| 66 | +{ | |
| 67 | + REGB_WR32(VPU_HW_BTRS_MTL_INTERRUPT_STAT, BTRS_MTL_ALL_IRQ_MASK); | |
| 68 | + if (REGB_RD32(VPU_HW_BTRS_MTL_INTERRUPT_STAT) == BTRS_MTL_ALL_IRQ_MASK) { | |
| 69 | + /* Writing 1s does not clear the interrupt status register */ | |
| 70 | + REGB_WR32(VPU_HW_BTRS_MTL_INTERRUPT_STAT, 0x0); | |
| 71 | + return true; | |
| 72 | + } | |
| 73 | + | |
| 74 | + return false; | |
| 75 | +} | |
| 76 | + | |
| 77 | +static void freq_ratios_init_mtl(struct ivpu_device *vdev) | |
| 78 | +{ | |
| 79 | + struct ivpu_hw_info *hw = vdev->hw; | |
| 80 | + u32 fmin_fuse, fmax_fuse; | |
| 81 | + | |
| 82 | + fmin_fuse = REGB_RD32(VPU_HW_BTRS_MTL_FMIN_FUSE); | |
| 83 | + hw->pll.min_ratio = REG_GET_FLD(VPU_HW_BTRS_MTL_FMIN_FUSE, MIN_RATIO, fmin_fuse); | |
| 84 | + hw->pll.pn_ratio = REG_GET_FLD(VPU_HW_BTRS_MTL_FMIN_FUSE, PN_RATIO, fmin_fuse); | |
| 85 | + | |
| 86 | + fmax_fuse = REGB_RD32(VPU_HW_BTRS_MTL_FMAX_FUSE); | |
| 87 | + hw->pll.max_ratio = REG_GET_FLD(VPU_HW_BTRS_MTL_FMAX_FUSE, MAX_RATIO, fmax_fuse); | |
| 88 | +} | |
| 89 | + | |
| 90 | +static void freq_ratios_init_lnl(struct ivpu_device *vdev) | |
| 91 | +{ | |
| 92 | + struct ivpu_hw_info *hw = vdev->hw; | |
| 93 | + u32 fmin_fuse, fmax_fuse; | |
| 94 | + | |
| 95 | + fmin_fuse = REGB_RD32(VPU_HW_BTRS_LNL_FMIN_FUSE); | |
| 96 | + hw->pll.min_ratio = REG_GET_FLD(VPU_HW_BTRS_LNL_FMIN_FUSE, MIN_RATIO, fmin_fuse); | |
| 97 | + hw->pll.pn_ratio = REG_GET_FLD(VPU_HW_BTRS_LNL_FMIN_FUSE, PN_RATIO, fmin_fuse); | |
| 98 | + | |
| 99 | + fmax_fuse = REGB_RD32(VPU_HW_BTRS_LNL_FMAX_FUSE); | |
| 100 | + hw->pll.max_ratio = REG_GET_FLD(VPU_HW_BTRS_LNL_FMAX_FUSE, MAX_RATIO, fmax_fuse); | |
| 101 | +} | |
| 102 | + | |
| 103 | +void ivpu_hw_btrs_freq_ratios_init(struct ivpu_device *vdev) | |
| 104 | +{ | |
| 105 | + struct ivpu_hw_info *hw = vdev->hw; | |
| 106 | + | |
| 107 | + if (ivpu_hw_btrs_gen(vdev) == IVPU_HW_BTRS_MTL) | |
| 108 | + freq_ratios_init_mtl(vdev); | |
| 109 | + else | |
| 110 | + freq_ratios_init_lnl(vdev); | |
| 111 | + | |
| 112 | + hw->pll.min_ratio = clamp_t(u8, ivpu_pll_min_ratio, hw->pll.min_ratio, hw->pll.max_ratio); | |
| 113 | + hw->pll.max_ratio = clamp_t(u8, ivpu_pll_max_ratio, hw->pll.min_ratio, hw->pll.max_ratio); | |
| 114 | + hw->pll.pn_ratio = clamp_t(u8, hw->pll.pn_ratio, hw->pll.min_ratio, hw->pll.max_ratio); | |
| 115 | +} | |
| 116 | + | |
| 117 | +static bool tile_disable_check(u32 config) | |
| 118 | +{ | |
| 119 | + /* Allowed values: 0 or one bit from range 0-5 (6 tiles) */ | |
| 120 | + if (config == 0) | |
| 121 | + return true; | |
| 122 | + | |
| 123 | + if (config > BIT(BTRS_LNL_TILE_MAX_NUM - 1)) | |
| 124 | + return false; | |
| 125 | + | |
| 126 | + if ((config & (config - 1)) == 0) | |
| 127 | + return true; | |
| 128 | + | |
| 129 | + return false; | |
| 130 | +} | |
| 131 | + | |
| 132 | +static int read_tile_config_fuse(struct ivpu_device *vdev, u32 *tile_fuse_config) | |
| 133 | +{ | |
| 134 | + u32 fuse; | |
| 135 | + u32 config; | |
| 136 | + | |
| 137 | + fuse = REGB_RD32(VPU_HW_BTRS_LNL_TILE_FUSE); | |
| 138 | + if (!REG_TEST_FLD(VPU_HW_BTRS_LNL_TILE_FUSE, VALID, fuse)) { | |
| 139 | + ivpu_err(vdev, "Fuse: invalid (0x%x)\n", fuse); | |
| 140 | + return -EIO; | |
| 141 | + } | |
| 142 | + | |
| 143 | + config = REG_GET_FLD(VPU_HW_BTRS_LNL_TILE_FUSE, CONFIG, fuse); | |
| 144 | + if (!tile_disable_check(config)) { | |
| 145 | + ivpu_err(vdev, "Fuse: Invalid tile disable config (0x%x)\n", config); | |
| 146 | + return -EIO; | |
| 147 | + } | |
| 148 | + | |
| 149 | + if (config) | |
| 150 | + ivpu_dbg(vdev, MISC, "Fuse: %d tiles enabled. Tile number %d disabled\n", | |
| 151 | + BTRS_LNL_TILE_MAX_NUM - 1, ffs(config) - 1); | |
| 152 | + else | |
| 153 | + ivpu_dbg(vdev, MISC, "Fuse: All %d tiles enabled\n", BTRS_LNL_TILE_MAX_NUM); | |
| 154 | + | |
| 155 | + *tile_fuse_config = config; | |
| 156 | + return 0; | |
| 157 | +} | |
| 158 | + | |
| 159 | +static int info_init_mtl(struct ivpu_device *vdev) | |
| 160 | +{ | |
| 161 | + struct ivpu_hw_info *hw = vdev->hw; | |
| 162 | + | |
| 163 | + hw->tile_fuse = BTRS_MTL_TILE_FUSE_ENABLE_BOTH; | |
| 164 | + hw->sku = BTRS_MTL_TILE_SKU_BOTH; | |
| 165 | + hw->config = BTRS_MTL_WP_CONFIG_2_TILE_4_3_RATIO; | |
| 166 | + hw->sched_mode = ivpu_sched_mode; | |
| 167 | + | |
| 168 | + return 0; | |
| 169 | +} | |
| 170 | + | |
| 171 | +static int info_init_lnl(struct ivpu_device *vdev) | |
| 172 | +{ | |
| 173 | + struct ivpu_hw_info *hw = vdev->hw; | |
| 174 | + u32 tile_fuse_config; | |
| 175 | + int ret; | |
| 176 | + | |
| 177 | + ret = read_tile_config_fuse(vdev, &tile_fuse_config); | |
| 178 | + if (ret) | |
| 179 | + return ret; | |
| 180 | + | |
| 181 | + hw->sched_mode = ivpu_sched_mode; | |
| 182 | + hw->tile_fuse = tile_fuse_config; | |
| 183 | + hw->pll.profiling_freq = PLL_PROFILING_FREQ_DEFAULT; | |
| 184 | + | |
| 185 | + return 0; | |
| 186 | +} | |
| 187 | + | |
| 188 | +int ivpu_hw_btrs_info_init(struct ivpu_device *vdev) | |
| 189 | +{ | |
| 190 | + if (ivpu_hw_btrs_gen(vdev) == IVPU_HW_BTRS_MTL) | |
| 191 | + return info_init_mtl(vdev); | |
| 192 | + else | |
| 193 | + return info_init_lnl(vdev); | |
| 194 | +} | |
| 195 | + | |
| 196 | +static int wp_request_sync(struct ivpu_device *vdev) | |
| 197 | +{ | |
| 198 | + if (ivpu_hw_btrs_gen(vdev) == IVPU_HW_BTRS_MTL) | |
| 199 | + return REGB_POLL_FLD(VPU_HW_BTRS_MTL_WP_REQ_CMD, SEND, 0, PLL_TIMEOUT_US); | |
| 200 | + else | |
| 201 | + return REGB_POLL_FLD(VPU_HW_BTRS_LNL_WP_REQ_CMD, SEND, 0, PLL_TIMEOUT_US); | |
| 202 | +} | |
| 203 | + | |
| 204 | +static int wait_for_status_ready(struct ivpu_device *vdev, bool enable) | |
| 205 | +{ | |
| 206 | + u32 exp_val = enable ? 0x1 : 0x0; | |
| 207 | + | |
| 208 | + if (IVPU_WA(punit_disabled)) | |
| 209 | + return 0; | |
| 210 | + | |
| 211 | + if (ivpu_hw_btrs_gen(vdev) == IVPU_HW_BTRS_MTL) | |
| 212 | + return REGB_POLL_FLD(VPU_HW_BTRS_MTL_VPU_STATUS, READY, exp_val, PLL_TIMEOUT_US); | |
| 213 | + else | |
| 214 | + return REGB_POLL_FLD(VPU_HW_BTRS_LNL_VPU_STATUS, READY, exp_val, PLL_TIMEOUT_US); | |
| 215 | +} | |
| 216 | + | |
| 217 | +struct wp_request { | |
| 218 | + u16 min; | |
| 219 | + u16 max; | |
| 220 | + u16 target; | |
| 221 | + u16 cfg; | |
| 222 | + u16 epp; | |
| 223 | + u16 cdyn; | |
| 224 | +}; | |
| 225 | + | |
| 226 | +static void wp_request_mtl(struct ivpu_device *vdev, struct wp_request *wp) | |
| 227 | +{ | |
| 228 | + u32 val; | |
| 229 | + | |
| 230 | + val = REGB_RD32(VPU_HW_BTRS_MTL_WP_REQ_PAYLOAD0); | |
| 231 | + val = REG_SET_FLD_NUM(VPU_HW_BTRS_MTL_WP_REQ_PAYLOAD0, MIN_RATIO, wp->min, val); | |
| 232 | + val = REG_SET_FLD_NUM(VPU_HW_BTRS_MTL_WP_REQ_PAYLOAD0, MAX_RATIO, wp->max, val); | |
| 233 | + REGB_WR32(VPU_HW_BTRS_MTL_WP_REQ_PAYLOAD0, val); | |
| 234 | + | |
| 235 | + val = REGB_RD32(VPU_HW_BTRS_MTL_WP_REQ_PAYLOAD1); | |
| 236 | + val = REG_SET_FLD_NUM(VPU_HW_BTRS_MTL_WP_REQ_PAYLOAD1, TARGET_RATIO, wp->target, val); | |
| 237 | + val = REG_SET_FLD_NUM(VPU_HW_BTRS_MTL_WP_REQ_PAYLOAD1, EPP, PLL_EPP_DEFAULT, val); | |
| 238 | + REGB_WR32(VPU_HW_BTRS_MTL_WP_REQ_PAYLOAD1, val); | |
| 239 | + | |
| 240 | + val = REGB_RD32(VPU_HW_BTRS_MTL_WP_REQ_PAYLOAD2); | |
| 241 | + val = REG_SET_FLD_NUM(VPU_HW_BTRS_MTL_WP_REQ_PAYLOAD2, CONFIG, wp->cfg, val); | |
| 242 | + REGB_WR32(VPU_HW_BTRS_MTL_WP_REQ_PAYLOAD2, val); | |
| 243 | + | |
| 244 | + val = REGB_RD32(VPU_HW_BTRS_MTL_WP_REQ_CMD); | |
| 245 | + val = REG_SET_FLD(VPU_HW_BTRS_MTL_WP_REQ_CMD, SEND, val); | |
| 246 | + REGB_WR32(VPU_HW_BTRS_MTL_WP_REQ_CMD, val); | |
| 247 | +} | |
| 248 | + | |
| 249 | +static void wp_request_lnl(struct ivpu_device *vdev, struct wp_request *wp) | |
| 250 | +{ | |
| 251 | + u32 val; | |
| 252 | + | |
| 253 | + val = REGB_RD32(VPU_HW_BTRS_LNL_WP_REQ_PAYLOAD0); | |
| 254 | + val = REG_SET_FLD_NUM(VPU_HW_BTRS_LNL_WP_REQ_PAYLOAD0, MIN_RATIO, wp->min, val); | |
| 255 | + val = REG_SET_FLD_NUM(VPU_HW_BTRS_LNL_WP_REQ_PAYLOAD0, MAX_RATIO, wp->max, val); | |
| 256 | + REGB_WR32(VPU_HW_BTRS_LNL_WP_REQ_PAYLOAD0, val); | |
| 257 | + | |
| 258 | + val = REGB_RD32(VPU_HW_BTRS_LNL_WP_REQ_PAYLOAD1); | |
| 259 | + val = REG_SET_FLD_NUM(VPU_HW_BTRS_LNL_WP_REQ_PAYLOAD1, TARGET_RATIO, wp->target, val); | |
| 260 | + val = REG_SET_FLD_NUM(VPU_HW_BTRS_LNL_WP_REQ_PAYLOAD1, EPP, wp->epp, val); | |
| 261 | + REGB_WR32(VPU_HW_BTRS_LNL_WP_REQ_PAYLOAD1, val); | |
| 262 | + | |
| 263 | + val = REGB_RD32(VPU_HW_BTRS_LNL_WP_REQ_PAYLOAD2); | |
| 264 | + val = REG_SET_FLD_NUM(VPU_HW_BTRS_LNL_WP_REQ_PAYLOAD2, CONFIG, wp->cfg, val); | |
| 265 | + val = REG_SET_FLD_NUM(VPU_HW_BTRS_LNL_WP_REQ_PAYLOAD2, CDYN, wp->cdyn, val); | |
| 266 | + REGB_WR32(VPU_HW_BTRS_LNL_WP_REQ_PAYLOAD2, val); | |
| 267 | + | |
| 268 | + val = REGB_RD32(VPU_HW_BTRS_LNL_WP_REQ_CMD); | |
| 269 | + val = REG_SET_FLD(VPU_HW_BTRS_LNL_WP_REQ_CMD, SEND, val); | |
| 270 | + REGB_WR32(VPU_HW_BTRS_LNL_WP_REQ_CMD, val); | |
| 271 | +} | |
| 272 | + | |
| 273 | +static void wp_request(struct ivpu_device *vdev, struct wp_request *wp) | |
| 274 | +{ | |
| 275 | + if (ivpu_hw_btrs_gen(vdev) == IVPU_HW_BTRS_MTL) | |
| 276 | + wp_request_mtl(vdev, wp); | |
| 277 | + else | |
| 278 | + wp_request_lnl(vdev, wp); | |
| 279 | +} | |
| 280 | + | |
| 281 | +static int wp_request_send(struct ivpu_device *vdev, struct wp_request *wp) | |
| 282 | +{ | |
| 283 | + int ret; | |
| 284 | + | |
| 285 | + ret = wp_request_sync(vdev); | |
| 286 | + if (ret) { | |
| 287 | + ivpu_err(vdev, "Failed to sync before workpoint request: %d\n", ret); | |
| 288 | + return ret; | |
| 289 | + } | |
| 290 | + | |
| 291 | + wp_request(vdev, wp); | |
| 292 | + | |
| 293 | + ret = wp_request_sync(vdev); | |
| 294 | + if (ret) | |
| 295 | + ivpu_err(vdev, "Failed to sync after workpoint request: %d\n", ret); | |
| 296 | + | |
| 297 | + return ret; | |
| 298 | +} | |
| 299 | + | |
| 300 | +static void prepare_wp_request(struct ivpu_device *vdev, struct wp_request *wp, bool enable) | |
| 301 | +{ | |
| 302 | + struct ivpu_hw_info *hw = vdev->hw; | |
| 303 | + | |
| 304 | + wp->min = hw->pll.min_ratio; | |
| 305 | + wp->max = hw->pll.max_ratio; | |
| 306 | + | |
| 307 | + if (ivpu_hw_btrs_gen(vdev) == IVPU_HW_BTRS_MTL) { | |
| 308 | + wp->target = enable ? hw->pll.pn_ratio : 0; | |
| 309 | + wp->cfg = enable ? hw->config : 0; | |
| 310 | + wp->cdyn = 0; | |
| 311 | + wp->epp = 0; | |
| 312 | + } else { | |
| 313 | + wp->target = hw->pll.pn_ratio; | |
| 314 | + wp->cfg = enable ? PLL_CONFIG_DEFAULT : 0; | |
| 315 | + wp->cdyn = enable ? PLL_CDYN_DEFAULT : 0; | |
| 316 | + wp->epp = enable ? PLL_EPP_DEFAULT : 0; | |
| 317 | + } | |
| 318 | + | |
| 319 | + /* Simics cannot start without at least one tile */ | |
| 320 | + if (enable && ivpu_is_simics(vdev)) | |
| 321 | + wp->cfg = 1; | |
| 322 | +} | |
| 323 | + | |
| 324 | +static int wait_for_pll_lock(struct ivpu_device *vdev, bool enable) | |
| 325 | +{ | |
| 326 | + u32 exp_val = enable ? 0x1 : 0x0; | |
| 327 | + | |
| 328 | + if (ivpu_hw_btrs_gen(vdev) != IVPU_HW_BTRS_MTL) | |
| 329 | + return 0; | |
| 330 | + | |
| 331 | + if (IVPU_WA(punit_disabled)) | |
| 332 | + return 0; | |
| 333 | + | |
| 334 | + return REGB_POLL_FLD(VPU_HW_BTRS_MTL_PLL_STATUS, LOCK, exp_val, PLL_TIMEOUT_US); | |
| 335 | +} | |
| 336 | + | |
| 337 | +int ivpu_hw_btrs_wp_drive(struct ivpu_device *vdev, bool enable) | |
| 338 | +{ | |
| 339 | + struct wp_request wp; | |
| 340 | + int ret; | |
| 341 | + | |
| 342 | + if (IVPU_WA(punit_disabled)) { | |
| 343 | + ivpu_dbg(vdev, PM, "Skipping workpoint request\n"); | |
| 344 | + return 0; | |
| 345 | + } | |
| 346 | + | |
| 347 | + prepare_wp_request(vdev, &wp, enable); | |
| 348 | + | |
| 349 | + ivpu_dbg(vdev, PM, "PLL workpoint request: %u Hz, config: 0x%x, epp: 0x%x, cdyn: 0x%x\n", | |
| 350 | + PLL_RATIO_TO_FREQ(wp.target), wp.cfg, wp.epp, wp.cdyn); | |
| 351 | + | |
| 352 | + ret = wp_request_send(vdev, &wp); | |
| 353 | + if (ret) { | |
| 354 | + ivpu_err(vdev, "Failed to send workpoint request: %d\n", ret); | |
| 355 | + return ret; | |
| 356 | + } | |
| 357 | + | |
| 358 | + ret = wait_for_pll_lock(vdev, enable); | |
| 359 | + if (ret) { | |
| 360 | + ivpu_err(vdev, "Timed out waiting for PLL lock\n"); | |
| 361 | + return ret; | |
| 362 | + } | |
| 363 | + | |
| 364 | + ret = wait_for_status_ready(vdev, enable); | |
| 365 | + if (ret) { | |
| 366 | + ivpu_err(vdev, "Timed out waiting for NPU ready status\n"); | |
| 367 | + return ret; | |
| 368 | + } | |
| 369 | + | |
| 370 | + return 0; | |
| 371 | +} | |
| 372 | + | |
| 373 | +static int d0i3_drive_mtl(struct ivpu_device *vdev, bool enable) | |
| 374 | +{ | |
| 375 | + int ret; | |
| 376 | + u32 val; | |
| 377 | + | |
| 378 | + ret = REGB_POLL_FLD(VPU_HW_BTRS_MTL_VPU_D0I3_CONTROL, INPROGRESS, 0, TIMEOUT_US); | |
| 379 | + if (ret) { | |
| 380 | + ivpu_err(vdev, "Failed to sync before D0i3 transition: %d\n", ret); | |
| 381 | + return ret; | |
| 382 | + } | |
| 383 | + | |
| 384 | + val = REGB_RD32(VPU_HW_BTRS_MTL_VPU_D0I3_CONTROL); | |
| 385 | + if (enable) | |
| 386 | + val = REG_SET_FLD(VPU_HW_BTRS_MTL_VPU_D0I3_CONTROL, I3, val); | |
| 387 | + else | |
| 388 | + val = REG_CLR_FLD(VPU_HW_BTRS_MTL_VPU_D0I3_CONTROL, I3, val); | |
| 389 | + REGB_WR32(VPU_HW_BTRS_MTL_VPU_D0I3_CONTROL, val); | |
| 390 | + | |
| 391 | + ret = REGB_POLL_FLD(VPU_HW_BTRS_MTL_VPU_D0I3_CONTROL, INPROGRESS, 0, TIMEOUT_US); | |
| 392 | + if (ret) | |
| 393 | + ivpu_err(vdev, "Failed to sync after D0i3 transition: %d\n", ret); | |
| 394 | + | |
| 395 | + return ret; | |
| 396 | +} | |
| 397 | + | |
| 398 | +static int d0i3_drive_lnl(struct ivpu_device *vdev, bool enable) | |
| 399 | +{ | |
| 400 | + int ret; | |
| 401 | + u32 val; | |
| 402 | + | |
| 403 | + ret = REGB_POLL_FLD(VPU_HW_BTRS_LNL_D0I3_CONTROL, INPROGRESS, 0, TIMEOUT_US); | |
| 404 | + if (ret) { | |
| 405 | + ivpu_err(vdev, "Failed to sync before D0i3 transition: %d\n", ret); | |
| 406 | + return ret; | |
| 407 | + } | |
| 408 | + | |
| 409 | + val = REGB_RD32(VPU_HW_BTRS_LNL_D0I3_CONTROL); | |
| 410 | + if (enable) | |
| 411 | + val = REG_SET_FLD(VPU_HW_BTRS_LNL_D0I3_CONTROL, I3, val); | |
| 412 | + else | |
| 413 | + val = REG_CLR_FLD(VPU_HW_BTRS_LNL_D0I3_CONTROL, I3, val); | |
| 414 | + REGB_WR32(VPU_HW_BTRS_LNL_D0I3_CONTROL, val); | |
| 415 | + | |
| 416 | + ret = REGB_POLL_FLD(VPU_HW_BTRS_LNL_D0I3_CONTROL, INPROGRESS, 0, TIMEOUT_US); | |
| 417 | + if (ret) { | |
| 418 | + ivpu_err(vdev, "Failed to sync after D0i3 transition: %d\n", ret); | |
| 419 | + return ret; | |
| 420 | + } | |
| 421 | + | |
| 422 | + return 0; | |
| 423 | +} | |
| 424 | + | |
| 425 | +static int d0i3_drive(struct ivpu_device *vdev, bool enable) | |
| 426 | +{ | |
| 427 | + if (ivpu_hw_btrs_gen(vdev) == IVPU_HW_BTRS_MTL) | |
| 428 | + return d0i3_drive_mtl(vdev, enable); | |
| 429 | + else | |
| 430 | + return d0i3_drive_lnl(vdev, enable); | |
| 431 | +} | |
| 432 | + | |
| 433 | +int ivpu_hw_btrs_d0i3_enable(struct ivpu_device *vdev) | |
| 434 | +{ | |
| 435 | + int ret; | |
| 436 | + | |
| 437 | + if (IVPU_WA(punit_disabled)) | |
| 438 | + return 0; | |
| 439 | + | |
| 440 | + ret = d0i3_drive(vdev, true); | |
| 441 | + if (ret) | |
| 442 | + ivpu_err(vdev, "Failed to enable D0i3: %d\n", ret); | |
| 443 | + | |
| 444 | + udelay(5); /* VPU requires 5 us to complete the transition */ | |
| 445 | + | |
| 446 | + return ret; | |
| 447 | +} | |
| 448 | + | |
| 449 | +int ivpu_hw_btrs_d0i3_disable(struct ivpu_device *vdev) | |
| 450 | +{ | |
| 451 | + int ret; | |
| 452 | + | |
| 453 | + if (IVPU_WA(punit_disabled)) | |
| 454 | + return 0; | |
| 455 | + | |
| 456 | + ret = d0i3_drive(vdev, false); | |
| 457 | + if (ret) | |
| 458 | + ivpu_err(vdev, "Failed to disable D0i3: %d\n", ret); | |
| 459 | + | |
| 460 | + return ret; | |
| 461 | +} | |
| 462 | + | |
| 463 | +int ivpu_hw_btrs_wait_for_clock_res_own_ack(struct ivpu_device *vdev) | |
| 464 | +{ | |
| 465 | + if (ivpu_hw_btrs_gen(vdev) == IVPU_HW_BTRS_MTL) | |
| 466 | + return 0; | |
| 467 | + | |
| 468 | + if (ivpu_is_simics(vdev)) | |
| 469 | + return 0; | |
| 470 | + | |
| 471 | + return REGB_POLL_FLD(VPU_HW_BTRS_LNL_VPU_STATUS, CLOCK_RESOURCE_OWN_ACK, 1, TIMEOUT_US); | |
| 472 | +} | |
| 473 | + | |
| 474 | +void ivpu_hw_btrs_set_port_arbitration_weights_lnl(struct ivpu_device *vdev) | |
| 475 | +{ | |
| 476 | + REGB_WR32(VPU_HW_BTRS_LNL_PORT_ARBITRATION_WEIGHTS, WEIGHTS_DEFAULT); | |
| 477 | + REGB_WR32(VPU_HW_BTRS_LNL_PORT_ARBITRATION_WEIGHTS_ATS, WEIGHTS_ATS_DEFAULT); | |
| 478 | +} | |
| 479 | + | |
| 480 | +static int ip_reset_mtl(struct ivpu_device *vdev) | |
| 481 | +{ | |
| 482 | + int ret; | |
| 483 | + u32 val; | |
| 484 | + | |
| 485 | + ret = REGB_POLL_FLD(VPU_HW_BTRS_MTL_VPU_IP_RESET, TRIGGER, 0, TIMEOUT_US); | |
| 486 | + if (ret) { | |
| 487 | + ivpu_err(vdev, "Timed out waiting for TRIGGER bit\n"); | |
| 488 | + return ret; | |
| 489 | + } | |
| 490 | + | |
| 491 | + val = REGB_RD32(VPU_HW_BTRS_MTL_VPU_IP_RESET); | |
| 492 | + val = REG_SET_FLD(VPU_HW_BTRS_MTL_VPU_IP_RESET, TRIGGER, val); | |
| 493 | + REGB_WR32(VPU_HW_BTRS_MTL_VPU_IP_RESET, val); | |
| 494 | + | |
| 495 | + ret = REGB_POLL_FLD(VPU_HW_BTRS_MTL_VPU_IP_RESET, TRIGGER, 0, TIMEOUT_US); | |
| 496 | + if (ret) | |
| 497 | + ivpu_err(vdev, "Timed out waiting for RESET completion\n"); | |
| 498 | + | |
| 499 | + return ret; | |
| 500 | +} | |
| 501 | + | |
| 502 | +static int ip_reset_lnl(struct ivpu_device *vdev) | |
| 503 | +{ | |
| 504 | + int ret; | |
| 505 | + u32 val; | |
| 506 | + | |
| 507 | + ivpu_hw_btrs_clock_relinquish_disable_lnl(vdev); | |
| 508 | + | |
| 509 | + ret = REGB_POLL_FLD(VPU_HW_BTRS_LNL_IP_RESET, TRIGGER, 0, TIMEOUT_US); | |
| 510 | + if (ret) { | |
| 511 | + ivpu_err(vdev, "Wait for *_TRIGGER timed out\n"); | |
| 512 | + return ret; | |
| 513 | + } | |
| 514 | + | |
| 515 | + val = REGB_RD32(VPU_HW_BTRS_LNL_IP_RESET); | |
| 516 | + val = REG_SET_FLD(VPU_HW_BTRS_LNL_IP_RESET, TRIGGER, val); | |
| 517 | + REGB_WR32(VPU_HW_BTRS_LNL_IP_RESET, val); | |
| 518 | + | |
| 519 | + ret = REGB_POLL_FLD(VPU_HW_BTRS_LNL_IP_RESET, TRIGGER, 0, TIMEOUT_US); | |
| 520 | + if (ret) | |
| 521 | + ivpu_err(vdev, "Timed out waiting for RESET completion\n"); | |
| 522 | + | |
| 523 | + return ret; | |
| 524 | +} | |
| 525 | + | |
| 526 | +int ivpu_hw_btrs_ip_reset(struct ivpu_device *vdev) | |
| 527 | +{ | |
| 528 | + if (IVPU_WA(punit_disabled)) | |
| 529 | + return 0; | |
| 530 | + | |
| 531 | + if (ivpu_hw_btrs_gen(vdev) == IVPU_HW_BTRS_MTL) | |
| 532 | + return ip_reset_mtl(vdev); | |
| 533 | + else | |
| 534 | + return ip_reset_lnl(vdev); | |
| 535 | +} | |
| 536 | + | |
| 537 | +void ivpu_hw_btrs_profiling_freq_reg_set_lnl(struct ivpu_device *vdev) | |
| 538 | +{ | |
| 539 | + u32 val = REGB_RD32(VPU_HW_BTRS_LNL_VPU_STATUS); | |
| 540 | + | |
| 541 | + if (vdev->hw->pll.profiling_freq == PLL_PROFILING_FREQ_DEFAULT) | |
| 542 | + val = REG_CLR_FLD(VPU_HW_BTRS_LNL_VPU_STATUS, PERF_CLK, val); | |
| 543 | + else | |
| 544 | + val = REG_SET_FLD(VPU_HW_BTRS_LNL_VPU_STATUS, PERF_CLK, val); | |
| 545 | + | |
| 546 | + REGB_WR32(VPU_HW_BTRS_LNL_VPU_STATUS, val); | |
| 547 | +} | |
| 548 | + | |
| 549 | +void ivpu_hw_btrs_ats_print_lnl(struct ivpu_device *vdev) | |
| 550 | +{ | |
| 551 | + ivpu_dbg(vdev, MISC, "Buttress ATS: %s\n", | |
| 552 | + REGB_RD32(VPU_HW_BTRS_LNL_HM_ATS) ? "Enable" : "Disable"); | |
| 553 | +} | |
| 554 | + | |
| 555 | +void ivpu_hw_btrs_clock_relinquish_disable_lnl(struct ivpu_device *vdev) | |
| 556 | +{ | |
| 557 | + u32 val = REGB_RD32(VPU_HW_BTRS_LNL_VPU_STATUS); | |
| 558 | + | |
| 559 | + val = REG_SET_FLD(VPU_HW_BTRS_LNL_VPU_STATUS, DISABLE_CLK_RELINQUISH, val); | |
| 560 | + REGB_WR32(VPU_HW_BTRS_LNL_VPU_STATUS, val); | |
| 561 | +} | |
| 562 | + | |
| 563 | +bool ivpu_hw_btrs_is_idle(struct ivpu_device *vdev) | |
| 564 | +{ | |
| 565 | + u32 val; | |
| 566 | + | |
| 567 | + if (IVPU_WA(punit_disabled)) | |
| 568 | + return true; | |
| 569 | + | |
| 570 | + if (ivpu_hw_btrs_gen(vdev) == IVPU_HW_BTRS_MTL) { | |
| 571 | + val = REGB_RD32(VPU_HW_BTRS_MTL_VPU_STATUS); | |
| 572 | + | |
| 573 | + return REG_TEST_FLD(VPU_HW_BTRS_MTL_VPU_STATUS, READY, val) && | |
| 574 | + REG_TEST_FLD(VPU_HW_BTRS_MTL_VPU_STATUS, IDLE, val); | |
| 575 | + } else { | |
| 576 | + val = REGB_RD32(VPU_HW_BTRS_LNL_VPU_STATUS); | |
| 577 | + | |
| 578 | + return REG_TEST_FLD(VPU_HW_BTRS_LNL_VPU_STATUS, READY, val) && | |
| 579 | + REG_TEST_FLD(VPU_HW_BTRS_LNL_VPU_STATUS, IDLE, val); | |
| 580 | + } | |
| 581 | +} | |
| 582 | + | |
| 583 | +int ivpu_hw_btrs_wait_for_idle(struct ivpu_device *vdev) | |
| 584 | +{ | |
| 585 | + if (ivpu_hw_btrs_gen(vdev) == IVPU_HW_BTRS_MTL) | |
| 586 | + return REGB_POLL_FLD(VPU_HW_BTRS_MTL_VPU_STATUS, IDLE, 0x1, IDLE_TIMEOUT_US); | |
| 587 | + else | |
| 588 | + return REGB_POLL_FLD(VPU_HW_BTRS_LNL_VPU_STATUS, IDLE, 0x1, IDLE_TIMEOUT_US); | |
| 589 | +} | |
| 590 | + | |
| 591 | +/* Handler for IRQs from Buttress core (irqB) */ | |
| 592 | +bool ivpu_hw_btrs_irq_handler_mtl(struct ivpu_device *vdev, int irq) | |
| 593 | +{ | |
| 594 | + u32 status = REGB_RD32(VPU_HW_BTRS_MTL_INTERRUPT_STAT) & BTRS_MTL_IRQ_MASK; | |
| 595 | + bool schedule_recovery = false; | |
| 596 | + | |
| 597 | + if (!status) | |
| 598 | + return false; | |
| 599 | + | |
| 600 | + if (REG_TEST_FLD(VPU_HW_BTRS_MTL_INTERRUPT_STAT, FREQ_CHANGE, status)) | |
| 601 | + ivpu_dbg(vdev, IRQ, "FREQ_CHANGE irq: %08x", | |
| 602 | + REGB_RD32(VPU_HW_BTRS_MTL_CURRENT_PLL)); | |
| 603 | + | |
| 604 | + if (REG_TEST_FLD(VPU_HW_BTRS_MTL_INTERRUPT_STAT, ATS_ERR, status)) { | |
| 605 | + ivpu_err(vdev, "ATS_ERR irq 0x%016llx", REGB_RD64(VPU_HW_BTRS_MTL_ATS_ERR_LOG_0)); | |
| 606 | + REGB_WR32(VPU_HW_BTRS_MTL_ATS_ERR_CLEAR, 0x1); | |
| 607 | + schedule_recovery = true; | |
| 608 | + } | |
| 609 | + | |
| 610 | + if (REG_TEST_FLD(VPU_HW_BTRS_MTL_INTERRUPT_STAT, UFI_ERR, status)) { | |
| 611 | + u32 ufi_log = REGB_RD32(VPU_HW_BTRS_MTL_UFI_ERR_LOG); | |
| 612 | + | |
| 613 | + ivpu_err(vdev, "UFI_ERR irq (0x%08x) opcode: 0x%02lx axi_id: 0x%02lx cq_id: 0x%03lx", | |
| 614 | + ufi_log, REG_GET_FLD(VPU_HW_BTRS_MTL_UFI_ERR_LOG, OPCODE, ufi_log), | |
| 615 | + REG_GET_FLD(VPU_HW_BTRS_MTL_UFI_ERR_LOG, AXI_ID, ufi_log), | |
| 616 | + REG_GET_FLD(VPU_HW_BTRS_MTL_UFI_ERR_LOG, CQ_ID, ufi_log)); | |
| 617 | + REGB_WR32(VPU_HW_BTRS_MTL_UFI_ERR_CLEAR, 0x1); | |
| 618 | + schedule_recovery = true; | |
| 619 | + } | |
| 620 | + | |
| 621 | + /* This must be done after interrupts are cleared at the source. */ | |
| 622 | + if (IVPU_WA(interrupt_clear_with_0)) | |
| 623 | + /* | |
| 624 | + * Writing 1 triggers an interrupt, so we can't perform read update write. | |
| 625 | + * Clear local interrupt status by writing 0 to all bits. | |
| 626 | + */ | |
| 627 | + REGB_WR32(VPU_HW_BTRS_MTL_INTERRUPT_STAT, 0x0); | |
| 628 | + else | |
| 629 | + REGB_WR32(VPU_HW_BTRS_MTL_INTERRUPT_STAT, status); | |
| 630 | + | |
| 631 | + if (schedule_recovery) | |
| 632 | + ivpu_pm_trigger_recovery(vdev, "Buttress IRQ"); | |
| 633 | + | |
| 634 | + return true; | |
| 635 | +} | |
| 636 | + | |
| 637 | +/* Handler for IRQs from Buttress core (irqB) */ | |
| 638 | +bool ivpu_hw_btrs_irq_handler_lnl(struct ivpu_device *vdev, int irq) | |
| 639 | +{ | |
| 640 | + u32 status = REGB_RD32(VPU_HW_BTRS_LNL_INTERRUPT_STAT) & BTRS_LNL_IRQ_MASK; | |
| 641 | + bool schedule_recovery = false; | |
| 642 | + | |
| 643 | + if (!status) | |
| 644 | + return false; | |
| 645 | + | |
| 646 | + if (REG_TEST_FLD(VPU_HW_BTRS_LNL_INTERRUPT_STAT, SURV_ERR, status)) { | |
| 647 | + ivpu_dbg(vdev, IRQ, "Survivability IRQ\n"); | |
| 648 | + if (!kfifo_put(&vdev->hw->irq.fifo, IVPU_HW_IRQ_SRC_DCT)) | |
| 649 | + ivpu_err_ratelimited(vdev, "IRQ FIFO full\n"); | |
| 650 | + } | |
| 651 | + | |
| 652 | + if (REG_TEST_FLD(VPU_HW_BTRS_LNL_INTERRUPT_STAT, FREQ_CHANGE, status)) | |
| 653 | + ivpu_dbg(vdev, IRQ, "FREQ_CHANGE irq: %08x", REGB_RD32(VPU_HW_BTRS_LNL_PLL_FREQ)); | |
| 654 | + | |
| 655 | + if (REG_TEST_FLD(VPU_HW_BTRS_LNL_INTERRUPT_STAT, ATS_ERR, status)) { | |
| 656 | + ivpu_err(vdev, "ATS_ERR LOG1 0x%08x ATS_ERR_LOG2 0x%08x\n", | |
| 657 | + REGB_RD32(VPU_HW_BTRS_LNL_ATS_ERR_LOG1), | |
| 658 | + REGB_RD32(VPU_HW_BTRS_LNL_ATS_ERR_LOG2)); | |
| 659 | + REGB_WR32(VPU_HW_BTRS_LNL_ATS_ERR_CLEAR, 0x1); | |
| 660 | + schedule_recovery = true; | |
| 661 | + } | |
| 662 | + | |
| 663 | + if (REG_TEST_FLD(VPU_HW_BTRS_LNL_INTERRUPT_STAT, CFI0_ERR, status)) { | |
| 664 | + ivpu_err(vdev, "CFI0_ERR 0x%08x", REGB_RD32(VPU_HW_BTRS_LNL_CFI0_ERR_LOG)); | |
| 665 | + REGB_WR32(VPU_HW_BTRS_LNL_CFI0_ERR_CLEAR, 0x1); | |
| 666 | + schedule_recovery = true; | |
| 667 | + } | |
| 668 | + | |
| 669 | + if (REG_TEST_FLD(VPU_HW_BTRS_LNL_INTERRUPT_STAT, CFI1_ERR, status)) { | |
| 670 | + ivpu_err(vdev, "CFI1_ERR 0x%08x", REGB_RD32(VPU_HW_BTRS_LNL_CFI1_ERR_LOG)); | |
| 671 | + REGB_WR32(VPU_HW_BTRS_LNL_CFI1_ERR_CLEAR, 0x1); | |
| 672 | + schedule_recovery = true; | |
| 673 | + } | |
| 674 | + | |
| 675 | + if (REG_TEST_FLD(VPU_HW_BTRS_LNL_INTERRUPT_STAT, IMR0_ERR, status)) { | |
| 676 | + ivpu_err(vdev, "IMR_ERR_CFI0 LOW: 0x%08x HIGH: 0x%08x", | |
| 677 | + REGB_RD32(VPU_HW_BTRS_LNL_IMR_ERR_CFI0_LOW), | |
| 678 | + REGB_RD32(VPU_HW_BTRS_LNL_IMR_ERR_CFI0_HIGH)); | |
| 679 | + REGB_WR32(VPU_HW_BTRS_LNL_IMR_ERR_CFI0_CLEAR, 0x1); | |
| 680 | + schedule_recovery = true; | |
| 681 | + } | |
| 682 | + | |
| 683 | + if (REG_TEST_FLD(VPU_HW_BTRS_LNL_INTERRUPT_STAT, IMR1_ERR, status)) { | |
| 684 | + ivpu_err(vdev, "IMR_ERR_CFI1 LOW: 0x%08x HIGH: 0x%08x", | |
| 685 | + REGB_RD32(VPU_HW_BTRS_LNL_IMR_ERR_CFI1_LOW), | |
| 686 | + REGB_RD32(VPU_HW_BTRS_LNL_IMR_ERR_CFI1_HIGH)); | |
| 687 | + REGB_WR32(VPU_HW_BTRS_LNL_IMR_ERR_CFI1_CLEAR, 0x1); | |
| 688 | + schedule_recovery = true; | |
| 689 | + } | |
| 690 | + | |
| 691 | + /* This must be done after interrupts are cleared at the source. */ | |
| 692 | + REGB_WR32(VPU_HW_BTRS_LNL_INTERRUPT_STAT, status); | |
| 693 | + | |
| 694 | + if (schedule_recovery) | |
| 695 | + ivpu_pm_trigger_recovery(vdev, "Buttress IRQ"); | |
| 696 | + | |
| 697 | + return true; | |
| 698 | +} | |
| 699 | + | |
| 700 | +int ivpu_hw_btrs_dct_get_request(struct ivpu_device *vdev, bool *enable) | |
| 701 | +{ | |
| 702 | + u32 val = REGB_RD32(VPU_HW_BTRS_LNL_PCODE_MAILBOX_SHADOW); | |
| 703 | + u32 cmd = REG_GET_FLD(VPU_HW_BTRS_LNL_PCODE_MAILBOX_SHADOW, CMD, val); | |
| 704 | + u32 param1 = REG_GET_FLD(VPU_HW_BTRS_LNL_PCODE_MAILBOX_SHADOW, PARAM1, val); | |
| 705 | + | |
| 706 | + if (cmd != DCT_REQ) { | |
| 707 | + ivpu_err_ratelimited(vdev, "Unsupported PCODE command: 0x%x\n", cmd); | |
| 708 | + return -EBADR; | |
| 709 | + } | |
| 710 | + | |
| 711 | + switch (param1) { | |
| 712 | + case DCT_ENABLE: | |
| 713 | + *enable = true; | |
| 714 | + return 0; | |
| 715 | + case DCT_DISABLE: | |
| 716 | + *enable = false; | |
| 717 | + return 0; | |
| 718 | + default: | |
| 719 | + ivpu_err_ratelimited(vdev, "Invalid PARAM1 value: %u\n", param1); | |
| 720 | + return -EINVAL; | |
| 721 | + } | |
| 722 | +} | |
| 723 | + | |
| 724 | +void ivpu_hw_btrs_dct_set_status(struct ivpu_device *vdev, bool enable, u32 active_percent) | |
| 725 | +{ | |
| 726 | + u32 val = 0; | |
| 727 | + u32 cmd = enable ? DCT_ENABLE : DCT_DISABLE; | |
| 728 | + | |
| 729 | + val = REG_SET_FLD_NUM(VPU_HW_BTRS_LNL_PCODE_MAILBOX_STATUS, CMD, DCT_REQ, val); | |
| 730 | + val = REG_SET_FLD_NUM(VPU_HW_BTRS_LNL_PCODE_MAILBOX_STATUS, PARAM1, cmd, val); | |
| 731 | + val = REG_SET_FLD_NUM(VPU_HW_BTRS_LNL_PCODE_MAILBOX_STATUS, PARAM2, active_percent, val); | |
| 732 | + | |
| 733 | + REGB_WR32(VPU_HW_BTRS_LNL_PCODE_MAILBOX_STATUS, val); | |
| 734 | +} | |
| 735 | + | |
| 736 | +static u32 pll_ratio_to_freq_mtl(u32 ratio, u32 config) | |
| 737 | +{ | |
| 738 | + u32 pll_clock = PLL_REF_CLK_FREQ * ratio; | |
| 739 | + u32 cpu_clock; | |
| 740 | + | |
| 741 | + if ((config & 0xff) == MTL_PLL_RATIO_4_3) | |
| 742 | + cpu_clock = pll_clock * 2 / 4; | |
| 743 | + else | |
| 744 | + cpu_clock = pll_clock * 2 / 5; | |
| 745 | + | |
| 746 | + return cpu_clock; | |
| 747 | +} | |
| 748 | + | |
| 749 | +u32 ivpu_hw_btrs_ratio_to_freq(struct ivpu_device *vdev, u32 ratio) | |
| 750 | +{ | |
| 751 | + struct ivpu_hw_info *hw = vdev->hw; | |
| 752 | + | |
| 753 | + if (ivpu_hw_btrs_gen(vdev) == IVPU_HW_BTRS_MTL) | |
| 754 | + return pll_ratio_to_freq_mtl(ratio, hw->config); | |
| 755 | + else | |
| 756 | + return PLL_RATIO_TO_FREQ(ratio); | |
| 757 | +} | |
| 758 | + | |
| 759 | +static u32 pll_freq_get_mtl(struct ivpu_device *vdev) | |
| 760 | +{ | |
| 761 | + u32 pll_curr_ratio; | |
| 762 | + | |
| 763 | + pll_curr_ratio = REGB_RD32(VPU_HW_BTRS_MTL_CURRENT_PLL); | |
| 764 | + pll_curr_ratio &= VPU_HW_BTRS_MTL_CURRENT_PLL_RATIO_MASK; | |
| 765 | + | |
| 766 | + if (!ivpu_is_silicon(vdev)) | |
| 767 | + return PLL_SIMULATION_FREQ; | |
| 768 | + | |
| 769 | + return pll_ratio_to_freq_mtl(pll_curr_ratio, vdev->hw->config); | |
| 770 | +} | |
| 771 | + | |
| 772 | +static u32 pll_freq_get_lnl(struct ivpu_device *vdev) | |
| 773 | +{ | |
| 774 | + u32 pll_curr_ratio; | |
| 775 | + | |
| 776 | + pll_curr_ratio = REGB_RD32(VPU_HW_BTRS_LNL_PLL_FREQ); | |
| 777 | + pll_curr_ratio &= VPU_HW_BTRS_LNL_PLL_FREQ_RATIO_MASK; | |
| 778 | + | |
| 779 | + return PLL_RATIO_TO_FREQ(pll_curr_ratio); | |
| 780 | +} | |
| 781 | + | |
| 782 | +u32 ivpu_hw_btrs_pll_freq_get(struct ivpu_device *vdev) | |
| 783 | +{ | |
| 784 | + if (ivpu_hw_btrs_gen(vdev) == IVPU_HW_BTRS_MTL) | |
| 785 | + return pll_freq_get_mtl(vdev); | |
| 786 | + else | |
| 787 | + return pll_freq_get_lnl(vdev); | |
| 788 | +} | |
| 789 | + | |
| 790 | +u32 ivpu_hw_btrs_telemetry_offset_get(struct ivpu_device *vdev) | |
| 791 | +{ | |
| 792 | + if (ivpu_hw_btrs_gen(vdev) == IVPU_HW_BTRS_MTL) | |
| 793 | + return REGB_RD32(VPU_HW_BTRS_MTL_VPU_TELEMETRY_OFFSET); | |
| 794 | + else | |
| 795 | + return REGB_RD32(VPU_HW_BTRS_LNL_VPU_TELEMETRY_OFFSET); | |
| 796 | +} | |
| 797 | + | |
| 798 | +u32 ivpu_hw_btrs_telemetry_size_get(struct ivpu_device *vdev) | |
| 799 | +{ | |
| 800 | + if (ivpu_hw_btrs_gen(vdev) == IVPU_HW_BTRS_MTL) | |
| 801 | + return REGB_RD32(VPU_HW_BTRS_MTL_VPU_TELEMETRY_SIZE); | |
| 802 | + else | |
| 803 | + return REGB_RD32(VPU_HW_BTRS_LNL_VPU_TELEMETRY_SIZE); | |
| 804 | +} | |
| 805 | + | |
| 806 | +u32 ivpu_hw_btrs_telemetry_enable_get(struct ivpu_device *vdev) | |
| 807 | +{ | |
| 808 | + if (ivpu_hw_btrs_gen(vdev) == IVPU_HW_BTRS_MTL) | |
| 809 | + return REGB_RD32(VPU_HW_BTRS_MTL_VPU_TELEMETRY_ENABLE); | |
| 810 | + else | |
| 811 | + return REGB_RD32(VPU_HW_BTRS_LNL_VPU_TELEMETRY_ENABLE); | |
| 812 | +} | |
| 813 | + | |
| 814 | +void ivpu_hw_btrs_global_int_disable(struct ivpu_device *vdev) | |
| 815 | +{ | |
| 816 | + if (ivpu_hw_btrs_gen(vdev) == IVPU_HW_BTRS_MTL) | |
| 817 | + REGB_WR32(VPU_HW_BTRS_MTL_GLOBAL_INT_MASK, 0x1); | |
| 818 | + else | |
| 819 | + REGB_WR32(VPU_HW_BTRS_LNL_GLOBAL_INT_MASK, 0x1); | |
| 820 | +} | |
| 821 | + | |
| 822 | +void ivpu_hw_btrs_global_int_enable(struct ivpu_device *vdev) | |
| 823 | +{ | |
| 824 | + if (ivpu_hw_btrs_gen(vdev) == IVPU_HW_BTRS_MTL) | |
| 825 | + REGB_WR32(VPU_HW_BTRS_MTL_GLOBAL_INT_MASK, 0x0); | |
| 826 | + else | |
| 827 | + REGB_WR32(VPU_HW_BTRS_LNL_GLOBAL_INT_MASK, 0x0); | |
| 828 | +} | |
| 829 | + | |
| 830 | +void ivpu_hw_btrs_irq_enable(struct ivpu_device *vdev) | |
| 831 | +{ | |
| 832 | + if (ivpu_hw_btrs_gen(vdev) == IVPU_HW_BTRS_MTL) { | |
| 833 | + REGB_WR32(VPU_HW_BTRS_MTL_LOCAL_INT_MASK, (u32)(~BTRS_MTL_IRQ_MASK)); | |
| 834 | + REGB_WR32(VPU_HW_BTRS_MTL_GLOBAL_INT_MASK, 0x0); | |
| 835 | + } else { | |
| 836 | + REGB_WR32(VPU_HW_BTRS_LNL_LOCAL_INT_MASK, (u32)(~BTRS_LNL_IRQ_MASK)); | |
| 837 | + REGB_WR32(VPU_HW_BTRS_LNL_GLOBAL_INT_MASK, 0x0); | |
| 838 | + } | |
| 839 | +} | |
| 840 | + | |
| 841 | +void ivpu_hw_btrs_irq_disable(struct ivpu_device *vdev) | |
| 842 | +{ | |
| 843 | + if (ivpu_hw_btrs_gen(vdev) == IVPU_HW_BTRS_MTL) { | |
| 844 | + REGB_WR32(VPU_HW_BTRS_MTL_GLOBAL_INT_MASK, 0x1); | |
| 845 | + REGB_WR32(VPU_HW_BTRS_MTL_LOCAL_INT_MASK, BTRS_IRQ_DISABLE_MASK); | |
| 846 | + } else { | |
| 847 | + REGB_WR32(VPU_HW_BTRS_LNL_GLOBAL_INT_MASK, 0x1); | |
| 848 | + REGB_WR32(VPU_HW_BTRS_LNL_LOCAL_INT_MASK, BTRS_IRQ_DISABLE_MASK); | |
| 849 | + } | |
| 850 | +} | |
| 851 | + | |
| 852 | +static void diagnose_failure_mtl(struct ivpu_device *vdev) | |
| 853 | +{ | |
| 854 | + u32 reg = REGB_RD32(VPU_HW_BTRS_MTL_INTERRUPT_STAT) & BTRS_MTL_IRQ_MASK; | |
| 855 | + | |
| 856 | + if (REG_TEST_FLD(VPU_HW_BTRS_MTL_INTERRUPT_STAT, ATS_ERR, reg)) | |
| 857 | + ivpu_err(vdev, "ATS_ERR irq 0x%016llx", REGB_RD64(VPU_HW_BTRS_MTL_ATS_ERR_LOG_0)); | |
| 858 | + | |
| 859 | + if (REG_TEST_FLD(VPU_HW_BTRS_MTL_INTERRUPT_STAT, UFI_ERR, reg)) { | |
| 860 | + u32 log = REGB_RD32(VPU_HW_BTRS_MTL_UFI_ERR_LOG); | |
| 861 | + | |
| 862 | + ivpu_err(vdev, "UFI_ERR irq (0x%08x) opcode: 0x%02lx axi_id: 0x%02lx cq_id: 0x%03lx", | |
| 863 | + log, REG_GET_FLD(VPU_HW_BTRS_MTL_UFI_ERR_LOG, OPCODE, log), | |
| 864 | + REG_GET_FLD(VPU_HW_BTRS_MTL_UFI_ERR_LOG, AXI_ID, log), | |
| 865 | + REG_GET_FLD(VPU_HW_BTRS_MTL_UFI_ERR_LOG, CQ_ID, log)); | |
| 866 | + } | |
| 867 | +} | |
| 868 | + | |
| 869 | +static void diagnose_failure_lnl(struct ivpu_device *vdev) | |
| 870 | +{ | |
| 871 | + u32 reg = REGB_RD32(VPU_HW_BTRS_MTL_INTERRUPT_STAT) & BTRS_LNL_IRQ_MASK; | |
| 872 | + | |
| 873 | + if (REG_TEST_FLD(VPU_HW_BTRS_LNL_INTERRUPT_STAT, ATS_ERR, reg)) { | |
| 874 | + ivpu_err(vdev, "ATS_ERR_LOG1 0x%08x ATS_ERR_LOG2 0x%08x\n", | |
| 875 | + REGB_RD32(VPU_HW_BTRS_LNL_ATS_ERR_LOG1), | |
| 876 | + REGB_RD32(VPU_HW_BTRS_LNL_ATS_ERR_LOG2)); | |
| 877 | + } | |
| 878 | + | |
| 879 | + if (REG_TEST_FLD(VPU_HW_BTRS_LNL_INTERRUPT_STAT, CFI0_ERR, reg)) | |
| 880 | + ivpu_err(vdev, "CFI0_ERR_LOG 0x%08x\n", REGB_RD32(VPU_HW_BTRS_LNL_CFI0_ERR_LOG)); | |
| 881 | + | |
| 882 | + if (REG_TEST_FLD(VPU_HW_BTRS_LNL_INTERRUPT_STAT, CFI1_ERR, reg)) | |
| 883 | + ivpu_err(vdev, "CFI1_ERR_LOG 0x%08x\n", REGB_RD32(VPU_HW_BTRS_LNL_CFI1_ERR_LOG)); | |
| 884 | + | |
| 885 | + if (REG_TEST_FLD(VPU_HW_BTRS_LNL_INTERRUPT_STAT, IMR0_ERR, reg)) | |
| 886 | + ivpu_err(vdev, "IMR_ERR_CFI0 LOW: 0x%08x HIGH: 0x%08x\n", | |
| 887 | + REGB_RD32(VPU_HW_BTRS_LNL_IMR_ERR_CFI0_LOW), | |
| 888 | + REGB_RD32(VPU_HW_BTRS_LNL_IMR_ERR_CFI0_HIGH)); | |
| 889 | + | |
| 890 | + if (REG_TEST_FLD(VPU_HW_BTRS_LNL_INTERRUPT_STAT, IMR1_ERR, reg)) | |
| 891 | + ivpu_err(vdev, "IMR_ERR_CFI1 LOW: 0x%08x HIGH: 0x%08x\n", | |
| 892 | + REGB_RD32(VPU_HW_BTRS_LNL_IMR_ERR_CFI1_LOW), | |
| 893 | + REGB_RD32(VPU_HW_BTRS_LNL_IMR_ERR_CFI1_HIGH)); | |
| 894 | + | |
| 895 | + if (REG_TEST_FLD(VPU_HW_BTRS_LNL_INTERRUPT_STAT, SURV_ERR, reg)) | |
| 896 | + ivpu_err(vdev, "Survivability IRQ\n"); | |
| 897 | +} | |
| 898 | + | |
| 899 | +void ivpu_hw_btrs_diagnose_failure(struct ivpu_device *vdev) | |
| 900 | +{ | |
| 901 | + if (ivpu_hw_btrs_gen(vdev) == IVPU_HW_BTRS_MTL) | |
| 902 | + return diagnose_failure_mtl(vdev); | |
| 903 | + else | |
| 904 | + return diagnose_failure_lnl(vdev); | |
| 905 | +} | |
| @@ -0,0 +1,50 @@ | ||
| 1 | +/* SPDX-License-Identifier: GPL-2.0-only */ | |
| 2 | +/* | |
| 3 | + * Copyright (C) 2020-2024 Intel Corporation | |
| 4 | + */ | |
| 5 | + | |
| 6 | +#ifndef __IVPU_HW_BTRS_H__ | |
| 7 | +#define __IVPU_HW_BTRS_H__ | |
| 8 | + | |
| 9 | +#include "ivpu_drv.h" | |
| 10 | +#include "ivpu_hw_37xx_reg.h" | |
| 11 | +#include "ivpu_hw_40xx_reg.h" | |
| 12 | +#include "ivpu_hw_reg_io.h" | |
| 13 | + | |
| 14 | +#define PLL_PROFILING_FREQ_DEFAULT 38400000 | |
| 15 | +#define PLL_PROFILING_FREQ_HIGH 400000000 | |
| 16 | +#define PLL_RATIO_TO_FREQ(x) ((x) * PLL_REF_CLK_FREQ) | |
| 17 | + | |
| 18 | +#define DCT_DEFAULT_ACTIVE_PERCENT 15u | |
| 19 | +#define DCT_PERIOD_US 35300u | |
| 20 | + | |
| 21 | +int ivpu_hw_btrs_info_init(struct ivpu_device *vdev); | |
| 22 | +void ivpu_hw_btrs_freq_ratios_init(struct ivpu_device *vdev); | |
| 23 | +int ivpu_hw_btrs_irqs_clear_with_0_mtl(struct ivpu_device *vdev); | |
| 24 | +int ivpu_hw_btrs_wp_drive(struct ivpu_device *vdev, bool enable); | |
| 25 | +int ivpu_hw_btrs_wait_for_clock_res_own_ack(struct ivpu_device *vdev); | |
| 26 | +int ivpu_hw_btrs_d0i3_enable(struct ivpu_device *vdev); | |
| 27 | +int ivpu_hw_btrs_d0i3_disable(struct ivpu_device *vdev); | |
| 28 | +void ivpu_hw_btrs_set_port_arbitration_weights_lnl(struct ivpu_device *vdev); | |
| 29 | +bool ivpu_hw_btrs_is_idle(struct ivpu_device *vdev); | |
| 30 | +int ivpu_hw_btrs_wait_for_idle(struct ivpu_device *vdev); | |
| 31 | +int ivpu_hw_btrs_ip_reset(struct ivpu_device *vdev); | |
| 32 | +void ivpu_hw_btrs_profiling_freq_reg_set_lnl(struct ivpu_device *vdev); | |
| 33 | +void ivpu_hw_btrs_ats_print_lnl(struct ivpu_device *vdev); | |
| 34 | +void ivpu_hw_btrs_clock_relinquish_disable_lnl(struct ivpu_device *vdev); | |
| 35 | +bool ivpu_hw_btrs_irq_handler_mtl(struct ivpu_device *vdev, int irq); | |
| 36 | +bool ivpu_hw_btrs_irq_handler_lnl(struct ivpu_device *vdev, int irq); | |
| 37 | +int ivpu_hw_btrs_dct_get_request(struct ivpu_device *vdev, bool *enable); | |
| 38 | +void ivpu_hw_btrs_dct_set_status(struct ivpu_device *vdev, bool enable, u32 dct_percent); | |
| 39 | +u32 ivpu_hw_btrs_pll_freq_get(struct ivpu_device *vdev); | |
| 40 | +u32 ivpu_hw_btrs_ratio_to_freq(struct ivpu_device *vdev, u32 ratio); | |
| 41 | +u32 ivpu_hw_btrs_telemetry_offset_get(struct ivpu_device *vdev); | |
| 42 | +u32 ivpu_hw_btrs_telemetry_size_get(struct ivpu_device *vdev); | |
| 43 | +u32 ivpu_hw_btrs_telemetry_enable_get(struct ivpu_device *vdev); | |
| 44 | +void ivpu_hw_btrs_global_int_enable(struct ivpu_device *vdev); | |
| 45 | +void ivpu_hw_btrs_global_int_disable(struct ivpu_device *vdev); | |
| 46 | +void ivpu_hw_btrs_irq_enable(struct ivpu_device *vdev); | |
| 47 | +void ivpu_hw_btrs_irq_disable(struct ivpu_device *vdev); | |
| 48 | +void ivpu_hw_btrs_diagnose_failure(struct ivpu_device *vdev); | |
| 49 | + | |
| 50 | +#endif /* __IVPU_HW_BTRS_H__ */ | |
| @@ -0,0 +1,108 @@ | ||
| 1 | +/* SPDX-License-Identifier: GPL-2.0-only */ | |
| 2 | +/* | |
| 3 | + * Copyright (C) 2020-2024 Intel Corporation | |
| 4 | + */ | |
| 5 | + | |
| 6 | +#ifndef __IVPU_HW_BTRS_LNL_REG_H__ | |
| 7 | +#define __IVPU_HW_BTRS_LNL_REG_H__ | |
| 8 | + | |
| 9 | +#include <linux/bits.h> | |
| 10 | + | |
| 11 | +#define VPU_HW_BTRS_LNL_INTERRUPT_STAT 0x00000000u | |
| 12 | +#define VPU_HW_BTRS_LNL_INTERRUPT_STAT_FREQ_CHANGE_MASK BIT_MASK(0) | |
| 13 | +#define VPU_HW_BTRS_LNL_INTERRUPT_STAT_ATS_ERR_MASK BIT_MASK(1) | |
| 14 | +#define VPU_HW_BTRS_LNL_INTERRUPT_STAT_CFI0_ERR_MASK BIT_MASK(2) | |
| 15 | +#define VPU_HW_BTRS_LNL_INTERRUPT_STAT_CFI1_ERR_MASK BIT_MASK(3) | |
| 16 | +#define VPU_HW_BTRS_LNL_INTERRUPT_STAT_IMR0_ERR_MASK BIT_MASK(4) | |
| 17 | +#define VPU_HW_BTRS_LNL_INTERRUPT_STAT_IMR1_ERR_MASK BIT_MASK(5) | |
| 18 | +#define VPU_HW_BTRS_LNL_INTERRUPT_STAT_SURV_ERR_MASK BIT_MASK(6) | |
| 19 | + | |
| 20 | +#define VPU_HW_BTRS_LNL_LOCAL_INT_MASK 0x00000004u | |
| 21 | +#define VPU_HW_BTRS_LNL_GLOBAL_INT_MASK 0x00000008u | |
| 22 | + | |
| 23 | +#define VPU_HW_BTRS_LNL_HM_ATS 0x0000000cu | |
| 24 | + | |
| 25 | +#define VPU_HW_BTRS_LNL_ATS_ERR_LOG1 0x00000010u | |
| 26 | +#define VPU_HW_BTRS_LNL_ATS_ERR_LOG2 0x00000014u | |
| 27 | +#define VPU_HW_BTRS_LNL_ATS_ERR_CLEAR 0x00000018u | |
| 28 | + | |
| 29 | +#define VPU_HW_BTRS_LNL_CFI0_ERR_LOG 0x0000001cu | |
| 30 | +#define VPU_HW_BTRS_LNL_CFI0_ERR_CLEAR 0x00000020u | |
| 31 | + | |
| 32 | +#define VPU_HW_BTRS_LNL_PORT_ARBITRATION_WEIGHTS_ATS 0x00000024u | |
| 33 | + | |
| 34 | +#define VPU_HW_BTRS_LNL_CFI1_ERR_LOG 0x00000040u | |
| 35 | +#define VPU_HW_BTRS_LNL_CFI1_ERR_CLEAR 0x00000044u | |
| 36 | + | |
| 37 | +#define VPU_HW_BTRS_LNL_IMR_ERR_CFI0_LOW 0x00000048u | |
| 38 | +#define VPU_HW_BTRS_LNL_IMR_ERR_CFI0_HIGH 0x0000004cu | |
| 39 | +#define VPU_HW_BTRS_LNL_IMR_ERR_CFI0_CLEAR 0x00000050u | |
| 40 | + | |
| 41 | +#define VPU_HW_BTRS_LNL_PORT_ARBITRATION_WEIGHTS 0x00000054u | |
| 42 | + | |
| 43 | +#define VPU_HW_BTRS_LNL_IMR_ERR_CFI1_LOW 0x00000058u | |
| 44 | +#define VPU_HW_BTRS_LNL_IMR_ERR_CFI1_HIGH 0x0000005cu | |
| 45 | +#define VPU_HW_BTRS_LNL_IMR_ERR_CFI1_CLEAR 0x00000060u | |
| 46 | + | |
| 47 | +#define VPU_HW_BTRS_LNL_PCODE_MAILBOX_STATUS 0x00000070u | |
| 48 | +#define VPU_HW_BTRS_LNL_PCODE_MAILBOX_STATUS_CMD_MASK GENMASK(7, 0) | |
| 49 | +#define VPU_HW_BTRS_LNL_PCODE_MAILBOX_STATUS_PARAM1_MASK GENMASK(15, 8) | |
| 50 | +#define VPU_HW_BTRS_LNL_PCODE_MAILBOX_STATUS_PARAM2_MASK GENMASK(23, 16) | |
| 51 | +#define VPU_HW_BTRS_LNL_PCODE_MAILBOX_STATUS_PARAM3_MASK GENMASK(31, 24) | |
| 52 | + | |
| 53 | +#define VPU_HW_BTRS_LNL_PCODE_MAILBOX_SHADOW 0x00000074u | |
| 54 | +#define VPU_HW_BTRS_LNL_PCODE_MAILBOX_SHADOW_CMD_MASK GENMASK(7, 0) | |
| 55 | +#define VPU_HW_BTRS_LNL_PCODE_MAILBOX_SHADOW_PARAM1_MASK GENMASK(15, 8) | |
| 56 | +#define VPU_HW_BTRS_LNL_PCODE_MAILBOX_SHADOW_PARAM2_MASK GENMASK(23, 16) | |
| 57 | +#define VPU_HW_BTRS_LNL_PCODE_MAILBOX_SHADOW_PARAM3_MASK GENMASK(31, 24) | |
| 58 | + | |
| 59 | +#define VPU_HW_BTRS_LNL_WP_REQ_PAYLOAD0 0x00000130u | |
| 60 | +#define VPU_HW_BTRS_LNL_WP_REQ_PAYLOAD0_MIN_RATIO_MASK GENMASK(15, 0) | |
| 61 | +#define VPU_HW_BTRS_LNL_WP_REQ_PAYLOAD0_MAX_RATIO_MASK GENMASK(31, 16) | |
| 62 | + | |
| 63 | +#define VPU_HW_BTRS_LNL_WP_REQ_PAYLOAD1 0x00000134u | |
| 64 | +#define VPU_HW_BTRS_LNL_WP_REQ_PAYLOAD1_TARGET_RATIO_MASK GENMASK(15, 0) | |
| 65 | +#define VPU_HW_BTRS_LNL_WP_REQ_PAYLOAD1_EPP_MASK GENMASK(31, 16) | |
| 66 | + | |
| 67 | +#define VPU_HW_BTRS_LNL_WP_REQ_PAYLOAD2 0x00000138u | |
| 68 | +#define VPU_HW_BTRS_LNL_WP_REQ_PAYLOAD2_CONFIG_MASK GENMASK(15, 0) | |
| 69 | +#define VPU_HW_BTRS_LNL_WP_REQ_PAYLOAD2_CDYN_MASK GENMASK(31, 16) | |
| 70 | + | |
| 71 | +#define VPU_HW_BTRS_LNL_WP_REQ_CMD 0x0000013cu | |
| 72 | +#define VPU_HW_BTRS_LNL_WP_REQ_CMD_SEND_MASK BIT_MASK(0) | |
| 73 | + | |
| 74 | +#define VPU_HW_BTRS_LNL_PLL_FREQ 0x00000148u | |
| 75 | +#define VPU_HW_BTRS_LNL_PLL_FREQ_RATIO_MASK GENMASK(15, 0) | |
| 76 | + | |
| 77 | +#define VPU_HW_BTRS_LNL_TILE_FUSE 0x00000150u | |
| 78 | +#define VPU_HW_BTRS_LNL_TILE_FUSE_VALID_MASK BIT_MASK(0) | |
| 79 | +#define VPU_HW_BTRS_LNL_TILE_FUSE_CONFIG_MASK GENMASK(6, 1) | |
| 80 | + | |
| 81 | +#define VPU_HW_BTRS_LNL_VPU_STATUS 0x00000154u | |
| 82 | +#define VPU_HW_BTRS_LNL_VPU_STATUS_READY_MASK BIT_MASK(0) | |
| 83 | +#define VPU_HW_BTRS_LNL_VPU_STATUS_IDLE_MASK BIT_MASK(1) | |
| 84 | +#define VPU_HW_BTRS_LNL_VPU_STATUS_DUP_IDLE_MASK BIT_MASK(2) | |
| 85 | +#define VPU_HW_BTRS_LNL_VPU_STATUS_CLOCK_RESOURCE_OWN_ACK_MASK BIT_MASK(6) | |
| 86 | +#define VPU_HW_BTRS_LNL_VPU_STATUS_POWER_RESOURCE_OWN_ACK_MASK BIT_MASK(7) | |
| 87 | +#define VPU_HW_BTRS_LNL_VPU_STATUS_PERF_CLK_MASK BIT_MASK(11) | |
| 88 | +#define VPU_HW_BTRS_LNL_VPU_STATUS_DISABLE_CLK_RELINQUISH_MASK BIT_MASK(12) | |
| 89 | + | |
| 90 | +#define VPU_HW_BTRS_LNL_IP_RESET 0x00000160u | |
| 91 | +#define VPU_HW_BTRS_LNL_IP_RESET_TRIGGER_MASK BIT_MASK(0) | |
| 92 | + | |
| 93 | +#define VPU_HW_BTRS_LNL_D0I3_CONTROL 0x00000164u | |
| 94 | +#define VPU_HW_BTRS_LNL_D0I3_CONTROL_INPROGRESS_MASK BIT_MASK(0) | |
| 95 | +#define VPU_HW_BTRS_LNL_D0I3_CONTROL_I3_MASK BIT_MASK(2) | |
| 96 | + | |
| 97 | +#define VPU_HW_BTRS_LNL_VPU_TELEMETRY_OFFSET 0x00000168u | |
| 98 | +#define VPU_HW_BTRS_LNL_VPU_TELEMETRY_SIZE 0x0000016cu | |
| 99 | +#define VPU_HW_BTRS_LNL_VPU_TELEMETRY_ENABLE 0x00000170u | |
| 100 | + | |
| 101 | +#define VPU_HW_BTRS_LNL_FMIN_FUSE 0x00000174u | |
| 102 | +#define VPU_HW_BTRS_LNL_FMIN_FUSE_MIN_RATIO_MASK GENMASK(7, 0) | |
| 103 | +#define VPU_HW_BTRS_LNL_FMIN_FUSE_PN_RATIO_MASK GENMASK(15, 8) | |
| 104 | + | |
| 105 | +#define VPU_HW_BTRS_LNL_FMAX_FUSE 0x00000178u | |
| 106 | +#define VPU_HW_BTRS_LNL_FMAX_FUSE_MAX_RATIO_MASK GENMASK(7, 0) | |
| 107 | + | |
| 108 | +#endif /* __IVPU_HW_BTRS_LNL_REG_H__ */ | |
| @@ -0,0 +1,83 @@ | ||
| 1 | +/* SPDX-License-Identifier: GPL-2.0-only */ | |
| 2 | +/* | |
| 3 | + * Copyright (C) 2020-2023 Intel Corporation | |
| 4 | + */ | |
| 5 | + | |
| 6 | +#ifndef __IVPU_HW_BTRS_MTL_REG_H__ | |
| 7 | +#define __IVPU_HW_BTRS_MTL_REG_H__ | |
| 8 | + | |
| 9 | +#include <linux/bits.h> | |
| 10 | + | |
| 11 | +#define VPU_HW_BTRS_MTL_INTERRUPT_TYPE 0x00000000u | |
| 12 | + | |
| 13 | +#define VPU_HW_BTRS_MTL_INTERRUPT_STAT 0x00000004u | |
| 14 | +#define VPU_HW_BTRS_MTL_INTERRUPT_STAT_FREQ_CHANGE_MASK BIT_MASK(0) | |
| 15 | +#define VPU_HW_BTRS_MTL_INTERRUPT_STAT_ATS_ERR_MASK BIT_MASK(1) | |
| 16 | +#define VPU_HW_BTRS_MTL_INTERRUPT_STAT_UFI_ERR_MASK BIT_MASK(2) | |
| 17 | + | |
| 18 | +#define VPU_HW_BTRS_MTL_WP_REQ_PAYLOAD0 0x00000008u | |
| 19 | +#define VPU_HW_BTRS_MTL_WP_REQ_PAYLOAD0_MIN_RATIO_MASK GENMASK(15, 0) | |
| 20 | +#define VPU_HW_BTRS_MTL_WP_REQ_PAYLOAD0_MAX_RATIO_MASK GENMASK(31, 16) | |
| 21 | + | |
| 22 | +#define VPU_HW_BTRS_MTL_WP_REQ_PAYLOAD1 0x0000000cu | |
| 23 | +#define VPU_HW_BTRS_MTL_WP_REQ_PAYLOAD1_TARGET_RATIO_MASK GENMASK(15, 0) | |
| 24 | +#define VPU_HW_BTRS_MTL_WP_REQ_PAYLOAD1_EPP_MASK GENMASK(31, 16) | |
| 25 | + | |
| 26 | +#define VPU_HW_BTRS_MTL_WP_REQ_PAYLOAD2 0x00000010u | |
| 27 | +#define VPU_HW_BTRS_MTL_WP_REQ_PAYLOAD2_CONFIG_MASK GENMASK(15, 0) | |
| 28 | + | |
| 29 | +#define VPU_HW_BTRS_MTL_WP_REQ_CMD 0x00000014u | |
| 30 | +#define VPU_HW_BTRS_MTL_WP_REQ_CMD_SEND_MASK BIT_MASK(0) | |
| 31 | + | |
| 32 | +#define VPU_HW_BTRS_MTL_WP_DOWNLOAD 0x00000018u | |
| 33 | +#define VPU_HW_BTRS_MTL_WP_DOWNLOAD_TARGET_RATIO_MASK GENMASK(15, 0) | |
| 34 | + | |
| 35 | +#define VPU_HW_BTRS_MTL_CURRENT_PLL 0x0000001cu | |
| 36 | +#define VPU_HW_BTRS_MTL_CURRENT_PLL_RATIO_MASK GENMASK(15, 0) | |
| 37 | + | |
| 38 | +#define VPU_HW_BTRS_MTL_PLL_ENABLE 0x00000020u | |
| 39 | + | |
| 40 | +#define VPU_HW_BTRS_MTL_FMIN_FUSE 0x00000024u | |
| 41 | +#define VPU_HW_BTRS_MTL_FMIN_FUSE_MIN_RATIO_MASK GENMASK(7, 0) | |
| 42 | +#define VPU_HW_BTRS_MTL_FMIN_FUSE_PN_RATIO_MASK GENMASK(15, 8) | |
| 43 | + | |
| 44 | +#define VPU_HW_BTRS_MTL_FMAX_FUSE 0x00000028u | |
| 45 | +#define VPU_HW_BTRS_MTL_FMAX_FUSE_MAX_RATIO_MASK GENMASK(7, 0) | |
| 46 | + | |
| 47 | +#define VPU_HW_BTRS_MTL_TILE_FUSE 0x0000002cu | |
| 48 | +#define VPU_HW_BTRS_MTL_TILE_FUSE_VALID_MASK BIT_MASK(0) | |
| 49 | +#define VPU_HW_BTRS_MTL_TILE_FUSE_SKU_MASK GENMASK(3, 2) | |
| 50 | + | |
| 51 | +#define VPU_HW_BTRS_MTL_LOCAL_INT_MASK 0x00000030u | |
| 52 | +#define VPU_HW_BTRS_MTL_GLOBAL_INT_MASK 0x00000034u | |
| 53 | + | |
| 54 | +#define VPU_HW_BTRS_MTL_PLL_STATUS 0x00000040u | |
| 55 | +#define VPU_HW_BTRS_MTL_PLL_STATUS_LOCK_MASK BIT_MASK(1) | |
| 56 | + | |
| 57 | +#define VPU_HW_BTRS_MTL_VPU_STATUS 0x00000044u | |
| 58 | +#define VPU_HW_BTRS_MTL_VPU_STATUS_READY_MASK BIT_MASK(0) | |
| 59 | +#define VPU_HW_BTRS_MTL_VPU_STATUS_IDLE_MASK BIT_MASK(1) | |
| 60 | + | |
| 61 | +#define VPU_HW_BTRS_MTL_VPU_D0I3_CONTROL 0x00000060u | |
| 62 | +#define VPU_HW_BTRS_MTL_VPU_D0I3_CONTROL_INPROGRESS_MASK BIT_MASK(0) | |
| 63 | +#define VPU_HW_BTRS_MTL_VPU_D0I3_CONTROL_I3_MASK BIT_MASK(2) | |
| 64 | + | |
| 65 | +#define VPU_HW_BTRS_MTL_VPU_IP_RESET 0x00000050u | |
| 66 | +#define VPU_HW_BTRS_MTL_VPU_IP_RESET_TRIGGER_MASK BIT_MASK(0) | |
| 67 | + | |
| 68 | +#define VPU_HW_BTRS_MTL_VPU_TELEMETRY_OFFSET 0x00000080u | |
| 69 | +#define VPU_HW_BTRS_MTL_VPU_TELEMETRY_SIZE 0x00000084u | |
| 70 | +#define VPU_HW_BTRS_MTL_VPU_TELEMETRY_ENABLE 0x00000088u | |
| 71 | + | |
| 72 | +#define VPU_HW_BTRS_MTL_ATS_ERR_LOG_0 0x000000a0u | |
| 73 | +#define VPU_HW_BTRS_MTL_ATS_ERR_LOG_1 0x000000a4u | |
| 74 | +#define VPU_HW_BTRS_MTL_ATS_ERR_CLEAR 0x000000a8u | |
| 75 | + | |
| 76 | +#define VPU_HW_BTRS_MTL_UFI_ERR_LOG 0x000000b0u | |
| 77 | +#define VPU_HW_BTRS_MTL_UFI_ERR_LOG_CQ_ID_MASK GENMASK(11, 0) | |
| 78 | +#define VPU_HW_BTRS_MTL_UFI_ERR_LOG_AXI_ID_MASK GENMASK(19, 12) | |
| 79 | +#define VPU_HW_BTRS_MTL_UFI_ERR_LOG_OPCODE_MASK GENMASK(24, 20) | |
| 80 | + | |
| 81 | +#define VPU_HW_BTRS_MTL_UFI_ERR_CLEAR 0x000000b4u | |
| 82 | + | |
| 83 | +#endif /* __IVPU_HW_BTRS_MTL_REG_H__ */ | |
| @@ -0,0 +1,1174 @@ | ||
| 1 | +// SPDX-License-Identifier: GPL-2.0-only | |
| 2 | +/* | |
| 3 | + * Copyright (C) 2020-2024 Intel Corporation | |
| 4 | + */ | |
| 5 | + | |
| 6 | +#include "ivpu_drv.h" | |
| 7 | +#include "ivpu_fw.h" | |
| 8 | +#include "ivpu_hw.h" | |
| 9 | +#include "ivpu_hw_37xx_reg.h" | |
| 10 | +#include "ivpu_hw_40xx_reg.h" | |
| 11 | +#include "ivpu_hw_ip.h" | |
| 12 | +#include "ivpu_hw_reg_io.h" | |
| 13 | +#include "ivpu_mmu.h" | |
| 14 | +#include "ivpu_pm.h" | |
| 15 | + | |
| 16 | +#define PWR_ISLAND_EN_POST_DLY_FREQ_DEFAULT 0 | |
| 17 | +#define PWR_ISLAND_EN_POST_DLY_FREQ_HIGH 18 | |
| 18 | +#define PWR_ISLAND_STATUS_DLY_FREQ_DEFAULT 3 | |
| 19 | +#define PWR_ISLAND_STATUS_DLY_FREQ_HIGH 46 | |
| 20 | +#define PWR_ISLAND_STATUS_TIMEOUT_US (5 * USEC_PER_MSEC) | |
| 21 | + | |
| 22 | +#define TIM_SAFE_ENABLE 0xf1d0dead | |
| 23 | +#define TIM_WATCHDOG_RESET_VALUE 0xffffffff | |
| 24 | + | |
| 25 | +#define ICB_0_IRQ_MASK_37XX ((REG_FLD(VPU_37XX_HOST_SS_ICB_STATUS_0, HOST_IPC_FIFO_INT)) | \ | |
| 26 | + (REG_FLD(VPU_37XX_HOST_SS_ICB_STATUS_0, MMU_IRQ_0_INT)) | \ | |
| 27 | + (REG_FLD(VPU_37XX_HOST_SS_ICB_STATUS_0, MMU_IRQ_1_INT)) | \ | |
| 28 | + (REG_FLD(VPU_37XX_HOST_SS_ICB_STATUS_0, MMU_IRQ_2_INT)) | \ | |
| 29 | + (REG_FLD(VPU_37XX_HOST_SS_ICB_STATUS_0, NOC_FIREWALL_INT)) | \ | |
| 30 | + (REG_FLD(VPU_37XX_HOST_SS_ICB_STATUS_0, CPU_INT_REDIRECT_0_INT)) | \ | |
| 31 | + (REG_FLD(VPU_37XX_HOST_SS_ICB_STATUS_0, CPU_INT_REDIRECT_1_INT))) | |
| 32 | + | |
| 33 | +#define ICB_1_IRQ_MASK_37XX ((REG_FLD(VPU_37XX_HOST_SS_ICB_STATUS_1, CPU_INT_REDIRECT_2_INT)) | \ | |
| 34 | + (REG_FLD(VPU_37XX_HOST_SS_ICB_STATUS_1, CPU_INT_REDIRECT_3_INT)) | \ | |
| 35 | + (REG_FLD(VPU_37XX_HOST_SS_ICB_STATUS_1, CPU_INT_REDIRECT_4_INT))) | |
| 36 | + | |
| 37 | +#define ICB_0_1_IRQ_MASK_37XX ((((u64)ICB_1_IRQ_MASK_37XX) << 32) | ICB_0_IRQ_MASK_37XX) | |
| 38 | + | |
| 39 | +#define ICB_0_IRQ_MASK_40XX ((REG_FLD(VPU_40XX_HOST_SS_ICB_STATUS_0, HOST_IPC_FIFO_INT)) | \ | |
| 40 | + (REG_FLD(VPU_40XX_HOST_SS_ICB_STATUS_0, MMU_IRQ_0_INT)) | \ | |
| 41 | + (REG_FLD(VPU_40XX_HOST_SS_ICB_STATUS_0, MMU_IRQ_1_INT)) | \ | |
| 42 | + (REG_FLD(VPU_40XX_HOST_SS_ICB_STATUS_0, MMU_IRQ_2_INT)) | \ | |
| 43 | + (REG_FLD(VPU_40XX_HOST_SS_ICB_STATUS_0, NOC_FIREWALL_INT)) | \ | |
| 44 | + (REG_FLD(VPU_40XX_HOST_SS_ICB_STATUS_0, CPU_INT_REDIRECT_0_INT)) | \ | |
| 45 | + (REG_FLD(VPU_40XX_HOST_SS_ICB_STATUS_0, CPU_INT_REDIRECT_1_INT))) | |
| 46 | + | |
| 47 | +#define ICB_1_IRQ_MASK_40XX ((REG_FLD(VPU_40XX_HOST_SS_ICB_STATUS_1, CPU_INT_REDIRECT_2_INT)) | \ | |
| 48 | + (REG_FLD(VPU_40XX_HOST_SS_ICB_STATUS_1, CPU_INT_REDIRECT_3_INT)) | \ | |
| 49 | + (REG_FLD(VPU_40XX_HOST_SS_ICB_STATUS_1, CPU_INT_REDIRECT_4_INT))) | |
| 50 | + | |
| 51 | +#define ICB_0_1_IRQ_MASK_40XX ((((u64)ICB_1_IRQ_MASK_40XX) << 32) | ICB_0_IRQ_MASK_40XX) | |
| 52 | + | |
| 53 | +#define ITF_FIREWALL_VIOLATION_MASK_37XX ((REG_FLD(VPU_37XX_HOST_SS_FW_SOC_IRQ_EN, CSS_ROM_CMX)) | \ | |
| 54 | + (REG_FLD(VPU_37XX_HOST_SS_FW_SOC_IRQ_EN, CSS_DBG)) | \ | |
| 55 | + (REG_FLD(VPU_37XX_HOST_SS_FW_SOC_IRQ_EN, CSS_CTRL)) | \ | |
| 56 | + (REG_FLD(VPU_37XX_HOST_SS_FW_SOC_IRQ_EN, DEC400)) | \ | |
| 57 | + (REG_FLD(VPU_37XX_HOST_SS_FW_SOC_IRQ_EN, MSS_NCE)) | \ | |
| 58 | + (REG_FLD(VPU_37XX_HOST_SS_FW_SOC_IRQ_EN, MSS_MBI)) | \ | |
| 59 | + (REG_FLD(VPU_37XX_HOST_SS_FW_SOC_IRQ_EN, MSS_MBI_CMX))) | |
| 60 | + | |
| 61 | +#define ITF_FIREWALL_VIOLATION_MASK_40XX ((REG_FLD(VPU_40XX_HOST_SS_FW_SOC_IRQ_EN, CSS_ROM_CMX)) | \ | |
| 62 | + (REG_FLD(VPU_40XX_HOST_SS_FW_SOC_IRQ_EN, CSS_DBG)) | \ | |
| 63 | + (REG_FLD(VPU_40XX_HOST_SS_FW_SOC_IRQ_EN, CSS_CTRL)) | \ | |
| 64 | + (REG_FLD(VPU_40XX_HOST_SS_FW_SOC_IRQ_EN, DEC400)) | \ | |
| 65 | + (REG_FLD(VPU_40XX_HOST_SS_FW_SOC_IRQ_EN, MSS_NCE)) | \ | |
| 66 | + (REG_FLD(VPU_40XX_HOST_SS_FW_SOC_IRQ_EN, MSS_MBI)) | \ | |
| 67 | + (REG_FLD(VPU_40XX_HOST_SS_FW_SOC_IRQ_EN, MSS_MBI_CMX))) | |
| 68 | + | |
| 69 | +static int wait_for_ip_bar(struct ivpu_device *vdev) | |
| 70 | +{ | |
| 71 | + return REGV_POLL_FLD(VPU_37XX_HOST_SS_CPR_RST_CLR, AON, 0, 100); | |
| 72 | +} | |
| 73 | + | |
| 74 | +static void host_ss_rst_clr(struct ivpu_device *vdev) | |
| 75 | +{ | |
| 76 | + u32 val = 0; | |
| 77 | + | |
| 78 | + val = REG_SET_FLD(VPU_37XX_HOST_SS_CPR_RST_CLR, TOP_NOC, val); | |
| 79 | + val = REG_SET_FLD(VPU_37XX_HOST_SS_CPR_RST_CLR, DSS_MAS, val); | |
| 80 | + val = REG_SET_FLD(VPU_37XX_HOST_SS_CPR_RST_CLR, MSS_MAS, val); | |
| 81 | + | |
| 82 | + REGV_WR32(VPU_37XX_HOST_SS_CPR_RST_CLR, val); | |
| 83 | +} | |
| 84 | + | |
| 85 | +static int host_ss_noc_qreqn_check_37xx(struct ivpu_device *vdev, u32 exp_val) | |
| 86 | +{ | |
| 87 | + u32 val = REGV_RD32(VPU_37XX_HOST_SS_NOC_QREQN); | |
| 88 | + | |
| 89 | + if (!REG_TEST_FLD_NUM(VPU_37XX_HOST_SS_NOC_QREQN, TOP_SOCMMIO, exp_val, val)) | |
| 90 | + return -EIO; | |
| 91 | + | |
| 92 | + return 0; | |
| 93 | +} | |
| 94 | + | |
| 95 | +static int host_ss_noc_qreqn_check_40xx(struct ivpu_device *vdev, u32 exp_val) | |
| 96 | +{ | |
| 97 | + u32 val = REGV_RD32(VPU_40XX_HOST_SS_NOC_QREQN); | |
| 98 | + | |
| 99 | + if (!REG_TEST_FLD_NUM(VPU_40XX_HOST_SS_NOC_QREQN, TOP_SOCMMIO, exp_val, val)) | |
| 100 | + return -EIO; | |
| 101 | + | |
| 102 | + return 0; | |
| 103 | +} | |
| 104 | + | |
| 105 | +static int host_ss_noc_qreqn_check(struct ivpu_device *vdev, u32 exp_val) | |
| 106 | +{ | |
| 107 | + if (ivpu_hw_ip_gen(vdev) == IVPU_HW_IP_37XX) | |
| 108 | + return host_ss_noc_qreqn_check_37xx(vdev, exp_val); | |
| 109 | + else | |
| 110 | + return host_ss_noc_qreqn_check_40xx(vdev, exp_val); | |
| 111 | +} | |
| 112 | + | |
| 113 | +static int host_ss_noc_qacceptn_check_37xx(struct ivpu_device *vdev, u32 exp_val) | |
| 114 | +{ | |
| 115 | + u32 val = REGV_RD32(VPU_37XX_HOST_SS_NOC_QACCEPTN); | |
| 116 | + | |
| 117 | + if (!REG_TEST_FLD_NUM(VPU_37XX_HOST_SS_NOC_QACCEPTN, TOP_SOCMMIO, exp_val, val)) | |
| 118 | + return -EIO; | |
| 119 | + | |
| 120 | + return 0; | |
| 121 | +} | |
| 122 | + | |
| 123 | +static int host_ss_noc_qacceptn_check_40xx(struct ivpu_device *vdev, u32 exp_val) | |
| 124 | +{ | |
| 125 | + u32 val = REGV_RD32(VPU_40XX_HOST_SS_NOC_QACCEPTN); | |
| 126 | + | |
| 127 | + if (!REG_TEST_FLD_NUM(VPU_40XX_HOST_SS_NOC_QACCEPTN, TOP_SOCMMIO, exp_val, val)) | |
| 128 | + return -EIO; | |
| 129 | + | |
| 130 | + return 0; | |
| 131 | +} | |
| 132 | + | |
| 133 | +static int host_ss_noc_qacceptn_check(struct ivpu_device *vdev, u32 exp_val) | |
| 134 | +{ | |
| 135 | + if (ivpu_hw_ip_gen(vdev) == IVPU_HW_IP_37XX) | |
| 136 | + return host_ss_noc_qacceptn_check_37xx(vdev, exp_val); | |
| 137 | + else | |
| 138 | + return host_ss_noc_qacceptn_check_40xx(vdev, exp_val); | |
| 139 | +} | |
| 140 | + | |
| 141 | +static int host_ss_noc_qdeny_check_37xx(struct ivpu_device *vdev, u32 exp_val) | |
| 142 | +{ | |
| 143 | + u32 val = REGV_RD32(VPU_37XX_HOST_SS_NOC_QDENY); | |
| 144 | + | |
| 145 | + if (!REG_TEST_FLD_NUM(VPU_37XX_HOST_SS_NOC_QDENY, TOP_SOCMMIO, exp_val, val)) | |
| 146 | + return -EIO; | |
| 147 | + | |
| 148 | + return 0; | |
| 149 | +} | |
| 150 | + | |
| 151 | +static int host_ss_noc_qdeny_check_40xx(struct ivpu_device *vdev, u32 exp_val) | |
| 152 | +{ | |
| 153 | + u32 val = REGV_RD32(VPU_40XX_HOST_SS_NOC_QDENY); | |
| 154 | + | |
| 155 | + if (!REG_TEST_FLD_NUM(VPU_40XX_HOST_SS_NOC_QDENY, TOP_SOCMMIO, exp_val, val)) | |
| 156 | + return -EIO; | |
| 157 | + | |
| 158 | + return 0; | |
| 159 | +} | |
| 160 | + | |
| 161 | +static int host_ss_noc_qdeny_check(struct ivpu_device *vdev, u32 exp_val) | |
| 162 | +{ | |
| 163 | + if (ivpu_hw_ip_gen(vdev) == IVPU_HW_IP_37XX) | |
| 164 | + return host_ss_noc_qdeny_check_37xx(vdev, exp_val); | |
| 165 | + else | |
| 166 | + return host_ss_noc_qdeny_check_40xx(vdev, exp_val); | |
| 167 | +} | |
| 168 | + | |
| 169 | +static int top_noc_qrenqn_check_37xx(struct ivpu_device *vdev, u32 exp_val) | |
| 170 | +{ | |
| 171 | + u32 val = REGV_RD32(VPU_37XX_TOP_NOC_QREQN); | |
| 172 | + | |
| 173 | + if (!REG_TEST_FLD_NUM(VPU_37XX_TOP_NOC_QREQN, CPU_CTRL, exp_val, val) || | |
| 174 | + !REG_TEST_FLD_NUM(VPU_37XX_TOP_NOC_QREQN, HOSTIF_L2CACHE, exp_val, val)) | |
| 175 | + return -EIO; | |
| 176 | + | |
| 177 | + return 0; | |
| 178 | +} | |
| 179 | + | |
| 180 | +static int top_noc_qrenqn_check_40xx(struct ivpu_device *vdev, u32 exp_val) | |
| 181 | +{ | |
| 182 | + u32 val = REGV_RD32(VPU_40XX_TOP_NOC_QREQN); | |
| 183 | + | |
| 184 | + if (!REG_TEST_FLD_NUM(VPU_40XX_TOP_NOC_QREQN, CPU_CTRL, exp_val, val) || | |
| 185 | + !REG_TEST_FLD_NUM(VPU_40XX_TOP_NOC_QREQN, HOSTIF_L2CACHE, exp_val, val)) | |
| 186 | + return -EIO; | |
| 187 | + | |
| 188 | + return 0; | |
| 189 | +} | |
| 190 | + | |
| 191 | +static int top_noc_qreqn_check(struct ivpu_device *vdev, u32 exp_val) | |
| 192 | +{ | |
| 193 | + if (ivpu_hw_ip_gen(vdev) == IVPU_HW_IP_37XX) | |
| 194 | + return top_noc_qrenqn_check_37xx(vdev, exp_val); | |
| 195 | + else | |
| 196 | + return top_noc_qrenqn_check_40xx(vdev, exp_val); | |
| 197 | +} | |
| 198 | + | |
| 199 | +int ivpu_hw_ip_host_ss_configure(struct ivpu_device *vdev) | |
| 200 | +{ | |
| 201 | + int ret; | |
| 202 | + | |
| 203 | + if (ivpu_hw_ip_gen(vdev) == IVPU_HW_IP_37XX) { | |
| 204 | + ret = wait_for_ip_bar(vdev); | |
| 205 | + if (ret) { | |
| 206 | + ivpu_err(vdev, "Timed out waiting for NPU IP bar\n"); | |
| 207 | + return ret; | |
| 208 | + } | |
| 209 | + host_ss_rst_clr(vdev); | |
| 210 | + } | |
| 211 | + | |
| 212 | + ret = host_ss_noc_qreqn_check(vdev, 0x0); | |
| 213 | + if (ret) { | |
| 214 | + ivpu_err(vdev, "Failed qreqn check: %d\n", ret); | |
| 215 | + return ret; | |
| 216 | + } | |
| 217 | + | |
| 218 | + ret = host_ss_noc_qacceptn_check(vdev, 0x0); | |
| 219 | + if (ret) { | |
| 220 | + ivpu_err(vdev, "Failed qacceptn check: %d\n", ret); | |
| 221 | + return ret; | |
| 222 | + } | |
| 223 | + | |
| 224 | + ret = host_ss_noc_qdeny_check(vdev, 0x0); | |
| 225 | + if (ret) | |
| 226 | + ivpu_err(vdev, "Failed qdeny check %d\n", ret); | |
| 227 | + | |
| 228 | + return ret; | |
| 229 | +} | |
| 230 | + | |
| 231 | +static void idle_gen_drive_37xx(struct ivpu_device *vdev, bool enable) | |
| 232 | +{ | |
| 233 | + u32 val = REGV_RD32(VPU_37XX_HOST_SS_AON_VPU_IDLE_GEN); | |
| 234 | + | |
| 235 | + if (enable) | |
| 236 | + val = REG_SET_FLD(VPU_37XX_HOST_SS_AON_VPU_IDLE_GEN, EN, val); | |
| 237 | + else | |
| 238 | + val = REG_CLR_FLD(VPU_37XX_HOST_SS_AON_VPU_IDLE_GEN, EN, val); | |
| 239 | + | |
| 240 | + REGV_WR32(VPU_37XX_HOST_SS_AON_VPU_IDLE_GEN, val); | |
| 241 | +} | |
| 242 | + | |
| 243 | +static void idle_gen_drive_40xx(struct ivpu_device *vdev, bool enable) | |
| 244 | +{ | |
| 245 | + u32 val = REGV_RD32(VPU_40XX_HOST_SS_AON_IDLE_GEN); | |
| 246 | + | |
| 247 | + if (enable) | |
| 248 | + val = REG_SET_FLD(VPU_40XX_HOST_SS_AON_IDLE_GEN, EN, val); | |
| 249 | + else | |
| 250 | + val = REG_CLR_FLD(VPU_40XX_HOST_SS_AON_IDLE_GEN, EN, val); | |
| 251 | + | |
| 252 | + REGV_WR32(VPU_40XX_HOST_SS_AON_IDLE_GEN, val); | |
| 253 | +} | |
| 254 | + | |
| 255 | +void ivpu_hw_ip_idle_gen_enable(struct ivpu_device *vdev) | |
| 256 | +{ | |
| 257 | + if (ivpu_hw_ip_gen(vdev) == IVPU_HW_IP_37XX) | |
| 258 | + idle_gen_drive_37xx(vdev, true); | |
| 259 | + else | |
| 260 | + idle_gen_drive_40xx(vdev, true); | |
| 261 | +} | |
| 262 | + | |
| 263 | +void ivpu_hw_ip_idle_gen_disable(struct ivpu_device *vdev) | |
| 264 | +{ | |
| 265 | + if (ivpu_hw_ip_gen(vdev) == IVPU_HW_IP_37XX) | |
| 266 | + idle_gen_drive_37xx(vdev, false); | |
| 267 | + else | |
| 268 | + idle_gen_drive_40xx(vdev, false); | |
| 269 | +} | |
| 270 | + | |
| 271 | +static void pwr_island_delay_set_50xx(struct ivpu_device *vdev) | |
| 272 | +{ | |
| 273 | + u32 val, post, status; | |
| 274 | + | |
| 275 | + if (vdev->hw->pll.profiling_freq == PLL_PROFILING_FREQ_DEFAULT) { | |
| 276 | + post = PWR_ISLAND_EN_POST_DLY_FREQ_DEFAULT; | |
| 277 | + status = PWR_ISLAND_STATUS_DLY_FREQ_DEFAULT; | |
| 278 | + } else { | |
| 279 | + post = PWR_ISLAND_EN_POST_DLY_FREQ_HIGH; | |
| 280 | + status = PWR_ISLAND_STATUS_DLY_FREQ_HIGH; | |
| 281 | + } | |
| 282 | + | |
| 283 | + val = REGV_RD32(VPU_50XX_HOST_SS_AON_PWR_ISLAND_EN_POST_DLY); | |
| 284 | + val = REG_SET_FLD_NUM(VPU_50XX_HOST_SS_AON_PWR_ISLAND_EN_POST_DLY, POST_DLY, post, val); | |
| 285 | + REGV_WR32(VPU_50XX_HOST_SS_AON_PWR_ISLAND_EN_POST_DLY, val); | |
| 286 | + | |
| 287 | + val = REGV_RD32(VPU_50XX_HOST_SS_AON_PWR_ISLAND_STATUS_DLY); | |
| 288 | + val = REG_SET_FLD_NUM(VPU_50XX_HOST_SS_AON_PWR_ISLAND_STATUS_DLY, STATUS_DLY, status, val); | |
| 289 | + REGV_WR32(VPU_50XX_HOST_SS_AON_PWR_ISLAND_STATUS_DLY, val); | |
| 290 | +} | |
| 291 | + | |
| 292 | +static void pwr_island_trickle_drive_37xx(struct ivpu_device *vdev, bool enable) | |
| 293 | +{ | |
| 294 | + u32 val = REGV_RD32(VPU_37XX_HOST_SS_AON_PWR_ISLAND_TRICKLE_EN0); | |
| 295 | + | |
| 296 | + if (enable) | |
| 297 | + val = REG_SET_FLD(VPU_37XX_HOST_SS_AON_PWR_ISLAND_TRICKLE_EN0, MSS_CPU, val); | |
| 298 | + else | |
| 299 | + val = REG_CLR_FLD(VPU_37XX_HOST_SS_AON_PWR_ISLAND_TRICKLE_EN0, MSS_CPU, val); | |
| 300 | + | |
| 301 | + REGV_WR32(VPU_37XX_HOST_SS_AON_PWR_ISLAND_TRICKLE_EN0, val); | |
| 302 | +} | |
| 303 | + | |
| 304 | +static void pwr_island_trickle_drive_40xx(struct ivpu_device *vdev, bool enable) | |
| 305 | +{ | |
| 306 | + u32 val = REGV_RD32(VPU_40XX_HOST_SS_AON_PWR_ISLAND_TRICKLE_EN0); | |
| 307 | + | |
| 308 | + if (enable) | |
| 309 | + val = REG_SET_FLD(VPU_40XX_HOST_SS_AON_PWR_ISLAND_TRICKLE_EN0, CSS_CPU, val); | |
| 310 | + else | |
| 311 | + val = REG_CLR_FLD(VPU_40XX_HOST_SS_AON_PWR_ISLAND_TRICKLE_EN0, CSS_CPU, val); | |
| 312 | + | |
| 313 | + REGV_WR32(VPU_40XX_HOST_SS_AON_PWR_ISLAND_TRICKLE_EN0, val); | |
| 314 | + | |
| 315 | + if (enable) | |
| 316 | + ndelay(500); | |
| 317 | +} | |
| 318 | + | |
| 319 | +static void pwr_island_drive_37xx(struct ivpu_device *vdev, bool enable) | |
| 320 | +{ | |
| 321 | + u32 val = REGV_RD32(VPU_40XX_HOST_SS_AON_PWR_ISLAND_EN0); | |
| 322 | + | |
| 323 | + if (enable) | |
| 324 | + val = REG_SET_FLD(VPU_40XX_HOST_SS_AON_PWR_ISLAND_EN0, CSS_CPU, val); | |
| 325 | + else | |
| 326 | + val = REG_CLR_FLD(VPU_40XX_HOST_SS_AON_PWR_ISLAND_EN0, CSS_CPU, val); | |
| 327 | + | |
| 328 | + REGV_WR32(VPU_40XX_HOST_SS_AON_PWR_ISLAND_EN0, val); | |
| 329 | + | |
| 330 | + if (!enable) | |
| 331 | + ndelay(500); | |
| 332 | +} | |
| 333 | + | |
| 334 | +static void pwr_island_drive_40xx(struct ivpu_device *vdev, bool enable) | |
| 335 | +{ | |
| 336 | + u32 val = REGV_RD32(VPU_37XX_HOST_SS_AON_PWR_ISLAND_EN0); | |
| 337 | + | |
| 338 | + if (enable) | |
| 339 | + val = REG_SET_FLD(VPU_37XX_HOST_SS_AON_PWR_ISLAND_EN0, MSS_CPU, val); | |
| 340 | + else | |
| 341 | + val = REG_CLR_FLD(VPU_37XX_HOST_SS_AON_PWR_ISLAND_EN0, MSS_CPU, val); | |
| 342 | + | |
| 343 | + REGV_WR32(VPU_37XX_HOST_SS_AON_PWR_ISLAND_EN0, val); | |
| 344 | +} | |
| 345 | + | |
| 346 | +static void pwr_island_enable(struct ivpu_device *vdev) | |
| 347 | +{ | |
| 348 | + if (ivpu_hw_ip_gen(vdev) == IVPU_HW_IP_37XX) { | |
| 349 | + pwr_island_trickle_drive_37xx(vdev, true); | |
| 350 | + pwr_island_drive_37xx(vdev, true); | |
| 351 | + } else { | |
| 352 | + pwr_island_trickle_drive_40xx(vdev, true); | |
| 353 | + pwr_island_drive_40xx(vdev, true); | |
| 354 | + } | |
| 355 | +} | |
| 356 | + | |
| 357 | +static int wait_for_pwr_island_status(struct ivpu_device *vdev, u32 exp_val) | |
| 358 | +{ | |
| 359 | + if (IVPU_WA(punit_disabled)) | |
| 360 | + return 0; | |
| 361 | + | |
| 362 | + if (ivpu_hw_ip_gen(vdev) == IVPU_HW_IP_37XX) | |
| 363 | + return REGV_POLL_FLD(VPU_37XX_HOST_SS_AON_PWR_ISLAND_STATUS0, MSS_CPU, exp_val, | |
| 364 | + PWR_ISLAND_STATUS_TIMEOUT_US); | |
| 365 | + else | |
| 366 | + return REGV_POLL_FLD(VPU_40XX_HOST_SS_AON_PWR_ISLAND_STATUS0, CSS_CPU, exp_val, | |
| 367 | + PWR_ISLAND_STATUS_TIMEOUT_US); | |
| 368 | +} | |
| 369 | + | |
| 370 | +static void pwr_island_isolation_drive_37xx(struct ivpu_device *vdev, bool enable) | |
| 371 | +{ | |
| 372 | + u32 val = REGV_RD32(VPU_37XX_HOST_SS_AON_PWR_ISO_EN0); | |
| 373 | + | |
| 374 | + if (enable) | |
| 375 | + val = REG_SET_FLD(VPU_37XX_HOST_SS_AON_PWR_ISO_EN0, MSS_CPU, val); | |
| 376 | + else | |
| 377 | + val = REG_CLR_FLD(VPU_37XX_HOST_SS_AON_PWR_ISO_EN0, MSS_CPU, val); | |
| 378 | + | |
| 379 | + REGV_WR32(VPU_37XX_HOST_SS_AON_PWR_ISO_EN0, val); | |
| 380 | +} | |
| 381 | + | |
| 382 | +static void pwr_island_isolation_drive_40xx(struct ivpu_device *vdev, bool enable) | |
| 383 | +{ | |
| 384 | + u32 val = REGV_RD32(VPU_40XX_HOST_SS_AON_PWR_ISO_EN0); | |
| 385 | + | |
| 386 | + if (enable) | |
| 387 | + val = REG_SET_FLD(VPU_40XX_HOST_SS_AON_PWR_ISO_EN0, CSS_CPU, val); | |
| 388 | + else | |
| 389 | + val = REG_CLR_FLD(VPU_40XX_HOST_SS_AON_PWR_ISO_EN0, CSS_CPU, val); | |
| 390 | + | |
| 391 | + REGV_WR32(VPU_40XX_HOST_SS_AON_PWR_ISO_EN0, val); | |
| 392 | +} | |
| 393 | + | |
| 394 | +static void pwr_island_isolation_drive(struct ivpu_device *vdev, bool enable) | |
| 395 | +{ | |
| 396 | + if (ivpu_hw_ip_gen(vdev) == IVPU_HW_IP_37XX) | |
| 397 | + pwr_island_isolation_drive_37xx(vdev, enable); | |
| 398 | + else | |
| 399 | + pwr_island_isolation_drive_40xx(vdev, enable); | |
| 400 | +} | |
| 401 | + | |
| 402 | +static void pwr_island_isolation_disable(struct ivpu_device *vdev) | |
| 403 | +{ | |
| 404 | + pwr_island_isolation_drive(vdev, false); | |
| 405 | +} | |
| 406 | + | |
| 407 | +static void host_ss_clk_drive_37xx(struct ivpu_device *vdev, bool enable) | |
| 408 | +{ | |
| 409 | + u32 val = REGV_RD32(VPU_37XX_HOST_SS_CPR_CLK_SET); | |
| 410 | + | |
| 411 | + if (enable) { | |
| 412 | + val = REG_SET_FLD(VPU_37XX_HOST_SS_CPR_CLK_SET, TOP_NOC, val); | |
| 413 | + val = REG_SET_FLD(VPU_37XX_HOST_SS_CPR_CLK_SET, DSS_MAS, val); | |
| 414 | + val = REG_SET_FLD(VPU_37XX_HOST_SS_CPR_CLK_SET, MSS_MAS, val); | |
| 415 | + } else { | |
| 416 | + val = REG_CLR_FLD(VPU_37XX_HOST_SS_CPR_CLK_SET, TOP_NOC, val); | |
| 417 | + val = REG_CLR_FLD(VPU_37XX_HOST_SS_CPR_CLK_SET, DSS_MAS, val); | |
| 418 | + val = REG_CLR_FLD(VPU_37XX_HOST_SS_CPR_CLK_SET, MSS_MAS, val); | |
| 419 | + } | |
| 420 | + | |
| 421 | + REGV_WR32(VPU_37XX_HOST_SS_CPR_CLK_SET, val); | |
| 422 | +} | |
| 423 | + | |
| 424 | +static void host_ss_clk_drive_40xx(struct ivpu_device *vdev, bool enable) | |
| 425 | +{ | |
| 426 | + u32 val = REGV_RD32(VPU_40XX_HOST_SS_CPR_CLK_EN); | |
| 427 | + | |
| 428 | + if (enable) { | |
| 429 | + val = REG_SET_FLD(VPU_40XX_HOST_SS_CPR_CLK_EN, TOP_NOC, val); | |
| 430 | + val = REG_SET_FLD(VPU_40XX_HOST_SS_CPR_CLK_EN, DSS_MAS, val); | |
| 431 | + val = REG_SET_FLD(VPU_40XX_HOST_SS_CPR_CLK_EN, CSS_MAS, val); | |
| 432 | + } else { | |
| 433 | + val = REG_CLR_FLD(VPU_40XX_HOST_SS_CPR_CLK_EN, TOP_NOC, val); | |
| 434 | + val = REG_CLR_FLD(VPU_40XX_HOST_SS_CPR_CLK_EN, DSS_MAS, val); | |
| 435 | + val = REG_CLR_FLD(VPU_40XX_HOST_SS_CPR_CLK_EN, CSS_MAS, val); | |
| 436 | + } | |
| 437 | + | |
| 438 | + REGV_WR32(VPU_40XX_HOST_SS_CPR_CLK_EN, val); | |
| 439 | +} | |
| 440 | + | |
| 441 | +static void host_ss_clk_drive(struct ivpu_device *vdev, bool enable) | |
| 442 | +{ | |
| 443 | + if (ivpu_hw_ip_gen(vdev) == IVPU_HW_IP_37XX) | |
| 444 | + host_ss_clk_drive_37xx(vdev, enable); | |
| 445 | + else | |
| 446 | + host_ss_clk_drive_40xx(vdev, enable); | |
| 447 | +} | |
| 448 | + | |
| 449 | +static void host_ss_clk_enable(struct ivpu_device *vdev) | |
| 450 | +{ | |
| 451 | + host_ss_clk_drive(vdev, true); | |
| 452 | +} | |
| 453 | + | |
| 454 | +static void host_ss_rst_drive_37xx(struct ivpu_device *vdev, bool enable) | |
| 455 | +{ | |
| 456 | + u32 val = REGV_RD32(VPU_37XX_HOST_SS_CPR_RST_SET); | |
| 457 | + | |
| 458 | + if (enable) { | |
| 459 | + val = REG_SET_FLD(VPU_37XX_HOST_SS_CPR_RST_SET, TOP_NOC, val); | |
| 460 | + val = REG_SET_FLD(VPU_37XX_HOST_SS_CPR_RST_SET, DSS_MAS, val); | |
| 461 | + val = REG_SET_FLD(VPU_37XX_HOST_SS_CPR_RST_SET, MSS_MAS, val); | |
| 462 | + } else { | |
| 463 | + val = REG_CLR_FLD(VPU_37XX_HOST_SS_CPR_RST_SET, TOP_NOC, val); | |
| 464 | + val = REG_CLR_FLD(VPU_37XX_HOST_SS_CPR_RST_SET, DSS_MAS, val); | |
| 465 | + val = REG_CLR_FLD(VPU_37XX_HOST_SS_CPR_RST_SET, MSS_MAS, val); | |
| 466 | + } | |
| 467 | + | |
| 468 | + REGV_WR32(VPU_37XX_HOST_SS_CPR_RST_SET, val); | |
| 469 | +} | |
| 470 | + | |
| 471 | +static void host_ss_rst_drive_40xx(struct ivpu_device *vdev, bool enable) | |
| 472 | +{ | |
| 473 | + u32 val = REGV_RD32(VPU_40XX_HOST_SS_CPR_RST_EN); | |
| 474 | + | |
| 475 | + if (enable) { | |
| 476 | + val = REG_SET_FLD(VPU_40XX_HOST_SS_CPR_RST_EN, TOP_NOC, val); | |
| 477 | + val = REG_SET_FLD(VPU_40XX_HOST_SS_CPR_RST_EN, DSS_MAS, val); | |
| 478 | + val = REG_SET_FLD(VPU_40XX_HOST_SS_CPR_RST_EN, CSS_MAS, val); | |
| 479 | + } else { | |
| 480 | + val = REG_CLR_FLD(VPU_40XX_HOST_SS_CPR_RST_EN, TOP_NOC, val); | |
| 481 | + val = REG_CLR_FLD(VPU_40XX_HOST_SS_CPR_RST_EN, DSS_MAS, val); | |
| 482 | + val = REG_CLR_FLD(VPU_40XX_HOST_SS_CPR_RST_EN, CSS_MAS, val); | |
| 483 | + } | |
| 484 | + | |
| 485 | + REGV_WR32(VPU_40XX_HOST_SS_CPR_RST_EN, val); | |
| 486 | +} | |
| 487 | + | |
| 488 | +static void host_ss_rst_drive(struct ivpu_device *vdev, bool enable) | |
| 489 | +{ | |
| 490 | + if (ivpu_hw_ip_gen(vdev) == IVPU_HW_IP_37XX) | |
| 491 | + host_ss_rst_drive_37xx(vdev, enable); | |
| 492 | + else | |
| 493 | + host_ss_rst_drive_40xx(vdev, enable); | |
| 494 | +} | |
| 495 | + | |
| 496 | +static void host_ss_rst_enable(struct ivpu_device *vdev) | |
| 497 | +{ | |
| 498 | + host_ss_rst_drive(vdev, true); | |
| 499 | +} | |
| 500 | + | |
| 501 | +static void host_ss_noc_qreqn_top_socmmio_drive_37xx(struct ivpu_device *vdev, bool enable) | |
| 502 | +{ | |
| 503 | + u32 val = REGV_RD32(VPU_37XX_HOST_SS_NOC_QREQN); | |
| 504 | + | |
| 505 | + if (enable) | |
| 506 | + val = REG_SET_FLD(VPU_37XX_HOST_SS_NOC_QREQN, TOP_SOCMMIO, val); | |
| 507 | + else | |
| 508 | + val = REG_CLR_FLD(VPU_37XX_HOST_SS_NOC_QREQN, TOP_SOCMMIO, val); | |
| 509 | + REGV_WR32(VPU_37XX_HOST_SS_NOC_QREQN, val); | |
| 510 | +} | |
| 511 | + | |
| 512 | +static void host_ss_noc_qreqn_top_socmmio_drive_40xx(struct ivpu_device *vdev, bool enable) | |
| 513 | +{ | |
| 514 | + u32 val = REGV_RD32(VPU_40XX_HOST_SS_NOC_QREQN); | |
| 515 | + | |
| 516 | + if (enable) | |
| 517 | + val = REG_SET_FLD(VPU_40XX_HOST_SS_NOC_QREQN, TOP_SOCMMIO, val); | |
| 518 | + else | |
| 519 | + val = REG_CLR_FLD(VPU_40XX_HOST_SS_NOC_QREQN, TOP_SOCMMIO, val); | |
| 520 | + REGV_WR32(VPU_40XX_HOST_SS_NOC_QREQN, val); | |
| 521 | +} | |
| 522 | + | |
| 523 | +static void host_ss_noc_qreqn_top_socmmio_drive(struct ivpu_device *vdev, bool enable) | |
| 524 | +{ | |
| 525 | + if (ivpu_hw_ip_gen(vdev) == IVPU_HW_IP_37XX) | |
| 526 | + host_ss_noc_qreqn_top_socmmio_drive_37xx(vdev, enable); | |
| 527 | + else | |
| 528 | + host_ss_noc_qreqn_top_socmmio_drive_40xx(vdev, enable); | |
| 529 | +} | |
| 530 | + | |
| 531 | +static int host_ss_axi_drive(struct ivpu_device *vdev, bool enable) | |
| 532 | +{ | |
| 533 | + int ret; | |
| 534 | + | |
| 535 | + host_ss_noc_qreqn_top_socmmio_drive(vdev, enable); | |
| 536 | + | |
| 537 | + ret = host_ss_noc_qacceptn_check(vdev, enable ? 0x1 : 0x0); | |
| 538 | + if (ret) { | |
| 539 | + ivpu_err(vdev, "Failed HOST SS NOC QACCEPTN check: %d\n", ret); | |
| 540 | + return ret; | |
| 541 | + } | |
| 542 | + | |
| 543 | + ret = host_ss_noc_qdeny_check(vdev, 0x0); | |
| 544 | + if (ret) | |
| 545 | + ivpu_err(vdev, "Failed HOST SS NOC QDENY check: %d\n", ret); | |
| 546 | + | |
| 547 | + return ret; | |
| 548 | +} | |
| 549 | + | |
| 550 | +static void top_noc_qreqn_drive_40xx(struct ivpu_device *vdev, bool enable) | |
| 551 | +{ | |
| 552 | + u32 val = REGV_RD32(VPU_40XX_TOP_NOC_QREQN); | |
| 553 | + | |
| 554 | + if (enable) { | |
| 555 | + val = REG_SET_FLD(VPU_40XX_TOP_NOC_QREQN, CPU_CTRL, val); | |
| 556 | + val = REG_SET_FLD(VPU_40XX_TOP_NOC_QREQN, HOSTIF_L2CACHE, val); | |
| 557 | + } else { | |
| 558 | + val = REG_CLR_FLD(VPU_40XX_TOP_NOC_QREQN, CPU_CTRL, val); | |
| 559 | + val = REG_CLR_FLD(VPU_40XX_TOP_NOC_QREQN, HOSTIF_L2CACHE, val); | |
| 560 | + } | |
| 561 | + | |
| 562 | + REGV_WR32(VPU_40XX_TOP_NOC_QREQN, val); | |
| 563 | +} | |
| 564 | + | |
| 565 | +static void top_noc_qreqn_drive_37xx(struct ivpu_device *vdev, bool enable) | |
| 566 | +{ | |
| 567 | + u32 val = REGV_RD32(VPU_37XX_TOP_NOC_QREQN); | |
| 568 | + | |
| 569 | + if (enable) { | |
| 570 | + val = REG_SET_FLD(VPU_37XX_TOP_NOC_QREQN, CPU_CTRL, val); | |
| 571 | + val = REG_SET_FLD(VPU_37XX_TOP_NOC_QREQN, HOSTIF_L2CACHE, val); | |
| 572 | + } else { | |
| 573 | + val = REG_CLR_FLD(VPU_37XX_TOP_NOC_QREQN, CPU_CTRL, val); | |
| 574 | + val = REG_CLR_FLD(VPU_37XX_TOP_NOC_QREQN, HOSTIF_L2CACHE, val); | |
| 575 | + } | |
| 576 | + | |
| 577 | + REGV_WR32(VPU_37XX_TOP_NOC_QREQN, val); | |
| 578 | +} | |
| 579 | + | |
| 580 | +static void top_noc_qreqn_drive(struct ivpu_device *vdev, bool enable) | |
| 581 | +{ | |
| 582 | + if (ivpu_hw_ip_gen(vdev) == IVPU_HW_IP_37XX) | |
| 583 | + top_noc_qreqn_drive_37xx(vdev, enable); | |
| 584 | + else | |
| 585 | + top_noc_qreqn_drive_40xx(vdev, enable); | |
| 586 | +} | |
| 587 | + | |
| 588 | +int ivpu_hw_ip_host_ss_axi_enable(struct ivpu_device *vdev) | |
| 589 | +{ | |
| 590 | + return host_ss_axi_drive(vdev, true); | |
| 591 | +} | |
| 592 | + | |
| 593 | +static int top_noc_qacceptn_check_37xx(struct ivpu_device *vdev, u32 exp_val) | |
| 594 | +{ | |
| 595 | + u32 val = REGV_RD32(VPU_37XX_TOP_NOC_QACCEPTN); | |
| 596 | + | |
| 597 | + if (!REG_TEST_FLD_NUM(VPU_37XX_TOP_NOC_QACCEPTN, CPU_CTRL, exp_val, val) || | |
| 598 | + !REG_TEST_FLD_NUM(VPU_37XX_TOP_NOC_QACCEPTN, HOSTIF_L2CACHE, exp_val, val)) | |
| 599 | + return -EIO; | |
| 600 | + | |
| 601 | + return 0; | |
| 602 | +} | |
| 603 | + | |
| 604 | +static int top_noc_qacceptn_check_40xx(struct ivpu_device *vdev, u32 exp_val) | |
| 605 | +{ | |
| 606 | + u32 val = REGV_RD32(VPU_40XX_TOP_NOC_QACCEPTN); | |
| 607 | + | |
| 608 | + if (!REG_TEST_FLD_NUM(VPU_40XX_TOP_NOC_QACCEPTN, CPU_CTRL, exp_val, val) || | |
| 609 | + !REG_TEST_FLD_NUM(VPU_40XX_TOP_NOC_QACCEPTN, HOSTIF_L2CACHE, exp_val, val)) | |
| 610 | + return -EIO; | |
| 611 | + | |
| 612 | + return 0; | |
| 613 | +} | |
| 614 | + | |
| 615 | +static int top_noc_qacceptn_check(struct ivpu_device *vdev, u32 exp_val) | |
| 616 | +{ | |
| 617 | + if (ivpu_hw_ip_gen(vdev) == IVPU_HW_IP_37XX) | |
| 618 | + return top_noc_qacceptn_check_37xx(vdev, exp_val); | |
| 619 | + else | |
| 620 | + return top_noc_qacceptn_check_40xx(vdev, exp_val); | |
| 621 | +} | |
| 622 | + | |
| 623 | +static int top_noc_qdeny_check_37xx(struct ivpu_device *vdev, u32 exp_val) | |
| 624 | +{ | |
| 625 | + u32 val = REGV_RD32(VPU_37XX_TOP_NOC_QDENY); | |
| 626 | + | |
| 627 | + if (!REG_TEST_FLD_NUM(VPU_37XX_TOP_NOC_QDENY, CPU_CTRL, exp_val, val) || | |
| 628 | + !REG_TEST_FLD_NUM(VPU_37XX_TOP_NOC_QDENY, HOSTIF_L2CACHE, exp_val, val)) | |
| 629 | + return -EIO; | |
| 630 | + | |
| 631 | + return 0; | |
| 632 | +} | |
| 633 | + | |
| 634 | +static int top_noc_qdeny_check_40xx(struct ivpu_device *vdev, u32 exp_val) | |
| 635 | +{ | |
| 636 | + u32 val = REGV_RD32(VPU_40XX_TOP_NOC_QDENY); | |
| 637 | + | |
| 638 | + if (!REG_TEST_FLD_NUM(VPU_40XX_TOP_NOC_QDENY, CPU_CTRL, exp_val, val) || | |
| 639 | + !REG_TEST_FLD_NUM(VPU_40XX_TOP_NOC_QDENY, HOSTIF_L2CACHE, exp_val, val)) | |
| 640 | + return -EIO; | |
| 641 | + | |
| 642 | + return 0; | |
| 643 | +} | |
| 644 | + | |
| 645 | +static int top_noc_qdeny_check(struct ivpu_device *vdev, u32 exp_val) | |
| 646 | +{ | |
| 647 | + if (ivpu_hw_ip_gen(vdev) == IVPU_HW_IP_37XX) | |
| 648 | + return top_noc_qdeny_check_37xx(vdev, exp_val); | |
| 649 | + else | |
| 650 | + return top_noc_qdeny_check_40xx(vdev, exp_val); | |
| 651 | +} | |
| 652 | + | |
| 653 | +static int top_noc_drive(struct ivpu_device *vdev, bool enable) | |
| 654 | +{ | |
| 655 | + int ret; | |
| 656 | + | |
| 657 | + top_noc_qreqn_drive(vdev, enable); | |
| 658 | + | |
| 659 | + ret = top_noc_qacceptn_check(vdev, enable ? 0x1 : 0x0); | |
| 660 | + if (ret) { | |
| 661 | + ivpu_err(vdev, "Failed TOP NOC QACCEPTN check: %d\n", ret); | |
| 662 | + return ret; | |
| 663 | + } | |
| 664 | + | |
| 665 | + ret = top_noc_qdeny_check(vdev, 0x0); | |
| 666 | + if (ret) | |
| 667 | + ivpu_err(vdev, "Failed TOP NOC QDENY check: %d\n", ret); | |
| 668 | + | |
| 669 | + return ret; | |
| 670 | +} | |
| 671 | + | |
| 672 | +int ivpu_hw_ip_top_noc_enable(struct ivpu_device *vdev) | |
| 673 | +{ | |
| 674 | + return top_noc_drive(vdev, true); | |
| 675 | +} | |
| 676 | + | |
| 677 | +static void dpu_active_drive_37xx(struct ivpu_device *vdev, bool enable) | |
| 678 | +{ | |
| 679 | + u32 val = REGV_RD32(VPU_37XX_HOST_SS_AON_DPU_ACTIVE); | |
| 680 | + | |
| 681 | + if (enable) | |
| 682 | + val = REG_SET_FLD(VPU_37XX_HOST_SS_AON_DPU_ACTIVE, DPU_ACTIVE, val); | |
| 683 | + else | |
| 684 | + val = REG_CLR_FLD(VPU_37XX_HOST_SS_AON_DPU_ACTIVE, DPU_ACTIVE, val); | |
| 685 | + | |
| 686 | + REGV_WR32(VPU_37XX_HOST_SS_AON_DPU_ACTIVE, val); | |
| 687 | +} | |
| 688 | + | |
| 689 | +int ivpu_hw_ip_pwr_domain_enable(struct ivpu_device *vdev) | |
| 690 | +{ | |
| 691 | + int ret; | |
| 692 | + | |
| 693 | + if (ivpu_hw_ip_gen(vdev) == IVPU_HW_IP_50XX) | |
| 694 | + pwr_island_delay_set_50xx(vdev); | |
| 695 | + | |
| 696 | + pwr_island_enable(vdev); | |
| 697 | + | |
| 698 | + ret = wait_for_pwr_island_status(vdev, 0x1); | |
| 699 | + if (ret) { | |
| 700 | + ivpu_err(vdev, "Timed out waiting for power island status\n"); | |
| 701 | + return ret; | |
| 702 | + } | |
| 703 | + | |
| 704 | + ret = top_noc_qreqn_check(vdev, 0x0); | |
| 705 | + if (ret) { | |
| 706 | + ivpu_err(vdev, "Failed TOP NOC QREQN check %d\n", ret); | |
| 707 | + return ret; | |
| 708 | + } | |
| 709 | + | |
| 710 | + host_ss_clk_enable(vdev); | |
| 711 | + pwr_island_isolation_disable(vdev); | |
| 712 | + host_ss_rst_enable(vdev); | |
| 713 | + | |
| 714 | + if (ivpu_hw_ip_gen(vdev) == IVPU_HW_IP_37XX) | |
| 715 | + dpu_active_drive_37xx(vdev, true); | |
| 716 | + | |
| 717 | + return ret; | |
| 718 | +} | |
| 719 | + | |
| 720 | +u64 ivpu_hw_ip_read_perf_timer_counter(struct ivpu_device *vdev) | |
| 721 | +{ | |
| 722 | + if (ivpu_hw_ip_gen(vdev) == IVPU_HW_IP_37XX) | |
| 723 | + return REGV_RD64(VPU_37XX_CPU_SS_TIM_PERF_FREE_CNT); | |
| 724 | + else | |
| 725 | + return REGV_RD64(VPU_40XX_CPU_SS_TIM_PERF_EXT_FREE_CNT); | |
| 726 | +} | |
| 727 | + | |
| 728 | +static void ivpu_hw_ip_snoop_disable_37xx(struct ivpu_device *vdev) | |
| 729 | +{ | |
| 730 | + u32 val = REGV_RD32(VPU_37XX_HOST_IF_TCU_PTW_OVERRIDES); | |
| 731 | + | |
| 732 | + val = REG_SET_FLD(VPU_37XX_HOST_IF_TCU_PTW_OVERRIDES, NOSNOOP_OVERRIDE_EN, val); | |
| 733 | + val = REG_CLR_FLD(VPU_37XX_HOST_IF_TCU_PTW_OVERRIDES, AW_NOSNOOP_OVERRIDE, val); | |
| 734 | + | |
| 735 | + if (ivpu_is_force_snoop_enabled(vdev)) | |
| 736 | + val = REG_CLR_FLD(VPU_37XX_HOST_IF_TCU_PTW_OVERRIDES, AR_NOSNOOP_OVERRIDE, val); | |
| 737 | + else | |
| 738 | + val = REG_SET_FLD(VPU_37XX_HOST_IF_TCU_PTW_OVERRIDES, AR_NOSNOOP_OVERRIDE, val); | |
| 739 | + | |
| 740 | + REGV_WR32(VPU_37XX_HOST_IF_TCU_PTW_OVERRIDES, val); | |
| 741 | +} | |
| 742 | + | |
| 743 | +static void ivpu_hw_ip_snoop_disable_40xx(struct ivpu_device *vdev) | |
| 744 | +{ | |
| 745 | + u32 val = REGV_RD32(VPU_40XX_HOST_IF_TCU_PTW_OVERRIDES); | |
| 746 | + | |
| 747 | + val = REG_SET_FLD(VPU_40XX_HOST_IF_TCU_PTW_OVERRIDES, SNOOP_OVERRIDE_EN, val); | |
| 748 | + val = REG_SET_FLD(VPU_40XX_HOST_IF_TCU_PTW_OVERRIDES, AW_SNOOP_OVERRIDE, val); | |
| 749 | + | |
| 750 | + if (ivpu_is_force_snoop_enabled(vdev)) | |
| 751 | + val = REG_SET_FLD(VPU_40XX_HOST_IF_TCU_PTW_OVERRIDES, AR_SNOOP_OVERRIDE, val); | |
| 752 | + else | |
| 753 | + val = REG_CLR_FLD(VPU_40XX_HOST_IF_TCU_PTW_OVERRIDES, AR_SNOOP_OVERRIDE, val); | |
| 754 | + | |
| 755 | + REGV_WR32(VPU_40XX_HOST_IF_TCU_PTW_OVERRIDES, val); | |
| 756 | +} | |
| 757 | + | |
| 758 | +void ivpu_hw_ip_snoop_disable(struct ivpu_device *vdev) | |
| 759 | +{ | |
| 760 | + if (ivpu_hw_ip_gen(vdev) == IVPU_HW_IP_37XX) | |
| 761 | + return ivpu_hw_ip_snoop_disable_37xx(vdev); | |
| 762 | + else | |
| 763 | + return ivpu_hw_ip_snoop_disable_40xx(vdev); | |
| 764 | +} | |
| 765 | + | |
| 766 | +static void ivpu_hw_ip_tbu_mmu_enable_37xx(struct ivpu_device *vdev) | |
| 767 | +{ | |
| 768 | + u32 val = REGV_RD32(VPU_37XX_HOST_IF_TBU_MMUSSIDV); | |
| 769 | + | |
| 770 | + val = REG_SET_FLD(VPU_37XX_HOST_IF_TBU_MMUSSIDV, TBU0_AWMMUSSIDV, val); | |
| 771 | + val = REG_SET_FLD(VPU_37XX_HOST_IF_TBU_MMUSSIDV, TBU0_ARMMUSSIDV, val); | |
| 772 | + val = REG_SET_FLD(VPU_37XX_HOST_IF_TBU_MMUSSIDV, TBU2_AWMMUSSIDV, val); | |
| 773 | + val = REG_SET_FLD(VPU_37XX_HOST_IF_TBU_MMUSSIDV, TBU2_ARMMUSSIDV, val); | |
| 774 | + | |
| 775 | + REGV_WR32(VPU_37XX_HOST_IF_TBU_MMUSSIDV, val); | |
| 776 | +} | |
| 777 | + | |
| 778 | +static void ivpu_hw_ip_tbu_mmu_enable_40xx(struct ivpu_device *vdev) | |
| 779 | +{ | |
| 780 | + u32 val = REGV_RD32(VPU_40XX_HOST_IF_TBU_MMUSSIDV); | |
| 781 | + | |
| 782 | + val = REG_SET_FLD(VPU_40XX_HOST_IF_TBU_MMUSSIDV, TBU0_AWMMUSSIDV, val); | |
| 783 | + val = REG_SET_FLD(VPU_40XX_HOST_IF_TBU_MMUSSIDV, TBU0_ARMMUSSIDV, val); | |
| 784 | + val = REG_SET_FLD(VPU_40XX_HOST_IF_TBU_MMUSSIDV, TBU1_AWMMUSSIDV, val); | |
| 785 | + val = REG_SET_FLD(VPU_40XX_HOST_IF_TBU_MMUSSIDV, TBU1_ARMMUSSIDV, val); | |
| 786 | + val = REG_SET_FLD(VPU_40XX_HOST_IF_TBU_MMUSSIDV, TBU2_AWMMUSSIDV, val); | |
| 787 | + val = REG_SET_FLD(VPU_40XX_HOST_IF_TBU_MMUSSIDV, TBU2_ARMMUSSIDV, val); | |
| 788 | + | |
| 789 | + REGV_WR32(VPU_40XX_HOST_IF_TBU_MMUSSIDV, val); | |
| 790 | +} | |
| 791 | + | |
| 792 | +void ivpu_hw_ip_tbu_mmu_enable(struct ivpu_device *vdev) | |
| 793 | +{ | |
| 794 | + if (ivpu_hw_ip_gen(vdev) == IVPU_HW_IP_37XX) | |
| 795 | + return ivpu_hw_ip_tbu_mmu_enable_37xx(vdev); | |
| 796 | + else | |
| 797 | + return ivpu_hw_ip_tbu_mmu_enable_40xx(vdev); | |
| 798 | +} | |
| 799 | + | |
| 800 | +static int soc_cpu_boot_37xx(struct ivpu_device *vdev) | |
| 801 | +{ | |
| 802 | + u32 val; | |
| 803 | + | |
| 804 | + val = REGV_RD32(VPU_37XX_CPU_SS_MSSCPU_CPR_LEON_RT_VEC); | |
| 805 | + val = REG_SET_FLD(VPU_37XX_CPU_SS_MSSCPU_CPR_LEON_RT_VEC, IRQI_RSTRUN0, val); | |
| 806 | + | |
| 807 | + val = REG_CLR_FLD(VPU_37XX_CPU_SS_MSSCPU_CPR_LEON_RT_VEC, IRQI_RSTVEC, val); | |
| 808 | + REGV_WR32(VPU_37XX_CPU_SS_MSSCPU_CPR_LEON_RT_VEC, val); | |
| 809 | + | |
| 810 | + val = REG_SET_FLD(VPU_37XX_CPU_SS_MSSCPU_CPR_LEON_RT_VEC, IRQI_RESUME0, val); | |
| 811 | + REGV_WR32(VPU_37XX_CPU_SS_MSSCPU_CPR_LEON_RT_VEC, val); | |
| 812 | + | |
| 813 | + val = REG_CLR_FLD(VPU_37XX_CPU_SS_MSSCPU_CPR_LEON_RT_VEC, IRQI_RESUME0, val); | |
| 814 | + REGV_WR32(VPU_37XX_CPU_SS_MSSCPU_CPR_LEON_RT_VEC, val); | |
| 815 | + | |
| 816 | + val = vdev->fw->entry_point >> 9; | |
| 817 | + REGV_WR32(VPU_37XX_HOST_SS_LOADING_ADDRESS_LO, val); | |
| 818 | + | |
| 819 | + val = REG_SET_FLD(VPU_37XX_HOST_SS_LOADING_ADDRESS_LO, DONE, val); | |
| 820 | + REGV_WR32(VPU_37XX_HOST_SS_LOADING_ADDRESS_LO, val); | |
| 821 | + | |
| 822 | + ivpu_dbg(vdev, PM, "Booting firmware, mode: %s\n", | |
| 823 | + vdev->fw->entry_point == vdev->fw->cold_boot_entry_point ? "cold boot" : "resume"); | |
| 824 | + | |
| 825 | + return 0; | |
| 826 | +} | |
| 827 | + | |
| 828 | +static int cpu_noc_qacceptn_check_40xx(struct ivpu_device *vdev, u32 exp_val) | |
| 829 | +{ | |
| 830 | + u32 val = REGV_RD32(VPU_40XX_CPU_SS_CPR_NOC_QACCEPTN); | |
| 831 | + | |
| 832 | + if (!REG_TEST_FLD_NUM(VPU_40XX_CPU_SS_CPR_NOC_QACCEPTN, TOP_MMIO, exp_val, val)) | |
| 833 | + return -EIO; | |
| 834 | + | |
| 835 | + return 0; | |
| 836 | +} | |
| 837 | + | |
| 838 | +static int cpu_noc_qdeny_check_40xx(struct ivpu_device *vdev, u32 exp_val) | |
| 839 | +{ | |
| 840 | + u32 val = REGV_RD32(VPU_40XX_CPU_SS_CPR_NOC_QDENY); | |
| 841 | + | |
| 842 | + if (!REG_TEST_FLD_NUM(VPU_40XX_CPU_SS_CPR_NOC_QDENY, TOP_MMIO, exp_val, val)) | |
| 843 | + return -EIO; | |
| 844 | + | |
| 845 | + return 0; | |
| 846 | +} | |
| 847 | + | |
| 848 | +static void cpu_noc_top_mmio_drive_40xx(struct ivpu_device *vdev, bool enable) | |
| 849 | +{ | |
| 850 | + u32 val = REGV_RD32(VPU_40XX_CPU_SS_CPR_NOC_QREQN); | |
| 851 | + | |
| 852 | + if (enable) | |
| 853 | + val = REG_SET_FLD(VPU_40XX_CPU_SS_CPR_NOC_QREQN, TOP_MMIO, val); | |
| 854 | + else | |
| 855 | + val = REG_CLR_FLD(VPU_40XX_CPU_SS_CPR_NOC_QREQN, TOP_MMIO, val); | |
| 856 | + REGV_WR32(VPU_40XX_CPU_SS_CPR_NOC_QREQN, val); | |
| 857 | +} | |
| 858 | + | |
| 859 | +static int soc_cpu_drive_40xx(struct ivpu_device *vdev, bool enable) | |
| 860 | +{ | |
| 861 | + int ret; | |
| 862 | + | |
| 863 | + cpu_noc_top_mmio_drive_40xx(vdev, enable); | |
| 864 | + | |
| 865 | + ret = cpu_noc_qacceptn_check_40xx(vdev, enable ? 0x1 : 0x0); | |
| 866 | + if (ret) { | |
| 867 | + ivpu_err(vdev, "Failed qacceptn check: %d\n", ret); | |
| 868 | + return ret; | |
| 869 | + } | |
| 870 | + | |
| 871 | + ret = cpu_noc_qdeny_check_40xx(vdev, 0x0); | |
| 872 | + if (ret) | |
| 873 | + ivpu_err(vdev, "Failed qdeny check: %d\n", ret); | |
| 874 | + | |
| 875 | + return ret; | |
| 876 | +} | |
| 877 | + | |
| 878 | +static int soc_cpu_enable(struct ivpu_device *vdev) | |
| 879 | +{ | |
| 880 | + return soc_cpu_drive_40xx(vdev, true); | |
| 881 | +} | |
| 882 | + | |
| 883 | +static int soc_cpu_boot_40xx(struct ivpu_device *vdev) | |
| 884 | +{ | |
| 885 | + int ret; | |
| 886 | + u32 val; | |
| 887 | + u64 val64; | |
| 888 | + | |
| 889 | + ret = soc_cpu_enable(vdev); | |
| 890 | + if (ret) { | |
| 891 | + ivpu_err(vdev, "Failed to enable SOC CPU: %d\n", ret); | |
| 892 | + return ret; | |
| 893 | + } | |
| 894 | + | |
| 895 | + val64 = vdev->fw->entry_point; | |
| 896 | + val64 <<= ffs(VPU_40XX_HOST_SS_VERIFICATION_ADDRESS_LO_IMAGE_LOCATION_MASK) - 1; | |
| 897 | + REGV_WR64(VPU_40XX_HOST_SS_VERIFICATION_ADDRESS_LO, val64); | |
| 898 | + | |
| 899 | + val = REGV_RD32(VPU_40XX_HOST_SS_VERIFICATION_ADDRESS_LO); | |
| 900 | + val = REG_SET_FLD(VPU_40XX_HOST_SS_VERIFICATION_ADDRESS_LO, DONE, val); | |
| 901 | + REGV_WR32(VPU_40XX_HOST_SS_VERIFICATION_ADDRESS_LO, val); | |
| 902 | + | |
| 903 | + ivpu_dbg(vdev, PM, "Booting firmware, mode: %s\n", | |
| 904 | + ivpu_fw_is_cold_boot(vdev) ? "cold boot" : "resume"); | |
| 905 | + | |
| 906 | + return 0; | |
| 907 | +} | |
| 908 | + | |
| 909 | +int ivpu_hw_ip_soc_cpu_boot(struct ivpu_device *vdev) | |
| 910 | +{ | |
| 911 | + if (ivpu_hw_ip_gen(vdev) == IVPU_HW_IP_37XX) | |
| 912 | + return soc_cpu_boot_37xx(vdev); | |
| 913 | + else | |
| 914 | + return soc_cpu_boot_40xx(vdev); | |
| 915 | +} | |
| 916 | + | |
| 917 | +static void wdt_disable_37xx(struct ivpu_device *vdev) | |
| 918 | +{ | |
| 919 | + u32 val; | |
| 920 | + | |
| 921 | + /* Enable writing and set non-zero WDT value */ | |
| 922 | + REGV_WR32(VPU_37XX_CPU_SS_TIM_SAFE, TIM_SAFE_ENABLE); | |
| 923 | + REGV_WR32(VPU_37XX_CPU_SS_TIM_WATCHDOG, TIM_WATCHDOG_RESET_VALUE); | |
| 924 | + | |
| 925 | + /* Enable writing and disable watchdog timer */ | |
| 926 | + REGV_WR32(VPU_37XX_CPU_SS_TIM_SAFE, TIM_SAFE_ENABLE); | |
| 927 | + REGV_WR32(VPU_37XX_CPU_SS_TIM_WDOG_EN, 0); | |
| 928 | + | |
| 929 | + /* Now clear the timeout interrupt */ | |
| 930 | + val = REGV_RD32(VPU_37XX_CPU_SS_TIM_GEN_CONFIG); | |
| 931 | + val = REG_CLR_FLD(VPU_37XX_CPU_SS_TIM_GEN_CONFIG, WDOG_TO_INT_CLR, val); | |
| 932 | + REGV_WR32(VPU_37XX_CPU_SS_TIM_GEN_CONFIG, val); | |
| 933 | +} | |
| 934 | + | |
| 935 | +static void wdt_disable_40xx(struct ivpu_device *vdev) | |
| 936 | +{ | |
| 937 | + u32 val; | |
| 938 | + | |
| 939 | + REGV_WR32(VPU_40XX_CPU_SS_TIM_SAFE, TIM_SAFE_ENABLE); | |
| 940 | + REGV_WR32(VPU_40XX_CPU_SS_TIM_WATCHDOG, TIM_WATCHDOG_RESET_VALUE); | |
| 941 | + | |
| 942 | + REGV_WR32(VPU_40XX_CPU_SS_TIM_SAFE, TIM_SAFE_ENABLE); | |
| 943 | + REGV_WR32(VPU_40XX_CPU_SS_TIM_WDOG_EN, 0); | |
| 944 | + | |
| 945 | + val = REGV_RD32(VPU_40XX_CPU_SS_TIM_GEN_CONFIG); | |
| 946 | + val = REG_CLR_FLD(VPU_40XX_CPU_SS_TIM_GEN_CONFIG, WDOG_TO_INT_CLR, val); | |
| 947 | + REGV_WR32(VPU_40XX_CPU_SS_TIM_GEN_CONFIG, val); | |
| 948 | +} | |
| 949 | + | |
| 950 | +void ivpu_hw_ip_wdt_disable(struct ivpu_device *vdev) | |
| 951 | +{ | |
| 952 | + if (ivpu_hw_ip_gen(vdev) == IVPU_HW_IP_37XX) | |
| 953 | + return wdt_disable_37xx(vdev); | |
| 954 | + else | |
| 955 | + return wdt_disable_40xx(vdev); | |
| 956 | +} | |
| 957 | + | |
| 958 | +static u32 ipc_rx_count_get_37xx(struct ivpu_device *vdev) | |
| 959 | +{ | |
| 960 | + u32 count = REGV_RD32_SILENT(VPU_37XX_HOST_SS_TIM_IPC_FIFO_STAT); | |
| 961 | + | |
| 962 | + return REG_GET_FLD(VPU_37XX_HOST_SS_TIM_IPC_FIFO_STAT, FILL_LEVEL, count); | |
| 963 | +} | |
| 964 | + | |
| 965 | +static u32 ipc_rx_count_get_40xx(struct ivpu_device *vdev) | |
| 966 | +{ | |
| 967 | + u32 count = REGV_RD32_SILENT(VPU_40XX_HOST_SS_TIM_IPC_FIFO_STAT); | |
| 968 | + | |
| 969 | + return REG_GET_FLD(VPU_40XX_HOST_SS_TIM_IPC_FIFO_STAT, FILL_LEVEL, count); | |
| 970 | +} | |
| 971 | + | |
| 972 | +u32 ivpu_hw_ip_ipc_rx_count_get(struct ivpu_device *vdev) | |
| 973 | +{ | |
| 974 | + if (ivpu_hw_ip_gen(vdev) == IVPU_HW_IP_37XX) | |
| 975 | + return ipc_rx_count_get_37xx(vdev); | |
| 976 | + else | |
| 977 | + return ipc_rx_count_get_40xx(vdev); | |
| 978 | +} | |
| 979 | + | |
| 980 | +void ivpu_hw_ip_irq_enable(struct ivpu_device *vdev) | |
| 981 | +{ | |
| 982 | + if (ivpu_hw_ip_gen(vdev) == IVPU_HW_IP_37XX) { | |
| 983 | + REGV_WR32(VPU_37XX_HOST_SS_FW_SOC_IRQ_EN, ITF_FIREWALL_VIOLATION_MASK_37XX); | |
| 984 | + REGV_WR64(VPU_37XX_HOST_SS_ICB_ENABLE_0, ICB_0_1_IRQ_MASK_37XX); | |
| 985 | + } else { | |
| 986 | + REGV_WR32(VPU_40XX_HOST_SS_FW_SOC_IRQ_EN, ITF_FIREWALL_VIOLATION_MASK_40XX); | |
| 987 | + REGV_WR64(VPU_40XX_HOST_SS_ICB_ENABLE_0, ICB_0_1_IRQ_MASK_40XX); | |
| 988 | + } | |
| 989 | +} | |
| 990 | + | |
| 991 | +void ivpu_hw_ip_irq_disable(struct ivpu_device *vdev) | |
| 992 | +{ | |
| 993 | + if (ivpu_hw_ip_gen(vdev) == IVPU_HW_IP_37XX) { | |
| 994 | + REGV_WR64(VPU_37XX_HOST_SS_ICB_ENABLE_0, 0x0ull); | |
| 995 | + REGV_WR32(VPU_37XX_HOST_SS_FW_SOC_IRQ_EN, 0x0); | |
| 996 | + } else { | |
| 997 | + REGV_WR64(VPU_40XX_HOST_SS_ICB_ENABLE_0, 0x0ull); | |
| 998 | + REGV_WR32(VPU_40XX_HOST_SS_FW_SOC_IRQ_EN, 0x0ul); | |
| 999 | + } | |
| 1000 | +} | |
| 1001 | + | |
| 1002 | +static void diagnose_failure_37xx(struct ivpu_device *vdev) | |
| 1003 | +{ | |
| 1004 | + u32 reg = REGV_RD32(VPU_37XX_HOST_SS_ICB_STATUS_0) & ICB_0_IRQ_MASK_37XX; | |
| 1005 | + | |
| 1006 | + if (ipc_rx_count_get_37xx(vdev)) | |
| 1007 | + ivpu_err(vdev, "IPC FIFO queue not empty, missed IPC IRQ"); | |
| 1008 | + | |
| 1009 | + if (REG_TEST_FLD(VPU_37XX_HOST_SS_ICB_STATUS_0, CPU_INT_REDIRECT_0_INT, reg)) | |
| 1010 | + ivpu_err(vdev, "WDT MSS timeout detected\n"); | |
| 1011 | + | |
| 1012 | + if (REG_TEST_FLD(VPU_37XX_HOST_SS_ICB_STATUS_0, CPU_INT_REDIRECT_1_INT, reg)) | |
| 1013 | + ivpu_err(vdev, "WDT NCE timeout detected\n"); | |
| 1014 | + | |
| 1015 | + if (REG_TEST_FLD(VPU_37XX_HOST_SS_ICB_STATUS_0, NOC_FIREWALL_INT, reg)) | |
| 1016 | + ivpu_err(vdev, "NOC Firewall irq detected\n"); | |
| 1017 | +} | |
| 1018 | + | |
| 1019 | +static void diagnose_failure_40xx(struct ivpu_device *vdev) | |
| 1020 | +{ | |
| 1021 | + u32 reg = REGV_RD32(VPU_40XX_HOST_SS_ICB_STATUS_0) & ICB_0_IRQ_MASK_40XX; | |
| 1022 | + | |
| 1023 | + if (ipc_rx_count_get_40xx(vdev)) | |
| 1024 | + ivpu_err(vdev, "IPC FIFO queue not empty, missed IPC IRQ"); | |
| 1025 | + | |
| 1026 | + if (REG_TEST_FLD(VPU_40XX_HOST_SS_ICB_STATUS_0, CPU_INT_REDIRECT_0_INT, reg)) | |
| 1027 | + ivpu_err(vdev, "WDT MSS timeout detected\n"); | |
| 1028 | + | |
| 1029 | + if (REG_TEST_FLD(VPU_40XX_HOST_SS_ICB_STATUS_0, CPU_INT_REDIRECT_1_INT, reg)) | |
| 1030 | + ivpu_err(vdev, "WDT NCE timeout detected\n"); | |
| 1031 | + | |
| 1032 | + if (REG_TEST_FLD(VPU_40XX_HOST_SS_ICB_STATUS_0, NOC_FIREWALL_INT, reg)) | |
| 1033 | + ivpu_err(vdev, "NOC Firewall irq detected\n"); | |
| 1034 | +} | |
| 1035 | + | |
| 1036 | +void ivpu_hw_ip_diagnose_failure(struct ivpu_device *vdev) | |
| 1037 | +{ | |
| 1038 | + if (ivpu_hw_ip_gen(vdev) == IVPU_HW_IP_37XX) | |
| 1039 | + diagnose_failure_37xx(vdev); | |
| 1040 | + else | |
| 1041 | + diagnose_failure_40xx(vdev); | |
| 1042 | +} | |
| 1043 | + | |
| 1044 | +void ivpu_hw_ip_irq_clear(struct ivpu_device *vdev) | |
| 1045 | +{ | |
| 1046 | + if (ivpu_hw_ip_gen(vdev) == IVPU_HW_IP_37XX) | |
| 1047 | + REGV_WR64(VPU_37XX_HOST_SS_ICB_CLEAR_0, ICB_0_1_IRQ_MASK_37XX); | |
| 1048 | + else | |
| 1049 | + REGV_WR64(VPU_40XX_HOST_SS_ICB_CLEAR_0, ICB_0_1_IRQ_MASK_40XX); | |
| 1050 | +} | |
| 1051 | + | |
| 1052 | +static void irq_wdt_nce_handler(struct ivpu_device *vdev) | |
| 1053 | +{ | |
| 1054 | + ivpu_pm_trigger_recovery(vdev, "WDT NCE IRQ"); | |
| 1055 | +} | |
| 1056 | + | |
| 1057 | +static void irq_wdt_mss_handler(struct ivpu_device *vdev) | |
| 1058 | +{ | |
| 1059 | + ivpu_hw_ip_wdt_disable(vdev); | |
| 1060 | + ivpu_pm_trigger_recovery(vdev, "WDT MSS IRQ"); | |
| 1061 | +} | |
| 1062 | + | |
| 1063 | +static void irq_noc_firewall_handler(struct ivpu_device *vdev) | |
| 1064 | +{ | |
| 1065 | + ivpu_pm_trigger_recovery(vdev, "NOC Firewall IRQ"); | |
| 1066 | +} | |
| 1067 | + | |
| 1068 | +/* Handler for IRQs from NPU core */ | |
| 1069 | +bool ivpu_hw_ip_irq_handler_37xx(struct ivpu_device *vdev, int irq) | |
| 1070 | +{ | |
| 1071 | + u32 status = REGV_RD32(VPU_37XX_HOST_SS_ICB_STATUS_0) & ICB_0_IRQ_MASK_37XX; | |
| 1072 | + | |
| 1073 | + if (!status) | |
| 1074 | + return false; | |
| 1075 | + | |
| 1076 | + REGV_WR32(VPU_37XX_HOST_SS_ICB_CLEAR_0, status); | |
| 1077 | + | |
| 1078 | + if (REG_TEST_FLD(VPU_37XX_HOST_SS_ICB_STATUS_0, MMU_IRQ_0_INT, status)) | |
| 1079 | + ivpu_mmu_irq_evtq_handler(vdev); | |
| 1080 | + | |
| 1081 | + if (REG_TEST_FLD(VPU_37XX_HOST_SS_ICB_STATUS_0, HOST_IPC_FIFO_INT, status)) | |
| 1082 | + ivpu_ipc_irq_handler(vdev); | |
| 1083 | + | |
| 1084 | + if (REG_TEST_FLD(VPU_37XX_HOST_SS_ICB_STATUS_0, MMU_IRQ_1_INT, status)) | |
| 1085 | + ivpu_dbg(vdev, IRQ, "MMU sync complete\n"); | |
| 1086 | + | |
| 1087 | + if (REG_TEST_FLD(VPU_37XX_HOST_SS_ICB_STATUS_0, MMU_IRQ_2_INT, status)) | |
| 1088 | + ivpu_mmu_irq_gerr_handler(vdev); | |
| 1089 | + | |
| 1090 | + if (REG_TEST_FLD(VPU_37XX_HOST_SS_ICB_STATUS_0, CPU_INT_REDIRECT_0_INT, status)) | |
| 1091 | + irq_wdt_mss_handler(vdev); | |
| 1092 | + | |
| 1093 | + if (REG_TEST_FLD(VPU_37XX_HOST_SS_ICB_STATUS_0, CPU_INT_REDIRECT_1_INT, status)) | |
| 1094 | + irq_wdt_nce_handler(vdev); | |
| 1095 | + | |
| 1096 | + if (REG_TEST_FLD(VPU_37XX_HOST_SS_ICB_STATUS_0, NOC_FIREWALL_INT, status)) | |
| 1097 | + irq_noc_firewall_handler(vdev); | |
| 1098 | + | |
| 1099 | + return true; | |
| 1100 | +} | |
| 1101 | + | |
| 1102 | +/* Handler for IRQs from NPU core */ | |
| 1103 | +bool ivpu_hw_ip_irq_handler_40xx(struct ivpu_device *vdev, int irq) | |
| 1104 | +{ | |
| 1105 | + u32 status = REGV_RD32(VPU_40XX_HOST_SS_ICB_STATUS_0) & ICB_0_IRQ_MASK_40XX; | |
| 1106 | + | |
| 1107 | + if (!status) | |
| 1108 | + return false; | |
| 1109 | + | |
| 1110 | + REGV_WR32(VPU_40XX_HOST_SS_ICB_CLEAR_0, status); | |
| 1111 | + | |
| 1112 | + if (REG_TEST_FLD(VPU_40XX_HOST_SS_ICB_STATUS_0, MMU_IRQ_0_INT, status)) | |
| 1113 | + ivpu_mmu_irq_evtq_handler(vdev); | |
| 1114 | + | |
| 1115 | + if (REG_TEST_FLD(VPU_40XX_HOST_SS_ICB_STATUS_0, HOST_IPC_FIFO_INT, status)) | |
| 1116 | + ivpu_ipc_irq_handler(vdev); | |
| 1117 | + | |
| 1118 | + if (REG_TEST_FLD(VPU_40XX_HOST_SS_ICB_STATUS_0, MMU_IRQ_1_INT, status)) | |
| 1119 | + ivpu_dbg(vdev, IRQ, "MMU sync complete\n"); | |
| 1120 | + | |
| 1121 | + if (REG_TEST_FLD(VPU_40XX_HOST_SS_ICB_STATUS_0, MMU_IRQ_2_INT, status)) | |
| 1122 | + ivpu_mmu_irq_gerr_handler(vdev); | |
| 1123 | + | |
| 1124 | + if (REG_TEST_FLD(VPU_40XX_HOST_SS_ICB_STATUS_0, CPU_INT_REDIRECT_0_INT, status)) | |
| 1125 | + irq_wdt_mss_handler(vdev); | |
| 1126 | + | |
| 1127 | + if (REG_TEST_FLD(VPU_40XX_HOST_SS_ICB_STATUS_0, CPU_INT_REDIRECT_1_INT, status)) | |
| 1128 | + irq_wdt_nce_handler(vdev); | |
| 1129 | + | |
| 1130 | + if (REG_TEST_FLD(VPU_40XX_HOST_SS_ICB_STATUS_0, NOC_FIREWALL_INT, status)) | |
| 1131 | + irq_noc_firewall_handler(vdev); | |
| 1132 | + | |
| 1133 | + return true; | |
| 1134 | +} | |
| 1135 | + | |
| 1136 | +static void db_set_37xx(struct ivpu_device *vdev, u32 db_id) | |
| 1137 | +{ | |
| 1138 | + u32 reg_stride = VPU_37XX_CPU_SS_DOORBELL_1 - VPU_37XX_CPU_SS_DOORBELL_0; | |
| 1139 | + u32 val = REG_FLD(VPU_37XX_CPU_SS_DOORBELL_0, SET); | |
| 1140 | + | |
| 1141 | + REGV_WR32I(VPU_37XX_CPU_SS_DOORBELL_0, reg_stride, db_id, val); | |
| 1142 | +} | |
| 1143 | + | |
| 1144 | +static void db_set_40xx(struct ivpu_device *vdev, u32 db_id) | |
| 1145 | +{ | |
| 1146 | + u32 reg_stride = VPU_40XX_CPU_SS_DOORBELL_1 - VPU_40XX_CPU_SS_DOORBELL_0; | |
| 1147 | + u32 val = REG_FLD(VPU_40XX_CPU_SS_DOORBELL_0, SET); | |
| 1148 | + | |
| 1149 | + REGV_WR32I(VPU_40XX_CPU_SS_DOORBELL_0, reg_stride, db_id, val); | |
| 1150 | +} | |
| 1151 | + | |
| 1152 | +void ivpu_hw_ip_db_set(struct ivpu_device *vdev, u32 db_id) | |
| 1153 | +{ | |
| 1154 | + if (ivpu_hw_ip_gen(vdev) == IVPU_HW_IP_37XX) | |
| 1155 | + db_set_37xx(vdev, db_id); | |
| 1156 | + else | |
| 1157 | + db_set_40xx(vdev, db_id); | |
| 1158 | +} | |
| 1159 | + | |
| 1160 | +u32 ivpu_hw_ip_ipc_rx_addr_get(struct ivpu_device *vdev) | |
| 1161 | +{ | |
| 1162 | + if (ivpu_hw_ip_gen(vdev) == IVPU_HW_IP_37XX) | |
| 1163 | + return REGV_RD32(VPU_37XX_HOST_SS_TIM_IPC_FIFO_ATM); | |
| 1164 | + else | |
| 1165 | + return REGV_RD32(VPU_40XX_HOST_SS_TIM_IPC_FIFO_ATM); | |
| 1166 | +} | |
| 1167 | + | |
| 1168 | +void ivpu_hw_ip_ipc_tx_set(struct ivpu_device *vdev, u32 vpu_addr) | |
| 1169 | +{ | |
| 1170 | + if (ivpu_hw_ip_gen(vdev) == IVPU_HW_IP_37XX) | |
| 1171 | + REGV_WR32(VPU_37XX_CPU_SS_TIM_IPC_FIFO, vpu_addr); | |
| 1172 | + else | |
| 1173 | + REGV_WR32(VPU_40XX_CPU_SS_TIM_IPC_FIFO, vpu_addr); | |
| 1174 | +} | |
| @@ -0,0 +1,36 @@ | ||
| 1 | +/* SPDX-License-Identifier: GPL-2.0-only */ | |
| 2 | +/* | |
| 3 | + * Copyright (C) 2020-2024 Intel Corporation | |
| 4 | + */ | |
| 5 | + | |
| 6 | +#ifndef __IVPU_HW_IP_H__ | |
| 7 | +#define __IVPU_HW_IP_H__ | |
| 8 | + | |
| 9 | +#include "ivpu_drv.h" | |
| 10 | + | |
| 11 | +int ivpu_hw_ip_host_ss_configure(struct ivpu_device *vdev); | |
| 12 | +void ivpu_hw_ip_idle_gen_enable(struct ivpu_device *vdev); | |
| 13 | +void ivpu_hw_ip_idle_gen_disable(struct ivpu_device *vdev); | |
| 14 | +int ivpu_hw_ip_pwr_domain_enable(struct ivpu_device *vdev); | |
| 15 | +int ivpu_hw_ip_host_ss_axi_enable(struct ivpu_device *vdev); | |
| 16 | +int ivpu_hw_ip_top_noc_enable(struct ivpu_device *vdev); | |
| 17 | +u64 ivpu_hw_ip_read_perf_timer_counter(struct ivpu_device *vdev); | |
| 18 | +void ivpu_hw_ip_snoop_disable(struct ivpu_device *vdev); | |
| 19 | +void ivpu_hw_ip_tbu_mmu_enable(struct ivpu_device *vdev); | |
| 20 | +int ivpu_hw_ip_soc_cpu_boot(struct ivpu_device *vdev); | |
| 21 | +void ivpu_hw_ip_wdt_disable(struct ivpu_device *vdev); | |
| 22 | +void ivpu_hw_ip_diagnose_failure(struct ivpu_device *vdev); | |
| 23 | +u32 ivpu_hw_ip_ipc_rx_count_get(struct ivpu_device *vdev); | |
| 24 | +void ivpu_hw_ip_irq_clear(struct ivpu_device *vdev); | |
| 25 | +bool ivpu_hw_ip_irq_handler_37xx(struct ivpu_device *vdev, int irq); | |
| 26 | +bool ivpu_hw_ip_irq_handler_40xx(struct ivpu_device *vdev, int irq); | |
| 27 | +void ivpu_hw_ip_db_set(struct ivpu_device *vdev, u32 db_id); | |
| 28 | +u32 ivpu_hw_ip_ipc_rx_addr_get(struct ivpu_device *vdev); | |
| 29 | +void ivpu_hw_ip_ipc_tx_set(struct ivpu_device *vdev, u32 vpu_addr); | |
| 30 | +void ivpu_hw_ip_irq_enable(struct ivpu_device *vdev); | |
| 31 | +void ivpu_hw_ip_irq_disable(struct ivpu_device *vdev); | |
| 32 | +void ivpu_hw_ip_diagnose_failure(struct ivpu_device *vdev); | |
| 33 | +void ivpu_hw_ip_fabric_req_override_enable_50xx(struct ivpu_device *vdev); | |
| 34 | +void ivpu_hw_ip_fabric_req_override_disable_50xx(struct ivpu_device *vdev); | |
| 35 | + | |
| 36 | +#endif /* __IVPU_HW_IP_H__ */ | |
| @@ -129,7 +129,7 @@ static void ivpu_ipc_tx_release(struct ivpu_device *vdev, u32 vpu_addr) · 128 unmodified lines | ||
| 129 | 129 | |
| 130 | 130 | static void ivpu_ipc_tx(struct ivpu_device *vdev, u32 vpu_addr) |
| 131 | 131 | { |
| 132 | − ivpu_hw_reg_ipc_tx_set(vdev, vpu_addr); | |
| 132 | + ivpu_hw_ipc_tx_set(vdev, vpu_addr); | |
| 133 | 133 | } |
| 134 | 134 | |
| 135 | 135 | static void |
| @@ -210,8 +210,7 @@ void ivpu_ipc_consumer_del(struct ivpu_device *vdev, struct ivpu_ipc_consumer *c · 74 unmodified lines | ||
| 210 | 210 | ivpu_ipc_tx_release(vdev, cons->tx_vpu_addr); |
| 211 | 211 | } |
| 212 | 212 | |
| 213 | −static int | |
| 214 | −ivpu_ipc_send(struct ivpu_device *vdev, struct ivpu_ipc_consumer *cons, struct vpu_jsm_msg *req) | |
| 213 | +int ivpu_ipc_send(struct ivpu_device *vdev, struct ivpu_ipc_consumer *cons, struct vpu_jsm_msg *req) | |
| 215 | 214 | { |
| 216 | 215 | struct ivpu_ipc_info *ipc = vdev->ipc; |
| 217 | 216 | int ret; |
| @@ -378,7 +377,7 @@ ivpu_ipc_match_consumer(struct ivpu_device *vdev, struct ivpu_ipc_consumer *cons · 160 unmodified lines | ||
| 378 | 377 | return false; |
| 379 | 378 | } |
| 380 | 379 | |
| 381 | −void ivpu_ipc_irq_handler(struct ivpu_device *vdev, bool *wake_thread) | |
| 380 | +void ivpu_ipc_irq_handler(struct ivpu_device *vdev) | |
| 382 | 381 | { |
| 383 | 382 | struct ivpu_ipc_info *ipc = vdev->ipc; |
| 384 | 383 | struct ivpu_ipc_consumer *cons; |
| @@ -392,8 +391,8 @@ void ivpu_ipc_irq_handler(struct ivpu_device *vdev, bool *wake_thread) · 7 unmodified lines | ||
| 392 | 391 | * Driver needs to purge all messages from IPC FIFO to clear IPC interrupt. |
| 393 | 392 | * Without purge IPC FIFO to 0 next IPC interrupts won't be generated. |
| 394 | 393 | */ |
| 395 | − while (ivpu_hw_reg_ipc_rx_count_get(vdev)) { | |
| 396 | − vpu_addr = ivpu_hw_reg_ipc_rx_addr_get(vdev); | |
| 394 | + while (ivpu_hw_ipc_rx_count_get(vdev)) { | |
| 395 | + vpu_addr = ivpu_hw_ipc_rx_addr_get(vdev); | |
| 397 | 396 | if (vpu_addr == REG_IO_ERROR) { |
| 398 | 397 | ivpu_err_ratelimited(vdev, "Failed to read IPC rx addr register\n"); |
| 399 | 398 | return; |
| @@ -442,11 +441,12 @@ void ivpu_ipc_irq_handler(struct ivpu_device *vdev, bool *wake_thread) · 42 unmodified lines | ||
| 442 | 441 | } |
| 443 | 442 | } |
| 444 | 443 | |
| 445 | − if (wake_thread) | |
| 446 | − *wake_thread = !list_empty(&ipc->cb_msg_list); | |
| 444 | + if (!list_empty(&ipc->cb_msg_list)) | |
| 445 | + if (!kfifo_put(&vdev->hw->irq.fifo, IVPU_HW_IRQ_SRC_IPC)) | |
| 446 | + ivpu_err_ratelimited(vdev, "IRQ FIFO full\n"); | |
| 447 | 447 | } |
| 448 | 448 | |
| 449 | −irqreturn_t ivpu_ipc_irq_thread_handler(struct ivpu_device *vdev) | |
| 449 | +void ivpu_ipc_irq_thread_handler(struct ivpu_device *vdev) | |
| 450 | 450 | { |
| 451 | 451 | struct ivpu_ipc_info *ipc = vdev->ipc; |
| 452 | 452 | struct ivpu_ipc_rx_msg *rx_msg, *r; |
| @@ -462,8 +462,6 @@ irqreturn_t ivpu_ipc_irq_thread_handler(struct ivpu_device *vdev) · 9 unmodified lines | ||
| 462 | 462 | rx_msg->callback(vdev, rx_msg->ipc_hdr, rx_msg->jsm_msg); |
| 463 | 463 | ivpu_ipc_rx_msg_del(vdev, rx_msg); |
| 464 | 464 | } |
| 465 | − | |
| 466 | − return IRQ_HANDLED; | |
| 467 | 465 | } |
| 468 | 466 | |
| 469 | 467 | int ivpu_ipc_init(struct ivpu_device *vdev) |
| @@ -1,6 +1,6 @@ | ||
| 1 | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
| 2 | 2 | /* |
| 3 | − * Copyright (C) 2020-2023 Intel Corporation | |
| 3 | + * Copyright (C) 2020-2024 Intel Corporation | |
| 4 | 4 | */ |
| 5 | 5 | |
| 6 | 6 | #ifndef __IVPU_IPC_H__ |
| @@ -89,13 +89,15 @@ void ivpu_ipc_enable(struct ivpu_device *vdev); · 82 unmodified lines | ||
| 89 | 89 | void ivpu_ipc_disable(struct ivpu_device *vdev); |
| 90 | 90 | void ivpu_ipc_reset(struct ivpu_device *vdev); |
| 91 | 91 | |
| 92 | −void ivpu_ipc_irq_handler(struct ivpu_device *vdev, bool *wake_thread); | |
| 93 | −irqreturn_t ivpu_ipc_irq_thread_handler(struct ivpu_device *vdev); | |
| 92 | +void ivpu_ipc_irq_handler(struct ivpu_device *vdev); | |
| 93 | +void ivpu_ipc_irq_thread_handler(struct ivpu_device *vdev); | |
| 94 | 94 | |
| 95 | 95 | void ivpu_ipc_consumer_add(struct ivpu_device *vdev, struct ivpu_ipc_consumer *cons, |
| 96 | 96 | u32 channel, ivpu_ipc_rx_callback_t callback); |
| 97 | 97 | void ivpu_ipc_consumer_del(struct ivpu_device *vdev, struct ivpu_ipc_consumer *cons); |
| 98 | 98 | |
| 99 | +int ivpu_ipc_send(struct ivpu_device *vdev, struct ivpu_ipc_consumer *cons, | |
| 100 | + struct vpu_jsm_msg *req); | |
| 99 | 101 | int ivpu_ipc_receive(struct ivpu_device *vdev, struct ivpu_ipc_consumer *cons, |
| 100 | 102 | struct ivpu_ipc_hdr *ipc_buf, struct vpu_jsm_msg *jsm_msg, |
| 101 | 103 | unsigned long timeout_ms); |
| @@ -1,6 +1,6 @@ | ||
| 1 | 1 | // SPDX-License-Identifier: GPL-2.0-only |
| 2 | 2 | /* |
| 3 | − * Copyright (C) 2020-2023 Intel Corporation | |
| 3 | + * Copyright (C) 2020-2024 Intel Corporation | |
| 4 | 4 | */ |
| 5 | 5 | |
| 6 | 6 | #include <drm/drm_file.h> |
| @@ -12,11 +12,13 @@ · 5 unmodified lines | ||
| 12 | 12 | #include <uapi/drm/ivpu_accel.h> |
| 13 | 13 | |
| 14 | 14 | #include "ivpu_drv.h" |
| 15 | +#include "ivpu_fw.h" | |
| 15 | 16 | #include "ivpu_hw.h" |
| 16 | 17 | #include "ivpu_ipc.h" |
| 17 | 18 | #include "ivpu_job.h" |
| 18 | 19 | #include "ivpu_jsm_msg.h" |
| 19 | 20 | #include "ivpu_pm.h" |
| 21 | +#include "vpu_boot_api.h" | |
| 20 | 22 | |
| 21 | 23 | #define CMD_BUF_IDX 0 |
| 22 | 24 | #define JOB_ID_JOB_MASK GENMASK(7, 0) |
| @@ -25,14 +27,60 @@ · 2 unmodified lines | ||
| 25 | 27 | |
| 26 | 28 | static void ivpu_cmdq_ring_db(struct ivpu_device *vdev, struct ivpu_cmdq *cmdq) |
| 27 | 29 | { |
| 28 | − ivpu_hw_reg_db_set(vdev, cmdq->db_id); | |
| 30 | + ivpu_hw_db_set(vdev, cmdq->db_id); | |
| 29 | 31 | } |
| 30 | 32 | |
| 31 | −static struct ivpu_cmdq *ivpu_cmdq_alloc(struct ivpu_file_priv *file_priv, u16 engine) | |
| 33 | +static int ivpu_preemption_buffers_create(struct ivpu_device *vdev, | |
| 34 | + struct ivpu_file_priv *file_priv, struct ivpu_cmdq *cmdq) | |
| 35 | +{ | |
| 36 | + u64 primary_size = ALIGN(vdev->fw->primary_preempt_buf_size, PAGE_SIZE); | |
| 37 | + u64 secondary_size = ALIGN(vdev->fw->secondary_preempt_buf_size, PAGE_SIZE); | |
| 38 | + struct ivpu_addr_range range; | |
| 39 | + | |
| 40 | + if (vdev->hw->sched_mode != VPU_SCHEDULING_MODE_HW) | |
| 41 | + return 0; | |
| 42 | + | |
| 43 | + range.start = vdev->hw->ranges.user.end - (primary_size * IVPU_NUM_CMDQS_PER_CTX); | |
| 44 | + range.end = vdev->hw->ranges.user.end; | |
| 45 | + cmdq->primary_preempt_buf = ivpu_bo_create(vdev, &file_priv->ctx, &range, primary_size, | |
| 46 | + DRM_IVPU_BO_WC); | |
| 47 | + if (!cmdq->primary_preempt_buf) { | |
| 48 | + ivpu_err(vdev, "Failed to create primary preemption buffer\n"); | |
| 49 | + return -ENOMEM; | |
| 50 | + } | |
| 51 | + | |
| 52 | + range.start = vdev->hw->ranges.shave.end - (secondary_size * IVPU_NUM_CMDQS_PER_CTX); | |
| 53 | + range.end = vdev->hw->ranges.shave.end; | |
| 54 | + cmdq->secondary_preempt_buf = ivpu_bo_create(vdev, &file_priv->ctx, &range, secondary_size, | |
| 55 | + DRM_IVPU_BO_WC); | |
| 56 | + if (!cmdq->secondary_preempt_buf) { | |
| 57 | + ivpu_err(vdev, "Failed to create secondary preemption buffer\n"); | |
| 58 | + goto err_free_primary; | |
| 59 | + } | |
| 60 | + | |
| 61 | + return 0; | |
| 62 | + | |
| 63 | +err_free_primary: | |
| 64 | + ivpu_bo_free(cmdq->primary_preempt_buf); | |
| 65 | + return -ENOMEM; | |
| 66 | +} | |
| 67 | + | |
| 68 | +static void ivpu_preemption_buffers_free(struct ivpu_device *vdev, | |
| 69 | + struct ivpu_file_priv *file_priv, struct ivpu_cmdq *cmdq) | |
| 70 | +{ | |
| 71 | + if (vdev->hw->sched_mode != VPU_SCHEDULING_MODE_HW) | |
| 72 | + return; | |
| 73 | + | |
| 74 | + drm_WARN_ON(&vdev->drm, !cmdq->primary_preempt_buf); | |
| 75 | + drm_WARN_ON(&vdev->drm, !cmdq->secondary_preempt_buf); | |
| 76 | + ivpu_bo_free(cmdq->primary_preempt_buf); | |
| 77 | + ivpu_bo_free(cmdq->secondary_preempt_buf); | |
| 78 | +} | |
| 79 | + | |
| 80 | +static struct ivpu_cmdq *ivpu_cmdq_alloc(struct ivpu_file_priv *file_priv) | |
| 32 | 81 | { |
| 33 | 82 | struct xa_limit db_xa_limit = {.max = IVPU_MAX_DB, .min = IVPU_MIN_DB}; |
| 34 | 83 | struct ivpu_device *vdev = file_priv->vdev; |
| 35 | − struct vpu_job_queue_header *jobq_header; | |
| 36 | 84 | struct ivpu_cmdq *cmdq; |
| 37 | 85 | int ret; |
| 38 | 86 | |
| @@ -50,18 +98,14 @@ static struct ivpu_cmdq *ivpu_cmdq_alloc(struct ivpu_file_priv *file_priv, u16 e · 11 unmodified lines | ||
| 50 | 98 | if (!cmdq->mem) |
| 51 | 99 | goto err_erase_xa; |
| 52 | 100 | |
| 53 | − cmdq->entry_count = (u32)((ivpu_bo_size(cmdq->mem) - sizeof(struct vpu_job_queue_header)) / | |
| 54 | − sizeof(struct vpu_job_queue_entry)); | |
| 55 | − | |
| 56 | − cmdq->jobq = (struct vpu_job_queue *)ivpu_bo_vaddr(cmdq->mem); | |
| 57 | − jobq_header = &cmdq->jobq->header; | |
| 58 | − jobq_header->engine_idx = engine; | |
| 59 | − jobq_header->head = 0; | |
| 60 | − jobq_header->tail = 0; | |
| 61 | − wmb(); /* Flush WC buffer for jobq->header */ | |
| 101 | + ret = ivpu_preemption_buffers_create(vdev, file_priv, cmdq); | |
| 102 | + if (ret) | |
| 103 | + goto err_free_cmdq_mem; | |
| 62 | 104 | |
| 63 | 105 | return cmdq; |
| 64 | 106 | |
| 107 | +err_free_cmdq_mem: | |
| 108 | + ivpu_bo_free(cmdq->mem); | |
| 65 | 109 | err_erase_xa: |
| 66 | 110 | xa_erase(&vdev->db_xa, cmdq->db_id); |
| 67 | 111 | err_free_cmdq: |
| @@ -74,92 +118,183 @@ static void ivpu_cmdq_free(struct ivpu_file_priv *file_priv, struct ivpu_cmdq *c · 6 unmodified lines | ||
| 74 | 118 | if (!cmdq) |
| 75 | 119 | return; |
| 76 | 120 | |
| 121 | + ivpu_preemption_buffers_free(file_priv->vdev, file_priv, cmdq); | |
| 77 | 122 | ivpu_bo_free(cmdq->mem); |
| 78 | 123 | xa_erase(&file_priv->vdev->db_xa, cmdq->db_id); |
| 79 | 124 | kfree(cmdq); |
| 80 | 125 | } |
| 81 | 126 | |
| 82 | −static struct ivpu_cmdq *ivpu_cmdq_acquire(struct ivpu_file_priv *file_priv, u16 engine) | |
| 127 | +static int ivpu_hws_cmdq_init(struct ivpu_file_priv *file_priv, struct ivpu_cmdq *cmdq, u16 engine, | |
| 128 | + u8 priority) | |
| 83 | 129 | { |
| 84 | 130 | struct ivpu_device *vdev = file_priv->vdev; |
| 85 | − struct ivpu_cmdq *cmdq = file_priv->cmdq[engine]; | |
| 131 | + int ret; | |
| 132 | + | |
| 133 | + ret = ivpu_jsm_hws_create_cmdq(vdev, file_priv->ctx.id, file_priv->ctx.id, cmdq->db_id, | |
| 134 | + task_pid_nr(current), engine, | |
| 135 | + cmdq->mem->vpu_addr, ivpu_bo_size(cmdq->mem)); | |
| 136 | + if (ret) | |
| 137 | + return ret; | |
| 138 | + | |
| 139 | + ret = ivpu_jsm_hws_set_context_sched_properties(vdev, file_priv->ctx.id, cmdq->db_id, | |
| 140 | + priority); | |
| 141 | + if (ret) | |
| 142 | + return ret; | |
| 143 | + | |
| 144 | + return 0; | |
| 145 | +} | |
| 146 | + | |
| 147 | +static int ivpu_register_db(struct ivpu_file_priv *file_priv, struct ivpu_cmdq *cmdq) | |
| 148 | +{ | |
| 149 | + struct ivpu_device *vdev = file_priv->vdev; | |
| 150 | + int ret; | |
| 151 | + | |
| 152 | + if (vdev->hw->sched_mode == VPU_SCHEDULING_MODE_HW) | |
| 153 | + ret = ivpu_jsm_hws_register_db(vdev, file_priv->ctx.id, cmdq->db_id, cmdq->db_id, | |
| 154 | + cmdq->mem->vpu_addr, ivpu_bo_size(cmdq->mem)); | |
| 155 | + else | |
| 156 | + ret = ivpu_jsm_register_db(vdev, file_priv->ctx.id, cmdq->db_id, | |
| 157 | + cmdq->mem->vpu_addr, ivpu_bo_size(cmdq->mem)); | |
| 158 | + | |
| 159 | + if (!ret) | |
| 160 | + ivpu_dbg(vdev, JOB, "DB %d registered to ctx %d\n", cmdq->db_id, file_priv->ctx.id); | |
| 161 | + | |
| 162 | + return ret; | |
| 163 | +} | |
| 164 | + | |
| 165 | +static int | |
| 166 | +ivpu_cmdq_init(struct ivpu_file_priv *file_priv, struct ivpu_cmdq *cmdq, u16 engine, u8 priority) | |
| 167 | +{ | |
| 168 | + struct ivpu_device *vdev = file_priv->vdev; | |
| 169 | + struct vpu_job_queue_header *jobq_header; | |
| 170 | + int ret; | |
| 171 | + | |
| 172 | + lockdep_assert_held(&file_priv->lock); | |
| 173 | + | |
| 174 | + if (cmdq->db_registered) | |
| 175 | + return 0; | |
| 176 | + | |
| 177 | + cmdq->entry_count = (u32)((ivpu_bo_size(cmdq->mem) - sizeof(struct vpu_job_queue_header)) / | |
| 178 | + sizeof(struct vpu_job_queue_entry)); | |
| 179 | + | |
| 180 | + cmdq->jobq = (struct vpu_job_queue *)ivpu_bo_vaddr(cmdq->mem); | |
| 181 | + jobq_header = &cmdq->jobq->header; | |
| 182 | + jobq_header->engine_idx = engine; | |
| 183 | + jobq_header->head = 0; | |
| 184 | + jobq_header->tail = 0; | |
| 185 | + wmb(); /* Flush WC buffer for jobq->header */ | |
| 186 | + | |
| 187 | + if (vdev->hw->sched_mode == VPU_SCHEDULING_MODE_HW) { | |
| 188 | + ret = ivpu_hws_cmdq_init(file_priv, cmdq, engine, priority); | |
| 189 | + if (ret) | |
| 190 | + return ret; | |
| 191 | + } | |
| 192 | + | |
| 193 | + ret = ivpu_register_db(file_priv, cmdq); | |
| 194 | + if (ret) | |
| 195 | + return ret; | |
| 196 | + | |
| 197 | + cmdq->db_registered = true; | |
| 198 | + | |
| 199 | + return 0; | |
| 200 | +} | |
| 201 | + | |
| 202 | +static int ivpu_cmdq_fini(struct ivpu_file_priv *file_priv, struct ivpu_cmdq *cmdq) | |
| 203 | +{ | |
| 204 | + struct ivpu_device *vdev = file_priv->vdev; | |
| 205 | + int ret; | |
| 206 | + | |
| 207 | + lockdep_assert_held(&file_priv->lock); | |
| 208 | + | |
| 209 | + if (!cmdq->db_registered) | |
| 210 | + return 0; | |
| 211 | + | |
| 212 | + cmdq->db_registered = false; | |
| 213 | + | |
| 214 | + if (vdev->hw->sched_mode == VPU_SCHEDULING_MODE_HW) { | |
| 215 | + ret = ivpu_jsm_hws_destroy_cmdq(vdev, file_priv->ctx.id, cmdq->db_id); | |
| 216 | + if (!ret) | |
| 217 | + ivpu_dbg(vdev, JOB, "Command queue %d destroyed\n", cmdq->db_id); | |
| 218 | + } | |
| 219 | + | |
| 220 | + ret = ivpu_jsm_unregister_db(vdev, cmdq->db_id); | |
| 221 | + if (!ret) | |
| 222 | + ivpu_dbg(vdev, JOB, "DB %d unregistered\n", cmdq->db_id); | |
| 223 | + | |
| 224 | + return 0; | |
| 225 | +} | |
| 226 | + | |
| 227 | +static struct ivpu_cmdq *ivpu_cmdq_acquire(struct ivpu_file_priv *file_priv, u16 engine, | |
| 228 | + u8 priority) | |
| 229 | +{ | |
| 230 | + int cmdq_idx = IVPU_CMDQ_INDEX(engine, priority); | |
| 231 | + struct ivpu_cmdq *cmdq = file_priv->cmdq[cmdq_idx]; | |
| 86 | 232 | int ret; |
| 87 | 233 | |
| 88 | 234 | lockdep_assert_held(&file_priv->lock); |
| 89 | 235 | |
| 90 | 236 | if (!cmdq) { |
| 91 | − cmdq = ivpu_cmdq_alloc(file_priv, engine); | |
| 237 | + cmdq = ivpu_cmdq_alloc(file_priv); | |
| 92 | 238 | if (!cmdq) |
| 93 | 239 | return NULL; |
| 94 | − file_priv->cmdq[engine] = cmdq; | |
| 240 | + file_priv->cmdq[cmdq_idx] = cmdq; | |
| 95 | 241 | } |
| 96 | 242 | |
| 97 | − if (cmdq->db_registered) | |
| 98 | − return cmdq; | |
| 99 | − | |
| 100 | − ret = ivpu_jsm_register_db(vdev, file_priv->ctx.id, cmdq->db_id, | |
| 101 | − cmdq->mem->vpu_addr, ivpu_bo_size(cmdq->mem)); | |
| 243 | + ret = ivpu_cmdq_init(file_priv, cmdq, engine, priority); | |
| 102 | 244 | if (ret) |
| 103 | 245 | return NULL; |
| 104 | 246 | |
| 105 | − cmdq->db_registered = true; | |
| 106 | − | |
| 107 | 247 | return cmdq; |
| 108 | 248 | } |
| 109 | 249 | |
| 110 | −static void ivpu_cmdq_release_locked(struct ivpu_file_priv *file_priv, u16 engine) | |
| 250 | +static void ivpu_cmdq_release_locked(struct ivpu_file_priv *file_priv, u16 engine, u8 priority) | |
| 111 | 251 | { |
| 112 | − struct ivpu_cmdq *cmdq = file_priv->cmdq[engine]; | |
| 252 | + int cmdq_idx = IVPU_CMDQ_INDEX(engine, priority); | |
| 253 | + struct ivpu_cmdq *cmdq = file_priv->cmdq[cmdq_idx]; | |
| 113 | 254 | |
| 114 | 255 | lockdep_assert_held(&file_priv->lock); |
| 115 | 256 | |
| 116 | 257 | if (cmdq) { |
| 117 | − file_priv->cmdq[engine] = NULL; | |
| 118 | − if (cmdq->db_registered) | |
| 119 | − ivpu_jsm_unregister_db(file_priv->vdev, cmdq->db_id); | |
| 120 | − | |
| 258 | + file_priv->cmdq[cmdq_idx] = NULL; | |
| 259 | + ivpu_cmdq_fini(file_priv, cmdq); | |
| 121 | 260 | ivpu_cmdq_free(file_priv, cmdq); |
| 122 | 261 | } |
| 123 | 262 | } |
| 124 | 263 | |
| 125 | 264 | void ivpu_cmdq_release_all_locked(struct ivpu_file_priv *file_priv) |
| 126 | 265 | { |
| 127 | − int i; | |
| 266 | + u16 engine; | |
| 267 | + u8 priority; | |
| 128 | 268 | |
| 129 | 269 | lockdep_assert_held(&file_priv->lock); |
| 130 | 270 | |
| 131 | − for (i = 0; i < IVPU_NUM_ENGINES; i++) | |
| 132 | − ivpu_cmdq_release_locked(file_priv, i); | |
| 271 | + for (engine = 0; engine < IVPU_NUM_ENGINES; engine++) | |
| 272 | + for (priority = 0; priority < IVPU_NUM_PRIORITIES; priority++) | |
| 273 | + ivpu_cmdq_release_locked(file_priv, engine, priority); | |
| 133 | 274 | } |
| 134 | 275 | |
| 135 | 276 | /* |
| 136 | − * Mark the doorbell as unregistered and reset job queue pointers. | |
| 277 | + * Mark the doorbell as unregistered | |
| 137 | 278 | * This function needs to be called when the VPU hardware is restarted |
| 138 | 279 | * and FW loses job queue state. The next time job queue is used it |
| 139 | 280 | * will be registered again. |
| 140 | 281 | */ |
| 141 | −static void ivpu_cmdq_reset_locked(struct ivpu_file_priv *file_priv, u16 engine) | |
| 142 | −{ | |
| 143 | − struct ivpu_cmdq *cmdq = file_priv->cmdq[engine]; | |
| 144 | − | |
| 145 | − lockdep_assert_held(&file_priv->lock); | |
| 146 | − | |
| 147 | − if (cmdq) { | |
| 148 | − cmdq->db_registered = false; | |
| 149 | − cmdq->jobq->header.head = 0; | |
| 150 | − cmdq->jobq->header.tail = 0; | |
| 151 | − wmb(); /* Flush WC buffer for jobq header */ | |
| 152 | − } | |
| 153 | −} | |
| 154 | − | |
| 155 | −static void ivpu_cmdq_reset_all(struct ivpu_file_priv *file_priv) | |
| 282 | +static void ivpu_cmdq_reset(struct ivpu_file_priv *file_priv) | |
| 156 | 283 | { |
| 157 | − int i; | |
| 284 | + u16 engine; | |
| 285 | + u8 priority; | |
| 158 | 286 | |
| 159 | 287 | mutex_lock(&file_priv->lock); |
| 160 | 288 | |
| 161 | − for (i = 0; i < IVPU_NUM_ENGINES; i++) | |
| 162 | − ivpu_cmdq_reset_locked(file_priv, i); | |
| 289 | + for (engine = 0; engine < IVPU_NUM_ENGINES; engine++) { | |
| 290 | + for (priority = 0; priority < IVPU_NUM_PRIORITIES; priority++) { | |
| 291 | + int cmdq_idx = IVPU_CMDQ_INDEX(engine, priority); | |
| 292 | + struct ivpu_cmdq *cmdq = file_priv->cmdq[cmdq_idx]; | |
| 293 | + | |
| 294 | + if (cmdq) | |
| 295 | + cmdq->db_registered = false; | |
| 296 | + } | |
| 297 | + } | |
| 163 | 298 | |
| 164 | 299 | mutex_unlock(&file_priv->lock); |
| 165 | 300 | } |
| @@ -172,10 +307,36 @@ void ivpu_cmdq_reset_all_contexts(struct ivpu_device *vdev) · 6 unmodified lines | ||
| 172 | 307 | mutex_lock(&vdev->context_list_lock); |
| 173 | 308 | |
| 174 | 309 | xa_for_each(&vdev->context_xa, ctx_id, file_priv) |
| 175 | − ivpu_cmdq_reset_all(file_priv); | |
| 310 | + ivpu_cmdq_reset(file_priv); | |
| 176 | 311 | |
| 177 | 312 | mutex_unlock(&vdev->context_list_lock); |
| 313 | +} | |
| 314 | + | |
| 315 | +static void ivpu_cmdq_fini_all(struct ivpu_file_priv *file_priv) | |
| 316 | +{ | |
| 317 | + u16 engine; | |
| 318 | + u8 priority; | |
| 319 | + | |
| 320 | + for (engine = 0; engine < IVPU_NUM_ENGINES; engine++) { | |
| 321 | + for (priority = 0; priority < IVPU_NUM_PRIORITIES; priority++) { | |
| 322 | + int cmdq_idx = IVPU_CMDQ_INDEX(engine, priority); | |
| 323 | + | |
| 324 | + if (file_priv->cmdq[cmdq_idx]) | |
| 325 | + ivpu_cmdq_fini(file_priv, file_priv->cmdq[cmdq_idx]); | |
| 326 | + } | |
| 327 | + } | |
| 328 | +} | |
| 178 | 329 | |
| 330 | +void ivpu_context_abort_locked(struct ivpu_file_priv *file_priv) | |
| 331 | +{ | |
| 332 | + struct ivpu_device *vdev = file_priv->vdev; | |
| 333 | + | |
| 334 | + lockdep_assert_held(&file_priv->lock); | |
| 335 | + | |
| 336 | + ivpu_cmdq_fini_all(file_priv); | |
| 337 | + | |
| 338 | + if (vdev->hw->sched_mode == VPU_SCHEDULING_MODE_OS) | |
| 339 | + ivpu_jsm_context_release(vdev, file_priv->ctx.id); | |
| 179 | 340 | } |
| 180 | 341 | |
| 181 | 342 | static int ivpu_cmdq_push_job(struct ivpu_cmdq *cmdq, struct ivpu_job *job) |
| @@ -199,6 +360,15 @@ static int ivpu_cmdq_push_job(struct ivpu_cmdq *cmdq, struct ivpu_job *job) · 17 unmodified lines | ||
| 199 | 360 | entry->flags = 0; |
| 200 | 361 | if (unlikely(ivpu_test_mode & IVPU_TEST_MODE_NULL_SUBMISSION)) |
| 201 | 362 | entry->flags = VPU_JOB_FLAGS_NULL_SUBMISSION_MASK; |
| 363 | + | |
| 364 | + if (vdev->hw->sched_mode == VPU_SCHEDULING_MODE_HW && | |
| 365 | + (unlikely(!(ivpu_test_mode & IVPU_TEST_MODE_PREEMPTION_DISABLE)))) { | |
| 366 | + entry->primary_preempt_buf_addr = cmdq->primary_preempt_buf->vpu_addr; | |
| 367 | + entry->primary_preempt_buf_size = ivpu_bo_size(cmdq->primary_preempt_buf); | |
| 368 | + entry->secondary_preempt_buf_addr = cmdq->secondary_preempt_buf->vpu_addr; | |
| 369 | + entry->secondary_preempt_buf_size = ivpu_bo_size(cmdq->secondary_preempt_buf); | |
| 370 | + } | |
| 371 | + | |
| 202 | 372 | wmb(); /* Ensure that tail is updated after filling entry */ |
| 203 | 373 | header->tail = next_entry; |
| 204 | 374 | wmb(); /* Flush WC buffer for jobq header */ |
| @@ -295,11 +465,28 @@ err_free_job: · 90 unmodified lines | ||
| 295 | 465 | return NULL; |
| 296 | 466 | } |
| 297 | 467 | |
| 468 | +static struct ivpu_job *ivpu_job_remove_from_submitted_jobs(struct ivpu_device *vdev, u32 job_id) | |
| 469 | +{ | |
| 470 | + struct ivpu_job *job; | |
| 471 | + | |
| 472 | + xa_lock(&vdev->submitted_jobs_xa); | |
| 473 | + job = __xa_erase(&vdev->submitted_jobs_xa, job_id); | |
| 474 | + | |
| 475 | + if (xa_empty(&vdev->submitted_jobs_xa) && job) { | |
| 476 | + vdev->busy_time = ktime_add(ktime_sub(ktime_get(), vdev->busy_start_ts), | |
| 477 | + vdev->busy_time); | |
| 478 | + } | |
| 479 | + | |
| 480 | + xa_unlock(&vdev->submitted_jobs_xa); | |
| 481 | + | |
| 482 | + return job; | |
| 483 | +} | |
| 484 | + | |
| 298 | 485 | static int ivpu_job_signal_and_destroy(struct ivpu_device *vdev, u32 job_id, u32 job_status) |
| 299 | 486 | { |
| 300 | 487 | struct ivpu_job *job; |
| 301 | 488 | |
| 302 | − job = xa_erase(&vdev->submitted_jobs_xa, job_id); | |
| 489 | + job = ivpu_job_remove_from_submitted_jobs(vdev, job_id); | |
| 303 | 490 | if (!job) |
| 304 | 491 | return -ENOENT; |
| 305 | 492 | |
| @@ -328,12 +515,13 @@ void ivpu_jobs_abort_all(struct ivpu_device *vdev) · 22 unmodified lines | ||
| 328 | 515 | ivpu_job_signal_and_destroy(vdev, id, DRM_IVPU_JOB_STATUS_ABORTED); |
| 329 | 516 | } |
| 330 | 517 | |
| 331 | −static int ivpu_job_submit(struct ivpu_job *job) | |
| 518 | +static int ivpu_job_submit(struct ivpu_job *job, u8 priority) | |
| 332 | 519 | { |
| 333 | 520 | struct ivpu_file_priv *file_priv = job->file_priv; |
| 334 | 521 | struct ivpu_device *vdev = job->vdev; |
| 335 | 522 | struct xa_limit job_id_range; |
| 336 | 523 | struct ivpu_cmdq *cmdq; |
| 524 | + bool is_first_job; | |
| 337 | 525 | int ret; |
| 338 | 526 | |
| 339 | 527 | ret = ivpu_rpm_get(vdev); |
| @@ -342,10 +530,10 @@ static int ivpu_job_submit(struct ivpu_job *job) · 2 unmodified lines | ||
| 342 | 530 | |
| 343 | 531 | mutex_lock(&file_priv->lock); |
| 344 | 532 | |
| 345 | − cmdq = ivpu_cmdq_acquire(job->file_priv, job->engine_idx); | |
| 533 | + cmdq = ivpu_cmdq_acquire(job->file_priv, job->engine_idx, priority); | |
| 346 | 534 | if (!cmdq) { |
| 347 | − ivpu_warn_ratelimited(vdev, "Failed get job queue, ctx %d engine %d\n", | |
| 348 | − file_priv->ctx.id, job->engine_idx); | |
| 535 | + ivpu_warn_ratelimited(vdev, "Failed to get job queue, ctx %d engine %d prio %d\n", | |
| 536 | + file_priv->ctx.id, job->engine_idx, priority); | |
| 349 | 537 | ret = -EINVAL; |
| 350 | 538 | goto err_unlock_file_priv; |
| 351 | 539 | } |
| @@ -354,6 +542,7 @@ static int ivpu_job_submit(struct ivpu_job *job) · 2 unmodified lines | ||
| 354 | 542 | job_id_range.max = job_id_range.min | JOB_ID_JOB_MASK; |
| 355 | 543 | |
| 356 | 544 | xa_lock(&vdev->submitted_jobs_xa); |
| 545 | + is_first_job = xa_empty(&vdev->submitted_jobs_xa); | |
| 357 | 546 | ret = __xa_alloc(&vdev->submitted_jobs_xa, &job->job_id, job, job_id_range, GFP_KERNEL); |
| 358 | 547 | if (ret) { |
| 359 | 548 | ivpu_dbg(vdev, JOB, "Too many active jobs in ctx %d\n", |
| @@ -373,10 +562,12 @@ static int ivpu_job_submit(struct ivpu_job *job) · 13 unmodified lines | ||
| 373 | 562 | wmb(); /* Flush WC buffer for jobq header */ |
| 374 | 563 | } else { |
| 375 | 564 | ivpu_cmdq_ring_db(vdev, cmdq); |
| 565 | + if (is_first_job) | |
| 566 | + vdev->busy_start_ts = ktime_get(); | |
| 376 | 567 | } |
| 377 | 568 | |
| 378 | − ivpu_dbg(vdev, JOB, "Job submitted: id %3u ctx %2d engine %d addr 0x%llx next %d\n", | |
| 379 | − job->job_id, file_priv->ctx.id, job->engine_idx, | |
| 569 | + ivpu_dbg(vdev, JOB, "Job submitted: id %3u ctx %2d engine %d prio %d addr 0x%llx next %d\n", | |
| 570 | + job->job_id, file_priv->ctx.id, job->engine_idx, priority, | |
| 380 | 571 | job->cmd_buf_vpu_addr, cmdq->jobq->header.tail); |
| 381 | 572 | |
| 382 | 573 | xa_unlock(&vdev->submitted_jobs_xa); |
| @@ -464,6 +655,14 @@ unlock_reservations: · 81 unmodified lines | ||
| 464 | 655 | return ret; |
| 465 | 656 | } |
| 466 | 657 | |
| 658 | +static inline u8 ivpu_job_to_hws_priority(struct ivpu_file_priv *file_priv, u8 priority) | |
| 659 | +{ | |
| 660 | + if (priority == DRM_IVPU_JOB_PRIORITY_DEFAULT) | |
| 661 | + return DRM_IVPU_JOB_PRIORITY_NORMAL; | |
| 662 | + | |
| 663 | + return priority - 1; | |
| 664 | +} | |
| 665 | + | |
| 467 | 666 | int ivpu_submit_ioctl(struct drm_device *dev, void *data, struct drm_file *file) |
| 468 | 667 | { |
| 469 | 668 | struct ivpu_file_priv *file_priv = file->driver_priv; |
| @@ -472,6 +671,7 @@ int ivpu_submit_ioctl(struct drm_device *dev, void *data, struct drm_file *file) · 2 unmodified lines | ||
| 472 | 671 | struct ivpu_job *job; |
| 473 | 672 | u32 *buf_handles; |
| 474 | 673 | int idx, ret; |
| 674 | + u8 priority; | |
| 475 | 675 | |
| 476 | 676 | if (params->engine > DRM_IVPU_ENGINE_COPY) |
| 477 | 677 | return -EINVAL; |
| @@ -525,8 +725,10 @@ int ivpu_submit_ioctl(struct drm_device *dev, void *data, struct drm_file *file) · 47 unmodified lines | ||
| 525 | 725 | goto err_destroy_job; |
| 526 | 726 | } |
| 527 | 727 | |
| 728 | + priority = ivpu_job_to_hws_priority(file_priv, params->priority); | |
| 729 | + | |
| 528 | 730 | down_read(&vdev->pm->reset_lock); |
| 529 | − ret = ivpu_job_submit(job); | |
| 731 | + ret = ivpu_job_submit(job, priority); | |
| 530 | 732 | up_read(&vdev->pm->reset_lock); |
| 531 | 733 | if (ret) |
| 532 | 734 | goto err_signal_fence; |
| @@ -1,6 +1,6 @@ | ||
| 1 | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
| 2 | 2 | /* |
| 3 | − * Copyright (C) 2020-2023 Intel Corporation | |
| 3 | + * Copyright (C) 2020-2024 Intel Corporation | |
| 4 | 4 | */ |
| 5 | 5 | |
| 6 | 6 | #ifndef __IVPU_JOB_H__ |
| @@ -24,6 +24,8 @@ struct ivpu_file_priv; · 17 unmodified lines | ||
| 24 | 24 | */ |
| 25 | 25 | struct ivpu_cmdq { |
| 26 | 26 | struct vpu_job_queue *jobq; |
| 27 | + struct ivpu_bo *primary_preempt_buf; | |
| 28 | + struct ivpu_bo *secondary_preempt_buf; | |
| 27 | 29 | struct ivpu_bo *mem; |
| 28 | 30 | u32 entry_count; |
| 29 | 31 | u32 db_id; |
| @@ -55,6 +57,8 @@ struct ivpu_job { · 25 unmodified lines | ||
| 55 | 57 | |
| 56 | 58 | int ivpu_submit_ioctl(struct drm_device *dev, void *data, struct drm_file *file); |
| 57 | 59 | |
| 60 | +void ivpu_context_abort_locked(struct ivpu_file_priv *file_priv); | |
| 61 | + | |
| 58 | 62 | void ivpu_cmdq_release_all_locked(struct ivpu_file_priv *file_priv); |
| 59 | 63 | void ivpu_cmdq_reset_all_contexts(struct ivpu_device *vdev); |
| 60 | 64 | |
| @@ -1,6 +1,6 @@ | ||
| 1 | 1 | // SPDX-License-Identifier: GPL-2.0-only |
| 2 | 2 | /* |
| 3 | − * Copyright (C) 2020-2023 Intel Corporation | |
| 3 | + * Copyright (C) 2020-2024 Intel Corporation | |
| 4 | 4 | */ |
| 5 | 5 | |
| 6 | 6 | #include "ivpu_drv.h" |
| @@ -103,14 +103,10 @@ int ivpu_jsm_register_db(struct ivpu_device *vdev, u32 ctx_id, u32 db_id, · 96 unmodified lines | ||
| 103 | 103 | |
| 104 | 104 | ret = ivpu_ipc_send_receive(vdev, &req, VPU_JSM_MSG_REGISTER_DB_DONE, &resp, |
| 105 | 105 | VPU_IPC_CHAN_ASYNC_CMD, vdev->timeout.jsm); |
| 106 | − if (ret) { | |
| 107 | − ivpu_err_ratelimited(vdev, "Failed to register doorbell %d: %d\n", db_id, ret); | |
| 108 | − return ret; | |
| 109 | − } | |
| 110 | − | |
| 111 | − ivpu_dbg(vdev, JSM, "Doorbell %d registered to context %d\n", db_id, ctx_id); | |
| 106 | + if (ret) | |
| 107 | + ivpu_err_ratelimited(vdev, "Failed to register doorbell %u: %d\n", db_id, ret); | |
| 112 | 108 | |
| 113 | − return 0; | |
| 109 | + return ret; | |
| 114 | 110 | } |
| 115 | 111 | |
| 116 | 112 | int ivpu_jsm_unregister_db(struct ivpu_device *vdev, u32 db_id) |
| @@ -123,14 +119,10 @@ int ivpu_jsm_unregister_db(struct ivpu_device *vdev, u32 db_id) · 6 unmodified lines | ||
| 123 | 119 | |
| 124 | 120 | ret = ivpu_ipc_send_receive(vdev, &req, VPU_JSM_MSG_UNREGISTER_DB_DONE, &resp, |
| 125 | 121 | VPU_IPC_CHAN_ASYNC_CMD, vdev->timeout.jsm); |
| 126 | − if (ret) { | |
| 127 | − ivpu_warn_ratelimited(vdev, "Failed to unregister doorbell %d: %d\n", db_id, ret); | |
| 128 | − return ret; | |
| 129 | − } | |
| 130 | − | |
| 131 | − ivpu_dbg(vdev, JSM, "Doorbell %d unregistered\n", db_id); | |
| 122 | + if (ret) | |
| 123 | + ivpu_warn_ratelimited(vdev, "Failed to unregister doorbell %u: %d\n", db_id, ret); | |
| 132 | 124 | |
| 133 | − return 0; | |
| 125 | + return ret; | |
| 134 | 126 | } |
| 135 | 127 | |
| 136 | 128 | int ivpu_jsm_get_heartbeat(struct ivpu_device *vdev, u32 engine, u64 *heartbeat) |
| @@ -255,11 +247,16 @@ int ivpu_jsm_context_release(struct ivpu_device *vdev, u32 host_ssid) · 118 unmodified lines | ||
| 255 | 247 | { |
| 256 | 248 | struct vpu_jsm_msg req = { .type = VPU_JSM_MSG_SSID_RELEASE }; |
| 257 | 249 | struct vpu_jsm_msg resp; |
| 250 | + int ret; | |
| 258 | 251 | |
| 259 | 252 | req.payload.ssid_release.host_ssid = host_ssid; |
| 260 | 253 | |
| 261 | − return ivpu_ipc_send_receive(vdev, &req, VPU_JSM_MSG_SSID_RELEASE_DONE, &resp, | |
| 262 | − VPU_IPC_CHAN_ASYNC_CMD, vdev->timeout.jsm); | |
| 254 | + ret = ivpu_ipc_send_receive(vdev, &req, VPU_JSM_MSG_SSID_RELEASE_DONE, &resp, | |
| 255 | + VPU_IPC_CHAN_ASYNC_CMD, vdev->timeout.jsm); | |
| 256 | + if (ret) | |
| 257 | + ivpu_warn_ratelimited(vdev, "Failed to release context: %d\n", ret); | |
| 258 | + | |
| 259 | + return ret; | |
| 263 | 260 | } |
| 264 | 261 | |
| 265 | 262 | int ivpu_jsm_pwr_d0i3_enter(struct ivpu_device *vdev) |
| @@ -281,3 +278,283 @@ int ivpu_jsm_pwr_d0i3_enter(struct ivpu_device *vdev) · 15 unmodified lines | ||
| 281 | 278 | |
| 282 | 279 | return ivpu_hw_wait_for_idle(vdev); |
| 283 | 280 | } |
| 281 | + | |
| 282 | +int ivpu_jsm_hws_create_cmdq(struct ivpu_device *vdev, u32 ctx_id, u32 cmdq_group, u32 cmdq_id, | |
| 283 | + u32 pid, u32 engine, u64 cmdq_base, u32 cmdq_size) | |
| 284 | +{ | |
| 285 | + struct vpu_jsm_msg req = { .type = VPU_JSM_MSG_CREATE_CMD_QUEUE }; | |
| 286 | + struct vpu_jsm_msg resp; | |
| 287 | + int ret; | |
| 288 | + | |
| 289 | + req.payload.hws_create_cmdq.host_ssid = ctx_id; | |
| 290 | + req.payload.hws_create_cmdq.process_id = pid; | |
| 291 | + req.payload.hws_create_cmdq.engine_idx = engine; | |
| 292 | + req.payload.hws_create_cmdq.cmdq_group = cmdq_group; | |
| 293 | + req.payload.hws_create_cmdq.cmdq_id = cmdq_id; | |
| 294 | + req.payload.hws_create_cmdq.cmdq_base = cmdq_base; | |
| 295 | + req.payload.hws_create_cmdq.cmdq_size = cmdq_size; | |
| 296 | + | |
| 297 | + ret = ivpu_ipc_send_receive(vdev, &req, VPU_JSM_MSG_CREATE_CMD_QUEUE_RSP, &resp, | |
| 298 | + VPU_IPC_CHAN_ASYNC_CMD, vdev->timeout.jsm); | |
| 299 | + if (ret) | |
| 300 | + ivpu_warn_ratelimited(vdev, "Failed to create command queue: %d\n", ret); | |
| 301 | + | |
| 302 | + return ret; | |
| 303 | +} | |
| 304 | + | |
| 305 | +int ivpu_jsm_hws_destroy_cmdq(struct ivpu_device *vdev, u32 ctx_id, u32 cmdq_id) | |
| 306 | +{ | |
| 307 | + struct vpu_jsm_msg req = { .type = VPU_JSM_MSG_DESTROY_CMD_QUEUE }; | |
| 308 | + struct vpu_jsm_msg resp; | |
| 309 | + int ret; | |
| 310 | + | |
| 311 | + req.payload.hws_destroy_cmdq.host_ssid = ctx_id; | |
| 312 | + req.payload.hws_destroy_cmdq.cmdq_id = cmdq_id; | |
| 313 | + | |
| 314 | + ret = ivpu_ipc_send_receive(vdev, &req, VPU_JSM_MSG_DESTROY_CMD_QUEUE_RSP, &resp, | |
| 315 | + VPU_IPC_CHAN_ASYNC_CMD, vdev->timeout.jsm); | |
| 316 | + if (ret) | |
| 317 | + ivpu_warn_ratelimited(vdev, "Failed to destroy command queue: %d\n", ret); | |
| 318 | + | |
| 319 | + return ret; | |
| 320 | +} | |
| 321 | + | |
| 322 | +int ivpu_jsm_hws_register_db(struct ivpu_device *vdev, u32 ctx_id, u32 cmdq_id, u32 db_id, | |
| 323 | + u64 cmdq_base, u32 cmdq_size) | |
| 324 | +{ | |
| 325 | + struct vpu_jsm_msg req = { .type = VPU_JSM_MSG_HWS_REGISTER_DB }; | |
| 326 | + struct vpu_jsm_msg resp; | |
| 327 | + int ret = 0; | |
| 328 | + | |
| 329 | + req.payload.hws_register_db.db_id = db_id; | |
| 330 | + req.payload.hws_register_db.host_ssid = ctx_id; | |
| 331 | + req.payload.hws_register_db.cmdq_id = cmdq_id; | |
| 332 | + req.payload.hws_register_db.cmdq_base = cmdq_base; | |
| 333 | + req.payload.hws_register_db.cmdq_size = cmdq_size; | |
| 334 | + | |
| 335 | + ret = ivpu_ipc_send_receive(vdev, &req, VPU_JSM_MSG_REGISTER_DB_DONE, &resp, | |
| 336 | + VPU_IPC_CHAN_ASYNC_CMD, vdev->timeout.jsm); | |
| 337 | + if (ret) | |
| 338 | + ivpu_err_ratelimited(vdev, "Failed to register doorbell %u: %d\n", db_id, ret); | |
| 339 | + | |
| 340 | + return ret; | |
| 341 | +} | |
| 342 | + | |
| 343 | +int ivpu_jsm_hws_resume_engine(struct ivpu_device *vdev, u32 engine) | |
| 344 | +{ | |
| 345 | + struct vpu_jsm_msg req = { .type = VPU_JSM_MSG_HWS_ENGINE_RESUME }; | |
| 346 | + struct vpu_jsm_msg resp; | |
| 347 | + int ret; | |
| 348 | + | |
| 349 | + if (engine >= VPU_ENGINE_NB) | |
| 350 | + return -EINVAL; | |
| 351 | + | |
| 352 | + req.payload.hws_resume_engine.engine_idx = engine; | |
| 353 | + | |
| 354 | + ret = ivpu_ipc_send_receive(vdev, &req, VPU_JSM_MSG_HWS_RESUME_ENGINE_DONE, &resp, | |
| 355 | + VPU_IPC_CHAN_ASYNC_CMD, vdev->timeout.jsm); | |
| 356 | + if (ret) | |
| 357 | + ivpu_err_ratelimited(vdev, "Failed to resume engine %d: %d\n", engine, ret); | |
| 358 | + | |
| 359 | + return ret; | |
| 360 | +} | |
| 361 | + | |
| 362 | +int ivpu_jsm_hws_set_context_sched_properties(struct ivpu_device *vdev, u32 ctx_id, u32 cmdq_id, | |
| 363 | + u32 priority) | |
| 364 | +{ | |
| 365 | + struct vpu_jsm_msg req = { .type = VPU_JSM_MSG_SET_CONTEXT_SCHED_PROPERTIES }; | |
| 366 | + struct vpu_jsm_msg resp; | |
| 367 | + int ret; | |
| 368 | + | |
| 369 | + req.payload.hws_set_context_sched_properties.host_ssid = ctx_id; | |
| 370 | + req.payload.hws_set_context_sched_properties.cmdq_id = cmdq_id; | |
| 371 | + req.payload.hws_set_context_sched_properties.priority_band = priority; | |
| 372 | + req.payload.hws_set_context_sched_properties.realtime_priority_level = 0; | |
| 373 | + req.payload.hws_set_context_sched_properties.in_process_priority = 0; | |
| 374 | + req.payload.hws_set_context_sched_properties.context_quantum = 20000; | |
| 375 | + req.payload.hws_set_context_sched_properties.grace_period_same_priority = 10000; | |
| 376 | + req.payload.hws_set_context_sched_properties.grace_period_lower_priority = 0; | |
| 377 | + | |
| 378 | + ret = ivpu_ipc_send_receive(vdev, &req, VPU_JSM_MSG_SET_CONTEXT_SCHED_PROPERTIES_RSP, &resp, | |
| 379 | + VPU_IPC_CHAN_ASYNC_CMD, vdev->timeout.jsm); | |
| 380 | + if (ret) | |
| 381 | + ivpu_warn_ratelimited(vdev, "Failed to set context sched properties: %d\n", ret); | |
| 382 | + | |
| 383 | + return ret; | |
| 384 | +} | |
| 385 | + | |
| 386 | +int ivpu_jsm_hws_set_scheduling_log(struct ivpu_device *vdev, u32 engine_idx, u32 host_ssid, | |
| 387 | + u64 vpu_log_buffer_va) | |
| 388 | +{ | |
| 389 | + struct vpu_jsm_msg req = { .type = VPU_JSM_MSG_HWS_SET_SCHEDULING_LOG }; | |
| 390 | + struct vpu_jsm_msg resp; | |
| 391 | + int ret; | |
| 392 | + | |
| 393 | + req.payload.hws_set_scheduling_log.engine_idx = engine_idx; | |
| 394 | + req.payload.hws_set_scheduling_log.host_ssid = host_ssid; | |
| 395 | + req.payload.hws_set_scheduling_log.vpu_log_buffer_va = vpu_log_buffer_va; | |
| 396 | + req.payload.hws_set_scheduling_log.notify_index = 0; | |
| 397 | + req.payload.hws_set_scheduling_log.enable_extra_events = | |
| 398 | + ivpu_test_mode & IVPU_TEST_MODE_HWS_EXTRA_EVENTS; | |
| 399 | + | |
| 400 | + ret = ivpu_ipc_send_receive(vdev, &req, VPU_JSM_MSG_HWS_SET_SCHEDULING_LOG_RSP, &resp, | |
| 401 | + VPU_IPC_CHAN_ASYNC_CMD, vdev->timeout.jsm); | |
| 402 | + if (ret) | |
| 403 | + ivpu_warn_ratelimited(vdev, "Failed to set scheduling log: %d\n", ret); | |
| 404 | + | |
| 405 | + return ret; | |
| 406 | +} | |
| 407 | + | |
| 408 | +int ivpu_jsm_hws_setup_priority_bands(struct ivpu_device *vdev) | |
| 409 | +{ | |
| 410 | + struct vpu_jsm_msg req = { .type = VPU_JSM_MSG_SET_PRIORITY_BAND_SETUP }; | |
| 411 | + struct vpu_jsm_msg resp; | |
| 412 | + int ret; | |
| 413 | + | |
| 414 | + /* Idle */ | |
| 415 | + req.payload.hws_priority_band_setup.grace_period[0] = 0; | |
| 416 | + req.payload.hws_priority_band_setup.process_grace_period[0] = 50000; | |
| 417 | + req.payload.hws_priority_band_setup.process_quantum[0] = 160000; | |
| 418 | + /* Normal */ | |
| 419 | + req.payload.hws_priority_band_setup.grace_period[1] = 50000; | |
| 420 | + req.payload.hws_priority_band_setup.process_grace_period[1] = 50000; | |
| 421 | + req.payload.hws_priority_band_setup.process_quantum[1] = 300000; | |
| 422 | + /* Focus */ | |
| 423 | + req.payload.hws_priority_band_setup.grace_period[2] = 50000; | |
| 424 | + req.payload.hws_priority_band_setup.process_grace_period[2] = 50000; | |
| 425 | + req.payload.hws_priority_band_setup.process_quantum[2] = 200000; | |
| 426 | + /* Realtime */ | |
| 427 | + req.payload.hws_priority_band_setup.grace_period[3] = 0; | |
| 428 | + req.payload.hws_priority_band_setup.process_grace_period[3] = 50000; | |
| 429 | + req.payload.hws_priority_band_setup.process_quantum[3] = 200000; | |
| 430 | + | |
| 431 | + req.payload.hws_priority_band_setup.normal_band_percentage = 10; | |
| 432 | + | |
| 433 | + ret = ivpu_ipc_send_receive_active(vdev, &req, VPU_JSM_MSG_SET_PRIORITY_BAND_SETUP_RSP, | |
| 434 | + &resp, VPU_IPC_CHAN_ASYNC_CMD, vdev->timeout.jsm); | |
| 435 | + if (ret) | |
| 436 | + ivpu_warn_ratelimited(vdev, "Failed to set priority bands: %d\n", ret); | |
| 437 | + | |
| 438 | + return ret; | |
| 439 | +} | |
| 440 | + | |
| 441 | +int ivpu_jsm_metric_streamer_start(struct ivpu_device *vdev, u64 metric_group_mask, | |
| 442 | + u64 sampling_rate, u64 buffer_addr, u64 buffer_size) | |
| 443 | +{ | |
| 444 | + struct vpu_jsm_msg req = { .type = VPU_JSM_MSG_METRIC_STREAMER_START }; | |
| 445 | + struct vpu_jsm_msg resp; | |
| 446 | + int ret; | |
| 447 | + | |
| 448 | + req.payload.metric_streamer_start.metric_group_mask = metric_group_mask; | |
| 449 | + req.payload.metric_streamer_start.sampling_rate = sampling_rate; | |
| 450 | + req.payload.metric_streamer_start.buffer_addr = buffer_addr; | |
| 451 | + req.payload.metric_streamer_start.buffer_size = buffer_size; | |
| 452 | + | |
| 453 | + ret = ivpu_ipc_send_receive(vdev, &req, VPU_JSM_MSG_METRIC_STREAMER_START_DONE, &resp, | |
| 454 | + VPU_IPC_CHAN_ASYNC_CMD, vdev->timeout.jsm); | |
| 455 | + if (ret) { | |
| 456 | + ivpu_warn_ratelimited(vdev, "Failed to start metric streamer: ret %d\n", ret); | |
| 457 | + return ret; | |
| 458 | + } | |
| 459 | + | |
| 460 | + return ret; | |
| 461 | +} | |
| 462 | + | |
| 463 | +int ivpu_jsm_metric_streamer_stop(struct ivpu_device *vdev, u64 metric_group_mask) | |
| 464 | +{ | |
| 465 | + struct vpu_jsm_msg req = { .type = VPU_JSM_MSG_METRIC_STREAMER_STOP }; | |
| 466 | + struct vpu_jsm_msg resp; | |
| 467 | + int ret; | |
| 468 | + | |
| 469 | + req.payload.metric_streamer_stop.metric_group_mask = metric_group_mask; | |
| 470 | + | |
| 471 | + ret = ivpu_ipc_send_receive(vdev, &req, VPU_JSM_MSG_METRIC_STREAMER_STOP_DONE, &resp, | |
| 472 | + VPU_IPC_CHAN_ASYNC_CMD, vdev->timeout.jsm); | |
| 473 | + if (ret) | |
| 474 | + ivpu_warn_ratelimited(vdev, "Failed to stop metric streamer: ret %d\n", ret); | |
| 475 | + | |
| 476 | + return ret; | |
| 477 | +} | |
| 478 | + | |
| 479 | +int ivpu_jsm_metric_streamer_update(struct ivpu_device *vdev, u64 metric_group_mask, | |
| 480 | + u64 buffer_addr, u64 buffer_size, u64 *bytes_written) | |
| 481 | +{ | |
| 482 | + struct vpu_jsm_msg req = { .type = VPU_JSM_MSG_METRIC_STREAMER_UPDATE }; | |
| 483 | + struct vpu_jsm_msg resp; | |
| 484 | + int ret; | |
| 485 | + | |
| 486 | + req.payload.metric_streamer_update.metric_group_mask = metric_group_mask; | |
| 487 | + req.payload.metric_streamer_update.buffer_addr = buffer_addr; | |
| 488 | + req.payload.metric_streamer_update.buffer_size = buffer_size; | |
| 489 | + | |
| 490 | + ret = ivpu_ipc_send_receive(vdev, &req, VPU_JSM_MSG_METRIC_STREAMER_UPDATE_DONE, &resp, | |
| 491 | + VPU_IPC_CHAN_ASYNC_CMD, vdev->timeout.jsm); | |
| 492 | + if (ret) { | |
| 493 | + ivpu_warn_ratelimited(vdev, "Failed to update metric streamer: ret %d\n", ret); | |
| 494 | + return ret; | |
| 495 | + } | |
| 496 | + | |
| 497 | + if (buffer_size && resp.payload.metric_streamer_done.bytes_written > buffer_size) { | |
| 498 | + ivpu_warn_ratelimited(vdev, "MS buffer overflow: bytes_written %#llx > buffer_size %#llx\n", | |
| 499 | + resp.payload.metric_streamer_done.bytes_written, buffer_size); | |
| 500 | + return -EOVERFLOW; | |
| 501 | + } | |
| 502 | + | |
| 503 | + *bytes_written = resp.payload.metric_streamer_done.bytes_written; | |
| 504 | + | |
| 505 | + return ret; | |
| 506 | +} | |
| 507 | + | |
| 508 | +int ivpu_jsm_metric_streamer_info(struct ivpu_device *vdev, u64 metric_group_mask, u64 buffer_addr, | |
| 509 | + u64 buffer_size, u32 *sample_size, u64 *info_size) | |
| 510 | +{ | |
| 511 | + struct vpu_jsm_msg req = { .type = VPU_JSM_MSG_METRIC_STREAMER_INFO }; | |
| 512 | + struct vpu_jsm_msg resp; | |
| 513 | + int ret; | |
| 514 | + | |
| 515 | + req.payload.metric_streamer_start.metric_group_mask = metric_group_mask; | |
| 516 | + req.payload.metric_streamer_start.buffer_addr = buffer_addr; | |
| 517 | + req.payload.metric_streamer_start.buffer_size = buffer_size; | |
| 518 | + | |
| 519 | + ret = ivpu_ipc_send_receive(vdev, &req, VPU_JSM_MSG_METRIC_STREAMER_INFO_DONE, &resp, | |
| 520 | + VPU_IPC_CHAN_ASYNC_CMD, vdev->timeout.jsm); | |
| 521 | + if (ret) { | |
| 522 | + ivpu_warn_ratelimited(vdev, "Failed to get metric streamer info: ret %d\n", ret); | |
| 523 | + return ret; | |
| 524 | + } | |
| 525 | + | |
| 526 | + if (!resp.payload.metric_streamer_done.sample_size) { | |
| 527 | + ivpu_warn_ratelimited(vdev, "Invalid sample size\n"); | |
| 528 | + return -EBADMSG; | |
| 529 | + } | |
| 530 | + | |
| 531 | + if (sample_size) | |
| 532 | + *sample_size = resp.payload.metric_streamer_done.sample_size; | |
| 533 | + if (info_size) | |
| 534 | + *info_size = resp.payload.metric_streamer_done.bytes_written; | |
| 535 | + | |
| 536 | + return ret; | |
| 537 | +} | |
| 538 | + | |
| 539 | +int ivpu_jsm_dct_enable(struct ivpu_device *vdev, u32 active_us, u32 inactive_us) | |
| 540 | +{ | |
| 541 | + struct vpu_jsm_msg req = { .type = VPU_JSM_MSG_DCT_ENABLE }; | |
| 542 | + struct vpu_jsm_msg resp; | |
| 543 | + | |
| 544 | + req.payload.pwr_dct_control.dct_active_us = active_us; | |
| 545 | + req.payload.pwr_dct_control.dct_inactive_us = inactive_us; | |
| 546 | + | |
| 547 | + return ivpu_ipc_send_receive_active(vdev, &req, VPU_JSM_MSG_DCT_ENABLE_DONE, | |
| 548 | + &resp, VPU_IPC_CHAN_ASYNC_CMD, | |
| 549 | + vdev->timeout.jsm); | |
| 550 | +} | |
| 551 | + | |
| 552 | +int ivpu_jsm_dct_disable(struct ivpu_device *vdev) | |
| 553 | +{ | |
| 554 | + struct vpu_jsm_msg req = { .type = VPU_JSM_MSG_DCT_DISABLE }; | |
| 555 | + struct vpu_jsm_msg resp; | |
| 556 | + | |
| 557 | + return ivpu_ipc_send_receive_active(vdev, &req, VPU_JSM_MSG_DCT_DISABLE_DONE, | |
| 558 | + &resp, VPU_IPC_CHAN_ASYNC_CMD, | |
| 559 | + vdev->timeout.jsm); | |
| 560 | +} | |
| @@ -1,6 +1,6 @@ | ||
| 1 | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
| 2 | 2 | /* |
| 3 | − * Copyright (C) 2020-2023 Intel Corporation | |
| 3 | + * Copyright (C) 2020-2024 Intel Corporation | |
| 4 | 4 | */ |
| 5 | 5 | |
| 6 | 6 | #ifndef __IVPU_JSM_MSG_H__ |
| @@ -23,4 +23,24 @@ int ivpu_jsm_trace_set_config(struct ivpu_device *vdev, u32 trace_level, u32 tra · 16 unmodified lines | ||
| 23 | 23 | u64 trace_hw_component_mask); |
| 24 | 24 | int ivpu_jsm_context_release(struct ivpu_device *vdev, u32 host_ssid); |
| 25 | 25 | int ivpu_jsm_pwr_d0i3_enter(struct ivpu_device *vdev); |
| 26 | +int ivpu_jsm_hws_create_cmdq(struct ivpu_device *vdev, u32 ctx_id, u32 cmdq_group, u32 cmdq_id, | |
| 27 | + u32 pid, u32 engine, u64 cmdq_base, u32 cmdq_size); | |
| 28 | +int ivpu_jsm_hws_destroy_cmdq(struct ivpu_device *vdev, u32 ctx_id, u32 cmdq_id); | |
| 29 | +int ivpu_jsm_hws_register_db(struct ivpu_device *vdev, u32 ctx_id, u32 cmdq_id, u32 db_id, | |
| 30 | + u64 cmdq_base, u32 cmdq_size); | |
| 31 | +int ivpu_jsm_hws_resume_engine(struct ivpu_device *vdev, u32 engine); | |
| 32 | +int ivpu_jsm_hws_set_context_sched_properties(struct ivpu_device *vdev, u32 ctx_id, u32 cmdq_id, | |
| 33 | + u32 priority); | |
| 34 | +int ivpu_jsm_hws_set_scheduling_log(struct ivpu_device *vdev, u32 engine_idx, u32 host_ssid, | |
| 35 | + u64 vpu_log_buffer_va); | |
| 36 | +int ivpu_jsm_hws_setup_priority_bands(struct ivpu_device *vdev); | |
| 37 | +int ivpu_jsm_metric_streamer_start(struct ivpu_device *vdev, u64 metric_group_mask, | |
| 38 | + u64 sampling_rate, u64 buffer_addr, u64 buffer_size); | |
| 39 | +int ivpu_jsm_metric_streamer_stop(struct ivpu_device *vdev, u64 metric_group_mask); | |
| 40 | +int ivpu_jsm_metric_streamer_update(struct ivpu_device *vdev, u64 metric_group_mask, | |
| 41 | + u64 buffer_addr, u64 buffer_size, u64 *bytes_written); | |
| 42 | +int ivpu_jsm_metric_streamer_info(struct ivpu_device *vdev, u64 metric_group_mask, u64 buffer_addr, | |
| 43 | + u64 buffer_size, u32 *sample_size, u64 *info_size); | |
| 44 | +int ivpu_jsm_dct_enable(struct ivpu_device *vdev, u32 active_us, u32 inactive_us); | |
| 45 | +int ivpu_jsm_dct_disable(struct ivpu_device *vdev); | |
| 26 | 46 | #endif |
| @@ -1,6 +1,6 @@ | ||
| 1 | 1 | // SPDX-License-Identifier: GPL-2.0-only |
| 2 | 2 | /* |
| 3 | − * Copyright (C) 2020-2023 Intel Corporation | |
| 3 | + * Copyright (C) 2020-2024 Intel Corporation | |
| 4 | 4 | */ |
| 5 | 5 | |
| 6 | 6 | #include <linux/circ_buf.h> |
| @@ -519,7 +519,8 @@ static int ivpu_mmu_cmdq_sync(struct ivpu_device *vdev) · 512 unmodified lines | ||
| 519 | 519 | if (ret) |
| 520 | 520 | return ret; |
| 521 | 521 | |
| 522 | − clflush_cache_range(q->base, IVPU_MMU_CMDQ_SIZE); | |
| 522 | + if (!ivpu_is_force_snoop_enabled(vdev)) | |
| 523 | + clflush_cache_range(q->base, IVPU_MMU_CMDQ_SIZE); | |
| 523 | 524 | REGV_WR32(IVPU_MMU_REG_CMDQ_PROD, q->prod); |
| 524 | 525 | |
| 525 | 526 | ret = ivpu_mmu_cmdq_wait_for_cons(vdev); |
| @@ -567,7 +568,8 @@ static int ivpu_mmu_reset(struct ivpu_device *vdev) · 41 unmodified lines | ||
| 567 | 568 | int ret; |
| 568 | 569 | |
| 569 | 570 | memset(mmu->cmdq.base, 0, IVPU_MMU_CMDQ_SIZE); |
| 570 | − clflush_cache_range(mmu->cmdq.base, IVPU_MMU_CMDQ_SIZE); | |
| 571 | + if (!ivpu_is_force_snoop_enabled(vdev)) | |
| 572 | + clflush_cache_range(mmu->cmdq.base, IVPU_MMU_CMDQ_SIZE); | |
| 571 | 573 | mmu->cmdq.prod = 0; |
| 572 | 574 | mmu->cmdq.cons = 0; |
| 573 | 575 | |
| @@ -661,7 +663,8 @@ static void ivpu_mmu_strtab_link_cd(struct ivpu_device *vdev, u32 sid) · 87 unmodified lines | ||
| 661 | 663 | WRITE_ONCE(entry[1], str[1]); |
| 662 | 664 | WRITE_ONCE(entry[0], str[0]); |
| 663 | 665 | |
| 664 | − clflush_cache_range(entry, IVPU_MMU_STRTAB_ENT_SIZE); | |
| 666 | + if (!ivpu_is_force_snoop_enabled(vdev)) | |
| 667 | + clflush_cache_range(entry, IVPU_MMU_STRTAB_ENT_SIZE); | |
| 665 | 668 | |
| 666 | 669 | ivpu_dbg(vdev, MMU, "STRTAB write entry (SSID=%u): 0x%llx, 0x%llx\n", sid, str[0], str[1]); |
| 667 | 670 | } |
| @@ -735,7 +738,8 @@ static int ivpu_mmu_cd_add(struct ivpu_device *vdev, u32 ssid, u64 cd_dma) · 67 unmodified lines | ||
| 735 | 738 | WRITE_ONCE(entry[3], cd[3]); |
| 736 | 739 | WRITE_ONCE(entry[0], cd[0]); |
| 737 | 740 | |
| 738 | − clflush_cache_range(entry, IVPU_MMU_CDTAB_ENT_SIZE); | |
| 741 | + if (!ivpu_is_force_snoop_enabled(vdev)) | |
| 742 | + clflush_cache_range(entry, IVPU_MMU_CDTAB_ENT_SIZE); | |
| 739 | 743 | |
| 740 | 744 | ivpu_dbg(vdev, MMU, "CDTAB %s entry (SSID=%u, dma=%pad): 0x%llx, 0x%llx, 0x%llx, 0x%llx\n", |
| 741 | 745 | cd_dma ? "write" : "clear", ssid, &cd_dma, cd[0], cd[1], cd[2], cd[3]); |
| @@ -874,8 +878,9 @@ static void ivpu_mmu_dump_event(struct ivpu_device *vdev, u32 *event) · 132 unmodified lines | ||
| 874 | 878 | u64 in_addr = ((u64)event[5]) << 32 | event[4]; |
| 875 | 879 | u32 sid = event[1]; |
| 876 | 880 | |
| 877 | − ivpu_err(vdev, "MMU EVTQ: 0x%x (%s) SSID: %d SID: %d, e[2] %08x, e[3] %08x, in addr: 0x%llx, fetch addr: 0x%llx\n", | |
| 878 | − op, ivpu_mmu_event_to_str(op), ssid, sid, event[2], event[3], in_addr, fetch_addr); | |
| 881 | + ivpu_err_ratelimited(vdev, "MMU EVTQ: 0x%x (%s) SSID: %d SID: %d, e[2] %08x, e[3] %08x, in addr: 0x%llx, fetch addr: 0x%llx\n", | |
| 882 | + op, ivpu_mmu_event_to_str(op), ssid, sid, | |
| 883 | + event[2], event[3], in_addr, fetch_addr); | |
| 879 | 884 | } |
| 880 | 885 | |
| 881 | 886 | static u32 *ivpu_mmu_get_event(struct ivpu_device *vdev) |
| @@ -911,6 +916,9 @@ void ivpu_mmu_irq_evtq_handler(struct ivpu_device *vdev) · 29 unmodified lines | ||
| 911 | 916 | ivpu_mmu_user_context_mark_invalid(vdev, ssid); |
| 912 | 917 | REGV_WR32(IVPU_MMU_REG_EVTQ_CONS_SEC, vdev->mmu->evtq.cons); |
| 913 | 918 | } |
| 919 | + | |
| 920 | + if (!kfifo_put(&vdev->hw->irq.fifo, IVPU_HW_IRQ_SRC_MMU_EVTQ)) | |
| 921 | + ivpu_err_ratelimited(vdev, "IRQ FIFO full\n"); | |
| 914 | 922 | } |
| 915 | 923 | |
| 916 | 924 | void ivpu_mmu_evtq_dump(struct ivpu_device *vdev) |
| @@ -24,6 +24,7 @@ · 23 unmodified lines | ||
| 24 | 24 | #define IVPU_MMU_ENTRY_FLAG_CONT BIT(52) |
| 25 | 25 | #define IVPU_MMU_ENTRY_FLAG_NG BIT(11) |
| 26 | 26 | #define IVPU_MMU_ENTRY_FLAG_AF BIT(10) |
| 27 | +#define IVPU_MMU_ENTRY_FLAG_RO BIT(7) | |
| 27 | 28 | #define IVPU_MMU_ENTRY_FLAG_USER BIT(6) |
| 28 | 29 | #define IVPU_MMU_ENTRY_FLAG_LLC_COHERENT BIT(2) |
| 29 | 30 | #define IVPU_MMU_ENTRY_FLAG_TYPE_PAGE BIT(1) |
| @@ -319,6 +320,91 @@ ivpu_mmu_context_map_pages(struct ivpu_device *vdev, struct ivpu_mmu_context *ct · 289 unmodified lines | ||
| 319 | 320 | return 0; |
| 320 | 321 | } |
| 321 | 322 | |
| 323 | +static void ivpu_mmu_context_set_page_ro(struct ivpu_device *vdev, struct ivpu_mmu_context *ctx, | |
| 324 | + u64 vpu_addr) | |
| 325 | +{ | |
| 326 | + int pgd_idx = FIELD_GET(IVPU_MMU_PGD_INDEX_MASK, vpu_addr); | |
| 327 | + int pud_idx = FIELD_GET(IVPU_MMU_PUD_INDEX_MASK, vpu_addr); | |
| 328 | + int pmd_idx = FIELD_GET(IVPU_MMU_PMD_INDEX_MASK, vpu_addr); | |
| 329 | + int pte_idx = FIELD_GET(IVPU_MMU_PTE_INDEX_MASK, vpu_addr); | |
| 330 | + | |
| 331 | + ctx->pgtable.pte_ptrs[pgd_idx][pud_idx][pmd_idx][pte_idx] |= IVPU_MMU_ENTRY_FLAG_RO; | |
| 332 | +} | |
| 333 | + | |
| 334 | +static void ivpu_mmu_context_split_page(struct ivpu_device *vdev, struct ivpu_mmu_context *ctx, | |
| 335 | + u64 vpu_addr) | |
| 336 | +{ | |
| 337 | + int pgd_idx = FIELD_GET(IVPU_MMU_PGD_INDEX_MASK, vpu_addr); | |
| 338 | + int pud_idx = FIELD_GET(IVPU_MMU_PUD_INDEX_MASK, vpu_addr); | |
| 339 | + int pmd_idx = FIELD_GET(IVPU_MMU_PMD_INDEX_MASK, vpu_addr); | |
| 340 | + int pte_idx = FIELD_GET(IVPU_MMU_PTE_INDEX_MASK, vpu_addr); | |
| 341 | + | |
| 342 | + ctx->pgtable.pte_ptrs[pgd_idx][pud_idx][pmd_idx][pte_idx] &= ~IVPU_MMU_ENTRY_FLAG_CONT; | |
| 343 | +} | |
| 344 | + | |
| 345 | +static void ivpu_mmu_context_split_64k_page(struct ivpu_device *vdev, struct ivpu_mmu_context *ctx, | |
| 346 | + u64 vpu_addr) | |
| 347 | +{ | |
| 348 | + u64 start = ALIGN_DOWN(vpu_addr, IVPU_MMU_CONT_PAGES_SIZE); | |
| 349 | + u64 end = ALIGN(vpu_addr, IVPU_MMU_CONT_PAGES_SIZE); | |
| 350 | + u64 offset = 0; | |
| 351 | + | |
| 352 | + ivpu_dbg(vdev, MMU_MAP, "Split 64K page ctx: %u vpu_addr: 0x%llx\n", ctx->id, vpu_addr); | |
| 353 | + | |
| 354 | + while (start + offset < end) { | |
| 355 | + ivpu_mmu_context_split_page(vdev, ctx, start + offset); | |
| 356 | + offset += IVPU_MMU_PAGE_SIZE; | |
| 357 | + } | |
| 358 | +} | |
| 359 | + | |
| 360 | +int | |
| 361 | +ivpu_mmu_context_set_pages_ro(struct ivpu_device *vdev, struct ivpu_mmu_context *ctx, u64 vpu_addr, | |
| 362 | + size_t size) | |
| 363 | +{ | |
| 364 | + u64 end = vpu_addr + size; | |
| 365 | + size_t size_left = size; | |
| 366 | + int ret; | |
| 367 | + | |
| 368 | + if (size == 0) | |
| 369 | + return 0; | |
| 370 | + | |
| 371 | + if (drm_WARN_ON(&vdev->drm, !IS_ALIGNED(vpu_addr | size, IVPU_MMU_PAGE_SIZE))) | |
| 372 | + return -EINVAL; | |
| 373 | + | |
| 374 | + mutex_lock(&ctx->lock); | |
| 375 | + | |
| 376 | + ivpu_dbg(vdev, MMU_MAP, "Set read-only pages ctx: %u vpu_addr: 0x%llx size: %lu\n", | |
| 377 | + ctx->id, vpu_addr, size); | |
| 378 | + | |
| 379 | + if (!ivpu_disable_mmu_cont_pages) { | |
| 380 | + /* Split 64K contiguous page at the beginning if needed */ | |
| 381 | + if (!IS_ALIGNED(vpu_addr, IVPU_MMU_CONT_PAGES_SIZE)) | |
| 382 | + ivpu_mmu_context_split_64k_page(vdev, ctx, vpu_addr); | |
| 383 | + | |
| 384 | + /* Split 64K contiguous page at the end if needed */ | |
| 385 | + if (!IS_ALIGNED(vpu_addr + size, IVPU_MMU_CONT_PAGES_SIZE)) | |
| 386 | + ivpu_mmu_context_split_64k_page(vdev, ctx, vpu_addr + size); | |
| 387 | + } | |
| 388 | + | |
| 389 | + while (size_left) { | |
| 390 | + if (vpu_addr < end) | |
| 391 | + ivpu_mmu_context_set_page_ro(vdev, ctx, vpu_addr); | |
| 392 | + | |
| 393 | + vpu_addr += IVPU_MMU_PAGE_SIZE; | |
| 394 | + size_left -= IVPU_MMU_PAGE_SIZE; | |
| 395 | + } | |
| 396 | + | |
| 397 | + /* Ensure page table modifications are flushed from wc buffers to memory */ | |
| 398 | + wmb(); | |
| 399 | + | |
| 400 | + mutex_unlock(&ctx->lock); | |
| 401 | + ret = ivpu_mmu_invalidate_tlb(vdev, ctx->id); | |
| 402 | + if (ret) | |
| 403 | + ivpu_err(vdev, "Failed to invalidate TLB for ctx %u: %d\n", ctx->id, ret); | |
| 404 | + | |
| 405 | + return 0; | |
| 406 | +} | |
| 407 | + | |
| 322 | 408 | static void ivpu_mmu_context_unmap_pages(struct ivpu_mmu_context *ctx, u64 vpu_addr, size_t size) |
| 323 | 409 | { |
| 324 | 410 | while (size) { |
| @@ -46,5 +46,7 @@ int ivpu_mmu_context_map_sgt(struct ivpu_device *vdev, struct ivpu_mmu_context * · 45 unmodified lines | ||
| 46 | 46 | u64 vpu_addr, struct sg_table *sgt, bool llc_coherent); |
| 47 | 47 | void ivpu_mmu_context_unmap_sgt(struct ivpu_device *vdev, struct ivpu_mmu_context *ctx, |
| 48 | 48 | u64 vpu_addr, struct sg_table *sgt); |
| 49 | +int ivpu_mmu_context_set_pages_ro(struct ivpu_device *vdev, struct ivpu_mmu_context *ctx, | |
| 50 | + u64 vpu_addr, size_t size); | |
| 49 | 51 | |
| 50 | 52 | #endif /* __IVPU_MMU_CONTEXT_H__ */ |
| @@ -0,0 +1,309 @@ | ||
| 1 | +// SPDX-License-Identifier: GPL-2.0-only OR MIT | |
| 2 | +/* | |
| 3 | + * Copyright (C) 2020-2024 Intel Corporation | |
| 4 | + */ | |
| 5 | + | |
| 6 | +#include <drm/drm_file.h> | |
| 7 | + | |
| 8 | +#include "ivpu_drv.h" | |
| 9 | +#include "ivpu_gem.h" | |
| 10 | +#include "ivpu_jsm_msg.h" | |
| 11 | +#include "ivpu_ms.h" | |
| 12 | +#include "ivpu_pm.h" | |
| 13 | + | |
| 14 | +#define MS_INFO_BUFFER_SIZE SZ_16K | |
| 15 | +#define MS_NUM_BUFFERS 2 | |
| 16 | +#define MS_READ_PERIOD_MULTIPLIER 2 | |
| 17 | +#define MS_MIN_SAMPLE_PERIOD_NS 1000000 | |
| 18 | + | |
| 19 | +static struct ivpu_ms_instance * | |
| 20 | +get_instance_by_mask(struct ivpu_file_priv *file_priv, u64 metric_mask) | |
| 21 | +{ | |
| 22 | + struct ivpu_ms_instance *ms; | |
| 23 | + | |
| 24 | + lockdep_assert_held(&file_priv->ms_lock); | |
| 25 | + | |
| 26 | + list_for_each_entry(ms, &file_priv->ms_instance_list, ms_instance_node) | |
| 27 | + if (ms->mask == metric_mask) | |
| 28 | + return ms; | |
| 29 | + | |
| 30 | + return NULL; | |
| 31 | +} | |
| 32 | + | |
| 33 | +int ivpu_ms_start_ioctl(struct drm_device *dev, void *data, struct drm_file *file) | |
| 34 | +{ | |
| 35 | + struct ivpu_file_priv *file_priv = file->driver_priv; | |
| 36 | + struct drm_ivpu_metric_streamer_start *args = data; | |
| 37 | + struct ivpu_device *vdev = file_priv->vdev; | |
| 38 | + struct ivpu_ms_instance *ms; | |
| 39 | + u64 single_buff_size; | |
| 40 | + u32 sample_size; | |
| 41 | + int ret; | |
| 42 | + | |
| 43 | + if (!args->metric_group_mask || !args->read_period_samples || | |
| 44 | + args->sampling_period_ns < MS_MIN_SAMPLE_PERIOD_NS) | |
| 45 | + return -EINVAL; | |
| 46 | + | |
| 47 | + mutex_lock(&file_priv->ms_lock); | |
| 48 | + | |
| 49 | + if (get_instance_by_mask(file_priv, args->metric_group_mask)) { | |
| 50 | + ivpu_err(vdev, "Instance already exists (mask %#llx)\n", args->metric_group_mask); | |
| 51 | + ret = -EALREADY; | |
| 52 | + goto unlock; | |
| 53 | + } | |
| 54 | + | |
| 55 | + ms = kzalloc(sizeof(*ms), GFP_KERNEL); | |
| 56 | + if (!ms) { | |
| 57 | + ret = -ENOMEM; | |
| 58 | + goto unlock; | |
| 59 | + } | |
| 60 | + | |
| 61 | + ms->mask = args->metric_group_mask; | |
| 62 | + | |
| 63 | + ret = ivpu_jsm_metric_streamer_info(vdev, ms->mask, 0, 0, &sample_size, NULL); | |
| 64 | + if (ret) | |
| 65 | + goto err_free_ms; | |
| 66 | + | |
| 67 | + single_buff_size = sample_size * | |
| 68 | + ((u64)args->read_period_samples * MS_READ_PERIOD_MULTIPLIER); | |
| 69 | + ms->bo = ivpu_bo_create_global(vdev, PAGE_ALIGN(single_buff_size * MS_NUM_BUFFERS), | |
| 70 | + DRM_IVPU_BO_CACHED | DRM_IVPU_BO_MAPPABLE); | |
| 71 | + if (!ms->bo) { | |
| 72 | + ivpu_err(vdev, "Failed to allocate MS buffer (size %llu)\n", single_buff_size); | |
| 73 | + ret = -ENOMEM; | |
| 74 | + goto err_free_ms; | |
| 75 | + } | |
| 76 | + | |
| 77 | + ms->buff_size = ivpu_bo_size(ms->bo) / MS_NUM_BUFFERS; | |
| 78 | + ms->active_buff_vpu_addr = ms->bo->vpu_addr; | |
| 79 | + ms->inactive_buff_vpu_addr = ms->bo->vpu_addr + ms->buff_size; | |
| 80 | + ms->active_buff_ptr = ivpu_bo_vaddr(ms->bo); | |
| 81 | + ms->inactive_buff_ptr = ivpu_bo_vaddr(ms->bo) + ms->buff_size; | |
| 82 | + | |
| 83 | + ret = ivpu_jsm_metric_streamer_start(vdev, ms->mask, args->sampling_period_ns, | |
| 84 | + ms->active_buff_vpu_addr, ms->buff_size); | |
| 85 | + if (ret) | |
| 86 | + goto err_free_bo; | |
| 87 | + | |
| 88 | + args->sample_size = sample_size; | |
| 89 | + args->max_data_size = ivpu_bo_size(ms->bo); | |
| 90 | + list_add_tail(&ms->ms_instance_node, &file_priv->ms_instance_list); | |
| 91 | + goto unlock; | |
| 92 | + | |
| 93 | +err_free_bo: | |
| 94 | + ivpu_bo_free(ms->bo); | |
| 95 | +err_free_ms: | |
| 96 | + kfree(ms); | |
| 97 | +unlock: | |
| 98 | + mutex_unlock(&file_priv->ms_lock); | |
| 99 | + return ret; | |
| 100 | +} | |
| 101 | + | |
| 102 | +static int | |
| 103 | +copy_leftover_bytes(struct ivpu_ms_instance *ms, | |
| 104 | + void __user *user_ptr, u64 user_size, u64 *user_bytes_copied) | |
| 105 | +{ | |
| 106 | + u64 copy_bytes; | |
| 107 | + | |
| 108 | + if (ms->leftover_bytes) { | |
| 109 | + copy_bytes = min(user_size - *user_bytes_copied, ms->leftover_bytes); | |
| 110 | + if (copy_to_user(user_ptr + *user_bytes_copied, ms->leftover_addr, copy_bytes)) | |
| 111 | + return -EFAULT; | |
| 112 | + | |
| 113 | + ms->leftover_bytes -= copy_bytes; | |
| 114 | + ms->leftover_addr += copy_bytes; | |
| 115 | + *user_bytes_copied += copy_bytes; | |
| 116 | + } | |
| 117 | + | |
| 118 | + return 0; | |
| 119 | +} | |
| 120 | + | |
| 121 | +static int | |
| 122 | +copy_samples_to_user(struct ivpu_device *vdev, struct ivpu_ms_instance *ms, | |
| 123 | + void __user *user_ptr, u64 user_size, u64 *user_bytes_copied) | |
| 124 | +{ | |
| 125 | + u64 bytes_written; | |
| 126 | + int ret; | |
| 127 | + | |
| 128 | + *user_bytes_copied = 0; | |
| 129 | + | |
| 130 | + ret = copy_leftover_bytes(ms, user_ptr, user_size, user_bytes_copied); | |
| 131 | + if (ret) | |
| 132 | + return ret; | |
| 133 | + | |
| 134 | + if (*user_bytes_copied == user_size) | |
| 135 | + return 0; | |
| 136 | + | |
| 137 | + ret = ivpu_jsm_metric_streamer_update(vdev, ms->mask, ms->inactive_buff_vpu_addr, | |
| 138 | + ms->buff_size, &bytes_written); | |
| 139 | + if (ret) | |
| 140 | + return ret; | |
| 141 | + | |
| 142 | + swap(ms->active_buff_vpu_addr, ms->inactive_buff_vpu_addr); | |
| 143 | + swap(ms->active_buff_ptr, ms->inactive_buff_ptr); | |
| 144 | + | |
| 145 | + ms->leftover_bytes = bytes_written; | |
| 146 | + ms->leftover_addr = ms->inactive_buff_ptr; | |
| 147 | + | |
| 148 | + return copy_leftover_bytes(ms, user_ptr, user_size, user_bytes_copied); | |
| 149 | +} | |
| 150 | + | |
| 151 | +int ivpu_ms_get_data_ioctl(struct drm_device *dev, void *data, struct drm_file *file) | |
| 152 | +{ | |
| 153 | + struct drm_ivpu_metric_streamer_get_data *args = data; | |
| 154 | + struct ivpu_file_priv *file_priv = file->driver_priv; | |
| 155 | + struct ivpu_device *vdev = file_priv->vdev; | |
| 156 | + struct ivpu_ms_instance *ms; | |
| 157 | + u64 bytes_written; | |
| 158 | + int ret; | |
| 159 | + | |
| 160 | + if (!args->metric_group_mask) | |
| 161 | + return -EINVAL; | |
| 162 | + | |
| 163 | + mutex_lock(&file_priv->ms_lock); | |
| 164 | + | |
| 165 | + ms = get_instance_by_mask(file_priv, args->metric_group_mask); | |
| 166 | + if (!ms) { | |
| 167 | + ivpu_err(vdev, "Instance doesn't exist for mask: %#llx\n", args->metric_group_mask); | |
| 168 | + ret = -EINVAL; | |
| 169 | + goto unlock; | |
| 170 | + } | |
| 171 | + | |
| 172 | + if (!args->buffer_size) { | |
| 173 | + ret = ivpu_jsm_metric_streamer_update(vdev, ms->mask, 0, 0, &bytes_written); | |
| 174 | + if (ret) | |
| 175 | + goto unlock; | |
| 176 | + args->data_size = bytes_written + ms->leftover_bytes; | |
| 177 | + goto unlock; | |
| 178 | + } | |
| 179 | + | |
| 180 | + if (!args->buffer_ptr) { | |
| 181 | + ret = -EINVAL; | |
| 182 | + goto unlock; | |
| 183 | + } | |
| 184 | + | |
| 185 | + ret = copy_samples_to_user(vdev, ms, u64_to_user_ptr(args->buffer_ptr), | |
| 186 | + args->buffer_size, &args->data_size); | |
| 187 | +unlock: | |
| 188 | + mutex_unlock(&file_priv->ms_lock); | |
| 189 | + | |
| 190 | + return ret; | |
| 191 | +} | |
| 192 | + | |
| 193 | +static void free_instance(struct ivpu_file_priv *file_priv, struct ivpu_ms_instance *ms) | |
| 194 | +{ | |
| 195 | + lockdep_assert_held(&file_priv->ms_lock); | |
| 196 | + | |
| 197 | + list_del(&ms->ms_instance_node); | |
| 198 | + ivpu_jsm_metric_streamer_stop(file_priv->vdev, ms->mask); | |
| 199 | + ivpu_bo_free(ms->bo); | |
| 200 | + kfree(ms); | |
| 201 | +} | |
| 202 | + | |
| 203 | +int ivpu_ms_stop_ioctl(struct drm_device *dev, void *data, struct drm_file *file) | |
| 204 | +{ | |
| 205 | + struct ivpu_file_priv *file_priv = file->driver_priv; | |
| 206 | + struct drm_ivpu_metric_streamer_stop *args = data; | |
| 207 | + struct ivpu_ms_instance *ms; | |
| 208 | + | |
| 209 | + if (!args->metric_group_mask) | |
| 210 | + return -EINVAL; | |
| 211 | + | |
| 212 | + mutex_lock(&file_priv->ms_lock); | |
| 213 | + | |
| 214 | + ms = get_instance_by_mask(file_priv, args->metric_group_mask); | |
| 215 | + if (ms) | |
| 216 | + free_instance(file_priv, ms); | |
| 217 | + | |
| 218 | + mutex_unlock(&file_priv->ms_lock); | |
| 219 | + | |
| 220 | + return ms ? 0 : -EINVAL; | |
| 221 | +} | |
| 222 | + | |
| 223 | +static inline struct ivpu_bo *get_ms_info_bo(struct ivpu_file_priv *file_priv) | |
| 224 | +{ | |
| 225 | + lockdep_assert_held(&file_priv->ms_lock); | |
| 226 | + | |
| 227 | + if (file_priv->ms_info_bo) | |
| 228 | + return file_priv->ms_info_bo; | |
| 229 | + | |
| 230 | + file_priv->ms_info_bo = ivpu_bo_create_global(file_priv->vdev, MS_INFO_BUFFER_SIZE, | |
| 231 | + DRM_IVPU_BO_CACHED | DRM_IVPU_BO_MAPPABLE); | |
| 232 | + return file_priv->ms_info_bo; | |
| 233 | +} | |
| 234 | + | |
| 235 | +int ivpu_ms_get_info_ioctl(struct drm_device *dev, void *data, struct drm_file *file) | |
| 236 | +{ | |
| 237 | + struct drm_ivpu_metric_streamer_get_data *args = data; | |
| 238 | + struct ivpu_file_priv *file_priv = file->driver_priv; | |
| 239 | + struct ivpu_device *vdev = file_priv->vdev; | |
| 240 | + struct ivpu_bo *bo; | |
| 241 | + u64 info_size; | |
| 242 | + int ret; | |
| 243 | + | |
| 244 | + if (!args->metric_group_mask) | |
| 245 | + return -EINVAL; | |
| 246 | + | |
| 247 | + if (!args->buffer_size) | |
| 248 | + return ivpu_jsm_metric_streamer_info(vdev, args->metric_group_mask, | |
| 249 | + 0, 0, NULL, &args->data_size); | |
| 250 | + if (!args->buffer_ptr) | |
| 251 | + return -EINVAL; | |
| 252 | + | |
| 253 | + mutex_lock(&file_priv->ms_lock); | |
| 254 | + | |
| 255 | + bo = get_ms_info_bo(file_priv); | |
| 256 | + if (!bo) { | |
| 257 | + ret = -ENOMEM; | |
| 258 | + goto unlock; | |
| 259 | + } | |
| 260 | + | |
| 261 | + ret = ivpu_jsm_metric_streamer_info(vdev, args->metric_group_mask, bo->vpu_addr, | |
| 262 | + ivpu_bo_size(bo), NULL, &info_size); | |
| 263 | + if (ret) | |
| 264 | + goto unlock; | |
| 265 | + | |
| 266 | + if (args->buffer_size < info_size) { | |
| 267 | + ret = -ENOSPC; | |
| 268 | + goto unlock; | |
| 269 | + } | |
| 270 | + | |
| 271 | + if (copy_to_user(u64_to_user_ptr(args->buffer_ptr), ivpu_bo_vaddr(bo), info_size)) | |
| 272 | + ret = -EFAULT; | |
| 273 | + | |
| 274 | + args->data_size = info_size; | |
| 275 | +unlock: | |
| 276 | + mutex_unlock(&file_priv->ms_lock); | |
| 277 | + | |
| 278 | + return ret; | |
| 279 | +} | |
| 280 | + | |
| 281 | +void ivpu_ms_cleanup(struct ivpu_file_priv *file_priv) | |
| 282 | +{ | |
| 283 | + struct ivpu_ms_instance *ms, *tmp; | |
| 284 | + | |
| 285 | + mutex_lock(&file_priv->ms_lock); | |
| 286 | + | |
| 287 | + if (file_priv->ms_info_bo) { | |
| 288 | + ivpu_bo_free(file_priv->ms_info_bo); | |
| 289 | + file_priv->ms_info_bo = NULL; | |
| 290 | + } | |
| 291 | + | |
| 292 | + list_for_each_entry_safe(ms, tmp, &file_priv->ms_instance_list, ms_instance_node) | |
| 293 | + free_instance(file_priv, ms); | |
| 294 | + | |
| 295 | + mutex_unlock(&file_priv->ms_lock); | |
| 296 | +} | |
| 297 | + | |
| 298 | +void ivpu_ms_cleanup_all(struct ivpu_device *vdev) | |
| 299 | +{ | |
| 300 | + struct ivpu_file_priv *file_priv; | |
| 301 | + unsigned long ctx_id; | |
| 302 | + | |
| 303 | + mutex_lock(&vdev->context_list_lock); | |
| 304 | + | |
| 305 | + xa_for_each(&vdev->context_xa, ctx_id, file_priv) | |
| 306 | + ivpu_ms_cleanup(file_priv); | |
| 307 | + | |
| 308 | + mutex_unlock(&vdev->context_list_lock); | |
| 309 | +} | |
| @@ -0,0 +1,36 @@ | ||
| 1 | +/* SPDX-License-Identifier: GPL-2.0-only OR MIT */ | |
| 2 | +/* | |
| 3 | + * Copyright (C) 2020-2024 Intel Corporation | |
| 4 | + */ | |
| 5 | +#ifndef __IVPU_MS_H__ | |
| 6 | +#define __IVPU_MS_H__ | |
| 7 | + | |
| 8 | +#include <linux/list.h> | |
| 9 | + | |
| 10 | +struct drm_device; | |
| 11 | +struct drm_file; | |
| 12 | +struct ivpu_bo; | |
| 13 | +struct ivpu_device; | |
| 14 | +struct ivpu_file_priv; | |
| 15 | + | |
| 16 | +struct ivpu_ms_instance { | |
| 17 | + struct ivpu_bo *bo; | |
| 18 | + struct list_head ms_instance_node; | |
| 19 | + u64 mask; | |
| 20 | + u64 buff_size; | |
| 21 | + u64 active_buff_vpu_addr; | |
| 22 | + u64 inactive_buff_vpu_addr; | |
| 23 | + void *active_buff_ptr; | |
| 24 | + void *inactive_buff_ptr; | |
| 25 | + u64 leftover_bytes; | |
| 26 | + void *leftover_addr; | |
| 27 | +}; | |
| 28 | + | |
| 29 | +int ivpu_ms_start_ioctl(struct drm_device *dev, void *data, struct drm_file *file); | |
| 30 | +int ivpu_ms_stop_ioctl(struct drm_device *dev, void *data, struct drm_file *file); | |
| 31 | +int ivpu_ms_get_data_ioctl(struct drm_device *dev, void *data, struct drm_file *file); | |
| 32 | +int ivpu_ms_get_info_ioctl(struct drm_device *dev, void *data, struct drm_file *file); | |
| 33 | +void ivpu_ms_cleanup(struct ivpu_file_priv *file_priv); | |
| 34 | +void ivpu_ms_cleanup_all(struct ivpu_device *vdev); | |
| 35 | + | |
| 36 | +#endif /* __IVPU_MS_H__ */ | |
| @@ -18,6 +18,7 @@ · 17 unmodified lines | ||
| 18 | 18 | #include "ivpu_job.h" |
| 19 | 19 | #include "ivpu_jsm_msg.h" |
| 20 | 20 | #include "ivpu_mmu.h" |
| 21 | +#include "ivpu_ms.h" | |
| 21 | 22 | #include "ivpu_pm.h" |
| 22 | 23 | |
| 23 | 24 | static bool ivpu_disable_recovery; |
| @@ -131,6 +132,7 @@ static void ivpu_pm_recovery_work(struct work_struct *work) · 107 unmodified lines | ||
| 131 | 132 | ivpu_suspend(vdev); |
| 132 | 133 | ivpu_pm_prepare_cold_boot(vdev); |
| 133 | 134 | ivpu_jobs_abort_all(vdev); |
| 135 | + ivpu_ms_cleanup_all(vdev); | |
| 134 | 136 | |
| 135 | 137 | ret = ivpu_resume(vdev); |
| 136 | 138 | if (ret) |
| @@ -235,41 +237,37 @@ int ivpu_pm_runtime_suspend_cb(struct device *dev) · 98 unmodified lines | ||
| 235 | 237 | { |
| 236 | 238 | struct drm_device *drm = dev_get_drvdata(dev); |
| 237 | 239 | struct ivpu_device *vdev = to_ivpu_device(drm); |
| 238 | − bool hw_is_idle = true; | |
| 239 | − int ret; | |
| 240 | + int ret, ret_d0i3; | |
| 241 | + bool is_idle; | |
| 240 | 242 | |
| 241 | 243 | drm_WARN_ON(&vdev->drm, !xa_empty(&vdev->submitted_jobs_xa)); |
| 242 | 244 | drm_WARN_ON(&vdev->drm, work_pending(&vdev->pm->recovery_work)); |
| 243 | 245 | |
| 244 | 246 | ivpu_dbg(vdev, PM, "Runtime suspend..\n"); |
| 245 | 247 | |
| 246 | − if (!ivpu_hw_is_idle(vdev) && vdev->pm->suspend_reschedule_counter) { | |
| 247 | − ivpu_dbg(vdev, PM, "Failed to enter idle, rescheduling suspend, retries left %d\n", | |
| 248 | − vdev->pm->suspend_reschedule_counter); | |
| 249 | − pm_schedule_suspend(dev, vdev->timeout.reschedule_suspend); | |
| 250 | − vdev->pm->suspend_reschedule_counter--; | |
| 251 | − return -EAGAIN; | |
| 252 | − } | |
| 248 | + ivpu_mmu_disable(vdev); | |
| 249 | + | |
| 250 | + is_idle = ivpu_hw_is_idle(vdev) || vdev->pm->dct_active_percent; | |
| 251 | + if (!is_idle) | |
| 252 | + ivpu_err(vdev, "NPU is not idle before autosuspend\n"); | |
| 253 | 253 | |
| 254 | − if (!vdev->pm->suspend_reschedule_counter) | |
| 255 | − hw_is_idle = false; | |
| 256 | − else if (ivpu_jsm_pwr_d0i3_enter(vdev)) | |
| 257 | − hw_is_idle = false; | |
| 254 | + ret_d0i3 = ivpu_jsm_pwr_d0i3_enter(vdev); | |
| 255 | + if (ret_d0i3) | |
| 256 | + ivpu_err(vdev, "Failed to prepare for d0i3: %d\n", ret_d0i3); | |
| 258 | 257 | |
| 259 | 258 | ret = ivpu_suspend(vdev); |
| 260 | 259 | if (ret) |
| 261 | 260 | ivpu_err(vdev, "Failed to suspend NPU: %d\n", ret); |
| 262 | 261 | |
| 263 | − if (!hw_is_idle) { | |
| 264 | − ivpu_err(vdev, "NPU failed to enter idle, force suspended.\n"); | |
| 262 | + if (!is_idle || ret_d0i3) { | |
| 263 | + ivpu_err(vdev, "Forcing cold boot due to previous errors\n"); | |
| 264 | + atomic_inc(&vdev->pm->reset_counter); | |
| 265 | 265 | ivpu_fw_log_dump(vdev); |
| 266 | 266 | ivpu_pm_prepare_cold_boot(vdev); |
| 267 | 267 | } else { |
| 268 | 268 | ivpu_pm_prepare_warm_boot(vdev); |
| 269 | 269 | } |
| 270 | 270 | |
| 271 | − vdev->pm->suspend_reschedule_counter = PM_RESCHEDULE_LIMIT; | |
| 272 | − | |
| 273 | 271 | ivpu_dbg(vdev, PM, "Runtime suspend done.\n"); |
| 274 | 272 | |
| 275 | 273 | return 0; |
| @@ -297,17 +295,6 @@ int ivpu_rpm_get(struct ivpu_device *vdev) · 21 unmodified lines | ||
| 297 | 295 | int ret; |
| 298 | 296 | |
| 299 | 297 | ret = pm_runtime_resume_and_get(vdev->drm.dev); |
| 300 | − if (!drm_WARN_ON(&vdev->drm, ret < 0)) | |
| 301 | − vdev->pm->suspend_reschedule_counter = PM_RESCHEDULE_LIMIT; | |
| 302 | − | |
| 303 | − return ret; | |
| 304 | −} | |
| 305 | − | |
| 306 | −int ivpu_rpm_get_if_active(struct ivpu_device *vdev) | |
| 307 | −{ | |
| 308 | − int ret; | |
| 309 | − | |
| 310 | − ret = pm_runtime_get_if_in_use(vdev->drm.dev); | |
| 311 | 298 | drm_WARN_ON(&vdev->drm, ret < 0); |
| 312 | 299 | |
| 313 | 300 | return ret; |
| @@ -333,6 +320,8 @@ void ivpu_pm_reset_prepare_cb(struct pci_dev *pdev) · 19 unmodified lines | ||
| 333 | 320 | ivpu_hw_reset(vdev); |
| 334 | 321 | ivpu_pm_prepare_cold_boot(vdev); |
| 335 | 322 | ivpu_jobs_abort_all(vdev); |
| 323 | + ivpu_ms_cleanup_all(vdev); | |
| 324 | + | |
| 336 | 325 | ivpu_dbg(vdev, PM, "Pre-reset done.\n"); |
| 337 | 326 | } |
| 338 | 327 | |
| @@ -360,7 +349,6 @@ void ivpu_pm_init(struct ivpu_device *vdev) · 21 unmodified lines | ||
| 360 | 349 | int delay; |
| 361 | 350 | |
| 362 | 351 | pm->vdev = vdev; |
| 363 | − pm->suspend_reschedule_counter = PM_RESCHEDULE_LIMIT; | |
| 364 | 352 | |
| 365 | 353 | init_rwsem(&pm->reset_lock); |
| 366 | 354 | atomic_set(&pm->reset_pending, 0); |
| @@ -401,3 +389,68 @@ void ivpu_pm_disable(struct ivpu_device *vdev) · 34 unmodified lines | ||
| 401 | 389 | pm_runtime_get_noresume(vdev->drm.dev); |
| 402 | 390 | pm_runtime_forbid(vdev->drm.dev); |
| 403 | 391 | } |
| 392 | + | |
| 393 | +int ivpu_pm_dct_init(struct ivpu_device *vdev) | |
| 394 | +{ | |
| 395 | + if (vdev->pm->dct_active_percent) | |
| 396 | + return ivpu_pm_dct_enable(vdev, vdev->pm->dct_active_percent); | |
| 397 | + | |
| 398 | + return 0; | |
| 399 | +} | |
| 400 | + | |
| 401 | +int ivpu_pm_dct_enable(struct ivpu_device *vdev, u8 active_percent) | |
| 402 | +{ | |
| 403 | + u32 active_us, inactive_us; | |
| 404 | + int ret; | |
| 405 | + | |
| 406 | + if (active_percent == 0 || active_percent > 100) | |
| 407 | + return -EINVAL; | |
| 408 | + | |
| 409 | + active_us = (DCT_PERIOD_US * active_percent) / 100; | |
| 410 | + inactive_us = DCT_PERIOD_US - active_us; | |
| 411 | + | |
| 412 | + ret = ivpu_jsm_dct_enable(vdev, active_us, inactive_us); | |
| 413 | + if (ret) { | |
| 414 | + ivpu_err_ratelimited(vdev, "Filed to enable DCT: %d\n", ret); | |
| 415 | + return ret; | |
| 416 | + } | |
| 417 | + | |
| 418 | + vdev->pm->dct_active_percent = active_percent; | |
| 419 | + | |
| 420 | + ivpu_dbg(vdev, PM, "DCT set to %u%% (D0: %uus, D0i2: %uus)\n", | |
| 421 | + active_percent, active_us, inactive_us); | |
| 422 | + return 0; | |
| 423 | +} | |
| 424 | + | |
| 425 | +int ivpu_pm_dct_disable(struct ivpu_device *vdev) | |
| 426 | +{ | |
| 427 | + int ret; | |
| 428 | + | |
| 429 | + ret = ivpu_jsm_dct_disable(vdev); | |
| 430 | + if (ret) { | |
| 431 | + ivpu_err_ratelimited(vdev, "Filed to disable DCT: %d\n", ret); | |
| 432 | + return ret; | |
| 433 | + } | |
| 434 | + | |
| 435 | + vdev->pm->dct_active_percent = 0; | |
| 436 | + | |
| 437 | + ivpu_dbg(vdev, PM, "DCT disabled\n"); | |
| 438 | + return 0; | |
| 439 | +} | |
| 440 | + | |
| 441 | +void ivpu_pm_dct_irq_thread_handler(struct ivpu_device *vdev) | |
| 442 | +{ | |
| 443 | + bool enable; | |
| 444 | + int ret; | |
| 445 | + | |
| 446 | + if (ivpu_hw_btrs_dct_get_request(vdev, &enable)) | |
| 447 | + return; | |
| 448 | + | |
| 449 | + if (vdev->pm->dct_active_percent) | |
| 450 | + ret = ivpu_pm_dct_enable(vdev, DCT_DEFAULT_ACTIVE_PERCENT); | |
| 451 | + else | |
| 452 | + ret = ivpu_pm_dct_disable(vdev); | |
| 453 | + | |
| 454 | + if (!ret) | |
| 455 | + ivpu_hw_btrs_dct_set_status(vdev, enable, vdev->pm->dct_active_percent); | |
| 456 | +} | |
| @@ -1,6 +1,6 @@ | ||
| 1 | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
| 2 | 2 | /* |
| 3 | − * Copyright (C) 2020-2023 Intel Corporation | |
| 3 | + * Copyright (C) 2020-2024 Intel Corporation | |
| 4 | 4 | */ |
| 5 | 5 | |
| 6 | 6 | #ifndef __IVPU_PM_H__ |
| @@ -19,7 +19,7 @@ struct ivpu_pm_info { · 12 unmodified lines | ||
| 19 | 19 | atomic_t reset_counter; |
| 20 | 20 | atomic_t reset_pending; |
| 21 | 21 | bool is_warmboot; |
| 22 | − u32 suspend_reschedule_counter; | |
| 22 | + u8 dct_active_percent; | |
| 23 | 23 | }; |
| 24 | 24 | |
| 25 | 25 | void ivpu_pm_init(struct ivpu_device *vdev); |
| @@ -36,11 +36,15 @@ void ivpu_pm_reset_prepare_cb(struct pci_dev *pdev); · 10 unmodified lines | ||
| 36 | 36 | void ivpu_pm_reset_done_cb(struct pci_dev *pdev); |
| 37 | 37 | |
| 38 | 38 | int __must_check ivpu_rpm_get(struct ivpu_device *vdev); |
| 39 | −int __must_check ivpu_rpm_get_if_active(struct ivpu_device *vdev); | |
| 40 | 39 | void ivpu_rpm_put(struct ivpu_device *vdev); |
| 41 | 40 | |
| 42 | 41 | void ivpu_pm_trigger_recovery(struct ivpu_device *vdev, const char *reason); |
| 43 | 42 | void ivpu_start_job_timeout_detection(struct ivpu_device *vdev); |
| 44 | 43 | void ivpu_stop_job_timeout_detection(struct ivpu_device *vdev); |
| 45 | 44 | |
| 45 | +int ivpu_pm_dct_init(struct ivpu_device *vdev); | |
| 46 | +int ivpu_pm_dct_enable(struct ivpu_device *vdev, u8 active_percent); | |
| 47 | +int ivpu_pm_dct_disable(struct ivpu_device *vdev); | |
| 48 | +void ivpu_pm_dct_irq_thread_handler(struct ivpu_device *vdev); | |
| 49 | + | |
| 46 | 50 | #endif /* __IVPU_PM_H__ */ |
| @@ -0,0 +1,58 @@ | ||
| 1 | +// SPDX-License-Identifier: GPL-2.0-only | |
| 2 | +/* | |
| 3 | + * Copyright (C) 2024 Intel Corporation | |
| 4 | + */ | |
| 5 | + | |
| 6 | +#include <linux/device.h> | |
| 7 | +#include <linux/err.h> | |
| 8 | + | |
| 9 | +#include "ivpu_hw.h" | |
| 10 | +#include "ivpu_sysfs.h" | |
| 11 | + | |
| 12 | +/* | |
| 13 | + * npu_busy_time_us is the time that the device spent executing jobs. | |
| 14 | + * The time is counted when and only when there are jobs submitted to firmware. | |
| 15 | + * | |
| 16 | + * This time can be used to measure the utilization of NPU, either by calculating | |
| 17 | + * npu_busy_time_us difference between two timepoints (i.e. measuring the time | |
| 18 | + * that the NPU was active during some workload) or monitoring utilization percentage | |
| 19 | + * by reading npu_busy_time_us periodically. | |
| 20 | + * | |
| 21 | + * When reading the value periodically, it shouldn't be read too often as it may have | |
| 22 | + * an impact on job submission performance. Recommended period is 1 second. | |
| 23 | + */ | |
| 24 | +static ssize_t | |
| 25 | +npu_busy_time_us_show(struct device *dev, struct device_attribute *attr, char *buf) | |
| 26 | +{ | |
| 27 | + struct drm_device *drm = dev_get_drvdata(dev); | |
| 28 | + struct ivpu_device *vdev = to_ivpu_device(drm); | |
| 29 | + ktime_t total, now = 0; | |
| 30 | + | |
| 31 | + xa_lock(&vdev->submitted_jobs_xa); | |
| 32 | + total = vdev->busy_time; | |
| 33 | + if (!xa_empty(&vdev->submitted_jobs_xa)) | |
| 34 | + now = ktime_sub(ktime_get(), vdev->busy_start_ts); | |
| 35 | + xa_unlock(&vdev->submitted_jobs_xa); | |
| 36 | + | |
| 37 | + return sysfs_emit(buf, "%lld\n", ktime_to_us(ktime_add(total, now))); | |
| 38 | +} | |
| 39 | + | |
| 40 | +static DEVICE_ATTR_RO(npu_busy_time_us); | |
| 41 | + | |
| 42 | +static struct attribute *ivpu_dev_attrs[] = { | |
| 43 | + &dev_attr_npu_busy_time_us.attr, | |
| 44 | + NULL, | |
| 45 | +}; | |
| 46 | + | |
| 47 | +static struct attribute_group ivpu_dev_attr_group = { | |
| 48 | + .attrs = ivpu_dev_attrs, | |
| 49 | +}; | |
| 50 | + | |
| 51 | +void ivpu_sysfs_init(struct ivpu_device *vdev) | |
| 52 | +{ | |
| 53 | + int ret; | |
| 54 | + | |
| 55 | + ret = devm_device_add_group(vdev->drm.dev, &ivpu_dev_attr_group); | |
| 56 | + if (ret) | |
| 57 | + ivpu_warn(vdev, "Failed to add group to device, ret %d", ret); | |
| 58 | +} | |
| @@ -0,0 +1,13 @@ | ||
| 1 | +/* SPDX-License-Identifier: GPL-2.0-only */ | |
| 2 | +/* | |
| 3 | + * Copyright (C) 2024 Intel Corporation | |
| 4 | + */ | |
| 5 | + | |
| 6 | +#ifndef __IVPU_SYSFS_H__ | |
| 7 | +#define __IVPU_SYSFS_H__ | |
| 8 | + | |
| 9 | +#include "ivpu_drv.h" | |
| 10 | + | |
| 11 | +void ivpu_sysfs_init(struct ivpu_device *vdev); | |
| 12 | + | |
| 13 | +#endif /* __IVPU_SYSFS_H__ */ | |
| @@ -27,7 +27,7 @@ · 26 unmodified lines | ||
| 27 | 27 | * Minor version changes when API backward compatibility is preserved. |
| 28 | 28 | * Resets to 0 if Major version is incremented. |
| 29 | 29 | */ |
| 30 | −#define VPU_BOOT_API_VER_MINOR 22 | |
| 30 | +#define VPU_BOOT_API_VER_MINOR 24 | |
| 31 | 31 | |
| 32 | 32 | /* |
| 33 | 33 | * API header changed (field names, documentation, formatting) but API itself has not been changed |
| @@ -80,6 +80,11 @@ struct vpu_firmware_header { · 46 unmodified lines | ||
| 80 | 80 | u32 preemption_buffer_2_size; |
| 81 | 81 | /* Space reserved for future preemption-related fields. */ |
| 82 | 82 | u32 preemption_reserved[6]; |
| 83 | + /* FW image read only section start address, 4KB aligned */ | |
| 84 | + u64 ro_section_start_address; | |
| 85 | + /* FW image read only section size, 4KB aligned */ | |
| 86 | + u32 ro_section_size; | |
| 87 | + u32 reserved; | |
| 83 | 88 | }; |
| 84 | 89 | |
| 85 | 90 | /* |
| @@ -333,7 +338,14 @@ struct vpu_boot_params { · 247 unmodified lines | ||
| 333 | 338 | * The KMD is required to update this value on every VPU reset. |
| 334 | 339 | */ |
| 335 | 340 | u64 system_time_us; |
| 336 | − u32 pad4[18]; | |
| 341 | + u32 pad4[2]; | |
| 342 | + /* | |
| 343 | + * The delta between device monotonic time and the current value of the | |
| 344 | + * HW timestamp register, in ticks. Written by the firmware during boot. | |
| 345 | + * Can be used by the KMD to calculate device time. | |
| 346 | + */ | |
| 347 | + u64 device_time_delta_ticks; | |
| 348 | + u32 pad7[14]; | |
| 337 | 349 | /* Warm boot information: 0x400 - 0x43F */ |
| 338 | 350 | u32 warm_boot_sections_count; |
| 339 | 351 | u32 warm_boot_start_address_reference; |
| @@ -1,6 +1,6 @@ | ||
| 1 | 1 | /* SPDX-License-Identifier: MIT */ |
| 2 | 2 | /* |
| 3 | − * Copyright (c) 2020-2023, Intel Corporation. | |
| 3 | + * Copyright (c) 2020-2024, Intel Corporation. | |
| 4 | 4 | */ |
| 5 | 5 | |
| 6 | 6 | /** |
| @@ -22,12 +22,12 @@ · 15 unmodified lines | ||
| 22 | 22 | /* |
| 23 | 23 | * Minor version changes when API backward compatibility is preserved. |
| 24 | 24 | */ |
| 25 | −#define VPU_JSM_API_VER_MINOR 15 | |
| 25 | +#define VPU_JSM_API_VER_MINOR 16 | |
| 26 | 26 | |
| 27 | 27 | /* |
| 28 | 28 | * API header changed (field names, documentation, formatting) but API itself has not been changed |
| 29 | 29 | */ |
| 30 | −#define VPU_JSM_API_VER_PATCH 6 | |
| 30 | +#define VPU_JSM_API_VER_PATCH 0 | |
| 31 | 31 | |
| 32 | 32 | /* |
| 33 | 33 | * Index in the API version table |
| @@ -868,6 +868,14 @@ struct vpu_ipc_msg_payload_hws_set_scheduling_log { · 834 unmodified lines | ||
| 868 | 868 | * is generated when an event log is written to this index. |
| 869 | 869 | */ |
| 870 | 870 | u64 notify_index; |
| 871 | + /* | |
| 872 | + * Enable extra events to be output to log for debug of scheduling algorithm. | |
| 873 | + * Interpreted by VPU as a boolean to enable or disable, expected values are | |
| 874 | + * 0 and 1. | |
| 875 | + */ | |
| 876 | + u32 enable_extra_events; | |
| 877 | + /* Zero Padding */ | |
| 878 | + u32 reserved_0; | |
| 871 | 879 | }; |
| 872 | 880 | |
| 873 | 881 | /* |
| @@ -802,4 +802,5 @@ module_exit(agp_amd64_cleanup); · 801 unmodified lines | ||
| 802 | 802 | |
| 803 | 803 | MODULE_AUTHOR("Dave Jones, Andi Kleen"); |
| 804 | 804 | module_param(agp_try_unsupported, bool, 0); |
| 805 | +MODULE_DESCRIPTION("GART driver for the AMD Opteron/Athlon64 on-CPU northbridge"); | |
| 805 | 806 | MODULE_LICENSE("GPL"); |
| @@ -12,7 +12,7 @@ · 11 unmodified lines | ||
| 12 | 12 | #include <asm/smp.h> |
| 13 | 13 | #include "agp.h" |
| 14 | 14 | #include "intel-agp.h" |
| 15 | −#include <drm/intel-gtt.h> | |
| 15 | +#include <drm/intel/intel-gtt.h> | |
| 16 | 16 | |
| 17 | 17 | static int intel_fetch_size(void) |
| 18 | 18 | { |
| @@ -920,4 +920,5 @@ module_init(agp_intel_init); · 901 unmodified lines | ||
| 920 | 920 | module_exit(agp_intel_cleanup); |
| 921 | 921 | |
| 922 | 922 | MODULE_AUTHOR("Dave Jones, Various @Intel"); |
| 923 | +MODULE_DESCRIPTION("Intel AGPGART routines"); | |
| 923 | 924 | MODULE_LICENSE("GPL and additional rights"); |
| @@ -25,7 +25,7 @@ · 24 unmodified lines | ||
| 25 | 25 | #include <asm/smp.h> |
| 26 | 26 | #include "agp.h" |
| 27 | 27 | #include "intel-agp.h" |
| 28 | −#include <drm/intel-gtt.h> | |
| 28 | +#include <drm/intel/intel-gtt.h> | |
| 29 | 29 | #include <asm/set_memory.h> |
| 30 | 30 | |
| 31 | 31 | /* |
| @@ -1461,4 +1461,5 @@ void intel_gmch_remove(void) · 1429 unmodified lines | ||
| 1461 | 1461 | EXPORT_SYMBOL(intel_gmch_remove); |
| 1462 | 1462 | |
| 1463 | 1463 | MODULE_AUTHOR("Dave Jones, Various @Intel"); |
| 1464 | +MODULE_DESCRIPTION("Intel GTT (Graphics Translation Table) routines"); | |
| 1464 | 1465 | MODULE_LICENSE("GPL and additional rights"); |
| @@ -433,4 +433,5 @@ module_param(agp_sis_force_delay, bool, 0); · 432 unmodified lines | ||
| 433 | 433 | MODULE_PARM_DESC(agp_sis_force_delay,"forces sis delay hack"); |
| 434 | 434 | module_param(agp_sis_agp_spec, int, 0); |
| 435 | 435 | MODULE_PARM_DESC(agp_sis_agp_spec,"0=force sis init, 1=force generic agp3 init, default: autodetect"); |
| 436 | +MODULE_DESCRIPTION("SiS AGPGART routines"); | |
| 436 | 437 | MODULE_LICENSE("GPL and additional rights"); |
| @@ -575,5 +575,6 @@ static void __exit agp_via_cleanup(void) · 574 unmodified lines | ||
| 575 | 575 | module_init(agp_via_init); |
| 576 | 576 | module_exit(agp_via_cleanup); |
| 577 | 577 | |
| 578 | +MODULE_DESCRIPTION("VIA AGPGART routines"); | |
| 578 | 579 | MODULE_LICENSE("GPL"); |
| 579 | 580 | MODULE_AUTHOR("Dave Jones"); |
| @@ -70,7 +70,7 @@ static void dma_fence_array_cb_func(struct dma_fence *f, · 69 unmodified lines | ||
| 70 | 70 | static bool dma_fence_array_enable_signaling(struct dma_fence *fence) |
| 71 | 71 | { |
| 72 | 72 | struct dma_fence_array *array = to_dma_fence_array(fence); |
| 73 | − struct dma_fence_array_cb *cb = (void *)(&array[1]); | |
| 73 | + struct dma_fence_array_cb *cb = array->callbacks; | |
| 74 | 74 | unsigned i; |
| 75 | 75 | |
| 76 | 76 | for (i = 0; i < array->num_fences; ++i) { |
| @@ -168,22 +168,20 @@ struct dma_fence_array *dma_fence_array_create(int num_fences, · 91 unmodified lines | ||
| 168 | 168 | bool signal_on_any) |
| 169 | 169 | { |
| 170 | 170 | struct dma_fence_array *array; |
| 171 | − size_t size = sizeof(*array); | |
| 172 | 171 | |
| 173 | 172 | WARN_ON(!num_fences || !fences); |
| 174 | 173 | |
| 175 | − /* Allocate the callback structures behind the array. */ | |
| 176 | − size += num_fences * sizeof(struct dma_fence_array_cb); | |
| 177 | − array = kzalloc(size, GFP_KERNEL); | |
| 174 | + array = kzalloc(struct_size(array, callbacks, num_fences), GFP_KERNEL); | |
| 178 | 175 | if (!array) |
| 179 | 176 | return NULL; |
| 180 | 177 | |
| 178 | + array->num_fences = num_fences; | |
| 179 | + | |
| 181 | 180 | spin_lock_init(&array->lock); |
| 182 | 181 | dma_fence_init(&array->base, &dma_fence_array_ops, &array->lock, |
| 183 | 182 | context, seqno); |
| 184 | 183 | init_irq_work(&array->work, irq_dma_fence_array_work); |
| 185 | 184 | |
| 186 | − array->num_fences = num_fences; | |
| 187 | 185 | atomic_set(&array->num_pending, signal_on_any ? 1 : num_fences); |
| 188 | 186 | array->fences = fences; |
| 189 | 187 | |
| @@ -50,8 +50,8 @@ static struct class *dma_heap_class; · 49 unmodified lines | ||
| 50 | 50 | static DEFINE_XARRAY_ALLOC(dma_heap_minors); |
| 51 | 51 | |
| 52 | 52 | static int dma_heap_buffer_alloc(struct dma_heap *heap, size_t len, |
| 53 | − unsigned int fd_flags, | |
| 54 | − unsigned int heap_flags) | |
| 53 | + u32 fd_flags, | |
| 54 | + u64 heap_flags) | |
| 55 | 55 | { |
| 56 | 56 | struct dma_buf *dmabuf; |
| 57 | 57 | int fd; |
| @@ -186,6 +186,13 @@ int dma_resv_reserve_fences(struct dma_resv *obj, unsigned int num_fences) · 185 unmodified lines | ||
| 186 | 186 | |
| 187 | 187 | dma_resv_assert_held(obj); |
| 188 | 188 | |
| 189 | + /* Driver and component code should never call this function with | |
| 190 | + * num_fences=0. If they do it usually points to bugs when calculating | |
| 191 | + * the number of needed fences dynamically. | |
| 192 | + */ | |
| 193 | + if (WARN_ON(!num_fences)) | |
| 194 | + return -EINVAL; | |
| 195 | + | |
| 189 | 196 | old = dma_resv_fences_list(obj); |
| 190 | 197 | if (old && old->max_fences) { |
| 191 | 198 | if ((old->num_fences + num_fences) <= old->max_fences) |
| @@ -274,8 +274,8 @@ static const struct dma_buf_ops cma_heap_buf_ops = { · 273 unmodified lines | ||
| 274 | 274 | |
| 275 | 275 | static struct dma_buf *cma_heap_allocate(struct dma_heap *heap, |
| 276 | 276 | unsigned long len, |
| 277 | − unsigned long fd_flags, | |
| 278 | − unsigned long heap_flags) | |
| 277 | + u32 fd_flags, | |
| 278 | + u64 heap_flags) | |
| 279 | 279 | { |
| 280 | 280 | struct cma_heap *cma_heap = dma_heap_get_drvdata(heap); |
| 281 | 281 | struct cma_heap_buffer *buffer; |
| @@ -333,8 +333,8 @@ static struct page *alloc_largest_available(unsigned long size, · 332 unmodified lines | ||
| 333 | 333 | |
| 334 | 334 | static struct dma_buf *system_heap_allocate(struct dma_heap *heap, |
| 335 | 335 | unsigned long len, |
| 336 | − unsigned long fd_flags, | |
| 337 | − unsigned long heap_flags) | |
| 336 | + u32 fd_flags, | |
| 337 | + u64 heap_flags) | |
| 338 | 338 | { |
| 339 | 339 | struct system_heap_buffer *buffer; |
| 340 | 340 | DEFINE_DMA_BUF_EXPORT_INFO(exp_info); |
| @@ -79,6 +79,7 @@ config DRM_KUNIT_TEST · 78 unmodified lines | ||
| 79 | 79 | depends on DRM && KUNIT && MMU |
| 80 | 80 | select DRM_BUDDY |
| 81 | 81 | select DRM_DISPLAY_DP_HELPER |
| 82 | + select DRM_DISPLAY_HDMI_STATE_HELPER | |
| 82 | 83 | select DRM_DISPLAY_HELPER |
| 83 | 84 | select DRM_EXEC |
| 84 | 85 | select DRM_EXPORT_FOR_TESTS if m |
| @@ -106,7 +107,7 @@ config DRM_KMS_HELPER · 21 unmodified lines | ||
| 106 | 107 | |
| 107 | 108 | config DRM_PANIC |
| 108 | 109 | bool "Display a user-friendly message when a kernel panic occurs" |
| 109 | − depends on DRM && !FRAMEBUFFER_CONSOLE | |
| 110 | + depends on DRM && !(FRAMEBUFFER_CONSOLE && VT_CONSOLE) | |
| 110 | 111 | select DRM_KMS_HELPER |
| 111 | 112 | select FONT_SUPPORT |
| 112 | 113 | help |
| @@ -136,6 +137,19 @@ config DRM_PANIC_DEBUG · 23 unmodified lines | ||
| 136 | 137 | This is unsafe and should not be enabled on a production build. |
| 137 | 138 | If in doubt, say "N". |
| 138 | 139 | |
| 140 | +config DRM_PANIC_SCREEN | |
| 141 | + string "Panic screen formater" | |
| 142 | + default "user" | |
| 143 | + depends on DRM_PANIC | |
| 144 | + help | |
| 145 | + This option enable to choose what will be displayed when a kernel | |
| 146 | + panic occurs. You can choose between "user", a short message telling | |
| 147 | + the user to reboot the system, or "kmsg" which will display the last | |
| 148 | + lines of kmsg. | |
| 149 | + This can also be overridden by drm.panic_screen=xxxx kernel parameter | |
| 150 | + or by writing to /sys/module/drm/parameters/panic_screen sysfs entry | |
| 151 | + Default is "user" | |
| 152 | + | |
| 139 | 153 | config DRM_DEBUG_DP_MST_TOPOLOGY_REFS |
| 140 | 154 | bool "Enable refcount backtrace history in the DP MST helpers" |
| 141 | 155 | depends on STACKTRACE_SUPPORT |
| @@ -108,6 +108,7 @@ drm_dma_helper-$(CONFIG_DRM_KMS_HELPER) += drm_fb_dma_helper.o · 107 unmodified lines | ||
| 108 | 108 | obj-$(CONFIG_DRM_GEM_DMA_HELPER) += drm_dma_helper.o |
| 109 | 109 | |
| 110 | 110 | drm_shmem_helper-y := drm_gem_shmem_helper.o |
| 111 | +drm_shmem_helper-$(CONFIG_DRM_FBDEV_EMULATION) += drm_fbdev_shmem.o | |
| 111 | 112 | obj-$(CONFIG_DRM_GEM_SHMEM_HELPER) += drm_shmem_helper.o |
| 112 | 113 | |
| 113 | 114 | drm_suballoc_helper-y := drm_suballoc.o |
| @@ -117,6 +118,7 @@ drm_vram_helper-y := drm_gem_vram_helper.o · 3 unmodified lines | ||
| 117 | 118 | obj-$(CONFIG_DRM_VRAM_HELPER) += drm_vram_helper.o |
| 118 | 119 | |
| 119 | 120 | drm_ttm_helper-y := drm_gem_ttm_helper.o |
| 121 | +drm_ttm_helper-$(CONFIG_DRM_FBDEV_EMULATION) += drm_fbdev_ttm.o | |
| 120 | 122 | obj-$(CONFIG_DRM_TTM_HELPER) += drm_ttm_helper.o |
| 121 | 123 | |
| 122 | 124 | # |
| @@ -142,9 +144,7 @@ drm_kms_helper-y := \ · 19 unmodified lines | ||
| 142 | 144 | drm_self_refresh_helper.o \ |
| 143 | 145 | drm_simple_kms_helper.o |
| 144 | 146 | drm_kms_helper-$(CONFIG_DRM_PANEL_BRIDGE) += bridge/panel.o |
| 145 | −drm_kms_helper-$(CONFIG_DRM_FBDEV_EMULATION) += \ | |
| 146 | − drm_fbdev_generic.o \ | |
| 147 | − drm_fb_helper.o | |
| 147 | +drm_kms_helper-$(CONFIG_DRM_FBDEV_EMULATION) += drm_fb_helper.o | |
| 148 | 148 | obj-$(CONFIG_DRM_KMS_HELPER) += drm_kms_helper.o |
| 149 | 149 | |
| 150 | 150 | # |
| @@ -246,22 +246,6 @@ amdgpu_connector_find_encoder(struct drm_connector *connector, · 245 unmodified lines | ||
| 246 | 246 | return NULL; |
| 247 | 247 | } |
| 248 | 248 | |
| 249 | −struct edid *amdgpu_connector_edid(struct drm_connector *connector) | |
| 250 | −{ | |
| 251 | − struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); | |
| 252 | − struct drm_property_blob *edid_blob = connector->edid_blob_ptr; | |
| 253 | − | |
| 254 | − if (amdgpu_connector->edid) { | |
| 255 | − return amdgpu_connector->edid; | |
| 256 | − } else if (edid_blob) { | |
| 257 | − struct edid *edid = kmemdup(edid_blob->data, edid_blob->length, GFP_KERNEL); | |
| 258 | − | |
| 259 | − if (edid) | |
| 260 | − amdgpu_connector->edid = edid; | |
| 261 | − } | |
| 262 | − return amdgpu_connector->edid; | |
| 263 | −} | |
| 264 | − | |
| 265 | 249 | static struct edid * |
| 266 | 250 | amdgpu_connector_get_hardcoded_edid(struct amdgpu_device *adev) |
| 267 | 251 | { |
| @@ -24,7 +24,6 @@ · 23 unmodified lines | ||
| 24 | 24 | #ifndef __AMDGPU_CONNECTORS_H__ |
| 25 | 25 | #define __AMDGPU_CONNECTORS_H__ |
| 26 | 26 | |
| 27 | −struct edid *amdgpu_connector_edid(struct drm_connector *connector); | |
| 28 | 27 | void amdgpu_connector_hotplug(struct drm_connector *connector); |
| 29 | 28 | int amdgpu_connector_get_monitor_bpc(struct drm_connector *connector); |
| 30 | 29 | u16 amdgpu_connector_encoder_get_dp_bridge_encoder_id(struct drm_connector *connector); |
| @@ -24,7 +24,7 @@ · 23 unmodified lines | ||
| 24 | 24 | |
| 25 | 25 | #include <drm/amdgpu_drm.h> |
| 26 | 26 | #include <drm/drm_drv.h> |
| 27 | −#include <drm/drm_fbdev_generic.h> | |
| 27 | +#include <drm/drm_fbdev_ttm.h> | |
| 28 | 28 | #include <drm/drm_gem.h> |
| 29 | 29 | #include <drm/drm_managed.h> |
| 30 | 30 | #include <drm/drm_pciids.h> |
| @@ -2346,9 +2346,9 @@ retry_init: · 2315 unmodified lines | ||
| 2346 | 2346 | !list_empty(&adev_to_drm(adev)->mode_config.connector_list)) { |
| 2347 | 2347 | /* select 8 bpp console on low vram cards */ |
| 2348 | 2348 | if (adev->gmc.real_vram_size <= (32*1024*1024)) |
| 2349 | − drm_fbdev_generic_setup(adev_to_drm(adev), 8); | |
| 2349 | + drm_fbdev_ttm_setup(adev_to_drm(adev), 8); | |
| 2350 | 2350 | else |
| 2351 | − drm_fbdev_generic_setup(adev_to_drm(adev), 32); | |
| 2351 | + drm_fbdev_ttm_setup(adev_to_drm(adev), 32); | |
| 2352 | 2352 | } |
| 2353 | 2353 | |
| 2354 | 2354 | ret = amdgpu_debugfs_init(adev); |
| @@ -65,9 +65,7 @@ static enum hrtimer_restart amdgpu_vkms_vblank_simulate(struct hrtimer *timer) · 64 unmodified lines | ||
| 65 | 65 | |
| 66 | 66 | static int amdgpu_vkms_enable_vblank(struct drm_crtc *crtc) |
| 67 | 67 | { |
| 68 | − struct drm_device *dev = crtc->dev; | |
| 69 | − unsigned int pipe = drm_crtc_index(crtc); | |
| 70 | − struct drm_vblank_crtc *vblank = &dev->vblank[pipe]; | |
| 68 | + struct drm_vblank_crtc *vblank = drm_crtc_vblank_crtc(crtc); | |
| 71 | 69 | struct amdgpu_vkms_output *out = drm_crtc_to_amdgpu_vkms_output(crtc); |
| 72 | 70 | struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); |
| 73 | 71 | |
| @@ -91,10 +89,8 @@ static bool amdgpu_vkms_get_vblank_timestamp(struct drm_crtc *crtc, · 17 unmodified lines | ||
| 91 | 89 | ktime_t *vblank_time, |
| 92 | 90 | bool in_vblank_irq) |
| 93 | 91 | { |
| 94 | − struct drm_device *dev = crtc->dev; | |
| 95 | − unsigned int pipe = crtc->index; | |
| 96 | 92 | struct amdgpu_vkms_output *output = drm_crtc_to_amdgpu_vkms_output(crtc); |
| 97 | − struct drm_vblank_crtc *vblank = &dev->vblank[pipe]; | |
| 93 | + struct drm_vblank_crtc *vblank = drm_crtc_vblank_crtc(crtc); | |
| 98 | 94 | struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); |
| 99 | 95 | |
| 100 | 96 | if (!READ_ONCE(vblank->enabled)) { |
| @@ -1299,7 +1299,7 @@ static void dce_v10_0_audio_write_speaker_allocation(struct drm_encoder *encoder · 1298 unmodified lines | ||
| 1299 | 1299 | return; |
| 1300 | 1300 | } |
| 1301 | 1301 | |
| 1302 | − sad_count = drm_edid_to_speaker_allocation(amdgpu_connector_edid(connector), &sadb); | |
| 1302 | + sad_count = drm_edid_to_speaker_allocation(amdgpu_connector->edid, &sadb); | |
| 1303 | 1303 | if (sad_count < 0) { |
| 1304 | 1304 | DRM_ERROR("Couldn't read Speaker Allocation Data Block: %d\n", sad_count); |
| 1305 | 1305 | sad_count = 0; |
| @@ -1369,7 +1369,7 @@ static void dce_v10_0_audio_write_sad_regs(struct drm_encoder *encoder) · 63 unmodified lines | ||
| 1369 | 1369 | return; |
| 1370 | 1370 | } |
| 1371 | 1371 | |
| 1372 | − sad_count = drm_edid_to_sad(amdgpu_connector_edid(connector), &sads); | |
| 1372 | + sad_count = drm_edid_to_sad(amdgpu_connector->edid, &sads); | |
| 1373 | 1373 | if (sad_count < 0) |
| 1374 | 1374 | DRM_ERROR("Couldn't read SADs: %d\n", sad_count); |
| 1375 | 1375 | if (sad_count <= 0) |
| @@ -1331,7 +1331,7 @@ static void dce_v11_0_audio_write_speaker_allocation(struct drm_encoder *encoder · 1330 unmodified lines | ||
| 1331 | 1331 | return; |
| 1332 | 1332 | } |
| 1333 | 1333 | |
| 1334 | − sad_count = drm_edid_to_speaker_allocation(amdgpu_connector_edid(connector), &sadb); | |
| 1334 | + sad_count = drm_edid_to_speaker_allocation(amdgpu_connector->edid, &sadb); | |
| 1335 | 1335 | if (sad_count < 0) { |
| 1336 | 1336 | DRM_ERROR("Couldn't read Speaker Allocation Data Block: %d\n", sad_count); |
| 1337 | 1337 | sad_count = 0; |
| @@ -1401,7 +1401,7 @@ static void dce_v11_0_audio_write_sad_regs(struct drm_encoder *encoder) · 63 unmodified lines | ||
| 1401 | 1401 | return; |
| 1402 | 1402 | } |
| 1403 | 1403 | |
| 1404 | − sad_count = drm_edid_to_sad(amdgpu_connector_edid(connector), &sads); | |
| 1404 | + sad_count = drm_edid_to_sad(amdgpu_connector->edid, &sads); | |
| 1405 | 1405 | if (sad_count < 0) |
| 1406 | 1406 | DRM_ERROR("Couldn't read SADs: %d\n", sad_count); |
| 1407 | 1407 | if (sad_count <= 0) |
| @@ -1217,7 +1217,7 @@ static void dce_v6_0_audio_write_speaker_allocation(struct drm_encoder *encoder) · 1216 unmodified lines | ||
| 1217 | 1217 | return; |
| 1218 | 1218 | } |
| 1219 | 1219 | |
| 1220 | − sad_count = drm_edid_to_speaker_allocation(amdgpu_connector_edid(connector), &sadb); | |
| 1220 | + sad_count = drm_edid_to_speaker_allocation(amdgpu_connector->edid, &sadb); | |
| 1221 | 1221 | if (sad_count < 0) { |
| 1222 | 1222 | DRM_ERROR("Couldn't read Speaker Allocation Data Block: %d\n", sad_count); |
| 1223 | 1223 | sad_count = 0; |
| @@ -1292,7 +1292,7 @@ static void dce_v6_0_audio_write_sad_regs(struct drm_encoder *encoder) · 68 unmodified lines | ||
| 1292 | 1292 | return; |
| 1293 | 1293 | } |
| 1294 | 1294 | |
| 1295 | − sad_count = drm_edid_to_sad(amdgpu_connector_edid(connector), &sads); | |
| 1295 | + sad_count = drm_edid_to_sad(amdgpu_connector->edid, &sads); | |
| 1296 | 1296 | if (sad_count < 0) |
| 1297 | 1297 | DRM_ERROR("Couldn't read SADs: %d\n", sad_count); |
| 1298 | 1298 | if (sad_count <= 0) |
| @@ -1272,7 +1272,7 @@ static void dce_v8_0_audio_write_speaker_allocation(struct drm_encoder *encoder) · 1271 unmodified lines | ||
| 1272 | 1272 | return; |
| 1273 | 1273 | } |
| 1274 | 1274 | |
| 1275 | − sad_count = drm_edid_to_speaker_allocation(amdgpu_connector_edid(connector), &sadb); | |
| 1275 | + sad_count = drm_edid_to_speaker_allocation(amdgpu_connector->edid, &sadb); | |
| 1276 | 1276 | if (sad_count < 0) { |
| 1277 | 1277 | DRM_ERROR("Couldn't read Speaker Allocation Data Block: %d\n", sad_count); |
| 1278 | 1278 | sad_count = 0; |
| @@ -1340,7 +1340,7 @@ static void dce_v8_0_audio_write_sad_regs(struct drm_encoder *encoder) · 61 unmodified lines | ||
| 1340 | 1340 | return; |
| 1341 | 1341 | } |
| 1342 | 1342 | |
| 1343 | − sad_count = drm_edid_to_sad(amdgpu_connector_edid(connector), &sads); | |
| 1343 | + sad_count = drm_edid_to_sad(amdgpu_connector->edid, &sads); | |
| 1344 | 1344 | if (sad_count < 0) |
| 1345 | 1345 | DRM_ERROR("Couldn't read SADs: %d\n", sad_count); |
| 1346 | 1346 | if (sad_count <= 0) |
| @@ -534,7 +534,7 @@ static void dm_vupdate_high_irq(void *interrupt_params) · 533 unmodified lines | ||
| 534 | 534 | if (acrtc) { |
| 535 | 535 | vrr_active = amdgpu_dm_crtc_vrr_active_irq(acrtc); |
| 536 | 536 | drm_dev = acrtc->base.dev; |
| 537 | − vblank = &drm_dev->vblank[acrtc->base.index]; | |
| 537 | + vblank = drm_crtc_vblank_crtc(&acrtc->base); | |
| 538 | 538 | previous_timestamp = atomic64_read(&irq_params->previous_timestamp); |
| 539 | 539 | frame_duration_ns = vblank->time - previous_timestamp; |
| 540 | 540 | |
| @@ -5,6 +5,7 @@ · 4 unmodified lines | ||
| 5 | 5 | * |
| 6 | 6 | */ |
| 7 | 7 | #include <linux/clk.h> |
| 8 | +#include <linux/of.h> | |
| 8 | 9 | #include <linux/pm_runtime.h> |
| 9 | 10 | #include <linux/spinlock.h> |
| 10 | 11 | |
| @@ -294,7 +295,6 @@ komeda_crtc_flush_and_wait_for_flip_done(struct komeda_crtc *kcrtc, · 283 unmodified lines | ||
| 294 | 295 | struct komeda_dev *mdev = kcrtc->master->mdev; |
| 295 | 296 | struct completion *flip_done; |
| 296 | 297 | struct completion temp; |
| 297 | − int timeout; | |
| 298 | 298 | |
| 299 | 299 | /* if caller doesn't send a flip_done, use a private flip_done */ |
| 300 | 300 | if (input_flip_done) { |
| @@ -308,8 +308,7 @@ komeda_crtc_flush_and_wait_for_flip_done(struct komeda_crtc *kcrtc, · 7 unmodified lines | ||
| 308 | 308 | mdev->funcs->flush(mdev, kcrtc->master->id, 0); |
| 309 | 309 | |
| 310 | 310 | /* wait the flip take affect.*/ |
| 311 | − timeout = wait_for_completion_timeout(flip_done, HZ); | |
| 312 | − if (timeout == 0) { | |
| 311 | + if (wait_for_completion_timeout(flip_done, HZ) == 0) { | |
| 313 | 312 | DRM_ERROR("wait pipe%d flip done timeout\n", kcrtc->master->id); |
| 314 | 313 | if (!input_flip_done) { |
| 315 | 314 | unsigned long flags; |
| @@ -610,12 +609,34 @@ get_crtc_primary(struct komeda_kms_dev *kms, struct komeda_crtc *crtc) · 294 unmodified lines | ||
| 610 | 609 | return NULL; |
| 611 | 610 | } |
| 612 | 611 | |
| 612 | +static int komeda_attach_bridge(struct device *dev, | |
| 613 | + struct komeda_pipeline *pipe, | |
| 614 | + struct drm_encoder *encoder) | |
| 615 | +{ | |
| 616 | + struct drm_bridge *bridge; | |
| 617 | + int err; | |
| 618 | + | |
| 619 | + bridge = devm_drm_of_get_bridge(dev, pipe->of_node, | |
| 620 | + KOMEDA_OF_PORT_OUTPUT, 0); | |
| 621 | + if (IS_ERR(bridge)) | |
| 622 | + return dev_err_probe(dev, PTR_ERR(bridge), "remote bridge not found for pipe: %s\n", | |
| 623 | + of_node_full_name(pipe->of_node)); | |
| 624 | + | |
| 625 | + err = drm_bridge_attach(encoder, bridge, NULL, 0); | |
| 626 | + if (err) | |
| 627 | + dev_err(dev, "bridge_attach() failed for pipe: %s\n", | |
| 628 | + of_node_full_name(pipe->of_node)); | |
| 629 | + | |
| 630 | + return err; | |
| 631 | +} | |
| 632 | + | |
| 613 | 633 | static int komeda_crtc_add(struct komeda_kms_dev *kms, |
| 614 | 634 | struct komeda_crtc *kcrtc) |
| 615 | 635 | { |
| 616 | 636 | struct drm_crtc *crtc = &kcrtc->base; |
| 617 | 637 | struct drm_device *base = &kms->base; |
| 618 | − struct drm_bridge *bridge; | |
| 638 | + struct komeda_pipeline *pipe = kcrtc->master; | |
| 639 | + struct drm_encoder *encoder = &kcrtc->encoder; | |
| 619 | 640 | int err; |
| 620 | 641 | |
| 621 | 642 | err = drm_crtc_init_with_planes(base, crtc, |
| @@ -626,27 +647,27 @@ static int komeda_crtc_add(struct komeda_kms_dev *kms, · 4 unmodified lines | ||
| 626 | 647 | |
| 627 | 648 | drm_crtc_helper_add(crtc, &komeda_crtc_helper_funcs); |
| 628 | 649 | |
| 629 | − crtc->port = kcrtc->master->of_output_port; | |
| 650 | + crtc->port = pipe->of_output_port; | |
| 630 | 651 | |
| 631 | 652 | /* Construct an encoder for each pipeline and attach it to the remote |
| 632 | 653 | * bridge |
| 633 | 654 | */ |
| 634 | 655 | kcrtc->encoder.possible_crtcs = drm_crtc_mask(crtc); |
| 635 | − err = drm_simple_encoder_init(base, &kcrtc->encoder, | |
| 636 | − DRM_MODE_ENCODER_TMDS); | |
| 656 | + err = drm_simple_encoder_init(base, encoder, DRM_MODE_ENCODER_TMDS); | |
| 637 | 657 | if (err) |
| 638 | 658 | return err; |
| 639 | 659 | |
| 640 | − bridge = devm_drm_of_get_bridge(base->dev, kcrtc->master->of_node, | |
| 641 | − KOMEDA_OF_PORT_OUTPUT, 0); | |
| 642 | − if (IS_ERR(bridge)) | |
| 643 | − return PTR_ERR(bridge); | |
| 644 | − | |
| 645 | − err = drm_bridge_attach(&kcrtc->encoder, bridge, NULL, 0); | |
| 660 | + if (pipe->of_output_links[0]) { | |
| 661 | + err = komeda_attach_bridge(base->dev, pipe, encoder); | |
| 662 | + if (err) | |
| 663 | + return err; | |
| 664 | + } | |
| 646 | 665 | |
| 647 | 666 | drm_crtc_enable_color_mgmt(crtc, 0, true, KOMEDA_COLOR_LUT_SIZE); |
| 648 | 667 | |
| 649 | − return err; | |
| 668 | + komeda_pipeline_dump(pipe); | |
| 669 | + | |
| 670 | + return 0; | |
| 650 | 671 | } |
| 651 | 672 | |
| 652 | 673 | int komeda_kms_add_crtcs(struct komeda_kms_dev *kms, struct komeda_dev *mdev) |
| @@ -9,7 +9,7 @@ · 8 unmodified lines | ||
| 9 | 9 | #include <linux/of.h> |
| 10 | 10 | #include <linux/platform_device.h> |
| 11 | 11 | #include <linux/pm_runtime.h> |
| 12 | −#include <drm/drm_fbdev_generic.h> | |
| 12 | +#include <drm/drm_fbdev_dma.h> | |
| 13 | 13 | #include <drm/drm_module.h> |
| 14 | 14 | #include <drm/drm_of.h> |
| 15 | 15 | #include "komeda_dev.h" |
| @@ -59,6 +59,10 @@ static int komeda_platform_probe(struct platform_device *pdev) · 43 unmodified lines | ||
| 59 | 59 | struct komeda_drv *mdrv; |
| 60 | 60 | int err; |
| 61 | 61 | |
| 62 | + err = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(40)); | |
| 63 | + if (err) | |
| 64 | + return dev_err_probe(dev, err, "DMA mask error\n"); | |
| 65 | + | |
| 62 | 66 | mdrv = devm_kzalloc(dev, sizeof(*mdrv), GFP_KERNEL); |
| 63 | 67 | if (!mdrv) |
| 64 | 68 | return -ENOMEM; |
| @@ -80,7 +84,7 @@ static int komeda_platform_probe(struct platform_device *pdev) · 15 unmodified lines | ||
| 80 | 84 | } |
| 81 | 85 | |
| 82 | 86 | dev_set_drvdata(dev, mdrv); |
| 83 | − drm_fbdev_generic_setup(&mdrv->kms->base, 32); | |
| 87 | + drm_fbdev_dma_setup(&mdrv->kms->base, 32); | |
| 84 | 88 | |
| 85 | 89 | return 0; |
| 86 | 90 | |
| @@ -191,5 +191,6 @@ void komeda_crtc_flush_and_wait_for_flip_done(struct komeda_crtc *kcrtc, · 190 unmodified lines | ||
| 191 | 191 | struct komeda_kms_dev *komeda_kms_attach(struct komeda_dev *mdev); |
| 192 | 192 | void komeda_kms_detach(struct komeda_kms_dev *kms); |
| 193 | 193 | void komeda_kms_shutdown(struct komeda_kms_dev *kms); |
| 194 | +void komeda_pipeline_dump(struct komeda_pipeline *pipe); | |
| 194 | 195 | |
| 195 | 196 | #endif /*_KOMEDA_KMS_H_*/ |
| @@ -10,6 +10,7 @@ · 9 unmodified lines | ||
| 10 | 10 | #include <drm/drm_print.h> |
| 11 | 11 | |
| 12 | 12 | #include "komeda_dev.h" |
| 13 | +#include "komeda_kms.h" | |
| 13 | 14 | #include "komeda_pipeline.h" |
| 14 | 15 | |
| 15 | 16 | /** komeda_pipeline_add - Add a pipeline to &komeda_dev */ |
| @@ -247,7 +248,7 @@ static void komeda_component_dump(struct komeda_component *c) · 231 unmodified lines | ||
| 247 | 248 | c->max_active_outputs, c->supported_outputs); |
| 248 | 249 | } |
| 249 | 250 | |
| 250 | −static void komeda_pipeline_dump(struct komeda_pipeline *pipe) | |
| 251 | +void komeda_pipeline_dump(struct komeda_pipeline *pipe) | |
| 251 | 252 | { |
| 252 | 253 | struct komeda_component *c; |
| 253 | 254 | int id; |
| @@ -351,7 +352,6 @@ int komeda_assemble_pipelines(struct komeda_dev *mdev) · 97 unmodified lines | ||
| 351 | 352 | pipe = mdev->pipelines[i]; |
| 352 | 353 | |
| 353 | 354 | komeda_pipeline_assemble(pipe); |
| 354 | − komeda_pipeline_dump(pipe); | |
| 355 | 355 | } |
| 356 | 356 | |
| 357 | 357 | return 0; |
| @@ -33,7 +33,7 @@ · 32 unmodified lines | ||
| 33 | 33 | #include <drm/drm_aperture.h> |
| 34 | 34 | #include <drm/drm_atomic_helper.h> |
| 35 | 35 | #include <drm/drm_drv.h> |
| 36 | −#include <drm/drm_fbdev_generic.h> | |
| 36 | +#include <drm/drm_fbdev_shmem.h> | |
| 37 | 37 | #include <drm/drm_gem_shmem_helper.h> |
| 38 | 38 | #include <drm/drm_module.h> |
| 39 | 39 | #include <drm/drm_probe_helper.h> |
| @@ -360,7 +360,7 @@ static int ast_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent) · 320 unmodified lines | ||
| 360 | 360 | if (ret) |
| 361 | 361 | return ret; |
| 362 | 362 | |
| 363 | − drm_fbdev_generic_setup(drm, 32); | |
| 363 | + drm_fbdev_shmem_setup(drm, 32); | |
| 364 | 364 | |
| 365 | 365 | return 0; |
| 366 | 366 | } |
| @@ -1,7 +1,7 @@ | ||
| 1 | 1 | # SPDX-License-Identifier: GPL-2.0-only |
| 2 | 2 | config DRM_ATMEL_HLCDC |
| 3 | 3 | tristate "DRM Support for ATMEL HLCDC Display Controller" |
| 4 | − depends on DRM && OF && COMMON_CLK && MFD_ATMEL_HLCDC && ARM | |
| 4 | + depends on DRM && OF && COMMON_CLK && ((MFD_ATMEL_HLCDC && ARM) || COMPILE_TEST) | |
| 5 | 5 | select DRM_GEM_DMA_HELPER |
| 6 | 6 | select DRM_KMS_HELPER |
| 7 | 7 | select DRM_PANEL |
| @@ -30,10 +30,12 @@ · 29 unmodified lines | ||
| 30 | 30 | * |
| 31 | 31 | * @base: base CRTC state |
| 32 | 32 | * @output_mode: RGBXXX output mode |
| 33 | + * @dpi: output DPI mode | |
| 33 | 34 | */ |
| 34 | 35 | struct atmel_hlcdc_crtc_state { |
| 35 | 36 | struct drm_crtc_state base; |
| 36 | 37 | unsigned int output_mode; |
| 38 | + u8 dpi; | |
| 37 | 39 | }; |
| 38 | 40 | |
| 39 | 41 | static inline struct atmel_hlcdc_crtc_state * |
| @@ -164,18 +166,24 @@ static void atmel_hlcdc_crtc_mode_set_nofb(struct drm_crtc *c) · 124 unmodified lines | ||
| 164 | 166 | state = drm_crtc_state_to_atmel_hlcdc_crtc_state(c->state); |
| 165 | 167 | cfg = state->output_mode << 8; |
| 166 | 168 | |
| 167 | − if (adj->flags & DRM_MODE_FLAG_NVSYNC) | |
| 168 | − cfg |= ATMEL_HLCDC_VSPOL; | |
| 169 | + if (!crtc->dc->desc->is_xlcdc) { | |
| 170 | + if (adj->flags & DRM_MODE_FLAG_NVSYNC) | |
| 171 | + cfg |= ATMEL_HLCDC_VSPOL; | |
| 169 | 172 | |
| 170 | − if (adj->flags & DRM_MODE_FLAG_NHSYNC) | |
| 171 | − cfg |= ATMEL_HLCDC_HSPOL; | |
| 173 | + if (adj->flags & DRM_MODE_FLAG_NHSYNC) | |
| 174 | + cfg |= ATMEL_HLCDC_HSPOL; | |
| 175 | + } else { | |
| 176 | + cfg |= state->dpi << 11; | |
| 177 | + } | |
| 172 | 178 | |
| 173 | 179 | regmap_update_bits(regmap, ATMEL_HLCDC_CFG(5), |
| 174 | 180 | ATMEL_HLCDC_HSPOL | ATMEL_HLCDC_VSPOL | |
| 175 | 181 | ATMEL_HLCDC_VSPDLYS | ATMEL_HLCDC_VSPDLYE | |
| 176 | 182 | ATMEL_HLCDC_DISPPOL | ATMEL_HLCDC_DISPDLY | |
| 177 | 183 | ATMEL_HLCDC_VSPSU | ATMEL_HLCDC_VSPHO | |
| 178 | − ATMEL_HLCDC_GUARDTIME_MASK | ATMEL_HLCDC_MODE_MASK, | |
| 184 | + ATMEL_HLCDC_GUARDTIME_MASK | | |
| 185 | + (crtc->dc->desc->is_xlcdc ? ATMEL_XLCDC_MODE_MASK | | |
| 186 | + ATMEL_XLCDC_DPI : ATMEL_HLCDC_MODE_MASK), | |
| 179 | 187 | cfg); |
| 180 | 188 | |
| 181 | 189 | clk_disable_unprepare(crtc->dc->hlcdc->sys_clk); |
| @@ -202,20 +210,37 @@ static void atmel_hlcdc_crtc_atomic_disable(struct drm_crtc *c, · 20 unmodified lines | ||
| 202 | 210 | |
| 203 | 211 | pm_runtime_get_sync(dev->dev); |
| 204 | 212 | |
| 213 | + if (crtc->dc->desc->is_xlcdc) { | |
| 214 | + regmap_write(regmap, ATMEL_HLCDC_DIS, ATMEL_XLCDC_CM); | |
| 215 | + if (regmap_read_poll_timeout(regmap, ATMEL_HLCDC_SR, status, | |
| 216 | + !(status & ATMEL_XLCDC_CM), | |
| 217 | + 10, 1000)) | |
| 218 | + dev_warn(dev->dev, "Atmel LCDC status register CMSTS timeout\n"); | |
| 219 | + | |
| 220 | + regmap_write(regmap, ATMEL_HLCDC_DIS, ATMEL_XLCDC_SD); | |
| 221 | + if (regmap_read_poll_timeout(regmap, ATMEL_HLCDC_SR, status, | |
| 222 | + status & ATMEL_XLCDC_SD, | |
| 223 | + 10, 1000)) | |
| 224 | + dev_warn(dev->dev, "Atmel LCDC status register SDSTS timeout\n"); | |
| 225 | + } | |
| 226 | + | |
| 205 | 227 | regmap_write(regmap, ATMEL_HLCDC_DIS, ATMEL_HLCDC_DISP); |
| 206 | − while (!regmap_read(regmap, ATMEL_HLCDC_SR, &status) && | |
| 207 | − (status & ATMEL_HLCDC_DISP)) | |
| 208 | − cpu_relax(); | |
| 228 | + if (regmap_read_poll_timeout(regmap, ATMEL_HLCDC_SR, status, | |
| 229 | + !(status & ATMEL_HLCDC_DISP), | |
| 230 | + 10, 1000)) | |
| 231 | + dev_warn(dev->dev, "Atmel LCDC status register DISPSTS timeout\n"); | |
| 209 | 232 | |
| 210 | 233 | regmap_write(regmap, ATMEL_HLCDC_DIS, ATMEL_HLCDC_SYNC); |
| 211 | − while (!regmap_read(regmap, ATMEL_HLCDC_SR, &status) && | |
| 212 | − (status & ATMEL_HLCDC_SYNC)) | |
| 213 | − cpu_relax(); | |
| 234 | + if (regmap_read_poll_timeout(regmap, ATMEL_HLCDC_SR, status, | |
| 235 | + !(status & ATMEL_HLCDC_SYNC), | |
| 236 | + 10, 1000)) | |
| 237 | + dev_warn(dev->dev, "Atmel LCDC status register LCDSTS timeout\n"); | |
| 214 | 238 | |
| 215 | 239 | regmap_write(regmap, ATMEL_HLCDC_DIS, ATMEL_HLCDC_PIXEL_CLK); |
| 216 | − while (!regmap_read(regmap, ATMEL_HLCDC_SR, &status) && | |
| 217 | − (status & ATMEL_HLCDC_PIXEL_CLK)) | |
| 218 | − cpu_relax(); | |
| 240 | + if (regmap_read_poll_timeout(regmap, ATMEL_HLCDC_SR, status, | |
| 241 | + !(status & ATMEL_HLCDC_PIXEL_CLK), | |
| 242 | + 10, 1000)) | |
| 243 | + dev_warn(dev->dev, "Atmel LCDC status register CLKSTS timeout\n"); | |
| 219 | 244 | |
| 220 | 245 | clk_disable_unprepare(crtc->dc->hlcdc->sys_clk); |
| 221 | 246 | pinctrl_pm_select_sleep_state(dev->dev); |
| @@ -241,30 +266,95 @@ static void atmel_hlcdc_crtc_atomic_enable(struct drm_crtc *c, · 19 unmodified lines | ||
| 241 | 266 | clk_prepare_enable(crtc->dc->hlcdc->sys_clk); |
| 242 | 267 | |
| 243 | 268 | regmap_write(regmap, ATMEL_HLCDC_EN, ATMEL_HLCDC_PIXEL_CLK); |
| 244 | − while (!regmap_read(regmap, ATMEL_HLCDC_SR, &status) && | |
| 245 | − !(status & ATMEL_HLCDC_PIXEL_CLK)) | |
| 246 | − cpu_relax(); | |
| 247 | − | |
| 269 | + if (regmap_read_poll_timeout(regmap, ATMEL_HLCDC_SR, status, | |
| 270 | + status & ATMEL_HLCDC_PIXEL_CLK, | |
| 271 | + 10, 1000)) | |
| 272 | + dev_warn(dev->dev, "Atmel LCDC status register CLKSTS timeout\n"); | |
| 248 | 273 | |
| 249 | 274 | regmap_write(regmap, ATMEL_HLCDC_EN, ATMEL_HLCDC_SYNC); |
| 250 | − while (!regmap_read(regmap, ATMEL_HLCDC_SR, &status) && | |
| 251 | − !(status & ATMEL_HLCDC_SYNC)) | |
| 252 | − cpu_relax(); | |
| 275 | + if (regmap_read_poll_timeout(regmap, ATMEL_HLCDC_SR, status, | |
| 276 | + status & ATMEL_HLCDC_SYNC, | |
| 277 | + 10, 1000)) | |
| 278 | + dev_warn(dev->dev, "Atmel LCDC status register LCDSTS timeout\n"); | |
| 253 | 279 | |
| 254 | 280 | regmap_write(regmap, ATMEL_HLCDC_EN, ATMEL_HLCDC_DISP); |
| 255 | − while (!regmap_read(regmap, ATMEL_HLCDC_SR, &status) && | |
| 256 | − !(status & ATMEL_HLCDC_DISP)) | |
| 257 | − cpu_relax(); | |
| 281 | + if (regmap_read_poll_timeout(regmap, ATMEL_HLCDC_SR, status, | |
| 282 | + status & ATMEL_HLCDC_DISP, | |
| 283 | + 10, 1000)) | |
| 284 | + dev_warn(dev->dev, "Atmel LCDC status register DISPSTS timeout\n"); | |
| 285 | + | |
| 286 | + if (crtc->dc->desc->is_xlcdc) { | |
| 287 | + regmap_write(regmap, ATMEL_HLCDC_EN, ATMEL_XLCDC_CM); | |
| 288 | + if (regmap_read_poll_timeout(regmap, ATMEL_HLCDC_SR, status, | |
| 289 | + status & ATMEL_XLCDC_CM, | |
| 290 | + 10, 1000)) | |
| 291 | + dev_warn(dev->dev, "Atmel LCDC status register CMSTS timeout\n"); | |
| 292 | + | |
| 293 | + regmap_write(regmap, ATMEL_HLCDC_EN, ATMEL_XLCDC_SD); | |
| 294 | + if (regmap_read_poll_timeout(regmap, ATMEL_HLCDC_SR, status, | |
| 295 | + !(status & ATMEL_XLCDC_SD), | |
| 296 | + 10, 1000)) | |
| 297 | + dev_warn(dev->dev, "Atmel LCDC status register SDSTS timeout\n"); | |
| 298 | + } | |
| 258 | 299 | |
| 259 | 300 | pm_runtime_put_sync(dev->dev); |
| 260 | 301 | |
| 261 | 302 | } |
| 262 | 303 | |
| 263 | −#define ATMEL_HLCDC_RGB444_OUTPUT BIT(0) | |
| 264 | −#define ATMEL_HLCDC_RGB565_OUTPUT BIT(1) | |
| 265 | −#define ATMEL_HLCDC_RGB666_OUTPUT BIT(2) | |
| 266 | −#define ATMEL_HLCDC_RGB888_OUTPUT BIT(3) | |
| 267 | −#define ATMEL_HLCDC_OUTPUT_MODE_MASK GENMASK(3, 0) | |
| 304 | +#define ATMEL_HLCDC_RGB444_OUTPUT BIT(0) | |
| 305 | +#define ATMEL_HLCDC_RGB565_OUTPUT BIT(1) | |
| 306 | +#define ATMEL_HLCDC_RGB666_OUTPUT BIT(2) | |
| 307 | +#define ATMEL_HLCDC_RGB888_OUTPUT BIT(3) | |
| 308 | +#define ATMEL_HLCDC_DPI_RGB565C1_OUTPUT BIT(4) | |
| 309 | +#define ATMEL_HLCDC_DPI_RGB565C2_OUTPUT BIT(5) | |
| 310 | +#define ATMEL_HLCDC_DPI_RGB565C3_OUTPUT BIT(6) | |
| 311 | +#define ATMEL_HLCDC_DPI_RGB666C1_OUTPUT BIT(7) | |
| 312 | +#define ATMEL_HLCDC_DPI_RGB666C2_OUTPUT BIT(8) | |
| 313 | +#define ATMEL_HLCDC_DPI_RGB888_OUTPUT BIT(9) | |
| 314 | +#define ATMEL_HLCDC_OUTPUT_MODE_MASK GENMASK(3, 0) | |
| 315 | +#define ATMEL_XLCDC_OUTPUT_MODE_MASK GENMASK(9, 0) | |
| 316 | + | |
| 317 | +static int atmel_xlcdc_connector_output_dsi(struct drm_encoder *encoder, | |
| 318 | + struct drm_display_info *info) | |
| 319 | +{ | |
| 320 | + int j; | |
| 321 | + unsigned int supported_fmts = 0; | |
| 322 | + | |
| 323 | + switch (atmel_hlcdc_encoder_get_bus_fmt(encoder)) { | |
| 324 | + case 0: | |
| 325 | + break; | |
| 326 | + case MEDIA_BUS_FMT_RGB565_1X16: | |
| 327 | + return ATMEL_HLCDC_DPI_RGB565C1_OUTPUT; | |
| 328 | + case MEDIA_BUS_FMT_RGB666_1X18: | |
| 329 | + return ATMEL_HLCDC_DPI_RGB666C1_OUTPUT; | |
| 330 | + case MEDIA_BUS_FMT_RGB666_1X24_CPADHI: | |
| 331 | + return ATMEL_HLCDC_DPI_RGB666C2_OUTPUT; | |
| 332 | + case MEDIA_BUS_FMT_RGB888_1X24: | |
| 333 | + return ATMEL_HLCDC_DPI_RGB888_OUTPUT; | |
| 334 | + default: | |
| 335 | + return -EINVAL; | |
| 336 | + } | |
| 337 | + | |
| 338 | + for (j = 0; j < info->num_bus_formats; j++) { | |
| 339 | + switch (info->bus_formats[j]) { | |
| 340 | + case MEDIA_BUS_FMT_RGB565_1X16: | |
| 341 | + supported_fmts |= ATMEL_HLCDC_DPI_RGB565C1_OUTPUT; | |
| 342 | + break; | |
| 343 | + case MEDIA_BUS_FMT_RGB666_1X18: | |
| 344 | + supported_fmts |= ATMEL_HLCDC_DPI_RGB666C1_OUTPUT; | |
| 345 | + break; | |
| 346 | + case MEDIA_BUS_FMT_RGB666_1X24_CPADHI: | |
| 347 | + supported_fmts |= ATMEL_HLCDC_DPI_RGB666C2_OUTPUT; | |
| 348 | + break; | |
| 349 | + case MEDIA_BUS_FMT_RGB888_1X24: | |
| 350 | + supported_fmts |= ATMEL_HLCDC_DPI_RGB888_OUTPUT; | |
| 351 | + break; | |
| 352 | + default: | |
| 353 | + break; | |
| 354 | + } | |
| 355 | + } | |
| 356 | + return supported_fmts; | |
| 357 | +} | |
| 268 | 358 | |
| 269 | 359 | static int atmel_hlcdc_connector_output_mode(struct drm_connector_state *state) |
| 270 | 360 | { |
| @@ -277,6 +367,13 @@ static int atmel_hlcdc_connector_output_mode(struct drm_connector_state *state) · 6 unmodified lines | ||
| 277 | 367 | encoder = state->best_encoder; |
| 278 | 368 | if (!encoder) |
| 279 | 369 | encoder = connector->encoder; |
| 370 | + /* | |
| 371 | + * atmel-hlcdc to support DSI formats with DSI video pipeline | |
| 372 | + * when DRM_MODE_ENCODER_DSI type is set by | |
| 373 | + * connector driver component. | |
| 374 | + */ | |
| 375 | + if (encoder->encoder_type == DRM_MODE_ENCODER_DSI) | |
| 376 | + return atmel_xlcdc_connector_output_dsi(encoder, info); | |
| 280 | 377 | |
| 281 | 378 | switch (atmel_hlcdc_encoder_get_bus_fmt(encoder)) { |
| 282 | 379 | case 0: |
| @@ -317,7 +414,7 @@ static int atmel_hlcdc_connector_output_mode(struct drm_connector_state *state) · 34 unmodified lines | ||
| 317 | 414 | |
| 318 | 415 | static int atmel_hlcdc_crtc_select_output_mode(struct drm_crtc_state *state) |
| 319 | 416 | { |
| 320 | − unsigned int output_fmts = ATMEL_HLCDC_OUTPUT_MODE_MASK; | |
| 417 | + unsigned int output_fmts; | |
| 321 | 418 | struct atmel_hlcdc_crtc_state *hstate; |
| 322 | 419 | struct drm_connector_state *cstate; |
| 323 | 420 | struct drm_connector *connector; |
| @@ -325,6 +422,8 @@ static int atmel_hlcdc_crtc_select_output_mode(struct drm_crtc_state *state) · 1 unmodified line | ||
| 325 | 422 | int i; |
| 326 | 423 | |
| 327 | 424 | crtc = drm_crtc_to_atmel_hlcdc_crtc(state->crtc); |
| 425 | + output_fmts = crtc->dc->desc->is_xlcdc ? ATMEL_XLCDC_OUTPUT_MODE_MASK : | |
| 426 | + ATMEL_HLCDC_OUTPUT_MODE_MASK; | |
| 328 | 427 | |
| 329 | 428 | for_each_new_connector_in_state(state->state, connector, cstate, i) { |
| 330 | 429 | unsigned int supported_fmts = 0; |
| @@ -345,7 +444,15 @@ static int atmel_hlcdc_crtc_select_output_mode(struct drm_crtc_state *state) · 14 unmodified lines | ||
| 345 | 444 | |
| 346 | 445 | hstate = drm_crtc_state_to_atmel_hlcdc_crtc_state(state); |
| 347 | 446 | hstate->output_mode = fls(output_fmts) - 1; |
| 348 | − | |
| 447 | + if (crtc->dc->desc->is_xlcdc) { | |
| 448 | + /* check if MIPI DPI bit needs to be set */ | |
| 449 | + if (fls(output_fmts) > 3) { | |
| 450 | + hstate->output_mode -= 4; | |
| 451 | + hstate->dpi = 1; | |
| 452 | + } else { | |
| 453 | + hstate->dpi = 0; | |
| 454 | + } | |
| 455 | + } | |
| 349 | 456 | return 0; |
| 350 | 457 | } |
| 351 | 458 | |
| @@ -449,6 +556,7 @@ static struct drm_crtc_state * · 97 unmodified lines | ||
| 449 | 556 | atmel_hlcdc_crtc_duplicate_state(struct drm_crtc *crtc) |
| 450 | 557 | { |
| 451 | 558 | struct atmel_hlcdc_crtc_state *state, *cur; |
| 559 | + struct atmel_hlcdc_crtc *c = drm_crtc_to_atmel_hlcdc_crtc(crtc); | |
| 452 | 560 | |
| 453 | 561 | if (WARN_ON(!crtc->state)) |
| 454 | 562 | return NULL; |
| @@ -460,6 +568,8 @@ atmel_hlcdc_crtc_duplicate_state(struct drm_crtc *crtc) · 5 unmodified lines | ||
| 460 | 568 | |
| 461 | 569 | cur = drm_crtc_state_to_atmel_hlcdc_crtc_state(crtc->state); |
| 462 | 570 | state->output_mode = cur->output_mode; |
| 571 | + if (c->dc->desc->is_xlcdc) | |
| 572 | + state->dpi = cur->dpi; | |
| 463 | 573 | |
| 464 | 574 | return &state->base; |
| 465 | 575 | } |
| @@ -58,6 +58,7 @@ static const struct atmel_hlcdc_dc_desc atmel_hlcdc_dc_at91sam9n12 = { · 57 unmodified lines | ||
| 58 | 58 | .conflicting_output_formats = true, |
| 59 | 59 | .nlayers = ARRAY_SIZE(atmel_hlcdc_at91sam9n12_layers), |
| 60 | 60 | .layers = atmel_hlcdc_at91sam9n12_layers, |
| 61 | + .ops = &atmel_hlcdc_ops, | |
| 61 | 62 | }; |
| 62 | 63 | |
| 63 | 64 | static const struct atmel_hlcdc_layer_desc atmel_hlcdc_at91sam9x5_layers[] = { |
| @@ -151,6 +152,7 @@ static const struct atmel_hlcdc_dc_desc atmel_hlcdc_dc_at91sam9x5 = { · 87 unmodified lines | ||
| 151 | 152 | .conflicting_output_formats = true, |
| 152 | 153 | .nlayers = ARRAY_SIZE(atmel_hlcdc_at91sam9x5_layers), |
| 153 | 154 | .layers = atmel_hlcdc_at91sam9x5_layers, |
| 155 | + .ops = &atmel_hlcdc_ops, | |
| 154 | 156 | }; |
| 155 | 157 | |
| 156 | 158 | static const struct atmel_hlcdc_layer_desc atmel_hlcdc_sama5d3_layers[] = { |
| @@ -269,6 +271,7 @@ static const struct atmel_hlcdc_dc_desc atmel_hlcdc_dc_sama5d3 = { · 112 unmodified lines | ||
| 269 | 271 | .conflicting_output_formats = true, |
| 270 | 272 | .nlayers = ARRAY_SIZE(atmel_hlcdc_sama5d3_layers), |
| 271 | 273 | .layers = atmel_hlcdc_sama5d3_layers, |
| 274 | + .ops = &atmel_hlcdc_ops, | |
| 272 | 275 | }; |
| 273 | 276 | |
| 274 | 277 | static const struct atmel_hlcdc_layer_desc atmel_hlcdc_sama5d4_layers[] = { |
| @@ -364,6 +367,7 @@ static const struct atmel_hlcdc_dc_desc atmel_hlcdc_dc_sama5d4 = { · 89 unmodified lines | ||
| 364 | 367 | .max_hpw = 0x3ff, |
| 365 | 368 | .nlayers = ARRAY_SIZE(atmel_hlcdc_sama5d4_layers), |
| 366 | 369 | .layers = atmel_hlcdc_sama5d4_layers, |
| 370 | + .ops = &atmel_hlcdc_ops, | |
| 367 | 371 | }; |
| 368 | 372 | |
| 369 | 373 | static const struct atmel_hlcdc_layer_desc atmel_hlcdc_sam9x60_layers[] = { |
| @@ -460,6 +464,103 @@ static const struct atmel_hlcdc_dc_desc atmel_hlcdc_dc_sam9x60 = { · 90 unmodified lines | ||
| 460 | 464 | .fixed_clksrc = true, |
| 461 | 465 | .nlayers = ARRAY_SIZE(atmel_hlcdc_sam9x60_layers), |
| 462 | 466 | .layers = atmel_hlcdc_sam9x60_layers, |
| 467 | + .ops = &atmel_hlcdc_ops, | |
| 468 | +}; | |
| 469 | + | |
| 470 | +static const struct atmel_hlcdc_layer_desc atmel_xlcdc_sam9x75_layers[] = { | |
| 471 | + { | |
| 472 | + .name = "base", | |
| 473 | + .formats = &atmel_hlcdc_plane_rgb_formats, | |
| 474 | + .regs_offset = 0x60, | |
| 475 | + .id = 0, | |
| 476 | + .type = ATMEL_HLCDC_BASE_LAYER, | |
| 477 | + .cfgs_offset = 0x1c, | |
| 478 | + .layout = { | |
| 479 | + .xstride = { 2 }, | |
| 480 | + .default_color = 3, | |
| 481 | + .general_config = 4, | |
| 482 | + .disc_pos = 5, | |
| 483 | + .disc_size = 6, | |
| 484 | + }, | |
| 485 | + .clut_offset = 0x700, | |
| 486 | + }, | |
| 487 | + { | |
| 488 | + .name = "overlay1", | |
| 489 | + .formats = &atmel_hlcdc_plane_rgb_formats, | |
| 490 | + .regs_offset = 0x160, | |
| 491 | + .id = 1, | |
| 492 | + .type = ATMEL_HLCDC_OVERLAY_LAYER, | |
| 493 | + .cfgs_offset = 0x1c, | |
| 494 | + .layout = { | |
| 495 | + .pos = 2, | |
| 496 | + .size = 3, | |
| 497 | + .xstride = { 4 }, | |
| 498 | + .pstride = { 5 }, | |
| 499 | + .default_color = 6, | |
| 500 | + .chroma_key = 7, | |
| 501 | + .chroma_key_mask = 8, | |
| 502 | + .general_config = 9, | |
| 503 | + }, | |
| 504 | + .clut_offset = 0xb00, | |
| 505 | + }, | |
| 506 | + { | |
| 507 | + .name = "overlay2", | |
| 508 | + .formats = &atmel_hlcdc_plane_rgb_formats, | |
| 509 | + .regs_offset = 0x260, | |
| 510 | + .id = 2, | |
| 511 | + .type = ATMEL_HLCDC_OVERLAY_LAYER, | |
| 512 | + .cfgs_offset = 0x1c, | |
| 513 | + .layout = { | |
| 514 | + .pos = 2, | |
| 515 | + .size = 3, | |
| 516 | + .xstride = { 4 }, | |
| 517 | + .pstride = { 5 }, | |
| 518 | + .default_color = 6, | |
| 519 | + .chroma_key = 7, | |
| 520 | + .chroma_key_mask = 8, | |
| 521 | + .general_config = 9, | |
| 522 | + }, | |
| 523 | + .clut_offset = 0xf00, | |
| 524 | + }, | |
| 525 | + { | |
| 526 | + .name = "high-end-overlay", | |
| 527 | + .formats = &atmel_hlcdc_plane_rgb_and_yuv_formats, | |
| 528 | + .regs_offset = 0x360, | |
| 529 | + .id = 3, | |
| 530 | + .type = ATMEL_HLCDC_OVERLAY_LAYER, | |
| 531 | + .cfgs_offset = 0x30, | |
| 532 | + .layout = { | |
| 533 | + .pos = 2, | |
| 534 | + .size = 3, | |
| 535 | + .memsize = 4, | |
| 536 | + .xstride = { 5, 7 }, | |
| 537 | + .pstride = { 6, 8 }, | |
| 538 | + .default_color = 9, | |
| 539 | + .chroma_key = 10, | |
| 540 | + .chroma_key_mask = 11, | |
| 541 | + .general_config = 12, | |
| 542 | + .csc = 16, | |
| 543 | + .scaler_config = 23, | |
| 544 | + .vxs_config = 30, | |
| 545 | + .hxs_config = 31, | |
| 546 | + }, | |
| 547 | + .clut_offset = 0x1300, | |
| 548 | + }, | |
| 549 | +}; | |
| 550 | + | |
| 551 | +static const struct atmel_hlcdc_dc_desc atmel_xlcdc_dc_sam9x75 = { | |
| 552 | + .min_width = 0, | |
| 553 | + .min_height = 0, | |
| 554 | + .max_width = 2048, | |
| 555 | + .max_height = 2048, | |
| 556 | + .max_spw = 0x3ff, | |
| 557 | + .max_vpw = 0x3ff, | |
| 558 | + .max_hpw = 0x3ff, | |
| 559 | + .fixed_clksrc = true, | |
| 560 | + .is_xlcdc = true, | |
| 561 | + .nlayers = ARRAY_SIZE(atmel_xlcdc_sam9x75_layers), | |
| 562 | + .layers = atmel_xlcdc_sam9x75_layers, | |
| 563 | + .ops = &atmel_xlcdc_ops, | |
| 463 | 564 | }; |
| 464 | 565 | |
| 465 | 566 | static const struct of_device_id atmel_hlcdc_of_match[] = { |
| @@ -487,6 +588,10 @@ static const struct of_device_id atmel_hlcdc_of_match[] = { · 21 unmodified lines | ||
| 487 | 588 | .compatible = "microchip,sam9x60-hlcdc", |
| 488 | 589 | .data = &atmel_hlcdc_dc_sam9x60, |
| 489 | 590 | }, |
| 591 | + { | |
| 592 | + .compatible = "microchip,sam9x75-xlcdc", | |
| 593 | + .data = &atmel_xlcdc_dc_sam9x75, | |
| 594 | + }, | |
| 490 | 595 | { /* sentinel */ }, |
| 491 | 596 | }; |
| 492 | 597 | MODULE_DEVICE_TABLE(of, atmel_hlcdc_of_match); |
| @@ -15,6 +15,7 @@ · 14 unmodified lines | ||
| 15 | 15 | |
| 16 | 16 | #include <drm/drm_plane.h> |
| 17 | 17 | |
| 18 | +/* LCD controller common registers */ | |
| 18 | 19 | #define ATMEL_HLCDC_LAYER_CHER 0x0 |
| 19 | 20 | #define ATMEL_HLCDC_LAYER_CHDR 0x4 |
| 20 | 21 | #define ATMEL_HLCDC_LAYER_CHSR 0x8 |
| @@ -128,6 +129,47 @@ · 107 unmodified lines | ||
| 128 | 129 | |
| 129 | 130 | #define ATMEL_HLCDC_MAX_LAYERS 6 |
| 130 | 131 | |
| 132 | +/* XLCDC controller specific registers */ | |
| 133 | +#define ATMEL_XLCDC_LAYER_ENR 0x10 | |
| 134 | +#define ATMEL_XLCDC_LAYER_EN BIT(0) | |
| 135 | + | |
| 136 | +#define ATMEL_XLCDC_LAYER_IER 0x0 | |
| 137 | +#define ATMEL_XLCDC_LAYER_IDR 0x4 | |
| 138 | +#define ATMEL_XLCDC_LAYER_ISR 0xc | |
| 139 | +#define ATMEL_XLCDC_LAYER_OVR_IRQ(p) BIT(2 + (8 * (p))) | |
| 140 | + | |
| 141 | +#define ATMEL_XLCDC_LAYER_PLANE_ADDR(p) (((p) * 0x4) + 0x18) | |
| 142 | + | |
| 143 | +#define ATMEL_XLCDC_LAYER_DMA_CFG 0 | |
| 144 | + | |
| 145 | +#define ATMEL_XLCDC_LAYER_DMA BIT(0) | |
| 146 | +#define ATMEL_XLCDC_LAYER_REP BIT(1) | |
| 147 | +#define ATMEL_XLCDC_LAYER_DISCEN BIT(4) | |
| 148 | + | |
| 149 | +#define ATMEL_XLCDC_LAYER_SFACTC_A0_MULT_AS (4 << 6) | |
| 150 | +#define ATMEL_XLCDC_LAYER_SFACTA_ONE BIT(9) | |
| 151 | +#define ATMEL_XLCDC_LAYER_DFACTC_M_A0_MULT_AS (6 << 11) | |
| 152 | +#define ATMEL_XLCDC_LAYER_DFACTA_ONE BIT(14) | |
| 153 | + | |
| 154 | +#define ATMEL_XLCDC_LAYER_A0_SHIFT 16 | |
| 155 | +#define ATMEL_XLCDC_LAYER_A0(x) \ | |
| 156 | + ((x) << ATMEL_XLCDC_LAYER_A0_SHIFT) | |
| 157 | + | |
| 158 | +#define ATMEL_XLCDC_LAYER_VSCALER_LUMA_ENABLE BIT(0) | |
| 159 | +#define ATMEL_XLCDC_LAYER_VSCALER_CHROMA_ENABLE BIT(1) | |
| 160 | +#define ATMEL_XLCDC_LAYER_HSCALER_LUMA_ENABLE BIT(4) | |
| 161 | +#define ATMEL_XLCDC_LAYER_HSCALER_CHROMA_ENABLE BIT(5) | |
| 162 | + | |
| 163 | +#define ATMEL_XLCDC_LAYER_VXSYCFG_ONE BIT(0) | |
| 164 | +#define ATMEL_XLCDC_LAYER_VXSYTAP2_ENABLE BIT(4) | |
| 165 | +#define ATMEL_XLCDC_LAYER_VXSCCFG_ONE BIT(16) | |
| 166 | +#define ATMEL_XLCDC_LAYER_VXSCTAP2_ENABLE BIT(20) | |
| 167 | + | |
| 168 | +#define ATMEL_XLCDC_LAYER_HXSYCFG_ONE BIT(0) | |
| 169 | +#define ATMEL_XLCDC_LAYER_HXSYTAP2_ENABLE BIT(4) | |
| 170 | +#define ATMEL_XLCDC_LAYER_HXSCCFG_ONE BIT(16) | |
| 171 | +#define ATMEL_XLCDC_LAYER_HXSCTAP2_ENABLE BIT(20) | |
| 172 | + | |
| 131 | 173 | /** |
| 132 | 174 | * Atmel HLCDC Layer registers layout structure |
| 133 | 175 | * |
| @@ -156,6 +198,8 @@ · 22 unmodified lines | ||
| 156 | 198 | * @disc_pos: discard area position register |
| 157 | 199 | * @disc_size: discard area size register |
| 158 | 200 | * @csc: color space conversion register |
| 201 | + * @vxs_config: vertical scalar filter taps control register | |
| 202 | + * @hxs_config: horizontal scalar filter taps control register | |
| 159 | 203 | */ |
| 160 | 204 | struct atmel_hlcdc_layer_cfg_layout { |
| 161 | 205 | int xstride[ATMEL_HLCDC_LAYER_MAX_PLANES]; |
| @@ -175,6 +219,8 @@ struct atmel_hlcdc_layer_cfg_layout { · 13 unmodified lines | ||
| 175 | 219 | int disc_pos; |
| 176 | 220 | int disc_size; |
| 177 | 221 | int csc; |
| 222 | + int vxs_config; | |
| 223 | + int hxs_config; | |
| 178 | 224 | }; |
| 179 | 225 | |
| 180 | 226 | /** |
| @@ -288,6 +334,64 @@ atmel_hlcdc_layer_to_plane(struct atmel_hlcdc_layer *layer) · 107 unmodified lines | ||
| 288 | 334 | return container_of(layer, struct atmel_hlcdc_plane, layer); |
| 289 | 335 | } |
| 290 | 336 | |
| 337 | +/** | |
| 338 | + * struct atmel_hlcdc_dc - Atmel HLCDC Display Controller. | |
| 339 | + * @desc: HLCDC Display Controller description | |
| 340 | + * @dscrpool: DMA coherent pool used to allocate DMA descriptors | |
| 341 | + * @hlcdc: pointer to the atmel_hlcdc structure provided by the MFD device | |
| 342 | + * @crtc: CRTC provided by the display controller | |
| 343 | + * @layers: active HLCDC layers | |
| 344 | + * @suspend: used to store the HLCDC state when entering suspend | |
| 345 | + * @suspend.imr: used to read/write LCDC Interrupt Mask Register | |
| 346 | + * @suspend.state: Atomic commit structure | |
| 347 | + */ | |
| 348 | +struct atmel_hlcdc_dc { | |
| 349 | + const struct atmel_hlcdc_dc_desc *desc; | |
| 350 | + struct dma_pool *dscrpool; | |
| 351 | + struct atmel_hlcdc *hlcdc; | |
| 352 | + struct drm_crtc *crtc; | |
| 353 | + struct atmel_hlcdc_layer *layers[ATMEL_HLCDC_MAX_LAYERS]; | |
| 354 | + struct { | |
| 355 | + u32 imr; | |
| 356 | + struct drm_atomic_state *state; | |
| 357 | + } suspend; | |
| 358 | +}; | |
| 359 | + | |
| 360 | +struct atmel_hlcdc_plane_state; | |
| 361 | + | |
| 362 | +/** | |
| 363 | + * struct atmel_lcdc_dc_ops - describes atmel_lcdc ops group | |
| 364 | + * to differentiate HLCDC and XLCDC IP code support | |
| 365 | + * @plane_setup_scaler: update the vertical and horizontal scaling factors | |
| 366 | + * @update_lcdc_buffers: update the each LCDC layers DMA registers | |
| 367 | + * @lcdc_atomic_disable: disable LCDC interrupts and layers | |
| 368 | + * @lcdc_update_general_settings: update each LCDC layers general | |
| 369 | + * configuration register | |
| 370 | + * @lcdc_atomic_update: enable the LCDC layers and interrupts | |
| 371 | + * @lcdc_csc_init: update the color space conversion co-efficient of | |
| 372 | + * High-end overlay register | |
| 373 | + * @lcdc_irq_dbg: to raise alert incase of interrupt overrun in any LCDC layer | |
| 374 | + */ | |
| 375 | +struct atmel_lcdc_dc_ops { | |
| 376 | + void (*plane_setup_scaler)(struct atmel_hlcdc_plane *plane, | |
| 377 | + struct atmel_hlcdc_plane_state *state); | |
| 378 | + void (*lcdc_update_buffers)(struct atmel_hlcdc_plane *plane, | |
| 379 | + struct atmel_hlcdc_plane_state *state, | |
| 380 | + u32 sr, int i); | |
| 381 | + void (*lcdc_atomic_disable)(struct atmel_hlcdc_plane *plane); | |
| 382 | + void (*lcdc_update_general_settings)(struct atmel_hlcdc_plane *plane, | |
| 383 | + struct atmel_hlcdc_plane_state *state); | |
| 384 | + void (*lcdc_atomic_update)(struct atmel_hlcdc_plane *plane, | |
| 385 | + struct atmel_hlcdc_dc *dc); | |
| 386 | + void (*lcdc_csc_init)(struct atmel_hlcdc_plane *plane, | |
| 387 | + const struct atmel_hlcdc_layer_desc *desc); | |
| 388 | + void (*lcdc_irq_dbg)(struct atmel_hlcdc_plane *plane, | |
| 389 | + const struct atmel_hlcdc_layer_desc *desc); | |
| 390 | +}; | |
| 391 | + | |
| 392 | +extern const struct atmel_lcdc_dc_ops atmel_hlcdc_ops; | |
| 393 | +extern const struct atmel_lcdc_dc_ops atmel_xlcdc_ops; | |
| 394 | + | |
| 291 | 395 | /** |
| 292 | 396 | * Atmel HLCDC Display Controller description structure. |
| 293 | 397 | * |
| @@ -304,8 +408,10 @@ atmel_hlcdc_layer_to_plane(struct atmel_hlcdc_layer *layer) · 10 unmodified lines | ||
| 304 | 408 | * @conflicting_output_formats: true if RGBXXX output formats conflict with |
| 305 | 409 | * each other. |
| 306 | 410 | * @fixed_clksrc: true if clock source is fixed |
| 411 | + * @is_xlcdc: true if XLCDC IP is supported | |
| 307 | 412 | * @layers: a layer description table describing available layers |
| 308 | 413 | * @nlayers: layer description table size |
| 414 | + * @ops: atmel lcdc dc ops | |
| 309 | 415 | */ |
| 310 | 416 | struct atmel_hlcdc_dc_desc { |
| 311 | 417 | int min_width; |
| @@ -317,32 +423,10 @@ struct atmel_hlcdc_dc_desc { · 5 unmodified lines | ||
| 317 | 423 | int max_hpw; |
| 318 | 424 | bool conflicting_output_formats; |
| 319 | 425 | bool fixed_clksrc; |
| 426 | + bool is_xlcdc; | |
| 320 | 427 | const struct atmel_hlcdc_layer_desc *layers; |
| 321 | 428 | int nlayers; |
| 322 | −}; | |
| 323 | − | |
| 324 | −/** | |
| 325 | − * Atmel HLCDC Display Controller. | |
| 326 | − * | |
| 327 | − * @desc: HLCDC Display Controller description | |
| 328 | − * @dscrpool: DMA coherent pool used to allocate DMA descriptors | |
| 329 | − * @hlcdc: pointer to the atmel_hlcdc structure provided by the MFD device | |
| 330 | − * @fbdev: framebuffer device attached to the Display Controller | |
| 331 | − * @crtc: CRTC provided by the display controller | |
| 332 | − * @planes: instantiated planes | |
| 333 | − * @layers: active HLCDC layers | |
| 334 | − * @suspend: used to store the HLCDC state when entering suspend | |
| 335 | − */ | |
| 336 | −struct atmel_hlcdc_dc { | |
| 337 | − const struct atmel_hlcdc_dc_desc *desc; | |
| 338 | − struct dma_pool *dscrpool; | |
| 339 | − struct atmel_hlcdc *hlcdc; | |
| 340 | − struct drm_crtc *crtc; | |
| 341 | − struct atmel_hlcdc_layer *layers[ATMEL_HLCDC_MAX_LAYERS]; | |
| 342 | − struct { | |
| 343 | − u32 imr; | |
| 344 | − struct drm_atomic_state *state; | |
| 345 | − } suspend; | |
| 429 | + const struct atmel_lcdc_dc_ops *ops; | |
| 346 | 430 | }; |
| 347 | 431 | |
| 348 | 432 | extern struct atmel_hlcdc_formats atmel_hlcdc_plane_rgb_formats; |
| @@ -282,8 +282,9 @@ atmel_hlcdc_plane_scaler_set_phicoeff(struct atmel_hlcdc_plane *plane, · 281 unmodified lines | ||
| 282 | 282 | coeff_tab[i]); |
| 283 | 283 | } |
| 284 | 284 | |
| 285 | −static void atmel_hlcdc_plane_setup_scaler(struct atmel_hlcdc_plane *plane, | |
| 286 | − struct atmel_hlcdc_plane_state *state) | |
| 285 | +static | |
| 286 | +void atmel_hlcdc_plane_setup_scaler(struct atmel_hlcdc_plane *plane, | |
| 287 | + struct atmel_hlcdc_plane_state *state) | |
| 287 | 288 | { |
| 288 | 289 | const struct atmel_hlcdc_layer_desc *desc = plane->layer.desc; |
| 289 | 290 | u32 xfactor, yfactor; |
| @@ -330,11 +331,61 @@ static void atmel_hlcdc_plane_setup_scaler(struct atmel_hlcdc_plane *plane, · 40 unmodified lines | ||
| 330 | 331 | yfactor)); |
| 331 | 332 | } |
| 332 | 333 | |
| 334 | +static | |
| 335 | +void atmel_xlcdc_plane_setup_scaler(struct atmel_hlcdc_plane *plane, | |
| 336 | + struct atmel_hlcdc_plane_state *state) | |
| 337 | +{ | |
| 338 | + const struct atmel_hlcdc_layer_desc *desc = plane->layer.desc; | |
| 339 | + u32 xfactor, yfactor; | |
| 340 | + | |
| 341 | + if (!desc->layout.scaler_config) | |
| 342 | + return; | |
| 343 | + | |
| 344 | + if (state->crtc_w == state->src_w && state->crtc_h == state->src_h) { | |
| 345 | + atmel_hlcdc_layer_write_cfg(&plane->layer, | |
| 346 | + desc->layout.scaler_config, 0); | |
| 347 | + return; | |
| 348 | + } | |
| 349 | + | |
| 350 | + /* xfactor = round[(2^20 * XMEMSIZE)/XSIZE)] */ | |
| 351 | + xfactor = (u32)(((1 << 20) * state->src_w) / state->crtc_w); | |
| 352 | + | |
| 353 | + /* yfactor = round[(2^20 * YMEMSIZE)/YSIZE)] */ | |
| 354 | + yfactor = (u32)(((1 << 20) * state->src_h) / state->crtc_h); | |
| 355 | + | |
| 356 | + atmel_hlcdc_layer_write_cfg(&plane->layer, desc->layout.scaler_config, | |
| 357 | + ATMEL_XLCDC_LAYER_VSCALER_LUMA_ENABLE | | |
| 358 | + ATMEL_XLCDC_LAYER_VSCALER_CHROMA_ENABLE | | |
| 359 | + ATMEL_XLCDC_LAYER_HSCALER_LUMA_ENABLE | | |
| 360 | + ATMEL_XLCDC_LAYER_HSCALER_CHROMA_ENABLE); | |
| 361 | + | |
| 362 | + atmel_hlcdc_layer_write_cfg(&plane->layer, desc->layout.scaler_config + 1, | |
| 363 | + yfactor); | |
| 364 | + atmel_hlcdc_layer_write_cfg(&plane->layer, desc->layout.scaler_config + 3, | |
| 365 | + xfactor); | |
| 366 | + | |
| 367 | + /* | |
| 368 | + * With YCbCr 4:2:2 and YCbYcr 4:2:0 window resampling, configuration | |
| 369 | + * register LCDC_HEOCFG25.VXSCFACT and LCDC_HEOCFG27.HXSCFACT is half | |
| 370 | + * the value of yfactor and xfactor. | |
| 371 | + */ | |
| 372 | + if (state->base.fb->format->format == DRM_FORMAT_YUV420) { | |
| 373 | + yfactor /= 2; | |
| 374 | + xfactor /= 2; | |
| 375 | + } | |
| 376 | + | |
| 377 | + atmel_hlcdc_layer_write_cfg(&plane->layer, desc->layout.scaler_config + 2, | |
| 378 | + yfactor); | |
| 379 | + atmel_hlcdc_layer_write_cfg(&plane->layer, desc->layout.scaler_config + 4, | |
| 380 | + xfactor); | |
| 381 | +} | |
| 382 | + | |
| 333 | 383 | static void |
| 334 | 384 | atmel_hlcdc_plane_update_pos_and_size(struct atmel_hlcdc_plane *plane, |
| 335 | 385 | struct atmel_hlcdc_plane_state *state) |
| 336 | 386 | { |
| 337 | 387 | const struct atmel_hlcdc_layer_desc *desc = plane->layer.desc; |
| 388 | + struct atmel_hlcdc_dc *dc = plane->base.dev->dev_private; | |
| 338 | 389 | |
| 339 | 390 | if (desc->layout.size) |
| 340 | 391 | atmel_hlcdc_layer_write_cfg(&plane->layer, desc->layout.size, |
| @@ -352,12 +403,12 @@ atmel_hlcdc_plane_update_pos_and_size(struct atmel_hlcdc_plane *plane, · 11 unmodified lines | ||
| 352 | 403 | ATMEL_HLCDC_LAYER_POS(state->crtc_x, |
| 353 | 404 | state->crtc_y)); |
| 354 | 405 | |
| 355 | − atmel_hlcdc_plane_setup_scaler(plane, state); | |
| 406 | + dc->desc->ops->plane_setup_scaler(plane, state); | |
| 356 | 407 | } |
| 357 | 408 | |
| 358 | −static void | |
| 359 | −atmel_hlcdc_plane_update_general_settings(struct atmel_hlcdc_plane *plane, | |
| 360 | − struct atmel_hlcdc_plane_state *state) | |
| 409 | +static | |
| 410 | +void atmel_hlcdc_plane_update_general_settings(struct atmel_hlcdc_plane *plane, | |
| 411 | + struct atmel_hlcdc_plane_state *state) | |
| 361 | 412 | { |
| 362 | 413 | unsigned int cfg = ATMEL_HLCDC_LAYER_DMA_BLEN_INCR16 | state->ahb_id; |
| 363 | 414 | const struct atmel_hlcdc_layer_desc *desc = plane->layer.desc; |
| @@ -393,6 +444,40 @@ atmel_hlcdc_plane_update_general_settings(struct atmel_hlcdc_plane *plane, · 29 unmodified lines | ||
| 393 | 444 | cfg); |
| 394 | 445 | } |
| 395 | 446 | |
| 447 | +static | |
| 448 | +void atmel_xlcdc_plane_update_general_settings(struct atmel_hlcdc_plane *plane, | |
| 449 | + struct atmel_hlcdc_plane_state *state) | |
| 450 | +{ | |
| 451 | + const struct atmel_hlcdc_layer_desc *desc = plane->layer.desc; | |
| 452 | + const struct drm_format_info *format = state->base.fb->format; | |
| 453 | + unsigned int cfg; | |
| 454 | + | |
| 455 | + atmel_hlcdc_layer_write_cfg(&plane->layer, ATMEL_XLCDC_LAYER_DMA_CFG, | |
| 456 | + ATMEL_HLCDC_LAYER_DMA_BLEN_INCR16 | state->ahb_id); | |
| 457 | + | |
| 458 | + cfg = ATMEL_XLCDC_LAYER_DMA | ATMEL_XLCDC_LAYER_REP; | |
| 459 | + | |
| 460 | + if (plane->base.type != DRM_PLANE_TYPE_PRIMARY) { | |
| 461 | + /* | |
| 462 | + * Alpha Blending bits specific to SAM9X7 SoC | |
| 463 | + */ | |
| 464 | + cfg |= ATMEL_XLCDC_LAYER_SFACTC_A0_MULT_AS | | |
| 465 | + ATMEL_XLCDC_LAYER_SFACTA_ONE | | |
| 466 | + ATMEL_XLCDC_LAYER_DFACTC_M_A0_MULT_AS | | |
| 467 | + ATMEL_XLCDC_LAYER_DFACTA_ONE; | |
| 468 | + if (format->has_alpha) | |
| 469 | + cfg |= ATMEL_XLCDC_LAYER_A0(0xff); | |
| 470 | + else | |
| 471 | + cfg |= ATMEL_XLCDC_LAYER_A0(state->base.alpha); | |
| 472 | + } | |
| 473 | + | |
| 474 | + if (state->disc_h && state->disc_w) | |
| 475 | + cfg |= ATMEL_XLCDC_LAYER_DISCEN; | |
| 476 | + | |
| 477 | + atmel_hlcdc_layer_write_cfg(&plane->layer, desc->layout.general_config, | |
| 478 | + cfg); | |
| 479 | +} | |
| 480 | + | |
| 396 | 481 | static void atmel_hlcdc_plane_update_format(struct atmel_hlcdc_plane *plane, |
| 397 | 482 | struct atmel_hlcdc_plane_state *state) |
| 398 | 483 | { |
| @@ -437,36 +522,55 @@ static void atmel_hlcdc_plane_update_clut(struct atmel_hlcdc_plane *plane, · 38 unmodified lines | ||
| 437 | 522 | } |
| 438 | 523 | } |
| 439 | 524 | |
| 525 | +static void atmel_hlcdc_update_buffers(struct atmel_hlcdc_plane *plane, | |
| 526 | + struct atmel_hlcdc_plane_state *state, | |
| 527 | + u32 sr, int i) | |
| 528 | +{ | |
| 529 | + atmel_hlcdc_layer_write_reg(&plane->layer, | |
| 530 | + ATMEL_HLCDC_LAYER_PLANE_HEAD(i), | |
| 531 | + state->dscrs[i]->self); | |
| 532 | + | |
| 533 | + if (sr & ATMEL_HLCDC_LAYER_EN) | |
| 534 | + return; | |
| 535 | + | |
| 536 | + atmel_hlcdc_layer_write_reg(&plane->layer, | |
| 537 | + ATMEL_HLCDC_LAYER_PLANE_ADDR(i), | |
| 538 | + state->dscrs[i]->addr); | |
| 539 | + atmel_hlcdc_layer_write_reg(&plane->layer, | |
| 540 | + ATMEL_HLCDC_LAYER_PLANE_CTRL(i), | |
| 541 | + state->dscrs[i]->ctrl); | |
| 542 | + atmel_hlcdc_layer_write_reg(&plane->layer, | |
| 543 | + ATMEL_HLCDC_LAYER_PLANE_NEXT(i), | |
| 544 | + state->dscrs[i]->self); | |
| 545 | +} | |
| 546 | + | |
| 547 | +static void atmel_xlcdc_update_buffers(struct atmel_hlcdc_plane *plane, | |
| 548 | + struct atmel_hlcdc_plane_state *state, | |
| 549 | + u32 sr, int i) | |
| 550 | +{ | |
| 551 | + atmel_hlcdc_layer_write_reg(&plane->layer, | |
| 552 | + ATMEL_XLCDC_LAYER_PLANE_ADDR(i), | |
| 553 | + state->dscrs[i]->addr); | |
| 554 | +} | |
| 555 | + | |
| 440 | 556 | static void atmel_hlcdc_plane_update_buffers(struct atmel_hlcdc_plane *plane, |
| 441 | − struct atmel_hlcdc_plane_state *state) | |
| 557 | + struct atmel_hlcdc_plane_state *state) | |
| 442 | 558 | { |
| 443 | 559 | const struct atmel_hlcdc_layer_desc *desc = plane->layer.desc; |
| 560 | + struct atmel_hlcdc_dc *dc = plane->base.dev->dev_private; | |
| 444 | 561 | struct drm_framebuffer *fb = state->base.fb; |
| 445 | 562 | u32 sr; |
| 446 | 563 | int i; |
| 447 | 564 | |
| 448 | − sr = atmel_hlcdc_layer_read_reg(&plane->layer, ATMEL_HLCDC_LAYER_CHSR); | |
| 565 | + if (!dc->desc->is_xlcdc) | |
| 566 | + sr = atmel_hlcdc_layer_read_reg(&plane->layer, ATMEL_HLCDC_LAYER_CHSR); | |
| 449 | 567 | |
| 450 | 568 | for (i = 0; i < state->nplanes; i++) { |
| 451 | 569 | struct drm_gem_dma_object *gem = drm_fb_dma_get_gem_obj(fb, i); |
| 452 | 570 | |
| 453 | 571 | state->dscrs[i]->addr = gem->dma_addr + state->offsets[i]; |
| 454 | 572 | |
| 455 | − atmel_hlcdc_layer_write_reg(&plane->layer, | |
| 456 | − ATMEL_HLCDC_LAYER_PLANE_HEAD(i), | |
| 457 | − state->dscrs[i]->self); | |
| 458 | − | |
| 459 | − if (!(sr & ATMEL_HLCDC_LAYER_EN)) { | |
| 460 | − atmel_hlcdc_layer_write_reg(&plane->layer, | |
| 461 | − ATMEL_HLCDC_LAYER_PLANE_ADDR(i), | |
| 462 | − state->dscrs[i]->addr); | |
| 463 | − atmel_hlcdc_layer_write_reg(&plane->layer, | |
| 464 | − ATMEL_HLCDC_LAYER_PLANE_CTRL(i), | |
| 465 | − state->dscrs[i]->ctrl); | |
| 466 | − atmel_hlcdc_layer_write_reg(&plane->layer, | |
| 467 | − ATMEL_HLCDC_LAYER_PLANE_NEXT(i), | |
| 468 | − state->dscrs[i]->self); | |
| 469 | − } | |
| 573 | + dc->desc->ops->lcdc_update_buffers(plane, state, sr, i); | |
| 470 | 574 | |
| 471 | 575 | if (desc->layout.xstride[i]) |
| 472 | 576 | atmel_hlcdc_layer_write_cfg(&plane->layer, |
| @@ -712,11 +816,8 @@ static int atmel_hlcdc_plane_atomic_check(struct drm_plane *p, · 239 unmodified lines | ||
| 712 | 816 | return 0; |
| 713 | 817 | } |
| 714 | 818 | |
| 715 | −static void atmel_hlcdc_plane_atomic_disable(struct drm_plane *p, | |
| 716 | − struct drm_atomic_state *state) | |
| 819 | +static void atmel_hlcdc_atomic_disable(struct atmel_hlcdc_plane *plane) | |
| 717 | 820 | { |
| 718 | − struct atmel_hlcdc_plane *plane = drm_plane_to_atmel_hlcdc_plane(p); | |
| 719 | − | |
| 720 | 821 | /* Disable interrupts */ |
| 721 | 822 | atmel_hlcdc_layer_write_reg(&plane->layer, ATMEL_HLCDC_LAYER_IDR, |
| 722 | 823 | 0xffffffff); |
| @@ -731,6 +832,70 @@ static void atmel_hlcdc_plane_atomic_disable(struct drm_plane *p, · 8 unmodified lines | ||
| 731 | 832 | atmel_hlcdc_layer_read_reg(&plane->layer, ATMEL_HLCDC_LAYER_ISR); |
| 732 | 833 | } |
| 733 | 834 | |
| 835 | +static void atmel_xlcdc_atomic_disable(struct atmel_hlcdc_plane *plane) | |
| 836 | +{ | |
| 837 | + /* Disable interrupts */ | |
| 838 | + atmel_hlcdc_layer_write_reg(&plane->layer, ATMEL_XLCDC_LAYER_IDR, | |
| 839 | + 0xffffffff); | |
| 840 | + | |
| 841 | + /* Disable the layer */ | |
| 842 | + atmel_hlcdc_layer_write_reg(&plane->layer, | |
| 843 | + ATMEL_XLCDC_LAYER_ENR, 0); | |
| 844 | + | |
| 845 | + /* Clear all pending interrupts */ | |
| 846 | + atmel_hlcdc_layer_read_reg(&plane->layer, ATMEL_XLCDC_LAYER_ISR); | |
| 847 | +} | |
| 848 | + | |
| 849 | +static void atmel_hlcdc_plane_atomic_disable(struct drm_plane *p, | |
| 850 | + struct drm_atomic_state *state) | |
| 851 | +{ | |
| 852 | + struct atmel_hlcdc_plane *plane = drm_plane_to_atmel_hlcdc_plane(p); | |
| 853 | + struct atmel_hlcdc_dc *dc = plane->base.dev->dev_private; | |
| 854 | + | |
| 855 | + dc->desc->ops->lcdc_atomic_disable(plane); | |
| 856 | +} | |
| 857 | + | |
| 858 | +static void atmel_hlcdc_atomic_update(struct atmel_hlcdc_plane *plane, | |
| 859 | + struct atmel_hlcdc_dc *dc) | |
| 860 | +{ | |
| 861 | + u32 sr; | |
| 862 | + | |
| 863 | + /* Enable the overrun interrupts. */ | |
| 864 | + atmel_hlcdc_layer_write_reg(&plane->layer, ATMEL_HLCDC_LAYER_IER, | |
| 865 | + ATMEL_HLCDC_LAYER_OVR_IRQ(0) | | |
| 866 | + ATMEL_HLCDC_LAYER_OVR_IRQ(1) | | |
| 867 | + ATMEL_HLCDC_LAYER_OVR_IRQ(2)); | |
| 868 | + | |
| 869 | + /* Apply the new config at the next SOF event. */ | |
| 870 | + sr = atmel_hlcdc_layer_read_reg(&plane->layer, ATMEL_HLCDC_LAYER_CHSR); | |
| 871 | + atmel_hlcdc_layer_write_reg(&plane->layer, ATMEL_HLCDC_LAYER_CHER, | |
| 872 | + ATMEL_HLCDC_LAYER_UPDATE | | |
| 873 | + (sr & ATMEL_HLCDC_LAYER_EN ? | |
| 874 | + ATMEL_HLCDC_LAYER_A2Q : ATMEL_HLCDC_LAYER_EN)); | |
| 875 | +} | |
| 876 | + | |
| 877 | +static void atmel_xlcdc_atomic_update(struct atmel_hlcdc_plane *plane, | |
| 878 | + struct atmel_hlcdc_dc *dc) | |
| 879 | +{ | |
| 880 | + /* Enable the overrun interrupts. */ | |
| 881 | + atmel_hlcdc_layer_write_reg(&plane->layer, ATMEL_XLCDC_LAYER_IER, | |
| 882 | + ATMEL_XLCDC_LAYER_OVR_IRQ(0) | | |
| 883 | + ATMEL_XLCDC_LAYER_OVR_IRQ(1) | | |
| 884 | + ATMEL_XLCDC_LAYER_OVR_IRQ(2)); | |
| 885 | + | |
| 886 | + atmel_hlcdc_layer_write_reg(&plane->layer, ATMEL_XLCDC_LAYER_ENR, | |
| 887 | + ATMEL_XLCDC_LAYER_EN); | |
| 888 | + | |
| 889 | + /* | |
| 890 | + * Updating XLCDC_xxxCFGx, XLCDC_xxxFBA and XLCDC_xxxEN, | |
| 891 | + * (where xxx indicates each layer) requires writing one to the | |
| 892 | + * Update Attribute field for each layer in LCDC_ATTRE register for SAM9X7. | |
| 893 | + */ | |
| 894 | + regmap_write(dc->hlcdc->regmap, ATMEL_XLCDC_ATTRE, ATMEL_XLCDC_BASE_UPDATE | | |
| 895 | + ATMEL_XLCDC_OVR1_UPDATE | ATMEL_XLCDC_OVR3_UPDATE | | |
| 896 | + ATMEL_XLCDC_HEO_UPDATE); | |
| 897 | +} | |
| 898 | + | |
| 734 | 899 | static void atmel_hlcdc_plane_atomic_update(struct drm_plane *p, |
| 735 | 900 | struct drm_atomic_state *state) |
| 736 | 901 | { |
| @@ -739,7 +904,7 @@ static void atmel_hlcdc_plane_atomic_update(struct drm_plane *p, · 2 unmodified lines | ||
| 739 | 904 | struct atmel_hlcdc_plane *plane = drm_plane_to_atmel_hlcdc_plane(p); |
| 740 | 905 | struct atmel_hlcdc_plane_state *hstate = |
| 741 | 906 | drm_plane_state_to_atmel_hlcdc_plane_state(new_s); |
| 742 | − u32 sr; | |
| 907 | + struct atmel_hlcdc_dc *dc = p->dev->dev_private; | |
| 743 | 908 | |
| 744 | 909 | if (!new_s->crtc || !new_s->fb) |
| 745 | 910 | return; |
| @@ -750,29 +915,83 @@ static void atmel_hlcdc_plane_atomic_update(struct drm_plane *p, · 4 unmodified lines | ||
| 750 | 915 | } |
| 751 | 916 | |
| 752 | 917 | atmel_hlcdc_plane_update_pos_and_size(plane, hstate); |
| 753 | − atmel_hlcdc_plane_update_general_settings(plane, hstate); | |
| 918 | + dc->desc->ops->lcdc_update_general_settings(plane, hstate); | |
| 754 | 919 | atmel_hlcdc_plane_update_format(plane, hstate); |
| 755 | 920 | atmel_hlcdc_plane_update_clut(plane, hstate); |
| 756 | 921 | atmel_hlcdc_plane_update_buffers(plane, hstate); |
| 757 | 922 | atmel_hlcdc_plane_update_disc_area(plane, hstate); |
| 758 | 923 | |
| 759 | − /* Enable the overrun interrupts. */ | |
| 760 | − atmel_hlcdc_layer_write_reg(&plane->layer, ATMEL_HLCDC_LAYER_IER, | |
| 761 | − ATMEL_HLCDC_LAYER_OVR_IRQ(0) | | |
| 762 | − ATMEL_HLCDC_LAYER_OVR_IRQ(1) | | |
| 763 | − ATMEL_HLCDC_LAYER_OVR_IRQ(2)); | |
| 924 | + dc->desc->ops->lcdc_atomic_update(plane, dc); | |
| 925 | +} | |
| 764 | 926 | |
| 765 | − /* Apply the new config at the next SOF event. */ | |
| 766 | − sr = atmel_hlcdc_layer_read_reg(&plane->layer, ATMEL_HLCDC_LAYER_CHSR); | |
| 767 | − atmel_hlcdc_layer_write_reg(&plane->layer, ATMEL_HLCDC_LAYER_CHER, | |
| 768 | − ATMEL_HLCDC_LAYER_UPDATE | | |
| 769 | − (sr & ATMEL_HLCDC_LAYER_EN ? | |
| 770 | − ATMEL_HLCDC_LAYER_A2Q : ATMEL_HLCDC_LAYER_EN)); | |
| 927 | +static void atmel_hlcdc_csc_init(struct atmel_hlcdc_plane *plane, | |
| 928 | + const struct atmel_hlcdc_layer_desc *desc) | |
| 929 | +{ | |
| 930 | + /* | |
| 931 | + * TODO: declare a "yuv-to-rgb-conv-factors" property to let | |
| 932 | + * userspace modify these factors (using a BLOB property ?). | |
| 933 | + */ | |
| 934 | + static const u32 hlcdc_csc_coeffs[] = { | |
| 935 | + 0x4c900091, | |
| 936 | + 0x7a5f5090, | |
| 937 | + 0x40040890 | |
| 938 | + }; | |
| 939 | + | |
| 940 | + for (int i = 0; i < ARRAY_SIZE(hlcdc_csc_coeffs); i++) { | |
| 941 | + atmel_hlcdc_layer_write_cfg(&plane->layer, | |
| 942 | + desc->layout.csc + i, | |
| 943 | + hlcdc_csc_coeffs[i]); | |
| 944 | + } | |
| 945 | +} | |
| 946 | + | |
| 947 | +static void atmel_xlcdc_csc_init(struct atmel_hlcdc_plane *plane, | |
| 948 | + const struct atmel_hlcdc_layer_desc *desc) | |
| 949 | +{ | |
| 950 | + /* | |
| 951 | + * yuv-to-rgb-conv-factors are now defined from LCDC_HEOCFG16 to | |
| 952 | + * LCDC_HEOCFG21 registers in SAM9X7. | |
| 953 | + */ | |
| 954 | + static const u32 xlcdc_csc_coeffs[] = { | |
| 955 | + 0x00000488, | |
| 956 | + 0x00000648, | |
| 957 | + 0x1EA00480, | |
| 958 | + 0x00001D28, | |
| 959 | + 0x08100480, | |
| 960 | + 0x00000000, | |
| 961 | + 0x00000007 | |
| 962 | + }; | |
| 963 | + | |
| 964 | + for (int i = 0; i < ARRAY_SIZE(xlcdc_csc_coeffs); i++) { | |
| 965 | + atmel_hlcdc_layer_write_cfg(&plane->layer, | |
| 966 | + desc->layout.csc + i, | |
| 967 | + xlcdc_csc_coeffs[i]); | |
| 968 | + } | |
| 969 | + | |
| 970 | + if (desc->layout.vxs_config && desc->layout.hxs_config) { | |
| 971 | + /* | |
| 972 | + * Updating vxs.config and hxs.config fixes the | |
| 973 | + * Green Color Issue in SAM9X7 EGT Video Player App | |
| 974 | + */ | |
| 975 | + atmel_hlcdc_layer_write_cfg(&plane->layer, | |
| 976 | + desc->layout.vxs_config, | |
| 977 | + ATMEL_XLCDC_LAYER_VXSYCFG_ONE | | |
| 978 | + ATMEL_XLCDC_LAYER_VXSYTAP2_ENABLE | | |
| 979 | + ATMEL_XLCDC_LAYER_VXSCCFG_ONE | | |
| 980 | + ATMEL_XLCDC_LAYER_VXSCTAP2_ENABLE); | |
| 981 | + | |
| 982 | + atmel_hlcdc_layer_write_cfg(&plane->layer, | |
| 983 | + desc->layout.hxs_config, | |
| 984 | + ATMEL_XLCDC_LAYER_HXSYCFG_ONE | | |
| 985 | + ATMEL_XLCDC_LAYER_HXSYTAP2_ENABLE | | |
| 986 | + ATMEL_XLCDC_LAYER_HXSCCFG_ONE | | |
| 987 | + ATMEL_XLCDC_LAYER_HXSCTAP2_ENABLE); | |
| 988 | + } | |
| 771 | 989 | } |
| 772 | 990 | |
| 773 | 991 | static int atmel_hlcdc_plane_init_properties(struct atmel_hlcdc_plane *plane) |
| 774 | 992 | { |
| 775 | 993 | const struct atmel_hlcdc_layer_desc *desc = plane->layer.desc; |
| 994 | + struct atmel_hlcdc_dc *dc = plane->base.dev->dev_private; | |
| 776 | 995 | |
| 777 | 996 | if (desc->type == ATMEL_HLCDC_OVERLAY_LAYER || |
| 778 | 997 | desc->type == ATMEL_HLCDC_CURSOR_LAYER) { |
| @@ -796,31 +1015,16 @@ static int atmel_hlcdc_plane_init_properties(struct atmel_hlcdc_plane *plane) · 17 unmodified lines | ||
| 796 | 1015 | return ret; |
| 797 | 1016 | } |
| 798 | 1017 | |
| 799 | − if (desc->layout.csc) { | |
| 800 | − /* | |
| 801 | − * TODO: decare a "yuv-to-rgb-conv-factors" property to let | |
| 802 | − * userspace modify these factors (using a BLOB property ?). | |
| 803 | − */ | |
| 804 | − atmel_hlcdc_layer_write_cfg(&plane->layer, | |
| 805 | − desc->layout.csc, | |
| 806 | − 0x4c900091); | |
| 807 | − atmel_hlcdc_layer_write_cfg(&plane->layer, | |
| 808 | − desc->layout.csc + 1, | |
| 809 | − 0x7a5f5090); | |
| 810 | − atmel_hlcdc_layer_write_cfg(&plane->layer, | |
| 811 | − desc->layout.csc + 2, | |
| 812 | − 0x40040890); | |
| 813 | − } | |
| 1018 | + if (desc->layout.csc) | |
| 1019 | + dc->desc->ops->lcdc_csc_init(plane, desc); | |
| 814 | 1020 | |
| 815 | 1021 | return 0; |
| 816 | 1022 | } |
| 817 | 1023 | |
| 818 | −void atmel_hlcdc_plane_irq(struct atmel_hlcdc_plane *plane) | |
| 1024 | +static void atmel_hlcdc_irq_dbg(struct atmel_hlcdc_plane *plane, | |
| 1025 | + const struct atmel_hlcdc_layer_desc *desc) | |
| 819 | 1026 | { |
| 820 | − const struct atmel_hlcdc_layer_desc *desc = plane->layer.desc; | |
| 821 | − u32 isr; | |
| 822 | − | |
| 823 | − isr = atmel_hlcdc_layer_read_reg(&plane->layer, ATMEL_HLCDC_LAYER_ISR); | |
| 1027 | + u32 isr = atmel_hlcdc_layer_read_reg(&plane->layer, ATMEL_HLCDC_LAYER_ISR); | |
| 824 | 1028 | |
| 825 | 1029 | /* |
| 826 | 1030 | * There's not much we can do in case of overrun except informing |
| @@ -834,6 +1038,51 @@ void atmel_hlcdc_plane_irq(struct atmel_hlcdc_plane *plane) · 7 unmodified lines | ||
| 834 | 1038 | desc->name); |
| 835 | 1039 | } |
| 836 | 1040 | |
| 1041 | +static void atmel_xlcdc_irq_dbg(struct atmel_hlcdc_plane *plane, | |
| 1042 | + const struct atmel_hlcdc_layer_desc *desc) | |
| 1043 | +{ | |
| 1044 | + u32 isr = atmel_hlcdc_layer_read_reg(&plane->layer, ATMEL_XLCDC_LAYER_ISR); | |
| 1045 | + | |
| 1046 | + /* | |
| 1047 | + * There's not much we can do in case of overrun except informing | |
| 1048 | + * the user. However, we are in interrupt context here, hence the | |
| 1049 | + * use of dev_dbg(). | |
| 1050 | + */ | |
| 1051 | + if (isr & | |
| 1052 | + (ATMEL_XLCDC_LAYER_OVR_IRQ(0) | ATMEL_XLCDC_LAYER_OVR_IRQ(1) | | |
| 1053 | + ATMEL_XLCDC_LAYER_OVR_IRQ(2))) | |
| 1054 | + dev_dbg(plane->base.dev->dev, "overrun on plane %s\n", | |
| 1055 | + desc->name); | |
| 1056 | +} | |
| 1057 | + | |
| 1058 | +void atmel_hlcdc_plane_irq(struct atmel_hlcdc_plane *plane) | |
| 1059 | +{ | |
| 1060 | + const struct atmel_hlcdc_layer_desc *desc = plane->layer.desc; | |
| 1061 | + struct atmel_hlcdc_dc *dc = plane->base.dev->dev_private; | |
| 1062 | + | |
| 1063 | + dc->desc->ops->lcdc_irq_dbg(plane, desc); | |
| 1064 | +} | |
| 1065 | + | |
| 1066 | +const struct atmel_lcdc_dc_ops atmel_hlcdc_ops = { | |
| 1067 | + .plane_setup_scaler = atmel_hlcdc_plane_setup_scaler, | |
| 1068 | + .lcdc_update_buffers = atmel_hlcdc_update_buffers, | |
| 1069 | + .lcdc_atomic_disable = atmel_hlcdc_atomic_disable, | |
| 1070 | + .lcdc_update_general_settings = atmel_hlcdc_plane_update_general_settings, | |
| 1071 | + .lcdc_atomic_update = atmel_hlcdc_atomic_update, | |
| 1072 | + .lcdc_csc_init = atmel_hlcdc_csc_init, | |
| 1073 | + .lcdc_irq_dbg = atmel_hlcdc_irq_dbg, | |
| 1074 | +}; | |
| 1075 | + | |
| 1076 | +const struct atmel_lcdc_dc_ops atmel_xlcdc_ops = { | |
| 1077 | + .plane_setup_scaler = atmel_xlcdc_plane_setup_scaler, | |
| 1078 | + .lcdc_update_buffers = atmel_xlcdc_update_buffers, | |
| 1079 | + .lcdc_atomic_disable = atmel_xlcdc_atomic_disable, | |
| 1080 | + .lcdc_update_general_settings = atmel_xlcdc_plane_update_general_settings, | |
| 1081 | + .lcdc_atomic_update = atmel_xlcdc_atomic_update, | |
| 1082 | + .lcdc_csc_init = atmel_xlcdc_csc_init, | |
| 1083 | + .lcdc_irq_dbg = atmel_xlcdc_irq_dbg, | |
| 1084 | +}; | |
| 1085 | + | |
| 837 | 1086 | static const struct drm_plane_helper_funcs atmel_hlcdc_layer_plane_helper_funcs = { |
| 838 | 1087 | .atomic_check = atmel_hlcdc_plane_atomic_check, |
| 839 | 1088 | .atomic_update = atmel_hlcdc_plane_atomic_update, |
| @@ -877,11 +877,6 @@ static int adv7511_connector_init(struct adv7511 *adv) · 876 unmodified lines | ||
| 877 | 877 | struct drm_bridge *bridge = &adv->bridge; |
| 878 | 878 | int ret; |
| 879 | 879 | |
| 880 | − if (!bridge->encoder) { | |
| 881 | − DRM_ERROR("Parent encoder object not found"); | |
| 882 | − return -ENODEV; | |
| 883 | − } | |
| 884 | − | |
| 885 | 880 | if (adv->i2c_main->irq) |
| 886 | 881 | adv->connector.polled = DRM_CONNECTOR_POLL_HPD; |
| 887 | 882 | else |
| @@ -47,7 +47,7 @@ struct anx6345 { · 46 unmodified lines | ||
| 47 | 47 | struct drm_dp_aux aux; |
| 48 | 48 | struct drm_bridge bridge; |
| 49 | 49 | struct i2c_client *client; |
| 50 | − struct edid *edid; | |
| 50 | + const struct drm_edid *drm_edid; | |
| 51 | 51 | struct drm_connector connector; |
| 52 | 52 | struct drm_panel *panel; |
| 53 | 53 | struct regulator *dvdd12; |
| @@ -458,7 +458,7 @@ static int anx6345_get_modes(struct drm_connector *connector) · 404 unmodified lines | ||
| 458 | 458 | |
| 459 | 459 | mutex_lock(&anx6345->lock); |
| 460 | 460 | |
| 461 | − if (!anx6345->edid) { | |
| 461 | + if (!anx6345->drm_edid) { | |
| 462 | 462 | if (!anx6345->powered) { |
| 463 | 463 | anx6345_poweron(anx6345); |
| 464 | 464 | power_off = true; |
| @@ -470,19 +470,18 @@ static int anx6345_get_modes(struct drm_connector *connector) · 5 unmodified lines | ||
| 470 | 470 | goto unlock; |
| 471 | 471 | } |
| 472 | 472 | |
| 473 | − anx6345->edid = drm_get_edid(connector, &anx6345->aux.ddc); | |
| 474 | − if (!anx6345->edid) | |
| 473 | + anx6345->drm_edid = drm_edid_read_ddc(connector, &anx6345->aux.ddc); | |
| 474 | + if (!anx6345->drm_edid) | |
| 475 | 475 | DRM_ERROR("Failed to read EDID from panel\n"); |
| 476 | 476 | |
| 477 | − err = drm_connector_update_edid_property(connector, | |
| 478 | − anx6345->edid); | |
| 477 | + err = drm_edid_connector_update(connector, anx6345->drm_edid); | |
| 479 | 478 | if (err) { |
| 480 | 479 | DRM_ERROR("Failed to update EDID property: %d\n", err); |
| 481 | 480 | goto unlock; |
| 482 | 481 | } |
| 483 | 482 | } |
| 484 | 483 | |
| 485 | − num_modes += drm_add_edid_modes(connector, anx6345->edid); | |
| 484 | + num_modes += drm_edid_connector_add_modes(connector); | |
| 486 | 485 | |
| 487 | 486 | /* Driver currently supports only 6bpc */ |
| 488 | 487 | connector->display_info.bpc = 6; |
| @@ -528,11 +527,6 @@ static int anx6345_bridge_attach(struct drm_bridge *bridge, · 39 unmodified lines | ||
| 528 | 527 | return -EINVAL; |
| 529 | 528 | } |
| 530 | 529 | |
| 531 | − if (!bridge->encoder) { | |
| 532 | − DRM_ERROR("Parent encoder object not found"); | |
| 533 | − return -ENODEV; | |
| 534 | − } | |
| 535 | − | |
| 536 | 530 | /* Register aux channel */ |
| 537 | 531 | anx6345->aux.name = "DP-AUX"; |
| 538 | 532 | anx6345->aux.dev = &anx6345->client->dev; |
| @@ -793,7 +787,7 @@ static void anx6345_i2c_remove(struct i2c_client *client) · 254 unmodified lines | ||
| 793 | 787 | |
| 794 | 788 | unregister_i2c_dummy_clients(anx6345); |
| 795 | 789 | |
| 796 | − kfree(anx6345->edid); | |
| 790 | + drm_edid_free(anx6345->drm_edid); | |
| 797 | 791 | |
| 798 | 792 | mutex_destroy(&anx6345->lock); |
| 799 | 793 | } |
| @@ -67,7 +67,7 @@ struct anx78xx { · 66 unmodified lines | ||
| 67 | 67 | struct drm_dp_aux aux; |
| 68 | 68 | struct drm_bridge bridge; |
| 69 | 69 | struct i2c_client *client; |
| 70 | − struct edid *edid; | |
| 70 | + const struct drm_edid *drm_edid; | |
| 71 | 71 | struct drm_connector connector; |
| 72 | 72 | struct anx78xx_platform_data pdata; |
| 73 | 73 | struct mutex lock; |
| @@ -830,8 +830,8 @@ static int anx78xx_get_modes(struct drm_connector *connector) · 756 unmodified lines | ||
| 830 | 830 | if (WARN_ON(!anx78xx->powered)) |
| 831 | 831 | return 0; |
| 832 | 832 | |
| 833 | − if (anx78xx->edid) | |
| 834 | − return drm_add_edid_modes(connector, anx78xx->edid); | |
| 833 | + if (anx78xx->drm_edid) | |
| 834 | + return drm_edid_connector_add_modes(connector); | |
| 835 | 835 | |
| 836 | 836 | mutex_lock(&anx78xx->lock); |
| 837 | 837 | |
| @@ -841,20 +841,21 @@ static int anx78xx_get_modes(struct drm_connector *connector) · 3 unmodified lines | ||
| 841 | 841 | goto unlock; |
| 842 | 842 | } |
| 843 | 843 | |
| 844 | − anx78xx->edid = drm_get_edid(connector, &anx78xx->aux.ddc); | |
| 845 | − if (!anx78xx->edid) { | |
| 844 | + anx78xx->drm_edid = drm_edid_read_ddc(connector, &anx78xx->aux.ddc); | |
| 845 | + | |
| 846 | + err = drm_edid_connector_update(connector, anx78xx->drm_edid); | |
| 847 | + | |
| 848 | + if (!anx78xx->drm_edid) { | |
| 846 | 849 | DRM_ERROR("Failed to read EDID\n"); |
| 847 | 850 | goto unlock; |
| 848 | 851 | } |
| 849 | 852 | |
| 850 | − err = drm_connector_update_edid_property(connector, | |
| 851 | − anx78xx->edid); | |
| 852 | 853 | if (err) { |
| 853 | 854 | DRM_ERROR("Failed to update EDID property: %d\n", err); |
| 854 | 855 | goto unlock; |
| 855 | 856 | } |
| 856 | 857 | |
| 857 | − num_modes = drm_add_edid_modes(connector, anx78xx->edid); | |
| 858 | + num_modes = drm_edid_connector_add_modes(connector); | |
| 858 | 859 | |
| 859 | 860 | unlock: |
| 860 | 861 | mutex_unlock(&anx78xx->lock); |
| @@ -897,11 +898,6 @@ static int anx78xx_bridge_attach(struct drm_bridge *bridge, · 36 unmodified lines | ||
| 897 | 898 | return -EINVAL; |
| 898 | 899 | } |
| 899 | 900 | |
| 900 | − if (!bridge->encoder) { | |
| 901 | − DRM_ERROR("Parent encoder object not found"); | |
| 902 | − return -ENODEV; | |
| 903 | − } | |
| 904 | − | |
| 905 | 901 | /* Register aux channel */ |
| 906 | 902 | anx78xx->aux.name = "DP-AUX"; |
| 907 | 903 | anx78xx->aux.dev = &anx78xx->client->dev; |
| @@ -1091,8 +1087,8 @@ static bool anx78xx_handle_common_int_4(struct anx78xx *anx78xx, u8 irq) · 183 unmodified lines | ||
| 1091 | 1087 | event = true; |
| 1092 | 1088 | anx78xx_poweroff(anx78xx); |
| 1093 | 1089 | /* Free cached EDID */ |
| 1094 | − kfree(anx78xx->edid); | |
| 1095 | − anx78xx->edid = NULL; | |
| 1090 | + drm_edid_free(anx78xx->drm_edid); | |
| 1091 | + anx78xx->drm_edid = NULL; | |
| 1096 | 1092 | } else if (irq & SP_HPD_PLUG) { |
| 1097 | 1093 | DRM_DEBUG_KMS("IRQ: Hot plug detect - cable plug\n"); |
| 1098 | 1094 | event = true; |
| @@ -1363,7 +1359,7 @@ static void anx78xx_i2c_remove(struct i2c_client *client) · 264 unmodified lines | ||
| 1363 | 1359 | |
| 1364 | 1360 | unregister_i2c_dummy_clients(anx78xx); |
| 1365 | 1361 | |
| 1366 | − kfree(anx78xx->edid); | |
| 1362 | + drm_edid_free(anx78xx->drm_edid); | |
| 1367 | 1363 | } |
| 1368 | 1364 | |
| 1369 | 1365 | static const struct of_device_id anx78xx_match_table[] = { |
| @@ -234,28 +234,6 @@ static int analogix_dp_training_pattern_dis(struct analogix_dp_device *dp) · 233 unmodified lines | ||
| 234 | 234 | return ret < 0 ? ret : 0; |
| 235 | 235 | } |
| 236 | 236 | |
| 237 | −static void | |
| 238 | −analogix_dp_set_lane_lane_pre_emphasis(struct analogix_dp_device *dp, | |
| 239 | − int pre_emphasis, int lane) | |
| 240 | −{ | |
| 241 | − switch (lane) { | |
| 242 | − case 0: | |
| 243 | − analogix_dp_set_lane0_pre_emphasis(dp, pre_emphasis); | |
| 244 | − break; | |
| 245 | − case 1: | |
| 246 | − analogix_dp_set_lane1_pre_emphasis(dp, pre_emphasis); | |
| 247 | − break; | |
| 248 | − | |
| 249 | − case 2: | |
| 250 | − analogix_dp_set_lane2_pre_emphasis(dp, pre_emphasis); | |
| 251 | − break; | |
| 252 | − | |
| 253 | − case 3: | |
| 254 | − analogix_dp_set_lane3_pre_emphasis(dp, pre_emphasis); | |
| 255 | − break; | |
| 256 | − } | |
| 257 | −} | |
| 258 | − | |
| 259 | 237 | static int analogix_dp_link_start(struct analogix_dp_device *dp) |
| 260 | 238 | { |
| 261 | 239 | u8 buf[4]; |
| @@ -286,10 +264,12 @@ static int analogix_dp_link_start(struct analogix_dp_device *dp) · 24 unmodified lines | ||
| 286 | 264 | return retval; |
| 287 | 265 | } |
| 288 | 266 | |
| 289 | − /* Set TX pre-emphasis to minimum */ | |
| 267 | + /* Set TX voltage-swing and pre-emphasis to minimum */ | |
| 290 | 268 | for (lane = 0; lane < lane_count; lane++) |
| 291 | − analogix_dp_set_lane_lane_pre_emphasis(dp, | |
| 292 | − PRE_EMPHASIS_LEVEL_0, lane); | |
| 269 | + dp->link_train.training_lane[lane] = | |
| 270 | + DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | | |
| 271 | + DP_TRAIN_PRE_EMPH_LEVEL_0; | |
| 272 | + analogix_dp_set_lane_link_training(dp); | |
| 293 | 273 | |
| 294 | 274 | /* Wait for PLL lock */ |
| 295 | 275 | pll_tries = 0; |
| @@ -384,54 +364,6 @@ static unsigned char analogix_dp_get_adjust_request_pre_emphasis( · 88 unmodified lines | ||
| 384 | 364 | return ((link_value >> shift) & 0xc) >> 2; |
| 385 | 365 | } |
| 386 | 366 | |
| 387 | −static void analogix_dp_set_lane_link_training(struct analogix_dp_device *dp, | |
| 388 | − u8 training_lane_set, int lane) | |
| 389 | −{ | |
| 390 | − switch (lane) { | |
| 391 | − case 0: | |
| 392 | − analogix_dp_set_lane0_link_training(dp, training_lane_set); | |
| 393 | − break; | |
| 394 | − case 1: | |
| 395 | − analogix_dp_set_lane1_link_training(dp, training_lane_set); | |
| 396 | − break; | |
| 397 | − | |
| 398 | − case 2: | |
| 399 | − analogix_dp_set_lane2_link_training(dp, training_lane_set); | |
| 400 | − break; | |
| 401 | − | |
| 402 | − case 3: | |
| 403 | − analogix_dp_set_lane3_link_training(dp, training_lane_set); | |
| 404 | − break; | |
| 405 | − } | |
| 406 | −} | |
| 407 | − | |
| 408 | −static unsigned int | |
| 409 | −analogix_dp_get_lane_link_training(struct analogix_dp_device *dp, | |
| 410 | − int lane) | |
| 411 | −{ | |
| 412 | − u32 reg; | |
| 413 | − | |
| 414 | − switch (lane) { | |
| 415 | − case 0: | |
| 416 | − reg = analogix_dp_get_lane0_link_training(dp); | |
| 417 | − break; | |
| 418 | − case 1: | |
| 419 | − reg = analogix_dp_get_lane1_link_training(dp); | |
| 420 | − break; | |
| 421 | − case 2: | |
| 422 | − reg = analogix_dp_get_lane2_link_training(dp); | |
| 423 | − break; | |
| 424 | − case 3: | |
| 425 | − reg = analogix_dp_get_lane3_link_training(dp); | |
| 426 | − break; | |
| 427 | − default: | |
| 428 | − WARN_ON(1); | |
| 429 | − return 0; | |
| 430 | − } | |
| 431 | − | |
| 432 | − return reg; | |
| 433 | −} | |
| 434 | − | |
| 435 | 367 | static void analogix_dp_reduce_link_rate(struct analogix_dp_device *dp) |
| 436 | 368 | { |
| 437 | 369 | analogix_dp_training_pattern_dis(dp); |
| @@ -478,11 +410,6 @@ static int analogix_dp_process_clock_recovery(struct analogix_dp_device *dp) · 40 unmodified lines | ||
| 478 | 410 | if (retval < 0) |
| 479 | 411 | return retval; |
| 480 | 412 | |
| 481 | − retval = drm_dp_dpcd_read(&dp->aux, DP_ADJUST_REQUEST_LANE0_1, | |
| 482 | − adjust_request, 2); | |
| 483 | − if (retval < 0) | |
| 484 | − return retval; | |
| 485 | − | |
| 486 | 413 | if (analogix_dp_clock_recovery_ok(link_status, lane_count) == 0) { |
| 487 | 414 | /* set training pattern 2 for EQ */ |
| 488 | 415 | analogix_dp_set_training_pattern(dp, TRAINING_PTN2); |
| @@ -495,38 +422,37 @@ static int analogix_dp_process_clock_recovery(struct analogix_dp_device *dp) · 6 unmodified lines | ||
| 495 | 422 | |
| 496 | 423 | dev_dbg(dp->dev, "Link Training Clock Recovery success\n"); |
| 497 | 424 | dp->link_train.lt_state = EQUALIZER_TRAINING; |
| 498 | − } else { | |
| 499 | − for (lane = 0; lane < lane_count; lane++) { | |
| 500 | − training_lane = analogix_dp_get_lane_link_training( | |
| 501 | − dp, lane); | |
| 502 | − voltage_swing = analogix_dp_get_adjust_request_voltage( | |
| 503 | − adjust_request, lane); | |
| 504 | − pre_emphasis = analogix_dp_get_adjust_request_pre_emphasis( | |
| 505 | − adjust_request, lane); | |
| 506 | − | |
| 507 | − if (DPCD_VOLTAGE_SWING_GET(training_lane) == | |
| 508 | − voltage_swing && | |
| 509 | − DPCD_PRE_EMPHASIS_GET(training_lane) == | |
| 510 | − pre_emphasis) | |
| 511 | − dp->link_train.cr_loop[lane]++; | |
| 512 | − | |
| 513 | − if (dp->link_train.cr_loop[lane] == MAX_CR_LOOP || | |
| 514 | − voltage_swing == VOLTAGE_LEVEL_3 || | |
| 515 | − pre_emphasis == PRE_EMPHASIS_LEVEL_3) { | |
| 516 | − dev_err(dp->dev, "CR Max reached (%d,%d,%d)\n", | |
| 517 | − dp->link_train.cr_loop[lane], | |
| 518 | − voltage_swing, pre_emphasis); | |
| 519 | − analogix_dp_reduce_link_rate(dp); | |
| 520 | − return -EIO; | |
| 521 | − } | |
| 425 | + | |
| 426 | + return 0; | |
| 427 | + } | |
| 428 | + | |
| 429 | + retval = drm_dp_dpcd_read(&dp->aux, DP_ADJUST_REQUEST_LANE0_1, | |
| 430 | + adjust_request, 2); | |
| 431 | + if (retval < 0) | |
| 432 | + return retval; | |
| 433 | + | |
| 434 | + for (lane = 0; lane < lane_count; lane++) { | |
| 435 | + training_lane = analogix_dp_get_lane_link_training(dp, lane); | |
| 436 | + voltage_swing = analogix_dp_get_adjust_request_voltage(adjust_request, lane); | |
| 437 | + pre_emphasis = analogix_dp_get_adjust_request_pre_emphasis(adjust_request, lane); | |
| 438 | + | |
| 439 | + if (DPCD_VOLTAGE_SWING_GET(training_lane) == voltage_swing && | |
| 440 | + DPCD_PRE_EMPHASIS_GET(training_lane) == pre_emphasis) | |
| 441 | + dp->link_train.cr_loop[lane]++; | |
| 442 | + | |
| 443 | + if (dp->link_train.cr_loop[lane] == MAX_CR_LOOP || | |
| 444 | + voltage_swing == VOLTAGE_LEVEL_3 || | |
| 445 | + pre_emphasis == PRE_EMPHASIS_LEVEL_3) { | |
| 446 | + dev_err(dp->dev, "CR Max reached (%d,%d,%d)\n", | |
| 447 | + dp->link_train.cr_loop[lane], | |
| 448 | + voltage_swing, pre_emphasis); | |
| 449 | + analogix_dp_reduce_link_rate(dp); | |
| 450 | + return -EIO; | |
| 522 | 451 | } |
| 523 | 452 | } |
| 524 | 453 | |
| 525 | 454 | analogix_dp_get_adjust_training_lane(dp, adjust_request); |
| 526 | − | |
| 527 | − for (lane = 0; lane < lane_count; lane++) | |
| 528 | − analogix_dp_set_lane_link_training(dp, | |
| 529 | − dp->link_train.training_lane[lane], lane); | |
| 455 | + analogix_dp_set_lane_link_training(dp); | |
| 530 | 456 | |
| 531 | 457 | retval = drm_dp_dpcd_write(&dp->aux, DP_TRAINING_LANE0_SET, |
| 532 | 458 | dp->link_train.training_lane, lane_count); |
| @@ -538,7 +464,7 @@ static int analogix_dp_process_clock_recovery(struct analogix_dp_device *dp) · 5 unmodified lines | ||
| 538 | 464 | |
| 539 | 465 | static int analogix_dp_process_equalizer_training(struct analogix_dp_device *dp) |
| 540 | 466 | { |
| 541 | − int lane, lane_count, retval; | |
| 467 | + int lane_count, retval; | |
| 542 | 468 | u32 reg; |
| 543 | 469 | u8 link_align, link_status[2], adjust_request[2]; |
| 544 | 470 | |
| @@ -598,9 +524,7 @@ static int analogix_dp_process_equalizer_training(struct analogix_dp_device *dp) · 53 unmodified lines | ||
| 598 | 524 | return -EIO; |
| 599 | 525 | } |
| 600 | 526 | |
| 601 | − for (lane = 0; lane < lane_count; lane++) | |
| 602 | − analogix_dp_set_lane_link_training(dp, | |
| 603 | − dp->link_train.training_lane[lane], lane); | |
| 527 | + analogix_dp_set_lane_link_training(dp); | |
| 604 | 528 | |
| 605 | 529 | retval = drm_dp_dpcd_write(&dp->aux, DP_TRAINING_LANE0_SET, |
| 606 | 530 | dp->link_train.training_lane, lane_count); |
| @@ -712,7 +636,7 @@ static int analogix_dp_full_link_train(struct analogix_dp_device *dp, · 105 unmodified lines | ||
| 712 | 636 | |
| 713 | 637 | static int analogix_dp_fast_link_train(struct analogix_dp_device *dp) |
| 714 | 638 | { |
| 715 | − int i, ret; | |
| 639 | + int ret; | |
| 716 | 640 | u8 link_align, link_status[2]; |
| 717 | 641 | enum pll_status status; |
| 718 | 642 | |
| @@ -720,11 +644,7 @@ static int analogix_dp_fast_link_train(struct analogix_dp_device *dp) · 1 unmodified line | ||
| 720 | 644 | |
| 721 | 645 | analogix_dp_set_link_bandwidth(dp, dp->link_train.link_rate); |
| 722 | 646 | analogix_dp_set_lane_count(dp, dp->link_train.lane_count); |
| 723 | − | |
| 724 | − for (i = 0; i < dp->link_train.lane_count; i++) { | |
| 725 | − analogix_dp_set_lane_link_training(dp, | |
| 726 | − dp->link_train.training_lane[i], i); | |
| 727 | − } | |
| 647 | + analogix_dp_set_lane_link_training(dp); | |
| 728 | 648 | |
| 729 | 649 | ret = readx_poll_timeout(analogix_dp_get_pll_lock_status, dp, status, |
| 730 | 650 | status != PLL_UNLOCKED, 120, |
| @@ -1108,7 +1028,7 @@ out: · 377 unmodified lines | ||
| 1108 | 1028 | static int analogix_dp_get_modes(struct drm_connector *connector) |
| 1109 | 1029 | { |
| 1110 | 1030 | struct analogix_dp_device *dp = to_dp(connector); |
| 1111 | − struct edid *edid; | |
| 1031 | + const struct drm_edid *drm_edid; | |
| 1112 | 1032 | int ret, num_modes = 0; |
| 1113 | 1033 | |
| 1114 | 1034 | if (dp->plat_data->panel) { |
| @@ -1120,12 +1040,13 @@ static int analogix_dp_get_modes(struct drm_connector *connector) · 5 unmodified lines | ||
| 1120 | 1040 | return 0; |
| 1121 | 1041 | } |
| 1122 | 1042 | |
| 1123 | − edid = drm_get_edid(connector, &dp->aux.ddc); | |
| 1124 | − if (edid) { | |
| 1125 | − drm_connector_update_edid_property(&dp->connector, | |
| 1126 | − edid); | |
| 1127 | − num_modes += drm_add_edid_modes(&dp->connector, edid); | |
| 1128 | − kfree(edid); | |
| 1043 | + drm_edid = drm_edid_read_ddc(connector, &dp->aux.ddc); | |
| 1044 | + | |
| 1045 | + drm_edid_connector_update(&dp->connector, drm_edid); | |
| 1046 | + | |
| 1047 | + if (drm_edid) { | |
| 1048 | + num_modes += drm_edid_connector_add_modes(&dp->connector); | |
| 1049 | + drm_edid_free(drm_edid); | |
| 1129 | 1050 | } |
| 1130 | 1051 | |
| 1131 | 1052 | ret = analogix_dp_prepare_panel(dp, false, false); |
| @@ -1228,11 +1149,6 @@ static int analogix_dp_bridge_attach(struct drm_bridge *bridge, · 96 unmodified lines | ||
| 1228 | 1149 | return -EINVAL; |
| 1229 | 1150 | } |
| 1230 | 1151 | |
| 1231 | − if (!bridge->encoder) { | |
| 1232 | − DRM_ERROR("Parent encoder object not found"); | |
| 1233 | − return -ENODEV; | |
| 1234 | − } | |
| 1235 | − | |
| 1236 | 1152 | if (!dp->plat_data->skip_connector) { |
| 1237 | 1153 | connector = &dp->connector; |
| 1238 | 1154 | connector->polled = DRM_CONNECTOR_POLL_HPD; |
| @@ -213,26 +213,8 @@ void analogix_dp_enable_enhanced_mode(struct analogix_dp_device *dp, · 212 unmodified lines | ||
| 213 | 213 | bool enable); |
| 214 | 214 | void analogix_dp_set_training_pattern(struct analogix_dp_device *dp, |
| 215 | 215 | enum pattern_set pattern); |
| 216 | −void analogix_dp_set_lane0_pre_emphasis(struct analogix_dp_device *dp, | |
| 217 | − u32 level); | |
| 218 | −void analogix_dp_set_lane1_pre_emphasis(struct analogix_dp_device *dp, | |
| 219 | − u32 level); | |
| 220 | −void analogix_dp_set_lane2_pre_emphasis(struct analogix_dp_device *dp, | |
| 221 | − u32 level); | |
| 222 | −void analogix_dp_set_lane3_pre_emphasis(struct analogix_dp_device *dp, | |
| 223 | − u32 level); | |
| 224 | −void analogix_dp_set_lane0_link_training(struct analogix_dp_device *dp, | |
| 225 | − u32 training_lane); | |
| 226 | −void analogix_dp_set_lane1_link_training(struct analogix_dp_device *dp, | |
| 227 | − u32 training_lane); | |
| 228 | −void analogix_dp_set_lane2_link_training(struct analogix_dp_device *dp, | |
| 229 | − u32 training_lane); | |
| 230 | −void analogix_dp_set_lane3_link_training(struct analogix_dp_device *dp, | |
| 231 | − u32 training_lane); | |
| 232 | −u32 analogix_dp_get_lane0_link_training(struct analogix_dp_device *dp); | |
| 233 | −u32 analogix_dp_get_lane1_link_training(struct analogix_dp_device *dp); | |
| 234 | −u32 analogix_dp_get_lane2_link_training(struct analogix_dp_device *dp); | |
| 235 | −u32 analogix_dp_get_lane3_link_training(struct analogix_dp_device *dp); | |
| 216 | +void analogix_dp_set_lane_link_training(struct analogix_dp_device *dp); | |
| 217 | +u32 analogix_dp_get_lane_link_training(struct analogix_dp_device *dp, u8 lane); | |
| 236 | 218 | void analogix_dp_reset_macro(struct analogix_dp_device *dp); |
| 237 | 219 | void analogix_dp_init_video(struct analogix_dp_device *dp); |
| 238 | 220 | |
| @@ -557,6 +557,20 @@ void analogix_dp_get_lane_count(struct analogix_dp_device *dp, u32 *count) · 556 unmodified lines | ||
| 557 | 557 | *count = reg; |
| 558 | 558 | } |
| 559 | 559 | |
| 560 | +void analogix_dp_set_lane_link_training(struct analogix_dp_device *dp) | |
| 561 | +{ | |
| 562 | + u8 lane; | |
| 563 | + | |
| 564 | + for (lane = 0; lane < dp->link_train.lane_count; lane++) | |
| 565 | + writel(dp->link_train.training_lane[lane], | |
| 566 | + dp->reg_base + ANALOGIX_DP_LN0_LINK_TRAINING_CTL + 4 * lane); | |
| 567 | +} | |
| 568 | + | |
| 569 | +u32 analogix_dp_get_lane_link_training(struct analogix_dp_device *dp, u8 lane) | |
| 570 | +{ | |
| 571 | + return readl(dp->reg_base + ANALOGIX_DP_LN0_LINK_TRAINING_CTL + 4 * lane); | |
| 572 | +} | |
| 573 | + | |
| 560 | 574 | void analogix_dp_enable_enhanced_mode(struct analogix_dp_device *dp, |
| 561 | 575 | bool enable) |
| 562 | 576 | { |
| @@ -606,106 +620,6 @@ void analogix_dp_set_training_pattern(struct analogix_dp_device *dp, · 43 unmodified lines | ||
| 606 | 620 | } |
| 607 | 621 | } |
| 608 | 622 | |
| 609 | −void analogix_dp_set_lane0_pre_emphasis(struct analogix_dp_device *dp, | |
| 610 | − u32 level) | |
| 611 | −{ | |
| 612 | − u32 reg; | |
| 613 | − | |
| 614 | − reg = readl(dp->reg_base + ANALOGIX_DP_LN0_LINK_TRAINING_CTL); | |
| 615 | − reg &= ~PRE_EMPHASIS_SET_MASK; | |
| 616 | − reg |= level << PRE_EMPHASIS_SET_SHIFT; | |
| 617 | − writel(reg, dp->reg_base + ANALOGIX_DP_LN0_LINK_TRAINING_CTL); | |
| 618 | −} | |
| 619 | − | |
| 620 | −void analogix_dp_set_lane1_pre_emphasis(struct analogix_dp_device *dp, | |
| 621 | − u32 level) | |
| 622 | −{ | |
| 623 | − u32 reg; | |
| 624 | − | |
| 625 | − reg = readl(dp->reg_base + ANALOGIX_DP_LN1_LINK_TRAINING_CTL); | |
| 626 | − reg &= ~PRE_EMPHASIS_SET_MASK; | |
| 627 | − reg |= level << PRE_EMPHASIS_SET_SHIFT; | |
| 628 | − writel(reg, dp->reg_base + ANALOGIX_DP_LN1_LINK_TRAINING_CTL); | |
| 629 | −} | |
| 630 | − | |
| 631 | −void analogix_dp_set_lane2_pre_emphasis(struct analogix_dp_device *dp, | |
| 632 | − u32 level) | |
| 633 | −{ | |
| 634 | − u32 reg; | |
| 635 | − | |
| 636 | − reg = readl(dp->reg_base + ANALOGIX_DP_LN2_LINK_TRAINING_CTL); | |
| 637 | − reg &= ~PRE_EMPHASIS_SET_MASK; | |
| 638 | − reg |= level << PRE_EMPHASIS_SET_SHIFT; | |
| 639 | − writel(reg, dp->reg_base + ANALOGIX_DP_LN2_LINK_TRAINING_CTL); | |
| 640 | −} | |
| 641 | − | |
| 642 | −void analogix_dp_set_lane3_pre_emphasis(struct analogix_dp_device *dp, | |
| 643 | − u32 level) | |
| 644 | −{ | |
| 645 | − u32 reg; | |
| 646 | − | |
| 647 | − reg = readl(dp->reg_base + ANALOGIX_DP_LN3_LINK_TRAINING_CTL); | |
| 648 | − reg &= ~PRE_EMPHASIS_SET_MASK; | |
| 649 | − reg |= level << PRE_EMPHASIS_SET_SHIFT; | |
| 650 | − writel(reg, dp->reg_base + ANALOGIX_DP_LN3_LINK_TRAINING_CTL); | |
| 651 | −} | |
| 652 | − | |
| 653 | −void analogix_dp_set_lane0_link_training(struct analogix_dp_device *dp, | |
| 654 | − u32 training_lane) | |
| 655 | −{ | |
| 656 | − u32 reg; | |
| 657 | − | |
| 658 | − reg = training_lane; | |
| 659 | − writel(reg, dp->reg_base + ANALOGIX_DP_LN0_LINK_TRAINING_CTL); | |
| 660 | −} | |
| 661 | − | |
| 662 | −void analogix_dp_set_lane1_link_training(struct analogix_dp_device *dp, | |
| 663 | − u32 training_lane) | |
| 664 | −{ | |
| 665 | − u32 reg; | |
| 666 | − | |
| 667 | − reg = training_lane; | |
| 668 | − writel(reg, dp->reg_base + ANALOGIX_DP_LN1_LINK_TRAINING_CTL); | |
| 669 | −} | |
| 670 | − | |
| 671 | −void analogix_dp_set_lane2_link_training(struct analogix_dp_device *dp, | |
| 672 | − u32 training_lane) | |
| 673 | −{ | |
| 674 | − u32 reg; | |
| 675 | − | |
| 676 | − reg = training_lane; | |
| 677 | − writel(reg, dp->reg_base + ANALOGIX_DP_LN2_LINK_TRAINING_CTL); | |
| 678 | −} | |
| 679 | − | |
| 680 | −void analogix_dp_set_lane3_link_training(struct analogix_dp_device *dp, | |
| 681 | − u32 training_lane) | |
| 682 | −{ | |
| 683 | − u32 reg; | |
| 684 | − | |
| 685 | − reg = training_lane; | |
| 686 | − writel(reg, dp->reg_base + ANALOGIX_DP_LN3_LINK_TRAINING_CTL); | |
| 687 | −} | |
| 688 | − | |
| 689 | −u32 analogix_dp_get_lane0_link_training(struct analogix_dp_device *dp) | |
| 690 | −{ | |
| 691 | − return readl(dp->reg_base + ANALOGIX_DP_LN0_LINK_TRAINING_CTL); | |
| 692 | −} | |
| 693 | − | |
| 694 | −u32 analogix_dp_get_lane1_link_training(struct analogix_dp_device *dp) | |
| 695 | −{ | |
| 696 | − return readl(dp->reg_base + ANALOGIX_DP_LN1_LINK_TRAINING_CTL); | |
| 697 | −} | |
| 698 | − | |
| 699 | −u32 analogix_dp_get_lane2_link_training(struct analogix_dp_device *dp) | |
| 700 | −{ | |
| 701 | − return readl(dp->reg_base + ANALOGIX_DP_LN2_LINK_TRAINING_CTL); | |
| 702 | −} | |
| 703 | − | |
| 704 | −u32 analogix_dp_get_lane3_link_training(struct analogix_dp_device *dp) | |
| 705 | −{ | |
| 706 | − return readl(dp->reg_base + ANALOGIX_DP_LN3_LINK_TRAINING_CTL); | |
| 707 | −} | |
| 708 | − | |
| 709 | 623 | void analogix_dp_reset_macro(struct analogix_dp_device *dp) |
| 710 | 624 | { |
| 711 | 625 | u32 reg; |
| @@ -1027,7 +941,6 @@ ssize_t analogix_dp_transfer(struct analogix_dp_device *dp, · 315 unmodified lines | ||
| 1027 | 941 | u32 status_reg; |
| 1028 | 942 | u8 *buffer = msg->buffer; |
| 1029 | 943 | unsigned int i; |
| 1030 | − int num_transferred = 0; | |
| 1031 | 944 | int ret; |
| 1032 | 945 | |
| 1033 | 946 | /* Buffer size of AUX CH is 16 bytes */ |
| @@ -1079,7 +992,6 @@ ssize_t analogix_dp_transfer(struct analogix_dp_device *dp, · 45 unmodified lines | ||
| 1079 | 992 | reg = buffer[i]; |
| 1080 | 993 | writel(reg, dp->reg_base + ANALOGIX_DP_BUF_DATA_0 + |
| 1081 | 994 | 4 * i); |
| 1082 | − num_transferred++; | |
| 1083 | 995 | } |
| 1084 | 996 | } |
| 1085 | 997 | |
| @@ -1127,7 +1039,6 @@ ssize_t analogix_dp_transfer(struct analogix_dp_device *dp, · 41 unmodified lines | ||
| 1127 | 1039 | reg = readl(dp->reg_base + ANALOGIX_DP_BUF_DATA_0 + |
| 1128 | 1040 | 4 * i); |
| 1129 | 1041 | buffer[i] = (unsigned char)reg; |
| 1130 | − num_transferred++; | |
| 1131 | 1042 | } |
| 1132 | 1043 | } |
| 1133 | 1044 | |
| @@ -1144,7 +1055,7 @@ ssize_t analogix_dp_transfer(struct analogix_dp_device *dp, · 10 unmodified lines | ||
| 1144 | 1055 | (msg->request & ~DP_AUX_I2C_MOT) == DP_AUX_NATIVE_READ) |
| 1145 | 1056 | msg->reply = DP_AUX_NATIVE_REPLY_ACK; |
| 1146 | 1057 | |
| 1147 | − return num_transferred > 0 ? num_transferred : -EBUSY; | |
| 1058 | + return msg->size; | |
| 1148 | 1059 | |
| 1149 | 1060 | aux_error: |
| 1150 | 1061 | /* if aux err happen, reset aux */ |
| @@ -464,9 +464,11 @@ static int anx7625_odfc_config(struct anx7625_data *ctx, · 463 unmodified lines | ||
| 464 | 464 | */ |
| 465 | 465 | static int anx7625_set_k_value(struct anx7625_data *ctx) |
| 466 | 466 | { |
| 467 | − struct edid *edid = (struct edid *)ctx->slimport_edid_p.edid_raw_data; | |
| 467 | + struct drm_edid_product_id id; | |
| 468 | 468 | |
| 469 | − if (edid->mfg_id[0] == IVO_MID0 && edid->mfg_id[1] == IVO_MID1) | |
| 469 | + drm_edid_get_product_id(ctx->cached_drm_edid, &id); | |
| 470 | + | |
| 471 | + if (be16_to_cpu(id.manufacturer_name) == IVO_MID) | |
| 470 | 472 | return anx7625_reg_write(ctx, ctx->i2c.rx_p1_client, |
| 471 | 473 | MIPI_DIGITAL_ADJ_1, 0x3B); |
| 472 | 474 | |
| @@ -1526,7 +1528,8 @@ static int anx7625_wait_hpd_asserted(struct drm_dp_aux *aux, · 1053 unmodified lines | ||
| 1526 | 1528 | |
| 1527 | 1529 | static void anx7625_remove_edid(struct anx7625_data *ctx) |
| 1528 | 1530 | { |
| 1529 | − ctx->slimport_edid_p.edid_block_num = -1; | |
| 1531 | + drm_edid_free(ctx->cached_drm_edid); | |
| 1532 | + ctx->cached_drm_edid = NULL; | |
| 1530 | 1533 | } |
| 1531 | 1534 | |
| 1532 | 1535 | static void anx7625_dp_adjust_swing(struct anx7625_data *ctx) |
| @@ -1787,27 +1790,32 @@ static ssize_t anx7625_aux_transfer(struct drm_dp_aux *aux, · 254 unmodified lines | ||
| 1787 | 1790 | static const struct drm_edid *anx7625_edid_read(struct anx7625_data *ctx) |
| 1788 | 1791 | { |
| 1789 | 1792 | struct device *dev = ctx->dev; |
| 1790 | − struct s_edid_data *p_edid = &ctx->slimport_edid_p; | |
| 1793 | + u8 *edid_buf; | |
| 1791 | 1794 | int edid_num; |
| 1792 | 1795 | |
| 1793 | − if (ctx->slimport_edid_p.edid_block_num > 0) | |
| 1796 | + if (ctx->cached_drm_edid) | |
| 1794 | 1797 | goto out; |
| 1795 | 1798 | |
| 1799 | + edid_buf = kmalloc(FOUR_BLOCK_SIZE, GFP_KERNEL); | |
| 1800 | + if (!edid_buf) | |
| 1801 | + return NULL; | |
| 1802 | + | |
| 1796 | 1803 | pm_runtime_get_sync(dev); |
| 1797 | 1804 | _anx7625_hpd_polling(ctx, 5000 * 100); |
| 1798 | − edid_num = sp_tx_edid_read(ctx, p_edid->edid_raw_data); | |
| 1805 | + edid_num = sp_tx_edid_read(ctx, edid_buf); | |
| 1799 | 1806 | pm_runtime_put_sync(dev); |
| 1800 | 1807 | |
| 1801 | 1808 | if (edid_num < 1) { |
| 1802 | 1809 | DRM_DEV_ERROR(dev, "Fail to read EDID: %d\n", edid_num); |
| 1810 | + kfree(edid_buf); | |
| 1803 | 1811 | return NULL; |
| 1804 | 1812 | } |
| 1805 | 1813 | |
| 1806 | − p_edid->edid_block_num = edid_num; | |
| 1814 | + ctx->cached_drm_edid = drm_edid_alloc(edid_buf, FOUR_BLOCK_SIZE); | |
| 1815 | + kfree(edid_buf); | |
| 1807 | 1816 | |
| 1808 | 1817 | out: |
| 1809 | − return drm_edid_alloc(ctx->slimport_edid_p.edid_raw_data, | |
| 1810 | − FOUR_BLOCK_SIZE); | |
| 1818 | + return drm_edid_dup(ctx->cached_drm_edid); | |
| 1811 | 1819 | } |
| 1812 | 1820 | |
| 1813 | 1821 | static enum drm_connector_status anx7625_sink_detect(struct anx7625_data *ctx) |
| @@ -2193,11 +2201,6 @@ static int anx7625_bridge_attach(struct drm_bridge *bridge, · 379 unmodified lines | ||
| 2193 | 2201 | if (!(flags & DRM_BRIDGE_ATTACH_NO_CONNECTOR)) |
| 2194 | 2202 | return -EINVAL; |
| 2195 | 2203 | |
| 2196 | − if (!bridge->encoder) { | |
| 2197 | − DRM_DEV_ERROR(dev, "Parent encoder object not found"); | |
| 2198 | − return -ENODEV; | |
| 2199 | − } | |
| 2200 | − | |
| 2201 | 2204 | ctx->aux.drm_dev = bridge->dev; |
| 2202 | 2205 | err = drm_dp_aux_register(&ctx->aux); |
| 2203 | 2206 | if (err) { |
| @@ -2435,11 +2438,6 @@ static void anx7625_bridge_atomic_enable(struct drm_bridge *bridge, · 231 unmodified lines | ||
| 2435 | 2438 | |
| 2436 | 2439 | dev_dbg(dev, "drm atomic enable\n"); |
| 2437 | 2440 | |
| 2438 | − if (!bridge->encoder) { | |
| 2439 | − dev_err(dev, "Parent encoder object not found"); | |
| 2440 | − return; | |
| 2441 | − } | |
| 2442 | − | |
| 2443 | 2441 | connector = drm_atomic_get_new_connector_for_encoder(state->base.state, |
| 2444 | 2442 | bridge->encoder); |
| 2445 | 2443 | if (!connector) |
| @@ -286,8 +286,7 @@ · 285 unmodified lines | ||
| 286 | 286 | |
| 287 | 287 | #define MIPI_LANE_CTRL_10 0x0F |
| 288 | 288 | #define MIPI_DIGITAL_ADJ_1 0x1B |
| 289 | −#define IVO_MID0 0x26 | |
| 290 | −#define IVO_MID1 0xCF | |
| 289 | +#define IVO_MID 0x26CF | |
| 291 | 290 | |
| 292 | 291 | #define MIPI_PLL_M_NUM_23_16 0x1E |
| 293 | 292 | #define MIPI_PLL_M_NUM_15_8 0x1F |
| @@ -417,11 +416,6 @@ enum audio_wd_len { · 123 unmodified lines | ||
| 417 | 416 | #define EDID_TRY_CNT 3 |
| 418 | 417 | #define SUPPORT_PIXEL_CLOCK 300000 |
| 419 | 418 | |
| 420 | −struct s_edid_data { | |
| 421 | − int edid_block_num; | |
| 422 | − u8 edid_raw_data[FOUR_BLOCK_SIZE]; | |
| 423 | −}; | |
| 424 | − | |
| 425 | 419 | /***************** Display End *****************/ |
| 426 | 420 | |
| 427 | 421 | #define MAX_LANES_SUPPORT 4 |
| @@ -466,7 +460,7 @@ struct anx7625_data { · 38 unmodified lines | ||
| 466 | 460 | struct anx7625_i2c_client i2c; |
| 467 | 461 | struct i2c_client *last_client; |
| 468 | 462 | struct timer_list hdcp_timer; |
| 469 | − struct s_edid_data slimport_edid_p; | |
| 463 | + const struct drm_edid *cached_drm_edid; | |
| 470 | 464 | struct device *codec_dev; |
| 471 | 465 | hdmi_codec_plugged_cb plugged_cb; |
| 472 | 466 | struct work_struct work; |
| @@ -1697,11 +1697,6 @@ static int cdns_mhdp_connector_init(struct cdns_mhdp_device *mhdp) · 1696 unmodified lines | ||
| 1697 | 1697 | struct drm_bridge *bridge = &mhdp->bridge; |
| 1698 | 1698 | int ret; |
| 1699 | 1699 | |
| 1700 | − if (!bridge->encoder) { | |
| 1701 | − dev_err(mhdp->dev, "Parent encoder object not found"); | |
| 1702 | − return -ENODEV; | |
| 1703 | − } | |
| 1704 | − | |
| 1705 | 1700 | conn->polled = DRM_CONNECTOR_POLL_HPD; |
| 1706 | 1701 | |
| 1707 | 1702 | ret = drm_connector_init(bridge->dev, conn, &cdns_mhdp_conn_funcs, |
| @@ -116,11 +116,6 @@ int ldb_bridge_attach_helper(struct drm_bridge *bridge, · 115 unmodified lines | ||
| 116 | 116 | return -EINVAL; |
| 117 | 117 | } |
| 118 | 118 | |
| 119 | − if (!bridge->encoder) { | |
| 120 | − DRM_DEV_ERROR(ldb->dev, "missing encoder\n"); | |
| 121 | − return -ENODEV; | |
| 122 | − } | |
| 123 | − | |
| 124 | 119 | return drm_bridge_attach(bridge->encoder, |
| 125 | 120 | ldb_ch->next_bridge, bridge, |
| 126 | 121 | DRM_BRIDGE_ATTACH_NO_CONNECTOR); |
| @@ -119,11 +119,6 @@ static int imx8qxp_pc_bridge_attach(struct drm_bridge *bridge, · 118 unmodified lines | ||
| 119 | 119 | return -EINVAL; |
| 120 | 120 | } |
| 121 | 121 | |
| 122 | − if (!bridge->encoder) { | |
| 123 | − DRM_DEV_ERROR(pc->dev, "missing encoder\n"); | |
| 124 | − return -ENODEV; | |
| 125 | − } | |
| 126 | − | |
| 127 | 122 | return drm_bridge_attach(bridge->encoder, |
| 128 | 123 | ch->next_bridge, bridge, |
| 129 | 124 | DRM_BRIDGE_ATTACH_NO_CONNECTOR); |
| @@ -138,11 +138,6 @@ static int imx8qxp_pixel_link_bridge_attach(struct drm_bridge *bridge, · 137 unmodified lines | ||
| 138 | 138 | return -EINVAL; |
| 139 | 139 | } |
| 140 | 140 | |
| 141 | − if (!bridge->encoder) { | |
| 142 | − DRM_DEV_ERROR(pl->dev, "missing encoder\n"); | |
| 143 | − return -ENODEV; | |
| 144 | − } | |
| 145 | − | |
| 146 | 141 | return drm_bridge_attach(bridge->encoder, |
| 147 | 142 | pl->next_bridge, bridge, |
| 148 | 143 | DRM_BRIDGE_ATTACH_NO_CONNECTOR); |
| @@ -58,11 +58,6 @@ static int imx8qxp_pxl2dpi_bridge_attach(struct drm_bridge *bridge, · 57 unmodified lines | ||
| 58 | 58 | return -EINVAL; |
| 59 | 59 | } |
| 60 | 60 | |
| 61 | − if (!bridge->encoder) { | |
| 62 | − DRM_DEV_ERROR(p2d->dev, "missing encoder\n"); | |
| 63 | − return -ENODEV; | |
| 64 | − } | |
| 65 | − | |
| 66 | 61 | return drm_bridge_attach(bridge->encoder, |
| 67 | 62 | p2d->next_bridge, bridge, |
| 68 | 63 | DRM_BRIDGE_ATTACH_NO_CONNECTOR); |
| @@ -1307,9 +1307,15 @@ static void it6505_video_reset(struct it6505 *it6505) · 1306 unmodified lines | ||
| 1307 | 1307 | it6505_link_reset_step_train(it6505); |
| 1308 | 1308 | it6505_set_bits(it6505, REG_DATA_MUTE_CTRL, EN_VID_MUTE, EN_VID_MUTE); |
| 1309 | 1309 | it6505_set_bits(it6505, REG_INFOFRAME_CTRL, EN_VID_CTRL_PKT, 0x00); |
| 1310 | − it6505_set_bits(it6505, REG_RESET_CTRL, VIDEO_RESET, VIDEO_RESET); | |
| 1310 | + | |
| 1311 | + it6505_set_bits(it6505, REG_VID_BUS_CTRL1, TX_FIFO_RESET, TX_FIFO_RESET); | |
| 1312 | + it6505_set_bits(it6505, REG_VID_BUS_CTRL1, TX_FIFO_RESET, 0x00); | |
| 1313 | + | |
| 1311 | 1314 | it6505_set_bits(it6505, REG_501_FIFO_CTRL, RST_501_FIFO, RST_501_FIFO); |
| 1312 | 1315 | it6505_set_bits(it6505, REG_501_FIFO_CTRL, RST_501_FIFO, 0x00); |
| 1316 | + | |
| 1317 | + it6505_set_bits(it6505, REG_RESET_CTRL, VIDEO_RESET, VIDEO_RESET); | |
| 1318 | + usleep_range(1000, 2000); | |
| 1313 | 1319 | it6505_set_bits(it6505, REG_RESET_CTRL, VIDEO_RESET, 0x00); |
| 1314 | 1320 | } |
| 1315 | 1321 | |
| @@ -2245,12 +2251,11 @@ static void it6505_link_training_work(struct work_struct *work) · 929 unmodified lines | ||
| 2245 | 2251 | if (ret) { |
| 2246 | 2252 | it6505->auto_train_retry = AUTO_TRAIN_RETRY; |
| 2247 | 2253 | it6505_link_train_ok(it6505); |
| 2248 | − return; | |
| 2249 | 2254 | } else { |
| 2250 | 2255 | it6505->auto_train_retry--; |
| 2256 | + it6505_dump(it6505); | |
| 2251 | 2257 | } |
| 2252 | 2258 | |
| 2253 | − it6505_dump(it6505); | |
| 2254 | 2259 | } |
| 2255 | 2260 | |
| 2256 | 2261 | static void it6505_plugged_status_to_codec(struct it6505 *it6505) |
| @@ -2471,31 +2476,53 @@ static void it6505_irq_link_train_fail(struct it6505 *it6505) · 214 unmodified lines | ||
| 2471 | 2476 | schedule_work(&it6505->link_works); |
| 2472 | 2477 | } |
| 2473 | 2478 | |
| 2474 | −static void it6505_irq_video_fifo_error(struct it6505 *it6505) | |
| 2479 | +static bool it6505_test_bit(unsigned int bit, const unsigned int *addr) | |
| 2475 | 2480 | { |
| 2476 | − struct device *dev = it6505->dev; | |
| 2477 | − | |
| 2478 | − DRM_DEV_DEBUG_DRIVER(dev, "video fifo overflow interrupt"); | |
| 2479 | − it6505->auto_train_retry = AUTO_TRAIN_RETRY; | |
| 2480 | − flush_work(&it6505->link_works); | |
| 2481 | − it6505_stop_hdcp(it6505); | |
| 2482 | − it6505_video_reset(it6505); | |
| 2481 | + return 1 & (addr[bit / BITS_PER_BYTE] >> (bit % BITS_PER_BYTE)); | |
| 2483 | 2482 | } |
| 2484 | 2483 | |
| 2485 | −static void it6505_irq_io_latch_fifo_overflow(struct it6505 *it6505) | |
| 2484 | +static void it6505_irq_video_handler(struct it6505 *it6505, const int *int_status) | |
| 2486 | 2485 | { |
| 2487 | 2486 | struct device *dev = it6505->dev; |
| 2487 | + int reg_0d, reg_int03; | |
| 2488 | 2488 | |
| 2489 | − DRM_DEV_DEBUG_DRIVER(dev, "IO latch fifo overflow interrupt"); | |
| 2490 | − it6505->auto_train_retry = AUTO_TRAIN_RETRY; | |
| 2491 | − flush_work(&it6505->link_works); | |
| 2492 | − it6505_stop_hdcp(it6505); | |
| 2493 | − it6505_video_reset(it6505); | |
| 2494 | −} | |
| 2489 | + /* | |
| 2490 | + * When video SCDT change with video not stable, | |
| 2491 | + * Or video FIFO error, need video reset | |
| 2492 | + */ | |
| 2495 | 2493 | |
| 2496 | −static bool it6505_test_bit(unsigned int bit, const unsigned int *addr) | |
| 2497 | −{ | |
| 2498 | − return 1 & (addr[bit / BITS_PER_BYTE] >> (bit % BITS_PER_BYTE)); | |
| 2494 | + if ((!it6505_get_video_status(it6505) && | |
| 2495 | + (it6505_test_bit(INT_SCDT_CHANGE, (unsigned int *)int_status))) || | |
| 2496 | + (it6505_test_bit(BIT_INT_IO_FIFO_OVERFLOW, | |
| 2497 | + (unsigned int *)int_status)) || | |
| 2498 | + (it6505_test_bit(BIT_INT_VID_FIFO_ERROR, | |
| 2499 | + (unsigned int *)int_status))) { | |
| 2500 | + it6505->auto_train_retry = AUTO_TRAIN_RETRY; | |
| 2501 | + flush_work(&it6505->link_works); | |
| 2502 | + it6505_stop_hdcp(it6505); | |
| 2503 | + it6505_video_reset(it6505); | |
| 2504 | + | |
| 2505 | + usleep_range(10000, 11000); | |
| 2506 | + | |
| 2507 | + /* | |
| 2508 | + * Clear FIFO error IRQ to prevent fifo error -> reset loop | |
| 2509 | + * HW will trigger SCDT change IRQ again when video stable | |
| 2510 | + */ | |
| 2511 | + | |
| 2512 | + reg_int03 = it6505_read(it6505, INT_STATUS_03); | |
| 2513 | + reg_0d = it6505_read(it6505, REG_SYSTEM_STS); | |
| 2514 | + | |
| 2515 | + reg_int03 &= (BIT(INT_VID_FIFO_ERROR) | BIT(INT_IO_LATCH_FIFO_OVERFLOW)); | |
| 2516 | + it6505_write(it6505, INT_STATUS_03, reg_int03); | |
| 2517 | + | |
| 2518 | + DRM_DEV_DEBUG_DRIVER(dev, "reg08 = 0x%02x", reg_int03); | |
| 2519 | + DRM_DEV_DEBUG_DRIVER(dev, "reg0D = 0x%02x", reg_0d); | |
| 2520 | + | |
| 2521 | + return; | |
| 2522 | + } | |
| 2523 | + | |
| 2524 | + if (it6505_test_bit(INT_SCDT_CHANGE, (unsigned int *)int_status)) | |
| 2525 | + it6505_irq_scdt(it6505); | |
| 2499 | 2526 | } |
| 2500 | 2527 | |
| 2501 | 2528 | static irqreturn_t it6505_int_threaded_handler(int unused, void *data) |
| @@ -2508,15 +2535,12 @@ static irqreturn_t it6505_int_threaded_handler(int unused, void *data) · 6 unmodified lines | ||
| 2508 | 2535 | } irq_vec[] = { |
| 2509 | 2536 | { BIT_INT_HPD, it6505_irq_hpd }, |
| 2510 | 2537 | { BIT_INT_HPD_IRQ, it6505_irq_hpd_irq }, |
| 2511 | − { BIT_INT_SCDT, it6505_irq_scdt }, | |
| 2512 | 2538 | { BIT_INT_HDCP_FAIL, it6505_irq_hdcp_fail }, |
| 2513 | 2539 | { BIT_INT_HDCP_DONE, it6505_irq_hdcp_done }, |
| 2514 | 2540 | { BIT_INT_AUX_CMD_FAIL, it6505_irq_aux_cmd_fail }, |
| 2515 | 2541 | { BIT_INT_HDCP_KSV_CHECK, it6505_irq_hdcp_ksv_check }, |
| 2516 | 2542 | { BIT_INT_AUDIO_FIFO_ERROR, it6505_irq_audio_fifo_error }, |
| 2517 | 2543 | { BIT_INT_LINK_TRAIN_FAIL, it6505_irq_link_train_fail }, |
| 2518 | − { BIT_INT_VID_FIFO_ERROR, it6505_irq_video_fifo_error }, | |
| 2519 | − { BIT_INT_IO_FIFO_OVERFLOW, it6505_irq_io_latch_fifo_overflow }, | |
| 2520 | 2544 | }; |
| 2521 | 2545 | int int_status[3], i; |
| 2522 | 2546 | |
| @@ -2546,6 +2570,7 @@ static irqreturn_t it6505_int_threaded_handler(int unused, void *data) · 23 unmodified lines | ||
| 2546 | 2570 | if (it6505_test_bit(irq_vec[i].bit, (unsigned int *)int_status)) |
| 2547 | 2571 | irq_vec[i].handler(it6505); |
| 2548 | 2572 | } |
| 2573 | + it6505_irq_video_handler(it6505, (unsigned int *)int_status); | |
| 2549 | 2574 | } |
| 2550 | 2575 | |
| 2551 | 2576 | pm_runtime_put_sync(dev); |
| @@ -2590,7 +2615,7 @@ static int it6505_poweron(struct it6505 *it6505) · 38 unmodified lines | ||
| 2590 | 2615 | gpiod_set_value_cansleep(pdata->gpiod_reset, 0); |
| 2591 | 2616 | usleep_range(1000, 2000); |
| 2592 | 2617 | gpiod_set_value_cansleep(pdata->gpiod_reset, 1); |
| 2593 | − usleep_range(10000, 20000); | |
| 2618 | + usleep_range(25000, 35000); | |
| 2594 | 2619 | } |
| 2595 | 2620 | |
| 2596 | 2621 | it6505->powered = true; |
| @@ -2882,11 +2907,6 @@ static int it6505_bridge_attach(struct drm_bridge *bridge, · 285 unmodified lines | ||
| 2882 | 2907 | return -EINVAL; |
| 2883 | 2908 | } |
| 2884 | 2909 | |
| 2885 | − if (!bridge->encoder) { | |
| 2886 | − dev_err(dev, "Parent encoder object not found"); | |
| 2887 | − return -ENODEV; | |
| 2888 | − } | |
| 2889 | − | |
| 2890 | 2910 | /* Register aux channel */ |
| 2891 | 2911 | it6505->aux.drm_dev = bridge->dev; |
| 2892 | 2912 | |
| @@ -1195,4 +1195,5 @@ static struct i2c_driver lt9611_driver = { · 1194 unmodified lines | ||
| 1195 | 1195 | }; |
| 1196 | 1196 | module_i2c_driver(lt9611_driver); |
| 1197 | 1197 | |
| 1198 | +MODULE_DESCRIPTION("Lontium LT9611 DSI/HDMI bridge driver"); | |
| 1198 | 1199 | MODULE_LICENSE("GPL v2"); |
| @@ -337,11 +337,6 @@ static int lt9611uxc_connector_init(struct drm_bridge *bridge, struct lt9611uxc · 336 unmodified lines | ||
| 337 | 337 | { |
| 338 | 338 | int ret; |
| 339 | 339 | |
| 340 | − if (!bridge->encoder) { | |
| 341 | − DRM_ERROR("Parent encoder object not found"); | |
| 342 | − return -ENODEV; | |
| 343 | − } | |
| 344 | − | |
| 345 | 340 | lt9611uxc->connector.polled = DRM_CONNECTOR_POLL_HPD; |
| 346 | 341 | |
| 347 | 342 | drm_connector_helper_add(<9611uxc->connector, |
| @@ -1021,6 +1016,7 @@ static struct i2c_driver lt9611uxc_driver = { · 673 unmodified lines | ||
| 1021 | 1016 | module_i2c_driver(lt9611uxc_driver); |
| 1022 | 1017 | |
| 1023 | 1018 | MODULE_AUTHOR("Dmitry Baryshkov <dmitry.baryshkov@linaro.org>"); |
| 1019 | +MODULE_DESCRIPTION("Lontium LT9611UXC DSI/HDMI bridge driver"); | |
| 1024 | 1020 | MODULE_LICENSE("GPL v2"); |
| 1025 | 1021 | |
| 1026 | 1022 | MODULE_FIRMWARE(FW_FILE); |
| @@ -165,11 +165,6 @@ static int ge_b850v3_lvds_create_connector(struct drm_bridge *bridge) · 164 unmodified lines | ||
| 165 | 165 | struct drm_connector *connector = &ge_b850v3_lvds_ptr->connector; |
| 166 | 166 | int ret; |
| 167 | 167 | |
| 168 | − if (!bridge->encoder) { | |
| 169 | − DRM_ERROR("Parent encoder object not found"); | |
| 170 | − return -ENODEV; | |
| 171 | − } | |
| 172 | − | |
| 173 | 168 | connector->polled = DRM_CONNECTOR_POLL_HPD; |
| 174 | 169 | |
| 175 | 170 | drm_connector_helper_add(connector, |
| @@ -229,11 +229,6 @@ static int ptn3460_bridge_attach(struct drm_bridge *bridge, · 228 unmodified lines | ||
| 229 | 229 | if (flags & DRM_BRIDGE_ATTACH_NO_CONNECTOR) |
| 230 | 230 | return 0; |
| 231 | 231 | |
| 232 | − if (!bridge->encoder) { | |
| 233 | − DRM_ERROR("Parent encoder object not found"); | |
| 234 | − return -ENODEV; | |
| 235 | − } | |
| 236 | − | |
| 237 | 232 | ptn_bridge->connector.polled = DRM_CONNECTOR_POLL_HPD; |
| 238 | 233 | ret = drm_connector_init(bridge->dev, &ptn_bridge->connector, |
| 239 | 234 | &ptn3460_connector_funcs, DRM_MODE_CONNECTOR_LVDS); |
| @@ -67,11 +67,6 @@ static int panel_bridge_attach(struct drm_bridge *bridge, · 66 unmodified lines | ||
| 67 | 67 | if (flags & DRM_BRIDGE_ATTACH_NO_CONNECTOR) |
| 68 | 68 | return 0; |
| 69 | 69 | |
| 70 | − if (!bridge->encoder) { | |
| 71 | − DRM_ERROR("Missing encoder\n"); | |
| 72 | − return -ENODEV; | |
| 73 | − } | |
| 74 | − | |
| 75 | 70 | drm_connector_helper_add(connector, |
| 76 | 71 | &panel_bridge_connector_helper_funcs); |
| 77 | 72 | |
| @@ -574,8 +574,8 @@ static unsigned long samsung_dsim_pll_find_pms(struct samsung_dsim *dsi, · 573 unmodified lines | ||
| 574 | 574 | u16 _m, best_m; |
| 575 | 575 | u8 _s, best_s; |
| 576 | 576 | |
| 577 | − p_min = DIV_ROUND_UP(fin, (12 * MHZ)); | |
| 578 | − p_max = fin / (6 * MHZ); | |
| 577 | + p_min = DIV_ROUND_UP(fin, (driver_data->pll_fin_max * MHZ)); | |
| 578 | + p_max = fin / (driver_data->pll_fin_min * MHZ); | |
| 579 | 579 | |
| 580 | 580 | for (_p = p_min; _p <= p_max; ++_p) { |
| 581 | 581 | for (_s = 0; _s <= 5; ++_s) { |
| @@ -1606,6 +1606,27 @@ static int samsung_dsim_atomic_check(struct drm_bridge *bridge, · 1024 unmodified lines | ||
| 1606 | 1606 | adjusted_mode->flags |= (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC); |
| 1607 | 1607 | } |
| 1608 | 1608 | |
| 1609 | + /* | |
| 1610 | + * When using video sync pulses, the HFP, HBP, and HSA are divided between | |
| 1611 | + * the available lanes if there is more than one lane. For certain | |
| 1612 | + * timings and lane configurations, the HFP may not be evenly divisible. | |
| 1613 | + * If the HFP is rounded down, it ends up being too small which can cause | |
| 1614 | + * some monitors to not sync properly. In these instances, adjust htotal | |
| 1615 | + * and hsync to round the HFP up, and recalculate the htotal. Through trial | |
| 1616 | + * and error, it appears that the HBP and HSA do not appearto need the same | |
| 1617 | + * correction that HFP does. | |
| 1618 | + */ | |
| 1619 | + if (dsi->lanes > 1) { | |
| 1620 | + int hfp = adjusted_mode->hsync_start - adjusted_mode->hdisplay; | |
| 1621 | + int remainder = hfp % dsi->lanes; | |
| 1622 | + | |
| 1623 | + if (remainder) { | |
| 1624 | + adjusted_mode->hsync_start += remainder; | |
| 1625 | + adjusted_mode->hsync_end += remainder; | |
| 1626 | + adjusted_mode->htotal += remainder; | |
| 1627 | + } | |
| 1628 | + } | |
| 1629 | + | |
| 1609 | 1630 | return 0; |
| 1610 | 1631 | } |
| 1611 | 1632 | |
| @@ -163,6 +163,14 @@ · 162 unmodified lines | ||
| 163 | 163 | |
| 164 | 164 | #define SII902X_AUDIO_PORT_INDEX 3 |
| 165 | 165 | |
| 166 | +/* | |
| 167 | + * The maximum resolution supported by the HDMI bridge is 1080p@60Hz | |
| 168 | + * and 1920x1200 requiring a pixel clock of 165MHz and the minimum | |
| 169 | + * resolution supported is 480p@60Hz requiring a pixel clock of 25MHz | |
| 170 | + */ | |
| 171 | +#define SII902X_MIN_PIXEL_CLOCK_KHZ 25000 | |
| 172 | +#define SII902X_MAX_PIXEL_CLOCK_KHZ 165000 | |
| 173 | + | |
| 166 | 174 | struct sii902x { |
| 167 | 175 | struct i2c_client *i2c; |
| 168 | 176 | struct regmap *regmap; |
| @@ -310,20 +318,12 @@ static int sii902x_get_modes(struct drm_connector *connector) · 141 unmodified lines | ||
| 310 | 318 | return num; |
| 311 | 319 | } |
| 312 | 320 | |
| 313 | −static enum drm_mode_status sii902x_mode_valid(struct drm_connector *connector, | |
| 314 | − struct drm_display_mode *mode) | |
| 315 | −{ | |
| 316 | − /* TODO: check mode */ | |
| 317 | − | |
| 318 | − return MODE_OK; | |
| 319 | −} | |
| 320 | − | |
| 321 | 321 | static const struct drm_connector_helper_funcs sii902x_connector_helper_funcs = { |
| 322 | 322 | .get_modes = sii902x_get_modes, |
| 323 | − .mode_valid = sii902x_mode_valid, | |
| 324 | 323 | }; |
| 325 | 324 | |
| 326 | −static void sii902x_bridge_disable(struct drm_bridge *bridge) | |
| 325 | +static void sii902x_bridge_atomic_disable(struct drm_bridge *bridge, | |
| 326 | + struct drm_bridge_state *old_bridge_state) | |
| 327 | 327 | { |
| 328 | 328 | struct sii902x *sii902x = bridge_to_sii902x(bridge); |
| 329 | 329 | |
| @@ -336,7 +336,8 @@ static void sii902x_bridge_disable(struct drm_bridge *bridge) · 6 unmodified lines | ||
| 336 | 336 | mutex_unlock(&sii902x->mutex); |
| 337 | 337 | } |
| 338 | 338 | |
| 339 | −static void sii902x_bridge_enable(struct drm_bridge *bridge) | |
| 339 | +static void sii902x_bridge_atomic_enable(struct drm_bridge *bridge, | |
| 340 | + struct drm_bridge_state *old_bridge_state) | |
| 340 | 341 | { |
| 341 | 342 | struct sii902x *sii902x = bridge_to_sii902x(bridge); |
| 342 | 343 | |
| @@ -495,6 +496,10 @@ static int sii902x_bridge_atomic_check(struct drm_bridge *bridge, · 152 unmodified lines | ||
| 495 | 496 | struct drm_crtc_state *crtc_state, |
| 496 | 497 | struct drm_connector_state *conn_state) |
| 497 | 498 | { |
| 499 | + if (crtc_state->mode.clock < SII902X_MIN_PIXEL_CLOCK_KHZ || | |
| 500 | + crtc_state->mode.clock > SII902X_MAX_PIXEL_CLOCK_KHZ) | |
| 501 | + return -EINVAL; | |
| 502 | + | |
| 498 | 503 | /* |
| 499 | 504 | * There might be flags negotiation supported in future but |
| 500 | 505 | * set the bus flags in atomic_check statically for now. |
| @@ -504,11 +509,25 @@ static int sii902x_bridge_atomic_check(struct drm_bridge *bridge, · 3 unmodified lines | ||
| 504 | 509 | return 0; |
| 505 | 510 | } |
| 506 | 511 | |
| 512 | +static enum drm_mode_status | |
| 513 | +sii902x_bridge_mode_valid(struct drm_bridge *bridge, | |
| 514 | + const struct drm_display_info *info, | |
| 515 | + const struct drm_display_mode *mode) | |
| 516 | +{ | |
| 517 | + if (mode->clock < SII902X_MIN_PIXEL_CLOCK_KHZ) | |
| 518 | + return MODE_CLOCK_LOW; | |
| 519 | + | |
| 520 | + if (mode->clock > SII902X_MAX_PIXEL_CLOCK_KHZ) | |
| 521 | + return MODE_CLOCK_HIGH; | |
| 522 | + | |
| 523 | + return MODE_OK; | |
| 524 | +} | |
| 525 | + | |
| 507 | 526 | static const struct drm_bridge_funcs sii902x_bridge_funcs = { |
| 508 | 527 | .attach = sii902x_bridge_attach, |
| 509 | 528 | .mode_set = sii902x_bridge_mode_set, |
| 510 | − .disable = sii902x_bridge_disable, | |
| 511 | − .enable = sii902x_bridge_enable, | |
| 529 | + .atomic_disable = sii902x_bridge_atomic_disable, | |
| 530 | + .atomic_enable = sii902x_bridge_atomic_enable, | |
| 512 | 531 | .detect = sii902x_bridge_detect, |
| 513 | 532 | .edid_read = sii902x_bridge_edid_read, |
| 514 | 533 | .atomic_reset = drm_atomic_helper_bridge_reset, |
| @@ -516,6 +535,7 @@ static const struct drm_bridge_funcs sii902x_bridge_funcs = { · 1 unmodified line | ||
| 516 | 535 | .atomic_destroy_state = drm_atomic_helper_bridge_destroy_state, |
| 517 | 536 | .atomic_get_input_bus_fmts = sii902x_bridge_atomic_get_input_bus_fmts, |
| 518 | 537 | .atomic_check = sii902x_bridge_atomic_check, |
| 538 | + .mode_valid = sii902x_bridge_mode_valid, | |
| 519 | 539 | }; |
| 520 | 540 | |
| 521 | 541 | static int sii902x_mute(struct sii902x *sii902x, bool mute) |
| @@ -961,4 +961,5 @@ static struct i2c_driver sii9234_driver = { · 960 unmodified lines | ||
| 961 | 961 | }; |
| 962 | 962 | |
| 963 | 963 | module_i2c_driver(sii9234_driver); |
| 964 | +MODULE_DESCRIPTION("Silicon Image SII9234 HDMI/MHL bridge driver"); | |
| 964 | 965 | MODULE_LICENSE("GPL"); |
| @@ -2384,4 +2384,5 @@ static struct i2c_driver sii8620_driver = { · 2383 unmodified lines | ||
| 2384 | 2384 | }; |
| 2385 | 2385 | |
| 2386 | 2386 | module_i2c_driver(sii8620_driver); |
| 2387 | +MODULE_DESCRIPTION("Silicon Image SiI8620 HDMI/MHL bridge driver"); | |
| 2387 | 2388 | MODULE_LICENSE("GPL v2"); |
| @@ -116,11 +116,6 @@ static int simple_bridge_attach(struct drm_bridge *bridge, · 115 unmodified lines | ||
| 116 | 116 | if (flags & DRM_BRIDGE_ATTACH_NO_CONNECTOR) |
| 117 | 117 | return 0; |
| 118 | 118 | |
| 119 | − if (!bridge->encoder) { | |
| 120 | − DRM_ERROR("Missing encoder\n"); | |
| 121 | − return -ENODEV; | |
| 122 | − } | |
| 123 | − | |
| 124 | 119 | drm_connector_helper_add(&sbridge->connector, |
| 125 | 120 | &simple_bridge_con_helper_funcs); |
| 126 | 121 | ret = drm_connector_init_with_ddc(bridge->dev, &sbridge->connector, |
| @@ -175,7 +170,6 @@ static int simple_bridge_probe(struct platform_device *pdev) · 48 unmodified lines | ||
| 175 | 170 | sbridge = devm_kzalloc(&pdev->dev, sizeof(*sbridge), GFP_KERNEL); |
| 176 | 171 | if (!sbridge) |
| 177 | 172 | return -ENOMEM; |
| 178 | − platform_set_drvdata(pdev, sbridge); | |
| 179 | 173 | |
| 180 | 174 | sbridge->info = of_device_get_match_data(&pdev->dev); |
| 181 | 175 | |
| @@ -213,16 +207,7 @@ static int simple_bridge_probe(struct platform_device *pdev) · 31 unmodified lines | ||
| 213 | 207 | sbridge->bridge.of_node = pdev->dev.of_node; |
| 214 | 208 | sbridge->bridge.timings = sbridge->info->timings; |
| 215 | 209 | |
| 216 | − drm_bridge_add(&sbridge->bridge); | |
| 217 | − | |
| 218 | − return 0; | |
| 219 | −} | |
| 220 | − | |
| 221 | −static void simple_bridge_remove(struct platform_device *pdev) | |
| 222 | −{ | |
| 223 | − struct simple_bridge *sbridge = platform_get_drvdata(pdev); | |
| 224 | − | |
| 225 | − drm_bridge_remove(&sbridge->bridge); | |
| 210 | + return devm_drm_bridge_add(&pdev->dev, &sbridge->bridge); | |
| 226 | 211 | } |
| 227 | 212 | |
| 228 | 213 | /* |
| @@ -299,7 +284,6 @@ MODULE_DEVICE_TABLE(of, simple_bridge_match); · 70 unmodified lines | ||
| 299 | 284 | |
| 300 | 285 | static struct platform_driver simple_bridge_driver = { |
| 301 | 286 | .probe = simple_bridge_probe, |
| 302 | − .remove_new = simple_bridge_remove, | |
| 303 | 287 | .driver = { |
| 304 | 288 | .name = "simple-bridge", |
| 305 | 289 | .of_match_table = simple_bridge_match, |
| @@ -1071,11 +1071,6 @@ static int dw_mipi_dsi_bridge_attach(struct drm_bridge *bridge, · 1070 unmodified lines | ||
| 1071 | 1071 | { |
| 1072 | 1072 | struct dw_mipi_dsi *dsi = bridge_to_dsi(bridge); |
| 1073 | 1073 | |
| 1074 | − if (!bridge->encoder) { | |
| 1075 | − DRM_ERROR("Parent encoder object not found\n"); | |
| 1076 | − return -ENODEV; | |
| 1077 | − } | |
| 1078 | − | |
| 1079 | 1074 | /* Set the encoder type as caller does not know it */ |
| 1080 | 1075 | bridge->encoder->encoder_type = DRM_MODE_ENCODER_DSI; |
| 1081 | 1076 | |
| @@ -382,6 +382,9 @@ struct tc_data { · 381 unmodified lines | ||
| 382 | 382 | |
| 383 | 383 | /* HPD pin number (0 or 1) or -ENODEV */ |
| 384 | 384 | int hpd_pin; |
| 385 | + | |
| 386 | + /* Number of pixels to subtract from a line due to pixel clock delta */ | |
| 387 | + u32 line_pixel_subtract; | |
| 385 | 388 | }; |
| 386 | 389 | |
| 387 | 390 | static inline struct tc_data *aux_to_tc(struct drm_dp_aux *a) |
| @@ -577,6 +580,11 @@ static int tc_pllupdate(struct tc_data *tc, unsigned int pllctrl) · 189 unmodified lines | ||
| 577 | 580 | return 0; |
| 578 | 581 | } |
| 579 | 582 | |
| 583 | +static u32 div64_round_up(u64 v, u32 d) | |
| 584 | +{ | |
| 585 | + return div_u64(v + d - 1, d); | |
| 586 | +} | |
| 587 | + | |
| 580 | 588 | static int tc_pxl_pll_en(struct tc_data *tc, u32 refclk, u32 pixelclock) |
| 581 | 589 | { |
| 582 | 590 | int ret; |
| @@ -658,8 +666,11 @@ static int tc_pxl_pll_en(struct tc_data *tc, u32 refclk, u32 pixelclock) · 75 unmodified lines | ||
| 658 | 666 | return -EINVAL; |
| 659 | 667 | } |
| 660 | 668 | |
| 661 | − dev_dbg(tc->dev, "PLL: got %d, delta %d\n", best_pixelclock, | |
| 662 | − best_delta); | |
| 669 | + tc->line_pixel_subtract = tc->mode.htotal - | |
| 670 | + div64_round_up(tc->mode.htotal * (u64)best_pixelclock, pixelclock); | |
| 671 | + | |
| 672 | + dev_dbg(tc->dev, "PLL: got %d, delta %d (subtract %d px)\n", best_pixelclock, | |
| 673 | + best_delta, tc->line_pixel_subtract); | |
| 663 | 674 | dev_dbg(tc->dev, "PLL: %d / %d / %d * %d / %d\n", refclk, |
| 664 | 675 | ext_div[best_pre], best_div, best_mul, ext_div[best_post]); |
| 665 | 676 | |
| @@ -885,6 +896,12 @@ static int tc_set_common_video_mode(struct tc_data *tc, · 219 unmodified lines | ||
| 885 | 896 | upper_margin, lower_margin, vsync_len); |
| 886 | 897 | dev_dbg(tc->dev, "total: %dx%d\n", mode->htotal, mode->vtotal); |
| 887 | 898 | |
| 899 | + if (right_margin > tc->line_pixel_subtract) { | |
| 900 | + right_margin -= tc->line_pixel_subtract; | |
| 901 | + } else { | |
| 902 | + dev_err(tc->dev, "Bridge pixel clock too slow for mode\n"); | |
| 903 | + right_margin = 0; | |
| 904 | + } | |
| 888 | 905 | |
| 889 | 906 | /* |
| 890 | 907 | * LCD Ctl Frame Size |
| @@ -894,7 +911,7 @@ static int tc_set_common_video_mode(struct tc_data *tc, · 3 unmodified lines | ||
| 894 | 911 | */ |
| 895 | 912 | ret = regmap_write(tc->regmap, VPCTRL0, |
| 896 | 913 | FIELD_PREP(VSDELAY, right_margin + 10) | |
| 897 | − OPXLFMT_RGB888 | FRMSYNC_DISABLED | MSF_DISABLED); | |
| 914 | + OPXLFMT_RGB888 | FRMSYNC_ENABLED | MSF_DISABLED); | |
| 898 | 915 | if (ret) |
| 899 | 916 | return ret; |
| 900 | 917 | |
| @@ -1629,7 +1646,7 @@ tc_edp_mode_valid(struct drm_bridge *bridge, · 728 unmodified lines | ||
| 1629 | 1646 | u32 req, avail; |
| 1630 | 1647 | u32 bits_per_pixel = 24; |
| 1631 | 1648 | |
| 1632 | − /* DPI interface clock limitation: upto 154 MHz */ | |
| 1649 | + /* DPI->(e)DP interface clock limitation: up to 154 MHz */ | |
| 1633 | 1650 | if (mode->clock > 154000) |
| 1634 | 1651 | return MODE_CLOCK_HIGH; |
| 1635 | 1652 | |
| @@ -2135,7 +2152,7 @@ static irqreturn_t tc_irq_handler(int irq, void *arg) · 499 unmodified lines | ||
| 2135 | 2152 | dev_err(tc->dev, "syserr %x\n", stat); |
| 2136 | 2153 | } |
| 2137 | 2154 | |
| 2138 | − if (tc->hpd_pin >= 0 && tc->bridge.dev) { | |
| 2155 | + if (tc->hpd_pin >= 0 && tc->bridge.dev && tc->aux.drm_dev) { | |
| 2139 | 2156 | /* |
| 2140 | 2157 | * H is triggered when the GPIO goes high. |
| 2141 | 2158 | * |
| @@ -133,11 +133,6 @@ static int tfp410_attach(struct drm_bridge *bridge, · 132 unmodified lines | ||
| 133 | 133 | if (flags & DRM_BRIDGE_ATTACH_NO_CONNECTOR) |
| 134 | 134 | return 0; |
| 135 | 135 | |
| 136 | − if (!bridge->encoder) { | |
| 137 | − dev_err(dvi->dev, "Missing encoder\n"); | |
| 138 | − return -ENODEV; | |
| 139 | − } | |
| 140 | − | |
| 141 | 136 | if (dvi->next_bridge->ops & DRM_BRIDGE_OP_DETECT) |
| 142 | 137 | dvi->connector.polled = DRM_CONNECTOR_POLL_HPD; |
| 143 | 138 | else |
| @@ -3,6 +3,30 @@ · 2 unmodified lines | ||
| 3 | 3 | |
| 4 | 4 | set -ex |
| 5 | 5 | |
| 6 | +function generate_testlist { | |
| 7 | + set +x | |
| 8 | + while read -r line; do | |
| 9 | + if [ "$line" = "TESTLIST" ] || [ "$line" = "END TESTLIST" ]; then | |
| 10 | + continue | |
| 11 | + fi | |
| 12 | + | |
| 13 | + tests=$(echo "$line" | tr ' ' '\n') | |
| 14 | + | |
| 15 | + for test in $tests; do | |
| 16 | + output=$(/igt/libexec/igt-gpu-tools/"$test" --list-subtests || true) | |
| 17 | + | |
| 18 | + if [ -z "$output" ]; then | |
| 19 | + echo "$test" | |
| 20 | + else | |
| 21 | + echo "$output" | while read -r subtest; do | |
| 22 | + echo "$test@$subtest" | |
| 23 | + done | |
| 24 | + fi | |
| 25 | + done | |
| 26 | + done < /igt/libexec/igt-gpu-tools/test-list.txt > /igt/libexec/igt-gpu-tools/ci-testlist.txt | |
| 27 | + set -x | |
| 28 | +} | |
| 29 | + | |
| 6 | 30 | git clone https://gitlab.freedesktop.org/drm/igt-gpu-tools.git --single-branch --no-checkout |
| 7 | 31 | cd igt-gpu-tools |
| 8 | 32 | git checkout $IGT_VERSION |
| @@ -21,15 +45,30 @@ MESON_OPTIONS="-Doverlay=disabled \ · 12 unmodified lines | ||
| 21 | 45 | -Dlibunwind=enabled \ |
| 22 | 46 | -Dprefix=/igt" |
| 23 | 47 | |
| 48 | +if [[ "$KERNEL_ARCH" = "arm64" ]] || [[ "$KERNEL_ARCH" = "arm" ]]; then | |
| 49 | + MESON_OPTIONS="$MESON_OPTIONS -Dxe_driver=disabled" | |
| 50 | +fi | |
| 51 | + | |
| 24 | 52 | mkdir -p /igt |
| 25 | 53 | meson build $MESON_OPTIONS $EXTRA_MESON_ARGS |
| 26 | 54 | ninja -C build -j${FDO_CI_CONCURRENT:-4} || ninja -C build -j 1 |
| 27 | 55 | ninja -C build install |
| 28 | 56 | |
| 57 | +if [[ "$KERNEL_ARCH" = "arm64" ]]; then | |
| 58 | + export LD_LIBRARY_PATH=$LD_LIBRARY_PATH:/igt/lib/aarch64-linux-gnu | |
| 59 | +elif [[ "$KERNEL_ARCH" = "arm" ]]; then | |
| 60 | + export LD_LIBRARY_PATH=$LD_LIBRARY_PATH:/igt/lib | |
| 61 | +else | |
| 62 | + export LD_LIBRARY_PATH=$LD_LIBRARY_PATH:/igt/lib64 | |
| 63 | +fi | |
| 64 | + | |
| 65 | +echo "Generating ci-testlist.txt" | |
| 66 | +generate_testlist | |
| 67 | + | |
| 29 | 68 | mkdir -p artifacts/ |
| 30 | 69 | tar -cf artifacts/igt.tar /igt |
| 31 | 70 | |
| 32 | 71 | # Pass needed files to the test stage |
| 33 | 72 | S3_ARTIFACT_NAME="igt.tar.gz" |
| 34 | 73 | gzip -c artifacts/igt.tar > ${S3_ARTIFACT_NAME} |
| 35 | −ci-fairy s3cp --token-file "${CI_JOB_JWT_FILE}" ${S3_ARTIFACT_NAME} https://${PIPELINE_ARTIFACTS_BASE}/${KERNEL_ARCH}/${S3_ARTIFACT_NAME} | |
| 74 | +ci-fairy s3cp --token-file "${S3_JWT_FILE}" ${S3_ARTIFACT_NAME} https://${PIPELINE_ARTIFACTS_BASE}/${KERNEL_ARCH}/${S3_ARTIFACT_NAME} | |
| @@ -12,6 +12,9 @@ rm -rf .git/rebase-apply · 11 unmodified lines | ||
| 12 | 12 | apt-get update |
| 13 | 13 | apt-get install -y libssl-dev |
| 14 | 14 | |
| 15 | +# for msm header validation | |
| 16 | +apt-get install -y python3-lxml | |
| 17 | + | |
| 15 | 18 | if [[ "$KERNEL_ARCH" = "arm64" ]]; then |
| 16 | 19 | GCC_ARCH="aarch64-linux-gnu" |
| 17 | 20 | DEBIAN_ARCH="arm64" |
| @@ -128,6 +131,7 @@ fi · 110 unmodified lines | ||
| 128 | 131 | # Pass needed files to the test stage |
| 129 | 132 | mkdir -p install |
| 130 | 133 | cp -rfv .gitlab-ci/* install/. |
| 134 | +cp -rfv ci/* install/. | |
| 131 | 135 | cp -rfv install/common install/ci-common |
| 132 | 136 | cp -rfv drivers/gpu/drm/ci/* install/. |
| 133 | 137 | |
| @@ -141,21 +145,21 @@ if [[ "$UPLOAD_TO_MINIO" = "1" ]]; then · 7 unmodified lines | ||
| 141 | 145 | FILES_TO_UPLOAD="$FILES_TO_UPLOAD $(basename -a $DEVICE_TREES)" |
| 142 | 146 | fi |
| 143 | 147 | |
| 148 | + ls -l "${S3_JWT_FILE}" | |
| 144 | 149 | for f in $FILES_TO_UPLOAD; do |
| 145 | − ci-fairy s3cp --token-file "${CI_JOB_JWT_FILE}" /lava-files/$f \ | |
| 150 | + ci-fairy s3cp --token-file "${S3_JWT_FILE}" /lava-files/$f \ | |
| 146 | 151 | https://${PIPELINE_ARTIFACTS_BASE}/${DEBIAN_ARCH}/$f |
| 147 | 152 | done |
| 148 | 153 | |
| 149 | 154 | S3_ARTIFACT_NAME="kernel-files.tar.zst" |
| 150 | 155 | tar --zstd -cf $S3_ARTIFACT_NAME install |
| 151 | − ci-fairy s3cp --token-file "${CI_JOB_JWT_FILE}" ${S3_ARTIFACT_NAME} https://${PIPELINE_ARTIFACTS_BASE}/${DEBIAN_ARCH}/${S3_ARTIFACT_NAME} | |
| 156 | + ci-fairy s3cp --token-file "${S3_JWT_FILE}" ${S3_ARTIFACT_NAME} https://${PIPELINE_ARTIFACTS_BASE}/${DEBIAN_ARCH}/${S3_ARTIFACT_NAME} | |
| 152 | 157 | |
| 153 | 158 | echo "Download vmlinux.xz from https://${PIPELINE_ARTIFACTS_BASE}/${DEBIAN_ARCH}/vmlinux.xz" |
| 154 | 159 | fi |
| 155 | 160 | |
| 156 | 161 | mkdir -p artifacts/install/lib |
| 157 | 162 | mv install/* artifacts/install/. |
| 158 | −rm -rf artifacts/install/modules | |
| 159 | 163 | ln -s common artifacts/install/ci-common |
| 160 | 164 | cp .config artifacts/${CI_JOB_NAME}_config |
| 161 | 165 | |
| @@ -106,6 +106,7 @@ build-nodebugfs:arm64: · 105 unmodified lines | ||
| 106 | 106 | extends: .build:arm64 |
| 107 | 107 | variables: |
| 108 | 108 | DISABLE_KCONFIGS: "DEBUG_FS" |
| 109 | + ENABLE_KCONFIGS: "EXPERT DRM_MSM_VALIDATE_XML" | |
| 109 | 110 | |
| 110 | 111 | build:x86_64: |
| 111 | 112 | extends: .build:x86_64 |
| @@ -36,15 +36,15 @@ debian/android_build: · 35 unmodified lines | ||
| 36 | 36 | rules: |
| 37 | 37 | - when: never |
| 38 | 38 | |
| 39 | −debian/x86_64_test-android: | |
| 39 | +.debian/x86_64_test-android: | |
| 40 | 40 | rules: |
| 41 | 41 | - when: never |
| 42 | 42 | |
| 43 | −windows_build_vs2019: | |
| 43 | +windows_build_msvc: | |
| 44 | 44 | rules: |
| 45 | 45 | - when: never |
| 46 | 46 | |
| 47 | −windows_test_vs2019: | |
| 47 | +windows_test_msvc: | |
| 48 | 48 | rules: |
| 49 | 49 | - when: never |
| 50 | 50 | |
| @@ -56,10 +56,6 @@ rustfmt: · 5 unmodified lines | ||
| 56 | 56 | rules: |
| 57 | 57 | - when: never |
| 58 | 58 | |
| 59 | −windows_vs2019: | |
| 60 | − rules: | |
| 61 | − - when: never | |
| 62 | − | |
| 63 | −clang-format: | |
| 59 | +windows_msvc: | |
| 64 | 60 | rules: |
| 65 | 61 | - when: never |
| @@ -1,11 +1,11 @@ | ||
| 1 | 1 | variables: |
| 2 | 2 | DRM_CI_PROJECT_PATH: &drm-ci-project-path mesa/mesa |
| 3 | − DRM_CI_COMMIT_SHA: &drm-ci-commit-sha 9d162de9a05155e1c4041857a5848842749164cf | |
| 3 | + DRM_CI_COMMIT_SHA: &drm-ci-commit-sha e2b9c5a9e3e4f9b532067af8022eaef8d6fc6c00 | |
| 4 | 4 | |
| 5 | 5 | UPSTREAM_REPO: git://anongit.freedesktop.org/drm/drm |
| 6 | 6 | TARGET_BRANCH: drm-next |
| 7 | 7 | |
| 8 | − IGT_VERSION: d2af13d9f5be5ce23d996e4afd3e45990f5ab977 | |
| 8 | + IGT_VERSION: 0df7b9b97f9da0e364f5ee30fe331004b8c86b56 | |
| 9 | 9 | |
| 10 | 10 | DEQP_RUNNER_GIT_URL: https://gitlab.freedesktop.org/anholt/deqp-runner.git |
| 11 | 11 | DEQP_RUNNER_GIT_TAG: v0.15.0 |
| @@ -19,33 +19,47 @@ variables: · 7 unmodified lines | ||
| 19 | 19 | bash download-git-cache.sh |
| 20 | 20 | rm download-git-cache.sh |
| 21 | 21 | set +o xtrace |
| 22 | + S3_JWT_FILE: /s3_jwt | |
| 22 | 23 | S3_HOST: s3.freedesktop.org |
| 24 | + # This bucket is used to fetch the kernel image | |
| 25 | + S3_KERNEL_BUCKET: mesa-rootfs | |
| 26 | + # Bucket for git cache | |
| 27 | + S3_GITCACHE_BUCKET: git-cache | |
| 28 | + # Bucket for the pipeline artifacts pushed to S3 | |
| 29 | + S3_ARTIFACTS_BUCKET: artifacts | |
| 23 | 30 | # per-pipeline artifact storage on MinIO |
| 24 | − PIPELINE_ARTIFACTS_BASE: ${S3_HOST}/artifacts/${CI_PROJECT_PATH}/${CI_PIPELINE_ID} | |
| 31 | + PIPELINE_ARTIFACTS_BASE: ${S3_HOST}/${S3_ARTIFACTS_BUCKET}/${CI_PROJECT_PATH}/${CI_PIPELINE_ID} | |
| 25 | 32 | # per-job artifact storage on MinIO |
| 26 | 33 | JOB_ARTIFACTS_BASE: ${PIPELINE_ARTIFACTS_BASE}/${CI_JOB_ID} |
| 27 | 34 | # default kernel for rootfs before injecting the current kernel tree |
| 28 | 35 | KERNEL_REPO: "gfx-ci/linux" |
| 29 | − KERNEL_TAG: "v6.6.4-for-mesa-ci-e4f4c500f7fb" | |
| 30 | − KERNEL_IMAGE_BASE: https://${S3_HOST}/mesa-lava/${KERNEL_REPO}/${KERNEL_TAG} | |
| 36 | + KERNEL_TAG: "v6.6.21-mesa-f8ea" | |
| 37 | + KERNEL_IMAGE_BASE: https://${S3_HOST}/${S3_KERNEL_BUCKET}/${KERNEL_REPO}/${KERNEL_TAG} | |
| 38 | + PKG_REPO_REV: "3cc12a2a" | |
| 31 | 39 | LAVA_TAGS: subset-1-gfx |
| 32 | 40 | LAVA_JOB_PRIORITY: 30 |
| 41 | + ARTIFACTS_BASE_URL: https://${CI_PROJECT_ROOT_NAMESPACE}.${CI_PAGES_DOMAIN}/-/${CI_PROJECT_NAME}/-/jobs/${CI_JOB_ID}/artifacts | |
| 42 | + # Python scripts for structured logger | |
| 43 | + PYTHONPATH: "$PYTHONPATH:$CI_PROJECT_DIR/install" | |
| 33 | 44 | |
| 34 | 45 | default: |
| 46 | + id_tokens: | |
| 47 | + S3_JWT: | |
| 48 | + aud: https://s3.freedesktop.org | |
| 35 | 49 | before_script: |
| 36 | 50 | - export SCRIPTS_DIR=$(mktemp -d) |
| 37 | 51 | - curl -L -s --retry 4 -f --retry-all-errors --retry-delay 60 -O --output-dir "${SCRIPTS_DIR}" "${DRM_CI_PROJECT_URL}/-/raw/${DRM_CI_COMMIT_SHA}/.gitlab-ci/setup-test-env.sh" |
| 38 | 52 | - source ${SCRIPTS_DIR}/setup-test-env.sh |
| 39 | 53 | - echo -e "\e[0Ksection_start:$(date +%s):unset_env_vars_section[collapsed=true]\r\e[0KUnsetting vulnerable environment variables" |
| 40 | − - export CI_JOB_JWT_FILE="${CI_JOB_JWT_FILE:-$(mktemp)}" | |
| 41 | − - echo -n "${CI_JOB_JWT}" > "${CI_JOB_JWT_FILE}" | |
| 42 | − - unset CI_JOB_JWT | |
| 54 | + - echo -n "${S3_JWT}" > "${S3_JWT_FILE}" | |
| 55 | + - unset CI_JOB_JWT S3_JWT | |
| 43 | 56 | - echo -e "\e[0Ksection_end:$(date +%s):unset_env_vars_section\r\e[0K" |
| 44 | 57 | |
| 45 | 58 | - echo -e "\e[0Ksection_start:$(date +%s):drm_ci_download_section[collapsed=true]\r\e[0KDownloading mesa from $DRM_CI_PROJECT_URL/-/archive/$DRM_CI_COMMIT_SHA/mesa-$DRM_CI_COMMIT_SHA.tar.gz" |
| 46 | 59 | - cd $CI_PROJECT_DIR |
| 47 | 60 | - curl --output - $DRM_CI_PROJECT_URL/-/archive/$DRM_CI_COMMIT_SHA/mesa-$DRM_CI_COMMIT_SHA.tar.gz | tar -xz |
| 48 | 61 | - mv mesa-$DRM_CI_COMMIT_SHA/.gitlab-ci* . |
| 62 | + - mv mesa-$DRM_CI_COMMIT_SHA/bin/ci . | |
| 49 | 63 | - rm -rf mesa-$DRM_CI_COMMIT_SHA/ |
| 50 | 64 | - echo -e "\e[0Ksection_end:$(date +%s):drm_ci_download_section\r\e[0K" |
| 51 | 65 | |
| @@ -53,9 +67,9 @@ default: · 1 unmodified line | ||
| 53 | 67 | - > |
| 54 | 68 | set +x |
| 55 | 69 | |
| 56 | − test -e "${CI_JOB_JWT_FILE}" && | |
| 57 | − export CI_JOB_JWT="$(<${CI_JOB_JWT_FILE})" && | |
| 58 | − rm "${CI_JOB_JWT_FILE}" | |
| 70 | + test -e "${S3_JWT_FILE}" && | |
| 71 | + export S3_JWT="$(<${S3_JWT_FILE})" && | |
| 72 | + rm "${S3_JWT_FILE}" | |
| 59 | 73 | |
| 60 | 74 | include: |
| 61 | 75 | - project: 'freedesktop/ci-templates' |
| @@ -87,6 +101,7 @@ include: · 25 unmodified lines | ||
| 87 | 101 | - '/src/intel/ci/gitlab-ci-inc.yml' |
| 88 | 102 | - '/src/freedreno/ci/gitlab-ci-inc.yml' |
| 89 | 103 | - '/src/amd/ci/gitlab-ci-inc.yml' |
| 104 | + - '/src/virtio/ci/gitlab-ci-inc.yml' | |
| 90 | 105 | - drivers/gpu/drm/ci/image-tags.yml |
| 91 | 106 | - drivers/gpu/drm/ci/container.yml |
| 92 | 107 | - drivers/gpu/drm/ci/static-checks.yml |
| @@ -98,6 +113,7 @@ include: · 5 unmodified lines | ||
| 98 | 113 | stages: |
| 99 | 114 | - sanity |
| 100 | 115 | - container |
| 116 | + - code-validation | |
| 101 | 117 | - git-archive |
| 102 | 118 | - build |
| 103 | 119 | - amdgpu |
| @@ -107,7 +123,7 @@ stages: · 3 unmodified lines | ||
| 107 | 123 | - msm |
| 108 | 124 | - rockchip |
| 109 | 125 | - virtio-gpu |
| 110 | − - lint | |
| 126 | + - software-driver | |
| 111 | 127 | |
| 112 | 128 | # YAML anchors for rule conditions |
| 113 | 129 | # -------------------------------- |
| @@ -218,14 +234,15 @@ make git archive: · 104 unmodified lines | ||
| 218 | 234 | script: |
| 219 | 235 | # Remove drm-ci files we just added |
| 220 | 236 | - rm -rf .gitlab-ci.* |
| 237 | + - rm -rf ci | |
| 221 | 238 | |
| 222 | 239 | # Compactify the .git directory |
| 223 | 240 | - git gc --aggressive |
| 224 | 241 | # compress the current folder |
| 225 | 242 | - tar -cvzf ../$CI_PROJECT_NAME.tar.gz . |
| 226 | 243 | |
| 227 | − # login with the JWT token file | |
| 228 | − - ci-fairy s3cp --token-file "${CI_JOB_JWT_FILE}" ../$CI_PROJECT_NAME.tar.gz https://$S3_HOST/git-cache/$CI_PROJECT_NAMESPACE/$CI_PROJECT_NAME/$CI_PROJECT_NAME.tar.gz | |
| 244 | + # Use id_tokens for JWT auth | |
| 245 | + - ci-fairy s3cp --token-file "${S3_JWT_FILE}" ../$CI_PROJECT_NAME.tar.gz https://$S3_HOST/${S3_GITCACHE_BUCKET}/$CI_PROJECT_NAMESPACE/$CI_PROJECT_NAME/$CI_PROJECT_NAME.tar.gz | |
| 229 | 246 | |
| 230 | 247 | |
| 231 | 248 | # Sanity checks of MR settings and commit logs |
| @@ -262,4 +279,4 @@ sanity: · 30 unmodified lines | ||
| 262 | 279 | |
| 263 | 280 | # Jobs that need to pass before spending hardware resources on further testing |
| 264 | 281 | .required-for-hardware-jobs: |
| 265 | − needs: [] | |
| 282 | + needs: [] | |
| @@ -30,10 +30,10 @@ case "$DRIVER_NAME" in · 29 unmodified lines | ||
| 30 | 30 | export IGT_FORCE_DRIVER="panfrost" |
| 31 | 31 | fi |
| 32 | 32 | ;; |
| 33 | − amdgpu) | |
| 33 | + amdgpu|vkms) | |
| 34 | 34 | # Cannot use HWCI_KERNEL_MODULES as at that point we don't have the module in /lib |
| 35 | − mv /install/modules/lib/modules/* /lib/modules/. | |
| 36 | − modprobe amdgpu | |
| 35 | + mv /install/modules/lib/modules/* /lib/modules/. || true | |
| 36 | + modprobe --first-time $DRIVER_NAME | |
| 37 | 37 | ;; |
| 38 | 38 | esac |
| 39 | 39 | |
| @@ -59,25 +59,26 @@ fi · 19 unmodified lines | ||
| 59 | 59 | |
| 60 | 60 | curl -L --retry 4 -f --retry-all-errors --retry-delay 60 -s ${FDO_HTTP_CACHE_URI:-}$PIPELINE_ARTIFACTS_BASE/$ARCH/igt.tar.gz | tar --zstd -v -x -C / |
| 61 | 61 | |
| 62 | +TESTLIST="/igt/libexec/igt-gpu-tools/ci-testlist.txt" | |
| 62 | 63 | |
| 63 | 64 | # If the job is parallel at the gitab job level, take the corresponding fraction |
| 64 | 65 | # of the caselist. |
| 65 | 66 | if [ -n "$CI_NODE_INDEX" ]; then |
| 66 | − sed -ni $CI_NODE_INDEX~$CI_NODE_TOTAL"p" /install/testlist.txt | |
| 67 | + sed -ni $CI_NODE_INDEX~$CI_NODE_TOTAL"p" $TESTLIST | |
| 67 | 68 | fi |
| 68 | 69 | |
| 69 | 70 | # core_getversion checks if the driver is loaded and probed correctly |
| 70 | 71 | # so run it in all shards |
| 71 | −if ! grep -q "core_getversion" /install/testlist.txt; then | |
| 72 | +if ! grep -q "core_getversion" $TESTLIST; then | |
| 72 | 73 | # Add the line to the file |
| 73 | − echo "core_getversion" >> /install/testlist.txt | |
| 74 | + echo "core_getversion" >> $TESTLIST | |
| 74 | 75 | fi |
| 75 | 76 | |
| 76 | 77 | set +e |
| 77 | 78 | igt-runner \ |
| 78 | 79 | run \ |
| 79 | 80 | --igt-folder /igt/libexec/igt-gpu-tools \ |
| 80 | − --caselist /install/testlist.txt \ | |
| 81 | + --caselist $TESTLIST \ | |
| 81 | 82 | --output /results \ |
| 82 | 83 | $IGT_SKIPS \ |
| 83 | 84 | $IGT_FLAKES \ |
| @@ -1,10 +1,10 @@ | ||
| 1 | 1 | variables: |
| 2 | − CONTAINER_TAG: "2023-10-11-mesa-uprev" | |
| 2 | + CONTAINER_TAG: "2024-05-09-mesa-uprev" | |
| 3 | 3 | DEBIAN_X86_64_BUILD_BASE_IMAGE: "debian/x86_64_build-base" |
| 4 | 4 | DEBIAN_BASE_TAG: "${CONTAINER_TAG}" |
| 5 | 5 | |
| 6 | 6 | DEBIAN_X86_64_BUILD_IMAGE_PATH: "debian/x86_64_build" |
| 7 | − DEBIAN_BUILD_TAG: "2023-10-08-config" | |
| 7 | + DEBIAN_BUILD_TAG: "2024-06-10-vkms" | |
| 8 | 8 | |
| 9 | 9 | KERNEL_ROOTFS_TAG: "2023-10-06-amd" |
| 10 | 10 | |
| @@ -27,7 +27,7 @@ KERNEL_IMAGE_BASE="https://${BASE_SYSTEM_HOST_PATH}" \ · 26 unmodified lines | ||
| 27 | 27 | section_end variables |
| 28 | 28 | |
| 29 | 29 | tar zcf job-rootfs-overlay.tar.gz -C results/job-rootfs-overlay/ . |
| 30 | −ci-fairy s3cp --token-file "${CI_JOB_JWT_FILE}" job-rootfs-overlay.tar.gz "https://${JOB_ROOTFS_OVERLAY_PATH}" | |
| 30 | +ci-fairy s3cp --token-file "${S3_JWT_FILE}" job-rootfs-overlay.tar.gz "https://${JOB_ROOTFS_OVERLAY_PATH}" | |
| 31 | 31 | |
| 32 | 32 | touch results/lava.log |
| 33 | 33 | tail -f results/lava.log & |
| @@ -45,7 +45,7 @@ PYTHONPATH=artifacts/ artifacts/lava/lava_job_submitter.py \ · 11 unmodified lines | ||
| 45 | 45 | --ci-project-dir "${CI_PROJECT_DIR}" \ |
| 46 | 46 | --device-type "${DEVICE_TYPE}" \ |
| 47 | 47 | --dtb-filename "${DTB}" \ |
| 48 | − --jwt-file "${CI_JOB_JWT_FILE}" \ | |
| 48 | + --jwt-file "${S3_JWT_FILE}" \ | |
| 49 | 49 | --kernel-image-name "${KERNEL_IMAGE_NAME}" \ |
| 50 | 50 | --kernel-image-type "${KERNEL_IMAGE_TYPE}" \ |
| 51 | 51 | --boot-method "${BOOT_METHOD}" \ |
| @@ -24,6 +24,7 @@ · 23 unmodified lines | ||
| 24 | 24 | variables: |
| 25 | 25 | HWCI_TEST_SCRIPT: "/install/igt_runner.sh" |
| 26 | 26 | DEBIAN_ARCH: "armhf" |
| 27 | + FARM: collabora | |
| 27 | 28 | dependencies: |
| 28 | 29 | - testing:arm32 |
| 29 | 30 | needs: |
| @@ -39,6 +40,7 @@ · 9 unmodified lines | ||
| 39 | 40 | variables: |
| 40 | 41 | HWCI_TEST_SCRIPT: "/install/igt_runner.sh" |
| 41 | 42 | DEBIAN_ARCH: "arm64" |
| 43 | + FARM: collabora | |
| 42 | 44 | dependencies: |
| 43 | 45 | - testing:arm64 |
| 44 | 46 | needs: |
| @@ -54,6 +56,7 @@ · 9 unmodified lines | ||
| 54 | 56 | variables: |
| 55 | 57 | HWCI_TEST_SCRIPT: "/install/igt_runner.sh" |
| 56 | 58 | DEBIAN_ARCH: "amd64" |
| 59 | + FARM: collabora | |
| 57 | 60 | dependencies: |
| 58 | 61 | - testing:x86_64 |
| 59 | 62 | needs: |
| @@ -74,6 +77,7 @@ · 14 unmodified lines | ||
| 74 | 77 | S3_ARTIFACT_NAME: "arm64/kernel-files" |
| 75 | 78 | BM_KERNEL: https://${PIPELINE_ARTIFACTS_BASE}/arm64/Image.gz |
| 76 | 79 | BM_CMDLINE: "ip=dhcp console=ttyMSM0,115200n8 $BM_KERNEL_EXTRA_ARGS root=/dev/nfs rw nfsrootdebug nfsroot=,tcp,nfsvers=4.2 init=/init $BM_KERNELARGS" |
| 80 | + FARM: google | |
| 77 | 81 | needs: |
| 78 | 82 | - debian/arm64_test |
| 79 | 83 | - job: testing:arm64 |
| @@ -116,8 +120,9 @@ msm:apq8016: · 36 unmodified lines | ||
| 116 | 120 | - .baremetal-igt-arm64 |
| 117 | 121 | stage: msm |
| 118 | 122 | variables: |
| 123 | + DEVICE_TYPE: apq8016-sbc-usb-host | |
| 119 | 124 | DRIVER_NAME: msm |
| 120 | − BM_DTB: https://${PIPELINE_ARTIFACTS_BASE}/arm64/apq8016-sbc-usb-host.dtb | |
| 125 | + BM_DTB: https://${PIPELINE_ARTIFACTS_BASE}/arm64/${DEVICE_TYPE}.dtb | |
| 121 | 126 | GPU_VERSION: apq8016 |
| 122 | 127 | # disabling unused clocks congests with the MDSS runtime PM trying to |
| 123 | 128 | # disable those clocks and causes boot to fail. |
| @@ -132,9 +137,10 @@ msm:apq8096: · 8 unmodified lines | ||
| 132 | 137 | - .baremetal-igt-arm64 |
| 133 | 138 | stage: msm |
| 134 | 139 | variables: |
| 140 | + DEVICE_TYPE: apq8096-db820c | |
| 135 | 141 | DRIVER_NAME: msm |
| 136 | 142 | BM_KERNEL_EXTRA_ARGS: maxcpus=2 |
| 137 | − BM_DTB: https://${PIPELINE_ARTIFACTS_BASE}/arm64/apq8096-db820c.dtb | |
| 143 | + BM_DTB: https://${PIPELINE_ARTIFACTS_BASE}/arm64/${DEVICE_TYPE}.dtb | |
| 138 | 144 | GPU_VERSION: apq8096 |
| 139 | 145 | RUNNER_TAG: google-freedreno-db820c |
| 140 | 146 | script: |
| @@ -146,6 +152,7 @@ msm:sdm845: · 5 unmodified lines | ||
| 146 | 152 | stage: msm |
| 147 | 153 | parallel: 6 |
| 148 | 154 | variables: |
| 155 | + DEVICE_TYPE: sdm845-cheza-r3 | |
| 149 | 156 | DRIVER_NAME: msm |
| 150 | 157 | BM_KERNEL: https://${PIPELINE_ARTIFACTS_BASE}/arm64/cheza-kernel |
| 151 | 158 | GPU_VERSION: sdm845 |
| @@ -184,6 +191,7 @@ rockchip:rk3399: · 32 unmodified lines | ||
| 184 | 191 | extends: |
| 185 | 192 | - .lava-igt:x86_64 |
| 186 | 193 | stage: i915 |
| 194 | + timeout: "1h30m" | |
| 187 | 195 | variables: |
| 188 | 196 | DRIVER_NAME: i915 |
| 189 | 197 | DTB: "" |
| @@ -194,7 +202,6 @@ i915:apl: · 4 unmodified lines | ||
| 194 | 202 | extends: |
| 195 | 203 | - .i915 |
| 196 | 204 | parallel: 3 |
| 197 | − timeout: "1h30m" | |
| 198 | 205 | variables: |
| 199 | 206 | DEVICE_TYPE: asus-C523NA-A20057-coral |
| 200 | 207 | GPU_VERSION: apl |
| @@ -204,7 +211,6 @@ i915:glk: · 3 unmodified lines | ||
| 204 | 211 | extends: |
| 205 | 212 | - .i915 |
| 206 | 213 | parallel: 2 |
| 207 | − timeout: "1h30m" | |
| 208 | 214 | variables: |
| 209 | 215 | DEVICE_TYPE: hp-x360-12b-ca0010nr-n4020-octopus |
| 210 | 216 | GPU_VERSION: glk |
| @@ -214,7 +220,6 @@ i915:amly: · 3 unmodified lines | ||
| 214 | 220 | extends: |
| 215 | 221 | - .i915 |
| 216 | 222 | parallel: 2 |
| 217 | − timeout: "1h30m" | |
| 218 | 223 | variables: |
| 219 | 224 | DEVICE_TYPE: asus-C433TA-AJ0005-rammus |
| 220 | 225 | GPU_VERSION: amly |
| @@ -233,7 +238,6 @@ i915:whl: · 12 unmodified lines | ||
| 233 | 238 | extends: |
| 234 | 239 | - .i915 |
| 235 | 240 | parallel: 2 |
| 236 | − timeout: "1h30m" | |
| 237 | 241 | variables: |
| 238 | 242 | DEVICE_TYPE: dell-latitude-5400-8665U-sarien |
| 239 | 243 | GPU_VERSION: whl |
| @@ -243,7 +247,6 @@ i915:cml: · 3 unmodified lines | ||
| 243 | 247 | extends: |
| 244 | 248 | - .i915 |
| 245 | 249 | parallel: 2 |
| 246 | − timeout: "1h30m" | |
| 247 | 250 | variables: |
| 248 | 251 | DEVICE_TYPE: asus-C436FA-Flip-hatch |
| 249 | 252 | GPU_VERSION: cml |
| @@ -335,7 +338,7 @@ meson:g12b: · 85 unmodified lines | ||
| 335 | 338 | RUNNER_TAG: mesa-ci-x86-64-lava-meson-g12b-a311d-khadas-vim3 |
| 336 | 339 | |
| 337 | 340 | virtio_gpu:none: |
| 338 | − stage: virtio-gpu | |
| 341 | + stage: software-driver | |
| 339 | 342 | variables: |
| 340 | 343 | CROSVM_GALLIUM_DRIVER: llvmpipe |
| 341 | 344 | DRIVER_NAME: virtio_gpu |
| @@ -355,3 +358,25 @@ virtio_gpu:none: · 13 unmodified lines | ||
| 355 | 358 | - debian/x86_64_test-gl |
| 356 | 359 | - testing:x86_64 |
| 357 | 360 | - igt:x86_64 |
| 361 | + | |
| 362 | +vkms:none: | |
| 363 | + stage: software-driver | |
| 364 | + variables: | |
| 365 | + DRIVER_NAME: vkms | |
| 366 | + GPU_VERSION: none | |
| 367 | + extends: | |
| 368 | + - .test-gl | |
| 369 | + - .test-rules | |
| 370 | + tags: | |
| 371 | + - kvm | |
| 372 | + script: | |
| 373 | + - ln -sf $CI_PROJECT_DIR/install /install | |
| 374 | + - mv install/bzImage /lava-files/bzImage | |
| 375 | + - mkdir -p /lib/modules | |
| 376 | + - mkdir -p $CI_PROJECT_DIR/results | |
| 377 | + - ln -sf $CI_PROJECT_DIR/results /results | |
| 378 | + - ./install/crosvm-runner.sh ./install/igt_runner.sh | |
| 379 | + needs: | |
| 380 | + - debian/x86_64_test-gl | |
| 381 | + - testing:x86_64 | |
| 382 | + - igt:x86_64 | |
| @@ -1,2761 +0,0 @@ | ||
| 1 | −core_auth@getclient-simple | |
| 2 | −core_auth@getclient-master-drop | |
| 3 | −core_auth@basic-auth | |
| 4 | −core_auth@many-magics | |
| 5 | −core_getclient | |
| 6 | −core_getstats | |
| 7 | −core_getversion | |
| 8 | −core_setmaster_vs_auth | |
| 9 | −drm_read@invalid-buffer | |
| 10 | −drm_read@fault-buffer | |
| 11 | −drm_read@empty-block | |
| 12 | −drm_read@empty-nonblock | |
| 13 | −drm_read@short-buffer-block | |
| 14 | −drm_read@short-buffer-nonblock | |
| 15 | −drm_read@short-buffer-wakeup | |
| 16 | −gem_eio@throttle | |
| 17 | −gem_eio@create | |
| 18 | −gem_eio@create-ext | |
| 19 | −gem_eio@context-create | |
| 20 | −gem_eio@execbuf | |
| 21 | −gem_eio@banned | |
| 22 | −gem_eio@suspend | |
| 23 | −gem_eio@hibernate | |
| 24 | −gem_eio@in-flight-external | |
| 25 | −gem_eio@in-flight-suspend | |
| 26 | −gem_eio@reset-stress | |
| 27 | −gem_eio@unwedge-stress | |
| 28 | −gem_eio@wait-immediate | |
| 29 | −gem_eio@wait-wedge-immediate | |
| 30 | −gem_eio@in-flight-immediate | |
| 31 | −gem_eio@in-flight-contexts-immediate | |
| 32 | −gem_eio@in-flight-internal-immediate | |
| 33 | −gem_eio@wait-1us | |
| 34 | −gem_eio@wait-wedge-1us | |
| 35 | −gem_eio@in-flight-1us | |
| 36 | −gem_eio@in-flight-contexts-1us | |
| 37 | −gem_eio@in-flight-internal-1us | |
| 38 | −gem_eio@wait-10ms | |
| 39 | −gem_eio@wait-wedge-10ms | |
| 40 | −gem_eio@in-flight-10ms | |
| 41 | −gem_eio@in-flight-contexts-10ms | |
| 42 | −gem_eio@in-flight-internal-10ms | |
| 43 | −gem_eio@kms | |
| 44 | −kms_3d | |
| 45 | −kms_addfb_basic@unused-handle | |
| 46 | −kms_addfb_basic@unused-pitches | |
| 47 | −kms_addfb_basic@unused-offsets | |
| 48 | −kms_addfb_basic@unused-modifier | |
| 49 | −kms_addfb_basic@clobberred-modifier | |
| 50 | −kms_addfb_basic@invalid-smem-bo-on-discrete | |
| 51 | −kms_addfb_basic@legacy-format | |
| 52 | −kms_addfb_basic@no-handle | |
| 53 | −kms_addfb_basic@basic | |
| 54 | −kms_addfb_basic@bad-pitch-0 | |
| 55 | −kms_addfb_basic@bad-pitch-32 | |
| 56 | −kms_addfb_basic@bad-pitch-63 | |
| 57 | −kms_addfb_basic@bad-pitch-128 | |
| 58 | −kms_addfb_basic@bad-pitch-256 | |
| 59 | −kms_addfb_basic@bad-pitch-1024 | |
| 60 | −kms_addfb_basic@bad-pitch-999 | |
| 61 | −kms_addfb_basic@bad-pitch-65536 | |
| 62 | −kms_addfb_basic@invalid-get-prop-any | |
| 63 | −kms_addfb_basic@invalid-get-prop | |
| 64 | −kms_addfb_basic@invalid-set-prop-any | |
| 65 | −kms_addfb_basic@invalid-set-prop | |
| 66 | −kms_addfb_basic@master-rmfb | |
| 67 | −kms_addfb_basic@addfb25-modifier-no-flag | |
| 68 | −kms_addfb_basic@addfb25-bad-modifier | |
| 69 | −kms_addfb_basic@addfb25-x-tiled-mismatch-legacy | |
| 70 | −kms_addfb_basic@addfb25-x-tiled-legacy | |
| 71 | −kms_addfb_basic@addfb25-framebuffer-vs-set-tiling | |
| 72 | −kms_addfb_basic@basic-x-tiled-legacy | |
| 73 | −kms_addfb_basic@framebuffer-vs-set-tiling | |
| 74 | −kms_addfb_basic@tile-pitch-mismatch | |
| 75 | −kms_addfb_basic@basic-y-tiled-legacy | |
| 76 | −kms_addfb_basic@size-max | |
| 77 | −kms_addfb_basic@too-wide | |
| 78 | −kms_addfb_basic@too-high | |
| 79 | −kms_addfb_basic@bo-too-small | |
| 80 | −kms_addfb_basic@small-bo | |
| 81 | −kms_addfb_basic@bo-too-small-due-to-tiling | |
| 82 | −kms_addfb_basic@addfb25-y-tiled-legacy | |
| 83 | −kms_addfb_basic@addfb25-yf-tiled-legacy | |
| 84 | −kms_addfb_basic@addfb25-y-tiled-small-legacy | |
| 85 | −kms_addfb_basic@addfb25-4-tiled | |
| 86 | −kms_async_flips@async-flip-with-page-flip-events | |
| 87 | −kms_async_flips@alternate-sync-async-flip | |
| 88 | −kms_async_flips@test-time-stamp | |
| 89 | −kms_async_flips@test-cursor | |
| 90 | −kms_async_flips@invalid-async-flip | |
| 91 | −kms_async_flips@crc | |
| 92 | −kms_atomic@plane-overlay-legacy | |
| 93 | −kms_atomic@plane-primary-legacy | |
| 94 | −kms_atomic@plane-primary-overlay-mutable-zpos | |
| 95 | −kms_atomic@plane-immutable-zpos | |
| 96 | −kms_atomic@test-only | |
| 97 | −kms_atomic@plane-cursor-legacy | |
| 98 | −kms_atomic@plane-invalid-params | |
| 99 | −kms_atomic@plane-invalid-params-fence | |
| 100 | −kms_atomic@crtc-invalid-params | |
| 101 | −kms_atomic@crtc-invalid-params-fence | |
| 102 | −kms_atomic@atomic-invalid-params | |
| 103 | −kms_atomic@atomic-plane-damage | |
| 104 | −kms_atomic_interruptible@legacy-setmode | |
| 105 | −kms_atomic_interruptible@atomic-setmode | |
| 106 | −kms_atomic_interruptible@legacy-dpms | |
| 107 | −kms_atomic_interruptible@legacy-pageflip | |
| 108 | −kms_atomic_interruptible@legacy-cursor | |
| 109 | −kms_atomic_interruptible@universal-setplane-primary | |
| 110 | −kms_atomic_interruptible@universal-setplane-cursor | |
| 111 | −kms_atomic_transition@plane-primary-toggle-with-vblank-wait | |
| 112 | −kms_atomic_transition@plane-all-transition | |
| 113 | −kms_atomic_transition@plane-all-transition-fencing | |
| 114 | −kms_atomic_transition@plane-all-transition-nonblocking | |
| 115 | −kms_atomic_transition@plane-all-transition-nonblocking-fencing | |
| 116 | −kms_atomic_transition@plane-use-after-nonblocking-unbind | |
| 117 | −kms_atomic_transition@plane-use-after-nonblocking-unbind-fencing | |
| 118 | −kms_atomic_transition@plane-all-modeset-transition | |
| 119 | −kms_atomic_transition@plane-all-modeset-transition-fencing | |
| 120 | −kms_atomic_transition@plane-all-modeset-transition-internal-panels | |
| 121 | −kms_atomic_transition@plane-all-modeset-transition-fencing-internal-panels | |
| 122 | −kms_atomic_transition@plane-toggle-modeset-transition | |
| 123 | −kms_atomic_transition@modeset-transition | |
| 124 | −kms_atomic_transition@modeset-transition-fencing | |
| 125 | −kms_atomic_transition@modeset-transition-nonblocking | |
| 126 | −kms_atomic_transition@modeset-transition-nonblocking-fencing | |
| 127 | −kms_big_fb@x-tiled-addfb-size-overflow | |
| 128 | −kms_big_fb@y-tiled-addfb-size-overflow | |
| 129 | −kms_big_fb@yf-tiled-addfb-size-overflow | |
| 130 | −kms_big_fb@4-tiled-addfb-size-overflow | |
| 131 | −kms_big_fb@x-tiled-addfb-size-offset-overflow | |
| 132 | −kms_big_fb@y-tiled-addfb-size-offset-overflow | |
| 133 | −kms_big_fb@yf-tiled-addfb-size-offset-overflow | |
| 134 | −kms_big_fb@4-tiled-addfb-size-offset-overflow | |
| 135 | −kms_big_fb@linear-addfb | |
| 136 | −kms_big_fb@x-tiled-addfb | |
| 137 | −kms_big_fb@y-tiled-addfb | |
| 138 | −kms_big_fb@yf-tiled-addfb | |
| 139 | −kms_big_fb@4-tiled-addfb | |
| 140 | −kms_big_fb@linear-8bpp-rotate-0 | |
| 141 | −kms_big_fb@linear-8bpp-rotate-90 | |
| 142 | −kms_big_fb@linear-8bpp-rotate-180 | |
| 143 | −kms_big_fb@linear-8bpp-rotate-270 | |
| 144 | −kms_big_fb@linear-16bpp-rotate-0 | |
| 145 | −kms_big_fb@linear-16bpp-rotate-90 | |
| 146 | −kms_big_fb@linear-16bpp-rotate-180 | |
| 147 | −kms_big_fb@linear-16bpp-rotate-270 | |
| 148 | −kms_big_fb@linear-32bpp-rotate-0 | |
| 149 | −kms_big_fb@linear-32bpp-rotate-90 | |
| 150 | −kms_big_fb@linear-32bpp-rotate-180 | |
| 151 | −kms_big_fb@linear-32bpp-rotate-270 | |
| 152 | −kms_big_fb@linear-64bpp-rotate-0 | |
| 153 | −kms_big_fb@linear-64bpp-rotate-90 | |
| 154 | −kms_big_fb@linear-64bpp-rotate-180 | |
| 155 | −kms_big_fb@linear-64bpp-rotate-270 | |
| 156 | −kms_big_fb@x-tiled-8bpp-rotate-0 | |
| 157 | −kms_big_fb@x-tiled-8bpp-rotate-90 | |
| 158 | −kms_big_fb@x-tiled-8bpp-rotate-180 | |
| 159 | −kms_big_fb@x-tiled-8bpp-rotate-270 | |
| 160 | −kms_big_fb@x-tiled-16bpp-rotate-0 | |
| 161 | −kms_big_fb@x-tiled-16bpp-rotate-90 | |
| 162 | −kms_big_fb@x-tiled-16bpp-rotate-180 | |
| 163 | −kms_big_fb@x-tiled-16bpp-rotate-270 | |
| 164 | −kms_big_fb@x-tiled-32bpp-rotate-0 | |
| 165 | −kms_big_fb@x-tiled-32bpp-rotate-90 | |
| 166 | −kms_big_fb@x-tiled-32bpp-rotate-180 | |
| 167 | −kms_big_fb@x-tiled-32bpp-rotate-270 | |
| 168 | −kms_big_fb@x-tiled-64bpp-rotate-0 | |
| 169 | −kms_big_fb@x-tiled-64bpp-rotate-90 | |
| 170 | −kms_big_fb@x-tiled-64bpp-rotate-180 | |
| 171 | −kms_big_fb@x-tiled-64bpp-rotate-270 | |
| 172 | −kms_big_fb@y-tiled-8bpp-rotate-0 | |
| 173 | −kms_big_fb@y-tiled-8bpp-rotate-90 | |
| 174 | −kms_big_fb@y-tiled-8bpp-rotate-180 | |
| 175 | −kms_big_fb@y-tiled-8bpp-rotate-270 | |
| 176 | −kms_big_fb@y-tiled-16bpp-rotate-0 | |
| 177 | −kms_big_fb@y-tiled-16bpp-rotate-90 | |
| 178 | −kms_big_fb@y-tiled-16bpp-rotate-180 | |
| 179 | −kms_big_fb@y-tiled-16bpp-rotate-270 | |
| 180 | −kms_big_fb@y-tiled-32bpp-rotate-0 | |
| 181 | −kms_big_fb@y-tiled-32bpp-rotate-90 | |
| 182 | −kms_big_fb@y-tiled-32bpp-rotate-180 | |
| 183 | −kms_big_fb@y-tiled-32bpp-rotate-270 | |
| 184 | −kms_big_fb@y-tiled-64bpp-rotate-0 | |
| 185 | −kms_big_fb@y-tiled-64bpp-rotate-90 | |
| 186 | −kms_big_fb@y-tiled-64bpp-rotate-180 | |
| 187 | −kms_big_fb@y-tiled-64bpp-rotate-270 | |
| 188 | −kms_big_fb@yf-tiled-8bpp-rotate-0 | |
| 189 | −kms_big_fb@yf-tiled-8bpp-rotate-90 | |
| 190 | −kms_big_fb@yf-tiled-8bpp-rotate-180 | |
| 191 | −kms_big_fb@yf-tiled-8bpp-rotate-270 | |
| 192 | −kms_big_fb@yf-tiled-16bpp-rotate-0 | |
| 193 | −kms_big_fb@yf-tiled-16bpp-rotate-90 | |
| 194 | −kms_big_fb@yf-tiled-16bpp-rotate-180 | |
| 195 | −kms_big_fb@yf-tiled-16bpp-rotate-270 | |
| 196 | −kms_big_fb@yf-tiled-32bpp-rotate-0 | |
| 197 | −kms_big_fb@yf-tiled-32bpp-rotate-90 | |
| 198 | −kms_big_fb@yf-tiled-32bpp-rotate-180 | |
| 199 | −kms_big_fb@yf-tiled-32bpp-rotate-270 | |
| 200 | −kms_big_fb@yf-tiled-64bpp-rotate-0 | |
| 201 | −kms_big_fb@yf-tiled-64bpp-rotate-90 | |
| 202 | −kms_big_fb@yf-tiled-64bpp-rotate-180 | |
| 203 | −kms_big_fb@yf-tiled-64bpp-rotate-270 | |
| 204 | −kms_big_fb@4-tiled-8bpp-rotate-0 | |
| 205 | −kms_big_fb@4-tiled-8bpp-rotate-90 | |
| 206 | −kms_big_fb@4-tiled-8bpp-rotate-180 | |
| 207 | −kms_big_fb@4-tiled-8bpp-rotate-270 | |
| 208 | −kms_big_fb@4-tiled-16bpp-rotate-0 | |
| 209 | −kms_big_fb@4-tiled-16bpp-rotate-90 | |
| 210 | −kms_big_fb@4-tiled-16bpp-rotate-180 | |
| 211 | −kms_big_fb@4-tiled-16bpp-rotate-270 | |
| 212 | −kms_big_fb@4-tiled-32bpp-rotate-0 | |
| 213 | −kms_big_fb@4-tiled-32bpp-rotate-90 | |
| 214 | −kms_big_fb@4-tiled-32bpp-rotate-180 | |
| 215 | −kms_big_fb@4-tiled-32bpp-rotate-270 | |
| 216 | −kms_big_fb@4-tiled-64bpp-rotate-0 | |
| 217 | −kms_big_fb@4-tiled-64bpp-rotate-90 | |
| 218 | −kms_big_fb@4-tiled-64bpp-rotate-180 | |
| 219 | −kms_big_fb@4-tiled-64bpp-rotate-270 | |
| 220 | −kms_big_fb@linear-max-hw-stride-32bpp-rotate-0 | |
| 221 | −kms_big_fb@linear-max-hw-stride-32bpp-rotate-180 | |
| 222 | −kms_big_fb@linear-max-hw-stride-64bpp-rotate-0 | |
| 223 | −kms_big_fb@linear-max-hw-stride-64bpp-rotate-180 | |
| 224 | −kms_big_fb@x-tiled-max-hw-stride-32bpp-rotate-0 | |
| 225 | −kms_big_fb@x-tiled-max-hw-stride-32bpp-rotate-0-async-flip | |
| 226 | −kms_big_fb@x-tiled-max-hw-stride-32bpp-rotate-180 | |
| 227 | −kms_big_fb@x-tiled-max-hw-stride-32bpp-rotate-180-async-flip | |
| 228 | −kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-0 | |
| 229 | −kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-0-async-flip | |
| 230 | −kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-180 | |
| 231 | −kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-180-async-flip | |
| 232 | −kms_big_fb@x-tiled-max-hw-stride-32bpp-rotate-0-hflip | |
| 233 | −kms_big_fb@x-tiled-max-hw-stride-32bpp-rotate-0-hflip-async-flip | |
| 234 | −kms_big_fb@x-tiled-max-hw-stride-32bpp-rotate-180-hflip | |
| 235 | −kms_big_fb@x-tiled-max-hw-stride-32bpp-rotate-180-hflip-async-flip | |
| 236 | −kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-0-hflip | |
| 237 | −kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-0-hflip-async-flip | |
| 238 | −kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-180-hflip | |
| 239 | −kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-180-hflip-async-flip | |
| 240 | −kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-0 | |
| 241 | −kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-0-async-flip | |
| 242 | −kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-180 | |
| 243 | −kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-180-async-flip | |
| 244 | −kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-0 | |
| 245 | −kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-0-async-flip | |
| 246 | −kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-180 | |
| 247 | −kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-180-async-flip | |
| 248 | −kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-0-hflip | |
| 249 | −kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-0-hflip-async-flip | |
| 250 | −kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-180-hflip | |
| 251 | −kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-180-hflip-async-flip | |
| 252 | −kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-0-hflip | |
| 253 | −kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-0-hflip-async-flip | |
| 254 | −kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-180-hflip | |
| 255 | −kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-180-hflip-async-flip | |
| 256 | −kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-0 | |
| 257 | −kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-0-async-flip | |
| 258 | −kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-180 | |
| 259 | −kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-180-async-flip | |
| 260 | −kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-0 | |
| 261 | −kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-0-async-flip | |
| 262 | −kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-180 | |
| 263 | −kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-180-async-flip | |
| 264 | −kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-0-hflip | |
| 265 | −kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-0-hflip-async-flip | |
| 266 | −kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-180-hflip | |
| 267 | −kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-180-hflip-async-flip | |
| 268 | −kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-0-hflip | |
| 269 | −kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-0-hflip-async-flip | |
| 270 | −kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-180-hflip | |
| 271 | −kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-180-hflip-async-flip | |
| 272 | −kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-0 | |
| 273 | −kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-0-async-flip | |
| 274 | −kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-180 | |
| 275 | −kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-180-async-flip | |
| 276 | −kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-0 | |
| 277 | −kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-0-async-flip | |
| 278 | −kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-180 | |
| 279 | −kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-180-async-flip | |
| 280 | −kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-0-hflip | |
| 281 | −kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-0-hflip-async-flip | |
| 282 | −kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-180-hflip | |
| 283 | −kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-180-hflip-async-flip | |
| 284 | −kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-0-hflip | |
| 285 | −kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-0-hflip-async-flip | |
| 286 | −kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-180-hflip | |
| 287 | −kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-180-hflip-async-flip | |
| 288 | −kms_big_joiner@basic | |
| 289 | −kms_big_joiner@invalid-modeset | |
| 290 | −kms_big_joiner@2x-modeset | |
| 291 | −kms_busy@basic | |
| 292 | −kms_busy@basic-hang | |
| 293 | −kms_busy@extended-pageflip-modeset-hang-oldfb | |
| 294 | −kms_busy@extended-pageflip-hang-oldfb | |
| 295 | −kms_busy@extended-pageflip-hang-newfb | |
| 296 | −kms_busy@extended-modeset-hang-oldfb | |
| 297 | −kms_busy@extended-modeset-hang-newfb | |
| 298 | −kms_busy@extended-modeset-hang-oldfb-with-reset | |
| 299 | −kms_busy@extended-modeset-hang-newfb-with-reset | |
| 300 | −kms_bw@linear-tiling-1-displays-1920x1080p | |
| 301 | −kms_bw@linear-tiling-1-displays-2560x1440p | |
| 302 | −kms_bw@linear-tiling-1-displays-3840x2160p | |
| 303 | −kms_bw@linear-tiling-2-displays-1920x1080p | |
| 304 | −kms_bw@linear-tiling-2-displays-2560x1440p | |
| 305 | −kms_bw@linear-tiling-2-displays-3840x2160p | |
| 306 | −kms_bw@linear-tiling-3-displays-1920x1080p | |
| 307 | −kms_bw@linear-tiling-3-displays-2560x1440p | |
| 308 | −kms_bw@linear-tiling-3-displays-3840x2160p | |
| 309 | −kms_bw@linear-tiling-4-displays-1920x1080p | |
| 310 | −kms_bw@linear-tiling-4-displays-2560x1440p | |
| 311 | −kms_bw@linear-tiling-4-displays-3840x2160p | |
| 312 | −kms_bw@linear-tiling-5-displays-1920x1080p | |
| 313 | −kms_bw@linear-tiling-5-displays-2560x1440p | |
| 314 | −kms_bw@linear-tiling-5-displays-3840x2160p | |
| 315 | −kms_bw@linear-tiling-6-displays-1920x1080p | |
| 316 | −kms_bw@linear-tiling-6-displays-2560x1440p | |
| 317 | −kms_bw@linear-tiling-6-displays-3840x2160p | |
| 318 | −kms_bw@linear-tiling-7-displays-1920x1080p | |
| 319 | −kms_bw@linear-tiling-7-displays-2560x1440p | |
| 320 | −kms_bw@linear-tiling-7-displays-3840x2160p | |
| 321 | −kms_bw@linear-tiling-8-displays-1920x1080p | |
| 322 | −kms_bw@linear-tiling-8-displays-2560x1440p | |
| 323 | −kms_bw@linear-tiling-8-displays-3840x2160p | |
| 324 | −kms_ccs@pipe-A-bad-pixel-format-y-tiled-ccs | |
| 325 | −kms_ccs@pipe-A-bad-pixel-format-yf-tiled-ccs | |
| 326 | −kms_ccs@pipe-A-bad-pixel-format-y-tiled-gen12-rc-ccs | |
| 327 | −kms_ccs@pipe-A-bad-pixel-format-y-tiled-gen12-rc-ccs-cc | |
| 328 | −kms_ccs@pipe-A-bad-pixel-format-y-tiled-gen12-mc-ccs | |
| 329 | −kms_ccs@pipe-A-bad-pixel-format-4-tiled-dg2-rc-ccs | |
| 330 | −kms_ccs@pipe-A-bad-pixel-format-4-tiled-dg2-mc-ccs | |
| 331 | −kms_ccs@pipe-A-bad-pixel-format-4-tiled-dg2-rc-ccs-cc | |
| 332 | −kms_ccs@pipe-A-bad-pixel-format-4-tiled-mtl-rc-ccs | |
| 333 | −kms_ccs@pipe-A-bad-pixel-format-4-tiled-mtl-mc-ccs | |
| 334 | −kms_ccs@pipe-A-bad-pixel-format-4-tiled-mtl-rc-ccs-cc | |
| 335 | −kms_ccs@pipe-A-bad-rotation-90-y-tiled-ccs | |
| 336 | −kms_ccs@pipe-A-bad-rotation-90-yf-tiled-ccs | |
| 337 | −kms_ccs@pipe-A-bad-rotation-90-y-tiled-gen12-rc-ccs | |
| 338 | −kms_ccs@pipe-A-bad-rotation-90-y-tiled-gen12-rc-ccs-cc | |
| 339 | −kms_ccs@pipe-A-bad-rotation-90-y-tiled-gen12-mc-ccs | |
| 340 | −kms_ccs@pipe-A-bad-rotation-90-4-tiled-dg2-rc-ccs | |
| 341 | −kms_ccs@pipe-A-bad-rotation-90-4-tiled-dg2-mc-ccs | |
| 342 | −kms_ccs@pipe-A-bad-rotation-90-4-tiled-dg2-rc-ccs-cc | |
| 343 | −kms_ccs@pipe-A-bad-rotation-90-4-tiled-mtl-rc-ccs | |
| 344 | −kms_ccs@pipe-A-bad-rotation-90-4-tiled-mtl-mc-ccs | |
| 345 | −kms_ccs@pipe-A-bad-rotation-90-4-tiled-mtl-rc-ccs-cc | |
| 346 | −kms_ccs@pipe-A-crc-primary-basic-y-tiled-ccs | |
| 347 | −kms_ccs@pipe-A-crc-primary-basic-yf-tiled-ccs | |
| 348 | −kms_ccs@pipe-A-crc-primary-basic-y-tiled-gen12-rc-ccs | |
| 349 | −kms_ccs@pipe-A-crc-primary-basic-y-tiled-gen12-rc-ccs-cc | |
| 350 | −kms_ccs@pipe-A-crc-primary-basic-y-tiled-gen12-mc-ccs | |
| 351 | −kms_ccs@pipe-A-crc-primary-basic-4-tiled-dg2-rc-ccs | |
| 352 | −kms_ccs@pipe-A-crc-primary-basic-4-tiled-dg2-mc-ccs | |
| 353 | −kms_ccs@pipe-A-crc-primary-basic-4-tiled-dg2-rc-ccs-cc | |
| 354 | −kms_ccs@pipe-A-crc-primary-basic-4-tiled-mtl-rc-ccs | |
| 355 | −kms_ccs@pipe-A-crc-primary-basic-4-tiled-mtl-mc-ccs | |
| 356 | −kms_ccs@pipe-A-crc-primary-basic-4-tiled-mtl-rc-ccs-cc | |
| 357 | −kms_ccs@pipe-A-crc-primary-rotation-180-y-tiled-ccs | |
| 358 | −kms_ccs@pipe-A-crc-primary-rotation-180-yf-tiled-ccs | |
| 359 | −kms_ccs@pipe-A-crc-primary-rotation-180-y-tiled-gen12-rc-ccs | |
| 360 | −kms_ccs@pipe-A-crc-primary-rotation-180-y-tiled-gen12-rc-ccs-cc | |
| 361 | −kms_ccs@pipe-A-crc-primary-rotation-180-y-tiled-gen12-mc-ccs | |
| 362 | −kms_ccs@pipe-A-crc-primary-rotation-180-4-tiled-dg2-rc-ccs | |
| 363 | −kms_ccs@pipe-A-crc-primary-rotation-180-4-tiled-dg2-mc-ccs | |
| 364 | −kms_ccs@pipe-A-crc-primary-rotation-180-4-tiled-dg2-rc-ccs-cc | |
| 365 | −kms_ccs@pipe-A-crc-primary-rotation-180-4-tiled-mtl-rc-ccs | |
| 366 | −kms_ccs@pipe-A-crc-primary-rotation-180-4-tiled-mtl-mc-ccs | |
| 367 | −kms_ccs@pipe-A-crc-primary-rotation-180-4-tiled-mtl-rc-ccs-cc | |
| 368 | −kms_ccs@pipe-A-random-ccs-data-y-tiled-ccs | |
| 369 | −kms_ccs@pipe-A-random-ccs-data-yf-tiled-ccs | |
| 370 | −kms_ccs@pipe-A-random-ccs-data-y-tiled-gen12-rc-ccs | |
| 371 | −kms_ccs@pipe-A-random-ccs-data-y-tiled-gen12-rc-ccs-cc | |
| 372 | −kms_ccs@pipe-A-random-ccs-data-y-tiled-gen12-mc-ccs | |
| 373 | −kms_ccs@pipe-A-random-ccs-data-4-tiled-dg2-rc-ccs | |
| 374 | −kms_ccs@pipe-A-random-ccs-data-4-tiled-dg2-mc-ccs | |
| 375 | −kms_ccs@pipe-A-random-ccs-data-4-tiled-dg2-rc-ccs-cc | |
| 376 | −kms_ccs@pipe-A-random-ccs-data-4-tiled-mtl-rc-ccs | |
| 377 | −kms_ccs@pipe-A-random-ccs-data-4-tiled-mtl-mc-ccs | |
| 378 | −kms_ccs@pipe-A-random-ccs-data-4-tiled-mtl-rc-ccs-cc | |
| 379 | −kms_ccs@pipe-A-missing-ccs-buffer-y-tiled-ccs | |
| 380 | −kms_ccs@pipe-A-missing-ccs-buffer-yf-tiled-ccs | |
| 381 | −kms_ccs@pipe-A-missing-ccs-buffer-y-tiled-gen12-rc-ccs | |
| 382 | −kms_ccs@pipe-A-missing-ccs-buffer-y-tiled-gen12-rc-ccs-cc | |
| 383 | −kms_ccs@pipe-A-missing-ccs-buffer-y-tiled-gen12-mc-ccs | |
| 384 | −kms_ccs@pipe-A-missing-ccs-buffer-4-tiled-mtl-rc-ccs | |
| 385 | −kms_ccs@pipe-A-missing-ccs-buffer-4-tiled-mtl-mc-ccs | |
| 386 | −kms_ccs@pipe-A-missing-ccs-buffer-4-tiled-mtl-rc-ccs-cc | |
| 387 | −kms_ccs@pipe-A-ccs-on-another-bo-y-tiled-ccs | |
| 388 | −kms_ccs@pipe-A-ccs-on-another-bo-yf-tiled-ccs | |
| 389 | −kms_ccs@pipe-A-ccs-on-another-bo-y-tiled-gen12-rc-ccs | |
| 390 | −kms_ccs@pipe-A-ccs-on-another-bo-y-tiled-gen12-rc-ccs-cc | |
| 391 | −kms_ccs@pipe-A-ccs-on-another-bo-y-tiled-gen12-mc-ccs | |
| 392 | −kms_ccs@pipe-A-ccs-on-another-bo-4-tiled-mtl-rc-ccs | |
| 393 | −kms_ccs@pipe-A-ccs-on-another-bo-4-tiled-mtl-mc-ccs | |
| 394 | −kms_ccs@pipe-A-ccs-on-another-bo-4-tiled-mtl-rc-ccs-cc | |
| 395 | −kms_ccs@pipe-A-bad-aux-stride-y-tiled-ccs | |
| 396 | −kms_ccs@pipe-A-bad-aux-stride-yf-tiled-ccs | |
| 397 | −kms_ccs@pipe-A-bad-aux-stride-y-tiled-gen12-rc-ccs | |
| 398 | −kms_ccs@pipe-A-bad-aux-stride-y-tiled-gen12-rc-ccs-cc | |
| 399 | −kms_ccs@pipe-A-bad-aux-stride-y-tiled-gen12-mc-ccs | |
| 400 | −kms_ccs@pipe-A-bad-aux-stride-4-tiled-mtl-rc-ccs | |
| 401 | −kms_ccs@pipe-A-bad-aux-stride-4-tiled-mtl-mc-ccs | |
| 402 | −kms_ccs@pipe-A-bad-aux-stride-4-tiled-mtl-rc-ccs-cc | |
| 403 | −kms_ccs@pipe-A-crc-sprite-planes-basic-y-tiled-ccs | |
| 404 | −kms_ccs@pipe-A-crc-sprite-planes-basic-yf-tiled-ccs | |
| 405 | −kms_ccs@pipe-A-crc-sprite-planes-basic-y-tiled-gen12-rc-ccs | |
| 406 | −kms_ccs@pipe-A-crc-sprite-planes-basic-y-tiled-gen12-rc-ccs-cc | |
| 407 | −kms_ccs@pipe-A-crc-sprite-planes-basic-y-tiled-gen12-mc-ccs | |
| 408 | −kms_ccs@pipe-A-crc-sprite-planes-basic-4-tiled-dg2-rc-ccs | |
| 409 | −kms_ccs@pipe-A-crc-sprite-planes-basic-4-tiled-dg2-mc-ccs | |
| 410 | −kms_ccs@pipe-A-crc-sprite-planes-basic-4-tiled-dg2-rc-ccs-cc | |
| 411 | −kms_ccs@pipe-A-crc-sprite-planes-basic-4-tiled-mtl-rc-ccs | |
| 412 | −kms_ccs@pipe-A-crc-sprite-planes-basic-4-tiled-mtl-mc-ccs | |
| 413 | −kms_ccs@pipe-A-crc-sprite-planes-basic-4-tiled-mtl-rc-ccs-cc | |
| 414 | −kms_ccs@pipe-B-bad-pixel-format-y-tiled-ccs | |
| 415 | −kms_ccs@pipe-B-bad-pixel-format-yf-tiled-ccs | |
| 416 | −kms_ccs@pipe-B-bad-pixel-format-y-tiled-gen12-rc-ccs | |
| 417 | −kms_ccs@pipe-B-bad-pixel-format-y-tiled-gen12-rc-ccs-cc | |
| 418 | −kms_ccs@pipe-B-bad-pixel-format-y-tiled-gen12-mc-ccs | |
| 419 | −kms_ccs@pipe-B-bad-pixel-format-4-tiled-dg2-rc-ccs | |
| 420 | −kms_ccs@pipe-B-bad-pixel-format-4-tiled-dg2-mc-ccs | |
| 421 | −kms_ccs@pipe-B-bad-pixel-format-4-tiled-dg2-rc-ccs-cc | |
| 422 | −kms_ccs@pipe-B-bad-pixel-format-4-tiled-mtl-rc-ccs | |
| 423 | −kms_ccs@pipe-B-bad-pixel-format-4-tiled-mtl-mc-ccs | |
| 424 | −kms_ccs@pipe-B-bad-pixel-format-4-tiled-mtl-rc-ccs-cc | |
| 425 | −kms_ccs@pipe-B-bad-rotation-90-y-tiled-ccs | |
| 426 | −kms_ccs@pipe-B-bad-rotation-90-yf-tiled-ccs | |
| 427 | −kms_ccs@pipe-B-bad-rotation-90-y-tiled-gen12-rc-ccs | |
| 428 | −kms_ccs@pipe-B-bad-rotation-90-y-tiled-gen12-rc-ccs-cc | |
| 429 | −kms_ccs@pipe-B-bad-rotation-90-y-tiled-gen12-mc-ccs | |
| 430 | −kms_ccs@pipe-B-bad-rotation-90-4-tiled-dg2-rc-ccs | |
| 431 | −kms_ccs@pipe-B-bad-rotation-90-4-tiled-dg2-mc-ccs | |
| 432 | −kms_ccs@pipe-B-bad-rotation-90-4-tiled-dg2-rc-ccs-cc | |
| 433 | −kms_ccs@pipe-B-bad-rotation-90-4-tiled-mtl-rc-ccs | |
| 434 | −kms_ccs@pipe-B-bad-rotation-90-4-tiled-mtl-mc-ccs | |
| 435 | −kms_ccs@pipe-B-bad-rotation-90-4-tiled-mtl-rc-ccs-cc | |
| 436 | −kms_ccs@pipe-B-crc-primary-basic-y-tiled-ccs | |
| 437 | −kms_ccs@pipe-B-crc-primary-basic-yf-tiled-ccs | |
| 438 | −kms_ccs@pipe-B-crc-primary-basic-y-tiled-gen12-rc-ccs | |
| 439 | −kms_ccs@pipe-B-crc-primary-basic-y-tiled-gen12-rc-ccs-cc | |
| 440 | −kms_ccs@pipe-B-crc-primary-basic-y-tiled-gen12-mc-ccs | |
| 441 | −kms_ccs@pipe-B-crc-primary-basic-4-tiled-dg2-rc-ccs | |
| 442 | −kms_ccs@pipe-B-crc-primary-basic-4-tiled-dg2-mc-ccs | |
| 443 | −kms_ccs@pipe-B-crc-primary-basic-4-tiled-dg2-rc-ccs-cc | |
| 444 | −kms_ccs@pipe-B-crc-primary-basic-4-tiled-mtl-rc-ccs | |
| 445 | −kms_ccs@pipe-B-crc-primary-basic-4-tiled-mtl-mc-ccs | |
| 446 | −kms_ccs@pipe-B-crc-primary-basic-4-tiled-mtl-rc-ccs-cc | |
| 447 | −kms_ccs@pipe-B-crc-primary-rotation-180-y-tiled-ccs | |
| 448 | −kms_ccs@pipe-B-crc-primary-rotation-180-yf-tiled-ccs | |
| 449 | −kms_ccs@pipe-B-crc-primary-rotation-180-y-tiled-gen12-rc-ccs | |
| 450 | −kms_ccs@pipe-B-crc-primary-rotation-180-y-tiled-gen12-rc-ccs-cc | |
| 451 | −kms_ccs@pipe-B-crc-primary-rotation-180-y-tiled-gen12-mc-ccs | |
| 452 | −kms_ccs@pipe-B-crc-primary-rotation-180-4-tiled-dg2-rc-ccs | |
| 453 | −kms_ccs@pipe-B-crc-primary-rotation-180-4-tiled-dg2-mc-ccs | |
| 454 | −kms_ccs@pipe-B-crc-primary-rotation-180-4-tiled-dg2-rc-ccs-cc | |
| 455 | −kms_ccs@pipe-B-crc-primary-rotation-180-4-tiled-mtl-rc-ccs | |
| 456 | −kms_ccs@pipe-B-crc-primary-rotation-180-4-tiled-mtl-mc-ccs | |
| 457 | −kms_ccs@pipe-B-crc-primary-rotation-180-4-tiled-mtl-rc-ccs-cc | |
| 458 | −kms_ccs@pipe-B-random-ccs-data-y-tiled-ccs | |
| 459 | −kms_ccs@pipe-B-random-ccs-data-yf-tiled-ccs | |
| 460 | −kms_ccs@pipe-B-random-ccs-data-y-tiled-gen12-rc-ccs | |
| 461 | −kms_ccs@pipe-B-random-ccs-data-y-tiled-gen12-rc-ccs-cc | |
| 462 | −kms_ccs@pipe-B-random-ccs-data-y-tiled-gen12-mc-ccs | |
| 463 | −kms_ccs@pipe-B-random-ccs-data-4-tiled-dg2-rc-ccs | |
| 464 | −kms_ccs@pipe-B-random-ccs-data-4-tiled-dg2-mc-ccs | |
| 465 | −kms_ccs@pipe-B-random-ccs-data-4-tiled-dg2-rc-ccs-cc | |
| 466 | −kms_ccs@pipe-B-random-ccs-data-4-tiled-mtl-rc-ccs | |
| 467 | −kms_ccs@pipe-B-random-ccs-data-4-tiled-mtl-mc-ccs | |
| 468 | −kms_ccs@pipe-B-random-ccs-data-4-tiled-mtl-rc-ccs-cc | |
| 469 | −kms_ccs@pipe-B-missing-ccs-buffer-y-tiled-ccs | |
| 470 | −kms_ccs@pipe-B-missing-ccs-buffer-yf-tiled-ccs | |
| 471 | −kms_ccs@pipe-B-missing-ccs-buffer-y-tiled-gen12-rc-ccs | |
| 472 | −kms_ccs@pipe-B-missing-ccs-buffer-y-tiled-gen12-rc-ccs-cc | |
| 473 | −kms_ccs@pipe-B-missing-ccs-buffer-y-tiled-gen12-mc-ccs | |
| 474 | −kms_ccs@pipe-B-missing-ccs-buffer-4-tiled-mtl-rc-ccs | |
| 475 | −kms_ccs@pipe-B-missing-ccs-buffer-4-tiled-mtl-mc-ccs | |
| 476 | −kms_ccs@pipe-B-missing-ccs-buffer-4-tiled-mtl-rc-ccs-cc | |
| 477 | −kms_ccs@pipe-B-ccs-on-another-bo-y-tiled-ccs | |
| 478 | −kms_ccs@pipe-B-ccs-on-another-bo-yf-tiled-ccs | |
| 479 | −kms_ccs@pipe-B-ccs-on-another-bo-y-tiled-gen12-rc-ccs | |
| 480 | −kms_ccs@pipe-B-ccs-on-another-bo-y-tiled-gen12-rc-ccs-cc | |
| 481 | −kms_ccs@pipe-B-ccs-on-another-bo-y-tiled-gen12-mc-ccs | |
| 482 | −kms_ccs@pipe-B-ccs-on-another-bo-4-tiled-mtl-rc-ccs | |
| 483 | −kms_ccs@pipe-B-ccs-on-another-bo-4-tiled-mtl-mc-ccs | |
| 484 | −kms_ccs@pipe-B-ccs-on-another-bo-4-tiled-mtl-rc-ccs-cc | |
| 485 | −kms_ccs@pipe-B-bad-aux-stride-y-tiled-ccs | |
| 486 | −kms_ccs@pipe-B-bad-aux-stride-yf-tiled-ccs | |
| 487 | −kms_ccs@pipe-B-bad-aux-stride-y-tiled-gen12-rc-ccs | |
| 488 | −kms_ccs@pipe-B-bad-aux-stride-y-tiled-gen12-rc-ccs-cc | |
| 489 | −kms_ccs@pipe-B-bad-aux-stride-y-tiled-gen12-mc-ccs | |
| 490 | −kms_ccs@pipe-B-bad-aux-stride-4-tiled-mtl-rc-ccs | |
| 491 | −kms_ccs@pipe-B-bad-aux-stride-4-tiled-mtl-mc-ccs | |
| 492 | −kms_ccs@pipe-B-bad-aux-stride-4-tiled-mtl-rc-ccs-cc | |
| 493 | −kms_ccs@pipe-B-crc-sprite-planes-basic-y-tiled-ccs | |
| 494 | −kms_ccs@pipe-B-crc-sprite-planes-basic-yf-tiled-ccs | |
| 495 | −kms_ccs@pipe-B-crc-sprite-planes-basic-y-tiled-gen12-rc-ccs | |
| 496 | −kms_ccs@pipe-B-crc-sprite-planes-basic-y-tiled-gen12-rc-ccs-cc | |
| 497 | −kms_ccs@pipe-B-crc-sprite-planes-basic-y-tiled-gen12-mc-ccs | |
| 498 | −kms_ccs@pipe-B-crc-sprite-planes-basic-4-tiled-dg2-rc-ccs | |
| 499 | −kms_ccs@pipe-B-crc-sprite-planes-basic-4-tiled-dg2-mc-ccs | |
| 500 | −kms_ccs@pipe-B-crc-sprite-planes-basic-4-tiled-dg2-rc-ccs-cc | |
| 501 | −kms_ccs@pipe-B-crc-sprite-planes-basic-4-tiled-mtl-rc-ccs | |
| 502 | −kms_ccs@pipe-B-crc-sprite-planes-basic-4-tiled-mtl-mc-ccs | |
| 503 | −kms_ccs@pipe-B-crc-sprite-planes-basic-4-tiled-mtl-rc-ccs-cc | |
| 504 | −kms_ccs@pipe-C-bad-pixel-format-y-tiled-ccs | |
| 505 | −kms_ccs@pipe-C-bad-pixel-format-yf-tiled-ccs | |
| 506 | −kms_ccs@pipe-C-bad-pixel-format-y-tiled-gen12-rc-ccs | |
| 507 | −kms_ccs@pipe-C-bad-pixel-format-y-tiled-gen12-rc-ccs-cc | |
| 508 | −kms_ccs@pipe-C-bad-pixel-format-y-tiled-gen12-mc-ccs | |
| 509 | −kms_ccs@pipe-C-bad-pixel-format-4-tiled-dg2-rc-ccs | |
| 510 | −kms_ccs@pipe-C-bad-pixel-format-4-tiled-dg2-mc-ccs | |
| 511 | −kms_ccs@pipe-C-bad-pixel-format-4-tiled-dg2-rc-ccs-cc | |
| 512 | −kms_ccs@pipe-C-bad-pixel-format-4-tiled-mtl-rc-ccs | |
| 513 | −kms_ccs@pipe-C-bad-pixel-format-4-tiled-mtl-mc-ccs | |
| 514 | −kms_ccs@pipe-C-bad-pixel-format-4-tiled-mtl-rc-ccs-cc | |
| 515 | −kms_ccs@pipe-C-bad-rotation-90-y-tiled-ccs | |
| 516 | −kms_ccs@pipe-C-bad-rotation-90-yf-tiled-ccs | |
| 517 | −kms_ccs@pipe-C-bad-rotation-90-y-tiled-gen12-rc-ccs | |
| 518 | −kms_ccs@pipe-C-bad-rotation-90-y-tiled-gen12-rc-ccs-cc | |
| 519 | −kms_ccs@pipe-C-bad-rotation-90-y-tiled-gen12-mc-ccs | |
| 520 | −kms_ccs@pipe-C-bad-rotation-90-4-tiled-dg2-rc-ccs | |
| 521 | −kms_ccs@pipe-C-bad-rotation-90-4-tiled-dg2-mc-ccs | |
| 522 | −kms_ccs@pipe-C-bad-rotation-90-4-tiled-dg2-rc-ccs-cc | |
| 523 | −kms_ccs@pipe-C-bad-rotation-90-4-tiled-mtl-rc-ccs | |
| 524 | −kms_ccs@pipe-C-bad-rotation-90-4-tiled-mtl-mc-ccs | |
| 525 | −kms_ccs@pipe-C-bad-rotation-90-4-tiled-mtl-rc-ccs-cc | |
| 526 | −kms_ccs@pipe-C-crc-primary-basic-y-tiled-ccs | |
| 527 | −kms_ccs@pipe-C-crc-primary-basic-yf-tiled-ccs | |
| 528 | −kms_ccs@pipe-C-crc-primary-basic-y-tiled-gen12-rc-ccs | |
| 529 | −kms_ccs@pipe-C-crc-primary-basic-y-tiled-gen12-rc-ccs-cc | |
| 530 | −kms_ccs@pipe-C-crc-primary-basic-y-tiled-gen12-mc-ccs | |
| 531 | −kms_ccs@pipe-C-crc-primary-basic-4-tiled-dg2-rc-ccs | |
| 532 | −kms_ccs@pipe-C-crc-primary-basic-4-tiled-dg2-mc-ccs | |
| 533 | −kms_ccs@pipe-C-crc-primary-basic-4-tiled-dg2-rc-ccs-cc | |
| 534 | −kms_ccs@pipe-C-crc-primary-basic-4-tiled-mtl-rc-ccs | |
| 535 | −kms_ccs@pipe-C-crc-primary-basic-4-tiled-mtl-mc-ccs | |
| 536 | −kms_ccs@pipe-C-crc-primary-basic-4-tiled-mtl-rc-ccs-cc | |
| 537 | −kms_ccs@pipe-C-crc-primary-rotation-180-y-tiled-ccs | |
| 538 | −kms_ccs@pipe-C-crc-primary-rotation-180-yf-tiled-ccs | |
| 539 | −kms_ccs@pipe-C-crc-primary-rotation-180-y-tiled-gen12-rc-ccs | |
| 540 | −kms_ccs@pipe-C-crc-primary-rotation-180-y-tiled-gen12-rc-ccs-cc | |
| 541 | −kms_ccs@pipe-C-crc-primary-rotation-180-y-tiled-gen12-mc-ccs | |
| 542 | −kms_ccs@pipe-C-crc-primary-rotation-180-4-tiled-dg2-rc-ccs | |
| 543 | −kms_ccs@pipe-C-crc-primary-rotation-180-4-tiled-dg2-mc-ccs | |
| 544 | −kms_ccs@pipe-C-crc-primary-rotation-180-4-tiled-dg2-rc-ccs-cc | |
| 545 | −kms_ccs@pipe-C-crc-primary-rotation-180-4-tiled-mtl-rc-ccs | |
| 546 | −kms_ccs@pipe-C-crc-primary-rotation-180-4-tiled-mtl-mc-ccs | |
| 547 | −kms_ccs@pipe-C-crc-primary-rotation-180-4-tiled-mtl-rc-ccs-cc | |
| 548 | −kms_ccs@pipe-C-random-ccs-data-y-tiled-ccs | |
| 549 | −kms_ccs@pipe-C-random-ccs-data-yf-tiled-ccs | |
| 550 | −kms_ccs@pipe-C-random-ccs-data-y-tiled-gen12-rc-ccs | |
| 551 | −kms_ccs@pipe-C-random-ccs-data-y-tiled-gen12-rc-ccs-cc | |
| 552 | −kms_ccs@pipe-C-random-ccs-data-y-tiled-gen12-mc-ccs | |
| 553 | −kms_ccs@pipe-C-random-ccs-data-4-tiled-dg2-rc-ccs | |
| 554 | −kms_ccs@pipe-C-random-ccs-data-4-tiled-dg2-mc-ccs | |
| 555 | −kms_ccs@pipe-C-random-ccs-data-4-tiled-dg2-rc-ccs-cc | |
| 556 | −kms_ccs@pipe-C-random-ccs-data-4-tiled-mtl-rc-ccs | |
| 557 | −kms_ccs@pipe-C-random-ccs-data-4-tiled-mtl-mc-ccs | |
| 558 | −kms_ccs@pipe-C-random-ccs-data-4-tiled-mtl-rc-ccs-cc | |
| 559 | −kms_ccs@pipe-C-missing-ccs-buffer-y-tiled-ccs | |
| 560 | −kms_ccs@pipe-C-missing-ccs-buffer-yf-tiled-ccs | |
| 561 | −kms_ccs@pipe-C-missing-ccs-buffer-y-tiled-gen12-rc-ccs | |
| 562 | −kms_ccs@pipe-C-missing-ccs-buffer-y-tiled-gen12-rc-ccs-cc | |
| 563 | −kms_ccs@pipe-C-missing-ccs-buffer-y-tiled-gen12-mc-ccs | |
| 564 | −kms_ccs@pipe-C-missing-ccs-buffer-4-tiled-mtl-rc-ccs | |
| 565 | −kms_ccs@pipe-C-missing-ccs-buffer-4-tiled-mtl-mc-ccs | |
| 566 | −kms_ccs@pipe-C-missing-ccs-buffer-4-tiled-mtl-rc-ccs-cc | |
| 567 | −kms_ccs@pipe-C-ccs-on-another-bo-y-tiled-ccs | |
| 568 | −kms_ccs@pipe-C-ccs-on-another-bo-yf-tiled-ccs | |
| 569 | −kms_ccs@pipe-C-ccs-on-another-bo-y-tiled-gen12-rc-ccs | |
| 570 | −kms_ccs@pipe-C-ccs-on-another-bo-y-tiled-gen12-rc-ccs-cc | |
| 571 | −kms_ccs@pipe-C-ccs-on-another-bo-y-tiled-gen12-mc-ccs | |
| 572 | −kms_ccs@pipe-C-ccs-on-another-bo-4-tiled-mtl-rc-ccs | |
| 573 | −kms_ccs@pipe-C-ccs-on-another-bo-4-tiled-mtl-mc-ccs | |
| 574 | −kms_ccs@pipe-C-ccs-on-another-bo-4-tiled-mtl-rc-ccs-cc | |
| 575 | −kms_ccs@pipe-C-bad-aux-stride-y-tiled-ccs | |
| 576 | −kms_ccs@pipe-C-bad-aux-stride-yf-tiled-ccs | |
| 577 | −kms_ccs@pipe-C-bad-aux-stride-y-tiled-gen12-rc-ccs | |
| 578 | −kms_ccs@pipe-C-bad-aux-stride-y-tiled-gen12-rc-ccs-cc | |
| 579 | −kms_ccs@pipe-C-bad-aux-stride-y-tiled-gen12-mc-ccs | |
| 580 | −kms_ccs@pipe-C-bad-aux-stride-4-tiled-mtl-rc-ccs | |
| 581 | −kms_ccs@pipe-C-bad-aux-stride-4-tiled-mtl-mc-ccs | |
| 582 | −kms_ccs@pipe-C-bad-aux-stride-4-tiled-mtl-rc-ccs-cc | |
| 583 | −kms_ccs@pipe-C-crc-sprite-planes-basic-y-tiled-ccs | |
| 584 | −kms_ccs@pipe-C-crc-sprite-planes-basic-yf-tiled-ccs | |
| 585 | −kms_ccs@pipe-C-crc-sprite-planes-basic-y-tiled-gen12-rc-ccs | |
| 586 | −kms_ccs@pipe-C-crc-sprite-planes-basic-y-tiled-gen12-rc-ccs-cc | |
| 587 | −kms_ccs@pipe-C-crc-sprite-planes-basic-y-tiled-gen12-mc-ccs | |
| 588 | −kms_ccs@pipe-C-crc-sprite-planes-basic-4-tiled-dg2-rc-ccs | |
| 589 | −kms_ccs@pipe-C-crc-sprite-planes-basic-4-tiled-dg2-mc-ccs | |
| 590 | −kms_ccs@pipe-C-crc-sprite-planes-basic-4-tiled-dg2-rc-ccs-cc | |
| 591 | −kms_ccs@pipe-C-crc-sprite-planes-basic-4-tiled-mtl-rc-ccs | |
| 592 | −kms_ccs@pipe-C-crc-sprite-planes-basic-4-tiled-mtl-mc-ccs | |
| 593 | −kms_ccs@pipe-C-crc-sprite-planes-basic-4-tiled-mtl-rc-ccs-cc | |
| 594 | −kms_ccs@pipe-D-bad-pixel-format-y-tiled-ccs | |
| 595 | −kms_ccs@pipe-D-bad-pixel-format-yf-tiled-ccs | |
| 596 | −kms_ccs@pipe-D-bad-pixel-format-y-tiled-gen12-rc-ccs | |
| 597 | −kms_ccs@pipe-D-bad-pixel-format-y-tiled-gen12-rc-ccs-cc | |
| 598 | −kms_ccs@pipe-D-bad-pixel-format-y-tiled-gen12-mc-ccs | |
| 599 | −kms_ccs@pipe-D-bad-pixel-format-4-tiled-dg2-rc-ccs | |
| 600 | −kms_ccs@pipe-D-bad-pixel-format-4-tiled-dg2-mc-ccs | |
| 601 | −kms_ccs@pipe-D-bad-pixel-format-4-tiled-dg2-rc-ccs-cc | |
| 602 | −kms_ccs@pipe-D-bad-pixel-format-4-tiled-mtl-rc-ccs | |
| 603 | −kms_ccs@pipe-D-bad-pixel-format-4-tiled-mtl-mc-ccs | |
| 604 | −kms_ccs@pipe-D-bad-pixel-format-4-tiled-mtl-rc-ccs-cc | |
| 605 | −kms_ccs@pipe-D-bad-rotation-90-y-tiled-ccs | |
| 606 | −kms_ccs@pipe-D-bad-rotation-90-yf-tiled-ccs | |
| 607 | −kms_ccs@pipe-D-bad-rotation-90-y-tiled-gen12-rc-ccs | |
| 608 | −kms_ccs@pipe-D-bad-rotation-90-y-tiled-gen12-rc-ccs-cc | |
| 609 | −kms_ccs@pipe-D-bad-rotation-90-y-tiled-gen12-mc-ccs | |
| 610 | −kms_ccs@pipe-D-bad-rotation-90-4-tiled-dg2-rc-ccs | |
| 611 | −kms_ccs@pipe-D-bad-rotation-90-4-tiled-dg2-mc-ccs | |
| 612 | −kms_ccs@pipe-D-bad-rotation-90-4-tiled-dg2-rc-ccs-cc | |
| 613 | −kms_ccs@pipe-D-bad-rotation-90-4-tiled-mtl-rc-ccs | |
| 614 | −kms_ccs@pipe-D-bad-rotation-90-4-tiled-mtl-mc-ccs | |
| 615 | −kms_ccs@pipe-D-bad-rotation-90-4-tiled-mtl-rc-ccs-cc | |
| 616 | −kms_ccs@pipe-D-crc-primary-basic-y-tiled-ccs | |
| 617 | −kms_ccs@pipe-D-crc-primary-basic-yf-tiled-ccs | |
| 618 | −kms_ccs@pipe-D-crc-primary-basic-y-tiled-gen12-rc-ccs | |
| 619 | −kms_ccs@pipe-D-crc-primary-basic-y-tiled-gen12-rc-ccs-cc | |
| 620 | −kms_ccs@pipe-D-crc-primary-basic-y-tiled-gen12-mc-ccs | |
| 621 | −kms_ccs@pipe-D-crc-primary-basic-4-tiled-dg2-rc-ccs | |
| 622 | −kms_ccs@pipe-D-crc-primary-basic-4-tiled-dg2-mc-ccs | |
| 623 | −kms_ccs@pipe-D-crc-primary-basic-4-tiled-dg2-rc-ccs-cc | |
| 624 | −kms_ccs@pipe-D-crc-primary-basic-4-tiled-mtl-rc-ccs | |
| 625 | −kms_ccs@pipe-D-crc-primary-basic-4-tiled-mtl-mc-ccs | |
| 626 | −kms_ccs@pipe-D-crc-primary-basic-4-tiled-mtl-rc-ccs-cc | |
| 627 | −kms_ccs@pipe-D-crc-primary-rotation-180-y-tiled-ccs | |
| 628 | −kms_ccs@pipe-D-crc-primary-rotation-180-yf-tiled-ccs | |
| 629 | −kms_ccs@pipe-D-crc-primary-rotation-180-y-tiled-gen12-rc-ccs | |
| 630 | −kms_ccs@pipe-D-crc-primary-rotation-180-y-tiled-gen12-rc-ccs-cc | |
| 631 | −kms_ccs@pipe-D-crc-primary-rotation-180-y-tiled-gen12-mc-ccs | |
| 632 | −kms_ccs@pipe-D-crc-primary-rotation-180-4-tiled-dg2-rc-ccs | |
| 633 | −kms_ccs@pipe-D-crc-primary-rotation-180-4-tiled-dg2-mc-ccs | |
| 634 | −kms_ccs@pipe-D-crc-primary-rotation-180-4-tiled-dg2-rc-ccs-cc | |
| 635 | −kms_ccs@pipe-D-crc-primary-rotation-180-4-tiled-mtl-rc-ccs | |
| 636 | −kms_ccs@pipe-D-crc-primary-rotation-180-4-tiled-mtl-mc-ccs | |
| 637 | −kms_ccs@pipe-D-crc-primary-rotation-180-4-tiled-mtl-rc-ccs-cc | |
| 638 | −kms_ccs@pipe-D-random-ccs-data-y-tiled-ccs | |
| 639 | −kms_ccs@pipe-D-random-ccs-data-yf-tiled-ccs | |
| 640 | −kms_ccs@pipe-D-random-ccs-data-y-tiled-gen12-rc-ccs | |
| 641 | −kms_ccs@pipe-D-random-ccs-data-y-tiled-gen12-rc-ccs-cc | |
| 642 | −kms_ccs@pipe-D-random-ccs-data-y-tiled-gen12-mc-ccs | |
| 643 | −kms_ccs@pipe-D-random-ccs-data-4-tiled-dg2-rc-ccs | |
| 644 | −kms_ccs@pipe-D-random-ccs-data-4-tiled-dg2-mc-ccs | |
| 645 | −kms_ccs@pipe-D-random-ccs-data-4-tiled-dg2-rc-ccs-cc | |
| 646 | −kms_ccs@pipe-D-random-ccs-data-4-tiled-mtl-rc-ccs | |
| 647 | −kms_ccs@pipe-D-random-ccs-data-4-tiled-mtl-mc-ccs | |
| 648 | −kms_ccs@pipe-D-random-ccs-data-4-tiled-mtl-rc-ccs-cc | |
| 649 | −kms_ccs@pipe-D-missing-ccs-buffer-y-tiled-ccs | |
| 650 | −kms_ccs@pipe-D-missing-ccs-buffer-yf-tiled-ccs | |
| 651 | −kms_ccs@pipe-D-missing-ccs-buffer-y-tiled-gen12-rc-ccs | |
| 652 | −kms_ccs@pipe-D-missing-ccs-buffer-y-tiled-gen12-rc-ccs-cc | |
| 653 | −kms_ccs@pipe-D-missing-ccs-buffer-y-tiled-gen12-mc-ccs | |
| 654 | −kms_ccs@pipe-D-missing-ccs-buffer-4-tiled-mtl-rc-ccs | |
| 655 | −kms_ccs@pipe-D-missing-ccs-buffer-4-tiled-mtl-mc-ccs | |
| 656 | −kms_ccs@pipe-D-missing-ccs-buffer-4-tiled-mtl-rc-ccs-cc | |
| 657 | −kms_ccs@pipe-D-ccs-on-another-bo-y-tiled-ccs | |
| 658 | −kms_ccs@pipe-D-ccs-on-another-bo-yf-tiled-ccs | |
| 659 | −kms_ccs@pipe-D-ccs-on-another-bo-y-tiled-gen12-rc-ccs | |
| 660 | −kms_ccs@pipe-D-ccs-on-another-bo-y-tiled-gen12-rc-ccs-cc | |
| 661 | −kms_ccs@pipe-D-ccs-on-another-bo-y-tiled-gen12-mc-ccs | |
| 662 | −kms_ccs@pipe-D-ccs-on-another-bo-4-tiled-mtl-rc-ccs | |
| 663 | −kms_ccs@pipe-D-ccs-on-another-bo-4-tiled-mtl-mc-ccs | |
| 664 | −kms_ccs@pipe-D-ccs-on-another-bo-4-tiled-mtl-rc-ccs-cc | |
| 665 | −kms_ccs@pipe-D-bad-aux-stride-y-tiled-ccs | |
| 666 | −kms_ccs@pipe-D-bad-aux-stride-yf-tiled-ccs | |
| 667 | −kms_ccs@pipe-D-bad-aux-stride-y-tiled-gen12-rc-ccs | |
| 668 | −kms_ccs@pipe-D-bad-aux-stride-y-tiled-gen12-rc-ccs-cc | |
| 669 | −kms_ccs@pipe-D-bad-aux-stride-y-tiled-gen12-mc-ccs | |
| 670 | −kms_ccs@pipe-D-bad-aux-stride-4-tiled-mtl-rc-ccs | |
| 671 | −kms_ccs@pipe-D-bad-aux-stride-4-tiled-mtl-mc-ccs | |
| 672 | −kms_ccs@pipe-D-bad-aux-stride-4-tiled-mtl-rc-ccs-cc | |
| 673 | −kms_ccs@pipe-D-crc-sprite-planes-basic-y-tiled-ccs | |
| 674 | −kms_ccs@pipe-D-crc-sprite-planes-basic-yf-tiled-ccs | |
| 675 | −kms_ccs@pipe-D-crc-sprite-planes-basic-y-tiled-gen12-rc-ccs | |
| 676 | −kms_ccs@pipe-D-crc-sprite-planes-basic-y-tiled-gen12-rc-ccs-cc | |
| 677 | −kms_ccs@pipe-D-crc-sprite-planes-basic-y-tiled-gen12-mc-ccs | |
| 678 | −kms_ccs@pipe-D-crc-sprite-planes-basic-4-tiled-dg2-rc-ccs | |
| 679 | −kms_ccs@pipe-D-crc-sprite-planes-basic-4-tiled-dg2-mc-ccs | |
| 680 | −kms_ccs@pipe-D-crc-sprite-planes-basic-4-tiled-dg2-rc-ccs-cc | |
| 681 | −kms_ccs@pipe-D-crc-sprite-planes-basic-4-tiled-mtl-rc-ccs | |
| 682 | −kms_ccs@pipe-D-crc-sprite-planes-basic-4-tiled-mtl-mc-ccs | |
| 683 | −kms_ccs@pipe-D-crc-sprite-planes-basic-4-tiled-mtl-rc-ccs-cc | |
| 684 | −kms_ccs@pipe-E-bad-pixel-format-y-tiled-ccs | |
| 685 | −kms_ccs@pipe-E-bad-pixel-format-yf-tiled-ccs | |
| 686 | −kms_ccs@pipe-E-bad-pixel-format-y-tiled-gen12-rc-ccs | |
| 687 | −kms_ccs@pipe-E-bad-pixel-format-y-tiled-gen12-rc-ccs-cc | |
| 688 | −kms_ccs@pipe-E-bad-pixel-format-y-tiled-gen12-mc-ccs | |
| 689 | −kms_ccs@pipe-E-bad-pixel-format-4-tiled-dg2-rc-ccs | |
| 690 | −kms_ccs@pipe-E-bad-pixel-format-4-tiled-dg2-mc-ccs | |
| 691 | −kms_ccs@pipe-E-bad-pixel-format-4-tiled-dg2-rc-ccs-cc | |
| 692 | −kms_ccs@pipe-E-bad-pixel-format-4-tiled-mtl-rc-ccs | |
| 693 | −kms_ccs@pipe-E-bad-pixel-format-4-tiled-mtl-mc-ccs | |
| 694 | −kms_ccs@pipe-E-bad-pixel-format-4-tiled-mtl-rc-ccs-cc | |
| 695 | −kms_ccs@pipe-E-bad-rotation-90-y-tiled-ccs | |
| 696 | −kms_ccs@pipe-E-bad-rotation-90-yf-tiled-ccs | |
| 697 | −kms_ccs@pipe-E-bad-rotation-90-y-tiled-gen12-rc-ccs | |
| 698 | −kms_ccs@pipe-E-bad-rotation-90-y-tiled-gen12-rc-ccs-cc | |
| 699 | −kms_ccs@pipe-E-bad-rotation-90-y-tiled-gen12-mc-ccs | |
| 700 | −kms_ccs@pipe-E-bad-rotation-90-4-tiled-dg2-rc-ccs | |
| 701 | −kms_ccs@pipe-E-bad-rotation-90-4-tiled-dg2-mc-ccs | |
| 702 | −kms_ccs@pipe-E-bad-rotation-90-4-tiled-dg2-rc-ccs-cc | |
| 703 | −kms_ccs@pipe-E-bad-rotation-90-4-tiled-mtl-rc-ccs | |
| 704 | −kms_ccs@pipe-E-bad-rotation-90-4-tiled-mtl-mc-ccs | |
| 705 | −kms_ccs@pipe-E-bad-rotation-90-4-tiled-mtl-rc-ccs-cc | |
| 706 | −kms_ccs@pipe-E-crc-primary-basic-y-tiled-ccs | |
| 707 | −kms_ccs@pipe-E-crc-primary-basic-yf-tiled-ccs | |
| 708 | −kms_ccs@pipe-E-crc-primary-basic-y-tiled-gen12-rc-ccs | |
| 709 | −kms_ccs@pipe-E-crc-primary-basic-y-tiled-gen12-rc-ccs-cc | |
| 710 | −kms_ccs@pipe-E-crc-primary-basic-y-tiled-gen12-mc-ccs | |
| 711 | −kms_ccs@pipe-E-crc-primary-basic-4-tiled-dg2-rc-ccs | |
| 712 | −kms_ccs@pipe-E-crc-primary-basic-4-tiled-dg2-mc-ccs | |
| 713 | −kms_ccs@pipe-E-crc-primary-basic-4-tiled-dg2-rc-ccs-cc | |
| 714 | −kms_ccs@pipe-E-crc-primary-basic-4-tiled-mtl-rc-ccs | |
| 715 | −kms_ccs@pipe-E-crc-primary-basic-4-tiled-mtl-mc-ccs | |
| 716 | −kms_ccs@pipe-E-crc-primary-basic-4-tiled-mtl-rc-ccs-cc | |
| 717 | −kms_ccs@pipe-E-crc-primary-rotation-180-y-tiled-ccs | |
| 718 | −kms_ccs@pipe-E-crc-primary-rotation-180-yf-tiled-ccs | |
| 719 | −kms_ccs@pipe-E-crc-primary-rotation-180-y-tiled-gen12-rc-ccs | |
| 720 | −kms_ccs@pipe-E-crc-primary-rotation-180-y-tiled-gen12-rc-ccs-cc | |
| 721 | −kms_ccs@pipe-E-crc-primary-rotation-180-y-tiled-gen12-mc-ccs | |
| 722 | −kms_ccs@pipe-E-crc-primary-rotation-180-4-tiled-dg2-rc-ccs | |
| 723 | −kms_ccs@pipe-E-crc-primary-rotation-180-4-tiled-dg2-mc-ccs | |
| 724 | −kms_ccs@pipe-E-crc-primary-rotation-180-4-tiled-dg2-rc-ccs-cc | |
| 725 | −kms_ccs@pipe-E-crc-primary-rotation-180-4-tiled-mtl-rc-ccs | |
| 726 | −kms_ccs@pipe-E-crc-primary-rotation-180-4-tiled-mtl-mc-ccs | |
| 727 | −kms_ccs@pipe-E-crc-primary-rotation-180-4-tiled-mtl-rc-ccs-cc | |
| 728 | −kms_ccs@pipe-E-random-ccs-data-y-tiled-ccs | |
| 729 | −kms_ccs@pipe-E-random-ccs-data-yf-tiled-ccs | |
| 730 | −kms_ccs@pipe-E-random-ccs-data-y-tiled-gen12-rc-ccs | |
| 731 | −kms_ccs@pipe-E-random-ccs-data-y-tiled-gen12-rc-ccs-cc | |
| 732 | −kms_ccs@pipe-E-random-ccs-data-y-tiled-gen12-mc-ccs | |
| 733 | −kms_ccs@pipe-E-random-ccs-data-4-tiled-dg2-rc-ccs | |
| 734 | −kms_ccs@pipe-E-random-ccs-data-4-tiled-dg2-mc-ccs | |
| 735 | −kms_ccs@pipe-E-random-ccs-data-4-tiled-dg2-rc-ccs-cc | |
| 736 | −kms_ccs@pipe-E-random-ccs-data-4-tiled-mtl-rc-ccs | |
| 737 | −kms_ccs@pipe-E-random-ccs-data-4-tiled-mtl-mc-ccs | |
| 738 | −kms_ccs@pipe-E-random-ccs-data-4-tiled-mtl-rc-ccs-cc | |
| 739 | −kms_ccs@pipe-E-missing-ccs-buffer-y-tiled-ccs | |
| 740 | −kms_ccs@pipe-E-missing-ccs-buffer-yf-tiled-ccs | |
| 741 | −kms_ccs@pipe-E-missing-ccs-buffer-y-tiled-gen12-rc-ccs | |
| 742 | −kms_ccs@pipe-E-missing-ccs-buffer-y-tiled-gen12-rc-ccs-cc | |
| 743 | −kms_ccs@pipe-E-missing-ccs-buffer-y-tiled-gen12-mc-ccs | |
| 744 | −kms_ccs@pipe-E-missing-ccs-buffer-4-tiled-mtl-rc-ccs | |
| 745 | −kms_ccs@pipe-E-missing-ccs-buffer-4-tiled-mtl-mc-ccs | |
| 746 | −kms_ccs@pipe-E-missing-ccs-buffer-4-tiled-mtl-rc-ccs-cc | |
| 747 | −kms_ccs@pipe-E-ccs-on-another-bo-y-tiled-ccs | |
| 748 | −kms_ccs@pipe-E-ccs-on-another-bo-yf-tiled-ccs | |
| 749 | −kms_ccs@pipe-E-ccs-on-another-bo-y-tiled-gen12-rc-ccs | |
| 750 | −kms_ccs@pipe-E-ccs-on-another-bo-y-tiled-gen12-rc-ccs-cc | |
| 751 | −kms_ccs@pipe-E-ccs-on-another-bo-y-tiled-gen12-mc-ccs | |
| 752 | −kms_ccs@pipe-E-ccs-on-another-bo-4-tiled-mtl-rc-ccs | |
| 753 | −kms_ccs@pipe-E-ccs-on-another-bo-4-tiled-mtl-mc-ccs | |
| 754 | −kms_ccs@pipe-E-ccs-on-another-bo-4-tiled-mtl-rc-ccs-cc | |
| 755 | −kms_ccs@pipe-E-bad-aux-stride-y-tiled-ccs | |
| 756 | −kms_ccs@pipe-E-bad-aux-stride-yf-tiled-ccs | |
| 757 | −kms_ccs@pipe-E-bad-aux-stride-y-tiled-gen12-rc-ccs | |
| 758 | −kms_ccs@pipe-E-bad-aux-stride-y-tiled-gen12-rc-ccs-cc | |
| 759 | −kms_ccs@pipe-E-bad-aux-stride-y-tiled-gen12-mc-ccs | |
| 760 | −kms_ccs@pipe-E-bad-aux-stride-4-tiled-mtl-rc-ccs | |
| 761 | −kms_ccs@pipe-E-bad-aux-stride-4-tiled-mtl-mc-ccs | |
| 762 | −kms_ccs@pipe-E-bad-aux-stride-4-tiled-mtl-rc-ccs-cc | |
| 763 | −kms_ccs@pipe-E-crc-sprite-planes-basic-y-tiled-ccs | |
| 764 | −kms_ccs@pipe-E-crc-sprite-planes-basic-yf-tiled-ccs | |
| 765 | −kms_ccs@pipe-E-crc-sprite-planes-basic-y-tiled-gen12-rc-ccs | |
| 766 | −kms_ccs@pipe-E-crc-sprite-planes-basic-y-tiled-gen12-rc-ccs-cc | |
| 767 | −kms_ccs@pipe-E-crc-sprite-planes-basic-y-tiled-gen12-mc-ccs | |
| 768 | −kms_ccs@pipe-E-crc-sprite-planes-basic-4-tiled-dg2-rc-ccs | |
| 769 | −kms_ccs@pipe-E-crc-sprite-planes-basic-4-tiled-dg2-mc-ccs | |
| 770 | −kms_ccs@pipe-E-crc-sprite-planes-basic-4-tiled-dg2-rc-ccs-cc | |
| 771 | −kms_ccs@pipe-E-crc-sprite-planes-basic-4-tiled-mtl-rc-ccs | |
| 772 | −kms_ccs@pipe-E-crc-sprite-planes-basic-4-tiled-mtl-mc-ccs | |
| 773 | −kms_ccs@pipe-E-crc-sprite-planes-basic-4-tiled-mtl-rc-ccs-cc | |
| 774 | −kms_ccs@pipe-F-bad-pixel-format-y-tiled-ccs | |
| 775 | −kms_ccs@pipe-F-bad-pixel-format-yf-tiled-ccs | |
| 776 | −kms_ccs@pipe-F-bad-pixel-format-y-tiled-gen12-rc-ccs | |
| 777 | −kms_ccs@pipe-F-bad-pixel-format-y-tiled-gen12-rc-ccs-cc | |
| 778 | −kms_ccs@pipe-F-bad-pixel-format-y-tiled-gen12-mc-ccs | |
| 779 | −kms_ccs@pipe-F-bad-pixel-format-4-tiled-dg2-rc-ccs | |
| 780 | −kms_ccs@pipe-F-bad-pixel-format-4-tiled-dg2-mc-ccs | |
| 781 | −kms_ccs@pipe-F-bad-pixel-format-4-tiled-dg2-rc-ccs-cc | |
| 782 | −kms_ccs@pipe-F-bad-pixel-format-4-tiled-mtl-rc-ccs | |
| 783 | −kms_ccs@pipe-F-bad-pixel-format-4-tiled-mtl-mc-ccs | |
| 784 | −kms_ccs@pipe-F-bad-pixel-format-4-tiled-mtl-rc-ccs-cc | |
| 785 | −kms_ccs@pipe-F-bad-rotation-90-y-tiled-ccs | |
| 786 | −kms_ccs@pipe-F-bad-rotation-90-yf-tiled-ccs | |
| 787 | −kms_ccs@pipe-F-bad-rotation-90-y-tiled-gen12-rc-ccs | |
| 788 | −kms_ccs@pipe-F-bad-rotation-90-y-tiled-gen12-rc-ccs-cc | |
| 789 | −kms_ccs@pipe-F-bad-rotation-90-y-tiled-gen12-mc-ccs | |
| 790 | −kms_ccs@pipe-F-bad-rotation-90-4-tiled-dg2-rc-ccs | |
| 791 | −kms_ccs@pipe-F-bad-rotation-90-4-tiled-dg2-mc-ccs | |
| 792 | −kms_ccs@pipe-F-bad-rotation-90-4-tiled-dg2-rc-ccs-cc | |
| 793 | −kms_ccs@pipe-F-bad-rotation-90-4-tiled-mtl-rc-ccs | |
| 794 | −kms_ccs@pipe-F-bad-rotation-90-4-tiled-mtl-mc-ccs | |
| 795 | −kms_ccs@pipe-F-bad-rotation-90-4-tiled-mtl-rc-ccs-cc | |
| 796 | −kms_ccs@pipe-F-crc-primary-basic-y-tiled-ccs | |
| 797 | −kms_ccs@pipe-F-crc-primary-basic-yf-tiled-ccs | |
| 798 | −kms_ccs@pipe-F-crc-primary-basic-y-tiled-gen12-rc-ccs | |
| 799 | −kms_ccs@pipe-F-crc-primary-basic-y-tiled-gen12-rc-ccs-cc | |
| 800 | −kms_ccs@pipe-F-crc-primary-basic-y-tiled-gen12-mc-ccs | |
| 801 | −kms_ccs@pipe-F-crc-primary-basic-4-tiled-dg2-rc-ccs | |
| 802 | −kms_ccs@pipe-F-crc-primary-basic-4-tiled-dg2-mc-ccs | |
| 803 | −kms_ccs@pipe-F-crc-primary-basic-4-tiled-dg2-rc-ccs-cc | |
| 804 | −kms_ccs@pipe-F-crc-primary-basic-4-tiled-mtl-rc-ccs | |
| 805 | −kms_ccs@pipe-F-crc-primary-basic-4-tiled-mtl-mc-ccs | |
| 806 | −kms_ccs@pipe-F-crc-primary-basic-4-tiled-mtl-rc-ccs-cc | |
| 807 | −kms_ccs@pipe-F-crc-primary-rotation-180-y-tiled-ccs | |
| 808 | −kms_ccs@pipe-F-crc-primary-rotation-180-yf-tiled-ccs | |
| 809 | −kms_ccs@pipe-F-crc-primary-rotation-180-y-tiled-gen12-rc-ccs | |
| 810 | −kms_ccs@pipe-F-crc-primary-rotation-180-y-tiled-gen12-rc-ccs-cc | |
| 811 | −kms_ccs@pipe-F-crc-primary-rotation-180-y-tiled-gen12-mc-ccs | |
| 812 | −kms_ccs@pipe-F-crc-primary-rotation-180-4-tiled-dg2-rc-ccs | |
| 813 | −kms_ccs@pipe-F-crc-primary-rotation-180-4-tiled-dg2-mc-ccs | |
| 814 | −kms_ccs@pipe-F-crc-primary-rotation-180-4-tiled-dg2-rc-ccs-cc | |
| 815 | −kms_ccs@pipe-F-crc-primary-rotation-180-4-tiled-mtl-rc-ccs | |
| 816 | −kms_ccs@pipe-F-crc-primary-rotation-180-4-tiled-mtl-mc-ccs | |
| 817 | −kms_ccs@pipe-F-crc-primary-rotation-180-4-tiled-mtl-rc-ccs-cc | |
| 818 | −kms_ccs@pipe-F-random-ccs-data-y-tiled-ccs | |
| 819 | −kms_ccs@pipe-F-random-ccs-data-yf-tiled-ccs | |
| 820 | −kms_ccs@pipe-F-random-ccs-data-y-tiled-gen12-rc-ccs | |
| 821 | −kms_ccs@pipe-F-random-ccs-data-y-tiled-gen12-rc-ccs-cc | |
| 822 | −kms_ccs@pipe-F-random-ccs-data-y-tiled-gen12-mc-ccs | |
| 823 | −kms_ccs@pipe-F-random-ccs-data-4-tiled-dg2-rc-ccs | |
| 824 | −kms_ccs@pipe-F-random-ccs-data-4-tiled-dg2-mc-ccs | |
| 825 | −kms_ccs@pipe-F-random-ccs-data-4-tiled-dg2-rc-ccs-cc | |
| 826 | −kms_ccs@pipe-F-random-ccs-data-4-tiled-mtl-rc-ccs | |
| 827 | −kms_ccs@pipe-F-random-ccs-data-4-tiled-mtl-mc-ccs | |
| 828 | −kms_ccs@pipe-F-random-ccs-data-4-tiled-mtl-rc-ccs-cc | |
| 829 | −kms_ccs@pipe-F-missing-ccs-buffer-y-tiled-ccs | |
| 830 | −kms_ccs@pipe-F-missing-ccs-buffer-yf-tiled-ccs | |
| 831 | −kms_ccs@pipe-F-missing-ccs-buffer-y-tiled-gen12-rc-ccs | |
| 832 | −kms_ccs@pipe-F-missing-ccs-buffer-y-tiled-gen12-rc-ccs-cc | |
| 833 | −kms_ccs@pipe-F-missing-ccs-buffer-y-tiled-gen12-mc-ccs | |
| 834 | −kms_ccs@pipe-F-missing-ccs-buffer-4-tiled-mtl-rc-ccs | |
| 835 | −kms_ccs@pipe-F-missing-ccs-buffer-4-tiled-mtl-mc-ccs | |
| 836 | −kms_ccs@pipe-F-missing-ccs-buffer-4-tiled-mtl-rc-ccs-cc | |
| 837 | −kms_ccs@pipe-F-ccs-on-another-bo-y-tiled-ccs | |
| 838 | −kms_ccs@pipe-F-ccs-on-another-bo-yf-tiled-ccs | |
| 839 | −kms_ccs@pipe-F-ccs-on-another-bo-y-tiled-gen12-rc-ccs | |
| 840 | −kms_ccs@pipe-F-ccs-on-another-bo-y-tiled-gen12-rc-ccs-cc | |
| 841 | −kms_ccs@pipe-F-ccs-on-another-bo-y-tiled-gen12-mc-ccs | |
| 842 | −kms_ccs@pipe-F-ccs-on-another-bo-4-tiled-mtl-rc-ccs | |
| 843 | −kms_ccs@pipe-F-ccs-on-another-bo-4-tiled-mtl-mc-ccs | |
| 844 | −kms_ccs@pipe-F-ccs-on-another-bo-4-tiled-mtl-rc-ccs-cc | |
| 845 | −kms_ccs@pipe-F-bad-aux-stride-y-tiled-ccs | |
| 846 | −kms_ccs@pipe-F-bad-aux-stride-yf-tiled-ccs | |
| 847 | −kms_ccs@pipe-F-bad-aux-stride-y-tiled-gen12-rc-ccs | |
| 848 | −kms_ccs@pipe-F-bad-aux-stride-y-tiled-gen12-rc-ccs-cc | |
| 849 | −kms_ccs@pipe-F-bad-aux-stride-y-tiled-gen12-mc-ccs | |
| 850 | −kms_ccs@pipe-F-bad-aux-stride-4-tiled-mtl-rc-ccs | |
| 851 | −kms_ccs@pipe-F-bad-aux-stride-4-tiled-mtl-mc-ccs | |
| 852 | −kms_ccs@pipe-F-bad-aux-stride-4-tiled-mtl-rc-ccs-cc | |
| 853 | −kms_ccs@pipe-F-crc-sprite-planes-basic-y-tiled-ccs | |
| 854 | −kms_ccs@pipe-F-crc-sprite-planes-basic-yf-tiled-ccs | |
| 855 | −kms_ccs@pipe-F-crc-sprite-planes-basic-y-tiled-gen12-rc-ccs | |
| 856 | −kms_ccs@pipe-F-crc-sprite-planes-basic-y-tiled-gen12-rc-ccs-cc | |
| 857 | −kms_ccs@pipe-F-crc-sprite-planes-basic-y-tiled-gen12-mc-ccs | |
| 858 | −kms_ccs@pipe-F-crc-sprite-planes-basic-4-tiled-dg2-rc-ccs | |
| 859 | −kms_ccs@pipe-F-crc-sprite-planes-basic-4-tiled-dg2-mc-ccs | |
| 860 | −kms_ccs@pipe-F-crc-sprite-planes-basic-4-tiled-dg2-rc-ccs-cc | |
| 861 | −kms_ccs@pipe-F-crc-sprite-planes-basic-4-tiled-mtl-rc-ccs | |
| 862 | −kms_ccs@pipe-F-crc-sprite-planes-basic-4-tiled-mtl-mc-ccs | |
| 863 | −kms_ccs@pipe-F-crc-sprite-planes-basic-4-tiled-mtl-rc-ccs-cc | |
| 864 | −kms_ccs@pipe-G-bad-pixel-format-y-tiled-ccs | |
| 865 | −kms_ccs@pipe-G-bad-pixel-format-yf-tiled-ccs | |
| 866 | −kms_ccs@pipe-G-bad-pixel-format-y-tiled-gen12-rc-ccs | |
| 867 | −kms_ccs@pipe-G-bad-pixel-format-y-tiled-gen12-rc-ccs-cc | |
| 868 | −kms_ccs@pipe-G-bad-pixel-format-y-tiled-gen12-mc-ccs | |
| 869 | −kms_ccs@pipe-G-bad-pixel-format-4-tiled-dg2-rc-ccs | |
| 870 | −kms_ccs@pipe-G-bad-pixel-format-4-tiled-dg2-mc-ccs | |
| 871 | −kms_ccs@pipe-G-bad-pixel-format-4-tiled-dg2-rc-ccs-cc | |
| 872 | −kms_ccs@pipe-G-bad-pixel-format-4-tiled-mtl-rc-ccs | |
| 873 | −kms_ccs@pipe-G-bad-pixel-format-4-tiled-mtl-mc-ccs | |
| 874 | −kms_ccs@pipe-G-bad-pixel-format-4-tiled-mtl-rc-ccs-cc | |
| 875 | −kms_ccs@pipe-G-bad-rotation-90-y-tiled-ccs | |
| 876 | −kms_ccs@pipe-G-bad-rotation-90-yf-tiled-ccs | |
| 877 | −kms_ccs@pipe-G-bad-rotation-90-y-tiled-gen12-rc-ccs | |
| 878 | −kms_ccs@pipe-G-bad-rotation-90-y-tiled-gen12-rc-ccs-cc | |
| 879 | −kms_ccs@pipe-G-bad-rotation-90-y-tiled-gen12-mc-ccs | |
| 880 | −kms_ccs@pipe-G-bad-rotation-90-4-tiled-dg2-rc-ccs | |
| 881 | −kms_ccs@pipe-G-bad-rotation-90-4-tiled-dg2-mc-ccs | |
| 882 | −kms_ccs@pipe-G-bad-rotation-90-4-tiled-dg2-rc-ccs-cc | |
| 883 | −kms_ccs@pipe-G-bad-rotation-90-4-tiled-mtl-rc-ccs | |
| 884 | −kms_ccs@pipe-G-bad-rotation-90-4-tiled-mtl-mc-ccs | |
| 885 | −kms_ccs@pipe-G-bad-rotation-90-4-tiled-mtl-rc-ccs-cc | |
| 886 | −kms_ccs@pipe-G-crc-primary-basic-y-tiled-ccs | |
| 887 | −kms_ccs@pipe-G-crc-primary-basic-yf-tiled-ccs | |
| 888 | −kms_ccs@pipe-G-crc-primary-basic-y-tiled-gen12-rc-ccs | |
| 889 | −kms_ccs@pipe-G-crc-primary-basic-y-tiled-gen12-rc-ccs-cc | |
| 890 | −kms_ccs@pipe-G-crc-primary-basic-y-tiled-gen12-mc-ccs | |
| 891 | −kms_ccs@pipe-G-crc-primary-basic-4-tiled-dg2-rc-ccs | |
| 892 | −kms_ccs@pipe-G-crc-primary-basic-4-tiled-dg2-mc-ccs | |
| 893 | −kms_ccs@pipe-G-crc-primary-basic-4-tiled-dg2-rc-ccs-cc | |
| 894 | −kms_ccs@pipe-G-crc-primary-basic-4-tiled-mtl-rc-ccs | |
| 895 | −kms_ccs@pipe-G-crc-primary-basic-4-tiled-mtl-mc-ccs | |
| 896 | −kms_ccs@pipe-G-crc-primary-basic-4-tiled-mtl-rc-ccs-cc | |
| 897 | −kms_ccs@pipe-G-crc-primary-rotation-180-y-tiled-ccs | |
| 898 | −kms_ccs@pipe-G-crc-primary-rotation-180-yf-tiled-ccs | |
| 899 | −kms_ccs@pipe-G-crc-primary-rotation-180-y-tiled-gen12-rc-ccs | |
| 900 | −kms_ccs@pipe-G-crc-primary-rotation-180-y-tiled-gen12-rc-ccs-cc | |
| 901 | −kms_ccs@pipe-G-crc-primary-rotation-180-y-tiled-gen12-mc-ccs | |
| 902 | −kms_ccs@pipe-G-crc-primary-rotation-180-4-tiled-dg2-rc-ccs | |
| 903 | −kms_ccs@pipe-G-crc-primary-rotation-180-4-tiled-dg2-mc-ccs | |
| 904 | −kms_ccs@pipe-G-crc-primary-rotation-180-4-tiled-dg2-rc-ccs-cc | |
| 905 | −kms_ccs@pipe-G-crc-primary-rotation-180-4-tiled-mtl-rc-ccs | |
| 906 | −kms_ccs@pipe-G-crc-primary-rotation-180-4-tiled-mtl-mc-ccs | |
| 907 | −kms_ccs@pipe-G-crc-primary-rotation-180-4-tiled-mtl-rc-ccs-cc | |
| 908 | −kms_ccs@pipe-G-random-ccs-data-y-tiled-ccs | |
| 909 | −kms_ccs@pipe-G-random-ccs-data-yf-tiled-ccs | |
| 910 | −kms_ccs@pipe-G-random-ccs-data-y-tiled-gen12-rc-ccs | |
| 911 | −kms_ccs@pipe-G-random-ccs-data-y-tiled-gen12-rc-ccs-cc | |
| 912 | −kms_ccs@pipe-G-random-ccs-data-y-tiled-gen12-mc-ccs | |
| 913 | −kms_ccs@pipe-G-random-ccs-data-4-tiled-dg2-rc-ccs | |
| 914 | −kms_ccs@pipe-G-random-ccs-data-4-tiled-dg2-mc-ccs | |
| 915 | −kms_ccs@pipe-G-random-ccs-data-4-tiled-dg2-rc-ccs-cc | |
| 916 | −kms_ccs@pipe-G-random-ccs-data-4-tiled-mtl-rc-ccs | |
| 917 | −kms_ccs@pipe-G-random-ccs-data-4-tiled-mtl-mc-ccs | |
| 918 | −kms_ccs@pipe-G-random-ccs-data-4-tiled-mtl-rc-ccs-cc | |
| 919 | −kms_ccs@pipe-G-missing-ccs-buffer-y-tiled-ccs | |
| 920 | −kms_ccs@pipe-G-missing-ccs-buffer-yf-tiled-ccs | |
| 921 | −kms_ccs@pipe-G-missing-ccs-buffer-y-tiled-gen12-rc-ccs | |
| 922 | −kms_ccs@pipe-G-missing-ccs-buffer-y-tiled-gen12-rc-ccs-cc | |
| 923 | −kms_ccs@pipe-G-missing-ccs-buffer-y-tiled-gen12-mc-ccs | |
| 924 | −kms_ccs@pipe-G-missing-ccs-buffer-4-tiled-mtl-rc-ccs | |
| 925 | −kms_ccs@pipe-G-missing-ccs-buffer-4-tiled-mtl-mc-ccs | |
| 926 | −kms_ccs@pipe-G-missing-ccs-buffer-4-tiled-mtl-rc-ccs-cc | |
| 927 | −kms_ccs@pipe-G-ccs-on-another-bo-y-tiled-ccs | |
| 928 | −kms_ccs@pipe-G-ccs-on-another-bo-yf-tiled-ccs | |
| 929 | −kms_ccs@pipe-G-ccs-on-another-bo-y-tiled-gen12-rc-ccs | |
| 930 | −kms_ccs@pipe-G-ccs-on-another-bo-y-tiled-gen12-rc-ccs-cc | |
| 931 | −kms_ccs@pipe-G-ccs-on-another-bo-y-tiled-gen12-mc-ccs | |
| 932 | −kms_ccs@pipe-G-ccs-on-another-bo-4-tiled-mtl-rc-ccs | |
| 933 | −kms_ccs@pipe-G-ccs-on-another-bo-4-tiled-mtl-mc-ccs | |
| 934 | −kms_ccs@pipe-G-ccs-on-another-bo-4-tiled-mtl-rc-ccs-cc | |
| 935 | −kms_ccs@pipe-G-bad-aux-stride-y-tiled-ccs | |
| 936 | −kms_ccs@pipe-G-bad-aux-stride-yf-tiled-ccs | |
| 937 | −kms_ccs@pipe-G-bad-aux-stride-y-tiled-gen12-rc-ccs | |
| 938 | −kms_ccs@pipe-G-bad-aux-stride-y-tiled-gen12-rc-ccs-cc | |
| 939 | −kms_ccs@pipe-G-bad-aux-stride-y-tiled-gen12-mc-ccs | |
| 940 | −kms_ccs@pipe-G-bad-aux-stride-4-tiled-mtl-rc-ccs | |
| 941 | −kms_ccs@pipe-G-bad-aux-stride-4-tiled-mtl-mc-ccs | |
| 942 | −kms_ccs@pipe-G-bad-aux-stride-4-tiled-mtl-rc-ccs-cc | |
| 943 | −kms_ccs@pipe-G-crc-sprite-planes-basic-y-tiled-ccs | |
| 944 | −kms_ccs@pipe-G-crc-sprite-planes-basic-yf-tiled-ccs | |
| 945 | −kms_ccs@pipe-G-crc-sprite-planes-basic-y-tiled-gen12-rc-ccs | |
| 946 | −kms_ccs@pipe-G-crc-sprite-planes-basic-y-tiled-gen12-rc-ccs-cc | |
| 947 | −kms_ccs@pipe-G-crc-sprite-planes-basic-y-tiled-gen12-mc-ccs | |
| 948 | −kms_ccs@pipe-G-crc-sprite-planes-basic-4-tiled-dg2-rc-ccs | |
| 949 | −kms_ccs@pipe-G-crc-sprite-planes-basic-4-tiled-dg2-mc-ccs | |
| 950 | −kms_ccs@pipe-G-crc-sprite-planes-basic-4-tiled-dg2-rc-ccs-cc | |
| 951 | −kms_ccs@pipe-G-crc-sprite-planes-basic-4-tiled-mtl-rc-ccs | |
| 952 | −kms_ccs@pipe-G-crc-sprite-planes-basic-4-tiled-mtl-mc-ccs | |
| 953 | −kms_ccs@pipe-G-crc-sprite-planes-basic-4-tiled-mtl-rc-ccs-cc | |
| 954 | −kms_ccs@pipe-H-bad-pixel-format-y-tiled-ccs | |
| 955 | −kms_ccs@pipe-H-bad-pixel-format-yf-tiled-ccs | |
| 956 | −kms_ccs@pipe-H-bad-pixel-format-y-tiled-gen12-rc-ccs | |
| 957 | −kms_ccs@pipe-H-bad-pixel-format-y-tiled-gen12-rc-ccs-cc | |
| 958 | −kms_ccs@pipe-H-bad-pixel-format-y-tiled-gen12-mc-ccs | |
| 959 | −kms_ccs@pipe-H-bad-pixel-format-4-tiled-dg2-rc-ccs | |
| 960 | −kms_ccs@pipe-H-bad-pixel-format-4-tiled-dg2-mc-ccs | |
| 961 | −kms_ccs@pipe-H-bad-pixel-format-4-tiled-dg2-rc-ccs-cc | |
| 962 | −kms_ccs@pipe-H-bad-pixel-format-4-tiled-mtl-rc-ccs | |
| 963 | −kms_ccs@pipe-H-bad-pixel-format-4-tiled-mtl-mc-ccs | |
| 964 | −kms_ccs@pipe-H-bad-pixel-format-4-tiled-mtl-rc-ccs-cc | |
| 965 | −kms_ccs@pipe-H-bad-rotation-90-y-tiled-ccs | |
| 966 | −kms_ccs@pipe-H-bad-rotation-90-yf-tiled-ccs | |
| 967 | −kms_ccs@pipe-H-bad-rotation-90-y-tiled-gen12-rc-ccs | |
| 968 | −kms_ccs@pipe-H-bad-rotation-90-y-tiled-gen12-rc-ccs-cc | |
| 969 | −kms_ccs@pipe-H-bad-rotation-90-y-tiled-gen12-mc-ccs | |
| 970 | −kms_ccs@pipe-H-bad-rotation-90-4-tiled-dg2-rc-ccs | |
| 971 | −kms_ccs@pipe-H-bad-rotation-90-4-tiled-dg2-mc-ccs | |
| 972 | −kms_ccs@pipe-H-bad-rotation-90-4-tiled-dg2-rc-ccs-cc | |
| 973 | −kms_ccs@pipe-H-bad-rotation-90-4-tiled-mtl-rc-ccs | |
| 974 | −kms_ccs@pipe-H-bad-rotation-90-4-tiled-mtl-mc-ccs | |
| 975 | −kms_ccs@pipe-H-bad-rotation-90-4-tiled-mtl-rc-ccs-cc | |
| 976 | −kms_ccs@pipe-H-crc-primary-basic-y-tiled-ccs | |
| 977 | −kms_ccs@pipe-H-crc-primary-basic-yf-tiled-ccs | |
| 978 | −kms_ccs@pipe-H-crc-primary-basic-y-tiled-gen12-rc-ccs | |
| 979 | −kms_ccs@pipe-H-crc-primary-basic-y-tiled-gen12-rc-ccs-cc | |
| 980 | −kms_ccs@pipe-H-crc-primary-basic-y-tiled-gen12-mc-ccs | |
| 981 | −kms_ccs@pipe-H-crc-primary-basic-4-tiled-dg2-rc-ccs | |
| 982 | −kms_ccs@pipe-H-crc-primary-basic-4-tiled-dg2-mc-ccs | |
| 983 | −kms_ccs@pipe-H-crc-primary-basic-4-tiled-dg2-rc-ccs-cc | |
| 984 | −kms_ccs@pipe-H-crc-primary-basic-4-tiled-mtl-rc-ccs | |
| 985 | −kms_ccs@pipe-H-crc-primary-basic-4-tiled-mtl-mc-ccs | |
| 986 | −kms_ccs@pipe-H-crc-primary-basic-4-tiled-mtl-rc-ccs-cc | |
| 987 | −kms_ccs@pipe-H-crc-primary-rotation-180-y-tiled-ccs | |
| 988 | −kms_ccs@pipe-H-crc-primary-rotation-180-yf-tiled-ccs | |
| 989 | −kms_ccs@pipe-H-crc-primary-rotation-180-y-tiled-gen12-rc-ccs | |
| 990 | −kms_ccs@pipe-H-crc-primary-rotation-180-y-tiled-gen12-rc-ccs-cc | |
| 991 | −kms_ccs@pipe-H-crc-primary-rotation-180-y-tiled-gen12-mc-ccs | |
| 992 | −kms_ccs@pipe-H-crc-primary-rotation-180-4-tiled-dg2-rc-ccs | |
| 993 | −kms_ccs@pipe-H-crc-primary-rotation-180-4-tiled-dg2-mc-ccs | |
| 994 | −kms_ccs@pipe-H-crc-primary-rotation-180-4-tiled-dg2-rc-ccs-cc | |
| 995 | −kms_ccs@pipe-H-crc-primary-rotation-180-4-tiled-mtl-rc-ccs | |
| 996 | −kms_ccs@pipe-H-crc-primary-rotation-180-4-tiled-mtl-mc-ccs | |
| 997 | −kms_ccs@pipe-H-crc-primary-rotation-180-4-tiled-mtl-rc-ccs-cc | |
| 998 | −kms_ccs@pipe-H-random-ccs-data-y-tiled-ccs | |
| 999 | −kms_ccs@pipe-H-random-ccs-data-yf-tiled-ccs | |
| 1000 | −kms_ccs@pipe-H-random-ccs-data-y-tiled-gen12-rc-ccs | |
| 1001 | −kms_ccs@pipe-H-random-ccs-data-y-tiled-gen12-rc-ccs-cc | |
| 1002 | −kms_ccs@pipe-H-random-ccs-data-y-tiled-gen12-mc-ccs | |
| 1003 | −kms_ccs@pipe-H-random-ccs-data-4-tiled-dg2-rc-ccs | |
| 1004 | −kms_ccs@pipe-H-random-ccs-data-4-tiled-dg2-mc-ccs | |
| 1005 | −kms_ccs@pipe-H-random-ccs-data-4-tiled-dg2-rc-ccs-cc | |
| 1006 | −kms_ccs@pipe-H-random-ccs-data-4-tiled-mtl-rc-ccs | |
| 1007 | −kms_ccs@pipe-H-random-ccs-data-4-tiled-mtl-mc-ccs | |
| 1008 | −kms_ccs@pipe-H-random-ccs-data-4-tiled-mtl-rc-ccs-cc | |
| 1009 | −kms_ccs@pipe-H-missing-ccs-buffer-y-tiled-ccs | |
| 1010 | −kms_ccs@pipe-H-missing-ccs-buffer-yf-tiled-ccs | |
| 1011 | −kms_ccs@pipe-H-missing-ccs-buffer-y-tiled-gen12-rc-ccs | |
| 1012 | −kms_ccs@pipe-H-missing-ccs-buffer-y-tiled-gen12-rc-ccs-cc | |
| 1013 | −kms_ccs@pipe-H-missing-ccs-buffer-y-tiled-gen12-mc-ccs | |
| 1014 | −kms_ccs@pipe-H-missing-ccs-buffer-4-tiled-mtl-rc-ccs | |
| 1015 | −kms_ccs@pipe-H-missing-ccs-buffer-4-tiled-mtl-mc-ccs | |
| 1016 | −kms_ccs@pipe-H-missing-ccs-buffer-4-tiled-mtl-rc-ccs-cc | |
| 1017 | −kms_ccs@pipe-H-ccs-on-another-bo-y-tiled-ccs | |
| 1018 | −kms_ccs@pipe-H-ccs-on-another-bo-yf-tiled-ccs | |
| 1019 | −kms_ccs@pipe-H-ccs-on-another-bo-y-tiled-gen12-rc-ccs | |
| 1020 | −kms_ccs@pipe-H-ccs-on-another-bo-y-tiled-gen12-rc-ccs-cc | |
| 1021 | −kms_ccs@pipe-H-ccs-on-another-bo-y-tiled-gen12-mc-ccs | |
| 1022 | −kms_ccs@pipe-H-ccs-on-another-bo-4-tiled-mtl-rc-ccs | |
| 1023 | −kms_ccs@pipe-H-ccs-on-another-bo-4-tiled-mtl-mc-ccs | |
| 1024 | −kms_ccs@pipe-H-ccs-on-another-bo-4-tiled-mtl-rc-ccs-cc | |
| 1025 | −kms_ccs@pipe-H-bad-aux-stride-y-tiled-ccs | |
| 1026 | −kms_ccs@pipe-H-bad-aux-stride-yf-tiled-ccs | |
| 1027 | −kms_ccs@pipe-H-bad-aux-stride-y-tiled-gen12-rc-ccs | |
| 1028 | −kms_ccs@pipe-H-bad-aux-stride-y-tiled-gen12-rc-ccs-cc | |
| 1029 | −kms_ccs@pipe-H-bad-aux-stride-y-tiled-gen12-mc-ccs | |
| 1030 | −kms_ccs@pipe-H-bad-aux-stride-4-tiled-mtl-rc-ccs | |
| 1031 | −kms_ccs@pipe-H-bad-aux-stride-4-tiled-mtl-mc-ccs | |
| 1032 | −kms_ccs@pipe-H-bad-aux-stride-4-tiled-mtl-rc-ccs-cc | |
| 1033 | −kms_ccs@pipe-H-crc-sprite-planes-basic-y-tiled-ccs | |
| 1034 | −kms_ccs@pipe-H-crc-sprite-planes-basic-yf-tiled-ccs | |
| 1035 | −kms_ccs@pipe-H-crc-sprite-planes-basic-y-tiled-gen12-rc-ccs | |
| 1036 | −kms_ccs@pipe-H-crc-sprite-planes-basic-y-tiled-gen12-rc-ccs-cc | |
| 1037 | −kms_ccs@pipe-H-crc-sprite-planes-basic-y-tiled-gen12-mc-ccs | |
| 1038 | −kms_ccs@pipe-H-crc-sprite-planes-basic-4-tiled-dg2-rc-ccs | |
| 1039 | −kms_ccs@pipe-H-crc-sprite-planes-basic-4-tiled-dg2-mc-ccs | |
| 1040 | −kms_ccs@pipe-H-crc-sprite-planes-basic-4-tiled-dg2-rc-ccs-cc | |
| 1041 | −kms_ccs@pipe-H-crc-sprite-planes-basic-4-tiled-mtl-rc-ccs | |
| 1042 | −kms_ccs@pipe-H-crc-sprite-planes-basic-4-tiled-mtl-mc-ccs | |
| 1043 | −kms_ccs@pipe-H-crc-sprite-planes-basic-4-tiled-mtl-rc-ccs-cc | |
| 1044 | −kms_cdclk@plane-scaling | |
| 1045 | −kms_cdclk@mode-transition | |
| 1046 | −kms_cdclk@mode-transition-all-outputs | |
| 1047 | −kms_color@degamma | |
| 1048 | −kms_color@gamma | |
| 1049 | −kms_color@legacy-gamma | |
| 1050 | −kms_color@legacy-gamma-reset | |
| 1051 | −kms_color@ctm-red-to-blue | |
| 1052 | −kms_color@ctm-green-to-red | |
| 1053 | −kms_color@ctm-blue-to-red | |
| 1054 | −kms_color@ctm-max | |
| 1055 | −kms_color@ctm-negative | |
| 1056 | −kms_color@ctm-0-25 | |
| 1057 | −kms_color@ctm-0-50 | |
| 1058 | −kms_color@ctm-0-75 | |
| 1059 | −kms_color@ctm-signed | |
| 1060 | −kms_color@deep-color | |
| 1061 | −kms_color@invalid-gamma-lut-sizes | |
| 1062 | −kms_color@invalid-degamma-lut-sizes | |
| 1063 | −kms_color@invalid-ctm-matrix-sizes | |
| 1064 | −kms_concurrent@multi-plane-atomic-lowres | |
| 1065 | −kms_content_protection@legacy | |
| 1066 | −kms_content_protection@atomic | |
| 1067 | −kms_content_protection@atomic-dpms | |
| 1068 | −kms_content_protection@lic | |
| 1069 | −kms_content_protection@type1 | |
| 1070 | −kms_content_protection@mei-interface | |
| 1071 | −kms_content_protection@content-type-change | |
| 1072 | −kms_content_protection@uevent | |
| 1073 | −kms_content_protection@srm | |
| 1074 | −kms_content_protection@dp-mst-type-0 | |
| 1075 | −kms_content_protection@dp-mst-lic-type-0 | |
| 1076 | −kms_content_protection@dp-mst-type-1 | |
| 1077 | −kms_content_protection@dp-mst-lic-type-1 | |
| 1078 | −kms_cursor_crc@cursor-size-change | |
| 1079 | −kms_cursor_crc@cursor-alpha-opaque | |
| 1080 | −kms_cursor_crc@cursor-alpha-transparent | |
| 1081 | −kms_cursor_crc@cursor-dpms | |
| 1082 | −kms_cursor_crc@cursor-suspend | |
| 1083 | −kms_cursor_crc@cursor-onscreen-32x32 | |
| 1084 | −kms_cursor_crc@cursor-offscreen-32x32 | |
| 1085 | −kms_cursor_crc@cursor-sliding-32x32 | |
| 1086 | −kms_cursor_crc@cursor-random-32x32 | |
| 1087 | −kms_cursor_crc@cursor-rapid-movement-32x32 | |
| 1088 | −kms_cursor_crc@cursor-onscreen-32x10 | |
| 1089 | −kms_cursor_crc@cursor-offscreen-32x10 | |
| 1090 | −kms_cursor_crc@cursor-sliding-32x10 | |
| 1091 | −kms_cursor_crc@cursor-random-32x10 | |
| 1092 | −kms_cursor_crc@cursor-rapid-movement-32x10 | |
| 1093 | −kms_cursor_crc@cursor-onscreen-64x64 | |
| 1094 | −kms_cursor_crc@cursor-offscreen-64x64 | |
| 1095 | −kms_cursor_crc@cursor-sliding-64x64 | |
| 1096 | −kms_cursor_crc@cursor-random-64x64 | |
| 1097 | −kms_cursor_crc@cursor-rapid-movement-64x64 | |
| 1098 | −kms_cursor_crc@cursor-onscreen-64x21 | |
| 1099 | −kms_cursor_crc@cursor-offscreen-64x21 | |
| 1100 | −kms_cursor_crc@cursor-sliding-64x21 | |
| 1101 | −kms_cursor_crc@cursor-random-64x21 | |
| 1102 | −kms_cursor_crc@cursor-rapid-movement-64x21 | |
| 1103 | −kms_cursor_crc@cursor-onscreen-128x128 | |
| 1104 | −kms_cursor_crc@cursor-offscreen-128x128 | |
| 1105 | −kms_cursor_crc@cursor-sliding-128x128 | |
| 1106 | −kms_cursor_crc@cursor-random-128x128 | |
| 1107 | −kms_cursor_crc@cursor-rapid-movement-128x128 | |
| 1108 | −kms_cursor_crc@cursor-onscreen-128x42 | |
| 1109 | −kms_cursor_crc@cursor-offscreen-128x42 | |
| 1110 | −kms_cursor_crc@cursor-sliding-128x42 | |
| 1111 | −kms_cursor_crc@cursor-random-128x42 | |
| 1112 | −kms_cursor_crc@cursor-rapid-movement-128x42 | |
| 1113 | −kms_cursor_crc@cursor-onscreen-256x256 | |
| 1114 | −kms_cursor_crc@cursor-offscreen-256x256 | |
| 1115 | −kms_cursor_crc@cursor-sliding-256x256 | |
| 1116 | −kms_cursor_crc@cursor-random-256x256 | |
| 1117 | −kms_cursor_crc@cursor-rapid-movement-256x256 | |
| 1118 | −kms_cursor_crc@cursor-onscreen-256x85 | |
| 1119 | −kms_cursor_crc@cursor-offscreen-256x85 | |
| 1120 | −kms_cursor_crc@cursor-sliding-256x85 | |
| 1121 | −kms_cursor_crc@cursor-random-256x85 | |
| 1122 | −kms_cursor_crc@cursor-rapid-movement-256x85 | |
| 1123 | −kms_cursor_crc@cursor-onscreen-512x512 | |
| 1124 | −kms_cursor_crc@cursor-offscreen-512x512 | |
| 1125 | −kms_cursor_crc@cursor-sliding-512x512 | |
| 1126 | −kms_cursor_crc@cursor-random-512x512 | |
| 1127 | −kms_cursor_crc@cursor-rapid-movement-512x512 | |
| 1128 | −kms_cursor_crc@cursor-onscreen-512x170 | |
| 1129 | −kms_cursor_crc@cursor-offscreen-512x170 | |
| 1130 | −kms_cursor_crc@cursor-sliding-512x170 | |
| 1131 | −kms_cursor_crc@cursor-random-512x170 | |
| 1132 | −kms_cursor_crc@cursor-rapid-movement-512x170 | |
| 1133 | −kms_cursor_crc@cursor-onscreen-max-size | |
| 1134 | −kms_cursor_crc@cursor-offscreen-max-size | |
| 1135 | −kms_cursor_crc@cursor-sliding-max-size | |
| 1136 | −kms_cursor_crc@cursor-random-max-size | |
| 1137 | −kms_cursor_crc@cursor-rapid-movement-max-size | |
| 1138 | −kms_cursor_legacy@single-bo | |
| 1139 | −kms_cursor_legacy@single-move | |
| 1140 | −kms_cursor_legacy@forked-bo | |
| 1141 | −kms_cursor_legacy@forked-move | |
| 1142 | −kms_cursor_legacy@torture-bo | |
| 1143 | −kms_cursor_legacy@torture-move | |
| 1144 | −kms_cursor_legacy@nonblocking-modeset-vs-cursor-atomic | |
| 1145 | −kms_cursor_legacy@long-nonblocking-modeset-vs-cursor-atomic | |
| 1146 | −kms_cursor_legacy@2x-flip-vs-cursor-legacy | |
| 1147 | −kms_cursor_legacy@2x-flip-vs-cursor-atomic | |
| 1148 | −kms_cursor_legacy@2x-long-flip-vs-cursor-legacy | |
| 1149 | −kms_cursor_legacy@2x-long-flip-vs-cursor-atomic | |
| 1150 | −kms_cursor_legacy@2x-nonblocking-modeset-vs-cursor-atomic | |
| 1151 | −kms_cursor_legacy@2x-long-nonblocking-modeset-vs-cursor-atomic | |
| 1152 | −kms_cursor_legacy@2x-cursor-vs-flip-legacy | |
| 1153 | −kms_cursor_legacy@2x-long-cursor-vs-flip-legacy | |
| 1154 | −kms_cursor_legacy@2x-cursor-vs-flip-atomic | |
| 1155 | −kms_cursor_legacy@2x-long-cursor-vs-flip-atomic | |
| 1156 | −kms_cursor_legacy@flip-vs-cursor-crc-legacy | |
| 1157 | −kms_cursor_legacy@flip-vs-cursor-crc-atomic | |
| 1158 | −kms_cursor_legacy@flip-vs-cursor-busy-crc-legacy | |
| 1159 | −kms_cursor_legacy@flip-vs-cursor-busy-crc-atomic | |
| 1160 | −kms_cursor_legacy@basic-flip-before-cursor-legacy | |
| 1161 | −kms_cursor_legacy@basic-busy-flip-before-cursor-legacy | |
| 1162 | −kms_cursor_legacy@basic-flip-after-cursor-legacy | |
| 1163 | −kms_cursor_legacy@basic-flip-before-cursor-varying-size | |
| 1164 | −kms_cursor_legacy@basic-busy-flip-before-cursor-varying-size | |
| 1165 | −kms_cursor_legacy@basic-flip-after-cursor-varying-size | |
| 1166 | −kms_cursor_legacy@short-flip-before-cursor-toggle | |
| 1167 | −kms_cursor_legacy@short-busy-flip-before-cursor-toggle | |
| 1168 | −kms_cursor_legacy@short-flip-after-cursor-toggle | |
| 1169 | −kms_cursor_legacy@basic-flip-before-cursor-atomic | |
| 1170 | −kms_cursor_legacy@basic-busy-flip-before-cursor-atomic | |
| 1171 | −kms_cursor_legacy@basic-flip-after-cursor-atomic | |
| 1172 | −kms_cursor_legacy@short-flip-before-cursor-atomic-transitions | |
| 1173 | −kms_cursor_legacy@short-busy-flip-before-cursor-atomic-transitions | |
| 1174 | −kms_cursor_legacy@short-flip-after-cursor-atomic-transitions | |
| 1175 | −kms_cursor_legacy@short-flip-before-cursor-atomic-transitions-varying-size | |
| 1176 | −kms_cursor_legacy@short-busy-flip-before-cursor-atomic-transitions-varying-size | |
| 1177 | −kms_cursor_legacy@short-flip-after-cursor-atomic-transitions-varying-size | |
| 1178 | −kms_cursor_legacy@cursor-vs-flip-legacy | |
| 1179 | −kms_cursor_legacy@flip-vs-cursor-legacy | |
| 1180 | −kms_cursor_legacy@cursorA-vs-flipA-legacy | |
| 1181 | −kms_cursor_legacy@cursorA-vs-flipB-legacy | |
| 1182 | −kms_cursor_legacy@cursorB-vs-flipA-legacy | |
| 1183 | −kms_cursor_legacy@cursorB-vs-flipB-legacy | |
| 1184 | −kms_cursor_legacy@cursor-vs-flip-varying-size | |
| 1185 | −kms_cursor_legacy@flip-vs-cursor-varying-size | |
| 1186 | −kms_cursor_legacy@cursorA-vs-flipA-varying-size | |
| 1187 | −kms_cursor_legacy@cursorA-vs-flipB-varying-size | |
| 1188 | −kms_cursor_legacy@cursorB-vs-flipA-varying-size | |
| 1189 | −kms_cursor_legacy@cursorB-vs-flipB-varying-size | |
| 1190 | −kms_cursor_legacy@cursor-vs-flip-toggle | |
| 1191 | −kms_cursor_legacy@flip-vs-cursor-toggle | |
| 1192 | −kms_cursor_legacy@cursorA-vs-flipA-toggle | |
| 1193 | −kms_cursor_legacy@cursorA-vs-flipB-toggle | |
| 1194 | −kms_cursor_legacy@cursorB-vs-flipA-toggle | |
| 1195 | −kms_cursor_legacy@cursorB-vs-flipB-toggle | |
| 1196 | −kms_cursor_legacy@cursor-vs-flip-atomic | |
| 1197 | −kms_cursor_legacy@flip-vs-cursor-atomic | |
| 1198 | −kms_cursor_legacy@cursorA-vs-flipA-atomic | |
| 1199 | −kms_cursor_legacy@cursorA-vs-flipB-atomic | |
| 1200 | −kms_cursor_legacy@cursorB-vs-flipA-atomic | |
| 1201 | −kms_cursor_legacy@cursorB-vs-flipB-atomic | |
| 1202 | −kms_cursor_legacy@cursor-vs-flip-atomic-transitions | |
| 1203 | −kms_cursor_legacy@flip-vs-cursor-atomic-transitions | |
| 1204 | −kms_cursor_legacy@cursorA-vs-flipA-atomic-transitions | |
| 1205 | −kms_cursor_legacy@cursorA-vs-flipB-atomic-transitions | |
| 1206 | −kms_cursor_legacy@cursorB-vs-flipA-atomic-transitions | |
| 1207 | −kms_cursor_legacy@cursorB-vs-flipB-atomic-transitions | |
| 1208 | −kms_cursor_legacy@cursor-vs-flip-atomic-transitions-varying-size | |
| 1209 | −kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size | |
| 1210 | −kms_cursor_legacy@cursorA-vs-flipA-atomic-transitions-varying-size | |
| 1211 | −kms_cursor_legacy@cursorA-vs-flipB-atomic-transitions-varying-size | |
| 1212 | −kms_cursor_legacy@cursorB-vs-flipA-atomic-transitions-varying-size | |
| 1213 | −kms_cursor_legacy@cursorB-vs-flipB-atomic-transitions-varying-size | |
| 1214 | −kms_dither@fb-8bpc-vs-panel-6bpc | |
| 1215 | −kms_dither@fb-8bpc-vs-panel-8bpc | |
| 1216 | −kms_dp_aux_dev | |
| 1217 | −kms_tiled_display@basic-test-pattern | |
| 1218 | −kms_tiled_display@basic-test-pattern-with-chamelium | |
| 1219 | −kms_draw_crc@draw-method-mmap-cpu | |
| 1220 | −kms_draw_crc@draw-method-mmap-gtt | |
| 1221 | −kms_draw_crc@draw-method-mmap-wc | |
| 1222 | −kms_draw_crc@draw-method-pwrite | |
| 1223 | −kms_draw_crc@draw-method-blt | |
| 1224 | −kms_draw_crc@draw-method-render | |
| 1225 | −kms_draw_crc@fill-fb | |
| 1226 | −kms_dsc@dsc-basic | |
| 1227 | −kms_dsc@dsc-with-formats | |
| 1228 | −kms_dsc@dsc-with-bpc | |
| 1229 | −kms_dsc@dsc-with-bpc-formats | |
| 1230 | −kms_dsc@dsc-with-output-formats | |
| 1231 | −kms_fbcon_fbt@fbc | |
| 1232 | −kms_fbcon_fbt@psr | |
| 1233 | −kms_fbcon_fbt@fbc-suspend | |
| 1234 | −kms_fbcon_fbt@psr-suspend | |
| 1235 | −kms_fence_pin_leak | |
| 1236 | −kms_flip@nonblocking-read | |
| 1237 | −kms_flip@wf_vblank-ts-check | |
| 1238 | −kms_flip@2x-wf_vblank-ts-check | |
| 1239 | −kms_flip@blocking-wf_vblank | |
| 1240 | −kms_flip@2x-blocking-wf_vblank | |
| 1241 | −kms_flip@absolute-wf_vblank | |
| 1242 | −kms_flip@2x-absolute-wf_vblank | |
| 1243 | −kms_flip@blocking-absolute-wf_vblank | |
| 1244 | −kms_flip@2x-blocking-absolute-wf_vblank | |
| 1245 | −kms_flip@basic-plain-flip | |
| 1246 | −kms_flip@2x-plain-flip | |
| 1247 | −kms_flip@busy-flip | |
| 1248 | −kms_flip@2x-busy-flip | |
| 1249 | −kms_flip@flip-vs-fences | |
| 1250 | −kms_flip@2x-flip-vs-fences | |
| 1251 | −kms_flip@plain-flip-ts-check | |
| 1252 | −kms_flip@2x-plain-flip-ts-check | |
| 1253 | −kms_flip@plain-flip-fb-recreate | |
| 1254 | −kms_flip@2x-plain-flip-fb-recreate | |
| 1255 | −kms_flip@flip-vs-rmfb | |
| 1256 | −kms_flip@2x-flip-vs-rmfb | |
| 1257 | −kms_flip@basic-flip-vs-dpms | |
| 1258 | −kms_flip@2x-flip-vs-dpms | |
| 1259 | −kms_flip@flip-vs-panning | |
| 1260 | −kms_flip@2x-flip-vs-panning | |
| 1261 | −kms_flip@basic-flip-vs-modeset | |
| 1262 | −kms_flip@2x-flip-vs-modeset | |
| 1263 | −kms_flip@flip-vs-expired-vblank | |
| 1264 | −kms_flip@2x-flip-vs-expired-vblank | |
| 1265 | −kms_flip@flip-vs-absolute-wf_vblank | |
| 1266 | −kms_flip@2x-flip-vs-absolute-wf_vblank | |
| 1267 | −kms_flip@basic-flip-vs-wf_vblank | |
| 1268 | −kms_flip@2x-flip-vs-wf_vblank | |
| 1269 | −kms_flip@flip-vs-blocking-wf-vblank | |
| 1270 | −kms_flip@2x-flip-vs-blocking-wf-vblank | |
| 1271 | −kms_flip@flip-vs-modeset-vs-hang | |
| 1272 | −kms_flip@2x-flip-vs-modeset-vs-hang | |
| 1273 | −kms_flip@flip-vs-panning-vs-hang | |
| 1274 | −kms_flip@2x-flip-vs-panning-vs-hang | |
| 1275 | −kms_flip@flip-vs-dpms-off-vs-modeset | |
| 1276 | −kms_flip@2x-flip-vs-dpms-off-vs-modeset | |
| 1277 | −kms_flip@single-buffer-flip-vs-dpms-off-vs-modeset | |
| 1278 | −kms_flip@2x-single-buffer-flip-vs-dpms-off-vs-modeset | |
| 1279 | −kms_flip@dpms-off-confusion | |
| 1280 | −kms_flip@nonexisting-fb | |
| 1281 | −kms_flip@2x-nonexisting-fb | |
| 1282 | −kms_flip@dpms-vs-vblank-race | |
| 1283 | −kms_flip@2x-dpms-vs-vblank-race | |
| 1284 | −kms_flip@modeset-vs-vblank-race | |
| 1285 | −kms_flip@2x-modeset-vs-vblank-race | |
| 1286 | −kms_flip@bo-too-big | |
| 1287 | −kms_flip@flip-vs-suspend | |
| 1288 | −kms_flip@2x-flip-vs-suspend | |
| 1289 | −kms_flip@wf_vblank-ts-check-interruptible | |
| 1290 | −kms_flip@2x-wf_vblank-ts-check-interruptible | |
| 1291 | −kms_flip@absolute-wf_vblank-interruptible | |
| 1292 | −kms_flip@2x-absolute-wf_vblank-interruptible | |
| 1293 | −kms_flip@blocking-absolute-wf_vblank-interruptible | |
| 1294 | −kms_flip@2x-blocking-absolute-wf_vblank-interruptible | |
| 1295 | −kms_flip@plain-flip-interruptible | |
| 1296 | −kms_flip@2x-plain-flip-interruptible | |
| 1297 | −kms_flip@flip-vs-fences-interruptible | |
| 1298 | −kms_flip@2x-flip-vs-fences-interruptible | |
| 1299 | −kms_flip@plain-flip-ts-check-interruptible | |
| 1300 | −kms_flip@2x-plain-flip-ts-check-interruptible | |
| 1301 | −kms_flip@plain-flip-fb-recreate-interruptible | |
| 1302 | −kms_flip@2x-plain-flip-fb-recreate-interruptible | |
| 1303 | −kms_flip@flip-vs-rmfb-interruptible | |
| 1304 | −kms_flip@2x-flip-vs-rmfb-interruptible | |
| 1305 | −kms_flip@flip-vs-panning-interruptible | |
| 1306 | −kms_flip@2x-flip-vs-panning-interruptible | |
| 1307 | −kms_flip@flip-vs-expired-vblank-interruptible | |
| 1308 | −kms_flip@2x-flip-vs-expired-vblank-interruptible | |
| 1309 | −kms_flip@flip-vs-absolute-wf_vblank-interruptible | |
| 1310 | −kms_flip@2x-flip-vs-absolute-wf_vblank-interruptible | |
| 1311 | −kms_flip@flip-vs-wf_vblank-interruptible | |
| 1312 | −kms_flip@2x-flip-vs-wf_vblank-interruptible | |
| 1313 | −kms_flip@flip-vs-dpms-off-vs-modeset-interruptible | |
| 1314 | −kms_flip@2x-flip-vs-dpms-off-vs-modeset-interruptible | |
| 1315 | −kms_flip@single-buffer-flip-vs-dpms-off-vs-modeset-interruptible | |
| 1316 | −kms_flip@2x-single-buffer-flip-vs-dpms-off-vs-modeset-interruptible | |
| 1317 | −kms_flip@dpms-off-confusion-interruptible | |
| 1318 | −kms_flip@nonexisting-fb-interruptible | |
| 1319 | −kms_flip@2x-nonexisting-fb-interruptible | |
| 1320 | −kms_flip@dpms-vs-vblank-race-interruptible | |
| 1321 | −kms_flip@2x-dpms-vs-vblank-race-interruptible | |
| 1322 | −kms_flip@modeset-vs-vblank-race-interruptible | |
| 1323 | −kms_flip@2x-modeset-vs-vblank-race-interruptible | |
| 1324 | −kms_flip@bo-too-big-interruptible | |
| 1325 | −kms_flip@flip-vs-suspend-interruptible | |
| 1326 | −kms_flip@2x-flip-vs-suspend-interruptible | |
| 1327 | −kms_flip_event_leak@basic | |
| 1328 | −kms_flip_scaled_crc@flip-32bpp-ytile-to-64bpp-ytile-downscaling | |
| 1329 | −kms_flip_scaled_crc@flip-32bpp-yftile-to-64bpp-yftile-downscaling | |
| 1330 | −kms_flip_scaled_crc@flip-32bpp-xtile-to-64bpp-xtile-downscaling | |
| 1331 | −kms_flip_scaled_crc@flip-32bpp-4tile-to-64bpp-4tile-downscaling | |
| 1332 | −kms_flip_scaled_crc@flip-32bpp-linear-to-64bpp-linear-downscaling | |
| 1333 | −kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytile-downscaling | |
| 1334 | −kms_flip_scaled_crc@flip-64bpp-yftile-to-32bpp-yftile-downscaling | |
| 1335 | −kms_flip_scaled_crc@flip-64bpp-xtile-to-32bpp-xtile-downscaling | |
| 1336 | −kms_flip_scaled_crc@flip-64bpp-4tile-to-32bpp-4tile-downscaling | |
| 1337 | −kms_flip_scaled_crc@flip-64bpp-linear-to-32bpp-linear-downscaling | |
| 1338 | −kms_flip_scaled_crc@flip-64bpp-ytile-to-16bpp-ytile-downscaling | |
| 1339 | −kms_flip_scaled_crc@flip-64bpp-yftile-to-16bpp-yftile-downscaling | |
| 1340 | −kms_flip_scaled_crc@flip-64bpp-xtile-to-16bpp-xtile-downscaling | |
| 1341 | −kms_flip_scaled_crc@flip-64bpp-4tile-to-16bpp-4tile-downscaling | |
| 1342 | −kms_flip_scaled_crc@flip-64bpp-linear-to-16bpp-linear-downscaling | |
| 1343 | −kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile-downscaling | |
| 1344 | −kms_flip_scaled_crc@flip-32bpp-yftileccs-to-64bpp-yftile-downscaling | |
| 1345 | −kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytilegen12rcccs-downscaling | |
| 1346 | −kms_flip_scaled_crc@flip-32bpp-4tile-to-32bpp-4tiledg2rcccs-downscaling | |
| 1347 | −kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs-downscaling | |
| 1348 | −kms_flip_scaled_crc@flip-32bpp-yftile-to-32bpp-yftileccs-downscaling | |
| 1349 | −kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilercccs-downscaling | |
| 1350 | −kms_flip_scaled_crc@flip-64bpp-4tile-to-32bpp-4tiledg2rcccs-downscaling | |
| 1351 | −kms_flip_scaled_crc@flip-32bpp-ytile-to-64bpp-ytile-upscaling | |
| 1352 | −kms_flip_scaled_crc@flip-32bpp-yftile-to-64bpp-yftile-upscaling | |
| 1353 | −kms_flip_scaled_crc@flip-32bpp-xtile-to-64bpp-xtile-upscaling | |
| 1354 | −kms_flip_scaled_crc@flip-32bpp-4tile-to-64bpp-4tile-upscaling | |
| 1355 | −kms_flip_scaled_crc@flip-32bpp-linear-to-64bpp-linear-upscaling | |
| 1356 | −kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytile-upscaling | |
| 1357 | −kms_flip_scaled_crc@flip-64bpp-yftile-to-32bpp-yftile-upscaling | |
| 1358 | −kms_flip_scaled_crc@flip-64bpp-xtile-to-32bpp-xtile-upscaling | |
| 1359 | −kms_flip_scaled_crc@flip-64bpp-4tile-to-32bpp-4tile-upscaling | |
| 1360 | −kms_flip_scaled_crc@flip-64bpp-linear-to-32bpp-linear-upscaling | |
| 1361 | −kms_flip_scaled_crc@flip-64bpp-ytile-to-16bpp-ytile-upscaling | |
| 1362 | −kms_flip_scaled_crc@flip-64bpp-yftile-to-16bpp-yftile-upscaling | |
| 1363 | −kms_flip_scaled_crc@flip-64bpp-xtile-to-16bpp-xtile-upscaling | |
| 1364 | −kms_flip_scaled_crc@flip-64bpp-4tile-to-16bpp-4tile-upscaling | |
| 1365 | −kms_flip_scaled_crc@flip-64bpp-linear-to-16bpp-linear-upscaling | |
| 1366 | −kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile-upscaling | |
| 1367 | −kms_flip_scaled_crc@flip-32bpp-yftileccs-to-64bpp-yftile-upscaling | |
| 1368 | −kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytilegen12rcccs-upscaling | |
| 1369 | −kms_flip_scaled_crc@flip-32bpp-4tile-to-32bpp-4tiledg2rcccs-upscaling | |
| 1370 | −kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs-upscaling | |
| 1371 | −kms_flip_scaled_crc@flip-32bpp-yftile-to-32bpp-yftileccs-upscaling | |
| 1372 | −kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilegen12rcccs-upscaling | |
| 1373 | −kms_flip_scaled_crc@flip-64bpp-4tile-to-32bpp-4tiledg2rcccs-upscaling | |
| 1374 | −kms_force_connector_basic@force-load-detect | |
| 1375 | −kms_force_connector_basic@force-connector-state | |
| 1376 | −kms_force_connector_basic@force-edid | |
| 1377 | −kms_force_connector_basic@prune-stale-modes | |
| 1378 | −kms_frontbuffer_tracking@fbc-1p-rte | |
| 1379 | −kms_frontbuffer_tracking@fbc-2p-rte | |
| 1380 | −kms_frontbuffer_tracking@psr-1p-rte | |
| 1381 | −kms_frontbuffer_tracking@psr-2p-rte | |
| 1382 | −kms_frontbuffer_tracking@fbcpsr-1p-rte | |
| 1383 | −kms_frontbuffer_tracking@fbcpsr-2p-rte | |
| 1384 | −kms_frontbuffer_tracking@drrs-1p-rte | |
| 1385 | −kms_frontbuffer_tracking@drrs-2p-rte | |
| 1386 | −kms_frontbuffer_tracking@fbcdrrs-1p-rte | |
| 1387 | −kms_frontbuffer_tracking@fbcdrrs-2p-rte | |
| 1388 | −kms_frontbuffer_tracking@psrdrrs-1p-rte | |
| 1389 | −kms_frontbuffer_tracking@psrdrrs-2p-rte | |
| 1390 | −kms_frontbuffer_tracking@fbcpsrdrrs-1p-rte | |
| 1391 | −kms_frontbuffer_tracking@fbcpsrdrrs-2p-rte | |
| 1392 | −kms_frontbuffer_tracking@fbc-1p-primscrn-pri-indfb-draw-mmap-cpu | |
| 1393 | −kms_frontbuffer_tracking@fbc-1p-primscrn-pri-indfb-draw-mmap-gtt | |
| 1394 | −kms_frontbuffer_tracking@fbc-1p-primscrn-pri-indfb-draw-mmap-wc | |
| 1395 | −kms_frontbuffer_tracking@fbc-1p-primscrn-pri-indfb-draw-pwrite | |
| 1396 | −kms_frontbuffer_tracking@fbc-1p-primscrn-pri-indfb-draw-blt | |
| 1397 | −kms_frontbuffer_tracking@fbc-1p-primscrn-pri-indfb-draw-render | |
| 1398 | −kms_frontbuffer_tracking@fbc-1p-primscrn-pri-shrfb-draw-mmap-cpu | |
| 1399 | −kms_frontbuffer_tracking@fbc-1p-primscrn-pri-shrfb-draw-mmap-gtt | |
| 1400 | −kms_frontbuffer_tracking@fbc-1p-primscrn-pri-shrfb-draw-mmap-wc | |
| 1401 | −kms_frontbuffer_tracking@fbc-1p-primscrn-pri-shrfb-draw-pwrite | |
| 1402 | −kms_frontbuffer_tracking@fbc-1p-primscrn-pri-shrfb-draw-blt | |
| 1403 | −kms_frontbuffer_tracking@fbc-1p-primscrn-pri-shrfb-draw-render | |
| 1404 | −kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-mmap-cpu | |
| 1405 | −kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-mmap-gtt | |
| 1406 | −kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-mmap-wc | |
| 1407 | −kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-pwrite | |
| 1408 | −kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-blt | |
| 1409 | −kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-render | |
| 1410 | −kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-mmap-cpu | |
| 1411 | −kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-mmap-gtt | |
| 1412 | −kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-mmap-wc | |
| 1413 | −kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-pwrite | |
| 1414 | −kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-blt | |
| 1415 | −kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-render | |
| 1416 | −kms_frontbuffer_tracking@fbc-1p-offscren-pri-indfb-draw-mmap-cpu | |
| 1417 | −kms_frontbuffer_tracking@fbc-1p-offscren-pri-indfb-draw-mmap-gtt | |
| 1418 | −kms_frontbuffer_tracking@fbc-1p-offscren-pri-indfb-draw-mmap-wc | |
| 1419 | −kms_frontbuffer_tracking@fbc-1p-offscren-pri-indfb-draw-pwrite | |
| 1420 | −kms_frontbuffer_tracking@fbc-1p-offscren-pri-indfb-draw-blt | |
| 1421 | −kms_frontbuffer_tracking@fbc-1p-offscren-pri-indfb-draw-render | |
| 1422 | −kms_frontbuffer_tracking@fbc-1p-offscren-pri-shrfb-draw-mmap-cpu | |
| 1423 | −kms_frontbuffer_tracking@fbc-1p-offscren-pri-shrfb-draw-mmap-gtt | |
| 1424 | −kms_frontbuffer_tracking@fbc-1p-offscren-pri-shrfb-draw-mmap-wc | |
| 1425 | −kms_frontbuffer_tracking@fbc-1p-offscren-pri-shrfb-draw-pwrite | |
| 1426 | −kms_frontbuffer_tracking@fbc-1p-offscren-pri-shrfb-draw-blt | |
| 1427 | −kms_frontbuffer_tracking@fbc-1p-offscren-pri-shrfb-draw-render | |
| 1428 | −kms_frontbuffer_tracking@fbc-2p-primscrn-pri-indfb-draw-mmap-cpu | |
| 1429 | −kms_frontbuffer_tracking@fbc-2p-primscrn-pri-indfb-draw-mmap-gtt | |
| 1430 | −kms_frontbuffer_tracking@fbc-2p-primscrn-pri-indfb-draw-mmap-wc | |
| 1431 | −kms_frontbuffer_tracking@fbc-2p-primscrn-pri-indfb-draw-pwrite | |
| 1432 | −kms_frontbuffer_tracking@fbc-2p-primscrn-pri-indfb-draw-blt | |
| 1433 | −kms_frontbuffer_tracking@fbc-2p-primscrn-pri-indfb-draw-render | |
| 1434 | −kms_frontbuffer_tracking@fbc-2p-primscrn-pri-shrfb-draw-mmap-cpu | |
| 1435 | −kms_frontbuffer_tracking@fbc-2p-primscrn-pri-shrfb-draw-mmap-gtt | |
| 1436 | −kms_frontbuffer_tracking@fbc-2p-primscrn-pri-shrfb-draw-mmap-wc | |
| 1437 | −kms_frontbuffer_tracking@fbc-2p-primscrn-pri-shrfb-draw-pwrite | |
| 1438 | −kms_frontbuffer_tracking@fbc-2p-primscrn-pri-shrfb-draw-blt | |
| 1439 | −kms_frontbuffer_tracking@fbc-2p-primscrn-pri-shrfb-draw-render | |
| 1440 | −kms_frontbuffer_tracking@fbc-2p-primscrn-cur-indfb-draw-mmap-cpu | |
| 1441 | −kms_frontbuffer_tracking@fbc-2p-primscrn-cur-indfb-draw-mmap-gtt | |
| 1442 | −kms_frontbuffer_tracking@fbc-2p-primscrn-cur-indfb-draw-mmap-wc | |
| 1443 | −kms_frontbuffer_tracking@fbc-2p-primscrn-cur-indfb-draw-pwrite | |
| 1444 | −kms_frontbuffer_tracking@fbc-2p-primscrn-cur-indfb-draw-blt | |
| 1445 | −kms_frontbuffer_tracking@fbc-2p-primscrn-cur-indfb-draw-render | |
| 1446 | −kms_frontbuffer_tracking@fbc-2p-primscrn-spr-indfb-draw-mmap-cpu | |
| 1447 | −kms_frontbuffer_tracking@fbc-2p-primscrn-spr-indfb-draw-mmap-gtt | |
| 1448 | −kms_frontbuffer_tracking@fbc-2p-primscrn-spr-indfb-draw-mmap-wc | |
| 1449 | −kms_frontbuffer_tracking@fbc-2p-primscrn-spr-indfb-draw-pwrite | |
| 1450 | −kms_frontbuffer_tracking@fbc-2p-primscrn-spr-indfb-draw-blt | |
| 1451 | −kms_frontbuffer_tracking@fbc-2p-primscrn-spr-indfb-draw-render | |
| 1452 | −kms_frontbuffer_tracking@fbc-2p-scndscrn-pri-indfb-draw-mmap-cpu | |
| 1453 | −kms_frontbuffer_tracking@fbc-2p-scndscrn-pri-indfb-draw-mmap-gtt | |
| 1454 | −kms_frontbuffer_tracking@fbc-2p-scndscrn-pri-indfb-draw-mmap-wc | |
| 1455 | −kms_frontbuffer_tracking@fbc-2p-scndscrn-pri-indfb-draw-pwrite | |
| 1456 | −kms_frontbuffer_tracking@fbc-2p-scndscrn-pri-indfb-draw-blt | |
| 1457 | −kms_frontbuffer_tracking@fbc-2p-scndscrn-pri-indfb-draw-render | |
| 1458 | −kms_frontbuffer_tracking@fbc-2p-scndscrn-pri-shrfb-draw-mmap-cpu | |
| 1459 | −kms_frontbuffer_tracking@fbc-2p-scndscrn-pri-shrfb-draw-mmap-gtt | |
| 1460 | −kms_frontbuffer_tracking@fbc-2p-scndscrn-pri-shrfb-draw-mmap-wc | |
| 1461 | −kms_frontbuffer_tracking@fbc-2p-scndscrn-pri-shrfb-draw-pwrite | |
| 1462 | −kms_frontbuffer_tracking@fbc-2p-scndscrn-pri-shrfb-draw-blt | |
| 1463 | −kms_frontbuffer_tracking@fbc-2p-scndscrn-pri-shrfb-draw-render | |
| 1464 | −kms_frontbuffer_tracking@fbc-2p-scndscrn-cur-indfb-draw-mmap-cpu | |
| 1465 | −kms_frontbuffer_tracking@fbc-2p-scndscrn-cur-indfb-draw-mmap-gtt | |
| 1466 | −kms_frontbuffer_tracking@fbc-2p-scndscrn-cur-indfb-draw-mmap-wc | |
| 1467 | −kms_frontbuffer_tracking@fbc-2p-scndscrn-cur-indfb-draw-pwrite | |
| 1468 | −kms_frontbuffer_tracking@fbc-2p-scndscrn-cur-indfb-draw-blt | |
| 1469 | −kms_frontbuffer_tracking@fbc-2p-scndscrn-cur-indfb-draw-render | |
| 1470 | −kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-draw-mmap-cpu | |
| 1471 | −kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-draw-mmap-gtt | |
| 1472 | −kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-draw-mmap-wc | |
| 1473 | −kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-draw-pwrite | |
| 1474 | −kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-draw-blt | |
| 1475 | −kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-draw-render | |
| 1476 | −kms_frontbuffer_tracking@psr-1p-primscrn-pri-indfb-draw-mmap-cpu | |
| 1477 | −kms_frontbuffer_tracking@psr-1p-primscrn-pri-indfb-draw-mmap-gtt | |
| 1478 | −kms_frontbuffer_tracking@psr-1p-primscrn-pri-indfb-draw-mmap-wc | |
| 1479 | −kms_frontbuffer_tracking@psr-1p-primscrn-pri-indfb-draw-pwrite | |
| 1480 | −kms_frontbuffer_tracking@psr-1p-primscrn-pri-indfb-draw-blt | |
| 1481 | −kms_frontbuffer_tracking@psr-1p-primscrn-pri-indfb-draw-render | |
| 1482 | −kms_frontbuffer_tracking@psr-1p-primscrn-pri-shrfb-draw-mmap-cpu | |
| 1483 | −kms_frontbuffer_tracking@psr-1p-primscrn-pri-shrfb-draw-mmap-gtt | |
| 1484 | −kms_frontbuffer_tracking@psr-1p-primscrn-pri-shrfb-draw-mmap-wc | |
| 1485 | −kms_frontbuffer_tracking@psr-1p-primscrn-pri-shrfb-draw-pwrite | |
| 1486 | −kms_frontbuffer_tracking@psr-1p-primscrn-pri-shrfb-draw-blt | |
| 1487 | −kms_frontbuffer_tracking@psr-1p-primscrn-pri-shrfb-draw-render | |
| 1488 | −kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-draw-mmap-cpu | |
| 1489 | −kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-draw-mmap-gtt | |
| 1490 | −kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-draw-mmap-wc | |
| 1491 | −kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-draw-pwrite | |
| 1492 | −kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-draw-blt | |
| 1493 | −kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-draw-render | |
| 1494 | −kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-draw-mmap-cpu | |
| 1495 | −kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-draw-mmap-gtt | |
| 1496 | −kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-draw-mmap-wc | |
| 1497 | −kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-draw-pwrite | |
| 1498 | −kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-draw-blt | |
| 1499 | −kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-draw-render | |
| 1500 | −kms_frontbuffer_tracking@psr-1p-offscren-pri-indfb-draw-mmap-cpu | |
| 1501 | −kms_frontbuffer_tracking@psr-1p-offscren-pri-indfb-draw-mmap-gtt | |
| 1502 | −kms_frontbuffer_tracking@psr-1p-offscren-pri-indfb-draw-mmap-wc | |
| 1503 | −kms_frontbuffer_tracking@psr-1p-offscren-pri-indfb-draw-pwrite | |
| 1504 | −kms_frontbuffer_tracking@psr-1p-offscren-pri-indfb-draw-blt | |
| 1505 | −kms_frontbuffer_tracking@psr-1p-offscren-pri-indfb-draw-render | |
| 1506 | −kms_frontbuffer_tracking@psr-1p-offscren-pri-shrfb-draw-mmap-cpu | |
| 1507 | −kms_frontbuffer_tracking@psr-1p-offscren-pri-shrfb-draw-mmap-gtt | |
| 1508 | −kms_frontbuffer_tracking@psr-1p-offscren-pri-shrfb-draw-mmap-wc | |
| 1509 | −kms_frontbuffer_tracking@psr-1p-offscren-pri-shrfb-draw-pwrite | |
| 1510 | −kms_frontbuffer_tracking@psr-1p-offscren-pri-shrfb-draw-blt | |
| 1511 | −kms_frontbuffer_tracking@psr-1p-offscren-pri-shrfb-draw-render | |
| 1512 | −kms_frontbuffer_tracking@psr-2p-primscrn-pri-indfb-draw-mmap-cpu | |
| 1513 | −kms_frontbuffer_tracking@psr-2p-primscrn-pri-indfb-draw-mmap-gtt | |
| 1514 | −kms_frontbuffer_tracking@psr-2p-primscrn-pri-indfb-draw-mmap-wc | |
| 1515 | −kms_frontbuffer_tracking@psr-2p-primscrn-pri-indfb-draw-pwrite | |
| 1516 | −kms_frontbuffer_tracking@psr-2p-primscrn-pri-indfb-draw-blt | |
| 1517 | −kms_frontbuffer_tracking@psr-2p-primscrn-pri-indfb-draw-render | |
| 1518 | −kms_frontbuffer_tracking@psr-2p-primscrn-pri-shrfb-draw-mmap-cpu | |
| 1519 | −kms_frontbuffer_tracking@psr-2p-primscrn-pri-shrfb-draw-mmap-gtt | |
| 1520 | −kms_frontbuffer_tracking@psr-2p-primscrn-pri-shrfb-draw-mmap-wc | |
| 1521 | −kms_frontbuffer_tracking@psr-2p-primscrn-pri-shrfb-draw-pwrite | |
| 1522 | −kms_frontbuffer_tracking@psr-2p-primscrn-pri-shrfb-draw-blt | |
| 1523 | −kms_frontbuffer_tracking@psr-2p-primscrn-pri-shrfb-draw-render | |
| 1524 | −kms_frontbuffer_tracking@psr-2p-primscrn-cur-indfb-draw-mmap-cpu | |
| 1525 | −kms_frontbuffer_tracking@psr-2p-primscrn-cur-indfb-draw-mmap-gtt | |
| 1526 | −kms_frontbuffer_tracking@psr-2p-primscrn-cur-indfb-draw-mmap-wc | |
| 1527 | −kms_frontbuffer_tracking@psr-2p-primscrn-cur-indfb-draw-pwrite | |
| 1528 | −kms_frontbuffer_tracking@psr-2p-primscrn-cur-indfb-draw-blt | |
| 1529 | −kms_frontbuffer_tracking@psr-2p-primscrn-cur-indfb-draw-render | |
| 1530 | −kms_frontbuffer_tracking@psr-2p-primscrn-spr-indfb-draw-mmap-cpu | |
| 1531 | −kms_frontbuffer_tracking@psr-2p-primscrn-spr-indfb-draw-mmap-gtt | |
| 1532 | −kms_frontbuffer_tracking@psr-2p-primscrn-spr-indfb-draw-mmap-wc | |
| 1533 | −kms_frontbuffer_tracking@psr-2p-primscrn-spr-indfb-draw-pwrite | |
| 1534 | −kms_frontbuffer_tracking@psr-2p-primscrn-spr-indfb-draw-blt | |
| 1535 | −kms_frontbuffer_tracking@psr-2p-primscrn-spr-indfb-draw-render | |
| 1536 | −kms_frontbuffer_tracking@psr-2p-scndscrn-pri-indfb-draw-mmap-cpu | |
| 1537 | −kms_frontbuffer_tracking@psr-2p-scndscrn-pri-indfb-draw-mmap-gtt | |
| 1538 | −kms_frontbuffer_tracking@psr-2p-scndscrn-pri-indfb-draw-mmap-wc | |
| 1539 | −kms_frontbuffer_tracking@psr-2p-scndscrn-pri-indfb-draw-pwrite | |
| 1540 | −kms_frontbuffer_tracking@psr-2p-scndscrn-pri-indfb-draw-blt | |
| 1541 | −kms_frontbuffer_tracking@psr-2p-scndscrn-pri-indfb-draw-render | |
| 1542 | −kms_frontbuffer_tracking@psr-2p-scndscrn-pri-shrfb-draw-mmap-cpu | |
| 1543 | −kms_frontbuffer_tracking@psr-2p-scndscrn-pri-shrfb-draw-mmap-gtt | |
| 1544 | −kms_frontbuffer_tracking@psr-2p-scndscrn-pri-shrfb-draw-mmap-wc | |
| 1545 | −kms_frontbuffer_tracking@psr-2p-scndscrn-pri-shrfb-draw-pwrite | |
| 1546 | −kms_frontbuffer_tracking@psr-2p-scndscrn-pri-shrfb-draw-blt | |
| 1547 | −kms_frontbuffer_tracking@psr-2p-scndscrn-pri-shrfb-draw-render | |
| 1548 | −kms_frontbuffer_tracking@psr-2p-scndscrn-cur-indfb-draw-mmap-cpu | |
| 1549 | −kms_frontbuffer_tracking@psr-2p-scndscrn-cur-indfb-draw-mmap-gtt | |
| 1550 | −kms_frontbuffer_tracking@psr-2p-scndscrn-cur-indfb-draw-mmap-wc | |
| 1551 | −kms_frontbuffer_tracking@psr-2p-scndscrn-cur-indfb-draw-pwrite | |
| 1552 | −kms_frontbuffer_tracking@psr-2p-scndscrn-cur-indfb-draw-blt | |
| 1553 | −kms_frontbuffer_tracking@psr-2p-scndscrn-cur-indfb-draw-render | |
| 1554 | −kms_frontbuffer_tracking@psr-2p-scndscrn-spr-indfb-draw-mmap-cpu | |
| 1555 | −kms_frontbuffer_tracking@psr-2p-scndscrn-spr-indfb-draw-mmap-gtt | |
| 1556 | −kms_frontbuffer_tracking@psr-2p-scndscrn-spr-indfb-draw-mmap-wc | |
| 1557 | −kms_frontbuffer_tracking@psr-2p-scndscrn-spr-indfb-draw-pwrite | |
| 1558 | −kms_frontbuffer_tracking@psr-2p-scndscrn-spr-indfb-draw-blt | |
| 1559 | −kms_frontbuffer_tracking@psr-2p-scndscrn-spr-indfb-draw-render | |
| 1560 | −kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-indfb-draw-mmap-cpu | |
| 1561 | −kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-indfb-draw-mmap-gtt | |
| 1562 | −kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-indfb-draw-mmap-wc | |
| 1563 | −kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-indfb-draw-pwrite | |
| 1564 | −kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-indfb-draw-blt | |
| 1565 | −kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-indfb-draw-render | |
| 1566 | −kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-shrfb-draw-mmap-cpu | |
| 1567 | −kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-shrfb-draw-mmap-gtt | |
| 1568 | −kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-shrfb-draw-mmap-wc | |
| 1569 | −kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-shrfb-draw-pwrite | |
| 1570 | −kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-shrfb-draw-blt | |
| 1571 | −kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-shrfb-draw-render | |
| 1572 | −kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-mmap-cpu | |
| 1573 | −kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-mmap-gtt | |
| 1574 | −kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-mmap-wc | |
| 1575 | −kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-pwrite | |
| 1576 | −kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-blt | |
| 1577 | −kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-render | |
| 1578 | −kms_frontbuffer_tracking@fbcpsr-1p-primscrn-spr-indfb-draw-mmap-cpu | |
| 1579 | −kms_frontbuffer_tracking@fbcpsr-1p-primscrn-spr-indfb-draw-mmap-gtt | |
| 1580 | −kms_frontbuffer_tracking@fbcpsr-1p-primscrn-spr-indfb-draw-mmap-wc | |
| 1581 | −kms_frontbuffer_tracking@fbcpsr-1p-primscrn-spr-indfb-draw-pwrite | |
| 1582 | −kms_frontbuffer_tracking@fbcpsr-1p-primscrn-spr-indfb-draw-blt | |
| 1583 | −kms_frontbuffer_tracking@fbcpsr-1p-primscrn-spr-indfb-draw-render | |
| 1584 | −kms_frontbuffer_tracking@fbcpsr-1p-offscren-pri-indfb-draw-mmap-cpu | |
| 1585 | −kms_frontbuffer_tracking@fbcpsr-1p-offscren-pri-indfb-draw-mmap-gtt | |
| 1586 | −kms_frontbuffer_tracking@fbcpsr-1p-offscren-pri-indfb-draw-mmap-wc | |
| 1587 | −kms_frontbuffer_tracking@fbcpsr-1p-offscren-pri-indfb-draw-pwrite | |
| 1588 | −kms_frontbuffer_tracking@fbcpsr-1p-offscren-pri-indfb-draw-blt | |
| 1589 | −kms_frontbuffer_tracking@fbcpsr-1p-offscren-pri-indfb-draw-render | |
| 1590 | −kms_frontbuffer_tracking@fbcpsr-1p-offscren-pri-shrfb-draw-mmap-cpu | |
| 1591 | −kms_frontbuffer_tracking@fbcpsr-1p-offscren-pri-shrfb-draw-mmap-gtt | |
| 1592 | −kms_frontbuffer_tracking@fbcpsr-1p-offscren-pri-shrfb-draw-mmap-wc | |
| 1593 | −kms_frontbuffer_tracking@fbcpsr-1p-offscren-pri-shrfb-draw-pwrite | |
| 1594 | −kms_frontbuffer_tracking@fbcpsr-1p-offscren-pri-shrfb-draw-blt | |
| 1595 | −kms_frontbuffer_tracking@fbcpsr-1p-offscren-pri-shrfb-draw-render | |
| 1596 | −kms_frontbuffer_tracking@fbcpsr-2p-primscrn-pri-indfb-draw-mmap-cpu | |
| 1597 | −kms_frontbuffer_tracking@fbcpsr-2p-primscrn-pri-indfb-draw-mmap-gtt | |
| 1598 | −kms_frontbuffer_tracking@fbcpsr-2p-primscrn-pri-indfb-draw-mmap-wc | |
| 1599 | −kms_frontbuffer_tracking@fbcpsr-2p-primscrn-pri-indfb-draw-pwrite | |
| 1600 | −kms_frontbuffer_tracking@fbcpsr-2p-primscrn-pri-indfb-draw-blt | |
| 1601 | −kms_frontbuffer_tracking@fbcpsr-2p-primscrn-pri-indfb-draw-render | |
| 1602 | −kms_frontbuffer_tracking@fbcpsr-2p-primscrn-pri-shrfb-draw-mmap-cpu | |
| 1603 | −kms_frontbuffer_tracking@fbcpsr-2p-primscrn-pri-shrfb-draw-mmap-gtt | |
| 1604 | −kms_frontbuffer_tracking@fbcpsr-2p-primscrn-pri-shrfb-draw-mmap-wc | |
| 1605 | −kms_frontbuffer_tracking@fbcpsr-2p-primscrn-pri-shrfb-draw-pwrite | |
| 1606 | −kms_frontbuffer_tracking@fbcpsr-2p-primscrn-pri-shrfb-draw-blt | |
| 1607 | −kms_frontbuffer_tracking@fbcpsr-2p-primscrn-pri-shrfb-draw-render | |
| 1608 | −kms_frontbuffer_tracking@fbcpsr-2p-primscrn-cur-indfb-draw-mmap-cpu | |
| 1609 | −kms_frontbuffer_tracking@fbcpsr-2p-primscrn-cur-indfb-draw-mmap-gtt | |
| 1610 | −kms_frontbuffer_tracking@fbcpsr-2p-primscrn-cur-indfb-draw-mmap-wc | |
| 1611 | −kms_frontbuffer_tracking@fbcpsr-2p-primscrn-cur-indfb-draw-pwrite | |
| 1612 | −kms_frontbuffer_tracking@fbcpsr-2p-primscrn-cur-indfb-draw-blt | |
| 1613 | −kms_frontbuffer_tracking@fbcpsr-2p-primscrn-cur-indfb-draw-render | |
| 1614 | −kms_frontbuffer_tracking@fbcpsr-2p-primscrn-spr-indfb-draw-mmap-cpu | |
| 1615 | −kms_frontbuffer_tracking@fbcpsr-2p-primscrn-spr-indfb-draw-mmap-gtt | |
| 1616 | −kms_frontbuffer_tracking@fbcpsr-2p-primscrn-spr-indfb-draw-mmap-wc | |
| 1617 | −kms_frontbuffer_tracking@fbcpsr-2p-primscrn-spr-indfb-draw-pwrite | |
| 1618 | −kms_frontbuffer_tracking@fbcpsr-2p-primscrn-spr-indfb-draw-blt | |
| 1619 | −kms_frontbuffer_tracking@fbcpsr-2p-primscrn-spr-indfb-draw-render | |
| 1620 | −kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-pri-indfb-draw-mmap-cpu | |
| 1621 | −kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-pri-indfb-draw-mmap-gtt | |
| 1622 | −kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-pri-indfb-draw-mmap-wc | |
| 1623 | −kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-pri-indfb-draw-pwrite | |
| 1624 | −kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-pri-indfb-draw-blt | |
| 1625 | −kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-pri-indfb-draw-render | |
| 1626 | −kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-pri-shrfb-draw-mmap-cpu | |
| 1627 | −kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-pri-shrfb-draw-mmap-gtt | |
| 1628 | −kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-pri-shrfb-draw-mmap-wc | |
| 1629 | −kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-pri-shrfb-draw-pwrite | |
| 1630 | −kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-pri-shrfb-draw-blt | |
| 1631 | −kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-pri-shrfb-draw-render | |
| 1632 | −kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-cur-indfb-draw-mmap-cpu | |
| 1633 | −kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-cur-indfb-draw-mmap-gtt | |
| 1634 | −kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-cur-indfb-draw-mmap-wc | |
| 1635 | −kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-cur-indfb-draw-pwrite | |
| 1636 | −kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-cur-indfb-draw-blt | |
| 1637 | −kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-cur-indfb-draw-render | |
| 1638 | −kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-spr-indfb-draw-mmap-cpu | |
| 1639 | −kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-spr-indfb-draw-mmap-gtt | |
| 1640 | −kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-spr-indfb-draw-mmap-wc | |
| 1641 | −kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-spr-indfb-draw-pwrite | |
| 1642 | −kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-spr-indfb-draw-blt | |
| 1643 | −kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-spr-indfb-draw-render | |
| 1644 | −kms_frontbuffer_tracking@drrs-1p-primscrn-pri-indfb-draw-mmap-cpu | |
| 1645 | −kms_frontbuffer_tracking@drrs-1p-primscrn-pri-indfb-draw-mmap-gtt | |
| 1646 | −kms_frontbuffer_tracking@drrs-1p-primscrn-pri-indfb-draw-mmap-wc | |
| 1647 | −kms_frontbuffer_tracking@drrs-1p-primscrn-pri-indfb-draw-pwrite | |
| 1648 | −kms_frontbuffer_tracking@drrs-1p-primscrn-pri-indfb-draw-blt | |
| 1649 | −kms_frontbuffer_tracking@drrs-1p-primscrn-pri-indfb-draw-render | |
| 1650 | −kms_frontbuffer_tracking@drrs-1p-primscrn-pri-shrfb-draw-mmap-cpu | |
| 1651 | −kms_frontbuffer_tracking@drrs-1p-primscrn-pri-shrfb-draw-mmap-gtt | |
| 1652 | −kms_frontbuffer_tracking@drrs-1p-primscrn-pri-shrfb-draw-mmap-wc | |
| 1653 | −kms_frontbuffer_tracking@drrs-1p-primscrn-pri-shrfb-draw-pwrite | |
| 1654 | −kms_frontbuffer_tracking@drrs-1p-primscrn-pri-shrfb-draw-blt | |
| 1655 | −kms_frontbuffer_tracking@drrs-1p-primscrn-pri-shrfb-draw-render | |
| 1656 | −kms_frontbuffer_tracking@drrs-1p-primscrn-cur-indfb-draw-mmap-cpu | |
| 1657 | −kms_frontbuffer_tracking@drrs-1p-primscrn-cur-indfb-draw-mmap-gtt | |
| 1658 | −kms_frontbuffer_tracking@drrs-1p-primscrn-cur-indfb-draw-mmap-wc | |
| 1659 | −kms_frontbuffer_tracking@drrs-1p-primscrn-cur-indfb-draw-pwrite | |
| 1660 | −kms_frontbuffer_tracking@drrs-1p-primscrn-cur-indfb-draw-blt | |
| 1661 | −kms_frontbuffer_tracking@drrs-1p-primscrn-cur-indfb-draw-render | |
| 1662 | −kms_frontbuffer_tracking@drrs-1p-primscrn-spr-indfb-draw-mmap-cpu | |
| 1663 | −kms_frontbuffer_tracking@drrs-1p-primscrn-spr-indfb-draw-mmap-gtt | |
| 1664 | −kms_frontbuffer_tracking@drrs-1p-primscrn-spr-indfb-draw-mmap-wc | |
| 1665 | −kms_frontbuffer_tracking@drrs-1p-primscrn-spr-indfb-draw-pwrite | |
| 1666 | −kms_frontbuffer_tracking@drrs-1p-primscrn-spr-indfb-draw-blt | |
| 1667 | −kms_frontbuffer_tracking@drrs-1p-primscrn-spr-indfb-draw-render | |
| 1668 | −kms_frontbuffer_tracking@drrs-1p-offscren-pri-indfb-draw-mmap-cpu | |
| 1669 | −kms_frontbuffer_tracking@drrs-1p-offscren-pri-indfb-draw-mmap-gtt | |
| 1670 | −kms_frontbuffer_tracking@drrs-1p-offscren-pri-indfb-draw-mmap-wc | |
| 1671 | −kms_frontbuffer_tracking@drrs-1p-offscren-pri-indfb-draw-pwrite | |
| 1672 | −kms_frontbuffer_tracking@drrs-1p-offscren-pri-indfb-draw-blt | |
| 1673 | −kms_frontbuffer_tracking@drrs-1p-offscren-pri-indfb-draw-render | |
| 1674 | −kms_frontbuffer_tracking@drrs-1p-offscren-pri-shrfb-draw-mmap-cpu | |
| 1675 | −kms_frontbuffer_tracking@drrs-1p-offscren-pri-shrfb-draw-mmap-gtt | |
| 1676 | −kms_frontbuffer_tracking@drrs-1p-offscren-pri-shrfb-draw-mmap-wc | |
| 1677 | −kms_frontbuffer_tracking@drrs-1p-offscren-pri-shrfb-draw-pwrite | |
| 1678 | −kms_frontbuffer_tracking@drrs-1p-offscren-pri-shrfb-draw-blt | |
| 1679 | −kms_frontbuffer_tracking@drrs-1p-offscren-pri-shrfb-draw-render | |
| 1680 | −kms_frontbuffer_tracking@drrs-2p-primscrn-pri-indfb-draw-mmap-cpu | |
| 1681 | −kms_frontbuffer_tracking@drrs-2p-primscrn-pri-indfb-draw-mmap-gtt | |
| 1682 | −kms_frontbuffer_tracking@drrs-2p-primscrn-pri-indfb-draw-mmap-wc | |
| 1683 | −kms_frontbuffer_tracking@drrs-2p-primscrn-pri-indfb-draw-pwrite | |
| 1684 | −kms_frontbuffer_tracking@drrs-2p-primscrn-pri-indfb-draw-blt | |
| 1685 | −kms_frontbuffer_tracking@drrs-2p-primscrn-pri-indfb-draw-render | |
| 1686 | −kms_frontbuffer_tracking@drrs-2p-primscrn-pri-shrfb-draw-mmap-cpu | |
| 1687 | −kms_frontbuffer_tracking@drrs-2p-primscrn-pri-shrfb-draw-mmap-gtt | |
| 1688 | −kms_frontbuffer_tracking@drrs-2p-primscrn-pri-shrfb-draw-mmap-wc | |
| 1689 | −kms_frontbuffer_tracking@drrs-2p-primscrn-pri-shrfb-draw-pwrite | |
| 1690 | −kms_frontbuffer_tracking@drrs-2p-primscrn-pri-shrfb-draw-blt | |
| 1691 | −kms_frontbuffer_tracking@drrs-2p-primscrn-pri-shrfb-draw-render | |
| 1692 | −kms_frontbuffer_tracking@drrs-2p-primscrn-cur-indfb-draw-mmap-cpu | |
| 1693 | −kms_frontbuffer_tracking@drrs-2p-primscrn-cur-indfb-draw-mmap-gtt | |
| 1694 | −kms_frontbuffer_tracking@drrs-2p-primscrn-cur-indfb-draw-mmap-wc | |
| 1695 | −kms_frontbuffer_tracking@drrs-2p-primscrn-cur-indfb-draw-pwrite | |
| 1696 | −kms_frontbuffer_tracking@drrs-2p-primscrn-cur-indfb-draw-blt | |
| 1697 | −kms_frontbuffer_tracking@drrs-2p-primscrn-cur-indfb-draw-render | |
| 1698 | −kms_frontbuffer_tracking@drrs-2p-primscrn-spr-indfb-draw-mmap-cpu | |
| 1699 | −kms_frontbuffer_tracking@drrs-2p-primscrn-spr-indfb-draw-mmap-gtt | |
| 1700 | −kms_frontbuffer_tracking@drrs-2p-primscrn-spr-indfb-draw-mmap-wc | |
| 1701 | −kms_frontbuffer_tracking@drrs-2p-primscrn-spr-indfb-draw-pwrite | |
| 1702 | −kms_frontbuffer_tracking@drrs-2p-primscrn-spr-indfb-draw-blt | |
| 1703 | −kms_frontbuffer_tracking@drrs-2p-primscrn-spr-indfb-draw-render | |
| 1704 | −kms_frontbuffer_tracking@drrs-2p-scndscrn-pri-indfb-draw-mmap-cpu | |
| 1705 | −kms_frontbuffer_tracking@drrs-2p-scndscrn-pri-indfb-draw-mmap-gtt | |
| 1706 | −kms_frontbuffer_tracking@drrs-2p-scndscrn-pri-indfb-draw-mmap-wc | |
| 1707 | −kms_frontbuffer_tracking@drrs-2p-scndscrn-pri-indfb-draw-pwrite | |
| 1708 | −kms_frontbuffer_tracking@drrs-2p-scndscrn-pri-indfb-draw-blt | |
| 1709 | −kms_frontbuffer_tracking@drrs-2p-scndscrn-pri-indfb-draw-render | |
| 1710 | −kms_frontbuffer_tracking@drrs-2p-scndscrn-pri-shrfb-draw-mmap-cpu | |
| 1711 | −kms_frontbuffer_tracking@drrs-2p-scndscrn-pri-shrfb-draw-mmap-gtt | |
| 1712 | −kms_frontbuffer_tracking@drrs-2p-scndscrn-pri-shrfb-draw-mmap-wc | |
| 1713 | −kms_frontbuffer_tracking@drrs-2p-scndscrn-pri-shrfb-draw-pwrite | |
| 1714 | −kms_frontbuffer_tracking@drrs-2p-scndscrn-pri-shrfb-draw-blt | |
| 1715 | −kms_frontbuffer_tracking@drrs-2p-scndscrn-pri-shrfb-draw-render | |
| 1716 | −kms_frontbuffer_tracking@drrs-2p-scndscrn-cur-indfb-draw-mmap-cpu | |
| 1717 | −kms_frontbuffer_tracking@drrs-2p-scndscrn-cur-indfb-draw-mmap-gtt | |
| 1718 | −kms_frontbuffer_tracking@drrs-2p-scndscrn-cur-indfb-draw-mmap-wc | |
| 1719 | −kms_frontbuffer_tracking@drrs-2p-scndscrn-cur-indfb-draw-pwrite | |
| 1720 | −kms_frontbuffer_tracking@drrs-2p-scndscrn-cur-indfb-draw-blt | |
| 1721 | −kms_frontbuffer_tracking@drrs-2p-scndscrn-cur-indfb-draw-render | |
| 1722 | −kms_frontbuffer_tracking@drrs-2p-scndscrn-spr-indfb-draw-mmap-cpu | |
| 1723 | −kms_frontbuffer_tracking@drrs-2p-scndscrn-spr-indfb-draw-mmap-gtt | |
| 1724 | −kms_frontbuffer_tracking@drrs-2p-scndscrn-spr-indfb-draw-mmap-wc | |
| 1725 | −kms_frontbuffer_tracking@drrs-2p-scndscrn-spr-indfb-draw-pwrite | |
| 1726 | −kms_frontbuffer_tracking@drrs-2p-scndscrn-spr-indfb-draw-blt | |
| 1727 | −kms_frontbuffer_tracking@drrs-2p-scndscrn-spr-indfb-draw-render | |
| 1728 | −kms_frontbuffer_tracking@fbcdrrs-1p-primscrn-pri-indfb-draw-mmap-cpu | |
| 1729 | −kms_frontbuffer_tracking@fbcdrrs-1p-primscrn-pri-indfb-draw-mmap-gtt | |
| 1730 | −kms_frontbuffer_tracking@fbcdrrs-1p-primscrn-pri-indfb-draw-mmap-wc | |
| 1731 | −kms_frontbuffer_tracking@fbcdrrs-1p-primscrn-pri-indfb-draw-pwrite | |
| 1732 | −kms_frontbuffer_tracking@fbcdrrs-1p-primscrn-pri-indfb-draw-blt | |
| 1733 | −kms_frontbuffer_tracking@fbcdrrs-1p-primscrn-pri-indfb-draw-render | |
| 1734 | −kms_frontbuffer_tracking@fbcdrrs-1p-primscrn-pri-shrfb-draw-mmap-cpu | |
| 1735 | −kms_frontbuffer_tracking@fbcdrrs-1p-primscrn-pri-shrfb-draw-mmap-gtt | |
| 1736 | −kms_frontbuffer_tracking@fbcdrrs-1p-primscrn-pri-shrfb-draw-mmap-wc | |
| 1737 | −kms_frontbuffer_tracking@fbcdrrs-1p-primscrn-pri-shrfb-draw-pwrite | |
| 1738 | −kms_frontbuffer_tracking@fbcdrrs-1p-primscrn-pri-shrfb-draw-blt | |
| 1739 | −kms_frontbuffer_tracking@fbcdrrs-1p-primscrn-pri-shrfb-draw-render | |
| 1740 | −kms_frontbuffer_tracking@fbcdrrs-1p-primscrn-cur-indfb-draw-mmap-cpu | |
| 1741 | −kms_frontbuffer_tracking@fbcdrrs-1p-primscrn-cur-indfb-draw-mmap-gtt | |
| 1742 | −kms_frontbuffer_tracking@fbcdrrs-1p-primscrn-cur-indfb-draw-mmap-wc | |
| 1743 | −kms_frontbuffer_tracking@fbcdrrs-1p-primscrn-cur-indfb-draw-pwrite | |
| 1744 | −kms_frontbuffer_tracking@fbcdrrs-1p-primscrn-cur-indfb-draw-blt | |
| 1745 | −kms_frontbuffer_tracking@fbcdrrs-1p-primscrn-cur-indfb-draw-render | |
| 1746 | −kms_frontbuffer_tracking@fbcdrrs-1p-primscrn-spr-indfb-draw-mmap-cpu | |
| 1747 | −kms_frontbuffer_tracking@fbcdrrs-1p-primscrn-spr-indfb-draw-mmap-gtt | |
| 1748 | −kms_frontbuffer_tracking@fbcdrrs-1p-primscrn-spr-indfb-draw-mmap-wc | |
| 1749 | −kms_frontbuffer_tracking@fbcdrrs-1p-primscrn-spr-indfb-draw-pwrite | |
| 1750 | −kms_frontbuffer_tracking@fbcdrrs-1p-primscrn-spr-indfb-draw-blt | |
| 1751 | −kms_frontbuffer_tracking@fbcdrrs-1p-primscrn-spr-indfb-draw-render | |
| 1752 | −kms_frontbuffer_tracking@fbcdrrs-1p-offscren-pri-indfb-draw-mmap-cpu | |
| 1753 | −kms_frontbuffer_tracking@fbcdrrs-1p-offscren-pri-indfb-draw-mmap-gtt | |
| 1754 | −kms_frontbuffer_tracking@fbcdrrs-1p-offscren-pri-indfb-draw-mmap-wc | |
| 1755 | −kms_frontbuffer_tracking@fbcdrrs-1p-offscren-pri-indfb-draw-pwrite | |
| 1756 | −kms_frontbuffer_tracking@fbcdrrs-1p-offscren-pri-indfb-draw-blt | |
| 1757 | −kms_frontbuffer_tracking@fbcdrrs-1p-offscren-pri-indfb-draw-render | |
| 1758 | −kms_frontbuffer_tracking@fbcdrrs-1p-offscren-pri-shrfb-draw-mmap-cpu | |
| 1759 | −kms_frontbuffer_tracking@fbcdrrs-1p-offscren-pri-shrfb-draw-mmap-gtt | |
| 1760 | −kms_frontbuffer_tracking@fbcdrrs-1p-offscren-pri-shrfb-draw-mmap-wc | |
| 1761 | −kms_frontbuffer_tracking@fbcdrrs-1p-offscren-pri-shrfb-draw-pwrite | |
| 1762 | −kms_frontbuffer_tracking@fbcdrrs-1p-offscren-pri-shrfb-draw-blt | |
| 1763 | −kms_frontbuffer_tracking@fbcdrrs-1p-offscren-pri-shrfb-draw-render | |
| 1764 | −kms_frontbuffer_tracking@fbcdrrs-2p-primscrn-pri-indfb-draw-mmap-cpu | |
| 1765 | −kms_frontbuffer_tracking@fbcdrrs-2p-primscrn-pri-indfb-draw-mmap-gtt | |
| 1766 | −kms_frontbuffer_tracking@fbcdrrs-2p-primscrn-pri-indfb-draw-mmap-wc | |
| 1767 | −kms_frontbuffer_tracking@fbcdrrs-2p-primscrn-pri-indfb-draw-pwrite | |
| 1768 | −kms_frontbuffer_tracking@fbcdrrs-2p-primscrn-pri-indfb-draw-blt | |
| 1769 | −kms_frontbuffer_tracking@fbcdrrs-2p-primscrn-pri-indfb-draw-render | |
| 1770 | −kms_frontbuffer_tracking@fbcdrrs-2p-primscrn-pri-shrfb-draw-mmap-cpu | |
| 1771 | −kms_frontbuffer_tracking@fbcdrrs-2p-primscrn-pri-shrfb-draw-mmap-gtt | |
| 1772 | −kms_frontbuffer_tracking@fbcdrrs-2p-primscrn-pri-shrfb-draw-mmap-wc | |
| 1773 | −kms_frontbuffer_tracking@fbcdrrs-2p-primscrn-pri-shrfb-draw-pwrite | |
| 1774 | −kms_frontbuffer_tracking@fbcdrrs-2p-primscrn-pri-shrfb-draw-blt | |
| 1775 | −kms_frontbuffer_tracking@fbcdrrs-2p-primscrn-pri-shrfb-draw-render | |
| 1776 | −kms_frontbuffer_tracking@fbcdrrs-2p-primscrn-cur-indfb-draw-mmap-cpu | |
| 1777 | −kms_frontbuffer_tracking@fbcdrrs-2p-primscrn-cur-indfb-draw-mmap-gtt | |
| 1778 | −kms_frontbuffer_tracking@fbcdrrs-2p-primscrn-cur-indfb-draw-mmap-wc | |
| 1779 | −kms_frontbuffer_tracking@fbcdrrs-2p-primscrn-cur-indfb-draw-pwrite | |
| 1780 | −kms_frontbuffer_tracking@fbcdrrs-2p-primscrn-cur-indfb-draw-blt | |
| 1781 | −kms_frontbuffer_tracking@fbcdrrs-2p-primscrn-cur-indfb-draw-render | |
| 1782 | −kms_frontbuffer_tracking@fbcdrrs-2p-primscrn-spr-indfb-draw-mmap-cpu | |
| 1783 | −kms_frontbuffer_tracking@fbcdrrs-2p-primscrn-spr-indfb-draw-mmap-gtt | |
| 1784 | −kms_frontbuffer_tracking@fbcdrrs-2p-primscrn-spr-indfb-draw-mmap-wc | |
| 1785 | −kms_frontbuffer_tracking@fbcdrrs-2p-primscrn-spr-indfb-draw-pwrite | |
| 1786 | −kms_frontbuffer_tracking@fbcdrrs-2p-primscrn-spr-indfb-draw-blt | |
| 1787 | −kms_frontbuffer_tracking@fbcdrrs-2p-primscrn-spr-indfb-draw-render | |
| 1788 | −kms_frontbuffer_tracking@fbcdrrs-2p-scndscrn-pri-indfb-draw-mmap-cpu | |
| 1789 | −kms_frontbuffer_tracking@fbcdrrs-2p-scndscrn-pri-indfb-draw-mmap-gtt | |
| 1790 | −kms_frontbuffer_tracking@fbcdrrs-2p-scndscrn-pri-indfb-draw-mmap-wc | |
| 1791 | −kms_frontbuffer_tracking@fbcdrrs-2p-scndscrn-pri-indfb-draw-pwrite | |
| 1792 | −kms_frontbuffer_tracking@fbcdrrs-2p-scndscrn-pri-indfb-draw-blt | |
| 1793 | −kms_frontbuffer_tracking@fbcdrrs-2p-scndscrn-pri-indfb-draw-render | |
| 1794 | −kms_frontbuffer_tracking@fbcdrrs-2p-scndscrn-pri-shrfb-draw-mmap-cpu | |
| 1795 | −kms_frontbuffer_tracking@fbcdrrs-2p-scndscrn-pri-shrfb-draw-mmap-gtt | |
| 1796 | −kms_frontbuffer_tracking@fbcdrrs-2p-scndscrn-pri-shrfb-draw-mmap-wc | |
| 1797 | −kms_frontbuffer_tracking@fbcdrrs-2p-scndscrn-pri-shrfb-draw-pwrite | |
| 1798 | −kms_frontbuffer_tracking@fbcdrrs-2p-scndscrn-pri-shrfb-draw-blt | |
| 1799 | −kms_frontbuffer_tracking@fbcdrrs-2p-scndscrn-pri-shrfb-draw-render | |
| 1800 | −kms_frontbuffer_tracking@fbcdrrs-2p-scndscrn-cur-indfb-draw-mmap-cpu | |
| 1801 | −kms_frontbuffer_tracking@fbcdrrs-2p-scndscrn-cur-indfb-draw-mmap-gtt | |
| 1802 | −kms_frontbuffer_tracking@fbcdrrs-2p-scndscrn-cur-indfb-draw-mmap-wc | |
| 1803 | −kms_frontbuffer_tracking@fbcdrrs-2p-scndscrn-cur-indfb-draw-pwrite | |
| 1804 | −kms_frontbuffer_tracking@fbcdrrs-2p-scndscrn-cur-indfb-draw-blt | |
| 1805 | −kms_frontbuffer_tracking@fbcdrrs-2p-scndscrn-cur-indfb-draw-render | |
| 1806 | −kms_frontbuffer_tracking@fbcdrrs-2p-scndscrn-spr-indfb-draw-mmap-cpu | |
| 1807 | −kms_frontbuffer_tracking@fbcdrrs-2p-scndscrn-spr-indfb-draw-mmap-gtt | |
| 1808 | −kms_frontbuffer_tracking@fbcdrrs-2p-scndscrn-spr-indfb-draw-mmap-wc | |
| 1809 | −kms_frontbuffer_tracking@fbcdrrs-2p-scndscrn-spr-indfb-draw-pwrite | |
| 1810 | −kms_frontbuffer_tracking@fbcdrrs-2p-scndscrn-spr-indfb-draw-blt | |
| 1811 | −kms_frontbuffer_tracking@fbcdrrs-2p-scndscrn-spr-indfb-draw-render | |
| 1812 | −kms_frontbuffer_tracking@psrdrrs-1p-primscrn-pri-indfb-draw-mmap-cpu | |
| 1813 | −kms_frontbuffer_tracking@psrdrrs-1p-primscrn-pri-indfb-draw-mmap-gtt | |
| 1814 | −kms_frontbuffer_tracking@psrdrrs-1p-primscrn-pri-indfb-draw-mmap-wc | |
| 1815 | −kms_frontbuffer_tracking@psrdrrs-1p-primscrn-pri-indfb-draw-pwrite | |
| 1816 | −kms_frontbuffer_tracking@psrdrrs-1p-primscrn-pri-indfb-draw-blt | |
| 1817 | −kms_frontbuffer_tracking@psrdrrs-1p-primscrn-pri-indfb-draw-render | |
| 1818 | −kms_frontbuffer_tracking@psrdrrs-1p-primscrn-pri-shrfb-draw-mmap-cpu | |
| 1819 | −kms_frontbuffer_tracking@psrdrrs-1p-primscrn-pri-shrfb-draw-mmap-gtt | |
| 1820 | −kms_frontbuffer_tracking@psrdrrs-1p-primscrn-pri-shrfb-draw-mmap-wc | |
| 1821 | −kms_frontbuffer_tracking@psrdrrs-1p-primscrn-pri-shrfb-draw-pwrite | |
| 1822 | −kms_frontbuffer_tracking@psrdrrs-1p-primscrn-pri-shrfb-draw-blt | |
| 1823 | −kms_frontbuffer_tracking@psrdrrs-1p-primscrn-pri-shrfb-draw-render | |
| 1824 | −kms_frontbuffer_tracking@psrdrrs-1p-primscrn-cur-indfb-draw-mmap-cpu | |
| 1825 | −kms_frontbuffer_tracking@psrdrrs-1p-primscrn-cur-indfb-draw-mmap-gtt | |
| 1826 | −kms_frontbuffer_tracking@psrdrrs-1p-primscrn-cur-indfb-draw-mmap-wc | |
| 1827 | −kms_frontbuffer_tracking@psrdrrs-1p-primscrn-cur-indfb-draw-pwrite | |
| 1828 | −kms_frontbuffer_tracking@psrdrrs-1p-primscrn-cur-indfb-draw-blt | |
| 1829 | −kms_frontbuffer_tracking@psrdrrs-1p-primscrn-cur-indfb-draw-render | |
| 1830 | −kms_frontbuffer_tracking@psrdrrs-1p-primscrn-spr-indfb-draw-mmap-cpu | |
| 1831 | −kms_frontbuffer_tracking@psrdrrs-1p-primscrn-spr-indfb-draw-mmap-gtt | |
| 1832 | −kms_frontbuffer_tracking@psrdrrs-1p-primscrn-spr-indfb-draw-mmap-wc | |
| 1833 | −kms_frontbuffer_tracking@psrdrrs-1p-primscrn-spr-indfb-draw-pwrite | |
| 1834 | −kms_frontbuffer_tracking@psrdrrs-1p-primscrn-spr-indfb-draw-blt | |
| 1835 | −kms_frontbuffer_tracking@psrdrrs-1p-primscrn-spr-indfb-draw-render | |
| 1836 | −kms_frontbuffer_tracking@psrdrrs-1p-offscren-pri-indfb-draw-mmap-cpu | |
| 1837 | −kms_frontbuffer_tracking@psrdrrs-1p-offscren-pri-indfb-draw-mmap-gtt | |
| 1838 | −kms_frontbuffer_tracking@psrdrrs-1p-offscren-pri-indfb-draw-mmap-wc | |
| 1839 | −kms_frontbuffer_tracking@psrdrrs-1p-offscren-pri-indfb-draw-pwrite | |
| 1840 | −kms_frontbuffer_tracking@psrdrrs-1p-offscren-pri-indfb-draw-blt | |
| 1841 | −kms_frontbuffer_tracking@psrdrrs-1p-offscren-pri-indfb-draw-render | |
| 1842 | −kms_frontbuffer_tracking@psrdrrs-1p-offscren-pri-shrfb-draw-mmap-cpu | |
| 1843 | −kms_frontbuffer_tracking@psrdrrs-1p-offscren-pri-shrfb-draw-mmap-gtt | |
| 1844 | −kms_frontbuffer_tracking@psrdrrs-1p-offscren-pri-shrfb-draw-mmap-wc | |
| 1845 | −kms_frontbuffer_tracking@psrdrrs-1p-offscren-pri-shrfb-draw-pwrite | |
| 1846 | −kms_frontbuffer_tracking@psrdrrs-1p-offscren-pri-shrfb-draw-blt | |
| 1847 | −kms_frontbuffer_tracking@psrdrrs-1p-offscren-pri-shrfb-draw-render | |
| 1848 | −kms_frontbuffer_tracking@psrdrrs-2p-primscrn-pri-indfb-draw-mmap-cpu | |
| 1849 | −kms_frontbuffer_tracking@psrdrrs-2p-primscrn-pri-indfb-draw-mmap-gtt | |
| 1850 | −kms_frontbuffer_tracking@psrdrrs-2p-primscrn-pri-indfb-draw-mmap-wc | |
| 1851 | −kms_frontbuffer_tracking@psrdrrs-2p-primscrn-pri-indfb-draw-pwrite | |
| 1852 | −kms_frontbuffer_tracking@psrdrrs-2p-primscrn-pri-indfb-draw-blt | |
| 1853 | −kms_frontbuffer_tracking@psrdrrs-2p-primscrn-pri-indfb-draw-render | |
| 1854 | −kms_frontbuffer_tracking@psrdrrs-2p-primscrn-pri-shrfb-draw-mmap-cpu | |
| 1855 | −kms_frontbuffer_tracking@psrdrrs-2p-primscrn-pri-shrfb-draw-mmap-gtt | |
| 1856 | −kms_frontbuffer_tracking@psrdrrs-2p-primscrn-pri-shrfb-draw-mmap-wc | |
| 1857 | −kms_frontbuffer_tracking@psrdrrs-2p-primscrn-pri-shrfb-draw-pwrite | |
| 1858 | −kms_frontbuffer_tracking@psrdrrs-2p-primscrn-pri-shrfb-draw-blt | |
| 1859 | −kms_frontbuffer_tracking@psrdrrs-2p-primscrn-pri-shrfb-draw-render | |
| 1860 | −kms_frontbuffer_tracking@psrdrrs-2p-primscrn-cur-indfb-draw-mmap-cpu | |
| 1861 | −kms_frontbuffer_tracking@psrdrrs-2p-primscrn-cur-indfb-draw-mmap-gtt | |
| 1862 | −kms_frontbuffer_tracking@psrdrrs-2p-primscrn-cur-indfb-draw-mmap-wc | |
| 1863 | −kms_frontbuffer_tracking@psrdrrs-2p-primscrn-cur-indfb-draw-pwrite | |
| 1864 | −kms_frontbuffer_tracking@psrdrrs-2p-primscrn-cur-indfb-draw-blt | |
| 1865 | −kms_frontbuffer_tracking@psrdrrs-2p-primscrn-cur-indfb-draw-render | |
| 1866 | −kms_frontbuffer_tracking@psrdrrs-2p-primscrn-spr-indfb-draw-mmap-cpu | |
| 1867 | −kms_frontbuffer_tracking@psrdrrs-2p-primscrn-spr-indfb-draw-mmap-gtt | |
| 1868 | −kms_frontbuffer_tracking@psrdrrs-2p-primscrn-spr-indfb-draw-mmap-wc | |
| 1869 | −kms_frontbuffer_tracking@psrdrrs-2p-primscrn-spr-indfb-draw-pwrite | |
| 1870 | −kms_frontbuffer_tracking@psrdrrs-2p-primscrn-spr-indfb-draw-blt | |
| 1871 | −kms_frontbuffer_tracking@psrdrrs-2p-primscrn-spr-indfb-draw-render | |
| 1872 | −kms_frontbuffer_tracking@psrdrrs-2p-scndscrn-pri-indfb-draw-mmap-cpu | |
| 1873 | −kms_frontbuffer_tracking@psrdrrs-2p-scndscrn-pri-indfb-draw-mmap-gtt | |
| 1874 | −kms_frontbuffer_tracking@psrdrrs-2p-scndscrn-pri-indfb-draw-mmap-wc | |
| 1875 | −kms_frontbuffer_tracking@psrdrrs-2p-scndscrn-pri-indfb-draw-pwrite | |
| 1876 | −kms_frontbuffer_tracking@psrdrrs-2p-scndscrn-pri-indfb-draw-blt | |
| 1877 | −kms_frontbuffer_tracking@psrdrrs-2p-scndscrn-pri-indfb-draw-render | |
| 1878 | −kms_frontbuffer_tracking@psrdrrs-2p-scndscrn-pri-shrfb-draw-mmap-cpu | |
| 1879 | −kms_frontbuffer_tracking@psrdrrs-2p-scndscrn-pri-shrfb-draw-mmap-gtt | |
| 1880 | −kms_frontbuffer_tracking@psrdrrs-2p-scndscrn-pri-shrfb-draw-mmap-wc | |
| 1881 | −kms_frontbuffer_tracking@psrdrrs-2p-scndscrn-pri-shrfb-draw-pwrite | |
| 1882 | −kms_frontbuffer_tracking@psrdrrs-2p-scndscrn-pri-shrfb-draw-blt | |
| 1883 | −kms_frontbuffer_tracking@psrdrrs-2p-scndscrn-pri-shrfb-draw-render | |
| 1884 | −kms_frontbuffer_tracking@psrdrrs-2p-scndscrn-cur-indfb-draw-mmap-cpu | |
| 1885 | −kms_frontbuffer_tracking@psrdrrs-2p-scndscrn-cur-indfb-draw-mmap-gtt | |
| 1886 | −kms_frontbuffer_tracking@psrdrrs-2p-scndscrn-cur-indfb-draw-mmap-wc | |
| 1887 | −kms_frontbuffer_tracking@psrdrrs-2p-scndscrn-cur-indfb-draw-pwrite | |
| 1888 | −kms_frontbuffer_tracking@psrdrrs-2p-scndscrn-cur-indfb-draw-blt | |
| 1889 | −kms_frontbuffer_tracking@psrdrrs-2p-scndscrn-cur-indfb-draw-render | |
| 1890 | −kms_frontbuffer_tracking@psrdrrs-2p-scndscrn-spr-indfb-draw-mmap-cpu | |
| 1891 | −kms_frontbuffer_tracking@psrdrrs-2p-scndscrn-spr-indfb-draw-mmap-gtt | |
| 1892 | −kms_frontbuffer_tracking@psrdrrs-2p-scndscrn-spr-indfb-draw-mmap-wc | |
| 1893 | −kms_frontbuffer_tracking@psrdrrs-2p-scndscrn-spr-indfb-draw-pwrite | |
| 1894 | −kms_frontbuffer_tracking@psrdrrs-2p-scndscrn-spr-indfb-draw-blt | |
| 1895 | −kms_frontbuffer_tracking@psrdrrs-2p-scndscrn-spr-indfb-draw-render | |
| 1896 | −kms_frontbuffer_tracking@fbcpsrdrrs-1p-primscrn-pri-indfb-draw-mmap-cpu | |
| 1897 | −kms_frontbuffer_tracking@fbcpsrdrrs-1p-primscrn-pri-indfb-draw-mmap-gtt | |
| 1898 | −kms_frontbuffer_tracking@fbcpsrdrrs-1p-primscrn-pri-indfb-draw-mmap-wc | |
| 1899 | −kms_frontbuffer_tracking@fbcpsrdrrs-1p-primscrn-pri-indfb-draw-pwrite | |
| 1900 | −kms_frontbuffer_tracking@fbcpsrdrrs-1p-primscrn-pri-indfb-draw-blt | |
| 1901 | −kms_frontbuffer_tracking@fbcpsrdrrs-1p-primscrn-pri-indfb-draw-render | |
| 1902 | −kms_frontbuffer_tracking@fbcpsrdrrs-1p-primscrn-pri-shrfb-draw-mmap-cpu | |
| 1903 | −kms_frontbuffer_tracking@fbcpsrdrrs-1p-primscrn-pri-shrfb-draw-mmap-gtt | |
| 1904 | −kms_frontbuffer_tracking@fbcpsrdrrs-1p-primscrn-pri-shrfb-draw-mmap-wc | |
| 1905 | −kms_frontbuffer_tracking@fbcpsrdrrs-1p-primscrn-pri-shrfb-draw-pwrite | |
| 1906 | −kms_frontbuffer_tracking@fbcpsrdrrs-1p-primscrn-pri-shrfb-draw-blt | |
| 1907 | −kms_frontbuffer_tracking@fbcpsrdrrs-1p-primscrn-pri-shrfb-draw-render | |
| 1908 | −kms_frontbuffer_tracking@fbcpsrdrrs-1p-primscrn-cur-indfb-draw-mmap-cpu | |
| 1909 | −kms_frontbuffer_tracking@fbcpsrdrrs-1p-primscrn-cur-indfb-draw-mmap-gtt | |
| 1910 | −kms_frontbuffer_tracking@fbcpsrdrrs-1p-primscrn-cur-indfb-draw-mmap-wc | |
| 1911 | −kms_frontbuffer_tracking@fbcpsrdrrs-1p-primscrn-cur-indfb-draw-pwrite | |
| 1912 | −kms_frontbuffer_tracking@fbcpsrdrrs-1p-primscrn-cur-indfb-draw-blt | |
| 1913 | −kms_frontbuffer_tracking@fbcpsrdrrs-1p-primscrn-cur-indfb-draw-render | |
| 1914 | −kms_frontbuffer_tracking@fbcpsrdrrs-1p-primscrn-spr-indfb-draw-mmap-cpu | |
| 1915 | −kms_frontbuffer_tracking@fbcpsrdrrs-1p-primscrn-spr-indfb-draw-mmap-gtt | |
| 1916 | −kms_frontbuffer_tracking@fbcpsrdrrs-1p-primscrn-spr-indfb-draw-mmap-wc | |
| 1917 | −kms_frontbuffer_tracking@fbcpsrdrrs-1p-primscrn-spr-indfb-draw-pwrite | |
| 1918 | −kms_frontbuffer_tracking@fbcpsrdrrs-1p-primscrn-spr-indfb-draw-blt | |
| 1919 | −kms_frontbuffer_tracking@fbcpsrdrrs-1p-primscrn-spr-indfb-draw-render | |
| 1920 | −kms_frontbuffer_tracking@fbcpsrdrrs-1p-offscren-pri-indfb-draw-mmap-cpu | |
| 1921 | −kms_frontbuffer_tracking@fbcpsrdrrs-1p-offscren-pri-indfb-draw-mmap-gtt | |
| 1922 | −kms_frontbuffer_tracking@fbcpsrdrrs-1p-offscren-pri-indfb-draw-mmap-wc | |
| 1923 | −kms_frontbuffer_tracking@fbcpsrdrrs-1p-offscren-pri-indfb-draw-pwrite | |
| 1924 | −kms_frontbuffer_tracking@fbcpsrdrrs-1p-offscren-pri-indfb-draw-blt | |
| 1925 | −kms_frontbuffer_tracking@fbcpsrdrrs-1p-offscren-pri-indfb-draw-render | |
| 1926 | −kms_frontbuffer_tracking@fbcpsrdrrs-1p-offscren-pri-shrfb-draw-mmap-cpu | |
| 1927 | −kms_frontbuffer_tracking@fbcpsrdrrs-1p-offscren-pri-shrfb-draw-mmap-gtt | |
| 1928 | −kms_frontbuffer_tracking@fbcpsrdrrs-1p-offscren-pri-shrfb-draw-mmap-wc | |
| 1929 | −kms_frontbuffer_tracking@fbcpsrdrrs-1p-offscren-pri-shrfb-draw-pwrite | |
| 1930 | −kms_frontbuffer_tracking@fbcpsrdrrs-1p-offscren-pri-shrfb-draw-blt | |
| 1931 | −kms_frontbuffer_tracking@fbcpsrdrrs-1p-offscren-pri-shrfb-draw-render | |
| 1932 | −kms_frontbuffer_tracking@fbcpsrdrrs-2p-primscrn-pri-indfb-draw-mmap-cpu | |
| 1933 | −kms_frontbuffer_tracking@fbcpsrdrrs-2p-primscrn-pri-indfb-draw-mmap-gtt | |
| 1934 | −kms_frontbuffer_tracking@fbcpsrdrrs-2p-primscrn-pri-indfb-draw-mmap-wc | |
| 1935 | −kms_frontbuffer_tracking@fbcpsrdrrs-2p-primscrn-pri-indfb-draw-pwrite | |
| 1936 | −kms_frontbuffer_tracking@fbcpsrdrrs-2p-primscrn-pri-indfb-draw-blt | |
| 1937 | −kms_frontbuffer_tracking@fbcpsrdrrs-2p-primscrn-pri-indfb-draw-render | |
| 1938 | −kms_frontbuffer_tracking@fbcpsrdrrs-2p-primscrn-pri-shrfb-draw-mmap-cpu | |
| 1939 | −kms_frontbuffer_tracking@fbcpsrdrrs-2p-primscrn-pri-shrfb-draw-mmap-gtt | |
| 1940 | −kms_frontbuffer_tracking@fbcpsrdrrs-2p-primscrn-pri-shrfb-draw-mmap-wc | |
| 1941 | −kms_frontbuffer_tracking@fbcpsrdrrs-2p-primscrn-pri-shrfb-draw-pwrite | |
| 1942 | −kms_frontbuffer_tracking@fbcpsrdrrs-2p-primscrn-pri-shrfb-draw-blt | |
| 1943 | −kms_frontbuffer_tracking@fbcpsrdrrs-2p-primscrn-pri-shrfb-draw-render | |
| 1944 | −kms_frontbuffer_tracking@fbcpsrdrrs-2p-primscrn-cur-indfb-draw-mmap-cpu | |
| 1945 | −kms_frontbuffer_tracking@fbcpsrdrrs-2p-primscrn-cur-indfb-draw-mmap-gtt | |
| 1946 | −kms_frontbuffer_tracking@fbcpsrdrrs-2p-primscrn-cur-indfb-draw-mmap-wc | |
| 1947 | −kms_frontbuffer_tracking@fbcpsrdrrs-2p-primscrn-cur-indfb-draw-pwrite | |
| 1948 | −kms_frontbuffer_tracking@fbcpsrdrrs-2p-primscrn-cur-indfb-draw-blt | |
| 1949 | −kms_frontbuffer_tracking@fbcpsrdrrs-2p-primscrn-cur-indfb-draw-render | |
| 1950 | −kms_frontbuffer_tracking@fbcpsrdrrs-2p-primscrn-spr-indfb-draw-mmap-cpu | |
| 1951 | −kms_frontbuffer_tracking@fbcpsrdrrs-2p-primscrn-spr-indfb-draw-mmap-gtt | |
| 1952 | −kms_frontbuffer_tracking@fbcpsrdrrs-2p-primscrn-spr-indfb-draw-mmap-wc | |
| 1953 | −kms_frontbuffer_tracking@fbcpsrdrrs-2p-primscrn-spr-indfb-draw-pwrite | |
| 1954 | −kms_frontbuffer_tracking@fbcpsrdrrs-2p-primscrn-spr-indfb-draw-blt | |
| 1955 | −kms_frontbuffer_tracking@fbcpsrdrrs-2p-primscrn-spr-indfb-draw-render | |
| 1956 | −kms_frontbuffer_tracking@fbcpsrdrrs-2p-scndscrn-pri-indfb-draw-mmap-cpu | |
| 1957 | −kms_frontbuffer_tracking@fbcpsrdrrs-2p-scndscrn-pri-indfb-draw-mmap-gtt | |
| 1958 | −kms_frontbuffer_tracking@fbcpsrdrrs-2p-scndscrn-pri-indfb-draw-mmap-wc | |
| 1959 | −kms_frontbuffer_tracking@fbcpsrdrrs-2p-scndscrn-pri-indfb-draw-pwrite | |
| 1960 | −kms_frontbuffer_tracking@fbcpsrdrrs-2p-scndscrn-pri-indfb-draw-blt | |
| 1961 | −kms_frontbuffer_tracking@fbcpsrdrrs-2p-scndscrn-pri-indfb-draw-render | |
| 1962 | −kms_frontbuffer_tracking@fbcpsrdrrs-2p-scndscrn-pri-shrfb-draw-mmap-cpu | |
| 1963 | −kms_frontbuffer_tracking@fbcpsrdrrs-2p-scndscrn-pri-shrfb-draw-mmap-gtt | |
| 1964 | −kms_frontbuffer_tracking@fbcpsrdrrs-2p-scndscrn-pri-shrfb-draw-mmap-wc | |
| 1965 | −kms_frontbuffer_tracking@fbcpsrdrrs-2p-scndscrn-pri-shrfb-draw-pwrite | |
| 1966 | −kms_frontbuffer_tracking@fbcpsrdrrs-2p-scndscrn-pri-shrfb-draw-blt | |
| 1967 | −kms_frontbuffer_tracking@fbcpsrdrrs-2p-scndscrn-pri-shrfb-draw-render | |
| 1968 | −kms_frontbuffer_tracking@fbcpsrdrrs-2p-scndscrn-cur-indfb-draw-mmap-cpu | |
| 1969 | −kms_frontbuffer_tracking@fbcpsrdrrs-2p-scndscrn-cur-indfb-draw-mmap-gtt | |
| 1970 | −kms_frontbuffer_tracking@fbcpsrdrrs-2p-scndscrn-cur-indfb-draw-mmap-wc | |
| 1971 | −kms_frontbuffer_tracking@fbcpsrdrrs-2p-scndscrn-cur-indfb-draw-pwrite | |
| 1972 | −kms_frontbuffer_tracking@fbcpsrdrrs-2p-scndscrn-cur-indfb-draw-blt | |
| 1973 | −kms_frontbuffer_tracking@fbcpsrdrrs-2p-scndscrn-cur-indfb-draw-render | |
| 1974 | −kms_frontbuffer_tracking@fbcpsrdrrs-2p-scndscrn-spr-indfb-draw-mmap-cpu | |
| 1975 | −kms_frontbuffer_tracking@fbcpsrdrrs-2p-scndscrn-spr-indfb-draw-mmap-gtt | |
| 1976 | −kms_frontbuffer_tracking@fbcpsrdrrs-2p-scndscrn-spr-indfb-draw-mmap-wc | |
| 1977 | −kms_frontbuffer_tracking@fbcpsrdrrs-2p-scndscrn-spr-indfb-draw-pwrite | |
| 1978 | −kms_frontbuffer_tracking@fbcpsrdrrs-2p-scndscrn-spr-indfb-draw-blt | |
| 1979 | −kms_frontbuffer_tracking@fbcpsrdrrs-2p-scndscrn-spr-indfb-draw-render | |
| 1980 | −kms_frontbuffer_tracking@fbc-1p-primscrn-indfb-pgflip-blt | |
| 1981 | −kms_frontbuffer_tracking@fbc-1p-primscrn-indfb-msflip-blt | |
| 1982 | −kms_frontbuffer_tracking@fbc-1p-primscrn-indfb-plflip-blt | |
| 1983 | −kms_frontbuffer_tracking@fbc-1p-primscrn-shrfb-pgflip-blt | |
| 1984 | −kms_frontbuffer_tracking@fbc-1p-primscrn-shrfb-msflip-blt | |
| 1985 | −kms_frontbuffer_tracking@fbc-1p-primscrn-shrfb-plflip-blt | |
| 1986 | −kms_frontbuffer_tracking@fbc-2p-primscrn-indfb-pgflip-blt | |
| 1987 | −kms_frontbuffer_tracking@fbc-2p-primscrn-indfb-msflip-blt | |
| 1988 | −kms_frontbuffer_tracking@fbc-2p-primscrn-indfb-plflip-blt | |
| 1989 | −kms_frontbuffer_tracking@fbc-2p-primscrn-shrfb-pgflip-blt | |
| 1990 | −kms_frontbuffer_tracking@fbc-2p-primscrn-shrfb-msflip-blt | |
| 1991 | −kms_frontbuffer_tracking@fbc-2p-primscrn-shrfb-plflip-blt | |
| 1992 | −kms_frontbuffer_tracking@fbc-2p-scndscrn-indfb-pgflip-blt | |
| 1993 | −kms_frontbuffer_tracking@fbc-2p-scndscrn-indfb-msflip-blt | |
| 1994 | −kms_frontbuffer_tracking@fbc-2p-scndscrn-indfb-plflip-blt | |
| 1995 | −kms_frontbuffer_tracking@fbc-2p-scndscrn-shrfb-pgflip-blt | |
| 1996 | −kms_frontbuffer_tracking@fbc-2p-scndscrn-shrfb-msflip-blt | |
| 1997 | −kms_frontbuffer_tracking@fbc-2p-scndscrn-shrfb-plflip-blt | |
| 1998 | −kms_frontbuffer_tracking@psr-1p-primscrn-indfb-pgflip-blt | |
| 1999 | −kms_frontbuffer_tracking@psr-1p-primscrn-indfb-msflip-blt | |
| 2000 | −kms_frontbuffer_tracking@psr-1p-primscrn-indfb-plflip-blt | |
| 2001 | −kms_frontbuffer_tracking@psr-1p-primscrn-shrfb-pgflip-blt | |
| 2002 | −kms_frontbuffer_tracking@psr-1p-primscrn-shrfb-msflip-blt | |
| 2003 | −kms_frontbuffer_tracking@psr-1p-primscrn-shrfb-plflip-blt | |
| 2004 | −kms_frontbuffer_tracking@psr-2p-primscrn-indfb-pgflip-blt | |
| 2005 | −kms_frontbuffer_tracking@psr-2p-primscrn-indfb-msflip-blt | |
| 2006 | −kms_frontbuffer_tracking@psr-2p-primscrn-indfb-plflip-blt | |
| 2007 | −kms_frontbuffer_tracking@psr-2p-primscrn-shrfb-pgflip-blt | |
| 2008 | −kms_frontbuffer_tracking@psr-2p-primscrn-shrfb-msflip-blt | |
| 2009 | −kms_frontbuffer_tracking@psr-2p-primscrn-shrfb-plflip-blt | |
| 2010 | −kms_frontbuffer_tracking@psr-2p-scndscrn-indfb-pgflip-blt | |
| 2011 | −kms_frontbuffer_tracking@psr-2p-scndscrn-indfb-msflip-blt | |
| 2012 | −kms_frontbuffer_tracking@psr-2p-scndscrn-indfb-plflip-blt | |
| 2013 | −kms_frontbuffer_tracking@psr-2p-scndscrn-shrfb-pgflip-blt | |
| 2014 | −kms_frontbuffer_tracking@psr-2p-scndscrn-shrfb-msflip-blt | |
| 2015 | −kms_frontbuffer_tracking@psr-2p-scndscrn-shrfb-plflip-blt | |
| 2016 | −kms_frontbuffer_tracking@fbcpsr-1p-primscrn-indfb-pgflip-blt | |
| 2017 | −kms_frontbuffer_tracking@fbcpsr-1p-primscrn-indfb-msflip-blt | |
| 2018 | −kms_frontbuffer_tracking@fbcpsr-1p-primscrn-indfb-plflip-blt | |
| 2019 | −kms_frontbuffer_tracking@fbcpsr-1p-primscrn-shrfb-pgflip-blt | |
| 2020 | −kms_frontbuffer_tracking@fbcpsr-1p-primscrn-shrfb-msflip-blt | |
| 2021 | −kms_frontbuffer_tracking@fbcpsr-1p-primscrn-shrfb-plflip-blt | |
| 2022 | −kms_frontbuffer_tracking@fbcpsr-2p-primscrn-indfb-pgflip-blt | |
| 2023 | −kms_frontbuffer_tracking@fbcpsr-2p-primscrn-indfb-msflip-blt | |
| 2024 | −kms_frontbuffer_tracking@fbcpsr-2p-primscrn-indfb-plflip-blt | |
| 2025 | −kms_frontbuffer_tracking@fbcpsr-2p-primscrn-shrfb-pgflip-blt | |
| 2026 | −kms_frontbuffer_tracking@fbcpsr-2p-primscrn-shrfb-msflip-blt | |
| 2027 | −kms_frontbuffer_tracking@fbcpsr-2p-primscrn-shrfb-plflip-blt | |
| 2028 | −kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-indfb-pgflip-blt | |
| 2029 | −kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-indfb-msflip-blt | |
| 2030 | −kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-indfb-plflip-blt | |
| 2031 | −kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-shrfb-pgflip-blt | |
| 2032 | −kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-shrfb-msflip-blt | |
| 2033 | −kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-shrfb-plflip-blt | |
| 2034 | −kms_frontbuffer_tracking@drrs-1p-primscrn-indfb-pgflip-blt | |
| 2035 | −kms_frontbuffer_tracking@drrs-1p-primscrn-indfb-msflip-blt | |
| 2036 | −kms_frontbuffer_tracking@drrs-1p-primscrn-indfb-plflip-blt | |
| 2037 | −kms_frontbuffer_tracking@drrs-1p-primscrn-shrfb-pgflip-blt | |
| 2038 | −kms_frontbuffer_tracking@drrs-1p-primscrn-shrfb-msflip-blt | |
| 2039 | −kms_frontbuffer_tracking@drrs-1p-primscrn-shrfb-plflip-blt | |
| 2040 | −kms_frontbuffer_tracking@drrs-2p-primscrn-indfb-pgflip-blt | |
| 2041 | −kms_frontbuffer_tracking@drrs-2p-primscrn-indfb-msflip-blt | |
| 2042 | −kms_frontbuffer_tracking@drrs-2p-primscrn-indfb-plflip-blt | |
| 2043 | −kms_frontbuffer_tracking@drrs-2p-primscrn-shrfb-pgflip-blt | |
| 2044 | −kms_frontbuffer_tracking@drrs-2p-primscrn-shrfb-msflip-blt | |
| 2045 | −kms_frontbuffer_tracking@drrs-2p-primscrn-shrfb-plflip-blt | |
| 2046 | −kms_frontbuffer_tracking@drrs-2p-scndscrn-indfb-pgflip-blt | |
| 2047 | −kms_frontbuffer_tracking@drrs-2p-scndscrn-indfb-msflip-blt | |
| 2048 | −kms_frontbuffer_tracking@drrs-2p-scndscrn-indfb-plflip-blt | |
| 2049 | −kms_frontbuffer_tracking@drrs-2p-scndscrn-shrfb-pgflip-blt | |
| 2050 | −kms_frontbuffer_tracking@drrs-2p-scndscrn-shrfb-msflip-blt | |
| 2051 | −kms_frontbuffer_tracking@drrs-2p-scndscrn-shrfb-plflip-blt | |
| 2052 | −kms_frontbuffer_tracking@fbcdrrs-1p-primscrn-indfb-pgflip-blt | |
| 2053 | −kms_frontbuffer_tracking@fbcdrrs-1p-primscrn-indfb-msflip-blt | |
| 2054 | −kms_frontbuffer_tracking@fbcdrrs-1p-primscrn-indfb-plflip-blt | |
| 2055 | −kms_frontbuffer_tracking@fbcdrrs-1p-primscrn-shrfb-pgflip-blt | |
| 2056 | −kms_frontbuffer_tracking@fbcdrrs-1p-primscrn-shrfb-msflip-blt | |
| 2057 | −kms_frontbuffer_tracking@fbcdrrs-1p-primscrn-shrfb-plflip-blt | |
| 2058 | −kms_frontbuffer_tracking@fbcdrrs-2p-primscrn-indfb-pgflip-blt | |
| 2059 | −kms_frontbuffer_tracking@fbcdrrs-2p-primscrn-indfb-msflip-blt | |
| 2060 | −kms_frontbuffer_tracking@fbcdrrs-2p-primscrn-indfb-plflip-blt | |
| 2061 | −kms_frontbuffer_tracking@fbcdrrs-2p-primscrn-shrfb-pgflip-blt | |
| 2062 | −kms_frontbuffer_tracking@fbcdrrs-2p-primscrn-shrfb-msflip-blt | |
| 2063 | −kms_frontbuffer_tracking@fbcdrrs-2p-primscrn-shrfb-plflip-blt | |
| 2064 | −kms_frontbuffer_tracking@fbcdrrs-2p-scndscrn-indfb-pgflip-blt | |
| 2065 | −kms_frontbuffer_tracking@fbcdrrs-2p-scndscrn-indfb-msflip-blt | |
| 2066 | −kms_frontbuffer_tracking@fbcdrrs-2p-scndscrn-indfb-plflip-blt | |
| 2067 | −kms_frontbuffer_tracking@fbcdrrs-2p-scndscrn-shrfb-pgflip-blt | |
| 2068 | −kms_frontbuffer_tracking@fbcdrrs-2p-scndscrn-shrfb-msflip-blt | |
| 2069 | −kms_frontbuffer_tracking@fbcdrrs-2p-scndscrn-shrfb-plflip-blt | |
| 2070 | −kms_frontbuffer_tracking@psrdrrs-1p-primscrn-indfb-pgflip-blt | |
| 2071 | −kms_frontbuffer_tracking@psrdrrs-1p-primscrn-indfb-msflip-blt | |
| 2072 | −kms_frontbuffer_tracking@psrdrrs-1p-primscrn-indfb-plflip-blt | |
| 2073 | −kms_frontbuffer_tracking@psrdrrs-1p-primscrn-shrfb-pgflip-blt | |
| 2074 | −kms_frontbuffer_tracking@psrdrrs-1p-primscrn-shrfb-msflip-blt | |
| 2075 | −kms_frontbuffer_tracking@psrdrrs-1p-primscrn-shrfb-plflip-blt | |
| 2076 | −kms_frontbuffer_tracking@psrdrrs-2p-primscrn-indfb-pgflip-blt | |
| 2077 | −kms_frontbuffer_tracking@psrdrrs-2p-primscrn-indfb-msflip-blt | |
| 2078 | −kms_frontbuffer_tracking@psrdrrs-2p-primscrn-indfb-plflip-blt | |
| 2079 | −kms_frontbuffer_tracking@psrdrrs-2p-primscrn-shrfb-pgflip-blt | |
| 2080 | −kms_frontbuffer_tracking@psrdrrs-2p-primscrn-shrfb-msflip-blt | |
| 2081 | −kms_frontbuffer_tracking@psrdrrs-2p-primscrn-shrfb-plflip-blt | |
| 2082 | −kms_frontbuffer_tracking@psrdrrs-2p-scndscrn-indfb-pgflip-blt | |
| 2083 | −kms_frontbuffer_tracking@psrdrrs-2p-scndscrn-indfb-msflip-blt | |
| 2084 | −kms_frontbuffer_tracking@psrdrrs-2p-scndscrn-indfb-plflip-blt | |
| 2085 | −kms_frontbuffer_tracking@psrdrrs-2p-scndscrn-shrfb-pgflip-blt | |
| 2086 | −kms_frontbuffer_tracking@psrdrrs-2p-scndscrn-shrfb-msflip-blt | |
| 2087 | −kms_frontbuffer_tracking@psrdrrs-2p-scndscrn-shrfb-plflip-blt | |
| 2088 | −kms_frontbuffer_tracking@fbcpsrdrrs-1p-primscrn-indfb-pgflip-blt | |
| 2089 | −kms_frontbuffer_tracking@fbcpsrdrrs-1p-primscrn-indfb-msflip-blt | |
| 2090 | −kms_frontbuffer_tracking@fbcpsrdrrs-1p-primscrn-indfb-plflip-blt | |
| 2091 | −kms_frontbuffer_tracking@fbcpsrdrrs-1p-primscrn-shrfb-pgflip-blt | |
| 2092 | −kms_frontbuffer_tracking@fbcpsrdrrs-1p-primscrn-shrfb-msflip-blt | |
| 2093 | −kms_frontbuffer_tracking@fbcpsrdrrs-1p-primscrn-shrfb-plflip-blt | |
| 2094 | −kms_frontbuffer_tracking@fbcpsrdrrs-2p-primscrn-indfb-pgflip-blt | |
| 2095 | −kms_frontbuffer_tracking@fbcpsrdrrs-2p-primscrn-indfb-msflip-blt | |
| 2096 | −kms_frontbuffer_tracking@fbcpsrdrrs-2p-primscrn-indfb-plflip-blt | |
| 2097 | −kms_frontbuffer_tracking@fbcpsrdrrs-2p-primscrn-shrfb-pgflip-blt | |
| 2098 | −kms_frontbuffer_tracking@fbcpsrdrrs-2p-primscrn-shrfb-msflip-blt | |
| 2099 | −kms_frontbuffer_tracking@fbcpsrdrrs-2p-primscrn-shrfb-plflip-blt | |
| 2100 | −kms_frontbuffer_tracking@fbcpsrdrrs-2p-scndscrn-indfb-pgflip-blt | |
| 2101 | −kms_frontbuffer_tracking@fbcpsrdrrs-2p-scndscrn-indfb-msflip-blt | |
| 2102 | −kms_frontbuffer_tracking@fbcpsrdrrs-2p-scndscrn-indfb-plflip-blt | |
| 2103 | −kms_frontbuffer_tracking@fbcpsrdrrs-2p-scndscrn-shrfb-pgflip-blt | |
| 2104 | −kms_frontbuffer_tracking@fbcpsrdrrs-2p-scndscrn-shrfb-msflip-blt | |
| 2105 | −kms_frontbuffer_tracking@fbcpsrdrrs-2p-scndscrn-shrfb-plflip-blt | |
| 2106 | −kms_frontbuffer_tracking@fbc-1p-indfb-fliptrack-mmap-gtt | |
| 2107 | −kms_frontbuffer_tracking@fbc-1p-shrfb-fliptrack-mmap-gtt | |
| 2108 | −kms_frontbuffer_tracking@fbc-2p-indfb-fliptrack-mmap-gtt | |
| 2109 | −kms_frontbuffer_tracking@fbc-2p-shrfb-fliptrack-mmap-gtt | |
| 2110 | −kms_frontbuffer_tracking@fbcpsr-1p-indfb-fliptrack-mmap-gtt | |
| 2111 | −kms_frontbuffer_tracking@fbcpsr-1p-shrfb-fliptrack-mmap-gtt | |
| 2112 | −kms_frontbuffer_tracking@fbcpsr-2p-indfb-fliptrack-mmap-gtt | |
| 2113 | −kms_frontbuffer_tracking@fbcpsr-2p-shrfb-fliptrack-mmap-gtt | |
| 2114 | −kms_frontbuffer_tracking@fbcdrrs-1p-indfb-fliptrack-mmap-gtt | |
| 2115 | −kms_frontbuffer_tracking@fbcdrrs-1p-shrfb-fliptrack-mmap-gtt | |
| 2116 | −kms_frontbuffer_tracking@fbcdrrs-2p-indfb-fliptrack-mmap-gtt | |
| 2117 | −kms_frontbuffer_tracking@fbcdrrs-2p-shrfb-fliptrack-mmap-gtt | |
| 2118 | −kms_frontbuffer_tracking@fbcpsrdrrs-1p-indfb-fliptrack-mmap-gtt | |
| 2119 | −kms_frontbuffer_tracking@fbcpsrdrrs-1p-shrfb-fliptrack-mmap-gtt | |
| 2120 | −kms_frontbuffer_tracking@fbcpsrdrrs-2p-indfb-fliptrack-mmap-gtt | |
| 2121 | −kms_frontbuffer_tracking@fbcpsrdrrs-2p-shrfb-fliptrack-mmap-gtt | |
| 2122 | −kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-move | |
| 2123 | −kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-onoff | |
| 2124 | −kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-move | |
| 2125 | −kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-onoff | |
| 2126 | −kms_frontbuffer_tracking@fbc-2p-primscrn-cur-indfb-move | |
| 2127 | −kms_frontbuffer_tracking@fbc-2p-primscrn-cur-indfb-onoff | |
| 2128 | −kms_frontbuffer_tracking@fbc-2p-primscrn-spr-indfb-move | |
| 2129 | −kms_frontbuffer_tracking@fbc-2p-primscrn-spr-indfb-onoff | |
| 2130 | −kms_frontbuffer_tracking@fbc-2p-scndscrn-cur-indfb-move | |
| 2131 | −kms_frontbuffer_tracking@fbc-2p-scndscrn-cur-indfb-onoff | |
| 2132 | −kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-move | |
| 2133 | −kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-onoff | |
| 2134 | −kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-move | |
| 2135 | −kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-onoff | |
| 2136 | −kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-move | |
| 2137 | −kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-onoff | |
| 2138 | −kms_frontbuffer_tracking@psr-2p-primscrn-cur-indfb-move | |
| 2139 | −kms_frontbuffer_tracking@psr-2p-primscrn-cur-indfb-onoff | |
| 2140 | −kms_frontbuffer_tracking@psr-2p-primscrn-spr-indfb-move | |
| 2141 | −kms_frontbuffer_tracking@psr-2p-primscrn-spr-indfb-onoff | |
| 2142 | −kms_frontbuffer_tracking@psr-2p-scndscrn-cur-indfb-move | |
| 2143 | −kms_frontbuffer_tracking@psr-2p-scndscrn-cur-indfb-onoff | |
| 2144 | −kms_frontbuffer_tracking@psr-2p-scndscrn-spr-indfb-move | |
| 2145 | −kms_frontbuffer_tracking@psr-2p-scndscrn-spr-indfb-onoff | |
| 2146 | −kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-move | |
| 2147 | −kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-onoff | |
| 2148 | −kms_frontbuffer_tracking@fbcpsr-1p-primscrn-spr-indfb-move | |
| 2149 | −kms_frontbuffer_tracking@fbcpsr-1p-primscrn-spr-indfb-onoff | |
| 2150 | −kms_frontbuffer_tracking@fbcpsr-2p-primscrn-cur-indfb-move | |
| 2151 | −kms_frontbuffer_tracking@fbcpsr-2p-primscrn-cur-indfb-onoff | |
| 2152 | −kms_frontbuffer_tracking@fbcpsr-2p-primscrn-spr-indfb-move | |
| 2153 | −kms_frontbuffer_tracking@fbcpsr-2p-primscrn-spr-indfb-onoff | |
| 2154 | −kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-cur-indfb-move | |
| 2155 | −kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-cur-indfb-onoff | |
| 2156 | −kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-spr-indfb-move | |
| 2157 | −kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-spr-indfb-onoff | |
| 2158 | −kms_frontbuffer_tracking@drrs-1p-primscrn-cur-indfb-move | |
| 2159 | −kms_frontbuffer_tracking@drrs-1p-primscrn-cur-indfb-onoff | |
| 2160 | −kms_frontbuffer_tracking@drrs-1p-primscrn-spr-indfb-move | |
| 2161 | −kms_frontbuffer_tracking@drrs-1p-primscrn-spr-indfb-onoff | |
| 2162 | −kms_frontbuffer_tracking@drrs-2p-primscrn-cur-indfb-move | |
| 2163 | −kms_frontbuffer_tracking@drrs-2p-primscrn-cur-indfb-onoff | |
| 2164 | −kms_frontbuffer_tracking@drrs-2p-primscrn-spr-indfb-move | |
| 2165 | −kms_frontbuffer_tracking@drrs-2p-primscrn-spr-indfb-onoff | |
| 2166 | −kms_frontbuffer_tracking@drrs-2p-scndscrn-cur-indfb-move | |
| 2167 | −kms_frontbuffer_tracking@drrs-2p-scndscrn-cur-indfb-onoff | |
| 2168 | −kms_frontbuffer_tracking@drrs-2p-scndscrn-spr-indfb-move | |
| 2169 | −kms_frontbuffer_tracking@drrs-2p-scndscrn-spr-indfb-onoff | |
| 2170 | −kms_frontbuffer_tracking@fbcdrrs-1p-primscrn-cur-indfb-move | |
| 2171 | −kms_frontbuffer_tracking@fbcdrrs-1p-primscrn-cur-indfb-onoff | |
| 2172 | −kms_frontbuffer_tracking@fbcdrrs-1p-primscrn-spr-indfb-move | |
| 2173 | −kms_frontbuffer_tracking@fbcdrrs-1p-primscrn-spr-indfb-onoff | |
| 2174 | −kms_frontbuffer_tracking@fbcdrrs-2p-primscrn-cur-indfb-move | |
| 2175 | −kms_frontbuffer_tracking@fbcdrrs-2p-primscrn-cur-indfb-onoff | |
| 2176 | −kms_frontbuffer_tracking@fbcdrrs-2p-primscrn-spr-indfb-move | |
| 2177 | −kms_frontbuffer_tracking@fbcdrrs-2p-primscrn-spr-indfb-onoff | |
| 2178 | −kms_frontbuffer_tracking@fbcdrrs-2p-scndscrn-cur-indfb-move | |
| 2179 | −kms_frontbuffer_tracking@fbcdrrs-2p-scndscrn-cur-indfb-onoff | |
| 2180 | −kms_frontbuffer_tracking@fbcdrrs-2p-scndscrn-spr-indfb-move | |
| 2181 | −kms_frontbuffer_tracking@fbcdrrs-2p-scndscrn-spr-indfb-onoff | |
| 2182 | −kms_frontbuffer_tracking@psrdrrs-1p-primscrn-cur-indfb-move | |
| 2183 | −kms_frontbuffer_tracking@psrdrrs-1p-primscrn-cur-indfb-onoff | |
| 2184 | −kms_frontbuffer_tracking@psrdrrs-1p-primscrn-spr-indfb-move | |
| 2185 | −kms_frontbuffer_tracking@psrdrrs-1p-primscrn-spr-indfb-onoff | |
| 2186 | −kms_frontbuffer_tracking@psrdrrs-2p-primscrn-cur-indfb-move | |
| 2187 | −kms_frontbuffer_tracking@psrdrrs-2p-primscrn-cur-indfb-onoff | |
| 2188 | −kms_frontbuffer_tracking@psrdrrs-2p-primscrn-spr-indfb-move | |
| 2189 | −kms_frontbuffer_tracking@psrdrrs-2p-primscrn-spr-indfb-onoff | |
| 2190 | −kms_frontbuffer_tracking@psrdrrs-2p-scndscrn-cur-indfb-move | |
| 2191 | −kms_frontbuffer_tracking@psrdrrs-2p-scndscrn-cur-indfb-onoff | |
| 2192 | −kms_frontbuffer_tracking@psrdrrs-2p-scndscrn-spr-indfb-move | |
| 2193 | −kms_frontbuffer_tracking@psrdrrs-2p-scndscrn-spr-indfb-onoff | |
| 2194 | −kms_frontbuffer_tracking@fbcpsrdrrs-1p-primscrn-cur-indfb-move | |
| 2195 | −kms_frontbuffer_tracking@fbcpsrdrrs-1p-primscrn-cur-indfb-onoff | |
| 2196 | −kms_frontbuffer_tracking@fbcpsrdrrs-1p-primscrn-spr-indfb-move | |
| 2197 | −kms_frontbuffer_tracking@fbcpsrdrrs-1p-primscrn-spr-indfb-onoff | |
| 2198 | −kms_frontbuffer_tracking@fbcpsrdrrs-2p-primscrn-cur-indfb-move | |
| 2199 | −kms_frontbuffer_tracking@fbcpsrdrrs-2p-primscrn-cur-indfb-onoff | |
| 2200 | −kms_frontbuffer_tracking@fbcpsrdrrs-2p-primscrn-spr-indfb-move | |
| 2201 | −kms_frontbuffer_tracking@fbcpsrdrrs-2p-primscrn-spr-indfb-onoff | |
| 2202 | −kms_frontbuffer_tracking@fbcpsrdrrs-2p-scndscrn-cur-indfb-move | |
| 2203 | −kms_frontbuffer_tracking@fbcpsrdrrs-2p-scndscrn-cur-indfb-onoff | |
| 2204 | −kms_frontbuffer_tracking@fbcpsrdrrs-2p-scndscrn-spr-indfb-move | |
| 2205 | −kms_frontbuffer_tracking@fbcpsrdrrs-2p-scndscrn-spr-indfb-onoff | |
| 2206 | −kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-fullscreen | |
| 2207 | −kms_frontbuffer_tracking@fbc-2p-primscrn-spr-indfb-fullscreen | |
| 2208 | −kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-fullscreen | |
| 2209 | −kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-fullscreen | |
| 2210 | −kms_frontbuffer_tracking@psr-2p-primscrn-spr-indfb-fullscreen | |
| 2211 | −kms_frontbuffer_tracking@psr-2p-scndscrn-spr-indfb-fullscreen | |
| 2212 | −kms_frontbuffer_tracking@fbcpsr-1p-primscrn-spr-indfb-fullscreen | |
| 2213 | −kms_frontbuffer_tracking@fbcpsr-2p-primscrn-spr-indfb-fullscreen | |
| 2214 | −kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-spr-indfb-fullscreen | |
| 2215 | −kms_frontbuffer_tracking@drrs-1p-primscrn-spr-indfb-fullscreen | |
| 2216 | −kms_frontbuffer_tracking@drrs-2p-primscrn-spr-indfb-fullscreen | |
| 2217 | −kms_frontbuffer_tracking@drrs-2p-scndscrn-spr-indfb-fullscreen | |
| 2218 | −kms_frontbuffer_tracking@fbcdrrs-1p-primscrn-spr-indfb-fullscreen | |
| 2219 | −kms_frontbuffer_tracking@fbcdrrs-2p-primscrn-spr-indfb-fullscreen | |
| 2220 | −kms_frontbuffer_tracking@fbcdrrs-2p-scndscrn-spr-indfb-fullscreen | |
| 2221 | −kms_frontbuffer_tracking@psrdrrs-1p-primscrn-spr-indfb-fullscreen | |
| 2222 | −kms_frontbuffer_tracking@psrdrrs-2p-primscrn-spr-indfb-fullscreen | |
| 2223 | −kms_frontbuffer_tracking@psrdrrs-2p-scndscrn-spr-indfb-fullscreen | |
| 2224 | −kms_frontbuffer_tracking@fbcpsrdrrs-1p-primscrn-spr-indfb-fullscreen | |
| 2225 | −kms_frontbuffer_tracking@fbcpsrdrrs-2p-primscrn-spr-indfb-fullscreen | |
| 2226 | −kms_frontbuffer_tracking@fbcpsrdrrs-2p-scndscrn-spr-indfb-fullscreen | |
| 2227 | −kms_frontbuffer_tracking@fbc-1p-pri-indfb-multidraw | |
| 2228 | −kms_frontbuffer_tracking@fbc-2p-pri-indfb-multidraw | |
| 2229 | −kms_frontbuffer_tracking@psr-1p-pri-indfb-multidraw | |
| 2230 | −kms_frontbuffer_tracking@psr-2p-pri-indfb-multidraw | |
| 2231 | −kms_frontbuffer_tracking@fbcpsr-1p-pri-indfb-multidraw | |
| 2232 | −kms_frontbuffer_tracking@fbcpsr-2p-pri-indfb-multidraw | |
| 2233 | −kms_frontbuffer_tracking@drrs-1p-pri-indfb-multidraw | |
| 2234 | −kms_frontbuffer_tracking@drrs-2p-pri-indfb-multidraw | |
| 2235 | −kms_frontbuffer_tracking@fbcdrrs-1p-pri-indfb-multidraw | |
| 2236 | −kms_frontbuffer_tracking@fbcdrrs-2p-pri-indfb-multidraw | |
| 2237 | −kms_frontbuffer_tracking@psrdrrs-1p-pri-indfb-multidraw | |
| 2238 | −kms_frontbuffer_tracking@psrdrrs-2p-pri-indfb-multidraw | |
| 2239 | −kms_frontbuffer_tracking@fbcpsrdrrs-1p-pri-indfb-multidraw | |
| 2240 | −kms_frontbuffer_tracking@fbcpsrdrrs-2p-pri-indfb-multidraw | |
| 2241 | −kms_frontbuffer_tracking@fbc-farfromfence-mmap-gtt | |
| 2242 | −kms_frontbuffer_tracking@psr-farfromfence-mmap-gtt | |
| 2243 | −kms_frontbuffer_tracking@fbcpsr-farfromfence-mmap-gtt | |
| 2244 | −kms_frontbuffer_tracking@drrs-farfromfence-mmap-gtt | |
| 2245 | −kms_frontbuffer_tracking@fbcdrrs-farfromfence-mmap-gtt | |
| 2246 | −kms_frontbuffer_tracking@psrdrrs-farfromfence-mmap-gtt | |
| 2247 | −kms_frontbuffer_tracking@fbcpsrdrrs-farfromfence-mmap-gtt | |
| 2248 | −kms_frontbuffer_tracking@fbc-rgb565-draw-mmap-cpu | |
| 2249 | −kms_frontbuffer_tracking@fbc-rgb101010-draw-mmap-cpu | |
| 2250 | −kms_frontbuffer_tracking@fbc-rgb565-draw-mmap-gtt | |
| 2251 | −kms_frontbuffer_tracking@fbc-rgb101010-draw-mmap-gtt | |
| 2252 | −kms_frontbuffer_tracking@fbc-rgb565-draw-mmap-wc | |
| 2253 | −kms_frontbuffer_tracking@fbc-rgb101010-draw-mmap-wc | |
| 2254 | −kms_frontbuffer_tracking@fbc-rgb565-draw-pwrite | |
| 2255 | −kms_frontbuffer_tracking@fbc-rgb101010-draw-pwrite | |
| 2256 | −kms_frontbuffer_tracking@fbc-rgb565-draw-blt | |
| 2257 | −kms_frontbuffer_tracking@fbc-rgb101010-draw-blt | |
| 2258 | −kms_frontbuffer_tracking@fbc-rgb565-draw-render | |
| 2259 | −kms_frontbuffer_tracking@fbc-rgb101010-draw-render | |
| 2260 | −kms_frontbuffer_tracking@psr-rgb565-draw-mmap-cpu | |
| 2261 | −kms_frontbuffer_tracking@psr-rgb101010-draw-mmap-cpu | |
| 2262 | −kms_frontbuffer_tracking@psr-rgb565-draw-mmap-gtt | |
| 2263 | −kms_frontbuffer_tracking@psr-rgb101010-draw-mmap-gtt | |
| 2264 | −kms_frontbuffer_tracking@psr-rgb565-draw-mmap-wc | |
| 2265 | −kms_frontbuffer_tracking@psr-rgb101010-draw-mmap-wc | |
| 2266 | −kms_frontbuffer_tracking@psr-rgb565-draw-pwrite | |
| 2267 | −kms_frontbuffer_tracking@psr-rgb101010-draw-pwrite | |
| 2268 | −kms_frontbuffer_tracking@psr-rgb565-draw-blt | |
| 2269 | −kms_frontbuffer_tracking@psr-rgb101010-draw-blt | |
| 2270 | −kms_frontbuffer_tracking@psr-rgb565-draw-render | |
| 2271 | −kms_frontbuffer_tracking@psr-rgb101010-draw-render | |
| 2272 | −kms_frontbuffer_tracking@fbcpsr-rgb565-draw-mmap-cpu | |
| 2273 | −kms_frontbuffer_tracking@fbcpsr-rgb101010-draw-mmap-cpu | |
| 2274 | −kms_frontbuffer_tracking@fbcpsr-rgb565-draw-mmap-gtt | |
| 2275 | −kms_frontbuffer_tracking@fbcpsr-rgb101010-draw-mmap-gtt | |
| 2276 | −kms_frontbuffer_tracking@fbcpsr-rgb565-draw-mmap-wc | |
| 2277 | −kms_frontbuffer_tracking@fbcpsr-rgb101010-draw-mmap-wc | |
| 2278 | −kms_frontbuffer_tracking@fbcpsr-rgb565-draw-pwrite | |
| 2279 | −kms_frontbuffer_tracking@fbcpsr-rgb101010-draw-pwrite | |
| 2280 | −kms_frontbuffer_tracking@fbcpsr-rgb565-draw-blt | |
| 2281 | −kms_frontbuffer_tracking@fbcpsr-rgb101010-draw-blt | |
| 2282 | −kms_frontbuffer_tracking@fbcpsr-rgb565-draw-render | |
| 2283 | −kms_frontbuffer_tracking@fbcpsr-rgb101010-draw-render | |
| 2284 | −kms_frontbuffer_tracking@drrs-rgb565-draw-mmap-cpu | |
| 2285 | −kms_frontbuffer_tracking@drrs-rgb101010-draw-mmap-cpu | |
| 2286 | −kms_frontbuffer_tracking@drrs-rgb565-draw-mmap-gtt | |
| 2287 | −kms_frontbuffer_tracking@drrs-rgb101010-draw-mmap-gtt | |
| 2288 | −kms_frontbuffer_tracking@drrs-rgb565-draw-mmap-wc | |
| 2289 | −kms_frontbuffer_tracking@drrs-rgb101010-draw-mmap-wc | |
| 2290 | −kms_frontbuffer_tracking@drrs-rgb565-draw-pwrite | |
| 2291 | −kms_frontbuffer_tracking@drrs-rgb101010-draw-pwrite | |
| 2292 | −kms_frontbuffer_tracking@drrs-rgb565-draw-blt | |
| 2293 | −kms_frontbuffer_tracking@drrs-rgb101010-draw-blt | |
| 2294 | −kms_frontbuffer_tracking@drrs-rgb565-draw-render | |
| 2295 | −kms_frontbuffer_tracking@drrs-rgb101010-draw-render | |
| 2296 | −kms_frontbuffer_tracking@fbcdrrs-rgb565-draw-mmap-cpu | |
| 2297 | −kms_frontbuffer_tracking@fbcdrrs-rgb101010-draw-mmap-cpu | |
| 2298 | −kms_frontbuffer_tracking@fbcdrrs-rgb565-draw-mmap-gtt | |
| 2299 | −kms_frontbuffer_tracking@fbcdrrs-rgb101010-draw-mmap-gtt | |
| 2300 | −kms_frontbuffer_tracking@fbcdrrs-rgb565-draw-mmap-wc | |
| 2301 | −kms_frontbuffer_tracking@fbcdrrs-rgb101010-draw-mmap-wc | |
| 2302 | −kms_frontbuffer_tracking@fbcdrrs-rgb565-draw-pwrite | |
| 2303 | −kms_frontbuffer_tracking@fbcdrrs-rgb101010-draw-pwrite | |
| 2304 | −kms_frontbuffer_tracking@fbcdrrs-rgb565-draw-blt | |
| 2305 | −kms_frontbuffer_tracking@fbcdrrs-rgb101010-draw-blt | |
| 2306 | −kms_frontbuffer_tracking@fbcdrrs-rgb565-draw-render | |
| 2307 | −kms_frontbuffer_tracking@fbcdrrs-rgb101010-draw-render | |
| 2308 | −kms_frontbuffer_tracking@psrdrrs-rgb565-draw-mmap-cpu | |
| 2309 | −kms_frontbuffer_tracking@psrdrrs-rgb101010-draw-mmap-cpu | |
| 2310 | −kms_frontbuffer_tracking@psrdrrs-rgb565-draw-mmap-gtt | |
| 2311 | −kms_frontbuffer_tracking@psrdrrs-rgb101010-draw-mmap-gtt | |
| 2312 | −kms_frontbuffer_tracking@psrdrrs-rgb565-draw-mmap-wc | |
| 2313 | −kms_frontbuffer_tracking@psrdrrs-rgb101010-draw-mmap-wc | |
| 2314 | −kms_frontbuffer_tracking@psrdrrs-rgb565-draw-pwrite | |
| 2315 | −kms_frontbuffer_tracking@psrdrrs-rgb101010-draw-pwrite | |
| 2316 | −kms_frontbuffer_tracking@psrdrrs-rgb565-draw-blt | |
| 2317 | −kms_frontbuffer_tracking@psrdrrs-rgb101010-draw-blt | |
| 2318 | −kms_frontbuffer_tracking@psrdrrs-rgb565-draw-render | |
| 2319 | −kms_frontbuffer_tracking@psrdrrs-rgb101010-draw-render | |
| 2320 | −kms_frontbuffer_tracking@fbcpsrdrrs-rgb565-draw-mmap-cpu | |
| 2321 | −kms_frontbuffer_tracking@fbcpsrdrrs-rgb101010-draw-mmap-cpu | |
| 2322 | −kms_frontbuffer_tracking@fbcpsrdrrs-rgb565-draw-mmap-gtt | |
| 2323 | −kms_frontbuffer_tracking@fbcpsrdrrs-rgb101010-draw-mmap-gtt | |
| 2324 | −kms_frontbuffer_tracking@fbcpsrdrrs-rgb565-draw-mmap-wc | |
| 2325 | −kms_frontbuffer_tracking@fbcpsrdrrs-rgb101010-draw-mmap-wc | |
| 2326 | −kms_frontbuffer_tracking@fbcpsrdrrs-rgb565-draw-pwrite | |
| 2327 | −kms_frontbuffer_tracking@fbcpsrdrrs-rgb101010-draw-pwrite | |
| 2328 | −kms_frontbuffer_tracking@fbcpsrdrrs-rgb565-draw-blt | |
| 2329 | −kms_frontbuffer_tracking@fbcpsrdrrs-rgb101010-draw-blt | |
| 2330 | −kms_frontbuffer_tracking@fbcpsrdrrs-rgb565-draw-render | |
| 2331 | −kms_frontbuffer_tracking@fbcpsrdrrs-rgb101010-draw-render | |
| 2332 | −kms_frontbuffer_tracking@fbc-indfb-scaledprimary | |
| 2333 | −kms_frontbuffer_tracking@fbc-shrfb-scaledprimary | |
| 2334 | −kms_frontbuffer_tracking@psr-indfb-scaledprimary | |
| 2335 | −kms_frontbuffer_tracking@psr-shrfb-scaledprimary | |
| 2336 | −kms_frontbuffer_tracking@fbcpsr-indfb-scaledprimary | |
| 2337 | −kms_frontbuffer_tracking@fbcpsr-shrfb-scaledprimary | |
| 2338 | −kms_frontbuffer_tracking@drrs-indfb-scaledprimary | |
| 2339 | −kms_frontbuffer_tracking@drrs-shrfb-scaledprimary | |
| 2340 | −kms_frontbuffer_tracking@fbcdrrs-indfb-scaledprimary | |
| 2341 | −kms_frontbuffer_tracking@fbcdrrs-shrfb-scaledprimary | |
| 2342 | −kms_frontbuffer_tracking@psrdrrs-indfb-scaledprimary | |
| 2343 | −kms_frontbuffer_tracking@psrdrrs-shrfb-scaledprimary | |
| 2344 | −kms_frontbuffer_tracking@fbcpsrdrrs-indfb-scaledprimary | |
| 2345 | −kms_frontbuffer_tracking@fbcpsrdrrs-shrfb-scaledprimary | |
| 2346 | −kms_frontbuffer_tracking@fbc-modesetfrombusy | |
| 2347 | −kms_frontbuffer_tracking@fbc-stridechange | |
| 2348 | −kms_frontbuffer_tracking@fbc-tiling-linear | |
| 2349 | −kms_frontbuffer_tracking@fbc-tiling-y | |
| 2350 | −kms_frontbuffer_tracking@fbc-tiling-4 | |
| 2351 | −kms_frontbuffer_tracking@fbc-suspend | |
| 2352 | −kms_frontbuffer_tracking@psr-modesetfrombusy | |
| 2353 | −kms_frontbuffer_tracking@psr-slowdraw | |
| 2354 | −kms_frontbuffer_tracking@psr-suspend | |
| 2355 | −kms_frontbuffer_tracking@fbcpsr-modesetfrombusy | |
| 2356 | −kms_frontbuffer_tracking@fbcpsr-stridechange | |
| 2357 | −kms_frontbuffer_tracking@fbcpsr-tiling-linear | |
| 2358 | −kms_frontbuffer_tracking@fbcpsr-tiling-y | |
| 2359 | −kms_frontbuffer_tracking@fbcpsr-tiling-4 | |
| 2360 | −kms_frontbuffer_tracking@fbcpsr-slowdraw | |
| 2361 | −kms_frontbuffer_tracking@fbcpsr-suspend | |
| 2362 | −kms_frontbuffer_tracking@drrs-modesetfrombusy | |
| 2363 | −kms_frontbuffer_tracking@drrs-slowdraw | |
| 2364 | −kms_frontbuffer_tracking@drrs-suspend | |
| 2365 | −kms_frontbuffer_tracking@fbcdrrs-modesetfrombusy | |
| 2366 | −kms_frontbuffer_tracking@fbcdrrs-stridechange | |
| 2367 | −kms_frontbuffer_tracking@fbcdrrs-tiling-linear | |
| 2368 | −kms_frontbuffer_tracking@fbcdrrs-tiling-y | |
| 2369 | −kms_frontbuffer_tracking@fbcdrrs-tiling-4 | |
| 2370 | −kms_frontbuffer_tracking@fbcdrrs-slowdraw | |
| 2371 | −kms_frontbuffer_tracking@fbcdrrs-suspend | |
| 2372 | −kms_frontbuffer_tracking@psrdrrs-modesetfrombusy | |
| 2373 | −kms_frontbuffer_tracking@psrdrrs-slowdraw | |
| 2374 | −kms_frontbuffer_tracking@psrdrrs-suspend | |
| 2375 | −kms_frontbuffer_tracking@fbcpsrdrrs-modesetfrombusy | |
| 2376 | −kms_frontbuffer_tracking@fbcpsrdrrs-stridechange | |
| 2377 | −kms_frontbuffer_tracking@fbcpsrdrrs-tiling-linear | |
| 2378 | −kms_frontbuffer_tracking@fbcpsrdrrs-tiling-y | |
| 2379 | −kms_frontbuffer_tracking@fbcpsrdrrs-tiling-4 | |
| 2380 | −kms_frontbuffer_tracking@fbcpsrdrrs-slowdraw | |
| 2381 | −kms_frontbuffer_tracking@fbcpsrdrrs-suspend | |
| 2382 | −kms_frontbuffer_tracking@basic | |
| 2383 | −kms_getfb@getfb-handle-zero | |
| 2384 | −kms_getfb@getfb-handle-valid | |
| 2385 | −kms_getfb@getfb-handle-closed | |
| 2386 | −kms_getfb@getfb-handle-not-fb | |
| 2387 | −kms_getfb@getfb-addfb-different-handles | |
| 2388 | −kms_getfb@getfb-repeated-different-handles | |
| 2389 | −kms_getfb@getfb-reject-ccs | |
| 2390 | −kms_getfb@getfb2-handle-zero | |
| 2391 | −kms_getfb@getfb2-handle-closed | |
| 2392 | −kms_getfb@getfb2-handle-not-fb | |
| 2393 | −kms_getfb@getfb2-accept-ccs | |
| 2394 | −kms_getfb@getfb2-into-addfb2 | |
| 2395 | −kms_getfb@getfb-handle-protection | |
| 2396 | −kms_getfb@getfb2-handle-protection | |
| 2397 | −kms_hdmi_inject@inject-4k | |
| 2398 | −kms_hdmi_inject@inject-audio | |
| 2399 | −kms_hdr@bpc-switch | |
| 2400 | −kms_hdr@bpc-switch-dpms | |
| 2401 | −kms_hdr@bpc-switch-suspend | |
| 2402 | −kms_hdr@static-toggle | |
| 2403 | −kms_hdr@static-toggle-dpms | |
| 2404 | −kms_hdr@static-toggle-suspend | |
| 2405 | −kms_hdr@static-swap | |
| 2406 | −kms_hdr@invalid-metadata-sizes | |
| 2407 | −kms_hdr@invalid-hdr | |
| 2408 | −kms_invalid_mode@clock-too-high | |
| 2409 | −kms_invalid_mode@zero-clock | |
| 2410 | −kms_invalid_mode@int-max-clock | |
| 2411 | −kms_invalid_mode@uint-max-clock | |
| 2412 | −kms_invalid_mode@zero-hdisplay | |
| 2413 | −kms_invalid_mode@zero-vdisplay | |
| 2414 | −kms_invalid_mode@bad-hsync-start | |
| 2415 | −kms_invalid_mode@bad-vsync-start | |
| 2416 | −kms_invalid_mode@bad-hsync-end | |
| 2417 | −kms_invalid_mode@bad-vsync-end | |
| 2418 | −kms_invalid_mode@bad-htotal | |
| 2419 | −kms_invalid_mode@bad-vtotal | |
| 2420 | −kms_legacy_colorkey@basic | |
| 2421 | −kms_legacy_colorkey@invalid-plane | |
| 2422 | −kms_multipipe_modeset@basic-max-pipe-crc-check | |
| 2423 | −kms_panel_fitting@legacy | |
| 2424 | −kms_panel_fitting@atomic-fastset | |
| 2425 | −kms_pipe_b_c_ivb@pipe-B-dpms-off-modeset-pipe-C | |
| 2426 | −kms_pipe_b_c_ivb@pipe-B-double-modeset-then-modeset-pipe-C | |
| 2427 | −kms_pipe_b_c_ivb@disable-pipe-B-enable-pipe-C | |
| 2428 | −kms_pipe_b_c_ivb@from-pipe-C-to-B-with-3-lanes | |
| 2429 | −kms_pipe_b_c_ivb@enable-pipe-C-while-B-has-3-lanes | |
| 2430 | −kms_pipe_crc_basic@bad-source | |
| 2431 | −kms_pipe_crc_basic@read-crc | |
| 2432 | −kms_pipe_crc_basic@read-crc-frame-sequence | |
| 2433 | −kms_pipe_crc_basic@nonblocking-crc | |
| 2434 | −kms_pipe_crc_basic@nonblocking-crc-frame-sequence | |
| 2435 | −kms_pipe_crc_basic@suspend-read-crc | |
| 2436 | −kms_pipe_crc_basic@hang-read-crc | |
| 2437 | −kms_pipe_crc_basic@disable-crc-after-crtc | |
| 2438 | −kms_pipe_crc_basic@compare-crc-sanitycheck-xr24 | |
| 2439 | −kms_pipe_crc_basic@compare-crc-sanitycheck-nv12 | |
| 2440 | −kms_plane@pixel-format | |
| 2441 | −kms_plane@pixel-format-source-clamping | |
| 2442 | −kms_plane@plane-position-covered | |
| 2443 | −kms_plane@plane-position-hole | |
| 2444 | −kms_plane@plane-position-hole-dpms | |
| 2445 | −kms_plane@plane-panning-top-left | |
| 2446 | −kms_plane@plane-panning-bottom-right | |
| 2447 | −kms_plane@plane-panning-bottom-right-suspend | |
| 2448 | −kms_plane@planar-pixel-format-settings | |
| 2449 | −kms_plane_alpha_blend@alpha-basic | |
| 2450 | −kms_plane_alpha_blend@alpha-7efc | |
| 2451 | −kms_plane_alpha_blend@coverage-7efc | |
| 2452 | −kms_plane_alpha_blend@coverage-vs-premult-vs-constant | |
| 2453 | −kms_plane_alpha_blend@alpha-transparent-fb | |
| 2454 | −kms_plane_alpha_blend@alpha-opaque-fb | |
| 2455 | −kms_plane_alpha_blend@constant-alpha-min | |
| 2456 | −kms_plane_alpha_blend@constant-alpha-mid | |
| 2457 | −kms_plane_alpha_blend@constant-alpha-max | |
| 2458 | −kms_plane_cursor@primary | |
| 2459 | −kms_plane_cursor@overlay | |
| 2460 | −kms_plane_cursor@viewport | |
| 2461 | −kms_plane_lowres@tiling-none | |
| 2462 | −kms_plane_lowres@tiling-x | |
| 2463 | −kms_plane_lowres@tiling-y | |
| 2464 | −kms_plane_lowres@tiling-yf | |
| 2465 | −kms_plane_lowres@tiling-4 | |
| 2466 | −kms_plane_multiple@tiling-none | |
| 2467 | −kms_plane_multiple@tiling-x | |
| 2468 | −kms_plane_multiple@tiling-y | |
| 2469 | −kms_plane_multiple@tiling-yf | |
| 2470 | −kms_plane_multiple@tiling-4 | |
| 2471 | −kms_plane_scaling@plane-upscale-20x20-with-pixel-format | |
| 2472 | −kms_plane_scaling@plane-upscale-factor-0-25-with-pixel-format | |
| 2473 | −kms_plane_scaling@plane-downscale-factor-0-25-with-pixel-format | |
| 2474 | −kms_plane_scaling@plane-downscale-factor-0-5-with-pixel-format | |
| 2475 | −kms_plane_scaling@plane-downscale-factor-0-75-with-pixel-format | |
| 2476 | −kms_plane_scaling@plane-scaler-unity-scaling-with-pixel-format | |
| 2477 | −kms_plane_scaling@plane-upscale-20x20-with-rotation | |
| 2478 | −kms_plane_scaling@plane-upscale-factor-0-25-with-rotation | |
| 2479 | −kms_plane_scaling@plane-downscale-factor-0-25-with-rotation | |
| 2480 | −kms_plane_scaling@plane-downscale-factor-0-5-with-rotation | |
| 2481 | −kms_plane_scaling@plane-downscale-factor-0-75-with-rotation | |
| 2482 | −kms_plane_scaling@plane-scaler-unity-scaling-with-rotation | |
| 2483 | −kms_plane_scaling@plane-upscale-20x20-with-modifiers | |
| 2484 | −kms_plane_scaling@plane-upscale-factor-0-25-with-modifiers | |
| 2485 | −kms_plane_scaling@plane-downscale-factor-0-25-with-modifiers | |
| 2486 | −kms_plane_scaling@plane-downscale-factor-0-5-with-modifiers | |
| 2487 | −kms_plane_scaling@plane-downscale-factor-0-75-with-modifiers | |
| 2488 | −kms_plane_scaling@plane-scaler-unity-scaling-with-modifiers | |
| 2489 | −kms_plane_scaling@plane-scaler-with-clipping-clamping-pixel-formats | |
| 2490 | −kms_plane_scaling@plane-scaler-with-clipping-clamping-rotation | |
| 2491 | −kms_plane_scaling@plane-scaler-with-clipping-clamping-modifiers | |
| 2492 | −kms_plane_scaling@planes-upscale-20x20 | |
| 2493 | −kms_plane_scaling@planes-upscale-factor-0-25 | |
| 2494 | −kms_plane_scaling@planes-scaler-unity-scaling | |
| 2495 | −kms_plane_scaling@planes-downscale-factor-0-25 | |
| 2496 | −kms_plane_scaling@planes-downscale-factor-0-5 | |
| 2497 | −kms_plane_scaling@planes-downscale-factor-0-75 | |
| 2498 | −kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-25 | |
| 2499 | −kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-5 | |
| 2500 | −kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-75 | |
| 2501 | −kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-25 | |
| 2502 | −kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-5 | |
| 2503 | −kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-75 | |
| 2504 | −kms_plane_scaling@planes-unity-scaling-downscale-factor-0-25 | |
| 2505 | −kms_plane_scaling@planes-unity-scaling-downscale-factor-0-5 | |
| 2506 | −kms_plane_scaling@planes-unity-scaling-downscale-factor-0-75 | |
| 2507 | −kms_plane_scaling@planes-downscale-factor-0-25-upscale-20x20 | |
| 2508 | −kms_plane_scaling@planes-downscale-factor-0-25-upscale-factor-0-25 | |
| 2509 | −kms_plane_scaling@planes-downscale-factor-0-25-unity-scaling | |
| 2510 | −kms_plane_scaling@planes-downscale-factor-0-5-upscale-20x20 | |
| 2511 | −kms_plane_scaling@planes-downscale-factor-0-5-upscale-factor-0-25 | |
| 2512 | −kms_plane_scaling@planes-downscale-factor-0-5-unity-scaling | |
| 2513 | −kms_plane_scaling@planes-downscale-factor-0-75-upscale-20x20 | |
| 2514 | −kms_plane_scaling@planes-downscale-factor-0-75-upscale-factor-0-25 | |
| 2515 | −kms_plane_scaling@planes-downscale-factor-0-75-unity-scaling | |
| 2516 | −kms_plane_scaling@intel-max-src-size | |
| 2517 | −kms_plane_scaling@invalid-num-scalers | |
| 2518 | −kms_plane_scaling@invalid-parameters | |
| 2519 | −kms_plane_scaling@2x-scaler-multi-pipe | |
| 2520 | −kms_prime@basic-crc-hybrid | |
| 2521 | −kms_prime@basic-modeset-hybrid | |
| 2522 | −kms_prime@D3hot | |
| 2523 | −kms_prime@basic-crc-vgem | |
| 2524 | −kms_prop_blob@basic | |
| 2525 | −kms_prop_blob@blob-prop-core | |
| 2526 | −kms_prop_blob@blob-prop-validate | |
| 2527 | −kms_prop_blob@blob-prop-lifetime | |
| 2528 | −kms_prop_blob@blob-multiple | |
| 2529 | −kms_prop_blob@invalid-get-prop-any | |
| 2530 | −kms_prop_blob@invalid-get-prop | |
| 2531 | −kms_prop_blob@invalid-set-prop-any | |
| 2532 | −kms_prop_blob@invalid-set-prop | |
| 2533 | −kms_properties@plane-properties-legacy | |
| 2534 | −kms_properties@plane-properties-atomic | |
| 2535 | −kms_properties@crtc-properties-legacy | |
| 2536 | −kms_properties@crtc-properties-atomic | |
| 2537 | −kms_properties@connector-properties-legacy | |
| 2538 | −kms_properties@connector-properties-atomic | |
| 2539 | −kms_properties@invalid-properties-legacy | |
| 2540 | −kms_properties@invalid-properties-atomic | |
| 2541 | −kms_properties@get_properties-sanity-atomic | |
| 2542 | −kms_properties@get_properties-sanity-non-atomic | |
| 2543 | −kms_psr@pr-basic | |
| 2544 | −kms_psr@pr-no-drrs | |
| 2545 | −kms_psr@pr-primary-page-flip | |
| 2546 | −kms_psr@pr-primary-mmap-gtt | |
| 2547 | −kms_psr@pr-primary-mmap-cpu | |
| 2548 | −kms_psr@pr-primary-blt | |
| 2549 | −kms_psr@pr-primary-render | |
| 2550 | −kms_psr@pr-sprite-mmap-gtt | |
| 2551 | −kms_psr@pr-cursor-mmap-gtt | |
| 2552 | −kms_psr@pr-sprite-mmap-cpu | |
| 2553 | −kms_psr@pr-cursor-mmap-cpu | |
| 2554 | −kms_psr@pr-sprite-blt | |
| 2555 | −kms_psr@pr-cursor-blt | |
| 2556 | −kms_psr@pr-sprite-render | |
| 2557 | −kms_psr@pr-cursor-render | |
| 2558 | −kms_psr@pr-sprite-plane-move | |
| 2559 | −kms_psr@pr-cursor-plane-move | |
| 2560 | −kms_psr@pr-sprite-plane-onoff | |
| 2561 | −kms_psr@pr-cursor-plane-onoff | |
| 2562 | −kms_psr@pr-dpms | |
| 2563 | −kms_psr@pr-suspend | |
| 2564 | −kms_psr@psr-basic | |
| 2565 | −kms_psr@psr-no-drrs | |
| 2566 | −kms_psr@psr-primary-page-flip | |
| 2567 | −kms_psr@psr-primary-mmap-gtt | |
| 2568 | −kms_psr@psr-primary-mmap-cpu | |
| 2569 | −kms_psr@psr-primary-blt | |
| 2570 | −kms_psr@psr-primary-render | |
| 2571 | −kms_psr@psr-sprite-mmap-gtt | |
| 2572 | −kms_psr@psr-cursor-mmap-gtt | |
| 2573 | −kms_psr@psr-sprite-mmap-cpu | |
| 2574 | −kms_psr@psr-cursor-mmap-cpu | |
| 2575 | −kms_psr@psr-sprite-blt | |
| 2576 | −kms_psr@psr-cursor-blt | |
| 2577 | −kms_psr@psr-sprite-render | |
| 2578 | −kms_psr@psr-cursor-render | |
| 2579 | −kms_psr@psr-sprite-plane-move | |
| 2580 | −kms_psr@psr-cursor-plane-move | |
| 2581 | −kms_psr@psr-sprite-plane-onoff | |
| 2582 | −kms_psr@psr-cursor-plane-onoff | |
| 2583 | −kms_psr@psr-dpms | |
| 2584 | −kms_psr@psr-suspend | |
| 2585 | −kms_psr@psr2-basic | |
| 2586 | −kms_psr@psr2-no-drrs | |
| 2587 | −kms_psr@psr2-primary-page-flip | |
| 2588 | −kms_psr@psr2-primary-mmap-gtt | |
| 2589 | −kms_psr@psr2-primary-mmap-cpu | |
| 2590 | −kms_psr@psr2-primary-blt | |
| 2591 | −kms_psr@psr2-primary-render | |
| 2592 | −kms_psr@psr2-sprite-mmap-gtt | |
| 2593 | −kms_psr@psr2-cursor-mmap-gtt | |
| 2594 | −kms_psr@psr2-sprite-mmap-cpu | |
| 2595 | −kms_psr@psr2-cursor-mmap-cpu | |
| 2596 | −kms_psr@psr2-sprite-blt | |
| 2597 | −kms_psr@psr2-cursor-blt | |
| 2598 | −kms_psr@psr2-sprite-render | |
| 2599 | −kms_psr@psr2-cursor-render | |
| 2600 | −kms_psr@psr2-sprite-plane-move | |
| 2601 | −kms_psr@psr2-cursor-plane-move | |
| 2602 | −kms_psr@psr2-sprite-plane-onoff | |
| 2603 | −kms_psr@psr2-cursor-plane-onoff | |
| 2604 | −kms_psr@psr2-dpms | |
| 2605 | −kms_psr@psr2-suspend | |
| 2606 | −kms_psr2_sf@primary-plane-update-sf-dmg-area | |
| 2607 | −kms_psr2_sf@primary-plane-update-sf-dmg-area-big-fb | |
| 2608 | −kms_psr2_sf@overlay-plane-update-sf-dmg-area | |
| 2609 | −kms_psr2_sf@cursor-plane-update-sf | |
| 2610 | −kms_psr2_sf@cursor-plane-move-continuous-sf | |
| 2611 | −kms_psr2_sf@cursor-plane-move-continuous-exceed-sf | |
| 2612 | −kms_psr2_sf@cursor-plane-move-continuous-exceed-fully-sf | |
| 2613 | −kms_psr2_sf@plane-move-sf-dmg-area | |
| 2614 | −kms_psr2_sf@overlay-plane-move-continuous-sf | |
| 2615 | −kms_psr2_sf@overlay-plane-move-continuous-exceed-sf | |
| 2616 | −kms_psr2_sf@overlay-plane-move-continuous-exceed-fully-sf | |
| 2617 | −kms_psr2_sf@overlay-primary-update-sf-dmg-area | |
| 2618 | −kms_psr2_sf@overlay-plane-update-continuous-sf | |
| 2619 | −kms_psr2_su@page_flip-XRGB8888 | |
| 2620 | −kms_psr2_su@page_flip-NV12 | |
| 2621 | −kms_psr2_su@page_flip-P010 | |
| 2622 | −kms_psr2_su@frontbuffer-XRGB8888 | |
| 2623 | −kms_pwrite_crc | |
| 2624 | −kms_rmfb@rmfb-ioctl | |
| 2625 | −kms_rmfb@close-fd | |
| 2626 | −kms_rotation_crc@primary-rotation-90 | |
| 2627 | −kms_rotation_crc@primary-rotation-180 | |
| 2628 | −kms_rotation_crc@primary-rotation-270 | |
| 2629 | −kms_rotation_crc@sprite-rotation-90 | |
| 2630 | −kms_rotation_crc@sprite-rotation-180 | |
| 2631 | −kms_rotation_crc@sprite-rotation-270 | |
| 2632 | −kms_rotation_crc@cursor-rotation-180 | |
| 2633 | −kms_rotation_crc@sprite-rotation-90-pos-100-0 | |
| 2634 | −kms_rotation_crc@bad-pixel-format | |
| 2635 | −kms_rotation_crc@bad-tiling | |
| 2636 | −kms_rotation_crc@primary-x-tiled-reflect-x-0 | |
| 2637 | −kms_rotation_crc@primary-x-tiled-reflect-x-180 | |
| 2638 | −kms_rotation_crc@primary-y-tiled-reflect-x-0 | |
| 2639 | −kms_rotation_crc@primary-y-tiled-reflect-x-90 | |
| 2640 | −kms_rotation_crc@primary-y-tiled-reflect-x-180 | |
| 2641 | −kms_rotation_crc@primary-y-tiled-reflect-x-270 | |
| 2642 | −kms_rotation_crc@primary-yf-tiled-reflect-x-0 | |
| 2643 | −kms_rotation_crc@primary-yf-tiled-reflect-x-90 | |
| 2644 | −kms_rotation_crc@primary-yf-tiled-reflect-x-180 | |
| 2645 | −kms_rotation_crc@primary-yf-tiled-reflect-x-270 | |
| 2646 | −kms_rotation_crc@primary-4-tiled-reflect-x-0 | |
| 2647 | −kms_rotation_crc@primary-4-tiled-reflect-x-180 | |
| 2648 | −kms_rotation_crc@multiplane-rotation | |
| 2649 | −kms_rotation_crc@multiplane-rotation-cropping-top | |
| 2650 | −kms_rotation_crc@multiplane-rotation-cropping-bottom | |
| 2651 | −kms_rotation_crc@exhaust-fences | |
| 2652 | −kms_scaling_modes@scaling-mode-full | |
| 2653 | −kms_scaling_modes@scaling-mode-center | |
| 2654 | −kms_scaling_modes@scaling-mode-full-aspect | |
| 2655 | −kms_scaling_modes@scaling-mode-none | |
| 2656 | −kms_selftest@drm_cmdline_parser | |
| 2657 | −kms_selftest@drm_damage_helper | |
| 2658 | −kms_selftest@drm_dp_mst_helper | |
| 2659 | −kms_selftest@drm_format_helper | |
| 2660 | −kms_selftest@drm_format | |
| 2661 | −kms_selftest@drm_framebuffer | |
| 2662 | −kms_selftest@drm_plane_helper | |
| 2663 | −kms_setmode@basic | |
| 2664 | −kms_setmode@basic-clone-single-crtc | |
| 2665 | −kms_setmode@invalid-clone-single-crtc | |
| 2666 | −kms_setmode@invalid-clone-exclusive-crtc | |
| 2667 | −kms_setmode@clone-exclusive-crtc | |
| 2668 | −kms_setmode@invalid-clone-single-crtc-stealing | |
| 2669 | −kms_sysfs_edid_timing | |
| 2670 | −kms_tv_load_detect@load-detect | |
| 2671 | −kms_universal_plane@universal-plane-functional | |
| 2672 | −kms_universal_plane@universal-plane-sanity | |
| 2673 | −kms_universal_plane@disable-primary-vs-flip | |
| 2674 | −kms_universal_plane@cursor-fb-leak | |
| 2675 | −kms_universal_plane@universal-plane-pageflip-windowed | |
| 2676 | −kms_vblank@invalid | |
| 2677 | −kms_vblank@crtc-id | |
| 2678 | −kms_vblank@accuracy-idle | |
| 2679 | −kms_vblank@query-idle | |
| 2680 | −kms_vblank@query-idle-hang | |
| 2681 | −kms_vblank@query-forked | |
| 2682 | −kms_vblank@query-forked-hang | |
| 2683 | −kms_vblank@query-busy | |
| 2684 | −kms_vblank@query-busy-hang | |
| 2685 | −kms_vblank@query-forked-busy | |
| 2686 | −kms_vblank@query-forked-busy-hang | |
| 2687 | −kms_vblank@wait-idle | |
| 2688 | −kms_vblank@wait-idle-hang | |
| 2689 | −kms_vblank@wait-forked | |
| 2690 | −kms_vblank@wait-forked-hang | |
| 2691 | −kms_vblank@wait-busy | |
| 2692 | −kms_vblank@wait-busy-hang | |
| 2693 | −kms_vblank@wait-forked-busy | |
| 2694 | −kms_vblank@wait-forked-busy-hang | |
| 2695 | −kms_vblank@ts-continuation-idle | |
| 2696 | −kms_vblank@ts-continuation-idle-hang | |
| 2697 | −kms_vblank@ts-continuation-dpms-rpm | |
| 2698 | −kms_vblank@ts-continuation-dpms-suspend | |
| 2699 | −kms_vblank@ts-continuation-suspend | |
| 2700 | −kms_vblank@ts-continuation-modeset | |
| 2701 | −kms_vblank@ts-continuation-modeset-hang | |
| 2702 | −kms_vblank@ts-continuation-modeset-rpm | |
| 2703 | −kms_vrr@flip-basic | |
| 2704 | −kms_vrr@flip-dpms | |
| 2705 | −kms_vrr@flip-suspend | |
| 2706 | −kms_vrr@flipline | |
| 2707 | −kms_vrr@negative-basic | |
| 2708 | −kms_writeback@writeback-pixel-formats | |
| 2709 | −kms_writeback@writeback-invalid-parameters | |
| 2710 | −kms_writeback@writeback-fb-id | |
| 2711 | −kms_writeback@writeback-check-output | |
| 2712 | −prime_mmap_kms@buffer-sharing | |
| 2713 | −msm_shrink@copy-gpu-sanitycheck-8 | |
| 2714 | −msm_shrink@copy-gpu-sanitycheck-32 | |
| 2715 | −msm_shrink@copy-gpu-8 | |
| 2716 | −msm_shrink@copy-gpu-32 | |
| 2717 | −msm_shrink@copy-gpu-madvise-8 | |
| 2718 | −msm_shrink@copy-gpu-madvise-32 | |
| 2719 | −msm_shrink@copy-gpu-oom-8 | |
| 2720 | −msm_shrink@copy-gpu-oom-32 | |
| 2721 | −msm_shrink@copy-mmap-sanitycheck-8 | |
| 2722 | −msm_shrink@copy-mmap-sanitycheck-32 | |
| 2723 | −msm_shrink@copy-mmap-8 | |
| 2724 | −msm_shrink@copy-mmap-32 | |
| 2725 | −msm_shrink@copy-mmap-madvise-8 | |
| 2726 | −msm_shrink@copy-mmap-madvise-32 | |
| 2727 | −msm_shrink@copy-mmap-oom-8 | |
| 2728 | −msm_shrink@copy-mmap-oom-32 | |
| 2729 | −msm_shrink@copy-mmap-dmabuf-sanitycheck-8 | |
| 2730 | −msm_shrink@copy-mmap-dmabuf-sanitycheck-32 | |
| 2731 | −msm_shrink@copy-mmap-dmabuf-8 | |
| 2732 | −msm_shrink@copy-mmap-dmabuf-32 | |
| 2733 | −msm_shrink@copy-mmap-dmabuf-madvise-8 | |
| 2734 | −msm_shrink@copy-mmap-dmabuf-madvise-32 | |
| 2735 | −msm_shrink@copy-mmap-dmabuf-oom-8 | |
| 2736 | −msm_shrink@copy-mmap-dmabuf-oom-32 | |
| 2737 | −msm_mapping@ring | |
| 2738 | −msm_mapping@sqefw | |
| 2739 | −msm_mapping@shadow | |
| 2740 | −msm_submitoverhead@submitbench-10-bos | |
| 2741 | −msm_submitoverhead@submitbench-10-bos-no-implicit-sync | |
| 2742 | −msm_submitoverhead@submitbench-100-bos | |
| 2743 | −msm_submitoverhead@submitbench-100-bos-no-implicit-sync | |
| 2744 | −msm_submitoverhead@submitbench-250-bos | |
| 2745 | −msm_submitoverhead@submitbench-250-bos-no-implicit-sync | |
| 2746 | −msm_submitoverhead@submitbench-500-bos | |
| 2747 | −msm_submitoverhead@submitbench-500-bos-no-implicit-sync | |
| 2748 | −msm_submitoverhead@submitbench-1000-bos | |
| 2749 | −msm_submitoverhead@submitbench-1000-bos-no-implicit-sync | |
| 2750 | −msm_recovery@hangcheck | |
| 2751 | −msm_recovery@gpu-fault | |
| 2752 | −msm_recovery@gpu-fault-parallel | |
| 2753 | −msm_recovery@iova-fault | |
| 2754 | −msm_submit@empty-submit | |
| 2755 | −msm_submit@invalid-queue-submit | |
| 2756 | −msm_submit@invalid-flags-submit | |
| 2757 | −msm_submit@invalid-in-fence-submit | |
| 2758 | −msm_submit@invalid-duplicate-bo-submit | |
| 2759 | −msm_submit@invalid-cmd-idx-submit | |
| 2760 | −msm_submit@invalid-cmd-type-submit | |
| 2761 | −msm_submit@valid-submit | |
| @@ -24,6 +24,7 @@ CONFIG_DRM=y · 23 unmodified lines | ||
| 24 | 24 | CONFIG_DRM_PANEL_SIMPLE=y |
| 25 | 25 | CONFIG_PWM_CROS_EC=y |
| 26 | 26 | CONFIG_BACKLIGHT_PWM=y |
| 27 | +CONFIG_DRM_VKMS=m | |
| 27 | 28 | |
| 28 | 29 | # Strip out some stuff we don't need for graphics testing, to reduce |
| 29 | 30 | # the build. |
| @@ -1,27 +1,40 @@ | ||
| 1 | +amdgpu/amd_abm@abm_enabled,Fail | |
| 2 | +amdgpu/amd_abm@abm_gradual,Fail | |
| 3 | +amdgpu/amd_abm@backlight_monotonic_abm,Fail | |
| 4 | +amdgpu/amd_abm@backlight_monotonic_basic,Fail | |
| 5 | +amdgpu/amd_assr@assr-links,Fail | |
| 6 | +amdgpu/amd_assr@assr-links-dpms,Fail | |
| 7 | +amdgpu/amd_mall@static-screen,Crash | |
| 8 | +amdgpu/amd_mode_switch@mode-switch-first-last-pipe-2,Crash | |
| 9 | +amdgpu/amd_plane@mpo-pan-nv12,Fail | |
| 10 | +amdgpu/amd_plane@mpo-pan-p010,Fail | |
| 11 | +amdgpu/amd_plane@mpo-pan-rgb,Crash | |
| 12 | +amdgpu/amd_plane@mpo-scale-nv12,Fail | |
| 13 | +amdgpu/amd_plane@mpo-scale-p010,Fail | |
| 14 | +amdgpu/amd_plane@mpo-scale-rgb,Crash | |
| 15 | +amdgpu/amd_plane@mpo-swizzle-toggle,Fail | |
| 16 | +amdgpu/amd_uvd_dec@amdgpu_uvd_decode,Fail | |
| 17 | +dumb_buffer@invalid-bpp,Fail | |
| 1 | 18 | kms_addfb_basic@bad-pitch-65536,Fail |
| 2 | 19 | kms_addfb_basic@bo-too-small,Fail |
| 3 | 20 | kms_addfb_basic@too-high,Fail |
| 4 | −kms_async_flips@async-flip-with-page-flip-events,Fail | |
| 5 | −kms_async_flips@crc,Fail | |
| 6 | −kms_async_flips@invalid-async-flip,Fail | |
| 7 | 21 | kms_atomic_transition@plane-all-modeset-transition-internal-panels,Fail |
| 8 | 22 | kms_atomic_transition@plane-all-transition,Fail |
| 9 | 23 | kms_atomic_transition@plane-all-transition-nonblocking,Fail |
| 10 | 24 | kms_atomic_transition@plane-toggle-modeset-transition,Fail |
| 11 | 25 | kms_atomic_transition@plane-use-after-nonblocking-unbind,Fail |
| 12 | −kms_bw@linear-tiling-1-displays-2560x1440p,Fail | |
| 13 | −kms_bw@linear-tiling-1-displays-3840x2160p,Fail | |
| 14 | −kms_bw@linear-tiling-2-displays-3840x2160p,Fail | |
| 15 | −kms_bw@linear-tiling-3-displays-1920x1080p,Fail | |
| 16 | −kms_color@degamma,Fail | |
| 26 | +kms_cursor_crc@cursor-onscreen-64x21,Fail | |
| 27 | +kms_cursor_crc@cursor-onscreen-64x64,Fail | |
| 28 | +kms_cursor_crc@cursor-random-64x21,Fail | |
| 29 | +kms_cursor_crc@cursor-random-64x64,Fail | |
| 17 | 30 | kms_cursor_crc@cursor-size-change,Fail |
| 18 | −kms_cursor_crc@pipe-A-cursor-size-change,Fail | |
| 19 | −kms_cursor_crc@pipe-B-cursor-size-change,Fail | |
| 31 | +kms_cursor_crc@cursor-sliding-64x21,Fail | |
| 32 | +kms_cursor_crc@cursor-sliding-64x64,Fail | |
| 20 | 33 | kms_flip@flip-vs-modeset-vs-hang,Fail |
| 21 | 34 | kms_flip@flip-vs-panning-vs-hang,Fail |
| 22 | −kms_hdr@bpc-switch,Fail | |
| 23 | −kms_hdr@bpc-switch-dpms,Fail | |
| 35 | +kms_lease@lease-uevent,Fail | |
| 24 | 36 | kms_plane@pixel-format,Fail |
| 25 | −kms_plane_multiple@atomic-pipe-A-tiling-none,Fail | |
| 26 | −kms_rmfb@close-fd,Fail | |
| 37 | +kms_plane_cursor@primary,Fail | |
| 27 | 38 | kms_rotation_crc@primary-rotation-180,Fail |
| 39 | +perf@i915-ref-count,Fail | |
| 40 | +tools_test@tools_test,Fail | |
| @@ -1 +1,8 @@ | ||
| 1 | +# Board Name: hp-11A-G6-EE-grunt | |
| 2 | +# Bug Report: https://lore.kernel.org/amd-gfx/3542730f-b8d7-404d-a947-b7a5e95d661c@collabora.com/T/#u | |
| 3 | +# IGT Version: 1.28-g0df7b9b97 | |
| 4 | +# Linux Version: 6.9.0-rc7 | |
| 5 | +# Failure Rate: 50 | |
| 1 | 6 | kms_async_flips@async-flip-with-page-flip-events |
| 7 | +kms_async_flips@crc | |
| 8 | +kms_plane@pixel-format-source-clamping | |
| @@ -1,2 +1,33 @@ | ||
| 1 | 1 | # Suspend to RAM seems to be broken on this machine |
| 2 | −.*suspend.* | |
| 2 | +.*suspend.* | |
| 3 | + | |
| 4 | +# Skip driver specific tests | |
| 5 | +msm_.* | |
| 6 | +nouveau_.* | |
| 7 | +panfrost_.* | |
| 8 | +^v3d.* | |
| 9 | +^vc4.* | |
| 10 | +^vmwgfx* | |
| 11 | + | |
| 12 | +# Skip intel specific tests | |
| 13 | +gem_.* | |
| 14 | +i915_.* | |
| 15 | +xe_.* | |
| 16 | + | |
| 17 | +# Currently fails and causes coverage loss for other tests | |
| 18 | +# since core_getversion also fails. | |
| 19 | +amdgpu/amd_module_load@reload | |
| 20 | +core_hotunplug.* | |
| 21 | + | |
| 22 | +# GPU reset seen and it hangs the machine | |
| 23 | +amdgpu/amd_deadlock@amdgpu-deadlock-sdma | |
| 24 | +amdgpu/amd_deadlock@amdgpu-gfx-illegal-reg-access | |
| 25 | +amdgpu/amd_dispatch@amdgpu-reset-test-gfx-with-IP-GFX-and-COMPUTE | |
| 26 | + | |
| 27 | +# Hangs the machine and timeout occurs | |
| 28 | +amdgpu/amd_pci_unplug@amdgpu_hotunplug_simple | |
| 29 | +amdgpu/amd_pci_unplug@amdgpu_hotunplug_with_cs | |
| 30 | +amdgpu/amd_pci_unplug@amdgpu_hotunplug_with_exported_bo | |
| 31 | +amdgpu/amd_pci_unplug@amdgpu_hotunplug_with_exported_fence | |
| 32 | +amdgpu/amd_vrr_range@freesync-parsing | |
| 33 | +device_reset.* | |
| @@ -1,3 +1,16 @@ | ||
| 1 | +core_setmaster@master-drop-set-user,Fail | |
| 2 | +core_setmaster_vs_auth,Fail | |
| 3 | +i915_module_load@load,Fail | |
| 4 | +i915_module_load@reload,Fail | |
| 5 | +i915_module_load@reload-no-display,Fail | |
| 6 | +i915_module_load@resize-bar,Fail | |
| 7 | +i915_pm_rpm@gem-execbuf-stress,Timeout | |
| 8 | +i915_pm_rpm@module-reload,Fail | |
| 9 | +kms_async_flips@invalid-async-flip,Timeout | |
| 10 | +kms_atomic_transition@modeset-transition-fencing,Timeout | |
| 11 | +kms_ccs@crc-primary-rotation-180-yf-tiled-ccs,Timeout | |
| 12 | +kms_fb_coherency@memset-crc,Crash | |
| 13 | +kms_flip@flip-vs-dpms-off-vs-modeset,Timeout | |
| 1 | 14 | kms_flip_scaled_crc@flip-32bpp-linear-to-64bpp-linear-downscaling,Fail |
| 2 | 15 | kms_flip_scaled_crc@flip-32bpp-linear-to-64bpp-linear-upscaling,Fail |
| 3 | 16 | kms_flip_scaled_crc@flip-32bpp-xtile-to-64bpp-xtile-downscaling,Fail |
| @@ -20,7 +33,25 @@ kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytile-downscaling,Fail · 16 unmodified lines | ||
| 20 | 33 | kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytile-upscaling,Fail |
| 21 | 34 | kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilegen12rcccs-upscaling,Fail |
| 22 | 35 | kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilercccs-downscaling,Fail |
| 36 | +kms_lease@lease-uevent,Fail | |
| 23 | 37 | kms_plane_alpha_blend@alpha-basic,Fail |
| 24 | 38 | kms_plane_alpha_blend@alpha-opaque-fb,Fail |
| 25 | 39 | kms_plane_alpha_blend@alpha-transparent-fb,Fail |
| 26 | 40 | kms_plane_alpha_blend@constant-alpha-max,Fail |
| 41 | +kms_plane_scaling@plane-scaler-with-clipping-clamping-rotation,Timeout | |
| 42 | +kms_pm_rpm@modeset-lpsp-stress,Timeout | |
| 43 | +kms_pm_rpm@modeset-stress-extra-wait,Timeout | |
| 44 | +kms_pm_rpm@universal-planes,Timeout | |
| 45 | +kms_pm_rpm@universal-planes-dpms,Timeout | |
| 46 | +perf@i915-ref-count,Fail | |
| 47 | +perf_pmu@module-unload,Fail | |
| 48 | +perf_pmu@rc6,Crash | |
| 49 | +sysfs_heartbeat_interval@long,Timeout | |
| 50 | +sysfs_heartbeat_interval@off,Timeout | |
| 51 | +sysfs_preempt_timeout@off,Timeout | |
| 52 | +sysfs_timeslice_duration@off,Timeout | |
| 53 | +xe_module_load@force-load,Fail | |
| 54 | +xe_module_load@load,Fail | |
| 55 | +xe_module_load@many-reload,Fail | |
| 56 | +xe_module_load@reload,Fail | |
| 57 | +xe_module_load@reload-no-display,Fail | |
| @@ -0,0 +1,9 @@ | ||
| 1 | +# Board Name: asus-C433TA-AJ0005-rammus | |
| 2 | +# Bug Report: https://lore.kernel.org/intel-gfx/af4ca4df-a3ef-4943-bdbf-4c3af2c333af@collabora.com/T/#u | |
| 3 | +# IGT Version: 1.28-g0df7b9b97 | |
| 4 | +# Linux Version: 6.9.0-rc7 | |
| 5 | +# Failure Rate: 50 | |
| 6 | +i915_hangman@engine-engine-error | |
| 7 | +i915_hangman@gt-engine-hang | |
| 8 | +kms_async_flips@crc | |
| 9 | +kms_universal_plane@cursor-fb-leak | |
| @@ -1,4 +1,24 @@ | ||
| 1 | 1 | # Suspend to RAM seems to be broken on this machine |
| 2 | 2 | .*suspend.* |
| 3 | 3 | # This is generating kernel oops with divide error |
| 4 | −kms_plane_scaling@invalid-parameters | |
| 4 | +kms_plane_scaling@invalid-parameters | |
| 5 | + | |
| 6 | +# Skip driver specific tests | |
| 7 | +^amdgpu.* | |
| 8 | +msm_.* | |
| 9 | +nouveau_.* | |
| 10 | +panfrost_.* | |
| 11 | +^v3d.* | |
| 12 | +^vc4.* | |
| 13 | +^vmwgfx* | |
| 14 | + | |
| 15 | +# GEM tests takes ~1000 hours, so skip it | |
| 16 | +gem_.* | |
| 17 | + | |
| 18 | +# Hangs the machine and timeout occurs | |
| 19 | +i915_pm_rc6_residency.* | |
| 20 | +i915_suspend.* | |
| 21 | +kms_scaling_modes.* | |
| 22 | + | |
| 23 | +# Kernel panic | |
| 24 | +drm_fdinfo.* | |
| @@ -1,13 +1,7 @@ | ||
| 1 | −kms_3d,Timeout | |
| 2 | −kms_bw@linear-tiling-2-displays-1920x1080p,Fail | |
| 3 | −kms_bw@linear-tiling-2-displays-2560x1440p,Fail | |
| 4 | −kms_bw@linear-tiling-2-displays-3840x2160p,Fail | |
| 5 | −kms_bw@linear-tiling-3-displays-1920x1080p,Fail | |
| 6 | −kms_bw@linear-tiling-3-displays-2560x1440p,Fail | |
| 7 | −kms_bw@linear-tiling-3-displays-3840x2160p,Fail | |
| 8 | −kms_bw@linear-tiling-4-displays-1920x1080p,Fail | |
| 9 | −kms_bw@linear-tiling-4-displays-2560x1440p,Fail | |
| 10 | −kms_bw@linear-tiling-4-displays-3840x2160p,Fail | |
| 1 | +i915_module_load@load,Fail | |
| 2 | +i915_module_load@reload,Fail | |
| 3 | +i915_module_load@reload-no-display,Fail | |
| 4 | +i915_module_load@resize-bar,Fail | |
| 11 | 5 | kms_flip_scaled_crc@flip-32bpp-linear-to-64bpp-linear-downscaling,Fail |
| 12 | 6 | kms_flip_scaled_crc@flip-32bpp-linear-to-64bpp-linear-upscaling,Fail |
| 13 | 7 | kms_flip_scaled_crc@flip-32bpp-xtile-to-64bpp-xtile-downscaling,Fail |
| @@ -30,18 +24,30 @@ kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytile-downscaling,Fail · 16 unmodified lines | ||
| 30 | 24 | kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytile-upscaling,Fail |
| 31 | 25 | kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilegen12rcccs-upscaling,Fail |
| 32 | 26 | kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilercccs-downscaling,Fail |
| 33 | −kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilercccs-upscaling,Fail | |
| 27 | +kms_lease@lease-uevent,Fail | |
| 34 | 28 | kms_plane_alpha_blend@alpha-basic,Fail |
| 35 | 29 | kms_plane_alpha_blend@alpha-opaque-fb,Fail |
| 36 | 30 | kms_plane_alpha_blend@alpha-transparent-fb,Fail |
| 37 | 31 | kms_plane_alpha_blend@constant-alpha-max,Fail |
| 38 | −kms_plane_alpha_blend@pipe-A-alpha-opaque-fb,Fail | |
| 39 | −kms_plane_alpha_blend@pipe-A-alpha-transparent-fb,Fail | |
| 40 | −kms_plane_alpha_blend@pipe-A-constant-alpha-max,Fail | |
| 41 | −kms_plane_alpha_blend@pipe-B-alpha-opaque-fb,Fail | |
| 42 | −kms_plane_alpha_blend@pipe-B-alpha-transparent-fb,Fail | |
| 43 | −kms_plane_alpha_blend@pipe-B-constant-alpha-max,Fail | |
| 44 | −kms_plane_alpha_blend@pipe-C-alpha-opaque-fb,Fail | |
| 45 | −kms_plane_alpha_blend@pipe-C-alpha-transparent-fb,Fail | |
| 46 | −kms_plane_alpha_blend@pipe-C-constant-alpha-max,Fail | |
| 32 | +kms_pm_backlight@basic-brightness,Fail | |
| 33 | +kms_pm_backlight@fade,Fail | |
| 34 | +kms_pm_backlight@fade-with-dpms,Fail | |
| 35 | +kms_pm_rpm@legacy-planes,Timeout | |
| 36 | +kms_pm_rpm@legacy-planes-dpms,Timeout | |
| 37 | +kms_pm_rpm@modeset-stress-extra-wait,Timeout | |
| 38 | +kms_pm_rpm@universal-planes,Timeout | |
| 39 | +kms_pm_rpm@universal-planes-dpms,Timeout | |
| 47 | 40 | kms_sysfs_edid_timing,Fail |
| 41 | +perf@i915-ref-count,Fail | |
| 42 | +perf@non-zero-reason,Timeout | |
| 43 | +perf_pmu@module-unload,Fail | |
| 44 | +perf_pmu@rc6,Crash | |
| 45 | +sysfs_heartbeat_interval@long,Timeout | |
| 46 | +sysfs_heartbeat_interval@off,Timeout | |
| 47 | +sysfs_preempt_timeout@off,Timeout | |
| 48 | +sysfs_timeslice_duration@off,Timeout | |
| 49 | +xe_module_load@force-load,Fail | |
| 50 | +xe_module_load@load,Fail | |
| 51 | +xe_module_load@many-reload,Fail | |
| 52 | +xe_module_load@reload,Fail | |
| 53 | +xe_module_load@reload-no-display,Fail | |
| @@ -0,0 +1,6 @@ | ||
| 1 | +# Board Name: asus-C523NA-A20057-coral | |
| 2 | +# Bug Report: https://lore.kernel.org/intel-gfx/af4ca4df-a3ef-4943-bdbf-4c3af2c333af@collabora.com/T/#u | |
| 3 | +# IGT Version: 1.28-g0df7b9b97 | |
| 4 | +# Linux Version: 6.9.0-rc7 | |
| 5 | +# Failure Rate: 50 | |
| 6 | +kms_fb_coherency@memset-crc | |
| @@ -3,4 +3,28 @@ · 2 unmodified lines | ||
| 3 | 3 | # This is generating kernel oops with divide error |
| 4 | 4 | kms_plane_scaling@invalid-parameters |
| 5 | 5 | # This is cascading issues |
| 6 | −kms_3d | |
| 6 | +kms_3d | |
| 7 | + | |
| 8 | +# Skip driver specific tests | |
| 9 | +^amdgpu.* | |
| 10 | +msm_.* | |
| 11 | +nouveau_.* | |
| 12 | +panfrost_.* | |
| 13 | +^v3d.* | |
| 14 | +^vc4.* | |
| 15 | +^vmwgfx* | |
| 16 | + | |
| 17 | +# GEM tests takes ~1000 hours, so skip it | |
| 18 | +gem_.* | |
| 19 | + | |
| 20 | +# Hangs the machine and timeout occurs | |
| 21 | +i915_pm_rc6_residency.* | |
| 22 | +i915_suspend.* | |
| 23 | +i915_pm_rpm.* | |
| 24 | +device_reset.* | |
| 25 | +api_intel_allocator.* | |
| 26 | +kms_frontbuffer_tracking.* | |
| 27 | +kms_ccs.* | |
| 28 | + | |
| 29 | +# Kernel panic | |
| 30 | +drm_fdinfo.* | |
| @@ -1,3 +1,19 @@ | ||
| 1 | +core_setmaster@master-drop-set-user,Fail | |
| 2 | +core_setmaster_vs_auth,Fail | |
| 3 | +i915_module_load@load,Fail | |
| 4 | +i915_module_load@reload,Fail | |
| 5 | +i915_module_load@reload-no-display,Fail | |
| 6 | +i915_module_load@resize-bar,Fail | |
| 7 | +i915_pipe_stress@stress-xrgb8888-untiled,Fail | |
| 8 | +i915_pipe_stress@stress-xrgb8888-ytiled,Fail | |
| 9 | +i915_pm_rpm@gem-execbuf-stress,Timeout | |
| 10 | +i915_pm_rpm@module-reload,Fail | |
| 11 | +i915_pm_rpm@system-suspend-execbuf,Timeout | |
| 12 | +kms_async_flips@invalid-async-flip,Timeout | |
| 13 | +kms_atomic_transition@modeset-transition-fencing,Timeout | |
| 14 | +kms_ccs@crc-primary-rotation-180-yf-tiled-ccs,Timeout | |
| 15 | +kms_fb_coherency@memset-crc,Crash | |
| 16 | +kms_flip@flip-vs-dpms-off-vs-modeset,Timeout | |
| 1 | 17 | kms_flip_scaled_crc@flip-32bpp-linear-to-64bpp-linear-downscaling,Fail |
| 2 | 18 | kms_flip_scaled_crc@flip-32bpp-linear-to-64bpp-linear-upscaling,Fail |
| 3 | 19 | kms_flip_scaled_crc@flip-32bpp-xtile-to-64bpp-xtile-downscaling,Fail |
| @@ -20,11 +36,33 @@ kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytile-downscaling,Fail · 16 unmodified lines | ||
| 20 | 36 | kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytile-upscaling,Fail |
| 21 | 37 | kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilegen12rcccs-upscaling,Fail |
| 22 | 38 | kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilercccs-downscaling,Fail |
| 39 | +kms_lease@lease-uevent,Fail | |
| 23 | 40 | kms_plane_alpha_blend@alpha-basic,Fail |
| 24 | 41 | kms_plane_alpha_blend@alpha-opaque-fb,Fail |
| 25 | 42 | kms_plane_alpha_blend@alpha-transparent-fb,Fail |
| 26 | 43 | kms_plane_alpha_blend@constant-alpha-max,Fail |
| 27 | 44 | kms_plane_alpha_blend@constant-alpha-min,Fail |
| 45 | +kms_plane_scaling@plane-scaler-with-clipping-clamping-rotation,Timeout | |
| 46 | +kms_pm_rpm@modeset-stress-extra-wait,Timeout | |
| 47 | +kms_pm_rpm@universal-planes,Timeout | |
| 48 | +kms_pm_rpm@universal-planes-dpms,Timeout | |
| 49 | +kms_psr2_sf@fbc-plane-move-sf-dmg-area,Timeout | |
| 50 | +kms_psr2_sf@overlay-plane-update-continuous-sf,Fail | |
| 51 | +kms_psr2_sf@overlay-plane-update-sf-dmg-area,Fail | |
| 52 | +kms_psr2_sf@primary-plane-update-sf-dmg-area,Fail | |
| 53 | +kms_psr2_sf@primary-plane-update-sf-dmg-area-big-fb,Fail | |
| 28 | 54 | kms_psr2_su@page_flip-NV12,Fail |
| 29 | 55 | kms_psr2_su@page_flip-P010,Fail |
| 56 | +kms_psr@psr-sprite-render,Timeout | |
| 30 | 57 | kms_setmode@basic,Fail |
| 58 | +perf@i915-ref-count,Fail | |
| 59 | +perf_pmu@module-unload,Fail | |
| 60 | +perf_pmu@rc6,Crash | |
| 61 | +perf_pmu@rc6-suspend,Crash | |
| 62 | +sysfs_heartbeat_interval@long,Timeout | |
| 63 | +sysfs_heartbeat_interval@off,Timeout | |
| 64 | +sysfs_preempt_timeout@off,Timeout | |
| 65 | +sysfs_timeslice_duration@off,Timeout | |
| 66 | +xe_module_load@force-load,Fail | |
| 67 | +xe_module_load@load,Fail | |
| 68 | +xe_module_load@many-reload,Fail | |
| @@ -0,0 +1,6 @@ | ||
| 1 | +# Board Name: asus-C436FA-Flip-hatch | |
| 2 | +# Bug Report: https://lore.kernel.org/intel-gfx/af4ca4df-a3ef-4943-bdbf-4c3af2c333af@collabora.com/T/#u | |
| 3 | +# IGT Version: 1.28-g0df7b9b97 | |
| 4 | +# Linux Version: 6.9.0-rc7 | |
| 5 | +# Failure Rate: 50 | |
| 6 | +kms_plane_alpha_blend@constant-alpha-min | |
| @@ -1,2 +1,25 @@ | ||
| 1 | 1 | # This is generating kernel oops with divide error |
| 2 | 2 | kms_plane_scaling@invalid-parameters |
| 3 | + | |
| 4 | +# Skip driver specific tests | |
| 5 | +^amdgpu.* | |
| 6 | +msm_.* | |
| 7 | +nouveau_.* | |
| 8 | +panfrost_.* | |
| 9 | +^v3d.* | |
| 10 | +^vc4.* | |
| 11 | +^vmwgfx* | |
| 12 | + | |
| 13 | +# GEM tests takes ~1000 hours, so skip it | |
| 14 | +gem_.* | |
| 15 | + | |
| 16 | +# Hangs the machine and timeout occurs | |
| 17 | +i915_pm_rc6_residency.* | |
| 18 | +i915_suspend.* | |
| 19 | +xe_module_load.* | |
| 20 | +api_intel_allocator.* | |
| 21 | +kms_cursor_legacy.* | |
| 22 | + | |
| 23 | +# Kernel panic | |
| 24 | +drm_fdinfo.* | |
| 25 | +kms_frontbuffer_tracking.* | |
| @@ -1,5 +1,20 @@ | ||
| 1 | −kms_fbcon_fbt@fbc,Fail | |
| 2 | −kms_flip@blocking-wf_vblank,Fail | |
| 1 | +core_setmaster@master-drop-set-user,Fail | |
| 2 | +i915_module_load@load,Fail | |
| 3 | +i915_module_load@reload,Fail | |
| 4 | +i915_module_load@reload-no-display,Fail | |
| 5 | +i915_module_load@resize-bar,Fail | |
| 6 | +kms_async_flips@invalid-async-flip,Timeout | |
| 7 | +kms_atomic_transition@modeset-transition-fencing,Timeout | |
| 8 | +kms_big_fb@linear-16bpp-rotate-0,Fail | |
| 9 | +kms_big_fb@linear-16bpp-rotate-180,Fail | |
| 10 | +kms_big_fb@linear-32bpp-rotate-0,Fail | |
| 11 | +kms_big_fb@linear-32bpp-rotate-180,Fail | |
| 12 | +kms_big_fb@linear-8bpp-rotate-0,Fail | |
| 13 | +kms_big_fb@linear-8bpp-rotate-180,Fail | |
| 14 | +kms_big_fb@linear-max-hw-stride-32bpp-rotate-0,Fail | |
| 15 | +kms_dirtyfb@default-dirtyfb-ioctl,Fail | |
| 16 | +kms_draw_crc@draw-method-render,Fail | |
| 17 | +kms_flip@flip-vs-dpms-off-vs-modeset,Timeout | |
| 3 | 18 | kms_flip@wf_vblank-ts-check,Fail |
| 4 | 19 | kms_flip@wf_vblank-ts-check-interruptible,Fail |
| 5 | 20 | kms_flip_scaled_crc@flip-32bpp-linear-to-64bpp-linear-downscaling,Fail |
| @@ -11,7 +26,6 @@ kms_flip_scaled_crc@flip-32bpp-ytile-to-64bpp-ytile-upscaling,Fail · 5 unmodified lines | ||
| 11 | 26 | kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile-downscaling,Fail |
| 12 | 27 | kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile-upscaling,Fail |
| 13 | 28 | kms_flip_scaled_crc@flip-64bpp-linear-to-16bpp-linear-downscaling,Fail |
| 14 | −kms_flip_scaled_crc@flip-64bpp-linear-to-16bpp-linear-upscaling,Fail | |
| 15 | 29 | kms_flip_scaled_crc@flip-64bpp-linear-to-32bpp-linear-downscaling,Fail |
| 16 | 30 | kms_flip_scaled_crc@flip-64bpp-linear-to-32bpp-linear-upscaling,Fail |
| 17 | 31 | kms_flip_scaled_crc@flip-64bpp-xtile-to-16bpp-xtile-downscaling,Fail |
| @@ -26,11 +40,24 @@ kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilegen12rcccs-upscaling,Fail · 8 unmodified lines | ||
| 26 | 40 | kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilercccs-downscaling,Fail |
| 27 | 41 | kms_frontbuffer_tracking@fbc-tiling-linear,Fail |
| 28 | 42 | kms_frontbuffer_tracking@fbcdrrs-tiling-linear,Fail |
| 29 | −kms_plane_alpha_blend@alpha-basic,Fail | |
| 43 | +kms_lease@lease-uevent,Fail | |
| 30 | 44 | kms_plane_alpha_blend@alpha-opaque-fb,Fail |
| 31 | −kms_plane_alpha_blend@alpha-transparent-fb,Fail | |
| 32 | −kms_plane_alpha_blend@constant-alpha-max,Fail | |
| 45 | +kms_plane_scaling@plane-scaler-with-clipping-clamping-rotation,Timeout | |
| 46 | +kms_pm_rpm@legacy-planes,Timeout | |
| 47 | +kms_pm_rpm@legacy-planes-dpms,Timeout | |
| 48 | +kms_pm_rpm@modeset-stress-extra-wait,Timeout | |
| 49 | +kms_pm_rpm@universal-planes,Timeout | |
| 50 | +kms_pm_rpm@universal-planes-dpms,Timeout | |
| 33 | 51 | kms_rotation_crc@multiplane-rotation,Fail |
| 34 | 52 | kms_rotation_crc@multiplane-rotation-cropping-bottom,Fail |
| 35 | 53 | kms_rotation_crc@multiplane-rotation-cropping-top,Fail |
| 36 | −kms_setmode@basic,Fail | |
| 54 | +perf@non-zero-reason,Timeout | |
| 55 | +sysfs_heartbeat_interval@long,Timeout | |
| 56 | +sysfs_heartbeat_interval@off,Timeout | |
| 57 | +sysfs_preempt_timeout@off,Timeout | |
| 58 | +sysfs_timeslice_duration@off,Timeout | |
| 59 | +xe_module_load@force-load,Fail | |
| 60 | +xe_module_load@load,Fail | |
| 61 | +xe_module_load@many-reload,Fail | |
| 62 | +xe_module_load@reload,Fail | |
| 63 | +xe_module_load@reload-no-display,Fail | |
| @@ -0,0 +1,7 @@ | ||
| 1 | +# Board Name: hp-x360-12b-ca0010nr-n4020-octopus | |
| 2 | +# Bug Report: https://lore.kernel.org/intel-gfx/af4ca4df-a3ef-4943-bdbf-4c3af2c333af@collabora.com/T/#u | |
| 3 | +# IGT Version: 1.28-g0df7b9b97 | |
| 4 | +# Linux Version: 6.9.0-rc7 | |
| 5 | +# Failure Rate: 50 | |
| 6 | +core_hotunplug@unplug-rescan | |
| 7 | +kms_fb_coherency@memset-crc | |
| @@ -2,4 +2,28 @@ · 1 unmodified line | ||
| 2 | 2 | .*suspend.* |
| 3 | 3 | |
| 4 | 4 | # This is generating kernel oops with divide error |
| 5 | −kms_plane_scaling@invalid-parameters | |
| 5 | +kms_plane_scaling@invalid-parameters | |
| 6 | + | |
| 7 | +# Skip driver specific tests | |
| 8 | +^amdgpu.* | |
| 9 | +msm_.* | |
| 10 | +nouveau_.* | |
| 11 | +panfrost_.* | |
| 12 | +^v3d.* | |
| 13 | +^vc4.* | |
| 14 | +^vmwgfx* | |
| 15 | + | |
| 16 | +# GEM tests takes ~1000 hours, so skip it | |
| 17 | +gem_.* | |
| 18 | + | |
| 19 | +# Hangs the machine and timeout occurs | |
| 20 | +i915_pm_rc6_residency.* | |
| 21 | +i915_suspend.* | |
| 22 | +i915_pm_rpm.* | |
| 23 | +kms_ccs.* | |
| 24 | +kms_plane_multiple.* | |
| 25 | +perf.* | |
| 26 | + | |
| 27 | +# Kernel panic | |
| 28 | +drm_fdinfo.* | |
| 29 | +kms_plane_alpha_blend.* | |
| @@ -1,32 +1,28 @@ | ||
| 1 | −kms_bw@linear-tiling-2-displays-2560x1440p,Fail | |
| 2 | −kms_bw@linear-tiling-4-displays-2560x1440p,Fail | |
| 3 | −kms_flip_scaled_crc@flip-32bpp-linear-to-64bpp-linear-downscaling,Fail | |
| 4 | −kms_flip_scaled_crc@flip-32bpp-linear-to-64bpp-linear-upscaling,Fail | |
| 1 | +i915_module_load@load,Fail | |
| 2 | +i915_module_load@reload,Fail | |
| 3 | +i915_module_load@reload-no-display,Fail | |
| 4 | +i915_module_load@resize-bar,Fail | |
| 5 | +i915_pm_rpm@gem-execbuf-stress,Timeout | |
| 5 | 6 | kms_flip_scaled_crc@flip-32bpp-xtile-to-64bpp-xtile-downscaling,Fail |
| 6 | −kms_flip_scaled_crc@flip-32bpp-xtile-to-64bpp-xtile-upscaling,Fail | |
| 7 | −kms_flip_scaled_crc@flip-32bpp-ytile-to-64bpp-ytile-downscaling,Fail | |
| 8 | 7 | kms_flip_scaled_crc@flip-32bpp-ytile-to-64bpp-ytile-upscaling,Fail |
| 9 | −kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile-downscaling,Fail | |
| 10 | 8 | kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile-upscaling,Fail |
| 11 | 9 | kms_flip_scaled_crc@flip-64bpp-linear-to-16bpp-linear-downscaling,Fail |
| 12 | −kms_flip_scaled_crc@flip-64bpp-linear-to-16bpp-linear-upscaling,Fail | |
| 13 | −kms_flip_scaled_crc@flip-64bpp-linear-to-32bpp-linear-downscaling,Fail | |
| 14 | 10 | kms_flip_scaled_crc@flip-64bpp-linear-to-32bpp-linear-upscaling,Fail |
| 15 | −kms_flip_scaled_crc@flip-64bpp-xtile-to-16bpp-xtile-downscaling,Fail | |
| 16 | 11 | kms_flip_scaled_crc@flip-64bpp-xtile-to-16bpp-xtile-upscaling,Fail |
| 17 | −kms_flip_scaled_crc@flip-64bpp-xtile-to-32bpp-xtile-downscaling,Fail | |
| 18 | −kms_flip_scaled_crc@flip-64bpp-xtile-to-32bpp-xtile-upscaling,Fail | |
| 19 | −kms_flip_scaled_crc@flip-64bpp-ytile-to-16bpp-ytile-downscaling,Fail | |
| 20 | −kms_flip_scaled_crc@flip-64bpp-ytile-to-16bpp-ytile-upscaling,Fail | |
| 21 | 12 | kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytile-downscaling,Fail |
| 22 | −kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytile-upscaling,Fail | |
| 23 | 13 | kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilegen12rcccs-upscaling,Fail |
| 24 | −kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilercccs-downscaling,Fail | |
| 25 | −kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilercccs-upscaling,Fail | |
| 26 | −kms_plane_alpha_blend@alpha-basic,Fail | |
| 27 | −kms_plane_alpha_blend@alpha-opaque-fb,Fail | |
| 14 | +kms_lease@lease-uevent,Fail | |
| 28 | 15 | kms_plane_alpha_blend@alpha-transparent-fb,Fail |
| 29 | −kms_plane_alpha_blend@constant-alpha-max,Fail | |
| 30 | −kms_plane_alpha_blend@pipe-A-constant-alpha-max,Fail | |
| 31 | −kms_plane_alpha_blend@pipe-B-alpha-opaque-fb,Fail | |
| 32 | −kms_plane_alpha_blend@pipe-C-constant-alpha-max,Fail | |
| 16 | +perf@i915-ref-count,Fail | |
| 17 | +perf_pmu@busy-accuracy-50,Fail | |
| 18 | +perf_pmu@module-unload,Fail | |
| 19 | +perf_pmu@rc6,Crash | |
| 20 | +sysfs_heartbeat_interval@long,Timeout | |
| 21 | +sysfs_heartbeat_interval@off,Timeout | |
| 22 | +sysfs_preempt_timeout@off,Timeout | |
| 23 | +sysfs_timeslice_duration@off,Timeout | |
| 24 | +xe_module_load@force-load,Fail | |
| 25 | +xe_module_load@load,Fail | |
| 26 | +xe_module_load@many-reload,Fail | |
| 27 | +xe_module_load@reload,Fail | |
| 28 | +xe_module_load@reload-no-display,Fail | |
| @@ -1 +1,6 @@ | ||
| 1 | −kms_async_flips@crc | |
| 1 | +# Board Name: hp-x360-14-G1-sona | |
| 2 | +# Bug Report: https://lore.kernel.org/intel-gfx/af4ca4df-a3ef-4943-bdbf-4c3af2c333af@collabora.com/T/#u | |
| 3 | +# IGT Version: 1.28-g0df7b9b97 | |
| 4 | +# Linux Version: 6.9.0-rc7 | |
| 5 | +# Failure Rate: 50 | |
| 6 | +prime_busy@hang | |
| @@ -2,4 +2,38 @@ · 1 unmodified line | ||
| 2 | 2 | .*suspend.* |
| 3 | 3 | |
| 4 | 4 | # This is generating kernel oops with divide error |
| 5 | −kms_plane_scaling@invalid-parameters | |
| 5 | +kms_plane_scaling@invalid-parameters | |
| 6 | + | |
| 7 | +# Skip driver specific tests | |
| 8 | +^amdgpu.* | |
| 9 | +msm_.* | |
| 10 | +nouveau_.* | |
| 11 | +panfrost_.* | |
| 12 | +^v3d.* | |
| 13 | +^vc4.* | |
| 14 | +^vmwgfx* | |
| 15 | + | |
| 16 | +# GEM tests takes ~1000 hours, so skip it | |
| 17 | +gem_.* | |
| 18 | + | |
| 19 | +# Hangs the machine and timeout occurs | |
| 20 | +i915_.* | |
| 21 | +api_intel_bb.* | |
| 22 | + | |
| 23 | +# Kernel panic | |
| 24 | +drm_fdinfo.* | |
| 25 | +kms_.* | |
| 26 | +prime_mmap_coherency.* | |
| 27 | +perf.* | |
| 28 | +drm_read.* | |
| 29 | +api_intel_allocator.* | |
| 30 | +sysfs_preempt_timeout.* | |
| 31 | +dumb_buffer.* | |
| 32 | +gen9_exec_parse.* | |
| 33 | +debugfs_test.* | |
| 34 | +core_hotunplug.* | |
| 35 | +tools_test.* | |
| 36 | + | |
| 37 | +# GPU hang | |
| 38 | +sysfs_timeslice_.* | |
| 39 | +sysfs_heartbeat_.* | |
| @@ -1,36 +1,43 @@ | ||
| 1 | −kms_bw@linear-tiling-2-displays-3840x2160p,Fail | |
| 2 | −kms_bw@linear-tiling-3-displays-1920x1080p,Fail | |
| 3 | −kms_bw@linear-tiling-3-displays-2560x1440p,Fail | |
| 4 | −kms_bw@linear-tiling-3-displays-3840x2160p,Fail | |
| 5 | −kms_bw@linear-tiling-4-displays-1920x1080p,Fail | |
| 6 | −kms_bw@linear-tiling-4-displays-2560x1440p,Fail | |
| 7 | −kms_bw@linear-tiling-4-displays-3840x2160p,Fail | |
| 8 | −kms_bw@linear-tiling-5-displays-1920x1080p,Fail | |
| 9 | −kms_bw@linear-tiling-5-displays-2560x1440p,Fail | |
| 10 | −kms_bw@linear-tiling-5-displays-3840x2160p,Fail | |
| 11 | −kms_flip@flip-vs-panning-vs-hang,Timeout | |
| 12 | −kms_flip_scaled_crc@flip-32bpp-linear-to-64bpp-linear-downscaling,Fail | |
| 13 | −kms_flip_scaled_crc@flip-32bpp-linear-to-64bpp-linear-upscaling,Fail | |
| 14 | −kms_flip_scaled_crc@flip-32bpp-xtile-to-64bpp-xtile-downscaling,Fail | |
| 15 | −kms_flip_scaled_crc@flip-32bpp-xtile-to-64bpp-xtile-upscaling,Fail | |
| 16 | −kms_flip_scaled_crc@flip-32bpp-ytile-to-64bpp-ytile-downscaling,Fail | |
| 17 | −kms_flip_scaled_crc@flip-32bpp-ytile-to-64bpp-ytile-upscaling,Fail | |
| 18 | −kms_flip_scaled_crc@flip-64bpp-linear-to-16bpp-linear-downscaling,Fail | |
| 19 | −kms_flip_scaled_crc@flip-64bpp-linear-to-16bpp-linear-upscaling,Fail | |
| 20 | −kms_flip_scaled_crc@flip-64bpp-linear-to-32bpp-linear-downscaling,Fail | |
| 21 | −kms_flip_scaled_crc@flip-64bpp-linear-to-32bpp-linear-upscaling,Fail | |
| 22 | −kms_flip_scaled_crc@flip-64bpp-xtile-to-16bpp-xtile-downscaling,Fail | |
| 23 | −kms_flip_scaled_crc@flip-64bpp-xtile-to-16bpp-xtile-upscaling,Fail | |
| 24 | −kms_flip_scaled_crc@flip-64bpp-xtile-to-32bpp-xtile-downscaling,Fail | |
| 25 | −kms_flip_scaled_crc@flip-64bpp-xtile-to-32bpp-xtile-upscaling,Fail | |
| 26 | −kms_flip_scaled_crc@flip-64bpp-ytile-to-16bpp-ytile-downscaling,Fail | |
| 27 | −kms_flip_scaled_crc@flip-64bpp-ytile-to-16bpp-ytile-upscaling,Fail | |
| 28 | −kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytile-downscaling,Fail | |
| 29 | −kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytile-upscaling,Fail | |
| 30 | −kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilegen12rcccs-upscaling,Fail | |
| 31 | −kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilercccs-downscaling,Fail | |
| 32 | −kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilercccs-upscaling,Fail | |
| 33 | −kms_rotation_crc@bad-pixel-format,Fail | |
| 1 | +api_intel_bb@blit-noreloc-keep-cache,Timeout | |
| 2 | +api_intel_bb@offset-control,Timeout | |
| 3 | +api_intel_bb@render-ccs,Timeout | |
| 4 | +core_getclient,Timeout | |
| 5 | +core_hotunplug@hotreplug-lateclose,Timeout | |
| 6 | +drm_read@short-buffer-block,Timeout | |
| 7 | +drm_read@short-buffer-nonblock,Timeout | |
| 8 | +dumb_buffer@map-uaf,Timeout | |
| 9 | +gen3_render_tiledx_blits,Timeout | |
| 10 | +gen7_exec_parse@basic-allocation,Timeout | |
| 11 | +gen7_exec_parse@batch-without-end,Timeout | |
| 12 | +gen9_exec_parse@batch-invalid-length,Timeout | |
| 13 | +gen9_exec_parse@bb-secure,Timeout | |
| 14 | +i915_module_load@load,Fail | |
| 15 | +i915_module_load@reload,Fail | |
| 16 | +i915_module_load@reload-no-display,Fail | |
| 17 | +i915_module_load@resize-bar,Fail | |
| 18 | +i915_pciid,Timeout | |
| 19 | +i915_query@engine-info,Timeout | |
| 20 | +kms_lease@lease-uevent,Fail | |
| 34 | 21 | kms_rotation_crc@multiplane-rotation,Fail |
| 35 | −kms_rotation_crc@multiplane-rotation-cropping-bottom,Fail | |
| 36 | −kms_rotation_crc@multiplane-rotation-cropping-top,Fail | |
| 22 | +perf@i915-ref-count,Fail | |
| 23 | +perf_pmu@busy,Timeout | |
| 24 | +perf_pmu@enable-race,Timeout | |
| 25 | +perf_pmu@event-wait,Timeout | |
| 26 | +perf_pmu@gt-awake,Timeout | |
| 27 | +perf_pmu@module-unload,Fail | |
| 28 | +perf_pmu@rc6,Crash | |
| 29 | +prime_mmap@test_map_unmap,Timeout | |
| 30 | +prime_self_import@basic-with_one_bo,Timeout | |
| 31 | +syncobj_basic@bad-destroy,Timeout | |
| 32 | +syncobj_eventfd@invalid-bad-pad,Timeout | |
| 33 | +syncobj_wait@invalid-multi-wait-unsubmitted-signaled,Timeout | |
| 34 | +syncobj_wait@invalid-signal-illegal-handle,Timeout | |
| 35 | +syncobj_wait@invalid-single-wait-all-unsubmitted,Timeout | |
| 36 | +syncobj_wait@multi-wait-all-submitted,Timeout | |
| 37 | +syncobj_wait@multi-wait-for-submit-submitted-signaled,Timeout | |
| 38 | +syncobj_wait@wait-any-complex,Timeout | |
| 39 | +syncobj_wait@wait-delayed-signal,Timeout | |
| 40 | +xe_module_load@force-load,Fail | |
| 41 | +xe_module_load@load,Fail | |
| 42 | +xe_module_load@reload,Fail | |
| 43 | +xe_module_load@reload-no-display,Fail | |
| @@ -8,4 +8,30 @@ gem_eio.* · 7 unmodified lines | ||
| 8 | 8 | kms_flip@absolute-wf_vblank@a-edp1 |
| 9 | 9 | |
| 10 | 10 | # This is generating kernel oops with divide error |
| 11 | −kms_plane_scaling@invalid-parameters | |
| 11 | +kms_plane_scaling@invalid-parameters | |
| 12 | + | |
| 13 | +# Skip driver specific tests | |
| 14 | +^amdgpu.* | |
| 15 | +msm_.* | |
| 16 | +nouveau_.* | |
| 17 | +panfrost_.* | |
| 18 | +^v3d.* | |
| 19 | +^vc4.* | |
| 20 | +^vmwgfx* | |
| 21 | + | |
| 22 | +# GEM tests takes ~1000 hours, so skip it | |
| 23 | +gem_.* | |
| 24 | + | |
| 25 | +# Kernel panic | |
| 26 | +drm_fdinfo.* | |
| 27 | + | |
| 28 | +# Hangs the machine and timeout occurs | |
| 29 | +i915_pm_rc6_residency.* | |
| 30 | +i915_suspend.* | |
| 31 | +sysfs_heartbeat_interval.* | |
| 32 | +syncobj_timeline.* | |
| 33 | +sysfs_timeslice_duration.* | |
| 34 | +syncobj_wait.* | |
| 35 | + | |
| 36 | +# Kernel panic and test hangs with multiple kms tests | |
| 37 | +kms_.* | |
| @@ -1,14 +1,25 @@ | ||
| 1 | −kms_bw@linear-tiling-2-displays-1920x1080p,Fail | |
| 2 | −kms_bw@linear-tiling-2-displays-2560x1440p,Fail | |
| 3 | −kms_bw@linear-tiling-2-displays-3840x2160p,Fail | |
| 4 | −kms_bw@linear-tiling-3-displays-1920x1080p,Fail | |
| 5 | −kms_bw@linear-tiling-3-displays-2560x1440p,Fail | |
| 6 | −kms_bw@linear-tiling-3-displays-3840x2160p,Fail | |
| 7 | −kms_bw@linear-tiling-4-displays-1920x1080p,Fail | |
| 8 | −kms_bw@linear-tiling-4-displays-2560x1440p,Fail | |
| 9 | −kms_bw@linear-tiling-4-displays-3840x2160p,Fail | |
| 10 | −kms_fbcon_fbt@fbc,Fail | |
| 11 | −kms_fbcon_fbt@fbc-suspend,Fail | |
| 1 | +core_setmaster@master-drop-set-user,Fail | |
| 2 | +core_setmaster_vs_auth,Fail | |
| 3 | +i915_module_load@load,Fail | |
| 4 | +i915_module_load@reload,Fail | |
| 5 | +i915_module_load@reload-no-display,Fail | |
| 6 | +i915_module_load@resize-bar,Fail | |
| 7 | +i915_pm_rpm@gem-execbuf-stress,Timeout | |
| 8 | +i915_pm_rpm@module-reload,Fail | |
| 9 | +i915_pm_rpm@system-suspend-execbuf,Timeout | |
| 10 | +kms_async_flips@invalid-async-flip,Timeout | |
| 11 | +kms_atomic_transition@modeset-transition-fencing,Timeout | |
| 12 | +kms_big_fb@linear-16bpp-rotate-0,Fail | |
| 13 | +kms_big_fb@linear-16bpp-rotate-180,Fail | |
| 14 | +kms_big_fb@linear-32bpp-rotate-0,Fail | |
| 15 | +kms_big_fb@linear-32bpp-rotate-180,Fail | |
| 16 | +kms_big_fb@linear-8bpp-rotate-0,Fail | |
| 17 | +kms_big_fb@linear-8bpp-rotate-180,Fail | |
| 18 | +kms_big_fb@linear-max-hw-stride-32bpp-rotate-0,Fail | |
| 19 | +kms_ccs@crc-primary-rotation-180-yf-tiled-ccs,Timeout | |
| 20 | +kms_dirtyfb@default-dirtyfb-ioctl,Fail | |
| 21 | +kms_draw_crc@draw-method-render,Fail | |
| 22 | +kms_fb_coherency@memset-crc,Crash | |
| 12 | 23 | kms_flip_scaled_crc@flip-32bpp-linear-to-64bpp-linear-downscaling,Fail |
| 13 | 24 | kms_flip_scaled_crc@flip-32bpp-linear-to-64bpp-linear-upscaling,Fail |
| 14 | 25 | kms_flip_scaled_crc@flip-32bpp-xtile-to-64bpp-xtile-downscaling,Fail |
| @@ -18,8 +29,6 @@ kms_flip_scaled_crc@flip-32bpp-ytile-to-64bpp-ytile-upscaling,Fail · 3 unmodified lines | ||
| 18 | 29 | kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile-downscaling,Fail |
| 19 | 30 | kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile-upscaling,Fail |
| 20 | 31 | kms_flip_scaled_crc@flip-64bpp-linear-to-16bpp-linear-downscaling,Fail |
| 21 | −kms_flip_scaled_crc@flip-64bpp-linear-to-16bpp-linear-upscaling,Fail | |
| 22 | −kms_flip_scaled_crc@flip-64bpp-linear-to-32bpp-linear-downscaling,Fail | |
| 23 | 32 | kms_flip_scaled_crc@flip-64bpp-linear-to-32bpp-linear-upscaling,Fail |
| 24 | 33 | kms_flip_scaled_crc@flip-64bpp-xtile-to-16bpp-xtile-downscaling,Fail |
| 25 | 34 | kms_flip_scaled_crc@flip-64bpp-xtile-to-16bpp-xtile-upscaling,Fail |
| @@ -31,18 +40,26 @@ kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytile-downscaling,Fail · 5 unmodified lines | ||
| 31 | 40 | kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytile-upscaling,Fail |
| 32 | 41 | kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilegen12rcccs-upscaling,Fail |
| 33 | 42 | kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilercccs-downscaling,Fail |
| 34 | −kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilercccs-upscaling,Fail | |
| 35 | 43 | kms_frontbuffer_tracking@fbc-tiling-linear,Fail |
| 44 | +kms_lease@lease-uevent,Fail | |
| 36 | 45 | kms_plane_alpha_blend@alpha-basic,Fail |
| 37 | 46 | kms_plane_alpha_blend@alpha-opaque-fb,Fail |
| 38 | 47 | kms_plane_alpha_blend@alpha-transparent-fb,Fail |
| 39 | 48 | kms_plane_alpha_blend@constant-alpha-max,Fail |
| 40 | −kms_plane_alpha_blend@pipe-A-alpha-opaque-fb,Fail | |
| 41 | −kms_plane_alpha_blend@pipe-A-alpha-transparent-fb,Fail | |
| 42 | −kms_plane_alpha_blend@pipe-A-constant-alpha-max,Fail | |
| 43 | −kms_plane_alpha_blend@pipe-B-alpha-opaque-fb,Fail | |
| 44 | −kms_plane_alpha_blend@pipe-B-alpha-transparent-fb,Fail | |
| 45 | −kms_plane_alpha_blend@pipe-B-constant-alpha-max,Fail | |
| 46 | −kms_plane_alpha_blend@pipe-C-alpha-opaque-fb,Fail | |
| 47 | −kms_plane_alpha_blend@pipe-C-alpha-transparent-fb,Fail | |
| 48 | −kms_plane_alpha_blend@pipe-C-constant-alpha-max,Fail | |
| 49 | +kms_plane_scaling@plane-scaler-with-clipping-clamping-rotation,Timeout | |
| 50 | +kms_pm_rpm@modeset-stress-extra-wait,Timeout | |
| 51 | +kms_pm_rpm@universal-planes,Timeout | |
| 52 | +kms_pm_rpm@universal-planes-dpms,Timeout | |
| 53 | +perf@i915-ref-count,Fail | |
| 54 | +perf_pmu@module-unload,Fail | |
| 55 | +perf_pmu@rc6,Crash | |
| 56 | +perf_pmu@rc6-suspend,Crash | |
| 57 | +sysfs_heartbeat_interval@long,Timeout | |
| 58 | +sysfs_heartbeat_interval@off,Timeout | |
| 59 | +sysfs_preempt_timeout@off,Timeout | |
| 60 | +sysfs_timeslice_duration@off,Timeout | |
| 61 | +xe_module_load@force-load,Fail | |
| 62 | +xe_module_load@load,Fail | |
| 63 | +xe_module_load@many-reload,Fail | |
| 64 | +xe_module_load@reload,Fail | |
| 65 | +xe_module_load@reload-no-display,Fail | |
| @@ -0,0 +1,6 @@ | ||
| 1 | +# Board Name: dell-latitude-5400-8665U-sarien | |
| 2 | +# Bug Report: https://lore.kernel.org/intel-gfx/af4ca4df-a3ef-4943-bdbf-4c3af2c333af@collabora.com/T/#u | |
| 3 | +# IGT Version: 1.28-g0df7b9b97 | |
| 4 | +# Linux Version: 6.9.0-rc7 | |
| 5 | +# Failure Rate: 50 | |
| 6 | +kms_pm_rpm@modeset-lpsp-stress | |
| @@ -1,2 +1,22 @@ | ||
| 1 | 1 | # This is generating kernel oops with divide error |
| 2 | −kms_plane_scaling@invalid-parameters | |
| 2 | +kms_plane_scaling@invalid-parameters | |
| 3 | + | |
| 4 | +# Skip driver specific tests | |
| 5 | +^amdgpu.* | |
| 6 | +msm_.* | |
| 7 | +nouveau_.* | |
| 8 | +panfrost_.* | |
| 9 | +^v3d.* | |
| 10 | +^vc4.* | |
| 11 | +^vmwgfx* | |
| 12 | + | |
| 13 | +# GEM tests takes ~1000 hours, so skip it | |
| 14 | +gem_.* | |
| 15 | + | |
| 16 | +# Hangs the machine and timeout occurs | |
| 17 | +i915_pm_rc6_residency.* | |
| 18 | +i915_suspend.* | |
| 19 | +kms_flip.* | |
| 20 | + | |
| 21 | +# Kernel panic | |
| 22 | +drm_fdinfo.* | |
| @@ -1,36 +1,30 @@ | ||
| 1 | +device_reset@cold-reset-bound,Fail | |
| 2 | +device_reset@reset-bound,Fail | |
| 3 | +device_reset@unbind-cold-reset-rebind,Fail | |
| 4 | +device_reset@unbind-reset-rebind,Fail | |
| 5 | +dumb_buffer@invalid-bpp,Fail | |
| 6 | +fbdev@eof,Fail | |
| 7 | +fbdev@read,Fail | |
| 8 | +fbdev@unaligned-write,Fail | |
| 1 | 9 | kms_3d,Fail |
| 2 | 10 | kms_bw@linear-tiling-1-displays-1920x1080p,Fail |
| 11 | +kms_bw@linear-tiling-1-displays-2160x1440p,Fail | |
| 3 | 12 | kms_bw@linear-tiling-1-displays-2560x1440p,Fail |
| 4 | 13 | kms_bw@linear-tiling-1-displays-3840x2160p,Fail |
| 5 | 14 | kms_bw@linear-tiling-2-displays-1920x1080p,Fail |
| 15 | +kms_bw@linear-tiling-2-displays-2160x1440p,Fail | |
| 6 | 16 | kms_bw@linear-tiling-2-displays-2560x1440p,Fail |
| 7 | 17 | kms_bw@linear-tiling-2-displays-3840x2160p,Fail |
| 8 | −kms_bw@linear-tiling-3-displays-1920x1080p,Fail | |
| 9 | −kms_bw@linear-tiling-3-displays-2560x1440p,Fail | |
| 10 | −kms_bw@linear-tiling-3-displays-3840x2160p,Fail | |
| 11 | 18 | kms_color@invalid-gamma-lut-sizes,Fail |
| 12 | −kms_color@pipe-A-invalid-gamma-lut-sizes,Fail | |
| 13 | −kms_color@pipe-B-invalid-gamma-lut-sizes,Fail | |
| 14 | 19 | kms_cursor_legacy@cursor-vs-flip-atomic,Fail |
| 15 | 20 | kms_cursor_legacy@cursor-vs-flip-legacy,Fail |
| 16 | 21 | kms_flip@flip-vs-modeset-vs-hang,Fail |
| 17 | 22 | kms_flip@flip-vs-panning-vs-hang,Fail |
| 18 | 23 | kms_flip@flip-vs-suspend,Fail |
| 19 | 24 | kms_flip@flip-vs-suspend-interruptible,Fail |
| 20 | −kms_force_connector_basic@force-edid,Fail | |
| 21 | −kms_force_connector_basic@force-load-detect,Fail | |
| 22 | −kms_force_connector_basic@prune-stale-modes,Fail | |
| 23 | −kms_hdmi_inject@inject-4k,Fail | |
| 24 | −kms_plane_scaling@planes-upscale-20x20,Fail | |
| 25 | −kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-25,Fail | |
| 26 | −kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-5,Fail | |
| 27 | −kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-75,Fail | |
| 28 | −kms_plane_scaling@upscale-with-modifier-20x20,Fail | |
| 29 | −kms_plane_scaling@upscale-with-pixel-format-20x20,Fail | |
| 30 | −kms_plane_scaling@upscale-with-rotation-20x20,Fail | |
| 25 | +kms_lease@lease-uevent,Fail | |
| 31 | 26 | kms_properties@get_properties-sanity-atomic,Fail |
| 32 | 27 | kms_properties@plane-properties-atomic,Fail |
| 33 | 28 | kms_properties@plane-properties-legacy,Fail |
| 34 | 29 | kms_rmfb@close-fd,Fail |
| 35 | −kms_selftest@drm_format,Timeout | |
| 36 | −kms_selftest@drm_format_helper,Timeout | |
| 30 | +tools_test@tools_test,Fail | |
| @@ -0,0 +1,11 @@ | ||
| 1 | +# Board Name: mt8173-elm-hana | |
| 2 | +# Bug Report: https://lore.kernel.org/linux-mediatek/0b2a1899-15dd-42fa-8f63-ea0ca28dbb17@collabora.com/T/#u | |
| 3 | +# IGT Version: 1.28-g0df7b9b97 | |
| 4 | +# Linux Version: 6.9.0-rc7 | |
| 5 | +# Failure Rate: 50 | |
| 6 | +core_setmaster_vs_auth | |
| 7 | +dumb_buffer@create-clear | |
| 8 | +fbdev@unaligned-write | |
| 9 | +fbdev@write | |
| 10 | +kms_cursor_legacy@cursor-vs-flip-atomic-transitions | |
| 11 | +kms_prop_blob@invalid-set-prop | |
| @@ -0,0 +1,16 @@ | ||
| 1 | +# Skip driver specific tests | |
| 2 | +^amdgpu.* | |
| 3 | +msm_.* | |
| 4 | +nouveau_.* | |
| 5 | +panfrost_.* | |
| 6 | +^v3d.* | |
| 7 | +^vc4.* | |
| 8 | +^vmwgfx* | |
| 9 | + | |
| 10 | +# Skip intel specific tests | |
| 11 | +gem_.* | |
| 12 | +i915_.* | |
| 13 | + | |
| 14 | +# Currently fails and causes coverage loss for other tests | |
| 15 | +# since core_getversion also fails. | |
| 16 | +core_hotunplug.* | |
| @@ -1,13 +1,8 @@ | ||
| 1 | −kms_addfb_basic@addfb25-bad-modifier,Fail | |
| 2 | −kms_bw@linear-tiling-1-displays-2560x1440p,Fail | |
| 3 | −kms_bw@linear-tiling-2-displays-1920x1080p,Fail | |
| 4 | −kms_bw@linear-tiling-2-displays-2560x1440p,Fail | |
| 5 | −kms_bw@linear-tiling-2-displays-3840x2160p,Fail | |
| 6 | −kms_bw@linear-tiling-3-displays-2560x1440p,Fail | |
| 7 | −kms_bw@linear-tiling-3-displays-3840x2160p,Fail | |
| 8 | −kms_color@pipe-A-invalid-gamma-lut-sizes,Fail | |
| 9 | −kms_plane_cursor@overlay,Fail | |
| 10 | −kms_plane_cursor@primary,Fail | |
| 11 | −kms_plane_cursor@viewport,Fail | |
| 12 | −kms_plane_scaling@upscale-with-rotation-20x20,Fail | |
| 13 | −kms_rmfb@close-fd,Fail | |
| 1 | +dumb_buffer@create-clear,Fail | |
| 2 | +dumb_buffer@create-valid-dumb,Fail | |
| 3 | +dumb_buffer@invalid-bpp,Fail | |
| 4 | +dumb_buffer@map-invalid-size,Fail | |
| 5 | +dumb_buffer@map-uaf,Fail | |
| 6 | +dumb_buffer@map-valid,Fail | |
| 7 | +panfrost_prime@gem-prime-import,Fail | |
| 8 | +tools_test@tools_test,Fail | |
| @@ -0,0 +1,18 @@ | ||
| 1 | +# Skip driver specific tests | |
| 2 | +^amdgpu.* | |
| 3 | +msm_.* | |
| 4 | +nouveau_.* | |
| 5 | +^v3d.* | |
| 6 | +^vc4.* | |
| 7 | +^vmwgfx* | |
| 8 | + | |
| 9 | +# Skip intel specific tests | |
| 10 | +gem_.* | |
| 11 | +i915_.* | |
| 12 | + | |
| 13 | +# Panfrost is not a KMS driver, so skip the KMS tests | |
| 14 | +kms_.* | |
| 15 | + | |
| 16 | +# Currently fails and causes coverage loss for other tests | |
| 17 | +# since core_getversion also fails. | |
| 18 | +core_hotunplug.* | |
| @@ -1,16 +1,8 @@ | ||
| 1 | −kms_3d,Fail | |
| 2 | −kms_cursor_legacy@forked-bo,Fail | |
| 3 | −kms_cursor_legacy@forked-move,Fail | |
| 4 | −kms_cursor_legacy@single-bo,Fail | |
| 5 | −kms_cursor_legacy@single-move,Fail | |
| 6 | −kms_cursor_legacy@torture-bo,Fail | |
| 7 | −kms_cursor_legacy@torture-move,Fail | |
| 8 | −kms_force_connector_basic@force-edid,Fail | |
| 9 | −kms_hdmi_inject@inject-4k,Fail | |
| 10 | −kms_plane_cursor@overlay,Fail | |
| 11 | −kms_plane_cursor@primary,Fail | |
| 12 | −kms_plane_cursor@viewport,Fail | |
| 13 | −kms_properties@connector-properties-atomic,Fail | |
| 14 | −kms_properties@connector-properties-legacy,Fail | |
| 15 | −kms_properties@get_properties-sanity-atomic,Fail | |
| 16 | −kms_properties@get_properties-sanity-non-atomic,Fail | |
| 1 | +dumb_buffer@create-clear,Fail | |
| 2 | +dumb_buffer@create-valid-dumb,Fail | |
| 3 | +dumb_buffer@invalid-bpp,Fail | |
| 4 | +dumb_buffer@map-invalid-size,Fail | |
| 5 | +dumb_buffer@map-uaf,Fail | |
| 6 | +dumb_buffer@map-valid,Fail | |
| 7 | +panfrost_prime@gem-prime-import,Fail | |
| 8 | +tools_test@tools_test,Fail | |
| @@ -0,0 +1,18 @@ | ||
| 1 | +# Skip driver specific tests | |
| 2 | +^amdgpu.* | |
| 3 | +msm_.* | |
| 4 | +nouveau_.* | |
| 5 | +^v3d.* | |
| 6 | +^vc4.* | |
| 7 | +^vmwgfx* | |
| 8 | + | |
| 9 | +# Skip intel specific tests | |
| 10 | +gem_.* | |
| 11 | +i915_.* | |
| 12 | + | |
| 13 | +# Panfrost is not a KMS driver, so skip the KMS tests | |
| 14 | +kms_.* | |
| 15 | + | |
| 16 | +# Currently fails and causes coverage loss for other tests | |
| 17 | +# since core_getversion also fails. | |
| 18 | +core_hotunplug.* | |
| @@ -1,19 +1,15 @@ | ||
| 1 | +device_reset@cold-reset-bound,Fail | |
| 2 | +device_reset@reset-bound,Fail | |
| 3 | +device_reset@unbind-cold-reset-rebind,Fail | |
| 4 | +device_reset@unbind-reset-rebind,Fail | |
| 5 | +dumb_buffer@invalid-bpp,Fail | |
| 1 | 6 | kms_3d,Fail |
| 2 | −kms_addfb_basic@addfb25-bad-modifier,Fail | |
| 3 | −kms_cursor_legacy@all-pipes-forked-bo,Fail | |
| 4 | −kms_cursor_legacy@all-pipes-forked-move,Fail | |
| 5 | −kms_cursor_legacy@all-pipes-single-bo,Fail | |
| 6 | −kms_cursor_legacy@all-pipes-single-move,Fail | |
| 7 | −kms_cursor_legacy@all-pipes-torture-bo,Fail | |
| 8 | −kms_cursor_legacy@all-pipes-torture-move,Fail | |
| 9 | −kms_cursor_legacy@pipe-A-forked-bo,Fail | |
| 10 | −kms_cursor_legacy@pipe-A-forked-move,Fail | |
| 11 | −kms_cursor_legacy@pipe-A-single-bo,Fail | |
| 12 | −kms_cursor_legacy@pipe-A-single-move,Fail | |
| 13 | −kms_cursor_legacy@pipe-A-torture-bo,Fail | |
| 14 | −kms_cursor_legacy@pipe-A-torture-move,Fail | |
| 7 | +kms_cursor_legacy@forked-move,Fail | |
| 8 | +kms_cursor_legacy@single-bo,Fail | |
| 9 | +kms_cursor_legacy@torture-bo,Fail | |
| 10 | +kms_cursor_legacy@torture-move,Fail | |
| 15 | 11 | kms_force_connector_basic@force-edid,Fail |
| 16 | 12 | kms_hdmi_inject@inject-4k,Fail |
| 17 | −kms_selftest@drm_format,Timeout | |
| 18 | −kms_selftest@drm_format_helper,Timeout | |
| 13 | +kms_lease@lease-uevent,Fail | |
| 19 | 14 | msm_mapping@ring,Fail |
| 15 | +tools_test@tools_test,Fail | |
| @@ -0,0 +1,15 @@ | ||
| 1 | +# Skip driver specific tests | |
| 2 | +^amdgpu.* | |
| 3 | +nouveau_.* | |
| 4 | +panfrost_.* | |
| 5 | +^v3d.* | |
| 6 | +^vc4.* | |
| 7 | +^vmwgfx* | |
| 8 | + | |
| 9 | +# Skip intel specific tests | |
| 10 | +gem_.* | |
| 11 | +i915_.* | |
| 12 | + | |
| 13 | +# Currently fails and causes coverage loss for other tests | |
| 14 | +# since core_getversion also fails. | |
| 15 | +core_hotunplug.* | |
| @@ -1,2 +1,8 @@ | ||
| 1 | +device_reset@cold-reset-bound,Fail | |
| 2 | +device_reset@reset-bound,Fail | |
| 3 | +device_reset@unbind-cold-reset-rebind,Fail | |
| 4 | +device_reset@unbind-reset-rebind,Fail | |
| 5 | +dumb_buffer@invalid-bpp,Fail | |
| 1 | 6 | kms_3d,Fail |
| 2 | −kms_addfb_basic@addfb25-bad-modifier,Fail | |
| 7 | +kms_lease@lease-uevent,Fail | |
| 8 | +tools_test@tools_test,Fail | |
| @@ -0,0 +1,6 @@ | ||
| 1 | +# Board Name: apq8096-db820c | |
| 2 | +# Bug Report: https://lore.kernel.org/linux-arm-msm/661483c8-ad82-400d-bcd8-e94986d20d7d@collabora.com/T/#u | |
| 3 | +# IGT Version: 1.28-g0df7b9b97 | |
| 4 | +# Linux Version: 6.9.0-rc7 | |
| 5 | +# Failure Rate: 50 | |
| 6 | +dumb_buffer@create-clear | |
| @@ -1,2 +1,26 @@ | ||
| 1 | 1 | # Whole machine hangs |
| 2 | −kms_cursor_legacy@all-pipes-torture-move | |
| 2 | +kms_cursor_legacy@all-pipes-torture-move | |
| 3 | + | |
| 4 | +# Skip driver specific tests | |
| 5 | +^amdgpu.* | |
| 6 | +nouveau_.* | |
| 7 | +panfrost_.* | |
| 8 | +^v3d.* | |
| 9 | +^vc4.* | |
| 10 | +^vmwgfx* | |
| 11 | + | |
| 12 | +# Skip intel specific tests | |
| 13 | +gem_.* | |
| 14 | +i915_.* | |
| 15 | + | |
| 16 | +# Currently fails and causes coverage loss for other tests | |
| 17 | +# since core_getversion also fails. | |
| 18 | +core_hotunplug.* | |
| 19 | + | |
| 20 | +# gpu fault | |
| 21 | +# [IGT] msm_mapping: executing | |
| 22 | +# [IGT] msm_mapping: starting subtest shadow | |
| 23 | +# *** gpu fault: ttbr0=00000001030ea000 iova=0000000001074000 dir=WRITE type=PERMISSION source=1f030000 (0,0,0,0) | |
| 24 | +# msm_mdp 901000.display-controller: RBBM | ME master split | status=0x701000B0 | |
| 25 | +# watchdog: BUG: soft lockup - CPU#0 stuck for 26s! [kworker/u16:3:46] | |
| 26 | +msm_mapping@shadow | |
| @@ -1,18 +1,191 @@ | ||
| 1 | +device_reset@cold-reset-bound,Fail | |
| 2 | +device_reset@reset-bound,Fail | |
| 3 | +device_reset@unbind-cold-reset-rebind,Fail | |
| 4 | +device_reset@unbind-reset-rebind,Fail | |
| 5 | +dumb_buffer@invalid-bpp,Fail | |
| 6 | +kms_atomic_transition@plane-primary-toggle-with-vblank-wait,Fail | |
| 1 | 7 | kms_color@ctm-0-25,Fail |
| 2 | 8 | kms_color@ctm-0-50,Fail |
| 3 | 9 | kms_color@ctm-0-75,Fail |
| 4 | 10 | kms_color@ctm-blue-to-red,Fail |
| 5 | 11 | kms_color@ctm-green-to-red,Fail |
| 12 | +kms_color@ctm-max,Fail | |
| 6 | 13 | kms_color@ctm-negative,Fail |
| 7 | 14 | kms_color@ctm-red-to-blue,Fail |
| 8 | 15 | kms_color@ctm-signed,Fail |
| 16 | +kms_content_protection@atomic,Crash | |
| 17 | +kms_content_protection@atomic-dpms,Crash | |
| 18 | +kms_content_protection@content-type-change,Crash | |
| 19 | +kms_content_protection@lic-type-0,Crash | |
| 20 | +kms_content_protection@lic-type-1,Crash | |
| 21 | +kms_content_protection@srm,Crash | |
| 22 | +kms_content_protection@type1,Crash | |
| 23 | +kms_content_protection@uevent,Crash | |
| 24 | +kms_cursor_crc@cursor-alpha-opaque,Fail | |
| 25 | +kms_cursor_crc@cursor-alpha-transparent,Fail | |
| 26 | +kms_cursor_crc@cursor-dpms,Fail | |
| 27 | +kms_cursor_crc@cursor-offscreen-128x128,Fail | |
| 28 | +kms_cursor_crc@cursor-offscreen-128x42,Fail | |
| 29 | +kms_cursor_crc@cursor-offscreen-256x256,Fail | |
| 30 | +kms_cursor_crc@cursor-offscreen-256x85,Fail | |
| 31 | +kms_cursor_crc@cursor-offscreen-32x10,Fail | |
| 32 | +kms_cursor_crc@cursor-offscreen-32x32,Fail | |
| 33 | +kms_cursor_crc@cursor-offscreen-512x170,Fail | |
| 34 | +kms_cursor_crc@cursor-offscreen-512x512,Fail | |
| 35 | +kms_cursor_crc@cursor-offscreen-64x21,Fail | |
| 36 | +kms_cursor_crc@cursor-offscreen-64x64,Fail | |
| 37 | +kms_cursor_crc@cursor-onscreen-128x128,Fail | |
| 38 | +kms_cursor_crc@cursor-onscreen-128x42,Fail | |
| 39 | +kms_cursor_crc@cursor-onscreen-256x256,Fail | |
| 40 | +kms_cursor_crc@cursor-onscreen-256x85,Fail | |
| 41 | +kms_cursor_crc@cursor-onscreen-32x10,Fail | |
| 42 | +kms_cursor_crc@cursor-onscreen-32x32,Fail | |
| 43 | +kms_cursor_crc@cursor-onscreen-512x170,Fail | |
| 44 | +kms_cursor_crc@cursor-onscreen-512x512,Fail | |
| 45 | +kms_cursor_crc@cursor-onscreen-64x21,Fail | |
| 46 | +kms_cursor_crc@cursor-onscreen-64x64,Fail | |
| 47 | +kms_cursor_crc@cursor-random-128x128,Fail | |
| 48 | +kms_cursor_crc@cursor-random-128x42,Fail | |
| 49 | +kms_cursor_crc@cursor-random-256x256,Fail | |
| 50 | +kms_cursor_crc@cursor-random-256x85,Fail | |
| 51 | +kms_cursor_crc@cursor-random-32x10,Fail | |
| 52 | +kms_cursor_crc@cursor-random-32x32,Fail | |
| 53 | +kms_cursor_crc@cursor-random-512x170,Fail | |
| 54 | +kms_cursor_crc@cursor-random-512x512,Fail | |
| 55 | +kms_cursor_crc@cursor-random-64x21,Fail | |
| 56 | +kms_cursor_crc@cursor-random-64x64,Fail | |
| 57 | +kms_cursor_crc@cursor-rapid-movement-128x128,Fail | |
| 58 | +kms_cursor_crc@cursor-rapid-movement-128x42,Fail | |
| 59 | +kms_cursor_crc@cursor-rapid-movement-256x256,Fail | |
| 60 | +kms_cursor_crc@cursor-rapid-movement-256x85,Fail | |
| 61 | +kms_cursor_crc@cursor-rapid-movement-32x10,Fail | |
| 62 | +kms_cursor_crc@cursor-rapid-movement-32x32,Fail | |
| 63 | +kms_cursor_crc@cursor-rapid-movement-512x170,Fail | |
| 64 | +kms_cursor_crc@cursor-rapid-movement-512x512,Fail | |
| 65 | +kms_cursor_crc@cursor-rapid-movement-64x21,Fail | |
| 66 | +kms_cursor_crc@cursor-rapid-movement-64x64,Fail | |
| 67 | +kms_cursor_crc@cursor-size-change,Fail | |
| 68 | +kms_cursor_crc@cursor-sliding-128x128,Fail | |
| 69 | +kms_cursor_crc@cursor-sliding-128x42,Fail | |
| 70 | +kms_cursor_crc@cursor-sliding-256x256,Fail | |
| 71 | +kms_cursor_crc@cursor-sliding-256x85,Fail | |
| 72 | +kms_cursor_crc@cursor-sliding-32x10,Fail | |
| 73 | +kms_cursor_crc@cursor-sliding-32x32,Fail | |
| 74 | +kms_cursor_crc@cursor-sliding-512x170,Fail | |
| 75 | +kms_cursor_crc@cursor-sliding-512x512,Fail | |
| 76 | +kms_cursor_crc@cursor-sliding-64x21,Fail | |
| 77 | +kms_cursor_crc@cursor-sliding-64x64,Fail | |
| 78 | +kms_cursor_edge_walk@128x128-left-edge,Fail | |
| 79 | +kms_cursor_edge_walk@128x128-right-edge,Fail | |
| 80 | +kms_cursor_edge_walk@128x128-top-bottom,Fail | |
| 81 | +kms_cursor_edge_walk@128x128-top-edge,Fail | |
| 82 | +kms_cursor_edge_walk@256x256-left-edge,Fail | |
| 83 | +kms_cursor_edge_walk@256x256-right-edge,Fail | |
| 84 | +kms_cursor_edge_walk@256x256-top-bottom,Fail | |
| 85 | +kms_cursor_edge_walk@256x256-top-edge,Fail | |
| 86 | +kms_cursor_edge_walk@64x64-left-edge,Fail | |
| 87 | +kms_cursor_edge_walk@64x64-right-edge,Fail | |
| 88 | +kms_cursor_edge_walk@64x64-top-bottom,Fail | |
| 89 | +kms_cursor_edge_walk@64x64-top-edge,Fail | |
| 90 | +kms_cursor_legacy@2x-cursor-vs-flip-atomic,Fail | |
| 91 | +kms_cursor_legacy@2x-cursor-vs-flip-legacy,Fail | |
| 92 | +kms_cursor_legacy@2x-flip-vs-cursor-atomic,Fail | |
| 93 | +kms_cursor_legacy@2x-flip-vs-cursor-legacy,Fail | |
| 94 | +kms_cursor_legacy@2x-long-cursor-vs-flip-atomic,Fail | |
| 95 | +kms_cursor_legacy@2x-long-cursor-vs-flip-legacy,Fail | |
| 96 | +kms_cursor_legacy@2x-long-flip-vs-cursor-atomic,Fail | |
| 97 | +kms_cursor_legacy@2x-long-flip-vs-cursor-legacy,Fail | |
| 9 | 98 | kms_cursor_legacy@cursor-vs-flip-toggle,Fail |
| 10 | 99 | kms_cursor_legacy@cursor-vs-flip-varying-size,Fail |
| 100 | +kms_display_modes@extended-mode-basic,Fail | |
| 101 | +kms_flip@2x-flip-vs-modeset-vs-hang,Fail | |
| 102 | +kms_flip@2x-flip-vs-panning-vs-hang,Fail | |
| 103 | +kms_flip@absolute-wf_vblank,Fail | |
| 104 | +kms_flip@absolute-wf_vblank-interruptible,Fail | |
| 105 | +kms_flip@basic-flip-vs-wf_vblank,Fail | |
| 106 | +kms_flip@basic-plain-flip,Fail | |
| 107 | +kms_flip@blocking-absolute-wf_vblank,Fail | |
| 108 | +kms_flip@blocking-absolute-wf_vblank-interruptible,Fail | |
| 109 | +kms_flip@blocking-wf_vblank,Fail | |
| 110 | +kms_flip@busy-flip,Fail | |
| 111 | +kms_flip@dpms-off-confusion,Fail | |
| 112 | +kms_flip@dpms-off-confusion-interruptible,Fail | |
| 113 | +kms_flip@dpms-vs-vblank-race,Fail | |
| 114 | +kms_flip@dpms-vs-vblank-race-interruptible,Fail | |
| 115 | +kms_flip@flip-vs-absolute-wf_vblank,Fail | |
| 116 | +kms_flip@flip-vs-absolute-wf_vblank-interruptible,Fail | |
| 117 | +kms_flip@flip-vs-blocking-wf-vblank,Fail | |
| 118 | +kms_flip@flip-vs-expired-vblank,Fail | |
| 119 | +kms_flip@flip-vs-expired-vblank-interruptible,Fail | |
| 11 | 120 | kms_flip@flip-vs-modeset-vs-hang,Fail |
| 121 | +kms_flip@flip-vs-panning,Fail | |
| 122 | +kms_flip@flip-vs-panning-interruptible,Fail | |
| 12 | 123 | kms_flip@flip-vs-panning-vs-hang,Fail |
| 124 | +kms_flip@flip-vs-rmfb,Fail | |
| 125 | +kms_flip@flip-vs-rmfb-interruptible,Fail | |
| 126 | +kms_flip@flip-vs-wf_vblank-interruptible,Fail | |
| 127 | +kms_flip@modeset-vs-vblank-race,Fail | |
| 128 | +kms_flip@modeset-vs-vblank-race-interruptible,Fail | |
| 129 | +kms_flip@plain-flip-fb-recreate,Fail | |
| 130 | +kms_flip@plain-flip-fb-recreate-interruptible,Fail | |
| 131 | +kms_flip@plain-flip-interruptible,Fail | |
| 132 | +kms_flip@plain-flip-ts-check,Fail | |
| 133 | +kms_flip@plain-flip-ts-check-interruptible,Fail | |
| 134 | +kms_flip@wf_vblank-ts-check,Fail | |
| 135 | +kms_flip@wf_vblank-ts-check-interruptible,Fail | |
| 136 | +kms_lease@cursor-implicit-plane,Fail | |
| 137 | +kms_lease@lease-uevent,Fail | |
| 138 | +kms_lease@page-flip-implicit-plane,Fail | |
| 139 | +kms_lease@setcrtc-implicit-plane,Fail | |
| 140 | +kms_lease@simple-lease,Fail | |
| 141 | +kms_multipipe_modeset@basic-max-pipe-crc-check,Fail | |
| 13 | 142 | kms_pipe_crc_basic@compare-crc-sanitycheck-nv12,Fail |
| 143 | +kms_pipe_crc_basic@compare-crc-sanitycheck-xr24,Fail | |
| 144 | +kms_pipe_crc_basic@disable-crc-after-crtc,Fail | |
| 145 | +kms_pipe_crc_basic@nonblocking-crc,Fail | |
| 146 | +kms_pipe_crc_basic@nonblocking-crc-frame-sequence,Fail | |
| 147 | +kms_pipe_crc_basic@read-crc,Fail | |
| 148 | +kms_pipe_crc_basic@read-crc-frame-sequence,Fail | |
| 149 | +kms_plane@pixel-format,Fail | |
| 150 | +kms_plane@pixel-format-source-clamping,Fail | |
| 151 | +kms_plane@plane-panning-bottom-right,Fail | |
| 152 | +kms_plane@plane-panning-top-left,Fail | |
| 153 | +kms_plane@plane-position-covered,Fail | |
| 154 | +kms_plane@plane-position-hole,Fail | |
| 155 | +kms_plane@plane-position-hole-dpms,Fail | |
| 14 | 156 | kms_plane_alpha_blend@alpha-7efc,Fail |
| 157 | +kms_plane_alpha_blend@alpha-basic,Fail | |
| 158 | +kms_plane_alpha_blend@alpha-opaque-fb,Fail | |
| 159 | +kms_plane_alpha_blend@alpha-transparent-fb,Fail | |
| 160 | +kms_plane_alpha_blend@constant-alpha-max,Fail | |
| 161 | +kms_plane_alpha_blend@constant-alpha-mid,Fail | |
| 162 | +kms_plane_alpha_blend@constant-alpha-min,Fail | |
| 15 | 163 | kms_plane_alpha_blend@coverage-7efc,Fail |
| 16 | 164 | kms_plane_alpha_blend@coverage-vs-premult-vs-constant,Fail |
| 165 | +kms_plane_cursor@primary,Fail | |
| 166 | +kms_plane_lowres@tiling-none,Fail | |
| 167 | +kms_plane_multiple@tiling-none,Fail | |
| 17 | 168 | kms_rmfb@close-fd,Fail |
| 18 | −kms_universal_plane@universal-plane-sanity,Fail | |
| 169 | +kms_rotation_crc@cursor-rotation-180,Fail | |
| 170 | +kms_rotation_crc@primary-rotation-180,Fail | |
| 171 | +kms_sequence@get-busy,Fail | |
| 172 | +kms_sequence@get-forked,Fail | |
| 173 | +kms_sequence@get-forked-busy,Fail | |
| 174 | +kms_sequence@get-idle,Fail | |
| 175 | +kms_sequence@queue-busy,Fail | |
| 176 | +kms_sequence@queue-idle,Fail | |
| 177 | +kms_vblank@accuracy-idle,Fail | |
| 178 | +kms_vblank@crtc-id,Fail | |
| 179 | +kms_vblank@query-busy,Fail | |
| 180 | +kms_vblank@query-forked,Fail | |
| 181 | +kms_vblank@query-forked-busy,Fail | |
| 182 | +kms_vblank@query-idle,Fail | |
| 183 | +kms_vblank@ts-continuation-dpms-rpm,Fail | |
| 184 | +kms_vblank@ts-continuation-idle,Fail | |
| 185 | +kms_vblank@ts-continuation-modeset,Fail | |
| 186 | +kms_vblank@ts-continuation-modeset-rpm,Fail | |
| 187 | +kms_vblank@wait-busy,Fail | |
| 188 | +kms_vblank@wait-forked,Fail | |
| 189 | +kms_vblank@wait-forked-busy,Fail | |
| 190 | +kms_vblank@wait-idle,Fail | |
| 191 | +tools_test@tools_test,Fail | |
| @@ -0,0 +1,8 @@ | ||
| 1 | +# Board Name: sc7180-trogdor-kingoftown | |
| 2 | +# Bug Report: https://lore.kernel.org/linux-arm-msm/661483c8-ad82-400d-bcd8-e94986d20d7d@collabora.com/T/#u | |
| 3 | +# IGT Version: 1.28-g0df7b9b97 | |
| 4 | +# Linux Version: 6.9.0-rc7 | |
| 5 | +# Failure Rate: 50 | |
| 6 | +msm_mapping@shadow | |
| 7 | +msm_shrink@copy-gpu-oom-32 | |
| 8 | +msm_shrink@copy-gpu-oom-8 | |
| @@ -1,2 +1,21 @@ | ||
| 1 | 1 | # Suspend to RAM seems to be broken on this machine |
| 2 | 2 | .*suspend.* |
| 3 | + | |
| 4 | +# Skip driver specific tests | |
| 5 | +^amdgpu.* | |
| 6 | +nouveau_.* | |
| 7 | +panfrost_.* | |
| 8 | +^v3d.* | |
| 9 | +^vc4.* | |
| 10 | +^vmwgfx* | |
| 11 | + | |
| 12 | +# Skip intel specific tests | |
| 13 | +gem_.* | |
| 14 | +i915_.* | |
| 15 | + | |
| 16 | +# Currently fails and causes coverage loss for other tests | |
| 17 | +# since core_getversion also fails. | |
| 18 | +core_hotunplug.* | |
| 19 | + | |
| 20 | +# Timeout occurs | |
| 21 | +kms_flip@2x-wf_vblank-ts-check | |
| @@ -1,18 +1,191 @@ | ||
| 1 | +device_reset@cold-reset-bound,Fail | |
| 2 | +device_reset@reset-bound,Fail | |
| 3 | +device_reset@unbind-cold-reset-rebind,Fail | |
| 4 | +device_reset@unbind-reset-rebind,Fail | |
| 5 | +dumb_buffer@invalid-bpp,Fail | |
| 6 | +kms_atomic_transition@plane-primary-toggle-with-vblank-wait,Fail | |
| 1 | 7 | kms_color@ctm-0-25,Fail |
| 2 | 8 | kms_color@ctm-0-50,Fail |
| 3 | 9 | kms_color@ctm-0-75,Fail |
| 4 | 10 | kms_color@ctm-blue-to-red,Fail |
| 5 | 11 | kms_color@ctm-green-to-red,Fail |
| 12 | +kms_color@ctm-max,Fail | |
| 6 | 13 | kms_color@ctm-negative,Fail |
| 7 | 14 | kms_color@ctm-red-to-blue,Fail |
| 8 | 15 | kms_color@ctm-signed,Fail |
| 16 | +kms_content_protection@atomic,Crash | |
| 17 | +kms_content_protection@atomic-dpms,Crash | |
| 18 | +kms_content_protection@content-type-change,Crash | |
| 19 | +kms_content_protection@lic-type-0,Crash | |
| 20 | +kms_content_protection@lic-type-1,Crash | |
| 21 | +kms_content_protection@srm,Crash | |
| 22 | +kms_content_protection@type1,Crash | |
| 23 | +kms_content_protection@uevent,Crash | |
| 24 | +kms_cursor_crc@cursor-alpha-opaque,Fail | |
| 25 | +kms_cursor_crc@cursor-alpha-transparent,Fail | |
| 26 | +kms_cursor_crc@cursor-dpms,Fail | |
| 27 | +kms_cursor_crc@cursor-offscreen-128x128,Fail | |
| 28 | +kms_cursor_crc@cursor-offscreen-128x42,Fail | |
| 29 | +kms_cursor_crc@cursor-offscreen-256x256,Fail | |
| 30 | +kms_cursor_crc@cursor-offscreen-256x85,Fail | |
| 31 | +kms_cursor_crc@cursor-offscreen-32x10,Fail | |
| 32 | +kms_cursor_crc@cursor-offscreen-32x32,Fail | |
| 33 | +kms_cursor_crc@cursor-offscreen-512x170,Fail | |
| 34 | +kms_cursor_crc@cursor-offscreen-512x512,Fail | |
| 35 | +kms_cursor_crc@cursor-offscreen-64x21,Fail | |
| 36 | +kms_cursor_crc@cursor-offscreen-64x64,Fail | |
| 37 | +kms_cursor_crc@cursor-onscreen-128x128,Fail | |
| 38 | +kms_cursor_crc@cursor-onscreen-128x42,Fail | |
| 39 | +kms_cursor_crc@cursor-onscreen-256x256,Fail | |
| 40 | +kms_cursor_crc@cursor-onscreen-256x85,Fail | |
| 41 | +kms_cursor_crc@cursor-onscreen-32x10,Fail | |
| 42 | +kms_cursor_crc@cursor-onscreen-32x32,Fail | |
| 43 | +kms_cursor_crc@cursor-onscreen-512x170,Fail | |
| 44 | +kms_cursor_crc@cursor-onscreen-512x512,Fail | |
| 45 | +kms_cursor_crc@cursor-onscreen-64x21,Fail | |
| 46 | +kms_cursor_crc@cursor-onscreen-64x64,Fail | |
| 47 | +kms_cursor_crc@cursor-random-128x128,Fail | |
| 48 | +kms_cursor_crc@cursor-random-128x42,Fail | |
| 49 | +kms_cursor_crc@cursor-random-256x256,Fail | |
| 50 | +kms_cursor_crc@cursor-random-256x85,Fail | |
| 51 | +kms_cursor_crc@cursor-random-32x10,Fail | |
| 52 | +kms_cursor_crc@cursor-random-32x32,Fail | |
| 53 | +kms_cursor_crc@cursor-random-512x170,Fail | |
| 54 | +kms_cursor_crc@cursor-random-512x512,Fail | |
| 55 | +kms_cursor_crc@cursor-random-64x21,Fail | |
| 56 | +kms_cursor_crc@cursor-random-64x64,Fail | |
| 57 | +kms_cursor_crc@cursor-rapid-movement-128x128,Fail | |
| 58 | +kms_cursor_crc@cursor-rapid-movement-128x42,Fail | |
| 59 | +kms_cursor_crc@cursor-rapid-movement-256x256,Fail | |
| 60 | +kms_cursor_crc@cursor-rapid-movement-256x85,Fail | |
| 61 | +kms_cursor_crc@cursor-rapid-movement-32x10,Fail | |
| 62 | +kms_cursor_crc@cursor-rapid-movement-32x32,Fail | |
| 63 | +kms_cursor_crc@cursor-rapid-movement-512x170,Fail | |
| 64 | +kms_cursor_crc@cursor-rapid-movement-512x512,Fail | |
| 65 | +kms_cursor_crc@cursor-rapid-movement-64x21,Fail | |
| 66 | +kms_cursor_crc@cursor-rapid-movement-64x64,Fail | |
| 67 | +kms_cursor_crc@cursor-size-change,Fail | |
| 68 | +kms_cursor_crc@cursor-sliding-128x128,Fail | |
| 69 | +kms_cursor_crc@cursor-sliding-128x42,Fail | |
| 70 | +kms_cursor_crc@cursor-sliding-256x256,Fail | |
| 71 | +kms_cursor_crc@cursor-sliding-256x85,Fail | |
| 72 | +kms_cursor_crc@cursor-sliding-32x10,Fail | |
| 73 | +kms_cursor_crc@cursor-sliding-32x32,Fail | |
| 74 | +kms_cursor_crc@cursor-sliding-512x170,Fail | |
| 75 | +kms_cursor_crc@cursor-sliding-512x512,Fail | |
| 76 | +kms_cursor_crc@cursor-sliding-64x21,Fail | |
| 77 | +kms_cursor_crc@cursor-sliding-64x64,Fail | |
| 78 | +kms_cursor_edge_walk@128x128-left-edge,Fail | |
| 79 | +kms_cursor_edge_walk@128x128-right-edge,Fail | |
| 80 | +kms_cursor_edge_walk@128x128-top-bottom,Fail | |
| 81 | +kms_cursor_edge_walk@128x128-top-edge,Fail | |
| 82 | +kms_cursor_edge_walk@256x256-left-edge,Fail | |
| 83 | +kms_cursor_edge_walk@256x256-right-edge,Fail | |
| 84 | +kms_cursor_edge_walk@256x256-top-bottom,Fail | |
| 85 | +kms_cursor_edge_walk@256x256-top-edge,Fail | |
| 86 | +kms_cursor_edge_walk@64x64-left-edge,Fail | |
| 87 | +kms_cursor_edge_walk@64x64-right-edge,Fail | |
| 88 | +kms_cursor_edge_walk@64x64-top-bottom,Fail | |
| 89 | +kms_cursor_edge_walk@64x64-top-edge,Fail | |
| 90 | +kms_cursor_legacy@2x-cursor-vs-flip-atomic,Fail | |
| 91 | +kms_cursor_legacy@2x-cursor-vs-flip-legacy,Fail | |
| 92 | +kms_cursor_legacy@2x-flip-vs-cursor-atomic,Fail | |
| 93 | +kms_cursor_legacy@2x-flip-vs-cursor-legacy,Fail | |
| 94 | +kms_cursor_legacy@2x-long-cursor-vs-flip-atomic,Fail | |
| 95 | +kms_cursor_legacy@2x-long-cursor-vs-flip-legacy,Fail | |
| 96 | +kms_cursor_legacy@2x-long-flip-vs-cursor-atomic,Fail | |
| 97 | +kms_cursor_legacy@2x-long-flip-vs-cursor-legacy,Fail | |
| 9 | 98 | kms_cursor_legacy@cursor-vs-flip-toggle,Fail |
| 10 | 99 | kms_cursor_legacy@cursor-vs-flip-varying-size,Fail |
| 100 | +kms_display_modes@extended-mode-basic,Fail | |
| 101 | +kms_flip@2x-flip-vs-modeset-vs-hang,Fail | |
| 102 | +kms_flip@2x-flip-vs-panning-vs-hang,Fail | |
| 103 | +kms_flip@absolute-wf_vblank,Fail | |
| 104 | +kms_flip@absolute-wf_vblank-interruptible,Fail | |
| 105 | +kms_flip@basic-flip-vs-wf_vblank,Fail | |
| 106 | +kms_flip@basic-plain-flip,Fail | |
| 107 | +kms_flip@blocking-absolute-wf_vblank,Fail | |
| 108 | +kms_flip@blocking-absolute-wf_vblank-interruptible,Fail | |
| 109 | +kms_flip@blocking-wf_vblank,Fail | |
| 110 | +kms_flip@busy-flip,Fail | |
| 111 | +kms_flip@dpms-off-confusion,Fail | |
| 112 | +kms_flip@dpms-off-confusion-interruptible,Fail | |
| 113 | +kms_flip@dpms-vs-vblank-race,Fail | |
| 114 | +kms_flip@dpms-vs-vblank-race-interruptible,Fail | |
| 115 | +kms_flip@flip-vs-absolute-wf_vblank,Fail | |
| 116 | +kms_flip@flip-vs-absolute-wf_vblank-interruptible,Fail | |
| 117 | +kms_flip@flip-vs-blocking-wf-vblank,Fail | |
| 118 | +kms_flip@flip-vs-expired-vblank,Fail | |
| 119 | +kms_flip@flip-vs-expired-vblank-interruptible,Fail | |
| 11 | 120 | kms_flip@flip-vs-modeset-vs-hang,Fail |
| 121 | +kms_flip@flip-vs-panning,Fail | |
| 122 | +kms_flip@flip-vs-panning-interruptible,Fail | |
| 12 | 123 | kms_flip@flip-vs-panning-vs-hang,Fail |
| 124 | +kms_flip@flip-vs-rmfb,Fail | |
| 125 | +kms_flip@flip-vs-rmfb-interruptible,Fail | |
| 126 | +kms_flip@flip-vs-wf_vblank-interruptible,Fail | |
| 127 | +kms_flip@modeset-vs-vblank-race,Fail | |
| 128 | +kms_flip@modeset-vs-vblank-race-interruptible,Fail | |
| 129 | +kms_flip@plain-flip-fb-recreate,Fail | |
| 130 | +kms_flip@plain-flip-fb-recreate-interruptible,Fail | |
| 131 | +kms_flip@plain-flip-interruptible,Fail | |
| 132 | +kms_flip@plain-flip-ts-check,Fail | |
| 133 | +kms_flip@plain-flip-ts-check-interruptible,Fail | |
| 134 | +kms_flip@wf_vblank-ts-check,Fail | |
| 135 | +kms_flip@wf_vblank-ts-check-interruptible,Fail | |
| 136 | +kms_lease@cursor-implicit-plane,Fail | |
| 137 | +kms_lease@lease-uevent,Fail | |
| 138 | +kms_lease@page-flip-implicit-plane,Fail | |
| 139 | +kms_lease@setcrtc-implicit-plane,Fail | |
| 140 | +kms_lease@simple-lease,Fail | |
| 141 | +kms_multipipe_modeset@basic-max-pipe-crc-check,Fail | |
| 13 | 142 | kms_pipe_crc_basic@compare-crc-sanitycheck-nv12,Fail |
| 143 | +kms_pipe_crc_basic@compare-crc-sanitycheck-xr24,Fail | |
| 144 | +kms_pipe_crc_basic@disable-crc-after-crtc,Fail | |
| 145 | +kms_pipe_crc_basic@nonblocking-crc,Fail | |
| 146 | +kms_pipe_crc_basic@nonblocking-crc-frame-sequence,Fail | |
| 147 | +kms_pipe_crc_basic@read-crc,Fail | |
| 148 | +kms_pipe_crc_basic@read-crc-frame-sequence,Fail | |
| 149 | +kms_plane@pixel-format,Fail | |
| 150 | +kms_plane@pixel-format-source-clamping,Fail | |
| 151 | +kms_plane@plane-panning-bottom-right,Fail | |
| 152 | +kms_plane@plane-panning-top-left,Fail | |
| 153 | +kms_plane@plane-position-covered,Fail | |
| 154 | +kms_plane@plane-position-hole,Fail | |
| 155 | +kms_plane@plane-position-hole-dpms,Fail | |
| 14 | 156 | kms_plane_alpha_blend@alpha-7efc,Fail |
| 157 | +kms_plane_alpha_blend@alpha-basic,Fail | |
| 158 | +kms_plane_alpha_blend@alpha-opaque-fb,Fail | |
| 159 | +kms_plane_alpha_blend@alpha-transparent-fb,Fail | |
| 160 | +kms_plane_alpha_blend@constant-alpha-max,Fail | |
| 161 | +kms_plane_alpha_blend@constant-alpha-mid,Fail | |
| 162 | +kms_plane_alpha_blend@constant-alpha-min,Fail | |
| 15 | 163 | kms_plane_alpha_blend@coverage-7efc,Fail |
| 16 | 164 | kms_plane_alpha_blend@coverage-vs-premult-vs-constant,Fail |
| 165 | +kms_plane_cursor@primary,Fail | |
| 166 | +kms_plane_lowres@tiling-none,Fail | |
| 167 | +kms_plane_multiple@tiling-none,Fail | |
| 17 | 168 | kms_rmfb@close-fd,Fail |
| 18 | −kms_universal_plane@universal-plane-sanity,Fail | |
| 169 | +kms_rotation_crc@cursor-rotation-180,Fail | |
| 170 | +kms_rotation_crc@primary-rotation-180,Fail | |
| 171 | +kms_sequence@get-busy,Fail | |
| 172 | +kms_sequence@get-forked,Fail | |
| 173 | +kms_sequence@get-forked-busy,Fail | |
| 174 | +kms_sequence@get-idle,Fail | |
| 175 | +kms_sequence@queue-busy,Fail | |
| 176 | +kms_sequence@queue-idle,Fail | |
| 177 | +kms_vblank@accuracy-idle,Fail | |
| 178 | +kms_vblank@crtc-id,Fail | |
| 179 | +kms_vblank@query-busy,Fail | |
| 180 | +kms_vblank@query-forked,Fail | |
| 181 | +kms_vblank@query-forked-busy,Fail | |
| 182 | +kms_vblank@query-idle,Fail | |
| 183 | +kms_vblank@ts-continuation-dpms-rpm,Fail | |
| 184 | +kms_vblank@ts-continuation-idle,Fail | |
| 185 | +kms_vblank@ts-continuation-modeset,Fail | |
| 186 | +kms_vblank@ts-continuation-modeset-rpm,Fail | |
| 187 | +kms_vblank@wait-busy,Fail | |
| 188 | +kms_vblank@wait-forked,Fail | |
| 189 | +kms_vblank@wait-forked-busy,Fail | |
| 190 | +kms_vblank@wait-idle,Fail | |
| 191 | +tools_test@tools_test,Fail | |
| @@ -0,0 +1,6 @@ | ||
| 1 | +# Board Name: sc7180-trogdor-lazor-limozeen-nots-r5 | |
| 2 | +# Bug Report: https://lore.kernel.org/linux-arm-msm/661483c8-ad82-400d-bcd8-e94986d20d7d@collabora.com/T/#u | |
| 3 | +# IGT Version: 1.28-g0df7b9b97 | |
| 4 | +# Linux Version: 6.9.0-rc7 | |
| 5 | +# Failure Rate: 50 | |
| 6 | +msm_mapping@shadow | |
| @@ -1,2 +1,18 @@ | ||
| 1 | 1 | # Suspend to RAM seems to be broken on this machine |
| 2 | 2 | .*suspend.* |
| 3 | + | |
| 4 | +# Skip driver specific tests | |
| 5 | +^amdgpu.* | |
| 6 | +nouveau_.* | |
| 7 | +panfrost_.* | |
| 8 | +^v3d.* | |
| 9 | +^vc4.* | |
| 10 | +^vmwgfx* | |
| 11 | + | |
| 12 | +# Skip intel specific tests | |
| 13 | +gem_.* | |
| 14 | +i915_.* | |
| 15 | + | |
| 16 | +# Currently fails and causes coverage loss for other tests | |
| 17 | +# since core_getversion also fails. | |
| 18 | +core_hotunplug.* | |
| @@ -1,3 +1,8 @@ | ||
| 1 | +device_reset@cold-reset-bound,Fail | |
| 2 | +device_reset@reset-bound,Fail | |
| 3 | +device_reset@unbind-cold-reset-rebind,Fail | |
| 4 | +device_reset@unbind-reset-rebind,Fail | |
| 5 | +dumb_buffer@invalid-bpp,Fail | |
| 1 | 6 | kms_color@ctm-0-25,Fail |
| 2 | 7 | kms_color@ctm-0-50,Fail |
| 3 | 8 | kms_color@ctm-0-75,Fail |
| @@ -6,17 +11,6 @@ kms_color@ctm-green-to-red,Fail · 2 unmodified lines | ||
| 6 | 11 | kms_color@ctm-negative,Fail |
| 7 | 12 | kms_color@ctm-red-to-blue,Fail |
| 8 | 13 | kms_color@ctm-signed,Fail |
| 9 | −kms_color@pipe-A-ctm-0-25,Fail | |
| 10 | −kms_color@pipe-A-ctm-0-5,Fail | |
| 11 | −kms_color@pipe-A-ctm-0-75,Fail | |
| 12 | −kms_color@pipe-A-ctm-blue-to-red,Fail | |
| 13 | −kms_color@pipe-A-ctm-green-to-red,Fail | |
| 14 | −kms_color@pipe-A-ctm-max,Fail | |
| 15 | −kms_color@pipe-A-ctm-negative,Fail | |
| 16 | −kms_color@pipe-A-ctm-red-to-blue,Fail | |
| 17 | −kms_color@pipe-A-legacy-gamma,Fail | |
| 18 | −kms_cursor_legacy@basic-flip-after-cursor-atomic,Fail | |
| 19 | −kms_cursor_legacy@basic-flip-after-cursor-varying-size,Fail | |
| 20 | 14 | kms_cursor_legacy@basic-flip-before-cursor-atomic,Fail |
| 21 | 15 | kms_cursor_legacy@basic-flip-before-cursor-legacy,Fail |
| 22 | 16 | kms_cursor_legacy@cursor-vs-flip-atomic,Fail |
| @@ -31,30 +25,12 @@ kms_cursor_legacy@flip-vs-cursor-crc-legacy,Fail · 8 unmodified lines | ||
| 31 | 25 | kms_cursor_legacy@flip-vs-cursor-legacy,Fail |
| 32 | 26 | kms_flip@flip-vs-modeset-vs-hang,Fail |
| 33 | 27 | kms_flip@flip-vs-panning-vs-hang,Fail |
| 28 | +kms_lease@lease-uevent,Fail | |
| 34 | 29 | kms_pipe_crc_basic@compare-crc-sanitycheck-nv12,Fail |
| 35 | 30 | kms_plane_alpha_blend@alpha-7efc,Fail |
| 36 | 31 | kms_plane_alpha_blend@coverage-7efc,Fail |
| 37 | 32 | kms_plane_alpha_blend@coverage-vs-premult-vs-constant,Fail |
| 38 | −kms_plane_alpha_blend@pipe-A-alpha-7efc,Fail | |
| 39 | −kms_plane_alpha_blend@pipe-A-coverage-7efc,Fail | |
| 40 | −kms_plane_alpha_blend@pipe-A-coverage-vs-premult-vs-constant,Fail | |
| 41 | 33 | kms_plane_cursor@overlay,Fail |
| 42 | −kms_plane_cursor@pipe-A-overlay-size-128,Fail | |
| 43 | −kms_plane_cursor@pipe-A-overlay-size-256,Fail | |
| 44 | −kms_plane_cursor@pipe-A-overlay-size-64,Fail | |
| 45 | −kms_plane_cursor@pipe-A-viewport-size-128,Fail | |
| 46 | −kms_plane_cursor@pipe-A-viewport-size-256,Fail | |
| 47 | −kms_plane_cursor@pipe-A-viewport-size-64,Fail | |
| 48 | 34 | kms_plane_cursor@viewport,Fail |
| 49 | −kms_plane_scaling@downscale-with-pixel-format-factor-0-25,Timeout | |
| 50 | −kms_plane_scaling@downscale-with-pixel-format-factor-0-5,Timeout | |
| 51 | −kms_plane_scaling@downscale-with-pixel-format-factor-0-75,Timeout | |
| 52 | −kms_plane_scaling@plane-downscale-with-pixel-format-factor-0-25,Timeout | |
| 53 | −kms_plane_scaling@plane-downscale-with-pixel-format-factor-0-5,Timeout | |
| 54 | −kms_plane_scaling@plane-downscale-with-pixel-format-factor-0-75,Timeout | |
| 55 | −kms_plane_scaling@plane-scaler-with-clipping-clamping-pixel-formats,Timeout | |
| 56 | −kms_plane_scaling@plane-scaler-with-pixel-format-unity-scaling,Timeout | |
| 57 | −kms_plane_scaling@planes-downscale-factor-0-25,Fail | |
| 58 | −kms_plane_scaling@scaler-with-clipping-clamping,Timeout | |
| 59 | −kms_plane_scaling@scaler-with-pixel-format-unity-scaling,Timeout | |
| 60 | 35 | kms_rmfb@close-fd,Fail |
| 36 | +tools_test@tools_test,Fail | |
| @@ -1,22 +1,19 @@ | ||
| 1 | −# Board Name: msm:sdm845 | |
| 2 | −# Bug Report: https://lore.kernel.org/dri-devel/46287831-edfa-78e8-6055-d7a08831c445@collabora.com/T/#u | |
| 1 | +# Board Name: sdm845-cheza-r3 | |
| 2 | +# Bug Report: https://lore.kernel.org/linux-arm-msm/661483c8-ad82-400d-bcd8-e94986d20d7d@collabora.com/T/#u | |
| 3 | +# IGT Version: 1.28-g0df7b9b97 | |
| 4 | +# Linux Version: 6.9.0-rc7 | |
| 3 | 5 | # Failure Rate: 50 |
| 4 | −# IGT Version: 1.28-gd2af13d9f | |
| 5 | −# Linux Version: 6.7.0-rc3 | |
| 6 | − | |
| 7 | −# Reported by deqp-runner | |
| 6 | +kms_cursor_legacy@basic-flip-after-cursor-atomic | |
| 8 | 7 | kms_cursor_legacy@basic-flip-after-cursor-legacy |
| 9 | −kms_cursor_legacy@flip-vs-cursor-toggle | |
| 8 | +kms_cursor_legacy@basic-flip-after-cursor-varying-size | |
| 9 | +kms_cursor_legacy@basic-flip-before-cursor-varying-size | |
| 10 | +kms_cursor_legacy@flip-vs-cursor-atomic-transitions | |
| 11 | +kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size | |
| 10 | 12 | kms_cursor_legacy@flip-vs-cursor-varying-size |
| 13 | +kms_cursor_legacy@short-flip-after-cursor-atomic-transitions | |
| 14 | +kms_cursor_legacy@short-flip-after-cursor-atomic-transitions-varying-size | |
| 11 | 15 | kms_cursor_legacy@short-flip-after-cursor-toggle |
| 12 | 16 | kms_cursor_legacy@short-flip-before-cursor-atomic-transitions |
| 13 | 17 | kms_cursor_legacy@short-flip-before-cursor-atomic-transitions-varying-size |
| 14 | 18 | msm_shrink@copy-gpu-32 |
| 15 | 19 | msm_shrink@copy-gpu-oom-32 |
| 16 | − | |
| 17 | −# The below test shows inconsistency across multiple runs, giving | |
| 18 | −# results of Pass and Fail alternately. | |
| 19 | −kms_cursor_legacy@basic-flip-before-cursor-varying-size | |
| 20 | −kms_cursor_legacy@flip-vs-cursor-atomic-transitions | |
| 21 | −kms_cursor_legacy@short-flip-after-cursor-atomic-transitions | |
| 22 | −kms_cursor_legacy@short-flip-after-cursor-atomic-transitions-varying-size | |
| @@ -5,3 +5,22 @@ kms_bw.* · 4 unmodified lines | ||
| 5 | 5 | # https://gitlab.freedesktop.org/gfx-ci/linux/-/commit/4b49f902ec6f2bb382cbbf489870573f4b43371e |
| 6 | 6 | # https://gitlab.freedesktop.org/gfx-ci/linux/-/commit/38cdf4c5559771e2474ae0fecef8469f65147bc1 |
| 7 | 7 | msm_mapping@* |
| 8 | + | |
| 9 | +# Skip driver specific tests | |
| 10 | +^amdgpu.* | |
| 11 | +nouveau_.* | |
| 12 | +panfrost_.* | |
| 13 | +^v3d.* | |
| 14 | +^vc4.* | |
| 15 | +^vmwgfx* | |
| 16 | + | |
| 17 | +# Skip intel specific tests | |
| 18 | +gem_.* | |
| 19 | +i915_.* | |
| 20 | + | |
| 21 | +# Currently fails and causes coverage loss for other tests | |
| 22 | +# since core_getversion also fails. | |
| 23 | +core_hotunplug.* | |
| 24 | + | |
| 25 | +# Whole machine hangs | |
| 26 | +kms_cursor_crc.* | |
| @@ -1,54 +1,8 @@ | ||
| 1 | −kms_3d,Crash | |
| 2 | −kms_bw@linear-tiling-2-displays-1920x1080p,Fail | |
| 3 | −kms_bw@linear-tiling-2-displays-2560x1440p,Fail | |
| 4 | −kms_bw@linear-tiling-2-displays-3840x2160p,Fail | |
| 5 | −kms_bw@linear-tiling-3-displays-1920x1080p,Fail | |
| 6 | −kms_bw@linear-tiling-3-displays-2560x1440p,Fail | |
| 7 | −kms_bw@linear-tiling-3-displays-3840x2160p,Fail | |
| 8 | −kms_flip@flip-vs-modeset-vs-hang,Crash | |
| 9 | −kms_flip@flip-vs-panning-vs-hang,Crash | |
| 10 | −kms_force_connector_basic@force-load-detect,Fail | |
| 11 | −kms_invalid_mode@int-max-clock,Crash | |
| 12 | −kms_pipe_crc_basic@compare-crc-sanitycheck-nv12,Crash | |
| 13 | −kms_pipe_crc_basic@nonblocking-crc-frame-sequence,Crash | |
| 14 | −kms_pipe_crc_basic@read-crc-frame-sequence,Crash | |
| 15 | −kms_plane@pixel-format,Crash | |
| 16 | −kms_plane@pixel-format-source-clamping,Crash | |
| 17 | −kms_plane@plane-position-hole,Crash | |
| 18 | −kms_plane@plane-position-hole-dpms,Crash | |
| 19 | −kms_plane_cursor@overlay,Crash | |
| 20 | −kms_plane_cursor@pipe-A-overlay-size-128,Fail | |
| 21 | −kms_plane_cursor@pipe-A-overlay-size-256,Fail | |
| 22 | −kms_plane_cursor@pipe-A-overlay-size-64,Fail | |
| 23 | −kms_plane_cursor@pipe-A-primary-size-128,Fail | |
| 24 | −kms_plane_cursor@pipe-A-primary-size-256,Fail | |
| 25 | −kms_plane_cursor@pipe-A-primary-size-64,Fail | |
| 26 | −kms_plane_cursor@pipe-A-viewport-size-128,Fail | |
| 27 | −kms_plane_cursor@pipe-A-viewport-size-256,Fail | |
| 28 | −kms_plane_cursor@pipe-A-viewport-size-64,Fail | |
| 29 | −kms_plane_cursor@pipe-B-overlay-size-128,Fail | |
| 30 | −kms_plane_cursor@pipe-B-overlay-size-256,Fail | |
| 31 | −kms_plane_cursor@pipe-B-overlay-size-64,Fail | |
| 32 | −kms_plane_cursor@pipe-B-primary-size-128,Fail | |
| 33 | −kms_plane_cursor@pipe-B-primary-size-256,Fail | |
| 34 | −kms_plane_cursor@pipe-B-primary-size-64,Fail | |
| 35 | −kms_plane_cursor@pipe-B-viewport-size-128,Fail | |
| 36 | −kms_plane_cursor@pipe-B-viewport-size-256,Fail | |
| 37 | −kms_plane_cursor@pipe-B-viewport-size-64,Fail | |
| 38 | −kms_plane_cursor@primary,Crash | |
| 39 | −kms_plane_cursor@viewport,Crash | |
| 40 | −kms_plane_lowres@tiling-none,Fail | |
| 41 | −kms_plane_scaling@downscale-with-modifier-factor-0-25,Fail | |
| 42 | −kms_plane_scaling@downscale-with-rotation-factor-0-25,Fail | |
| 43 | −kms_plane_scaling@upscale-with-modifier-20x20,Fail | |
| 44 | −kms_plane_scaling@upscale-with-modifier-factor-0-25,Fail | |
| 45 | −kms_plane_scaling@upscale-with-pixel-format-20x20,Fail | |
| 46 | −kms_plane_scaling@upscale-with-pixel-format-factor-0-25,Fail | |
| 47 | −kms_plane_scaling@upscale-with-rotation-20x20,Fail | |
| 48 | −kms_prime@basic-crc,Fail | |
| 49 | −kms_properties@connector-properties-atomic,Crash | |
| 50 | −kms_properties@connector-properties-legacy,Crash | |
| 51 | −kms_properties@get_properties-sanity-atomic,Crash | |
| 52 | −kms_properties@get_properties-sanity-non-atomic,Crash | |
| 53 | −kms_rmfb@close-fd,Crash | |
| 54 | −kms_setmode@invalid-clone-single-crtc,Crash | |
| 1 | +dumb_buffer@create-clear,Crash | |
| 2 | +dumb_buffer@create-valid-dumb,Crash | |
| 3 | +dumb_buffer@invalid-bpp,Crash | |
| 4 | +dumb_buffer@map-invalid-size,Crash | |
| 5 | +dumb_buffer@map-uaf,Crash | |
| 6 | +dumb_buffer@map-valid,Crash | |
| 7 | +panfrost_prime@gem-prime-import,Crash | |
| 8 | +tools_test@tools_test,Crash | |
| @@ -49,4 +49,23 @@ kms_plane_lowres@pipe-F-tiling-y · 48 unmodified lines | ||
| 49 | 49 | kms_cursor_crc.* |
| 50 | 50 | |
| 51 | 51 | # Machine is hanging in this test, so skip it |
| 52 | −kms_pipe_crc_basic@disable-crc-after-crtc | |
| 52 | +kms_pipe_crc_basic@disable-crc-after-crtc | |
| 53 | + | |
| 54 | +# Skip driver specific tests | |
| 55 | +^amdgpu.* | |
| 56 | +msm_.* | |
| 57 | +nouveau_.* | |
| 58 | +^v3d.* | |
| 59 | +^vc4.* | |
| 60 | +^vmwgfx* | |
| 61 | + | |
| 62 | +# Skip intel specific tests | |
| 63 | +gem_.* | |
| 64 | +i915_.* | |
| 65 | + | |
| 66 | +# Panfrost is not a KMS driver, so skip the KMS tests | |
| 67 | +kms_.* | |
| 68 | + | |
| 69 | +# Currently fails and causes coverage loss for other tests | |
| 70 | +# since core_getversion also fails. | |
| 71 | +core_hotunplug.* | |
| @@ -1,75 +1,8 @@ | ||
| 1 | −kms_color@gamma,Fail | |
| 2 | −kms_color@legacy-gamma,Fail | |
| 3 | −kms_color@pipe-A-legacy-gamma,Fail | |
| 4 | −kms_color@pipe-B-legacy-gamma,Fail | |
| 5 | −kms_cursor_crc@cursor-alpha-opaque,Fail | |
| 6 | −kms_cursor_crc@cursor-alpha-transparent,Fail | |
| 7 | −kms_cursor_crc@cursor-dpms,Fail | |
| 8 | −kms_cursor_crc@cursor-offscreen-32x10,Fail | |
| 9 | −kms_cursor_crc@cursor-offscreen-32x32,Fail | |
| 10 | −kms_cursor_crc@cursor-offscreen-64x64,Fail | |
| 11 | −kms_cursor_crc@cursor-onscreen-32x10,Fail | |
| 12 | −kms_cursor_crc@cursor-onscreen-32x32,Fail | |
| 13 | −kms_cursor_crc@cursor-onscreen-64x21,Fail | |
| 14 | −kms_cursor_crc@cursor-onscreen-64x64,Fail | |
| 15 | −kms_cursor_crc@cursor-random-32x10,Fail | |
| 16 | −kms_cursor_crc@cursor-random-32x32,Fail | |
| 17 | −kms_cursor_crc@cursor-random-64x21,Fail | |
| 18 | −kms_cursor_crc@cursor-random-64x64,Fail | |
| 19 | −kms_cursor_crc@cursor-rapid-movement-32x32,Fail | |
| 20 | −kms_cursor_crc@cursor-rapid-movement-64x21,Fail | |
| 21 | −kms_cursor_crc@cursor-rapid-movement-64x64,Fail | |
| 22 | −kms_cursor_crc@cursor-size-change,Fail | |
| 23 | −kms_cursor_crc@cursor-sliding-32x10,Fail | |
| 24 | −kms_cursor_crc@cursor-sliding-32x32,Fail | |
| 25 | −kms_cursor_crc@cursor-sliding-64x21,Fail | |
| 26 | −kms_cursor_crc@cursor-sliding-64x64,Fail | |
| 27 | −kms_flip@basic-flip-vs-wf_vblank,Fail | |
| 28 | −kms_flip@blocking-wf_vblank,Fail | |
| 29 | −kms_flip@dpms-vs-vblank-race,Fail | |
| 30 | −kms_flip@flip-vs-absolute-wf_vblank,Fail | |
| 31 | −kms_flip@flip-vs-absolute-wf_vblank-interruptible,Fail | |
| 32 | −kms_flip@flip-vs-blocking-wf-vblank,Fail | |
| 33 | −kms_flip@flip-vs-modeset-vs-hang,Fail | |
| 34 | −kms_flip@flip-vs-panning,Fail | |
| 35 | −kms_flip@flip-vs-panning-interruptible,Fail | |
| 36 | −kms_flip@flip-vs-panning-vs-hang,Fail | |
| 37 | −kms_flip@modeset-vs-vblank-race,Fail | |
| 38 | −kms_flip@plain-flip-fb-recreate,Fail | |
| 39 | −kms_flip@plain-flip-fb-recreate-interruptible,Fail | |
| 40 | −kms_flip@plain-flip-ts-check,Fail | |
| 41 | −kms_flip@plain-flip-ts-check-interruptible,Fail | |
| 42 | −kms_flip@wf_vblank-ts-check,Fail | |
| 43 | −kms_flip@wf_vblank-ts-check-interruptible,Fail | |
| 44 | −kms_invalid_mode@int-max-clock,Fail | |
| 45 | −kms_pipe_crc_basic@compare-crc-sanitycheck-nv12,Fail | |
| 46 | −kms_pipe_crc_basic@compare-crc-sanitycheck-xr24,Fail | |
| 47 | −kms_pipe_crc_basic@disable-crc-after-crtc,Fail | |
| 48 | −kms_pipe_crc_basic@nonblocking-crc,Fail | |
| 49 | −kms_pipe_crc_basic@nonblocking-crc-frame-sequence,Fail | |
| 50 | −kms_pipe_crc_basic@read-crc,Fail | |
| 51 | −kms_pipe_crc_basic@read-crc-frame-sequence,Fail | |
| 52 | −kms_plane@pixel-format,Fail | |
| 53 | −kms_plane@pixel-format-source-clamping,Fail | |
| 54 | −kms_plane@plane-panning-bottom-right,Fail | |
| 55 | −kms_plane@plane-panning-top-left,Fail | |
| 56 | −kms_plane@plane-position-covered,Fail | |
| 57 | −kms_plane@plane-position-hole,Fail | |
| 58 | −kms_plane@plane-position-hole-dpms,Fail | |
| 59 | −kms_plane_cursor@overlay,Fail | |
| 60 | −kms_plane_cursor@pipe-B-overlay-size-128,Fail | |
| 61 | −kms_plane_cursor@pipe-B-overlay-size-256,Fail | |
| 62 | −kms_plane_cursor@pipe-B-overlay-size-64,Fail | |
| 63 | −kms_plane_cursor@pipe-B-primary-size-128,Fail | |
| 64 | −kms_plane_cursor@pipe-B-primary-size-256,Fail | |
| 65 | −kms_plane_cursor@pipe-B-primary-size-64,Fail | |
| 66 | −kms_plane_cursor@pipe-B-viewport-size-128,Fail | |
| 67 | −kms_plane_cursor@pipe-B-viewport-size-256,Fail | |
| 68 | −kms_plane_cursor@pipe-B-viewport-size-64,Fail | |
| 69 | −kms_plane_cursor@primary,Fail | |
| 70 | −kms_plane_cursor@viewport,Fail | |
| 71 | −kms_plane_multiple@atomic-pipe-B-tiling-none,Fail | |
| 72 | −kms_plane_multiple@tiling-none,Fail | |
| 73 | −kms_prime@basic-crc,Fail | |
| 74 | −kms_rmfb@close-fd,Fail | |
| 75 | −kms_universal_plane@universal-plane-pipe-B-functional,Fail | |
| 1 | +dumb_buffer@create-clear,Fail | |
| 2 | +dumb_buffer@create-valid-dumb,Fail | |
| 3 | +dumb_buffer@invalid-bpp,Fail | |
| 4 | +dumb_buffer@map-invalid-size,Fail | |
| 5 | +dumb_buffer@map-uaf,Fail | |
| 6 | +dumb_buffer@map-valid,Fail | |
| 7 | +panfrost_prime@gem-prime-import,Fail | |
| 8 | +tools_test@tools_test,Fail | |
| @@ -1,7 +1,6 @@ | ||
| 1 | −kms_bw@linear-tiling-2-displays-1920x1080p | |
| 2 | −kms_cursor_crc@cursor-offscreen-64x21 | |
| 3 | −kms_flip@dpms-vs-vblank-race-interruptible | |
| 4 | −kms_flip@flip-vs-wf_vblank-interruptible | |
| 5 | −kms_plane_cursor@overlay | |
| 6 | −kms_plane_cursor@primary | |
| 7 | −kms_plane_cursor@viewport | |
| 1 | +# Board Name: rk3399-gru-kevin | |
| 2 | +# Bug Report: https://lore.kernel.org/dri-devel/5cc34a8b-c1fa-4744-9031-2d33ecf41011@collabora.com/T/#u | |
| 3 | +# IGT Version: 1.28-g0df7b9b97 | |
| 4 | +# Linux Version: 6.9.0-rc7 | |
| 5 | +# Failure Rate: 50 | |
| 6 | +panfrost_submit@pan-unhandled-pagefault | |
| @@ -3,3 +3,22 @@ · 2 unmodified lines | ||
| 3 | 3 | |
| 4 | 4 | # Too unstable, machine ends up hanging after lots of Oopses |
| 5 | 5 | kms_cursor_legacy.* |
| 6 | + | |
| 7 | +# Skip driver specific tests | |
| 8 | +^amdgpu.* | |
| 9 | +msm_.* | |
| 10 | +nouveau_.* | |
| 11 | +^v3d.* | |
| 12 | +^vc4.* | |
| 13 | +^vmwgfx* | |
| 14 | + | |
| 15 | +# Skip intel specific tests | |
| 16 | +gem_.* | |
| 17 | +i915_.* | |
| 18 | + | |
| 19 | +# Panfrost is not a KMS driver, so skip the KMS tests | |
| 20 | +kms_.* | |
| 21 | + | |
| 22 | +# Currently fails and causes coverage loss for other tests | |
| 23 | +# since core_getversion also fails. | |
| 24 | +core_hotunplug.* | |
| @@ -93,10 +93,10 @@ def add_unit_test_or_update_result_to_fails_if_present(fails_txt, unit_test, fai · 92 unmodified lines | ||
| 93 | 93 | def split_unit_test_from_collate(xfails): |
| 94 | 94 | for job_name in xfails.keys(): |
| 95 | 95 | for job_id in xfails[job_name].copy().keys(): |
| 96 | − if "not found" in xfails[job_name][job_id]: | |
| 96 | + if "not found" in xfails[job_name][job_id].content_as_str: | |
| 97 | 97 | del xfails[job_name][job_id] |
| 98 | 98 | continue |
| 99 | − xfails[job_name][job_id] = xfails[job_name][job_id].strip().split("\n") | |
| 99 | + xfails[job_name][job_id] = xfails[job_name][job_id].content_as_str.splitlines() | |
| 100 | 100 | |
| 101 | 101 | |
| 102 | 102 | def get_xfails_from_pipeline_url(pipeline_url): |
| @@ -1,33 +1,72 @@ | ||
| 1 | −kms_addfb_basic@addfb25-bad-modifier,Fail | |
| 2 | 1 | kms_addfb_basic@bad-pitch-65536,Fail |
| 3 | 2 | kms_addfb_basic@bo-too-small,Fail |
| 4 | 3 | kms_addfb_basic@size-max,Fail |
| 5 | 4 | kms_addfb_basic@too-high,Fail |
| 6 | 5 | kms_atomic_transition@plane-primary-toggle-with-vblank-wait,Fail |
| 7 | 6 | kms_bw@linear-tiling-1-displays-1920x1080p,Fail |
| 7 | +kms_bw@linear-tiling-1-displays-2160x1440p,Fail | |
| 8 | 8 | kms_bw@linear-tiling-1-displays-2560x1440p,Fail |
| 9 | 9 | kms_bw@linear-tiling-1-displays-3840x2160p,Fail |
| 10 | +kms_bw@linear-tiling-10-displays-1920x1080p,Fail | |
| 11 | +kms_bw@linear-tiling-10-displays-2160x1440p,Fail | |
| 12 | +kms_bw@linear-tiling-10-displays-2560x1440p,Fail | |
| 13 | +kms_bw@linear-tiling-10-displays-3840x2160p,Fail | |
| 14 | +kms_bw@linear-tiling-11-displays-1920x1080p,Fail | |
| 15 | +kms_bw@linear-tiling-11-displays-2160x1440p,Fail | |
| 16 | +kms_bw@linear-tiling-11-displays-2560x1440p,Fail | |
| 17 | +kms_bw@linear-tiling-11-displays-3840x2160p,Fail | |
| 18 | +kms_bw@linear-tiling-12-displays-1920x1080p,Fail | |
| 19 | +kms_bw@linear-tiling-12-displays-2160x1440p,Fail | |
| 20 | +kms_bw@linear-tiling-12-displays-2560x1440p,Fail | |
| 21 | +kms_bw@linear-tiling-12-displays-3840x2160p,Fail | |
| 22 | +kms_bw@linear-tiling-13-displays-1920x1080p,Fail | |
| 23 | +kms_bw@linear-tiling-13-displays-2160x1440p,Fail | |
| 24 | +kms_bw@linear-tiling-13-displays-2560x1440p,Fail | |
| 25 | +kms_bw@linear-tiling-13-displays-3840x2160p,Fail | |
| 26 | +kms_bw@linear-tiling-14-displays-1920x1080p,Fail | |
| 27 | +kms_bw@linear-tiling-14-displays-2160x1440p,Fail | |
| 28 | +kms_bw@linear-tiling-14-displays-2560x1440p,Fail | |
| 29 | +kms_bw@linear-tiling-14-displays-3840x2160p,Fail | |
| 30 | +kms_bw@linear-tiling-15-displays-1920x1080p,Fail | |
| 31 | +kms_bw@linear-tiling-15-displays-2160x1440p,Fail | |
| 32 | +kms_bw@linear-tiling-15-displays-2560x1440p,Fail | |
| 33 | +kms_bw@linear-tiling-15-displays-3840x2160p,Fail | |
| 34 | +kms_bw@linear-tiling-16-displays-1920x1080p,Fail | |
| 35 | +kms_bw@linear-tiling-16-displays-2160x1440p,Fail | |
| 36 | +kms_bw@linear-tiling-16-displays-2560x1440p,Fail | |
| 37 | +kms_bw@linear-tiling-16-displays-3840x2160p,Fail | |
| 10 | 38 | kms_bw@linear-tiling-2-displays-1920x1080p,Fail |
| 39 | +kms_bw@linear-tiling-2-displays-2160x1440p,Fail | |
| 11 | 40 | kms_bw@linear-tiling-2-displays-2560x1440p,Fail |
| 12 | 41 | kms_bw@linear-tiling-2-displays-3840x2160p,Fail |
| 13 | 42 | kms_bw@linear-tiling-3-displays-1920x1080p,Fail |
| 43 | +kms_bw@linear-tiling-3-displays-2160x1440p,Fail | |
| 14 | 44 | kms_bw@linear-tiling-3-displays-2560x1440p,Fail |
| 15 | 45 | kms_bw@linear-tiling-3-displays-3840x2160p,Fail |
| 16 | 46 | kms_bw@linear-tiling-4-displays-1920x1080p,Fail |
| 47 | +kms_bw@linear-tiling-4-displays-2160x1440p,Fail | |
| 17 | 48 | kms_bw@linear-tiling-4-displays-2560x1440p,Fail |
| 18 | 49 | kms_bw@linear-tiling-4-displays-3840x2160p,Fail |
| 19 | 50 | kms_bw@linear-tiling-5-displays-1920x1080p,Fail |
| 51 | +kms_bw@linear-tiling-5-displays-2160x1440p,Fail | |
| 20 | 52 | kms_bw@linear-tiling-5-displays-2560x1440p,Fail |
| 21 | 53 | kms_bw@linear-tiling-5-displays-3840x2160p,Fail |
| 22 | 54 | kms_bw@linear-tiling-6-displays-1920x1080p,Fail |
| 55 | +kms_bw@linear-tiling-6-displays-2160x1440p,Fail | |
| 23 | 56 | kms_bw@linear-tiling-6-displays-2560x1440p,Fail |
| 24 | 57 | kms_bw@linear-tiling-6-displays-3840x2160p,Fail |
| 25 | 58 | kms_bw@linear-tiling-7-displays-1920x1080p,Fail |
| 59 | +kms_bw@linear-tiling-7-displays-2160x1440p,Fail | |
| 26 | 60 | kms_bw@linear-tiling-7-displays-2560x1440p,Fail |
| 27 | 61 | kms_bw@linear-tiling-7-displays-3840x2160p,Fail |
| 28 | 62 | kms_bw@linear-tiling-8-displays-1920x1080p,Fail |
| 63 | +kms_bw@linear-tiling-8-displays-2160x1440p,Fail | |
| 29 | 64 | kms_bw@linear-tiling-8-displays-2560x1440p,Fail |
| 30 | 65 | kms_bw@linear-tiling-8-displays-3840x2160p,Fail |
| 66 | +kms_bw@linear-tiling-9-displays-1920x1080p,Fail | |
| 67 | +kms_bw@linear-tiling-9-displays-2160x1440p,Fail | |
| 68 | +kms_bw@linear-tiling-9-displays-2560x1440p,Fail | |
| 69 | +kms_bw@linear-tiling-9-displays-3840x2160p,Fail | |
| 31 | 70 | kms_flip@absolute-wf_vblank,Fail |
| 32 | 71 | kms_flip@absolute-wf_vblank-interruptible,Fail |
| 33 | 72 | kms_flip@basic-flip-vs-wf_vblank,Fail |
| @@ -54,31 +93,34 @@ kms_flip@plain-flip-ts-check-interruptible,Fail · 20 unmodified lines | ||
| 54 | 93 | kms_flip@wf_vblank-ts-check,Fail |
| 55 | 94 | kms_flip@wf_vblank-ts-check-interruptible,Fail |
| 56 | 95 | kms_invalid_mode@int-max-clock,Fail |
| 57 | −kms_plane_scaling@downscale-with-modifier-factor-0-25,Fail | |
| 58 | −kms_plane_scaling@downscale-with-rotation-factor-0-25,Fail | |
| 59 | −kms_plane_scaling@planes-upscale-20x20,Fail | |
| 60 | −kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-25,Fail | |
| 61 | −kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-5,Fail | |
| 62 | −kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-75,Fail | |
| 63 | −kms_plane_scaling@upscale-with-modifier-20x20,Fail | |
| 64 | −kms_plane_scaling@upscale-with-modifier-factor-0-25,Fail | |
| 65 | −kms_plane_scaling@upscale-with-pixel-format-20x20,Fail | |
| 66 | −kms_plane_scaling@upscale-with-pixel-format-factor-0-25,Fail | |
| 67 | −kms_plane_scaling@upscale-with-rotation-20x20,Fail | |
| 68 | −kms_selftest@drm_format,Timeout | |
| 69 | −kms_selftest@drm_format_helper,Timeout | |
| 96 | +kms_lease@cursor-implicit-plane,Fail | |
| 97 | +kms_lease@lease-uevent,Fail | |
| 98 | +kms_lease@page-flip-implicit-plane,Fail | |
| 99 | +kms_lease@setcrtc-implicit-plane,Fail | |
| 100 | +kms_lease@simple-lease,Fail | |
| 101 | +kms_sequence@get-busy,Fail | |
| 102 | +kms_sequence@get-forked,Fail | |
| 103 | +kms_sequence@get-forked-busy,Fail | |
| 104 | +kms_sequence@get-idle,Fail | |
| 105 | +kms_sequence@queue-busy,Fail | |
| 106 | +kms_sequence@queue-idle,Fail | |
| 70 | 107 | kms_setmode@basic,Fail |
| 108 | +kms_vblank@accuracy-idle,Fail | |
| 71 | 109 | kms_vblank@crtc-id,Fail |
| 72 | 110 | kms_vblank@invalid,Fail |
| 73 | −kms_vblank@pipe-A-accuracy-idle,Fail | |
| 74 | −kms_vblank@pipe-A-query-busy,Fail | |
| 75 | −kms_vblank@pipe-A-query-forked,Fail | |
| 76 | −kms_vblank@pipe-A-query-forked-busy,Fail | |
| 77 | −kms_vblank@pipe-A-query-idle,Fail | |
| 78 | −kms_vblank@pipe-A-ts-continuation-idle,Fail | |
| 79 | −kms_vblank@pipe-A-ts-continuation-modeset,Fail | |
| 80 | −kms_vblank@pipe-A-ts-continuation-suspend,Fail | |
| 81 | −kms_vblank@pipe-A-wait-busy,Fail | |
| 82 | −kms_vblank@pipe-A-wait-forked,Fail | |
| 83 | −kms_vblank@pipe-A-wait-forked-busy,Fail | |
| 84 | −kms_vblank@pipe-A-wait-idle,Fail | |
| 111 | +kms_vblank@query-busy,Fail | |
| 112 | +kms_vblank@query-forked,Fail | |
| 113 | +kms_vblank@query-forked-busy,Fail | |
| 114 | +kms_vblank@query-idle,Fail | |
| 115 | +kms_vblank@ts-continuation-dpms-rpm,Fail | |
| 116 | +kms_vblank@ts-continuation-dpms-suspend,Fail | |
| 117 | +kms_vblank@ts-continuation-idle,Fail | |
| 118 | +kms_vblank@ts-continuation-modeset,Fail | |
| 119 | +kms_vblank@ts-continuation-modeset-rpm,Fail | |
| 120 | +kms_vblank@ts-continuation-suspend,Fail | |
| 121 | +kms_vblank@wait-busy,Fail | |
| 122 | +kms_vblank@wait-forked,Fail | |
| 123 | +kms_vblank@wait-forked-busy,Fail | |
| 124 | +kms_vblank@wait-idle,Fail | |
| 125 | +perf@i915-ref-count,Fail | |
| 126 | +tools_test@tools_test,Fail | |
| @@ -3,4 +3,22 @@ · 2 unmodified lines | ||
| 3 | 3 | kms_cursor_legacy.* |
| 4 | 4 | |
| 5 | 5 | # Job just hangs without any output |
| 6 | −kms_flip@flip-vs-suspend.* | |
| 6 | +kms_flip@flip-vs-suspend.* | |
| 7 | + | |
| 8 | +# Skip driver specific tests | |
| 9 | +^amdgpu.* | |
| 10 | +msm_.* | |
| 11 | +nouveau_.* | |
| 12 | +panfrost_.* | |
| 13 | +^v3d.* | |
| 14 | +^vc4.* | |
| 15 | +^vmwgfx* | |
| 16 | + | |
| 17 | +# Skip intel specific tests | |
| 18 | +gem_.* | |
| 19 | +i915_.* | |
| 20 | +xe_.* | |
| 21 | + | |
| 22 | +# Currently fails and causes coverage loss for other tests | |
| 23 | +# since core_getversion also fails. | |
| 24 | +core_hotunplug.* | |
| @@ -0,0 +1,57 @@ | ||
| 1 | +core_hotunplug@hotrebind,Fail | |
| 2 | +core_hotunplug@hotrebind-lateclose,Fail | |
| 3 | +core_hotunplug@hotreplug,Fail | |
| 4 | +core_hotunplug@hotreplug-lateclose,Fail | |
| 5 | +core_hotunplug@hotunbind-rebind,Fail | |
| 6 | +core_hotunplug@hotunplug-rescan,Fail | |
| 7 | +core_hotunplug@unbind-rebind,Fail | |
| 8 | +core_hotunplug@unplug-rescan,Fail | |
| 9 | +device_reset@cold-reset-bound,Fail | |
| 10 | +device_reset@reset-bound,Fail | |
| 11 | +device_reset@unbind-cold-reset-rebind,Fail | |
| 12 | +device_reset@unbind-reset-rebind,Fail | |
| 13 | +dumb_buffer@invalid-bpp,Fail | |
| 14 | +kms_content_protection@atomic,Crash | |
| 15 | +kms_content_protection@atomic-dpms,Crash | |
| 16 | +kms_content_protection@content-type-change,Crash | |
| 17 | +kms_content_protection@lic-type-0,Crash | |
| 18 | +kms_content_protection@lic-type-1,Crash | |
| 19 | +kms_content_protection@srm,Crash | |
| 20 | +kms_content_protection@type1,Crash | |
| 21 | +kms_content_protection@uevent,Crash | |
| 22 | +kms_cursor_crc@cursor-rapid-movement-128x128,Fail | |
| 23 | +kms_cursor_crc@cursor-rapid-movement-128x42,Fail | |
| 24 | +kms_cursor_crc@cursor-rapid-movement-256x256,Fail | |
| 25 | +kms_cursor_crc@cursor-rapid-movement-256x85,Fail | |
| 26 | +kms_cursor_crc@cursor-rapid-movement-32x10,Fail | |
| 27 | +kms_cursor_crc@cursor-rapid-movement-32x32,Fail | |
| 28 | +kms_cursor_crc@cursor-rapid-movement-512x170,Fail | |
| 29 | +kms_cursor_crc@cursor-rapid-movement-512x512,Fail | |
| 30 | +kms_cursor_crc@cursor-rapid-movement-64x21,Fail | |
| 31 | +kms_cursor_crc@cursor-rapid-movement-64x64,Fail | |
| 32 | +kms_cursor_legacy@basic-flip-before-cursor-atomic,Fail | |
| 33 | +kms_cursor_legacy@basic-flip-before-cursor-legacy,Fail | |
| 34 | +kms_cursor_legacy@cursor-vs-flip-atomic,Fail | |
| 35 | +kms_cursor_legacy@cursor-vs-flip-legacy,Fail | |
| 36 | +kms_cursor_legacy@cursor-vs-flip-toggle,Fail | |
| 37 | +kms_cursor_legacy@cursor-vs-flip-varying-size,Fail | |
| 38 | +kms_cursor_legacy@flip-vs-cursor-atomic,Fail | |
| 39 | +kms_cursor_legacy@flip-vs-cursor-crc-atomic,Fail | |
| 40 | +kms_cursor_legacy@flip-vs-cursor-crc-legacy,Fail | |
| 41 | +kms_cursor_legacy@flip-vs-cursor-legacy,Fail | |
| 42 | +kms_flip@flip-vs-modeset-vs-hang,Fail | |
| 43 | +kms_flip@flip-vs-panning-vs-hang,Fail | |
| 44 | +kms_flip@flip-vs-suspend,Timeout | |
| 45 | +kms_flip@flip-vs-suspend-interruptible,Timeout | |
| 46 | +kms_flip@plain-flip-fb-recreate,Fail | |
| 47 | +kms_lease@lease-uevent,Fail | |
| 48 | +kms_pipe_crc_basic@nonblocking-crc,Fail | |
| 49 | +kms_pipe_crc_basic@nonblocking-crc-frame-sequence,Fail | |
| 50 | +kms_writeback@writeback-check-output,Fail | |
| 51 | +kms_writeback@writeback-check-output-XRGB2101010,Fail | |
| 52 | +kms_writeback@writeback-fb-id,Fail | |
| 53 | +kms_writeback@writeback-fb-id-XRGB2101010,Fail | |
| 54 | +kms_writeback@writeback-invalid-parameters,Fail | |
| 55 | +kms_writeback@writeback-pixel-formats,Fail | |
| 56 | +perf@i915-ref-count,Fail | |
| 57 | +tools_test@tools_test,Fail | |
| @@ -0,0 +1,69 @@ | ||
| 1 | +# Board Name: vkms | |
| 2 | +# Bug Report: https://lore.kernel.org/dri-devel/61ed26af-062c-443c-9df2-d1ee319f3fb0@collabora.com/T/#u | |
| 3 | +# Failure Rate: 50 | |
| 4 | +# IGT Version: 1.28-g0df7b9b97 | |
| 5 | +# Linux Version: 6.9.0-rc7 | |
| 6 | +kms_cursor_legacy@long-nonblocking-modeset-vs-cursor-atomic | |
| 7 | + | |
| 8 | +# Board Name: vkms | |
| 9 | +# Bug Report: https://lore.kernel.org/dri-devel/61ed26af-062c-443c-9df2-d1ee319f3fb0@collabora.com/T/#u | |
| 10 | +# Failure Rate: 50 | |
| 11 | +# IGT Version: 1.28-g0df7b9b97 | |
| 12 | +# Linux Version: 6.9.0-rc7 | |
| 13 | +kms_flip@basic-flip-vs-wf_vblank | |
| 14 | + | |
| 15 | +# Board Name: vkms | |
| 16 | +# Bug Report: https://lore.kernel.org/dri-devel/61ed26af-062c-443c-9df2-d1ee319f3fb0@collabora.com/T/#u | |
| 17 | +# Failure Rate: 50 | |
| 18 | +# IGT Version: 1.28-g0df7b9b97 | |
| 19 | +# Linux Version: 6.9.0-rc7 | |
| 20 | +kms_flip@flip-vs-expired-vblank-interruptible | |
| 21 | + | |
| 22 | +# Board Name: vkms | |
| 23 | +# Bug Report: https://lore.kernel.org/dri-devel/61ed26af-062c-443c-9df2-d1ee319f3fb0@collabora.com/T/#u | |
| 24 | +# Failure Rate: 50 | |
| 25 | +# IGT Version: 1.28-g0df7b9b97 | |
| 26 | +# Linux Version: 6.9.0-rc7 | |
| 27 | +kms_flip@flip-vs-wf_vblank-interruptible | |
| 28 | + | |
| 29 | +# Board Name: vkms | |
| 30 | +# Bug Report: https://lore.kernel.org/dri-devel/61ed26af-062c-443c-9df2-d1ee319f3fb0@collabora.com/T/#u | |
| 31 | +# Failure Rate: 50 | |
| 32 | +# IGT Version: 1.28-g0df7b9b97 | |
| 33 | +# Linux Version: 6.9.0-rc7 | |
| 34 | +kms_flip@plain-flip-fb-recreate-interruptible | |
| 35 | + | |
| 36 | +# Board Name: vkms | |
| 37 | +# Bug Report: https://lore.kernel.org/dri-devel/61ed26af-062c-443c-9df2-d1ee319f3fb0@collabora.com/T/#u | |
| 38 | +# Failure Rate: 50 | |
| 39 | +# IGT Version: 1.28-g0df7b9b97 | |
| 40 | +# Linux Version: 6.9.0-rc7 | |
| 41 | +kms_flip@plain-flip-ts-check | |
| 42 | + | |
| 43 | +# Board Name: vkms | |
| 44 | +# Bug Report: https://lore.kernel.org/dri-devel/61ed26af-062c-443c-9df2-d1ee319f3fb0@collabora.com/T/#u | |
| 45 | +# Failure Rate: 50 | |
| 46 | +# IGT Version: 1.28-g0df7b9b97 | |
| 47 | +# Linux Version: 6.9.0-rc7 | |
| 48 | +kms_flip@plain-flip-ts-check-interruptible | |
| 49 | + | |
| 50 | +# Board Name: vkms | |
| 51 | +# Bug Report: https://lore.kernel.org/dri-devel/61ed26af-062c-443c-9df2-d1ee319f3fb0@collabora.com/T/#u | |
| 52 | +# Failure Rate: 50 | |
| 53 | +# IGT Version: 1.28-g0df7b9b97 | |
| 54 | +# Linux Version: 6.9.0-rc7 | |
| 55 | +kms_flip@flip-vs-absolute-wf_vblank | |
| 56 | + | |
| 57 | +# Board Name: vkms | |
| 58 | +# Bug Report: https://lore.kernel.org/dri-devel/61ed26af-062c-443c-9df2-d1ee319f3fb0@collabora.com/T/#u | |
| 59 | +# Failure Rate: 50 | |
| 60 | +# IGT Version: 1.28-g0df7b9b97 | |
| 61 | +# Linux Version: 6.9.0-rc7 | |
| 62 | +kms_flip@flip-vs-absolute-wf_vblank-interruptible | |
| 63 | + | |
| 64 | +# Board Name: vkms | |
| 65 | +# Bug Report: https://lore.kernel.org/dri-devel/61ed26af-062c-443c-9df2-d1ee319f3fb0@collabora.com/T/#u | |
| 66 | +# Failure Rate: 50 | |
| 67 | +# IGT Version: 1.28-g0df7b9b97 | |
| 68 | +# Linux Version: 6.9.0-rc7 | |
| 69 | +kms_flip@flip-vs-blocking-wf-vblank | |
| @@ -0,0 +1,119 @@ | ||
| 1 | +# keeps printing vkms_vblank_simulate: vblank timer overrun and never ends | |
| 2 | +kms_invalid_mode@int-max-clock | |
| 3 | + | |
| 4 | +# Kernel panic | |
| 5 | +kms_cursor_crc@cursor-rapid-movement-32x10 | |
| 6 | +# Oops: 0000 [#1] PREEMPT SMP NOPTI | |
| 7 | +# CPU: 0 PID: 2635 Comm: kworker/u8:13 Not tainted 6.9.0-rc7-g40935263a1fd #1 | |
| 8 | +# Hardware name: ChromiumOS crosvm, BIOS 0 | |
| 9 | +# Workqueue: vkms_composer vkms_composer_worker [vkms] | |
| 10 | +# RIP: 0010:compose_active_planes+0x1c7/0x4e0 [vkms] | |
| 11 | +# Code: c9 0f 84 6a 01 00 00 8b 42 30 2b 42 28 41 39 c5 0f 8c 6f 01 00 00 49 83 c7 01 49 39 df 74 3b 4b 8b 34 fc 48 8b 96 48 01 00 00 <8b> 42 78 89 c1 83 e1 0a a8 20 74 b1 45 89 f5 41 f7 d5 44 03 6a 34 | |
| 12 | +# RSP: 0018:ffffbb4700c17d58 EFLAGS: 00010246 | |
| 13 | +# RAX: 0000000000000400 RBX: 0000000000000002 RCX: 0000000000000002 | |
| 14 | +# RDX: 0000000000000000 RSI: ffffa2ad0788c000 RDI: 00000000fff479a8 | |
| 15 | +# RBP: 0000000000000004 R08: 0000000000000000 R09: 0000000000000000 | |
| 16 | +# R10: ffffa2ad0bb14000 R11: 0000000000000000 R12: ffffa2ad03e21700 | |
| 17 | +# R13: 0000000000000003 R14: 0000000000000004 R15: 0000000000000000 | |
| 18 | +# FS: 0000000000000000(0000) GS:ffffa2ad2bc00000(0000) knlGS:0000000000000000 | |
| 19 | +# CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033 | |
| 20 | +# CR2: 0000000000000078 CR3: 000000010bd30000 CR4: 0000000000350ef0 | |
| 21 | +# Call Trace: | |
| 22 | +# <TASK> | |
| 23 | +# ? __die+0x1e/0x60 | |
| 24 | +# ? page_fault_oops+0x17b/0x490 | |
| 25 | +# ? exc_page_fault+0x6d/0x230 | |
| 26 | +# ? asm_exc_page_fault+0x26/0x30 | |
| 27 | +# ? compose_active_planes+0x1c7/0x4e0 [vkms] | |
| 28 | +# ? compose_active_planes+0x2a3/0x4e0 [vkms] | |
| 29 | +# ? srso_return_thunk+0x5/0x5f | |
| 30 | +# vkms_composer_worker+0x205/0x240 [vkms] | |
| 31 | +# process_one_work+0x1f4/0x6b0 | |
| 32 | +# ? lock_is_held_type+0x9e/0x110 | |
| 33 | +# worker_thread+0x17e/0x350 | |
| 34 | +# ? __pfx_worker_thread+0x10/0x10 | |
| 35 | +# kthread+0xce/0x100 | |
| 36 | +# ? __pfx_kthread+0x10/0x10 | |
| 37 | +# ret_from_fork+0x2f/0x50 | |
| 38 | +# ? __pfx_kthread+0x10/0x10 | |
| 39 | +# ret_from_fork_asm+0x1a/0x30 | |
| 40 | +# </TASK> | |
| 41 | +# Modules linked in: vkms | |
| 42 | +# CR2: 0000000000000078 | |
| 43 | +# ---[ end trace 0000000000000000 ]--- | |
| 44 | +# RIP: 0010:compose_active_planes+0x1c7/0x4e0 [vkms] | |
| 45 | +# Code: c9 0f 84 6a 01 00 00 8b 42 30 2b 42 28 41 39 c5 0f 8c 6f 01 00 00 49 83 c7 01 49 39 df 74 3b 4b 8b 34 fc 48 8b 96 48 01 00 00 <8b> 42 78 89 c1 83 e1 0a a8 20 74 b1 45 89 f5 41 f7 d5 44 03 6a 34 | |
| 46 | +# RSP: 0018:ffffbb4700c17d58 EFLAGS: 00010246 | |
| 47 | +# RAX: 0000000000000400 RBX: 0000000000000002 RCX: 0000000000000002 | |
| 48 | +# RDX: 0000000000000000 RSI: ffffa2ad0788c000 RDI: 00000000fff479a8 | |
| 49 | +# RBP: 0000000000000004 R08: 0000000000000000 R09: 0000000000000000 | |
| 50 | +# R10: ffffa2ad0bb14000 R11: 0000000000000000 R12: ffffa2ad03e21700 | |
| 51 | +# R13: 0000000000000003 R14: 0000000000000004 R15: 0000000000000000 | |
| 52 | +# FS: 0000000000000000(0000) GS:ffffa2ad2bc00000(0000) knlGS:0000000000000000 | |
| 53 | +# CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033 | |
| 54 | + | |
| 55 | +kms_cursor_crc@cursor-rapid-movement-256x85 | |
| 56 | +# [drm:drm_crtc_add_crc_entry] *ERROR* Overflow of CRC buffer, userspace reads too slow. | |
| 57 | +# Oops: 0000 [#1] PREEMPT SMP NOPTI | |
| 58 | +# CPU: 1 PID: 10 Comm: kworker/u8:0 Not tainted 6.9.0-rc7-g646381cde463 #1 | |
| 59 | +# Hardware name: ChromiumOS crosvm, BIOS 0 | |
| 60 | +# Workqueue: vkms_composer vkms_composer_worker [vkms] | |
| 61 | +# RIP: 0010:compose_active_planes+0x1c7/0x4e0 [vkms] | |
| 62 | +# Code: c9 0f 84 6a 01 00 00 8b 42 30 2b 42 28 41 39 c5 0f 8c 6f 01 00 00 49 83 c7 01 49 39 df 74 3b 4b 8b 34 fc 48 8b 96 48 01 00 00 <8b> 42 78 89 c1 83 e1 0a a8 20 74 b1 45 89 f5 41 f7 d5 44 03 6a 34 | |
| 63 | +# RSP: 0018:ffffa7e980057d58 EFLAGS: 00010246 | |
| 64 | +# RAX: 0000000000000400 RBX: 0000000000000002 RCX: 0000000000000002 | |
| 65 | +# RDX: 0000000000000000 RSI: ffff977987aa5c00 RDI: 000000001b43a85f | |
| 66 | +# RBP: 0000000000000001 R08: 0000000000000000 R09: 0000000000000000 | |
| 67 | +# R10: ffff977981bf0000 R11: 0000000000000000 R12: ffff977989622590 | |
| 68 | +# R13: 0000000000000000 R14: 0000000000000001 R15: 0000000000000000 | |
| 69 | +# FS: 0000000000000000(0000) GS:ffff9779abd00000(0000) knlGS:0000000000000000 | |
| 70 | +# CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033 | |
| 71 | +# CR2: 0000000000000078 CR3: 0000000109b38000 CR4: 0000000000350ef0 | |
| 72 | +# Call Trace: | |
| 73 | +# <TASK> | |
| 74 | +# ? __die+0x1e/0x60 | |
| 75 | +# ? page_fault_oops+0x17b/0x490 | |
| 76 | +# ? exc_page_fault+0x6d/0x230 | |
| 77 | +# ? asm_exc_page_fault+0x26/0x30 | |
| 78 | +# ? compose_active_planes+0x1c7/0x4e0 [vkms] | |
| 79 | +# ? compose_active_planes+0x2a3/0x4e0 [vkms] | |
| 80 | +# ? srso_return_thunk+0x5/0x5f | |
| 81 | +# vkms_composer_worker+0x205/0x240 [vkms] | |
| 82 | +# process_one_work+0x1f4/0x6b0 | |
| 83 | +# ? lock_is_held_type+0x9e/0x110 | |
| 84 | +# worker_thread+0x17e/0x350 | |
| 85 | +# ? __pfx_worker_thread+0x10/0x10 | |
| 86 | +# kthread+0xce/0x100 | |
| 87 | +# ? __pfx_kthread+0x10/0x10 | |
| 88 | +# ret_from_fork+0x2f/0x50 | |
| 89 | +# ? __pfx_kthread+0x10/0x10 | |
| 90 | +# ret_from_fork_asm+0x1a/0x30 | |
| 91 | +# </TASK> | |
| 92 | +# Modules linked in: vkms | |
| 93 | +# CR2: 0000000000000078 | |
| 94 | +# ---[ end trace 0000000000000000 ]--- | |
| 95 | +# RIP: 0010:compose_active_planes+0x1c7/0x4e0 [vkms] | |
| 96 | +# Code: c9 0f 84 6a 01 00 00 8b 42 30 2b 42 28 41 39 c5 0f 8c 6f 01 00 00 49 83 c7 01 49 39 df 74 3b 4b 8b 34 fc 48 8b 96 48 01 00 00 <8b> 42 78 89 c1 83 e1 0a a8 20 74 b1 45 89 f5 41 f7 d5 44 03 6a 34 | |
| 97 | +# RSP: 0018:ffffa7e980057d58 EFLAGS: 00010246 | |
| 98 | +# RAX: 0000000000000400 RBX: 0000000000000002 RCX: 0000000000000002 | |
| 99 | +# RDX: 0000000000000000 RSI: ffff977987aa5c00 RDI: 000000001b43a85f | |
| 100 | +# RBP: 0000000000000001 R08: 0000000000000000 R09: 0000000000000000 | |
| 101 | +# R10: ffff977981bf0000 R11: 0000000000000000 R12: ffff977989622590 | |
| 102 | +# R13: 0000000000000000 R14: 0000000000000001 R15: 0000000000000000 | |
| 103 | +# FS: 0000000000000000(0000) GS:ffff9779abd00000(0000) knlGS:0000000000000000 | |
| 104 | +# CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033 | |
| 105 | +# CR2: 0000000000000078 CR3: 0000000109b38000 CR4: 0000000000350ef0 | |
| 106 | + | |
| 107 | +# Skip driver specific tests | |
| 108 | +^amdgpu.* | |
| 109 | +msm_.* | |
| 110 | +nouveau_.* | |
| 111 | +panfrost_.* | |
| 112 | +^v3d.* | |
| 113 | +^vc4.* | |
| 114 | +^vmwgfx* | |
| 115 | + | |
| 116 | +# Skip intel specific tests | |
| 117 | +gem_.* | |
| 118 | +i915_.* | |
| 119 | +xe_.* | |
| @@ -70,3 +70,10 @@ config DRM_DISPLAY_HDMI_HELPER · 69 unmodified lines | ||
| 70 | 70 | depends on DRM_DISPLAY_HELPER |
| 71 | 71 | help |
| 72 | 72 | DRM display helpers for HDMI. |
| 73 | + | |
| 74 | +config DRM_DISPLAY_HDMI_STATE_HELPER | |
| 75 | + bool | |
| 76 | + depends on DRM_DISPLAY_HELPER | |
| 77 | + select DRM_DISPLAY_HDMI_HELPER | |
| 78 | + help | |
| 79 | + DRM KMS state helpers for HDMI. | |
| @@ -14,6 +14,8 @@ drm_display_helper-$(CONFIG_DRM_DISPLAY_HDCP_HELPER) += drm_hdcp_helper.o · 13 unmodified lines | ||
| 14 | 14 | drm_display_helper-$(CONFIG_DRM_DISPLAY_HDMI_HELPER) += \ |
| 15 | 15 | drm_hdmi_helper.o \ |
| 16 | 16 | drm_scdc_helper.o |
| 17 | +drm_display_helper-$(CONFIG_DRM_DISPLAY_HDMI_STATE_HELPER) += \ | |
| 18 | + drm_hdmi_state_helper.o | |
| 17 | 19 | drm_display_helper-$(CONFIG_DRM_DISPLAY_DP_AUX_CHARDEV) += drm_dp_aux_dev.o |
| 18 | 20 | drm_display_helper-$(CONFIG_DRM_DISPLAY_DP_AUX_CEC) += drm_dp_cec.o |
| 19 | 21 | |
| @@ -195,3 +195,64 @@ void drm_hdmi_avi_infoframe_content_type(struct hdmi_avi_infoframe *frame, · 194 unmodified lines | ||
| 195 | 195 | frame->itc = conn_state->content_type != DRM_MODE_CONTENT_TYPE_NO_DATA; |
| 196 | 196 | } |
| 197 | 197 | EXPORT_SYMBOL(drm_hdmi_avi_infoframe_content_type); |
| 198 | + | |
| 199 | +/** | |
| 200 | + * drm_hdmi_compute_mode_clock() - Computes the TMDS Character Rate | |
| 201 | + * @mode: Display mode to compute the clock for | |
| 202 | + * @bpc: Bits per character | |
| 203 | + * @fmt: Output Pixel Format used | |
| 204 | + * | |
| 205 | + * Returns the TMDS Character Rate for a given mode, bpc count and output format. | |
| 206 | + * | |
| 207 | + * RETURNS: | |
| 208 | + * The TMDS Character Rate, in Hertz, or 0 on error. | |
| 209 | + */ | |
| 210 | +unsigned long long | |
| 211 | +drm_hdmi_compute_mode_clock(const struct drm_display_mode *mode, | |
| 212 | + unsigned int bpc, enum hdmi_colorspace fmt) | |
| 213 | +{ | |
| 214 | + unsigned long long clock = mode->clock * 1000ULL; | |
| 215 | + unsigned int vic = drm_match_cea_mode(mode); | |
| 216 | + | |
| 217 | + /* | |
| 218 | + * CTA-861-G Spec, section 5.4 - Color Coding and Quantization | |
| 219 | + * mandates that VIC 1 always uses 8 bpc. | |
| 220 | + */ | |
| 221 | + if (vic == 1 && bpc != 8) | |
| 222 | + return 0; | |
| 223 | + | |
| 224 | + if (fmt == HDMI_COLORSPACE_YUV422) { | |
| 225 | + /* | |
| 226 | + * HDMI 1.0 Spec, section 6.5 - Pixel Encoding states that | |
| 227 | + * YUV422 sends 24 bits over three channels, with Cb and Cr | |
| 228 | + * components being sent on odd and even pixels, respectively. | |
| 229 | + * | |
| 230 | + * If fewer than 12 bpc are sent, data are left justified. | |
| 231 | + */ | |
| 232 | + if (bpc > 12) | |
| 233 | + return 0; | |
| 234 | + | |
| 235 | + /* | |
| 236 | + * HDMI 1.0 Spec, section 6.5 - Pixel Encoding | |
| 237 | + * specifies that YUV422 sends two 12-bits components over | |
| 238 | + * three TMDS channels per pixel clock, which is equivalent to | |
| 239 | + * three 8-bits components over three channels used by RGB as | |
| 240 | + * far as the clock rate goes. | |
| 241 | + */ | |
| 242 | + bpc = 8; | |
| 243 | + } | |
| 244 | + | |
| 245 | + /* | |
| 246 | + * HDMI 2.0 Spec, Section 7.1 - YCbCr 4:2:0 Pixel Encoding | |
| 247 | + * specifies that YUV420 encoding is carried at a TMDS Character Rate | |
| 248 | + * equal to half the pixel clock rate. | |
| 249 | + */ | |
| 250 | + if (fmt == HDMI_COLORSPACE_YUV420) | |
| 251 | + clock = clock / 2; | |
| 252 | + | |
| 253 | + if (mode->flags & DRM_MODE_FLAG_DBLCLK) | |
| 254 | + clock = clock * 2; | |
| 255 | + | |
| 256 | + return DIV_ROUND_CLOSEST_ULL(clock * bpc, 8); | |
| 257 | +} | |
| 258 | +EXPORT_SYMBOL(drm_hdmi_compute_mode_clock); | |
| @@ -0,0 +1,752 @@ | ||
| 1 | +// SPDX-License-Identifier: MIT | |
| 2 | + | |
| 3 | +#include <drm/drm_atomic.h> | |
| 4 | +#include <drm/drm_connector.h> | |
| 5 | +#include <drm/drm_edid.h> | |
| 6 | +#include <drm/drm_print.h> | |
| 7 | + | |
| 8 | +#include <drm/display/drm_hdmi_helper.h> | |
| 9 | +#include <drm/display/drm_hdmi_state_helper.h> | |
| 10 | + | |
| 11 | +/** | |
| 12 | + * __drm_atomic_helper_connector_hdmi_reset() - Initializes all HDMI @drm_connector_state resources | |
| 13 | + * @connector: DRM connector | |
| 14 | + * @new_conn_state: connector state to reset | |
| 15 | + * | |
| 16 | + * Initializes all HDMI resources from a @drm_connector_state without | |
| 17 | + * actually allocating it. This is useful for HDMI drivers, in | |
| 18 | + * combination with __drm_atomic_helper_connector_reset() or | |
| 19 | + * drm_atomic_helper_connector_reset(). | |
| 20 | + */ | |
| 21 | +void __drm_atomic_helper_connector_hdmi_reset(struct drm_connector *connector, | |
| 22 | + struct drm_connector_state *new_conn_state) | |
| 23 | +{ | |
| 24 | + unsigned int max_bpc = connector->max_bpc; | |
| 25 | + | |
| 26 | + new_conn_state->max_bpc = max_bpc; | |
| 27 | + new_conn_state->max_requested_bpc = max_bpc; | |
| 28 | + new_conn_state->hdmi.broadcast_rgb = DRM_HDMI_BROADCAST_RGB_AUTO; | |
| 29 | +} | |
| 30 | +EXPORT_SYMBOL(__drm_atomic_helper_connector_hdmi_reset); | |
| 31 | + | |
| 32 | +static const struct drm_display_mode * | |
| 33 | +connector_state_get_mode(const struct drm_connector_state *conn_state) | |
| 34 | +{ | |
| 35 | + struct drm_atomic_state *state; | |
| 36 | + struct drm_crtc_state *crtc_state; | |
| 37 | + struct drm_crtc *crtc; | |
| 38 | + | |
| 39 | + state = conn_state->state; | |
| 40 | + if (!state) | |
| 41 | + return NULL; | |
| 42 | + | |
| 43 | + crtc = conn_state->crtc; | |
| 44 | + if (!crtc) | |
| 45 | + return NULL; | |
| 46 | + | |
| 47 | + crtc_state = drm_atomic_get_new_crtc_state(state, crtc); | |
| 48 | + if (!crtc_state) | |
| 49 | + return NULL; | |
| 50 | + | |
| 51 | + return &crtc_state->mode; | |
| 52 | +} | |
| 53 | + | |
| 54 | +static bool hdmi_is_limited_range(const struct drm_connector *connector, | |
| 55 | + const struct drm_connector_state *conn_state) | |
| 56 | +{ | |
| 57 | + const struct drm_display_info *info = &connector->display_info; | |
| 58 | + const struct drm_display_mode *mode = | |
| 59 | + connector_state_get_mode(conn_state); | |
| 60 | + | |
| 61 | + /* | |
| 62 | + * The Broadcast RGB property only applies to RGB format, and | |
| 63 | + * i915 just assumes limited range for YCbCr output, so let's | |
| 64 | + * just do the same. | |
| 65 | + */ | |
| 66 | + if (conn_state->hdmi.output_format != HDMI_COLORSPACE_RGB) | |
| 67 | + return true; | |
| 68 | + | |
| 69 | + if (conn_state->hdmi.broadcast_rgb == DRM_HDMI_BROADCAST_RGB_FULL) | |
| 70 | + return false; | |
| 71 | + | |
| 72 | + if (conn_state->hdmi.broadcast_rgb == DRM_HDMI_BROADCAST_RGB_LIMITED) | |
| 73 | + return true; | |
| 74 | + | |
| 75 | + if (!info->is_hdmi) | |
| 76 | + return false; | |
| 77 | + | |
| 78 | + return drm_default_rgb_quant_range(mode) == HDMI_QUANTIZATION_RANGE_LIMITED; | |
| 79 | +} | |
| 80 | + | |
| 81 | +static bool | |
| 82 | +sink_supports_format_bpc(const struct drm_connector *connector, | |
| 83 | + const struct drm_display_info *info, | |
| 84 | + const struct drm_display_mode *mode, | |
| 85 | + unsigned int format, unsigned int bpc) | |
| 86 | +{ | |
| 87 | + struct drm_device *dev = connector->dev; | |
| 88 | + u8 vic = drm_match_cea_mode(mode); | |
| 89 | + | |
| 90 | + /* | |
| 91 | + * CTA-861-F, section 5.4 - Color Coding & Quantization states | |
| 92 | + * that the bpc must be 8, 10, 12 or 16 except for the default | |
| 93 | + * 640x480 VIC1 where the value must be 8. | |
| 94 | + * | |
| 95 | + * The definition of default here is ambiguous but the spec | |
| 96 | + * refers to VIC1 being the default timing in several occasions | |
| 97 | + * so our understanding is that for the default timing (ie, | |
| 98 | + * VIC1), the bpc must be 8. | |
| 99 | + */ | |
| 100 | + if (vic == 1 && bpc != 8) { | |
| 101 | + drm_dbg_kms(dev, "VIC1 requires a bpc of 8, got %u\n", bpc); | |
| 102 | + return false; | |
| 103 | + } | |
| 104 | + | |
| 105 | + if (!info->is_hdmi && | |
| 106 | + (format != HDMI_COLORSPACE_RGB || bpc != 8)) { | |
| 107 | + drm_dbg_kms(dev, "DVI Monitors require an RGB output at 8 bpc\n"); | |
| 108 | + return false; | |
| 109 | + } | |
| 110 | + | |
| 111 | + if (!(connector->hdmi.supported_formats & BIT(format))) { | |
| 112 | + drm_dbg_kms(dev, "%s format unsupported by the connector.\n", | |
| 113 | + drm_hdmi_connector_get_output_format_name(format)); | |
| 114 | + return false; | |
| 115 | + } | |
| 116 | + | |
| 117 | + switch (format) { | |
| 118 | + case HDMI_COLORSPACE_RGB: | |
| 119 | + drm_dbg_kms(dev, "RGB Format, checking the constraints.\n"); | |
| 120 | + | |
| 121 | + /* | |
| 122 | + * In some cases, like when the EDID readout fails, or | |
| 123 | + * is not an HDMI compliant EDID for some reason, the | |
| 124 | + * color_formats field will be blank and not report any | |
| 125 | + * format supported. In such a case, assume that RGB is | |
| 126 | + * supported so we can keep things going and light up | |
| 127 | + * the display. | |
| 128 | + */ | |
| 129 | + if (!(info->color_formats & DRM_COLOR_FORMAT_RGB444)) | |
| 130 | + drm_warn(dev, "HDMI Sink doesn't support RGB, something's wrong.\n"); | |
| 131 | + | |
| 132 | + if (bpc == 10 && !(info->edid_hdmi_rgb444_dc_modes & DRM_EDID_HDMI_DC_30)) { | |
| 133 | + drm_dbg_kms(dev, "10 BPC but sink doesn't support Deep Color 30.\n"); | |
| 134 | + return false; | |
| 135 | + } | |
| 136 | + | |
| 137 | + if (bpc == 12 && !(info->edid_hdmi_rgb444_dc_modes & DRM_EDID_HDMI_DC_36)) { | |
| 138 | + drm_dbg_kms(dev, "12 BPC but sink doesn't support Deep Color 36.\n"); | |
| 139 | + return false; | |
| 140 | + } | |
| 141 | + | |
| 142 | + drm_dbg_kms(dev, "RGB format supported in that configuration.\n"); | |
| 143 | + | |
| 144 | + return true; | |
| 145 | + | |
| 146 | + case HDMI_COLORSPACE_YUV420: | |
| 147 | + /* TODO: YUV420 is unsupported at the moment. */ | |
| 148 | + drm_dbg_kms(dev, "YUV420 format isn't supported yet.\n"); | |
| 149 | + return false; | |
| 150 | + | |
| 151 | + case HDMI_COLORSPACE_YUV422: | |
| 152 | + drm_dbg_kms(dev, "YUV422 format, checking the constraints.\n"); | |
| 153 | + | |
| 154 | + if (!(info->color_formats & DRM_COLOR_FORMAT_YCBCR422)) { | |
| 155 | + drm_dbg_kms(dev, "Sink doesn't support YUV422.\n"); | |
| 156 | + return false; | |
| 157 | + } | |
| 158 | + | |
| 159 | + if (bpc > 12) { | |
| 160 | + drm_dbg_kms(dev, "YUV422 only supports 12 bpc or lower.\n"); | |
| 161 | + return false; | |
| 162 | + } | |
| 163 | + | |
| 164 | + /* | |
| 165 | + * HDMI Spec 1.3 - Section 6.5 Pixel Encodings and Color Depth | |
| 166 | + * states that Deep Color is not relevant for YUV422 so we | |
| 167 | + * don't need to check the Deep Color bits in the EDIDs here. | |
| 168 | + */ | |
| 169 | + | |
| 170 | + drm_dbg_kms(dev, "YUV422 format supported in that configuration.\n"); | |
| 171 | + | |
| 172 | + return true; | |
| 173 | + | |
| 174 | + case HDMI_COLORSPACE_YUV444: | |
| 175 | + drm_dbg_kms(dev, "YUV444 format, checking the constraints.\n"); | |
| 176 | + | |
| 177 | + if (!(info->color_formats & DRM_COLOR_FORMAT_YCBCR444)) { | |
| 178 | + drm_dbg_kms(dev, "Sink doesn't support YUV444.\n"); | |
| 179 | + return false; | |
| 180 | + } | |
| 181 | + | |
| 182 | + if (bpc == 10 && !(info->edid_hdmi_ycbcr444_dc_modes & DRM_EDID_HDMI_DC_30)) { | |
| 183 | + drm_dbg_kms(dev, "10 BPC but sink doesn't support Deep Color 30.\n"); | |
| 184 | + return false; | |
| 185 | + } | |
| 186 | + | |
| 187 | + if (bpc == 12 && !(info->edid_hdmi_ycbcr444_dc_modes & DRM_EDID_HDMI_DC_36)) { | |
| 188 | + drm_dbg_kms(dev, "12 BPC but sink doesn't support Deep Color 36.\n"); | |
| 189 | + return false; | |
| 190 | + } | |
| 191 | + | |
| 192 | + drm_dbg_kms(dev, "YUV444 format supported in that configuration.\n"); | |
| 193 | + | |
| 194 | + return true; | |
| 195 | + } | |
| 196 | + | |
| 197 | + drm_dbg_kms(dev, "Unsupported pixel format.\n"); | |
| 198 | + return false; | |
| 199 | +} | |
| 200 | + | |
| 201 | +static enum drm_mode_status | |
| 202 | +hdmi_clock_valid(const struct drm_connector *connector, | |
| 203 | + const struct drm_display_mode *mode, | |
| 204 | + unsigned long long clock) | |
| 205 | +{ | |
| 206 | + const struct drm_connector_hdmi_funcs *funcs = connector->hdmi.funcs; | |
| 207 | + const struct drm_display_info *info = &connector->display_info; | |
| 208 | + | |
| 209 | + if (info->max_tmds_clock && clock > info->max_tmds_clock * 1000) | |
| 210 | + return MODE_CLOCK_HIGH; | |
| 211 | + | |
| 212 | + if (funcs && funcs->tmds_char_rate_valid) { | |
| 213 | + enum drm_mode_status status; | |
| 214 | + | |
| 215 | + status = funcs->tmds_char_rate_valid(connector, mode, clock); | |
| 216 | + if (status != MODE_OK) | |
| 217 | + return status; | |
| 218 | + } | |
| 219 | + | |
| 220 | + return MODE_OK; | |
| 221 | +} | |
| 222 | + | |
| 223 | +static int | |
| 224 | +hdmi_compute_clock(const struct drm_connector *connector, | |
| 225 | + struct drm_connector_state *conn_state, | |
| 226 | + const struct drm_display_mode *mode, | |
| 227 | + unsigned int bpc, enum hdmi_colorspace fmt) | |
| 228 | +{ | |
| 229 | + enum drm_mode_status status; | |
| 230 | + unsigned long long clock; | |
| 231 | + | |
| 232 | + clock = drm_hdmi_compute_mode_clock(mode, bpc, fmt); | |
| 233 | + if (!clock) | |
| 234 | + return -EINVAL; | |
| 235 | + | |
| 236 | + status = hdmi_clock_valid(connector, mode, clock); | |
| 237 | + if (status != MODE_OK) | |
| 238 | + return -EINVAL; | |
| 239 | + | |
| 240 | + conn_state->hdmi.tmds_char_rate = clock; | |
| 241 | + | |
| 242 | + return 0; | |
| 243 | +} | |
| 244 | + | |
| 245 | +static bool | |
| 246 | +hdmi_try_format_bpc(const struct drm_connector *connector, | |
| 247 | + struct drm_connector_state *conn_state, | |
| 248 | + const struct drm_display_mode *mode, | |
| 249 | + unsigned int bpc, enum hdmi_colorspace fmt) | |
| 250 | +{ | |
| 251 | + const struct drm_display_info *info = &connector->display_info; | |
| 252 | + struct drm_device *dev = connector->dev; | |
| 253 | + int ret; | |
| 254 | + | |
| 255 | + drm_dbg_kms(dev, "Trying %s output format\n", | |
| 256 | + drm_hdmi_connector_get_output_format_name(fmt)); | |
| 257 | + | |
| 258 | + if (!sink_supports_format_bpc(connector, info, mode, fmt, bpc)) { | |
| 259 | + drm_dbg_kms(dev, "%s output format not supported with %u bpc\n", | |
| 260 | + drm_hdmi_connector_get_output_format_name(fmt), | |
| 261 | + bpc); | |
| 262 | + return false; | |
| 263 | + } | |
| 264 | + | |
| 265 | + ret = hdmi_compute_clock(connector, conn_state, mode, bpc, fmt); | |
| 266 | + if (ret) { | |
| 267 | + drm_dbg_kms(dev, "Couldn't compute clock for %s output format and %u bpc\n", | |
| 268 | + drm_hdmi_connector_get_output_format_name(fmt), | |
| 269 | + bpc); | |
| 270 | + return false; | |
| 271 | + } | |
| 272 | + | |
| 273 | + drm_dbg_kms(dev, "%s output format supported with %u (TMDS char rate: %llu Hz)\n", | |
| 274 | + drm_hdmi_connector_get_output_format_name(fmt), | |
| 275 | + bpc, conn_state->hdmi.tmds_char_rate); | |
| 276 | + | |
| 277 | + return true; | |
| 278 | +} | |
| 279 | + | |
| 280 | +static int | |
| 281 | +hdmi_compute_format(const struct drm_connector *connector, | |
| 282 | + struct drm_connector_state *conn_state, | |
| 283 | + const struct drm_display_mode *mode, | |
| 284 | + unsigned int bpc) | |
| 285 | +{ | |
| 286 | + struct drm_device *dev = connector->dev; | |
| 287 | + | |
| 288 | + /* | |
| 289 | + * TODO: Add support for YCbCr420 output for HDMI 2.0 capable | |
| 290 | + * devices, for modes that only support YCbCr420. | |
| 291 | + */ | |
| 292 | + if (hdmi_try_format_bpc(connector, conn_state, mode, bpc, HDMI_COLORSPACE_RGB)) { | |
| 293 | + conn_state->hdmi.output_format = HDMI_COLORSPACE_RGB; | |
| 294 | + return 0; | |
| 295 | + } | |
| 296 | + | |
| 297 | + drm_dbg_kms(dev, "Failed. No Format Supported for that bpc count.\n"); | |
| 298 | + | |
| 299 | + return -EINVAL; | |
| 300 | +} | |
| 301 | + | |
| 302 | +static int | |
| 303 | +hdmi_compute_config(const struct drm_connector *connector, | |
| 304 | + struct drm_connector_state *conn_state, | |
| 305 | + const struct drm_display_mode *mode) | |
| 306 | +{ | |
| 307 | + struct drm_device *dev = connector->dev; | |
| 308 | + unsigned int max_bpc = clamp_t(unsigned int, | |
| 309 | + conn_state->max_bpc, | |
| 310 | + 8, connector->max_bpc); | |
| 311 | + unsigned int bpc; | |
| 312 | + int ret; | |
| 313 | + | |
| 314 | + for (bpc = max_bpc; bpc >= 8; bpc -= 2) { | |
| 315 | + drm_dbg_kms(dev, "Trying with a %d bpc output\n", bpc); | |
| 316 | + | |
| 317 | + ret = hdmi_compute_format(connector, conn_state, mode, bpc); | |
| 318 | + if (ret) | |
| 319 | + continue; | |
| 320 | + | |
| 321 | + conn_state->hdmi.output_bpc = bpc; | |
| 322 | + | |
| 323 | + drm_dbg_kms(dev, | |
| 324 | + "Mode %ux%u @ %uHz: Found configuration: bpc: %u, fmt: %s, clock: %llu\n", | |
| 325 | + mode->hdisplay, mode->vdisplay, drm_mode_vrefresh(mode), | |
| 326 | + conn_state->hdmi.output_bpc, | |
| 327 | + drm_hdmi_connector_get_output_format_name(conn_state->hdmi.output_format), | |
| 328 | + conn_state->hdmi.tmds_char_rate); | |
| 329 | + | |
| 330 | + return 0; | |
| 331 | + } | |
| 332 | + | |
| 333 | + return -EINVAL; | |
| 334 | +} | |
| 335 | + | |
| 336 | +static int hdmi_generate_avi_infoframe(const struct drm_connector *connector, | |
| 337 | + struct drm_connector_state *conn_state) | |
| 338 | +{ | |
| 339 | + const struct drm_display_mode *mode = | |
| 340 | + connector_state_get_mode(conn_state); | |
| 341 | + struct drm_connector_hdmi_infoframe *infoframe = | |
| 342 | + &conn_state->hdmi.infoframes.avi; | |
| 343 | + struct hdmi_avi_infoframe *frame = | |
| 344 | + &infoframe->data.avi; | |
| 345 | + bool is_limited_range = conn_state->hdmi.is_limited_range; | |
| 346 | + enum hdmi_quantization_range rgb_quant_range = | |
| 347 | + is_limited_range ? HDMI_QUANTIZATION_RANGE_LIMITED : HDMI_QUANTIZATION_RANGE_FULL; | |
| 348 | + int ret; | |
| 349 | + | |
| 350 | + ret = drm_hdmi_avi_infoframe_from_display_mode(frame, connector, mode); | |
| 351 | + if (ret) | |
| 352 | + return ret; | |
| 353 | + | |
| 354 | + frame->colorspace = conn_state->hdmi.output_format; | |
| 355 | + | |
| 356 | + /* | |
| 357 | + * FIXME: drm_hdmi_avi_infoframe_quant_range() doesn't handle | |
| 358 | + * YUV formats at all at the moment, so if we ever support YUV | |
| 359 | + * formats this needs to be revised. | |
| 360 | + */ | |
| 361 | + drm_hdmi_avi_infoframe_quant_range(frame, connector, mode, rgb_quant_range); | |
| 362 | + drm_hdmi_avi_infoframe_colorimetry(frame, conn_state); | |
| 363 | + drm_hdmi_avi_infoframe_bars(frame, conn_state); | |
| 364 | + | |
| 365 | + infoframe->set = true; | |
| 366 | + | |
| 367 | + return 0; | |
| 368 | +} | |
| 369 | + | |
| 370 | +static int hdmi_generate_spd_infoframe(const struct drm_connector *connector, | |
| 371 | + struct drm_connector_state *conn_state) | |
| 372 | +{ | |
| 373 | + struct drm_connector_hdmi_infoframe *infoframe = | |
| 374 | + &conn_state->hdmi.infoframes.spd; | |
| 375 | + struct hdmi_spd_infoframe *frame = | |
| 376 | + &infoframe->data.spd; | |
| 377 | + int ret; | |
| 378 | + | |
| 379 | + ret = hdmi_spd_infoframe_init(frame, | |
| 380 | + connector->hdmi.vendor, | |
| 381 | + connector->hdmi.product); | |
| 382 | + if (ret) | |
| 383 | + return ret; | |
| 384 | + | |
| 385 | + frame->sdi = HDMI_SPD_SDI_PC; | |
| 386 | + | |
| 387 | + infoframe->set = true; | |
| 388 | + | |
| 389 | + return 0; | |
| 390 | +} | |
| 391 | + | |
| 392 | +static int hdmi_generate_hdr_infoframe(const struct drm_connector *connector, | |
| 393 | + struct drm_connector_state *conn_state) | |
| 394 | +{ | |
| 395 | + struct drm_connector_hdmi_infoframe *infoframe = | |
| 396 | + &conn_state->hdmi.infoframes.hdr_drm; | |
| 397 | + struct hdmi_drm_infoframe *frame = | |
| 398 | + &infoframe->data.drm; | |
| 399 | + int ret; | |
| 400 | + | |
| 401 | + if (connector->max_bpc < 10) | |
| 402 | + return 0; | |
| 403 | + | |
| 404 | + if (!conn_state->hdr_output_metadata) | |
| 405 | + return 0; | |
| 406 | + | |
| 407 | + ret = drm_hdmi_infoframe_set_hdr_metadata(frame, conn_state); | |
| 408 | + if (ret) | |
| 409 | + return ret; | |
| 410 | + | |
| 411 | + infoframe->set = true; | |
| 412 | + | |
| 413 | + return 0; | |
| 414 | +} | |
| 415 | + | |
| 416 | +static int hdmi_generate_hdmi_vendor_infoframe(const struct drm_connector *connector, | |
| 417 | + struct drm_connector_state *conn_state) | |
| 418 | +{ | |
| 419 | + const struct drm_display_info *info = &connector->display_info; | |
| 420 | + const struct drm_display_mode *mode = | |
| 421 | + connector_state_get_mode(conn_state); | |
| 422 | + struct drm_connector_hdmi_infoframe *infoframe = | |
| 423 | + &conn_state->hdmi.infoframes.hdmi; | |
| 424 | + struct hdmi_vendor_infoframe *frame = | |
| 425 | + &infoframe->data.vendor.hdmi; | |
| 426 | + int ret; | |
| 427 | + | |
| 428 | + if (!info->has_hdmi_infoframe) | |
| 429 | + return 0; | |
| 430 | + | |
| 431 | + ret = drm_hdmi_vendor_infoframe_from_display_mode(frame, connector, mode); | |
| 432 | + if (ret) | |
| 433 | + return ret; | |
| 434 | + | |
| 435 | + infoframe->set = true; | |
| 436 | + | |
| 437 | + return 0; | |
| 438 | +} | |
| 439 | + | |
| 440 | +static int | |
| 441 | +hdmi_generate_infoframes(const struct drm_connector *connector, | |
| 442 | + struct drm_connector_state *conn_state) | |
| 443 | +{ | |
| 444 | + const struct drm_display_info *info = &connector->display_info; | |
| 445 | + int ret; | |
| 446 | + | |
| 447 | + if (!info->is_hdmi) | |
| 448 | + return 0; | |
| 449 | + | |
| 450 | + ret = hdmi_generate_avi_infoframe(connector, conn_state); | |
| 451 | + if (ret) | |
| 452 | + return ret; | |
| 453 | + | |
| 454 | + ret = hdmi_generate_spd_infoframe(connector, conn_state); | |
| 455 | + if (ret) | |
| 456 | + return ret; | |
| 457 | + | |
| 458 | + /* | |
| 459 | + * Audio Infoframes will be generated by ALSA, and updated by | |
| 460 | + * drm_atomic_helper_connector_hdmi_update_audio_infoframe(). | |
| 461 | + */ | |
| 462 | + | |
| 463 | + ret = hdmi_generate_hdr_infoframe(connector, conn_state); | |
| 464 | + if (ret) | |
| 465 | + return ret; | |
| 466 | + | |
| 467 | + ret = hdmi_generate_hdmi_vendor_infoframe(connector, conn_state); | |
| 468 | + if (ret) | |
| 469 | + return ret; | |
| 470 | + | |
| 471 | + return 0; | |
| 472 | +} | |
| 473 | + | |
| 474 | +/** | |
| 475 | + * drm_atomic_helper_connector_hdmi_check() - Helper to check HDMI connector atomic state | |
| 476 | + * @connector: DRM Connector | |
| 477 | + * @state: the DRM State object | |
| 478 | + * | |
| 479 | + * Provides a default connector state check handler for HDMI connectors. | |
| 480 | + * Checks that a desired connector update is valid, and updates various | |
| 481 | + * fields of derived state. | |
| 482 | + * | |
| 483 | + * RETURNS: | |
| 484 | + * Zero on success, or an errno code otherwise. | |
| 485 | + */ | |
| 486 | +int drm_atomic_helper_connector_hdmi_check(struct drm_connector *connector, | |
| 487 | + struct drm_atomic_state *state) | |
| 488 | +{ | |
| 489 | + struct drm_connector_state *old_conn_state = | |
| 490 | + drm_atomic_get_old_connector_state(state, connector); | |
| 491 | + struct drm_connector_state *new_conn_state = | |
| 492 | + drm_atomic_get_new_connector_state(state, connector); | |
| 493 | + const struct drm_display_mode *mode = | |
| 494 | + connector_state_get_mode(new_conn_state); | |
| 495 | + int ret; | |
| 496 | + | |
| 497 | + new_conn_state->hdmi.is_limited_range = hdmi_is_limited_range(connector, new_conn_state); | |
| 498 | + | |
| 499 | + ret = hdmi_compute_config(connector, new_conn_state, mode); | |
| 500 | + if (ret) | |
| 501 | + return ret; | |
| 502 | + | |
| 503 | + ret = hdmi_generate_infoframes(connector, new_conn_state); | |
| 504 | + if (ret) | |
| 505 | + return ret; | |
| 506 | + | |
| 507 | + if (old_conn_state->hdmi.broadcast_rgb != new_conn_state->hdmi.broadcast_rgb || | |
| 508 | + old_conn_state->hdmi.output_bpc != new_conn_state->hdmi.output_bpc || | |
| 509 | + old_conn_state->hdmi.output_format != new_conn_state->hdmi.output_format) { | |
| 510 | + struct drm_crtc *crtc = new_conn_state->crtc; | |
| 511 | + struct drm_crtc_state *crtc_state; | |
| 512 | + | |
| 513 | + crtc_state = drm_atomic_get_crtc_state(state, crtc); | |
| 514 | + if (IS_ERR(crtc_state)) | |
| 515 | + return PTR_ERR(crtc_state); | |
| 516 | + | |
| 517 | + crtc_state->mode_changed = true; | |
| 518 | + } | |
| 519 | + | |
| 520 | + return 0; | |
| 521 | +} | |
| 522 | +EXPORT_SYMBOL(drm_atomic_helper_connector_hdmi_check); | |
| 523 | + | |
| 524 | +#define HDMI_MAX_INFOFRAME_SIZE 29 | |
| 525 | + | |
| 526 | +static int clear_device_infoframe(struct drm_connector *connector, | |
| 527 | + enum hdmi_infoframe_type type) | |
| 528 | +{ | |
| 529 | + const struct drm_connector_hdmi_funcs *funcs = connector->hdmi.funcs; | |
| 530 | + struct drm_device *dev = connector->dev; | |
| 531 | + int ret; | |
| 532 | + | |
| 533 | + drm_dbg_kms(dev, "Clearing infoframe type 0x%x\n", type); | |
| 534 | + | |
| 535 | + if (!funcs || !funcs->clear_infoframe) { | |
| 536 | + drm_dbg_kms(dev, "Function not implemented, bailing.\n"); | |
| 537 | + return 0; | |
| 538 | + } | |
| 539 | + | |
| 540 | + ret = funcs->clear_infoframe(connector, type); | |
| 541 | + if (ret) { | |
| 542 | + drm_dbg_kms(dev, "Call failed: %d\n", ret); | |
| 543 | + return ret; | |
| 544 | + } | |
| 545 | + | |
| 546 | + return 0; | |
| 547 | +} | |
| 548 | + | |
| 549 | +static int clear_infoframe(struct drm_connector *connector, | |
| 550 | + struct drm_connector_hdmi_infoframe *old_frame) | |
| 551 | +{ | |
| 552 | + int ret; | |
| 553 | + | |
| 554 | + ret = clear_device_infoframe(connector, old_frame->data.any.type); | |
| 555 | + if (ret) | |
| 556 | + return ret; | |
| 557 | + | |
| 558 | + return 0; | |
| 559 | +} | |
| 560 | + | |
| 561 | +static int write_device_infoframe(struct drm_connector *connector, | |
| 562 | + union hdmi_infoframe *frame) | |
| 563 | +{ | |
| 564 | + const struct drm_connector_hdmi_funcs *funcs = connector->hdmi.funcs; | |
| 565 | + struct drm_device *dev = connector->dev; | |
| 566 | + u8 buffer[HDMI_MAX_INFOFRAME_SIZE]; | |
| 567 | + int ret; | |
| 568 | + int len; | |
| 569 | + | |
| 570 | + drm_dbg_kms(dev, "Writing infoframe type %x\n", frame->any.type); | |
| 571 | + | |
| 572 | + if (!funcs || !funcs->write_infoframe) { | |
| 573 | + drm_dbg_kms(dev, "Function not implemented, bailing.\n"); | |
| 574 | + return -EINVAL; | |
| 575 | + } | |
| 576 | + | |
| 577 | + len = hdmi_infoframe_pack(frame, buffer, sizeof(buffer)); | |
| 578 | + if (len < 0) | |
| 579 | + return len; | |
| 580 | + | |
| 581 | + ret = funcs->write_infoframe(connector, frame->any.type, buffer, len); | |
| 582 | + if (ret) { | |
| 583 | + drm_dbg_kms(dev, "Call failed: %d\n", ret); | |
| 584 | + return ret; | |
| 585 | + } | |
| 586 | + | |
| 587 | + return 0; | |
| 588 | +} | |
| 589 | + | |
| 590 | +static int write_infoframe(struct drm_connector *connector, | |
| 591 | + struct drm_connector_hdmi_infoframe *new_frame) | |
| 592 | +{ | |
| 593 | + int ret; | |
| 594 | + | |
| 595 | + ret = write_device_infoframe(connector, &new_frame->data); | |
| 596 | + if (ret) | |
| 597 | + return ret; | |
| 598 | + | |
| 599 | + return 0; | |
| 600 | +} | |
| 601 | + | |
| 602 | +static int write_or_clear_infoframe(struct drm_connector *connector, | |
| 603 | + struct drm_connector_hdmi_infoframe *old_frame, | |
| 604 | + struct drm_connector_hdmi_infoframe *new_frame) | |
| 605 | +{ | |
| 606 | + if (new_frame->set) | |
| 607 | + return write_infoframe(connector, new_frame); | |
| 608 | + | |
| 609 | + if (old_frame->set && !new_frame->set) | |
| 610 | + return clear_infoframe(connector, old_frame); | |
| 611 | + | |
| 612 | + return 0; | |
| 613 | +} | |
| 614 | + | |
| 615 | +/** | |
| 616 | + * drm_atomic_helper_connector_hdmi_update_infoframes - Update the Infoframes | |
| 617 | + * @connector: A pointer to the HDMI connector | |
| 618 | + * @state: The HDMI connector state to generate the infoframe from | |
| 619 | + * | |
| 620 | + * This function is meant for HDMI connector drivers to write their | |
| 621 | + * infoframes. It will typically be used in a | |
| 622 | + * @drm_connector_helper_funcs.atomic_enable implementation. | |
| 623 | + * | |
| 624 | + * Returns: | |
| 625 | + * Zero on success, error code on failure. | |
| 626 | + */ | |
| 627 | +int drm_atomic_helper_connector_hdmi_update_infoframes(struct drm_connector *connector, | |
| 628 | + struct drm_atomic_state *state) | |
| 629 | +{ | |
| 630 | + struct drm_connector_state *old_conn_state = | |
| 631 | + drm_atomic_get_old_connector_state(state, connector); | |
| 632 | + struct drm_connector_state *new_conn_state = | |
| 633 | + drm_atomic_get_new_connector_state(state, connector); | |
| 634 | + struct drm_display_info *info = &connector->display_info; | |
| 635 | + int ret; | |
| 636 | + | |
| 637 | + if (!info->is_hdmi) | |
| 638 | + return 0; | |
| 639 | + | |
| 640 | + mutex_lock(&connector->hdmi.infoframes.lock); | |
| 641 | + | |
| 642 | + ret = write_or_clear_infoframe(connector, | |
| 643 | + &old_conn_state->hdmi.infoframes.avi, | |
| 644 | + &new_conn_state->hdmi.infoframes.avi); | |
| 645 | + if (ret) | |
| 646 | + goto out; | |
| 647 | + | |
| 648 | + if (connector->hdmi.infoframes.audio.set) { | |
| 649 | + ret = write_infoframe(connector, | |
| 650 | + &connector->hdmi.infoframes.audio); | |
| 651 | + if (ret) | |
| 652 | + goto out; | |
| 653 | + } | |
| 654 | + | |
| 655 | + ret = write_or_clear_infoframe(connector, | |
| 656 | + &old_conn_state->hdmi.infoframes.hdr_drm, | |
| 657 | + &new_conn_state->hdmi.infoframes.hdr_drm); | |
| 658 | + if (ret) | |
| 659 | + goto out; | |
| 660 | + | |
| 661 | + ret = write_or_clear_infoframe(connector, | |
| 662 | + &old_conn_state->hdmi.infoframes.spd, | |
| 663 | + &new_conn_state->hdmi.infoframes.spd); | |
| 664 | + if (ret) | |
| 665 | + goto out; | |
| 666 | + | |
| 667 | + if (info->has_hdmi_infoframe) { | |
| 668 | + ret = write_or_clear_infoframe(connector, | |
| 669 | + &old_conn_state->hdmi.infoframes.hdmi, | |
| 670 | + &new_conn_state->hdmi.infoframes.hdmi); | |
| 671 | + if (ret) | |
| 672 | + goto out; | |
| 673 | + } | |
| 674 | + | |
| 675 | +out: | |
| 676 | + mutex_unlock(&connector->hdmi.infoframes.lock); | |
| 677 | + return ret; | |
| 678 | +} | |
| 679 | +EXPORT_SYMBOL(drm_atomic_helper_connector_hdmi_update_infoframes); | |
| 680 | + | |
| 681 | +/** | |
| 682 | + * drm_atomic_helper_connector_hdmi_update_audio_infoframe - Update the Audio Infoframe | |
| 683 | + * @connector: A pointer to the HDMI connector | |
| 684 | + * @frame: A pointer to the audio infoframe to write | |
| 685 | + * | |
| 686 | + * This function is meant for HDMI connector drivers to update their | |
| 687 | + * audio infoframe. It will typically be used in one of the ALSA hooks | |
| 688 | + * (most likely prepare). | |
| 689 | + * | |
| 690 | + * Returns: | |
| 691 | + * Zero on success, error code on failure. | |
| 692 | + */ | |
| 693 | +int | |
| 694 | +drm_atomic_helper_connector_hdmi_update_audio_infoframe(struct drm_connector *connector, | |
| 695 | + struct hdmi_audio_infoframe *frame) | |
| 696 | +{ | |
| 697 | + struct drm_connector_hdmi_infoframe *infoframe = | |
| 698 | + &connector->hdmi.infoframes.audio; | |
| 699 | + struct drm_display_info *info = &connector->display_info; | |
| 700 | + int ret; | |
| 701 | + | |
| 702 | + if (!info->is_hdmi) | |
| 703 | + return 0; | |
| 704 | + | |
| 705 | + mutex_lock(&connector->hdmi.infoframes.lock); | |
| 706 | + | |
| 707 | + memcpy(&infoframe->data, frame, sizeof(infoframe->data)); | |
| 708 | + infoframe->set = true; | |
| 709 | + | |
| 710 | + ret = write_infoframe(connector, infoframe); | |
| 711 | + | |
| 712 | + mutex_unlock(&connector->hdmi.infoframes.lock); | |
| 713 | + | |
| 714 | + return ret; | |
| 715 | +} | |
| 716 | +EXPORT_SYMBOL(drm_atomic_helper_connector_hdmi_update_audio_infoframe); | |
| 717 | + | |
| 718 | +/** | |
| 719 | + * drm_atomic_helper_connector_hdmi_disable_audio_infoframe - Stop sending the Audio Infoframe | |
| 720 | + * @connector: A pointer to the HDMI connector | |
| 721 | + * | |
| 722 | + * This function is meant for HDMI connector drivers to stop sending their | |
| 723 | + * audio infoframe. It will typically be used in one of the ALSA hooks | |
| 724 | + * (most likely shutdown). | |
| 725 | + * | |
| 726 | + * Returns: | |
| 727 | + * Zero on success, error code on failure. | |
| 728 | + */ | |
| 729 | +int | |
| 730 | +drm_atomic_helper_connector_hdmi_disable_audio_infoframe(struct drm_connector *connector) | |
| 731 | +{ | |
| 732 | + struct drm_connector_hdmi_infoframe *infoframe = | |
| 733 | + &connector->hdmi.infoframes.audio; | |
| 734 | + struct drm_display_info *info = &connector->display_info; | |
| 735 | + int ret; | |
| 736 | + | |
| 737 | + if (!info->is_hdmi) | |
| 738 | + return 0; | |
| 739 | + | |
| 740 | + mutex_lock(&connector->hdmi.infoframes.lock); | |
| 741 | + | |
| 742 | + infoframe->set = false; | |
| 743 | + | |
| 744 | + ret = clear_infoframe(connector, infoframe); | |
| 745 | + | |
| 746 | + memset(&infoframe->data, 0, sizeof(infoframe->data)); | |
| 747 | + | |
| 748 | + mutex_unlock(&connector->hdmi.infoframes.lock); | |
| 749 | + | |
| 750 | + return ret; | |
| 751 | +} | |
| 752 | +EXPORT_SYMBOL(drm_atomic_helper_connector_hdmi_disable_audio_infoframe); | |
| @@ -1143,6 +1143,17 @@ static void drm_atomic_connector_print_state(struct drm_printer *p, · 1142 unmodified lines | ||
| 1143 | 1143 | drm_printf(p, "\tmax_requested_bpc=%d\n", state->max_requested_bpc); |
| 1144 | 1144 | drm_printf(p, "\tcolorspace=%s\n", drm_get_colorspace_name(state->colorspace)); |
| 1145 | 1145 | |
| 1146 | + if (connector->connector_type == DRM_MODE_CONNECTOR_HDMIA || | |
| 1147 | + connector->connector_type == DRM_MODE_CONNECTOR_HDMIB) { | |
| 1148 | + drm_printf(p, "\tbroadcast_rgb=%s\n", | |
| 1149 | + drm_hdmi_connector_get_broadcast_rgb_name(state->hdmi.broadcast_rgb)); | |
| 1150 | + drm_printf(p, "\tis_limited_range=%c\n", state->hdmi.is_limited_range ? 'y' : 'n'); | |
| 1151 | + drm_printf(p, "\toutput_bpc=%u\n", state->hdmi.output_bpc); | |
| 1152 | + drm_printf(p, "\toutput_format=%s\n", | |
| 1153 | + drm_hdmi_connector_get_output_format_name(state->hdmi.output_format)); | |
| 1154 | + drm_printf(p, "\ttmds_char_rate=%llu\n", state->hdmi.tmds_char_rate); | |
| 1155 | + } | |
| 1156 | + | |
| 1146 | 1157 | if (connector->connector_type == DRM_MODE_CONNECTOR_WRITEBACK) |
| 1147 | 1158 | if (state->writeback_job && state->writeback_job->fb) |
| 1148 | 1159 | drm_printf(p, "\tfb=%d\n", state->writeback_job->fb->base.id); |
| @@ -776,6 +776,8 @@ static int drm_atomic_connector_set_property(struct drm_connector *connector, · 775 unmodified lines | ||
| 776 | 776 | state->max_requested_bpc = val; |
| 777 | 777 | } else if (property == connector->privacy_screen_sw_state_property) { |
| 778 | 778 | state->privacy_screen_sw_state = val; |
| 779 | + } else if (property == connector->broadcast_rgb_property) { | |
| 780 | + state->hdmi.broadcast_rgb = val; | |
| 779 | 781 | } else if (connector->funcs->atomic_set_property) { |
| 780 | 782 | return connector->funcs->atomic_set_property(connector, |
| 781 | 783 | state, property, val); |
| @@ -859,6 +861,8 @@ drm_atomic_connector_get_property(struct drm_connector *connector, · 77 unmodified lines | ||
| 859 | 861 | *val = state->max_requested_bpc; |
| 860 | 862 | } else if (property == connector->privacy_screen_sw_state_property) { |
| 861 | 863 | *val = state->privacy_screen_sw_state; |
| 864 | + } else if (property == connector->broadcast_rgb_property) { | |
| 865 | + *val = state->hdmi.broadcast_rgb; | |
| 862 | 866 | } else if (connector->funcs->atomic_get_property) { |
| 863 | 867 | return connector->funcs->atomic_get_property(connector, |
| 864 | 868 | state, property, val); |
| @@ -353,13 +353,8 @@ err_reset_bridge: · 352 unmodified lines | ||
| 353 | 353 | bridge->encoder = NULL; |
| 354 | 354 | list_del(&bridge->chain_node); |
| 355 | 355 | |
| 356 | −#ifdef CONFIG_OF | |
| 357 | 356 | DRM_ERROR("failed to attach bridge %pOF to encoder %s: %d\n", |
| 358 | 357 | bridge->of_node, encoder->name, ret); |
| 359 | −#else | |
| 360 | − DRM_ERROR("failed to attach bridge to encoder %s: %d\n", | |
| 361 | − encoder->name, ret); | |
| 362 | −#endif | |
| 363 | 358 | |
| 364 | 359 | return ret; |
| 365 | 360 | } |
| @@ -472,43 +467,6 @@ void drm_bridge_detach(struct drm_bridge *bridge) · 106 unmodified lines | ||
| 472 | 467 | * needed, in order to gradually transition to the new model. |
| 473 | 468 | */ |
| 474 | 469 | |
| 475 | −/** | |
| 476 | − * drm_bridge_chain_mode_fixup - fixup proposed mode for all bridges in the | |
| 477 | − * encoder chain | |
| 478 | − * @bridge: bridge control structure | |
| 479 | − * @mode: desired mode to be set for the bridge | |
| 480 | − * @adjusted_mode: updated mode that works for this bridge | |
| 481 | − * | |
| 482 | − * Calls &drm_bridge_funcs.mode_fixup for all the bridges in the | |
| 483 | − * encoder chain, starting from the first bridge to the last. | |
| 484 | − * | |
| 485 | − * Note: the bridge passed should be the one closest to the encoder | |
| 486 | − * | |
| 487 | − * RETURNS: | |
| 488 | − * true on success, false on failure | |
| 489 | − */ | |
| 490 | −bool drm_bridge_chain_mode_fixup(struct drm_bridge *bridge, | |
| 491 | − const struct drm_display_mode *mode, | |
| 492 | − struct drm_display_mode *adjusted_mode) | |
| 493 | −{ | |
| 494 | − struct drm_encoder *encoder; | |
| 495 | − | |
| 496 | − if (!bridge) | |
| 497 | − return true; | |
| 498 | − | |
| 499 | − encoder = bridge->encoder; | |
| 500 | − list_for_each_entry_from(bridge, &encoder->bridge_chain, chain_node) { | |
| 501 | − if (!bridge->funcs->mode_fixup) | |
| 502 | − continue; | |
| 503 | − | |
| 504 | − if (!bridge->funcs->mode_fixup(bridge, mode, adjusted_mode)) | |
| 505 | − return false; | |
| 506 | − } | |
| 507 | − | |
| 508 | − return true; | |
| 509 | −} | |
| 510 | −EXPORT_SYMBOL(drm_bridge_chain_mode_fixup); | |
| 511 | − | |
| 512 | 470 | /** |
| 513 | 471 | * drm_bridge_chain_mode_valid - validate the mode against all bridges in the |
| 514 | 472 | * encoder chain. |
| @@ -15,8 +15,10 @@ · 14 unmodified lines | ||
| 15 | 15 | #include <drm/drm_connector.h> |
| 16 | 16 | #include <drm/drm_device.h> |
| 17 | 17 | #include <drm/drm_edid.h> |
| 18 | +#include <drm/drm_managed.h> | |
| 18 | 19 | #include <drm/drm_modeset_helper_vtables.h> |
| 19 | 20 | #include <drm/drm_probe_helper.h> |
| 21 | +#include <drm/display/drm_hdmi_state_helper.h> | |
| 20 | 22 | |
| 21 | 23 | /** |
| 22 | 24 | * DOC: overview |
| @@ -86,6 +88,13 @@ struct drm_bridge_connector { · 63 unmodified lines | ||
| 86 | 88 | * connector modes detection, if any (see &DRM_BRIDGE_OP_MODES). |
| 87 | 89 | */ |
| 88 | 90 | struct drm_bridge *bridge_modes; |
| 91 | + /** | |
| 92 | + * @bridge_hdmi: | |
| 93 | + * | |
| 94 | + * The bridge in the chain that implements necessary support for the | |
| 95 | + * HDMI connector infrastructure, if any (see &DRM_BRIDGE_OP_HDMI). | |
| 96 | + */ | |
| 97 | + struct drm_bridge *bridge_hdmi; | |
| 89 | 98 | }; |
| 90 | 99 | |
| 91 | 100 | #define to_drm_bridge_connector(x) \ |
| @@ -193,19 +202,6 @@ drm_bridge_connector_detect(struct drm_connector *connector, bool force) · 101 unmodified lines | ||
| 193 | 202 | return status; |
| 194 | 203 | } |
| 195 | 204 | |
| 196 | −static void drm_bridge_connector_destroy(struct drm_connector *connector) | |
| 197 | −{ | |
| 198 | − struct drm_bridge_connector *bridge_connector = | |
| 199 | − to_drm_bridge_connector(connector); | |
| 200 | − | |
| 201 | − drm_connector_unregister(connector); | |
| 202 | − drm_connector_cleanup(connector); | |
| 203 | − | |
| 204 | − fwnode_handle_put(connector->fwnode); | |
| 205 | − | |
| 206 | − kfree(bridge_connector); | |
| 207 | −} | |
| 208 | − | |
| 209 | 205 | static void drm_bridge_connector_debugfs_init(struct drm_connector *connector, |
| 210 | 206 | struct dentry *root) |
| 211 | 207 | { |
| @@ -224,7 +220,6 @@ static const struct drm_connector_funcs drm_bridge_connector_funcs = { · 12 unmodified lines | ||
| 224 | 220 | .reset = drm_atomic_helper_connector_reset, |
| 225 | 221 | .detect = drm_bridge_connector_detect, |
| 226 | 222 | .fill_modes = drm_helper_probe_single_connector_modes, |
| 227 | − .destroy = drm_bridge_connector_destroy, | |
| 228 | 223 | .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state, |
| 229 | 224 | .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, |
| 230 | 225 | .debugfs_init = drm_bridge_connector_debugfs_init, |
| @@ -300,6 +295,60 @@ static const struct drm_connector_helper_funcs drm_bridge_connector_helper_funcs · 69 unmodified lines | ||
| 300 | 295 | .disable_hpd = drm_bridge_connector_disable_hpd, |
| 301 | 296 | }; |
| 302 | 297 | |
| 298 | +static enum drm_mode_status | |
| 299 | +drm_bridge_connector_tmds_char_rate_valid(const struct drm_connector *connector, | |
| 300 | + const struct drm_display_mode *mode, | |
| 301 | + unsigned long long tmds_rate) | |
| 302 | +{ | |
| 303 | + struct drm_bridge_connector *bridge_connector = | |
| 304 | + to_drm_bridge_connector(connector); | |
| 305 | + struct drm_bridge *bridge; | |
| 306 | + | |
| 307 | + bridge = bridge_connector->bridge_hdmi; | |
| 308 | + if (!bridge) | |
| 309 | + return MODE_ERROR; | |
| 310 | + | |
| 311 | + if (bridge->funcs->hdmi_tmds_char_rate_valid) | |
| 312 | + return bridge->funcs->hdmi_tmds_char_rate_valid(bridge, mode, tmds_rate); | |
| 313 | + else | |
| 314 | + return MODE_OK; | |
| 315 | +} | |
| 316 | + | |
| 317 | +static int drm_bridge_connector_clear_infoframe(struct drm_connector *connector, | |
| 318 | + enum hdmi_infoframe_type type) | |
| 319 | +{ | |
| 320 | + struct drm_bridge_connector *bridge_connector = | |
| 321 | + to_drm_bridge_connector(connector); | |
| 322 | + struct drm_bridge *bridge; | |
| 323 | + | |
| 324 | + bridge = bridge_connector->bridge_hdmi; | |
| 325 | + if (!bridge) | |
| 326 | + return -EINVAL; | |
| 327 | + | |
| 328 | + return bridge->funcs->hdmi_clear_infoframe(bridge, type); | |
| 329 | +} | |
| 330 | + | |
| 331 | +static int drm_bridge_connector_write_infoframe(struct drm_connector *connector, | |
| 332 | + enum hdmi_infoframe_type type, | |
| 333 | + const u8 *buffer, size_t len) | |
| 334 | +{ | |
| 335 | + struct drm_bridge_connector *bridge_connector = | |
| 336 | + to_drm_bridge_connector(connector); | |
| 337 | + struct drm_bridge *bridge; | |
| 338 | + | |
| 339 | + bridge = bridge_connector->bridge_hdmi; | |
| 340 | + if (!bridge) | |
| 341 | + return -EINVAL; | |
| 342 | + | |
| 343 | + return bridge->funcs->hdmi_write_infoframe(bridge, type, buffer, len); | |
| 344 | +} | |
| 345 | + | |
| 346 | +static const struct drm_connector_hdmi_funcs drm_bridge_connector_hdmi_funcs = { | |
| 347 | + .tmds_char_rate_valid = drm_bridge_connector_tmds_char_rate_valid, | |
| 348 | + .clear_infoframe = drm_bridge_connector_clear_infoframe, | |
| 349 | + .write_infoframe = drm_bridge_connector_write_infoframe, | |
| 350 | +}; | |
| 351 | + | |
| 303 | 352 | /* ----------------------------------------------------------------------------- |
| 304 | 353 | * Bridge Connector Initialisation |
| 305 | 354 | */ |
| @@ -325,10 +374,12 @@ struct drm_connector *drm_bridge_connector_init(struct drm_device *drm, · 19 unmodified lines | ||
| 325 | 374 | struct drm_connector *connector; |
| 326 | 375 | struct i2c_adapter *ddc = NULL; |
| 327 | 376 | struct drm_bridge *bridge, *panel_bridge = NULL; |
| 377 | + unsigned int supported_formats = BIT(HDMI_COLORSPACE_RGB); | |
| 378 | + unsigned int max_bpc = 8; | |
| 328 | 379 | int connector_type; |
| 329 | 380 | int ret; |
| 330 | 381 | |
| 331 | − bridge_connector = kzalloc(sizeof(*bridge_connector), GFP_KERNEL); | |
| 382 | + bridge_connector = drmm_kzalloc(drm, sizeof(*bridge_connector), GFP_KERNEL); | |
| 332 | 383 | if (!bridge_connector) |
| 333 | 384 | return ERR_PTR(-ENOMEM); |
| 334 | 385 | |
| @@ -361,6 +412,20 @@ struct drm_connector *drm_bridge_connector_init(struct drm_device *drm, · 26 unmodified lines | ||
| 361 | 412 | bridge_connector->bridge_detect = bridge; |
| 362 | 413 | if (bridge->ops & DRM_BRIDGE_OP_MODES) |
| 363 | 414 | bridge_connector->bridge_modes = bridge; |
| 415 | + if (bridge->ops & DRM_BRIDGE_OP_HDMI) { | |
| 416 | + if (bridge_connector->bridge_hdmi) | |
| 417 | + return ERR_PTR(-EBUSY); | |
| 418 | + if (!bridge->funcs->hdmi_write_infoframe || | |
| 419 | + !bridge->funcs->hdmi_clear_infoframe) | |
| 420 | + return ERR_PTR(-EINVAL); | |
| 421 | + | |
| 422 | + bridge_connector->bridge_hdmi = bridge; | |
| 423 | + | |
| 424 | + if (bridge->supported_formats) | |
| 425 | + supported_formats = bridge->supported_formats; | |
| 426 | + if (bridge->max_bpc) | |
| 427 | + max_bpc = bridge->max_bpc; | |
| 428 | + } | |
| 364 | 429 | |
| 365 | 430 | if (!drm_bridge_get_next_bridge(bridge)) |
| 366 | 431 | connector_type = bridge->type; |
| @@ -383,7 +448,17 @@ struct drm_connector *drm_bridge_connector_init(struct drm_device *drm, · 16 unmodified lines | ||
| 383 | 448 | return ERR_PTR(-EINVAL); |
| 384 | 449 | } |
| 385 | 450 | |
| 386 | − ret = drm_connector_init_with_ddc(drm, connector, | |
| 451 | + if (bridge_connector->bridge_hdmi) | |
| 452 | + ret = drmm_connector_hdmi_init(drm, connector, | |
| 453 | + bridge_connector->bridge_hdmi->vendor, | |
| 454 | + bridge_connector->bridge_hdmi->product, | |
| 455 | + &drm_bridge_connector_funcs, | |
| 456 | + &drm_bridge_connector_hdmi_funcs, | |
| 457 | + connector_type, ddc, | |
| 458 | + supported_formats, | |
| 459 | + max_bpc); | |
| 460 | + else | |
| 461 | + ret = drmm_connector_init(drm, connector, | |
| 387 | 462 | &drm_bridge_connector_funcs, |
| 388 | 463 | connector_type, ddc); |
| 389 | 464 | if (ret) { |
| @@ -278,6 +278,7 @@ static int __drm_connector_init(struct drm_device *dev, · 277 unmodified lines | ||
| 278 | 278 | INIT_LIST_HEAD(&connector->modes); |
| 279 | 279 | mutex_init(&connector->mutex); |
| 280 | 280 | mutex_init(&connector->edid_override_mutex); |
| 281 | + mutex_init(&connector->hdmi.infoframes.lock); | |
| 281 | 282 | connector->edid_blob_ptr = NULL; |
| 282 | 283 | connector->epoch_counter = 0; |
| 283 | 284 | connector->tile_blob_ptr = NULL; |
| @@ -452,6 +453,86 @@ int drmm_connector_init(struct drm_device *dev, · 168 unmodified lines | ||
| 452 | 453 | } |
| 453 | 454 | EXPORT_SYMBOL(drmm_connector_init); |
| 454 | 455 | |
| 456 | +/** | |
| 457 | + * drmm_connector_hdmi_init - Init a preallocated HDMI connector | |
| 458 | + * @dev: DRM device | |
| 459 | + * @connector: A pointer to the HDMI connector to init | |
| 460 | + * @vendor: HDMI Controller Vendor name | |
| 461 | + * @product: HDMI Controller Product name | |
| 462 | + * @funcs: callbacks for this connector | |
| 463 | + * @hdmi_funcs: HDMI-related callbacks for this connector | |
| 464 | + * @connector_type: user visible type of the connector | |
| 465 | + * @ddc: optional pointer to the associated ddc adapter | |
| 466 | + * @supported_formats: Bitmask of @hdmi_colorspace listing supported output formats | |
| 467 | + * @max_bpc: Maximum bits per char the HDMI connector supports | |
| 468 | + * | |
| 469 | + * Initialises a preallocated HDMI connector. Connectors can be | |
| 470 | + * subclassed as part of driver connector objects. | |
| 471 | + * | |
| 472 | + * Cleanup is automatically handled with a call to | |
| 473 | + * drm_connector_cleanup() in a DRM-managed action. | |
| 474 | + * | |
| 475 | + * The connector structure should be allocated with drmm_kzalloc(). | |
| 476 | + * | |
| 477 | + * Returns: | |
| 478 | + * Zero on success, error code on failure. | |
| 479 | + */ | |
| 480 | +int drmm_connector_hdmi_init(struct drm_device *dev, | |
| 481 | + struct drm_connector *connector, | |
| 482 | + const char *vendor, const char *product, | |
| 483 | + const struct drm_connector_funcs *funcs, | |
| 484 | + const struct drm_connector_hdmi_funcs *hdmi_funcs, | |
| 485 | + int connector_type, | |
| 486 | + struct i2c_adapter *ddc, | |
| 487 | + unsigned long supported_formats, | |
| 488 | + unsigned int max_bpc) | |
| 489 | +{ | |
| 490 | + int ret; | |
| 491 | + | |
| 492 | + if (!vendor || !product) | |
| 493 | + return -EINVAL; | |
| 494 | + | |
| 495 | + if ((strlen(vendor) > DRM_CONNECTOR_HDMI_VENDOR_LEN) || | |
| 496 | + (strlen(product) > DRM_CONNECTOR_HDMI_PRODUCT_LEN)) | |
| 497 | + return -EINVAL; | |
| 498 | + | |
| 499 | + if (!(connector_type == DRM_MODE_CONNECTOR_HDMIA || | |
| 500 | + connector_type == DRM_MODE_CONNECTOR_HDMIB)) | |
| 501 | + return -EINVAL; | |
| 502 | + | |
| 503 | + if (!supported_formats || !(supported_formats & BIT(HDMI_COLORSPACE_RGB))) | |
| 504 | + return -EINVAL; | |
| 505 | + | |
| 506 | + if (!(max_bpc == 8 || max_bpc == 10 || max_bpc == 12)) | |
| 507 | + return -EINVAL; | |
| 508 | + | |
| 509 | + ret = drmm_connector_init(dev, connector, funcs, connector_type, ddc); | |
| 510 | + if (ret) | |
| 511 | + return ret; | |
| 512 | + | |
| 513 | + connector->hdmi.supported_formats = supported_formats; | |
| 514 | + strtomem_pad(connector->hdmi.vendor, vendor, 0); | |
| 515 | + strtomem_pad(connector->hdmi.product, product, 0); | |
| 516 | + | |
| 517 | + /* | |
| 518 | + * drm_connector_attach_max_bpc_property() requires the | |
| 519 | + * connector to have a state. | |
| 520 | + */ | |
| 521 | + if (connector->funcs->reset) | |
| 522 | + connector->funcs->reset(connector); | |
| 523 | + | |
| 524 | + drm_connector_attach_max_bpc_property(connector, 8, max_bpc); | |
| 525 | + connector->max_bpc = max_bpc; | |
| 526 | + | |
| 527 | + if (max_bpc > 8) | |
| 528 | + drm_connector_attach_hdr_output_metadata_property(connector); | |
| 529 | + | |
| 530 | + connector->hdmi.funcs = hdmi_funcs; | |
| 531 | + | |
| 532 | + return 0; | |
| 533 | +} | |
| 534 | +EXPORT_SYMBOL(drmm_connector_hdmi_init); | |
| 535 | + | |
| 455 | 536 | /** |
| 456 | 537 | * drm_connector_attach_edid_property - attach edid property. |
| 457 | 538 | * @connector: the connector |
| @@ -584,6 +665,7 @@ void drm_connector_cleanup(struct drm_connector *connector) · 126 unmodified lines | ||
| 584 | 665 | connector->funcs->atomic_destroy_state(connector, |
| 585 | 666 | connector->state); |
| 586 | 667 | |
| 668 | + mutex_destroy(&connector->hdmi.infoframes.lock); | |
| 587 | 669 | mutex_destroy(&connector->mutex); |
| 588 | 670 | |
| 589 | 671 | memset(connector, 0, sizeof(*connector)); |
| @@ -1005,6 +1087,7 @@ static const struct drm_prop_enum_list drm_tv_mode_enum_list[] = { · 415 unmodified lines | ||
| 1005 | 1087 | { DRM_MODE_TV_MODE_PAL_M, "PAL-M" }, |
| 1006 | 1088 | { DRM_MODE_TV_MODE_PAL_N, "PAL-N" }, |
| 1007 | 1089 | { DRM_MODE_TV_MODE_SECAM, "SECAM" }, |
| 1090 | + { DRM_MODE_TV_MODE_MONOCHROME, "Mono" }, | |
| 1008 | 1091 | }; |
| 1009 | 1092 | DRM_ENUM_NAME_FN(drm_get_tv_mode_name, drm_tv_mode_enum_list) |
| 1010 | 1093 | |
| @@ -1144,6 +1227,53 @@ static const u32 dp_colorspaces = · 133 unmodified lines | ||
| 1144 | 1227 | BIT(DRM_MODE_COLORIMETRY_BT2020_CYCC) | |
| 1145 | 1228 | BIT(DRM_MODE_COLORIMETRY_BT2020_YCC); |
| 1146 | 1229 | |
| 1230 | +static const struct drm_prop_enum_list broadcast_rgb_names[] = { | |
| 1231 | + { DRM_HDMI_BROADCAST_RGB_AUTO, "Automatic" }, | |
| 1232 | + { DRM_HDMI_BROADCAST_RGB_FULL, "Full" }, | |
| 1233 | + { DRM_HDMI_BROADCAST_RGB_LIMITED, "Limited 16:235" }, | |
| 1234 | +}; | |
| 1235 | + | |
| 1236 | +/* | |
| 1237 | + * drm_hdmi_connector_get_broadcast_rgb_name - Return a string for HDMI connector RGB broadcast selection | |
| 1238 | + * @broadcast_rgb: Broadcast RGB selection to compute name of | |
| 1239 | + * | |
| 1240 | + * Returns: the name of the Broadcast RGB selection, or NULL if the type | |
| 1241 | + * is not valid. | |
| 1242 | + */ | |
| 1243 | +const char * | |
| 1244 | +drm_hdmi_connector_get_broadcast_rgb_name(enum drm_hdmi_broadcast_rgb broadcast_rgb) | |
| 1245 | +{ | |
| 1246 | + if (broadcast_rgb >= ARRAY_SIZE(broadcast_rgb_names)) | |
| 1247 | + return NULL; | |
| 1248 | + | |
| 1249 | + return broadcast_rgb_names[broadcast_rgb].name; | |
| 1250 | +} | |
| 1251 | +EXPORT_SYMBOL(drm_hdmi_connector_get_broadcast_rgb_name); | |
| 1252 | + | |
| 1253 | +static const char * const output_format_str[] = { | |
| 1254 | + [HDMI_COLORSPACE_RGB] = "RGB", | |
| 1255 | + [HDMI_COLORSPACE_YUV420] = "YUV 4:2:0", | |
| 1256 | + [HDMI_COLORSPACE_YUV422] = "YUV 4:2:2", | |
| 1257 | + [HDMI_COLORSPACE_YUV444] = "YUV 4:4:4", | |
| 1258 | +}; | |
| 1259 | + | |
| 1260 | +/* | |
| 1261 | + * drm_hdmi_connector_get_output_format_name() - Return a string for HDMI connector output format | |
| 1262 | + * @fmt: Output format to compute name of | |
| 1263 | + * | |
| 1264 | + * Returns: the name of the output format, or NULL if the type is not | |
| 1265 | + * valid. | |
| 1266 | + */ | |
| 1267 | +const char * | |
| 1268 | +drm_hdmi_connector_get_output_format_name(enum hdmi_colorspace fmt) | |
| 1269 | +{ | |
| 1270 | + if (fmt >= ARRAY_SIZE(output_format_str)) | |
| 1271 | + return NULL; | |
| 1272 | + | |
| 1273 | + return output_format_str[fmt]; | |
| 1274 | +} | |
| 1275 | +EXPORT_SYMBOL(drm_hdmi_connector_get_output_format_name); | |
| 1276 | + | |
| 1147 | 1277 | /** |
| 1148 | 1278 | * DOC: standard connector properties |
| 1149 | 1279 | * |
| @@ -1616,6 +1746,38 @@ EXPORT_SYMBOL(drm_connector_attach_dp_subconnector_property); · 466 unmodified lines | ||
| 1616 | 1746 | /** |
| 1617 | 1747 | * DOC: HDMI connector properties |
| 1618 | 1748 | * |
| 1749 | + * Broadcast RGB (HDMI specific) | |
| 1750 | + * Indicates the Quantization Range (Full vs Limited) used. The color | |
| 1751 | + * processing pipeline will be adjusted to match the value of the | |
| 1752 | + * property, and the Infoframes will be generated and sent accordingly. | |
| 1753 | + * | |
| 1754 | + * This property is only relevant if the HDMI output format is RGB. If | |
| 1755 | + * it's one of the YCbCr variant, it will be ignored. | |
| 1756 | + * | |
| 1757 | + * The CRTC attached to the connector must be configured by user-space to | |
| 1758 | + * always produce full-range pixels. | |
| 1759 | + * | |
| 1760 | + * The value of this property can be one of the following: | |
| 1761 | + * | |
| 1762 | + * Automatic: | |
| 1763 | + * The quantization range is selected automatically based on the | |
| 1764 | + * mode according to the HDMI specifications (HDMI 1.4b - Section | |
| 1765 | + * 6.6 - Video Quantization Ranges). | |
| 1766 | + * | |
| 1767 | + * Full: | |
| 1768 | + * Full quantization range is forced. | |
| 1769 | + * | |
| 1770 | + * Limited 16:235: | |
| 1771 | + * Limited quantization range is forced. Unlike the name suggests, | |
| 1772 | + * this works for any number of bits-per-component. | |
| 1773 | + * | |
| 1774 | + * Property values other than Automatic can result in colors being off (if | |
| 1775 | + * limited is selected but the display expects full), or a black screen | |
| 1776 | + * (if full is selected but the display expects limited). | |
| 1777 | + * | |
| 1778 | + * Drivers can set up this property by calling | |
| 1779 | + * drm_connector_attach_broadcast_rgb_property(). | |
| 1780 | + * | |
| 1619 | 1781 | * content type (HDMI specific): |
| 1620 | 1782 | * Indicates content type setting to be used in HDMI infoframes to indicate |
| 1621 | 1783 | * content type for the external device, so that it adjusts its display |
| @@ -1697,6 +1859,12 @@ EXPORT_SYMBOL(drm_connector_attach_dp_subconnector_property); · 75 unmodified lines | ||
| 1697 | 1859 | * TV Mode is CCIR System B (aka 625-lines) together with |
| 1698 | 1860 | * the SECAM Color Encoding. |
| 1699 | 1861 | * |
| 1862 | + * Mono: | |
| 1863 | + * | |
| 1864 | + * Use timings appropriate to the DRM mode, including | |
| 1865 | + * equalizing pulses for a 525-line or 625-line mode, | |
| 1866 | + * with no pedestal or color encoding. | |
| 1867 | + * | |
| 1700 | 1868 | * Drivers can set up this property by calling |
| 1701 | 1869 | * drm_mode_create_tv_properties(). |
| 1702 | 1870 | */ |
| @@ -2478,6 +2646,39 @@ int drm_connector_attach_hdr_output_metadata_property(struct drm_connector *conn · 775 unmodified lines | ||
| 2478 | 2646 | } |
| 2479 | 2647 | EXPORT_SYMBOL(drm_connector_attach_hdr_output_metadata_property); |
| 2480 | 2648 | |
| 2649 | +/** | |
| 2650 | + * drm_connector_attach_broadcast_rgb_property - attach "Broadcast RGB" property | |
| 2651 | + * @connector: connector to attach the property on. | |
| 2652 | + * | |
| 2653 | + * This is used to add support for forcing the RGB range on a connector | |
| 2654 | + * | |
| 2655 | + * Returns: | |
| 2656 | + * Zero on success, negative errno on failure. | |
| 2657 | + */ | |
| 2658 | +int drm_connector_attach_broadcast_rgb_property(struct drm_connector *connector) | |
| 2659 | +{ | |
| 2660 | + struct drm_device *dev = connector->dev; | |
| 2661 | + struct drm_property *prop; | |
| 2662 | + | |
| 2663 | + prop = connector->broadcast_rgb_property; | |
| 2664 | + if (!prop) { | |
| 2665 | + prop = drm_property_create_enum(dev, DRM_MODE_PROP_ENUM, | |
| 2666 | + "Broadcast RGB", | |
| 2667 | + broadcast_rgb_names, | |
| 2668 | + ARRAY_SIZE(broadcast_rgb_names)); | |
| 2669 | + if (!prop) | |
| 2670 | + return -EINVAL; | |
| 2671 | + | |
| 2672 | + connector->broadcast_rgb_property = prop; | |
| 2673 | + } | |
| 2674 | + | |
| 2675 | + drm_object_attach_property(&connector->base, prop, | |
| 2676 | + DRM_HDMI_BROADCAST_RGB_AUTO); | |
| 2677 | + | |
| 2678 | + return 0; | |
| 2679 | +} | |
| 2680 | +EXPORT_SYMBOL(drm_connector_attach_broadcast_rgb_property); | |
| 2681 | + | |
| 2481 | 2682 | /** |
| 2482 | 2683 | * drm_connector_attach_colorspace_property - attach "Colorspace" property |
| 2483 | 2684 | * @connector: connector to attach the property on. |
| @@ -303,6 +303,8 @@ const u8 *drm_edid_find_extension(const struct drm_edid *drm_edid, · 302 unmodified lines | ||
| 303 | 303 | int ext_id, int *ext_index); |
| 304 | 304 | void drm_edid_cta_sad_get(const struct cea_sad *cta_sad, u8 *sad); |
| 305 | 305 | void drm_edid_cta_sad_set(struct cea_sad *cta_sad, const u8 *sad); |
| 306 | +ssize_t drm_edid_connector_property_show(struct drm_connector *connector, | |
| 307 | + char *buf, loff_t off, size_t count); | |
| 306 | 308 | |
| 307 | 309 | /* drm_edid_load.c */ |
| 308 | 310 | #ifdef CONFIG_DRM_LOAD_EDID_FIRMWARE |
| @@ -520,6 +520,156 @@ static const struct file_operations drm_connector_fops = { · 519 unmodified lines | ||
| 520 | 520 | .write = connector_write |
| 521 | 521 | }; |
| 522 | 522 | |
| 523 | +#define HDMI_MAX_INFOFRAME_SIZE 29 | |
| 524 | + | |
| 525 | +static ssize_t | |
| 526 | +audio_infoframe_read(struct file *filp, char __user *ubuf, size_t count, loff_t *ppos) | |
| 527 | +{ | |
| 528 | + struct drm_connector_hdmi_infoframe *infoframe; | |
| 529 | + struct drm_connector *connector; | |
| 530 | + union hdmi_infoframe *frame; | |
| 531 | + u8 buf[HDMI_INFOFRAME_SIZE(AUDIO)]; | |
| 532 | + ssize_t len = 0; | |
| 533 | + | |
| 534 | + connector = filp->private_data; | |
| 535 | + mutex_lock(&connector->hdmi.infoframes.lock); | |
| 536 | + | |
| 537 | + infoframe = &connector->hdmi.infoframes.audio; | |
| 538 | + if (!infoframe->set) | |
| 539 | + goto out; | |
| 540 | + | |
| 541 | + frame = &infoframe->data; | |
| 542 | + len = hdmi_infoframe_pack(frame, buf, sizeof(buf)); | |
| 543 | + if (len < 0) | |
| 544 | + goto out; | |
| 545 | + | |
| 546 | + len = simple_read_from_buffer(ubuf, count, ppos, buf, len); | |
| 547 | + | |
| 548 | +out: | |
| 549 | + mutex_unlock(&connector->hdmi.infoframes.lock); | |
| 550 | + return len; | |
| 551 | +} | |
| 552 | + | |
| 553 | +static const struct file_operations audio_infoframe_fops = { | |
| 554 | + .owner = THIS_MODULE, | |
| 555 | + .open = simple_open, | |
| 556 | + .read = audio_infoframe_read, | |
| 557 | +}; | |
| 558 | + | |
| 559 | +static int create_hdmi_audio_infoframe_file(struct drm_connector *connector, | |
| 560 | + struct dentry *parent) | |
| 561 | +{ | |
| 562 | + struct dentry *file; | |
| 563 | + | |
| 564 | + file = debugfs_create_file("audio", 0400, parent, connector, &audio_infoframe_fops); | |
| 565 | + if (IS_ERR(file)) | |
| 566 | + return PTR_ERR(file); | |
| 567 | + | |
| 568 | + return 0; | |
| 569 | +} | |
| 570 | + | |
| 571 | +#define DEFINE_INFOFRAME_FILE(_f) \ | |
| 572 | +static ssize_t _f##_read_infoframe(struct file *filp, \ | |
| 573 | + char __user *ubuf, \ | |
| 574 | + size_t count, \ | |
| 575 | + loff_t *ppos) \ | |
| 576 | +{ \ | |
| 577 | + struct drm_connector_hdmi_infoframe *infoframe; \ | |
| 578 | + struct drm_connector_state *conn_state; \ | |
| 579 | + struct drm_connector *connector; \ | |
| 580 | + union hdmi_infoframe *frame; \ | |
| 581 | + struct drm_device *dev; \ | |
| 582 | + u8 buf[HDMI_MAX_INFOFRAME_SIZE]; \ | |
| 583 | + ssize_t len = 0; \ | |
| 584 | + \ | |
| 585 | + connector = filp->private_data; \ | |
| 586 | + dev = connector->dev; \ | |
| 587 | + \ | |
| 588 | + drm_modeset_lock(&dev->mode_config.connection_mutex, NULL); \ | |
| 589 | + \ | |
| 590 | + conn_state = connector->state; \ | |
| 591 | + infoframe = &conn_state->hdmi.infoframes._f; \ | |
| 592 | + if (!infoframe->set) \ | |
| 593 | + goto out; \ | |
| 594 | + \ | |
| 595 | + frame = &infoframe->data; \ | |
| 596 | + len = hdmi_infoframe_pack(frame, buf, sizeof(buf)); \ | |
| 597 | + if (len < 0) \ | |
| 598 | + goto out; \ | |
| 599 | + \ | |
| 600 | + len = simple_read_from_buffer(ubuf, count, ppos, buf, len); \ | |
| 601 | + \ | |
| 602 | +out: \ | |
| 603 | + drm_modeset_unlock(&dev->mode_config.connection_mutex); \ | |
| 604 | + return len; \ | |
| 605 | +} \ | |
| 606 | +\ | |
| 607 | +static const struct file_operations _f##_infoframe_fops = { \ | |
| 608 | + .owner = THIS_MODULE, \ | |
| 609 | + .open = simple_open, \ | |
| 610 | + .read = _f##_read_infoframe, \ | |
| 611 | +}; \ | |
| 612 | +\ | |
| 613 | +static int create_hdmi_## _f ## _infoframe_file(struct drm_connector *connector, \ | |
| 614 | + struct dentry *parent) \ | |
| 615 | +{ \ | |
| 616 | + struct dentry *file; \ | |
| 617 | + \ | |
| 618 | + file = debugfs_create_file(#_f, 0400, parent, connector, &_f ## _infoframe_fops); \ | |
| 619 | + if (IS_ERR(file)) \ | |
| 620 | + return PTR_ERR(file); \ | |
| 621 | + \ | |
| 622 | + return 0; \ | |
| 623 | +} | |
| 624 | + | |
| 625 | +DEFINE_INFOFRAME_FILE(avi); | |
| 626 | +DEFINE_INFOFRAME_FILE(hdmi); | |
| 627 | +DEFINE_INFOFRAME_FILE(hdr_drm); | |
| 628 | +DEFINE_INFOFRAME_FILE(spd); | |
| 629 | + | |
| 630 | +static int create_hdmi_infoframe_files(struct drm_connector *connector, | |
| 631 | + struct dentry *parent) | |
| 632 | +{ | |
| 633 | + int ret; | |
| 634 | + | |
| 635 | + ret = create_hdmi_audio_infoframe_file(connector, parent); | |
| 636 | + if (ret) | |
| 637 | + return ret; | |
| 638 | + | |
| 639 | + ret = create_hdmi_avi_infoframe_file(connector, parent); | |
| 640 | + if (ret) | |
| 641 | + return ret; | |
| 642 | + | |
| 643 | + ret = create_hdmi_hdmi_infoframe_file(connector, parent); | |
| 644 | + if (ret) | |
| 645 | + return ret; | |
| 646 | + | |
| 647 | + ret = create_hdmi_hdr_drm_infoframe_file(connector, parent); | |
| 648 | + if (ret) | |
| 649 | + return ret; | |
| 650 | + | |
| 651 | + ret = create_hdmi_spd_infoframe_file(connector, parent); | |
| 652 | + if (ret) | |
| 653 | + return ret; | |
| 654 | + | |
| 655 | + return 0; | |
| 656 | +} | |
| 657 | + | |
| 658 | +static void hdmi_debugfs_add(struct drm_connector *connector) | |
| 659 | +{ | |
| 660 | + struct dentry *dir; | |
| 661 | + | |
| 662 | + if (!(connector->connector_type == DRM_MODE_CONNECTOR_HDMIA || | |
| 663 | + connector->connector_type == DRM_MODE_CONNECTOR_HDMIB)) | |
| 664 | + return; | |
| 665 | + | |
| 666 | + dir = debugfs_create_dir("infoframes", connector->debugfs_entry); | |
| 667 | + if (IS_ERR(dir)) | |
| 668 | + return; | |
| 669 | + | |
| 670 | + create_hdmi_infoframe_files(connector, dir); | |
| 671 | +} | |
| 672 | + | |
| 523 | 673 | void drm_debugfs_connector_add(struct drm_connector *connector) |
| 524 | 674 | { |
| 525 | 675 | struct drm_device *dev = connector->dev; |
| @@ -547,6 +697,8 @@ void drm_debugfs_connector_add(struct drm_connector *connector) · 21 unmodified lines | ||
| 547 | 697 | debugfs_create_file("output_bpc", 0444, root, connector, |
| 548 | 698 | &output_bpc_fops); |
| 549 | 699 | |
| 700 | + hdmi_debugfs_add(connector); | |
| 701 | + | |
| 550 | 702 | if (connector->funcs->debugfs_init) |
| 551 | 703 | connector->funcs->debugfs_init(connector, root); |
| 552 | 704 | } |
| @@ -597,10 +749,10 @@ static int bridges_show(struct seq_file *m, void *data) · 44 unmodified lines | ||
| 597 | 749 | drm_printf(&p, "\ttype: [%d] %s\n", |
| 598 | 750 | bridge->type, |
| 599 | 751 | drm_get_connector_type_name(bridge->type)); |
| 600 | −#ifdef CONFIG_OF | |
| 752 | + | |
| 601 | 753 | if (bridge->of_node) |
| 602 | 754 | drm_printf(&p, "\tOF: %pOFfc\n", bridge->of_node); |
| 603 | −#endif | |
| 755 | + | |
| 604 | 756 | drm_printf(&p, "\tops: [0x%x]", bridge->ops); |
| 605 | 757 | if (bridge->ops & DRM_BRIDGE_OP_DETECT) |
| 606 | 758 | drm_puts(&p, " detect"); |
| @@ -610,6 +762,8 @@ static int bridges_show(struct seq_file *m, void *data) · 3 unmodified lines | ||
| 610 | 762 | drm_puts(&p, " hpd"); |
| 611 | 763 | if (bridge->ops & DRM_BRIDGE_OP_MODES) |
| 612 | 764 | drm_puts(&p, " modes"); |
| 765 | + if (bridge->ops & DRM_BRIDGE_OP_HDMI) | |
| 766 | + drm_puts(&p, " hdmi"); | |
| 613 | 767 | drm_puts(&p, "\n"); |
| 614 | 768 | } |
| 615 | 769 | |
| @@ -346,7 +346,7 @@ void drm_minor_release(struct drm_minor *minor) · 345 unmodified lines | ||
| 346 | 346 | * if (ret) |
| 347 | 347 | * return ret; |
| 348 | 348 | * |
| 349 | − * drm_fbdev_generic_setup(drm, 32); | |
| 349 | + * drm_fbdev_{...}_setup(drm, 32); | |
| 350 | 350 | * |
| 351 | 351 | * return 0; |
| 352 | 352 | * } |
| @@ -947,9 +947,9 @@ int drm_dev_register(struct drm_device *dev, unsigned long flags) · 594 unmodified lines | ||
| 947 | 947 | } |
| 948 | 948 | drm_panic_register(dev); |
| 949 | 949 | |
| 950 | − DRM_INFO("Initialized %s %d.%d.%d %s for %s on minor %d\n", | |
| 950 | + DRM_INFO("Initialized %s %d.%d.%d for %s on minor %d\n", | |
| 951 | 951 | driver->name, driver->major, driver->minor, |
| 952 | − driver->patchlevel, driver->date, | |
| 952 | + driver->patchlevel, | |
| 953 | 953 | dev->dev ? dev_name(dev->dev) : "virtual device", |
| 954 | 954 | dev->primary ? dev->primary->index : dev->accel->index); |
| 955 | 955 | |
| @@ -2464,34 +2464,6 @@ fail: · 2463 unmodified lines | ||
| 2464 | 2464 | return NULL; |
| 2465 | 2465 | } |
| 2466 | 2466 | |
| 2467 | −/** | |
| 2468 | − * drm_do_get_edid - get EDID data using a custom EDID block read function | |
| 2469 | − * @connector: connector we're probing | |
| 2470 | − * @read_block: EDID block read function | |
| 2471 | − * @context: private data passed to the block read function | |
| 2472 | − * | |
| 2473 | − * When the I2C adapter connected to the DDC bus is hidden behind a device that | |
| 2474 | − * exposes a different interface to read EDID blocks this function can be used | |
| 2475 | − * to get EDID data using a custom block read function. | |
| 2476 | − * | |
| 2477 | − * As in the general case the DDC bus is accessible by the kernel at the I2C | |
| 2478 | − * level, drivers must make all reasonable efforts to expose it as an I2C | |
| 2479 | − * adapter and use drm_get_edid() instead of abusing this function. | |
| 2480 | − * | |
| 2481 | − * The EDID may be overridden using debugfs override_edid or firmware EDID | |
| 2482 | − * (drm_edid_load_firmware() and drm.edid_firmware parameter), in this priority | |
| 2483 | − * order. Having either of them bypasses actual EDID reads. | |
| 2484 | − * | |
| 2485 | − * Return: Pointer to valid EDID or NULL if we couldn't find any. | |
| 2486 | − */ | |
| 2487 | −struct edid *drm_do_get_edid(struct drm_connector *connector, | |
| 2488 | − read_block_fn read_block, | |
| 2489 | − void *context) | |
| 2490 | −{ | |
| 2491 | − return _drm_do_get_edid(connector, read_block, context, NULL); | |
| 2492 | −} | |
| 2493 | −EXPORT_SYMBOL_GPL(drm_do_get_edid); | |
| 2494 | − | |
| 2495 | 2467 | /** |
| 2496 | 2468 | * drm_edid_raw - Get a pointer to the raw EDID data. |
| 2497 | 2469 | * @drm_edid: drm_edid container |
| @@ -6969,6 +6941,39 @@ out: · 4471 unmodified lines | ||
| 6969 | 6941 | return ret; |
| 6970 | 6942 | } |
| 6971 | 6943 | |
| 6944 | +/* For sysfs edid show implementation */ | |
| 6945 | +ssize_t drm_edid_connector_property_show(struct drm_connector *connector, | |
| 6946 | + char *buf, loff_t off, size_t count) | |
| 6947 | +{ | |
| 6948 | + const void *edid; | |
| 6949 | + size_t size; | |
| 6950 | + ssize_t ret = 0; | |
| 6951 | + | |
| 6952 | + mutex_lock(&connector->dev->mode_config.mutex); | |
| 6953 | + | |
| 6954 | + if (!connector->edid_blob_ptr) | |
| 6955 | + goto unlock; | |
| 6956 | + | |
| 6957 | + edid = connector->edid_blob_ptr->data; | |
| 6958 | + size = connector->edid_blob_ptr->length; | |
| 6959 | + if (!edid) | |
| 6960 | + goto unlock; | |
| 6961 | + | |
| 6962 | + if (off >= size) | |
| 6963 | + goto unlock; | |
| 6964 | + | |
| 6965 | + if (off + count > size) | |
| 6966 | + count = size - off; | |
| 6967 | + | |
| 6968 | + memcpy(buf, edid + off, count); | |
| 6969 | + | |
| 6970 | + ret = count; | |
| 6971 | +unlock: | |
| 6972 | + mutex_unlock(&connector->dev->mode_config.mutex); | |
| 6973 | + | |
| 6974 | + return ret; | |
| 6975 | +} | |
| 6976 | + | |
| 6972 | 6977 | /** |
| 6973 | 6978 | * drm_edid_connector_update - Update connector information from EDID |
| 6974 | 6979 | * @connector: Connector |
| @@ -85,12 +85,8 @@ static DEFINE_MUTEX(kernel_fb_helper_lock); · 84 unmodified lines | ||
| 85 | 85 | * The fb helper functions are useful to provide an fbdev on top of a drm kernel |
| 86 | 86 | * mode setting driver. They can be used mostly independently from the crtc |
| 87 | 87 | * helper functions used by many drivers to implement the kernel mode setting |
| 88 | − * interfaces. | |
| 89 | − * | |
| 90 | − * Drivers that support a dumb buffer with a virtual address and mmap support, | |
| 91 | − * should try out the generic fbdev emulation using drm_fbdev_generic_setup(). | |
| 92 | − * It will automatically set up deferred I/O if the driver requires a shadow | |
| 93 | − * buffer. | |
| 88 | + * interfaces. Drivers that use one of the shared memory managers, TTM, SHMEM, | |
| 89 | + * DMA, should instead use the corresponding fbdev emulation. | |
| 94 | 90 | * |
| 95 | 91 | * Existing fbdev implementations should restore the fbdev console by using |
| 96 | 92 | * drm_fb_helper_lastclose() as their &drm_driver.lastclose callback. |
| @@ -126,9 +122,6 @@ static DEFINE_MUTEX(kernel_fb_helper_lock); · 29 unmodified lines | ||
| 126 | 122 | * atomic context. If drm_fb_helper_deferred_io() is used as the deferred_io |
| 127 | 123 | * callback it will also schedule dirty_work with the damage collected from the |
| 128 | 124 | * mmap page writes. |
| 129 | − * | |
| 130 | − * Deferred I/O is not compatible with SHMEM. Such drivers should request an | |
| 131 | − * fbdev shadow buffer and call drm_fbdev_generic_setup() instead. | |
| 132 | 125 | */ |
| 133 | 126 | |
| 134 | 127 | static void drm_fb_helper_restore_lut_atomic(struct drm_crtc *crtc) |
| @@ -4,6 +4,7 @@ · 3 unmodified lines | ||
| 4 | 4 | |
| 5 | 5 | #include <drm/drm_crtc_helper.h> |
| 6 | 6 | #include <drm/drm_drv.h> |
| 7 | +#include <drm/drm_fb_dma_helper.h> | |
| 7 | 8 | #include <drm/drm_fb_helper.h> |
| 8 | 9 | #include <drm/drm_framebuffer.h> |
| 9 | 10 | #include <drm/drm_gem_dma_helper.h> |
| @@ -35,6 +36,22 @@ static int drm_fbdev_dma_fb_release(struct fb_info *info, int user) · 25 unmodified lines | ||
| 35 | 36 | return 0; |
| 36 | 37 | } |
| 37 | 38 | |
| 39 | +FB_GEN_DEFAULT_DEFERRED_DMAMEM_OPS(drm_fbdev_dma, | |
| 40 | + drm_fb_helper_damage_range, | |
| 41 | + drm_fb_helper_damage_area); | |
| 42 | + | |
| 43 | +static int drm_fbdev_dma_fb_mmap(struct fb_info *info, struct vm_area_struct *vma) | |
| 44 | +{ | |
| 45 | + struct drm_fb_helper *fb_helper = info->par; | |
| 46 | + struct drm_framebuffer *fb = fb_helper->fb; | |
| 47 | + struct drm_gem_dma_object *dma = drm_fb_dma_get_gem_obj(fb, 0); | |
| 48 | + | |
| 49 | + if (!dma->map_noncoherent) | |
| 50 | + vma->vm_page_prot = pgprot_writecombine(vma->vm_page_prot); | |
| 51 | + | |
| 52 | + return fb_deferred_io_mmap(info, vma); | |
| 53 | +} | |
| 54 | + | |
| 38 | 55 | static void drm_fbdev_dma_fb_destroy(struct fb_info *info) |
| 39 | 56 | { |
| 40 | 57 | struct drm_fb_helper *fb_helper = info->par; |
| @@ -42,6 +59,7 @@ static void drm_fbdev_dma_fb_destroy(struct fb_info *info) · 1 unmodified line | ||
| 42 | 59 | if (!fb_helper->dev) |
| 43 | 60 | return; |
| 44 | 61 | |
| 62 | + fb_deferred_io_cleanup(info); | |
| 45 | 63 | drm_fb_helper_fini(fb_helper); |
| 46 | 64 | |
| 47 | 65 | drm_client_buffer_vunmap(fb_helper->buffer); |
| @@ -51,20 +69,13 @@ static void drm_fbdev_dma_fb_destroy(struct fb_info *info) · 3 unmodified lines | ||
| 51 | 69 | kfree(fb_helper); |
| 52 | 70 | } |
| 53 | 71 | |
| 54 | −static int drm_fbdev_dma_fb_mmap(struct fb_info *info, struct vm_area_struct *vma) | |
| 55 | −{ | |
| 56 | − struct drm_fb_helper *fb_helper = info->par; | |
| 57 | − | |
| 58 | − return drm_gem_prime_mmap(fb_helper->buffer->gem, vma); | |
| 59 | −} | |
| 60 | − | |
| 61 | 72 | static const struct fb_ops drm_fbdev_dma_fb_ops = { |
| 62 | 73 | .owner = THIS_MODULE, |
| 63 | 74 | .fb_open = drm_fbdev_dma_fb_open, |
| 64 | 75 | .fb_release = drm_fbdev_dma_fb_release, |
| 65 | − __FB_DEFAULT_DMAMEM_OPS_RDWR, | |
| 76 | + __FB_DEFAULT_DEFERRED_OPS_RDWR(drm_fbdev_dma), | |
| 66 | 77 | DRM_FB_HELPER_DEFAULT_OPS, |
| 67 | − __FB_DEFAULT_DMAMEM_OPS_DRAW, | |
| 78 | + __FB_DEFAULT_DEFERRED_OPS_DRAW(drm_fbdev_dma), | |
| 68 | 79 | .fb_mmap = drm_fbdev_dma_fb_mmap, |
| 69 | 80 | .fb_destroy = drm_fbdev_dma_fb_destroy, |
| 70 | 81 | }; |
| @@ -98,10 +109,6 @@ static int drm_fbdev_dma_helper_fb_probe(struct drm_fb_helper *fb_helper, · 27 unmodified lines | ||
| 98 | 109 | dma_obj = to_drm_gem_dma_obj(buffer->gem); |
| 99 | 110 | |
| 100 | 111 | fb = buffer->fb; |
| 101 | − if (drm_WARN_ON(dev, fb->funcs->dirty)) { | |
| 102 | − ret = -ENODEV; /* damage handling not supported; use generic emulation */ | |
| 103 | − goto err_drm_client_buffer_delete; | |
| 104 | − } | |
| 105 | 112 | |
| 106 | 113 | ret = drm_client_buffer_vmap(buffer, &map); |
| 107 | 114 | if (ret) { |
| @@ -112,7 +119,7 @@ static int drm_fbdev_dma_helper_fb_probe(struct drm_fb_helper *fb_helper, · 4 unmodified lines | ||
| 112 | 119 | } |
| 113 | 120 | |
| 114 | 121 | fb_helper->buffer = buffer; |
| 115 | − fb_helper->fb = buffer->fb; | |
| 122 | + fb_helper->fb = fb; | |
| 116 | 123 | |
| 117 | 124 | info = drm_fb_helper_alloc_info(fb_helper); |
| 118 | 125 | if (IS_ERR(info)) { |
| @@ -133,8 +140,19 @@ static int drm_fbdev_dma_helper_fb_probe(struct drm_fb_helper *fb_helper, · 14 unmodified lines | ||
| 133 | 140 | info->fix.smem_start = page_to_phys(virt_to_page(info->screen_buffer)); |
| 134 | 141 | info->fix.smem_len = info->screen_size; |
| 135 | 142 | |
| 143 | + /* deferred I/O */ | |
| 144 | + fb_helper->fbdefio.delay = HZ / 20; | |
| 145 | + fb_helper->fbdefio.deferred_io = drm_fb_helper_deferred_io; | |
| 146 | + | |
| 147 | + info->fbdefio = &fb_helper->fbdefio; | |
| 148 | + ret = fb_deferred_io_init(info); | |
| 149 | + if (ret) | |
| 150 | + goto err_drm_fb_helper_release_info; | |
| 151 | + | |
| 136 | 152 | return 0; |
| 137 | 153 | |
| 154 | +err_drm_fb_helper_release_info: | |
| 155 | + drm_fb_helper_release_info(fb_helper); | |
| 138 | 156 | err_drm_client_buffer_vunmap: |
| 139 | 157 | fb_helper->fb = NULL; |
| 140 | 158 | fb_helper->buffer = NULL; |
| @@ -144,8 +162,28 @@ err_drm_client_buffer_delete: · 3 unmodified lines | ||
| 144 | 162 | return ret; |
| 145 | 163 | } |
| 146 | 164 | |
| 165 | +static int drm_fbdev_dma_helper_fb_dirty(struct drm_fb_helper *helper, | |
| 166 | + struct drm_clip_rect *clip) | |
| 167 | +{ | |
| 168 | + struct drm_device *dev = helper->dev; | |
| 169 | + int ret; | |
| 170 | + | |
| 171 | + /* Call damage handlers only if necessary */ | |
| 172 | + if (!(clip->x1 < clip->x2 && clip->y1 < clip->y2)) | |
| 173 | + return 0; | |
| 174 | + | |
| 175 | + if (helper->fb->funcs->dirty) { | |
| 176 | + ret = helper->fb->funcs->dirty(helper->fb, NULL, 0, 0, clip, 1); | |
| 177 | + if (drm_WARN_ONCE(dev, ret, "Dirty helper failed: ret=%d\n", ret)) | |
| 178 | + return ret; | |
| 179 | + } | |
| 180 | + | |
| 181 | + return 0; | |
| 182 | +} | |
| 183 | + | |
| 147 | 184 | static const struct drm_fb_helper_funcs drm_fbdev_dma_helper_funcs = { |
| 148 | 185 | .fb_probe = drm_fbdev_dma_helper_fb_probe, |
| 186 | + .fb_dirty = drm_fbdev_dma_helper_fb_dirty, | |
| 149 | 187 | }; |
| 150 | 188 | |
| 151 | 189 | /* |
| @@ -0,0 +1,317 @@ | ||
| 1 | +// SPDX-License-Identifier: MIT | |
| 2 | + | |
| 3 | +#include <linux/fb.h> | |
| 4 | + | |
| 5 | +#include <drm/drm_crtc_helper.h> | |
| 6 | +#include <drm/drm_drv.h> | |
| 7 | +#include <drm/drm_fb_helper.h> | |
| 8 | +#include <drm/drm_framebuffer.h> | |
| 9 | +#include <drm/drm_gem_framebuffer_helper.h> | |
| 10 | +#include <drm/drm_gem_shmem_helper.h> | |
| 11 | + | |
| 12 | +#include <drm/drm_fbdev_shmem.h> | |
| 13 | + | |
| 14 | +/* | |
| 15 | + * struct fb_ops | |
| 16 | + */ | |
| 17 | + | |
| 18 | +static int drm_fbdev_shmem_fb_open(struct fb_info *info, int user) | |
| 19 | +{ | |
| 20 | + struct drm_fb_helper *fb_helper = info->par; | |
| 21 | + | |
| 22 | + /* No need to take a ref for fbcon because it unbinds on unregister */ | |
| 23 | + if (user && !try_module_get(fb_helper->dev->driver->fops->owner)) | |
| 24 | + return -ENODEV; | |
| 25 | + | |
| 26 | + return 0; | |
| 27 | +} | |
| 28 | + | |
| 29 | +static int drm_fbdev_shmem_fb_release(struct fb_info *info, int user) | |
| 30 | +{ | |
| 31 | + struct drm_fb_helper *fb_helper = info->par; | |
| 32 | + | |
| 33 | + if (user) | |
| 34 | + module_put(fb_helper->dev->driver->fops->owner); | |
| 35 | + | |
| 36 | + return 0; | |
| 37 | +} | |
| 38 | + | |
| 39 | +FB_GEN_DEFAULT_DEFERRED_SYSMEM_OPS(drm_fbdev_shmem, | |
| 40 | + drm_fb_helper_damage_range, | |
| 41 | + drm_fb_helper_damage_area); | |
| 42 | + | |
| 43 | +static int drm_fbdev_shmem_fb_mmap(struct fb_info *info, struct vm_area_struct *vma) | |
| 44 | +{ | |
| 45 | + struct drm_fb_helper *fb_helper = info->par; | |
| 46 | + struct drm_framebuffer *fb = fb_helper->fb; | |
| 47 | + struct drm_gem_object *obj = drm_gem_fb_get_obj(fb, 0); | |
| 48 | + struct drm_gem_shmem_object *shmem = to_drm_gem_shmem_obj(obj); | |
| 49 | + | |
| 50 | + if (shmem->map_wc) | |
| 51 | + vma->vm_page_prot = pgprot_writecombine(vma->vm_page_prot); | |
| 52 | + | |
| 53 | + return fb_deferred_io_mmap(info, vma); | |
| 54 | +} | |
| 55 | + | |
| 56 | +static void drm_fbdev_shmem_fb_destroy(struct fb_info *info) | |
| 57 | +{ | |
| 58 | + struct drm_fb_helper *fb_helper = info->par; | |
| 59 | + | |
| 60 | + if (!fb_helper->dev) | |
| 61 | + return; | |
| 62 | + | |
| 63 | + fb_deferred_io_cleanup(info); | |
| 64 | + drm_fb_helper_fini(fb_helper); | |
| 65 | + | |
| 66 | + drm_client_buffer_vunmap(fb_helper->buffer); | |
| 67 | + drm_client_framebuffer_delete(fb_helper->buffer); | |
| 68 | + drm_client_release(&fb_helper->client); | |
| 69 | + drm_fb_helper_unprepare(fb_helper); | |
| 70 | + kfree(fb_helper); | |
| 71 | +} | |
| 72 | + | |
| 73 | +static const struct fb_ops drm_fbdev_shmem_fb_ops = { | |
| 74 | + .owner = THIS_MODULE, | |
| 75 | + .fb_open = drm_fbdev_shmem_fb_open, | |
| 76 | + .fb_release = drm_fbdev_shmem_fb_release, | |
| 77 | + __FB_DEFAULT_DEFERRED_OPS_RDWR(drm_fbdev_shmem), | |
| 78 | + DRM_FB_HELPER_DEFAULT_OPS, | |
| 79 | + __FB_DEFAULT_DEFERRED_OPS_DRAW(drm_fbdev_shmem), | |
| 80 | + .fb_mmap = drm_fbdev_shmem_fb_mmap, | |
| 81 | + .fb_destroy = drm_fbdev_shmem_fb_destroy, | |
| 82 | +}; | |
| 83 | + | |
| 84 | +static struct page *drm_fbdev_shmem_get_page(struct fb_info *info, unsigned long offset) | |
| 85 | +{ | |
| 86 | + struct drm_fb_helper *fb_helper = info->par; | |
| 87 | + struct drm_framebuffer *fb = fb_helper->fb; | |
| 88 | + struct drm_gem_object *obj = drm_gem_fb_get_obj(fb, 0); | |
| 89 | + struct drm_gem_shmem_object *shmem = to_drm_gem_shmem_obj(obj); | |
| 90 | + unsigned int i = offset >> PAGE_SHIFT; | |
| 91 | + struct page *page; | |
| 92 | + | |
| 93 | + if (fb_WARN_ON_ONCE(info, offset > obj->size)) | |
| 94 | + return NULL; | |
| 95 | + | |
| 96 | + page = shmem->pages[i]; // protected by active vmap | |
| 97 | + if (page) | |
| 98 | + get_page(page); | |
| 99 | + fb_WARN_ON_ONCE(info, !page); | |
| 100 | + | |
| 101 | + return page; | |
| 102 | +} | |
| 103 | + | |
| 104 | +/* | |
| 105 | + * struct drm_fb_helper | |
| 106 | + */ | |
| 107 | + | |
| 108 | +static int drm_fbdev_shmem_helper_fb_probe(struct drm_fb_helper *fb_helper, | |
| 109 | + struct drm_fb_helper_surface_size *sizes) | |
| 110 | +{ | |
| 111 | + struct drm_client_dev *client = &fb_helper->client; | |
| 112 | + struct drm_device *dev = fb_helper->dev; | |
| 113 | + struct drm_client_buffer *buffer; | |
| 114 | + struct drm_gem_shmem_object *shmem; | |
| 115 | + struct drm_framebuffer *fb; | |
| 116 | + struct fb_info *info; | |
| 117 | + u32 format; | |
| 118 | + struct iosys_map map; | |
| 119 | + int ret; | |
| 120 | + | |
| 121 | + drm_dbg_kms(dev, "surface width(%d), height(%d) and bpp(%d)\n", | |
| 122 | + sizes->surface_width, sizes->surface_height, | |
| 123 | + sizes->surface_bpp); | |
| 124 | + | |
| 125 | + format = drm_driver_legacy_fb_format(dev, sizes->surface_bpp, sizes->surface_depth); | |
| 126 | + buffer = drm_client_framebuffer_create(client, sizes->surface_width, | |
| 127 | + sizes->surface_height, format); | |
| 128 | + if (IS_ERR(buffer)) | |
| 129 | + return PTR_ERR(buffer); | |
| 130 | + shmem = to_drm_gem_shmem_obj(buffer->gem); | |
| 131 | + | |
| 132 | + fb = buffer->fb; | |
| 133 | + | |
| 134 | + ret = drm_client_buffer_vmap(buffer, &map); | |
| 135 | + if (ret) { | |
| 136 | + goto err_drm_client_buffer_delete; | |
| 137 | + } else if (drm_WARN_ON(dev, map.is_iomem)) { | |
| 138 | + ret = -ENODEV; /* I/O memory not supported; use generic emulation */ | |
| 139 | + goto err_drm_client_buffer_delete; | |
| 140 | + } | |
| 141 | + | |
| 142 | + fb_helper->buffer = buffer; | |
| 143 | + fb_helper->fb = fb; | |
| 144 | + | |
| 145 | + info = drm_fb_helper_alloc_info(fb_helper); | |
| 146 | + if (IS_ERR(info)) { | |
| 147 | + ret = PTR_ERR(info); | |
| 148 | + goto err_drm_client_buffer_vunmap; | |
| 149 | + } | |
| 150 | + | |
| 151 | + drm_fb_helper_fill_info(info, fb_helper, sizes); | |
| 152 | + | |
| 153 | + info->fbops = &drm_fbdev_shmem_fb_ops; | |
| 154 | + | |
| 155 | + /* screen */ | |
| 156 | + info->flags |= FBINFO_VIRTFB; /* system memory */ | |
| 157 | + if (!shmem->map_wc) | |
| 158 | + info->flags |= FBINFO_READS_FAST; /* signal caching */ | |
| 159 | + info->screen_size = sizes->surface_height * fb->pitches[0]; | |
| 160 | + info->screen_buffer = map.vaddr; | |
| 161 | + info->fix.smem_len = info->screen_size; | |
| 162 | + | |
| 163 | + /* deferred I/O */ | |
| 164 | + fb_helper->fbdefio.delay = HZ / 20; | |
| 165 | + fb_helper->fbdefio.get_page = drm_fbdev_shmem_get_page; | |
| 166 | + fb_helper->fbdefio.deferred_io = drm_fb_helper_deferred_io; | |
| 167 | + | |
| 168 | + info->fbdefio = &fb_helper->fbdefio; | |
| 169 | + ret = fb_deferred_io_init(info); | |
| 170 | + if (ret) | |
| 171 | + goto err_drm_fb_helper_release_info; | |
| 172 | + | |
| 173 | + return 0; | |
| 174 | + | |
| 175 | +err_drm_fb_helper_release_info: | |
| 176 | + drm_fb_helper_release_info(fb_helper); | |
| 177 | +err_drm_client_buffer_vunmap: | |
| 178 | + fb_helper->fb = NULL; | |
| 179 | + fb_helper->buffer = NULL; | |
| 180 | + drm_client_buffer_vunmap(buffer); | |
| 181 | +err_drm_client_buffer_delete: | |
| 182 | + drm_client_framebuffer_delete(buffer); | |
| 183 | + return ret; | |
| 184 | +} | |
| 185 | + | |
| 186 | +static int drm_fbdev_shmem_helper_fb_dirty(struct drm_fb_helper *helper, | |
| 187 | + struct drm_clip_rect *clip) | |
| 188 | +{ | |
| 189 | + struct drm_device *dev = helper->dev; | |
| 190 | + int ret; | |
| 191 | + | |
| 192 | + /* Call damage handlers only if necessary */ | |
| 193 | + if (!(clip->x1 < clip->x2 && clip->y1 < clip->y2)) | |
| 194 | + return 0; | |
| 195 | + | |
| 196 | + if (helper->fb->funcs->dirty) { | |
| 197 | + ret = helper->fb->funcs->dirty(helper->fb, NULL, 0, 0, clip, 1); | |
| 198 | + if (drm_WARN_ONCE(dev, ret, "Dirty helper failed: ret=%d\n", ret)) | |
| 199 | + return ret; | |
| 200 | + } | |
| 201 | + | |
| 202 | + return 0; | |
| 203 | +} | |
| 204 | + | |
| 205 | +static const struct drm_fb_helper_funcs drm_fbdev_shmem_helper_funcs = { | |
| 206 | + .fb_probe = drm_fbdev_shmem_helper_fb_probe, | |
| 207 | + .fb_dirty = drm_fbdev_shmem_helper_fb_dirty, | |
| 208 | +}; | |
| 209 | + | |
| 210 | +/* | |
| 211 | + * struct drm_client_funcs | |
| 212 | + */ | |
| 213 | + | |
| 214 | +static void drm_fbdev_shmem_client_unregister(struct drm_client_dev *client) | |
| 215 | +{ | |
| 216 | + struct drm_fb_helper *fb_helper = drm_fb_helper_from_client(client); | |
| 217 | + | |
| 218 | + if (fb_helper->info) { | |
| 219 | + drm_fb_helper_unregister_info(fb_helper); | |
| 220 | + } else { | |
| 221 | + drm_client_release(&fb_helper->client); | |
| 222 | + drm_fb_helper_unprepare(fb_helper); | |
| 223 | + kfree(fb_helper); | |
| 224 | + } | |
| 225 | +} | |
| 226 | + | |
| 227 | +static int drm_fbdev_shmem_client_restore(struct drm_client_dev *client) | |
| 228 | +{ | |
| 229 | + drm_fb_helper_lastclose(client->dev); | |
| 230 | + | |
| 231 | + return 0; | |
| 232 | +} | |
| 233 | + | |
| 234 | +static int drm_fbdev_shmem_client_hotplug(struct drm_client_dev *client) | |
| 235 | +{ | |
| 236 | + struct drm_fb_helper *fb_helper = drm_fb_helper_from_client(client); | |
| 237 | + struct drm_device *dev = client->dev; | |
| 238 | + int ret; | |
| 239 | + | |
| 240 | + if (dev->fb_helper) | |
| 241 | + return drm_fb_helper_hotplug_event(dev->fb_helper); | |
| 242 | + | |
| 243 | + ret = drm_fb_helper_init(dev, fb_helper); | |
| 244 | + if (ret) | |
| 245 | + goto err_drm_err; | |
| 246 | + | |
| 247 | + if (!drm_drv_uses_atomic_modeset(dev)) | |
| 248 | + drm_helper_disable_unused_functions(dev); | |
| 249 | + | |
| 250 | + ret = drm_fb_helper_initial_config(fb_helper); | |
| 251 | + if (ret) | |
| 252 | + goto err_drm_fb_helper_fini; | |
| 253 | + | |
| 254 | + return 0; | |
| 255 | + | |
| 256 | +err_drm_fb_helper_fini: | |
| 257 | + drm_fb_helper_fini(fb_helper); | |
| 258 | +err_drm_err: | |
| 259 | + drm_err(dev, "fbdev-shmem: Failed to setup emulation (ret=%d)\n", ret); | |
| 260 | + return ret; | |
| 261 | +} | |
| 262 | + | |
| 263 | +static const struct drm_client_funcs drm_fbdev_shmem_client_funcs = { | |
| 264 | + .owner = THIS_MODULE, | |
| 265 | + .unregister = drm_fbdev_shmem_client_unregister, | |
| 266 | + .restore = drm_fbdev_shmem_client_restore, | |
| 267 | + .hotplug = drm_fbdev_shmem_client_hotplug, | |
| 268 | +}; | |
| 269 | + | |
| 270 | +/** | |
| 271 | + * drm_fbdev_shmem_setup() - Setup fbdev emulation for GEM SHMEM helpers | |
| 272 | + * @dev: DRM device | |
| 273 | + * @preferred_bpp: Preferred bits per pixel for the device. | |
| 274 | + * 32 is used if this is zero. | |
| 275 | + * | |
| 276 | + * This function sets up fbdev emulation for GEM DMA drivers that support | |
| 277 | + * dumb buffers with a virtual address and that can be mmap'ed. | |
| 278 | + * drm_fbdev_shmem_setup() shall be called after the DRM driver registered | |
| 279 | + * the new DRM device with drm_dev_register(). | |
| 280 | + * | |
| 281 | + * Restore, hotplug events and teardown are all taken care of. Drivers that do | |
| 282 | + * suspend/resume need to call drm_fb_helper_set_suspend_unlocked() themselves. | |
| 283 | + * Simple drivers might use drm_mode_config_helper_suspend(). | |
| 284 | + * | |
| 285 | + * This function is safe to call even when there are no connectors present. | |
| 286 | + * Setup will be retried on the next hotplug event. | |
| 287 | + * | |
| 288 | + * The fbdev is destroyed by drm_dev_unregister(). | |
| 289 | + */ | |
| 290 | +void drm_fbdev_shmem_setup(struct drm_device *dev, unsigned int preferred_bpp) | |
| 291 | +{ | |
| 292 | + struct drm_fb_helper *fb_helper; | |
| 293 | + int ret; | |
| 294 | + | |
| 295 | + drm_WARN(dev, !dev->registered, "Device has not been registered.\n"); | |
| 296 | + drm_WARN(dev, dev->fb_helper, "fb_helper is already set!\n"); | |
| 297 | + | |
| 298 | + fb_helper = kzalloc(sizeof(*fb_helper), GFP_KERNEL); | |
| 299 | + if (!fb_helper) | |
| 300 | + return; | |
| 301 | + drm_fb_helper_prepare(dev, fb_helper, preferred_bpp, &drm_fbdev_shmem_helper_funcs); | |
| 302 | + | |
| 303 | + ret = drm_client_init(dev, &fb_helper->client, "fbdev", &drm_fbdev_shmem_client_funcs); | |
| 304 | + if (ret) { | |
| 305 | + drm_err(dev, "Failed to register client: %d\n", ret); | |
| 306 | + goto err_drm_client_init; | |
| 307 | + } | |
| 308 | + | |
| 309 | + drm_client_register(&fb_helper->client); | |
| 310 | + | |
| 311 | + return; | |
| 312 | + | |
| 313 | +err_drm_client_init: | |
| 314 | + drm_fb_helper_unprepare(fb_helper); | |
| 315 | + kfree(fb_helper); | |
| 316 | +} | |
| 317 | +EXPORT_SYMBOL(drm_fbdev_shmem_setup); | |
| @@ -10,10 +10,10 @@ · 9 unmodified lines | ||
| 10 | 10 | #include <drm/drm_gem.h> |
| 11 | 11 | #include <drm/drm_print.h> |
| 12 | 12 | |
| 13 | −#include <drm/drm_fbdev_generic.h> | |
| 13 | +#include <drm/drm_fbdev_ttm.h> | |
| 14 | 14 | |
| 15 | 15 | /* @user: 1=userspace, 0=fbcon */ |
| 16 | −static int drm_fbdev_generic_fb_open(struct fb_info *info, int user) | |
| 16 | +static int drm_fbdev_ttm_fb_open(struct fb_info *info, int user) | |
| 17 | 17 | { |
| 18 | 18 | struct drm_fb_helper *fb_helper = info->par; |
| 19 | 19 | |
| @@ -24,7 +24,7 @@ static int drm_fbdev_generic_fb_open(struct fb_info *info, int user) · 4 unmodified lines | ||
| 24 | 24 | return 0; |
| 25 | 25 | } |
| 26 | 26 | |
| 27 | −static int drm_fbdev_generic_fb_release(struct fb_info *info, int user) | |
| 27 | +static int drm_fbdev_ttm_fb_release(struct fb_info *info, int user) | |
| 28 | 28 | { |
| 29 | 29 | struct drm_fb_helper *fb_helper = info->par; |
| 30 | 30 | |
| @@ -34,11 +34,11 @@ static int drm_fbdev_generic_fb_release(struct fb_info *info, int user) · 3 unmodified lines | ||
| 34 | 34 | return 0; |
| 35 | 35 | } |
| 36 | 36 | |
| 37 | −FB_GEN_DEFAULT_DEFERRED_SYSMEM_OPS(drm_fbdev_generic, | |
| 37 | +FB_GEN_DEFAULT_DEFERRED_SYSMEM_OPS(drm_fbdev_ttm, | |
| 38 | 38 | drm_fb_helper_damage_range, |
| 39 | 39 | drm_fb_helper_damage_area); |
| 40 | 40 | |
| 41 | −static void drm_fbdev_generic_fb_destroy(struct fb_info *info) | |
| 41 | +static void drm_fbdev_ttm_fb_destroy(struct fb_info *info) | |
| 42 | 42 | { |
| 43 | 43 | struct drm_fb_helper *fb_helper = info->par; |
| 44 | 44 | void *shadow = info->screen_buffer; |
| @@ -56,19 +56,19 @@ static void drm_fbdev_generic_fb_destroy(struct fb_info *info) · 11 unmodified lines | ||
| 56 | 56 | kfree(fb_helper); |
| 57 | 57 | } |
| 58 | 58 | |
| 59 | −static const struct fb_ops drm_fbdev_generic_fb_ops = { | |
| 59 | +static const struct fb_ops drm_fbdev_ttm_fb_ops = { | |
| 60 | 60 | .owner = THIS_MODULE, |
| 61 | − .fb_open = drm_fbdev_generic_fb_open, | |
| 62 | − .fb_release = drm_fbdev_generic_fb_release, | |
| 63 | − FB_DEFAULT_DEFERRED_OPS(drm_fbdev_generic), | |
| 61 | + .fb_open = drm_fbdev_ttm_fb_open, | |
| 62 | + .fb_release = drm_fbdev_ttm_fb_release, | |
| 63 | + FB_DEFAULT_DEFERRED_OPS(drm_fbdev_ttm), | |
| 64 | 64 | DRM_FB_HELPER_DEFAULT_OPS, |
| 65 | − .fb_destroy = drm_fbdev_generic_fb_destroy, | |
| 65 | + .fb_destroy = drm_fbdev_ttm_fb_destroy, | |
| 66 | 66 | }; |
| 67 | 67 | |
| 68 | 68 | /* |
| 69 | 69 | * This function uses the client API to create a framebuffer backed by a dumb buffer. |
| 70 | 70 | */ |
| 71 | −static int drm_fbdev_generic_helper_fb_probe(struct drm_fb_helper *fb_helper, | |
| 71 | +static int drm_fbdev_ttm_helper_fb_probe(struct drm_fb_helper *fb_helper, | |
| 72 | 72 | struct drm_fb_helper_surface_size *sizes) |
| 73 | 73 | { |
| 74 | 74 | struct drm_client_dev *client = &fb_helper->client; |
| @@ -108,7 +108,7 @@ static int drm_fbdev_generic_helper_fb_probe(struct drm_fb_helper *fb_helper, · 33 unmodified lines | ||
| 108 | 108 | |
| 109 | 109 | drm_fb_helper_fill_info(info, fb_helper, sizes); |
| 110 | 110 | |
| 111 | − info->fbops = &drm_fbdev_generic_fb_ops; | |
| 111 | + info->fbops = &drm_fbdev_ttm_fb_ops; | |
| 112 | 112 | |
| 113 | 113 | /* screen */ |
| 114 | 114 | info->flags |= FBINFO_VIRTFB | FBINFO_READS_FAST; |
| @@ -137,9 +137,9 @@ err_drm_client_framebuffer_delete: · 22 unmodified lines | ||
| 137 | 137 | return ret; |
| 138 | 138 | } |
| 139 | 139 | |
| 140 | −static void drm_fbdev_generic_damage_blit_real(struct drm_fb_helper *fb_helper, | |
| 141 | − struct drm_clip_rect *clip, | |
| 142 | − struct iosys_map *dst) | |
| 140 | +static void drm_fbdev_ttm_damage_blit_real(struct drm_fb_helper *fb_helper, | |
| 141 | + struct drm_clip_rect *clip, | |
| 142 | + struct iosys_map *dst) | |
| 143 | 143 | { |
| 144 | 144 | struct drm_framebuffer *fb = fb_helper->fb; |
| 145 | 145 | size_t offset = clip->y1 * fb->pitches[0]; |
| @@ -176,8 +176,8 @@ static void drm_fbdev_generic_damage_blit_real(struct drm_fb_helper *fb_helper, · 30 unmodified lines | ||
| 176 | 176 | } |
| 177 | 177 | } |
| 178 | 178 | |
| 179 | −static int drm_fbdev_generic_damage_blit(struct drm_fb_helper *fb_helper, | |
| 180 | − struct drm_clip_rect *clip) | |
| 179 | +static int drm_fbdev_ttm_damage_blit(struct drm_fb_helper *fb_helper, | |
| 180 | + struct drm_clip_rect *clip) | |
| 181 | 181 | { |
| 182 | 182 | struct drm_client_buffer *buffer = fb_helper->buffer; |
| 183 | 183 | struct iosys_map map, dst; |
| @@ -201,7 +201,7 @@ static int drm_fbdev_generic_damage_blit(struct drm_fb_helper *fb_helper, · 17 unmodified lines | ||
| 201 | 201 | goto out; |
| 202 | 202 | |
| 203 | 203 | dst = map; |
| 204 | − drm_fbdev_generic_damage_blit_real(fb_helper, clip, &dst); | |
| 204 | + drm_fbdev_ttm_damage_blit_real(fb_helper, clip, &dst); | |
| 205 | 205 | |
| 206 | 206 | drm_client_buffer_vunmap_local(buffer); |
| 207 | 207 | |
| @@ -211,8 +211,8 @@ out: · 3 unmodified lines | ||
| 211 | 211 | return ret; |
| 212 | 212 | } |
| 213 | 213 | |
| 214 | −static int drm_fbdev_generic_helper_fb_dirty(struct drm_fb_helper *helper, | |
| 215 | − struct drm_clip_rect *clip) | |
| 214 | +static int drm_fbdev_ttm_helper_fb_dirty(struct drm_fb_helper *helper, | |
| 215 | + struct drm_clip_rect *clip) | |
| 216 | 216 | { |
| 217 | 217 | struct drm_device *dev = helper->dev; |
| 218 | 218 | int ret; |
| @@ -221,7 +221,7 @@ static int drm_fbdev_generic_helper_fb_dirty(struct drm_fb_helper *helper, · 2 unmodified lines | ||
| 221 | 221 | if (!(clip->x1 < clip->x2 && clip->y1 < clip->y2)) |
| 222 | 222 | return 0; |
| 223 | 223 | |
| 224 | − ret = drm_fbdev_generic_damage_blit(helper, clip); | |
| 224 | + ret = drm_fbdev_ttm_damage_blit(helper, clip); | |
| 225 | 225 | if (drm_WARN_ONCE(dev, ret, "Damage blitter failed: ret=%d\n", ret)) |
| 226 | 226 | return ret; |
| 227 | 227 | |
| @@ -234,12 +234,12 @@ static int drm_fbdev_generic_helper_fb_dirty(struct drm_fb_helper *helper, · 6 unmodified lines | ||
| 234 | 234 | return 0; |
| 235 | 235 | } |
| 236 | 236 | |
| 237 | −static const struct drm_fb_helper_funcs drm_fbdev_generic_helper_funcs = { | |
| 238 | − .fb_probe = drm_fbdev_generic_helper_fb_probe, | |
| 239 | − .fb_dirty = drm_fbdev_generic_helper_fb_dirty, | |
| 237 | +static const struct drm_fb_helper_funcs drm_fbdev_ttm_helper_funcs = { | |
| 238 | + .fb_probe = drm_fbdev_ttm_helper_fb_probe, | |
| 239 | + .fb_dirty = drm_fbdev_ttm_helper_fb_dirty, | |
| 240 | 240 | }; |
| 241 | 241 | |
| 242 | −static void drm_fbdev_generic_client_unregister(struct drm_client_dev *client) | |
| 242 | +static void drm_fbdev_ttm_client_unregister(struct drm_client_dev *client) | |
| 243 | 243 | { |
| 244 | 244 | struct drm_fb_helper *fb_helper = drm_fb_helper_from_client(client); |
| 245 | 245 | |
| @@ -252,14 +252,14 @@ static void drm_fbdev_generic_client_unregister(struct drm_client_dev *client) · 6 unmodified lines | ||
| 252 | 252 | } |
| 253 | 253 | } |
| 254 | 254 | |
| 255 | −static int drm_fbdev_generic_client_restore(struct drm_client_dev *client) | |
| 255 | +static int drm_fbdev_ttm_client_restore(struct drm_client_dev *client) | |
| 256 | 256 | { |
| 257 | 257 | drm_fb_helper_lastclose(client->dev); |
| 258 | 258 | |
| 259 | 259 | return 0; |
| 260 | 260 | } |
| 261 | 261 | |
| 262 | −static int drm_fbdev_generic_client_hotplug(struct drm_client_dev *client) | |
| 262 | +static int drm_fbdev_ttm_client_hotplug(struct drm_client_dev *client) | |
| 263 | 263 | { |
| 264 | 264 | struct drm_fb_helper *fb_helper = drm_fb_helper_from_client(client); |
| 265 | 265 | struct drm_device *dev = client->dev; |
| @@ -284,32 +284,32 @@ static int drm_fbdev_generic_client_hotplug(struct drm_client_dev *client) · 18 unmodified lines | ||
| 284 | 284 | err_drm_fb_helper_fini: |
| 285 | 285 | drm_fb_helper_fini(fb_helper); |
| 286 | 286 | err_drm_err: |
| 287 | − drm_err(dev, "fbdev: Failed to setup generic emulation (ret=%d)\n", ret); | |
| 287 | + drm_err(dev, "fbdev: Failed to setup emulation (ret=%d)\n", ret); | |
| 288 | 288 | return ret; |
| 289 | 289 | } |
| 290 | 290 | |
| 291 | −static const struct drm_client_funcs drm_fbdev_generic_client_funcs = { | |
| 291 | +static const struct drm_client_funcs drm_fbdev_ttm_client_funcs = { | |
| 292 | 292 | .owner = THIS_MODULE, |
| 293 | − .unregister = drm_fbdev_generic_client_unregister, | |
| 294 | − .restore = drm_fbdev_generic_client_restore, | |
| 295 | − .hotplug = drm_fbdev_generic_client_hotplug, | |
| 293 | + .unregister = drm_fbdev_ttm_client_unregister, | |
| 294 | + .restore = drm_fbdev_ttm_client_restore, | |
| 295 | + .hotplug = drm_fbdev_ttm_client_hotplug, | |
| 296 | 296 | }; |
| 297 | 297 | |
| 298 | 298 | /** |
| 299 | − * drm_fbdev_generic_setup() - Setup generic fbdev emulation | |
| 299 | + * drm_fbdev_ttm_setup() - Setup fbdev emulation for TTM-based drivers | |
| 300 | 300 | * @dev: DRM device |
| 301 | 301 | * @preferred_bpp: Preferred bits per pixel for the device. |
| 302 | 302 | * |
| 303 | − * This function sets up generic fbdev emulation for drivers that supports | |
| 303 | + * This function sets up fbdev emulation for TTM-based drivers that support | |
| 304 | 304 | * dumb buffers with a virtual address and that can be mmap'ed. |
| 305 | − * drm_fbdev_generic_setup() shall be called after the DRM driver registered | |
| 305 | + * drm_fbdev_ttm_setup() shall be called after the DRM driver registered | |
| 306 | 306 | * the new DRM device with drm_dev_register(). |
| 307 | 307 | * |
| 308 | 308 | * Restore, hotplug events and teardown are all taken care of. Drivers that do |
| 309 | 309 | * suspend/resume need to call drm_fb_helper_set_suspend_unlocked() themselves. |
| 310 | 310 | * Simple drivers might use drm_mode_config_helper_suspend(). |
| 311 | 311 | * |
| 312 | − * In order to provide fixed mmap-able memory ranges, generic fbdev emulation | |
| 312 | + * In order to provide fixed mmap-able memory ranges, fbdev emulation | |
| 313 | 313 | * uses a shadow buffer in system memory. The implementation blits the shadow |
| 314 | 314 | * fbdev buffer onto the real buffer in regular intervals. |
| 315 | 315 | * |
| @@ -318,7 +318,7 @@ static const struct drm_client_funcs drm_fbdev_generic_client_funcs = { · 2 unmodified lines | ||
| 318 | 318 | * |
| 319 | 319 | * The fbdev is destroyed by drm_dev_unregister(). |
| 320 | 320 | */ |
| 321 | −void drm_fbdev_generic_setup(struct drm_device *dev, unsigned int preferred_bpp) | |
| 321 | +void drm_fbdev_ttm_setup(struct drm_device *dev, unsigned int preferred_bpp) | |
| 322 | 322 | { |
| 323 | 323 | struct drm_fb_helper *fb_helper; |
| 324 | 324 | int ret; |
| @@ -329,9 +329,9 @@ void drm_fbdev_generic_setup(struct drm_device *dev, unsigned int preferred_bpp) · 4 unmodified lines | ||
| 329 | 329 | fb_helper = kzalloc(sizeof(*fb_helper), GFP_KERNEL); |
| 330 | 330 | if (!fb_helper) |
| 331 | 331 | return; |
| 332 | − drm_fb_helper_prepare(dev, fb_helper, preferred_bpp, &drm_fbdev_generic_helper_funcs); | |
| 332 | + drm_fb_helper_prepare(dev, fb_helper, preferred_bpp, &drm_fbdev_ttm_helper_funcs); | |
| 333 | 333 | |
| 334 | − ret = drm_client_init(dev, &fb_helper->client, "fbdev", &drm_fbdev_generic_client_funcs); | |
| 334 | + ret = drm_client_init(dev, &fb_helper->client, "fbdev", &drm_fbdev_ttm_client_funcs); | |
| 335 | 335 | if (ret) { |
| 336 | 336 | drm_err(dev, "Failed to register client: %d\n", ret); |
| 337 | 337 | goto err_drm_client_init; |
| @@ -346,4 +346,4 @@ err_drm_client_init: · 8 unmodified lines | ||
| 346 | 346 | kfree(fb_helper); |
| 347 | 347 | return; |
| 348 | 348 | } |
| 349 | −EXPORT_SYMBOL(drm_fbdev_generic_setup); | |
| 349 | +EXPORT_SYMBOL(drm_fbdev_ttm_setup); | |
| @@ -529,9 +529,10 @@ int drm_version(struct drm_device *dev, void *data, · 528 unmodified lines | ||
| 529 | 529 | version->version_patchlevel = dev->driver->patchlevel; |
| 530 | 530 | err = drm_copy_field(version->name, &version->name_len, |
| 531 | 531 | dev->driver->name); |
| 532 | + | |
| 533 | + /* Driver date is deprecated. Userspace expects a non-empty string. */ | |
| 532 | 534 | if (!err) |
| 533 | − err = drm_copy_field(version->date, &version->date_len, | |
| 534 | − dev->driver->date); | |
| 535 | + err = drm_copy_field(version->date, &version->date_len, "0"); | |
| 535 | 536 | if (!err) |
| 536 | 537 | err = drm_copy_field(version->desc, &version->desc_len, |
| 537 | 538 | dev->driver->desc); |
| @@ -206,6 +206,7 @@ int mipi_dbi_buf_copy(void *dst, struct iosys_map *src, struct drm_framebuffer * · 205 unmodified lines | ||
| 206 | 206 | struct drm_rect *clip, bool swap, |
| 207 | 207 | struct drm_format_conv_state *fmtcnv_state) |
| 208 | 208 | { |
| 209 | + struct mipi_dbi_dev *dbidev = drm_to_mipi_dbi_dev(fb->dev); | |
| 209 | 210 | struct drm_gem_object *gem = drm_gem_fb_get_obj(fb, 0); |
| 210 | 211 | struct iosys_map dst_map = IOSYS_MAP_INIT_VADDR(dst); |
| 211 | 212 | int ret; |
| @@ -222,8 +223,18 @@ int mipi_dbi_buf_copy(void *dst, struct iosys_map *src, struct drm_framebuffer * · 10 unmodified lines | ||
| 222 | 223 | else |
| 223 | 224 | drm_fb_memcpy(&dst_map, NULL, src, fb, clip); |
| 224 | 225 | break; |
| 226 | + case DRM_FORMAT_RGB888: | |
| 227 | + drm_fb_memcpy(&dst_map, NULL, src, fb, clip); | |
| 228 | + break; | |
| 225 | 229 | case DRM_FORMAT_XRGB8888: |
| 226 | − drm_fb_xrgb8888_to_rgb565(&dst_map, NULL, src, fb, clip, fmtcnv_state, swap); | |
| 230 | + switch (dbidev->pixel_format) { | |
| 231 | + case DRM_FORMAT_RGB565: | |
| 232 | + drm_fb_xrgb8888_to_rgb565(&dst_map, NULL, src, fb, clip, fmtcnv_state, swap); | |
| 233 | + break; | |
| 234 | + case DRM_FORMAT_RGB888: | |
| 235 | + drm_fb_xrgb8888_to_rgb888(&dst_map, NULL, src, fb, clip, fmtcnv_state); | |
| 236 | + break; | |
| 237 | + } | |
| 227 | 238 | break; |
| 228 | 239 | default: |
| 229 | 240 | drm_err_once(fb->dev, "Format is not supported: %p4cc\n", |
| @@ -260,9 +271,11 @@ static void mipi_dbi_fb_dirty(struct iosys_map *src, struct drm_framebuffer *fb, · 30 unmodified lines | ||
| 260 | 271 | struct mipi_dbi_dev *dbidev = drm_to_mipi_dbi_dev(fb->dev); |
| 261 | 272 | unsigned int height = rect->y2 - rect->y1; |
| 262 | 273 | unsigned int width = rect->x2 - rect->x1; |
| 274 | + const struct drm_format_info *dst_format; | |
| 263 | 275 | struct mipi_dbi *dbi = &dbidev->dbi; |
| 264 | 276 | bool swap = dbi->swap_bytes; |
| 265 | 277 | int ret = 0; |
| 278 | + size_t len; | |
| 266 | 279 | bool full; |
| 267 | 280 | void *tr; |
| 268 | 281 | |
| @@ -283,8 +296,13 @@ static void mipi_dbi_fb_dirty(struct iosys_map *src, struct drm_framebuffer *fb, · 14 unmodified lines | ||
| 283 | 296 | mipi_dbi_set_window_address(dbidev, rect->x1, rect->x2 - 1, rect->y1, |
| 284 | 297 | rect->y2 - 1); |
| 285 | 298 | |
| 286 | − ret = mipi_dbi_command_buf(dbi, MIPI_DCS_WRITE_MEMORY_START, tr, | |
| 287 | − width * height * 2); | |
| 299 | + if (fb->format->format == DRM_FORMAT_XRGB8888) | |
| 300 | + dst_format = drm_format_info(dbidev->pixel_format); | |
| 301 | + else | |
| 302 | + dst_format = fb->format; | |
| 303 | + len = drm_format_info_min_pitch(dst_format, 0, width) * height; | |
| 304 | + | |
| 305 | + ret = mipi_dbi_command_buf(dbi, MIPI_DCS_WRITE_MEMORY_START, tr, len); | |
| 288 | 306 | err_msg: |
| 289 | 307 | if (ret) |
| 290 | 308 | drm_err_once(fb->dev, "Failed to update display %d\n", ret); |
| @@ -572,7 +590,7 @@ static const uint32_t mipi_dbi_formats[] = { · 281 unmodified lines | ||
| 572 | 590 | * has one fixed &drm_display_mode which is rotated according to @rotation. |
| 573 | 591 | * This mode is used to set the mode config min/max width/height properties. |
| 574 | 592 | * |
| 575 | − * Use mipi_dbi_dev_init() if you don't need custom formats. | |
| 593 | + * Use mipi_dbi_dev_init() if you want native RGB565 and emulated XRGB8888 format. | |
| 576 | 594 | * |
| 577 | 595 | * Note: |
| 578 | 596 | * Some of the helper functions expects RGB565 to be the default format and the |
| @@ -631,6 +649,9 @@ int mipi_dbi_dev_init_with_formats(struct mipi_dbi_dev *dbidev, · 52 unmodified lines | ||
| 631 | 649 | drm->mode_config.min_height = dbidev->mode.vdisplay; |
| 632 | 650 | drm->mode_config.max_height = dbidev->mode.vdisplay; |
| 633 | 651 | dbidev->rotation = rotation; |
| 652 | + dbidev->pixel_format = formats[0]; | |
| 653 | + if (formats[0] == DRM_FORMAT_RGB888) | |
| 654 | + dbidev->dbi.write_memory_bpw = 8; | |
| 634 | 655 | |
| 635 | 656 | DRM_DEBUG_KMS("rotation = %u\n", rotation); |
| 636 | 657 | |
| @@ -824,15 +845,6 @@ u32 mipi_dbi_spi_cmd_max_speed(struct spi_device *spi, size_t len) · 187 unmodified lines | ||
| 824 | 845 | } |
| 825 | 846 | EXPORT_SYMBOL(mipi_dbi_spi_cmd_max_speed); |
| 826 | 847 | |
| 827 | −static bool mipi_dbi_machine_little_endian(void) | |
| 828 | −{ | |
| 829 | −#if defined(__LITTLE_ENDIAN) | |
| 830 | − return true; | |
| 831 | −#else | |
| 832 | − return false; | |
| 833 | −#endif | |
| 834 | −} | |
| 835 | − | |
| 836 | 848 | /* |
| 837 | 849 | * MIPI DBI Type C Option 1 |
| 838 | 850 | * |
| @@ -855,7 +867,7 @@ static int mipi_dbi_spi1e_transfer(struct mipi_dbi *dbi, int dc, · 16 unmodified lines | ||
| 855 | 867 | const void *buf, size_t len, |
| 856 | 868 | unsigned int bpw) |
| 857 | 869 | { |
| 858 | − bool swap_bytes = (bpw == 16 && mipi_dbi_machine_little_endian()); | |
| 870 | + bool swap_bytes = (bpw == 16); | |
| 859 | 871 | size_t chunk, max_chunk = dbi->tx_buf9_len; |
| 860 | 872 | struct spi_device *spi = dbi->spi; |
| 861 | 873 | struct spi_transfer tr = { |
| @@ -1004,7 +1016,7 @@ static int mipi_dbi_spi1_transfer(struct mipi_dbi *dbi, int dc, · 142 unmodified lines | ||
| 1004 | 1016 | size_t chunk = min(len, max_chunk); |
| 1005 | 1017 | unsigned int i; |
| 1006 | 1018 | |
| 1007 | − if (bpw == 16 && mipi_dbi_machine_little_endian()) { | |
| 1019 | + if (bpw == 16) { | |
| 1008 | 1020 | for (i = 0; i < (chunk * 2); i += 2) { |
| 1009 | 1021 | dst16[i] = *src16 >> 8; |
| 1010 | 1022 | dst16[i + 1] = *src16++ & 0xFF; |
| @@ -1088,7 +1100,7 @@ static int mipi_dbi_typec1_command_read(struct mipi_dbi *dbi, u8 *cmd, · 77 unmodified lines | ||
| 1088 | 1100 | static int mipi_dbi_typec1_command(struct mipi_dbi *dbi, u8 *cmd, |
| 1089 | 1101 | u8 *parameters, size_t num) |
| 1090 | 1102 | { |
| 1091 | − unsigned int bpw = (*cmd == MIPI_DCS_WRITE_MEMORY_START) ? 16 : 8; | |
| 1103 | + unsigned int bpw = 8; | |
| 1092 | 1104 | int ret; |
| 1093 | 1105 | |
| 1094 | 1106 | if (mipi_dbi_command_is_read(dbi, *cmd)) |
| @@ -1100,6 +1112,9 @@ static int mipi_dbi_typec1_command(struct mipi_dbi *dbi, u8 *cmd, · 5 unmodified lines | ||
| 1100 | 1112 | if (ret || !num) |
| 1101 | 1113 | return ret; |
| 1102 | 1114 | |
| 1115 | + if (*cmd == MIPI_DCS_WRITE_MEMORY_START) | |
| 1116 | + bpw = dbi->write_memory_bpw; | |
| 1117 | + | |
| 1103 | 1118 | return mipi_dbi_spi1_transfer(dbi, 1, parameters, num, bpw); |
| 1104 | 1119 | } |
| 1105 | 1120 | |
| @@ -1193,8 +1208,8 @@ static int mipi_dbi_typec3_command(struct mipi_dbi *dbi, u8 *cmd, · 87 unmodified lines | ||
| 1193 | 1208 | if (ret || !num) |
| 1194 | 1209 | return ret; |
| 1195 | 1210 | |
| 1196 | − if (*cmd == MIPI_DCS_WRITE_MEMORY_START && !dbi->swap_bytes) | |
| 1197 | − bpw = 16; | |
| 1211 | + if (*cmd == MIPI_DCS_WRITE_MEMORY_START) | |
| 1212 | + bpw = dbi->write_memory_bpw; | |
| 1198 | 1213 | |
| 1199 | 1214 | spi_bus_lock(spi->controller); |
| 1200 | 1215 | gpiod_set_value_cansleep(dbi->dc, 1); |
| @@ -1218,11 +1233,23 @@ static int mipi_dbi_typec3_command(struct mipi_dbi *dbi, u8 *cmd, · 17 unmodified lines | ||
| 1218 | 1233 | * If @dc is set, a Type C Option 3 interface is assumed, if not |
| 1219 | 1234 | * Type C Option 1. |
| 1220 | 1235 | * |
| 1221 | − * If the SPI master driver doesn't support the necessary bits per word, | |
| 1222 | − * the following transformation is used: | |
| 1236 | + * If the command is %MIPI_DCS_WRITE_MEMORY_START and the pixel format is RGB565, endianness has | |
| 1237 | + * to be taken into account. The MIPI DBI serial interface is big endian and framebuffers are | |
| 1238 | + * assumed stored in memory as little endian (%DRM_FORMAT_BIG_ENDIAN is not supported). | |
| 1223 | 1239 | * |
| 1224 | − * - 9-bit: reorder buffer as 9x 8-bit words, padded with no-op command. | |
| 1225 | − * - 16-bit: if big endian send as 8-bit, if little endian swap bytes | |
| 1240 | + * This is how endianness is handled: | |
| 1241 | + * | |
| 1242 | + * Option 1 (D/C as a bit): The buffer is sent on the wire byte by byte so the 16-bit buffer is | |
| 1243 | + * byteswapped before transfer. | |
| 1244 | + * | |
| 1245 | + * Option 3 (D/C as a gpio): If the SPI controller supports 16 bits per word the buffer can be | |
| 1246 | + * sent as-is. If not the caller is responsible for swapping the bytes | |
| 1247 | + * before calling mipi_dbi_command_buf() and the buffer is sent 8 bpw. | |
| 1248 | + * | |
| 1249 | + * This handling is optimised for %DRM_FORMAT_RGB565 framebuffers. | |
| 1250 | + * | |
| 1251 | + * If the interface is Option 1 and the SPI controller doesn't support 9 bits per word, | |
| 1252 | + * the buffer is sent as 9x 8-bit words, padded with MIPI DCS no-op commands if necessary. | |
| 1226 | 1253 | * |
| 1227 | 1254 | * Returns: |
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