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Merge drm/drm-next into drm-xe-next

Need to sync some header include that propagated through drm-intel-next. v2: After some changes in drm/drm-next

Rodrigo Vivi committed 2 years ago

Commit 8664e762 parents 33991ae 541b1b0616 files · +27860 −18095Browse files

Showing the changes to include/uapi (5 of 616 files). Show all

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5 files
  1. include/uapi/drm/amdgpu_drm.h +9 −0
  2. include/uapi/drm/drm_mode.h +0 −8
  3. include/uapi/drm/ivpu_accel.h +68 −1
  4. include/uapi/drm/v3d_drm.h +48 −0
  5. include/uapi/linux/dma-heap.h +1 −1
include/uapi/drm/amdgpu_drm.h+9−0
@@ -1283,6 +1283,15 @@ struct drm_amdgpu_info_gpuvm_fault { · 1282 unmodified lines
1283#define AMDGPU_FAMILY_GC_11_5_0 150 /* GC 11.5.0 */1283#define AMDGPU_FAMILY_GC_11_5_0 150 /* GC 11.5.0 */
1284#define AMDGPU_FAMILY_GC_12_0_0 152 /* GC 12.0.0 */1284#define AMDGPU_FAMILY_GC_12_0_0 152 /* GC 12.0.0 */
1285 1285
1286/* FIXME wrong namespace! */
1287struct drm_color_ctm_3x4 {
1288 /*
1289 * Conversion matrix with 3x4 dimensions in S31.32 sign-magnitude
1290 * (not two's complement!) format.
1291 */
1292 __u64 matrix[12];
1293};
1294
1286#if defined(__cplusplus)1295#if defined(__cplusplus)
1287}1296}
1288#endif1297#endif
include/uapi/drm/drm_mode.h+0−8
@@ -846,14 +846,6 @@ struct drm_color_ctm { · 845 unmodified lines
846 __u64 matrix[9];846 __u64 matrix[9];
847};847};
848 848
849struct drm_color_ctm_3x4 {
850 /*
851 * Conversion matrix with 3x4 dimensions in S31.32 sign-magnitude
852 * (not two's complement!) format.
853 */
854 __u64 matrix[12];
855};
856
857struct drm_color_lut {849struct drm_color_lut {
858 /*850 /*
859 * Values are mapped linearly to 0.0 - 1.0 range, with 0x0 == 0.0 and851 * Values are mapped linearly to 0.0 - 1.0 range, with 0x0 == 0.0 and
include/uapi/drm/ivpu_accel.h+68−1
@@ -1,6 +1,6 @@
1/* SPDX-License-Identifier: GPL-2.0-only WITH Linux-syscall-note */1/* SPDX-License-Identifier: GPL-2.0-only WITH Linux-syscall-note */
2/*2/*
3 * Copyright (C) 2020-2023 Intel Corporation3 * Copyright (C) 2020-2024 Intel Corporation
4 */4 */
5 5
6#ifndef __UAPI_IVPU_DRM_H__6#ifndef __UAPI_IVPU_DRM_H__
@@ -21,6 +21,10 @@ extern "C" { · 14 unmodified lines
21#define DRM_IVPU_BO_INFO 0x0321#define DRM_IVPU_BO_INFO 0x03
22#define DRM_IVPU_SUBMIT 0x0522#define DRM_IVPU_SUBMIT 0x05
23#define DRM_IVPU_BO_WAIT 0x0623#define DRM_IVPU_BO_WAIT 0x06
24#define DRM_IVPU_METRIC_STREAMER_START 0x07
25#define DRM_IVPU_METRIC_STREAMER_STOP 0x08
26#define DRM_IVPU_METRIC_STREAMER_GET_DATA 0x09
27#define DRM_IVPU_METRIC_STREAMER_GET_INFO 0x0a
24 28
25#define DRM_IOCTL_IVPU_GET_PARAM \29#define DRM_IOCTL_IVPU_GET_PARAM \
26 DRM_IOWR(DRM_COMMAND_BASE + DRM_IVPU_GET_PARAM, struct drm_ivpu_param)30 DRM_IOWR(DRM_COMMAND_BASE + DRM_IVPU_GET_PARAM, struct drm_ivpu_param)
@@ -40,6 +44,22 @@ extern "C" { · 13 unmodified lines
40#define DRM_IOCTL_IVPU_BO_WAIT \44#define DRM_IOCTL_IVPU_BO_WAIT \
41 DRM_IOWR(DRM_COMMAND_BASE + DRM_IVPU_BO_WAIT, struct drm_ivpu_bo_wait)45 DRM_IOWR(DRM_COMMAND_BASE + DRM_IVPU_BO_WAIT, struct drm_ivpu_bo_wait)
42 46
47#define DRM_IOCTL_IVPU_METRIC_STREAMER_START \
48 DRM_IOWR(DRM_COMMAND_BASE + DRM_IVPU_METRIC_STREAMER_START, \
49 struct drm_ivpu_metric_streamer_start)
50
51#define DRM_IOCTL_IVPU_METRIC_STREAMER_STOP \
52 DRM_IOW(DRM_COMMAND_BASE + DRM_IVPU_METRIC_STREAMER_STOP, \
53 struct drm_ivpu_metric_streamer_stop)
54
55#define DRM_IOCTL_IVPU_METRIC_STREAMER_GET_DATA \
56 DRM_IOWR(DRM_COMMAND_BASE + DRM_IVPU_METRIC_STREAMER_GET_DATA, \
57 struct drm_ivpu_metric_streamer_get_data)
58
59#define DRM_IOCTL_IVPU_METRIC_STREAMER_GET_INFO \
60 DRM_IOWR(DRM_COMMAND_BASE + DRM_IVPU_METRIC_STREAMER_GET_INFO, \
61 struct drm_ivpu_metric_streamer_get_data)
62
43/**63/**
44 * DOC: contexts64 * DOC: contexts
45 *65 *
@@ -336,6 +356,53 @@ struct drm_ivpu_bo_wait { · 290 unmodified lines
336 __u32 pad;356 __u32 pad;
337};357};
338 358
359/**
360 * struct drm_ivpu_metric_streamer_start - Start collecting metric data
361 */
362struct drm_ivpu_metric_streamer_start {
363 /** @metric_group_mask: Indicates metric streamer instance */
364 __u64 metric_group_mask;
365 /** @sampling_period_ns: Sampling period in nanoseconds */
366 __u64 sampling_period_ns;
367 /**
368 * @read_period_samples:
369 *
370 * Number of samples after which user space will try to read the data.
371 * Reading the data after significantly longer period may cause data loss.
372 */
373 __u32 read_period_samples;
374 /** @sample_size: Returned size of a single sample in bytes */
375 __u32 sample_size;
376 /** @max_data_size: Returned max @data_size from %DRM_IOCTL_IVPU_METRIC_STREAMER_GET_DATA */
377 __u32 max_data_size;
378};
379
380/**
381 * struct drm_ivpu_metric_streamer_get_data - Copy collected metric data
382 */
383struct drm_ivpu_metric_streamer_get_data {
384 /** @metric_group_mask: Indicates metric streamer instance */
385 __u64 metric_group_mask;
386 /** @buffer_ptr: A pointer to a destination for the copied data */
387 __u64 buffer_ptr;
388 /** @buffer_size: Size of the destination buffer */
389 __u64 buffer_size;
390 /**
391 * @data_size: Returned size of copied metric data
392 *
393 * If the @buffer_size is zero, returns the amount of data ready to be copied.
394 */
395 __u64 data_size;
396};
397
398/**
399 * struct drm_ivpu_metric_streamer_stop - Stop collecting metric data
400 */
401struct drm_ivpu_metric_streamer_stop {
402 /** @metric_group_mask: Indicates metric streamer instance */
403 __u64 metric_group_mask;
404};
405
339#if defined(__cplusplus)406#if defined(__cplusplus)
340}407}
341#endif408#endif
include/uapi/drm/v3d_drm.h+48−0
@@ -42,6 +42,7 @@ extern "C" { · 41 unmodified lines
42#define DRM_V3D_PERFMON_DESTROY 0x0942#define DRM_V3D_PERFMON_DESTROY 0x09
43#define DRM_V3D_PERFMON_GET_VALUES 0x0a43#define DRM_V3D_PERFMON_GET_VALUES 0x0a
44#define DRM_V3D_SUBMIT_CPU 0x0b44#define DRM_V3D_SUBMIT_CPU 0x0b
45#define DRM_V3D_PERFMON_GET_COUNTER 0x0c
45 46
46#define DRM_IOCTL_V3D_SUBMIT_CL DRM_IOWR(DRM_COMMAND_BASE + DRM_V3D_SUBMIT_CL, struct drm_v3d_submit_cl)47#define DRM_IOCTL_V3D_SUBMIT_CL DRM_IOWR(DRM_COMMAND_BASE + DRM_V3D_SUBMIT_CL, struct drm_v3d_submit_cl)
47#define DRM_IOCTL_V3D_WAIT_BO DRM_IOWR(DRM_COMMAND_BASE + DRM_V3D_WAIT_BO, struct drm_v3d_wait_bo)48#define DRM_IOCTL_V3D_WAIT_BO DRM_IOWR(DRM_COMMAND_BASE + DRM_V3D_WAIT_BO, struct drm_v3d_wait_bo)
@@ -58,6 +59,8 @@ extern "C" { · 10 unmodified lines
58#define DRM_IOCTL_V3D_PERFMON_GET_VALUES DRM_IOWR(DRM_COMMAND_BASE + DRM_V3D_PERFMON_GET_VALUES, \59#define DRM_IOCTL_V3D_PERFMON_GET_VALUES DRM_IOWR(DRM_COMMAND_BASE + DRM_V3D_PERFMON_GET_VALUES, \
59 struct drm_v3d_perfmon_get_values)60 struct drm_v3d_perfmon_get_values)
60#define DRM_IOCTL_V3D_SUBMIT_CPU DRM_IOW(DRM_COMMAND_BASE + DRM_V3D_SUBMIT_CPU, struct drm_v3d_submit_cpu)61#define DRM_IOCTL_V3D_SUBMIT_CPU DRM_IOW(DRM_COMMAND_BASE + DRM_V3D_SUBMIT_CPU, struct drm_v3d_submit_cpu)
62#define DRM_IOCTL_V3D_PERFMON_GET_COUNTER DRM_IOWR(DRM_COMMAND_BASE + DRM_V3D_PERFMON_GET_COUNTER, \
63 struct drm_v3d_perfmon_get_counter)
61 64
62#define DRM_V3D_SUBMIT_CL_FLUSH_CACHE 0x0165#define DRM_V3D_SUBMIT_CL_FLUSH_CACHE 0x01
63#define DRM_V3D_SUBMIT_EXTENSION 0x0266#define DRM_V3D_SUBMIT_EXTENSION 0x02
@@ -286,6 +289,7 @@ enum drm_v3d_param { · 222 unmodified lines
286 DRM_V3D_PARAM_SUPPORTS_PERFMON,289 DRM_V3D_PARAM_SUPPORTS_PERFMON,
287 DRM_V3D_PARAM_SUPPORTS_MULTISYNC_EXT,290 DRM_V3D_PARAM_SUPPORTS_MULTISYNC_EXT,
288 DRM_V3D_PARAM_SUPPORTS_CPU_QUEUE,291 DRM_V3D_PARAM_SUPPORTS_CPU_QUEUE,
292 DRM_V3D_PARAM_MAX_PERF_COUNTERS,
289};293};
290 294
291struct drm_v3d_get_param {295struct drm_v3d_get_param {
@@ -599,6 +603,16 @@ struct drm_v3d_submit_cpu { · 307 unmodified lines
599 __u64 extensions;603 __u64 extensions;
600};604};
601 605
606/* The performance counters index represented by this enum are deprecated and
607 * must no longer be used. These counters are only valid for V3D 4.2.
608 *
609 * In order to check for performance counter information,
610 * use DRM_IOCTL_V3D_PERFMON_GET_COUNTER.
611 *
612 * Don't use V3D_PERFCNT_NUM to retrieve the maximum number of performance
613 * counters. You should use DRM_IOCTL_V3D_GET_PARAM with the following
614 * parameter: DRM_V3D_PARAM_MAX_PERF_COUNTERS.
615 */
602enum {616enum {
603 V3D_PERFCNT_FEP_VALID_PRIMTS_NO_PIXELS,617 V3D_PERFCNT_FEP_VALID_PRIMTS_NO_PIXELS,
604 V3D_PERFCNT_FEP_VALID_PRIMS,618 V3D_PERFCNT_FEP_VALID_PRIMS,
@@ -717,6 +731,40 @@ struct drm_v3d_perfmon_get_values { · 112 unmodified lines
717 __u64 values_ptr;731 __u64 values_ptr;
718};732};
719 733
734#define DRM_V3D_PERFCNT_MAX_NAME 64
735#define DRM_V3D_PERFCNT_MAX_CATEGORY 32
736#define DRM_V3D_PERFCNT_MAX_DESCRIPTION 256
737
738/**
739 * struct drm_v3d_perfmon_get_counter - ioctl to get the description of a
740 * performance counter
741 *
742 * As userspace needs to retrieve information about the performance counters
743 * available, this IOCTL allows users to get information about a performance
744 * counter (name, category and description).
745 */
746struct drm_v3d_perfmon_get_counter {
747 /*
748 * Counter ID
749 *
750 * Must be smaller than the maximum number of performance counters, which
751 * can be retrieve through DRM_V3D_PARAM_MAX_PERF_COUNTERS.
752 */
753 __u8 counter;
754
755 /* Name of the counter */
756 __u8 name[DRM_V3D_PERFCNT_MAX_NAME];
757
758 /* Category of the counter */
759 __u8 category[DRM_V3D_PERFCNT_MAX_CATEGORY];
760
761 /* Description of the counter */
762 __u8 description[DRM_V3D_PERFCNT_MAX_DESCRIPTION];
763
764 /* mbz */
765 __u8 reserved[7];
766};
767
720#if defined(__cplusplus)768#if defined(__cplusplus)
721}769}
722#endif770#endif
include/uapi/linux/dma-heap.h+1−1
@@ -19,7 +19,7 @@ · 18 unmodified lines
19#define DMA_HEAP_VALID_FD_FLAGS (O_CLOEXEC | O_ACCMODE)19#define DMA_HEAP_VALID_FD_FLAGS (O_CLOEXEC | O_ACCMODE)
20 20
21/* Currently no heap flags */21/* Currently no heap flags */
22#define DMA_HEAP_VALID_HEAP_FLAGS (0)22#define DMA_HEAP_VALID_HEAP_FLAGS (0ULL)
23 23
24/**24/**
25 * struct dma_heap_allocation_data - metadata passed from userspace for25 * struct dma_heap_allocation_data - metadata passed from userspace for