Pull drm updates from Dave Airlie: "Highlights are support for privacy screens found in new laptops, a bunch of nomodeset refactoring, and i915 enables ADL-P systems by default, while starting to add RPL-S support. vmwgfx adds GEM and support for OpenGL 4.3 features in userspace. Lots of internal refactorings around dma reservations, and lots of driver refactoring as well. Summary: core: - add privacy screen support - move nomodeset option into drm subsystem - clean up nomodeset handling in drivers - make drm_irq.c legacy - fix stack_depot name conflicts - remove DMA_BUF_SET_NAME ioctl restrictions - sysfs: send hotplug event - replace several DRM_* logging macros with drm_* - move hashtable to legacy code - add error return from gem_create_object - cma-helper: improve interfaces, drop CONFIG_DRM_KMS_CMA_HELPER - kernel.h related include cleanups - support XRGB2101010 source buffers ttm: - don't include drm hashtable - stop pruning fences after wait - documentation updates dma-buf: - add dma_resv selftest - add debugfs helpers - remove dma_resv_get_excl_unlocked - documentation - make fences mandatory in dma_resv_add_excl_fence dp: - add link training delay helpers gem: - link shmem/cma helpers into separate modules - use dma_resv iteratior - import dma-buf namespace into gem helper modules scheduler: - fence grab fix - lockdep fixes bridge: - switch to managed MIPI DSI helpers - register and attach during probe fixes - convert to YAML in several places. panel: - add bunch of new panesl simpledrm: - support FB_DAMAGE_CLIPS - support virtual screen sizes - add Apple M1 support amdgpu: - enable seamless boot for DCN 3.01 - runtime PM fixes - use drm_kms_helper_connector_hotplug_event - get all fences at once - use generic drm fb helpers - PSR/DPCD/LTTPR/DSC/PM/RAS/OLED/SRIOV fixes - add smart trace buffer (STB) for supported GPUs - display debugfs entries - new SMU debug option - Documentation update amdkfd: - IP discovery enumeration refactor - interface between driver fixes - SVM fixes - kfd uapi header to define some sysfs bitfields. i915: - support VESA panel backlights - enable ADL-P by default - add eDP privacy screen support - add Raptor Lake S (RPL-S) support - DG2 page table support - lots of GuC/HuC fw refactoring - refactored i915->gt interfaces - CD clock squashing support - enable 10-bit gamma support - update ADL-P DMC fw to v2.14 - enable runtime PM autosuspend by default - ADL-P DSI support - per-lane DP drive settings for ICL+ - add support for pipe C/D DMC firmware - Atomic gamma LUT updates - remove CCS FB stride restrictions on ADL-P - VRR platform support for display 11 - add support for display audio codec keepalive - lots of display refactoring - fix runtime PM handling during PXP suspend - improved eviction performance with async TTM moves - async VMA unbinding improvements - VMA locking refactoring - improved error capture robustness - use per device iommu checks - drop bits stealing from i915_sw_fence function ptr - remove dma_resv_prune - add IC cache invalidation on DG2 nouveau: - crc fixes - validate LUTs in atomic check - set HDMI AVI RGB quant to full tegra: - buffer objects reworks for dma-buf compat - NVDEC driver uAPI support - power management improvements etnaviv: - IOMMU enabled system support - fix > 4GB command buffer mapping - close a DoS vector - fix spurious GPU resets ast: - fix i2c initialization rcar-du: - DSI output support exynos: - replace legacy gpio interface - implement generic GEM object mmap msm: - dpu plane state cleanup in prep for multirect - dpu debugfs cleanups - dp support for sc7280 - a506 support - removal of struct_mutex - remove old eDP sub-driver anx7625: - support MIPI DSI input - support HDMI audio - fix reading EDID lvds: - fix bridge DT bindings megachips: - probe both bridges before registering dw-hdmi: - allow interlace on bridge ps8640: - enable runtime PM - support aux-bus tx358768: - enable reference clock - add pulse mode support ti-sn65dsi86: - use regmap bulk write - add PWM support etnaviv: - get all fences at once gma500: - gem object cleanups kmb: - enable fb console radeon: - use dma_resv_wait_timeout rockchip: - add DSP hold timeout - suspend/resume fixes - PLL clock fixes - implement mmap in GEM object functions - use generic fbdev emulation sun4i: - use CMA helpers without vmap support vc4: - fix HDMI-CEC hang with display is off - power on HDMI controller while disabling - support 4K@60Hz modes - support 10-bit YUV 4:2:0 output vmwgfx: - fix leak on probe errors - fail probing on broken hosts - new placement for MOB page tables - hide internal BOs from userspace - implement GEM support - implement GL 4.3 support virtio: - overflow fixes xen: - implement mmap as GEM object function omapdrm: - fix scatterlist export - support virtual planes mediatek: - MT8192 support - CMDQ refinement" * tag 'drm-next-2022-01-07' of git://anongit.freedesktop.org/drm/drm: (1241 commits) drm/amdgpu: no DC support for headless chips drm/amd/display: fix dereference before NULL check drm/amdgpu: always reset the asic in suspend (v2) drm/amdgpu: put SMU into proper state on runpm suspending for BOCO capable platform drm/amd/display: Fix the uninitialized variable in enable_stream_features() drm/amdgpu: fix runpm documentation amdgpu/pm: Make sysfs pm attributes as read-only for VFs drm/amdgpu: save error count in RAS poison handler drm/amdgpu: drop redundant semicolon drm/amd/display: get and restore link res map drm/amd/display: support dynamic HPO DP link encoder allocation drm/amd/display: access hpo dp link encoder only through link resource drm/amd/display: populate link res in both detection and validation drm/amd/display: define link res and make it accessible to all link interfaces drm/amd/display: 3.2.167 drm/amd/display: [FW Promotion] Release 0.0.98 drm/amd/display: Undo ODM combine drm/amd/display: Add reg defs for DCN303 drm/amd/display: Changed pipe split policy to allow for multi-display pipe split drm/amd/display: Set optimize_pwr_state for DCN31 ...
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| @@ -80,7 +80,7 @@ extern "C" { · 79 unmodified lines | ||
| 80 | 80 | * |
| 81 | 81 | * %AMDGPU_GEM_DOMAIN_GTT GPU accessible system memory, mapped into the |
| 82 | 82 | * GPU's virtual address space via gart. Gart memory linearizes non-contiguous |
| 83 | − * pages of system memory, allows GPU access system memory in a linezrized | |
| 83 | + * pages of system memory, allows GPU access system memory in a linearized | |
| 84 | 84 | * fashion. |
| 85 | 85 | * |
| 86 | 86 | * %AMDGPU_GEM_DOMAIN_VRAM Local video memory. For APUs, it is memory |
| @@ -1096,6 +1096,24 @@ extern "C" { · 1095 unmodified lines | ||
| 1096 | 1096 | #define DRM_IOCTL_SYNCOBJ_TRANSFER DRM_IOWR(0xCC, struct drm_syncobj_transfer) |
| 1097 | 1097 | #define DRM_IOCTL_SYNCOBJ_TIMELINE_SIGNAL DRM_IOWR(0xCD, struct drm_syncobj_timeline_array) |
| 1098 | 1098 | |
| 1099 | +/** | |
| 1100 | + * DRM_IOCTL_MODE_GETFB2 - Get framebuffer metadata. | |
| 1101 | + * | |
| 1102 | + * This queries metadata about a framebuffer. User-space fills | |
| 1103 | + * &drm_mode_fb_cmd2.fb_id as the input, and the kernels fills the rest of the | |
| 1104 | + * struct as the output. | |
| 1105 | + * | |
| 1106 | + * If the client is DRM master or has &CAP_SYS_ADMIN, &drm_mode_fb_cmd2.handles | |
| 1107 | + * will be filled with GEM buffer handles. Planes are valid until one has a | |
| 1108 | + * zero handle -- this can be used to compute the number of planes. | |
| 1109 | + * | |
| 1110 | + * Otherwise, &drm_mode_fb_cmd2.handles will be zeroed and planes are valid | |
| 1111 | + * until one has a zero &drm_mode_fb_cmd2.pitches. | |
| 1112 | + * | |
| 1113 | + * If the framebuffer has a format modifier, &DRM_MODE_FB_MODIFIERS will be set | |
| 1114 | + * in &drm_mode_fb_cmd2.flags and &drm_mode_fb_cmd2.modifier will contain the | |
| 1115 | + * modifier. Otherwise, user-space must ignore &drm_mode_fb_cmd2.modifier. | |
| 1116 | + */ | |
| 1099 | 1117 | #define DRM_IOCTL_MODE_GETFB2 DRM_IOWR(0xCE, struct drm_mode_fb_cmd2) |
| 1100 | 1118 | |
| 1101 | 1119 | /* |
| @@ -314,6 +314,13 @@ extern "C" { · 313 unmodified lines | ||
| 314 | 314 | */ |
| 315 | 315 | #define DRM_FORMAT_P016 fourcc_code('P', '0', '1', '6') /* 2x2 subsampled Cr:Cb plane 16 bits per channel */ |
| 316 | 316 | |
| 317 | +/* 2 plane YCbCr420. | |
| 318 | + * 3 10 bit components and 2 padding bits packed into 4 bytes. | |
| 319 | + * index 0 = Y plane, [31:0] x:Y2:Y1:Y0 2:10:10:10 little endian | |
| 320 | + * index 1 = Cr:Cb plane, [63:0] x:Cr2:Cb2:Cr1:x:Cb1:Cr0:Cb0 [2:10:10:10:2:10:10:10] little endian | |
| 321 | + */ | |
| 322 | +#define DRM_FORMAT_P030 fourcc_code('P', '0', '3', '0') /* 2x2 subsampled Cr:Cb plane 10 bits per channel packed */ | |
| 323 | + | |
| 317 | 324 | /* 3 plane non-subsampled (444) YCbCr |
| 318 | 325 | * 16 bits per component, but only 10 bits are used and 6 bits are padded |
| 319 | 326 | * index 0: Y plane, [15:0] Y:x [10:6] little endian |
| @@ -854,6 +861,10 @@ drm_fourcc_canonicalize_nvidia_format_mod(__u64 modifier) · 534 unmodified lines | ||
| 854 | 861 | * and UV. Some SAND-using hardware stores UV in a separate tiled |
| 855 | 862 | * image from Y to reduce the column height, which is not supported |
| 856 | 863 | * with these modifiers. |
| 864 | + * | |
| 865 | + * The DRM_FORMAT_MOD_BROADCOM_SAND128_COL_HEIGHT modifier is also | |
| 866 | + * supported for DRM_FORMAT_P030 where the columns remain as 128 bytes | |
| 867 | + * wide, but as this is a 10 bpp format that translates to 96 pixels. | |
| 857 | 868 | */ |
| 858 | 869 | |
| 859 | 870 | #define DRM_FORMAT_MOD_BROADCOM_SAND32_COL_HEIGHT(v) \ |
| @@ -110,6 +110,7 @@ extern "C" { · 109 unmodified lines | ||
| 110 | 110 | #define DRM_VMW_PARAM_HW_CAPS2 13 |
| 111 | 111 | #define DRM_VMW_PARAM_SM4_1 14 |
| 112 | 112 | #define DRM_VMW_PARAM_SM5 15 |
| 113 | +#define DRM_VMW_PARAM_GL43 16 | |
| 113 | 114 | |
| 114 | 115 | /** |
| 115 | 116 | * enum drm_vmw_handle_type - handle type for ref ioctls |
| @@ -0,0 +1,108 @@ | ||
| 1 | +/* SPDX-License-Identifier: GPL-2.0 OR MIT WITH Linux-syscall-note */ | |
| 2 | +/* | |
| 3 | + * Copyright 2021 Advanced Micro Devices, Inc. | |
| 4 | + * | |
| 5 | + * Permission is hereby granted, free of charge, to any person obtaining a | |
| 6 | + * copy of this software and associated documentation files (the "Software"), | |
| 7 | + * to deal in the Software without restriction, including without limitation | |
| 8 | + * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
| 9 | + * and/or sell copies of the Software, and to permit persons to whom the | |
| 10 | + * Software is furnished to do so, subject to the following conditions: | |
| 11 | + * | |
| 12 | + * The above copyright notice and this permission notice shall be included in | |
| 13 | + * all copies or substantial portions of the Software. | |
| 14 | + * | |
| 15 | + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
| 16 | + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
| 17 | + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
| 18 | + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
| 19 | + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
| 20 | + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
| 21 | + * OTHER DEALINGS IN THE SOFTWARE. | |
| 22 | + */ | |
| 23 | + | |
| 24 | +#ifndef KFD_SYSFS_H_INCLUDED | |
| 25 | +#define KFD_SYSFS_H_INCLUDED | |
| 26 | + | |
| 27 | +/* Capability bits in node properties */ | |
| 28 | +#define HSA_CAP_HOT_PLUGGABLE 0x00000001 | |
| 29 | +#define HSA_CAP_ATS_PRESENT 0x00000002 | |
| 30 | +#define HSA_CAP_SHARED_WITH_GRAPHICS 0x00000004 | |
| 31 | +#define HSA_CAP_QUEUE_SIZE_POW2 0x00000008 | |
| 32 | +#define HSA_CAP_QUEUE_SIZE_32BIT 0x00000010 | |
| 33 | +#define HSA_CAP_QUEUE_IDLE_EVENT 0x00000020 | |
| 34 | +#define HSA_CAP_VA_LIMIT 0x00000040 | |
| 35 | +#define HSA_CAP_WATCH_POINTS_SUPPORTED 0x00000080 | |
| 36 | +#define HSA_CAP_WATCH_POINTS_TOTALBITS_MASK 0x00000f00 | |
| 37 | +#define HSA_CAP_WATCH_POINTS_TOTALBITS_SHIFT 8 | |
| 38 | +#define HSA_CAP_DOORBELL_TYPE_TOTALBITS_MASK 0x00003000 | |
| 39 | +#define HSA_CAP_DOORBELL_TYPE_TOTALBITS_SHIFT 12 | |
| 40 | + | |
| 41 | +#define HSA_CAP_DOORBELL_TYPE_PRE_1_0 0x0 | |
| 42 | +#define HSA_CAP_DOORBELL_TYPE_1_0 0x1 | |
| 43 | +#define HSA_CAP_DOORBELL_TYPE_2_0 0x2 | |
| 44 | +#define HSA_CAP_AQL_QUEUE_DOUBLE_MAP 0x00004000 | |
| 45 | + | |
| 46 | +/* Old buggy user mode depends on this being 0 */ | |
| 47 | +#define HSA_CAP_RESERVED_WAS_SRAM_EDCSUPPORTED 0x00080000 | |
| 48 | + | |
| 49 | +#define HSA_CAP_MEM_EDCSUPPORTED 0x00100000 | |
| 50 | +#define HSA_CAP_RASEVENTNOTIFY 0x00200000 | |
| 51 | +#define HSA_CAP_ASIC_REVISION_MASK 0x03c00000 | |
| 52 | +#define HSA_CAP_ASIC_REVISION_SHIFT 22 | |
| 53 | +#define HSA_CAP_SRAM_EDCSUPPORTED 0x04000000 | |
| 54 | +#define HSA_CAP_SVMAPI_SUPPORTED 0x08000000 | |
| 55 | +#define HSA_CAP_FLAGS_COHERENTHOSTACCESS 0x10000000 | |
| 56 | +#define HSA_CAP_RESERVED 0xe00f8000 | |
| 57 | + | |
| 58 | +/* Heap types in memory properties */ | |
| 59 | +#define HSA_MEM_HEAP_TYPE_SYSTEM 0 | |
| 60 | +#define HSA_MEM_HEAP_TYPE_FB_PUBLIC 1 | |
| 61 | +#define HSA_MEM_HEAP_TYPE_FB_PRIVATE 2 | |
| 62 | +#define HSA_MEM_HEAP_TYPE_GPU_GDS 3 | |
| 63 | +#define HSA_MEM_HEAP_TYPE_GPU_LDS 4 | |
| 64 | +#define HSA_MEM_HEAP_TYPE_GPU_SCRATCH 5 | |
| 65 | + | |
| 66 | +/* Flag bits in memory properties */ | |
| 67 | +#define HSA_MEM_FLAGS_HOT_PLUGGABLE 0x00000001 | |
| 68 | +#define HSA_MEM_FLAGS_NON_VOLATILE 0x00000002 | |
| 69 | +#define HSA_MEM_FLAGS_RESERVED 0xfffffffc | |
| 70 | + | |
| 71 | +/* Cache types in cache properties */ | |
| 72 | +#define HSA_CACHE_TYPE_DATA 0x00000001 | |
| 73 | +#define HSA_CACHE_TYPE_INSTRUCTION 0x00000002 | |
| 74 | +#define HSA_CACHE_TYPE_CPU 0x00000004 | |
| 75 | +#define HSA_CACHE_TYPE_HSACU 0x00000008 | |
| 76 | +#define HSA_CACHE_TYPE_RESERVED 0xfffffff0 | |
| 77 | + | |
| 78 | +/* Link types in IO link properties (matches CRAT link types) */ | |
| 79 | +#define HSA_IOLINK_TYPE_UNDEFINED 0 | |
| 80 | +#define HSA_IOLINK_TYPE_HYPERTRANSPORT 1 | |
| 81 | +#define HSA_IOLINK_TYPE_PCIEXPRESS 2 | |
| 82 | +#define HSA_IOLINK_TYPE_AMBA 3 | |
| 83 | +#define HSA_IOLINK_TYPE_MIPI 4 | |
| 84 | +#define HSA_IOLINK_TYPE_QPI_1_1 5 | |
| 85 | +#define HSA_IOLINK_TYPE_RESERVED1 6 | |
| 86 | +#define HSA_IOLINK_TYPE_RESERVED2 7 | |
| 87 | +#define HSA_IOLINK_TYPE_RAPID_IO 8 | |
| 88 | +#define HSA_IOLINK_TYPE_INFINIBAND 9 | |
| 89 | +#define HSA_IOLINK_TYPE_RESERVED3 10 | |
| 90 | +#define HSA_IOLINK_TYPE_XGMI 11 | |
| 91 | +#define HSA_IOLINK_TYPE_XGOP 12 | |
| 92 | +#define HSA_IOLINK_TYPE_GZ 13 | |
| 93 | +#define HSA_IOLINK_TYPE_ETHERNET_RDMA 14 | |
| 94 | +#define HSA_IOLINK_TYPE_RDMA_OTHER 15 | |
| 95 | +#define HSA_IOLINK_TYPE_OTHER 16 | |
| 96 | + | |
| 97 | +/* Flag bits in IO link properties (matches CRAT flags, excluding the | |
| 98 | + * bi-directional flag, which is not offially part of the CRAT spec, and | |
| 99 | + * only used internally in KFD) | |
| 100 | + */ | |
| 101 | +#define HSA_IOLINK_FLAGS_ENABLED (1 << 0) | |
| 102 | +#define HSA_IOLINK_FLAGS_NON_COHERENT (1 << 1) | |
| 103 | +#define HSA_IOLINK_FLAGS_NO_ATOMICS_32_BIT (1 << 2) | |
| 104 | +#define HSA_IOLINK_FLAGS_NO_ATOMICS_64_BIT (1 << 3) | |
| 105 | +#define HSA_IOLINK_FLAGS_NO_PEER_TO_PEER_DMA (1 << 4) | |
| 106 | +#define HSA_IOLINK_FLAGS_RESERVED 0xffffffe0 | |
| 107 | + | |
| 108 | +#endif | |