History

Merge tag 'amd-drm-next-5.17-2021-12-30' of ssh://gitlab.freedesktop.org/agd5f/linux into drm-next

amd-drm-next-5.17-2021-12-30: amdgpu: - Suspend/resume fixes - Fence fix - Misc code cleanups - IP discovery fixes - SRIOV fixes - RAS fixes - GMC 8 VRAM detection fix - FRU fixes for Aldebaran - Display fixes amdkfd: - SVM fixes - IP discovery fixes

Dave Airlie committed 4 years ago

Commit cb6846f2 parents 011e8c3 0637d4183 files · +1814 −747Browse files

Unified · Split

83 files
  1. drivers/gpu/drm/amd/amdgpu/amdgpu.h +2 −1
  2. drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c +3 −3
  3. drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h +2 −1
  4. drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c +13 −14
  5. drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +29 −17
  6. drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c +55 −23
  7. drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c +23 −4
  8. drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c +87 −39
  9. drivers/gpu/drm/amd/amdgpu/amdgpu_fru_eeprom.c +15 −10
  10. drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c +3 −0
  11. drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h +1 −3
  12. drivers/gpu/drm/amd/amdgpu/amdgpu_umc.c +99 −68
  13. drivers/gpu/drm/amd/amdgpu/amdgpu_umc.h +2 −2
  14. drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c +24 −12
  15. drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h +1 −0
  16. drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c +89 −28
  17. drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c +0 −6
  18. drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c +10 −3
  19. drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c +43 −20
  20. drivers/gpu/drm/amd/amdgpu/psp_v11_0.c +15 −63
  21. drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c +46 −37
  22. drivers/gpu/drm/amd/amdgpu/soc15_common.h +5 −0
  23. drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c +7 −0
  24. drivers/gpu/drm/amd/amdkfd/kfd_device.c +71 −9
  25. drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c +22 −6
  26. drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.h +5 −0
  27. drivers/gpu/drm/amd/amdkfd/kfd_int_process_v9.c +40 −4
  28. drivers/gpu/drm/amd/amdkfd/kfd_migrate.c +1 −1
  29. drivers/gpu/drm/amd/amdkfd/kfd_priv.h +2 −0
  30. drivers/gpu/drm/amd/amdkfd/kfd_svm.c +29 −6
  31. drivers/gpu/drm/amd/amdkfd/kfd_svm.h +2 −1
  32. drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/vg_clk_mgr.c +1 −1
  33. drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c +1 −0
  34. drivers/gpu/drm/amd/display/dc/core/dc.c +0 −18
  35. drivers/gpu/drm/amd/display/dc/core/dc_debug.c +2 −0
  36. drivers/gpu/drm/amd/display/dc/core/dc_link.c +173 −68
  37. drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c +434 −67
  38. drivers/gpu/drm/amd/display/dc/core/dc_link_dpia.c +32 −16
  39. drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c +37 −26
  40. drivers/gpu/drm/amd/display/dc/core/dc_resource.c +127 −72
  41. drivers/gpu/drm/amd/display/dc/dc.h +2 −1
  42. drivers/gpu/drm/amd/display/dc/dc_link.h +12 −3
  43. drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c +4 −10
  44. drivers/gpu/drm/amd/display/dc/dcn10/dcn10_init.c +1 −0
  45. drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c +1 −1
  46. drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c +2 −3
  47. drivers/gpu/drm/amd/display/dc/dcn201/dcn201_hwseq.c +2 −1
  48. drivers/gpu/drm/amd/display/dc/dcn201/dcn201_resource.c +1 −1
  49. drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c +1 −1
  50. drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.c +1 −12
  51. drivers/gpu/drm/amd/display/dc/dcn301/dcn301_resource.c +1 −1
  52. drivers/gpu/drm/amd/display/dc/dcn302/dcn302_resource.c +1 −1
  53. drivers/gpu/drm/amd/display/dc/dcn303/dcn303_dccg.h +18 −2
  54. drivers/gpu/drm/amd/display/dc/dcn303/dcn303_resource.c +1 −1
  55. drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hpo_dp_link_encoder.c +5 −1
  56. drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hpo_dp_link_encoder.h +2 −1
  57. drivers/gpu/drm/amd/display/dc/dcn31/dcn31_init.c +1 −0
  58. drivers/gpu/drm/amd/display/dc/dcn31/dcn31_resource.c +24 −3
  59. drivers/gpu/drm/amd/display/dc/dcn31/dcn31_resource.h +31 −0
  60. drivers/gpu/drm/amd/display/dc/dml/dml_wrapper.c +1 −1
  61. drivers/gpu/drm/amd/display/dc/inc/core_status.h +2 −0
  62. drivers/gpu/drm/amd/display/dc/inc/core_types.h +17 −0
  63. drivers/gpu/drm/amd/display/dc/inc/dc_link_dp.h +11 −4
  64. drivers/gpu/drm/amd/display/dc/inc/dc_link_dpia.h +3 −2
  65. drivers/gpu/drm/amd/display/dc/inc/hw/link_encoder.h +2 −1
  66. drivers/gpu/drm/amd/display/dc/inc/link_hwss.h +8 −2
  67. drivers/gpu/drm/amd/display/dc/inc/resource.h +4 −2
  68. drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h +2 −2
  69. drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c +2 −2
  70. drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_7_2_0_offset.h +0 −2
  71. drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_7_2_0_sh_mask.h +0 −12
  72. drivers/gpu/drm/amd/include/discovery.h +49 −0
  73. drivers/gpu/drm/amd/pm/amdgpu_pm.c +8 −1
  74. drivers/gpu/drm/amd/pm/inc/aldebaran_ppsmc.h +3 −1
  75. drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h +3 −3
  76. drivers/gpu/drm/amd/pm/inc/smu_types.h +2 −1
  77. drivers/gpu/drm/amd/pm/inc/smu_v11_0.h +1 −1
  78. drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c +5 −8
  79. drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c +1 −1
  80. drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c +1 −1
  81. drivers/gpu/drm/amd/pm/swsmu/smu12/smu_v12_0.c +2 −1
  82. drivers/gpu/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c +13 −2
  83. drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c +10 −5
drivers/gpu/drm/amd/amdgpu/amdgpu.h+2−1
@@ -812,6 +812,7 @@ struct amd_powerplay { · 811 unmodified lines
812812
813813 #define AMDGPU_RESET_MAGIC_NUM 64
814814 #define AMDGPU_MAX_DF_PERFMONS 4
815+#define AMDGPU_PRODUCT_NAME_LEN 64
815816 struct amdgpu_device {
816817 struct device *dev;
817818 struct pci_dev *pdev;
@@ -1082,7 +1083,7 @@ struct amdgpu_device { · 264 unmodified lines
10821083
10831084 /* Chip product information */
10841085 char product_number[16];
1085− char product_name[32];
1086+ char product_name[AMDGPU_PRODUCT_NAME_LEN];
10861087 char serial[20];
10871088
10881089 atomic_t throttling_logging_enabled;
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c+3−3
@@ -721,13 +721,13 @@ bool amdgpu_amdkfd_have_atomics_support(struct amdgpu_device *adev) · 720 unmodified lines
721721 return adev->have_atomics_support;
722722 }
723723
724−void amdgpu_amdkfd_ras_poison_consumption_handler(struct amdgpu_device *adev)
724+void amdgpu_amdkfd_ras_poison_consumption_handler(struct amdgpu_device *adev, bool reset)
725725 {
726726 struct ras_err_data err_data = {0, 0, 0, NULL};
727727
728728 /* CPU MCA will handle page retirement if connected_to_cpu is 1 */
729729 if (!adev->gmc.xgmi.connected_to_cpu)
730− amdgpu_umc_process_ras_data_cb(adev, &err_data, NULL);
731− else
730+ amdgpu_umc_poison_handler(adev, &err_data, reset);
731+ else if (reset)
732732 amdgpu_amdkfd_gpu_reset(adev);
733733 }
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h+2−1
@@ -296,7 +296,8 @@ int amdgpu_amdkfd_gpuvm_import_dmabuf(struct amdgpu_device *adev, · 295 unmodified lines
296296 uint64_t *mmap_offset);
297297 int amdgpu_amdkfd_get_tile_config(struct amdgpu_device *adev,
298298 struct tile_config *config);
299−void amdgpu_amdkfd_ras_poison_consumption_handler(struct amdgpu_device *adev);
299+void amdgpu_amdkfd_ras_poison_consumption_handler(struct amdgpu_device *adev,
300+ bool reset);
300301 #if IS_ENABLED(CONFIG_HSA_AMD)
301302 void amdgpu_amdkfd_gpuvm_init_mem_limits(void);
302303 void amdgpu_amdkfd_gpuvm_destroy_cb(struct amdgpu_device *adev,
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c+13−14
@@ -166,7 +166,7 @@ int kgd_gfx_v9_init_interrupts(struct amdgpu_device *adev, uint32_t pipe_id) · 165 unmodified lines
166166
167167 lock_srbm(adev, mec, pipe, 0, 0);
168168
169− WREG32(SOC15_REG_OFFSET(GC, 0, mmCPC_INT_CNTL),
169+ WREG32_SOC15(GC, 0, mmCPC_INT_CNTL,
170170 CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK |
171171 CP_INT_CNTL_RING0__OPCODE_ERROR_INT_ENABLE_MASK);
172172
@@ -279,7 +279,7 @@ int kgd_gfx_v9_hqd_load(struct amdgpu_device *adev, void *mqd, · 106 unmodified lines
279279 lower_32_bits((uintptr_t)wptr));
280280 WREG32_RLC(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR_HI),
281281 upper_32_bits((uintptr_t)wptr));
282− WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_PQ_WPTR_POLL_CNTL1),
282+ WREG32_SOC15(GC, 0, mmCP_PQ_WPTR_POLL_CNTL1,
283283 (uint32_t)get_queue_mask(adev, pipe_id, queue_id));
284284 }
285285
@@ -488,13 +488,13 @@ bool kgd_gfx_v9_hqd_is_occupied(struct amdgpu_device *adev, · 202 unmodified lines
488488 uint32_t low, high;
489489
490490 acquire_queue(adev, pipe_id, queue_id);
491− act = RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_ACTIVE));
491+ act = RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE);
492492 if (act) {
493493 low = lower_32_bits(queue_address >> 8);
494494 high = upper_32_bits(queue_address >> 8);
495495
496− if (low == RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_BASE)) &&
497− high == RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_BASE_HI)))
496+ if (low == RREG32_SOC15(GC, 0, mmCP_HQD_PQ_BASE) &&
497+ high == RREG32_SOC15(GC, 0, mmCP_HQD_PQ_BASE_HI))
498498 retval = true;
499499 }
500500 release_queue(adev);
@@ -556,7 +556,7 @@ int kgd_gfx_v9_hqd_destroy(struct amdgpu_device *adev, void *mqd, · 55 unmodified lines
556556
557557 end_jiffies = (utimeout * HZ / 1000) + jiffies;
558558 while (true) {
559− temp = RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_ACTIVE));
559+ temp = RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE);
560560 if (!(temp & CP_HQD_ACTIVE__ACTIVE_MASK))
561561 break;
562562 if (time_after(jiffies, end_jiffies)) {
@@ -645,7 +645,7 @@ int kgd_gfx_v9_wave_control_execute(struct amdgpu_device *adev, · 82 unmodified lines
645645 mutex_lock(&adev->grbm_idx_mutex);
646646
647647 WREG32_SOC15_RLC_SHADOW(GC, 0, mmGRBM_GFX_INDEX, gfx_index_val);
648− WREG32(SOC15_REG_OFFSET(GC, 0, mmSQ_CMD), sq_cmd);
648+ WREG32_SOC15(GC, 0, mmSQ_CMD, sq_cmd);
649649
650650 data = REG_SET_FIELD(data, GRBM_GFX_INDEX,
651651 INSTANCE_BROADCAST_WRITES, 1);
@@ -722,7 +722,7 @@ static void get_wave_count(struct amdgpu_device *adev, int queue_idx, · 70 unmodified lines
722722 pipe_idx = queue_idx / adev->gfx.mec.num_queue_per_pipe;
723723 queue_slot = queue_idx % adev->gfx.mec.num_queue_per_pipe;
724724 soc15_grbm_select(adev, 1, pipe_idx, queue_slot, 0);
725− reg_val = RREG32(SOC15_REG_OFFSET(GC, 0, mmSPI_CSQ_WF_ACTIVE_COUNT_0) +
725+ reg_val = RREG32_SOC15_IP(GC, SOC15_REG_OFFSET(GC, 0, mmSPI_CSQ_WF_ACTIVE_COUNT_0) +
726726 queue_slot);
727727 *wave_cnt = reg_val & SPI_CSQ_WF_ACTIVE_COUNT_0__COUNT_MASK;
728728 if (*wave_cnt != 0)
@@ -809,8 +809,7 @@ void kgd_gfx_v9_get_cu_occupancy(struct amdgpu_device *adev, int pasid, · 80 unmodified lines
809809 for (sh_idx = 0; sh_idx < sh_cnt; sh_idx++) {
810810
811811 gfx_v9_0_select_se_sh(adev, se_idx, sh_idx, 0xffffffff);
812− queue_map = RREG32(SOC15_REG_OFFSET(GC, 0,
813− mmSPI_CSQ_WF_ACTIVE_STATUS));
812+ queue_map = RREG32_SOC15(GC, 0, mmSPI_CSQ_WF_ACTIVE_STATUS);
814813
815814 /*
816815 * Assumption: queue map encodes following schema: four
@@ -860,17 +859,17 @@ void kgd_gfx_v9_program_trap_handler_settings(struct amdgpu_device *adev, · 43 unmodified lines
860859 /*
861860 * Program TBA registers
862861 */
863− WREG32(SOC15_REG_OFFSET(GC, 0, mmSQ_SHADER_TBA_LO),
862+ WREG32_SOC15(GC, 0, mmSQ_SHADER_TBA_LO,
864863 lower_32_bits(tba_addr >> 8));
865− WREG32(SOC15_REG_OFFSET(GC, 0, mmSQ_SHADER_TBA_HI),
864+ WREG32_SOC15(GC, 0, mmSQ_SHADER_TBA_HI,
866865 upper_32_bits(tba_addr >> 8));
867866
868867 /*
869868 * Program TMA registers
870869 */
871− WREG32(SOC15_REG_OFFSET(GC, 0, mmSQ_SHADER_TMA_LO),
870+ WREG32_SOC15(GC, 0, mmSQ_SHADER_TMA_LO,
872871 lower_32_bits(tma_addr >> 8));
873− WREG32(SOC15_REG_OFFSET(GC, 0, mmSQ_SHADER_TMA_HI),
872+ WREG32_SOC15(GC, 0, mmSQ_SHADER_TMA_HI,
874873 upper_32_bits(tma_addr >> 8));
875874
876875 unlock_srbm(adev);
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c+29−17
@@ -2317,6 +2317,10 @@ static int amdgpu_device_ip_init(struct amdgpu_device *adev) · 2316 unmodified lines
23172317
23182318 /* need to do gmc hw init early so we can allocate gpu mem */
23192319 if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC) {
2320+ /* Try to reserve bad pages early */
2321+ if (amdgpu_sriov_vf(adev))
2322+ amdgpu_virt_exchange_data(adev);
2323+
23202324 r = amdgpu_device_vram_scratch_init(adev);
23212325 if (r) {
23222326 DRM_ERROR("amdgpu_vram_scratch_init failed %d\n", r);
@@ -2348,7 +2352,7 @@ static int amdgpu_device_ip_init(struct amdgpu_device *adev) · 25 unmodified lines
23482352 }
23492353
23502354 if (amdgpu_sriov_vf(adev))
2351− amdgpu_virt_init_data_exchange(adev);
2355+ amdgpu_virt_exchange_data(adev);
23522356
23532357 r = amdgpu_ib_pool_init(adev);
23542358 if (r) {
@@ -2615,11 +2619,10 @@ static int amdgpu_device_ip_late_init(struct amdgpu_device *adev) · 260 unmodified lines
26152619 if (r)
26162620 DRM_ERROR("enable mgpu fan boost failed (%d).\n", r);
26172621
2618− /* For XGMI + passthrough configuration on arcturus, enable light SBR */
2619− if (adev->asic_type == CHIP_ARCTURUS &&
2620− amdgpu_passthrough(adev) &&
2621− adev->gmc.xgmi.num_physical_nodes > 1)
2622− smu_set_light_sbr(&adev->smu, true);
2622+ /* For passthrough configuration on arcturus and aldebaran, enable special handling SBR */
2623+ if (amdgpu_passthrough(adev) && ((adev->asic_type == CHIP_ARCTURUS && adev->gmc.xgmi.num_physical_nodes > 1)||
2624+ adev->asic_type == CHIP_ALDEBARAN ))
2625+ smu_handle_passthrough_sbr(&adev->smu, true);
26232626
26242627 if (adev->gmc.xgmi.num_physical_nodes > 1) {
26252628 mutex_lock(&mgpu_info.mutex);
@@ -3182,6 +3185,12 @@ static void amdgpu_device_detect_sriov_bios(struct amdgpu_device *adev) · 556 unmodified lines
31823185 bool amdgpu_device_asic_has_dc_support(enum amd_asic_type asic_type)
31833186 {
31843187 switch (asic_type) {
3188+#ifdef CONFIG_DRM_AMDGPU_SI
3189+ case CHIP_HAINAN:
3190+#endif
3191+ case CHIP_TOPAZ:
3192+ /* chips with no display hardware */
3193+ return false;
31853194 #if defined(CONFIG_DRM_AMD_DC)
31863195 case CHIP_TAHITI:
31873196 case CHIP_PITCAIRN:
@@ -3573,6 +3582,13 @@ int amdgpu_device_init(struct amdgpu_device *adev, · 385 unmodified lines
35733582 if (r)
35743583 return r;
35753584
3585+ /* Need to get xgmi info early to decide the reset behavior*/
3586+ if (adev->gmc.xgmi.supported) {
3587+ r = adev->gfxhub.funcs->get_xgmi_info(adev);
3588+ if (r)
3589+ return r;
3590+ }
3591+
35763592 /* enable PCIE atomic ops */
35773593 if (amdgpu_sriov_vf(adev))
35783594 adev->have_atomics_support = ((struct amd_sriov_msg_pf2vf_info *)
@@ -3885,11 +3901,14 @@ void amdgpu_device_fini_hw(struct amdgpu_device *adev) · 306 unmodified lines
38853901
38863902 amdgpu_irq_fini_hw(adev);
38873903
3888− ttm_device_clear_dma_mappings(&adev->mman.bdev);
3904+ if (adev->mman.initialized)
3905+ ttm_device_clear_dma_mappings(&adev->mman.bdev);
38893906
38903907 amdgpu_gart_dummy_page_fini(adev);
38913908
3892− amdgpu_device_unmap_mmio(adev);
3909+ if (drm_dev_is_unplugged(adev_to_drm(adev)))
3910+ amdgpu_device_unmap_mmio(adev);
3911+
38933912 }
38943913
38953914 void amdgpu_device_fini_sw(struct amdgpu_device *adev)
@@ -4507,7 +4526,7 @@ int amdgpu_device_mode1_reset(struct amdgpu_device *adev) · 611 unmodified lines
45074526 int amdgpu_device_pre_asic_reset(struct amdgpu_device *adev,
45084527 struct amdgpu_reset_context *reset_context)
45094528 {
4510− int i, j, r = 0;
4529+ int i, r = 0;
45114530 struct amdgpu_job *job = NULL;
45124531 bool need_full_reset =
45134532 test_bit(AMDGPU_NEED_FULL_RESET, &reset_context->flags);
@@ -4529,15 +4548,8 @@ int amdgpu_device_pre_asic_reset(struct amdgpu_device *adev, · 15 unmodified lines
45294548
45304549 /*clear job fence from fence drv to avoid force_completion
45314550 *leave NULL and vm flush fence in fence drv */
4532− for (j = 0; j <= ring->fence_drv.num_fences_mask; j++) {
4533− struct dma_fence *old, **ptr;
4551+ amdgpu_fence_driver_clear_job_fences(ring);
45344552
4535− ptr = &ring->fence_drv.fences[j];
4536− old = rcu_dereference_protected(*ptr, 1);
4537− if (old && test_bit(AMDGPU_FENCE_FLAG_EMBED_IN_JOB_BIT, &old->flags)) {
4538− RCU_INIT_POINTER(*ptr, NULL);
4539− }
4540− }
45414553 /* after all hw jobs are reset, hw fence is meaningless, so force_completion */
45424554 amdgpu_fence_driver_force_completion(ring);
45434555 }
drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c+55−23
@@ -565,10 +565,15 @@ void amdgpu_discovery_harvest_ip(struct amdgpu_device *adev) · 564 unmodified lines
565565 }
566566 }
567567
568+union gc_info {
569+ struct gc_info_v1_0 v1;
570+ struct gc_info_v2_0 v2;
571+};
572+
568573 int amdgpu_discovery_get_gfx_info(struct amdgpu_device *adev)
569574 {
570575 struct binary_header *bhdr;
571− struct gc_info_v1_0 *gc_info;
576+ union gc_info *gc_info;
572577
573578 if (!adev->mman.discovery_bin) {
574579 DRM_ERROR("ip discovery uninitialized\n");
@@ -576,28 +581,55 @@ int amdgpu_discovery_get_gfx_info(struct amdgpu_device *adev) · 1 unmodified line
576581 }
577582
578583 bhdr = (struct binary_header *)adev->mman.discovery_bin;
579− gc_info = (struct gc_info_v1_0 *)(adev->mman.discovery_bin +
584+ gc_info = (union gc_info *)(adev->mman.discovery_bin +
580585 le16_to_cpu(bhdr->table_list[GC].offset));
581−
582− adev->gfx.config.max_shader_engines = le32_to_cpu(gc_info->gc_num_se);
583− adev->gfx.config.max_cu_per_sh = 2 * (le32_to_cpu(gc_info->gc_num_wgp0_per_sa) +
584− le32_to_cpu(gc_info->gc_num_wgp1_per_sa));
585− adev->gfx.config.max_sh_per_se = le32_to_cpu(gc_info->gc_num_sa_per_se);
586− adev->gfx.config.max_backends_per_se = le32_to_cpu(gc_info->gc_num_rb_per_se);
587− adev->gfx.config.max_texture_channel_caches = le32_to_cpu(gc_info->gc_num_gl2c);
588− adev->gfx.config.max_gprs = le32_to_cpu(gc_info->gc_num_gprs);
589− adev->gfx.config.max_gs_threads = le32_to_cpu(gc_info->gc_num_max_gs_thds);
590− adev->gfx.config.gs_vgt_table_depth = le32_to_cpu(gc_info->gc_gs_table_depth);
591− adev->gfx.config.gs_prim_buffer_depth = le32_to_cpu(gc_info->gc_gsprim_buff_depth);
592− adev->gfx.config.double_offchip_lds_buf = le32_to_cpu(gc_info->gc_double_offchip_lds_buffer);
593− adev->gfx.cu_info.wave_front_size = le32_to_cpu(gc_info->gc_wave_size);
594− adev->gfx.cu_info.max_waves_per_simd = le32_to_cpu(gc_info->gc_max_waves_per_simd);
595− adev->gfx.cu_info.max_scratch_slots_per_cu = le32_to_cpu(gc_info->gc_max_scratch_slots_per_cu);
596− adev->gfx.cu_info.lds_size = le32_to_cpu(gc_info->gc_lds_size);
597− adev->gfx.config.num_sc_per_sh = le32_to_cpu(gc_info->gc_num_sc_per_se) /
598− le32_to_cpu(gc_info->gc_num_sa_per_se);
599− adev->gfx.config.num_packer_per_sc = le32_to_cpu(gc_info->gc_num_packer_per_sc);
600−
586+ switch (gc_info->v1.header.version_major) {
587+ case 1:
588+ adev->gfx.config.max_shader_engines = le32_to_cpu(gc_info->v1.gc_num_se);
589+ adev->gfx.config.max_cu_per_sh = 2 * (le32_to_cpu(gc_info->v1.gc_num_wgp0_per_sa) +
590+ le32_to_cpu(gc_info->v1.gc_num_wgp1_per_sa));
591+ adev->gfx.config.max_sh_per_se = le32_to_cpu(gc_info->v1.gc_num_sa_per_se);
592+ adev->gfx.config.max_backends_per_se = le32_to_cpu(gc_info->v1.gc_num_rb_per_se);
593+ adev->gfx.config.max_texture_channel_caches = le32_to_cpu(gc_info->v1.gc_num_gl2c);
594+ adev->gfx.config.max_gprs = le32_to_cpu(gc_info->v1.gc_num_gprs);
595+ adev->gfx.config.max_gs_threads = le32_to_cpu(gc_info->v1.gc_num_max_gs_thds);
596+ adev->gfx.config.gs_vgt_table_depth = le32_to_cpu(gc_info->v1.gc_gs_table_depth);
597+ adev->gfx.config.gs_prim_buffer_depth = le32_to_cpu(gc_info->v1.gc_gsprim_buff_depth);
598+ adev->gfx.config.double_offchip_lds_buf = le32_to_cpu(gc_info->v1.gc_double_offchip_lds_buffer);
599+ adev->gfx.cu_info.wave_front_size = le32_to_cpu(gc_info->v1.gc_wave_size);
600+ adev->gfx.cu_info.max_waves_per_simd = le32_to_cpu(gc_info->v1.gc_max_waves_per_simd);
601+ adev->gfx.cu_info.max_scratch_slots_per_cu = le32_to_cpu(gc_info->v1.gc_max_scratch_slots_per_cu);
602+ adev->gfx.cu_info.lds_size = le32_to_cpu(gc_info->v1.gc_lds_size);
603+ adev->gfx.config.num_sc_per_sh = le32_to_cpu(gc_info->v1.gc_num_sc_per_se) /
604+ le32_to_cpu(gc_info->v1.gc_num_sa_per_se);
605+ adev->gfx.config.num_packer_per_sc = le32_to_cpu(gc_info->v1.gc_num_packer_per_sc);
606+ break;
607+ case 2:
608+ adev->gfx.config.max_shader_engines = le32_to_cpu(gc_info->v2.gc_num_se);
609+ adev->gfx.config.max_cu_per_sh = le32_to_cpu(gc_info->v2.gc_num_cu_per_sh);
610+ adev->gfx.config.max_sh_per_se = le32_to_cpu(gc_info->v2.gc_num_sh_per_se);
611+ adev->gfx.config.max_backends_per_se = le32_to_cpu(gc_info->v2.gc_num_rb_per_se);
612+ adev->gfx.config.max_texture_channel_caches = le32_to_cpu(gc_info->v2.gc_num_tccs);
613+ adev->gfx.config.max_gprs = le32_to_cpu(gc_info->v2.gc_num_gprs);
614+ adev->gfx.config.max_gs_threads = le32_to_cpu(gc_info->v2.gc_num_max_gs_thds);
615+ adev->gfx.config.gs_vgt_table_depth = le32_to_cpu(gc_info->v2.gc_gs_table_depth);
616+ adev->gfx.config.gs_prim_buffer_depth = le32_to_cpu(gc_info->v2.gc_gsprim_buff_depth);
617+ adev->gfx.config.double_offchip_lds_buf = le32_to_cpu(gc_info->v2.gc_double_offchip_lds_buffer);
618+ adev->gfx.cu_info.wave_front_size = le32_to_cpu(gc_info->v2.gc_wave_size);
619+ adev->gfx.cu_info.max_waves_per_simd = le32_to_cpu(gc_info->v2.gc_max_waves_per_simd);
620+ adev->gfx.cu_info.max_scratch_slots_per_cu = le32_to_cpu(gc_info->v2.gc_max_scratch_slots_per_cu);
621+ adev->gfx.cu_info.lds_size = le32_to_cpu(gc_info->v2.gc_lds_size);
622+ adev->gfx.config.num_sc_per_sh = le32_to_cpu(gc_info->v2.gc_num_sc_per_se) /
623+ le32_to_cpu(gc_info->v2.gc_num_sh_per_se);
624+ adev->gfx.config.num_packer_per_sc = le32_to_cpu(gc_info->v2.gc_num_packer_per_sc);
625+ break;
626+ default:
627+ dev_err(adev->dev,
628+ "Unhandled GC info table %d.%d\n",
629+ gc_info->v1.header.version_major,
630+ gc_info->v1.header.version_minor);
631+ return -EINVAL;
632+ }
601633 return 0;
602634 }
603635
@@ -992,7 +1024,7 @@ static int amdgpu_discovery_set_mes_ip_blocks(struct amdgpu_device *adev) · 388 unmodified lines
9921024 amdgpu_device_ip_block_add(adev, &mes_v10_1_ip_block);
9931025 break;
9941026 default:
995− break;;
1027+ break;
9961028 }
9971029 return 0;
9981030 }
drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c+23−4
@@ -330,10 +330,11 @@ module_param_named(aspm, amdgpu_aspm, int, 0444); · 329 unmodified lines
330330
331331 /**
332332 * DOC: runpm (int)
333− * Override for runtime power management control for dGPUs in PX/HG laptops. The amdgpu driver can dynamically power down
334− * the dGPU on PX/HG laptops when it is idle. The default is -1 (auto enable). Setting the value to 0 disables this functionality.
333+ * Override for runtime power management control for dGPUs. The amdgpu driver can dynamically power down
334+ * the dGPUs when they are idle if supported. The default is -1 (auto enable).
335+ * Setting the value to 0 disables this functionality.
335336 */
336−MODULE_PARM_DESC(runpm, "PX runtime pm (2 = force enable with BAMACO, 1 = force enable with BACO, 0 = disable, -1 = PX only default)");
337+MODULE_PARM_DESC(runpm, "PX runtime pm (2 = force enable with BAMACO, 1 = force enable with BACO, 0 = disable, -1 = auto)");
337338 module_param_named(runpm, amdgpu_runtime_pm, int, 0444);
338339
339340 /**
@@ -2168,7 +2169,10 @@ static int amdgpu_pmops_suspend(struct device *dev) · 1828 unmodified lines
21682169 adev->in_s3 = true;
21692170 r = amdgpu_device_suspend(drm_dev, true);
21702171 adev->in_s3 = false;
2171−
2172+ if (r)
2173+ return r;
2174+ if (!adev->in_s0ix)
2175+ r = amdgpu_asic_reset(adev);
21722176 return r;
21732177 }
21742178
@@ -2249,12 +2253,27 @@ static int amdgpu_pmops_runtime_suspend(struct device *dev) · 74 unmodified lines
22492253 if (amdgpu_device_supports_px(drm_dev))
22502254 drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
22512255
2256+ /*
2257+ * By setting mp1_state as PP_MP1_STATE_UNLOAD, MP1 will do some
2258+ * proper cleanups and put itself into a state ready for PNP. That
2259+ * can address some random resuming failure observed on BOCO capable
2260+ * platforms.
2261+ * TODO: this may be also needed for PX capable platform.
2262+ */
2263+ if (amdgpu_device_supports_boco(drm_dev))
2264+ adev->mp1_state = PP_MP1_STATE_UNLOAD;
2265+
22522266 ret = amdgpu_device_suspend(drm_dev, false);
22532267 if (ret) {
22542268 adev->in_runpm = false;
2269+ if (amdgpu_device_supports_boco(drm_dev))
2270+ adev->mp1_state = PP_MP1_STATE_NONE;
22552271 return ret;
22562272 }
22572273
2274+ if (amdgpu_device_supports_boco(drm_dev))
2275+ adev->mp1_state = PP_MP1_STATE_NONE;
2276+
22582277 if (amdgpu_device_supports_px(drm_dev)) {
22592278 /* Only need to handle PCI state in the driver for ATPX
22602279 * PCI core handles it for _PR3.
drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c+87−39
@@ -77,11 +77,13 @@ void amdgpu_fence_slab_fini(void) · 76 unmodified lines
7777 * Cast helper
7878 */
7979 static const struct dma_fence_ops amdgpu_fence_ops;
80+static const struct dma_fence_ops amdgpu_job_fence_ops;
8081 static inline struct amdgpu_fence *to_amdgpu_fence(struct dma_fence *f)
8182 {
8283 struct amdgpu_fence *__f = container_of(f, struct amdgpu_fence, base);
8384
84− if (__f->base.ops == &amdgpu_fence_ops)
85+ if (__f->base.ops == &amdgpu_fence_ops ||
86+ __f->base.ops == &amdgpu_job_fence_ops)
8587 return __f;
8688
8789 return NULL;
@@ -158,19 +160,18 @@ int amdgpu_fence_emit(struct amdgpu_ring *ring, struct dma_fence **f, struct amd · 70 unmodified lines
158160 }
159161
160162 seq = ++ring->fence_drv.sync_seq;
161− if (job != NULL && job->job_run_counter) {
163+ if (job && job->job_run_counter) {
162164 /* reinit seq for resubmitted jobs */
163165 fence->seqno = seq;
164166 } else {
165− dma_fence_init(fence, &amdgpu_fence_ops,
166− &ring->fence_drv.lock,
167− adev->fence_context + ring->idx,
168− seq);
169− }
170−
171− if (job != NULL) {
172− /* mark this fence has a parent job */
173− set_bit(AMDGPU_FENCE_FLAG_EMBED_IN_JOB_BIT, &fence->flags);
167+ if (job)
168+ dma_fence_init(fence, &amdgpu_job_fence_ops,
169+ &ring->fence_drv.lock,
170+ adev->fence_context + ring->idx, seq);
171+ else
172+ dma_fence_init(fence, &amdgpu_fence_ops,
173+ &ring->fence_drv.lock,
174+ adev->fence_context + ring->idx, seq);
174175 }
175176
176177 amdgpu_ring_emit_fence(ring, ring->fence_drv.gpu_addr,
@@ -620,6 +621,25 @@ void amdgpu_fence_driver_hw_init(struct amdgpu_device *adev) · 443 unmodified lines
620621 }
621622 }
622623
624+/**
625+ * amdgpu_fence_driver_clear_job_fences - clear job embedded fences of ring
626+ *
627+ * @ring: fence of the ring to be cleared
628+ *
629+ */
630+void amdgpu_fence_driver_clear_job_fences(struct amdgpu_ring *ring)
631+{
632+ int i;
633+ struct dma_fence *old, **ptr;
634+
635+ for (i = 0; i <= ring->fence_drv.num_fences_mask; i++) {
636+ ptr = &ring->fence_drv.fences[i];
637+ old = rcu_dereference_protected(*ptr, 1);
638+ if (old && old->ops == &amdgpu_job_fence_ops)
639+ RCU_INIT_POINTER(*ptr, NULL);
640+ }
641+}
642+
623643 /**
624644 * amdgpu_fence_driver_force_completion - force signal latest fence of ring
625645 *
@@ -643,16 +663,14 @@ static const char *amdgpu_fence_get_driver_name(struct dma_fence *fence) · 17 unmodified lines
643663
644664 static const char *amdgpu_fence_get_timeline_name(struct dma_fence *f)
645665 {
646− struct amdgpu_ring *ring;
666+ return (const char *)to_amdgpu_fence(f)->ring->name;
667+}
647668
648− if (test_bit(AMDGPU_FENCE_FLAG_EMBED_IN_JOB_BIT, &f->flags)) {
649− struct amdgpu_job *job = container_of(f, struct amdgpu_job, hw_fence);
669+static const char *amdgpu_job_fence_get_timeline_name(struct dma_fence *f)
670+{
671+ struct amdgpu_job *job = container_of(f, struct amdgpu_job, hw_fence);
650672
651− ring = to_amdgpu_ring(job->base.sched);
652− } else {
653− ring = to_amdgpu_fence(f)->ring;
654− }
655− return (const char *)ring->name;
673+ return (const char *)to_amdgpu_ring(job->base.sched)->name;
656674 }
657675
658676 /**
@@ -665,18 +683,25 @@ static const char *amdgpu_fence_get_timeline_name(struct dma_fence *f) · 6 unmodified lines
665683 */
666684 static bool amdgpu_fence_enable_signaling(struct dma_fence *f)
667685 {
668− struct amdgpu_ring *ring;
686+ if (!timer_pending(&to_amdgpu_fence(f)->ring->fence_drv.fallback_timer))
687+ amdgpu_fence_schedule_fallback(to_amdgpu_fence(f)->ring);
669688
670− if (test_bit(AMDGPU_FENCE_FLAG_EMBED_IN_JOB_BIT, &f->flags)) {
671− struct amdgpu_job *job = container_of(f, struct amdgpu_job, hw_fence);
689+ return true;
690+}
672691
673− ring = to_amdgpu_ring(job->base.sched);
674− } else {
675− ring = to_amdgpu_fence(f)->ring;
676− }
692+/**
693+ * amdgpu_job_fence_enable_signaling - enable signalling on job fence
694+ * @f: fence
695+ *
696+ * This is the simliar function with amdgpu_fence_enable_signaling above, it
697+ * only handles the job embedded fence.
698+ */
699+static bool amdgpu_job_fence_enable_signaling(struct dma_fence *f)
700+{
701+ struct amdgpu_job *job = container_of(f, struct amdgpu_job, hw_fence);
677702
678− if (!timer_pending(&ring->fence_drv.fallback_timer))
679− amdgpu_fence_schedule_fallback(ring);
703+ if (!timer_pending(&to_amdgpu_ring(job->base.sched)->fence_drv.fallback_timer))
704+ amdgpu_fence_schedule_fallback(to_amdgpu_ring(job->base.sched));
680705
681706 return true;
682707 }
@@ -692,19 +717,23 @@ static void amdgpu_fence_free(struct rcu_head *rcu) · 9 unmodified lines
692717 {
693718 struct dma_fence *f = container_of(rcu, struct dma_fence, rcu);
694719
695− if (test_bit(AMDGPU_FENCE_FLAG_EMBED_IN_JOB_BIT, &f->flags)) {
696− /* free job if fence has a parent job */
697− struct amdgpu_job *job;
698−
699− job = container_of(f, struct amdgpu_job, hw_fence);
700− kfree(job);
701− } else {
702720 /* free fence_slab if it's separated fence*/
703− struct amdgpu_fence *fence;
721+ kmem_cache_free(amdgpu_fence_slab, to_amdgpu_fence(f));
722+}
704723
705− fence = to_amdgpu_fence(f);
706− kmem_cache_free(amdgpu_fence_slab, fence);
707− }
724+/**
725+ * amdgpu_job_fence_free - free up the job with embedded fence
726+ *
727+ * @rcu: RCU callback head
728+ *
729+ * Free up the job with embedded fence after the RCU grace period.
730+ */
731+static void amdgpu_job_fence_free(struct rcu_head *rcu)
732+{
733+ struct dma_fence *f = container_of(rcu, struct dma_fence, rcu);
734+
735+ /* free job if fence has a parent job */
736+ kfree(container_of(f, struct amdgpu_job, hw_fence));
708737 }
709738
710739 /**
@@ -720,6 +749,19 @@ static void amdgpu_fence_release(struct dma_fence *f) · 9 unmodified lines
720749 call_rcu(&f->rcu, amdgpu_fence_free);
721750 }
722751
752+/**
753+ * amdgpu_job_fence_release - callback that job embedded fence can be freed
754+ *
755+ * @f: fence
756+ *
757+ * This is the simliar function with amdgpu_fence_release above, it
758+ * only handles the job embedded fence.
759+ */
760+static void amdgpu_job_fence_release(struct dma_fence *f)
761+{
762+ call_rcu(&f->rcu, amdgpu_job_fence_free);
763+}
764+
723765 static const struct dma_fence_ops amdgpu_fence_ops = {
724766 .get_driver_name = amdgpu_fence_get_driver_name,
725767 .get_timeline_name = amdgpu_fence_get_timeline_name,
@@ -727,6 +769,12 @@ static const struct dma_fence_ops amdgpu_fence_ops = { · 1 unmodified line
727769 .release = amdgpu_fence_release,
728770 };
729771
772+static const struct dma_fence_ops amdgpu_job_fence_ops = {
773+ .get_driver_name = amdgpu_fence_get_driver_name,
774+ .get_timeline_name = amdgpu_job_fence_get_timeline_name,
775+ .enable_signaling = amdgpu_job_fence_enable_signaling,
776+ .release = amdgpu_job_fence_release,
777+};
730778
731779 /*
732780 * Fence debugfs
drivers/gpu/drm/amd/amdgpu/amdgpu_fru_eeprom.c+15−10
@@ -56,6 +56,9 @@ static bool is_fru_eeprom_supported(struct amdgpu_device *adev) · 55 unmodified lines
5656 return true;
5757 else
5858 return false;
59+ case CHIP_ALDEBARAN:
60+ /* All Aldebaran SKUs have the FRU */
61+ return true;
5962 default:
6063 return false;
6164 }
@@ -88,13 +91,17 @@ static int amdgpu_fru_read_eeprom(struct amdgpu_device *adev, uint32_t addrptr, · 26 unmodified lines
8891
8992 int amdgpu_fru_get_product_info(struct amdgpu_device *adev)
9093 {
91− unsigned char buff[34];
94+ unsigned char buff[AMDGPU_PRODUCT_NAME_LEN+2];
9295 u32 addrptr;
9396 int size, len;
97+ int offset = 2;
9498
9599 if (!is_fru_eeprom_supported(adev))
96100 return 0;
97101
102+ if (adev->asic_type == CHIP_ALDEBARAN)
103+ offset = 0;
104+
98105 /* If algo exists, it means that the i2c_adapter's initialized */
99106 if (!adev->pm.smu_i2c.algo) {
100107 DRM_WARN("Cannot access FRU, EEPROM accessor not initialized");
@@ -131,15 +138,13 @@ int amdgpu_fru_get_product_info(struct amdgpu_device *adev) · 30 unmodified lines
131138 }
132139
133140 len = size;
134− /* Product name should only be 32 characters. Any more,
135− * and something could be wrong. Cap it at 32 to be safe
136− */
137− if (len >= sizeof(adev->product_name)) {
138− DRM_WARN("FRU Product Number is larger than 32 characters. This is likely a mistake");
139− len = sizeof(adev->product_name) - 1;
141+ if (len >= AMDGPU_PRODUCT_NAME_LEN) {
142+ DRM_WARN("FRU Product Name is larger than %d characters. This is likely a mistake",
143+ AMDGPU_PRODUCT_NAME_LEN);
144+ len = AMDGPU_PRODUCT_NAME_LEN - 1;
140145 }
141146 /* Start at 2 due to buff using fields 0 and 1 for the address */
142− memcpy(adev->product_name, &buff[2], len);
147+ memcpy(adev->product_name, &buff[offset], len);
143148 adev->product_name[len] = '\0';
144149
145150 addrptr += size + 1;
@@ -157,7 +162,7 @@ int amdgpu_fru_get_product_info(struct amdgpu_device *adev) · 11 unmodified lines
157162 DRM_WARN("FRU Product Number is larger than 16 characters. This is likely a mistake");
158163 len = sizeof(adev->product_number) - 1;
159164 }
160− memcpy(adev->product_number, &buff[2], len);
165+ memcpy(adev->product_number, &buff[offset], len);
161166 adev->product_number[len] = '\0';
162167
163168 addrptr += size + 1;
@@ -184,7 +189,7 @@ int amdgpu_fru_get_product_info(struct amdgpu_device *adev) · 20 unmodified lines
184189 DRM_WARN("FRU Serial Number is larger than 16 characters. This is likely a mistake");
185190 len = sizeof(adev->serial) - 1;
186191 }
187− memcpy(adev->serial, &buff[2], len);
192+ memcpy(adev->serial, &buff[offset], len);
188193 adev->serial[len] = '\0';
189194
190195 return 0;
drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c+3−0
@@ -264,6 +264,9 @@ static int amdgpu_gem_object_mmap(struct drm_gem_object *obj, struct vm_area_str · 263 unmodified lines
264264 !(vma->vm_flags & (VM_READ | VM_WRITE | VM_EXEC)))
265265 vma->vm_flags &= ~VM_MAYWRITE;
266266
267+ if (bo->kfd_bo)
268+ vma->vm_flags |= VM_DONTCOPY;
269+
267270 return drm_gem_ttm_mmap(obj, vma);
268271 }
269272
drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h+1−3
@@ -53,9 +53,6 @@ enum amdgpu_ring_priority_level { · 52 unmodified lines
5353 #define AMDGPU_FENCE_FLAG_INT (1 << 1)
5454 #define AMDGPU_FENCE_FLAG_TC_WB_ONLY (1 << 2)
5555
56−/* fence flag bit to indicate the face is embedded in job*/
57−#define AMDGPU_FENCE_FLAG_EMBED_IN_JOB_BIT (DMA_FENCE_FLAG_USER_BITS + 1)
58−
5956 #define to_amdgpu_ring(s) container_of((s), struct amdgpu_ring, sched)
6057
6158 #define AMDGPU_IB_POOL_SIZE (1024 * 1024)
@@ -114,6 +111,7 @@ struct amdgpu_fence_driver { · 52 unmodified lines
114111 struct dma_fence **fences;
115112 };
116113
114+void amdgpu_fence_driver_clear_job_fences(struct amdgpu_ring *ring);
117115 void amdgpu_fence_driver_force_completion(struct amdgpu_ring *ring);
118116
119117 int amdgpu_fence_driver_init_ring(struct amdgpu_ring *ring,
drivers/gpu/drm/amd/amdgpu/amdgpu_umc.c+99−68
@@ -23,74 +23,10 @@ · 22 unmodified lines
2323
2424 #include "amdgpu_ras.h"
2525
26−int amdgpu_umc_ras_late_init(struct amdgpu_device *adev)
27−{
28− int r;
29− struct ras_fs_if fs_info = {
30− .sysfs_name = "umc_err_count",
31− };
32− struct ras_ih_if ih_info = {
33− .cb = amdgpu_umc_process_ras_data_cb,
34− };
35−
36− if (!adev->umc.ras_if) {
37− adev->umc.ras_if =
38− kmalloc(sizeof(struct ras_common_if), GFP_KERNEL);
39− if (!adev->umc.ras_if)
40− return -ENOMEM;
41− adev->umc.ras_if->block = AMDGPU_RAS_BLOCK__UMC;
42− adev->umc.ras_if->type = AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE;
43− adev->umc.ras_if->sub_block_index = 0;
44− }
45− ih_info.head = fs_info.head = *adev->umc.ras_if;
46−
47− r = amdgpu_ras_late_init(adev, adev->umc.ras_if,
48− &fs_info, &ih_info);
49− if (r)
50− goto free;
51−
52− if (amdgpu_ras_is_supported(adev, adev->umc.ras_if->block)) {
53− r = amdgpu_irq_get(adev, &adev->gmc.ecc_irq, 0);
54− if (r)
55− goto late_fini;
56− } else {
57− r = 0;
58− goto free;
59− }
60−
61− /* ras init of specific umc version */
62− if (adev->umc.ras_funcs &&
63− adev->umc.ras_funcs->err_cnt_init)
64− adev->umc.ras_funcs->err_cnt_init(adev);
65−
66− return 0;
67−
68−late_fini:
69− amdgpu_ras_late_fini(adev, adev->umc.ras_if, &ih_info);
70−free:
71− kfree(adev->umc.ras_if);
72− adev->umc.ras_if = NULL;
73− return r;
74−}
75−
76−void amdgpu_umc_ras_fini(struct amdgpu_device *adev)
77−{
78− if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__UMC) &&
79− adev->umc.ras_if) {
80− struct ras_common_if *ras_if = adev->umc.ras_if;
81− struct ras_ih_if ih_info = {
82− .head = *ras_if,
83− .cb = amdgpu_umc_process_ras_data_cb,
84− };
85−
86− amdgpu_ras_late_fini(adev, ras_if, &ih_info);
87− kfree(ras_if);
88− }
89−}
90−
91−int amdgpu_umc_process_ras_data_cb(struct amdgpu_device *adev,
26+static int amdgpu_umc_do_page_retirement(struct amdgpu_device *adev,
9227 void *ras_error_status,
93− struct amdgpu_iv_entry *entry)
28+ struct amdgpu_iv_entry *entry,
29+ bool reset)
9430 {
9531 struct ras_err_data *err_data = (struct ras_err_data *)ras_error_status;
9632 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
@@ -164,13 +100,108 @@ int amdgpu_umc_process_ras_data_cb(struct amdgpu_device *adev, · 67 unmodified lines
164100 adev->smu.ppt_funcs->send_hbm_bad_pages_num(&adev->smu, con->eeprom_control.ras_num_recs);
165101 }
166102
167− amdgpu_ras_reset_gpu(adev);
103+ if (reset)
104+ amdgpu_ras_reset_gpu(adev);
168105 }
169106
170107 kfree(err_data->err_addr);
171108 return AMDGPU_RAS_SUCCESS;
172109 }
173110
111+int amdgpu_umc_poison_handler(struct amdgpu_device *adev,
112+ void *ras_error_status,
113+ bool reset)
114+{
115+ int ret;
116+ struct ras_err_data *err_data = (struct ras_err_data *)ras_error_status;
117+ struct ras_common_if head = {
118+ .block = AMDGPU_RAS_BLOCK__UMC,
119+ };
120+ struct ras_manager *obj = amdgpu_ras_find_obj(adev, &head);
121+
122+ ret =
123+ amdgpu_umc_do_page_retirement(adev, ras_error_status, NULL, reset);
124+
125+ if (ret == AMDGPU_RAS_SUCCESS && obj) {
126+ obj->err_data.ue_count += err_data->ue_count;
127+ obj->err_data.ce_count += err_data->ce_count;
128+ }
129+
130+ return ret;
131+}
132+
133+static int amdgpu_umc_process_ras_data_cb(struct amdgpu_device *adev,
134+ void *ras_error_status,
135+ struct amdgpu_iv_entry *entry)
136+{
137+ return amdgpu_umc_do_page_retirement(adev, ras_error_status, entry, true);
138+}
139+
140+int amdgpu_umc_ras_late_init(struct amdgpu_device *adev)
141+{
142+ int r;
143+ struct ras_fs_if fs_info = {
144+ .sysfs_name = "umc_err_count",
145+ };
146+ struct ras_ih_if ih_info = {
147+ .cb = amdgpu_umc_process_ras_data_cb,
148+ };
149+
150+ if (!adev->umc.ras_if) {
151+ adev->umc.ras_if =
152+ kmalloc(sizeof(struct ras_common_if), GFP_KERNEL);
153+ if (!adev->umc.ras_if)
154+ return -ENOMEM;
155+ adev->umc.ras_if->block = AMDGPU_RAS_BLOCK__UMC;
156+ adev->umc.ras_if->type = AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE;
157+ adev->umc.ras_if->sub_block_index = 0;
158+ }
159+ ih_info.head = fs_info.head = *adev->umc.ras_if;
160+
161+ r = amdgpu_ras_late_init(adev, adev->umc.ras_if,
162+ &fs_info, &ih_info);
163+ if (r)
164+ goto free;
165+
166+ if (amdgpu_ras_is_supported(adev, adev->umc.ras_if->block)) {
167+ r = amdgpu_irq_get(adev, &adev->gmc.ecc_irq, 0);
168+ if (r)
169+ goto late_fini;
170+ } else {
171+ r = 0;
172+ goto free;
173+ }
174+
175+ /* ras init of specific umc version */
176+ if (adev->umc.ras_funcs &&
177+ adev->umc.ras_funcs->err_cnt_init)
178+ adev->umc.ras_funcs->err_cnt_init(adev);
179+
180+ return 0;
181+
182+late_fini:
183+ amdgpu_ras_late_fini(adev, adev->umc.ras_if, &ih_info);
184+free:
185+ kfree(adev->umc.ras_if);
186+ adev->umc.ras_if = NULL;
187+ return r;
188+}
189+
190+void amdgpu_umc_ras_fini(struct amdgpu_device *adev)
191+{
192+ if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__UMC) &&
193+ adev->umc.ras_if) {
194+ struct ras_common_if *ras_if = adev->umc.ras_if;
195+ struct ras_ih_if ih_info = {
196+ .head = *ras_if,
197+ .cb = amdgpu_umc_process_ras_data_cb,
198+ };
199+
200+ amdgpu_ras_late_fini(adev, ras_if, &ih_info);
201+ kfree(ras_if);
202+ }
203+}
204+
174205 int amdgpu_umc_process_ecc_irq(struct amdgpu_device *adev,
175206 struct amdgpu_irq_src *source,
176207 struct amdgpu_iv_entry *entry)
drivers/gpu/drm/amd/amdgpu/amdgpu_umc.h+2−2
@@ -78,9 +78,9 @@ struct amdgpu_umc { · 77 unmodified lines
7878
7979 int amdgpu_umc_ras_late_init(struct amdgpu_device *adev);
8080 void amdgpu_umc_ras_fini(struct amdgpu_device *adev);
81−int amdgpu_umc_process_ras_data_cb(struct amdgpu_device *adev,
81+int amdgpu_umc_poison_handler(struct amdgpu_device *adev,
8282 void *ras_error_status,
83− struct amdgpu_iv_entry *entry);
83+ bool reset);
8484 int amdgpu_umc_process_ecc_irq(struct amdgpu_device *adev,
8585 struct amdgpu_irq_src *source,
8686 struct amdgpu_iv_entry *entry);
drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c+24−12
@@ -622,17 +622,35 @@ void amdgpu_virt_fini_data_exchange(struct amdgpu_device *adev) · 621 unmodified lines
622622
623623 void amdgpu_virt_init_data_exchange(struct amdgpu_device *adev)
624624 {
625− uint64_t bp_block_offset = 0;
626− uint32_t bp_block_size = 0;
627− struct amd_sriov_msg_pf2vf_info *pf2vf_v2 = NULL;
628−
629625 adev->virt.fw_reserve.p_pf2vf = NULL;
630626 adev->virt.fw_reserve.p_vf2pf = NULL;
631627 adev->virt.vf2pf_update_interval_ms = 0;
632628
633− if (adev->mman.fw_vram_usage_va != NULL) {
629+ if (adev->bios != NULL) {
634630 adev->virt.vf2pf_update_interval_ms = 2000;
635631
632+ adev->virt.fw_reserve.p_pf2vf =
633+ (struct amd_sriov_msg_pf2vf_info_header *)
634+ (adev->bios + (AMD_SRIOV_MSG_PF2VF_OFFSET_KB << 10));
635+
636+ amdgpu_virt_read_pf2vf_data(adev);
637+ }
638+
639+ if (adev->virt.vf2pf_update_interval_ms != 0) {
640+ INIT_DELAYED_WORK(&adev->virt.vf2pf_work, amdgpu_virt_update_vf2pf_work_item);
641+ schedule_delayed_work(&(adev->virt.vf2pf_work), msecs_to_jiffies(adev->virt.vf2pf_update_interval_ms));
642+ }
643+}
644+
645+
646+void amdgpu_virt_exchange_data(struct amdgpu_device *adev)
647+{
648+ uint64_t bp_block_offset = 0;
649+ uint32_t bp_block_size = 0;
650+ struct amd_sriov_msg_pf2vf_info *pf2vf_v2 = NULL;
651+
652+ if (adev->mman.fw_vram_usage_va != NULL) {
653+
636654 adev->virt.fw_reserve.p_pf2vf =
637655 (struct amd_sriov_msg_pf2vf_info_header *)
638656 (adev->mman.fw_vram_usage_va + (AMD_SRIOV_MSG_PF2VF_OFFSET_KB << 10));
@@ -663,16 +681,10 @@ void amdgpu_virt_init_data_exchange(struct amdgpu_device *adev) · 24 unmodified lines
663681 (adev->bios + (AMD_SRIOV_MSG_PF2VF_OFFSET_KB << 10));
664682
665683 amdgpu_virt_read_pf2vf_data(adev);
666−
667− return;
668− }
669−
670− if (adev->virt.vf2pf_update_interval_ms != 0) {
671− INIT_DELAYED_WORK(&adev->virt.vf2pf_work, amdgpu_virt_update_vf2pf_work_item);
672− schedule_delayed_work(&(adev->virt.vf2pf_work), adev->virt.vf2pf_update_interval_ms);
673684 }
674685 }
675686
687+
676688 void amdgpu_detect_virtualization(struct amdgpu_device *adev)
677689 {
678690 uint32_t reg;
drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h+1−0
@@ -308,6 +308,7 @@ int amdgpu_virt_alloc_mm_table(struct amdgpu_device *adev); · 307 unmodified lines
308308 void amdgpu_virt_free_mm_table(struct amdgpu_device *adev);
309309 void amdgpu_virt_release_ras_err_handler_data(struct amdgpu_device *adev);
310310 void amdgpu_virt_init_data_exchange(struct amdgpu_device *adev);
311+void amdgpu_virt_exchange_data(struct amdgpu_device *adev);
311312 void amdgpu_virt_fini_data_exchange(struct amdgpu_device *adev);
312313 void amdgpu_detect_virtualization(struct amdgpu_device *adev);
313314
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c+89−28
@@ -63,6 +63,13 @@ · 62 unmodified lines
6363 #define mmGCEA_PROBE_MAP 0x070c
6464 #define mmGCEA_PROBE_MAP_BASE_IDX 0
6565
66+#define GFX9_RLCG_GC_WRITE_OLD (0x8 << 28)
67+#define GFX9_RLCG_GC_WRITE (0x0 << 28)
68+#define GFX9_RLCG_GC_READ (0x1 << 28)
69+#define GFX9_RLCG_VFGATE_DISABLED 0x4000000
70+#define GFX9_RLCG_WRONG_OPERATION_TYPE 0x2000000
71+#define GFX9_RLCG_NOT_IN_RANGE 0x1000000
72+
6673 MODULE_FIRMWARE("amdgpu/vega10_ce.bin");
6774 MODULE_FIRMWARE("amdgpu/vega10_pfp.bin");
6875 MODULE_FIRMWARE("amdgpu/vega10_me.bin");
@@ -739,7 +746,7 @@ static const u32 GFX_RLC_SRM_INDEX_CNTL_DATA_OFFSETS[] = · 670 unmodified lines
739746 mmRLC_SRM_INDEX_CNTL_DATA_7 - mmRLC_SRM_INDEX_CNTL_DATA_0,
740747 };
741748
742−static void gfx_v9_0_rlcg_w(struct amdgpu_device *adev, u32 offset, u32 v, u32 flag)
749+static u32 gfx_v9_0_rlcg_rw(struct amdgpu_device *adev, u32 offset, u32 v, uint32_t flag)
743750 {
744751 static void *scratch_reg0;
745752 static void *scratch_reg1;
@@ -748,21 +755,20 @@ static void gfx_v9_0_rlcg_w(struct amdgpu_device *adev, u32 offset, u32 v, u32 f · 2 unmodified lines
748755 static void *spare_int;
749756 static uint32_t grbm_cntl;
750757 static uint32_t grbm_idx;
758+ uint32_t i = 0;
759+ uint32_t retries = 50000;
760+ u32 ret = 0;
761+ u32 tmp;
751762
752763 scratch_reg0 = adev->rmmio + (adev->reg_offset[GC_HWIP][0][mmSCRATCH_REG0_BASE_IDX] + mmSCRATCH_REG0)*4;
753764 scratch_reg1 = adev->rmmio + (adev->reg_offset[GC_HWIP][0][mmSCRATCH_REG1_BASE_IDX] + mmSCRATCH_REG1)*4;
754− scratch_reg2 = adev->rmmio + (adev->reg_offset[GC_HWIP][0][mmSCRATCH_REG1_BASE_IDX] + mmSCRATCH_REG2)*4;
755− scratch_reg3 = adev->rmmio + (adev->reg_offset[GC_HWIP][0][mmSCRATCH_REG1_BASE_IDX] + mmSCRATCH_REG3)*4;
765+ scratch_reg2 = adev->rmmio + (adev->reg_offset[GC_HWIP][0][mmSCRATCH_REG2_BASE_IDX] + mmSCRATCH_REG2)*4;
766+ scratch_reg3 = adev->rmmio + (adev->reg_offset[GC_HWIP][0][mmSCRATCH_REG3_BASE_IDX] + mmSCRATCH_REG3)*4;
756767 spare_int = adev->rmmio + (adev->reg_offset[GC_HWIP][0][mmRLC_SPARE_INT_BASE_IDX] + mmRLC_SPARE_INT)*4;
757768
758769 grbm_cntl = adev->reg_offset[GC_HWIP][0][mmGRBM_GFX_CNTL_BASE_IDX] + mmGRBM_GFX_CNTL;
759770 grbm_idx = adev->reg_offset[GC_HWIP][0][mmGRBM_GFX_INDEX_BASE_IDX] + mmGRBM_GFX_INDEX;
760771
761− if (amdgpu_sriov_runtime(adev)) {
762− pr_err("shouldn't call rlcg write register during runtime\n");
763− return;
764− }
765−
766772 if (offset == grbm_cntl || offset == grbm_idx) {
767773 if (offset == grbm_cntl)
768774 writel(v, scratch_reg2);
@@ -771,41 +777,95 @@ static void gfx_v9_0_rlcg_w(struct amdgpu_device *adev, u32 offset, u32 v, u32 f · 2 unmodified lines
771777
772778 writel(v, ((void __iomem *)adev->rmmio) + (offset * 4));
773779 } else {
774− uint32_t i = 0;
775− uint32_t retries = 50000;
776−
780+ /*
781+ * SCRATCH_REG0 = read/write value
782+ * SCRATCH_REG1[30:28] = command
783+ * SCRATCH_REG1[19:0] = address in dword
784+ * SCRATCH_REG1[26:24] = Error reporting
785+ */
777786 writel(v, scratch_reg0);
778− writel(offset | 0x80000000, scratch_reg1);
787+ writel(offset | flag, scratch_reg1);
779788 writel(1, spare_int);
780− for (i = 0; i < retries; i++) {
781− u32 tmp;
782789
790+ for (i = 0; i < retries; i++) {
783791 tmp = readl(scratch_reg1);
784− if (!(tmp & 0x80000000))
792+ if (!(tmp & flag))
785793 break;
786794
787795 udelay(10);
788796 }
789− if (i >= retries)
790− pr_err("timeout: rlcg program reg:0x%05x failed !\n", offset);
797+
798+ if (i >= retries) {
799+ if (amdgpu_sriov_reg_indirect_gc(adev)) {
800+ if (tmp & GFX9_RLCG_VFGATE_DISABLED)
801+ pr_err("The vfgate is disabled, program reg:0x%05x failed!\n", offset);
802+ else if (tmp & GFX9_RLCG_WRONG_OPERATION_TYPE)
803+ pr_err("Wrong operation type, program reg:0x%05x failed!\n", offset);
804+ else if (tmp & GFX9_RLCG_NOT_IN_RANGE)
805+ pr_err("The register is not in range, program reg:0x%05x failed!\n", offset);
806+ else
807+ pr_err("Unknown error type, program reg:0x%05x failed!\n", offset);
808+ } else
809+ pr_err("timeout: rlcg program reg:0x%05x failed!\n", offset);
810+ }
791811 }
792812
813+ ret = readl(scratch_reg0);
814+
815+ return ret;
816+}
817+
818+static bool gfx_v9_0_get_rlcg_flag(struct amdgpu_device *adev, u32 acc_flags, u32 hwip,
819+ int write, u32 *rlcg_flag)
820+{
821+
822+ switch (hwip) {
823+ case GC_HWIP:
824+ if (amdgpu_sriov_reg_indirect_gc(adev)) {
825+ *rlcg_flag = write ? GFX9_RLCG_GC_WRITE : GFX9_RLCG_GC_READ;
826+
827+ return true;
828+ /* only in new version, AMDGPU_REGS_NO_KIQ and AMDGPU_REGS_RLC enabled simultaneously */
829+ } else if ((acc_flags & AMDGPU_REGS_RLC) && !(acc_flags & AMDGPU_REGS_NO_KIQ) && write) {
830+ *rlcg_flag = GFX9_RLCG_GC_WRITE_OLD;
831+ return true;
832+ }
833+
834+ break;
835+ default:
836+ return false;
837+ }
838+
839+ return false;
840+}
841+
842+static u32 gfx_v9_0_sriov_rreg(struct amdgpu_device *adev, u32 offset, u32 acc_flags, u32 hwip)
843+{
844+ u32 rlcg_flag;
845+
846+ if (!amdgpu_sriov_runtime(adev) && gfx_v9_0_get_rlcg_flag(adev, acc_flags, hwip, 0, &rlcg_flag))
847+ return gfx_v9_0_rlcg_rw(adev, offset, 0, rlcg_flag);
848+
849+ if (acc_flags & AMDGPU_REGS_NO_KIQ)
850+ return RREG32_NO_KIQ(offset);
851+ else
852+ return RREG32(offset);
793853 }
794854
795855 static void gfx_v9_0_sriov_wreg(struct amdgpu_device *adev, u32 offset,
796− u32 v, u32 acc_flags, u32 hwip)
856+ u32 value, u32 acc_flags, u32 hwip)
797857 {
798− if ((acc_flags & AMDGPU_REGS_RLC) &&
799− amdgpu_sriov_fullaccess(adev)) {
800− gfx_v9_0_rlcg_w(adev, offset, v, acc_flags);
858+ u32 rlcg_flag;
801859
860+ if (!amdgpu_sriov_runtime(adev) && gfx_v9_0_get_rlcg_flag(adev, acc_flags, hwip, 1, &rlcg_flag)) {
861+ gfx_v9_0_rlcg_rw(adev, offset, value, rlcg_flag);
802862 return;
803863 }
804864
805865 if (acc_flags & AMDGPU_REGS_NO_KIQ)
806− WREG32_NO_KIQ(offset, v);
866+ WREG32_NO_KIQ(offset, value);
807867 else
808− WREG32(offset, v);
868+ WREG32(offset, value);
809869 }
810870
811871 #define VEGA10_GB_ADDR_CONFIG_GOLDEN 0x2a114042
@@ -5135,7 +5195,7 @@ static void gfx_v9_0_update_spm_vmid(struct amdgpu_device *adev, unsigned vmid) · 4323 unmodified lines
51355195 if (amdgpu_sriov_is_pp_one_vf(adev))
51365196 data = RREG32_NO_KIQ(reg);
51375197 else
5138− data = RREG32(reg);
5198+ data = RREG32_SOC15(GC, 0, mmRLC_SPM_MC_CNTL);
51395199
51405200 data &= ~RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK;
51415201 data |= (vmid & RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK) << RLC_SPM_MC_CNTL__RLC_SPM_VMID__SHIFT;
@@ -5191,6 +5251,7 @@ static const struct amdgpu_rlc_funcs gfx_v9_0_rlc_funcs = { · 49 unmodified lines
51915251 .start = gfx_v9_0_rlc_start,
51925252 .update_spm_vmid = gfx_v9_0_update_spm_vmid,
51935253 .sriov_wreg = gfx_v9_0_sriov_wreg,
5254+ .sriov_rreg = gfx_v9_0_sriov_rreg,
51945255 .is_rlcg_access_range = gfx_v9_0_is_rlcg_access_range,
51955256 };
51965257
@@ -5796,16 +5857,16 @@ static void gfx_v9_0_set_compute_eop_interrupt_state(struct amdgpu_device *adev, · 599 unmodified lines
57965857
57975858 switch (state) {
57985859 case AMDGPU_IRQ_STATE_DISABLE:
5799− mec_int_cntl = RREG32(mec_int_cntl_reg);
5860+ mec_int_cntl = RREG32_SOC15_IP(GC,mec_int_cntl_reg);
58005861 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL,
58015862 TIME_STAMP_INT_ENABLE, 0);
5802− WREG32(mec_int_cntl_reg, mec_int_cntl);
5863+ WREG32_SOC15_IP(GC, mec_int_cntl_reg, mec_int_cntl);
58035864 break;
58045865 case AMDGPU_IRQ_STATE_ENABLE:
5805− mec_int_cntl = RREG32(mec_int_cntl_reg);
5866+ mec_int_cntl = RREG32_SOC15_IP(GC, mec_int_cntl_reg);
58065867 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL,
58075868 TIME_STAMP_INT_ENABLE, 1);
5808− WREG32(mec_int_cntl_reg, mec_int_cntl);
5869+ WREG32_SOC15_IP(GC, mec_int_cntl_reg, mec_int_cntl);
58095870 break;
58105871 default:
58115872 break;
drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c+0−6
@@ -914,12 +914,6 @@ static int gmc_v10_0_sw_init(void *handle) · 913 unmodified lines
914914 return r;
915915 }
916916
917− if (adev->gmc.xgmi.supported) {
918− r = adev->gfxhub.funcs->get_xgmi_info(adev);
919− if (r)
920− return r;
921− }
922−
923917 r = gmc_v10_0_mc_init(adev);
924918 if (r)
925919 return r;
drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c+10−3
@@ -515,10 +515,10 @@ static void gmc_v8_0_mc_program(struct amdgpu_device *adev) · 514 unmodified lines
515515 static int gmc_v8_0_mc_init(struct amdgpu_device *adev)
516516 {
517517 int r;
518+ u32 tmp;
518519
519520 adev->gmc.vram_width = amdgpu_atombios_get_vram_width(adev);
520521 if (!adev->gmc.vram_width) {
521− u32 tmp;
522522 int chansize, numchan;
523523
524524 /* Get VRAM informations */
@@ -562,8 +562,15 @@ static int gmc_v8_0_mc_init(struct amdgpu_device *adev) · 37 unmodified lines
562562 adev->gmc.vram_width = numchan * chansize;
563563 }
564564 /* size in MB on si */
565− adev->gmc.mc_vram_size = RREG32(mmCONFIG_MEMSIZE) * 1024ULL * 1024ULL;
566− adev->gmc.real_vram_size = RREG32(mmCONFIG_MEMSIZE) * 1024ULL * 1024ULL;
565+ tmp = RREG32(mmCONFIG_MEMSIZE);
566+ /* some boards may have garbage in the upper 16 bits */
567+ if (tmp & 0xffff0000) {
568+ DRM_INFO("Probable bad vram size: 0x%08x\n", tmp);
569+ if (tmp & 0xffff)
570+ tmp &= 0xffff;
571+ }
572+ adev->gmc.mc_vram_size = tmp * 1024ULL * 1024ULL;
573+ adev->gmc.real_vram_size = adev->gmc.mc_vram_size;
567574
568575 if (!(adev->flags & AMD_IS_APU)) {
569576 r = amdgpu_device_resize_fb_bar(adev);
drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c+43−20
@@ -478,9 +478,18 @@ static int gmc_v9_0_vm_fault_interrupt_state(struct amdgpu_device *adev, · 477 unmodified lines
478478 hub = &adev->vmhub[j];
479479 for (i = 0; i < 16; i++) {
480480 reg = hub->vm_context0_cntl + i;
481− tmp = RREG32(reg);
481+
482+ if (j == AMDGPU_GFXHUB_0)
483+ tmp = RREG32_SOC15_IP(GC, reg);
484+ else
485+ tmp = RREG32_SOC15_IP(MMHUB, reg);
486+
482487 tmp &= ~bits;
483− WREG32(reg, tmp);
488+
489+ if (j == AMDGPU_GFXHUB_0)
490+ WREG32_SOC15_IP(GC, reg, tmp);
491+ else
492+ WREG32_SOC15_IP(MMHUB, reg, tmp);
484493 }
485494 }
486495 break;
@@ -489,9 +498,18 @@ static int gmc_v9_0_vm_fault_interrupt_state(struct amdgpu_device *adev, · 2 unmodified lines
489498 hub = &adev->vmhub[j];
490499 for (i = 0; i < 16; i++) {
491500 reg = hub->vm_context0_cntl + i;
492− tmp = RREG32(reg);
501+
502+ if (j == AMDGPU_GFXHUB_0)
503+ tmp = RREG32_SOC15_IP(GC, reg);
504+ else
505+ tmp = RREG32_SOC15_IP(MMHUB, reg);
506+
493507 tmp |= bits;
494− WREG32(reg, tmp);
508+
509+ if (j == AMDGPU_GFXHUB_0)
510+ WREG32_SOC15_IP(GC, reg, tmp);
511+ else
512+ WREG32_SOC15_IP(MMHUB, reg, tmp);
495513 }
496514 }
497515 break;
@@ -788,9 +806,12 @@ static void gmc_v9_0_flush_gpu_tlb(struct amdgpu_device *adev, uint32_t vmid, · 290 unmodified lines
788806 /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */
789807 if (use_semaphore) {
790808 for (j = 0; j < adev->usec_timeout; j++) {
791− /* a read return value of 1 means semaphore acuqire */
792− tmp = RREG32_NO_KIQ(hub->vm_inv_eng0_sem +
793− hub->eng_distance * eng);
809+ /* a read return value of 1 means semaphore acquire */
810+ if (vmhub == AMDGPU_GFXHUB_0)
811+ tmp = RREG32_SOC15_IP_NO_KIQ(GC, hub->vm_inv_eng0_sem + hub->eng_distance * eng);
812+ else
813+ tmp = RREG32_SOC15_IP_NO_KIQ(MMHUB, hub->vm_inv_eng0_sem + hub->eng_distance * eng);
814+
794815 if (tmp & 0x1)
795816 break;
796817 udelay(1);
@@ -801,8 +822,10 @@ static void gmc_v9_0_flush_gpu_tlb(struct amdgpu_device *adev, uint32_t vmid, · 4 unmodified lines
801822 }
802823
803824 do {
804− WREG32_NO_KIQ(hub->vm_inv_eng0_req +
805− hub->eng_distance * eng, inv_req);
825+ if (vmhub == AMDGPU_GFXHUB_0)
826+ WREG32_SOC15_IP_NO_KIQ(GC, hub->vm_inv_eng0_req + hub->eng_distance * eng, inv_req);
827+ else
828+ WREG32_SOC15_IP_NO_KIQ(MMHUB, hub->vm_inv_eng0_req + hub->eng_distance * eng, inv_req);
806829
807830 /*
808831 * Issue a dummy read to wait for the ACK register to
@@ -815,8 +838,11 @@ static void gmc_v9_0_flush_gpu_tlb(struct amdgpu_device *adev, uint32_t vmid, · 6 unmodified lines
815838 hub->eng_distance * eng);
816839
817840 for (j = 0; j < adev->usec_timeout; j++) {
818− tmp = RREG32_NO_KIQ(hub->vm_inv_eng0_ack +
819− hub->eng_distance * eng);
841+ if (vmhub == AMDGPU_GFXHUB_0)
842+ tmp = RREG32_SOC15_IP_NO_KIQ(GC, hub->vm_inv_eng0_ack + hub->eng_distance * eng);
843+ else
844+ tmp = RREG32_SOC15_IP_NO_KIQ(MMHUB, hub->vm_inv_eng0_ack + hub->eng_distance * eng);
845+
820846 if (tmp & (1 << vmid))
821847 break;
822848 udelay(1);
@@ -827,13 +853,16 @@ static void gmc_v9_0_flush_gpu_tlb(struct amdgpu_device *adev, uint32_t vmid, · 4 unmodified lines
827853 } while (inv_req);
828854
829855 /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */
830− if (use_semaphore)
856+ if (use_semaphore) {
831857 /*
832858 * add semaphore release after invalidation,
833859 * write with 0 means semaphore release
834860 */
835− WREG32_NO_KIQ(hub->vm_inv_eng0_sem +
836− hub->eng_distance * eng, 0);
861+ if (vmhub == AMDGPU_GFXHUB_0)
862+ WREG32_SOC15_IP_NO_KIQ(GC, hub->vm_inv_eng0_sem + hub->eng_distance * eng, 0);
863+ else
864+ WREG32_SOC15_IP_NO_KIQ(MMHUB, hub->vm_inv_eng0_sem + hub->eng_distance * eng, 0);
865+ }
837866
838867 spin_unlock(&adev->gmc.invalidate_lock);
839868
@@ -1599,12 +1628,6 @@ static int gmc_v9_0_sw_init(void *handle) · 759 unmodified lines
15991628 }
16001629 adev->need_swiotlb = drm_need_swiotlb(44);
16011630
1602− if (adev->gmc.xgmi.supported) {
1603− r = adev->gfxhub.funcs->get_xgmi_info(adev);
1604− if (r)
1605− return r;
1606− }
1607−
16081631 r = gmc_v9_0_mc_init(adev);
16091632 if (r)
16101633 return r;
drivers/gpu/drm/amd/amdgpu/psp_v11_0.c+15−63
@@ -277,13 +277,15 @@ static bool psp_v11_0_is_sos_alive(struct psp_context *psp) · 276 unmodified lines
277277 return sol_reg != 0x0;
278278 }
279279
280−static int psp_v11_0_bootloader_load_kdb(struct psp_context *psp)
280+static int psp_v11_0_bootloader_load_component(struct psp_context *psp,
281+ struct psp_bin_desc *bin_desc,
282+ enum psp_bootloader_cmd bl_cmd)
281283 {
282284 int ret;
283285 uint32_t psp_gfxdrv_command_reg = 0;
284286 struct amdgpu_device *adev = psp->adev;
285287
286− /* Check tOS sign of life register to confirm sys driver and sOS
288+ /* Check sOS sign of life register to confirm sys driver and sOS
287289 * are already been loaded.
288290 */
289291 if (psp_v11_0_is_sos_alive(psp))
@@ -293,13 +295,13 @@ static int psp_v11_0_bootloader_load_kdb(struct psp_context *psp) · 3 unmodified lines
293295 if (ret)
294296 return ret;
295297
296− /* Copy PSP KDB binary to memory */
297− psp_copy_fw(psp, psp->kdb.start_addr, psp->kdb.size_bytes);
298+ /* Copy PSP System Driver binary to memory */
299+ psp_copy_fw(psp, bin_desc->start_addr, bin_desc->size_bytes);
298300
299− /* Provide the PSP KDB to bootloader */
301+ /* Provide the sys driver to bootloader */
300302 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36,
301303 (uint32_t)(psp->fw_pri_mc_addr >> 20));
302− psp_gfxdrv_command_reg = PSP_BL__LOAD_KEY_DATABASE;
304+ psp_gfxdrv_command_reg = bl_cmd;
303305 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35,
304306 psp_gfxdrv_command_reg);
305307
@@ -308,69 +310,19 @@ static int psp_v11_0_bootloader_load_kdb(struct psp_context *psp) · 2 unmodified lines
308310 return ret;
309311 }
310312
311−static int psp_v11_0_bootloader_load_spl(struct psp_context *psp)
313+static int psp_v11_0_bootloader_load_kdb(struct psp_context *psp)
312314 {
313− int ret;
314− uint32_t psp_gfxdrv_command_reg = 0;
315− struct amdgpu_device *adev = psp->adev;
316−
317− /* Check tOS sign of life register to confirm sys driver and sOS
318− * are already been loaded.
319− */
320− if (psp_v11_0_is_sos_alive(psp))
321− return 0;
322−
323− ret = psp_v11_0_wait_for_bootloader(psp);
324− if (ret)
325− return ret;
326−
327− /* Copy PSP SPL binary to memory */
328− psp_copy_fw(psp, psp->spl.start_addr, psp->spl.size_bytes);
329−
330− /* Provide the PSP SPL to bootloader */
331− WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36,
332− (uint32_t)(psp->fw_pri_mc_addr >> 20));
333− psp_gfxdrv_command_reg = PSP_BL__LOAD_TOS_SPL_TABLE;
334− WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35,
335− psp_gfxdrv_command_reg);
336−
337− ret = psp_v11_0_wait_for_bootloader(psp);
315+ return psp_v11_0_bootloader_load_component(psp, &psp->kdb, PSP_BL__LOAD_KEY_DATABASE);
316+}
338317
339− return ret;
318+static int psp_v11_0_bootloader_load_spl(struct psp_context *psp)
319+{
320+ return psp_v11_0_bootloader_load_component(psp, &psp->spl, PSP_BL__LOAD_TOS_SPL_TABLE);
340321 }
341322
342323 static int psp_v11_0_bootloader_load_sysdrv(struct psp_context *psp)
343324 {
344− int ret;
345− uint32_t psp_gfxdrv_command_reg = 0;
346− struct amdgpu_device *adev = psp->adev;
347−
348− /* Check sOS sign of life register to confirm sys driver and sOS
349− * are already been loaded.
350− */
351− if (psp_v11_0_is_sos_alive(psp))
352− return 0;
353−
354− ret = psp_v11_0_wait_for_bootloader(psp);
355− if (ret)
356− return ret;
357−
358− /* Copy PSP System Driver binary to memory */
359− psp_copy_fw(psp, psp->sys.start_addr, psp->sys.size_bytes);
360−
361− /* Provide the sys driver to bootloader */
362− WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36,
363− (uint32_t)(psp->fw_pri_mc_addr >> 20));
364− psp_gfxdrv_command_reg = PSP_BL__LOAD_SYSDRV;
365− WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35,
366− psp_gfxdrv_command_reg);
367−
368− /* there might be handshake issue with hardware which needs delay */
369− mdelay(20);
370−
371− ret = psp_v11_0_wait_for_bootloader(psp);
372−
373− return ret;
325+ return psp_v11_0_bootloader_load_component(psp, &psp->sys, PSP_BL__LOAD_SYSDRV);
374326 }
375327
376328 static int psp_v11_0_bootloader_load_sos(struct psp_context *psp)
drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c+46−37
@@ -542,9 +542,6 @@ static void sdma_v5_2_ctx_switch_enable(struct amdgpu_device *adev, bool enable) · 541 unmodified lines
542542 }
543543
544544 for (i = 0; i < adev->sdma.num_instances; i++) {
545− f32_cntl = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CNTL));
546− f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL,
547− AUTO_CTXSW_ENABLE, enable ? 1 : 0);
548545 if (enable && amdgpu_sdma_phase_quantum) {
549546 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_PHASE0_QUANTUM),
550547 phase_quantum);
@@ -553,7 +550,13 @@ static void sdma_v5_2_ctx_switch_enable(struct amdgpu_device *adev, bool enable) · 2 unmodified lines
553550 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_PHASE2_QUANTUM),
554551 phase_quantum);
555552 }
556− WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CNTL), f32_cntl);
553+
554+ if (!amdgpu_sriov_vf(adev)) {
555+ f32_cntl = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CNTL));
556+ f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL,
557+ AUTO_CTXSW_ENABLE, enable ? 1 : 0);
558+ WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CNTL), f32_cntl);
559+ }
557560 }
558561
559562 }
@@ -576,10 +579,12 @@ static void sdma_v5_2_enable(struct amdgpu_device *adev, bool enable) · 16 unmodified lines
576579 sdma_v5_2_rlc_stop(adev);
577580 }
578581
579− for (i = 0; i < adev->sdma.num_instances; i++) {
580− f32_cntl = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_F32_CNTL));
581− f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, enable ? 0 : 1);
582− WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_F32_CNTL), f32_cntl);
582+ if (!amdgpu_sriov_vf(adev)) {
583+ for (i = 0; i < adev->sdma.num_instances; i++) {
584+ f32_cntl = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_F32_CNTL));
585+ f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, enable ? 0 : 1);
586+ WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_F32_CNTL), f32_cntl);
587+ }
583588 }
584589 }
585590
@@ -608,7 +613,8 @@ static int sdma_v5_2_gfx_resume(struct amdgpu_device *adev) · 22 unmodified lines
608613 ring = &adev->sdma.instance[i].ring;
609614 wb_offset = (ring->rptr_offs * 4);
610615
611− WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL), 0);
616+ if (!amdgpu_sriov_vf(adev))
617+ WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL), 0);
612618
613619 /* Set ring buffer size in dwords */
614620 rb_bufsz = order_base_2(ring->ring_size / 4);
@@ -683,32 +689,34 @@ static int sdma_v5_2_gfx_resume(struct amdgpu_device *adev) · 68 unmodified lines
683689 sdma_v5_2_ring_set_wptr(ring);
684690
685691 /* set minor_ptr_update to 0 after wptr programed */
686− WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_MINOR_PTR_UPDATE), 0);
687692
688− /* set utc l1 enable flag always to 1 */
689− temp = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CNTL));
690− temp = REG_SET_FIELD(temp, SDMA0_CNTL, UTC_L1_ENABLE, 1);
691−
692− /* enable MCBP */
693− temp = REG_SET_FIELD(temp, SDMA0_CNTL, MIDCMD_PREEMPT_ENABLE, 1);
694− WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CNTL), temp);
695−
696− /* Set up RESP_MODE to non-copy addresses */
697− temp = RREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_UTCL1_CNTL));
698− temp = REG_SET_FIELD(temp, SDMA0_UTCL1_CNTL, RESP_MODE, 3);
699− temp = REG_SET_FIELD(temp, SDMA0_UTCL1_CNTL, REDO_DELAY, 9);
700− WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_UTCL1_CNTL), temp);
701−
702− /* program default cache read and write policy */
703− temp = RREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_UTCL1_PAGE));
704− /* clean read policy and write policy bits */
705− temp &= 0xFF0FFF;
706− temp |= ((CACHE_READ_POLICY_L2__DEFAULT << 12) |
707− (CACHE_WRITE_POLICY_L2__DEFAULT << 14) |
708− SDMA0_UTCL1_PAGE__LLC_NOALLOC_MASK);
709− WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_UTCL1_PAGE), temp);
693+ WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_MINOR_PTR_UPDATE), 0);
710694
695+ /* SRIOV VF has no control of any of registers below */
711696 if (!amdgpu_sriov_vf(adev)) {
697+ /* set utc l1 enable flag always to 1 */
698+ temp = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CNTL));
699+ temp = REG_SET_FIELD(temp, SDMA0_CNTL, UTC_L1_ENABLE, 1);
700+
701+ /* enable MCBP */
702+ temp = REG_SET_FIELD(temp, SDMA0_CNTL, MIDCMD_PREEMPT_ENABLE, 1);
703+ WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CNTL), temp);
704+
705+ /* Set up RESP_MODE to non-copy addresses */
706+ temp = RREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_UTCL1_CNTL));
707+ temp = REG_SET_FIELD(temp, SDMA0_UTCL1_CNTL, RESP_MODE, 3);
708+ temp = REG_SET_FIELD(temp, SDMA0_UTCL1_CNTL, REDO_DELAY, 9);
709+ WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_UTCL1_CNTL), temp);
710+
711+ /* program default cache read and write policy */
712+ temp = RREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_UTCL1_PAGE));
713+ /* clean read policy and write policy bits */
714+ temp &= 0xFF0FFF;
715+ temp |= ((CACHE_READ_POLICY_L2__DEFAULT << 12) |
716+ (CACHE_WRITE_POLICY_L2__DEFAULT << 14) |
717+ SDMA0_UTCL1_PAGE__LLC_NOALLOC_MASK);
718+ WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_UTCL1_PAGE), temp);
719+
712720 /* unhalt engine */
713721 temp = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_F32_CNTL));
714722 temp = REG_SET_FIELD(temp, SDMA0_F32_CNTL, HALT, 0);
@@ -1436,13 +1444,14 @@ static int sdma_v5_2_set_trap_irq_state(struct amdgpu_device *adev, · 721 unmodified lines
14361444 enum amdgpu_interrupt_state state)
14371445 {
14381446 u32 sdma_cntl;
1439−
14401447 u32 reg_offset = sdma_v5_2_get_reg_offset(adev, type, mmSDMA0_CNTL);
14411448
1442− sdma_cntl = RREG32(reg_offset);
1443− sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE,
1444− state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
1445− WREG32(reg_offset, sdma_cntl);
1449+ if (!amdgpu_sriov_vf(adev)) {
1450+ sdma_cntl = RREG32(reg_offset);
1451+ sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE,
1452+ state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
1453+ WREG32(reg_offset, sdma_cntl);
1454+ }
14461455
14471456 return 0;
14481457 }
drivers/gpu/drm/amd/amdgpu/soc15_common.h+5−0
@@ -51,6 +51,8 @@ · 50 unmodified lines
5151
5252 #define RREG32_SOC15_IP(ip, reg) __RREG32_SOC15_RLC__(reg, 0, ip##_HWIP)
5353
54+#define RREG32_SOC15_IP_NO_KIQ(ip, reg) __RREG32_SOC15_RLC__(reg, AMDGPU_REGS_NO_KIQ, ip##_HWIP)
55+
5456 #define RREG32_SOC15_NO_KIQ(ip, inst, reg) \
5557 __RREG32_SOC15_RLC__(adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg, \
5658 AMDGPU_REGS_NO_KIQ, ip##_HWIP)
@@ -65,6 +67,9 @@ · 8 unmodified lines
6567 #define WREG32_SOC15_IP(ip, reg, value) \
6668 __WREG32_SOC15_RLC__(reg, value, 0, ip##_HWIP)
6769
70+#define WREG32_SOC15_IP_NO_KIQ(ip, reg, value) \
71+ __WREG32_SOC15_RLC__(reg, value, AMDGPU_REGS_NO_KIQ, ip##_HWIP)
72+
6873 #define WREG32_SOC15_NO_KIQ(ip, inst, reg, value) \
6974 __WREG32_SOC15_RLC__(adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg, \
7075 value, AMDGPU_REGS_NO_KIQ, ip##_HWIP)
drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c+7−0
@@ -246,6 +246,13 @@ static int vcn_v1_0_suspend(void *handle) · 245 unmodified lines
246246 {
247247 int r;
248248 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
249+ bool idle_work_unexecuted;
250+
251+ idle_work_unexecuted = cancel_delayed_work_sync(&adev->vcn.idle_work);
252+ if (idle_work_unexecuted) {
253+ if (adev->pm.dpm_enabled)
254+ amdgpu_dpm_enable_uvd(adev, false);
255+ }
249256
250257 r = vcn_v1_0_hw_fini(adev);
251258 if (r)
drivers/gpu/drm/amd/amdkfd/kfd_device.c+71−9
@@ -59,11 +59,78 @@ static void kfd_gtt_sa_fini(struct kfd_dev *kfd); · 58 unmodified lines
5959
6060 static int kfd_resume(struct kfd_dev *kfd);
6161
62+static void kfd_device_info_set_sdma_queue_num(struct kfd_dev *kfd)
63+{
64+ uint32_t sdma_version = kfd->adev->ip_versions[SDMA0_HWIP][0];
65+
66+ switch (sdma_version) {
67+ case IP_VERSION(4, 0, 0):/* VEGA10 */
68+ case IP_VERSION(4, 0, 1):/* VEGA12 */
69+ case IP_VERSION(4, 1, 0):/* RAVEN */
70+ case IP_VERSION(4, 1, 1):/* RAVEN */
71+ case IP_VERSION(4, 1, 2):/* RENIOR */
72+ case IP_VERSION(5, 2, 1):/* VANGOGH */
73+ case IP_VERSION(5, 2, 3):/* YELLOW_CARP */
74+ kfd->device_info.num_sdma_queues_per_engine = 2;
75+ break;
76+ case IP_VERSION(4, 2, 0):/* VEGA20 */
77+ case IP_VERSION(4, 2, 2):/* ARCTUTUS */
78+ case IP_VERSION(4, 4, 0):/* ALDEBARAN */
79+ case IP_VERSION(5, 0, 0):/* NAVI10 */
80+ case IP_VERSION(5, 0, 1):/* CYAN_SKILLFISH */
81+ case IP_VERSION(5, 0, 2):/* NAVI14 */
82+ case IP_VERSION(5, 0, 5):/* NAVI12 */
83+ case IP_VERSION(5, 2, 0):/* SIENNA_CICHLID */
84+ case IP_VERSION(5, 2, 2):/* NAVY_FLOUDER */
85+ case IP_VERSION(5, 2, 4):/* DIMGREY_CAVEFISH */
86+ case IP_VERSION(5, 2, 5):/* BEIGE_GOBY */
87+ kfd->device_info.num_sdma_queues_per_engine = 8;
88+ break;
89+ default:
90+ dev_warn(kfd_device,
91+ "Default sdma queue per engine(8) is set due to "
92+ "mismatch of sdma ip block(SDMA_HWIP:0x%x).\n",
93+ sdma_version);
94+ kfd->device_info.num_sdma_queues_per_engine = 8;
95+ }
96+}
97+
98+static void kfd_device_info_set_event_interrupt_class(struct kfd_dev *kfd)
99+{
100+ uint32_t gc_version = KFD_GC_VERSION(kfd);
101+
102+ switch (gc_version) {
103+ case IP_VERSION(9, 0, 1): /* VEGA10 */
104+ case IP_VERSION(9, 1, 0): /* RAVEN */
105+ case IP_VERSION(9, 2, 1): /* VEGA12 */
106+ case IP_VERSION(9, 2, 2): /* RAVEN */
107+ case IP_VERSION(9, 3, 0): /* RENOIR */
108+ case IP_VERSION(9, 4, 0): /* VEGA20 */
109+ case IP_VERSION(9, 4, 1): /* ARCTURUS */
110+ case IP_VERSION(9, 4, 2): /* ALDEBARAN */
111+ case IP_VERSION(10, 3, 1): /* VANGOGH */
112+ case IP_VERSION(10, 3, 3): /* YELLOW_CARP */
113+ case IP_VERSION(10, 1, 3): /* CYAN_SKILLFISH */
114+ case IP_VERSION(10, 1, 10): /* NAVI10 */
115+ case IP_VERSION(10, 1, 2): /* NAVI12 */
116+ case IP_VERSION(10, 1, 1): /* NAVI14 */
117+ case IP_VERSION(10, 3, 0): /* SIENNA_CICHLID */
118+ case IP_VERSION(10, 3, 2): /* NAVY_FLOUNDER */
119+ case IP_VERSION(10, 3, 4): /* DIMGREY_CAVEFISH */
120+ case IP_VERSION(10, 3, 5): /* BEIGE_GOBY */
121+ kfd->device_info.event_interrupt_class = &event_interrupt_class_v9;
122+ break;
123+ default:
124+ dev_warn(kfd_device, "v9 event interrupt handler is set due to "
125+ "mismatch of gc ip block(GC_HWIP:0x%x).\n", gc_version);
126+ kfd->device_info.event_interrupt_class = &event_interrupt_class_v9;
127+ }
128+}
129+
62130 static void kfd_device_info_init(struct kfd_dev *kfd,
63131 bool vf, uint32_t gfx_target_version)
64132 {
65133 uint32_t gc_version = KFD_GC_VERSION(kfd);
66− uint32_t sdma_version = kfd->adev->ip_versions[SDMA0_HWIP][0];
67134 uint32_t asic_type = kfd->adev->asic_type;
68135
69136 kfd->device_info.max_pasid_bits = 16;
@@ -75,16 +142,11 @@ static void kfd_device_info_init(struct kfd_dev *kfd, · 5 unmodified lines
75142 if (KFD_IS_SOC15(kfd)) {
76143 kfd->device_info.doorbell_size = 8;
77144 kfd->device_info.ih_ring_entry_size = 8 * sizeof(uint32_t);
78− kfd->device_info.event_interrupt_class = &event_interrupt_class_v9;
79145 kfd->device_info.supports_cwsr = true;
80146
81− if ((sdma_version >= IP_VERSION(4, 0, 0) &&
82− sdma_version <= IP_VERSION(4, 2, 0)) ||
83− sdma_version == IP_VERSION(5, 2, 1) ||
84− sdma_version == IP_VERSION(5, 2, 3))
85− kfd->device_info.num_sdma_queues_per_engine = 2;
86− else
87− kfd->device_info.num_sdma_queues_per_engine = 8;
147+ kfd_device_info_set_sdma_queue_num(kfd);
148+
149+ kfd_device_info_set_event_interrupt_class(kfd);
88150
89151 /* Raven */
90152 if (gc_version == IP_VERSION(9, 1, 0) ||
drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c+22−6
@@ -47,7 +47,7 @@ static int execute_queues_cpsch(struct device_queue_manager *dqm, · 46 unmodified lines
4747 uint32_t filter_param);
4848 static int unmap_queues_cpsch(struct device_queue_manager *dqm,
4949 enum kfd_unmap_queues_filter filter,
50− uint32_t filter_param);
50+ uint32_t filter_param, bool reset);
5151
5252 static int map_queues_cpsch(struct device_queue_manager *dqm);
5353
@@ -570,7 +570,7 @@ static int update_queue(struct device_queue_manager *dqm, struct queue *q, · 516 unmodified lines
570570 /* Make sure the queue is unmapped before updating the MQD */
571571 if (dqm->sched_policy != KFD_SCHED_POLICY_NO_HWS) {
572572 retval = unmap_queues_cpsch(dqm,
573− KFD_UNMAP_QUEUES_FILTER_DYNAMIC_QUEUES, 0);
573+ KFD_UNMAP_QUEUES_FILTER_DYNAMIC_QUEUES, 0, false);
574574 if (retval) {
575575 pr_err("unmap queue failed\n");
576576 goto out_unlock;
@@ -1223,7 +1223,7 @@ static int stop_cpsch(struct device_queue_manager *dqm) · 646 unmodified lines
12231223 }
12241224
12251225 if (!dqm->is_hws_hang)
1226− unmap_queues_cpsch(dqm, KFD_UNMAP_QUEUES_FILTER_ALL_QUEUES, 0);
1226+ unmap_queues_cpsch(dqm, KFD_UNMAP_QUEUES_FILTER_ALL_QUEUES, 0, false);
12271227 hanging = dqm->is_hws_hang || dqm->is_resetting;
12281228 dqm->sched_running = false;
12291229
@@ -1419,7 +1419,7 @@ static int map_queues_cpsch(struct device_queue_manager *dqm) · 189 unmodified lines
14191419 /* dqm->lock mutex has to be locked before calling this function */
14201420 static int unmap_queues_cpsch(struct device_queue_manager *dqm,
14211421 enum kfd_unmap_queues_filter filter,
1422− uint32_t filter_param)
1422+ uint32_t filter_param, bool reset)
14231423 {
14241424 int retval = 0;
14251425 struct mqd_manager *mqd_mgr;
@@ -1432,7 +1432,7 @@ static int unmap_queues_cpsch(struct device_queue_manager *dqm, · 6 unmodified lines
14321432 return retval;
14331433
14341434 retval = pm_send_unmap_queue(&dqm->packet_mgr, KFD_QUEUE_TYPE_COMPUTE,
1435− filter, filter_param, false, 0);
1435+ filter, filter_param, reset, 0);
14361436 if (retval)
14371437 return retval;
14381438
@@ -1476,6 +1476,21 @@ static int unmap_queues_cpsch(struct device_queue_manager *dqm, · 37 unmodified lines
14761476 return retval;
14771477 }
14781478
1479+/* only for compute queue */
1480+static int reset_queues_cpsch(struct device_queue_manager *dqm,
1481+ uint16_t pasid)
1482+{
1483+ int retval;
1484+
1485+ dqm_lock(dqm);
1486+
1487+ retval = unmap_queues_cpsch(dqm, KFD_UNMAP_QUEUES_FILTER_BY_PASID,
1488+ pasid, true);
1489+
1490+ dqm_unlock(dqm);
1491+ return retval;
1492+}
1493+
14791494 /* dqm->lock mutex has to be locked before calling this function */
14801495 static int execute_queues_cpsch(struct device_queue_manager *dqm,
14811496 enum kfd_unmap_queues_filter filter,
@@ -1485,7 +1500,7 @@ static int execute_queues_cpsch(struct device_queue_manager *dqm, · 3 unmodified lines
14851500
14861501 if (dqm->is_hws_hang)
14871502 return -EIO;
1488− retval = unmap_queues_cpsch(dqm, filter, filter_param);
1503+ retval = unmap_queues_cpsch(dqm, filter, filter_param, false);
14891504 if (retval)
14901505 return retval;
14911506
@@ -1896,6 +1911,7 @@ struct device_queue_manager *device_queue_manager_init(struct kfd_dev *dev) · 404 unmodified lines
18961911 dqm->ops.evict_process_queues = evict_process_queues_cpsch;
18971912 dqm->ops.restore_process_queues = restore_process_queues_cpsch;
18981913 dqm->ops.get_wave_state = get_wave_state;
1914+ dqm->ops.reset_queues = reset_queues_cpsch;
18991915 break;
19001916 case KFD_SCHED_POLICY_NO_HWS:
19011917 /* initialize dqm for no cp scheduling */
drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.h+5−0
@@ -81,6 +81,8 @@ struct device_process_node { · 80 unmodified lines
8181 *
8282 * @get_wave_state: Retrieves context save state and optionally copies the
8383 * control stack, if kept in the MQD, to the given userspace address.
84+ *
85+ * @reset_queues: reset queues which consume RAS poison
8486 */
8587
8688 struct device_queue_manager_ops {
@@ -134,6 +136,9 @@ struct device_queue_manager_ops { · 47 unmodified lines
134136 void __user *ctl_stack,
135137 u32 *ctl_stack_used_size,
136138 u32 *save_area_used_size);
139+
140+ int (*reset_queues)(struct device_queue_manager *dqm,
141+ uint16_t pasid);
137142 };
138143
139144 struct device_queue_manager_asic_ops {
drivers/gpu/drm/amd/amdkfd/kfd_int_process_v9.c+40−4
@@ -89,6 +89,44 @@ enum SQ_INTERRUPT_ERROR_TYPE { · 88 unmodified lines
8989 #define KFD_SQ_INT_DATA__ERR_TYPE_MASK 0xF00000
9090 #define KFD_SQ_INT_DATA__ERR_TYPE__SHIFT 20
9191
92+static void event_interrupt_poison_consumption(struct kfd_dev *dev,
93+ uint16_t pasid, uint16_t source_id)
94+{
95+ int ret = -EINVAL;
96+ struct kfd_process *p = kfd_lookup_process_by_pasid(pasid);
97+
98+ if (!p)
99+ return;
100+
101+ /* all queues of a process will be unmapped in one time */
102+ if (atomic_read(&p->poison)) {
103+ kfd_unref_process(p);
104+ return;
105+ }
106+
107+ atomic_set(&p->poison, 1);
108+ kfd_unref_process(p);
109+
110+ switch (source_id) {
111+ case SOC15_INTSRC_SQ_INTERRUPT_MSG:
112+ if (dev->dqm->ops.reset_queues)
113+ ret = dev->dqm->ops.reset_queues(dev->dqm, pasid);
114+ break;
115+ case SOC15_INTSRC_SDMA_ECC:
116+ default:
117+ break;
118+ }
119+
120+ kfd_signal_poison_consumed_event(dev, pasid);
121+
122+ /* resetting queue passes, do page retirement without gpu reset
123+ resetting queue fails, fallback to gpu reset solution */
124+ if (!ret)
125+ amdgpu_amdkfd_ras_poison_consumption_handler(dev->adev, false);
126+ else
127+ amdgpu_amdkfd_ras_poison_consumption_handler(dev->adev, true);
128+}
129+
92130 static bool event_interrupt_isr_v9(struct kfd_dev *dev,
93131 const uint32_t *ih_ring_entry,
94132 uint32_t *patched_ihre,
@@ -230,8 +268,7 @@ static void event_interrupt_wq_v9(struct kfd_dev *dev, · 135 unmodified lines
230268 sq_intr_err);
231269 if (sq_intr_err != SQ_INTERRUPT_ERROR_TYPE_ILLEGAL_INST &&
232270 sq_intr_err != SQ_INTERRUPT_ERROR_TYPE_MEMVIOL) {
233− kfd_signal_poison_consumed_event(dev, pasid);
234− amdgpu_amdkfd_ras_poison_consumption_handler(dev->adev);
271+ event_interrupt_poison_consumption(dev, pasid, source_id);
235272 return;
236273 }
237274 break;
@@ -252,8 +289,7 @@ static void event_interrupt_wq_v9(struct kfd_dev *dev, · 14 unmodified lines
252289 if (source_id == SOC15_INTSRC_SDMA_TRAP) {
253290 kfd_signal_event_interrupt(pasid, context_id0 & 0xfffffff, 28);
254291 } else if (source_id == SOC15_INTSRC_SDMA_ECC) {
255− kfd_signal_poison_consumed_event(dev, pasid);
256− amdgpu_amdkfd_ras_poison_consumption_handler(dev->adev);
292+ event_interrupt_poison_consumption(dev, pasid, source_id);
257293 return;
258294 }
259295 } else if (client_id == SOC15_IH_CLIENTID_VMC ||
drivers/gpu/drm/amd/amdkfd/kfd_migrate.c+1−1
@@ -549,7 +549,7 @@ static void svm_migrate_page_free(struct page *page) · 548 unmodified lines
549549
550550 if (svm_bo) {
551551 pr_debug_ratelimited("ref: %d\n", kref_read(&svm_bo->kref));
552− svm_range_bo_unref(svm_bo);
552+ svm_range_bo_unref_async(svm_bo);
553553 }
554554 }
555555
drivers/gpu/drm/amd/amdkfd/kfd_priv.h+2−0
@@ -856,6 +856,8 @@ struct kfd_process { · 855 unmodified lines
856856 struct svm_range_list svms;
857857
858858 bool xnack_enabled;
859+
860+ atomic_t poison;
859861 };
860862
861863 #define KFD_PROCESS_TABLE_SIZE 5 /* bits: 32 entries */
drivers/gpu/drm/amd/amdkfd/kfd_svm.c+29−6
@@ -332,6 +332,8 @@ static void svm_range_bo_release(struct kref *kref) · 331 unmodified lines
332332 struct svm_range_bo *svm_bo;
333333
334334 svm_bo = container_of(kref, struct svm_range_bo, kref);
335+ pr_debug("svm_bo 0x%p\n", svm_bo);
336+
335337 spin_lock(&svm_bo->list_lock);
336338 while (!list_empty(&svm_bo->range_list)) {
337339 struct svm_range *prange =
@@ -365,12 +367,33 @@ static void svm_range_bo_release(struct kref *kref) · 27 unmodified lines
365367 kfree(svm_bo);
366368 }
367369
368−void svm_range_bo_unref(struct svm_range_bo *svm_bo)
370+static void svm_range_bo_wq_release(struct work_struct *work)
369371 {
370− if (!svm_bo)
371− return;
372+ struct svm_range_bo *svm_bo;
373+
374+ svm_bo = container_of(work, struct svm_range_bo, release_work);
375+ svm_range_bo_release(&svm_bo->kref);
376+}
377+
378+static void svm_range_bo_release_async(struct kref *kref)
379+{
380+ struct svm_range_bo *svm_bo;
381+
382+ svm_bo = container_of(kref, struct svm_range_bo, kref);
383+ pr_debug("svm_bo 0x%p\n", svm_bo);
384+ INIT_WORK(&svm_bo->release_work, svm_range_bo_wq_release);
385+ schedule_work(&svm_bo->release_work);
386+}
372387
373− kref_put(&svm_bo->kref, svm_range_bo_release);
388+void svm_range_bo_unref_async(struct svm_range_bo *svm_bo)
389+{
390+ kref_put(&svm_bo->kref, svm_range_bo_release_async);
391+}
392+
393+static void svm_range_bo_unref(struct svm_range_bo *svm_bo)
394+{
395+ if (svm_bo)
396+ kref_put(&svm_bo->kref, svm_range_bo_release);
374397 }
375398
376399 static bool
@@ -2254,8 +2277,8 @@ svm_range_cpu_invalidate_pagetables(struct mmu_interval_notifier *mni, · 1877 unmodified lines
22542277
22552278 start = mni->interval_tree.start;
22562279 last = mni->interval_tree.last;
2257− start = (start > range->start ? start : range->start) >> PAGE_SHIFT;
2258− last = (last < (range->end - 1) ? last : range->end - 1) >> PAGE_SHIFT;
2280+ start = max(start, range->start) >> PAGE_SHIFT;
2281+ last = min(last, range->end - 1) >> PAGE_SHIFT;
22592282 pr_debug("[0x%lx 0x%lx] range[0x%lx 0x%lx] notifier[0x%lx 0x%lx] %d\n",
22602283 start, last, range->start >> PAGE_SHIFT,
22612284 (range->end - 1) >> PAGE_SHIFT,
drivers/gpu/drm/amd/amdkfd/kfd_svm.h+2−1
@@ -48,6 +48,7 @@ struct svm_range_bo { · 47 unmodified lines
4848 struct work_struct eviction_work;
4949 struct svm_range_list *svms;
5050 uint32_t evicting;
51+ struct work_struct release_work;
5152 };
5253
5354 enum svm_work_list_ops {
@@ -195,7 +196,7 @@ void svm_range_list_lock_and_flush_work(struct svm_range_list *svms, struct mm_s · 141 unmodified lines
195196 */
196197 #define KFD_IS_SVM_API_SUPPORTED(dev) ((dev)->pgmap.type != 0)
197198
198−void svm_range_bo_unref(struct svm_range_bo *svm_bo);
199+void svm_range_bo_unref_async(struct svm_range_bo *svm_bo);
199200 #else
200201
201202 struct kfd_process;
drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/vg_clk_mgr.c+1−1
@@ -741,7 +741,7 @@ void vg_clk_mgr_construct( · 740 unmodified lines
741741 sizeof(struct watermarks),
742742 &clk_mgr->smu_wm_set.mc_address.quad_part);
743743
744− if (clk_mgr->smu_wm_set.wm_set == 0) {
744+ if (!clk_mgr->smu_wm_set.wm_set) {
745745 clk_mgr->smu_wm_set.wm_set = &dummy_wms;
746746 clk_mgr->smu_wm_set.mc_address.quad_part = 0;
747747 }
drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c+1−0
@@ -158,6 +158,7 @@ void dcn31_update_clocks(struct clk_mgr *clk_mgr_base, · 157 unmodified lines
158158 union display_idle_optimization_u idle_info = { 0 };
159159 idle_info.idle_info.df_request_disabled = 1;
160160 idle_info.idle_info.phy_ref_clk_off = 1;
161+ idle_info.idle_info.s0i2_rdy = 1;
161162 dcn31_smu_set_display_idle_optimization(clk_mgr, idle_info.data);
162163 /* update power state */
163164 clk_mgr_base->clks.pwr_state = DCN_PWR_STATE_LOW_POWER;
drivers/gpu/drm/amd/display/dc/core/dc.c+0−18
@@ -274,24 +274,6 @@ static bool create_links( · 273 unmodified lines
274274 goto failed_alloc;
275275 }
276276
277−#if defined(CONFIG_DRM_AMD_DC_DCN)
278− if (IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment) &&
279− dc->caps.dp_hpo &&
280− link->dc->res_pool->res_cap->num_hpo_dp_link_encoder > 0) {
281− /* FPGA case - Allocate HPO DP link encoder */
282− if (i < link->dc->res_pool->res_cap->num_hpo_dp_link_encoder) {
283− link->hpo_dp_link_enc = link->dc->res_pool->hpo_dp_link_enc[i];
284−
285− if (link->hpo_dp_link_enc == NULL) {
286− BREAK_TO_DEBUGGER();
287− goto failed_alloc;
288− }
289− link->hpo_dp_link_enc->hpd_source = link->link_enc->hpd_source;
290− link->hpo_dp_link_enc->transmitter = link->link_enc->transmitter;
291− }
292− }
293−#endif
294−
295277 link->link_status.dpcd_caps = &link->dpcd_caps;
296278
297279 enc_init.ctx = dc->ctx;
drivers/gpu/drm/amd/display/dc/core/dc_debug.c+2−0
@@ -422,6 +422,8 @@ char *dc_status_to_str(enum dc_status status) · 421 unmodified lines
422422 return "The operation is not supported.";
423423 case DC_UNSUPPORTED_VALUE:
424424 return "The value specified is not supported.";
425+ case DC_NO_LINK_ENC_RESOURCE:
426+ return "No link encoder resource";
425427 case DC_ERROR_UNEXPECTED:
426428 return "Unexpected error";
427429 }
drivers/gpu/drm/amd/display/dc/core/dc_link.c+173−68
@@ -66,31 +66,6 @@ · 65 unmodified lines
6666 /*******************************************************************************
6767 * Private functions
6868 ******************************************************************************/
69−#if defined(CONFIG_DRM_AMD_DC_DCN)
70−static bool add_dp_hpo_link_encoder_to_link(struct dc_link *link)
71−{
72− struct hpo_dp_link_encoder *enc = resource_get_unused_hpo_dp_link_encoder(
73− link->dc->res_pool);
74−
75− if (!link->hpo_dp_link_enc && enc) {
76− link->hpo_dp_link_enc = enc;
77− link->hpo_dp_link_enc->transmitter = link->link_enc->transmitter;
78− link->hpo_dp_link_enc->hpd_source = link->link_enc->hpd_source;
79− }
80−
81− return (link->hpo_dp_link_enc != NULL);
82−}
83−
84−static void remove_dp_hpo_link_encoder_from_link(struct dc_link *link)
85−{
86− if (link->hpo_dp_link_enc) {
87− link->hpo_dp_link_enc->hpd_source = HPD_SOURCEID_UNKNOWN;
88− link->hpo_dp_link_enc->transmitter = TRANSMITTER_UNKNOWN;
89− link->hpo_dp_link_enc = NULL;
90− }
91−}
92−#endif
93−
9469 static void dc_link_destruct(struct dc_link *link)
9570 {
9671 int i;
@@ -118,12 +93,6 @@ static void dc_link_destruct(struct dc_link *link) · 21 unmodified lines
11893 link->link_enc->funcs->destroy(&link->link_enc);
11994 }
12095
121−#if defined(CONFIG_DRM_AMD_DC_DCN)
122− if (link->hpo_dp_link_enc) {
123− remove_dp_hpo_link_encoder_from_link(link);
124− }
125−#endif
126−
12796 if (link->local_sink)
12897 dc_sink_release(link->local_sink);
12998
@@ -881,6 +850,7 @@ static bool dc_link_detect_helper(struct dc_link *link, · 751 unmodified lines
881850 enum dc_connection_type pre_connection_type = dc_connection_none;
882851 bool perform_dp_seamless_boot = false;
883852 const uint32_t post_oui_delay = 30; // 30ms
853+ struct link_resource link_res = { 0 };
884854
885855 DC_LOGGER_INIT(link->ctx->logger);
886856
@@ -975,7 +945,10 @@ static bool dc_link_detect_helper(struct dc_link *link, · 88 unmodified lines
975945
976946 #if defined(CONFIG_DRM_AMD_DC_DCN)
977947 if (dp_get_link_encoding_format(&link->reported_link_cap) == DP_128b_132b_ENCODING)
978− add_dp_hpo_link_encoder_to_link(link);
948+ link_res.hpo_dp_link_enc = resource_get_hpo_dp_link_enc_for_det_lt(
949+ &link->dc->current_state->res_ctx,
950+ link->dc->res_pool,
951+ link);
979952 #endif
980953
981954 if (link->type == dc_connection_mst_branch) {
@@ -986,7 +959,7 @@ static bool dc_link_detect_helper(struct dc_link *link, · 4 unmodified lines
986959 * empty which leads to allocate_mst_payload() has "0"
987960 * pbn_per_slot value leading to exception on dc_fixpt_div()
988961 */
989− dp_verify_mst_link_cap(link);
962+ dp_verify_mst_link_cap(link, &link_res);
990963
991964 /*
992965 * This call will initiate MST topology discovery. Which
@@ -1150,6 +1123,7 @@ static bool dc_link_detect_helper(struct dc_link *link, · 157 unmodified lines
11501123 // verify link cap for SST non-seamless boot
11511124 if (!perform_dp_seamless_boot)
11521125 dp_verify_link_cap_with_retries(link,
1126+ &link_res,
11531127 &link->reported_link_cap,
11541128 LINK_TRAINING_MAX_VERIFY_RETRY);
11551129 } else {
@@ -1844,6 +1818,8 @@ static void enable_stream_features(struct pipe_ctx *pipe_ctx) · 688 unmodified lines
18441818 union down_spread_ctrl old_downspread;
18451819 union down_spread_ctrl new_downspread;
18461820
1821+ memset(&old_downspread, 0, sizeof(old_downspread));
1822+
18471823 core_link_read_dpcd(link, DP_DOWNSPREAD_CTRL,
18481824 &old_downspread.raw, sizeof(old_downspread));
18491825
@@ -2503,7 +2479,8 @@ static void write_i2c_redriver_setting( · 653 unmodified lines
25032479 DC_LOG_DEBUG("Set redriver failed");
25042480 }
25052481
2506−static void disable_link(struct dc_link *link, enum signal_type signal)
2482+static void disable_link(struct dc_link *link, const struct link_resource *link_res,
2483+ enum signal_type signal)
25072484 {
25082485 /*
25092486 * TODO: implement call for dp_set_hw_test_pattern
@@ -2522,20 +2499,20 @@ static void disable_link(struct dc_link *link, enum signal_type signal) · 12 unmodified lines
25222499 struct dc_link_settings link_settings = link->cur_link_settings;
25232500 #endif
25242501 if (dc_is_dp_sst_signal(signal))
2525− dp_disable_link_phy(link, signal);
2502+ dp_disable_link_phy(link, link_res, signal);
25262503 else
2527− dp_disable_link_phy_mst(link, signal);
2504+ dp_disable_link_phy_mst(link, link_res, signal);
25282505
25292506 if (dc_is_dp_sst_signal(signal) ||
25302507 link->mst_stream_alloc_table.stream_count == 0) {
25312508 #if defined(CONFIG_DRM_AMD_DC_DCN)
25322509 if (dp_get_link_encoding_format(&link_settings) == DP_8b_10b_ENCODING) {
25332510 dp_set_fec_enable(link, false);
2534− dp_set_fec_ready(link, false);
2511+ dp_set_fec_ready(link, link_res, false);
25352512 }
25362513 #else
25372514 dp_set_fec_enable(link, false);
2538− dp_set_fec_ready(link, false);
2515+ dp_set_fec_ready(link, link_res, false);
25392516 #endif
25402517 }
25412518 } else {
@@ -2646,7 +2623,7 @@ static enum dc_status enable_link( · 104 unmodified lines
26462623 * new link settings.
26472624 */
26482625 if (link->link_status.link_active) {
2649− disable_link(link, pipe_ctx->stream->signal);
2626+ disable_link(link, &pipe_ctx->link_res, pipe_ctx->stream->signal);
26502627 }
26512628
26522629 switch (pipe_ctx->stream->signal) {
@@ -3421,7 +3398,7 @@ static enum dc_status dc_link_update_sst_payload(struct pipe_ctx *pipe_ctx, · 768 unmodified lines
34213398 {
34223399 struct dc_stream_state *stream = pipe_ctx->stream;
34233400 struct dc_link *link = stream->link;
3424− struct hpo_dp_link_encoder *hpo_dp_link_encoder = link->hpo_dp_link_enc;
3401+ struct hpo_dp_link_encoder *hpo_dp_link_encoder = pipe_ctx->link_res.hpo_dp_link_enc;
34253402 struct hpo_dp_stream_encoder *hpo_dp_stream_encoder = pipe_ctx->stream_res.hpo_dp_stream_enc;
34263403 struct link_mst_stream_allocation_table proposed_table = {0};
34273404 struct fixed31_32 avg_time_slots_per_mtp;
@@ -3503,7 +3480,7 @@ enum dc_status dc_link_allocate_mst_payload(struct pipe_ctx *pipe_ctx) · 75 unmodified lines
35033480 struct link_encoder *link_encoder = NULL;
35043481 struct stream_encoder *stream_encoder = pipe_ctx->stream_res.stream_enc;
35053482 #if defined(CONFIG_DRM_AMD_DC_DCN)
3506− struct hpo_dp_link_encoder *hpo_dp_link_encoder = link->hpo_dp_link_enc;
3483+ struct hpo_dp_link_encoder *hpo_dp_link_encoder = pipe_ctx->link_res.hpo_dp_link_enc;
35073484 struct hpo_dp_stream_encoder *hpo_dp_stream_encoder = pipe_ctx->stream_res.hpo_dp_stream_enc;
35083485 #endif
35093486 struct dp_mst_stream_allocation_table proposed_table = {0};
@@ -3833,7 +3810,7 @@ static enum dc_status deallocate_mst_payload(struct pipe_ctx *pipe_ctx) · 323 unmodified lines
38333810 struct link_encoder *link_encoder = NULL;
38343811 struct stream_encoder *stream_encoder = pipe_ctx->stream_res.stream_enc;
38353812 #if defined(CONFIG_DRM_AMD_DC_DCN)
3836− struct hpo_dp_link_encoder *hpo_dp_link_encoder = link->hpo_dp_link_enc;
3813+ struct hpo_dp_link_encoder *hpo_dp_link_encoder = pipe_ctx->link_res.hpo_dp_link_enc;
38373814 struct hpo_dp_stream_encoder *hpo_dp_stream_encoder = pipe_ctx->stream_res.hpo_dp_stream_enc;
38383815 #endif
38393816 struct dp_mst_stream_allocation_table proposed_table = {0};
@@ -4009,12 +3986,9 @@ static void update_psp_stream_config(struct pipe_ctx *pipe_ctx, bool dpms_off) · 169 unmodified lines
40093986 config.dig_be = pipe_ctx->stream->link->link_enc_hw_inst;
40103987 #if defined(CONFIG_DRM_AMD_DC_DCN)
40113988 config.stream_enc_idx = pipe_ctx->stream_res.stream_enc->id - ENGINE_ID_DIGA;
4012−
3989+
40133990 if (pipe_ctx->stream->link->ep_type == DISPLAY_ENDPOINT_PHY ||
40143991 pipe_ctx->stream->link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA) {
4015− link_enc = pipe_ctx->stream->link->link_enc;
4016− config.dio_output_type = pipe_ctx->stream->link->ep_type;
4017− config.dio_output_idx = link_enc->transmitter - TRANSMITTER_UNIPHY_A;
40183992 if (pipe_ctx->stream->link->ep_type == DISPLAY_ENDPOINT_PHY)
40193993 link_enc = pipe_ctx->stream->link->link_enc;
40203994 else if (pipe_ctx->stream->link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA)
@@ -4081,7 +4055,8 @@ static void update_psp_stream_config(struct pipe_ctx *pipe_ctx, bool dpms_off) · 60 unmodified lines
40814055 config.link_enc_idx = link_enc->transmitter - TRANSMITTER_UNIPHY_A;
40824056 if (is_dp_128b_132b_signal(pipe_ctx)) {
40834057 config.stream_enc_idx = pipe_ctx->stream_res.hpo_dp_stream_enc->id - ENGINE_ID_HPO_DP_0;
4084− config.link_enc_idx = pipe_ctx->stream->link->hpo_dp_link_enc->inst;
4058+
4059+ config.link_enc_idx = pipe_ctx->link_res.hpo_dp_link_enc->inst;
40854060 config.dp2_enabled = 1;
40864061 }
40874062 #endif
@@ -4112,7 +4087,7 @@ static void fpga_dp_hpo_enable_link_and_stream(struct dc_state *state, struct pi · 24 unmodified lines
41124087 stream->link->cur_link_settings = link_settings;
41134088
41144089 /* Enable clock, Configure lane count, and Enable Link Encoder*/
4115− enable_dp_hpo_output(stream->link, &stream->link->cur_link_settings);
4090+ enable_dp_hpo_output(stream->link, &pipe_ctx->link_res, &stream->link->cur_link_settings);
41164091
41174092 #ifdef DIAGS_BUILD
41184093 /* Workaround for FPGA HPO capture DP link data:
@@ -4162,12 +4137,12 @@ static void fpga_dp_hpo_enable_link_and_stream(struct dc_state *state, struct pi · 43 unmodified lines
41624137 proposed_table.stream_allocations[0].hpo_dp_stream_enc = pipe_ctx->stream_res.hpo_dp_stream_enc;
41634138 }
41644139
4165− stream->link->hpo_dp_link_enc->funcs->update_stream_allocation_table(
4166− stream->link->hpo_dp_link_enc,
4140+ pipe_ctx->link_res.hpo_dp_link_enc->funcs->update_stream_allocation_table(
4141+ pipe_ctx->link_res.hpo_dp_link_enc,
41674142 &proposed_table);
41684143
4169− stream->link->hpo_dp_link_enc->funcs->set_throttled_vcp_size(
4170− stream->link->hpo_dp_link_enc,
4144+ pipe_ctx->link_res.hpo_dp_link_enc->funcs->set_throttled_vcp_size(
4145+ pipe_ctx->link_res.hpo_dp_link_enc,
41714146 pipe_ctx->stream_res.hpo_dp_stream_enc->inst,
41724147 avg_time_slots_per_mtp);
41734148
@@ -4356,7 +4331,8 @@ void core_link_enable_stream( · 182 unmodified lines
43564331 if (status != DC_FAIL_DP_LINK_TRAINING ||
43574332 pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST) {
43584333 if (false == stream->link->link_status.link_active)
4359− disable_link(stream->link, pipe_ctx->stream->signal);
4334+ disable_link(stream->link, &pipe_ctx->link_res,
4335+ pipe_ctx->stream->signal);
43604336 BREAK_TO_DEBUGGER();
43614337 return;
43624338 }
@@ -4505,14 +4481,14 @@ void core_link_disable_stream(struct pipe_ctx *pipe_ctx) · 142 unmodified lines
45054481 * state machine.
45064482 * In DP2 or MST mode, our encoder will stay video active
45074483 */
4508− disable_link(pipe_ctx->stream->link, pipe_ctx->stream->signal);
4484+ disable_link(pipe_ctx->stream->link, &pipe_ctx->link_res, pipe_ctx->stream->signal);
45094485 dc->hwss.disable_stream(pipe_ctx);
45104486 } else {
45114487 dc->hwss.disable_stream(pipe_ctx);
4512− disable_link(pipe_ctx->stream->link, pipe_ctx->stream->signal);
4488+ disable_link(pipe_ctx->stream->link, &pipe_ctx->link_res, pipe_ctx->stream->signal);
45134489 }
45144490 #else
4515− disable_link(pipe_ctx->stream->link, pipe_ctx->stream->signal);
4491+ disable_link(pipe_ctx->stream->link, &pipe_ctx->link_res, pipe_ctx->stream->signal);
45164492
45174493 dc->hwss.disable_stream(pipe_ctx);
45184494 #endif
@@ -4595,16 +4571,22 @@ void dc_link_set_drive_settings(struct dc *dc, · 76 unmodified lines
45954571 {
45964572
45974573 int i;
4574+ struct pipe_ctx *pipe = NULL;
4575+ const struct link_resource *link_res;
45984576
4599− for (i = 0; i < dc->link_count; i++) {
4600− if (dc->links[i] == link)
4601− break;
4602− }
4577+ link_res = dc_link_get_cur_link_res(link);
46034578
4604− if (i >= dc->link_count)
4579+ for (i = 0; i < MAX_PIPES; i++) {
4580+ pipe = &dc->current_state->res_ctx.pipe_ctx[i];
4581+ if (pipe->stream && pipe->stream->link) {
4582+ if (pipe->stream->link == link)
4583+ break;
4584+ }
4585+ }
4586+ if (pipe && link_res)
4587+ dc_link_dp_set_drive_settings(pipe->stream->link, link_res, lt_settings);
4588+ else
46054589 ASSERT_CRITICAL(false);
4606−
4607− dc_link_dp_set_drive_settings(dc->links[i], lt_settings);
46084590 }
46094591
46104592 void dc_link_set_preferred_link_settings(struct dc *dc,
@@ -4665,11 +4647,9 @@ void dc_link_set_preferred_training_settings(struct dc *dc, · 54 unmodified lines
46654647 if (link_setting != NULL) {
46664648 link->preferred_link_setting = *link_setting;
46674649 #if defined(CONFIG_DRM_AMD_DC_DCN)
4668− if (dp_get_link_encoding_format(link_setting) ==
4669− DP_128b_132b_ENCODING && !link->hpo_dp_link_enc) {
4670− if (!add_dp_hpo_link_encoder_to_link(link))
4671− memset(&link->preferred_link_setting, 0, sizeof(link->preferred_link_setting));
4672− }
4650+ if (dp_get_link_encoding_format(link_setting) == DP_128b_132b_ENCODING)
4651+ /* TODO: add dc update for acquiring link res */
4652+ skip_immediate_retrain = true;
46734653 #endif
46744654 } else {
46754655 link->preferred_link_setting.lane_count = LANE_COUNT_UNKNOWN;
@@ -4796,6 +4776,9 @@ void dc_link_overwrite_extended_receiver_cap( · 120 unmodified lines
47964776
47974777 bool dc_link_is_fec_supported(const struct dc_link *link)
47984778 {
4779+ /* TODO - use asic cap instead of link_enc->features
4780+ * we no longer know which link enc to use for this link before commit
4781+ */
47994782 struct link_encoder *link_enc = NULL;
48004783
48014784 /* Links supporting dynamically assigned link encoder will be assigned next
@@ -4890,3 +4873,125 @@ uint32_t dc_bandwidth_in_kbps_from_timing( · 88 unmodified lines
48904873 return kbps;
48914874
48924875 }
4876+
4877+const struct link_resource *dc_link_get_cur_link_res(const struct dc_link *link)
4878+{
4879+ int i;
4880+ struct pipe_ctx *pipe = NULL;
4881+ const struct link_resource *link_res = NULL;
4882+
4883+ for (i = 0; i < MAX_PIPES; i++) {
4884+ pipe = &link->dc->current_state->res_ctx.pipe_ctx[i];
4885+ if (pipe->stream && pipe->stream->link && pipe->top_pipe == NULL) {
4886+ if (pipe->stream->link == link) {
4887+ link_res = &pipe->link_res;
4888+ break;
4889+ }
4890+ }
4891+ }
4892+
4893+ return link_res;
4894+}
4895+
4896+/**
4897+ * dc_get_cur_link_res_map() - take a snapshot of current link resource allocation state
4898+ * @dc: pointer to dc of the dm calling this
4899+ * @map: a dc link resource snapshot defined internally to dc.
4900+ *
4901+ * DM needs to capture a snapshot of current link resource allocation mapping
4902+ * and store it in its persistent storage.
4903+ *
4904+ * Some of the link resource is using first come first serve policy.
4905+ * The allocation mapping depends on original hotplug order. This information
4906+ * is lost after driver is loaded next time. The snapshot is used in order to
4907+ * restore link resource to its previous state so user will get consistent
4908+ * link capability allocation across reboot.
4909+ *
4910+ * Return: none (void function)
4911+ *
4912+ */
4913+void dc_get_cur_link_res_map(const struct dc *dc, uint32_t *map)
4914+{
4915+#if defined(CONFIG_DRM_AMD_DC_DCN)
4916+ struct dc_link *link;
4917+ uint8_t i;
4918+ uint32_t hpo_dp_recycle_map = 0;
4919+
4920+ *map = 0;
4921+
4922+ if (dc->caps.dp_hpo) {
4923+ for (i = 0; i < dc->caps.max_links; i++) {
4924+ link = dc->links[i];
4925+ if (link->link_status.link_active &&
4926+ dp_get_link_encoding_format(&link->reported_link_cap) == DP_128b_132b_ENCODING &&
4927+ dp_get_link_encoding_format(&link->cur_link_settings) != DP_128b_132b_ENCODING)
4928+ /* hpo dp link encoder is considered as recycled, when RX reports 128b/132b encoding capability
4929+ * but current link doesn't use it.
4930+ */
4931+ hpo_dp_recycle_map |= (1 << i);
4932+ }
4933+ *map |= (hpo_dp_recycle_map << LINK_RES_HPO_DP_REC_MAP__SHIFT);
4934+ }
4935+#endif
4936+}
4937+
4938+/**
4939+ * dc_restore_link_res_map() - restore link resource allocation state from a snapshot
4940+ * @dc: pointer to dc of the dm calling this
4941+ * @map: a dc link resource snapshot defined internally to dc.
4942+ *
4943+ * DM needs to call this function after initial link detection on boot and
4944+ * before first commit streams to restore link resource allocation state
4945+ * from previous boot session.
4946+ *
4947+ * Some of the link resource is using first come first serve policy.
4948+ * The allocation mapping depends on original hotplug order. This information
4949+ * is lost after driver is loaded next time. The snapshot is used in order to
4950+ * restore link resource to its previous state so user will get consistent
4951+ * link capability allocation across reboot.
4952+ *
4953+ * Return: none (void function)
4954+ *
4955+ */
4956+void dc_restore_link_res_map(const struct dc *dc, uint32_t *map)
4957+{
4958+#if defined(CONFIG_DRM_AMD_DC_DCN)
4959+ struct dc_link *link;
4960+ uint8_t i;
4961+ unsigned int available_hpo_dp_count;
4962+ uint32_t hpo_dp_recycle_map = (*map & LINK_RES_HPO_DP_REC_MAP__MASK)
4963+ >> LINK_RES_HPO_DP_REC_MAP__SHIFT;
4964+
4965+ if (dc->caps.dp_hpo) {
4966+ available_hpo_dp_count = dc->res_pool->hpo_dp_link_enc_count;
4967+ /* remove excess 128b/132b encoding support for not recycled links */
4968+ for (i = 0; i < dc->caps.max_links; i++) {
4969+ if ((hpo_dp_recycle_map & (1 << i)) == 0) {
4970+ link = dc->links[i];
4971+ if (link->type != dc_connection_none &&
4972+ dp_get_link_encoding_format(&link->verified_link_cap) == DP_128b_132b_ENCODING) {
4973+ if (available_hpo_dp_count > 0)
4974+ available_hpo_dp_count--;
4975+ else
4976+ /* remove 128b/132b encoding capability by limiting verified link rate to HBR3 */
4977+ link->verified_link_cap.link_rate = LINK_RATE_HIGH3;
4978+ }
4979+ }
4980+ }
4981+ /* remove excess 128b/132b encoding support for recycled links */
4982+ for (i = 0; i < dc->caps.max_links; i++) {
4983+ if ((hpo_dp_recycle_map & (1 << i)) != 0) {
4984+ link = dc->links[i];
4985+ if (link->type != dc_connection_none &&
4986+ dp_get_link_encoding_format(&link->verified_link_cap) == DP_128b_132b_ENCODING) {
4987+ if (available_hpo_dp_count > 0)
4988+ available_hpo_dp_count--;
4989+ else
4990+ /* remove 128b/132b encoding capability by limiting verified link rate to HBR3 */
4991+ link->verified_link_cap.link_rate = LINK_RATE_HIGH3;
4992+ }
4993+ }
4994+ }
4995+ }
4996+#endif
4997+}
drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c+434−67
@@ -1251,6 +1251,7 @@ bool dp_is_max_vs_reached( · 1250 unmodified lines
12511251
12521252 static bool perform_post_lt_adj_req_sequence(
12531253 struct dc_link *link,
1254+ const struct link_resource *link_res,
12541255 struct link_training_settings *lt_settings)
12551256 {
12561257 enum dc_lane_count lane_count =
@@ -1314,6 +1315,7 @@ static bool perform_post_lt_adj_req_sequence( · 57 unmodified lines
13141315 lt_settings->hw_lane_settings, lt_settings->dpcd_lane_settings);
13151316
13161317 dc_link_dp_set_drive_settings(link,
1318+ link_res,
13171319 lt_settings);
13181320 break;
13191321 }
@@ -1388,6 +1390,7 @@ enum link_training_result dp_get_cr_failure(enum dc_lane_count ln_count, · 68 unmodified lines
13881390
13891391 static enum link_training_result perform_channel_equalization_sequence(
13901392 struct dc_link *link,
1393+ const struct link_resource *link_res,
13911394 struct link_training_settings *lt_settings,
13921395 uint32_t offset)
13931396 {
@@ -1410,12 +1413,12 @@ static enum link_training_result perform_channel_equalization_sequence( · 16 unmodified lines
14101413 tr_pattern = DP_TRAINING_PATTERN_SEQUENCE_4;
14111414 #endif
14121415
1413− dp_set_hw_training_pattern(link, tr_pattern, offset);
1416+ dp_set_hw_training_pattern(link, link_res, tr_pattern, offset);
14141417
14151418 for (retries_ch_eq = 0; retries_ch_eq <= LINK_TRAINING_MAX_RETRY_COUNT;
14161419 retries_ch_eq++) {
14171420
1418− dp_set_hw_lane_settings(link, lt_settings, offset);
1421+ dp_set_hw_lane_settings(link, link_res, lt_settings, offset);
14191422
14201423 /* 2. update DPCD*/
14211424 if (!retries_ch_eq)
@@ -1479,18 +1482,20 @@ static enum link_training_result perform_channel_equalization_sequence( · 57 unmodified lines
14791482 }
14801483
14811484 static void start_clock_recovery_pattern_early(struct dc_link *link,
1485+ const struct link_resource *link_res,
14821486 struct link_training_settings *lt_settings,
14831487 uint32_t offset)
14841488 {
14851489 DC_LOG_HW_LINK_TRAINING("%s\n GPU sends TPS1. Wait 400us.\n",
14861490 __func__);
1487− dp_set_hw_training_pattern(link, lt_settings->pattern_for_cr, offset);
1488− dp_set_hw_lane_settings(link, lt_settings, offset);
1491+ dp_set_hw_training_pattern(link, link_res, lt_settings->pattern_for_cr, offset);
1492+ dp_set_hw_lane_settings(link, link_res, lt_settings, offset);
14891493 udelay(400);
14901494 }
14911495
14921496 static enum link_training_result perform_clock_recovery_sequence(
14931497 struct dc_link *link,
1498+ const struct link_resource *link_res,
14941499 struct link_training_settings *lt_settings,
14951500 uint32_t offset)
14961501 {
@@ -1506,7 +1511,7 @@ static enum link_training_result perform_clock_recovery_sequence( · 9 unmodified lines
15061511 retry_count = 0;
15071512
15081513 if (!link->ctx->dc->work_arounds.lt_early_cr_pattern)
1509− dp_set_hw_training_pattern(link, lt_settings->pattern_for_cr, offset);
1514+ dp_set_hw_training_pattern(link, link_res, lt_settings->pattern_for_cr, offset);
15101515
15111516 /* najeeb - The synaptics MST hub can put the LT in
15121517 * infinite loop by switching the VS
@@ -1523,6 +1528,7 @@ static enum link_training_result perform_clock_recovery_sequence( · 10 unmodified lines
15231528 /* 1. call HWSS to set lane settings*/
15241529 dp_set_hw_lane_settings(
15251530 link,
1531+ link_res,
15261532 lt_settings,
15271533 offset);
15281534
@@ -1544,9 +1550,6 @@ static enum link_training_result perform_clock_recovery_sequence( · 15 unmodified lines
15441550 /* 3. wait receiver to lock-on*/
15451551 wait_time_microsec = lt_settings->cr_pattern_time;
15461552
1547− if (link->lttpr_mode == LTTPR_MODE_NON_TRANSPARENT)
1548− wait_time_microsec = TRAINING_AUX_RD_INTERVAL;
1549−
15501553 if (link->dc->debug.apply_vendor_specific_lttpr_wa &&
15511554 (link->chip_caps & EXT_DISPLAY_PATH_CAPS__DP_FIXED_VS_EN)) {
15521555 wait_time_microsec = 16000;
@@ -1624,13 +1627,14 @@ static enum link_training_result perform_clock_recovery_sequence( · 71 unmodified lines
16241627
16251628 static inline enum link_training_result dp_transition_to_video_idle(
16261629 struct dc_link *link,
1630+ const struct link_resource *link_res,
16271631 struct link_training_settings *lt_settings,
16281632 enum link_training_result status)
16291633 {
16301634 union lane_count_set lane_count_set = {0};
16311635
16321636 /* 4. mainlink output idle pattern*/
1633− dp_set_hw_test_pattern(link, DP_TEST_PATTERN_VIDEO_MODE, NULL, 0);
1637+ dp_set_hw_test_pattern(link, link_res, DP_TEST_PATTERN_VIDEO_MODE, NULL, 0);
16341638
16351639 /*
16361640 * 5. post training adjust if required
@@ -1654,7 +1658,7 @@ static inline enum link_training_result dp_transition_to_video_idle( · 17 unmodified lines
16541658 }
16551659
16561660 if (status == LINK_TRAINING_SUCCESS &&
1657− perform_post_lt_adj_req_sequence(link, lt_settings) == false)
1661+ perform_post_lt_adj_req_sequence(link, link_res, lt_settings) == false)
16581662 status = LINK_TRAINING_LQA_FAIL;
16591663
16601664 lane_count_set.bits.LANE_COUNT_SET = lt_settings->link_settings.lane_count;
@@ -2097,10 +2101,11 @@ static void print_status_message( · 436 unmodified lines
20972101
20982102 void dc_link_dp_set_drive_settings(
20992103 struct dc_link *link,
2104+ const struct link_resource *link_res,
21002105 struct link_training_settings *lt_settings)
21012106 {
21022107 /* program ASIC PHY settings*/
2103− dp_set_hw_lane_settings(link, lt_settings, DPRX);
2108+ dp_set_hw_lane_settings(link, link_res, lt_settings, DPRX);
21042109
21052110 dp_hw_to_dpcd_lane_settings(lt_settings,
21062111 lt_settings->hw_lane_settings, lt_settings->dpcd_lane_settings);
@@ -2111,6 +2116,7 @@ void dc_link_dp_set_drive_settings( · 4 unmodified lines
21112116
21122117 bool dc_link_dp_perform_link_training_skip_aux(
21132118 struct dc_link *link,
2119+ const struct link_resource *link_res,
21142120 const struct dc_link_settings *link_setting)
21152121 {
21162122 struct link_training_settings lt_settings = {0};
@@ -2127,10 +2133,10 @@ bool dc_link_dp_perform_link_training_skip_aux( · 10 unmodified lines
21272133 /* 1. Perform_clock_recovery_sequence. */
21282134
21292135 /* transmit training pattern for clock recovery */
2130− dp_set_hw_training_pattern(link, lt_settings.pattern_for_cr, DPRX);
2136+ dp_set_hw_training_pattern(link, link_res, lt_settings.pattern_for_cr, DPRX);
21312137
21322138 /* call HWSS to set lane settings*/
2133− dp_set_hw_lane_settings(link, &lt_settings, DPRX);
2139+ dp_set_hw_lane_settings(link, link_res, &lt_settings, DPRX);
21342140
21352141 /* wait receiver to lock-on*/
21362142 dp_wait_for_training_aux_rd_interval(link, lt_settings.cr_pattern_time);
@@ -2138,10 +2144,10 @@ bool dc_link_dp_perform_link_training_skip_aux( · 1 unmodified line
21382144 /* 2. Perform_channel_equalization_sequence. */
21392145
21402146 /* transmit training pattern for channel equalization. */
2141− dp_set_hw_training_pattern(link, lt_settings.pattern_for_eq, DPRX);
2147+ dp_set_hw_training_pattern(link, link_res, lt_settings.pattern_for_eq, DPRX);
21422148
21432149 /* call HWSS to set lane settings*/
2144− dp_set_hw_lane_settings(link, &lt_settings, DPRX);
2150+ dp_set_hw_lane_settings(link, link_res, &lt_settings, DPRX);
21452151
21462152 /* wait receiver to lock-on. */
21472153 dp_wait_for_training_aux_rd_interval(link, lt_settings.eq_pattern_time);
@@ -2149,7 +2155,7 @@ bool dc_link_dp_perform_link_training_skip_aux( · 1 unmodified line
21492155 /* 3. Perform_link_training_int. */
21502156
21512157 /* Mainlink output idle pattern. */
2152− dp_set_hw_test_pattern(link, DP_TEST_PATTERN_VIDEO_MODE, NULL, 0);
2158+ dp_set_hw_test_pattern(link, link_res, DP_TEST_PATTERN_VIDEO_MODE, NULL, 0);
21532159
21542160 print_status_message(link, &lt_settings, LINK_TRAINING_SUCCESS);
21552161
@@ -2230,6 +2236,7 @@ static void dpcd_128b_132b_get_aux_rd_interval(struct dc_link *link, · 74 unmodified lines
22302236
22312237 static enum link_training_result dp_perform_128b_132b_channel_eq_done_sequence(
22322238 struct dc_link *link,
2239+ const struct link_resource *link_res,
22332240 struct link_training_settings *lt_settings)
22342241 {
22352242 uint8_t loop_count;
@@ -2241,7 +2248,7 @@ static enum link_training_result dp_perform_128b_132b_channel_eq_done_sequence( · 5 unmodified lines
22412248 union lane_adjust dpcd_lane_adjust[LANE_COUNT_DP_MAX] = {0};
22422249
22432250 /* Transmit 128b/132b_TPS1 over Main-Link */
2244− dp_set_hw_training_pattern(link, lt_settings->pattern_for_cr, DPRX);
2251+ dp_set_hw_training_pattern(link, link_res, lt_settings->pattern_for_cr, DPRX);
22452252 /* Set TRAINING_PATTERN_SET to 01h */
22462253 dpcd_set_training_pattern(link, lt_settings->pattern_for_cr);
22472254
@@ -2251,8 +2258,8 @@ static enum link_training_result dp_perform_128b_132b_channel_eq_done_sequence( · 3 unmodified lines
22512258 &dpcd_lane_status_updated, dpcd_lane_adjust, DPRX);
22522259 dp_decide_lane_settings(lt_settings, dpcd_lane_adjust,
22532260 lt_settings->hw_lane_settings, lt_settings->dpcd_lane_settings);
2254− dp_set_hw_lane_settings(link, lt_settings, DPRX);
2255− dp_set_hw_training_pattern(link, lt_settings->pattern_for_eq, DPRX);
2261+ dp_set_hw_lane_settings(link, link_res, lt_settings, DPRX);
2262+ dp_set_hw_training_pattern(link, link_res, lt_settings->pattern_for_eq, DPRX);
22562263
22572264 /* Set loop counter to start from 1 */
22582265 loop_count = 1;
@@ -2279,7 +2286,7 @@ static enum link_training_result dp_perform_128b_132b_channel_eq_done_sequence( · 20 unmodified lines
22792286 } else if (dpcd_lane_status_updated.bits.LT_FAILED_128b_132b) {
22802287 status = DP_128b_132b_LT_FAILED;
22812288 } else {
2282− dp_set_hw_lane_settings(link, lt_settings, DPRX);
2289+ dp_set_hw_lane_settings(link, link_res, lt_settings, DPRX);
22832290 dpcd_set_lane_settings(link, lt_settings, DPRX);
22842291 }
22852292 loop_count++;
@@ -2308,6 +2315,7 @@ static enum link_training_result dp_perform_128b_132b_channel_eq_done_sequence( · 22 unmodified lines
23082315
23092316 static enum link_training_result dp_perform_128b_132b_cds_done_sequence(
23102317 struct dc_link *link,
2318+ const struct link_resource *link_res,
23112319 struct link_training_settings *lt_settings)
23122320 {
23132321 /* Assumption: assume hardware has transmitted eq pattern */
@@ -2344,6 +2352,7 @@ static enum link_training_result dp_perform_128b_132b_cds_done_sequence( · 30 unmodified lines
23442352
23452353 static enum link_training_result dp_perform_8b_10b_link_training(
23462354 struct dc_link *link,
2355+ const struct link_resource *link_res,
23472356 struct link_training_settings *lt_settings)
23482357 {
23492358 enum link_training_result status = LINK_TRAINING_SUCCESS;
@@ -2353,7 +2362,7 @@ static enum link_training_result dp_perform_8b_10b_link_training( · 3 unmodified lines
23532362 uint8_t lane = 0;
23542363
23552364 if (link->ctx->dc->work_arounds.lt_early_cr_pattern)
2356− start_clock_recovery_pattern_early(link, lt_settings, DPRX);
2365+ start_clock_recovery_pattern_early(link, link_res, lt_settings, DPRX);
23572366
23582367 /* 1. set link rate, lane count and spread. */
23592368 dpcd_set_link_settings(link, lt_settings);
@@ -2367,12 +2376,13 @@ static enum link_training_result dp_perform_8b_10b_link_training( · 7 unmodified lines
23672376
23682377 for (repeater_id = repeater_cnt; (repeater_id > 0 && status == LINK_TRAINING_SUCCESS);
23692378 repeater_id--) {
2370− status = perform_clock_recovery_sequence(link, lt_settings, repeater_id);
2379+ status = perform_clock_recovery_sequence(link, link_res, lt_settings, repeater_id);
23712380
23722381 if (status != LINK_TRAINING_SUCCESS)
23732382 break;
23742383
23752384 status = perform_channel_equalization_sequence(link,
2385+ link_res,
23762386 lt_settings,
23772387 repeater_id);
23782388
@@ -2387,9 +2397,10 @@ static enum link_training_result dp_perform_8b_10b_link_training( · 8 unmodified lines
23872397 }
23882398
23892399 if (status == LINK_TRAINING_SUCCESS) {
2390− status = perform_clock_recovery_sequence(link, lt_settings, DPRX);
2400+ status = perform_clock_recovery_sequence(link, link_res, lt_settings, DPRX);
23912401 if (status == LINK_TRAINING_SUCCESS) {
23922402 status = perform_channel_equalization_sequence(link,
2403+ link_res,
23932404 lt_settings,
23942405 DPRX);
23952406 }
@@ -2401,6 +2412,7 @@ static enum link_training_result dp_perform_8b_10b_link_training( · 5 unmodified lines
24012412 #if defined(CONFIG_DRM_AMD_DC_DCN)
24022413 static enum link_training_result dp_perform_128b_132b_link_training(
24032414 struct dc_link *link,
2415+ const struct link_resource *link_res,
24042416 struct link_training_settings *lt_settings)
24052417 {
24062418 enum link_training_result result = LINK_TRAINING_SUCCESS;
@@ -2412,23 +2424,358 @@ static enum link_training_result dp_perform_128b_132b_link_training( · 5 unmodified lines
24122424 decide_8b_10b_training_settings(link,
24132425 &lt_settings->link_settings,
24142426 &legacy_settings);
2415− return dp_perform_8b_10b_link_training(link, &legacy_settings);
2427+ return dp_perform_8b_10b_link_training(link, link_res, &legacy_settings);
24162428 }
24172429
24182430 dpcd_set_link_settings(link, lt_settings);
24192431
24202432 if (result == LINK_TRAINING_SUCCESS)
2421− result = dp_perform_128b_132b_channel_eq_done_sequence(link, lt_settings);
2433+ result = dp_perform_128b_132b_channel_eq_done_sequence(link, link_res, lt_settings);
24222434
24232435 if (result == LINK_TRAINING_SUCCESS)
2424− result = dp_perform_128b_132b_cds_done_sequence(link, lt_settings);
2436+ result = dp_perform_128b_132b_cds_done_sequence(link, link_res, lt_settings);
24252437
24262438 return result;
24272439 }
24282440 #endif
24292441
2442+static enum link_training_result dc_link_dp_perform_fixed_vs_pe_training_sequence(
2443+ struct dc_link *link,
2444+ const struct link_resource *link_res,
2445+ struct link_training_settings *lt_settings)
2446+{
2447+ const uint8_t vendor_lttpr_write_data_reset[4] = {0x1, 0x50, 0x63, 0xFF};
2448+ const uint8_t offset = dp_convert_to_count(
2449+ link->dpcd_caps.lttpr_caps.phy_repeater_cnt);
2450+ const uint8_t vendor_lttpr_write_data_intercept_en[4] = {0x1, 0x55, 0x63, 0x0};
2451+ const uint8_t vendor_lttpr_write_data_intercept_dis[4] = {0x1, 0x55, 0x63, 0x68};
2452+ uint8_t vendor_lttpr_write_data_vs[4] = {0x1, 0x51, 0x63, 0x0};
2453+ uint8_t vendor_lttpr_write_data_pe[4] = {0x1, 0x52, 0x63, 0x0};
2454+ uint32_t vendor_lttpr_write_address = 0xF004F;
2455+ enum link_training_result status = LINK_TRAINING_SUCCESS;
2456+ uint8_t lane = 0;
2457+ union down_spread_ctrl downspread = {0};
2458+ union lane_count_set lane_count_set = {0};
2459+ uint8_t toggle_rate;
2460+ uint8_t rate;
2461+
2462+ /* Only 8b/10b is supported */
2463+ ASSERT(dp_get_link_encoding_format(&lt_settings->link_settings) ==
2464+ DP_8b_10b_ENCODING);
2465+
2466+ if (offset != 0xFF) {
2467+ vendor_lttpr_write_address +=
2468+ ((DP_REPEATER_CONFIGURATION_AND_STATUS_SIZE) * (offset - 1));
2469+ }
2470+
2471+ /* Vendor specific: Reset lane settings */
2472+ core_link_write_dpcd(
2473+ link,
2474+ vendor_lttpr_write_address,
2475+ &vendor_lttpr_write_data_reset[0],
2476+ sizeof(vendor_lttpr_write_data_reset));
2477+ core_link_write_dpcd(
2478+ link,
2479+ vendor_lttpr_write_address,
2480+ &vendor_lttpr_write_data_vs[0],
2481+ sizeof(vendor_lttpr_write_data_vs));
2482+ core_link_write_dpcd(
2483+ link,
2484+ vendor_lttpr_write_address,
2485+ &vendor_lttpr_write_data_pe[0],
2486+ sizeof(vendor_lttpr_write_data_pe));
2487+
2488+ /* Vendor specific: Enable intercept */
2489+ core_link_write_dpcd(
2490+ link,
2491+ vendor_lttpr_write_address,
2492+ &vendor_lttpr_write_data_intercept_en[0],
2493+ sizeof(vendor_lttpr_write_data_intercept_en));
2494+
2495+ /* 1. set link rate, lane count and spread. */
2496+
2497+ downspread.raw = (uint8_t)(lt_settings->link_settings.link_spread);
2498+
2499+ lane_count_set.bits.LANE_COUNT_SET =
2500+ lt_settings->link_settings.lane_count;
2501+
2502+ lane_count_set.bits.ENHANCED_FRAMING = lt_settings->enhanced_framing;
2503+ lane_count_set.bits.POST_LT_ADJ_REQ_GRANTED = 0;
2504+
2505+
2506+ if (lt_settings->pattern_for_eq < DP_TRAINING_PATTERN_SEQUENCE_4) {
2507+ lane_count_set.bits.POST_LT_ADJ_REQ_GRANTED =
2508+ link->dpcd_caps.max_ln_count.bits.POST_LT_ADJ_REQ_SUPPORTED;
2509+ }
2510+
2511+ core_link_write_dpcd(link, DP_DOWNSPREAD_CTRL,
2512+ &downspread.raw, sizeof(downspread));
2513+
2514+ core_link_write_dpcd(link, DP_LANE_COUNT_SET,
2515+ &lane_count_set.raw, 1);
2516+
2517+#if defined(CONFIG_DRM_AMD_DC_DCN)
2518+ rate = get_dpcd_link_rate(&lt_settings->link_settings);
2519+#else
2520+ rate = (uint8_t) (lt_settings->link_settings.link_rate);
2521+#endif
2522+
2523+ /* Vendor specific: Toggle link rate */
2524+ toggle_rate = (rate == 0x6) ? 0xA : 0x6;
2525+
2526+ if (link->vendor_specific_lttpr_link_rate_wa == rate) {
2527+ core_link_write_dpcd(
2528+ link,
2529+ DP_LINK_BW_SET,
2530+ &toggle_rate,
2531+ 1);
2532+ }
2533+
2534+ link->vendor_specific_lttpr_link_rate_wa = rate;
2535+
2536+ core_link_write_dpcd(link, DP_LINK_BW_SET, &rate, 1);
2537+
2538+ DC_LOG_HW_LINK_TRAINING("%s\n %x rate = %x\n %x lane = %x framing = %x\n %x spread = %x\n",
2539+ __func__,
2540+ DP_LINK_BW_SET,
2541+ lt_settings->link_settings.link_rate,
2542+ DP_LANE_COUNT_SET,
2543+ lt_settings->link_settings.lane_count,
2544+ lt_settings->enhanced_framing,
2545+ DP_DOWNSPREAD_CTRL,
2546+ lt_settings->link_settings.link_spread);
2547+
2548+ /* 2. Perform link training */
2549+
2550+ /* Perform Clock Recovery Sequence */
2551+ if (status == LINK_TRAINING_SUCCESS) {
2552+ uint32_t retries_cr;
2553+ uint32_t retry_count;
2554+ uint32_t wait_time_microsec;
2555+ enum dc_lane_count lane_count = lt_settings->link_settings.lane_count;
2556+ union lane_status dpcd_lane_status[LANE_COUNT_DP_MAX];
2557+ union lane_align_status_updated dpcd_lane_status_updated;
2558+ union lane_adjust dpcd_lane_adjust[LANE_COUNT_DP_MAX] = {0};
2559+
2560+ retries_cr = 0;
2561+ retry_count = 0;
2562+
2563+ while ((retries_cr < LINK_TRAINING_MAX_RETRY_COUNT) &&
2564+ (retry_count < LINK_TRAINING_MAX_CR_RETRY)) {
2565+
2566+ memset(&dpcd_lane_status, '\0', sizeof(dpcd_lane_status));
2567+ memset(&dpcd_lane_status_updated, '\0',
2568+ sizeof(dpcd_lane_status_updated));
2569+
2570+ /* 1. call HWSS to set lane settings */
2571+ dp_set_hw_lane_settings(
2572+ link,
2573+ link_res,
2574+ lt_settings,
2575+ 0);
2576+
2577+ /* 2. update DPCD of the receiver */
2578+ if (!retry_count) {
2579+ /* EPR #361076 - write as a 5-byte burst,
2580+ * but only for the 1-st iteration.
2581+ */
2582+ dpcd_set_lt_pattern_and_lane_settings(
2583+ link,
2584+ lt_settings,
2585+ lt_settings->pattern_for_cr,
2586+ 0);
2587+ /* Vendor specific: Disable intercept */
2588+ core_link_write_dpcd(
2589+ link,
2590+ vendor_lttpr_write_address,
2591+ &vendor_lttpr_write_data_intercept_dis[0],
2592+ sizeof(vendor_lttpr_write_data_intercept_dis));
2593+ } else {
2594+ vendor_lttpr_write_data_vs[3] = 0;
2595+ vendor_lttpr_write_data_pe[3] = 0;
2596+
2597+ for (lane = 0; lane < lane_count; lane++) {
2598+ vendor_lttpr_write_data_vs[3] |=
2599+ lt_settings->dpcd_lane_settings[lane].bits.VOLTAGE_SWING_SET << (2 * lane);
2600+ vendor_lttpr_write_data_pe[3] |=
2601+ lt_settings->dpcd_lane_settings[lane].bits.PRE_EMPHASIS_SET << (2 * lane);
2602+ }
2603+
2604+ /* Vendor specific: Update VS and PE to DPRX requested value */
2605+ core_link_write_dpcd(
2606+ link,
2607+ vendor_lttpr_write_address,
2608+ &vendor_lttpr_write_data_vs[0],
2609+ sizeof(vendor_lttpr_write_data_vs));
2610+ core_link_write_dpcd(
2611+ link,
2612+ vendor_lttpr_write_address,
2613+ &vendor_lttpr_write_data_pe[0],
2614+ sizeof(vendor_lttpr_write_data_pe));
2615+
2616+ dpcd_set_lane_settings(
2617+ link,
2618+ lt_settings,
2619+ 0);
2620+ }
2621+
2622+ /* 3. wait receiver to lock-on*/
2623+ wait_time_microsec = lt_settings->cr_pattern_time;
2624+
2625+ dp_wait_for_training_aux_rd_interval(
2626+ link,
2627+ wait_time_microsec);
2628+
2629+ /* 4. Read lane status and requested drive
2630+ * settings as set by the sink
2631+ */
2632+ dp_get_lane_status_and_lane_adjust(
2633+ link,
2634+ lt_settings,
2635+ dpcd_lane_status,
2636+ &dpcd_lane_status_updated,
2637+ dpcd_lane_adjust,
2638+ 0);
2639+
2640+ /* 5. check CR done*/
2641+ if (dp_is_cr_done(lane_count, dpcd_lane_status)) {
2642+ status = LINK_TRAINING_SUCCESS;
2643+ break;
2644+ }
2645+
2646+ /* 6. max VS reached*/
2647+ if (dp_is_max_vs_reached(lt_settings))
2648+ break;
2649+
2650+ /* 7. same lane settings */
2651+ /* Note: settings are the same for all lanes,
2652+ * so comparing first lane is sufficient
2653+ */
2654+ if (lt_settings->dpcd_lane_settings[0].bits.VOLTAGE_SWING_SET ==
2655+ dpcd_lane_adjust[0].bits.VOLTAGE_SWING_LANE)
2656+ retries_cr++;
2657+ else
2658+ retries_cr = 0;
2659+
2660+ /* 8. update VS/PE/PC2 in lt_settings*/
2661+ dp_decide_lane_settings(lt_settings, dpcd_lane_adjust,
2662+ lt_settings->hw_lane_settings, lt_settings->dpcd_lane_settings);
2663+ retry_count++;
2664+ }
2665+
2666+ if (retry_count >= LINK_TRAINING_MAX_CR_RETRY) {
2667+ ASSERT(0);
2668+ DC_LOG_ERROR("%s: Link Training Error, could not get CR after %d tries. Possibly voltage swing issue",
2669+ __func__,
2670+ LINK_TRAINING_MAX_CR_RETRY);
2671+
2672+ }
2673+
2674+ status = dp_get_cr_failure(lane_count, dpcd_lane_status);
2675+ }
2676+
2677+ /* Perform Channel EQ Sequence */
2678+ if (status == LINK_TRAINING_SUCCESS) {
2679+ enum dc_dp_training_pattern tr_pattern;
2680+ uint32_t retries_ch_eq;
2681+ uint32_t wait_time_microsec;
2682+ enum dc_lane_count lane_count = lt_settings->link_settings.lane_count;
2683+ union lane_align_status_updated dpcd_lane_status_updated = {0};
2684+ union lane_status dpcd_lane_status[LANE_COUNT_DP_MAX] = {0};
2685+ union lane_adjust dpcd_lane_adjust[LANE_COUNT_DP_MAX] = {0};
2686+
2687+ /* Note: also check that TPS4 is a supported feature*/
2688+ tr_pattern = lt_settings->pattern_for_eq;
2689+
2690+ dp_set_hw_training_pattern(link, link_res, tr_pattern, 0);
2691+
2692+ status = LINK_TRAINING_EQ_FAIL_EQ;
2693+
2694+ for (retries_ch_eq = 0; retries_ch_eq <= LINK_TRAINING_MAX_RETRY_COUNT;
2695+ retries_ch_eq++) {
2696+
2697+ dp_set_hw_lane_settings(link, link_res, lt_settings, 0);
2698+
2699+ vendor_lttpr_write_data_vs[3] = 0;
2700+ vendor_lttpr_write_data_pe[3] = 0;
2701+
2702+ for (lane = 0; lane < lane_count; lane++) {
2703+ vendor_lttpr_write_data_vs[3] |=
2704+ lt_settings->dpcd_lane_settings[lane].bits.VOLTAGE_SWING_SET << (2 * lane);
2705+ vendor_lttpr_write_data_pe[3] |=
2706+ lt_settings->dpcd_lane_settings[lane].bits.PRE_EMPHASIS_SET << (2 * lane);
2707+ }
2708+
2709+ /* Vendor specific: Update VS and PE to DPRX requested value */
2710+ core_link_write_dpcd(
2711+ link,
2712+ vendor_lttpr_write_address,
2713+ &vendor_lttpr_write_data_vs[0],
2714+ sizeof(vendor_lttpr_write_data_vs));
2715+ core_link_write_dpcd(
2716+ link,
2717+ vendor_lttpr_write_address,
2718+ &vendor_lttpr_write_data_pe[0],
2719+ sizeof(vendor_lttpr_write_data_pe));
2720+
2721+ /* 2. update DPCD*/
2722+ if (!retries_ch_eq)
2723+ /* EPR #361076 - write as a 5-byte burst,
2724+ * but only for the 1-st iteration
2725+ */
2726+
2727+ dpcd_set_lt_pattern_and_lane_settings(
2728+ link,
2729+ lt_settings,
2730+ tr_pattern, 0);
2731+ else
2732+ dpcd_set_lane_settings(link, lt_settings, 0);
2733+
2734+ /* 3. wait for receiver to lock-on*/
2735+ wait_time_microsec = lt_settings->eq_pattern_time;
2736+
2737+ dp_wait_for_training_aux_rd_interval(
2738+ link,
2739+ wait_time_microsec);
2740+
2741+ /* 4. Read lane status and requested
2742+ * drive settings as set by the sink
2743+ */
2744+ dp_get_lane_status_and_lane_adjust(
2745+ link,
2746+ lt_settings,
2747+ dpcd_lane_status,
2748+ &dpcd_lane_status_updated,
2749+ dpcd_lane_adjust,
2750+ 0);
2751+
2752+ /* 5. check CR done*/
2753+ if (!dp_is_cr_done(lane_count, dpcd_lane_status)) {
2754+ status = LINK_TRAINING_EQ_FAIL_CR;
2755+ break;
2756+ }
2757+
2758+ /* 6. check CHEQ done*/
2759+ if (dp_is_ch_eq_done(lane_count, dpcd_lane_status) &&
2760+ dp_is_symbol_locked(lane_count, dpcd_lane_status) &&
2761+ dp_is_interlane_aligned(dpcd_lane_status_updated)) {
2762+ status = LINK_TRAINING_SUCCESS;
2763+ break;
2764+ }
2765+
2766+ /* 7. update VS/PE/PC2 in lt_settings*/
2767+ dp_decide_lane_settings(lt_settings, dpcd_lane_adjust,
2768+ lt_settings->hw_lane_settings, lt_settings->dpcd_lane_settings);
2769+ }
2770+ }
2771+
2772+ return status;
2773+}
2774+
2775+
24302776 enum link_training_result dc_link_dp_perform_link_training(
24312777 struct dc_link *link,
2778+ const struct link_resource *link_res,
24322779 const struct dc_link_settings *link_settings,
24332780 bool skip_video_pattern)
24342781 {
@@ -2459,18 +2806,22 @@ enum link_training_result dc_link_dp_perform_link_training( · 24 unmodified lines
24592806
24602807 /* configure link prior to entering training mode */
24612808 dpcd_configure_lttpr_mode(link, &lt_settings);
2462− dp_set_fec_ready(link, lt_settings.should_set_fec_ready);
2809+ dp_set_fec_ready(link, link_res, lt_settings.should_set_fec_ready);
24632810 dpcd_configure_channel_coding(link, &lt_settings);
24642811
24652812 /* enter training mode:
24662813 * Per DP specs starting from here, DPTX device shall not issue
24672814 * Non-LT AUX transactions inside training mode.
24682815 */
2469− if (encoding == DP_8b_10b_ENCODING)
2470− status = dp_perform_8b_10b_link_training(link, &lt_settings);
2816+ if (!link->dc->debug.apply_vendor_specific_lttpr_wa &&
2817+ (link->chip_caps & EXT_DISPLAY_PATH_CAPS__DP_FIXED_VS_EN) &&
2818+ link->lttpr_mode == LTTPR_MODE_TRANSPARENT)
2819+ status = dc_link_dp_perform_fixed_vs_pe_training_sequence(link, link_res, &lt_settings);
2820+ else if (encoding == DP_8b_10b_ENCODING)
2821+ status = dp_perform_8b_10b_link_training(link, link_res, &lt_settings);
24712822 #if defined(CONFIG_DRM_AMD_DC_DCN)
24722823 else if (encoding == DP_128b_132b_ENCODING)
2473− status = dp_perform_128b_132b_link_training(link, &lt_settings);
2824+ status = dp_perform_128b_132b_link_training(link, link_res, &lt_settings);
24742825 #endif
24752826 else
24762827 ASSERT(0);
@@ -2488,6 +2839,7 @@ enum link_training_result dc_link_dp_perform_link_training( · 11 unmodified lines
24882839 /* switch to video idle */
24892840 if ((status == LINK_TRAINING_SUCCESS) || !skip_video_pattern)
24902841 status = dp_transition_to_video_idle(link,
2842+ link_res,
24912843 &lt_settings,
24922844 status);
24932845
@@ -2539,6 +2891,7 @@ bool perform_link_training_with_retries( · 45 unmodified lines
25392891
25402892 dp_enable_link_phy(
25412893 link,
2894+ &pipe_ctx->link_res,
25422895 signal,
25432896 pipe_ctx->clock_source->id,
25442897 &current_setting);
@@ -2566,23 +2919,24 @@ bool perform_link_training_with_retries( · 21 unmodified lines
25662919 dp_set_panel_mode(link, panel_mode);
25672920
25682921 if (link->aux_access_disabled) {
2569− dc_link_dp_perform_link_training_skip_aux(link, &current_setting);
2922+ dc_link_dp_perform_link_training_skip_aux(link, &pipe_ctx->link_res, &current_setting);
25702923 return true;
25712924 } else {
25722925 /** @todo Consolidate USB4 DP and DPx.x training. */
25732926 if (link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA) {
25742927 status = dc_link_dpia_perform_link_training(link,
2575− &current_setting,
2576− skip_video_pattern);
2928+ &pipe_ctx->link_res,
2929+ &current_setting,
2930+ skip_video_pattern);
25772931
25782932 /* Transmit idle pattern once training successful. */
25792933 if (status == LINK_TRAINING_SUCCESS)
2580− dp_set_hw_test_pattern(link, DP_TEST_PATTERN_VIDEO_MODE,
2581− NULL, 0);
2934+ dp_set_hw_test_pattern(link, &pipe_ctx->link_res, DP_TEST_PATTERN_VIDEO_MODE, NULL, 0);
25822935 } else {
25832936 status = dc_link_dp_perform_link_training(link,
2584− &current_setting,
2585− skip_video_pattern);
2937+ &pipe_ctx->link_res,
2938+ &current_setting,
2939+ skip_video_pattern);
25862940 }
25872941
25882942 if (status == LINK_TRAINING_SUCCESS)
@@ -2597,7 +2951,7 @@ bool perform_link_training_with_retries( · 8 unmodified lines
25972951 DC_LOG_WARNING("%s: Link training attempt %u of %d failed\n",
25982952 __func__, (unsigned int)j + 1, attempts);
25992953
2600− dp_disable_link_phy(link, signal);
2954+ dp_disable_link_phy(link, &pipe_ctx->link_res, signal);
26012955
26022956 /* Abort link training if failure due to sink being unplugged. */
26032957 if (status == LINK_TRAINING_ABORT) {
@@ -2646,12 +3000,13 @@ static enum clock_source_id get_clock_source_id(struct dc_link *link) · 42 unmodified lines
26463000 return dp_cs_id;
26473001 }
26483002
2649−static void set_dp_mst_mode(struct dc_link *link, bool mst_enable)
3003+static void set_dp_mst_mode(struct dc_link *link, const struct link_resource *link_res,
3004+ bool mst_enable)
26503005 {
26513006 if (mst_enable == false &&
26523007 link->type == dc_connection_mst_branch) {
26533008 /* Disable MST on link. Use only local sink. */
2654− dp_disable_link_phy_mst(link, link->connector_signal);
3009+ dp_disable_link_phy_mst(link, link_res, link->connector_signal);
26553010
26563011 link->type = dc_connection_single;
26573012 link->local_sink = link->remote_sinks[0];
@@ -2662,7 +3017,7 @@ static void set_dp_mst_mode(struct dc_link *link, bool mst_enable) · 4 unmodified lines
26623017 link->type == dc_connection_single &&
26633018 link->remote_sinks[0] != NULL) {
26643019 /* Re-enable MST on link. */
2665− dp_disable_link_phy(link, link->connector_signal);
3020+ dp_disable_link_phy(link, link_res, link->connector_signal);
26663021 dp_enable_mst_on_sink(link, true);
26673022
26683023 link->type = dc_connection_mst_branch;
@@ -2688,6 +3043,7 @@ bool dc_link_dp_sync_lt_begin(struct dc_link *link) · 19 unmodified lines
26883043
26893044 enum link_training_result dc_link_dp_sync_lt_attempt(
26903045 struct dc_link *link,
3046+ const struct link_resource *link_res,
26913047 struct dc_link_settings *link_settings,
26923048 struct dc_link_training_overrides *lt_overrides)
26933049 {
@@ -2707,14 +3063,14 @@ enum link_training_result dc_link_dp_sync_lt_attempt( · 13 unmodified lines
27073063 &lt_settings);
27083064 /* Setup MST Mode */
27093065 if (lt_overrides->mst_enable)
2710− set_dp_mst_mode(link, *lt_overrides->mst_enable);
3066+ set_dp_mst_mode(link, link_res, *lt_overrides->mst_enable);
27113067
27123068 /* Disable link */
2713− dp_disable_link_phy(link, link->connector_signal);
3069+ dp_disable_link_phy(link, link_res, link->connector_signal);
27143070
27153071 /* Enable link */
27163072 dp_cs_id = get_clock_source_id(link);
2717− dp_enable_link_phy(link, link->connector_signal,
3073+ dp_enable_link_phy(link, link_res, link->connector_signal,
27183074 dp_cs_id, link_settings);
27193075
27203076 /* Set FEC enable */
@@ -2722,7 +3078,7 @@ enum link_training_result dc_link_dp_sync_lt_attempt( · 1 unmodified line
27223078 if (dp_get_link_encoding_format(link_settings) == DP_8b_10b_ENCODING) {
27233079 #endif
27243080 fec_enable = lt_overrides->fec_enable && *lt_overrides->fec_enable;
2725− dp_set_fec_ready(link, fec_enable);
3081+ dp_set_fec_ready(link, NULL, fec_enable);
27263082 #if defined(CONFIG_DRM_AMD_DC_DCN)
27273083 }
27283084 #endif
@@ -2739,7 +3095,7 @@ enum link_training_result dc_link_dp_sync_lt_attempt( · 10 unmodified lines
27393095
27403096 /* Attempt to train with given link training settings */
27413097 if (link->ctx->dc->work_arounds.lt_early_cr_pattern)
2742− start_clock_recovery_pattern_early(link, &lt_settings, DPRX);
3098+ start_clock_recovery_pattern_early(link, link_res, &lt_settings, DPRX);
27433099
27443100 /* Set link rate, lane count and spread. */
27453101 dpcd_set_link_settings(link, &lt_settings);
@@ -2747,9 +3103,10 @@ enum link_training_result dc_link_dp_sync_lt_attempt( · 1 unmodified line
27473103 /* 2. perform link training (set link training done
27483104 * to false is done as well)
27493105 */
2750− lt_status = perform_clock_recovery_sequence(link, &lt_settings, DPRX);
3106+ lt_status = perform_clock_recovery_sequence(link, link_res, &lt_settings, DPRX);
27513107 if (lt_status == LINK_TRAINING_SUCCESS) {
27523108 lt_status = perform_channel_equalization_sequence(link,
3109+ link_res,
27533110 &lt_settings,
27543111 DPRX);
27553112 }
@@ -2770,11 +3127,11 @@ bool dc_link_dp_sync_lt_end(struct dc_link *link, bool link_down) · 14 unmodified lines
27703127 #if defined(CONFIG_DRM_AMD_DC_DCN)
27713128 struct dc_link_settings link_settings = link->cur_link_settings;
27723129 #endif
2773− dp_disable_link_phy(link, link->connector_signal);
3130+ dp_disable_link_phy(link, NULL, link->connector_signal);
27743131 #if defined(CONFIG_DRM_AMD_DC_DCN)
27753132 if (dp_get_link_encoding_format(&link_settings) == DP_8b_10b_ENCODING)
27763133 #endif
2777− dp_set_fec_ready(link, false);
3134+ dp_set_fec_ready(link, NULL, false);
27783135 }
27793136
27803137 link->sync_lt_in_progress = false;
@@ -2829,7 +3186,8 @@ bool dc_link_dp_get_max_link_enc_cap(const struct dc_link *link, struct dc_link_ · 48 unmodified lines
28293186 return false;
28303187 }
28313188
2832−static struct dc_link_settings get_max_link_cap(struct dc_link *link)
3189+static struct dc_link_settings get_max_link_cap(struct dc_link *link,
3190+ const struct link_resource *link_res)
28333191 {
28343192 struct dc_link_settings max_link_cap = {0};
28353193 #if defined(CONFIG_DRM_AMD_DC_DCN)
@@ -2853,9 +3211,11 @@ static struct dc_link_settings get_max_link_cap(struct dc_link *link) · 17 unmodified lines
28533211 if (link_enc)
28543212 link_enc->funcs->get_max_link_cap(link_enc, &max_link_cap);
28553213 #if defined(CONFIG_DRM_AMD_DC_DCN)
2856− if (max_link_cap.link_rate >= LINK_RATE_UHBR10 &&
2857− !link->hpo_dp_link_enc)
2858− max_link_cap.link_rate = LINK_RATE_HIGH3;
3214+ if (max_link_cap.link_rate >= LINK_RATE_UHBR10) {
3215+ if (!link_res->hpo_dp_link_enc ||
3216+ link->dc->debug.disable_uhbr)
3217+ max_link_cap.link_rate = LINK_RATE_HIGH3;
3218+ }
28593219 #endif
28603220
28613221 /* Lower link settings based on sink's link cap */
@@ -2873,7 +3233,7 @@ static struct dc_link_settings get_max_link_cap(struct dc_link *link) · 11 unmodified lines
28733233 * account for lttpr repeaters cap
28743234 * notes: repeaters do not snoop in the DPRX Capabilities addresses (3.6.3).
28753235 */
2876− if (link->lttpr_mode == LTTPR_MODE_NON_TRANSPARENT) {
3236+ if (link->lttpr_mode != LTTPR_MODE_NON_LTTPR) {
28773237 if (link->dpcd_caps.lttpr_caps.max_lane_count < max_link_cap.lane_count)
28783238 max_link_cap.lane_count = link->dpcd_caps.lttpr_caps.max_lane_count;
28793239
@@ -3012,6 +3372,7 @@ bool hpd_rx_irq_check_link_loss_status( · 132 unmodified lines
30123372
30133373 bool dp_verify_link_cap(
30143374 struct dc_link *link,
3375+ const struct link_resource *link_res,
30153376 struct dc_link_settings *known_limit_link_setting,
30163377 int *fail_count)
30173378 {
@@ -3029,7 +3390,7 @@ bool dp_verify_link_cap( · 11 unmodified lines
30293390 /* link training starts with the maximum common settings
30303391 * supported by both sink and ASIC.
30313392 */
3032− max_link_cap = get_max_link_cap(link);
3393+ max_link_cap = get_max_link_cap(link, link_res);
30333394 initial_link_settings = get_common_supported_link_settings(
30343395 *known_limit_link_setting,
30353396 max_link_cap);
@@ -3069,7 +3430,7 @@ bool dp_verify_link_cap( · 33 unmodified lines
30693430 * find the physical link capability
30703431 */
30713432 /* disable PHY done possible by BIOS, will be done by driver itself */
3072− dp_disable_link_phy(link, link->connector_signal);
3433+ dp_disable_link_phy(link, link_res, link->connector_signal);
30733434
30743435 dp_cs_id = get_clock_source_id(link);
30753436
@@ -3081,8 +3442,8 @@ bool dp_verify_link_cap( · 5 unmodified lines
30813442 */
30823443 if (link->link_enc && link->link_enc->features.flags.bits.DP_IS_USB_C &&
30833444 link->dc->debug.usbc_combo_phy_reset_wa) {
3084− dp_enable_link_phy(link, link->connector_signal, dp_cs_id, cur);
3085− dp_disable_link_phy(link, link->connector_signal);
3445+ dp_enable_link_phy(link, link_res, link->connector_signal, dp_cs_id, cur);
3446+ dp_disable_link_phy(link, link_res, link->connector_signal);
30863447 }
30873448
30883449 do {
@@ -3093,6 +3454,7 @@ bool dp_verify_link_cap( · 4 unmodified lines
30933454
30943455 dp_enable_link_phy(
30953456 link,
3457+ link_res,
30963458 link->connector_signal,
30973459 dp_cs_id,
30983460 cur);
@@ -3103,6 +3465,7 @@ bool dp_verify_link_cap( · 4 unmodified lines
31033465 else {
31043466 status = dc_link_dp_perform_link_training(
31053467 link,
3468+ link_res,
31063469 cur,
31073470 skip_video_pattern);
31083471 if (status == LINK_TRAINING_SUCCESS)
@@ -3124,7 +3487,7 @@ bool dp_verify_link_cap( · 15 unmodified lines
31243487 * setting or before returning we'll enable it later
31253488 * based on the actual mode we're driving
31263489 */
3127− dp_disable_link_phy(link, link->connector_signal);
3490+ dp_disable_link_phy(link, link_res, link->connector_signal);
31283491 } while (!success && decide_fallback_link_setting(link,
31293492 initial_link_settings, cur, status));
31303493
@@ -3148,6 +3511,7 @@ bool dp_verify_link_cap( · 17 unmodified lines
31483511
31493512 bool dp_verify_link_cap_with_retries(
31503513 struct dc_link *link,
3514+ const struct link_resource *link_res,
31513515 struct dc_link_settings *known_limit_link_setting,
31523516 int attempts)
31533517 {
@@ -3165,7 +3529,7 @@ bool dp_verify_link_cap_with_retries( · 11 unmodified lines
31653529 link->verified_link_cap.link_rate = LINK_RATE_LOW;
31663530 link->verified_link_cap.link_spread = LINK_SPREAD_DISABLED;
31673531 break;
3168− } else if (dp_verify_link_cap(link,
3532+ } else if (dp_verify_link_cap(link, link_res,
31693533 known_limit_link_setting,
31703534 &fail_count) && fail_count == 0) {
31713535 success = true;
@@ -3177,13 +3541,13 @@ bool dp_verify_link_cap_with_retries( · 5 unmodified lines
31773541 }
31783542
31793543 bool dp_verify_mst_link_cap(
3180− struct dc_link *link)
3544+ struct dc_link *link, const struct link_resource *link_res)
31813545 {
31823546 struct dc_link_settings max_link_cap = {0};
31833547
31843548 if (dp_get_link_encoding_format(&link->reported_link_cap) ==
31853549 DP_8b_10b_ENCODING) {
3186− max_link_cap = get_max_link_cap(link);
3550+ max_link_cap = get_max_link_cap(link, link_res);
31873551 link->verified_link_cap = get_common_supported_link_settings(
31883552 link->reported_link_cap,
31893553 max_link_cap);
@@ -3192,6 +3556,7 @@ bool dp_verify_mst_link_cap( · 2 unmodified lines
31923556 else if (dp_get_link_encoding_format(&link->reported_link_cap) ==
31933557 DP_128b_132b_ENCODING) {
31943558 dp_verify_link_cap_with_retries(link,
3559+ link_res,
31953560 &link->reported_link_cap,
31963561 LINK_TRAINING_MAX_VERIFY_RETRY);
31973562 }
@@ -5720,7 +6085,7 @@ bool dc_link_dp_set_test_pattern( · 2522 unmodified lines
57206085 DP_TEST_PATTERN_VIDEO_MODE) {
57216086 /* Set CRTC Test Pattern */
57226087 set_crtc_test_pattern(link, pipe_ctx, test_pattern, test_pattern_color_space);
5723− dp_set_hw_test_pattern(link, test_pattern,
6088+ dp_set_hw_test_pattern(link, &pipe_ctx->link_res, test_pattern,
57246089 (uint8_t *)p_custom_pattern,
57256090 (uint32_t)cust_pattern_size);
57266091
@@ -5751,7 +6116,7 @@ bool dc_link_dp_set_test_pattern( · 24 unmodified lines
57516116 p_link_settings->dpcd_lane_settings,
57526117 p_link_settings->link_settings.lane_count);
57536118 } else {
5754− dp_set_hw_lane_settings(link, p_link_settings, DPRX);
6119+ dp_set_hw_lane_settings(link, &pipe_ctx->link_res, p_link_settings, DPRX);
57556120 dpcd_set_lane_settings(link, p_link_settings, DPRX);
57566121 }
57576122 }
@@ -5766,7 +6131,7 @@ bool dc_link_dp_set_test_pattern( · 8 unmodified lines
57666131 pipes->stream_res.stream_enc->funcs->dp_blank(link, pipe_ctx->stream_res.stream_enc);
57676132 }
57686133
5769− dp_set_hw_test_pattern(link, test_pattern,
6134+ dp_set_hw_test_pattern(link, &pipe_ctx->link_res, test_pattern,
57706135 (uint8_t *)p_custom_pattern,
57716136 (uint32_t)cust_pattern_size);
57726137
@@ -6086,7 +6451,7 @@ enum dp_panel_mode dp_get_panel_mode(struct dc_link *link) · 313 unmodified lines
60866451 return DP_PANEL_MODE_DEFAULT;
60876452 }
60886453
6089−enum dc_status dp_set_fec_ready(struct dc_link *link, bool ready)
6454+enum dc_status dp_set_fec_ready(struct dc_link *link, const struct link_resource *link_res, bool ready)
60906455 {
60916456 /* FEC has to be "set ready" before the link training.
60926457 * The policy is to always train with FEC
@@ -6653,8 +7018,10 @@ struct fixed31_32 calculate_sst_avg_time_slots_per_mtp( · 560 unmodified lines
66537018
66547019 bool is_dp_128b_132b_signal(struct pipe_ctx *pipe_ctx)
66557020 {
7021+ /* If this assert is hit then we have a link encoder dynamic management issue */
7022+ ASSERT(pipe_ctx->stream_res.hpo_dp_stream_enc ? pipe_ctx->link_res.hpo_dp_link_enc != NULL : true);
66567023 return (pipe_ctx->stream_res.hpo_dp_stream_enc &&
6657− pipe_ctx->stream->link->hpo_dp_link_enc &&
7024+ pipe_ctx->link_res.hpo_dp_link_enc &&
66587025 dc_is_dp_signal(pipe_ctx->stream->signal));
66597026 }
66607027 #endif
drivers/gpu/drm/amd/display/dc/core/dc_link_dpia.c+32−16
@@ -77,7 +77,9 @@ enum dc_status dpcd_get_tunneling_device_data(struct dc_link *link) · 76 unmodified lines
7777 * @param[in] link_setting Lane count, link rate and downspread control.
7878 * @param[out] lt_settings Link settings and drive settings (voltage swing and pre-emphasis).
7979 */
80−static enum link_training_result dpia_configure_link(struct dc_link *link,
80+static enum link_training_result dpia_configure_link(
81+ struct dc_link *link,
82+ const struct link_resource *link_res,
8183 const struct dc_link_settings *link_setting,
8284 struct link_training_settings *lt_settings)
8385 {
@@ -111,7 +113,7 @@ static enum link_training_result dpia_configure_link(struct dc_link *link, · 27 unmodified lines
111113 fec_enable = *link->preferred_training_settings.fec_enable;
112114 else
113115 fec_enable = true;
114− status = dp_set_fec_ready(link, fec_enable);
116+ status = dp_set_fec_ready(link, link_res, fec_enable);
115117 if (status != DC_OK && link->is_hpd_pending)
116118 return LINK_TRAINING_ABORT;
117119
@@ -252,7 +254,9 @@ static enum dc_status dpcd_set_lt_pattern(struct dc_link *link, · 134 unmodified lines
252254 * @param lt_settings link_setting and drive settings (voltage swing and pre-emphasis).
253255 * @param hop The Hop in display path. DPRX = 0.
254256 */
255−static enum link_training_result dpia_training_cr_non_transparent(struct dc_link *link,
257+static enum link_training_result dpia_training_cr_non_transparent(
258+ struct dc_link *link,
259+ const struct link_resource *link_res,
256260 struct link_training_settings *lt_settings,
257261 uint32_t hop)
258262 {
@@ -411,7 +415,9 @@ static enum link_training_result dpia_training_cr_non_transparent(struct dc_link · 152 unmodified lines
411415 * @param link DPIA link being trained.
412416 * @param lt_settings link_setting and drive settings (voltage swing and pre-emphasis).
413417 */
414−static enum link_training_result dpia_training_cr_transparent(struct dc_link *link,
418+static enum link_training_result dpia_training_cr_transparent(
419+ struct dc_link *link,
420+ const struct link_resource *link_res,
415421 struct link_training_settings *lt_settings)
416422 {
417423 enum link_training_result result = LINK_TRAINING_CR_FAIL_LANE0;
@@ -511,16 +517,18 @@ static enum link_training_result dpia_training_cr_transparent(struct dc_link *li · 93 unmodified lines
511517 * @param lt_settings link_setting and drive settings (voltage swing and pre-emphasis).
512518 * @param hop The Hop in display path. DPRX = 0.
513519 */
514−static enum link_training_result dpia_training_cr_phase(struct dc_link *link,
520+static enum link_training_result dpia_training_cr_phase(
521+ struct dc_link *link,
522+ const struct link_resource *link_res,
515523 struct link_training_settings *lt_settings,
516524 uint32_t hop)
517525 {
518526 enum link_training_result result = LINK_TRAINING_CR_FAIL_LANE0;
519527
520528 if (link->lttpr_mode == LTTPR_MODE_NON_TRANSPARENT)
521− result = dpia_training_cr_non_transparent(link, lt_settings, hop);
529+ result = dpia_training_cr_non_transparent(link, link_res, lt_settings, hop);
522530 else
523− result = dpia_training_cr_transparent(link, lt_settings);
531+ result = dpia_training_cr_transparent(link, link_res, lt_settings);
524532
525533 return result;
526534 }
@@ -561,7 +569,9 @@ static uint32_t dpia_get_eq_aux_rd_interval(const struct dc_link *link, · 34 unmodified lines
561569 * @param lt_settings link_setting and drive settings (voltage swing and pre-emphasis).
562570 * @param hop The Hop in display path. DPRX = 0.
563571 */
564−static enum link_training_result dpia_training_eq_non_transparent(struct dc_link *link,
572+static enum link_training_result dpia_training_eq_non_transparent(
573+ struct dc_link *link,
574+ const struct link_resource *link_res,
565575 struct link_training_settings *lt_settings,
566576 uint32_t hop)
567577 {
@@ -700,7 +710,9 @@ static enum link_training_result dpia_training_eq_non_transparent(struct dc_link · 132 unmodified lines
700710 * @param lt_settings link_setting and drive settings (voltage swing and pre-emphasis).
701711 * @param hop The Hop in display path. DPRX = 0.
702712 */
703−static enum link_training_result dpia_training_eq_transparent(struct dc_link *link,
713+static enum link_training_result dpia_training_eq_transparent(
714+ struct dc_link *link,
715+ const struct link_resource *link_res,
704716 struct link_training_settings *lt_settings)
705717 {
706718 enum link_training_result result = LINK_TRAINING_EQ_FAIL_EQ;
@@ -779,16 +791,18 @@ static enum link_training_result dpia_training_eq_transparent(struct dc_link *li · 72 unmodified lines
779791 * @param lt_settings link_setting and drive settings (voltage swing and pre-emphasis).
780792 * @param hop The Hop in display path. DPRX = 0.
781793 */
782−static enum link_training_result dpia_training_eq_phase(struct dc_link *link,
794+static enum link_training_result dpia_training_eq_phase(
795+ struct dc_link *link,
796+ const struct link_resource *link_res,
783797 struct link_training_settings *lt_settings,
784798 uint32_t hop)
785799 {
786800 enum link_training_result result;
787801
788802 if (link->lttpr_mode == LTTPR_MODE_NON_TRANSPARENT)
789− result = dpia_training_eq_non_transparent(link, lt_settings, hop);
803+ result = dpia_training_eq_non_transparent(link, link_res, lt_settings, hop);
790804 else
791− result = dpia_training_eq_transparent(link, lt_settings);
805+ result = dpia_training_eq_transparent(link, link_res, lt_settings);
792806
793807 return result;
794808 }
@@ -908,7 +922,9 @@ static void dpia_training_abort(struct dc_link *link, uint32_t hop) · 113 unmodified lines
908922 core_link_send_set_config(link, DPIA_SET_CFG_SET_LINK, data);
909923 }
910924
911−enum link_training_result dc_link_dpia_perform_link_training(struct dc_link *link,
925+enum link_training_result dc_link_dpia_perform_link_training(
926+ struct dc_link *link,
927+ const struct link_resource *link_res,
912928 const struct dc_link_settings *link_setting,
913929 bool skip_video_pattern)
914930 {
@@ -918,7 +934,7 @@ enum link_training_result dc_link_dpia_perform_link_training(struct dc_link *lin · 3 unmodified lines
918934 int8_t repeater_id; /* Current hop. */
919935
920936 /* Configure link as prescribed in link_setting and set LTTPR mode. */
921− result = dpia_configure_link(link, link_setting, &lt_settings);
937+ result = dpia_configure_link(link, link_res, link_setting, &lt_settings);
922938 if (result != LINK_TRAINING_SUCCESS)
923939 return result;
924940
@@ -930,12 +946,12 @@ enum link_training_result dc_link_dpia_perform_link_training(struct dc_link *lin · 5 unmodified lines
930946 */
931947 for (repeater_id = repeater_cnt; repeater_id >= 0; repeater_id--) {
932948 /* Clock recovery. */
933− result = dpia_training_cr_phase(link, &lt_settings, repeater_id);
949+ result = dpia_training_cr_phase(link, link_res, &lt_settings, repeater_id);
934950 if (result != LINK_TRAINING_SUCCESS)
935951 break;
936952
937953 /* Equalization. */
938− result = dpia_training_eq_phase(link, &lt_settings, repeater_id);
954+ result = dpia_training_eq_phase(link, link_res, &lt_settings, repeater_id);
939955 if (result != LINK_TRAINING_SUCCESS)
940956 break;
941957
drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c+37−26
@@ -71,6 +71,7 @@ void dp_source_sequence_trace(struct dc_link *link, uint8_t dp_test_mode) · 70 unmodified lines
7171
7272 void dp_enable_link_phy(
7373 struct dc_link *link,
74+ const struct link_resource *link_res,
7475 enum signal_type signal,
7576 enum clock_source_id clock_source,
7677 const struct dc_link_settings *link_settings)
@@ -135,7 +136,7 @@ void dp_enable_link_phy( · 58 unmodified lines
135136
136137 #if defined(CONFIG_DRM_AMD_DC_DCN)
137138 if (dp_get_link_encoding_format(link_settings) == DP_128b_132b_ENCODING) {
138− enable_dp_hpo_output(link, link_settings);
139+ enable_dp_hpo_output(link, link_res, link_settings);
139140 } else if (dp_get_link_encoding_format(link_settings) == DP_8b_10b_ENCODING) {
140141 if (dc_is_dp_sst_signal(signal)) {
141142 link_enc->funcs->enable_dp_output(
@@ -236,12 +237,13 @@ bool edp_receiver_ready_T7(struct dc_link *link) · 94 unmodified lines
236237 return result;
237238 }
238239
239−void dp_disable_link_phy(struct dc_link *link, enum signal_type signal)
240+void dp_disable_link_phy(struct dc_link *link, const struct link_resource *link_res,
241+ enum signal_type signal)
240242 {
241243 struct dc *dc = link->ctx->dc;
242244 struct dmcu *dmcu = dc->res_pool->dmcu;
243245 #if defined(CONFIG_DRM_AMD_DC_DCN)
244− struct hpo_dp_link_encoder *hpo_link_enc = link->hpo_dp_link_enc;
246+ struct hpo_dp_link_encoder *hpo_link_enc = link_res->hpo_dp_link_enc;
245247 #endif
246248 struct link_encoder *link_enc;
247249
@@ -260,7 +262,7 @@ void dp_disable_link_phy(struct dc_link *link, enum signal_type signal) · 12 unmodified lines
260262 link->dc->hwss.edp_backlight_control(link, false);
261263 #if defined(CONFIG_DRM_AMD_DC_DCN)
262264 if (dp_get_link_encoding_format(&link->cur_link_settings) == DP_128b_132b_ENCODING)
263− disable_dp_hpo_output(link, signal);
265+ disable_dp_hpo_output(link, link_res, signal);
264266 else
265267 link_enc->funcs->disable_output(link_enc, signal);
266268 #else
@@ -274,7 +276,7 @@ void dp_disable_link_phy(struct dc_link *link, enum signal_type signal) · 7 unmodified lines
274276 #if defined(CONFIG_DRM_AMD_DC_DCN)
275277 if (dp_get_link_encoding_format(&link->cur_link_settings) == DP_128b_132b_ENCODING &&
276278 hpo_link_enc)
277− disable_dp_hpo_output(link, signal);
279+ disable_dp_hpo_output(link, link_res, signal);
278280 else
279281 link_enc->funcs->disable_output(link_enc, signal);
280282 #else
@@ -294,13 +296,14 @@ void dp_disable_link_phy(struct dc_link *link, enum signal_type signal) · 13 unmodified lines
294296 dc->clk_mgr->funcs->notify_link_rate_change(dc->clk_mgr, link);
295297 }
296298
297−void dp_disable_link_phy_mst(struct dc_link *link, enum signal_type signal)
299+void dp_disable_link_phy_mst(struct dc_link *link, const struct link_resource *link_res,
300+ enum signal_type signal)
298301 {
299302 /* MST disable link only when no stream use the link */
300303 if (link->mst_stream_alloc_table.stream_count > 0)
301304 return;
302305
303− dp_disable_link_phy(link, signal);
306+ dp_disable_link_phy(link, link_res, signal);
304307
305308 /* set the sink to SST mode after disabling the link */
306309 dp_enable_mst_on_sink(link, false);
@@ -308,6 +311,7 @@ void dp_disable_link_phy_mst(struct dc_link *link, enum signal_type signal) · 1 unmodified line
308311
309312 bool dp_set_hw_training_pattern(
310313 struct dc_link *link,
314+ const struct link_resource *link_res,
311315 enum dc_dp_training_pattern pattern,
312316 uint32_t offset)
313317 {
@@ -338,7 +342,7 @@ bool dp_set_hw_training_pattern( · 24 unmodified lines
338342 break;
339343 }
340344
341− dp_set_hw_test_pattern(link, test_pattern, NULL, 0);
345+ dp_set_hw_test_pattern(link, link_res, test_pattern, NULL, 0);
342346
343347 return true;
344348 }
@@ -349,6 +353,7 @@ bool dp_set_hw_training_pattern( · 4 unmodified lines
349353 #endif
350354 void dp_set_hw_lane_settings(
351355 struct dc_link *link,
356+ const struct link_resource *link_res,
352357 const struct link_training_settings *link_settings,
353358 uint32_t offset)
354359 {
@@ -361,8 +366,8 @@ void dp_set_hw_lane_settings( · 6 unmodified lines
361366 #if defined(CONFIG_DRM_AMD_DC_DCN)
362367 if (dp_get_link_encoding_format(&link_settings->link_settings) ==
363368 DP_128b_132b_ENCODING) {
364− link->hpo_dp_link_enc->funcs->set_ffe(
365− link->hpo_dp_link_enc,
369+ link_res->hpo_dp_link_enc->funcs->set_ffe(
370+ link_res->hpo_dp_link_enc,
366371 &link_settings->link_settings,
367372 link_settings->lane_settings[0].FFE_PRESET.raw);
368373 } else if (dp_get_link_encoding_format(&link_settings->link_settings)
@@ -379,6 +384,7 @@ void dp_set_hw_lane_settings( · 10 unmodified lines
379384
380385 void dp_set_hw_test_pattern(
381386 struct dc_link *link,
387+ const struct link_resource *link_res,
382388 enum dp_test_pattern test_pattern,
383389 uint8_t *custom_pattern,
384390 uint32_t custom_pattern_size)
@@ -406,8 +412,8 @@ void dp_set_hw_test_pattern( · 21 unmodified lines
406412 #if defined(CONFIG_DRM_AMD_DC_DCN)
407413 switch (link_encoding_format) {
408414 case DP_128b_132b_ENCODING:
409− link->hpo_dp_link_enc->funcs->set_link_test_pattern(
410− link->hpo_dp_link_enc, &pattern_param);
415+ link_res->hpo_dp_link_enc->funcs->set_link_test_pattern(
416+ link_res->hpo_dp_link_enc, &pattern_param);
411417 break;
412418 case DP_8b_10b_ENCODING:
413419 ASSERT(encoder);
@@ -446,7 +452,7 @@ void dp_retrain_link_dp_test(struct dc_link *link, · 32 unmodified lines
446452 pipes[i].stream_res.stream_enc);
447453
448454 /* disable any test pattern that might be active */
449− dp_set_hw_test_pattern(link,
455+ dp_set_hw_test_pattern(link, &pipes[i].link_res,
450456 DP_TEST_PATTERN_VIDEO_MODE, NULL, 0);
451457
452458 dp_receiver_power_ctrl(link, false);
@@ -763,7 +769,9 @@ static enum phyd32clk_clock_source get_phyd32clk_src(struct dc_link *link) · 310 unmodified lines
763769 }
764770 }
765771
766−void enable_dp_hpo_output(struct dc_link *link, const struct dc_link_settings *link_settings)
772+void enable_dp_hpo_output(struct dc_link *link,
773+ const struct link_resource *link_res,
774+ const struct dc_link_settings *link_settings)
767775 {
768776 const struct dc *dc = link->dc;
769777 enum phyd32clk_clock_source phyd32clk;
@@ -789,10 +797,11 @@ void enable_dp_hpo_output(struct dc_link *link, const struct dc_link_settings *l · 19 unmodified lines
789797 }
790798 } else {
791799 /* DP2.0 HW: call transmitter control to enable PHY */
792− link->hpo_dp_link_enc->funcs->enable_link_phy(
793− link->hpo_dp_link_enc,
800+ link_res->hpo_dp_link_enc->funcs->enable_link_phy(
801+ link_res->hpo_dp_link_enc,
794802 link_settings,
795− link->link_enc->transmitter);
803+ link->link_enc->transmitter,
804+ link->link_enc->hpd_source);
796805 }
797806
798807 /* DCCG muxing and DTBCLK DTO */
@@ -806,24 +815,26 @@ void enable_dp_hpo_output(struct dc_link *link, const struct dc_link_settings *l · 7 unmodified lines
806815 phyd32clk = get_phyd32clk_src(link);
807816 dc->res_pool->dccg->funcs->enable_symclk32_le(
808817 dc->res_pool->dccg,
809− link->hpo_dp_link_enc->inst,
818+ link_res->hpo_dp_link_enc->inst,
810819 phyd32clk);
811− link->hpo_dp_link_enc->funcs->link_enable(
812− link->hpo_dp_link_enc,
813− link_settings->lane_count);
820+ link_res->hpo_dp_link_enc->funcs->link_enable(
821+ link_res->hpo_dp_link_enc,
822+ link_settings->lane_count);
814823 }
815824 }
816825
817−void disable_dp_hpo_output(struct dc_link *link, enum signal_type signal)
826+void disable_dp_hpo_output(struct dc_link *link,
827+ const struct link_resource *link_res,
828+ enum signal_type signal)
818829 {
819830 const struct dc *dc = link->dc;
820831
821− link->hpo_dp_link_enc->funcs->link_disable(link->hpo_dp_link_enc);
832+ link_res->hpo_dp_link_enc->funcs->link_disable(link_res->hpo_dp_link_enc);
822833
823834 if (IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {
824835 dc->res_pool->dccg->funcs->disable_symclk32_le(
825836 dc->res_pool->dccg,
826− link->hpo_dp_link_enc->inst);
837+ link_res->hpo_dp_link_enc->inst);
827838
828839 dc->res_pool->dccg->funcs->set_physymclk(
829840 dc->res_pool->dccg,
@@ -834,8 +845,8 @@ void disable_dp_hpo_output(struct dc_link *link, enum signal_type signal) · 4 unmodified lines
834845 dm_set_phyd32clk(dc->ctx, 0);
835846 } else {
836847 /* DP2.0 HW: call transmitter control to disable PHY */
837− link->hpo_dp_link_enc->funcs->disable_link_phy(
838− link->hpo_dp_link_enc,
848+ link_res->hpo_dp_link_enc->funcs->disable_link_phy(
849+ link_res->hpo_dp_link_enc,
839850 signal);
840851 }
841852 }
drivers/gpu/drm/amd/display/dc/core/dc_resource.c+127−72
@@ -734,10 +734,6 @@ static void calculate_split_count_and_index(struct pipe_ctx *pipe_ctx, int *spli · 733 unmodified lines
734734 (*split_idx)++;
735735 split_pipe = split_pipe->top_pipe;
736736 }
737−
738− /* MPO window on right side of ODM split */
739− if (split_pipe && split_pipe->prev_odm_pipe && !pipe_ctx->prev_odm_pipe)
740− (*split_idx)++;
741737 } else {
742738 /*Get odm split index*/
743739 struct pipe_ctx *split_pipe = pipe_ctx->prev_odm_pipe;
@@ -784,11 +780,7 @@ static void calculate_recout(struct pipe_ctx *pipe_ctx) · 40 unmodified lines
784780 /*
785781 * Only the leftmost ODM pipe should be offset by a nonzero distance
786782 */
787− if (pipe_ctx->top_pipe && pipe_ctx->top_pipe->prev_odm_pipe && !pipe_ctx->prev_odm_pipe) {
788− /* MPO window on right side of ODM split */
789− data->recout.x = stream->dst.x + (surf_clip.x - stream->dst.width/2) *
790− stream->dst.width / stream->src.width;
791− } else if (!pipe_ctx->prev_odm_pipe || split_idx == split_count) {
783+ if (!pipe_ctx->prev_odm_pipe || split_idx == split_count) {
792784 data->recout.x = stream->dst.x;
793785 if (stream->src.x < surf_clip.x)
794786 data->recout.x += (surf_clip.x - stream->src.x) * stream->dst.width
@@ -986,8 +978,6 @@ static void calculate_inits_and_viewports(struct pipe_ctx *pipe_ctx) · 191 unmodified lines
986978 * stream->dst.height / stream->src.height;
987979 if (pipe_ctx->prev_odm_pipe && split_idx)
988980 ro_lb = data->h_active * split_idx - recout_full_x;
989− else if (pipe_ctx->top_pipe && pipe_ctx->top_pipe->prev_odm_pipe)
990− ro_lb = data->h_active * split_idx - recout_full_x + data->recout.x;
991981 else
992982 ro_lb = data->recout.x - recout_full_x;
993983 ro_tb = data->recout.y - recout_full_y;
@@ -1086,9 +1076,6 @@ bool resource_build_scaling_params(struct pipe_ctx *pipe_ctx) · 92 unmodified lines
10861076 timing->v_border_top + timing->v_border_bottom;
10871077 if (pipe_ctx->next_odm_pipe || pipe_ctx->prev_odm_pipe)
10881078 pipe_ctx->plane_res.scl_data.h_active /= get_num_odm_splits(pipe_ctx) + 1;
1089− /* ODM + windows MPO, where window is on either right or left ODM half */
1090− else if (pipe_ctx->top_pipe && (pipe_ctx->top_pipe->next_odm_pipe || pipe_ctx->top_pipe->prev_odm_pipe))
1091− pipe_ctx->plane_res.scl_data.h_active /= get_num_odm_splits(pipe_ctx->top_pipe) + 1;
10921079
10931080 /* depends on h_active */
10941081 calculate_recout(pipe_ctx);
@@ -1097,6 +1084,11 @@ bool resource_build_scaling_params(struct pipe_ctx *pipe_ctx) · 2 unmodified lines
10971084 /* depends on scaling ratios and recout, does not calculate offset yet */
10981085 calculate_viewport_size(pipe_ctx);
10991086
1087+ /* Stopgap for validation of ODM + MPO on one side of screen case */
1088+ if (pipe_ctx->plane_res.scl_data.viewport.height < 1 ||
1089+ pipe_ctx->plane_res.scl_data.viewport.width < 1)
1090+ return false;
1091+
11001092 /*
11011093 * LB calculations depend on vp size, h/v_active and scaling ratios
11021094 * Setting line buffer pixel depth to 24bpp yields banding
@@ -1445,54 +1437,23 @@ bool dc_add_plane_to_context( · 342 unmodified lines
14451437 if (head_pipe != free_pipe) {
14461438 tail_pipe = resource_get_tail_pipe(&context->res_ctx, head_pipe);
14471439 ASSERT(tail_pipe);
1448−
1449− /* ODM + window MPO, where MPO window is on right half only */
1450− if (free_pipe->plane_state &&
1451− (free_pipe->plane_state->clip_rect.x >= free_pipe->stream->src.width/2) &&
1452− tail_pipe->next_odm_pipe) {
1453− free_pipe->stream_res.tg = tail_pipe->next_odm_pipe->stream_res.tg;
1454− free_pipe->stream_res.abm = tail_pipe->next_odm_pipe->stream_res.abm;
1455− free_pipe->stream_res.opp = tail_pipe->next_odm_pipe->stream_res.opp;
1456− free_pipe->stream_res.stream_enc = tail_pipe->next_odm_pipe->stream_res.stream_enc;
1457− free_pipe->stream_res.audio = tail_pipe->next_odm_pipe->stream_res.audio;
1458− free_pipe->clock_source = tail_pipe->next_odm_pipe->clock_source;
1459−
1460− free_pipe->top_pipe = tail_pipe->next_odm_pipe;
1461− tail_pipe->next_odm_pipe->bottom_pipe = free_pipe;
1462− } else {
1463− free_pipe->stream_res.tg = tail_pipe->stream_res.tg;
1464− free_pipe->stream_res.abm = tail_pipe->stream_res.abm;
1465− free_pipe->stream_res.opp = tail_pipe->stream_res.opp;
1466− free_pipe->stream_res.stream_enc = tail_pipe->stream_res.stream_enc;
1467− free_pipe->stream_res.audio = tail_pipe->stream_res.audio;
1468− free_pipe->clock_source = tail_pipe->clock_source;
1469−
1470− free_pipe->top_pipe = tail_pipe;
1471− tail_pipe->bottom_pipe = free_pipe;
1472−
1473− if (!free_pipe->next_odm_pipe && tail_pipe->next_odm_pipe && tail_pipe->next_odm_pipe->bottom_pipe) {
1474− free_pipe->next_odm_pipe = tail_pipe->next_odm_pipe->bottom_pipe;
1475− tail_pipe->next_odm_pipe->bottom_pipe->prev_odm_pipe = free_pipe;
1476− }
1477− if (!free_pipe->prev_odm_pipe && tail_pipe->prev_odm_pipe && tail_pipe->prev_odm_pipe->bottom_pipe) {
1478− free_pipe->prev_odm_pipe = tail_pipe->prev_odm_pipe->bottom_pipe;
1479− tail_pipe->prev_odm_pipe->bottom_pipe->next_odm_pipe = free_pipe;
1480− }
1440+ free_pipe->stream_res.tg = tail_pipe->stream_res.tg;
1441+ free_pipe->stream_res.abm = tail_pipe->stream_res.abm;
1442+ free_pipe->stream_res.opp = tail_pipe->stream_res.opp;
1443+ free_pipe->stream_res.stream_enc = tail_pipe->stream_res.stream_enc;
1444+ free_pipe->stream_res.audio = tail_pipe->stream_res.audio;
1445+ free_pipe->clock_source = tail_pipe->clock_source;
1446+ free_pipe->top_pipe = tail_pipe;
1447+ tail_pipe->bottom_pipe = free_pipe;
1448+ if (!free_pipe->next_odm_pipe && tail_pipe->next_odm_pipe && tail_pipe->next_odm_pipe->bottom_pipe) {
1449+ free_pipe->next_odm_pipe = tail_pipe->next_odm_pipe->bottom_pipe;
1450+ tail_pipe->next_odm_pipe->bottom_pipe->prev_odm_pipe = free_pipe;
1451+ }
1452+ if (!free_pipe->prev_odm_pipe && tail_pipe->prev_odm_pipe && tail_pipe->prev_odm_pipe->bottom_pipe) {
1453+ free_pipe->prev_odm_pipe = tail_pipe->prev_odm_pipe->bottom_pipe;
1454+ tail_pipe->prev_odm_pipe->bottom_pipe->next_odm_pipe = free_pipe;
14811455 }
14821456 }
1483−
1484− /* ODM + window MPO, where MPO window is on left half only */
1485− if (free_pipe->plane_state &&
1486− (free_pipe->plane_state->clip_rect.x + free_pipe->plane_state->clip_rect.width <=
1487− free_pipe->stream->src.x + free_pipe->stream->src.width/2)) {
1488− break;
1489− }
1490− /* ODM + window MPO, where MPO window is on right half only */
1491− if (free_pipe->plane_state &&
1492− (free_pipe->plane_state->clip_rect.x >= free_pipe->stream->src.width/2)) {
1493− break;
1494− }
1495−
14961457 head_pipe = head_pipe->next_odm_pipe;
14971458 }
14981459 /* assign new surfaces*/
@@ -1763,6 +1724,94 @@ static void update_hpo_dp_stream_engine_usage( · 264 unmodified lines
17631724 res_ctx->is_hpo_dp_stream_enc_acquired[i] = acquired;
17641725 }
17651726 }
1727+
1728+static inline int find_acquired_hpo_dp_link_enc_for_link(
1729+ const struct resource_context *res_ctx,
1730+ const struct dc_link *link)
1731+{
1732+ int i;
1733+
1734+ for (i = 0; i < ARRAY_SIZE(res_ctx->hpo_dp_link_enc_to_link_idx); i++)
1735+ if (res_ctx->hpo_dp_link_enc_ref_cnts[i] > 0 &&
1736+ res_ctx->hpo_dp_link_enc_to_link_idx[i] == link->link_index)
1737+ return i;
1738+
1739+ return -1;
1740+}
1741+
1742+static inline int find_free_hpo_dp_link_enc(const struct resource_context *res_ctx,
1743+ const struct resource_pool *pool)
1744+{
1745+ int i;
1746+
1747+ for (i = 0; i < ARRAY_SIZE(res_ctx->hpo_dp_link_enc_ref_cnts); i++)
1748+ if (res_ctx->hpo_dp_link_enc_ref_cnts[i] == 0)
1749+ break;
1750+
1751+ return (i < ARRAY_SIZE(res_ctx->hpo_dp_link_enc_ref_cnts) &&
1752+ i < pool->hpo_dp_link_enc_count) ? i : -1;
1753+}
1754+
1755+static inline void acquire_hpo_dp_link_enc(
1756+ struct resource_context *res_ctx,
1757+ unsigned int link_index,
1758+ int enc_index)
1759+{
1760+ res_ctx->hpo_dp_link_enc_to_link_idx[enc_index] = link_index;
1761+ res_ctx->hpo_dp_link_enc_ref_cnts[enc_index] = 1;
1762+}
1763+
1764+static inline void retain_hpo_dp_link_enc(
1765+ struct resource_context *res_ctx,
1766+ int enc_index)
1767+{
1768+ res_ctx->hpo_dp_link_enc_ref_cnts[enc_index]++;
1769+}
1770+
1771+static inline void release_hpo_dp_link_enc(
1772+ struct resource_context *res_ctx,
1773+ int enc_index)
1774+{
1775+ ASSERT(res_ctx->hpo_dp_link_enc_ref_cnts[enc_index] > 0);
1776+ res_ctx->hpo_dp_link_enc_ref_cnts[enc_index]--;
1777+}
1778+
1779+static bool add_hpo_dp_link_enc_to_ctx(struct resource_context *res_ctx,
1780+ const struct resource_pool *pool,
1781+ struct pipe_ctx *pipe_ctx,
1782+ struct dc_stream_state *stream)
1783+{
1784+ int enc_index;
1785+
1786+ enc_index = find_acquired_hpo_dp_link_enc_for_link(res_ctx, stream->link);
1787+
1788+ if (enc_index >= 0) {
1789+ retain_hpo_dp_link_enc(res_ctx, enc_index);
1790+ } else {
1791+ enc_index = find_free_hpo_dp_link_enc(res_ctx, pool);
1792+ if (enc_index >= 0)
1793+ acquire_hpo_dp_link_enc(res_ctx, stream->link->link_index, enc_index);
1794+ }
1795+
1796+ if (enc_index >= 0)
1797+ pipe_ctx->link_res.hpo_dp_link_enc = pool->hpo_dp_link_enc[enc_index];
1798+
1799+ return pipe_ctx->link_res.hpo_dp_link_enc != NULL;
1800+}
1801+
1802+static void remove_hpo_dp_link_enc_from_ctx(struct resource_context *res_ctx,
1803+ struct pipe_ctx *pipe_ctx,
1804+ struct dc_stream_state *stream)
1805+{
1806+ int enc_index;
1807+
1808+ enc_index = find_acquired_hpo_dp_link_enc_for_link(res_ctx, stream->link);
1809+
1810+ if (enc_index >= 0) {
1811+ release_hpo_dp_link_enc(res_ctx, enc_index);
1812+ pipe_ctx->link_res.hpo_dp_link_enc = NULL;
1813+ }
1814+}
17661815 #endif
17671816
17681817 /* TODO: release audio object */
@@ -1925,6 +1974,7 @@ enum dc_status dc_remove_stream_from_ctx( · 156 unmodified lines
19251974 &new_ctx->res_ctx, dc->res_pool,
19261975 del_pipe->stream_res.hpo_dp_stream_enc,
19271976 false);
1977+ remove_hpo_dp_link_enc_from_ctx(&new_ctx->res_ctx, del_pipe, del_pipe->stream);
19281978 }
19291979 #endif
19301980
@@ -2200,6 +2250,8 @@ enum dc_status resource_map_pool_resources( · 269 unmodified lines
22002250 &context->res_ctx, pool,
22012251 pipe_ctx->stream_res.hpo_dp_stream_enc,
22022252 true);
2253+ if (!add_hpo_dp_link_enc_to_ctx(&context->res_ctx, pool, pipe_ctx, stream))
2254+ return DC_NO_LINK_ENC_RESOURCE;
22032255 }
22042256 }
22052257 #endif
@@ -2875,6 +2927,8 @@ bool pipe_need_reprogram( · 669 unmodified lines
28752927 #if defined(CONFIG_DRM_AMD_DC_DCN)
28762928 if (pipe_ctx_old->stream_res.hpo_dp_stream_enc != pipe_ctx->stream_res.hpo_dp_stream_enc)
28772929 return true;
2930+ if (pipe_ctx_old->link_res.hpo_dp_link_enc != pipe_ctx->link_res.hpo_dp_link_enc)
2931+ return true;
28782932 #endif
28792933
28802934 /* DIG link encoder resource assignment for stream changed. */
@@ -3143,22 +3197,23 @@ void get_audio_check(struct audio_info *aud_modes, · 262 unmodified lines
31433197 }
31443198
31453199 #if defined(CONFIG_DRM_AMD_DC_DCN)
3146−struct hpo_dp_link_encoder *resource_get_unused_hpo_dp_link_encoder(
3147− const struct resource_pool *pool)
3200+struct hpo_dp_link_encoder *resource_get_hpo_dp_link_enc_for_det_lt(
3201+ const struct resource_context *res_ctx,
3202+ const struct resource_pool *pool,
3203+ const struct dc_link *link)
31483204 {
3149− uint8_t i;
3150− struct hpo_dp_link_encoder *enc = NULL;
3205+ struct hpo_dp_link_encoder *hpo_dp_link_enc = NULL;
3206+ int enc_index;
31513207
3152− ASSERT(pool->hpo_dp_link_enc_count <= MAX_HPO_DP2_LINK_ENCODERS);
3208+ enc_index = find_acquired_hpo_dp_link_enc_for_link(res_ctx, link);
31533209
3154− for (i = 0; i < pool->hpo_dp_link_enc_count; i++) {
3155− if (pool->hpo_dp_link_enc[i]->transmitter == TRANSMITTER_UNKNOWN) {
3156− enc = pool->hpo_dp_link_enc[i];
3157− break;
3158− }
3159− }
3210+ if (enc_index < 0)
3211+ enc_index = find_free_hpo_dp_link_enc(res_ctx, pool);
3212+
3213+ if (enc_index >= 0)
3214+ hpo_dp_link_enc = pool->hpo_dp_link_enc[enc_index];
31603215
3161− return enc;
3216+ return hpo_dp_link_enc;
31623217 }
31633218 #endif
31643219
drivers/gpu/drm/amd/display/dc/dc.h+2−1
@@ -47,7 +47,7 @@ struct aux_payload; · 46 unmodified lines
4747 struct set_config_cmd_payload;
4848 struct dmub_notification;
4949
50−#define DC_VER "3.2.166"
50+#define DC_VER "3.2.167"
5151
5252 #define MAX_SURFACES 3
5353 #define MAX_PLANES 6
@@ -691,6 +691,7 @@ struct dc_debug_options { · 637 unmodified lines
691691 /* TODO - remove once tested */
692692 bool legacy_dp2_lt;
693693 bool set_mst_en_for_sst;
694+ bool disable_uhbr;
694695 bool force_dp2_lt_fallback_method;
695696 #endif
696697 union mem_low_power_enable_options enable_mem_low_power;
drivers/gpu/drm/amd/display/dc/dc_link.h+12−3
@@ -30,6 +30,8 @@ · 29 unmodified lines
3030 #include "dc_types.h"
3131 #include "grph_object_defs.h"
3232
33+struct link_resource;
34+
3335 enum dc_link_fec_state {
3436 dc_link_fec_not_ready,
3537 dc_link_fec_ready,
@@ -160,9 +162,6 @@ struct dc_link { · 124 unmodified lines
160162
161163 struct panel_cntl *panel_cntl;
162164 struct link_encoder *link_enc;
163−#if defined(CONFIG_DRM_AMD_DC_DCN)
164− struct hpo_dp_link_encoder *hpo_dp_link_enc;
165−#endif
166165 struct graphics_object_id link_id;
167166 /* Endpoint type distinguishes display endpoints which do not have entries
168167 * in the BIOS connector table from those that do. Helps when tracking link
@@ -359,14 +358,17 @@ void dc_link_remove_remote_sink( · 190 unmodified lines
359358
360359 void dc_link_dp_set_drive_settings(
361360 struct dc_link *link,
361+ const struct link_resource *link_res,
362362 struct link_training_settings *lt_settings);
363363
364364 bool dc_link_dp_perform_link_training_skip_aux(
365365 struct dc_link *link,
366+ const struct link_resource *link_res,
366367 const struct dc_link_settings *link_setting);
367368
368369 enum link_training_result dc_link_dp_perform_link_training(
369370 struct dc_link *link,
371+ const struct link_resource *link_res,
370372 const struct dc_link_settings *link_settings,
371373 bool skip_video_pattern);
372374
@@ -374,6 +376,7 @@ bool dc_link_dp_sync_lt_begin(struct dc_link *link); · 1 unmodified line
374376
375377 enum link_training_result dc_link_dp_sync_lt_attempt(
376378 struct dc_link *link,
379+ const struct link_resource *link_res,
377380 struct dc_link_settings *link_setting,
378381 struct dc_link_training_overrides *lt_settings);
379382
@@ -454,4 +457,10 @@ bool dc_link_should_enable_fec(const struct dc_link *link); · 74 unmodified lines
454457 uint32_t dc_link_bw_kbps_from_raw_frl_link_rate_data(uint8_t bw);
455458 enum dp_link_encoding dc_link_dp_mst_decide_link_encoding_format(const struct dc_link *link);
456459 #endif
460+
461+const struct link_resource *dc_link_get_cur_link_res(const struct dc_link *link);
462+/* take a snapshot of current link resource allocation state */
463+void dc_get_cur_link_res_map(const struct dc *dc, uint32_t *map);
464+/* restore link resource allocation state from a snapshot */
465+void dc_restore_link_res_map(const struct dc *dc, uint32_t *map);
457466 #endif /* DC_LINK_H_ */
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c+4−10
@@ -468,8 +468,6 @@ void dcn10_log_hw_state(struct dc *dc, · 467 unmodified lines
468468 log_mpc_crc(dc, log_ctx);
469469
470470 {
471− int hpo_dp_link_enc_count = 0;
472−
473471 if (pool->hpo_dp_stream_enc_count > 0) {
474472 DTN_INFO("DP HPO S_ENC: Enabled OTG Format Depth Vid SDP Compressed Link\n");
475473 for (i = 0; i < pool->hpo_dp_stream_enc_count; i++) {
@@ -500,18 +498,14 @@ void dcn10_log_hw_state(struct dc *dc, · 24 unmodified lines
500498 }
501499
502500 /* log DP HPO L_ENC section if any hpo_dp_link_enc exists */
503− for (i = 0; i < dc->link_count; i++)
504− if (dc->links[i]->hpo_dp_link_enc)
505− hpo_dp_link_enc_count++;
506−
507− if (hpo_dp_link_enc_count) {
501+ if (pool->hpo_dp_link_enc_count) {
508502 DTN_INFO("DP HPO L_ENC: Enabled Mode Lanes Stream Slots VC Rate X VC Rate Y\n");
509503
510− for (i = 0; i < dc->link_count; i++) {
511− struct hpo_dp_link_encoder *hpo_dp_link_enc = dc->links[i]->hpo_dp_link_enc;
504+ for (i = 0; i < pool->hpo_dp_link_enc_count; i++) {
505+ struct hpo_dp_link_encoder *hpo_dp_link_enc = pool->hpo_dp_link_enc[i];
512506 struct hpo_dp_link_enc_state hpo_dp_le_state = {0};
513507
514− if (hpo_dp_link_enc && hpo_dp_link_enc->funcs->read_state) {
508+ if (hpo_dp_link_enc->funcs->read_state) {
515509 hpo_dp_link_enc->funcs->read_state(hpo_dp_link_enc, &hpo_dp_le_state);
516510 DTN_INFO("[%d]: %d %6s %d %d %d %d %d\n",
517511 hpo_dp_link_enc->inst,
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_init.c+1−0
@@ -78,6 +78,7 @@ static const struct hw_sequencer_funcs dcn10_funcs = { · 77 unmodified lines
7878 .get_clock = dcn10_get_clock,
7979 .get_vupdate_offset_from_vsync = dcn10_get_vupdate_offset_from_vsync,
8080 .calc_vupdate_position = dcn10_calc_vupdate_position,
81+ .power_down = dce110_power_down,
8182 .set_backlight_level = dce110_set_backlight_level,
8283 .set_abm_immediate_disable = dce110_set_abm_immediate_disable,
8384 .set_pipe = dce110_set_pipe,
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c+1−1
@@ -2414,7 +2414,7 @@ void dcn20_enable_stream(struct pipe_ctx *pipe_ctx) · 2413 unmodified lines
24142414 pipe_ctx->stream_res.hpo_dp_stream_enc->funcs->map_stream_to_link(
24152415 pipe_ctx->stream_res.hpo_dp_stream_enc,
24162416 pipe_ctx->stream_res.hpo_dp_stream_enc->inst,
2417− link->hpo_dp_link_enc->inst);
2417+ pipe_ctx->link_res.hpo_dp_link_enc->inst);
24182418 }
24192419
24202420 if (!is_dp_128b_132b_signal(pipe_ctx) && link_enc)
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c+2−3
@@ -1069,7 +1069,7 @@ static const struct dc_debug_options debug_defaults_drv = { · 1068 unmodified lines
10691069 .timing_trace = false,
10701070 .clock_trace = true,
10711071 .disable_pplib_clock_request = true,
1072− .pipe_split_policy = MPC_SPLIT_AVOID_MULT_DISP,
1072+ .pipe_split_policy = MPC_SPLIT_DYNAMIC,
10731073 .force_single_disp_pipe_split = false,
10741074 .disable_dcc = DCC_ENABLE,
10751075 .vsr_support = true,
@@ -3093,8 +3093,7 @@ static enum dcn_zstate_support_state decide_zstate_support(struct dc *dc, struc · 2017 unmodified lines
30933093 else if (context->stream_count == 1 && context->streams[0]->signal == SIGNAL_TYPE_EDP) {
30943094 struct dc_link *link = context->streams[0]->sink->link;
30953095
3096− if ((link->link_index == 0 && link->psr_settings.psr_feature_enabled)
3097− || context->bw_ctx.dml.vba.StutterPeriod > 5000.0)
3096+ if (link->link_index == 0 && context->bw_ctx.dml.vba.StutterPeriod > 5000.0)
30983097 return DCN_ZSTATE_SUPPORT_ALLOW;
30993098 else
31003099 return DCN_ZSTATE_SUPPORT_DISALLOW;
drivers/gpu/drm/amd/display/dc/dcn201/dcn201_hwseq.c+2−1
@@ -134,11 +134,12 @@ void dcn201_update_plane_addr(const struct dc *dc, struct pipe_ctx *pipe_ctx) · 133 unmodified lines
134134 PHYSICAL_ADDRESS_LOC addr;
135135 struct dc_plane_state *plane_state = pipe_ctx->plane_state;
136136 struct dce_hwseq *hws = dc->hwseq;
137− struct dc_plane_address uma = plane_state->address;
137+ struct dc_plane_address uma;
138138
139139 if (plane_state == NULL)
140140 return;
141141
142+ uma = plane_state->address;
142143 addr_patched = patch_address_for_sbs_tb_stereo(pipe_ctx, &addr);
143144
144145 plane_address_in_gpu_space_to_uma(hws, &uma);
drivers/gpu/drm/amd/display/dc/dcn201/dcn201_resource.c+1−1
@@ -603,7 +603,7 @@ static const struct dc_debug_options debug_defaults_drv = { · 602 unmodified lines
603603 .timing_trace = false,
604604 .clock_trace = true,
605605 .disable_pplib_clock_request = true,
606− .pipe_split_policy = MPC_SPLIT_AVOID,
606+ .pipe_split_policy = MPC_SPLIT_DYNAMIC,
607607 .force_single_disp_pipe_split = false,
608608 .disable_dcc = DCC_ENABLE,
609609 .vsr_support = true,
drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c+1−1
@@ -873,7 +873,7 @@ static const struct dc_debug_options debug_defaults_drv = { · 872 unmodified lines
873873 .clock_trace = true,
874874 .disable_pplib_clock_request = true,
875875 .min_disp_clk_khz = 100000,
876− .pipe_split_policy = MPC_SPLIT_AVOID_MULT_DISP,
876+ .pipe_split_policy = MPC_SPLIT_DYNAMIC,
877877 .force_single_disp_pipe_split = false,
878878 .disable_dcc = DCC_ENABLE,
879879 .vsr_support = true,
drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.c+1−12
@@ -840,7 +840,7 @@ static const struct dc_debug_options debug_defaults_drv = { · 839 unmodified lines
840840 .timing_trace = false,
841841 .clock_trace = true,
842842 .disable_pplib_clock_request = true,
843− .pipe_split_policy = MPC_SPLIT_AVOID_MULT_DISP,
843+ .pipe_split_policy = MPC_SPLIT_DYNAMIC,
844844 .force_single_disp_pipe_split = false,
845845 .disable_dcc = DCC_ENABLE,
846846 .vsr_support = true,
@@ -1761,17 +1761,6 @@ static bool dcn30_split_stream_for_mpc_or_odm( · 914 unmodified lines
17611761 int pipe_idx = sec_pipe->pipe_idx;
17621762 const struct resource_pool *pool = dc->res_pool;
17631763
1764− if (pri_pipe->plane_state) {
1765− /* ODM + window MPO, where MPO window is on left half only */
1766− if (pri_pipe->plane_state->clip_rect.x + pri_pipe->plane_state->clip_rect.width <=
1767− pri_pipe->stream->src.x + pri_pipe->stream->src.width/2)
1768− return true;
1769−
1770− /* ODM + window MPO, where MPO window is on right half only */
1771− if (pri_pipe->plane_state->clip_rect.x >= pri_pipe->stream->src.width/2)
1772− return true;
1773− }
1774−
17751764 *sec_pipe = *pri_pipe;
17761765
17771766 sec_pipe->pipe_idx = pipe_idx;
drivers/gpu/drm/amd/display/dc/dcn301/dcn301_resource.c+1−1
@@ -686,7 +686,7 @@ static const struct dc_debug_options debug_defaults_drv = { · 685 unmodified lines
686686 .disable_clock_gate = true,
687687 .disable_pplib_clock_request = true,
688688 .disable_pplib_wm_range = true,
689− .pipe_split_policy = MPC_SPLIT_AVOID,
689+ .pipe_split_policy = MPC_SPLIT_DYNAMIC,
690690 .force_single_disp_pipe_split = false,
691691 .disable_dcc = DCC_ENABLE,
692692 .vsr_support = true,
drivers/gpu/drm/amd/display/dc/dcn302/dcn302_resource.c+1−1
@@ -211,7 +211,7 @@ static const struct dc_debug_options debug_defaults_drv = { · 210 unmodified lines
211211 .timing_trace = false,
212212 .clock_trace = true,
213213 .disable_pplib_clock_request = true,
214− .pipe_split_policy = MPC_SPLIT_AVOID_MULT_DISP,
214+ .pipe_split_policy = MPC_SPLIT_DYNAMIC,
215215 .force_single_disp_pipe_split = false,
216216 .disable_dcc = DCC_ENABLE,
217217 .vsr_support = true,
drivers/gpu/drm/amd/display/dc/dcn303/dcn303_dccg.h+18−2
@@ -15,7 +15,11 @@ · 14 unmodified lines
1515 SR(DPPCLK_DTO_CTRL),\
1616 DCCG_SRII(DTO_PARAM, DPPCLK, 0),\
1717 DCCG_SRII(DTO_PARAM, DPPCLK, 1),\
18− SR(REFCLK_CNTL)
18+ SR(REFCLK_CNTL),\
19+ SR(DISPCLK_FREQ_CHANGE_CNTL),\
20+ DCCG_SRII(PIXEL_RATE_CNTL, OTG, 0),\
21+ DCCG_SRII(PIXEL_RATE_CNTL, OTG, 1)
22+
1923
2024 #define DCCG_MASK_SH_LIST_DCN3_03(mask_sh) \
2125 DCCG_SFI(DPPCLK_DTO_CTRL, DTO_ENABLE, DPPCLK, 0, mask_sh),\
@@ -25,6 +29,18 @@ · 3 unmodified lines
2529 DCCG_SF(DPPCLK0_DTO_PARAM, DPPCLK0_DTO_PHASE, mask_sh),\
2630 DCCG_SF(DPPCLK0_DTO_PARAM, DPPCLK0_DTO_MODULO, mask_sh),\
2731 DCCG_SF(REFCLK_CNTL, REFCLK_CLOCK_EN, mask_sh),\
28− DCCG_SF(REFCLK_CNTL, REFCLK_SRC_SEL, mask_sh)
32+ DCCG_SF(REFCLK_CNTL, REFCLK_SRC_SEL, mask_sh),\
33+ DCCG_SF(DISPCLK_FREQ_CHANGE_CNTL, DISPCLK_STEP_DELAY, mask_sh),\
34+ DCCG_SF(DISPCLK_FREQ_CHANGE_CNTL, DISPCLK_STEP_SIZE, mask_sh),\
35+ DCCG_SF(DISPCLK_FREQ_CHANGE_CNTL, DISPCLK_FREQ_RAMP_DONE, mask_sh),\
36+ DCCG_SF(DISPCLK_FREQ_CHANGE_CNTL, DISPCLK_MAX_ERRDET_CYCLES, mask_sh),\
37+ DCCG_SF(DISPCLK_FREQ_CHANGE_CNTL, DCCG_FIFO_ERRDET_RESET, mask_sh),\
38+ DCCG_SF(DISPCLK_FREQ_CHANGE_CNTL, DCCG_FIFO_ERRDET_STATE, mask_sh),\
39+ DCCG_SF(DISPCLK_FREQ_CHANGE_CNTL, DCCG_FIFO_ERRDET_OVR_EN, mask_sh),\
40+ DCCG_SF(DISPCLK_FREQ_CHANGE_CNTL, DISPCLK_CHG_FWD_CORR_DISABLE, mask_sh),\
41+ DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, ADD_PIXEL, 0, mask_sh),\
42+ DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, ADD_PIXEL, 1, mask_sh),\
43+ DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, DROP_PIXEL, 0, mask_sh),\
44+ DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, DROP_PIXEL, 1, mask_sh)
2945
3046 #endif //__DCN303_DCCG_H__
drivers/gpu/drm/amd/display/dc/dcn303/dcn303_resource.c+1−1
@@ -193,7 +193,7 @@ static const struct dc_debug_options debug_defaults_drv = { · 192 unmodified lines
193193 .timing_trace = false,
194194 .clock_trace = true,
195195 .disable_pplib_clock_request = true,
196− .pipe_split_policy = MPC_SPLIT_AVOID_MULT_DISP,
196+ .pipe_split_policy = MPC_SPLIT_DYNAMIC,
197197 .force_single_disp_pipe_split = false,
198198 .disable_dcc = DCC_ENABLE,
199199 .vsr_support = true,
drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hpo_dp_link_encoder.c+5−1
@@ -499,7 +499,8 @@ static enum bp_result link_transmitter_control( · 498 unmodified lines
499499 void dcn31_hpo_dp_link_enc_enable_dp_output(
500500 struct hpo_dp_link_encoder *enc,
501501 const struct dc_link_settings *link_settings,
502− enum transmitter transmitter)
502+ enum transmitter transmitter,
503+ enum hpd_source_id hpd_source)
503504 {
504505 struct dcn31_hpo_dp_link_encoder *enc3 = DCN3_1_HPO_DP_LINK_ENC_FROM_HPO_LINK_ENC(enc);
505506 struct bp_transmitter_control cntl = { 0 };
@@ -508,6 +509,9 @@ void dcn31_hpo_dp_link_enc_enable_dp_output( · 2 unmodified lines
508509 /* Set the transmitter */
509510 enc3->base.transmitter = transmitter;
510511
512+ /* Set the hpd source */
513+ enc3->base.hpd_source = hpd_source;
514+
511515 /* Enable the PHY */
512516 cntl.action = TRANSMITTER_CONTROL_ENABLE;
513517 cntl.engine_id = ENGINE_ID_UNKNOWN;
drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hpo_dp_link_encoder.h+2−1
@@ -184,7 +184,8 @@ void hpo_dp_link_encoder31_construct(struct dcn31_hpo_dp_link_encoder *enc31, · 183 unmodified lines
184184 void dcn31_hpo_dp_link_enc_enable_dp_output(
185185 struct hpo_dp_link_encoder *enc,
186186 const struct dc_link_settings *link_settings,
187− enum transmitter transmitter);
187+ enum transmitter transmitter,
188+ enum hpd_source_id hpd_source);
188189
189190 void dcn31_hpo_dp_link_enc_disable_output(
190191 struct hpo_dp_link_encoder *enc,
drivers/gpu/drm/amd/display/dc/dcn31/dcn31_init.c+1−0
@@ -103,6 +103,7 @@ static const struct hw_sequencer_funcs dcn31_funcs = { · 102 unmodified lines
103103 .z10_restore = dcn31_z10_restore,
104104 .z10_save_init = dcn31_z10_save_init,
105105 .set_disp_pattern_generator = dcn30_set_disp_pattern_generator,
106+ .optimize_pwr_state = dcn21_optimize_pwr_state,
106107 .exit_optimized_pwr_state = dcn21_exit_optimized_pwr_state,
107108 .update_visual_confirm_color = dcn20_update_visual_confirm_color,
108109 };
drivers/gpu/drm/amd/display/dc/dcn31/dcn31_resource.c+24−3
@@ -355,6 +355,14 @@ static const struct dce110_clk_src_regs clk_src_regs[] = { · 354 unmodified lines
355355 clk_src_regs(3, D),
356356 clk_src_regs(4, E)
357357 };
358+/*pll_id being rempped in dmub, in driver it is logical instance*/
359+static const struct dce110_clk_src_regs clk_src_regs_b0[] = {
360+ clk_src_regs(0, A),
361+ clk_src_regs(1, B),
362+ clk_src_regs(2, F),
363+ clk_src_regs(3, G),
364+ clk_src_regs(4, E)
365+};
358366
359367 static const struct dce110_clk_src_shift cs_shift = {
360368 CS_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT)
@@ -995,7 +1003,7 @@ static const struct dc_debug_options debug_defaults_drv = { · 634 unmodified lines
9951003 .timing_trace = false,
9961004 .clock_trace = true,
9971005 .disable_pplib_clock_request = false,
998− .pipe_split_policy = MPC_SPLIT_AVOID,
1006+ .pipe_split_policy = MPC_SPLIT_DYNAMIC,
9991007 .force_single_disp_pipe_split = false,
10001008 .disable_dcc = DCC_ENABLE,
10011009 .vsr_support = true,
@@ -2294,14 +2302,27 @@ static bool dcn31_resource_construct( · 1292 unmodified lines
22942302 dcn30_clock_source_create(ctx, ctx->dc_bios,
22952303 CLOCK_SOURCE_COMBO_PHY_PLL1,
22962304 &clk_src_regs[1], false);
2297− pool->base.clock_sources[DCN31_CLK_SRC_PLL2] =
2305+ /*move phypllx_pixclk_resync to dmub next*/
2306+ if (dc->ctx->asic_id.hw_internal_rev == YELLOW_CARP_B0) {
2307+ pool->base.clock_sources[DCN31_CLK_SRC_PLL2] =
2308+ dcn30_clock_source_create(ctx, ctx->dc_bios,
2309+ CLOCK_SOURCE_COMBO_PHY_PLL2,
2310+ &clk_src_regs_b0[2], false);
2311+ pool->base.clock_sources[DCN31_CLK_SRC_PLL3] =
2312+ dcn30_clock_source_create(ctx, ctx->dc_bios,
2313+ CLOCK_SOURCE_COMBO_PHY_PLL3,
2314+ &clk_src_regs_b0[3], false);
2315+ } else {
2316+ pool->base.clock_sources[DCN31_CLK_SRC_PLL2] =
22982317 dcn30_clock_source_create(ctx, ctx->dc_bios,
22992318 CLOCK_SOURCE_COMBO_PHY_PLL2,
23002319 &clk_src_regs[2], false);
2301− pool->base.clock_sources[DCN31_CLK_SRC_PLL3] =
2320+ pool->base.clock_sources[DCN31_CLK_SRC_PLL3] =
23022321 dcn30_clock_source_create(ctx, ctx->dc_bios,
23032322 CLOCK_SOURCE_COMBO_PHY_PLL3,
23042323 &clk_src_regs[3], false);
2324+ }
2325+
23052326 pool->base.clock_sources[DCN31_CLK_SRC_PLL4] =
23062327 dcn30_clock_source_create(ctx, ctx->dc_bios,
23072328 CLOCK_SOURCE_COMBO_PHY_PLL4,
drivers/gpu/drm/amd/display/dc/dcn31/dcn31_resource.h+31−0
@@ -49,4 +49,35 @@ struct resource_pool *dcn31_create_resource_pool( · 48 unmodified lines
4949 const struct dc_init_data *init_data,
5050 struct dc *dc);
5151
52+/*temp: B0 specific before switch to dcn313 headers*/
53+#ifndef regPHYPLLF_PIXCLK_RESYNC_CNTL
54+#define regPHYPLLF_PIXCLK_RESYNC_CNTL 0x007e
55+#define regPHYPLLF_PIXCLK_RESYNC_CNTL_BASE_IDX 1
56+#define regPHYPLLG_PIXCLK_RESYNC_CNTL 0x005f
57+#define regPHYPLLG_PIXCLK_RESYNC_CNTL_BASE_IDX 1
58+
59+//PHYPLLF_PIXCLK_RESYNC_CNTL
60+#define PHYPLLF_PIXCLK_RESYNC_CNTL__PHYPLLF_PIXCLK_RESYNC_ENABLE__SHIFT 0x0
61+#define PHYPLLF_PIXCLK_RESYNC_CNTL__PHYPLLF_DEEP_COLOR_DTO_ENABLE_STATUS__SHIFT 0x1
62+#define PHYPLLF_PIXCLK_RESYNC_CNTL__PHYPLLF_DCCG_DEEP_COLOR_CNTL__SHIFT 0x4
63+#define PHYPLLF_PIXCLK_RESYNC_CNTL__PHYPLLF_PIXCLK_ENABLE__SHIFT 0x8
64+#define PHYPLLF_PIXCLK_RESYNC_CNTL__PHYPLLF_PIXCLK_DOUBLE_RATE_ENABLE__SHIFT 0x9
65+#define PHYPLLF_PIXCLK_RESYNC_CNTL__PHYPLLF_PIXCLK_RESYNC_ENABLE_MASK 0x00000001L
66+#define PHYPLLF_PIXCLK_RESYNC_CNTL__PHYPLLF_DEEP_COLOR_DTO_ENABLE_STATUS_MASK 0x00000002L
67+#define PHYPLLF_PIXCLK_RESYNC_CNTL__PHYPLLF_DCCG_DEEP_COLOR_CNTL_MASK 0x00000030L
68+#define PHYPLLF_PIXCLK_RESYNC_CNTL__PHYPLLF_PIXCLK_ENABLE_MASK 0x00000100L
69+#define PHYPLLF_PIXCLK_RESYNC_CNTL__PHYPLLF_PIXCLK_DOUBLE_RATE_ENABLE_MASK 0x00000200L
70+
71+//PHYPLLG_PIXCLK_RESYNC_CNTL
72+#define PHYPLLG_PIXCLK_RESYNC_CNTL__PHYPLLG_PIXCLK_RESYNC_ENABLE__SHIFT 0x0
73+#define PHYPLLG_PIXCLK_RESYNC_CNTL__PHYPLLG_DEEP_COLOR_DTO_ENABLE_STATUS__SHIFT 0x1
74+#define PHYPLLG_PIXCLK_RESYNC_CNTL__PHYPLLG_DCCG_DEEP_COLOR_CNTL__SHIFT 0x4
75+#define PHYPLLG_PIXCLK_RESYNC_CNTL__PHYPLLG_PIXCLK_ENABLE__SHIFT 0x8
76+#define PHYPLLG_PIXCLK_RESYNC_CNTL__PHYPLLG_PIXCLK_DOUBLE_RATE_ENABLE__SHIFT 0x9
77+#define PHYPLLG_PIXCLK_RESYNC_CNTL__PHYPLLG_PIXCLK_RESYNC_ENABLE_MASK 0x00000001L
78+#define PHYPLLG_PIXCLK_RESYNC_CNTL__PHYPLLG_DEEP_COLOR_DTO_ENABLE_STATUS_MASK 0x00000002L
79+#define PHYPLLG_PIXCLK_RESYNC_CNTL__PHYPLLG_DCCG_DEEP_COLOR_CNTL_MASK 0x00000030L
80+#define PHYPLLG_PIXCLK_RESYNC_CNTL__PHYPLLG_PIXCLK_ENABLE_MASK 0x00000100L
81+#define PHYPLLG_PIXCLK_RESYNC_CNTL__PHYPLLG_PIXCLK_DOUBLE_RATE_ENABLE_MASK 0x00000200L
82+#endif
5283 #endif /* _DCN31_RESOURCE_H_ */
drivers/gpu/drm/amd/display/dc/dml/dml_wrapper.c+1−1
@@ -1274,7 +1274,7 @@ static void dcn20_adjust_adaptive_sync_v_startup( · 1273 unmodified lines
12741274 static bool is_dp_128b_132b_signal(struct pipe_ctx *pipe_ctx)
12751275 {
12761276 return (pipe_ctx->stream_res.hpo_dp_stream_enc &&
1277− pipe_ctx->stream->link->hpo_dp_link_enc &&
1277+ pipe_ctx->link_res.hpo_dp_link_enc &&
12781278 dc_is_dp_signal(pipe_ctx->stream->signal));
12791279 }
12801280
drivers/gpu/drm/amd/display/dc/inc/core_status.h+2−0
@@ -53,6 +53,8 @@ enum dc_status { · 52 unmodified lines
5353 DC_NOT_SUPPORTED = 24,
5454 DC_UNSUPPORTED_VALUE = 25,
5555
56+ DC_NO_LINK_ENC_RESOURCE = 26,
57+
5658 DC_ERROR_UNEXPECTED = -1
5759 };
5860
drivers/gpu/drm/amd/display/dc/inc/core_types.h+17−0
@@ -334,6 +334,20 @@ struct plane_resource { · 333 unmodified lines
334334 struct dcn_fe_bandwidth bw;
335335 };
336336
337+#if defined(CONFIG_DRM_AMD_DC_DCN)
338+#define LINK_RES_HPO_DP_REC_MAP__MASK 0xFFFF
339+#define LINK_RES_HPO_DP_REC_MAP__SHIFT 0
340+#endif
341+
342+/* all mappable hardware resources used to enable a link */
343+struct link_resource {
344+#if defined(CONFIG_DRM_AMD_DC_DCN)
345+ struct hpo_dp_link_encoder *hpo_dp_link_enc;
346+#else
347+ void *dummy;
348+#endif
349+};
350+
337351 union pipe_update_flags {
338352 struct {
339353 uint32_t enable : 1;
@@ -361,6 +375,7 @@ struct pipe_ctx { · 21 unmodified lines
361375
362376 struct plane_resource plane_res;
363377 struct stream_resource stream_res;
378+ struct link_resource link_res;
364379
365380 struct clock_source *clock_source;
366381
@@ -412,6 +427,8 @@ struct resource_context { · 45 unmodified lines
412427 struct link_enc_cfg_context link_enc_cfg_ctx;
413428 #if defined(CONFIG_DRM_AMD_DC_DCN)
414429 bool is_hpo_dp_stream_enc_acquired[MAX_HPO_DP2_ENCODERS];
430+ unsigned int hpo_dp_link_enc_to_link_idx[MAX_HPO_DP2_LINK_ENCODERS];
431+ int hpo_dp_link_enc_ref_cnts[MAX_HPO_DP2_LINK_ENCODERS];
415432 #endif
416433 #if defined(CONFIG_DRM_AMD_DC_DCN)
417434 bool is_mpc_3dlut_acquired[MAX_PIPES];
drivers/gpu/drm/amd/display/dc/inc/dc_link_dp.h+11−4
@@ -56,16 +56,19 @@ enum { · 55 unmodified lines
5656
5757 bool dp_verify_link_cap(
5858 struct dc_link *link,
59+ const struct link_resource *link_res,
5960 struct dc_link_settings *known_limit_link_setting,
6061 int *fail_count);
6162
6263 bool dp_verify_link_cap_with_retries(
6364 struct dc_link *link,
65+ const struct link_resource *link_res,
6466 struct dc_link_settings *known_limit_link_setting,
6567 int attempts);
6668
6769 bool dp_verify_mst_link_cap(
68− struct dc_link *link);
70+ struct dc_link *link,
71+ const struct link_resource *link_res);
6972
7073 bool dp_validate_mode_timing(
7174 struct dc_link *link,
@@ -168,7 +171,7 @@ uint8_t dc_dp_initialize_scrambling_data_symbols( · 96 unmodified lines
168171 struct dc_link *link,
169172 enum dc_dp_training_pattern pattern);
170173
171−enum dc_status dp_set_fec_ready(struct dc_link *link, bool ready);
174+enum dc_status dp_set_fec_ready(struct dc_link *link, const struct link_resource *link_res, bool ready);
172175 void dp_set_fec_enable(struct dc_link *link, bool enable);
173176 struct link_encoder *dp_get_link_enc(struct dc_link *link);
174177 bool dp_set_dsc_enable(struct pipe_ctx *pipe_ctx, bool enable);
@@ -211,8 +214,12 @@ bool dpcd_poll_for_allocation_change_trigger(struct dc_link *link); · 36 unmodified lines
211214 struct fixed31_32 calculate_sst_avg_time_slots_per_mtp(
212215 const struct dc_stream_state *stream,
213216 const struct dc_link *link);
214−void enable_dp_hpo_output(struct dc_link *link, const struct dc_link_settings *link_settings);
215−void disable_dp_hpo_output(struct dc_link *link, enum signal_type signal);
217+void enable_dp_hpo_output(struct dc_link *link,
218+ const struct link_resource *link_res,
219+ const struct dc_link_settings *link_settings);
220+void disable_dp_hpo_output(struct dc_link *link,
221+ const struct link_resource *link_res,
222+ enum signal_type signal);
216223 void setup_dp_hpo_stream(struct pipe_ctx *pipe_ctx, bool enable);
217224 bool is_dp_128b_132b_signal(struct pipe_ctx *pipe_ctx);
218225 void reset_dp_hpo_stream_encoders_for_link(struct dc_link *link);
drivers/gpu/drm/amd/display/dc/inc/dc_link_dpia.h+3−2
@@ -91,8 +91,9 @@ enum dc_status dpcd_get_tunneling_device_data(struct dc_link *link); · 90 unmodified lines
9191 * DPIA equivalent of dc_link_dp_perfrorm_link_training.
9292 * Aborts link training upon detection of sink unplug.
9393 */
94−enum link_training_result
95−dc_link_dpia_perform_link_training(struct dc_link *link,
94+enum link_training_result dc_link_dpia_perform_link_training(
95+ struct dc_link *link,
96+ const struct link_resource *link_res,
9697 const struct dc_link_settings *link_setting,
9798 bool skip_video_pattern);
9899
drivers/gpu/drm/amd/display/dc/inc/hw/link_encoder.h+2−1
@@ -268,7 +268,8 @@ struct hpo_dp_link_encoder_funcs { · 267 unmodified lines
268268
269269 void (*enable_link_phy)(struct hpo_dp_link_encoder *enc,
270270 const struct dc_link_settings *link_settings,
271− enum transmitter transmitter);
271+ enum transmitter transmitter,
272+ enum hpd_source_id hpd_source);
272273
273274 void (*disable_link_phy)(struct hpo_dp_link_encoder *link_enc,
274275 enum signal_type signal);
drivers/gpu/drm/amd/display/dc/inc/link_hwss.h+8−2
@@ -32,6 +32,7 @@ struct gpio *get_hpd_gpio(struct dc_bios *dcb, · 31 unmodified lines
3232
3333 void dp_enable_link_phy(
3434 struct dc_link *link,
35+ const struct link_resource *link_res,
3536 enum signal_type signal,
3637 enum clock_source_id clock_source,
3738 const struct dc_link_settings *link_settings);
@@ -42,22 +43,27 @@ void edp_add_delay_for_T9(struct dc_link *link); · 4 unmodified lines
4243 bool edp_receiver_ready_T9(struct dc_link *link);
4344 bool edp_receiver_ready_T7(struct dc_link *link);
4445
45−void dp_disable_link_phy(struct dc_link *link, enum signal_type signal);
46+void dp_disable_link_phy(struct dc_link *link, const struct link_resource *link_res,
47+ enum signal_type signal);
4648
47−void dp_disable_link_phy_mst(struct dc_link *link, enum signal_type signal);
49+void dp_disable_link_phy_mst(struct dc_link *link, const struct link_resource *link_res,
50+ enum signal_type signal);
4851
4952 bool dp_set_hw_training_pattern(
5053 struct dc_link *link,
54+ const struct link_resource *link_res,
5155 enum dc_dp_training_pattern pattern,
5256 uint32_t offset);
5357
5458 void dp_set_hw_lane_settings(
5559 struct dc_link *link,
60+ const struct link_resource *link_res,
5661 const struct link_training_settings *link_settings,
5762 uint32_t offset);
5863
5964 void dp_set_hw_test_pattern(
6065 struct dc_link *link,
66+ const struct link_resource *link_res,
6167 enum dp_test_pattern test_pattern,
6268 uint8_t *custom_pattern,
6369 uint32_t custom_pattern_size);
drivers/gpu/drm/amd/display/dc/inc/resource.h+4−2
@@ -206,8 +206,10 @@ int get_num_mpc_splits(struct pipe_ctx *pipe); · 205 unmodified lines
206206 int get_num_odm_splits(struct pipe_ctx *pipe);
207207
208208 #if defined(CONFIG_DRM_AMD_DC_DCN)
209−struct hpo_dp_link_encoder *resource_get_unused_hpo_dp_link_encoder(
210− const struct resource_pool *pool);
209+struct hpo_dp_link_encoder *resource_get_hpo_dp_link_enc_for_det_lt(
210+ const struct resource_context *res_ctx,
211+ const struct resource_pool *pool,
212+ const struct dc_link *link);
211213 #endif
212214
213215 void reset_syncd_pipes_from_disabled_pipes(struct dc *dc,
drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h+2−2
@@ -46,10 +46,10 @@ · 45 unmodified lines
4646
4747 /* Firmware versioning. */
4848 #ifdef DMUB_EXPOSE_VERSION
49−#define DMUB_FW_VERSION_GIT_HASH 0xc99a4517
49+#define DMUB_FW_VERSION_GIT_HASH 0xbaf06b95
5050 #define DMUB_FW_VERSION_MAJOR 0
5151 #define DMUB_FW_VERSION_MINOR 0
52−#define DMUB_FW_VERSION_REVISION 97
52+#define DMUB_FW_VERSION_REVISION 98
5353 #define DMUB_FW_VERSION_TEST 0
5454 #define DMUB_FW_VERSION_VBIOS 0
5555 #define DMUB_FW_VERSION_HOTFIX 0
drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c+2−2
@@ -852,7 +852,7 @@ bool dmub_srv_should_detect(struct dmub_srv *dmub) · 851 unmodified lines
852852
853853 enum dmub_status dmub_srv_clear_inbox0_ack(struct dmub_srv *dmub)
854854 {
855− if (!dmub->hw_init || dmub->hw_funcs.clear_inbox0_ack_register)
855+ if (!dmub->hw_init || !dmub->hw_funcs.clear_inbox0_ack_register)
856856 return DMUB_STATUS_INVALID;
857857
858858 dmub->hw_funcs.clear_inbox0_ack_register(dmub);
@@ -878,7 +878,7 @@ enum dmub_status dmub_srv_wait_for_inbox0_ack(struct dmub_srv *dmub, uint32_t ti · 19 unmodified lines
878878 enum dmub_status dmub_srv_send_inbox0_cmd(struct dmub_srv *dmub,
879879 union dmub_inbox0_data_register data)
880880 {
881− if (!dmub->hw_init || dmub->hw_funcs.send_inbox0_cmd)
881+ if (!dmub->hw_init || !dmub->hw_funcs.send_inbox0_cmd)
882882 return DMUB_STATUS_INVALID;
883883
884884 dmub->hw_funcs.send_inbox0_cmd(dmub, data);
drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_7_2_0_offset.h+0−2
@@ -20753,8 +20753,6 @@ · 20752 unmodified lines
2075320753
2075420754 // addressBlock: nbio_nbif0_gdc_GDCDEC
2075520755 // base address: 0xd0000000
20756−#define regGDC1_LOGAN_FAST_WRITE_RESPONSE_CNTL 0x2ffc0eda
20757−#define regGDC1_LOGAN_FAST_WRITE_RESPONSE_CNTL_BASE_IDX 5
2075820756 #define regGDC1_NGDC_SDP_PORT_CTRL 0x2ffc0ee2
2075920757 #define regGDC1_NGDC_SDP_PORT_CTRL_BASE_IDX 5
2076020758 #define regGDC1_SHUB_REGS_IF_CTL 0x2ffc0ee3
drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_7_2_0_sh_mask.h+0−12
@@ -1,4 +1,3 @@
1−
21 /*
32 * Copyright (C) 2020 Advanced Micro Devices, Inc.
43 *
@@ -108541,17 +108540,6 @@ · 108536 unmodified lines
108541108540
108542108541
108543108542 // addressBlock: nbio_nbif0_gdc_GDCDEC
108544−//GDC1_LOGAN_FAST_WRITE_RESPONSE_CNTL
108545−#define GDC1_LOGAN_FAST_WRITE_RESPONSE_CNTL__LOGAN0_FAST_WRITE_RESPONSE_EN__SHIFT 0x0
108546−#define GDC1_LOGAN_FAST_WRITE_RESPONSE_CNTL__LOGAN1_FAST_WRITE_RESPONSE_EN__SHIFT 0x1
108547−#define GDC1_LOGAN_FAST_WRITE_RESPONSE_CNTL__LOGAN2_FAST_WRITE_RESPONSE_EN__SHIFT 0x2
108548−#define GDC1_LOGAN_FAST_WRITE_RESPONSE_CNTL__LOGAN3_FAST_WRITE_RESPONSE_EN__SHIFT 0x3
108549−#define GDC1_LOGAN_FAST_WRITE_RESPONSE_CNTL__FWR_NORMAL_ARB_MODE__SHIFT 0x10
108550−#define GDC1_LOGAN_FAST_WRITE_RESPONSE_CNTL__LOGAN0_FAST_WRITE_RESPONSE_EN_MASK 0x00000001L
108551−#define GDC1_LOGAN_FAST_WRITE_RESPONSE_CNTL__LOGAN1_FAST_WRITE_RESPONSE_EN_MASK 0x00000002L
108552−#define GDC1_LOGAN_FAST_WRITE_RESPONSE_CNTL__LOGAN2_FAST_WRITE_RESPONSE_EN_MASK 0x00000004L
108553−#define GDC1_LOGAN_FAST_WRITE_RESPONSE_CNTL__LOGAN3_FAST_WRITE_RESPONSE_EN_MASK 0x00000008L
108554−#define GDC1_LOGAN_FAST_WRITE_RESPONSE_CNTL__FWR_NORMAL_ARB_MODE_MASK 0x00010000L
108555108543 //GDC1_NGDC_SDP_PORT_CTRL
108556108544 #define GDC1_NGDC_SDP_PORT_CTRL__SDP_DISCON_HYSTERESIS__SHIFT 0x0
108557108545 #define GDC1_NGDC_SDP_PORT_CTRL__NGDC_OBFF_HW_URGENT_EARLY_WAKEUP_EN__SHIFT 0xf
drivers/gpu/drm/amd/include/discovery.h+49−0
@@ -143,6 +143,55 @@ struct gc_info_v1_0 { · 142 unmodified lines
143143 uint32_t gc_num_gl2a;
144144 };
145145
146+struct gc_info_v1_1 {
147+ struct gpu_info_header header;
148+
149+ uint32_t gc_num_se;
150+ uint32_t gc_num_wgp0_per_sa;
151+ uint32_t gc_num_wgp1_per_sa;
152+ uint32_t gc_num_rb_per_se;
153+ uint32_t gc_num_gl2c;
154+ uint32_t gc_num_gprs;
155+ uint32_t gc_num_max_gs_thds;
156+ uint32_t gc_gs_table_depth;
157+ uint32_t gc_gsprim_buff_depth;
158+ uint32_t gc_parameter_cache_depth;
159+ uint32_t gc_double_offchip_lds_buffer;
160+ uint32_t gc_wave_size;
161+ uint32_t gc_max_waves_per_simd;
162+ uint32_t gc_max_scratch_slots_per_cu;
163+ uint32_t gc_lds_size;
164+ uint32_t gc_num_sc_per_se;
165+ uint32_t gc_num_sa_per_se;
166+ uint32_t gc_num_packer_per_sc;
167+ uint32_t gc_num_gl2a;
168+ uint32_t gc_num_tcp_per_sa;
169+ uint32_t gc_num_sdp_interface;
170+ uint32_t gc_num_tcps;
171+};
172+
173+struct gc_info_v2_0 {
174+ struct gpu_info_header header;
175+
176+ uint32_t gc_num_se;
177+ uint32_t gc_num_cu_per_sh;
178+ uint32_t gc_num_sh_per_se;
179+ uint32_t gc_num_rb_per_se;
180+ uint32_t gc_num_tccs;
181+ uint32_t gc_num_gprs;
182+ uint32_t gc_num_max_gs_thds;
183+ uint32_t gc_gs_table_depth;
184+ uint32_t gc_gsprim_buff_depth;
185+ uint32_t gc_parameter_cache_depth;
186+ uint32_t gc_double_offchip_lds_buffer;
187+ uint32_t gc_wave_size;
188+ uint32_t gc_max_waves_per_simd;
189+ uint32_t gc_max_scratch_slots_per_cu;
190+ uint32_t gc_lds_size;
191+ uint32_t gc_num_sc_per_se;
192+ uint32_t gc_num_packer_per_sc;
193+};
194+
146195 typedef struct harvest_info_header {
147196 uint32_t signature; /* Table Signature */
148197 uint32_t version; /* Table Version */
drivers/gpu/drm/amd/pm/amdgpu_pm.c+8−1
@@ -2090,7 +2090,8 @@ static int default_attr_update(struct amdgpu_device *adev, struct amdgpu_device_ · 2089 unmodified lines
20902090 } else if (DEVICE_ATTR_IS(unique_id)) {
20912091 if (asic_type != CHIP_VEGA10 &&
20922092 asic_type != CHIP_VEGA20 &&
2093− asic_type != CHIP_ARCTURUS)
2093+ asic_type != CHIP_ARCTURUS &&
2094+ asic_type != CHIP_ALDEBARAN)
20942095 *states = ATTR_STATE_UNSUPPORTED;
20952096 } else if (DEVICE_ATTR_IS(pp_features)) {
20962097 if (adev->flags & AMD_IS_APU || asic_type < CHIP_VEGA10)
@@ -2133,6 +2134,12 @@ static int default_attr_update(struct amdgpu_device *adev, struct amdgpu_device_ · 36 unmodified lines
21332134 }
21342135 }
21352136
2137+ /* setting should not be allowed from VF */
2138+ if (amdgpu_sriov_vf(adev)) {
2139+ dev_attr->attr.mode &= ~S_IWUGO;
2140+ dev_attr->store = NULL;
2141+ }
2142+
21362143 #undef DEVICE_ATTR_IS
21372144
21382145 return 0;
drivers/gpu/drm/amd/pm/inc/aldebaran_ppsmc.h+3−1
@@ -102,7 +102,9 @@ · 101 unmodified lines
102102
103103 #define PPSMC_MSG_GfxDriverResetRecovery 0x42
104104 #define PPSMC_MSG_BoardPowerCalibration 0x43
105−#define PPSMC_Message_Count 0x44
105+#define PPSMC_MSG_HeavySBR 0x45
106+#define PPSMC_Message_Count 0x46
107+
106108
107109 //PPSMC Reset Types
108110 #define PPSMC_RESET_TYPE_WARM_RESET 0x00
drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h+3−3
@@ -1257,9 +1257,9 @@ struct pptable_funcs { · 1256 unmodified lines
12571257 int (*set_fine_grain_gfx_freq_parameters)(struct smu_context *smu);
12581258
12591259 /**
1260− * @set_light_sbr: Set light sbr mode for the SMU.
1260+ * @smu_handle_passthrough_sbr: Send message to SMU about special handling for SBR.
12611261 */
1262− int (*set_light_sbr)(struct smu_context *smu, bool enable);
1262+ int (*smu_handle_passthrough_sbr)(struct smu_context *smu, bool enable);
12631263
12641264 /**
12651265 * @wait_for_event: Wait for events from SMU.
@@ -1415,7 +1415,7 @@ int smu_allow_xgmi_power_down(struct smu_context *smu, bool en); · 149 unmodified lines
14151415
14161416 int smu_get_status_gfxoff(struct amdgpu_device *adev, uint32_t *value);
14171417
1418−int smu_set_light_sbr(struct smu_context *smu, bool enable);
1418+int smu_handle_passthrough_sbr(struct smu_context *smu, bool enable);
14191419
14201420 int smu_wait_for_event(struct amdgpu_device *adev, enum smu_event_type event,
14211421 uint64_t event_arg);
drivers/gpu/drm/amd/pm/inc/smu_types.h+2−1
@@ -229,7 +229,8 @@ · 228 unmodified lines
229229 __SMU_DUMMY_MAP(BoardPowerCalibration), \
230230 __SMU_DUMMY_MAP(RequestGfxclk), \
231231 __SMU_DUMMY_MAP(ForceGfxVid), \
232− __SMU_DUMMY_MAP(UnforceGfxVid),
232+ __SMU_DUMMY_MAP(UnforceGfxVid), \
233+ __SMU_DUMMY_MAP(HeavySBR),
233234
234235 #undef __SMU_DUMMY_MAP
235236 #define __SMU_DUMMY_MAP(type) SMU_MSG_##type
drivers/gpu/drm/amd/pm/inc/smu_v11_0.h+1−1
@@ -312,7 +312,7 @@ int smu_v11_0_deep_sleep_control(struct smu_context *smu, · 311 unmodified lines
312312
313313 void smu_v11_0_interrupt_work(struct smu_context *smu);
314314
315−int smu_v11_0_set_light_sbr(struct smu_context *smu, bool enable);
315+int smu_v11_0_handle_passthrough_sbr(struct smu_context *smu, bool enable);
316316
317317 int smu_v11_0_restore_user_od_settings(struct smu_context *smu);
318318
drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c+5−8
@@ -1569,9 +1569,7 @@ static int smu_suspend(void *handle) · 1568 unmodified lines
15691569
15701570 smu->watermarks_bitmap &= ~(WATERMARKS_LOADED);
15711571
1572− /* skip CGPG when in S0ix */
1573− if (smu->is_apu && !adev->in_s0ix)
1574− smu_set_gfx_cgpg(&adev->smu, false);
1572+ smu_set_gfx_cgpg(&adev->smu, false);
15751573
15761574 return 0;
15771575 }
@@ -1602,8 +1600,7 @@ static int smu_resume(void *handle) · 24 unmodified lines
16021600 return ret;
16031601 }
16041602
1605− if (smu->is_apu)
1606− smu_set_gfx_cgpg(&adev->smu, true);
1603+ smu_set_gfx_cgpg(&adev->smu, true);
16071604
16081605 smu->disable_uclk_switch = 0;
16091606
@@ -3061,13 +3058,13 @@ static int smu_gfx_state_change_set(void *handle, · 1451 unmodified lines
30613058 return ret;
30623059 }
30633060
3064−int smu_set_light_sbr(struct smu_context *smu, bool enable)
3061+int smu_handle_passthrough_sbr(struct smu_context *smu, bool enable)
30653062 {
30663063 int ret = 0;
30673064
30683065 mutex_lock(&smu->mutex);
3069− if (smu->ppt_funcs->set_light_sbr)
3070− ret = smu->ppt_funcs->set_light_sbr(smu, enable);
3066+ if (smu->ppt_funcs->smu_handle_passthrough_sbr)
3067+ ret = smu->ppt_funcs->smu_handle_passthrough_sbr(smu, enable);
30713068 mutex_unlock(&smu->mutex);
30723069
30733070 return ret;
drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c+1−1
@@ -2472,7 +2472,7 @@ static const struct pptable_funcs arcturus_ppt_funcs = { · 2471 unmodified lines
24722472 .deep_sleep_control = smu_v11_0_deep_sleep_control,
24732473 .get_fan_parameters = arcturus_get_fan_parameters,
24742474 .interrupt_work = smu_v11_0_interrupt_work,
2475− .set_light_sbr = smu_v11_0_set_light_sbr,
2475+ .smu_handle_passthrough_sbr = smu_v11_0_handle_passthrough_sbr,
24762476 .set_mp1_state = smu_cmn_set_mp1_state,
24772477 };
24782478
drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c+1−1
@@ -1724,7 +1724,7 @@ int smu_v11_0_mode1_reset(struct smu_context *smu) · 1723 unmodified lines
17241724 return ret;
17251725 }
17261726
1727−int smu_v11_0_set_light_sbr(struct smu_context *smu, bool enable)
1727+int smu_v11_0_handle_passthrough_sbr(struct smu_context *smu, bool enable)
17281728 {
17291729 int ret = 0;
17301730
drivers/gpu/drm/amd/pm/swsmu/smu12/smu_v12_0.c+2−1
@@ -120,7 +120,8 @@ int smu_v12_0_powergate_sdma(struct smu_context *smu, bool gate) · 119 unmodified lines
120120
121121 int smu_v12_0_set_gfx_cgpg(struct smu_context *smu, bool enable)
122122 {
123− if (!(smu->adev->pg_flags & AMD_PG_SUPPORT_GFX_PG))
123+ /* Until now the SMU12 only implemented for Renoir series so here neen't do APU check. */
124+ if (!(smu->adev->pg_flags & AMD_PG_SUPPORT_GFX_PG) || smu->adev->in_s0ix)
124125 return 0;
125126
126127 return smu_cmn_send_smc_msg_with_param(smu,
drivers/gpu/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c+13−2
@@ -141,6 +141,7 @@ static const struct cmn2asic_msg_mapping aldebaran_message_map[SMU_MSG_MAX_COUNT · 140 unmodified lines
141141 MSG_MAP(SetUclkDpmMode, PPSMC_MSG_SetUclkDpmMode, 0),
142142 MSG_MAP(GfxDriverResetRecovery, PPSMC_MSG_GfxDriverResetRecovery, 0),
143143 MSG_MAP(BoardPowerCalibration, PPSMC_MSG_BoardPowerCalibration, 0),
144+ MSG_MAP(HeavySBR, PPSMC_MSG_HeavySBR, 0),
144145 };
145146
146147 static const struct cmn2asic_mapping aldebaran_clk_map[SMU_CLK_COUNT] = {
@@ -1605,7 +1606,8 @@ out_unlock: · 1458 unmodified lines
16051606 mutex_unlock(&smu->metrics_lock);
16061607
16071608 adev->unique_id = ((uint64_t)upper32 << 32) | lower32;
1608− sprintf(adev->serial, "%016llx", adev->unique_id);
1609+ if (adev->serial[0] == '\0')
1610+ sprintf(adev->serial, "%016llx", adev->unique_id);
16091611 }
16101612
16111613 static bool aldebaran_is_baco_supported(struct smu_context *smu)
@@ -1625,7 +1627,7 @@ static int aldebaran_allow_xgmi_power_down(struct smu_context *smu, bool en) · 13 unmodified lines
16251627 {
16261628 return smu_cmn_send_smc_msg_with_param(smu,
16271629 SMU_MSG_GmiPwrDnControl,
1628− en ? 1 : 0,
1630+ en ? 0 : 1,
16291631 NULL);
16301632 }
16311633
@@ -1912,6 +1914,14 @@ out: · 280 unmodified lines
19121914 return ret;
19131915 }
19141916
1917+static int aldebaran_smu_handle_passthrough_sbr(struct smu_context *smu, bool enable)
1918+{
1919+ int ret = 0;
1920+ ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_HeavySBR, enable ? 1 : 0, NULL);
1921+
1922+ return ret;
1923+}
1924+
19151925 static bool aldebaran_is_mode1_reset_supported(struct smu_context *smu)
19161926 {
19171927 #if 0
@@ -2021,6 +2031,7 @@ static const struct pptable_funcs aldebaran_ppt_funcs = { · 103 unmodified lines
20212031 .get_gpu_metrics = aldebaran_get_gpu_metrics,
20222032 .mode1_reset_is_support = aldebaran_is_mode1_reset_supported,
20232033 .mode2_reset_is_support = aldebaran_is_mode2_reset_supported,
2034+ .smu_handle_passthrough_sbr = aldebaran_smu_handle_passthrough_sbr,
20242035 .mode1_reset = aldebaran_mode1_reset,
20252036 .set_mp1_state = aldebaran_set_mp1_state,
20262037 .mode2_reset = aldebaran_mode2_reset,
drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c+10−5
@@ -212,7 +212,7 @@ int smu_v13_0_check_fw_version(struct smu_context *smu) · 211 unmodified lines
212212 if (smu->is_apu)
213213 adev->pm.fw_version = smu_version;
214214
215− switch (smu->adev->ip_versions[MP1_HWIP][0]) {
215+ switch (adev->ip_versions[MP1_HWIP][0]) {
216216 case IP_VERSION(13, 0, 2):
217217 smu->smc_driver_if_version = SMU13_DRIVER_IF_VERSION_ALDE;
218218 break;
@@ -221,12 +221,17 @@ int smu_v13_0_check_fw_version(struct smu_context *smu) · 2 unmodified lines
221221 smu->smc_driver_if_version = SMU13_DRIVER_IF_VERSION_YELLOW_CARP;
222222 break;
223223 default:
224− dev_err(smu->adev->dev, "smu unsupported IP version: 0x%x.\n",
225− smu->adev->ip_versions[MP1_HWIP][0]);
224+ dev_err(adev->dev, "smu unsupported IP version: 0x%x.\n",
225+ adev->ip_versions[MP1_HWIP][0]);
226226 smu->smc_driver_if_version = SMU13_DRIVER_IF_VERSION_INV;
227227 break;
228228 }
229229
230+ /* only for dGPU w/ SMU13*/
231+ if (adev->pm.fw)
232+ dev_dbg(adev->dev, "smu fw reported version = 0x%08x (%d.%d.%d)\n",
233+ smu_version, smu_major, smu_minor, smu_debug);
234+
230235 /*
231236 * 1. if_version mismatch is not critical as our fw is designed
232237 * to be backward compatible.
@@ -236,11 +241,11 @@ int smu_v13_0_check_fw_version(struct smu_context *smu) · 3 unmodified lines
236241 * of halt driver loading.
237242 */
238243 if (if_version != smu->smc_driver_if_version) {
239− dev_info(smu->adev->dev, "smu driver if version = 0x%08x, smu fw if version = 0x%08x, "
244+ dev_info(adev->dev, "smu driver if version = 0x%08x, smu fw if version = 0x%08x, "
240245 "smu fw version = 0x%08x (%d.%d.%d)\n",
241246 smu->smc_driver_if_version, if_version,
242247 smu_version, smu_major, smu_minor, smu_debug);
243− dev_warn(smu->adev->dev, "SMU driver if version not matched\n");
248+ dev_warn(adev->dev, "SMU driver if version not matched\n");
244249 }
245250
246251 return ret;