History

Merge tag 'phy-for-6.3' of git://git.kernel.org/pub/scm/linux/kernel/git/phy/linux-phy

Pull phy updates from Vinod Koul: "This features a bunch of new device support, a couple of new drivers, yaml conversion and updates of a few drivers. Core support: - New devm_of_phy_optional_get() API with users and conversion New hardware support: - Mediatek MT7986 phy support - Qualcomm SM8550 UFS, PCIe, combo phy support, SM6115 / SM4250 USB3 phy support, SM6350 combo phy support, SM6125 UFS PHY support amd SM8350 & SM8450 combo phy support - Qualcomm SNPS eUSB2 eUSB2 repeater drivers - Allwinner F1C100s USB PHY support - Tegra xusb support for Tegra234 Updates: - Yaml conversion for Qualcomm pcie2 phy and usb-hsic-phy - G4 mode support in Qualcomm UFS phy and support for various SoCs - Yaml conversion for Meson usb2 phy - TI Type C support for usb phy for j721 - Yaml conversion for Tegra xusb binding" * tag 'phy-for-6.3' of git://git.kernel.org/pub/scm/linux/kernel/git/phy/linux-phy: (106 commits) phy: qcom: phy-qcom-snps-eusb2: Add support for eUSB2 repeater phy: qcom: Add QCOM SNPS eUSB2 repeater driver dt-bindings: phy: qcom,snps-eusb2-phy: Add phys property for the repeater dt-bindings: phy: Add qcom,snps-eusb2-repeater schema file dt-bindings: phy: amlogic,g12a-usb3-pcie-phy: add missing optional phy-supply property phy: rockchip-typec: Fix unsigned comparison with less than zero phy: rockchip-typec: fix tcphy_get_mode error case phy: qcom: snps-eusb2: Add missing headers phy: qcom-qmp-combo: Add support for SM8550 phy: qcom-qmp: Add v6 DP register offsets phy: qcom-qmp: pcs-usb: Add v6 register offsets dt-bindings: phy: qcom,sc8280xp-qmp-usb43dp: Document SM8550 compatible phy: qcom: Add QCOM SNPS eUSB2 driver dt-bindings: phy: Add qcom,snps-eusb2-phy schema file phy: qcom-qmp-pcie: Add support for SM8550 g3x2 and g4x2 PCIEs phy: qcom-qmp: qserdes-lane-shared: Add v6 register offsets phy: qcom-qmp: qserdes-txrx: Add v6.20 register offsets phy: qcom-qmp: pcs-pcie: Add v6.20 register offsets phy: qcom-qmp: pcs-pcie: Add v6 register offsets phy: qcom-qmp: pcs: Add v6.20 register offsets ...

Linus Torvalds committed 3 years ago

Commit 8ff99ad2 parents 9e6bfd4 3584f6369 files · +6574 −1495Browse files

Unified · Split

69 files
  1. Documentation/devicetree/bindings/phy/allwinner,suniv-f1c100s-usb-phy.yaml +83 −0
  2. Documentation/devicetree/bindings/phy/amlogic,g12a-usb3-pcie-phy.yaml +5 −0
  3. Documentation/devicetree/bindings/phy/amlogic,meson-gxl-usb2-phy.yaml +56 −0
  4. Documentation/devicetree/bindings/phy/mediatek,tphy.yaml +1 −0
  5. Documentation/devicetree/bindings/phy/meson-gxl-usb2-phy.txt +0 −21
  6. Documentation/devicetree/bindings/phy/nvidia,tegra124-xusb-padctl.txt +0 −779
  7. Documentation/devicetree/bindings/phy/nvidia,tegra124-xusb-padctl.yaml +654 −0
  8. Documentation/devicetree/bindings/phy/nvidia,tegra186-xusb-padctl.yaml +544 −0
  9. Documentation/devicetree/bindings/phy/nvidia,tegra194-xusb-padctl.yaml +632 −0
  10. Documentation/devicetree/bindings/phy/nvidia,tegra210-xusb-padctl.yaml +786 −0
  11. Documentation/devicetree/bindings/phy/qcom,msm8996-qmp-ufs-phy.yaml +3 −0
  12. Documentation/devicetree/bindings/phy/qcom,msm8996-qmp-usb3-phy.yaml +3 −0
  13. Documentation/devicetree/bindings/phy/qcom,pcie2-phy.yaml +86 −0
  14. Documentation/devicetree/bindings/phy/qcom,qusb2-phy.yaml +85 −75
  15. Documentation/devicetree/bindings/phy/qcom,sc7180-qmp-usb3-dp-phy.yaml +73 −16
  16. Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml +51 −1
  17. Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-ufs-phy.yaml +5 −0
  18. Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-usb43dp-phy.yaml +4 −0
  19. Documentation/devicetree/bindings/phy/qcom,snps-eusb2-phy.yaml +79 −0
  20. Documentation/devicetree/bindings/phy/qcom,snps-eusb2-repeater.yaml +52 −0
  21. Documentation/devicetree/bindings/phy/qcom,usb-hsic-phy.txt +0 −65
  22. Documentation/devicetree/bindings/phy/qcom,usb-hsic-phy.yaml +67 −0
  23. Documentation/devicetree/bindings/phy/qcom,usb-snps-femto-v2.yaml +20 −13
  24. Documentation/devicetree/bindings/phy/qcom-pcie2-phy.txt +0 −42
  25. Documentation/devicetree/bindings/phy/ti,tcan104x-can.yaml +1 −0
  26. Documentation/driver-api/phy/phy.rst +14 −10
  27. drivers/net/ethernet/freescale/fman/fman_memac.c +4 −5
  28. drivers/net/ethernet/microchip/lan966x/lan966x_main.c +2 −3
  29. drivers/pci/controller/pci-tegra.c +1 −4
  30. drivers/phy/allwinner/phy-sun4i-usb.c +24 −35
  31. drivers/phy/mediatek/phy-mtk-io.h +2 −2
  32. drivers/phy/phy-can-transceiver.c +4 −0
  33. drivers/phy/phy-core.c +30 −21
  34. drivers/phy/qualcomm/Kconfig +64 −4
  35. drivers/phy/qualcomm/Makefile +8 −6
  36. drivers/phy/qualcomm/phy-qcom-eusb2-repeater.c +259 −0
  37. drivers/phy/qualcomm/phy-qcom-pcie2.c +5 −1
  38. drivers/phy/qualcomm/phy-qcom-qmp-combo.c +724 −26
  39. drivers/phy/qualcomm/phy-qcom-qmp-pcie-msm8996.c +3 −3
  40. drivers/phy/qualcomm/phy-qcom-qmp-pcie.c +535 −53
  41. drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v6.h +15 −0
  42. drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v6_20.h +23 −0
  43. drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v2.h +25 −0
  44. drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v3.h +3 −0
  45. drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v5.h +5 −0
  46. drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v6.h +31 −0
  47. drivers/phy/qualcomm/phy-qcom-qmp-pcs-usb-v6.h +31 −0
  48. drivers/phy/qualcomm/phy-qcom-qmp-pcs-v2.h +8 −11
  49. drivers/phy/qualcomm/phy-qcom-qmp-pcs-v5.h +4 −0
  50. drivers/phy/qualcomm/phy-qcom-qmp-pcs-v6.h +16 −0
  51. drivers/phy/qualcomm/phy-qcom-qmp-pcs-v6_20.h +18 −0
  52. drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v6.h +82 −0
  53. drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com.h +1 −1
  54. drivers/phy/qualcomm/phy-qcom-qmp-qserdes-ln-shrd-v6.h +32 −0
  55. drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-ufs-v6.h +30 −0
  56. drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-v5_5nm.h +0 −5
  57. drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-v6.h +77 −0
  58. drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-v6_20.h +45 −0
  59. drivers/phy/qualcomm/phy-qcom-qmp-ufs.c +538 −150
  60. drivers/phy/qualcomm/phy-qcom-qmp-usb.c +41 −42
  61. drivers/phy/qualcomm/phy-qcom-qmp.h +12 −11
  62. drivers/phy/qualcomm/phy-qcom-snps-eusb2.c +441 −0
  63. drivers/phy/renesas/r8a779f0-ether-serdes.c +30 −35
  64. drivers/phy/rockchip/phy-rockchip-typec.c +3 −4
  65. drivers/phy/tegra/xusb.c +17 −0
  66. drivers/phy/ti/phy-j721e-wiz.c +56 −10
  67. drivers/usb/host/ehci-exynos.c +6 −17
  68. drivers/usb/host/ohci-exynos.c +6 −17
  69. include/linux/phy/phy.h +9 −7
Documentation/devicetree/bindings/phy/allwinner,suniv-f1c100s-usb-phy.yaml+83−0
@@ -0,0 +1,83 @@
1+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2+%YAML 1.2
3+---
4+$id: http://devicetree.org/schemas/phy/allwinner,suniv-f1c100s-usb-phy.yaml#
5+$schema: http://devicetree.org/meta-schemas/core.yaml#
6+
7+title: Allwinner F1C100s USB PHY
8+
9+maintainers:
10+ - Chen-Yu Tsai <wens@csie.org>
11+ - Maxime Ripard <mripard@kernel.org>
12+
13+properties:
14+ "#phy-cells":
15+ const: 1
16+
17+ compatible:
18+ const: allwinner,suniv-f1c100s-usb-phy
19+
20+ reg:
21+ maxItems: 1
22+ description: PHY Control registers
23+
24+ reg-names:
25+ const: phy_ctrl
26+
27+ clocks:
28+ maxItems: 1
29+ description: USB OTG PHY bus clock
30+
31+ clock-names:
32+ const: usb0_phy
33+
34+ resets:
35+ maxItems: 1
36+ description: USB OTG reset
37+
38+ reset-names:
39+ const: usb0_reset
40+
41+ usb0_id_det-gpios:
42+ maxItems: 1
43+ description: GPIO to the USB OTG ID pin
44+
45+ usb0_vbus_det-gpios:
46+ maxItems: 1
47+ description: GPIO to the USB OTG VBUS detect pin
48+
49+ usb0_vbus_power-supply:
50+ description: Power supply to detect the USB OTG VBUS
51+
52+ usb0_vbus-supply:
53+ description: Regulator controlling USB OTG VBUS
54+
55+required:
56+ - "#phy-cells"
57+ - compatible
58+ - clocks
59+ - clock-names
60+ - reg
61+ - reg-names
62+ - resets
63+ - reset-names
64+
65+additionalProperties: false
66+
67+examples:
68+ - |
69+ #include <dt-bindings/gpio/gpio.h>
70+ #include <dt-bindings/clock/suniv-ccu-f1c100s.h>
71+ #include <dt-bindings/reset/suniv-ccu-f1c100s.h>
72+
73+ phy@1c13400 {
74+ compatible = "allwinner,suniv-f1c100s-usb-phy";
75+ reg = <0x01c13400 0x10>;
76+ reg-names = "phy_ctrl";
77+ clocks = <&ccu CLK_USB_PHY0>;
78+ clock-names = "usb0_phy";
79+ resets = <&ccu RST_USB_PHY0>;
80+ reset-names = "usb0_reset";
81+ #phy-cells = <1>;
82+ usb0_id_det-gpios = <&pio 4 2 GPIO_ACTIVE_HIGH>;
83+ };
Documentation/devicetree/bindings/phy/amlogic,g12a-usb3-pcie-phy.yaml+5−0
@@ -35,6 +35,11 @@ properties: · 34 unmodified lines
3535 "#phy-cells":
3636 const: 1
3737
38+ phy-supply:
39+ description:
40+ Phandle to a regulator that provides power to the PHY. This
41+ regulator will be managed during the PHY power on/off sequence.
42+
3843 required:
3944 - compatible
4045 - reg
Documentation/devicetree/bindings/phy/amlogic,meson-gxl-usb2-phy.yaml+56−0
@@ -0,0 +1,56 @@
1+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2+%YAML 1.2
3+---
4+$id: http://devicetree.org/schemas/phy/amlogic,meson-gxl-usb2-phy.yaml#
5+$schema: http://devicetree.org/meta-schemas/core.yaml#
6+
7+title: Amlogic Meson GXL USB2 PHY
8+
9+maintainers:
10+ - Neil Armstrong <neil.armstrong@linaro.org>
11+
12+properties:
13+ compatible:
14+ const: amlogic,meson-gxl-usb2-phy
15+
16+ reg:
17+ maxItems: 1
18+
19+ clocks:
20+ maxItems: 1
21+
22+ clock-names:
23+ items:
24+ - const: phy
25+
26+ resets:
27+ maxItems: 1
28+
29+ reset-names:
30+ items:
31+ - const: phy
32+
33+ "#phy-cells":
34+ const: 0
35+
36+ phy-supply: true
37+
38+required:
39+ - compatible
40+ - reg
41+ - "#phy-cells"
42+
43+additionalProperties: false
44+
45+examples:
46+ - |
47+ phy@78000 {
48+ compatible = "amlogic,meson-gxl-usb2-phy";
49+ reg = <0x78000 0x20>;
50+ clocks = <&xtal>;
51+ clock-names = "phy";
52+ resets = <&phy_reset>;
53+ reset-names = "phy";
54+ #phy-cells = <0>;
55+ phy-supply = <&usb2_supply>;
56+ };
Documentation/devicetree/bindings/phy/mediatek,tphy.yaml+1−0
@@ -79,6 +79,7 @@ properties: · 78 unmodified lines
7979 - enum:
8080 - mediatek,mt2712-tphy
8181 - mediatek,mt7629-tphy
82+ - mediatek,mt7986-tphy
8283 - mediatek,mt8183-tphy
8384 - mediatek,mt8186-tphy
8485 - mediatek,mt8192-tphy
Documentation/devicetree/bindings/phy/meson-gxl-usb2-phy.txt+0−21
@@ -1,21 +0,0 @@
1−* Amlogic Meson GXL and GXM USB2 PHY binding
2−
3−Required properties:
4−- compatible: Should be "amlogic,meson-gxl-usb2-phy"
5−- reg: The base address and length of the registers
6−- #phys-cells: must be 0 (see phy-bindings.txt in this directory)
7−
8−Optional properties:
9−- clocks: a phandle to the clock of this PHY
10−- clock-names: must be "phy"
11−- resets: a phandle to the reset line of this PHY
12−- reset-names: must be "phy"
13−- phy-supply: see phy-bindings.txt in this directory
14−
15−
16−Example:
17− usb2_phy0: phy@78000 {
18− compatible = "amlogic,meson-gxl-usb2-phy";
19− #phy-cells = <0>;
20− reg = <0x0 0x78000 0x0 0x20>;
21− };
Documentation/devicetree/bindings/phy/nvidia,tegra124-xusb-padctl.txt+0−779
@@ -1,779 +0,0 @@
1−Device tree binding for NVIDIA Tegra XUSB pad controller
2−========================================================
3−
4−The Tegra XUSB pad controller manages a set of I/O lanes (with differential
5−signals) which connect directly to pins/pads on the SoC package. Each lane
6−is controlled by a HW block referred to as a "pad" in the Tegra hardware
7−documentation. Each such "pad" may control either one or multiple lanes,
8−and thus contains any logic common to all its lanes. Each lane can be
9−separately configured and powered up.
10−
11−Some of the lanes are high-speed lanes, which can be used for PCIe, SATA or
12−super-speed USB. Other lanes are for various types of low-speed, full-speed
13−or high-speed USB (such as UTMI, ULPI and HSIC). The XUSB pad controller
14−contains a software-configurable mux that sits between the I/O controller
15−ports (e.g. PCIe) and the lanes.
16−
17−In addition to per-lane configuration, USB 3.0 ports may require additional
18−settings on a per-board basis.
19−
20−Pads will be represented as children of the top-level XUSB pad controller
21−device tree node. Each lane exposed by the pad will be represented by its
22−own subnode and can be referenced by users of the lane using the standard
23−PHY bindings, as described by the phy-bindings.txt file in this directory.
24−
25−The Tegra hardware documentation refers to the connection between the XUSB
26−pad controller and the XUSB controller as "ports". This is confusing since
27−"port" is typically used to denote the physical USB receptacle. The device
28−tree binding in this document uses the term "port" to refer to the logical
29−abstraction of the signals that are routed to a USB receptacle (i.e. a PHY
30−for the USB signal, the VBUS power supply, the USB 2.0 companion port for
31−USB 3.0 receptacles, ...).
32−
33−Required properties:
34−--------------------
35−- compatible: Must be:
36− - Tegra124: "nvidia,tegra124-xusb-padctl"
37− - Tegra132: "nvidia,tegra132-xusb-padctl", "nvidia,tegra124-xusb-padctl"
38− - Tegra210: "nvidia,tegra210-xusb-padctl"
39− - Tegra186: "nvidia,tegra186-xusb-padctl"
40− - Tegra194: "nvidia,tegra194-xusb-padctl"
41−- reg: Physical base address and length of the controller's registers.
42−- resets: Must contain an entry for each entry in reset-names.
43−- reset-names: Must include the following entries:
44− - "padctl"
45−
46−For Tegra124:
47−- avdd-pll-utmip-supply: UTMI PLL power supply. Must supply 1.8 V.
48−- avdd-pll-erefe-supply: PLLE reference PLL power supply. Must supply 1.05 V.
49−- avdd-pex-pll-supply: PCIe/USB3 PLL power supply. Must supply 1.05 V.
50−- hvdd-pex-pll-e-supply: High-voltage PLLE power supply. Must supply 3.3 V.
51−
52−For Tegra210:
53−- avdd-pll-utmip-supply: UTMI PLL power supply. Must supply 1.8 V.
54−- avdd-pll-uerefe-supply: PLLE reference PLL power supply. Must supply 1.05 V.
55−- dvdd-pex-pll-supply: PCIe/USB3 PLL power supply. Must supply 1.05 V.
56−- hvdd-pex-pll-e-supply: High-voltage PLLE power supply. Must supply 1.8 V.
57−- nvidia,pmc: phandle and specifier referring to the Tegra210 PMC node.
58−
59−For Tegra186:
60−- avdd-pll-erefeut-supply: UPHY brick and reference clock as well as UTMI PHY
61− power supply. Must supply 1.8 V.
62−- avdd-usb-supply: USB I/Os, VBUS, ID, REXT, D+/D- power supply. Must supply
63− 3.3 V.
64−- vclamp-usb-supply: Bias rail for USB pad. Must supply 1.8 V.
65−- vddio-hsic-supply: HSIC PHY power supply. Must supply 1.2 V.
66−
67−For Tegra194:
68−- avdd-usb-supply: USB I/Os, VBUS, ID, REXT, D+/D- power supply. Must supply
69− 3.3 V.
70−- vclamp-usb-supply: Bias rail for USB pad. Must supply 1.8 V.
71−
72−Pad nodes:
73−==========
74−
75−A required child node named "pads" contains a list of subnodes, one for each
76−of the pads exposed by the XUSB pad controller. Each pad may need additional
77−resources that can be referenced in its pad node.
78−
79−The "status" property is used to enable or disable the use of a pad. If set
80−to "disabled", the pad will not be used on the given board. In order to use
81−the pad and any of its lanes, this property must be set to "okay".
82−
83−For Tegra124 and Tegra132, the following pads exist: usb2, ulpi, hsic, pcie
84−and sata. No extra resources are required for operation of these pads.
85−
86−For Tegra210, the following pads exist: usb2, hsic, pcie and sata. Below is
87−a description of the properties of each pad.
88−
89−UTMI pad:
90−---------
91−
92−Required properties:
93−- clocks: Must contain an entry for each entry in clock-names.
94−- clock-names: Must contain the following entries:
95− - "trk": phandle and specifier referring to the USB2 tracking clock
96−
97−HSIC pad:
98−---------
99−
100−Required properties:
101−- clocks: Must contain an entry for each entry in clock-names.
102−- clock-names: Must contain the following entries:
103− - "trk": phandle and specifier referring to the HSIC tracking clock
104−
105−PCIe pad:
106−---------
107−
108−Required properties:
109−- clocks: Must contain an entry for each entry in clock-names.
110−- clock-names: Must contain the following entries:
111− - "pll": phandle and specifier referring to the PLLE
112−- resets: Must contain an entry for each entry in reset-names.
113−- reset-names: Must contain the following entries:
114− - "phy": reset for the PCIe UPHY block
115−
116−SATA pad:
117−---------
118−
119−Required properties:
120−- resets: Must contain an entry for each entry in reset-names.
121−- reset-names: Must contain the following entries:
122− - "phy": reset for the SATA UPHY block
123−
124−
125−PHY nodes:
126−==========
127−
128−Each pad node has a child named "lanes" that contains one or more children of
129−its own, each representing one of the lanes controlled by the pad.
130−
131−Required properties:
132−--------------------
133−- status: Defines the operation status of the PHY. Valid values are:
134− - "disabled": the PHY is disabled
135− - "okay": the PHY is enabled
136−- #phy-cells: Should be 0. Since each lane represents a single PHY, there is
137− no need for an additional specifier.
138−- nvidia,function: The output function of the PHY. See below for a list of
139− valid functions per SoC generation.
140−
141−For Tegra124 and Tegra132, the list of valid PHY nodes is given below:
142−- usb2: usb2-0, usb2-1, usb2-2
143− - functions: "snps", "xusb", "uart"
144−- ulpi: ulpi-0
145− - functions: "snps", "xusb"
146−- hsic: hsic-0, hsic-1
147− - functions: "snps", "xusb"
148−- pcie: pcie-0, pcie-1, pcie-2, pcie-3, pcie-4
149− - functions: "pcie", "usb3-ss"
150−- sata: sata-0
151− - functions: "usb3-ss", "sata"
152−
153−For Tegra210, the list of valid PHY nodes is given below:
154−- usb2: usb2-0, usb2-1, usb2-2, usb2-3
155− - functions: "snps", "xusb", "uart"
156−- hsic: hsic-0, hsic-1
157− - functions: "snps", "xusb"
158−- pcie: pcie-0, pcie-1, pcie-2, pcie-3, pcie-4, pcie-5, pcie-6
159− - functions: "pcie-x1", "usb3-ss", "pcie-x4"
160−- sata: sata-0
161− - functions: "usb3-ss", "sata"
162−
163−For Tegra194, the list of valid PHY nodes is given below:
164−- usb2: usb2-0, usb2-1, usb2-2, usb2-3
165− - functions: "xusb"
166−- usb3: usb3-0, usb3-1, usb3-2, usb3-3
167− - functions: "xusb"
168−
169−Port nodes:
170−===========
171−
172−A required child node named "ports" contains a list of all the ports exposed
173−by the XUSB pad controller. Per-port configuration is only required for USB.
174−
175−USB2 ports:
176−-----------
177−
178−Required properties:
179−- status: Defines the operation status of the port. Valid values are:
180− - "disabled": the port is disabled
181− - "okay": the port is enabled
182−- mode: A string that determines the mode in which to run the port. Valid
183− values are:
184− - "host": for USB host mode
185− - "device": for USB device mode
186− - "otg": for USB OTG mode
187−
188−Required properties for OTG/Peripheral capable USB2 ports:
189−- usb-role-switch: Boolean property to indicate that the port support OTG or
190− peripheral mode. If present, the port supports switching between USB host
191− and peripheral roles. Connector should be added as subnode.
192− See usb/usb-conn-gpio.txt.
193−
194−Optional properties:
195−- nvidia,internal: A boolean property whose presence determines that a port
196− is internal. In the absence of this property the port is considered to be
197− external.
198−- vbus-supply: phandle to a regulator supplying the VBUS voltage.
199−
200−ULPI ports:
201−-----------
202−
203−Optional properties:
204−- status: Defines the operation status of the port. Valid values are:
205− - "disabled": the port is disabled
206− - "okay": the port is enabled
207−- nvidia,internal: A boolean property whose presence determines that a port
208− is internal. In the absence of this property the port is considered to be
209− external.
210−- vbus-supply: phandle to a regulator supplying the VBUS voltage.
211−
212−HSIC ports:
213−-----------
214−
215−Required properties:
216−- status: Defines the operation status of the port. Valid values are:
217− - "disabled": the port is disabled
218− - "okay": the port is enabled
219−
220−Optional properties:
221−- vbus-supply: phandle to a regulator supplying the VBUS voltage.
222−
223−Super-speed USB ports:
224−----------------------
225−
226−Required properties:
227−- status: Defines the operation status of the port. Valid values are:
228− - "disabled": the port is disabled
229− - "okay": the port is enabled
230−- nvidia,usb2-companion: A single cell that specifies the physical port number
231− to map this super-speed USB port to. The range of valid port numbers varies
232− with the SoC generation:
233− - 0-2: for Tegra124 and Tegra132
234− - 0-3: for Tegra210
235−
236−Optional properties:
237−- nvidia,internal: A boolean property whose presence determines that a port
238− is internal. In the absence of this property the port is considered to be
239− external.
240−
241−- maximum-speed: Only for Tegra194. A string property that specifies maximum
242− supported speed of a usb3 port. Valid values are:
243− - "super-speed-plus": default, the usb3 port supports USB 3.1 Gen 2 speed.
244− - "super-speed": the usb3 port supports USB 3.1 Gen 1 speed only.
245−
246−For Tegra124 and Tegra132, the XUSB pad controller exposes the following
247−ports:
248−- 3x USB2: usb2-0, usb2-1, usb2-2
249−- 1x ULPI: ulpi-0
250−- 2x HSIC: hsic-0, hsic-1
251−- 2x super-speed USB: usb3-0, usb3-1
252−
253−For Tegra210, the XUSB pad controller exposes the following ports:
254−- 4x USB2: usb2-0, usb2-1, usb2-2, usb2-3
255−- 2x HSIC: hsic-0, hsic-1
256−- 4x super-speed USB: usb3-0, usb3-1, usb3-2, usb3-3
257−
258−For Tegra194, the XUSB pad controller exposes the following ports:
259−- 4x USB2: usb2-0, usb2-1, usb2-2, usb2-3
260−- 4x super-speed USB: usb3-0, usb3-1, usb3-2, usb3-3
261−
262−Examples:
263−=========
264−
265−Tegra124 and Tegra132:
266−----------------------
267−
268−SoC include:
269−
270− padctl@7009f000 {
271− /* for Tegra124 */
272− compatible = "nvidia,tegra124-xusb-padctl";
273− /* for Tegra132 */
274− compatible = "nvidia,tegra132-xusb-padctl",
275− "nvidia,tegra124-xusb-padctl";
276− reg = <0x0 0x7009f000 0x0 0x1000>;
277− resets = <&tegra_car 142>;
278− reset-names = "padctl";
279−
280− pads {
281− usb2 {
282− status = "disabled";
283−
284− lanes {
285− usb2-0 {
286− status = "disabled";
287− #phy-cells = <0>;
288− };
289−
290− usb2-1 {
291− status = "disabled";
292− #phy-cells = <0>;
293− };
294−
295− usb2-2 {
296− status = "disabled";
297− #phy-cells = <0>;
298− };
299− };
300− };
301−
302− ulpi {
303− status = "disabled";
304−
305− lanes {
306− ulpi-0 {
307− status = "disabled";
308− #phy-cells = <0>;
309− };
310− };
311− };
312−
313− hsic {
314− status = "disabled";
315−
316− lanes {
317− hsic-0 {
318− status = "disabled";
319− #phy-cells = <0>;
320− };
321−
322− hsic-1 {
323− status = "disabled";
324− #phy-cells = <0>;
325− };
326− };
327− };
328−
329− pcie {
330− status = "disabled";
331−
332− lanes {
333− pcie-0 {
334− status = "disabled";
335− #phy-cells = <0>;
336− };
337−
338− pcie-1 {
339− status = "disabled";
340− #phy-cells = <0>;
341− };
342−
343− pcie-2 {
344− status = "disabled";
345− #phy-cells = <0>;
346− };
347−
348− pcie-3 {
349− status = "disabled";
350− #phy-cells = <0>;
351− };
352−
353− pcie-4 {
354− status = "disabled";
355− #phy-cells = <0>;
356− };
357− };
358− };
359−
360− sata {
361− status = "disabled";
362−
363− lanes {
364− sata-0 {
365− status = "disabled";
366− #phy-cells = <0>;
367− };
368− };
369− };
370− };
371−
372− ports {
373− usb2-0 {
374− status = "disabled";
375− };
376−
377− usb2-1 {
378− status = "disabled";
379− };
380−
381− usb2-2 {
382− status = "disabled";
383− };
384−
385− ulpi-0 {
386− status = "disabled";
387− };
388−
389− hsic-0 {
390− status = "disabled";
391− };
392−
393− hsic-1 {
394− status = "disabled";
395− };
396−
397− usb3-0 {
398− status = "disabled";
399− };
400−
401− usb3-1 {
402− status = "disabled";
403− };
404− };
405− };
406−
407−Board file:
408−
409− padctl@7009f000 {
410− status = "okay";
411−
412− pads {
413− usb2 {
414− status = "okay";
415−
416− lanes {
417− usb2-0 {
418− nvidia,function = "xusb";
419− status = "okay";
420− };
421−
422− usb2-1 {
423− nvidia,function = "xusb";
424− status = "okay";
425− };
426−
427− usb2-2 {
428− nvidia,function = "xusb";
429− status = "okay";
430− };
431− };
432− };
433−
434− pcie {
435− status = "okay";
436−
437− lanes {
438− pcie-0 {
439− nvidia,function = "usb3-ss";
440− status = "okay";
441− };
442−
443− pcie-2 {
444− nvidia,function = "pcie";
445− status = "okay";
446− };
447−
448− pcie-4 {
449− nvidia,function = "pcie";
450− status = "okay";
451− };
452− };
453− };
454−
455− sata {
456− status = "okay";
457−
458− lanes {
459− sata-0 {
460− nvidia,function = "sata";
461− status = "okay";
462− };
463− };
464− };
465− };
466−
467− ports {
468− /* Micro A/B */
469− usb2-0 {
470− status = "okay";
471− mode = "otg";
472− };
473−
474− /* Mini PCIe */
475− usb2-1 {
476− status = "okay";
477− mode = "host";
478− };
479−
480− /* USB3 */
481− usb2-2 {
482− status = "okay";
483− mode = "host";
484−
485− vbus-supply = <&vdd_usb3_vbus>;
486− };
487−
488− usb3-0 {
489− nvidia,port = <2>;
490− status = "okay";
491− };
492− };
493− };
494−
495−Tegra210:
496−---------
497−
498−SoC include:
499−
500− padctl@7009f000 {
501− compatible = "nvidia,tegra210-xusb-padctl";
502− reg = <0x0 0x7009f000 0x0 0x1000>;
503− resets = <&tegra_car 142>;
504− reset-names = "padctl";
505−
506− status = "disabled";
507−
508− pads {
509− usb2 {
510− clocks = <&tegra_car TEGRA210_CLK_USB2_TRK>;
511− clock-names = "trk";
512− status = "disabled";
513−
514− lanes {
515− usb2-0 {
516− status = "disabled";
517− #phy-cells = <0>;
518− };
519−
520− usb2-1 {
521− status = "disabled";
522− #phy-cells = <0>;
523− };
524−
525− usb2-2 {
526− status = "disabled";
527− #phy-cells = <0>;
528− };
529−
530− usb2-3 {
531− status = "disabled";
532− #phy-cells = <0>;
533− };
534− };
535− };
536−
537− hsic {
538− clocks = <&tegra_car TEGRA210_CLK_HSIC_TRK>;
539− clock-names = "trk";
540− status = "disabled";
541−
542− lanes {
543− hsic-0 {
544− status = "disabled";
545− #phy-cells = <0>;
546− };
547−
548− hsic-1 {
549− status = "disabled";
550− #phy-cells = <0>;
551− };
552− };
553− };
554−
555− pcie {
556− clocks = <&tegra_car TEGRA210_CLK_PLL_E>;
557− clock-names = "pll";
558− resets = <&tegra_car 205>;
559− reset-names = "phy";
560− status = "disabled";
561−
562− lanes {
563− pcie-0 {
564− status = "disabled";
565− #phy-cells = <0>;
566− };
567−
568− pcie-1 {
569− status = "disabled";
570− #phy-cells = <0>;
571− };
572−
573− pcie-2 {
574− status = "disabled";
575− #phy-cells = <0>;
576− };
577−
578− pcie-3 {
579− status = "disabled";
580− #phy-cells = <0>;
581− };
582−
583− pcie-4 {
584− status = "disabled";
585− #phy-cells = <0>;
586− };
587−
588− pcie-5 {
589− status = "disabled";
590− #phy-cells = <0>;
591− };
592−
593− pcie-6 {
594− status = "disabled";
595− #phy-cells = <0>;
596− };
597− };
598− };
599−
600− sata {
601− clocks = <&tegra_car TEGRA210_CLK_PLL_E>;
602− clock-names = "pll";
603− resets = <&tegra_car 204>;
604− reset-names = "phy";
605− status = "disabled";
606−
607− lanes {
608− sata-0 {
609− status = "disabled";
610− #phy-cells = <0>;
611− };
612− };
613− };
614− };
615−
616− ports {
617− usb2-0 {
618− status = "disabled";
619− };
620−
621− usb2-1 {
622− status = "disabled";
623− };
624−
625− usb2-2 {
626− status = "disabled";
627− };
628−
629− usb2-3 {
630− status = "disabled";
631− };
632−
633− hsic-0 {
634− status = "disabled";
635− };
636−
637− hsic-1 {
638− status = "disabled";
639− };
640−
641− usb3-0 {
642− status = "disabled";
643− };
644−
645− usb3-1 {
646− status = "disabled";
647− };
648−
649− usb3-2 {
650− status = "disabled";
651− };
652−
653− usb3-3 {
654− status = "disabled";
655− };
656− };
657− };
658−
659−Board file:
660−
661− padctl@7009f000 {
662− status = "okay";
663−
664− pads {
665− usb2 {
666− status = "okay";
667−
668− lanes {
669− usb2-0 {
670− nvidia,function = "xusb";
671− status = "okay";
672− };
673−
674− usb2-1 {
675− nvidia,function = "xusb";
676− status = "okay";
677− };
678−
679− usb2-2 {
680− nvidia,function = "xusb";
681− status = "okay";
682− };
683−
684− usb2-3 {
685− nvidia,function = "xusb";
686− status = "okay";
687− };
688− };
689− };
690−
691− pcie {
692− status = "okay";
693−
694− lanes {
695− pcie-0 {
696− nvidia,function = "pcie-x1";
697− status = "okay";
698− };
699−
700− pcie-1 {
701− nvidia,function = "pcie-x4";
702− status = "okay";
703− };
704−
705− pcie-2 {
706− nvidia,function = "pcie-x4";
707− status = "okay";
708− };
709−
710− pcie-3 {
711− nvidia,function = "pcie-x4";
712− status = "okay";
713− };
714−
715− pcie-4 {
716− nvidia,function = "pcie-x4";
717− status = "okay";
718− };
719−
720− pcie-5 {
721− nvidia,function = "usb3-ss";
722− status = "okay";
723− };
724−
725− pcie-6 {
726− nvidia,function = "usb3-ss";
727− status = "okay";
728− };
729− };
730− };
731−
732− sata {
733− status = "okay";
734−
735− lanes {
736− sata-0 {
737− nvidia,function = "sata";
738− status = "okay";
739− };
740− };
741− };
742− };
743−
744− ports {
745− usb2-0 {
746− status = "okay";
747− mode = "otg";
748− };
749−
750− usb2-1 {
751− status = "okay";
752− vbus-supply = <&vdd_5v0_rtl>;
753− mode = "host";
754− };
755−
756− usb2-2 {
757− status = "okay";
758− vbus-supply = <&vdd_usb_vbus>;
759− mode = "host";
760− };
761−
762− usb2-3 {
763− status = "okay";
764− mode = "host";
765− };
766−
767− usb3-0 {
768− status = "okay";
769− nvidia,lanes = "pcie-6";
770− nvidia,port = <1>;
771− };
772−
773− usb3-1 {
774− status = "okay";
775− nvidia,lanes = "pcie-5";
776− nvidia,port = <2>;
777− };
778− };
779− };
Documentation/devicetree/bindings/phy/nvidia,tegra124-xusb-padctl.yaml+654−0
@@ -0,0 +1,654 @@
1+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
2+%YAML 1.2
3+---
4+$id: http://devicetree.org/schemas/phy/nvidia,tegra124-xusb-padctl.yaml#
5+$schema: http://devicetree.org/meta-schemas/core.yaml#
6+
7+title: NVIDIA Tegra124 XUSB pad controller
8+
9+maintainers:
10+ - Thierry Reding <thierry.reding@gmail.com>
11+ - Jon Hunter <jonathanh@nvidia.com>
12+
13+description: |
14+ The Tegra XUSB pad controller manages a set of I/O lanes (with differential
15+ signals) which connect directly to pins/pads on the SoC package. Each lane
16+ is controlled by a HW block referred to as a "pad" in the Tegra hardware
17+ documentation. Each such "pad" may control either one or multiple lanes,
18+ and thus contains any logic common to all its lanes. Each lane can be
19+ separately configured and powered up.
20+
21+ Some of the lanes are high-speed lanes, which can be used for PCIe, SATA or
22+ super-speed USB. Other lanes are for various types of low-speed, full-speed
23+ or high-speed USB (such as UTMI, ULPI and HSIC). The XUSB pad controller
24+ contains a software-configurable mux that sits between the I/O controller
25+ ports (e.g. PCIe) and the lanes.
26+
27+ In addition to per-lane configuration, USB 3.0 ports may require additional
28+ settings on a per-board basis.
29+
30+ Pads will be represented as children of the top-level XUSB pad controller
31+ device tree node. Each lane exposed by the pad will be represented by its
32+ own subnode and can be referenced by users of the lane using the standard
33+ PHY bindings, as described by the phy-bindings.txt file in this directory.
34+
35+ The Tegra hardware documentation refers to the connection between the XUSB
36+ pad controller and the XUSB controller as "ports". This is confusing since
37+ "port" is typically used to denote the physical USB receptacle. The device
38+ tree binding in this document uses the term "port" to refer to the logical
39+ abstraction of the signals that are routed to a USB receptacle (i.e. a PHY
40+ for the USB signal, the VBUS power supply, the USB 2.0 companion port for
41+ USB 3.0 receptacles, ...).
42+
43+properties:
44+ compatible:
45+ oneOf:
46+ - enum:
47+ - nvidia,tegra124-xusb-padctl
48+
49+ - items:
50+ - const: nvidia,tegra132-xusb-padctl
51+ - const: nvidia,tegra124-xusb-padctl
52+
53+ reg:
54+ maxItems: 1
55+
56+ interrupts:
57+ items:
58+ - description: XUSB pad controller interrupt
59+
60+ resets:
61+ items:
62+ - description: pad controller reset
63+
64+ reset-names:
65+ items:
66+ - const: padctl
67+
68+ avdd-pll-utmip-supply:
69+ description: UTMI PLL power supply. Must supply 1.8 V.
70+
71+ avdd-pll-erefe-supply:
72+ description: PLLE reference PLL power supply. Must supply 1.05 V.
73+
74+ avdd-pex-pll-supply:
75+ description: PCIe/USB3 PLL power supply. Must supply 1.05 V.
76+
77+ hvdd-pex-pll-e-supply:
78+ description: High-voltage PLLE power supply. Must supply 3.3 V.
79+
80+ pads:
81+ description: A required child node named "pads" contains a list of
82+ subnodes, one for each of the pads exposed by the XUSB pad controller.
83+ Each pad may need additional resources that can be referenced in its
84+ pad node.
85+
86+ The "status" property is used to enable or disable the use of a pad.
87+ If set to "disabled", the pad will not be used on the given board. In
88+ order to use the pad and any of its lanes, this property must be set
89+ to "okay" or be absent.
90+ type: object
91+ additionalProperties: false
92+ properties:
93+ usb2:
94+ type: object
95+ additionalProperties: false
96+ properties:
97+ clocks:
98+ items:
99+ - description: USB2 tracking clock
100+
101+ clock-names:
102+ items:
103+ - const: trk
104+
105+ lanes:
106+ type: object
107+ additionalProperties: false
108+ properties:
109+ usb2-0:
110+ type: object
111+ additionalProperties: false
112+ properties:
113+ "#phy-cells":
114+ const: 0
115+
116+ nvidia,function:
117+ description: Function selection for this lane.
118+ $ref: /schemas/types.yaml#/definitions/string
119+ enum: [ snps, xusb, uart ]
120+
121+ usb2-1:
122+ type: object
123+ additionalProperties: false
124+ properties:
125+ "#phy-cells":
126+ const: 0
127+
128+ nvidia,function:
129+ description: Function selection for this lane.
130+ $ref: /schemas/types.yaml#/definitions/string
131+ enum: [ snps, xusb, uart ]
132+
133+ usb2-2:
134+ type: object
135+ additionalProperties: false
136+ properties:
137+ "#phy-cells":
138+ const: 0
139+
140+ nvidia,function:
141+ description: Function selection for this lane.
142+ $ref: /schemas/types.yaml#/definitions/string
143+ enum: [ snps, xusb, uart ]
144+
145+ ulpi:
146+ type: object
147+ additionalProperties: false
148+ properties:
149+ lanes:
150+ type: object
151+ additionalProperties: false
152+ properties:
153+ ulpi-0:
154+ type: object
155+ additionalProperties: false
156+ properties:
157+ "#phy-cells":
158+ const: 0
159+
160+ nvidia,function:
161+ description: Function selection for this lane.
162+ $ref: /schemas/types.yaml#/definitions/string
163+ enum: [ snps, xusb ]
164+
165+ hsic:
166+ type: object
167+ additionalProperties: false
168+ properties:
169+ clocks:
170+ items:
171+ - description: HSIC tracking clock
172+
173+ clock-names:
174+ items:
175+ - const: trk
176+
177+ lanes:
178+ type: object
179+ additionalProperties: false
180+ properties:
181+ hsic-0:
182+ type: object
183+ additionalProperties: false
184+ properties:
185+ "#phy-cells":
186+ const: 0
187+
188+ nvidia,function:
189+ description: Function selection for this lane.
190+ $ref: /schemas/types.yaml#/definitions/string
191+ enum: [ snps, xusb ]
192+
193+ hsic-1:
194+ type: object
195+ additionalProperties: false
196+ properties:
197+ "#phy-cells":
198+ const: 0
199+
200+ nvidia,function:
201+ description: Function selection for this lane.
202+ $ref: /schemas/types.yaml#/definitions/string
203+ enum: [ snps, xusb ]
204+
205+ pcie:
206+ type: object
207+ additionalProperties: false
208+ properties:
209+ clocks:
210+ items:
211+ - description: PLLE clock
212+
213+ clock-names:
214+ items:
215+ - const: pll
216+
217+ resets:
218+ items:
219+ - description: reset for the PCIe UPHY block
220+
221+ reset-names:
222+ items:
223+ - const: phy
224+
225+ lanes:
226+ type: object
227+ additionalProperties: false
228+ properties:
229+ pcie-0:
230+ type: object
231+ additionalProperties: false
232+ properties:
233+ "#phy-cells":
234+ const: 0
235+
236+ nvidia,function:
237+ description: Function selection for this lane.
238+ $ref: /schemas/types.yaml#/definitions/string
239+ enum: [ pcie, usb3-ss ]
240+
241+ pcie-1:
242+ type: object
243+ additionalProperties: false
244+ properties:
245+ "#phy-cells":
246+ const: 0
247+
248+ nvidia,function:
249+ description: Function selection for this lane.
250+ $ref: /schemas/types.yaml#/definitions/string
251+ enum: [ pcie, usb3-ss ]
252+
253+ pcie-2:
254+ type: object
255+ additionalProperties: false
256+ properties:
257+ "#phy-cells":
258+ const: 0
259+
260+ nvidia,function:
261+ description: Function selection for this lane.
262+ $ref: /schemas/types.yaml#/definitions/string
263+ enum: [ pcie, usb3-ss ]
264+
265+ pcie-3:
266+ type: object
267+ additionalProperties: false
268+ properties:
269+ "#phy-cells":
270+ const: 0
271+
272+ nvidia,function:
273+ description: Function selection for this lane.
274+ $ref: /schemas/types.yaml#/definitions/string
275+ enum: [ pcie, usb3-ss ]
276+
277+ pcie-4:
278+ type: object
279+ additionalProperties: false
280+ properties:
281+ "#phy-cells":
282+ const: 0
283+
284+ nvidia,function:
285+ description: Function selection for this lane.
286+ $ref: /schemas/types.yaml#/definitions/string
287+ enum: [ pcie, usb3-ss ]
288+
289+ sata:
290+ type: object
291+ additionalProperties: false
292+ properties:
293+ resets:
294+ items:
295+ - description: reset for the SATA UPHY block
296+
297+ reset-names:
298+ items:
299+ - const: phy
300+
301+ lanes:
302+ type: object
303+ additionalProperties: false
304+ properties:
305+ sata-0:
306+ type: object
307+ additionalProperties: false
308+ properties:
309+ "#phy-cells":
310+ const: 0
311+
312+ nvidia,function:
313+ description: Function selection for this lane.
314+ $ref: /schemas/types.yaml#/definitions/string
315+ enum: [ sata, usb3-ss ]
316+
317+ ports:
318+ description: A required child node named "ports" contains a list of
319+ subnodes, one for each of the ports exposed by the XUSB pad controller.
320+ Each port may need additional resources that can be referenced in its
321+ port node.
322+
323+ The "status" property is used to enable or disable the use of a port.
324+ If set to "disabled", the port will not be used on the given board. In
325+ order to use the port, this property must be set to "okay".
326+ type: object
327+ additionalProperties: false
328+ properties:
329+ usb2-0:
330+ type: object
331+ additionalProperties: false
332+ properties:
333+ # no need to further describe this because the connector will
334+ # match on gpio-usb-b-connector or usb-b-connector and cause
335+ # that binding to be selected for the subnode
336+ connector:
337+ type: object
338+
339+ mode:
340+ description: A string that determines the mode in which to
341+ run the port.
342+ $ref: /schemas/types.yaml#/definitions/string
343+ enum: [ host, peripheral, otg ]
344+
345+ nvidia,internal:
346+ description: A boolean property whose presence determines
347+ that a port is internal. In the absence of this property
348+ the port is considered to be external.
349+ $ref: /schemas/types.yaml#/definitions/flag
350+
351+ usb-role-switch:
352+ description: |
353+ A boolean property whole presence indicates that the port
354+ supports OTG or peripheral mode. If present, the port
355+ supports switching between USB host and peripheral roles.
356+ A connector must be added as a subnode in that case.
357+
358+ See ../connector/usb-connector.yaml.
359+
360+ vbus-supply:
361+ description: A phandle to the regulator supplying the VBUS
362+ voltage.
363+
364+ usb2-1:
365+ type: object
366+ additionalProperties: false
367+ properties:
368+ # no need to further describe this because the connector will
369+ # match on gpio-usb-b-connector or usb-b-connector and cause
370+ # that binding to be selected for the subnode
371+ connector:
372+ type: object
373+
374+ mode:
375+ description: A string that determines the mode in which to
376+ run the port.
377+ $ref: /schemas/types.yaml#/definitions/string
378+ enum: [ host, peripheral, otg ]
379+
380+ nvidia,internal:
381+ description: A boolean property whose presence determines
382+ that a port is internal. In the absence of this property
383+ the port is considered to be external.
384+ $ref: /schemas/types.yaml#/definitions/flag
385+
386+ usb-role-switch:
387+ description: |
388+ A boolean property whole presence indicates that the port
389+ supports OTG or peripheral mode. If present, the port
390+ supports switching between USB host and peripheral roles.
391+ A connector must be added as a subnode in that case.
392+
393+ See ../connector/usb-connector.yaml.
394+
395+ vbus-supply:
396+ description: A phandle to the regulator supplying the VBUS
397+ voltage.
398+
399+ usb2-2:
400+ type: object
401+ additionalProperties: false
402+ properties:
403+ # no need to further describe this because the connector will
404+ # match on gpio-usb-b-connector or usb-b-connector and cause
405+ # that binding to be selected for the subnode
406+ connector:
407+ type: object
408+
409+ mode:
410+ description: A string that determines the mode in which to
411+ run the port.
412+ $ref: /schemas/types.yaml#/definitions/string
413+ enum: [ host, peripheral, otg ]
414+
415+ nvidia,internal:
416+ description: A boolean property whose presence determines
417+ that a port is internal. In the absence of this property
418+ the port is considered to be external.
419+ $ref: /schemas/types.yaml#/definitions/flag
420+
421+ usb-role-switch:
422+ description: |
423+ A boolean property whole presence indicates that the port
424+ supports OTG or peripheral mode. If present, the port
425+ supports switching between USB host and peripheral roles.
426+ A connector must be added as a subnode in that case.
427+
428+ See ../connector/usb-connector.yaml.
429+
430+ vbus-supply:
431+ description: A phandle to the regulator supplying the VBUS
432+ voltage.
433+
434+ ulpi-0:
435+ type: object
436+ additionalProperties: false
437+ properties:
438+ nvidia,internal:
439+ description: A boolean property whose presence determines
440+ that a port is internal. In the absence of this property
441+ the port is considered to be external.
442+ $ref: /schemas/types.yaml#/definitions/flag
443+
444+ vbus-supply:
445+ description: A phandle to the regulator supplying the VBUS
446+ voltage.
447+
448+ hsic-0:
449+ type: object
450+ additionalProperties: false
451+ properties:
452+ vbus-supply:
453+ description: A phandle to the regulator supplying the VBUS
454+ voltage.
455+
456+ hsic-1:
457+ type: object
458+ additionalProperties: false
459+ properties:
460+ vbus-supply:
461+ description: A phandle to the regulator supplying the VBUS
462+ voltage.
463+
464+ usb3-0:
465+ type: object
466+ additionalProperties: false
467+ properties:
468+ nvidia,internal:
469+ description: A boolean property whose presence determines
470+ that a port is internal. In the absence of this property
471+ the port is considered to be external.
472+ $ref: /schemas/types.yaml#/definitions/flag
473+
474+ nvidia,usb2-companion:
475+ description: A single cell that specifies the physical port
476+ number to map this super-speed USB port to. The range of
477+ valid port numbers varies with the SoC generation.
478+ $ref: /schemas/types.yaml#/definitions/uint32
479+ enum: [ 0, 1, 2 ]
480+
481+ vbus-supply:
482+ description: A phandle to the regulator supplying the VBUS
483+ voltage.
484+
485+ usb3-1:
486+ type: object
487+ additionalProperties: false
488+ properties:
489+ nvidia,internal:
490+ description: A boolean property whose presence determines
491+ that a port is internal. In the absence of this property
492+ the port is considered to be external.
493+ $ref: /schemas/types.yaml#/definitions/flag
494+
495+ nvidia,usb2-companion:
496+ description: A single cell that specifies the physical port
497+ number to map this super-speed USB port to. The range of
498+ valid port numbers varies with the SoC generation.
499+ $ref: /schemas/types.yaml#/definitions/uint32
500+ enum: [ 0, 1, 2 ]
501+
502+ vbus-supply:
503+ description: A phandle to the regulator supplying the VBUS
504+ voltage.
505+
506+additionalProperties: false
507+
508+required:
509+ - compatible
510+ - reg
511+ - resets
512+ - reset-names
513+ - avdd-pll-utmip-supply
514+ - avdd-pll-erefe-supply
515+ - avdd-pex-pll-supply
516+ - hvdd-pex-pll-e-supply
517+
518+examples:
519+ # Tegra124 and Tegra132
520+ - |
521+ #include <dt-bindings/interrupt-controller/arm-gic.h>
522+
523+ padctl@7009f000 {
524+ compatible = "nvidia,tegra124-xusb-padctl";
525+ reg = <0x7009f000 0x1000>;
526+ interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
527+ resets = <&tegra_car 142>;
528+ reset-names = "padctl";
529+
530+ avdd-pll-utmip-supply = <&vddio_1v8>;
531+ avdd-pll-erefe-supply = <&avdd_1v05_run>;
532+ avdd-pex-pll-supply = <&vdd_1v05_run>;
533+ hvdd-pex-pll-e-supply = <&vdd_3v3_lp0>;
534+
535+ pads {
536+ usb2 {
537+ lanes {
538+ usb2-0 {
539+ nvidia,function = "xusb";
540+ #phy-cells = <0>;
541+ };
542+
543+ usb2-1 {
544+ nvidia,function = "xusb";
545+ #phy-cells = <0>;
546+ };
547+
548+ usb2-2 {
549+ nvidia,function = "xusb";
550+ #phy-cells = <0>;
551+ };
552+ };
553+ };
554+
555+ ulpi {
556+ lanes {
557+ ulpi-0 {
558+ status = "disabled";
559+ #phy-cells = <0>;
560+ };
561+ };
562+ };
563+
564+ hsic {
565+ lanes {
566+ hsic-0 {
567+ status = "disabled";
568+ #phy-cells = <0>;
569+ };
570+
571+ hsic-1 {
572+ status = "disabled";
573+ #phy-cells = <0>;
574+ };
575+ };
576+ };
577+
578+ pcie {
579+ lanes {
580+ pcie-0 {
581+ nvidia,function = "usb3-ss";
582+ #phy-cells = <0>;
583+ };
584+
585+ pcie-1 {
586+ status = "disabled";
587+ #phy-cells = <0>;
588+ };
589+
590+ pcie-2 {
591+ nvidia,function = "pcie";
592+ #phy-cells = <0>;
593+ };
594+
595+ pcie-3 {
596+ status = "disabled";
597+ #phy-cells = <0>;
598+ };
599+
600+ pcie-4 {
601+ nvidia,function = "pcie";
602+ #phy-cells = <0>;
603+ };
604+ };
605+ };
606+
607+ sata {
608+ lanes {
609+ sata-0 {
610+ nvidia,function = "sata";
611+ #phy-cells = <0>;
612+ };
613+ };
614+ };
615+ };
616+
617+ ports {
618+ /* Micro A/B */
619+ usb2-0 {
620+ mode = "otg";
621+ };
622+
623+ /* Mini PCIe */
624+ usb2-1 {
625+ mode = "host";
626+ };
627+
628+ /* USB3 */
629+ usb2-2 {
630+ vbus-supply = <&vdd_usb3_vbus>;
631+ mode = "host";
632+ };
633+
634+ ulpi-0 {
635+ status = "disabled";
636+ };
637+
638+ hsic-0 {
639+ status = "disabled";
640+ };
641+
642+ hsic-1 {
643+ status = "disabled";
644+ };
645+
646+ usb3-0 {
647+ nvidia,usb2-companion = <2>;
648+ };
649+
650+ usb3-1 {
651+ status = "disabled";
652+ };
653+ };
654+ };
Documentation/devicetree/bindings/phy/nvidia,tegra186-xusb-padctl.yaml+544−0
@@ -0,0 +1,544 @@
1+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
2+%YAML 1.2
3+---
4+$id: http://devicetree.org/schemas/phy/nvidia,tegra186-xusb-padctl.yaml#
5+$schema: http://devicetree.org/meta-schemas/core.yaml#
6+
7+title: NVIDIA Tegra186 XUSB pad controller
8+
9+maintainers:
10+ - Thierry Reding <thierry.reding@gmail.com>
11+ - Jon Hunter <jonathanh@nvidia.com>
12+
13+description: |
14+ The Tegra XUSB pad controller manages a set of I/O lanes (with differential
15+ signals) which connect directly to pins/pads on the SoC package. Each lane
16+ is controlled by a HW block referred to as a "pad" in the Tegra hardware
17+ documentation. Each such "pad" may control either one or multiple lanes,
18+ and thus contains any logic common to all its lanes. Each lane can be
19+ separately configured and powered up.
20+
21+ Some of the lanes are high-speed lanes, which can be used for PCIe, SATA or
22+ super-speed USB. Other lanes are for various types of low-speed, full-speed
23+ or high-speed USB (such as UTMI, ULPI and HSIC). The XUSB pad controller
24+ contains a software-configurable mux that sits between the I/O controller
25+ ports (e.g. PCIe) and the lanes.
26+
27+ In addition to per-lane configuration, USB 3.0 ports may require additional
28+ settings on a per-board basis.
29+
30+ Pads will be represented as children of the top-level XUSB pad controller
31+ device tree node. Each lane exposed by the pad will be represented by its
32+ own subnode and can be referenced by users of the lane using the standard
33+ PHY bindings, as described by the phy-bindings.txt file in this directory.
34+
35+ The Tegra hardware documentation refers to the connection between the XUSB
36+ pad controller and the XUSB controller as "ports". This is confusing since
37+ "port" is typically used to denote the physical USB receptacle. The device
38+ tree binding in this document uses the term "port" to refer to the logical
39+ abstraction of the signals that are routed to a USB receptacle (i.e. a PHY
40+ for the USB signal, the VBUS power supply, the USB 2.0 companion port for
41+ USB 3.0 receptacles, ...).
42+
43+properties:
44+ compatible:
45+ const: nvidia,tegra186-xusb-padctl
46+
47+ reg:
48+ items:
49+ - description: pad controller registers
50+ - description: AO registers
51+
52+ interrupts:
53+ items:
54+ - description: XUSB pad controller interrupt
55+
56+ reg-names:
57+ items:
58+ - const: padctl
59+ - const: ao
60+
61+ resets:
62+ items:
63+ - description: pad controller reset
64+
65+ reset-names:
66+ items:
67+ - const: padctl
68+
69+ avdd-pll-erefeut-supply:
70+ description: UPHY brick and reference clock as well as UTMI PHY
71+ power supply. Must supply 1.8 V.
72+
73+ avdd-usb-supply:
74+ description: USB I/Os, VBUS, ID, REXT, D+/D- power supply. Must
75+ supply 3.3 V.
76+
77+ vclamp-usb-supply:
78+ description: Bias rail for USB pad. Must supply 1.8 V.
79+
80+ vddio-hsic-supply:
81+ description: HSIC PHY power supply. Must supply 1.2 V.
82+
83+ pads:
84+ description: A required child node named "pads" contains a list of
85+ subnodes, one for each of the pads exposed by the XUSB pad controller.
86+ Each pad may need additional resources that can be referenced in its
87+ pad node.
88+
89+ The "status" property is used to enable or disable the use of a pad.
90+ If set to "disabled", the pad will not be used on the given board. In
91+ order to use the pad and any of its lanes, this property must be set
92+ to "okay" or be absent.
93+ type: object
94+ additionalProperties: false
95+ properties:
96+ usb2:
97+ type: object
98+ additionalProperties: false
99+ properties:
100+ clocks:
101+ items:
102+ - description: USB2 tracking clock
103+
104+ clock-names:
105+ items:
106+ - const: trk
107+
108+ lanes:
109+ type: object
110+ additionalProperties: false
111+ properties:
112+ usb2-0:
113+ type: object
114+ additionalProperties: false
115+ properties:
116+ "#phy-cells":
117+ const: 0
118+
119+ nvidia,function:
120+ description: Function selection for this lane.
121+ $ref: /schemas/types.yaml#/definitions/string
122+ enum: [ xusb ]
123+
124+ usb2-1:
125+ type: object
126+ additionalProperties: false
127+ properties:
128+ "#phy-cells":
129+ const: 0
130+
131+ nvidia,function:
132+ description: Function selection for this lane.
133+ $ref: /schemas/types.yaml#/definitions/string
134+ enum: [ xusb ]
135+
136+ usb2-2:
137+ type: object
138+ additionalProperties: false
139+ properties:
140+ "#phy-cells":
141+ const: 0
142+
143+ nvidia,function:
144+ description: Function selection for this lane.
145+ $ref: /schemas/types.yaml#/definitions/string
146+ enum: [ xusb ]
147+
148+ hsic:
149+ type: object
150+ additionalProperties: false
151+ properties:
152+ clocks:
153+ items:
154+ - description: HSIC tracking clock
155+
156+ clock-names:
157+ items:
158+ - const: trk
159+
160+ lanes:
161+ type: object
162+ additionalProperties: false
163+ properties:
164+ hsic-0:
165+ type: object
166+ additionalProperties: false
167+ properties:
168+ "#phy-cells":
169+ const: 0
170+
171+ nvidia,function:
172+ description: Function selection for this lane.
173+ $ref: /schemas/types.yaml#/definitions/string
174+ enum: [ xusb ]
175+
176+ usb3:
177+ type: object
178+ additionalProperties: false
179+ properties:
180+ lanes:
181+ type: object
182+ additionalProperties: false
183+ properties:
184+ usb3-0:
185+ type: object
186+ additionalProperties: false
187+ properties:
188+ "#phy-cells":
189+ const: 0
190+
191+ nvidia,function:
192+ description: Function selection for this lane.
193+ $ref: /schemas/types.yaml#/definitions/string
194+ enum: [ xusb ]
195+
196+ usb3-1:
197+ type: object
198+ additionalProperties: false
199+ properties:
200+ "#phy-cells":
201+ const: 0
202+
203+ nvidia,function:
204+ description: Function selection for this lane.
205+ $ref: /schemas/types.yaml#/definitions/string
206+ enum: [ xusb ]
207+
208+ usb3-2:
209+ type: object
210+ additionalProperties: false
211+ properties:
212+ "#phy-cells":
213+ const: 0
214+
215+ nvidia,function:
216+ description: Function selection for this lane.
217+ $ref: /schemas/types.yaml#/definitions/string
218+ enum: [ xusb ]
219+
220+ ports:
221+ description: A required child node named "ports" contains a list of
222+ subnodes, one for each of the ports exposed by the XUSB pad controller.
223+ Each port may need additional resources that can be referenced in its
224+ port node.
225+
226+ The "status" property is used to enable or disable the use of a port.
227+ If set to "disabled", the port will not be used on the given board. In
228+ order to use the port, this property must be set to "okay".
229+ type: object
230+ additionalProperties: false
231+ properties:
232+ usb2-0:
233+ type: object
234+ additionalProperties: false
235+ properties:
236+ # no need to further describe this because the connector will
237+ # match on gpio-usb-b-connector or usb-b-connector and cause
238+ # that binding to be selected for the subnode
239+ connector:
240+ type: object
241+
242+ mode:
243+ description: A string that determines the mode in which to
244+ run the port.
245+ $ref: /schemas/types.yaml#/definitions/string
246+ enum: [ host, peripheral, otg ]
247+
248+ nvidia,internal:
249+ description: A boolean property whose presence determines
250+ that a port is internal. In the absence of this property
251+ the port is considered to be external.
252+ $ref: /schemas/types.yaml#/definitions/flag
253+
254+ usb-role-switch:
255+ description: |
256+ A boolean property whole presence indicates that the port
257+ supports OTG or peripheral mode. If present, the port
258+ supports switching between USB host and peripheral roles.
259+ A connector must be added as a subnode in that case.
260+
261+ See ../connector/usb-connector.yaml.
262+
263+ vbus-supply:
264+ description: A phandle to the regulator supplying the VBUS
265+ voltage.
266+
267+ dependencies:
268+ usb-role-switch: [ connector ]
269+
270+ usb2-1:
271+ type: object
272+ additionalProperties: false
273+ properties:
274+ # no need to further describe this because the connector will
275+ # match on gpio-usb-b-connector or usb-b-connector and cause
276+ # that binding to be selected for the subnode
277+ connector:
278+ type: object
279+
280+ mode:
281+ description: A string that determines the mode in which to
282+ run the port.
283+ $ref: /schemas/types.yaml#/definitions/string
284+ enum: [ host, peripheral, otg ]
285+
286+ nvidia,internal:
287+ description: A boolean property whose presence determines
288+ that a port is internal. In the absence of this property
289+ the port is considered to be external.
290+ $ref: /schemas/types.yaml#/definitions/flag
291+
292+ usb-role-switch:
293+ description: |
294+ A boolean property whole presence indicates that the port
295+ supports OTG or peripheral mode. If present, the port
296+ supports switching between USB host and peripheral roles.
297+ A connector must be added as a subnode in that case.
298+
299+ See ../connector/usb-connector.yaml.
300+
301+ vbus-supply:
302+ description: A phandle to the regulator supplying the VBUS
303+ voltage.
304+
305+ dependencies:
306+ usb-role-switch: [ connector ]
307+
308+ usb2-2:
309+ type: object
310+ additionalProperties: false
311+ properties:
312+ # no need to further describe this because the connector will
313+ # match on gpio-usb-b-connector or usb-b-connector and cause
314+ # that binding to be selected for the subnode
315+ connector:
316+ type: object
317+
318+ mode:
319+ description: A string that determines the mode in which to
320+ run the port.
321+ $ref: /schemas/types.yaml#/definitions/string
322+ enum: [ host, peripheral, otg ]
323+
324+ nvidia,internal:
325+ description: A boolean property whose presence determines
326+ that a port is internal. In the absence of this property
327+ the port is considered to be external.
328+ $ref: /schemas/types.yaml#/definitions/flag
329+
330+ usb-role-switch:
331+ description: |
332+ A boolean property whole presence indicates that the port
333+ supports OTG or peripheral mode. If present, the port
334+ supports switching between USB host and peripheral roles.
335+ A connector must be added as a subnode in that case.
336+
337+ See ../connector/usb-connector.yaml.
338+
339+ vbus-supply:
340+ description: A phandle to the regulator supplying the VBUS
341+ voltage.
342+
343+ dependencies:
344+ usb-role-switch: [ connector ]
345+
346+ hsic-0:
347+ type: object
348+ additionalProperties: false
349+
350+ usb3-0:
351+ type: object
352+ additionalProperties: false
353+ properties:
354+ nvidia,internal:
355+ description: A boolean property whose presence determines
356+ that a port is internal. In the absence of this property
357+ the port is considered to be external.
358+ $ref: /schemas/types.yaml#/definitions/flag
359+
360+ nvidia,usb2-companion:
361+ description: A single cell that specifies the physical port
362+ number to map this super-speed USB port to. The range of
363+ valid port numbers varies with the SoC generation.
364+ $ref: /schemas/types.yaml#/definitions/uint32
365+ enum: [ 0, 1, 2, 3 ]
366+
367+ vbus-supply:
368+ description: A phandle to the regulator supplying the VBUS
369+ voltage.
370+
371+ usb3-1:
372+ type: object
373+ additionalProperties: false
374+ properties:
375+ nvidia,internal:
376+ description: A boolean property whose presence determines
377+ that a port is internal. In the absence of this property
378+ the port is considered to be external.
379+ $ref: /schemas/types.yaml#/definitions/flag
380+
381+ nvidia,usb2-companion:
382+ description: A single cell that specifies the physical port
383+ number to map this super-speed USB port to. The range of
384+ valid port numbers varies with the SoC generation.
385+ $ref: /schemas/types.yaml#/definitions/uint32
386+ enum: [ 0, 1, 2, 3 ]
387+
388+ vbus-supply:
389+ description: A phandle to the regulator supplying the VBUS
390+ voltage.
391+
392+ usb3-2:
393+ type: object
394+ additionalProperties: false
395+ properties:
396+ nvidia,internal:
397+ description: A boolean property whose presence determines
398+ that a port is internal. In the absence of this property
399+ the port is considered to be external.
400+ $ref: /schemas/types.yaml#/definitions/flag
401+
402+ nvidia,usb2-companion:
403+ description: A single cell that specifies the physical port
404+ number to map this super-speed USB port to. The range of
405+ valid port numbers varies with the SoC generation.
406+ $ref: /schemas/types.yaml#/definitions/uint32
407+ enum: [ 0, 1, 2, 3 ]
408+
409+ vbus-supply:
410+ description: A phandle to the regulator supplying the VBUS
411+ voltage.
412+
413+additionalProperties: false
414+
415+required:
416+ - compatible
417+ - reg
418+ - resets
419+ - reset-names
420+ - avdd-pll-erefeut-supply
421+ - avdd-usb-supply
422+ - vclamp-usb-supply
423+ - vddio-hsic-supply
424+
425+examples:
426+ - |
427+ #include <dt-bindings/clock/tegra186-clock.h>
428+ #include <dt-bindings/gpio/tegra186-gpio.h>
429+ #include <dt-bindings/interrupt-controller/arm-gic.h>
430+ #include <dt-bindings/reset/tegra186-reset.h>
431+
432+ padctl@3520000 {
433+ compatible = "nvidia,tegra186-xusb-padctl";
434+ reg = <0x03520000 0x1000>,
435+ <0x03540000 0x1000>;
436+ reg-names = "padctl", "ao";
437+ interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
438+
439+ resets = <&bpmp TEGRA186_RESET_XUSB_PADCTL>;
440+ reset-names = "padctl";
441+
442+ avdd-pll-erefeut-supply = <&vdd_1v8_pll>;
443+ avdd-usb-supply = <&vdd_3v3_sys>;
444+ vclamp-usb-supply = <&vdd_1v8>;
445+ vddio-hsic-supply = <&gnd>;
446+
447+ pads {
448+ usb2 {
449+ clocks = <&bpmp TEGRA186_CLK_USB2_TRK>;
450+ clock-names = "trk";
451+
452+ lanes {
453+ usb2-0 {
454+ nvidia,function = "xusb";
455+ #phy-cells = <0>;
456+ };
457+
458+ usb2-1 {
459+ nvidia,function = "xusb";
460+ #phy-cells = <0>;
461+ };
462+
463+ usb2-2 {
464+ nvidia,function = "xusb";
465+ #phy-cells = <0>;
466+ };
467+ };
468+ };
469+
470+ hsic {
471+ clocks = <&bpmp TEGRA186_CLK_HSIC_TRK>;
472+ clock-names = "trk";
473+ status = "disabled";
474+
475+ lanes {
476+ hsic-0 {
477+ status = "disabled";
478+ #phy-cells = <0>;
479+ };
480+ };
481+ };
482+
483+ usb3 {
484+ lanes {
485+ usb3-0 {
486+ nvidia,function = "xusb";
487+ #phy-cells = <0>;
488+ };
489+
490+ usb3-1 {
491+ nvidia,function = "xusb";
492+ #phy-cells = <0>;
493+ };
494+
495+ usb3-2 {
496+ nvidia,function = "xusb";
497+ #phy-cells = <0>;
498+ };
499+ };
500+ };
501+ };
502+
503+ ports {
504+ usb2-0 {
505+ mode = "otg";
506+ vbus-supply = <&vdd_usb0>;
507+ usb-role-switch;
508+
509+ connector {
510+ compatible = "gpio-usb-b-connector",
511+ "usb-b-connector";
512+ label = "micro-USB";
513+ type = "micro";
514+ vbus-gpios = <&gpio TEGRA186_MAIN_GPIO(X, 7) GPIO_ACTIVE_LOW>;
515+ id-gpios = <&pmic 0 GPIO_ACTIVE_HIGH>;
516+ };
517+ };
518+
519+ usb2-1 {
520+ vbus-supply = <&vdd_usb1>;
521+ mode = "host";
522+ };
523+
524+ usb2-2 {
525+ status = "disabled";
526+ };
527+
528+ hsic-0 {
529+ status = "disabled";
530+ };
531+
532+ usb3-0 {
533+ nvidia,usb2-companion = <1>;
534+ };
535+
536+ usb3-1 {
537+ status = "disabled";
538+ };
539+
540+ usb3-2 {
541+ status = "disabled";
542+ };
543+ };
544+ };
Documentation/devicetree/bindings/phy/nvidia,tegra194-xusb-padctl.yaml+632−0
@@ -0,0 +1,632 @@
1+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
2+%YAML 1.2
3+---
4+$id: http://devicetree.org/schemas/phy/nvidia,tegra194-xusb-padctl.yaml#
5+$schema: http://devicetree.org/meta-schemas/core.yaml#
6+
7+title: NVIDIA Tegra194 XUSB pad controller
8+
9+maintainers:
10+ - Thierry Reding <thierry.reding@gmail.com>
11+ - Jon Hunter <jonathanh@nvidia.com>
12+
13+description: |
14+ The Tegra XUSB pad controller manages a set of I/O lanes (with differential
15+ signals) which connect directly to pins/pads on the SoC package. Each lane
16+ is controlled by a HW block referred to as a "pad" in the Tegra hardware
17+ documentation. Each such "pad" may control either one or multiple lanes,
18+ and thus contains any logic common to all its lanes. Each lane can be
19+ separately configured and powered up.
20+
21+ Some of the lanes are high-speed lanes, which can be used for PCIe, SATA or
22+ super-speed USB. Other lanes are for various types of low-speed, full-speed
23+ or high-speed USB (such as UTMI, ULPI and HSIC). The XUSB pad controller
24+ contains a software-configurable mux that sits between the I/O controller
25+ ports (e.g. PCIe) and the lanes.
26+
27+ In addition to per-lane configuration, USB 3.0 ports may require additional
28+ settings on a per-board basis.
29+
30+ Pads will be represented as children of the top-level XUSB pad controller
31+ device tree node. Each lane exposed by the pad will be represented by its
32+ own subnode and can be referenced by users of the lane using the standard
33+ PHY bindings, as described by the phy-bindings.txt file in this directory.
34+
35+ The Tegra hardware documentation refers to the connection between the XUSB
36+ pad controller and the XUSB controller as "ports". This is confusing since
37+ "port" is typically used to denote the physical USB receptacle. The device
38+ tree binding in this document uses the term "port" to refer to the logical
39+ abstraction of the signals that are routed to a USB receptacle (i.e. a PHY
40+ for the USB signal, the VBUS power supply, the USB 2.0 companion port for
41+ USB 3.0 receptacles, ...).
42+
43+properties:
44+ compatible:
45+ enum:
46+ - nvidia,tegra194-xusb-padctl
47+ - nvidia,tegra234-xusb-padctl
48+
49+ reg:
50+ items:
51+ - description: pad controller registers
52+ - description: AO registers
53+
54+ reg-names:
55+ items:
56+ - const: padctl
57+ - const: ao
58+
59+ interrupts:
60+ items:
61+ - description: XUSB pad controller interrupt
62+
63+ resets:
64+ items:
65+ - description: pad controller reset
66+
67+ reset-names:
68+ items:
69+ - const: padctl
70+
71+ avdd-usb-supply:
72+ description: USB I/Os, VBUS, ID, REXT, D+/D- power supply. Must
73+ supply 3.3 V.
74+
75+ vclamp-usb-supply:
76+ description: Bias rail for USB pad. Must supply 1.8 V.
77+
78+ pads:
79+ description: A required child node named "pads" contains a list of
80+ subnodes, one for each of the pads exposed by the XUSB pad controller.
81+ Each pad may need additional resources that can be referenced in its
82+ pad node.
83+
84+ The "status" property is used to enable or disable the use of a pad.
85+ If set to "disabled", the pad will not be used on the given board. In
86+ order to use the pad and any of its lanes, this property must be set
87+ to "okay" or absent.
88+ type: object
89+ additionalProperties: false
90+ properties:
91+ usb2:
92+ type: object
93+ additionalProperties: false
94+ properties:
95+ clocks:
96+ items:
97+ - description: USB2 tracking clock
98+
99+ clock-names:
100+ items:
101+ - const: trk
102+
103+ lanes:
104+ type: object
105+ additionalProperties: false
106+ properties:
107+ usb2-0:
108+ type: object
109+ additionalProperties: false
110+ properties:
111+ "#phy-cells":
112+ const: 0
113+
114+ nvidia,function:
115+ description: Function selection for this lane.
116+ $ref: /schemas/types.yaml#/definitions/string
117+ enum: [ xusb ]
118+
119+ usb2-1:
120+ type: object
121+ additionalProperties: false
122+ properties:
123+ "#phy-cells":
124+ const: 0
125+
126+ nvidia,function:
127+ description: Function selection for this lane.
128+ $ref: /schemas/types.yaml#/definitions/string
129+ enum: [ xusb ]
130+
131+ usb2-2:
132+ type: object
133+ additionalProperties: false
134+ properties:
135+ "#phy-cells":
136+ const: 0
137+
138+ nvidia,function:
139+ description: Function selection for this lane.
140+ $ref: /schemas/types.yaml#/definitions/string
141+ enum: [ xusb ]
142+
143+ usb2-3:
144+ type: object
145+ additionalProperties: false
146+ properties:
147+ "#phy-cells":
148+ const: 0
149+
150+ nvidia,function:
151+ description: Function selection for this lane.
152+ $ref: /schemas/types.yaml#/definitions/string
153+ enum: [ xusb ]
154+
155+ usb3:
156+ type: object
157+ additionalProperties: false
158+ properties:
159+ lanes:
160+ type: object
161+ additionalProperties: false
162+ properties:
163+ usb3-0:
164+ type: object
165+ additionalProperties: false
166+ properties:
167+ "#phy-cells":
168+ const: 0
169+
170+ nvidia,function:
171+ description: Function selection for this lane.
172+ $ref: /schemas/types.yaml#/definitions/string
173+ enum: [ xusb ]
174+
175+ usb3-1:
176+ type: object
177+ additionalProperties: false
178+ properties:
179+ "#phy-cells":
180+ const: 0
181+
182+ nvidia,function:
183+ description: Function selection for this lane.
184+ $ref: /schemas/types.yaml#/definitions/string
185+ enum: [ xusb ]
186+
187+ usb3-2:
188+ type: object
189+ additionalProperties: false
190+ properties:
191+ "#phy-cells":
192+ const: 0
193+
194+ nvidia,function:
195+ description: Function selection for this lane.
196+ $ref: /schemas/types.yaml#/definitions/string
197+ enum: [ xusb ]
198+
199+ usb3-3:
200+ type: object
201+ additionalProperties: false
202+ properties:
203+ "#phy-cells":
204+ const: 0
205+
206+ nvidia,function:
207+ description: Function selection for this lane.
208+ $ref: /schemas/types.yaml#/definitions/string
209+ enum: [ xusb ]
210+
211+ ports:
212+ description: A required child node named "ports" contains a list of
213+ subnodes, one for each of the ports exposed by the XUSB pad controller.
214+ Each port may need additional resources that can be referenced in its
215+ port node.
216+
217+ The "status" property is used to enable or disable the use of a port.
218+ If set to "disabled", the port will not be used on the given board. In
219+ order to use the port, this property must be set to "okay".
220+ type: object
221+ additionalProperties: false
222+ properties:
223+ usb2-0:
224+ type: object
225+ additionalProperties: false
226+ properties:
227+ # no need to further describe this because the connector will
228+ # match on gpio-usb-b-connector or usb-b-connector and cause
229+ # that binding to be selected for the subnode
230+ connector:
231+ type: object
232+
233+ mode:
234+ description: A string that determines the mode in which to
235+ run the port.
236+ $ref: /schemas/types.yaml#/definitions/string
237+ enum: [ host, peripheral, otg ]
238+
239+ nvidia,internal:
240+ description: A boolean property whose presence determines
241+ that a port is internal. In the absence of this property
242+ the port is considered to be external.
243+ $ref: /schemas/types.yaml#/definitions/flag
244+
245+ usb-role-switch:
246+ description: |
247+ A boolean property whole presence indicates that the port
248+ supports OTG or peripheral mode. If present, the port
249+ supports switching between USB host and peripheral roles.
250+ A connector must be added as a subnode in that case.
251+
252+ See ../connector/usb-connector.yaml.
253+
254+ vbus-supply:
255+ description: A phandle to the regulator supplying the VBUS
256+ voltage.
257+
258+ dependencies:
259+ usb-role-switch: [ connector ]
260+
261+ usb2-1:
262+ type: object
263+ additionalProperties: false
264+ properties:
265+ # no need to further describe this because the connector will
266+ # match on gpio-usb-b-connector or usb-b-connector and cause
267+ # that binding to be selected for the subnode
268+ connector:
269+ type: object
270+
271+ mode:
272+ description: A string that determines the mode in which to
273+ run the port.
274+ $ref: /schemas/types.yaml#/definitions/string
275+ enum: [ host, peripheral, otg ]
276+
277+ nvidia,internal:
278+ description: A boolean property whose presence determines
279+ that a port is internal. In the absence of this property
280+ the port is considered to be external.
281+ $ref: /schemas/types.yaml#/definitions/flag
282+
283+ usb-role-switch:
284+ description: |
285+ A boolean property whole presence indicates that the port
286+ supports OTG or peripheral mode. If present, the port
287+ supports switching between USB host and peripheral roles.
288+ A connector must be added as a subnode in that case.
289+
290+ See ../connector/usb-connector.yaml.
291+
292+ vbus-supply:
293+ description: A phandle to the regulator supplying the VBUS
294+ voltage.
295+
296+ dependencies:
297+ usb-role-switch: [ connector ]
298+
299+ usb2-2:
300+ type: object
301+ additionalProperties: false
302+ properties:
303+ # no need to further describe this because the connector will
304+ # match on gpio-usb-b-connector or usb-b-connector and cause
305+ # that binding to be selected for the subnode
306+ connector:
307+ type: object
308+
309+ mode:
310+ description: A string that determines the mode in which to
311+ run the port.
312+ $ref: /schemas/types.yaml#/definitions/string
313+ enum: [ host, peripheral, otg ]
314+
315+ nvidia,internal:
316+ description: A boolean property whose presence determines
317+ that a port is internal. In the absence of this property
318+ the port is considered to be external.
319+ $ref: /schemas/types.yaml#/definitions/flag
320+
321+ usb-role-switch:
322+ description: |
323+ A boolean property whole presence indicates that the port
324+ supports OTG or peripheral mode. If present, the port
325+ supports switching between USB host and peripheral roles.
326+ A connector must be added as a subnode in that case.
327+
328+ See ../connector/usb-connector.yaml.
329+
330+ vbus-supply:
331+ description: A phandle to the regulator supplying the VBUS
332+ voltage.
333+
334+ dependencies:
335+ usb-role-switch: [ connector ]
336+
337+ usb2-3:
338+ type: object
339+ additionalProperties: false
340+ properties:
341+ # no need to further describe this because the connector will
342+ # match on gpio-usb-b-connector or usb-b-connector and cause
343+ # that binding to be selected for the subnode
344+ connector:
345+ type: object
346+
347+ mode:
348+ description: A string that determines the mode in which to
349+ run the port.
350+ $ref: /schemas/types.yaml#/definitions/string
351+ enum: [ host, peripheral, otg ]
352+
353+ nvidia,internal:
354+ description: A boolean property whose presence determines
355+ that a port is internal. In the absence of this property
356+ the port is considered to be external.
357+ $ref: /schemas/types.yaml#/definitions/flag
358+
359+ usb-role-switch:
360+ description: |
361+ A boolean property whole presence indicates that the port
362+ supports OTG or peripheral mode. If present, the port
363+ supports switching between USB host and peripheral roles.
364+ A connector must be added as a subnode in that case.
365+
366+ See ../connector/usb-connector.yaml.
367+
368+ vbus-supply:
369+ description: A phandle to the regulator supplying the VBUS
370+ voltage.
371+
372+ dependencies:
373+ usb-role-switch: [ connector ]
374+
375+ usb3-0:
376+ type: object
377+ additionalProperties: false
378+ properties:
379+ maximum-speed:
380+ description: A string property that specifies the maximum
381+ supported speed of a USB3 port.
382+ $ref: /schemas/types.yaml#/definitions/string
383+ oneOf:
384+ - description: The USB3 port supports USB 3.1 Gen 2 speed.
385+ This is the default.
386+ const: super-speed-plus
387+ - description: The USB3 port supports USB 3.1 Gen 1 speed
388+ only.
389+ const: super-speed
390+
391+ nvidia,internal:
392+ description: A boolean property whose presence determines
393+ that a port is internal. In the absence of this property
394+ the port is considered to be external.
395+ $ref: /schemas/types.yaml#/definitions/flag
396+
397+ nvidia,usb2-companion:
398+ description: A single cell that specifies the physical port
399+ number to map this super-speed USB port to. The range of
400+ valid port numbers varies with the SoC generation.
401+ $ref: /schemas/types.yaml#/definitions/uint32
402+ enum: [ 0, 1, 2, 3 ]
403+
404+ vbus-supply:
405+ description: A phandle to the regulator supplying the VBUS
406+ voltage.
407+
408+ usb3-1:
409+ type: object
410+ additionalProperties: false
411+ properties:
412+ maximum-speed:
413+ description: A string property that specifies the maximum
414+ supported speed of a USB3 port.
415+ $ref: /schemas/types.yaml#/definitions/string
416+ oneOf:
417+ - description: The USB3 port supports USB 3.1 Gen 2 speed.
418+ This is the default.
419+ const: super-speed-plus
420+ - description: The USB3 port supports USB 3.1 Gen 1 speed
421+ only.
422+ const: super-speed
423+
424+ nvidia,internal:
425+ description: A boolean property whose presence determines
426+ that a port is internal. In the absence of this property
427+ the port is considered to be external.
428+ $ref: /schemas/types.yaml#/definitions/flag
429+
430+ nvidia,usb2-companion:
431+ description: A single cell that specifies the physical port
432+ number to map this super-speed USB port to. The range of
433+ valid port numbers varies with the SoC generation.
434+ $ref: /schemas/types.yaml#/definitions/uint32
435+ enum: [ 0, 1, 2, 3 ]
436+
437+ vbus-supply:
438+ description: A phandle to the regulator supplying the VBUS
439+ voltage.
440+
441+ usb3-2:
442+ type: object
443+ additionalProperties: false
444+ properties:
445+ maximum-speed:
446+ description: A string property that specifies the maximum
447+ supported speed of a USB3 port.
448+ $ref: /schemas/types.yaml#/definitions/string
449+ oneOf:
450+ - description: The USB3 port supports USB 3.1 Gen 2 speed.
451+ This is the default.
452+ const: super-speed-plus
453+ - description: The USB3 port supports USB 3.1 Gen 1 speed
454+ only.
455+ const: super-speed
456+
457+ nvidia,internal:
458+ description: A boolean property whose presence determines
459+ that a port is internal. In the absence of this property
460+ the port is considered to be external.
461+ $ref: /schemas/types.yaml#/definitions/flag
462+
463+ nvidia,usb2-companion:
464+ description: A single cell that specifies the physical port
465+ number to map this super-speed USB port to. The range of
466+ valid port numbers varies with the SoC generation.
467+ $ref: /schemas/types.yaml#/definitions/uint32
468+ enum: [ 0, 1, 2, 3 ]
469+
470+ vbus-supply:
471+ description: A phandle to the regulator supplying the VBUS
472+ voltage.
473+
474+ usb3-3:
475+ type: object
476+ additionalProperties: false
477+ properties:
478+ maximum-speed:
479+ description: A string property that specifies the maximum
480+ supported speed of a USB3 port.
481+ $ref: /schemas/types.yaml#/definitions/string
482+ oneOf:
483+ - description: The USB3 port supports USB 3.1 Gen 2 speed.
484+ This is the default.
485+ const: super-speed-plus
486+ - description: The USB3 port supports USB 3.1 Gen 1 speed
487+ only.
488+ const: super-speed
489+
490+ nvidia,internal:
491+ description: A boolean property whose presence determines
492+ that a port is internal. In the absence of this property
493+ the port is considered to be external.
494+ $ref: /schemas/types.yaml#/definitions/flag
495+
496+ nvidia,usb2-companion:
497+ description: A single cell that specifies the physical port
498+ number to map this super-speed USB port to. The range of
499+ valid port numbers varies with the SoC generation.
500+ $ref: /schemas/types.yaml#/definitions/uint32
501+ enum: [ 0, 1, 2, 3 ]
502+
503+ vbus-supply:
504+ description: A phandle to the regulator supplying the VBUS
505+ voltage.
506+
507+additionalProperties: false
508+
509+required:
510+ - compatible
511+ - reg
512+ - resets
513+ - reset-names
514+ - avdd-usb-supply
515+ - vclamp-usb-supply
516+
517+examples:
518+ - |
519+ #include <dt-bindings/clock/tegra194-clock.h>
520+ #include <dt-bindings/gpio/tegra194-gpio.h>
521+ #include <dt-bindings/interrupt-controller/arm-gic.h>
522+ #include <dt-bindings/reset/tegra194-reset.h>
523+
524+ padctl@3520000 {
525+ compatible = "nvidia,tegra194-xusb-padctl";
526+ reg = <0x03520000 0x1000>,
527+ <0x03540000 0x1000>;
528+ reg-names = "padctl", "ao";
529+ interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
530+
531+ resets = <&bpmp TEGRA194_RESET_XUSB_PADCTL>;
532+ reset-names = "padctl";
533+
534+ avdd-usb-supply = <&vdd_usb_3v3>;
535+ vclamp-usb-supply = <&vdd_1v8ao>;
536+
537+ pads {
538+ usb2 {
539+ clocks = <&bpmp TEGRA194_CLK_USB2_TRK>;
540+ clock-names = "trk";
541+
542+ lanes {
543+ usb2-0 {
544+ nvidia,function = "xusb";
545+ status = "disabled";
546+ #phy-cells = <0>;
547+ };
548+
549+ usb2-1 {
550+ nvidia,function = "xusb";
551+ #phy-cells = <0>;
552+ };
553+
554+ usb2-2 {
555+ nvidia,function = "xusb";
556+ status = "disabled";
557+ #phy-cells = <0>;
558+ };
559+
560+ usb2-3 {
561+ nvidia,function = "xusb";
562+ #phy-cells = <0>;
563+ };
564+ };
565+ };
566+
567+ usb3 {
568+ lanes {
569+ usb3-0 {
570+ nvidia,function = "xusb";
571+ #phy-cells = <0>;
572+ };
573+
574+ usb3-1 {
575+ nvidia,function = "xusb";
576+ status = "disabled";
577+ #phy-cells = <0>;
578+ };
579+
580+ usb3-2 {
581+ nvidia,function = "xusb";
582+ status = "disabled";
583+ #phy-cells = <0>;
584+ };
585+
586+ usb3-3 {
587+ nvidia,function = "xusb";
588+ #phy-cells = <0>;
589+ };
590+ };
591+ };
592+ };
593+
594+ ports {
595+ usb2-0 {
596+ status = "disabled";
597+ };
598+
599+ usb2-1 {
600+ vbus-supply = <&vdd_5v0_sys>;
601+ mode = "host";
602+ };
603+
604+ usb2-2 {
605+ status = "disabled";
606+ };
607+
608+ usb2-3 {
609+ vbus-supply = <&vdd_5v_sata>;
610+ mode = "host";
611+ };
612+
613+ usb3-0 {
614+ vbus-supply = <&vdd_5v0_sys>;
615+ nvidia,usb2-companion = <1>;
616+ };
617+
618+ usb3-1 {
619+ status = "disabled";
620+ };
621+
622+ usb3-2 {
623+ status = "disabled";
624+ };
625+
626+ usb3-3 {
627+ maximum-speed = "super-speed";
628+ vbus-supply = <&vdd_5v0_sys>;
629+ nvidia,usb2-companion = <3>;
630+ };
631+ };
632+ };
Documentation/devicetree/bindings/phy/nvidia,tegra210-xusb-padctl.yaml+786−0
@@ -0,0 +1,786 @@
1+# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
2+%YAML 1.2
3+---
4+$id: http://devicetree.org/schemas/phy/nvidia,tegra210-xusb-padctl.yaml#
5+$schema: http://devicetree.org/meta-schemas/core.yaml#
6+
7+title: NVIDIA Tegra210 XUSB pad controller
8+
9+maintainers:
10+ - Thierry Reding <thierry.reding@gmail.com>
11+ - Jon Hunter <jonathanh@nvidia.com>
12+
13+description: |
14+ The Tegra XUSB pad controller manages a set of I/O lanes (with differential
15+ signals) which connect directly to pins/pads on the SoC package. Each lane
16+ is controlled by a HW block referred to as a "pad" in the Tegra hardware
17+ documentation. Each such "pad" may control either one or multiple lanes,
18+ and thus contains any logic common to all its lanes. Each lane can be
19+ separately configured and powered up.
20+
21+ Some of the lanes are high-speed lanes, which can be used for PCIe, SATA or
22+ super-speed USB. Other lanes are for various types of low-speed, full-speed
23+ or high-speed USB (such as UTMI, ULPI and HSIC). The XUSB pad controller
24+ contains a software-configurable mux that sits between the I/O controller
25+ ports (e.g. PCIe) and the lanes.
26+
27+ In addition to per-lane configuration, USB 3.0 ports may require additional
28+ settings on a per-board basis.
29+
30+ Pads will be represented as children of the top-level XUSB pad controller
31+ device tree node. Each lane exposed by the pad will be represented by its
32+ own subnode and can be referenced by users of the lane using the standard
33+ PHY bindings, as described by the phy-bindings.txt file in this directory.
34+
35+ The Tegra hardware documentation refers to the connection between the XUSB
36+ pad controller and the XUSB controller as "ports". This is confusing since
37+ "port" is typically used to denote the physical USB receptacle. The device
38+ tree binding in this document uses the term "port" to refer to the logical
39+ abstraction of the signals that are routed to a USB receptacle (i.e. a PHY
40+ for the USB signal, the VBUS power supply, the USB 2.0 companion port for
41+ USB 3.0 receptacles, ...).
42+
43+properties:
44+ compatible:
45+ const: nvidia,tegra210-xusb-padctl
46+
47+ reg:
48+ maxItems: 1
49+
50+ resets:
51+ items:
52+ - description: pad controller reset
53+
54+ interrupts:
55+ items:
56+ - description: XUSB pad controller interrupt
57+
58+ reset-names:
59+ items:
60+ - const: padctl
61+
62+ avdd-pll-utmip-supply:
63+ description: UTMI PLL power supply. Must supply 1.8 V.
64+
65+ avdd-pll-uerefe-supply:
66+ description: PLLE reference PLL power supply. Must supply 1.05 V.
67+
68+ dvdd-pex-pll-supply:
69+ description: PCIe/USB3 PLL power supply. Must supply 1.05 V.
70+
71+ hvdd-pex-pll-e-supply:
72+ description: High-voltage PLLE power supply. Must supply 1.8 V.
73+
74+ nvidia,pmc:
75+ description: phandle to the Tegra Power Management Controller (PMC) node
76+ $ref: /schemas/types.yaml#/definitions/phandle
77+
78+ pads:
79+ description: A required child node named "pads" contains a list of
80+ subnodes, one for each of the pads exposed by the XUSB pad controller.
81+ Each pad may need additional resources that can be referenced in its
82+ pad node.
83+
84+ The "status" property is used to enable or disable the use of a pad.
85+ If set to "disabled", the pad will not be used on the given board. In
86+ order to use the pad and any of its lanes, this property must be set
87+ to "okay" or be absent.
88+ type: object
89+ additionalProperties: false
90+ properties:
91+ usb2:
92+ type: object
93+ additionalProperties: false
94+ properties:
95+ clocks:
96+ items:
97+ - description: USB2 tracking clock
98+
99+ clock-names:
100+ items:
101+ - const: trk
102+
103+ lanes:
104+ type: object
105+ additionalProperties: false
106+ properties:
107+ usb2-0:
108+ type: object
109+ additionalProperties: false
110+ properties:
111+ "#phy-cells":
112+ const: 0
113+
114+ nvidia,function:
115+ description: Function selection for this lane.
116+ $ref: /schemas/types.yaml#/definitions/string
117+ enum: [ snps, xusb, uart ]
118+
119+ usb2-1:
120+ type: object
121+ additionalProperties: false
122+ properties:
123+ "#phy-cells":
124+ const: 0
125+
126+ nvidia,function:
127+ description: Function selection for this lane.
128+ $ref: /schemas/types.yaml#/definitions/string
129+ enum: [ snps, xusb, uart ]
130+
131+ usb2-2:
132+ type: object
133+ additionalProperties: false
134+ properties:
135+ "#phy-cells":
136+ const: 0
137+
138+ nvidia,function:
139+ description: Function selection for this lane.
140+ $ref: /schemas/types.yaml#/definitions/string
141+ enum: [ snps, xusb, uart ]
142+
143+ usb2-3:
144+ type: object
145+ additionalProperties: false
146+ properties:
147+ "#phy-cells":
148+ const: 0
149+
150+ nvidia,function:
151+ description: Function selection for this lane.
152+ $ref: /schemas/types.yaml#/definitions/string
153+ enum: [ snps, xusb, uart ]
154+
155+ hsic:
156+ type: object
157+ additionalProperties: false
158+ properties:
159+ clocks:
160+ items:
161+ - description: HSIC tracking clock
162+
163+ clock-names:
164+ items:
165+ - const: trk
166+
167+ lanes:
168+ type: object
169+ additionalProperties: false
170+ properties:
171+ hsic-0:
172+ type: object
173+ additionalProperties: false
174+ properties:
175+ "#phy-cells":
176+ const: 0
177+
178+ nvidia,function:
179+ description: Function selection for this lane.
180+ $ref: /schemas/types.yaml#/definitions/string
181+ enum: [ snps, xusb ]
182+
183+ hsic-1:
184+ type: object
185+ additionalProperties: false
186+ properties:
187+ "#phy-cells":
188+ const: 0
189+
190+ nvidia,function:
191+ description: Function selection for this lane.
192+ $ref: /schemas/types.yaml#/definitions/string
193+ enum: [ snps, xusb ]
194+
195+ pcie:
196+ type: object
197+ additionalProperties: false
198+ properties:
199+ clocks:
200+ items:
201+ - description: PCIe PLL clock source
202+
203+ clock-names:
204+ items:
205+ - const: pll
206+
207+ resets:
208+ items:
209+ - description: PCIe PHY reset
210+
211+ reset-names:
212+ items:
213+ - const: phy
214+
215+ lanes:
216+ type: object
217+ additionalProperties: false
218+ properties:
219+ pcie-0:
220+ type: object
221+ additionalProperties: false
222+ properties:
223+ "#phy-cells":
224+ const: 0
225+
226+ nvidia,function:
227+ description: Function selection for this lane.
228+ $ref: /schemas/types.yaml#/definitions/string
229+ enum: [ pcie-x1, usb3-ss, pcie-x4 ]
230+
231+ pcie-1:
232+ type: object
233+ additionalProperties: false
234+ properties:
235+ "#phy-cells":
236+ const: 0
237+
238+ nvidia,function:
239+ description: Function selection for this lane.
240+ $ref: /schemas/types.yaml#/definitions/string
241+ enum: [ pcie-x1, usb3-ss, pcie-x4 ]
242+
243+ pcie-2:
244+ type: object
245+ additionalProperties: false
246+ properties:
247+ "#phy-cells":
248+ const: 0
249+
250+ nvidia,function:
251+ description: Function selection for this lane.
252+ $ref: /schemas/types.yaml#/definitions/string
253+ enum: [ pcie-x1, usb3-ss, pcie-x4 ]
254+
255+ pcie-3:
256+ type: object
257+ additionalProperties: false
258+ properties:
259+ "#phy-cells":
260+ const: 0
261+
262+ nvidia,function:
263+ description: Function selection for this lane.
264+ $ref: /schemas/types.yaml#/definitions/string
265+ enum: [ pcie-x1, usb3-ss, pcie-x4 ]
266+
267+ pcie-4:
268+ type: object
269+ additionalProperties: false
270+ properties:
271+ "#phy-cells":
272+ const: 0
273+
274+ nvidia,function:
275+ description: Function selection for this lane.
276+ $ref: /schemas/types.yaml#/definitions/string
277+ enum: [ pcie-x1, usb3-ss, pcie-x4 ]
278+
279+ pcie-5:
280+ type: object
281+ additionalProperties: false
282+ properties:
283+ "#phy-cells":
284+ const: 0
285+
286+ nvidia,function:
287+ description: Function selection for this lane.
288+ $ref: /schemas/types.yaml#/definitions/string
289+ enum: [ pcie-x1, usb3-ss, pcie-x4 ]
290+
291+ pcie-6:
292+ type: object
293+ additionalProperties: false
294+ properties:
295+ "#phy-cells":
296+ const: 0
297+
298+ nvidia,function:
299+ description: Function selection for this lane.
300+ $ref: /schemas/types.yaml#/definitions/string
301+ enum: [ pcie-x1, usb3-ss, pcie-x4 ]
302+
303+ sata:
304+ type: object
305+ additionalProperties: false
306+ properties:
307+ clocks:
308+ items:
309+ - description: SATA PLL clock source
310+
311+ clock-names:
312+ items:
313+ - const: pll
314+
315+ resets:
316+ items:
317+ - description: SATA PHY reset
318+
319+ reset-names:
320+ items:
321+ - const: phy
322+
323+ lanes:
324+ type: object
325+ additionalProperties: false
326+ properties:
327+ sata-0:
328+ type: object
329+ additionalProperties: false
330+ properties:
331+ "#phy-cells":
332+ const: 0
333+
334+ nvidia,function:
335+ description: Function selection for this lane.
336+ $ref: /schemas/types.yaml#/definitions/string
337+ enum: [ usb3-ss, sata ]
338+
339+ ports:
340+ description: A required child node named "ports" contains a list of
341+ subnodes, one for each of the ports exposed by the XUSB pad controller.
342+ Each port may need additional resources that can be referenced in its
343+ port node.
344+
345+ The "status" property is used to enable or disable the use of a port.
346+ If set to "disabled", the port will not be used on the given board. In
347+ order to use the port, this property must be set to "okay".
348+ type: object
349+ additionalProperties: false
350+ properties:
351+ usb2-0:
352+ type: object
353+ additionalProperties: false
354+ properties:
355+ # no need to further describe this because the connector will
356+ # match on gpio-usb-b-connector or usb-b-connector and cause
357+ # that binding to be selected for the subnode
358+ connector:
359+ type: object
360+
361+ mode:
362+ description: A string that determines the mode in which to
363+ run the port.
364+ $ref: /schemas/types.yaml#/definitions/string
365+ enum: [ host, peripheral, otg ]
366+
367+ nvidia,internal:
368+ description: A boolean property whose presence determines
369+ that a port is internal. In the absence of this property
370+ the port is considered to be external.
371+ $ref: /schemas/types.yaml#/definitions/flag
372+
373+ usb-role-switch:
374+ description: |
375+ A boolean property whole presence indicates that the port
376+ supports OTG or peripheral mode. If present, the port
377+ supports switching between USB host and peripheral roles.
378+ A connector must be added as a subnode in that case.
379+
380+ See ../connector/usb-connector.yaml.
381+
382+ vbus-supply:
383+ description: A phandle to the regulator supplying the VBUS
384+ voltage.
385+
386+ dependencies:
387+ usb-role-switch: [ connector ]
388+
389+ usb2-1:
390+ type: object
391+ additionalProperties: false
392+ properties:
393+ # no need to further describe this because the connector will
394+ # match on gpio-usb-b-connector or usb-b-connector and cause
395+ # that binding to be selected for the subnode
396+ connector:
397+ type: object
398+
399+ mode:
400+ description: A string that determines the mode in which to
401+ run the port.
402+ $ref: /schemas/types.yaml#/definitions/string
403+ enum: [ host, peripheral, otg ]
404+
405+ nvidia,internal:
406+ description: A boolean property whose presence determines
407+ that a port is internal. In the absence of this property
408+ the port is considered to be external.
409+ $ref: /schemas/types.yaml#/definitions/flag
410+
411+ usb-role-switch:
412+ description: |
413+ A boolean property whole presence indicates that the port
414+ supports OTG or peripheral mode. If present, the port
415+ supports switching between USB host and peripheral roles.
416+ A connector must be added as a subnode in that case.
417+
418+ See ../connector/usb-connector.yaml.
419+
420+ vbus-supply:
421+ description: A phandle to the regulator supplying the VBUS
422+ voltage.
423+
424+ dependencies:
425+ usb-role-switch: [ connector ]
426+
427+ usb2-2:
428+ type: object
429+ additionalProperties: false
430+ properties:
431+ # no need to further describe this because the connector will
432+ # match on gpio-usb-b-connector or usb-b-connector and cause
433+ # that binding to be selected for the subnode
434+ connector:
435+ type: object
436+
437+ mode:
438+ description: A string that determines the mode in which to
439+ run the port.
440+ $ref: /schemas/types.yaml#/definitions/string
441+ enum: [ host, peripheral, otg ]
442+
443+ nvidia,internal:
444+ description: A boolean property whose presence determines
445+ that a port is internal. In the absence of this property
446+ the port is considered to be external.
447+ $ref: /schemas/types.yaml#/definitions/flag
448+
449+ usb-role-switch:
450+ description: |
451+ A boolean property whole presence indicates that the port
452+ supports OTG or peripheral mode. If present, the port
453+ supports switching between USB host and peripheral roles.
454+ A connector must be added as a subnode in that case.
455+
456+ See ../connector/usb-connector.yaml.
457+
458+ vbus-supply:
459+ description: A phandle to the regulator supplying the VBUS
460+ voltage.
461+
462+ dependencies:
463+ usb-role-switch: [ connector ]
464+
465+ usb2-3:
466+ type: object
467+ additionalProperties: false
468+ properties:
469+ # no need to further describe this because the connector will
470+ # match on gpio-usb-b-connector or usb-b-connector and cause
471+ # that binding to be selected for the subnode
472+ connector:
473+ type: object
474+
475+ mode:
476+ description: A string that determines the mode in which to
477+ run the port.
478+ $ref: /schemas/types.yaml#/definitions/string
479+ enum: [ host, peripheral, otg ]
480+
481+ nvidia,internal:
482+ description: A boolean property whose presence determines
483+ that a port is internal. In the absence of this property
484+ the port is considered to be external.
485+ $ref: /schemas/types.yaml#/definitions/flag
486+
487+ usb-role-switch:
488+ description: |
489+ A boolean property whole presence indicates that the port
490+ supports OTG or peripheral mode. If present, the port
491+ supports switching between USB host and peripheral roles.
492+ A connector must be added as a subnode in that case.
493+
494+ See ../connector/usb-connector.yaml.
495+
496+ vbus-supply:
497+ description: A phandle to the regulator supplying the VBUS
498+ voltage.
499+
500+ dependencies:
501+ usb-role-switch: [ connector ]
502+
503+ hsic-0:
504+ type: object
505+ additionalProperties: false
506+ properties:
507+ vbus-supply:
508+ description: A phandle to the regulator supplying the VBUS
509+ voltage.
510+
511+ hsic-1:
512+ type: object
513+ additionalProperties: false
514+ properties:
515+ vbus-supply:
516+ description: A phandle to the regulator supplying the VBUS
517+ voltage.
518+
519+ usb3-0:
520+ type: object
521+ additionalProperties: false
522+ properties:
523+ nvidia,internal:
524+ description: A boolean property whose presence determines
525+ that a port is internal. In the absence of this property
526+ the port is considered to be external.
527+ $ref: /schemas/types.yaml#/definitions/flag
528+
529+ nvidia,usb2-companion:
530+ description: A single cell that specifies the physical port
531+ number to map this super-speed USB port to. The range of
532+ valid port numbers varies with the SoC generation.
533+ $ref: /schemas/types.yaml#/definitions/uint32
534+ enum: [ 0, 1, 2, 3 ]
535+
536+ vbus-supply:
537+ description: A phandle to the regulator supplying the VBUS
538+ voltage.
539+
540+ usb3-1:
541+ type: object
542+ additionalProperties: false
543+ properties:
544+ nvidia,internal:
545+ description: A boolean property whose presence determines
546+ that a port is internal. In the absence of this property
547+ the port is considered to be external.
548+ $ref: /schemas/types.yaml#/definitions/flag
549+
550+ nvidia,usb2-companion:
551+ description: A single cell that specifies the physical port
552+ number to map this super-speed USB port to. The range of
553+ valid port numbers varies with the SoC generation.
554+ $ref: /schemas/types.yaml#/definitions/uint32
555+ enum: [ 0, 1, 2, 3 ]
556+
557+ vbus-supply:
558+ description: A phandle to the regulator supplying the VBUS
559+ voltage.
560+
561+ usb3-2:
562+ type: object
563+ additionalProperties: false
564+ properties:
565+ nvidia,internal:
566+ description: A boolean property whose presence determines
567+ that a port is internal. In the absence of this property
568+ the port is considered to be external.
569+ $ref: /schemas/types.yaml#/definitions/flag
570+
571+ nvidia,usb2-companion:
572+ description: A single cell that specifies the physical port
573+ number to map this super-speed USB port to. The range of
574+ valid port numbers varies with the SoC generation.
575+ $ref: /schemas/types.yaml#/definitions/uint32
576+ enum: [ 0, 1, 2, 3 ]
577+
578+ vbus-supply:
579+ description: A phandle to the regulator supplying the VBUS
580+ voltage.
581+
582+ usb3-3:
583+ type: object
584+ additionalProperties: false
585+ properties:
586+ nvidia,internal:
587+ description: A boolean property whose presence determines
588+ that a port is internal. In the absence of this property
589+ the port is considered to be external.
590+ $ref: /schemas/types.yaml#/definitions/flag
591+
592+ nvidia,usb2-companion:
593+ description: A single cell that specifies the physical port
594+ number to map this super-speed USB port to. The range of
595+ valid port numbers varies with the SoC generation.
596+ $ref: /schemas/types.yaml#/definitions/uint32
597+ enum: [ 0, 1, 2, 3 ]
598+
599+ vbus-supply:
600+ description: A phandle to the regulator supplying the VBUS
601+ voltage.
602+
603+additionalProperties: false
604+
605+required:
606+ - avdd-pll-utmip-supply
607+ - avdd-pll-uerefe-supply
608+ - dvdd-pex-pll-supply
609+ - hvdd-pex-pll-e-supply
610+
611+examples:
612+ - |
613+ #include <dt-bindings/clock/tegra210-car.h>
614+ #include <dt-bindings/gpio/tegra-gpio.h>
615+ #include <dt-bindings/interrupt-controller/arm-gic.h>
616+
617+ padctl@7009f000 {
618+ compatible = "nvidia,tegra210-xusb-padctl";
619+ reg = <0x7009f000 0x1000>;
620+ interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
621+ resets = <&tegra_car 142>;
622+ reset-names = "padctl";
623+
624+ avdd-pll-utmip-supply = <&vdd_1v8>;
625+ avdd-pll-uerefe-supply = <&vdd_pex_1v05>;
626+ dvdd-pex-pll-supply = <&vdd_pex_1v05>;
627+ hvdd-pex-pll-e-supply = <&vdd_1v8>;
628+
629+ pads {
630+ usb2 {
631+ clocks = <&tegra_car TEGRA210_CLK_USB2_TRK>;
632+ clock-names = "trk";
633+
634+ lanes {
635+ usb2-0 {
636+ nvidia,function = "xusb";
637+ #phy-cells = <0>;
638+ };
639+
640+ usb2-1 {
641+ nvidia,function = "xusb";
642+ #phy-cells = <0>;
643+ };
644+
645+ usb2-2 {
646+ nvidia,function = "xusb";
647+ #phy-cells = <0>;
648+ };
649+
650+ usb2-3 {
651+ nvidia,function = "xusb";
652+ #phy-cells = <0>;
653+ };
654+ };
655+ };
656+
657+ hsic {
658+ clocks = <&tegra_car TEGRA210_CLK_HSIC_TRK>;
659+ clock-names = "trk";
660+ status = "disabled";
661+
662+ lanes {
663+ hsic-0 {
664+ status = "disabled";
665+ #phy-cells = <0>;
666+ };
667+
668+ hsic-1 {
669+ status = "disabled";
670+ #phy-cells = <0>;
671+ };
672+ };
673+ };
674+
675+ pcie {
676+ clocks = <&tegra_car TEGRA210_CLK_PLL_E>;
677+ clock-names = "pll";
678+ resets = <&tegra_car 205>;
679+ reset-names = "phy";
680+
681+ lanes {
682+ pcie-0 {
683+ nvidia,function = "pcie-x1";
684+ #phy-cells = <0>;
685+ };
686+
687+ pcie-1 {
688+ nvidia,function = "pcie-x4";
689+ #phy-cells = <0>;
690+ };
691+
692+ pcie-2 {
693+ nvidia,function = "pcie-x4";
694+ #phy-cells = <0>;
695+ };
696+
697+ pcie-3 {
698+ nvidia,function = "pcie-x4";
699+ #phy-cells = <0>;
700+ };
701+
702+ pcie-4 {
703+ nvidia,function = "pcie-x4";
704+ #phy-cells = <0>;
705+ };
706+
707+ pcie-5 {
708+ nvidia,function = "usb3-ss";
709+ #phy-cells = <0>;
710+ };
711+
712+ pcie-6 {
713+ nvidia,function = "usb3-ss";
714+ #phy-cells = <0>;
715+ };
716+ };
717+ };
718+
719+ sata {
720+ clocks = <&tegra_car TEGRA210_CLK_PLL_E>;
721+ clock-names = "pll";
722+ resets = <&tegra_car 204>;
723+ reset-names = "phy";
724+
725+ lanes {
726+ sata-0 {
727+ nvidia,function = "sata";
728+ #phy-cells = <0>;
729+ };
730+ };
731+ };
732+ };
733+
734+ ports {
735+ usb2-0 {
736+ mode = "peripheral";
737+ usb-role-switch;
738+
739+ connector {
740+ compatible = "gpio-usb-b-connector",
741+ "usb-b-connector";
742+ label = "micro-USB";
743+ type = "micro";
744+ vbus-gpios = <&gpio TEGRA_GPIO(CC, 4) GPIO_ACTIVE_LOW>;
745+ };
746+ };
747+
748+ usb2-1 {
749+ vbus-supply = <&vdd_5v0_rtl>;
750+ mode = "host";
751+ };
752+
753+ usb2-2 {
754+ vbus-supply = <&vdd_usb_vbus>;
755+ mode = "host";
756+ };
757+
758+ usb2-3 {
759+ mode = "host";
760+ };
761+
762+ hsic-0 {
763+ status = "disabled";
764+ };
765+
766+ hsic-1 {
767+ status = "disabled";
768+ };
769+
770+ usb3-0 {
771+ nvidia,usb2-companion = <1>;
772+ };
773+
774+ usb3-1 {
775+ nvidia,usb2-companion = <2>;
776+ };
777+
778+ usb3-2 {
779+ status = "disabled";
780+ };
781+
782+ usb3-3 {
783+ status = "disabled";
784+ };
785+ };
786+ };
Documentation/devicetree/bindings/phy/qcom,msm8996-qmp-ufs-phy.yaml+3−0
@@ -75,6 +75,9 @@ patternProperties: · 74 unmodified lines
7575 minItems: 3
7676 maxItems: 6
7777
78+ "#clock-cells":
79+ const: 1
80+
7881 "#phy-cells":
7982 const: 0
8083
Documentation/devicetree/bindings/phy/qcom,msm8996-qmp-usb3-phy.yaml+3−0
@@ -30,6 +30,7 @@ properties: · 29 unmodified lines
3030 - qcom,sdm845-qmp-usb3-uni-phy
3131 - qcom,sdx55-qmp-usb3-uni-phy
3232 - qcom,sdx65-qmp-usb3-uni-phy
33+ - qcom,sm6115-qmp-usb3-phy
3334 - qcom,sm8150-qmp-usb3-phy
3435 - qcom,sm8150-qmp-usb3-uni-phy
3536 - qcom,sm8250-qmp-usb3-phy
@@ -253,6 +254,7 @@ allOf: · 217 unmodified lines
253254 contains:
254255 enum:
255256 - qcom,qcm2290-qmp-usb3-phy
257+ - qcom,sm6115-qmp-usb3-phy
256258 then:
257259 properties:
258260 clocks:
@@ -321,6 +323,7 @@ allOf: · 62 unmodified lines
321323 - qcom,sc8180x-qmp-usb3-phy
322324 - qcom,sdx55-qmp-usb3-uni-phy
323325 - qcom,sdx65-qmp-usb3-uni-phy
326+ - qcom,sm6115-qmp-usb3-phy
324327 - qcom,sm8150-qmp-usb3-uni-phy
325328 - qcom,sm8250-qmp-usb3-phy
326329 then:
Documentation/devicetree/bindings/phy/qcom,pcie2-phy.yaml+86−0
@@ -0,0 +1,86 @@
1+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2+%YAML 1.2
3+---
4+$id: http://devicetree.org/schemas/phy/qcom,pcie2-phy.yaml#
5+$schema: http://devicetree.org/meta-schemas/core.yaml#
6+
7+title: Qualcomm PCIe2 PHY controller
8+
9+maintainers:
10+ - Vinod Koul <vkoul@kernel.org>
11+
12+description:
13+ The Qualcomm PCIe2 PHY is a Synopsys based phy found in a number of Qualcomm
14+ platforms.
15+
16+properties:
17+ compatible:
18+ items:
19+ - const: qcom,qcs404-pcie2-phy
20+ - const: qcom,pcie2-phy
21+
22+ reg:
23+ items:
24+ - description: PHY register set
25+
26+ clocks:
27+ items:
28+ - description: a clock-specifier pair for the "pipe" clock
29+
30+ clock-output-names:
31+ maxItems: 1
32+
33+ "#clock-cells":
34+ const: 0
35+
36+ "#phy-cells":
37+ const: 0
38+
39+ vdda-vp-supply:
40+ description: low voltage regulator
41+
42+ vdda-vph-supply:
43+ description: high voltage regulator
44+
45+ resets:
46+ maxItems: 2
47+
48+ reset-names:
49+ items:
50+ - const: phy
51+ - const: pipe
52+
53+required:
54+ - compatible
55+ - reg
56+ - clocks
57+ - clock-output-names
58+ - "#clock-cells"
59+ - "#phy-cells"
60+ - vdda-vp-supply
61+ - vdda-vph-supply
62+ - resets
63+ - reset-names
64+
65+additionalProperties: false
66+
67+examples:
68+ - |
69+ #include <dt-bindings/clock/qcom,gcc-qcs404.h>
70+ phy@7786000 {
71+ compatible = "qcom,qcs404-pcie2-phy", "qcom,pcie2-phy";
72+ reg = <0x07786000 0xb8>;
73+
74+ clocks = <&gcc GCC_PCIE_0_PIPE_CLK>;
75+ resets = <&gcc GCC_PCIEPHY_0_PHY_BCR>,
76+ <&gcc GCC_PCIE_0_PIPE_ARES>;
77+ reset-names = "phy", "pipe";
78+
79+ vdda-vp-supply = <&vreg_l3_1p05>;
80+ vdda-vph-supply = <&vreg_l5_1p8>;
81+
82+ clock-output-names = "pcie_0_pipe_clk";
83+ #clock-cells = <0>;
84+ #phy-cells = <0>;
85+ };
86+...
Documentation/devicetree/bindings/phy/qcom,qusb2-phy.yaml+85−75
@@ -82,81 +82,74 @@ properties: · 81 unmodified lines
8282 Phandle to TCSR syscon register region.
8383 $ref: /schemas/types.yaml#/definitions/phandle
8484
85−if:
86− properties:
87− compatible:
88− contains:
89− const: qcom,qusb2-v2-phy
90−then:
91− properties:
92− qcom,imp-res-offset-value:
93− description:
94− It is a 6 bit value that specifies offset to be
95− added to PHY refgen RESCODE via IMP_CTRL1 register. It is a PHY
96− tuning parameter that may vary for different boards of same SOC.
97− $ref: /schemas/types.yaml#/definitions/uint32
98− minimum: 0
99− maximum: 63
100− default: 0
101−
102− qcom,bias-ctrl-value:
103− description:
104− It is a 6 bit value that specifies bias-ctrl-value. It is a PHY
105− tuning parameter that may vary for different boards of same SOC.
106− $ref: /schemas/types.yaml#/definitions/uint32
107− minimum: 0
108− maximum: 63
109− default: 32
110−
111− qcom,charge-ctrl-value:
112− description:
113− It is a 2 bit value that specifies charge-ctrl-value. It is a PHY
114− tuning parameter that may vary for different boards of same SOC.
115− $ref: /schemas/types.yaml#/definitions/uint32
116− minimum: 0
117− maximum: 3
118− default: 0
119−
120− qcom,hstx-trim-value:
121− description:
122− It is a 4 bit value that specifies tuning for HSTX
123− output current.
124− Possible range is - 15mA to 24mA (stepsize of 600 uA).
125− See dt-bindings/phy/phy-qcom-qusb2.h for applicable values.
126− $ref: /schemas/types.yaml#/definitions/uint32
127− minimum: 0
128− maximum: 15
129− default: 3
130−
131− qcom,preemphasis-level:
132− description:
133− It is a 2 bit value that specifies pre-emphasis level.
134− Possible range is 0 to 15% (stepsize of 5%).
135− See dt-bindings/phy/phy-qcom-qusb2.h for applicable values.
136− $ref: /schemas/types.yaml#/definitions/uint32
137− minimum: 0
138− maximum: 3
139− default: 2
140−
141− qcom,preemphasis-width:
142− description:
143− It is a 1 bit value that specifies how long the HSTX
144− pre-emphasis (specified using qcom,preemphasis-level) must be in
145− effect. Duration could be half-bit of full-bit.
146− See dt-bindings/phy/phy-qcom-qusb2.h for applicable values.
147− $ref: /schemas/types.yaml#/definitions/uint32
148− minimum: 0
149− maximum: 1
150− default: 0
151−
152− qcom,hsdisc-trim-value:
153− description:
154− It is a 2 bit value tuning parameter that control disconnect
155− threshold and may vary for different boards of same SOC.
156− $ref: /schemas/types.yaml#/definitions/uint32
157− minimum: 0
158− maximum: 3
159− default: 0
85+ qcom,imp-res-offset-value:
86+ description:
87+ It is a 6 bit value that specifies offset to be
88+ added to PHY refgen RESCODE via IMP_CTRL1 register. It is a PHY
89+ tuning parameter that may vary for different boards of same SOC.
90+ $ref: /schemas/types.yaml#/definitions/uint32
91+ minimum: 0
92+ maximum: 63
93+ default: 0
94+
95+ qcom,bias-ctrl-value:
96+ description:
97+ It is a 6 bit value that specifies bias-ctrl-value. It is a PHY
98+ tuning parameter that may vary for different boards of same SOC.
99+ $ref: /schemas/types.yaml#/definitions/uint32
100+ minimum: 0
101+ maximum: 63
102+ default: 32
103+
104+ qcom,charge-ctrl-value:
105+ description:
106+ It is a 2 bit value that specifies charge-ctrl-value. It is a PHY
107+ tuning parameter that may vary for different boards of same SOC.
108+ $ref: /schemas/types.yaml#/definitions/uint32
109+ minimum: 0
110+ maximum: 3
111+ default: 0
112+
113+ qcom,hstx-trim-value:
114+ description:
115+ It is a 4 bit value that specifies tuning for HSTX
116+ output current.
117+ Possible range is - 15mA to 24mA (stepsize of 600 uA).
118+ See dt-bindings/phy/phy-qcom-qusb2.h for applicable values.
119+ $ref: /schemas/types.yaml#/definitions/uint32
120+ minimum: 0
121+ maximum: 15
122+ default: 3
123+
124+ qcom,preemphasis-level:
125+ description:
126+ It is a 2 bit value that specifies pre-emphasis level.
127+ Possible range is 0 to 15% (stepsize of 5%).
128+ See dt-bindings/phy/phy-qcom-qusb2.h for applicable values.
129+ $ref: /schemas/types.yaml#/definitions/uint32
130+ minimum: 0
131+ maximum: 3
132+ default: 2
133+
134+ qcom,preemphasis-width:
135+ description:
136+ It is a 1 bit value that specifies how long the HSTX
137+ pre-emphasis (specified using qcom,preemphasis-level) must be in
138+ effect. Duration could be half-bit of full-bit.
139+ See dt-bindings/phy/phy-qcom-qusb2.h for applicable values.
140+ $ref: /schemas/types.yaml#/definitions/uint32
141+ minimum: 0
142+ maximum: 1
143+ default: 0
144+
145+ qcom,hsdisc-trim-value:
146+ description:
147+ It is a 2 bit value tuning parameter that control disconnect
148+ threshold and may vary for different boards of same SOC.
149+ $ref: /schemas/types.yaml#/definitions/uint32
150+ minimum: 0
151+ maximum: 3
152+ default: 0
160153
161154 required:
162155 - compatible
@@ -169,6 +162,23 @@ required: · 6 unmodified lines
169162 - vdda-phy-dpdm-supply
170163 - resets
171164
165+allOf:
166+ - if:
167+ not:
168+ properties:
169+ compatible:
170+ contains:
171+ const: qcom,qusb2-v2-phy
172+ then:
173+ properties:
174+ qcom,imp-res-offset-value: false
175+ qcom,bias-ctrl-value: false
176+ qcom,charge-ctrl-value: false
177+ qcom,hstx-trim-value: false
178+ qcom,preemphasis-level: false
179+ qcom,preemphasis-width: false
180+ qcom,hsdisc-trim-value: false
181+
172182 additionalProperties: false
173183
174184 examples:
Documentation/devicetree/bindings/phy/qcom,sc7180-qmp-usb3-dp-phy.yaml+73−16
@@ -19,12 +19,17 @@ maintainers: · 18 unmodified lines
1919
2020 properties:
2121 compatible:
22− enum:
23− - qcom,sc7180-qmp-usb3-dp-phy
24− - qcom,sc7280-qmp-usb3-dp-phy
25− - qcom,sc8180x-qmp-usb3-dp-phy
26− - qcom,sdm845-qmp-usb3-dp-phy
27− - qcom,sm8250-qmp-usb3-dp-phy
22+ oneOf:
23+ - enum:
24+ - qcom,sc7180-qmp-usb3-dp-phy
25+ - qcom,sc8180x-qmp-usb3-dp-phy
26+ - qcom,sdm845-qmp-usb3-dp-phy
27+ - qcom,sm8250-qmp-usb3-dp-phy
28+ - items:
29+ - enum:
30+ - qcom,sc7280-qmp-usb3-dp-phy
31+ - const: qcom,sm8250-qmp-usb3-dp-phy
32+
2833 reg:
2934 items:
3035 - description: Address and length of PHY's USB serdes block.
@@ -46,18 +51,12 @@ properties: · 15 unmodified lines
4651 ranges: true
4752
4853 clocks:
49− items:
50− - description: Phy aux clock.
51− - description: Phy config clock.
52− - description: 19.2 MHz ref clk.
53− - description: Phy common block aux clock.
54+ minItems: 3
55+ maxItems: 4
5456
5557 clock-names:
56− items:
57− - const: aux
58− - const: cfg_ahb
59− - const: ref
60− - const: com_aux
58+ minItems: 3
59+ maxItems: 4
6160
6261 power-domains:
6362 maxItems: 1
@@ -166,6 +165,64 @@ required: · 102 unmodified lines
166165 - vdda-phy-supply
167166 - vdda-pll-supply
168167
168+allOf:
169+ - if:
170+ properties:
171+ compatible:
172+ enum:
173+ - qcom,sc7180-qmp-usb3-dp-phy
174+ - qcom,sdm845-qmp-usb3-dp-phy
175+ then:
176+ properties:
177+ clocks:
178+ items:
179+ - description: Phy aux clock
180+ - description: Phy config clock
181+ - description: 19.2 MHz ref clk
182+ - description: Phy common block aux clock
183+ clock-names:
184+ items:
185+ - const: aux
186+ - const: cfg_ahb
187+ - const: ref
188+ - const: com_aux
189+
190+ - if:
191+ properties:
192+ compatible:
193+ enum:
194+ - qcom,sc8180x-qmp-usb3-dp-phy
195+ then:
196+ properties:
197+ clocks:
198+ items:
199+ - description: Phy aux clock
200+ - description: 19.2 MHz ref clk
201+ - description: Phy common block aux clock
202+ clock-names:
203+ items:
204+ - const: aux
205+ - const: ref
206+ - const: com_aux
207+
208+ - if:
209+ properties:
210+ compatible:
211+ enum:
212+ - qcom,sm8250-qmp-usb3-dp-phy
213+ then:
214+ properties:
215+ clocks:
216+ items:
217+ - description: Phy aux clock
218+ - description: Board XO source
219+ - description: Phy common block aux clock
220+ clock-names:
221+ items:
222+ - const: aux
223+ - const: ref_clk_src
224+ - const: com_aux
225+
169226 additionalProperties: false
170227
171228 examples:
Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml+51−1
@@ -19,15 +19,20 @@ properties: · 18 unmodified lines
1919 - qcom,sc8280xp-qmp-gen3x1-pcie-phy
2020 - qcom,sc8280xp-qmp-gen3x2-pcie-phy
2121 - qcom,sc8280xp-qmp-gen3x4-pcie-phy
22+ - qcom,sm8350-qmp-gen3x1-pcie-phy
23+ - qcom,sm8550-qmp-gen3x2-pcie-phy
24+ - qcom,sm8550-qmp-gen4x2-pcie-phy
2225
2326 reg:
2427 minItems: 1
2528 maxItems: 2
2629
2730 clocks:
31+ minItems: 5
2832 maxItems: 6
2933
3034 clock-names:
35+ minItems: 5
3136 items:
3237 - const: aux
3338 - const: cfg_ahb
@@ -40,16 +45,21 @@ properties: · 6 unmodified lines
4045 maxItems: 1
4146
4247 resets:
43− maxItems: 1
48+ minItems: 1
49+ maxItems: 2
4450
4551 reset-names:
52+ minItems: 1
4653 items:
4754 - const: phy
55+ - const: phy_nocsr
4856
4957 vdda-phy-supply: true
5058
5159 vdda-pll-supply: true
5260
61+ vdda-qref-supply: true
62+
5363 qcom,4ln-config-sel:
5464 description: PCIe 4-lane configuration
5565 $ref: /schemas/types.yaml#/definitions/phandle-array
@@ -104,6 +114,46 @@ allOf: · 48 unmodified lines
104114 reg:
105115 maxItems: 1
106116
117+ - if:
118+ properties:
119+ compatible:
120+ contains:
121+ enum:
122+ - qcom,sm8350-qmp-gen3x1-pcie-phy
123+ - qcom,sm8550-qmp-gen3x2-pcie-phy
124+ - qcom,sm8550-qmp-gen4x2-pcie-phy
125+ then:
126+ properties:
127+ clocks:
128+ maxItems: 5
129+ clock-names:
130+ maxItems: 5
131+ else:
132+ properties:
133+ clocks:
134+ minItems: 6
135+ clock-names:
136+ minItems: 6
137+
138+ - if:
139+ properties:
140+ compatible:
141+ contains:
142+ enum:
143+ - qcom,sm8550-qmp-gen4x2-pcie-phy
144+ then:
145+ properties:
146+ resets:
147+ minItems: 2
148+ reset-names:
149+ minItems: 2
150+ else:
151+ properties:
152+ resets:
153+ maxItems: 1
154+ reset-names:
155+ maxItems: 1
156+
107157 examples:
108158 - |
109159 #include <dt-bindings/clock/qcom,gcc-sc8280xp.h>
Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-ufs-phy.yaml+5−0
@@ -17,6 +17,8 @@ properties: · 16 unmodified lines
1717 compatible:
1818 enum:
1919 - qcom,sc8280xp-qmp-ufs-phy
20+ - qcom,sm6125-qmp-ufs-phy
21+ - qcom,sm8550-qmp-ufs-phy
2022
2123 reg:
2224 maxItems: 1
@@ -43,6 +45,9 @@ properties: · 20 unmodified lines
4345
4446 vdda-pll-supply: true
4547
48+ "#clock-cells":
49+ const: 1
50+
4651 "#phy-cells":
4752 const: 0
4853
Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-usb43dp-phy.yaml+4−0
@@ -17,6 +17,10 @@ properties: · 16 unmodified lines
1717 compatible:
1818 enum:
1919 - qcom,sc8280xp-qmp-usb43dp-phy
20+ - qcom,sm6350-qmp-usb3-dp-phy
21+ - qcom,sm8350-qmp-usb3-dp-phy
22+ - qcom,sm8450-qmp-usb3-dp-phy
23+ - qcom,sm8550-qmp-usb3-dp-phy
2024
2125 reg:
2226 maxItems: 1
Documentation/devicetree/bindings/phy/qcom,snps-eusb2-phy.yaml+79−0
@@ -0,0 +1,79 @@
1+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2+%YAML 1.2
3+---
4+$id: http://devicetree.org/schemas/phy/qcom,snps-eusb2-phy.yaml#
5+$schema: http://devicetree.org/meta-schemas/core.yaml#
6+
7+title: Qualcomm SNPS eUSB2 phy controller
8+
9+maintainers:
10+ - Abel Vesa <abel.vesa@linaro.org>
11+
12+description:
13+ eUSB2 controller supports LS/FS/HS usb connectivity on Qualcomm chipsets.
14+
15+properties:
16+ compatible:
17+ const: qcom,sm8550-snps-eusb2-phy
18+
19+ reg:
20+ maxItems: 1
21+
22+ "#phy-cells":
23+ const: 0
24+
25+ clocks:
26+ items:
27+ - description: ref
28+
29+ clock-names:
30+ items:
31+ - const: ref
32+
33+ resets:
34+ maxItems: 1
35+
36+ phys:
37+ maxItems: 1
38+ description:
39+ Phandle to eUSB2 to USB 2.0 repeater
40+
41+ vdd-supply:
42+ description:
43+ Phandle to 0.88V regulator supply to PHY digital circuit.
44+
45+ vdda12-supply:
46+ description:
47+ Phandle to 1.2V regulator supply to PHY refclk pll block.
48+
49+required:
50+ - compatible
51+ - reg
52+ - "#phy-cells"
53+ - clocks
54+ - clock-names
55+ - vdd-supply
56+ - vdda12-supply
57+ - resets
58+
59+additionalProperties: false
60+
61+examples:
62+ - |
63+ #include <dt-bindings/clock/qcom,sm8550-gcc.h>
64+ #include <dt-bindings/clock/qcom,rpmh.h>
65+ #include <dt-bindings/clock/qcom,sm8550-tcsr.h>
66+
67+ usb_1_hsphy: phy@88e3000 {
68+ compatible = "qcom,sm8550-snps-eusb2-phy";
69+ reg = <0x88e3000 0x154>;
70+ #phy-cells = <0>;
71+
72+ clocks = <&tcsrcc TCSR_USB2_CLKREF_EN>;
73+ clock-names = "ref";
74+
75+ vdd-supply = <&vreg_l1e_0p88>;
76+ vdda12-supply = <&vreg_l3e_1p2>;
77+
78+ resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
79+ };
Documentation/devicetree/bindings/phy/qcom,snps-eusb2-repeater.yaml+52−0
@@ -0,0 +1,52 @@
1+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2+%YAML 1.2
3+---
4+$id: http://devicetree.org/schemas/phy/qcom,snps-eusb2-repeater.yaml#
5+$schema: http://devicetree.org/meta-schemas/core.yaml#
6+
7+title: Qualcomm Synopsis eUSB2 to USB 2.0 repeater
8+
9+maintainers:
10+ - Abel Vesa <abel.vesa@linaro.org>
11+
12+description:
13+ eUSB2 repeater converts between eUSB2 and USB 2.0 signaling levels and
14+ allows a eUSB2 PHY to connect to legacy USB 2.0 products
15+
16+properties:
17+ compatible:
18+ const: qcom,pm8550b-eusb2-repeater
19+
20+ reg:
21+ maxItems: 1
22+
23+ "#phy-cells":
24+ const: 0
25+
26+ vdd18-supply: true
27+
28+ vdd3-supply: true
29+
30+required:
31+ - compatible
32+ - reg
33+ - "#phy-cells"
34+
35+additionalProperties: false
36+
37+examples:
38+ - |
39+ #include <dt-bindings/spmi/spmi.h>
40+
41+ pmic@7 {
42+ reg = <0x7 SPMI_USID>;
43+ #address-cells = <1>;
44+ #size-cells = <0>;
45+
46+ pm8550b_eusb2_repeater: phy@fd00 {
47+ compatible = "qcom,pm8550b-eusb2-repeater";
48+ reg = <0xfd00>;
49+ #phy-cells = <0>;
50+ };
51+ };
52+...
Documentation/devicetree/bindings/phy/qcom,usb-hsic-phy.txt+0−65
@@ -1,65 +0,0 @@
1−Qualcomm's USB HSIC PHY
2−
3−PROPERTIES
4−
5−- compatible:
6− Usage: required
7− Value type: <string>
8− Definition: Should contain "qcom,usb-hsic-phy" and more specifically one of the
9− following:
10−
11− "qcom,usb-hsic-phy-mdm9615"
12− "qcom,usb-hsic-phy-msm8974"
13−
14−- #phy-cells:
15− Usage: required
16− Value type: <u32>
17− Definition: Should contain 0
18−
19−- clocks:
20− Usage: required
21− Value type: <prop-encoded-array>
22− Definition: Should contain clock specifier for phy, calibration and
23− a calibration sleep clock
24−
25−- clock-names:
26− Usage: required
27− Value type: <stringlist>
28− Definition: Should contain "phy, "cal" and "cal_sleep"
29−
30−- pinctrl-names:
31− Usage: required
32− Value type: <stringlist>
33− Definition: Should contain "init" and "default" in that order
34−
35−- pinctrl-0:
36− Usage: required
37− Value type: <prop-encoded-array>
38− Definition: List of pinctrl settings to apply to keep HSIC pins in a glitch
39− free state
40−
41−- pinctrl-1:
42− Usage: required
43− Value type: <prop-encoded-array>
44− Definition: List of pinctrl settings to apply to mux out the HSIC pins
45−
46−EXAMPLE
47−
48−usb-controller {
49− ulpi {
50− phy {
51− compatible = "qcom,usb-hsic-phy-msm8974",
52− "qcom,usb-hsic-phy";
53− #phy-cells = <0>;
54− pinctrl-names = "init", "default";
55− pinctrl-0 = <&hsic_sleep>;
56− pinctrl-1 = <&hsic_default>;
57− clocks = <&gcc GCC_USB_HSIC_CLK>,
58− <&gcc GCC_USB_HSIC_IO_CAL_CLK>,
59− <&gcc GCC_USB_HSIC_IO_CAL_SLEEP_CLK>;
60− clock-names = "phy", "cal", "cal_sleep";
61− assigned-clocks = <&gcc GCC_USB_HSIC_IO_CAL_CLK>;
62− assigned-clock-rates = <960000>;
63− };
64− };
65−};
Documentation/devicetree/bindings/phy/qcom,usb-hsic-phy.yaml+67−0
@@ -0,0 +1,67 @@
1+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2+%YAML 1.2
3+---
4+$id: http://devicetree.org/schemas/phy/qcom,usb-hsic-phy.yaml#
5+$schema: http://devicetree.org/meta-schemas/core.yaml#
6+
7+title: Qualcomm USB HSIC PHY Controller
8+
9+maintainers:
10+ - Bjorn Andersson <andersson@kernel.org>
11+ - Vinod Koul <vkoul@kernel.org>
12+
13+properties:
14+ compatible:
15+ items:
16+ - enum:
17+ - qcom,usb-hsic-phy-mdm9615
18+ - qcom,usb-hsic-phy-msm8974
19+ - const: qcom,usb-hsic-phy
20+
21+ clocks:
22+ maxItems: 3
23+
24+ clock-names:
25+ items:
26+ - const: phy
27+ - const: cal
28+ - const: cal_sleep
29+
30+ "#phy-cells":
31+ const: 0
32+
33+ pinctrl-0: true
34+ pinctrl-1: true
35+
36+ pinctrl-names:
37+ items:
38+ - const: init
39+ - const: default
40+
41+required:
42+ - compatible
43+ - clocks
44+ - clock-names
45+ - "#phy-cells"
46+ - pinctrl-0
47+ - pinctrl-1
48+ - pinctrl-names
49+
50+additionalProperties: false
51+
52+examples:
53+ - |
54+ #include <dt-bindings/clock/qcom,gcc-msm8974.h>
55+
56+ phy {
57+ compatible = "qcom,usb-hsic-phy-msm8974",
58+ "qcom,usb-hsic-phy";
59+ clocks = <&gcc GCC_USB_HSIC_CLK>,
60+ <&gcc GCC_USB_HSIC_IO_CAL_CLK>,
61+ <&gcc GCC_USB_HSIC_IO_CAL_SLEEP_CLK>;
62+ clock-names = "phy", "cal", "cal_sleep";
63+ #phy-cells = <0>;
64+ pinctrl-names = "init", "default";
65+ pinctrl-0 = <&hsic_sleep>;
66+ pinctrl-1 = <&hsic_default>;
67+ };
Documentation/devicetree/bindings/phy/qcom,usb-snps-femto-v2.yaml+20−13
@@ -14,18 +14,25 @@ description: | · 13 unmodified lines
1414
1515 properties:
1616 compatible:
17− enum:
18− - qcom,usb-snps-hs-5nm-phy
19− - qcom,usb-snps-hs-7nm-phy
20− - qcom,sc7280-usb-hs-phy
21− - qcom,sc8180x-usb-hs-phy
22− - qcom,sc8280xp-usb-hs-phy
23− - qcom,sm6375-usb-hs-phy
24− - qcom,sm8150-usb-hs-phy
25− - qcom,sm8250-usb-hs-phy
26− - qcom,sm8350-usb-hs-phy
27− - qcom,sm8450-usb-hs-phy
28− - qcom,usb-snps-femto-v2-phy
17+ oneOf:
18+ - enum:
19+ - qcom,sc8180x-usb-hs-phy
20+ - qcom,usb-snps-femto-v2-phy
21+ - items:
22+ - enum:
23+ - qcom,sc8280xp-usb-hs-phy
24+ - const: qcom,usb-snps-hs-5nm-phy
25+ - items:
26+ - enum:
27+ - qcom,sc7280-usb-hs-phy
28+ - qcom,sdx55-usb-hs-phy
29+ - qcom,sdx65-usb-hs-phy
30+ - qcom,sm6375-usb-hs-phy
31+ - qcom,sm8150-usb-hs-phy
32+ - qcom,sm8250-usb-hs-phy
33+ - qcom,sm8350-usb-hs-phy
34+ - qcom,sm8450-usb-hs-phy
35+ - const: qcom,usb-snps-hs-7nm-phy
2936
3037 reg:
3138 maxItems: 1
@@ -160,7 +167,7 @@ examples: · 128 unmodified lines
160167 #include <dt-bindings/clock/qcom,rpmh.h>
161168 #include <dt-bindings/clock/qcom,gcc-sm8150.h>
162169 phy@88e2000 {
163− compatible = "qcom,sm8150-usb-hs-phy";
170+ compatible = "qcom,sm8150-usb-hs-phy", "qcom,usb-snps-hs-7nm-phy";
164171 reg = <0x088e2000 0x400>;
165172 #phy-cells = <0>;
166173
Documentation/devicetree/bindings/phy/qcom-pcie2-phy.txt+0−42
@@ -1,42 +0,0 @@
1−Qualcomm PCIe2 PHY controller
2−=============================
3−
4−The Qualcomm PCIe2 PHY is a Synopsys based phy found in a number of Qualcomm
5−platforms.
6−
7−Required properties:
8− - compatible: compatible list, should be:
9− "qcom,qcs404-pcie2-phy", "qcom,pcie2-phy"
10−
11− - reg: offset and length of the PHY register set.
12− - #phy-cells: must be 0.
13−
14− - clocks: a clock-specifier pair for the "pipe" clock
15−
16− - vdda-vp-supply: phandle to low voltage regulator
17− - vdda-vph-supply: phandle to high voltage regulator
18−
19− - resets: reset-specifier pairs for the "phy" and "pipe" resets
20− - reset-names: list of resets, should contain:
21− "phy" and "pipe"
22−
23− - clock-output-names: name of the outgoing clock signal from the PHY PLL
24− - #clock-cells: must be 0
25−
26−Example:
27− phy@7786000 {
28− compatible = "qcom,qcs404-pcie2-phy", "qcom,pcie2-phy";
29− reg = <0x07786000 0xb8>;
30−
31− clocks = <&gcc GCC_PCIE_0_PIPE_CLK>;
32− resets = <&gcc GCC_PCIEPHY_0_PHY_BCR>,
33− <&gcc GCC_PCIE_0_PIPE_ARES>;
34− reset-names = "phy", "pipe";
35−
36− vdda-vp-supply = <&vreg_l3_1p05>;
37− vdda-vph-supply = <&vreg_l5_1p8>;
38−
39− clock-output-names = "pcie_0_pipe_clk";
40− #clock-cells = <0>;
41− #phy-cells = <0>;
42− };
Documentation/devicetree/bindings/phy/ti,tcan104x-can.yaml+1−0
@@ -15,6 +15,7 @@ properties: · 14 unmodified lines
1515
1616 compatible:
1717 enum:
18+ - nxp,tjr1443
1819 - ti,tcan1042
1920 - ti,tcan1043
2021
Documentation/driver-api/phy/phy.rst+14−10
@@ -103,27 +103,31 @@ it. This framework provides the following APIs to get a reference to the PHY. · 102 unmodified lines
103103 ::
104104
105105 struct phy *phy_get(struct device *dev, const char *string);
106− struct phy *phy_optional_get(struct device *dev, const char *string);
107106 struct phy *devm_phy_get(struct device *dev, const char *string);
108107 struct phy *devm_phy_optional_get(struct device *dev,
109108 const char *string);
109+ struct phy *devm_of_phy_get(struct device *dev, struct device_node *np,
110+ const char *con_id);
111+ struct phy *devm_of_phy_optional_get(struct device *dev,
112+ struct device_node *np,
113+ const char *con_id);
110114 struct phy *devm_of_phy_get_by_index(struct device *dev,
111115 struct device_node *np,
112116 int index);
113117
114−phy_get, phy_optional_get, devm_phy_get and devm_phy_optional_get can
115−be used to get the PHY. In the case of dt boot, the string arguments
118+phy_get, devm_phy_get and devm_phy_optional_get can be used to get the PHY.
119+In the case of dt boot, the string arguments
116120 should contain the phy name as given in the dt data and in the case of
117121 non-dt boot, it should contain the label of the PHY. The two
118122 devm_phy_get associates the device with the PHY using devres on
119123 successful PHY get. On driver detach, release function is invoked on
120−the devres data and devres data is freed. phy_optional_get and
121−devm_phy_optional_get should be used when the phy is optional. These
122−two functions will never return -ENODEV, but instead returns NULL when
123−the phy cannot be found.Some generic drivers, such as ehci, may use multiple
124−phys and for such drivers referencing phy(s) by name(s) does not make sense. In
125−this case, devm_of_phy_get_by_index can be used to get a phy reference based on
126−the index.
124+the devres data and devres data is freed.
125+The _optional_get variants should be used when the phy is optional. These
126+functions will never return -ENODEV, but instead return NULL when
127+the phy cannot be found.
128+Some generic drivers, such as ehci, may use multiple phys. In this case,
129+devm_of_phy_get or devm_of_phy_get_by_index can be used to get a phy
130+reference based on name or index.
127131
128132 It should be noted that NULL is a valid phy reference. All phy
129133 consumer calls on the NULL phy become NOPs. That is the release calls,
drivers/net/ethernet/freescale/fman/fman_memac.c+4−5
@@ -1155,13 +1155,12 @@ int memac_initialization(struct mac_device *mac_dev, · 1154 unmodified lines
11551155 else
11561156 memac->sgmii_pcs = pcs;
11571157
1158− memac->serdes = devm_of_phy_get(mac_dev->dev, mac_node, "serdes");
1159− err = PTR_ERR(memac->serdes);
1160− if (err == -ENODEV || err == -ENOSYS) {
1158+ memac->serdes = devm_of_phy_optional_get(mac_dev->dev, mac_node,
1159+ "serdes");
1160+ if (!memac->serdes) {
11611161 dev_dbg(mac_dev->dev, "could not get (optional) serdes\n");
1162− memac->serdes = NULL;
11631162 } else if (IS_ERR(memac->serdes)) {
1164− dev_err_probe(mac_dev->dev, err, "could not get serdes\n");
1163+ err = PTR_ERR(memac->serdes);
11651164 goto _return_fm_mac_free;
11661165 }
11671166
drivers/net/ethernet/microchip/lan966x/lan966x_main.c+2−3
@@ -1154,9 +1154,8 @@ static int lan966x_probe(struct platform_device *pdev) · 1153 unmodified lines
11541154 lan966x->ports[p]->config.portmode = phy_mode;
11551155 lan966x->ports[p]->fwnode = fwnode_handle_get(portnp);
11561156
1157− serdes = devm_of_phy_get(lan966x->dev, to_of_node(portnp), NULL);
1158− if (PTR_ERR(serdes) == -ENODEV)
1159− serdes = NULL;
1157+ serdes = devm_of_phy_optional_get(lan966x->dev,
1158+ to_of_node(portnp), NULL);
11601159 if (IS_ERR(serdes)) {
11611160 err = PTR_ERR(serdes);
11621161 goto cleanup_ports;
drivers/pci/controller/pci-tegra.c+1−4
@@ -1330,12 +1330,9 @@ static struct phy *devm_of_phy_optional_get_index(struct device *dev, · 1329 unmodified lines
13301330 if (!name)
13311331 return ERR_PTR(-ENOMEM);
13321332
1333− phy = devm_of_phy_get(dev, np, name);
1333+ phy = devm_of_phy_optional_get(dev, np, name);
13341334 kfree(name);
13351335
1336− if (PTR_ERR(phy) == -ENODEV)
1337− phy = NULL;
1338−
13391336 return phy;
13401337 }
13411338
drivers/phy/allwinner/phy-sun4i-usb.c+24−35
@@ -99,28 +99,17 @@ · 98 unmodified lines
9999 #define DEBOUNCE_TIME msecs_to_jiffies(50)
100100 #define POLL_TIME msecs_to_jiffies(250)
101101
102−enum sun4i_usb_phy_type {
103− sun4i_a10_phy,
104− sun6i_a31_phy,
105− sun8i_a33_phy,
106− sun8i_a83t_phy,
107− sun8i_h3_phy,
108− sun8i_r40_phy,
109− sun8i_v3s_phy,
110− sun50i_a64_phy,
111− sun50i_h6_phy,
112−};
113−
114102 struct sun4i_usb_phy_cfg {
115103 int num_phys;
116104 int hsic_index;
117− enum sun4i_usb_phy_type type;
118105 u32 disc_thresh;
119106 u32 hci_phy_ctl_clear;
120107 u8 phyctl_offset;
121108 bool dedicated_clocks;
122109 bool phy0_dual_route;
123110 bool needs_phy2_siddq;
111+ bool siddq_in_base;
112+ bool poll_vbusen;
124113 int missing_phys;
125114 };
126115
@@ -252,7 +241,8 @@ static void sun4i_usb_phy_passby(struct sun4i_usb_phy *phy, int enable) · 125 unmodified lines
252241 SUNXI_AHB_INCRX_ALIGN_EN | SUNXI_ULPI_BYPASS_EN;
253242
254243 /* A83T USB2 is HSIC */
255− if (phy_data->cfg->type == sun8i_a83t_phy && phy->index == 2)
244+ if (phy_data->cfg->hsic_index &&
245+ phy->index == phy_data->cfg->hsic_index)
256246 bits |= SUNXI_EHCI_HS_FORCE | SUNXI_HSIC_CONNECT_INT |
257247 SUNXI_HSIC;
258248
@@ -340,8 +330,7 @@ static int sun4i_usb_phy_init(struct phy *_phy) · 81 unmodified lines
340330 writel(val, phy->pmu + REG_HCI_PHY_CTL);
341331 }
342332
343− if (data->cfg->type == sun8i_a83t_phy ||
344− data->cfg->type == sun50i_h6_phy) {
333+ if (data->cfg->siddq_in_base) {
345334 if (phy->index == 0) {
346335 val = readl(data->base + data->cfg->phyctl_offset);
347336 val |= PHY_CTL_VBUSVLDEXT;
@@ -385,8 +374,7 @@ static int sun4i_usb_phy_exit(struct phy *_phy) · 37 unmodified lines
385374 struct sun4i_usb_phy_data *data = to_sun4i_usb_phy_data(phy);
386375
387376 if (phy->index == 0) {
388− if (data->cfg->type == sun8i_a83t_phy ||
389− data->cfg->type == sun50i_h6_phy) {
377+ if (data->cfg->siddq_in_base) {
390378 void __iomem *phyctl = data->base +
391379 data->cfg->phyctl_offset;
392380
@@ -466,9 +454,8 @@ static bool sun4i_usb_phy0_poll(struct sun4i_usb_phy_data *data) · 73 unmodified lines
466454 * vbus using the N_VBUSEN pin on the pmic, so we must poll
467455 * when using the pmic for vbus-det _and_ we're driving vbus.
468456 */
469− if ((data->cfg->type == sun6i_a31_phy ||
470− data->cfg->type == sun8i_a33_phy) &&
471− data->vbus_power_supply && data->phys[0].regulator_on)
457+ if (data->cfg->poll_vbusen && data->vbus_power_supply &&
458+ data->phys[0].regulator_on)
472459 return true;
473460
474461 return false;
@@ -918,9 +905,15 @@ static int sun4i_usb_phy_probe(struct platform_device *pdev) · 443 unmodified lines
918905 return 0;
919906 }
920907
908+static const struct sun4i_usb_phy_cfg suniv_f1c100s_cfg = {
909+ .num_phys = 1,
910+ .disc_thresh = 3,
911+ .phyctl_offset = REG_PHYCTL_A10,
912+ .dedicated_clocks = true,
913+};
914+
921915 static const struct sun4i_usb_phy_cfg sun4i_a10_cfg = {
922916 .num_phys = 3,
923− .type = sun4i_a10_phy,
924917 .disc_thresh = 3,
925918 .phyctl_offset = REG_PHYCTL_A10,
926919 .dedicated_clocks = false,
@@ -928,7 +921,6 @@ static const struct sun4i_usb_phy_cfg sun4i_a10_cfg = { · 1 unmodified line
928921
929922 static const struct sun4i_usb_phy_cfg sun5i_a13_cfg = {
930923 .num_phys = 2,
931− .type = sun4i_a10_phy,
932924 .disc_thresh = 2,
933925 .phyctl_offset = REG_PHYCTL_A10,
934926 .dedicated_clocks = false,
@@ -936,15 +928,14 @@ static const struct sun4i_usb_phy_cfg sun5i_a13_cfg = { · 1 unmodified line
936928
937929 static const struct sun4i_usb_phy_cfg sun6i_a31_cfg = {
938930 .num_phys = 3,
939− .type = sun6i_a31_phy,
940931 .disc_thresh = 3,
941932 .phyctl_offset = REG_PHYCTL_A10,
942933 .dedicated_clocks = true,
934+ .poll_vbusen = true,
943935 };
944936
945937 static const struct sun4i_usb_phy_cfg sun7i_a20_cfg = {
946938 .num_phys = 3,
947− .type = sun4i_a10_phy,
948939 .disc_thresh = 2,
949940 .phyctl_offset = REG_PHYCTL_A10,
950941 .dedicated_clocks = false,
@@ -952,31 +943,30 @@ static const struct sun4i_usb_phy_cfg sun7i_a20_cfg = { · 1 unmodified line
952943
953944 static const struct sun4i_usb_phy_cfg sun8i_a23_cfg = {
954945 .num_phys = 2,
955− .type = sun6i_a31_phy,
956946 .disc_thresh = 3,
957947 .phyctl_offset = REG_PHYCTL_A10,
958948 .dedicated_clocks = true,
949+ .poll_vbusen = true,
959950 };
960951
961952 static const struct sun4i_usb_phy_cfg sun8i_a33_cfg = {
962953 .num_phys = 2,
963− .type = sun8i_a33_phy,
964954 .disc_thresh = 3,
965955 .phyctl_offset = REG_PHYCTL_A33,
966956 .dedicated_clocks = true,
957+ .poll_vbusen = true,
967958 };
968959
969960 static const struct sun4i_usb_phy_cfg sun8i_a83t_cfg = {
970961 .num_phys = 3,
971962 .hsic_index = 2,
972− .type = sun8i_a83t_phy,
973963 .phyctl_offset = REG_PHYCTL_A33,
974964 .dedicated_clocks = true,
965+ .siddq_in_base = true,
975966 };
976967
977968 static const struct sun4i_usb_phy_cfg sun8i_h3_cfg = {
978969 .num_phys = 4,
979− .type = sun8i_h3_phy,
980970 .disc_thresh = 3,
981971 .phyctl_offset = REG_PHYCTL_A33,
982972 .dedicated_clocks = true,
@@ -986,7 +976,6 @@ static const struct sun4i_usb_phy_cfg sun8i_h3_cfg = { · 3 unmodified lines
986976
987977 static const struct sun4i_usb_phy_cfg sun8i_r40_cfg = {
988978 .num_phys = 3,
989− .type = sun8i_r40_phy,
990979 .disc_thresh = 3,
991980 .phyctl_offset = REG_PHYCTL_A33,
992981 .dedicated_clocks = true,
@@ -996,7 +985,6 @@ static const struct sun4i_usb_phy_cfg sun8i_r40_cfg = { · 3 unmodified lines
996985
997986 static const struct sun4i_usb_phy_cfg sun8i_v3s_cfg = {
998987 .num_phys = 1,
999− .type = sun8i_v3s_phy,
1000988 .disc_thresh = 3,
1001989 .phyctl_offset = REG_PHYCTL_A33,
1002990 .dedicated_clocks = true,
@@ -1006,16 +994,15 @@ static const struct sun4i_usb_phy_cfg sun8i_v3s_cfg = { · 3 unmodified lines
1006994
1007995 static const struct sun4i_usb_phy_cfg sun20i_d1_cfg = {
1008996 .num_phys = 2,
1009− .type = sun50i_h6_phy,
1010997 .phyctl_offset = REG_PHYCTL_A33,
1011998 .dedicated_clocks = true,
1012999 .hci_phy_ctl_clear = PHY_CTL_SIDDQ,
10131000 .phy0_dual_route = true,
1001+ .siddq_in_base = true,
10141002 };
10151003
10161004 static const struct sun4i_usb_phy_cfg sun50i_a64_cfg = {
10171005 .num_phys = 2,
1018− .type = sun50i_a64_phy,
10191006 .disc_thresh = 3,
10201007 .phyctl_offset = REG_PHYCTL_A33,
10211008 .dedicated_clocks = true,
@@ -1025,22 +1012,22 @@ static const struct sun4i_usb_phy_cfg sun50i_a64_cfg = { · 3 unmodified lines
10251012
10261013 static const struct sun4i_usb_phy_cfg sun50i_h6_cfg = {
10271014 .num_phys = 4,
1028− .type = sun50i_h6_phy,
10291015 .phyctl_offset = REG_PHYCTL_A33,
10301016 .dedicated_clocks = true,
10311017 .phy0_dual_route = true,
10321018 .missing_phys = BIT(1) | BIT(2),
1019+ .siddq_in_base = true,
10331020 };
10341021
10351022 static const struct sun4i_usb_phy_cfg sun50i_h616_cfg = {
10361023 .num_phys = 4,
1037− .type = sun50i_h6_phy,
10381024 .disc_thresh = 3,
10391025 .phyctl_offset = REG_PHYCTL_A33,
10401026 .dedicated_clocks = true,
10411027 .phy0_dual_route = true,
10421028 .hci_phy_ctl_clear = PHY_CTL_SIDDQ,
10431029 .needs_phy2_siddq = true,
1030+ .siddq_in_base = true,
10441031 };
10451032
10461033 static const struct of_device_id sun4i_usb_phy_of_match[] = {
@@ -1059,6 +1046,8 @@ static const struct of_device_id sun4i_usb_phy_of_match[] = { · 12 unmodified lines
10591046 .data = &sun50i_a64_cfg},
10601047 { .compatible = "allwinner,sun50i-h6-usb-phy", .data = &sun50i_h6_cfg },
10611048 { .compatible = "allwinner,sun50i-h616-usb-phy", .data = &sun50i_h616_cfg },
1049+ { .compatible = "allwinner,suniv-f1c100s-usb-phy",
1050+ .data = &suniv_f1c100s_cfg },
10621051 { },
10631052 };
10641053 MODULE_DEVICE_TABLE(of, sun4i_usb_phy_of_match);
drivers/phy/mediatek/phy-mtk-io.h+2−2
@@ -39,8 +39,8 @@ static inline void mtk_phy_update_bits(void __iomem *reg, u32 mask, u32 val) · 38 unmodified lines
3939 /* field @mask shall be constant and continuous */
4040 #define mtk_phy_update_field(reg, mask, val) \
4141 ({ \
42− typeof(mask) mask_ = (mask); \
43− mtk_phy_update_bits(reg, mask_, FIELD_PREP(mask_, val)); \
42+ BUILD_BUG_ON_MSG(!__builtin_constant_p(mask), "mask is not constant"); \
43+ mtk_phy_update_bits(reg, mask, FIELD_PREP(mask, val)); \
4444 })
4545
4646 #endif
drivers/phy/phy-can-transceiver.c+4−0
@@ -84,6 +84,10 @@ static const struct of_device_id can_transceiver_phy_ids[] = { · 83 unmodified lines
8484 .compatible = "ti,tcan1043",
8585 .data = &tcan1043_drvdata
8686 },
87+ {
88+ .compatible = "nxp,tjr1443",
89+ .data = &tcan1043_drvdata
90+ },
8791 { }
8892 };
8993 MODULE_DEVICE_TABLE(of, can_transceiver_phy_ids);
drivers/phy/phy-core.c+30−21
@@ -766,27 +766,6 @@ struct phy *phy_get(struct device *dev, const char *string) · 765 unmodified lines
766766 }
767767 EXPORT_SYMBOL_GPL(phy_get);
768768
769−/**
770− * phy_optional_get() - lookup and obtain a reference to an optional phy.
771− * @dev: device that requests this phy
772− * @string: the phy name as given in the dt data or the name of the controller
773− * port for non-dt case
774− *
775− * Returns the phy driver, after getting a refcount to it; or
776− * NULL if there is no such phy. The caller is responsible for
777− * calling phy_put() to release that count.
778− */
779−struct phy *phy_optional_get(struct device *dev, const char *string)
780−{
781− struct phy *phy = phy_get(dev, string);
782−
783− if (PTR_ERR(phy) == -ENODEV)
784− phy = NULL;
785−
786− return phy;
787−}
788−EXPORT_SYMBOL_GPL(phy_optional_get);
789−
790769 /**
791770 * devm_phy_get() - lookup and obtain a reference to a phy.
792771 * @dev: device that requests this phy
@@ -879,6 +858,36 @@ struct phy *devm_of_phy_get(struct device *dev, struct device_node *np, · 86 unmodified lines
879858 }
880859 EXPORT_SYMBOL_GPL(devm_of_phy_get);
881860
861+/**
862+ * devm_of_phy_optional_get() - lookup and obtain a reference to an optional
863+ * phy.
864+ * @dev: device that requests this phy
865+ * @np: node containing the phy
866+ * @con_id: name of the phy from device's point of view
867+ *
868+ * Gets the phy using of_phy_get(), and associates a device with it using
869+ * devres. On driver detach, release function is invoked on the devres data,
870+ * then, devres data is freed. This differs to devm_of_phy_get() in
871+ * that if the phy does not exist, it is not considered an error and
872+ * -ENODEV will not be returned. Instead the NULL phy is returned,
873+ * which can be passed to all other phy consumer calls.
874+ */
875+struct phy *devm_of_phy_optional_get(struct device *dev, struct device_node *np,
876+ const char *con_id)
877+{
878+ struct phy *phy = devm_of_phy_get(dev, np, con_id);
879+
880+ if (PTR_ERR(phy) == -ENODEV)
881+ phy = NULL;
882+
883+ if (IS_ERR(phy))
884+ dev_err_probe(dev, PTR_ERR(phy), "failed to get PHY %pOF:%s",
885+ np, con_id);
886+
887+ return phy;
888+}
889+EXPORT_SYMBOL_GPL(devm_of_phy_optional_get);
890+
882891 /**
883892 * devm_of_phy_get_by_index() - lookup and obtain a reference to a phy by index.
884893 * @dev: device that requests this phy
drivers/phy/qualcomm/Kconfig+64−4
@@ -50,14 +50,56 @@ config PHY_QCOM_PCIE2 · 49 unmodified lines
5050 Enable this to support the Qualcomm PCIe PHY, used with the Synopsys
5151 based PCIe controller.
5252
53−config PHY_QCOM_QMP
54− tristate "Qualcomm QMP PHY Driver"
53+menuconfig PHY_QCOM_QMP
54+ tristate "Qualcomm QMP PHY Drivers"
5555 depends on OF && COMMON_CLK && (ARCH_QCOM || COMPILE_TEST)
56+
57+if PHY_QCOM_QMP
58+
59+config PHY_QCOM_QMP_COMBO
60+ tristate "Qualcomm QMP Combo PHY Driver"
61+ default PHY_QCOM_QMP
5662 select GENERIC_PHY
5763 select MFD_SYSCON
5864 help
59− Enable this to support the QMP PHY transceiver that is used
60− with controllers such as PCIe, UFS, and USB on Qualcomm chips.
65+ Enable this to support the QMP Combo PHY transceiver that is used
66+ with USB3 and DisplayPort controllers on Qualcomm chips.
67+
68+config PHY_QCOM_QMP_PCIE
69+ tristate "Qualcomm QMP PCIe PHY Driver"
70+ depends on PCI || COMPILE_TEST
71+ select GENERIC_PHY
72+ default PHY_QCOM_QMP
73+ help
74+ Enable this to support the QMP PCIe PHY transceiver that is used
75+ with PCIe controllers on Qualcomm chips.
76+
77+config PHY_QCOM_QMP_PCIE_8996
78+ tristate "Qualcomm QMP PCIe 8996 PHY Driver"
79+ depends on PCI || COMPILE_TEST
80+ select GENERIC_PHY
81+ default PHY_QCOM_QMP
82+ help
83+ Enable this to support the QMP PCIe PHY transceiver that is used
84+ with PCIe controllers on Qualcomm msm8996 chips.
85+
86+config PHY_QCOM_QMP_UFS
87+ tristate "Qualcomm QMP UFS PHY Driver"
88+ select GENERIC_PHY
89+ default PHY_QCOM_QMP
90+ help
91+ Enable this to support the QMP UFS PHY transceiver that is used
92+ with UFS controllers on Qualcomm chips.
93+
94+config PHY_QCOM_QMP_USB
95+ tristate "Qualcomm QMP USB PHY Driver"
96+ select GENERIC_PHY
97+ default PHY_QCOM_QMP
98+ help
99+ Enable this to support the QMP USB PHY transceiver that is used
100+ with USB3 controllers on Qualcomm chips.
101+
102+endif # PHY_QCOM_QMP
61103
62104 config PHY_QCOM_QUSB2
63105 tristate "Qualcomm QUSB2 PHY Driver"
@@ -70,6 +112,24 @@ config PHY_QCOM_QUSB2 · 6 unmodified lines
70112 PHY which is usually paired with either the ChipIdea or Synopsys DWC3
71113 USB IPs on MSM SOCs.
72114
115+config PHY_QCOM_SNPS_EUSB2
116+ tristate "Qualcomm SNPS eUSB2 PHY Driver"
117+ depends on OF && (ARCH_QCOM || COMPILE_TEST)
118+ select GENERIC_PHY
119+ help
120+ Enable support for the USB high-speed SNPS eUSB2 phy on Qualcomm
121+ chipsets. The PHY is paired with a Synopsys DWC3 USB controller
122+ on Qualcomm SOCs.
123+
124+config PHY_QCOM_EUSB2_REPEATER
125+ tristate "Qualcomm SNPS eUSB2 Repeater Driver"
126+ depends on OF && (ARCH_QCOM || COMPILE_TEST)
127+ select GENERIC_PHY
128+ help
129+ Enable support for the USB high-speed SNPS eUSB2 repeater on Qualcomm
130+ PMICs. The repeater is paired with a Synopsys eUSB2 Phy
131+ on Qualcomm SOCs.
132+
73133 config PHY_QCOM_USB_HS
74134 tristate "Qualcomm USB HS PHY module"
75135 depends on USB_ULPI_BUS
drivers/phy/qualcomm/Makefile+8−6
@@ -5,14 +5,16 @@ obj-$(CONFIG_PHY_QCOM_EDP) += phy-qcom-edp.o · 4 unmodified lines
55 obj-$(CONFIG_PHY_QCOM_IPQ4019_USB) += phy-qcom-ipq4019-usb.o
66 obj-$(CONFIG_PHY_QCOM_IPQ806X_SATA) += phy-qcom-ipq806x-sata.o
77 obj-$(CONFIG_PHY_QCOM_PCIE2) += phy-qcom-pcie2.o
8−obj-$(CONFIG_PHY_QCOM_QMP) += \
9− phy-qcom-qmp-combo.o \
10− phy-qcom-qmp-pcie.o \
11− phy-qcom-qmp-pcie-msm8996.o \
12− phy-qcom-qmp-ufs.o \
13− phy-qcom-qmp-usb.o
8+
9+obj-$(CONFIG_PHY_QCOM_QMP_COMBO) += phy-qcom-qmp-combo.o
10+obj-$(CONFIG_PHY_QCOM_QMP_PCIE) += phy-qcom-qmp-pcie.o
11+obj-$(CONFIG_PHY_QCOM_QMP_PCIE_8996) += phy-qcom-qmp-pcie-msm8996.o
12+obj-$(CONFIG_PHY_QCOM_QMP_UFS) += phy-qcom-qmp-ufs.o
13+obj-$(CONFIG_PHY_QCOM_QMP_USB) += phy-qcom-qmp-usb.o
1414
1515 obj-$(CONFIG_PHY_QCOM_QUSB2) += phy-qcom-qusb2.o
16+obj-$(CONFIG_PHY_QCOM_SNPS_EUSB2) += phy-qcom-snps-eusb2.o
17+obj-$(CONFIG_PHY_QCOM_EUSB2_REPEATER) += phy-qcom-eusb2-repeater.o
1618 obj-$(CONFIG_PHY_QCOM_USB_HS) += phy-qcom-usb-hs.o
1719 obj-$(CONFIG_PHY_QCOM_USB_HSIC) += phy-qcom-usb-hsic.o
1820 obj-$(CONFIG_PHY_QCOM_USB_HS_28NM) += phy-qcom-usb-hs-28nm.o
drivers/phy/qualcomm/phy-qcom-eusb2-repeater.c+259−0
@@ -0,0 +1,259 @@
1+// SPDX-License-Identifier: GPL-2.0
2+/*
3+ * Copyright (c) 2023, Linaro Limited
4+ */
5+
6+#include <linux/module.h>
7+#include <linux/platform_device.h>
8+#include <linux/regulator/consumer.h>
9+#include <linux/regmap.h>
10+#include <linux/of.h>
11+#include <linux/of_device.h>
12+#include <linux/phy/phy.h>
13+
14+/* eUSB2 status registers */
15+#define EUSB2_RPTR_STATUS 0x08
16+#define RPTR_OK BIT(7)
17+
18+/* eUSB2 control registers */
19+#define EUSB2_EN_CTL1 0x46
20+#define EUSB2_RPTR_EN BIT(7)
21+
22+#define EUSB2_FORCE_EN_5 0xe8
23+#define F_CLK_19P2M_EN BIT(6)
24+
25+#define EUSB2_FORCE_VAL_5 0xeD
26+#define V_CLK_19P2M_EN BIT(6)
27+
28+#define EUSB2_TUNE_IUSB2 0x51
29+#define EUSB2_TUNE_SQUELCH_U 0x54
30+#define EUSB2_TUNE_USB2_PREEM 0x57
31+
32+#define QCOM_EUSB2_REPEATER_INIT_CFG(o, v) \
33+ { \
34+ .offset = o, \
35+ .val = v, \
36+ }
37+
38+struct eusb2_repeater_init_tbl {
39+ unsigned int offset;
40+ unsigned int val;
41+};
42+
43+struct eusb2_repeater_cfg {
44+ const struct eusb2_repeater_init_tbl *init_tbl;
45+ int init_tbl_num;
46+ const char * const *vreg_list;
47+ int num_vregs;
48+};
49+
50+struct eusb2_repeater {
51+ struct device *dev;
52+ struct regmap *regmap;
53+ struct phy *phy;
54+ struct regulator_bulk_data *vregs;
55+ const struct eusb2_repeater_cfg *cfg;
56+ u16 base;
57+ enum phy_mode mode;
58+};
59+
60+static const char * const pm8550b_vreg_l[] = {
61+ "vdd18", "vdd3",
62+};
63+
64+static const struct eusb2_repeater_init_tbl pm8550b_init_tbl[] = {
65+ QCOM_EUSB2_REPEATER_INIT_CFG(EUSB2_TUNE_IUSB2, 0x8),
66+ QCOM_EUSB2_REPEATER_INIT_CFG(EUSB2_TUNE_SQUELCH_U, 0x3),
67+ QCOM_EUSB2_REPEATER_INIT_CFG(EUSB2_TUNE_USB2_PREEM, 0x5),
68+};
69+
70+static const struct eusb2_repeater_cfg pm8550b_eusb2_cfg = {
71+ .init_tbl = pm8550b_init_tbl,
72+ .init_tbl_num = ARRAY_SIZE(pm8550b_init_tbl),
73+ .vreg_list = pm8550b_vreg_l,
74+ .num_vregs = ARRAY_SIZE(pm8550b_vreg_l),
75+};
76+
77+static int eusb2_repeater_init_vregs(struct eusb2_repeater *rptr)
78+{
79+ int num = rptr->cfg->num_vregs;
80+ struct device *dev = rptr->dev;
81+ int i;
82+
83+ rptr->vregs = devm_kcalloc(dev, num, sizeof(*rptr->vregs), GFP_KERNEL);
84+ if (!rptr->vregs)
85+ return -ENOMEM;
86+
87+ for (i = 0; i < num; i++)
88+ rptr->vregs[i].supply = rptr->cfg->vreg_list[i];
89+
90+ return devm_regulator_bulk_get(dev, num, rptr->vregs);
91+}
92+
93+static int eusb2_repeater_init(struct phy *phy)
94+{
95+ struct eusb2_repeater *rptr = phy_get_drvdata(phy);
96+ const struct eusb2_repeater_init_tbl *init_tbl = rptr->cfg->init_tbl;
97+ int num = rptr->cfg->init_tbl_num;
98+ u32 val;
99+ int ret;
100+ int i;
101+
102+ ret = regulator_bulk_enable(rptr->cfg->num_vregs, rptr->vregs);
103+ if (ret)
104+ return ret;
105+
106+ regmap_update_bits(rptr->regmap, rptr->base + EUSB2_EN_CTL1,
107+ EUSB2_RPTR_EN, EUSB2_RPTR_EN);
108+
109+ for (i = 0; i < num; i++)
110+ regmap_update_bits(rptr->regmap,
111+ rptr->base + init_tbl[i].offset,
112+ init_tbl[i].val, init_tbl[i].val);
113+
114+ ret = regmap_read_poll_timeout(rptr->regmap,
115+ rptr->base + EUSB2_RPTR_STATUS, val,
116+ val & RPTR_OK, 10, 5);
117+ if (ret)
118+ dev_err(rptr->dev, "initialization timed-out\n");
119+
120+ return ret;
121+}
122+
123+static int eusb2_repeater_set_mode(struct phy *phy,
124+ enum phy_mode mode, int submode)
125+{
126+ struct eusb2_repeater *rptr = phy_get_drvdata(phy);
127+
128+ switch (mode) {
129+ case PHY_MODE_USB_HOST:
130+ /*
131+ * CM.Lx is prohibited when repeater is already into Lx state as
132+ * per eUSB 1.2 Spec. Below implement software workaround until
133+ * PHY and controller is fixing seen observation.
134+ */
135+ regmap_update_bits(rptr->regmap, rptr->base + EUSB2_FORCE_EN_5,
136+ F_CLK_19P2M_EN, F_CLK_19P2M_EN);
137+ regmap_update_bits(rptr->regmap, rptr->base + EUSB2_FORCE_VAL_5,
138+ V_CLK_19P2M_EN, V_CLK_19P2M_EN);
139+ break;
140+ case PHY_MODE_USB_DEVICE:
141+ /*
142+ * In device mode clear host mode related workaround as there
143+ * is no repeater reset available, and enable/disable of
144+ * repeater doesn't clear previous value due to shared
145+ * regulators (say host <-> device mode switch).
146+ */
147+ regmap_update_bits(rptr->regmap, rptr->base + EUSB2_FORCE_EN_5,
148+ F_CLK_19P2M_EN, 0);
149+ regmap_update_bits(rptr->regmap, rptr->base + EUSB2_FORCE_VAL_5,
150+ V_CLK_19P2M_EN, 0);
151+ break;
152+ default:
153+ return -EINVAL;
154+ }
155+
156+ return 0;
157+}
158+
159+static int eusb2_repeater_exit(struct phy *phy)
160+{
161+ struct eusb2_repeater *rptr = phy_get_drvdata(phy);
162+
163+ return regulator_bulk_disable(rptr->cfg->num_vregs, rptr->vregs);
164+}
165+
166+static const struct phy_ops eusb2_repeater_ops = {
167+ .init = eusb2_repeater_init,
168+ .exit = eusb2_repeater_exit,
169+ .set_mode = eusb2_repeater_set_mode,
170+ .owner = THIS_MODULE,
171+};
172+
173+static int eusb2_repeater_probe(struct platform_device *pdev)
174+{
175+ struct eusb2_repeater *rptr;
176+ struct device *dev = &pdev->dev;
177+ struct phy_provider *phy_provider;
178+ struct device_node *np = dev->of_node;
179+ u32 res;
180+ int ret;
181+
182+ rptr = devm_kzalloc(dev, sizeof(*rptr), GFP_KERNEL);
183+ if (!rptr)
184+ return -ENOMEM;
185+
186+ rptr->dev = dev;
187+ dev_set_drvdata(dev, rptr);
188+
189+ rptr->cfg = of_device_get_match_data(dev);
190+ if (!rptr->cfg)
191+ return -EINVAL;
192+
193+ rptr->regmap = dev_get_regmap(dev->parent, NULL);
194+ if (!rptr->regmap)
195+ return -ENODEV;
196+
197+ ret = of_property_read_u32(np, "reg", &res);
198+ if (ret < 0)
199+ return ret;
200+
201+ rptr->base = res;
202+
203+ ret = eusb2_repeater_init_vregs(rptr);
204+ if (ret < 0) {
205+ dev_err(dev, "unable to get supplies\n");
206+ return ret;
207+ }
208+
209+ rptr->phy = devm_phy_create(dev, np, &eusb2_repeater_ops);
210+ if (IS_ERR(rptr->phy)) {
211+ dev_err(dev, "failed to create PHY: %d\n", ret);
212+ return PTR_ERR(rptr->phy);
213+ }
214+
215+ phy_set_drvdata(rptr->phy, rptr);
216+
217+ phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
218+ if (IS_ERR(phy_provider))
219+ return PTR_ERR(phy_provider);
220+
221+ dev_info(dev, "Registered Qcom-eUSB2 repeater\n");
222+
223+ return 0;
224+}
225+
226+static int eusb2_repeater_remove(struct platform_device *pdev)
227+{
228+ struct eusb2_repeater *rptr = platform_get_drvdata(pdev);
229+
230+ if (!rptr)
231+ return 0;
232+
233+ eusb2_repeater_exit(rptr->phy);
234+
235+ return 0;
236+}
237+
238+static const struct of_device_id eusb2_repeater_of_match_table[] = {
239+ {
240+ .compatible = "qcom,pm8550b-eusb2-repeater",
241+ .data = &pm8550b_eusb2_cfg,
242+ },
243+ { },
244+};
245+MODULE_DEVICE_TABLE(of, eusb2_repeater_of_match_table);
246+
247+static struct platform_driver eusb2_repeater_driver = {
248+ .probe = eusb2_repeater_probe,
249+ .remove = eusb2_repeater_remove,
250+ .driver = {
251+ .name = "qcom-eusb2-repeater",
252+ .of_match_table = eusb2_repeater_of_match_table,
253+ },
254+};
255+
256+module_platform_driver(eusb2_repeater_driver);
257+
258+MODULE_DESCRIPTION("Qualcomm PMIC eUSB2 Repeater driver");
259+MODULE_LICENSE("GPL");
drivers/phy/qualcomm/phy-qcom-pcie2.c+5−1
@@ -243,7 +243,11 @@ static int phy_pipe_clksrc_register(struct qcom_phy *qphy) · 242 unmodified lines
243243 fixed->fixed_rate = 250000000;
244244 fixed->hw.init = &init;
245245
246− return devm_clk_hw_register(qphy->dev, &fixed->hw);
246+ ret = devm_clk_hw_register(qphy->dev, &fixed->hw);
247+ if (ret < 0)
248+ return ret;
249+
250+ return devm_of_clk_add_hw_provider(qphy->dev, of_clk_hw_simple_get, &fixed->hw);
247251 }
248252
249253 static int qcom_pcie2_phy_probe(struct platform_device *pdev)
drivers/phy/qualcomm/phy-qcom-qmp-combo.c+724−26
@@ -23,6 +23,10 @@ · 22 unmodified lines
2323 #include <dt-bindings/phy/phy-qcom-qmp.h>
2424
2525 #include "phy-qcom-qmp.h"
26+#include "phy-qcom-qmp-pcs-misc-v3.h"
27+#include "phy-qcom-qmp-pcs-usb-v4.h"
28+#include "phy-qcom-qmp-pcs-usb-v5.h"
29+#include "phy-qcom-qmp-pcs-usb-v6.h"
2630
2731 /* QPHY_SW_RESET bit */
2832 #define SW_RESET BIT(0)
@@ -56,9 +60,6 @@ · 27 unmodified lines
5660 /* QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR register bits */
5761 #define IRQ_CLEAR BIT(0)
5862
59−/* QPHY_PCS_LFPS_RXTERM_IRQ_STATUS register bits */
60−#define RCVR_DETECT BIT(0)
61−
6263 /* QPHY_V3_PCS_MISC_CLAMP_ENABLE register bits */
6364 #define CLAMP_EN BIT(0) /* enables i/o clamp_n */
6465
@@ -96,31 +97,29 @@ enum qphy_reg_layout { · 31 unmodified lines
9697 QPHY_PCS_STATUS,
9798 QPHY_PCS_AUTONOMOUS_MODE_CTRL,
9899 QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR,
99− QPHY_PCS_LFPS_RXTERM_IRQ_STATUS,
100100 QPHY_PCS_POWER_DOWN_CONTROL,
101101 /* Keep last to ensure regs_layout arrays are properly initialized */
102102 QPHY_LAYOUT_SIZE
103103 };
104104
105105 static const unsigned int qmp_v3_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = {
106− [QPHY_SW_RESET] = 0x00,
107− [QPHY_START_CTRL] = 0x08,
108− [QPHY_PCS_STATUS] = 0x174,
109− [QPHY_PCS_POWER_DOWN_CONTROL] = 0x04,
110− [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = 0x0d8,
111− [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = 0x0dc,
112− [QPHY_PCS_LFPS_RXTERM_IRQ_STATUS] = 0x170,
106+ [QPHY_SW_RESET] = QPHY_V3_PCS_SW_RESET,
107+ [QPHY_START_CTRL] = QPHY_V3_PCS_START_CONTROL,
108+ [QPHY_PCS_STATUS] = QPHY_V3_PCS_PCS_STATUS,
109+ [QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V3_PCS_POWER_DOWN_CONTROL,
110+ [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = QPHY_V3_PCS_AUTONOMOUS_MODE_CTRL,
111+ [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = QPHY_V3_PCS_LFPS_RXTERM_IRQ_CLEAR,
113112 };
114113
115114 static const unsigned int qmp_v4_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = {
116− [QPHY_SW_RESET] = 0x00,
117− [QPHY_START_CTRL] = 0x44,
118− [QPHY_PCS_STATUS] = 0x14,
119− [QPHY_PCS_POWER_DOWN_CONTROL] = 0x40,
115+ [QPHY_SW_RESET] = QPHY_V4_PCS_SW_RESET,
116+ [QPHY_START_CTRL] = QPHY_V4_PCS_START_CONTROL,
117+ [QPHY_PCS_STATUS] = QPHY_V4_PCS_PCS_STATUS1,
118+ [QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V4_PCS_POWER_DOWN_CONTROL,
120119
121120 /* In PCS_USB */
122− [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = 0x008,
123− [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = 0x014,
121+ [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = QPHY_V4_PCS_USB3_AUTONOMOUS_MODE_CTRL,
122+ [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = QPHY_V4_PCS_USB3_LFPS_RXTERM_IRQ_CLEAR,
124123 };
125124
126125 static const struct qmp_phy_init_tbl qmp_v3_usb3_serdes_tbl[] = {
@@ -311,6 +310,70 @@ static const struct qmp_phy_init_tbl qmp_v3_usb3_pcs_tbl[] = { · 184 unmodified lines
311310 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13),
312311 };
313312
313+static const struct qmp_phy_init_tbl sm6350_usb3_rx_tbl[] = {
314+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
315+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
316+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4e),
317+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x18),
318+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
319+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
320+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03),
321+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x16),
322+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x05),
323+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x75),
324+};
325+
326+static const struct qmp_phy_init_tbl sm6350_usb3_pcs_tbl[] = {
327+ /* FLL settings */
328+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83),
329+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09),
330+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2),
331+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x40),
332+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02),
333+
334+ /* Lock Det settings */
335+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1),
336+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f),
337+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47),
338+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG2, 0x1b),
339+
340+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0xcc),
341+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V0, 0x9f),
342+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V1, 0x9f),
343+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V2, 0xb7),
344+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V3, 0x4e),
345+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V4, 0x65),
346+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_LS, 0x6b),
347+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x15),
348+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0d),
349+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V1, 0x15),
350+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V1, 0x0d),
351+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V2, 0x15),
352+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V2, 0x0d),
353+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V3, 0x15),
354+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V3, 0x1d),
355+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V4, 0x15),
356+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V4, 0x0d),
357+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_LS, 0x15),
358+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_LS, 0x0d),
359+
360+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RATE_SLEW_CNTRL, 0x02),
361+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
362+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44),
363+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
364+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
365+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
366+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40),
367+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00),
368+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75),
369+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86),
370+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13),
371+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_DET_HIGH_COUNT_VAL, 0x04),
372+
373+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_REFGEN_REQ_CONFIG1, 0x21),
374+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_REFGEN_REQ_CONFIG2, 0x60),
375+};
376+
314377 static const struct qmp_phy_init_tbl sm8150_usb3_serdes_tbl[] = {
315378 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_EN_CENTER, 0x01),
316379 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER1, 0x31),
@@ -494,6 +557,223 @@ static const struct qmp_phy_init_tbl sm8250_usb3_pcs_usb_tbl[] = { · 177 unmodified lines
494557 QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07),
495558 };
496559
560+static const struct qmp_phy_init_tbl sm8350_usb3_tx_tbl[] = {
561+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_TX, 0x00),
562+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_RX, 0x00),
563+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x16),
564+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x0e),
565+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0x35),
566+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_3, 0x3f),
567+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_4, 0x7f),
568+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_5, 0x3f),
569+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_RCV_DETECT_LVL_2, 0x12),
570+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_PI_QEC_CTRL, 0x21),
571+};
572+
573+static const struct qmp_phy_init_tbl sm8350_usb3_rx_tbl[] = {
574+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FO_GAIN, 0x0a),
575+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_GAIN, 0x05),
576+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
577+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
578+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
579+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
580+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0x99),
581+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH1, 0x08),
582+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH2, 0x08),
583+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN1, 0x00),
584+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN2, 0x04),
585+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL1, 0x54),
586+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x0f),
587+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
588+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
589+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
590+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
591+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
592+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47),
593+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_CNTRL, 0x04),
594+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
595+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0xbb),
596+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0x7b),
597+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xbb),
598+ QMP_PHY_INIT_CFG_LANE(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x3d, 1),
599+ QMP_PHY_INIT_CFG_LANE(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x3c, 2),
600+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0xdb),
601+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0x64),
602+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0x24),
603+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0xd2),
604+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x13),
605+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xa9),
606+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_EN_TIMER, 0x04),
607+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
608+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_AUX_DATA_TCOARSE_TFINE, 0xa0),
609+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_DCC_CTRL1, 0x0c),
610+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_GM_CAL, 0x00),
611+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_VTH_CODE, 0x10),
612+};
613+
614+static const struct qmp_phy_init_tbl sm8350_usb3_pcs_tbl[] = {
615+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
616+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
617+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0),
618+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07),
619+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG3, 0x20),
620+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13),
621+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21),
622+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa),
623+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0a),
624+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88),
625+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13),
626+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c),
627+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b),
628+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10),
629+};
630+
631+static const struct qmp_phy_init_tbl sm8350_usb3_pcs_usb_tbl[] = {
632+ QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_RCVR_DTCT_DLY_U3_L, 0x40),
633+ QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_RCVR_DTCT_DLY_U3_H, 0x00),
634+ QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
635+ QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07),
636+};
637+
638+static const struct qmp_phy_init_tbl sm8550_usb3_serdes_tbl[] = {
639+ QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE1_MODE1, 0xc0),
640+ QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE2_MODE1, 0x01),
641+ QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE1, 0x02),
642+ QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE1, 0x16),
643+ QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE1, 0x36),
644+ QMP_PHY_INIT_CFG(QSERDES_V6_COM_CORECLK_DIV_MODE1, 0x04),
645+ QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE1, 0x16),
646+ QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE1, 0x41),
647+ QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE1, 0x41),
648+ QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MSB_MODE1, 0x00),
649+ QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START1_MODE1, 0x55),
650+ QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START2_MODE1, 0x75),
651+ QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START3_MODE1, 0x01),
652+ QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_SEL_1, 0x01),
653+ QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE1_MODE1, 0x25),
654+ QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE2_MODE1, 0x02),
655+ QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0x5c),
656+ QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x0f),
657+ QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0x5c),
658+ QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x0f),
659+ QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE1_MODE0, 0xc0),
660+ QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE2_MODE0, 0x01),
661+ QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE0, 0x02),
662+ QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE0, 0x16),
663+ QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE0, 0x36),
664+ QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x08),
665+ QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x1a),
666+ QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x41),
667+ QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MSB_MODE0, 0x00),
668+ QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START1_MODE0, 0x55),
669+ QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START2_MODE0, 0x75),
670+ QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START3_MODE0, 0x01),
671+ QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE1_MODE0, 0x25),
672+ QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE2_MODE0, 0x02),
673+ QMP_PHY_INIT_CFG(QSERDES_V6_COM_BG_TIMER, 0x0a),
674+ QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_EN_CENTER, 0x01),
675+ QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_PER1, 0x62),
676+ QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_PER2, 0x02),
677+ QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYSCLK_BUF_ENABLE, 0x0c),
678+ QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYSCLK_EN_SEL, 0x1a),
679+ QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_CFG, 0x14),
680+ QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAP, 0x04),
681+ QMP_PHY_INIT_CFG(QSERDES_V6_COM_CORE_CLK_EN, 0x20),
682+ QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_CONFIG_1, 0x16),
683+ QMP_PHY_INIT_CFG(QSERDES_V6_COM_AUTO_GAIN_ADJ_CTRL_1, 0xb6),
684+ QMP_PHY_INIT_CFG(QSERDES_V6_COM_AUTO_GAIN_ADJ_CTRL_2, 0x4b),
685+ QMP_PHY_INIT_CFG(QSERDES_V6_COM_AUTO_GAIN_ADJ_CTRL_3, 0x37),
686+ QMP_PHY_INIT_CFG(QSERDES_V6_COM_ADDITIONAL_MISC, 0x0c),
687+};
688+
689+static const struct qmp_phy_init_tbl sm8550_usb3_tx_tbl[] = {
690+ QMP_PHY_INIT_CFG(QSERDES_V6_TX_RES_CODE_LANE_TX, 0x00),
691+ QMP_PHY_INIT_CFG(QSERDES_V6_TX_RES_CODE_LANE_RX, 0x00),
692+ QMP_PHY_INIT_CFG(QSERDES_V6_TX_RES_CODE_LANE_OFFSET_TX, 0x1f),
693+ QMP_PHY_INIT_CFG(QSERDES_V6_TX_RES_CODE_LANE_OFFSET_RX, 0x09),
694+ QMP_PHY_INIT_CFG(QSERDES_V6_TX_LANE_MODE_1, 0xf5),
695+ QMP_PHY_INIT_CFG(QSERDES_V6_TX_LANE_MODE_3, 0x3f),
696+ QMP_PHY_INIT_CFG(QSERDES_V6_TX_LANE_MODE_4, 0x3f),
697+ QMP_PHY_INIT_CFG(QSERDES_V6_TX_LANE_MODE_5, 0x5f),
698+ QMP_PHY_INIT_CFG(QSERDES_V6_TX_RCV_DETECT_LVL_2, 0x12),
699+ QMP_PHY_INIT_CFG_LANE(QSERDES_V6_TX_PI_QEC_CTRL, 0x21, 1),
700+ QMP_PHY_INIT_CFG_LANE(QSERDES_V6_TX_PI_QEC_CTRL, 0x05, 2),
701+};
702+
703+static const struct qmp_phy_init_tbl sm8550_usb3_rx_tbl[] = {
704+ QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_FO_GAIN, 0x0a),
705+ QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_SO_GAIN, 0x06),
706+ QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
707+ QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
708+ QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
709+ QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
710+ QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_PI_CONTROLS, 0x99),
711+ QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_SB2_THRESH1, 0x08),
712+ QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_SB2_THRESH2, 0x08),
713+ QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_SB2_GAIN1, 0x00),
714+ QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_SB2_GAIN2, 0x0a),
715+ QMP_PHY_INIT_CFG(QSERDES_V6_RX_AUX_DATA_TCOARSE_TFINE, 0xa0),
716+ QMP_PHY_INIT_CFG(QSERDES_V6_RX_VGA_CAL_CNTRL1, 0x54),
717+ QMP_PHY_INIT_CFG(QSERDES_V6_RX_VGA_CAL_CNTRL2, 0x0f),
718+ QMP_PHY_INIT_CFG(QSERDES_V6_RX_GM_CAL, 0x13),
719+ QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
720+ QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
721+ QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
722+ QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_IDAC_TSETTLE_LOW, 0x07),
723+ QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
724+ QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47),
725+ QMP_PHY_INIT_CFG(QSERDES_V6_RX_SIGDET_CNTRL, 0x04),
726+ QMP_PHY_INIT_CFG(QSERDES_V6_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
727+ QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_01_LOW, 0xdc),
728+ QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_01_HIGH, 0x5c),
729+ QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_01_HIGH2, 0x9c),
730+ QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_01_HIGH3, 0x1d),
731+ QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_01_HIGH4, 0x09),
732+ QMP_PHY_INIT_CFG(QSERDES_V6_RX_DFE_EN_TIMER, 0x04),
733+ QMP_PHY_INIT_CFG(QSERDES_V6_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
734+ QMP_PHY_INIT_CFG(QSERDES_V6_RX_DCC_CTRL1, 0x0c),
735+ QMP_PHY_INIT_CFG(QSERDES_V6_RX_VTH_CODE, 0x10),
736+ QMP_PHY_INIT_CFG(QSERDES_V6_RX_SIGDET_CAL_CTRL1, 0x14),
737+ QMP_PHY_INIT_CFG(QSERDES_V6_RX_SIGDET_CAL_TRIM, 0x08),
738+
739+ QMP_PHY_INIT_CFG_LANE(QSERDES_V6_RX_RX_MODE_00_LOW, 0x3f, 1),
740+ QMP_PHY_INIT_CFG_LANE(QSERDES_V6_RX_RX_MODE_00_HIGH, 0xbf, 1),
741+ QMP_PHY_INIT_CFG_LANE(QSERDES_V6_RX_RX_MODE_00_HIGH2, 0xff, 1),
742+ QMP_PHY_INIT_CFG_LANE(QSERDES_V6_RX_RX_MODE_00_HIGH3, 0xdf, 1),
743+ QMP_PHY_INIT_CFG_LANE(QSERDES_V6_RX_RX_MODE_00_HIGH4, 0xed, 1),
744+
745+ QMP_PHY_INIT_CFG_LANE(QSERDES_V6_RX_RX_MODE_00_LOW, 0xbf, 2),
746+ QMP_PHY_INIT_CFG_LANE(QSERDES_V6_RX_RX_MODE_00_HIGH, 0xbf, 2),
747+ QMP_PHY_INIT_CFG_LANE(QSERDES_V6_RX_RX_MODE_00_HIGH2, 0xbf, 2),
748+ QMP_PHY_INIT_CFG_LANE(QSERDES_V6_RX_RX_MODE_00_HIGH3, 0xdf, 2),
749+ QMP_PHY_INIT_CFG_LANE(QSERDES_V6_RX_RX_MODE_00_HIGH4, 0xfd, 2),
750+};
751+
752+static const struct qmp_phy_init_tbl sm8550_usb3_pcs_tbl[] = {
753+ QMP_PHY_INIT_CFG(QPHY_USB_V6_PCS_LOCK_DETECT_CONFIG1, 0xc4),
754+ QMP_PHY_INIT_CFG(QPHY_USB_V6_PCS_LOCK_DETECT_CONFIG2, 0x89),
755+ QMP_PHY_INIT_CFG(QPHY_USB_V6_PCS_LOCK_DETECT_CONFIG3, 0x20),
756+ QMP_PHY_INIT_CFG(QPHY_USB_V6_PCS_LOCK_DETECT_CONFIG6, 0x13),
757+ QMP_PHY_INIT_CFG(QPHY_USB_V6_PCS_REFGEN_REQ_CONFIG1, 0x21),
758+ QMP_PHY_INIT_CFG(QPHY_USB_V6_PCS_RX_SIGDET_LVL, 0x99),
759+ QMP_PHY_INIT_CFG(QPHY_USB_V6_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
760+ QMP_PHY_INIT_CFG(QPHY_USB_V6_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
761+ QMP_PHY_INIT_CFG(QPHY_USB_V6_PCS_CDR_RESET_TIME, 0x0a),
762+ QMP_PHY_INIT_CFG(QPHY_USB_V6_PCS_ALIGN_DETECT_CONFIG1, 0x88),
763+ QMP_PHY_INIT_CFG(QPHY_USB_V6_PCS_ALIGN_DETECT_CONFIG2, 0x13),
764+ QMP_PHY_INIT_CFG(QPHY_USB_V6_PCS_PCS_TX_RX_CONFIG, 0x0c),
765+ QMP_PHY_INIT_CFG(QPHY_USB_V6_PCS_EQ_CONFIG1, 0x4b),
766+ QMP_PHY_INIT_CFG(QPHY_USB_V6_PCS_EQ_CONFIG5, 0x10),
767+ QMP_PHY_INIT_CFG(QPHY_USB_V6_PCS_USB3_POWER_STATE_CONFIG1, 0x68),
768+};
769+
770+static const struct qmp_phy_init_tbl sm8550_usb3_pcs_usb_tbl[] = {
771+ QMP_PHY_INIT_CFG(QPHY_USB_V6_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
772+ QMP_PHY_INIT_CFG(QPHY_USB_V6_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07),
773+ QMP_PHY_INIT_CFG(QPHY_USB_V6_PCS_USB3_RCVR_DTCT_DLY_U3_L, 0x40),
774+ QMP_PHY_INIT_CFG(QPHY_USB_V6_PCS_USB3_RCVR_DTCT_DLY_U3_H, 0x00),
775+};
776+
497777 static const struct qmp_phy_init_tbl qmp_v4_dp_serdes_tbl[] = {
498778 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SVS_MODE_CLK_SEL, 0x05),
499779 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x3b),
@@ -600,6 +880,20 @@ static const struct qmp_phy_init_tbl qmp_v5_dp_serdes_tbl[] = { · 100 unmodified lines
600880 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORE_CLK_EN, 0x1f),
601881 };
602882
883+static const struct qmp_phy_init_tbl qmp_v5_dp_tx_tbl[] = {
884+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_VMODE_CTRL1, 0x40),
885+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_PRE_STALL_LDO_BOOST_EN, 0x30),
886+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_INTERFACE_SELECT, 0x3b),
887+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_CLKBUF_ENABLE, 0x0f),
888+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_RESET_TSYNC_EN, 0x03),
889+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_TRAN_DRVR_EMP_EN, 0x0f),
890+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_PARRATE_REC_DETECT_IDLE_EN, 0x00),
891+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_TX_INTERFACE_MODE, 0x00),
892+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x11),
893+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x11),
894+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_TX_BAND, 0x04),
895+};
896+
603897 static const struct qmp_phy_init_tbl qmp_v5_5nm_dp_tx_tbl[] = {
604898 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_LANE_MODE_3, 0x51),
605899 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_TRANSCEIVER_BIAS_EN, 0x1a),
@@ -615,6 +909,91 @@ static const struct qmp_phy_init_tbl qmp_v5_5nm_dp_tx_tbl[] = { · 9 unmodified lines
615909 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_TX_BAND, 0x01),
616910 };
617911
912+static const struct qmp_phy_init_tbl qmp_v6_dp_serdes_tbl[] = {
913+ QMP_PHY_INIT_CFG(QSERDES_V6_COM_SVS_MODE_CLK_SEL, 0x15),
914+ QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYSCLK_EN_SEL, 0x3b),
915+ QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYS_CLK_CTRL, 0x02),
916+ QMP_PHY_INIT_CFG(QSERDES_V6_COM_CLK_ENABLE1, 0x0c),
917+ QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYSCLK_BUF_ENABLE, 0x06),
918+ QMP_PHY_INIT_CFG(QSERDES_V6_COM_CLK_SELECT, 0x30),
919+ QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_IVCO, 0x0f),
920+ QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE0, 0x36),
921+ QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE0, 0x16),
922+ QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE0, 0x06),
923+ QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START1_MODE0, 0x00),
924+ QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_CONFIG_1, 0x12),
925+ QMP_PHY_INIT_CFG(QSERDES_V6_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
926+ QMP_PHY_INIT_CFG(QSERDES_V6_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
927+ QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAP, 0x00),
928+ QMP_PHY_INIT_CFG(QSERDES_V6_COM_BG_TIMER, 0x0a),
929+ QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CORE_CLK_DIV_MODE0, 0x14),
930+ QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_CTRL, 0x00),
931+ QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_BIAS_EN_CLK_BUFLR_EN, 0x17),
932+ QMP_PHY_INIT_CFG(QSERDES_V6_COM_CORE_CLK_EN, 0x0f),
933+};
934+
935+static const struct qmp_phy_init_tbl qmp_v6_dp_tx_tbl[] = {
936+ QMP_PHY_INIT_CFG(QSERDES_V6_TX_VMODE_CTRL1, 0x40),
937+ QMP_PHY_INIT_CFG(QSERDES_V6_TX_PRE_STALL_LDO_BOOST_EN, 0x30),
938+ QMP_PHY_INIT_CFG(QSERDES_V6_TX_INTERFACE_SELECT, 0x3b),
939+ QMP_PHY_INIT_CFG(QSERDES_V6_TX_CLKBUF_ENABLE, 0x0f),
940+ QMP_PHY_INIT_CFG(QSERDES_V6_TX_RESET_TSYNC_EN, 0x03),
941+ QMP_PHY_INIT_CFG(QSERDES_V6_TX_TRAN_DRVR_EMP_EN, 0x0f),
942+ QMP_PHY_INIT_CFG(QSERDES_V6_TX_PARRATE_REC_DETECT_IDLE_EN, 0x00),
943+ QMP_PHY_INIT_CFG(QSERDES_V6_TX_TX_INTERFACE_MODE, 0x00),
944+ QMP_PHY_INIT_CFG(QSERDES_V6_TX_RES_CODE_LANE_OFFSET_TX, 0x0c),
945+ QMP_PHY_INIT_CFG(QSERDES_V6_TX_RES_CODE_LANE_OFFSET_RX, 0x0c),
946+ QMP_PHY_INIT_CFG(QSERDES_V6_TX_TX_BAND, 0x4),
947+};
948+
949+static const struct qmp_phy_init_tbl qmp_v6_dp_serdes_tbl_rbr[] = {
950+ QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_SEL_1, 0x05),
951+ QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x34),
952+ QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START2_MODE0, 0xc0),
953+ QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START3_MODE0, 0x0b),
954+ QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x37),
955+ QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x04),
956+ QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_EN, 0x04),
957+ QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0x71),
958+ QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x0c),
959+};
960+
961+static const struct qmp_phy_init_tbl qmp_v6_dp_serdes_tbl_hbr[] = {
962+ QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_SEL_1, 0x03),
963+ QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x34),
964+ QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START2_MODE0, 0xc0),
965+ QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START3_MODE0, 0x0b),
966+ QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x07),
967+ QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x07),
968+ QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_EN, 0x08),
969+ QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0x71),
970+ QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x0c),
971+};
972+
973+static const struct qmp_phy_init_tbl qmp_v6_dp_serdes_tbl_hbr2[] = {
974+ QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_SEL_1, 0x01),
975+ QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x46),
976+ QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START2_MODE0, 0x00),
977+ QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START3_MODE0, 0x05),
978+ QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x0f),
979+ QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x0e),
980+ QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_EN, 0x08),
981+ QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0x97),
982+ QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x10),
983+};
984+
985+static const struct qmp_phy_init_tbl qmp_v6_dp_serdes_tbl_hbr3[] = {
986+ QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_SEL_1, 0x00),
987+ QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x34),
988+ QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START2_MODE0, 0xc0),
989+ QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START3_MODE0, 0x0b),
990+ QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x17),
991+ QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x15),
992+ QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_EN, 0x08),
993+ QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0x71),
994+ QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x0c),
995+};
996+
618997 static const struct qmp_phy_init_tbl sc8280xp_usb43dp_serdes_tbl[] = {
619998 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_EN_CENTER, 0x01),
620999 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER1, 0x31),
@@ -768,6 +1147,27 @@ static const u8 qmp_dp_v3_voltage_swing_hbr_rbr[4][4] = { · 147 unmodified lines
7681147 { 0x1f, 0xff, 0xff, 0xff }
7691148 };
7701149
1150+static const u8 qmp_dp_v4_pre_emphasis_hbr3_hbr2[4][4] = {
1151+ { 0x00, 0x0c, 0x15, 0x1b },
1152+ { 0x02, 0x0e, 0x16, 0xff },
1153+ { 0x02, 0x11, 0xff, 0xff },
1154+ { 0x04, 0xff, 0xff, 0xff }
1155+};
1156+
1157+static const u8 qmp_dp_v4_pre_emphasis_hbr_rbr[4][4] = {
1158+ { 0x00, 0x0d, 0x14, 0x1a },
1159+ { 0x00, 0x0e, 0x15, 0xff },
1160+ { 0x00, 0x0d, 0xff, 0xff },
1161+ { 0x03, 0xff, 0xff, 0xff }
1162+};
1163+
1164+static const u8 qmp_dp_v4_voltage_swing_hbr_rbr[4][4] = {
1165+ { 0x08, 0x0f, 0x16, 0x1f },
1166+ { 0x11, 0x1e, 0x1f, 0xff },
1167+ { 0x16, 0x1f, 0xff, 0xff },
1168+ { 0x1f, 0xff, 0xff, 0xff }
1169+};
1170+
7711171 static const u8 qmp_dp_v5_pre_emphasis_hbr3_hbr2[4][4] = {
7721172 { 0x20, 0x2c, 0x35, 0x3b },
7731173 { 0x22, 0x2e, 0x36, 0xff },
@@ -796,6 +1196,13 @@ static const u8 qmp_dp_v5_voltage_swing_hbr_rbr[4][4] = { · 22 unmodified lines
7961196 { 0x3f, 0xff, 0xff, 0xff }
7971197 };
7981198
1199+static const u8 qmp_dp_v6_pre_emphasis_hbr_rbr[4][4] = {
1200+ { 0x20, 0x2d, 0x34, 0x3a },
1201+ { 0x20, 0x2e, 0x35, 0xff },
1202+ { 0x20, 0x2e, 0xff, 0xff },
1203+ { 0x22, 0xff, 0xff, 0xff }
1204+};
1205+
7991206 struct qmp_combo;
8001207
8011208 struct qmp_combo_offsets {
@@ -809,6 +1216,8 @@ struct qmp_combo_offsets { · 7 unmodified lines
8091216 u16 usb3_pcs;
8101217 u16 usb3_pcs_usb;
8111218 u16 dp_serdes;
1219+ u16 dp_txa;
1220+ u16 dp_txb;
8121221 u16 dp_dp_phy;
8131222 };
8141223
@@ -928,6 +1337,9 @@ static int qmp_v4_calibrate_dp_phy(struct qmp_combo *qmp); · 113 unmodified lines
9281337
9291338 static int qmp_v5_configure_dp_phy(struct qmp_combo *qmp);
9301339
1340+static void qmp_v6_dp_aux_init(struct qmp_combo *qmp);
1341+static int qmp_v6_configure_dp_phy(struct qmp_combo *qmp);
1342+
9311343 static inline void qphy_setbits(void __iomem *base, u32 offset, u32 val)
9321344 {
9331345 u32 reg;
@@ -975,6 +1387,21 @@ static const char * const sc7180_usb3phy_reset_l[] = { · 41 unmodified lines
9751387 "phy",
9761388 };
9771389
1390+static const struct qmp_combo_offsets qmp_combo_offsets_v3 = {
1391+ .com = 0x0000,
1392+ .txa = 0x1200,
1393+ .rxa = 0x1400,
1394+ .txb = 0x1600,
1395+ .rxb = 0x1800,
1396+ .usb3_serdes = 0x1000,
1397+ .usb3_pcs_misc = 0x1a00,
1398+ .usb3_pcs = 0x1c00,
1399+ .dp_serdes = 0x2000,
1400+ .dp_txa = 0x2200,
1401+ .dp_txb = 0x2600,
1402+ .dp_dp_phy = 0x2a00,
1403+};
1404+
9781405 static const struct qmp_combo_offsets qmp_combo_offsets_v5 = {
9791406 .com = 0x0000,
9801407 .txa = 0x0400,
@@ -989,6 +1416,22 @@ static const struct qmp_combo_offsets qmp_combo_offsets_v5 = { · 8 unmodified lines
9891416 .dp_dp_phy = 0x2200,
9901417 };
9911418
1419+static const struct qmp_combo_offsets qmp_combo_offsets_v6 = {
1420+ .com = 0x0000,
1421+ .txa = 0x1200,
1422+ .rxa = 0x1400,
1423+ .txb = 0x1600,
1424+ .rxb = 0x1800,
1425+ .usb3_serdes = 0x1000,
1426+ .usb3_pcs_misc = 0x1a00,
1427+ .usb3_pcs = 0x1c00,
1428+ .usb3_pcs_usb = 0x1f00,
1429+ .dp_serdes = 0x2000,
1430+ .dp_txa = 0x2200,
1431+ .dp_txb = 0x2600,
1432+ .dp_dp_phy = 0x2a00,
1433+};
1434+
9921435 static const struct qmp_phy_cfg sc7180_usb3dpphy_cfg = {
9931436 .serdes_tbl = qmp_v3_usb3_serdes_tbl,
9941437 .serdes_tbl_num = ARRAY_SIZE(qmp_v3_usb3_serdes_tbl),
@@ -1172,6 +1615,51 @@ static const struct qmp_phy_cfg sc8280xp_usb43dpphy_cfg = { · 177 unmodified lines
11721615 .regs = qmp_v4_usb3phy_regs_layout,
11731616 };
11741617
1618+static const struct qmp_phy_cfg sm6350_usb3dpphy_cfg = {
1619+ .offsets = &qmp_combo_offsets_v3,
1620+
1621+ .serdes_tbl = qmp_v3_usb3_serdes_tbl,
1622+ .serdes_tbl_num = ARRAY_SIZE(qmp_v3_usb3_serdes_tbl),
1623+ .tx_tbl = qmp_v3_usb3_tx_tbl,
1624+ .tx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_tx_tbl),
1625+ .rx_tbl = sm6350_usb3_rx_tbl,
1626+ .rx_tbl_num = ARRAY_SIZE(sm6350_usb3_rx_tbl),
1627+ .pcs_tbl = sm6350_usb3_pcs_tbl,
1628+ .pcs_tbl_num = ARRAY_SIZE(sm6350_usb3_pcs_tbl),
1629+
1630+ .dp_serdes_tbl = qmp_v3_dp_serdes_tbl,
1631+ .dp_serdes_tbl_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl),
1632+ .dp_tx_tbl = qmp_v3_dp_tx_tbl,
1633+ .dp_tx_tbl_num = ARRAY_SIZE(qmp_v3_dp_tx_tbl),
1634+
1635+ .serdes_tbl_rbr = qmp_v3_dp_serdes_tbl_rbr,
1636+ .serdes_tbl_rbr_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_rbr),
1637+ .serdes_tbl_hbr = qmp_v3_dp_serdes_tbl_hbr,
1638+ .serdes_tbl_hbr_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_hbr),
1639+ .serdes_tbl_hbr2 = qmp_v3_dp_serdes_tbl_hbr2,
1640+ .serdes_tbl_hbr2_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_hbr2),
1641+ .serdes_tbl_hbr3 = qmp_v3_dp_serdes_tbl_hbr3,
1642+ .serdes_tbl_hbr3_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_hbr3),
1643+
1644+ .swing_hbr_rbr = &qmp_dp_v3_voltage_swing_hbr_rbr,
1645+ .pre_emphasis_hbr_rbr = &qmp_dp_v3_pre_emphasis_hbr_rbr,
1646+ .swing_hbr3_hbr2 = &qmp_dp_v3_voltage_swing_hbr3_hbr2,
1647+ .pre_emphasis_hbr3_hbr2 = &qmp_dp_v3_pre_emphasis_hbr3_hbr2,
1648+
1649+ .dp_aux_init = qmp_v3_dp_aux_init,
1650+ .configure_dp_tx = qmp_v3_configure_dp_tx,
1651+ .configure_dp_phy = qmp_v3_configure_dp_phy,
1652+ .calibrate_dp_phy = qmp_v3_calibrate_dp_phy,
1653+
1654+ .clk_list = qmp_v4_phy_clk_l,
1655+ .num_clks = ARRAY_SIZE(qmp_v4_phy_clk_l),
1656+ .reset_list = msm8996_usb3phy_reset_l,
1657+ .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
1658+ .vreg_list = qmp_phy_vreg_l,
1659+ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
1660+ .regs = qmp_v3_usb3phy_regs_layout,
1661+};
1662+
11751663 static const struct qmp_phy_cfg sm8250_usb3dpphy_cfg = {
11761664 .serdes_tbl = sm8150_usb3_serdes_tbl,
11771665 .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_serdes_tbl),
@@ -1220,6 +1708,102 @@ static const struct qmp_phy_cfg sm8250_usb3dpphy_cfg = { · 42 unmodified lines
12201708 .has_pwrdn_delay = true,
12211709 };
12221710
1711+static const struct qmp_phy_cfg sm8350_usb3dpphy_cfg = {
1712+ .offsets = &qmp_combo_offsets_v3,
1713+
1714+ .serdes_tbl = sm8150_usb3_serdes_tbl,
1715+ .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_serdes_tbl),
1716+ .tx_tbl = sm8350_usb3_tx_tbl,
1717+ .tx_tbl_num = ARRAY_SIZE(sm8350_usb3_tx_tbl),
1718+ .rx_tbl = sm8350_usb3_rx_tbl,
1719+ .rx_tbl_num = ARRAY_SIZE(sm8350_usb3_rx_tbl),
1720+ .pcs_tbl = sm8350_usb3_pcs_tbl,
1721+ .pcs_tbl_num = ARRAY_SIZE(sm8350_usb3_pcs_tbl),
1722+ .pcs_usb_tbl = sm8350_usb3_pcs_usb_tbl,
1723+ .pcs_usb_tbl_num = ARRAY_SIZE(sm8350_usb3_pcs_usb_tbl),
1724+
1725+ .dp_serdes_tbl = qmp_v4_dp_serdes_tbl,
1726+ .dp_serdes_tbl_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl),
1727+ .dp_tx_tbl = qmp_v5_dp_tx_tbl,
1728+ .dp_tx_tbl_num = ARRAY_SIZE(qmp_v5_dp_tx_tbl),
1729+
1730+ .serdes_tbl_rbr = qmp_v4_dp_serdes_tbl_rbr,
1731+ .serdes_tbl_rbr_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_rbr),
1732+ .serdes_tbl_hbr = qmp_v4_dp_serdes_tbl_hbr,
1733+ .serdes_tbl_hbr_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr),
1734+ .serdes_tbl_hbr2 = qmp_v4_dp_serdes_tbl_hbr2,
1735+ .serdes_tbl_hbr2_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr2),
1736+ .serdes_tbl_hbr3 = qmp_v4_dp_serdes_tbl_hbr3,
1737+ .serdes_tbl_hbr3_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr3),
1738+
1739+ .swing_hbr_rbr = &qmp_dp_v4_voltage_swing_hbr_rbr,
1740+ .pre_emphasis_hbr_rbr = &qmp_dp_v4_pre_emphasis_hbr_rbr,
1741+ .swing_hbr3_hbr2 = &qmp_dp_v3_voltage_swing_hbr3_hbr2,
1742+ .pre_emphasis_hbr3_hbr2 = &qmp_dp_v4_pre_emphasis_hbr3_hbr2,
1743+
1744+ .dp_aux_init = qmp_v4_dp_aux_init,
1745+ .configure_dp_tx = qmp_v4_configure_dp_tx,
1746+ .configure_dp_phy = qmp_v4_configure_dp_phy,
1747+ .calibrate_dp_phy = qmp_v4_calibrate_dp_phy,
1748+
1749+ .clk_list = qmp_v4_phy_clk_l,
1750+ .num_clks = ARRAY_SIZE(qmp_v4_phy_clk_l),
1751+ .reset_list = msm8996_usb3phy_reset_l,
1752+ .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
1753+ .vreg_list = qmp_phy_vreg_l,
1754+ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
1755+ .regs = qmp_v4_usb3phy_regs_layout,
1756+
1757+ .has_pwrdn_delay = true,
1758+};
1759+
1760+static const struct qmp_phy_cfg sm8550_usb3dpphy_cfg = {
1761+ .offsets = &qmp_combo_offsets_v6,
1762+
1763+ .serdes_tbl = sm8550_usb3_serdes_tbl,
1764+ .serdes_tbl_num = ARRAY_SIZE(sm8550_usb3_serdes_tbl),
1765+ .tx_tbl = sm8550_usb3_tx_tbl,
1766+ .tx_tbl_num = ARRAY_SIZE(sm8550_usb3_tx_tbl),
1767+ .rx_tbl = sm8550_usb3_rx_tbl,
1768+ .rx_tbl_num = ARRAY_SIZE(sm8550_usb3_rx_tbl),
1769+ .pcs_tbl = sm8550_usb3_pcs_tbl,
1770+ .pcs_tbl_num = ARRAY_SIZE(sm8550_usb3_pcs_tbl),
1771+ .pcs_usb_tbl = sm8550_usb3_pcs_usb_tbl,
1772+ .pcs_usb_tbl_num = ARRAY_SIZE(sm8550_usb3_pcs_usb_tbl),
1773+
1774+ .dp_serdes_tbl = qmp_v6_dp_serdes_tbl,
1775+ .dp_serdes_tbl_num = ARRAY_SIZE(qmp_v6_dp_serdes_tbl),
1776+ .dp_tx_tbl = qmp_v6_dp_tx_tbl,
1777+ .dp_tx_tbl_num = ARRAY_SIZE(qmp_v6_dp_tx_tbl),
1778+
1779+ .serdes_tbl_rbr = qmp_v6_dp_serdes_tbl_rbr,
1780+ .serdes_tbl_rbr_num = ARRAY_SIZE(qmp_v6_dp_serdes_tbl_rbr),
1781+ .serdes_tbl_hbr = qmp_v6_dp_serdes_tbl_hbr,
1782+ .serdes_tbl_hbr_num = ARRAY_SIZE(qmp_v6_dp_serdes_tbl_hbr),
1783+ .serdes_tbl_hbr2 = qmp_v6_dp_serdes_tbl_hbr2,
1784+ .serdes_tbl_hbr2_num = ARRAY_SIZE(qmp_v6_dp_serdes_tbl_hbr2),
1785+ .serdes_tbl_hbr3 = qmp_v6_dp_serdes_tbl_hbr3,
1786+ .serdes_tbl_hbr3_num = ARRAY_SIZE(qmp_v6_dp_serdes_tbl_hbr3),
1787+
1788+ .swing_hbr_rbr = &qmp_dp_v5_voltage_swing_hbr_rbr,
1789+ .pre_emphasis_hbr_rbr = &qmp_dp_v6_pre_emphasis_hbr_rbr,
1790+ .swing_hbr3_hbr2 = &qmp_dp_v5_voltage_swing_hbr3_hbr2,
1791+ .pre_emphasis_hbr3_hbr2 = &qmp_dp_v5_pre_emphasis_hbr3_hbr2,
1792+
1793+ .dp_aux_init = qmp_v6_dp_aux_init,
1794+ .configure_dp_tx = qmp_v4_configure_dp_tx,
1795+ .configure_dp_phy = qmp_v6_configure_dp_phy,
1796+ .calibrate_dp_phy = qmp_v4_calibrate_dp_phy,
1797+
1798+ .regs = qmp_v4_usb3phy_regs_layout,
1799+ .clk_list = qmp_v4_phy_clk_l,
1800+ .num_clks = ARRAY_SIZE(qmp_v4_phy_clk_l),
1801+ .reset_list = msm8996_usb3phy_reset_l,
1802+ .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
1803+ .vreg_list = qmp_phy_vreg_l,
1804+ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
1805+};
1806+
12231807 static void qmp_combo_configure_lane(void __iomem *base,
12241808 const struct qmp_phy_init_tbl tbl[],
12251809 int num,
@@ -1530,6 +2114,33 @@ static void qmp_v4_dp_aux_init(struct qmp_combo *qmp) · 304 unmodified lines
15302114 qmp->dp_dp_phy + QSERDES_V4_DP_PHY_AUX_INTERRUPT_MASK);
15312115 }
15322116
2117+static void qmp_v6_dp_aux_init(struct qmp_combo *qmp)
2118+{
2119+ writel(DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_PSR_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN |
2120+ DP_PHY_PD_CTL_PLL_PWRDN | DP_PHY_PD_CTL_DP_CLAMP_EN,
2121+ qmp->dp_dp_phy + QSERDES_DP_PHY_PD_CTL);
2122+
2123+ /* Turn on BIAS current for PHY/PLL */
2124+ writel(0x17, qmp->dp_serdes + QSERDES_V6_COM_PLL_BIAS_EN_CLK_BUFLR_EN);
2125+
2126+ writel(0x00, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG0);
2127+ writel(0x13, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG1);
2128+ writel(0xa4, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG2);
2129+ writel(0x00, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG3);
2130+ writel(0x0a, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG4);
2131+ writel(0x26, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG5);
2132+ writel(0x0a, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG6);
2133+ writel(0x03, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG7);
2134+ writel(0xb7, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG8);
2135+ writel(0x03, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG9);
2136+ qmp->dp_aux_cfg = 0;
2137+
2138+ writel(PHY_AUX_STOP_ERR_MASK | PHY_AUX_DEC_ERR_MASK |
2139+ PHY_AUX_SYNC_ERR_MASK | PHY_AUX_ALIGN_ERR_MASK |
2140+ PHY_AUX_REQ_ERR_MASK,
2141+ qmp->dp_dp_phy + QSERDES_V4_DP_PHY_AUX_INTERRUPT_MASK);
2142+}
2143+
15332144 static void qmp_v4_configure_dp_tx(struct qmp_combo *qmp)
15342145 {
15352146 /* Program default values before writing proper values */
@@ -1543,7 +2154,10 @@ static void qmp_v4_configure_dp_tx(struct qmp_combo *qmp) · 7 unmodified lines
15432154 QSERDES_V4_TX_TX_EMP_POST1_LVL);
15442155 }
15452156
1546−static int qmp_v45_configure_dp_phy(struct qmp_combo *qmp)
2157+static int qmp_v456_configure_dp_phy(struct qmp_combo *qmp,
2158+ unsigned int com_resetm_ctrl_reg,
2159+ unsigned int com_c_ready_status_reg,
2160+ unsigned int dp_phy_status_reg)
15472161 {
15482162 const struct phy_configure_opts_dp *dp_opts = &qmp->dp_opts;
15492163 u32 phy_vco_div, status;
@@ -1590,9 +2204,9 @@ static int qmp_v45_configure_dp_phy(struct qmp_combo *qmp) · 40 unmodified lines
15902204 writel(0x01, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG);
15912205 writel(0x09, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG);
15922206
1593− writel(0x20, qmp->dp_serdes + QSERDES_V4_COM_RESETSM_CNTRL);
2207+ writel(0x20, qmp->dp_serdes + com_resetm_ctrl_reg);
15942208
1595− if (readl_poll_timeout(qmp->dp_serdes + QSERDES_V4_COM_C_READY_STATUS,
2209+ if (readl_poll_timeout(qmp->dp_serdes + com_c_ready_status_reg,
15962210 status,
15972211 ((status & BIT(0)) > 0),
15982212 500,
@@ -1615,14 +2229,14 @@ static int qmp_v45_configure_dp_phy(struct qmp_combo *qmp) · 16 unmodified lines
16152229
16162230 writel(0x19, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG);
16172231
1618− if (readl_poll_timeout(qmp->dp_dp_phy + QSERDES_V4_DP_PHY_STATUS,
2232+ if (readl_poll_timeout(qmp->dp_dp_phy + dp_phy_status_reg,
16192233 status,
16202234 ((status & BIT(0)) > 0),
16212235 500,
16222236 10000))
16232237 return -ETIMEDOUT;
16242238
1625− if (readl_poll_timeout(qmp->dp_dp_phy + QSERDES_V4_DP_PHY_STATUS,
2239+ if (readl_poll_timeout(qmp->dp_dp_phy + dp_phy_status_reg,
16262240 status,
16272241 ((status & BIT(1)) > 0),
16282242 500,
@@ -1640,7 +2254,9 @@ static int qmp_v4_configure_dp_phy(struct qmp_combo *qmp) · 11 unmodified lines
16402254 u32 status;
16412255 int ret;
16422256
1643− ret = qmp_v45_configure_dp_phy(qmp);
2257+ ret = qmp_v456_configure_dp_phy(qmp, QSERDES_V4_COM_RESETSM_CNTRL,
2258+ QSERDES_V4_COM_C_READY_STATUS,
2259+ QSERDES_V4_DP_PHY_STATUS);
16442260 if (ret < 0)
16452261 return ret;
16462262
@@ -1702,7 +2318,9 @@ static int qmp_v5_configure_dp_phy(struct qmp_combo *qmp) · 55 unmodified lines
17022318 u32 status;
17032319 int ret;
17042320
1705− ret = qmp_v45_configure_dp_phy(qmp);
2321+ ret = qmp_v456_configure_dp_phy(qmp, QSERDES_V4_COM_RESETSM_CNTRL,
2322+ QSERDES_V4_COM_C_READY_STATUS,
2323+ QSERDES_V4_DP_PHY_STATUS);
17062324 if (ret < 0)
17072325 return ret;
17082326
@@ -1751,6 +2369,65 @@ static int qmp_v5_configure_dp_phy(struct qmp_combo *qmp) · 42 unmodified lines
17512369 return 0;
17522370 }
17532371
2372+static int qmp_v6_configure_dp_phy(struct qmp_combo *qmp)
2373+{
2374+ const struct phy_configure_opts_dp *dp_opts = &qmp->dp_opts;
2375+ u32 bias0_en, drvr0_en, bias1_en, drvr1_en;
2376+ bool reverse = false;
2377+ u32 status;
2378+ int ret;
2379+
2380+ ret = qmp_v456_configure_dp_phy(qmp, QSERDES_V6_COM_RESETSM_CNTRL,
2381+ QSERDES_V6_COM_C_READY_STATUS,
2382+ QSERDES_V6_DP_PHY_STATUS);
2383+ if (ret < 0)
2384+ return ret;
2385+
2386+ if (dp_opts->lanes == 1) {
2387+ bias0_en = reverse ? 0x3e : 0x1a;
2388+ drvr0_en = reverse ? 0x13 : 0x10;
2389+ bias1_en = reverse ? 0x15 : 0x3e;
2390+ drvr1_en = reverse ? 0x10 : 0x13;
2391+ } else if (dp_opts->lanes == 2) {
2392+ bias0_en = reverse ? 0x3f : 0x15;
2393+ drvr0_en = 0x10;
2394+ bias1_en = reverse ? 0x15 : 0x3f;
2395+ drvr1_en = 0x10;
2396+ } else {
2397+ bias0_en = 0x3f;
2398+ bias1_en = 0x3f;
2399+ drvr0_en = 0x10;
2400+ drvr1_en = 0x10;
2401+ }
2402+
2403+ writel(drvr0_en, qmp->dp_tx + QSERDES_V4_TX_HIGHZ_DRVR_EN);
2404+ writel(bias0_en, qmp->dp_tx + QSERDES_V4_TX_TRANSCEIVER_BIAS_EN);
2405+ writel(drvr1_en, qmp->dp_tx2 + QSERDES_V4_TX_HIGHZ_DRVR_EN);
2406+ writel(bias1_en, qmp->dp_tx2 + QSERDES_V4_TX_TRANSCEIVER_BIAS_EN);
2407+
2408+ writel(0x18, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG);
2409+ udelay(2000);
2410+ writel(0x19, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG);
2411+
2412+ if (readl_poll_timeout(qmp->dp_dp_phy + QSERDES_V6_DP_PHY_STATUS,
2413+ status,
2414+ ((status & BIT(1)) > 0),
2415+ 500,
2416+ 10000))
2417+ return -ETIMEDOUT;
2418+
2419+ writel(0x0a, qmp->dp_tx + QSERDES_V4_TX_TX_POL_INV);
2420+ writel(0x0a, qmp->dp_tx2 + QSERDES_V4_TX_TX_POL_INV);
2421+
2422+ writel(0x27, qmp->dp_tx + QSERDES_V4_TX_TX_DRV_LVL);
2423+ writel(0x27, qmp->dp_tx2 + QSERDES_V4_TX_TX_DRV_LVL);
2424+
2425+ writel(0x20, qmp->dp_tx + QSERDES_V4_TX_TX_EMP_POST1_LVL);
2426+ writel(0x20, qmp->dp_tx2 + QSERDES_V4_TX_TX_EMP_POST1_LVL);
2427+
2428+ return 0;
2429+}
2430+
17542431 /*
17552432 * We need to calibrate the aux setting here as many times
17562433 * as the caller tries
@@ -2641,8 +3318,13 @@ static int qmp_combo_parse_dt(struct qmp_combo *qmp) · 884 unmodified lines
26413318 qmp->pcs_usb = base + offs->usb3_pcs_usb;
26423319
26433320 qmp->dp_serdes = base + offs->dp_serdes;
2644− qmp->dp_tx = base + offs->txa;
2645− qmp->dp_tx2 = base + offs->txb;
3321+ if (offs->dp_txa) {
3322+ qmp->dp_tx = base + offs->dp_txa;
3323+ qmp->dp_tx2 = base + offs->dp_txb;
3324+ } else {
3325+ qmp->dp_tx = base + offs->txa;
3326+ qmp->dp_tx2 = base + offs->txb;
3327+ }
26463328 qmp->dp_dp_phy = base + offs->dp_dp_phy;
26473329
26483330 qmp->pipe_clk = devm_clk_get(dev, "usb3_pipe");
@@ -2789,10 +3471,26 @@ static const struct of_device_id qmp_combo_of_match_table[] = { · 140 unmodified lines
27893471 .compatible = "qcom,sdm845-qmp-usb3-dp-phy",
27903472 .data = &sdm845_usb3dpphy_cfg,
27913473 },
3474+ {
3475+ .compatible = "qcom,sm6350-qmp-usb3-dp-phy",
3476+ .data = &sm6350_usb3dpphy_cfg,
3477+ },
27923478 {
27933479 .compatible = "qcom,sm8250-qmp-usb3-dp-phy",
27943480 .data = &sm8250_usb3dpphy_cfg,
27953481 },
3482+ {
3483+ .compatible = "qcom,sm8350-qmp-usb3-dp-phy",
3484+ .data = &sm8350_usb3dpphy_cfg,
3485+ },
3486+ {
3487+ .compatible = "qcom,sm8450-qmp-usb3-dp-phy",
3488+ .data = &sm8350_usb3dpphy_cfg,
3489+ },
3490+ {
3491+ .compatible = "qcom,sm8550-qmp-usb3-dp-phy",
3492+ .data = &sm8550_usb3dpphy_cfg,
3493+ },
27963494 { }
27973495 };
27983496 MODULE_DEVICE_TABLE(of, qmp_combo_of_match_table);
drivers/phy/qualcomm/phy-qcom-qmp-pcie-msm8996.c+3−3
@@ -84,9 +84,9 @@ static const unsigned int pciephy_regs_layout[QPHY_LAYOUT_SIZE] = { · 83 unmodified lines
8484 [QPHY_COM_POWER_DOWN_CONTROL] = 0x404,
8585 [QPHY_COM_START_CONTROL] = 0x408,
8686 [QPHY_COM_PCS_READY_STATUS] = 0x448,
87− [QPHY_SW_RESET] = 0x00,
88− [QPHY_START_CTRL] = 0x08,
89− [QPHY_PCS_STATUS] = 0x174,
87+ [QPHY_SW_RESET] = QPHY_V2_PCS_SW_RESET,
88+ [QPHY_START_CTRL] = QPHY_V2_PCS_START_CONTROL,
89+ [QPHY_PCS_STATUS] = QPHY_V2_PCS_PCI_PCS_STATUS,
9090 };
9191
9292 static const struct qmp_phy_init_tbl msm8996_pcie_serdes_tbl[] = {
drivers/phy/qualcomm/phy-qcom-qmp-pcie.c+535−53
@@ -24,6 +24,14 @@ · 23 unmodified lines
2424 #include <linux/slab.h>
2525
2626 #include "phy-qcom-qmp.h"
27+#include "phy-qcom-qmp-pcs-misc-v3.h"
28+#include "phy-qcom-qmp-pcs-pcie-v4.h"
29+#include "phy-qcom-qmp-pcs-pcie-v4_20.h"
30+#include "phy-qcom-qmp-pcs-pcie-v5.h"
31+#include "phy-qcom-qmp-pcs-pcie-v5_20.h"
32+#include "phy-qcom-qmp-pcs-pcie-v6.h"
33+#include "phy-qcom-qmp-pcs-pcie-v6_20.h"
34+#include "phy-qcom-qmp-pcie-qhp.h"
2735
2836 /* QPHY_SW_RESET bit */
2937 #define SW_RESET BIT(0)
@@ -74,25 +82,18 @@ enum qphy_reg_layout { · 44 unmodified lines
7482 QPHY_LAYOUT_SIZE
7583 };
7684
77−static const unsigned int ipq_pciephy_gen3_regs_layout[QPHY_LAYOUT_SIZE] = {
78− [QPHY_SW_RESET] = 0x00,
79− [QPHY_START_CTRL] = 0x44,
80− [QPHY_PCS_STATUS] = 0x14,
81− [QPHY_PCS_POWER_DOWN_CONTROL] = 0x40,
85+static const unsigned int pciephy_v2_regs_layout[QPHY_LAYOUT_SIZE] = {
86+ [QPHY_SW_RESET] = QPHY_V2_PCS_SW_RESET,
87+ [QPHY_START_CTRL] = QPHY_V2_PCS_START_CONTROL,
88+ [QPHY_PCS_STATUS] = QPHY_V2_PCS_PCI_PCS_STATUS,
89+ [QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V2_PCS_POWER_DOWN_CONTROL,
8290 };
8391
84−static const unsigned int pciephy_regs_layout[QPHY_LAYOUT_SIZE] = {
85− [QPHY_SW_RESET] = 0x00,
86− [QPHY_START_CTRL] = 0x08,
87− [QPHY_PCS_STATUS] = 0x174,
88− [QPHY_PCS_POWER_DOWN_CONTROL] = 0x04,
89−};
90−
91−static const unsigned int sdm845_qmp_pciephy_regs_layout[QPHY_LAYOUT_SIZE] = {
92− [QPHY_SW_RESET] = 0x00,
93− [QPHY_START_CTRL] = 0x08,
94− [QPHY_PCS_STATUS] = 0x174,
95− [QPHY_PCS_POWER_DOWN_CONTROL] = 0x04,
92+static const unsigned int pciephy_v3_regs_layout[QPHY_LAYOUT_SIZE] = {
93+ [QPHY_SW_RESET] = QPHY_V3_PCS_SW_RESET,
94+ [QPHY_START_CTRL] = QPHY_V3_PCS_START_CONTROL,
95+ [QPHY_PCS_STATUS] = QPHY_V3_PCS_PCS_STATUS,
96+ [QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V3_PCS_POWER_DOWN_CONTROL,
9697 };
9798
9899 static const unsigned int sdm845_qhp_pciephy_regs_layout[QPHY_LAYOUT_SIZE] = {
@@ -102,11 +103,18 @@ static const unsigned int sdm845_qhp_pciephy_regs_layout[QPHY_LAYOUT_SIZE] = { · 3 unmodified lines
102103 [QPHY_PCS_POWER_DOWN_CONTROL] = 0x04,
103104 };
104105
105−static const unsigned int sm8250_pcie_regs_layout[QPHY_LAYOUT_SIZE] = {
106− [QPHY_SW_RESET] = 0x00,
107− [QPHY_START_CTRL] = 0x44,
108− [QPHY_PCS_STATUS] = 0x14,
109− [QPHY_PCS_POWER_DOWN_CONTROL] = 0x40,
106+static const unsigned int pciephy_v4_regs_layout[QPHY_LAYOUT_SIZE] = {
107+ [QPHY_SW_RESET] = QPHY_V4_PCS_SW_RESET,
108+ [QPHY_START_CTRL] = QPHY_V4_PCS_START_CONTROL,
109+ [QPHY_PCS_STATUS] = QPHY_V4_PCS_PCS_STATUS1,
110+ [QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V4_PCS_POWER_DOWN_CONTROL,
111+};
112+
113+static const unsigned int pciephy_v5_regs_layout[QPHY_LAYOUT_SIZE] = {
114+ [QPHY_SW_RESET] = QPHY_V5_PCS_SW_RESET,
115+ [QPHY_START_CTRL] = QPHY_V5_PCS_START_CONTROL,
116+ [QPHY_PCS_STATUS] = QPHY_V5_PCS_PCS_STATUS1,
117+ [QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V5_PCS_POWER_DOWN_CONTROL,
110118 };
111119
112120 static const struct qmp_phy_init_tbl msm8998_pcie_serdes_tbl[] = {
@@ -1216,7 +1224,7 @@ static const struct qmp_phy_init_tbl sdx55_qmp_pcie_pcs_misc_tbl[] = { · 1103 unmodified lines
12161224 QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_LANE1_INSIG_MX_CTRL2, 0x00),
12171225 };
12181226
1219−static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_serdes_tbl[] = {
1227+static const struct qmp_phy_init_tbl sm8450_qmp_gen3_pcie_serdes_tbl[] = {
12201228 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_EN_SEL, 0x08),
12211229 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_SELECT, 0x34),
12221230 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORECLK_DIV_MODE1, 0x08),
@@ -1250,7 +1258,6 @@ static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_serdes_tbl[] = { · 27 unmodified lines
12501258 QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca),
12511259 QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x18),
12521260 QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xa2),
1253− QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_BUF_ENABLE, 0x07),
12541261 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_EN_CENTER, 0x01),
12551262 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER1, 0x31),
12561263 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER2, 0x01),
@@ -1261,6 +1268,10 @@ static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_serdes_tbl[] = { · 4 unmodified lines
12611268 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_ENABLE1, 0x90),
12621269 };
12631270
1271+static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_rc_serdes_tbl[] = {
1272+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_BUF_ENABLE, 0x07),
1273+};
1274+
12641275 static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_tx_tbl[] = {
12651276 QMP_PHY_INIT_CFG(QSERDES_V5_TX_PI_QEC_CTRL, 0x20),
12661277 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0x75),
@@ -1269,11 +1280,9 @@ static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_tx_tbl[] = { · 2 unmodified lines
12691280 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x04),
12701281 };
12711282
1272−static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_rx_tbl[] = {
1283+static const struct qmp_phy_init_tbl sm8450_qmp_gen3_pcie_rx_tbl[] = {
12731284 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0x7f),
12741285 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0xff),
1275− QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xbf),
1276− QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x3f),
12771286 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0xd8),
12781287 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0xdc),
12791288 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0xdc),
@@ -1281,20 +1290,25 @@ static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_rx_tbl[] = { · 1 unmodified line
12811290 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x34),
12821291 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xa6),
12831292 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH3, 0x34),
1284− QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH4, 0x38),
1285− QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x07),
12861293 QMP_PHY_INIT_CFG(QSERDES_V5_RX_GM_CAL, 0x00),
12871294 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH1, 0x08),
12881295 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH2, 0x08),
1289− QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0xf0),
12901296 QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
12911297 QMP_PHY_INIT_CFG(QSERDES_V5_RX_TX_ADAPT_POST_THRESH, 0xf0),
1298+};
1299+
1300+static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_rc_rx_tbl[] = {
1301+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xbf),
1302+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x3f),
1303+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH4, 0x38),
1304+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x07),
1305+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0xf0),
12921306 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x07),
12931307 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FO_GAIN, 0x09),
12941308 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_GAIN, 0x05),
12951309 };
12961310
1297−static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_pcs_tbl[] = {
1311+static const struct qmp_phy_init_tbl sm8450_qmp_gen3_pcie_pcs_tbl[] = {
12981312 QMP_PHY_INIT_CFG(QPHY_V5_PCS_RX_SIGDET_LVL, 0x77),
12991313 QMP_PHY_INIT_CFG(QPHY_V5_PCS_RATE_SLEW_CNTRL1, 0x0b),
13001314 QMP_PHY_INIT_CFG(QPHY_V5_PCS_REFGEN_REQ_CONFIG1, 0x05),
@@ -1307,6 +1321,40 @@ static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_pcs_misc_tbl[] = { · 6 unmodified lines
13071321 QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1),
13081322 };
13091323
1324+static const struct qmp_phy_init_tbl sm8350_qmp_gen3x1_pcie_tx_tbl[] = {
1325+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_PI_QEC_CTRL, 0x20),
1326+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0x75),
1327+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_4, 0x3f),
1328+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x1d),
1329+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x0c),
1330+};
1331+
1332+static const struct qmp_phy_init_tbl sm8350_qmp_gen3x1_pcie_rc_rx_tbl[] = {
1333+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xbf),
1334+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x3f),
1335+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x07),
1336+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0xf0),
1337+};
1338+
1339+static const struct qmp_phy_init_tbl sm8350_qmp_gen3x2_pcie_rc_rx_tbl[] = {
1340+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0x7f),
1341+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x34),
1342+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x0f),
1343+};
1344+
1345+static const struct qmp_phy_init_tbl sm8350_qmp_gen3x2_pcie_tx_tbl[] = {
1346+ QMP_PHY_INIT_CFG_LANE(QSERDES_V5_TX_PI_QEC_CTRL, 0x02, 1),
1347+ QMP_PHY_INIT_CFG_LANE(QSERDES_V5_TX_PI_QEC_CTRL, 0x04, 2),
1348+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0xd5),
1349+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_4, 0x3f),
1350+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x1d),
1351+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x0c),
1352+};
1353+
1354+static const struct qmp_phy_init_tbl sm8350_qmp_gen3x2_pcie_rc_pcs_tbl[] = {
1355+ QMP_PHY_INIT_CFG(QPHY_V5_PCS_EQ_CONFIG2, 0x0f),
1356+};
1357+
13101358 static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_serdes_tbl[] = {
13111359 QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIAS_EN_CLKBUFLR_EN, 0x14),
13121360 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_IVCO, 0x0f),
@@ -1458,6 +1506,234 @@ static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_ep_pcs_misc_tbl[] = · 145 unmodified lines
14581506 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_OSC_DTCT_MODE2_CONFIG5, 0x08),
14591507 };
14601508
1509+static const struct qmp_phy_init_tbl sm8550_qmp_gen3x2_pcie_serdes_tbl[] = {
1510+ QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_EN_CENTER, 0x01),
1511+ QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_PER1, 0x62),
1512+ QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_PER2, 0x02),
1513+ QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE1_MODE0, 0xf8),
1514+ QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE2_MODE0, 0x01),
1515+ QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE1_MODE1, 0x93),
1516+ QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE2_MODE1, 0x01),
1517+ QMP_PHY_INIT_CFG(QSERDES_V6_COM_CLK_ENABLE1, 0x90),
1518+ QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYS_CLK_CTRL, 0x82),
1519+ QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_IVCO, 0x07),
1520+ QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE0, 0x02),
1521+ QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE1, 0x02),
1522+ QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE0, 0x16),
1523+ QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE1, 0x16),
1524+ QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE0, 0x36),
1525+ QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE1, 0x36),
1526+ QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYSCLK_EN_SEL, 0x08),
1527+ QMP_PHY_INIT_CFG(QSERDES_V6_COM_BG_TIMER, 0x0a),
1528+ QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_EN, 0x42),
1529+ QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x04),
1530+ QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x0d),
1531+ QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE1, 0x0a),
1532+ QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE1, 0x1a),
1533+ QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x41),
1534+ QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE1, 0x34),
1535+ QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START1_MODE0, 0xab),
1536+ QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START2_MODE0, 0xaa),
1537+ QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START3_MODE0, 0x01),
1538+ QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START1_MODE1, 0x55),
1539+ QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START2_MODE1, 0x55),
1540+ QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START3_MODE1, 0x01),
1541+ QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAP, 0x14),
1542+ QMP_PHY_INIT_CFG(QSERDES_V6_COM_CLK_SELECT, 0x34),
1543+ QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_SEL_1, 0x01),
1544+ QMP_PHY_INIT_CFG(QSERDES_V6_COM_CORECLK_DIV_MODE1, 0x04),
1545+ QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_CONFIG_1, 0x16),
1546+ QMP_PHY_INIT_CFG(QSERDES_V6_COM_ADDITIONAL_MISC_3, 0x0f),
1547+ QMP_PHY_INIT_CFG(QSERDES_V6_COM_CORE_CLK_EN, 0xa0),
1548+};
1549+
1550+static const struct qmp_phy_init_tbl sm8550_qmp_gen3x2_pcie_tx_tbl[] = {
1551+ QMP_PHY_INIT_CFG(QSERDES_V6_TX_LANE_MODE_1, 0x15),
1552+ QMP_PHY_INIT_CFG(QSERDES_V6_TX_LANE_MODE_4, 0x3f),
1553+ QMP_PHY_INIT_CFG(QSERDES_V6_TX_PI_QEC_CTRL, 0x02),
1554+ QMP_PHY_INIT_CFG(QSERDES_V6_TX_RES_CODE_LANE_OFFSET_RX, 0x06),
1555+ QMP_PHY_INIT_CFG(QSERDES_V6_TX_RES_CODE_LANE_OFFSET_TX, 0x18),
1556+};
1557+
1558+static const struct qmp_phy_init_tbl sm8550_qmp_gen3x2_pcie_rx_tbl[] = {
1559+ QMP_PHY_INIT_CFG(QSERDES_V6_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
1560+ QMP_PHY_INIT_CFG(QSERDES_V6_RX_GM_CAL, 0x11),
1561+ QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_00_HIGH, 0xbf),
1562+ QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_00_HIGH2, 0xbf),
1563+ QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_00_HIGH3, 0xb7),
1564+ QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_00_HIGH4, 0xea),
1565+ QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_00_LOW, 0x3f),
1566+ QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_01_HIGH, 0x5c),
1567+ QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_01_HIGH2, 0x9c),
1568+ QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_01_HIGH3, 0x1a),
1569+ QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_01_HIGH4, 0x89),
1570+ QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_01_LOW, 0xdc),
1571+ QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_10_HIGH, 0x94),
1572+ QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_10_HIGH2, 0x5b),
1573+ QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_10_HIGH3, 0x1a),
1574+ QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_10_HIGH4, 0x89),
1575+ QMP_PHY_INIT_CFG(QSERDES_V6_RX_TX_ADAPT_POST_THRESH, 0xf0),
1576+ QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_FO_GAIN, 0x09),
1577+ QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_SO_GAIN, 0x05),
1578+ QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_SB2_THRESH1, 0x08),
1579+ QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_SB2_THRESH2, 0x08),
1580+ QMP_PHY_INIT_CFG(QSERDES_V6_RX_VGA_CAL_CNTRL2, 0x0f),
1581+ QMP_PHY_INIT_CFG(QSERDES_V6_RX_SIDGET_ENABLES, 0x1c),
1582+ QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_IDAC_TSETTLE_LOW, 0x07),
1583+ QMP_PHY_INIT_CFG(QSERDES_V6_RX_SIGDET_CAL_TRIM, 0x08),
1584+};
1585+
1586+static const struct qmp_phy_init_tbl sm8550_qmp_gen3x2_pcie_pcs_tbl[] = {
1587+ QMP_PHY_INIT_CFG(QPHY_V6_PCS_REFGEN_REQ_CONFIG1, 0x05),
1588+ QMP_PHY_INIT_CFG(QPHY_V6_PCS_RX_SIGDET_LVL, 0x77),
1589+ QMP_PHY_INIT_CFG(QPHY_V6_PCS_RATE_SLEW_CNTRL1, 0x0b),
1590+ QMP_PHY_INIT_CFG(QPHY_V6_PCS_EQ_CONFIG2, 0x0f),
1591+ QMP_PHY_INIT_CFG(QPHY_V6_PCS_PCS_TX_RX_CONFIG, 0x8c),
1592+};
1593+
1594+static const struct qmp_phy_init_tbl sm8550_qmp_gen3x2_pcie_pcs_misc_tbl[] = {
1595+ QMP_PHY_INIT_CFG(QPHY_PCIE_V6_PCS_PCIE_POWER_STATE_CONFIG2, 0x1d),
1596+ QMP_PHY_INIT_CFG(QPHY_PCIE_V6_PCS_PCIE_POWER_STATE_CONFIG4, 0x07),
1597+ QMP_PHY_INIT_CFG(QPHY_PCIE_V6_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1),
1598+ QMP_PHY_INIT_CFG(QPHY_PCIE_V6_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00),
1599+};
1600+
1601+static const struct qmp_phy_init_tbl sm8550_qmp_gen4x2_pcie_serdes_tbl[] = {
1602+ QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE1_MODE1, 0x26),
1603+ QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE2_MODE1, 0x03),
1604+ QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE1, 0x06),
1605+ QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE1, 0x16),
1606+ QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE1, 0x36),
1607+ QMP_PHY_INIT_CFG(QSERDES_V6_COM_CORECLK_DIV_MODE1, 0x04),
1608+ QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE1, 0x0a),
1609+ QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE1, 0x1a),
1610+ QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE1, 0x68),
1611+ QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START1_MODE1, 0xab),
1612+ QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START2_MODE1, 0xaa),
1613+ QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START3_MODE1, 0x02),
1614+ QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_SEL_1, 0x12),
1615+ QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE1_MODE0, 0xf8),
1616+ QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE2_MODE0, 0x01),
1617+ QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE0, 0x06),
1618+ QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE0, 0x16),
1619+ QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE0, 0x36),
1620+ QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CORE_CLK_DIV_MODE0, 0x0a),
1621+ QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x04),
1622+ QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x0d),
1623+ QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x41),
1624+ QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START1_MODE0, 0xab),
1625+ QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START2_MODE0, 0xaa),
1626+ QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START3_MODE0, 0x01),
1627+ QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_HS_SWITCH_SEL_1, 0x00),
1628+ QMP_PHY_INIT_CFG(QSERDES_V6_COM_BG_TIMER, 0x0a),
1629+ QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_EN_CENTER, 0x01),
1630+ QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_PER1, 0x62),
1631+ QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_PER2, 0x02),
1632+ QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_POST_DIV_MUX, 0x40),
1633+ QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_BIAS_EN_CLK_BUFLR_EN, 0x14),
1634+ QMP_PHY_INIT_CFG(QSERDES_V6_COM_CLK_ENABLE1, 0x90),
1635+ QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYS_CLK_CTRL, 0x82),
1636+ QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_IVCO, 0x0f),
1637+ QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYSCLK_EN_SEL, 0x08),
1638+ QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_EN, 0x46),
1639+ QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_CFG, 0x04),
1640+ QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAP, 0x14),
1641+ QMP_PHY_INIT_CFG(QSERDES_V6_COM_CLK_SELECT, 0x34),
1642+ QMP_PHY_INIT_CFG(QSERDES_V6_COM_CORE_CLK_EN, 0xa0),
1643+ QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_CONFIG_1, 0x06),
1644+ QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_MISC_1, 0x88),
1645+ QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_MODE, 0x14),
1646+ QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_VCO_DC_LEVEL_CTRL, 0x0f),
1647+};
1648+
1649+static const struct qmp_phy_init_tbl sm8550_qmp_gen4x2_pcie_ln_shrd_tbl[] = {
1650+ QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RXCLK_DIV2_CTRL, 0x01),
1651+ QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_Q_EN_RATES, 0xe),
1652+ QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_DFE_DAC_ENABLE1, 0x00),
1653+ QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_TX_ADAPT_POST_THRESH1, 0x00),
1654+ QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_TX_ADAPT_POST_THRESH2, 0x1f),
1655+ QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B0, 0x12),
1656+ QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B1, 0x12),
1657+ QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B2, 0xdb),
1658+ QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B3, 0x9a),
1659+ QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B4, 0x38),
1660+ QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B5, 0xb6),
1661+ QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B6, 0x64),
1662+ QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH1_RATE210, 0x1f),
1663+ QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH1_RATE3, 0x1f),
1664+ QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH2_RATE210, 0x1f),
1665+ QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH2_RATE3, 0x1f),
1666+ QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH3_RATE210, 0x1f),
1667+ QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH3_RATE3, 0x1f),
1668+ QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH4_RATE3, 0x1f),
1669+ QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH5_RATE3, 0x1f),
1670+ QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH6_RATE3, 0x1f),
1671+};
1672+
1673+static const struct qmp_phy_init_tbl sm8550_qmp_gen4x2_pcie_tx_tbl[] = {
1674+ QMP_PHY_INIT_CFG(QSERDES_V6_20_TX_RES_CODE_LANE_OFFSET_TX, 0x1d),
1675+ QMP_PHY_INIT_CFG(QSERDES_V6_20_TX_RES_CODE_LANE_OFFSET_RX, 0x03),
1676+ QMP_PHY_INIT_CFG(QSERDES_V6_20_TX_LANE_MODE_1, 0x01),
1677+ QMP_PHY_INIT_CFG(QSERDES_V6_20_TX_LANE_MODE_2, 0x00),
1678+ QMP_PHY_INIT_CFG(QSERDES_V6_20_TX_LANE_MODE_3, 0x51),
1679+ QMP_PHY_INIT_CFG(QSERDES_V6_20_TX_TRAN_DRVR_EMP_EN, 0x34),
1680+};
1681+
1682+static const struct qmp_phy_init_tbl sm8550_qmp_gen4x2_pcie_rx_tbl[] = {
1683+ QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_UCDR_FO_GAIN_RATE_2, 0x0a),
1684+ QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_UCDR_FO_GAIN_RATE_3, 0x0a),
1685+ QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_UCDR_PI_CONTROLS, 0x16),
1686+ QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_UCDR_SO_ACC_DEFAULT_VAL_RATE3, 0x00),
1687+ QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_IVCM_CAL_CTRL2, 0x80),
1688+ QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_IVCM_POSTCAL_OFFSET, 0x7c),
1689+ QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_DFE_3, 0x05),
1690+ QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_VGA_CAL_MAN_VAL, 0x0a),
1691+ QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_GM_CAL, 0x0d),
1692+ QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_EQU_ADAPTOR_CNTRL4, 0x0b),
1693+ QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_SIGDET_ENABLES, 0x1c),
1694+ QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_PHPRE_CTRL, 0x20),
1695+ QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_DFE_CTLE_POST_CAL_OFFSET, 0x30),
1696+ QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_Q_PI_INTRINSIC_BIAS_RATE32, 0x09),
1697+ QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B0, 0x14),
1698+ QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B1, 0xb3),
1699+ QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B2, 0x58),
1700+ QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B3, 0x9a),
1701+ QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B4, 0x26),
1702+ QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B5, 0xb6),
1703+ QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B6, 0xee),
1704+ QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B0, 0xdb),
1705+ QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B1, 0xdb),
1706+ QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B2, 0xa0),
1707+ QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B3, 0xdf),
1708+ QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B4, 0x78),
1709+ QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B5, 0x76),
1710+ QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B6, 0xff),
1711+};
1712+
1713+static const struct qmp_phy_init_tbl sm8550_qmp_gen4x2_pcie_pcs_tbl[] = {
1714+ QMP_PHY_INIT_CFG(QPHY_V6_20_PCS_G3S2_PRE_GAIN, 0x2e),
1715+ QMP_PHY_INIT_CFG(QPHY_V6_20_PCS_COM_ELECIDLE_DLY_SEL, 0x25),
1716+ QMP_PHY_INIT_CFG(QPHY_V6_20_PCS_EQ_CONFIG4, 0x00),
1717+ QMP_PHY_INIT_CFG(QPHY_V6_20_PCS_EQ_CONFIG5, 0x22),
1718+ QMP_PHY_INIT_CFG(QPHY_V6_20_PCS_TX_RX_CONFIG1, 0x04),
1719+ QMP_PHY_INIT_CFG(QPHY_V6_20_PCS_TX_RX_CONFIG2, 0x02),
1720+};
1721+
1722+static const struct qmp_phy_init_tbl sm8550_qmp_gen4x2_pcie_pcs_misc_tbl[] = {
1723+ QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_ENDPOINT_REFCLK_DRIVE, 0xc1),
1724+ QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_OSC_DTCT_ATCIONS, 0x00),
1725+ QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_EQ_CONFIG1, 0x16),
1726+ QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_EQ_CONFIG5, 0x02),
1727+ QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_G4_PRE_GAIN, 0x2e),
1728+ QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_RX_MARGINING_CONFIG1, 0x03),
1729+ QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_RX_MARGINING_CONFIG3, 0x28),
1730+ QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_TX_RX_CONFIG, 0xc0),
1731+ QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_POWER_STATE_CONFIG2, 0x1d),
1732+ QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_RX_MARGINING_CONFIG5, 0x0f),
1733+ QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_G3_FOM_EQ_CONFIG5, 0xf2),
1734+ QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_G4_FOM_EQ_CONFIG5, 0xf2),
1735+};
1736+
14611737 struct qmp_pcie_offsets {
14621738 u16 serdes;
14631739 u16 pcs;
@@ -1466,6 +1742,7 @@ struct qmp_pcie_offsets { · 2 unmodified lines
14661742 u16 rx;
14671743 u16 tx2;
14681744 u16 rx2;
1745+ u16 ln_shrd;
14691746 };
14701747
14711748 struct qmp_phy_cfg_tbls {
@@ -1479,6 +1756,8 @@ struct qmp_phy_cfg_tbls { · 7 unmodified lines
14791756 int pcs_num;
14801757 const struct qmp_phy_init_tbl *pcs_misc;
14811758 int pcs_misc_num;
1759+ const struct qmp_phy_init_tbl *ln_shrd;
1760+ int ln_shrd_num;
14821761 };
14831762
14841763 /* struct qmp_phy_cfg - per-PHY initialization config */
@@ -1521,6 +1800,8 @@ struct qmp_phy_cfg { · 36 unmodified lines
15211800
15221801 bool skip_start_delay;
15231802
1803+ bool has_nocsr_reset;
1804+
15241805 /* QMP PHY pipe clock interface rate */
15251806 unsigned long pipe_clock_rate;
15261807 };
@@ -1538,6 +1819,7 @@ struct qmp_pcie { · 11 unmodified lines
15381819 void __iomem *rx;
15391820 void __iomem *tx2;
15401821 void __iomem *rx2;
1822+ void __iomem *ln_shrd;
15411823
15421824 void __iomem *port_b;
15431825
@@ -1546,6 +1828,7 @@ struct qmp_pcie { · 2 unmodified lines
15461828 int num_pipe_clks;
15471829
15481830 struct reset_control_bulk_data *resets;
1831+ struct reset_control *nocsr_reset;
15491832 struct regulator_bulk_data *vregs;
15501833
15511834 struct phy *phy;
@@ -1600,6 +1883,10 @@ static const char * const qmp_phy_vreg_l[] = { · 48 unmodified lines
16001883 "vdda-phy", "vdda-pll",
16011884 };
16021885
1886+static const char * const sm8550_qmp_phy_vreg_l[] = {
1887+ "vdda-phy", "vdda-pll", "vdda-qref",
1888+};
1889+
16031890 /* list of resets */
16041891 static const char * const ipq8074_pciephy_reset_l[] = {
16051892 "phy", "common",
@@ -1619,6 +1906,17 @@ static const struct qmp_pcie_offsets qmp_pcie_offsets_v5 = { · 13 unmodified lines
16191906 .rx2 = 0x1800,
16201907 };
16211908
1909+static const struct qmp_pcie_offsets qmp_pcie_offsets_v6_20 = {
1910+ .serdes = 0x1000,
1911+ .pcs = 0x1200,
1912+ .pcs_misc = 0x1400,
1913+ .tx = 0x0000,
1914+ .rx = 0x0200,
1915+ .tx2 = 0x0800,
1916+ .rx2 = 0x0a00,
1917+ .ln_shrd = 0x0e00,
1918+};
1919+
16221920 static const struct qmp_phy_cfg ipq8074_pciephy_cfg = {
16231921 .lanes = 1,
16241922
@@ -1638,7 +1936,7 @@ static const struct qmp_phy_cfg ipq8074_pciephy_cfg = { · 13 unmodified lines
16381936 .num_resets = ARRAY_SIZE(ipq8074_pciephy_reset_l),
16391937 .vreg_list = NULL,
16401938 .num_vregs = 0,
1641− .regs = pciephy_regs_layout,
1939+ .regs = pciephy_v2_regs_layout,
16421940
16431941 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
16441942 .phy_status = PHYSTATUS,
@@ -1665,7 +1963,7 @@ static const struct qmp_phy_cfg ipq8074_pciephy_gen3_cfg = { · 20 unmodified lines
16651963 .num_resets = ARRAY_SIZE(ipq8074_pciephy_reset_l),
16661964 .vreg_list = NULL,
16671965 .num_vregs = 0,
1668− .regs = ipq_pciephy_gen3_regs_layout,
1966+ .regs = pciephy_v4_regs_layout,
16691967
16701968 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
16711969 .phy_status = PHYSTATUS,
@@ -1694,7 +1992,7 @@ static const struct qmp_phy_cfg ipq6018_pciephy_cfg = { · 22 unmodified lines
16941992 .num_resets = ARRAY_SIZE(ipq8074_pciephy_reset_l),
16951993 .vreg_list = NULL,
16961994 .num_vregs = 0,
1697− .regs = ipq_pciephy_gen3_regs_layout,
1995+ .regs = pciephy_v4_regs_layout,
16981996
16991997 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
17001998 .phy_status = PHYSTATUS,
@@ -1721,7 +2019,7 @@ static const struct qmp_phy_cfg sdm845_qmp_pciephy_cfg = { · 20 unmodified lines
17212019 .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
17222020 .vreg_list = qmp_phy_vreg_l,
17232021 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
1724− .regs = sdm845_qmp_pciephy_regs_layout,
2022+ .regs = pciephy_v3_regs_layout,
17252023
17262024 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
17272025 .phy_status = PHYSTATUS,
@@ -1783,7 +2081,7 @@ static const struct qmp_phy_cfg sm8250_qmp_gen3x1_pciephy_cfg = { · 55 unmodified lines
17832081 .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
17842082 .vreg_list = qmp_phy_vreg_l,
17852083 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
1786− .regs = sm8250_pcie_regs_layout,
2084+ .regs = pciephy_v4_regs_layout,
17872085
17882086 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
17892087 .phy_status = PHYSTATUS,
@@ -1820,7 +2118,7 @@ static const struct qmp_phy_cfg sm8250_qmp_gen3x2_pciephy_cfg = { · 30 unmodified lines
18202118 .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
18212119 .vreg_list = qmp_phy_vreg_l,
18222120 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
1823− .regs = sm8250_pcie_regs_layout,
2121+ .regs = pciephy_v4_regs_layout,
18242122
18252123 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
18262124 .phy_status = PHYSTATUS,
@@ -1845,7 +2143,7 @@ static const struct qmp_phy_cfg msm8998_pciephy_cfg = { · 18 unmodified lines
18452143 .num_resets = ARRAY_SIZE(ipq8074_pciephy_reset_l),
18462144 .vreg_list = qmp_phy_vreg_l,
18472145 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
1848− .regs = pciephy_regs_layout,
2146+ .regs = pciephy_v3_regs_layout,
18492147
18502148 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
18512149 .phy_status = PHYSTATUS,
@@ -1874,7 +2172,7 @@ static const struct qmp_phy_cfg sc8180x_pciephy_cfg = { · 22 unmodified lines
18742172 .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
18752173 .vreg_list = qmp_phy_vreg_l,
18762174 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
1877− .regs = sm8250_pcie_regs_layout,
2175+ .regs = pciephy_v4_regs_layout,
18782176
18792177 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
18802178 .phy_status = PHYSTATUS,
@@ -1909,7 +2207,7 @@ static const struct qmp_phy_cfg sc8280xp_qmp_gen3x1_pciephy_cfg = { · 28 unmodified lines
19092207 .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
19102208 .vreg_list = qmp_phy_vreg_l,
19112209 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
1912− .regs = sm8250_pcie_regs_layout,
2210+ .regs = pciephy_v5_regs_layout,
19132211
19142212 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
19152213 .phy_status = PHYSTATUS,
@@ -1944,7 +2242,7 @@ static const struct qmp_phy_cfg sc8280xp_qmp_gen3x2_pciephy_cfg = { · 28 unmodified lines
19442242 .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
19452243 .vreg_list = qmp_phy_vreg_l,
19462244 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
1947− .regs = sm8250_pcie_regs_layout,
2245+ .regs = pciephy_v5_regs_layout,
19482246
19492247 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
19502248 .phy_status = PHYSTATUS,
@@ -1982,7 +2280,7 @@ static const struct qmp_phy_cfg sc8280xp_qmp_gen3x4_pciephy_cfg = { · 31 unmodified lines
19822280 .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
19832281 .vreg_list = qmp_phy_vreg_l,
19842282 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
1985− .regs = sm8250_pcie_regs_layout,
2283+ .regs = pciephy_v5_regs_layout,
19862284
19872285 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
19882286 .phy_status = PHYSTATUS,
@@ -2009,34 +2307,116 @@ static const struct qmp_phy_cfg sdx55_qmp_pciephy_cfg = { · 20 unmodified lines
20092307 .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
20102308 .vreg_list = qmp_phy_vreg_l,
20112309 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
2012− .regs = sm8250_pcie_regs_layout,
2310+ .regs = pciephy_v4_regs_layout,
20132311
20142312 .pwrdn_ctrl = SW_PWRDN,
20152313 .phy_status = PHYSTATUS_4_20,
20162314 };
20172315
2316+static const struct qmp_phy_cfg sm8350_qmp_gen3x1_pciephy_cfg = {
2317+ .lanes = 1,
2318+
2319+ .offsets = &qmp_pcie_offsets_v5,
2320+
2321+ .tbls = {
2322+ .serdes = sm8450_qmp_gen3_pcie_serdes_tbl,
2323+ .serdes_num = ARRAY_SIZE(sm8450_qmp_gen3_pcie_serdes_tbl),
2324+ .tx = sm8350_qmp_gen3x1_pcie_tx_tbl,
2325+ .tx_num = ARRAY_SIZE(sm8350_qmp_gen3x1_pcie_tx_tbl),
2326+ .rx = sm8450_qmp_gen3_pcie_rx_tbl,
2327+ .rx_num = ARRAY_SIZE(sm8450_qmp_gen3_pcie_rx_tbl),
2328+ .pcs = sm8450_qmp_gen3_pcie_pcs_tbl,
2329+ .pcs_num = ARRAY_SIZE(sm8450_qmp_gen3_pcie_pcs_tbl),
2330+ .pcs_misc = sm8450_qmp_gen3x1_pcie_pcs_misc_tbl,
2331+ .pcs_misc_num = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_pcs_misc_tbl),
2332+ },
2333+
2334+ .tbls_rc = &(const struct qmp_phy_cfg_tbls) {
2335+ .serdes = sm8450_qmp_gen3x1_pcie_rc_serdes_tbl,
2336+ .serdes_num = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_rc_serdes_tbl),
2337+ .rx = sm8350_qmp_gen3x1_pcie_rc_rx_tbl,
2338+ .rx_num = ARRAY_SIZE(sm8350_qmp_gen3x1_pcie_rc_rx_tbl),
2339+ },
2340+
2341+ .clk_list = sc8280xp_pciephy_clk_l,
2342+ .num_clks = ARRAY_SIZE(sc8280xp_pciephy_clk_l),
2343+ .reset_list = sdm845_pciephy_reset_l,
2344+ .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
2345+ .vreg_list = qmp_phy_vreg_l,
2346+ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
2347+ .regs = pciephy_v5_regs_layout,
2348+
2349+ .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
2350+ .phy_status = PHYSTATUS,
2351+};
2352+
2353+static const struct qmp_phy_cfg sm8350_qmp_gen3x2_pciephy_cfg = {
2354+ .lanes = 2,
2355+
2356+ .offsets = &qmp_pcie_offsets_v5,
2357+
2358+ .tbls = {
2359+ .serdes = sm8450_qmp_gen3_pcie_serdes_tbl,
2360+ .serdes_num = ARRAY_SIZE(sm8450_qmp_gen3_pcie_serdes_tbl),
2361+ .tx = sm8350_qmp_gen3x2_pcie_tx_tbl,
2362+ .tx_num = ARRAY_SIZE(sm8350_qmp_gen3x2_pcie_tx_tbl),
2363+ .rx = sm8450_qmp_gen3_pcie_rx_tbl,
2364+ .rx_num = ARRAY_SIZE(sm8450_qmp_gen3_pcie_rx_tbl),
2365+ .pcs = sm8450_qmp_gen3_pcie_pcs_tbl,
2366+ .pcs_num = ARRAY_SIZE(sm8450_qmp_gen3_pcie_pcs_tbl),
2367+ .pcs_misc = sc8280xp_qmp_gen3x2_pcie_pcs_misc_tbl,
2368+ .pcs_misc_num = ARRAY_SIZE(sc8280xp_qmp_gen3x2_pcie_pcs_misc_tbl),
2369+ },
2370+
2371+ .tbls_rc = &(const struct qmp_phy_cfg_tbls) {
2372+ .rx = sm8350_qmp_gen3x2_pcie_rc_rx_tbl,
2373+ .rx_num = ARRAY_SIZE(sm8350_qmp_gen3x2_pcie_rc_rx_tbl),
2374+ .pcs = sm8350_qmp_gen3x2_pcie_rc_pcs_tbl,
2375+ .pcs_num = ARRAY_SIZE(sm8350_qmp_gen3x2_pcie_rc_pcs_tbl),
2376+ },
2377+
2378+ .clk_list = sc8280xp_pciephy_clk_l,
2379+ .num_clks = ARRAY_SIZE(sc8280xp_pciephy_clk_l),
2380+ .reset_list = sdm845_pciephy_reset_l,
2381+ .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
2382+ .vreg_list = qmp_phy_vreg_l,
2383+ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
2384+ .regs = pciephy_v5_regs_layout,
2385+
2386+ .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
2387+ .phy_status = PHYSTATUS,
2388+};
2389+
20182390 static const struct qmp_phy_cfg sm8450_qmp_gen3x1_pciephy_cfg = {
20192391 .lanes = 1,
20202392
20212393 .tbls = {
2022− .serdes = sm8450_qmp_gen3x1_pcie_serdes_tbl,
2023− .serdes_num = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_serdes_tbl),
2394+ .serdes = sm8450_qmp_gen3_pcie_serdes_tbl,
2395+ .serdes_num = ARRAY_SIZE(sm8450_qmp_gen3_pcie_serdes_tbl),
20242396 .tx = sm8450_qmp_gen3x1_pcie_tx_tbl,
20252397 .tx_num = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_tx_tbl),
2026− .rx = sm8450_qmp_gen3x1_pcie_rx_tbl,
2027− .rx_num = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_rx_tbl),
2028− .pcs = sm8450_qmp_gen3x1_pcie_pcs_tbl,
2029− .pcs_num = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_pcs_tbl),
2398+ .rx = sm8450_qmp_gen3_pcie_rx_tbl,
2399+ .rx_num = ARRAY_SIZE(sm8450_qmp_gen3_pcie_rx_tbl),
2400+ .pcs = sm8450_qmp_gen3_pcie_pcs_tbl,
2401+ .pcs_num = ARRAY_SIZE(sm8450_qmp_gen3_pcie_pcs_tbl),
20302402 .pcs_misc = sm8450_qmp_gen3x1_pcie_pcs_misc_tbl,
20312403 .pcs_misc_num = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_pcs_misc_tbl),
20322404 },
2405+
2406+ .tbls_rc = &(const struct qmp_phy_cfg_tbls) {
2407+ .serdes = sm8450_qmp_gen3x1_pcie_rc_serdes_tbl,
2408+ .serdes_num = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_rc_serdes_tbl),
2409+ .rx = sm8450_qmp_gen3x1_pcie_rc_rx_tbl,
2410+ .rx_num = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_rc_rx_tbl),
2411+ },
2412+
20332413 .clk_list = sdm845_pciephy_clk_l,
20342414 .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l),
20352415 .reset_list = sdm845_pciephy_reset_l,
20362416 .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
20372417 .vreg_list = qmp_phy_vreg_l,
20382418 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
2039− .regs = sm8250_pcie_regs_layout,
2419+ .regs = pciephy_v5_regs_layout,
20402420
20412421 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
20422422 .phy_status = PHYSTATUS,
@@ -2078,12 +2458,73 @@ static const struct qmp_phy_cfg sm8450_qmp_gen4x2_pciephy_cfg = { · 35 unmodified lines
20782458 .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
20792459 .vreg_list = qmp_phy_vreg_l,
20802460 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
2081− .regs = sm8250_pcie_regs_layout,
2461+ .regs = pciephy_v5_regs_layout,
20822462
20832463 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
20842464 .phy_status = PHYSTATUS_4_20,
20852465 };
20862466
2467+static const struct qmp_phy_cfg sm8550_qmp_gen3x2_pciephy_cfg = {
2468+ .lanes = 2,
2469+
2470+ .offsets = &qmp_pcie_offsets_v5,
2471+
2472+ .tbls = {
2473+ .serdes = sm8550_qmp_gen3x2_pcie_serdes_tbl,
2474+ .serdes_num = ARRAY_SIZE(sm8550_qmp_gen3x2_pcie_serdes_tbl),
2475+ .tx = sm8550_qmp_gen3x2_pcie_tx_tbl,
2476+ .tx_num = ARRAY_SIZE(sm8550_qmp_gen3x2_pcie_tx_tbl),
2477+ .rx = sm8550_qmp_gen3x2_pcie_rx_tbl,
2478+ .rx_num = ARRAY_SIZE(sm8550_qmp_gen3x2_pcie_rx_tbl),
2479+ .pcs = sm8550_qmp_gen3x2_pcie_pcs_tbl,
2480+ .pcs_num = ARRAY_SIZE(sm8550_qmp_gen3x2_pcie_pcs_tbl),
2481+ .pcs_misc = sm8550_qmp_gen3x2_pcie_pcs_misc_tbl,
2482+ .pcs_misc_num = ARRAY_SIZE(sm8550_qmp_gen3x2_pcie_pcs_misc_tbl),
2483+ },
2484+ .clk_list = sc8280xp_pciephy_clk_l,
2485+ .num_clks = ARRAY_SIZE(sc8280xp_pciephy_clk_l),
2486+ .reset_list = sdm845_pciephy_reset_l,
2487+ .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
2488+ .vreg_list = qmp_phy_vreg_l,
2489+ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
2490+ .regs = pciephy_v5_regs_layout,
2491+
2492+ .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
2493+ .phy_status = PHYSTATUS,
2494+};
2495+
2496+static const struct qmp_phy_cfg sm8550_qmp_gen4x2_pciephy_cfg = {
2497+ .lanes = 2,
2498+
2499+ .offsets = &qmp_pcie_offsets_v6_20,
2500+
2501+ .tbls = {
2502+ .serdes = sm8550_qmp_gen4x2_pcie_serdes_tbl,
2503+ .serdes_num = ARRAY_SIZE(sm8550_qmp_gen4x2_pcie_serdes_tbl),
2504+ .tx = sm8550_qmp_gen4x2_pcie_tx_tbl,
2505+ .tx_num = ARRAY_SIZE(sm8550_qmp_gen4x2_pcie_tx_tbl),
2506+ .rx = sm8550_qmp_gen4x2_pcie_rx_tbl,
2507+ .rx_num = ARRAY_SIZE(sm8550_qmp_gen4x2_pcie_rx_tbl),
2508+ .pcs = sm8550_qmp_gen4x2_pcie_pcs_tbl,
2509+ .pcs_num = ARRAY_SIZE(sm8550_qmp_gen4x2_pcie_pcs_tbl),
2510+ .pcs_misc = sm8550_qmp_gen4x2_pcie_pcs_misc_tbl,
2511+ .pcs_misc_num = ARRAY_SIZE(sm8550_qmp_gen4x2_pcie_pcs_misc_tbl),
2512+ .ln_shrd = sm8550_qmp_gen4x2_pcie_ln_shrd_tbl,
2513+ .ln_shrd_num = ARRAY_SIZE(sm8550_qmp_gen4x2_pcie_ln_shrd_tbl),
2514+ },
2515+ .clk_list = sc8280xp_pciephy_clk_l,
2516+ .num_clks = ARRAY_SIZE(sc8280xp_pciephy_clk_l),
2517+ .reset_list = sdm845_pciephy_reset_l,
2518+ .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
2519+ .vreg_list = sm8550_qmp_phy_vreg_l,
2520+ .num_vregs = ARRAY_SIZE(sm8550_qmp_phy_vreg_l),
2521+ .regs = pciephy_v5_regs_layout,
2522+
2523+ .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
2524+ .phy_status = PHYSTATUS_4_20,
2525+ .has_nocsr_reset = true,
2526+};
2527+
20872528 static void qmp_pcie_configure_lane(void __iomem *base,
20882529 const struct qmp_phy_init_tbl tbl[],
20892530 int num,
@@ -2138,6 +2579,7 @@ static void qmp_pcie_init_registers(struct qmp_pcie *qmp, const struct qmp_phy_c · 48 unmodified lines
21382579 void __iomem *rx2 = qmp->rx2;
21392580 void __iomem *pcs = qmp->pcs;
21402581 void __iomem *pcs_misc = qmp->pcs_misc;
2582+ void __iomem *ln_shrd = qmp->ln_shrd;
21412583
21422584 if (!tbls)
21432585 return;
@@ -2159,6 +2601,8 @@ static void qmp_pcie_init_registers(struct qmp_pcie *qmp, const struct qmp_phy_c · 15 unmodified lines
21592601 qmp_pcie_configure(serdes, cfg->serdes_4ln_tbl, cfg->serdes_4ln_num);
21602602 qmp_pcie_init_port_b(qmp, tbls);
21612603 }
2604+
2605+ qmp_pcie_configure(ln_shrd, tbls->ln_shrd, tbls->ln_shrd_num);
21622606 }
21632607
21642608 static int qmp_pcie_init(struct phy *phy)
@@ -2179,12 +2623,18 @@ static int qmp_pcie_init(struct phy *phy) · 14 unmodified lines
21792623 goto err_disable_regulators;
21802624 }
21812625
2626+ ret = reset_control_assert(qmp->nocsr_reset);
2627+ if (ret) {
2628+ dev_err(qmp->dev, "no-csr reset assert failed\n");
2629+ goto err_assert_reset;
2630+ }
2631+
21822632 usleep_range(200, 300);
21832633
21842634 ret = reset_control_bulk_deassert(cfg->num_resets, qmp->resets);
21852635 if (ret) {
21862636 dev_err(qmp->dev, "reset deassert failed\n");
2187− goto err_disable_regulators;
2637+ goto err_assert_reset;
21882638 }
21892639
21902640 ret = clk_bulk_prepare_enable(cfg->num_clks, qmp->clks);
@@ -2240,6 +2690,12 @@ static int qmp_pcie_power_on(struct phy *phy) · 49 unmodified lines
22402690 if (ret)
22412691 return ret;
22422692
2693+ ret = reset_control_deassert(qmp->nocsr_reset);
2694+ if (ret) {
2695+ dev_err(qmp->dev, "no-csr reset deassert failed\n");
2696+ goto err_disable_pipe_clk;
2697+ }
2698+
22432699 /* Pull PHY out of reset state */
22442700 qphy_clrbits(pcs, cfg->regs[QPHY_SW_RESET], SW_RESET);
22452701
@@ -2373,6 +2829,13 @@ static int qmp_pcie_reset_init(struct qmp_pcie *qmp) · 127 unmodified lines
23732829 if (ret)
23742830 return dev_err_probe(dev, ret, "failed to get resets\n");
23752831
2832+ if (cfg->has_nocsr_reset) {
2833+ qmp->nocsr_reset = devm_reset_control_get_exclusive(dev, "phy_nocsr");
2834+ if (IS_ERR(qmp->nocsr_reset))
2835+ return dev_err_probe(dev, PTR_ERR(qmp->nocsr_reset),
2836+ "failed to get no-csr reset\n");
2837+ }
2838+
23762839 return 0;
23772840 }
23782841
@@ -2595,11 +3058,18 @@ static int qmp_pcie_parse_dt(struct qmp_pcie *qmp) · 216 unmodified lines
25953058 return PTR_ERR(qmp->port_b);
25963059 }
25973060
3061+ if (cfg->tbls.ln_shrd)
3062+ qmp->ln_shrd = base + offs->ln_shrd;
3063+
25983064 qmp->num_pipe_clks = 2;
25993065 qmp->pipe_clks[0].id = "pipe";
26003066 qmp->pipe_clks[1].id = "pipediv2";
26013067
2602− ret = devm_clk_bulk_get(dev, qmp->num_pipe_clks, qmp->pipe_clks);
3068+ ret = devm_clk_bulk_get(dev, 1, qmp->pipe_clks);
3069+ if (ret)
3070+ return ret;
3071+
3072+ ret = devm_clk_bulk_get_optional(dev, qmp->num_pipe_clks - 1, qmp->pipe_clks + 1);
26033073 if (ret)
26043074 return ret;
26053075
@@ -2719,12 +3189,24 @@ static const struct of_device_id qmp_pcie_of_match_table[] = { · 113 unmodified lines
27193189 }, {
27203190 .compatible = "qcom,sm8250-qmp-modem-pcie-phy",
27213191 .data = &sm8250_qmp_gen3x2_pciephy_cfg,
3192+ }, {
3193+ .compatible = "qcom,sm8350-qmp-gen3x1-pcie-phy",
3194+ .data = &sm8350_qmp_gen3x1_pciephy_cfg,
3195+ }, {
3196+ .compatible = "qcom,sm8350-qmp-gen3x2-pcie-phy",
3197+ .data = &sm8350_qmp_gen3x2_pciephy_cfg,
27223198 }, {
27233199 .compatible = "qcom,sm8450-qmp-gen3x1-pcie-phy",
27243200 .data = &sm8450_qmp_gen3x1_pciephy_cfg,
27253201 }, {
27263202 .compatible = "qcom,sm8450-qmp-gen4x2-pcie-phy",
27273203 .data = &sm8450_qmp_gen4x2_pciephy_cfg,
3204+ }, {
3205+ .compatible = "qcom,sm8550-qmp-gen3x2-pcie-phy",
3206+ .data = &sm8550_qmp_gen3x2_pciephy_cfg,
3207+ }, {
3208+ .compatible = "qcom,sm8550-qmp-gen4x2-pcie-phy",
3209+ .data = &sm8550_qmp_gen4x2_pciephy_cfg,
27283210 },
27293211 { },
27303212 };
drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v6.h+15−0
@@ -0,0 +1,15 @@
1+/* SPDX-License-Identifier: GPL-2.0 */
2+/*
3+ * Copyright (c) 2023, Linaro Limited
4+ */
5+
6+#ifndef QCOM_PHY_QMP_PCS_PCIE_V6_H_
7+#define QCOM_PHY_QMP_PCS_PCIE_V6_H_
8+
9+/* Only for QMP V6 PHY - PCIE have different offsets than V5 */
10+#define QPHY_PCIE_V6_PCS_PCIE_POWER_STATE_CONFIG2 0x0c
11+#define QPHY_PCIE_V6_PCS_PCIE_POWER_STATE_CONFIG4 0x14
12+#define QPHY_PCIE_V6_PCS_PCIE_ENDPOINT_REFCLK_DRIVE 0x20
13+#define QPHY_PCIE_V6_PCS_PCIE_OSC_DTCT_ACTIONS 0x94
14+
15+#endif
drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v6_20.h+23−0
@@ -0,0 +1,23 @@
1+/* SPDX-License-Identifier: GPL-2.0 */
2+/*
3+ * Copyright (c) 2023, Linaro Limited
4+ */
5+
6+#ifndef QCOM_PHY_QMP_PCS_PCIE_V6_20_H_
7+#define QCOM_PHY_QMP_PCS_PCIE_V6_20_H_
8+
9+/* Only for QMP V6_20 PHY - PCIE have different offsets than V5 */
10+#define QPHY_PCIE_V6_20_PCS_POWER_STATE_CONFIG2 0x00c
11+#define QPHY_PCIE_V6_20_PCS_TX_RX_CONFIG 0x018
12+#define QPHY_PCIE_V6_20_PCS_ENDPOINT_REFCLK_DRIVE 0x01c
13+#define QPHY_PCIE_V6_20_PCS_OSC_DTCT_ATCIONS 0x090
14+#define QPHY_PCIE_V6_20_PCS_EQ_CONFIG1 0x0a0
15+#define QPHY_PCIE_V6_20_PCS_EQ_CONFIG5 0x108
16+#define QPHY_PCIE_V6_20_PCS_G4_PRE_GAIN 0x15c
17+#define QPHY_PCIE_V6_20_PCS_RX_MARGINING_CONFIG1 0x17c
18+#define QPHY_PCIE_V6_20_PCS_RX_MARGINING_CONFIG3 0x184
19+#define QPHY_PCIE_V6_20_PCS_RX_MARGINING_CONFIG5 0x18c
20+#define QPHY_PCIE_V6_20_PCS_G3_FOM_EQ_CONFIG5 0x1ac
21+#define QPHY_PCIE_V6_20_PCS_G4_FOM_EQ_CONFIG5 0x1c0
22+
23+#endif
drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v2.h+25−0
@@ -0,0 +1,25 @@
1+/* SPDX-License-Identifier: GPL-2.0 */
2+/*
3+ * Copyright (c) 2017, The Linux Foundation. All rights reserved.
4+ */
5+
6+#ifndef QCOM_PHY_QMP_PCS_UFS_V2_H_
7+#define QCOM_PHY_QMP_PCS_UFS_V2_H_
8+
9+#define QPHY_V2_PCS_UFS_PHY_START 0x000
10+#define QPHY_V2_PCS_UFS_POWER_DOWN_CONTROL 0x004
11+
12+#define QPHY_V2_PCS_UFS_TX_LARGE_AMP_DRV_LVL 0x034
13+#define QPHY_V2_PCS_UFS_TX_LARGE_AMP_POST_EMP_LVL 0x038
14+#define QPHY_V2_PCS_UFS_TX_SMALL_AMP_DRV_LVL 0x03c
15+#define QPHY_V2_PCS_UFS_TX_SMALL_AMP_POST_EMP_LVL 0x040
16+
17+#define QPHY_V2_PCS_UFS_RX_MIN_STALL_NOCONFIG_TIME_CAP 0x0cc
18+#define QPHY_V2_PCS_UFS_RX_SYM_RESYNC_CTRL 0x13c
19+#define QPHY_V2_PCS_UFS_RX_MIN_HIBERN8_TIME 0x140
20+#define QPHY_V2_PCS_UFS_RX_SIGDET_CTRL2 0x148
21+#define QPHY_V2_PCS_UFS_RX_PWM_GEAR_BAND 0x154
22+
23+#define QPHY_V2_PCS_UFS_READY_STATUS 0x168
24+
25+#endif
drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v3.h+3−0
@@ -6,12 +6,15 @@ · 5 unmodified lines
66 #ifndef QCOM_PHY_QMP_PCS_UFS_V3_H_
77 #define QCOM_PHY_QMP_PCS_UFS_V3_H_
88
9+#define QPHY_V3_PCS_UFS_PHY_START 0x000
10+#define QPHY_V3_PCS_UFS_POWER_DOWN_CONTROL 0x004
911 #define QPHY_V3_PCS_UFS_TX_LARGE_AMP_DRV_LVL 0x02c
1012 #define QPHY_V3_PCS_UFS_TX_SMALL_AMP_DRV_LVL 0x034
1113 #define QPHY_V3_PCS_UFS_RX_SYM_RESYNC_CTRL 0x134
1214 #define QPHY_V3_PCS_UFS_RX_MIN_HIBERN8_TIME 0x138
1315 #define QPHY_V3_PCS_UFS_RX_SIGDET_CTRL1 0x13c
1416 #define QPHY_V3_PCS_UFS_RX_SIGDET_CTRL2 0x140
17+#define QPHY_V3_PCS_UFS_READY_STATUS 0x160
1518 #define QPHY_V3_PCS_UFS_TX_MID_TERM_CTRL1 0x1bc
1619 #define QPHY_V3_PCS_UFS_MULTI_LANE_CTRL1 0x1c4
1720
drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v5.h+5−0
@@ -8,11 +8,15 @@ · 7 unmodified lines
88 #define QCOM_PHY_QMP_PCS_UFS_V5_H_
99
1010 /* Only for QMP V5 PHY - UFS PCS registers */
11+#define QPHY_V5_PCS_UFS_PHY_START 0x000
12+#define QPHY_V5_PCS_UFS_POWER_DOWN_CONTROL 0x004
13+#define QPHY_V5_PCS_UFS_SW_RESET 0x008
1114 #define QPHY_V5_PCS_UFS_TIMER_20US_CORECLK_STEPS_MSB 0x00c
1215 #define QPHY_V5_PCS_UFS_TIMER_20US_CORECLK_STEPS_LSB 0x010
1316 #define QPHY_V5_PCS_UFS_PLL_CNTL 0x02c
1417 #define QPHY_V5_PCS_UFS_TX_LARGE_AMP_DRV_LVL 0x030
1518 #define QPHY_V5_PCS_UFS_TX_SMALL_AMP_DRV_LVL 0x038
19+#define QPHY_V5_PCS_UFS_BIST_FIXED_PAT_CTRL 0x060
1620 #define QPHY_V5_PCS_UFS_TX_HSGEAR_CAPABILITY 0x074
1721 #define QPHY_V5_PCS_UFS_RX_HSGEAR_CAPABILITY 0x0b4
1822 #define QPHY_V5_PCS_UFS_DEBUG_BUS_CLKSEL 0x124
@@ -21,6 +25,7 @@ · 2 unmodified lines
2125 #define QPHY_V5_PCS_UFS_RX_SIGDET_CTRL2 0x158
2226 #define QPHY_V5_PCS_UFS_TX_PWM_GEAR_BAND 0x160
2327 #define QPHY_V5_PCS_UFS_TX_HS_GEAR_BAND 0x168
28+#define QPHY_V5_PCS_UFS_READY_STATUS 0x180
2429 #define QPHY_V5_PCS_UFS_TX_MID_TERM_CTRL1 0x1d8
2530 #define QPHY_V5_PCS_UFS_MULTI_LANE_CTRL1 0x1e0
2631
drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v6.h+31−0
@@ -0,0 +1,31 @@
1+/* SPDX-License-Identifier: GPL-2.0 */
2+/*
3+ * Copyright (c) 2023, Linaro Limited
4+ */
5+
6+#ifndef QCOM_PHY_QMP_PCS_UFS_V6_H_
7+#define QCOM_PHY_QMP_PCS_UFS_V6_H_
8+
9+/* Only for QMP V6 PHY - UFS PCS registers */
10+#define QPHY_V6_PCS_UFS_PHY_START 0x000
11+#define QPHY_V6_PCS_UFS_POWER_DOWN_CONTROL 0x004
12+#define QPHY_V6_PCS_UFS_SW_RESET 0x008
13+#define QPHY_V6_PCS_UFS_TIMER_20US_CORECLK_STEPS_MSB 0x00c
14+#define QPHY_V6_PCS_UFS_TIMER_20US_CORECLK_STEPS_LSB 0x010
15+#define QPHY_V6_PCS_UFS_PLL_CNTL 0x02c
16+#define QPHY_V6_PCS_UFS_TX_LARGE_AMP_DRV_LVL 0x030
17+#define QPHY_V6_PCS_UFS_TX_SMALL_AMP_DRV_LVL 0x038
18+#define QPHY_V6_PCS_UFS_BIST_FIXED_PAT_CTRL 0x060
19+#define QPHY_V6_PCS_UFS_TX_HSGEAR_CAPABILITY 0x074
20+#define QPHY_V6_PCS_UFS_RX_HSGEAR_CAPABILITY 0x0bc
21+#define QPHY_V6_PCS_UFS_DEBUG_BUS_CLKSEL 0x158
22+#define QPHY_V6_PCS_UFS_LINECFG_DISABLE 0x17c
23+#define QPHY_V6_PCS_UFS_RX_MIN_HIBERN8_TIME 0x184
24+#define QPHY_V6_PCS_UFS_RX_SIGDET_CTRL2 0x18c
25+#define QPHY_V6_PCS_UFS_TX_PWM_GEAR_BAND 0x178
26+#define QPHY_V6_PCS_UFS_TX_HS_GEAR_BAND 0x174
27+#define QPHY_V6_PCS_UFS_READY_STATUS 0x1a8
28+#define QPHY_V6_PCS_UFS_TX_MID_TERM_CTRL1 0x1f4
29+#define QPHY_V6_PCS_UFS_MULTI_LANE_CTRL1 0x1fc
30+
31+#endif
drivers/phy/qualcomm/phy-qcom-qmp-pcs-usb-v6.h+31−0
@@ -0,0 +1,31 @@
1+/* SPDX-License-Identifier: GPL-2.0 */
2+/*
3+ * Copyright (c) 2022, The Linux Foundation. All rights reserved.
4+ */
5+
6+#ifndef QCOM_PHY_QMP_PCS_USB_V6_H_
7+#define QCOM_PHY_QMP_PCS_USB_V6_H_
8+
9+/* Only for QMP V6 PHY - USB3 have different offsets than V5 */
10+#define QPHY_USB_V6_PCS_LOCK_DETECT_CONFIG1 0xc4
11+#define QPHY_USB_V6_PCS_LOCK_DETECT_CONFIG2 0xc8
12+#define QPHY_USB_V6_PCS_LOCK_DETECT_CONFIG3 0xcc
13+#define QPHY_USB_V6_PCS_LOCK_DETECT_CONFIG6 0xd8
14+#define QPHY_USB_V6_PCS_REFGEN_REQ_CONFIG1 0xdc
15+#define QPHY_USB_V6_PCS_USB3_POWER_STATE_CONFIG1 0x90
16+#define QPHY_USB_V6_PCS_RX_SIGDET_LVL 0x188
17+#define QPHY_USB_V6_PCS_RCVR_DTCT_DLY_P1U2_L 0x190
18+#define QPHY_USB_V6_PCS_RCVR_DTCT_DLY_P1U2_H 0x194
19+#define QPHY_USB_V6_PCS_CDR_RESET_TIME 0x1b0
20+#define QPHY_USB_V6_PCS_ALIGN_DETECT_CONFIG1 0x1c0
21+#define QPHY_USB_V6_PCS_ALIGN_DETECT_CONFIG2 0x1c4
22+#define QPHY_USB_V6_PCS_PCS_TX_RX_CONFIG 0x1d0
23+#define QPHY_USB_V6_PCS_EQ_CONFIG1 0x1dc
24+#define QPHY_USB_V6_PCS_EQ_CONFIG5 0x1ec
25+
26+#define QPHY_USB_V6_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL 0x18
27+#define QPHY_USB_V6_PCS_USB3_RXEQTRAINING_DFE_TIME_S2 0x3c
28+#define QPHY_USB_V6_PCS_USB3_RCVR_DTCT_DLY_U3_L 0x40
29+#define QPHY_USB_V6_PCS_USB3_RCVR_DTCT_DLY_U3_H 0x44
30+
31+#endif
drivers/phy/qualcomm/phy-qcom-qmp-pcs-v2.h+8−11
@@ -7,13 +7,11 @@ · 6 unmodified lines
77 #define QCOM_PHY_QMP_PCS_V2_H_
88
99 /* Only for QMP V2 PHY - PCS registers */
10+#define QPHY_V2_PCS_SW_RESET 0x000
1011 #define QPHY_V2_PCS_POWER_DOWN_CONTROL 0x004
12+#define QPHY_V2_PCS_START_CONTROL 0x008
1113 #define QPHY_V2_PCS_TXDEEMPH_M6DB_V0 0x024
1214 #define QPHY_V2_PCS_TXDEEMPH_M3P5DB_V0 0x028
13−#define QPHY_V2_PCS_TX_LARGE_AMP_DRV_LVL 0x034
14−#define QPHY_V2_PCS_TX_LARGE_AMP_POST_EMP_LVL 0x038
15−#define QPHY_V2_PCS_TX_SMALL_AMP_DRV_LVL 0x03c
16−#define QPHY_V2_PCS_TX_SMALL_AMP_POST_EMP_LVL 0x040
1715 #define QPHY_V2_PCS_ENDPOINT_REFCLK_DRIVE 0x054
1816 #define QPHY_V2_PCS_RX_IDLE_DTCT_CNTRL 0x058
1917 #define QPHY_V2_PCS_POWER_STATE_CONFIG1 0x060
@@ -30,17 +28,16 @@ · 10 unmodified lines
3028 #define QPHY_V2_PCS_FLL_CNT_VAL_L 0x0c8
3129 #define QPHY_V2_PCS_FLL_CNT_VAL_H_TOL 0x0cc
3230 #define QPHY_V2_PCS_FLL_MAN_CODE 0x0d0
33−
34−/* UFS only ? */
35−#define QPHY_V2_PCS_RX_MIN_STALL_NOCONFIG_TIME_CAP 0x0cc
36−#define QPHY_V2_PCS_RX_SYM_RESYNC_CTRL 0x13c
37−#define QPHY_V2_PCS_RX_MIN_HIBERN8_TIME 0x140
38−#define QPHY_V2_PCS_RX_SIGDET_CTRL2 0x148
39−#define QPHY_V2_PCS_RX_PWM_GEAR_BAND 0x154
31+#define QPHY_V2_PCS_AUTONOMOUS_MODE_CTRL 0x0d4
32+#define QPHY_V2_PCS_LFPS_RXTERM_IRQ_CLEAR 0x0d8
33+#define QPHY_V2_PCS_LFPS_RXTERM_IRQ_STATUS 0x178
34+#define QPHY_V2_PCS_USB_PCS_STATUS 0x17c /* USB */
4035 #define QPHY_V2_PCS_PLL_LOCK_CHK_DLY_TIME_AUXCLK_LSB 0x1a8
4136 #define QPHY_V2_PCS_OSC_DTCT_ACTIONS 0x1ac
4237 #define QPHY_V2_PCS_RX_SIGDET_LVL 0x1d8
4338 #define QPHY_V2_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB 0x1dc
4439 #define QPHY_V2_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB 0x1e0
4540
41+#define QPHY_V2_PCS_PCI_PCS_STATUS 0x174 /* PCI */
42+
4643 #endif
drivers/phy/qualcomm/phy-qcom-qmp-pcs-v5.h+4−0
@@ -7,6 +7,10 @@ · 6 unmodified lines
77 #define QCOM_PHY_QMP_PCS_V5_H_
88
99 /* Only for QMP V5 PHY - USB/PCIe PCS registers */
10+#define QPHY_V5_PCS_SW_RESET 0x000
11+#define QPHY_V5_PCS_PCS_STATUS1 0x014
12+#define QPHY_V5_PCS_POWER_DOWN_CONTROL 0x040
13+#define QPHY_V5_PCS_START_CONTROL 0x044
1014 #define QPHY_V5_PCS_LOCK_DETECT_CONFIG1 0x0c4
1115 #define QPHY_V5_PCS_LOCK_DETECT_CONFIG2 0x0c8
1216 #define QPHY_V5_PCS_LOCK_DETECT_CONFIG3 0x0cc
drivers/phy/qualcomm/phy-qcom-qmp-pcs-v6.h+16−0
@@ -0,0 +1,16 @@
1+/* SPDX-License-Identifier: GPL-2.0 */
2+/*
3+ * Copyright (c) 2023, Linaro Limited
4+ */
5+
6+#ifndef QCOM_PHY_QMP_PCS_V6_H_
7+#define QCOM_PHY_QMP_PCS_V6_H_
8+
9+/* Only for QMP V6 PHY - USB/PCIe PCS registers */
10+#define QPHY_V6_PCS_REFGEN_REQ_CONFIG1 0xdc
11+#define QPHY_V6_PCS_RX_SIGDET_LVL 0x188
12+#define QPHY_V6_PCS_RATE_SLEW_CNTRL1 0x198
13+#define QPHY_V6_PCS_EQ_CONFIG2 0x1e0
14+#define QPHY_V6_PCS_PCS_TX_RX_CONFIG 0x1d0
15+
16+#endif
drivers/phy/qualcomm/phy-qcom-qmp-pcs-v6_20.h+18−0
@@ -0,0 +1,18 @@
1+/* SPDX-License-Identifier: GPL-2.0 */
2+/*
3+ * Copyright (c) 2023, Linaro Limited
4+ */
5+
6+#ifndef QCOM_PHY_QMP_PCS_V6_20_H_
7+#define QCOM_PHY_QMP_PCS_V6_20_H_
8+
9+/* Only for QMP V6_20 PHY - USB/PCIe PCS registers */
10+#define QPHY_V6_20_PCS_G3S2_PRE_GAIN 0x178
11+#define QPHY_V6_20_PCS_RX_SIGDET_LVL 0x190
12+#define QPHY_V6_20_PCS_COM_ELECIDLE_DLY_SEL 0x1b8
13+#define QPHY_V6_20_PCS_TX_RX_CONFIG1 0x1dc
14+#define QPHY_V6_20_PCS_TX_RX_CONFIG2 0x1e0
15+#define QPHY_V6_20_PCS_EQ_CONFIG4 0x1f8
16+#define QPHY_V6_20_PCS_EQ_CONFIG5 0x1fc
17+
18+#endif
drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v6.h+82−0
@@ -0,0 +1,82 @@
1+/* SPDX-License-Identifier: GPL-2.0 */
2+/*
3+ * Copyright (c) 2023, Linaro Limited
4+ */
5+
6+#ifndef QCOM_PHY_QMP_QSERDES_COM_V6_H_
7+#define QCOM_PHY_QMP_QSERDES_COM_V6_H_
8+
9+/* Only for QMP V6 PHY - QSERDES COM registers */
10+
11+#define QSERDES_V6_COM_SSC_STEP_SIZE1_MODE1 0x00
12+#define QSERDES_V6_COM_SSC_STEP_SIZE2_MODE1 0x04
13+#define QSERDES_V6_COM_CP_CTRL_MODE1 0x10
14+#define QSERDES_V6_COM_PLL_RCTRL_MODE1 0x14
15+#define QSERDES_V6_COM_PLL_CCTRL_MODE1 0x18
16+#define QSERDES_V6_COM_CORECLK_DIV_MODE1 0x1c
17+#define QSERDES_V6_COM_LOCK_CMP1_MODE1 0x20
18+#define QSERDES_V6_COM_LOCK_CMP2_MODE1 0x24
19+#define QSERDES_V6_COM_DEC_START_MODE1 0x28
20+#define QSERDES_V6_COM_DEC_START_MSB_MODE1 0x2c
21+#define QSERDES_V6_COM_DIV_FRAC_START1_MODE1 0x30
22+#define QSERDES_V6_COM_DIV_FRAC_START2_MODE1 0x34
23+#define QSERDES_V6_COM_DIV_FRAC_START3_MODE1 0x38
24+#define QSERDES_V6_COM_HSCLK_SEL_1 0x3c
25+#define QSERDES_V6_COM_VCO_TUNE1_MODE1 0x48
26+#define QSERDES_V6_COM_VCO_TUNE2_MODE1 0x4c
27+#define QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE1_MODE1 0x50
28+#define QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE2_MODE1 0x54
29+#define QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE1_MODE0 0x58
30+#define QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE2_MODE0 0x5c
31+#define QSERDES_V6_COM_SSC_STEP_SIZE1_MODE0 0x60
32+#define QSERDES_V6_COM_SSC_STEP_SIZE2_MODE0 0x64
33+#define QSERDES_V6_COM_CP_CTRL_MODE0 0x70
34+#define QSERDES_V6_COM_PLL_RCTRL_MODE0 0x74
35+#define QSERDES_V6_COM_PLL_CCTRL_MODE0 0x78
36+#define QSERDES_V6_COM_PLL_CORE_CLK_DIV_MODE0 0x7c
37+#define QSERDES_V6_COM_LOCK_CMP1_MODE0 0x80
38+#define QSERDES_V6_COM_LOCK_CMP2_MODE0 0x84
39+#define QSERDES_V6_COM_DEC_START_MODE0 0x88
40+#define QSERDES_V6_COM_DEC_START_MSB_MODE0 0x8c
41+#define QSERDES_V6_COM_DIV_FRAC_START1_MODE0 0x90
42+#define QSERDES_V6_COM_DIV_FRAC_START2_MODE0 0x94
43+#define QSERDES_V6_COM_DIV_FRAC_START3_MODE0 0x98
44+#define QSERDES_V6_COM_HSCLK_HS_SWITCH_SEL_1 0x9c
45+#define QSERDES_V6_COM_INTEGLOOP_GAIN0_MODE0 0xa0
46+#define QSERDES_V6_COM_INTEGLOOP_GAIN1_MODE0 0xa4
47+#define QSERDES_V6_COM_VCO_TUNE1_MODE0 0xa8
48+#define QSERDES_V6_COM_VCO_TUNE2_MODE0 0xac
49+#define QSERDES_V6_COM_BG_TIMER 0xbc
50+#define QSERDES_V6_COM_SSC_EN_CENTER 0xc0
51+#define QSERDES_V6_COM_SSC_PER1 0xcc
52+#define QSERDES_V6_COM_SSC_PER2 0xd0
53+#define QSERDES_V6_COM_PLL_POST_DIV_MUX 0xd8
54+#define QSERDES_V6_COM_PLL_BIAS_EN_CLK_BUFLR_EN 0xdc
55+#define QSERDES_V6_COM_CLK_ENABLE1 0xe0
56+#define QSERDES_V6_COM_SYS_CLK_CTRL 0xe4
57+#define QSERDES_V6_COM_SYSCLK_BUF_ENABLE 0xe8
58+#define QSERDES_V6_COM_PLL_IVCO 0xf4
59+#define QSERDES_V6_COM_SYSCLK_EN_SEL 0x110
60+#define QSERDES_V6_COM_RESETSM_CNTRL 0x118
61+#define QSERDES_V6_COM_LOCK_CMP_EN 0x120
62+#define QSERDES_V6_COM_LOCK_CMP_CFG 0x124
63+#define QSERDES_V6_COM_VCO_TUNE_CTRL 0x13c
64+#define QSERDES_V6_COM_VCO_TUNE_MAP 0x140
65+#define QSERDES_V6_COM_VCO_TUNE_INITVAL2 0x148
66+#define QSERDES_V6_COM_CLK_SELECT 0x164
67+#define QSERDES_V6_COM_CORE_CLK_EN 0x170
68+#define QSERDES_V6_COM_CMN_CONFIG_1 0x174
69+#define QSERDES_V6_COM_SVS_MODE_CLK_SEL 0x17c
70+#define QSERDES_V6_COM_CMN_MISC_1 0x184
71+#define QSERDES_V6_COM_CMN_MODE 0x188
72+#define QSERDES_V6_COM_PLL_VCO_DC_LEVEL_CTRL 0x198
73+#define QSERDES_V6_COM_AUTO_GAIN_ADJ_CTRL_1 0x1a4
74+#define QSERDES_V6_COM_AUTO_GAIN_ADJ_CTRL_2 0x1a8
75+#define QSERDES_V6_COM_AUTO_GAIN_ADJ_CTRL_3 0x1ac
76+#define QSERDES_V6_COM_ADDITIONAL_MISC 0x1b4
77+#define QSERDES_V6_COM_ADDITIONAL_MISC_2 0x1b8
78+#define QSERDES_V6_COM_ADDITIONAL_MISC_3 0x1bc
79+#define QSERDES_V6_COM_CMN_STATUS 0x1d0
80+#define QSERDES_V6_COM_C_READY_STATUS 0x1f8
81+
82+#endif
drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com.h+1−1
@@ -135,6 +135,6 @@ · 134 unmodified lines
135135 #define QSERDES_COM_CMN_MISC2 0x1b8
136136 #define QSERDES_COM_CORECLK_DIV_MODE1 0x1bc
137137 #define QSERDES_COM_CORECLK_DIV_MODE2 0x1c0
138−#define QSERDES_COM_CMN_RSVD5 0x1c0
138+#define QSERDES_COM_CMN_RSVD5 0x1c4
139139
140140 #endif
drivers/phy/qualcomm/phy-qcom-qmp-qserdes-ln-shrd-v6.h+32−0
@@ -0,0 +1,32 @@
1+/* SPDX-License-Identifier: GPL-2.0 */
2+/*
3+ * Copyright (c) 2023, Linaro Limited
4+ */
5+
6+#ifndef QCOM_PHY_QMP_QSERDES_LN_SHRD_V6_H_
7+#define QCOM_PHY_QMP_QSERDES_LN_SHRD_V6_H_
8+
9+#define QSERDES_V6_LN_SHRD_RXCLK_DIV2_CTRL 0xa0
10+#define QSERDES_V6_LN_SHRD_RX_Q_EN_RATES 0xb0
11+#define QSERDES_V6_LN_SHRD_DFE_DAC_ENABLE1 0xb4
12+#define QSERDES_V6_LN_SHRD_TX_ADAPT_POST_THRESH1 0xc4
13+#define QSERDES_V6_LN_SHRD_TX_ADAPT_POST_THRESH2 0xc8
14+#define QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B0 0xd4
15+#define QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B1 0xd8
16+#define QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B2 0xdc
17+#define QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B3 0xe0
18+#define QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B4 0xe4
19+#define QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B5 0xe8
20+#define QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B6 0xec
21+#define QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH1_RATE210 0xf0
22+#define QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH1_RATE3 0xf4
23+#define QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH2_RATE210 0xf8
24+#define QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH2_RATE3 0xfc
25+#define QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH3_RATE210 0x100
26+#define QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH3_RATE3 0x104
27+#define QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH4_RATE3 0x10c
28+#define QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH5_RATE3 0x114
29+#define QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH6_RATE3 0x11c
30+#define QSERDES_V6_LN_SHRD_RX_SUMMER_CAL_SPD_MODE 0x128
31+
32+#endif
drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-ufs-v6.h+30−0
@@ -0,0 +1,30 @@
1+/* SPDX-License-Identifier: GPL-2.0 */
2+/*
3+ * Copyright (c) 2023, Linaro Limited
4+ */
5+
6+#ifndef QCOM_PHY_QMP_QSERDES_TXRX_UFS_V6_H_
7+#define QCOM_PHY_QMP_QSERDES_TXRX_UFS_V6_H_
8+
9+#define QSERDES_UFS_V6_TX_RES_CODE_LANE_TX 0x28
10+#define QSERDES_UFS_V6_TX_RES_CODE_LANE_RX 0x2c
11+#define QSERDES_UFS_V6_TX_RES_CODE_LANE_OFFSET_TX 0x30
12+#define QSERDES_UFS_V6_TX_RES_CODE_LANE_OFFSET_RX 0x34
13+
14+#define QSERDES_UFS_V6_RX_UCDR_FASTLOCK_FO_GAIN_RATE2 0x08
15+#define QSERDES_UFS_V6_RX_UCDR_FASTLOCK_FO_GAIN_RATE4 0x10
16+#define QSERDES_UFS_V6_RX_VGA_CAL_MAN_VAL 0x178
17+#define QSERDES_UFS_V6_RX_MODE_RATE_0_1_B0 0x208
18+#define QSERDES_UFS_V6_RX_MODE_RATE_0_1_B1 0x20c
19+#define QSERDES_UFS_V6_RX_MODE_RATE_0_1_B3 0x214
20+#define QSERDES_UFS_V6_RX_MODE_RATE_0_1_B6 0x220
21+#define QSERDES_UFS_V6_RX_MODE_RATE2_B3 0x238
22+#define QSERDES_UFS_V6_RX_MODE_RATE2_B6 0x244
23+#define QSERDES_UFS_V6_RX_MODE_RATE3_B3 0x25c
24+#define QSERDES_UFS_V6_RX_MODE_RATE3_B4 0x260
25+#define QSERDES_UFS_V6_RX_MODE_RATE3_B5 0x264
26+#define QSERDES_UFS_V6_RX_MODE_RATE3_B8 0x270
27+#define QSERDES_UFS_V6_RX_MODE_RATE4_B3 0x280
28+#define QSERDES_UFS_V6_RX_MODE_RATE4_B6 0x28c
29+
30+#endif
drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-v5_5nm.h+0−5
@@ -7,11 +7,6 @@ · 6 unmodified lines
77 #define QCOM_PHY_QMP_QSERDES_TXRX_V5_5NM_H_
88
99 /* Only for QMP V5 5NM PHY - TX registers */
10−#define QSERDES_V5_5NM_TX_RES_CODE_LANE_OFFSET_TX 0x30
11−#define QSERDES_V5_5NM_TX_RES_CODE_LANE_OFFSET_RX 0x34
12−#define QSERDES_V5_5NM_TX_LANE_MODE_1 0x78
13−#define QSERDES_V5_5NM_TX_LANE_MODE_2 0x7c
14−#define QSERDES_V5_5NM_TX_LANE_MODE_3 0x80
1510 #define QSERDES_V5_5NM_TX_BIST_MODE_LANENO 0x00
1611 #define QSERDES_V5_5NM_TX_BIST_INVERT 0x04
1712 #define QSERDES_V5_5NM_TX_CLKBUF_ENABLE 0x08
drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-v6.h+77−0
@@ -0,0 +1,77 @@
1+/* SPDX-License-Identifier: GPL-2.0 */
2+/*
3+ * Copyright (c) 2023, Linaro Limited
4+ */
5+
6+#ifndef QCOM_PHY_QMP_QSERDES_TXRX_USB_V6_H_
7+#define QCOM_PHY_QMP_QSERDES_TXRX_USB_V6_H_
8+
9+#define QSERDES_V6_TX_CLKBUF_ENABLE 0x08
10+#define QSERDES_V6_TX_RESET_TSYNC_EN 0x1c
11+#define QSERDES_V6_TX_PRE_STALL_LDO_BOOST_EN 0x20
12+#define QSERDES_V6_TX_TX_BAND 0x24
13+#define QSERDES_V6_TX_INTERFACE_SELECT 0x2c
14+#define QSERDES_V6_TX_RES_CODE_LANE_TX 0x34
15+#define QSERDES_V6_TX_RES_CODE_LANE_RX 0x38
16+#define QSERDES_V6_TX_RES_CODE_LANE_OFFSET_TX 0x3c
17+#define QSERDES_V6_TX_RES_CODE_LANE_OFFSET_RX 0x40
18+#define QSERDES_V6_TX_PARRATE_REC_DETECT_IDLE_EN 0x60
19+#define QSERDES_V6_TX_BIST_PATTERN7 0x7c
20+#define QSERDES_V6_TX_LANE_MODE_1 0x84
21+#define QSERDES_V6_TX_LANE_MODE_3 0x8c
22+#define QSERDES_V6_TX_LANE_MODE_4 0x90
23+#define QSERDES_V6_TX_LANE_MODE_5 0x94
24+#define QSERDES_V6_TX_RCV_DETECT_LVL_2 0xa4
25+#define QSERDES_V6_TX_TRAN_DRVR_EMP_EN 0xc0
26+#define QSERDES_V6_TX_TX_INTERFACE_MODE 0xc4
27+#define QSERDES_V6_TX_VMODE_CTRL1 0xc8
28+#define QSERDES_V6_TX_PI_QEC_CTRL 0xe4
29+
30+#define QSERDES_V6_RX_UCDR_FO_GAIN 0x08
31+#define QSERDES_V6_RX_UCDR_SO_GAIN 0x14
32+#define QSERDES_V6_RX_UCDR_FASTLOCK_FO_GAIN 0x30
33+#define QSERDES_V6_RX_UCDR_SO_SATURATION_AND_ENABLE 0x34
34+#define QSERDES_V6_RX_UCDR_FASTLOCK_COUNT_LOW 0x3c
35+#define QSERDES_V6_RX_UCDR_FASTLOCK_COUNT_HIGH 0x40
36+#define QSERDES_V6_RX_UCDR_PI_CONTROLS 0x44
37+#define QSERDES_V6_RX_UCDR_SB2_THRESH1 0x4c
38+#define QSERDES_V6_RX_UCDR_SB2_THRESH2 0x50
39+#define QSERDES_V6_RX_UCDR_SB2_GAIN1 0x54
40+#define QSERDES_V6_RX_UCDR_SB2_GAIN2 0x58
41+#define QSERDES_V6_RX_AUX_DATA_TCOARSE_TFINE 0x60
42+#define QSERDES_V6_RX_TX_ADAPT_POST_THRESH 0xcc
43+#define QSERDES_V6_RX_VGA_CAL_CNTRL1 0xd4
44+#define QSERDES_V6_RX_VGA_CAL_CNTRL2 0xd8
45+#define QSERDES_V6_RX_GM_CAL 0xdc
46+#define QSERDES_V6_RX_RX_EQU_ADAPTOR_CNTRL2 0xec
47+#define QSERDES_V6_RX_RX_EQU_ADAPTOR_CNTRL3 0xf0
48+#define QSERDES_V6_RX_RX_EQU_ADAPTOR_CNTRL4 0xf4
49+#define QSERDES_V6_RX_RX_IDAC_TSETTLE_LOW 0xf8
50+#define QSERDES_V6_RX_RX_IDAC_TSETTLE_HIGH 0xfc
51+#define QSERDES_V6_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x110
52+#define QSERDES_V6_RX_SIDGET_ENABLES 0x118
53+#define QSERDES_V6_RX_SIGDET_CNTRL 0x11c
54+#define QSERDES_V6_RX_SIGDET_DEGLITCH_CNTRL 0x124
55+#define QSERDES_V6_RX_RX_MODE_00_LOW 0x15c
56+#define QSERDES_V6_RX_RX_MODE_00_HIGH 0x160
57+#define QSERDES_V6_RX_RX_MODE_00_HIGH2 0x164
58+#define QSERDES_V6_RX_RX_MODE_00_HIGH3 0x168
59+#define QSERDES_V6_RX_RX_MODE_00_HIGH4 0x16c
60+#define QSERDES_V6_RX_RX_MODE_01_LOW 0x170
61+#define QSERDES_V6_RX_RX_MODE_01_HIGH 0x174
62+#define QSERDES_V6_RX_RX_MODE_01_HIGH2 0x178
63+#define QSERDES_V6_RX_RX_MODE_01_HIGH3 0x17c
64+#define QSERDES_V6_RX_RX_MODE_01_HIGH4 0x180
65+#define QSERDES_V6_RX_RX_MODE_10_LOW 0x184
66+#define QSERDES_V6_RX_RX_MODE_10_HIGH 0x188
67+#define QSERDES_V6_RX_RX_MODE_10_HIGH2 0x18c
68+#define QSERDES_V6_RX_RX_MODE_10_HIGH3 0x190
69+#define QSERDES_V6_RX_RX_MODE_10_HIGH4 0x194
70+#define QSERDES_V6_RX_DFE_EN_TIMER 0x1a0
71+#define QSERDES_V6_RX_DFE_CTLE_POST_CAL_OFFSET 0x1a4
72+#define QSERDES_V6_RX_DCC_CTRL1 0x1a8
73+#define QSERDES_V6_RX_VTH_CODE 0x1b0
74+#define QSERDES_V6_RX_SIGDET_CAL_CTRL1 0x1e4
75+#define QSERDES_V6_RX_SIGDET_CAL_TRIM 0x1f8
76+
77+#endif
drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-v6_20.h+45−0
@@ -0,0 +1,45 @@
1+/* SPDX-License-Identifier: GPL-2.0 */
2+/*
3+ * Copyright (c) 2023, Linaro Limited
4+ */
5+
6+#ifndef QCOM_PHY_QMP_QSERDES_TXRX_PCIE_V6_20_H_
7+#define QCOM_PHY_QMP_QSERDES_TXRX_PCIE_V6_20_H_
8+
9+#define QSERDES_V6_20_TX_RES_CODE_LANE_OFFSET_TX 0x30
10+#define QSERDES_V6_20_TX_RES_CODE_LANE_OFFSET_RX 0x34
11+#define QSERDES_V6_20_TX_TRAN_DRVR_EMP_EN 0xac
12+#define QSERDES_V6_20_TX_LANE_MODE_1 0x78
13+#define QSERDES_V6_20_TX_LANE_MODE_2 0x7c
14+#define QSERDES_V6_20_TX_LANE_MODE_3 0x80
15+
16+#define QSERDES_V6_20_RX_UCDR_FO_GAIN_RATE_2 0x08
17+#define QSERDES_V6_20_RX_UCDR_FO_GAIN_RATE_3 0x0c
18+#define QSERDES_V6_20_RX_UCDR_PI_CONTROLS 0x20
19+#define QSERDES_V6_20_RX_UCDR_SO_ACC_DEFAULT_VAL_RATE3 0x34
20+#define QSERDES_V6_20_RX_IVCM_CAL_CTRL2 0x9c
21+#define QSERDES_V6_20_RX_IVCM_POSTCAL_OFFSET 0xa0
22+#define QSERDES_V6_20_RX_DFE_3 0xb4
23+#define QSERDES_V6_20_RX_VGA_CAL_MAN_VAL 0xe8
24+#define QSERDES_V6_20_RX_GM_CAL 0x10c
25+#define QSERDES_V6_20_RX_EQU_ADAPTOR_CNTRL4 0x120
26+#define QSERDES_V6_20_RX_SIGDET_ENABLES 0x148
27+#define QSERDES_V6_20_RX_PHPRE_CTRL 0x188
28+#define QSERDES_V6_20_RX_DFE_CTLE_POST_CAL_OFFSET 0x194
29+#define QSERDES_V6_20_RX_Q_PI_INTRINSIC_BIAS_RATE32 0x1dc
30+#define QSERDES_V6_20_RX_MODE_RATE2_B0 0x1f4
31+#define QSERDES_V6_20_RX_MODE_RATE2_B1 0x1f8
32+#define QSERDES_V6_20_RX_MODE_RATE2_B2 0x1fc
33+#define QSERDES_V6_20_RX_MODE_RATE2_B3 0x200
34+#define QSERDES_V6_20_RX_MODE_RATE2_B4 0x204
35+#define QSERDES_V6_20_RX_MODE_RATE2_B5 0x208
36+#define QSERDES_V6_20_RX_MODE_RATE2_B6 0x20c
37+#define QSERDES_V6_20_RX_MODE_RATE3_B0 0x210
38+#define QSERDES_V6_20_RX_MODE_RATE3_B1 0x214
39+#define QSERDES_V6_20_RX_MODE_RATE3_B2 0x218
40+#define QSERDES_V6_20_RX_MODE_RATE3_B3 0x21c
41+#define QSERDES_V6_20_RX_MODE_RATE3_B4 0x220
42+#define QSERDES_V6_20_RX_MODE_RATE3_B5 0x224
43+#define QSERDES_V6_20_RX_MODE_RATE3_B6 0x228
44+
45+#endif
drivers/phy/qualcomm/phy-qcom-qmp-ufs.c+538−150
@@ -20,7 +20,15 @@ · 19 unmodified lines
2020 #include <linux/reset.h>
2121 #include <linux/slab.h>
2222
23+#include <ufs/unipro.h>
2324 #include "phy-qcom-qmp.h"
25+#include "phy-qcom-qmp-pcs-ufs-v2.h"
26+#include "phy-qcom-qmp-pcs-ufs-v3.h"
27+#include "phy-qcom-qmp-pcs-ufs-v4.h"
28+#include "phy-qcom-qmp-pcs-ufs-v5.h"
29+#include "phy-qcom-qmp-pcs-ufs-v6.h"
30+
31+#include "phy-qcom-qmp-qserdes-txrx-ufs-v6.h"
2432
2533 /* QPHY_SW_RESET bit */
2634 #define SW_RESET BIT(0)
@@ -69,32 +77,40 @@ enum qphy_reg_layout { · 42 unmodified lines
6977 QPHY_LAYOUT_SIZE
7078 };
7179
72−static const unsigned int msm8996_ufsphy_regs_layout[QPHY_LAYOUT_SIZE] = {
73− [QPHY_START_CTRL] = 0x00,
74− [QPHY_PCS_READY_STATUS] = 0x168,
75− [QPHY_PCS_POWER_DOWN_CONTROL] = 0x04,
76−};
77−
78−static const unsigned int sdm845_ufsphy_regs_layout[QPHY_LAYOUT_SIZE] = {
79− [QPHY_START_CTRL] = 0x00,
80− [QPHY_PCS_READY_STATUS] = 0x160,
81− [QPHY_PCS_POWER_DOWN_CONTROL] = 0x04,
80+static const unsigned int ufsphy_v2_regs_layout[QPHY_LAYOUT_SIZE] = {
81+ [QPHY_START_CTRL] = QPHY_V2_PCS_UFS_PHY_START,
82+ [QPHY_PCS_READY_STATUS] = QPHY_V2_PCS_UFS_READY_STATUS,
83+ [QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V2_PCS_UFS_POWER_DOWN_CONTROL,
8284 };
8385
84−static const unsigned int sm6115_ufsphy_regs_layout[QPHY_LAYOUT_SIZE] = {
85− [QPHY_START_CTRL] = 0x00,
86− [QPHY_PCS_READY_STATUS] = 0x168,
87− [QPHY_PCS_POWER_DOWN_CONTROL] = 0x04,
86+static const unsigned int ufsphy_v3_regs_layout[QPHY_LAYOUT_SIZE] = {
87+ [QPHY_START_CTRL] = QPHY_V3_PCS_UFS_PHY_START,
88+ [QPHY_PCS_READY_STATUS] = QPHY_V3_PCS_UFS_READY_STATUS,
89+ [QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V3_PCS_UFS_POWER_DOWN_CONTROL,
8890 };
8991
90−static const unsigned int sm8150_ufsphy_regs_layout[QPHY_LAYOUT_SIZE] = {
92+static const unsigned int ufsphy_v4_regs_layout[QPHY_LAYOUT_SIZE] = {
9193 [QPHY_START_CTRL] = QPHY_V4_PCS_UFS_PHY_START,
9294 [QPHY_PCS_READY_STATUS] = QPHY_V4_PCS_UFS_READY_STATUS,
9395 [QPHY_SW_RESET] = QPHY_V4_PCS_UFS_SW_RESET,
9496 [QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V4_PCS_UFS_POWER_DOWN_CONTROL,
9597 };
9698
97−static const struct qmp_phy_init_tbl msm8996_ufs_serdes_tbl[] = {
99+static const unsigned int ufsphy_v5_regs_layout[QPHY_LAYOUT_SIZE] = {
100+ [QPHY_START_CTRL] = QPHY_V5_PCS_UFS_PHY_START,
101+ [QPHY_PCS_READY_STATUS] = QPHY_V5_PCS_UFS_READY_STATUS,
102+ [QPHY_SW_RESET] = QPHY_V5_PCS_UFS_SW_RESET,
103+ [QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V5_PCS_UFS_POWER_DOWN_CONTROL,
104+};
105+
106+static const unsigned int ufsphy_v6_regs_layout[QPHY_LAYOUT_SIZE] = {
107+ [QPHY_START_CTRL] = QPHY_V6_PCS_UFS_PHY_START,
108+ [QPHY_PCS_READY_STATUS] = QPHY_V6_PCS_UFS_READY_STATUS,
109+ [QPHY_SW_RESET] = QPHY_V6_PCS_UFS_SW_RESET,
110+ [QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V6_PCS_UFS_POWER_DOWN_CONTROL,
111+};
112+
113+static const struct qmp_phy_init_tbl msm8996_ufsphy_serdes[] = {
98114 QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x0e),
99115 QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0xd7),
100116 QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30),
@@ -143,12 +159,12 @@ static const struct qmp_phy_init_tbl msm8996_ufs_serdes_tbl[] = { · 42 unmodified lines
143159 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE1, 0x00),
144160 };
145161
146−static const struct qmp_phy_init_tbl msm8996_ufs_tx_tbl[] = {
162+static const struct qmp_phy_init_tbl msm8996_ufsphy_tx[] = {
147163 QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45),
148164 QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x02),
149165 };
150166
151−static const struct qmp_phy_init_tbl msm8996_ufs_rx_tbl[] = {
167+static const struct qmp_phy_init_tbl msm8996_ufsphy_rx[] = {
152168 QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_LVL, 0x24),
153169 QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_CNTRL, 0x02),
154170 QMP_PHY_INIT_CFG(QSERDES_RX_RX_INTERFACE_MODE, 0x00),
@@ -162,7 +178,7 @@ static const struct qmp_phy_init_tbl msm8996_ufs_rx_tbl[] = { · 7 unmodified lines
162178 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0E),
163179 };
164180
165−static const struct qmp_phy_init_tbl sm6115_ufsphy_serdes_tbl[] = {
181+static const struct qmp_phy_init_tbl sm6115_ufsphy_serdes[] = {
166182 QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x0e),
167183 QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x14),
168184 QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30),
@@ -213,17 +229,18 @@ static const struct qmp_phy_init_tbl sm6115_ufsphy_serdes_tbl[] = { · 44 unmodified lines
213229 QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f),
214230 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_INITVAL1, 0xff),
215231 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_INITVAL2, 0x00),
232+};
216233
217− /* Rate B */
234+static const struct qmp_phy_init_tbl sm6115_ufsphy_hs_b_serdes[] = {
218235 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x44),
219236 };
220237
221−static const struct qmp_phy_init_tbl sm6115_ufsphy_tx_tbl[] = {
238+static const struct qmp_phy_init_tbl sm6115_ufsphy_tx[] = {
222239 QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45),
223240 QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x06),
224241 };
225242
226−static const struct qmp_phy_init_tbl sm6115_ufsphy_rx_tbl[] = {
243+static const struct qmp_phy_init_tbl sm6115_ufsphy_rx[] = {
227244 QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_LVL, 0x24),
228245 QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_CNTRL, 0x0F),
229246 QMP_PHY_INIT_CFG(QSERDES_RX_RX_INTERFACE_MODE, 0x40),
@@ -241,19 +258,19 @@ static const struct qmp_phy_init_tbl sm6115_ufsphy_rx_tbl[] = { · 11 unmodified lines
241258 QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x5B),
242259 };
243260
244−static const struct qmp_phy_init_tbl sm6115_ufsphy_pcs_tbl[] = {
245− QMP_PHY_INIT_CFG(QPHY_V2_PCS_RX_PWM_GEAR_BAND, 0x15),
246− QMP_PHY_INIT_CFG(QPHY_V2_PCS_RX_SIGDET_CTRL2, 0x6d),
247− QMP_PHY_INIT_CFG(QPHY_V2_PCS_TX_LARGE_AMP_DRV_LVL, 0x0f),
248− QMP_PHY_INIT_CFG(QPHY_V2_PCS_TX_SMALL_AMP_DRV_LVL, 0x02),
249− QMP_PHY_INIT_CFG(QPHY_V2_PCS_RX_MIN_STALL_NOCONFIG_TIME_CAP, 0x28),
250− QMP_PHY_INIT_CFG(QPHY_V2_PCS_RX_SYM_RESYNC_CTRL, 0x03),
251− QMP_PHY_INIT_CFG(QPHY_V2_PCS_TX_LARGE_AMP_POST_EMP_LVL, 0x12),
252− QMP_PHY_INIT_CFG(QPHY_V2_PCS_TX_SMALL_AMP_POST_EMP_LVL, 0x0f),
253− QMP_PHY_INIT_CFG(QPHY_V2_PCS_RX_MIN_HIBERN8_TIME, 0x9a), /* 8 us */
261+static const struct qmp_phy_init_tbl sm6115_ufsphy_pcs[] = {
262+ QMP_PHY_INIT_CFG(QPHY_V2_PCS_UFS_RX_PWM_GEAR_BAND, 0x15),
263+ QMP_PHY_INIT_CFG(QPHY_V2_PCS_UFS_RX_SIGDET_CTRL2, 0x6d),
264+ QMP_PHY_INIT_CFG(QPHY_V2_PCS_UFS_TX_LARGE_AMP_DRV_LVL, 0x0f),
265+ QMP_PHY_INIT_CFG(QPHY_V2_PCS_UFS_TX_SMALL_AMP_DRV_LVL, 0x02),
266+ QMP_PHY_INIT_CFG(QPHY_V2_PCS_UFS_RX_MIN_STALL_NOCONFIG_TIME_CAP, 0x28),
267+ QMP_PHY_INIT_CFG(QPHY_V2_PCS_UFS_RX_SYM_RESYNC_CTRL, 0x03),
268+ QMP_PHY_INIT_CFG(QPHY_V2_PCS_UFS_TX_LARGE_AMP_POST_EMP_LVL, 0x12),
269+ QMP_PHY_INIT_CFG(QPHY_V2_PCS_UFS_TX_SMALL_AMP_POST_EMP_LVL, 0x0f),
270+ QMP_PHY_INIT_CFG(QPHY_V2_PCS_UFS_RX_MIN_HIBERN8_TIME, 0x9a), /* 8 us */
254271 };
255272
256−static const struct qmp_phy_init_tbl sdm845_ufsphy_serdes_tbl[] = {
273+static const struct qmp_phy_init_tbl sdm845_ufsphy_serdes[] = {
257274 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02),
258275 QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x04),
259276 QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x0a),
@@ -290,18 +307,19 @@ static const struct qmp_phy_init_tbl sdm845_ufsphy_serdes_tbl[] = { · 30 unmodified lines
290307 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE1, 0x00),
291308 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE1, 0x32),
292309 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE1, 0x0f),
310+};
293311
294− /* Rate B */
312+static const struct qmp_phy_init_tbl sdm845_ufsphy_hs_b_serdes[] = {
295313 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x44),
296314 };
297315
298−static const struct qmp_phy_init_tbl sdm845_ufsphy_tx_tbl[] = {
316+static const struct qmp_phy_init_tbl sdm845_ufsphy_tx[] = {
299317 QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x06),
300318 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x04),
301319 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x07),
302320 };
303321
304−static const struct qmp_phy_init_tbl sdm845_ufsphy_rx_tbl[] = {
322+static const struct qmp_phy_init_tbl sdm845_ufsphy_rx[] = {
305323 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_LVL, 0x24),
306324 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x0f),
307325 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x1e),
@@ -320,7 +338,7 @@ static const struct qmp_phy_init_tbl sdm845_ufsphy_rx_tbl[] = { · 12 unmodified lines
320338 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x59),
321339 };
322340
323−static const struct qmp_phy_init_tbl sdm845_ufsphy_pcs_tbl[] = {
341+static const struct qmp_phy_init_tbl sdm845_ufsphy_pcs[] = {
324342 QMP_PHY_INIT_CFG(QPHY_V3_PCS_UFS_RX_SIGDET_CTRL2, 0x6e),
325343 QMP_PHY_INIT_CFG(QPHY_V3_PCS_UFS_TX_LARGE_AMP_DRV_LVL, 0x0a),
326344 QMP_PHY_INIT_CFG(QPHY_V3_PCS_UFS_TX_SMALL_AMP_DRV_LVL, 0x02),
@@ -331,7 +349,7 @@ static const struct qmp_phy_init_tbl sdm845_ufsphy_pcs_tbl[] = { · 4 unmodified lines
331349 QMP_PHY_INIT_CFG(QPHY_V3_PCS_UFS_MULTI_LANE_CTRL1, 0x02),
332350 };
333351
334−static const struct qmp_phy_init_tbl sm8150_ufsphy_serdes_tbl[] = {
352+static const struct qmp_phy_init_tbl sm8150_ufsphy_serdes[] = {
335353 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0xd9),
336354 QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x11),
337355 QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_HS_SWITCH_SEL, 0x00),
@@ -356,12 +374,13 @@ static const struct qmp_phy_init_tbl sm8150_ufsphy_serdes_tbl[] = { · 18 unmodified lines
356374 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x0f),
357375 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xdd),
358376 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x23),
377+};
359378
360− /* Rate B */
379+static const struct qmp_phy_init_tbl sm8150_ufsphy_hs_b_serdes[] = {
361380 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x06),
362381 };
363382
364−static const struct qmp_phy_init_tbl sm8150_ufsphy_tx_tbl[] = {
383+static const struct qmp_phy_init_tbl sm8150_ufsphy_tx[] = {
365384 QMP_PHY_INIT_CFG(QSERDES_V4_TX_PWM_GEAR_1_DIVIDER_BAND0_1, 0x06),
366385 QMP_PHY_INIT_CFG(QSERDES_V4_TX_PWM_GEAR_2_DIVIDER_BAND0_1, 0x03),
367386 QMP_PHY_INIT_CFG(QSERDES_V4_TX_PWM_GEAR_3_DIVIDER_BAND0_1, 0x01),
@@ -370,7 +389,11 @@ static const struct qmp_phy_init_tbl sm8150_ufsphy_tx_tbl[] = { · 2 unmodified lines
370389 QMP_PHY_INIT_CFG(QSERDES_V4_TX_TRAN_DRVR_EMP_EN, 0x0c),
371390 };
372391
373−static const struct qmp_phy_init_tbl sm8150_ufsphy_rx_tbl[] = {
392+static const struct qmp_phy_init_tbl sm8150_ufsphy_hs_g4_tx[] = {
393+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0x75),
394+};
395+
396+static const struct qmp_phy_init_tbl sm8150_ufsphy_rx[] = {
374397 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_LVL, 0x24),
375398 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x0f),
376399 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x1e),
@@ -405,10 +428,28 @@ static const struct qmp_phy_init_tbl sm8150_ufsphy_rx_tbl[] = { · 28 unmodified lines
405428 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH2, 0xc8),
406429 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH3, 0x3b),
407430 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH4, 0xb1),
431+};
408432
433+static const struct qmp_phy_init_tbl sm8150_ufsphy_hs_g4_rx[] = {
434+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x5a),
435+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CTRL2, 0x81),
436+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0e),
437+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_TERM_BW, 0x6f),
438+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_MEASURE_TIME, 0x20),
439+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0x80),
440+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x01),
441+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x3f),
442+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0xff),
443+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xff),
444+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f),
445+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x6c),
446+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0x6d),
447+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0x6d),
448+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0xed),
449+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0x3c),
409450 };
410451
411−static const struct qmp_phy_init_tbl sm8150_ufsphy_pcs_tbl[] = {
452+static const struct qmp_phy_init_tbl sm8150_ufsphy_pcs[] = {
412453 QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_RX_SIGDET_CTRL2, 0x6d),
413454 QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TX_LARGE_AMP_DRV_LVL, 0x0a),
414455 QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TX_SMALL_AMP_DRV_LVL, 0x02),
@@ -418,7 +459,40 @@ static const struct qmp_phy_init_tbl sm8150_ufsphy_pcs_tbl[] = { · 3 unmodified lines
418459 QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_MULTI_LANE_CTRL1, 0x02),
419460 };
420461
421−static const struct qmp_phy_init_tbl sm8350_ufsphy_serdes_tbl[] = {
462+static const struct qmp_phy_init_tbl sm8150_ufsphy_hs_g4_pcs[] = {
463+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TX_LARGE_AMP_DRV_LVL, 0x10),
464+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_BIST_FIXED_PAT_CTRL, 0x0a),
465+};
466+
467+static const struct qmp_phy_init_tbl sm8250_ufsphy_hs_g4_tx[] = {
468+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0xe5),
469+};
470+
471+static const struct qmp_phy_init_tbl sm8250_ufsphy_hs_g4_rx[] = {
472+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x5a),
473+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CTRL2, 0x81),
474+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0e),
475+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_TERM_BW, 0x6f),
476+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL1, 0x04),
477+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x00),
478+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x09),
479+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x07),
480+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x17),
481+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_MEASURE_TIME, 0x20),
482+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0x80),
483+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x01),
484+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x3f),
485+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0xff),
486+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xff),
487+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f),
488+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x2c),
489+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0x6d),
490+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0x6d),
491+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0xed),
492+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0x3c),
493+};
494+
495+static const struct qmp_phy_init_tbl sm8350_ufsphy_serdes[] = {
422496 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_EN_SEL, 0xd9),
423497 QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_SEL, 0x11),
424498 QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_HS_SWITCH_SEL, 0x00),
@@ -443,12 +517,13 @@ static const struct qmp_phy_init_tbl sm8350_ufsphy_serdes_tbl[] = { · 18 unmodified lines
443517 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE1, 0x1e),
444518 QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xdd),
445519 QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x23),
520+};
446521
447− /* Rate B */
522+static const struct qmp_phy_init_tbl sm8350_ufsphy_hs_b_serdes[] = {
448523 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAP, 0x06),
449524 };
450525
451−static const struct qmp_phy_init_tbl sm8350_ufsphy_tx_tbl[] = {
526+static const struct qmp_phy_init_tbl sm8350_ufsphy_tx[] = {
452527 QMP_PHY_INIT_CFG(QSERDES_V5_TX_PWM_GEAR_1_DIVIDER_BAND0_1, 0x06),
453528 QMP_PHY_INIT_CFG(QSERDES_V5_TX_PWM_GEAR_2_DIVIDER_BAND0_1, 0x03),
454529 QMP_PHY_INIT_CFG(QSERDES_V5_TX_PWM_GEAR_3_DIVIDER_BAND0_1, 0x01),
@@ -460,7 +535,7 @@ static const struct qmp_phy_init_tbl sm8350_ufsphy_tx_tbl[] = { · 5 unmodified lines
460535 QMP_PHY_INIT_CFG(QSERDES_V5_TX_TRAN_DRVR_EMP_EN, 0x0c),
461536 };
462537
463−static const struct qmp_phy_init_tbl sm8350_ufsphy_rx_tbl[] = {
538+static const struct qmp_phy_init_tbl sm8350_ufsphy_rx[] = {
464539 QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_LVL, 0x24),
465540 QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_CNTRL, 0x0f),
466541 QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_DEGLITCH_CNTRL, 0x1e),
@@ -500,24 +575,100 @@ static const struct qmp_phy_init_tbl sm8350_ufsphy_rx_tbl[] = { · 33 unmodified lines
500575 QMP_PHY_INIT_CFG(QSERDES_V5_RX_DCC_CTRL1, 0x0c),
501576 };
502577
503−static const struct qmp_phy_init_tbl sm8350_ufsphy_pcs_tbl[] = {
578+static const struct qmp_phy_init_tbl sm8350_ufsphy_pcs[] = {
504579 QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_RX_SIGDET_CTRL2, 0x6d),
505580 QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_LARGE_AMP_DRV_LVL, 0x0a),
506581 QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_SMALL_AMP_DRV_LVL, 0x02),
507582 QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_MID_TERM_CTRL1, 0x43),
508583 QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_DEBUG_BUS_CLKSEL, 0x1f),
509584 QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_RX_MIN_HIBERN8_TIME, 0xff),
510− QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_PLL_CNTL, 0x03),
511− QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TIMER_20US_CORECLK_STEPS_MSB, 0x16),
512− QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TIMER_20US_CORECLK_STEPS_LSB, 0xd8),
513− QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_PWM_GEAR_BAND, 0xaa),
514− QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_HS_GEAR_BAND, 0x06),
515− QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_HSGEAR_CAPABILITY, 0x03),
516− QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_RX_HSGEAR_CAPABILITY, 0x03),
517585 QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_RX_SIGDET_CTRL1, 0x0e),
518586 QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_MULTI_LANE_CTRL1, 0x02),
519587 };
520588
589+static const struct qmp_phy_init_tbl sm8350_ufsphy_g4_tx[] = {
590+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0xe5),
591+};
592+
593+static const struct qmp_phy_init_tbl sm8350_ufsphy_g4_rx[] = {
594+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CTRL2, 0x81),
595+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_TERM_BW, 0x6f),
596+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL2, 0x00),
597+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
598+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
599+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_MEASURE_TIME, 0x20),
600+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_TSETTLE_LOW, 0x80),
601+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_TSETTLE_HIGH, 0x01),
602+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0xbf),
603+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0xbf),
604+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0x7f),
605+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x7f),
606+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0x2d),
607+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0x6d),
608+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0x6d),
609+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0xed),
610+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0x3c),
611+};
612+
613+static const struct qmp_phy_init_tbl sm8350_ufsphy_g4_pcs[] = {
614+ QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_BIST_FIXED_PAT_CTRL, 0x0a),
615+};
616+
617+static const struct qmp_phy_init_tbl sm8550_ufsphy_serdes[] = {
618+ QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYSCLK_EN_SEL, 0xd9),
619+ QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_CONFIG_1, 0x16),
620+ QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_SEL_1, 0x11),
621+ QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_HS_SWITCH_SEL_1, 0x00),
622+ QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_EN, 0x01),
623+ QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAP, 0x04),
624+ QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_IVCO, 0x0f),
625+ QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_INITVAL2, 0x00),
626+ QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x41),
627+ QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE0, 0x0a),
628+ QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE0, 0x18),
629+ QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE0, 0x14),
630+ QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x7f),
631+ QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x06),
632+ QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x4c),
633+ QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE0, 0x0a),
634+ QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE0, 0x18),
635+ QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE0, 0x14),
636+ QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x99),
637+ QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x07),
638+};
639+
640+static const struct qmp_phy_init_tbl sm8550_ufsphy_tx[] = {
641+ QMP_PHY_INIT_CFG(QSERDES_V6_TX_LANE_MODE_1, 0x05),
642+ QMP_PHY_INIT_CFG(QSERDES_UFS_V6_TX_RES_CODE_LANE_OFFSET_TX, 0x07),
643+};
644+
645+static const struct qmp_phy_init_tbl sm8550_ufsphy_rx[] = {
646+ QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_FASTLOCK_FO_GAIN_RATE2, 0x0c),
647+ QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_FASTLOCK_FO_GAIN_RATE4, 0x0f),
648+ QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_VGA_CAL_MAN_VAL, 0x0e),
649+
650+ QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE_0_1_B0, 0xc2),
651+ QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE_0_1_B1, 0xc2),
652+ QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE_0_1_B3, 0x1a),
653+ QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE_0_1_B6, 0x60),
654+
655+ QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE2_B3, 0x9e),
656+ QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE2_B6, 0x60),
657+
658+ QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE3_B3, 0x9e),
659+ QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE3_B4, 0x0e),
660+ QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE3_B5, 0x36),
661+ QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE3_B8, 0x02),
662+};
663+
664+static const struct qmp_phy_init_tbl sm8550_ufsphy_pcs[] = {
665+ QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_RX_SIGDET_CTRL2, 0x69),
666+ QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_TX_LARGE_AMP_DRV_LVL, 0x0f),
667+ QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_TX_MID_TERM_CTRL1, 0x43),
668+ QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_PLL_CNTL, 0x2b),
669+ QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_MULTI_LANE_CTRL1, 0x02),
670+};
671+
521672 struct qmp_ufs_offsets {
522673 u16 serdes;
523674 u16 pcs;
@@ -527,21 +678,30 @@ struct qmp_ufs_offsets { · 3 unmodified lines
527678 u16 rx2;
528679 };
529680
681+struct qmp_phy_cfg_tbls {
682+ /* Init sequence for PHY blocks - serdes, tx, rx, pcs */
683+ const struct qmp_phy_init_tbl *serdes;
684+ int serdes_num;
685+ const struct qmp_phy_init_tbl *tx;
686+ int tx_num;
687+ const struct qmp_phy_init_tbl *rx;
688+ int rx_num;
689+ const struct qmp_phy_init_tbl *pcs;
690+ int pcs_num;
691+};
692+
530693 /* struct qmp_phy_cfg - per-PHY initialization config */
531694 struct qmp_phy_cfg {
532695 int lanes;
533696
534697 const struct qmp_ufs_offsets *offsets;
535698
536− /* Init sequence for PHY blocks - serdes, tx, rx, pcs */
537− const struct qmp_phy_init_tbl *serdes_tbl;
538− int serdes_tbl_num;
539− const struct qmp_phy_init_tbl *tx_tbl;
540− int tx_tbl_num;
541− const struct qmp_phy_init_tbl *rx_tbl;
542− int rx_tbl_num;
543− const struct qmp_phy_init_tbl *pcs_tbl;
544− int pcs_tbl_num;
699+ /* Main init sequence for PHY blocks - serdes, tx, rx, pcs */
700+ const struct qmp_phy_cfg_tbls tbls;
701+ /* Additional sequence for HS Series B */
702+ const struct qmp_phy_cfg_tbls tbls_hs_b;
703+ /* Additional sequence for HS G4 */
704+ const struct qmp_phy_cfg_tbls tbls_hs_g4;
545705
546706 /* clock ids to be requested */
547707 const char * const *clk_list;
@@ -575,6 +735,8 @@ struct qmp_ufs { · 27 unmodified lines
575735 struct reset_control *ufs_reset;
576736
577737 struct phy *phy;
738+ u32 mode;
739+ u32 submode;
578740 };
579741
580742 static inline void qphy_setbits(void __iomem *base, u32 offset, u32 val)
@@ -620,7 +782,7 @@ static const char * const qmp_phy_vreg_l[] = { · 39 unmodified lines
620782 "vdda-phy", "vdda-pll",
621783 };
622784
623−static const struct qmp_ufs_offsets qmp_ufs_offsets_v5 = {
785+static const struct qmp_ufs_offsets qmp_ufs_offsets = {
624786 .serdes = 0,
625787 .pcs = 0xc00,
626788 .tx = 0x400,
@@ -629,15 +791,26 @@ static const struct qmp_ufs_offsets qmp_ufs_offsets_v5 = { · 2 unmodified lines
629791 .rx2 = 0xa00,
630792 };
631793
632−static const struct qmp_phy_cfg msm8996_ufs_cfg = {
794+static const struct qmp_ufs_offsets qmp_ufs_offsets_v6 = {
795+ .serdes = 0,
796+ .pcs = 0x0400,
797+ .tx = 0x1000,
798+ .rx = 0x1200,
799+ .tx2 = 0x1800,
800+ .rx2 = 0x1a00,
801+};
802+
803+static const struct qmp_phy_cfg msm8996_ufsphy_cfg = {
633804 .lanes = 1,
634805
635− .serdes_tbl = msm8996_ufs_serdes_tbl,
636− .serdes_tbl_num = ARRAY_SIZE(msm8996_ufs_serdes_tbl),
637− .tx_tbl = msm8996_ufs_tx_tbl,
638− .tx_tbl_num = ARRAY_SIZE(msm8996_ufs_tx_tbl),
639− .rx_tbl = msm8996_ufs_rx_tbl,
640− .rx_tbl_num = ARRAY_SIZE(msm8996_ufs_rx_tbl),
806+ .tbls = {
807+ .serdes = msm8996_ufsphy_serdes,
808+ .serdes_num = ARRAY_SIZE(msm8996_ufsphy_serdes),
809+ .tx = msm8996_ufsphy_tx,
810+ .tx_num = ARRAY_SIZE(msm8996_ufsphy_tx),
811+ .rx = msm8996_ufsphy_rx,
812+ .rx_num = ARRAY_SIZE(msm8996_ufsphy_rx),
813+ },
641814
642815 .clk_list = msm8996_ufs_phy_clk_l,
643816 .num_clks = ARRAY_SIZE(msm8996_ufs_phy_clk_l),
@@ -645,7 +818,7 @@ static const struct qmp_phy_cfg msm8996_ufs_cfg = { · 1 unmodified line
645818 .vreg_list = qmp_phy_vreg_l,
646819 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
647820
648− .regs = msm8996_ufsphy_regs_layout,
821+ .regs = ufsphy_v2_regs_layout,
649822
650823 .no_pcs_sw_reset = true,
651824 };
@@ -653,39 +826,59 @@ static const struct qmp_phy_cfg msm8996_ufs_cfg = { · 1 unmodified line
653826 static const struct qmp_phy_cfg sc8280xp_ufsphy_cfg = {
654827 .lanes = 2,
655828
656− .offsets = &qmp_ufs_offsets_v5,
657−
658− .serdes_tbl = sm8350_ufsphy_serdes_tbl,
659− .serdes_tbl_num = ARRAY_SIZE(sm8350_ufsphy_serdes_tbl),
660− .tx_tbl = sm8350_ufsphy_tx_tbl,
661− .tx_tbl_num = ARRAY_SIZE(sm8350_ufsphy_tx_tbl),
662− .rx_tbl = sm8350_ufsphy_rx_tbl,
663− .rx_tbl_num = ARRAY_SIZE(sm8350_ufsphy_rx_tbl),
664− .pcs_tbl = sm8350_ufsphy_pcs_tbl,
665− .pcs_tbl_num = ARRAY_SIZE(sm8350_ufsphy_pcs_tbl),
829+ .offsets = &qmp_ufs_offsets,
830+
831+ .tbls = {
832+ .serdes = sm8350_ufsphy_serdes,
833+ .serdes_num = ARRAY_SIZE(sm8350_ufsphy_serdes),
834+ .tx = sm8350_ufsphy_tx,
835+ .tx_num = ARRAY_SIZE(sm8350_ufsphy_tx),
836+ .rx = sm8350_ufsphy_rx,
837+ .rx_num = ARRAY_SIZE(sm8350_ufsphy_rx),
838+ .pcs = sm8350_ufsphy_pcs,
839+ .pcs_num = ARRAY_SIZE(sm8350_ufsphy_pcs),
840+ },
841+ .tbls_hs_b = {
842+ .serdes = sm8350_ufsphy_hs_b_serdes,
843+ .serdes_num = ARRAY_SIZE(sm8350_ufsphy_hs_b_serdes),
844+ },
845+ .tbls_hs_g4 = {
846+ .tx = sm8350_ufsphy_g4_tx,
847+ .tx_num = ARRAY_SIZE(sm8350_ufsphy_g4_tx),
848+ .rx = sm8350_ufsphy_g4_rx,
849+ .rx_num = ARRAY_SIZE(sm8350_ufsphy_g4_rx),
850+ .pcs = sm8350_ufsphy_g4_pcs,
851+ .pcs_num = ARRAY_SIZE(sm8350_ufsphy_g4_pcs),
852+ },
666853 .clk_list = sdm845_ufs_phy_clk_l,
667854 .num_clks = ARRAY_SIZE(sdm845_ufs_phy_clk_l),
668855 .vreg_list = qmp_phy_vreg_l,
669856 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
670− .regs = sm8150_ufsphy_regs_layout,
857+ .regs = ufsphy_v5_regs_layout,
671858 };
672859
673860 static const struct qmp_phy_cfg sdm845_ufsphy_cfg = {
674861 .lanes = 2,
675862
676− .serdes_tbl = sdm845_ufsphy_serdes_tbl,
677− .serdes_tbl_num = ARRAY_SIZE(sdm845_ufsphy_serdes_tbl),
678− .tx_tbl = sdm845_ufsphy_tx_tbl,
679− .tx_tbl_num = ARRAY_SIZE(sdm845_ufsphy_tx_tbl),
680− .rx_tbl = sdm845_ufsphy_rx_tbl,
681− .rx_tbl_num = ARRAY_SIZE(sdm845_ufsphy_rx_tbl),
682− .pcs_tbl = sdm845_ufsphy_pcs_tbl,
683− .pcs_tbl_num = ARRAY_SIZE(sdm845_ufsphy_pcs_tbl),
863+ .tbls = {
864+ .serdes = sdm845_ufsphy_serdes,
865+ .serdes_num = ARRAY_SIZE(sdm845_ufsphy_serdes),
866+ .tx = sdm845_ufsphy_tx,
867+ .tx_num = ARRAY_SIZE(sdm845_ufsphy_tx),
868+ .rx = sdm845_ufsphy_rx,
869+ .rx_num = ARRAY_SIZE(sdm845_ufsphy_rx),
870+ .pcs = sdm845_ufsphy_pcs,
871+ .pcs_num = ARRAY_SIZE(sdm845_ufsphy_pcs),
872+ },
873+ .tbls_hs_b = {
874+ .serdes = sdm845_ufsphy_hs_b_serdes,
875+ .serdes_num = ARRAY_SIZE(sdm845_ufsphy_hs_b_serdes),
876+ },
684877 .clk_list = sdm845_ufs_phy_clk_l,
685878 .num_clks = ARRAY_SIZE(sdm845_ufs_phy_clk_l),
686879 .vreg_list = qmp_phy_vreg_l,
687880 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
688− .regs = sdm845_ufsphy_regs_layout,
881+ .regs = ufsphy_v3_regs_layout,
689882
690883 .no_pcs_sw_reset = true,
691884 };
@@ -693,19 +886,27 @@ static const struct qmp_phy_cfg sdm845_ufsphy_cfg = { · 1 unmodified line
693886 static const struct qmp_phy_cfg sm6115_ufsphy_cfg = {
694887 .lanes = 1,
695888
696− .serdes_tbl = sm6115_ufsphy_serdes_tbl,
697− .serdes_tbl_num = ARRAY_SIZE(sm6115_ufsphy_serdes_tbl),
698− .tx_tbl = sm6115_ufsphy_tx_tbl,
699− .tx_tbl_num = ARRAY_SIZE(sm6115_ufsphy_tx_tbl),
700− .rx_tbl = sm6115_ufsphy_rx_tbl,
701− .rx_tbl_num = ARRAY_SIZE(sm6115_ufsphy_rx_tbl),
702− .pcs_tbl = sm6115_ufsphy_pcs_tbl,
703− .pcs_tbl_num = ARRAY_SIZE(sm6115_ufsphy_pcs_tbl),
889+ .offsets = &qmp_ufs_offsets,
890+
891+ .tbls = {
892+ .serdes = sm6115_ufsphy_serdes,
893+ .serdes_num = ARRAY_SIZE(sm6115_ufsphy_serdes),
894+ .tx = sm6115_ufsphy_tx,
895+ .tx_num = ARRAY_SIZE(sm6115_ufsphy_tx),
896+ .rx = sm6115_ufsphy_rx,
897+ .rx_num = ARRAY_SIZE(sm6115_ufsphy_rx),
898+ .pcs = sm6115_ufsphy_pcs,
899+ .pcs_num = ARRAY_SIZE(sm6115_ufsphy_pcs),
900+ },
901+ .tbls_hs_b = {
902+ .serdes = sm6115_ufsphy_hs_b_serdes,
903+ .serdes_num = ARRAY_SIZE(sm6115_ufsphy_hs_b_serdes),
904+ },
704905 .clk_list = sdm845_ufs_phy_clk_l,
705906 .num_clks = ARRAY_SIZE(sdm845_ufs_phy_clk_l),
706907 .vreg_list = qmp_phy_vreg_l,
707908 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
708− .regs = sm6115_ufsphy_regs_layout,
909+ .regs = ufsphy_v2_regs_layout,
709910
710911 .no_pcs_sw_reset = true,
711912 };
@@ -713,55 +914,151 @@ static const struct qmp_phy_cfg sm6115_ufsphy_cfg = { · 1 unmodified line
713914 static const struct qmp_phy_cfg sm8150_ufsphy_cfg = {
714915 .lanes = 2,
715916
716− .serdes_tbl = sm8150_ufsphy_serdes_tbl,
717− .serdes_tbl_num = ARRAY_SIZE(sm8150_ufsphy_serdes_tbl),
718− .tx_tbl = sm8150_ufsphy_tx_tbl,
719− .tx_tbl_num = ARRAY_SIZE(sm8150_ufsphy_tx_tbl),
720− .rx_tbl = sm8150_ufsphy_rx_tbl,
721− .rx_tbl_num = ARRAY_SIZE(sm8150_ufsphy_rx_tbl),
722− .pcs_tbl = sm8150_ufsphy_pcs_tbl,
723− .pcs_tbl_num = ARRAY_SIZE(sm8150_ufsphy_pcs_tbl),
917+ .tbls = {
918+ .serdes = sm8150_ufsphy_serdes,
919+ .serdes_num = ARRAY_SIZE(sm8150_ufsphy_serdes),
920+ .tx = sm8150_ufsphy_tx,
921+ .tx_num = ARRAY_SIZE(sm8150_ufsphy_tx),
922+ .rx = sm8150_ufsphy_rx,
923+ .rx_num = ARRAY_SIZE(sm8150_ufsphy_rx),
924+ .pcs = sm8150_ufsphy_pcs,
925+ .pcs_num = ARRAY_SIZE(sm8150_ufsphy_pcs),
926+ },
927+ .tbls_hs_b = {
928+ .serdes = sm8150_ufsphy_hs_b_serdes,
929+ .serdes_num = ARRAY_SIZE(sm8150_ufsphy_hs_b_serdes),
930+ },
931+ .tbls_hs_g4 = {
932+ .tx = sm8150_ufsphy_hs_g4_tx,
933+ .tx_num = ARRAY_SIZE(sm8150_ufsphy_hs_g4_tx),
934+ .rx = sm8150_ufsphy_hs_g4_rx,
935+ .rx_num = ARRAY_SIZE(sm8150_ufsphy_hs_g4_rx),
936+ .pcs = sm8150_ufsphy_hs_g4_pcs,
937+ .pcs_num = ARRAY_SIZE(sm8150_ufsphy_hs_g4_pcs),
938+ },
939+ .clk_list = sdm845_ufs_phy_clk_l,
940+ .num_clks = ARRAY_SIZE(sdm845_ufs_phy_clk_l),
941+ .vreg_list = qmp_phy_vreg_l,
942+ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
943+ .regs = ufsphy_v4_regs_layout,
944+};
945+
946+static const struct qmp_phy_cfg sm8250_ufsphy_cfg = {
947+ .lanes = 2,
948+
949+ .tbls = {
950+ .serdes = sm8150_ufsphy_serdes,
951+ .serdes_num = ARRAY_SIZE(sm8150_ufsphy_serdes),
952+ .tx = sm8150_ufsphy_tx,
953+ .tx_num = ARRAY_SIZE(sm8150_ufsphy_tx),
954+ .rx = sm8150_ufsphy_rx,
955+ .rx_num = ARRAY_SIZE(sm8150_ufsphy_rx),
956+ .pcs = sm8150_ufsphy_pcs,
957+ .pcs_num = ARRAY_SIZE(sm8150_ufsphy_pcs),
958+ },
959+ .tbls_hs_b = {
960+ .serdes = sm8150_ufsphy_hs_b_serdes,
961+ .serdes_num = ARRAY_SIZE(sm8150_ufsphy_hs_b_serdes),
962+ },
963+ .tbls_hs_g4 = {
964+ .tx = sm8250_ufsphy_hs_g4_tx,
965+ .tx_num = ARRAY_SIZE(sm8250_ufsphy_hs_g4_tx),
966+ .rx = sm8250_ufsphy_hs_g4_rx,
967+ .rx_num = ARRAY_SIZE(sm8250_ufsphy_hs_g4_rx),
968+ .pcs = sm8150_ufsphy_hs_g4_pcs,
969+ .pcs_num = ARRAY_SIZE(sm8150_ufsphy_hs_g4_pcs),
970+ },
724971 .clk_list = sdm845_ufs_phy_clk_l,
725972 .num_clks = ARRAY_SIZE(sdm845_ufs_phy_clk_l),
726973 .vreg_list = qmp_phy_vreg_l,
727974 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
728− .regs = sm8150_ufsphy_regs_layout,
975+ .regs = ufsphy_v4_regs_layout,
729976 };
730977
731978 static const struct qmp_phy_cfg sm8350_ufsphy_cfg = {
732979 .lanes = 2,
733980
734− .serdes_tbl = sm8350_ufsphy_serdes_tbl,
735− .serdes_tbl_num = ARRAY_SIZE(sm8350_ufsphy_serdes_tbl),
736− .tx_tbl = sm8350_ufsphy_tx_tbl,
737− .tx_tbl_num = ARRAY_SIZE(sm8350_ufsphy_tx_tbl),
738− .rx_tbl = sm8350_ufsphy_rx_tbl,
739− .rx_tbl_num = ARRAY_SIZE(sm8350_ufsphy_rx_tbl),
740− .pcs_tbl = sm8350_ufsphy_pcs_tbl,
741− .pcs_tbl_num = ARRAY_SIZE(sm8350_ufsphy_pcs_tbl),
981+ .tbls = {
982+ .serdes = sm8350_ufsphy_serdes,
983+ .serdes_num = ARRAY_SIZE(sm8350_ufsphy_serdes),
984+ .tx = sm8350_ufsphy_tx,
985+ .tx_num = ARRAY_SIZE(sm8350_ufsphy_tx),
986+ .rx = sm8350_ufsphy_rx,
987+ .rx_num = ARRAY_SIZE(sm8350_ufsphy_rx),
988+ .pcs = sm8350_ufsphy_pcs,
989+ .pcs_num = ARRAY_SIZE(sm8350_ufsphy_pcs),
990+ },
991+ .tbls_hs_b = {
992+ .serdes = sm8350_ufsphy_hs_b_serdes,
993+ .serdes_num = ARRAY_SIZE(sm8350_ufsphy_hs_b_serdes),
994+ },
995+ .tbls_hs_g4 = {
996+ .tx = sm8350_ufsphy_g4_tx,
997+ .tx_num = ARRAY_SIZE(sm8350_ufsphy_g4_tx),
998+ .rx = sm8350_ufsphy_g4_rx,
999+ .rx_num = ARRAY_SIZE(sm8350_ufsphy_g4_rx),
1000+ .pcs = sm8350_ufsphy_g4_pcs,
1001+ .pcs_num = ARRAY_SIZE(sm8350_ufsphy_g4_pcs),
1002+ },
7421003 .clk_list = sdm845_ufs_phy_clk_l,
7431004 .num_clks = ARRAY_SIZE(sdm845_ufs_phy_clk_l),
7441005 .vreg_list = qmp_phy_vreg_l,
7451006 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
746− .regs = sm8150_ufsphy_regs_layout,
1007+ .regs = ufsphy_v5_regs_layout,
7471008 };
7481009
7491010 static const struct qmp_phy_cfg sm8450_ufsphy_cfg = {
7501011 .lanes = 2,
7511012
752− .serdes_tbl = sm8350_ufsphy_serdes_tbl,
753− .serdes_tbl_num = ARRAY_SIZE(sm8350_ufsphy_serdes_tbl),
754− .tx_tbl = sm8350_ufsphy_tx_tbl,
755− .tx_tbl_num = ARRAY_SIZE(sm8350_ufsphy_tx_tbl),
756− .rx_tbl = sm8350_ufsphy_rx_tbl,
757− .rx_tbl_num = ARRAY_SIZE(sm8350_ufsphy_rx_tbl),
758− .pcs_tbl = sm8350_ufsphy_pcs_tbl,
759− .pcs_tbl_num = ARRAY_SIZE(sm8350_ufsphy_pcs_tbl),
1013+ .tbls = {
1014+ .serdes = sm8350_ufsphy_serdes,
1015+ .serdes_num = ARRAY_SIZE(sm8350_ufsphy_serdes),
1016+ .tx = sm8350_ufsphy_tx,
1017+ .tx_num = ARRAY_SIZE(sm8350_ufsphy_tx),
1018+ .rx = sm8350_ufsphy_rx,
1019+ .rx_num = ARRAY_SIZE(sm8350_ufsphy_rx),
1020+ .pcs = sm8350_ufsphy_pcs,
1021+ .pcs_num = ARRAY_SIZE(sm8350_ufsphy_pcs),
1022+ },
1023+ .tbls_hs_b = {
1024+ .serdes = sm8350_ufsphy_hs_b_serdes,
1025+ .serdes_num = ARRAY_SIZE(sm8350_ufsphy_hs_b_serdes),
1026+ },
1027+ .tbls_hs_g4 = {
1028+ .tx = sm8350_ufsphy_g4_tx,
1029+ .tx_num = ARRAY_SIZE(sm8350_ufsphy_g4_tx),
1030+ .rx = sm8350_ufsphy_g4_rx,
1031+ .rx_num = ARRAY_SIZE(sm8350_ufsphy_g4_rx),
1032+ .pcs = sm8350_ufsphy_g4_pcs,
1033+ .pcs_num = ARRAY_SIZE(sm8350_ufsphy_g4_pcs),
1034+ },
7601035 .clk_list = sm8450_ufs_phy_clk_l,
7611036 .num_clks = ARRAY_SIZE(sm8450_ufs_phy_clk_l),
7621037 .vreg_list = qmp_phy_vreg_l,
7631038 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
764− .regs = sm8150_ufsphy_regs_layout,
1039+ .regs = ufsphy_v5_regs_layout,
1040+};
1041+
1042+static const struct qmp_phy_cfg sm8550_ufsphy_cfg = {
1043+ .lanes = 2,
1044+
1045+ .offsets = &qmp_ufs_offsets_v6,
1046+
1047+ .tbls = {
1048+ .serdes = sm8550_ufsphy_serdes,
1049+ .serdes_num = ARRAY_SIZE(sm8550_ufsphy_serdes),
1050+ .tx = sm8550_ufsphy_tx,
1051+ .tx_num = ARRAY_SIZE(sm8550_ufsphy_tx),
1052+ .rx = sm8550_ufsphy_rx,
1053+ .rx_num = ARRAY_SIZE(sm8550_ufsphy_rx),
1054+ .pcs = sm8550_ufsphy_pcs,
1055+ .pcs_num = ARRAY_SIZE(sm8550_ufsphy_pcs),
1056+ },
1057+ .clk_list = sdm845_ufs_phy_clk_l,
1058+ .num_clks = ARRAY_SIZE(sdm845_ufs_phy_clk_l),
1059+ .vreg_list = qmp_phy_vreg_l,
1060+ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
1061+ .regs = ufsphy_v6_regs_layout,
7651062 };
7661063
7671064 static void qmp_ufs_configure_lane(void __iomem *base,
@@ -790,16 +1087,46 @@ static void qmp_ufs_configure(void __iomem *base, · 22 unmodified lines
7901087 qmp_ufs_configure_lane(base, tbl, num, 0xff);
7911088 }
7921089
793−static int qmp_ufs_serdes_init(struct qmp_ufs *qmp)
1090+static void qmp_ufs_serdes_init(struct qmp_ufs *qmp, const struct qmp_phy_cfg_tbls *tbls)
7941091 {
795− const struct qmp_phy_cfg *cfg = qmp->cfg;
7961092 void __iomem *serdes = qmp->serdes;
797− const struct qmp_phy_init_tbl *serdes_tbl = cfg->serdes_tbl;
798− int serdes_tbl_num = cfg->serdes_tbl_num;
7991093
800− qmp_ufs_configure(serdes, serdes_tbl, serdes_tbl_num);
1094+ qmp_ufs_configure(serdes, tbls->serdes, tbls->serdes_num);
1095+}
8011096
802− return 0;
1097+static void qmp_ufs_lanes_init(struct qmp_ufs *qmp, const struct qmp_phy_cfg_tbls *tbls)
1098+{
1099+ const struct qmp_phy_cfg *cfg = qmp->cfg;
1100+ void __iomem *tx = qmp->tx;
1101+ void __iomem *rx = qmp->rx;
1102+
1103+ qmp_ufs_configure_lane(tx, tbls->tx, tbls->tx_num, 1);
1104+ qmp_ufs_configure_lane(rx, tbls->rx, tbls->rx_num, 1);
1105+
1106+ if (cfg->lanes >= 2) {
1107+ qmp_ufs_configure_lane(qmp->tx2, tbls->tx, tbls->tx_num, 2);
1108+ qmp_ufs_configure_lane(qmp->rx2, tbls->rx, tbls->rx_num, 2);
1109+ }
1110+}
1111+
1112+static void qmp_ufs_pcs_init(struct qmp_ufs *qmp, const struct qmp_phy_cfg_tbls *tbls)
1113+{
1114+ void __iomem *pcs = qmp->pcs;
1115+
1116+ qmp_ufs_configure(pcs, tbls->pcs, tbls->pcs_num);
1117+}
1118+
1119+static void qmp_ufs_init_registers(struct qmp_ufs *qmp, const struct qmp_phy_cfg *cfg)
1120+{
1121+ qmp_ufs_serdes_init(qmp, &cfg->tbls);
1122+ if (qmp->mode == PHY_MODE_UFS_HS_B)
1123+ qmp_ufs_serdes_init(qmp, &cfg->tbls_hs_b);
1124+ qmp_ufs_lanes_init(qmp, &cfg->tbls);
1125+ if (qmp->submode == UFS_HS_G4)
1126+ qmp_ufs_lanes_init(qmp, &cfg->tbls_hs_g4);
1127+ qmp_ufs_pcs_init(qmp, &cfg->tbls);
1128+ if (qmp->submode == UFS_HS_G4)
1129+ qmp_ufs_pcs_init(qmp, &cfg->tbls_hs_g4);
8031130 }
8041131
8051132 static int qmp_ufs_com_init(struct qmp_ufs *qmp)
@@ -886,25 +1213,12 @@ static int qmp_ufs_power_on(struct phy *phy) · 80 unmodified lines
8861213 {
8871214 struct qmp_ufs *qmp = phy_get_drvdata(phy);
8881215 const struct qmp_phy_cfg *cfg = qmp->cfg;
889− void __iomem *tx = qmp->tx;
890− void __iomem *rx = qmp->rx;
8911216 void __iomem *pcs = qmp->pcs;
8921217 void __iomem *status;
8931218 unsigned int val;
8941219 int ret;
8951220
896− qmp_ufs_serdes_init(qmp);
897−
898− /* Tx, Rx, and PCS configurations */
899− qmp_ufs_configure_lane(tx, cfg->tx_tbl, cfg->tx_tbl_num, 1);
900− qmp_ufs_configure_lane(rx, cfg->rx_tbl, cfg->rx_tbl_num, 1);
901−
902− if (cfg->lanes >= 2) {
903− qmp_ufs_configure_lane(qmp->tx2, cfg->tx_tbl, cfg->tx_tbl_num, 2);
904− qmp_ufs_configure_lane(qmp->rx2, cfg->rx_tbl, cfg->rx_tbl_num, 2);
905− }
906−
907− qmp_ufs_configure(pcs, cfg->pcs_tbl, cfg->pcs_tbl_num);
1221+ qmp_ufs_init_registers(qmp, cfg);
9081222
9091223 ret = reset_control_deassert(qmp->ufs_reset);
9101224 if (ret)
@@ -981,9 +1295,20 @@ static int qmp_ufs_disable(struct phy *phy) · 70 unmodified lines
9811295 return qmp_ufs_exit(phy);
9821296 }
9831297
1298+static int qmp_ufs_set_mode(struct phy *phy, enum phy_mode mode, int submode)
1299+{
1300+ struct qmp_ufs *qmp = phy_get_drvdata(phy);
1301+
1302+ qmp->mode = mode;
1303+ qmp->submode = submode;
1304+
1305+ return 0;
1306+}
1307+
9841308 static const struct phy_ops qcom_qmp_ufs_phy_ops = {
9851309 .power_on = qmp_ufs_enable,
9861310 .power_off = qmp_ufs_disable,
1311+ .set_mode = qmp_ufs_set_mode,
9871312 .owner = THIS_MODULE,
9881313 };
9891314
@@ -1021,6 +1346,59 @@ static int qmp_ufs_clk_init(struct qmp_ufs *qmp) · 31 unmodified lines
10211346 return devm_clk_bulk_get(dev, num, qmp->clks);
10221347 }
10231348
1349+static void qmp_ufs_clk_release_provider(void *res)
1350+{
1351+ of_clk_del_provider(res);
1352+}
1353+
1354+#define UFS_SYMBOL_CLOCKS 3
1355+
1356+static int qmp_ufs_register_clocks(struct qmp_ufs *qmp, struct device_node *np)
1357+{
1358+ struct clk_hw_onecell_data *clk_data;
1359+ struct clk_hw *hw;
1360+ char name[64];
1361+ int ret;
1362+
1363+ clk_data = devm_kzalloc(qmp->dev,
1364+ struct_size(clk_data, hws, UFS_SYMBOL_CLOCKS),
1365+ GFP_KERNEL);
1366+ if (!clk_data)
1367+ return -ENOMEM;
1368+
1369+ clk_data->num = UFS_SYMBOL_CLOCKS;
1370+
1371+ snprintf(name, sizeof(name), "%s::rx_symbol_0", dev_name(qmp->dev));
1372+ hw = devm_clk_hw_register_fixed_rate(qmp->dev, name, NULL, 0, 0);
1373+ if (IS_ERR(hw))
1374+ return PTR_ERR(hw);
1375+
1376+ clk_data->hws[0] = hw;
1377+
1378+ snprintf(name, sizeof(name), "%s::rx_symbol_1", dev_name(qmp->dev));
1379+ hw = devm_clk_hw_register_fixed_rate(qmp->dev, name, NULL, 0, 0);
1380+ if (IS_ERR(hw))
1381+ return PTR_ERR(hw);
1382+
1383+ clk_data->hws[1] = hw;
1384+
1385+ snprintf(name, sizeof(name), "%s::tx_symbol_0", dev_name(qmp->dev));
1386+ hw = devm_clk_hw_register_fixed_rate(qmp->dev, name, NULL, 0, 0);
1387+ if (IS_ERR(hw))
1388+ return PTR_ERR(hw);
1389+
1390+ clk_data->hws[2] = hw;
1391+
1392+ ret = of_clk_add_hw_provider(np, of_clk_hw_onecell_get, clk_data);
1393+ if (ret)
1394+ return ret;
1395+
1396+ /*
1397+ * Roll a devm action because the clock provider can be a child node.
1398+ */
1399+ return devm_add_action_or_reset(qmp->dev, qmp_ufs_clk_release_provider, np);
1400+}
1401+
10241402 static int qmp_ufs_parse_dt_legacy(struct qmp_ufs *qmp, struct device_node *np)
10251403 {
10261404 struct platform_device *pdev = to_platform_device(qmp->dev);
@@ -1133,6 +1511,10 @@ static int qmp_ufs_probe(struct platform_device *pdev) · 106 unmodified lines
11331511 if (ret)
11341512 goto err_node_put;
11351513
1514+ ret = qmp_ufs_register_clocks(qmp, np);
1515+ if (ret)
1516+ goto err_node_put;
1517+
11361518 qmp->phy = devm_phy_create(dev, np, &qcom_qmp_ufs_phy_ops);
11371519 if (IS_ERR(qmp->phy)) {
11381520 ret = PTR_ERR(qmp->phy);
@@ -1156,7 +1538,7 @@ err_node_put: · 17 unmodified lines
11561538 static const struct of_device_id qmp_ufs_of_match_table[] = {
11571539 {
11581540 .compatible = "qcom,msm8996-qmp-ufs-phy",
1159− .data = &msm8996_ufs_cfg,
1541+ .data = &msm8996_ufsphy_cfg,
11601542 }, {
11611543 .compatible = "qcom,msm8998-qmp-ufs-phy",
11621544 .data = &sdm845_ufsphy_cfg,
@@ -1172,6 +1554,9 @@ static const struct of_device_id qmp_ufs_of_match_table[] = { · 9 unmodified lines
11721554 }, {
11731555 .compatible = "qcom,sm6115-qmp-ufs-phy",
11741556 .data = &sm6115_ufsphy_cfg,
1557+ }, {
1558+ .compatible = "qcom,sm6125-qmp-ufs-phy",
1559+ .data = &sm6115_ufsphy_cfg,
11751560 }, {
11761561 .compatible = "qcom,sm6350-qmp-ufs-phy",
11771562 .data = &sdm845_ufsphy_cfg,
@@ -1180,13 +1565,16 @@ static const struct of_device_id qmp_ufs_of_match_table[] = { · 2 unmodified lines
11801565 .data = &sm8150_ufsphy_cfg,
11811566 }, {
11821567 .compatible = "qcom,sm8250-qmp-ufs-phy",
1183− .data = &sm8150_ufsphy_cfg,
1568+ .data = &sm8250_ufsphy_cfg,
11841569 }, {
11851570 .compatible = "qcom,sm8350-qmp-ufs-phy",
11861571 .data = &sm8350_ufsphy_cfg,
11871572 }, {
11881573 .compatible = "qcom,sm8450-qmp-ufs-phy",
11891574 .data = &sm8450_ufsphy_cfg,
1575+ }, {
1576+ .compatible = "qcom,sm8550-qmp-ufs-phy",
1577+ .data = &sm8550_ufsphy_cfg,
11901578 },
11911579 { },
11921580 };
drivers/phy/qualcomm/phy-qcom-qmp-usb.c+41−42
@@ -21,6 +21,9 @@ · 20 unmodified lines
2121 #include <linux/slab.h>
2222
2323 #include "phy-qcom-qmp.h"
24+#include "phy-qcom-qmp-pcs-misc-v3.h"
25+#include "phy-qcom-qmp-pcs-usb-v4.h"
26+#include "phy-qcom-qmp-pcs-usb-v5.h"
2427
2528 /* QPHY_SW_RESET bit */
2629 #define SW_RESET BIT(0)
@@ -54,9 +57,6 @@ · 27 unmodified lines
5457 /* QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR register bits */
5558 #define IRQ_CLEAR BIT(0)
5659
57−/* QPHY_PCS_LFPS_RXTERM_IRQ_STATUS register bits */
58−#define RCVR_DETECT BIT(0)
59−
6060 /* QPHY_V3_PCS_MISC_CLAMP_ENABLE register bits */
6161 #define CLAMP_EN BIT(0) /* enables i/o clamp_n */
6262
@@ -94,53 +94,49 @@ enum qphy_reg_layout { · 31 unmodified lines
9494 QPHY_PCS_STATUS,
9595 QPHY_PCS_AUTONOMOUS_MODE_CTRL,
9696 QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR,
97− QPHY_PCS_LFPS_RXTERM_IRQ_STATUS,
9897 QPHY_PCS_POWER_DOWN_CONTROL,
99− /* PCS_MISC registers */
100− QPHY_PCS_MISC_TYPEC_CTRL,
10198 /* Keep last to ensure regs_layout arrays are properly initialized */
10299 QPHY_LAYOUT_SIZE
103100 };
104101
105−static const unsigned int usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = {
106− [QPHY_SW_RESET] = 0x00,
107− [QPHY_START_CTRL] = 0x08,
108− [QPHY_PCS_STATUS] = 0x17c,
109− [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = 0x0d4,
110− [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = 0x0d8,
111− [QPHY_PCS_LFPS_RXTERM_IRQ_STATUS] = 0x178,
112− [QPHY_PCS_POWER_DOWN_CONTROL] = 0x04,
102+static const unsigned int qmp_v2_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = {
103+ [QPHY_SW_RESET] = QPHY_V2_PCS_SW_RESET,
104+ [QPHY_START_CTRL] = QPHY_V2_PCS_START_CONTROL,
105+ [QPHY_PCS_STATUS] = QPHY_V2_PCS_USB_PCS_STATUS,
106+ [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = QPHY_V2_PCS_AUTONOMOUS_MODE_CTRL,
107+ [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = QPHY_V2_PCS_LFPS_RXTERM_IRQ_CLEAR,
108+ [QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V2_PCS_POWER_DOWN_CONTROL,
113109 };
114110
115111 static const unsigned int qmp_v3_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = {
116− [QPHY_SW_RESET] = 0x00,
117− [QPHY_START_CTRL] = 0x08,
118− [QPHY_PCS_STATUS] = 0x174,
119− [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = 0x0d8,
120− [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = 0x0dc,
121− [QPHY_PCS_LFPS_RXTERM_IRQ_STATUS] = 0x170,
122− [QPHY_PCS_POWER_DOWN_CONTROL] = 0x04,
112+ [QPHY_SW_RESET] = QPHY_V3_PCS_SW_RESET,
113+ [QPHY_START_CTRL] = QPHY_V3_PCS_START_CONTROL,
114+ [QPHY_PCS_STATUS] = QPHY_V3_PCS_PCS_STATUS,
115+ [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = QPHY_V3_PCS_AUTONOMOUS_MODE_CTRL,
116+ [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = QPHY_V3_PCS_LFPS_RXTERM_IRQ_CLEAR,
117+ [QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V3_PCS_POWER_DOWN_CONTROL,
123118 };
124119
125120 static const unsigned int qmp_v4_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = {
126− [QPHY_SW_RESET] = 0x00,
127− [QPHY_START_CTRL] = 0x44,
128− [QPHY_PCS_STATUS] = 0x14,
129− [QPHY_PCS_POWER_DOWN_CONTROL] = 0x40,
121+ [QPHY_SW_RESET] = QPHY_V4_PCS_SW_RESET,
122+ [QPHY_START_CTRL] = QPHY_V4_PCS_START_CONTROL,
123+ [QPHY_PCS_STATUS] = QPHY_V4_PCS_PCS_STATUS1,
124+ [QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V4_PCS_POWER_DOWN_CONTROL,
130125
131126 /* In PCS_USB */
132− [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = 0x008,
133− [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = 0x014,
127+ [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = QPHY_V4_PCS_USB3_AUTONOMOUS_MODE_CTRL,
128+ [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = QPHY_V4_PCS_USB3_LFPS_RXTERM_IRQ_CLEAR,
134129 };
135130
136−static const unsigned int qcm2290_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = {
137− [QPHY_SW_RESET] = 0x00,
138− [QPHY_PCS_POWER_DOWN_CONTROL] = 0x04,
139− [QPHY_START_CTRL] = 0x08,
140− [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = 0xd8,
141− [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = 0xdc,
142− [QPHY_PCS_STATUS] = 0x174,
143− [QPHY_PCS_MISC_TYPEC_CTRL] = 0x00,
131+static const unsigned int qmp_v5_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = {
132+ [QPHY_SW_RESET] = QPHY_V5_PCS_SW_RESET,
133+ [QPHY_START_CTRL] = QPHY_V5_PCS_START_CONTROL,
134+ [QPHY_PCS_STATUS] = QPHY_V5_PCS_PCS_STATUS1,
135+ [QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V5_PCS_POWER_DOWN_CONTROL,
136+
137+ /* In PCS_USB */
138+ [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = QPHY_V5_PCS_USB3_AUTONOMOUS_MODE_CTRL,
139+ [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = QPHY_V5_PCS_USB3_LFPS_RXTERM_IRQ_CLEAR,
144140 };
145141
146142 static const struct qmp_phy_init_tbl ipq8074_usb3_serdes_tbl[] = {
@@ -1265,7 +1261,7 @@ static const struct qmp_phy_init_tbl qcm2290_usb3_tx_tbl[] = { · 1118 unmodified lines
12651261
12661262 static const struct qmp_phy_init_tbl qcm2290_usb3_rx_tbl[] = {
12671263 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
1268− QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x00),
1264+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x80),
12691265 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x00),
12701266 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x00),
12711267 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FO_GAIN, 0x0a),
@@ -1607,7 +1603,7 @@ static const struct qmp_phy_cfg msm8996_usb3phy_cfg = { · 335 unmodified lines
16071603 .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
16081604 .vreg_list = qmp_phy_vreg_l,
16091605 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
1610− .regs = usb3phy_regs_layout,
1606+ .regs = qmp_v2_usb3phy_regs_layout,
16111607 };
16121608
16131609 static const struct qmp_phy_cfg qmp_v3_usb3phy_cfg = {
@@ -1675,7 +1671,7 @@ static const struct qmp_phy_cfg sc8280xp_usb3_uniphy_cfg = { · 61 unmodified lines
16751671 .num_resets = ARRAY_SIZE(qcm2290_usb3phy_reset_l),
16761672 .vreg_list = qmp_phy_vreg_l,
16771673 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
1678− .regs = qmp_v4_usb3phy_regs_layout,
1674+ .regs = qmp_v5_usb3phy_regs_layout,
16791675 };
16801676
16811677 static const struct qmp_phy_cfg qmp_v3_usb3_uniphy_cfg = {
@@ -1866,7 +1862,7 @@ static const struct qmp_phy_cfg sdx65_usb3_uniphy_cfg = { · 184 unmodified lines
18661862 .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
18671863 .vreg_list = qmp_phy_vreg_l,
18681864 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
1869− .regs = qmp_v4_usb3phy_regs_layout,
1865+ .regs = qmp_v5_usb3phy_regs_layout,
18701866 .pcs_usb_offset = 0x1000,
18711867
18721868 .has_pwrdn_delay = true,
@@ -1891,7 +1887,7 @@ static const struct qmp_phy_cfg sm8350_usb3phy_cfg = { · 18 unmodified lines
18911887 .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
18921888 .vreg_list = qmp_phy_vreg_l,
18931889 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
1894− .regs = qmp_v4_usb3phy_regs_layout,
1890+ .regs = qmp_v5_usb3phy_regs_layout,
18951891 .pcs_usb_offset = 0x300,
18961892
18971893 .has_pwrdn_delay = true,
@@ -1917,7 +1913,7 @@ static const struct qmp_phy_cfg sm8350_usb3_uniphy_cfg = { · 19 unmodified lines
19171913 .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
19181914 .vreg_list = qmp_phy_vreg_l,
19191915 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
1920− .regs = qmp_v4_usb3phy_regs_layout,
1916+ .regs = qmp_v5_usb3phy_regs_layout,
19211917 .pcs_usb_offset = 0x1000,
19221918
19231919 .has_pwrdn_delay = true,
@@ -1940,7 +1936,7 @@ static const struct qmp_phy_cfg qcm2290_usb3phy_cfg = { · 16 unmodified lines
19401936 .num_resets = ARRAY_SIZE(qcm2290_usb3phy_reset_l),
19411937 .vreg_list = qmp_phy_vreg_l,
19421938 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
1943− .regs = qcm2290_usb3phy_regs_layout,
1939+ .regs = qmp_v3_usb3phy_regs_layout,
19441940 };
19451941
19461942 static void qmp_usb_configure_lane(void __iomem *base,
@@ -2622,6 +2618,9 @@ static const struct of_device_id qmp_usb_of_match_table[] = { · 675 unmodified lines
26222618 }, {
26232619 .compatible = "qcom,sdx65-qmp-usb3-uni-phy",
26242620 .data = &sdx65_usb3_uniphy_cfg,
2621+ }, {
2622+ .compatible = "qcom,sm6115-qmp-usb3-phy",
2623+ .data = &qcm2290_usb3phy_cfg,
26252624 }, {
26262625 .compatible = "qcom,sm8150-qmp-usb3-phy",
26272626 .data = &sm8150_usb3phy_cfg,
drivers/phy/qualcomm/phy-qcom-qmp.h+12−11
@@ -21,31 +21,28 @@ · 20 unmodified lines
2121 #include "phy-qcom-qmp-qserdes-txrx-v5_20.h"
2222 #include "phy-qcom-qmp-qserdes-txrx-v5_5nm.h"
2323
24+#include "phy-qcom-qmp-qserdes-com-v6.h"
25+#include "phy-qcom-qmp-qserdes-txrx-v6.h"
26+#include "phy-qcom-qmp-qserdes-txrx-v6_20.h"
27+#include "phy-qcom-qmp-qserdes-ln-shrd-v6.h"
28+
2429 #include "phy-qcom-qmp-qserdes-pll.h"
2530
2631 #include "phy-qcom-qmp-pcs-v2.h"
2732
2833 #include "phy-qcom-qmp-pcs-v3.h"
29−#include "phy-qcom-qmp-pcs-misc-v3.h"
30−#include "phy-qcom-qmp-pcs-ufs-v3.h"
3134
3235 #include "phy-qcom-qmp-pcs-v4.h"
33−#include "phy-qcom-qmp-pcs-pcie-v4.h"
34−#include "phy-qcom-qmp-pcs-usb-v4.h"
35−#include "phy-qcom-qmp-pcs-ufs-v4.h"
3636
3737 #include "phy-qcom-qmp-pcs-v4_20.h"
38−#include "phy-qcom-qmp-pcs-pcie-v4_20.h"
3938
4039 #include "phy-qcom-qmp-pcs-v5.h"
40+
4141 #include "phy-qcom-qmp-pcs-v5_20.h"
42−#include "phy-qcom-qmp-pcs-pcie-v5.h"
43−#include "phy-qcom-qmp-pcs-usb-v5.h"
44−#include "phy-qcom-qmp-pcs-ufs-v5.h"
4542
46−#include "phy-qcom-qmp-pcs-pcie-v5_20.h"
43+#include "phy-qcom-qmp-pcs-v6.h"
4744
48−#include "phy-qcom-qmp-pcie-qhp.h"
45+#include "phy-qcom-qmp-pcs-v6_20.h"
4946
5047 /* Only for QMP V3 & V4 PHY - DP COM registers */
5148 #define QPHY_V3_DP_COM_PHY_MODE_CTRL 0x00
@@ -137,4 +134,8 @@ · 85 unmodified lines
137134 #define QPHY_V4_PCS_MISC_TYPEC_STATUS 0x10
138135 #define QPHY_V4_PCS_MISC_PLACEHOLDER_STATUS 0x14
139136
137+/* Only for QMP V6 PHY - DP PHY registers */
138+#define QSERDES_V6_DP_PHY_AUX_INTERRUPT_STATUS 0x0e0
139+#define QSERDES_V6_DP_PHY_STATUS 0x0e4
140+
140141 #endif
drivers/phy/qualcomm/phy-qcom-snps-eusb2.c+441−0
@@ -0,0 +1,441 @@
1+// SPDX-License-Identifier: GPL-2.0
2+/*
3+ * Copyright (c) 2023, Linaro Limited
4+ */
5+
6+#include <linux/bitfield.h>
7+#include <linux/clk.h>
8+#include <linux/delay.h>
9+#include <linux/iopoll.h>
10+#include <linux/phy/phy.h>
11+#include <linux/platform_device.h>
12+#include <linux/regulator/consumer.h>
13+#include <linux/reset.h>
14+
15+#define USB_PHY_UTMI_CTRL0 (0x3c)
16+#define SLEEPM BIT(0)
17+#define OPMODE_MASK GENMASK(4, 3)
18+#define OPMODE_NONDRIVING BIT(3)
19+
20+#define USB_PHY_UTMI_CTRL5 (0x50)
21+#define POR BIT(1)
22+
23+#define USB_PHY_HS_PHY_CTRL_COMMON0 (0x54)
24+#define PHY_ENABLE BIT(0)
25+#define SIDDQ_SEL BIT(1)
26+#define SIDDQ BIT(2)
27+#define RETENABLEN BIT(3)
28+#define FSEL_MASK GENMASK(6, 4)
29+#define FSEL_19_2_MHZ_VAL (0x0)
30+#define FSEL_38_4_MHZ_VAL (0x4)
31+
32+#define USB_PHY_CFG_CTRL_1 (0x58)
33+#define PHY_CFG_PLL_CPBIAS_CNTRL_MASK GENMASK(7, 1)
34+
35+#define USB_PHY_CFG_CTRL_2 (0x5c)
36+#define PHY_CFG_PLL_FB_DIV_7_0_MASK GENMASK(7, 0)
37+#define DIV_7_0_19_2_MHZ_VAL (0x90)
38+#define DIV_7_0_38_4_MHZ_VAL (0xc8)
39+
40+#define USB_PHY_CFG_CTRL_3 (0x60)
41+#define PHY_CFG_PLL_FB_DIV_11_8_MASK GENMASK(3, 0)
42+#define DIV_11_8_19_2_MHZ_VAL (0x1)
43+#define DIV_11_8_38_4_MHZ_VAL (0x0)
44+
45+#define PHY_CFG_PLL_REF_DIV GENMASK(7, 4)
46+#define PLL_REF_DIV_VAL (0x0)
47+
48+#define USB_PHY_HS_PHY_CTRL2 (0x64)
49+#define VBUSVLDEXT0 BIT(0)
50+#define USB2_SUSPEND_N BIT(2)
51+#define USB2_SUSPEND_N_SEL BIT(3)
52+#define VBUS_DET_EXT_SEL BIT(4)
53+
54+#define USB_PHY_CFG_CTRL_4 (0x68)
55+#define PHY_CFG_PLL_GMP_CNTRL_MASK GENMASK(1, 0)
56+#define PHY_CFG_PLL_INT_CNTRL_MASK GENMASK(7, 2)
57+
58+#define USB_PHY_CFG_CTRL_5 (0x6c)
59+#define PHY_CFG_PLL_PROP_CNTRL_MASK GENMASK(4, 0)
60+#define PHY_CFG_PLL_VREF_TUNE_MASK GENMASK(7, 6)
61+
62+#define USB_PHY_CFG_CTRL_6 (0x70)
63+#define PHY_CFG_PLL_VCO_CNTRL_MASK GENMASK(2, 0)
64+
65+#define USB_PHY_CFG_CTRL_7 (0x74)
66+
67+#define USB_PHY_CFG_CTRL_8 (0x78)
68+#define PHY_CFG_TX_FSLS_VREF_TUNE_MASK GENMASK(1, 0)
69+#define PHY_CFG_TX_FSLS_VREG_BYPASS BIT(2)
70+#define PHY_CFG_TX_HS_VREF_TUNE_MASK GENMASK(5, 3)
71+#define PHY_CFG_TX_HS_XV_TUNE_MASK GENMASK(7, 6)
72+
73+#define USB_PHY_CFG_CTRL_9 (0x7c)
74+#define PHY_CFG_TX_PREEMP_TUNE_MASK GENMASK(2, 0)
75+#define PHY_CFG_TX_RES_TUNE_MASK GENMASK(4, 3)
76+#define PHY_CFG_TX_RISE_TUNE_MASK GENMASK(6, 5)
77+#define PHY_CFG_RCAL_BYPASS BIT(7)
78+
79+#define USB_PHY_CFG_CTRL_10 (0x80)
80+
81+#define USB_PHY_CFG0 (0x94)
82+#define DATAPATH_CTRL_OVERRIDE_EN BIT(0)
83+#define CMN_CTRL_OVERRIDE_EN BIT(1)
84+
85+#define UTMI_PHY_CMN_CTRL0 (0x98)
86+#define TESTBURNIN BIT(6)
87+
88+#define USB_PHY_FSEL_SEL (0xb8)
89+#define FSEL_SEL BIT(0)
90+
91+#define USB_PHY_APB_ACCESS_CMD (0x130)
92+#define RW_ACCESS BIT(0)
93+#define APB_START_CMD BIT(1)
94+#define APB_LOGIC_RESET BIT(2)
95+
96+#define USB_PHY_APB_ACCESS_STATUS (0x134)
97+#define ACCESS_DONE BIT(0)
98+#define TIMED_OUT BIT(1)
99+#define ACCESS_ERROR BIT(2)
100+#define ACCESS_IN_PROGRESS BIT(3)
101+
102+#define USB_PHY_APB_ADDRESS (0x138)
103+#define APB_REG_ADDR_MASK GENMASK(7, 0)
104+
105+#define USB_PHY_APB_WRDATA_LSB (0x13c)
106+#define APB_REG_WRDATA_7_0_MASK GENMASK(3, 0)
107+
108+#define USB_PHY_APB_WRDATA_MSB (0x140)
109+#define APB_REG_WRDATA_15_8_MASK GENMASK(7, 4)
110+
111+#define USB_PHY_APB_RDDATA_LSB (0x144)
112+#define APB_REG_RDDATA_7_0_MASK GENMASK(3, 0)
113+
114+#define USB_PHY_APB_RDDATA_MSB (0x148)
115+#define APB_REG_RDDATA_15_8_MASK GENMASK(7, 4)
116+
117+static const char * const eusb2_hsphy_vreg_names[] = {
118+ "vdd", "vdda12",
119+};
120+
121+#define EUSB2_NUM_VREGS ARRAY_SIZE(eusb2_hsphy_vreg_names)
122+
123+struct qcom_snps_eusb2_hsphy {
124+ struct phy *phy;
125+ void __iomem *base;
126+
127+ struct clk *ref_clk;
128+ struct reset_control *phy_reset;
129+
130+ struct regulator_bulk_data vregs[EUSB2_NUM_VREGS];
131+
132+ enum phy_mode mode;
133+
134+ struct phy *repeater;
135+};
136+
137+static int qcom_snps_eusb2_hsphy_set_mode(struct phy *p, enum phy_mode mode, int submode)
138+{
139+ struct qcom_snps_eusb2_hsphy *phy = phy_get_drvdata(p);
140+
141+ phy->mode = mode;
142+
143+ return phy_set_mode_ext(phy->repeater, mode, submode);
144+}
145+
146+static void qcom_snps_eusb2_hsphy_write_mask(void __iomem *base, u32 offset,
147+ u32 mask, u32 val)
148+{
149+ u32 reg;
150+
151+ reg = readl_relaxed(base + offset);
152+ reg &= ~mask;
153+ reg |= val & mask;
154+ writel_relaxed(reg, base + offset);
155+
156+ /* Ensure above write is completed */
157+ readl_relaxed(base + offset);
158+}
159+
160+static void qcom_eusb2_default_parameters(struct qcom_snps_eusb2_hsphy *phy)
161+{
162+ /* default parameters: tx pre-emphasis */
163+ qcom_snps_eusb2_hsphy_write_mask(phy->base, USB_PHY_CFG_CTRL_9,
164+ PHY_CFG_TX_PREEMP_TUNE_MASK,
165+ FIELD_PREP(PHY_CFG_TX_PREEMP_TUNE_MASK, 0));
166+
167+ /* tx rise/fall time */
168+ qcom_snps_eusb2_hsphy_write_mask(phy->base, USB_PHY_CFG_CTRL_9,
169+ PHY_CFG_TX_RISE_TUNE_MASK,
170+ FIELD_PREP(PHY_CFG_TX_RISE_TUNE_MASK, 0x2));
171+
172+ /* source impedance adjustment */
173+ qcom_snps_eusb2_hsphy_write_mask(phy->base, USB_PHY_CFG_CTRL_9,
174+ PHY_CFG_TX_RES_TUNE_MASK,
175+ FIELD_PREP(PHY_CFG_TX_RES_TUNE_MASK, 0x1));
176+
177+ /* dc voltage level adjustement */
178+ qcom_snps_eusb2_hsphy_write_mask(phy->base, USB_PHY_CFG_CTRL_8,
179+ PHY_CFG_TX_HS_VREF_TUNE_MASK,
180+ FIELD_PREP(PHY_CFG_TX_HS_VREF_TUNE_MASK, 0x3));
181+
182+ /* transmitter HS crossover adjustement */
183+ qcom_snps_eusb2_hsphy_write_mask(phy->base, USB_PHY_CFG_CTRL_8,
184+ PHY_CFG_TX_HS_XV_TUNE_MASK,
185+ FIELD_PREP(PHY_CFG_TX_HS_XV_TUNE_MASK, 0x0));
186+}
187+
188+static int qcom_eusb2_ref_clk_init(struct qcom_snps_eusb2_hsphy *phy)
189+{
190+ unsigned long ref_clk_freq = clk_get_rate(phy->ref_clk);
191+
192+ switch (ref_clk_freq) {
193+ case 19200000:
194+ qcom_snps_eusb2_hsphy_write_mask(phy->base, USB_PHY_HS_PHY_CTRL_COMMON0,
195+ FSEL_MASK,
196+ FIELD_PREP(FSEL_MASK, FSEL_19_2_MHZ_VAL));
197+
198+ qcom_snps_eusb2_hsphy_write_mask(phy->base, USB_PHY_CFG_CTRL_2,
199+ PHY_CFG_PLL_FB_DIV_7_0_MASK,
200+ DIV_7_0_19_2_MHZ_VAL);
201+
202+ qcom_snps_eusb2_hsphy_write_mask(phy->base, USB_PHY_CFG_CTRL_3,
203+ PHY_CFG_PLL_FB_DIV_11_8_MASK,
204+ DIV_11_8_19_2_MHZ_VAL);
205+ break;
206+
207+ case 38400000:
208+ qcom_snps_eusb2_hsphy_write_mask(phy->base, USB_PHY_HS_PHY_CTRL_COMMON0,
209+ FSEL_MASK,
210+ FIELD_PREP(FSEL_MASK, FSEL_38_4_MHZ_VAL));
211+
212+ qcom_snps_eusb2_hsphy_write_mask(phy->base, USB_PHY_CFG_CTRL_2,
213+ PHY_CFG_PLL_FB_DIV_7_0_MASK,
214+ DIV_7_0_38_4_MHZ_VAL);
215+
216+ qcom_snps_eusb2_hsphy_write_mask(phy->base, USB_PHY_CFG_CTRL_3,
217+ PHY_CFG_PLL_FB_DIV_11_8_MASK,
218+ DIV_11_8_38_4_MHZ_VAL);
219+ break;
220+
221+ default:
222+ dev_err(&phy->phy->dev, "unsupported ref_clk_freq:%lu\n", ref_clk_freq);
223+ return -EINVAL;
224+ }
225+
226+ qcom_snps_eusb2_hsphy_write_mask(phy->base, USB_PHY_CFG_CTRL_3,
227+ PHY_CFG_PLL_REF_DIV, PLL_REF_DIV_VAL);
228+
229+ return 0;
230+}
231+
232+static int qcom_snps_eusb2_hsphy_init(struct phy *p)
233+{
234+ struct qcom_snps_eusb2_hsphy *phy = phy_get_drvdata(p);
235+ int ret;
236+
237+ ret = regulator_bulk_enable(ARRAY_SIZE(phy->vregs), phy->vregs);
238+ if (ret)
239+ return ret;
240+
241+ ret = phy_init(phy->repeater);
242+ if (ret) {
243+ dev_err(&p->dev, "repeater init failed. %d\n", ret);
244+ goto disable_vreg;
245+ }
246+
247+ ret = clk_prepare_enable(phy->ref_clk);
248+ if (ret) {
249+ dev_err(&p->dev, "failed to enable ref clock, %d\n", ret);
250+ goto disable_vreg;
251+ }
252+
253+ ret = reset_control_assert(phy->phy_reset);
254+ if (ret) {
255+ dev_err(&p->dev, "failed to assert phy_reset, %d\n", ret);
256+ goto disable_ref_clk;
257+ }
258+
259+ usleep_range(100, 150);
260+
261+ ret = reset_control_deassert(phy->phy_reset);
262+ if (ret) {
263+ dev_err(&p->dev, "failed to de-assert phy_reset, %d\n", ret);
264+ goto disable_ref_clk;
265+ }
266+
267+ qcom_snps_eusb2_hsphy_write_mask(phy->base, USB_PHY_CFG0,
268+ CMN_CTRL_OVERRIDE_EN, CMN_CTRL_OVERRIDE_EN);
269+
270+ qcom_snps_eusb2_hsphy_write_mask(phy->base, USB_PHY_UTMI_CTRL5, POR, POR);
271+
272+ qcom_snps_eusb2_hsphy_write_mask(phy->base, USB_PHY_HS_PHY_CTRL_COMMON0,
273+ PHY_ENABLE | RETENABLEN, PHY_ENABLE | RETENABLEN);
274+
275+ qcom_snps_eusb2_hsphy_write_mask(phy->base, USB_PHY_APB_ACCESS_CMD,
276+ APB_LOGIC_RESET, APB_LOGIC_RESET);
277+
278+ qcom_snps_eusb2_hsphy_write_mask(phy->base, UTMI_PHY_CMN_CTRL0, TESTBURNIN, 0);
279+
280+ qcom_snps_eusb2_hsphy_write_mask(phy->base, USB_PHY_FSEL_SEL,
281+ FSEL_SEL, FSEL_SEL);
282+
283+ /* update ref_clk related registers */
284+ ret = qcom_eusb2_ref_clk_init(phy);
285+ if (ret)
286+ goto disable_ref_clk;
287+
288+ qcom_snps_eusb2_hsphy_write_mask(phy->base, USB_PHY_CFG_CTRL_1,
289+ PHY_CFG_PLL_CPBIAS_CNTRL_MASK,
290+ FIELD_PREP(PHY_CFG_PLL_CPBIAS_CNTRL_MASK, 0x1));
291+
292+ qcom_snps_eusb2_hsphy_write_mask(phy->base, USB_PHY_CFG_CTRL_4,
293+ PHY_CFG_PLL_INT_CNTRL_MASK,
294+ FIELD_PREP(PHY_CFG_PLL_INT_CNTRL_MASK, 0x8));
295+
296+ qcom_snps_eusb2_hsphy_write_mask(phy->base, USB_PHY_CFG_CTRL_4,
297+ PHY_CFG_PLL_GMP_CNTRL_MASK,
298+ FIELD_PREP(PHY_CFG_PLL_GMP_CNTRL_MASK, 0x1));
299+
300+ qcom_snps_eusb2_hsphy_write_mask(phy->base, USB_PHY_CFG_CTRL_5,
301+ PHY_CFG_PLL_PROP_CNTRL_MASK,
302+ FIELD_PREP(PHY_CFG_PLL_PROP_CNTRL_MASK, 0x10));
303+
304+ qcom_snps_eusb2_hsphy_write_mask(phy->base, USB_PHY_CFG_CTRL_6,
305+ PHY_CFG_PLL_VCO_CNTRL_MASK,
306+ FIELD_PREP(PHY_CFG_PLL_VCO_CNTRL_MASK, 0x0));
307+
308+ qcom_snps_eusb2_hsphy_write_mask(phy->base, USB_PHY_CFG_CTRL_5,
309+ PHY_CFG_PLL_VREF_TUNE_MASK,
310+ FIELD_PREP(PHY_CFG_PLL_VREF_TUNE_MASK, 0x1));
311+
312+ qcom_snps_eusb2_hsphy_write_mask(phy->base, USB_PHY_HS_PHY_CTRL2,
313+ VBUS_DET_EXT_SEL, VBUS_DET_EXT_SEL);
314+
315+ /* set default parameters */
316+ qcom_eusb2_default_parameters(phy);
317+
318+ qcom_snps_eusb2_hsphy_write_mask(phy->base, USB_PHY_HS_PHY_CTRL2,
319+ USB2_SUSPEND_N_SEL | USB2_SUSPEND_N,
320+ USB2_SUSPEND_N_SEL | USB2_SUSPEND_N);
321+
322+ qcom_snps_eusb2_hsphy_write_mask(phy->base, USB_PHY_UTMI_CTRL0, SLEEPM, SLEEPM);
323+
324+ qcom_snps_eusb2_hsphy_write_mask(phy->base, USB_PHY_HS_PHY_CTRL_COMMON0,
325+ SIDDQ_SEL, SIDDQ_SEL);
326+
327+ qcom_snps_eusb2_hsphy_write_mask(phy->base, USB_PHY_HS_PHY_CTRL_COMMON0,
328+ SIDDQ, 0);
329+
330+ qcom_snps_eusb2_hsphy_write_mask(phy->base, USB_PHY_UTMI_CTRL5, POR, 0);
331+
332+ qcom_snps_eusb2_hsphy_write_mask(phy->base, USB_PHY_HS_PHY_CTRL2,
333+ USB2_SUSPEND_N_SEL, 0);
334+
335+ return 0;
336+
337+disable_ref_clk:
338+ clk_disable_unprepare(phy->ref_clk);
339+
340+disable_vreg:
341+ regulator_bulk_disable(ARRAY_SIZE(phy->vregs), phy->vregs);
342+
343+ return ret;
344+}
345+
346+static int qcom_snps_eusb2_hsphy_exit(struct phy *p)
347+{
348+ struct qcom_snps_eusb2_hsphy *phy = phy_get_drvdata(p);
349+
350+ clk_disable_unprepare(phy->ref_clk);
351+
352+ regulator_bulk_disable(ARRAY_SIZE(phy->vregs), phy->vregs);
353+
354+ phy_exit(phy->repeater);
355+
356+ return 0;
357+}
358+
359+static const struct phy_ops qcom_snps_eusb2_hsphy_ops = {
360+ .init = qcom_snps_eusb2_hsphy_init,
361+ .exit = qcom_snps_eusb2_hsphy_exit,
362+ .set_mode = qcom_snps_eusb2_hsphy_set_mode,
363+ .owner = THIS_MODULE,
364+};
365+
366+static int qcom_snps_eusb2_hsphy_probe(struct platform_device *pdev)
367+{
368+ struct device *dev = &pdev->dev;
369+ struct device_node *np = dev->of_node;
370+ struct qcom_snps_eusb2_hsphy *phy;
371+ struct phy_provider *phy_provider;
372+ struct phy *generic_phy;
373+ int ret, i;
374+ int num;
375+
376+ phy = devm_kzalloc(dev, sizeof(*phy), GFP_KERNEL);
377+ if (!phy)
378+ return -ENOMEM;
379+
380+ phy->base = devm_platform_ioremap_resource(pdev, 0);
381+ if (IS_ERR(phy->base))
382+ return PTR_ERR(phy->base);
383+
384+ phy->phy_reset = devm_reset_control_get_exclusive(dev, NULL);
385+ if (IS_ERR(phy->phy_reset))
386+ return PTR_ERR(phy->phy_reset);
387+
388+ phy->ref_clk = devm_clk_get(dev, "ref");
389+ if (IS_ERR(phy->ref_clk))
390+ return dev_err_probe(dev, PTR_ERR(phy->ref_clk),
391+ "failed to get ref clk\n");
392+
393+ num = ARRAY_SIZE(phy->vregs);
394+ for (i = 0; i < num; i++)
395+ phy->vregs[i].supply = eusb2_hsphy_vreg_names[i];
396+
397+ ret = devm_regulator_bulk_get(dev, num, phy->vregs);
398+ if (ret)
399+ return dev_err_probe(dev, ret,
400+ "failed to get regulator supplies\n");
401+
402+ phy->repeater = devm_of_phy_get_by_index(dev, np, 0);
403+ if (IS_ERR(phy->repeater))
404+ return dev_err_probe(dev, PTR_ERR(phy->repeater),
405+ "failed to get repeater\n");
406+
407+ generic_phy = devm_phy_create(dev, NULL, &qcom_snps_eusb2_hsphy_ops);
408+ if (IS_ERR(generic_phy)) {
409+ dev_err(dev, "failed to create phy %d\n", ret);
410+ return PTR_ERR(generic_phy);
411+ }
412+
413+ dev_set_drvdata(dev, phy);
414+ phy_set_drvdata(generic_phy, phy);
415+
416+ phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
417+ if (IS_ERR(phy_provider))
418+ return PTR_ERR(phy_provider);
419+
420+ dev_info(dev, "Registered Qcom-eUSB2 phy\n");
421+
422+ return 0;
423+}
424+
425+static const struct of_device_id qcom_snps_eusb2_hsphy_of_match_table[] = {
426+ { .compatible = "qcom,sm8550-snps-eusb2-phy", },
427+ { },
428+};
429+MODULE_DEVICE_TABLE(of, qcom_snps_eusb2_hsphy_of_match_table);
430+
431+static struct platform_driver qcom_snps_eusb2_hsphy_driver = {
432+ .probe = qcom_snps_eusb2_hsphy_probe,
433+ .driver = {
434+ .name = "qcom-snps-eusb2-hsphy",
435+ .of_match_table = qcom_snps_eusb2_hsphy_of_match_table,
436+ },
437+};
438+
439+module_platform_driver(qcom_snps_eusb2_hsphy_driver);
440+MODULE_DESCRIPTION("Qualcomm SNPS eUSB2 HS PHY driver");
441+MODULE_LICENSE("GPL");
drivers/phy/renesas/r8a779f0-ether-serdes.c+30−35
@@ -18,7 +18,6 @@ · 17 unmodified lines
1818 #define R8A779F0_ETH_SERDES_BANK_SELECT 0x03fc
1919 #define R8A779F0_ETH_SERDES_TIMEOUT_US 100000
2020 #define R8A779F0_ETH_SERDES_NUM_RETRY_LINKUP 3
21−#define R8A779F0_ETH_SERDES_NUM_RETRY_INIT 3
2221
2322 struct r8a779f0_eth_serdes_drv_data;
2423 struct r8a779f0_eth_serdes_channel {
@@ -242,51 +241,46 @@ static int r8a779f0_eth_serdes_hw_init(struct r8a779f0_eth_serdes_channel *chann · 217 unmodified lines
242241 if (ret)
243242 return ret;
244243
245− ret = r8a779f0_eth_serdes_reg_wait(&dd->channel[0], 0x0000, 0x380, BIT(15), 0);
244+ return r8a779f0_eth_serdes_reg_wait(&dd->channel[0], 0x0000, 0x380, BIT(15), 0);
245+}
246+
247+static int r8a779f0_eth_serdes_init(struct phy *p)
248+{
249+ struct r8a779f0_eth_serdes_channel *channel = phy_get_drvdata(p);
250+ int ret;
251+
252+ ret = r8a779f0_eth_serdes_hw_init(channel);
253+ if (!ret)
254+ channel->dd->initialized = true;
255+
256+ return ret;
257+}
258+
259+static int r8a779f0_eth_serdes_hw_init_late(struct r8a779f0_eth_serdes_channel
260+*channel)
261+{
262+ int ret;
263+
264+ ret = r8a779f0_eth_serdes_chan_setting(channel);
246265 if (ret)
247266 return ret;
248267
249− for (i = 0; i < R8A779F0_ETH_SERDES_NUM; i++) {
250− ret = r8a779f0_eth_serdes_chan_setting(&dd->channel[i]);
251− if (ret)
252− return ret;
253− }
254−
255− for (i = 0; i < R8A779F0_ETH_SERDES_NUM; i++) {
256− ret = r8a779f0_eth_serdes_chan_speed(&dd->channel[i]);
257− if (ret)
258− return ret;
259− }
268+ ret = r8a779f0_eth_serdes_chan_speed(channel);
269+ if (ret)
270+ return ret;
260271
261− for (i = 0; i < R8A779F0_ETH_SERDES_NUM; i++)
262− r8a779f0_eth_serdes_write32(dd->channel[i].addr, 0x03c0, 0x380, 0x0000);
263− for (i = 0; i < R8A779F0_ETH_SERDES_NUM; i++)
264− r8a779f0_eth_serdes_write32(dd->channel[i].addr, 0x03d0, 0x380, 0x0000);
272+ r8a779f0_eth_serdes_write32(channel->addr, 0x03c0, 0x380, 0x0000);
265273
266− for (i = 0; i < R8A779F0_ETH_SERDES_NUM; i++) {
267− ret = r8a779f0_eth_serdes_monitor_linkup(&dd->channel[i]);
268− if (ret)
269− return ret;
270− }
274+ r8a779f0_eth_serdes_write32(channel->addr, 0x03d0, 0x380, 0x0000);
271275
272− return 0;
276+ return r8a779f0_eth_serdes_monitor_linkup(channel);
273277 }
274278
275−static int r8a779f0_eth_serdes_init(struct phy *p)
279+static int r8a779f0_eth_serdes_power_on(struct phy *p)
276280 {
277281 struct r8a779f0_eth_serdes_channel *channel = phy_get_drvdata(p);
278− int i, ret;
279282
280− for (i = 0; i < R8A779F0_ETH_SERDES_NUM_RETRY_INIT; i++) {
281− ret = r8a779f0_eth_serdes_hw_init(channel);
282− if (!ret) {
283− channel->dd->initialized = true;
284− break;
285− }
286− usleep_range(1000, 2000);
287− }
288−
289− return ret;
283+ return r8a779f0_eth_serdes_hw_init_late(channel);
290284 }
291285
292286 static int r8a779f0_eth_serdes_set_mode(struct phy *p, enum phy_mode mode,
@@ -319,6 +313,7 @@ static int r8a779f0_eth_serdes_set_speed(struct phy *p, int speed) · 26 unmodified lines
319313
320314 static const struct phy_ops r8a779f0_eth_serdes_ops = {
321315 .init = r8a779f0_eth_serdes_init,
316+ .power_on = r8a779f0_eth_serdes_power_on,
322317 .set_mode = r8a779f0_eth_serdes_set_mode,
323318 .set_speed = r8a779f0_eth_serdes_set_speed,
324319 };
drivers/phy/rockchip/phy-rockchip-typec.c+3−4
@@ -808,9 +808,8 @@ static int tcphy_get_mode(struct rockchip_typec_phy *tcphy) · 807 unmodified lines
808808 struct extcon_dev *edev = tcphy->extcon;
809809 union extcon_property_value property;
810810 unsigned int id;
811− bool ufp, dp;
812811 u8 mode;
813− int ret;
812+ int ret, ufp, dp;
814813
815814 if (!edev)
816815 return MODE_DFP_USB;
@@ -821,10 +820,10 @@ static int tcphy_get_mode(struct rockchip_typec_phy *tcphy) · 4 unmodified lines
821820 mode = MODE_DFP_USB;
822821 id = EXTCON_USB_HOST;
823822
824− if (ufp) {
823+ if (ufp > 0) {
825824 mode = MODE_UFP_USB;
826825 id = EXTCON_USB;
827− } else if (dp) {
826+ } else if (dp > 0) {
828827 mode = MODE_DFP_DP;
829828 id = EXTCON_DISP_DP;
830829
drivers/phy/tegra/xusb.c+17−0
@@ -718,6 +718,22 @@ static int tegra_xusb_setup_usb_role_switch(struct tegra_xusb_port *port) · 717 unmodified lines
718718 return err;
719719 }
720720
721+static void tegra_xusb_parse_usb_role_default_mode(struct tegra_xusb_port *port)
722+{
723+ enum usb_role role = USB_ROLE_NONE;
724+ enum usb_dr_mode mode = usb_get_role_switch_default_mode(&port->dev);
725+
726+ if (mode == USB_DR_MODE_HOST)
727+ role = USB_ROLE_HOST;
728+ else if (mode == USB_DR_MODE_PERIPHERAL)
729+ role = USB_ROLE_DEVICE;
730+
731+ if (role != USB_ROLE_NONE) {
732+ usb_role_switch_set_role(port->usb_role_sw, role);
733+ dev_dbg(&port->dev, "usb role default mode is %s", modes[mode]);
734+ }
735+}
736+
721737 static int tegra_xusb_usb2_port_parse_dt(struct tegra_xusb_usb2_port *usb2)
722738 {
723739 struct tegra_xusb_port *port = &usb2->base;
@@ -747,6 +763,7 @@ static int tegra_xusb_usb2_port_parse_dt(struct tegra_xusb_usb2_port *usb2) · 23 unmodified lines
747763 err = tegra_xusb_setup_usb_role_switch(port);
748764 if (err < 0)
749765 return err;
766+ tegra_xusb_parse_usb_role_default_mode(port);
750767 } else {
751768 dev_err(&port->dev, "usb-role-switch not found for %s mode",
752769 modes[usb2->mode]);
drivers/phy/ti/phy-j721e-wiz.c+56−10
@@ -58,6 +58,14 @@ enum wiz_lane_standard_mode { · 57 unmodified lines
5858 LANE_MODE_GEN4,
5959 };
6060
61+/*
62+ * List of master lanes used for lane swapping
63+ */
64+enum wiz_typec_master_lane {
65+ LANE0 = 0,
66+ LANE2 = 2,
67+};
68+
6169 enum wiz_refclk_mux_sel {
6270 PLL0_REFCLK,
6371 PLL1_REFCLK,
@@ -194,6 +202,9 @@ static const struct reg_field p_mac_div_sel1[WIZ_MAX_LANES] = { · 130 unmodified lines
194202 static const struct reg_field typec_ln10_swap =
195203 REG_FIELD(WIZ_SERDES_TYPEC, 30, 30);
196204
205+static const struct reg_field typec_ln23_swap =
206+ REG_FIELD(WIZ_SERDES_TYPEC, 31, 31);
207+
197208 struct wiz_clk_mux {
198209 struct clk_hw hw;
199210 struct regmap_field *field;
@@ -367,6 +378,7 @@ struct wiz { · 167 unmodified lines
367378 struct regmap_field *mux_sel_field[WIZ_MUX_NUM_CLOCKS];
368379 struct regmap_field *div_sel_field[WIZ_DIV_NUM_CLOCKS_16G];
369380 struct regmap_field *typec_ln10_swap;
381+ struct regmap_field *typec_ln23_swap;
370382 struct regmap_field *sup_legacy_clk_override;
371383
372384 struct device *dev;
@@ -376,6 +388,7 @@ struct wiz { · 3 unmodified lines
376388 struct gpio_desc *gpio_typec_dir;
377389 int typec_dir_delay;
378390 u32 lane_phy_type[WIZ_MAX_LANES];
391+ u32 master_lane_num[WIZ_MAX_LANES];
379392 struct clk *input_clks[WIZ_MAX_INPUT_CLOCKS];
380393 struct clk *output_clks[WIZ_MAX_OUTPUT_CLOCKS];
381394 struct clk_onecell_data clk_data;
@@ -675,6 +688,13 @@ static int wiz_regfield_init(struct wiz *wiz) · 293 unmodified lines
675688 return PTR_ERR(wiz->typec_ln10_swap);
676689 }
677690
691+ wiz->typec_ln23_swap = devm_regmap_field_alloc(dev, regmap,
692+ typec_ln23_swap);
693+ if (IS_ERR(wiz->typec_ln23_swap)) {
694+ dev_err(dev, "LN23_SWAP reg field init failed\n");
695+ return PTR_ERR(wiz->typec_ln23_swap);
696+ }
697+
678698 wiz->phy_en_refclk = devm_regmap_field_alloc(dev, regmap, phy_en_refclk);
679699 if (IS_ERR(wiz->phy_en_refclk)) {
680700 dev_err(dev, "PHY_EN_REFCLK reg field init failed\n");
@@ -1234,15 +1254,39 @@ static int wiz_phy_reset_deassert(struct reset_controller_dev *rcdev, · 553 unmodified lines
12341254 struct wiz *wiz = dev_get_drvdata(dev);
12351255 int ret;
12361256
1237− /* if typec-dir gpio was specified, set LN10 SWAP bit based on that */
1238− if (id == 0 && wiz->gpio_typec_dir) {
1239− if (wiz->typec_dir_delay)
1240− msleep_interruptible(wiz->typec_dir_delay);
1241−
1242− if (gpiod_get_value_cansleep(wiz->gpio_typec_dir))
1243− regmap_field_write(wiz->typec_ln10_swap, 1);
1244− else
1245− regmap_field_write(wiz->typec_ln10_swap, 0);
1257+ if (id == 0) {
1258+ /* if typec-dir gpio was specified, set LN10 SWAP bit based on that */
1259+ if (wiz->gpio_typec_dir) {
1260+ if (wiz->typec_dir_delay)
1261+ msleep_interruptible(wiz->typec_dir_delay);
1262+
1263+ if (gpiod_get_value_cansleep(wiz->gpio_typec_dir))
1264+ regmap_field_write(wiz->typec_ln10_swap, 1);
1265+ else
1266+ regmap_field_write(wiz->typec_ln10_swap, 0);
1267+ } else {
1268+ /* if no typec-dir gpio is specified and PHY type is USB3
1269+ * with master lane number is '0' or '2', then set LN10 or
1270+ * LN23 SWAP bit to '1' respectively.
1271+ */
1272+ u32 num_lanes = wiz->num_lanes;
1273+ int i;
1274+
1275+ for (i = 0; i < num_lanes; i++) {
1276+ if (wiz->lane_phy_type[i] == PHY_TYPE_USB3) {
1277+ switch (wiz->master_lane_num[i]) {
1278+ case LANE0:
1279+ regmap_field_write(wiz->typec_ln10_swap, 1);
1280+ break;
1281+ case LANE2:
1282+ regmap_field_write(wiz->typec_ln23_swap, 1);
1283+ break;
1284+ default:
1285+ break;
1286+ }
1287+ }
1288+ }
1289+ }
12461290 }
12471291
12481292 if (id == 0) {
@@ -1386,8 +1430,10 @@ static int wiz_get_lane_phy_types(struct device *dev, struct wiz *wiz) · 137 unmodified lines
13861430 dev_dbg(dev, "%s: Lanes %u-%u have phy-type %u\n", __func__,
13871431 reg, reg + num_lanes - 1, phy_type);
13881432
1389− for (i = reg; i < reg + num_lanes; i++)
1433+ for (i = reg; i < reg + num_lanes; i++) {
1434+ wiz->master_lane_num[i] = reg;
13901435 wiz->lane_phy_type[i] = phy_type;
1436+ }
13911437 }
13921438
13931439 return 0;
drivers/usb/host/ehci-exynos.c+6−17
@@ -80,19 +80,11 @@ static int exynos_ehci_get_phy(struct device *dev, · 79 unmodified lines
8080 return -EINVAL;
8181 }
8282
83− phy = devm_of_phy_get(dev, child, NULL);
83+ phy = devm_of_phy_optional_get(dev, child, NULL);
8484 exynos_ehci->phy[phy_number] = phy;
8585 if (IS_ERR(phy)) {
86− ret = PTR_ERR(phy);
87− if (ret == -EPROBE_DEFER) {
88− of_node_put(child);
89− return ret;
90− } else if (ret != -ENOSYS && ret != -ENODEV) {
91− dev_err(dev,
92− "Error retrieving usb2 phy: %d\n", ret);
93− of_node_put(child);
94− return ret;
95− }
86+ of_node_put(child);
87+ return PTR_ERR(phy);
9688 }
9789 }
9890
@@ -108,12 +100,10 @@ static int exynos_ehci_phy_enable(struct device *dev) · 9 unmodified lines
108100 int ret = 0;
109101
110102 for (i = 0; ret == 0 && i < PHY_NUMBER; i++)
111− if (!IS_ERR(exynos_ehci->phy[i]))
112− ret = phy_power_on(exynos_ehci->phy[i]);
103+ ret = phy_power_on(exynos_ehci->phy[i]);
113104 if (ret)
114105 for (i--; i >= 0; i--)
115− if (!IS_ERR(exynos_ehci->phy[i]))
116− phy_power_off(exynos_ehci->phy[i]);
106+ phy_power_off(exynos_ehci->phy[i]);
117107
118108 return ret;
119109 }
@@ -125,8 +115,7 @@ static void exynos_ehci_phy_disable(struct device *dev) · 5 unmodified lines
125115 int i;
126116
127117 for (i = 0; i < PHY_NUMBER; i++)
128− if (!IS_ERR(exynos_ehci->phy[i]))
129− phy_power_off(exynos_ehci->phy[i]);
118+ phy_power_off(exynos_ehci->phy[i]);
130119 }
131120
132121 static void exynos_setup_vbus_gpio(struct device *dev)
drivers/usb/host/ohci-exynos.c+6−17
@@ -69,19 +69,11 @@ static int exynos_ohci_get_phy(struct device *dev, · 68 unmodified lines
6969 return -EINVAL;
7070 }
7171
72− phy = devm_of_phy_get(dev, child, NULL);
72+ phy = devm_of_phy_optional_get(dev, child, NULL);
7373 exynos_ohci->phy[phy_number] = phy;
7474 if (IS_ERR(phy)) {
75− ret = PTR_ERR(phy);
76− if (ret == -EPROBE_DEFER) {
77− of_node_put(child);
78− return ret;
79− } else if (ret != -ENOSYS && ret != -ENODEV) {
80− dev_err(dev,
81− "Error retrieving usb2 phy: %d\n", ret);
82− of_node_put(child);
83− return ret;
84− }
75+ of_node_put(child);
76+ return PTR_ERR(phy);
8577 }
8678 }
8779
@@ -97,12 +89,10 @@ static int exynos_ohci_phy_enable(struct device *dev) · 9 unmodified lines
9789 int ret = 0;
9890
9991 for (i = 0; ret == 0 && i < PHY_NUMBER; i++)
100− if (!IS_ERR(exynos_ohci->phy[i]))
101− ret = phy_power_on(exynos_ohci->phy[i]);
92+ ret = phy_power_on(exynos_ohci->phy[i]);
10293 if (ret)
10394 for (i--; i >= 0; i--)
104− if (!IS_ERR(exynos_ohci->phy[i]))
105− phy_power_off(exynos_ohci->phy[i]);
95+ phy_power_off(exynos_ohci->phy[i]);
10696
10797 return ret;
10898 }
@@ -114,8 +104,7 @@ static void exynos_ohci_phy_disable(struct device *dev) · 5 unmodified lines
114104 int i;
115105
116106 for (i = 0; i < PHY_NUMBER; i++)
117− if (!IS_ERR(exynos_ohci->phy[i]))
118− phy_power_off(exynos_ohci->phy[i]);
107+ phy_power_off(exynos_ohci->phy[i]);
119108 }
120109
121110 static int exynos_ohci_probe(struct platform_device *pdev)
include/linux/phy/phy.h+9−7
@@ -250,11 +250,12 @@ static inline void phy_set_bus_width(struct phy *phy, int bus_width) · 249 unmodified lines
250250 phy->attrs.bus_width = bus_width;
251251 }
252252 struct phy *phy_get(struct device *dev, const char *string);
253−struct phy *phy_optional_get(struct device *dev, const char *string);
254253 struct phy *devm_phy_get(struct device *dev, const char *string);
255254 struct phy *devm_phy_optional_get(struct device *dev, const char *string);
256255 struct phy *devm_of_phy_get(struct device *dev, struct device_node *np,
257256 const char *con_id);
257+struct phy *devm_of_phy_optional_get(struct device *dev, struct device_node *np,
258+ const char *con_id);
258259 struct phy *devm_of_phy_get_by_index(struct device *dev, struct device_node *np,
259260 int index);
260261 void of_phy_put(struct phy *phy);
@@ -426,12 +427,6 @@ static inline struct phy *phy_get(struct device *dev, const char *string) · 165 unmodified lines
426427 return ERR_PTR(-ENOSYS);
427428 }
428429
429−static inline struct phy *phy_optional_get(struct device *dev,
430− const char *string)
431−{
432− return ERR_PTR(-ENOSYS);
433−}
434−
435430 static inline struct phy *devm_phy_get(struct device *dev, const char *string)
436431 {
437432 return ERR_PTR(-ENOSYS);
@@ -450,6 +445,13 @@ static inline struct phy *devm_of_phy_get(struct device *dev, · 12 unmodified lines
450445 return ERR_PTR(-ENOSYS);
451446 }
452447
448+static inline struct phy *devm_of_phy_optional_get(struct device *dev,
449+ struct device_node *np,
450+ const char *con_id)
451+{
452+ return NULL;
453+}
454+
453455 static inline struct phy *devm_of_phy_get_by_index(struct device *dev,
454456 struct device_node *np,
455457 int index)

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