History

Merge tag 'tty-5.19-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/tty

Pull tty and serial driver updates from Greg KH: "Here is the big set of tty and serial driver updates for 5.19-rc1. Lots of tiny cleanups in here, the major stuff is: - termbit cleanups and unification by Ilpo. A much needed change that goes a long way to making things simpler for all of the different arches - tty documentation cleanups and movements to their own place in the documentation tree - old tty driver cleanups and fixes from Jiri to bring some existing drivers into the modern world - RS485 cleanups and unifications to make it easier for individual drivers to support this mode instead of having to duplicate logic in each driver - Lots of 8250 driver updates and additions - new device id additions - n_gsm continued fixes and cleanups - other minor serial driver updates and cleanups All of these have been in linux-next for weeks with no reported issues" * tag 'tty-5.19-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/tty: (166 commits) tty: Rework receive flow control char logic pcmcia: synclink_cs: Don't allow CS5-6 serial: stm32-usart: Correct CSIZE, bits, and parity serial: st-asc: Sanitize CSIZE and correct PARENB for CS7 serial: sifive: Sanitize CSIZE and c_iflag serial: sh-sci: Don't allow CS5-6 serial: txx9: Don't allow CS5-6 serial: rda-uart: Don't allow CS5-6 serial: digicolor-usart: Don't allow CS5-6 serial: uartlite: Fix BRKINT clearing serial: cpm_uart: Fix build error without CONFIG_SERIAL_CPM_CONSOLE serial: core: Do stop_rx in suspend path for console if console_suspend is disabled tty: serial: qcom-geni-serial: Remove uart frequency table. Instead, find suitable frequency with call to clk_round_rate. dt-bindings: serial: renesas,em-uart: Add RZ/V2M clock to access the registers serial: 8250_fintek: Check SER_RS485_RTS_* only with RS485 Revert "serial: 8250_mtk: Make sure to select the right FEATURE_SEL" serial: msm_serial: disable interrupts in __msm_console_write() serial: meson: acquire port->lock in startup() serial: 8250_dw: Use dev_err_probe() serial: 8250_dw: Use devm_add_action_or_reset() ...

Linus Torvalds committed 4 years ago

Commit 932c2982 parents 4ad680f 25e02ba114 files · +3164 −2451Browse files

Unified · Split

114 files
  1. Documentation/devicetree/bindings/serial/fsl-lpuart.yaml +3 −1
  2. Documentation/devicetree/bindings/serial/qcom,serial-geni-qcom.yaml +86 −0
  3. Documentation/devicetree/bindings/serial/renesas,em-uart.yaml +31 −6
  4. Documentation/devicetree/bindings/serial/renesas,hscif.yaml +8 −1
  5. Documentation/devicetree/bindings/serial/renesas,scif.yaml +1 −1
  6. Documentation/devicetree/bindings/serial/rs485.yaml +5 −0
  7. Documentation/devicetree/bindings/serial/socionext,uniphier-uart.yaml +4 −1
  8. Documentation/driver-api/index.rst +1 −0
  9. Documentation/driver-api/serial/driver.rst +1 −1
  10. Documentation/driver-api/serial/index.rst +0 −2
  11. Documentation/driver-api/serial/n_gsm.rst +0 −159
  12. Documentation/driver-api/tty/index.rst +16 −6
  13. Documentation/driver-api/tty/moxa-smartio.rst +0 −0
  14. Documentation/driver-api/tty/n_gsm.rst +153 −0
  15. Documentation/driver-api/tty/n_tty.rst +0 −0
  16. Documentation/driver-api/tty/tty_buffer.rst +0 −0
  17. Documentation/driver-api/tty/tty_driver.rst +0 −0
  18. Documentation/driver-api/tty/tty_internals.rst +0 −0
  19. Documentation/driver-api/tty/tty_ldisc.rst +0 −0
  20. Documentation/driver-api/tty/tty_port.rst +0 −0
  21. Documentation/driver-api/tty/tty_struct.rst +0 −0
  22. Documentation/firmware-guide/acpi/enumeration.rst +25 −0
  23. Documentation/index.rst +0 −1
  24. Documentation/misc-devices/index.rst +1 −0
  25. Documentation/misc-devices/oxsemi-tornado.rst +131 −0
  26. MAINTAINERS +1 −1
  27. arch/alpha/include/uapi/asm/termbits.h +79 −135
  28. arch/mips/include/uapi/asm/termbits.h +99 −150
  29. arch/parisc/include/uapi/asm/termbits.h +94 −147
  30. arch/powerpc/include/uapi/asm/termbits.h +64 −118
  31. arch/sparc/include/uapi/asm/termbits.h +84 −139
  32. drivers/char/Kconfig +2 −1
  33. drivers/char/pcmcia/synclink_cs.c +5 −3
  34. drivers/char/ttyprintk.c +16 −0
  35. drivers/tty/amiserial.c +0 −2
  36. drivers/tty/goldfish.c +2 −0
  37. drivers/tty/hvc/Kconfig +19 −0
  38. drivers/tty/hvc/hvc_dcc.c +190 −4
  39. drivers/tty/hvc/hvc_opal.c +3 −3
  40. drivers/tty/hvc/hvc_vio.c +1 −1
  41. drivers/tty/hvc/hvcs.c +2 −3
  42. drivers/tty/hvc/hvsi.c +1 −1
  43. drivers/tty/mxser.c +2 −3
  44. drivers/tty/n_gsm.c +24 −13
  45. drivers/tty/n_tty.c +61 −12
  46. drivers/tty/serial/8250/8250.h +41 −0
  47. drivers/tty/serial/8250/8250_aspeed_vuart.c +2 −0
  48. drivers/tty/serial/8250/8250_core.c +0 −1
  49. drivers/tty/serial/8250/8250_dma.c +5 −2
  50. drivers/tty/serial/8250/8250_dw.c +149 −80
  51. drivers/tty/serial/8250/8250_dwlib.c +96 −20
  52. drivers/tty/serial/8250/8250_dwlib.h +51 −0
  53. drivers/tty/serial/8250/8250_fintek.c +4 −4
  54. drivers/tty/serial/8250/8250_mtk.c +0 −7
  55. drivers/tty/serial/8250/8250_of.c +2 −0
  56. drivers/tty/serial/8250/8250_pci.c +335 −145
  57. drivers/tty/serial/8250/8250_port.c +98 −42
  58. drivers/tty/serial/8250/8250_pxa.c +0 −1
  59. drivers/tty/serial/8250/Kconfig +1 −1
  60. drivers/tty/serial/Kconfig +5 −4
  61. drivers/tty/serial/altera_jtaguart.c +2 −4
  62. drivers/tty/serial/amba-pl011.c +31 −17
  63. drivers/tty/serial/amba-pl011.h +0 −35
  64. drivers/tty/serial/atmel_serial.c +1 −3
  65. drivers/tty/serial/cpm_uart/cpm_uart.h +2 −0
  66. drivers/tty/serial/cpm_uart/cpm_uart_core.c +1 −1
  67. drivers/tty/serial/cpm_uart/cpm_uart_cpm2.c +0 −1
  68. drivers/tty/serial/digicolor-usart.c +2 −0
  69. drivers/tty/serial/fsl_lpuart.c +8 −58
  70. drivers/tty/serial/icom.c +386 −152
  71. drivers/tty/serial/icom.h +0 −274
  72. drivers/tty/serial/imx.c +0 −2
  73. drivers/tty/serial/jsm/jsm_cls.c +1 −7
  74. drivers/tty/serial/jsm/jsm_neo.c +1 −7
  75. drivers/tty/serial/max310x.c +0 −1
  76. drivers/tty/serial/men_z135_uart.c +0 −1
  77. drivers/tty/serial/meson_uart.c +37 −3
  78. drivers/tty/serial/mpc52xx_uart.c +2 −3
  79. drivers/tty/serial/msm_serial.c +5 −0
  80. drivers/tty/serial/omap-serial.c +3 −10
  81. drivers/tty/serial/owl-uart.c +4 −3
  82. drivers/tty/serial/pch_uart.c +12 −65
  83. drivers/tty/serial/pic32_uart.c +116 −43
  84. drivers/tty/serial/pic32_uart.h +0 −125
  85. drivers/tty/serial/pmac_zilog.c +2 −67
  86. drivers/tty/serial/pmac_zilog.h +0 −11
  87. drivers/tty/serial/qcom_geni_serial.c +37 −21
  88. drivers/tty/serial/rda-uart.c +2 −0
  89. drivers/tty/serial/sa1100.c +2 −2
  90. drivers/tty/serial/samsung_tty.c +13 −0
  91. drivers/tty/serial/sc16is7xx.c +0 −10
  92. drivers/tty/serial/serial_core.c +69 −20
  93. drivers/tty/serial/serial_txx9.c +2 −0
  94. drivers/tty/serial/sh-sci.c +5 −1
  95. drivers/tty/serial/sifive.c +11 −9
  96. drivers/tty/serial/st-asc.c +4 −0
  97. drivers/tty/serial/stm32-usart.c +187 −38
  98. drivers/tty/serial/stm32-usart.h +3 −0
  99. drivers/tty/serial/sunplus-uart.c +1 −1
  100. drivers/tty/serial/sunsu.c +0 −2
  101. drivers/tty/serial/uartlite.c +2 −1
  102. drivers/tty/serial/xilinx_uartps.c +16 −30
  103. drivers/tty/serial/zs.c +1 −1
  104. drivers/tty/synclink_gt.c +2 −0
  105. drivers/tty/sysrq.c +15 −12
  106. drivers/tty/tty_baudrate.c +8 −27
  107. drivers/tty/tty_ioctl.c +0 −2
  108. drivers/usb/class/cdc-acm.h +0 −8
  109. drivers/usb/serial/ark3116.c +1 −2
  110. drivers/usb/serial/whiteheat.c +0 −4
  111. include/linux/serial_core.h +1 −0
  112. include/linux/serial_s3c.h +3 −0
  113. include/uapi/asm-generic/termbits-common.h +65 −0
  114. include/uapi/asm-generic/termbits.h +94 −145
Documentation/devicetree/bindings/serial/fsl-lpuart.yaml+3−1
@@ -23,7 +23,9 @@ properties: · 22 unmodified lines
2323 - fsl,imx8qxp-lpuart
2424 - fsl,imxrt1050-lpuart
2525 - items:
26− - const: fsl,imx8ulp-lpuart
26+ - enum:
27+ - fsl,imx93-lpuart
28+ - fsl,imx8ulp-lpuart
2729 - const: fsl,imx7ulp-lpuart
2830 - items:
2931 - enum:
Documentation/devicetree/bindings/serial/qcom,serial-geni-qcom.yaml+86−0
@@ -0,0 +1,86 @@
1+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2+%YAML 1.2
3+---
4+$id: "http://devicetree.org/schemas/serial/qcom,serial-geni-qcom.yaml#"
5+$schema: "http://devicetree.org/meta-schemas/core.yaml#"
6+
7+title: Qualcomm Geni based QUP UART interface
8+
9+maintainers:
10+ - Andy Gross <agross@kernel.org>
11+ - Bjorn Andersson <bjorn.andersson@linaro.org>
12+
13+allOf:
14+ - $ref: /schemas/serial/serial.yaml#
15+
16+properties:
17+ compatible:
18+ enum:
19+ - qcom,geni-uart
20+ - qcom,geni-debug-uart
21+
22+ clocks:
23+ maxItems: 1
24+
25+ clock-names:
26+ const: se
27+
28+ interconnects:
29+ maxItems: 2
30+
31+ interconnect-names:
32+ items:
33+ - const: qup-core
34+ - const: qup-config
35+
36+ interrupts:
37+ minItems: 1
38+ items:
39+ - description: UART core irq
40+ - description: Wakeup irq (RX GPIO)
41+
42+ operating-points-v2: true
43+
44+ pinctrl-0: true
45+ pinctrl-1: true
46+
47+ pinctrl-names:
48+ minItems: 1
49+ items:
50+ - const: default
51+ - const: sleep
52+
53+ power-domains:
54+ maxItems: 1
55+
56+ reg:
57+ maxItems: 1
58+
59+required:
60+ - compatible
61+ - clocks
62+ - clock-names
63+ - interrupts
64+ - reg
65+
66+unevaluatedProperties: false
67+
68+examples:
69+ - |
70+ #include <dt-bindings/interrupt-controller/arm-gic.h>
71+ #include <dt-bindings/clock/qcom,gcc-sc7180.h>
72+ #include <dt-bindings/interconnect/qcom,sc7180.h>
73+
74+ serial@a88000 {
75+ compatible = "qcom,geni-uart";
76+ reg = <0xa88000 0x7000>;
77+ interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
78+ clock-names = "se";
79+ clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
80+ pinctrl-0 = <&qup_uart0_default>;
81+ pinctrl-names = "default";
82+ interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
83+ <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>;
84+ interconnect-names = "qup-core", "qup-config";
85+ };
86+...
Documentation/devicetree/bindings/serial/renesas,em-uart.yaml+31−6
@@ -9,12 +9,16 @@ title: Renesas EMMA Mobile UART Interface · 8 unmodified lines
99 maintainers:
1010 - Magnus Damm <magnus.damm@gmail.com>
1111
12−allOf:
13− - $ref: serial.yaml#
14−
1512 properties:
1613 compatible:
17− const: renesas,em-uart
14+ oneOf:
15+ - items:
16+ - enum:
17+ - renesas,r9a09g011-uart # RZ/V2M
18+ - const: renesas,em-uart # generic EMMA Mobile compatible UART
19+
20+ - items:
21+ - const: renesas,em-uart # generic EMMA Mobile compatible UART
1822
1923 reg:
2024 maxItems: 1
@@ -23,10 +27,31 @@ properties: · 2 unmodified lines
2327 maxItems: 1
2428
2529 clocks:
26− maxItems: 1
30+ minItems: 1
31+ items:
32+ - description: UART functional clock
33+ - description: Internal clock to access the registers
2734
2835 clock-names:
29− const: sclk
36+ minItems: 1
37+ items:
38+ - const: sclk
39+ - const: pclk
40+
41+allOf:
42+ - $ref: serial.yaml#
43+
44+ - if:
45+ properties:
46+ compatible:
47+ contains:
48+ const: renesas,r9a09g011-uart
49+ then:
50+ properties:
51+ clocks:
52+ minItems: 2
53+ clock-names:
54+ minItems: 2
3055
3156 required:
3257 - compatible
Documentation/devicetree/bindings/serial/renesas,hscif.yaml+8−1
@@ -51,10 +51,16 @@ properties: · 50 unmodified lines
5151 - renesas,hscif-r8a77980 # R-Car V3H
5252 - renesas,hscif-r8a77990 # R-Car E3
5353 - renesas,hscif-r8a77995 # R-Car D3
54− - renesas,hscif-r8a779a0 # R-Car V3U
5554 - const: renesas,rcar-gen3-hscif # R-Car Gen3 and RZ/G2
5655 - const: renesas,hscif # generic HSCIF compatible UART
5756
57+ - items:
58+ - enum:
59+ - renesas,hscif-r8a779a0 # R-Car V3U
60+ - renesas,hscif-r8a779g0 # R-Car V4H
61+ - const: renesas,rcar-gen4-hscif # R-Car Gen4
62+ - const: renesas,hscif # generic HSCIF compatible UART
63+
5864 reg:
5965 maxItems: 1
6066
@@ -113,6 +119,7 @@ if: · 52 unmodified lines
113119 enum:
114120 - renesas,rcar-gen2-hscif
115121 - renesas,rcar-gen3-hscif
122+ - renesas,rcar-gen4-hscif
116123 then:
117124 required:
118125 - resets
Documentation/devicetree/bindings/serial/renesas,scif.yaml+1−1
@@ -60,12 +60,12 @@ properties: · 59 unmodified lines
6060 - renesas,scif-r8a77980 # R-Car V3H
6161 - renesas,scif-r8a77990 # R-Car E3
6262 - renesas,scif-r8a77995 # R-Car D3
63− - renesas,scif-r8a779a0 # R-Car V3U
6463 - const: renesas,rcar-gen3-scif # R-Car Gen3 and RZ/G2
6564 - const: renesas,scif # generic SCIF compatible UART
6665
6766 - items:
6867 - enum:
68+ - renesas,scif-r8a779a0 # R-Car V3U
6969 - renesas,scif-r8a779f0 # R-Car S4-8
7070 - const: renesas,rcar-gen4-scif # R-Car Gen4
7171 - const: renesas,scif # generic SCIF compatible UART
Documentation/devicetree/bindings/serial/rs485.yaml+5−0
@@ -33,6 +33,11 @@ properties: · 32 unmodified lines
3333 description: drive RTS low when sending (default is high).
3434 $ref: /schemas/types.yaml#/definitions/flag
3535
36+ rs485-rx-active-high:
37+ description: Polarity of receiver enable signal (when separate from RTS).
38+ True indicates active high (default is low).
39+ $ref: /schemas/types.yaml#/definitions/flag
40+
3641 linux,rs485-enabled-at-boot-time:
3742 description: enables the rs485 feature at boot time. It can be disabled
3843 later with proper ioctl.
Documentation/devicetree/bindings/serial/socionext,uniphier-uart.yaml+4−1
@@ -20,7 +20,10 @@ properties: · 19 unmodified lines
2020 maxItems: 1
2121
2222 clocks:
23− minItems: 1
23+ maxItems: 1
24+
25+ resets:
26+ maxItems: 1
2427
2528 auto-flow-control:
2629 description: enable automatic flow control support.
Documentation/driver-api/index.rst+1−0
@@ -101,6 +101,7 @@ available subsections can be seen below. · 100 unmodified lines
101101 surface_aggregator/index
102102 switchtec
103103 sync_file
104+ tty/index
104105 vfio-mediated-device
105106 vfio
106107 vfio-pci-device-specific-driver-acceptance
Documentation/driver-api/serial/driver.rst+1−1
@@ -311,7 +311,7 @@ hardware. · 310 unmodified lines
311311 This call must not sleep
312312
313313 set_ldisc(port,termios)
314− Notifier for discipline change. See Documentation/tty/tty_ldisc.rst.
314+ Notifier for discipline change. See ../tty/tty_ldisc.rst.
315315
316316 Locking: caller holds tty_port->mutex
317317
Documentation/driver-api/serial/index.rst+0−2
@@ -16,8 +16,6 @@ Serial drivers · 15 unmodified lines
1616 .. toctree::
1717 :maxdepth: 1
1818
19− moxa-smartio
20− n_gsm
2119 serial-iso7816
2220 serial-rs485
2321
Documentation/driver-api/serial/n_gsm.rst+0−159
@@ -1,159 +0,0 @@
1−==============================
2−GSM 0710 tty multiplexor HOWTO
3−==============================
4−
5−This line discipline implements the GSM 07.10 multiplexing protocol
6−detailed in the following 3GPP document:
7−
8− https://www.3gpp.org/ftp/Specs/archive/07_series/07.10/0710-720.zip
9−
10−This document give some hints on how to use this driver with GPRS and 3G
11−modems connected to a physical serial port.
12−
13−How to use it
14−-------------
15−1. config initiator
16−^^^^^^^^^^^^^^^^^^^^^
17−
18−1.1 initialize the modem in 0710 mux mode (usually AT+CMUX= command) through
19− its serial port. Depending on the modem used, you can pass more or less
20− parameters to this command.
21−
22−1.2 switch the serial line to using the n_gsm line discipline by using
23− TIOCSETD ioctl.
24−
25−1.3 configure the mux using GSMIOC_GETCONF / GSMIOC_SETCONF ioctl.
26−
27−1.4 obtain base gsmtty number for the used serial port.
28−
29−Major parts of the initialization program :
30−(a good starting point is util-linux-ng/sys-utils/ldattach.c)::
31−
32− #include <stdio.h>
33− #include <stdint.h>
34− #include <linux/gsmmux.h>
35− #include <linux/tty.h>
36− #define DEFAULT_SPEED B115200
37− #define SERIAL_PORT /dev/ttyS0
38−
39− int ldisc = N_GSM0710;
40− struct gsm_config c;
41− struct termios configuration;
42− uint32_t first;
43−
44− /* open the serial port connected to the modem */
45− fd = open(SERIAL_PORT, O_RDWR | O_NOCTTY | O_NDELAY);
46−
47− /* configure the serial port : speed, flow control ... */
48−
49− /* send the AT commands to switch the modem to CMUX mode
50− and check that it's successful (should return OK) */
51− write(fd, "AT+CMUX=0\r", 10);
52−
53− /* experience showed that some modems need some time before
54− being able to answer to the first MUX packet so a delay
55− may be needed here in some case */
56− sleep(3);
57−
58− /* use n_gsm line discipline */
59− ioctl(fd, TIOCSETD, &ldisc);
60−
61− /* get n_gsm configuration */
62− ioctl(fd, GSMIOC_GETCONF, &c);
63− /* we are initiator and need encoding 0 (basic) */
64− c.initiator = 1;
65− c.encapsulation = 0;
66− /* our modem defaults to a maximum size of 127 bytes */
67− c.mru = 127;
68− c.mtu = 127;
69− /* set the new configuration */
70− ioctl(fd, GSMIOC_SETCONF, &c);
71− /* get first gsmtty device node */
72− ioctl(fd, GSMIOC_GETFIRST, &first);
73− printf("first muxed line: /dev/gsmtty%i\n", first);
74−
75− /* and wait for ever to keep the line discipline enabled */
76− daemon(0,0);
77− pause();
78−
79−1.5 use these devices as plain serial ports.
80−
81− for example, it's possible:
82−
83− - and to use gnokii to send / receive SMS on ttygsm1
84− - to use ppp to establish a datalink on ttygsm2
85−
86−1.6 first close all virtual ports before closing the physical port.
87−
88− Note that after closing the physical port the modem is still in multiplexing
89− mode. This may prevent a successful re-opening of the port later. To avoid
90− this situation either reset the modem if your hardware allows that or send
91− a disconnect command frame manually before initializing the multiplexing mode
92− for the second time. The byte sequence for the disconnect command frame is::
93−
94− 0xf9, 0x03, 0xef, 0x03, 0xc3, 0x16, 0xf9.
95−
96−2. config requester
97−^^^^^^^^^^^^^^^^^^^^^
98−
99−2.1 receive string "AT+CMUX= command" through its serial port,initialize
100− mux mode config
101−
102−2.2 switch the serial line to using the n_gsm line discipline by using
103− TIOCSETD ioctl.
104−
105−2.3 configure the mux using GSMIOC_GETCONF / GSMIOC_SETCONF ioctl.
106−
107−2.4 obtain base gsmtty number for the used serial port::
108−
109− #include <stdio.h>
110− #include <stdint.h>
111− #include <linux/gsmmux.h>
112− #include <linux/tty.h>
113− #define DEFAULT_SPEED B115200
114− #define SERIAL_PORT /dev/ttyS0
115−
116− int ldisc = N_GSM0710;
117− struct gsm_config c;
118− struct termios configuration;
119− uint32_t first;
120−
121− /* open the serial port */
122− fd = open(SERIAL_PORT, O_RDWR | O_NOCTTY | O_NDELAY);
123−
124− /* configure the serial port : speed, flow control ... */
125−
126− /* get serial data and check "AT+CMUX=command" parameter ... */
127−
128− /* use n_gsm line discipline */
129− ioctl(fd, TIOCSETD, &ldisc);
130−
131− /* get n_gsm configuration */
132− ioctl(fd, GSMIOC_GETCONF, &c);
133− /* we are requester and need encoding 0 (basic) */
134− c.initiator = 0;
135− c.encapsulation = 0;
136− /* our modem defaults to a maximum size of 127 bytes */
137− c.mru = 127;
138− c.mtu = 127;
139− /* set the new configuration */
140− ioctl(fd, GSMIOC_SETCONF, &c);
141− /* get first gsmtty device node */
142− ioctl(fd, GSMIOC_GETFIRST, &first);
143− printf("first muxed line: /dev/gsmtty%i\n", first);
144−
145− /* and wait for ever to keep the line discipline enabled */
146− daemon(0,0);
147− pause();
148−
149−Additional Documentation
150−------------------------
151−More practical details on the protocol and how it's supported by industrial
152−modems can be found in the following documents :
153−
154−- http://www.telit.com/module/infopool/download.php?id=616
155−- http://www.u-blox.com/images/downloads/Product_Docs/LEON-G100-G200-MuxImplementation_ApplicationNote_%28GSM%20G1-CS-10002%29.pdf
156−- http://www.sierrawireless.com/Support/Downloads/AirPrime/WMP_Series/~/media/Support_Downloads/AirPrime/Application_notes/CMUX_Feature_Application_Note-Rev004.ashx
157−- http://wm.sim.com/sim/News/photo/2010721161442.pdf
158−
159−11-03-08 - Eric Bénard - <eric@eukrea.com>
Documentation/driver-api/tty/index.rstrenamed from Documentation/tty/index.rst+16−6
@@ -36,18 +36,16 @@ In-detail description of the named TTY structures is in separate documents: · 35 unmodified lines
3636 tty_struct
3737 tty_ldisc
3838 tty_buffer
39− n_tty
4039 tty_internals
4140
4241 Writing TTY Driver
4342 ==================
4443
4544 Before one starts writing a TTY driver, they must consider
46−:doc:`Serial <../driver-api/serial/driver>` and :doc:`USB Serial
47−<../usb/usb-serial>` layers
48−first. Drivers for serial devices can often use one of these specific layers to
49−implement a serial driver. Only special devices should be handled directly by
50−the TTY Layer. If you are about to write such a driver, read on.
45+:doc:`Serial <../serial/driver>` and :doc:`USB Serial <../../usb/usb-serial>`
46+layers first. Drivers for serial devices can often use one of these specific
47+layers to implement a serial driver. Only special devices should be handled
48+directly by the TTY Layer. If you are about to write such a driver, read on.
5149
5250 A *typical* sequence a TTY driver performs is as follows:
5351
@@ -61,3 +59,15 @@ A *typical* sequence a TTY driver performs is as follows: · 7 unmodified lines
6159 Steps regarding driver, i.e. 1., 3., and 5. are described in detail in
6260 :doc:`tty_driver`. For the other two (devices handling), look into
6361 :doc:`tty_port`.
62+
63+Other Documentation
64+===================
65+
66+Miscellaneous documentation can be further found in these documents:
67+
68+.. toctree::
69+ :maxdepth: 2
70+
71+ moxa-smartio
72+ n_gsm
73+ n_tty
Documentation/driver-api/tty/moxa-smartio.rstrenamed from Documentation/driver-api/serial/moxa-smartio.rst+0−0

File renamed without changes.

Documentation/driver-api/tty/n_gsm.rst+153−0
@@ -0,0 +1,153 @@
1+==============================
2+GSM 0710 tty multiplexor HOWTO
3+==============================
4+
5+.. contents:: :local:
6+
7+This line discipline implements the GSM 07.10 multiplexing protocol
8+detailed in the following 3GPP document:
9+
10+ https://www.3gpp.org/ftp/Specs/archive/07_series/07.10/0710-720.zip
11+
12+This document give some hints on how to use this driver with GPRS and 3G
13+modems connected to a physical serial port.
14+
15+How to use it
16+=============
17+
18+Config Initiator
19+----------------
20+
21+#. Initialize the modem in 0710 mux mode (usually ``AT+CMUX=`` command) through
22+ its serial port. Depending on the modem used, you can pass more or less
23+ parameters to this command.
24+
25+#. Switch the serial line to using the n_gsm line discipline by using
26+ ``TIOCSETD`` ioctl.
27+
28+#. Configure the mux using ``GSMIOC_GETCONF``/``GSMIOC_SETCONF`` ioctl.
29+
30+#. Obtain base gsmtty number for the used serial port.
31+
32+ Major parts of the initialization program
33+ (a good starting point is util-linux-ng/sys-utils/ldattach.c)::
34+
35+ #include <stdio.h>
36+ #include <stdint.h>
37+ #include <linux/gsmmux.h>
38+ #include <linux/tty.h>
39+
40+ #define DEFAULT_SPEED B115200
41+ #define SERIAL_PORT /dev/ttyS0
42+
43+ int ldisc = N_GSM0710;
44+ struct gsm_config c;
45+ struct termios configuration;
46+ uint32_t first;
47+
48+ /* open the serial port connected to the modem */
49+ fd = open(SERIAL_PORT, O_RDWR | O_NOCTTY | O_NDELAY);
50+
51+ /* configure the serial port : speed, flow control ... */
52+
53+ /* send the AT commands to switch the modem to CMUX mode
54+ and check that it's successful (should return OK) */
55+ write(fd, "AT+CMUX=0\r", 10);
56+
57+ /* experience showed that some modems need some time before
58+ being able to answer to the first MUX packet so a delay
59+ may be needed here in some case */
60+ sleep(3);
61+
62+ /* use n_gsm line discipline */
63+ ioctl(fd, TIOCSETD, &ldisc);
64+
65+ /* get n_gsm configuration */
66+ ioctl(fd, GSMIOC_GETCONF, &c);
67+ /* we are initiator and need encoding 0 (basic) */
68+ c.initiator = 1;
69+ c.encapsulation = 0;
70+ /* our modem defaults to a maximum size of 127 bytes */
71+ c.mru = 127;
72+ c.mtu = 127;
73+ /* set the new configuration */
74+ ioctl(fd, GSMIOC_SETCONF, &c);
75+ /* get first gsmtty device node */
76+ ioctl(fd, GSMIOC_GETFIRST, &first);
77+ printf("first muxed line: /dev/gsmtty%i\n", first);
78+
79+ /* and wait for ever to keep the line discipline enabled */
80+ daemon(0,0);
81+ pause();
82+
83+#. Use these devices as plain serial ports.
84+
85+ For example, it's possible:
86+
87+ - to use *gnokii* to send / receive SMS on ``ttygsm1``
88+ - to use *ppp* to establish a datalink on ``ttygsm2``
89+
90+#. First close all virtual ports before closing the physical port.
91+
92+ Note that after closing the physical port the modem is still in multiplexing
93+ mode. This may prevent a successful re-opening of the port later. To avoid
94+ this situation either reset the modem if your hardware allows that or send
95+ a disconnect command frame manually before initializing the multiplexing mode
96+ for the second time. The byte sequence for the disconnect command frame is::
97+
98+ 0xf9, 0x03, 0xef, 0x03, 0xc3, 0x16, 0xf9
99+
100+Config Requester
101+----------------
102+
103+#. Receive ``AT+CMUX=`` command through its serial port, initialize mux mode
104+ config.
105+
106+#. Switch the serial line to using the *n_gsm* line discipline by using
107+ ``TIOCSETD`` ioctl.
108+
109+#. Configure the mux using ``GSMIOC_GETCONF``/``GSMIOC_SETCONF`` ioctl.
110+
111+#. Obtain base gsmtty number for the used serial port::
112+
113+ #include <stdio.h>
114+ #include <stdint.h>
115+ #include <linux/gsmmux.h>
116+ #include <linux/tty.h>
117+ #define DEFAULT_SPEED B115200
118+ #define SERIAL_PORT /dev/ttyS0
119+
120+ int ldisc = N_GSM0710;
121+ struct gsm_config c;
122+ struct termios configuration;
123+ uint32_t first;
124+
125+ /* open the serial port */
126+ fd = open(SERIAL_PORT, O_RDWR | O_NOCTTY | O_NDELAY);
127+
128+ /* configure the serial port : speed, flow control ... */
129+
130+ /* get serial data and check "AT+CMUX=command" parameter ... */
131+
132+ /* use n_gsm line discipline */
133+ ioctl(fd, TIOCSETD, &ldisc);
134+
135+ /* get n_gsm configuration */
136+ ioctl(fd, GSMIOC_GETCONF, &c);
137+ /* we are requester and need encoding 0 (basic) */
138+ c.initiator = 0;
139+ c.encapsulation = 0;
140+ /* our modem defaults to a maximum size of 127 bytes */
141+ c.mru = 127;
142+ c.mtu = 127;
143+ /* set the new configuration */
144+ ioctl(fd, GSMIOC_SETCONF, &c);
145+ /* get first gsmtty device node */
146+ ioctl(fd, GSMIOC_GETFIRST, &first);
147+ printf("first muxed line: /dev/gsmtty%i\n", first);
148+
149+ /* and wait for ever to keep the line discipline enabled */
150+ daemon(0,0);
151+ pause();
152+
153+11-03-08 - Eric Bénard - <eric@eukrea.com>
Documentation/driver-api/tty/n_tty.rstrenamed from Documentation/tty/n_tty.rst+0−0

File renamed without changes.

Documentation/driver-api/tty/tty_buffer.rstrenamed from Documentation/tty/tty_buffer.rst+0−0

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Documentation/driver-api/tty/tty_driver.rstrenamed from Documentation/tty/tty_driver.rst+0−0

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Documentation/driver-api/tty/tty_internals.rstrenamed from Documentation/tty/tty_internals.rst+0−0

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Documentation/driver-api/tty/tty_ldisc.rstrenamed from Documentation/tty/tty_ldisc.rst+0−0

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Documentation/driver-api/tty/tty_port.rstrenamed from Documentation/tty/tty_port.rst+0−0

File renamed without changes.

Documentation/driver-api/tty/tty_struct.rstrenamed from Documentation/tty/tty_struct.rst+0−0

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Documentation/firmware-guide/acpi/enumeration.rst+25−0
@@ -389,6 +389,31 @@ descriptors once the device is released. · 388 unmodified lines
389389 See Documentation/firmware-guide/acpi/gpio-properties.rst for more information
390390 about the _DSD binding related to GPIOs.
391391
392+RS-485 support
393+==============
394+
395+ACPI _DSD (Device Specific Data) can be used to describe RS-485 capability
396+of UART.
397+
398+For example::
399+
400+ Device (DEV)
401+ {
402+ ...
403+
404+ // ACPI 5.1 _DSD used for RS-485 capabilities
405+ Name (_DSD, Package ()
406+ {
407+ ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
408+ Package ()
409+ {
410+ Package () {"rs485-rts-active-low", Zero},
411+ Package () {"rs485-rx-active-high", Zero},
412+ Package () {"rs485-rx-during-tx", Zero},
413+ }
414+ })
415+ ...
416+
392417 MFD devices
393418 ===========
394419
Documentation/index.rst+0−1
@@ -136,7 +136,6 @@ needed). · 135 unmodified lines
136136 misc-devices/index
137137 scheduler/index
138138 mhi/index
139− tty/index
140139 peci/index
141140
142141 Architecture-agnostic documentation
Documentation/misc-devices/index.rst+1−0
@@ -25,6 +25,7 @@ fit into other categories. · 24 unmodified lines
2525 isl29003
2626 lis3lv02d
2727 max6875
28+ oxsemi-tornado
2829 pci-endpoint-test
2930 spear-pcie-gadget
3031 uacce
Documentation/misc-devices/oxsemi-tornado.rst+131−0
@@ -0,0 +1,131 @@
1+.. SPDX-License-Identifier: GPL-2.0
2+
3+====================================================================
4+Notes on Oxford Semiconductor PCIe (Tornado) 950 serial port devices
5+====================================================================
6+
7+Oxford Semiconductor PCIe (Tornado) 950 serial port devices are driven
8+by a fixed 62.5MHz clock input derived from the 100MHz PCI Express clock.
9+
10+The baud rate produced by the baud generator is obtained from this input
11+frequency by dividing it by the clock prescaler, which can be set to any
12+value from 1 to 63.875 in increments of 0.125, and then the usual 16-bit
13+divisor is used as with the original 8250, to divide the frequency by a
14+value from 1 to 65535. Finally a programmable oversampling rate is used
15+that can take any value from 4 to 16 to divide the frequency further and
16+determine the actual baud rate used. Baud rates from 15625000bps down
17+to 0.933bps can be obtained this way.
18+
19+By default the oversampling rate is set to 16 and the clock prescaler is
20+set to 33.875, meaning that the frequency to be used as the reference
21+for the usual 16-bit divisor is 115313.653, which is close enough to the
22+frequency of 115200 used by the original 8250 for the same values to be
23+used for the divisor to obtain the requested baud rates by software that
24+is unaware of the extra clock controls available.
25+
26+The oversampling rate is programmed with the TCR register and the clock
27+prescaler is programmed with the CPR/CPR2 register pair [OX200]_ [OX952]_
28+[OX954]_ [OX958]_. To switch away from the default value of 33.875 for
29+the prescaler the enhanced mode has to be explicitly enabled though, by
30+setting bit 4 of the EFR. In that mode setting bit 7 in the MCR enables
31+the prescaler or otherwise it is bypassed as if the value of 1 was used.
32+Additionally writing any value to CPR clears CPR2 for compatibility with
33+old software written for older conventional PCI Oxford Semiconductor
34+devices that do not have the extra prescaler's 9th bit in CPR2, so the
35+CPR/CPR2 register pair has to be programmed in the right order.
36+
37+By using these parameters rates from 15625000bps down to 1bps can be
38+obtained, with either exact or highly-accurate actual bit rates for
39+standard and many non-standard rates.
40+
41+Here are the figures for the standard and some non-standard baud rates
42+(including those quoted in Oxford Semiconductor documentation), giving
43+the requested rate (r), the actual rate yielded (a) and its deviation
44+from the requested rate (d), and the values of the oversampling rate
45+(tcr), the clock prescaler (cpr) and the divisor (div) produced by the
46+new ``get_divisor`` handler:
47+
48+::
49+
50+ r: 15625000, a: 15625000.00, d: 0.0000%, tcr: 4, cpr: 1.000, div: 1
51+ r: 12500000, a: 12500000.00, d: 0.0000%, tcr: 5, cpr: 1.000, div: 1
52+ r: 10416666, a: 10416666.67, d: 0.0000%, tcr: 6, cpr: 1.000, div: 1
53+ r: 8928571, a: 8928571.43, d: 0.0000%, tcr: 7, cpr: 1.000, div: 1
54+ r: 7812500, a: 7812500.00, d: 0.0000%, tcr: 8, cpr: 1.000, div: 1
55+ r: 4000000, a: 4000000.00, d: 0.0000%, tcr: 5, cpr: 3.125, div: 1
56+ r: 3686400, a: 3676470.59, d: -0.2694%, tcr: 8, cpr: 2.125, div: 1
57+ r: 3500000, a: 3496503.50, d: -0.0999%, tcr: 13, cpr: 1.375, div: 1
58+ r: 3000000, a: 2976190.48, d: -0.7937%, tcr: 14, cpr: 1.500, div: 1
59+ r: 2500000, a: 2500000.00, d: 0.0000%, tcr: 10, cpr: 2.500, div: 1
60+ r: 2000000, a: 2000000.00, d: 0.0000%, tcr: 10, cpr: 3.125, div: 1
61+ r: 1843200, a: 1838235.29, d: -0.2694%, tcr: 16, cpr: 2.125, div: 1
62+ r: 1500000, a: 1492537.31, d: -0.4975%, tcr: 5, cpr: 8.375, div: 1
63+ r: 1152000, a: 1152073.73, d: 0.0064%, tcr: 14, cpr: 3.875, div: 1
64+ r: 921600, a: 919117.65, d: -0.2694%, tcr: 16, cpr: 2.125, div: 2
65+ r: 576000, a: 576036.87, d: 0.0064%, tcr: 14, cpr: 3.875, div: 2
66+ r: 460800, a: 460829.49, d: 0.0064%, tcr: 7, cpr: 3.875, div: 5
67+ r: 230400, a: 230414.75, d: 0.0064%, tcr: 14, cpr: 3.875, div: 5
68+ r: 115200, a: 115207.37, d: 0.0064%, tcr: 14, cpr: 1.250, div: 31
69+ r: 57600, a: 57603.69, d: 0.0064%, tcr: 8, cpr: 3.875, div: 35
70+ r: 38400, a: 38402.46, d: 0.0064%, tcr: 14, cpr: 3.875, div: 30
71+ r: 19200, a: 19201.23, d: 0.0064%, tcr: 8, cpr: 3.875, div: 105
72+ r: 9600, a: 9600.06, d: 0.0006%, tcr: 9, cpr: 1.125, div: 643
73+ r: 4800, a: 4799.98, d: -0.0004%, tcr: 7, cpr: 2.875, div: 647
74+ r: 2400, a: 2400.02, d: 0.0008%, tcr: 9, cpr: 2.250, div: 1286
75+ r: 1200, a: 1200.00, d: 0.0000%, tcr: 14, cpr: 2.875, div: 1294
76+ r: 300, a: 300.00, d: 0.0000%, tcr: 11, cpr: 2.625, div: 7215
77+ r: 200, a: 200.00, d: 0.0000%, tcr: 16, cpr: 1.250, div: 15625
78+ r: 150, a: 150.00, d: 0.0000%, tcr: 13, cpr: 2.250, div: 14245
79+ r: 134, a: 134.00, d: 0.0000%, tcr: 11, cpr: 2.625, div: 16153
80+ r: 110, a: 110.00, d: 0.0000%, tcr: 12, cpr: 1.000, div: 47348
81+ r: 75, a: 75.00, d: 0.0000%, tcr: 4, cpr: 5.875, div: 35461
82+ r: 50, a: 50.00, d: 0.0000%, tcr: 16, cpr: 1.250, div: 62500
83+ r: 25, a: 25.00, d: 0.0000%, tcr: 16, cpr: 2.500, div: 62500
84+ r: 4, a: 4.00, d: 0.0000%, tcr: 16, cpr: 20.000, div: 48828
85+ r: 2, a: 2.00, d: 0.0000%, tcr: 16, cpr: 40.000, div: 48828
86+ r: 1, a: 1.00, d: 0.0000%, tcr: 16, cpr: 63.875, div: 61154
87+
88+With the baud base set to 15625000 and the unsigned 16-bit UART_DIV_MAX
89+limitation imposed by ``serial8250_get_baud_rate`` standard baud rates
90+below 300bps become unavailable in the regular way, e.g. the rate of
91+200bps requires the baud base to be divided by 78125 and that is beyond
92+the unsigned 16-bit range. The historic spd_cust feature can still be
93+used by encoding the values for, the prescaler, the oversampling rate
94+and the clock divisor (DLM/DLL) as follows to obtain such rates if so
95+required:
96+
97+::
98+
99+ 31 29 28 20 19 16 15 0
100+ +-----+-----------------+-------+-------------------------------+
101+ |0 0 0| CPR2:CPR | TCR | DLM:DLL |
102+ +-----+-----------------+-------+-------------------------------+
103+
104+Use a value such encoded for the ``custom_divisor`` field along with the
105+ASYNC_SPD_CUST flag set in the ``flags`` field in ``struct serial_struct``
106+passed with the TIOCSSERIAL ioctl(2), such as with the setserial(8)
107+utility and its ``divisor`` and ``spd_cust`` parameters, and then select
108+the baud rate of 38400bps. Note that the value of 0 in TCR sets the
109+oversampling rate to 16 and prescaler values below 1 in CPR2/CPR are
110+clamped by the driver to 1.
111+
112+For example the value of 0x1f4004e2 will set CPR2/CPR, TCR and DLM/DLL
113+respectively to 0x1f4, 0x0 and 0x04e2, choosing the prescaler value,
114+the oversampling rate and the clock divisor of 62.500, 16 and 1250
115+respectively. These parameters will set the baud rate for the serial
116+port to 62500000 / 62.500 / 1250 / 16 = 50bps.
117+
118+Maciej W. Rozycki <macro@orcam.me.uk>
119+
120+.. [OX200] "OXPCIe200 PCI Express Multi-Port Bridge", Oxford Semiconductor,
121+ Inc., DS-0045, 10 Nov 2008, Section "950 Mode", pp. 64-65
122+
123+.. [OX952] "OXPCIe952 PCI Express Bridge to Dual Serial & Parallel Port",
124+ Oxford Semiconductor, Inc., DS-0046, Mar 06 08, Section "950 Mode",
125+ p. 20
126+
127+.. [OX954] "OXPCIe954 PCI Express Bridge to Quad Serial Port", Oxford
128+ Semiconductor, Inc., DS-0047, Feb 08, Section "950 Mode", p. 20
129+
130+.. [OX958] "OXPCIe958 PCI Express Bridge to Octal Serial Port", Oxford
131+ Semiconductor, Inc., DS-0048, Feb 08, Section "950 Mode", p. 20
MAINTAINERS+1−1
@@ -13411,7 +13411,7 @@ F: drivers/net/phy/motorcomm.c · 13410 unmodified lines
1341113411 MOXA SMARTIO/INDUSTIO/INTELLIO SERIAL CARD
1341213412 M: Jiri Slaby <jirislaby@kernel.org>
1341313413 S: Maintained
13414−F: Documentation/driver-api/serial/moxa-smartio.rst
13414+F: Documentation/driver-api/tty/moxa-smartio.rst
1341513415 F: drivers/tty/mxser.*
1341613416
1341713417 MR800 AVERMEDIA USB FM RADIO DRIVER
arch/alpha/include/uapi/asm/termbits.h+79−135
@@ -2,10 +2,8 @@ · 1 unmodified line
22 #ifndef _ALPHA_TERMBITS_H
33 #define _ALPHA_TERMBITS_H
44
5−#include <linux/posix_types.h>
5+#include <asm-generic/termbits-common.h>
66
7−typedef unsigned char cc_t;
8−typedef unsigned int speed_t;
97 typedef unsigned int tcflag_t;
108
119 /*
@@ -53,76 +51,58 @@ struct ktermios { · 41 unmodified lines
5351 };
5452
5553 /* c_cc characters */
56−#define VEOF 0
57−#define VEOL 1
58−#define VEOL2 2
59−#define VERASE 3
60−#define VWERASE 4
61−#define VKILL 5
62−#define VREPRINT 6
63−#define VSWTC 7
64−#define VINTR 8
65−#define VQUIT 9
66−#define VSUSP 10
67−#define VSTART 12
68−#define VSTOP 13
69−#define VLNEXT 14
70−#define VDISCARD 15
71−#define VMIN 16
72−#define VTIME 17
54+#define VEOF 0
55+#define VEOL 1
56+#define VEOL2 2
57+#define VERASE 3
58+#define VWERASE 4
59+#define VKILL 5
60+#define VREPRINT 6
61+#define VSWTC 7
62+#define VINTR 8
63+#define VQUIT 9
64+#define VSUSP 10
65+#define VSTART 12
66+#define VSTOP 13
67+#define VLNEXT 14
68+#define VDISCARD 15
69+#define VMIN 16
70+#define VTIME 17
7371
7472 /* c_iflag bits */
75−#define IGNBRK 0000001
76−#define BRKINT 0000002
77−#define IGNPAR 0000004
78−#define PARMRK 0000010
79−#define INPCK 0000020
80−#define ISTRIP 0000040
81−#define INLCR 0000100
82−#define IGNCR 0000200
83−#define ICRNL 0000400
84−#define IXON 0001000
85−#define IXOFF 0002000
86−#define IXANY 0004000
87−#define IUCLC 0010000
88−#define IMAXBEL 0020000
89−#define IUTF8 0040000
73+#define IXON 0x0200
74+#define IXOFF 0x0400
75+#define IUCLC 0x1000
76+#define IMAXBEL 0x2000
77+#define IUTF8 0x4000
9078
9179 /* c_oflag bits */
92−#define OPOST 0000001
93−#define ONLCR 0000002
94−#define OLCUC 0000004
95−
96−#define OCRNL 0000010
97−#define ONOCR 0000020
98−#define ONLRET 0000040
99−
100−#define OFILL 00000100
101−#define OFDEL 00000200
102−#define NLDLY 00001400
103−#define NL0 00000000
104−#define NL1 00000400
105−#define NL2 00001000
106−#define NL3 00001400
107−#define TABDLY 00006000
108−#define TAB0 00000000
109−#define TAB1 00002000
110−#define TAB2 00004000
111−#define TAB3 00006000
112−#define CRDLY 00030000
113−#define CR0 00000000
114−#define CR1 00010000
115−#define CR2 00020000
116−#define CR3 00030000
117−#define FFDLY 00040000
118−#define FF0 00000000
119−#define FF1 00040000
120−#define BSDLY 00100000
121−#define BS0 00000000
122−#define BS1 00100000
123−#define VTDLY 00200000
124−#define VT0 00000000
125−#define VT1 00200000
80+#define ONLCR 0x00002
81+#define OLCUC 0x00004
82+#define NLDLY 0x00300
83+#define NL0 0x00000
84+#define NL1 0x00100
85+#define NL2 0x00200
86+#define NL3 0x00300
87+#define TABDLY 0x00c00
88+#define TAB0 0x00000
89+#define TAB1 0x00400
90+#define TAB2 0x00800
91+#define TAB3 0x00c00
92+#define CRDLY 0x03000
93+#define CR0 0x00000
94+#define CR1 0x01000
95+#define CR2 0x02000
96+#define CR3 0x03000
97+#define FFDLY 0x04000
98+#define FF0 0x00000
99+#define FF1 0x04000
100+#define BSDLY 0x08000
101+#define BS0 0x00000
102+#define BS1 0x08000
103+#define VTDLY 0x10000
104+#define VT0 0x00000
105+#define VT1 0x10000
126106 /*
127107 * Should be equivalent to TAB3, see description of TAB3 in
128108 * POSIX.1-2008, Ch. 11.2.3 "Output Modes"
@@ -130,61 +110,36 @@ struct ktermios { · 1 unmodified line
130110 #define XTABS TAB3
131111
132112 /* c_cflag bit meaning */
133−#define CBAUD 0000037
134−#define B0 0000000 /* hang up */
135−#define B50 0000001
136−#define B75 0000002
137−#define B110 0000003
138−#define B134 0000004
139−#define B150 0000005
140−#define B200 0000006
141−#define B300 0000007
142−#define B600 0000010
143−#define B1200 0000011
144−#define B1800 0000012
145−#define B2400 0000013
146−#define B4800 0000014
147−#define B9600 0000015
148−#define B19200 0000016
149−#define B38400 0000017
150−#define EXTA B19200
151−#define EXTB B38400
152−#define CBAUDEX 0000000
153−#define B57600 00020
154−#define B115200 00021
155−#define B230400 00022
156−#define B460800 00023
157−#define B500000 00024
158−#define B576000 00025
159−#define B921600 00026
160−#define B1000000 00027
161−#define B1152000 00030
162−#define B1500000 00031
163−#define B2000000 00032
164−#define B2500000 00033
165−#define B3000000 00034
166−#define B3500000 00035
167−#define B4000000 00036
168−#define BOTHER 00037
169−
170−#define CSIZE 00001400
171−#define CS5 00000000
172−#define CS6 00000400
173−#define CS7 00001000
174−#define CS8 00001400
175−
176−#define CSTOPB 00002000
177−#define CREAD 00004000
178−#define PARENB 00010000
179−#define PARODD 00020000
180−#define HUPCL 00040000
181−
182−#define CLOCAL 00100000
183−#define CMSPAR 010000000000 /* mark or space (stick) parity */
184−#define CRTSCTS 020000000000 /* flow control */
185−
186−#define CIBAUD 07600000
187−#define IBSHIFT 16
113+#define CBAUD 0x0000001f
114+#define CBAUDEX 0x00000000
115+#define BOTHER 0x0000001f
116+#define B57600 0x00000010
117+#define B115200 0x00000011
118+#define B230400 0x00000012
119+#define B460800 0x00000013
120+#define B500000 0x00000014
121+#define B576000 0x00000015
122+#define B921600 0x00000016
123+#define B1000000 0x00000017
124+#define B1152000 0x00000018
125+#define B1500000 0x00000019
126+#define B2000000 0x0000001a
127+#define B2500000 0x0000001b
128+#define B3000000 0x0000001c
129+#define B3500000 0x0000001d
130+#define B4000000 0x0000001e
131+#define CSIZE 0x00000300
132+#define CS5 0x00000000
133+#define CS6 0x00000100
134+#define CS7 0x00000200
135+#define CS8 0x00000300
136+#define CSTOPB 0x00000400
137+#define CREAD 0x00000800
138+#define PARENB 0x00001000
139+#define PARODD 0x00002000
140+#define HUPCL 0x00004000
141+#define CLOCAL 0x00008000
142+#define CIBAUD 0x001f0000
188143
189144 /* c_lflag bits */
190145 #define ISIG 0x00000080
@@ -204,17 +159,6 @@ struct ktermios { · 13 unmodified lines
204159 #define IEXTEN 0x00000400
205160 #define EXTPROC 0x10000000
206161
207−/* Values for the ACTION argument to `tcflow'. */
208−#define TCOOFF 0
209−#define TCOON 1
210−#define TCIOFF 2
211−#define TCION 3
212−
213−/* Values for the QUEUE_SELECTOR argument to `tcflush'. */
214−#define TCIFLUSH 0
215−#define TCOFLUSH 1
216−#define TCIOFLUSH 2
217−
218162 /* Values for the OPTIONAL_ACTIONS argument to `tcsetattr'. */
219163 #define TCSANOW 0
220164 #define TCSADRAIN 1
arch/mips/include/uapi/asm/termbits.h+99−150
@@ -11,11 +11,9 @@ · 10 unmodified lines
1111 #ifndef _ASM_TERMBITS_H
1212 #define _ASM_TERMBITS_H
1313
14−#include <linux/posix_types.h>
14+#include <asm-generic/termbits-common.h>
1515
16−typedef unsigned char cc_t;
17−typedef unsigned int speed_t;
18−typedef unsigned int tcflag_t;
16+typedef unsigned int tcflag_t;
1917
2018 /*
2119 * The ABI says nothing about NCC but seems to use NCCS as
@@ -54,175 +52,126 @@ struct ktermios { · 32 unmodified lines
5452 };
5553
5654 /* c_cc characters */
57−#define VINTR 0 /* Interrupt character [ISIG]. */
58−#define VQUIT 1 /* Quit character [ISIG]. */
59−#define VERASE 2 /* Erase character [ICANON]. */
60−#define VKILL 3 /* Kill-line character [ICANON]. */
61−#define VMIN 4 /* Minimum number of bytes read at once [!ICANON]. */
62−#define VTIME 5 /* Time-out value (tenths of a second) [!ICANON]. */
63−#define VEOL2 6 /* Second EOL character [ICANON]. */
55+#define VINTR 0 /* Interrupt character [ISIG] */
56+#define VQUIT 1 /* Quit character [ISIG] */
57+#define VERASE 2 /* Erase character [ICANON] */
58+#define VKILL 3 /* Kill-line character [ICANON] */
59+#define VMIN 4 /* Minimum number of bytes read at once [!ICANON] */
60+#define VTIME 5 /* Time-out value (tenths of a second) [!ICANON] */
61+#define VEOL2 6 /* Second EOL character [ICANON] */
6462 #define VSWTC 7 /* ??? */
6563 #define VSWTCH VSWTC
66−#define VSTART 8 /* Start (X-ON) character [IXON, IXOFF]. */
67−#define VSTOP 9 /* Stop (X-OFF) character [IXON, IXOFF]. */
68−#define VSUSP 10 /* Suspend character [ISIG]. */
64+#define VSTART 8 /* Start (X-ON) character [IXON, IXOFF] */
65+#define VSTOP 9 /* Stop (X-OFF) character [IXON, IXOFF] */
66+#define VSUSP 10 /* Suspend character [ISIG] */
6967 #if 0
7068 /*
7169 * VDSUSP is not supported
7270 */
73−#define VDSUSP 11 /* Delayed suspend character [ISIG]. */
71+#define VDSUSP 11 /* Delayed suspend character [ISIG] */
7472 #endif
75−#define VREPRINT 12 /* Reprint-line character [ICANON]. */
76−#define VDISCARD 13 /* Discard character [IEXTEN]. */
77−#define VWERASE 14 /* Word-erase character [ICANON]. */
78−#define VLNEXT 15 /* Literal-next character [IEXTEN]. */
79−#define VEOF 16 /* End-of-file character [ICANON]. */
80−#define VEOL 17 /* End-of-line character [ICANON]. */
73+#define VREPRINT 12 /* Reprint-line character [ICANON] */
74+#define VDISCARD 13 /* Discard character [IEXTEN] */
75+#define VWERASE 14 /* Word-erase character [ICANON] */
76+#define VLNEXT 15 /* Literal-next character [IEXTEN] */
77+#define VEOF 16 /* End-of-file character [ICANON] */
78+#define VEOL 17 /* End-of-line character [ICANON] */
8179
8280 /* c_iflag bits */
83−#define IGNBRK 0000001 /* Ignore break condition. */
84−#define BRKINT 0000002 /* Signal interrupt on break. */
85−#define IGNPAR 0000004 /* Ignore characters with parity errors. */
86−#define PARMRK 0000010 /* Mark parity and framing errors. */
87−#define INPCK 0000020 /* Enable input parity check. */
88−#define ISTRIP 0000040 /* Strip 8th bit off characters. */
89−#define INLCR 0000100 /* Map NL to CR on input. */
90−#define IGNCR 0000200 /* Ignore CR. */
91−#define ICRNL 0000400 /* Map CR to NL on input. */
92−#define IUCLC 0001000 /* Map upper case to lower case on input. */
93−#define IXON 0002000 /* Enable start/stop output control. */
94−#define IXANY 0004000 /* Any character will restart after stop. */
95−#define IXOFF 0010000 /* Enable start/stop input control. */
96−#define IMAXBEL 0020000 /* Ring bell when input queue is full. */
97−#define IUTF8 0040000 /* Input is UTF-8 */
81+#define IUCLC 0x0200 /* Map upper case to lower case on input */
82+#define IXON 0x0400 /* Enable start/stop output control */
83+#define IXOFF 0x1000 /* Enable start/stop input control */
84+#define IMAXBEL 0x2000 /* Ring bell when input queue is full */
85+#define IUTF8 0x4000 /* Input is UTF-8 */
9886
9987 /* c_oflag bits */
100−#define OPOST 0000001 /* Perform output processing. */
101−#define OLCUC 0000002 /* Map lower case to upper case on output. */
102−#define ONLCR 0000004 /* Map NL to CR-NL on output. */
103−#define OCRNL 0000010
104−#define ONOCR 0000020
105−#define ONLRET 0000040
106−#define OFILL 0000100
107−#define OFDEL 0000200
108−#define NLDLY 0000400
109−#define NL0 0000000
110−#define NL1 0000400
111−#define CRDLY 0003000
112−#define CR0 0000000
113−#define CR1 0001000
114−#define CR2 0002000
115−#define CR3 0003000
116−#define TABDLY 0014000
117−#define TAB0 0000000
118−#define TAB1 0004000
119−#define TAB2 0010000
120−#define TAB3 0014000
121−#define XTABS 0014000
122−#define BSDLY 0020000
123−#define BS0 0000000
124−#define BS1 0020000
125−#define VTDLY 0040000
126−#define VT0 0000000
127−#define VT1 0040000
128−#define FFDLY 0100000
129−#define FF0 0000000
130−#define FF1 0100000
88+#define OLCUC 0x00002 /* Map lower case to upper case on output */
89+#define ONLCR 0x00004 /* Map NL to CR-NL on output */
90+#define NLDLY 0x00100
91+#define NL0 0x00000
92+#define NL1 0x00100
93+#define CRDLY 0x00600
94+#define CR0 0x00000
95+#define CR1 0x00200
96+#define CR2 0x00400
97+#define CR3 0x00600
98+#define TABDLY 0x01800
99+#define TAB0 0x00000
100+#define TAB1 0x00800
101+#define TAB2 0x01000
102+#define TAB3 0x01800
103+#define XTABS 0x01800
104+#define BSDLY 0x02000
105+#define BS0 0x00000
106+#define BS1 0x02000
107+#define VTDLY 0x04000
108+#define VT0 0x00000
109+#define VT1 0x04000
110+#define FFDLY 0x08000
111+#define FF0 0x00000
112+#define FF1 0x08000
131113 /*
132114 #define PAGEOUT ???
133115 #define WRAP ???
134116 */
135117
136118 /* c_cflag bit meaning */
137−#define CBAUD 0010017
138−#define B0 0000000 /* hang up */
139−#define B50 0000001
140−#define B75 0000002
141−#define B110 0000003
142−#define B134 0000004
143−#define B150 0000005
144−#define B200 0000006
145−#define B300 0000007
146−#define B600 0000010
147−#define B1200 0000011
148−#define B1800 0000012
149−#define B2400 0000013
150−#define B4800 0000014
151−#define B9600 0000015
152−#define B19200 0000016
153−#define B38400 0000017
154−#define EXTA B19200
155−#define EXTB B38400
156−#define CSIZE 0000060 /* Number of bits per byte (mask). */
157−#define CS5 0000000 /* 5 bits per byte. */
158−#define CS6 0000020 /* 6 bits per byte. */
159−#define CS7 0000040 /* 7 bits per byte. */
160−#define CS8 0000060 /* 8 bits per byte. */
161−#define CSTOPB 0000100 /* Two stop bits instead of one. */
162−#define CREAD 0000200 /* Enable receiver. */
163−#define PARENB 0000400 /* Parity enable. */
164−#define PARODD 0001000 /* Odd parity instead of even. */
165−#define HUPCL 0002000 /* Hang up on last close. */
166−#define CLOCAL 0004000 /* Ignore modem status lines. */
167−#define CBAUDEX 0010000
168−#define BOTHER 0010000
169−#define B57600 0010001
170−#define B115200 0010002
171−#define B230400 0010003
172−#define B460800 0010004
173−#define B500000 0010005
174−#define B576000 0010006
175−#define B921600 0010007
176−#define B1000000 0010010
177−#define B1152000 0010011
178−#define B1500000 0010012
179−#define B2000000 0010013
180−#define B2500000 0010014
181−#define B3000000 0010015
182−#define B3500000 0010016
183−#define B4000000 0010017
184−#define CIBAUD 002003600000 /* input baud rate */
185−#define CMSPAR 010000000000 /* mark or space (stick) parity */
186−#define CRTSCTS 020000000000 /* flow control */
187−
188−#define IBSHIFT 16 /* Shift from CBAUD to CIBAUD */
119+#define CBAUD 0x0000100f
120+#define CSIZE 0x00000030 /* Number of bits per byte (mask) */
121+#define CS5 0x00000000 /* 5 bits per byte */
122+#define CS6 0x00000010 /* 6 bits per byte */
123+#define CS7 0x00000020 /* 7 bits per byte */
124+#define CS8 0x00000030 /* 8 bits per byte */
125+#define CSTOPB 0x00000040 /* Two stop bits instead of one */
126+#define CREAD 0x00000080 /* Enable receiver */
127+#define PARENB 0x00000100 /* Parity enable */
128+#define PARODD 0x00000200 /* Odd parity instead of even */
129+#define HUPCL 0x00000400 /* Hang up on last close */
130+#define CLOCAL 0x00000800 /* Ignore modem status lines */
131+#define CBAUDEX 0x00001000
132+#define BOTHER 0x00001000
133+#define B57600 0x00001001
134+#define B115200 0x00001002
135+#define B230400 0x00001003
136+#define B460800 0x00001004
137+#define B500000 0x00001005
138+#define B576000 0x00001006
139+#define B921600 0x00001007
140+#define B1000000 0x00001008
141+#define B1152000 0x00001009
142+#define B1500000 0x0000100a
143+#define B2000000 0x0000100b
144+#define B2500000 0x0000100c
145+#define B3000000 0x0000100d
146+#define B3500000 0x0000100e
147+#define B4000000 0x0000100f
148+#define CIBAUD 0x100f0000 /* input baud rate */
189149
190150 /* c_lflag bits */
191−#define ISIG 0000001 /* Enable signals. */
192−#define ICANON 0000002 /* Do erase and kill processing. */
193−#define XCASE 0000004
194−#define ECHO 0000010 /* Enable echo. */
195−#define ECHOE 0000020 /* Visual erase for ERASE. */
196−#define ECHOK 0000040 /* Echo NL after KILL. */
197−#define ECHONL 0000100 /* Echo NL even if ECHO is off. */
198−#define NOFLSH 0000200 /* Disable flush after interrupt. */
199−#define IEXTEN 0000400 /* Enable DISCARD and LNEXT. */
200−#define ECHOCTL 0001000 /* Echo control characters as ^X. */
201−#define ECHOPRT 0002000 /* Hardcopy visual erase. */
202−#define ECHOKE 0004000 /* Visual erase for KILL. */
203−#define FLUSHO 0020000
204−#define PENDIN 0040000 /* Retype pending input (state). */
205−#define TOSTOP 0100000 /* Send SIGTTOU for background output. */
206−#define ITOSTOP TOSTOP
207−#define EXTPROC 0200000 /* External processing on pty */
151+#define ISIG 0x00001 /* Enable signals */
152+#define ICANON 0x00002 /* Do erase and kill processing */
153+#define XCASE 0x00004
154+#define ECHO 0x00008 /* Enable echo */
155+#define ECHOE 0x00010 /* Visual erase for ERASE */
156+#define ECHOK 0x00020 /* Echo NL after KILL */
157+#define ECHONL 0x00040 /* Echo NL even if ECHO is off */
158+#define NOFLSH 0x00080 /* Disable flush after interrupt */
159+#define IEXTEN 0x00100 /* Enable DISCARD and LNEXT */
160+#define ECHOCTL 0x00200 /* Echo control characters as ^X */
161+#define ECHOPRT 0x00400 /* Hardcopy visual erase */
162+#define ECHOKE 0x00800 /* Visual erase for KILL */
163+#define FLUSHO 0x02000
164+#define PENDIN 0x04000 /* Retype pending input (state) */
165+#define TOSTOP 0x08000 /* Send SIGTTOU for background output */
166+#define ITOSTOP TOSTOP
167+#define EXTPROC 0x10000 /* External processing on pty */
208168
209169 /* ioctl (fd, TIOCSERGETLSR, &result) where result may be as below */
210170 #define TIOCSER_TEMT 0x01 /* Transmitter physically empty */
211171
212−/* tcflow() and TCXONC use these */
213−#define TCOOFF 0 /* Suspend output. */
214−#define TCOON 1 /* Restart suspended output. */
215−#define TCIOFF 2 /* Send a STOP character. */
216−#define TCION 3 /* Send a START character. */
217−
218−/* tcflush() and TCFLSH use these */
219−#define TCIFLUSH 0 /* Discard data received but not yet read. */
220−#define TCOFLUSH 1 /* Discard data written but not yet sent. */
221−#define TCIOFLUSH 2 /* Discard all pending data. */
222−
223172 /* tcsetattr uses these */
224−#define TCSANOW TCSETS /* Change immediately. */
225−#define TCSADRAIN TCSETSW /* Change when pending output is written. */
226−#define TCSAFLUSH TCSETSF /* Flush pending input before changing. */
173+#define TCSANOW TCSETS /* Change immediately */
174+#define TCSADRAIN TCSETSW /* Change when pending output is written */
175+#define TCSAFLUSH TCSETSF /* Flush pending input before changing */
227176
228177 #endif /* _ASM_TERMBITS_H */
arch/parisc/include/uapi/asm/termbits.h+94−147
@@ -2,10 +2,8 @@ · 1 unmodified line
22 #ifndef __ARCH_PARISC_TERMBITS_H__
33 #define __ARCH_PARISC_TERMBITS_H__
44
5−#include <linux/posix_types.h>
5+#include <asm-generic/termbits-common.h>
66
7−typedef unsigned char cc_t;
8−typedef unsigned int speed_t;
97 typedef unsigned int tcflag_t;
108
119 #define NCCS 19
@@ -41,158 +39,107 @@ struct ktermios { · 29 unmodified lines
4139 };
4240
4341 /* c_cc characters */
44−#define VINTR 0
45−#define VQUIT 1
46−#define VERASE 2
47−#define VKILL 3
48−#define VEOF 4
49−#define VTIME 5
50−#define VMIN 6
51−#define VSWTC 7
52−#define VSTART 8
53−#define VSTOP 9
54−#define VSUSP 10
55−#define VEOL 11
56−#define VREPRINT 12
57−#define VDISCARD 13
58−#define VWERASE 14
59−#define VLNEXT 15
60−#define VEOL2 16
61−
42+#define VINTR 0
43+#define VQUIT 1
44+#define VERASE 2
45+#define VKILL 3
46+#define VEOF 4
47+#define VTIME 5
48+#define VMIN 6
49+#define VSWTC 7
50+#define VSTART 8
51+#define VSTOP 9
52+#define VSUSP 10
53+#define VEOL 11
54+#define VREPRINT 12
55+#define VDISCARD 13
56+#define VWERASE 14
57+#define VLNEXT 15
58+#define VEOL2 16
6259
6360 /* c_iflag bits */
64−#define IGNBRK 0000001
65−#define BRKINT 0000002
66−#define IGNPAR 0000004
67−#define PARMRK 0000010
68−#define INPCK 0000020
69−#define ISTRIP 0000040
70−#define INLCR 0000100
71−#define IGNCR 0000200
72−#define ICRNL 0000400
73−#define IUCLC 0001000
74−#define IXON 0002000
75−#define IXANY 0004000
76−#define IXOFF 0010000
77−#define IMAXBEL 0040000
78−#define IUTF8 0100000
61+#define IUCLC 0x0200
62+#define IXON 0x0400
63+#define IXOFF 0x1000
64+#define IMAXBEL 0x4000
65+#define IUTF8 0x8000
7966
8067 /* c_oflag bits */
81−#define OPOST 0000001
82−#define OLCUC 0000002
83−#define ONLCR 0000004
84−#define OCRNL 0000010
85−#define ONOCR 0000020
86−#define ONLRET 0000040
87−#define OFILL 0000100
88−#define OFDEL 0000200
89−#define NLDLY 0000400
90−#define NL0 0000000
91−#define NL1 0000400
92−#define CRDLY 0003000
93−#define CR0 0000000
94−#define CR1 0001000
95−#define CR2 0002000
96−#define CR3 0003000
97−#define TABDLY 0014000
98−#define TAB0 0000000
99−#define TAB1 0004000
100−#define TAB2 0010000
101−#define TAB3 0014000
102−#define XTABS 0014000
103−#define BSDLY 0020000
104−#define BS0 0000000
105−#define BS1 0020000
106−#define VTDLY 0040000
107−#define VT0 0000000
108−#define VT1 0040000
109−#define FFDLY 0100000
110−#define FF0 0000000
111−#define FF1 0100000
68+#define OLCUC 0x00002
69+#define ONLCR 0x00004
70+#define NLDLY 0x00100
71+#define NL0 0x00000
72+#define NL1 0x00100
73+#define CRDLY 0x00600
74+#define CR0 0x00000
75+#define CR1 0x00200
76+#define CR2 0x00400
77+#define CR3 0x00600
78+#define TABDLY 0x01800
79+#define TAB0 0x00000
80+#define TAB1 0x00800
81+#define TAB2 0x01000
82+#define TAB3 0x01800
83+#define XTABS 0x01800
84+#define BSDLY 0x02000
85+#define BS0 0x00000
86+#define BS1 0x02000
87+#define VTDLY 0x04000
88+#define VT0 0x00000
89+#define VT1 0x04000
90+#define FFDLY 0x08000
91+#define FF0 0x00000
92+#define FF1 0x08000
11293
11394 /* c_cflag bit meaning */
114−#define CBAUD 0010017
115−#define B0 0000000 /* hang up */
116−#define B50 0000001
117−#define B75 0000002
118−#define B110 0000003
119−#define B134 0000004
120−#define B150 0000005
121−#define B200 0000006
122−#define B300 0000007
123−#define B600 0000010
124−#define B1200 0000011
125−#define B1800 0000012
126−#define B2400 0000013
127−#define B4800 0000014
128−#define B9600 0000015
129−#define B19200 0000016
130−#define B38400 0000017
131−#define EXTA B19200
132−#define EXTB B38400
133−#define CSIZE 0000060
134−#define CS5 0000000
135−#define CS6 0000020
136−#define CS7 0000040
137−#define CS8 0000060
138−#define CSTOPB 0000100
139−#define CREAD 0000200
140−#define PARENB 0000400
141−#define PARODD 0001000
142−#define HUPCL 0002000
143−#define CLOCAL 0004000
144−#define CBAUDEX 0010000
145−#define BOTHER 0010000
146−#define B57600 0010001
147−#define B115200 0010002
148−#define B230400 0010003
149−#define B460800 0010004
150−#define B500000 0010005
151−#define B576000 0010006
152−#define B921600 0010007
153−#define B1000000 0010010
154−#define B1152000 0010011
155−#define B1500000 0010012
156−#define B2000000 0010013
157−#define B2500000 0010014
158−#define B3000000 0010015
159−#define B3500000 0010016
160−#define B4000000 0010017
161−#define CIBAUD 002003600000 /* input baud rate */
162−#define CMSPAR 010000000000 /* mark or space (stick) parity */
163−#define CRTSCTS 020000000000 /* flow control */
164−
165−#define IBSHIFT 16 /* Shift from CBAUD to CIBAUD */
166−
95+#define CBAUD 0x0000100f
96+#define CSIZE 0x00000030
97+#define CS5 0x00000000
98+#define CS6 0x00000010
99+#define CS7 0x00000020
100+#define CS8 0x00000030
101+#define CSTOPB 0x00000040
102+#define CREAD 0x00000080
103+#define PARENB 0x00000100
104+#define PARODD 0x00000200
105+#define HUPCL 0x00000400
106+#define CLOCAL 0x00000800
107+#define CBAUDEX 0x00001000
108+#define BOTHER 0x00001000
109+#define B57600 0x00001001
110+#define B115200 0x00001002
111+#define B230400 0x00001003
112+#define B460800 0x00001004
113+#define B500000 0x00001005
114+#define B576000 0x00001006
115+#define B921600 0x00001007
116+#define B1000000 0x00001008
117+#define B1152000 0x00001009
118+#define B1500000 0x0000100a
119+#define B2000000 0x0000100b
120+#define B2500000 0x0000100c
121+#define B3000000 0x0000100d
122+#define B3500000 0x0000100e
123+#define B4000000 0x0000100f
124+#define CIBAUD 0x100f0000 /* input baud rate */
167125
168126 /* c_lflag bits */
169−#define ISIG 0000001
170−#define ICANON 0000002
171−#define XCASE 0000004
172−#define ECHO 0000010
173−#define ECHOE 0000020
174−#define ECHOK 0000040
175−#define ECHONL 0000100
176−#define NOFLSH 0000200
177−#define TOSTOP 0000400
178−#define ECHOCTL 0001000
179−#define ECHOPRT 0002000
180−#define ECHOKE 0004000
181−#define FLUSHO 0010000
182−#define PENDIN 0040000
183−#define IEXTEN 0100000
184−#define EXTPROC 0200000
185−
186−/* tcflow() and TCXONC use these */
187−#define TCOOFF 0
188−#define TCOON 1
189−#define TCIOFF 2
190−#define TCION 3
191−
192−/* tcflush() and TCFLSH use these */
193−#define TCIFLUSH 0
194−#define TCOFLUSH 1
195−#define TCIOFLUSH 2
127+#define ISIG 0x00001
128+#define ICANON 0x00002
129+#define XCASE 0x00004
130+#define ECHO 0x00008
131+#define ECHOE 0x00010
132+#define ECHOK 0x00020
133+#define ECHONL 0x00040
134+#define NOFLSH 0x00080
135+#define TOSTOP 0x00100
136+#define ECHOCTL 0x00200
137+#define ECHOPRT 0x00400
138+#define ECHOKE 0x00800
139+#define FLUSHO 0x01000
140+#define PENDIN 0x04000
141+#define IEXTEN 0x08000
142+#define EXTPROC 0x10000
196143
197144 /* tcsetattr uses these */
198145 #define TCSANOW 0
arch/powerpc/include/uapi/asm/termbits.h+64−118
@@ -9,8 +9,8 @@ · 8 unmodified lines
99 * 2 of the License, or (at your option) any later version.
1010 */
1111
12−typedef unsigned char cc_t;
13−typedef unsigned int speed_t;
12+#include <asm-generic/termbits-common.h>
13+
1414 typedef unsigned int tcflag_t;
1515
1616 /*
@@ -64,115 +64,72 @@ struct ktermios { · 47 unmodified lines
6464 #define VDISCARD 16
6565
6666 /* c_iflag bits */
67−#define IGNBRK 0000001
68−#define BRKINT 0000002
69−#define IGNPAR 0000004
70−#define PARMRK 0000010
71−#define INPCK 0000020
72−#define ISTRIP 0000040
73−#define INLCR 0000100
74−#define IGNCR 0000200
75−#define ICRNL 0000400
76−#define IXON 0001000
77−#define IXOFF 0002000
78−#define IXANY 0004000
79−#define IUCLC 0010000
80−#define IMAXBEL 0020000
81−#define IUTF8 0040000
67+#define IXON 0x0200
68+#define IXOFF 0x0400
69+#define IUCLC 0x1000
70+#define IMAXBEL 0x2000
71+#define IUTF8 0x4000
8272
8373 /* c_oflag bits */
84−#define OPOST 0000001
85−#define ONLCR 0000002
86−#define OLCUC 0000004
87−
88−#define OCRNL 0000010
89−#define ONOCR 0000020
90−#define ONLRET 0000040
91−
92−#define OFILL 00000100
93−#define OFDEL 00000200
94−#define NLDLY 00001400
95−#define NL0 00000000
96−#define NL1 00000400
97−#define NL2 00001000
98−#define NL3 00001400
99−#define TABDLY 00006000
100−#define TAB0 00000000
101−#define TAB1 00002000
102−#define TAB2 00004000
103−#define TAB3 00006000
104−#define XTABS 00006000 /* required by POSIX to == TAB3 */
105−#define CRDLY 00030000
106−#define CR0 00000000
107−#define CR1 00010000
108−#define CR2 00020000
109−#define CR3 00030000
110−#define FFDLY 00040000
111−#define FF0 00000000
112−#define FF1 00040000
113−#define BSDLY 00100000
114−#define BS0 00000000
115−#define BS1 00100000
116−#define VTDLY 00200000
117−#define VT0 00000000
118−#define VT1 00200000
74+#define ONLCR 0x00002
75+#define OLCUC 0x00004
76+#define NLDLY 0x00300
77+#define NL0 0x00000
78+#define NL1 0x00100
79+#define NL2 0x00200
80+#define NL3 0x00300
81+#define TABDLY 0x00c00
82+#define TAB0 0x00000
83+#define TAB1 0x00400
84+#define TAB2 0x00800
85+#define TAB3 0x00c00
86+#define XTABS 0x00c00 /* required by POSIX to == TAB3 */
87+#define CRDLY 0x03000
88+#define CR0 0x00000
89+#define CR1 0x01000
90+#define CR2 0x02000
91+#define CR3 0x03000
92+#define FFDLY 0x04000
93+#define FF0 0x00000
94+#define FF1 0x04000
95+#define BSDLY 0x08000
96+#define BS0 0x00000
97+#define BS1 0x08000
98+#define VTDLY 0x10000
99+#define VT0 0x00000
100+#define VT1 0x10000
119101
120102 /* c_cflag bit meaning */
121−#define CBAUD 0000377
122−#define B0 0000000 /* hang up */
123−#define B50 0000001
124−#define B75 0000002
125−#define B110 0000003
126−#define B134 0000004
127−#define B150 0000005
128−#define B200 0000006
129−#define B300 0000007
130−#define B600 0000010
131−#define B1200 0000011
132−#define B1800 0000012
133−#define B2400 0000013
134−#define B4800 0000014
135−#define B9600 0000015
136−#define B19200 0000016
137−#define B38400 0000017
138−#define EXTA B19200
139−#define EXTB B38400
140−#define CBAUDEX 0000000
141−#define B57600 00020
142−#define B115200 00021
143−#define B230400 00022
144−#define B460800 00023
145−#define B500000 00024
146−#define B576000 00025
147−#define B921600 00026
148−#define B1000000 00027
149−#define B1152000 00030
150−#define B1500000 00031
151−#define B2000000 00032
152−#define B2500000 00033
153−#define B3000000 00034
154−#define B3500000 00035
155−#define B4000000 00036
156−#define BOTHER 00037
157−
158−#define CIBAUD 077600000
159−#define IBSHIFT 16 /* Shift from CBAUD to CIBAUD */
160−
161−#define CSIZE 00001400
162−#define CS5 00000000
163−#define CS6 00000400
164−#define CS7 00001000
165−#define CS8 00001400
166−
167−#define CSTOPB 00002000
168−#define CREAD 00004000
169−#define PARENB 00010000
170−#define PARODD 00020000
171−#define HUPCL 00040000
172−
173−#define CLOCAL 00100000
174−#define CMSPAR 010000000000 /* mark or space (stick) parity */
175−#define CRTSCTS 020000000000 /* flow control */
103+#define CBAUD 0x000000ff
104+#define CBAUDEX 0x00000000
105+#define BOTHER 0x0000001f
106+#define B57600 0x00000010
107+#define B115200 0x00000011
108+#define B230400 0x00000012
109+#define B460800 0x00000013
110+#define B500000 0x00000014
111+#define B576000 0x00000015
112+#define B921600 0x00000016
113+#define B1000000 0x00000017
114+#define B1152000 0x00000018
115+#define B1500000 0x00000019
116+#define B2000000 0x0000001a
117+#define B2500000 0x0000001b
118+#define B3000000 0x0000001c
119+#define B3500000 0x0000001d
120+#define B4000000 0x0000001e
121+#define CSIZE 0x00000300
122+#define CS5 0x00000000
123+#define CS6 0x00000100
124+#define CS7 0x00000200
125+#define CS8 0x00000300
126+#define CSTOPB 0x00000400
127+#define CREAD 0x00000800
128+#define PARENB 0x00001000
129+#define PARODD 0x00002000
130+#define HUPCL 0x00004000
131+#define CLOCAL 0x00008000
132+#define CIBAUD 0x00ff0000
176133
177134 /* c_lflag bits */
178135 #define ISIG 0x00000080
@@ -192,17 +149,6 @@ struct ktermios { · 13 unmodified lines
192149 #define IEXTEN 0x00000400
193150 #define EXTPROC 0x10000000
194151
195−/* Values for the ACTION argument to `tcflow'. */
196−#define TCOOFF 0
197−#define TCOON 1
198−#define TCIOFF 2
199−#define TCION 3
200−
201−/* Values for the QUEUE_SELECTOR argument to `tcflush'. */
202−#define TCIFLUSH 0
203−#define TCOFLUSH 1
204−#define TCIOFLUSH 2
205−
206152 /* Values for the OPTIONAL_ACTIONS argument to `tcsetattr'. */
207153 #define TCSANOW 0
208154 #define TCSADRAIN 1
arch/sparc/include/uapi/asm/termbits.h+84−139
@@ -2,15 +2,12 @@ · 1 unmodified line
22 #ifndef _UAPI_SPARC_TERMBITS_H
33 #define _UAPI_SPARC_TERMBITS_H
44
5−#include <linux/posix_types.h>
6−
7−typedef unsigned char cc_t;
8−typedef unsigned int speed_t;
5+#include <asm-generic/termbits-common.h>
96
107 #if defined(__sparc__) && defined(__arch64__)
11−typedef unsigned int tcflag_t;
8+typedef unsigned int tcflag_t;
129 #else
13−typedef unsigned long tcflag_t;
10+typedef unsigned long tcflag_t;
1411 #endif
1512
1613 #define NCC 8
@@ -61,21 +58,19 @@ struct ktermios { · 44 unmodified lines
6158 };
6259
6360 /* c_cc characters */
64−#define VINTR 0
65−#define VQUIT 1
66−#define VERASE 2
67−#define VKILL 3
68−#define VEOF 4
69−#define VEOL 5
70−#define VEOL2 6
71−#define VSWTC 7
72−#define VSTART 8
73−#define VSTOP 9
74−
75−
61+#define VINTR 0
62+#define VQUIT 1
63+#define VERASE 2
64+#define VKILL 3
65+#define VEOF 4
66+#define VEOL 5
67+#define VEOL2 6
68+#define VSWTC 7
69+#define VSTART 8
70+#define VSTOP 9
7671
7772 #define VSUSP 10
78−#define VDSUSP 11 /* SunOS POSIX nicety I do believe... */
73+#define VDSUSP 11 /* SunOS POSIX nicety I do believe... */
7974 #define VREPRINT 12
8075 #define VDISCARD 13
8176 #define VWERASE 14
@@ -90,121 +85,83 @@ struct ktermios { · 8 unmodified lines
9085 #endif
9186
9287 /* c_iflag bits */
93−#define IGNBRK 0x00000001
94−#define BRKINT 0x00000002
95−#define IGNPAR 0x00000004
96−#define PARMRK 0x00000008
97−#define INPCK 0x00000010
98−#define ISTRIP 0x00000020
99−#define INLCR 0x00000040
100−#define IGNCR 0x00000080
101−#define ICRNL 0x00000100
102−#define IUCLC 0x00000200
103−#define IXON 0x00000400
104−#define IXANY 0x00000800
105−#define IXOFF 0x00001000
106−#define IMAXBEL 0x00002000
107−#define IUTF8 0x00004000
88+#define IUCLC 0x0200
89+#define IXON 0x0400
90+#define IXOFF 0x1000
91+#define IMAXBEL 0x2000
92+#define IUTF8 0x4000
10893
10994 /* c_oflag bits */
110−#define OPOST 0x00000001
111−#define OLCUC 0x00000002
112−#define ONLCR 0x00000004
113−#define OCRNL 0x00000008
114−#define ONOCR 0x00000010
115−#define ONLRET 0x00000020
116−#define OFILL 0x00000040
117−#define OFDEL 0x00000080
118−#define NLDLY 0x00000100
119−#define NL0 0x00000000
120−#define NL1 0x00000100
121−#define CRDLY 0x00000600
122−#define CR0 0x00000000
123−#define CR1 0x00000200
124−#define CR2 0x00000400
125−#define CR3 0x00000600
126−#define TABDLY 0x00001800
127−#define TAB0 0x00000000
128−#define TAB1 0x00000800
129−#define TAB2 0x00001000
130−#define TAB3 0x00001800
131−#define XTABS 0x00001800
132−#define BSDLY 0x00002000
133−#define BS0 0x00000000
134−#define BS1 0x00002000
135−#define VTDLY 0x00004000
136−#define VT0 0x00000000
137−#define VT1 0x00004000
138−#define FFDLY 0x00008000
139−#define FF0 0x00000000
140−#define FF1 0x00008000
141−#define PAGEOUT 0x00010000 /* SUNOS specific */
142−#define WRAP 0x00020000 /* SUNOS specific */
95+#define OLCUC 0x00002
96+#define ONLCR 0x00004
97+#define NLDLY 0x00100
98+#define NL0 0x00000
99+#define NL1 0x00100
100+#define CRDLY 0x00600
101+#define CR0 0x00000
102+#define CR1 0x00200
103+#define CR2 0x00400
104+#define CR3 0x00600
105+#define TABDLY 0x01800
106+#define TAB0 0x00000
107+#define TAB1 0x00800
108+#define TAB2 0x01000
109+#define TAB3 0x01800
110+#define XTABS 0x01800
111+#define BSDLY 0x02000
112+#define BS0 0x00000
113+#define BS1 0x02000
114+#define VTDLY 0x04000
115+#define VT0 0x00000
116+#define VT1 0x04000
117+#define FFDLY 0x08000
118+#define FF0 0x00000
119+#define FF1 0x08000
120+#define PAGEOUT 0x10000 /* SUNOS specific */
121+#define WRAP 0x20000 /* SUNOS specific */
143122
144123 /* c_cflag bit meaning */
145−#define CBAUD 0x0000100f
146−#define B0 0x00000000 /* hang up */
147−#define B50 0x00000001
148−#define B75 0x00000002
149−#define B110 0x00000003
150−#define B134 0x00000004
151−#define B150 0x00000005
152−#define B200 0x00000006
153−#define B300 0x00000007
154−#define B600 0x00000008
155−#define B1200 0x00000009
156−#define B1800 0x0000000a
157−#define B2400 0x0000000b
158−#define B4800 0x0000000c
159−#define B9600 0x0000000d
160−#define B19200 0x0000000e
161−#define B38400 0x0000000f
162−#define EXTA B19200
163−#define EXTB B38400
164−#define CSIZE 0x00000030
165−#define CS5 0x00000000
166−#define CS6 0x00000010
167−#define CS7 0x00000020
168−#define CS8 0x00000030
169−#define CSTOPB 0x00000040
170−#define CREAD 0x00000080
171−#define PARENB 0x00000100
172−#define PARODD 0x00000200
173−#define HUPCL 0x00000400
174−#define CLOCAL 0x00000800
175−#define CBAUDEX 0x00001000
124+#define CBAUD 0x0000100f
125+#define CSIZE 0x00000030
126+#define CS5 0x00000000
127+#define CS6 0x00000010
128+#define CS7 0x00000020
129+#define CS8 0x00000030
130+#define CSTOPB 0x00000040
131+#define CREAD 0x00000080
132+#define PARENB 0x00000100
133+#define PARODD 0x00000200
134+#define HUPCL 0x00000400
135+#define CLOCAL 0x00000800
136+#define CBAUDEX 0x00001000
176137 /* We'll never see these speeds with the Zilogs, but for completeness... */
177−#define BOTHER 0x00001000
178−#define B57600 0x00001001
179−#define B115200 0x00001002
180−#define B230400 0x00001003
181−#define B460800 0x00001004
138+#define BOTHER 0x00001000
139+#define B57600 0x00001001
140+#define B115200 0x00001002
141+#define B230400 0x00001003
142+#define B460800 0x00001004
182143 /* This is what we can do with the Zilogs. */
183−#define B76800 0x00001005
144+#define B76800 0x00001005
184145 /* This is what we can do with the SAB82532. */
185−#define B153600 0x00001006
186−#define B307200 0x00001007
187−#define B614400 0x00001008
188−#define B921600 0x00001009
146+#define B153600 0x00001006
147+#define B307200 0x00001007
148+#define B614400 0x00001008
149+#define B921600 0x00001009
189150 /* And these are the rest... */
190−#define B500000 0x0000100a
191−#define B576000 0x0000100b
192−#define B1000000 0x0000100c
193−#define B1152000 0x0000100d
194−#define B1500000 0x0000100e
195−#define B2000000 0x0000100f
151+#define B500000 0x0000100a
152+#define B576000 0x0000100b
153+#define B1000000 0x0000100c
154+#define B1152000 0x0000100d
155+#define B1500000 0x0000100e
156+#define B2000000 0x0000100f
196157 /* These have totally bogus values and nobody uses them
197158 so far. Later on we'd have to use say 0x10000x and
198159 adjust CBAUD constant and drivers accordingly.
199−#define B2500000 0x00001010
200−#define B3000000 0x00001011
201−#define B3500000 0x00001012
202−#define B4000000 0x00001013 */
203−#define CIBAUD 0x100f0000 /* input baud rate (not used) */
204−#define CMSPAR 0x40000000 /* mark or space (stick) parity */
205−#define CRTSCTS 0x80000000 /* flow control */
206−
207−#define IBSHIFT 16 /* Shift from CBAUD to CIBAUD */
160+#define B2500000 0x00001010
161+#define B3000000 0x00001011
162+#define B3500000 0x00001012
163+#define B4000000 0x00001013 */
164+#define CIBAUD 0x100f0000 /* input baud rate (not used) */
208165
209166 /* c_lflag bits */
210167 #define ISIG 0x00000001
@@ -219,7 +176,7 @@ struct ktermios { · 8 unmodified lines
219176 #define ECHOCTL 0x00000200
220177 #define ECHOPRT 0x00000400
221178 #define ECHOKE 0x00000800
222−#define DEFECHO 0x00001000 /* SUNOS thing, what is it? */
179+#define DEFECHO 0x00001000 /* SUNOS thing, what is it? */
223180 #define FLUSHO 0x00002000
224181 #define PENDIN 0x00004000
225182 #define IEXTEN 0x00008000
@@ -244,21 +201,9 @@ struct ktermios { · 18 unmodified lines
244201 /* ioctl (fd, TIOCSERGETLSR, &result) where result may be as below */
245202 #define TIOCSER_TEMT 0x01 /* Transmitter physically empty */
246203
247−
248−/* tcflow() and TCXONC use these */
249−#define TCOOFF 0
250−#define TCOON 1
251−#define TCIOFF 2
252−#define TCION 3
253−
254−/* tcflush() and TCFLSH use these */
255−#define TCIFLUSH 0
256−#define TCOFLUSH 1
257−#define TCIOFLUSH 2
258−
259204 /* tcsetattr uses these */
260−#define TCSANOW 0
261−#define TCSADRAIN 1
262−#define TCSAFLUSH 2
205+#define TCSANOW 0
206+#define TCSADRAIN 1
207+#define TCSAFLUSH 2
263208
264209 #endif /* _UAPI_SPARC_TERMBITS_H */
drivers/char/Kconfig+2−1
@@ -18,7 +18,8 @@ config TTY_PRINTK · 17 unmodified lines
1818 The feature is useful to inline user messages with kernel
1919 messages.
2020 In order to use this feature, you should output user messages
21− to /dev/ttyprintk or redirect console to this TTY.
21+ to /dev/ttyprintk or redirect console to this TTY, or boot
22+ the kernel with console=ttyprintk.
2223
2324 If unsure, say N.
2425
drivers/char/pcmcia/synclink_cs.c+5−3
@@ -1418,7 +1418,11 @@ static void mgslpc_change_params(MGSLPC_INFO *info, struct tty_struct *tty) · 1417 unmodified lines
14181418 info->serial_signals &= ~(SerialSignal_RTS | SerialSignal_DTR);
14191419
14201420 /* byte size and parity */
1421−
1421+ if ((cflag & CSIZE) != CS8) {
1422+ cflag &= ~CSIZE;
1423+ cflag |= CS7;
1424+ tty->termios.c_cflag = cflag;
1425+ }
14221426 info->params.data_bits = tty_get_char_size(cflag);
14231427
14241428 if (cflag & CSTOPB)
@@ -1432,10 +1436,8 @@ static void mgslpc_change_params(MGSLPC_INFO *info, struct tty_struct *tty) · 7 unmodified lines
14321436 info->params.parity = ASYNC_PARITY_ODD;
14331437 else
14341438 info->params.parity = ASYNC_PARITY_EVEN;
1435−#ifdef CMSPAR
14361439 if (cflag & CMSPAR)
14371440 info->params.parity = ASYNC_PARITY_SPACE;
1438−#endif
14391441 }
14401442
14411443 /* calculate number of jiffies to transmit a full
drivers/char/ttyprintk.c+16−0
@@ -11,6 +11,7 @@ · 10 unmodified lines
1111 * of the boot process, for example.
1212 */
1313
14+#include <linux/console.h>
1415 #include <linux/device.h>
1516 #include <linux/serial.h>
1617 #include <linux/tty.h>
@@ -163,6 +164,18 @@ static const struct tty_port_operations tpk_port_ops = { · 146 unmodified lines
163164
164165 static struct tty_driver *ttyprintk_driver;
165166
167+static struct tty_driver *ttyprintk_console_device(struct console *c,
168+ int *index)
169+{
170+ *index = 0;
171+ return ttyprintk_driver;
172+}
173+
174+static struct console ttyprintk_console = {
175+ .name = "ttyprintk",
176+ .device = ttyprintk_console_device,
177+};
178+
166179 static int __init ttyprintk_init(void)
167180 {
168181 int ret;
@@ -195,6 +208,8 @@ static int __init ttyprintk_init(void) · 26 unmodified lines
195208 goto error;
196209 }
197210
211+ register_console(&ttyprintk_console);
212+
198213 return 0;
199214
200215 error:
@@ -205,6 +220,7 @@ error: · 4 unmodified lines
205220
206221 static void __exit ttyprintk_exit(void)
207222 {
223+ unregister_console(&ttyprintk_console);
208224 tty_unregister_driver(ttyprintk_driver);
209225 tty_driver_kref_put(ttyprintk_driver);
210226 tty_port_destroy(&tpk_port.port);
drivers/tty/amiserial.c+0−2
@@ -588,10 +588,8 @@ static void change_speed(struct tty_struct *tty, struct serial_state *info, · 587 unmodified lines
588588 }
589589 if (!(cflag & PARODD))
590590 cval |= UART_LCR_EPAR;
591−#ifdef CMSPAR
592591 if (cflag & CMSPAR)
593592 cval |= UART_LCR_SPAR;
594−#endif
595593
596594 /* Determine divisor based on baud rate */
597595 baud = tty_get_baud_rate(tty);
drivers/tty/goldfish.c+2−0
@@ -405,6 +405,7 @@ static int goldfish_tty_probe(struct platform_device *pdev) · 404 unmodified lines
405405 err_tty_register_device_failed:
406406 free_irq(irq, qtty);
407407 err_dec_line_count:
408+ tty_port_destroy(&qtty->port);
408409 goldfish_tty_current_line_count--;
409410 if (goldfish_tty_current_line_count == 0)
410411 goldfish_tty_delete_driver();
@@ -426,6 +427,7 @@ static int goldfish_tty_remove(struct platform_device *pdev) · 15 unmodified lines
426427 iounmap(qtty->base);
427428 qtty->base = NULL;
428429 free_irq(qtty->irq, pdev);
430+ tty_port_destroy(&qtty->port);
429431 goldfish_tty_current_line_count--;
430432 if (goldfish_tty_current_line_count == 0)
431433 goldfish_tty_delete_driver();
drivers/tty/hvc/Kconfig+19−0
@@ -87,6 +87,25 @@ config HVC_DCC · 86 unmodified lines
8787 driver. This console is used through a JTAG only on ARM. If you don't have
8888 a JTAG then you probably don't want this option.
8989
90+config HVC_DCC_SERIALIZE_SMP
91+ bool "Use DCC only on CPU core 0"
92+ depends on SMP && HVC_DCC
93+ help
94+ This is a DEBUG option to serialize all console input and output to CPU 0.
95+ Some external debuggers, do not handle reads/writes from/to DCC on more
96+ than one CPU core. Each core has its own DCC device registers, so when a
97+ CPU core reads or writes from/to DCC, it only accesses its own DCC device.
98+ Since kernel code can run on any CPU core, every time the kernel wants to
99+ write to the console, it might write to a different DCC.
100+
101+ In SMP mode, external debuggers create multiple windows, and each window
102+ shows the DCC output only from that core's DCC. The result is that
103+ console output is either lost or scattered across windows.
104+
105+ Enable this option only if you are sure that you do not need features like
106+ CPU hotplug to work. For example, during early chipset bringups without
107+ debug serial console support. If unsure, say N.
108+
90109 config HVC_RISCV_SBI
91110 bool "RISC-V SBI console support"
92111 depends on RISCV_SBI_V01
drivers/tty/hvc/hvc_dcc.c+190−4
@@ -1,10 +1,15 @@
11 // SPDX-License-Identifier: GPL-2.0
2−/* Copyright (c) 2010, 2014 The Linux Foundation. All rights reserved. */
2+/* Copyright (c) 2010, 2014, 2022 The Linux Foundation. All rights reserved. */
33
44 #include <linux/console.h>
5+#include <linux/cpu.h>
6+#include <linux/cpumask.h>
57 #include <linux/init.h>
8+#include <linux/kfifo.h>
69 #include <linux/serial.h>
710 #include <linux/serial_core.h>
11+#include <linux/smp.h>
12+#include <linux/spinlock.h>
813
914 #include <asm/dcc.h>
1015 #include <asm/processor.h>
@@ -15,6 +20,15 @@ · 4 unmodified lines
1520 #define DCC_STATUS_RX (1 << 30)
1621 #define DCC_STATUS_TX (1 << 29)
1722
23+#define DCC_INBUF_SIZE 128
24+#define DCC_OUTBUF_SIZE 1024
25+
26+/* Lock to serialize access to DCC fifo */
27+static DEFINE_SPINLOCK(dcc_lock);
28+
29+static DEFINE_KFIFO(inbuf, unsigned char, DCC_INBUF_SIZE);
30+static DEFINE_KFIFO(outbuf, unsigned char, DCC_OUTBUF_SIZE);
31+
1832 static void dcc_uart_console_putchar(struct uart_port *port, unsigned char ch)
1933 {
2034 while (__dcc_getstatus() & DCC_STATUS_TX)
@@ -67,24 +81,176 @@ static int hvc_dcc_get_chars(uint32_t vt, char *buf, int count) · 46 unmodified lines
6781 return i;
6882 }
6983
84+/*
85+ * Check if the DCC is enabled. If CONFIG_HVC_DCC_SERIALIZE_SMP is enabled,
86+ * then we assume then this function will be called first on core0. That way,
87+ * dcc_core0_available will be true only if it's available on core0.
88+ */
7089 static bool hvc_dcc_check(void)
7190 {
7291 unsigned long time = jiffies + (HZ / 10);
92+ static bool dcc_core0_available;
93+
94+ /*
95+ * If we're not on core 0, but we previously confirmed that DCC is
96+ * active, then just return true.
97+ */
98+ int cpu = get_cpu();
99+
100+ if (IS_ENABLED(CONFIG_HVC_DCC_SERIALIZE_SMP) && cpu && dcc_core0_available) {
101+ put_cpu();
102+ return true;
103+ }
104+
105+ put_cpu();
73106
74107 /* Write a test character to check if it is handled */
75108 __dcc_putchar('\n');
76109
77110 while (time_is_after_jiffies(time)) {
78− if (!(__dcc_getstatus() & DCC_STATUS_TX))
111+ if (!(__dcc_getstatus() & DCC_STATUS_TX)) {
112+ dcc_core0_available = true;
79113 return true;
114+ }
80115 }
81116
82117 return false;
83118 }
84119
120+/*
121+ * Workqueue function that writes the output FIFO to the DCC on core 0.
122+ */
123+static void dcc_put_work(struct work_struct *work)
124+{
125+ unsigned char ch;
126+ unsigned long irqflags;
127+
128+ spin_lock_irqsave(&dcc_lock, irqflags);
129+
130+ /* While there's data in the output FIFO, write it to the DCC */
131+ while (kfifo_get(&outbuf, &ch))
132+ hvc_dcc_put_chars(0, &ch, 1);
133+
134+ /* While we're at it, check for any input characters */
135+ while (!kfifo_is_full(&inbuf)) {
136+ if (!hvc_dcc_get_chars(0, &ch, 1))
137+ break;
138+ kfifo_put(&inbuf, ch);
139+ }
140+
141+ spin_unlock_irqrestore(&dcc_lock, irqflags);
142+}
143+
144+static DECLARE_WORK(dcc_pwork, dcc_put_work);
145+
146+/*
147+ * Workqueue function that reads characters from DCC and puts them into the
148+ * input FIFO.
149+ */
150+static void dcc_get_work(struct work_struct *work)
151+{
152+ unsigned char ch;
153+ unsigned long irqflags;
154+
155+ /*
156+ * Read characters from DCC and put them into the input FIFO, as
157+ * long as there is room and we have characters to read.
158+ */
159+ spin_lock_irqsave(&dcc_lock, irqflags);
160+
161+ while (!kfifo_is_full(&inbuf)) {
162+ if (!hvc_dcc_get_chars(0, &ch, 1))
163+ break;
164+ kfifo_put(&inbuf, ch);
165+ }
166+ spin_unlock_irqrestore(&dcc_lock, irqflags);
167+}
168+
169+static DECLARE_WORK(dcc_gwork, dcc_get_work);
170+
171+/*
172+ * Write characters directly to the DCC if we're on core 0 and the FIFO
173+ * is empty, or write them to the FIFO if we're not.
174+ */
175+static int hvc_dcc0_put_chars(u32 vt, const char *buf, int count)
176+{
177+ int len;
178+ unsigned long irqflags;
179+
180+ if (!IS_ENABLED(CONFIG_HVC_DCC_SERIALIZE_SMP))
181+ return hvc_dcc_put_chars(vt, buf, count);
182+
183+ spin_lock_irqsave(&dcc_lock, irqflags);
184+ if (smp_processor_id() || (!kfifo_is_empty(&outbuf))) {
185+ len = kfifo_in(&outbuf, buf, count);
186+ spin_unlock_irqrestore(&dcc_lock, irqflags);
187+
188+ /*
189+ * We just push data to the output FIFO, so schedule the
190+ * workqueue that will actually write that data to DCC.
191+ * CPU hotplug is disabled in dcc_init so CPU0 cannot be
192+ * offlined after the cpu online check.
193+ */
194+ if (cpu_online(0))
195+ schedule_work_on(0, &dcc_pwork);
196+
197+ return len;
198+ }
199+
200+ /*
201+ * If we're already on core 0, and the FIFO is empty, then just
202+ * write the data to DCC.
203+ */
204+ len = hvc_dcc_put_chars(vt, buf, count);
205+ spin_unlock_irqrestore(&dcc_lock, irqflags);
206+
207+ return len;
208+}
209+
210+/*
211+ * Read characters directly from the DCC if we're on core 0 and the FIFO
212+ * is empty, or read them from the FIFO if we're not.
213+ */
214+static int hvc_dcc0_get_chars(u32 vt, char *buf, int count)
215+{
216+ int len;
217+ unsigned long irqflags;
218+
219+ if (!IS_ENABLED(CONFIG_HVC_DCC_SERIALIZE_SMP))
220+ return hvc_dcc_get_chars(vt, buf, count);
221+
222+ spin_lock_irqsave(&dcc_lock, irqflags);
223+
224+ if (smp_processor_id() || (!kfifo_is_empty(&inbuf))) {
225+ len = kfifo_out(&inbuf, buf, count);
226+ spin_unlock_irqrestore(&dcc_lock, irqflags);
227+
228+ /*
229+ * If the FIFO was empty, there may be characters in the DCC
230+ * that we haven't read yet. Schedule a workqueue to fill
231+ * the input FIFO, so that the next time this function is
232+ * called, we'll have data. CPU hotplug is disabled in dcc_init
233+ * so CPU0 cannot be offlined after the cpu online check.
234+ */
235+ if (!len && cpu_online(0))
236+ schedule_work_on(0, &dcc_gwork);
237+
238+ return len;
239+ }
240+
241+ /*
242+ * If we're already on core 0, and the FIFO is empty, then just
243+ * read the data from DCC.
244+ */
245+ len = hvc_dcc_get_chars(vt, buf, count);
246+ spin_unlock_irqrestore(&dcc_lock, irqflags);
247+
248+ return len;
249+}
250+
85251 static const struct hv_ops hvc_dcc_get_put_ops = {
86− .get_chars = hvc_dcc_get_chars,
87− .put_chars = hvc_dcc_put_chars,
252+ .get_chars = hvc_dcc0_get_chars,
253+ .put_chars = hvc_dcc0_put_chars,
88254 };
89255
90256 static int __init hvc_dcc_console_init(void)
@@ -108,6 +274,26 @@ static int __init hvc_dcc_init(void) · 17 unmodified lines
108274 if (!hvc_dcc_check())
109275 return -ENODEV;
110276
277+ if (IS_ENABLED(CONFIG_HVC_DCC_SERIALIZE_SMP)) {
278+ pr_warn("\n");
279+ pr_warn("********************************************************************\n");
280+ pr_warn("** NOTICE NOTICE NOTICE NOTICE NOTICE NOTICE NOTICE **\n");
281+ pr_warn("** **\n");
282+ pr_warn("** HVC_DCC_SERIALIZE_SMP SUPPORT HAS BEEN ENABLED IN THIS KERNEL **\n");
283+ pr_warn("** **\n");
284+ pr_warn("** This means that this is a DEBUG kernel and unsafe for **\n");
285+ pr_warn("** production use and has important feature like CPU hotplug **\n");
286+ pr_warn("** disabled. **\n");
287+ pr_warn("** **\n");
288+ pr_warn("** If you see this message and you are not debugging the **\n");
289+ pr_warn("** kernel, report this immediately to your vendor! **\n");
290+ pr_warn("** **\n");
291+ pr_warn("** NOTICE NOTICE NOTICE NOTICE NOTICE NOTICE NOTICE **\n");
292+ pr_warn("********************************************************************\n");
293+
294+ cpu_hotplug_disable();
295+ }
296+
111297 p = hvc_alloc(0, 0, &hvc_dcc_get_put_ops, 128);
112298
113299 return PTR_ERR_OR_ZERO(p);
drivers/tty/hvc/hvc_opal.c+3−3
@@ -13,12 +13,12 @@ · 12 unmodified lines
1313 #include <linux/slab.h>
1414 #include <linux/console.h>
1515 #include <linux/of.h>
16+#include <linux/of_irq.h>
1617 #include <linux/of_platform.h>
1718 #include <linux/export.h>
1819 #include <linux/interrupt.h>
1920
2021 #include <asm/hvconsole.h>
21−#include <asm/prom.h>
2222 #include <asm/firmware.h>
2323 #include <asm/hvsi.h>
2424 #include <asm/udbg.h>
@@ -342,9 +342,9 @@ void __init hvc_opal_init_early(void) · 317 unmodified lines
342342 * path, so we hard wire it
343343 */
344344 opal = of_find_node_by_path("/ibm,opal/consoles");
345− if (opal)
345+ if (opal) {
346346 pr_devel("hvc_opal: Found consoles in new location\n");
347− if (!opal) {
347+ } else {
348348 opal = of_find_node_by_path("/ibm,opal");
349349 if (opal)
350350 pr_devel("hvc_opal: "
drivers/tty/hvc/hvc_vio.c+1−1
@@ -28,10 +28,10 @@ · 27 unmodified lines
2828 #include <linux/delay.h>
2929 #include <linux/slab.h>
3030 #include <linux/console.h>
31+#include <linux/of.h>
3132
3233 #include <asm/hvconsole.h>
3334 #include <asm/vio.h>
34−#include <asm/prom.h>
3535 #include <asm/hvsi.h>
3636 #include <asm/udbg.h>
3737 #include <asm/machdep.h>
drivers/tty/hvc/hvcs.c+2−3
@@ -581,10 +581,9 @@ static int hvcs_io(struct hvcs_struct *hvcsd) · 580 unmodified lines
581581
582582 spin_unlock_irqrestore(&hvcsd->lock, flags);
583583 /* This is synch -- FIXME :js: it is not! */
584− if(got)
584+ if (got)
585585 tty_flip_buffer_push(&hvcsd->port);
586−
587− if (!got) {
586+ else {
588587 /* Do this _after_ the flip_buffer_push */
589588 spin_lock_irqsave(&hvcsd->lock, flags);
590589 vio_enable_interrupts(hvcsd->vdev);
drivers/tty/hvc/hvsi.c+1−1
@@ -26,13 +26,13 @@ · 25 unmodified lines
2626 #include <linux/module.h>
2727 #include <linux/major.h>
2828 #include <linux/kernel.h>
29+#include <linux/of_irq.h>
2930 #include <linux/spinlock.h>
3031 #include <linux/sysrq.h>
3132 #include <linux/tty.h>
3233 #include <linux/tty_flip.h>
3334 #include <asm/hvcall.h>
3435 #include <asm/hvconsole.h>
35−#include <asm/prom.h>
3636 #include <linux/uaccess.h>
3737 #include <asm/vio.h>
3838 #include <asm/param.h>
drivers/tty/mxser.c+2−3
@@ -528,7 +528,6 @@ static int mxser_set_baud(struct tty_struct *tty, speed_t newspd) · 527 unmodified lines
528528 outb(quot >> 8, info->ioaddr + UART_DLM); /* MS of divisor */
529529 outb(cval, info->ioaddr + UART_LCR); /* reset DLAB */
530530
531−#ifdef BOTHER
532531 if (C_BAUD(tty) == BOTHER) {
533532 quot = MXSER_BAUD_BASE % newspd;
534533 quot *= 8;
@@ -539,9 +538,9 @@ static int mxser_set_baud(struct tty_struct *tty, speed_t newspd) · 4 unmodified lines
539538 quot /= newspd;
540539
541540 mxser_set_must_enum_value(info->ioaddr, quot);
542− } else
543−#endif
541+ } else {
544542 mxser_set_must_enum_value(info->ioaddr, 0);
543+ }
545544
546545 return 0;
547546 }
drivers/tty/n_gsm.c+24−13
@@ -444,6 +444,25 @@ static u8 gsm_encode_modem(const struct gsm_dlci *dlci) · 443 unmodified lines
444444 return modembits;
445445 }
446446
447+static void gsm_hex_dump_bytes(const char *fname, const u8 *data,
448+ unsigned long len)
449+{
450+ char *prefix;
451+
452+ if (!fname) {
453+ print_hex_dump(KERN_INFO, "", DUMP_PREFIX_NONE, 16, 1, data, len,
454+ true);
455+ return;
456+ }
457+
458+ prefix = kasprintf(GFP_KERNEL, "%s: ", fname);
459+ if (!prefix)
460+ return;
461+ print_hex_dump(KERN_INFO, prefix, DUMP_PREFIX_OFFSET, 16, 1, data, len,
462+ true);
463+ kfree(prefix);
464+}
465+
447466 /**
448467 * gsm_print_packet - display a frame for debug
449468 * @hdr: header to print before decode
@@ -508,7 +527,7 @@ static void gsm_print_packet(const char *hdr, int addr, int cr, · 58 unmodified lines
508527 else
509528 pr_cont("(F)");
510529
511− print_hex_dump_bytes("", DUMP_PREFIX_NONE, data, dlen);
530+ gsm_hex_dump_bytes(NULL, data, dlen);
512531 }
513532
514533
@@ -698,9 +717,7 @@ static void gsm_data_kick(struct gsm_mux *gsm, struct gsm_dlci *dlci) · 183 unmodified lines
698717 }
699718
700719 if (debug & 4)
701− print_hex_dump_bytes("gsm_data_kick: ",
702− DUMP_PREFIX_OFFSET,
703− gsm->txframe, len);
720+ gsm_hex_dump_bytes(__func__, gsm->txframe, len);
704721 if (gsmld_output(gsm, gsm->txframe, len) <= 0)
705722 break;
706723 /* FIXME: Can eliminate one SOF in many more cases */
@@ -749,7 +766,7 @@ static void __gsm_data_queue(struct gsm_dlci *dlci, struct gsm_msg *msg) · 42 unmodified lines
749766
750767 *--dp = msg->ctrl;
751768 if (gsm->initiator)
752− *--dp = (msg->addr << 2) | 2 | EA;
769+ *--dp = (msg->addr << 2) | CR | EA;
753770 else
754771 *--dp = (msg->addr << 2) | EA;
755772 *fcs = gsm_fcs_add_block(INIT_FCS, dp , msg->data - dp);
@@ -1907,10 +1924,6 @@ static void gsm_queue(struct gsm_mux *gsm) · 1151 unmodified lines
19071924 case UI|PF:
19081925 case UIH:
19091926 case UIH|PF:
1910−#if 0
1911− if (cr)
1912− goto invalid;
1913−#endif
19141927 if (dlci == NULL || dlci->state != DLCI_OPEN) {
19151928 gsm_command(gsm, address, DM|PF);
19161929 return;
@@ -2448,8 +2461,7 @@ static int gsmld_output(struct gsm_mux *gsm, u8 *data, int len) · 531 unmodified lines
24482461 return -ENOSPC;
24492462 }
24502463 if (debug & 4)
2451− print_hex_dump_bytes("gsmld_output: ", DUMP_PREFIX_OFFSET,
2452− data, len);
2464+ gsm_hex_dump_bytes(__func__, data, len);
24532465 return gsm->tty->ops->write(gsm->tty, data, len);
24542466 }
24552467
@@ -2525,8 +2537,7 @@ static void gsmld_receive_buf(struct tty_struct *tty, const unsigned char *cp, · 69 unmodified lines
25252537 char flags = TTY_NORMAL;
25262538
25272539 if (debug & 4)
2528− print_hex_dump_bytes("gsmld_receive: ", DUMP_PREFIX_OFFSET,
2529− cp, count);
2540+ gsm_hex_dump_bytes(__func__, cp, count);
25302541
25312542 for (; count; count--, cp++) {
25322543 if (fp)
drivers/tty/n_tty.c+61−12
@@ -1220,21 +1220,34 @@ n_tty_receive_signal_char(struct tty_struct *tty, int signal, unsigned char c) · 1219 unmodified lines
12201220 process_echoes(tty);
12211221 }
12221222
1223+static bool n_tty_is_char_flow_ctrl(struct tty_struct *tty, unsigned char c)
1224+{
1225+ return c == START_CHAR(tty) || c == STOP_CHAR(tty);
1226+}
1227+
1228+/* Returns true if c is consumed as flow-control character */
1229+static bool n_tty_receive_char_flow_ctrl(struct tty_struct *tty, unsigned char c)
1230+{
1231+ if (!n_tty_is_char_flow_ctrl(tty, c))
1232+ return false;
1233+
1234+ if (c == START_CHAR(tty)) {
1235+ start_tty(tty);
1236+ process_echoes(tty);
1237+ return true;
1238+ }
1239+
1240+ /* STOP_CHAR */
1241+ stop_tty(tty);
1242+ return true;
1243+}
1244+
12231245 static void n_tty_receive_char_special(struct tty_struct *tty, unsigned char c)
12241246 {
12251247 struct n_tty_data *ldata = tty->disc_data;
12261248
1227− if (I_IXON(tty)) {
1228− if (c == START_CHAR(tty)) {
1229− start_tty(tty);
1230− process_echoes(tty);
1231− return;
1232− }
1233− if (c == STOP_CHAR(tty)) {
1234− stop_tty(tty);
1235− return;
1236− }
1237− }
1249+ if (I_IXON(tty) && n_tty_receive_char_flow_ctrl(tty, c))
1250+ return;
12381251
12391252 if (L_ISIG(tty)) {
12401253 if (c == INTR_CHAR(tty)) {
@@ -1975,6 +1988,35 @@ static bool canon_copy_from_read_buf(struct tty_struct *tty, · 734 unmodified lines
19751988 return ldata->read_tail != canon_head;
19761989 }
19771990
1991+/*
1992+ * If we finished a read at the exact location of an
1993+ * EOF (special EOL character that's a __DISABLED_CHAR)
1994+ * in the stream, silently eat the EOF.
1995+ */
1996+static void canon_skip_eof(struct tty_struct *tty)
1997+{
1998+ struct n_tty_data *ldata = tty->disc_data;
1999+ size_t tail, canon_head;
2000+
2001+ canon_head = smp_load_acquire(&ldata->canon_head);
2002+ tail = ldata->read_tail;
2003+
2004+ // No data?
2005+ if (tail == canon_head)
2006+ return;
2007+
2008+ // See if the tail position is EOF in the circular buffer
2009+ tail &= (N_TTY_BUF_SIZE - 1);
2010+ if (!test_bit(tail, ldata->read_flags))
2011+ return;
2012+ if (read_buf(ldata, tail) != __DISABLED_CHAR)
2013+ return;
2014+
2015+ // Clear the EOL bit, skip the EOF char.
2016+ clear_bit(tail, ldata->read_flags);
2017+ smp_store_release(&ldata->read_tail, ldata->read_tail + 1);
2018+}
2019+
19782020 /**
19792021 * job_control - check job control
19802022 * @tty: tty
@@ -2045,7 +2087,14 @@ static ssize_t n_tty_read(struct tty_struct *tty, struct file *file, · 64 unmodified lines
20452087 */
20462088 if (*cookie) {
20472089 if (ldata->icanon && !L_EXTPROC(tty)) {
2048− if (canon_copy_from_read_buf(tty, &kb, &nr))
2090+ /*
2091+ * If we have filled the user buffer, see
2092+ * if we should skip an EOF character before
2093+ * releasing the lock and returning done.
2094+ */
2095+ if (!nr)
2096+ canon_skip_eof(tty);
2097+ else if (canon_copy_from_read_buf(tty, &kb, &nr))
20492098 return kb - kbuf;
20502099 } else {
20512100 if (copy_from_read_buf(tty, &kb, &nr))
drivers/tty/serial/8250/8250.h+41−0
@@ -17,6 +17,8 @@ · 16 unmodified lines
1717 struct uart_8250_dma {
1818 int (*tx_dma)(struct uart_8250_port *p);
1919 int (*rx_dma)(struct uart_8250_port *p);
20+ void (*prepare_tx_dma)(struct uart_8250_port *p);
21+ void (*prepare_rx_dma)(struct uart_8250_port *p);
2022
2123 /* Filter function */
2224 dma_filter_fn fn;
@@ -83,6 +85,7 @@ struct serial8250_config { · 60 unmodified lines
8385 #define UART_CAP_MINI BIT(17) /* Mini UART on BCM283X family lacks:
8486 * STOP PARITY EPAR SPAR WLEN5 WLEN6
8587 */
88+#define UART_CAP_NOTEMT BIT(18) /* UART without interrupt on TEMT available */
8689
8790 #define UART_BUG_QUOT BIT(0) /* UART has buggy quot LSB */
8891 #define UART_BUG_TXEN BIT(1) /* UART has buggy TX IIR status */
@@ -120,6 +123,28 @@ static inline void serial_out(struct uart_8250_port *up, int offset, int value) · 31 unmodified lines
120123 up->port.serial_out(&up->port, offset, value);
121124 }
122125
126+/*
127+ * For the 16C950
128+ */
129+static void serial_icr_write(struct uart_8250_port *up, int offset, int value)
130+{
131+ serial_out(up, UART_SCR, offset);
132+ serial_out(up, UART_ICR, value);
133+}
134+
135+static unsigned int __maybe_unused serial_icr_read(struct uart_8250_port *up,
136+ int offset)
137+{
138+ unsigned int value;
139+
140+ serial_icr_write(up, UART_ACR, up->acr | UART_ACR_ICRRD);
141+ serial_out(up, UART_SCR, offset);
142+ value = serial_in(up, UART_ICR);
143+ serial_icr_write(up, UART_ACR, up->acr);
144+
145+ return value;
146+}
147+
123148 void serial8250_clear_and_reinit_fifos(struct uart_8250_port *p);
124149
125150 static inline int serial_dl_read(struct uart_8250_port *up)
@@ -302,6 +327,22 @@ extern int serial8250_rx_dma(struct uart_8250_port *); · 176 unmodified lines
302327 extern void serial8250_rx_dma_flush(struct uart_8250_port *);
303328 extern int serial8250_request_dma(struct uart_8250_port *);
304329 extern void serial8250_release_dma(struct uart_8250_port *);
330+
331+static inline void serial8250_do_prepare_tx_dma(struct uart_8250_port *p)
332+{
333+ struct uart_8250_dma *dma = p->dma;
334+
335+ if (dma->prepare_tx_dma)
336+ dma->prepare_tx_dma(p);
337+}
338+
339+static inline void serial8250_do_prepare_rx_dma(struct uart_8250_port *p)
340+{
341+ struct uart_8250_dma *dma = p->dma;
342+
343+ if (dma->prepare_rx_dma)
344+ dma->prepare_rx_dma(p);
345+}
305346 #else
306347 static inline int serial8250_tx_dma(struct uart_8250_port *p)
307348 {
drivers/tty/serial/8250/8250_aspeed_vuart.c+2−0
@@ -429,6 +429,8 @@ static int aspeed_vuart_probe(struct platform_device *pdev) · 428 unmodified lines
429429 timer_setup(&vuart->unthrottle_timer, aspeed_vuart_unthrottle_exp, 0);
430430
431431 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
432+ if (!res)
433+ return -EINVAL;
432434
433435 memset(&port, 0, sizeof(port));
434436 port.port.private_data = vuart;
drivers/tty/serial/8250/8250_core.c+0−1
@@ -32,7 +32,6 @@ · 31 unmodified lines
3232 #include <linux/mutex.h>
3333 #include <linux/slab.h>
3434 #include <linux/uaccess.h>
35−#include <linux/pm_runtime.h>
3635 #include <linux/io.h>
3736 #ifdef CONFIG_SPARC
3837 #include <linux/sunserialcore.h>
drivers/tty/serial/8250/8250_dma.c+5−2
@@ -34,7 +34,7 @@ static void __dma_tx_complete(void *param) · 33 unmodified lines
3434 uart_write_wakeup(&p->port);
3535
3636 ret = serial8250_tx_dma(p);
37− if (ret)
37+ if (ret || !dma->tx_running)
3838 serial8250_set_THRI(p);
3939
4040 spin_unlock_irqrestore(&p->port.lock, flags);
@@ -80,12 +80,13 @@ int serial8250_tx_dma(struct uart_8250_port *p) · 39 unmodified lines
8080
8181 if (uart_tx_stopped(&p->port) || uart_circ_empty(xmit)) {
8282 /* We have been called from __dma_tx_complete() */
83− serial8250_rpm_put_tx(p);
8483 return 0;
8584 }
8685
8786 dma->tx_size = CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE);
8887
88+ serial8250_do_prepare_tx_dma(p);
89+
8990 desc = dmaengine_prep_slave_single(dma->txchan,
9091 dma->tx_addr + xmit->tail,
9192 dma->tx_size, DMA_MEM_TO_DEV,
@@ -123,6 +124,8 @@ int serial8250_rx_dma(struct uart_8250_port *p) · 31 unmodified lines
123124 if (dma->rx_running)
124125 return 0;
125126
127+ serial8250_do_prepare_rx_dma(p);
128+
126129 desc = dmaengine_prep_slave_single(dma->rxchan, dma->rx_addr,
127130 dma->rx_size, DMA_DEV_TO_MEM,
128131 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
drivers/tty/serial/8250/8250_dw.c+149−80
@@ -12,13 +12,13 @@ · 11 unmodified lines
1212 #include <linux/delay.h>
1313 #include <linux/device.h>
1414 #include <linux/io.h>
15+#include <linux/mod_devicetable.h>
1516 #include <linux/module.h>
1617 #include <linux/serial_8250.h>
1718 #include <linux/serial_reg.h>
1819 #include <linux/of.h>
19−#include <linux/of_irq.h>
20−#include <linux/of_platform.h>
2120 #include <linux/platform_device.h>
21+#include <linux/property.h>
2222 #include <linux/workqueue.h>
2323 #include <linux/notifier.h>
2424 #include <linux/slab.h>
@@ -33,30 +33,28 @@ · 8 unmodified lines
3333
3434 /* Offsets for the DesignWare specific registers */
3535 #define DW_UART_USR 0x1f /* UART Status Register */
36+#define DW_UART_DMASA 0xa8 /* DMA Software Ack */
37+
38+#define OCTEON_UART_USR 0x27 /* UART Status Register */
39+
40+#define RZN1_UART_TDMACR 0x10c /* DMA Control Register Transmit Mode */
41+#define RZN1_UART_RDMACR 0x110 /* DMA Control Register Receive Mode */
3642
3743 /* DesignWare specific register fields */
3844 #define DW_UART_MCR_SIRE BIT(6)
3945
40−struct dw8250_data {
41− struct dw8250_port_data data;
46+/* Renesas specific register fields */
47+#define RZN1_UART_xDMACR_DMA_EN BIT(0)
48+#define RZN1_UART_xDMACR_1_WORD_BURST (0 << 1)
49+#define RZN1_UART_xDMACR_4_WORD_BURST (1 << 1)
50+#define RZN1_UART_xDMACR_8_WORD_BURST (3 << 1)
51+#define RZN1_UART_xDMACR_BLK_SZ(x) ((x) << 3)
4252
43− u8 usr_reg;
44− int msr_mask_on;
45− int msr_mask_off;
46− struct clk *clk;
47− struct clk *pclk;
48− struct notifier_block clk_notifier;
49− struct work_struct clk_work;
50− struct reset_control *rst;
51−
52− unsigned int skip_autocfg:1;
53− unsigned int uart_16550_compatible:1;
54−};
55−
56−static inline struct dw8250_data *to_dw8250_data(struct dw8250_port_data *data)
57−{
58− return container_of(data, struct dw8250_data, data);
59−}
53+/* Quirks */
54+#define DW_UART_QUIRK_OCTEON BIT(0)
55+#define DW_UART_QUIRK_ARMADA_38X BIT(1)
56+#define DW_UART_QUIRK_SKIP_SET_RATE BIT(2)
57+#define DW_UART_QUIRK_IS_DMA_FC BIT(3)
6058
6159 static inline struct dw8250_data *clk_to_dw8250_data(struct notifier_block *nb)
6260 {
@@ -238,6 +236,8 @@ static int dw8250_handle_irq(struct uart_port *p) · 175 unmodified lines
238236 struct uart_8250_port *up = up_to_u8250p(p);
239237 struct dw8250_data *d = to_dw8250_data(p->private_data);
240238 unsigned int iir = p->serial_in(p, UART_IIR);
239+ bool rx_timeout = (iir & 0x3f) == UART_IIR_RX_TIMEOUT;
240+ unsigned int quirks = d->pdata->quirks;
241241 unsigned int status;
242242 unsigned long flags;
243243
@@ -251,7 +251,7 @@ static int dw8250_handle_irq(struct uart_port *p) · 7 unmodified lines
251251 * This problem has only been observed so far when not in DMA mode
252252 * so we limit the workaround only to non-DMA mode.
253253 */
254− if (!up->dma && ((iir & 0x3f) == UART_IIR_RX_TIMEOUT)) {
254+ if (!up->dma && rx_timeout) {
255255 spin_lock_irqsave(&p->lock, flags);
256256 status = p->serial_in(p, UART_LSR);
257257
@@ -261,12 +261,21 @@ static int dw8250_handle_irq(struct uart_port *p) · 3 unmodified lines
261261 spin_unlock_irqrestore(&p->lock, flags);
262262 }
263263
264+ /* Manually stop the Rx DMA transfer when acting as flow controller */
265+ if (quirks & DW_UART_QUIRK_IS_DMA_FC && up->dma && up->dma->rx_running && rx_timeout) {
266+ status = p->serial_in(p, UART_LSR);
267+ if (status & (UART_LSR_DR | UART_LSR_BI)) {
268+ dw8250_writel_ext(p, RZN1_UART_RDMACR, 0);
269+ dw8250_writel_ext(p, DW_UART_DMASA, 1);
270+ }
271+ }
272+
264273 if (serial8250_handle_irq(p, iir))
265274 return 1;
266275
267276 if ((iir & UART_IIR_BUSY) == UART_IIR_BUSY) {
268277 /* Clear the USR */
269− (void)p->serial_in(p, d->usr_reg);
278+ (void)p->serial_in(p, d->pdata->usr_reg);
270279
271280 return 1;
272281 }
@@ -384,11 +393,48 @@ static bool dw8250_idma_filter(struct dma_chan *chan, void *param) · 111 unmodified lines
384393 return param == chan->device->dev;
385394 }
386395
396+static u32 dw8250_rzn1_get_dmacr_burst(int max_burst)
397+{
398+ if (max_burst >= 8)
399+ return RZN1_UART_xDMACR_8_WORD_BURST;
400+ else if (max_burst >= 4)
401+ return RZN1_UART_xDMACR_4_WORD_BURST;
402+ else
403+ return RZN1_UART_xDMACR_1_WORD_BURST;
404+}
405+
406+static void dw8250_prepare_tx_dma(struct uart_8250_port *p)
407+{
408+ struct uart_port *up = &p->port;
409+ struct uart_8250_dma *dma = p->dma;
410+ u32 val;
411+
412+ dw8250_writel_ext(up, RZN1_UART_TDMACR, 0);
413+ val = dw8250_rzn1_get_dmacr_burst(dma->txconf.dst_maxburst) |
414+ RZN1_UART_xDMACR_BLK_SZ(dma->tx_size) |
415+ RZN1_UART_xDMACR_DMA_EN;
416+ dw8250_writel_ext(up, RZN1_UART_TDMACR, val);
417+}
418+
419+static void dw8250_prepare_rx_dma(struct uart_8250_port *p)
420+{
421+ struct uart_port *up = &p->port;
422+ struct uart_8250_dma *dma = p->dma;
423+ u32 val;
424+
425+ dw8250_writel_ext(up, RZN1_UART_RDMACR, 0);
426+ val = dw8250_rzn1_get_dmacr_burst(dma->rxconf.src_maxburst) |
427+ RZN1_UART_xDMACR_BLK_SZ(dma->rx_size) |
428+ RZN1_UART_xDMACR_DMA_EN;
429+ dw8250_writel_ext(up, RZN1_UART_RDMACR, val);
430+}
431+
387432 static void dw8250_quirks(struct uart_port *p, struct dw8250_data *data)
388433 {
389434 struct device_node *np = p->dev->of_node;
390435
391436 if (np) {
437+ unsigned int quirks = data->pdata->quirks;
392438 int id;
393439
394440 /* get index of serial line, if found in DT aliases */
@@ -396,12 +442,11 @@ static void dw8250_quirks(struct uart_port *p, struct dw8250_data *data) · 1 unmodified line
396442 if (id >= 0)
397443 p->line = id;
398444 #ifdef CONFIG_64BIT
399− if (of_device_is_compatible(np, "cavium,octeon-3860-uart")) {
445+ if (quirks & DW_UART_QUIRK_OCTEON) {
400446 p->serial_in = dw8250_serial_inq;
401447 p->serial_out = dw8250_serial_outq;
402448 p->flags = UPF_SKIP_TEST | UPF_SHARE_IRQ | UPF_FIXED_TYPE;
403449 p->type = PORT_OCTEON;
404− data->usr_reg = 0x27;
405450 data->skip_autocfg = true;
406451 }
407452 #endif
@@ -412,10 +457,16 @@ static void dw8250_quirks(struct uart_port *p, struct dw8250_data *data) · 4 unmodified lines
412457 p->serial_out = dw8250_serial_out32be;
413458 }
414459
415− if (of_device_is_compatible(np, "marvell,armada-38x-uart"))
460+ if (quirks & DW_UART_QUIRK_ARMADA_38X)
416461 p->serial_out = dw8250_serial_out38x;
417− if (of_device_is_compatible(np, "starfive,jh7100-uart"))
462+ if (quirks & DW_UART_QUIRK_SKIP_SET_RATE)
418463 p->set_termios = dw8250_do_set_termios;
464+ if (quirks & DW_UART_QUIRK_IS_DMA_FC) {
465+ data->data.dma.txconf.device_fc = 1;
466+ data->data.dma.rxconf.device_fc = 1;
467+ data->data.dma.prepare_tx_dma = dw8250_prepare_tx_dma;
468+ data->data.dma.prepare_rx_dma = dw8250_prepare_rx_dma;
469+ }
419470
420471 } else if (acpi_dev_present("APMC0D08", NULL, -1)) {
421472 p->iotype = UPIO_MEM32;
@@ -433,21 +484,30 @@ static void dw8250_quirks(struct uart_port *p, struct dw8250_data *data) · 11 unmodified lines
433484 }
434485 }
435486
487+static void dw8250_clk_disable_unprepare(void *data)
488+{
489+ clk_disable_unprepare(data);
490+}
491+
492+static void dw8250_reset_control_assert(void *data)
493+{
494+ reset_control_assert(data);
495+}
496+
436497 static int dw8250_probe(struct platform_device *pdev)
437498 {
438499 struct uart_8250_port uart = {}, *up = &uart;
439− struct resource *regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
440500 struct uart_port *p = &up->port;
441501 struct device *dev = &pdev->dev;
442502 struct dw8250_data *data;
503+ struct resource *regs;
443504 int irq;
444505 int err;
445506 u32 val;
446507
447− if (!regs) {
448− dev_err(dev, "no registers defined\n");
449− return -EINVAL;
450− }
508+ regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
509+ if (!regs)
510+ return dev_err_probe(dev, -EINVAL, "no registers defined\n");
451511
452512 irq = platform_get_irq(pdev, 0);
453513 if (irq < 0)
@@ -476,7 +536,7 @@ static int dw8250_probe(struct platform_device *pdev) · 22 unmodified lines
476536 return -ENOMEM;
477537
478538 data->data.dma.fn = dw8250_fallback_dma_filter;
479− data->usr_reg = DW_UART_USR;
539+ data->pdata = device_get_match_data(p->dev);
480540 p->private_data = &data->data;
481541
482542 data->uart_16550_compatible = device_property_read_bool(dev,
@@ -532,37 +592,41 @@ static int dw8250_probe(struct platform_device *pdev) · 49 unmodified lines
532592
533593 err = clk_prepare_enable(data->clk);
534594 if (err)
535− dev_warn(dev, "could not enable optional baudclk: %d\n", err);
595+ return dev_err_probe(dev, err, "could not enable optional baudclk\n");
596+
597+ err = devm_add_action_or_reset(dev, dw8250_clk_disable_unprepare, data->clk);
598+ if (err)
599+ return err;
536600
537601 if (data->clk)
538602 p->uartclk = clk_get_rate(data->clk);
539603
540604 /* If no clock rate is defined, fail. */
541− if (!p->uartclk) {
542− dev_err(dev, "clock rate not defined\n");
543− err = -EINVAL;
544− goto err_clk;
545− }
605+ if (!p->uartclk)
606+ return dev_err_probe(dev, -EINVAL, "clock rate not defined\n");
546607
547608 data->pclk = devm_clk_get_optional(dev, "apb_pclk");
548− if (IS_ERR(data->pclk)) {
549− err = PTR_ERR(data->pclk);
550− goto err_clk;
551− }
609+ if (IS_ERR(data->pclk))
610+ return PTR_ERR(data->pclk);
552611
553612 err = clk_prepare_enable(data->pclk);
554− if (err) {
555− dev_err(dev, "could not enable apb_pclk\n");
556− goto err_clk;
557− }
613+ if (err)
614+ return dev_err_probe(dev, err, "could not enable apb_pclk\n");
615+
616+ err = devm_add_action_or_reset(dev, dw8250_clk_disable_unprepare, data->pclk);
617+ if (err)
618+ return err;
558619
559620 data->rst = devm_reset_control_get_optional_exclusive(dev, NULL);
560− if (IS_ERR(data->rst)) {
561− err = PTR_ERR(data->rst);
562− goto err_pclk;
563− }
621+ if (IS_ERR(data->rst))
622+ return PTR_ERR(data->rst);
623+
564624 reset_control_deassert(data->rst);
565625
626+ err = devm_add_action_or_reset(dev, dw8250_reset_control_assert, data->rst);
627+ if (err)
628+ return err;
629+
566630 dw8250_quirks(p, data);
567631
568632 /* If the Busy Functionality is not implemented, don't handle it */
@@ -580,10 +644,8 @@ static int dw8250_probe(struct platform_device *pdev) · 11 unmodified lines
580644 }
581645
582646 data->data.line = serial8250_register_8250_port(up);
583− if (data->data.line < 0) {
584− err = data->data.line;
585− goto err_reset;
586− }
647+ if (data->data.line < 0)
648+ return data->data.line;
587649
588650 /*
589651 * Some platforms may provide a reference clock shared between several
@@ -593,9 +655,8 @@ static int dw8250_probe(struct platform_device *pdev) · 3 unmodified lines
593655 if (data->clk) {
594656 err = clk_notifier_register(data->clk, &data->clk_notifier);
595657 if (err)
596− dev_warn(p->dev, "Failed to set the clock notifier\n");
597− else
598− queue_work(system_unbound_wq, &data->clk_work);
658+ return dev_err_probe(dev, err, "Failed to set the clock notifier\n");
659+ queue_work(system_unbound_wq, &data->clk_work);
599660 }
600661
601662 platform_set_drvdata(pdev, data);
@@ -604,17 +665,6 @@ static int dw8250_probe(struct platform_device *pdev) · 2 unmodified lines
604665 pm_runtime_enable(dev);
605666
606667 return 0;
607−
608−err_reset:
609− reset_control_assert(data->rst);
610−
611−err_pclk:
612− clk_disable_unprepare(data->pclk);
613−
614−err_clk:
615− clk_disable_unprepare(data->clk);
616−
617− return err;
618668 }
619669
620670 static int dw8250_remove(struct platform_device *pdev)
@@ -632,12 +682,6 @@ static int dw8250_remove(struct platform_device *pdev) · 11 unmodified lines
632682
633683 serial8250_unregister_port(data->data.line);
634684
635− reset_control_assert(data->rst);
636−
637− clk_disable_unprepare(data->pclk);
638−
639− clk_disable_unprepare(data->clk);
640−
641685 pm_runtime_disable(dev);
642686 pm_runtime_put_noidle(dev);
643687
@@ -693,12 +737,37 @@ static const struct dev_pm_ops dw8250_pm_ops = { · 49 unmodified lines
693737 SET_RUNTIME_PM_OPS(dw8250_runtime_suspend, dw8250_runtime_resume, NULL)
694738 };
695739
740+static const struct dw8250_platform_data dw8250_dw_apb = {
741+ .usr_reg = DW_UART_USR,
742+};
743+
744+static const struct dw8250_platform_data dw8250_octeon_3860_data = {
745+ .usr_reg = OCTEON_UART_USR,
746+ .quirks = DW_UART_QUIRK_OCTEON,
747+};
748+
749+static const struct dw8250_platform_data dw8250_armada_38x_data = {
750+ .usr_reg = DW_UART_USR,
751+ .quirks = DW_UART_QUIRK_ARMADA_38X,
752+};
753+
754+static const struct dw8250_platform_data dw8250_renesas_rzn1_data = {
755+ .usr_reg = DW_UART_USR,
756+ .cpr_val = 0x00012f32,
757+ .quirks = DW_UART_QUIRK_IS_DMA_FC,
758+};
759+
760+static const struct dw8250_platform_data dw8250_starfive_jh7100_data = {
761+ .usr_reg = DW_UART_USR,
762+ .quirks = DW_UART_QUIRK_SKIP_SET_RATE,
763+};
764+
696765 static const struct of_device_id dw8250_of_match[] = {
697− { .compatible = "snps,dw-apb-uart" },
698− { .compatible = "cavium,octeon-3860-uart" },
699− { .compatible = "marvell,armada-38x-uart" },
700− { .compatible = "renesas,rzn1-uart" },
701− { .compatible = "starfive,jh7100-uart" },
766+ { .compatible = "snps,dw-apb-uart", .data = &dw8250_dw_apb },
767+ { .compatible = "cavium,octeon-3860-uart", .data = &dw8250_octeon_3860_data },
768+ { .compatible = "marvell,armada-38x-uart", .data = &dw8250_armada_38x_data },
769+ { .compatible = "renesas,rzn1-uart", .data = &dw8250_renesas_rzn1_data },
770+ { .compatible = "starfive,jh7100-uart", .data = &dw8250_starfive_jh7100_data },
702771 { /* Sentinel */ }
703772 };
704773 MODULE_DEVICE_TABLE(of, dw8250_of_match);
drivers/tty/serial/8250/8250_dwlib.c+96−20
@@ -2,19 +2,32 @@ · 1 unmodified line
22 /* Synopsys DesignWare 8250 library. */
33
44 #include <linux/bitops.h>
5+#include <linux/bitfield.h>
56 #include <linux/device.h>
6−#include <linux/io.h>
77 #include <linux/kernel.h>
8+#include <linux/property.h>
89 #include <linux/serial_8250.h>
910 #include <linux/serial_core.h>
1011
1112 #include "8250_dwlib.h"
1213
1314 /* Offsets for the DesignWare specific registers */
15+#define DW_UART_TCR 0xac /* Transceiver Control Register (RS485) */
16+#define DW_UART_DE_EN 0xb0 /* Driver Output Enable Register */
17+#define DW_UART_RE_EN 0xb4 /* Receiver Output Enable Register */
1418 #define DW_UART_DLF 0xc0 /* Divisor Latch Fraction Register */
1519 #define DW_UART_CPR 0xf4 /* Component Parameter Register */
1620 #define DW_UART_UCV 0xf8 /* UART Component Version */
1721
22+/* Transceiver Control Register bits */
23+#define DW_UART_TCR_RS485_EN BIT(0)
24+#define DW_UART_TCR_RE_POL BIT(1)
25+#define DW_UART_TCR_DE_POL BIT(2)
26+#define DW_UART_TCR_XFER_MODE GENMASK(4, 3)
27+#define DW_UART_TCR_XFER_MODE_DE_DURING_RE FIELD_PREP(DW_UART_TCR_XFER_MODE, 0)
28+#define DW_UART_TCR_XFER_MODE_SW_DE_OR_RE FIELD_PREP(DW_UART_TCR_XFER_MODE, 1)
29+#define DW_UART_TCR_XFER_MODE_DE_OR_RE FIELD_PREP(DW_UART_TCR_XFER_MODE, 2)
30+
1831 /* Component Parameter Register bits */
1932 #define DW_UART_CPR_ABP_DATA_WIDTH (3 << 0)
2033 #define DW_UART_CPR_AFCE_MODE (1 << 4)
@@ -32,21 +45,6 @@ · 11 unmodified lines
3245 /* Helper for FIFO size calculation */
3346 #define DW_UART_CPR_FIFO_SIZE(a) (((a >> 16) & 0xff) * 16)
3447
35−static inline u32 dw8250_readl_ext(struct uart_port *p, int offset)
36−{
37− if (p->iotype == UPIO_MEM32BE)
38− return ioread32be(p->membase + offset);
39− return readl(p->membase + offset);
40−}
41−
42−static inline void dw8250_writel_ext(struct uart_port *p, int offset, u32 reg)
43−{
44− if (p->iotype == UPIO_MEM32BE)
45− iowrite32be(reg, p->membase + offset);
46− else
47− writel(reg, p->membase + offset);
48−}
49−
5048 /*
5149 * divisor = div(I) + div(F)
5250 * "I" means integer, "F" means fractional
@@ -87,11 +85,87 @@ void dw8250_do_set_termios(struct uart_port *p, struct ktermios *termios, struct · 34 unmodified lines
8785 }
8886 EXPORT_SYMBOL_GPL(dw8250_do_set_termios);
8987
88+static int dw8250_rs485_config(struct uart_port *p, struct serial_rs485 *rs485)
89+{
90+ u32 tcr;
91+
92+ tcr = dw8250_readl_ext(p, DW_UART_TCR);
93+ tcr &= ~DW_UART_TCR_XFER_MODE;
94+
95+ if (rs485->flags & SER_RS485_ENABLED) {
96+ /* Clear unsupported flags. */
97+ rs485->flags &= SER_RS485_ENABLED | SER_RS485_RX_DURING_TX |
98+ SER_RS485_RTS_ON_SEND | SER_RS485_RTS_AFTER_SEND;
99+ tcr |= DW_UART_TCR_RS485_EN;
100+
101+ if (rs485->flags & SER_RS485_RX_DURING_TX) {
102+ tcr |= DW_UART_TCR_XFER_MODE_DE_DURING_RE;
103+ } else {
104+ /* HW does not support same DE level for tx and rx */
105+ if (!(rs485->flags & SER_RS485_RTS_ON_SEND) ==
106+ !(rs485->flags & SER_RS485_RTS_AFTER_SEND))
107+ return -EINVAL;
108+
109+ tcr |= DW_UART_TCR_XFER_MODE_DE_OR_RE;
110+ }
111+ dw8250_writel_ext(p, DW_UART_DE_EN, 1);
112+ dw8250_writel_ext(p, DW_UART_RE_EN, 1);
113+ } else {
114+ rs485->flags = 0;
115+
116+ tcr &= ~DW_UART_TCR_RS485_EN;
117+ }
118+
119+ /* Reset to default polarity */
120+ tcr |= DW_UART_TCR_DE_POL;
121+ tcr &= ~DW_UART_TCR_RE_POL;
122+
123+ if (!(rs485->flags & SER_RS485_RTS_ON_SEND))
124+ tcr &= ~DW_UART_TCR_DE_POL;
125+ if (device_property_read_bool(p->dev, "rs485-rx-active-high"))
126+ tcr |= DW_UART_TCR_RE_POL;
127+
128+ dw8250_writel_ext(p, DW_UART_TCR, tcr);
129+
130+ rs485->delay_rts_before_send = 0;
131+ rs485->delay_rts_after_send = 0;
132+
133+ p->rs485 = *rs485;
134+
135+ return 0;
136+}
137+
138+/*
139+ * Tests if RE_EN register can have non-zero value to see if RS-485 HW support
140+ * is present.
141+ */
142+static bool dw8250_detect_rs485_hw(struct uart_port *p)
143+{
144+ u32 reg;
145+
146+ dw8250_writel_ext(p, DW_UART_RE_EN, 1);
147+ reg = dw8250_readl_ext(p, DW_UART_RE_EN);
148+ dw8250_writel_ext(p, DW_UART_RE_EN, 0);
149+ return reg;
150+}
151+
90152 void dw8250_setup_port(struct uart_port *p)
91153 {
154+ struct dw8250_port_data *pd = p->private_data;
155+ struct dw8250_data *data = to_dw8250_data(pd);
92156 struct uart_8250_port *up = up_to_u8250p(p);
93157 u32 reg;
94158
159+ pd->hw_rs485_support = dw8250_detect_rs485_hw(p);
160+ if (pd->hw_rs485_support) {
161+ p->rs485_config = dw8250_rs485_config;
162+ } else {
163+ p->rs485_config = serial8250_em485_config;
164+ up->rs485_start_tx = serial8250_em485_start_tx;
165+ up->rs485_stop_tx = serial8250_em485_stop_tx;
166+ }
167+ up->capabilities |= UART_CAP_NOTEMT;
168+
95169 /*
96170 * If the Component Version Register returns zero, we know that
97171 * ADDITIONAL_FEATURES are not enabled. No need to go any further.
@@ -108,14 +182,16 @@ void dw8250_setup_port(struct uart_port *p) · 10 unmodified lines
108182 dw8250_writel_ext(p, DW_UART_DLF, 0);
109183
110184 if (reg) {
111− struct dw8250_port_data *d = p->private_data;
112−
113− d->dlf_size = fls(reg);
185+ pd->dlf_size = fls(reg);
114186 p->get_divisor = dw8250_get_divisor;
115187 p->set_divisor = dw8250_set_divisor;
116188 }
117189
118190 reg = dw8250_readl_ext(p, DW_UART_CPR);
191+ if (!reg) {
192+ reg = data->pdata->cpr_val;
193+ dev_dbg(p->dev, "CPR is not available, using 0x%08x instead\n", reg);
194+ }
119195 if (!reg)
120196 return;
121197
@@ -124,7 +200,7 @@ void dw8250_setup_port(struct uart_port *p) · 2 unmodified lines
124200 p->type = PORT_16550A;
125201 p->flags |= UPF_FIXED_TYPE;
126202 p->fifosize = DW_UART_CPR_FIFO_SIZE(reg);
127− up->capabilities = UART_CAP_FIFO;
203+ up->capabilities = UART_CAP_FIFO | UART_CAP_NOTEMT;
128204 }
129205
130206 if (reg & DW_UART_CPR_AFCE_MODE)
drivers/tty/serial/8250/8250_dwlib.h+51−0
@@ -1,10 +1,16 @@
11 /* SPDX-License-Identifier: GPL-2.0+ */
22 /* Synopsys DesignWare 8250 library header file. */
33
4+#include <linux/io.h>
5+#include <linux/notifier.h>
46 #include <linux/types.h>
7+#include <linux/workqueue.h>
58
69 #include "8250.h"
710
11+struct clk;
12+struct reset_control;
13+
814 struct dw8250_port_data {
915 /* Port properties */
1016 int line;
@@ -14,7 +20,52 @@ struct dw8250_port_data { · 3 unmodified lines
1420
1521 /* Hardware configuration */
1622 u8 dlf_size;
23+
24+ /* RS485 variables */
25+ bool hw_rs485_support;
26+};
27+
28+struct dw8250_platform_data {
29+ u8 usr_reg;
30+ u32 cpr_val;
31+ unsigned int quirks;
32+};
33+
34+struct dw8250_data {
35+ struct dw8250_port_data data;
36+ const struct dw8250_platform_data *pdata;
37+
38+ int msr_mask_on;
39+ int msr_mask_off;
40+ struct clk *clk;
41+ struct clk *pclk;
42+ struct notifier_block clk_notifier;
43+ struct work_struct clk_work;
44+ struct reset_control *rst;
45+
46+ unsigned int skip_autocfg:1;
47+ unsigned int uart_16550_compatible:1;
1748 };
1849
1950 void dw8250_do_set_termios(struct uart_port *p, struct ktermios *termios, struct ktermios *old);
2051 void dw8250_setup_port(struct uart_port *p);
52+
53+static inline struct dw8250_data *to_dw8250_data(struct dw8250_port_data *data)
54+{
55+ return container_of(data, struct dw8250_data, data);
56+}
57+
58+static inline u32 dw8250_readl_ext(struct uart_port *p, int offset)
59+{
60+ if (p->iotype == UPIO_MEM32BE)
61+ return ioread32be(p->membase + offset);
62+ return readl(p->membase + offset);
63+}
64+
65+static inline void dw8250_writel_ext(struct uart_port *p, int offset, u32 reg)
66+{
67+ if (p->iotype == UPIO_MEM32BE)
68+ iowrite32be(reg, p->membase + offset);
69+ else
70+ writel(reg, p->membase + offset);
71+}
drivers/tty/serial/8250/8250_fintek.c+4−4
@@ -200,12 +200,12 @@ static int fintek_8250_rs485_config(struct uart_port *port, · 199 unmodified lines
200200 if (!pdata)
201201 return -EINVAL;
202202
203− /* Hardware do not support same RTS level on send and receive */
204− if (!(rs485->flags & SER_RS485_RTS_ON_SEND) ==
205− !(rs485->flags & SER_RS485_RTS_AFTER_SEND))
206− return -EINVAL;
207203
208204 if (rs485->flags & SER_RS485_ENABLED) {
205+ /* Hardware do not support same RTS level on send and receive */
206+ if (!(rs485->flags & SER_RS485_RTS_ON_SEND) ==
207+ !(rs485->flags & SER_RS485_RTS_AFTER_SEND))
208+ return -EINVAL;
209209 memset(rs485->padding, 0, sizeof(rs485->padding));
210210 config |= RS485_URA;
211211 } else {
drivers/tty/serial/8250/8250_mtk.c+0−7
@@ -54,9 +54,6 @@ · 53 unmodified lines
5454 #define MTK_UART_TX_TRIGGER 1
5555 #define MTK_UART_RX_TRIGGER MTK_UART_RX_SIZE
5656
57−#define MTK_UART_FEATURE_SEL 39 /* Feature Selection register */
58−#define MTK_UART_FEAT_NEWRMAP BIT(0) /* Use new register map */
59−
6057 #define MTK_UART_XON1 40 /* I/O: Xon character 1 */
6158 #define MTK_UART_XOFF1 42 /* I/O: Xoff character 1 */
6259
@@ -575,10 +572,6 @@ static int mtk8250_probe(struct platform_device *pdev) · 512 unmodified lines
575572 uart.dma = data->dma;
576573 #endif
577574
578− /* Set AP UART new register map */
579− writel(MTK_UART_FEAT_NEWRMAP, uart.port.membase +
580− (MTK_UART_FEATURE_SEL << uart.port.regshift));
581−
582575 /* Disable Rate Fix function */
583576 writel(0x0, uart.port.membase +
584577 (MTK_UART_RATE_FIX << uart.port.regshift));
drivers/tty/serial/8250/8250_of.c+2−0
@@ -326,6 +326,8 @@ static const struct of_device_id of_platform_serial_table[] = { · 325 unmodified lines
326326 .data = (void *)PORT_ALTR_16550_F64, },
327327 { .compatible = "altr,16550-FIFO128",
328328 .data = (void *)PORT_ALTR_16550_F128, },
329+ { .compatible = "fsl,16550-FIFO64",
330+ .data = (void *)PORT_16550A_FSL64, },
329331 { .compatible = "mediatek,mtk-btif",
330332 .data = (void *)PORT_MTK_BTIF, },
331333 { .compatible = "mrvl,mmp-uart",
drivers/tty/serial/8250/8250_pci.c+335−145
@@ -11,6 +11,7 @@ · 10 unmodified lines
1111 #include <linux/pci.h>
1212 #include <linux/string.h>
1313 #include <linux/kernel.h>
14+#include <linux/math.h>
1415 #include <linux/slab.h>
1516 #include <linux/delay.h>
1617 #include <linux/tty.h>
@@ -994,41 +995,29 @@ static void pci_ite887x_exit(struct pci_dev *dev) · 977 unmodified lines
994995 }
995996
996997 /*
997− * EndRun Technologies.
998− * Determine the number of ports available on the device.
998+ * Oxford Semiconductor Inc.
999+ * Check if an OxSemi device is part of the Tornado range of devices.
9991000 */
10001001 #define PCI_VENDOR_ID_ENDRUN 0x7401
10011002 #define PCI_DEVICE_ID_ENDRUN_1588 0xe100
10021003
1003−static int pci_endrun_init(struct pci_dev *dev)
1004+static bool pci_oxsemi_tornado_p(struct pci_dev *dev)
10041005 {
1005− u8 __iomem *p;
1006− unsigned long deviceID;
1007− unsigned int number_uarts = 0;
1006+ /* OxSemi Tornado devices are all 0xCxxx */
1007+ if (dev->vendor == PCI_VENDOR_ID_OXSEMI &&
1008+ (dev->device & 0xf000) != 0xc000)
1009+ return false;
10081010
1009− /* EndRun device is all 0xexxx */
1011+ /* EndRun devices are all 0xExxx */
10101012 if (dev->vendor == PCI_VENDOR_ID_ENDRUN &&
1011− (dev->device & 0xf000) != 0xe000)
1012− return 0;
1013−
1014− p = pci_iomap(dev, 0, 5);
1015− if (p == NULL)
1016− return -ENOMEM;
1013+ (dev->device & 0xf000) != 0xe000)
1014+ return false;
10171015
1018− deviceID = ioread32(p);
1019− /* EndRun device */
1020− if (deviceID == 0x07000200) {
1021− number_uarts = ioread8(p + 4);
1022− pci_dbg(dev, "%d ports detected on EndRun PCI Express device\n", number_uarts);
1023− }
1024− pci_iounmap(dev, p);
1025− return number_uarts;
1016+ return true;
10261017 }
10271018
10281019 /*
1029− * Oxford Semiconductor Inc.
1030− * Check that device is part of the Tornado range of devices, then determine
1031− * the number of ports available on the device.
1020+ * Determine the number of ports available on a Tornado device.
10321021 */
10331022 static int pci_oxsemi_tornado_init(struct pci_dev *dev)
10341023 {
@@ -1036,9 +1025,7 @@ static int pci_oxsemi_tornado_init(struct pci_dev *dev) · 1 unmodified line
10361025 unsigned long deviceID;
10371026 unsigned int number_uarts = 0;
10381027
1039− /* OxSemi Tornado devices are all 0xCxxx */
1040− if (dev->vendor == PCI_VENDOR_ID_OXSEMI &&
1041− (dev->device & 0xF000) != 0xC000)
1028+ if (!pci_oxsemi_tornado_p(dev))
10421029 return 0;
10431030
10441031 p = pci_iomap(dev, 0, 5);
@@ -1049,12 +1036,217 @@ static int pci_oxsemi_tornado_init(struct pci_dev *dev) · 4 unmodified lines
10491036 /* Tornado device */
10501037 if (deviceID == 0x07000200) {
10511038 number_uarts = ioread8(p + 4);
1052− pci_dbg(dev, "%d ports detected on Oxford PCI Express device\n", number_uarts);
1039+ pci_dbg(dev, "%d ports detected on %s PCI Express device\n",
1040+ number_uarts,
1041+ dev->vendor == PCI_VENDOR_ID_ENDRUN ?
1042+ "EndRun" : "Oxford");
10531043 }
10541044 pci_iounmap(dev, p);
10551045 return number_uarts;
10561046 }
10571047
1048+/* Tornado-specific constants for the TCR and CPR registers; see below. */
1049+#define OXSEMI_TORNADO_TCR_MASK 0xf
1050+#define OXSEMI_TORNADO_CPR_MASK 0x1ff
1051+#define OXSEMI_TORNADO_CPR_MIN 0x008
1052+#define OXSEMI_TORNADO_CPR_DEF 0x10f
1053+
1054+/*
1055+ * Determine the oversampling rate, the clock prescaler, and the clock
1056+ * divisor for the requested baud rate. The clock rate is 62.5 MHz,
1057+ * which is four times the baud base, and the prescaler increments in
1058+ * steps of 1/8. Therefore to make calculations on integers we need
1059+ * to use a scaled clock rate, which is the baud base multiplied by 32
1060+ * (or our assumed UART clock rate multiplied by 2).
1061+ *
1062+ * The allowed oversampling rates are from 4 up to 16 inclusive (values
1063+ * from 0 to 3 inclusive map to 16). Likewise the clock prescaler allows
1064+ * values between 1.000 and 63.875 inclusive (operation for values from
1065+ * 0.000 to 0.875 has not been specified). The clock divisor is the usual
1066+ * unsigned 16-bit integer.
1067+ *
1068+ * For the most accurate baud rate we use a table of predetermined
1069+ * oversampling rates and clock prescalers that records all possible
1070+ * products of the two parameters in the range from 4 up to 255 inclusive,
1071+ * and additionally 335 for the 1500000bps rate, with the prescaler scaled
1072+ * by 8. The table is sorted by the decreasing value of the oversampling
1073+ * rate and ties are resolved by sorting by the decreasing value of the
1074+ * product. This way preference is given to higher oversampling rates.
1075+ *
1076+ * We iterate over the table and choose the product of an oversampling
1077+ * rate and a clock prescaler that gives the lowest integer division
1078+ * result deviation, or if an exact integer divider is found we stop
1079+ * looking for it right away. We do some fixup if the resulting clock
1080+ * divisor required would be out of its unsigned 16-bit integer range.
1081+ *
1082+ * Finally we abuse the supposed fractional part returned to encode the
1083+ * 4-bit value of the oversampling rate and the 9-bit value of the clock
1084+ * prescaler which will end up in the TCR and CPR/CPR2 registers.
1085+ */
1086+static unsigned int pci_oxsemi_tornado_get_divisor(struct uart_port *port,
1087+ unsigned int baud,
1088+ unsigned int *frac)
1089+{
1090+ static u8 p[][2] = {
1091+ { 16, 14, }, { 16, 13, }, { 16, 12, }, { 16, 11, },
1092+ { 16, 10, }, { 16, 9, }, { 16, 8, }, { 15, 17, },
1093+ { 15, 16, }, { 15, 15, }, { 15, 14, }, { 15, 13, },
1094+ { 15, 12, }, { 15, 11, }, { 15, 10, }, { 15, 9, },
1095+ { 15, 8, }, { 14, 18, }, { 14, 17, }, { 14, 14, },
1096+ { 14, 13, }, { 14, 12, }, { 14, 11, }, { 14, 10, },
1097+ { 14, 9, }, { 14, 8, }, { 13, 19, }, { 13, 18, },
1098+ { 13, 17, }, { 13, 13, }, { 13, 12, }, { 13, 11, },
1099+ { 13, 10, }, { 13, 9, }, { 13, 8, }, { 12, 19, },
1100+ { 12, 18, }, { 12, 17, }, { 12, 11, }, { 12, 9, },
1101+ { 12, 8, }, { 11, 23, }, { 11, 22, }, { 11, 21, },
1102+ { 11, 20, }, { 11, 19, }, { 11, 18, }, { 11, 17, },
1103+ { 11, 11, }, { 11, 10, }, { 11, 9, }, { 11, 8, },
1104+ { 10, 25, }, { 10, 23, }, { 10, 20, }, { 10, 19, },
1105+ { 10, 17, }, { 10, 10, }, { 10, 9, }, { 10, 8, },
1106+ { 9, 27, }, { 9, 23, }, { 9, 21, }, { 9, 19, },
1107+ { 9, 18, }, { 9, 17, }, { 9, 9, }, { 9, 8, },
1108+ { 8, 31, }, { 8, 29, }, { 8, 23, }, { 8, 19, },
1109+ { 8, 17, }, { 8, 8, }, { 7, 35, }, { 7, 31, },
1110+ { 7, 29, }, { 7, 25, }, { 7, 23, }, { 7, 21, },
1111+ { 7, 19, }, { 7, 17, }, { 7, 15, }, { 7, 14, },
1112+ { 7, 13, }, { 7, 12, }, { 7, 11, }, { 7, 10, },
1113+ { 7, 9, }, { 7, 8, }, { 6, 41, }, { 6, 37, },
1114+ { 6, 31, }, { 6, 29, }, { 6, 23, }, { 6, 19, },
1115+ { 6, 17, }, { 6, 13, }, { 6, 11, }, { 6, 10, },
1116+ { 6, 9, }, { 6, 8, }, { 5, 67, }, { 5, 47, },
1117+ { 5, 43, }, { 5, 41, }, { 5, 37, }, { 5, 31, },
1118+ { 5, 29, }, { 5, 25, }, { 5, 23, }, { 5, 19, },
1119+ { 5, 17, }, { 5, 15, }, { 5, 13, }, { 5, 11, },
1120+ { 5, 10, }, { 5, 9, }, { 5, 8, }, { 4, 61, },
1121+ { 4, 59, }, { 4, 53, }, { 4, 47, }, { 4, 43, },
1122+ { 4, 41, }, { 4, 37, }, { 4, 31, }, { 4, 29, },
1123+ { 4, 23, }, { 4, 19, }, { 4, 17, }, { 4, 13, },
1124+ { 4, 9, }, { 4, 8, },
1125+ };
1126+ /* Scale the quotient for comparison to get the fractional part. */
1127+ const unsigned int quot_scale = 65536;
1128+ unsigned int sclk = port->uartclk * 2;
1129+ unsigned int sdiv = DIV_ROUND_CLOSEST(sclk, baud);
1130+ unsigned int best_squot;
1131+ unsigned int squot;
1132+ unsigned int quot;
1133+ u16 cpr;
1134+ u8 tcr;
1135+ int i;
1136+
1137+ /* Old custom speed handling. */
1138+ if (baud == 38400 && (port->flags & UPF_SPD_MASK) == UPF_SPD_CUST) {
1139+ unsigned int cust_div = port->custom_divisor;
1140+
1141+ quot = cust_div & UART_DIV_MAX;
1142+ tcr = (cust_div >> 16) & OXSEMI_TORNADO_TCR_MASK;
1143+ cpr = (cust_div >> 20) & OXSEMI_TORNADO_CPR_MASK;
1144+ if (cpr < OXSEMI_TORNADO_CPR_MIN)
1145+ cpr = OXSEMI_TORNADO_CPR_DEF;
1146+ } else {
1147+ best_squot = quot_scale;
1148+ for (i = 0; i < ARRAY_SIZE(p); i++) {
1149+ unsigned int spre;
1150+ unsigned int srem;
1151+ u8 cp;
1152+ u8 tc;
1153+
1154+ tc = p[i][0];
1155+ cp = p[i][1];
1156+ spre = tc * cp;
1157+
1158+ srem = sdiv % spre;
1159+ if (srem > spre / 2)
1160+ srem = spre - srem;
1161+ squot = DIV_ROUND_CLOSEST(srem * quot_scale, spre);
1162+
1163+ if (srem == 0) {
1164+ tcr = tc;
1165+ cpr = cp;
1166+ quot = sdiv / spre;
1167+ break;
1168+ } else if (squot < best_squot) {
1169+ best_squot = squot;
1170+ tcr = tc;
1171+ cpr = cp;
1172+ quot = DIV_ROUND_CLOSEST(sdiv, spre);
1173+ }
1174+ }
1175+ while (tcr <= (OXSEMI_TORNADO_TCR_MASK + 1) >> 1 &&
1176+ quot % 2 == 0) {
1177+ quot >>= 1;
1178+ tcr <<= 1;
1179+ }
1180+ while (quot > UART_DIV_MAX) {
1181+ if (tcr <= (OXSEMI_TORNADO_TCR_MASK + 1) >> 1) {
1182+ quot >>= 1;
1183+ tcr <<= 1;
1184+ } else if (cpr <= OXSEMI_TORNADO_CPR_MASK >> 1) {
1185+ quot >>= 1;
1186+ cpr <<= 1;
1187+ } else {
1188+ quot = quot * cpr / OXSEMI_TORNADO_CPR_MASK;
1189+ cpr = OXSEMI_TORNADO_CPR_MASK;
1190+ }
1191+ }
1192+ }
1193+
1194+ *frac = (cpr << 8) | (tcr & OXSEMI_TORNADO_TCR_MASK);
1195+ return quot;
1196+}
1197+
1198+/*
1199+ * Set the oversampling rate in the transmitter clock cycle register (TCR),
1200+ * the clock prescaler in the clock prescaler register (CPR and CPR2), and
1201+ * the clock divisor in the divisor latch (DLL and DLM). Note that for
1202+ * backwards compatibility any write to CPR clears CPR2 and therefore CPR
1203+ * has to be written first, followed by CPR2, which occupies the location
1204+ * of CKS used with earlier UART designs.
1205+ */
1206+static void pci_oxsemi_tornado_set_divisor(struct uart_port *port,
1207+ unsigned int baud,
1208+ unsigned int quot,
1209+ unsigned int quot_frac)
1210+{
1211+ struct uart_8250_port *up = up_to_u8250p(port);
1212+ u8 cpr2 = quot_frac >> 16;
1213+ u8 cpr = quot_frac >> 8;
1214+ u8 tcr = quot_frac;
1215+
1216+ serial_icr_write(up, UART_TCR, tcr);
1217+ serial_icr_write(up, UART_CPR, cpr);
1218+ serial_icr_write(up, UART_CKS, cpr2);
1219+ serial8250_do_set_divisor(port, baud, quot, 0);
1220+}
1221+
1222+/*
1223+ * For Tornado devices we force MCR[7] set for the Divide-by-M N/8 baud rate
1224+ * generator prescaler (CPR and CPR2). Otherwise no prescaler would be used.
1225+ */
1226+static void pci_oxsemi_tornado_set_mctrl(struct uart_port *port,
1227+ unsigned int mctrl)
1228+{
1229+ struct uart_8250_port *up = up_to_u8250p(port);
1230+
1231+ up->mcr |= UART_MCR_CLKSEL;
1232+ serial8250_do_set_mctrl(port, mctrl);
1233+}
1234+
1235+static int pci_oxsemi_tornado_setup(struct serial_private *priv,
1236+ const struct pciserial_board *board,
1237+ struct uart_8250_port *up, int idx)
1238+{
1239+ struct pci_dev *dev = priv->dev;
1240+
1241+ if (pci_oxsemi_tornado_p(dev)) {
1242+ up->port.get_divisor = pci_oxsemi_tornado_get_divisor;
1243+ up->port.set_divisor = pci_oxsemi_tornado_set_divisor;
1244+ up->port.set_mctrl = pci_oxsemi_tornado_set_mctrl;
1245+ }
1246+
1247+ return pci_default_setup(priv, board, up, idx);
1248+}
1249+
10581250 static int pci_asix_setup(struct serial_private *priv,
10591251 const struct pciserial_board *board,
10601252 struct uart_8250_port *port, int idx)
@@ -2244,7 +2436,7 @@ static struct pci_serial_quirk pci_serial_quirks[] = { · 1183 unmodified lines
22442436 .device = PCI_ANY_ID,
22452437 .subvendor = PCI_ANY_ID,
22462438 .subdevice = PCI_ANY_ID,
2247− .init = pci_endrun_init,
2439+ .init = pci_oxsemi_tornado_init,
22482440 .setup = pci_default_setup,
22492441 },
22502442 /*
@@ -2256,7 +2448,7 @@ static struct pci_serial_quirk pci_serial_quirks[] = { · 5 unmodified lines
22562448 .subvendor = PCI_ANY_ID,
22572449 .subdevice = PCI_ANY_ID,
22582450 .init = pci_oxsemi_tornado_init,
2259− .setup = pci_default_setup,
2451+ .setup = pci_oxsemi_tornado_setup,
22602452 },
22612453 {
22622454 .vendor = PCI_VENDOR_ID_MAINPINE,
@@ -2264,7 +2456,7 @@ static struct pci_serial_quirk pci_serial_quirks[] = { · 1 unmodified line
22642456 .subvendor = PCI_ANY_ID,
22652457 .subdevice = PCI_ANY_ID,
22662458 .init = pci_oxsemi_tornado_init,
2267− .setup = pci_default_setup,
2459+ .setup = pci_oxsemi_tornado_setup,
22682460 },
22692461 {
22702462 .vendor = PCI_VENDOR_ID_DIGI,
@@ -2272,7 +2464,7 @@ static struct pci_serial_quirk pci_serial_quirks[] = { · 1 unmodified line
22722464 .subvendor = PCI_SUBVENDOR_ID_IBM,
22732465 .subdevice = PCI_ANY_ID,
22742466 .init = pci_oxsemi_tornado_init,
2275− .setup = pci_default_setup,
2467+ .setup = pci_oxsemi_tornado_setup,
22762468 },
22772469 {
22782470 .vendor = PCI_VENDOR_ID_INTEL,
@@ -2589,7 +2781,7 @@ enum pci_board_num_t { · 310 unmodified lines
25892781 pbn_b0_2_1843200,
25902782 pbn_b0_4_1843200,
25912783
2592− pbn_b0_1_3906250,
2784+ pbn_b0_1_15625000,
25932785
25942786 pbn_b0_bt_1_115200,
25952787 pbn_b0_bt_2_115200,
@@ -2667,12 +2859,11 @@ enum pci_board_num_t { · 71 unmodified lines
26672859 pbn_panacom2,
26682860 pbn_panacom4,
26692861 pbn_plx_romulus,
2670− pbn_endrun_2_3906250,
26712862 pbn_oxsemi,
2672− pbn_oxsemi_1_3906250,
2673− pbn_oxsemi_2_3906250,
2674− pbn_oxsemi_4_3906250,
2675− pbn_oxsemi_8_3906250,
2863+ pbn_oxsemi_1_15625000,
2864+ pbn_oxsemi_2_15625000,
2865+ pbn_oxsemi_4_15625000,
2866+ pbn_oxsemi_8_15625000,
26762867 pbn_intel_i960,
26772868 pbn_sgi_ioc3,
26782869 pbn_computone_4,
@@ -2815,10 +3006,10 @@ static struct pciserial_board pci_boards[] = { · 136 unmodified lines
28153006 .uart_offset = 8,
28163007 },
28173008
2818− [pbn_b0_1_3906250] = {
3009+ [pbn_b0_1_15625000] = {
28193010 .flags = FL_BASE0,
28203011 .num_ports = 1,
2821− .base_baud = 3906250,
3012+ .base_baud = 15625000,
28223013 .uart_offset = 8,
28233014 },
28243015
@@ -3189,20 +3380,6 @@ static struct pciserial_board pci_boards[] = { · 364 unmodified lines
31893380 .first_offset = 0x03,
31903381 },
31913382
3192− /*
3193− * EndRun Technologies
3194− * Uses the size of PCI Base region 0 to
3195− * signal now many ports are available
3196− * 2 port 952 Uart support
3197− */
3198− [pbn_endrun_2_3906250] = {
3199− .flags = FL_BASE0,
3200− .num_ports = 2,
3201− .base_baud = 3906250,
3202− .uart_offset = 0x200,
3203− .first_offset = 0x1000,
3204− },
3205−
32063383 /*
32073384 * This board uses the size of PCI Base region 0 to
32083385 * signal now many ports are available
@@ -3213,31 +3390,31 @@ static struct pciserial_board pci_boards[] = { · 4 unmodified lines
32133390 .base_baud = 115200,
32143391 .uart_offset = 8,
32153392 },
3216− [pbn_oxsemi_1_3906250] = {
3393+ [pbn_oxsemi_1_15625000] = {
32173394 .flags = FL_BASE0,
32183395 .num_ports = 1,
3219− .base_baud = 3906250,
3396+ .base_baud = 15625000,
32203397 .uart_offset = 0x200,
32213398 .first_offset = 0x1000,
32223399 },
3223− [pbn_oxsemi_2_3906250] = {
3400+ [pbn_oxsemi_2_15625000] = {
32243401 .flags = FL_BASE0,
32253402 .num_ports = 2,
3226− .base_baud = 3906250,
3403+ .base_baud = 15625000,
32273404 .uart_offset = 0x200,
32283405 .first_offset = 0x1000,
32293406 },
3230− [pbn_oxsemi_4_3906250] = {
3407+ [pbn_oxsemi_4_15625000] = {
32313408 .flags = FL_BASE0,
32323409 .num_ports = 4,
3233− .base_baud = 3906250,
3410+ .base_baud = 15625000,
32343411 .uart_offset = 0x200,
32353412 .first_offset = 0x1000,
32363413 },
3237− [pbn_oxsemi_8_3906250] = {
3414+ [pbn_oxsemi_8_15625000] = {
32383415 .flags = FL_BASE0,
32393416 .num_ports = 8,
3240− .base_baud = 3906250,
3417+ .base_baud = 15625000,
32413418 .uart_offset = 0x200,
32423419 .first_offset = 0x1000,
32433420 },
@@ -3518,6 +3695,12 @@ static struct pciserial_board pci_boards[] = { · 274 unmodified lines
35183695 },
35193696 };
35203697
3698+#define REPORT_CONFIG(option) \
3699+ (IS_ENABLED(CONFIG_##option) ? 0 : (kernel_ulong_t)&#option)
3700+#define REPORT_8250_CONFIG(option) \
3701+ (IS_ENABLED(CONFIG_SERIAL_8250_##option) ? \
3702+ 0 : (kernel_ulong_t)&"SERIAL_8250_"#option)
3703+
35213704 static const struct pci_device_id blacklist[] = {
35223705 /* softmodems */
35233706 { PCI_VDEVICE(AL, 0x5457), }, /* ALi Corporation M5457 AC'97 Modem */
@@ -3525,40 +3708,43 @@ static const struct pci_device_id blacklist[] = { · 1 unmodified line
35253708 { PCI_DEVICE(0x1543, 0x3052), }, /* Si3052-based modem, default IDs */
35263709
35273710 /* multi-io cards handled by parport_serial */
3528− { PCI_DEVICE(0x4348, 0x7053), }, /* WCH CH353 2S1P */
3529− { PCI_DEVICE(0x4348, 0x5053), }, /* WCH CH353 1S1P */
3530− { PCI_DEVICE(0x1c00, 0x3250), }, /* WCH CH382 2S1P */
3711+ /* WCH CH353 2S1P */
3712+ { PCI_DEVICE(0x4348, 0x7053), 0, 0, REPORT_CONFIG(PARPORT_SERIAL), },
3713+ /* WCH CH353 1S1P */
3714+ { PCI_DEVICE(0x4348, 0x5053), 0, 0, REPORT_CONFIG(PARPORT_SERIAL), },
3715+ /* WCH CH382 2S1P */
3716+ { PCI_DEVICE(0x1c00, 0x3250), 0, 0, REPORT_CONFIG(PARPORT_SERIAL), },
35313717
35323718 /* Intel platforms with MID UART */
3533− { PCI_VDEVICE(INTEL, 0x081b), },
3534− { PCI_VDEVICE(INTEL, 0x081c), },
3535− { PCI_VDEVICE(INTEL, 0x081d), },
3536− { PCI_VDEVICE(INTEL, 0x1191), },
3537− { PCI_VDEVICE(INTEL, 0x18d8), },
3538− { PCI_VDEVICE(INTEL, 0x19d8), },
3719+ { PCI_VDEVICE(INTEL, 0x081b), REPORT_8250_CONFIG(MID), },
3720+ { PCI_VDEVICE(INTEL, 0x081c), REPORT_8250_CONFIG(MID), },
3721+ { PCI_VDEVICE(INTEL, 0x081d), REPORT_8250_CONFIG(MID), },
3722+ { PCI_VDEVICE(INTEL, 0x1191), REPORT_8250_CONFIG(MID), },
3723+ { PCI_VDEVICE(INTEL, 0x18d8), REPORT_8250_CONFIG(MID), },
3724+ { PCI_VDEVICE(INTEL, 0x19d8), REPORT_8250_CONFIG(MID), },
35393725
35403726 /* Intel platforms with DesignWare UART */
3541− { PCI_VDEVICE(INTEL, 0x0936), },
3542− { PCI_VDEVICE(INTEL, 0x0f0a), },
3543− { PCI_VDEVICE(INTEL, 0x0f0c), },
3544− { PCI_VDEVICE(INTEL, 0x228a), },
3545− { PCI_VDEVICE(INTEL, 0x228c), },
3546− { PCI_VDEVICE(INTEL, 0x4b96), },
3547− { PCI_VDEVICE(INTEL, 0x4b97), },
3548− { PCI_VDEVICE(INTEL, 0x4b98), },
3549− { PCI_VDEVICE(INTEL, 0x4b99), },
3550− { PCI_VDEVICE(INTEL, 0x4b9a), },
3551− { PCI_VDEVICE(INTEL, 0x4b9b), },
3552− { PCI_VDEVICE(INTEL, 0x9ce3), },
3553− { PCI_VDEVICE(INTEL, 0x9ce4), },
3727+ { PCI_VDEVICE(INTEL, 0x0936), REPORT_8250_CONFIG(LPSS), },
3728+ { PCI_VDEVICE(INTEL, 0x0f0a), REPORT_8250_CONFIG(LPSS), },
3729+ { PCI_VDEVICE(INTEL, 0x0f0c), REPORT_8250_CONFIG(LPSS), },
3730+ { PCI_VDEVICE(INTEL, 0x228a), REPORT_8250_CONFIG(LPSS), },
3731+ { PCI_VDEVICE(INTEL, 0x228c), REPORT_8250_CONFIG(LPSS), },
3732+ { PCI_VDEVICE(INTEL, 0x4b96), REPORT_8250_CONFIG(LPSS), },
3733+ { PCI_VDEVICE(INTEL, 0x4b97), REPORT_8250_CONFIG(LPSS), },
3734+ { PCI_VDEVICE(INTEL, 0x4b98), REPORT_8250_CONFIG(LPSS), },
3735+ { PCI_VDEVICE(INTEL, 0x4b99), REPORT_8250_CONFIG(LPSS), },
3736+ { PCI_VDEVICE(INTEL, 0x4b9a), REPORT_8250_CONFIG(LPSS), },
3737+ { PCI_VDEVICE(INTEL, 0x4b9b), REPORT_8250_CONFIG(LPSS), },
3738+ { PCI_VDEVICE(INTEL, 0x9ce3), REPORT_8250_CONFIG(LPSS), },
3739+ { PCI_VDEVICE(INTEL, 0x9ce4), REPORT_8250_CONFIG(LPSS), },
35543740
35553741 /* Exar devices */
3556− { PCI_VDEVICE(EXAR, PCI_ANY_ID), },
3557− { PCI_VDEVICE(COMMTECH, PCI_ANY_ID), },
3742+ { PCI_VDEVICE(EXAR, PCI_ANY_ID), REPORT_8250_CONFIG(EXAR), },
3743+ { PCI_VDEVICE(COMMTECH, PCI_ANY_ID), REPORT_8250_CONFIG(EXAR), },
35583744
35593745 /* Pericom devices */
3560− { PCI_VDEVICE(PERICOM, PCI_ANY_ID), },
3561− { PCI_VDEVICE(ACCESSIO, PCI_ANY_ID), },
3746+ { PCI_VDEVICE(PERICOM, PCI_ANY_ID), REPORT_8250_CONFIG(PERICOM), },
3747+ { PCI_VDEVICE(ACCESSIO, PCI_ANY_ID), REPORT_8250_CONFIG(PERICOM), },
35623748
35633749 /* End of the black list */
35643750 { }
@@ -3840,8 +4026,12 @@ pciserial_init_one(struct pci_dev *dev, const struct pci_device_id *ent) · 275 unmodified lines
38404026 board = &pci_boards[ent->driver_data];
38414027
38424028 exclude = pci_match_id(blacklist, dev);
3843− if (exclude)
4029+ if (exclude) {
4030+ if (exclude->driver_data)
4031+ pci_warn(dev, "ignoring port, enable %s to handle\n",
4032+ (const char *)exclude->driver_data);
38444033 return -ENODEV;
4034+ }
38454035
38464036 rc = pcim_enable_device(dev);
38474037 pci_save_state(dev);
@@ -4109,13 +4299,6 @@ static const struct pci_device_id serial_pci_tbl[] = { · 261 unmodified lines
41094299 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_ROMULUS,
41104300 0x10b5, 0x106a, 0, 0,
41114301 pbn_plx_romulus },
4112− /*
4113− * EndRun Technologies. PCI express device range.
4114− * EndRun PTP/1588 has 2 Native UARTs.
4115− */
4116− { PCI_VENDOR_ID_ENDRUN, PCI_DEVICE_ID_ENDRUN_1588,
4117− PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4118− pbn_endrun_2_3906250 },
41194302 /*
41204303 * Quatech cards. These actually have configurable clocks but for
41214304 * now we just use the default.
@@ -4225,158 +4408,165 @@ static const struct pci_device_id serial_pci_tbl[] = { · 103 unmodified lines
42254408 */
42264409 { PCI_VENDOR_ID_OXSEMI, 0xc101, /* OXPCIe952 1 Legacy UART */
42274410 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4228− pbn_b0_1_3906250 },
4411+ pbn_b0_1_15625000 },
42294412 { PCI_VENDOR_ID_OXSEMI, 0xc105, /* OXPCIe952 1 Legacy UART */
42304413 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4231− pbn_b0_1_3906250 },
4414+ pbn_b0_1_15625000 },
42324415 { PCI_VENDOR_ID_OXSEMI, 0xc11b, /* OXPCIe952 1 Native UART */
42334416 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4234− pbn_oxsemi_1_3906250 },
4417+ pbn_oxsemi_1_15625000 },
42354418 { PCI_VENDOR_ID_OXSEMI, 0xc11f, /* OXPCIe952 1 Native UART */
42364419 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4237− pbn_oxsemi_1_3906250 },
4420+ pbn_oxsemi_1_15625000 },
42384421 { PCI_VENDOR_ID_OXSEMI, 0xc120, /* OXPCIe952 1 Legacy UART */
42394422 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4240− pbn_b0_1_3906250 },
4423+ pbn_b0_1_15625000 },
42414424 { PCI_VENDOR_ID_OXSEMI, 0xc124, /* OXPCIe952 1 Legacy UART */
42424425 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4243− pbn_b0_1_3906250 },
4426+ pbn_b0_1_15625000 },
42444427 { PCI_VENDOR_ID_OXSEMI, 0xc138, /* OXPCIe952 1 Native UART */
42454428 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4246− pbn_oxsemi_1_3906250 },
4429+ pbn_oxsemi_1_15625000 },
42474430 { PCI_VENDOR_ID_OXSEMI, 0xc13d, /* OXPCIe952 1 Native UART */
42484431 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4249− pbn_oxsemi_1_3906250 },
4432+ pbn_oxsemi_1_15625000 },
42504433 { PCI_VENDOR_ID_OXSEMI, 0xc140, /* OXPCIe952 1 Legacy UART */
42514434 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4252− pbn_b0_1_3906250 },
4435+ pbn_b0_1_15625000 },
42534436 { PCI_VENDOR_ID_OXSEMI, 0xc141, /* OXPCIe952 1 Legacy UART */
42544437 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4255− pbn_b0_1_3906250 },
4438+ pbn_b0_1_15625000 },
42564439 { PCI_VENDOR_ID_OXSEMI, 0xc144, /* OXPCIe952 1 Legacy UART */
42574440 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4258− pbn_b0_1_3906250 },
4441+ pbn_b0_1_15625000 },
42594442 { PCI_VENDOR_ID_OXSEMI, 0xc145, /* OXPCIe952 1 Legacy UART */
42604443 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4261− pbn_b0_1_3906250 },
4444+ pbn_b0_1_15625000 },
42624445 { PCI_VENDOR_ID_OXSEMI, 0xc158, /* OXPCIe952 2 Native UART */
42634446 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4264− pbn_oxsemi_2_3906250 },
4447+ pbn_oxsemi_2_15625000 },
42654448 { PCI_VENDOR_ID_OXSEMI, 0xc15d, /* OXPCIe952 2 Native UART */
42664449 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4267− pbn_oxsemi_2_3906250 },
4450+ pbn_oxsemi_2_15625000 },
42684451 { PCI_VENDOR_ID_OXSEMI, 0xc208, /* OXPCIe954 4 Native UART */
42694452 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4270− pbn_oxsemi_4_3906250 },
4453+ pbn_oxsemi_4_15625000 },
42714454 { PCI_VENDOR_ID_OXSEMI, 0xc20d, /* OXPCIe954 4 Native UART */
42724455 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4273− pbn_oxsemi_4_3906250 },
4456+ pbn_oxsemi_4_15625000 },
42744457 { PCI_VENDOR_ID_OXSEMI, 0xc308, /* OXPCIe958 8 Native UART */
42754458 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4276− pbn_oxsemi_8_3906250 },
4459+ pbn_oxsemi_8_15625000 },
42774460 { PCI_VENDOR_ID_OXSEMI, 0xc30d, /* OXPCIe958 8 Native UART */
42784461 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4279− pbn_oxsemi_8_3906250 },
4462+ pbn_oxsemi_8_15625000 },
42804463 { PCI_VENDOR_ID_OXSEMI, 0xc40b, /* OXPCIe200 1 Native UART */
42814464 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4282− pbn_oxsemi_1_3906250 },
4465+ pbn_oxsemi_1_15625000 },
42834466 { PCI_VENDOR_ID_OXSEMI, 0xc40f, /* OXPCIe200 1 Native UART */
42844467 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4285− pbn_oxsemi_1_3906250 },
4468+ pbn_oxsemi_1_15625000 },
42864469 { PCI_VENDOR_ID_OXSEMI, 0xc41b, /* OXPCIe200 1 Native UART */
42874470 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4288− pbn_oxsemi_1_3906250 },
4471+ pbn_oxsemi_1_15625000 },
42894472 { PCI_VENDOR_ID_OXSEMI, 0xc41f, /* OXPCIe200 1 Native UART */
42904473 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4291− pbn_oxsemi_1_3906250 },
4474+ pbn_oxsemi_1_15625000 },
42924475 { PCI_VENDOR_ID_OXSEMI, 0xc42b, /* OXPCIe200 1 Native UART */
42934476 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4294− pbn_oxsemi_1_3906250 },
4477+ pbn_oxsemi_1_15625000 },
42954478 { PCI_VENDOR_ID_OXSEMI, 0xc42f, /* OXPCIe200 1 Native UART */
42964479 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4297− pbn_oxsemi_1_3906250 },
4480+ pbn_oxsemi_1_15625000 },
42984481 { PCI_VENDOR_ID_OXSEMI, 0xc43b, /* OXPCIe200 1 Native UART */
42994482 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4300− pbn_oxsemi_1_3906250 },
4483+ pbn_oxsemi_1_15625000 },
43014484 { PCI_VENDOR_ID_OXSEMI, 0xc43f, /* OXPCIe200 1 Native UART */
43024485 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4303− pbn_oxsemi_1_3906250 },
4486+ pbn_oxsemi_1_15625000 },
43044487 { PCI_VENDOR_ID_OXSEMI, 0xc44b, /* OXPCIe200 1 Native UART */
43054488 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4306− pbn_oxsemi_1_3906250 },
4489+ pbn_oxsemi_1_15625000 },
43074490 { PCI_VENDOR_ID_OXSEMI, 0xc44f, /* OXPCIe200 1 Native UART */
43084491 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4309− pbn_oxsemi_1_3906250 },
4492+ pbn_oxsemi_1_15625000 },
43104493 { PCI_VENDOR_ID_OXSEMI, 0xc45b, /* OXPCIe200 1 Native UART */
43114494 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4312− pbn_oxsemi_1_3906250 },
4495+ pbn_oxsemi_1_15625000 },
43134496 { PCI_VENDOR_ID_OXSEMI, 0xc45f, /* OXPCIe200 1 Native UART */
43144497 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4315− pbn_oxsemi_1_3906250 },
4498+ pbn_oxsemi_1_15625000 },
43164499 { PCI_VENDOR_ID_OXSEMI, 0xc46b, /* OXPCIe200 1 Native UART */
43174500 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4318− pbn_oxsemi_1_3906250 },
4501+ pbn_oxsemi_1_15625000 },
43194502 { PCI_VENDOR_ID_OXSEMI, 0xc46f, /* OXPCIe200 1 Native UART */
43204503 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4321− pbn_oxsemi_1_3906250 },
4504+ pbn_oxsemi_1_15625000 },
43224505 { PCI_VENDOR_ID_OXSEMI, 0xc47b, /* OXPCIe200 1 Native UART */
43234506 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4324− pbn_oxsemi_1_3906250 },
4507+ pbn_oxsemi_1_15625000 },
43254508 { PCI_VENDOR_ID_OXSEMI, 0xc47f, /* OXPCIe200 1 Native UART */
43264509 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4327− pbn_oxsemi_1_3906250 },
4510+ pbn_oxsemi_1_15625000 },
43284511 { PCI_VENDOR_ID_OXSEMI, 0xc48b, /* OXPCIe200 1 Native UART */
43294512 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4330− pbn_oxsemi_1_3906250 },
4513+ pbn_oxsemi_1_15625000 },
43314514 { PCI_VENDOR_ID_OXSEMI, 0xc48f, /* OXPCIe200 1 Native UART */
43324515 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4333− pbn_oxsemi_1_3906250 },
4516+ pbn_oxsemi_1_15625000 },
43344517 { PCI_VENDOR_ID_OXSEMI, 0xc49b, /* OXPCIe200 1 Native UART */
43354518 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4336− pbn_oxsemi_1_3906250 },
4519+ pbn_oxsemi_1_15625000 },
43374520 { PCI_VENDOR_ID_OXSEMI, 0xc49f, /* OXPCIe200 1 Native UART */
43384521 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4339− pbn_oxsemi_1_3906250 },
4522+ pbn_oxsemi_1_15625000 },
43404523 { PCI_VENDOR_ID_OXSEMI, 0xc4ab, /* OXPCIe200 1 Native UART */
43414524 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4342− pbn_oxsemi_1_3906250 },
4525+ pbn_oxsemi_1_15625000 },
43434526 { PCI_VENDOR_ID_OXSEMI, 0xc4af, /* OXPCIe200 1 Native UART */
43444527 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4345− pbn_oxsemi_1_3906250 },
4528+ pbn_oxsemi_1_15625000 },
43464529 { PCI_VENDOR_ID_OXSEMI, 0xc4bb, /* OXPCIe200 1 Native UART */
43474530 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4348− pbn_oxsemi_1_3906250 },
4531+ pbn_oxsemi_1_15625000 },
43494532 { PCI_VENDOR_ID_OXSEMI, 0xc4bf, /* OXPCIe200 1 Native UART */
43504533 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4351− pbn_oxsemi_1_3906250 },
4534+ pbn_oxsemi_1_15625000 },
43524535 { PCI_VENDOR_ID_OXSEMI, 0xc4cb, /* OXPCIe200 1 Native UART */
43534536 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4354− pbn_oxsemi_1_3906250 },
4537+ pbn_oxsemi_1_15625000 },
43554538 { PCI_VENDOR_ID_OXSEMI, 0xc4cf, /* OXPCIe200 1 Native UART */
43564539 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4357− pbn_oxsemi_1_3906250 },
4540+ pbn_oxsemi_1_15625000 },
43584541 /*
43594542 * Mainpine Inc. IQ Express "Rev3" utilizing OxSemi Tornado
43604543 */
43614544 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 1 Port V.34 Super-G3 Fax */
43624545 PCI_VENDOR_ID_MAINPINE, 0x4001, 0, 0,
4363− pbn_oxsemi_1_3906250 },
4546+ pbn_oxsemi_1_15625000 },
43644547 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 2 Port V.34 Super-G3 Fax */
43654548 PCI_VENDOR_ID_MAINPINE, 0x4002, 0, 0,
4366− pbn_oxsemi_2_3906250 },
4549+ pbn_oxsemi_2_15625000 },
43674550 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 4 Port V.34 Super-G3 Fax */
43684551 PCI_VENDOR_ID_MAINPINE, 0x4004, 0, 0,
4369− pbn_oxsemi_4_3906250 },
4552+ pbn_oxsemi_4_15625000 },
43704553 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 8 Port V.34 Super-G3 Fax */
43714554 PCI_VENDOR_ID_MAINPINE, 0x4008, 0, 0,
4372− pbn_oxsemi_8_3906250 },
4555+ pbn_oxsemi_8_15625000 },
43734556
43744557 /*
43754558 * Digi/IBM PCIe 2-port Async EIA-232 Adapter utilizing OxSemi Tornado
43764559 */
43774560 { PCI_VENDOR_ID_DIGI, PCIE_DEVICE_ID_NEO_2_OX_IBM,
43784561 PCI_SUBVENDOR_ID_IBM, PCI_ANY_ID, 0, 0,
4379− pbn_oxsemi_2_3906250 },
4562+ pbn_oxsemi_2_15625000 },
4563+ /*
4564+ * EndRun Technologies. PCI express device range.
4565+ * EndRun PTP/1588 has 2 Native UARTs utilizing OxSemi 952.
4566+ */
4567+ { PCI_VENDOR_ID_ENDRUN, PCI_DEVICE_ID_ENDRUN_1588,
4568+ PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4569+ pbn_oxsemi_2_15625000 },
43804570
43814571 /*
43824572 * SBS Technologies, Inc. P-Octal and PMC-OCTPRO cards,
drivers/tty/serial/8250/8250_port.c+98−42
@@ -263,7 +263,7 @@ static const struct serial8250_config uart_config[] = { · 262 unmodified lines
263263 .tx_loadsz = 63,
264264 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10 |
265265 UART_FCR7_64BYTE,
266− .flags = UART_CAP_FIFO,
266+ .flags = UART_CAP_FIFO | UART_CAP_NOTEMT,
267267 },
268268 [PORT_RT2880] = {
269269 .name = "Palmchip BK-3103",
@@ -537,27 +537,6 @@ serial_port_out_sync(struct uart_port *p, int offset, int value) · 267 unmodified lines
537537 }
538538 }
539539
540−/*
541− * For the 16C950
542− */
543−static void serial_icr_write(struct uart_8250_port *up, int offset, int value)
544−{
545− serial_out(up, UART_SCR, offset);
546− serial_out(up, UART_ICR, value);
547−}
548−
549−static unsigned int serial_icr_read(struct uart_8250_port *up, int offset)
550−{
551− unsigned int value;
552−
553− serial_icr_write(up, UART_ACR, up->acr | UART_ACR_ICRRD);
554− serial_out(up, UART_SCR, offset);
555− value = serial_in(up, UART_ICR);
556− serial_icr_write(up, UART_ACR, up->acr);
557−
558− return value;
559−}
560−
561540 /*
562541 * FIFO support.
563542 */
@@ -1504,18 +1483,19 @@ static void start_hrtimer_ms(struct hrtimer *hrt, unsigned long msec) · 940 unmodified lines
15041483 hrtimer_start(hrt, ms_to_ktime(msec), HRTIMER_MODE_REL);
15051484 }
15061485
1507−static void __stop_tx_rs485(struct uart_8250_port *p)
1486+static void __stop_tx_rs485(struct uart_8250_port *p, u64 stop_delay)
15081487 {
15091488 struct uart_8250_em485 *em485 = p->em485;
15101489
1490+ stop_delay += (u64)p->port.rs485.delay_rts_after_send * NSEC_PER_MSEC;
1491+
15111492 /*
15121493 * rs485_stop_tx() is going to set RTS according to config
15131494 * AND flush RX FIFO if required.
15141495 */
1515− if (p->port.rs485.delay_rts_after_send > 0) {
1496+ if (stop_delay > 0) {
15161497 em485->active_timer = &em485->stop_tx_timer;
1517− start_hrtimer_ms(&em485->stop_tx_timer,
1518− p->port.rs485.delay_rts_after_send);
1498+ hrtimer_start(&em485->stop_tx_timer, ns_to_ktime(stop_delay), HRTIMER_MODE_REL);
15191499 } else {
15201500 p->rs485_stop_tx(p);
15211501 em485->active_timer = NULL;
@@ -1535,16 +1515,32 @@ static inline void __stop_tx(struct uart_8250_port *p) · 13 unmodified lines
15351515
15361516 if (em485) {
15371517 unsigned char lsr = serial_in(p, UART_LSR);
1518+ u64 stop_delay = 0;
1519+
1520+ if (!(lsr & UART_LSR_THRE))
1521+ return;
15381522 /*
15391523 * To provide required timeing and allow FIFO transfer,
15401524 * __stop_tx_rs485() must be called only when both FIFO and
1541− * shift register are empty. It is for device driver to enable
1542− * interrupt on TEMT.
1525+ * shift register are empty. The device driver should either
1526+ * enable interrupt on TEMT or set UART_CAP_NOTEMT that will
1527+ * enlarge stop_tx_timer by the tx time of one frame to cover
1528+ * for emptying of the shift register.
15431529 */
1544− if ((lsr & BOTH_EMPTY) != BOTH_EMPTY)
1545− return;
1530+ if (!(lsr & UART_LSR_TEMT)) {
1531+ if (!(p->capabilities & UART_CAP_NOTEMT))
1532+ return;
1533+ /*
1534+ * RTS might get deasserted too early with the normal
1535+ * frame timing formula. It seems to suggest THRE might
1536+ * get asserted already during tx of the stop bit
1537+ * rather than after it is fully sent.
1538+ * Roughly estimate 1 extra bit here with / 7.
1539+ */
1540+ stop_delay = p->port.frame_time + DIV_ROUND_UP(p->port.frame_time, 7);
1541+ }
15461542
1547− __stop_tx_rs485(p);
1543+ __stop_tx_rs485(p, stop_delay);
15481544 }
15491545 __do_stop_tx(p);
15501546 }
@@ -1948,9 +1944,12 @@ int serial8250_handle_irq(struct uart_port *port, unsigned int iir) · 397 unmodified lines
19481944 status = serial8250_rx_chars(up, status);
19491945 }
19501946 serial8250_modem_status(up);
1951− if ((!up->dma || up->dma->tx_err) && (status & UART_LSR_THRE) &&
1952− (up->ier & UART_IER_THRI))
1953− serial8250_tx_chars(up);
1947+ if ((status & UART_LSR_THRE) && (up->ier & UART_IER_THRI)) {
1948+ if (!up->dma || up->dma->tx_err)
1949+ serial8250_tx_chars(up);
1950+ else
1951+ __stop_tx(up);
1952+ }
19541953
19551954 uart_unlock_and_check_sysrq_irqrestore(port, flags);
19561955
@@ -2077,10 +2076,7 @@ static void serial8250_break_ctl(struct uart_port *port, int break_state) · 120 unmodified lines
20772076 serial8250_rpm_put(up);
20782077 }
20792078
2080−/*
2081− * Wait for transmitter & holding register to empty
2082− */
2083−static void wait_for_xmitr(struct uart_8250_port *up, int bits)
2079+static void wait_for_lsr(struct uart_8250_port *up, int bits)
20842080 {
20852081 unsigned int status, tmout = 10000;
20862082
@@ -2097,6 +2093,16 @@ static void wait_for_xmitr(struct uart_8250_port *up, int bits) · 10 unmodified lines
20972093 udelay(1);
20982094 touch_nmi_watchdog();
20992095 }
2096+}
2097+
2098+/*
2099+ * Wait for transmitter & holding register to empty
2100+ */
2101+static void wait_for_xmitr(struct uart_8250_port *up, int bits)
2102+{
2103+ unsigned int tmout;
2104+
2105+ wait_for_lsr(up, bits);
21002106
21012107 /* Wait up to 1s for flow control if necessary */
21022108 if (up->port.flags & UPF_CONS_FLOW) {
@@ -2614,10 +2620,8 @@ static unsigned char serial8250_compute_lcr(struct uart_8250_port *up, · 511 unmodified lines
26142620 }
26152621 if (!(c_cflag & PARODD))
26162622 cval |= UART_LCR_EPAR;
2617−#ifdef CMSPAR
26182623 if (c_cflag & CMSPAR)
26192624 cval |= UART_LCR_SPAR;
2620−#endif
26212625
26222626 return cval;
26232627 }
@@ -3332,6 +3336,35 @@ static void serial8250_console_restore(struct uart_8250_port *up) · 708 unmodified lines
33323336 serial8250_out_MCR(up, up->mcr | UART_MCR_DTR | UART_MCR_RTS);
33333337 }
33343338
3339+/*
3340+ * Print a string to the serial port using the device FIFO
3341+ *
3342+ * It sends fifosize bytes and then waits for the fifo
3343+ * to get empty.
3344+ */
3345+static void serial8250_console_fifo_write(struct uart_8250_port *up,
3346+ const char *s, unsigned int count)
3347+{
3348+ int i;
3349+ const char *end = s + count;
3350+ unsigned int fifosize = up->tx_loadsz;
3351+ bool cr_sent = false;
3352+
3353+ while (s != end) {
3354+ wait_for_lsr(up, UART_LSR_THRE);
3355+
3356+ for (i = 0; i < fifosize && s != end; ++i) {
3357+ if (*s == '\n' && !cr_sent) {
3358+ serial_out(up, UART_TX, '\r');
3359+ cr_sent = true;
3360+ } else {
3361+ serial_out(up, UART_TX, *s++);
3362+ cr_sent = false;
3363+ }
3364+ }
3365+ }
3366+}
3367+
33353368 /*
33363369 * Print a string to the serial port trying not to disturb
33373370 * any possible real use of the port...
@@ -3347,7 +3380,7 @@ void serial8250_console_write(struct uart_8250_port *up, const char *s, · 9 unmodified lines
33473380 struct uart_8250_em485 *em485 = up->em485;
33483381 struct uart_port *port = &up->port;
33493382 unsigned long flags;
3350− unsigned int ier;
3383+ unsigned int ier, use_fifo;
33513384 int locked = 1;
33523385
33533386 touch_nmi_watchdog();
@@ -3379,7 +3412,30 @@ void serial8250_console_write(struct uart_8250_port *up, const char *s, · 25 unmodified lines
33793412 mdelay(port->rs485.delay_rts_before_send);
33803413 }
33813414
3382− uart_console_write(port, s, count, serial8250_console_putchar);
3415+ use_fifo = (up->capabilities & UART_CAP_FIFO) &&
3416+ /*
3417+ * BCM283x requires to check the fifo
3418+ * after each byte.
3419+ */
3420+ !(up->capabilities & UART_CAP_MINI) &&
3421+ /*
3422+ * tx_loadsz contains the transmit fifo size
3423+ */
3424+ up->tx_loadsz > 1 &&
3425+ (up->fcr & UART_FCR_ENABLE_FIFO) &&
3426+ port->state &&
3427+ test_bit(TTY_PORT_INITIALIZED, &port->state->port.iflags) &&
3428+ /*
3429+ * After we put a data in the fifo, the controller will send
3430+ * it regardless of the CTS state. Therefore, only use fifo
3431+ * if we don't use control flow.
3432+ */
3433+ !(up->port.flags & UPF_CONS_FLOW);
3434+
3435+ if (likely(use_fifo))
3436+ serial8250_console_fifo_write(up, s, count);
3437+ else
3438+ uart_console_write(port, s, count, serial8250_console_putchar);
33833439
33843440 /*
33853441 * Finally, wait for transmitter to become empty
drivers/tty/serial/8250/8250_pxa.c+0−1
@@ -22,7 +22,6 @@ · 21 unmodified lines
2222 #include <linux/platform_device.h>
2323 #include <linux/slab.h>
2424 #include <linux/clk.h>
25−#include <linux/pm_runtime.h>
2625
2726 #include "8250.h"
2827
drivers/tty/serial/8250/Kconfig+1−1
@@ -380,7 +380,7 @@ config SERIAL_8250_DW · 379 unmodified lines
380380 config SERIAL_8250_EM
381381 tristate "Support for Emma Mobile integrated serial port"
382382 depends on SERIAL_8250 && HAVE_CLK
383− depends on (ARM && ARCH_RENESAS) || COMPILE_TEST
383+ depends on ARCH_RENESAS || COMPILE_TEST
384384 help
385385 Selecting this option will add support for the integrated serial
386386 port hardware found on the Emma Mobile line of processors.
drivers/tty/serial/Kconfig+5−4
@@ -782,7 +782,7 @@ config SERIAL_PMACZILOG_CONSOLE · 781 unmodified lines
782782
783783 config SERIAL_CPM
784784 tristate "CPM SCC/SMC serial port support"
785− depends on CPM2 || CPM1
785+ depends on CPM2 || CPM1 || (PPC32 && COMPILE_TEST)
786786 select SERIAL_CORE
787787 help
788788 This driver supports the SCC and SMC serial ports on Motorola
@@ -806,7 +806,7 @@ config SERIAL_CPM_CONSOLE · 17 unmodified lines
806806
807807 config SERIAL_PIC32
808808 tristate "Microchip PIC32 serial support"
809− depends on MACH_PIC32
809+ depends on MACH_PIC32 || (MIPS && COMPILE_TEST)
810810 select SERIAL_CORE
811811 help
812812 If you have a PIC32, this driver supports the serial ports.
@@ -817,7 +817,7 @@ config SERIAL_PIC32 · 4 unmodified lines
817817
818818 config SERIAL_PIC32_CONSOLE
819819 bool "PIC32 serial console support"
820− depends on SERIAL_PIC32
820+ depends on SERIAL_PIC32=y
821821 select SERIAL_CORE_CONSOLE
822822 help
823823 If you have a PIC32, this driver supports the putting a console on one
@@ -1246,7 +1246,7 @@ config SERIAL_XILINX_PS_UART_CONSOLE · 422 unmodified lines
12461246
12471247 config SERIAL_AR933X
12481248 tristate "AR933X serial port support"
1249− depends on HAVE_CLK && ATH79
1249+ depends on (HAVE_CLK && ATH79) || (MIPS && COMPILE_TEST)
12501250 select SERIAL_CORE
12511251 select SERIAL_MCTRL_GPIO if GPIOLIB
12521252 help
@@ -1442,6 +1442,7 @@ config SERIAL_STM32_CONSOLE · 189 unmodified lines
14421442 bool "Support for console on STM32"
14431443 depends on SERIAL_STM32=y
14441444 select SERIAL_CORE_CONSOLE
1445+ select SERIAL_EARLYCON
14451446
14461447 config SERIAL_MVEBU_UART
14471448 bool "Marvell EBU serial port support"
drivers/tty/serial/altera_jtaguart.c+2−4
@@ -168,10 +168,8 @@ static void altera_jtaguart_tx_chars(struct altera_jtaguart *pp) · 167 unmodified lines
168168 }
169169 }
170170
171− if (pending == 0) {
172− pp->imr &= ~ALTERA_JTAGUART_CONTROL_WE_MSK;
173− writel(pp->imr, port->membase + ALTERA_JTAGUART_CONTROL_REG);
174− }
171+ if (pending == 0)
172+ altera_jtaguart_stop_tx(port);
175173 }
176174
177175 static irqreturn_t altera_jtaguart_interrupt(int irq, void *data)
drivers/tty/serial/amba-pl011.c+31−17
@@ -42,8 +42,6 @@ · 41 unmodified lines
4242 #include <linux/io.h>
4343 #include <linux/acpi.h>
4444
45−#include "amba-pl011.h"
46−
4745 #define UART_NR 14
4846
4947 #define SERIAL_AMBA_MAJOR 204
@@ -55,6 +53,36 @@ · 5 unmodified lines
5553 #define UART_DR_ERROR (UART011_DR_OE|UART011_DR_BE|UART011_DR_PE|UART011_DR_FE)
5654 #define UART_DUMMY_DR_RX (1 << 16)
5755
56+enum {
57+ REG_DR,
58+ REG_ST_DMAWM,
59+ REG_ST_TIMEOUT,
60+ REG_FR,
61+ REG_LCRH_RX,
62+ REG_LCRH_TX,
63+ REG_IBRD,
64+ REG_FBRD,
65+ REG_CR,
66+ REG_IFLS,
67+ REG_IMSC,
68+ REG_RIS,
69+ REG_MIS,
70+ REG_ICR,
71+ REG_DMACR,
72+ REG_ST_XFCR,
73+ REG_ST_XON1,
74+ REG_ST_XON2,
75+ REG_ST_XOFF1,
76+ REG_ST_XOFF2,
77+ REG_ST_ITCR,
78+ REG_ST_ITIP,
79+ REG_ST_ABCR,
80+ REG_ST_ABIMSC,
81+
82+ /* The size of the array - must be last */
83+ REG_ARRAY_SIZE,
84+};
85+
5886 static u16 pl011_std_offsets[REG_ARRAY_SIZE] = {
5987 [REG_DR] = UART01x_DR,
6088 [REG_FR] = UART01x_FR,
@@ -2175,25 +2203,11 @@ static int pl011_rs485_config(struct uart_port *port, · 2114 unmodified lines
21752203 struct uart_amba_port *uap =
21762204 container_of(port, struct uart_amba_port, port);
21772205
2178− /* pick sane settings if the user hasn't */
2179− if (!(rs485->flags & SER_RS485_RTS_ON_SEND) ==
2180− !(rs485->flags & SER_RS485_RTS_AFTER_SEND)) {
2181− rs485->flags |= SER_RS485_RTS_ON_SEND;
2182− rs485->flags &= ~SER_RS485_RTS_AFTER_SEND;
2183− }
2184− /* clamp the delays to [0, 100ms] */
2185− rs485->delay_rts_before_send = min(rs485->delay_rts_before_send, 100U);
2186− rs485->delay_rts_after_send = min(rs485->delay_rts_after_send, 100U);
2187− memset(rs485->padding, 0, sizeof(rs485->padding));
2188−
21892206 if (port->rs485.flags & SER_RS485_ENABLED)
21902207 pl011_rs485_tx_stop(uap);
21912208
2192− /* Set new configuration */
2193− port->rs485 = *rs485;
2194−
21952209 /* Make sure auto RTS is disabled */
2196− if (port->rs485.flags & SER_RS485_ENABLED) {
2210+ if (rs485->flags & SER_RS485_ENABLED) {
21972211 u32 cr = pl011_read(uap, REG_CR);
21982212
21992213 cr &= ~UART011_CR_RTSEN;
drivers/tty/serial/amba-pl011.h+0−35
@@ -1,35 +0,0 @@
1−/* SPDX-License-Identifier: GPL-2.0 */
2−#ifndef AMBA_PL011_H
3−#define AMBA_PL011_H
4−
5−enum {
6− REG_DR,
7− REG_ST_DMAWM,
8− REG_ST_TIMEOUT,
9− REG_FR,
10− REG_LCRH_RX,
11− REG_LCRH_TX,
12− REG_IBRD,
13− REG_FBRD,
14− REG_CR,
15− REG_IFLS,
16− REG_IMSC,
17− REG_RIS,
18− REG_MIS,
19− REG_ICR,
20− REG_DMACR,
21− REG_ST_XFCR,
22− REG_ST_XON1,
23− REG_ST_XON2,
24− REG_ST_XOFF1,
25− REG_ST_XOFF2,
26− REG_ST_ITCR,
27− REG_ST_ITIP,
28− REG_ST_ABCR,
29− REG_ST_ABIMSC,
30−
31− /* The size of the array - must be last */
32− REG_ARRAY_SIZE,
33−};
34−
35−#endif
drivers/tty/serial/atmel_serial.c+1−3
@@ -299,11 +299,9 @@ static int atmel_config_rs485(struct uart_port *port, · 298 unmodified lines
299299 /* Resetting serial mode to RS232 (0x0) */
300300 mode &= ~ATMEL_US_USMODE;
301301
302− port->rs485 = *rs485conf;
303−
304302 if (rs485conf->flags & SER_RS485_ENABLED) {
305303 dev_dbg(port->dev, "Setting UART to RS485\n");
306− if (port->rs485.flags & SER_RS485_RX_DURING_TX)
304+ if (rs485conf->flags & SER_RS485_RX_DURING_TX)
307305 atmel_port->tx_done_mask = ATMEL_US_TXRDY;
308306 else
309307 atmel_port->tx_done_mask = ATMEL_US_TXEMPTY;
drivers/tty/serial/cpm_uart/cpm_uart.h+2−0
@@ -19,6 +19,8 @@ struct gpio_desc; · 18 unmodified lines
1919 #include "cpm_uart_cpm2.h"
2020 #elif defined(CONFIG_CPM1)
2121 #include "cpm_uart_cpm1.h"
22+#elif defined(CONFIG_COMPILE_TEST)
23+#include "cpm_uart_cpm2.h"
2224 #endif
2325
2426 #define SERIAL_CPM_MAJOR 204
drivers/tty/serial/cpm_uart/cpm_uart_core.c+1−1
@@ -1247,7 +1247,7 @@ static int cpm_uart_init_port(struct device_node *np, · 1246 unmodified lines
12471247 }
12481248
12491249 #ifdef CONFIG_PPC_EARLY_DEBUG_CPM
1250−#ifdef CONFIG_CONSOLE_POLL
1250+#if defined(CONFIG_CONSOLE_POLL) && defined(CONFIG_SERIAL_CPM_CONSOLE)
12511251 if (!udbg_port)
12521252 #endif
12531253 udbg_putc = NULL;
drivers/tty/serial/cpm_uart/cpm_uart_cpm2.c+0−1
@@ -25,7 +25,6 @@ · 24 unmodified lines
2525 #include <asm/io.h>
2626 #include <asm/irq.h>
2727 #include <asm/fs_pd.h>
28−#include <asm/prom.h>
2928
3029 #include <linux/serial_core.h>
3130 #include <linux/kernel.h>
drivers/tty/serial/digicolor-usart.c+2−0
@@ -309,6 +309,8 @@ static void digicolor_uart_set_termios(struct uart_port *port, · 308 unmodified lines
309309 case CS8:
310310 default:
311311 config |= UA_CONFIG_CHAR_LEN;
312+ termios->c_cflag &= ~CSIZE;
313+ termios->c_cflag |= CS8;
312314 break;
313315 }
314316
drivers/tty/serial/fsl_lpuart.c+8−58
@@ -239,8 +239,6 @@ · 238 unmodified lines
239239 /* IMX lpuart has four extra unused regs located at the beginning */
240240 #define IMX_REG_OFF 0x10
241241
242−static DEFINE_IDA(fsl_lpuart_ida);
243−
244242 enum lpuart_type {
245243 VF610_LPUART,
246244 LS1021A_LPUART,
@@ -276,7 +274,6 @@ struct lpuart_port { · 29 unmodified lines
276274 int rx_dma_rng_buf_len;
277275 unsigned int dma_tx_nents;
278276 wait_queue_head_t dma_wait;
279− bool id_allocated;
280277 };
281278
282279 struct lpuart_soc_data {
@@ -1118,7 +1115,7 @@ static void lpuart_copy_rx_to_tty(struct lpuart_port *sport) · 835 unmodified lines
11181115 struct dma_chan *chan = sport->dma_rx_chan;
11191116 struct circ_buf *ring = &sport->rx_ring;
11201117 unsigned long flags;
1121− int count = 0, copied;
1118+ int count, copied;
11221119
11231120 if (lpuart_is_32(sport)) {
11241121 unsigned long sr = lpuart32_read(&sport->port, UARTSTAT);
@@ -1377,19 +1374,6 @@ static int lpuart_config_rs485(struct uart_port *port, · 252 unmodified lines
13771374 /* Enable auto RS-485 RTS mode */
13781375 modem |= UARTMODEM_TXRTSE;
13791376
1380− /*
1381− * RTS needs to be logic HIGH either during transfer _or_ after
1382− * transfer, other variants are not supported by the hardware.
1383− */
1384−
1385− if (!(rs485->flags & (SER_RS485_RTS_ON_SEND |
1386− SER_RS485_RTS_AFTER_SEND)))
1387− rs485->flags |= SER_RS485_RTS_ON_SEND;
1388−
1389− if (rs485->flags & SER_RS485_RTS_ON_SEND &&
1390− rs485->flags & SER_RS485_RTS_AFTER_SEND)
1391− rs485->flags &= ~SER_RS485_RTS_AFTER_SEND;
1392−
13931377 /*
13941378 * The hardware defaults to RTS logic HIGH while transfer.
13951379 * Switch polarity in case RTS shall be logic HIGH
@@ -1402,9 +1386,6 @@ static int lpuart_config_rs485(struct uart_port *port, · 6 unmodified lines
14021386 modem |= UARTMODEM_TXRTSPOL;
14031387 }
14041388
1405− /* Store the new configuration */
1406− sport->port.rs485 = *rs485;
1407−
14081389 writeb(modem, sport->port.membase + UARTMODEM);
14091390 return 0;
14101391 }
@@ -1428,19 +1409,6 @@ static int lpuart32_config_rs485(struct uart_port *port, · 17 unmodified lines
14281409 /* Enable auto RS-485 RTS mode */
14291410 modem |= UARTMODEM_TXRTSE;
14301411
1431− /*
1432− * RTS needs to be logic HIGH either during transfer _or_ after
1433− * transfer, other variants are not supported by the hardware.
1434− */
1435−
1436− if (!(rs485->flags & (SER_RS485_RTS_ON_SEND |
1437− SER_RS485_RTS_AFTER_SEND)))
1438− rs485->flags |= SER_RS485_RTS_ON_SEND;
1439−
1440− if (rs485->flags & SER_RS485_RTS_ON_SEND &&
1441− rs485->flags & SER_RS485_RTS_AFTER_SEND)
1442− rs485->flags &= ~SER_RS485_RTS_AFTER_SEND;
1443−
14441412 /*
14451413 * The hardware defaults to RTS logic HIGH while transfer.
14461414 * Switch polarity in case RTS shall be logic HIGH
@@ -1453,9 +1421,6 @@ static int lpuart32_config_rs485(struct uart_port *port, · 6 unmodified lines
14531421 modem |= UARTMODEM_TXRTSPOL;
14541422 }
14551423
1456− /* Store the new configuration */
1457− sport->port.rs485 = *rs485;
1458−
14591424 lpuart32_write(&sport->port, modem, UARTMODIR);
14601425 return 0;
14611426 }
@@ -2145,12 +2110,10 @@ lpuart32_set_termios(struct uart_port *port, struct ktermios *termios, · 683 unmodified lines
21452110 if (sport->port.rs485.flags & SER_RS485_ENABLED)
21462111 termios->c_cflag &= ~CRTSCTS;
21472112
2148− if (termios->c_cflag & CRTSCTS) {
2149− modem |= (UARTMODIR_RXRTSE | UARTMODIR_TXCTSE);
2150− } else {
2151− termios->c_cflag &= ~CRTSCTS;
2113+ if (termios->c_cflag & CRTSCTS)
2114+ modem |= UARTMODIR_RXRTSE | UARTMODIR_TXCTSE;
2115+ else
21522116 modem &= ~(UARTMODIR_RXRTSE | UARTMODIR_TXCTSE);
2153− }
21542117
21552118 if (termios->c_cflag & CSTOPB)
21562119 bd |= UARTBAUD_SBNS;
@@ -2717,23 +2680,18 @@ static int lpuart_probe(struct platform_device *pdev) · 560 unmodified lines
27172680
27182681 ret = of_alias_get_id(np, "serial");
27192682 if (ret < 0) {
2720− ret = ida_simple_get(&fsl_lpuart_ida, 0, UART_NR, GFP_KERNEL);
2721− if (ret < 0) {
2722− dev_err(&pdev->dev, "port line is full, add device failed\n");
2723− return ret;
2724− }
2725− sport->id_allocated = true;
2683+ dev_err(&pdev->dev, "failed to get alias id, errno %d\n", ret);
2684+ return ret;
27262685 }
27272686 if (ret >= ARRAY_SIZE(lpuart_ports)) {
27282687 dev_err(&pdev->dev, "serial%d out of range\n", ret);
2729− ret = -EINVAL;
2730− goto failed_out_of_range;
2688+ return -EINVAL;
27312689 }
27322690 sport->port.line = ret;
27332691
27342692 ret = lpuart_enable_clks(sport);
27352693 if (ret)
2736− goto failed_clock_enable;
2694+ return ret;
27372695 sport->port.uartclk = lpuart_get_baud_clk_rate(sport);
27382696
27392697 lpuart_ports[sport->port.line] = sport;
@@ -2781,10 +2739,6 @@ failed_reset: · 41 unmodified lines
27812739 uart_remove_one_port(&lpuart_reg, &sport->port);
27822740 failed_attach_port:
27832741 lpuart_disable_clks(sport);
2784−failed_clock_enable:
2785−failed_out_of_range:
2786− if (sport->id_allocated)
2787− ida_simple_remove(&fsl_lpuart_ida, sport->port.line);
27882742 return ret;
27892743 }
27902744
@@ -2794,9 +2748,6 @@ static int lpuart_remove(struct platform_device *pdev) · 3 unmodified lines
27942748
27952749 uart_remove_one_port(&lpuart_reg, &sport->port);
27962750
2797− if (sport->id_allocated)
2798− ida_simple_remove(&fsl_lpuart_ida, sport->port.line);
2799−
28002751 lpuart_disable_clks(sport);
28012752
28022753 if (sport->dma_tx_chan)
@@ -2926,7 +2877,6 @@ static int __init lpuart_serial_init(void) · 123 unmodified lines
29262877
29272878 static void __exit lpuart_serial_exit(void)
29282879 {
2929− ida_destroy(&fsl_lpuart_ida);
29302880 platform_driver_unregister(&lpuart_driver);
29312881 uart_unregister_driver(&lpuart_reg);
29322882 }
drivers/tty/serial/icom.c+386−152
@@ -19,6 +19,7 @@ · 18 unmodified lines
1919 #include <linux/fs.h>
2020 #include <linux/tty_flip.h>
2121 #include <linux/serial.h>
22+#include <linux/serial_core.h>
2223 #include <linux/serial_reg.h>
2324 #include <linux/major.h>
2425 #include <linux/string.h>
@@ -41,15 +42,273 @@ · 16 unmodified lines
4142 #include <asm/irq.h>
4243 #include <linux/uaccess.h>
4344
44−#include "icom.h"
45−
4645 /*#define ICOM_TRACE enable port trace capabilities */
4746
4847 #define ICOM_DRIVER_NAME "icom"
49−#define ICOM_VERSION_STR "1.3.1"
5048 #define NR_PORTS 128
51−#define ICOM_PORT ((struct icom_port *)port)
52−#define to_icom_adapter(d) container_of(d, struct icom_adapter, kref)
49+
50+static const unsigned int icom_acfg_baud[] = {
51+ 300,
52+ 600,
53+ 900,
54+ 1200,
55+ 1800,
56+ 2400,
57+ 3600,
58+ 4800,
59+ 7200,
60+ 9600,
61+ 14400,
62+ 19200,
63+ 28800,
64+ 38400,
65+ 57600,
66+ 76800,
67+ 115200,
68+ 153600,
69+ 230400,
70+ 307200,
71+ 460800,
72+};
73+#define BAUD_TABLE_LIMIT (ARRAY_SIZE(icom_acfg_baud) - 1)
74+
75+struct icom_regs {
76+ u32 control; /* Adapter Control Register */
77+ u32 interrupt; /* Adapter Interrupt Register */
78+ u32 int_mask; /* Adapter Interrupt Mask Reg */
79+ u32 int_pri; /* Adapter Interrupt Priority r */
80+ u32 int_reg_b; /* Adapter non-masked Interrupt */
81+ u32 resvd01;
82+ u32 resvd02;
83+ u32 resvd03;
84+ u32 control_2; /* Adapter Control Register 2 */
85+ u32 interrupt_2; /* Adapter Interrupt Register 2 */
86+ u32 int_mask_2; /* Adapter Interrupt Mask 2 */
87+ u32 int_pri_2; /* Adapter Interrupt Prior 2 */
88+ u32 int_reg_2b; /* Adapter non-masked 2 */
89+};
90+
91+struct func_dram {
92+ u32 reserved[108]; /* 0-1B0 reserved by personality code */
93+ u32 RcvStatusAddr; /* 1B0-1B3 Status Address for Next rcv */
94+ u8 RcvStnAddr; /* 1B4 Receive Station Addr */
95+ u8 IdleState; /* 1B5 Idle State */
96+ u8 IdleMonitor; /* 1B6 Idle Monitor */
97+ u8 FlagFillIdleTimer; /* 1B7 Flag Fill Idle Timer */
98+ u32 XmitStatusAddr; /* 1B8-1BB Transmit Status Address */
99+ u8 StartXmitCmd; /* 1BC Start Xmit Command */
100+ u8 HDLCConfigReg; /* 1BD Reserved */
101+ u8 CauseCode; /* 1BE Cause code for fatal error */
102+ u8 xchar; /* 1BF High priority send */
103+ u32 reserved3; /* 1C0-1C3 Reserved */
104+ u8 PrevCmdReg; /* 1C4 Reserved */
105+ u8 CmdReg; /* 1C5 Command Register */
106+ u8 async_config2; /* 1C6 Async Config Byte 2 */
107+ u8 async_config3; /* 1C7 Async Config Byte 3 */
108+ u8 dce_resvd[20]; /* 1C8-1DB DCE Rsvd */
109+ u8 dce_resvd21; /* 1DC DCE Rsvd (21st byte */
110+ u8 misc_flags; /* 1DD misc flags */
111+#define V2_HARDWARE 0x40
112+#define ICOM_HDW_ACTIVE 0x01
113+ u8 call_length; /* 1DE Phone #/CFI buff ln */
114+ u8 call_length2; /* 1DF Upper byte (unused) */
115+ u32 call_addr; /* 1E0-1E3 Phn #/CFI buff addr */
116+ u16 timer_value; /* 1E4-1E5 general timer value */
117+ u8 timer_command; /* 1E6 general timer cmd */
118+ u8 dce_command; /* 1E7 dce command reg */
119+ u8 dce_cmd_status; /* 1E8 dce command stat */
120+ u8 x21_r1_ioff; /* 1E9 dce ready counter */
121+ u8 x21_r0_ioff; /* 1EA dce not ready ctr */
122+ u8 x21_ralt_ioff; /* 1EB dce CNR counter */
123+ u8 x21_r1_ion; /* 1EC dce ready I on ctr */
124+ u8 rsvd_ier; /* 1ED Rsvd for IER (if ne */
125+ u8 ier; /* 1EE Interrupt Enable */
126+ u8 isr; /* 1EF Input Signal Reg */
127+ u8 osr; /* 1F0 Output Signal Reg */
128+ u8 reset; /* 1F1 Reset/Reload Reg */
129+ u8 disable; /* 1F2 Disable Reg */
130+ u8 sync; /* 1F3 Sync Reg */
131+ u8 error_stat; /* 1F4 Error Status */
132+ u8 cable_id; /* 1F5 Cable ID */
133+ u8 cs_length; /* 1F6 CS Load Length */
134+ u8 mac_length; /* 1F7 Mac Load Length */
135+ u32 cs_load_addr; /* 1F8-1FB Call Load PCI Addr */
136+ u32 mac_load_addr; /* 1FC-1FF Mac Load PCI Addr */
137+};
138+
139+/*
140+ * adapter defines and structures
141+ */
142+#define ICOM_CONTROL_START_A 0x00000008
143+#define ICOM_CONTROL_STOP_A 0x00000004
144+#define ICOM_CONTROL_START_B 0x00000002
145+#define ICOM_CONTROL_STOP_B 0x00000001
146+#define ICOM_CONTROL_START_C 0x00000008
147+#define ICOM_CONTROL_STOP_C 0x00000004
148+#define ICOM_CONTROL_START_D 0x00000002
149+#define ICOM_CONTROL_STOP_D 0x00000001
150+#define ICOM_IRAM_OFFSET 0x1000
151+#define ICOM_IRAM_SIZE 0x0C00
152+#define ICOM_DCE_IRAM_OFFSET 0x0A00
153+#define ICOM_CABLE_ID_VALID 0x01
154+#define ICOM_CABLE_ID_MASK 0xF0
155+#define ICOM_DISABLE 0x80
156+#define CMD_XMIT_RCV_ENABLE 0xC0
157+#define CMD_XMIT_ENABLE 0x40
158+#define CMD_RCV_DISABLE 0x00
159+#define CMD_RCV_ENABLE 0x80
160+#define CMD_RESTART 0x01
161+#define CMD_HOLD_XMIT 0x02
162+#define CMD_SND_BREAK 0x04
163+#define RS232_CABLE 0x06
164+#define V24_CABLE 0x0E
165+#define V35_CABLE 0x0C
166+#define V36_CABLE 0x02
167+#define NO_CABLE 0x00
168+#define START_DOWNLOAD 0x80
169+#define ICOM_INT_MASK_PRC_A 0x00003FFF
170+#define ICOM_INT_MASK_PRC_B 0x3FFF0000
171+#define ICOM_INT_MASK_PRC_C 0x00003FFF
172+#define ICOM_INT_MASK_PRC_D 0x3FFF0000
173+#define INT_RCV_COMPLETED 0x1000
174+#define INT_XMIT_COMPLETED 0x2000
175+#define INT_IDLE_DETECT 0x0800
176+#define INT_RCV_DISABLED 0x0400
177+#define INT_XMIT_DISABLED 0x0200
178+#define INT_RCV_XMIT_SHUTDOWN 0x0100
179+#define INT_FATAL_ERROR 0x0080
180+#define INT_CABLE_PULL 0x0020
181+#define INT_SIGNAL_CHANGE 0x0010
182+#define HDLC_PPP_PURE_ASYNC 0x02
183+#define HDLC_FF_FILL 0x00
184+#define HDLC_HDW_FLOW 0x01
185+#define START_XMIT 0x80
186+#define ICOM_ACFG_DRIVE1 0x20
187+#define ICOM_ACFG_NO_PARITY 0x00
188+#define ICOM_ACFG_PARITY_ENAB 0x02
189+#define ICOM_ACFG_PARITY_ODD 0x01
190+#define ICOM_ACFG_8BPC 0x00
191+#define ICOM_ACFG_7BPC 0x04
192+#define ICOM_ACFG_6BPC 0x08
193+#define ICOM_ACFG_5BPC 0x0C
194+#define ICOM_ACFG_1STOP_BIT 0x00
195+#define ICOM_ACFG_2STOP_BIT 0x10
196+#define ICOM_DTR 0x80
197+#define ICOM_RTS 0x40
198+#define ICOM_RI 0x08
199+#define ICOM_DSR 0x80
200+#define ICOM_DCD 0x20
201+#define ICOM_CTS 0x40
202+
203+#define NUM_XBUFFS 1
204+#define NUM_RBUFFS 2
205+#define RCV_BUFF_SZ 0x0200
206+#define XMIT_BUFF_SZ 0x1000
207+struct statusArea {
208+ /**********************************************/
209+ /* Transmit Status Area */
210+ /**********************************************/
211+ struct xmit_status_area{
212+ __le32 leNext; /* Next entry in Little Endian on Adapter */
213+ __le32 leNextASD;
214+ __le32 leBuffer; /* Buffer for entry in LE for Adapter */
215+ __le16 leLengthASD;
216+ __le16 leOffsetASD;
217+ __le16 leLength; /* Length of data in segment */
218+ __le16 flags;
219+#define SA_FLAGS_DONE 0x0080 /* Done with Segment */
220+#define SA_FLAGS_CONTINUED 0x8000 /* More Segments */
221+#define SA_FLAGS_IDLE 0x4000 /* Mark IDLE after frm */
222+#define SA_FLAGS_READY_TO_XMIT 0x0800
223+#define SA_FLAGS_STAT_MASK 0x007F
224+ } xmit[NUM_XBUFFS];
225+
226+ /**********************************************/
227+ /* Receive Status Area */
228+ /**********************************************/
229+ struct {
230+ __le32 leNext; /* Next entry in Little Endian on Adapter */
231+ __le32 leNextASD;
232+ __le32 leBuffer; /* Buffer for entry in LE for Adapter */
233+ __le16 WorkingLength; /* size of segment */
234+ __le16 reserv01;
235+ __le16 leLength; /* Length of data in segment */
236+ __le16 flags;
237+#define SA_FL_RCV_DONE 0x0010 /* Data ready */
238+#define SA_FLAGS_OVERRUN 0x0040
239+#define SA_FLAGS_PARITY_ERROR 0x0080
240+#define SA_FLAGS_FRAME_ERROR 0x0001
241+#define SA_FLAGS_FRAME_TRUNC 0x0002
242+#define SA_FLAGS_BREAK_DET 0x0004 /* set conditionally by device driver, not hardware */
243+#define SA_FLAGS_RCV_MASK 0xFFE6
244+ } rcv[NUM_RBUFFS];
245+};
246+
247+struct icom_adapter;
248+
249+
250+#define ICOM_MAJOR 243
251+#define ICOM_MINOR_START 0
252+
253+struct icom_port {
254+ struct uart_port uart_port;
255+ unsigned char cable_id;
256+ unsigned char read_status_mask;
257+ unsigned char ignore_status_mask;
258+ void __iomem * int_reg;
259+ struct icom_regs __iomem *global_reg;
260+ struct func_dram __iomem *dram;
261+ int port;
262+ struct statusArea *statStg;
263+ dma_addr_t statStg_pci;
264+ __le32 *xmitRestart;
265+ dma_addr_t xmitRestart_pci;
266+ unsigned char *xmit_buf;
267+ dma_addr_t xmit_buf_pci;
268+ unsigned char *recv_buf;
269+ dma_addr_t recv_buf_pci;
270+ int next_rcv;
271+ int status;
272+#define ICOM_PORT_ACTIVE 1 /* Port exists. */
273+#define ICOM_PORT_OFF 0 /* Port does not exist. */
274+ struct icom_adapter *adapter;
275+};
276+
277+struct icom_adapter {
278+ void __iomem * base_addr;
279+ unsigned long base_addr_pci;
280+ struct pci_dev *pci_dev;
281+ struct icom_port port_info[4];
282+ int index;
283+ int version;
284+#define ADAPTER_V1 0x0001
285+#define ADAPTER_V2 0x0002
286+ u32 subsystem_id;
287+#define FOUR_PORT_MODEL 0x0252
288+#define V2_TWO_PORTS_RVX 0x021A
289+#define V2_ONE_PORT_RVX_ONE_PORT_IMBED_MDM 0x0251
290+ int numb_ports;
291+ struct list_head icom_adapter_entry;
292+ struct kref kref;
293+};
294+
295+/* prototype */
296+extern void iCom_sercons_init(void);
297+
298+struct lookup_proc_table {
299+ u32 __iomem *global_control_reg;
300+ unsigned long processor_id;
301+};
302+
303+struct lookup_int_table {
304+ u32 __iomem *global_int_mask;
305+ unsigned long processor_id;
306+};
307+
308+static inline struct icom_port *to_icom_port(struct uart_port *port)
309+{
310+ return container_of(port, struct icom_port, uart_port);
311+}
53312
54313 static const struct pci_device_id icom_pci_table[] = {
55314 {
@@ -222,7 +481,7 @@ static int get_port_memory(struct icom_port *icom_port) · 166 unmodified lines
222481 if (index < (NUM_XBUFFS - 1)) {
223482 memset(&icom_port->statStg->xmit[index], 0, sizeof(struct xmit_status_area));
224483 icom_port->statStg->xmit[index].leLengthASD =
225− (unsigned short int) cpu_to_le16(XMIT_BUFF_SZ);
484+ cpu_to_le16(XMIT_BUFF_SZ);
226485 trace(icom_port, "FOD_ADDR", stgAddr);
227486 trace(icom_port, "FOD_XBUFF",
228487 (unsigned long) icom_port->xmit_buf);
@@ -231,7 +490,7 @@ static int get_port_memory(struct icom_port *icom_port) · 2 unmodified lines
231490 } else if (index == (NUM_XBUFFS - 1)) {
232491 memset(&icom_port->statStg->xmit[index], 0, sizeof(struct xmit_status_area));
233492 icom_port->statStg->xmit[index].leLengthASD =
234− (unsigned short int) cpu_to_le16(XMIT_BUFF_SZ);
493+ cpu_to_le16(XMIT_BUFF_SZ);
235494 trace(icom_port, "FOD_XBUFF",
236495 (unsigned long) icom_port->xmit_buf);
237496 icom_port->statStg->xmit[index].leBuffer =
@@ -249,7 +508,7 @@ static int get_port_memory(struct icom_port *icom_port) · 11 unmodified lines
249508 stgAddr = stgAddr + sizeof(icom_port->statStg->rcv[0]);
250509 icom_port->statStg->rcv[index].leLength = 0;
251510 icom_port->statStg->rcv[index].WorkingLength =
252− (unsigned short int) cpu_to_le16(RCV_BUFF_SZ);
511+ cpu_to_le16(RCV_BUFF_SZ);
253512 if (index < (NUM_RBUFFS - 1) ) {
254513 offset = stgAddr - (unsigned long) icom_port->statStg;
255514 icom_port->statStg->rcv[index].leNext =
@@ -617,16 +876,17 @@ unlock: · 361 unmodified lines
617876
618877 static int icom_write(struct uart_port *port)
619878 {
879+ struct icom_port *icom_port = to_icom_port(port);
620880 unsigned long data_count;
621881 unsigned char cmdReg;
622882 unsigned long offset;
623883 int temp_tail = port->state->xmit.tail;
624884
625− trace(ICOM_PORT, "WRITE", 0);
885+ trace(icom_port, "WRITE", 0);
626886
627− if (cpu_to_le16(ICOM_PORT->statStg->xmit[0].flags) &
887+ if (le16_to_cpu(icom_port->statStg->xmit[0].flags) &
628888 SA_FLAGS_READY_TO_XMIT) {
629− trace(ICOM_PORT, "WRITE_FULL", 0);
889+ trace(icom_port, "WRITE_FULL", 0);
630890 return 0;
631891 }
632892
@@ -634,7 +894,7 @@ static int icom_write(struct uart_port *port) · 1 unmodified line
634894 while ((port->state->xmit.head != temp_tail) &&
635895 (data_count <= XMIT_BUFF_SZ)) {
636896
637− ICOM_PORT->xmit_buf[data_count++] =
897+ icom_port->xmit_buf[data_count++] =
638898 port->state->xmit.buf[temp_tail];
639899
640900 temp_tail++;
@@ -642,22 +902,22 @@ static int icom_write(struct uart_port *port) · 1 unmodified line
642902 }
643903
644904 if (data_count) {
645− ICOM_PORT->statStg->xmit[0].flags =
905+ icom_port->statStg->xmit[0].flags =
646906 cpu_to_le16(SA_FLAGS_READY_TO_XMIT);
647− ICOM_PORT->statStg->xmit[0].leLength =
907+ icom_port->statStg->xmit[0].leLength =
648908 cpu_to_le16(data_count);
649909 offset =
650− (unsigned long) &ICOM_PORT->statStg->xmit[0] -
651− (unsigned long) ICOM_PORT->statStg;
652− *ICOM_PORT->xmitRestart =
653− cpu_to_le32(ICOM_PORT->statStg_pci + offset);
654− cmdReg = readb(&ICOM_PORT->dram->CmdReg);
910+ (unsigned long) &icom_port->statStg->xmit[0] -
911+ (unsigned long) icom_port->statStg;
912+ *icom_port->xmitRestart =
913+ cpu_to_le32(icom_port->statStg_pci + offset);
914+ cmdReg = readb(&icom_port->dram->CmdReg);
655915 writeb(cmdReg | CMD_XMIT_RCV_ENABLE,
656− &ICOM_PORT->dram->CmdReg);
657− writeb(START_XMIT, &ICOM_PORT->dram->StartXmitCmd);
658− trace(ICOM_PORT, "WRITE_START", data_count);
916+ &icom_port->dram->CmdReg);
917+ writeb(START_XMIT, &icom_port->dram->StartXmitCmd);
918+ trace(icom_port, "WRITE_START", data_count);
659919 /* write flush */
660− readb(&ICOM_PORT->dram->StartXmitCmd);
920+ readb(&icom_port->dram->StartXmitCmd);
661921 }
662922
663923 return data_count;
@@ -696,8 +956,7 @@ static inline void check_modem_status(struct icom_port *icom_port) · 32 unmodified lines
696956
697957 static void xmit_interrupt(u16 port_int_reg, struct icom_port *icom_port)
698958 {
699− unsigned short int count;
700− int i;
959+ u16 count, i;
701960
702961 if (port_int_reg & (INT_XMIT_COMPLETED)) {
703962 trace(icom_port, "XMIT_COMPLETE", 0);
@@ -706,8 +965,7 @@ static void xmit_interrupt(u16 port_int_reg, struct icom_port *icom_port) · 2 unmodified lines
706965 icom_port->statStg->xmit[0].flags &=
707966 cpu_to_le16(~SA_FLAGS_READY_TO_XMIT);
708967
709− count = (unsigned short int)
710− cpu_to_le16(icom_port->statStg->xmit[0].leLength);
968+ count = le16_to_cpu(icom_port->statStg->xmit[0].leLength);
711969 icom_port->uart_port.icount.tx += count;
712970
713971 for (i=0; i<count &&
@@ -729,7 +987,7 @@ static void recv_interrupt(u16 port_int_reg, struct icom_port *icom_port) · 15 unmodified lines
729987 {
730988 short int count, rcv_buff;
731989 struct tty_port *port = &icom_port->uart_port.state->port;
732− unsigned short int status;
990+ u16 status;
733991 struct uart_icount *icount;
734992 unsigned long offset;
735993 unsigned char flag;
@@ -737,19 +995,18 @@ static void recv_interrupt(u16 port_int_reg, struct icom_port *icom_port) · 1 unmodified line
737995 trace(icom_port, "RCV_COMPLETE", 0);
738996 rcv_buff = icom_port->next_rcv;
739997
740− status = cpu_to_le16(icom_port->statStg->rcv[rcv_buff].flags);
998+ status = le16_to_cpu(icom_port->statStg->rcv[rcv_buff].flags);
741999 while (status & SA_FL_RCV_DONE) {
7421000 int first = -1;
7431001
7441002 trace(icom_port, "FID_STATUS", status);
745− count = cpu_to_le16(icom_port->statStg->rcv[rcv_buff].leLength);
1003+ count = le16_to_cpu(icom_port->statStg->rcv[rcv_buff].leLength);
7461004
7471005 trace(icom_port, "RCV_COUNT", count);
7481006
7491007 trace(icom_port, "REAL_COUNT", count);
7501008
751− offset =
752− cpu_to_le32(icom_port->statStg->rcv[rcv_buff].leBuffer) -
1009+ offset = le32_to_cpu(icom_port->statStg->rcv[rcv_buff].leBuffer) -
7531010 icom_port->recv_buf_pci;
7541011
7551012 /* Block copy all but the last byte as this may have status */
@@ -819,13 +1076,13 @@ ignore_char: · 63 unmodified lines
8191076 icom_port->statStg->rcv[rcv_buff].flags = 0;
8201077 icom_port->statStg->rcv[rcv_buff].leLength = 0;
8211078 icom_port->statStg->rcv[rcv_buff].WorkingLength =
822− (unsigned short int) cpu_to_le16(RCV_BUFF_SZ);
1079+ cpu_to_le16(RCV_BUFF_SZ);
8231080
8241081 rcv_buff++;
8251082 if (rcv_buff == NUM_RBUFFS)
8261083 rcv_buff = 0;
8271084
828− status = cpu_to_le16(icom_port->statStg->rcv[rcv_buff].flags);
1085+ status = le16_to_cpu(icom_port->statStg->rcv[rcv_buff].flags);
8291086 }
8301087 icom_port->next_rcv = rcv_buff;
8311088
@@ -925,11 +1182,12 @@ static irqreturn_t icom_interrupt(int irq, void *dev_id) · 93 unmodified lines
9251182 */
9261183 static unsigned int icom_tx_empty(struct uart_port *port)
9271184 {
1185+ struct icom_port *icom_port = to_icom_port(port);
9281186 int ret;
9291187 unsigned long flags;
9301188
9311189 spin_lock_irqsave(&port->lock, flags);
932− if (cpu_to_le16(ICOM_PORT->statStg->xmit[0].flags) &
1190+ if (le16_to_cpu(icom_port->statStg->xmit[0].flags) &
9331191 SA_FLAGS_READY_TO_XMIT)
9341192 ret = TIOCSER_TEMT;
9351193 else
@@ -941,38 +1199,40 @@ static unsigned int icom_tx_empty(struct uart_port *port) · 5 unmodified lines
9411199
9421200 static void icom_set_mctrl(struct uart_port *port, unsigned int mctrl)
9431201 {
1202+ struct icom_port *icom_port = to_icom_port(port);
9441203 unsigned char local_osr;
9451204
946− trace(ICOM_PORT, "SET_MODEM", 0);
947− local_osr = readb(&ICOM_PORT->dram->osr);
1205+ trace(icom_port, "SET_MODEM", 0);
1206+ local_osr = readb(&icom_port->dram->osr);
9481207
9491208 if (mctrl & TIOCM_RTS) {
950− trace(ICOM_PORT, "RAISE_RTS", 0);
1209+ trace(icom_port, "RAISE_RTS", 0);
9511210 local_osr |= ICOM_RTS;
9521211 } else {
953− trace(ICOM_PORT, "LOWER_RTS", 0);
1212+ trace(icom_port, "LOWER_RTS", 0);
9541213 local_osr &= ~ICOM_RTS;
9551214 }
9561215
9571216 if (mctrl & TIOCM_DTR) {
958− trace(ICOM_PORT, "RAISE_DTR", 0);
1217+ trace(icom_port, "RAISE_DTR", 0);
9591218 local_osr |= ICOM_DTR;
9601219 } else {
961− trace(ICOM_PORT, "LOWER_DTR", 0);
1220+ trace(icom_port, "LOWER_DTR", 0);
9621221 local_osr &= ~ICOM_DTR;
9631222 }
9641223
965− writeb(local_osr, &ICOM_PORT->dram->osr);
1224+ writeb(local_osr, &icom_port->dram->osr);
9661225 }
9671226
9681227 static unsigned int icom_get_mctrl(struct uart_port *port)
9691228 {
1229+ struct icom_port *icom_port = to_icom_port(port);
9701230 unsigned char status;
9711231 unsigned int result;
9721232
973− trace(ICOM_PORT, "GET_MODEM", 0);
1233+ trace(icom_port, "GET_MODEM", 0);
9741234
975− status = readb(&ICOM_PORT->dram->isr);
1235+ status = readb(&icom_port->dram->isr);
9761236
9771237 result = ((status & ICOM_DCD) ? TIOCM_CAR : 0)
9781238 | ((status & ICOM_RI) ? TIOCM_RNG : 0)
@@ -983,44 +1243,47 @@ static unsigned int icom_get_mctrl(struct uart_port *port) · 4 unmodified lines
9831243
9841244 static void icom_stop_tx(struct uart_port *port)
9851245 {
1246+ struct icom_port *icom_port = to_icom_port(port);
9861247 unsigned char cmdReg;
9871248
988− trace(ICOM_PORT, "STOP", 0);
989− cmdReg = readb(&ICOM_PORT->dram->CmdReg);
990− writeb(cmdReg | CMD_HOLD_XMIT, &ICOM_PORT->dram->CmdReg);
1249+ trace(icom_port, "STOP", 0);
1250+ cmdReg = readb(&icom_port->dram->CmdReg);
1251+ writeb(cmdReg | CMD_HOLD_XMIT, &icom_port->dram->CmdReg);
9911252 }
9921253
9931254 static void icom_start_tx(struct uart_port *port)
9941255 {
1256+ struct icom_port *icom_port = to_icom_port(port);
9951257 unsigned char cmdReg;
9961258
997− trace(ICOM_PORT, "START", 0);
998− cmdReg = readb(&ICOM_PORT->dram->CmdReg);
1259+ trace(icom_port, "START", 0);
1260+ cmdReg = readb(&icom_port->dram->CmdReg);
9991261 if ((cmdReg & CMD_HOLD_XMIT) == CMD_HOLD_XMIT)
10001262 writeb(cmdReg & ~CMD_HOLD_XMIT,
1001− &ICOM_PORT->dram->CmdReg);
1263+ &icom_port->dram->CmdReg);
10021264
10031265 icom_write(port);
10041266 }
10051267
10061268 static void icom_send_xchar(struct uart_port *port, char ch)
10071269 {
1270+ struct icom_port *icom_port = to_icom_port(port);
10081271 unsigned char xdata;
10091272 int index;
10101273 unsigned long flags;
10111274
1012− trace(ICOM_PORT, "SEND_XCHAR", ch);
1275+ trace(icom_port, "SEND_XCHAR", ch);
10131276
10141277 /* wait .1 sec to send char */
10151278 for (index = 0; index < 10; index++) {
10161279 spin_lock_irqsave(&port->lock, flags);
1017− xdata = readb(&ICOM_PORT->dram->xchar);
1280+ xdata = readb(&icom_port->dram->xchar);
10181281 if (xdata == 0x00) {
1019− trace(ICOM_PORT, "QUICK_WRITE", 0);
1020− writeb(ch, &ICOM_PORT->dram->xchar);
1282+ trace(icom_port, "QUICK_WRITE", 0);
1283+ writeb(ch, &icom_port->dram->xchar);
10211284
10221285 /* flush write operation */
1023− xdata = readb(&ICOM_PORT->dram->xchar);
1286+ xdata = readb(&icom_port->dram->xchar);
10241287 spin_unlock_irqrestore(&port->lock, flags);
10251288 break;
10261289 }
@@ -1031,38 +1294,41 @@ static void icom_send_xchar(struct uart_port *port, char ch) · 4 unmodified lines
10311294
10321295 static void icom_stop_rx(struct uart_port *port)
10331296 {
1297+ struct icom_port *icom_port = to_icom_port(port);
10341298 unsigned char cmdReg;
10351299
1036− cmdReg = readb(&ICOM_PORT->dram->CmdReg);
1037− writeb(cmdReg & ~CMD_RCV_ENABLE, &ICOM_PORT->dram->CmdReg);
1300+ cmdReg = readb(&icom_port->dram->CmdReg);
1301+ writeb(cmdReg & ~CMD_RCV_ENABLE, &icom_port->dram->CmdReg);
10381302 }
10391303
10401304 static void icom_break(struct uart_port *port, int break_state)
10411305 {
1306+ struct icom_port *icom_port = to_icom_port(port);
10421307 unsigned char cmdReg;
10431308 unsigned long flags;
10441309
10451310 spin_lock_irqsave(&port->lock, flags);
1046− trace(ICOM_PORT, "BREAK", 0);
1047− cmdReg = readb(&ICOM_PORT->dram->CmdReg);
1311+ trace(icom_port, "BREAK", 0);
1312+ cmdReg = readb(&icom_port->dram->CmdReg);
10481313 if (break_state == -1) {
1049− writeb(cmdReg | CMD_SND_BREAK, &ICOM_PORT->dram->CmdReg);
1314+ writeb(cmdReg | CMD_SND_BREAK, &icom_port->dram->CmdReg);
10501315 } else {
1051− writeb(cmdReg & ~CMD_SND_BREAK, &ICOM_PORT->dram->CmdReg);
1316+ writeb(cmdReg & ~CMD_SND_BREAK, &icom_port->dram->CmdReg);
10521317 }
10531318 spin_unlock_irqrestore(&port->lock, flags);
10541319 }
10551320
10561321 static int icom_open(struct uart_port *port)
10571322 {
1323+ struct icom_port *icom_port = to_icom_port(port);
10581324 int retval;
10591325
1060− kref_get(&ICOM_PORT->adapter->kref);
1061− retval = startup(ICOM_PORT);
1326+ kref_get(&icom_port->adapter->kref);
1327+ retval = startup(icom_port);
10621328
10631329 if (retval) {
1064− kref_put(&ICOM_PORT->adapter->kref, icom_kref_release);
1065− trace(ICOM_PORT, "STARTUP_ERROR", 0);
1330+ kref_put(&icom_port->adapter->kref, icom_kref_release);
1331+ trace(icom_port, "STARTUP_ERROR", 0);
10661332 return retval;
10671333 }
10681334
@@ -1071,23 +1337,25 @@ static int icom_open(struct uart_port *port) · 2 unmodified lines
10711337
10721338 static void icom_close(struct uart_port *port)
10731339 {
1340+ struct icom_port *icom_port = to_icom_port(port);
10741341 unsigned char cmdReg;
10751342
1076− trace(ICOM_PORT, "CLOSE", 0);
1343+ trace(icom_port, "CLOSE", 0);
10771344
10781345 /* stop receiver */
1079− cmdReg = readb(&ICOM_PORT->dram->CmdReg);
1080− writeb(cmdReg & ~CMD_RCV_ENABLE, &ICOM_PORT->dram->CmdReg);
1346+ cmdReg = readb(&icom_port->dram->CmdReg);
1347+ writeb(cmdReg & ~CMD_RCV_ENABLE, &icom_port->dram->CmdReg);
10811348
1082− shutdown(ICOM_PORT);
1349+ shutdown(icom_port);
10831350
1084− kref_put(&ICOM_PORT->adapter->kref, icom_kref_release);
1351+ kref_put(&icom_port->adapter->kref, icom_kref_release);
10851352 }
10861353
10871354 static void icom_set_termios(struct uart_port *port,
10881355 struct ktermios *termios,
10891356 struct ktermios *old_termios)
10901357 {
1358+ struct icom_port *icom_port = to_icom_port(port);
10911359 int baud;
10921360 unsigned cflag, iflag;
10931361 char new_config2;
@@ -1099,7 +1367,7 @@ static void icom_set_termios(struct uart_port *port, · 5 unmodified lines
10991367 unsigned long flags;
11001368
11011369 spin_lock_irqsave(&port->lock, flags);
1102− trace(ICOM_PORT, "CHANGE_SPEED", 0);
1370+ trace(icom_port, "CHANGE_SPEED", 0);
11031371
11041372 cflag = termios->c_cflag;
11051373 iflag = termios->c_iflag;
@@ -1130,12 +1398,12 @@ static void icom_set_termios(struct uart_port *port, · 24 unmodified lines
11301398 if (cflag & PARENB) {
11311399 /* parity bit enabled */
11321400 new_config2 |= ICOM_ACFG_PARITY_ENAB;
1133− trace(ICOM_PORT, "PARENB", 0);
1401+ trace(icom_port, "PARENB", 0);
11341402 }
11351403 if (cflag & PARODD) {
11361404 /* odd parity */
11371405 new_config2 |= ICOM_ACFG_PARITY_ODD;
1138− trace(ICOM_PORT, "PARODD", 0);
1406+ trace(icom_port, "PARODD", 0);
11391407 }
11401408
11411409 /* Determine divisor based on baud rate */
@@ -1155,100 +1423,99 @@ static void icom_set_termios(struct uart_port *port, · 13 unmodified lines
11551423 uart_update_timeout(port, cflag, baud);
11561424
11571425 /* CTS flow control flag and modem status interrupts */
1158− tmp_byte = readb(&(ICOM_PORT->dram->HDLCConfigReg));
1426+ tmp_byte = readb(&(icom_port->dram->HDLCConfigReg));
11591427 if (cflag & CRTSCTS)
11601428 tmp_byte |= HDLC_HDW_FLOW;
11611429 else
11621430 tmp_byte &= ~HDLC_HDW_FLOW;
1163− writeb(tmp_byte, &(ICOM_PORT->dram->HDLCConfigReg));
1431+ writeb(tmp_byte, &(icom_port->dram->HDLCConfigReg));
11641432
11651433 /*
11661434 * Set up parity check flag
11671435 */
1168− ICOM_PORT->read_status_mask = SA_FLAGS_OVERRUN | SA_FL_RCV_DONE;
1436+ icom_port->read_status_mask = SA_FLAGS_OVERRUN | SA_FL_RCV_DONE;
11691437 if (iflag & INPCK)
1170− ICOM_PORT->read_status_mask |=
1438+ icom_port->read_status_mask |=
11711439 SA_FLAGS_FRAME_ERROR | SA_FLAGS_PARITY_ERROR;
11721440
11731441 if ((iflag & BRKINT) || (iflag & PARMRK))
1174− ICOM_PORT->read_status_mask |= SA_FLAGS_BREAK_DET;
1442+ icom_port->read_status_mask |= SA_FLAGS_BREAK_DET;
11751443
11761444 /*
11771445 * Characters to ignore
11781446 */
1179− ICOM_PORT->ignore_status_mask = 0;
1447+ icom_port->ignore_status_mask = 0;
11801448 if (iflag & IGNPAR)
1181− ICOM_PORT->ignore_status_mask |=
1449+ icom_port->ignore_status_mask |=
11821450 SA_FLAGS_PARITY_ERROR | SA_FLAGS_FRAME_ERROR;
11831451 if (iflag & IGNBRK) {
1184− ICOM_PORT->ignore_status_mask |= SA_FLAGS_BREAK_DET;
1452+ icom_port->ignore_status_mask |= SA_FLAGS_BREAK_DET;
11851453 /*
11861454 * If we're ignore parity and break indicators, ignore
11871455 * overruns too. (For real raw support).
11881456 */
11891457 if (iflag & IGNPAR)
1190− ICOM_PORT->ignore_status_mask |= SA_FLAGS_OVERRUN;
1458+ icom_port->ignore_status_mask |= SA_FLAGS_OVERRUN;
11911459 }
11921460
11931461 /*
11941462 * !!! ignore all characters if CREAD is not set
11951463 */
11961464 if ((cflag & CREAD) == 0)
1197− ICOM_PORT->ignore_status_mask |= SA_FL_RCV_DONE;
1465+ icom_port->ignore_status_mask |= SA_FL_RCV_DONE;
11981466
11991467 /* Turn off Receiver to prepare for reset */
1200− writeb(CMD_RCV_DISABLE, &ICOM_PORT->dram->CmdReg);
1468+ writeb(CMD_RCV_DISABLE, &icom_port->dram->CmdReg);
12011469
12021470 for (index = 0; index < 10; index++) {
1203− if (readb(&ICOM_PORT->dram->PrevCmdReg) == 0x00) {
1471+ if (readb(&icom_port->dram->PrevCmdReg) == 0x00) {
12041472 break;
12051473 }
12061474 }
12071475
12081476 /* clear all current buffers of data */
12091477 for (rcv_buff = 0; rcv_buff < NUM_RBUFFS; rcv_buff++) {
1210− ICOM_PORT->statStg->rcv[rcv_buff].flags = 0;
1211− ICOM_PORT->statStg->rcv[rcv_buff].leLength = 0;
1212− ICOM_PORT->statStg->rcv[rcv_buff].WorkingLength =
1213− (unsigned short int) cpu_to_le16(RCV_BUFF_SZ);
1478+ icom_port->statStg->rcv[rcv_buff].flags = 0;
1479+ icom_port->statStg->rcv[rcv_buff].leLength = 0;
1480+ icom_port->statStg->rcv[rcv_buff].WorkingLength =
1481+ cpu_to_le16(RCV_BUFF_SZ);
12141482 }
12151483
12161484 for (xmit_buff = 0; xmit_buff < NUM_XBUFFS; xmit_buff++) {
1217− ICOM_PORT->statStg->xmit[xmit_buff].flags = 0;
1485+ icom_port->statStg->xmit[xmit_buff].flags = 0;
12181486 }
12191487
12201488 /* activate changes and start xmit and receiver here */
12211489 /* Enable the receiver */
1222− writeb(new_config3, &(ICOM_PORT->dram->async_config3));
1223− writeb(new_config2, &(ICOM_PORT->dram->async_config2));
1224− tmp_byte = readb(&(ICOM_PORT->dram->HDLCConfigReg));
1490+ writeb(new_config3, &(icom_port->dram->async_config3));
1491+ writeb(new_config2, &(icom_port->dram->async_config2));
1492+ tmp_byte = readb(&(icom_port->dram->HDLCConfigReg));
12251493 tmp_byte |= HDLC_PPP_PURE_ASYNC | HDLC_FF_FILL;
1226− writeb(tmp_byte, &(ICOM_PORT->dram->HDLCConfigReg));
1227− writeb(0x04, &(ICOM_PORT->dram->FlagFillIdleTimer)); /* 0.5 seconds */
1228− writeb(0xFF, &(ICOM_PORT->dram->ier)); /* enable modem signal interrupts */
1494+ writeb(tmp_byte, &(icom_port->dram->HDLCConfigReg));
1495+ writeb(0x04, &(icom_port->dram->FlagFillIdleTimer)); /* 0.5 seconds */
1496+ writeb(0xFF, &(icom_port->dram->ier)); /* enable modem signal interrupts */
12291497
12301498 /* reset processor */
1231− writeb(CMD_RESTART, &ICOM_PORT->dram->CmdReg);
1499+ writeb(CMD_RESTART, &icom_port->dram->CmdReg);
12321500
12331501 for (index = 0; index < 10; index++) {
1234− if (readb(&ICOM_PORT->dram->CmdReg) == 0x00) {
1502+ if (readb(&icom_port->dram->CmdReg) == 0x00) {
12351503 break;
12361504 }
12371505 }
12381506
12391507 /* Enable Transmitter and Receiver */
12401508 offset =
1241− (unsigned long) &ICOM_PORT->statStg->rcv[0] -
1242− (unsigned long) ICOM_PORT->statStg;
1243− writel(ICOM_PORT->statStg_pci + offset,
1244− &ICOM_PORT->dram->RcvStatusAddr);
1245− ICOM_PORT->next_rcv = 0;
1246− ICOM_PORT->put_length = 0;
1247− *ICOM_PORT->xmitRestart = 0;
1248− writel(ICOM_PORT->xmitRestart_pci,
1249− &ICOM_PORT->dram->XmitStatusAddr);
1250− trace(ICOM_PORT, "XR_ENAB", 0);
1251− writeb(CMD_XMIT_RCV_ENABLE, &ICOM_PORT->dram->CmdReg);
1509+ (unsigned long) &icom_port->statStg->rcv[0] -
1510+ (unsigned long) icom_port->statStg;
1511+ writel(icom_port->statStg_pci + offset,
1512+ &icom_port->dram->RcvStatusAddr);
1513+ icom_port->next_rcv = 0;
1514+ *icom_port->xmitRestart = 0;
1515+ writel(icom_port->xmitRestart_pci,
1516+ &icom_port->dram->XmitStatusAddr);
1517+ trace(icom_port, "XR_ENAB", 0);
1518+ writeb(CMD_XMIT_RCV_ENABLE, &icom_port->dram->CmdReg);
12521519
12531520 spin_unlock_irqrestore(&port->lock, flags);
12541521 }
@@ -1258,15 +1525,6 @@ static const char *icom_type(struct uart_port *port) · 3 unmodified lines
12581525 return "icom";
12591526 }
12601527
1261−static void icom_release_port(struct uart_port *port)
1262−{
1263−}
1264−
1265−static int icom_request_port(struct uart_port *port)
1266−{
1267− return 0;
1268−}
1269−
12701528 static void icom_config_port(struct uart_port *port, int flags)
12711529 {
12721530 port->type = PORT_ICOM;
@@ -1285,8 +1543,6 @@ static const struct uart_ops icom_ops = { · 12 unmodified lines
12851543 .shutdown = icom_close,
12861544 .set_termios = icom_set_termios,
12871545 .type = icom_type,
1288− .release_port = icom_release_port,
1289− .request_port = icom_request_port,
12901546 .config_port = icom_config_port,
12911547 };
12921548
@@ -1315,7 +1571,6 @@ static int icom_init_ports(struct icom_adapter *icom_adapter) · 22 unmodified lines
13151571 icom_port = &icom_adapter->port_info[i];
13161572 icom_port->port = i;
13171573 icom_port->status = ICOM_PORT_ACTIVE;
1318− icom_port->imbed_modem = ICOM_UNKNOWN;
13191574 }
13201575 } else {
13211576 if (subsystem_id == PCI_DEVICE_ID_IBM_ICOM_FOUR_PORT_MODEL) {
@@ -1326,26 +1581,15 @@ static int icom_init_ports(struct icom_adapter *icom_adapter) · 4 unmodified lines
13261581
13271582 icom_port->port = i;
13281583 icom_port->status = ICOM_PORT_ACTIVE;
1329− icom_port->imbed_modem = ICOM_IMBED_MODEM;
13301584 }
13311585 } else {
13321586 icom_adapter->numb_ports = 4;
13331587
13341588 icom_adapter->port_info[0].port = 0;
13351589 icom_adapter->port_info[0].status = ICOM_PORT_ACTIVE;
1336−
1337− if (subsystem_id ==
1338− PCI_DEVICE_ID_IBM_ICOM_V2_ONE_PORT_RVX_ONE_PORT_MDM) {
1339− icom_adapter->port_info[0].imbed_modem = ICOM_IMBED_MODEM;
1340− } else {
1341− icom_adapter->port_info[0].imbed_modem = ICOM_RVX;
1342− }
1343−
13441590 icom_adapter->port_info[1].status = ICOM_PORT_OFF;
1345−
13461591 icom_adapter->port_info[2].port = 2;
13471592 icom_adapter->port_info[2].status = ICOM_PORT_ACTIVE;
1348− icom_adapter->port_info[2].imbed_modem = ICOM_RVX;
13491593 icom_adapter->port_info[3].status = ICOM_PORT_OFF;
13501594 }
13511595 }
@@ -1401,7 +1645,6 @@ static int icom_alloc_adapter(struct icom_adapter · 49 unmodified lines
14011645 int adapter_count = 0;
14021646 struct icom_adapter *icom_adapter;
14031647 struct icom_adapter *cur_adapter_entry;
1404− struct list_head *tmp;
14051648
14061649 icom_adapter = kzalloc(sizeof(struct icom_adapter), GFP_KERNEL);
14071650
@@ -1409,10 +1652,8 @@ static int icom_alloc_adapter(struct icom_adapter · 1 unmodified line
14091652 return -ENOMEM;
14101653 }
14111654
1412− list_for_each(tmp, &icom_adapter_head) {
1413− cur_adapter_entry =
1414− list_entry(tmp, struct icom_adapter,
1415− icom_adapter_entry);
1655+ list_for_each_entry(cur_adapter_entry, &icom_adapter_head,
1656+ icom_adapter_entry) {
14161657 if (cur_adapter_entry->index != adapter_count) {
14171658 break;
14181659 }
@@ -1420,7 +1661,8 @@ static int icom_alloc_adapter(struct icom_adapter · 1 unmodified line
14201661 }
14211662
14221663 icom_adapter->index = adapter_count;
1423− list_add_tail(&icom_adapter->icom_adapter_entry, tmp);
1664+ list_add_tail(&icom_adapter->icom_adapter_entry,
1665+ &cur_adapter_entry->icom_adapter_entry);
14241666
14251667 *icom_adapter_ref = icom_adapter;
14261668 return 0;
@@ -1432,8 +1674,10 @@ static void icom_free_adapter(struct icom_adapter *icom_adapter) · 5 unmodified lines
14321674 kfree(icom_adapter);
14331675 }
14341676
1435−static void icom_remove_adapter(struct icom_adapter *icom_adapter)
1677+static void icom_kref_release(struct kref *kref)
14361678 {
1679+ struct icom_adapter *icom_adapter = container_of(kref,
1680+ struct icom_adapter, kref);
14371681 struct icom_port *icom_port;
14381682 int index;
14391683
@@ -1466,14 +1710,6 @@ static void icom_remove_adapter(struct icom_adapter *icom_adapter) · 26 unmodified lines
14661710 icom_free_adapter(icom_adapter);
14671711 }
14681712
1469−static void icom_kref_release(struct kref *kref)
1470−{
1471− struct icom_adapter *icom_adapter;
1472−
1473− icom_adapter = to_icom_adapter(kref);
1474− icom_remove_adapter(icom_adapter);
1475−}
1476−
14771713 static int icom_probe(struct pci_dev *dev,
14781714 const struct pci_device_id *ent)
14791715 {
@@ -1501,7 +1737,7 @@ static int icom_probe(struct pci_dev *dev, · 21 unmodified lines
15011737 retval = pci_read_config_dword(dev, PCI_COMMAND, &command_reg);
15021738 if (retval) {
15031739 dev_err(&dev->dev, "PCI Config read FAILED\n");
1504− return retval;
1740+ goto probe_exit0;
15051741 }
15061742
15071743 pci_write_config_dword(dev, PCI_COMMAND,
@@ -1589,11 +1825,9 @@ probe_exit0: · 81 unmodified lines
15891825 static void icom_remove(struct pci_dev *dev)
15901826 {
15911827 struct icom_adapter *icom_adapter;
1592− struct list_head *tmp;
15931828
1594− list_for_each(tmp, &icom_adapter_head) {
1595− icom_adapter = list_entry(tmp, struct icom_adapter,
1596− icom_adapter_entry);
1829+ list_for_each_entry(icom_adapter, &icom_adapter_head,
1830+ icom_adapter_entry) {
15971831 if (icom_adapter->pci_dev == dev) {
15981832 kref_put(&icom_adapter->kref, icom_kref_release);
15991833 return;
drivers/tty/serial/icom.h+0−274
@@ -1,274 +0,0 @@
1−/* SPDX-License-Identifier: GPL-2.0+ */
2−/*
3− * icom.h
4− *
5− * Copyright (C) 2001 Michael Anderson, IBM Corporation
6− *
7− * Serial device driver include file.
8− */
9−
10−#include <linux/serial_core.h>
11−
12−#define BAUD_TABLE_LIMIT ((sizeof(icom_acfg_baud)/sizeof(int)) - 1)
13−static int icom_acfg_baud[] = {
14− 300,
15− 600,
16− 900,
17− 1200,
18− 1800,
19− 2400,
20− 3600,
21− 4800,
22− 7200,
23− 9600,
24− 14400,
25− 19200,
26− 28800,
27− 38400,
28− 57600,
29− 76800,
30− 115200,
31− 153600,
32− 230400,
33− 307200,
34− 460800,
35−};
36−
37−struct icom_regs {
38− u32 control; /* Adapter Control Register */
39− u32 interrupt; /* Adapter Interrupt Register */
40− u32 int_mask; /* Adapter Interrupt Mask Reg */
41− u32 int_pri; /* Adapter Interrupt Priority r */
42− u32 int_reg_b; /* Adapter non-masked Interrupt */
43− u32 resvd01;
44− u32 resvd02;
45− u32 resvd03;
46− u32 control_2; /* Adapter Control Register 2 */
47− u32 interrupt_2; /* Adapter Interrupt Register 2 */
48− u32 int_mask_2; /* Adapter Interrupt Mask 2 */
49− u32 int_pri_2; /* Adapter Interrupt Prior 2 */
50− u32 int_reg_2b; /* Adapter non-masked 2 */
51−};
52−
53−struct func_dram {
54− u32 reserved[108]; /* 0-1B0 reserved by personality code */
55− u32 RcvStatusAddr; /* 1B0-1B3 Status Address for Next rcv */
56− u8 RcvStnAddr; /* 1B4 Receive Station Addr */
57− u8 IdleState; /* 1B5 Idle State */
58− u8 IdleMonitor; /* 1B6 Idle Monitor */
59− u8 FlagFillIdleTimer; /* 1B7 Flag Fill Idle Timer */
60− u32 XmitStatusAddr; /* 1B8-1BB Transmit Status Address */
61− u8 StartXmitCmd; /* 1BC Start Xmit Command */
62− u8 HDLCConfigReg; /* 1BD Reserved */
63− u8 CauseCode; /* 1BE Cause code for fatal error */
64− u8 xchar; /* 1BF High priority send */
65− u32 reserved3; /* 1C0-1C3 Reserved */
66− u8 PrevCmdReg; /* 1C4 Reserved */
67− u8 CmdReg; /* 1C5 Command Register */
68− u8 async_config2; /* 1C6 Async Config Byte 2 */
69− u8 async_config3; /* 1C7 Async Config Byte 3 */
70− u8 dce_resvd[20]; /* 1C8-1DB DCE Rsvd */
71− u8 dce_resvd21; /* 1DC DCE Rsvd (21st byte */
72− u8 misc_flags; /* 1DD misc flags */
73−#define V2_HARDWARE 0x40
74−#define ICOM_HDW_ACTIVE 0x01
75− u8 call_length; /* 1DE Phone #/CFI buff ln */
76− u8 call_length2; /* 1DF Upper byte (unused) */
77− u32 call_addr; /* 1E0-1E3 Phn #/CFI buff addr */
78− u16 timer_value; /* 1E4-1E5 general timer value */
79− u8 timer_command; /* 1E6 general timer cmd */
80− u8 dce_command; /* 1E7 dce command reg */
81− u8 dce_cmd_status; /* 1E8 dce command stat */
82− u8 x21_r1_ioff; /* 1E9 dce ready counter */
83− u8 x21_r0_ioff; /* 1EA dce not ready ctr */
84− u8 x21_ralt_ioff; /* 1EB dce CNR counter */
85− u8 x21_r1_ion; /* 1EC dce ready I on ctr */
86− u8 rsvd_ier; /* 1ED Rsvd for IER (if ne */
87− u8 ier; /* 1EE Interrupt Enable */
88− u8 isr; /* 1EF Input Signal Reg */
89− u8 osr; /* 1F0 Output Signal Reg */
90− u8 reset; /* 1F1 Reset/Reload Reg */
91− u8 disable; /* 1F2 Disable Reg */
92− u8 sync; /* 1F3 Sync Reg */
93− u8 error_stat; /* 1F4 Error Status */
94− u8 cable_id; /* 1F5 Cable ID */
95− u8 cs_length; /* 1F6 CS Load Length */
96− u8 mac_length; /* 1F7 Mac Load Length */
97− u32 cs_load_addr; /* 1F8-1FB Call Load PCI Addr */
98− u32 mac_load_addr; /* 1FC-1FF Mac Load PCI Addr */
99−};
100−
101−/*
102− * adapter defines and structures
103− */
104−#define ICOM_CONTROL_START_A 0x00000008
105−#define ICOM_CONTROL_STOP_A 0x00000004
106−#define ICOM_CONTROL_START_B 0x00000002
107−#define ICOM_CONTROL_STOP_B 0x00000001
108−#define ICOM_CONTROL_START_C 0x00000008
109−#define ICOM_CONTROL_STOP_C 0x00000004
110−#define ICOM_CONTROL_START_D 0x00000002
111−#define ICOM_CONTROL_STOP_D 0x00000001
112−#define ICOM_IRAM_OFFSET 0x1000
113−#define ICOM_IRAM_SIZE 0x0C00
114−#define ICOM_DCE_IRAM_OFFSET 0x0A00
115−#define ICOM_CABLE_ID_VALID 0x01
116−#define ICOM_CABLE_ID_MASK 0xF0
117−#define ICOM_DISABLE 0x80
118−#define CMD_XMIT_RCV_ENABLE 0xC0
119−#define CMD_XMIT_ENABLE 0x40
120−#define CMD_RCV_DISABLE 0x00
121−#define CMD_RCV_ENABLE 0x80
122−#define CMD_RESTART 0x01
123−#define CMD_HOLD_XMIT 0x02
124−#define CMD_SND_BREAK 0x04
125−#define RS232_CABLE 0x06
126−#define V24_CABLE 0x0E
127−#define V35_CABLE 0x0C
128−#define V36_CABLE 0x02
129−#define NO_CABLE 0x00
130−#define START_DOWNLOAD 0x80
131−#define ICOM_INT_MASK_PRC_A 0x00003FFF
132−#define ICOM_INT_MASK_PRC_B 0x3FFF0000
133−#define ICOM_INT_MASK_PRC_C 0x00003FFF
134−#define ICOM_INT_MASK_PRC_D 0x3FFF0000
135−#define INT_RCV_COMPLETED 0x1000
136−#define INT_XMIT_COMPLETED 0x2000
137−#define INT_IDLE_DETECT 0x0800
138−#define INT_RCV_DISABLED 0x0400
139−#define INT_XMIT_DISABLED 0x0200
140−#define INT_RCV_XMIT_SHUTDOWN 0x0100
141−#define INT_FATAL_ERROR 0x0080
142−#define INT_CABLE_PULL 0x0020
143−#define INT_SIGNAL_CHANGE 0x0010
144−#define HDLC_PPP_PURE_ASYNC 0x02
145−#define HDLC_FF_FILL 0x00
146−#define HDLC_HDW_FLOW 0x01
147−#define START_XMIT 0x80
148−#define ICOM_ACFG_DRIVE1 0x20
149−#define ICOM_ACFG_NO_PARITY 0x00
150−#define ICOM_ACFG_PARITY_ENAB 0x02
151−#define ICOM_ACFG_PARITY_ODD 0x01
152−#define ICOM_ACFG_8BPC 0x00
153−#define ICOM_ACFG_7BPC 0x04
154−#define ICOM_ACFG_6BPC 0x08
155−#define ICOM_ACFG_5BPC 0x0C
156−#define ICOM_ACFG_1STOP_BIT 0x00
157−#define ICOM_ACFG_2STOP_BIT 0x10
158−#define ICOM_DTR 0x80
159−#define ICOM_RTS 0x40
160−#define ICOM_RI 0x08
161−#define ICOM_DSR 0x80
162−#define ICOM_DCD 0x20
163−#define ICOM_CTS 0x40
164−
165−#define NUM_XBUFFS 1
166−#define NUM_RBUFFS 2
167−#define RCV_BUFF_SZ 0x0200
168−#define XMIT_BUFF_SZ 0x1000
169−struct statusArea {
170− /**********************************************/
171− /* Transmit Status Area */
172− /**********************************************/
173− struct xmit_status_area{
174− u32 leNext; /* Next entry in Little Endian on Adapter */
175− u32 leNextASD;
176− u32 leBuffer; /* Buffer for entry in LE for Adapter */
177− u16 leLengthASD;
178− u16 leOffsetASD;
179− u16 leLength; /* Length of data in segment */
180− u16 flags;
181−#define SA_FLAGS_DONE 0x0080 /* Done with Segment */
182−#define SA_FLAGS_CONTINUED 0x8000 /* More Segments */
183−#define SA_FLAGS_IDLE 0x4000 /* Mark IDLE after frm */
184−#define SA_FLAGS_READY_TO_XMIT 0x0800
185−#define SA_FLAGS_STAT_MASK 0x007F
186− } xmit[NUM_XBUFFS];
187−
188− /**********************************************/
189− /* Receive Status Area */
190− /**********************************************/
191− struct {
192− u32 leNext; /* Next entry in Little Endian on Adapter */
193− u32 leNextASD;
194− u32 leBuffer; /* Buffer for entry in LE for Adapter */
195− u16 WorkingLength; /* size of segment */
196− u16 reserv01;
197− u16 leLength; /* Length of data in segment */
198− u16 flags;
199−#define SA_FL_RCV_DONE 0x0010 /* Data ready */
200−#define SA_FLAGS_OVERRUN 0x0040
201−#define SA_FLAGS_PARITY_ERROR 0x0080
202−#define SA_FLAGS_FRAME_ERROR 0x0001
203−#define SA_FLAGS_FRAME_TRUNC 0x0002
204−#define SA_FLAGS_BREAK_DET 0x0004 /* set conditionally by device driver, not hardware */
205−#define SA_FLAGS_RCV_MASK 0xFFE6
206− } rcv[NUM_RBUFFS];
207−};
208−
209−struct icom_adapter;
210−
211−
212−#define ICOM_MAJOR 243
213−#define ICOM_MINOR_START 0
214−
215−struct icom_port {
216− struct uart_port uart_port;
217− u8 imbed_modem;
218−#define ICOM_UNKNOWN 1
219−#define ICOM_RVX 2
220−#define ICOM_IMBED_MODEM 3
221− unsigned char cable_id;
222− unsigned char read_status_mask;
223− unsigned char ignore_status_mask;
224− void __iomem * int_reg;
225− struct icom_regs __iomem *global_reg;
226− struct func_dram __iomem *dram;
227− int port;
228− struct statusArea *statStg;
229− dma_addr_t statStg_pci;
230− u32 *xmitRestart;
231− dma_addr_t xmitRestart_pci;
232− unsigned char *xmit_buf;
233− dma_addr_t xmit_buf_pci;
234− unsigned char *recv_buf;
235− dma_addr_t recv_buf_pci;
236− int next_rcv;
237− int put_length;
238− int status;
239−#define ICOM_PORT_ACTIVE 1 /* Port exists. */
240−#define ICOM_PORT_OFF 0 /* Port does not exist. */
241− int load_in_progress;
242− struct icom_adapter *adapter;
243−};
244−
245−struct icom_adapter {
246− void __iomem * base_addr;
247− unsigned long base_addr_pci;
248− struct pci_dev *pci_dev;
249− struct icom_port port_info[4];
250− int index;
251− int version;
252−#define ADAPTER_V1 0x0001
253−#define ADAPTER_V2 0x0002
254− u32 subsystem_id;
255−#define FOUR_PORT_MODEL 0x0252
256−#define V2_TWO_PORTS_RVX 0x021A
257−#define V2_ONE_PORT_RVX_ONE_PORT_IMBED_MDM 0x0251
258− int numb_ports;
259− struct list_head icom_adapter_entry;
260− struct kref kref;
261−};
262−
263−/* prototype */
264−extern void iCom_sercons_init(void);
265−
266−struct lookup_proc_table {
267− u32 __iomem *global_control_reg;
268− unsigned long processor_id;
269−};
270−
271−struct lookup_int_table {
272− u32 __iomem *global_int_mask;
273− unsigned long processor_id;
274−};
drivers/tty/serial/imx.c+0−2
@@ -1937,8 +1937,6 @@ static int imx_uart_rs485_config(struct uart_port *port, · 1936 unmodified lines
19371937 rs485conf->flags & SER_RS485_RX_DURING_TX)
19381938 imx_uart_start_rx(port);
19391939
1940− port->rs485 = *rs485conf;
1941−
19421940 return 0;
19431941 }
19441942
drivers/tty/serial/jsm/jsm_cls.c+1−7
@@ -689,7 +689,7 @@ static void cls_param(struct jsm_channel *ch) · 688 unmodified lines
689689 /*
690690 * If baud rate is zero, flush queues, and set mval to drop DTR.
691691 */
692− if ((ch->ch_c_cflag & (CBAUD)) == 0) {
692+ if ((ch->ch_c_cflag & CBAUD) == B0) {
693693 ch->ch_r_head = 0;
694694 ch->ch_r_tail = 0;
695695 ch->ch_e_head = 0;
@@ -723,14 +723,8 @@ static void cls_param(struct jsm_channel *ch) · 27 unmodified lines
723723 if (!(ch->ch_c_cflag & PARODD))
724724 lcr |= UART_LCR_EPAR;
725725
726− /*
727− * Not all platforms support mark/space parity,
728− * so this will hide behind an ifdef.
729− */
730−#ifdef CMSPAR
731726 if (ch->ch_c_cflag & CMSPAR)
732727 lcr |= UART_LCR_SPAR;
733−#endif
734728
735729 if (ch->ch_c_cflag & CSTOPB)
736730 lcr |= UART_LCR_STOP;
drivers/tty/serial/jsm/jsm_neo.c+1−7
@@ -938,7 +938,7 @@ static void neo_param(struct jsm_channel *ch) · 937 unmodified lines
938938 /*
939939 * If baud rate is zero, flush queues, and set mval to drop DTR.
940940 */
941− if ((ch->ch_c_cflag & (CBAUD)) == 0) {
941+ if ((ch->ch_c_cflag & CBAUD) == B0) {
942942 ch->ch_r_head = ch->ch_r_tail = 0;
943943 ch->ch_e_head = ch->ch_e_tail = 0;
944944
@@ -997,14 +997,8 @@ static void neo_param(struct jsm_channel *ch) · 52 unmodified lines
997997 if (!(ch->ch_c_cflag & PARODD))
998998 lcr |= UART_LCR_EPAR;
999999
1000− /*
1001− * Not all platforms support mark/space parity,
1002− * so this will hide behind an ifdef.
1003− */
1004−#ifdef CMSPAR
10051000 if (ch->ch_c_cflag & CMSPAR)
10061001 lcr |= UART_LCR_SPAR;
1007−#endif
10081002
10091003 if (ch->ch_c_cflag & CSTOPB)
10101004 lcr |= UART_LCR_STOP;
drivers/tty/serial/max310x.c+0−1
@@ -1037,7 +1037,6 @@ static int max310x_rs485_config(struct uart_port *port, · 1036 unmodified lines
10371037
10381038 rs485->flags &= SER_RS485_RTS_ON_SEND | SER_RS485_RX_DURING_TX |
10391039 SER_RS485_ENABLED;
1040− memset(rs485->padding, 0, sizeof(rs485->padding));
10411040 port->rs485 = *rs485;
10421041
10431042 schedule_work(&one->rs_work);
drivers/tty/serial/men_z135_uart.c+0−1
@@ -833,7 +833,6 @@ static int men_z135_probe(struct mcb_device *mdev, · 832 unmodified lines
833833 uart->port.iotype = UPIO_MEM;
834834 uart->port.ops = &men_z135_ops;
835835 uart->port.irq = mcb_get_irq(mdev);
836− uart->port.iotype = UPIO_MEM;
837836 uart->port.flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP;
838837 uart->port.line = line++;
839838 uart->port.dev = dev;
drivers/tty/serial/meson_uart.c+37−3
@@ -68,6 +68,7 @@ · 67 unmodified lines
6868 #define AML_UART_BAUD_MASK 0x7fffff
6969 #define AML_UART_BAUD_USE BIT(23)
7070 #define AML_UART_BAUD_XTAL BIT(24)
71+#define AML_UART_BAUD_XTAL_DIV2 BIT(27)
7172
7273 #define AML_UART_PORT_NUM 12
7374 #define AML_UART_PORT_OFFSET 6
@@ -80,6 +81,10 @@ static struct uart_driver meson_uart_driver; · 6 unmodified lines
8081
8182 static struct uart_port *meson_ports[AML_UART_PORT_NUM];
8283
84+struct meson_uart_data {
85+ bool has_xtal_div2;
86+};
87+
8388 static void meson_uart_set_mctrl(struct uart_port *port, unsigned int mctrl)
8489 {
8590 }
@@ -253,6 +258,14 @@ static const char *meson_uart_type(struct uart_port *port) · 167 unmodified lines
253258 return (port->type == PORT_MESON) ? "meson_uart" : NULL;
254259 }
255260
261+/*
262+ * This function is called only from probe() using a temporary io mapping
263+ * in order to perform a reset before setting up the device. Since the
264+ * temporarily mapped region was successfully requested, there can be no
265+ * console on this port at this time. Hence it is not necessary for this
266+ * function to acquire the port->lock. (Since there is no console on this
267+ * port at this time, the port->lock is not initialized yet.)
268+ */
256269 static void meson_uart_reset(struct uart_port *port)
257270 {
258271 u32 val;
@@ -267,9 +280,12 @@ static void meson_uart_reset(struct uart_port *port) · 8 unmodified lines
267280
268281 static int meson_uart_startup(struct uart_port *port)
269282 {
283+ unsigned long flags;
270284 u32 val;
271285 int ret = 0;
272286
287+ spin_lock_irqsave(&port->lock, flags);
288+
273289 val = readl(port->membase + AML_UART_CONTROL);
274290 val |= AML_UART_CLEAR_ERR;
275291 writel(val, port->membase + AML_UART_CONTROL);
@@ -285,6 +301,8 @@ static int meson_uart_startup(struct uart_port *port) · 9 unmodified lines
285301 val = (AML_UART_RECV_IRQ(1) | AML_UART_XMIT_IRQ(port->fifosize / 2));
286302 writel(val, port->membase + AML_UART_MISC);
287303
304+ spin_unlock_irqrestore(&port->lock, flags);
305+
288306 ret = request_irq(port->irq, meson_uart_interrupt, 0,
289307 port->name, port);
290308
@@ -293,16 +311,23 @@ static int meson_uart_startup(struct uart_port *port) · 2 unmodified lines
293311
294312 static void meson_uart_change_speed(struct uart_port *port, unsigned long baud)
295313 {
296− u32 val;
314+ const struct meson_uart_data *private_data = port->private_data;
315+ u32 val = 0;
297316
298317 while (!meson_uart_tx_empty(port))
299318 cpu_relax();
300319
301320 if (port->uartclk == 24000000) {
302− val = ((port->uartclk / 3) / baud) - 1;
321+ unsigned int xtal_div = 3;
322+
323+ if (private_data && private_data->has_xtal_div2) {
324+ xtal_div = 2;
325+ val |= AML_UART_BAUD_XTAL_DIV2;
326+ }
327+ val |= DIV_ROUND_CLOSEST(port->uartclk / xtal_div, baud) - 1;
303328 val |= AML_UART_BAUD_XTAL;
304329 } else {
305− val = ((port->uartclk * 10 / (baud * 4) + 5) / 10) - 1;
330+ val = DIV_ROUND_CLOSEST(port->uartclk / 4, baud) - 1;
306331 }
307332 val |= AML_UART_BAUD_USE;
308333 writel(val, port->membase + AML_UART_REG5);
@@ -749,6 +774,7 @@ static int meson_uart_probe(struct platform_device *pdev) · 440 unmodified lines
749774 port->x_char = 0;
750775 port->ops = &meson_uart_ops;
751776 port->fifosize = fifosize;
777+ port->private_data = (void *)device_get_match_data(&pdev->dev);
752778
753779 meson_ports[pdev->id] = port;
754780 platform_set_drvdata(pdev, port);
@@ -777,11 +803,19 @@ static int meson_uart_remove(struct platform_device *pdev) · 22 unmodified lines
777803 return 0;
778804 }
779805
806+static struct meson_uart_data s4_uart_data = {
807+ .has_xtal_div2 = true,
808+};
809+
780810 static const struct of_device_id meson_uart_dt_match[] = {
781811 { .compatible = "amlogic,meson6-uart" },
782812 { .compatible = "amlogic,meson8-uart" },
783813 { .compatible = "amlogic,meson8b-uart" },
784814 { .compatible = "amlogic,meson-gx-uart" },
815+ {
816+ .compatible = "amlogic,meson-s4-uart",
817+ .data = (void *)&s4_uart_data,
818+ },
785819 { /* sentinel */ },
786820 };
787821 MODULE_DEVICE_TABLE(of, meson_uart_dt_match);
drivers/tty/serial/mpc52xx_uart.c+2−3
@@ -38,6 +38,8 @@ · 37 unmodified lines
3838 #include <linux/delay.h>
3939 #include <linux/io.h>
4040 #include <linux/of.h>
41+#include <linux/of_address.h>
42+#include <linux/of_irq.h>
4143 #include <linux/of_platform.h>
4244 #include <linux/clk.h>
4345
@@ -754,9 +756,6 @@ static void mpc512x_psc_get_irq(struct uart_port *port, struct device_node *np) · 710 unmodified lines
754756 port->irqflags = IRQF_SHARED;
755757 port->irq = psc_fifoc_irq;
756758 }
757−#endif
758−
759−#ifdef CONFIG_PPC_MPC512x
760759
761760 #define PSC_5125(port) ((struct mpc5125_psc __iomem *)((port)->membase))
762761 #define FIFO_5125(port) ((struct mpc512x_psc_fifo __iomem *)(PSC_5125(port)+1))
drivers/tty/serial/msm_serial.c+5−0
@@ -1599,6 +1599,7 @@ static inline struct uart_port *msm_get_port_from_line(unsigned int line) · 1598 unmodified lines
15991599 static void __msm_console_write(struct uart_port *port, const char *s,
16001600 unsigned int count, bool is_uartdm)
16011601 {
1602+ unsigned long flags;
16021603 int i;
16031604 int num_newlines = 0;
16041605 bool replaced = false;
@@ -1616,6 +1617,8 @@ static void __msm_console_write(struct uart_port *port, const char *s, · 11 unmodified lines
16161617 num_newlines++;
16171618 count += num_newlines;
16181619
1620+ local_irq_save(flags);
1621+
16191622 if (port->sysrq)
16201623 locked = 0;
16211624 else if (oops_in_progress)
@@ -1661,6 +1664,8 @@ static void __msm_console_write(struct uart_port *port, const char *s, · 39 unmodified lines
16611664
16621665 if (locked)
16631666 spin_unlock(&port->lock);
1667+
1668+ local_irq_restore(flags);
16641669 }
16651670
16661671 static void msm_console_write(struct console *co, const char *s,
drivers/tty/serial/omap-serial.c+3−10
@@ -1336,18 +1336,11 @@ serial_omap_config_rs485(struct uart_port *port, struct serial_rs485 *rs485) · 1335 unmodified lines
13361336 up->ier = 0;
13371337 serial_out(up, UART_IER, 0);
13381338
1339− /* Clamp the delays to [0, 100ms] */
1340− rs485->delay_rts_before_send = min(rs485->delay_rts_before_send, 100U);
1341− rs485->delay_rts_after_send = min(rs485->delay_rts_after_send, 100U);
1342−
1343− /* store new config */
1344− port->rs485 = *rs485;
1345−
13461339 if (up->rts_gpiod) {
13471340 /* enable / disable rts */
1348− val = (port->rs485.flags & SER_RS485_ENABLED) ?
1341+ val = (rs485->flags & SER_RS485_ENABLED) ?
13491342 SER_RS485_RTS_AFTER_SEND : SER_RS485_RTS_ON_SEND;
1350− val = (port->rs485.flags & val) ? 1 : 0;
1343+ val = (rs485->flags & val) ? 1 : 0;
13511344 gpiod_set_value(up->rts_gpiod, val);
13521345 }
13531346
@@ -1358,7 +1351,7 @@ serial_omap_config_rs485(struct uart_port *port, struct serial_rs485 *rs485) · 4 unmodified lines
13581351 /* If RS-485 is disabled, make sure the THR interrupt is fired when
13591352 * TX FIFO is below the trigger level.
13601353 */
1361− if (!(port->rs485.flags & SER_RS485_ENABLED) &&
1354+ if (!(rs485->flags & SER_RS485_ENABLED) &&
13621355 (up->scr & OMAP_UART_SCR_TX_EMPTY)) {
13631356 up->scr &= ~OMAP_UART_SCR_TX_EMPTY;
13641357 serial_out(up, UART_OMAP_SCR, up->scr);
drivers/tty/serial/owl-uart.c+4−3
@@ -184,9 +184,6 @@ static void owl_uart_send_chars(struct uart_port *port) · 183 unmodified lines
184184 struct circ_buf *xmit = &port->state->xmit;
185185 unsigned int ch;
186186
187− if (uart_tx_stopped(port))
188− return;
189−
190187 if (port->x_char) {
191188 while (!(owl_uart_read(port, OWL_UART_STAT) & OWL_UART_STAT_TFFU))
192189 cpu_relax();
@@ -195,6 +192,9 @@ static void owl_uart_send_chars(struct uart_port *port) · 2 unmodified lines
195192 port->x_char = 0;
196193 }
197194
195+ if (uart_tx_stopped(port))
196+ return;
197+
198198 while (!(owl_uart_read(port, OWL_UART_STAT) & OWL_UART_STAT_TFFU)) {
199199 if (uart_circ_empty(xmit))
200200 break;
@@ -731,6 +731,7 @@ static int owl_uart_probe(struct platform_device *pdev) · 530 unmodified lines
731731 owl_port->port.uartclk = clk_get_rate(owl_port->clk);
732732 if (owl_port->port.uartclk == 0) {
733733 dev_err(&pdev->dev, "clock rate is zero\n");
734+ clk_disable_unprepare(owl_port->clk);
734735 return -EINVAL;
735736 }
736737 owl_port->port.flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP | UPF_LOW_LATENCY;
drivers/tty/serial/pch_uart.c+12−65
@@ -550,18 +550,6 @@ static u8 pch_uart_hal_get_modem(struct eg20t_port *priv) · 549 unmodified lines
550550 return (u8)msr;
551551 }
552552
553−static void pch_uart_hal_write(struct eg20t_port *priv,
554− const unsigned char *buf, int tx_size)
555−{
556− int i;
557− unsigned int thr;
558−
559− for (i = 0; i < tx_size;) {
560− thr = buf[i++];
561− iowrite8(thr, priv->membase + PCH_UART_THR);
562− }
563−}
564−
565553 static int pch_uart_hal_read(struct eg20t_port *priv, unsigned char *buf,
566554 int rx_size)
567555 {
@@ -624,22 +612,6 @@ static int push_rx(struct eg20t_port *priv, const unsigned char *buf, · 56 unmodified lines
624612 return 0;
625613 }
626614
627−static int pop_tx_x(struct eg20t_port *priv, unsigned char *buf)
628−{
629− int ret = 0;
630− struct uart_port *port = &priv->port;
631−
632− if (port->x_char) {
633− dev_dbg(priv->port.dev, "%s:X character send %02x (%lu)\n",
634− __func__, port->x_char, jiffies);
635− buf[0] = port->x_char;
636− port->x_char = 0;
637− ret = 1;
638− }
639−
640− return ret;
641−}
642−
643615 static int dma_push_rx(struct eg20t_port *priv, int size)
644616 {
645617 int room;
@@ -785,31 +757,6 @@ static void pch_dma_tx_complete(void *arg) · 139 unmodified lines
785757 pch_uart_hal_enable_interrupt(priv, PCH_UART_HAL_TX_INT);
786758 }
787759
788−static int pop_tx(struct eg20t_port *priv, int size)
789−{
790− int count = 0;
791− struct uart_port *port = &priv->port;
792− struct circ_buf *xmit = &port->state->xmit;
793−
794− if (uart_tx_stopped(port) || uart_circ_empty(xmit) || count >= size)
795− goto pop_tx_end;
796−
797− do {
798− int cnt_to_end =
799− CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE);
800− int sz = min(size - count, cnt_to_end);
801− pch_uart_hal_write(priv, &xmit->buf[xmit->tail], sz);
802− xmit->tail = (xmit->tail + sz) & (UART_XMIT_SIZE - 1);
803− count += sz;
804− } while (!uart_circ_empty(xmit) && count < size);
805−
806−pop_tx_end:
807− dev_dbg(priv->port.dev, "%d characters. Remained %d characters.(%lu)\n",
808− count, size - count, jiffies);
809−
810− return count;
811−}
812−
813760 static int handle_rx_to(struct eg20t_port *priv)
814761 {
815762 struct pch_uart_buffer *buf;
@@ -875,8 +822,6 @@ static unsigned int handle_tx(struct eg20t_port *priv) · 59 unmodified lines
875822 struct uart_port *port = &priv->port;
876823 struct circ_buf *xmit = &port->state->xmit;
877824 int fifo_size;
878− int tx_size;
879− int size;
880825 int tx_empty;
881826
882827 if (!priv->start_tx) {
@@ -889,19 +834,19 @@ static unsigned int handle_tx(struct eg20t_port *priv) · 6 unmodified lines
889834
890835 fifo_size = max(priv->fifo_size, 1);
891836 tx_empty = 1;
892− if (pop_tx_x(priv, xmit->buf)) {
893− pch_uart_hal_write(priv, xmit->buf, 1);
837+ if (port->x_char) {
838+ iowrite8(port->x_char, priv->membase + PCH_UART_THR);
894839 port->icount.tx++;
840+ port->x_char = 0;
895841 tx_empty = 0;
896842 fifo_size--;
897843 }
898− size = min(xmit->head - xmit->tail, fifo_size);
899− if (size < 0)
900− size = fifo_size;
901844
902− tx_size = pop_tx(priv, size);
903− if (tx_size > 0) {
904− port->icount.tx += tx_size;
845+ while (!uart_tx_stopped(port) && !uart_circ_empty(xmit) && fifo_size) {
846+ iowrite8(xmit->buf[xmit->tail], priv->membase + PCH_UART_THR);
847+ xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
848+ port->icount.tx++;
849+ fifo_size--;
905850 tx_empty = 0;
906851 }
907852
@@ -946,9 +891,11 @@ static unsigned int dma_handle_tx(struct eg20t_port *priv) · 38 unmodified lines
946891 }
947892
948893 fifo_size = max(priv->fifo_size, 1);
949− if (pop_tx_x(priv, xmit->buf)) {
950− pch_uart_hal_write(priv, xmit->buf, 1);
894+
895+ if (port->x_char) {
896+ iowrite8(port->x_char, priv->membase + PCH_UART_THR);
951897 port->icount.tx++;
898+ port->x_char = 0;
952899 fifo_size--;
953900 }
954901
drivers/tty/serial/pic32_uart.c+116−43
@@ -25,38 +25,114 @@ · 24 unmodified lines
2525 #include <linux/delay.h>
2626
2727 #include <asm/mach-pic32/pic32.h>
28−#include "pic32_uart.h"
2928
3029 /* UART name and device definitions */
3130 #define PIC32_DEV_NAME "pic32-uart"
3231 #define PIC32_MAX_UARTS 6
3332 #define PIC32_SDEV_NAME "ttyPIC"
3433
35−/* pic32_sport pointer for console use */
36−static struct pic32_sport *pic32_sports[PIC32_MAX_UARTS];
34+#define PIC32_UART_DFLT_BRATE 9600
35+#define PIC32_UART_TX_FIFO_DEPTH 8
36+#define PIC32_UART_RX_FIFO_DEPTH 8
37+
38+#define PIC32_UART_MODE 0x00
39+#define PIC32_UART_STA 0x10
40+#define PIC32_UART_TX 0x20
41+#define PIC32_UART_RX 0x30
42+#define PIC32_UART_BRG 0x40
43+
44+/* struct pic32_sport - pic32 serial port descriptor
45+ * @port: uart port descriptor
46+ * @idx: port index
47+ * @irq_fault: virtual fault interrupt number
48+ * @irq_fault_name: irq fault name
49+ * @irq_rx: virtual rx interrupt number
50+ * @irq_rx_name: irq rx name
51+ * @irq_tx: virtual tx interrupt number
52+ * @irq_tx_name: irq tx name
53+ * @cts_gpio: clear to send gpio
54+ * @dev: device descriptor
55+ **/
56+struct pic32_sport {
57+ struct uart_port port;
58+ int idx;
59+
60+ int irq_fault;
61+ const char *irq_fault_name;
62+ int irq_rx;
63+ const char *irq_rx_name;
64+ int irq_tx;
65+ const char *irq_tx_name;
66+ bool enable_tx_irq;
67+
68+ bool hw_flow_ctrl;
69+ int cts_gpio;
70+
71+ struct clk *clk;
72+
73+ struct device *dev;
74+};
3775
38−static inline void pic32_wait_deplete_txbuf(struct pic32_sport *sport)
76+static inline struct pic32_sport *to_pic32_sport(struct uart_port *port)
3977 {
40− /* wait for tx empty, otherwise chars will be lost or corrupted */
41− while (!(pic32_uart_readl(sport, PIC32_UART_STA) & PIC32_UART_STA_TRMT))
42− udelay(1);
78+ return container_of(port, struct pic32_sport, port);
4379 }
4480
45−static inline int pic32_enable_clock(struct pic32_sport *sport)
81+static inline void pic32_uart_writel(struct pic32_sport *sport,
82+ u32 reg, u32 val)
4683 {
47− int ret = clk_prepare_enable(sport->clk);
48−
49− if (ret)
50− return ret;
84+ __raw_writel(val, sport->port.membase + reg);
85+}
5186
52− sport->ref_clk++;
53− return 0;
87+static inline u32 pic32_uart_readl(struct pic32_sport *sport, u32 reg)
88+{
89+ return __raw_readl(sport->port.membase + reg);
5490 }
5591
56−static inline void pic32_disable_clock(struct pic32_sport *sport)
92+/* pic32 uart mode register bits */
93+#define PIC32_UART_MODE_ON BIT(15)
94+#define PIC32_UART_MODE_FRZ BIT(14)
95+#define PIC32_UART_MODE_SIDL BIT(13)
96+#define PIC32_UART_MODE_IREN BIT(12)
97+#define PIC32_UART_MODE_RTSMD BIT(11)
98+#define PIC32_UART_MODE_RESV1 BIT(10)
99+#define PIC32_UART_MODE_UEN1 BIT(9)
100+#define PIC32_UART_MODE_UEN0 BIT(8)
101+#define PIC32_UART_MODE_WAKE BIT(7)
102+#define PIC32_UART_MODE_LPBK BIT(6)
103+#define PIC32_UART_MODE_ABAUD BIT(5)
104+#define PIC32_UART_MODE_RXINV BIT(4)
105+#define PIC32_UART_MODE_BRGH BIT(3)
106+#define PIC32_UART_MODE_PDSEL1 BIT(2)
107+#define PIC32_UART_MODE_PDSEL0 BIT(1)
108+#define PIC32_UART_MODE_STSEL BIT(0)
109+
110+/* pic32 uart status register bits */
111+#define PIC32_UART_STA_UTXISEL1 BIT(15)
112+#define PIC32_UART_STA_UTXISEL0 BIT(14)
113+#define PIC32_UART_STA_UTXINV BIT(13)
114+#define PIC32_UART_STA_URXEN BIT(12)
115+#define PIC32_UART_STA_UTXBRK BIT(11)
116+#define PIC32_UART_STA_UTXEN BIT(10)
117+#define PIC32_UART_STA_UTXBF BIT(9)
118+#define PIC32_UART_STA_TRMT BIT(8)
119+#define PIC32_UART_STA_URXISEL1 BIT(7)
120+#define PIC32_UART_STA_URXISEL0 BIT(6)
121+#define PIC32_UART_STA_ADDEN BIT(5)
122+#define PIC32_UART_STA_RIDLE BIT(4)
123+#define PIC32_UART_STA_PERR BIT(3)
124+#define PIC32_UART_STA_FERR BIT(2)
125+#define PIC32_UART_STA_OERR BIT(1)
126+#define PIC32_UART_STA_URXDA BIT(0)
127+
128+/* pic32_sport pointer for console use */
129+static struct pic32_sport *pic32_sports[PIC32_MAX_UARTS];
130+
131+static inline void pic32_wait_deplete_txbuf(struct pic32_sport *sport)
57132 {
58− sport->ref_clk--;
59− clk_disable_unprepare(sport->clk);
133+ /* wait for tx empty, otherwise chars will be lost or corrupted */
134+ while (!(pic32_uart_readl(sport, PIC32_UART_STA) & PIC32_UART_STA_TRMT))
135+ udelay(1);
60136 }
61137
62138 /* serial core request to check if uart tx buffer is empty */
@@ -117,16 +193,16 @@ static unsigned int pic32_uart_get_mctrl(struct uart_port *port) · 54 unmodified lines
117193 */
118194 static inline void pic32_uart_irqtxen(struct pic32_sport *sport, u8 en)
119195 {
120− if (en && !tx_irq_enabled(sport)) {
196+ if (en && !sport->enable_tx_irq) {
121197 enable_irq(sport->irq_tx);
122− tx_irq_enabled(sport) = 1;
123− } else if (!en && tx_irq_enabled(sport)) {
198+ sport->enable_tx_irq = true;
199+ } else if (!en && sport->enable_tx_irq) {
124200 /* use disable_irq_nosync() and not disable_irq() to avoid self
125201 * imposed deadlock by not waiting for irq handler to end,
126202 * since this callback is called from interrupt context.
127203 */
128204 disable_irq_nosync(sport->irq_tx);
129− tx_irq_enabled(sport) = 0;
205+ sport->enable_tx_irq = false;
130206 }
131207 }
132208
@@ -395,7 +471,7 @@ static int pic32_uart_startup(struct uart_port *port) · 262 unmodified lines
395471
396472 local_irq_save(flags);
397473
398− ret = pic32_enable_clock(sport);
474+ ret = clk_prepare_enable(sport->clk);
399475 if (ret) {
400476 local_irq_restore(flags);
401477 goto out_done;
@@ -419,7 +495,7 @@ static int pic32_uart_startup(struct uart_port *port) · 17 unmodified lines
419495 * For each irq request_irq() is called with interrupt disabled.
420496 * And the irq is enabled as soon as we are ready to handle them.
421497 */
422− tx_irq_enabled(sport) = 0;
498+ sport->enable_tx_irq = false;
423499
424500 sport->irq_fault_name = kasprintf(GFP_KERNEL, "%s%d-fault",
425501 pic32_uart_type(port),
@@ -431,7 +507,7 @@ static int pic32_uart_startup(struct uart_port *port) · 5 unmodified lines
431507 }
432508 irq_set_status_flags(sport->irq_fault, IRQ_NOAUTOEN);
433509 ret = request_irq(sport->irq_fault, pic32_uart_fault_interrupt,
434− sport->irqflags_fault, sport->irq_fault_name, port);
510+ IRQF_NO_THREAD, sport->irq_fault_name, port);
435511 if (ret) {
436512 dev_err(port->dev, "%s: request irq(%d) err! ret:%d name:%s\n",
437513 __func__, sport->irq_fault, ret,
@@ -449,7 +525,7 @@ static int pic32_uart_startup(struct uart_port *port) · 11 unmodified lines
449525 }
450526 irq_set_status_flags(sport->irq_rx, IRQ_NOAUTOEN);
451527 ret = request_irq(sport->irq_rx, pic32_uart_rx_interrupt,
452− sport->irqflags_rx, sport->irq_rx_name, port);
528+ IRQF_NO_THREAD, sport->irq_rx_name, port);
453529 if (ret) {
454530 dev_err(port->dev, "%s: request irq(%d) err! ret:%d name:%s\n",
455531 __func__, sport->irq_rx, ret,
@@ -467,7 +543,7 @@ static int pic32_uart_startup(struct uart_port *port) · 11 unmodified lines
467543 }
468544 irq_set_status_flags(sport->irq_tx, IRQ_NOAUTOEN);
469545 ret = request_irq(sport->irq_tx, pic32_uart_tx_interrupt,
470− sport->irqflags_tx, sport->irq_tx_name, port);
546+ IRQF_NO_THREAD, sport->irq_tx_name, port);
471547 if (ret) {
472548 dev_err(port->dev, "%s: request irq(%d) err! ret:%d name:%s\n",
473549 __func__, sport->irq_tx, ret,
@@ -488,19 +564,21 @@ static int pic32_uart_startup(struct uart_port *port) · 14 unmodified lines
488564 /* enable all interrupts and eanable uart */
489565 pic32_uart_en_and_unmask(port);
490566
567+ local_irq_restore(flags);
568+
491569 enable_irq(sport->irq_rx);
492570
493571 return 0;
494572
495573 out_t:
496− kfree(sport->irq_tx_name);
497574 free_irq(sport->irq_tx, port);
575+ kfree(sport->irq_tx_name);
498576 out_r:
499− kfree(sport->irq_rx_name);
500577 free_irq(sport->irq_rx, port);
578+ kfree(sport->irq_rx_name);
501579 out_f:
502− kfree(sport->irq_fault_name);
503580 free_irq(sport->irq_fault, port);
581+ kfree(sport->irq_fault_name);
504582 out_done:
505583 return ret;
506584 }
@@ -515,12 +593,15 @@ static void pic32_uart_shutdown(struct uart_port *port) · 8 unmodified lines
515593 spin_lock_irqsave(&port->lock, flags);
516594 pic32_uart_dsbl_and_mask(port);
517595 spin_unlock_irqrestore(&port->lock, flags);
518− pic32_disable_clock(sport);
596+ clk_disable_unprepare(sport->clk);
519597
520598 /* free all 3 interrupts for this UART */
521599 free_irq(sport->irq_fault, port);
600+ kfree(sport->irq_fault_name);
522601 free_irq(sport->irq_tx, port);
602+ kfree(sport->irq_tx_name);
523603 free_irq(sport->irq_rx, port);
604+ kfree(sport->irq_rx_name);
524605 }
525606
526607 /* serial core request to change current uart setting */
@@ -712,10 +793,9 @@ static void pic32_console_write(struct console *co, const char *s, · 185 unmodified lines
712793 unsigned int count)
713794 {
714795 struct pic32_sport *sport = pic32_sports[co->index];
715− struct uart_port *port = pic32_get_port(sport);
716796
717797 /* call uart helper to deal with \r\n */
718− uart_console_write(port, s, count, pic32_console_putchar);
798+ uart_console_write(&sport->port, s, count, pic32_console_putchar);
719799 }
720800
721801 /* console core request to setup given console, find matching uart
@@ -724,7 +804,6 @@ static void pic32_console_write(struct console *co, const char *s, · 2 unmodified lines
724804 static int pic32_console_setup(struct console *co, char *options)
725805 {
726806 struct pic32_sport *sport;
727− struct uart_port *port = NULL;
728807 int baud = 115200;
729808 int bits = 8;
730809 int parity = 'n';
@@ -737,16 +816,15 @@ static int pic32_console_setup(struct console *co, char *options) · 6 unmodified lines
737816 sport = pic32_sports[co->index];
738817 if (!sport)
739818 return -ENODEV;
740− port = pic32_get_port(sport);
741819
742− ret = pic32_enable_clock(sport);
820+ ret = clk_prepare_enable(sport->clk);
743821 if (ret)
744822 return ret;
745823
746824 if (options)
747825 uart_parse_options(options, &baud, &parity, &bits, &flow);
748826
749− return uart_set_options(port, co, baud, parity, bits, flow);
827+ return uart_set_options(&sport->port, co, baud, parity, bits, flow);
750828 }
751829
752830 static struct uart_driver pic32_uart_driver;
@@ -816,13 +894,9 @@ static int pic32_uart_probe(struct platform_device *pdev) · 63 unmodified lines
816894
817895 sport->idx = uart_idx;
818896 sport->irq_fault = irq_of_parse_and_map(np, 0);
819− sport->irqflags_fault = IRQF_NO_THREAD;
820897 sport->irq_rx = irq_of_parse_and_map(np, 1);
821− sport->irqflags_rx = IRQF_NO_THREAD;
822898 sport->irq_tx = irq_of_parse_and_map(np, 2);
823− sport->irqflags_tx = IRQF_NO_THREAD;
824899 sport->clk = devm_clk_get(&pdev->dev, NULL);
825− sport->cts_gpio = -EINVAL;
826900 sport->dev = &pdev->dev;
827901
828902 /* Hardware flow control: gpios
@@ -850,7 +924,6 @@ static int pic32_uart_probe(struct platform_device *pdev) · 21 unmodified lines
850924
851925 pic32_sports[uart_idx] = sport;
852926 port = &sport->port;
853− memset(port, 0, sizeof(*port));
854927 port->iotype = UPIO_MEM;
855928 port->mapbase = res_mem->start;
856929 port->ops = &pic32_uart_ops;
@@ -872,7 +945,7 @@ static int pic32_uart_probe(struct platform_device *pdev) · 15 unmodified lines
872945 /* The peripheral clock has been enabled by console_setup,
873946 * so disable it till the port is used.
874947 */
875− pic32_disable_clock(sport);
948+ clk_disable_unprepare(sport->clk);
876949 }
877950 #endif
878951
@@ -893,7 +966,7 @@ static int pic32_uart_remove(struct platform_device *pdev) · 14 unmodified lines
893966 struct pic32_sport *sport = to_pic32_sport(port);
894967
895968 uart_remove_one_port(&pic32_uart_driver, port);
896− pic32_disable_clock(sport);
969+ clk_disable_unprepare(sport->clk);
897970 platform_set_drvdata(pdev, NULL);
898971 pic32_sports[sport->idx] = NULL;
899972
drivers/tty/serial/pic32_uart.h+0−125
@@ -1,125 +0,0 @@
1−/* SPDX-License-Identifier: GPL-2.0+ */
2−/*
3− * PIC32 Integrated Serial Driver.
4− *
5− * Copyright (C) 2015 Microchip Technology, Inc.
6− *
7− * Authors:
8− * Sorin-Andrei Pistirica <andrei.pistirica@microchip.com>
9− */
10−#ifndef __DT_PIC32_UART_H__
11−#define __DT_PIC32_UART_H__
12−
13−#define PIC32_UART_DFLT_BRATE (9600)
14−#define PIC32_UART_TX_FIFO_DEPTH (8)
15−#define PIC32_UART_RX_FIFO_DEPTH (8)
16−
17−#define PIC32_UART_MODE 0x00
18−#define PIC32_UART_STA 0x10
19−#define PIC32_UART_TX 0x20
20−#define PIC32_UART_RX 0x30
21−#define PIC32_UART_BRG 0x40
22−
23−struct pic32_console_opt {
24− int baud;
25− int parity;
26− int bits;
27− int flow;
28−};
29−
30−/* struct pic32_sport - pic32 serial port descriptor
31− * @port: uart port descriptor
32− * @idx: port index
33− * @irq_fault: virtual fault interrupt number
34− * @irqflags_fault: flags related to fault irq
35− * @irq_fault_name: irq fault name
36− * @irq_rx: virtual rx interrupt number
37− * @irqflags_rx: flags related to rx irq
38− * @irq_rx_name: irq rx name
39− * @irq_tx: virtual tx interrupt number
40− * @irqflags_tx: : flags related to tx irq
41− * @irq_tx_name: irq tx name
42− * @cts_gpio: clear to send gpio
43− * @dev: device descriptor
44− **/
45−struct pic32_sport {
46− struct uart_port port;
47− struct pic32_console_opt opt;
48− int idx;
49−
50− int irq_fault;
51− int irqflags_fault;
52− const char *irq_fault_name;
53− int irq_rx;
54− int irqflags_rx;
55− const char *irq_rx_name;
56− int irq_tx;
57− int irqflags_tx;
58− const char *irq_tx_name;
59− u8 enable_tx_irq;
60−
61− bool hw_flow_ctrl;
62− int cts_gpio;
63−
64− int ref_clk;
65− struct clk *clk;
66−
67− struct device *dev;
68−};
69−#define to_pic32_sport(c) container_of(c, struct pic32_sport, port)
70−#define pic32_get_port(sport) (&sport->port)
71−#define pic32_get_opt(sport) (&sport->opt)
72−#define tx_irq_enabled(sport) (sport->enable_tx_irq)
73−
74−static inline void pic32_uart_writel(struct pic32_sport *sport,
75− u32 reg, u32 val)
76−{
77− struct uart_port *port = pic32_get_port(sport);
78−
79− __raw_writel(val, port->membase + reg);
80−}
81−
82−static inline u32 pic32_uart_readl(struct pic32_sport *sport, u32 reg)
83−{
84− struct uart_port *port = pic32_get_port(sport);
85−
86− return __raw_readl(port->membase + reg);
87−}
88−
89−/* pic32 uart mode register bits */
90−#define PIC32_UART_MODE_ON BIT(15)
91−#define PIC32_UART_MODE_FRZ BIT(14)
92−#define PIC32_UART_MODE_SIDL BIT(13)
93−#define PIC32_UART_MODE_IREN BIT(12)
94−#define PIC32_UART_MODE_RTSMD BIT(11)
95−#define PIC32_UART_MODE_RESV1 BIT(10)
96−#define PIC32_UART_MODE_UEN1 BIT(9)
97−#define PIC32_UART_MODE_UEN0 BIT(8)
98−#define PIC32_UART_MODE_WAKE BIT(7)
99−#define PIC32_UART_MODE_LPBK BIT(6)
100−#define PIC32_UART_MODE_ABAUD BIT(5)
101−#define PIC32_UART_MODE_RXINV BIT(4)
102−#define PIC32_UART_MODE_BRGH BIT(3)
103−#define PIC32_UART_MODE_PDSEL1 BIT(2)
104−#define PIC32_UART_MODE_PDSEL0 BIT(1)
105−#define PIC32_UART_MODE_STSEL BIT(0)
106−
107−/* pic32 uart status register bits */
108−#define PIC32_UART_STA_UTXISEL1 BIT(15)
109−#define PIC32_UART_STA_UTXISEL0 BIT(14)
110−#define PIC32_UART_STA_UTXINV BIT(13)
111−#define PIC32_UART_STA_URXEN BIT(12)
112−#define PIC32_UART_STA_UTXBRK BIT(11)
113−#define PIC32_UART_STA_UTXEN BIT(10)
114−#define PIC32_UART_STA_UTXBF BIT(9)
115−#define PIC32_UART_STA_TRMT BIT(8)
116−#define PIC32_UART_STA_URXISEL1 BIT(7)
117−#define PIC32_UART_STA_URXISEL0 BIT(6)
118−#define PIC32_UART_STA_ADDEN BIT(5)
119−#define PIC32_UART_STA_RIDLE BIT(4)
120−#define PIC32_UART_STA_PERR BIT(3)
121−#define PIC32_UART_STA_FERR BIT(2)
122−#define PIC32_UART_STA_OERR BIT(1)
123−#define PIC32_UART_STA_URXDA BIT(0)
124−
125−#endif /* __DT_PIC32_UART_H__ */
drivers/tty/serial/pmac_zilog.c+2−67
@@ -24,7 +24,6 @@ · 23 unmodified lines
2424 */
2525
2626 #undef DEBUG
27−#undef DEBUG_HARD
2827 #undef USE_CTRL_O_SYSRQ
2928
3029 #include <linux/module.h>
@@ -51,7 +50,6 @@ · 20 unmodified lines
5150 #include <asm/irq.h>
5251
5352 #ifdef CONFIG_PPC_PMAC
54−#include <asm/prom.h>
5553 #include <asm/machdep.h>
5654 #include <asm/pmac_feature.h>
5755 #include <asm/dbdma.h>
@@ -66,10 +64,6 @@ · 8 unmodified lines
6664
6765 #include "pmac_zilog.h"
6866
69−/* Not yet implemented */
70−#undef HAS_DBDMA
71−
72−static char version[] __initdata = "pmac_zilog: 0.6 (Benjamin Herrenschmidt <benh@kernel.crashing.org>)";
7367 MODULE_AUTHOR("Benjamin Herrenschmidt <benh@kernel.crashing.org>");
7468 MODULE_DESCRIPTION("Driver for the Mac and PowerMac serial ports.");
7569 MODULE_LICENSE("GPL");
@@ -446,9 +440,6 @@ static irqreturn_t pmz_interrupt(int irq, void *dev_id) · 370 unmodified lines
446440 spin_lock(&uap_a->port.lock);
447441 r3 = read_zsreg(uap_a, R3);
448442
449−#ifdef DEBUG_HARD
450− pmz_debug("irq, r3: %x\n", r3);
451−#endif
452443 /* Channel A */
453444 push = false;
454445 if (r3 & (CHAEXT | CHATxIP | CHARxIP)) {
@@ -613,8 +604,6 @@ static void pmz_start_tx(struct uart_port *port) · 158 unmodified lines
613604 struct uart_pmac_port *uap = to_pmz(port);
614605 unsigned char status;
615606
616− pmz_debug("pmz: start_tx()\n");
617−
618607 uap->flags |= PMACZILOG_FLAG_TX_ACTIVE;
619608 uap->flags &= ~PMACZILOG_FLAG_TX_STOPPED;
620609
@@ -636,7 +625,7 @@ static void pmz_start_tx(struct uart_port *port) · 15 unmodified lines
636625 struct circ_buf *xmit = &port->state->xmit;
637626
638627 if (uart_circ_empty(xmit))
639− goto out;
628+ return;
640629 write_zsdata(uap, xmit->buf[xmit->tail]);
641630 zssync(uap);
642631 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
@@ -645,8 +634,6 @@ static void pmz_start_tx(struct uart_port *port) · 2 unmodified lines
645634 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
646635 uart_write_wakeup(&uap->port);
647636 }
648− out:
649− pmz_debug("pmz: start_tx() done.\n");
650637 }
651638
652639 /*
@@ -659,13 +646,9 @@ static void pmz_stop_rx(struct uart_port *port) · 6 unmodified lines
659646 {
660647 struct uart_pmac_port *uap = to_pmz(port);
661648
662− pmz_debug("pmz: stop_rx()()\n");
663−
664649 /* Disable all RX interrupts. */
665650 uap->curregs[R1] &= ~RxINT_MASK;
666651 pmz_maybe_update_regs(uap);
667−
668− pmz_debug("pmz: stop_rx() done.\n");
669652 }
670653
671654 /*
@@ -910,8 +893,6 @@ static int pmz_startup(struct uart_port *port) · 238 unmodified lines
910893 unsigned long flags;
911894 int pwr_delay = 0;
912895
913− pmz_debug("pmz: startup()\n");
914−
915896 uap->flags |= PMACZILOG_FLAG_IS_OPEN;
916897
917898 /* A console is never powered down. Else, power up and
@@ -947,8 +928,6 @@ static int pmz_startup(struct uart_port *port) · 29 unmodified lines
947928 pmz_interrupt_control(uap, 1);
948929 spin_unlock_irqrestore(&port->lock, flags);
949930
950− pmz_debug("pmz: startup() done.\n");
951−
952931 return 0;
953932 }
954933
@@ -957,8 +936,6 @@ static void pmz_shutdown(struct uart_port *port) · 2 unmodified lines
957936 struct uart_pmac_port *uap = to_pmz(port);
958937 unsigned long flags;
959938
960− pmz_debug("pmz: shutdown()\n");
961−
962939 spin_lock_irqsave(&port->lock, flags);
963940
964941 /* Disable interrupt requests for the channel */
@@ -987,8 +964,6 @@ static void pmz_shutdown(struct uart_port *port) · 22 unmodified lines
987964 pmz_set_scc_power(uap, 0); /* Shut the chip down */
988965
989966 spin_unlock_irqrestore(&port->lock, flags);
990−
991− pmz_debug("pmz: shutdown() done.\n");
992967 }
993968
994969 /* Shared by TTY driver and serial console setup. The port lock is held
@@ -1233,10 +1208,6 @@ static void __pmz_set_termios(struct uart_port *port, struct ktermios *termios, · 238 unmodified lines
12331208 struct uart_pmac_port *uap = to_pmz(port);
12341209 unsigned long baud;
12351210
1236− pmz_debug("pmz: set_termios()\n");
1237−
1238− memcpy(&uap->termios_cache, termios, sizeof(struct ktermios));
1239−
12401211 /* XXX Check which revs of machines actually allow 1 and 4Mb speeds
12411212 * on the IR dongle. Note that the IRTTY driver currently doesn't know
12421213 * about the FIR mode and high speed modes. So these are unused. For
@@ -1270,8 +1241,6 @@ static void __pmz_set_termios(struct uart_port *port, struct ktermios *termios, · 27 unmodified lines
12701241 pmz_maybe_update_regs(uap);
12711242 }
12721243 uart_update_timeout(port, termios->c_cflag, baud);
1273−
1274− pmz_debug("pmz: set_termios() done.\n");
12751244 }
12761245
12771246 /* The port lock is not held. */
@@ -1400,7 +1369,7 @@ static int __init pmz_init_port(struct uart_pmac_port *uap) · 122 unmodified lines
14001369 char name[1];
14011370 } *slots;
14021371 int len;
1403− struct resource r_ports, r_rxdma, r_txdma;
1372+ struct resource r_ports;
14041373
14051374 /*
14061375 * Request & map chip registers
@@ -1412,35 +1381,6 @@ static int __init pmz_init_port(struct uart_pmac_port *uap) · 5 unmodified lines
14121381
14131382 uap->control_reg = uap->port.membase;
14141383 uap->data_reg = uap->control_reg + 0x10;
1415−
1416− /*
1417− * Request & map DBDMA registers
1418− */
1419−#ifdef HAS_DBDMA
1420− if (of_address_to_resource(np, 1, &r_txdma) == 0 &&
1421− of_address_to_resource(np, 2, &r_rxdma) == 0)
1422− uap->flags |= PMACZILOG_FLAG_HAS_DMA;
1423−#else
1424− memset(&r_txdma, 0, sizeof(struct resource));
1425− memset(&r_rxdma, 0, sizeof(struct resource));
1426−#endif
1427− if (ZS_HAS_DMA(uap)) {
1428− uap->tx_dma_regs = ioremap(r_txdma.start, 0x100);
1429− if (uap->tx_dma_regs == NULL) {
1430− uap->flags &= ~PMACZILOG_FLAG_HAS_DMA;
1431− goto no_dma;
1432− }
1433− uap->rx_dma_regs = ioremap(r_rxdma.start, 0x100);
1434− if (uap->rx_dma_regs == NULL) {
1435− iounmap(uap->tx_dma_regs);
1436− uap->tx_dma_regs = NULL;
1437− uap->flags &= ~PMACZILOG_FLAG_HAS_DMA;
1438− goto no_dma;
1439− }
1440− uap->tx_dma_irq = irq_of_parse_and_map(np, 1);
1441− uap->rx_dma_irq = irq_of_parse_and_map(np, 2);
1442− }
1443−no_dma:
14441384
14451385 /*
14461386 * Detect port type
@@ -1506,8 +1446,6 @@ no_dma: · 59 unmodified lines
15061446 of_device_is_compatible(np->parent->parent, "gatwick")) {
15071447 /* IRQs on gatwick are offset by 64 */
15081448 uap->port.irq = irq_create_mapping(NULL, 64 + 15);
1509− uap->tx_dma_irq = irq_create_mapping(NULL, 64 + 4);
1510− uap->rx_dma_irq = irq_create_mapping(NULL, 64 + 5);
15111449 }
15121450
15131451 /* Setup some valid baud rate information in the register
@@ -1527,8 +1465,6 @@ static void pmz_dispose_port(struct uart_pmac_port *uap) · 13 unmodified lines
15271465 struct device_node *np;
15281466
15291467 np = uap->node;
1530− iounmap(uap->rx_dma_regs);
1531− iounmap(uap->tx_dma_regs);
15321468 iounmap(uap->control_reg);
15331469 uap->node = NULL;
15341470 of_node_put(np);
@@ -1875,7 +1811,6 @@ static struct platform_driver pmz_driver = { · 340 unmodified lines
18751811 static int __init init_pmz(void)
18761812 {
18771813 int rc, i;
1878− printk(KERN_INFO "%s\n", version);
18791814
18801815 /*
18811816 * First, we need to do a direct OF-based probe pass. We
drivers/tty/serial/pmac_zilog.h+0−11
@@ -43,7 +43,6 @@ struct uart_pmac_port { · 42 unmodified lines
4343 #define PMACZILOG_FLAG_TX_ACTIVE 0x00000040
4444 #define PMACZILOG_FLAG_IS_IRDA 0x00000100
4545 #define PMACZILOG_FLAG_IS_INTMODEM 0x00000200
46−#define PMACZILOG_FLAG_HAS_DMA 0x00000400
4746 #define PMACZILOG_FLAG_RSRC_REQUESTED 0x00000800
4847 #define PMACZILOG_FLAG_IS_OPEN 0x00002000
4948 #define PMACZILOG_FLAG_IS_EXTCLK 0x00008000
@@ -55,16 +54,7 @@ struct uart_pmac_port { · 5 unmodified lines
5554 volatile u8 __iomem *control_reg;
5655 volatile u8 __iomem *data_reg;
5756
58−#ifdef CONFIG_PPC_PMAC
59− unsigned int tx_dma_irq;
60− unsigned int rx_dma_irq;
61− volatile struct dbdma_regs __iomem *tx_dma_regs;
62− volatile struct dbdma_regs __iomem *rx_dma_regs;
63−#endif
64−
6557 unsigned char irq_name[8];
66−
67− struct ktermios termios_cache;
6858 };
6959
7060 #define to_pmz(p) ((struct uart_pmac_port *)(p))
@@ -377,7 +367,6 @@ static inline void zssync(struct uart_pmac_port *port) · 306 unmodified lines
377367 #define ZS_WANTS_MODEM_STATUS(UP) ((UP)->flags & PMACZILOG_FLAG_MODEM_STATUS)
378368 #define ZS_IS_IRDA(UP) ((UP)->flags & PMACZILOG_FLAG_IS_IRDA)
379369 #define ZS_IS_INTMODEM(UP) ((UP)->flags & PMACZILOG_FLAG_IS_INTMODEM)
380−#define ZS_HAS_DMA(UP) ((UP)->flags & PMACZILOG_FLAG_HAS_DMA)
381370 #define ZS_IS_OPEN(UP) ((UP)->flags & PMACZILOG_FLAG_IS_OPEN)
382371 #define ZS_IS_EXTCLK(UP) ((UP)->flags & PMACZILOG_FLAG_IS_EXTCLK)
383372
drivers/tty/serial/qcom_geni_serial.c+37−21
@@ -149,12 +149,6 @@ static unsigned int qcom_geni_serial_tx_empty(struct uart_port *port); · 148 unmodified lines
149149 static void qcom_geni_serial_stop_rx(struct uart_port *uport);
150150 static void qcom_geni_serial_handle_rx(struct uart_port *uport, bool drop);
151151
152−static const unsigned long root_freq[] = {7372800, 14745600, 19200000, 29491200,
153− 32000000, 48000000, 51200000, 64000000,
154− 80000000, 96000000, 100000000,
155− 102400000, 112000000, 120000000,
156− 128000000};
157−
158152 #define to_dev_port(ptr, member) \
159153 container_of(ptr, struct qcom_geni_serial_port, member)
160154
@@ -507,7 +501,7 @@ static void qcom_geni_serial_console_write(struct console *co, const char *s, · 346 unmodified lines
507501 */
508502 qcom_geni_serial_poll_tx_done(uport);
509503
510− if (uart_circ_chars_pending(&uport->state->xmit)) {
504+ if (!uart_circ_empty(&uport->state->xmit)) {
511505 irq_en = readl(uport->membase + SE_GENI_M_IRQ_EN);
512506 writel(irq_en | M_TX_FIFO_WATERMARK_EN,
513507 uport->membase + SE_GENI_M_IRQ_EN);
@@ -946,25 +940,43 @@ static int qcom_geni_serial_startup(struct uart_port *uport) · 432 unmodified lines
946940 return 0;
947941 }
948942
949−static unsigned long get_clk_cfg(unsigned long clk_freq)
950−{
951− int i;
952−
953− for (i = 0; i < ARRAY_SIZE(root_freq); i++) {
954− if (!(root_freq[i] % clk_freq))
955− return root_freq[i];
956− }
957− return 0;
958−}
959−
960−static unsigned long get_clk_div_rate(unsigned int baud,
943+static unsigned long get_clk_div_rate(struct clk *clk, unsigned int baud,
961944 unsigned int sampling_rate, unsigned int *clk_div)
962945 {
963946 unsigned long ser_clk;
964947 unsigned long desired_clk;
948+ unsigned long freq, prev;
949+ unsigned long div, maxdiv;
950+ int64_t mult;
965951
966952 desired_clk = baud * sampling_rate;
967− ser_clk = get_clk_cfg(desired_clk);
953+ if (!desired_clk) {
954+ pr_err("%s: Invalid frequency\n", __func__);
955+ return 0;
956+ }
957+
958+ maxdiv = CLK_DIV_MSK >> CLK_DIV_SHFT;
959+ prev = 0;
960+
961+ for (div = 1; div <= maxdiv; div++) {
962+ mult = div * desired_clk;
963+ if (mult > ULONG_MAX)
964+ break;
965+
966+ freq = clk_round_rate(clk, (unsigned long)mult);
967+ if (!(freq % desired_clk)) {
968+ ser_clk = freq;
969+ break;
970+ }
971+
972+ if (!prev)
973+ ser_clk = freq;
974+ else if (prev == freq)
975+ break;
976+
977+ prev = freq;
978+ }
979+
968980 if (!ser_clk) {
969981 pr_err("%s: Can't find matching DFS entry for baud %d\n",
970982 __func__, baud);
@@ -972,6 +984,9 @@ static unsigned long get_clk_div_rate(unsigned int baud, · 1 unmodified line
972984 }
973985
974986 *clk_div = ser_clk / desired_clk;
987+ if (!(*clk_div))
988+ *clk_div = 1;
989+
975990 return ser_clk;
976991 }
977992
@@ -1003,7 +1018,8 @@ static void qcom_geni_serial_set_termios(struct uart_port *uport, · 25 unmodified lines
10031018 if (ver >= QUP_SE_VERSION_2_5)
10041019 sampling_rate /= 2;
10051020
1006− clk_rate = get_clk_div_rate(baud, sampling_rate, &clk_div);
1021+ clk_rate = get_clk_div_rate(port->se.clk, baud,
1022+ sampling_rate, &clk_div);
10071023 if (!clk_rate)
10081024 goto out_restart_rx;
10091025
drivers/tty/serial/rda-uart.c+2−0
@@ -262,6 +262,8 @@ static void rda_uart_set_termios(struct uart_port *port, · 261 unmodified lines
262262 fallthrough;
263263 case CS7:
264264 ctrl &= ~RDA_UART_DBITS_8;
265+ termios->c_cflag &= ~CSIZE;
266+ termios->c_cflag |= CS7;
265267 break;
266268 default:
267269 ctrl |= RDA_UART_DBITS_8;
drivers/tty/serial/sa1100.c+2−2
@@ -446,6 +446,8 @@ sa1100_set_termios(struct uart_port *port, struct ktermios *termios, · 445 unmodified lines
446446 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/16);
447447 quot = uart_get_divisor(port, baud);
448448
449+ del_timer_sync(&sport->timer);
450+
449451 spin_lock_irqsave(&sport->port.lock, flags);
450452
451453 sport->port.read_status_mask &= UTSR0_TO_SM(UTSR0_TFS);
@@ -476,8 +478,6 @@ sa1100_set_termios(struct uart_port *port, struct ktermios *termios, · 24 unmodified lines
476478 UTSR1_TO_SM(UTSR1_ROR);
477479 }
478480
479− del_timer_sync(&sport->timer);
480−
481481 /*
482482 * Update the per-port timeout.
483483 */
drivers/tty/serial/samsung_tty.c+13−0
@@ -2480,12 +2480,24 @@ s3c24xx_serial_console_write(struct console *co, const char *s, · 2479 unmodified lines
24802480 unsigned int count)
24812481 {
24822482 unsigned int ucon = rd_regl(cons_uart, S3C2410_UCON);
2483+ unsigned long flags;
2484+ bool locked = true;
24832485
24842486 /* not possible to xmit on unconfigured port */
24852487 if (!s3c24xx_port_configured(ucon))
24862488 return;
24872489
2490+ if (cons_uart->sysrq)
2491+ locked = false;
2492+ else if (oops_in_progress)
2493+ locked = spin_trylock_irqsave(&cons_uart->lock, flags);
2494+ else
2495+ spin_lock_irqsave(&cons_uart->lock, flags);
2496+
24882497 uart_console_write(cons_uart, s, count, s3c24xx_serial_console_putchar);
2498+
2499+ if (locked)
2500+ spin_unlock_irqrestore(&cons_uart->lock, flags);
24892501 }
24902502
24912503 /* Shouldn't be __init, as it can be instantiated from other module */
@@ -2814,6 +2826,7 @@ static const struct s3c24xx_serial_drv_data s5l_serial_drv_data = { · 322 unmodified lines
28142826 .num_clks = 1,
28152827 .clksel_mask = 0,
28162828 .clksel_shift = 0,
2829+ .ucon_mask = APPLE_S5L_UCON_MASK,
28172830 },
28182831 .def_cfg = {
28192832 .ucon = APPLE_S5L_UCON_DEFAULT,
drivers/tty/serial/sc16is7xx.c+0−10
@@ -1134,16 +1134,6 @@ static int sc16is7xx_config_rs485(struct uart_port *port, · 1133 unmodified lines
11341134 struct sc16is7xx_one *one = to_sc16is7xx_one(port, port);
11351135
11361136 if (rs485->flags & SER_RS485_ENABLED) {
1137− bool rts_during_rx, rts_during_tx;
1138−
1139− rts_during_rx = rs485->flags & SER_RS485_RTS_AFTER_SEND;
1140− rts_during_tx = rs485->flags & SER_RS485_RTS_ON_SEND;
1141−
1142− if (rts_during_rx == rts_during_tx)
1143− dev_err(port->dev,
1144− "unsupported RTS signalling on_send:%d after_send:%d - exactly one of RS485 RTS flags should be set\n",
1145− rts_during_tx, rts_during_rx);
1146−
11471137 /*
11481138 * RTS signal is handled by HW, it's timing can't be influenced.
11491139 * However, it's sometimes useful to delay TX even without RTS
drivers/tty/serial/serial_core.c+69−20
@@ -24,6 +24,7 @@ · 23 unmodified lines
2424 #include <linux/sysrq.h>
2525 #include <linux/delay.h>
2626 #include <linux/mutex.h>
27+#include <linux/math64.h>
2728 #include <linux/security.h>
2829
2930 #include <linux/irq.h>
@@ -42,6 +43,11 @@ static struct lock_class_key port_lock_key; · 12 unmodified lines
4243
4344 #define HIGH_BITS_OFFSET ((sizeof(long)-sizeof(int))*8)
4445
46+/*
47+ * Max time with active RTS before/after data is sent.
48+ */
49+#define RS485_MAX_RTS_DELAY 100 /* msecs */
50+
4551 static void uart_change_speed(struct tty_struct *tty, struct uart_state *state,
4652 struct ktermios *old_termios);
4753 static void uart_wait_until_sent(struct tty_struct *tty, int timeout);
@@ -333,15 +339,18 @@ void · 285 unmodified lines
333339 uart_update_timeout(struct uart_port *port, unsigned int cflag,
334340 unsigned int baud)
335341 {
336− unsigned int size;
342+ unsigned int size = tty_get_frame_size(cflag);
343+ u64 frame_time;
337344
338− size = tty_get_frame_size(cflag) * port->fifosize;
345+ frame_time = (u64)size * NSEC_PER_SEC;
346+ size *= port->fifosize;
339347
340348 /*
341349 * Figure the timeout to send the above number of bits.
342350 * Add .02 seconds of slop
343351 */
344352 port->timeout = (HZ * size) / baud + HZ/50;
353+ port->frame_time = DIV64_U64_ROUND_UP(frame_time, baud);
345354 }
346355 EXPORT_SYMBOL(uart_update_timeout);
347356
@@ -1296,8 +1305,36 @@ static int uart_set_rs485_config(struct uart_port *port, · 948 unmodified lines
12961305 if (copy_from_user(&rs485, rs485_user, sizeof(*rs485_user)))
12971306 return -EFAULT;
12981307
1308+ /* pick sane settings if the user hasn't */
1309+ if (!(rs485.flags & SER_RS485_RTS_ON_SEND) ==
1310+ !(rs485.flags & SER_RS485_RTS_AFTER_SEND)) {
1311+ dev_warn_ratelimited(port->dev,
1312+ "%s (%d): invalid RTS setting, using RTS_ON_SEND instead\n",
1313+ port->name, port->line);
1314+ rs485.flags |= SER_RS485_RTS_ON_SEND;
1315+ rs485.flags &= ~SER_RS485_RTS_AFTER_SEND;
1316+ }
1317+
1318+ if (rs485.delay_rts_before_send > RS485_MAX_RTS_DELAY) {
1319+ rs485.delay_rts_before_send = RS485_MAX_RTS_DELAY;
1320+ dev_warn_ratelimited(port->dev,
1321+ "%s (%d): RTS delay before sending clamped to %u ms\n",
1322+ port->name, port->line, rs485.delay_rts_before_send);
1323+ }
1324+
1325+ if (rs485.delay_rts_after_send > RS485_MAX_RTS_DELAY) {
1326+ rs485.delay_rts_after_send = RS485_MAX_RTS_DELAY;
1327+ dev_warn_ratelimited(port->dev,
1328+ "%s (%d): RTS delay after sending clamped to %u ms\n",
1329+ port->name, port->line, rs485.delay_rts_after_send);
1330+ }
1331+ /* Return clean padding area to userspace */
1332+ memset(rs485.padding, 0, sizeof(rs485.padding));
1333+
12991334 spin_lock_irqsave(&port->lock, flags);
13001335 ret = port->rs485_config(port, &rs485);
1336+ if (!ret)
1337+ port->rs485 = rs485;
13011338 spin_unlock_irqrestore(&port->lock, flags);
13021339 if (ret)
13031340 return ret;
@@ -1610,24 +1647,24 @@ static void uart_wait_until_sent(struct tty_struct *tty, int timeout) · 306 unmodified lines
16101647 * Note: we have to use pretty tight timings here to satisfy
16111648 * the NIST-PCTS.
16121649 */
1613− char_time = (port->timeout - HZ/50) / port->fifosize;
1614− char_time = char_time / 5;
1615− if (char_time == 0)
1616− char_time = 1;
1650+ char_time = max(nsecs_to_jiffies(port->frame_time / 5), 1UL);
1651+
16171652 if (timeout && timeout < char_time)
16181653 char_time = timeout;
16191654
1620− /*
1621− * If the transmitter hasn't cleared in twice the approximate
1622− * amount of time to send the entire FIFO, it probably won't
1623− * ever clear. This assumes the UART isn't doing flow
1624− * control, which is currently the case. Hence, if it ever
1625− * takes longer than port->timeout, this is probably due to a
1626− * UART bug of some kind. So, we clamp the timeout parameter at
1627− * 2*port->timeout.
1628− */
1629− if (timeout == 0 || timeout > 2 * port->timeout)
1630− timeout = 2 * port->timeout;
1655+ if (!uart_cts_enabled(port)) {
1656+ /*
1657+ * If the transmitter hasn't cleared in twice the approximate
1658+ * amount of time to send the entire FIFO, it probably won't
1659+ * ever clear. This assumes the UART isn't doing flow
1660+ * control, which is currently the case. Hence, if it ever
1661+ * takes longer than port->timeout, this is probably due to a
1662+ * UART bug of some kind. So, we clamp the timeout parameter at
1663+ * 2*port->timeout.
1664+ */
1665+ if (timeout == 0 || timeout > 2 * port->timeout)
1666+ timeout = 2 * port->timeout;
1667+ }
16311668
16321669 expire = jiffies + timeout;
16331670
@@ -1643,7 +1680,7 @@ static void uart_wait_until_sent(struct tty_struct *tty, int timeout) · 9 unmodified lines
16431680 msleep_interruptible(jiffies_to_msecs(char_time));
16441681 if (signal_pending(current))
16451682 break;
1646− if (time_after(jiffies, expire))
1683+ if (timeout && time_after(jiffies, expire))
16471684 break;
16481685 }
16491686 uart_port_deref(port);
@@ -2174,15 +2211,23 @@ int uart_suspend_port(struct uart_driver *drv, struct uart_port *uport) · 524 unmodified lines
21742211 }
21752212 put_device(tty_dev);
21762213
2177− /* Nothing to do if the console is not suspending */
2178− if (!console_suspend_enabled && uart_console(uport))
2214+ /*
2215+ * Nothing to do if the console is not suspending
2216+ * except stop_rx to prevent any asynchronous data
2217+ * over RX line. Re-start_rx, when required, is
2218+ * done by set_termios in resume sequence
2219+ */
2220+ if (!console_suspend_enabled && uart_console(uport)) {
2221+ uport->ops->stop_rx(uport);
21792222 goto unlock;
2223+ }
21802224
21812225 uport->suspended = 1;
21822226
21832227 if (tty_port_initialized(port)) {
21842228 const struct uart_ops *ops = uport->ops;
21852229 int tries;
2230+ unsigned int mctrl;
21862231
21872232 tty_port_set_suspended(port, 1);
21882233 tty_port_set_initialized(port, 0);
@@ -2190,6 +2235,9 @@ int uart_suspend_port(struct uart_driver *drv, struct uart_port *uport) · 1 unmodified line
21902235 spin_lock_irq(&uport->lock);
21912236 ops->stop_tx(uport);
21922237 ops->set_mctrl(uport, 0);
2238+ /* save mctrl so it can be restored on resume */
2239+ mctrl = uport->mctrl;
2240+ uport->mctrl = 0;
21932241 ops->stop_rx(uport);
21942242 spin_unlock_irq(&uport->lock);
21952243
@@ -2203,6 +2251,7 @@ int uart_suspend_port(struct uart_driver *drv, struct uart_port *uport) · 7 unmodified lines
22032251 uport->name);
22042252
22052253 ops->shutdown(uport);
2254+ uport->mctrl = mctrl;
22062255 }
22072256
22082257 /*
drivers/tty/serial/serial_txx9.c+2−0
@@ -618,6 +618,8 @@ serial_txx9_set_termios(struct uart_port *up, struct ktermios *termios, · 617 unmodified lines
618618 case CS6: /* not supported */
619619 case CS8:
620620 cval |= TXX9_SILCR_UMODE_8BIT;
621+ termios->c_cflag &= ~CSIZE;
622+ termios->c_cflag |= CS8;
621623 break;
622624 }
623625
drivers/tty/serial/sh-sci.c+5−1
@@ -2379,8 +2379,12 @@ static void sci_set_termios(struct uart_port *port, struct ktermios *termios, · 2378 unmodified lines
23792379 int best_clk = -1;
23802380 unsigned long flags;
23812381
2382− if ((termios->c_cflag & CSIZE) == CS7)
2382+ if ((termios->c_cflag & CSIZE) == CS7) {
23832383 smr_val |= SCSMR_CHR;
2384+ } else {
2385+ termios->c_cflag &= ~CSIZE;
2386+ termios->c_cflag |= CS8;
2387+ }
23842388 if (termios->c_cflag & PARENB)
23852389 smr_val |= SCSMR_PE;
23862390 if (termios->c_cflag & PARODD)
drivers/tty/serial/sifive.c+11−9
@@ -148,7 +148,6 @@ · 147 unmodified lines
148148 * @port: struct uart_port embedded in this struct
149149 * @dev: struct device *
150150 * @ier: shadowed copy of the interrupt enable register
151− * @clkin_rate: input clock to the UART IP block.
152151 * @baud_rate: UART serial line rate (e.g., 115200 baud)
153152 * @clk: reference to this device's clock
154153 * @clk_notifier: clock rate change notifier for upstream clock changes
@@ -159,7 +158,6 @@ struct sifive_serial_port { · 4 unmodified lines
159158 struct uart_port port;
160159 struct device *dev;
161160 unsigned char ier;
162− unsigned long clkin_rate;
163161 unsigned long baud_rate;
164162 struct clk *clk;
165163 struct notifier_block clk_notifier;
@@ -463,7 +461,7 @@ static void __ssp_update_div(struct sifive_serial_port *ssp) · 297 unmodified lines
463461 {
464462 u16 div;
465463
466− div = DIV_ROUND_UP(ssp->clkin_rate, ssp->baud_rate) - 1;
464+ div = DIV_ROUND_UP(ssp->port.uartclk, ssp->baud_rate) - 1;
467465
468466 __ssp_writel(div, SIFIVE_SERIAL_DIV_OFFS, ssp);
469467 }
@@ -648,8 +646,8 @@ static int sifive_serial_clk_notifier(struct notifier_block *nb, · 178 unmodified lines
648646 udelay(DIV_ROUND_UP(12 * 1000 * 1000, ssp->baud_rate));
649647 }
650648
651− if (event == POST_RATE_CHANGE && ssp->clkin_rate != cnd->new_rate) {
652− ssp->clkin_rate = cnd->new_rate;
649+ if (event == POST_RATE_CHANGE && ssp->port.uartclk != cnd->new_rate) {
650+ ssp->port.uartclk = cnd->new_rate;
653651 __ssp_update_div(ssp);
654652 }
655653
@@ -666,19 +664,24 @@ static void sifive_serial_set_termios(struct uart_port *port, · 10 unmodified lines
666664 int rate;
667665 char nstop;
668666
669− if ((termios->c_cflag & CSIZE) != CS8)
667+ if ((termios->c_cflag & CSIZE) != CS8) {
670668 dev_err_once(ssp->port.dev, "only 8-bit words supported\n");
669+ termios->c_cflag &= ~CSIZE;
670+ termios->c_cflag |= CS8;
671+ }
671672 if (termios->c_iflag & (INPCK | PARMRK))
672673 dev_err_once(ssp->port.dev, "parity checking not supported\n");
673674 if (termios->c_iflag & BRKINT)
674675 dev_err_once(ssp->port.dev, "BREAK detection not supported\n");
676+ termios->c_iflag &= ~(INPCK|PARMRK|BRKINT);
675677
676678 /* Set number of stop bits */
677679 nstop = (termios->c_cflag & CSTOPB) ? 2 : 1;
678680 __ssp_set_stop_bits(ssp, nstop);
679681
680682 /* Set line rate */
681− rate = uart_get_baud_rate(port, termios, old, 0, ssp->clkin_rate / 16);
683+ rate = uart_get_baud_rate(port, termios, old, 0,
684+ ssp->port.uartclk / 16);
682685 __ssp_update_baud_rate(ssp, rate);
683686
684687 spin_lock_irqsave(&ssp->port.lock, flags);
@@ -996,9 +999,8 @@ static int sifive_serial_probe(struct platform_device *pdev) · 311 unmodified lines
996999 }
9971000
9981001 /* Set up clock divider */
999− ssp->clkin_rate = clk_get_rate(ssp->clk);
1002+ ssp->port.uartclk = clk_get_rate(ssp->clk);
10001003 ssp->baud_rate = SIFIVE_DEFAULT_BAUD_RATE;
1001− ssp->port.uartclk = ssp->baud_rate * 16;
10021004 __ssp_update_div(ssp);
10031005
10041006 platform_set_drvdata(pdev, ssp);
drivers/tty/serial/st-asc.c+4−0
@@ -535,10 +535,14 @@ static void asc_set_termios(struct uart_port *port, struct ktermios *termios, · 534 unmodified lines
535535 /* set character length */
536536 if ((cflag & CSIZE) == CS7) {
537537 ctrl_val |= ASC_CTL_MODE_7BIT_PAR;
538+ cflag |= PARENB;
538539 } else {
539540 ctrl_val |= (cflag & PARENB) ? ASC_CTL_MODE_8BIT_PAR :
540541 ASC_CTL_MODE_8BIT;
542+ cflag &= ~CSIZE;
543+ cflag |= CS8;
541544 }
545+ termios->c_cflag = cflag;
542546
543547 /* set stop bit */
544548 ctrl_val |= (cflag & CSTOPB) ? ASC_CTL_STOP_2BIT : ASC_CTL_STOP_1BIT;
drivers/tty/serial/stm32-usart.c+187−38
@@ -37,6 +37,7 @@ · 36 unmodified lines
3737
3838 static void stm32_usart_stop_tx(struct uart_port *port);
3939 static void stm32_usart_transmit_chars(struct uart_port *port);
40+static void __maybe_unused stm32_usart_console_putchar(struct uart_port *port, unsigned char ch);
4041
4142 static inline struct stm32_port *to_stm32_port(struct uart_port *port)
4243 {
@@ -107,8 +108,6 @@ static int stm32_usart_config_rs485(struct uart_port *port, · 64 unmodified lines
107108
108109 stm32_usart_clr_bits(port, ofs->cr1, BIT(cfg->uart_enable_bit));
109110
110− port->rs485 = *rs485conf;
111−
112111 rs485conf->flags |= SER_RS485_RX_DURING_TX;
113112
114113 if (rs485conf->flags & SER_RS485_ENABLED) {
@@ -128,13 +127,10 @@ static int stm32_usart_config_rs485(struct uart_port *port, · 13 unmodified lines
128127 rs485conf->delay_rts_after_send,
129128 baud);
130129
131− if (rs485conf->flags & SER_RS485_RTS_ON_SEND) {
130+ if (rs485conf->flags & SER_RS485_RTS_ON_SEND)
132131 cr3 &= ~USART_CR3_DEP;
133− rs485conf->flags &= ~SER_RS485_RTS_AFTER_SEND;
134− } else {
132+ else
135133 cr3 |= USART_CR3_DEP;
136− rs485conf->flags |= SER_RS485_RTS_AFTER_SEND;
137− }
138134
139135 writel_relaxed(cr3, port->membase + ofs->cr3);
140136 writel_relaxed(cr1, port->membase + ofs->cr1);
@@ -421,6 +417,14 @@ static void stm32_usart_tx_interrupt_enable(struct uart_port *port) · 280 unmodified lines
421417 stm32_usart_set_bits(port, ofs->cr1, USART_CR1_TXEIE);
422418 }
423419
420+static void stm32_usart_tc_interrupt_enable(struct uart_port *port)
421+{
422+ struct stm32_port *stm32_port = to_stm32_port(port);
423+ const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
424+
425+ stm32_usart_set_bits(port, ofs->cr1, USART_CR1_TCIE);
426+}
427+
424428 static void stm32_usart_rx_dma_complete(void *arg)
425429 {
426430 struct uart_port *port = arg;
@@ -446,6 +450,50 @@ static void stm32_usart_tx_interrupt_disable(struct uart_port *port) · 19 unmodified lines
446450 stm32_usart_clr_bits(port, ofs->cr1, USART_CR1_TXEIE);
447451 }
448452
453+static void stm32_usart_tc_interrupt_disable(struct uart_port *port)
454+{
455+ struct stm32_port *stm32_port = to_stm32_port(port);
456+ const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
457+
458+ stm32_usart_clr_bits(port, ofs->cr1, USART_CR1_TCIE);
459+}
460+
461+static void stm32_usart_rs485_rts_enable(struct uart_port *port)
462+{
463+ struct stm32_port *stm32_port = to_stm32_port(port);
464+ struct serial_rs485 *rs485conf = &port->rs485;
465+
466+ if (stm32_port->hw_flow_control ||
467+ !(rs485conf->flags & SER_RS485_ENABLED))
468+ return;
469+
470+ if (rs485conf->flags & SER_RS485_RTS_ON_SEND) {
471+ mctrl_gpio_set(stm32_port->gpios,
472+ stm32_port->port.mctrl | TIOCM_RTS);
473+ } else {
474+ mctrl_gpio_set(stm32_port->gpios,
475+ stm32_port->port.mctrl & ~TIOCM_RTS);
476+ }
477+}
478+
479+static void stm32_usart_rs485_rts_disable(struct uart_port *port)
480+{
481+ struct stm32_port *stm32_port = to_stm32_port(port);
482+ struct serial_rs485 *rs485conf = &port->rs485;
483+
484+ if (stm32_port->hw_flow_control ||
485+ !(rs485conf->flags & SER_RS485_ENABLED))
486+ return;
487+
488+ if (rs485conf->flags & SER_RS485_RTS_ON_SEND) {
489+ mctrl_gpio_set(stm32_port->gpios,
490+ stm32_port->port.mctrl & ~TIOCM_RTS);
491+ } else {
492+ mctrl_gpio_set(stm32_port->gpios,
493+ stm32_port->port.mctrl | TIOCM_RTS);
494+ }
495+}
496+
449497 static void stm32_usart_transmit_chars_pio(struct uart_port *port)
450498 {
451499 struct stm32_port *stm32_port = to_stm32_port(port);
@@ -553,6 +601,13 @@ static void stm32_usart_transmit_chars(struct uart_port *port) · 101 unmodified lines
553601 u32 isr;
554602 int ret;
555603
604+ if (!stm32_port->hw_flow_control &&
605+ port->rs485.flags & SER_RS485_ENABLED) {
606+ stm32_port->txdone = false;
607+ stm32_usart_tc_interrupt_disable(port);
608+ stm32_usart_rs485_rts_enable(port);
609+ }
610+
556611 if (port->x_char) {
557612 if (stm32_usart_tx_dma_started(stm32_port) &&
558613 stm32_usart_tx_dma_enabled(stm32_port))
@@ -593,8 +648,14 @@ static void stm32_usart_transmit_chars(struct uart_port *port) · 34 unmodified lines
593648 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
594649 uart_write_wakeup(port);
595650
596− if (uart_circ_empty(xmit))
651+ if (uart_circ_empty(xmit)) {
597652 stm32_usart_tx_interrupt_disable(port);
653+ if (!stm32_port->hw_flow_control &&
654+ port->rs485.flags & SER_RS485_ENABLED) {
655+ stm32_port->txdone = true;
656+ stm32_usart_tc_interrupt_enable(port);
657+ }
658+ }
598659 }
599660
600661 static irqreturn_t stm32_usart_interrupt(int irq, void *ptr)
@@ -608,6 +669,13 @@ static irqreturn_t stm32_usart_interrupt(int irq, void *ptr) · 7 unmodified lines
608669
609670 sr = readl_relaxed(port->membase + ofs->isr);
610671
672+ if (!stm32_port->hw_flow_control &&
673+ port->rs485.flags & SER_RS485_ENABLED &&
674+ (sr & USART_SR_TC)) {
675+ stm32_usart_tc_interrupt_disable(port);
676+ stm32_usart_rs485_rts_disable(port);
677+ }
678+
611679 if ((sr & USART_SR_RTOF) && ofs->icr != UNDEF_REG)
612680 writel_relaxed(USART_ICR_RTOCF,
613681 port->membase + ofs->icr);
@@ -717,44 +785,27 @@ static void stm32_usart_disable_ms(struct uart_port *port) · 103 unmodified lines
717785 static void stm32_usart_stop_tx(struct uart_port *port)
718786 {
719787 struct stm32_port *stm32_port = to_stm32_port(port);
720− struct serial_rs485 *rs485conf = &port->rs485;
721788 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
722789
723790 stm32_usart_tx_interrupt_disable(port);
724791 if (stm32_usart_tx_dma_started(stm32_port) && stm32_usart_tx_dma_enabled(stm32_port))
725792 stm32_usart_clr_bits(port, ofs->cr3, USART_CR3_DMAT);
726793
727− if (rs485conf->flags & SER_RS485_ENABLED) {
728− if (rs485conf->flags & SER_RS485_RTS_ON_SEND) {
729− mctrl_gpio_set(stm32_port->gpios,
730− stm32_port->port.mctrl & ~TIOCM_RTS);
731− } else {
732− mctrl_gpio_set(stm32_port->gpios,
733− stm32_port->port.mctrl | TIOCM_RTS);
734− }
735− }
794+ stm32_usart_rs485_rts_disable(port);
736795 }
737796
738797 /* There are probably characters waiting to be transmitted. */
739798 static void stm32_usart_start_tx(struct uart_port *port)
740799 {
741− struct stm32_port *stm32_port = to_stm32_port(port);
742− struct serial_rs485 *rs485conf = &port->rs485;
743800 struct circ_buf *xmit = &port->state->xmit;
744801
745− if (uart_circ_empty(xmit) && !port->x_char)
802+ if (uart_circ_empty(xmit) && !port->x_char) {
803+ stm32_usart_rs485_rts_disable(port);
746804 return;
747−
748− if (rs485conf->flags & SER_RS485_ENABLED) {
749− if (rs485conf->flags & SER_RS485_RTS_ON_SEND) {
750− mctrl_gpio_set(stm32_port->gpios,
751− stm32_port->port.mctrl | TIOCM_RTS);
752− } else {
753− mctrl_gpio_set(stm32_port->gpios,
754− stm32_port->port.mctrl & ~TIOCM_RTS);
755− }
756805 }
757806
807+ stm32_usart_rs485_rts_enable(port);
808+
758809 stm32_usart_transmit_chars(port);
759810 }
760811
@@ -1037,13 +1088,22 @@ static void stm32_usart_set_termios(struct uart_port *port, · 276 unmodified lines
10371088 * CS8 or (CS7 + parity), 8 bits word aka [M1:M0] = 0b00
10381089 * M0 and M1 already cleared by cr1 initialization.
10391090 */
1040− if (bits == 9)
1091+ if (bits == 9) {
10411092 cr1 |= USART_CR1_M0;
1042− else if ((bits == 7) && cfg->has_7bits_data)
1093+ } else if ((bits == 7) && cfg->has_7bits_data) {
10431094 cr1 |= USART_CR1_M1;
1044− else if (bits != 8)
1095+ } else if (bits != 8) {
10451096 dev_dbg(port->dev, "Unsupported data bits config: %u bits\n"
10461097 , bits);
1098+ cflag &= ~CSIZE;
1099+ cflag |= CS8;
1100+ termios->c_cflag = cflag;
1101+ bits = 8;
1102+ if (cflag & PARENB) {
1103+ bits++;
1104+ cr1 |= USART_CR1_M0;
1105+ }
1106+ }
10471107
10481108 if (ofs->rtor != UNDEF_REG && (stm32_port->rx_ch ||
10491109 (stm32_port->fifoen &&
@@ -1222,6 +1282,33 @@ static void stm32_usart_pm(struct uart_port *port, unsigned int state, · 172 unmodified lines
12221282 }
12231283 }
12241284
1285+#if defined(CONFIG_CONSOLE_POLL)
1286+
1287+ /* Callbacks for characters polling in debug context (i.e. KGDB). */
1288+static int stm32_usart_poll_init(struct uart_port *port)
1289+{
1290+ struct stm32_port *stm32_port = to_stm32_port(port);
1291+
1292+ return clk_prepare_enable(stm32_port->clk);
1293+}
1294+
1295+static int stm32_usart_poll_get_char(struct uart_port *port)
1296+{
1297+ struct stm32_port *stm32_port = to_stm32_port(port);
1298+ const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
1299+
1300+ if (!(readl_relaxed(port->membase + ofs->isr) & USART_SR_RXNE))
1301+ return NO_POLL_CHAR;
1302+
1303+ return readl_relaxed(port->membase + ofs->rdr) & stm32_port->rdr_mask;
1304+}
1305+
1306+static void stm32_usart_poll_put_char(struct uart_port *port, unsigned char ch)
1307+{
1308+ stm32_usart_console_putchar(port, ch);
1309+}
1310+#endif /* CONFIG_CONSOLE_POLL */
1311+
12251312 static const struct uart_ops stm32_uart_ops = {
12261313 .tx_empty = stm32_usart_tx_empty,
12271314 .set_mctrl = stm32_usart_set_mctrl,
@@ -1243,6 +1330,11 @@ static const struct uart_ops stm32_uart_ops = { · 15 unmodified lines
12431330 .request_port = stm32_usart_request_port,
12441331 .config_port = stm32_usart_config_port,
12451332 .verify_port = stm32_usart_verify_port,
1333+#if defined(CONFIG_CONSOLE_POLL)
1334+ .poll_init = stm32_usart_poll_init,
1335+ .poll_get_char = stm32_usart_poll_get_char,
1336+ .poll_put_char = stm32_usart_poll_put_char,
1337+#endif /* CONFIG_CONSOLE_POLL */
12461338 };
12471339
12481340 /*
@@ -1640,18 +1732,24 @@ static int stm32_usart_serial_remove(struct platform_device *pdev) · 391 unmodified lines
16401732 return 0;
16411733 }
16421734
1643−#ifdef CONFIG_SERIAL_STM32_CONSOLE
1644−static void stm32_usart_console_putchar(struct uart_port *port, unsigned char ch)
1735+static void __maybe_unused stm32_usart_console_putchar(struct uart_port *port, unsigned char ch)
16451736 {
16461737 struct stm32_port *stm32_port = to_stm32_port(port);
16471738 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
1739+ u32 isr;
1740+ int ret;
16481741
1649− while (!(readl_relaxed(port->membase + ofs->isr) & USART_SR_TXE))
1650− cpu_relax();
1651−
1742+ ret = readl_relaxed_poll_timeout_atomic(port->membase + ofs->isr, isr,
1743+ (isr & USART_SR_TXE), 100,
1744+ STM32_USART_TIMEOUT_USEC);
1745+ if (ret != 0) {
1746+ dev_err(port->dev, "Error while sending data in UART TX : %d\n", ret);
1747+ return;
1748+ }
16521749 writel_relaxed(ch, port->membase + ofs->tdr);
16531750 }
16541751
1752+#ifdef CONFIG_SERIAL_STM32_CONSOLE
16551753 static void stm32_usart_console_write(struct console *co, const char *s,
16561754 unsigned int cnt)
16571755 {
@@ -1727,6 +1825,57 @@ static struct console stm32_console = { · 69 unmodified lines
17271825 #define STM32_SERIAL_CONSOLE NULL
17281826 #endif /* CONFIG_SERIAL_STM32_CONSOLE */
17291827
1828+#ifdef CONFIG_SERIAL_EARLYCON
1829+static void early_stm32_usart_console_putchar(struct uart_port *port, unsigned char ch)
1830+{
1831+ struct stm32_usart_info *info = port->private_data;
1832+
1833+ while (!(readl_relaxed(port->membase + info->ofs.isr) & USART_SR_TXE))
1834+ cpu_relax();
1835+
1836+ writel_relaxed(ch, port->membase + info->ofs.tdr);
1837+}
1838+
1839+static void early_stm32_serial_write(struct console *console, const char *s, unsigned int count)
1840+{
1841+ struct earlycon_device *device = console->data;
1842+ struct uart_port *port = &device->port;
1843+
1844+ uart_console_write(port, s, count, early_stm32_usart_console_putchar);
1845+}
1846+
1847+static int __init early_stm32_h7_serial_setup(struct earlycon_device *device, const char *options)
1848+{
1849+ if (!(device->port.membase || device->port.iobase))
1850+ return -ENODEV;
1851+ device->port.private_data = &stm32h7_info;
1852+ device->con->write = early_stm32_serial_write;
1853+ return 0;
1854+}
1855+
1856+static int __init early_stm32_f7_serial_setup(struct earlycon_device *device, const char *options)
1857+{
1858+ if (!(device->port.membase || device->port.iobase))
1859+ return -ENODEV;
1860+ device->port.private_data = &stm32f7_info;
1861+ device->con->write = early_stm32_serial_write;
1862+ return 0;
1863+}
1864+
1865+static int __init early_stm32_f4_serial_setup(struct earlycon_device *device, const char *options)
1866+{
1867+ if (!(device->port.membase || device->port.iobase))
1868+ return -ENODEV;
1869+ device->port.private_data = &stm32f4_info;
1870+ device->con->write = early_stm32_serial_write;
1871+ return 0;
1872+}
1873+
1874+OF_EARLYCON_DECLARE(stm32, "st,stm32h7-uart", early_stm32_h7_serial_setup);
1875+OF_EARLYCON_DECLARE(stm32, "st,stm32f7-uart", early_stm32_f7_serial_setup);
1876+OF_EARLYCON_DECLARE(stm32, "st,stm32-uart", early_stm32_f4_serial_setup);
1877+#endif /* CONFIG_SERIAL_EARLYCON */
1878+
17301879 static struct uart_driver stm32_usart_driver = {
17311880 .driver_name = DRIVER_NAME,
17321881 .dev_name = STM32_SERIAL_NAME,
drivers/tty/serial/stm32-usart.h+3−0
@@ -251,6 +251,8 @@ struct stm32_usart_info stm32h7_info = { · 250 unmodified lines
251251 #define RX_BUF_P (RX_BUF_L / 2) /* dma rx buffer period */
252252 #define TX_BUF_L RX_BUF_L /* dma tx buffer length */
253253
254+#define STM32_USART_TIMEOUT_USEC USEC_PER_SEC /* 1s timeout in µs */
255+
254256 struct stm32_port {
255257 struct uart_port port;
256258 struct clk *clk;
@@ -269,6 +271,7 @@ struct stm32_port { · 12 unmodified lines
269271 bool hw_flow_control;
270272 bool swap; /* swap RX & TX pins */
271273 bool fifoen;
274+ bool txdone;
272275 int rxftcfg; /* RX FIFO threshold CFG */
273276 int txftcfg; /* TX FIFO threshold CFG */
274277 bool wakeup_src;
drivers/tty/serial/sunplus-uart.c+1−1
@@ -498,7 +498,7 @@ static const struct uart_ops sunplus_uart_ops = { · 497 unmodified lines
498498 };
499499
500500 #ifdef CONFIG_SERIAL_SUNPLUS_CONSOLE
501−struct sunplus_uart_port *sunplus_console_ports[SUP_UART_NR];
501+static struct sunplus_uart_port *sunplus_console_ports[SUP_UART_NR];
502502
503503 static void sunplus_uart_console_putchar(struct uart_port *port,
504504 unsigned char ch)
drivers/tty/serial/sunsu.c+0−2
@@ -798,10 +798,8 @@ sunsu_change_speed(struct uart_port *port, unsigned int cflag, · 797 unmodified lines
798798 cval |= UART_LCR_PARITY;
799799 if (!(cflag & PARODD))
800800 cval |= UART_LCR_EPAR;
801−#ifdef CMSPAR
802801 if (cflag & CMSPAR)
803802 cval |= UART_LCR_SPAR;
804−#endif
805803
806804 /*
807805 * Work around a bug in the Oxford Semiconductor 952 rev B
drivers/tty/serial/uartlite.c+2−1
@@ -321,7 +321,8 @@ static void ulite_set_termios(struct uart_port *port, struct ktermios *termios, · 320 unmodified lines
321321 struct uartlite_data *pdata = port->private_data;
322322
323323 /* Set termios to what the hardware supports */
324− termios->c_cflag &= ~(BRKINT | CSTOPB | PARENB | PARODD | CSIZE);
324+ termios->c_iflag &= ~BRKINT;
325+ termios->c_cflag &= ~(CSTOPB | PARENB | PARODD | CSIZE);
325326 termios->c_cflag |= pdata->cflags & (PARENB | PARODD | CSIZE);
326327 tty_termios_encode_baud_rate(termios, pdata->baud, pdata->baud);
327328
drivers/tty/serial/xilinx_uartps.c+16−30
@@ -313,41 +313,27 @@ static void cdns_uart_handle_rx(void *dev_id, unsigned int isrstatus) · 312 unmodified lines
313313 static void cdns_uart_handle_tx(void *dev_id)
314314 {
315315 struct uart_port *port = (struct uart_port *)dev_id;
316+ struct circ_buf *xmit = &port->state->xmit;
316317 unsigned int numbytes;
317318
318− if (uart_circ_empty(&port->state->xmit)) {
319+ if (uart_circ_empty(xmit)) {
319320 writel(CDNS_UART_IXR_TXEMPTY, port->membase + CDNS_UART_IDR);
320− } else {
321− numbytes = port->fifosize;
322− while (numbytes && !uart_circ_empty(&port->state->xmit) &&
323− !(readl(port->membase + CDNS_UART_SR) &
324− CDNS_UART_SR_TXFULL)) {
325− /*
326− * Get the data from the UART circular buffer
327− * and write it to the cdns_uart's TX_FIFO
328− * register.
329− */
330− writel(
331− port->state->xmit.buf[port->state->xmit.tail],
332− port->membase + CDNS_UART_FIFO);
333−
334− port->icount.tx++;
335−
336− /*
337− * Adjust the tail of the UART buffer and wrap
338− * the buffer if it reaches limit.
339− */
340− port->state->xmit.tail =
341− (port->state->xmit.tail + 1) &
342− (UART_XMIT_SIZE - 1);
343−
344− numbytes--;
345− }
321+ return;
322+ }
346323
347− if (uart_circ_chars_pending(
348− &port->state->xmit) < WAKEUP_CHARS)
349− uart_write_wakeup(port);
324+ numbytes = port->fifosize;
325+ while (numbytes && !uart_circ_empty(xmit) &&
326+ !(readl(port->membase + CDNS_UART_SR) & CDNS_UART_SR_TXFULL)) {
327+
328+ writel(xmit->buf[xmit->tail], port->membase + CDNS_UART_FIFO);
329+
330+ port->icount.tx++;
331+ xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
332+ numbytes--;
350333 }
334+
335+ if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
336+ uart_write_wakeup(port);
351337 }
352338
353339 /**
drivers/tty/serial/zs.c+1−1
@@ -981,7 +981,7 @@ static const char *zs_type(struct uart_port *uport) · 980 unmodified lines
981981 static void zs_release_port(struct uart_port *uport)
982982 {
983983 iounmap(uport->membase);
984− uport->membase = 0;
984+ uport->membase = NULL;
985985 release_mem_region(uport->mapbase, ZS_CHAN_IO_SIZE);
986986 }
987987
drivers/tty/synclink_gt.c+2−0
@@ -1746,6 +1746,8 @@ static int hdlcdev_init(struct slgt_info *info) · 1745 unmodified lines
17461746 */
17471747 static void hdlcdev_exit(struct slgt_info *info)
17481748 {
1749+ if (!info->netdev)
1750+ return;
17491751 unregister_hdlc_device(info->netdev);
17501752 free_netdev(info->netdev);
17511753 info->netdev = NULL;
drivers/tty/sysrq.c+15−12
@@ -232,8 +232,10 @@ static void showacpu(void *dummy) · 231 unmodified lines
232232 unsigned long flags;
233233
234234 /* Idle CPUs have no interesting backtrace. */
235− if (idle_cpu(smp_processor_id()))
235+ if (idle_cpu(smp_processor_id())) {
236+ pr_info("CPU%d: backtrace skipped as idling\n", smp_processor_id());
236237 return;
238+ }
237239
238240 raw_spin_lock_irqsave(&show_lock, flags);
239241 pr_info("CPU%d:\n", smp_processor_id());
@@ -260,10 +262,13 @@ static void sysrq_handle_showallcpus(int key) · 20 unmodified lines
260262
261263 if (in_hardirq())
262264 regs = get_irq_regs();
263− if (regs) {
264− pr_info("CPU%d:\n", smp_processor_id());
265+
266+ pr_info("CPU%d:\n", smp_processor_id());
267+ if (regs)
265268 show_regs(regs);
266− }
269+ else
270+ show_stack(NULL, NULL, KERN_INFO);
271+
267272 schedule_work(&sysrq_showallcpus);
268273 }
269274 }
@@ -274,6 +279,8 @@ static const struct sysrq_key_op sysrq_showallcpus_op = { · 4 unmodified lines
274279 .action_msg = "Show backtrace of all active CPUs",
275280 .enable_mask = SYSRQ_ENABLE_DUMP,
276281 };
282+#else
283+#define sysrq_showallcpus_op (*(const struct sysrq_key_op *)NULL)
277284 #endif
278285
279286 static void sysrq_handle_showregs(int key)
@@ -405,6 +412,7 @@ static const struct sysrq_key_op sysrq_moom_op = { · 125 unmodified lines
405412 .enable_mask = SYSRQ_ENABLE_SIGNAL,
406413 };
407414
415+#ifdef CONFIG_BLOCK
408416 static void sysrq_handle_thaw(int key)
409417 {
410418 emergency_thaw_all();
@@ -415,6 +423,9 @@ static const struct sysrq_key_op sysrq_thaw_op = { · 4 unmodified lines
415423 .action_msg = "Emergency Thaw of all frozen filesystems",
416424 .enable_mask = SYSRQ_ENABLE_SIGNAL,
417425 };
426+#else
427+#define sysrq_thaw_op (*(const struct sysrq_key_op *)NULL)
428+#endif
418429
419430 static void sysrq_handle_kill(int key)
420431 {
@@ -468,17 +479,9 @@ static const struct sysrq_key_op *sysrq_key_table[62] = { · 47 unmodified lines
468479 NULL, /* g */
469480 NULL, /* h - reserved for help */
470481 &sysrq_kill_op, /* i */
471−#ifdef CONFIG_BLOCK
472482 &sysrq_thaw_op, /* j */
473−#else
474− NULL, /* j */
475−#endif
476483 &sysrq_SAK_op, /* k */
477−#ifdef CONFIG_SMP
478484 &sysrq_showallcpus_op, /* l */
479−#else
480− NULL, /* l */
481−#endif
482485 &sysrq_showmem_op, /* m */
483486 &sysrq_unrt_op, /* n */
484487 /* o: This will often be registered as 'Off' at init time */
drivers/tty/tty_baudrate.c+8−27
@@ -61,11 +61,10 @@ speed_t tty_termios_baud_rate(struct ktermios *termios) · 60 unmodified lines
6161
6262 cbaud = termios->c_cflag & CBAUD;
6363
64−#ifdef BOTHER
6564 /* Magic token for arbitrary speed via c_ispeed/c_ospeed */
6665 if (cbaud == BOTHER)
6766 return termios->c_ospeed;
68−#endif
67+
6968 if (cbaud & CBAUDEX) {
7069 cbaud &= ~CBAUDEX;
7170
@@ -92,16 +91,15 @@ EXPORT_SYMBOL(tty_termios_baud_rate); · 20 unmodified lines
9291
9392 speed_t tty_termios_input_baud_rate(struct ktermios *termios)
9493 {
95−#ifdef IBSHIFT
9694 unsigned int cbaud = (termios->c_cflag >> IBSHIFT) & CBAUD;
9795
9896 if (cbaud == B0)
9997 return tty_termios_baud_rate(termios);
100−#ifdef BOTHER
98+
10199 /* Magic token for arbitrary speed via c_ispeed*/
102100 if (cbaud == BOTHER)
103101 return termios->c_ispeed;
104−#endif
102+
105103 if (cbaud & CBAUDEX) {
106104 cbaud &= ~CBAUDEX;
107105
@@ -111,9 +109,6 @@ speed_t tty_termios_input_baud_rate(struct ktermios *termios) · 3 unmodified lines
111109 cbaud += 15;
112110 }
113111 return cbaud >= n_baud_table ? 0 : baud_table[cbaud];
114−#else /* IBSHIFT */
115− return tty_termios_baud_rate(termios);
116−#endif /* IBSHIFT */
117112 }
118113 EXPORT_SYMBOL(tty_termios_input_baud_rate);
119114
@@ -153,11 +148,9 @@ void tty_termios_encode_baud_rate(struct ktermios *termios, · 33 unmodified lines
153148 termios->c_ispeed = ibaud;
154149 termios->c_ospeed = obaud;
155150
156−#ifdef IBSHIFT
157151 if (((termios->c_cflag >> IBSHIFT) & CBAUD) != B0)
158152 ibinput = 1; /* An input speed was specified */
159−#endif
160−#ifdef BOTHER
153+
161154 /* If the user asked for a precise weird speed give a precise weird
162155 * answer. If they asked for a Bfoo speed they may have problems
163156 * digesting non-exact replies so fuzz a bit.
@@ -170,11 +163,9 @@ void tty_termios_encode_baud_rate(struct ktermios *termios, · 6 unmodified lines
170163 }
171164 if (((termios->c_cflag >> IBSHIFT) & CBAUD) == BOTHER)
172165 iclose = 0;
173−#endif
166+
174167 termios->c_cflag &= ~CBAUD;
175−#ifdef IBSHIFT
176168 termios->c_cflag &= ~(CBAUD << IBSHIFT);
177−#endif
178169
179170 /*
180171 * Our goal is to find a close match to the standard baud rate
@@ -194,22 +185,16 @@ void tty_termios_encode_baud_rate(struct ktermios *termios, · 13 unmodified lines
194185 /* For the case input == output don't set IBAUD bits
195186 * if the user didn't do so.
196187 */
197− if (ofound == i && !ibinput)
188+ if (ofound == i && !ibinput) {
198189 ifound = i;
199−#ifdef IBSHIFT
200− else {
190+ } else {
201191 ifound = i;
202192 termios->c_cflag |= (baud_bits[i] << IBSHIFT);
203193 }
204−#endif
205194 }
206195 } while (++i < n_baud_table);
207196
208− /*
209− * If we found no match then use BOTHER if provided or warn
210− * the user their platform maintainer needs to wake up if not.
211− */
212−#ifdef BOTHER
197+ /* If we found no match then use BOTHER. */
213198 if (ofound == -1)
214199 termios->c_cflag |= BOTHER;
215200 /* Set exact input bits only if the input and output differ or the
@@ -217,10 +202,6 @@ void tty_termios_encode_baud_rate(struct ktermios *termios, · 1 unmodified line
217202 */
218203 if (ifound == -1 && (ibaud != obaud || ibinput))
219204 termios->c_cflag |= (BOTHER << IBSHIFT);
220−#else
221− if (ifound == -1 || ofound == -1)
222− pr_warn_once("tty: Unable to return correct speed data as your architecture needs updating.\n");
223−#endif
224205 }
225206 EXPORT_SYMBOL_GPL(tty_termios_encode_baud_rate);
226207
drivers/tty/tty_ioctl.c+0−2
@@ -562,10 +562,8 @@ static int set_sgttyb(struct tty_struct *tty, struct sgttyb __user *sgttyb) · 561 unmodified lines
562562 termios.c_cc[VKILL] = tmp.sg_kill;
563563 set_sgflags(&termios, tmp.sg_flags);
564564 /* Try and encode into Bfoo format */
565−#ifdef BOTHER
566565 tty_termios_encode_baud_rate(&termios, termios.c_ispeed,
567566 termios.c_ospeed);
568−#endif
569567 up_write(&tty->termios_rwsem);
570568 tty_set_termios(tty, &termios);
571569 return 0;
drivers/usb/class/cdc-acm.h+0−8
@@ -7,14 +7,6 @@ · 6 unmodified lines
77 *
88 */
99
10−/*
11− * CMSPAR, some architectures can't have space and mark parity.
12− */
13−
14−#ifndef CMSPAR
15−#define CMSPAR 0
16−#endif
17−
1810 /*
1911 * Major and minor numbers.
2012 */
drivers/usb/serial/ark3116.c+1−2
@@ -208,10 +208,9 @@ static void ark3116_set_termios(struct tty_struct *tty, · 207 unmodified lines
208208 lcr |= UART_LCR_PARITY;
209209 if (!(cflag & PARODD))
210210 lcr |= UART_LCR_EPAR;
211−#ifdef CMSPAR
212211 if (cflag & CMSPAR)
213212 lcr |= UART_LCR_SPAR;
214−#endif
213+
215214 /* handshake control */
216215 hcr = (cflag & CRTSCTS) ? 0x03 : 0x00;
217216
drivers/usb/serial/whiteheat.c+0−4
@@ -30,10 +30,6 @@ · 29 unmodified lines
3030 #include <linux/usb/ezusb.h>
3131 #include "whiteheat.h" /* WhiteHEAT specific commands */
3232
33−#ifndef CMSPAR
34−#define CMSPAR 0
35−#endif
36−
3733 /*
3834 * Version Information
3935 */
include/linux/serial_core.h+1−0
@@ -232,6 +232,7 @@ struct uart_port { · 231 unmodified lines
232232 int hw_stopped; /* sw-assisted CTS flow state */
233233 unsigned int mctrl; /* current modem ctrl settings */
234234 unsigned int timeout; /* character-based timeout */
235+ unsigned int frame_time; /* frame timing in ns */
235236 unsigned int type; /* port type */
236237 const struct uart_ops *ops;
237238 unsigned int custom_divisor;
include/linux/serial_s3c.h+3−0
@@ -256,6 +256,9 @@ · 255 unmodified lines
256256 #define APPLE_S5L_UCON_DEFAULT (S3C2410_UCON_TXIRQMODE | \
257257 S3C2410_UCON_RXIRQMODE | \
258258 S3C2410_UCON_RXFIFO_TOI)
259+#define APPLE_S5L_UCON_MASK (APPLE_S5L_UCON_RXTO_ENA_MSK | \
260+ APPLE_S5L_UCON_RXTHRESH_ENA_MSK | \
261+ APPLE_S5L_UCON_TXTHRESH_ENA_MSK)
259262
260263 #define APPLE_S5L_UTRSTAT_RXTHRESH (1<<4)
261264 #define APPLE_S5L_UTRSTAT_TXTHRESH (1<<5)
include/uapi/asm-generic/termbits-common.h+65−0
@@ -0,0 +1,65 @@
1+/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
2+#ifndef __ASM_GENERIC_TERMBITS_COMMON_H
3+#define __ASM_GENERIC_TERMBITS_COMMON_H
4+
5+typedef unsigned char cc_t;
6+typedef unsigned int speed_t;
7+
8+/* c_iflag bits */
9+#define IGNBRK 0x001 /* Ignore break condition */
10+#define BRKINT 0x002 /* Signal interrupt on break */
11+#define IGNPAR 0x004 /* Ignore characters with parity errors */
12+#define PARMRK 0x008 /* Mark parity and framing errors */
13+#define INPCK 0x010 /* Enable input parity check */
14+#define ISTRIP 0x020 /* Strip 8th bit off characters */
15+#define INLCR 0x040 /* Map NL to CR on input */
16+#define IGNCR 0x080 /* Ignore CR */
17+#define ICRNL 0x100 /* Map CR to NL on input */
18+#define IXANY 0x800 /* Any character will restart after stop */
19+
20+/* c_oflag bits */
21+#define OPOST 0x01 /* Perform output processing */
22+#define OCRNL 0x08
23+#define ONOCR 0x10
24+#define ONLRET 0x20
25+#define OFILL 0x40
26+#define OFDEL 0x80
27+
28+/* c_cflag bit meaning */
29+/* Common CBAUD rates */
30+#define B0 0x00000000 /* hang up */
31+#define B50 0x00000001
32+#define B75 0x00000002
33+#define B110 0x00000003
34+#define B134 0x00000004
35+#define B150 0x00000005
36+#define B200 0x00000006
37+#define B300 0x00000007
38+#define B600 0x00000008
39+#define B1200 0x00000009
40+#define B1800 0x0000000a
41+#define B2400 0x0000000b
42+#define B4800 0x0000000c
43+#define B9600 0x0000000d
44+#define B19200 0x0000000e
45+#define B38400 0x0000000f
46+#define EXTA B19200
47+#define EXTB B38400
48+
49+#define CMSPAR 0x40000000 /* mark or space (stick) parity */
50+#define CRTSCTS 0x80000000 /* flow control */
51+
52+#define IBSHIFT 16 /* Shift from CBAUD to CIBAUD */
53+
54+/* tcflow() ACTION argument and TCXONC use these */
55+#define TCOOFF 0 /* Suspend output */
56+#define TCOON 1 /* Restart suspended output */
57+#define TCIOFF 2 /* Send a STOP character */
58+#define TCION 3 /* Send a START character */
59+
60+/* tcflush() QUEUE_SELECTOR argument and TCFLSH use these */
61+#define TCIFLUSH 0 /* Discard data received but not yet read */
62+#define TCOFLUSH 1 /* Discard data written but not yet sent */
63+#define TCIOFLUSH 2 /* Discard all pending data */
64+
65+#endif /* __ASM_GENERIC_TERMBITS_COMMON_H */
include/uapi/asm-generic/termbits.h+94−145
@@ -2,10 +2,8 @@ · 1 unmodified line
22 #ifndef __ASM_GENERIC_TERMBITS_H
33 #define __ASM_GENERIC_TERMBITS_H
44
5−#include <linux/posix_types.h>
5+#include <asm-generic/termbits-common.h>
66
7−typedef unsigned char cc_t;
8−typedef unsigned int speed_t;
97 typedef unsigned int tcflag_t;
108
119 #define NCCS 19
@@ -41,156 +39,107 @@ struct ktermios { · 29 unmodified lines
4139 };
4240
4341 /* c_cc characters */
44−#define VINTR 0
45−#define VQUIT 1
46−#define VERASE 2
47−#define VKILL 3
48−#define VEOF 4
49−#define VTIME 5
50−#define VMIN 6
51−#define VSWTC 7
52−#define VSTART 8
53−#define VSTOP 9
54−#define VSUSP 10
55−#define VEOL 11
56−#define VREPRINT 12
57−#define VDISCARD 13
58−#define VWERASE 14
59−#define VLNEXT 15
60−#define VEOL2 16
42+#define VINTR 0
43+#define VQUIT 1
44+#define VERASE 2
45+#define VKILL 3
46+#define VEOF 4
47+#define VTIME 5
48+#define VMIN 6
49+#define VSWTC 7
50+#define VSTART 8
51+#define VSTOP 9
52+#define VSUSP 10
53+#define VEOL 11
54+#define VREPRINT 12
55+#define VDISCARD 13
56+#define VWERASE 14
57+#define VLNEXT 15
58+#define VEOL2 16
6159
6260 /* c_iflag bits */
63−#define IGNBRK 0000001
64−#define BRKINT 0000002
65−#define IGNPAR 0000004
66−#define PARMRK 0000010
67−#define INPCK 0000020
68−#define ISTRIP 0000040
69−#define INLCR 0000100
70−#define IGNCR 0000200
71−#define ICRNL 0000400
72−#define IUCLC 0001000
73−#define IXON 0002000
74−#define IXANY 0004000
75−#define IXOFF 0010000
76−#define IMAXBEL 0020000
77−#define IUTF8 0040000
61+#define IUCLC 0x0200
62+#define IXON 0x0400
63+#define IXOFF 0x1000
64+#define IMAXBEL 0x2000
65+#define IUTF8 0x4000
7866
7967 /* c_oflag bits */
80−#define OPOST 0000001
81−#define OLCUC 0000002
82−#define ONLCR 0000004
83−#define OCRNL 0000010
84−#define ONOCR 0000020
85−#define ONLRET 0000040
86−#define OFILL 0000100
87−#define OFDEL 0000200
88−#define NLDLY 0000400
89−#define NL0 0000000
90−#define NL1 0000400
91−#define CRDLY 0003000
92−#define CR0 0000000
93−#define CR1 0001000
94−#define CR2 0002000
95−#define CR3 0003000
96−#define TABDLY 0014000
97−#define TAB0 0000000
98−#define TAB1 0004000
99−#define TAB2 0010000
100−#define TAB3 0014000
101−#define XTABS 0014000
102−#define BSDLY 0020000
103−#define BS0 0000000
104−#define BS1 0020000
105−#define VTDLY 0040000
106−#define VT0 0000000
107−#define VT1 0040000
108−#define FFDLY 0100000
109−#define FF0 0000000
110−#define FF1 0100000
68+#define OLCUC 0x00002
69+#define ONLCR 0x00004
70+#define NLDLY 0x00100
71+#define NL0 0x00000
72+#define NL1 0x00100
73+#define CRDLY 0x00600
74+#define CR0 0x00000
75+#define CR1 0x00200
76+#define CR2 0x00400
77+#define CR3 0x00600
78+#define TABDLY 0x01800
79+#define TAB0 0x00000
80+#define TAB1 0x00800
81+#define TAB2 0x01000
82+#define TAB3 0x01800
83+#define XTABS 0x01800
84+#define BSDLY 0x02000
85+#define BS0 0x00000
86+#define BS1 0x02000
87+#define VTDLY 0x04000
88+#define VT0 0x00000
89+#define VT1 0x04000
90+#define FFDLY 0x08000
91+#define FF0 0x00000
92+#define FF1 0x08000
11193
11294 /* c_cflag bit meaning */
113−#define CBAUD 0010017
114−#define B0 0000000 /* hang up */
115−#define B50 0000001
116−#define B75 0000002
117−#define B110 0000003
118−#define B134 0000004
119−#define B150 0000005
120−#define B200 0000006
121−#define B300 0000007
122−#define B600 0000010
123−#define B1200 0000011
124−#define B1800 0000012
125−#define B2400 0000013
126−#define B4800 0000014
127−#define B9600 0000015
128−#define B19200 0000016
129−#define B38400 0000017
130−#define EXTA B19200
131−#define EXTB B38400
132−#define CSIZE 0000060
133−#define CS5 0000000
134−#define CS6 0000020
135−#define CS7 0000040
136−#define CS8 0000060
137−#define CSTOPB 0000100
138−#define CREAD 0000200
139−#define PARENB 0000400
140−#define PARODD 0001000
141−#define HUPCL 0002000
142−#define CLOCAL 0004000
143−#define CBAUDEX 0010000
144−#define BOTHER 0010000
145−#define B57600 0010001
146−#define B115200 0010002
147−#define B230400 0010003
148−#define B460800 0010004
149−#define B500000 0010005
150−#define B576000 0010006
151−#define B921600 0010007
152−#define B1000000 0010010
153−#define B1152000 0010011
154−#define B1500000 0010012
155−#define B2000000 0010013
156−#define B2500000 0010014
157−#define B3000000 0010015
158−#define B3500000 0010016
159−#define B4000000 0010017
160−#define CIBAUD 002003600000 /* input baud rate */
161−#define CMSPAR 010000000000 /* mark or space (stick) parity */
162−#define CRTSCTS 020000000000 /* flow control */
163−
164−#define IBSHIFT 16 /* Shift from CBAUD to CIBAUD */
95+#define CBAUD 0x0000100f
96+#define CSIZE 0x00000030
97+#define CS5 0x00000000
98+#define CS6 0x00000010
99+#define CS7 0x00000020
100+#define CS8 0x00000030
101+#define CSTOPB 0x00000040
102+#define CREAD 0x00000080
103+#define PARENB 0x00000100
104+#define PARODD 0x00000200
105+#define HUPCL 0x00000400
106+#define CLOCAL 0x00000800
107+#define CBAUDEX 0x00001000
108+#define BOTHER 0x00001000
109+#define B57600 0x00001001
110+#define B115200 0x00001002
111+#define B230400 0x00001003
112+#define B460800 0x00001004
113+#define B500000 0x00001005
114+#define B576000 0x00001006
115+#define B921600 0x00001007
116+#define B1000000 0x00001008
117+#define B1152000 0x00001009
118+#define B1500000 0x0000100a
119+#define B2000000 0x0000100b
120+#define B2500000 0x0000100c
121+#define B3000000 0x0000100d
122+#define B3500000 0x0000100e
123+#define B4000000 0x0000100f
124+#define CIBAUD 0x100f0000 /* input baud rate */
165125
166126 /* c_lflag bits */
167−#define ISIG 0000001
168−#define ICANON 0000002
169−#define XCASE 0000004
170−#define ECHO 0000010
171−#define ECHOE 0000020
172−#define ECHOK 0000040
173−#define ECHONL 0000100
174−#define NOFLSH 0000200
175−#define TOSTOP 0000400
176−#define ECHOCTL 0001000
177−#define ECHOPRT 0002000
178−#define ECHOKE 0004000
179−#define FLUSHO 0010000
180−#define PENDIN 0040000
181−#define IEXTEN 0100000
182−#define EXTPROC 0200000
183−
184−/* tcflow() and TCXONC use these */
185−#define TCOOFF 0
186−#define TCOON 1
187−#define TCIOFF 2
188−#define TCION 3
189−
190−/* tcflush() and TCFLSH use these */
191−#define TCIFLUSH 0
192−#define TCOFLUSH 1
193−#define TCIOFLUSH 2
127+#define ISIG 0x00001
128+#define ICANON 0x00002
129+#define XCASE 0x00004
130+#define ECHO 0x00008
131+#define ECHOE 0x00010
132+#define ECHOK 0x00020
133+#define ECHONL 0x00040
134+#define NOFLSH 0x00080
135+#define TOSTOP 0x00100
136+#define ECHOCTL 0x00200
137+#define ECHOPRT 0x00400
138+#define ECHOKE 0x00800
139+#define FLUSHO 0x01000
140+#define PENDIN 0x04000
141+#define IEXTEN 0x08000
142+#define EXTPROC 0x10000
194143
195144 /* tcsetattr uses these */
196145 #define TCSANOW 0