History

Merge branch 'drm-next-4.18' of git://people.freedesktop.org/~agd5f/linux into drm-next

Main changes for 4.18. I'd like to do a separate pull for vega20 later this week or next. Highlights: - Reserve pre-OS scanout buffer during init for seemless transition from console to driver - VEGAM support - Improved GPU scheduler documentation - Initial gfxoff support for raven - SR-IOV fixes - Default to non-AGP on PowerPC for radeon - Fine grained clock voltage control for vega10 - Power profiles for vega10 - Further clean up of powerplay/driver interface - Underlay fixes - Display link bw updates - Gamma fixes - Scatter/Gather display support on CZ/ST - Misc bug fixes and clean ups [airlied: fixup v3d vs scheduler API change]

Dave Airlie committed 8 years ago

Commit 95d2c3e2 parents b8a7108 8344c53259 files · +14419 −4589Browse files

Unified · Split

259 files
  1. drivers/gpu/drm/amd/amdgpu/Makefile +4 −0
  2. drivers/gpu/drm/amd/amdgpu/amdgpu.h +40 −3
  3. drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c +5 −6
  4. drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c +9 −3
  5. drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c +9 −2
  6. drivers/gpu/drm/amd/amdgpu/amdgpu_atpx_handler.c +1 −1
  7. drivers/gpu/drm/amd/amdgpu/amdgpu_benchmark.c +11 −4
  8. drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c +3 −241
  9. drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c +4 −4
  10. drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c +5 −11
  11. drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c +61 −11
  12. drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c +190 −5
  13. drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +80 −25
  14. drivers/gpu/drm/amd/amdgpu/amdgpu_display.c +9 −31
  15. drivers/gpu/drm/amd/amdgpu/amdgpu_display.h +1 −1
  16. drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.c +20 −0
  17. drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h +3 −8
  18. drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c +12 −2
  19. drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c +6 −6
  20. drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c +3 −2
  21. drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c +11 −6
  22. drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c +37 −13
  23. drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c +6 −2
  24. drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c +50 −8
  25. drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h +0 −1
  26. drivers/gpu/drm/amd/amdgpu/amdgpu_object.c +72 −48
  27. drivers/gpu/drm/amd/amdgpu/amdgpu_object.h +34 −4
  28. drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c +282 −83
  29. drivers/gpu/drm/amd/amdgpu/amdgpu_prime.c +10 −4
  30. drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c +20 −0
  31. drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h +10 −1
  32. drivers/gpu/drm/amd/amdgpu/amdgpu_test.c +12 −6
  33. drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h +1 −1
  34. drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c +71 −39
  35. drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h +1 −0
  36. drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c +49 −3
  37. drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h +22 −0
  38. drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c +6 −1
  39. drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c +32 −3
  40. drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c +2 −2
  41. drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c +71 −43
  42. drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h +3 −2
  43. drivers/gpu/drm/amd/amdgpu/ci_dpm.c +2 −2
  44. drivers/gpu/drm/amd/amdgpu/cik.c +7 −0
  45. drivers/gpu/drm/amd/amdgpu/dce_v10_0.c +5 −12
  46. drivers/gpu/drm/amd/amdgpu/dce_v11_0.c +15 −15
  47. drivers/gpu/drm/amd/amdgpu/dce_v6_0.c +5 −12
  48. drivers/gpu/drm/amd/amdgpu/dce_v8_0.c +5 −12
  49. drivers/gpu/drm/amd/amdgpu/dce_virtual.c +4 −5
  50. drivers/gpu/drm/amd/amdgpu/df_v1_7.c +112 −0
  51. drivers/gpu/drm/amd/amdgpu/df_v1_7.h +13 −25
  52. drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c +80 −22
  53. drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c +185 −82
  54. drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c +23 −2
  55. drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c +23 −2
  56. drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c +29 −4
  57. drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c +77 −60
  58. drivers/gpu/drm/amd/amdgpu/kv_dpm.c +2 −2
  59. drivers/gpu/drm/amd/amdgpu/mxgpu_ai.c +3 −1
  60. drivers/gpu/drm/amd/amdgpu/psp_gfx_if.h +46 −21
  61. drivers/gpu/drm/amd/amdgpu/psp_v10_0.c +9 −0
  62. drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c +9 −3
  63. drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c +35 −28
  64. drivers/gpu/drm/amd/amdgpu/si.c +7 −0
  65. drivers/gpu/drm/amd/amdgpu/si_dpm.c +1 −1
  66. drivers/gpu/drm/amd/amdgpu/soc15.c +19 −58
  67. drivers/gpu/drm/amd/amdgpu/soc15d.h +1 −0
  68. drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c +2 −2
  69. drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c +16 −4
  70. drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c +15 −2
  71. drivers/gpu/drm/amd/amdgpu/vce_v3_0.c +4 −3
  72. drivers/gpu/drm/amd/amdgpu/vce_v4_0.c +1 −0
  73. drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c +2 −0
  74. drivers/gpu/drm/amd/amdgpu/vi.c +111 −19
  75. drivers/gpu/drm/amd/display/Kconfig +6 −8
  76. drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +153 −72
  77. drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h +3 −2
  78. drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c +1 −0
  79. drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c +12 −8
  80. drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_services.c +11 −2
  81. drivers/gpu/drm/amd/display/dc/basics/fixpt31_32.c +79 −79
  82. drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c +85 −1
  83. drivers/gpu/drm/amd/display/dc/bios/command_table.c +12 −10
  84. drivers/gpu/drm/amd/display/dc/bios/command_table2.c +16 −10
  85. drivers/gpu/drm/amd/display/dc/bios/command_table_helper.c +3 −0
  86. drivers/gpu/drm/amd/display/dc/bios/command_table_helper2.c +3 −0
  87. drivers/gpu/drm/amd/display/dc/calcs/calcs_logger.h +579 −0
  88. drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c +256 −4
  89. drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c +37 −37
  90. drivers/gpu/drm/amd/display/dc/core/dc.c +17 −95
  91. drivers/gpu/drm/amd/display/dc/core/dc_debug.c +16 −22
  92. drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c +23 −1
  93. drivers/gpu/drm/amd/display/dc/core/dc_link.c +42 −21
  94. drivers/gpu/drm/amd/display/dc/core/dc_link_ddc.c +7 −3
  95. drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c +23 −7
  96. drivers/gpu/drm/amd/display/dc/core/dc_resource.c +94 −178
  97. drivers/gpu/drm/amd/display/dc/core/dc_stream.c +22 −2
  98. drivers/gpu/drm/amd/display/dc/core/dc_surface.c +14 −8
  99. drivers/gpu/drm/amd/display/dc/dc.h +6 −24
  100. drivers/gpu/drm/amd/display/dc/dc_helper.c +59 −0
  101. drivers/gpu/drm/amd/display/dc/dc_hw_types.h +5 −0
  102. drivers/gpu/drm/amd/display/dc/dc_link.h +9 −0
  103. drivers/gpu/drm/amd/display/dc/dc_stream.h +8 −20
  104. drivers/gpu/drm/amd/display/dc/dc_types.h +9 −6
  105. drivers/gpu/drm/amd/display/dc/dce/dce_audio.c +5 −4
  106. drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c +12 −5
  107. drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.c +2 −1
  108. drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c +4 −2
  109. drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.h +2 −0
  110. drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c +94 −9
  111. drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h +17 −0
  112. drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c +19 −49
  113. drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c +0 −33
  114. drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c +74 −21
  115. drivers/gpu/drm/amd/display/dc/dce110/dce110_mem_input_v.c +1 −0
  116. drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c +0 −33
  117. drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c +8 −8
  118. drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator_v.c +0 −7
  119. drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c +1 −34
  120. drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.h +0 −5
  121. drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c +1 −2
  122. drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c +6 −6
  123. drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c +0 −49
  124. drivers/gpu/drm/amd/display/dc/dcn10/Makefile +1 −1
  125. drivers/gpu/drm/amd/display/dc/dcn10/dcn10_cm_common.c +6 −6
  126. drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c +34 −2
  127. drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h +73 −3
  128. drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c +56 −34
  129. drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.c +220 −1
  130. drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.h +1 −6
  131. drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c +176 −11
  132. drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h +50 −29
  133. drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c +221 −67
  134. drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c +22 −2
  135. drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.h +5 −0
  136. drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c +88 −6
  137. drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h +16 −0
  138. drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c +21 −282
  139. drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c +1490 −0
  140. drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h +524 −0
  141. drivers/gpu/drm/amd/display/dc/dm_services.h +4 −0
  142. drivers/gpu/drm/amd/display/dc/dml/display_mode_lib.c +76 −62
  143. drivers/gpu/drm/amd/display/dc/dml/display_mode_structs.h +3 −2
  144. drivers/gpu/drm/amd/display/dc/gpio/hw_factory.c +3 −0
  145. drivers/gpu/drm/amd/display/dc/gpio/hw_translate.c +3 −0
  146. drivers/gpu/drm/amd/display/dc/i2caux/dce110/i2c_hw_engine_dce110.c +1 −1
  147. drivers/gpu/drm/amd/display/dc/i2caux/i2caux.c +3 −0
  148. drivers/gpu/drm/amd/display/dc/inc/core_types.h +1 −5
  149. drivers/gpu/drm/amd/display/dc/inc/dc_link_ddc.h +3 −2
  150. drivers/gpu/drm/amd/display/dc/inc/dce_calcs.h +4 −0
  151. drivers/gpu/drm/amd/display/dc/inc/hw/dchubbub.h +64 −0
  152. drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h +17 −1
  153. drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h +1 −1
  154. drivers/gpu/drm/amd/display/dc/inc/hw/hw_shared.h +5 −5
  155. drivers/gpu/drm/amd/display/dc/inc/hw/ipp.h +1 −1
  156. drivers/gpu/drm/amd/display/dc/inc/hw/link_encoder.h +1 −0
  157. drivers/gpu/drm/amd/display/dc/inc/hw/mem_input.h +1 −0
  158. drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h +17 −0
  159. drivers/gpu/drm/amd/display/dc/inc/hw/stream_encoder.h +23 −13
  160. drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h +3 −0
  161. drivers/gpu/drm/amd/display/dc/inc/hw/transform.h +1 −1
  162. drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h +16 −1
  163. drivers/gpu/drm/amd/display/dc/inc/reg_helper.h +56 −0
  164. drivers/gpu/drm/amd/display/dc/inc/resource.h +0 −4
  165. drivers/gpu/drm/amd/display/dc/irq_types.h +7 −0
  166. drivers/gpu/drm/amd/display/include/dal_asic_id.h +14 −2
  167. drivers/gpu/drm/amd/display/include/dal_types.h +3 −0
  168. drivers/gpu/drm/amd/display/include/fixed31_32.h +19 −21
  169. drivers/gpu/drm/amd/display/include/logger_types.h +32 −32
  170. drivers/gpu/drm/amd/display/modules/color/color_gamma.c +337 −45
  171. drivers/gpu/drm/amd/display/modules/color/color_gamma.h +47 −1
  172. drivers/gpu/drm/amd/display/modules/stats/stats.c +43 −22
  173. drivers/gpu/drm/amd/include/amd_shared.h +20 −0
  174. drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_1_0_offset.h +16 −3
  175. drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_1_0_sh_mask.h +8 −0
  176. drivers/gpu/drm/amd/include/asic_reg/df/df_1_7_default.h +26 −0
  177. drivers/gpu/drm/amd/include/asic_reg/df/df_1_7_offset.h +33 −0
  178. drivers/gpu/drm/amd/include/asic_reg/df/df_1_7_sh_mask.h +48 −0
  179. drivers/gpu/drm/amd/include/atombios.h +7 −0
  180. drivers/gpu/drm/amd/include/atomfirmware.h +168 −2
  181. drivers/gpu/drm/amd/include/cgs_common.h +0 −170
  182. drivers/gpu/drm/amd/include/kgd_pp_interface.h +1 −12
  183. drivers/gpu/drm/amd/powerplay/amd_powerplay.c +158 −331
  184. drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c +5 −17
  185. drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c +72 −18
  186. drivers/gpu/drm/amd/powerplay/hwmgr/pp_psm.c +1 −1
  187. drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.c +135 −69
  188. drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.h +14 −1
  189. drivers/gpu/drm/amd/powerplay/hwmgr/ppatomfwctrl.c +47 −52
  190. drivers/gpu/drm/amd/powerplay/hwmgr/ppatomfwctrl.h +2 −0
  191. drivers/gpu/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c +38 −1
  192. drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c +2 −2
  193. drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c +158 −28
  194. drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.h +1 −2
  195. drivers/gpu/drm/amd/powerplay/hwmgr/smu7_clockpowergating.c +8 −8
  196. drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c +195 −183
  197. drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.h +2 −1
  198. drivers/gpu/drm/amd/powerplay/hwmgr/smu7_powertune.c +197 −9
  199. drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c +14 −23
  200. drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.c +98 −0
  201. drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.h +27 −0
  202. drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c +452 −499
  203. drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.h +14 −12
  204. drivers/gpu/drm/amd/powerplay/hwmgr/vega10_powertune.c +59 −62
  205. drivers/gpu/drm/amd/powerplay/hwmgr/vega10_processpptables.c +1 −1
  206. drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c +41 −66
  207. drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c +63 −32
  208. drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.h +1 −1
  209. drivers/gpu/drm/amd/powerplay/hwmgr/vega12_processpptables.c +6 −1
  210. drivers/gpu/drm/amd/powerplay/hwmgr/vega12_thermal.c +15 −22
  211. drivers/gpu/drm/amd/powerplay/inc/hardwaremanager.h +1 −5
  212. drivers/gpu/drm/amd/powerplay/inc/hwmgr.h +11 −21
  213. drivers/gpu/drm/amd/powerplay/inc/rv_ppsmc.h +3 −1
  214. drivers/gpu/drm/amd/powerplay/inc/smu75.h +760 −0
  215. drivers/gpu/drm/amd/powerplay/inc/smu75_discrete.h +886 −0
  216. drivers/gpu/drm/amd/powerplay/inc/vega10_ppsmc.h +1 −0
  217. drivers/gpu/drm/amd/powerplay/smumgr/Makefile +1 −1
  218. drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c +2 −10
  219. drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c +10 −14
  220. drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c +2 −7
  221. drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c +6 −19
  222. drivers/gpu/drm/amd/powerplay/smumgr/smu10_smumgr.c +13 −26
  223. drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c +13 −27
  224. drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.h +0 −1
  225. drivers/gpu/drm/amd/powerplay/smumgr/smumgr.c +1 −0
  226. drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c +6 −13
  227. drivers/gpu/drm/amd/powerplay/smumgr/vega10_smumgr.c +17 −35
  228. drivers/gpu/drm/amd/powerplay/smumgr/vega12_smumgr.c +19 −37
  229. drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c +2382 −0
  230. drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.h +75 −0
  231. drivers/gpu/drm/etnaviv/etnaviv_drv.c +1 −1
  232. drivers/gpu/drm/radeon/atombios_crtc.c +9 −23
  233. drivers/gpu/drm/radeon/radeon_atpx_handler.c +1 −1
  234. drivers/gpu/drm/radeon/radeon_connectors.c +5 −5
  235. drivers/gpu/drm/radeon/radeon_device.c +3 −3
  236. drivers/gpu/drm/radeon/radeon_display.c +16 −37
  237. drivers/gpu/drm/radeon/radeon_drv.c +5 −0
  238. drivers/gpu/drm/radeon/radeon_fb.c +10 −10
  239. drivers/gpu/drm/radeon/radeon_legacy_crtc.c +6 −14
  240. drivers/gpu/drm/radeon/radeon_mode.h +1 −7
  241. drivers/gpu/drm/scheduler/gpu_scheduler.c +61 −15
  242. drivers/gpu/drm/scheduler/gpu_scheduler_trace.h +1 −1
  243. drivers/gpu/drm/ttm/ttm_agp_backend.c +1 −0
  244. drivers/gpu/drm/ttm/ttm_bo.c +1 −1
  245. drivers/gpu/drm/ttm/ttm_bo_manager.c +1 −0
  246. drivers/gpu/drm/ttm/ttm_bo_util.c +31 −20
  247. drivers/gpu/drm/ttm/ttm_bo_vm.c +1 −0
  248. drivers/gpu/drm/ttm/ttm_execbuf_util.c +1 −0
  249. drivers/gpu/drm/ttm/ttm_lock.c +1 −0
  250. drivers/gpu/drm/ttm/ttm_memory.c +1 −0
  251. drivers/gpu/drm/ttm/ttm_module.c +1 −0
  252. drivers/gpu/drm/ttm/ttm_object.c +1 −0
  253. drivers/gpu/drm/ttm/ttm_page_alloc.c +8 −3
  254. drivers/gpu/drm/ttm/ttm_page_alloc_dma.c +2 −1
  255. drivers/gpu/drm/ttm/ttm_tt.c +1 −0
  256. drivers/gpu/drm/v3d/v3d_drv.c +1 −1
  257. include/drm/amd_asic_type.h +1 −0
  258. include/drm/gpu_scheduler.h +50 −5
  259. include/uapi/drm/amdgpu_drm.h +20 −0
drivers/gpu/drm/amd/amdgpu/Makefile+4−0
@@ -64,6 +64,10 @@ amdgpu-$(CONFIG_DRM_AMDGPU_SI)+= si.o gmc_v6_0.o gfx_v6_0.o si_ih.o si_dma.o dce · 63 unmodified lines
6464 amdgpu-y += \
6565 vi.o mxgpu_vi.o nbio_v6_1.o soc15.o emu_soc.o mxgpu_ai.o nbio_v7_0.o vega10_reg_init.o
6666
67+# add DF block
68+amdgpu-y += \
69+ df_v1_7.o
70+
6771 # add GMC block
6872 amdgpu-y += \
6973 gmc_v7_0.o \
drivers/gpu/drm/amd/amdgpu/amdgpu.h+40−3
@@ -129,6 +129,7 @@ extern int amdgpu_lbpw; · 128 unmodified lines
129129 extern int amdgpu_compute_multipipe;
130130 extern int amdgpu_gpu_recovery;
131131 extern int amdgpu_emu_mode;
132+extern uint amdgpu_smu_memory_pool_size;
132133
133134 #ifdef CONFIG_DRM_AMDGPU_SI
134135 extern int amdgpu_si_support;
@@ -137,6 +138,7 @@ extern int amdgpu_si_support; · 2 unmodified lines
137138 extern int amdgpu_cik_support;
138139 #endif
139140
141+#define AMDGPU_SG_THRESHOLD (256*1024*1024)
140142 #define AMDGPU_DEFAULT_GTT_SIZE_MB 3072ULL /* 3GB by default */
141143 #define AMDGPU_WAIT_IDLE_TIMEOUT_IN_MS 3000
142144 #define AMDGPU_MAX_USEC_TIMEOUT 100000 /* 100 ms */
@@ -222,10 +224,10 @@ enum amdgpu_kiq_irq { · 79 unmodified lines
222224 AMDGPU_CP_KIQ_IRQ_LAST
223225 };
224226
225−int amdgpu_device_ip_set_clockgating_state(struct amdgpu_device *adev,
227+int amdgpu_device_ip_set_clockgating_state(void *dev,
226228 enum amd_ip_block_type block_type,
227229 enum amd_clockgating_state state);
228−int amdgpu_device_ip_set_powergating_state(struct amdgpu_device *adev,
230+int amdgpu_device_ip_set_powergating_state(void *dev,
229231 enum amd_ip_block_type block_type,
230232 enum amd_powergating_state state);
231233 void amdgpu_device_ip_get_clockgating_state(struct amdgpu_device *adev,
@@ -681,6 +683,8 @@ int amdgpu_ctx_ioctl(struct drm_device *dev, void *data, · 449 unmodified lines
681683 int amdgpu_ctx_wait_prev_fence(struct amdgpu_ctx *ctx, unsigned ring_id);
682684
683685 void amdgpu_ctx_mgr_init(struct amdgpu_ctx_mgr *mgr);
686+void amdgpu_ctx_mgr_entity_cleanup(struct amdgpu_ctx_mgr *mgr);
687+void amdgpu_ctx_mgr_entity_fini(struct amdgpu_ctx_mgr *mgr);
684688 void amdgpu_ctx_mgr_fini(struct amdgpu_ctx_mgr *mgr);
685689
686690
@@ -771,9 +775,18 @@ struct amdgpu_rlc { · 84 unmodified lines
771775 u32 starting_offsets_start;
772776 u32 reg_list_format_size_bytes;
773777 u32 reg_list_size_bytes;
778+ u32 reg_list_format_direct_reg_list_length;
779+ u32 save_restore_list_cntl_size_bytes;
780+ u32 save_restore_list_gpm_size_bytes;
781+ u32 save_restore_list_srm_size_bytes;
774782
775783 u32 *register_list_format;
776784 u32 *register_restore;
785+ u8 *save_restore_list_cntl;
786+ u8 *save_restore_list_gpm;
787+ u8 *save_restore_list_srm;
788+
789+ bool is_rlc_v2_1;
777790 };
778791
779792 #define AMDGPU_MAX_COMPUTE_QUEUES KGD_MAX_QUEUES
@@ -867,6 +880,8 @@ struct amdgpu_gfx_config { · 87 unmodified lines
867880
868881 /* gfx configure feature */
869882 uint32_t double_offchip_lds_buf;
883+ /* cached value of DB_DEBUG2 */
884+ uint32_t db_debug2;
870885 };
871886
872887 struct amdgpu_cu_info {
@@ -938,6 +953,12 @@ struct amdgpu_gfx { · 65 unmodified lines
938953 uint32_t ce_feature_version;
939954 uint32_t pfp_feature_version;
940955 uint32_t rlc_feature_version;
956+ uint32_t rlc_srlc_fw_version;
957+ uint32_t rlc_srlc_feature_version;
958+ uint32_t rlc_srlg_fw_version;
959+ uint32_t rlc_srlg_feature_version;
960+ uint32_t rlc_srls_fw_version;
961+ uint32_t rlc_srls_feature_version;
941962 uint32_t mec_feature_version;
942963 uint32_t mec2_feature_version;
943964 struct amdgpu_ring gfx_ring[AMDGPU_MAX_GFX_RINGS];
@@ -1204,6 +1225,8 @@ struct amdgpu_asic_funcs { · 260 unmodified lines
12041225 /* invalidate hdp read cache */
12051226 void (*invalidate_hdp)(struct amdgpu_device *adev,
12061227 struct amdgpu_ring *ring);
1228+ /* check if the asic needs a full reset of if soft reset will work */
1229+ bool (*need_full_reset)(struct amdgpu_device *adev);
12071230 };
12081231
12091232 /*
@@ -1368,7 +1391,17 @@ struct amdgpu_nbio_funcs { · 158 unmodified lines
13681391 void (*detect_hw_virt)(struct amdgpu_device *adev);
13691392 };
13701393
1371−
1394+struct amdgpu_df_funcs {
1395+ void (*init)(struct amdgpu_device *adev);
1396+ void (*enable_broadcast_mode)(struct amdgpu_device *adev,
1397+ bool enable);
1398+ u32 (*get_fb_channel_number)(struct amdgpu_device *adev);
1399+ u32 (*get_hbm_channel_number)(struct amdgpu_device *adev);
1400+ void (*update_medium_grain_clock_gating)(struct amdgpu_device *adev,
1401+ bool enable);
1402+ void (*get_clockgating_state)(struct amdgpu_device *adev,
1403+ u32 *flags);
1404+};
13721405 /* Define the HW IP blocks will be used in driver , add more if necessary */
13731406 enum amd_hw_ip_block_type {
13741407 GC_HWIP = 1,
@@ -1398,6 +1431,7 @@ enum amd_hw_ip_block_type { · 23 unmodified lines
13981431 struct amd_powerplay {
13991432 void *pp_handle;
14001433 const struct amd_pm_funcs *pp_funcs;
1434+ uint32_t pp_feature;
14011435 };
14021436
14031437 #define AMDGPU_RESET_MAGIC_NUM 64
@@ -1590,6 +1624,7 @@ struct amdgpu_device { · 186 unmodified lines
15901624 uint32_t *reg_offset[MAX_HWIP][HWIP_MAX_INSTANCE];
15911625
15921626 const struct amdgpu_nbio_funcs *nbio_funcs;
1627+ const struct amdgpu_df_funcs *df_funcs;
15931628
15941629 /* delayed work_func for deferring clockgating during resume */
15951630 struct delayed_work late_init_work;
@@ -1764,6 +1799,7 @@ amdgpu_get_sdma_instance(struct amdgpu_ring *ring) · 168 unmodified lines
17641799 #define amdgpu_asic_get_config_memsize(adev) (adev)->asic_funcs->get_config_memsize((adev))
17651800 #define amdgpu_asic_flush_hdp(adev, r) (adev)->asic_funcs->flush_hdp((adev), (r))
17661801 #define amdgpu_asic_invalidate_hdp(adev, r) (adev)->asic_funcs->invalidate_hdp((adev), (r))
1802+#define amdgpu_asic_need_full_reset(adev) (adev)->asic_funcs->need_full_reset((adev))
17671803 #define amdgpu_gmc_flush_gpu_tlb(adev, vmid) (adev)->gmc.gmc_funcs->flush_gpu_tlb((adev), (vmid))
17681804 #define amdgpu_gmc_emit_flush_gpu_tlb(r, vmid, addr) (r)->adev->gmc.gmc_funcs->emit_flush_gpu_tlb((r), (vmid), (addr))
17691805 #define amdgpu_gmc_emit_pasid_mapping(r, vmid, pasid) (r)->adev->gmc.gmc_funcs->emit_pasid_mapping((r), (vmid), (pasid))
@@ -1790,6 +1826,7 @@ amdgpu_get_sdma_instance(struct amdgpu_ring *ring) · 20 unmodified lines
17901826 #define amdgpu_ring_emit_rreg(r, d) (r)->funcs->emit_rreg((r), (d))
17911827 #define amdgpu_ring_emit_wreg(r, d, v) (r)->funcs->emit_wreg((r), (d), (v))
17921828 #define amdgpu_ring_emit_reg_wait(r, d, v, m) (r)->funcs->emit_reg_wait((r), (d), (v), (m))
1829+#define amdgpu_ring_emit_reg_write_reg_wait(r, d0, d1, v, m) (r)->funcs->emit_reg_write_reg_wait((r), (d0), (d1), (v), (m))
17931830 #define amdgpu_ring_emit_tmz(r, b) (r)->funcs->emit_tmz((r), (b))
17941831 #define amdgpu_ring_pad_ib(r, ib) ((r)->funcs->pad_ib((r), (ib)))
17951832 #define amdgpu_ring_init_cond_exec(r) (r)->funcs->init_cond_exec((r))
drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c+5−6
@@ -290,12 +290,11 @@ static int acp_hw_init(void *handle) · 289 unmodified lines
290290 else if (r)
291291 return r;
292292
293− r = cgs_get_pci_resource(adev->acp.cgs_device, CGS_RESOURCE_TYPE_MMIO,
294− 0x5289, 0, &acp_base);
295− if (r == -ENODEV)
296− return 0;
297− else if (r)
298− return r;
293+ if (adev->rmmio_size == 0 || adev->rmmio_size < 0x5289)
294+ return -EINVAL;
295+
296+ acp_base = adev->rmmio_base;
297+
299298 if (adev->asic_type != CHIP_STONEY) {
300299 adev->acp.acp_genpd = kzalloc(sizeof(struct acp_pm_domain), GFP_KERNEL);
301300 if (adev->acp.acp_genpd == NULL)
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c+9−3
@@ -243,13 +243,19 @@ int alloc_gtt_mem(struct kgd_dev *kgd, size_t size, · 242 unmodified lines
243243 {
244244 struct amdgpu_device *adev = (struct amdgpu_device *)kgd;
245245 struct amdgpu_bo *bo = NULL;
246+ struct amdgpu_bo_param bp;
246247 int r;
247248 uint64_t gpu_addr_tmp = 0;
248249 void *cpu_ptr_tmp = NULL;
249250
250− r = amdgpu_bo_create(adev, size, PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT,
251− AMDGPU_GEM_CREATE_CPU_GTT_USWC, ttm_bo_type_kernel,
252− NULL, &bo);
251+ memset(&bp, 0, sizeof(bp));
252+ bp.size = size;
253+ bp.byte_align = PAGE_SIZE;
254+ bp.domain = AMDGPU_GEM_DOMAIN_GTT;
255+ bp.flags = AMDGPU_GEM_CREATE_CPU_GTT_USWC;
256+ bp.type = ttm_bo_type_kernel;
257+ bp.resv = NULL;
258+ r = amdgpu_bo_create(adev, &bp, &bo);
253259 if (r) {
254260 dev_err(adev->dev,
255261 "failed to allocate BO for amdkfd (%d)\n", r);
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c+9−2
@@ -1143,6 +1143,7 @@ int amdgpu_amdkfd_gpuvm_alloc_memory_of_gpu( · 1142 unmodified lines
11431143 struct amdgpu_vm *avm = (struct amdgpu_vm *)vm;
11441144 uint64_t user_addr = 0;
11451145 struct amdgpu_bo *bo;
1146+ struct amdgpu_bo_param bp;
11461147 int byte_align;
11471148 u32 domain, alloc_domain;
11481149 u64 alloc_flags;
@@ -1215,8 +1216,14 @@ int amdgpu_amdkfd_gpuvm_alloc_memory_of_gpu( · 66 unmodified lines
12151216 pr_debug("\tcreate BO VA 0x%llx size 0x%llx domain %s\n",
12161217 va, size, domain_string(alloc_domain));
12171218
1218− ret = amdgpu_bo_create(adev, size, byte_align,
1219− alloc_domain, alloc_flags, ttm_bo_type_device, NULL, &bo);
1219+ memset(&bp, 0, sizeof(bp));
1220+ bp.size = size;
1221+ bp.byte_align = byte_align;
1222+ bp.domain = alloc_domain;
1223+ bp.flags = alloc_flags;
1224+ bp.type = ttm_bo_type_device;
1225+ bp.resv = NULL;
1226+ ret = amdgpu_bo_create(adev, &bp, &bo);
12201227 if (ret) {
12211228 pr_debug("Failed to create BO on domain %s. ret %d\n",
12221229 domain_string(alloc_domain), ret);
drivers/gpu/drm/amd/amdgpu/amdgpu_atpx_handler.c+1−1
@@ -550,7 +550,7 @@ static int amdgpu_atpx_init(void) · 549 unmodified lines
550550 * look up whether we are the integrated or discrete GPU (all asics).
551551 * Returns the client id.
552552 */
553−static int amdgpu_atpx_get_client_id(struct pci_dev *pdev)
553+static enum vga_switcheroo_client_id amdgpu_atpx_get_client_id(struct pci_dev *pdev)
554554 {
555555 if (amdgpu_atpx_priv.dhandle == ACPI_HANDLE(&pdev->dev))
556556 return VGA_SWITCHEROO_IGD;
drivers/gpu/drm/amd/amdgpu/amdgpu_benchmark.c+11−4
@@ -75,13 +75,20 @@ static void amdgpu_benchmark_move(struct amdgpu_device *adev, unsigned size, · 74 unmodified lines
7575 {
7676 struct amdgpu_bo *dobj = NULL;
7777 struct amdgpu_bo *sobj = NULL;
78+ struct amdgpu_bo_param bp;
7879 uint64_t saddr, daddr;
7980 int r, n;
8081 int time;
8182
83+ memset(&bp, 0, sizeof(bp));
84+ bp.size = size;
85+ bp.byte_align = PAGE_SIZE;
86+ bp.domain = sdomain;
87+ bp.flags = 0;
88+ bp.type = ttm_bo_type_kernel;
89+ bp.resv = NULL;
8290 n = AMDGPU_BENCHMARK_ITERATIONS;
83− r = amdgpu_bo_create(adev, size, PAGE_SIZE,sdomain, 0,
84− ttm_bo_type_kernel, NULL, &sobj);
91+ r = amdgpu_bo_create(adev, &bp, &sobj);
8592 if (r) {
8693 goto out_cleanup;
8794 }
@@ -93,8 +100,8 @@ static void amdgpu_benchmark_move(struct amdgpu_device *adev, unsigned size, · 5 unmodified lines
93100 if (r) {
94101 goto out_cleanup;
95102 }
96− r = amdgpu_bo_create(adev, size, PAGE_SIZE, ddomain, 0,
97− ttm_bo_type_kernel, NULL, &dobj);
103+ bp.domain = ddomain;
104+ r = amdgpu_bo_create(adev, &bp, &dobj);
98105 if (r) {
99106 goto out_cleanup;
100107 }
drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c+3−241
@@ -23,7 +23,6 @@ · 22 unmodified lines
2323 */
2424 #include <linux/list.h>
2525 #include <linux/slab.h>
26−#include <linux/pci.h>
2726 #include <drm/drmP.h>
2827 #include <linux/firmware.h>
2928 #include <drm/amdgpu_drm.h>
@@ -109,121 +108,6 @@ static void amdgpu_cgs_write_ind_register(struct cgs_device *cgs_device, · 79 unmodified lines
109108 WARN(1, "Invalid indirect register space");
110109 }
111110
112−static int amdgpu_cgs_get_pci_resource(struct cgs_device *cgs_device,
113− enum cgs_resource_type resource_type,
114− uint64_t size,
115− uint64_t offset,
116− uint64_t *resource_base)
117−{
118− CGS_FUNC_ADEV;
119−
120− if (resource_base == NULL)
121− return -EINVAL;
122−
123− switch (resource_type) {
124− case CGS_RESOURCE_TYPE_MMIO:
125− if (adev->rmmio_size == 0)
126− return -ENOENT;
127− if ((offset + size) > adev->rmmio_size)
128− return -EINVAL;
129− *resource_base = adev->rmmio_base;
130− return 0;
131− case CGS_RESOURCE_TYPE_DOORBELL:
132− if (adev->doorbell.size == 0)
133− return -ENOENT;
134− if ((offset + size) > adev->doorbell.size)
135− return -EINVAL;
136− *resource_base = adev->doorbell.base;
137− return 0;
138− case CGS_RESOURCE_TYPE_FB:
139− case CGS_RESOURCE_TYPE_IO:
140− case CGS_RESOURCE_TYPE_ROM:
141− default:
142− return -EINVAL;
143− }
144−}
145−
146−static const void *amdgpu_cgs_atom_get_data_table(struct cgs_device *cgs_device,
147− unsigned table, uint16_t *size,
148− uint8_t *frev, uint8_t *crev)
149−{
150− CGS_FUNC_ADEV;
151− uint16_t data_start;
152−
153− if (amdgpu_atom_parse_data_header(
154− adev->mode_info.atom_context, table, size,
155− frev, crev, &data_start))
156− return (uint8_t*)adev->mode_info.atom_context->bios +
157− data_start;
158−
159− return NULL;
160−}
161−
162−static int amdgpu_cgs_atom_get_cmd_table_revs(struct cgs_device *cgs_device, unsigned table,
163− uint8_t *frev, uint8_t *crev)
164−{
165− CGS_FUNC_ADEV;
166−
167− if (amdgpu_atom_parse_cmd_header(
168− adev->mode_info.atom_context, table,
169− frev, crev))
170− return 0;
171−
172− return -EINVAL;
173−}
174−
175−static int amdgpu_cgs_atom_exec_cmd_table(struct cgs_device *cgs_device, unsigned table,
176− void *args)
177−{
178− CGS_FUNC_ADEV;
179−
180− return amdgpu_atom_execute_table(
181− adev->mode_info.atom_context, table, args);
182−}
183−
184−static int amdgpu_cgs_set_clockgating_state(struct cgs_device *cgs_device,
185− enum amd_ip_block_type block_type,
186− enum amd_clockgating_state state)
187−{
188− CGS_FUNC_ADEV;
189− int i, r = -1;
190−
191− for (i = 0; i < adev->num_ip_blocks; i++) {
192− if (!adev->ip_blocks[i].status.valid)
193− continue;
194−
195− if (adev->ip_blocks[i].version->type == block_type) {
196− r = adev->ip_blocks[i].version->funcs->set_clockgating_state(
197− (void *)adev,
198− state);
199− break;
200− }
201− }
202− return r;
203−}
204−
205−static int amdgpu_cgs_set_powergating_state(struct cgs_device *cgs_device,
206− enum amd_ip_block_type block_type,
207− enum amd_powergating_state state)
208−{
209− CGS_FUNC_ADEV;
210− int i, r = -1;
211−
212− for (i = 0; i < adev->num_ip_blocks; i++) {
213− if (!adev->ip_blocks[i].status.valid)
214− continue;
215−
216− if (adev->ip_blocks[i].version->type == block_type) {
217− r = adev->ip_blocks[i].version->funcs->set_powergating_state(
218− (void *)adev,
219− state);
220− break;
221− }
222− }
223− return r;
224−}
225−
226−
227111 static uint32_t fw_type_convert(struct cgs_device *cgs_device, uint32_t fw_type)
228112 {
229113 CGS_FUNC_ADEV;
@@ -271,18 +155,6 @@ static uint32_t fw_type_convert(struct cgs_device *cgs_device, uint32_t fw_type) · 41 unmodified lines
271155 return result;
272156 }
273157
274−static int amdgpu_cgs_rel_firmware(struct cgs_device *cgs_device, enum cgs_ucode_id type)
275−{
276− CGS_FUNC_ADEV;
277− if ((CGS_UCODE_ID_SMU == type) || (CGS_UCODE_ID_SMU_SK == type)) {
278− release_firmware(adev->pm.fw);
279− adev->pm.fw = NULL;
280− return 0;
281− }
282− /* cannot release other firmware because they are not created by cgs */
283− return -EINVAL;
284−}
285−
286158 static uint16_t amdgpu_get_firmware_version(struct cgs_device *cgs_device,
287159 enum cgs_ucode_id type)
288160 {
@@ -326,34 +198,6 @@ static uint16_t amdgpu_get_firmware_version(struct cgs_device *cgs_device, · 37 unmodified lines
326198 return fw_version;
327199 }
328200
329−static int amdgpu_cgs_enter_safe_mode(struct cgs_device *cgs_device,
330− bool en)
331−{
332− CGS_FUNC_ADEV;
333−
334− if (adev->gfx.rlc.funcs->enter_safe_mode == NULL ||
335− adev->gfx.rlc.funcs->exit_safe_mode == NULL)
336− return 0;
337−
338− if (en)
339− adev->gfx.rlc.funcs->enter_safe_mode(adev);
340− else
341− adev->gfx.rlc.funcs->exit_safe_mode(adev);
342−
343− return 0;
344−}
345−
346−static void amdgpu_cgs_lock_grbm_idx(struct cgs_device *cgs_device,
347− bool lock)
348−{
349− CGS_FUNC_ADEV;
350−
351− if (lock)
352− mutex_lock(&adev->grbm_idx_mutex);
353− else
354− mutex_unlock(&adev->grbm_idx_mutex);
355−}
356−
357201 static int amdgpu_cgs_get_firmware_info(struct cgs_device *cgs_device,
358202 enum cgs_ucode_id type,
359203 struct cgs_firmware_info *info)
@@ -541,6 +385,9 @@ static int amdgpu_cgs_get_firmware_info(struct cgs_device *cgs_device, · 181 unmodified lines
541385 case CHIP_POLARIS12:
542386 strcpy(fw_name, "amdgpu/polaris12_smc.bin");
543387 break;
388+ case CHIP_VEGAM:
389+ strcpy(fw_name, "amdgpu/vegam_smc.bin");
390+ break;
544391 case CHIP_VEGA10:
545392 if ((adev->pdev->device == 0x687f) &&
546393 ((adev->pdev->revision == 0xc0) ||
@@ -598,97 +445,12 @@ static int amdgpu_cgs_get_firmware_info(struct cgs_device *cgs_device, · 51 unmodified lines
598445 return 0;
599446 }
600447
601−static int amdgpu_cgs_is_virtualization_enabled(void *cgs_device)
602−{
603− CGS_FUNC_ADEV;
604− return amdgpu_sriov_vf(adev);
605−}
606−
607−static int amdgpu_cgs_get_active_displays_info(struct cgs_device *cgs_device,
608− struct cgs_display_info *info)
609−{
610− CGS_FUNC_ADEV;
611− struct cgs_mode_info *mode_info;
612−
613− if (info == NULL)
614− return -EINVAL;
615−
616− mode_info = info->mode_info;
617− if (mode_info)
618− /* if the displays are off, vblank time is max */
619− mode_info->vblank_time_us = 0xffffffff;
620−
621− if (!amdgpu_device_has_dc_support(adev)) {
622− struct amdgpu_crtc *amdgpu_crtc;
623− struct drm_device *ddev = adev->ddev;
624− struct drm_crtc *crtc;
625− uint32_t line_time_us, vblank_lines;
626−
627− if (adev->mode_info.num_crtc && adev->mode_info.mode_config_initialized) {
628− list_for_each_entry(crtc,
629− &ddev->mode_config.crtc_list, head) {
630− amdgpu_crtc = to_amdgpu_crtc(crtc);
631− if (crtc->enabled) {
632− info->active_display_mask |= (1 << amdgpu_crtc->crtc_id);
633− info->display_count++;
634− }
635− if (mode_info != NULL &&
636− crtc->enabled && amdgpu_crtc->enabled &&
637− amdgpu_crtc->hw_mode.clock) {
638− line_time_us = (amdgpu_crtc->hw_mode.crtc_htotal * 1000) /
639− amdgpu_crtc->hw_mode.clock;
640− vblank_lines = amdgpu_crtc->hw_mode.crtc_vblank_end -
641− amdgpu_crtc->hw_mode.crtc_vdisplay +
642− (amdgpu_crtc->v_border * 2);
643− mode_info->vblank_time_us = vblank_lines * line_time_us;
644− mode_info->refresh_rate = drm_mode_vrefresh(&amdgpu_crtc->hw_mode);
645− /* we have issues with mclk switching with refresh rates
646− * over 120 hz on the non-DC code.
647− */
648− if (mode_info->refresh_rate > 120)
649− mode_info->vblank_time_us = 0;
650− mode_info = NULL;
651− }
652− }
653− }
654− } else {
655− info->display_count = adev->pm.pm_display_cfg.num_display;
656− if (mode_info != NULL) {
657− mode_info->vblank_time_us = adev->pm.pm_display_cfg.min_vblank_time;
658− mode_info->refresh_rate = adev->pm.pm_display_cfg.vrefresh;
659− }
660− }
661− return 0;
662−}
663−
664−
665−static int amdgpu_cgs_notify_dpm_enabled(struct cgs_device *cgs_device, bool enabled)
666−{
667− CGS_FUNC_ADEV;
668−
669− adev->pm.dpm_enabled = enabled;
670−
671− return 0;
672−}
673−
674448 static const struct cgs_ops amdgpu_cgs_ops = {
675449 .read_register = amdgpu_cgs_read_register,
676450 .write_register = amdgpu_cgs_write_register,
677451 .read_ind_register = amdgpu_cgs_read_ind_register,
678452 .write_ind_register = amdgpu_cgs_write_ind_register,
679− .get_pci_resource = amdgpu_cgs_get_pci_resource,
680− .atom_get_data_table = amdgpu_cgs_atom_get_data_table,
681− .atom_get_cmd_table_revs = amdgpu_cgs_atom_get_cmd_table_revs,
682− .atom_exec_cmd_table = amdgpu_cgs_atom_exec_cmd_table,
683453 .get_firmware_info = amdgpu_cgs_get_firmware_info,
684− .rel_firmware = amdgpu_cgs_rel_firmware,
685− .set_powergating_state = amdgpu_cgs_set_powergating_state,
686− .set_clockgating_state = amdgpu_cgs_set_clockgating_state,
687− .get_active_displays_info = amdgpu_cgs_get_active_displays_info,
688− .notify_dpm_enabled = amdgpu_cgs_notify_dpm_enabled,
689− .is_virtualization_enabled = amdgpu_cgs_is_virtualization_enabled,
690− .enter_safe_mode = amdgpu_cgs_enter_safe_mode,
691− .lock_grbm_idx = amdgpu_cgs_lock_grbm_idx,
692454 };
693455
694456 struct cgs_device *amdgpu_cgs_create_device(struct amdgpu_device *adev)
drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c+4−4
@@ -691,7 +691,7 @@ static int amdgpu_connector_lvds_get_modes(struct drm_connector *connector) · 690 unmodified lines
691691 return ret;
692692 }
693693
694−static int amdgpu_connector_lvds_mode_valid(struct drm_connector *connector,
694+static enum drm_mode_status amdgpu_connector_lvds_mode_valid(struct drm_connector *connector,
695695 struct drm_display_mode *mode)
696696 {
697697 struct drm_encoder *encoder = amdgpu_connector_best_single_encoder(connector);
@@ -843,7 +843,7 @@ static int amdgpu_connector_vga_get_modes(struct drm_connector *connector) · 145 unmodified lines
843843 return ret;
844844 }
845845
846−static int amdgpu_connector_vga_mode_valid(struct drm_connector *connector,
846+static enum drm_mode_status amdgpu_connector_vga_mode_valid(struct drm_connector *connector,
847847 struct drm_display_mode *mode)
848848 {
849849 struct drm_device *dev = connector->dev;
@@ -1172,7 +1172,7 @@ static void amdgpu_connector_dvi_force(struct drm_connector *connector) · 322 unmodified lines
11721172 amdgpu_connector->use_digital = true;
11731173 }
11741174
1175−static int amdgpu_connector_dvi_mode_valid(struct drm_connector *connector,
1175+static enum drm_mode_status amdgpu_connector_dvi_mode_valid(struct drm_connector *connector,
11761176 struct drm_display_mode *mode)
11771177 {
11781178 struct drm_device *dev = connector->dev;
@@ -1448,7 +1448,7 @@ out: · 269 unmodified lines
14481448 return ret;
14491449 }
14501450
1451−static int amdgpu_connector_dp_mode_valid(struct drm_connector *connector,
1451+static enum drm_mode_status amdgpu_connector_dp_mode_valid(struct drm_connector *connector,
14521452 struct drm_display_mode *mode)
14531453 {
14541454 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c+5−11
@@ -382,8 +382,7 @@ retry: · 381 unmodified lines
382382
383383 p->bytes_moved += ctx.bytes_moved;
384384 if (adev->gmc.visible_vram_size < adev->gmc.real_vram_size &&
385− bo->tbo.mem.mem_type == TTM_PL_VRAM &&
386− bo->tbo.mem.start < adev->gmc.visible_vram_size >> PAGE_SHIFT)
385+ amdgpu_bo_in_cpu_visible_vram(bo))
387386 p->bytes_moved_vis += ctx.bytes_moved;
388387
389388 if (unlikely(r == -ENOMEM) && domain != bo->allowed_domains) {
@@ -411,7 +410,6 @@ static bool amdgpu_cs_try_evict(struct amdgpu_cs_parser *p, · 21 unmodified lines
411410 struct amdgpu_bo_list_entry *candidate = p->evictable;
412411 struct amdgpu_bo *bo = candidate->robj;
413412 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
414− u64 initial_bytes_moved, bytes_moved;
415413 bool update_bytes_moved_vis;
416414 uint32_t other;
417415
@@ -435,18 +433,14 @@ static bool amdgpu_cs_try_evict(struct amdgpu_cs_parser *p, · 17 unmodified lines
435433 continue;
436434
437435 /* Good we can try to move this BO somewhere else */
438− amdgpu_ttm_placement_from_domain(bo, other);
439436 update_bytes_moved_vis =
440437 adev->gmc.visible_vram_size < adev->gmc.real_vram_size &&
441− bo->tbo.mem.mem_type == TTM_PL_VRAM &&
442− bo->tbo.mem.start < adev->gmc.visible_vram_size >> PAGE_SHIFT;
443− initial_bytes_moved = atomic64_read(&adev->num_bytes_moved);
438+ amdgpu_bo_in_cpu_visible_vram(bo);
439+ amdgpu_ttm_placement_from_domain(bo, other);
444440 r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
445− bytes_moved = atomic64_read(&adev->num_bytes_moved) -
446− initial_bytes_moved;
447− p->bytes_moved += bytes_moved;
441+ p->bytes_moved += ctx.bytes_moved;
448442 if (update_bytes_moved_vis)
449− p->bytes_moved_vis += bytes_moved;
443+ p->bytes_moved_vis += ctx.bytes_moved;
450444
451445 if (unlikely(r))
452446 break;
drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c+61−11
@@ -91,7 +91,7 @@ static int amdgpu_ctx_init(struct amdgpu_device *adev, · 90 unmodified lines
9191 continue;
9292
9393 r = drm_sched_entity_init(&ring->sched, &ctx->rings[i].entity,
94− rq, amdgpu_sched_jobs, &ctx->guilty);
94+ rq, &ctx->guilty);
9595 if (r)
9696 goto failed;
9797 }
@@ -111,8 +111,9 @@ failed: · 13 unmodified lines
111111 return r;
112112 }
113113
114−static void amdgpu_ctx_fini(struct amdgpu_ctx *ctx)
114+static void amdgpu_ctx_fini(struct kref *ref)
115115 {
116+ struct amdgpu_ctx *ctx = container_of(ref, struct amdgpu_ctx, refcount);
116117 struct amdgpu_device *adev = ctx->adev;
117118 unsigned i, j;
118119
@@ -125,13 +126,11 @@ static void amdgpu_ctx_fini(struct amdgpu_ctx *ctx) · 6 unmodified lines
125126 kfree(ctx->fences);
126127 ctx->fences = NULL;
127128
128− for (i = 0; i < adev->num_rings; i++)
129− drm_sched_entity_fini(&adev->rings[i]->sched,
130− &ctx->rings[i].entity);
131−
132129 amdgpu_queue_mgr_fini(adev, &ctx->queue_mgr);
133130
134131 mutex_destroy(&ctx->lock);
132+
133+ kfree(ctx);
135134 }
136135
137136 static int amdgpu_ctx_alloc(struct amdgpu_device *adev,
@@ -170,12 +169,15 @@ static int amdgpu_ctx_alloc(struct amdgpu_device *adev, · 32 unmodified lines
170169 static void amdgpu_ctx_do_release(struct kref *ref)
171170 {
172171 struct amdgpu_ctx *ctx;
172+ u32 i;
173173
174174 ctx = container_of(ref, struct amdgpu_ctx, refcount);
175175
176− amdgpu_ctx_fini(ctx);
176+ for (i = 0; i < ctx->adev->num_rings; i++)
177+ drm_sched_entity_fini(&ctx->adev->rings[i]->sched,
178+ &ctx->rings[i].entity);
177179
178− kfree(ctx);
180+ amdgpu_ctx_fini(ref);
179181 }
180182
181183 static int amdgpu_ctx_free(struct amdgpu_fpriv *fpriv, uint32_t id)
@@ -419,9 +421,11 @@ int amdgpu_ctx_wait_prev_fence(struct amdgpu_ctx *ctx, unsigned ring_id) · 237 unmodified lines
419421
420422 if (other) {
421423 signed long r;
422− r = dma_fence_wait_timeout(other, false, MAX_SCHEDULE_TIMEOUT);
424+ r = dma_fence_wait(other, true);
423425 if (r < 0) {
424− DRM_ERROR("Error (%ld) waiting for fence!\n", r);
426+ if (r != -ERESTARTSYS)
427+ DRM_ERROR("Error (%ld) waiting for fence!\n", r);
428+
425429 return r;
426430 }
427431 }
@@ -435,16 +439,62 @@ void amdgpu_ctx_mgr_init(struct amdgpu_ctx_mgr *mgr) · 7 unmodified lines
435439 idr_init(&mgr->ctx_handles);
436440 }
437441
442+void amdgpu_ctx_mgr_entity_fini(struct amdgpu_ctx_mgr *mgr)
443+{
444+ struct amdgpu_ctx *ctx;
445+ struct idr *idp;
446+ uint32_t id, i;
447+
448+ idp = &mgr->ctx_handles;
449+
450+ idr_for_each_entry(idp, ctx, id) {
451+
452+ if (!ctx->adev)
453+ return;
454+
455+ for (i = 0; i < ctx->adev->num_rings; i++)
456+ if (kref_read(&ctx->refcount) == 1)
457+ drm_sched_entity_do_release(&ctx->adev->rings[i]->sched,
458+ &ctx->rings[i].entity);
459+ else
460+ DRM_ERROR("ctx %p is still alive\n", ctx);
461+ }
462+}
463+
464+void amdgpu_ctx_mgr_entity_cleanup(struct amdgpu_ctx_mgr *mgr)
465+{
466+ struct amdgpu_ctx *ctx;
467+ struct idr *idp;
468+ uint32_t id, i;
469+
470+ idp = &mgr->ctx_handles;
471+
472+ idr_for_each_entry(idp, ctx, id) {
473+
474+ if (!ctx->adev)
475+ return;
476+
477+ for (i = 0; i < ctx->adev->num_rings; i++)
478+ if (kref_read(&ctx->refcount) == 1)
479+ drm_sched_entity_cleanup(&ctx->adev->rings[i]->sched,
480+ &ctx->rings[i].entity);
481+ else
482+ DRM_ERROR("ctx %p is still alive\n", ctx);
483+ }
484+}
485+
438486 void amdgpu_ctx_mgr_fini(struct amdgpu_ctx_mgr *mgr)
439487 {
440488 struct amdgpu_ctx *ctx;
441489 struct idr *idp;
442490 uint32_t id;
443491
492+ amdgpu_ctx_mgr_entity_cleanup(mgr);
493+
444494 idp = &mgr->ctx_handles;
445495
446496 idr_for_each_entry(idp, ctx, id) {
447− if (kref_put(&ctx->refcount, amdgpu_ctx_do_release) != 1)
497+ if (kref_put(&ctx->refcount, amdgpu_ctx_fini) != 1)
448498 DRM_ERROR("ctx %p is still alive\n", ctx);
449499 }
450500
drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c+190−5
@@ -28,8 +28,13 @@ · 27 unmodified lines
2828 #include <linux/debugfs.h>
2929 #include "amdgpu.h"
3030
31−/*
32− * Debugfs
31+/**
32+ * amdgpu_debugfs_add_files - Add simple debugfs entries
33+ *
34+ * @adev: Device to attach debugfs entries to
35+ * @files: Array of function callbacks that respond to reads
36+ * @nfiles: Number of callbacks to register
37+ *
3338 */
3439 int amdgpu_debugfs_add_files(struct amdgpu_device *adev,
3540 const struct drm_info_list *files,
@@ -64,7 +69,33 @@ int amdgpu_debugfs_add_files(struct amdgpu_device *adev, · 28 unmodified lines
6469
6570 #if defined(CONFIG_DEBUG_FS)
6671
67−
72+/**
73+ * amdgpu_debugfs_process_reg_op - Handle MMIO register reads/writes
74+ *
75+ * @read: True if reading
76+ * @f: open file handle
77+ * @buf: User buffer to write/read to
78+ * @size: Number of bytes to write/read
79+ * @pos: Offset to seek to
80+ *
81+ * This debugfs entry has special meaning on the offset being sought.
82+ * Various bits have different meanings:
83+ *
84+ * Bit 62: Indicates a GRBM bank switch is needed
85+ * Bit 61: Indicates a SRBM bank switch is needed (implies bit 62 is
86+ * zero)
87+ * Bits 24..33: The SE or ME selector if needed
88+ * Bits 34..43: The SH (or SA) or PIPE selector if needed
89+ * Bits 44..53: The INSTANCE (or CU/WGP) or QUEUE selector if needed
90+ *
91+ * Bit 23: Indicates that the PM power gating lock should be held
92+ * This is necessary to read registers that might be
93+ * unreliable during a power gating transistion.
94+ *
95+ * The lower bits are the BYTE offset of the register to read. This
96+ * allows reading multiple registers in a single call and having
97+ * the returned size reflect that.
98+ */
6899 static int amdgpu_debugfs_process_reg_op(bool read, struct file *f,
69100 char __user *buf, size_t size, loff_t *pos)
70101 {
@@ -164,19 +195,37 @@ end: · 93 unmodified lines
164195 return result;
165196 }
166197
167−
198+/**
199+ * amdgpu_debugfs_regs_read - Callback for reading MMIO registers
200+ */
168201 static ssize_t amdgpu_debugfs_regs_read(struct file *f, char __user *buf,
169202 size_t size, loff_t *pos)
170203 {
171204 return amdgpu_debugfs_process_reg_op(true, f, buf, size, pos);
172205 }
173206
207+/**
208+ * amdgpu_debugfs_regs_write - Callback for writing MMIO registers
209+ */
174210 static ssize_t amdgpu_debugfs_regs_write(struct file *f, const char __user *buf,
175211 size_t size, loff_t *pos)
176212 {
177213 return amdgpu_debugfs_process_reg_op(false, f, (char __user *)buf, size, pos);
178214 }
179215
216+
217+/**
218+ * amdgpu_debugfs_regs_pcie_read - Read from a PCIE register
219+ *
220+ * @f: open file handle
221+ * @buf: User buffer to store read data in
222+ * @size: Number of bytes to read
223+ * @pos: Offset to seek to
224+ *
225+ * The lower bits are the BYTE offset of the register to read. This
226+ * allows reading multiple registers in a single call and having
227+ * the returned size reflect that.
228+ */
180229 static ssize_t amdgpu_debugfs_regs_pcie_read(struct file *f, char __user *buf,
181230 size_t size, loff_t *pos)
182231 {
@@ -204,6 +253,18 @@ static ssize_t amdgpu_debugfs_regs_pcie_read(struct file *f, char __user *buf, · 21 unmodified lines
204253 return result;
205254 }
206255
256+/**
257+ * amdgpu_debugfs_regs_pcie_write - Write to a PCIE register
258+ *
259+ * @f: open file handle
260+ * @buf: User buffer to write data from
261+ * @size: Number of bytes to write
262+ * @pos: Offset to seek to
263+ *
264+ * The lower bits are the BYTE offset of the register to write. This
265+ * allows writing multiple registers in a single call and having
266+ * the returned size reflect that.
267+ */
207268 static ssize_t amdgpu_debugfs_regs_pcie_write(struct file *f, const char __user *buf,
208269 size_t size, loff_t *pos)
209270 {
@@ -232,6 +293,18 @@ static ssize_t amdgpu_debugfs_regs_pcie_write(struct file *f, const char __user · 22 unmodified lines
232293 return result;
233294 }
234295
296+/**
297+ * amdgpu_debugfs_regs_didt_read - Read from a DIDT register
298+ *
299+ * @f: open file handle
300+ * @buf: User buffer to store read data in
301+ * @size: Number of bytes to read
302+ * @pos: Offset to seek to
303+ *
304+ * The lower bits are the BYTE offset of the register to read. This
305+ * allows reading multiple registers in a single call and having
306+ * the returned size reflect that.
307+ */
235308 static ssize_t amdgpu_debugfs_regs_didt_read(struct file *f, char __user *buf,
236309 size_t size, loff_t *pos)
237310 {
@@ -259,6 +332,18 @@ static ssize_t amdgpu_debugfs_regs_didt_read(struct file *f, char __user *buf, · 21 unmodified lines
259332 return result;
260333 }
261334
335+/**
336+ * amdgpu_debugfs_regs_didt_write - Write to a DIDT register
337+ *
338+ * @f: open file handle
339+ * @buf: User buffer to write data from
340+ * @size: Number of bytes to write
341+ * @pos: Offset to seek to
342+ *
343+ * The lower bits are the BYTE offset of the register to write. This
344+ * allows writing multiple registers in a single call and having
345+ * the returned size reflect that.
346+ */
262347 static ssize_t amdgpu_debugfs_regs_didt_write(struct file *f, const char __user *buf,
263348 size_t size, loff_t *pos)
264349 {
@@ -287,6 +372,18 @@ static ssize_t amdgpu_debugfs_regs_didt_write(struct file *f, const char __user · 22 unmodified lines
287372 return result;
288373 }
289374
375+/**
376+ * amdgpu_debugfs_regs_smc_read - Read from a SMC register
377+ *
378+ * @f: open file handle
379+ * @buf: User buffer to store read data in
380+ * @size: Number of bytes to read
381+ * @pos: Offset to seek to
382+ *
383+ * The lower bits are the BYTE offset of the register to read. This
384+ * allows reading multiple registers in a single call and having
385+ * the returned size reflect that.
386+ */
290387 static ssize_t amdgpu_debugfs_regs_smc_read(struct file *f, char __user *buf,
291388 size_t size, loff_t *pos)
292389 {
@@ -314,6 +411,18 @@ static ssize_t amdgpu_debugfs_regs_smc_read(struct file *f, char __user *buf, · 21 unmodified lines
314411 return result;
315412 }
316413
414+/**
415+ * amdgpu_debugfs_regs_smc_write - Write to a SMC register
416+ *
417+ * @f: open file handle
418+ * @buf: User buffer to write data from
419+ * @size: Number of bytes to write
420+ * @pos: Offset to seek to
421+ *
422+ * The lower bits are the BYTE offset of the register to write. This
423+ * allows writing multiple registers in a single call and having
424+ * the returned size reflect that.
425+ */
317426 static ssize_t amdgpu_debugfs_regs_smc_write(struct file *f, const char __user *buf,
318427 size_t size, loff_t *pos)
319428 {
@@ -342,6 +451,20 @@ static ssize_t amdgpu_debugfs_regs_smc_write(struct file *f, const char __user * · 22 unmodified lines
342451 return result;
343452 }
344453
454+/**
455+ * amdgpu_debugfs_gca_config_read - Read from gfx config data
456+ *
457+ * @f: open file handle
458+ * @buf: User buffer to store read data in
459+ * @size: Number of bytes to read
460+ * @pos: Offset to seek to
461+ *
462+ * This file is used to access configuration data in a somewhat
463+ * stable fashion. The format is a series of DWORDs with the first
464+ * indicating which revision it is. New content is appended to the
465+ * end so that older software can still read the data.
466+ */
467+
345468 static ssize_t amdgpu_debugfs_gca_config_read(struct file *f, char __user *buf,
346469 size_t size, loff_t *pos)
347470 {
@@ -418,6 +541,19 @@ static ssize_t amdgpu_debugfs_gca_config_read(struct file *f, char __user *buf, · 70 unmodified lines
418541 return result;
419542 }
420543
544+/**
545+ * amdgpu_debugfs_sensor_read - Read from the powerplay sensors
546+ *
547+ * @f: open file handle
548+ * @buf: User buffer to store read data in
549+ * @size: Number of bytes to read
550+ * @pos: Offset to seek to
551+ *
552+ * The offset is treated as the BYTE address of one of the sensors
553+ * enumerated in amd/include/kgd_pp_interface.h under the
554+ * 'amd_pp_sensors' enumeration. For instance to read the UVD VCLK
555+ * you would use the offset 3 * 4 = 12.
556+ */
421557 static ssize_t amdgpu_debugfs_sensor_read(struct file *f, char __user *buf,
422558 size_t size, loff_t *pos)
423559 {
@@ -428,7 +564,7 @@ static ssize_t amdgpu_debugfs_sensor_read(struct file *f, char __user *buf, · 4 unmodified lines
428564 if (size & 3 || *pos & 0x3)
429565 return -EINVAL;
430566
431− if (amdgpu_dpm == 0)
567+ if (!adev->pm.dpm_enabled)
432568 return -EINVAL;
433569
434570 /* convert offset to sensor number */
@@ -457,6 +593,27 @@ static ssize_t amdgpu_debugfs_sensor_read(struct file *f, char __user *buf, · 22 unmodified lines
457593 return !r ? outsize : r;
458594 }
459595
596+/** amdgpu_debugfs_wave_read - Read WAVE STATUS data
597+ *
598+ * @f: open file handle
599+ * @buf: User buffer to store read data in
600+ * @size: Number of bytes to read
601+ * @pos: Offset to seek to
602+ *
603+ * The offset being sought changes which wave that the status data
604+ * will be returned for. The bits are used as follows:
605+ *
606+ * Bits 0..6: Byte offset into data
607+ * Bits 7..14: SE selector
608+ * Bits 15..22: SH/SA selector
609+ * Bits 23..30: CU/{WGP+SIMD} selector
610+ * Bits 31..36: WAVE ID selector
611+ * Bits 37..44: SIMD ID selector
612+ *
613+ * The returned data begins with one DWORD of version information
614+ * Followed by WAVE STATUS registers relevant to the GFX IP version
615+ * being used. See gfx_v8_0_read_wave_data() for an example output.
616+ */
460617 static ssize_t amdgpu_debugfs_wave_read(struct file *f, char __user *buf,
461618 size_t size, loff_t *pos)
462619 {
@@ -507,6 +664,28 @@ static ssize_t amdgpu_debugfs_wave_read(struct file *f, char __user *buf, · 44 unmodified lines
507664 return result;
508665 }
509666
667+/** amdgpu_debugfs_gpr_read - Read wave gprs
668+ *
669+ * @f: open file handle
670+ * @buf: User buffer to store read data in
671+ * @size: Number of bytes to read
672+ * @pos: Offset to seek to
673+ *
674+ * The offset being sought changes which wave that the status data
675+ * will be returned for. The bits are used as follows:
676+ *
677+ * Bits 0..11: Byte offset into data
678+ * Bits 12..19: SE selector
679+ * Bits 20..27: SH/SA selector
680+ * Bits 28..35: CU/{WGP+SIMD} selector
681+ * Bits 36..43: WAVE ID selector
682+ * Bits 37..44: SIMD ID selector
683+ * Bits 52..59: Thread selector
684+ * Bits 60..61: Bank selector (VGPR=0,SGPR=1)
685+ *
686+ * The return data comes from the SGPR or VGPR register bank for
687+ * the selected operational unit.
688+ */
510689 static ssize_t amdgpu_debugfs_gpr_read(struct file *f, char __user *buf,
511690 size_t size, loff_t *pos)
512691 {
@@ -637,6 +816,12 @@ static const char *debugfs_regs_names[] = { · 124 unmodified lines
637816 "amdgpu_gpr",
638817 };
639818
819+/**
820+ * amdgpu_debugfs_regs_init - Initialize debugfs entries that provide
821+ * register access.
822+ *
823+ * @adev: The device to attach the debugfs entries to
824+ */
640825 int amdgpu_debugfs_regs_init(struct amdgpu_device *adev)
641826 {
642827 struct drm_minor *minor = adev->ddev->primary;
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c+80−25
@@ -83,6 +83,7 @@ static const char *amdgpu_asic_name[] = { · 82 unmodified lines
8383 "POLARIS10",
8484 "POLARIS11",
8585 "POLARIS12",
86+ "VEGAM",
8687 "VEGA10",
8788 "VEGA12",
8889 "RAVEN",
@@ -690,6 +691,8 @@ void amdgpu_device_gart_location(struct amdgpu_device *adev, · 601 unmodified lines
690691 {
691692 u64 size_af, size_bf;
692693
694+ mc->gart_size += adev->pm.smu_prv_buffer_size;
695+
693696 size_af = adev->gmc.mc_mask - mc->vram_end;
694697 size_bf = mc->vram_start;
695698 if (size_bf > size_af) {
@@ -907,6 +910,46 @@ static void amdgpu_device_check_vm_size(struct amdgpu_device *adev) · 211 unmodified lines
907910 }
908911 }
909912
913+static void amdgpu_device_check_smu_prv_buffer_size(struct amdgpu_device *adev)
914+{
915+ struct sysinfo si;
916+ bool is_os_64 = (sizeof(void *) == 8) ? true : false;
917+ uint64_t total_memory;
918+ uint64_t dram_size_seven_GB = 0x1B8000000;
919+ uint64_t dram_size_three_GB = 0xB8000000;
920+
921+ if (amdgpu_smu_memory_pool_size == 0)
922+ return;
923+
924+ if (!is_os_64) {
925+ DRM_WARN("Not 64-bit OS, feature not supported\n");
926+ goto def_value;
927+ }
928+ si_meminfo(&si);
929+ total_memory = (uint64_t)si.totalram * si.mem_unit;
930+
931+ if ((amdgpu_smu_memory_pool_size == 1) ||
932+ (amdgpu_smu_memory_pool_size == 2)) {
933+ if (total_memory < dram_size_three_GB)
934+ goto def_value1;
935+ } else if ((amdgpu_smu_memory_pool_size == 4) ||
936+ (amdgpu_smu_memory_pool_size == 8)) {
937+ if (total_memory < dram_size_seven_GB)
938+ goto def_value1;
939+ } else {
940+ DRM_WARN("Smu memory pool size not supported\n");
941+ goto def_value;
942+ }
943+ adev->pm.smu_prv_buffer_size = amdgpu_smu_memory_pool_size << 28;
944+
945+ return;
946+
947+def_value1:
948+ DRM_WARN("No enough system memory\n");
949+def_value:
950+ adev->pm.smu_prv_buffer_size = 0;
951+}
952+
910953 /**
911954 * amdgpu_device_check_arguments - validate module params
912955 *
@@ -948,6 +991,8 @@ static void amdgpu_device_check_arguments(struct amdgpu_device *adev) · 35 unmodified lines
948991 amdgpu_vm_fragment_size = -1;
949992 }
950993
994+ amdgpu_device_check_smu_prv_buffer_size(adev);
995+
951996 amdgpu_device_check_vm_size(adev);
952997
953998 amdgpu_device_check_block_size(adev);
@@ -1039,10 +1084,11 @@ static const struct vga_switcheroo_client_ops amdgpu_switcheroo_ops = { · 85 unmodified lines
10391084 * the hardware IP specified.
10401085 * Returns the error code from the last instance.
10411086 */
1042−int amdgpu_device_ip_set_clockgating_state(struct amdgpu_device *adev,
1087+int amdgpu_device_ip_set_clockgating_state(void *dev,
10431088 enum amd_ip_block_type block_type,
10441089 enum amd_clockgating_state state)
10451090 {
1091+ struct amdgpu_device *adev = dev;
10461092 int i, r = 0;
10471093
10481094 for (i = 0; i < adev->num_ip_blocks; i++) {
@@ -1072,10 +1118,11 @@ int amdgpu_device_ip_set_clockgating_state(struct amdgpu_device *adev, · 23 unmodified lines
10721118 * the hardware IP specified.
10731119 * Returns the error code from the last instance.
10741120 */
1075−int amdgpu_device_ip_set_powergating_state(struct amdgpu_device *adev,
1121+int amdgpu_device_ip_set_powergating_state(void *dev,
10761122 enum amd_ip_block_type block_type,
10771123 enum amd_powergating_state state)
10781124 {
1125+ struct amdgpu_device *adev = dev;
10791126 int i, r = 0;
10801127
10811128 for (i = 0; i < adev->num_ip_blocks; i++) {
@@ -1320,9 +1367,10 @@ static int amdgpu_device_parse_gpu_info_fw(struct amdgpu_device *adev) · 238 unmodified lines
13201367 case CHIP_TOPAZ:
13211368 case CHIP_TONGA:
13221369 case CHIP_FIJI:
1323− case CHIP_POLARIS11:
13241370 case CHIP_POLARIS10:
1371+ case CHIP_POLARIS11:
13251372 case CHIP_POLARIS12:
1373+ case CHIP_VEGAM:
13261374 case CHIP_CARRIZO:
13271375 case CHIP_STONEY:
13281376 #ifdef CONFIG_DRM_AMDGPU_SI
@@ -1428,9 +1476,10 @@ static int amdgpu_device_ip_early_init(struct amdgpu_device *adev) · 99 unmodified lines
14281476 case CHIP_TOPAZ:
14291477 case CHIP_TONGA:
14301478 case CHIP_FIJI:
1431− case CHIP_POLARIS11:
14321479 case CHIP_POLARIS10:
1480+ case CHIP_POLARIS11:
14331481 case CHIP_POLARIS12:
1482+ case CHIP_VEGAM:
14341483 case CHIP_CARRIZO:
14351484 case CHIP_STONEY:
14361485 if (adev->asic_type == CHIP_CARRIZO || adev->asic_type == CHIP_STONEY)
@@ -1499,6 +1548,8 @@ static int amdgpu_device_ip_early_init(struct amdgpu_device *adev) · 62 unmodified lines
14991548 return -EAGAIN;
15001549 }
15011550
1551+ adev->powerplay.pp_feature = amdgpu_pp_feature_mask;
1552+
15021553 for (i = 0; i < adev->num_ip_blocks; i++) {
15031554 if ((amdgpu_ip_block_mask & (1 << i)) == 0) {
15041555 DRM_ERROR("disabled ip block: %d <%s>\n",
@@ -1654,6 +1705,10 @@ static int amdgpu_device_ip_late_set_cg_state(struct amdgpu_device *adev) · 149 unmodified lines
16541705 if (amdgpu_emu_mode == 1)
16551706 return 0;
16561707
1708+ r = amdgpu_ib_ring_tests(adev);
1709+ if (r)
1710+ DRM_ERROR("ib ring test failed (%d).\n", r);
1711+
16571712 for (i = 0; i < adev->num_ip_blocks; i++) {
16581713 if (!adev->ip_blocks[i].status.valid)
16591714 continue;
@@ -1704,8 +1759,8 @@ static int amdgpu_device_ip_late_init(struct amdgpu_device *adev) · 44 unmodified lines
17041759 }
17051760 }
17061761
1707− mod_delayed_work(system_wq, &adev->late_init_work,
1708− msecs_to_jiffies(AMDGPU_RESUME_MS));
1762+ queue_delayed_work(system_wq, &adev->late_init_work,
1763+ msecs_to_jiffies(AMDGPU_RESUME_MS));
17091764
17101765 amdgpu_device_fill_reset_magic(adev);
17111766
@@ -1850,6 +1905,12 @@ int amdgpu_device_ip_suspend(struct amdgpu_device *adev) · 138 unmodified lines
18501905 if (amdgpu_sriov_vf(adev))
18511906 amdgpu_virt_request_full_gpu(adev, false);
18521907
1908+ /* ungate SMC block powergating */
1909+ if (adev->powerplay.pp_feature & PP_GFXOFF_MASK)
1910+ amdgpu_device_ip_set_powergating_state(adev,
1911+ AMD_IP_BLOCK_TYPE_SMC,
1912+ AMD_CG_STATE_UNGATE);
1913+
18531914 /* ungate SMC block first */
18541915 r = amdgpu_device_ip_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_SMC,
18551916 AMD_CG_STATE_UNGATE);
@@ -2086,14 +2147,12 @@ bool amdgpu_device_asic_has_dc_support(enum amd_asic_type asic_type) · 230 unmodified lines
20862147 case CHIP_MULLINS:
20872148 case CHIP_CARRIZO:
20882149 case CHIP_STONEY:
2089− case CHIP_POLARIS11:
20902150 case CHIP_POLARIS10:
2151+ case CHIP_POLARIS11:
20912152 case CHIP_POLARIS12:
2153+ case CHIP_VEGAM:
20922154 case CHIP_TONGA:
20932155 case CHIP_FIJI:
2094−#if defined(CONFIG_DRM_AMD_DC_PRE_VEGA)
2095− return amdgpu_dc != 0;
2096−#endif
20972156 case CHIP_VEGA10:
20982157 case CHIP_VEGA12:
20992158 #if defined(CONFIG_DRM_AMD_DC_DCN1_0)
@@ -2375,10 +2434,6 @@ fence_driver_init: · 275 unmodified lines
23752434 goto failed;
23762435 }
23772436
2378− r = amdgpu_ib_ring_tests(adev);
2379− if (r)
2380− DRM_ERROR("ib ring test failed (%d).\n", r);
2381−
23822437 if (amdgpu_sriov_vf(adev))
23832438 amdgpu_virt_init_data_exchange(adev);
23842439
@@ -2539,7 +2594,7 @@ int amdgpu_device_suspend(struct drm_device *dev, bool suspend, bool fbcon) · 154 unmodified lines
25392594 /* unpin the front buffers and cursors */
25402595 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
25412596 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2542− struct amdgpu_framebuffer *rfb = to_amdgpu_framebuffer(crtc->primary->fb);
2597+ struct drm_framebuffer *fb = crtc->primary->fb;
25432598 struct amdgpu_bo *robj;
25442599
25452600 if (amdgpu_crtc->cursor_bo) {
@@ -2551,10 +2606,10 @@ int amdgpu_device_suspend(struct drm_device *dev, bool suspend, bool fbcon) · 5 unmodified lines
25512606 }
25522607 }
25532608
2554− if (rfb == NULL || rfb->obj == NULL) {
2609+ if (fb == NULL || fb->obj[0] == NULL) {
25552610 continue;
25562611 }
2557− robj = gem_to_amdgpu_bo(rfb->obj);
2612+ robj = gem_to_amdgpu_bo(fb->obj[0]);
25582613 /* don't unpin kernel fb objects */
25592614 if (!amdgpu_fbdev_robj_is_fb(adev, robj)) {
25602615 r = amdgpu_bo_reserve(robj, true);
@@ -2640,11 +2695,6 @@ int amdgpu_device_resume(struct drm_device *dev, bool resume, bool fbcon) · 79 unmodified lines
26402695 }
26412696 amdgpu_fence_driver_resume(adev);
26422697
2643− if (resume) {
2644− r = amdgpu_ib_ring_tests(adev);
2645− if (r)
2646− DRM_ERROR("ib ring test failed (%d).\n", r);
2647− }
26482698
26492699 r = amdgpu_device_ip_late_init(adev);
26502700 if (r)
@@ -2736,6 +2786,9 @@ static bool amdgpu_device_ip_check_soft_reset(struct amdgpu_device *adev) · 85 unmodified lines
27362786 if (amdgpu_sriov_vf(adev))
27372787 return true;
27382788
2789+ if (amdgpu_asic_need_full_reset(adev))
2790+ return true;
2791+
27392792 for (i = 0; i < adev->num_ip_blocks; i++) {
27402793 if (!adev->ip_blocks[i].status.valid)
27412794 continue;
@@ -2792,6 +2845,9 @@ static bool amdgpu_device_ip_need_full_reset(struct amdgpu_device *adev) · 50 unmodified lines
27922845 {
27932846 int i;
27942847
2848+ if (amdgpu_asic_need_full_reset(adev))
2849+ return true;
2850+
27952851 for (i = 0; i < adev->num_ip_blocks; i++) {
27962852 if (!adev->ip_blocks[i].status.valid)
27972853 continue;
@@ -3087,20 +3143,19 @@ static int amdgpu_device_reset_sriov(struct amdgpu_device *adev, · 289 unmodified lines
30873143
30883144 /* now we are okay to resume SMC/CP/SDMA */
30893145 r = amdgpu_device_ip_reinit_late_sriov(adev);
3090− amdgpu_virt_release_full_gpu(adev, true);
30913146 if (r)
30923147 goto error;
30933148
30943149 amdgpu_irq_gpu_reset_resume_helper(adev);
30953150 r = amdgpu_ib_ring_tests(adev);
30963151
3152+error:
3153+ amdgpu_virt_release_full_gpu(adev, true);
30973154 if (!r && adev->virt.gim_feature & AMDGIM_FEATURE_GIM_FLR_VRAMLOST) {
30983155 atomic_inc(&adev->vram_lost_counter);
30993156 r = amdgpu_device_handle_vram_lost(adev);
31003157 }
31013158
3102−error:
3103−
31043159 return r;
31053160 }
31063161
drivers/gpu/drm/amd/amdgpu/amdgpu_display.c+9−31
@@ -35,6 +35,7 @@ · 34 unmodified lines
3535 #include <linux/pm_runtime.h>
3636 #include <drm/drm_crtc_helper.h>
3737 #include <drm/drm_edid.h>
38+#include <drm/drm_gem_framebuffer_helper.h>
3839 #include <drm/drm_fb_helper.h>
3940
4041 static void amdgpu_display_flip_callback(struct dma_fence *f,
@@ -151,8 +152,6 @@ int amdgpu_display_crtc_page_flip_target(struct drm_crtc *crtc, · 110 unmodified lines
151152 struct drm_device *dev = crtc->dev;
152153 struct amdgpu_device *adev = dev->dev_private;
153154 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
154− struct amdgpu_framebuffer *old_amdgpu_fb;
155− struct amdgpu_framebuffer *new_amdgpu_fb;
156155 struct drm_gem_object *obj;
157156 struct amdgpu_flip_work *work;
158157 struct amdgpu_bo *new_abo;
@@ -174,15 +173,13 @@ int amdgpu_display_crtc_page_flip_target(struct drm_crtc *crtc, · 15 unmodified lines
174173 work->async = (page_flip_flags & DRM_MODE_PAGE_FLIP_ASYNC) != 0;
175174
176175 /* schedule unpin of the old buffer */
177− old_amdgpu_fb = to_amdgpu_framebuffer(crtc->primary->fb);
178− obj = old_amdgpu_fb->obj;
176+ obj = crtc->primary->fb->obj[0];
179177
180178 /* take a reference to the old object */
181179 work->old_abo = gem_to_amdgpu_bo(obj);
182180 amdgpu_bo_ref(work->old_abo);
183181
184− new_amdgpu_fb = to_amdgpu_framebuffer(fb);
185− obj = new_amdgpu_fb->obj;
182+ obj = fb->obj[0];
186183 new_abo = gem_to_amdgpu_bo(obj);
187184
188185 /* pin the new buffer */
@@ -192,7 +189,7 @@ int amdgpu_display_crtc_page_flip_target(struct drm_crtc *crtc, · 3 unmodified lines
192189 goto cleanup;
193190 }
194191
195− r = amdgpu_bo_pin(new_abo, amdgpu_display_framebuffer_domains(adev), &base);
192+ r = amdgpu_bo_pin(new_abo, amdgpu_display_supported_domains(adev), &base);
196193 if (unlikely(r != 0)) {
197194 DRM_ERROR("failed to pin new abo buffer before flip\n");
198195 goto unreserve;
@@ -482,31 +479,12 @@ bool amdgpu_display_ddc_probe(struct amdgpu_connector *amdgpu_connector, · 283 unmodified lines
482479 return true;
483480 }
484481
485−static void amdgpu_display_user_framebuffer_destroy(struct drm_framebuffer *fb)
486−{
487− struct amdgpu_framebuffer *amdgpu_fb = to_amdgpu_framebuffer(fb);
488−
489− drm_gem_object_put_unlocked(amdgpu_fb->obj);
490− drm_framebuffer_cleanup(fb);
491− kfree(amdgpu_fb);
492−}
493−
494−static int amdgpu_display_user_framebuffer_create_handle(
495− struct drm_framebuffer *fb,
496− struct drm_file *file_priv,
497− unsigned int *handle)
498−{
499− struct amdgpu_framebuffer *amdgpu_fb = to_amdgpu_framebuffer(fb);
500−
501− return drm_gem_handle_create(file_priv, amdgpu_fb->obj, handle);
502−}
503−
504482 static const struct drm_framebuffer_funcs amdgpu_fb_funcs = {
505− .destroy = amdgpu_display_user_framebuffer_destroy,
506− .create_handle = amdgpu_display_user_framebuffer_create_handle,
483+ .destroy = drm_gem_fb_destroy,
484+ .create_handle = drm_gem_fb_create_handle,
507485 };
508486
509−uint32_t amdgpu_display_framebuffer_domains(struct amdgpu_device *adev)
487+uint32_t amdgpu_display_supported_domains(struct amdgpu_device *adev)
510488 {
511489 uint32_t domain = AMDGPU_GEM_DOMAIN_VRAM;
512490
@@ -526,11 +504,11 @@ int amdgpu_display_framebuffer_init(struct drm_device *dev, · 13 unmodified lines
526504 struct drm_gem_object *obj)
527505 {
528506 int ret;
529− rfb->obj = obj;
507+ rfb->base.obj[0] = obj;
530508 drm_helper_mode_fill_fb_struct(dev, &rfb->base, mode_cmd);
531509 ret = drm_framebuffer_init(dev, &rfb->base, &amdgpu_fb_funcs);
532510 if (ret) {
533− rfb->obj = NULL;
511+ rfb->base.obj[0] = NULL;
534512 return ret;
535513 }
536514 return 0;
drivers/gpu/drm/amd/amdgpu/amdgpu_display.h+1−1
@@ -23,7 +23,7 @@ · 22 unmodified lines
2323 #ifndef __AMDGPU_DISPLAY_H__
2424 #define __AMDGPU_DISPLAY_H__
2525
26−uint32_t amdgpu_display_framebuffer_domains(struct amdgpu_device *adev);
26+uint32_t amdgpu_display_supported_domains(struct amdgpu_device *adev);
2727 struct drm_framebuffer *
2828 amdgpu_display_user_framebuffer_create(struct drm_device *dev,
2929 struct drm_file *file_priv,
drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.c+20−0
@@ -115,6 +115,26 @@ void amdgpu_dpm_print_ps_status(struct amdgpu_device *adev, · 114 unmodified lines
115115 pr_cont("\n");
116116 }
117117
118+void amdgpu_dpm_get_active_displays(struct amdgpu_device *adev)
119+{
120+ struct drm_device *ddev = adev->ddev;
121+ struct drm_crtc *crtc;
122+ struct amdgpu_crtc *amdgpu_crtc;
123+
124+ adev->pm.dpm.new_active_crtcs = 0;
125+ adev->pm.dpm.new_active_crtc_count = 0;
126+ if (adev->mode_info.num_crtc && adev->mode_info.mode_config_initialized) {
127+ list_for_each_entry(crtc,
128+ &ddev->mode_config.crtc_list, head) {
129+ amdgpu_crtc = to_amdgpu_crtc(crtc);
130+ if (amdgpu_crtc->enabled) {
131+ adev->pm.dpm.new_active_crtcs |= (1 << amdgpu_crtc->crtc_id);
132+ adev->pm.dpm.new_active_crtc_count++;
133+ }
134+ }
135+ }
136+}
137+
118138
119139 u32 amdgpu_dpm_get_vblank_time(struct amdgpu_device *adev)
120140 {
drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h+3−8
@@ -52,8 +52,6 @@ enum amdgpu_dpm_event_src { · 51 unmodified lines
5252 AMDGPU_DPM_EVENT_SRC_DIGIAL_OR_EXTERNAL = 4
5353 };
5454
55−#define SCLK_DEEP_SLEEP_MASK 0x8
56−
5755 struct amdgpu_ps {
5856 u32 caps; /* vbios flags */
5957 u32 class; /* vbios flags */
@@ -349,12 +347,6 @@ enum amdgpu_pcie_gen { · 289 unmodified lines
349347 ((adev)->powerplay.pp_funcs->set_clockgating_by_smu(\
350348 (adev)->powerplay.pp_handle, msg_id))
351349
352−#define amdgpu_dpm_notify_smu_memory_info(adev, virtual_addr_low, \
353− virtual_addr_hi, mc_addr_low, mc_addr_hi, size) \
354− ((adev)->powerplay.pp_funcs->notify_smu_memory_info)( \
355− (adev)->powerplay.pp_handle, virtual_addr_low, \
356− virtual_addr_hi, mc_addr_low, mc_addr_hi, size)
357−
358350 #define amdgpu_dpm_get_power_profile_mode(adev, buf) \
359351 ((adev)->powerplay.pp_funcs->get_power_profile_mode(\
360352 (adev)->powerplay.pp_handle, buf))
@@ -445,6 +437,8 @@ struct amdgpu_pm { · 84 unmodified lines
445437 uint32_t pcie_gen_mask;
446438 uint32_t pcie_mlw_mask;
447439 struct amd_pp_display_configuration pm_display_cfg;/* set by dc */
440+ uint32_t smu_prv_buffer_size;
441+ struct amdgpu_bo *smu_prv_buffer;
448442 };
449443
450444 #define R600_SSTU_DFLT 0
@@ -482,6 +476,7 @@ void amdgpu_dpm_print_ps_status(struct amdgpu_device *adev, · 31 unmodified lines
482476 struct amdgpu_ps *rps);
483477 u32 amdgpu_dpm_get_vblank_time(struct amdgpu_device *adev);
484478 u32 amdgpu_dpm_get_vrefresh(struct amdgpu_device *adev);
479+void amdgpu_dpm_get_active_displays(struct amdgpu_device *adev);
485480 bool amdgpu_is_uvd_state(u32 class, u32 class2);
486481 void amdgpu_calculate_u_and_p(u32 i, u32 r_c, u32 p_b,
487482 u32 *p, u32 *u);
drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c+12−2
@@ -75,9 +75,10 @@ · 74 unmodified lines
7575 * - 3.23.0 - Add query for VRAM lost counter
7676 * - 3.24.0 - Add high priority compute support for gfx9
7777 * - 3.25.0 - Add support for sensor query info (stable pstate sclk/mclk).
78+ * - 3.26.0 - GFX9: Process AMDGPU_IB_FLAG_TC_WB_NOT_INVALIDATE.
7879 */
7980 #define KMS_DRIVER_MAJOR 3
80−#define KMS_DRIVER_MINOR 25
81+#define KMS_DRIVER_MINOR 26
8182 #define KMS_DRIVER_PATCHLEVEL 0
8283
8384 int amdgpu_vram_limit = 0;
@@ -121,7 +122,7 @@ uint amdgpu_pg_mask = 0xffffffff; · 37 unmodified lines
121122 uint amdgpu_sdma_phase_quantum = 32;
122123 char *amdgpu_disable_cu = NULL;
123124 char *amdgpu_virtual_display = NULL;
124−uint amdgpu_pp_feature_mask = 0xffffbfff;
125+uint amdgpu_pp_feature_mask = 0xffff3fff; /* gfxoff (bit 15) disabled by default */
125126 int amdgpu_ngg = 0;
126127 int amdgpu_prim_buf_per_se = 0;
127128 int amdgpu_pos_buf_per_se = 0;
@@ -132,6 +133,7 @@ int amdgpu_lbpw = -1; · 4 unmodified lines
132133 int amdgpu_compute_multipipe = -1;
133134 int amdgpu_gpu_recovery = -1; /* auto */
134135 int amdgpu_emu_mode = 0;
136+uint amdgpu_smu_memory_pool_size = 0;
135137
136138 MODULE_PARM_DESC(vramlimit, "Restrict VRAM for testing, in megabytes");
137139 module_param_named(vramlimit, amdgpu_vram_limit, int, 0600);
@@ -316,6 +318,11 @@ MODULE_PARM_DESC(cik_support, "CIK support (1 = enabled (default), 0 = disabled) · 178 unmodified lines
316318 module_param_named(cik_support, amdgpu_cik_support, int, 0444);
317319 #endif
318320
321+MODULE_PARM_DESC(smu_memory_pool_size,
322+ "reserve gtt for smu debug usage, 0 = disable,"
323+ "0x1 = 256Mbyte, 0x2 = 512Mbyte, 0x4 = 1 Gbyte, 0x8 = 2GByte");
324+module_param_named(smu_memory_pool_size, amdgpu_smu_memory_pool_size, uint, 0444);
325+
319326 static const struct pci_device_id pciidlist[] = {
320327 #ifdef CONFIG_DRM_AMDGPU_SI
321328 {0x1002, 0x6780, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
@@ -534,6 +541,9 @@ static const struct pci_device_id pciidlist[] = { · 212 unmodified lines
534541 {0x1002, 0x6995, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12},
535542 {0x1002, 0x6997, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12},
536543 {0x1002, 0x699F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12},
544+ /* VEGAM */
545+ {0x1002, 0x694C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGAM},
546+ {0x1002, 0x694E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGAM},
537547 /* Vega 10 */
538548 {0x1002, 0x6860, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
539549 {0x1002, 0x6861, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c+6−6
@@ -137,7 +137,7 @@ static int amdgpufb_create_pinned_object(struct amdgpu_fbdev *rfbdev, · 136 unmodified lines
137137 /* need to align pitch with crtc limits */
138138 mode_cmd->pitches[0] = amdgpu_align_pitch(adev, mode_cmd->width, cpp,
139139 fb_tiled);
140− domain = amdgpu_display_framebuffer_domains(adev);
140+ domain = amdgpu_display_supported_domains(adev);
141141
142142 height = ALIGN(mode_cmd->height, 8);
143143 size = mode_cmd->pitches[0] * height;
@@ -292,9 +292,9 @@ static int amdgpu_fbdev_destroy(struct drm_device *dev, struct amdgpu_fbdev *rfb · 148 unmodified lines
292292
293293 drm_fb_helper_unregister_fbi(&rfbdev->helper);
294294
295− if (rfb->obj) {
296− amdgpufb_destroy_pinned_object(rfb->obj);
297− rfb->obj = NULL;
295+ if (rfb->base.obj[0]) {
296+ amdgpufb_destroy_pinned_object(rfb->base.obj[0]);
297+ rfb->base.obj[0] = NULL;
298298 drm_framebuffer_unregister_private(&rfb->base);
299299 drm_framebuffer_cleanup(&rfb->base);
300300 }
@@ -377,7 +377,7 @@ int amdgpu_fbdev_total_size(struct amdgpu_device *adev) · 76 unmodified lines
377377 if (!adev->mode_info.rfbdev)
378378 return 0;
379379
380− robj = gem_to_amdgpu_bo(adev->mode_info.rfbdev->rfb.obj);
380+ robj = gem_to_amdgpu_bo(adev->mode_info.rfbdev->rfb.base.obj[0]);
381381 size += amdgpu_bo_size(robj);
382382 return size;
383383 }
@@ -386,7 +386,7 @@ bool amdgpu_fbdev_robj_is_fb(struct amdgpu_device *adev, struct amdgpu_bo *robj) · 2 unmodified lines
386386 {
387387 if (!adev->mode_info.rfbdev)
388388 return false;
389− if (robj == gem_to_amdgpu_bo(adev->mode_info.rfbdev->rfb.obj))
389+ if (robj == gem_to_amdgpu_bo(adev->mode_info.rfbdev->rfb.base.obj[0]))
390390 return true;
391391 return false;
392392 }
drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c+3−2
@@ -131,7 +131,8 @@ static u32 amdgpu_fence_read(struct amdgpu_ring *ring) · 130 unmodified lines
131131 * Emits a fence command on the requested ring (all asics).
132132 * Returns 0 on success, -ENOMEM on failure.
133133 */
134−int amdgpu_fence_emit(struct amdgpu_ring *ring, struct dma_fence **f)
134+int amdgpu_fence_emit(struct amdgpu_ring *ring, struct dma_fence **f,
135+ unsigned flags)
135136 {
136137 struct amdgpu_device *adev = ring->adev;
137138 struct amdgpu_fence *fence;
@@ -149,7 +150,7 @@ int amdgpu_fence_emit(struct amdgpu_ring *ring, struct dma_fence **f) · 11 unmodified lines
149150 adev->fence_context + ring->idx,
150151 seq);
151152 amdgpu_ring_emit_fence(ring, ring->fence_drv.gpu_addr,
152− seq, AMDGPU_FENCE_FLAG_INT);
153+ seq, flags | AMDGPU_FENCE_FLAG_INT);
153154
154155 ptr = &ring->fence_drv.fences[seq & ring->fence_drv.num_fences_mask];
155156 /* This function can't be called concurrently anyway, otherwise
drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c+11−6
@@ -113,12 +113,17 @@ int amdgpu_gart_table_vram_alloc(struct amdgpu_device *adev) · 112 unmodified lines
113113 int r;
114114
115115 if (adev->gart.robj == NULL) {
116− r = amdgpu_bo_create(adev, adev->gart.table_size, PAGE_SIZE,
117− AMDGPU_GEM_DOMAIN_VRAM,
118− AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED |
119− AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS,
120− ttm_bo_type_kernel, NULL,
121− &adev->gart.robj);
116+ struct amdgpu_bo_param bp;
117+
118+ memset(&bp, 0, sizeof(bp));
119+ bp.size = adev->gart.table_size;
120+ bp.byte_align = PAGE_SIZE;
121+ bp.domain = AMDGPU_GEM_DOMAIN_VRAM;
122+ bp.flags = AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED |
123+ AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS;
124+ bp.type = ttm_bo_type_kernel;
125+ bp.resv = NULL;
126+ r = amdgpu_bo_create(adev, &bp, &adev->gart.robj);
122127 if (r) {
123128 return r;
124129 }
drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c+37−13
@@ -48,17 +48,25 @@ int amdgpu_gem_object_create(struct amdgpu_device *adev, unsigned long size, · 47 unmodified lines
4848 struct drm_gem_object **obj)
4949 {
5050 struct amdgpu_bo *bo;
51+ struct amdgpu_bo_param bp;
5152 int r;
5253
54+ memset(&bp, 0, sizeof(bp));
5355 *obj = NULL;
5456 /* At least align on page size */
5557 if (alignment < PAGE_SIZE) {
5658 alignment = PAGE_SIZE;
5759 }
5860
61+ bp.size = size;
62+ bp.byte_align = alignment;
63+ bp.type = type;
64+ bp.resv = resv;
65+ bp.preferred_domain = initial_domain;
5966 retry:
60− r = amdgpu_bo_create(adev, size, alignment, initial_domain,
61− flags, type, resv, &bo);
67+ bp.flags = flags;
68+ bp.domain = initial_domain;
69+ r = amdgpu_bo_create(adev, &bp, &bo);
6270 if (r) {
6371 if (r != -ERESTARTSYS) {
6472 if (flags & AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED) {
@@ -221,12 +229,7 @@ int amdgpu_gem_create_ioctl(struct drm_device *dev, void *data, · 156 unmodified lines
221229 return -EINVAL;
222230
223231 /* reject invalid gem domains */
224− if (args->in.domains & ~(AMDGPU_GEM_DOMAIN_CPU |
225− AMDGPU_GEM_DOMAIN_GTT |
226− AMDGPU_GEM_DOMAIN_VRAM |
227− AMDGPU_GEM_DOMAIN_GDS |
228− AMDGPU_GEM_DOMAIN_GWS |
229− AMDGPU_GEM_DOMAIN_OA))
232+ if (args->in.domains & ~AMDGPU_GEM_DOMAIN_MASK)
230233 return -EINVAL;
231234
232235 /* create a gem object to contain this object in */
@@ -771,16 +774,23 @@ int amdgpu_mode_dumb_create(struct drm_file *file_priv, · 538 unmodified lines
771774 }
772775
773776 #if defined(CONFIG_DEBUG_FS)
777+
778+#define amdgpu_debugfs_gem_bo_print_flag(m, bo, flag) \
779+ if (bo->flags & (AMDGPU_GEM_CREATE_ ## flag)) { \
780+ seq_printf((m), " " #flag); \
781+ }
782+
774783 static int amdgpu_debugfs_gem_bo_info(int id, void *ptr, void *data)
775784 {
776785 struct drm_gem_object *gobj = ptr;
777786 struct amdgpu_bo *bo = gem_to_amdgpu_bo(gobj);
778787 struct seq_file *m = data;
779788
789+ struct dma_buf_attachment *attachment;
790+ struct dma_buf *dma_buf;
780791 unsigned domain;
781792 const char *placement;
782793 unsigned pin_count;
783− uint64_t offset;
784794
785795 domain = amdgpu_mem_type_to_domain(bo->tbo.mem.mem_type);
786796 switch (domain) {
@@ -798,13 +808,27 @@ static int amdgpu_debugfs_gem_bo_info(int id, void *ptr, void *data) · 11 unmodified lines
798808 seq_printf(m, "\t0x%08x: %12ld byte %s",
799809 id, amdgpu_bo_size(bo), placement);
800810
801− offset = READ_ONCE(bo->tbo.mem.start);
802− if (offset != AMDGPU_BO_INVALID_OFFSET)
803− seq_printf(m, " @ 0x%010Lx", offset);
804−
805811 pin_count = READ_ONCE(bo->pin_count);
806812 if (pin_count)
807813 seq_printf(m, " pin count %d", pin_count);
814+
815+ dma_buf = READ_ONCE(bo->gem_base.dma_buf);
816+ attachment = READ_ONCE(bo->gem_base.import_attach);
817+
818+ if (attachment)
819+ seq_printf(m, " imported from %p", dma_buf);
820+ else if (dma_buf)
821+ seq_printf(m, " exported as %p", dma_buf);
822+
823+ amdgpu_debugfs_gem_bo_print_flag(m, bo, CPU_ACCESS_REQUIRED);
824+ amdgpu_debugfs_gem_bo_print_flag(m, bo, NO_CPU_ACCESS);
825+ amdgpu_debugfs_gem_bo_print_flag(m, bo, CPU_GTT_USWC);
826+ amdgpu_debugfs_gem_bo_print_flag(m, bo, VRAM_CLEARED);
827+ amdgpu_debugfs_gem_bo_print_flag(m, bo, SHADOW);
828+ amdgpu_debugfs_gem_bo_print_flag(m, bo, VRAM_CONTIGUOUS);
829+ amdgpu_debugfs_gem_bo_print_flag(m, bo, VM_ALWAYS_VALID);
830+ amdgpu_debugfs_gem_bo_print_flag(m, bo, EXPLICIT_SYNC);
831+
808832 seq_printf(m, "\n");
809833
810834 return 0;
drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c+6−2
@@ -127,6 +127,7 @@ int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs, · 126 unmodified lines
127127 struct amdgpu_vm *vm;
128128 uint64_t fence_ctx;
129129 uint32_t status = 0, alloc_size;
130+ unsigned fence_flags = 0;
130131
131132 unsigned i;
132133 int r = 0;
@@ -227,7 +228,10 @@ int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs, · 94 unmodified lines
227228 #endif
228229 amdgpu_asic_invalidate_hdp(adev, ring);
229230
230− r = amdgpu_fence_emit(ring, f);
231+ if (ib->flags & AMDGPU_IB_FLAG_TC_WB_NOT_INVALIDATE)
232+ fence_flags |= AMDGPU_FENCE_FLAG_TC_WB_ONLY;
233+
234+ r = amdgpu_fence_emit(ring, f, fence_flags);
231235 if (r) {
232236 dev_err(adev->dev, "failed to emit fence (%d)\n", r);
233237 if (job && job->vmid)
@@ -242,7 +246,7 @@ int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs, · 8 unmodified lines
242246 /* wrap the last IB with fence */
243247 if (job && job->uf_addr) {
244248 amdgpu_ring_emit_fence(ring, job->uf_addr, job->uf_sequence,
245− AMDGPU_FENCE_FLAG_64BIT);
249+ fence_flags | AMDGPU_FENCE_FLAG_64BIT);
246250 }
247251
248252 if (patch_offset != ~0 && ring->funcs->patch_cond_exec)
drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c+50−8
@@ -31,6 +31,7 @@ · 30 unmodified lines
3131 #include "amdgpu_sched.h"
3232 #include "amdgpu_uvd.h"
3333 #include "amdgpu_vce.h"
34+#include "atom.h"
3435
3536 #include <linux/vga_switcheroo.h>
3637 #include <linux/slab.h>
@@ -214,6 +215,18 @@ static int amdgpu_firmware_info(struct drm_amdgpu_info_firmware *fw_info, · 177 unmodified lines
214215 fw_info->ver = adev->gfx.rlc_fw_version;
215216 fw_info->feature = adev->gfx.rlc_feature_version;
216217 break;
218+ case AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_CNTL:
219+ fw_info->ver = adev->gfx.rlc_srlc_fw_version;
220+ fw_info->feature = adev->gfx.rlc_srlc_feature_version;
221+ break;
222+ case AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_GPM_MEM:
223+ fw_info->ver = adev->gfx.rlc_srlg_fw_version;
224+ fw_info->feature = adev->gfx.rlc_srlg_feature_version;
225+ break;
226+ case AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_SRM_MEM:
227+ fw_info->ver = adev->gfx.rlc_srls_fw_version;
228+ fw_info->feature = adev->gfx.rlc_srls_feature_version;
229+ break;
217230 case AMDGPU_INFO_FW_GFX_MEC:
218231 if (query_fw->index == 0) {
219232 fw_info->ver = adev->gfx.mec_fw_version;
@@ -279,6 +292,9 @@ static int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file · 59 unmodified lines
279292 if (!info->return_size || !info->return_pointer)
280293 return -EINVAL;
281294
295+ /* Ensure IB tests are run on ring */
296+ flush_delayed_work(&adev->late_init_work);
297+
282298 switch (info->query) {
283299 case AMDGPU_INFO_ACCEL_WORKING:
284300 ui32 = adev->accel_working;
@@ -701,10 +717,7 @@ static int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file · 416 unmodified lines
701717 }
702718 }
703719 case AMDGPU_INFO_SENSOR: {
704− struct pp_gpu_power query = {0};
705− int query_size = sizeof(query);
706−
707− if (amdgpu_dpm == 0)
720+ if (!adev->pm.dpm_enabled)
708721 return -ENOENT;
709722
710723 switch (info->sensor_info.type) {
@@ -746,10 +759,10 @@ static int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file · 35 unmodified lines
746759 /* get average GPU power */
747760 if (amdgpu_dpm_read_sensor(adev,
748761 AMDGPU_PP_SENSOR_GPU_POWER,
749− (void *)&query, &query_size)) {
762+ (void *)&ui32, &ui32_size)) {
750763 return -EINVAL;
751764 }
752− ui32 = query.average_gpu_power >> 8;
765+ ui32 >>= 8;
753766 break;
754767 case AMDGPU_INFO_SENSOR_VDDNB:
755768 /* get VDDNB in millivolts */
@@ -913,8 +926,7 @@ void amdgpu_driver_postclose_kms(struct drm_device *dev, · 157 unmodified lines
913926 return;
914927
915928 pm_runtime_get_sync(dev->dev);
916−
917− amdgpu_ctx_mgr_fini(&fpriv->ctx_mgr);
929+ amdgpu_ctx_mgr_entity_fini(&fpriv->ctx_mgr);
918930
919931 if (adev->asic_type != CHIP_RAVEN) {
920932 amdgpu_uvd_free_handles(adev, file_priv);
@@ -935,6 +947,8 @@ void amdgpu_driver_postclose_kms(struct drm_device *dev, · 14 unmodified lines
935947 pd = amdgpu_bo_ref(fpriv->vm.root.base.bo);
936948
937949 amdgpu_vm_fini(adev, &fpriv->vm);
950+ amdgpu_ctx_mgr_fini(&fpriv->ctx_mgr);
951+
938952 if (pasid)
939953 amdgpu_pasid_free_delayed(pd->tbo.resv, pasid);
940954 amdgpu_bo_unref(&pd);
@@ -1088,6 +1102,7 @@ static int amdgpu_debugfs_firmware_info(struct seq_file *m, void *data) · 147 unmodified lines
10881102 struct amdgpu_device *adev = dev->dev_private;
10891103 struct drm_amdgpu_info_firmware fw_info;
10901104 struct drm_amdgpu_query_fw query_fw;
1105+ struct atom_context *ctx = adev->mode_info.atom_context;
10911106 int ret, i;
10921107
10931108 /* VCE */
@@ -1146,6 +1161,30 @@ static int amdgpu_debugfs_firmware_info(struct seq_file *m, void *data) · 52 unmodified lines
11461161 seq_printf(m, "RLC feature version: %u, firmware version: 0x%08x\n",
11471162 fw_info.feature, fw_info.ver);
11481163
1164+ /* RLC SAVE RESTORE LIST CNTL */
1165+ query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_CNTL;
1166+ ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1167+ if (ret)
1168+ return ret;
1169+ seq_printf(m, "RLC SRLC feature version: %u, firmware version: 0x%08x\n",
1170+ fw_info.feature, fw_info.ver);
1171+
1172+ /* RLC SAVE RESTORE LIST GPM MEM */
1173+ query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_GPM_MEM;
1174+ ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1175+ if (ret)
1176+ return ret;
1177+ seq_printf(m, "RLC SRLG feature version: %u, firmware version: 0x%08x\n",
1178+ fw_info.feature, fw_info.ver);
1179+
1180+ /* RLC SAVE RESTORE LIST SRM MEM */
1181+ query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_SRM_MEM;
1182+ ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1183+ if (ret)
1184+ return ret;
1185+ seq_printf(m, "RLC SRLS feature version: %u, firmware version: 0x%08x\n",
1186+ fw_info.feature, fw_info.ver);
1187+
11491188 /* MEC */
11501189 query_fw.fw_type = AMDGPU_INFO_FW_GFX_MEC;
11511190 query_fw.index = 0;
@@ -1210,6 +1249,9 @@ static int amdgpu_debugfs_firmware_info(struct seq_file *m, void *data) · 58 unmodified lines
12101249 seq_printf(m, "VCN feature version: %u, firmware version: 0x%08x\n",
12111250 fw_info.feature, fw_info.ver);
12121251
1252+
1253+ seq_printf(m, "VBIOS version: %s\n", ctx->vbios_version);
1254+
12131255 return 0;
12141256 }
12151257
drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h+0−1
@@ -308,7 +308,6 @@ struct amdgpu_display_funcs { · 307 unmodified lines
308308
309309 struct amdgpu_framebuffer {
310310 struct drm_framebuffer base;
311− struct drm_gem_object *obj;
312311
313312 /* caching for later use */
314313 uint64_t address;
drivers/gpu/drm/amd/amdgpu/amdgpu_object.c+72−48
@@ -191,14 +191,21 @@ int amdgpu_bo_create_reserved(struct amdgpu_device *adev, · 190 unmodified lines
191191 u32 domain, struct amdgpu_bo **bo_ptr,
192192 u64 *gpu_addr, void **cpu_addr)
193193 {
194+ struct amdgpu_bo_param bp;
194195 bool free = false;
195196 int r;
196197
198+ memset(&bp, 0, sizeof(bp));
199+ bp.size = size;
200+ bp.byte_align = align;
201+ bp.domain = domain;
202+ bp.flags = AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED |
203+ AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS;
204+ bp.type = ttm_bo_type_kernel;
205+ bp.resv = NULL;
206+
197207 if (!*bo_ptr) {
198− r = amdgpu_bo_create(adev, size, align, domain,
199− AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED |
200− AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS,
201− ttm_bo_type_kernel, NULL, bo_ptr);
208+ r = amdgpu_bo_create(adev, &bp, bo_ptr);
202209 if (r) {
203210 dev_err(adev->dev, "(%d) failed to allocate kernel bo\n",
204211 r);
@@ -341,27 +348,25 @@ fail: · 136 unmodified lines
341348 return false;
342349 }
343350
344−static int amdgpu_bo_do_create(struct amdgpu_device *adev, unsigned long size,
345− int byte_align, u32 domain,
346− u64 flags, enum ttm_bo_type type,
347− struct reservation_object *resv,
351+static int amdgpu_bo_do_create(struct amdgpu_device *adev,
352+ struct amdgpu_bo_param *bp,
348353 struct amdgpu_bo **bo_ptr)
349354 {
350355 struct ttm_operation_ctx ctx = {
351− .interruptible = (type != ttm_bo_type_kernel),
356+ .interruptible = (bp->type != ttm_bo_type_kernel),
352357 .no_wait_gpu = false,
353− .resv = resv,
358+ .resv = bp->resv,
354359 .flags = TTM_OPT_FLAG_ALLOW_RES_EVICT
355360 };
356361 struct amdgpu_bo *bo;
357− unsigned long page_align;
362+ unsigned long page_align, size = bp->size;
358363 size_t acc_size;
359364 int r;
360365
361− page_align = roundup(byte_align, PAGE_SIZE) >> PAGE_SHIFT;
366+ page_align = roundup(bp->byte_align, PAGE_SIZE) >> PAGE_SHIFT;
362367 size = ALIGN(size, PAGE_SIZE);
363368
364− if (!amdgpu_bo_validate_size(adev, size, domain))
369+ if (!amdgpu_bo_validate_size(adev, size, bp->domain))
365370 return -ENOMEM;
366371
367372 *bo_ptr = NULL;
@@ -375,18 +380,14 @@ static int amdgpu_bo_do_create(struct amdgpu_device *adev, unsigned long size, · 7 unmodified lines
375380 drm_gem_private_object_init(adev->ddev, &bo->gem_base, size);
376381 INIT_LIST_HEAD(&bo->shadow_list);
377382 INIT_LIST_HEAD(&bo->va);
378− bo->preferred_domains = domain & (AMDGPU_GEM_DOMAIN_VRAM |
379− AMDGPU_GEM_DOMAIN_GTT |
380− AMDGPU_GEM_DOMAIN_CPU |
381− AMDGPU_GEM_DOMAIN_GDS |
382− AMDGPU_GEM_DOMAIN_GWS |
383− AMDGPU_GEM_DOMAIN_OA);
383+ bo->preferred_domains = bp->preferred_domain ? bp->preferred_domain :
384+ bp->domain;
384385 bo->allowed_domains = bo->preferred_domains;
385− if (type != ttm_bo_type_kernel &&
386+ if (bp->type != ttm_bo_type_kernel &&
386387 bo->allowed_domains == AMDGPU_GEM_DOMAIN_VRAM)
387388 bo->allowed_domains |= AMDGPU_GEM_DOMAIN_GTT;
388389
389− bo->flags = flags;
390+ bo->flags = bp->flags;
390391
391392 #ifdef CONFIG_X86_32
392393 /* XXX: Write-combined CPU mappings of GTT seem broken on 32-bit
@@ -417,11 +418,13 @@ static int amdgpu_bo_do_create(struct amdgpu_device *adev, unsigned long size, · 24 unmodified lines
417418 #endif
418419
419420 bo->tbo.bdev = &adev->mman.bdev;
420− amdgpu_ttm_placement_from_domain(bo, domain);
421+ amdgpu_ttm_placement_from_domain(bo, bp->domain);
422+ if (bp->type == ttm_bo_type_kernel)
423+ bo->tbo.priority = 1;
421424
422− r = ttm_bo_init_reserved(&adev->mman.bdev, &bo->tbo, size, type,
425+ r = ttm_bo_init_reserved(&adev->mman.bdev, &bo->tbo, size, bp->type,
423426 &bo->placement, page_align, &ctx, acc_size,
424− NULL, resv, &amdgpu_ttm_bo_destroy);
427+ NULL, bp->resv, &amdgpu_ttm_bo_destroy);
425428 if (unlikely(r != 0))
426429 return r;
427430
@@ -433,10 +436,7 @@ static int amdgpu_bo_do_create(struct amdgpu_device *adev, unsigned long size, · 5 unmodified lines
433436 else
434437 amdgpu_cs_report_moved_bytes(adev, ctx.bytes_moved, 0);
435438
436− if (type == ttm_bo_type_kernel)
437− bo->tbo.priority = 1;
438−
439− if (flags & AMDGPU_GEM_CREATE_VRAM_CLEARED &&
439+ if (bp->flags & AMDGPU_GEM_CREATE_VRAM_CLEARED &&
440440 bo->tbo.mem.placement & TTM_PL_FLAG_VRAM) {
441441 struct dma_fence *fence;
442442
@@ -449,20 +449,20 @@ static int amdgpu_bo_do_create(struct amdgpu_device *adev, unsigned long size, · 6 unmodified lines
449449 bo->tbo.moving = dma_fence_get(fence);
450450 dma_fence_put(fence);
451451 }
452− if (!resv)
452+ if (!bp->resv)
453453 amdgpu_bo_unreserve(bo);
454454 *bo_ptr = bo;
455455
456456 trace_amdgpu_bo_create(bo);
457457
458458 /* Treat CPU_ACCESS_REQUIRED only as a hint if given by UMD */
459− if (type == ttm_bo_type_device)
459+ if (bp->type == ttm_bo_type_device)
460460 bo->flags &= ~AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED;
461461
462462 return 0;
463463
464464 fail_unreserve:
465− if (!resv)
465+ if (!bp->resv)
466466 ww_mutex_unlock(&bo->tbo.resv->lock);
467467 amdgpu_bo_unref(&bo);
468468 return r;
@@ -472,16 +472,22 @@ static int amdgpu_bo_create_shadow(struct amdgpu_device *adev, · 3 unmodified lines
472472 unsigned long size, int byte_align,
473473 struct amdgpu_bo *bo)
474474 {
475+ struct amdgpu_bo_param bp;
475476 int r;
476477
477478 if (bo->shadow)
478479 return 0;
479480
480− r = amdgpu_bo_do_create(adev, size, byte_align, AMDGPU_GEM_DOMAIN_GTT,
481− AMDGPU_GEM_CREATE_CPU_GTT_USWC |
482− AMDGPU_GEM_CREATE_SHADOW,
483− ttm_bo_type_kernel,
484− bo->tbo.resv, &bo->shadow);
481+ memset(&bp, 0, sizeof(bp));
482+ bp.size = size;
483+ bp.byte_align = byte_align;
484+ bp.domain = AMDGPU_GEM_DOMAIN_GTT;
485+ bp.flags = AMDGPU_GEM_CREATE_CPU_GTT_USWC |
486+ AMDGPU_GEM_CREATE_SHADOW;
487+ bp.type = ttm_bo_type_kernel;
488+ bp.resv = bo->tbo.resv;
489+
490+ r = amdgpu_bo_do_create(adev, &bp, &bo->shadow);
485491 if (!r) {
486492 bo->shadow->parent = amdgpu_bo_ref(bo);
487493 mutex_lock(&adev->shadow_list_lock);
@@ -492,28 +498,26 @@ static int amdgpu_bo_create_shadow(struct amdgpu_device *adev, · 4 unmodified lines
492498 return r;
493499 }
494500
495−int amdgpu_bo_create(struct amdgpu_device *adev, unsigned long size,
496− int byte_align, u32 domain,
497− u64 flags, enum ttm_bo_type type,
498− struct reservation_object *resv,
501+int amdgpu_bo_create(struct amdgpu_device *adev,
502+ struct amdgpu_bo_param *bp,
499503 struct amdgpu_bo **bo_ptr)
500504 {
501− uint64_t parent_flags = flags & ~AMDGPU_GEM_CREATE_SHADOW;
505+ u64 flags = bp->flags;
502506 int r;
503507
504− r = amdgpu_bo_do_create(adev, size, byte_align, domain,
505− parent_flags, type, resv, bo_ptr);
508+ bp->flags = bp->flags & ~AMDGPU_GEM_CREATE_SHADOW;
509+ r = amdgpu_bo_do_create(adev, bp, bo_ptr);
506510 if (r)
507511 return r;
508512
509513 if ((flags & AMDGPU_GEM_CREATE_SHADOW) && amdgpu_need_backup(adev)) {
510− if (!resv)
514+ if (!bp->resv)
511515 WARN_ON(reservation_object_lock((*bo_ptr)->tbo.resv,
512516 NULL));
513517
514− r = amdgpu_bo_create_shadow(adev, size, byte_align, (*bo_ptr));
518+ r = amdgpu_bo_create_shadow(adev, bp->size, bp->byte_align, (*bo_ptr));
515519
516− if (!resv)
520+ if (!bp->resv)
517521 reservation_object_unlock((*bo_ptr)->tbo.resv);
518522
519523 if (r)
@@ -689,8 +693,21 @@ int amdgpu_bo_pin_restricted(struct amdgpu_bo *bo, u32 domain, · 169 unmodified lines
689693 return -EINVAL;
690694
691695 /* A shared bo cannot be migrated to VRAM */
692− if (bo->prime_shared_count && (domain == AMDGPU_GEM_DOMAIN_VRAM))
693− return -EINVAL;
696+ if (bo->prime_shared_count) {
697+ if (domain & AMDGPU_GEM_DOMAIN_GTT)
698+ domain = AMDGPU_GEM_DOMAIN_GTT;
699+ else
700+ return -EINVAL;
701+ }
702+
703+ /* This assumes only APU display buffers are pinned with (VRAM|GTT).
704+ * See function amdgpu_display_supported_domains()
705+ */
706+ if (domain == (AMDGPU_GEM_DOMAIN_VRAM | AMDGPU_GEM_DOMAIN_GTT)) {
707+ domain = AMDGPU_GEM_DOMAIN_VRAM;
708+ if (adev->gmc.real_vram_size <= AMDGPU_SG_THRESHOLD)
709+ domain = AMDGPU_GEM_DOMAIN_GTT;
710+ }
694711
695712 if (bo->pin_count) {
696713 uint32_t mem_type = bo->tbo.mem.mem_type;
@@ -838,6 +855,13 @@ int amdgpu_bo_init(struct amdgpu_device *adev) · 141 unmodified lines
838855 return amdgpu_ttm_init(adev);
839856 }
840857
858+int amdgpu_bo_late_init(struct amdgpu_device *adev)
859+{
860+ amdgpu_ttm_late_init(adev);
861+
862+ return 0;
863+}
864+
841865 void amdgpu_bo_fini(struct amdgpu_device *adev)
842866 {
843867 amdgpu_ttm_fini(adev);
drivers/gpu/drm/amd/amdgpu/amdgpu_object.h+34−4
@@ -33,6 +33,16 @@ · 32 unmodified lines
3333
3434 #define AMDGPU_BO_INVALID_OFFSET LONG_MAX
3535
36+struct amdgpu_bo_param {
37+ unsigned long size;
38+ int byte_align;
39+ u32 domain;
40+ u32 preferred_domain;
41+ u64 flags;
42+ enum ttm_bo_type type;
43+ struct reservation_object *resv;
44+};
45+
3646 /* bo virtual addresses in a vm */
3747 struct amdgpu_bo_va_mapping {
3848 struct amdgpu_bo_va *bo_va;
@@ -195,6 +205,27 @@ static inline bool amdgpu_bo_gpu_accessible(struct amdgpu_bo *bo) · 156 unmodified lines
195205 }
196206 }
197207
208+/**
209+ * amdgpu_bo_in_cpu_visible_vram - check if BO is (partly) in visible VRAM
210+ */
211+static inline bool amdgpu_bo_in_cpu_visible_vram(struct amdgpu_bo *bo)
212+{
213+ struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
214+ unsigned fpfn = adev->gmc.visible_vram_size >> PAGE_SHIFT;
215+ struct drm_mm_node *node = bo->tbo.mem.mm_node;
216+ unsigned long pages_left;
217+
218+ if (bo->tbo.mem.mem_type != TTM_PL_VRAM)
219+ return false;
220+
221+ for (pages_left = bo->tbo.mem.num_pages; pages_left;
222+ pages_left -= node->size, node++)
223+ if (node->start < fpfn)
224+ return true;
225+
226+ return false;
227+}
228+
198229 /**
199230 * amdgpu_bo_explicit_sync - return whether the bo is explicitly synced
200231 */
@@ -203,10 +234,8 @@ static inline bool amdgpu_bo_explicit_sync(struct amdgpu_bo *bo) · 2 unmodified lines
203234 return bo->flags & AMDGPU_GEM_CREATE_EXPLICIT_SYNC;
204235 }
205236
206−int amdgpu_bo_create(struct amdgpu_device *adev, unsigned long size,
207− int byte_align, u32 domain,
208− u64 flags, enum ttm_bo_type type,
209− struct reservation_object *resv,
237+int amdgpu_bo_create(struct amdgpu_device *adev,
238+ struct amdgpu_bo_param *bp,
210239 struct amdgpu_bo **bo_ptr);
211240 int amdgpu_bo_create_reserved(struct amdgpu_device *adev,
212241 unsigned long size, int align,
@@ -230,6 +259,7 @@ int amdgpu_bo_pin_restricted(struct amdgpu_bo *bo, u32 domain, · 17 unmodified lines
230259 int amdgpu_bo_unpin(struct amdgpu_bo *bo);
231260 int amdgpu_bo_evict_vram(struct amdgpu_device *adev);
232261 int amdgpu_bo_init(struct amdgpu_device *adev);
262+int amdgpu_bo_late_init(struct amdgpu_device *adev);
233263 void amdgpu_bo_fini(struct amdgpu_device *adev);
234264 int amdgpu_bo_fbdev_mmap(struct amdgpu_bo *bo,
235265 struct vm_area_struct *vma);
drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c+282−83
@@ -77,6 +77,37 @@ void amdgpu_pm_acpi_event_handler(struct amdgpu_device *adev) · 76 unmodified lines
7777 }
7878 }
7979
80+/**
81+ * DOC: power_dpm_state
82+ *
83+ * This is a legacy interface and is only provided for backwards compatibility.
84+ * The amdgpu driver provides a sysfs API for adjusting certain power
85+ * related parameters. The file power_dpm_state is used for this.
86+ * It accepts the following arguments:
87+ * - battery
88+ * - balanced
89+ * - performance
90+ *
91+ * battery
92+ *
93+ * On older GPUs, the vbios provided a special power state for battery
94+ * operation. Selecting battery switched to this state. This is no
95+ * longer provided on newer GPUs so the option does nothing in that case.
96+ *
97+ * balanced
98+ *
99+ * On older GPUs, the vbios provided a special power state for balanced
100+ * operation. Selecting balanced switched to this state. This is no
101+ * longer provided on newer GPUs so the option does nothing in that case.
102+ *
103+ * performance
104+ *
105+ * On older GPUs, the vbios provided a special power state for performance
106+ * operation. Selecting performance switched to this state. This is no
107+ * longer provided on newer GPUs so the option does nothing in that case.
108+ *
109+ */
110+
80111 static ssize_t amdgpu_get_dpm_state(struct device *dev,
81112 struct device_attribute *attr,
82113 char *buf)
@@ -131,6 +162,59 @@ fail: · 48 unmodified lines
131162 return count;
132163 }
133164
165+
166+/**
167+ * DOC: power_dpm_force_performance_level
168+ *
169+ * The amdgpu driver provides a sysfs API for adjusting certain power
170+ * related parameters. The file power_dpm_force_performance_level is
171+ * used for this. It accepts the following arguments:
172+ * - auto
173+ * - low
174+ * - high
175+ * - manual
176+ * - GPU fan
177+ * - profile_standard
178+ * - profile_min_sclk
179+ * - profile_min_mclk
180+ * - profile_peak
181+ *
182+ * auto
183+ *
184+ * When auto is selected, the driver will attempt to dynamically select
185+ * the optimal power profile for current conditions in the driver.
186+ *
187+ * low
188+ *
189+ * When low is selected, the clocks are forced to the lowest power state.
190+ *
191+ * high
192+ *
193+ * When high is selected, the clocks are forced to the highest power state.
194+ *
195+ * manual
196+ *
197+ * When manual is selected, the user can manually adjust which power states
198+ * are enabled for each clock domain via the sysfs pp_dpm_mclk, pp_dpm_sclk,
199+ * and pp_dpm_pcie files and adjust the power state transition heuristics
200+ * via the pp_power_profile_mode sysfs file.
201+ *
202+ * profile_standard
203+ * profile_min_sclk
204+ * profile_min_mclk
205+ * profile_peak
206+ *
207+ * When the profiling modes are selected, clock and power gating are
208+ * disabled and the clocks are set for different profiling cases. This
209+ * mode is recommended for profiling specific work loads where you do
210+ * not want clock or power gating for clock fluctuation to interfere
211+ * with your results. profile_standard sets the clocks to a fixed clock
212+ * level which varies from asic to asic. profile_min_sclk forces the sclk
213+ * to the lowest level. profile_min_mclk forces the mclk to the lowest level.
214+ * profile_peak sets all clocks (mclk, sclk, pcie) to the highest levels.
215+ *
216+ */
217+
134218 static ssize_t amdgpu_get_dpm_forced_performance_level(struct device *dev,
135219 struct device_attribute *attr,
136220 char *buf)
@@ -324,6 +408,17 @@ fail: · 187 unmodified lines
324408 return count;
325409 }
326410
411+/**
412+ * DOC: pp_table
413+ *
414+ * The amdgpu driver provides a sysfs API for uploading new powerplay
415+ * tables. The file pp_table is used for this. Reading the file
416+ * will dump the current power play table. Writing to the file
417+ * will attempt to upload a new powerplay table and re-initialize
418+ * powerplay using that new table.
419+ *
420+ */
421+
327422 static ssize_t amdgpu_get_pp_table(struct device *dev,
328423 struct device_attribute *attr,
329424 char *buf)
@@ -360,6 +455,29 @@ static ssize_t amdgpu_set_pp_table(struct device *dev, · 30 unmodified lines
360455 return count;
361456 }
362457
458+/**
459+ * DOC: pp_od_clk_voltage
460+ *
461+ * The amdgpu driver provides a sysfs API for adjusting the clocks and voltages
462+ * in each power level within a power state. The pp_od_clk_voltage is used for
463+ * this.
464+ *
465+ * Reading the file will display:
466+ * - a list of engine clock levels and voltages labeled OD_SCLK
467+ * - a list of memory clock levels and voltages labeled OD_MCLK
468+ * - a list of valid ranges for sclk, mclk, and voltage labeled OD_RANGE
469+ *
470+ * To manually adjust these settings, first select manual using
471+ * power_dpm_force_performance_level. Enter a new value for each
472+ * level by writing a string that contains "s/m level clock voltage" to
473+ * the file. E.g., "s 1 500 820" will update sclk level 1 to be 500 MHz
474+ * at 820 mV; "m 0 350 810" will update mclk level 0 to be 350 MHz at
475+ * 810 mV. When you have edited all of the states as needed, write
476+ * "c" (commit) to the file to commit your changes. If you want to reset to the
477+ * default power levels, write "r" (reset) to the file to reset them.
478+ *
479+ */
480+
363481 static ssize_t amdgpu_set_pp_od_clk_voltage(struct device *dev,
364482 struct device_attribute *attr,
365483 const char *buf,
@@ -437,6 +555,7 @@ static ssize_t amdgpu_get_pp_od_clk_voltage(struct device *dev, · 71 unmodified lines
437555 if (adev->powerplay.pp_funcs->print_clock_levels) {
438556 size = amdgpu_dpm_print_clock_levels(adev, OD_SCLK, buf);
439557 size += amdgpu_dpm_print_clock_levels(adev, OD_MCLK, buf+size);
558+ size += amdgpu_dpm_print_clock_levels(adev, OD_RANGE, buf+size);
440559 return size;
441560 } else {
442561 return snprintf(buf, PAGE_SIZE, "\n");
@@ -444,6 +563,23 @@ static ssize_t amdgpu_get_pp_od_clk_voltage(struct device *dev, · 1 unmodified line
444563
445564 }
446565
566+/**
567+ * DOC: pp_dpm_sclk pp_dpm_mclk pp_dpm_pcie
568+ *
569+ * The amdgpu driver provides a sysfs API for adjusting what power levels
570+ * are enabled for a given power state. The files pp_dpm_sclk, pp_dpm_mclk,
571+ * and pp_dpm_pcie are used for this.
572+ *
573+ * Reading back the files will show you the available power levels within
574+ * the power state and the clock information for those levels.
575+ *
576+ * To manually adjust these states, first select manual using
577+ * power_dpm_force_performance_level.
578+ * Secondly,Enter a new value for each level by inputing a string that
579+ * contains " echo xx xx xx > pp_dpm_sclk/mclk/pcie"
580+ * E.g., echo 4 5 6 to > pp_dpm_sclk will enable sclk levels 4, 5, and 6.
581+ */
582+
447583 static ssize_t amdgpu_get_pp_dpm_sclk(struct device *dev,
448584 struct device_attribute *attr,
449585 char *buf)
@@ -466,23 +602,27 @@ static ssize_t amdgpu_set_pp_dpm_sclk(struct device *dev, · 16 unmodified lines
466602 struct amdgpu_device *adev = ddev->dev_private;
467603 int ret;
468604 long level;
469− uint32_t i, mask = 0;
470− char sub_str[2];
605+ uint32_t mask = 0;
606+ char *sub_str = NULL;
607+ char *tmp;
608+ char buf_cpy[count];
609+ const char delimiter[3] = {' ', '\n', '\0'};
471610
472− for (i = 0; i < strlen(buf); i++) {
473− if (*(buf + i) == '\n')
474− continue;
475− sub_str[0] = *(buf + i);
476− sub_str[1] = '\0';
477− ret = kstrtol(sub_str, 0, &level);
611+ memcpy(buf_cpy, buf, count+1);
612+ tmp = buf_cpy;
613+ while (tmp[0]) {
614+ sub_str = strsep(&tmp, delimiter);
615+ if (strlen(sub_str)) {
616+ ret = kstrtol(sub_str, 0, &level);
478617
479− if (ret) {
480− count = -EINVAL;
481− goto fail;
482− }
483− mask |= 1 << level;
618+ if (ret) {
619+ count = -EINVAL;
620+ goto fail;
621+ }
622+ mask |= 1 << level;
623+ } else
624+ break;
484625 }
485−
486626 if (adev->powerplay.pp_funcs->force_clock_level)
487627 amdgpu_dpm_force_clock_level(adev, PP_SCLK, mask);
488628
@@ -512,21 +652,26 @@ static ssize_t amdgpu_set_pp_dpm_mclk(struct device *dev, · 23 unmodified lines
512652 struct amdgpu_device *adev = ddev->dev_private;
513653 int ret;
514654 long level;
515− uint32_t i, mask = 0;
516− char sub_str[2];
655+ uint32_t mask = 0;
656+ char *sub_str = NULL;
657+ char *tmp;
658+ char buf_cpy[count];
659+ const char delimiter[3] = {' ', '\n', '\0'};
517660
518− for (i = 0; i < strlen(buf); i++) {
519− if (*(buf + i) == '\n')
520− continue;
521− sub_str[0] = *(buf + i);
522− sub_str[1] = '\0';
523− ret = kstrtol(sub_str, 0, &level);
661+ memcpy(buf_cpy, buf, count+1);
662+ tmp = buf_cpy;
663+ while (tmp[0]) {
664+ sub_str = strsep(&tmp, delimiter);
665+ if (strlen(sub_str)) {
666+ ret = kstrtol(sub_str, 0, &level);
524667
525− if (ret) {
526− count = -EINVAL;
527− goto fail;
528− }
529− mask |= 1 << level;
668+ if (ret) {
669+ count = -EINVAL;
670+ goto fail;
671+ }
672+ mask |= 1 << level;
673+ } else
674+ break;
530675 }
531676 if (adev->powerplay.pp_funcs->force_clock_level)
532677 amdgpu_dpm_force_clock_level(adev, PP_MCLK, mask);
@@ -557,21 +702,27 @@ static ssize_t amdgpu_set_pp_dpm_pcie(struct device *dev, · 24 unmodified lines
557702 struct amdgpu_device *adev = ddev->dev_private;
558703 int ret;
559704 long level;
560− uint32_t i, mask = 0;
561− char sub_str[2];
705+ uint32_t mask = 0;
706+ char *sub_str = NULL;
707+ char *tmp;
708+ char buf_cpy[count];
709+ const char delimiter[3] = {' ', '\n', '\0'};
562710
563− for (i = 0; i < strlen(buf); i++) {
564− if (*(buf + i) == '\n')
565− continue;
566− sub_str[0] = *(buf + i);
567− sub_str[1] = '\0';
568− ret = kstrtol(sub_str, 0, &level);
711+ memcpy(buf_cpy, buf, count+1);
712+ tmp = buf_cpy;
569713
570− if (ret) {
571− count = -EINVAL;
572− goto fail;
573− }
574− mask |= 1 << level;
714+ while (tmp[0]) {
715+ sub_str = strsep(&tmp, delimiter);
716+ if (strlen(sub_str)) {
717+ ret = kstrtol(sub_str, 0, &level);
718+
719+ if (ret) {
720+ count = -EINVAL;
721+ goto fail;
722+ }
723+ mask |= 1 << level;
724+ } else
725+ break;
575726 }
576727 if (adev->powerplay.pp_funcs->force_clock_level)
577728 amdgpu_dpm_force_clock_level(adev, PP_PCIE, mask);
@@ -668,6 +819,26 @@ fail: · 90 unmodified lines
668819 return count;
669820 }
670821
822+/**
823+ * DOC: pp_power_profile_mode
824+ *
825+ * The amdgpu driver provides a sysfs API for adjusting the heuristics
826+ * related to switching between power levels in a power state. The file
827+ * pp_power_profile_mode is used for this.
828+ *
829+ * Reading this file outputs a list of all of the predefined power profiles
830+ * and the relevant heuristics settings for that profile.
831+ *
832+ * To select a profile or create a custom profile, first select manual using
833+ * power_dpm_force_performance_level. Writing the number of a predefined
834+ * profile to pp_power_profile_mode will enable those heuristics. To
835+ * create a custom set of heuristics, write a string of numbers to the file
836+ * starting with the number of the custom profile along with a setting
837+ * for each heuristic parameter. Due to differences across asic families
838+ * the heuristic parameters vary from family to family.
839+ *
840+ */
841+
671842 static ssize_t amdgpu_get_pp_power_profile_mode(struct device *dev,
672843 struct device_attribute *attr,
673844 char *buf)
@@ -1020,8 +1191,8 @@ static ssize_t amdgpu_hwmon_show_power_avg(struct device *dev, · 346 unmodified lines
10201191 {
10211192 struct amdgpu_device *adev = dev_get_drvdata(dev);
10221193 struct drm_device *ddev = adev->ddev;
1023− struct pp_gpu_power query = {0};
1024− int r, size = sizeof(query);
1194+ u32 query = 0;
1195+ int r, size = sizeof(u32);
10251196 unsigned uw;
10261197
10271198 /* Can't get power when the card is off */
@@ -1041,7 +1212,7 @@ static ssize_t amdgpu_hwmon_show_power_avg(struct device *dev, · 13 unmodified lines
10411212 return r;
10421213
10431214 /* convert to microwatts */
1044− uw = (query.average_gpu_power >> 8) * 1000000;
1215+ uw = (query >> 8) * 1000000 + (query & 0xff) * 1000;
10451216
10461217 return snprintf(buf, PAGE_SIZE, "%u\n", uw);
10471218 }
@@ -1109,6 +1280,46 @@ static ssize_t amdgpu_hwmon_set_power_cap(struct device *dev, · 61 unmodified lines
11091280 return count;
11101281 }
11111282
1283+
1284+/**
1285+ * DOC: hwmon
1286+ *
1287+ * The amdgpu driver exposes the following sensor interfaces:
1288+ * - GPU temperature (via the on-die sensor)
1289+ * - GPU voltage
1290+ * - Northbridge voltage (APUs only)
1291+ * - GPU power
1292+ * - GPU fan
1293+ *
1294+ * hwmon interfaces for GPU temperature:
1295+ * - temp1_input: the on die GPU temperature in millidegrees Celsius
1296+ * - temp1_crit: temperature critical max value in millidegrees Celsius
1297+ * - temp1_crit_hyst: temperature hysteresis for critical limit in millidegrees Celsius
1298+ *
1299+ * hwmon interfaces for GPU voltage:
1300+ * - in0_input: the voltage on the GPU in millivolts
1301+ * - in1_input: the voltage on the Northbridge in millivolts
1302+ *
1303+ * hwmon interfaces for GPU power:
1304+ * - power1_average: average power used by the GPU in microWatts
1305+ * - power1_cap_min: minimum cap supported in microWatts
1306+ * - power1_cap_max: maximum cap supported in microWatts
1307+ * - power1_cap: selected power cap in microWatts
1308+ *
1309+ * hwmon interfaces for GPU fan:
1310+ * - pwm1: pulse width modulation fan level (0-255)
1311+ * - pwm1_enable: pulse width modulation fan control method
1312+ * 0: no fan speed control
1313+ * 1: manual fan speed control using pwm interface
1314+ * 2: automatic fan speed control
1315+ * - pwm1_min: pulse width modulation fan control minimum level (0)
1316+ * - pwm1_max: pulse width modulation fan control maximum level (255)
1317+ * - fan1_input: fan speed in RPM
1318+ *
1319+ * You can use hwmon tools like sensors to view this information on your system.
1320+ *
1321+ */
1322+
11121323 static SENSOR_DEVICE_ATTR(temp1_input, S_IRUGO, amdgpu_hwmon_show_temp, NULL, 0);
11131324 static SENSOR_DEVICE_ATTR(temp1_crit, S_IRUGO, amdgpu_hwmon_show_temp_thresh, NULL, 0);
11141325 static SENSOR_DEVICE_ATTR(temp1_crit_hyst, S_IRUGO, amdgpu_hwmon_show_temp_thresh, NULL, 1);
@@ -1153,19 +1364,14 @@ static umode_t hwmon_attributes_visible(struct kobject *kobj, · 38 unmodified lines
11531364 struct amdgpu_device *adev = dev_get_drvdata(dev);
11541365 umode_t effective_mode = attr->mode;
11551366
1156− /* handle non-powerplay limitations */
1157− if (!adev->powerplay.pp_handle) {
1158− /* Skip fan attributes if fan is not present */
1159− if (adev->pm.no_fan &&
1160− (attr == &sensor_dev_attr_pwm1.dev_attr.attr ||
1161− attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr ||
1162− attr == &sensor_dev_attr_pwm1_max.dev_attr.attr ||
1163− attr == &sensor_dev_attr_pwm1_min.dev_attr.attr))
1164− return 0;
1165− /* requires powerplay */
1166− if (attr == &sensor_dev_attr_fan1_input.dev_attr.attr)
1167− return 0;
1168− }
1367+
1368+ /* Skip fan attributes if fan is not present */
1369+ if (adev->pm.no_fan && (attr == &sensor_dev_attr_pwm1.dev_attr.attr ||
1370+ attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr ||
1371+ attr == &sensor_dev_attr_pwm1_max.dev_attr.attr ||
1372+ attr == &sensor_dev_attr_pwm1_min.dev_attr.attr ||
1373+ attr == &sensor_dev_attr_fan1_input.dev_attr.attr))
1374+ return 0;
11691375
11701376 /* Skip limit attributes if DPM is not enabled */
11711377 if (!adev->pm.dpm_enabled &&
@@ -1658,9 +1864,6 @@ void amdgpu_pm_sysfs_fini(struct amdgpu_device *adev) · 486 unmodified lines
16581864
16591865 void amdgpu_pm_compute_clocks(struct amdgpu_device *adev)
16601866 {
1661− struct drm_device *ddev = adev->ddev;
1662− struct drm_crtc *crtc;
1663− struct amdgpu_crtc *amdgpu_crtc;
16641867 int i = 0;
16651868
16661869 if (!adev->pm.dpm_enabled)
@@ -1676,21 +1879,25 @@ void amdgpu_pm_compute_clocks(struct amdgpu_device *adev) · 9 unmodified lines
16761879 }
16771880
16781881 if (adev->powerplay.pp_funcs->dispatch_tasks) {
1882+ if (!amdgpu_device_has_dc_support(adev)) {
1883+ mutex_lock(&adev->pm.mutex);
1884+ amdgpu_dpm_get_active_displays(adev);
1885+ adev->pm.pm_display_cfg.num_display = adev->pm.dpm.new_active_crtcs;
1886+ adev->pm.pm_display_cfg.vrefresh = amdgpu_dpm_get_vrefresh(adev);
1887+ adev->pm.pm_display_cfg.min_vblank_time = amdgpu_dpm_get_vblank_time(adev);
1888+ /* we have issues with mclk switching with refresh rates over 120 hz on the non-DC code. */
1889+ if (adev->pm.pm_display_cfg.vrefresh > 120)
1890+ adev->pm.pm_display_cfg.min_vblank_time = 0;
1891+ if (adev->powerplay.pp_funcs->display_configuration_change)
1892+ adev->powerplay.pp_funcs->display_configuration_change(
1893+ adev->powerplay.pp_handle,
1894+ &adev->pm.pm_display_cfg);
1895+ mutex_unlock(&adev->pm.mutex);
1896+ }
16791897 amdgpu_dpm_dispatch_task(adev, AMD_PP_TASK_DISPLAY_CONFIG_CHANGE, NULL);
16801898 } else {
16811899 mutex_lock(&adev->pm.mutex);
1682− adev->pm.dpm.new_active_crtcs = 0;
1683− adev->pm.dpm.new_active_crtc_count = 0;
1684− if (adev->mode_info.num_crtc && adev->mode_info.mode_config_initialized) {
1685− list_for_each_entry(crtc,
1686− &ddev->mode_config.crtc_list, head) {
1687− amdgpu_crtc = to_amdgpu_crtc(crtc);
1688− if (amdgpu_crtc->enabled) {
1689− adev->pm.dpm.new_active_crtcs |= (1 << amdgpu_crtc->crtc_id);
1690− adev->pm.dpm.new_active_crtc_count++;
1691− }
1692− }
1693− }
1900+ amdgpu_dpm_get_active_displays(adev);
16941901 /* update battery/ac status */
16951902 if (power_supply_is_system_supplied() > 0)
16961903 adev->pm.dpm.ac_power = true;
@@ -1711,7 +1918,7 @@ void amdgpu_pm_compute_clocks(struct amdgpu_device *adev) · 14 unmodified lines
17111918 static int amdgpu_debugfs_pm_info_pp(struct seq_file *m, struct amdgpu_device *adev)
17121919 {
17131920 uint32_t value;
1714− struct pp_gpu_power query = {0};
1921+ uint32_t query = 0;
17151922 int size;
17161923
17171924 /* sanity check PP is enabled */
@@ -1734,17 +1941,9 @@ static int amdgpu_debugfs_pm_info_pp(struct seq_file *m, struct amdgpu_device *a · 16 unmodified lines
17341941 seq_printf(m, "\t%u mV (VDDGFX)\n", value);
17351942 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VDDNB, (void *)&value, &size))
17361943 seq_printf(m, "\t%u mV (VDDNB)\n", value);
1737− size = sizeof(query);
1738− if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GPU_POWER, (void *)&query, &size)) {
1739− seq_printf(m, "\t%u.%u W (VDDC)\n", query.vddc_power >> 8,
1740− query.vddc_power & 0xff);
1741− seq_printf(m, "\t%u.%u W (VDDCI)\n", query.vddci_power >> 8,
1742− query.vddci_power & 0xff);
1743− seq_printf(m, "\t%u.%u W (max GPU)\n", query.max_gpu_power >> 8,
1744− query.max_gpu_power & 0xff);
1745− seq_printf(m, "\t%u.%u W (average GPU)\n", query.average_gpu_power >> 8,
1746− query.average_gpu_power & 0xff);
1747− }
1944+ size = sizeof(uint32_t);
1945+ if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GPU_POWER, (void *)&query, &size))
1946+ seq_printf(m, "\t%u.%u W (average GPU)\n", query >> 8, query & 0xff);
17481947 size = sizeof(value);
17491948 seq_printf(m, "\n");
17501949
drivers/gpu/drm/amd/amdgpu/amdgpu_prime.c+10−4
@@ -102,12 +102,18 @@ amdgpu_gem_prime_import_sg_table(struct drm_device *dev, · 101 unmodified lines
102102 struct reservation_object *resv = attach->dmabuf->resv;
103103 struct amdgpu_device *adev = dev->dev_private;
104104 struct amdgpu_bo *bo;
105+ struct amdgpu_bo_param bp;
105106 int ret;
106107
108+ memset(&bp, 0, sizeof(bp));
109+ bp.size = attach->dmabuf->size;
110+ bp.byte_align = PAGE_SIZE;
111+ bp.domain = AMDGPU_GEM_DOMAIN_CPU;
112+ bp.flags = 0;
113+ bp.type = ttm_bo_type_sg;
114+ bp.resv = resv;
107115 ww_mutex_lock(&resv->lock, NULL);
108− ret = amdgpu_bo_create(adev, attach->dmabuf->size, PAGE_SIZE,
109− AMDGPU_GEM_DOMAIN_CPU, 0, ttm_bo_type_sg,
110− resv, &bo);
116+ ret = amdgpu_bo_create(adev, &bp, &bo);
111117 if (ret)
112118 goto error;
113119
@@ -209,7 +215,7 @@ static int amdgpu_gem_begin_cpu_access(struct dma_buf *dma_buf, · 95 unmodified lines
209215 struct amdgpu_bo *bo = gem_to_amdgpu_bo(dma_buf->priv);
210216 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
211217 struct ttm_operation_ctx ctx = { true, false };
212− u32 domain = amdgpu_display_framebuffer_domains(adev);
218+ u32 domain = amdgpu_display_supported_domains(adev);
213219 int ret;
214220 bool reads = (direction == DMA_BIDIRECTIONAL ||
215221 direction == DMA_FROM_DEVICE);
drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c+20−0
@@ -459,6 +459,26 @@ void amdgpu_ring_lru_touch(struct amdgpu_device *adev, struct amdgpu_ring *ring) · 458 unmodified lines
459459 spin_unlock(&adev->ring_lru_list_lock);
460460 }
461461
462+/**
463+ * amdgpu_ring_emit_reg_write_reg_wait_helper - ring helper
464+ *
465+ * @adev: amdgpu_device pointer
466+ * @reg0: register to write
467+ * @reg1: register to wait on
468+ * @ref: reference value to write/wait on
469+ * @mask: mask to wait on
470+ *
471+ * Helper for rings that don't support write and wait in a
472+ * single oneshot packet.
473+ */
474+void amdgpu_ring_emit_reg_write_reg_wait_helper(struct amdgpu_ring *ring,
475+ uint32_t reg0, uint32_t reg1,
476+ uint32_t ref, uint32_t mask)
477+{
478+ amdgpu_ring_emit_wreg(ring, reg0, ref);
479+ amdgpu_ring_emit_reg_wait(ring, reg1, mask, mask);
480+}
481+
462482 /*
463483 * Debugfs info
464484 */
drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h+10−1
@@ -42,6 +42,7 @@ · 41 unmodified lines
4242
4343 #define AMDGPU_FENCE_FLAG_64BIT (1 << 0)
4444 #define AMDGPU_FENCE_FLAG_INT (1 << 1)
45+#define AMDGPU_FENCE_FLAG_TC_WB_ONLY (1 << 2)
4546
4647 enum amdgpu_ring_type {
4748 AMDGPU_RING_TYPE_GFX,
@@ -90,7 +91,8 @@ int amdgpu_fence_driver_start_ring(struct amdgpu_ring *ring, · 42 unmodified lines
9091 unsigned irq_type);
9192 void amdgpu_fence_driver_suspend(struct amdgpu_device *adev);
9293 void amdgpu_fence_driver_resume(struct amdgpu_device *adev);
93−int amdgpu_fence_emit(struct amdgpu_ring *ring, struct dma_fence **fence);
94+int amdgpu_fence_emit(struct amdgpu_ring *ring, struct dma_fence **fence,
95+ unsigned flags);
9496 int amdgpu_fence_emit_polling(struct amdgpu_ring *ring, uint32_t *s);
9597 void amdgpu_fence_process(struct amdgpu_ring *ring);
9698 int amdgpu_fence_wait_empty(struct amdgpu_ring *ring);
@@ -154,6 +156,9 @@ struct amdgpu_ring_funcs { · 57 unmodified lines
154156 void (*emit_wreg)(struct amdgpu_ring *ring, uint32_t reg, uint32_t val);
155157 void (*emit_reg_wait)(struct amdgpu_ring *ring, uint32_t reg,
156158 uint32_t val, uint32_t mask);
159+ void (*emit_reg_write_reg_wait)(struct amdgpu_ring *ring,
160+ uint32_t reg0, uint32_t reg1,
161+ uint32_t ref, uint32_t mask);
157162 void (*emit_tmz)(struct amdgpu_ring *ring, bool start);
158163 /* priority functions */
159164 void (*set_priority) (struct amdgpu_ring *ring,
@@ -228,6 +233,10 @@ int amdgpu_ring_lru_get(struct amdgpu_device *adev, int type, · 68 unmodified lines
228233 int *blacklist, int num_blacklist,
229234 bool lru_pipe_order, struct amdgpu_ring **ring);
230235 void amdgpu_ring_lru_touch(struct amdgpu_device *adev, struct amdgpu_ring *ring);
236+void amdgpu_ring_emit_reg_write_reg_wait_helper(struct amdgpu_ring *ring,
237+ uint32_t reg0, uint32_t val0,
238+ uint32_t reg1, uint32_t val1);
239+
231240 static inline void amdgpu_ring_clear_ring(struct amdgpu_ring *ring)
232241 {
233242 int i = 0;
drivers/gpu/drm/amd/amdgpu/amdgpu_test.c+12−6
@@ -33,6 +33,7 @@ static void amdgpu_do_test_moves(struct amdgpu_device *adev) · 32 unmodified lines
3333 struct amdgpu_ring *ring = adev->mman.buffer_funcs_ring;
3434 struct amdgpu_bo *vram_obj = NULL;
3535 struct amdgpu_bo **gtt_obj = NULL;
36+ struct amdgpu_bo_param bp;
3637 uint64_t gart_addr, vram_addr;
3738 unsigned n, size;
3839 int i, r;
@@ -58,9 +59,15 @@ static void amdgpu_do_test_moves(struct amdgpu_device *adev) · 19 unmodified lines
5859 r = 1;
5960 goto out_cleanup;
6061 }
61−
62− r = amdgpu_bo_create(adev, size, PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM, 0,
63− ttm_bo_type_kernel, NULL, &vram_obj);
62+ memset(&bp, 0, sizeof(bp));
63+ bp.size = size;
64+ bp.byte_align = PAGE_SIZE;
65+ bp.domain = AMDGPU_GEM_DOMAIN_VRAM;
66+ bp.flags = 0;
67+ bp.type = ttm_bo_type_kernel;
68+ bp.resv = NULL;
69+
70+ r = amdgpu_bo_create(adev, &bp, &vram_obj);
6471 if (r) {
6572 DRM_ERROR("Failed to create VRAM object\n");
6673 goto out_cleanup;
@@ -79,9 +86,8 @@ static void amdgpu_do_test_moves(struct amdgpu_device *adev) · 12 unmodified lines
7986 void **vram_start, **vram_end;
8087 struct dma_fence *fence = NULL;
8188
82− r = amdgpu_bo_create(adev, size, PAGE_SIZE,
83− AMDGPU_GEM_DOMAIN_GTT, 0,
84− ttm_bo_type_kernel, NULL, gtt_obj + i);
89+ bp.domain = AMDGPU_GEM_DOMAIN_GTT;
90+ r = amdgpu_bo_create(adev, &bp, gtt_obj + i);
8591 if (r) {
8692 DRM_ERROR("Failed to create GTT object %d\n", i);
8793 goto out_lclean;
drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h+1−1
@@ -275,7 +275,7 @@ TRACE_EVENT(amdgpu_vm_bo_unmap, · 274 unmodified lines
275275 ),
276276
277277 TP_fast_assign(
278− __entry->bo = bo_va->base.bo;
278+ __entry->bo = bo_va ? bo_va->base.bo : NULL;
279279 __entry->start = mapping->start;
280280 __entry->last = mapping->last;
281281 __entry->offset = mapping->offset;
drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c+71−39
@@ -111,7 +111,7 @@ static int amdgpu_ttm_global_init(struct amdgpu_device *adev) · 110 unmodified lines
111111 ring = adev->mman.buffer_funcs_ring;
112112 rq = &ring->sched.sched_rq[DRM_SCHED_PRIORITY_KERNEL];
113113 r = drm_sched_entity_init(&ring->sched, &adev->mman.entity,
114− rq, amdgpu_sched_jobs, NULL);
114+ rq, NULL);
115115 if (r) {
116116 DRM_ERROR("Failed setting up TTM BO move run queue.\n");
117117 goto error_entity;
@@ -223,20 +223,8 @@ static void amdgpu_evict_flags(struct ttm_buffer_object *bo, · 105 unmodified lines
223223 if (!adev->mman.buffer_funcs_enabled) {
224224 amdgpu_ttm_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_CPU);
225225 } else if (adev->gmc.visible_vram_size < adev->gmc.real_vram_size &&
226− !(abo->flags & AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED)) {
227− unsigned fpfn = adev->gmc.visible_vram_size >> PAGE_SHIFT;
228− struct drm_mm_node *node = bo->mem.mm_node;
229− unsigned long pages_left;
230−
231− for (pages_left = bo->mem.num_pages;
232− pages_left;
233− pages_left -= node->size, node++) {
234− if (node->start < fpfn)
235− break;
236− }
237−
238− if (!pages_left)
239− goto gtt;
226+ !(abo->flags & AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED) &&
227+ amdgpu_bo_in_cpu_visible_vram(abo)) {
240228
241229 /* Try evicting to the CPU inaccessible part of VRAM
242230 * first, but only set GTT as busy placement, so this
@@ -245,12 +233,11 @@ static void amdgpu_evict_flags(struct ttm_buffer_object *bo, · 2 unmodified lines
245233 */
246234 amdgpu_ttm_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_VRAM |
247235 AMDGPU_GEM_DOMAIN_GTT);
248− abo->placements[0].fpfn = fpfn;
236+ abo->placements[0].fpfn = adev->gmc.visible_vram_size >> PAGE_SHIFT;
249237 abo->placements[0].lpfn = 0;
250238 abo->placement.busy_placement = &abo->placements[1];
251239 abo->placement.num_busy_placement = 1;
252240 } else {
253−gtt:
254241 amdgpu_ttm_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_GTT);
255242 }
256243 break;
@@ -856,6 +843,45 @@ static void amdgpu_ttm_tt_unpin_userptr(struct ttm_tt *ttm) · 599 unmodified lines
856843 sg_free_table(ttm->sg);
857844 }
858845
846+int amdgpu_ttm_gart_bind(struct amdgpu_device *adev,
847+ struct ttm_buffer_object *tbo,
848+ uint64_t flags)
849+{
850+ struct amdgpu_bo *abo = ttm_to_amdgpu_bo(tbo);
851+ struct ttm_tt *ttm = tbo->ttm;
852+ struct amdgpu_ttm_tt *gtt = (void *)ttm;
853+ int r;
854+
855+ if (abo->flags & AMDGPU_GEM_CREATE_MQD_GFX9) {
856+ uint64_t page_idx = 1;
857+
858+ r = amdgpu_gart_bind(adev, gtt->offset, page_idx,
859+ ttm->pages, gtt->ttm.dma_address, flags);
860+ if (r)
861+ goto gart_bind_fail;
862+
863+ /* Patch mtype of the second part BO */
864+ flags &= ~AMDGPU_PTE_MTYPE_MASK;
865+ flags |= AMDGPU_PTE_MTYPE(AMDGPU_MTYPE_NC);
866+
867+ r = amdgpu_gart_bind(adev,
868+ gtt->offset + (page_idx << PAGE_SHIFT),
869+ ttm->num_pages - page_idx,
870+ &ttm->pages[page_idx],
871+ &(gtt->ttm.dma_address[page_idx]), flags);
872+ } else {
873+ r = amdgpu_gart_bind(adev, gtt->offset, ttm->num_pages,
874+ ttm->pages, gtt->ttm.dma_address, flags);
875+ }
876+
877+gart_bind_fail:
878+ if (r)
879+ DRM_ERROR("failed to bind %lu pages at 0x%08llX\n",
880+ ttm->num_pages, gtt->offset);
881+
882+ return r;
883+}
884+
859885 static int amdgpu_ttm_backend_bind(struct ttm_tt *ttm,
860886 struct ttm_mem_reg *bo_mem)
861887 {
@@ -929,8 +955,7 @@ int amdgpu_ttm_alloc_gart(struct ttm_buffer_object *bo) · 67 unmodified lines
929955
930956 flags = amdgpu_ttm_tt_pte_flags(adev, bo->ttm, &tmp);
931957 gtt->offset = (u64)tmp.start << PAGE_SHIFT;
932− r = amdgpu_gart_bind(adev, gtt->offset, bo->ttm->num_pages,
933− bo->ttm->pages, gtt->ttm.dma_address, flags);
958+ r = amdgpu_ttm_gart_bind(adev, bo, flags);
934959 if (unlikely(r)) {
935960 ttm_bo_mem_put(bo, &tmp);
936961 return r;
@@ -947,19 +972,15 @@ int amdgpu_ttm_alloc_gart(struct ttm_buffer_object *bo) · 10 unmodified lines
947972 int amdgpu_ttm_recover_gart(struct ttm_buffer_object *tbo)
948973 {
949974 struct amdgpu_device *adev = amdgpu_ttm_adev(tbo->bdev);
950− struct amdgpu_ttm_tt *gtt = (void *)tbo->ttm;
951975 uint64_t flags;
952976 int r;
953977
954− if (!gtt)
978+ if (!tbo->ttm)
955979 return 0;
956980
957− flags = amdgpu_ttm_tt_pte_flags(adev, &gtt->ttm.ttm, &tbo->mem);
958− r = amdgpu_gart_bind(adev, gtt->offset, gtt->ttm.ttm.num_pages,
959− gtt->ttm.ttm.pages, gtt->ttm.dma_address, flags);
960− if (r)
961− DRM_ERROR("failed to bind %lu pages at 0x%08llX\n",
962− gtt->ttm.ttm.num_pages, gtt->offset);
981+ flags = amdgpu_ttm_tt_pte_flags(adev, tbo->ttm, &tbo->mem);
982+ r = amdgpu_ttm_gart_bind(adev, tbo, flags);
983+
963984 return r;
964985 }
965986
@@ -1349,6 +1370,7 @@ static void amdgpu_ttm_fw_reserve_vram_fini(struct amdgpu_device *adev) · 383 unmodified lines
13491370 static int amdgpu_ttm_fw_reserve_vram_init(struct amdgpu_device *adev)
13501371 {
13511372 struct ttm_operation_ctx ctx = { false, false };
1373+ struct amdgpu_bo_param bp;
13521374 int r = 0;
13531375 int i;
13541376 u64 vram_size = adev->gmc.visible_vram_size;
@@ -1356,17 +1378,21 @@ static int amdgpu_ttm_fw_reserve_vram_init(struct amdgpu_device *adev) · 1 unmodified line
13561378 u64 size = adev->fw_vram_usage.size;
13571379 struct amdgpu_bo *bo;
13581380
1381+ memset(&bp, 0, sizeof(bp));
1382+ bp.size = adev->fw_vram_usage.size;
1383+ bp.byte_align = PAGE_SIZE;
1384+ bp.domain = AMDGPU_GEM_DOMAIN_VRAM;
1385+ bp.flags = AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED |
1386+ AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS;
1387+ bp.type = ttm_bo_type_kernel;
1388+ bp.resv = NULL;
13591389 adev->fw_vram_usage.va = NULL;
13601390 adev->fw_vram_usage.reserved_bo = NULL;
13611391
13621392 if (adev->fw_vram_usage.size > 0 &&
13631393 adev->fw_vram_usage.size <= vram_size) {
13641394
1365− r = amdgpu_bo_create(adev, adev->fw_vram_usage.size, PAGE_SIZE,
1366− AMDGPU_GEM_DOMAIN_VRAM,
1367− AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED |
1368− AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS,
1369− ttm_bo_type_kernel, NULL,
1395+ r = amdgpu_bo_create(adev, &bp,
13701396 &adev->fw_vram_usage.reserved_bo);
13711397 if (r)
13721398 goto error_create;
@@ -1474,12 +1500,14 @@ int amdgpu_ttm_init(struct amdgpu_device *adev) · 101 unmodified lines
14741500 return r;
14751501 }
14761502
1477− r = amdgpu_bo_create_kernel(adev, adev->gmc.stolen_size, PAGE_SIZE,
1478− AMDGPU_GEM_DOMAIN_VRAM,
1479− &adev->stolen_vga_memory,
1480− NULL, NULL);
1481− if (r)
1482− return r;
1503+ if (adev->gmc.stolen_size) {
1504+ r = amdgpu_bo_create_kernel(adev, adev->gmc.stolen_size, PAGE_SIZE,
1505+ AMDGPU_GEM_DOMAIN_VRAM,
1506+ &adev->stolen_vga_memory,
1507+ NULL, NULL);
1508+ if (r)
1509+ return r;
1510+ }
14831511 DRM_INFO("amdgpu: %uM of VRAM memory ready\n",
14841512 (unsigned) (adev->gmc.real_vram_size / (1024 * 1024)));
14851513
@@ -1548,13 +1576,17 @@ int amdgpu_ttm_init(struct amdgpu_device *adev) · 62 unmodified lines
15481576 return 0;
15491577 }
15501578
1579+void amdgpu_ttm_late_init(struct amdgpu_device *adev)
1580+{
1581+ amdgpu_bo_free_kernel(&adev->stolen_vga_memory, NULL, NULL);
1582+}
1583+
15511584 void amdgpu_ttm_fini(struct amdgpu_device *adev)
15521585 {
15531586 if (!adev->mman.initialized)
15541587 return;
15551588
15561589 amdgpu_ttm_debugfs_fini(adev);
1557− amdgpu_bo_free_kernel(&adev->stolen_vga_memory, NULL, NULL);
15581590 amdgpu_ttm_fw_reserve_vram_fini(adev);
15591591 if (adev->mman.aper_base_kaddr)
15601592 iounmap(adev->mman.aper_base_kaddr);
drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h+1−0
@@ -77,6 +77,7 @@ uint64_t amdgpu_vram_mgr_usage(struct ttm_mem_type_manager *man); · 76 unmodified lines
7777 uint64_t amdgpu_vram_mgr_vis_usage(struct ttm_mem_type_manager *man);
7878
7979 int amdgpu_ttm_init(struct amdgpu_device *adev);
80+void amdgpu_ttm_late_init(struct amdgpu_device *adev);
8081 void amdgpu_ttm_fini(struct amdgpu_device *adev);
8182 void amdgpu_ttm_set_buffer_funcs_status(struct amdgpu_device *adev,
8283 bool enable);
drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c+49−3
@@ -161,8 +161,38 @@ void amdgpu_ucode_print_rlc_hdr(const struct common_firmware_header *hdr) · 160 unmodified lines
161161 le32_to_cpu(rlc_hdr->reg_list_format_separate_array_offset_bytes));
162162 DRM_DEBUG("reg_list_separate_size_bytes: %u\n",
163163 le32_to_cpu(rlc_hdr->reg_list_separate_size_bytes));
164− DRM_DEBUG("reg_list_separate_size_bytes: %u\n",
165− le32_to_cpu(rlc_hdr->reg_list_separate_size_bytes));
164+ DRM_DEBUG("reg_list_separate_array_offset_bytes: %u\n",
165+ le32_to_cpu(rlc_hdr->reg_list_separate_array_offset_bytes));
166+ if (version_minor == 1) {
167+ const struct rlc_firmware_header_v2_1 *v2_1 =
168+ container_of(rlc_hdr, struct rlc_firmware_header_v2_1, v2_0);
169+ DRM_DEBUG("reg_list_format_direct_reg_list_length: %u\n",
170+ le32_to_cpu(v2_1->reg_list_format_direct_reg_list_length));
171+ DRM_DEBUG("save_restore_list_cntl_ucode_ver: %u\n",
172+ le32_to_cpu(v2_1->save_restore_list_cntl_ucode_ver));
173+ DRM_DEBUG("save_restore_list_cntl_feature_ver: %u\n",
174+ le32_to_cpu(v2_1->save_restore_list_cntl_feature_ver));
175+ DRM_DEBUG("save_restore_list_cntl_size_bytes %u\n",
176+ le32_to_cpu(v2_1->save_restore_list_cntl_size_bytes));
177+ DRM_DEBUG("save_restore_list_cntl_offset_bytes: %u\n",
178+ le32_to_cpu(v2_1->save_restore_list_cntl_offset_bytes));
179+ DRM_DEBUG("save_restore_list_gpm_ucode_ver: %u\n",
180+ le32_to_cpu(v2_1->save_restore_list_gpm_ucode_ver));
181+ DRM_DEBUG("save_restore_list_gpm_feature_ver: %u\n",
182+ le32_to_cpu(v2_1->save_restore_list_gpm_feature_ver));
183+ DRM_DEBUG("save_restore_list_gpm_size_bytes %u\n",
184+ le32_to_cpu(v2_1->save_restore_list_gpm_size_bytes));
185+ DRM_DEBUG("save_restore_list_gpm_offset_bytes: %u\n",
186+ le32_to_cpu(v2_1->save_restore_list_gpm_offset_bytes));
187+ DRM_DEBUG("save_restore_list_srm_ucode_ver: %u\n",
188+ le32_to_cpu(v2_1->save_restore_list_srm_ucode_ver));
189+ DRM_DEBUG("save_restore_list_srm_feature_ver: %u\n",
190+ le32_to_cpu(v2_1->save_restore_list_srm_feature_ver));
191+ DRM_DEBUG("save_restore_list_srm_size_bytes %u\n",
192+ le32_to_cpu(v2_1->save_restore_list_srm_size_bytes));
193+ DRM_DEBUG("save_restore_list_srm_offset_bytes: %u\n",
194+ le32_to_cpu(v2_1->save_restore_list_srm_offset_bytes));
195+ }
166196 } else {
167197 DRM_ERROR("Unknown RLC ucode version: %u.%u\n", version_major, version_minor);
168198 }
@@ -265,6 +295,7 @@ amdgpu_ucode_get_load_type(struct amdgpu_device *adev, int load_type) · 96 unmodified lines
265295 case CHIP_POLARIS10:
266296 case CHIP_POLARIS11:
267297 case CHIP_POLARIS12:
298+ case CHIP_VEGAM:
268299 if (!load_type)
269300 return AMDGPU_FW_LOAD_DIRECT;
270301 else
@@ -307,7 +338,10 @@ static int amdgpu_ucode_init_single_fw(struct amdgpu_device *adev, · 36 unmodified lines
307338 (ucode->ucode_id != AMDGPU_UCODE_ID_CP_MEC1 &&
308339 ucode->ucode_id != AMDGPU_UCODE_ID_CP_MEC2 &&
309340 ucode->ucode_id != AMDGPU_UCODE_ID_CP_MEC1_JT &&
310− ucode->ucode_id != AMDGPU_UCODE_ID_CP_MEC2_JT)) {
341+ ucode->ucode_id != AMDGPU_UCODE_ID_CP_MEC2_JT &&
342+ ucode->ucode_id != AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL &&
343+ ucode->ucode_id != AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM &&
344+ ucode->ucode_id != AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM)) {
311345 ucode->ucode_size = le32_to_cpu(header->ucode_size_bytes);
312346
313347 memcpy(ucode->kaddr, (void *)((uint8_t *)ucode->fw->data +
@@ -329,6 +363,18 @@ static int amdgpu_ucode_init_single_fw(struct amdgpu_device *adev, · 15 unmodified lines
329363 le32_to_cpu(header->ucode_array_offset_bytes) +
330364 le32_to_cpu(cp_hdr->jt_offset) * 4),
331365 ucode->ucode_size);
366+ } else if (ucode->ucode_id == AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL) {
367+ ucode->ucode_size = adev->gfx.rlc.save_restore_list_cntl_size_bytes;
368+ memcpy(ucode->kaddr, adev->gfx.rlc.save_restore_list_cntl,
369+ ucode->ucode_size);
370+ } else if (ucode->ucode_id == AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM) {
371+ ucode->ucode_size = adev->gfx.rlc.save_restore_list_gpm_size_bytes;
372+ memcpy(ucode->kaddr, adev->gfx.rlc.save_restore_list_gpm,
373+ ucode->ucode_size);
374+ } else if (ucode->ucode_id == AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM) {
375+ ucode->ucode_size = adev->gfx.rlc.save_restore_list_srm_size_bytes;
376+ memcpy(ucode->kaddr, adev->gfx.rlc.save_restore_list_srm,
377+ ucode->ucode_size);
332378 }
333379
334380 return 0;
drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h+22−0
@@ -98,6 +98,24 @@ struct rlc_firmware_header_v2_0 { · 97 unmodified lines
9898 uint32_t reg_list_separate_array_offset_bytes; /* payload offset from the start of the header */
9999 };
100100
101+/* version_major=2, version_minor=1 */
102+struct rlc_firmware_header_v2_1 {
103+ struct rlc_firmware_header_v2_0 v2_0;
104+ uint32_t reg_list_format_direct_reg_list_length; /* length of direct reg list format array */
105+ uint32_t save_restore_list_cntl_ucode_ver;
106+ uint32_t save_restore_list_cntl_feature_ver;
107+ uint32_t save_restore_list_cntl_size_bytes;
108+ uint32_t save_restore_list_cntl_offset_bytes;
109+ uint32_t save_restore_list_gpm_ucode_ver;
110+ uint32_t save_restore_list_gpm_feature_ver;
111+ uint32_t save_restore_list_gpm_size_bytes;
112+ uint32_t save_restore_list_gpm_offset_bytes;
113+ uint32_t save_restore_list_srm_ucode_ver;
114+ uint32_t save_restore_list_srm_feature_ver;
115+ uint32_t save_restore_list_srm_size_bytes;
116+ uint32_t save_restore_list_srm_offset_bytes;
117+};
118+
101119 /* version_major=1, version_minor=0 */
102120 struct sdma_firmware_header_v1_0 {
103121 struct common_firmware_header header;
@@ -148,6 +166,7 @@ union amdgpu_firmware_header { · 44 unmodified lines
148166 struct gfx_firmware_header_v1_0 gfx;
149167 struct rlc_firmware_header_v1_0 rlc;
150168 struct rlc_firmware_header_v2_0 rlc_v2_0;
169+ struct rlc_firmware_header_v2_1 rlc_v2_1;
151170 struct sdma_firmware_header_v1_0 sdma;
152171 struct sdma_firmware_header_v1_1 sdma_v1_1;
153172 struct gpu_info_firmware_header_v1_0 gpu_info;
@@ -168,6 +187,9 @@ enum AMDGPU_UCODE_ID { · 14 unmodified lines
168187 AMDGPU_UCODE_ID_CP_MEC2,
169188 AMDGPU_UCODE_ID_CP_MEC2_JT,
170189 AMDGPU_UCODE_ID_RLC_G,
190+ AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL,
191+ AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM,
192+ AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM,
171193 AMDGPU_UCODE_ID_STORAGE,
172194 AMDGPU_UCODE_ID_SMC,
173195 AMDGPU_UCODE_ID_UVD,
drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c+6−1
@@ -66,6 +66,7 @@ · 65 unmodified lines
6666 #define FIRMWARE_POLARIS10 "amdgpu/polaris10_uvd.bin"
6767 #define FIRMWARE_POLARIS11 "amdgpu/polaris11_uvd.bin"
6868 #define FIRMWARE_POLARIS12 "amdgpu/polaris12_uvd.bin"
69+#define FIRMWARE_VEGAM "amdgpu/vegam_uvd.bin"
6970
7071 #define FIRMWARE_VEGA10 "amdgpu/vega10_uvd.bin"
7172 #define FIRMWARE_VEGA12 "amdgpu/vega12_uvd.bin"
@@ -109,6 +110,7 @@ MODULE_FIRMWARE(FIRMWARE_STONEY); · 37 unmodified lines
109110 MODULE_FIRMWARE(FIRMWARE_POLARIS10);
110111 MODULE_FIRMWARE(FIRMWARE_POLARIS11);
111112 MODULE_FIRMWARE(FIRMWARE_POLARIS12);
113+MODULE_FIRMWARE(FIRMWARE_VEGAM);
112114
113115 MODULE_FIRMWARE(FIRMWARE_VEGA10);
114116 MODULE_FIRMWARE(FIRMWARE_VEGA12);
@@ -172,6 +174,9 @@ int amdgpu_uvd_sw_init(struct amdgpu_device *adev) · 57 unmodified lines
172174 case CHIP_VEGA12:
173175 fw_name = FIRMWARE_VEGA12;
174176 break;
177+ case CHIP_VEGAM:
178+ fw_name = FIRMWARE_VEGAM;
179+ break;
175180 default:
176181 return -EINVAL;
177182 }
@@ -237,7 +242,7 @@ int amdgpu_uvd_sw_init(struct amdgpu_device *adev) · 59 unmodified lines
237242 ring = &adev->uvd.ring;
238243 rq = &ring->sched.sched_rq[DRM_SCHED_PRIORITY_NORMAL];
239244 r = drm_sched_entity_init(&ring->sched, &adev->uvd.entity,
240− rq, amdgpu_sched_jobs, NULL);
245+ rq, NULL);
241246 if (r != 0) {
242247 DRM_ERROR("Failed setting up UVD run queue.\n");
243248 return r;
drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c+32−3
@@ -51,8 +51,9 @@ · 50 unmodified lines
5151 #define FIRMWARE_FIJI "amdgpu/fiji_vce.bin"
5252 #define FIRMWARE_STONEY "amdgpu/stoney_vce.bin"
5353 #define FIRMWARE_POLARIS10 "amdgpu/polaris10_vce.bin"
54−#define FIRMWARE_POLARIS11 "amdgpu/polaris11_vce.bin"
55−#define FIRMWARE_POLARIS12 "amdgpu/polaris12_vce.bin"
54+#define FIRMWARE_POLARIS11 "amdgpu/polaris11_vce.bin"
55+#define FIRMWARE_POLARIS12 "amdgpu/polaris12_vce.bin"
56+#define FIRMWARE_VEGAM "amdgpu/vegam_vce.bin"
5657
5758 #define FIRMWARE_VEGA10 "amdgpu/vega10_vce.bin"
5859 #define FIRMWARE_VEGA12 "amdgpu/vega12_vce.bin"
@@ -71,6 +72,7 @@ MODULE_FIRMWARE(FIRMWARE_STONEY); · 12 unmodified lines
7172 MODULE_FIRMWARE(FIRMWARE_POLARIS10);
7273 MODULE_FIRMWARE(FIRMWARE_POLARIS11);
7374 MODULE_FIRMWARE(FIRMWARE_POLARIS12);
75+MODULE_FIRMWARE(FIRMWARE_VEGAM);
7476
7577 MODULE_FIRMWARE(FIRMWARE_VEGA10);
7678 MODULE_FIRMWARE(FIRMWARE_VEGA12);
@@ -132,6 +134,9 @@ int amdgpu_vce_sw_init(struct amdgpu_device *adev, unsigned long size) · 55 unmodified lines
132134 case CHIP_POLARIS12:
133135 fw_name = FIRMWARE_POLARIS12;
134136 break;
137+ case CHIP_VEGAM:
138+ fw_name = FIRMWARE_VEGAM;
139+ break;
135140 case CHIP_VEGA10:
136141 fw_name = FIRMWARE_VEGA10;
137142 break;
@@ -181,7 +186,7 @@ int amdgpu_vce_sw_init(struct amdgpu_device *adev, unsigned long size) · 43 unmodified lines
181186 ring = &adev->vce.ring[0];
182187 rq = &ring->sched.sched_rq[DRM_SCHED_PRIORITY_NORMAL];
183188 r = drm_sched_entity_init(&ring->sched, &adev->vce.entity,
184− rq, amdgpu_sched_jobs, NULL);
189+ rq, NULL);
185190 if (r != 0) {
186191 DRM_ERROR("Failed setting up VCE run queue.\n");
187192 return r;
@@ -755,6 +760,18 @@ int amdgpu_vce_ring_parse_cs(struct amdgpu_cs_parser *p, uint32_t ib_idx) · 567 unmodified lines
755760 if (r)
756761 goto out;
757762 break;
763+
764+ case 0x0500000d: /* MV buffer */
765+ r = amdgpu_vce_validate_bo(p, ib_idx, idx + 3,
766+ idx + 2, 0, 0);
767+ if (r)
768+ goto out;
769+
770+ r = amdgpu_vce_validate_bo(p, ib_idx, idx + 8,
771+ idx + 7, 0, 0);
772+ if (r)
773+ goto out;
774+ break;
758775 }
759776
760777 idx += len / 4;
@@ -860,6 +877,18 @@ int amdgpu_vce_ring_parse_cs(struct amdgpu_cs_parser *p, uint32_t ib_idx) · 99 unmodified lines
860877 goto out;
861878 break;
862879
880+ case 0x0500000d: /* MV buffer */
881+ r = amdgpu_vce_cs_reloc(p, ib_idx, idx + 3,
882+ idx + 2, *size, 0);
883+ if (r)
884+ goto out;
885+
886+ r = amdgpu_vce_cs_reloc(p, ib_idx, idx + 8,
887+ idx + 7, *size / 12, 0);
888+ if (r)
889+ goto out;
890+ break;
891+
863892 default:
864893 DRM_ERROR("invalid VCE command (0x%x)!\n", cmd);
865894 r = -EINVAL;
drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c+2−2
@@ -105,7 +105,7 @@ int amdgpu_vcn_sw_init(struct amdgpu_device *adev) · 104 unmodified lines
105105 ring = &adev->vcn.ring_dec;
106106 rq = &ring->sched.sched_rq[DRM_SCHED_PRIORITY_NORMAL];
107107 r = drm_sched_entity_init(&ring->sched, &adev->vcn.entity_dec,
108− rq, amdgpu_sched_jobs, NULL);
108+ rq, NULL);
109109 if (r != 0) {
110110 DRM_ERROR("Failed setting up VCN dec run queue.\n");
111111 return r;
@@ -114,7 +114,7 @@ int amdgpu_vcn_sw_init(struct amdgpu_device *adev) · 2 unmodified lines
114114 ring = &adev->vcn.ring_enc[0];
115115 rq = &ring->sched.sched_rq[DRM_SCHED_PRIORITY_NORMAL];
116116 r = drm_sched_entity_init(&ring->sched, &adev->vcn.entity_enc,
117− rq, amdgpu_sched_jobs, NULL);
117+ rq, NULL);
118118 if (r != 0) {
119119 DRM_ERROR("Failed setting up VCN enc run queue.\n");
120120 return r;
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c+71−43
@@ -94,6 +94,36 @@ struct amdgpu_prt_cb { · 93 unmodified lines
9494 struct dma_fence_cb cb;
9595 };
9696
97+static void amdgpu_vm_bo_base_init(struct amdgpu_vm_bo_base *base,
98+ struct amdgpu_vm *vm,
99+ struct amdgpu_bo *bo)
100+{
101+ base->vm = vm;
102+ base->bo = bo;
103+ INIT_LIST_HEAD(&base->bo_list);
104+ INIT_LIST_HEAD(&base->vm_status);
105+
106+ if (!bo)
107+ return;
108+ list_add_tail(&base->bo_list, &bo->va);
109+
110+ if (bo->tbo.resv != vm->root.base.bo->tbo.resv)
111+ return;
112+
113+ if (bo->preferred_domains &
114+ amdgpu_mem_type_to_domain(bo->tbo.mem.mem_type))
115+ return;
116+
117+ /*
118+ * we checked all the prerequisites, but it looks like this per vm bo
119+ * is currently evicted. add the bo to the evicted list to make sure it
120+ * is validated on next vm use to avoid fault.
121+ * */
122+ spin_lock(&vm->status_lock);
123+ list_move_tail(&base->vm_status, &vm->evicted);
124+ spin_unlock(&vm->status_lock);
125+}
126+
97127 /**
98128 * amdgpu_vm_level_shift - return the addr shift for each level
99129 *
@@ -412,11 +442,16 @@ static int amdgpu_vm_alloc_levels(struct amdgpu_device *adev, · 312 unmodified lines
412442 struct amdgpu_bo *pt;
413443
414444 if (!entry->base.bo) {
415− r = amdgpu_bo_create(adev,
416− amdgpu_vm_bo_size(adev, level),
417− AMDGPU_GPU_PAGE_SIZE,
418− AMDGPU_GEM_DOMAIN_VRAM, flags,
419− ttm_bo_type_kernel, resv, &pt);
445+ struct amdgpu_bo_param bp;
446+
447+ memset(&bp, 0, sizeof(bp));
448+ bp.size = amdgpu_vm_bo_size(adev, level);
449+ bp.byte_align = AMDGPU_GPU_PAGE_SIZE;
450+ bp.domain = AMDGPU_GEM_DOMAIN_VRAM;
451+ bp.flags = flags;
452+ bp.type = ttm_bo_type_kernel;
453+ bp.resv = resv;
454+ r = amdgpu_bo_create(adev, &bp, &pt);
420455 if (r)
421456 return r;
422457
@@ -441,11 +476,9 @@ static int amdgpu_vm_alloc_levels(struct amdgpu_device *adev, · 18 unmodified lines
441476 */
442477 pt->parent = amdgpu_bo_ref(parent->base.bo);
443478
444− entry->base.vm = vm;
445− entry->base.bo = pt;
446− list_add_tail(&entry->base.bo_list, &pt->va);
479+ amdgpu_vm_bo_base_init(&entry->base, vm, pt);
447480 spin_lock(&vm->status_lock);
448− list_add(&entry->base.vm_status, &vm->relocated);
481+ list_move(&entry->base.vm_status, &vm->relocated);
449482 spin_unlock(&vm->status_lock);
450483 }
451484
@@ -628,7 +661,7 @@ int amdgpu_vm_flush(struct amdgpu_ring *ring, struct amdgpu_job *job, bool need_ · 176 unmodified lines
628661 amdgpu_gmc_emit_pasid_mapping(ring, job->vmid, job->pasid);
629662
630663 if (vm_flush_needed || pasid_mapping_needed) {
631− r = amdgpu_fence_emit(ring, &fence);
664+ r = amdgpu_fence_emit(ring, &fence, 0);
632665 if (r)
633666 return r;
634667 }
@@ -1557,6 +1590,15 @@ int amdgpu_vm_bo_update(struct amdgpu_device *adev, · 922 unmodified lines
15571590
15581591 spin_lock(&vm->status_lock);
15591592 list_del_init(&bo_va->base.vm_status);
1593+
1594+ /* If the BO is not in its preferred location add it back to
1595+ * the evicted list so that it gets validated again on the
1596+ * next command submission.
1597+ */
1598+ if (bo && bo->tbo.resv == vm->root.base.bo->tbo.resv &&
1599+ !(bo->preferred_domains &
1600+ amdgpu_mem_type_to_domain(bo->tbo.mem.mem_type)))
1601+ list_add_tail(&bo_va->base.vm_status, &vm->evicted);
15601602 spin_unlock(&vm->status_lock);
15611603
15621604 list_splice_init(&bo_va->invalids, &bo_va->valids);
@@ -1827,36 +1869,12 @@ struct amdgpu_bo_va *amdgpu_vm_bo_add(struct amdgpu_device *adev, · 264 unmodified lines
18271869 if (bo_va == NULL) {
18281870 return NULL;
18291871 }
1830− bo_va->base.vm = vm;
1831− bo_va->base.bo = bo;
1832− INIT_LIST_HEAD(&bo_va->base.bo_list);
1833− INIT_LIST_HEAD(&bo_va->base.vm_status);
1872+ amdgpu_vm_bo_base_init(&bo_va->base, vm, bo);
18341873
18351874 bo_va->ref_count = 1;
18361875 INIT_LIST_HEAD(&bo_va->valids);
18371876 INIT_LIST_HEAD(&bo_va->invalids);
18381877
1839− if (!bo)
1840− return bo_va;
1841−
1842− list_add_tail(&bo_va->base.bo_list, &bo->va);
1843−
1844− if (bo->tbo.resv != vm->root.base.bo->tbo.resv)
1845− return bo_va;
1846−
1847− if (bo->preferred_domains &
1848− amdgpu_mem_type_to_domain(bo->tbo.mem.mem_type))
1849− return bo_va;
1850−
1851− /*
1852− * We checked all the prerequisites, but it looks like this per VM BO
1853− * is currently evicted. add the BO to the evicted list to make sure it
1854− * is validated on next VM use to avoid fault.
1855− * */
1856− spin_lock(&vm->status_lock);
1857− list_move_tail(&bo_va->base.vm_status, &vm->evicted);
1858− spin_unlock(&vm->status_lock);
1859−
18601878 return bo_va;
18611879 }
18621880
@@ -2234,6 +2252,10 @@ void amdgpu_vm_bo_invalidate(struct amdgpu_device *adev, · 371 unmodified lines
22342252 {
22352253 struct amdgpu_vm_bo_base *bo_base;
22362254
2255+ /* shadow bo doesn't have bo base, its validation needs its parent */
2256+ if (bo->parent && bo->parent->shadow == bo)
2257+ bo = bo->parent;
2258+
22372259 list_for_each_entry(bo_base, &bo->va, bo_list) {
22382260 struct amdgpu_vm *vm = bo_base->vm;
22392261
@@ -2355,6 +2377,8 @@ void amdgpu_vm_adjust_size(struct amdgpu_device *adev, uint32_t vm_size, · 115 unmodified lines
23552377 int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm,
23562378 int vm_context, unsigned int pasid)
23572379 {
2380+ struct amdgpu_bo_param bp;
2381+ struct amdgpu_bo *root;
23582382 const unsigned align = min(AMDGPU_VM_PTB_ALIGN_SIZE,
23592383 AMDGPU_VM_PTE_COUNT(adev) * 8);
23602384 unsigned ring_instance;
@@ -2380,7 +2404,7 @@ int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm, · 19 unmodified lines
23802404 ring = adev->vm_manager.vm_pte_rings[ring_instance];
23812405 rq = &ring->sched.sched_rq[DRM_SCHED_PRIORITY_KERNEL];
23822406 r = drm_sched_entity_init(&ring->sched, &vm->entity,
2383− rq, amdgpu_sched_jobs, NULL);
2407+ rq, NULL);
23842408 if (r)
23852409 return r;
23862410
@@ -2409,24 +2433,28 @@ int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm, · 22 unmodified lines
24092433 flags |= AMDGPU_GEM_CREATE_SHADOW;
24102434
24112435 size = amdgpu_vm_bo_size(adev, adev->vm_manager.root_level);
2412− r = amdgpu_bo_create(adev, size, align, AMDGPU_GEM_DOMAIN_VRAM, flags,
2413− ttm_bo_type_kernel, NULL, &vm->root.base.bo);
2436+ memset(&bp, 0, sizeof(bp));
2437+ bp.size = size;
2438+ bp.byte_align = align;
2439+ bp.domain = AMDGPU_GEM_DOMAIN_VRAM;
2440+ bp.flags = flags;
2441+ bp.type = ttm_bo_type_kernel;
2442+ bp.resv = NULL;
2443+ r = amdgpu_bo_create(adev, &bp, &root);
24142444 if (r)
24152445 goto error_free_sched_entity;
24162446
2417− r = amdgpu_bo_reserve(vm->root.base.bo, true);
2447+ r = amdgpu_bo_reserve(root, true);
24182448 if (r)
24192449 goto error_free_root;
24202450
2421− r = amdgpu_vm_clear_bo(adev, vm, vm->root.base.bo,
2451+ r = amdgpu_vm_clear_bo(adev, vm, root,
24222452 adev->vm_manager.root_level,
24232453 vm->pte_support_ats);
24242454 if (r)
24252455 goto error_unreserve;
24262456
2427− vm->root.base.vm = vm;
2428− list_add_tail(&vm->root.base.bo_list, &vm->root.base.bo->va);
2429− list_add_tail(&vm->root.base.vm_status, &vm->evicted);
2457+ amdgpu_vm_bo_base_init(&vm->root.base, vm, root);
24302458 amdgpu_bo_unreserve(vm->root.base.bo);
24312459
24322460 if (pasid) {
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h+3−2
@@ -75,11 +75,12 @@ struct amdgpu_bo_list_entry; · 74 unmodified lines
7575 /* PDE Block Fragment Size for VEGA10 */
7676 #define AMDGPU_PDE_BFS(a) ((uint64_t)a << 59)
7777
78−/* VEGA10 only */
78+
79+/* For GFX9 */
7980 #define AMDGPU_PTE_MTYPE(a) ((uint64_t)a << 57)
8081 #define AMDGPU_PTE_MTYPE_MASK AMDGPU_PTE_MTYPE(3ULL)
8182
82−/* For Raven */
83+#define AMDGPU_MTYPE_NC 0
8384 #define AMDGPU_MTYPE_CC 2
8485
8586 #define AMDGPU_PTE_DEFAULT_ATC (AMDGPU_PTE_SYSTEM \
drivers/gpu/drm/amd/amdgpu/ci_dpm.c+2−2
@@ -5903,7 +5903,7 @@ static int ci_dpm_init(struct amdgpu_device *adev) · 5902 unmodified lines
59035903 pi->pcie_dpm_key_disabled = 0;
59045904 pi->thermal_sclk_dpm_enabled = 0;
59055905
5906− if (amdgpu_pp_feature_mask & SCLK_DEEP_SLEEP_MASK)
5906+ if (adev->powerplay.pp_feature & PP_SCLK_DEEP_SLEEP_MASK)
59075907 pi->caps_sclk_ds = true;
59085908 else
59095909 pi->caps_sclk_ds = false;
@@ -6255,7 +6255,7 @@ static int ci_dpm_late_init(void *handle) · 345 unmodified lines
62556255 int ret;
62566256 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
62576257
6258− if (!amdgpu_dpm)
6258+ if (!adev->pm.dpm_enabled)
62596259 return 0;
62606260
62616261 /* init the sysfs and debugfs files late */
drivers/gpu/drm/amd/amdgpu/cik.c+7−0
@@ -1735,6 +1735,12 @@ static void cik_invalidate_hdp(struct amdgpu_device *adev, · 1734 unmodified lines
17351735 }
17361736 }
17371737
1738+static bool cik_need_full_reset(struct amdgpu_device *adev)
1739+{
1740+ /* change this when we support soft reset */
1741+ return true;
1742+}
1743+
17381744 static const struct amdgpu_asic_funcs cik_asic_funcs =
17391745 {
17401746 .read_disabled_bios = &cik_read_disabled_bios,
@@ -1748,6 +1754,7 @@ static const struct amdgpu_asic_funcs cik_asic_funcs = · 7 unmodified lines
17481754 .get_config_memsize = &cik_get_config_memsize,
17491755 .flush_hdp = &cik_flush_hdp,
17501756 .invalidate_hdp = &cik_invalidate_hdp,
1757+ .need_full_reset = &cik_need_full_reset,
17511758 };
17521759
17531760 static int cik_common_early_init(void *handle)
drivers/gpu/drm/amd/amdgpu/dce_v10_0.c+5−12
@@ -1823,7 +1823,6 @@ static int dce_v10_0_crtc_do_set_base(struct drm_crtc *crtc, · 1822 unmodified lines
18231823 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
18241824 struct drm_device *dev = crtc->dev;
18251825 struct amdgpu_device *adev = dev->dev_private;
1826− struct amdgpu_framebuffer *amdgpu_fb;
18271826 struct drm_framebuffer *target_fb;
18281827 struct drm_gem_object *obj;
18291828 struct amdgpu_bo *abo;
@@ -1842,18 +1841,15 @@ static int dce_v10_0_crtc_do_set_base(struct drm_crtc *crtc, · 12 unmodified lines
18421841 return 0;
18431842 }
18441843
1845− if (atomic) {
1846− amdgpu_fb = to_amdgpu_framebuffer(fb);
1844+ if (atomic)
18471845 target_fb = fb;
1848− } else {
1849− amdgpu_fb = to_amdgpu_framebuffer(crtc->primary->fb);
1846+ else
18501847 target_fb = crtc->primary->fb;
1851− }
18521848
18531849 /* If atomic, assume fb object is pinned & idle & fenced and
18541850 * just update base pointers
18551851 */
1856− obj = amdgpu_fb->obj;
1852+ obj = target_fb->obj[0];
18571853 abo = gem_to_amdgpu_bo(obj);
18581854 r = amdgpu_bo_reserve(abo, false);
18591855 if (unlikely(r != 0))
@@ -2043,8 +2039,7 @@ static int dce_v10_0_crtc_do_set_base(struct drm_crtc *crtc, · 183 unmodified lines
20432039 WREG32(mmMASTER_UPDATE_MODE + amdgpu_crtc->crtc_offset, 0);
20442040
20452041 if (!atomic && fb && fb != crtc->primary->fb) {
2046− amdgpu_fb = to_amdgpu_framebuffer(fb);
2047− abo = gem_to_amdgpu_bo(amdgpu_fb->obj);
2042+ abo = gem_to_amdgpu_bo(fb->obj[0]);
20482043 r = amdgpu_bo_reserve(abo, true);
20492044 if (unlikely(r != 0))
20502045 return r;
@@ -2526,11 +2521,9 @@ static void dce_v10_0_crtc_disable(struct drm_crtc *crtc) · 475 unmodified lines
25262521 dce_v10_0_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
25272522 if (crtc->primary->fb) {
25282523 int r;
2529− struct amdgpu_framebuffer *amdgpu_fb;
25302524 struct amdgpu_bo *abo;
25312525
2532− amdgpu_fb = to_amdgpu_framebuffer(crtc->primary->fb);
2533− abo = gem_to_amdgpu_bo(amdgpu_fb->obj);
2526+ abo = gem_to_amdgpu_bo(crtc->primary->fb->obj[0]);
25342527 r = amdgpu_bo_reserve(abo, true);
25352528 if (unlikely(r))
25362529 DRM_ERROR("failed to reserve abo before unpin\n");
drivers/gpu/drm/amd/amdgpu/dce_v11_0.c+15−15
@@ -173,6 +173,7 @@ static void dce_v11_0_init_golden_registers(struct amdgpu_device *adev) · 172 unmodified lines
173173 ARRAY_SIZE(polaris11_golden_settings_a11));
174174 break;
175175 case CHIP_POLARIS10:
176+ case CHIP_VEGAM:
176177 amdgpu_device_program_register_sequence(adev,
177178 polaris10_golden_settings_a11,
178179 ARRAY_SIZE(polaris10_golden_settings_a11));
@@ -473,6 +474,7 @@ static int dce_v11_0_get_num_crtc (struct amdgpu_device *adev) · 294 unmodified lines
473474 num_crtc = 2;
474475 break;
475476 case CHIP_POLARIS10:
477+ case CHIP_VEGAM:
476478 num_crtc = 6;
477479 break;
478480 case CHIP_POLARIS11:
@@ -1445,6 +1447,7 @@ static int dce_v11_0_audio_init(struct amdgpu_device *adev) · 966 unmodified lines
14451447 adev->mode_info.audio.num_pins = 7;
14461448 break;
14471449 case CHIP_POLARIS10:
1450+ case CHIP_VEGAM:
14481451 adev->mode_info.audio.num_pins = 8;
14491452 break;
14501453 case CHIP_POLARIS11:
@@ -1862,7 +1865,6 @@ static int dce_v11_0_crtc_do_set_base(struct drm_crtc *crtc, · 411 unmodified lines
18621865 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
18631866 struct drm_device *dev = crtc->dev;
18641867 struct amdgpu_device *adev = dev->dev_private;
1865− struct amdgpu_framebuffer *amdgpu_fb;
18661868 struct drm_framebuffer *target_fb;
18671869 struct drm_gem_object *obj;
18681870 struct amdgpu_bo *abo;
@@ -1881,18 +1883,15 @@ static int dce_v11_0_crtc_do_set_base(struct drm_crtc *crtc, · 12 unmodified lines
18811883 return 0;
18821884 }
18831885
1884− if (atomic) {
1885− amdgpu_fb = to_amdgpu_framebuffer(fb);
1886+ if (atomic)
18861887 target_fb = fb;
1887− } else {
1888− amdgpu_fb = to_amdgpu_framebuffer(crtc->primary->fb);
1888+ else
18891889 target_fb = crtc->primary->fb;
1890− }
18911890
18921891 /* If atomic, assume fb object is pinned & idle & fenced and
18931892 * just update base pointers
18941893 */
1895− obj = amdgpu_fb->obj;
1894+ obj = target_fb->obj[0];
18961895 abo = gem_to_amdgpu_bo(obj);
18971896 r = amdgpu_bo_reserve(abo, false);
18981897 if (unlikely(r != 0))
@@ -2082,8 +2081,7 @@ static int dce_v11_0_crtc_do_set_base(struct drm_crtc *crtc, · 183 unmodified lines
20822081 WREG32(mmCRTC_MASTER_UPDATE_MODE + amdgpu_crtc->crtc_offset, 0);
20832082
20842083 if (!atomic && fb && fb != crtc->primary->fb) {
2085− amdgpu_fb = to_amdgpu_framebuffer(fb);
2086− abo = gem_to_amdgpu_bo(amdgpu_fb->obj);
2084+ abo = gem_to_amdgpu_bo(fb->obj[0]);
20872085 r = amdgpu_bo_reserve(abo, true);
20882086 if (unlikely(r != 0))
20892087 return r;
@@ -2253,7 +2251,8 @@ static u32 dce_v11_0_pick_pll(struct drm_crtc *crtc) · 163 unmodified lines
22532251
22542252 if ((adev->asic_type == CHIP_POLARIS10) ||
22552253 (adev->asic_type == CHIP_POLARIS11) ||
2256− (adev->asic_type == CHIP_POLARIS12)) {
2254+ (adev->asic_type == CHIP_POLARIS12) ||
2255+ (adev->asic_type == CHIP_VEGAM)) {
22572256 struct amdgpu_encoder *amdgpu_encoder =
22582257 to_amdgpu_encoder(amdgpu_crtc->encoder);
22592258 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
@@ -2601,11 +2600,9 @@ static void dce_v11_0_crtc_disable(struct drm_crtc *crtc) · 341 unmodified lines
26012600 dce_v11_0_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
26022601 if (crtc->primary->fb) {
26032602 int r;
2604− struct amdgpu_framebuffer *amdgpu_fb;
26052603 struct amdgpu_bo *abo;
26062604
2607− amdgpu_fb = to_amdgpu_framebuffer(crtc->primary->fb);
2608− abo = gem_to_amdgpu_bo(amdgpu_fb->obj);
2605+ abo = gem_to_amdgpu_bo(crtc->primary->fb->obj[0]);
26092606 r = amdgpu_bo_reserve(abo, true);
26102607 if (unlikely(r))
26112608 DRM_ERROR("failed to reserve abo before unpin\n");
@@ -2673,7 +2670,8 @@ static int dce_v11_0_crtc_mode_set(struct drm_crtc *crtc, · 61 unmodified lines
26732670
26742671 if ((adev->asic_type == CHIP_POLARIS10) ||
26752672 (adev->asic_type == CHIP_POLARIS11) ||
2676− (adev->asic_type == CHIP_POLARIS12)) {
2673+ (adev->asic_type == CHIP_POLARIS12) ||
2674+ (adev->asic_type == CHIP_VEGAM)) {
26772675 struct amdgpu_encoder *amdgpu_encoder =
26782676 to_amdgpu_encoder(amdgpu_crtc->encoder);
26792677 int encoder_mode =
@@ -2830,6 +2828,7 @@ static int dce_v11_0_early_init(void *handle) · 150 unmodified lines
28302828 adev->mode_info.num_dig = 9;
28312829 break;
28322830 case CHIP_POLARIS10:
2831+ case CHIP_VEGAM:
28332832 adev->mode_info.num_hpd = 6;
28342833 adev->mode_info.num_dig = 6;
28352834 break;
@@ -2949,7 +2948,8 @@ static int dce_v11_0_hw_init(void *handle) · 113 unmodified lines
29492948 amdgpu_atombios_encoder_init_dig(adev);
29502949 if ((adev->asic_type == CHIP_POLARIS10) ||
29512950 (adev->asic_type == CHIP_POLARIS11) ||
2952− (adev->asic_type == CHIP_POLARIS12)) {
2951+ (adev->asic_type == CHIP_POLARIS12) ||
2952+ (adev->asic_type == CHIP_VEGAM)) {
29532953 amdgpu_atombios_crtc_set_dce_clock(adev, adev->clock.default_dispclk,
29542954 DCE_CLOCK_TYPE_DISPCLK, ATOM_GCK_DFS);
29552955 amdgpu_atombios_crtc_set_dce_clock(adev, 0,
drivers/gpu/drm/amd/amdgpu/dce_v6_0.c+5−12
@@ -1780,7 +1780,6 @@ static int dce_v6_0_crtc_do_set_base(struct drm_crtc *crtc, · 1779 unmodified lines
17801780 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
17811781 struct drm_device *dev = crtc->dev;
17821782 struct amdgpu_device *adev = dev->dev_private;
1783− struct amdgpu_framebuffer *amdgpu_fb;
17841783 struct drm_framebuffer *target_fb;
17851784 struct drm_gem_object *obj;
17861785 struct amdgpu_bo *abo;
@@ -1798,18 +1797,15 @@ static int dce_v6_0_crtc_do_set_base(struct drm_crtc *crtc, · 11 unmodified lines
17981797 return 0;
17991798 }
18001799
1801− if (atomic) {
1802− amdgpu_fb = to_amdgpu_framebuffer(fb);
1800+ if (atomic)
18031801 target_fb = fb;
1804− } else {
1805− amdgpu_fb = to_amdgpu_framebuffer(crtc->primary->fb);
1802+ else
18061803 target_fb = crtc->primary->fb;
1807− }
18081804
18091805 /* If atomic, assume fb object is pinned & idle & fenced and
18101806 * just update base pointers
18111807 */
1812− obj = amdgpu_fb->obj;
1808+ obj = target_fb->obj[0];
18131809 abo = gem_to_amdgpu_bo(obj);
18141810 r = amdgpu_bo_reserve(abo, false);
18151811 if (unlikely(r != 0))
@@ -1978,8 +1974,7 @@ static int dce_v6_0_crtc_do_set_base(struct drm_crtc *crtc, · 162 unmodified lines
19781974 WREG32(mmMASTER_UPDATE_MODE + amdgpu_crtc->crtc_offset, 0);
19791975
19801976 if (!atomic && fb && fb != crtc->primary->fb) {
1981− amdgpu_fb = to_amdgpu_framebuffer(fb);
1982− abo = gem_to_amdgpu_bo(amdgpu_fb->obj);
1977+ abo = gem_to_amdgpu_bo(fb->obj[0]);
19831978 r = amdgpu_bo_reserve(abo, true);
19841979 if (unlikely(r != 0))
19851980 return r;
@@ -2414,11 +2409,9 @@ static void dce_v6_0_crtc_disable(struct drm_crtc *crtc) · 428 unmodified lines
24142409 dce_v6_0_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
24152410 if (crtc->primary->fb) {
24162411 int r;
2417− struct amdgpu_framebuffer *amdgpu_fb;
24182412 struct amdgpu_bo *abo;
24192413
2420− amdgpu_fb = to_amdgpu_framebuffer(crtc->primary->fb);
2421− abo = gem_to_amdgpu_bo(amdgpu_fb->obj);
2414+ abo = gem_to_amdgpu_bo(crtc->primary->fb->obj[0]);
24222415 r = amdgpu_bo_reserve(abo, true);
24232416 if (unlikely(r))
24242417 DRM_ERROR("failed to reserve abo before unpin\n");
drivers/gpu/drm/amd/amdgpu/dce_v8_0.c+5−12
@@ -1754,7 +1754,6 @@ static int dce_v8_0_crtc_do_set_base(struct drm_crtc *crtc, · 1753 unmodified lines
17541754 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
17551755 struct drm_device *dev = crtc->dev;
17561756 struct amdgpu_device *adev = dev->dev_private;
1757− struct amdgpu_framebuffer *amdgpu_fb;
17581757 struct drm_framebuffer *target_fb;
17591758 struct drm_gem_object *obj;
17601759 struct amdgpu_bo *abo;
@@ -1773,18 +1772,15 @@ static int dce_v8_0_crtc_do_set_base(struct drm_crtc *crtc, · 12 unmodified lines
17731772 return 0;
17741773 }
17751774
1776− if (atomic) {
1777− amdgpu_fb = to_amdgpu_framebuffer(fb);
1775+ if (atomic)
17781776 target_fb = fb;
1779− } else {
1780− amdgpu_fb = to_amdgpu_framebuffer(crtc->primary->fb);
1777+ else
17811778 target_fb = crtc->primary->fb;
1782− }
17831779
17841780 /* If atomic, assume fb object is pinned & idle & fenced and
17851781 * just update base pointers
17861782 */
1787− obj = amdgpu_fb->obj;
1783+ obj = target_fb->obj[0];
17881784 abo = gem_to_amdgpu_bo(obj);
17891785 r = amdgpu_bo_reserve(abo, false);
17901786 if (unlikely(r != 0))
@@ -1955,8 +1951,7 @@ static int dce_v8_0_crtc_do_set_base(struct drm_crtc *crtc, · 164 unmodified lines
19551951 WREG32(mmMASTER_UPDATE_MODE + amdgpu_crtc->crtc_offset, 0);
19561952
19571953 if (!atomic && fb && fb != crtc->primary->fb) {
1958− amdgpu_fb = to_amdgpu_framebuffer(fb);
1959− abo = gem_to_amdgpu_bo(amdgpu_fb->obj);
1954+ abo = gem_to_amdgpu_bo(fb->obj[0]);
19601955 r = amdgpu_bo_reserve(abo, true);
19611956 if (unlikely(r != 0))
19621957 return r;
@@ -2430,11 +2425,9 @@ static void dce_v8_0_crtc_disable(struct drm_crtc *crtc) · 467 unmodified lines
24302425 dce_v8_0_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
24312426 if (crtc->primary->fb) {
24322427 int r;
2433− struct amdgpu_framebuffer *amdgpu_fb;
24342428 struct amdgpu_bo *abo;
24352429
2436− amdgpu_fb = to_amdgpu_framebuffer(crtc->primary->fb);
2437− abo = gem_to_amdgpu_bo(amdgpu_fb->obj);
2430+ abo = gem_to_amdgpu_bo(crtc->primary->fb->obj[0]);
24382431 r = amdgpu_bo_reserve(abo, true);
24392432 if (unlikely(r))
24402433 DRM_ERROR("failed to reserve abo before unpin\n");
drivers/gpu/drm/amd/amdgpu/dce_virtual.c+4−5
@@ -168,11 +168,9 @@ static void dce_virtual_crtc_disable(struct drm_crtc *crtc) · 167 unmodified lines
168168 dce_virtual_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
169169 if (crtc->primary->fb) {
170170 int r;
171− struct amdgpu_framebuffer *amdgpu_fb;
172171 struct amdgpu_bo *abo;
173172
174− amdgpu_fb = to_amdgpu_framebuffer(crtc->primary->fb);
175− abo = gem_to_amdgpu_bo(amdgpu_fb->obj);
173+ abo = gem_to_amdgpu_bo(crtc->primary->fb->obj[0]);
176174 r = amdgpu_bo_reserve(abo, true);
177175 if (unlikely(r))
178176 DRM_ERROR("failed to reserve abo before unpin\n");
@@ -329,7 +327,7 @@ static int dce_virtual_get_modes(struct drm_connector *connector) · 150 unmodified lines
329327 return 0;
330328 }
331329
332−static int dce_virtual_mode_valid(struct drm_connector *connector,
330+static enum drm_mode_status dce_virtual_mode_valid(struct drm_connector *connector,
333331 struct drm_display_mode *mode)
334332 {
335333 return MODE_OK;
@@ -462,8 +460,9 @@ static int dce_virtual_hw_init(void *handle) · 126 unmodified lines
462460 break;
463461 case CHIP_CARRIZO:
464462 case CHIP_STONEY:
465− case CHIP_POLARIS11:
466463 case CHIP_POLARIS10:
464+ case CHIP_POLARIS11:
465+ case CHIP_VEGAM:
467466 dce_v11_0_disable_dce(adev);
468467 break;
469468 case CHIP_TOPAZ:
drivers/gpu/drm/amd/amdgpu/df_v1_7.c+112−0
@@ -0,0 +1,112 @@
1+/*
2+ * Copyright 2018 Advanced Micro Devices, Inc.
3+ *
4+ * Permission is hereby granted, free of charge, to any person obtaining a
5+ * copy of this software and associated documentation files (the "Software"),
6+ * to deal in the Software without restriction, including without limitation
7+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8+ * and/or sell copies of the Software, and to permit persons to whom the
9+ * Software is furnished to do so, subject to the following conditions:
10+ *
11+ * The above copyright notice and this permission notice shall be included in
12+ * all copies or substantial portions of the Software.
13+ *
14+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20+ * OTHER DEALINGS IN THE SOFTWARE.
21+ *
22+ */
23+#include "amdgpu.h"
24+#include "df_v1_7.h"
25+
26+#include "df/df_1_7_default.h"
27+#include "df/df_1_7_offset.h"
28+#include "df/df_1_7_sh_mask.h"
29+
30+static u32 df_v1_7_channel_number[] = {1, 2, 0, 4, 0, 8, 0, 16, 2};
31+
32+static void df_v1_7_init (struct amdgpu_device *adev)
33+{
34+}
35+
36+static void df_v1_7_enable_broadcast_mode(struct amdgpu_device *adev,
37+ bool enable)
38+{
39+ u32 tmp;
40+
41+ if (enable) {
42+ tmp = RREG32_SOC15(DF, 0, mmFabricConfigAccessControl);
43+ tmp &= ~FabricConfigAccessControl__CfgRegInstAccEn_MASK;
44+ WREG32_SOC15(DF, 0, mmFabricConfigAccessControl, tmp);
45+ } else
46+ WREG32_SOC15(DF, 0, mmFabricConfigAccessControl,
47+ mmFabricConfigAccessControl_DEFAULT);
48+}
49+
50+static u32 df_v1_7_get_fb_channel_number(struct amdgpu_device *adev)
51+{
52+ u32 tmp;
53+
54+ tmp = RREG32_SOC15(DF, 0, mmDF_CS_AON0_DramBaseAddress0);
55+ tmp &= DF_CS_AON0_DramBaseAddress0__IntLvNumChan_MASK;
56+ tmp >>= DF_CS_AON0_DramBaseAddress0__IntLvNumChan__SHIFT;
57+
58+ return tmp;
59+}
60+
61+static u32 df_v1_7_get_hbm_channel_number(struct amdgpu_device *adev)
62+{
63+ int fb_channel_number;
64+
65+ fb_channel_number = adev->df_funcs->get_fb_channel_number(adev);
66+
67+ return df_v1_7_channel_number[fb_channel_number];
68+}
69+
70+static void df_v1_7_update_medium_grain_clock_gating(struct amdgpu_device *adev,
71+ bool enable)
72+{
73+ u32 tmp;
74+
75+ /* Put DF on broadcast mode */
76+ adev->df_funcs->enable_broadcast_mode(adev, true);
77+
78+ if (enable && (adev->cg_flags & AMD_CG_SUPPORT_DF_MGCG)) {
79+ tmp = RREG32_SOC15(DF, 0, mmDF_PIE_AON0_DfGlobalClkGater);
80+ tmp &= ~DF_PIE_AON0_DfGlobalClkGater__MGCGMode_MASK;
81+ tmp |= DF_V1_7_MGCG_ENABLE_15_CYCLE_DELAY;
82+ WREG32_SOC15(DF, 0, mmDF_PIE_AON0_DfGlobalClkGater, tmp);
83+ } else {
84+ tmp = RREG32_SOC15(DF, 0, mmDF_PIE_AON0_DfGlobalClkGater);
85+ tmp &= ~DF_PIE_AON0_DfGlobalClkGater__MGCGMode_MASK;
86+ tmp |= DF_V1_7_MGCG_DISABLE;
87+ WREG32_SOC15(DF, 0, mmDF_PIE_AON0_DfGlobalClkGater, tmp);
88+ }
89+
90+ /* Exit boradcast mode */
91+ adev->df_funcs->enable_broadcast_mode(adev, false);
92+}
93+
94+static void df_v1_7_get_clockgating_state(struct amdgpu_device *adev,
95+ u32 *flags)
96+{
97+ u32 tmp;
98+
99+ /* AMD_CG_SUPPORT_DF_MGCG */
100+ tmp = RREG32_SOC15(DF, 0, mmDF_PIE_AON0_DfGlobalClkGater);
101+ if (tmp & DF_V1_7_MGCG_ENABLE_15_CYCLE_DELAY)
102+ *flags |= AMD_CG_SUPPORT_DF_MGCG;
103+}
104+
105+const struct amdgpu_df_funcs df_v1_7_funcs = {
106+ .init = df_v1_7_init,
107+ .enable_broadcast_mode = df_v1_7_enable_broadcast_mode,
108+ .get_fb_channel_number = df_v1_7_get_fb_channel_number,
109+ .get_hbm_channel_number = df_v1_7_get_hbm_channel_number,
110+ .update_medium_grain_clock_gating = df_v1_7_update_medium_grain_clock_gating,
111+ .get_clockgating_state = df_v1_7_get_clockgating_state,
112+};
drivers/gpu/drm/amd/amdgpu/df_v1_7.hrenamed from drivers/gpu/drm/amd/powerplay/inc/pp_soc15.h+13−25
@@ -1,5 +1,5 @@
11 /*
2− * Copyright 2016 Advanced Micro Devices, Inc.
2+ * Copyright 2018 Advanced Micro Devices, Inc.
33 *
44 * Permission is hereby granted, free of charge, to any person obtaining a
55 * copy of this software and associated documentation files (the "Software"),
@@ -20,33 +20,21 @@ · 14 unmodified lines
2020 * OTHER DEALINGS IN THE SOFTWARE.
2121 *
2222 */
23−#ifndef PP_SOC15_H
24−#define PP_SOC15_H
2523
26−#include "soc15_hw_ip.h"
27−#include "vega10_ip_offset.h"
24+#ifndef __DF_V1_7_H__
25+#define __DF_V1_7_H__
2826
29−inline static uint32_t soc15_get_register_offset(
30− uint32_t hw_id,
31− uint32_t inst,
32− uint32_t segment,
33− uint32_t offset)
27+#include "soc15_common.h"
28+enum DF_V1_7_MGCG
3429 {
35− uint32_t reg = 0;
30+ DF_V1_7_MGCG_DISABLE = 0,
31+ DF_V1_7_MGCG_ENABLE_00_CYCLE_DELAY =1,
32+ DF_V1_7_MGCG_ENABLE_01_CYCLE_DELAY =2,
33+ DF_V1_7_MGCG_ENABLE_15_CYCLE_DELAY =13,
34+ DF_V1_7_MGCG_ENABLE_31_CYCLE_DELAY =14,
35+ DF_V1_7_MGCG_ENABLE_63_CYCLE_DELAY =15
36+};
3637
37− if (hw_id == THM_HWID)
38− reg = THM_BASE.instance[inst].segment[segment] + offset;
39− else if (hw_id == NBIF_HWID)
40− reg = NBIF_BASE.instance[inst].segment[segment] + offset;
41− else if (hw_id == MP1_HWID)
42− reg = MP1_BASE.instance[inst].segment[segment] + offset;
43− else if (hw_id == DF_HWID)
44− reg = DF_BASE.instance[inst].segment[segment] + offset;
45− else if (hw_id == GC_HWID)
46− reg = GC_BASE.instance[inst].segment[segment] + offset;
47− else if (hw_id == SMUIO_HWID)
48− reg = SMUIO_BASE.instance[inst].segment[segment] + offset;
49− return reg;
50−}
38+extern const struct amdgpu_df_funcs df_v1_7_funcs;
5139
5240 #endif
drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c+80−22
@@ -125,18 +125,6 @@ MODULE_FIRMWARE("amdgpu/fiji_mec.bin"); · 124 unmodified lines
125125 MODULE_FIRMWARE("amdgpu/fiji_mec2.bin");
126126 MODULE_FIRMWARE("amdgpu/fiji_rlc.bin");
127127
128−MODULE_FIRMWARE("amdgpu/polaris11_ce.bin");
129−MODULE_FIRMWARE("amdgpu/polaris11_ce_2.bin");
130−MODULE_FIRMWARE("amdgpu/polaris11_pfp.bin");
131−MODULE_FIRMWARE("amdgpu/polaris11_pfp_2.bin");
132−MODULE_FIRMWARE("amdgpu/polaris11_me.bin");
133−MODULE_FIRMWARE("amdgpu/polaris11_me_2.bin");
134−MODULE_FIRMWARE("amdgpu/polaris11_mec.bin");
135−MODULE_FIRMWARE("amdgpu/polaris11_mec_2.bin");
136−MODULE_FIRMWARE("amdgpu/polaris11_mec2.bin");
137−MODULE_FIRMWARE("amdgpu/polaris11_mec2_2.bin");
138−MODULE_FIRMWARE("amdgpu/polaris11_rlc.bin");
139−
140128 MODULE_FIRMWARE("amdgpu/polaris10_ce.bin");
141129 MODULE_FIRMWARE("amdgpu/polaris10_ce_2.bin");
142130 MODULE_FIRMWARE("amdgpu/polaris10_pfp.bin");
@@ -149,6 +137,18 @@ MODULE_FIRMWARE("amdgpu/polaris10_mec2.bin"); · 6 unmodified lines
149137 MODULE_FIRMWARE("amdgpu/polaris10_mec2_2.bin");
150138 MODULE_FIRMWARE("amdgpu/polaris10_rlc.bin");
151139
140+MODULE_FIRMWARE("amdgpu/polaris11_ce.bin");
141+MODULE_FIRMWARE("amdgpu/polaris11_ce_2.bin");
142+MODULE_FIRMWARE("amdgpu/polaris11_pfp.bin");
143+MODULE_FIRMWARE("amdgpu/polaris11_pfp_2.bin");
144+MODULE_FIRMWARE("amdgpu/polaris11_me.bin");
145+MODULE_FIRMWARE("amdgpu/polaris11_me_2.bin");
146+MODULE_FIRMWARE("amdgpu/polaris11_mec.bin");
147+MODULE_FIRMWARE("amdgpu/polaris11_mec_2.bin");
148+MODULE_FIRMWARE("amdgpu/polaris11_mec2.bin");
149+MODULE_FIRMWARE("amdgpu/polaris11_mec2_2.bin");
150+MODULE_FIRMWARE("amdgpu/polaris11_rlc.bin");
151+
152152 MODULE_FIRMWARE("amdgpu/polaris12_ce.bin");
153153 MODULE_FIRMWARE("amdgpu/polaris12_ce_2.bin");
154154 MODULE_FIRMWARE("amdgpu/polaris12_pfp.bin");
@@ -161,6 +161,13 @@ MODULE_FIRMWARE("amdgpu/polaris12_mec2.bin"); · 6 unmodified lines
161161 MODULE_FIRMWARE("amdgpu/polaris12_mec2_2.bin");
162162 MODULE_FIRMWARE("amdgpu/polaris12_rlc.bin");
163163
164+MODULE_FIRMWARE("amdgpu/vegam_ce.bin");
165+MODULE_FIRMWARE("amdgpu/vegam_pfp.bin");
166+MODULE_FIRMWARE("amdgpu/vegam_me.bin");
167+MODULE_FIRMWARE("amdgpu/vegam_mec.bin");
168+MODULE_FIRMWARE("amdgpu/vegam_mec2.bin");
169+MODULE_FIRMWARE("amdgpu/vegam_rlc.bin");
170+
164171 static const struct amdgpu_gds_reg_offset amdgpu_gds_reg_offset[] =
165172 {
166173 {mmGDS_VMID0_BASE, mmGDS_VMID0_SIZE, mmGDS_GWS_VMID0, mmGDS_OA_VMID0},
@@ -292,6 +299,37 @@ static const u32 tonga_mgcg_cgcg_init[] = · 125 unmodified lines
292299 mmCP_MEM_SLP_CNTL, 0x00000001, 0x00000001,
293300 };
294301
302+static const u32 golden_settings_vegam_a11[] =
303+{
304+ mmCB_HW_CONTROL, 0x0001f3cf, 0x00007208,
305+ mmCB_HW_CONTROL_2, 0x0f000000, 0x0d000000,
306+ mmCB_HW_CONTROL_3, 0x000001ff, 0x00000040,
307+ mmDB_DEBUG2, 0xf00fffff, 0x00000400,
308+ mmPA_SC_ENHANCE, 0xffffffff, 0x20000001,
309+ mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000,
310+ mmPA_SC_RASTER_CONFIG, 0x3f3fffff, 0x3a00161a,
311+ mmPA_SC_RASTER_CONFIG_1, 0x0000003f, 0x0000002e,
312+ mmRLC_CGCG_CGLS_CTRL, 0x00000003, 0x0001003c,
313+ mmRLC_CGCG_CGLS_CTRL_3D, 0xffffffff, 0x0001003c,
314+ mmSQ_CONFIG, 0x07f80000, 0x01180000,
315+ mmTA_CNTL_AUX, 0x000f000f, 0x000b0000,
316+ mmTCC_CTRL, 0x00100000, 0xf31fff7f,
317+ mmTCP_ADDR_CONFIG, 0x000003ff, 0x000000f7,
318+ mmTCP_CHAN_STEER_HI, 0xffffffff, 0x00000000,
319+ mmTCP_CHAN_STEER_LO, 0xffffffff, 0x32761054,
320+ mmVGT_RESET_DEBUG, 0x00000004, 0x00000004,
321+};
322+
323+static const u32 vegam_golden_common_all[] =
324+{
325+ mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
326+ mmGB_ADDR_CONFIG, 0xffffffff, 0x22011003,
327+ mmSPI_RESOURCE_RESERVE_CU_0, 0xffffffff, 0x00000800,
328+ mmSPI_RESOURCE_RESERVE_CU_1, 0xffffffff, 0x00000800,
329+ mmSPI_RESOURCE_RESERVE_EN_CU_0, 0xffffffff, 0x00FF7FBF,
330+ mmSPI_RESOURCE_RESERVE_EN_CU_1, 0xffffffff, 0x00FF7FAF,
331+};
332+
295333 static const u32 golden_settings_polaris11_a11[] =
296334 {
297335 mmCB_HW_CONTROL, 0x0000f3cf, 0x00007208,
@@ -712,6 +750,14 @@ static void gfx_v8_0_init_golden_registers(struct amdgpu_device *adev) · 414 unmodified lines
712750 tonga_golden_common_all,
713751 ARRAY_SIZE(tonga_golden_common_all));
714752 break;
753+ case CHIP_VEGAM:
754+ amdgpu_device_program_register_sequence(adev,
755+ golden_settings_vegam_a11,
756+ ARRAY_SIZE(golden_settings_vegam_a11));
757+ amdgpu_device_program_register_sequence(adev,
758+ vegam_golden_common_all,
759+ ARRAY_SIZE(vegam_golden_common_all));
760+ break;
715761 case CHIP_POLARIS11:
716762 case CHIP_POLARIS12:
717763 amdgpu_device_program_register_sequence(adev,
@@ -918,17 +964,20 @@ static int gfx_v8_0_init_microcode(struct amdgpu_device *adev) · 200 unmodified lines
918964 case CHIP_FIJI:
919965 chip_name = "fiji";
920966 break;
921− case CHIP_POLARIS11:
922− chip_name = "polaris11";
967+ case CHIP_STONEY:
968+ chip_name = "stoney";
923969 break;
924970 case CHIP_POLARIS10:
925971 chip_name = "polaris10";
926972 break;
973+ case CHIP_POLARIS11:
974+ chip_name = "polaris11";
975+ break;
927976 case CHIP_POLARIS12:
928977 chip_name = "polaris12";
929978 break;
930− case CHIP_STONEY:
931− chip_name = "stoney";
979+ case CHIP_VEGAM:
980+ chip_name = "vegam";
932981 break;
933982 default:
934983 BUG();
@@ -1770,6 +1819,7 @@ static int gfx_v8_0_gpu_early_init(struct amdgpu_device *adev) · 835 unmodified lines
17701819 gb_addr_config = POLARIS11_GB_ADDR_CONFIG_GOLDEN;
17711820 break;
17721821 case CHIP_POLARIS10:
1822+ case CHIP_VEGAM:
17731823 ret = amdgpu_atombios_get_gfx_info(adev);
17741824 if (ret)
17751825 return ret;
@@ -1957,12 +2007,13 @@ static int gfx_v8_0_sw_init(void *handle) · 181 unmodified lines
19572007 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
19582008
19592009 switch (adev->asic_type) {
1960− case CHIP_FIJI:
19612010 case CHIP_TONGA:
2011+ case CHIP_CARRIZO:
2012+ case CHIP_FIJI:
2013+ case CHIP_POLARIS10:
19622014 case CHIP_POLARIS11:
19632015 case CHIP_POLARIS12:
1964− case CHIP_POLARIS10:
1965− case CHIP_CARRIZO:
2016+ case CHIP_VEGAM:
19662017 adev->gfx.mec.num_mec = 2;
19672018 break;
19682019 case CHIP_TOPAZ:
@@ -2323,6 +2374,7 @@ static void gfx_v8_0_tiling_mode_table_init(struct amdgpu_device *adev) · 354 unmodified lines
23232374
23242375 break;
23252376 case CHIP_FIJI:
2377+ case CHIP_VEGAM:
23262378 modearray[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
23272379 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
23282380 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
@@ -3504,6 +3556,7 @@ gfx_v8_0_raster_config(struct amdgpu_device *adev, u32 *rconf, u32 *rconf1) · 1175 unmodified lines
35043556 {
35053557 switch (adev->asic_type) {
35063558 case CHIP_FIJI:
3559+ case CHIP_VEGAM:
35073560 *rconf |= RB_MAP_PKR0(2) | RB_MAP_PKR1(2) |
35083561 RB_XSEL2(1) | PKR_MAP(2) |
35093562 PKR_XSEL(1) | PKR_YSEL(1) |
@@ -4071,7 +4124,8 @@ static void gfx_v8_0_init_pg(struct amdgpu_device *adev) · 561 unmodified lines
40714124 gfx_v8_0_init_power_gating(adev);
40724125 WREG32(mmRLC_PG_ALWAYS_ON_CU_MASK, adev->gfx.cu_info.ao_cu_mask);
40734126 } else if ((adev->asic_type == CHIP_POLARIS11) ||
4074− (adev->asic_type == CHIP_POLARIS12)) {
4127+ (adev->asic_type == CHIP_POLARIS12) ||
4128+ (adev->asic_type == CHIP_VEGAM)) {
40754129 gfx_v8_0_init_csb(adev);
40764130 gfx_v8_0_init_save_restore_list(adev);
40774131 gfx_v8_0_enable_save_restore_machine(adev);
@@ -4146,7 +4200,8 @@ static int gfx_v8_0_rlc_resume(struct amdgpu_device *adev) · 68 unmodified lines
41464200 WREG32(mmRLC_CGCG_CGLS_CTRL, tmp);
41474201 if (adev->asic_type == CHIP_POLARIS11 ||
41484202 adev->asic_type == CHIP_POLARIS10 ||
4149− adev->asic_type == CHIP_POLARIS12) {
4203+ adev->asic_type == CHIP_POLARIS12 ||
4204+ adev->asic_type == CHIP_VEGAM) {
41504205 tmp = RREG32(mmRLC_CGCG_CGLS_CTRL_3D);
41514206 tmp &= ~0x3;
41524207 WREG32(mmRLC_CGCG_CGLS_CTRL_3D, tmp);
@@ -5498,7 +5553,8 @@ static void gfx_v8_0_enable_gfx_static_mg_power_gating(struct amdgpu_device *ade · 1345 unmodified lines
54985553 bool enable)
54995554 {
55005555 if ((adev->asic_type == CHIP_POLARIS11) ||
5501− (adev->asic_type == CHIP_POLARIS12))
5556+ (adev->asic_type == CHIP_POLARIS12) ||
5557+ (adev->asic_type == CHIP_VEGAM))
55025558 /* Send msg to SMU via Powerplay */
55035559 amdgpu_device_ip_set_powergating_state(adev,
55045560 AMD_IP_BLOCK_TYPE_SMC,
@@ -5588,6 +5644,7 @@ static int gfx_v8_0_set_powergating_state(void *handle, · 83 unmodified lines
55885644 break;
55895645 case CHIP_POLARIS11:
55905646 case CHIP_POLARIS12:
5647+ case CHIP_VEGAM:
55915648 if ((adev->pg_flags & AMD_PG_SUPPORT_GFX_SMG) && enable)
55925649 gfx_v8_0_enable_gfx_static_mg_power_gating(adev, true);
55935650 else
@@ -6154,6 +6211,7 @@ static int gfx_v8_0_set_clockgating_state(void *handle, · 560 unmodified lines
61546211 case CHIP_POLARIS10:
61556212 case CHIP_POLARIS11:
61566213 case CHIP_POLARIS12:
6214+ case CHIP_VEGAM:
61576215 gfx_v8_0_polaris_update_gfx_clock_gating(adev, state);
61586216 break;
61596217 default:
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c+185−82
@@ -41,7 +41,6 @@ · 40 unmodified lines
4141 #define GFX9_MEC_HPD_SIZE 2048
4242 #define RLCG_UCODE_LOADING_START_ADDRESS 0x00002000L
4343 #define RLC_SAVE_RESTORE_ADDR_STARTING_OFFSET 0x00000000L
44−#define GFX9_RLC_FORMAT_DIRECT_REG_LIST_LENGTH 34
4544
4645 #define mmPWR_MISC_CNTL_STATUS 0x0183
4746 #define mmPWR_MISC_CNTL_STATUS_BASE_IDX 0
@@ -185,6 +184,30 @@ static const struct soc15_reg_golden golden_settings_gc_9_2_1_vg12[] = · 137 unmodified lines
185184 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTD_CNTL, 0x01bd9f33, 0x01000000)
186185 };
187186
187+static const u32 GFX_RLC_SRM_INDEX_CNTL_ADDR_OFFSETS[] =
188+{
189+ mmRLC_SRM_INDEX_CNTL_ADDR_0 - mmRLC_SRM_INDEX_CNTL_ADDR_0,
190+ mmRLC_SRM_INDEX_CNTL_ADDR_1 - mmRLC_SRM_INDEX_CNTL_ADDR_0,
191+ mmRLC_SRM_INDEX_CNTL_ADDR_2 - mmRLC_SRM_INDEX_CNTL_ADDR_0,
192+ mmRLC_SRM_INDEX_CNTL_ADDR_3 - mmRLC_SRM_INDEX_CNTL_ADDR_0,
193+ mmRLC_SRM_INDEX_CNTL_ADDR_4 - mmRLC_SRM_INDEX_CNTL_ADDR_0,
194+ mmRLC_SRM_INDEX_CNTL_ADDR_5 - mmRLC_SRM_INDEX_CNTL_ADDR_0,
195+ mmRLC_SRM_INDEX_CNTL_ADDR_6 - mmRLC_SRM_INDEX_CNTL_ADDR_0,
196+ mmRLC_SRM_INDEX_CNTL_ADDR_7 - mmRLC_SRM_INDEX_CNTL_ADDR_0,
197+};
198+
199+static const u32 GFX_RLC_SRM_INDEX_CNTL_DATA_OFFSETS[] =
200+{
201+ mmRLC_SRM_INDEX_CNTL_DATA_0 - mmRLC_SRM_INDEX_CNTL_DATA_0,
202+ mmRLC_SRM_INDEX_CNTL_DATA_1 - mmRLC_SRM_INDEX_CNTL_DATA_0,
203+ mmRLC_SRM_INDEX_CNTL_DATA_2 - mmRLC_SRM_INDEX_CNTL_DATA_0,
204+ mmRLC_SRM_INDEX_CNTL_DATA_3 - mmRLC_SRM_INDEX_CNTL_DATA_0,
205+ mmRLC_SRM_INDEX_CNTL_DATA_4 - mmRLC_SRM_INDEX_CNTL_DATA_0,
206+ mmRLC_SRM_INDEX_CNTL_DATA_5 - mmRLC_SRM_INDEX_CNTL_DATA_0,
207+ mmRLC_SRM_INDEX_CNTL_DATA_6 - mmRLC_SRM_INDEX_CNTL_DATA_0,
208+ mmRLC_SRM_INDEX_CNTL_DATA_7 - mmRLC_SRM_INDEX_CNTL_DATA_0,
209+};
210+
188211 #define VEGA10_GB_ADDR_CONFIG_GOLDEN 0x2a114042
189212 #define VEGA12_GB_ADDR_CONFIG_GOLDEN 0x24104041
190213 #define RAVEN_GB_ADDR_CONFIG_GOLDEN 0x24000042
@@ -401,6 +424,27 @@ static void gfx_v9_0_free_microcode(struct amdgpu_device *adev) · 210 unmodified lines
401424 kfree(adev->gfx.rlc.register_list_format);
402425 }
403426
427+static void gfx_v9_0_init_rlc_ext_microcode(struct amdgpu_device *adev)
428+{
429+ const struct rlc_firmware_header_v2_1 *rlc_hdr;
430+
431+ rlc_hdr = (const struct rlc_firmware_header_v2_1 *)adev->gfx.rlc_fw->data;
432+ adev->gfx.rlc_srlc_fw_version = le32_to_cpu(rlc_hdr->save_restore_list_cntl_ucode_ver);
433+ adev->gfx.rlc_srlc_feature_version = le32_to_cpu(rlc_hdr->save_restore_list_cntl_feature_ver);
434+ adev->gfx.rlc.save_restore_list_cntl_size_bytes = le32_to_cpu(rlc_hdr->save_restore_list_cntl_size_bytes);
435+ adev->gfx.rlc.save_restore_list_cntl = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->save_restore_list_cntl_offset_bytes);
436+ adev->gfx.rlc_srlg_fw_version = le32_to_cpu(rlc_hdr->save_restore_list_gpm_ucode_ver);
437+ adev->gfx.rlc_srlg_feature_version = le32_to_cpu(rlc_hdr->save_restore_list_gpm_feature_ver);
438+ adev->gfx.rlc.save_restore_list_gpm_size_bytes = le32_to_cpu(rlc_hdr->save_restore_list_gpm_size_bytes);
439+ adev->gfx.rlc.save_restore_list_gpm = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->save_restore_list_gpm_offset_bytes);
440+ adev->gfx.rlc_srls_fw_version = le32_to_cpu(rlc_hdr->save_restore_list_srm_ucode_ver);
441+ adev->gfx.rlc_srls_feature_version = le32_to_cpu(rlc_hdr->save_restore_list_srm_feature_ver);
442+ adev->gfx.rlc.save_restore_list_srm_size_bytes = le32_to_cpu(rlc_hdr->save_restore_list_srm_size_bytes);
443+ adev->gfx.rlc.save_restore_list_srm = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->save_restore_list_srm_offset_bytes);
444+ adev->gfx.rlc.reg_list_format_direct_reg_list_length =
445+ le32_to_cpu(rlc_hdr->reg_list_format_direct_reg_list_length);
446+}
447+
404448 static int gfx_v9_0_init_microcode(struct amdgpu_device *adev)
405449 {
406450 const char *chip_name;
@@ -412,6 +456,8 @@ static int gfx_v9_0_init_microcode(struct amdgpu_device *adev) · 5 unmodified lines
412456 const struct rlc_firmware_header_v2_0 *rlc_hdr;
413457 unsigned int *tmp = NULL;
414458 unsigned int i = 0;
459+ uint16_t version_major;
460+ uint16_t version_minor;
415461
416462 DRM_DEBUG("\n");
417463
@@ -468,6 +514,12 @@ static int gfx_v9_0_init_microcode(struct amdgpu_device *adev) · 50 unmodified lines
468514 goto out;
469515 err = amdgpu_ucode_validate(adev->gfx.rlc_fw);
470516 rlc_hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data;
517+
518+ version_major = le16_to_cpu(rlc_hdr->header.header_version_major);
519+ version_minor = le16_to_cpu(rlc_hdr->header.header_version_minor);
520+ if (version_major == 2 && version_minor == 1)
521+ adev->gfx.rlc.is_rlc_v2_1 = true;
522+
471523 adev->gfx.rlc_fw_version = le32_to_cpu(rlc_hdr->header.ucode_version);
472524 adev->gfx.rlc_feature_version = le32_to_cpu(rlc_hdr->ucode_feature_version);
473525 adev->gfx.rlc.save_and_restore_offset =
@@ -508,6 +560,9 @@ static int gfx_v9_0_init_microcode(struct amdgpu_device *adev) · 34 unmodified lines
508560 for (i = 0 ; i < (rlc_hdr->reg_list_size_bytes >> 2); i++)
509561 adev->gfx.rlc.register_restore[i] = le32_to_cpu(tmp[i]);
510562
563+ if (adev->gfx.rlc.is_rlc_v2_1)
564+ gfx_v9_0_init_rlc_ext_microcode(adev);
565+
511566 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec.bin", chip_name);
512567 err = request_firmware(&adev->gfx.mec_fw, fw_name, adev->dev);
513568 if (err)
@@ -566,6 +621,26 @@ static int gfx_v9_0_init_microcode(struct amdgpu_device *adev) · 52 unmodified lines
566621 adev->firmware.fw_size +=
567622 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
568623
624+ if (adev->gfx.rlc.is_rlc_v2_1) {
625+ info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL];
626+ info->ucode_id = AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL;
627+ info->fw = adev->gfx.rlc_fw;
628+ adev->firmware.fw_size +=
629+ ALIGN(adev->gfx.rlc.save_restore_list_cntl_size_bytes, PAGE_SIZE);
630+
631+ info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM];
632+ info->ucode_id = AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM;
633+ info->fw = adev->gfx.rlc_fw;
634+ adev->firmware.fw_size +=
635+ ALIGN(adev->gfx.rlc.save_restore_list_gpm_size_bytes, PAGE_SIZE);
636+
637+ info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM];
638+ info->ucode_id = AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM;
639+ info->fw = adev->gfx.rlc_fw;
640+ adev->firmware.fw_size +=
641+ ALIGN(adev->gfx.rlc.save_restore_list_srm_size_bytes, PAGE_SIZE);
642+ }
643+
569644 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC1];
570645 info->ucode_id = AMDGPU_UCODE_ID_CP_MEC1;
571646 info->fw = adev->gfx.mec_fw;
@@ -1600,6 +1675,7 @@ static void gfx_v9_0_gpu_init(struct amdgpu_device *adev) · 1028 unmodified lines
16001675
16011676 gfx_v9_0_setup_rb(adev);
16021677 gfx_v9_0_get_cu_info(adev, &adev->gfx.cu_info);
1678+ adev->gfx.config.db_debug2 = RREG32_SOC15(GC, 0, mmDB_DEBUG2);
16031679
16041680 /* XXX SH_MEM regs */
16051681 /* where to put LDS, scratch, GPUVM in FSA64 space */
@@ -1616,7 +1692,10 @@ static void gfx_v9_0_gpu_init(struct amdgpu_device *adev) · 10 unmodified lines
16161692 tmp = REG_SET_FIELD(0, SH_MEM_CONFIG, ALIGNMENT_MODE,
16171693 SH_MEM_ALIGNMENT_MODE_UNALIGNED);
16181694 WREG32_SOC15(GC, 0, mmSH_MEM_CONFIG, tmp);
1619− tmp = adev->gmc.shared_aperture_start >> 48;
1695+ tmp = REG_SET_FIELD(0, SH_MEM_BASES, PRIVATE_BASE,
1696+ (adev->gmc.private_aperture_start >> 48));
1697+ tmp = REG_SET_FIELD(tmp, SH_MEM_BASES, SHARED_BASE,
1698+ (adev->gmc.shared_aperture_start >> 48));
16201699 WREG32_SOC15(GC, 0, mmSH_MEM_BASES, tmp);
16211700 }
16221701 }
@@ -1708,55 +1787,42 @@ static void gfx_v9_0_init_csb(struct amdgpu_device *adev) · 85 unmodified lines
17081787 adev->gfx.rlc.clear_state_size);
17091788 }
17101789
1711−static void gfx_v9_0_parse_ind_reg_list(int *register_list_format,
1790+static void gfx_v9_1_parse_ind_reg_list(int *register_list_format,
17121791 int indirect_offset,
17131792 int list_size,
17141793 int *unique_indirect_regs,
17151794 int *unique_indirect_reg_count,
1716− int max_indirect_reg_count,
17171795 int *indirect_start_offsets,
1718− int *indirect_start_offsets_count,
1719− int max_indirect_start_offsets_count)
1796+ int *indirect_start_offsets_count)
17201797 {
17211798 int idx;
1722− bool new_entry = true;
17231799
17241800 for (; indirect_offset < list_size; indirect_offset++) {
1801+ indirect_start_offsets[*indirect_start_offsets_count] = indirect_offset;
1802+ *indirect_start_offsets_count = *indirect_start_offsets_count + 1;
17251803
1726− if (new_entry) {
1727− new_entry = false;
1728− indirect_start_offsets[*indirect_start_offsets_count] = indirect_offset;
1729− *indirect_start_offsets_count = *indirect_start_offsets_count + 1;
1730− BUG_ON(*indirect_start_offsets_count >= max_indirect_start_offsets_count);
1731− }
1804+ while (register_list_format[indirect_offset] != 0xFFFFFFFF) {
1805+ indirect_offset += 2;
17321806
1733− if (register_list_format[indirect_offset] == 0xFFFFFFFF) {
1734− new_entry = true;
1735− continue;
1736− }
1807+ /* look for the matching indice */
1808+ for (idx = 0; idx < *unique_indirect_reg_count; idx++) {
1809+ if (unique_indirect_regs[idx] ==
1810+ register_list_format[indirect_offset] ||
1811+ !unique_indirect_regs[idx])
1812+ break;
1813+ }
17371814
1738− indirect_offset += 2;
1815+ BUG_ON(idx >= *unique_indirect_reg_count);
17391816
1740− /* look for the matching indice */
1741− for (idx = 0; idx < *unique_indirect_reg_count; idx++) {
1742− if (unique_indirect_regs[idx] ==
1743− register_list_format[indirect_offset])
1744− break;
1745− }
1817+ if (!unique_indirect_regs[idx])
1818+ unique_indirect_regs[idx] = register_list_format[indirect_offset];
17461819
1747− if (idx >= *unique_indirect_reg_count) {
1748− unique_indirect_regs[*unique_indirect_reg_count] =
1749− register_list_format[indirect_offset];
1750− idx = *unique_indirect_reg_count;
1751− *unique_indirect_reg_count = *unique_indirect_reg_count + 1;
1752− BUG_ON(*unique_indirect_reg_count >= max_indirect_reg_count);
1820+ indirect_offset++;
17531821 }
1754−
1755− register_list_format[indirect_offset] = idx;
17561822 }
17571823 }
17581824
1759−static int gfx_v9_0_init_rlc_save_restore_list(struct amdgpu_device *adev)
1825+static int gfx_v9_1_init_rlc_save_restore_list(struct amdgpu_device *adev)
17601826 {
17611827 int unique_indirect_regs[] = {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0};
17621828 int unique_indirect_reg_count = 0;
@@ -1765,7 +1831,7 @@ static int gfx_v9_0_init_rlc_save_restore_list(struct amdgpu_device *adev) · 2 unmodified lines
17651831 int indirect_start_offsets_count = 0;
17661832
17671833 int list_size = 0;
1768− int i = 0;
1834+ int i = 0, j = 0;
17691835 u32 tmp = 0;
17701836
17711837 u32 *register_list_format =
@@ -1776,15 +1842,14 @@ static int gfx_v9_0_init_rlc_save_restore_list(struct amdgpu_device *adev) · 4 unmodified lines
17761842 adev->gfx.rlc.reg_list_format_size_bytes);
17771843
17781844 /* setup unique_indirect_regs array and indirect_start_offsets array */
1779− gfx_v9_0_parse_ind_reg_list(register_list_format,
1780− GFX9_RLC_FORMAT_DIRECT_REG_LIST_LENGTH,
1781− adev->gfx.rlc.reg_list_format_size_bytes >> 2,
1782− unique_indirect_regs,
1783− &unique_indirect_reg_count,
1784− ARRAY_SIZE(unique_indirect_regs),
1785− indirect_start_offsets,
1786− &indirect_start_offsets_count,
1787− ARRAY_SIZE(indirect_start_offsets));
1845+ unique_indirect_reg_count = ARRAY_SIZE(unique_indirect_regs);
1846+ gfx_v9_1_parse_ind_reg_list(register_list_format,
1847+ adev->gfx.rlc.reg_list_format_direct_reg_list_length,
1848+ adev->gfx.rlc.reg_list_format_size_bytes >> 2,
1849+ unique_indirect_regs,
1850+ &unique_indirect_reg_count,
1851+ indirect_start_offsets,
1852+ &indirect_start_offsets_count);
17881853
17891854 /* enable auto inc in case it is disabled */
17901855 tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_CNTL));
@@ -1798,19 +1863,37 @@ static int gfx_v9_0_init_rlc_save_restore_list(struct amdgpu_device *adev) · 7 unmodified lines
17981863 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_ARAM_DATA),
17991864 adev->gfx.rlc.register_restore[i]);
18001865
1801− /* load direct register */
1802− WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_ARAM_ADDR), 0);
1803− for (i = 0; i < adev->gfx.rlc.reg_list_size_bytes >> 2; i++)
1804− WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_ARAM_DATA),
1805− adev->gfx.rlc.register_restore[i]);
1806−
18071866 /* load indirect register */
18081867 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_SCRATCH_ADDR),
18091868 adev->gfx.rlc.reg_list_format_start);
1810− for (i = 0; i < adev->gfx.rlc.reg_list_format_size_bytes >> 2; i++)
1869+
1870+ /* direct register portion */
1871+ for (i = 0; i < adev->gfx.rlc.reg_list_format_direct_reg_list_length; i++)
18111872 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_SCRATCH_DATA),
18121873 register_list_format[i]);
18131874
1875+ /* indirect register portion */
1876+ while (i < (adev->gfx.rlc.reg_list_format_size_bytes >> 2)) {
1877+ if (register_list_format[i] == 0xFFFFFFFF) {
1878+ WREG32_SOC15(GC, 0, mmRLC_GPM_SCRATCH_DATA, register_list_format[i++]);
1879+ continue;
1880+ }
1881+
1882+ WREG32_SOC15(GC, 0, mmRLC_GPM_SCRATCH_DATA, register_list_format[i++]);
1883+ WREG32_SOC15(GC, 0, mmRLC_GPM_SCRATCH_DATA, register_list_format[i++]);
1884+
1885+ for (j = 0; j < unique_indirect_reg_count; j++) {
1886+ if (register_list_format[i] == unique_indirect_regs[j]) {
1887+ WREG32_SOC15(GC, 0, mmRLC_GPM_SCRATCH_DATA, j);
1888+ break;
1889+ }
1890+ }
1891+
1892+ BUG_ON(j >= unique_indirect_reg_count);
1893+
1894+ i++;
1895+ }
1896+
18141897 /* set save/restore list size */
18151898 list_size = adev->gfx.rlc.reg_list_size_bytes >> 2;
18161899 list_size = list_size >> 1;
@@ -1823,14 +1906,19 @@ static int gfx_v9_0_init_rlc_save_restore_list(struct amdgpu_device *adev) · 6 unmodified lines
18231906 adev->gfx.rlc.starting_offsets_start);
18241907 for (i = 0; i < ARRAY_SIZE(indirect_start_offsets); i++)
18251908 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_SCRATCH_DATA),
1826− indirect_start_offsets[i]);
1909+ indirect_start_offsets[i]);
18271910
18281911 /* load unique indirect regs*/
18291912 for (i = 0; i < ARRAY_SIZE(unique_indirect_regs); i++) {
1830− WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_INDEX_CNTL_ADDR_0) + i,
1831− unique_indirect_regs[i] & 0x3FFFF);
1832− WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_INDEX_CNTL_DATA_0) + i,
1833− unique_indirect_regs[i] >> 20);
1913+ if (unique_indirect_regs[i] != 0) {
1914+ WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_INDEX_CNTL_ADDR_0)
1915+ + GFX_RLC_SRM_INDEX_CNTL_ADDR_OFFSETS[i],
1916+ unique_indirect_regs[i] & 0x3FFFF);
1917+
1918+ WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_INDEX_CNTL_DATA_0)
1919+ + GFX_RLC_SRM_INDEX_CNTL_DATA_OFFSETS[i],
1920+ unique_indirect_regs[i] >> 20);
1921+ }
18341922 }
18351923
18361924 kfree(register_list_format);
@@ -2010,6 +2098,9 @@ static void gfx_v9_0_enable_gfx_dynamic_mg_power_gating(struct amdgpu_device *ad · 173 unmodified lines
20102098
20112099 static void gfx_v9_0_init_pg(struct amdgpu_device *adev)
20122100 {
2101+ if (!adev->gfx.rlc.is_rlc_v2_1)
2102+ return;
2103+
20132104 if (adev->pg_flags & (AMD_PG_SUPPORT_GFX_PG |
20142105 AMD_PG_SUPPORT_GFX_SMG |
20152106 AMD_PG_SUPPORT_GFX_DMG |
@@ -2017,27 +2108,12 @@ static void gfx_v9_0_init_pg(struct amdgpu_device *adev) · 1 unmodified line
20172108 AMD_PG_SUPPORT_GDS |
20182109 AMD_PG_SUPPORT_RLC_SMU_HS)) {
20192110 gfx_v9_0_init_csb(adev);
2020− gfx_v9_0_init_rlc_save_restore_list(adev);
2111+ gfx_v9_1_init_rlc_save_restore_list(adev);
20212112 gfx_v9_0_enable_save_restore_machine(adev);
20222113
2023− if (adev->asic_type == CHIP_RAVEN) {
2024− WREG32(mmRLC_JUMP_TABLE_RESTORE,
2025− adev->gfx.rlc.cp_table_gpu_addr >> 8);
2026− gfx_v9_0_init_gfx_power_gating(adev);
2027−
2028− if (adev->pg_flags & AMD_PG_SUPPORT_RLC_SMU_HS) {
2029− gfx_v9_0_enable_sck_slow_down_on_power_up(adev, true);
2030− gfx_v9_0_enable_sck_slow_down_on_power_down(adev, true);
2031− } else {
2032− gfx_v9_0_enable_sck_slow_down_on_power_up(adev, false);
2033− gfx_v9_0_enable_sck_slow_down_on_power_down(adev, false);
2034− }
2035−
2036− if (adev->pg_flags & AMD_PG_SUPPORT_CP)
2037− gfx_v9_0_enable_cp_power_gating(adev, true);
2038− else
2039− gfx_v9_0_enable_cp_power_gating(adev, false);
2040− }
2114+ WREG32(mmRLC_JUMP_TABLE_RESTORE,
2115+ adev->gfx.rlc.cp_table_gpu_addr >> 8);
2116+ gfx_v9_0_init_gfx_power_gating(adev);
20412117 }
20422118 }
20432119
@@ -3061,6 +3137,9 @@ static int gfx_v9_0_hw_fini(void *handle) · 1017 unmodified lines
30613137 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
30623138 int i;
30633139
3140+ amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_GFX,
3141+ AMD_PG_STATE_UNGATE);
3142+
30643143 amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0);
30653144 amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0);
30663145
@@ -3279,6 +3358,11 @@ static int gfx_v9_0_late_init(void *handle) · 212 unmodified lines
32793358 if (r)
32803359 return r;
32813360
3361+ r = amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_GFX,
3362+ AMD_PG_STATE_GATE);
3363+ if (r)
3364+ return r;
3365+
32823366 return 0;
32833367 }
32843368
@@ -3339,8 +3423,7 @@ static void gfx_v9_0_exit_rlc_safe_mode(struct amdgpu_device *adev) · 54 unmodified lines
33393423 static void gfx_v9_0_update_gfx_cg_power_gating(struct amdgpu_device *adev,
33403424 bool enable)
33413425 {
3342− /* TODO: double check if we need to perform under safe mdoe */
3343− /* gfx_v9_0_enter_rlc_safe_mode(adev); */
3426+ gfx_v9_0_enter_rlc_safe_mode(adev);
33443427
33453428 if ((adev->pg_flags & AMD_PG_SUPPORT_GFX_PG) && enable) {
33463429 gfx_v9_0_enable_gfx_cg_power_gating(adev, true);
@@ -3351,7 +3434,7 @@ static void gfx_v9_0_update_gfx_cg_power_gating(struct amdgpu_device *adev, · 4 unmodified lines
33513434 gfx_v9_0_enable_gfx_pipeline_powergating(adev, false);
33523435 }
33533436
3354− /* gfx_v9_0_exit_rlc_safe_mode(adev); */
3437+ gfx_v9_0_exit_rlc_safe_mode(adev);
33553438 }
33563439
33573440 static void gfx_v9_0_update_gfx_mg_power_gating(struct amdgpu_device *adev,
@@ -3742,7 +3825,7 @@ static void gfx_v9_0_ring_emit_ib_gfx(struct amdgpu_ring *ring, · 384 unmodified lines
37423825 }
37433826
37443827 amdgpu_ring_write(ring, header);
3745−BUG_ON(ib->gpu_addr & 0x3); /* Dword align */
3828+ BUG_ON(ib->gpu_addr & 0x3); /* Dword align */
37463829 amdgpu_ring_write(ring,
37473830 #ifdef __BIG_ENDIAN
37483831 (2 << 0) |
@@ -3774,13 +3857,16 @@ static void gfx_v9_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, · 25 unmodified lines
37743857 {
37753858 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
37763859 bool int_sel = flags & AMDGPU_FENCE_FLAG_INT;
3860+ bool writeback = flags & AMDGPU_FENCE_FLAG_TC_WB_ONLY;
37773861
37783862 /* RELEASE_MEM - flush caches, send int */
37793863 amdgpu_ring_write(ring, PACKET3(PACKET3_RELEASE_MEM, 6));
3780− amdgpu_ring_write(ring, (EOP_TCL1_ACTION_EN |
3781− EOP_TC_ACTION_EN |
3782− EOP_TC_WB_ACTION_EN |
3783− EOP_TC_MD_ACTION_EN |
3864+ amdgpu_ring_write(ring, ((writeback ? (EOP_TC_WB_ACTION_EN |
3865+ EOP_TC_NC_ACTION_EN) :
3866+ (EOP_TCL1_ACTION_EN |
3867+ EOP_TC_ACTION_EN |
3868+ EOP_TC_WB_ACTION_EN |
3869+ EOP_TC_MD_ACTION_EN)) |
37843870 EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) |
37853871 EVENT_INDEX(5)));
37863872 amdgpu_ring_write(ring, DATA_SEL(write64bit ? 2 : 1) | INT_SEL(int_sel ? 2 : 0));
@@ -4137,6 +4223,20 @@ static void gfx_v9_0_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg, · 350 unmodified lines
41374223 gfx_v9_0_wait_reg_mem(ring, 0, 0, 0, reg, 0, val, mask, 0x20);
41384224 }
41394225
4226+static void gfx_v9_0_ring_emit_reg_write_reg_wait(struct amdgpu_ring *ring,
4227+ uint32_t reg0, uint32_t reg1,
4228+ uint32_t ref, uint32_t mask)
4229+{
4230+ int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX);
4231+
4232+ if (amdgpu_sriov_vf(ring->adev))
4233+ gfx_v9_0_wait_reg_mem(ring, usepfp, 0, 1, reg0, reg1,
4234+ ref, mask, 0x20);
4235+ else
4236+ amdgpu_ring_emit_reg_write_reg_wait_helper(ring, reg0, reg1,
4237+ ref, mask);
4238+}
4239+
41404240 static void gfx_v9_0_set_gfx_eop_interrupt_state(struct amdgpu_device *adev,
41414241 enum amdgpu_interrupt_state state)
41424242 {
@@ -4458,6 +4558,7 @@ static const struct amdgpu_ring_funcs gfx_v9_0_ring_funcs_gfx = { · 315 unmodified lines
44584558 .emit_tmz = gfx_v9_0_ring_emit_tmz,
44594559 .emit_wreg = gfx_v9_0_ring_emit_wreg,
44604560 .emit_reg_wait = gfx_v9_0_ring_emit_reg_wait,
4561+ .emit_reg_write_reg_wait = gfx_v9_0_ring_emit_reg_write_reg_wait,
44614562 };
44624563
44634564 static const struct amdgpu_ring_funcs gfx_v9_0_ring_funcs_compute = {
@@ -4492,6 +4593,7 @@ static const struct amdgpu_ring_funcs gfx_v9_0_ring_funcs_compute = { · 28 unmodified lines
44924593 .set_priority = gfx_v9_0_ring_set_priority_compute,
44934594 .emit_wreg = gfx_v9_0_ring_emit_wreg,
44944595 .emit_reg_wait = gfx_v9_0_ring_emit_reg_wait,
4596+ .emit_reg_write_reg_wait = gfx_v9_0_ring_emit_reg_write_reg_wait,
44954597 };
44964598
44974599 static const struct amdgpu_ring_funcs gfx_v9_0_ring_funcs_kiq = {
@@ -4522,6 +4624,7 @@ static const struct amdgpu_ring_funcs gfx_v9_0_ring_funcs_kiq = { · 24 unmodified lines
45224624 .emit_rreg = gfx_v9_0_ring_emit_rreg,
45234625 .emit_wreg = gfx_v9_0_ring_emit_wreg,
45244626 .emit_reg_wait = gfx_v9_0_ring_emit_reg_wait,
4627+ .emit_reg_write_reg_wait = gfx_v9_0_ring_emit_reg_write_reg_wait,
45254628 };
45264629
45274630 static void gfx_v9_0_set_ring_funcs(struct amdgpu_device *adev)
drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c+23−2
@@ -819,12 +819,33 @@ static int gmc_v6_0_late_init(void *handle) · 818 unmodified lines
819819 {
820820 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
821821
822+ amdgpu_bo_late_init(adev);
823+
822824 if (amdgpu_vm_fault_stop != AMDGPU_VM_FAULT_STOP_ALWAYS)
823825 return amdgpu_irq_get(adev, &adev->gmc.vm_fault, 0);
824826 else
825827 return 0;
826828 }
827829
830+static unsigned gmc_v6_0_get_vbios_fb_size(struct amdgpu_device *adev)
831+{
832+ u32 d1vga_control = RREG32(mmD1VGA_CONTROL);
833+ unsigned size;
834+
835+ if (REG_GET_FIELD(d1vga_control, D1VGA_CONTROL, D1VGA_MODE_ENABLE)) {
836+ size = 9 * 1024 * 1024; /* reserve 8MB for vga emulator and 1 MB for FB */
837+ } else {
838+ u32 viewport = RREG32(mmVIEWPORT_SIZE);
839+ size = (REG_GET_FIELD(viewport, VIEWPORT_SIZE, VIEWPORT_HEIGHT) *
840+ REG_GET_FIELD(viewport, VIEWPORT_SIZE, VIEWPORT_WIDTH) *
841+ 4);
842+ }
843+ /* return 0 if the pre-OS buffer uses up most of vram */
844+ if ((adev->gmc.real_vram_size - size) < (8 * 1024 * 1024))
845+ return 0;
846+ return size;
847+}
848+
828849 static int gmc_v6_0_sw_init(void *handle)
829850 {
830851 int r;
@@ -851,8 +872,6 @@ static int gmc_v6_0_sw_init(void *handle) · 20 unmodified lines
851872
852873 adev->gmc.mc_mask = 0xffffffffffULL;
853874
854− adev->gmc.stolen_size = 256 * 1024;
855−
856875 adev->need_dma32 = false;
857876 dma_bits = adev->need_dma32 ? 32 : 40;
858877 r = pci_set_dma_mask(adev->pdev, DMA_BIT_MASK(dma_bits));
@@ -878,6 +897,8 @@ static int gmc_v6_0_sw_init(void *handle) · 19 unmodified lines
878897 if (r)
879898 return r;
880899
900+ adev->gmc.stolen_size = gmc_v6_0_get_vbios_fb_size(adev);
901+
881902 r = amdgpu_bo_init(adev);
882903 if (r)
883904 return r;
drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c+23−2
@@ -958,12 +958,33 @@ static int gmc_v7_0_late_init(void *handle) · 957 unmodified lines
958958 {
959959 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
960960
961+ amdgpu_bo_late_init(adev);
962+
961963 if (amdgpu_vm_fault_stop != AMDGPU_VM_FAULT_STOP_ALWAYS)
962964 return amdgpu_irq_get(adev, &adev->gmc.vm_fault, 0);
963965 else
964966 return 0;
965967 }
966968
969+static unsigned gmc_v7_0_get_vbios_fb_size(struct amdgpu_device *adev)
970+{
971+ u32 d1vga_control = RREG32(mmD1VGA_CONTROL);
972+ unsigned size;
973+
974+ if (REG_GET_FIELD(d1vga_control, D1VGA_CONTROL, D1VGA_MODE_ENABLE)) {
975+ size = 9 * 1024 * 1024; /* reserve 8MB for vga emulator and 1 MB for FB */
976+ } else {
977+ u32 viewport = RREG32(mmVIEWPORT_SIZE);
978+ size = (REG_GET_FIELD(viewport, VIEWPORT_SIZE, VIEWPORT_HEIGHT) *
979+ REG_GET_FIELD(viewport, VIEWPORT_SIZE, VIEWPORT_WIDTH) *
980+ 4);
981+ }
982+ /* return 0 if the pre-OS buffer uses up most of vram */
983+ if ((adev->gmc.real_vram_size - size) < (8 * 1024 * 1024))
984+ return 0;
985+ return size;
986+}
987+
967988 static int gmc_v7_0_sw_init(void *handle)
968989 {
969990 int r;
@@ -998,8 +1019,6 @@ static int gmc_v7_0_sw_init(void *handle) · 28 unmodified lines
9981019 */
9991020 adev->gmc.mc_mask = 0xffffffffffULL; /* 40 bit MC */
10001021
1001− adev->gmc.stolen_size = 256 * 1024;
1002−
10031022 /* set DMA mask + need_dma32 flags.
10041023 * PCIE - can handle 40-bits.
10051024 * IGP - can handle 40-bits
@@ -1030,6 +1049,8 @@ static int gmc_v7_0_sw_init(void *handle) · 24 unmodified lines
10301049 if (r)
10311050 return r;
10321051
1052+ adev->gmc.stolen_size = gmc_v7_0_get_vbios_fb_size(adev);
1053+
10331054 /* Memory manager */
10341055 r = amdgpu_bo_init(adev);
10351056 if (r)
drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c+29−4
@@ -138,6 +138,7 @@ static void gmc_v8_0_init_golden_registers(struct amdgpu_device *adev) · 137 unmodified lines
138138 break;
139139 case CHIP_POLARIS11:
140140 case CHIP_POLARIS12:
141+ case CHIP_VEGAM:
141142 amdgpu_device_program_register_sequence(adev,
142143 golden_settings_polaris11_a11,
143144 ARRAY_SIZE(golden_settings_polaris11_a11));
@@ -231,6 +232,7 @@ static int gmc_v8_0_init_microcode(struct amdgpu_device *adev) · 87 unmodified lines
231232 case CHIP_FIJI:
232233 case CHIP_CARRIZO:
233234 case CHIP_STONEY:
235+ case CHIP_VEGAM:
234236 return 0;
235237 default: BUG();
236238 }
@@ -567,9 +569,10 @@ static int gmc_v8_0_mc_init(struct amdgpu_device *adev) · 330 unmodified lines
567569 /* set the gart size */
568570 if (amdgpu_gart_size == -1) {
569571 switch (adev->asic_type) {
570− case CHIP_POLARIS11: /* all engines support GPUVM */
571572 case CHIP_POLARIS10: /* all engines support GPUVM */
573+ case CHIP_POLARIS11: /* all engines support GPUVM */
572574 case CHIP_POLARIS12: /* all engines support GPUVM */
575+ case CHIP_VEGAM: /* all engines support GPUVM */
573576 default:
574577 adev->gmc.gart_size = 256ULL << 20;
575578 break;
@@ -1049,12 +1052,33 @@ static int gmc_v8_0_late_init(void *handle) · 473 unmodified lines
10491052 {
10501053 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
10511054
1055+ amdgpu_bo_late_init(adev);
1056+
10521057 if (amdgpu_vm_fault_stop != AMDGPU_VM_FAULT_STOP_ALWAYS)
10531058 return amdgpu_irq_get(adev, &adev->gmc.vm_fault, 0);
10541059 else
10551060 return 0;
10561061 }
10571062
1063+static unsigned gmc_v8_0_get_vbios_fb_size(struct amdgpu_device *adev)
1064+{
1065+ u32 d1vga_control = RREG32(mmD1VGA_CONTROL);
1066+ unsigned size;
1067+
1068+ if (REG_GET_FIELD(d1vga_control, D1VGA_CONTROL, D1VGA_MODE_ENABLE)) {
1069+ size = 9 * 1024 * 1024; /* reserve 8MB for vga emulator and 1 MB for FB */
1070+ } else {
1071+ u32 viewport = RREG32(mmVIEWPORT_SIZE);
1072+ size = (REG_GET_FIELD(viewport, VIEWPORT_SIZE, VIEWPORT_HEIGHT) *
1073+ REG_GET_FIELD(viewport, VIEWPORT_SIZE, VIEWPORT_WIDTH) *
1074+ 4);
1075+ }
1076+ /* return 0 if the pre-OS buffer uses up most of vram */
1077+ if ((adev->gmc.real_vram_size - size) < (8 * 1024 * 1024))
1078+ return 0;
1079+ return size;
1080+}
1081+
10581082 #define mmMC_SEQ_MISC0_FIJI 0xA71
10591083
10601084 static int gmc_v8_0_sw_init(void *handle)
@@ -1068,7 +1092,8 @@ static int gmc_v8_0_sw_init(void *handle) · 7 unmodified lines
10681092 } else {
10691093 u32 tmp;
10701094
1071− if (adev->asic_type == CHIP_FIJI)
1095+ if ((adev->asic_type == CHIP_FIJI) ||
1096+ (adev->asic_type == CHIP_VEGAM))
10721097 tmp = RREG32(mmMC_SEQ_MISC0_FIJI);
10731098 else
10741099 tmp = RREG32(mmMC_SEQ_MISC0);
@@ -1096,8 +1121,6 @@ static int gmc_v8_0_sw_init(void *handle) · 21 unmodified lines
10961121 */
10971122 adev->gmc.mc_mask = 0xffffffffffULL; /* 40 bit MC */
10981123
1099− adev->gmc.stolen_size = 256 * 1024;
1100−
11011124 /* set DMA mask + need_dma32 flags.
11021125 * PCIE - can handle 40-bits.
11031126 * IGP - can handle 40-bits
@@ -1128,6 +1151,8 @@ static int gmc_v8_0_sw_init(void *handle) · 24 unmodified lines
11281151 if (r)
11291152 return r;
11301153
1154+ adev->gmc.stolen_size = gmc_v8_0_get_vbios_fb_size(adev);
1155+
11311156 /* Memory manager */
11321157 r = amdgpu_bo_init(adev);
11331158 if (r)
drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c+77−60
@@ -43,19 +43,13 @@ · 42 unmodified lines
4343 #include "gfxhub_v1_0.h"
4444 #include "mmhub_v1_0.h"
4545
46−#define mmDF_CS_AON0_DramBaseAddress0 0x0044
47−#define mmDF_CS_AON0_DramBaseAddress0_BASE_IDX 0
48−//DF_CS_AON0_DramBaseAddress0
49−#define DF_CS_AON0_DramBaseAddress0__AddrRngVal__SHIFT 0x0
50−#define DF_CS_AON0_DramBaseAddress0__LgcyMmioHoleEn__SHIFT 0x1
51−#define DF_CS_AON0_DramBaseAddress0__IntLvNumChan__SHIFT 0x4
52−#define DF_CS_AON0_DramBaseAddress0__IntLvAddrSel__SHIFT 0x8
53−#define DF_CS_AON0_DramBaseAddress0__DramBaseAddr__SHIFT 0xc
54−#define DF_CS_AON0_DramBaseAddress0__AddrRngVal_MASK 0x00000001L
55−#define DF_CS_AON0_DramBaseAddress0__LgcyMmioHoleEn_MASK 0x00000002L
56−#define DF_CS_AON0_DramBaseAddress0__IntLvNumChan_MASK 0x000000F0L
57−#define DF_CS_AON0_DramBaseAddress0__IntLvAddrSel_MASK 0x00000700L
58−#define DF_CS_AON0_DramBaseAddress0__DramBaseAddr_MASK 0xFFFFF000L
46+/* add these here since we already include dce12 headers and these are for DCN */
47+#define mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION 0x055d
48+#define mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_BASE_IDX 2
49+#define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_WIDTH__SHIFT 0x0
50+#define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_HEIGHT__SHIFT 0x10
51+#define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_WIDTH_MASK 0x00003FFFL
52+#define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_HEIGHT_MASK 0x3FFF0000L
5953
6054 /* XXX Move this macro to VEGA10 header file, which is like vid.h for VI.*/
6155 #define AMDGPU_NUM_OF_VMIDS 8
@@ -385,11 +379,9 @@ static uint64_t gmc_v9_0_emit_flush_gpu_tlb(struct amdgpu_ring *ring, · 323 unmodified lines
385379 amdgpu_ring_emit_wreg(ring, hub->ctx0_ptb_addr_hi32 + (2 * vmid),
386380 upper_32_bits(pd_addr));
387381
388− amdgpu_ring_emit_wreg(ring, hub->vm_inv_eng0_req + eng, req);
389−
390− /* wait for the invalidate to complete */
391− amdgpu_ring_emit_reg_wait(ring, hub->vm_inv_eng0_ack + eng,
392− 1 << vmid, 1 << vmid);
382+ amdgpu_ring_emit_reg_write_reg_wait(ring, hub->vm_inv_eng0_req + eng,
383+ hub->vm_inv_eng0_ack + eng,
384+ req, 1 << vmid);
393385
394386 return pd_addr;
395387 }
@@ -556,8 +548,7 @@ static int gmc_v9_0_early_init(void *handle) · 160 unmodified lines
556548 adev->gmc.shared_aperture_start = 0x2000000000000000ULL;
557549 adev->gmc.shared_aperture_end =
558550 adev->gmc.shared_aperture_start + (4ULL << 30) - 1;
559− adev->gmc.private_aperture_start =
560− adev->gmc.shared_aperture_end + 1;
551+ adev->gmc.private_aperture_start = 0x1000000000000000ULL;
561552 adev->gmc.private_aperture_end =
562553 adev->gmc.private_aperture_start + (4ULL << 30) - 1;
563554
@@ -659,6 +650,11 @@ static int gmc_v9_0_late_init(void *handle) · 95 unmodified lines
659650 unsigned i;
660651 int r;
661652
653+ /*
654+ * TODO - Uncomment once GART corruption issue is fixed.
655+ */
656+ /* amdgpu_bo_late_init(adev); */
657+
662658 for(i = 0; i < adev->num_rings; ++i) {
663659 struct amdgpu_ring *ring = adev->rings[i];
664660 unsigned vmhub = ring->funcs->vmhub;
@@ -714,7 +710,6 @@ static void gmc_v9_0_vram_gtt_location(struct amdgpu_device *adev, · 49 unmodified lines
714710 */
715711 static int gmc_v9_0_mc_init(struct amdgpu_device *adev)
716712 {
717− u32 tmp;
718713 int chansize, numchan;
719714 int r;
720715
@@ -727,39 +722,7 @@ static int gmc_v9_0_mc_init(struct amdgpu_device *adev) · 6 unmodified lines
727722 else
728723 chansize = 128;
729724
730− tmp = RREG32_SOC15(DF, 0, mmDF_CS_AON0_DramBaseAddress0);
731− tmp &= DF_CS_AON0_DramBaseAddress0__IntLvNumChan_MASK;
732− tmp >>= DF_CS_AON0_DramBaseAddress0__IntLvNumChan__SHIFT;
733− switch (tmp) {
734− case 0:
735− default:
736− numchan = 1;
737− break;
738− case 1:
739− numchan = 2;
740− break;
741− case 2:
742− numchan = 0;
743− break;
744− case 3:
745− numchan = 4;
746− break;
747− case 4:
748− numchan = 0;
749− break;
750− case 5:
751− numchan = 8;
752− break;
753− case 6:
754− numchan = 0;
755− break;
756− case 7:
757− numchan = 16;
758− break;
759− case 8:
760− numchan = 2;
761− break;
762− }
725+ numchan = adev->df_funcs->get_hbm_channel_number(adev);
763726 adev->gmc.vram_width = numchan * chansize;
764727 }
765728
@@ -826,6 +789,52 @@ static int gmc_v9_0_gart_init(struct amdgpu_device *adev) · 60 unmodified lines
826789 return amdgpu_gart_table_vram_alloc(adev);
827790 }
828791
792+static unsigned gmc_v9_0_get_vbios_fb_size(struct amdgpu_device *adev)
793+{
794+#if 0
795+ u32 d1vga_control = RREG32_SOC15(DCE, 0, mmD1VGA_CONTROL);
796+#endif
797+ unsigned size;
798+
799+ /*
800+ * TODO Remove once GART corruption is resolved
801+ * Check related code in gmc_v9_0_sw_fini
802+ * */
803+ size = 9 * 1024 * 1024;
804+
805+#if 0
806+ if (REG_GET_FIELD(d1vga_control, D1VGA_CONTROL, D1VGA_MODE_ENABLE)) {
807+ size = 9 * 1024 * 1024; /* reserve 8MB for vga emulator and 1 MB for FB */
808+ } else {
809+ u32 viewport;
810+
811+ switch (adev->asic_type) {
812+ case CHIP_RAVEN:
813+ viewport = RREG32_SOC15(DCE, 0, mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION);
814+ size = (REG_GET_FIELD(viewport,
815+ HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION, PRI_VIEWPORT_HEIGHT) *
816+ REG_GET_FIELD(viewport,
817+ HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION, PRI_VIEWPORT_WIDTH) *
818+ 4);
819+ break;
820+ case CHIP_VEGA10:
821+ case CHIP_VEGA12:
822+ default:
823+ viewport = RREG32_SOC15(DCE, 0, mmSCL0_VIEWPORT_SIZE);
824+ size = (REG_GET_FIELD(viewport, SCL0_VIEWPORT_SIZE, VIEWPORT_HEIGHT) *
825+ REG_GET_FIELD(viewport, SCL0_VIEWPORT_SIZE, VIEWPORT_WIDTH) *
826+ 4);
827+ break;
828+ }
829+ }
830+ /* return 0 if the pre-OS buffer uses up most of vram */
831+ if ((adev->gmc.real_vram_size - size) < (8 * 1024 * 1024))
832+ return 0;
833+
834+#endif
835+ return size;
836+}
837+
829838 static int gmc_v9_0_sw_init(void *handle)
830839 {
831840 int r;
@@ -877,12 +886,6 @@ static int gmc_v9_0_sw_init(void *handle) · 45 unmodified lines
877886 */
878887 adev->gmc.mc_mask = 0xffffffffffffULL; /* 48 bit MC */
879888
880− /*
881− * It needs to reserve 8M stolen memory for vega10
882− * TODO: Figure out how to avoid that...
883− */
884− adev->gmc.stolen_size = 8 * 1024 * 1024;
885−
886889 /* set DMA mask + need_dma32 flags.
887890 * PCIE - can handle 44-bits.
888891 * IGP - can handle 44-bits
@@ -907,6 +910,8 @@ static int gmc_v9_0_sw_init(void *handle) · 18 unmodified lines
907910 if (r)
908911 return r;
909912
913+ adev->gmc.stolen_size = gmc_v9_0_get_vbios_fb_size(adev);
914+
910915 /* Memory manager */
911916 r = amdgpu_bo_init(adev);
912917 if (r)
@@ -950,6 +955,18 @@ static int gmc_v9_0_sw_fini(void *handle) · 37 unmodified lines
950955 amdgpu_gem_force_release(adev);
951956 amdgpu_vm_manager_fini(adev);
952957 gmc_v9_0_gart_fini(adev);
958+
959+ /*
960+ * TODO:
961+ * Currently there is a bug where some memory client outside
962+ * of the driver writes to first 8M of VRAM on S3 resume,
963+ * this overrides GART which by default gets placed in first 8M and
964+ * causes VM_FAULTS once GTT is accessed.
965+ * Keep the stolen memory reservation until the while this is not solved.
966+ * Also check code in gmc_v9_0_get_vbios_fb_size and gmc_v9_0_late_init
967+ */
968+ amdgpu_bo_free_kernel(&adev->stolen_vga_memory, NULL, NULL);
969+
953970 amdgpu_bo_fini(adev);
954971
955972 return 0;
drivers/gpu/drm/amd/amdgpu/kv_dpm.c+2−2
@@ -2817,7 +2817,7 @@ static int kv_dpm_init(struct amdgpu_device *adev) · 2816 unmodified lines
28172817 pi->caps_tcp_ramping = true;
28182818 }
28192819
2820− if (amdgpu_pp_feature_mask & SCLK_DEEP_SLEEP_MASK)
2820+ if (adev->powerplay.pp_feature & PP_SCLK_DEEP_SLEEP_MASK)
28212821 pi->caps_sclk_ds = true;
28222822 else
28232823 pi->caps_sclk_ds = false;
@@ -2974,7 +2974,7 @@ static int kv_dpm_late_init(void *handle) · 150 unmodified lines
29742974 /* powerdown unused blocks for now */
29752975 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
29762976
2977− if (!amdgpu_dpm)
2977+ if (!adev->pm.dpm_enabled)
29782978 return 0;
29792979
29802980 kv_dpm_powergate_acp(adev, true);
drivers/gpu/drm/amd/amdgpu/mxgpu_ai.c+3−1
@@ -260,8 +260,10 @@ static void xgpu_ai_mailbox_flr_work(struct work_struct *work) · 259 unmodified lines
260260 } while (timeout > 1);
261261
262262 flr_done:
263− if (locked)
263+ if (locked) {
264+ adev->in_gpu_reset = 0;
264265 mutex_unlock(&adev->lock_reset);
266+ }
265267
266268 /* Trigger recovery for world switch failure if no TDR */
267269 if (amdgpu_lockup_timeout == 0)
drivers/gpu/drm/amd/amdgpu/psp_gfx_if.h+46−21
@@ -40,11 +40,20 @@ enum psp_gfx_crtl_cmd_id · 39 unmodified lines
4040 GFX_CTRL_CMD_ID_INIT_GPCOM_RING = 0x00020000, /* initialize GPCOM ring */
4141 GFX_CTRL_CMD_ID_DESTROY_RINGS = 0x00030000, /* destroy rings */
4242 GFX_CTRL_CMD_ID_CAN_INIT_RINGS = 0x00040000, /* is it allowed to initialized the rings */
43+ GFX_CTRL_CMD_ID_ENABLE_INT = 0x00050000, /* enable PSP-to-Gfx interrupt */
44+ GFX_CTRL_CMD_ID_DISABLE_INT = 0x00060000, /* disable PSP-to-Gfx interrupt */
45+ GFX_CTRL_CMD_ID_MODE1_RST = 0x00070000, /* trigger the Mode 1 reset */
4346
4447 GFX_CTRL_CMD_ID_MAX = 0x000F0000, /* max command ID */
4548 };
4649
4750
51+/*-----------------------------------------------------------------------------
52+ NOTE: All physical addresses used in this interface are actually
53+ GPU Virtual Addresses.
54+*/
55+
56+
4857 /* Control registers of the TEE Gfx interface. These are located in
4958 * SRBM-to-PSP mailbox registers (total 8 registers).
5059 */
@@ -55,8 +64,8 @@ struct psp_gfx_ctrl · 4 unmodified lines
5564 volatile uint32_t rbi_rptr; /* +8 Read pointer (index) of RBI ring */
5665 volatile uint32_t gpcom_wptr; /* +12 Write pointer (index) of GPCOM ring */
5766 volatile uint32_t gpcom_rptr; /* +16 Read pointer (index) of GPCOM ring */
58− volatile uint32_t ring_addr_lo; /* +20 bits [31:0] of physical address of ring buffer */
59− volatile uint32_t ring_addr_hi; /* +24 bits [63:32] of physical address of ring buffer */
67+ volatile uint32_t ring_addr_lo; /* +20 bits [31:0] of GPU Virtual of ring buffer (VMID=0)*/
68+ volatile uint32_t ring_addr_hi; /* +24 bits [63:32] of GPU Virtual of ring buffer (VMID=0) */
6069 volatile uint32_t ring_buf_size; /* +28 Ring buffer size (in bytes) */
6170
6271 };
@@ -78,6 +87,8 @@ enum psp_gfx_cmd_id · 15 unmodified lines
7887 GFX_CMD_ID_LOAD_ASD = 0x00000004, /* load ASD Driver */
7988 GFX_CMD_ID_SETUP_TMR = 0x00000005, /* setup TMR region */
8089 GFX_CMD_ID_LOAD_IP_FW = 0x00000006, /* load HW IP FW */
90+ GFX_CMD_ID_DESTROY_TMR = 0x00000007, /* destroy TMR region */
91+ GFX_CMD_ID_SAVE_RESTORE = 0x00000008, /* save/restore HW IP FW */
8192
8293 };
8394
@@ -85,11 +96,11 @@ enum psp_gfx_cmd_id · 1 unmodified line
8596 /* Command to load Trusted Application binary into PSP OS. */
8697 struct psp_gfx_cmd_load_ta
8798 {
88− uint32_t app_phy_addr_lo; /* bits [31:0] of the physical address of the TA binary (must be 4 KB aligned) */
89− uint32_t app_phy_addr_hi; /* bits [63:32] of the physical address of the TA binary */
99+ uint32_t app_phy_addr_lo; /* bits [31:0] of the GPU Virtual address of the TA binary (must be 4 KB aligned) */
100+ uint32_t app_phy_addr_hi; /* bits [63:32] of the GPU Virtual address of the TA binary */
90101 uint32_t app_len; /* length of the TA binary in bytes */
91− uint32_t cmd_buf_phy_addr_lo; /* bits [31:0] of the physical address of CMD buffer (must be 4 KB aligned) */
92− uint32_t cmd_buf_phy_addr_hi; /* bits [63:32] of the physical address of CMD buffer */
102+ uint32_t cmd_buf_phy_addr_lo; /* bits [31:0] of the GPU Virtual address of CMD buffer (must be 4 KB aligned) */
103+ uint32_t cmd_buf_phy_addr_hi; /* bits [63:32] of the GPU Virtual address of CMD buffer */
93104 uint32_t cmd_buf_len; /* length of the CMD buffer in bytes; must be multiple of 4 KB */
94105
95106 /* Note: CmdBufLen can be set to 0. In this case no persistent CMD buffer is provided
@@ -111,8 +122,8 @@ struct psp_gfx_cmd_unload_ta · 15 unmodified lines
111122 */
112123 struct psp_gfx_buf_desc
113124 {
114− uint32_t buf_phy_addr_lo; /* bits [31:0] of physical address of the buffer (must be 4 KB aligned) */
115− uint32_t buf_phy_addr_hi; /* bits [63:32] of physical address of the buffer */
125+ uint32_t buf_phy_addr_lo; /* bits [31:0] of GPU Virtual address of the buffer (must be 4 KB aligned) */
126+ uint32_t buf_phy_addr_hi; /* bits [63:32] of GPU Virtual address of the buffer */
116127 uint32_t buf_size; /* buffer size in bytes (must be multiple of 4 KB and no bigger than 64 MB) */
117128
118129 };
@@ -145,8 +156,8 @@ struct psp_gfx_cmd_invoke_cmd · 26 unmodified lines
145156 /* Command to setup TMR region. */
146157 struct psp_gfx_cmd_setup_tmr
147158 {
148− uint32_t buf_phy_addr_lo; /* bits [31:0] of physical address of TMR buffer (must be 4 KB aligned) */
149− uint32_t buf_phy_addr_hi; /* bits [63:32] of physical address of TMR buffer */
159+ uint32_t buf_phy_addr_lo; /* bits [31:0] of GPU Virtual address of TMR buffer (must be 4 KB aligned) */
160+ uint32_t buf_phy_addr_hi; /* bits [63:32] of GPU Virtual address of TMR buffer */
150161 uint32_t buf_size; /* buffer size in bytes (must be multiple of 4 KB) */
151162
152163 };
@@ -174,18 +185,32 @@ enum psp_gfx_fw_type · 21 unmodified lines
174185 GFX_FW_TYPE_ISP = 16,
175186 GFX_FW_TYPE_ACP = 17,
176187 GFX_FW_TYPE_SMU = 18,
188+ GFX_FW_TYPE_MMSCH = 19,
189+ GFX_FW_TYPE_RLC_RESTORE_LIST_GPM_MEM = 20,
190+ GFX_FW_TYPE_RLC_RESTORE_LIST_SRM_MEM = 21,
191+ GFX_FW_TYPE_RLC_RESTORE_LIST_CNTL = 22,
192+ GFX_FW_TYPE_MAX = 23
177193 };
178194
179195 /* Command to load HW IP FW. */
180196 struct psp_gfx_cmd_load_ip_fw
181197 {
182− uint32_t fw_phy_addr_lo; /* bits [31:0] of physical address of FW location (must be 4 KB aligned) */
183− uint32_t fw_phy_addr_hi; /* bits [63:32] of physical address of FW location */
198+ uint32_t fw_phy_addr_lo; /* bits [31:0] of GPU Virtual address of FW location (must be 4 KB aligned) */
199+ uint32_t fw_phy_addr_hi; /* bits [63:32] of GPU Virtual address of FW location */
184200 uint32_t fw_size; /* FW buffer size in bytes */
185201 enum psp_gfx_fw_type fw_type; /* FW type */
186202
187203 };
188204
205+/* Command to save/restore HW IP FW. */
206+struct psp_gfx_cmd_save_restore_ip_fw
207+{
208+ uint32_t save_fw; /* if set, command is used for saving fw otherwise for resetoring*/
209+ uint32_t save_restore_addr_lo; /* bits [31:0] of FB address of GART memory used as save/restore buffer (must be 4 KB aligned) */
210+ uint32_t save_restore_addr_hi; /* bits [63:32] of FB address of GART memory used as save/restore buffer */
211+ uint32_t buf_size; /* Size of the save/restore buffer in bytes */
212+ enum psp_gfx_fw_type fw_type; /* FW type */
213+};
189214
190215 /* All GFX ring buffer commands. */
191216 union psp_gfx_commands
@@ -195,7 +220,7 @@ union psp_gfx_commands · 3 unmodified lines
195220 struct psp_gfx_cmd_invoke_cmd cmd_invoke_cmd;
196221 struct psp_gfx_cmd_setup_tmr cmd_setup_tmr;
197222 struct psp_gfx_cmd_load_ip_fw cmd_load_ip_fw;
198−
223+ struct psp_gfx_cmd_save_restore_ip_fw cmd_save_restore_ip_fw;
199224 };
200225
201226
@@ -226,8 +251,8 @@ struct psp_gfx_cmd_resp · 24 unmodified lines
226251
227252 /* These fields are used for RBI only. They are all 0 in GPCOM commands
228253 */
229− uint32_t resp_buf_addr_lo; /* +12 bits [31:0] of physical address of response buffer (must be 4 KB aligned) */
230− uint32_t resp_buf_addr_hi; /* +16 bits [63:32] of physical address of response buffer */
254+ uint32_t resp_buf_addr_lo; /* +12 bits [31:0] of GPU Virtual address of response buffer (must be 4 KB aligned) */
255+ uint32_t resp_buf_addr_hi; /* +16 bits [63:32] of GPU Virtual address of response buffer */
231256 uint32_t resp_offset; /* +20 offset within response buffer */
232257 uint32_t resp_buf_size; /* +24 total size of the response buffer in bytes */
233258
@@ -251,19 +276,19 @@ struct psp_gfx_cmd_resp · 17 unmodified lines
251276 /* Structure of the Ring Buffer Frame */
252277 struct psp_gfx_rb_frame
253278 {
254− uint32_t cmd_buf_addr_lo; /* +0 bits [31:0] of physical address of command buffer (must be 4 KB aligned) */
255− uint32_t cmd_buf_addr_hi; /* +4 bits [63:32] of physical address of command buffer */
279+ uint32_t cmd_buf_addr_lo; /* +0 bits [31:0] of GPU Virtual address of command buffer (must be 4 KB aligned) */
280+ uint32_t cmd_buf_addr_hi; /* +4 bits [63:32] of GPU Virtual address of command buffer */
256281 uint32_t cmd_buf_size; /* +8 command buffer size in bytes */
257− uint32_t fence_addr_lo; /* +12 bits [31:0] of physical address of Fence for this frame */
258− uint32_t fence_addr_hi; /* +16 bits [63:32] of physical address of Fence for this frame */
282+ uint32_t fence_addr_lo; /* +12 bits [31:0] of GPU Virtual address of Fence for this frame */
283+ uint32_t fence_addr_hi; /* +16 bits [63:32] of GPU Virtual address of Fence for this frame */
259284 uint32_t fence_value; /* +20 Fence value */
260285 uint32_t sid_lo; /* +24 bits [31:0] of SID value (used only for RBI frames) */
261286 uint32_t sid_hi; /* +28 bits [63:32] of SID value (used only for RBI frames) */
262287 uint8_t vmid; /* +32 VMID value used for mapping of all addresses for this frame */
263288 uint8_t frame_type; /* +33 1: destory context frame, 0: all other frames; used only for RBI frames */
264289 uint8_t reserved1[2]; /* +34 reserved, must be 0 */
265− uint32_t reserved2[7]; /* +40 reserved, must be 0 */
266− /* total 64 bytes */
290+ uint32_t reserved2[7]; /* +36 reserved, must be 0 */
291+ /* total 64 bytes */
267292 };
268293
269294 #endif /* _PSP_TEE_GFX_IF_H_ */
drivers/gpu/drm/amd/amdgpu/psp_v10_0.c+9−0
@@ -70,6 +70,15 @@ psp_v10_0_get_fw_type(struct amdgpu_firmware_info *ucode, enum psp_gfx_fw_type * · 69 unmodified lines
7070 case AMDGPU_UCODE_ID_RLC_G:
7171 *type = GFX_FW_TYPE_RLC_G;
7272 break;
73+ case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL:
74+ *type = GFX_FW_TYPE_RLC_RESTORE_LIST_CNTL;
75+ break;
76+ case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM:
77+ *type = GFX_FW_TYPE_RLC_RESTORE_LIST_GPM_MEM;
78+ break;
79+ case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM:
80+ *type = GFX_FW_TYPE_RLC_RESTORE_LIST_SRM_MEM;
81+ break;
7382 case AMDGPU_UCODE_ID_SMC:
7483 *type = GFX_FW_TYPE_SMU;
7584 break;
drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c+9−3
@@ -62,6 +62,8 @@ MODULE_FIRMWARE("amdgpu/polaris11_sdma.bin"); · 61 unmodified lines
6262 MODULE_FIRMWARE("amdgpu/polaris11_sdma1.bin");
6363 MODULE_FIRMWARE("amdgpu/polaris12_sdma.bin");
6464 MODULE_FIRMWARE("amdgpu/polaris12_sdma1.bin");
65+MODULE_FIRMWARE("amdgpu/vegam_sdma.bin");
66+MODULE_FIRMWARE("amdgpu/vegam_sdma1.bin");
6567
6668
6769 static const u32 sdma_offsets[SDMA_MAX_INSTANCE] =
@@ -209,6 +211,7 @@ static void sdma_v3_0_init_golden_registers(struct amdgpu_device *adev) · 141 unmodified lines
209211 break;
210212 case CHIP_POLARIS11:
211213 case CHIP_POLARIS12:
214+ case CHIP_VEGAM:
212215 amdgpu_device_program_register_sequence(adev,
213216 golden_settings_polaris11_a11,
214217 ARRAY_SIZE(golden_settings_polaris11_a11));
@@ -275,15 +278,18 @@ static int sdma_v3_0_init_microcode(struct amdgpu_device *adev) · 60 unmodified lines
275278 case CHIP_FIJI:
276279 chip_name = "fiji";
277280 break;
278− case CHIP_POLARIS11:
279− chip_name = "polaris11";
280− break;
281281 case CHIP_POLARIS10:
282282 chip_name = "polaris10";
283283 break;
284+ case CHIP_POLARIS11:
285+ chip_name = "polaris11";
286+ break;
284287 case CHIP_POLARIS12:
285288 chip_name = "polaris12";
286289 break;
290+ case CHIP_VEGAM:
291+ chip_name = "vegam";
292+ break;
287293 case CHIP_CARRIZO:
288294 chip_name = "carrizo";
289295 break;
drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c+35−28
@@ -360,6 +360,31 @@ static void sdma_v4_0_ring_emit_ib(struct amdgpu_ring *ring, · 359 unmodified lines
360360
361361 }
362362
363+static void sdma_v4_0_wait_reg_mem(struct amdgpu_ring *ring,
364+ int mem_space, int hdp,
365+ uint32_t addr0, uint32_t addr1,
366+ uint32_t ref, uint32_t mask,
367+ uint32_t inv)
368+{
369+ amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) |
370+ SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(hdp) |
371+ SDMA_PKT_POLL_REGMEM_HEADER_MEM_POLL(mem_space) |
372+ SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)); /* == */
373+ if (mem_space) {
374+ /* memory */
375+ amdgpu_ring_write(ring, addr0);
376+ amdgpu_ring_write(ring, addr1);
377+ } else {
378+ /* registers */
379+ amdgpu_ring_write(ring, addr0 << 2);
380+ amdgpu_ring_write(ring, addr1 << 2);
381+ }
382+ amdgpu_ring_write(ring, ref); /* reference */
383+ amdgpu_ring_write(ring, mask); /* mask */
384+ amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
385+ SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(inv)); /* retry count, poll interval */
386+}
387+
363388 /**
364389 * sdma_v4_0_ring_emit_hdp_flush - emit an hdp flush on the DMA ring
365390 *
@@ -378,15 +403,10 @@ static void sdma_v4_0_ring_emit_hdp_flush(struct amdgpu_ring *ring) · 12 unmodified lines
378403 else
379404 ref_and_mask = nbio_hf_reg->ref_and_mask_sdma1;
380405
381− amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) |
382− SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(1) |
383− SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)); /* == */
384− amdgpu_ring_write(ring, (adev->nbio_funcs->get_hdp_flush_done_offset(adev)) << 2);
385− amdgpu_ring_write(ring, (adev->nbio_funcs->get_hdp_flush_req_offset(adev)) << 2);
386− amdgpu_ring_write(ring, ref_and_mask); /* reference */
387− amdgpu_ring_write(ring, ref_and_mask); /* mask */
388− amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
389− SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); /* retry count, poll interval */
406+ sdma_v4_0_wait_reg_mem(ring, 0, 1,
407+ adev->nbio_funcs->get_hdp_flush_done_offset(adev),
408+ adev->nbio_funcs->get_hdp_flush_req_offset(adev),
409+ ref_and_mask, ref_and_mask, 10);
390410 }
391411
392412 /**
@@ -1114,16 +1134,10 @@ static void sdma_v4_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring) · 721 unmodified lines
11141134 uint64_t addr = ring->fence_drv.gpu_addr;
11151135
11161136 /* wait for idle */
1117− amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) |
1118− SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(0) |
1119− SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3) | /* equal */
1120− SDMA_PKT_POLL_REGMEM_HEADER_MEM_POLL(1));
1121− amdgpu_ring_write(ring, addr & 0xfffffffc);
1122− amdgpu_ring_write(ring, upper_32_bits(addr) & 0xffffffff);
1123− amdgpu_ring_write(ring, seq); /* reference */
1124− amdgpu_ring_write(ring, 0xffffffff); /* mask */
1125− amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
1126− SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(4)); /* retry count, poll interval */
1137+ sdma_v4_0_wait_reg_mem(ring, 1, 0,
1138+ addr & 0xfffffffc,
1139+ upper_32_bits(addr) & 0xffffffff,
1140+ seq, 0xffffffff, 4);
11271141 }
11281142
11291143
@@ -1154,15 +1168,7 @@ static void sdma_v4_0_ring_emit_wreg(struct amdgpu_ring *ring, · 24 unmodified lines
11541168 static void sdma_v4_0_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg,
11551169 uint32_t val, uint32_t mask)
11561170 {
1157− amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) |
1158− SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(0) |
1159− SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)); /* equal */
1160− amdgpu_ring_write(ring, reg << 2);
1161− amdgpu_ring_write(ring, 0);
1162− amdgpu_ring_write(ring, val); /* reference */
1163− amdgpu_ring_write(ring, mask); /* mask */
1164− amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
1165− SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10));
1171+ sdma_v4_0_wait_reg_mem(ring, 0, 0, reg, 0, val, mask, 10);
11661172 }
11671173
11681174 static int sdma_v4_0_early_init(void *handle)
@@ -1605,6 +1611,7 @@ static const struct amdgpu_ring_funcs sdma_v4_0_ring_funcs = { · 436 unmodified lines
16051611 .pad_ib = sdma_v4_0_ring_pad_ib,
16061612 .emit_wreg = sdma_v4_0_ring_emit_wreg,
16071613 .emit_reg_wait = sdma_v4_0_ring_emit_reg_wait,
1614+ .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper,
16081615 };
16091616
16101617 static void sdma_v4_0_set_ring_funcs(struct amdgpu_device *adev)
drivers/gpu/drm/amd/amdgpu/si.c+7−0
@@ -1252,6 +1252,12 @@ static void si_invalidate_hdp(struct amdgpu_device *adev, · 1251 unmodified lines
12521252 }
12531253 }
12541254
1255+static bool si_need_full_reset(struct amdgpu_device *adev)
1256+{
1257+ /* change this when we support soft reset */
1258+ return true;
1259+}
1260+
12551261 static int si_get_pcie_lanes(struct amdgpu_device *adev)
12561262 {
12571263 u32 link_width_cntl;
@@ -1332,6 +1338,7 @@ static const struct amdgpu_asic_funcs si_asic_funcs = · 74 unmodified lines
13321338 .get_config_memsize = &si_get_config_memsize,
13331339 .flush_hdp = &si_flush_hdp,
13341340 .invalidate_hdp = &si_invalidate_hdp,
1341+ .need_full_reset = &si_need_full_reset,
13351342 };
13361343
13371344 static uint32_t si_get_rev_id(struct amdgpu_device *adev)
drivers/gpu/drm/amd/amdgpu/si_dpm.c+1−1
@@ -7580,7 +7580,7 @@ static int si_dpm_late_init(void *handle) · 7579 unmodified lines
75807580 int ret;
75817581 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
75827582
7583− if (!amdgpu_dpm)
7583+ if (!adev->pm.dpm_enabled)
75847584 return 0;
75857585
75867586 ret = si_set_temperature_range(adev);
drivers/gpu/drm/amd/amdgpu/soc15.c+19−58
@@ -52,6 +52,7 @@ · 51 unmodified lines
5252 #include "gmc_v9_0.h"
5353 #include "gfxhub_v1_0.h"
5454 #include "mmhub_v1_0.h"
55+#include "df_v1_7.h"
5556 #include "vega10_ih.h"
5657 #include "sdma_v4_0.h"
5758 #include "uvd_v7_0.h"
@@ -60,33 +61,6 @@ · 2 unmodified lines
6061 #include "dce_virtual.h"
6162 #include "mxgpu_ai.h"
6263
63−#define mmFabricConfigAccessControl 0x0410
64−#define mmFabricConfigAccessControl_BASE_IDX 0
65−#define mmFabricConfigAccessControl_DEFAULT 0x00000000
66−//FabricConfigAccessControl
67−#define FabricConfigAccessControl__CfgRegInstAccEn__SHIFT 0x0
68−#define FabricConfigAccessControl__CfgRegInstAccRegLock__SHIFT 0x1
69−#define FabricConfigAccessControl__CfgRegInstID__SHIFT 0x10
70−#define FabricConfigAccessControl__CfgRegInstAccEn_MASK 0x00000001L
71−#define FabricConfigAccessControl__CfgRegInstAccRegLock_MASK 0x00000002L
72−#define FabricConfigAccessControl__CfgRegInstID_MASK 0x00FF0000L
73−
74−
75−#define mmDF_PIE_AON0_DfGlobalClkGater 0x00fc
76−#define mmDF_PIE_AON0_DfGlobalClkGater_BASE_IDX 0
77−//DF_PIE_AON0_DfGlobalClkGater
78−#define DF_PIE_AON0_DfGlobalClkGater__MGCGMode__SHIFT 0x0
79−#define DF_PIE_AON0_DfGlobalClkGater__MGCGMode_MASK 0x0000000FL
80−
81−enum {
82− DF_MGCG_DISABLE = 0,
83− DF_MGCG_ENABLE_00_CYCLE_DELAY =1,
84− DF_MGCG_ENABLE_01_CYCLE_DELAY =2,
85− DF_MGCG_ENABLE_15_CYCLE_DELAY =13,
86− DF_MGCG_ENABLE_31_CYCLE_DELAY =14,
87− DF_MGCG_ENABLE_63_CYCLE_DELAY =15
88−};
89−
9064 #define mmMP0_MISC_CGTT_CTRL0 0x01b9
9165 #define mmMP0_MISC_CGTT_CTRL0_BASE_IDX 0
9266 #define mmMP0_MISC_LIGHT_SLEEP_CTRL 0x01ba
@@ -313,6 +287,7 @@ static struct soc15_allowed_register_entry soc15_allowed_read_registers[] = { · 220 unmodified lines
313287 { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_STALLED_STAT1)},
314288 { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_STATUS)},
315289 { SOC15_REG_ENTRY(GC, 0, mmGB_ADDR_CONFIG)},
290+ { SOC15_REG_ENTRY(GC, 0, mmDB_DEBUG2)},
316291 };
317292
318293 static uint32_t soc15_read_indexed_register(struct amdgpu_device *adev, u32 se_num,
@@ -341,6 +316,8 @@ static uint32_t soc15_get_register_value(struct amdgpu_device *adev, · 22 unmodified lines
341316 } else {
342317 if (reg_offset == SOC15_REG_OFFSET(GC, 0, mmGB_ADDR_CONFIG))
343318 return adev->gfx.config.gb_addr_config;
319+ else if (reg_offset == SOC15_REG_OFFSET(GC, 0, mmDB_DEBUG2))
320+ return adev->gfx.config.db_debug2;
344321 return RREG32(reg_offset);
345322 }
346323 }
@@ -521,6 +498,7 @@ int soc15_set_ip_blocks(struct amdgpu_device *adev) · 174 unmodified lines
521498 else
522499 adev->nbio_funcs = &nbio_v6_1_funcs;
523500
501+ adev->df_funcs = &df_v1_7_funcs;
524502 adev->nbio_funcs->detect_hw_virt(adev);
525503
526504 if (amdgpu_sriov_vf(adev))
@@ -593,6 +571,12 @@ static void soc15_invalidate_hdp(struct amdgpu_device *adev, · 66 unmodified lines
593571 HDP, 0, mmHDP_READ_CACHE_INVALIDATE), 1);
594572 }
595573
574+static bool soc15_need_full_reset(struct amdgpu_device *adev)
575+{
576+ /* change this when we implement soft reset */
577+ return true;
578+}
579+
596580 static const struct amdgpu_asic_funcs soc15_asic_funcs =
597581 {
598582 .read_disabled_bios = &soc15_read_disabled_bios,
@@ -606,6 +590,7 @@ static const struct amdgpu_asic_funcs soc15_asic_funcs = · 7 unmodified lines
606590 .get_config_memsize = &soc15_get_config_memsize,
607591 .flush_hdp = &soc15_flush_hdp,
608592 .invalidate_hdp = &soc15_invalidate_hdp,
593+ .need_full_reset = &soc15_need_full_reset,
609594 };
610595
611596 static int soc15_common_early_init(void *handle)
@@ -697,6 +682,11 @@ static int soc15_common_early_init(void *handle) · 85 unmodified lines
697682 AMD_CG_SUPPORT_SDMA_LS;
698683 adev->pg_flags = AMD_PG_SUPPORT_SDMA;
699684
685+ if (adev->powerplay.pp_feature & PP_GFXOFF_MASK)
686+ adev->pg_flags |= AMD_PG_SUPPORT_GFX_PG |
687+ AMD_PG_SUPPORT_CP |
688+ AMD_PG_SUPPORT_RLC_SMU_HS;
689+
700690 adev->external_rev_id = 0x1;
701691 break;
702692 default:
@@ -871,32 +861,6 @@ static void soc15_update_rom_medium_grain_clock_gating(struct amdgpu_device *ade · 168 unmodified lines
871861 WREG32(SOC15_REG_OFFSET(SMUIO, 0, mmCGTT_ROM_CLK_CTRL0), data);
872862 }
873863
874−static void soc15_update_df_medium_grain_clock_gating(struct amdgpu_device *adev,
875− bool enable)
876−{
877− uint32_t data;
878−
879− /* Put DF on broadcast mode */
880− data = RREG32(SOC15_REG_OFFSET(DF, 0, mmFabricConfigAccessControl));
881− data &= ~FabricConfigAccessControl__CfgRegInstAccEn_MASK;
882− WREG32(SOC15_REG_OFFSET(DF, 0, mmFabricConfigAccessControl), data);
883−
884− if (enable && (adev->cg_flags & AMD_CG_SUPPORT_DF_MGCG)) {
885− data = RREG32(SOC15_REG_OFFSET(DF, 0, mmDF_PIE_AON0_DfGlobalClkGater));
886− data &= ~DF_PIE_AON0_DfGlobalClkGater__MGCGMode_MASK;
887− data |= DF_MGCG_ENABLE_15_CYCLE_DELAY;
888− WREG32(SOC15_REG_OFFSET(DF, 0, mmDF_PIE_AON0_DfGlobalClkGater), data);
889− } else {
890− data = RREG32(SOC15_REG_OFFSET(DF, 0, mmDF_PIE_AON0_DfGlobalClkGater));
891− data &= ~DF_PIE_AON0_DfGlobalClkGater__MGCGMode_MASK;
892− data |= DF_MGCG_DISABLE;
893− WREG32(SOC15_REG_OFFSET(DF, 0, mmDF_PIE_AON0_DfGlobalClkGater), data);
894− }
895−
896− WREG32(SOC15_REG_OFFSET(DF, 0, mmFabricConfigAccessControl),
897− mmFabricConfigAccessControl_DEFAULT);
898−}
899−
900864 static int soc15_common_set_clockgating_state(void *handle,
901865 enum amd_clockgating_state state)
902866 {
@@ -920,7 +884,7 @@ static int soc15_common_set_clockgating_state(void *handle, · 17 unmodified lines
920884 state == AMD_CG_STATE_GATE ? true : false);
921885 soc15_update_rom_medium_grain_clock_gating(adev,
922886 state == AMD_CG_STATE_GATE ? true : false);
923− soc15_update_df_medium_grain_clock_gating(adev,
887+ adev->df_funcs->update_medium_grain_clock_gating(adev,
924888 state == AMD_CG_STATE_GATE ? true : false);
925889 break;
926890 case CHIP_RAVEN:
@@ -973,10 +937,7 @@ static void soc15_common_get_clockgating_state(void *handle, u32 *flags) · 46 unmodified lines
973937 if (!(data & CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE0_MASK))
974938 *flags |= AMD_CG_SUPPORT_ROM_MGCG;
975939
976− /* AMD_CG_SUPPORT_DF_MGCG */
977− data = RREG32(SOC15_REG_OFFSET(DF, 0, mmDF_PIE_AON0_DfGlobalClkGater));
978− if (data & DF_MGCG_ENABLE_15_CYCLE_DELAY)
979− *flags |= AMD_CG_SUPPORT_DF_MGCG;
940+ adev->df_funcs->get_clockgating_state(adev, flags);
980941 }
981942
982943 static int soc15_common_set_powergating_state(void *handle,
drivers/gpu/drm/amd/amdgpu/soc15d.h+1−0
@@ -159,6 +159,7 @@ · 158 unmodified lines
159159 #define EOP_TC_WB_ACTION_EN (1 << 15) /* L2 */
160160 #define EOP_TCL1_ACTION_EN (1 << 16)
161161 #define EOP_TC_ACTION_EN (1 << 17) /* L2 */
162+#define EOP_TC_NC_ACTION_EN (1 << 19)
162163 #define EOP_TC_MD_ACTION_EN (1 << 21) /* L2 metadata */
163164
164165 #define DATA_SEL(x) ((x) << 29)
drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c+2−2
@@ -688,7 +688,7 @@ static int uvd_v4_2_set_powergating_state(void *handle, · 687 unmodified lines
688688
689689 if (state == AMD_PG_STATE_GATE) {
690690 uvd_v4_2_stop(adev);
691− if (adev->pg_flags & AMD_PG_SUPPORT_UVD && amdgpu_dpm == 0) {
691+ if (adev->pg_flags & AMD_PG_SUPPORT_UVD && !adev->pm.dpm_enabled) {
692692 if (!(RREG32_SMC(ixCURRENT_PG_STATUS) &
693693 CURRENT_PG_STATUS__UVD_PG_STATUS_MASK)) {
694694 WREG32(mmUVD_PGFSM_CONFIG, (UVD_PGFSM_CONFIG__UVD_PGFSM_FSM_ADDR_MASK |
@@ -699,7 +699,7 @@ static int uvd_v4_2_set_powergating_state(void *handle, · 4 unmodified lines
699699 }
700700 return 0;
701701 } else {
702− if (adev->pg_flags & AMD_PG_SUPPORT_UVD && amdgpu_dpm == 0) {
702+ if (adev->pg_flags & AMD_PG_SUPPORT_UVD && !adev->pm.dpm_enabled) {
703703 if (RREG32_SMC(ixCURRENT_PG_STATUS) &
704704 CURRENT_PG_STATUS__UVD_PG_STATUS_MASK) {
705705 WREG32(mmUVD_PGFSM_CONFIG, (UVD_PGFSM_CONFIG__UVD_PGFSM_FSM_ADDR_MASK |
drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c+16−4
@@ -62,7 +62,7 @@ static void uvd_v6_0_enable_mgcg(struct amdgpu_device *adev, · 61 unmodified lines
6262 static inline bool uvd_v6_0_enc_support(struct amdgpu_device *adev)
6363 {
6464 return ((adev->asic_type >= CHIP_POLARIS10) &&
65− (adev->asic_type <= CHIP_POLARIS12) &&
65+ (adev->asic_type <= CHIP_VEGAM) &&
6666 (!adev->uvd.fw_version || adev->uvd.fw_version >= FW_1_130_16));
6767 }
6868
@@ -429,7 +429,7 @@ static int uvd_v6_0_sw_init(void *handle) · 360 unmodified lines
429429 ring = &adev->uvd.ring_enc[0];
430430 rq = &ring->sched.sched_rq[DRM_SCHED_PRIORITY_NORMAL];
431431 r = drm_sched_entity_init(&ring->sched, &adev->uvd.entity_enc,
432− rq, amdgpu_sched_jobs, NULL);
432+ rq, NULL);
433433 if (r) {
434434 DRM_ERROR("Failed setting up UVD ENC run queue.\n");
435435 return r;
@@ -963,6 +963,16 @@ static void uvd_v6_0_enc_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, · 527 unmodified lines
963963 amdgpu_ring_write(ring, HEVC_ENC_CMD_TRAP);
964964 }
965965
966+/**
967+ * uvd_v6_0_ring_emit_hdp_flush - skip HDP flushing
968+ *
969+ * @ring: amdgpu_ring pointer
970+ */
971+static void uvd_v6_0_ring_emit_hdp_flush(struct amdgpu_ring *ring)
972+{
973+ /* The firmware doesn't seem to like touching registers at this point. */
974+}
975+
966976 /**
967977 * uvd_v6_0_ring_test_ring - register write test
968978 *
@@ -1528,12 +1538,13 @@ static const struct amdgpu_ring_funcs uvd_v6_0_ring_phys_funcs = { · 559 unmodified lines
15281538 .set_wptr = uvd_v6_0_ring_set_wptr,
15291539 .parse_cs = amdgpu_uvd_ring_parse_cs,
15301540 .emit_frame_size =
1531− 6 + 6 + /* hdp flush / invalidate */
1541+ 6 + /* hdp invalidate */
15321542 10 + /* uvd_v6_0_ring_emit_pipeline_sync */
15331543 14, /* uvd_v6_0_ring_emit_fence x1 no user fence */
15341544 .emit_ib_size = 8, /* uvd_v6_0_ring_emit_ib */
15351545 .emit_ib = uvd_v6_0_ring_emit_ib,
15361546 .emit_fence = uvd_v6_0_ring_emit_fence,
1547+ .emit_hdp_flush = uvd_v6_0_ring_emit_hdp_flush,
15371548 .test_ring = uvd_v6_0_ring_test_ring,
15381549 .test_ib = amdgpu_uvd_ring_test_ib,
15391550 .insert_nop = amdgpu_ring_insert_nop,
@@ -1552,7 +1563,7 @@ static const struct amdgpu_ring_funcs uvd_v6_0_ring_vm_funcs = { · 12 unmodified lines
15521563 .get_wptr = uvd_v6_0_ring_get_wptr,
15531564 .set_wptr = uvd_v6_0_ring_set_wptr,
15541565 .emit_frame_size =
1555− 6 + 6 + /* hdp flush / invalidate */
1566+ 6 + /* hdp invalidate */
15561567 10 + /* uvd_v6_0_ring_emit_pipeline_sync */
15571568 VI_FLUSH_GPU_TLB_NUM_WREG * 6 + 8 + /* uvd_v6_0_ring_emit_vm_flush */
15581569 14 + 14, /* uvd_v6_0_ring_emit_fence x2 vm fence */
@@ -1561,6 +1572,7 @@ static const struct amdgpu_ring_funcs uvd_v6_0_ring_vm_funcs = { · 2 unmodified lines
15611572 .emit_fence = uvd_v6_0_ring_emit_fence,
15621573 .emit_vm_flush = uvd_v6_0_ring_emit_vm_flush,
15631574 .emit_pipeline_sync = uvd_v6_0_ring_emit_pipeline_sync,
1575+ .emit_hdp_flush = uvd_v6_0_ring_emit_hdp_flush,
15641576 .test_ring = uvd_v6_0_ring_test_ring,
15651577 .test_ib = amdgpu_uvd_ring_test_ib,
15661578 .insert_nop = amdgpu_ring_insert_nop,
drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c+15−2
@@ -418,7 +418,7 @@ static int uvd_v7_0_sw_init(void *handle) · 417 unmodified lines
418418 ring = &adev->uvd.ring_enc[0];
419419 rq = &ring->sched.sched_rq[DRM_SCHED_PRIORITY_NORMAL];
420420 r = drm_sched_entity_init(&ring->sched, &adev->uvd.entity_enc,
421− rq, amdgpu_sched_jobs, NULL);
421+ rq, NULL);
422422 if (r) {
423423 DRM_ERROR("Failed setting up UVD ENC run queue.\n");
424424 return r;
@@ -1135,6 +1135,16 @@ static void uvd_v7_0_enc_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, · 710 unmodified lines
11351135 amdgpu_ring_write(ring, HEVC_ENC_CMD_TRAP);
11361136 }
11371137
1138+/**
1139+ * uvd_v7_0_ring_emit_hdp_flush - skip HDP flushing
1140+ *
1141+ * @ring: amdgpu_ring pointer
1142+ */
1143+static void uvd_v7_0_ring_emit_hdp_flush(struct amdgpu_ring *ring)
1144+{
1145+ /* The firmware doesn't seem to like touching registers at this point. */
1146+}
1147+
11381148 /**
11391149 * uvd_v7_0_ring_test_ring - register write test
11401150 *
@@ -1654,7 +1664,7 @@ static const struct amdgpu_ring_funcs uvd_v7_0_ring_vm_funcs = { · 513 unmodified lines
16541664 .get_wptr = uvd_v7_0_ring_get_wptr,
16551665 .set_wptr = uvd_v7_0_ring_set_wptr,
16561666 .emit_frame_size =
1657− 6 + 6 + /* hdp flush / invalidate */
1667+ 6 + /* hdp invalidate */
16581668 SOC15_FLUSH_GPU_TLB_NUM_WREG * 6 +
16591669 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 8 +
16601670 8 + /* uvd_v7_0_ring_emit_vm_flush */
@@ -1663,6 +1673,7 @@ static const struct amdgpu_ring_funcs uvd_v7_0_ring_vm_funcs = { · 2 unmodified lines
16631673 .emit_ib = uvd_v7_0_ring_emit_ib,
16641674 .emit_fence = uvd_v7_0_ring_emit_fence,
16651675 .emit_vm_flush = uvd_v7_0_ring_emit_vm_flush,
1676+ .emit_hdp_flush = uvd_v7_0_ring_emit_hdp_flush,
16661677 .test_ring = uvd_v7_0_ring_test_ring,
16671678 .test_ib = amdgpu_uvd_ring_test_ib,
16681679 .insert_nop = uvd_v7_0_ring_insert_nop,
@@ -1671,6 +1682,7 @@ static const struct amdgpu_ring_funcs uvd_v7_0_ring_vm_funcs = { · 2 unmodified lines
16711682 .end_use = amdgpu_uvd_ring_end_use,
16721683 .emit_wreg = uvd_v7_0_ring_emit_wreg,
16731684 .emit_reg_wait = uvd_v7_0_ring_emit_reg_wait,
1685+ .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper,
16741686 };
16751687
16761688 static const struct amdgpu_ring_funcs uvd_v7_0_enc_ring_vm_funcs = {
@@ -1702,6 +1714,7 @@ static const struct amdgpu_ring_funcs uvd_v7_0_enc_ring_vm_funcs = { · 25 unmodified lines
17021714 .end_use = amdgpu_uvd_ring_end_use,
17031715 .emit_wreg = uvd_v7_0_enc_ring_emit_wreg,
17041716 .emit_reg_wait = uvd_v7_0_enc_ring_emit_reg_wait,
1717+ .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper,
17051718 };
17061719
17071720 static void uvd_v7_0_set_ring_funcs(struct amdgpu_device *adev)
drivers/gpu/drm/amd/amdgpu/vce_v3_0.c+4−3
@@ -388,7 +388,8 @@ static unsigned vce_v3_0_get_harvest_config(struct amdgpu_device *adev) · 387 unmodified lines
388388 default:
389389 if ((adev->asic_type == CHIP_POLARIS10) ||
390390 (adev->asic_type == CHIP_POLARIS11) ||
391− (adev->asic_type == CHIP_POLARIS12))
391+ (adev->asic_type == CHIP_POLARIS12) ||
392+ (adev->asic_type == CHIP_VEGAM))
392393 return AMDGPU_VCE_HARVEST_VCE1;
393394
394395 return 0;
@@ -467,8 +468,8 @@ static int vce_v3_0_hw_init(void *handle) · 72 unmodified lines
467468 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
468469
469470 vce_v3_0_override_vce_clock_gating(adev, true);
470− if (!(adev->flags & AMD_IS_APU))
471− amdgpu_asic_set_vce_clocks(adev, 10000, 10000);
471+
472+ amdgpu_asic_set_vce_clocks(adev, 10000, 10000);
472473
473474 for (i = 0; i < adev->vce.num_rings; i++)
474475 adev->vce.ring[i].ready = false;
drivers/gpu/drm/amd/amdgpu/vce_v4_0.c+1−0
@@ -1081,6 +1081,7 @@ static const struct amdgpu_ring_funcs vce_v4_0_ring_vm_funcs = { · 1080 unmodified lines
10811081 .end_use = amdgpu_vce_ring_end_use,
10821082 .emit_wreg = vce_v4_0_emit_wreg,
10831083 .emit_reg_wait = vce_v4_0_emit_reg_wait,
1084+ .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper,
10841085 };
10851086
10861087 static void vce_v4_0_set_ring_funcs(struct amdgpu_device *adev)
drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c+2−0
@@ -1109,6 +1109,7 @@ static const struct amdgpu_ring_funcs vcn_v1_0_dec_ring_vm_funcs = { · 1108 unmodified lines
11091109 .end_use = amdgpu_vcn_ring_end_use,
11101110 .emit_wreg = vcn_v1_0_dec_ring_emit_wreg,
11111111 .emit_reg_wait = vcn_v1_0_dec_ring_emit_reg_wait,
1112+ .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper,
11121113 };
11131114
11141115 static const struct amdgpu_ring_funcs vcn_v1_0_enc_ring_vm_funcs = {
@@ -1139,6 +1140,7 @@ static const struct amdgpu_ring_funcs vcn_v1_0_enc_ring_vm_funcs = { · 24 unmodified lines
11391140 .end_use = amdgpu_vcn_ring_end_use,
11401141 .emit_wreg = vcn_v1_0_enc_ring_emit_wreg,
11411142 .emit_reg_wait = vcn_v1_0_enc_ring_emit_reg_wait,
1143+ .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper,
11421144 };
11431145
11441146 static void vcn_v1_0_set_dec_ring_funcs(struct amdgpu_device *adev)
drivers/gpu/drm/amd/amdgpu/vi.c+111−19
@@ -305,9 +305,10 @@ static void vi_init_golden_registers(struct amdgpu_device *adev) · 304 unmodified lines
305305 stoney_mgcg_cgcg_init,
306306 ARRAY_SIZE(stoney_mgcg_cgcg_init));
307307 break;
308− case CHIP_POLARIS11:
309308 case CHIP_POLARIS10:
309+ case CHIP_POLARIS11:
310310 case CHIP_POLARIS12:
311+ case CHIP_VEGAM:
311312 default:
312313 break;
313314 }
@@ -728,33 +729,59 @@ static int vi_set_uvd_clock(struct amdgpu_device *adev, u32 clock, · 414 unmodified lines
728729 return r;
729730
730731 tmp = RREG32_SMC(cntl_reg);
731− tmp &= ~(CG_DCLK_CNTL__DCLK_DIR_CNTL_EN_MASK |
732− CG_DCLK_CNTL__DCLK_DIVIDER_MASK);
732+
733+ if (adev->flags & AMD_IS_APU)
734+ tmp &= ~CG_DCLK_CNTL__DCLK_DIVIDER_MASK;
735+ else
736+ tmp &= ~(CG_DCLK_CNTL__DCLK_DIR_CNTL_EN_MASK |
737+ CG_DCLK_CNTL__DCLK_DIVIDER_MASK);
733738 tmp |= dividers.post_divider;
734739 WREG32_SMC(cntl_reg, tmp);
735740
736741 for (i = 0; i < 100; i++) {
737− if (RREG32_SMC(status_reg) & CG_DCLK_STATUS__DCLK_STATUS_MASK)
738− break;
742+ tmp = RREG32_SMC(status_reg);
743+ if (adev->flags & AMD_IS_APU) {
744+ if (tmp & 0x10000)
745+ break;
746+ } else {
747+ if (tmp & CG_DCLK_STATUS__DCLK_STATUS_MASK)
748+ break;
749+ }
739750 mdelay(10);
740751 }
741752 if (i == 100)
742753 return -ETIMEDOUT;
743−
744754 return 0;
745755 }
746756
757+#define ixGNB_CLK1_DFS_CNTL 0xD82200F0
758+#define ixGNB_CLK1_STATUS 0xD822010C
759+#define ixGNB_CLK2_DFS_CNTL 0xD8220110
760+#define ixGNB_CLK2_STATUS 0xD822012C
761+#define ixGNB_CLK3_DFS_CNTL 0xD8220130
762+#define ixGNB_CLK3_STATUS 0xD822014C
763+
747764 static int vi_set_uvd_clocks(struct amdgpu_device *adev, u32 vclk, u32 dclk)
748765 {
749766 int r;
750767
751− r = vi_set_uvd_clock(adev, vclk, ixCG_VCLK_CNTL, ixCG_VCLK_STATUS);
752− if (r)
753− return r;
768+ if (adev->flags & AMD_IS_APU) {
769+ r = vi_set_uvd_clock(adev, vclk, ixGNB_CLK2_DFS_CNTL, ixGNB_CLK2_STATUS);
770+ if (r)
771+ return r;
754772
755− r = vi_set_uvd_clock(adev, dclk, ixCG_DCLK_CNTL, ixCG_DCLK_STATUS);
756− if (r)
757− return r;
773+ r = vi_set_uvd_clock(adev, dclk, ixGNB_CLK1_DFS_CNTL, ixGNB_CLK1_STATUS);
774+ if (r)
775+ return r;
776+ } else {
777+ r = vi_set_uvd_clock(adev, vclk, ixCG_VCLK_CNTL, ixCG_VCLK_STATUS);
778+ if (r)
779+ return r;
780+
781+ r = vi_set_uvd_clock(adev, dclk, ixCG_DCLK_CNTL, ixCG_DCLK_STATUS);
782+ if (r)
783+ return r;
784+ }
758785
759786 return 0;
760787 }
@@ -764,6 +791,22 @@ static int vi_set_vce_clocks(struct amdgpu_device *adev, u32 evclk, u32 ecclk) · 3 unmodified lines
764791 int r, i;
765792 struct atom_clock_dividers dividers;
766793 u32 tmp;
794+ u32 reg_ctrl;
795+ u32 reg_status;
796+ u32 status_mask;
797+ u32 reg_mask;
798+
799+ if (adev->flags & AMD_IS_APU) {
800+ reg_ctrl = ixGNB_CLK3_DFS_CNTL;
801+ reg_status = ixGNB_CLK3_STATUS;
802+ status_mask = 0x00010000;
803+ reg_mask = CG_ECLK_CNTL__ECLK_DIVIDER_MASK;
804+ } else {
805+ reg_ctrl = ixCG_ECLK_CNTL;
806+ reg_status = ixCG_ECLK_STATUS;
807+ status_mask = CG_ECLK_STATUS__ECLK_STATUS_MASK;
808+ reg_mask = CG_ECLK_CNTL__ECLK_DIR_CNTL_EN_MASK | CG_ECLK_CNTL__ECLK_DIVIDER_MASK;
809+ }
767810
768811 r = amdgpu_atombios_get_clock_dividers(adev,
769812 COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK,
@@ -772,24 +815,25 @@ static int vi_set_vce_clocks(struct amdgpu_device *adev, u32 evclk, u32 ecclk) · 2 unmodified lines
772815 return r;
773816
774817 for (i = 0; i < 100; i++) {
775− if (RREG32_SMC(ixCG_ECLK_STATUS) & CG_ECLK_STATUS__ECLK_STATUS_MASK)
818+ if (RREG32_SMC(reg_status) & status_mask)
776819 break;
777820 mdelay(10);
778821 }
822+
779823 if (i == 100)
780824 return -ETIMEDOUT;
781825
782− tmp = RREG32_SMC(ixCG_ECLK_CNTL);
783− tmp &= ~(CG_ECLK_CNTL__ECLK_DIR_CNTL_EN_MASK |
784− CG_ECLK_CNTL__ECLK_DIVIDER_MASK);
826+ tmp = RREG32_SMC(reg_ctrl);
827+ tmp &= ~reg_mask;
785828 tmp |= dividers.post_divider;
786− WREG32_SMC(ixCG_ECLK_CNTL, tmp);
829+ WREG32_SMC(reg_ctrl, tmp);
787830
788831 for (i = 0; i < 100; i++) {
789− if (RREG32_SMC(ixCG_ECLK_STATUS) & CG_ECLK_STATUS__ECLK_STATUS_MASK)
832+ if (RREG32_SMC(reg_status) & status_mask)
790833 break;
791834 mdelay(10);
792835 }
836+
793837 if (i == 100)
794838 return -ETIMEDOUT;
795839
@@ -876,6 +920,27 @@ static void vi_invalidate_hdp(struct amdgpu_device *adev, · 80 unmodified lines
876920 }
877921 }
878922
923+static bool vi_need_full_reset(struct amdgpu_device *adev)
924+{
925+ switch (adev->asic_type) {
926+ case CHIP_CARRIZO:
927+ case CHIP_STONEY:
928+ /* CZ has hang issues with full reset at the moment */
929+ return false;
930+ case CHIP_FIJI:
931+ case CHIP_TONGA:
932+ /* XXX: soft reset should work on fiji and tonga */
933+ return true;
934+ case CHIP_POLARIS10:
935+ case CHIP_POLARIS11:
936+ case CHIP_POLARIS12:
937+ case CHIP_TOPAZ:
938+ default:
939+ /* change this when we support soft reset */
940+ return true;
941+ }
942+}
943+
879944 static const struct amdgpu_asic_funcs vi_asic_funcs =
880945 {
881946 .read_disabled_bios = &vi_read_disabled_bios,
@@ -889,6 +954,7 @@ static const struct amdgpu_asic_funcs vi_asic_funcs = · 7 unmodified lines
889954 .get_config_memsize = &vi_get_config_memsize,
890955 .flush_hdp = &vi_flush_hdp,
891956 .invalidate_hdp = &vi_invalidate_hdp,
957+ .need_full_reset = &vi_need_full_reset,
892958 };
893959
894960 #define CZ_REV_BRISTOL(rev) \
@@ -1031,6 +1097,30 @@ static int vi_common_early_init(void *handle) · 136 unmodified lines
10311097 adev->pg_flags = 0;
10321098 adev->external_rev_id = adev->rev_id + 0x64;
10331099 break;
1100+ case CHIP_VEGAM:
1101+ adev->cg_flags = 0;
1102+ /*AMD_CG_SUPPORT_GFX_MGCG |
1103+ AMD_CG_SUPPORT_GFX_RLC_LS |
1104+ AMD_CG_SUPPORT_GFX_CP_LS |
1105+ AMD_CG_SUPPORT_GFX_CGCG |
1106+ AMD_CG_SUPPORT_GFX_CGLS |
1107+ AMD_CG_SUPPORT_GFX_3D_CGCG |
1108+ AMD_CG_SUPPORT_GFX_3D_CGLS |
1109+ AMD_CG_SUPPORT_SDMA_MGCG |
1110+ AMD_CG_SUPPORT_SDMA_LS |
1111+ AMD_CG_SUPPORT_BIF_MGCG |
1112+ AMD_CG_SUPPORT_BIF_LS |
1113+ AMD_CG_SUPPORT_HDP_MGCG |
1114+ AMD_CG_SUPPORT_HDP_LS |
1115+ AMD_CG_SUPPORT_ROM_MGCG |
1116+ AMD_CG_SUPPORT_MC_MGCG |
1117+ AMD_CG_SUPPORT_MC_LS |
1118+ AMD_CG_SUPPORT_DRM_LS |
1119+ AMD_CG_SUPPORT_UVD_MGCG |
1120+ AMD_CG_SUPPORT_VCE_MGCG;*/
1121+ adev->pg_flags = 0;
1122+ adev->external_rev_id = adev->rev_id + 0x6E;
1123+ break;
10341124 case CHIP_CARRIZO:
10351125 adev->cg_flags = AMD_CG_SUPPORT_UVD_MGCG |
10361126 AMD_CG_SUPPORT_GFX_MGCG |
@@ -1422,6 +1512,7 @@ static int vi_common_set_clockgating_state(void *handle, · 385 unmodified lines
14221512 case CHIP_POLARIS10:
14231513 case CHIP_POLARIS11:
14241514 case CHIP_POLARIS12:
1515+ case CHIP_VEGAM:
14251516 vi_common_set_clockgating_state_by_smu(adev, state);
14261517 default:
14271518 break;
@@ -1551,9 +1642,10 @@ int vi_set_ip_blocks(struct amdgpu_device *adev) · 123 unmodified lines
15511642 amdgpu_device_ip_block_add(adev, &vce_v3_0_ip_block);
15521643 }
15531644 break;
1554− case CHIP_POLARIS11:
15551645 case CHIP_POLARIS10:
1646+ case CHIP_POLARIS11:
15561647 case CHIP_POLARIS12:
1648+ case CHIP_VEGAM:
15571649 amdgpu_device_ip_block_add(adev, &vi_common_ip_block);
15581650 amdgpu_device_ip_block_add(adev, &gmc_v8_1_ip_block);
15591651 amdgpu_device_ip_block_add(adev, &tonga_ih_ip_block);
drivers/gpu/drm/amd/display/Kconfig+6−8
@@ -9,14 +9,6 @@ config DRM_AMD_DC · 8 unmodified lines
99 support for AMDGPU. This adds required support for Vega and
1010 Raven ASICs.
1111
12−config DRM_AMD_DC_PRE_VEGA
13− bool "DC support for Polaris and older ASICs"
14− default y
15− help
16− Choose this option to enable the new DC support for older asics
17− by default. This includes Polaris, Carrizo, Tonga, Bonaire,
18− and Hawaii.
19−
2012 config DRM_AMD_DC_FBC
2113 bool "AMD FBC - Enable Frame Buffer Compression"
2214 depends on DRM_AMD_DC
@@ -42,4 +34,10 @@ config DEBUG_KERNEL_DC · 19 unmodified lines
4234 if you want to hit
4335 kdgb_break in assert.
4436
37+config DRM_AMD_DC_VEGAM
38+ bool "VEGAM support"
39+ depends on DRM_AMD_DC
40+ help
41+ Choose this option if you want to have
42+ VEGAM support for display engine
4543 endmenu
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c+153−72
@@ -433,11 +433,6 @@ static int amdgpu_dm_init(struct amdgpu_device *adev) · 432 unmodified lines
433433
434434 init_data.dce_environment = DCE_ENV_PRODUCTION_DRV;
435435
436− if (amdgpu_dc_log)
437− init_data.log_mask = DC_DEFAULT_LOG_MASK;
438− else
439− init_data.log_mask = DC_MIN_LOG_MASK;
440−
441436 /*
442437 * TODO debug why this doesn't work on Raven
443438 */
@@ -649,18 +644,6 @@ amdgpu_dm_find_first_crtc_matching_connector(struct drm_atomic_state *state, · 205 unmodified lines
649644 static int dm_resume(void *handle)
650645 {
651646 struct amdgpu_device *adev = handle;
652− struct amdgpu_display_manager *dm = &adev->dm;
653− int ret = 0;
654−
655− /* power on hardware */
656− dc_set_power_state(dm->dc, DC_ACPI_CM_POWER_STATE_D0);
657−
658− ret = amdgpu_dm_display_resume(adev);
659− return ret;
660−}
661−
662−int amdgpu_dm_display_resume(struct amdgpu_device *adev)
663−{
664647 struct drm_device *ddev = adev->ddev;
665648 struct amdgpu_display_manager *dm = &adev->dm;
666649 struct amdgpu_dm_connector *aconnector;
@@ -671,10 +654,12 @@ int amdgpu_dm_display_resume(struct amdgpu_device *adev) · 4 unmodified lines
671654 struct drm_plane *plane;
672655 struct drm_plane_state *new_plane_state;
673656 struct dm_plane_state *dm_new_plane_state;
674−
675− int ret = 0;
657+ int ret;
676658 int i;
677659
660+ /* power on hardware */
661+ dc_set_power_state(dm->dc, DC_ACPI_CM_POWER_STATE_D0);
662+
678663 /* program HPD filter */
679664 dc_resume(dm->dc);
680665
@@ -688,8 +673,7 @@ int amdgpu_dm_display_resume(struct amdgpu_device *adev) · 7 unmodified lines
688673 amdgpu_dm_irq_resume_early(adev);
689674
690675 /* Do detection*/
691− list_for_each_entry(connector,
692− &ddev->mode_config.connector_list, head) {
676+ list_for_each_entry(connector, &ddev->mode_config.connector_list, head) {
693677 aconnector = to_amdgpu_dm_connector(connector);
694678
695679 /*
@@ -711,7 +695,7 @@ int amdgpu_dm_display_resume(struct amdgpu_device *adev) · 15 unmodified lines
711695 }
712696
713697 /* Force mode set in atomic comit */
714− for_each_new_crtc_in_state(adev->dm.cached_state, crtc, new_crtc_state, i)
698+ for_each_new_crtc_in_state(dm->cached_state, crtc, new_crtc_state, i)
715699 new_crtc_state->active_changed = true;
716700
717701 /*
@@ -719,7 +703,7 @@ int amdgpu_dm_display_resume(struct amdgpu_device *adev) · 1 unmodified line
719703 * them here, since they were duplicated as part of the suspend
720704 * procedure.
721705 */
722− for_each_new_crtc_in_state(adev->dm.cached_state, crtc, new_crtc_state, i) {
706+ for_each_new_crtc_in_state(dm->cached_state, crtc, new_crtc_state, i) {
723707 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
724708 if (dm_new_crtc_state->stream) {
725709 WARN_ON(kref_read(&dm_new_crtc_state->stream->refcount) > 1);
@@ -728,7 +712,7 @@ int amdgpu_dm_display_resume(struct amdgpu_device *adev) · 2 unmodified lines
728712 }
729713 }
730714
731− for_each_new_plane_in_state(adev->dm.cached_state, plane, new_plane_state, i) {
715+ for_each_new_plane_in_state(dm->cached_state, plane, new_plane_state, i) {
732716 dm_new_plane_state = to_dm_plane_state(new_plane_state);
733717 if (dm_new_plane_state->dc_state) {
734718 WARN_ON(kref_read(&dm_new_plane_state->dc_state->refcount) > 1);
@@ -737,9 +721,9 @@ int amdgpu_dm_display_resume(struct amdgpu_device *adev) · 2 unmodified lines
737721 }
738722 }
739723
740− ret = drm_atomic_helper_resume(ddev, adev->dm.cached_state);
724+ ret = drm_atomic_helper_resume(ddev, dm->cached_state);
741725
742− adev->dm.cached_state = NULL;
726+ dm->cached_state = NULL;
743727
744728 amdgpu_dm_irq_resume_late(adev);
745729
@@ -1529,6 +1513,9 @@ static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev) · 783 unmodified lines
15291513 case CHIP_POLARIS11:
15301514 case CHIP_POLARIS10:
15311515 case CHIP_POLARIS12:
1516+#if defined(CONFIG_DRM_AMD_DC_VEGAM)
1517+ case CHIP_VEGAM:
1518+#endif
15321519 case CHIP_VEGA10:
15331520 case CHIP_VEGA12:
15341521 if (dce110_register_irq_handlers(dm->adev)) {
@@ -1549,7 +1536,7 @@ static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev) · 14 unmodified lines
15491536 break;
15501537 #endif
15511538 default:
1552− DRM_ERROR("Usupported ASIC type: 0x%X\n", adev->asic_type);
1539+ DRM_ERROR("Unsupported ASIC type: 0x%X\n", adev->asic_type);
15531540 goto fail;
15541541 }
15551542
@@ -1657,7 +1644,6 @@ static ssize_t s3_debug_store(struct device *device, · 101 unmodified lines
16571644 if (ret == 0) {
16581645 if (s3_state) {
16591646 dm_resume(adev);
1660− amdgpu_dm_display_resume(adev);
16611647 drm_kms_helper_hotplug_event(adev->ddev);
16621648 } else
16631649 dm_suspend(adev);
@@ -1722,6 +1708,9 @@ static int dm_early_init(void *handle) · 58 unmodified lines
17221708 adev->mode_info.plane_type = dm_plane_type_default;
17231709 break;
17241710 case CHIP_POLARIS10:
1711+#if defined(CONFIG_DRM_AMD_DC_VEGAM)
1712+ case CHIP_VEGAM:
1713+#endif
17251714 adev->mode_info.num_crtc = 6;
17261715 adev->mode_info.num_hpd = 6;
17271716 adev->mode_info.num_dig = 6;
@@ -1743,7 +1732,7 @@ static int dm_early_init(void *handle) · 15 unmodified lines
17431732 break;
17441733 #endif
17451734 default:
1746− DRM_ERROR("Usupported ASIC type: 0x%X\n", adev->asic_type);
1735+ DRM_ERROR("Unsupported ASIC type: 0x%X\n", adev->asic_type);
17471736 return -EINVAL;
17481737 }
17491738
@@ -1848,7 +1837,7 @@ static bool fill_rects_from_plane_state(const struct drm_plane_state *state, · 98 unmodified lines
18481837 static int get_fb_info(const struct amdgpu_framebuffer *amdgpu_fb,
18491838 uint64_t *tiling_flags)
18501839 {
1851− struct amdgpu_bo *rbo = gem_to_amdgpu_bo(amdgpu_fb->obj);
1840+ struct amdgpu_bo *rbo = gem_to_amdgpu_bo(amdgpu_fb->base.obj[0]);
18521841 int r = amdgpu_bo_reserve(rbo, false);
18531842
18541843 if (unlikely(r)) {
@@ -2017,7 +2006,6 @@ static int fill_plane_attributes(struct amdgpu_device *adev, · 162 unmodified lines
20172006 const struct amdgpu_framebuffer *amdgpu_fb =
20182007 to_amdgpu_framebuffer(plane_state->fb);
20192008 const struct drm_crtc *crtc = plane_state->crtc;
2020− struct dc_transfer_func *input_tf;
20212009 int ret = 0;
20222010
20232011 if (!fill_rects_from_plane_state(plane_state, dc_plane_state))
@@ -2031,13 +2019,6 @@ static int fill_plane_attributes(struct amdgpu_device *adev, · 7 unmodified lines
20312019 if (ret)
20322020 return ret;
20332021
2034− input_tf = dc_create_transfer_func();
2035−
2036− if (input_tf == NULL)
2037− return -ENOMEM;
2038−
2039− dc_plane_state->in_transfer_func = input_tf;
2040−
20412022 /*
20422023 * Always set input transfer function, since plane state is refreshed
20432024 * every time.
@@ -2206,7 +2187,6 @@ fill_stream_properties_from_drm_display_mode(struct dc_stream_state *stream, · 162 unmodified lines
22062187 const struct drm_connector *connector)
22072188 {
22082189 struct dc_crtc_timing *timing_out = &stream->timing;
2209− struct dc_transfer_func *tf = dc_create_transfer_func();
22102190
22112191 memset(timing_out, 0, sizeof(struct dc_crtc_timing));
22122192
@@ -2250,9 +2230,8 @@ fill_stream_properties_from_drm_display_mode(struct dc_stream_state *stream, · 37 unmodified lines
22502230
22512231 stream->output_color_space = get_output_color_space(timing_out);
22522232
2253− tf->type = TF_TYPE_PREDEFINED;
2254− tf->tf = TRANSFER_FUNCTION_SRGB;
2255− stream->out_transfer_func = tf;
2233+ stream->out_transfer_func->type = TF_TYPE_PREDEFINED;
2234+ stream->out_transfer_func->tf = TRANSFER_FUNCTION_SRGB;
22562235 }
22572236
22582237 static void fill_audio_info(struct audio_info *audio_info,
@@ -2488,6 +2467,9 @@ create_stream_for_sink(struct amdgpu_dm_connector *aconnector, · 229 unmodified lines
24882467
24892468 update_stream_signal(stream);
24902469
2470+ if (dm_state && dm_state->freesync_capable)
2471+ stream->ignore_msa_timing_param = true;
2472+
24912473 return stream;
24922474 }
24932475
@@ -2710,18 +2692,15 @@ static void amdgpu_dm_connector_destroy(struct drm_connector *connector) · 216 unmodified lines
27102692 const struct dc_link *link = aconnector->dc_link;
27112693 struct amdgpu_device *adev = connector->dev->dev_private;
27122694 struct amdgpu_display_manager *dm = &adev->dm;
2695+
27132696 #if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) ||\
27142697 defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE)
27152698
27162699 if ((link->connector_signal & (SIGNAL_TYPE_EDP | SIGNAL_TYPE_LVDS)) &&
2717− link->type != dc_connection_none) {
2718− amdgpu_dm_register_backlight_device(dm);
2719−
2720− if (dm->backlight_dev) {
2721− backlight_device_unregister(dm->backlight_dev);
2722− dm->backlight_dev = NULL;
2723− }
2724−
2700+ link->type != dc_connection_none &&
2701+ dm->backlight_dev) {
2702+ backlight_device_unregister(dm->backlight_dev);
2703+ dm->backlight_dev = NULL;
27252704 }
27262705 #endif
27272706 drm_connector_unregister(connector);
@@ -2855,7 +2834,7 @@ static void handle_edid_mgmt(struct amdgpu_dm_connector *aconnector) · 127 unmodified lines
28552834 create_eml_sink(aconnector);
28562835 }
28572836
2858−int amdgpu_dm_connector_mode_valid(struct drm_connector *connector,
2837+enum drm_mode_status amdgpu_dm_connector_mode_valid(struct drm_connector *connector,
28592838 struct drm_display_mode *mode)
28602839 {
28612840 int result = MODE_ERROR;
@@ -3058,8 +3037,7 @@ static int dm_plane_helper_prepare_fb(struct drm_plane *plane, · 196 unmodified lines
30583037 }
30593038
30603039 afb = to_amdgpu_framebuffer(new_state->fb);
3061−
3062− obj = afb->obj;
3040+ obj = new_state->fb->obj[0];
30633041 rbo = gem_to_amdgpu_bo(obj);
30643042 adev = amdgpu_ttm_adev(rbo->tbo.bdev);
30653043 r = amdgpu_bo_reserve(rbo, false);
@@ -3067,12 +3045,11 @@ static int dm_plane_helper_prepare_fb(struct drm_plane *plane, · 1 unmodified line
30673045 return r;
30683046
30693047 if (plane->type != DRM_PLANE_TYPE_CURSOR)
3070− domain = amdgpu_display_framebuffer_domains(adev);
3048+ domain = amdgpu_display_supported_domains(adev);
30713049 else
30723050 domain = AMDGPU_GEM_DOMAIN_VRAM;
30733051
30743052 r = amdgpu_bo_pin(rbo, domain, &afb->address);
3075−
30763053 amdgpu_bo_unreserve(rbo);
30773054
30783055 if (unlikely(r != 0)) {
@@ -3123,14 +3100,12 @@ static void dm_plane_helper_cleanup_fb(struct drm_plane *plane, · 44 unmodified lines
31233100 struct drm_plane_state *old_state)
31243101 {
31253102 struct amdgpu_bo *rbo;
3126− struct amdgpu_framebuffer *afb;
31273103 int r;
31283104
31293105 if (!old_state->fb)
31303106 return;
31313107
3132− afb = to_amdgpu_framebuffer(old_state->fb);
3133− rbo = gem_to_amdgpu_bo(afb->obj);
3108+ rbo = gem_to_amdgpu_bo(old_state->fb->obj[0]);
31343109 r = amdgpu_bo_reserve(rbo, false);
31353110 if (unlikely(r)) {
31363111 DRM_ERROR("failed to reserve rbo before unpin\n");
@@ -3773,7 +3748,7 @@ static void remove_stream(struct amdgpu_device *adev, · 636 unmodified lines
37733748 static int get_cursor_position(struct drm_plane *plane, struct drm_crtc *crtc,
37743749 struct dc_cursor_position *position)
37753750 {
3776− struct amdgpu_crtc *amdgpu_crtc = amdgpu_crtc = to_amdgpu_crtc(crtc);
3751+ struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
37773752 int x, y;
37783753 int xorigin = 0, yorigin = 0;
37793754
@@ -3905,7 +3880,7 @@ static void amdgpu_dm_do_flip(struct drm_crtc *crtc, · 125 unmodified lines
39053880 int r, vpos, hpos;
39063881 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
39073882 struct amdgpu_framebuffer *afb = to_amdgpu_framebuffer(fb);
3908− struct amdgpu_bo *abo = gem_to_amdgpu_bo(afb->obj);
3883+ struct amdgpu_bo *abo = gem_to_amdgpu_bo(fb->obj[0]);
39093884 struct amdgpu_device *adev = crtc->dev->dev_private;
39103885 bool async_flip = (crtc->state->pageflip_flags & DRM_MODE_PAGE_FLIP_ASYNC) != 0;
39113886 struct dc_flip_addrs addr = { {0} };
@@ -3986,6 +3961,96 @@ static void amdgpu_dm_do_flip(struct drm_crtc *crtc, · 74 unmodified lines
39863961 spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
39873962 }
39883963
3964+/*
3965+ * TODO this whole function needs to go
3966+ *
3967+ * dc_surface_update is needlessly complex. See if we can just replace this
3968+ * with a dc_plane_state and follow the atomic model a bit more closely here.
3969+ */
3970+static bool commit_planes_to_stream(
3971+ struct dc *dc,
3972+ struct dc_plane_state **plane_states,
3973+ uint8_t new_plane_count,
3974+ struct dm_crtc_state *dm_new_crtc_state,
3975+ struct dm_crtc_state *dm_old_crtc_state,
3976+ struct dc_state *state)
3977+{
3978+ /* no need to dynamically allocate this. it's pretty small */
3979+ struct dc_surface_update updates[MAX_SURFACES];
3980+ struct dc_flip_addrs *flip_addr;
3981+ struct dc_plane_info *plane_info;
3982+ struct dc_scaling_info *scaling_info;
3983+ int i;
3984+ struct dc_stream_state *dc_stream = dm_new_crtc_state->stream;
3985+ struct dc_stream_update *stream_update =
3986+ kzalloc(sizeof(struct dc_stream_update), GFP_KERNEL);
3987+
3988+ if (!stream_update) {
3989+ BREAK_TO_DEBUGGER();
3990+ return false;
3991+ }
3992+
3993+ flip_addr = kcalloc(MAX_SURFACES, sizeof(struct dc_flip_addrs),
3994+ GFP_KERNEL);
3995+ plane_info = kcalloc(MAX_SURFACES, sizeof(struct dc_plane_info),
3996+ GFP_KERNEL);
3997+ scaling_info = kcalloc(MAX_SURFACES, sizeof(struct dc_scaling_info),
3998+ GFP_KERNEL);
3999+
4000+ if (!flip_addr || !plane_info || !scaling_info) {
4001+ kfree(flip_addr);
4002+ kfree(plane_info);
4003+ kfree(scaling_info);
4004+ kfree(stream_update);
4005+ return false;
4006+ }
4007+
4008+ memset(updates, 0, sizeof(updates));
4009+
4010+ stream_update->src = dc_stream->src;
4011+ stream_update->dst = dc_stream->dst;
4012+ stream_update->out_transfer_func = dc_stream->out_transfer_func;
4013+
4014+ for (i = 0; i < new_plane_count; i++) {
4015+ updates[i].surface = plane_states[i];
4016+ updates[i].gamma =
4017+ (struct dc_gamma *)plane_states[i]->gamma_correction;
4018+ updates[i].in_transfer_func = plane_states[i]->in_transfer_func;
4019+ flip_addr[i].address = plane_states[i]->address;
4020+ flip_addr[i].flip_immediate = plane_states[i]->flip_immediate;
4021+ plane_info[i].color_space = plane_states[i]->color_space;
4022+ plane_info[i].format = plane_states[i]->format;
4023+ plane_info[i].plane_size = plane_states[i]->plane_size;
4024+ plane_info[i].rotation = plane_states[i]->rotation;
4025+ plane_info[i].horizontal_mirror = plane_states[i]->horizontal_mirror;
4026+ plane_info[i].stereo_format = plane_states[i]->stereo_format;
4027+ plane_info[i].tiling_info = plane_states[i]->tiling_info;
4028+ plane_info[i].visible = plane_states[i]->visible;
4029+ plane_info[i].per_pixel_alpha = plane_states[i]->per_pixel_alpha;
4030+ plane_info[i].dcc = plane_states[i]->dcc;
4031+ scaling_info[i].scaling_quality = plane_states[i]->scaling_quality;
4032+ scaling_info[i].src_rect = plane_states[i]->src_rect;
4033+ scaling_info[i].dst_rect = plane_states[i]->dst_rect;
4034+ scaling_info[i].clip_rect = plane_states[i]->clip_rect;
4035+
4036+ updates[i].flip_addr = &flip_addr[i];
4037+ updates[i].plane_info = &plane_info[i];
4038+ updates[i].scaling_info = &scaling_info[i];
4039+ }
4040+
4041+ dc_commit_updates_for_stream(
4042+ dc,
4043+ updates,
4044+ new_plane_count,
4045+ dc_stream, stream_update, plane_states, state);
4046+
4047+ kfree(flip_addr);
4048+ kfree(plane_info);
4049+ kfree(scaling_info);
4050+ kfree(stream_update);
4051+ return true;
4052+}
4053+
39894054 static void amdgpu_dm_commit_planes(struct drm_atomic_state *state,
39904055 struct drm_device *dev,
39914056 struct amdgpu_display_manager *dm,
@@ -4001,6 +4066,8 @@ static void amdgpu_dm_commit_planes(struct drm_atomic_state *state, · 9 unmodified lines
40014066 struct drm_crtc_state *new_pcrtc_state =
40024067 drm_atomic_get_new_crtc_state(state, pcrtc);
40034068 struct dm_crtc_state *acrtc_state = to_dm_crtc_state(new_pcrtc_state);
4069+ struct dm_crtc_state *dm_old_crtc_state =
4070+ to_dm_crtc_state(drm_atomic_get_old_crtc_state(state, pcrtc));
40044071 struct dm_atomic_state *dm_state = to_dm_atomic_state(state);
40054072 int planes_count = 0;
40064073 unsigned long flags;
@@ -4037,7 +4104,7 @@ static void amdgpu_dm_commit_planes(struct drm_atomic_state *state, · 30 unmodified lines
40374104 }
40384105 spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
40394106
4040− if (!pflip_needed) {
4107+ if (!pflip_needed || plane->type == DRM_PLANE_TYPE_OVERLAY) {
40414108 WARN_ON(!dm_new_plane_state->dc_state);
40424109
40434110 plane_states_constructed[planes_count] = dm_new_plane_state->dc_state;
@@ -4079,10 +4146,12 @@ static void amdgpu_dm_commit_planes(struct drm_atomic_state *state, · 35 unmodified lines
40794146 spin_unlock_irqrestore(&pcrtc->dev->event_lock, flags);
40804147 }
40814148
4082− if (false == dc_commit_planes_to_stream(dm->dc,
4149+
4150+ if (false == commit_planes_to_stream(dm->dc,
40834151 plane_states_constructed,
40844152 planes_count,
4085− dc_stream_attach,
4153+ acrtc_state,
4154+ dm_old_crtc_state,
40864155 dm_state->context))
40874156 dm_error("%s: Failed to attach plane!\n", __func__);
40884157 } else {
@@ -4307,8 +4376,10 @@ static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state) · 218 unmodified lines
43074376 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc);
43084377 struct dc_stream_status *status = NULL;
43094378
4310− if (acrtc)
4379+ if (acrtc) {
43114380 new_crtc_state = drm_atomic_get_new_crtc_state(state, &acrtc->base);
4381+ old_crtc_state = drm_atomic_get_old_crtc_state(state, &acrtc->base);
4382+ }
43124383
43134384 /* Skip any modesets/resets */
43144385 if (!acrtc || drm_atomic_crtc_needs_modeset(new_crtc_state))
@@ -4331,11 +4402,12 @@ static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state) · 16 unmodified lines
43314402 WARN_ON(!status->plane_count);
43324403
43334404 /*TODO How it works with MPO ?*/
4334− if (!dc_commit_planes_to_stream(
4405+ if (!commit_planes_to_stream(
43354406 dm->dc,
43364407 status->plane_states,
43374408 status->plane_count,
4338− dm_new_crtc_state->stream,
4409+ dm_new_crtc_state,
4410+ to_dm_crtc_state(old_crtc_state),
43394411 dm_state->context))
43404412 dm_error("%s: Failed to update stream scaling!\n", __func__);
43414413 }
@@ -4578,7 +4650,7 @@ static int dm_update_crtcs_state(struct dc *dc, · 236 unmodified lines
45784650 if (aconnector && enable) {
45794651 // Make sure fake sink is created in plug-in scenario
45804652 new_con_state = drm_atomic_get_connector_state(state,
4581− &aconnector->base);
4653+ &aconnector->base);
45824654
45834655 if (IS_ERR(new_con_state)) {
45844656 ret = PTR_ERR_OR_ZERO(new_con_state);
@@ -4755,7 +4827,8 @@ static int dm_update_planes_state(struct dc *dc, · 170 unmodified lines
47554827
47564828 /* Remove any changed/removed planes */
47574829 if (!enable) {
4758− if (pflip_needed)
4830+ if (pflip_needed &&
4831+ plane->type != DRM_PLANE_TYPE_OVERLAY)
47594832 continue;
47604833
47614834 if (!old_plane_crtc)
@@ -4802,7 +4875,8 @@ static int dm_update_planes_state(struct dc *dc, · 40 unmodified lines
48024875 if (!dm_new_crtc_state->stream)
48034876 continue;
48044877
4805− if (pflip_needed)
4878+ if (pflip_needed &&
4879+ plane->type != DRM_PLANE_TYPE_OVERLAY)
48064880 continue;
48074881
48084882 WARN_ON(dm_new_plane_state->dc_state);
@@ -5009,17 +5083,24 @@ void amdgpu_dm_add_sink_to_freesync_module(struct drm_connector *connector, · 200 unmodified lines
50095083 struct edid *edid)
50105084 {
50115085 int i;
5012− uint64_t val_capable;
50135086 bool edid_check_required;
50145087 struct detailed_timing *timing;
50155088 struct detailed_non_pixel *data;
50165089 struct detailed_data_monitor_range *range;
50175090 struct amdgpu_dm_connector *amdgpu_dm_connector =
50185091 to_amdgpu_dm_connector(connector);
5092+ struct dm_connector_state *dm_con_state;
50195093
50205094 struct drm_device *dev = connector->dev;
50215095 struct amdgpu_device *adev = dev->dev_private;
50225096
5097+ if (!connector->state) {
5098+ DRM_ERROR("%s - Connector has no state", __func__);
5099+ return;
5100+ }
5101+
5102+ dm_con_state = to_dm_connector_state(connector->state);
5103+
50235104 edid_check_required = false;
50245105 if (!amdgpu_dm_connector->dc_sink) {
50255106 DRM_ERROR("dc_sink NULL, could not add free_sync module.\n");
@@ -5038,7 +5119,7 @@ void amdgpu_dm_add_sink_to_freesync_module(struct drm_connector *connector, · 12 unmodified lines
50385119 amdgpu_dm_connector);
50395120 }
50405121 }
5041− val_capable = 0;
5122+ dm_con_state->freesync_capable = false;
50425123 if (edid_check_required == true && (edid->version > 1 ||
50435124 (edid->version == 1 && edid->revision > 1))) {
50445125 for (i = 0; i < 4; i++) {
@@ -5074,7 +5155,7 @@ void amdgpu_dm_add_sink_to_freesync_module(struct drm_connector *connector, · 29 unmodified lines
50745155 amdgpu_dm_connector->min_vfreq * 1000000;
50755156 amdgpu_dm_connector->caps.max_refresh_in_micro_hz =
50765157 amdgpu_dm_connector->max_vfreq * 1000000;
5077− val_capable = 1;
5158+ dm_con_state->freesync_capable = true;
50785159 }
50795160 }
50805161
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h+3−2
@@ -28,7 +28,6 @@ · 27 unmodified lines
2828
2929 #include <drm/drmP.h>
3030 #include <drm/drm_atomic.h>
31−#include "dc.h"
3231
3332 /*
3433 * This file contains the definition for amdgpu_display_manager
@@ -53,6 +52,7 @@ · 18 unmodified lines
5352 struct amdgpu_device;
5453 struct drm_device;
5554 struct amdgpu_dm_irq_handler_data;
55+struct dc;
5656
5757 struct amdgpu_dm_prev_state {
5858 struct drm_framebuffer *fb;
@@ -220,6 +220,7 @@ struct dm_connector_state { · 161 unmodified lines
220220 uint8_t underscan_hborder;
221221 bool underscan_enable;
222222 struct mod_freesync_user_enable user_enable;
223+ bool freesync_capable;
223224 };
224225
225226 #define to_dm_connector_state(x)\
@@ -246,7 +247,7 @@ void amdgpu_dm_connector_init_helper(struct amdgpu_display_manager *dm, · 20 unmodified lines
246247 struct dc_link *link,
247248 int link_index);
248249
249−int amdgpu_dm_connector_mode_valid(struct drm_connector *connector,
250+enum drm_mode_status amdgpu_dm_connector_mode_valid(struct drm_connector *connector,
250251 struct drm_display_mode *mode);
251252
252253 void dm_restore_drm_connector_state(struct drm_device *dev,
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c+1−0
@@ -25,6 +25,7 @@ · 24 unmodified lines
2525
2626 #include "amdgpu_mode.h"
2727 #include "amdgpu_dm.h"
28+#include "dc.h"
2829 #include "modules/color/color_gamma.h"
2930
3031 #define MAX_DRM_LUT_VALUE 0xFFFF
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c+12−8
@@ -83,21 +83,22 @@ static ssize_t dm_dp_aux_transfer(struct drm_dp_aux *aux, · 82 unmodified lines
8383 enum i2c_mot_mode mot = (msg->request & DP_AUX_I2C_MOT) ?
8484 I2C_MOT_TRUE : I2C_MOT_FALSE;
8585 enum ddc_result res;
86− ssize_t read_bytes;
86+ uint32_t read_bytes = msg->size;
8787
8888 if (WARN_ON(msg->size > 16))
8989 return -E2BIG;
9090
9191 switch (msg->request & ~DP_AUX_I2C_MOT) {
9292 case DP_AUX_NATIVE_READ:
93− read_bytes = dal_ddc_service_read_dpcd_data(
93+ res = dal_ddc_service_read_dpcd_data(
9494 TO_DM_AUX(aux)->ddc_service,
9595 false,
9696 I2C_MOT_UNDEF,
9797 msg->address,
9898 msg->buffer,
99− msg->size);
100− return read_bytes;
99+ msg->size,
100+ &read_bytes);
101+ break;
101102 case DP_AUX_NATIVE_WRITE:
102103 res = dal_ddc_service_write_dpcd_data(
103104 TO_DM_AUX(aux)->ddc_service,
@@ -108,14 +109,15 @@ static ssize_t dm_dp_aux_transfer(struct drm_dp_aux *aux, · 4 unmodified lines
108109 msg->size);
109110 break;
110111 case DP_AUX_I2C_READ:
111− read_bytes = dal_ddc_service_read_dpcd_data(
112+ res = dal_ddc_service_read_dpcd_data(
112113 TO_DM_AUX(aux)->ddc_service,
113114 true,
114115 mot,
115116 msg->address,
116117 msg->buffer,
117− msg->size);
118− return read_bytes;
118+ msg->size,
119+ &read_bytes);
120+ break;
119121 case DP_AUX_I2C_WRITE:
120122 res = dal_ddc_service_write_dpcd_data(
121123 TO_DM_AUX(aux)->ddc_service,
@@ -137,7 +139,9 @@ static ssize_t dm_dp_aux_transfer(struct drm_dp_aux *aux, · 15 unmodified lines
137139 r == DDC_RESULT_SUCESSFULL);
138140 #endif
139141
140− return msg->size;
142+ if (res != DDC_RESULT_SUCESSFULL)
143+ return -EIO;
144+ return read_bytes;
141145 }
142146
143147 static enum drm_connector_status
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_services.c+11−2
@@ -37,8 +37,17 @@ · 36 unmodified lines
3737
3838 unsigned long long dm_get_timestamp(struct dc_context *ctx)
3939 {
40− /* TODO: return actual timestamp */
41− return 0;
40+ struct timespec64 time;
41+
42+ getrawmonotonic64(&time);
43+ return timespec64_to_ns(&time);
44+}
45+
46+unsigned long long dm_get_elapse_time_in_ns(struct dc_context *ctx,
47+ unsigned long long current_time_stamp,
48+ unsigned long long last_time_stamp)
49+{
50+ return current_time_stamp - last_time_stamp;
4251 }
4352
4453 void dm_perf_trace_timestamp(const char *func_name, unsigned int line)
drivers/gpu/drm/amd/display/dc/basics/fixpt31_32.c+79−79
@@ -26,13 +26,13 @@ · 25 unmodified lines
2626 #include "dm_services.h"
2727 #include "include/fixed31_32.h"
2828
29−static inline uint64_t abs_i64(
30− int64_t arg)
29+static inline unsigned long long abs_i64(
30+ long long arg)
3131 {
3232 if (arg > 0)
33− return (uint64_t)arg;
33+ return (unsigned long long)arg;
3434 else
35− return (uint64_t)(-arg);
35+ return (unsigned long long)(-arg);
3636 }
3737
3838 /*
@@ -40,12 +40,12 @@ static inline uint64_t abs_i64( · 1 unmodified line
4040 * result = dividend / divisor
4141 * *remainder = dividend % divisor
4242 */
43−static inline uint64_t complete_integer_division_u64(
44− uint64_t dividend,
45− uint64_t divisor,
46− uint64_t *remainder)
43+static inline unsigned long long complete_integer_division_u64(
44+ unsigned long long dividend,
45+ unsigned long long divisor,
46+ unsigned long long *remainder)
4747 {
48− uint64_t result;
48+ unsigned long long result;
4949
5050 ASSERT(divisor);
5151
@@ -65,29 +65,29 @@ static inline uint64_t complete_integer_division_u64( · 13 unmodified lines
6565 (FRACTIONAL_PART_MASK & (x))
6666
6767 struct fixed31_32 dal_fixed31_32_from_fraction(
68− int64_t numerator,
69− int64_t denominator)
68+ long long numerator,
69+ long long denominator)
7070 {
7171 struct fixed31_32 res;
7272
7373 bool arg1_negative = numerator < 0;
7474 bool arg2_negative = denominator < 0;
7575
76− uint64_t arg1_value = arg1_negative ? -numerator : numerator;
77− uint64_t arg2_value = arg2_negative ? -denominator : denominator;
76+ unsigned long long arg1_value = arg1_negative ? -numerator : numerator;
77+ unsigned long long arg2_value = arg2_negative ? -denominator : denominator;
7878
79− uint64_t remainder;
79+ unsigned long long remainder;
8080
8181 /* determine integer part */
8282
83− uint64_t res_value = complete_integer_division_u64(
83+ unsigned long long res_value = complete_integer_division_u64(
8484 arg1_value, arg2_value, &remainder);
8585
8686 ASSERT(res_value <= LONG_MAX);
8787
8888 /* determine fractional part */
8989 {
90− uint32_t i = FIXED31_32_BITS_PER_FRACTIONAL_PART;
90+ unsigned int i = FIXED31_32_BITS_PER_FRACTIONAL_PART;
9191
9292 do {
9393 remainder <<= 1;
@@ -103,14 +103,14 @@ struct fixed31_32 dal_fixed31_32_from_fraction( · 9 unmodified lines
103103
104104 /* round up LSB */
105105 {
106− uint64_t summand = (remainder << 1) >= arg2_value;
106+ unsigned long long summand = (remainder << 1) >= arg2_value;
107107
108108 ASSERT(res_value <= LLONG_MAX - summand);
109109
110110 res_value += summand;
111111 }
112112
113− res.value = (int64_t)res_value;
113+ res.value = (long long)res_value;
114114
115115 if (arg1_negative ^ arg2_negative)
116116 res.value = -res.value;
@@ -119,7 +119,7 @@ struct fixed31_32 dal_fixed31_32_from_fraction( · 2 unmodified lines
119119 }
120120
121121 struct fixed31_32 dal_fixed31_32_from_int_nonconst(
122− int64_t arg)
122+ long long arg)
123123 {
124124 struct fixed31_32 res;
125125
@@ -132,7 +132,7 @@ struct fixed31_32 dal_fixed31_32_from_int_nonconst( · 6 unmodified lines
132132
133133 struct fixed31_32 dal_fixed31_32_shl(
134134 struct fixed31_32 arg,
135− uint8_t shift)
135+ unsigned char shift)
136136 {
137137 struct fixed31_32 res;
138138
@@ -181,16 +181,16 @@ struct fixed31_32 dal_fixed31_32_mul( · 42 unmodified lines
181181 bool arg1_negative = arg1.value < 0;
182182 bool arg2_negative = arg2.value < 0;
183183
184− uint64_t arg1_value = arg1_negative ? -arg1.value : arg1.value;
185− uint64_t arg2_value = arg2_negative ? -arg2.value : arg2.value;
184+ unsigned long long arg1_value = arg1_negative ? -arg1.value : arg1.value;
185+ unsigned long long arg2_value = arg2_negative ? -arg2.value : arg2.value;
186186
187− uint64_t arg1_int = GET_INTEGER_PART(arg1_value);
188− uint64_t arg2_int = GET_INTEGER_PART(arg2_value);
187+ unsigned long long arg1_int = GET_INTEGER_PART(arg1_value);
188+ unsigned long long arg2_int = GET_INTEGER_PART(arg2_value);
189189
190− uint64_t arg1_fra = GET_FRACTIONAL_PART(arg1_value);
191− uint64_t arg2_fra = GET_FRACTIONAL_PART(arg2_value);
190+ unsigned long long arg1_fra = GET_FRACTIONAL_PART(arg1_value);
191+ unsigned long long arg2_fra = GET_FRACTIONAL_PART(arg2_value);
192192
193− uint64_t tmp;
193+ unsigned long long tmp;
194194
195195 res.value = arg1_int * arg2_int;
196196
@@ -200,22 +200,22 @@ struct fixed31_32 dal_fixed31_32_mul( · 3 unmodified lines
200200
201201 tmp = arg1_int * arg2_fra;
202202
203− ASSERT(tmp <= (uint64_t)(LLONG_MAX - res.value));
203+ ASSERT(tmp <= (unsigned long long)(LLONG_MAX - res.value));
204204
205205 res.value += tmp;
206206
207207 tmp = arg2_int * arg1_fra;
208208
209− ASSERT(tmp <= (uint64_t)(LLONG_MAX - res.value));
209+ ASSERT(tmp <= (unsigned long long)(LLONG_MAX - res.value));
210210
211211 res.value += tmp;
212212
213213 tmp = arg1_fra * arg2_fra;
214214
215215 tmp = (tmp >> FIXED31_32_BITS_PER_FRACTIONAL_PART) +
216− (tmp >= (uint64_t)dal_fixed31_32_half.value);
216+ (tmp >= (unsigned long long)dal_fixed31_32_half.value);
217217
218− ASSERT(tmp <= (uint64_t)(LLONG_MAX - res.value));
218+ ASSERT(tmp <= (unsigned long long)(LLONG_MAX - res.value));
219219
220220 res.value += tmp;
221221
@@ -230,13 +230,13 @@ struct fixed31_32 dal_fixed31_32_sqr( · 8 unmodified lines
230230 {
231231 struct fixed31_32 res;
232232
233− uint64_t arg_value = abs_i64(arg.value);
233+ unsigned long long arg_value = abs_i64(arg.value);
234234
235− uint64_t arg_int = GET_INTEGER_PART(arg_value);
235+ unsigned long long arg_int = GET_INTEGER_PART(arg_value);
236236
237− uint64_t arg_fra = GET_FRACTIONAL_PART(arg_value);
237+ unsigned long long arg_fra = GET_FRACTIONAL_PART(arg_value);
238238
239− uint64_t tmp;
239+ unsigned long long tmp;
240240
241241 res.value = arg_int * arg_int;
242242
@@ -246,20 +246,20 @@ struct fixed31_32 dal_fixed31_32_sqr( · 3 unmodified lines
246246
247247 tmp = arg_int * arg_fra;
248248
249− ASSERT(tmp <= (uint64_t)(LLONG_MAX - res.value));
249+ ASSERT(tmp <= (unsigned long long)(LLONG_MAX - res.value));
250250
251251 res.value += tmp;
252252
253− ASSERT(tmp <= (uint64_t)(LLONG_MAX - res.value));
253+ ASSERT(tmp <= (unsigned long long)(LLONG_MAX - res.value));
254254
255255 res.value += tmp;
256256
257257 tmp = arg_fra * arg_fra;
258258
259259 tmp = (tmp >> FIXED31_32_BITS_PER_FRACTIONAL_PART) +
260− (tmp >= (uint64_t)dal_fixed31_32_half.value);
260+ (tmp >= (unsigned long long)dal_fixed31_32_half.value);
261261
262− ASSERT(tmp <= (uint64_t)(LLONG_MAX - res.value));
262+ ASSERT(tmp <= (unsigned long long)(LLONG_MAX - res.value));
263263
264264 res.value += tmp;
265265
@@ -288,7 +288,7 @@ struct fixed31_32 dal_fixed31_32_sinc( · 22 unmodified lines
288288
289289 struct fixed31_32 res = dal_fixed31_32_one;
290290
291− int32_t n = 27;
291+ int n = 27;
292292
293293 struct fixed31_32 arg_norm = arg;
294294
@@ -299,7 +299,7 @@ struct fixed31_32 dal_fixed31_32_sinc( · 4 unmodified lines
299299 arg_norm,
300300 dal_fixed31_32_mul_int(
301301 dal_fixed31_32_two_pi,
302− (int32_t)div64_s64(
302+ (int)div64_s64(
303303 arg_norm.value,
304304 dal_fixed31_32_two_pi.value)));
305305 }
@@ -343,7 +343,7 @@ struct fixed31_32 dal_fixed31_32_cos( · 37 unmodified lines
343343
344344 struct fixed31_32 res = dal_fixed31_32_one;
345345
346− int32_t n = 26;
346+ int n = 26;
347347
348348 do {
349349 res = dal_fixed31_32_sub(
@@ -370,7 +370,7 @@ struct fixed31_32 dal_fixed31_32_cos( · 20 unmodified lines
370370 static struct fixed31_32 fixed31_32_exp_from_taylor_series(
371371 struct fixed31_32 arg)
372372 {
373− uint32_t n = 9;
373+ unsigned int n = 9;
374374
375375 struct fixed31_32 res = dal_fixed31_32_from_fraction(
376376 n + 2,
@@ -409,7 +409,7 @@ struct fixed31_32 dal_fixed31_32_exp( · 32 unmodified lines
409409 if (dal_fixed31_32_le(
410410 dal_fixed31_32_ln2_div_2,
411411 dal_fixed31_32_abs(arg))) {
412− int32_t m = dal_fixed31_32_round(
412+ int m = dal_fixed31_32_round(
413413 dal_fixed31_32_div(
414414 arg,
415415 dal_fixed31_32_ln2));
@@ -429,7 +429,7 @@ struct fixed31_32 dal_fixed31_32_exp( · 13 unmodified lines
429429 if (m > 0)
430430 return dal_fixed31_32_shl(
431431 fixed31_32_exp_from_taylor_series(r),
432− (uint8_t)m);
432+ (unsigned char)m);
433433 else
434434 return dal_fixed31_32_div_int(
435435 fixed31_32_exp_from_taylor_series(r),
@@ -482,50 +482,50 @@ struct fixed31_32 dal_fixed31_32_pow( · 46 unmodified lines
482482 arg2));
483483 }
484484
485−int32_t dal_fixed31_32_floor(
485+int dal_fixed31_32_floor(
486486 struct fixed31_32 arg)
487487 {
488− uint64_t arg_value = abs_i64(arg.value);
488+ unsigned long long arg_value = abs_i64(arg.value);
489489
490490 if (arg.value >= 0)
491− return (int32_t)GET_INTEGER_PART(arg_value);
491+ return (int)GET_INTEGER_PART(arg_value);
492492 else
493− return -(int32_t)GET_INTEGER_PART(arg_value);
493+ return -(int)GET_INTEGER_PART(arg_value);
494494 }
495495
496−int32_t dal_fixed31_32_round(
496+int dal_fixed31_32_round(
497497 struct fixed31_32 arg)
498498 {
499− uint64_t arg_value = abs_i64(arg.value);
499+ unsigned long long arg_value = abs_i64(arg.value);
500500
501− const int64_t summand = dal_fixed31_32_half.value;
501+ const long long summand = dal_fixed31_32_half.value;
502502
503− ASSERT(LLONG_MAX - (int64_t)arg_value >= summand);
503+ ASSERT(LLONG_MAX - (long long)arg_value >= summand);
504504
505505 arg_value += summand;
506506
507507 if (arg.value >= 0)
508− return (int32_t)GET_INTEGER_PART(arg_value);
508+ return (int)GET_INTEGER_PART(arg_value);
509509 else
510− return -(int32_t)GET_INTEGER_PART(arg_value);
510+ return -(int)GET_INTEGER_PART(arg_value);
511511 }
512512
513−int32_t dal_fixed31_32_ceil(
513+int dal_fixed31_32_ceil(
514514 struct fixed31_32 arg)
515515 {
516− uint64_t arg_value = abs_i64(arg.value);
516+ unsigned long long arg_value = abs_i64(arg.value);
517517
518− const int64_t summand = dal_fixed31_32_one.value -
518+ const long long summand = dal_fixed31_32_one.value -
519519 dal_fixed31_32_epsilon.value;
520520
521− ASSERT(LLONG_MAX - (int64_t)arg_value >= summand);
521+ ASSERT(LLONG_MAX - (long long)arg_value >= summand);
522522
523523 arg_value += summand;
524524
525525 if (arg.value >= 0)
526− return (int32_t)GET_INTEGER_PART(arg_value);
526+ return (int)GET_INTEGER_PART(arg_value);
527527 else
528− return -(int32_t)GET_INTEGER_PART(arg_value);
528+ return -(int)GET_INTEGER_PART(arg_value);
529529 }
530530
531531 /* this function is a generic helper to translate fixed point value to
@@ -535,15 +535,15 @@ int32_t dal_fixed31_32_ceil( · 3 unmodified lines
535535 * part in 32 bits. It is used in hw programming (scaler)
536536 */
537537
538−static inline uint32_t ux_dy(
539− int64_t value,
540− uint32_t integer_bits,
541− uint32_t fractional_bits)
538+static inline unsigned int ux_dy(
539+ long long value,
540+ unsigned int integer_bits,
541+ unsigned int fractional_bits)
542542 {
543543 /* 1. create mask of integer part */
544− uint32_t result = (1 << integer_bits) - 1;
544+ unsigned int result = (1 << integer_bits) - 1;
545545 /* 2. mask out fractional part */
546− uint32_t fractional_part = FRACTIONAL_PART_MASK & value;
546+ unsigned int fractional_part = FRACTIONAL_PART_MASK & value;
547547 /* 3. shrink fixed point integer part to be of integer_bits width*/
548548 result &= GET_INTEGER_PART(value);
549549 /* 4. make space for fractional part to be filled in after integer */
@@ -554,13 +554,13 @@ static inline uint32_t ux_dy( · 4 unmodified lines
554554 return result | fractional_part;
555555 }
556556
557−static inline uint32_t clamp_ux_dy(
558− int64_t value,
559− uint32_t integer_bits,
560− uint32_t fractional_bits,
561− uint32_t min_clamp)
557+static inline unsigned int clamp_ux_dy(
558+ long long value,
559+ unsigned int integer_bits,
560+ unsigned int fractional_bits,
561+ unsigned int min_clamp)
562562 {
563− uint32_t truncated_val = ux_dy(value, integer_bits, fractional_bits);
563+ unsigned int truncated_val = ux_dy(value, integer_bits, fractional_bits);
564564
565565 if (value >= (1LL << (integer_bits + FIXED31_32_BITS_PER_FRACTIONAL_PART)))
566566 return (1 << (integer_bits + fractional_bits)) - 1;
@@ -570,35 +570,35 @@ static inline uint32_t clamp_ux_dy( · 3 unmodified lines
570570 return min_clamp;
571571 }
572572
573−uint32_t dal_fixed31_32_u2d19(
573+unsigned int dal_fixed31_32_u2d19(
574574 struct fixed31_32 arg)
575575 {
576576 return ux_dy(arg.value, 2, 19);
577577 }
578578
579−uint32_t dal_fixed31_32_u0d19(
579+unsigned int dal_fixed31_32_u0d19(
580580 struct fixed31_32 arg)
581581 {
582582 return ux_dy(arg.value, 0, 19);
583583 }
584584
585−uint32_t dal_fixed31_32_clamp_u0d14(
585+unsigned int dal_fixed31_32_clamp_u0d14(
586586 struct fixed31_32 arg)
587587 {
588588 return clamp_ux_dy(arg.value, 0, 14, 1);
589589 }
590590
591−uint32_t dal_fixed31_32_clamp_u0d10(
591+unsigned int dal_fixed31_32_clamp_u0d10(
592592 struct fixed31_32 arg)
593593 {
594594 return clamp_ux_dy(arg.value, 0, 10, 1);
595595 }
596596
597−int32_t dal_fixed31_32_s4d19(
597+int dal_fixed31_32_s4d19(
598598 struct fixed31_32 arg)
599599 {
600600 if (arg.value < 0)
601− return -(int32_t)ux_dy(dal_fixed31_32_abs(arg).value, 4, 19);
601+ return -(int)ux_dy(dal_fixed31_32_abs(arg).value, 4, 19);
602602 else
603603 return ux_dy(arg.value, 4, 19);
604604 }
drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c+85−1
@@ -70,6 +70,10 @@ static enum bp_result get_firmware_info_v3_1( · 69 unmodified lines
7070 struct bios_parser *bp,
7171 struct dc_firmware_info *info);
7272
73+static enum bp_result get_firmware_info_v3_2(
74+ struct bios_parser *bp,
75+ struct dc_firmware_info *info);
76+
7377 static struct atom_hpd_int_record *get_hpd_record(struct bios_parser *bp,
7478 struct atom_display_object_path_v2 *object);
7579
@@ -1321,9 +1325,11 @@ static enum bp_result bios_parser_get_firmware_info( · 1245 unmodified lines
13211325 case 3:
13221326 switch (revision.minor) {
13231327 case 1:
1324− case 2:
13251328 result = get_firmware_info_v3_1(bp, info);
13261329 break;
1330+ case 2:
1331+ result = get_firmware_info_v3_2(bp, info);
1332+ break;
13271333 default:
13281334 break;
13291335 }
@@ -1383,6 +1389,84 @@ static enum bp_result get_firmware_info_v3_1( · 53 unmodified lines
13831389 return BP_RESULT_OK;
13841390 }
13851391
1392+static enum bp_result get_firmware_info_v3_2(
1393+ struct bios_parser *bp,
1394+ struct dc_firmware_info *info)
1395+{
1396+ struct atom_firmware_info_v3_2 *firmware_info;
1397+ struct atom_display_controller_info_v4_1 *dce_info = NULL;
1398+ struct atom_common_table_header *header;
1399+ struct atom_data_revision revision;
1400+ struct atom_smu_info_v3_2 *smu_info_v3_2 = NULL;
1401+ struct atom_smu_info_v3_3 *smu_info_v3_3 = NULL;
1402+
1403+ if (!info)
1404+ return BP_RESULT_BADINPUT;
1405+
1406+ firmware_info = GET_IMAGE(struct atom_firmware_info_v3_2,
1407+ DATA_TABLES(firmwareinfo));
1408+
1409+ dce_info = GET_IMAGE(struct atom_display_controller_info_v4_1,
1410+ DATA_TABLES(dce_info));
1411+
1412+ if (!firmware_info || !dce_info)
1413+ return BP_RESULT_BADBIOSTABLE;
1414+
1415+ memset(info, 0, sizeof(*info));
1416+
1417+ header = GET_IMAGE(struct atom_common_table_header,
1418+ DATA_TABLES(smu_info));
1419+ get_atom_data_table_revision(header, &revision);
1420+
1421+ if (revision.minor == 2) {
1422+ /* Vega12 */
1423+ smu_info_v3_2 = GET_IMAGE(struct atom_smu_info_v3_2,
1424+ DATA_TABLES(smu_info));
1425+
1426+ if (!smu_info_v3_2)
1427+ return BP_RESULT_BADBIOSTABLE;
1428+
1429+ info->default_engine_clk = smu_info_v3_2->bootup_dcefclk_10khz * 10;
1430+ } else if (revision.minor == 3) {
1431+ /* Vega20 */
1432+ smu_info_v3_3 = GET_IMAGE(struct atom_smu_info_v3_3,
1433+ DATA_TABLES(smu_info));
1434+
1435+ if (!smu_info_v3_3)
1436+ return BP_RESULT_BADBIOSTABLE;
1437+
1438+ info->default_engine_clk = smu_info_v3_3->bootup_dcefclk_10khz * 10;
1439+ }
1440+
1441+ // We need to convert from 10KHz units into KHz units.
1442+ info->default_memory_clk = firmware_info->bootup_mclk_in10khz * 10;
1443+
1444+ /* 27MHz for Vega10 & Vega12; 100MHz for Vega20 */
1445+ info->pll_info.crystal_frequency = dce_info->dce_refclk_10khz * 10;
1446+ /* Hardcode frequency if BIOS gives no DCE Ref Clk */
1447+ if (info->pll_info.crystal_frequency == 0) {
1448+ if (revision.minor == 2)
1449+ info->pll_info.crystal_frequency = 27000;
1450+ else if (revision.minor == 3)
1451+ info->pll_info.crystal_frequency = 100000;
1452+ }
1453+ /*dp_phy_ref_clk is not correct for atom_display_controller_info_v4_2, but we don't use it*/
1454+ info->dp_phy_ref_clk = dce_info->dpphy_refclk_10khz * 10;
1455+ info->i2c_engine_ref_clk = dce_info->i2c_engine_refclk_10khz * 10;
1456+
1457+ /* Get GPU PLL VCO Clock */
1458+ if (bp->cmd_tbl.get_smu_clock_info != NULL) {
1459+ if (revision.minor == 2)
1460+ info->smu_gpu_pll_output_freq =
1461+ bp->cmd_tbl.get_smu_clock_info(bp, SMU9_SYSPLL0_ID) * 10;
1462+ else if (revision.minor == 3)
1463+ info->smu_gpu_pll_output_freq =
1464+ bp->cmd_tbl.get_smu_clock_info(bp, SMU11_SYSPLL3_0_ID) * 10;
1465+ }
1466+
1467+ return BP_RESULT_OK;
1468+}
1469+
13861470 static enum bp_result bios_parser_get_encoder_cap_info(
13871471 struct dc_bios *dcb,
13881472 struct graphics_object_id object_id,
drivers/gpu/drm/amd/display/dc/bios/command_table.c+12−10
@@ -24,7 +24,7 @@ · 23 unmodified lines
2424 */
2525
2626 #include "dm_services.h"
27−
27+#include "amdgpu.h"
2828 #include "atom.h"
2929
3030 #include "include/bios_parser_interface.h"
@@ -35,16 +35,16 @@ · 4 unmodified lines
3535 #include "bios_parser_types_internal.h"
3636
3737 #define EXEC_BIOS_CMD_TABLE(command, params)\
38− (cgs_atom_exec_cmd_table(bp->base.ctx->cgs_device, \
38+ (amdgpu_atom_execute_table(((struct amdgpu_device *)bp->base.ctx->driver_context)->mode_info.atom_context, \
3939 GetIndexIntoMasterTable(COMMAND, command), \
40− &params) == 0)
40+ (uint32_t *)&params) == 0)
4141
4242 #define BIOS_CMD_TABLE_REVISION(command, frev, crev)\
43− cgs_atom_get_cmd_table_revs(bp->base.ctx->cgs_device, \
43+ amdgpu_atom_parse_cmd_header(((struct amdgpu_device *)bp->base.ctx->driver_context)->mode_info.atom_context, \
4444 GetIndexIntoMasterTable(COMMAND, command), &frev, &crev)
4545
4646 #define BIOS_CMD_TABLE_PARA_REVISION(command)\
47− bios_cmd_table_para_revision(bp->base.ctx->cgs_device, \
47+ bios_cmd_table_para_revision(bp->base.ctx->driver_context, \
4848 GetIndexIntoMasterTable(COMMAND, command))
4949
5050 static void init_dig_encoder_control(struct bios_parser *bp);
@@ -82,16 +82,18 @@ void dal_bios_parser_init_cmd_tbl(struct bios_parser *bp) · 31 unmodified lines
8282 init_set_dce_clock(bp);
8383 }
8484
85−static uint32_t bios_cmd_table_para_revision(void *cgs_device,
85+static uint32_t bios_cmd_table_para_revision(void *dev,
8686 uint32_t index)
8787 {
88+ struct amdgpu_device *adev = dev;
8889 uint8_t frev, crev;
8990
90− if (cgs_atom_get_cmd_table_revs(cgs_device,
91+ if (amdgpu_atom_parse_cmd_header(adev->mode_info.atom_context,
9192 index,
92− &frev, &crev) != 0)
93+ &frev, &crev))
94+ return crev;
95+ else
9396 return 0;
94− return crev;
9597 }
9698
9799 /*******************************************************************************
@@ -368,7 +370,7 @@ static void init_transmitter_control(struct bios_parser *bp) · 270 unmodified lines
368370 uint8_t crev;
369371
370372 if (BIOS_CMD_TABLE_REVISION(UNIPHYTransmitterControl,
371− frev, crev) != 0)
373+ frev, crev) == false)
372374 BREAK_TO_DEBUGGER();
373375 switch (crev) {
374376 case 2:
drivers/gpu/drm/amd/display/dc/bios/command_table2.c+16−10
@@ -26,14 +26,18 @@ · 25 unmodified lines
2626 #include "dm_services.h"
2727
2828 #include "ObjectID.h"
29−#include "atomfirmware.h"
3029
30+#include "atomfirmware.h"
31+#include "atom.h"
3132 #include "include/bios_parser_interface.h"
3233
3334 #include "command_table2.h"
3435 #include "command_table_helper2.h"
3536 #include "bios_parser_helper.h"
3637 #include "bios_parser_types_internal2.h"
38+#include "amdgpu.h"
39+
40+
3741 #define DC_LOGGER \
3842 bp->base.ctx->logger
3943
@@ -43,16 +47,16 @@ · 3 unmodified lines
4347 ->FieldName)-(char *)0)/sizeof(uint16_t))
4448
4549 #define EXEC_BIOS_CMD_TABLE(fname, params)\
46− (cgs_atom_exec_cmd_table(bp->base.ctx->cgs_device, \
50+ (amdgpu_atom_execute_table(((struct amdgpu_device *)bp->base.ctx->driver_context)->mode_info.atom_context, \
4751 GET_INDEX_INTO_MASTER_TABLE(command, fname), \
48− &params) == 0)
52+ (uint32_t *)&params) == 0)
4953
5054 #define BIOS_CMD_TABLE_REVISION(fname, frev, crev)\
51− cgs_atom_get_cmd_table_revs(bp->base.ctx->cgs_device, \
55+ amdgpu_atom_parse_cmd_header(((struct amdgpu_device *)bp->base.ctx->driver_context)->mode_info.atom_context, \
5256 GET_INDEX_INTO_MASTER_TABLE(command, fname), &frev, &crev)
5357
5458 #define BIOS_CMD_TABLE_PARA_REVISION(fname)\
55− bios_cmd_table_para_revision(bp->base.ctx->cgs_device, \
59+ bios_cmd_table_para_revision(bp->base.ctx->driver_context, \
5660 GET_INDEX_INTO_MASTER_TABLE(command, fname))
5761
5862 static void init_dig_encoder_control(struct bios_parser *bp);
@@ -86,16 +90,18 @@ void dal_firmware_parser_init_cmd_tbl(struct bios_parser *bp) · 27 unmodified lines
8690 init_get_smu_clock_info(bp);
8791 }
8892
89−static uint32_t bios_cmd_table_para_revision(void *cgs_device,
93+static uint32_t bios_cmd_table_para_revision(void *dev,
9094 uint32_t index)
9195 {
96+ struct amdgpu_device *adev = dev;
9297 uint8_t frev, crev;
9398
94− if (cgs_atom_get_cmd_table_revs(cgs_device,
99+ if (amdgpu_atom_parse_cmd_header(adev->mode_info.atom_context,
95100 index,
96− &frev, &crev) != 0)
101+ &frev, &crev))
102+ return crev;
103+ else
97104 return 0;
98− return crev;
99105 }
100106
101107 /******************************************************************************
@@ -201,7 +207,7 @@ static void init_transmitter_control(struct bios_parser *bp) · 99 unmodified lines
201207 uint8_t frev;
202208 uint8_t crev;
203209
204− if (BIOS_CMD_TABLE_REVISION(dig1transmittercontrol, frev, crev) != 0)
210+ if (BIOS_CMD_TABLE_REVISION(dig1transmittercontrol, frev, crev) == false)
205211 BREAK_TO_DEBUGGER();
206212 switch (crev) {
207213 case 6:
drivers/gpu/drm/amd/display/dc/bios/command_table_helper.c+3−0
@@ -51,6 +51,9 @@ bool dal_bios_parser_init_cmd_tbl_helper( · 50 unmodified lines
5151 return true;
5252
5353 case DCE_VERSION_11_2:
54+#if defined(CONFIG_DRM_AMD_DC_VEGAM)
55+ case DCE_VERSION_11_22:
56+#endif
5457 *h = dal_cmd_tbl_helper_dce112_get_table();
5558 return true;
5659
drivers/gpu/drm/amd/display/dc/bios/command_table_helper2.c+3−0
@@ -52,6 +52,9 @@ bool dal_bios_parser_init_cmd_tbl_helper2( · 51 unmodified lines
5252 return true;
5353
5454 case DCE_VERSION_11_2:
55+#if defined(CONFIG_DRM_AMD_DC_VEGAM)
56+ case DCE_VERSION_11_22:
57+#endif
5558 *h = dal_cmd_tbl_helper_dce112_get_table2();
5659 return true;
5760 #if defined(CONFIG_DRM_AMD_DC_DCN1_0)
drivers/gpu/drm/amd/display/dc/calcs/calcs_logger.h+579−0
@@ -0,0 +1,579 @@
1+/*
2+ * Copyright 2018 Advanced Micro Devices, Inc.
3+ *
4+ * Permission is hereby granted, free of charge, to any person obtaining a
5+ * copy of this software and associated documentation files (the "Software"),
6+ * to deal in the Software without restriction, including without limitation
7+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8+ * and/or sell copies of the Software, and to permit persons to whom the
9+ * Software is furnished to do so, subject to the following conditions:
10+ *
11+ * The above copyright notice and this permission notice shall be included in
12+ * all copies or substantial portions of the Software.
13+ *
14+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20+ * OTHER DEALINGS IN THE SOFTWARE.
21+ *
22+ * Authors: AMD
23+ *
24+ */
25+
26+#ifndef _CALCS_CALCS_LOGGER_H_
27+#define _CALCS_CALCS_LOGGER_H_
28+#define DC_LOGGER \
29+ logger
30+
31+static void print_bw_calcs_dceip(struct dal_logger *logger, const struct bw_calcs_dceip *dceip)
32+{
33+
34+ DC_LOG_BANDWIDTH_CALCS("#####################################################################");
35+ DC_LOG_BANDWIDTH_CALCS("struct bw_calcs_dceip");
36+ DC_LOG_BANDWIDTH_CALCS("#####################################################################");
37+ DC_LOG_BANDWIDTH_CALCS(" [enum] bw_calcs_version version %d", dceip->version);
38+ DC_LOG_BANDWIDTH_CALCS(" [bool] large_cursor: %d", dceip->large_cursor);
39+ DC_LOG_BANDWIDTH_CALCS(" [bool] dmif_pipe_en_fbc_chunk_tracker: %d", dceip->dmif_pipe_en_fbc_chunk_tracker);
40+ DC_LOG_BANDWIDTH_CALCS(" [bool] display_write_back_supported: %d", dceip->display_write_back_supported);
41+ DC_LOG_BANDWIDTH_CALCS(" [bool] argb_compression_support: %d", dceip->argb_compression_support);
42+ DC_LOG_BANDWIDTH_CALCS(" [bool] pre_downscaler_enabled: %d", dceip->pre_downscaler_enabled);
43+ DC_LOG_BANDWIDTH_CALCS(" [bool] underlay_downscale_prefetch_enabled: %d",
44+ dceip->underlay_downscale_prefetch_enabled);
45+ DC_LOG_BANDWIDTH_CALCS(" [bool] graphics_lb_nodownscaling_multi_line_prefetching: %d",
46+ dceip->graphics_lb_nodownscaling_multi_line_prefetching);
47+ DC_LOG_BANDWIDTH_CALCS(" [bool] limit_excessive_outstanding_dmif_requests: %d",
48+ dceip->limit_excessive_outstanding_dmif_requests);
49+ DC_LOG_BANDWIDTH_CALCS(" [uint32_t] cursor_max_outstanding_group_num: %d",
50+ dceip->cursor_max_outstanding_group_num);
51+ DC_LOG_BANDWIDTH_CALCS(" [uint32_t] lines_interleaved_into_lb: %d", dceip->lines_interleaved_into_lb);
52+ DC_LOG_BANDWIDTH_CALCS(" [uint32_t] low_power_tiling_mode: %d", dceip->low_power_tiling_mode);
53+ DC_LOG_BANDWIDTH_CALCS(" [uint32_t] chunk_width: %d", dceip->chunk_width);
54+ DC_LOG_BANDWIDTH_CALCS(" [uint32_t] number_of_graphics_pipes: %d", dceip->number_of_graphics_pipes);
55+ DC_LOG_BANDWIDTH_CALCS(" [uint32_t] number_of_underlay_pipes: %d", dceip->number_of_underlay_pipes);
56+ DC_LOG_BANDWIDTH_CALCS(" [uint32_t] max_dmif_buffer_allocated: %d", dceip->max_dmif_buffer_allocated);
57+ DC_LOG_BANDWIDTH_CALCS(" [uint32_t] graphics_dmif_size: %d", dceip->graphics_dmif_size);
58+ DC_LOG_BANDWIDTH_CALCS(" [uint32_t] underlay_luma_dmif_size: %d", dceip->underlay_luma_dmif_size);
59+ DC_LOG_BANDWIDTH_CALCS(" [uint32_t] underlay_chroma_dmif_size: %d", dceip->underlay_chroma_dmif_size);
60+ DC_LOG_BANDWIDTH_CALCS(" [uint32_t] scatter_gather_lines_of_pte_prefetching_in_linear_mode: %d",
61+ dceip->scatter_gather_lines_of_pte_prefetching_in_linear_mode);
62+ DC_LOG_BANDWIDTH_CALCS(" [uint32_t] display_write_back420_luma_mcifwr_buffer_size: %d",
63+ dceip->display_write_back420_luma_mcifwr_buffer_size);
64+ DC_LOG_BANDWIDTH_CALCS(" [uint32_t] display_write_back420_chroma_mcifwr_buffer_size: %d",
65+ dceip->display_write_back420_chroma_mcifwr_buffer_size);
66+ DC_LOG_BANDWIDTH_CALCS(" [uint32_t] scatter_gather_pte_request_rows_in_tiling_mode: %d",
67+ dceip->scatter_gather_pte_request_rows_in_tiling_mode);
68+ DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] underlay_vscaler_efficiency10_bit_per_component: %d",
69+ bw_fixed_to_int(dceip->underlay_vscaler_efficiency10_bit_per_component));
70+ DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] underlay_vscaler_efficiency12_bit_per_component: %d",
71+ bw_fixed_to_int(dceip->underlay_vscaler_efficiency12_bit_per_component));
72+ DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] graphics_vscaler_efficiency6_bit_per_component: %d",
73+ bw_fixed_to_int(dceip->graphics_vscaler_efficiency6_bit_per_component));
74+ DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] graphics_vscaler_efficiency8_bit_per_component: %d",
75+ bw_fixed_to_int(dceip->graphics_vscaler_efficiency8_bit_per_component));
76+ DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] graphics_vscaler_efficiency10_bit_per_component: %d",
77+ bw_fixed_to_int(dceip->graphics_vscaler_efficiency10_bit_per_component));
78+ DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] graphics_vscaler_efficiency12_bit_per_component: %d",
79+ bw_fixed_to_int(dceip->graphics_vscaler_efficiency12_bit_per_component));
80+ DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] alpha_vscaler_efficiency: %d",
81+ bw_fixed_to_int(dceip->alpha_vscaler_efficiency));
82+ DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] lb_write_pixels_per_dispclk: %d",
83+ bw_fixed_to_int(dceip->lb_write_pixels_per_dispclk));
84+ DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] lb_size_per_component444: %d",
85+ bw_fixed_to_int(dceip->lb_size_per_component444));
86+ DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] stutter_and_dram_clock_state_change_gated_before_cursor: %d",
87+ bw_fixed_to_int(dceip->stutter_and_dram_clock_state_change_gated_before_cursor));
88+ DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] underlay420_luma_lb_size_per_component: %d",
89+ bw_fixed_to_int(dceip->underlay420_luma_lb_size_per_component));
90+ DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] underlay420_chroma_lb_size_per_component: %d",
91+ bw_fixed_to_int(dceip->underlay420_chroma_lb_size_per_component));
92+ DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] underlay422_lb_size_per_component: %d",
93+ bw_fixed_to_int(dceip->underlay422_lb_size_per_component));
94+ DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] cursor_chunk_width: %d", bw_fixed_to_int(dceip->cursor_chunk_width));
95+ DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] cursor_dcp_buffer_lines: %d",
96+ bw_fixed_to_int(dceip->cursor_dcp_buffer_lines));
97+ DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] underlay_maximum_width_efficient_for_tiling: %d",
98+ bw_fixed_to_int(dceip->underlay_maximum_width_efficient_for_tiling));
99+ DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] underlay_maximum_height_efficient_for_tiling: %d",
100+ bw_fixed_to_int(dceip->underlay_maximum_height_efficient_for_tiling));
101+ DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] peak_pte_request_to_eviction_ratio_limiting_multiple_displays_or_single_rotated_display: %d",
102+ bw_fixed_to_int(dceip->peak_pte_request_to_eviction_ratio_limiting_multiple_displays_or_single_rotated_display));
103+ DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] peak_pte_request_to_eviction_ratio_limiting_single_display_no_rotation: %d",
104+ bw_fixed_to_int(dceip->peak_pte_request_to_eviction_ratio_limiting_single_display_no_rotation));
105+ DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] minimum_outstanding_pte_request_limit: %d",
106+ bw_fixed_to_int(dceip->minimum_outstanding_pte_request_limit));
107+ DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] maximum_total_outstanding_pte_requests_allowed_by_saw: %d",
108+ bw_fixed_to_int(dceip->maximum_total_outstanding_pte_requests_allowed_by_saw));
109+ DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] linear_mode_line_request_alternation_slice: %d",
110+ bw_fixed_to_int(dceip->linear_mode_line_request_alternation_slice));
111+ DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] request_efficiency: %d", bw_fixed_to_int(dceip->request_efficiency));
112+ DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] dispclk_per_request: %d", bw_fixed_to_int(dceip->dispclk_per_request));
113+ DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] dispclk_ramping_factor: %d",
114+ bw_fixed_to_int(dceip->dispclk_ramping_factor));
115+ DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] display_pipe_throughput_factor: %d",
116+ bw_fixed_to_int(dceip->display_pipe_throughput_factor));
117+ DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] mcifwr_all_surfaces_burst_time: %d",
118+ bw_fixed_to_int(dceip->mcifwr_all_surfaces_burst_time));
119+ DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] dmif_request_buffer_size: %d",
120+ bw_fixed_to_int(dceip->dmif_request_buffer_size));
121+
122+
123+}
124+
125+static void print_bw_calcs_vbios(struct dal_logger *logger, const struct bw_calcs_vbios *vbios)
126+{
127+
128+ DC_LOG_BANDWIDTH_CALCS("#####################################################################");
129+ DC_LOG_BANDWIDTH_CALCS("struct bw_calcs_vbios vbios");
130+ DC_LOG_BANDWIDTH_CALCS("#####################################################################");
131+ DC_LOG_BANDWIDTH_CALCS(" [enum] bw_defines memory_type: %d", vbios->memory_type);
132+ DC_LOG_BANDWIDTH_CALCS(" [enum] bw_defines memory_type: %d", vbios->memory_type);
133+ DC_LOG_BANDWIDTH_CALCS(" [uint32_t] dram_channel_width_in_bits: %d", vbios->dram_channel_width_in_bits);
134+ DC_LOG_BANDWIDTH_CALCS(" [uint32_t] number_of_dram_channels: %d", vbios->number_of_dram_channels);
135+ DC_LOG_BANDWIDTH_CALCS(" [uint32_t] number_of_dram_banks: %d", vbios->number_of_dram_banks);
136+ DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] low_yclk: %d", bw_fixed_to_int(vbios->low_yclk));
137+ DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] mid_yclk: %d", bw_fixed_to_int(vbios->mid_yclk));
138+ DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] high_yclk: %d", bw_fixed_to_int(vbios->high_yclk));
139+ DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] low_sclk: %d", bw_fixed_to_int(vbios->low_sclk));
140+ DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] mid1_sclk: %d", bw_fixed_to_int(vbios->mid1_sclk));
141+ DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] mid2_sclk: %d", bw_fixed_to_int(vbios->mid2_sclk));
142+ DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] mid3_sclk: %d", bw_fixed_to_int(vbios->mid3_sclk));
143+ DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] mid4_sclk: %d", bw_fixed_to_int(vbios->mid4_sclk));
144+ DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] mid5_sclk: %d", bw_fixed_to_int(vbios->mid5_sclk));
145+ DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] mid6_sclk: %d", bw_fixed_to_int(vbios->mid6_sclk));
146+ DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] high_sclk: %d", bw_fixed_to_int(vbios->high_sclk));
147+ DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] low_voltage_max_dispclk: %d",
148+ bw_fixed_to_int(vbios->low_voltage_max_dispclk));
149+ DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] mid_voltage_max_dispclk;: %d",
150+ bw_fixed_to_int(vbios->mid_voltage_max_dispclk));
151+ DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] high_voltage_max_dispclk;: %d",
152+ bw_fixed_to_int(vbios->high_voltage_max_dispclk));
153+ DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] low_voltage_max_phyclk: %d",
154+ bw_fixed_to_int(vbios->low_voltage_max_phyclk));
155+ DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] mid_voltage_max_phyclk: %d",
156+ bw_fixed_to_int(vbios->mid_voltage_max_phyclk));
157+ DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] high_voltage_max_phyclk: %d",
158+ bw_fixed_to_int(vbios->high_voltage_max_phyclk));
159+ DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] data_return_bus_width: %d", bw_fixed_to_int(vbios->data_return_bus_width));
160+ DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] trc: %d", bw_fixed_to_int(vbios->trc));
161+ DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] dmifmc_urgent_latency: %d", bw_fixed_to_int(vbios->dmifmc_urgent_latency));
162+ DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] stutter_self_refresh_exit_latency: %d",
163+ bw_fixed_to_int(vbios->stutter_self_refresh_exit_latency));
164+ DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] stutter_self_refresh_entry_latency: %d",
165+ bw_fixed_to_int(vbios->stutter_self_refresh_entry_latency));
166+ DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] nbp_state_change_latency: %d",
167+ bw_fixed_to_int(vbios->nbp_state_change_latency));
168+ DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] mcifwrmc_urgent_latency: %d",
169+ bw_fixed_to_int(vbios->mcifwrmc_urgent_latency));
170+ DC_LOG_BANDWIDTH_CALCS(" [bool] scatter_gather_enable: %d", vbios->scatter_gather_enable);
171+ DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] down_spread_percentage: %d",
172+ bw_fixed_to_int(vbios->down_spread_percentage));
173+ DC_LOG_BANDWIDTH_CALCS(" [uint32_t] cursor_width: %d", vbios->cursor_width);
174+ DC_LOG_BANDWIDTH_CALCS(" [uint32_t] average_compression_rate: %d", vbios->average_compression_rate);
175+ DC_LOG_BANDWIDTH_CALCS(" [uint32_t] number_of_request_slots_gmc_reserves_for_dmif_per_channel: %d",
176+ vbios->number_of_request_slots_gmc_reserves_for_dmif_per_channel);
177+ DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] blackout_duration: %d", bw_fixed_to_int(vbios->blackout_duration));
178+ DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] maximum_blackout_recovery_time: %d",
179+ bw_fixed_to_int(vbios->maximum_blackout_recovery_time));
180+
181+
182+}
183+
184+static void print_bw_calcs_data(struct dal_logger *logger, struct bw_calcs_data *data)
185+{
186+
187+ int i, j, k;
188+
189+ DC_LOG_BANDWIDTH_CALCS("#####################################################################");
190+ DC_LOG_BANDWIDTH_CALCS("struct bw_calcs_data data");
191+ DC_LOG_BANDWIDTH_CALCS("#####################################################################");
192+ DC_LOG_BANDWIDTH_CALCS(" [uint32_t] number_of_displays: %d", data->number_of_displays);
193+ DC_LOG_BANDWIDTH_CALCS(" [enum] bw_defines underlay_surface_type: %d", data->underlay_surface_type);
194+ DC_LOG_BANDWIDTH_CALCS(" [enum] bw_defines panning_and_bezel_adjustment: %d",
195+ data->panning_and_bezel_adjustment);
196+ DC_LOG_BANDWIDTH_CALCS(" [enum] bw_defines graphics_tiling_mode: %d", data->graphics_tiling_mode);
197+ DC_LOG_BANDWIDTH_CALCS(" [uint32_t] graphics_lb_bpc: %d", data->graphics_lb_bpc);
198+ DC_LOG_BANDWIDTH_CALCS(" [uint32_t] underlay_lb_bpc: %d", data->underlay_lb_bpc);
199+ DC_LOG_BANDWIDTH_CALCS(" [enum] bw_defines underlay_tiling_mode: %d", data->underlay_tiling_mode);
200+ DC_LOG_BANDWIDTH_CALCS(" [enum] bw_defines d0_underlay_mode: %d", data->d0_underlay_mode);
201+ DC_LOG_BANDWIDTH_CALCS(" [bool] d1_display_write_back_dwb_enable: %d", data->d1_display_write_back_dwb_enable);
202+ DC_LOG_BANDWIDTH_CALCS(" [enum] bw_defines d1_underlay_mode: %d", data->d1_underlay_mode);
203+ DC_LOG_BANDWIDTH_CALCS(" [bool] cpup_state_change_enable: %d", data->cpup_state_change_enable);
204+ DC_LOG_BANDWIDTH_CALCS(" [bool] cpuc_state_change_enable: %d", data->cpuc_state_change_enable);
205+ DC_LOG_BANDWIDTH_CALCS(" [bool] nbp_state_change_enable: %d", data->nbp_state_change_enable);
206+ DC_LOG_BANDWIDTH_CALCS(" [bool] stutter_mode_enable: %d", data->stutter_mode_enable);
207+ DC_LOG_BANDWIDTH_CALCS(" [uint32_t] y_clk_level: %d", data->y_clk_level);
208+ DC_LOG_BANDWIDTH_CALCS(" [uint32_t] sclk_level: %d", data->sclk_level);
209+ DC_LOG_BANDWIDTH_CALCS(" [uint32_t] number_of_underlay_surfaces: %d", data->number_of_underlay_surfaces);
210+ DC_LOG_BANDWIDTH_CALCS(" [uint32_t] number_of_dram_wrchannels: %d", data->number_of_dram_wrchannels);
211+ DC_LOG_BANDWIDTH_CALCS(" [uint32_t] chunk_request_delay: %d", data->chunk_request_delay);
212+ DC_LOG_BANDWIDTH_CALCS(" [uint32_t] number_of_dram_channels: %d", data->number_of_dram_channels);
213+ DC_LOG_BANDWIDTH_CALCS(" [enum] bw_defines underlay_micro_tile_mode: %d", data->underlay_micro_tile_mode);
214+ DC_LOG_BANDWIDTH_CALCS(" [enum] bw_defines graphics_micro_tile_mode: %d", data->graphics_micro_tile_mode);
215+ DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] max_phyclk: %d", bw_fixed_to_int(data->max_phyclk));
216+ DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] dram_efficiency: %d", bw_fixed_to_int(data->dram_efficiency));
217+ DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] src_width_after_surface_type: %d",
218+ bw_fixed_to_int(data->src_width_after_surface_type));
219+ DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] src_height_after_surface_type: %d",
220+ bw_fixed_to_int(data->src_height_after_surface_type));
221+ DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] hsr_after_surface_type: %d",
222+ bw_fixed_to_int(data->hsr_after_surface_type));
223+ DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] vsr_after_surface_type: %d", bw_fixed_to_int(data->vsr_after_surface_type));
224+ DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] src_width_after_rotation: %d",
225+ bw_fixed_to_int(data->src_width_after_rotation));
226+ DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] src_height_after_rotation: %d",
227+ bw_fixed_to_int(data->src_height_after_rotation));
228+ DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] hsr_after_rotation: %d", bw_fixed_to_int(data->hsr_after_rotation));
229+ DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] vsr_after_rotation: %d", bw_fixed_to_int(data->vsr_after_rotation));
230+ DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] source_height_pixels: %d", bw_fixed_to_int(data->source_height_pixels));
231+ DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] hsr_after_stereo: %d", bw_fixed_to_int(data->hsr_after_stereo));
232+ DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] vsr_after_stereo: %d", bw_fixed_to_int(data->vsr_after_stereo));
233+ DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] source_width_in_lb: %d", bw_fixed_to_int(data->source_width_in_lb));
234+ DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] lb_line_pitch: %d", bw_fixed_to_int(data->lb_line_pitch));
235+ DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] underlay_maximum_source_efficient_for_tiling: %d",
236+ bw_fixed_to_int(data->underlay_maximum_source_efficient_for_tiling));
237+ DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] num_lines_at_frame_start: %d",
238+ bw_fixed_to_int(data->num_lines_at_frame_start));
239+ DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] min_dmif_size_in_time: %d", bw_fixed_to_int(data->min_dmif_size_in_time));
240+ DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] min_mcifwr_size_in_time: %d",
241+ bw_fixed_to_int(data->min_mcifwr_size_in_time));
242+ DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] total_requests_for_dmif_size: %d",
243+ bw_fixed_to_int(data->total_requests_for_dmif_size));
244+ DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] peak_pte_request_to_eviction_ratio_limiting: %d",
245+ bw_fixed_to_int(data->peak_pte_request_to_eviction_ratio_limiting));
246+ DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] useful_pte_per_pte_request: %d",
247+ bw_fixed_to_int(data->useful_pte_per_pte_request));
248+ DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] scatter_gather_pte_request_rows: %d",
249+ bw_fixed_to_int(data->scatter_gather_pte_request_rows));
250+ DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] scatter_gather_row_height: %d",
251+ bw_fixed_to_int(data->scatter_gather_row_height));
252+ DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] scatter_gather_pte_requests_in_vblank: %d",
253+ bw_fixed_to_int(data->scatter_gather_pte_requests_in_vblank));
254+ DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] inefficient_linear_pitch_in_bytes: %d",
255+ bw_fixed_to_int(data->inefficient_linear_pitch_in_bytes));
256+ DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] cursor_total_data: %d", bw_fixed_to_int(data->cursor_total_data));
257+ DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] cursor_total_request_groups: %d",
258+ bw_fixed_to_int(data->cursor_total_request_groups));
259+ DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] scatter_gather_total_pte_requests: %d",
260+ bw_fixed_to_int(data->scatter_gather_total_pte_requests));
261+ DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] scatter_gather_total_pte_request_groups: %d",
262+ bw_fixed_to_int(data->scatter_gather_total_pte_request_groups));
263+ DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] tile_width_in_pixels: %d", bw_fixed_to_int(data->tile_width_in_pixels));
264+ DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] dmif_total_number_of_data_request_page_close_open: %d",
265+ bw_fixed_to_int(data->dmif_total_number_of_data_request_page_close_open));
266+ DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] mcifwr_total_number_of_data_request_page_close_open: %d",
267+ bw_fixed_to_int(data->mcifwr_total_number_of_data_request_page_close_open));
268+ DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] bytes_per_page_close_open: %d",
269+ bw_fixed_to_int(data->bytes_per_page_close_open));
270+ DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] mcifwr_total_page_close_open_time: %d",
271+ bw_fixed_to_int(data->mcifwr_total_page_close_open_time));
272+ DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] total_requests_for_adjusted_dmif_size: %d",
273+ bw_fixed_to_int(data->total_requests_for_adjusted_dmif_size));
274+ DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] total_dmifmc_urgent_trips: %d",
275+ bw_fixed_to_int(data->total_dmifmc_urgent_trips));
276+ DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] total_dmifmc_urgent_latency: %d",
277+ bw_fixed_to_int(data->total_dmifmc_urgent_latency));
278+ DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] total_display_reads_required_data: %d",
279+ bw_fixed_to_int(data->total_display_reads_required_data));
280+ DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] total_display_reads_required_dram_access_data: %d",
281+ bw_fixed_to_int(data->total_display_reads_required_dram_access_data));
282+ DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] total_display_writes_required_data: %d",
283+ bw_fixed_to_int(data->total_display_writes_required_data));
284+ DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] total_display_writes_required_dram_access_data: %d",
285+ bw_fixed_to_int(data->total_display_writes_required_dram_access_data));
286+ DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] display_reads_required_data: %d",
287+ bw_fixed_to_int(data->display_reads_required_data));
288+ DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] display_reads_required_dram_access_data: %d",
289+ bw_fixed_to_int(data->display_reads_required_dram_access_data));
290+ DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] dmif_total_page_close_open_time: %d",
291+ bw_fixed_to_int(data->dmif_total_page_close_open_time));
292+ DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] min_cursor_memory_interface_buffer_size_in_time: %d",
293+ bw_fixed_to_int(data->min_cursor_memory_interface_buffer_size_in_time));
294+ DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] min_read_buffer_size_in_time: %d",
295+ bw_fixed_to_int(data->min_read_buffer_size_in_time));
296+ DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] display_reads_time_for_data_transfer: %d",
297+ bw_fixed_to_int(data->display_reads_time_for_data_transfer));
298+ DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] display_writes_time_for_data_transfer: %d",
299+ bw_fixed_to_int(data->display_writes_time_for_data_transfer));
300+ DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] dmif_required_dram_bandwidth: %d",
301+ bw_fixed_to_int(data->dmif_required_dram_bandwidth));
302+ DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] mcifwr_required_dram_bandwidth: %d",
303+ bw_fixed_to_int(data->mcifwr_required_dram_bandwidth));
304+ DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] required_dmifmc_urgent_latency_for_page_close_open: %d",
305+ bw_fixed_to_int(data->required_dmifmc_urgent_latency_for_page_close_open));
306+ DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] required_mcifmcwr_urgent_latency: %d",
307+ bw_fixed_to_int(data->required_mcifmcwr_urgent_latency));
308+ DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] required_dram_bandwidth_gbyte_per_second: %d",
309+ bw_fixed_to_int(data->required_dram_bandwidth_gbyte_per_second));
310+ DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] dram_bandwidth: %d", bw_fixed_to_int(data->dram_bandwidth));
311+ DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] dmif_required_sclk: %d", bw_fixed_to_int(data->dmif_required_sclk));
312+ DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] mcifwr_required_sclk: %d", bw_fixed_to_int(data->mcifwr_required_sclk));
313+ DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] required_sclk: %d", bw_fixed_to_int(data->required_sclk));
314+ DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] downspread_factor: %d", bw_fixed_to_int(data->downspread_factor));
315+ DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] v_scaler_efficiency: %d", bw_fixed_to_int(data->v_scaler_efficiency));
316+ DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] scaler_limits_factor: %d", bw_fixed_to_int(data->scaler_limits_factor));
317+ DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] display_pipe_pixel_throughput: %d",
318+ bw_fixed_to_int(data->display_pipe_pixel_throughput));
319+ DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] total_dispclk_required_with_ramping: %d",
320+ bw_fixed_to_int(data->total_dispclk_required_with_ramping));
321+ DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] total_dispclk_required_without_ramping: %d",
322+ bw_fixed_to_int(data->total_dispclk_required_without_ramping));
323+ DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] total_read_request_bandwidth: %d",
324+ bw_fixed_to_int(data->total_read_request_bandwidth));
325+ DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] total_write_request_bandwidth: %d",
326+ bw_fixed_to_int(data->total_write_request_bandwidth));
327+ DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] dispclk_required_for_total_read_request_bandwidth: %d",
328+ bw_fixed_to_int(data->dispclk_required_for_total_read_request_bandwidth));
329+ DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] total_dispclk_required_with_ramping_with_request_bandwidth: %d",
330+ bw_fixed_to_int(data->total_dispclk_required_with_ramping_with_request_bandwidth));
331+ DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] total_dispclk_required_without_ramping_with_request_bandwidth: %d",
332+ bw_fixed_to_int(data->total_dispclk_required_without_ramping_with_request_bandwidth));
333+ DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] dispclk: %d", bw_fixed_to_int(data->dispclk));
334+ DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] blackout_recovery_time: %d", bw_fixed_to_int(data->blackout_recovery_time));
335+ DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] min_pixels_per_data_fifo_entry: %d",
336+ bw_fixed_to_int(data->min_pixels_per_data_fifo_entry));
337+ DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] sclk_deep_sleep: %d", bw_fixed_to_int(data->sclk_deep_sleep));
338+ DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] chunk_request_time: %d", bw_fixed_to_int(data->chunk_request_time));
339+ DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] cursor_request_time: %d", bw_fixed_to_int(data->cursor_request_time));
340+ DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] line_source_pixels_transfer_time: %d",
341+ bw_fixed_to_int(data->line_source_pixels_transfer_time));
342+ DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] dmifdram_access_efficiency: %d",
343+ bw_fixed_to_int(data->dmifdram_access_efficiency));
344+ DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] mcifwrdram_access_efficiency: %d",
345+ bw_fixed_to_int(data->mcifwrdram_access_efficiency));
346+ DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] total_average_bandwidth_no_compression: %d",
347+ bw_fixed_to_int(data->total_average_bandwidth_no_compression));
348+ DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] total_average_bandwidth: %d",
349+ bw_fixed_to_int(data->total_average_bandwidth));
350+ DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] total_stutter_cycle_duration: %d",
351+ bw_fixed_to_int(data->total_stutter_cycle_duration));
352+ DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] stutter_burst_time: %d", bw_fixed_to_int(data->stutter_burst_time));
353+ DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] time_in_self_refresh: %d", bw_fixed_to_int(data->time_in_self_refresh));
354+ DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] stutter_efficiency: %d", bw_fixed_to_int(data->stutter_efficiency));
355+ DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] worst_number_of_trips_to_memory: %d",
356+ bw_fixed_to_int(data->worst_number_of_trips_to_memory));
357+ DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] immediate_flip_time: %d", bw_fixed_to_int(data->immediate_flip_time));
358+ DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] latency_for_non_dmif_clients: %d",
359+ bw_fixed_to_int(data->latency_for_non_dmif_clients));
360+ DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] latency_for_non_mcifwr_clients: %d",
361+ bw_fixed_to_int(data->latency_for_non_mcifwr_clients));
362+ DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] dmifmc_urgent_latency_supported_in_high_sclk_and_yclk: %d",
363+ bw_fixed_to_int(data->dmifmc_urgent_latency_supported_in_high_sclk_and_yclk));
364+ DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] nbp_state_dram_speed_change_margin: %d",
365+ bw_fixed_to_int(data->nbp_state_dram_speed_change_margin));
366+ DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] display_reads_time_for_data_transfer_and_urgent_latency: %d",
367+ bw_fixed_to_int(data->display_reads_time_for_data_transfer_and_urgent_latency));
368+ DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] dram_speed_change_margin: %d",
369+ bw_fixed_to_int(data->dram_speed_change_margin));
370+ DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] min_vblank_dram_speed_change_margin: %d",
371+ bw_fixed_to_int(data->min_vblank_dram_speed_change_margin));
372+ DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] min_stutter_refresh_duration: %d",
373+ bw_fixed_to_int(data->min_stutter_refresh_duration));
374+ DC_LOG_BANDWIDTH_CALCS(" [uint32_t] total_stutter_dmif_buffer_size: %d", data->total_stutter_dmif_buffer_size);
375+ DC_LOG_BANDWIDTH_CALCS(" [uint32_t] total_bytes_requested: %d", data->total_bytes_requested);
376+ DC_LOG_BANDWIDTH_CALCS(" [uint32_t] min_stutter_dmif_buffer_size: %d", data->min_stutter_dmif_buffer_size);
377+ DC_LOG_BANDWIDTH_CALCS(" [uint32_t] num_stutter_bursts: %d", data->num_stutter_bursts);
378+ DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] v_blank_nbp_state_dram_speed_change_latency_supported: %d",
379+ bw_fixed_to_int(data->v_blank_nbp_state_dram_speed_change_latency_supported));
380+ DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] nbp_state_dram_speed_change_latency_supported: %d",
381+ bw_fixed_to_int(data->nbp_state_dram_speed_change_latency_supported));
382+
383+ for (i = 0; i < maximum_number_of_surfaces; i++) {
384+ DC_LOG_BANDWIDTH_CALCS(" [bool] fbc_en[%d]:%d\n", i, data->fbc_en[i]);
385+ DC_LOG_BANDWIDTH_CALCS(" [bool] lpt_en[%d]:%d", i, data->lpt_en[i]);
386+ DC_LOG_BANDWIDTH_CALCS(" [bool] displays_match_flag[%d]:%d", i, data->displays_match_flag[i]);
387+ DC_LOG_BANDWIDTH_CALCS(" [bool] use_alpha[%d]:%d", i, data->use_alpha[i]);
388+ DC_LOG_BANDWIDTH_CALCS(" [bool] orthogonal_rotation[%d]:%d", i, data->orthogonal_rotation[i]);
389+ DC_LOG_BANDWIDTH_CALCS(" [bool] enable[%d]:%d", i, data->enable[i]);
390+ DC_LOG_BANDWIDTH_CALCS(" [bool] access_one_channel_only[%d]:%d", i, data->access_one_channel_only[i]);
391+ DC_LOG_BANDWIDTH_CALCS(" [bool] scatter_gather_enable_for_pipe[%d]:%d",
392+ i, data->scatter_gather_enable_for_pipe[i]);
393+ DC_LOG_BANDWIDTH_CALCS(" [bool] interlace_mode[%d]:%d",
394+ i, data->interlace_mode[i]);
395+ DC_LOG_BANDWIDTH_CALCS(" [bool] display_pstate_change_enable[%d]:%d",
396+ i, data->display_pstate_change_enable[i]);
397+ DC_LOG_BANDWIDTH_CALCS(" [bool] line_buffer_prefetch[%d]:%d", i, data->line_buffer_prefetch[i]);
398+ DC_LOG_BANDWIDTH_CALCS(" [uint32_t] bytes_per_pixel[%d]:%d", i, data->bytes_per_pixel[i]);
399+ DC_LOG_BANDWIDTH_CALCS(" [uint32_t] max_chunks_non_fbc_mode[%d]:%d",
400+ i, data->max_chunks_non_fbc_mode[i]);
401+ DC_LOG_BANDWIDTH_CALCS(" [uint32_t] lb_bpc[%d]:%d", i, data->lb_bpc[i]);
402+ DC_LOG_BANDWIDTH_CALCS(" [uint32_t] output_bpphdmi[%d]:%d", i, data->output_bpphdmi[i]);
403+ DC_LOG_BANDWIDTH_CALCS(" [uint32_t] output_bppdp4_lane_hbr[%d]:%d", i, data->output_bppdp4_lane_hbr[i]);
404+ DC_LOG_BANDWIDTH_CALCS(" [uint32_t] output_bppdp4_lane_hbr2[%d]:%d",
405+ i, data->output_bppdp4_lane_hbr2[i]);
406+ DC_LOG_BANDWIDTH_CALCS(" [uint32_t] output_bppdp4_lane_hbr3[%d]:%d",
407+ i, data->output_bppdp4_lane_hbr3[i]);
408+ DC_LOG_BANDWIDTH_CALCS(" [enum] bw_defines stereo_mode[%d]:%d", i, data->stereo_mode[i]);
409+ DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] dmif_buffer_transfer_time[%d]:%d",
410+ i, bw_fixed_to_int(data->dmif_buffer_transfer_time[i]));
411+ DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] displays_with_same_mode[%d]:%d",
412+ i, bw_fixed_to_int(data->displays_with_same_mode[i]));
413+ DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] stutter_dmif_buffer_size[%d]:%d",
414+ i, bw_fixed_to_int(data->stutter_dmif_buffer_size[i]));
415+ DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] stutter_refresh_duration[%d]:%d",
416+ i, bw_fixed_to_int(data->stutter_refresh_duration[i]));
417+ DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] stutter_exit_watermark[%d]:%d",
418+ i, bw_fixed_to_int(data->stutter_exit_watermark[i]));
419+ DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] stutter_entry_watermark[%d]:%d",
420+ i, bw_fixed_to_int(data->stutter_entry_watermark[i]));
421+ DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] h_total[%d]:%d", i, bw_fixed_to_int(data->h_total[i]));
422+ DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] v_total[%d]:%d", i, bw_fixed_to_int(data->v_total[i]));
423+ DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] pixel_rate[%d]:%d", i, bw_fixed_to_int(data->pixel_rate[i]));
424+ DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] src_width[%d]:%d", i, bw_fixed_to_int(data->src_width[i]));
425+ DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] pitch_in_pixels[%d]:%d",
426+ i, bw_fixed_to_int(data->pitch_in_pixels[i]));
427+ DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] pitch_in_pixels_after_surface_type[%d]:%d",
428+ i, bw_fixed_to_int(data->pitch_in_pixels_after_surface_type[i]));
429+ DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] src_height[%d]:%d", i, bw_fixed_to_int(data->src_height[i]));
430+ DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] scale_ratio[%d]:%d", i, bw_fixed_to_int(data->scale_ratio[i]));
431+ DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] h_taps[%d]:%d", i, bw_fixed_to_int(data->h_taps[i]));
432+ DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] v_taps[%d]:%d", i, bw_fixed_to_int(data->v_taps[i]));
433+ DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] h_scale_ratio[%d]:%d", i, bw_fixed_to_int(data->h_scale_ratio[i]));
434+ DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] v_scale_ratio[%d]:%d", i, bw_fixed_to_int(data->v_scale_ratio[i]));
435+ DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] rotation_angle[%d]:%d",
436+ i, bw_fixed_to_int(data->rotation_angle[i]));
437+ DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] compression_rate[%d]:%d",
438+ i, bw_fixed_to_int(data->compression_rate[i]));
439+ DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] hsr[%d]:%d", i, bw_fixed_to_int(data->hsr[i]));
440+ DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] vsr[%d]:%d", i, bw_fixed_to_int(data->vsr[i]));
441+ DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] source_width_rounded_up_to_chunks[%d]:%d",
442+ i, bw_fixed_to_int(data->source_width_rounded_up_to_chunks[i]));
443+ DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] source_width_pixels[%d]:%d",
444+ i, bw_fixed_to_int(data->source_width_pixels[i]));
445+ DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] source_height_rounded_up_to_chunks[%d]:%d",
446+ i, bw_fixed_to_int(data->source_height_rounded_up_to_chunks[i]));
447+ DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] display_bandwidth[%d]:%d",
448+ i, bw_fixed_to_int(data->display_bandwidth[i]));
449+ DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] request_bandwidth[%d]:%d",
450+ i, bw_fixed_to_int(data->request_bandwidth[i]));
451+ DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] bytes_per_request[%d]:%d",
452+ i, bw_fixed_to_int(data->bytes_per_request[i]));
453+ DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] useful_bytes_per_request[%d]:%d",
454+ i, bw_fixed_to_int(data->useful_bytes_per_request[i]));
455+ DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] lines_interleaved_in_mem_access[%d]:%d",
456+ i, bw_fixed_to_int(data->lines_interleaved_in_mem_access[i]));
457+ DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] latency_hiding_lines[%d]:%d",
458+ i, bw_fixed_to_int(data->latency_hiding_lines[i]));
459+ DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] lb_partitions[%d]:%d",
460+ i, bw_fixed_to_int(data->lb_partitions[i]));
461+ DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] lb_partitions_max[%d]:%d",
462+ i, bw_fixed_to_int(data->lb_partitions_max[i]));
463+ DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] dispclk_required_with_ramping[%d]:%d",
464+ i, bw_fixed_to_int(data->dispclk_required_with_ramping[i]));
465+ DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] dispclk_required_without_ramping[%d]:%d",
466+ i, bw_fixed_to_int(data->dispclk_required_without_ramping[i]));
467+ DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] data_buffer_size[%d]:%d",
468+ i, bw_fixed_to_int(data->data_buffer_size[i]));
469+ DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] outstanding_chunk_request_limit[%d]:%d",
470+ i, bw_fixed_to_int(data->outstanding_chunk_request_limit[i]));
471+ DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] urgent_watermark[%d]:%d",
472+ i, bw_fixed_to_int(data->urgent_watermark[i]));
473+ DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] nbp_state_change_watermark[%d]:%d",
474+ i, bw_fixed_to_int(data->nbp_state_change_watermark[i]));
475+ DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] v_filter_init[%d]:%d", i, bw_fixed_to_int(data->v_filter_init[i]));
476+ DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] stutter_cycle_duration[%d]:%d",
477+ i, bw_fixed_to_int(data->stutter_cycle_duration[i]));
478+ DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] average_bandwidth[%d]:%d",
479+ i, bw_fixed_to_int(data->average_bandwidth[i]));
480+ DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] average_bandwidth_no_compression[%d]:%d",
481+ i, bw_fixed_to_int(data->average_bandwidth_no_compression[i]));
482+ DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] scatter_gather_pte_request_limit[%d]:%d",
483+ i, bw_fixed_to_int(data->scatter_gather_pte_request_limit[i]));
484+ DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] lb_size_per_component[%d]:%d",
485+ i, bw_fixed_to_int(data->lb_size_per_component[i]));
486+ DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] memory_chunk_size_in_bytes[%d]:%d",
487+ i, bw_fixed_to_int(data->memory_chunk_size_in_bytes[i]));
488+ DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] pipe_chunk_size_in_bytes[%d]:%d",
489+ i, bw_fixed_to_int(data->pipe_chunk_size_in_bytes[i]));
490+ DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] number_of_trips_to_memory_for_getting_apte_row[%d]:%d",
491+ i, bw_fixed_to_int(data->number_of_trips_to_memory_for_getting_apte_row[i]));
492+ DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] adjusted_data_buffer_size[%d]:%d",
493+ i, bw_fixed_to_int(data->adjusted_data_buffer_size[i]));
494+ DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] adjusted_data_buffer_size_in_memory[%d]:%d",
495+ i, bw_fixed_to_int(data->adjusted_data_buffer_size_in_memory[i]));
496+ DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] pixels_per_data_fifo_entry[%d]:%d",
497+ i, bw_fixed_to_int(data->pixels_per_data_fifo_entry[i]));
498+ DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] scatter_gather_pte_requests_in_row[%d]:%d",
499+ i, bw_fixed_to_int(data->scatter_gather_pte_requests_in_row[i]));
500+ DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] pte_request_per_chunk[%d]:%d",
501+ i, bw_fixed_to_int(data->pte_request_per_chunk[i]));
502+ DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] scatter_gather_page_width[%d]:%d",
503+ i, bw_fixed_to_int(data->scatter_gather_page_width[i]));
504+ DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] scatter_gather_page_height[%d]:%d",
505+ i, bw_fixed_to_int(data->scatter_gather_page_height[i]));
506+ DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] lb_lines_in_per_line_out_in_beginning_of_frame[%d]:%d",
507+ i, bw_fixed_to_int(data->lb_lines_in_per_line_out_in_beginning_of_frame[i]));
508+ DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] lb_lines_in_per_line_out_in_middle_of_frame[%d]:%d",
509+ i, bw_fixed_to_int(data->lb_lines_in_per_line_out_in_middle_of_frame[i]));
510+ DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] cursor_width_pixels[%d]:%d",
511+ i, bw_fixed_to_int(data->cursor_width_pixels[i]));
512+ DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] minimum_latency_hiding[%d]:%d",
513+ i, bw_fixed_to_int(data->minimum_latency_hiding[i]));
514+ DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] maximum_latency_hiding[%d]:%d",
515+ i, bw_fixed_to_int(data->maximum_latency_hiding[i]));
516+ DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] minimum_latency_hiding_with_cursor[%d]:%d",
517+ i, bw_fixed_to_int(data->minimum_latency_hiding_with_cursor[i]));
518+ DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] maximum_latency_hiding_with_cursor[%d]:%d",
519+ i, bw_fixed_to_int(data->maximum_latency_hiding_with_cursor[i]));
520+ DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] src_pixels_for_first_output_pixel[%d]:%d",
521+ i, bw_fixed_to_int(data->src_pixels_for_first_output_pixel[i]));
522+ DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] src_pixels_for_last_output_pixel[%d]:%d",
523+ i, bw_fixed_to_int(data->src_pixels_for_last_output_pixel[i]));
524+ DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] src_data_for_first_output_pixel[%d]:%d",
525+ i, bw_fixed_to_int(data->src_data_for_first_output_pixel[i]));
526+ DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] src_data_for_last_output_pixel[%d]:%d",
527+ i, bw_fixed_to_int(data->src_data_for_last_output_pixel[i]));
528+ DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] active_time[%d]:%d", i, bw_fixed_to_int(data->active_time[i]));
529+ DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] horizontal_blank_and_chunk_granularity_factor[%d]:%d",
530+ i, bw_fixed_to_int(data->horizontal_blank_and_chunk_granularity_factor[i]));
531+ DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] cursor_latency_hiding[%d]:%d",
532+ i, bw_fixed_to_int(data->cursor_latency_hiding[i]));
533+ DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] v_blank_dram_speed_change_margin[%d]:%d",
534+ i, bw_fixed_to_int(data->v_blank_dram_speed_change_margin[i]));
535+ }
536+
537+ for (i = 0; i < maximum_number_of_surfaces; i++) {
538+ for (j = 0; j < 3; j++) {
539+ for (k = 0; k < 8; k++) {
540+
541+ DC_LOG_BANDWIDTH_CALCS("\n [bw_fixed] line_source_transfer_time[%d][%d][%d]:%d",
542+ i, j, k, bw_fixed_to_int(data->line_source_transfer_time[i][j][k]));
543+ DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] dram_speed_change_line_source_transfer_time[%d][%d][%d]:%d",
544+ i, j, k,
545+ bw_fixed_to_int(data->dram_speed_change_line_source_transfer_time[i][j][k]));
546+ }
547+ }
548+ }
549+
550+ for (i = 0; i < 3; i++) {
551+ for (j = 0; j < 8; j++) {
552+
553+ DC_LOG_BANDWIDTH_CALCS("\n [uint32_t] num_displays_with_margin[%d][%d]:%d",
554+ i, j, data->num_displays_with_margin[i][j]);
555+ DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] dmif_burst_time[%d][%d]:%d",
556+ i, j, bw_fixed_to_int(data->dmif_burst_time[i][j]));
557+ DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] mcifwr_burst_time[%d][%d]:%d",
558+ i, j, bw_fixed_to_int(data->mcifwr_burst_time[i][j]));
559+ DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] min_dram_speed_change_margin[%d][%d]:%d",
560+ i, j, bw_fixed_to_int(data->min_dram_speed_change_margin[i][j]));
561+ DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] dispclk_required_for_dram_speed_change[%d][%d]:%d",
562+ i, j, bw_fixed_to_int(data->dispclk_required_for_dram_speed_change[i][j]));
563+ DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] blackout_duration_margin[%d][%d]:%d",
564+ i, j, bw_fixed_to_int(data->blackout_duration_margin[i][j]));
565+ DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] dispclk_required_for_blackout_duration[%d][%d]:%d",
566+ i, j, bw_fixed_to_int(data->dispclk_required_for_blackout_duration[i][j]));
567+ DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] dispclk_required_for_blackout_recovery[%d][%d]:%d",
568+ i, j, bw_fixed_to_int(data->dispclk_required_for_blackout_recovery[i][j]));
569+ }
570+ }
571+
572+ for (i = 0; i < 6; i++) {
573+ DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] dmif_required_sclk_for_urgent_latency[%d]:%d",
574+ i, bw_fixed_to_int(data->dmif_required_sclk_for_urgent_latency[i]));
575+ }
576+}
577+;
578+
579+#endif /* _CALCS_CALCS_LOGGER_H_ */
drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c+256−4
@@ -28,6 +28,7 @@ · 27 unmodified lines
2828 #include "dc.h"
2929 #include "core_types.h"
3030 #include "dal_asic_id.h"
31+#include "calcs_logger.h"
3132
3233 /*
3334 * NOTE:
@@ -52,11 +53,16 @@ static enum bw_calcs_version bw_calcs_version_from_asic_id(struct hw_asic_id asi · 18 unmodified lines
5253 return BW_CALCS_VERSION_CARRIZO;
5354
5455 case FAMILY_VI:
56+ if (ASIC_REV_IS_POLARIS12_V(asic_id.hw_internal_rev))
57+ return BW_CALCS_VERSION_POLARIS12;
5558 if (ASIC_REV_IS_POLARIS10_P(asic_id.hw_internal_rev))
5659 return BW_CALCS_VERSION_POLARIS10;
57− if (ASIC_REV_IS_POLARIS11_M(asic_id.hw_internal_rev) ||
58− ASIC_REV_IS_POLARIS12_V(asic_id.hw_internal_rev))
60+ if (ASIC_REV_IS_POLARIS11_M(asic_id.hw_internal_rev))
5961 return BW_CALCS_VERSION_POLARIS11;
62+#if defined(CONFIG_DRM_AMD_DC_VEGAM)
63+ if (ASIC_REV_IS_VEGAM(asic_id.hw_internal_rev))
64+ return BW_CALCS_VERSION_VEGAM;
65+#endif
6066 return BW_CALCS_VERSION_INVALID;
6167
6268 case FAMILY_AI:
@@ -2145,6 +2151,11 @@ void bw_calcs_init(struct bw_calcs_dceip *bw_dceip, · 2082 unmodified lines
21452151 dceip.mcifwr_all_surfaces_burst_time = bw_int_to_fixed(0); /* todo: this is a bug*/
21462152 break;
21472153 case BW_CALCS_VERSION_POLARIS10:
2154+#if defined(CONFIG_DRM_AMD_DC_VEGAM)
2155+ /* TODO: Treat VEGAM the same as P10 for now
2156+ * Need to tune the para for VEGAM if needed */
2157+ case BW_CALCS_VERSION_VEGAM:
2158+#endif
21482159 vbios.memory_type = bw_def_gddr5;
21492160 vbios.dram_channel_width_in_bits = 32;
21502161 vbios.number_of_dram_channels = asic_id.vram_width / vbios.dram_channel_width_in_bits;
@@ -2373,6 +2384,122 @@ void bw_calcs_init(struct bw_calcs_dceip *bw_dceip, · 222 unmodified lines
23732384 dceip.scatter_gather_pte_request_rows_in_tiling_mode = 2;
23742385 dceip.mcifwr_all_surfaces_burst_time = bw_int_to_fixed(0);
23752386 break;
2387+ case BW_CALCS_VERSION_POLARIS12:
2388+ vbios.memory_type = bw_def_gddr5;
2389+ vbios.dram_channel_width_in_bits = 32;
2390+ vbios.number_of_dram_channels = asic_id.vram_width / vbios.dram_channel_width_in_bits;
2391+ vbios.number_of_dram_banks = 8;
2392+ vbios.high_yclk = bw_int_to_fixed(6000);
2393+ vbios.mid_yclk = bw_int_to_fixed(3200);
2394+ vbios.low_yclk = bw_int_to_fixed(1000);
2395+ vbios.low_sclk = bw_int_to_fixed(678);
2396+ vbios.mid1_sclk = bw_int_to_fixed(864);
2397+ vbios.mid2_sclk = bw_int_to_fixed(900);
2398+ vbios.mid3_sclk = bw_int_to_fixed(920);
2399+ vbios.mid4_sclk = bw_int_to_fixed(940);
2400+ vbios.mid5_sclk = bw_int_to_fixed(960);
2401+ vbios.mid6_sclk = bw_int_to_fixed(980);
2402+ vbios.high_sclk = bw_int_to_fixed(1049);
2403+ vbios.low_voltage_max_dispclk = bw_int_to_fixed(459);
2404+ vbios.mid_voltage_max_dispclk = bw_int_to_fixed(654);
2405+ vbios.high_voltage_max_dispclk = bw_int_to_fixed(1108);
2406+ vbios.low_voltage_max_phyclk = bw_int_to_fixed(540);
2407+ vbios.mid_voltage_max_phyclk = bw_int_to_fixed(810);
2408+ vbios.high_voltage_max_phyclk = bw_int_to_fixed(810);
2409+ vbios.data_return_bus_width = bw_int_to_fixed(32);
2410+ vbios.trc = bw_int_to_fixed(48);
2411+ if (vbios.number_of_dram_channels == 2) // 64-bit
2412+ vbios.dmifmc_urgent_latency = bw_int_to_fixed(4);
2413+ else
2414+ vbios.dmifmc_urgent_latency = bw_int_to_fixed(3);
2415+ vbios.stutter_self_refresh_exit_latency = bw_int_to_fixed(5);
2416+ vbios.stutter_self_refresh_entry_latency = bw_int_to_fixed(0);
2417+ vbios.nbp_state_change_latency = bw_int_to_fixed(250);
2418+ vbios.mcifwrmc_urgent_latency = bw_int_to_fixed(10);
2419+ vbios.scatter_gather_enable = false;
2420+ vbios.down_spread_percentage = bw_frc_to_fixed(5, 10);
2421+ vbios.cursor_width = 32;
2422+ vbios.average_compression_rate = 4;
2423+ vbios.number_of_request_slots_gmc_reserves_for_dmif_per_channel = 256;
2424+ vbios.blackout_duration = bw_int_to_fixed(0); /* us */
2425+ vbios.maximum_blackout_recovery_time = bw_int_to_fixed(0);
2426+
2427+ dceip.max_average_percent_of_ideal_port_bw_display_can_use_in_normal_system_operation = 100;
2428+ dceip.max_average_percent_of_ideal_drambw_display_can_use_in_normal_system_operation = 100;
2429+ dceip.percent_of_ideal_port_bw_received_after_urgent_latency = 100;
2430+ dceip.large_cursor = false;
2431+ dceip.dmif_request_buffer_size = bw_int_to_fixed(768);
2432+ dceip.dmif_pipe_en_fbc_chunk_tracker = false;
2433+ dceip.cursor_max_outstanding_group_num = 1;
2434+ dceip.lines_interleaved_into_lb = 2;
2435+ dceip.chunk_width = 256;
2436+ dceip.number_of_graphics_pipes = 5;
2437+ dceip.number_of_underlay_pipes = 0;
2438+ dceip.low_power_tiling_mode = 0;
2439+ dceip.display_write_back_supported = true;
2440+ dceip.argb_compression_support = true;
2441+ dceip.underlay_vscaler_efficiency6_bit_per_component =
2442+ bw_frc_to_fixed(35556, 10000);
2443+ dceip.underlay_vscaler_efficiency8_bit_per_component =
2444+ bw_frc_to_fixed(34286, 10000);
2445+ dceip.underlay_vscaler_efficiency10_bit_per_component =
2446+ bw_frc_to_fixed(32, 10);
2447+ dceip.underlay_vscaler_efficiency12_bit_per_component =
2448+ bw_int_to_fixed(3);
2449+ dceip.graphics_vscaler_efficiency6_bit_per_component =
2450+ bw_frc_to_fixed(35, 10);
2451+ dceip.graphics_vscaler_efficiency8_bit_per_component =
2452+ bw_frc_to_fixed(34286, 10000);
2453+ dceip.graphics_vscaler_efficiency10_bit_per_component =
2454+ bw_frc_to_fixed(32, 10);
2455+ dceip.graphics_vscaler_efficiency12_bit_per_component =
2456+ bw_int_to_fixed(3);
2457+ dceip.alpha_vscaler_efficiency = bw_int_to_fixed(3);
2458+ dceip.max_dmif_buffer_allocated = 4;
2459+ dceip.graphics_dmif_size = 12288;
2460+ dceip.underlay_luma_dmif_size = 19456;
2461+ dceip.underlay_chroma_dmif_size = 23552;
2462+ dceip.pre_downscaler_enabled = true;
2463+ dceip.underlay_downscale_prefetch_enabled = true;
2464+ dceip.lb_write_pixels_per_dispclk = bw_int_to_fixed(1);
2465+ dceip.lb_size_per_component444 = bw_int_to_fixed(245952);
2466+ dceip.graphics_lb_nodownscaling_multi_line_prefetching = true;
2467+ dceip.stutter_and_dram_clock_state_change_gated_before_cursor =
2468+ bw_int_to_fixed(1);
2469+ dceip.underlay420_luma_lb_size_per_component = bw_int_to_fixed(
2470+ 82176);
2471+ dceip.underlay420_chroma_lb_size_per_component =
2472+ bw_int_to_fixed(164352);
2473+ dceip.underlay422_lb_size_per_component = bw_int_to_fixed(
2474+ 82176);
2475+ dceip.cursor_chunk_width = bw_int_to_fixed(64);
2476+ dceip.cursor_dcp_buffer_lines = bw_int_to_fixed(4);
2477+ dceip.underlay_maximum_width_efficient_for_tiling =
2478+ bw_int_to_fixed(1920);
2479+ dceip.underlay_maximum_height_efficient_for_tiling =
2480+ bw_int_to_fixed(1080);
2481+ dceip.peak_pte_request_to_eviction_ratio_limiting_multiple_displays_or_single_rotated_display =
2482+ bw_frc_to_fixed(3, 10);
2483+ dceip.peak_pte_request_to_eviction_ratio_limiting_single_display_no_rotation =
2484+ bw_int_to_fixed(25);
2485+ dceip.minimum_outstanding_pte_request_limit = bw_int_to_fixed(
2486+ 2);
2487+ dceip.maximum_total_outstanding_pte_requests_allowed_by_saw =
2488+ bw_int_to_fixed(128);
2489+ dceip.limit_excessive_outstanding_dmif_requests = true;
2490+ dceip.linear_mode_line_request_alternation_slice =
2491+ bw_int_to_fixed(64);
2492+ dceip.scatter_gather_lines_of_pte_prefetching_in_linear_mode =
2493+ 32;
2494+ dceip.display_write_back420_luma_mcifwr_buffer_size = 12288;
2495+ dceip.display_write_back420_chroma_mcifwr_buffer_size = 8192;
2496+ dceip.request_efficiency = bw_frc_to_fixed(8, 10);
2497+ dceip.dispclk_per_request = bw_int_to_fixed(2);
2498+ dceip.dispclk_ramping_factor = bw_frc_to_fixed(105, 100);
2499+ dceip.display_pipe_throughput_factor = bw_frc_to_fixed(105, 100);
2500+ dceip.scatter_gather_pte_request_rows_in_tiling_mode = 2;
2501+ dceip.mcifwr_all_surfaces_burst_time = bw_int_to_fixed(0);
2502+ break;
23762503 case BW_CALCS_VERSION_STONEY:
23772504 vbios.memory_type = bw_def_gddr5;
23782505 vbios.dram_channel_width_in_bits = 64;
@@ -2815,6 +2942,19 @@ static void populate_initial_data( · 436 unmodified lines
28152942 data->bytes_per_pixel[num_displays + 4] = 4;
28162943 break;
28172944 }
2945+ } else if (pipe[i].stream->dst.width != 0 &&
2946+ pipe[i].stream->dst.height != 0 &&
2947+ pipe[i].stream->src.width != 0 &&
2948+ pipe[i].stream->src.height != 0) {
2949+ data->src_width[num_displays + 4] = bw_int_to_fixed(pipe[i].stream->src.width);
2950+ data->pitch_in_pixels[num_displays + 4] = data->src_width[num_displays + 4];
2951+ data->src_height[num_displays + 4] = bw_int_to_fixed(pipe[i].stream->src.height);
2952+ data->h_taps[num_displays + 4] = pipe[i].stream->src.width == pipe[i].stream->dst.width ? bw_int_to_fixed(1) : bw_int_to_fixed(2);
2953+ data->v_taps[num_displays + 4] = pipe[i].stream->src.height == pipe[i].stream->dst.height ? bw_int_to_fixed(1) : bw_int_to_fixed(2);
2954+ data->h_scale_ratio[num_displays + 4] = bw_frc_to_fixed(pipe[i].stream->src.width, pipe[i].stream->dst.width);
2955+ data->v_scale_ratio[num_displays + 4] = bw_frc_to_fixed(pipe[i].stream->src.height, pipe[i].stream->dst.height);
2956+ data->rotation_angle[num_displays + 4] = bw_int_to_fixed(0);
2957+ data->bytes_per_pixel[num_displays + 4] = 4;
28182958 } else {
28192959 data->src_width[num_displays + 4] = bw_int_to_fixed(pipe[i].stream->timing.h_addressable);
28202960 data->pitch_in_pixels[num_displays + 4] = data->src_width[num_displays + 4];
@@ -2873,6 +3013,11 @@ bool bw_calcs(struct dc_context *ctx, · 52 unmodified lines
28733013 struct bw_fixed mid_yclk = vbios->mid_yclk;
28743014 struct bw_fixed low_yclk = vbios->low_yclk;
28753015
3016+ if (ctx->dc->debug.bandwidth_calcs_trace) {
3017+ print_bw_calcs_dceip(ctx->logger, dceip);
3018+ print_bw_calcs_vbios(ctx->logger, vbios);
3019+ print_bw_calcs_data(ctx->logger, data);
3020+ }
28763021 calculate_bandwidth(dceip, vbios, data);
28773022
28783023 yclk_lvl = data->y_clk_level;
@@ -2968,7 +3113,33 @@ bool bw_calcs(struct dc_context *ctx, · 89 unmodified lines
29683113 bw_fixed_to_int(bw_mul(data->
29693114 stutter_exit_watermark[9], bw_int_to_fixed(1000)));
29703115
2971−
3116+ calcs_output->stutter_entry_wm_ns[0].a_mark =
3117+ bw_fixed_to_int(bw_mul(data->
3118+ stutter_entry_watermark[4], bw_int_to_fixed(1000)));
3119+ calcs_output->stutter_entry_wm_ns[1].a_mark =
3120+ bw_fixed_to_int(bw_mul(data->
3121+ stutter_entry_watermark[5], bw_int_to_fixed(1000)));
3122+ calcs_output->stutter_entry_wm_ns[2].a_mark =
3123+ bw_fixed_to_int(bw_mul(data->
3124+ stutter_entry_watermark[6], bw_int_to_fixed(1000)));
3125+ if (ctx->dc->caps.max_slave_planes) {
3126+ calcs_output->stutter_entry_wm_ns[3].a_mark =
3127+ bw_fixed_to_int(bw_mul(data->
3128+ stutter_entry_watermark[0], bw_int_to_fixed(1000)));
3129+ calcs_output->stutter_entry_wm_ns[4].a_mark =
3130+ bw_fixed_to_int(bw_mul(data->
3131+ stutter_entry_watermark[1], bw_int_to_fixed(1000)));
3132+ } else {
3133+ calcs_output->stutter_entry_wm_ns[3].a_mark =
3134+ bw_fixed_to_int(bw_mul(data->
3135+ stutter_entry_watermark[7], bw_int_to_fixed(1000)));
3136+ calcs_output->stutter_entry_wm_ns[4].a_mark =
3137+ bw_fixed_to_int(bw_mul(data->
3138+ stutter_entry_watermark[8], bw_int_to_fixed(1000)));
3139+ }
3140+ calcs_output->stutter_entry_wm_ns[5].a_mark =
3141+ bw_fixed_to_int(bw_mul(data->
3142+ stutter_entry_watermark[9], bw_int_to_fixed(1000)));
29723143
29733144 calcs_output->urgent_wm_ns[0].a_mark =
29743145 bw_fixed_to_int(bw_mul(data->
@@ -3063,7 +3234,33 @@ bool bw_calcs(struct dc_context *ctx, · 88 unmodified lines
30633234 bw_fixed_to_int(bw_mul(data->
30643235 stutter_exit_watermark[9], bw_int_to_fixed(1000)));
30653236
3066−
3237+ calcs_output->stutter_entry_wm_ns[0].b_mark =
3238+ bw_fixed_to_int(bw_mul(data->
3239+ stutter_entry_watermark[4], bw_int_to_fixed(1000)));
3240+ calcs_output->stutter_entry_wm_ns[1].b_mark =
3241+ bw_fixed_to_int(bw_mul(data->
3242+ stutter_entry_watermark[5], bw_int_to_fixed(1000)));
3243+ calcs_output->stutter_entry_wm_ns[2].b_mark =
3244+ bw_fixed_to_int(bw_mul(data->
3245+ stutter_entry_watermark[6], bw_int_to_fixed(1000)));
3246+ if (ctx->dc->caps.max_slave_planes) {
3247+ calcs_output->stutter_entry_wm_ns[3].b_mark =
3248+ bw_fixed_to_int(bw_mul(data->
3249+ stutter_entry_watermark[0], bw_int_to_fixed(1000)));
3250+ calcs_output->stutter_entry_wm_ns[4].b_mark =
3251+ bw_fixed_to_int(bw_mul(data->
3252+ stutter_entry_watermark[1], bw_int_to_fixed(1000)));
3253+ } else {
3254+ calcs_output->stutter_entry_wm_ns[3].b_mark =
3255+ bw_fixed_to_int(bw_mul(data->
3256+ stutter_entry_watermark[7], bw_int_to_fixed(1000)));
3257+ calcs_output->stutter_entry_wm_ns[4].b_mark =
3258+ bw_fixed_to_int(bw_mul(data->
3259+ stutter_entry_watermark[8], bw_int_to_fixed(1000)));
3260+ }
3261+ calcs_output->stutter_entry_wm_ns[5].b_mark =
3262+ bw_fixed_to_int(bw_mul(data->
3263+ stutter_entry_watermark[9], bw_int_to_fixed(1000)));
30673264
30683265 calcs_output->urgent_wm_ns[0].b_mark =
30693266 bw_fixed_to_int(bw_mul(data->
@@ -3156,6 +3353,34 @@ bool bw_calcs(struct dc_context *ctx, · 86 unmodified lines
31563353 bw_fixed_to_int(bw_mul(data->
31573354 stutter_exit_watermark[9], bw_int_to_fixed(1000)));
31583355
3356+ calcs_output->stutter_entry_wm_ns[0].c_mark =
3357+ bw_fixed_to_int(bw_mul(data->
3358+ stutter_entry_watermark[4], bw_int_to_fixed(1000)));
3359+ calcs_output->stutter_entry_wm_ns[1].c_mark =
3360+ bw_fixed_to_int(bw_mul(data->
3361+ stutter_entry_watermark[5], bw_int_to_fixed(1000)));
3362+ calcs_output->stutter_entry_wm_ns[2].c_mark =
3363+ bw_fixed_to_int(bw_mul(data->
3364+ stutter_entry_watermark[6], bw_int_to_fixed(1000)));
3365+ if (ctx->dc->caps.max_slave_planes) {
3366+ calcs_output->stutter_entry_wm_ns[3].c_mark =
3367+ bw_fixed_to_int(bw_mul(data->
3368+ stutter_entry_watermark[0], bw_int_to_fixed(1000)));
3369+ calcs_output->stutter_entry_wm_ns[4].c_mark =
3370+ bw_fixed_to_int(bw_mul(data->
3371+ stutter_entry_watermark[1], bw_int_to_fixed(1000)));
3372+ } else {
3373+ calcs_output->stutter_entry_wm_ns[3].c_mark =
3374+ bw_fixed_to_int(bw_mul(data->
3375+ stutter_entry_watermark[7], bw_int_to_fixed(1000)));
3376+ calcs_output->stutter_entry_wm_ns[4].c_mark =
3377+ bw_fixed_to_int(bw_mul(data->
3378+ stutter_entry_watermark[8], bw_int_to_fixed(1000)));
3379+ }
3380+ calcs_output->stutter_entry_wm_ns[5].c_mark =
3381+ bw_fixed_to_int(bw_mul(data->
3382+ stutter_entry_watermark[9], bw_int_to_fixed(1000)));
3383+
31593384 calcs_output->urgent_wm_ns[0].c_mark =
31603385 bw_fixed_to_int(bw_mul(data->
31613386 urgent_watermark[4], bw_int_to_fixed(1000)));
@@ -3260,6 +3485,33 @@ bool bw_calcs(struct dc_context *ctx, · 98 unmodified lines
32603485 bw_fixed_to_int(bw_mul(data->
32613486 stutter_exit_watermark[9], bw_int_to_fixed(1000)));
32623487
3488+ calcs_output->stutter_entry_wm_ns[0].d_mark =
3489+ bw_fixed_to_int(bw_mul(data->
3490+ stutter_entry_watermark[4], bw_int_to_fixed(1000)));
3491+ calcs_output->stutter_entry_wm_ns[1].d_mark =
3492+ bw_fixed_to_int(bw_mul(data->
3493+ stutter_entry_watermark[5], bw_int_to_fixed(1000)));
3494+ calcs_output->stutter_entry_wm_ns[2].d_mark =
3495+ bw_fixed_to_int(bw_mul(data->
3496+ stutter_entry_watermark[6], bw_int_to_fixed(1000)));
3497+ if (ctx->dc->caps.max_slave_planes) {
3498+ calcs_output->stutter_entry_wm_ns[3].d_mark =
3499+ bw_fixed_to_int(bw_mul(data->
3500+ stutter_entry_watermark[0], bw_int_to_fixed(1000)));
3501+ calcs_output->stutter_entry_wm_ns[4].d_mark =
3502+ bw_fixed_to_int(bw_mul(data->
3503+ stutter_entry_watermark[1], bw_int_to_fixed(1000)));
3504+ } else {
3505+ calcs_output->stutter_entry_wm_ns[3].d_mark =
3506+ bw_fixed_to_int(bw_mul(data->
3507+ stutter_entry_watermark[7], bw_int_to_fixed(1000)));
3508+ calcs_output->stutter_entry_wm_ns[4].d_mark =
3509+ bw_fixed_to_int(bw_mul(data->
3510+ stutter_entry_watermark[8], bw_int_to_fixed(1000)));
3511+ }
3512+ calcs_output->stutter_entry_wm_ns[5].d_mark =
3513+ bw_fixed_to_int(bw_mul(data->
3514+ stutter_entry_watermark[9], bw_int_to_fixed(1000)));
32633515
32643516 calcs_output->urgent_wm_ns[0].d_mark =
32653517 bw_fixed_to_int(bw_mul(data->
drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c+37−37
@@ -1459,39 +1459,39 @@ void dcn_bw_notify_pplib_of_wm_ranges(struct dc *dc) · 1458 unmodified lines
14591459 void dcn_bw_sync_calcs_and_dml(struct dc *dc)
14601460 {
14611461 kernel_fpu_begin();
1462− DC_LOG_BANDWIDTH_CALCS("sr_exit_time: %d ns\n"
1463− "sr_enter_plus_exit_time: %d ns\n"
1464− "urgent_latency: %d ns\n"
1465− "write_back_latency: %d ns\n"
1466− "percent_of_ideal_drambw_received_after_urg_latency: %d %\n"
1462+ DC_LOG_BANDWIDTH_CALCS("sr_exit_time: %f ns\n"
1463+ "sr_enter_plus_exit_time: %f ns\n"
1464+ "urgent_latency: %f ns\n"
1465+ "write_back_latency: %f ns\n"
1466+ "percent_of_ideal_drambw_received_after_urg_latency: %f %%\n"
14671467 "max_request_size: %d bytes\n"
1468− "dcfclkv_max0p9: %d kHz\n"
1469− "dcfclkv_nom0p8: %d kHz\n"
1470− "dcfclkv_mid0p72: %d kHz\n"
1471− "dcfclkv_min0p65: %d kHz\n"
1472− "max_dispclk_vmax0p9: %d kHz\n"
1473− "max_dispclk_vnom0p8: %d kHz\n"
1474− "max_dispclk_vmid0p72: %d kHz\n"
1475− "max_dispclk_vmin0p65: %d kHz\n"
1476− "max_dppclk_vmax0p9: %d kHz\n"
1477− "max_dppclk_vnom0p8: %d kHz\n"
1478− "max_dppclk_vmid0p72: %d kHz\n"
1479− "max_dppclk_vmin0p65: %d kHz\n"
1480− "socclk: %d kHz\n"
1481− "fabric_and_dram_bandwidth_vmax0p9: %d MB/s\n"
1482− "fabric_and_dram_bandwidth_vnom0p8: %d MB/s\n"
1483− "fabric_and_dram_bandwidth_vmid0p72: %d MB/s\n"
1484− "fabric_and_dram_bandwidth_vmin0p65: %d MB/s\n"
1485− "phyclkv_max0p9: %d kHz\n"
1486− "phyclkv_nom0p8: %d kHz\n"
1487− "phyclkv_mid0p72: %d kHz\n"
1488− "phyclkv_min0p65: %d kHz\n"
1489− "downspreading: %d %\n"
1468+ "dcfclkv_max0p9: %f kHz\n"
1469+ "dcfclkv_nom0p8: %f kHz\n"
1470+ "dcfclkv_mid0p72: %f kHz\n"
1471+ "dcfclkv_min0p65: %f kHz\n"
1472+ "max_dispclk_vmax0p9: %f kHz\n"
1473+ "max_dispclk_vnom0p8: %f kHz\n"
1474+ "max_dispclk_vmid0p72: %f kHz\n"
1475+ "max_dispclk_vmin0p65: %f kHz\n"
1476+ "max_dppclk_vmax0p9: %f kHz\n"
1477+ "max_dppclk_vnom0p8: %f kHz\n"
1478+ "max_dppclk_vmid0p72: %f kHz\n"
1479+ "max_dppclk_vmin0p65: %f kHz\n"
1480+ "socclk: %f kHz\n"
1481+ "fabric_and_dram_bandwidth_vmax0p9: %f MB/s\n"
1482+ "fabric_and_dram_bandwidth_vnom0p8: %f MB/s\n"
1483+ "fabric_and_dram_bandwidth_vmid0p72: %f MB/s\n"
1484+ "fabric_and_dram_bandwidth_vmin0p65: %f MB/s\n"
1485+ "phyclkv_max0p9: %f kHz\n"
1486+ "phyclkv_nom0p8: %f kHz\n"
1487+ "phyclkv_mid0p72: %f kHz\n"
1488+ "phyclkv_min0p65: %f kHz\n"
1489+ "downspreading: %f %%\n"
14901490 "round_trip_ping_latency_cycles: %d DCFCLK Cycles\n"
14911491 "urgent_out_of_order_return_per_channel: %d Bytes\n"
14921492 "number_of_channels: %d\n"
14931493 "vmm_page_size: %d Bytes\n"
1494− "dram_clock_change_latency: %d ns\n"
1494+ "dram_clock_change_latency: %f ns\n"
14951495 "return_bus_width: %d Bytes\n",
14961496 dc->dcn_soc->sr_exit_time * 1000,
14971497 dc->dcn_soc->sr_enter_plus_exit_time * 1000,
@@ -1527,11 +1527,11 @@ void dcn_bw_sync_calcs_and_dml(struct dc *dc) · 29 unmodified lines
15271527 dc->dcn_soc->vmm_page_size,
15281528 dc->dcn_soc->dram_clock_change_latency * 1000,
15291529 dc->dcn_soc->return_bus_width);
1530− DC_LOG_BANDWIDTH_CALCS("rob_buffer_size_in_kbyte: %d\n"
1531− "det_buffer_size_in_kbyte: %d\n"
1532− "dpp_output_buffer_pixels: %d\n"
1533− "opp_output_buffer_lines: %d\n"
1534− "pixel_chunk_size_in_kbyte: %d\n"
1530+ DC_LOG_BANDWIDTH_CALCS("rob_buffer_size_in_kbyte: %f\n"
1531+ "det_buffer_size_in_kbyte: %f\n"
1532+ "dpp_output_buffer_pixels: %f\n"
1533+ "opp_output_buffer_lines: %f\n"
1534+ "pixel_chunk_size_in_kbyte: %f\n"
15351535 "pte_enable: %d\n"
15361536 "pte_chunk_size: %d kbytes\n"
15371537 "meta_chunk_size: %d kbytes\n"
@@ -1550,13 +1550,13 @@ void dcn_bw_sync_calcs_and_dml(struct dc *dc) · 12 unmodified lines
15501550 "max_pscl_tolb_throughput: %d pixels/dppclk\n"
15511551 "max_lb_tovscl_throughput: %d pixels/dppclk\n"
15521552 "max_vscl_tohscl_throughput: %d pixels/dppclk\n"
1553− "max_hscl_ratio: %d\n"
1554− "max_vscl_ratio: %d\n"
1553+ "max_hscl_ratio: %f\n"
1554+ "max_vscl_ratio: %f\n"
15551555 "max_hscl_taps: %d\n"
15561556 "max_vscl_taps: %d\n"
15571557 "pte_buffer_size_in_requests: %d\n"
1558− "dispclk_ramping_margin: %d %\n"
1559− "under_scan_factor: %d %\n"
1558+ "dispclk_ramping_margin: %f %%\n"
1559+ "under_scan_factor: %f %%\n"
15601560 "max_inter_dcn_tile_repeaters: %d\n"
15611561 "can_vstartup_lines_exceed_vsync_plus_back_porch_lines_minus_one: %d\n"
15621562 "bug_forcing_luma_and_chroma_request_to_same_size_fixed: %d\n"
drivers/gpu/drm/amd/display/dc/core/dc.c+17−95
@@ -936,95 +936,6 @@ bool dc_post_update_surfaces_to_stream(struct dc *dc) · 935 unmodified lines
936936 return true;
937937 }
938938
939−/*
940− * TODO this whole function needs to go
941− *
942− * dc_surface_update is needlessly complex. See if we can just replace this
943− * with a dc_plane_state and follow the atomic model a bit more closely here.
944− */
945−bool dc_commit_planes_to_stream(
946− struct dc *dc,
947− struct dc_plane_state **plane_states,
948− uint8_t new_plane_count,
949− struct dc_stream_state *dc_stream,
950− struct dc_state *state)
951−{
952− /* no need to dynamically allocate this. it's pretty small */
953− struct dc_surface_update updates[MAX_SURFACES];
954− struct dc_flip_addrs *flip_addr;
955− struct dc_plane_info *plane_info;
956− struct dc_scaling_info *scaling_info;
957− int i;
958− struct dc_stream_update *stream_update =
959− kzalloc(sizeof(struct dc_stream_update), GFP_KERNEL);
960−
961− if (!stream_update) {
962− BREAK_TO_DEBUGGER();
963− return false;
964− }
965−
966− flip_addr = kcalloc(MAX_SURFACES, sizeof(struct dc_flip_addrs),
967− GFP_KERNEL);
968− plane_info = kcalloc(MAX_SURFACES, sizeof(struct dc_plane_info),
969− GFP_KERNEL);
970− scaling_info = kcalloc(MAX_SURFACES, sizeof(struct dc_scaling_info),
971− GFP_KERNEL);
972−
973− if (!flip_addr || !plane_info || !scaling_info) {
974− kfree(flip_addr);
975− kfree(plane_info);
976− kfree(scaling_info);
977− kfree(stream_update);
978− return false;
979− }
980−
981− memset(updates, 0, sizeof(updates));
982−
983− stream_update->src = dc_stream->src;
984− stream_update->dst = dc_stream->dst;
985− stream_update->out_transfer_func = dc_stream->out_transfer_func;
986−
987− for (i = 0; i < new_plane_count; i++) {
988− updates[i].surface = plane_states[i];
989− updates[i].gamma =
990− (struct dc_gamma *)plane_states[i]->gamma_correction;
991− updates[i].in_transfer_func = plane_states[i]->in_transfer_func;
992− flip_addr[i].address = plane_states[i]->address;
993− flip_addr[i].flip_immediate = plane_states[i]->flip_immediate;
994− plane_info[i].color_space = plane_states[i]->color_space;
995− plane_info[i].input_tf = plane_states[i]->input_tf;
996− plane_info[i].format = plane_states[i]->format;
997− plane_info[i].plane_size = plane_states[i]->plane_size;
998− plane_info[i].rotation = plane_states[i]->rotation;
999− plane_info[i].horizontal_mirror = plane_states[i]->horizontal_mirror;
1000− plane_info[i].stereo_format = plane_states[i]->stereo_format;
1001− plane_info[i].tiling_info = plane_states[i]->tiling_info;
1002− plane_info[i].visible = plane_states[i]->visible;
1003− plane_info[i].per_pixel_alpha = plane_states[i]->per_pixel_alpha;
1004− plane_info[i].dcc = plane_states[i]->dcc;
1005− scaling_info[i].scaling_quality = plane_states[i]->scaling_quality;
1006− scaling_info[i].src_rect = plane_states[i]->src_rect;
1007− scaling_info[i].dst_rect = plane_states[i]->dst_rect;
1008− scaling_info[i].clip_rect = plane_states[i]->clip_rect;
1009−
1010− updates[i].flip_addr = &flip_addr[i];
1011− updates[i].plane_info = &plane_info[i];
1012− updates[i].scaling_info = &scaling_info[i];
1013− }
1014−
1015− dc_commit_updates_for_stream(
1016− dc,
1017− updates,
1018− new_plane_count,
1019− dc_stream, stream_update, plane_states, state);
1020−
1021− kfree(flip_addr);
1022− kfree(plane_info);
1023− kfree(scaling_info);
1024− kfree(stream_update);
1025− return true;
1026−}
1027−
1028939 struct dc_state *dc_create_state(void)
1029940 {
1030941 struct dc_state *context = kzalloc(sizeof(struct dc_state),
@@ -1107,9 +1018,6 @@ static enum surface_update_type get_plane_info_update_type(const struct dc_surfa · 76 unmodified lines
11071018 if (u->plane_info->color_space != u->surface->color_space)
11081019 update_flags->bits.color_space_change = 1;
11091020
1110− if (u->plane_info->input_tf != u->surface->input_tf)
1111− update_flags->bits.input_tf_change = 1;
1112−
11131021 if (u->plane_info->horizontal_mirror != u->surface->horizontal_mirror)
11141022 update_flags->bits.horizontal_mirror_change = 1;
11151023
@@ -1243,12 +1151,20 @@ static enum surface_update_type det_surface_update(const struct dc *dc, · 127 unmodified lines
12431151 if (u->input_csc_color_matrix)
12441152 update_flags->bits.input_csc_change = 1;
12451153
1246− if (update_flags->bits.in_transfer_func_change
1247− || update_flags->bits.input_csc_change) {
1154+ if (u->coeff_reduction_factor)
1155+ update_flags->bits.coeff_reduction_change = 1;
1156+
1157+ if (update_flags->bits.in_transfer_func_change) {
12481158 type = UPDATE_TYPE_MED;
12491159 elevate_update_type(&overall_type, type);
12501160 }
12511161
1162+ if (update_flags->bits.input_csc_change
1163+ || update_flags->bits.coeff_reduction_change) {
1164+ type = UPDATE_TYPE_FULL;
1165+ elevate_update_type(&overall_type, type);
1166+ }
1167+
12521168 return overall_type;
12531169 }
12541170
@@ -1297,7 +1213,7 @@ enum surface_update_type dc_check_update_surfaces_for_stream( · 42 unmodified lines
12971213 type = check_update_surfaces_for_stream(dc, updates, surface_count, stream_update, stream_status);
12981214 if (type == UPDATE_TYPE_FULL)
12991215 for (i = 0; i < surface_count; i++)
1300− updates[i].surface->update_flags.bits.full_update = 1;
1216+ updates[i].surface->update_flags.raw = 0xFFFFFFFF;
13011217
13021218 return type;
13031219 }
@@ -1375,6 +1291,12 @@ static void commit_planes_for_stream(struct dc *dc, · 71 unmodified lines
13751291 pipe_ctx->stream_res.abm->funcs->set_abm_level(
13761292 pipe_ctx->stream_res.abm, stream->abm_level);
13771293 }
1294+
1295+ if (stream_update && stream_update->periodic_fn_vsync_delta &&
1296+ pipe_ctx->stream_res.tg->funcs->program_vline_interrupt)
1297+ pipe_ctx->stream_res.tg->funcs->program_vline_interrupt(
1298+ pipe_ctx->stream_res.tg, &pipe_ctx->stream->timing,
1299+ pipe_ctx->stream->periodic_fn_vsync_delta);
13781300 }
13791301 }
13801302
drivers/gpu/drm/amd/display/dc/core/dc_debug.c+16−22
@@ -36,8 +36,9 @@ · 35 unmodified lines
3636 #include "hw_sequencer.h"
3737
3838 #include "resource.h"
39−#define DC_LOGGER \
40− logger
39+
40+#define DC_LOGGER_INIT(logger)
41+
4142
4243 #define SURFACE_TRACE(...) do {\
4344 if (dc->debug.surface_trace) \
@@ -60,8 +61,7 @@ void pre_surface_trace( · 16 unmodified lines
6061 int surface_count)
6162 {
6263 int i;
63− struct dc *core_dc = dc;
64− struct dal_logger *logger = core_dc->ctx->logger;
64+ DC_LOGGER_INIT(dc->ctx->logger);
6565
6666 for (i = 0; i < surface_count; i++) {
6767 const struct dc_plane_state *plane_state = plane_states[i];
@@ -72,8 +72,8 @@ void pre_surface_trace( · 4 unmodified lines
7272 "plane_state->visible = %d;\n"
7373 "plane_state->flip_immediate = %d;\n"
7474 "plane_state->address.type = %d;\n"
75− "plane_state->address.grph.addr.quad_part = 0x%X;\n"
76− "plane_state->address.grph.meta_addr.quad_part = 0x%X;\n"
75+ "plane_state->address.grph.addr.quad_part = 0x%llX;\n"
76+ "plane_state->address.grph.meta_addr.quad_part = 0x%llX;\n"
7777 "plane_state->scaling_quality.h_taps = %d;\n"
7878 "plane_state->scaling_quality.v_taps = %d;\n"
7979 "plane_state->scaling_quality.h_taps_c = %d;\n"
@@ -155,7 +155,6 @@ void pre_surface_trace( · 75 unmodified lines
155155 "plane_state->tiling_info.gfx8.pipe_config = %d;\n"
156156 "plane_state->tiling_info.gfx8.array_mode = %d;\n"
157157 "plane_state->color_space = %d;\n"
158− "plane_state->input_tf = %d;\n"
159158 "plane_state->dcc.enable = %d;\n"
160159 "plane_state->format = %d;\n"
161160 "plane_state->rotation = %d;\n"
@@ -163,7 +162,6 @@ void pre_surface_trace( · 1 unmodified line
163162 plane_state->tiling_info.gfx8.pipe_config,
164163 plane_state->tiling_info.gfx8.array_mode,
165164 plane_state->color_space,
166− plane_state->input_tf,
167165 plane_state->dcc.enable,
168166 plane_state->format,
169167 plane_state->rotation,
@@ -183,8 +181,7 @@ void update_surface_trace( · 13 unmodified lines
183181 int surface_count)
184182 {
185183 int i;
186− struct dc *core_dc = dc;
187− struct dal_logger *logger = core_dc->ctx->logger;
184+ DC_LOGGER_INIT(dc->ctx->logger);
188185
189186 for (i = 0; i < surface_count; i++) {
190187 const struct dc_surface_update *update = &updates[i];
@@ -192,8 +189,8 @@ void update_surface_trace( · 1 unmodified line
192189 SURFACE_TRACE("Update %d\n", i);
193190 if (update->flip_addr) {
194191 SURFACE_TRACE("flip_addr->address.type = %d;\n"
195− "flip_addr->address.grph.addr.quad_part = 0x%X;\n"
196− "flip_addr->address.grph.meta_addr.quad_part = 0x%X;\n"
192+ "flip_addr->address.grph.addr.quad_part = 0x%llX;\n"
193+ "flip_addr->address.grph.meta_addr.quad_part = 0x%llX;\n"
197194 "flip_addr->flip_immediate = %d;\n",
198195 update->flip_addr->address.type,
199196 update->flip_addr->address.grph.addr.quad_part,
@@ -204,16 +201,15 @@ void update_surface_trace( · 4 unmodified lines
204201 if (update->plane_info) {
205202 SURFACE_TRACE(
206203 "plane_info->color_space = %d;\n"
207− "plane_info->input_tf = %d;\n"
208204 "plane_info->format = %d;\n"
209205 "plane_info->plane_size.grph.surface_pitch = %d;\n"
210206 "plane_info->plane_size.grph.surface_size.height = %d;\n"
211207 "plane_info->plane_size.grph.surface_size.width = %d;\n"
212208 "plane_info->plane_size.grph.surface_size.x = %d;\n"
213209 "plane_info->plane_size.grph.surface_size.y = %d;\n"
214− "plane_info->rotation = %d;\n",
210+ "plane_info->rotation = %d;\n"
211+ "plane_info->stereo_format = %d;\n",
215212 update->plane_info->color_space,
216− update->plane_info->input_tf,
217213 update->plane_info->format,
218214 update->plane_info->plane_size.grph.surface_pitch,
219215 update->plane_info->plane_size.grph.surface_size.height,
@@ -303,8 +299,7 @@ void update_surface_trace( · 83 unmodified lines
303299
304300 void post_surface_trace(struct dc *dc)
305301 {
306− struct dc *core_dc = dc;
307− struct dal_logger *logger = core_dc->ctx->logger;
302+ DC_LOGGER_INIT(dc->ctx->logger);
308303
309304 SURFACE_TRACE("post surface process.\n");
310305
@@ -316,10 +311,10 @@ void context_timing_trace( · 5 unmodified lines
316311 {
317312 int i;
318313 struct dc *core_dc = dc;
319− struct dal_logger *logger = core_dc->ctx->logger;
320314 int h_pos[MAX_PIPES], v_pos[MAX_PIPES];
321315 struct crtc_position position;
322316 unsigned int underlay_idx = core_dc->res_pool->underlay_pipe_index;
317+ DC_LOGGER_INIT(dc->ctx->logger);
323318
324319
325320 for (i = 0; i < core_dc->res_pool->pipe_count; i++) {
@@ -354,9 +349,7 @@ void context_clock_trace( · 28 unmodified lines
354349 struct dc_state *context)
355350 {
356351 #if defined(CONFIG_DRM_AMD_DC_DCN1_0)
357− struct dc *core_dc = dc;
358− struct dal_logger *logger = core_dc->ctx->logger;
359−
352+ DC_LOGGER_INIT(dc->ctx->logger);
360353 CLOCK_TRACE("Current: dispclk_khz:%d max_dppclk_khz:%d dcfclk_khz:%d\n"
361354 "dcfclk_deep_sleep_khz:%d fclk_khz:%d socclk_khz:%d\n",
362355 context->bw.dcn.calc_clk.dispclk_khz,
@@ -371,6 +364,7 @@ void context_clock_trace( · 8 unmodified lines
371364 context->bw.dcn.calc_clk.dppclk_khz,
372365 context->bw.dcn.calc_clk.dcfclk_khz,
373366 context->bw.dcn.calc_clk.dcfclk_deep_sleep_khz,
374− context->bw.dcn.calc_clk.fclk_khz);
367+ context->bw.dcn.calc_clk.fclk_khz,
368+ context->bw.dcn.calc_clk.socclk_khz);
375369 #endif
376370 }
drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c+23−1
@@ -208,6 +208,7 @@ void color_space_to_black_color( · 207 unmodified lines
208208 case COLOR_SPACE_YCBCR709:
209209 case COLOR_SPACE_YCBCR601_LIMITED:
210210 case COLOR_SPACE_YCBCR709_LIMITED:
211+ case COLOR_SPACE_2020_YCBCR:
211212 *black_color = black_color_format[BLACK_COLOR_FORMAT_YUV_CV];
212213 break;
213214
@@ -216,7 +217,25 @@ void color_space_to_black_color( · 2 unmodified lines
216217 black_color_format[BLACK_COLOR_FORMAT_RGB_LIMITED];
217218 break;
218219
219− default:
220+ /**
221+ * Remove default and add case for all color space
222+ * so when we forget to add new color space
223+ * compiler will give a warning
224+ */
225+ case COLOR_SPACE_UNKNOWN:
226+ case COLOR_SPACE_SRGB:
227+ case COLOR_SPACE_XR_RGB:
228+ case COLOR_SPACE_MSREF_SCRGB:
229+ case COLOR_SPACE_XV_YCC_709:
230+ case COLOR_SPACE_XV_YCC_601:
231+ case COLOR_SPACE_2020_RGB_FULLRANGE:
232+ case COLOR_SPACE_2020_RGB_LIMITEDRANGE:
233+ case COLOR_SPACE_ADOBERGB:
234+ case COLOR_SPACE_DCIP3:
235+ case COLOR_SPACE_DISPLAYNATIVE:
236+ case COLOR_SPACE_DOLBYVISION:
237+ case COLOR_SPACE_APPCTRL:
238+ case COLOR_SPACE_CUSTOMPOINTS:
220239 /* fefault is sRGB black (full range). */
221240 *black_color =
222241 black_color_format[BLACK_COLOR_FORMAT_RGB_FULLRANGE];
@@ -230,6 +249,9 @@ bool hwss_wait_for_blank_complete( · 7 unmodified lines
230249 {
231250 int counter;
232251
252+ /* Not applicable if the pipe is not primary, save 300ms of boot time */
253+ if (!tg->funcs->is_blanked)
254+ return true;
233255 for (counter = 0; counter < 100; counter++) {
234256 if (tg->funcs->is_blanked(tg))
235257 break;
drivers/gpu/drm/amd/display/dc/core/dc_link.c+42−21
@@ -45,8 +45,9 @@ · 44 unmodified lines
4545 #include "dce/dce_11_0_d.h"
4646 #include "dce/dce_11_0_enum.h"
4747 #include "dce/dce_11_0_sh_mask.h"
48−#define DC_LOGGER \
49− dc_ctx->logger
48+
49+#define DC_LOGGER_INIT(logger)
50+
5051
5152 #define LINK_INFO(...) \
5253 DC_LOG_HW_HOTPLUG( \
@@ -561,7 +562,7 @@ bool dc_link_detect(struct dc_link *link, enum dc_detect_reason reason) · 508 unmodified lines
561562 struct dc_context *dc_ctx = link->ctx;
562563 struct dc_sink *sink = NULL;
563564 enum dc_connection_type new_connection_type = dc_connection_none;
564−
565+ DC_LOGGER_INIT(link->ctx->logger);
565566 if (link->connector_signal == SIGNAL_TYPE_VIRTUAL)
566567 return false;
567568
@@ -927,6 +928,7 @@ static bool construct( · 359 unmodified lines
927928 struct integrated_info info = {{{ 0 }}};
928929 struct dc_bios *bios = init_params->dc->ctx->dc_bios;
929930 const struct dc_vbios_funcs *bp_funcs = bios->funcs;
931+ DC_LOGGER_INIT(dc_ctx->logger);
930932
931933 link->irq_source_hpd = DC_IRQ_SOURCE_INVALID;
932934 link->irq_source_hpd_rx = DC_IRQ_SOURCE_INVALID;
@@ -1135,7 +1137,8 @@ static void dpcd_configure_panel_mode( · 202 unmodified lines
11351137 {
11361138 union dpcd_edp_config edp_config_set;
11371139 bool panel_mode_edp = false;
1138− struct dc_context *dc_ctx = link->ctx;
1140+ DC_LOGGER_INIT(link->ctx->logger);
1141+
11391142 memset(&edp_config_set, '\0', sizeof(union dpcd_edp_config));
11401143
11411144 if (DP_PANEL_MODE_DEFAULT != panel_mode) {
@@ -1183,16 +1186,21 @@ static void enable_stream_features(struct pipe_ctx *pipe_ctx) · 41 unmodified lines
11831186 {
11841187 struct dc_stream_state *stream = pipe_ctx->stream;
11851188 struct dc_link *link = stream->sink->link;
1186− union down_spread_ctrl downspread;
1189+ union down_spread_ctrl old_downspread;
1190+ union down_spread_ctrl new_downspread;
11871191
11881192 core_link_read_dpcd(link, DP_DOWNSPREAD_CTRL,
1189− &downspread.raw, sizeof(downspread));
1193+ &old_downspread.raw, sizeof(old_downspread));
11901194
1191− downspread.bits.IGNORE_MSA_TIMING_PARAM =
1195+ new_downspread.raw = old_downspread.raw;
1196+
1197+ new_downspread.bits.IGNORE_MSA_TIMING_PARAM =
11921198 (stream->ignore_msa_timing_param) ? 1 : 0;
11931199
1194− core_link_write_dpcd(link, DP_DOWNSPREAD_CTRL,
1195− &downspread.raw, sizeof(downspread));
1200+ if (new_downspread.raw != old_downspread.raw) {
1201+ core_link_write_dpcd(link, DP_DOWNSPREAD_CTRL,
1202+ &new_downspread.raw, sizeof(new_downspread));
1203+ }
11961204 }
11971205
11981206 static enum dc_status enable_link_dp(
@@ -1843,9 +1851,22 @@ static void disable_link(struct dc_link *link, enum signal_type signal) · 644 unmodified lines
18431851
18441852 static bool dp_active_dongle_validate_timing(
18451853 const struct dc_crtc_timing *timing,
1846− const struct dc_dongle_caps *dongle_caps)
1854+ const struct dpcd_caps *dpcd_caps)
18471855 {
18481856 unsigned int required_pix_clk = timing->pix_clk_khz;
1857+ const struct dc_dongle_caps *dongle_caps = &dpcd_caps->dongle_caps;
1858+
1859+ switch (dpcd_caps->dongle_type) {
1860+ case DISPLAY_DONGLE_DP_VGA_CONVERTER:
1861+ case DISPLAY_DONGLE_DP_DVI_CONVERTER:
1862+ case DISPLAY_DONGLE_DP_DVI_DONGLE:
1863+ if (timing->pixel_encoding == PIXEL_ENCODING_RGB)
1864+ return true;
1865+ else
1866+ return false;
1867+ default:
1868+ break;
1869+ }
18491870
18501871 if (dongle_caps->dongle_type != DISPLAY_DONGLE_DP_HDMI_CONVERTER ||
18511872 dongle_caps->extendedCapValid == false)
@@ -1911,7 +1932,7 @@ enum dc_status dc_link_validate_mode_timing( · 59 unmodified lines
19111932 const struct dc_crtc_timing *timing)
19121933 {
19131934 uint32_t max_pix_clk = stream->sink->dongle_max_pix_clk;
1914− struct dc_dongle_caps *dongle_caps = &link->dpcd_caps.dongle_caps;
1935+ struct dpcd_caps *dpcd_caps = &link->dpcd_caps;
19151936
19161937 /* A hack to avoid failing any modes for EDID override feature on
19171938 * topology change such as lower quality cable for DP or different dongle
@@ -1924,7 +1945,7 @@ enum dc_status dc_link_validate_mode_timing( · 6 unmodified lines
19241945 return DC_EXCEED_DONGLE_CAP;
19251946
19261947 /* Active Dongle*/
1927− if (!dp_active_dongle_validate_timing(timing, dongle_caps))
1948+ if (!dp_active_dongle_validate_timing(timing, dpcd_caps))
19281949 return DC_EXCEED_DONGLE_CAP;
19291950
19301951 switch (stream->signal) {
@@ -1950,10 +1971,10 @@ bool dc_link_set_backlight_level(const struct dc_link *link, uint32_t level, · 19 unmodified lines
19501971 struct dc *core_dc = link->ctx->dc;
19511972 struct abm *abm = core_dc->res_pool->abm;
19521973 struct dmcu *dmcu = core_dc->res_pool->dmcu;
1953− struct dc_context *dc_ctx = link->ctx;
19541974 unsigned int controller_id = 0;
19551975 bool use_smooth_brightness = true;
19561976 int i;
1977+ DC_LOGGER_INIT(link->ctx->logger);
19571978
19581979 if ((dmcu == NULL) ||
19591980 (abm == NULL) ||
@@ -1961,7 +1982,7 @@ bool dc_link_set_backlight_level(const struct dc_link *link, uint32_t level, · 1 unmodified line
19611982 return false;
19621983
19631984 if (stream) {
1964− if (stream->bl_pwm_level == 0)
1985+ if (stream->bl_pwm_level == EDP_BACKLIGHT_RAMP_DISABLE_LEVEL)
19651986 frame_ramp = 0;
19661987
19671988 ((struct dc_stream_state *)stream)->bl_pwm_level = level;
@@ -2149,8 +2170,8 @@ static enum dc_status allocate_mst_payload(struct pipe_ctx *pipe_ctx) · 181 unmodified lines
21492170 struct fixed31_32 avg_time_slots_per_mtp;
21502171 struct fixed31_32 pbn;
21512172 struct fixed31_32 pbn_per_slot;
2152− struct dc_context *dc_ctx = link->ctx;
21532173 uint8_t i;
2174+ DC_LOGGER_INIT(link->ctx->logger);
21542175
21552176 /* enable_link_dp_mst already check link->enabled_stream_count
21562177 * and stream is in link->stream[]. This is called during set mode,
@@ -2178,11 +2199,11 @@ static enum dc_status allocate_mst_payload(struct pipe_ctx *pipe_ctx) · 21 unmodified lines
21782199 link->mst_stream_alloc_table.stream_count);
21792200
21802201 for (i = 0; i < MAX_CONTROLLER_NUM; i++) {
2181− DC_LOG_MST("stream_enc[%d]: 0x%x "
2202+ DC_LOG_MST("stream_enc[%d]: %p "
21822203 "stream[%d].vcp_id: %d "
21832204 "stream[%d].slot_count: %d\n",
21842205 i,
2185− link->mst_stream_alloc_table.stream_allocations[i].stream_enc,
2206+ (void *) link->mst_stream_alloc_table.stream_allocations[i].stream_enc,
21862207 i,
21872208 link->mst_stream_alloc_table.stream_allocations[i].vcp_id,
21882209 i,
@@ -2229,7 +2250,7 @@ static enum dc_status deallocate_mst_payload(struct pipe_ctx *pipe_ctx) · 40 unmodified lines
22292250 struct fixed31_32 avg_time_slots_per_mtp = dal_fixed31_32_from_int(0);
22302251 uint8_t i;
22312252 bool mst_mode = (link->type == dc_connection_mst_branch);
2232− struct dc_context *dc_ctx = link->ctx;
2253+ DC_LOGGER_INIT(link->ctx->logger);
22332254
22342255 /* deallocate_mst_payload is called before disable link. When mode or
22352256 * disable/enable monitor, new stream is created which is not in link
@@ -2268,11 +2289,11 @@ static enum dc_status deallocate_mst_payload(struct pipe_ctx *pipe_ctx) · 32 unmodified lines
22682289 link->mst_stream_alloc_table.stream_count);
22692290
22702291 for (i = 0; i < MAX_CONTROLLER_NUM; i++) {
2271− DC_LOG_MST("stream_enc[%d]: 0x%x "
2292+ DC_LOG_MST("stream_enc[%d]: %p "
22722293 "stream[%d].vcp_id: %d "
22732294 "stream[%d].slot_count: %d\n",
22742295 i,
2275− link->mst_stream_alloc_table.stream_allocations[i].stream_enc,
2296+ (void *) link->mst_stream_alloc_table.stream_allocations[i].stream_enc,
22762297 i,
22772298 link->mst_stream_alloc_table.stream_allocations[i].vcp_id,
22782299 i,
@@ -2302,8 +2323,8 @@ void core_link_enable_stream( · 23 unmodified lines
23022323 struct pipe_ctx *pipe_ctx)
23032324 {
23042325 struct dc *core_dc = pipe_ctx->stream->ctx->dc;
2305− struct dc_context *dc_ctx = pipe_ctx->stream->ctx;
23062326 enum dc_status status;
2327+ DC_LOGGER_INIT(pipe_ctx->stream->ctx->logger);
23072328
23082329 /* eDP lit up by bios already, no need to enable again. */
23092330 if (pipe_ctx->stream->signal == SIGNAL_TYPE_EDP &&
drivers/gpu/drm/amd/display/dc/core/dc_link_ddc.c+7−3
@@ -629,13 +629,14 @@ bool dal_ddc_service_query_ddc_data( · 628 unmodified lines
629629 return ret;
630630 }
631631
632−ssize_t dal_ddc_service_read_dpcd_data(
632+enum ddc_result dal_ddc_service_read_dpcd_data(
633633 struct ddc_service *ddc,
634634 bool i2c,
635635 enum i2c_mot_mode mot,
636636 uint32_t address,
637637 uint8_t *data,
638− uint32_t len)
638+ uint32_t len,
639+ uint32_t *read)
639640 {
640641 struct aux_payload read_payload = {
641642 .i2c_over_aux = i2c,
@@ -652,6 +653,8 @@ ssize_t dal_ddc_service_read_dpcd_data( · 10 unmodified lines
652653 .mot = mot
653654 };
654655
656+ *read = 0;
657+
655658 if (len > DEFAULT_AUX_MAX_DATA_SIZE) {
656659 BREAK_TO_DEBUGGER();
657660 return DDC_RESULT_FAILED_INVALID_OPERATION;
@@ -661,7 +664,8 @@ ssize_t dal_ddc_service_read_dpcd_data( · 3 unmodified lines
661664 ddc->ctx->i2caux,
662665 ddc->ddc_pin,
663666 &command)) {
664− return (ssize_t)command.payloads->length;
667+ *read = command.payloads->length;
668+ return DDC_RESULT_SUCESSFULL;
665669 }
666670
667671 return DDC_RESULT_FAILED_OPERATION;
drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c+23−7
@@ -1378,8 +1378,8 @@ static uint32_t bandwidth_in_kbps_from_timing( · 1377 unmodified lines
13781378 {
13791379 uint32_t bits_per_channel = 0;
13801380 uint32_t kbps;
1381− switch (timing->display_color_depth) {
13821381
1382+ switch (timing->display_color_depth) {
13831383 case COLOR_DEPTH_666:
13841384 bits_per_channel = 6;
13851385 break;
@@ -1401,14 +1401,20 @@ static uint32_t bandwidth_in_kbps_from_timing( · 15 unmodified lines
14011401 default:
14021402 break;
14031403 }
1404+
14041405 ASSERT(bits_per_channel != 0);
14051406
14061407 kbps = timing->pix_clk_khz;
14071408 kbps *= bits_per_channel;
14081409
1409− if (timing->flags.Y_ONLY != 1)
1410+ if (timing->flags.Y_ONLY != 1) {
14101411 /*Only YOnly make reduce bandwidth by 1/3 compares to RGB*/
14111412 kbps *= 3;
1413+ if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR420)
1414+ kbps /= 2;
1415+ else if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR422)
1416+ kbps = kbps * 2 / 3;
1417+ }
14121418
14131419 return kbps;
14141420
@@ -2278,6 +2284,8 @@ static bool retrieve_link_cap(struct dc_link *link) · 863 unmodified lines
22782284 union edp_configuration_cap edp_config_cap;
22792285 union dp_downstream_port_present ds_port = { 0 };
22802286 enum dc_status status = DC_ERROR_UNEXPECTED;
2287+ uint32_t read_dpcd_retry_cnt = 3;
2288+ int i;
22812289
22822290 memset(dpcd_data, '\0', sizeof(dpcd_data));
22832291 memset(&down_strm_port_count,
@@ -2285,11 +2293,15 @@ static bool retrieve_link_cap(struct dc_link *link) · 1 unmodified line
22852293 memset(&edp_config_cap, '\0',
22862294 sizeof(union edp_configuration_cap));
22872295
2288− status = core_link_read_dpcd(
2289− link,
2290− DP_DPCD_REV,
2291− dpcd_data,
2292− sizeof(dpcd_data));
2296+ for (i = 0; i < read_dpcd_retry_cnt; i++) {
2297+ status = core_link_read_dpcd(
2298+ link,
2299+ DP_DPCD_REV,
2300+ dpcd_data,
2301+ sizeof(dpcd_data));
2302+ if (status == DC_OK)
2303+ break;
2304+ }
22932305
22942306 if (status != DC_OK) {
22952307 dm_error("%s: Read dpcd data failed.\n", __func__);
@@ -2376,6 +2388,10 @@ bool detect_dp_sink_caps(struct dc_link *link) · 80 unmodified lines
23762388 void detect_edp_sink_caps(struct dc_link *link)
23772389 {
23782390 retrieve_link_cap(link);
2391+
2392+ if (link->reported_link_cap.link_rate == LINK_RATE_UNKNOWN)
2393+ link->reported_link_cap.link_rate = LINK_RATE_HIGH2;
2394+
23792395 link->verified_link_cap = link->reported_link_cap;
23802396 }
23812397
drivers/gpu/drm/amd/display/dc/core/dc_resource.c+94−178
@@ -45,8 +45,9 @@ · 44 unmodified lines
4545 #include "dcn10/dcn10_resource.h"
4646 #endif
4747 #include "dce120/dce120_resource.h"
48−#define DC_LOGGER \
49− ctx->logger
48+
49+#define DC_LOGGER_INIT(logger)
50+
5051 enum dce_version resource_parse_asic_id(struct hw_asic_id asic_id)
5152 {
5253 enum dce_version dc_version = DCE_VERSION_UNKNOWN;
@@ -78,6 +79,10 @@ enum dce_version resource_parse_asic_id(struct hw_asic_id asic_id) · 25 unmodified lines
7879 ASIC_REV_IS_POLARIS12_V(asic_id.hw_internal_rev)) {
7980 dc_version = DCE_VERSION_11_2;
8081 }
82+#if defined(CONFIG_DRM_AMD_DC_VEGAM)
83+ if (ASIC_REV_IS_VEGAM(asic_id.hw_internal_rev))
84+ dc_version = DCE_VERSION_11_22;
85+#endif
8186 break;
8287 case FAMILY_AI:
8388 dc_version = DCE_VERSION_12_0;
@@ -124,6 +129,9 @@ struct resource_pool *dc_create_resource_pool( · 40 unmodified lines
124129 num_virtual_links, dc, asic_id);
125130 break;
126131 case DCE_VERSION_11_2:
132+#if defined(CONFIG_DRM_AMD_DC_VEGAM)
133+ case DCE_VERSION_11_22:
134+#endif
127135 res_pool = dce112_create_resource_pool(
128136 num_virtual_links, dc);
129137 break;
@@ -835,7 +843,7 @@ bool resource_build_scaling_params(struct pipe_ctx *pipe_ctx) · 705 unmodified lines
835843 struct dc_crtc_timing *timing = &pipe_ctx->stream->timing;
836844 struct view recout_skip = { 0 };
837845 bool res = false;
838− struct dc_context *ctx = pipe_ctx->stream->ctx;
846+ DC_LOGGER_INIT(pipe_ctx->stream->ctx->logger);
839847 /* Important: scaling ratio calculation requires pixel format,
840848 * lb depth calculation requires recout and taps require scaling ratios.
841849 * Inits require viewport, taps, ratios and recout of split pipe
@@ -843,6 +851,9 @@ bool resource_build_scaling_params(struct pipe_ctx *pipe_ctx) · 1 unmodified line
843851 pipe_ctx->plane_res.scl_data.format = convert_pixel_format_to_dalsurface(
844852 pipe_ctx->plane_state->format);
845853
854+ if (pipe_ctx->stream->timing.flags.INTERLACE)
855+ pipe_ctx->stream->dst.height *= 2;
856+
846857 calculate_scaling_ratios(pipe_ctx);
847858
848859 calculate_viewport(pipe_ctx);
@@ -863,6 +874,8 @@ bool resource_build_scaling_params(struct pipe_ctx *pipe_ctx) · 14 unmodified lines
863874
864875 pipe_ctx->plane_res.scl_data.h_active = timing->h_addressable + timing->h_border_left + timing->h_border_right;
865876 pipe_ctx->plane_res.scl_data.v_active = timing->v_addressable + timing->v_border_top + timing->v_border_bottom;
877+ if (pipe_ctx->stream->timing.flags.INTERLACE)
878+ pipe_ctx->plane_res.scl_data.v_active *= 2;
866879
867880
868881 /* Taps calculations */
@@ -908,6 +921,9 @@ bool resource_build_scaling_params(struct pipe_ctx *pipe_ctx) · 39 unmodified lines
908921 plane_state->dst_rect.x,
909922 plane_state->dst_rect.y);
910923
924+ if (pipe_ctx->stream->timing.flags.INTERLACE)
925+ pipe_ctx->stream->dst.height /= 2;
926+
911927 return res;
912928 }
913929
@@ -1294,6 +1310,19 @@ bool dc_add_all_planes_for_stream( · 380 unmodified lines
12941310 }
12951311
12961312
1313+static bool is_hdr_static_meta_changed(struct dc_stream_state *cur_stream,
1314+ struct dc_stream_state *new_stream)
1315+{
1316+ if (cur_stream == NULL)
1317+ return true;
1318+
1319+ if (memcmp(&cur_stream->hdr_static_metadata,
1320+ &new_stream->hdr_static_metadata,
1321+ sizeof(struct dc_info_packet)) != 0)
1322+ return true;
1323+
1324+ return false;
1325+}
12971326
12981327 static bool is_timing_changed(struct dc_stream_state *cur_stream,
12991328 struct dc_stream_state *new_stream)
@@ -1329,6 +1358,9 @@ static bool are_stream_backends_same( · 29 unmodified lines
13291358 if (is_timing_changed(stream_a, stream_b))
13301359 return false;
13311360
1361+ if (is_hdr_static_meta_changed(stream_a, stream_b))
1362+ return false;
1363+
13321364 return true;
13331365 }
13341366
@@ -1599,18 +1631,6 @@ enum dc_status dc_remove_stream_from_ctx( · 264 unmodified lines
15991631 return DC_OK;
16001632 }
16011633
1602−static void copy_pipe_ctx(
1603− const struct pipe_ctx *from_pipe_ctx, struct pipe_ctx *to_pipe_ctx)
1604−{
1605− struct dc_plane_state *plane_state = to_pipe_ctx->plane_state;
1606− struct dc_stream_state *stream = to_pipe_ctx->stream;
1607−
1608− *to_pipe_ctx = *from_pipe_ctx;
1609− to_pipe_ctx->stream = stream;
1610− if (plane_state != NULL)
1611− to_pipe_ctx->plane_state = plane_state;
1612−}
1613−
16141634 static struct dc_stream_state *find_pll_sharable_stream(
16151635 struct dc_stream_state *stream_needs_pll,
16161636 struct dc_state *context)
@@ -1703,7 +1723,7 @@ enum dc_status resource_map_pool_resources( · 86 unmodified lines
17031723 pipe_idx = acquire_first_split_pipe(&context->res_ctx, pool, stream);
17041724 #endif
17051725
1706− if (pipe_idx < 0)
1726+ if (pipe_idx < 0 || context->res_ctx.pipe_ctx[pipe_idx].stream_res.tg == NULL)
17071727 return DC_NO_CONTROLLER_RESOURCE;
17081728
17091729 pipe_ctx = &context->res_ctx.pipe_ctx[pipe_idx];
@@ -1752,26 +1772,6 @@ enum dc_status resource_map_pool_resources( · 42 unmodified lines
17521772 return DC_ERROR_UNEXPECTED;
17531773 }
17541774
1755−/* first stream in the context is used to populate the rest */
1756−void validate_guaranteed_copy_streams(
1757− struct dc_state *context,
1758− int max_streams)
1759−{
1760− int i;
1761−
1762− for (i = 1; i < max_streams; i++) {
1763− context->streams[i] = context->streams[0];
1764−
1765− copy_pipe_ctx(&context->res_ctx.pipe_ctx[0],
1766− &context->res_ctx.pipe_ctx[i]);
1767− context->res_ctx.pipe_ctx[i].stream =
1768− context->res_ctx.pipe_ctx[0].stream;
1769−
1770− dc_stream_retain(context->streams[i]);
1771− context->stream_count++;
1772− }
1773−}
1774−
17751775 void dc_resource_state_copy_construct_current(
17761776 const struct dc *dc,
17771777 struct dc_state *dst_ctx)
@@ -1798,9 +1798,9 @@ enum dc_status dc_validate_global_state( · 20 unmodified lines
17981798 return DC_ERROR_UNEXPECTED;
17991799
18001800 if (dc->res_pool->funcs->validate_global) {
1801− result = dc->res_pool->funcs->validate_global(dc, new_ctx);
1802− if (result != DC_OK)
1803− return result;
1801+ result = dc->res_pool->funcs->validate_global(dc, new_ctx);
1802+ if (result != DC_OK)
1803+ return result;
18041804 }
18051805
18061806 for (i = 0; i < new_ctx->stream_count; i++) {
@@ -1843,7 +1843,7 @@ enum dc_status dc_validate_global_state( · 36 unmodified lines
18431843 }
18441844
18451845 static void patch_gamut_packet_checksum(
1846− struct encoder_info_packet *gamut_packet)
1846+ struct dc_info_packet *gamut_packet)
18471847 {
18481848 /* For gamut we recalc checksum */
18491849 if (gamut_packet->valid) {
@@ -1862,12 +1862,11 @@ static void patch_gamut_packet_checksum( · 12 unmodified lines
18621862 }
18631863
18641864 static void set_avi_info_frame(
1865− struct encoder_info_packet *info_packet,
1865+ struct dc_info_packet *info_packet,
18661866 struct pipe_ctx *pipe_ctx)
18671867 {
18681868 struct dc_stream_state *stream = pipe_ctx->stream;
18691869 enum dc_color_space color_space = COLOR_SPACE_UNKNOWN;
1870− struct info_frame info_frame = { {0} };
18711870 uint32_t pixel_encoding = 0;
18721871 enum scanning_type scan_type = SCANNING_TYPE_NODATA;
18731872 enum dc_aspect_ratio aspect = ASPECT_RATIO_NO_DATA;
@@ -1877,22 +1876,24 @@ static void set_avi_info_frame( · 3 unmodified lines
18771876 unsigned int cn0_cn1_value = 0;
18781877 uint8_t *check_sum = NULL;
18791878 uint8_t byte_index = 0;
1880− union hdmi_info_packet *hdmi_info = &info_frame.avi_info_packet.info_packet_hdmi;
1879+ union hdmi_info_packet hdmi_info;
18811880 union display_content_support support = {0};
18821881 unsigned int vic = pipe_ctx->stream->timing.vic;
18831882 enum dc_timing_3d_format format;
18841883
1884+ memset(&hdmi_info, 0, sizeof(union hdmi_info_packet));
1885+
18851886 color_space = pipe_ctx->stream->output_color_space;
18861887 if (color_space == COLOR_SPACE_UNKNOWN)
18871888 color_space = (stream->timing.pixel_encoding == PIXEL_ENCODING_RGB) ?
18881889 COLOR_SPACE_SRGB:COLOR_SPACE_YCBCR709;
18891890
18901891 /* Initialize header */
1891− hdmi_info->bits.header.info_frame_type = HDMI_INFOFRAME_TYPE_AVI;
1892+ hdmi_info.bits.header.info_frame_type = HDMI_INFOFRAME_TYPE_AVI;
18921893 /* InfoFrameVersion_3 is defined by CEA861F (Section 6.4), but shall
18931894 * not be used in HDMI 2.0 (Section 10.1) */
1894− hdmi_info->bits.header.version = 2;
1895− hdmi_info->bits.header.length = HDMI_AVI_INFOFRAME_SIZE;
1895+ hdmi_info.bits.header.version = 2;
1896+ hdmi_info.bits.header.length = HDMI_AVI_INFOFRAME_SIZE;
18961897
18971898 /*
18981899 * IDO-defined (Y2,Y1,Y0 = 1,1,1) shall not be used by devices built
@@ -1918,39 +1919,39 @@ static void set_avi_info_frame( · 19 unmodified lines
19181919
19191920 /* Y0_Y1_Y2 : The pixel encoding */
19201921 /* H14b AVI InfoFrame has extension on Y-field from 2 bits to 3 bits */
1921− hdmi_info->bits.Y0_Y1_Y2 = pixel_encoding;
1922+ hdmi_info.bits.Y0_Y1_Y2 = pixel_encoding;
19221923
19231924 /* A0 = 1 Active Format Information valid */
1924− hdmi_info->bits.A0 = ACTIVE_FORMAT_VALID;
1925+ hdmi_info.bits.A0 = ACTIVE_FORMAT_VALID;
19251926
19261927 /* B0, B1 = 3; Bar info data is valid */
1927− hdmi_info->bits.B0_B1 = BAR_INFO_BOTH_VALID;
1928+ hdmi_info.bits.B0_B1 = BAR_INFO_BOTH_VALID;
19281929
1929− hdmi_info->bits.SC0_SC1 = PICTURE_SCALING_UNIFORM;
1930+ hdmi_info.bits.SC0_SC1 = PICTURE_SCALING_UNIFORM;
19301931
19311932 /* S0, S1 : Underscan / Overscan */
19321933 /* TODO: un-hardcode scan type */
19331934 scan_type = SCANNING_TYPE_UNDERSCAN;
1934− hdmi_info->bits.S0_S1 = scan_type;
1935+ hdmi_info.bits.S0_S1 = scan_type;
19351936
19361937 /* C0, C1 : Colorimetry */
19371938 if (color_space == COLOR_SPACE_YCBCR709 ||
19381939 color_space == COLOR_SPACE_YCBCR709_LIMITED)
1939− hdmi_info->bits.C0_C1 = COLORIMETRY_ITU709;
1940+ hdmi_info.bits.C0_C1 = COLORIMETRY_ITU709;
19401941 else if (color_space == COLOR_SPACE_YCBCR601 ||
19411942 color_space == COLOR_SPACE_YCBCR601_LIMITED)
1942− hdmi_info->bits.C0_C1 = COLORIMETRY_ITU601;
1943+ hdmi_info.bits.C0_C1 = COLORIMETRY_ITU601;
19431944 else {
1944− hdmi_info->bits.C0_C1 = COLORIMETRY_NO_DATA;
1945+ hdmi_info.bits.C0_C1 = COLORIMETRY_NO_DATA;
19451946 }
19461947 if (color_space == COLOR_SPACE_2020_RGB_FULLRANGE ||
19471948 color_space == COLOR_SPACE_2020_RGB_LIMITEDRANGE ||
19481949 color_space == COLOR_SPACE_2020_YCBCR) {
1949− hdmi_info->bits.EC0_EC2 = COLORIMETRYEX_BT2020RGBYCBCR;
1950− hdmi_info->bits.C0_C1 = COLORIMETRY_EXTENDED;
1950+ hdmi_info.bits.EC0_EC2 = COLORIMETRYEX_BT2020RGBYCBCR;
1951+ hdmi_info.bits.C0_C1 = COLORIMETRY_EXTENDED;
19511952 } else if (color_space == COLOR_SPACE_ADOBERGB) {
1952− hdmi_info->bits.EC0_EC2 = COLORIMETRYEX_ADOBERGB;
1953− hdmi_info->bits.C0_C1 = COLORIMETRY_EXTENDED;
1953+ hdmi_info.bits.EC0_EC2 = COLORIMETRYEX_ADOBERGB;
1954+ hdmi_info.bits.C0_C1 = COLORIMETRY_EXTENDED;
19541955 }
19551956
19561957 /* TODO: un-hardcode aspect ratio */
@@ -1959,18 +1960,18 @@ static void set_avi_info_frame( · 2 unmodified lines
19591960 switch (aspect) {
19601961 case ASPECT_RATIO_4_3:
19611962 case ASPECT_RATIO_16_9:
1962− hdmi_info->bits.M0_M1 = aspect;
1963+ hdmi_info.bits.M0_M1 = aspect;
19631964 break;
19641965
19651966 case ASPECT_RATIO_NO_DATA:
19661967 case ASPECT_RATIO_64_27:
19671968 case ASPECT_RATIO_256_135:
19681969 default:
1969− hdmi_info->bits.M0_M1 = 0;
1970+ hdmi_info.bits.M0_M1 = 0;
19701971 }
19711972
19721973 /* Active Format Aspect ratio - same as Picture Aspect Ratio. */
1973− hdmi_info->bits.R0_R3 = ACTIVE_FORMAT_ASPECT_RATIO_SAME_AS_PICTURE;
1974+ hdmi_info.bits.R0_R3 = ACTIVE_FORMAT_ASPECT_RATIO_SAME_AS_PICTURE;
19741975
19751976 /* TODO: un-hardcode cn0_cn1 and itc */
19761977
@@ -2013,8 +2014,8 @@ static void set_avi_info_frame( · 36 unmodified lines
20132014 }
20142015 }
20152016 }
2016− hdmi_info->bits.CN0_CN1 = cn0_cn1_value;
2017− hdmi_info->bits.ITC = itc_value;
2017+ hdmi_info.bits.CN0_CN1 = cn0_cn1_value;
2018+ hdmi_info.bits.ITC = itc_value;
20182019 }
20192020
20202021 /* TODO : We should handle YCC quantization */
@@ -2023,19 +2024,19 @@ static void set_avi_info_frame( · 2 unmodified lines
20232024 stream->sink->edid_caps.qy_bit == 1) {
20242025 if (color_space == COLOR_SPACE_SRGB ||
20252026 color_space == COLOR_SPACE_2020_RGB_FULLRANGE) {
2026− hdmi_info->bits.Q0_Q1 = RGB_QUANTIZATION_FULL_RANGE;
2027− hdmi_info->bits.YQ0_YQ1 = YYC_QUANTIZATION_FULL_RANGE;
2027+ hdmi_info.bits.Q0_Q1 = RGB_QUANTIZATION_FULL_RANGE;
2028+ hdmi_info.bits.YQ0_YQ1 = YYC_QUANTIZATION_FULL_RANGE;
20282029 } else if (color_space == COLOR_SPACE_SRGB_LIMITED ||
20292030 color_space == COLOR_SPACE_2020_RGB_LIMITEDRANGE) {
2030− hdmi_info->bits.Q0_Q1 = RGB_QUANTIZATION_LIMITED_RANGE;
2031− hdmi_info->bits.YQ0_YQ1 = YYC_QUANTIZATION_LIMITED_RANGE;
2031+ hdmi_info.bits.Q0_Q1 = RGB_QUANTIZATION_LIMITED_RANGE;
2032+ hdmi_info.bits.YQ0_YQ1 = YYC_QUANTIZATION_LIMITED_RANGE;
20322033 } else {
2033− hdmi_info->bits.Q0_Q1 = RGB_QUANTIZATION_DEFAULT_RANGE;
2034− hdmi_info->bits.YQ0_YQ1 = YYC_QUANTIZATION_LIMITED_RANGE;
2034+ hdmi_info.bits.Q0_Q1 = RGB_QUANTIZATION_DEFAULT_RANGE;
2035+ hdmi_info.bits.YQ0_YQ1 = YYC_QUANTIZATION_LIMITED_RANGE;
20352036 }
20362037 } else {
2037− hdmi_info->bits.Q0_Q1 = RGB_QUANTIZATION_DEFAULT_RANGE;
2038− hdmi_info->bits.YQ0_YQ1 = YYC_QUANTIZATION_LIMITED_RANGE;
2038+ hdmi_info.bits.Q0_Q1 = RGB_QUANTIZATION_DEFAULT_RANGE;
2039+ hdmi_info.bits.YQ0_YQ1 = YYC_QUANTIZATION_LIMITED_RANGE;
20392040 }
20402041
20412042 ///VIC
@@ -2060,51 +2061,49 @@ static void set_avi_info_frame( · 18 unmodified lines
20602061 break;
20612062 }
20622063 }
2063− hdmi_info->bits.VIC0_VIC7 = vic;
2064+ hdmi_info.bits.VIC0_VIC7 = vic;
20642065
20652066 /* pixel repetition
20662067 * PR0 - PR3 start from 0 whereas pHwPathMode->mode.timing.flags.pixel
20672068 * repetition start from 1 */
2068− hdmi_info->bits.PR0_PR3 = 0;
2069+ hdmi_info.bits.PR0_PR3 = 0;
20692070
20702071 /* Bar Info
20712072 * barTop: Line Number of End of Top Bar.
20722073 * barBottom: Line Number of Start of Bottom Bar.
20732074 * barLeft: Pixel Number of End of Left Bar.
20742075 * barRight: Pixel Number of Start of Right Bar. */
2075− hdmi_info->bits.bar_top = stream->timing.v_border_top;
2076− hdmi_info->bits.bar_bottom = (stream->timing.v_total
2076+ hdmi_info.bits.bar_top = stream->timing.v_border_top;
2077+ hdmi_info.bits.bar_bottom = (stream->timing.v_total
20772078 - stream->timing.v_border_bottom + 1);
2078− hdmi_info->bits.bar_left = stream->timing.h_border_left;
2079− hdmi_info->bits.bar_right = (stream->timing.h_total
2079+ hdmi_info.bits.bar_left = stream->timing.h_border_left;
2080+ hdmi_info.bits.bar_right = (stream->timing.h_total
20802081 - stream->timing.h_border_right + 1);
20812082
20822083 /* check_sum - Calculate AFMT_AVI_INFO0 ~ AFMT_AVI_INFO3 */
2083− check_sum = &info_frame.avi_info_packet.info_packet_hdmi.packet_raw_data.sb[0];
2084+ check_sum = &hdmi_info.packet_raw_data.sb[0];
20842085
20852086 *check_sum = HDMI_INFOFRAME_TYPE_AVI + HDMI_AVI_INFOFRAME_SIZE + 2;
20862087
20872088 for (byte_index = 1; byte_index <= HDMI_AVI_INFOFRAME_SIZE; byte_index++)
2088− *check_sum += hdmi_info->packet_raw_data.sb[byte_index];
2089+ *check_sum += hdmi_info.packet_raw_data.sb[byte_index];
20892090
20902091 /* one byte complement */
20912092 *check_sum = (uint8_t) (0x100 - *check_sum);
20922093
20932094 /* Store in hw_path_mode */
2094− info_packet->hb0 = hdmi_info->packet_raw_data.hb0;
2095− info_packet->hb1 = hdmi_info->packet_raw_data.hb1;
2096− info_packet->hb2 = hdmi_info->packet_raw_data.hb2;
2095+ info_packet->hb0 = hdmi_info.packet_raw_data.hb0;
2096+ info_packet->hb1 = hdmi_info.packet_raw_data.hb1;
2097+ info_packet->hb2 = hdmi_info.packet_raw_data.hb2;
20972098
2098− for (byte_index = 0; byte_index < sizeof(info_frame.avi_info_packet.
2099− info_packet_hdmi.packet_raw_data.sb); byte_index++)
2100− info_packet->sb[byte_index] = info_frame.avi_info_packet.
2101− info_packet_hdmi.packet_raw_data.sb[byte_index];
2099+ for (byte_index = 0; byte_index < sizeof(hdmi_info.packet_raw_data.sb); byte_index++)
2100+ info_packet->sb[byte_index] = hdmi_info.packet_raw_data.sb[byte_index];
21022101
21032102 info_packet->valid = true;
21042103 }
21052104
21062105 static void set_vendor_info_packet(
2107− struct encoder_info_packet *info_packet,
2106+ struct dc_info_packet *info_packet,
21082107 struct dc_stream_state *stream)
21092108 {
21102109 uint32_t length = 0;
@@ -2217,7 +2216,7 @@ static void set_vendor_info_packet( · 106 unmodified lines
22172216 }
22182217
22192218 static void set_spd_info_packet(
2220− struct encoder_info_packet *info_packet,
2219+ struct dc_info_packet *info_packet,
22212220 struct dc_stream_state *stream)
22222221 {
22232222 /* SPD info packet for FreeSync */
@@ -2338,104 +2337,19 @@ static void set_spd_info_packet( · 114 unmodified lines
23382337 }
23392338
23402339 static void set_hdr_static_info_packet(
2341− struct encoder_info_packet *info_packet,
2340+ struct dc_info_packet *info_packet,
23422341 struct dc_stream_state *stream)
23432342 {
2344− uint16_t i = 0;
2345− enum signal_type signal = stream->signal;
2346− uint32_t data;
2343+ /* HDR Static Metadata info packet for HDR10 */
23472344
2348− if (!stream->hdr_static_metadata.hdr_supported)
2345+ if (!stream->hdr_static_metadata.valid)
23492346 return;
23502347
2351− if (dc_is_hdmi_signal(signal)) {
2352− info_packet->valid = true;
2353−
2354− info_packet->hb0 = 0x87;
2355− info_packet->hb1 = 0x01;
2356− info_packet->hb2 = 0x1A;
2357− i = 1;
2358− } else if (dc_is_dp_signal(signal)) {
2359− info_packet->valid = true;
2360−
2361− info_packet->hb0 = 0x00;
2362− info_packet->hb1 = 0x87;
2363− info_packet->hb2 = 0x1D;
2364− info_packet->hb3 = (0x13 << 2);
2365− i = 2;
2366− }
2367−
2368− data = stream->hdr_static_metadata.is_hdr;
2369− info_packet->sb[i++] = data ? 0x02 : 0x00;
2370− info_packet->sb[i++] = 0x00;
2371−
2372− data = stream->hdr_static_metadata.chromaticity_green_x / 2;
2373− info_packet->sb[i++] = data & 0xFF;
2374− info_packet->sb[i++] = (data & 0xFF00) >> 8;
2375−
2376− data = stream->hdr_static_metadata.chromaticity_green_y / 2;
2377− info_packet->sb[i++] = data & 0xFF;
2378− info_packet->sb[i++] = (data & 0xFF00) >> 8;
2379−
2380− data = stream->hdr_static_metadata.chromaticity_blue_x / 2;
2381− info_packet->sb[i++] = data & 0xFF;
2382− info_packet->sb[i++] = (data & 0xFF00) >> 8;
2383−
2384− data = stream->hdr_static_metadata.chromaticity_blue_y / 2;
2385− info_packet->sb[i++] = data & 0xFF;
2386− info_packet->sb[i++] = (data & 0xFF00) >> 8;
2387−
2388− data = stream->hdr_static_metadata.chromaticity_red_x / 2;
2389− info_packet->sb[i++] = data & 0xFF;
2390− info_packet->sb[i++] = (data & 0xFF00) >> 8;
2391−
2392− data = stream->hdr_static_metadata.chromaticity_red_y / 2;
2393− info_packet->sb[i++] = data & 0xFF;
2394− info_packet->sb[i++] = (data & 0xFF00) >> 8;
2395−
2396− data = stream->hdr_static_metadata.chromaticity_white_point_x / 2;
2397− info_packet->sb[i++] = data & 0xFF;
2398− info_packet->sb[i++] = (data & 0xFF00) >> 8;
2399−
2400− data = stream->hdr_static_metadata.chromaticity_white_point_y / 2;
2401− info_packet->sb[i++] = data & 0xFF;
2402− info_packet->sb[i++] = (data & 0xFF00) >> 8;
2403−
2404− data = stream->hdr_static_metadata.max_luminance;
2405− info_packet->sb[i++] = data & 0xFF;
2406− info_packet->sb[i++] = (data & 0xFF00) >> 8;
2407−
2408− data = stream->hdr_static_metadata.min_luminance;
2409− info_packet->sb[i++] = data & 0xFF;
2410− info_packet->sb[i++] = (data & 0xFF00) >> 8;
2411−
2412− data = stream->hdr_static_metadata.maximum_content_light_level;
2413− info_packet->sb[i++] = data & 0xFF;
2414− info_packet->sb[i++] = (data & 0xFF00) >> 8;
2415−
2416− data = stream->hdr_static_metadata.maximum_frame_average_light_level;
2417− info_packet->sb[i++] = data & 0xFF;
2418− info_packet->sb[i++] = (data & 0xFF00) >> 8;
2419−
2420− if (dc_is_hdmi_signal(signal)) {
2421− uint32_t checksum = 0;
2422−
2423− checksum += info_packet->hb0;
2424− checksum += info_packet->hb1;
2425− checksum += info_packet->hb2;
2426−
2427− for (i = 1; i <= info_packet->hb2; i++)
2428− checksum += info_packet->sb[i];
2429−
2430− info_packet->sb[0] = 0x100 - checksum;
2431− } else if (dc_is_dp_signal(signal)) {
2432− info_packet->sb[0] = 0x01;
2433− info_packet->sb[1] = 0x1A;
2434− }
2348+ *info_packet = stream->hdr_static_metadata;
24352349 }
24362350
24372351 static void set_vsc_info_packet(
2438− struct encoder_info_packet *info_packet,
2352+ struct dc_info_packet *info_packet,
24392353 struct dc_stream_state *stream)
24402354 {
24412355 unsigned int vscPacketRevision = 0;
@@ -2650,6 +2564,8 @@ bool pipe_need_reprogram( · 208 unmodified lines
26502564 if (is_timing_changed(pipe_ctx_old->stream, pipe_ctx->stream))
26512565 return true;
26522566
2567+ if (is_hdr_static_meta_changed(pipe_ctx_old->stream, pipe_ctx->stream))
2568+ return true;
26532569
26542570 return false;
26552571 }
drivers/gpu/drm/amd/display/dc/core/dc_stream.c+22−2
@@ -101,14 +101,16 @@ static void construct(struct dc_stream_state *stream, · 100 unmodified lines
101101 stream->status.link = stream->sink->link;
102102
103103 update_stream_signal(stream);
104+
105+ stream->out_transfer_func = dc_create_transfer_func();
106+ stream->out_transfer_func->type = TF_TYPE_BYPASS;
104107 }
105108
106109 static void destruct(struct dc_stream_state *stream)
107110 {
108111 dc_sink_release(stream->sink);
109112 if (stream->out_transfer_func != NULL) {
110− dc_transfer_func_release(
111− stream->out_transfer_func);
113+ dc_transfer_func_release(stream->out_transfer_func);
112114 stream->out_transfer_func = NULL;
113115 }
114116 }
@@ -176,6 +178,7 @@ bool dc_stream_set_cursor_attributes( · 61 unmodified lines
176178 int i;
177179 struct dc *core_dc;
178180 struct resource_context *res_ctx;
181+ struct pipe_ctx *pipe_to_program = NULL;
179182
180183 if (NULL == stream) {
181184 dm_error("DC: dc_stream is NULL!\n");
@@ -203,9 +206,17 @@ bool dc_stream_set_cursor_attributes( · 21 unmodified lines
203206 if (pipe_ctx->top_pipe && pipe_ctx->plane_state != pipe_ctx->top_pipe->plane_state)
204207 continue;
205208
209+ if (!pipe_to_program) {
210+ pipe_to_program = pipe_ctx;
211+ core_dc->hwss.pipe_control_lock(core_dc, pipe_to_program, true);
212+ }
206213
207214 core_dc->hwss.set_cursor_attribute(pipe_ctx);
208215 }
216+
217+ if (pipe_to_program)
218+ core_dc->hwss.pipe_control_lock(core_dc, pipe_to_program, false);
219+
209220 return true;
210221 }
211222
@@ -216,6 +227,7 @@ bool dc_stream_set_cursor_position( · 4 unmodified lines
216227 int i;
217228 struct dc *core_dc;
218229 struct resource_context *res_ctx;
230+ struct pipe_ctx *pipe_to_program = NULL;
219231
220232 if (NULL == stream) {
221233 dm_error("DC: dc_stream is NULL!\n");
@@ -241,9 +253,17 @@ bool dc_stream_set_cursor_position( · 19 unmodified lines
241253 !pipe_ctx->plane_res.ipp)
242254 continue;
243255
256+ if (!pipe_to_program) {
257+ pipe_to_program = pipe_ctx;
258+ core_dc->hwss.pipe_control_lock(core_dc, pipe_to_program, true);
259+ }
260+
244261 core_dc->hwss.set_cursor_position(pipe_ctx);
245262 }
246263
264+ if (pipe_to_program)
265+ core_dc->hwss.pipe_control_lock(core_dc, pipe_to_program, false);
266+
247267 return true;
248268 }
249269
drivers/gpu/drm/amd/display/dc/core/dc_surface.c+14−8
@@ -38,6 +38,12 @@ · 37 unmodified lines
3838 static void construct(struct dc_context *ctx, struct dc_plane_state *plane_state)
3939 {
4040 plane_state->ctx = ctx;
41+
42+ plane_state->gamma_correction = dc_create_gamma();
43+ plane_state->gamma_correction->is_identity = true;
44+
45+ plane_state->in_transfer_func = dc_create_transfer_func();
46+ plane_state->in_transfer_func->type = TF_TYPE_BYPASS;
4147 }
4248
4349 static void destruct(struct dc_plane_state *plane_state)
@@ -66,8 +72,8 @@ struct dc_plane_state *dc_create_plane_state(struct dc *dc) · 22 unmodified lines
6672 {
6773 struct dc *core_dc = dc;
6874
69− struct dc_plane_state *plane_state = kzalloc(sizeof(*plane_state),
70− GFP_KERNEL);
75+ struct dc_plane_state *plane_state = kvzalloc(sizeof(*plane_state),
76+ GFP_KERNEL);
7177
7278 if (NULL == plane_state)
7379 return NULL;
@@ -120,7 +126,7 @@ static void dc_plane_state_free(struct kref *kref) · 46 unmodified lines
120126 {
121127 struct dc_plane_state *plane_state = container_of(kref, struct dc_plane_state, refcount);
122128 destruct(plane_state);
123− kfree(plane_state);
129+ kvfree(plane_state);
124130 }
125131
126132 void dc_plane_state_release(struct dc_plane_state *plane_state)
@@ -136,7 +142,7 @@ void dc_gamma_retain(struct dc_gamma *gamma) · 9 unmodified lines
136142 static void dc_gamma_free(struct kref *kref)
137143 {
138144 struct dc_gamma *gamma = container_of(kref, struct dc_gamma, refcount);
139− kfree(gamma);
145+ kvfree(gamma);
140146 }
141147
142148 void dc_gamma_release(struct dc_gamma **gamma)
@@ -147,7 +153,7 @@ void dc_gamma_release(struct dc_gamma **gamma) · 4 unmodified lines
147153
148154 struct dc_gamma *dc_create_gamma(void)
149155 {
150− struct dc_gamma *gamma = kzalloc(sizeof(*gamma), GFP_KERNEL);
156+ struct dc_gamma *gamma = kvzalloc(sizeof(*gamma), GFP_KERNEL);
151157
152158 if (gamma == NULL)
153159 goto alloc_fail;
@@ -167,7 +173,7 @@ void dc_transfer_func_retain(struct dc_transfer_func *tf) · 13 unmodified lines
167173 static void dc_transfer_func_free(struct kref *kref)
168174 {
169175 struct dc_transfer_func *tf = container_of(kref, struct dc_transfer_func, refcount);
170− kfree(tf);
176+ kvfree(tf);
171177 }
172178
173179 void dc_transfer_func_release(struct dc_transfer_func *tf)
@@ -175,9 +181,9 @@ void dc_transfer_func_release(struct dc_transfer_func *tf) · 1 unmodified line
175181 kref_put(&tf->refcount, dc_transfer_func_free);
176182 }
177183
178−struct dc_transfer_func *dc_create_transfer_func(void)
184+struct dc_transfer_func *dc_create_transfer_func()
179185 {
180− struct dc_transfer_func *tf = kzalloc(sizeof(*tf), GFP_KERNEL);
186+ struct dc_transfer_func *tf = kvzalloc(sizeof(*tf), GFP_KERNEL);
181187
182188 if (tf == NULL)
183189 goto alloc_fail;
drivers/gpu/drm/amd/display/dc/dc.h+6−24
@@ -38,7 +38,7 @@ · 37 unmodified lines
3838 #include "inc/compressor.h"
3939 #include "dml/display_mode_lib.h"
4040
41−#define DC_VER "3.1.38"
41+#define DC_VER "3.1.44"
4242
4343 #define MAX_SURFACES 3
4444 #define MAX_STREAMS 6
@@ -202,6 +202,7 @@ struct dc_debug { · 157 unmodified lines
202202 bool timing_trace;
203203 bool clock_trace;
204204 bool validation_trace;
205+ bool bandwidth_calcs_trace;
205206
206207 /* stutter efficiency related */
207208 bool disable_stutter;
@@ -332,20 +333,6 @@ enum { · 124 unmodified lines
332333 TRANSFER_FUNC_POINTS = 1025
333334 };
334335
335−// Moved here from color module for linux
336−enum color_transfer_func {
337− transfer_func_unknown,
338− transfer_func_srgb,
339− transfer_func_bt709,
340− transfer_func_pq2084,
341− transfer_func_pq2084_interim,
342− transfer_func_linear_0_1,
343− transfer_func_linear_0_125,
344− transfer_func_dolbyvision,
345− transfer_func_gamma_22,
346− transfer_func_gamma_26
347−};
348−
349336 struct dc_hdr_static_metadata {
350337 /* display chromaticities and white point in units of 0.00001 */
351338 unsigned int chromaticity_green_x;
@@ -361,9 +348,6 @@ struct dc_hdr_static_metadata { · 9 unmodified lines
361348 uint32_t max_luminance;
362349 uint32_t maximum_content_light_level;
363350 uint32_t maximum_frame_average_light_level;
364−
365− bool hdr_supported;
366− bool is_hdr;
367351 };
368352
369353 enum dc_transfer_func_type {
@@ -419,7 +403,6 @@ union surface_update_flags { · 49 unmodified lines
419403 /* Medium updates */
420404 uint32_t dcc_change:1;
421405 uint32_t color_space_change:1;
422− uint32_t input_tf_change:1;
423406 uint32_t horizontal_mirror_change:1;
424407 uint32_t per_pixel_alpha_change:1;
425408 uint32_t rotation_change:1;
@@ -428,6 +411,7 @@ union surface_update_flags { · 2 unmodified lines
428411 uint32_t position_change:1;
429412 uint32_t in_transfer_func_change:1;
430413 uint32_t input_csc_change:1;
414+ uint32_t coeff_reduction_change:1;
431415 uint32_t output_tf_change:1;
432416 uint32_t pixel_format_change:1;
433417
@@ -460,7 +444,7 @@ struct dc_plane_state { · 26 unmodified lines
460444 struct dc_gamma *gamma_correction;
461445 struct dc_transfer_func *in_transfer_func;
462446 struct dc_bias_and_scale *bias_and_scale;
463− struct csc_transform input_csc_color_matrix;
447+ struct dc_csc_transform input_csc_color_matrix;
464448 struct fixed31_32 coeff_reduction_factor;
465449 uint32_t sdr_white_level;
466450
@@ -468,7 +452,6 @@ struct dc_plane_state { · 1 unmodified line
468452 struct dc_hdr_static_metadata hdr_static_ctx;
469453
470454 enum dc_color_space color_space;
471− enum color_transfer_func input_tf;
472455
473456 enum surface_pixel_format format;
474457 enum dc_rotation_angle rotation;
@@ -498,7 +481,6 @@ struct dc_plane_info { · 23 unmodified lines
498481 enum dc_rotation_angle rotation;
499482 enum plane_stereo_format stereo_format;
500483 enum dc_color_space color_space;
501− enum color_transfer_func input_tf;
502484 unsigned int sdr_white_level;
503485 bool horizontal_mirror;
504486 bool visible;
@@ -525,10 +507,9 @@ struct dc_surface_update { · 20 unmodified lines
525507 * null means no updates
526508 */
527509 struct dc_gamma *gamma;
528− enum color_transfer_func color_input_tf;
529510 struct dc_transfer_func *in_transfer_func;
530511
531− struct csc_transform *input_csc_color_matrix;
512+ struct dc_csc_transform *input_csc_color_matrix;
532513 struct fixed31_32 *coeff_reduction_factor;
533514 };
534515
@@ -699,6 +680,7 @@ struct dc_cursor { · 164 unmodified lines
699680 struct dc_cursor_attributes attributes;
700681 };
701682
683+
702684 /*******************************************************************************
703685 * Interrupt interfaces
704686 ******************************************************************************/
drivers/gpu/drm/amd/display/dc/dc_helper.c+59−0
@@ -117,6 +117,65 @@ uint32_t generic_reg_get5(const struct dc_context *ctx, uint32_t addr, · 116 unmodified lines
117117 return reg_val;
118118 }
119119
120+uint32_t generic_reg_get6(const struct dc_context *ctx, uint32_t addr,
121+ uint8_t shift1, uint32_t mask1, uint32_t *field_value1,
122+ uint8_t shift2, uint32_t mask2, uint32_t *field_value2,
123+ uint8_t shift3, uint32_t mask3, uint32_t *field_value3,
124+ uint8_t shift4, uint32_t mask4, uint32_t *field_value4,
125+ uint8_t shift5, uint32_t mask5, uint32_t *field_value5,
126+ uint8_t shift6, uint32_t mask6, uint32_t *field_value6)
127+{
128+ uint32_t reg_val = dm_read_reg(ctx, addr);
129+ *field_value1 = get_reg_field_value_ex(reg_val, mask1, shift1);
130+ *field_value2 = get_reg_field_value_ex(reg_val, mask2, shift2);
131+ *field_value3 = get_reg_field_value_ex(reg_val, mask3, shift3);
132+ *field_value4 = get_reg_field_value_ex(reg_val, mask4, shift4);
133+ *field_value5 = get_reg_field_value_ex(reg_val, mask5, shift5);
134+ *field_value6 = get_reg_field_value_ex(reg_val, mask6, shift6);
135+ return reg_val;
136+}
137+
138+uint32_t generic_reg_get7(const struct dc_context *ctx, uint32_t addr,
139+ uint8_t shift1, uint32_t mask1, uint32_t *field_value1,
140+ uint8_t shift2, uint32_t mask2, uint32_t *field_value2,
141+ uint8_t shift3, uint32_t mask3, uint32_t *field_value3,
142+ uint8_t shift4, uint32_t mask4, uint32_t *field_value4,
143+ uint8_t shift5, uint32_t mask5, uint32_t *field_value5,
144+ uint8_t shift6, uint32_t mask6, uint32_t *field_value6,
145+ uint8_t shift7, uint32_t mask7, uint32_t *field_value7)
146+{
147+ uint32_t reg_val = dm_read_reg(ctx, addr);
148+ *field_value1 = get_reg_field_value_ex(reg_val, mask1, shift1);
149+ *field_value2 = get_reg_field_value_ex(reg_val, mask2, shift2);
150+ *field_value3 = get_reg_field_value_ex(reg_val, mask3, shift3);
151+ *field_value4 = get_reg_field_value_ex(reg_val, mask4, shift4);
152+ *field_value5 = get_reg_field_value_ex(reg_val, mask5, shift5);
153+ *field_value6 = get_reg_field_value_ex(reg_val, mask6, shift6);
154+ *field_value7 = get_reg_field_value_ex(reg_val, mask7, shift7);
155+ return reg_val;
156+}
157+
158+uint32_t generic_reg_get8(const struct dc_context *ctx, uint32_t addr,
159+ uint8_t shift1, uint32_t mask1, uint32_t *field_value1,
160+ uint8_t shift2, uint32_t mask2, uint32_t *field_value2,
161+ uint8_t shift3, uint32_t mask3, uint32_t *field_value3,
162+ uint8_t shift4, uint32_t mask4, uint32_t *field_value4,
163+ uint8_t shift5, uint32_t mask5, uint32_t *field_value5,
164+ uint8_t shift6, uint32_t mask6, uint32_t *field_value6,
165+ uint8_t shift7, uint32_t mask7, uint32_t *field_value7,
166+ uint8_t shift8, uint32_t mask8, uint32_t *field_value8)
167+{
168+ uint32_t reg_val = dm_read_reg(ctx, addr);
169+ *field_value1 = get_reg_field_value_ex(reg_val, mask1, shift1);
170+ *field_value2 = get_reg_field_value_ex(reg_val, mask2, shift2);
171+ *field_value3 = get_reg_field_value_ex(reg_val, mask3, shift3);
172+ *field_value4 = get_reg_field_value_ex(reg_val, mask4, shift4);
173+ *field_value5 = get_reg_field_value_ex(reg_val, mask5, shift5);
174+ *field_value6 = get_reg_field_value_ex(reg_val, mask6, shift6);
175+ *field_value7 = get_reg_field_value_ex(reg_val, mask7, shift7);
176+ *field_value8 = get_reg_field_value_ex(reg_val, mask8, shift8);
177+ return reg_val;
178+}
120179 /* note: va version of this is pretty bad idea, since there is a output parameter pass by pointer
121180 * compiler won't be able to check for size match and is prone to stack corruption type of bugs
122181
drivers/gpu/drm/amd/display/dc/dc_hw_types.h+5−0
@@ -423,6 +423,11 @@ enum dc_gamma_type { · 422 unmodified lines
423423 GAMMA_CS_TFM_1D = 3,
424424 };
425425
426+struct dc_csc_transform {
427+ uint16_t matrix[12];
428+ bool enable_adjustment;
429+};
430+
426431 struct dc_gamma {
427432 struct kref refcount;
428433 enum dc_gamma_type type;
drivers/gpu/drm/amd/display/dc/dc_link.h+9−0
@@ -51,6 +51,14 @@ struct link_mst_stream_allocation_table { · 50 unmodified lines
5151 struct link_mst_stream_allocation stream_allocations[MAX_CONTROLLER_NUM];
5252 };
5353
54+struct time_stamp {
55+ uint64_t edp_poweroff;
56+ uint64_t edp_poweron;
57+};
58+
59+struct link_trace {
60+ struct time_stamp time_stamp;
61+};
5462 /*
5563 * A link contains one or more sinks and their connected status.
5664 * The currently active signal type (HDMI, DP-SST, DP-MST) is also reported.
@@ -114,6 +122,7 @@ struct dc_link { · 57 unmodified lines
114122
115123 struct dc_link_status link_status;
116124
125+ struct link_trace link_trace;
117126 };
118127
119128 const struct dc_link_status *dc_link_get_status(const struct dc_link *dc_link);
drivers/gpu/drm/amd/display/dc/dc_stream.h+8−20
@@ -58,18 +58,20 @@ struct dc_stream_state { · 57 unmodified lines
5858
5959 struct freesync_context freesync_ctx;
6060
61− struct dc_hdr_static_metadata hdr_static_metadata;
61+ struct dc_info_packet hdr_static_metadata;
6262 struct dc_transfer_func *out_transfer_func;
6363 struct colorspace_transform gamut_remap_matrix;
64− struct csc_transform csc_color_matrix;
64+ struct dc_csc_transform csc_color_matrix;
6565
6666 enum dc_color_space output_color_space;
6767 enum dc_dither_option dither_option;
6868
6969 enum view_3d_format view_format;
70− enum color_transfer_func output_tf;
7170
7271 bool ignore_msa_timing_param;
72+
73+ unsigned long long periodic_fn_vsync_delta;
74+
7375 /* TODO: custom INFO packets */
7476 /* TODO: ABM info (DMCU) */
7577 /* PSR info */
@@ -110,9 +112,10 @@ struct dc_stream_update { · 34 unmodified lines
110112 struct rect src;
111113 struct rect dst;
112114 struct dc_transfer_func *out_transfer_func;
113− struct dc_hdr_static_metadata *hdr_static_metadata;
114− enum color_transfer_func color_output_tf;
115+ struct dc_info_packet *hdr_static_metadata;
115116 unsigned int *abm_level;
117+
118+ unsigned long long *periodic_fn_vsync_delta;
116119 };
117120
118121 bool dc_is_stream_unchanged(
@@ -131,13 +134,6 @@ bool dc_is_stream_scaling_unchanged( · 12 unmodified lines
131134 * This does not trigger a flip. No surface address is programmed.
132135 */
133136
134−bool dc_commit_planes_to_stream(
135− struct dc *dc,
136− struct dc_plane_state **plane_states,
137− uint8_t new_plane_count,
138− struct dc_stream_state *dc_stream,
139− struct dc_state *state);
140−
141137 void dc_commit_updates_for_stream(struct dc *dc,
142138 struct dc_surface_update *srf_updates,
143139 int surface_count,
@@ -208,14 +204,6 @@ bool dc_add_all_planes_for_stream( · 64 unmodified lines
208204
209205 enum dc_status dc_validate_stream(struct dc *dc, struct dc_stream_state *stream);
210206
211−/*
212− * This function takes a stream and checks if it is guaranteed to be supported.
213− * Guaranteed means that MAX_COFUNC similar streams are supported.
214− *
215− * After this call:
216− * No hardware is programmed for call. Only validation is done.
217− */
218−
219207 /*
220208 * Set up streams and links associated to drive sinks
221209 * The streams parameter is an absolute set of all active streams.
drivers/gpu/drm/amd/display/dc/dc_types.h+9−6
@@ -370,12 +370,6 @@ struct dc_csc_adjustments { · 369 unmodified lines
370370 struct fixed31_32 hue;
371371 };
372372
373−enum {
374− MAX_LANES = 2,
375− MAX_COFUNC_PATH = 6,
376− LAYER_INDEX_PRIMARY = -1,
377−};
378−
379373 enum dpcd_downstream_port_max_bpc {
380374 DOWN_STREAM_MAX_8BPC = 0,
381375 DOWN_STREAM_MAX_10BPC,
@@ -530,6 +524,15 @@ struct vrr_params { · 148 unmodified lines
530524 uint32_t frame_counter;
531525 };
532526
527+struct dc_info_packet {
528+ bool valid;
529+ uint8_t hb0;
530+ uint8_t hb1;
531+ uint8_t hb2;
532+ uint8_t hb3;
533+ uint8_t sb[32];
534+};
535+
533536 #define DC_PLANE_UPDATE_TIMES_MAX 10
534537
535538 struct dc_plane_flip_time {
drivers/gpu/drm/amd/display/dc/dce/dce_audio.c+5−4
@@ -33,8 +33,9 @@ · 32 unmodified lines
3333
3434 #define CTX \
3535 aud->base.ctx
36−#define DC_LOGGER \
37− aud->base.ctx->logger
36+
37+#define DC_LOGGER_INIT()
38+
3839 #define REG(reg)\
3940 (aud->regs->reg)
4041
@@ -348,8 +349,8 @@ static void set_audio_latency( · 307 unmodified lines
348349
349350 void dce_aud_az_enable(struct audio *audio)
350351 {
351− struct dce_audio *aud = DCE_AUD(audio);
352352 uint32_t value = AZ_REG_READ(AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL);
353+ DC_LOGGER_INIT();
353354
354355 set_reg_field_value(value, 1,
355356 AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL,
@@ -371,7 +372,7 @@ void dce_aud_az_enable(struct audio *audio) · 15 unmodified lines
371372 void dce_aud_az_disable(struct audio *audio)
372373 {
373374 uint32_t value;
374− struct dce_audio *aud = DCE_AUD(audio);
375+ DC_LOGGER_INIT();
375376
376377 value = AZ_REG_READ(AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL);
377378 set_reg_field_value(value, 1,
drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c+12−5
@@ -41,8 +41,9 @@ · 40 unmodified lines
4141
4242 #define CTX \
4343 clk_src->base.ctx
44−#define DC_LOGGER \
45− calc_pll_cs->ctx->logger
44+
45+#define DC_LOGGER_INIT()
46+
4647 #undef FN
4748 #define FN(reg_name, field_name) \
4849 clk_src->cs_shift->field_name, clk_src->cs_mask->field_name
@@ -467,7 +468,7 @@ static uint32_t dce110_get_pix_clk_dividers_helper ( · 418 unmodified lines
467468 {
468469 uint32_t field = 0;
469470 uint32_t pll_calc_error = MAX_PLL_CALC_ERROR;
470− struct calc_pll_clock_source *calc_pll_cs = &clk_src->calc_pll;
471+ DC_LOGGER_INIT();
471472 /* Check if reference clock is external (not pcie/xtalin)
472473 * HW Dce80 spec:
473474 * 00 - PCIE_REFCLK, 01 - XTALIN, 02 - GENERICA, 03 - GENERICB
@@ -557,8 +558,8 @@ static uint32_t dce110_get_pix_clk_dividers( · 83 unmodified lines
557558 struct pll_settings *pll_settings)
558559 {
559560 struct dce110_clk_src *clk_src = TO_DCE110_CLK_SRC(cs);
560− struct calc_pll_clock_source *calc_pll_cs = &clk_src->calc_pll;
561561 uint32_t pll_calc_error = MAX_PLL_CALC_ERROR;
562+ DC_LOGGER_INIT();
562563
563564 if (pix_clk_params == NULL || pll_settings == NULL
564565 || pix_clk_params->requested_pix_clk == 0) {
@@ -589,6 +590,9 @@ static uint32_t dce110_get_pix_clk_dividers( · 24 unmodified lines
589590 pll_settings, pix_clk_params);
590591 break;
591592 case DCE_VERSION_11_2:
593+#if defined(CONFIG_DRM_AMD_DC_VEGAM)
594+ case DCE_VERSION_11_22:
595+#endif
592596 case DCE_VERSION_12_0:
593597 #if defined(CONFIG_DRM_AMD_DC_DCN1_0)
594598 case DCN_VERSION_1_0:
@@ -978,6 +982,9 @@ static bool dce110_program_pix_clk( · 383 unmodified lines
978982
979983 break;
980984 case DCE_VERSION_11_2:
985+#if defined(CONFIG_DRM_AMD_DC_VEGAM)
986+ case DCE_VERSION_11_22:
987+#endif
981988 case DCE_VERSION_12_0:
982989 #if defined(CONFIG_DRM_AMD_DC_DCN1_0)
983990 case DCN_VERSION_1_0:
@@ -1054,7 +1061,7 @@ static void get_ss_info_from_atombios( · 70 unmodified lines
10541061 struct spread_spectrum_info *ss_info_cur;
10551062 struct spread_spectrum_data *ss_data_cur;
10561063 uint32_t i;
1057− struct calc_pll_clock_source *calc_pll_cs = &clk_src->calc_pll;
1064+ DC_LOGGER_INIT();
10581065 if (ss_entries_num == NULL) {
10591066 DC_LOG_SYNC(
10601067 "Invalid entry !!!\n");
drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.c+2−1
@@ -53,7 +53,8 @@ void dce_pipe_control_lock(struct dc *dc, · 52 unmodified lines
5353 struct dce_hwseq *hws = dc->hwseq;
5454
5555 /* Not lock pipe when blank */
56− if (lock && pipe->stream_res.tg->funcs->is_blanked(pipe->stream_res.tg))
56+ if (lock && pipe->stream_res.tg->funcs->is_blanked &&
57+ pipe->stream_res.tg->funcs->is_blanked(pipe->stream_res.tg))
5758 return;
5859
5960 val = REG_GET_4(BLND_V_UPDATE_LOCK[pipe->stream_res.tg->inst],
drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c+4−2
@@ -113,6 +113,7 @@ static const struct link_encoder_funcs dce110_lnk_enc_funcs = { · 112 unmodified lines
113113 .connect_dig_be_to_fe = dce110_link_encoder_connect_dig_be_to_fe,
114114 .enable_hpd = dce110_link_encoder_enable_hpd,
115115 .disable_hpd = dce110_link_encoder_disable_hpd,
116+ .is_dig_enabled = dce110_is_dig_enabled,
116117 .destroy = dce110_link_encoder_destroy
117118 };
118119
@@ -535,8 +536,9 @@ void dce110_psr_program_secondary_packet(struct link_encoder *enc, · 416 unmodified lines
535536 DP_SEC_GSP0_PRIORITY, 1);
536537 }
537538
538−static bool is_dig_enabled(const struct dce110_link_encoder *enc110)
539+bool dce110_is_dig_enabled(struct link_encoder *enc)
539540 {
541+ struct dce110_link_encoder *enc110 = TO_DCE110_LINK_ENC(enc);
540542 uint32_t value;
541543
542544 REG_GET(DIG_BE_EN_CNTL, DIG_ENABLE, &value);
@@ -1031,7 +1033,7 @@ void dce110_link_encoder_disable_output( · 488 unmodified lines
10311033 struct bp_transmitter_control cntl = { 0 };
10321034 enum bp_result result;
10331035
1034− if (!is_dig_enabled(enc110)) {
1036+ if (!dce110_is_dig_enabled(enc)) {
10351037 /* OF_SKIP_POWER_DOWN_INACTIVE_ENCODER */
10361038 return;
10371039 }
drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.h+2−0
@@ -263,4 +263,6 @@ void dce110_psr_program_dp_dphy_fast_training(struct link_encoder *enc, · 262 unmodified lines
263263 void dce110_psr_program_secondary_packet(struct link_encoder *enc,
264264 unsigned int sdp_transmit_line_num_deadline);
265265
266+bool dce110_is_dig_enabled(struct link_encoder *enc);
267+
266268 #endif /* __DC_LINK_ENCODER__DCE110_H__ */
drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c+94−9
@@ -174,6 +174,25 @@ static void program_urgency_watermark( · 173 unmodified lines
174174 URGENCY_HIGH_WATERMARK, urgency_high_wm);
175175 }
176176
177+static void dce120_program_urgency_watermark(
178+ struct dce_mem_input *dce_mi,
179+ uint32_t wm_select,
180+ uint32_t urgency_low_wm,
181+ uint32_t urgency_high_wm)
182+{
183+ REG_UPDATE(DPG_WATERMARK_MASK_CONTROL,
184+ URGENCY_WATERMARK_MASK, wm_select);
185+
186+ REG_SET_2(DPG_PIPE_URGENCY_CONTROL, 0,
187+ URGENCY_LOW_WATERMARK, urgency_low_wm,
188+ URGENCY_HIGH_WATERMARK, urgency_high_wm);
189+
190+ REG_SET_2(DPG_PIPE_URGENT_LEVEL_CONTROL, 0,
191+ URGENT_LEVEL_LOW_WATERMARK, urgency_low_wm,
192+ URGENT_LEVEL_HIGH_WATERMARK, urgency_high_wm);
193+
194+}
195+
177196 static void program_nbp_watermark(
178197 struct dce_mem_input *dce_mi,
179198 uint32_t wm_select,
@@ -206,6 +225,25 @@ static void program_nbp_watermark( · 26 unmodified lines
206225 }
207226 }
208227
228+static void dce120_program_stutter_watermark(
229+ struct dce_mem_input *dce_mi,
230+ uint32_t wm_select,
231+ uint32_t stutter_mark,
232+ uint32_t stutter_entry)
233+{
234+ REG_UPDATE(DPG_WATERMARK_MASK_CONTROL,
235+ STUTTER_EXIT_SELF_REFRESH_WATERMARK_MASK, wm_select);
236+
237+ if (REG(DPG_PIPE_STUTTER_CONTROL2))
238+ REG_UPDATE_2(DPG_PIPE_STUTTER_CONTROL2,
239+ STUTTER_EXIT_SELF_REFRESH_WATERMARK, stutter_mark,
240+ STUTTER_ENTER_SELF_REFRESH_WATERMARK, stutter_entry);
241+ else
242+ REG_UPDATE_2(DPG_PIPE_STUTTER_CONTROL,
243+ STUTTER_EXIT_SELF_REFRESH_WATERMARK, stutter_mark,
244+ STUTTER_ENTER_SELF_REFRESH_WATERMARK, stutter_entry);
245+}
246+
209247 static void program_stutter_watermark(
210248 struct dce_mem_input *dce_mi,
211249 uint32_t wm_select,
@@ -225,7 +263,8 @@ static void program_stutter_watermark( · 13 unmodified lines
225263 static void dce_mi_program_display_marks(
226264 struct mem_input *mi,
227265 struct dce_watermarks nbp,
228− struct dce_watermarks stutter,
266+ struct dce_watermarks stutter_exit,
267+ struct dce_watermarks stutter_enter,
229268 struct dce_watermarks urgent,
230269 uint32_t total_dest_line_time_ns)
231270 {
@@ -243,13 +282,14 @@ static void dce_mi_program_display_marks( · 11 unmodified lines
243282 program_nbp_watermark(dce_mi, 2, nbp.a_mark); /* set a */
244283 program_nbp_watermark(dce_mi, 1, nbp.d_mark); /* set d */
245284
246− program_stutter_watermark(dce_mi, 2, stutter.a_mark); /* set a */
247− program_stutter_watermark(dce_mi, 1, stutter.d_mark); /* set d */
285+ program_stutter_watermark(dce_mi, 2, stutter_exit.a_mark); /* set a */
286+ program_stutter_watermark(dce_mi, 1, stutter_exit.d_mark); /* set d */
248287 }
249288
250−static void dce120_mi_program_display_marks(struct mem_input *mi,
289+static void dce112_mi_program_display_marks(struct mem_input *mi,
251290 struct dce_watermarks nbp,
252− struct dce_watermarks stutter,
291+ struct dce_watermarks stutter_exit,
292+ struct dce_watermarks stutter_entry,
253293 struct dce_watermarks urgent,
254294 uint32_t total_dest_line_time_ns)
255295 {
@@ -273,10 +313,43 @@ static void dce120_mi_program_display_marks(struct mem_input *mi, · 17 unmodified lines
273313 program_nbp_watermark(dce_mi, 2, nbp.c_mark); /* set c */
274314 program_nbp_watermark(dce_mi, 3, nbp.d_mark); /* set d */
275315
276− program_stutter_watermark(dce_mi, 0, stutter.a_mark); /* set a */
277− program_stutter_watermark(dce_mi, 1, stutter.b_mark); /* set b */
278− program_stutter_watermark(dce_mi, 2, stutter.c_mark); /* set c */
279− program_stutter_watermark(dce_mi, 3, stutter.d_mark); /* set d */
316+ program_stutter_watermark(dce_mi, 0, stutter_exit.a_mark); /* set a */
317+ program_stutter_watermark(dce_mi, 1, stutter_exit.b_mark); /* set b */
318+ program_stutter_watermark(dce_mi, 2, stutter_exit.c_mark); /* set c */
319+ program_stutter_watermark(dce_mi, 3, stutter_exit.d_mark); /* set d */
320+}
321+
322+static void dce120_mi_program_display_marks(struct mem_input *mi,
323+ struct dce_watermarks nbp,
324+ struct dce_watermarks stutter_exit,
325+ struct dce_watermarks stutter_entry,
326+ struct dce_watermarks urgent,
327+ uint32_t total_dest_line_time_ns)
328+{
329+ struct dce_mem_input *dce_mi = TO_DCE_MEM_INPUT(mi);
330+ uint32_t stutter_en = mi->ctx->dc->debug.disable_stutter ? 0 : 1;
331+
332+ dce120_program_urgency_watermark(dce_mi, 0, /* set a */
333+ urgent.a_mark, total_dest_line_time_ns);
334+ dce120_program_urgency_watermark(dce_mi, 1, /* set b */
335+ urgent.b_mark, total_dest_line_time_ns);
336+ dce120_program_urgency_watermark(dce_mi, 2, /* set c */
337+ urgent.c_mark, total_dest_line_time_ns);
338+ dce120_program_urgency_watermark(dce_mi, 3, /* set d */
339+ urgent.d_mark, total_dest_line_time_ns);
340+
341+ REG_UPDATE_2(DPG_PIPE_STUTTER_CONTROL,
342+ STUTTER_ENABLE, stutter_en,
343+ STUTTER_IGNORE_FBC, 1);
344+ program_nbp_watermark(dce_mi, 0, nbp.a_mark); /* set a */
345+ program_nbp_watermark(dce_mi, 1, nbp.b_mark); /* set b */
346+ program_nbp_watermark(dce_mi, 2, nbp.c_mark); /* set c */
347+ program_nbp_watermark(dce_mi, 3, nbp.d_mark); /* set d */
348+
349+ dce120_program_stutter_watermark(dce_mi, 0, stutter_exit.a_mark, stutter_entry.a_mark); /* set a */
350+ dce120_program_stutter_watermark(dce_mi, 1, stutter_exit.b_mark, stutter_entry.b_mark); /* set b */
351+ dce120_program_stutter_watermark(dce_mi, 2, stutter_exit.c_mark, stutter_entry.c_mark); /* set c */
352+ dce120_program_stutter_watermark(dce_mi, 3, stutter_exit.d_mark, stutter_entry.d_mark); /* set d */
280353 }
281354
282355 static void program_tiling(
@@ -694,6 +767,18 @@ void dce112_mem_input_construct( · 411 unmodified lines
694767 const struct dce_mem_input_registers *regs,
695768 const struct dce_mem_input_shift *mi_shift,
696769 const struct dce_mem_input_mask *mi_mask)
770+{
771+ dce_mem_input_construct(dce_mi, ctx, inst, regs, mi_shift, mi_mask);
772+ dce_mi->base.funcs->mem_input_program_display_marks = dce112_mi_program_display_marks;
773+}
774+
775+void dce120_mem_input_construct(
776+ struct dce_mem_input *dce_mi,
777+ struct dc_context *ctx,
778+ int inst,
779+ const struct dce_mem_input_registers *regs,
780+ const struct dce_mem_input_shift *mi_shift,
781+ const struct dce_mem_input_mask *mi_mask)
697782 {
698783 dce_mem_input_construct(dce_mi, ctx, inst, regs, mi_shift, mi_mask);
699784 dce_mi->base.funcs->mem_input_program_display_marks = dce120_mi_program_display_marks;
drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h+17−0
@@ -106,6 +106,7 @@ struct dce_mem_input_registers { · 105 unmodified lines
106106 uint32_t DPG_PIPE_ARBITRATION_CONTROL1;
107107 uint32_t DPG_WATERMARK_MASK_CONTROL;
108108 uint32_t DPG_PIPE_URGENCY_CONTROL;
109+ uint32_t DPG_PIPE_URGENT_LEVEL_CONTROL;
109110 uint32_t DPG_PIPE_NB_PSTATE_CHANGE_CONTROL;
110111 uint32_t DPG_PIPE_LOW_POWER_CONTROL;
111112 uint32_t DPG_PIPE_STUTTER_CONTROL;
@@ -213,6 +214,11 @@ struct dce_mem_input_registers { · 101 unmodified lines
213214
214215 #define MI_DCE12_DMIF_PG_MASK_SH_LIST(mask_sh, blk)\
215216 SFB(blk, DPG_PIPE_STUTTER_CONTROL2, STUTTER_EXIT_SELF_REFRESH_WATERMARK, mask_sh),\
217+ SFB(blk, DPG_PIPE_STUTTER_CONTROL2, STUTTER_ENTER_SELF_REFRESH_WATERMARK, mask_sh),\
218+ SFB(blk, DPG_PIPE_URGENT_LEVEL_CONTROL, URGENT_LEVEL_LOW_WATERMARK, mask_sh),\
219+ SFB(blk, DPG_PIPE_URGENT_LEVEL_CONTROL, URGENT_LEVEL_HIGH_WATERMARK, mask_sh),\
220+ SFB(blk, DPG_PIPE_URGENCY_CONTROL, URGENCY_LOW_WATERMARK, mask_sh),\
221+ SFB(blk, DPG_PIPE_URGENCY_CONTROL, URGENCY_HIGH_WATERMARK, mask_sh),\
216222 SFB(blk, DPG_WATERMARK_MASK_CONTROL, PSTATE_CHANGE_WATERMARK_MASK, mask_sh),\
217223 SFB(blk, DPG_PIPE_LOW_POWER_CONTROL, PSTATE_CHANGE_ENABLE, mask_sh),\
218224 SFB(blk, DPG_PIPE_LOW_POWER_CONTROL, PSTATE_CHANGE_URGENT_DURING_REQUEST, mask_sh),\
@@ -286,6 +292,8 @@ struct dce_mem_input_registers { · 67 unmodified lines
286292 type STUTTER_EXIT_SELF_REFRESH_WATERMARK_MASK; \
287293 type URGENCY_LOW_WATERMARK; \
288294 type URGENCY_HIGH_WATERMARK; \
295+ type URGENT_LEVEL_LOW_WATERMARK;\
296+ type URGENT_LEVEL_HIGH_WATERMARK;\
289297 type NB_PSTATE_CHANGE_ENABLE; \
290298 type NB_PSTATE_CHANGE_URGENT_DURING_REQUEST; \
291299 type NB_PSTATE_CHANGE_NOT_SELF_REFRESH_DURING_REQUEST; \
@@ -297,6 +305,7 @@ struct dce_mem_input_registers { · 5 unmodified lines
297305 type STUTTER_ENABLE; \
298306 type STUTTER_IGNORE_FBC; \
299307 type STUTTER_EXIT_SELF_REFRESH_WATERMARK; \
308+ type STUTTER_ENTER_SELF_REFRESH_WATERMARK; \
300309 type DMIF_BUFFERS_ALLOCATED; \
301310 type DMIF_BUFFERS_ALLOCATION_COMPLETED; \
302311 type ENABLE; /* MC_HUB_RDREQ_DMIF_LIMIT */\
@@ -344,4 +353,12 @@ void dce112_mem_input_construct( · 41 unmodified lines
344353 const struct dce_mem_input_shift *mi_shift,
345354 const struct dce_mem_input_mask *mi_mask);
346355
356+void dce120_mem_input_construct(
357+ struct dce_mem_input *dce_mi,
358+ struct dc_context *ctx,
359+ int inst,
360+ const struct dce_mem_input_registers *regs,
361+ const struct dce_mem_input_shift *mi_shift,
362+ const struct dce_mem_input_mask *mi_mask);
363+
347364 #endif /*__DCE_MEM_INPUT_H__*/
drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c+19−49
@@ -26,27 +26,10 @@ · 25 unmodified lines
2626 #include "dc_bios_types.h"
2727 #include "dce_stream_encoder.h"
2828 #include "reg_helper.h"
29+#include "hw_shared.h"
30+
2931 #define DC_LOGGER \
3032 enc110->base.ctx->logger
31−enum DP_PIXEL_ENCODING {
32−DP_PIXEL_ENCODING_RGB444 = 0x00000000,
33−DP_PIXEL_ENCODING_YCBCR422 = 0x00000001,
34−DP_PIXEL_ENCODING_YCBCR444 = 0x00000002,
35−DP_PIXEL_ENCODING_RGB_WIDE_GAMUT = 0x00000003,
36−DP_PIXEL_ENCODING_Y_ONLY = 0x00000004,
37−DP_PIXEL_ENCODING_YCBCR420 = 0x00000005,
38−DP_PIXEL_ENCODING_RESERVED = 0x00000006,
39−};
40−
41−
42−enum DP_COMPONENT_DEPTH {
43−DP_COMPONENT_DEPTH_6BPC = 0x00000000,
44−DP_COMPONENT_DEPTH_8BPC = 0x00000001,
45−DP_COMPONENT_DEPTH_10BPC = 0x00000002,
46−DP_COMPONENT_DEPTH_12BPC = 0x00000003,
47−DP_COMPONENT_DEPTH_16BPC = 0x00000004,
48−DP_COMPONENT_DEPTH_RESERVED = 0x00000005,
49−};
5033
5134
5235 #define REG(reg)\
@@ -80,7 +63,7 @@ enum { · 27 unmodified lines
8063 static void dce110_update_generic_info_packet(
8164 struct dce110_stream_encoder *enc110,
8265 uint32_t packet_index,
83− const struct encoder_info_packet *info_packet)
66+ const struct dc_info_packet *info_packet)
8467 {
8568 uint32_t regval;
8669 /* TODOFPGA Figure out a proper number for max_retries polling for lock
@@ -196,7 +179,7 @@ static void dce110_update_generic_info_packet( · 109 unmodified lines
196179 static void dce110_update_hdmi_info_packet(
197180 struct dce110_stream_encoder *enc110,
198181 uint32_t packet_index,
199− const struct encoder_info_packet *info_packet)
182+ const struct dc_info_packet *info_packet)
200183 {
201184 uint32_t cont, send, line;
202185
@@ -314,11 +297,11 @@ static void dce110_stream_encoder_dp_set_stream_attribute( · 111 unmodified lines
314297 switch (crtc_timing->pixel_encoding) {
315298 case PIXEL_ENCODING_YCBCR422:
316299 REG_UPDATE(DP_PIXEL_FORMAT, DP_PIXEL_ENCODING,
317− DP_PIXEL_ENCODING_YCBCR422);
300+ DP_PIXEL_ENCODING_TYPE_YCBCR422);
318301 break;
319302 case PIXEL_ENCODING_YCBCR444:
320303 REG_UPDATE(DP_PIXEL_FORMAT, DP_PIXEL_ENCODING,
321− DP_PIXEL_ENCODING_YCBCR444);
304+ DP_PIXEL_ENCODING_TYPE_YCBCR444);
322305
323306 if (crtc_timing->flags.Y_ONLY)
324307 if (crtc_timing->display_color_depth != COLOR_DEPTH_666)
@@ -326,7 +309,7 @@ static void dce110_stream_encoder_dp_set_stream_attribute( · 1 unmodified line
326309 * Color depth of Y-only could be
327310 * 8, 10, 12, 16 bits */
328311 REG_UPDATE(DP_PIXEL_FORMAT, DP_PIXEL_ENCODING,
329− DP_PIXEL_ENCODING_Y_ONLY);
312+ DP_PIXEL_ENCODING_TYPE_Y_ONLY);
330313 /* Note: DP_MSA_MISC1 bit 7 is the indicator
331314 * of Y-only mode.
332315 * This bit is set in HW if register
@@ -334,7 +317,7 @@ static void dce110_stream_encoder_dp_set_stream_attribute( · 1 unmodified line
334317 break;
335318 case PIXEL_ENCODING_YCBCR420:
336319 REG_UPDATE(DP_PIXEL_FORMAT, DP_PIXEL_ENCODING,
337− DP_PIXEL_ENCODING_YCBCR420);
320+ DP_PIXEL_ENCODING_TYPE_YCBCR420);
338321 if (enc110->se_mask->DP_VID_M_DOUBLE_VALUE_EN)
339322 REG_UPDATE(DP_VID_TIMING, DP_VID_M_DOUBLE_VALUE_EN, 1);
340323
@@ -345,7 +328,7 @@ static void dce110_stream_encoder_dp_set_stream_attribute( · 4 unmodified lines
345328 break;
346329 default:
347330 REG_UPDATE(DP_PIXEL_FORMAT, DP_PIXEL_ENCODING,
348− DP_PIXEL_ENCODING_RGB444);
331+ DP_PIXEL_ENCODING_TYPE_RGB444);
349332 break;
350333 }
351334
@@ -363,20 +346,20 @@ static void dce110_stream_encoder_dp_set_stream_attribute( · 11 unmodified lines
363346 break;
364347 case COLOR_DEPTH_888:
365348 REG_UPDATE(DP_PIXEL_FORMAT, DP_COMPONENT_DEPTH,
366− DP_COMPONENT_DEPTH_8BPC);
349+ DP_COMPONENT_PIXEL_DEPTH_8BPC);
367350 break;
368351 case COLOR_DEPTH_101010:
369352 REG_UPDATE(DP_PIXEL_FORMAT, DP_COMPONENT_DEPTH,
370− DP_COMPONENT_DEPTH_10BPC);
353+ DP_COMPONENT_PIXEL_DEPTH_10BPC);
371354
372355 break;
373356 case COLOR_DEPTH_121212:
374357 REG_UPDATE(DP_PIXEL_FORMAT, DP_COMPONENT_DEPTH,
375− DP_COMPONENT_DEPTH_12BPC);
358+ DP_COMPONENT_PIXEL_DEPTH_12BPC);
376359 break;
377360 default:
378361 REG_UPDATE(DP_PIXEL_FORMAT, DP_COMPONENT_DEPTH,
379− DP_COMPONENT_DEPTH_6BPC);
362+ DP_COMPONENT_PIXEL_DEPTH_6BPC);
380363 break;
381364 }
382365
@@ -836,7 +819,7 @@ static void dce110_stream_encoder_update_dp_info_packets( · 453 unmodified lines
836819 const struct encoder_info_frame *info_frame)
837820 {
838821 struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc);
839− uint32_t value = REG_READ(DP_SEC_CNTL);
822+ uint32_t value = 0;
840823
841824 if (info_frame->vsc.valid)
842825 dce110_update_generic_info_packet(
@@ -870,6 +853,7 @@ static void dce110_stream_encoder_update_dp_info_packets( · 27 unmodified lines
870853 * Therefore we need to enable master bit
871854 * if at least on of the fields is not 0
872855 */
856+ value = REG_READ(DP_SEC_CNTL);
873857 if (value)
874858 REG_UPDATE(DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, 1);
875859 }
@@ -879,7 +863,7 @@ static void dce110_stream_encoder_stop_dp_info_packets( · 3 unmodified lines
879863 {
880864 /* stop generic packets on DP */
881865 struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc);
882− uint32_t value = REG_READ(DP_SEC_CNTL);
866+ uint32_t value = 0;
883867
884868 if (enc110->se_mask->DP_SEC_AVI_ENABLE) {
885869 REG_SET_7(DP_SEC_CNTL, 0,
@@ -892,25 +876,10 @@ static void dce110_stream_encoder_stop_dp_info_packets( · 6 unmodified lines
892876 DP_SEC_STREAM_ENABLE, 0);
893877 }
894878
895−#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
896− if (enc110->se_mask->DP_SEC_GSP7_ENABLE) {
897− REG_SET_10(DP_SEC_CNTL, 0,
898− DP_SEC_GSP0_ENABLE, 0,
899− DP_SEC_GSP1_ENABLE, 0,
900− DP_SEC_GSP2_ENABLE, 0,
901− DP_SEC_GSP3_ENABLE, 0,
902− DP_SEC_GSP4_ENABLE, 0,
903− DP_SEC_GSP5_ENABLE, 0,
904− DP_SEC_GSP6_ENABLE, 0,
905− DP_SEC_GSP7_ENABLE, 0,
906− DP_SEC_MPG_ENABLE, 0,
907− DP_SEC_STREAM_ENABLE, 0);
908− }
909−#endif
910879 /* this register shared with audio info frame.
911880 * therefore we need to keep master enabled
912881 * if at least one of the fields is not 0 */
913−
882+ value = REG_READ(DP_SEC_CNTL);
914883 if (value)
915884 REG_UPDATE(DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, 1);
916885
@@ -1513,7 +1482,7 @@ static void dce110_se_disable_dp_audio( · 596 unmodified lines
15131482 struct stream_encoder *enc)
15141483 {
15151484 struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc);
1516− uint32_t value = REG_READ(DP_SEC_CNTL);
1485+ uint32_t value = 0;
15171486
15181487 /* Disable Audio packets */
15191488 REG_UPDATE_5(DP_SEC_CNTL,
@@ -1525,6 +1494,7 @@ static void dce110_se_disable_dp_audio( · 5 unmodified lines
15251494
15261495 /* This register shared with encoder info frame. Therefore we need to
15271496 keep master enabled if at least on of the fields is not 0 */
1497+ value = REG_READ(DP_SEC_CNTL);
15281498 if (value != 0)
15291499 REG_UPDATE(DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, 1);
15301500
drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c+0−33
@@ -733,38 +733,6 @@ enum dc_status dce100_add_stream_to_ctx( · 732 unmodified lines
733733 return result;
734734 }
735735
736−enum dc_status dce100_validate_guaranteed(
737− struct dc *dc,
738− struct dc_stream_state *dc_stream,
739− struct dc_state *context)
740−{
741− enum dc_status result = DC_ERROR_UNEXPECTED;
742−
743− context->streams[0] = dc_stream;
744− dc_stream_retain(context->streams[0]);
745− context->stream_count++;
746−
747− result = resource_map_pool_resources(dc, context, dc_stream);
748−
749− if (result == DC_OK)
750− result = resource_map_clock_resources(dc, context, dc_stream);
751−
752− if (result == DC_OK)
753− result = build_mapped_resource(dc, context, dc_stream);
754−
755− if (result == DC_OK) {
756− validate_guaranteed_copy_streams(
757− context, dc->caps.max_streams);
758− result = resource_build_scaling_params_for_context(dc, context);
759− }
760−
761− if (result == DC_OK)
762− if (!dce100_validate_bandwidth(dc, context))
763− result = DC_FAIL_BANDWIDTH_VALIDATE;
764−
765− return result;
766−}
767−
768736 static void dce100_destroy_resource_pool(struct resource_pool **pool)
769737 {
770738 struct dce110_resource_pool *dce110_pool = TO_DCE110_RES_POOL(*pool);
@@ -786,7 +754,6 @@ enum dc_status dce100_validate_plane(const struct dc_plane_state *plane_state, s · 15 unmodified lines
786754 static const struct resource_funcs dce100_res_pool_funcs = {
787755 .destroy = dce100_destroy_resource_pool,
788756 .link_enc_create = dce100_link_encoder_create,
789− .validate_guaranteed = dce100_validate_guaranteed,
790757 .validate_bandwidth = dce100_validate_bandwidth,
791758 .validate_plane = dce100_validate_plane,
792759 .add_stream_to_ctx = dce100_add_stream_to_ctx,
drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c+74−21
@@ -70,8 +70,9 @@ · 69 unmodified lines
7070
7171 #define CTX \
7272 hws->ctx
73−#define DC_LOGGER \
74− ctx->logger
73+
74+#define DC_LOGGER_INIT()
75+
7576 #define REG(reg)\
7677 hws->regs->reg
7778
@@ -279,7 +280,9 @@ dce110_set_input_transfer_func(struct pipe_ctx *pipe_ctx, · 201 unmodified lines
279280 build_prescale_params(&prescale_params, plane_state);
280281 ipp->funcs->ipp_program_prescale(ipp, &prescale_params);
281282
282− if (plane_state->gamma_correction && dce_use_lut(plane_state->format))
283+ if (plane_state->gamma_correction &&
284+ !plane_state->gamma_correction->is_identity &&
285+ dce_use_lut(plane_state->format))
283286 ipp->funcs->ipp_program_input_lut(ipp, plane_state->gamma_correction);
284287
285288 if (tf == NULL) {
@@ -851,6 +854,28 @@ void hwss_edp_power_control( · 565 unmodified lines
851854
852855 if (power_up != is_panel_powered_on(hwseq)) {
853856 /* Send VBIOS command to prompt eDP panel power */
857+ if (power_up) {
858+ unsigned long long current_ts = dm_get_timestamp(ctx);
859+ unsigned long long duration_in_ms =
860+ dm_get_elapse_time_in_ns(
861+ ctx,
862+ current_ts,
863+ div64_u64(link->link_trace.time_stamp.edp_poweroff, 1000000));
864+ unsigned long long wait_time_ms = 0;
865+
866+ /* max 500ms from LCDVDD off to on */
867+ if (link->link_trace.time_stamp.edp_poweroff == 0)
868+ wait_time_ms = 500;
869+ else if (duration_in_ms < 500)
870+ wait_time_ms = 500 - duration_in_ms;
871+
872+ if (wait_time_ms) {
873+ msleep(wait_time_ms);
874+ dm_output_to_console("%s: wait %lld ms to power on eDP.\n",
875+ __func__, wait_time_ms);
876+ }
877+
878+ }
854879
855880 DC_LOG_HW_RESUME_S3(
856881 "%s: Panel Power action: %s\n",
@@ -864,9 +889,14 @@ void hwss_edp_power_control( · 7 unmodified lines
864889 cntl.coherent = false;
865890 cntl.lanes_number = LANE_COUNT_FOUR;
866891 cntl.hpd_sel = link->link_enc->hpd_source;
867−
868892 bp_result = link_transmitter_control(ctx->dc_bios, &cntl);
869893
894+ if (!power_up)
895+ /*save driver power off time stamp*/
896+ link->link_trace.time_stamp.edp_poweroff = dm_get_timestamp(ctx);
897+ else
898+ link->link_trace.time_stamp.edp_poweron = dm_get_timestamp(ctx);
899+
870900 if (bp_result != BP_RESULT_OK)
871901 DC_LOG_ERROR(
872902 "%s: Panel Power bp_result: %d\n",
@@ -1011,7 +1041,7 @@ void dce110_unblank_stream(struct pipe_ctx *pipe_ctx, · 138 unmodified lines
10111041
10121042 if (link->local_sink && link->local_sink->sink_signal == SIGNAL_TYPE_EDP) {
10131043 link->dc->hwss.edp_backlight_control(link, true);
1014− stream->bl_pwm_level = 0;
1044+ stream->bl_pwm_level = EDP_BACKLIGHT_RAMP_DISABLE_LEVEL;
10151045 }
10161046 }
10171047 void dce110_blank_stream(struct pipe_ctx *pipe_ctx)
@@ -1203,7 +1233,7 @@ static void program_scaler(const struct dc *dc, · 185 unmodified lines
12031233 &pipe_ctx->plane_res.scl_data);
12041234 }
12051235
1206−static enum dc_status dce110_prog_pixclk_crtc_otg(
1236+static enum dc_status dce110_enable_stream_timing(
12071237 struct pipe_ctx *pipe_ctx,
12081238 struct dc_state *context,
12091239 struct dc *dc)
@@ -1269,7 +1299,7 @@ static enum dc_status apply_single_controller_ctx_to_hw( · 59 unmodified lines
12691299 pipe_ctx[pipe_ctx->pipe_idx];
12701300
12711301 /* */
1272− dc->hwss.prog_pixclk_crtc_otg(pipe_ctx, context, dc);
1302+ dc->hwss.enable_stream_timing(pipe_ctx, context, dc);
12731303
12741304 /* FPGA does not program backend */
12751305 if (IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {
@@ -1441,6 +1471,17 @@ static void disable_vga_and_power_gate_all_controllers( · 165 unmodified lines
14411471 }
14421472 }
14431473
1474+static struct dc_link *get_link_for_edp(struct dc *dc)
1475+{
1476+ int i;
1477+
1478+ for (i = 0; i < dc->link_count; i++) {
1479+ if (dc->links[i]->connector_signal == SIGNAL_TYPE_EDP)
1480+ return dc->links[i];
1481+ }
1482+ return NULL;
1483+}
1484+
14441485 static struct dc_link *get_link_for_edp_not_in_use(
14451486 struct dc *dc,
14461487 struct dc_state *context)
@@ -1475,20 +1516,21 @@ static struct dc_link *get_link_for_edp_not_in_use( · 28 unmodified lines
14751516 */
14761517 void dce110_enable_accelerated_mode(struct dc *dc, struct dc_state *context)
14771518 {
1478− struct dc_bios *dcb = dc->ctx->dc_bios;
1479−
1480− /* vbios already light up eDP, so we can leverage vbios and skip eDP
1481− * programming
1482− */
1483− bool can_eDP_fast_boot_optimize =
1484− (dcb->funcs->get_vga_enabled_displays(dc->ctx->dc_bios) == ATOM_DISPLAY_LCD1_ACTIVE);
1485−
1486− /* if OS doesn't light up eDP and eDP link is available, we want to disable */
14871519 struct dc_link *edp_link_to_turnoff = NULL;
1520+ struct dc_link *edp_link = get_link_for_edp(dc);
1521+ bool can_eDP_fast_boot_optimize = false;
1522+
1523+ if (edp_link) {
1524+ can_eDP_fast_boot_optimize =
1525+ edp_link->link_enc->funcs->is_dig_enabled(edp_link->link_enc);
1526+ }
14881527
14891528 if (can_eDP_fast_boot_optimize) {
14901529 edp_link_to_turnoff = get_link_for_edp_not_in_use(dc, context);
14911530
1531+ /* if OS doesn't light up eDP and eDP link is available, we want to disable
1532+ * If resume from S4/S5, should optimization.
1533+ */
14921534 if (!edp_link_to_turnoff)
14931535 dc->apply_edp_fast_boot_optimization = true;
14941536 }
@@ -1544,6 +1586,7 @@ static void dce110_set_displaymarks( · 49 unmodified lines
15441586 pipe_ctx->plane_res.mi,
15451587 context->bw.dce.nbp_state_change_wm_ns[num_pipes],
15461588 context->bw.dce.stutter_exit_wm_ns[num_pipes],
1589+ context->bw.dce.stutter_entry_wm_ns[num_pipes],
15471590 context->bw.dce.urgent_wm_ns[num_pipes],
15481591 total_dest_line_time_ns);
15491592 if (i == underlay_idx) {
@@ -1569,6 +1612,7 @@ static void set_safe_displaymarks( · 19 unmodified lines
15691612 MAX_WATERMARK, MAX_WATERMARK, MAX_WATERMARK, MAX_WATERMARK };
15701613 struct dce_watermarks nbp_marks = {
15711614 SAFE_NBP_MARK, SAFE_NBP_MARK, SAFE_NBP_MARK, SAFE_NBP_MARK };
1615+ struct dce_watermarks min_marks = { 0, 0, 0, 0};
15721616
15731617 for (i = 0; i < MAX_PIPES; i++) {
15741618 if (res_ctx->pipe_ctx[i].stream == NULL || res_ctx->pipe_ctx[i].plane_res.mi == NULL)
@@ -1578,6 +1622,7 @@ static void set_safe_displaymarks( · 3 unmodified lines
15781622 res_ctx->pipe_ctx[i].plane_res.mi,
15791623 nbp_marks,
15801624 max_marks,
1625+ min_marks,
15811626 max_marks,
15821627 MAX_WATERMARK);
15831628
@@ -1803,6 +1848,9 @@ static bool should_enable_fbc(struct dc *dc, · 219 unmodified lines
18031848 }
18041849 }
18051850
1851+ /* Pipe context should be found */
1852+ ASSERT(pipe_ctx);
1853+
18061854 /* Only supports eDP */
18071855 if (pipe_ctx->stream->sink->link->connector_signal != SIGNAL_TYPE_EDP)
18081856 return false;
@@ -2699,8 +2747,11 @@ static void dce110_program_front_end_for_pipe( · 890 unmodified lines
26992747 struct dc_plane_state *plane_state = pipe_ctx->plane_state;
27002748 struct xfm_grph_csc_adjustment adjust;
27012749 struct out_csc_color_matrix tbl_entry;
2750+#if defined(CONFIG_DRM_AMD_DC_FBC)
2751+ unsigned int underlay_idx = dc->res_pool->underlay_pipe_index;
2752+#endif
27022753 unsigned int i;
2703− struct dc_context *ctx = dc->ctx;
2754+ DC_LOGGER_INIT();
27042755 memset(&tbl_entry, 0, sizeof(tbl_entry));
27052756
27062757 if (dc->current_state)
@@ -2740,7 +2791,9 @@ static void dce110_program_front_end_for_pipe( · 33 unmodified lines
27402791 program_scaler(dc, pipe_ctx);
27412792
27422793 #if defined(CONFIG_DRM_AMD_DC_FBC)
2743− if (dc->fbc_compressor && old_pipe->stream) {
2794+ /* fbc not applicable on Underlay pipe */
2795+ if (dc->fbc_compressor && old_pipe->stream &&
2796+ pipe_ctx->pipe_idx != underlay_idx) {
27442797 if (plane_state->tiling_info.gfx8.array_mode == DC_ARRAY_LINEAR_GENERAL)
27452798 dc->fbc_compressor->funcs->disable_fbc(dc->fbc_compressor);
27462799 else
@@ -2776,13 +2829,13 @@ static void dce110_program_front_end_for_pipe( · 29 unmodified lines
27762829 dc->hwss.set_output_transfer_func(pipe_ctx, pipe_ctx->stream);
27772830
27782831 DC_LOG_SURFACE(
2779− "Pipe:%d 0x%x: addr hi:0x%x, "
2832+ "Pipe:%d %p: addr hi:0x%x, "
27802833 "addr low:0x%x, "
27812834 "src: %d, %d, %d,"
27822835 " %d; dst: %d, %d, %d, %d;"
27832836 "clip: %d, %d, %d, %d\n",
27842837 pipe_ctx->pipe_idx,
2785− pipe_ctx->plane_state,
2838+ (void *) pipe_ctx->plane_state,
27862839 pipe_ctx->plane_state->address.grph.addr.high_part,
27872840 pipe_ctx->plane_state->address.grph.addr.low_part,
27882841 pipe_ctx->plane_state->src_rect.x,
@@ -2993,7 +3046,7 @@ static const struct hw_sequencer_funcs dce110_funcs = { · 204 unmodified lines
29933046 .get_position = get_position,
29943047 .set_static_screen_control = set_static_screen_control,
29953048 .reset_hw_ctx_wrap = dce110_reset_hw_ctx_wrap,
2996− .prog_pixclk_crtc_otg = dce110_prog_pixclk_crtc_otg,
3049+ .enable_stream_timing = dce110_enable_stream_timing,
29973050 .setup_stereo = NULL,
29983051 .set_avmute = dce110_set_avmute,
29993052 .wait_for_mpcc_disconnect = dce110_wait_for_mpcc_disconnect,
drivers/gpu/drm/amd/display/dc/dce110/dce110_mem_input_v.c+1−0
@@ -923,6 +923,7 @@ void dce_mem_input_v_program_display_marks( · 922 unmodified lines
923923 struct mem_input *mem_input,
924924 struct dce_watermarks nbp,
925925 struct dce_watermarks stutter,
926+ struct dce_watermarks stutter_enter,
926927 struct dce_watermarks urgent,
927928 uint32_t total_dest_line_time_ns)
928929 {
drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c+0−33
@@ -930,38 +930,6 @@ static enum dc_status dce110_add_stream_to_ctx( · 929 unmodified lines
930930 return result;
931931 }
932932
933−static enum dc_status dce110_validate_guaranteed(
934− struct dc *dc,
935− struct dc_stream_state *dc_stream,
936− struct dc_state *context)
937−{
938− enum dc_status result = DC_ERROR_UNEXPECTED;
939−
940− context->streams[0] = dc_stream;
941− dc_stream_retain(context->streams[0]);
942− context->stream_count++;
943−
944− result = resource_map_pool_resources(dc, context, dc_stream);
945−
946− if (result == DC_OK)
947− result = resource_map_clock_resources(dc, context, dc_stream);
948−
949− if (result == DC_OK)
950− result = build_mapped_resource(dc, context, dc_stream);
951−
952− if (result == DC_OK) {
953− validate_guaranteed_copy_streams(
954− context, dc->caps.max_streams);
955− result = resource_build_scaling_params_for_context(dc, context);
956− }
957−
958− if (result == DC_OK)
959− if (!dce110_validate_bandwidth(dc, context))
960− result = DC_FAIL_BANDWIDTH_VALIDATE;
961−
962− return result;
963−}
964−
965933 static struct pipe_ctx *dce110_acquire_underlay(
966934 struct dc_state *context,
967935 const struct resource_pool *pool,
@@ -1036,7 +1004,6 @@ static void dce110_destroy_resource_pool(struct resource_pool **pool) · 68 unmodified lines
10361004 static const struct resource_funcs dce110_res_pool_funcs = {
10371005 .destroy = dce110_destroy_resource_pool,
10381006 .link_enc_create = dce110_link_encoder_create,
1039− .validate_guaranteed = dce110_validate_guaranteed,
10401007 .validate_bandwidth = dce110_validate_bandwidth,
10411008 .validate_plane = dce110_validate_plane,
10421009 .acquire_idle_pipe_for_layer = dce110_acquire_underlay,
drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c+8−8
@@ -431,14 +431,6 @@ void dce110_timing_generator_set_drr( · 430 unmodified lines
431431 0,
432432 CRTC_V_TOTAL_CONTROL,
433433 CRTC_SET_V_TOTAL_MIN_MASK);
434− set_reg_field_value(v_total_min,
435− 0,
436− CRTC_V_TOTAL_MIN,
437− CRTC_V_TOTAL_MIN);
438− set_reg_field_value(v_total_max,
439− 0,
440− CRTC_V_TOTAL_MAX,
441− CRTC_V_TOTAL_MAX);
442434 set_reg_field_value(v_total_cntl,
443435 0,
444436 CRTC_V_TOTAL_CONTROL,
@@ -447,6 +439,14 @@ void dce110_timing_generator_set_drr( · 2 unmodified lines
447439 0,
448440 CRTC_V_TOTAL_CONTROL,
449441 CRTC_V_TOTAL_MAX_SEL);
442+ set_reg_field_value(v_total_min,
443+ 0,
444+ CRTC_V_TOTAL_MIN,
445+ CRTC_V_TOTAL_MIN);
446+ set_reg_field_value(v_total_max,
447+ 0,
448+ CRTC_V_TOTAL_MAX,
449+ CRTC_V_TOTAL_MAX);
450450 set_reg_field_value(v_total_cntl,
451451 0,
452452 CRTC_V_TOTAL_CONTROL,
drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator_v.c+0−7
@@ -648,12 +648,6 @@ static void dce110_timing_generator_v_disable_vga( · 647 unmodified lines
648648 return;
649649 }
650650
651−static bool dce110_tg_v_is_blanked(struct timing_generator *tg)
652−{
653− /* Signal comes from the primary pipe, underlay is never blanked. */
654− return false;
655−}
656−
657651 /** ********************************************************************************************
658652 *
659653 * DCE11 Timing Generator Constructor / Destructor
@@ -670,7 +664,6 @@ static const struct timing_generator_funcs dce110_tg_v_funcs = { · 10 unmodified lines
670664 .set_early_control = dce110_timing_generator_v_set_early_control,
671665 .wait_for_state = dce110_timing_generator_v_wait_for_state,
672666 .set_blank = dce110_timing_generator_v_set_blank,
673− .is_blanked = dce110_tg_v_is_blanked,
674667 .set_colors = dce110_timing_generator_v_set_colors,
675668 .set_overscan_blank_color =
676669 dce110_timing_generator_v_set_overscan_color_black,
drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c+1−34
@@ -430,7 +430,7 @@ static struct stream_encoder *dce112_stream_encoder_create( · 429 unmodified lines
430430
431431 if (!enc110)
432432 return NULL;
433−
433+
434434 dce110_stream_encoder_construct(enc110, ctx, ctx->dc_bios, eng_id,
435435 &stream_enc_regs[eng_id],
436436 &se_shift, &se_mask);
@@ -867,38 +867,6 @@ enum dc_status dce112_add_stream_to_ctx( · 430 unmodified lines
867867 return result;
868868 }
869869
870−enum dc_status dce112_validate_guaranteed(
871− struct dc *dc,
872− struct dc_stream_state *stream,
873− struct dc_state *context)
874−{
875− enum dc_status result = DC_ERROR_UNEXPECTED;
876−
877− context->streams[0] = stream;
878− dc_stream_retain(context->streams[0]);
879− context->stream_count++;
880−
881− result = resource_map_pool_resources(dc, context, stream);
882−
883− if (result == DC_OK)
884− result = resource_map_phy_clock_resources(dc, context, stream);
885−
886− if (result == DC_OK)
887− result = build_mapped_resource(dc, context, stream);
888−
889− if (result == DC_OK) {
890− validate_guaranteed_copy_streams(
891− context, dc->caps.max_streams);
892− result = resource_build_scaling_params_for_context(dc, context);
893− }
894−
895− if (result == DC_OK)
896− if (!dce112_validate_bandwidth(dc, context))
897− result = DC_FAIL_BANDWIDTH_VALIDATE;
898−
899− return result;
900−}
901−
902870 enum dc_status dce112_validate_global(
903871 struct dc *dc,
904872 struct dc_state *context)
@@ -921,7 +889,6 @@ static void dce112_destroy_resource_pool(struct resource_pool **pool) · 16 unmodified lines
921889 static const struct resource_funcs dce112_res_pool_funcs = {
922890 .destroy = dce112_destroy_resource_pool,
923891 .link_enc_create = dce112_link_encoder_create,
924− .validate_guaranteed = dce112_validate_guaranteed,
925892 .validate_bandwidth = dce112_validate_bandwidth,
926893 .validate_plane = dce100_validate_plane,
927894 .add_stream_to_ctx = dce112_add_stream_to_ctx,
drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.h+0−5
@@ -42,11 +42,6 @@ enum dc_status dce112_validate_with_context( · 41 unmodified lines
4242 struct dc_state *context,
4343 struct dc_state *old_context);
4444
45−enum dc_status dce112_validate_guaranteed(
46− struct dc *dc,
47− struct dc_stream_state *dc_stream,
48− struct dc_state *context);
49−
5045 bool dce112_validate_bandwidth(
5146 struct dc *dc,
5247 struct dc_state *context);
drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c+1−2
@@ -652,7 +652,7 @@ static struct mem_input *dce120_mem_input_create( · 651 unmodified lines
652652 return NULL;
653653 }
654654
655− dce112_mem_input_construct(dce_mi, ctx, inst, &mi_regs[inst], &mi_shifts, &mi_masks);
655+ dce120_mem_input_construct(dce_mi, ctx, inst, &mi_regs[inst], &mi_shifts, &mi_masks);
656656 return &dce_mi->base;
657657 }
658658
@@ -684,7 +684,6 @@ static void dce120_destroy_resource_pool(struct resource_pool **pool) · 25 unmodified lines
684684 static const struct resource_funcs dce120_res_pool_funcs = {
685685 .destroy = dce120_destroy_resource_pool,
686686 .link_enc_create = dce120_link_encoder_create,
687− .validate_guaranteed = dce112_validate_guaranteed,
688687 .validate_bandwidth = dce112_validate_bandwidth,
689688 .validate_plane = dce100_validate_plane,
690689 .add_stream_to_ctx = dce112_add_stream_to_ctx
drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c+6−6
@@ -570,18 +570,18 @@ void dce120_timing_generator_set_drr( · 569 unmodified lines
570570 0x180);
571571
572572 } else {
573− CRTC_REG_UPDATE(
574− CRTC0_CRTC_V_TOTAL_MIN,
575− CRTC_V_TOTAL_MIN, 0);
576− CRTC_REG_UPDATE(
577− CRTC0_CRTC_V_TOTAL_MAX,
578− CRTC_V_TOTAL_MAX, 0);
579573 CRTC_REG_SET_N(CRTC0_CRTC_V_TOTAL_CONTROL, 5,
580574 FD(CRTC0_CRTC_V_TOTAL_CONTROL__CRTC_V_TOTAL_MIN_SEL), 0,
581575 FD(CRTC0_CRTC_V_TOTAL_CONTROL__CRTC_V_TOTAL_MAX_SEL), 0,
582576 FD(CRTC0_CRTC_V_TOTAL_CONTROL__CRTC_FORCE_LOCK_ON_EVENT), 0,
583577 FD(CRTC0_CRTC_V_TOTAL_CONTROL__CRTC_FORCE_LOCK_TO_MASTER_VSYNC), 0,
584578 FD(CRTC0_CRTC_V_TOTAL_CONTROL__CRTC_SET_V_TOTAL_MIN_MASK), 0);
579+ CRTC_REG_UPDATE(
580+ CRTC0_CRTC_V_TOTAL_MIN,
581+ CRTC_V_TOTAL_MIN, 0);
582+ CRTC_REG_UPDATE(
583+ CRTC0_CRTC_V_TOTAL_MAX,
584+ CRTC_V_TOTAL_MAX, 0);
585585 CRTC_REG_UPDATE(
586586 CRTC0_CRTC_STATIC_SCREEN_CONTROL,
587587 CRTC_STATIC_SCREEN_EVENT_MASK,
drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c+0−49
@@ -691,23 +691,6 @@ static void destruct(struct dce110_resource_pool *pool) · 690 unmodified lines
691691 }
692692 }
693693
694−static enum dc_status build_mapped_resource(
695− const struct dc *dc,
696− struct dc_state *context,
697− struct dc_stream_state *stream)
698−{
699− struct pipe_ctx *pipe_ctx = resource_get_head_pipe_for_stream(&context->res_ctx, stream);
700−
701− if (!pipe_ctx)
702− return DC_ERROR_UNEXPECTED;
703−
704− dce110_resource_build_pipe_hw_param(pipe_ctx);
705−
706− resource_build_info_frame(pipe_ctx);
707−
708− return DC_OK;
709−}
710−
711694 bool dce80_validate_bandwidth(
712695 struct dc *dc,
713696 struct dc_state *context)
@@ -749,37 +732,6 @@ enum dc_status dce80_validate_global( · 35 unmodified lines
749732 return DC_OK;
750733 }
751734
752−enum dc_status dce80_validate_guaranteed(
753− struct dc *dc,
754− struct dc_stream_state *dc_stream,
755− struct dc_state *context)
756−{
757− enum dc_status result = DC_ERROR_UNEXPECTED;
758−
759− context->streams[0] = dc_stream;
760− dc_stream_retain(context->streams[0]);
761− context->stream_count++;
762−
763− result = resource_map_pool_resources(dc, context, dc_stream);
764−
765− if (result == DC_OK)
766− result = resource_map_clock_resources(dc, context, dc_stream);
767−
768− if (result == DC_OK)
769− result = build_mapped_resource(dc, context, dc_stream);
770−
771− if (result == DC_OK) {
772− validate_guaranteed_copy_streams(
773− context, dc->caps.max_streams);
774− result = resource_build_scaling_params_for_context(dc, context);
775− }
776−
777− if (result == DC_OK)
778− result = dce80_validate_bandwidth(dc, context);
779−
780− return result;
781−}
782−
783735 static void dce80_destroy_resource_pool(struct resource_pool **pool)
784736 {
785737 struct dce110_resource_pool *dce110_pool = TO_DCE110_RES_POOL(*pool);
@@ -792,7 +744,6 @@ static void dce80_destroy_resource_pool(struct resource_pool **pool) · 6 unmodified lines
792744 static const struct resource_funcs dce80_res_pool_funcs = {
793745 .destroy = dce80_destroy_resource_pool,
794746 .link_enc_create = dce80_link_encoder_create,
795− .validate_guaranteed = dce80_validate_guaranteed,
796747 .validate_bandwidth = dce80_validate_bandwidth,
797748 .validate_plane = dce100_validate_plane,
798749 .add_stream_to_ctx = dce100_add_stream_to_ctx,
drivers/gpu/drm/amd/display/dc/dcn10/Makefile+1−1
@@ -26,7 +26,7 @@ DCN10 = dcn10_resource.o dcn10_ipp.o dcn10_hw_sequencer.o \ · 25 unmodified lines
2626 dcn10_dpp.o dcn10_opp.o dcn10_optc.o \
2727 dcn10_hubp.o dcn10_mpc.o \
2828 dcn10_dpp_dscl.o dcn10_dpp_cm.o dcn10_cm_common.o \
29− dcn10_hubbub.o
29+ dcn10_hubbub.o dcn10_stream_encoder.o
3030
3131 AMD_DAL_DCN10 = $(addprefix $(AMDDALPATH)/dc/dcn10/,$(DCN10))
3232
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_cm_common.c+6−6
@@ -367,15 +367,15 @@ bool cm_helper_translate_curve_to_hw_format( · 366 unmodified lines
367367
368368 lut_params->hw_points_num = hw_points;
369369
370− i = 1;
371− for (k = 0; k < MAX_REGIONS_NUMBER && i < MAX_REGIONS_NUMBER; k++) {
370+ k = 0;
371+ for (i = 1; i < MAX_REGIONS_NUMBER; i++) {
372372 if (seg_distr[k] != -1) {
373373 lut_params->arr_curve_points[k].segments_num =
374374 seg_distr[k];
375375 lut_params->arr_curve_points[i].offset =
376376 lut_params->arr_curve_points[k].offset + (1 << seg_distr[k]);
377377 }
378− i++;
378+ k++;
379379 }
380380
381381 if (seg_distr[k] != -1)
@@ -529,15 +529,15 @@ bool cm_helper_translate_curve_to_degamma_hw_format( · 147 unmodified lines
529529
530530 lut_params->hw_points_num = hw_points;
531531
532− i = 1;
533− for (k = 0; k < MAX_REGIONS_NUMBER && i < MAX_REGIONS_NUMBER; k++) {
532+ k = 0;
533+ for (i = 1; i < MAX_REGIONS_NUMBER; i++) {
534534 if (seg_distr[k] != -1) {
535535 lut_params->arr_curve_points[k].segments_num =
536536 seg_distr[k];
537537 lut_params->arr_curve_points[i].offset =
538538 lut_params->arr_curve_points[k].offset + (1 << seg_distr[k]);
539539 }
540− i++;
540+ k++;
541541 }
542542
543543 if (seg_distr[k] != -1)
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c+34−2
@@ -98,6 +98,30 @@ enum gamut_remap_select { · 97 unmodified lines
9898 GAMUT_REMAP_COMB_COEFF
9999 };
100100
101+void dpp_read_state(struct dpp *dpp_base,
102+ struct dcn_dpp_state *s)
103+{
104+ struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base);
105+
106+ REG_GET(CM_IGAM_CONTROL,
107+ CM_IGAM_LUT_MODE, &s->igam_lut_mode);
108+ REG_GET(CM_IGAM_CONTROL,
109+ CM_IGAM_INPUT_FORMAT, &s->igam_input_format);
110+ REG_GET(CM_DGAM_CONTROL,
111+ CM_DGAM_LUT_MODE, &s->dgam_lut_mode);
112+ REG_GET(CM_RGAM_CONTROL,
113+ CM_RGAM_LUT_MODE, &s->rgam_lut_mode);
114+ REG_GET(CM_GAMUT_REMAP_CONTROL,
115+ CM_GAMUT_REMAP_MODE, &s->gamut_remap_mode);
116+
117+ s->gamut_remap_c11_c12 = REG_READ(CM_GAMUT_REMAP_C11_C12);
118+ s->gamut_remap_c13_c14 = REG_READ(CM_GAMUT_REMAP_C13_C14);
119+ s->gamut_remap_c21_c22 = REG_READ(CM_GAMUT_REMAP_C21_C22);
120+ s->gamut_remap_c23_c24 = REG_READ(CM_GAMUT_REMAP_C23_C24);
121+ s->gamut_remap_c31_c32 = REG_READ(CM_GAMUT_REMAP_C31_C32);
122+ s->gamut_remap_c33_c34 = REG_READ(CM_GAMUT_REMAP_C33_C34);
123+}
124+
101125 /* Program gamut remap in bypass mode */
102126 void dpp_set_gamut_remap_bypass(struct dcn10_dpp *dpp)
103127 {
@@ -121,6 +145,13 @@ bool dpp_get_optimal_number_of_taps( · 17 unmodified lines
121145 else
122146 pixel_width = scl_data->viewport.width;
123147
148+ /* Some ASICs does not support FP16 scaling, so we reject modes require this*/
149+ if (scl_data->viewport.width != scl_data->h_active &&
150+ scl_data->viewport.height != scl_data->v_active &&
151+ dpp->caps->dscl_data_proc_format == DSCL_DATA_PRCESSING_FIXED_FORMAT &&
152+ scl_data->format == PIXEL_FORMAT_FP16)
153+ return false;
154+
124155 /* TODO: add lb check */
125156
126157 /* No support for programming ratio of 4, drop to 3.99999.. */
@@ -257,7 +288,7 @@ void dpp1_cnv_setup ( · 130 unmodified lines
257288 struct dpp *dpp_base,
258289 enum surface_pixel_format format,
259290 enum expansion_mode mode,
260− struct csc_transform input_csc_color_matrix,
291+ struct dc_csc_transform input_csc_color_matrix,
261292 enum dc_color_space input_color_space)
262293 {
263294 uint32_t pixel_format;
@@ -416,7 +447,7 @@ void dpp1_set_cursor_position( · 152 unmodified lines
416447 if (src_x_offset >= (int)param->viewport_width)
417448 cur_en = 0; /* not visible beyond right edge*/
418449
419− if (src_x_offset + (int)width < 0)
450+ if (src_x_offset + (int)width <= 0)
420451 cur_en = 0; /* not visible beyond left edge*/
421452
422453 REG_UPDATE(CURSOR0_CONTROL,
@@ -443,6 +474,7 @@ void dpp1_dppclk_control( · 20 unmodified lines
443474 }
444475
445476 static const struct dpp_funcs dcn10_dpp_funcs = {
477+ .dpp_read_state = dpp_read_state,
446478 .dpp_reset = dpp_reset,
447479 .dpp_set_scaler = dpp1_dscl_set_scaler_manual_scale,
448480 .dpp_get_optimal_number_of_taps = dpp_get_optimal_number_of_taps,
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h+73−3
@@ -44,6 +44,10 @@ · 43 unmodified lines
4444 #define TF_REG_LIST_DCN(id) \
4545 SRI(CM_GAMUT_REMAP_CONTROL, CM, id),\
4646 SRI(CM_GAMUT_REMAP_C11_C12, CM, id),\
47+ SRI(CM_GAMUT_REMAP_C13_C14, CM, id),\
48+ SRI(CM_GAMUT_REMAP_C21_C22, CM, id),\
49+ SRI(CM_GAMUT_REMAP_C23_C24, CM, id),\
50+ SRI(CM_GAMUT_REMAP_C31_C32, CM, id),\
4751 SRI(CM_GAMUT_REMAP_C33_C34, CM, id),\
4852 SRI(DSCL_EXT_OVERSCAN_LEFT_RIGHT, DSCL, id), \
4953 SRI(DSCL_EXT_OVERSCAN_TOP_BOTTOM, DSCL, id), \
@@ -108,6 +112,8 @@ · 58 unmodified lines
108112 SRI(CM_DGAM_LUT_DATA, CM, id), \
109113 SRI(CM_CONTROL, CM, id), \
110114 SRI(CM_DGAM_CONTROL, CM, id), \
115+ SRI(CM_TEST_DEBUG_INDEX, CM, id), \
116+ SRI(CM_TEST_DEBUG_DATA, CM, id), \
111117 SRI(FORMAT_CONTROL, CNVC_CFG, id), \
112118 SRI(CNVC_SURFACE_PIXEL_FORMAT, CNVC_CFG, id), \
113119 SRI(CURSOR0_CONTROL, CNVC_CUR, id), \
@@ -175,6 +181,14 @@ · 61 unmodified lines
175181 TF_SF(CM0_CM_GAMUT_REMAP_CONTROL, CM_GAMUT_REMAP_MODE, mask_sh),\
176182 TF_SF(CM0_CM_GAMUT_REMAP_C11_C12, CM_GAMUT_REMAP_C11, mask_sh),\
177183 TF_SF(CM0_CM_GAMUT_REMAP_C11_C12, CM_GAMUT_REMAP_C12, mask_sh),\
184+ TF_SF(CM0_CM_GAMUT_REMAP_C13_C14, CM_GAMUT_REMAP_C13, mask_sh),\
185+ TF_SF(CM0_CM_GAMUT_REMAP_C13_C14, CM_GAMUT_REMAP_C14, mask_sh),\
186+ TF_SF(CM0_CM_GAMUT_REMAP_C21_C22, CM_GAMUT_REMAP_C21, mask_sh),\
187+ TF_SF(CM0_CM_GAMUT_REMAP_C21_C22, CM_GAMUT_REMAP_C22, mask_sh),\
188+ TF_SF(CM0_CM_GAMUT_REMAP_C23_C24, CM_GAMUT_REMAP_C23, mask_sh),\
189+ TF_SF(CM0_CM_GAMUT_REMAP_C23_C24, CM_GAMUT_REMAP_C24, mask_sh),\
190+ TF_SF(CM0_CM_GAMUT_REMAP_C31_C32, CM_GAMUT_REMAP_C31, mask_sh),\
191+ TF_SF(CM0_CM_GAMUT_REMAP_C31_C32, CM_GAMUT_REMAP_C32, mask_sh),\
178192 TF_SF(CM0_CM_GAMUT_REMAP_C33_C34, CM_GAMUT_REMAP_C33, mask_sh),\
179193 TF_SF(CM0_CM_GAMUT_REMAP_C33_C34, CM_GAMUT_REMAP_C34, mask_sh),\
180194 TF_SF(DSCL0_DSCL_EXT_OVERSCAN_LEFT_RIGHT, EXT_OVERSCAN_LEFT, mask_sh),\
@@ -300,6 +314,7 @@ · 119 unmodified lines
300314 TF_SF(CM0_CM_DGAM_LUT_INDEX, CM_DGAM_LUT_INDEX, mask_sh), \
301315 TF_SF(CM0_CM_DGAM_LUT_DATA, CM_DGAM_LUT_DATA, mask_sh), \
302316 TF_SF(CM0_CM_DGAM_CONTROL, CM_DGAM_LUT_MODE, mask_sh), \
317+ TF_SF(CM0_CM_TEST_DEBUG_INDEX, CM_TEST_DEBUG_INDEX, mask_sh), \
303318 TF_SF(CNVC_CFG0_FORMAT_CONTROL, CNVC_BYPASS, mask_sh), \
304319 TF2_SF(CNVC_CFG0, FORMAT_CONTROL__ALPHA_EN, mask_sh), \
305320 TF_SF(CNVC_CFG0_FORMAT_CONTROL, FORMAT_EXPANSION_MODE, mask_sh), \
@@ -417,6 +432,41 @@ · 111 unmodified lines
417432 TF_SF(CURSOR0_CURSOR_CONTROL, CURSOR_ENABLE, mask_sh), \
418433 TF_SF(DPP_TOP0_DPP_CONTROL, DPPCLK_RATE_CONTROL, mask_sh)
419434
435+/*
436+ *
437+ DCN1 CM debug status register definition
438+
439+ register :ID9_CM_STATUS do
440+ implement_ref :cm
441+ map to: :cmdebugind, at: j
442+ width 32
443+ disclosure NEVER
444+
445+ field :ID9_VUPDATE_CFG, [0], R
446+ field :ID9_IGAM_LUT_MODE, [2..1], R
447+ field :ID9_BNS_BYPASS, [3], R
448+ field :ID9_ICSC_MODE, [5..4], R
449+ field :ID9_DGAM_LUT_MODE, [8..6], R
450+ field :ID9_HDR_BYPASS, [9], R
451+ field :ID9_GAMUT_REMAP_MODE, [11..10], R
452+ field :ID9_RGAM_LUT_MODE, [14..12], R
453+ #1 free bit
454+ field :ID9_OCSC_MODE, [18..16], R
455+ field :ID9_DENORM_MODE, [21..19], R
456+ field :ID9_ROUND_TRUNC_MODE, [25..22], R
457+ field :ID9_DITHER_EN, [26], R
458+ field :ID9_DITHER_MODE, [28..27], R
459+ end
460+*/
461+
462+#define TF_DEBUG_REG_LIST_SH_DCN10 \
463+ .CM_TEST_DEBUG_DATA_ID9_ICSC_MODE = 4, \
464+ .CM_TEST_DEBUG_DATA_ID9_OCSC_MODE = 16
465+
466+#define TF_DEBUG_REG_LIST_MASK_DCN10 \
467+ .CM_TEST_DEBUG_DATA_ID9_ICSC_MODE = 0x30, \
468+ .CM_TEST_DEBUG_DATA_ID9_OCSC_MODE = 0x70000
469+
420470 #define TF_REG_FIELD_LIST(type) \
421471 type EXT_OVERSCAN_LEFT; \
422472 type EXT_OVERSCAN_RIGHT; \
@@ -486,6 +536,14 @@ · 63 unmodified lines
486536 type CM_GAMUT_REMAP_MODE; \
487537 type CM_GAMUT_REMAP_C11; \
488538 type CM_GAMUT_REMAP_C12; \
539+ type CM_GAMUT_REMAP_C13; \
540+ type CM_GAMUT_REMAP_C14; \
541+ type CM_GAMUT_REMAP_C21; \
542+ type CM_GAMUT_REMAP_C22; \
543+ type CM_GAMUT_REMAP_C23; \
544+ type CM_GAMUT_REMAP_C24; \
545+ type CM_GAMUT_REMAP_C31; \
546+ type CM_GAMUT_REMAP_C32; \
489547 type CM_GAMUT_REMAP_C33; \
490548 type CM_GAMUT_REMAP_C34; \
491549 type CM_COMA_C11; \
@@ -1010,6 +1068,9 @@ · 518 unmodified lines
10101068 type CUR0_EXPANSION_MODE; \
10111069 type CUR0_ENABLE; \
10121070 type CM_BYPASS; \
1071+ type CM_TEST_DEBUG_INDEX; \
1072+ type CM_TEST_DEBUG_DATA_ID9_ICSC_MODE; \
1073+ type CM_TEST_DEBUG_DATA_ID9_OCSC_MODE;\
10131074 type FORMAT_CONTROL__ALPHA_EN; \
10141075 type CUR0_COLOR0; \
10151076 type CUR0_COLOR1; \
@@ -1054,6 +1115,10 @@ struct dcn_dpp_mask { · 38 unmodified lines
10541115 uint32_t RECOUT_SIZE; \
10551116 uint32_t CM_GAMUT_REMAP_CONTROL; \
10561117 uint32_t CM_GAMUT_REMAP_C11_C12; \
1118+ uint32_t CM_GAMUT_REMAP_C13_C14; \
1119+ uint32_t CM_GAMUT_REMAP_C21_C22; \
1120+ uint32_t CM_GAMUT_REMAP_C23_C24; \
1121+ uint32_t CM_GAMUT_REMAP_C31_C32; \
10571122 uint32_t CM_GAMUT_REMAP_C33_C34; \
10581123 uint32_t CM_COMA_C11_C12; \
10591124 uint32_t CM_COMA_C33_C34; \
@@ -1255,6 +1320,8 @@ struct dcn_dpp_mask { · 195 unmodified lines
12551320 uint32_t CM_IGAM_LUT_RW_CONTROL; \
12561321 uint32_t CM_IGAM_LUT_RW_INDEX; \
12571322 uint32_t CM_IGAM_LUT_SEQ_COLOR; \
1323+ uint32_t CM_TEST_DEBUG_INDEX; \
1324+ uint32_t CM_TEST_DEBUG_DATA; \
12581325 uint32_t FORMAT_CONTROL; \
12591326 uint32_t CNVC_SURFACE_PIXEL_FORMAT; \
12601327 uint32_t CURSOR_CONTROL; \
@@ -1289,8 +1356,8 @@ struct dcn10_dpp { · 28 unmodified lines
12891356
12901357 enum dcn10_input_csc_select {
12911358 INPUT_CSC_SELECT_BYPASS = 0,
1292− INPUT_CSC_SELECT_ICSC,
1293− INPUT_CSC_SELECT_COMA
1359+ INPUT_CSC_SELECT_ICSC = 1,
1360+ INPUT_CSC_SELECT_COMA = 2
12941361 };
12951362
12961363 void dpp1_set_cursor_attributes(
@@ -1364,6 +1431,9 @@ bool dpp_get_optimal_number_of_taps( · 67 unmodified lines
13641431 struct scaler_data *scl_data,
13651432 const struct scaling_taps *in_taps);
13661433
1434+void dpp_read_state(struct dpp *dpp_base,
1435+ struct dcn_dpp_state *s);
1436+
13671437 void dpp_reset(struct dpp *dpp_base);
13681438
13691439 void dpp1_cm_program_regamma_lut(
@@ -1408,7 +1478,7 @@ void dpp1_cnv_setup ( · 38 unmodified lines
14081478 struct dpp *dpp_base,
14091479 enum surface_pixel_format format,
14101480 enum expansion_mode mode,
1411− struct csc_transform input_csc_color_matrix,
1481+ struct dc_csc_transform input_csc_color_matrix,
14121482 enum dc_color_space input_color_space);
14131483
14141484 void dpp1_full_bypass(struct dpp *dpp_base);
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c+56−34
@@ -216,41 +216,55 @@ static void dpp1_cm_program_color_matrix( · 215 unmodified lines
216216 struct dcn10_dpp *dpp,
217217 const uint16_t *regval)
218218 {
219− uint32_t mode;
219+ uint32_t ocsc_mode;
220+ uint32_t cur_mode;
220221 struct color_matrices_reg gam_regs;
221222
222− REG_GET(CM_OCSC_CONTROL, CM_OCSC_MODE, &mode);
223−
224223 if (regval == NULL) {
225224 BREAK_TO_DEBUGGER();
226225 return;
227226 }
228− mode = 4;
227+
228+ /* determine which CSC matrix (ocsc or comb) we are using
229+ * currently. select the alternate set to double buffer
230+ * the CSC update so CSC is updated on frame boundary
231+ */
232+ REG_SET(CM_TEST_DEBUG_INDEX, 0,
233+ CM_TEST_DEBUG_INDEX, 9);
234+
235+ REG_GET(CM_TEST_DEBUG_DATA,
236+ CM_TEST_DEBUG_DATA_ID9_OCSC_MODE, &cur_mode);
237+
238+ if (cur_mode != 4)
239+ ocsc_mode = 4;
240+ else
241+ ocsc_mode = 5;
242+
243+
229244 gam_regs.shifts.csc_c11 = dpp->tf_shift->CM_OCSC_C11;
230245 gam_regs.masks.csc_c11 = dpp->tf_mask->CM_OCSC_C11;
231246 gam_regs.shifts.csc_c12 = dpp->tf_shift->CM_OCSC_C12;
232247 gam_regs.masks.csc_c12 = dpp->tf_mask->CM_OCSC_C12;
233248
234− if (mode == 4) {
249+ if (ocsc_mode == 4) {
235250
236251 gam_regs.csc_c11_c12 = REG(CM_OCSC_C11_C12);
237252 gam_regs.csc_c33_c34 = REG(CM_OCSC_C33_C34);
238253
239− cm_helper_program_color_matrices(
240− dpp->base.ctx,
241− regval,
242− &gam_regs);
243−
244254 } else {
245255
246256 gam_regs.csc_c11_c12 = REG(CM_COMB_C11_C12);
247257 gam_regs.csc_c33_c34 = REG(CM_COMB_C33_C34);
248258
249− cm_helper_program_color_matrices(
250− dpp->base.ctx,
251− regval,
252− &gam_regs);
253259 }
260+
261+ cm_helper_program_color_matrices(
262+ dpp->base.ctx,
263+ regval,
264+ &gam_regs);
265+
266+ REG_SET(CM_OCSC_CONTROL, 0, CM_OCSC_MODE, ocsc_mode);
267+
254268 }
255269
256270 void dpp1_cm_set_output_csc_default(
@@ -260,15 +274,14 @@ void dpp1_cm_set_output_csc_default( · 3 unmodified lines
260274 struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base);
261275 const uint16_t *regval = NULL;
262276 int arr_size;
263− uint32_t ocsc_mode = 4;
264277
265278 regval = find_color_matrix(colorspace, &arr_size);
266279 if (regval == NULL) {
267280 BREAK_TO_DEBUGGER();
268281 return;
269282 }
283+
270284 dpp1_cm_program_color_matrix(dpp, regval);
271− REG_SET(CM_OCSC_CONTROL, 0, CM_OCSC_MODE, ocsc_mode);
272285 }
273286
274287 static void dpp1_cm_get_reg_field(
@@ -329,9 +342,8 @@ void dpp1_cm_set_output_csc_adjustment( · 54 unmodified lines
329342 const uint16_t *regval)
330343 {
331344 struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base);
332− uint32_t ocsc_mode = 4;
345+
333346 dpp1_cm_program_color_matrix(dpp, regval);
334− REG_SET(CM_OCSC_CONTROL, 0, CM_OCSC_MODE, ocsc_mode);
335347 }
336348
337349 void dpp1_cm_power_on_regamma_lut(struct dpp *dpp_base,
@@ -437,17 +449,18 @@ void dpp1_cm_program_regamma_lutb_settings( · 99 unmodified lines
437449 void dpp1_program_input_csc(
438450 struct dpp *dpp_base,
439451 enum dc_color_space color_space,
440− enum dcn10_input_csc_select select,
452+ enum dcn10_input_csc_select input_select,
441453 const struct out_csc_color_matrix *tbl_entry)
442454 {
443455 struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base);
444456 int i;
445457 int arr_size = sizeof(dcn10_input_csc_matrix)/sizeof(struct dcn10_input_csc_matrix);
446458 const uint16_t *regval = NULL;
447− uint32_t selection = 1;
459+ uint32_t cur_select = 0;
460+ enum dcn10_input_csc_select select;
448461 struct color_matrices_reg gam_regs;
449462
450− if (select == INPUT_CSC_SELECT_BYPASS) {
463+ if (input_select == INPUT_CSC_SELECT_BYPASS) {
451464 REG_SET(CM_ICSC_CONTROL, 0, CM_ICSC_MODE, 0);
452465 return;
453466 }
@@ -467,36 +480,45 @@ void dpp1_program_input_csc( · 13 unmodified lines
467480 regval = tbl_entry->regval;
468481 }
469482
470− if (select == INPUT_CSC_SELECT_COMA)
471− selection = 2;
472− REG_SET(CM_ICSC_CONTROL, 0,
473− CM_ICSC_MODE, selection);
483+ /* determine which CSC matrix (icsc or coma) we are using
484+ * currently. select the alternate set to double buffer
485+ * the CSC update so CSC is updated on frame boundary
486+ */
487+ REG_SET(CM_TEST_DEBUG_INDEX, 0,
488+ CM_TEST_DEBUG_INDEX, 9);
489+
490+ REG_GET(CM_TEST_DEBUG_DATA,
491+ CM_TEST_DEBUG_DATA_ID9_ICSC_MODE, &cur_select);
492+
493+ if (cur_select != INPUT_CSC_SELECT_ICSC)
494+ select = INPUT_CSC_SELECT_ICSC;
495+ else
496+ select = INPUT_CSC_SELECT_COMA;
474497
475498 gam_regs.shifts.csc_c11 = dpp->tf_shift->CM_ICSC_C11;
476499 gam_regs.masks.csc_c11 = dpp->tf_mask->CM_ICSC_C11;
477500 gam_regs.shifts.csc_c12 = dpp->tf_shift->CM_ICSC_C12;
478501 gam_regs.masks.csc_c12 = dpp->tf_mask->CM_ICSC_C12;
479502
480−
481503 if (select == INPUT_CSC_SELECT_ICSC) {
482504
483505 gam_regs.csc_c11_c12 = REG(CM_ICSC_C11_C12);
484506 gam_regs.csc_c33_c34 = REG(CM_ICSC_C33_C34);
485507
486− cm_helper_program_color_matrices(
487− dpp->base.ctx,
488− regval,
489− &gam_regs);
490508 } else {
491509
492510 gam_regs.csc_c11_c12 = REG(CM_COMA_C11_C12);
493511 gam_regs.csc_c33_c34 = REG(CM_COMA_C33_C34);
494512
495− cm_helper_program_color_matrices(
496− dpp->base.ctx,
497− regval,
498− &gam_regs);
499513 }
514+
515+ cm_helper_program_color_matrices(
516+ dpp->base.ctx,
517+ regval,
518+ &gam_regs);
519+
520+ REG_SET(CM_ICSC_CONTROL, 0,
521+ CM_ICSC_MODE, select);
500522 }
501523
502524 //keep here for now, decide multi dce support later
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.c+220−1
@@ -476,8 +476,227 @@ void hubbub1_toggle_watermark_change_req(struct hubbub *hubbub) · 475 unmodified lines
476476 DCHUBBUB_ARB_WATERMARK_CHANGE_REQUEST, watermark_change_req);
477477 }
478478
479+static bool hubbub1_dcc_support_swizzle(
480+ enum swizzle_mode_values swizzle,
481+ unsigned int bytes_per_element,
482+ enum segment_order *segment_order_horz,
483+ enum segment_order *segment_order_vert)
484+{
485+ bool standard_swizzle = false;
486+ bool display_swizzle = false;
487+
488+ switch (swizzle) {
489+ case DC_SW_4KB_S:
490+ case DC_SW_64KB_S:
491+ case DC_SW_VAR_S:
492+ case DC_SW_4KB_S_X:
493+ case DC_SW_64KB_S_X:
494+ case DC_SW_VAR_S_X:
495+ standard_swizzle = true;
496+ break;
497+ case DC_SW_4KB_D:
498+ case DC_SW_64KB_D:
499+ case DC_SW_VAR_D:
500+ case DC_SW_4KB_D_X:
501+ case DC_SW_64KB_D_X:
502+ case DC_SW_VAR_D_X:
503+ display_swizzle = true;
504+ break;
505+ default:
506+ break;
507+ }
508+
509+ if (bytes_per_element == 1 && standard_swizzle) {
510+ *segment_order_horz = segment_order__contiguous;
511+ *segment_order_vert = segment_order__na;
512+ return true;
513+ }
514+ if (bytes_per_element == 2 && standard_swizzle) {
515+ *segment_order_horz = segment_order__non_contiguous;
516+ *segment_order_vert = segment_order__contiguous;
517+ return true;
518+ }
519+ if (bytes_per_element == 4 && standard_swizzle) {
520+ *segment_order_horz = segment_order__non_contiguous;
521+ *segment_order_vert = segment_order__contiguous;
522+ return true;
523+ }
524+ if (bytes_per_element == 8 && standard_swizzle) {
525+ *segment_order_horz = segment_order__na;
526+ *segment_order_vert = segment_order__contiguous;
527+ return true;
528+ }
529+ if (bytes_per_element == 8 && display_swizzle) {
530+ *segment_order_horz = segment_order__contiguous;
531+ *segment_order_vert = segment_order__non_contiguous;
532+ return true;
533+ }
534+
535+ return false;
536+}
537+
538+static bool hubbub1_dcc_support_pixel_format(
539+ enum surface_pixel_format format,
540+ unsigned int *bytes_per_element)
541+{
542+ /* DML: get_bytes_per_element */
543+ switch (format) {
544+ case SURFACE_PIXEL_FORMAT_GRPH_ARGB1555:
545+ case SURFACE_PIXEL_FORMAT_GRPH_RGB565:
546+ *bytes_per_element = 2;
547+ return true;
548+ case SURFACE_PIXEL_FORMAT_GRPH_ARGB8888:
549+ case SURFACE_PIXEL_FORMAT_GRPH_ABGR8888:
550+ case SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010:
551+ case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010:
552+ *bytes_per_element = 4;
553+ return true;
554+ case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616:
555+ case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F:
556+ case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F:
557+ *bytes_per_element = 8;
558+ return true;
559+ default:
560+ return false;
561+ }
562+}
563+
564+static void hubbub1_get_blk256_size(unsigned int *blk256_width, unsigned int *blk256_height,
565+ unsigned int bytes_per_element)
566+{
567+ /* copied from DML. might want to refactor DML to leverage from DML */
568+ /* DML : get_blk256_size */
569+ if (bytes_per_element == 1) {
570+ *blk256_width = 16;
571+ *blk256_height = 16;
572+ } else if (bytes_per_element == 2) {
573+ *blk256_width = 16;
574+ *blk256_height = 8;
575+ } else if (bytes_per_element == 4) {
576+ *blk256_width = 8;
577+ *blk256_height = 8;
578+ } else if (bytes_per_element == 8) {
579+ *blk256_width = 8;
580+ *blk256_height = 4;
581+ }
582+}
583+
584+static void hubbub1_det_request_size(
585+ unsigned int height,
586+ unsigned int width,
587+ unsigned int bpe,
588+ bool *req128_horz_wc,
589+ bool *req128_vert_wc)
590+{
591+ unsigned int detile_buf_size = 164 * 1024; /* 164KB for DCN1.0 */
592+
593+ unsigned int blk256_height = 0;
594+ unsigned int blk256_width = 0;
595+ unsigned int swath_bytes_horz_wc, swath_bytes_vert_wc;
596+
597+ hubbub1_get_blk256_size(&blk256_width, &blk256_height, bpe);
598+
599+ swath_bytes_horz_wc = height * blk256_height * bpe;
600+ swath_bytes_vert_wc = width * blk256_width * bpe;
601+
602+ *req128_horz_wc = (2 * swath_bytes_horz_wc <= detile_buf_size) ?
603+ false : /* full 256B request */
604+ true; /* half 128b request */
605+
606+ *req128_vert_wc = (2 * swath_bytes_vert_wc <= detile_buf_size) ?
607+ false : /* full 256B request */
608+ true; /* half 128b request */
609+}
610+
611+static bool hubbub1_get_dcc_compression_cap(struct hubbub *hubbub,
612+ const struct dc_dcc_surface_param *input,
613+ struct dc_surface_dcc_cap *output)
614+{
615+ struct dc *dc = hubbub->ctx->dc;
616+ /* implement section 1.6.2.1 of DCN1_Programming_Guide.docx */
617+ enum dcc_control dcc_control;
618+ unsigned int bpe;
619+ enum segment_order segment_order_horz, segment_order_vert;
620+ bool req128_horz_wc, req128_vert_wc;
621+
622+ memset(output, 0, sizeof(*output));
623+
624+ if (dc->debug.disable_dcc == DCC_DISABLE)
625+ return false;
626+
627+ if (!hubbub->funcs->dcc_support_pixel_format(input->format, &bpe))
628+ return false;
629+
630+ if (!hubbub->funcs->dcc_support_swizzle(input->swizzle_mode, bpe,
631+ &segment_order_horz, &segment_order_vert))
632+ return false;
633+
634+ hubbub1_det_request_size(input->surface_size.height, input->surface_size.width,
635+ bpe, &req128_horz_wc, &req128_vert_wc);
636+
637+ if (!req128_horz_wc && !req128_vert_wc) {
638+ dcc_control = dcc_control__256_256_xxx;
639+ } else if (input->scan == SCAN_DIRECTION_HORIZONTAL) {
640+ if (!req128_horz_wc)
641+ dcc_control = dcc_control__256_256_xxx;
642+ else if (segment_order_horz == segment_order__contiguous)
643+ dcc_control = dcc_control__128_128_xxx;
644+ else
645+ dcc_control = dcc_control__256_64_64;
646+ } else if (input->scan == SCAN_DIRECTION_VERTICAL) {
647+ if (!req128_vert_wc)
648+ dcc_control = dcc_control__256_256_xxx;
649+ else if (segment_order_vert == segment_order__contiguous)
650+ dcc_control = dcc_control__128_128_xxx;
651+ else
652+ dcc_control = dcc_control__256_64_64;
653+ } else {
654+ if ((req128_horz_wc &&
655+ segment_order_horz == segment_order__non_contiguous) ||
656+ (req128_vert_wc &&
657+ segment_order_vert == segment_order__non_contiguous))
658+ /* access_dir not known, must use most constraining */
659+ dcc_control = dcc_control__256_64_64;
660+ else
661+ /* reg128 is true for either horz and vert
662+ * but segment_order is contiguous
663+ */
664+ dcc_control = dcc_control__128_128_xxx;
665+ }
666+
667+ if (dc->debug.disable_dcc == DCC_HALF_REQ_DISALBE &&
668+ dcc_control != dcc_control__256_256_xxx)
669+ return false;
670+
671+ switch (dcc_control) {
672+ case dcc_control__256_256_xxx:
673+ output->grph.rgb.max_uncompressed_blk_size = 256;
674+ output->grph.rgb.max_compressed_blk_size = 256;
675+ output->grph.rgb.independent_64b_blks = false;
676+ break;
677+ case dcc_control__128_128_xxx:
678+ output->grph.rgb.max_uncompressed_blk_size = 128;
679+ output->grph.rgb.max_compressed_blk_size = 128;
680+ output->grph.rgb.independent_64b_blks = false;
681+ break;
682+ case dcc_control__256_64_64:
683+ output->grph.rgb.max_uncompressed_blk_size = 256;
684+ output->grph.rgb.max_compressed_blk_size = 64;
685+ output->grph.rgb.independent_64b_blks = true;
686+ break;
687+ }
688+
689+ output->capable = true;
690+ output->const_color_support = false;
691+
692+ return true;
693+}
694+
479695 static const struct hubbub_funcs hubbub1_funcs = {
480− .update_dchub = hubbub1_update_dchub
696+ .update_dchub = hubbub1_update_dchub,
697+ .dcc_support_swizzle = hubbub1_dcc_support_swizzle,
698+ .dcc_support_pixel_format = hubbub1_dcc_support_pixel_format,
699+ .get_dcc_compression_cap = hubbub1_get_dcc_compression_cap,
481700 };
482701
483702 void hubbub1_construct(struct hubbub *hubbub,
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.h+1−6
@@ -27,6 +27,7 @@ · 26 unmodified lines
2727 #define __DC_HUBBUB_DCN10_H__
2828
2929 #include "core_types.h"
30+#include "dchubbub.h"
3031
3132 #define HUBHUB_REG_LIST_DCN()\
3233 SR(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A),\
@@ -173,12 +174,6 @@ struct dcn_hubbub_wm { · 140 unmodified lines
173174 struct dcn_hubbub_wm_set sets[4];
174175 };
175176
176−struct hubbub_funcs {
177− void (*update_dchub)(
178− struct hubbub *hubbub,
179− struct dchub_init_data *dh_data);
180−};
181−
182177 struct hubbub {
183178 const struct hubbub_funcs *funcs;
184179 struct dc_context *ctx;
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c+176−11
@@ -146,6 +146,9 @@ void hubp1_program_size_and_rotation( · 145 unmodified lines
146146 * 444 or 420 luma
147147 */
148148 if (format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) {
149+ ASSERT(plane_size->video.chroma_pitch != 0);
150+ /* Chroma pitch zero can cause system hang! */
151+
149152 pitch = plane_size->video.luma_pitch - 1;
150153 meta_pitch = dcc->video.meta_pitch_l - 1;
151154 pitch_c = plane_size->video.chroma_pitch - 1;
@@ -535,11 +538,13 @@ void hubp1_program_deadline( · 383 unmodified lines
535538 REG_SET(VBLANK_PARAMETERS_3, 0,
536539 REFCYC_PER_META_CHUNK_VBLANK_L, dlg_attr->refcyc_per_meta_chunk_vblank_l);
537540
538− REG_SET(NOM_PARAMETERS_0, 0,
539− DST_Y_PER_PTE_ROW_NOM_L, dlg_attr->dst_y_per_pte_row_nom_l);
541+ if (REG(NOM_PARAMETERS_0))
542+ REG_SET(NOM_PARAMETERS_0, 0,
543+ DST_Y_PER_PTE_ROW_NOM_L, dlg_attr->dst_y_per_pte_row_nom_l);
540544
541− REG_SET(NOM_PARAMETERS_1, 0,
542− REFCYC_PER_PTE_GROUP_NOM_L, dlg_attr->refcyc_per_pte_group_nom_l);
545+ if (REG(NOM_PARAMETERS_1))
546+ REG_SET(NOM_PARAMETERS_1, 0,
547+ REFCYC_PER_PTE_GROUP_NOM_L, dlg_attr->refcyc_per_pte_group_nom_l);
543548
544549 REG_SET(NOM_PARAMETERS_4, 0,
545550 DST_Y_PER_META_ROW_NOM_L, dlg_attr->dst_y_per_meta_row_nom_l);
@@ -568,11 +573,13 @@ void hubp1_program_deadline( · 22 unmodified lines
568573 REG_SET(VBLANK_PARAMETERS_4, 0,
569574 REFCYC_PER_META_CHUNK_VBLANK_C, dlg_attr->refcyc_per_meta_chunk_vblank_c);
570575
571− REG_SET(NOM_PARAMETERS_2, 0,
572− DST_Y_PER_PTE_ROW_NOM_C, dlg_attr->dst_y_per_pte_row_nom_c);
576+ if (REG(NOM_PARAMETERS_2))
577+ REG_SET(NOM_PARAMETERS_2, 0,
578+ DST_Y_PER_PTE_ROW_NOM_C, dlg_attr->dst_y_per_pte_row_nom_c);
573579
574− REG_SET(NOM_PARAMETERS_3, 0,
575− REFCYC_PER_PTE_GROUP_NOM_C, dlg_attr->refcyc_per_pte_group_nom_c);
580+ if (REG(NOM_PARAMETERS_3))
581+ REG_SET(NOM_PARAMETERS_3, 0,
582+ REFCYC_PER_PTE_GROUP_NOM_C, dlg_attr->refcyc_per_pte_group_nom_c);
576583
577584 REG_SET(NOM_PARAMETERS_6, 0,
578585 DST_Y_PER_META_ROW_NOM_C, dlg_attr->dst_y_per_meta_row_nom_c);
@@ -609,6 +616,13 @@ void hubp1_program_deadline( · 30 unmodified lines
609616 REG_SET(DCN_SURF1_TTU_CNTL1, 0,
610617 REFCYC_PER_REQ_DELIVERY_PRE,
611618 ttu_attr->refcyc_per_req_delivery_pre_c);
619+
620+ REG_SET_3(DCN_CUR0_TTU_CNTL0, 0,
621+ REFCYC_PER_REQ_DELIVERY, ttu_attr->refcyc_per_req_delivery_cur0,
622+ QoS_LEVEL_FIXED, ttu_attr->qos_level_fixed_cur0,
623+ QoS_RAMP_DISABLE, ttu_attr->qos_ramp_disable_cur0);
624+ REG_SET(DCN_CUR0_TTU_CNTL1, 0,
625+ REFCYC_PER_REQ_DELIVERY_PRE, ttu_attr->refcyc_per_req_delivery_pre_cur0);
612626 }
613627
614628 static void hubp1_setup(
@@ -752,9 +766,159 @@ void min_set_viewport( · 137 unmodified lines
752766 PRI_VIEWPORT_Y_START_C, viewport_c->y);
753767 }
754768
755−void hubp1_read_state(struct dcn10_hubp *hubp1,
756− struct dcn_hubp_state *s)
769+void hubp1_read_state(struct hubp *hubp)
757770 {
771+ struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp);
772+ struct dcn_hubp_state *s = &hubp1->state;
773+ struct _vcs_dpi_display_dlg_regs_st *dlg_attr = &s->dlg_attr;
774+ struct _vcs_dpi_display_ttu_regs_st *ttu_attr = &s->ttu_attr;
775+ struct _vcs_dpi_display_rq_regs_st *rq_regs = &s->rq_regs;
776+
777+ /* Requester */
778+ REG_GET(HUBPRET_CONTROL,
779+ DET_BUF_PLANE1_BASE_ADDRESS, &rq_regs->plane1_base_address);
780+ REG_GET_4(DCN_EXPANSION_MODE,
781+ DRQ_EXPANSION_MODE, &rq_regs->drq_expansion_mode,
782+ PRQ_EXPANSION_MODE, &rq_regs->prq_expansion_mode,
783+ MRQ_EXPANSION_MODE, &rq_regs->mrq_expansion_mode,
784+ CRQ_EXPANSION_MODE, &rq_regs->crq_expansion_mode);
785+ REG_GET_8(DCHUBP_REQ_SIZE_CONFIG,
786+ CHUNK_SIZE, &rq_regs->rq_regs_l.chunk_size,
787+ MIN_CHUNK_SIZE, &rq_regs->rq_regs_l.min_chunk_size,
788+ META_CHUNK_SIZE, &rq_regs->rq_regs_l.meta_chunk_size,
789+ MIN_META_CHUNK_SIZE, &rq_regs->rq_regs_l.min_meta_chunk_size,
790+ DPTE_GROUP_SIZE, &rq_regs->rq_regs_l.dpte_group_size,
791+ MPTE_GROUP_SIZE, &rq_regs->rq_regs_l.mpte_group_size,
792+ SWATH_HEIGHT, &rq_regs->rq_regs_l.swath_height,
793+ PTE_ROW_HEIGHT_LINEAR, &rq_regs->rq_regs_l.pte_row_height_linear);
794+ REG_GET_8(DCHUBP_REQ_SIZE_CONFIG_C,
795+ CHUNK_SIZE_C, &rq_regs->rq_regs_c.chunk_size,
796+ MIN_CHUNK_SIZE_C, &rq_regs->rq_regs_c.min_chunk_size,
797+ META_CHUNK_SIZE_C, &rq_regs->rq_regs_c.meta_chunk_size,
798+ MIN_META_CHUNK_SIZE_C, &rq_regs->rq_regs_c.min_meta_chunk_size,
799+ DPTE_GROUP_SIZE_C, &rq_regs->rq_regs_c.dpte_group_size,
800+ MPTE_GROUP_SIZE_C, &rq_regs->rq_regs_c.mpte_group_size,
801+ SWATH_HEIGHT_C, &rq_regs->rq_regs_c.swath_height,
802+ PTE_ROW_HEIGHT_LINEAR_C, &rq_regs->rq_regs_c.pte_row_height_linear);
803+
804+ /* DLG - Per hubp */
805+ REG_GET_2(BLANK_OFFSET_0,
806+ REFCYC_H_BLANK_END, &dlg_attr->refcyc_h_blank_end,
807+ DLG_V_BLANK_END, &dlg_attr->dlg_vblank_end);
808+
809+ REG_GET(BLANK_OFFSET_1,
810+ MIN_DST_Y_NEXT_START, &dlg_attr->min_dst_y_next_start);
811+
812+ REG_GET(DST_DIMENSIONS,
813+ REFCYC_PER_HTOTAL, &dlg_attr->refcyc_per_htotal);
814+
815+ REG_GET_2(DST_AFTER_SCALER,
816+ REFCYC_X_AFTER_SCALER, &dlg_attr->refcyc_x_after_scaler,
817+ DST_Y_AFTER_SCALER, &dlg_attr->dst_y_after_scaler);
818+
819+ if (REG(PREFETCH_SETTINS))
820+ REG_GET_2(PREFETCH_SETTINS,
821+ DST_Y_PREFETCH, &dlg_attr->dst_y_prefetch,
822+ VRATIO_PREFETCH, &dlg_attr->vratio_prefetch);
823+ else
824+ REG_GET_2(PREFETCH_SETTINGS,
825+ DST_Y_PREFETCH, &dlg_attr->dst_y_prefetch,
826+ VRATIO_PREFETCH, &dlg_attr->vratio_prefetch);
827+
828+ REG_GET_2(VBLANK_PARAMETERS_0,
829+ DST_Y_PER_VM_VBLANK, &dlg_attr->dst_y_per_vm_vblank,
830+ DST_Y_PER_ROW_VBLANK, &dlg_attr->dst_y_per_row_vblank);
831+
832+ REG_GET(REF_FREQ_TO_PIX_FREQ,
833+ REF_FREQ_TO_PIX_FREQ, &dlg_attr->ref_freq_to_pix_freq);
834+
835+ /* DLG - Per luma/chroma */
836+ REG_GET(VBLANK_PARAMETERS_1,
837+ REFCYC_PER_PTE_GROUP_VBLANK_L, &dlg_attr->refcyc_per_pte_group_vblank_l);
838+
839+ REG_GET(VBLANK_PARAMETERS_3,
840+ REFCYC_PER_META_CHUNK_VBLANK_L, &dlg_attr->refcyc_per_meta_chunk_vblank_l);
841+
842+ if (REG(NOM_PARAMETERS_0))
843+ REG_GET(NOM_PARAMETERS_0,
844+ DST_Y_PER_PTE_ROW_NOM_L, &dlg_attr->dst_y_per_pte_row_nom_l);
845+
846+ if (REG(NOM_PARAMETERS_1))
847+ REG_GET(NOM_PARAMETERS_1,
848+ REFCYC_PER_PTE_GROUP_NOM_L, &dlg_attr->refcyc_per_pte_group_nom_l);
849+
850+ REG_GET(NOM_PARAMETERS_4,
851+ DST_Y_PER_META_ROW_NOM_L, &dlg_attr->dst_y_per_meta_row_nom_l);
852+
853+ REG_GET(NOM_PARAMETERS_5,
854+ REFCYC_PER_META_CHUNK_NOM_L, &dlg_attr->refcyc_per_meta_chunk_nom_l);
855+
856+ REG_GET_2(PER_LINE_DELIVERY_PRE,
857+ REFCYC_PER_LINE_DELIVERY_PRE_L, &dlg_attr->refcyc_per_line_delivery_pre_l,
858+ REFCYC_PER_LINE_DELIVERY_PRE_C, &dlg_attr->refcyc_per_line_delivery_pre_c);
859+
860+ REG_GET_2(PER_LINE_DELIVERY,
861+ REFCYC_PER_LINE_DELIVERY_L, &dlg_attr->refcyc_per_line_delivery_l,
862+ REFCYC_PER_LINE_DELIVERY_C, &dlg_attr->refcyc_per_line_delivery_c);
863+
864+ if (REG(PREFETCH_SETTINS_C))
865+ REG_GET(PREFETCH_SETTINS_C,
866+ VRATIO_PREFETCH_C, &dlg_attr->vratio_prefetch_c);
867+ else
868+ REG_GET(PREFETCH_SETTINGS_C,
869+ VRATIO_PREFETCH_C, &dlg_attr->vratio_prefetch_c);
870+
871+ REG_GET(VBLANK_PARAMETERS_2,
872+ REFCYC_PER_PTE_GROUP_VBLANK_C, &dlg_attr->refcyc_per_pte_group_vblank_c);
873+
874+ REG_GET(VBLANK_PARAMETERS_4,
875+ REFCYC_PER_META_CHUNK_VBLANK_C, &dlg_attr->refcyc_per_meta_chunk_vblank_c);
876+
877+ if (REG(NOM_PARAMETERS_2))
878+ REG_GET(NOM_PARAMETERS_2,
879+ DST_Y_PER_PTE_ROW_NOM_C, &dlg_attr->dst_y_per_pte_row_nom_c);
880+
881+ if (REG(NOM_PARAMETERS_3))
882+ REG_GET(NOM_PARAMETERS_3,
883+ REFCYC_PER_PTE_GROUP_NOM_C, &dlg_attr->refcyc_per_pte_group_nom_c);
884+
885+ REG_GET(NOM_PARAMETERS_6,
886+ DST_Y_PER_META_ROW_NOM_C, &dlg_attr->dst_y_per_meta_row_nom_c);
887+
888+ REG_GET(NOM_PARAMETERS_7,
889+ REFCYC_PER_META_CHUNK_NOM_C, &dlg_attr->refcyc_per_meta_chunk_nom_c);
890+
891+ /* TTU - per hubp */
892+ REG_GET_2(DCN_TTU_QOS_WM,
893+ QoS_LEVEL_LOW_WM, &ttu_attr->qos_level_low_wm,
894+ QoS_LEVEL_HIGH_WM, &ttu_attr->qos_level_high_wm);
895+
896+ REG_GET_2(DCN_GLOBAL_TTU_CNTL,
897+ MIN_TTU_VBLANK, &ttu_attr->min_ttu_vblank,
898+ QoS_LEVEL_FLIP, &ttu_attr->qos_level_flip);
899+
900+ /* TTU - per luma/chroma */
901+ /* Assumed surf0 is luma and 1 is chroma */
902+
903+ REG_GET_3(DCN_SURF0_TTU_CNTL0,
904+ REFCYC_PER_REQ_DELIVERY, &ttu_attr->refcyc_per_req_delivery_l,
905+ QoS_LEVEL_FIXED, &ttu_attr->qos_level_fixed_l,
906+ QoS_RAMP_DISABLE, &ttu_attr->qos_ramp_disable_l);
907+
908+ REG_GET(DCN_SURF0_TTU_CNTL1,
909+ REFCYC_PER_REQ_DELIVERY_PRE,
910+ &ttu_attr->refcyc_per_req_delivery_pre_l);
911+
912+ REG_GET_3(DCN_SURF1_TTU_CNTL0,
913+ REFCYC_PER_REQ_DELIVERY, &ttu_attr->refcyc_per_req_delivery_c,
914+ QoS_LEVEL_FIXED, &ttu_attr->qos_level_fixed_c,
915+ QoS_RAMP_DISABLE, &ttu_attr->qos_ramp_disable_c);
916+
917+ REG_GET(DCN_SURF1_TTU_CNTL1,
918+ REFCYC_PER_REQ_DELIVERY_PRE,
919+ &ttu_attr->refcyc_per_req_delivery_pre_c);
920+
921+ /* Rest of hubp */
758922 REG_GET(DCSURF_SURFACE_CONFIG,
759923 SURFACE_PIXEL_FORMAT, &s->pixel_format);
760924
@@ -897,7 +1061,7 @@ void hubp1_cursor_set_position( · 136 unmodified lines
8971061 if (src_x_offset >= (int)param->viewport_width)
8981062 cur_en = 0; /* not visible beyond right edge*/
8991063
900− if (src_x_offset + (int)hubp->curs_attr.width < 0)
1064+ if (src_x_offset + (int)hubp->curs_attr.width <= 0)
9011065 cur_en = 0; /* not visible beyond left edge*/
9021066
9031067 if (cur_en && REG_READ(CURSOR_SURFACE_ADDRESS) == 0)
@@ -952,6 +1116,7 @@ static struct hubp_funcs dcn10_hubp_funcs = { · 48 unmodified lines
9521116 .hubp_disconnect = hubp1_disconnect,
9531117 .hubp_clk_cntl = hubp1_clk_cntl,
9541118 .hubp_vtg_sel = hubp1_vtg_sel,
1119+ .hubp_read_state = hubp1_read_state,
9551120 };
9561121
9571122 /*****************************************/
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h+50−29
@@ -30,6 +30,7 @@ · 29 unmodified lines
3030 #define TO_DCN10_HUBP(hubp)\
3131 container_of(hubp, struct dcn10_hubp, base)
3232
33+/* Register address initialization macro for all ASICs (including those with reduced functionality) */
3334 #define HUBP_REG_LIST_DCN(id)\
3435 SRI(DCHUBP_CNTL, HUBP, id),\
3536 SRI(HUBPREQ_DEBUG_DB, HUBP, id),\
@@ -78,16 +79,12 @@ · 42 unmodified lines
7879 SRI(REF_FREQ_TO_PIX_FREQ, HUBPREQ, id),\
7980 SRI(VBLANK_PARAMETERS_1, HUBPREQ, id),\
8081 SRI(VBLANK_PARAMETERS_3, HUBPREQ, id),\
81− SRI(NOM_PARAMETERS_0, HUBPREQ, id),\
82− SRI(NOM_PARAMETERS_1, HUBPREQ, id),\
8382 SRI(NOM_PARAMETERS_4, HUBPREQ, id),\
8483 SRI(NOM_PARAMETERS_5, HUBPREQ, id),\
8584 SRI(PER_LINE_DELIVERY_PRE, HUBPREQ, id),\
8685 SRI(PER_LINE_DELIVERY, HUBPREQ, id),\
8786 SRI(VBLANK_PARAMETERS_2, HUBPREQ, id),\
8887 SRI(VBLANK_PARAMETERS_4, HUBPREQ, id),\
89− SRI(NOM_PARAMETERS_2, HUBPREQ, id),\
90− SRI(NOM_PARAMETERS_3, HUBPREQ, id),\
9188 SRI(NOM_PARAMETERS_6, HUBPREQ, id),\
9289 SRI(NOM_PARAMETERS_7, HUBPREQ, id),\
9390 SRI(DCN_TTU_QOS_WM, HUBPREQ, id),\
@@ -96,11 +93,21 @@ · 2 unmodified lines
9693 SRI(DCN_SURF0_TTU_CNTL1, HUBPREQ, id),\
9794 SRI(DCN_SURF1_TTU_CNTL0, HUBPREQ, id),\
9895 SRI(DCN_SURF1_TTU_CNTL1, HUBPREQ, id),\
99− SRI(DCN_VM_MX_L1_TLB_CNTL, HUBPREQ, id),\
96+ SRI(DCN_CUR0_TTU_CNTL0, HUBPREQ, id),\
97+ SRI(DCN_CUR0_TTU_CNTL1, HUBPREQ, id),\
10098 SRI(HUBP_CLK_CNTL, HUBP, id)
10199
100+/* Register address initialization macro for ASICs with VM */
101+#define HUBP_REG_LIST_DCN_VM(id)\
102+ SRI(NOM_PARAMETERS_0, HUBPREQ, id),\
103+ SRI(NOM_PARAMETERS_1, HUBPREQ, id),\
104+ SRI(NOM_PARAMETERS_2, HUBPREQ, id),\
105+ SRI(NOM_PARAMETERS_3, HUBPREQ, id),\
106+ SRI(DCN_VM_MX_L1_TLB_CNTL, HUBPREQ, id)
107+
102108 #define HUBP_REG_LIST_DCN10(id)\
103109 HUBP_REG_LIST_DCN(id),\
110+ HUBP_REG_LIST_DCN_VM(id),\
104111 SRI(PREFETCH_SETTINS, HUBPREQ, id),\
105112 SRI(PREFETCH_SETTINS_C, HUBPREQ, id),\
106113 SRI(DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB, HUBPREQ, id),\
@@ -198,6 +205,8 @@ · 91 unmodified lines
198205 uint32_t DCN_SURF0_TTU_CNTL1; \
199206 uint32_t DCN_SURF1_TTU_CNTL0; \
200207 uint32_t DCN_SURF1_TTU_CNTL1; \
208+ uint32_t DCN_CUR0_TTU_CNTL0; \
209+ uint32_t DCN_CUR0_TTU_CNTL1; \
201210 uint32_t DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB; \
202211 uint32_t DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LSB; \
203212 uint32_t DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB; \
@@ -237,6 +246,7 @@ · 33 unmodified lines
237246 #define HUBP_SF(reg_name, field_name, post_fix)\
238247 .field_name = reg_name ## __ ## field_name ## post_fix
239248
249+/* Mask/shift struct generation macro for all ASICs (including those with reduced functionality) */
240250 #define HUBP_MASK_SH_LIST_DCN(mask_sh)\
241251 HUBP_SF(HUBP0_DCHUBP_CNTL, HUBP_BLANK_EN, mask_sh),\
242252 HUBP_SF(HUBP0_DCHUBP_CNTL, HUBP_TTU_DISABLE, mask_sh),\
@@ -335,8 +345,6 @@ · 92 unmodified lines
335345 HUBP_SF(HUBPREQ0_REF_FREQ_TO_PIX_FREQ, REF_FREQ_TO_PIX_FREQ, mask_sh),\
336346 HUBP_SF(HUBPREQ0_VBLANK_PARAMETERS_1, REFCYC_PER_PTE_GROUP_VBLANK_L, mask_sh),\
337347 HUBP_SF(HUBPREQ0_VBLANK_PARAMETERS_3, REFCYC_PER_META_CHUNK_VBLANK_L, mask_sh),\
338− HUBP_SF(HUBPREQ0_NOM_PARAMETERS_0, DST_Y_PER_PTE_ROW_NOM_L, mask_sh),\
339− HUBP_SF(HUBPREQ0_NOM_PARAMETERS_1, REFCYC_PER_PTE_GROUP_NOM_L, mask_sh),\
340348 HUBP_SF(HUBPREQ0_NOM_PARAMETERS_4, DST_Y_PER_META_ROW_NOM_L, mask_sh),\
341349 HUBP_SF(HUBPREQ0_NOM_PARAMETERS_5, REFCYC_PER_META_CHUNK_NOM_L, mask_sh),\
342350 HUBP_SF(HUBPREQ0_PER_LINE_DELIVERY_PRE, REFCYC_PER_LINE_DELIVERY_PRE_L, mask_sh),\
@@ -345,8 +353,6 @@ · 2 unmodified lines
345353 HUBP_SF(HUBPREQ0_PER_LINE_DELIVERY, REFCYC_PER_LINE_DELIVERY_C, mask_sh),\
346354 HUBP_SF(HUBPREQ0_VBLANK_PARAMETERS_2, REFCYC_PER_PTE_GROUP_VBLANK_C, mask_sh),\
347355 HUBP_SF(HUBPREQ0_VBLANK_PARAMETERS_4, REFCYC_PER_META_CHUNK_VBLANK_C, mask_sh),\
348− HUBP_SF(HUBPREQ0_NOM_PARAMETERS_2, DST_Y_PER_PTE_ROW_NOM_C, mask_sh),\
349− HUBP_SF(HUBPREQ0_NOM_PARAMETERS_3, REFCYC_PER_PTE_GROUP_NOM_C, mask_sh),\
350356 HUBP_SF(HUBPREQ0_NOM_PARAMETERS_6, DST_Y_PER_META_ROW_NOM_C, mask_sh),\
351357 HUBP_SF(HUBPREQ0_NOM_PARAMETERS_7, REFCYC_PER_META_CHUNK_NOM_C, mask_sh),\
352358 HUBP_SF(HUBPREQ0_DCN_TTU_QOS_WM, QoS_LEVEL_LOW_WM, mask_sh),\
@@ -357,12 +363,24 @@ · 4 unmodified lines
357363 HUBP_SF(HUBPREQ0_DCN_SURF0_TTU_CNTL0, QoS_LEVEL_FIXED, mask_sh),\
358364 HUBP_SF(HUBPREQ0_DCN_SURF0_TTU_CNTL0, QoS_RAMP_DISABLE, mask_sh),\
359365 HUBP_SF(HUBPREQ0_DCN_SURF0_TTU_CNTL1, REFCYC_PER_REQ_DELIVERY_PRE, mask_sh),\
366+ HUBP_SF(HUBP0_HUBP_CLK_CNTL, HUBP_CLOCK_ENABLE, mask_sh)
367+
368+/* Mask/shift struct generation macro for ASICs with VM */
369+#define HUBP_MASK_SH_LIST_DCN_VM(mask_sh)\
370+ HUBP_SF(HUBPREQ0_NOM_PARAMETERS_0, DST_Y_PER_PTE_ROW_NOM_L, mask_sh),\
371+ HUBP_SF(HUBPREQ0_NOM_PARAMETERS_1, REFCYC_PER_PTE_GROUP_NOM_L, mask_sh),\
372+ HUBP_SF(HUBPREQ0_NOM_PARAMETERS_2, DST_Y_PER_PTE_ROW_NOM_C, mask_sh),\
373+ HUBP_SF(HUBPREQ0_NOM_PARAMETERS_3, REFCYC_PER_PTE_GROUP_NOM_C, mask_sh),\
360374 HUBP_SF(HUBPREQ0_DCN_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, mask_sh),\
361375 HUBP_SF(HUBPREQ0_DCN_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, mask_sh),\
362− HUBP_SF(HUBP0_HUBP_CLK_CNTL, HUBP_CLOCK_ENABLE, mask_sh)
376+ HUBP_SF(HUBPREQ0_DCN_CUR0_TTU_CNTL0, REFCYC_PER_REQ_DELIVERY, mask_sh),\
377+ HUBP_SF(HUBPREQ0_DCN_CUR0_TTU_CNTL0, QoS_LEVEL_FIXED, mask_sh),\
378+ HUBP_SF(HUBPREQ0_DCN_CUR0_TTU_CNTL0, QoS_RAMP_DISABLE, mask_sh),\
379+ HUBP_SF(HUBPREQ0_DCN_CUR0_TTU_CNTL1, REFCYC_PER_REQ_DELIVERY_PRE, mask_sh)
363380
364381 #define HUBP_MASK_SH_LIST_DCN10(mask_sh)\
365382 HUBP_MASK_SH_LIST_DCN(mask_sh),\
383+ HUBP_MASK_SH_LIST_DCN_VM(mask_sh),\
366384 HUBP_SF(HUBPREQ0_PREFETCH_SETTINS, DST_Y_PREFETCH, mask_sh),\
367385 HUBP_SF(HUBPREQ0_PREFETCH_SETTINS, VRATIO_PREFETCH, mask_sh),\
368386 HUBP_SF(HUBPREQ0_PREFETCH_SETTINS_C, VRATIO_PREFETCH_C, mask_sh),\
@@ -601,8 +619,29 @@ struct dcn_mi_mask { · 232 unmodified lines
601619 DCN_HUBP_REG_FIELD_LIST(uint32_t);
602620 };
603621
622+struct dcn_hubp_state {
623+ struct _vcs_dpi_display_dlg_regs_st dlg_attr;
624+ struct _vcs_dpi_display_ttu_regs_st ttu_attr;
625+ struct _vcs_dpi_display_rq_regs_st rq_regs;
626+ uint32_t pixel_format;
627+ uint32_t inuse_addr_hi;
628+ uint32_t viewport_width;
629+ uint32_t viewport_height;
630+ uint32_t rotation_angle;
631+ uint32_t h_mirror_en;
632+ uint32_t sw_mode;
633+ uint32_t dcc_en;
634+ uint32_t blank_en;
635+ uint32_t underflow_status;
636+ uint32_t ttu_disable;
637+ uint32_t min_ttu_vblank;
638+ uint32_t qos_level_low_wm;
639+ uint32_t qos_level_high_wm;
640+};
641+
604642 struct dcn10_hubp {
605643 struct hubp base;
644+ struct dcn_hubp_state state;
606645 const struct dcn_mi_registers *hubp_regs;
607646 const struct dcn_mi_shift *hubp_shift;
608647 const struct dcn_mi_mask *hubp_mask;
@@ -680,25 +719,7 @@ void dcn10_hubp_construct( · 71 unmodified lines
680719 const struct dcn_mi_shift *hubp_shift,
681720 const struct dcn_mi_mask *hubp_mask);
682721
683−
684−struct dcn_hubp_state {
685− uint32_t pixel_format;
686− uint32_t inuse_addr_hi;
687− uint32_t viewport_width;
688− uint32_t viewport_height;
689− uint32_t rotation_angle;
690− uint32_t h_mirror_en;
691− uint32_t sw_mode;
692− uint32_t dcc_en;
693− uint32_t blank_en;
694− uint32_t underflow_status;
695− uint32_t ttu_disable;
696− uint32_t min_ttu_vblank;
697− uint32_t qos_level_low_wm;
698− uint32_t qos_level_high_wm;
699−};
700−void hubp1_read_state(struct dcn10_hubp *hubp1,
701− struct dcn_hubp_state *s);
722+void hubp1_read_state(struct hubp *hubp);
702723
703724 enum cursor_pitch hubp1_get_cursor_pitch(unsigned int pitch);
704725
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c+221−67
@@ -45,8 +45,8 @@ · 44 unmodified lines
4545 #include "dcn10_hubbub.h"
4646 #include "dcn10_cm_common.h"
4747
48−#define DC_LOGGER \
49− ctx->logger
48+#define DC_LOGGER_INIT(logger)
49+
5050 #define CTX \
5151 hws->ctx
5252 #define REG(reg)\
@@ -56,16 +56,17 @@ · 3 unmodified lines
5656 #define FN(reg_name, field_name) \
5757 hws->shifts->field_name, hws->masks->field_name
5858
59+/*print is 17 wide, first two characters are spaces*/
5960 #define DTN_INFO_MICRO_SEC(ref_cycle) \
6061 print_microsec(dc_ctx, ref_cycle)
6162
6263 void print_microsec(struct dc_context *dc_ctx, uint32_t ref_cycle)
6364 {
64− static const uint32_t ref_clk_mhz = 48;
65− static const unsigned int frac = 10;
65+ const uint32_t ref_clk_mhz = dc_ctx->dc->res_pool->ref_clock_inKhz / 1000;
66+ static const unsigned int frac = 1000;
6667 uint32_t us_x10 = (ref_cycle * frac) / ref_clk_mhz;
6768
68− DTN_INFO("%d.%d \t ",
69+ DTN_INFO(" %11d.%03d",
6970 us_x10 / frac,
7071 us_x10 % frac);
7172 }
@@ -92,14 +93,14 @@ void dcn10_log_hubbub_state(struct dc *dc) · 20 unmodified lines
9293
9394 hubbub1_wm_read_state(dc->res_pool->hubbub, &wm);
9495
95− DTN_INFO("HUBBUB WM: \t data_urgent \t pte_meta_urgent \t "
96− "sr_enter \t sr_exit \t dram_clk_change \n");
96+ DTN_INFO("HUBBUB WM: data_urgent pte_meta_urgent"
97+ " sr_enter sr_exit dram_clk_change\n");
9798
9899 for (i = 0; i < 4; i++) {
99100 struct dcn_hubbub_wm_set *s;
100101
101102 s = &wm.sets[i];
102− DTN_INFO("WM_Set[%d]:\t ", s->wm_set);
103+ DTN_INFO("WM_Set[%d]:", s->wm_set);
103104 DTN_INFO_MICRO_SEC(s->data_urgent);
104105 DTN_INFO_MICRO_SEC(s->pte_meta_urgent);
105106 DTN_INFO_MICRO_SEC(s->sr_enter);
@@ -111,6 +112,116 @@ void dcn10_log_hubbub_state(struct dc *dc) · 5 unmodified lines
111112 DTN_INFO("\n");
112113 }
113114
115+static void dcn10_log_hubp_states(struct dc *dc)
116+{
117+ struct dc_context *dc_ctx = dc->ctx;
118+ struct resource_pool *pool = dc->res_pool;
119+ int i;
120+
121+ DTN_INFO("HUBP: format addr_hi width height"
122+ " rot mir sw_mode dcc_en blank_en ttu_dis underflow"
123+ " min_ttu_vblank qos_low_wm qos_high_wm\n");
124+ for (i = 0; i < pool->pipe_count; i++) {
125+ struct hubp *hubp = pool->hubps[i];
126+ struct dcn_hubp_state *s = &(TO_DCN10_HUBP(hubp)->state);
127+
128+ hubp->funcs->hubp_read_state(hubp);
129+
130+ DTN_INFO("[%2d]: %5xh %6xh %5d %6d %2xh %2xh %6xh"
131+ " %6d %8d %7d %8xh",
132+ hubp->inst,
133+ s->pixel_format,
134+ s->inuse_addr_hi,
135+ s->viewport_width,
136+ s->viewport_height,
137+ s->rotation_angle,
138+ s->h_mirror_en,
139+ s->sw_mode,
140+ s->dcc_en,
141+ s->blank_en,
142+ s->ttu_disable,
143+ s->underflow_status);
144+ DTN_INFO_MICRO_SEC(s->min_ttu_vblank);
145+ DTN_INFO_MICRO_SEC(s->qos_level_low_wm);
146+ DTN_INFO_MICRO_SEC(s->qos_level_high_wm);
147+ DTN_INFO("\n");
148+ }
149+
150+ DTN_INFO("\n=========RQ========\n");
151+ DTN_INFO("HUBP: drq_exp_m prq_exp_m mrq_exp_m crq_exp_m plane1_ba L:chunk_s min_chu_s meta_ch_s"
152+ " min_m_c_s dpte_gr_s mpte_gr_s swath_hei pte_row_h C:chunk_s min_chu_s meta_ch_s"
153+ " min_m_c_s dpte_gr_s mpte_gr_s swath_hei pte_row_h\n");
154+ for (i = 0; i < pool->pipe_count; i++) {
155+ struct dcn_hubp_state *s = &(TO_DCN10_HUBP(pool->hubps[i])->state);
156+ struct _vcs_dpi_display_rq_regs_st *rq_regs = &s->rq_regs;
157+
158+ DTN_INFO("[%2d]: %8xh %8xh %8xh %8xh %8xh %8xh %8xh %8xh %8xh %8xh %8xh %8xh %8xh %8xh %8xh %8xh %8xh %8xh %8xh %8xh %8xh\n",
159+ i, rq_regs->drq_expansion_mode, rq_regs->prq_expansion_mode, rq_regs->mrq_expansion_mode,
160+ rq_regs->crq_expansion_mode, rq_regs->plane1_base_address, rq_regs->rq_regs_l.chunk_size,
161+ rq_regs->rq_regs_l.min_chunk_size, rq_regs->rq_regs_l.meta_chunk_size,
162+ rq_regs->rq_regs_l.min_meta_chunk_size, rq_regs->rq_regs_l.dpte_group_size,
163+ rq_regs->rq_regs_l.mpte_group_size, rq_regs->rq_regs_l.swath_height,
164+ rq_regs->rq_regs_l.pte_row_height_linear, rq_regs->rq_regs_c.chunk_size, rq_regs->rq_regs_c.min_chunk_size,
165+ rq_regs->rq_regs_c.meta_chunk_size, rq_regs->rq_regs_c.min_meta_chunk_size,
166+ rq_regs->rq_regs_c.dpte_group_size, rq_regs->rq_regs_c.mpte_group_size,
167+ rq_regs->rq_regs_c.swath_height, rq_regs->rq_regs_c.pte_row_height_linear);
168+ }
169+
170+ DTN_INFO("========DLG========\n");
171+ DTN_INFO("HUBP: rc_hbe dlg_vbe min_d_y_n rc_per_ht rc_x_a_s "
172+ " dst_y_a_s dst_y_pf dst_y_vvb dst_y_rvb dst_y_vfl dst_y_rfl rf_pix_fq"
173+ " vratio_pf vrat_pf_c rc_pg_vbl rc_pg_vbc rc_mc_vbl rc_mc_vbc rc_pg_fll"
174+ " rc_pg_flc rc_mc_fll rc_mc_flc pr_nom_l pr_nom_c rc_pg_nl rc_pg_nc "
175+ " mr_nom_l mr_nom_c rc_mc_nl rc_mc_nc rc_ld_pl rc_ld_pc rc_ld_l "
176+ " rc_ld_c cha_cur0 ofst_cur1 cha_cur1 vr_af_vc0 ddrq_limt x_rt_dlay"
177+ " x_rp_dlay x_rr_sfl\n");
178+ for (i = 0; i < pool->pipe_count; i++) {
179+ struct dcn_hubp_state *s = &(TO_DCN10_HUBP(pool->hubps[i])->state);
180+ struct _vcs_dpi_display_dlg_regs_st *dlg_regs = &s->dlg_attr;
181+
182+ DTN_INFO("[%2d]: %8xh %8xh %8xh %8xh %8xh %8xh %8xh %8xh %8xh %8xh %8xh %8xh %8xh"
183+ "% 8xh %8xh %8xh %8xh %8xh %8xh %8xh %8xh %8xh %8xh %8xh %8xh %8xh %8xh"
184+ " %8xh %8xh %8xh %8xh %8xh %8xh %8xh %8xh %8xh %8xh %8xh %8xh %8xh %8xh %8xh\n",
185+ i, dlg_regs->refcyc_h_blank_end, dlg_regs->dlg_vblank_end, dlg_regs->min_dst_y_next_start,
186+ dlg_regs->refcyc_per_htotal, dlg_regs->refcyc_x_after_scaler, dlg_regs->dst_y_after_scaler,
187+ dlg_regs->dst_y_prefetch, dlg_regs->dst_y_per_vm_vblank, dlg_regs->dst_y_per_row_vblank,
188+ dlg_regs->dst_y_per_vm_flip, dlg_regs->dst_y_per_row_flip, dlg_regs->ref_freq_to_pix_freq,
189+ dlg_regs->vratio_prefetch, dlg_regs->vratio_prefetch_c, dlg_regs->refcyc_per_pte_group_vblank_l,
190+ dlg_regs->refcyc_per_pte_group_vblank_c, dlg_regs->refcyc_per_meta_chunk_vblank_l,
191+ dlg_regs->refcyc_per_meta_chunk_vblank_c, dlg_regs->refcyc_per_pte_group_flip_l,
192+ dlg_regs->refcyc_per_pte_group_flip_c, dlg_regs->refcyc_per_meta_chunk_flip_l,
193+ dlg_regs->refcyc_per_meta_chunk_flip_c, dlg_regs->dst_y_per_pte_row_nom_l,
194+ dlg_regs->dst_y_per_pte_row_nom_c, dlg_regs->refcyc_per_pte_group_nom_l,
195+ dlg_regs->refcyc_per_pte_group_nom_c, dlg_regs->dst_y_per_meta_row_nom_l,
196+ dlg_regs->dst_y_per_meta_row_nom_c, dlg_regs->refcyc_per_meta_chunk_nom_l,
197+ dlg_regs->refcyc_per_meta_chunk_nom_c, dlg_regs->refcyc_per_line_delivery_pre_l,
198+ dlg_regs->refcyc_per_line_delivery_pre_c, dlg_regs->refcyc_per_line_delivery_l,
199+ dlg_regs->refcyc_per_line_delivery_c, dlg_regs->chunk_hdl_adjust_cur0, dlg_regs->dst_y_offset_cur1,
200+ dlg_regs->chunk_hdl_adjust_cur1, dlg_regs->vready_after_vcount0, dlg_regs->dst_y_delta_drq_limit,
201+ dlg_regs->xfc_reg_transfer_delay, dlg_regs->xfc_reg_precharge_delay,
202+ dlg_regs->xfc_reg_remote_surface_flip_latency);
203+ }
204+
205+ DTN_INFO("========TTU========\n");
206+ DTN_INFO("HUBP: qos_ll_wm qos_lh_wm mn_ttu_vb qos_l_flp rc_rd_p_l rc_rd_l rc_rd_p_c"
207+ " rc_rd_c rc_rd_c0 rc_rd_pc0 rc_rd_c1 rc_rd_pc1 qos_lf_l qos_rds_l"
208+ " qos_lf_c qos_rds_c qos_lf_c0 qos_rds_c0 qos_lf_c1 qos_rds_c1\n");
209+ for (i = 0; i < pool->pipe_count; i++) {
210+ struct dcn_hubp_state *s = &(TO_DCN10_HUBP(pool->hubps[i])->state);
211+ struct _vcs_dpi_display_ttu_regs_st *ttu_regs = &s->ttu_attr;
212+
213+ DTN_INFO("[%2d]: %8xh %8xh %8xh %8xh %8xh %8xh %8xh %8xh %8xh %8xh %8xh %8xh %8xh %8xh %8xh %8xh %8xh %8xh %8xh %8xh\n",
214+ i, ttu_regs->qos_level_low_wm, ttu_regs->qos_level_high_wm, ttu_regs->min_ttu_vblank,
215+ ttu_regs->qos_level_flip, ttu_regs->refcyc_per_req_delivery_pre_l, ttu_regs->refcyc_per_req_delivery_l,
216+ ttu_regs->refcyc_per_req_delivery_pre_c, ttu_regs->refcyc_per_req_delivery_c, ttu_regs->refcyc_per_req_delivery_cur0,
217+ ttu_regs->refcyc_per_req_delivery_pre_cur0, ttu_regs->refcyc_per_req_delivery_cur1,
218+ ttu_regs->refcyc_per_req_delivery_pre_cur1, ttu_regs->qos_level_fixed_l, ttu_regs->qos_ramp_disable_l,
219+ ttu_regs->qos_level_fixed_c, ttu_regs->qos_ramp_disable_c, ttu_regs->qos_level_fixed_cur0,
220+ ttu_regs->qos_ramp_disable_cur0, ttu_regs->qos_level_fixed_cur1, ttu_regs->qos_ramp_disable_cur1);
221+ }
222+ DTN_INFO("\n");
223+}
224+
114225 void dcn10_log_hw_state(struct dc *dc)
115226 {
116227 struct dc_context *dc_ctx = dc->ctx;
@@ -121,41 +232,64 @@ void dcn10_log_hw_state(struct dc *dc) · 4 unmodified lines
121232
122233 dcn10_log_hubbub_state(dc);
123234
124− DTN_INFO("HUBP:\t format \t addr_hi \t width \t height \t "
125− "rotation \t mirror \t sw_mode \t "
126− "dcc_en \t blank_en \t ttu_dis \t underflow \t "
127− "min_ttu_vblank \t qos_low_wm \t qos_high_wm \n");
235+ dcn10_log_hubp_states(dc);
128236
237+ DTN_INFO("DPP: IGAM format IGAM mode DGAM mode RGAM mode"
238+ " GAMUT mode C11 C12 C13 C14 C21 C22 C23 C24 "
239+ "C31 C32 C33 C34\n");
129240 for (i = 0; i < pool->pipe_count; i++) {
130− struct hubp *hubp = pool->hubps[i];
131− struct dcn_hubp_state s;
241+ struct dpp *dpp = pool->dpps[i];
242+ struct dcn_dpp_state s;
243+
244+ dpp->funcs->dpp_read_state(dpp, &s);
245+
246+ DTN_INFO("[%2d]: %11xh %-11s %-11s %-11s"
247+ "%8x %08xh %08xh %08xh %08xh %08xh %08xh",
248+ dpp->inst,
249+ s.igam_input_format,
250+ (s.igam_lut_mode == 0) ? "BypassFixed" :
251+ ((s.igam_lut_mode == 1) ? "BypassFloat" :
252+ ((s.igam_lut_mode == 2) ? "RAM" :
253+ ((s.igam_lut_mode == 3) ? "RAM" :
254+ "Unknown"))),
255+ (s.dgam_lut_mode == 0) ? "Bypass" :
256+ ((s.dgam_lut_mode == 1) ? "sRGB" :
257+ ((s.dgam_lut_mode == 2) ? "Ycc" :
258+ ((s.dgam_lut_mode == 3) ? "RAM" :
259+ ((s.dgam_lut_mode == 4) ? "RAM" :
260+ "Unknown")))),
261+ (s.rgam_lut_mode == 0) ? "Bypass" :
262+ ((s.rgam_lut_mode == 1) ? "sRGB" :
263+ ((s.rgam_lut_mode == 2) ? "Ycc" :
264+ ((s.rgam_lut_mode == 3) ? "RAM" :
265+ ((s.rgam_lut_mode == 4) ? "RAM" :
266+ "Unknown")))),
267+ s.gamut_remap_mode,
268+ s.gamut_remap_c11_c12,
269+ s.gamut_remap_c13_c14,
270+ s.gamut_remap_c21_c22,
271+ s.gamut_remap_c23_c24,
272+ s.gamut_remap_c31_c32,
273+ s.gamut_remap_c33_c34);
274+ DTN_INFO("\n");
275+ }
276+ DTN_INFO("\n");
132277
133− hubp1_read_state(TO_DCN10_HUBP(hubp), &s);
278+ DTN_INFO("MPCC: OPP DPP MPCCBOT MODE ALPHA_MODE PREMULT OVERLAP_ONLY IDLE\n");
279+ for (i = 0; i < pool->pipe_count; i++) {
280+ struct mpcc_state s = {0};
134281
135− DTN_INFO("[%d]:\t %xh \t %xh \t %d \t %d \t "
136− "%xh \t %xh \t %xh \t "
137− "%d \t %d \t %d \t %xh \t",
138− hubp->inst,
139− s.pixel_format,
140− s.inuse_addr_hi,
141− s.viewport_width,
142− s.viewport_height,
143− s.rotation_angle,
144− s.h_mirror_en,
145− s.sw_mode,
146− s.dcc_en,
147− s.blank_en,
148− s.ttu_disable,
149− s.underflow_status);
150− DTN_INFO_MICRO_SEC(s.min_ttu_vblank);
151− DTN_INFO_MICRO_SEC(s.qos_level_low_wm);
152− DTN_INFO_MICRO_SEC(s.qos_level_high_wm);
153− DTN_INFO("\n");
282+ pool->mpc->funcs->read_mpcc_state(pool->mpc, i, &s);
283+ if (s.opp_id != 0xf)
284+ DTN_INFO("[%2d]: %2xh %2xh %6xh %4d %10d %7d %12d %4d\n",
285+ i, s.opp_id, s.dpp_id, s.bot_mpcc_id,
286+ s.mode, s.alpha_mode, s.pre_multiplied_alpha, s.overlap_only,
287+ s.idle);
154288 }
155289 DTN_INFO("\n");
156290
157− DTN_INFO("OTG:\t v_bs \t v_be \t v_ss \t v_se \t vpol \t vmax \t vmin \t "
158− "h_bs \t h_be \t h_ss \t h_se \t hpol \t htot \t vtot \t underflow\n");
291+ DTN_INFO("OTG: v_bs v_be v_ss v_se vpol vmax vmin vmax_sel vmin_sel"
292+ " h_bs h_be h_ss h_se hpol htot vtot underflow\n");
159293
160294 for (i = 0; i < pool->timing_generator_count; i++) {
161295 struct timing_generator *tg = pool->timing_generators[i];
@@ -167,9 +301,8 @@ void dcn10_log_hw_state(struct dc *dc) · 5 unmodified lines
167301 if ((s.otg_enabled & 1) == 0)
168302 continue;
169303
170− DTN_INFO("[%d]:\t %d \t %d \t %d \t %d \t "
171− "%d \t %d \t %d \t %d \t %d \t %d \t "
172− "%d \t %d \t %d \t %d \t %d \t ",
304+ DTN_INFO("[%d]: %5d %5d %5d %5d %5d %5d %5d %9d %9d %5d %5d %5d"
305+ " %5d %5d %5d %5d %9d\n",
173306 tg->inst,
174307 s.v_blank_start,
175308 s.v_blank_end,
@@ -178,6 +311,8 @@ void dcn10_log_hw_state(struct dc *dc) · 2 unmodified lines
178311 s.v_sync_a_pol,
179312 s.v_total_max,
180313 s.v_total_min,
314+ s.v_total_max_sel,
315+ s.v_total_min_sel,
181316 s.h_blank_start,
182317 s.h_blank_end,
183318 s.h_sync_a_start,
@@ -186,10 +321,19 @@ void dcn10_log_hw_state(struct dc *dc) · 2 unmodified lines
186321 s.h_total,
187322 s.v_total,
188323 s.underflow_occurred_status);
189− DTN_INFO("\n");
190324 }
191325 DTN_INFO("\n");
192326
327+ DTN_INFO("\nCALCULATED Clocks: dcfclk_khz:%d dcfclk_deep_sleep_khz:%d dispclk_khz:%d\n"
328+ "dppclk_khz:%d max_supported_dppclk_khz:%d fclk_khz:%d socclk_khz:%d\n\n",
329+ dc->current_state->bw.dcn.calc_clk.dcfclk_khz,
330+ dc->current_state->bw.dcn.calc_clk.dcfclk_deep_sleep_khz,
331+ dc->current_state->bw.dcn.calc_clk.dispclk_khz,
332+ dc->current_state->bw.dcn.calc_clk.dppclk_khz,
333+ dc->current_state->bw.dcn.calc_clk.max_supported_dppclk_khz,
334+ dc->current_state->bw.dcn.calc_clk.fclk_khz,
335+ dc->current_state->bw.dcn.calc_clk.socclk_khz);
336+
193337 log_mpc_crc(dc);
194338
195339 DTN_INFO_END();
@@ -354,7 +498,7 @@ static void power_on_plane( · 158 unmodified lines
354498 struct dce_hwseq *hws,
355499 int plane_id)
356500 {
357− struct dc_context *ctx = hws->ctx;
501+ DC_LOGGER_INIT(hws->ctx->logger);
358502 if (REG(DC_IP_REQUEST_CNTL)) {
359503 REG_SET(DC_IP_REQUEST_CNTL, 0,
360504 IP_REQUEST_EN, 1);
@@ -461,7 +605,7 @@ static void false_optc_underflow_wa( · 100 unmodified lines
461605 tg->funcs->clear_optc_underflow(tg);
462606 }
463607
464−static enum dc_status dcn10_prog_pixclk_crtc_otg(
608+static enum dc_status dcn10_enable_stream_timing(
465609 struct pipe_ctx *pipe_ctx,
466610 struct dc_state *context,
467611 struct dc *dc)
@@ -553,7 +697,7 @@ static void reset_back_end_for_pipe( · 85 unmodified lines
553697 struct dc_state *context)
554698 {
555699 int i;
556− struct dc_context *ctx = dc->ctx;
700+ DC_LOGGER_INIT(dc->ctx->logger);
557701 if (pipe_ctx->stream_res.stream_enc == NULL) {
558702 pipe_ctx->stream = NULL;
559703 return;
@@ -649,7 +793,7 @@ static void plane_atomic_power_down(struct dc *dc, struct pipe_ctx *pipe_ctx) · 89 unmodified lines
649793 {
650794 struct dce_hwseq *hws = dc->hwseq;
651795 struct dpp *dpp = pipe_ctx->plane_res.dpp;
652− struct dc_context *ctx = dc->ctx;
796+ DC_LOGGER_INIT(dc->ctx->logger);
653797
654798 if (REG(DC_IP_REQUEST_CNTL)) {
655799 REG_SET(DC_IP_REQUEST_CNTL, 0,
@@ -699,7 +843,7 @@ static void plane_atomic_disable(struct dc *dc, struct pipe_ctx *pipe_ctx) · 43 unmodified lines
699843
700844 static void dcn10_disable_plane(struct dc *dc, struct pipe_ctx *pipe_ctx)
701845 {
702− struct dc_context *ctx = dc->ctx;
846+ DC_LOGGER_INIT(dc->ctx->logger);
703847
704848 if (!pipe_ctx->plane_res.hubp || pipe_ctx->plane_res.hubp->power_gated)
705849 return;
@@ -945,9 +1089,8 @@ static bool dcn10_set_input_transfer_func(struct pipe_ctx *pipe_ctx, · 239 unmodified lines
9451089 tf = plane_state->in_transfer_func;
9461090
9471091 if (plane_state->gamma_correction &&
948− plane_state->gamma_correction->is_identity)
949− dpp_base->funcs->dpp_set_degamma(dpp_base, IPP_DEGAMMA_MODE_BYPASS);
950− else if (plane_state->gamma_correction && dce_use_lut(plane_state->format))
1092+ !plane_state->gamma_correction->is_identity
1093+ && dce_use_lut(plane_state->format))
9511094 dpp_base->funcs->dpp_program_input_lut(dpp_base, plane_state->gamma_correction);
9521095
9531096 if (tf == NULL)
@@ -1433,7 +1576,7 @@ static void program_csc_matrix(struct pipe_ctx *pipe_ctx, · 479 unmodified lines
14331576 }
14341577 }
14351578
1436−static void program_output_csc(struct dc *dc,
1579+static void dcn10_program_output_csc(struct dc *dc,
14371580 struct pipe_ctx *pipe_ctx,
14381581 enum dc_color_space colorspace,
14391582 uint16_t *matrix,
@@ -1623,6 +1766,8 @@ static void update_mpcc(struct dc *dc, struct pipe_ctx *pipe_ctx) · 183 unmodified lines
16231766 struct mpc *mpc = dc->res_pool->mpc;
16241767 struct mpc_tree *mpc_tree_params = &(pipe_ctx->stream_res.opp->mpc_tree_params);
16251768
1769+
1770+
16261771 /* TODO: proper fix once fpga works */
16271772
16281773 if (dc->debug.surface_visual_confirm)
@@ -1649,6 +1794,7 @@ static void update_mpcc(struct dc *dc, struct pipe_ctx *pipe_ctx) · 20 unmodified lines
16491794 pipe_ctx->stream->output_color_space)
16501795 && per_pixel_alpha;
16511796
1797+
16521798 /*
16531799 * TODO: remove hack
16541800 * Note: currently there is a bug in init_hw such that
@@ -1659,6 +1805,12 @@ static void update_mpcc(struct dc *dc, struct pipe_ctx *pipe_ctx) · 4 unmodified lines
16591805 */
16601806 mpcc_id = hubp->inst;
16611807
1808+ /* If there is no full update, don't need to touch MPC tree*/
1809+ if (!pipe_ctx->plane_state->update_flags.bits.full_update) {
1810+ mpc->funcs->update_blending(mpc, &blnd_cfg, mpcc_id);
1811+ return;
1812+ }
1813+
16621814 /* check if this MPCC is already being used */
16631815 new_mpcc = mpc->funcs->get_mpcc_for_dpp(mpc_tree_params, mpcc_id);
16641816 /* remove MPCC if being used */
@@ -1777,7 +1929,7 @@ static void update_dchubp_dpp( · 112 unmodified lines
17771929 /*gamut remap*/
17781930 program_gamut_remap(pipe_ctx);
17791931
1780− program_output_csc(dc,
1932+ dc->hwss.program_output_csc(dc,
17811933 pipe_ctx,
17821934 pipe_ctx->stream->output_color_space,
17831935 pipe_ctx->stream->csc_color_matrix.matrix,
@@ -1810,9 +1962,9 @@ static void update_dchubp_dpp( · 26 unmodified lines
18101962 hubp->funcs->set_blank(hubp, false);
18111963 }
18121964
1813−static void dcn10_otg_blank(
1965+static void dcn10_blank_pixel_data(
18141966 struct dc *dc,
1815− struct stream_resource stream_res,
1967+ struct stream_resource *stream_res,
18161968 struct dc_stream_state *stream,
18171969 bool blank)
18181970 {
@@ -1823,21 +1975,21 @@ static void dcn10_otg_blank( · 4 unmodified lines
18231975 color_space = stream->output_color_space;
18241976 color_space_to_black_color(dc, color_space, &black_color);
18251977
1826− if (stream_res.tg->funcs->set_blank_color)
1827− stream_res.tg->funcs->set_blank_color(
1828− stream_res.tg,
1978+ if (stream_res->tg->funcs->set_blank_color)
1979+ stream_res->tg->funcs->set_blank_color(
1980+ stream_res->tg,
18291981 &black_color);
18301982
18311983 if (!blank) {
1832− if (stream_res.tg->funcs->set_blank)
1833− stream_res.tg->funcs->set_blank(stream_res.tg, blank);
1834− if (stream_res.abm)
1835− stream_res.abm->funcs->set_abm_level(stream_res.abm, stream->abm_level);
1984+ if (stream_res->tg->funcs->set_blank)
1985+ stream_res->tg->funcs->set_blank(stream_res->tg, blank);
1986+ if (stream_res->abm)
1987+ stream_res->abm->funcs->set_abm_level(stream_res->abm, stream->abm_level);
18361988 } else if (blank) {
1837− if (stream_res.abm)
1838− stream_res.abm->funcs->set_abm_immediate_disable(stream_res.abm);
1839− if (stream_res.tg->funcs->set_blank)
1840− stream_res.tg->funcs->set_blank(stream_res.tg, blank);
1989+ if (stream_res->abm)
1990+ stream_res->abm->funcs->set_abm_immediate_disable(stream_res->abm);
1991+ if (stream_res->tg->funcs->set_blank)
1992+ stream_res->tg->funcs->set_blank(stream_res->tg, blank);
18411993 }
18421994 }
18431995
@@ -1876,7 +2028,7 @@ static void program_all_pipe_in_tree( · 32 unmodified lines
18762028 pipe_ctx->stream_res.tg->funcs->program_global_sync(
18772029 pipe_ctx->stream_res.tg);
18782030
1879− dcn10_otg_blank(dc, pipe_ctx->stream_res,
2031+ dc->hwss.blank_pixel_data(dc, &pipe_ctx->stream_res,
18802032 pipe_ctx->stream, blank);
18812033 }
18822034
@@ -1983,9 +2135,9 @@ static void dcn10_apply_ctx_for_surface( · 100 unmodified lines
19832135 bool removed_pipe[4] = { false };
19842136 unsigned int ref_clk_mhz = dc->res_pool->ref_clock_inKhz/1000;
19852137 bool program_water_mark = false;
1986− struct dc_context *ctx = dc->ctx;
19872138 struct pipe_ctx *top_pipe_to_program =
19882139 find_top_pipe_for_stream(dc, context, stream);
2140+ DC_LOGGER_INIT(dc->ctx->logger);
19892141
19902142 if (!top_pipe_to_program)
19912143 return;
@@ -1996,7 +2148,7 @@ static void dcn10_apply_ctx_for_surface( · 4 unmodified lines
19962148
19972149 if (num_planes == 0) {
19982150 /* OTG blank before remove all front end */
1999− dcn10_otg_blank(dc, top_pipe_to_program->stream_res, top_pipe_to_program->stream, true);
2151+ dc->hwss.blank_pixel_data(dc, &top_pipe_to_program->stream_res, top_pipe_to_program->stream, true);
20002152 }
20012153
20022154 /* Disconnect unused mpcc */
@@ -2527,6 +2679,7 @@ static const struct hw_sequencer_funcs dcn10_funcs = { · 524 unmodified lines
25272679 .update_pending_status = dcn10_update_pending_status,
25282680 .set_input_transfer_func = dcn10_set_input_transfer_func,
25292681 .set_output_transfer_func = dcn10_set_output_transfer_func,
2682+ .program_output_csc = dcn10_program_output_csc,
25302683 .power_down = dce110_power_down,
25312684 .enable_accelerated_mode = dce110_enable_accelerated_mode,
25322685 .enable_timing_synchronization = dcn10_enable_timing_synchronization,
@@ -2538,10 +2691,11 @@ static const struct hw_sequencer_funcs dcn10_funcs = { · 5 unmodified lines
25382691 .blank_stream = dce110_blank_stream,
25392692 .enable_display_power_gating = dcn10_dummy_display_power_gating,
25402693 .disable_plane = dcn10_disable_plane,
2694+ .blank_pixel_data = dcn10_blank_pixel_data,
25412695 .pipe_control_lock = dcn10_pipe_control_lock,
25422696 .set_bandwidth = dcn10_set_bandwidth,
25432697 .reset_hw_ctx_wrap = reset_hw_ctx_wrap,
2544− .prog_pixclk_crtc_otg = dcn10_prog_pixclk_crtc_otg,
2698+ .enable_stream_timing = dcn10_enable_stream_timing,
25452699 .set_drr = set_drr,
25462700 .get_position = get_position,
25472701 .set_static_screen_control = set_static_screen_control,
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c+22−2
@@ -65,6 +65,7 @@ static void mpc1_update_blending( · 64 unmodified lines
6565 int mpcc_id)
6666 {
6767 struct dcn10_mpc *mpc10 = TO_DCN10_MPC(mpc);
68+ struct mpcc *mpcc = mpc1_get_mpcc(mpc, mpcc_id);
6869
6970 REG_UPDATE_5(MPCC_CONTROL[mpcc_id],
7071 MPCC_ALPHA_BLND_MODE, blnd_cfg->alpha_mode,
@@ -74,6 +75,7 @@ static void mpc1_update_blending( · 3 unmodified lines
7475 MPCC_GLOBAL_GAIN, blnd_cfg->global_gain);
7576
7677 mpc1_set_bg_color(mpc, &blnd_cfg->black_color, mpcc_id);
78+ mpcc->blnd_cfg = *blnd_cfg;
7779 }
7880
7981 void mpc1_update_stereo_mix(
@@ -235,8 +237,7 @@ struct mpcc *mpc1_insert_plane( · 155 unmodified lines
235237 }
236238
237239 /* update the blending configuration */
238− new_mpcc->blnd_cfg = *blnd_cfg;
239− mpc->funcs->update_blending(mpc, &new_mpcc->blnd_cfg, mpcc_id);
240+ mpc->funcs->update_blending(mpc, blnd_cfg, mpcc_id);
240241
241242 /* update the stereo mix settings, if provided */
242243 if (sm_cfg != NULL) {
@@ -409,7 +410,26 @@ void mpc1_init_mpcc_list_from_hw( · 166 unmodified lines
409410 }
410411 }
411412
413+void mpc1_read_mpcc_state(
414+ struct mpc *mpc,
415+ int mpcc_inst,
416+ struct mpcc_state *s)
417+{
418+ struct dcn10_mpc *mpc10 = TO_DCN10_MPC(mpc);
419+
420+ REG_GET(MPCC_OPP_ID[mpcc_inst], MPCC_OPP_ID, &s->opp_id);
421+ REG_GET(MPCC_TOP_SEL[mpcc_inst], MPCC_TOP_SEL, &s->dpp_id);
422+ REG_GET(MPCC_BOT_SEL[mpcc_inst], MPCC_BOT_SEL, &s->bot_mpcc_id);
423+ REG_GET_4(MPCC_CONTROL[mpcc_inst], MPCC_MODE, &s->mode,
424+ MPCC_ALPHA_BLND_MODE, &s->alpha_mode,
425+ MPCC_ALPHA_MULTIPLIED_MODE, &s->pre_multiplied_alpha,
426+ MPCC_BLND_ACTIVE_OVERLAP_ONLY, &s->overlap_only);
427+ REG_GET_2(MPCC_STATUS[mpcc_inst], MPCC_IDLE, &s->idle,
428+ MPCC_BUSY, &s->busy);
429+}
430+
412431 const struct mpc_funcs dcn10_mpc_funcs = {
432+ .read_mpcc_state = mpc1_read_mpcc_state,
413433 .insert_plane = mpc1_insert_plane,
414434 .remove_mpcc = mpc1_remove_mpcc,
415435 .mpc_init = mpc1_mpc_init,
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.h+5−0
@@ -183,4 +183,9 @@ struct mpcc *mpc1_get_mpcc_for_dpp( · 182 unmodified lines
183183 struct mpc_tree *tree,
184184 int dpp_id);
185185
186+void mpc1_read_mpcc_state(
187+ struct mpc *mpc,
188+ int mpcc_inst,
189+ struct mpcc_state *s);
190+
186191 #endif
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c+88−6
@@ -93,6 +93,81 @@ static void optc1_disable_stereo(struct timing_generator *optc) · 92 unmodified lines
9393 OTG_3D_STRUCTURE_STEREO_SEL_OVR, 0);
9494 }
9595
96+static uint32_t get_start_vline(struct timing_generator *optc, const struct dc_crtc_timing *dc_crtc_timing)
97+{
98+ struct dc_crtc_timing patched_crtc_timing;
99+ int vesa_sync_start;
100+ int asic_blank_end;
101+ int interlace_factor;
102+ int vertical_line_start;
103+
104+ patched_crtc_timing = *dc_crtc_timing;
105+ optc1_apply_front_porch_workaround(optc, &patched_crtc_timing);
106+
107+ vesa_sync_start = patched_crtc_timing.h_addressable +
108+ patched_crtc_timing.h_border_right +
109+ patched_crtc_timing.h_front_porch;
110+
111+ asic_blank_end = patched_crtc_timing.h_total -
112+ vesa_sync_start -
113+ patched_crtc_timing.h_border_left;
114+
115+ interlace_factor = patched_crtc_timing.flags.INTERLACE ? 2 : 1;
116+
117+ vesa_sync_start = patched_crtc_timing.v_addressable +
118+ patched_crtc_timing.v_border_bottom +
119+ patched_crtc_timing.v_front_porch;
120+
121+ asic_blank_end = (patched_crtc_timing.v_total -
122+ vesa_sync_start -
123+ patched_crtc_timing.v_border_top)
124+ * interlace_factor;
125+
126+ vertical_line_start = asic_blank_end - optc->dlg_otg_param.vstartup_start + 1;
127+ if (vertical_line_start < 0) {
128+ ASSERT(0);
129+ vertical_line_start = 0;
130+ }
131+
132+ return vertical_line_start;
133+}
134+
135+void optc1_program_vline_interrupt(
136+ struct timing_generator *optc,
137+ const struct dc_crtc_timing *dc_crtc_timing,
138+ unsigned long long vsync_delta)
139+{
140+
141+ struct optc *optc1 = DCN10TG_FROM_TG(optc);
142+
143+ unsigned long long req_delta_tens_of_usec = div64_u64((vsync_delta + 9999), 10000);
144+ unsigned long long pix_clk_hundreds_khz = div64_u64((dc_crtc_timing->pix_clk_khz + 99), 100);
145+ uint32_t req_delta_lines = (uint32_t) div64_u64(
146+ (req_delta_tens_of_usec * pix_clk_hundreds_khz + dc_crtc_timing->h_total - 1),
147+ dc_crtc_timing->h_total);
148+
149+ uint32_t vsync_line = get_start_vline(optc, dc_crtc_timing);
150+ uint32_t start_line = 0;
151+ uint32_t endLine = 0;
152+
153+ if (req_delta_lines != 0)
154+ req_delta_lines--;
155+
156+ if (req_delta_lines > vsync_line)
157+ start_line = dc_crtc_timing->v_total - (req_delta_lines - vsync_line) - 1;
158+ else
159+ start_line = vsync_line - req_delta_lines;
160+
161+ endLine = start_line + 2;
162+
163+ if (endLine >= dc_crtc_timing->v_total)
164+ endLine = 2;
165+
166+ REG_SET_2(OTG_VERTICAL_INTERRUPT0_POSITION, 0,
167+ OTG_VERTICAL_INTERRUPT0_LINE_START, start_line,
168+ OTG_VERTICAL_INTERRUPT0_LINE_END, endLine);
169+}
170+
96171 /**
97172 * program_timing_generator used by mode timing set
98173 * Program CRTC Timing Registers - OTG_H_*, OTG_V_*, Pixel repetition.
@@ -780,17 +855,17 @@ void optc1_set_drr( · 681 unmodified lines
780855 OTG_SET_V_TOTAL_MIN_MASK_EN, 0,
781856 OTG_SET_V_TOTAL_MIN_MASK, 0);
782857 } else {
783− REG_SET(OTG_V_TOTAL_MIN, 0,
784− OTG_V_TOTAL_MIN, 0);
785−
786− REG_SET(OTG_V_TOTAL_MAX, 0,
787− OTG_V_TOTAL_MAX, 0);
788−
789858 REG_UPDATE_4(OTG_V_TOTAL_CONTROL,
790859 OTG_SET_V_TOTAL_MIN_MASK, 0,
791860 OTG_V_TOTAL_MIN_SEL, 0,
792861 OTG_V_TOTAL_MAX_SEL, 0,
793862 OTG_FORCE_LOCK_ON_EVENT, 0);
863+
864+ REG_SET(OTG_V_TOTAL_MIN, 0,
865+ OTG_V_TOTAL_MIN, 0);
866+
867+ REG_SET(OTG_V_TOTAL_MAX, 0,
868+ OTG_V_TOTAL_MAX, 0);
794869 }
795870 }
796871
@@ -1154,6 +1229,12 @@ void optc1_read_otg_state(struct optc *optc1, · 357 unmodified lines
11541229 REG_GET(OTG_V_TOTAL_MIN,
11551230 OTG_V_TOTAL_MIN, &s->v_total_min);
11561231
1232+ REG_GET(OTG_V_TOTAL_CONTROL,
1233+ OTG_V_TOTAL_MAX_SEL, &s->v_total_max_sel);
1234+
1235+ REG_GET(OTG_V_TOTAL_CONTROL,
1236+ OTG_V_TOTAL_MIN_SEL, &s->v_total_min_sel);
1237+
11571238 REG_GET_2(OTG_V_SYNC_A,
11581239 OTG_V_SYNC_A_START, &s->v_sync_a_start,
11591240 OTG_V_SYNC_A_END, &s->v_sync_a_end);
@@ -1215,6 +1296,7 @@ static bool optc1_is_optc_underflow_occurred(struct timing_generator *optc) · 55 unmodified lines
12151296 static const struct timing_generator_funcs dcn10_tg_funcs = {
12161297 .validate_timing = optc1_validate_timing,
12171298 .program_timing = optc1_program_timing,
1299+ .program_vline_interrupt = optc1_program_vline_interrupt,
12181300 .program_global_sync = optc1_program_global_sync,
12191301 .enable_crtc = optc1_enable_crtc,
12201302 .disable_crtc = optc1_disable_crtc,
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h+16−0
@@ -65,6 +65,8 @@ · 64 unmodified lines
6565 SRI(OTG_NOM_VERT_POSITION, OTG, inst),\
6666 SRI(OTG_BLACK_COLOR, OTG, inst),\
6767 SRI(OTG_CLOCK_CONTROL, OTG, inst),\
68+ SRI(OTG_VERTICAL_INTERRUPT0_CONTROL, OTG, inst),\
69+ SRI(OTG_VERTICAL_INTERRUPT0_POSITION, OTG, inst),\
6870 SRI(OTG_VERTICAL_INTERRUPT2_CONTROL, OTG, inst),\
6971 SRI(OTG_VERTICAL_INTERRUPT2_POSITION, OTG, inst),\
7072 SRI(OPTC_INPUT_CLOCK_CONTROL, ODM, inst),\
@@ -124,6 +126,8 @@ struct dcn_optc_registers { · 53 unmodified lines
124126 uint32_t OTG_TEST_PATTERN_CONTROL;
125127 uint32_t OTG_TEST_PATTERN_COLOR;
126128 uint32_t OTG_CLOCK_CONTROL;
129+ uint32_t OTG_VERTICAL_INTERRUPT0_CONTROL;
130+ uint32_t OTG_VERTICAL_INTERRUPT0_POSITION;
127131 uint32_t OTG_VERTICAL_INTERRUPT2_CONTROL;
128132 uint32_t OTG_VERTICAL_INTERRUPT2_POSITION;
129133 uint32_t OPTC_INPUT_CLOCK_CONTROL;
@@ -206,6 +210,9 @@ struct dcn_optc_registers { · 76 unmodified lines
206210 SF(OTG0_OTG_CLOCK_CONTROL, OTG_CLOCK_EN, mask_sh),\
207211 SF(OTG0_OTG_CLOCK_CONTROL, OTG_CLOCK_ON, mask_sh),\
208212 SF(OTG0_OTG_CLOCK_CONTROL, OTG_CLOCK_GATE_DIS, mask_sh),\
213+ SF(OTG0_OTG_VERTICAL_INTERRUPT0_CONTROL, OTG_VERTICAL_INTERRUPT0_INT_ENABLE, mask_sh),\
214+ SF(OTG0_OTG_VERTICAL_INTERRUPT0_POSITION, OTG_VERTICAL_INTERRUPT0_LINE_START, mask_sh),\
215+ SF(OTG0_OTG_VERTICAL_INTERRUPT0_POSITION, OTG_VERTICAL_INTERRUPT0_LINE_END, mask_sh),\
209216 SF(OTG0_OTG_VERTICAL_INTERRUPT2_CONTROL, OTG_VERTICAL_INTERRUPT2_INT_ENABLE, mask_sh),\
210217 SF(OTG0_OTG_VERTICAL_INTERRUPT2_POSITION, OTG_VERTICAL_INTERRUPT2_LINE_START, mask_sh),\
211218 SF(ODM0_OPTC_INPUT_CLOCK_CONTROL, OPTC_INPUT_CLK_EN, mask_sh),\
@@ -323,6 +330,9 @@ struct dcn_optc_registers { · 111 unmodified lines
323330 type OTG_CLOCK_EN;\
324331 type OTG_CLOCK_ON;\
325332 type OTG_CLOCK_GATE_DIS;\
333+ type OTG_VERTICAL_INTERRUPT0_INT_ENABLE;\
334+ type OTG_VERTICAL_INTERRUPT0_LINE_START;\
335+ type OTG_VERTICAL_INTERRUPT0_LINE_END;\
326336 type OTG_VERTICAL_INTERRUPT2_INT_ENABLE;\
327337 type OTG_VERTICAL_INTERRUPT2_LINE_START;\
328338 type OPTC_INPUT_CLK_EN;\
@@ -396,6 +406,8 @@ struct dcn_otg_state { · 67 unmodified lines
396406 uint32_t v_total;
397407 uint32_t v_total_max;
398408 uint32_t v_total_min;
409+ uint32_t v_total_min_sel;
410+ uint32_t v_total_max_sel;
399411 uint32_t v_sync_a_start;
400412 uint32_t v_sync_a_end;
401413 uint32_t h_blank_start;
@@ -420,6 +432,10 @@ void optc1_program_timing( · 18 unmodified lines
420432 const struct dc_crtc_timing *dc_crtc_timing,
421433 bool use_vbios);
422434
435+void optc1_program_vline_interrupt(struct timing_generator *optc,
436+ const struct dc_crtc_timing *dc_crtc_timing,
437+ unsigned long long vsync_delta);
438+
423439 void optc1_program_global_sync(
424440 struct timing_generator *optc);
425441
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c+21−282
@@ -39,7 +39,7 @@ · 38 unmodified lines
3939 #include "dce110/dce110_hw_sequencer.h"
4040 #include "dcn10/dcn10_opp.h"
4141 #include "dce/dce_link_encoder.h"
42−#include "dce/dce_stream_encoder.h"
42+#include "dcn10/dcn10_stream_encoder.h"
4343 #include "dce/dce_clocks.h"
4444 #include "dce/dce_clock_source.h"
4545 #include "dce/dce_audio.h"
@@ -166,36 +166,22 @@ static const struct dce_abm_mask abm_mask = { · 120 unmodified lines
166166
167167 #define stream_enc_regs(id)\
168168 [id] = {\
169− SE_DCN_REG_LIST(id),\
170− .TMDS_CNTL = 0,\
171− .AFMT_AVI_INFO0 = 0,\
172− .AFMT_AVI_INFO1 = 0,\
173− .AFMT_AVI_INFO2 = 0,\
174− .AFMT_AVI_INFO3 = 0,\
169+ SE_DCN_REG_LIST(id)\
175170 }
176171
177−static const struct dce110_stream_enc_registers stream_enc_regs[] = {
172+static const struct dcn10_stream_enc_registers stream_enc_regs[] = {
178173 stream_enc_regs(0),
179174 stream_enc_regs(1),
180175 stream_enc_regs(2),
181176 stream_enc_regs(3),
182177 };
183178
184−static const struct dce_stream_encoder_shift se_shift = {
179+static const struct dcn10_stream_encoder_shift se_shift = {
185180 SE_COMMON_MASK_SH_LIST_DCN10(__SHIFT)
186181 };
187182
188−static const struct dce_stream_encoder_mask se_mask = {
189− SE_COMMON_MASK_SH_LIST_DCN10(_MASK),
190− .AFMT_GENERIC0_UPDATE = 0,
191− .AFMT_GENERIC2_UPDATE = 0,
192− .DP_DYN_RANGE = 0,
193− .DP_YCBCR_RANGE = 0,
194− .HDMI_AVI_INFO_SEND = 0,
195− .HDMI_AVI_INFO_CONT = 0,
196− .HDMI_AVI_INFO_LINE = 0,
197− .DP_SEC_AVI_ENABLE = 0,
198− .AFMT_AVI_INFO_VERSION = 0
183+static const struct dcn10_stream_encoder_mask se_mask = {
184+ SE_COMMON_MASK_SH_LIST_DCN10(_MASK)
199185 };
200186
201187 #define audio_regs(id)\
@@ -320,11 +306,14 @@ static const struct dcn_dpp_registers tf_regs[] = { · 118 unmodified lines
320306 };
321307
322308 static const struct dcn_dpp_shift tf_shift = {
323− TF_REG_LIST_SH_MASK_DCN10(__SHIFT)
309+ TF_REG_LIST_SH_MASK_DCN10(__SHIFT),
310+ TF_DEBUG_REG_LIST_SH_DCN10
311+
324312 };
325313
326314 static const struct dcn_dpp_mask tf_mask = {
327315 TF_REG_LIST_SH_MASK_DCN10(_MASK),
316+ TF_DEBUG_REG_LIST_MASK_DCN10
328317 };
329318
330319 static const struct dcn_mpc_registers mpc_regs = {
@@ -650,16 +639,16 @@ static struct stream_encoder *dcn10_stream_encoder_create( · 319 unmodified lines
650639 enum engine_id eng_id,
651640 struct dc_context *ctx)
652641 {
653− struct dce110_stream_encoder *enc110 =
654− kzalloc(sizeof(struct dce110_stream_encoder), GFP_KERNEL);
642+ struct dcn10_stream_encoder *enc1 =
643+ kzalloc(sizeof(struct dcn10_stream_encoder), GFP_KERNEL);
655644
656− if (!enc110)
645+ if (!enc1)
657646 return NULL;
658647
659− dce110_stream_encoder_construct(enc110, ctx, ctx->dc_bios, eng_id,
648+ dcn10_stream_encoder_construct(enc1, ctx, ctx->dc_bios, eng_id,
660649 &stream_enc_regs[eng_id],
661650 &se_shift, &se_mask);
662− return &enc110->base;
651+ return &enc1->base;
663652 }
664653
665654 static const struct dce_hwseq_registers hwseq_reg = {
@@ -918,36 +907,6 @@ enum dc_status dcn10_add_stream_to_ctx( · 252 unmodified lines
918907 return result;
919908 }
920909
921−enum dc_status dcn10_validate_guaranteed(
922− struct dc *dc,
923− struct dc_stream_state *dc_stream,
924− struct dc_state *context)
925−{
926− enum dc_status result = DC_ERROR_UNEXPECTED;
927−
928− context->streams[0] = dc_stream;
929− dc_stream_retain(context->streams[0]);
930− context->stream_count++;
931−
932− result = resource_map_pool_resources(dc, context, dc_stream);
933−
934− if (result == DC_OK)
935− result = resource_map_phy_clock_resources(dc, context, dc_stream);
936−
937− if (result == DC_OK)
938− result = build_mapped_resource(dc, context, dc_stream);
939−
940− if (result == DC_OK) {
941− validate_guaranteed_copy_streams(
942− context, dc->caps.max_streams);
943− result = resource_build_scaling_params_for_context(dc, context);
944− }
945− if (result == DC_OK && !dcn_validate_bandwidth(dc, context))
946− return DC_FAIL_BANDWIDTH_VALIDATE;
947−
948− return result;
949−}
950−
951910 static struct pipe_ctx *dcn10_acquire_idle_pipe_for_layer(
952911 struct dc_state *context,
953912 const struct resource_pool *pool,
@@ -978,235 +937,16 @@ static struct pipe_ctx *dcn10_acquire_idle_pipe_for_layer( · 24 unmodified lines
978937 return idle_pipe;
979938 }
980939
981−enum dcc_control {
982− dcc_control__256_256_xxx,
983− dcc_control__128_128_xxx,
984− dcc_control__256_64_64,
985−};
986−
987−enum segment_order {
988− segment_order__na,
989− segment_order__contiguous,
990− segment_order__non_contiguous,
991−};
992−
993−static bool dcc_support_pixel_format(
994− enum surface_pixel_format format,
995− unsigned int *bytes_per_element)
996−{
997− /* DML: get_bytes_per_element */
998− switch (format) {
999− case SURFACE_PIXEL_FORMAT_GRPH_ARGB1555:
1000− case SURFACE_PIXEL_FORMAT_GRPH_RGB565:
1001− *bytes_per_element = 2;
1002− return true;
1003− case SURFACE_PIXEL_FORMAT_GRPH_ARGB8888:
1004− case SURFACE_PIXEL_FORMAT_GRPH_ABGR8888:
1005− case SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010:
1006− case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010:
1007− *bytes_per_element = 4;
1008− return true;
1009− case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616:
1010− case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F:
1011− case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F:
1012− *bytes_per_element = 8;
1013− return true;
1014− default:
1015− return false;
1016− }
1017−}
1018−
1019−static bool dcc_support_swizzle(
1020− enum swizzle_mode_values swizzle,
1021− unsigned int bytes_per_element,
1022− enum segment_order *segment_order_horz,
1023− enum segment_order *segment_order_vert)
1024−{
1025− bool standard_swizzle = false;
1026− bool display_swizzle = false;
1027−
1028− switch (swizzle) {
1029− case DC_SW_4KB_S:
1030− case DC_SW_64KB_S:
1031− case DC_SW_VAR_S:
1032− case DC_SW_4KB_S_X:
1033− case DC_SW_64KB_S_X:
1034− case DC_SW_VAR_S_X:
1035− standard_swizzle = true;
1036− break;
1037− case DC_SW_4KB_D:
1038− case DC_SW_64KB_D:
1039− case DC_SW_VAR_D:
1040− case DC_SW_4KB_D_X:
1041− case DC_SW_64KB_D_X:
1042− case DC_SW_VAR_D_X:
1043− display_swizzle = true;
1044− break;
1045− default:
1046− break;
1047− }
1048−
1049− if (bytes_per_element == 1 && standard_swizzle) {
1050− *segment_order_horz = segment_order__contiguous;
1051− *segment_order_vert = segment_order__na;
1052− return true;
1053− }
1054− if (bytes_per_element == 2 && standard_swizzle) {
1055− *segment_order_horz = segment_order__non_contiguous;
1056− *segment_order_vert = segment_order__contiguous;
1057− return true;
1058− }
1059− if (bytes_per_element == 4 && standard_swizzle) {
1060− *segment_order_horz = segment_order__non_contiguous;
1061− *segment_order_vert = segment_order__contiguous;
1062− return true;
1063− }
1064− if (bytes_per_element == 8 && standard_swizzle) {
1065− *segment_order_horz = segment_order__na;
1066− *segment_order_vert = segment_order__contiguous;
1067− return true;
1068− }
1069− if (bytes_per_element == 8 && display_swizzle) {
1070− *segment_order_horz = segment_order__contiguous;
1071− *segment_order_vert = segment_order__non_contiguous;
1072− return true;
1073− }
1074−
1075− return false;
1076−}
1077−
1078−static void get_blk256_size(unsigned int *blk256_width, unsigned int *blk256_height,
1079− unsigned int bytes_per_element)
1080−{
1081− /* copied from DML. might want to refactor DML to leverage from DML */
1082− /* DML : get_blk256_size */
1083− if (bytes_per_element == 1) {
1084− *blk256_width = 16;
1085− *blk256_height = 16;
1086− } else if (bytes_per_element == 2) {
1087− *blk256_width = 16;
1088− *blk256_height = 8;
1089− } else if (bytes_per_element == 4) {
1090− *blk256_width = 8;
1091− *blk256_height = 8;
1092− } else if (bytes_per_element == 8) {
1093− *blk256_width = 8;
1094− *blk256_height = 4;
1095− }
1096−}
1097−
1098−static void det_request_size(
1099− unsigned int height,
1100− unsigned int width,
1101− unsigned int bpe,
1102− bool *req128_horz_wc,
1103− bool *req128_vert_wc)
1104−{
1105− unsigned int detile_buf_size = 164 * 1024; /* 164KB for DCN1.0 */
1106−
1107− unsigned int blk256_height = 0;
1108− unsigned int blk256_width = 0;
1109− unsigned int swath_bytes_horz_wc, swath_bytes_vert_wc;
1110−
1111− get_blk256_size(&blk256_width, &blk256_height, bpe);
1112−
1113− swath_bytes_horz_wc = height * blk256_height * bpe;
1114− swath_bytes_vert_wc = width * blk256_width * bpe;
1115−
1116− *req128_horz_wc = (2 * swath_bytes_horz_wc <= detile_buf_size) ?
1117− false : /* full 256B request */
1118− true; /* half 128b request */
1119−
1120− *req128_vert_wc = (2 * swath_bytes_vert_wc <= detile_buf_size) ?
1121− false : /* full 256B request */
1122− true; /* half 128b request */
1123−}
1124−
1125−static bool get_dcc_compression_cap(const struct dc *dc,
940+static bool dcn10_get_dcc_compression_cap(const struct dc *dc,
1126941 const struct dc_dcc_surface_param *input,
1127942 struct dc_surface_dcc_cap *output)
1128943 {
1129− /* implement section 1.6.2.1 of DCN1_Programming_Guide.docx */
1130− enum dcc_control dcc_control;
1131− unsigned int bpe;
1132− enum segment_order segment_order_horz, segment_order_vert;
1133− bool req128_horz_wc, req128_vert_wc;
1134−
1135− memset(output, 0, sizeof(*output));
1136−
1137− if (dc->debug.disable_dcc == DCC_DISABLE)
1138− return false;
1139−
1140− if (!dcc_support_pixel_format(input->format,
1141− &bpe))
1142− return false;
1143−
1144− if (!dcc_support_swizzle(input->swizzle_mode, bpe,
1145− &segment_order_horz, &segment_order_vert))
1146− return false;
1147−
1148− det_request_size(input->surface_size.height, input->surface_size.width,
1149− bpe, &req128_horz_wc, &req128_vert_wc);
1150−
1151− if (!req128_horz_wc && !req128_vert_wc) {
1152− dcc_control = dcc_control__256_256_xxx;
1153− } else if (input->scan == SCAN_DIRECTION_HORIZONTAL) {
1154− if (!req128_horz_wc)
1155− dcc_control = dcc_control__256_256_xxx;
1156− else if (segment_order_horz == segment_order__contiguous)
1157− dcc_control = dcc_control__128_128_xxx;
1158− else
1159− dcc_control = dcc_control__256_64_64;
1160− } else if (input->scan == SCAN_DIRECTION_VERTICAL) {
1161− if (!req128_vert_wc)
1162− dcc_control = dcc_control__256_256_xxx;
1163− else if (segment_order_vert == segment_order__contiguous)
1164− dcc_control = dcc_control__128_128_xxx;
1165− else
1166− dcc_control = dcc_control__256_64_64;
1167− } else {
1168− if ((req128_horz_wc &&
1169− segment_order_horz == segment_order__non_contiguous) ||
1170− (req128_vert_wc &&
1171− segment_order_vert == segment_order__non_contiguous))
1172− /* access_dir not known, must use most constraining */
1173− dcc_control = dcc_control__256_64_64;
1174− else
1175− /* reg128 is true for either horz and vert
1176− * but segment_order is contiguous
1177− */
1178− dcc_control = dcc_control__128_128_xxx;
1179− }
1180−
1181− if (dc->debug.disable_dcc == DCC_HALF_REQ_DISALBE &&
1182− dcc_control != dcc_control__256_256_xxx)
1183− return false;
1184−
1185− switch (dcc_control) {
1186− case dcc_control__256_256_xxx:
1187− output->grph.rgb.max_uncompressed_blk_size = 256;
1188− output->grph.rgb.max_compressed_blk_size = 256;
1189− output->grph.rgb.independent_64b_blks = false;
1190− break;
1191− case dcc_control__128_128_xxx:
1192− output->grph.rgb.max_uncompressed_blk_size = 128;
1193− output->grph.rgb.max_compressed_blk_size = 128;
1194− output->grph.rgb.independent_64b_blks = false;
1195− break;
1196− case dcc_control__256_64_64:
1197− output->grph.rgb.max_uncompressed_blk_size = 256;
1198− output->grph.rgb.max_compressed_blk_size = 64;
1199− output->grph.rgb.independent_64b_blks = true;
1200− break;
1201− }
1202−
1203− output->capable = true;
1204− output->const_color_support = false;
1205−
1206− return true;
944+ return dc->res_pool->hubbub->funcs->get_dcc_compression_cap(
945+ dc->res_pool->hubbub,
946+ input,
947+ output);
1207948 }
1208949
1209−
1210950 static void dcn10_destroy_resource_pool(struct resource_pool **pool)
1211951 {
1212952 struct dcn10_resource_pool *dcn10_pool = TO_DCN10_RES_POOL(*pool);
@@ -1227,13 +967,12 @@ static enum dc_status dcn10_validate_plane(const struct dc_plane_state *plane_st · 14 unmodified lines
1227967 }
1228968
1229969 static struct dc_cap_funcs cap_funcs = {
1230− .get_dcc_compression_cap = get_dcc_compression_cap
970+ .get_dcc_compression_cap = dcn10_get_dcc_compression_cap
1231971 };
1232972
1233973 static struct resource_funcs dcn10_res_pool_funcs = {
1234974 .destroy = dcn10_destroy_resource_pool,
1235975 .link_enc_create = dcn10_link_encoder_create,
1236− .validate_guaranteed = dcn10_validate_guaranteed,
1237976 .validate_bandwidth = dcn_validate_bandwidth,
1238977 .acquire_idle_pipe_for_layer = dcn10_acquire_idle_pipe_for_layer,
1239978 .validate_plane = dcn10_validate_plane,
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c+1490−0
@@ -0,0 +1,1490 @@
1+/*
2+ * Copyright 2012-15 Advanced Micro Devices, Inc.
3+ *
4+ * Permission is hereby granted, free of charge, to any person obtaining a
5+ * copy of this software and associated documentation files (the "Software"),
6+ * to deal in the Software without restriction, including without limitation
7+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8+ * and/or sell copies of the Software, and to permit persons to whom the
9+ * Software is furnished to do so, subject to the following conditions:
10+ *
11+ * The above copyright notice and this permission notice shall be included in
12+ * all copies or substantial portions of the Software.
13+ *
14+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20+ * OTHER DEALINGS IN THE SOFTWARE.
21+ *
22+ * Authors: AMD
23+ *
24+ */
25+
26+
27+#include "dc_bios_types.h"
28+#include "dcn10_stream_encoder.h"
29+#include "reg_helper.h"
30+#include "hw_shared.h"
31+
32+#define DC_LOGGER \
33+ enc1->base.ctx->logger
34+
35+
36+#define REG(reg)\
37+ (enc1->regs->reg)
38+
39+#undef FN
40+#define FN(reg_name, field_name) \
41+ enc1->se_shift->field_name, enc1->se_mask->field_name
42+
43+#define VBI_LINE_0 0
44+#define DP_BLANK_MAX_RETRY 20
45+#define HDMI_CLOCK_CHANNEL_RATE_MORE_340M 340000
46+
47+
48+enum {
49+ DP_MST_UPDATE_MAX_RETRY = 50
50+};
51+
52+#define CTX \
53+ enc1->base.ctx
54+
55+void enc1_update_generic_info_packet(
56+ struct dcn10_stream_encoder *enc1,
57+ uint32_t packet_index,
58+ const struct dc_info_packet *info_packet)
59+{
60+ uint32_t regval;
61+ /* TODOFPGA Figure out a proper number for max_retries polling for lock
62+ * use 50 for now.
63+ */
64+ uint32_t max_retries = 50;
65+
66+ /*we need turn on clock before programming AFMT block*/
67+ REG_UPDATE(AFMT_CNTL, AFMT_AUDIO_CLOCK_EN, 1);
68+
69+ if (packet_index >= 8)
70+ ASSERT(0);
71+
72+ /* poll dig_update_lock is not locked -> asic internal signal
73+ * assume otg master lock will unlock it
74+ */
75+/* REG_WAIT(AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC_LOCK_STATUS,
76+ 0, 10, max_retries);*/
77+
78+ /* check if HW reading GSP memory */
79+ REG_WAIT(AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC_CONFLICT,
80+ 0, 10, max_retries);
81+
82+ /* HW does is not reading GSP memory not reading too long ->
83+ * something wrong. clear GPS memory access and notify?
84+ * hw SW is writing to GSP memory
85+ */
86+ REG_UPDATE(AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC_CONFLICT_CLR, 1);
87+
88+ /* choose which generic packet to use */
89+ regval = REG_READ(AFMT_VBI_PACKET_CONTROL);
90+ REG_UPDATE(AFMT_VBI_PACKET_CONTROL,
91+ AFMT_GENERIC_INDEX, packet_index);
92+
93+ /* write generic packet header
94+ * (4th byte is for GENERIC0 only)
95+ */
96+ REG_SET_4(AFMT_GENERIC_HDR, 0,
97+ AFMT_GENERIC_HB0, info_packet->hb0,
98+ AFMT_GENERIC_HB1, info_packet->hb1,
99+ AFMT_GENERIC_HB2, info_packet->hb2,
100+ AFMT_GENERIC_HB3, info_packet->hb3);
101+
102+ /* write generic packet contents
103+ * (we never use last 4 bytes)
104+ * there are 8 (0-7) mmDIG0_AFMT_GENERIC0_x registers
105+ */
106+ {
107+ const uint32_t *content =
108+ (const uint32_t *) &info_packet->sb[0];
109+
110+ REG_WRITE(AFMT_GENERIC_0, *content++);
111+ REG_WRITE(AFMT_GENERIC_1, *content++);
112+ REG_WRITE(AFMT_GENERIC_2, *content++);
113+ REG_WRITE(AFMT_GENERIC_3, *content++);
114+ REG_WRITE(AFMT_GENERIC_4, *content++);
115+ REG_WRITE(AFMT_GENERIC_5, *content++);
116+ REG_WRITE(AFMT_GENERIC_6, *content++);
117+ REG_WRITE(AFMT_GENERIC_7, *content);
118+ }
119+
120+ switch (packet_index) {
121+ case 0:
122+ REG_UPDATE(AFMT_VBI_PACKET_CONTROL1,
123+ AFMT_GENERIC0_FRAME_UPDATE, 1);
124+ break;
125+ case 1:
126+ REG_UPDATE(AFMT_VBI_PACKET_CONTROL1,
127+ AFMT_GENERIC1_FRAME_UPDATE, 1);
128+ break;
129+ case 2:
130+ REG_UPDATE(AFMT_VBI_PACKET_CONTROL1,
131+ AFMT_GENERIC2_FRAME_UPDATE, 1);
132+ break;
133+ case 3:
134+ REG_UPDATE(AFMT_VBI_PACKET_CONTROL1,
135+ AFMT_GENERIC3_FRAME_UPDATE, 1);
136+ break;
137+ case 4:
138+ REG_UPDATE(AFMT_VBI_PACKET_CONTROL1,
139+ AFMT_GENERIC4_FRAME_UPDATE, 1);
140+ break;
141+ case 5:
142+ REG_UPDATE(AFMT_VBI_PACKET_CONTROL1,
143+ AFMT_GENERIC5_FRAME_UPDATE, 1);
144+ break;
145+ case 6:
146+ REG_UPDATE(AFMT_VBI_PACKET_CONTROL1,
147+ AFMT_GENERIC6_FRAME_UPDATE, 1);
148+ break;
149+ case 7:
150+ REG_UPDATE(AFMT_VBI_PACKET_CONTROL1,
151+ AFMT_GENERIC7_FRAME_UPDATE, 1);
152+ break;
153+ default:
154+ break;
155+ }
156+}
157+
158+static void enc1_update_hdmi_info_packet(
159+ struct dcn10_stream_encoder *enc1,
160+ uint32_t packet_index,
161+ const struct dc_info_packet *info_packet)
162+{
163+ uint32_t cont, send, line;
164+
165+ if (info_packet->valid) {
166+ enc1_update_generic_info_packet(
167+ enc1,
168+ packet_index,
169+ info_packet);
170+
171+ /* enable transmission of packet(s) -
172+ * packet transmission begins on the next frame
173+ */
174+ cont = 1;
175+ /* send packet(s) every frame */
176+ send = 1;
177+ /* select line number to send packets on */
178+ line = 2;
179+ } else {
180+ cont = 0;
181+ send = 0;
182+ line = 0;
183+ }
184+
185+ /* choose which generic packet control to use */
186+ switch (packet_index) {
187+ case 0:
188+ REG_UPDATE_3(HDMI_GENERIC_PACKET_CONTROL0,
189+ HDMI_GENERIC0_CONT, cont,
190+ HDMI_GENERIC0_SEND, send,
191+ HDMI_GENERIC0_LINE, line);
192+ break;
193+ case 1:
194+ REG_UPDATE_3(HDMI_GENERIC_PACKET_CONTROL0,
195+ HDMI_GENERIC1_CONT, cont,
196+ HDMI_GENERIC1_SEND, send,
197+ HDMI_GENERIC1_LINE, line);
198+ break;
199+ case 2:
200+ REG_UPDATE_3(HDMI_GENERIC_PACKET_CONTROL1,
201+ HDMI_GENERIC0_CONT, cont,
202+ HDMI_GENERIC0_SEND, send,
203+ HDMI_GENERIC0_LINE, line);
204+ break;
205+ case 3:
206+ REG_UPDATE_3(HDMI_GENERIC_PACKET_CONTROL1,
207+ HDMI_GENERIC1_CONT, cont,
208+ HDMI_GENERIC1_SEND, send,
209+ HDMI_GENERIC1_LINE, line);
210+ break;
211+ case 4:
212+ REG_UPDATE_3(HDMI_GENERIC_PACKET_CONTROL2,
213+ HDMI_GENERIC0_CONT, cont,
214+ HDMI_GENERIC0_SEND, send,
215+ HDMI_GENERIC0_LINE, line);
216+ break;
217+ case 5:
218+ REG_UPDATE_3(HDMI_GENERIC_PACKET_CONTROL2,
219+ HDMI_GENERIC1_CONT, cont,
220+ HDMI_GENERIC1_SEND, send,
221+ HDMI_GENERIC1_LINE, line);
222+ break;
223+ case 6:
224+ REG_UPDATE_3(HDMI_GENERIC_PACKET_CONTROL3,
225+ HDMI_GENERIC0_CONT, cont,
226+ HDMI_GENERIC0_SEND, send,
227+ HDMI_GENERIC0_LINE, line);
228+ break;
229+ case 7:
230+ REG_UPDATE_3(HDMI_GENERIC_PACKET_CONTROL3,
231+ HDMI_GENERIC1_CONT, cont,
232+ HDMI_GENERIC1_SEND, send,
233+ HDMI_GENERIC1_LINE, line);
234+ break;
235+ default:
236+ /* invalid HW packet index */
237+ DC_LOG_WARNING(
238+ "Invalid HW packet index: %s()\n",
239+ __func__);
240+ return;
241+ }
242+}
243+
244+/* setup stream encoder in dp mode */
245+void enc1_stream_encoder_dp_set_stream_attribute(
246+ struct stream_encoder *enc,
247+ struct dc_crtc_timing *crtc_timing,
248+ enum dc_color_space output_color_space)
249+{
250+ uint32_t h_active_start;
251+ uint32_t v_active_start;
252+ uint32_t misc0 = 0;
253+ uint32_t misc1 = 0;
254+ uint32_t h_blank;
255+ uint32_t h_back_porch;
256+ uint8_t synchronous_clock = 0; /* asynchronous mode */
257+ uint8_t colorimetry_bpc;
258+ uint8_t dynamic_range_rgb = 0; /*full range*/
259+ uint8_t dynamic_range_ycbcr = 1; /*bt709*/
260+
261+ struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
262+
263+ REG_UPDATE(DP_DB_CNTL, DP_DB_DISABLE, 1);
264+
265+ /* set pixel encoding */
266+ switch (crtc_timing->pixel_encoding) {
267+ case PIXEL_ENCODING_YCBCR422:
268+ REG_UPDATE(DP_PIXEL_FORMAT, DP_PIXEL_ENCODING,
269+ DP_PIXEL_ENCODING_TYPE_YCBCR422);
270+ break;
271+ case PIXEL_ENCODING_YCBCR444:
272+ REG_UPDATE(DP_PIXEL_FORMAT, DP_PIXEL_ENCODING,
273+ DP_PIXEL_ENCODING_TYPE_YCBCR444);
274+
275+ if (crtc_timing->flags.Y_ONLY)
276+ if (crtc_timing->display_color_depth != COLOR_DEPTH_666)
277+ /* HW testing only, no use case yet.
278+ * Color depth of Y-only could be
279+ * 8, 10, 12, 16 bits
280+ */
281+ REG_UPDATE(DP_PIXEL_FORMAT, DP_PIXEL_ENCODING,
282+ DP_PIXEL_ENCODING_TYPE_Y_ONLY);
283+ /* Note: DP_MSA_MISC1 bit 7 is the indicator
284+ * of Y-only mode.
285+ * This bit is set in HW if register
286+ * DP_PIXEL_ENCODING is programmed to 0x4
287+ */
288+ break;
289+ case PIXEL_ENCODING_YCBCR420:
290+ REG_UPDATE(DP_PIXEL_FORMAT, DP_PIXEL_ENCODING,
291+ DP_PIXEL_ENCODING_TYPE_YCBCR420);
292+ REG_UPDATE(DP_VID_TIMING, DP_VID_N_MUL, 1);
293+ break;
294+ default:
295+ REG_UPDATE(DP_PIXEL_FORMAT, DP_PIXEL_ENCODING,
296+ DP_PIXEL_ENCODING_TYPE_RGB444);
297+ break;
298+ }
299+
300+ misc1 = REG_READ(DP_MSA_MISC);
301+
302+ /* set color depth */
303+
304+ switch (crtc_timing->display_color_depth) {
305+ case COLOR_DEPTH_666:
306+ REG_UPDATE(DP_PIXEL_FORMAT, DP_COMPONENT_DEPTH,
307+ 0);
308+ break;
309+ case COLOR_DEPTH_888:
310+ REG_UPDATE(DP_PIXEL_FORMAT, DP_COMPONENT_DEPTH,
311+ DP_COMPONENT_PIXEL_DEPTH_8BPC);
312+ break;
313+ case COLOR_DEPTH_101010:
314+ REG_UPDATE(DP_PIXEL_FORMAT, DP_COMPONENT_DEPTH,
315+ DP_COMPONENT_PIXEL_DEPTH_10BPC);
316+
317+ break;
318+ case COLOR_DEPTH_121212:
319+ REG_UPDATE(DP_PIXEL_FORMAT, DP_COMPONENT_DEPTH,
320+ DP_COMPONENT_PIXEL_DEPTH_12BPC);
321+ break;
322+ default:
323+ REG_UPDATE(DP_PIXEL_FORMAT, DP_COMPONENT_DEPTH,
324+ DP_COMPONENT_PIXEL_DEPTH_6BPC);
325+ break;
326+ }
327+
328+ /* set dynamic range and YCbCr range */
329+
330+ switch (crtc_timing->display_color_depth) {
331+ case COLOR_DEPTH_666:
332+ colorimetry_bpc = 0;
333+ break;
334+ case COLOR_DEPTH_888:
335+ colorimetry_bpc = 1;
336+ break;
337+ case COLOR_DEPTH_101010:
338+ colorimetry_bpc = 2;
339+ break;
340+ case COLOR_DEPTH_121212:
341+ colorimetry_bpc = 3;
342+ break;
343+ default:
344+ colorimetry_bpc = 0;
345+ break;
346+ }
347+
348+ misc0 = misc0 | synchronous_clock;
349+ misc0 = colorimetry_bpc << 5;
350+
351+ switch (output_color_space) {
352+ case COLOR_SPACE_SRGB:
353+ misc0 = misc0 | 0x0;
354+ misc1 = misc1 & ~0x80; /* bit7 = 0*/
355+ dynamic_range_rgb = 0; /*full range*/
356+ break;
357+ case COLOR_SPACE_SRGB_LIMITED:
358+ misc0 = misc0 | 0x8; /* bit3=1 */
359+ misc1 = misc1 & ~0x80; /* bit7 = 0*/
360+ dynamic_range_rgb = 1; /*limited range*/
361+ break;
362+ case COLOR_SPACE_YCBCR601:
363+ case COLOR_SPACE_YCBCR601_LIMITED:
364+ misc0 = misc0 | 0x8; /* bit3=1, bit4=0 */
365+ misc1 = misc1 & ~0x80; /* bit7 = 0*/
366+ dynamic_range_ycbcr = 0; /*bt601*/
367+ if (crtc_timing->pixel_encoding == PIXEL_ENCODING_YCBCR422)
368+ misc0 = misc0 | 0x2; /* bit2=0, bit1=1 */
369+ else if (crtc_timing->pixel_encoding == PIXEL_ENCODING_YCBCR444)
370+ misc0 = misc0 | 0x4; /* bit2=1, bit1=0 */
371+ break;
372+ case COLOR_SPACE_YCBCR709:
373+ case COLOR_SPACE_YCBCR709_LIMITED:
374+ misc0 = misc0 | 0x18; /* bit3=1, bit4=1 */
375+ misc1 = misc1 & ~0x80; /* bit7 = 0*/
376+ dynamic_range_ycbcr = 1; /*bt709*/
377+ if (crtc_timing->pixel_encoding == PIXEL_ENCODING_YCBCR422)
378+ misc0 = misc0 | 0x2; /* bit2=0, bit1=1 */
379+ else if (crtc_timing->pixel_encoding == PIXEL_ENCODING_YCBCR444)
380+ misc0 = misc0 | 0x4; /* bit2=1, bit1=0 */
381+ break;
382+ case COLOR_SPACE_2020_RGB_LIMITEDRANGE:
383+ dynamic_range_rgb = 1; /*limited range*/
384+ break;
385+ case COLOR_SPACE_2020_RGB_FULLRANGE:
386+ case COLOR_SPACE_2020_YCBCR:
387+ case COLOR_SPACE_XR_RGB:
388+ case COLOR_SPACE_MSREF_SCRGB:
389+ case COLOR_SPACE_ADOBERGB:
390+ case COLOR_SPACE_DCIP3:
391+ case COLOR_SPACE_XV_YCC_709:
392+ case COLOR_SPACE_XV_YCC_601:
393+ case COLOR_SPACE_DISPLAYNATIVE:
394+ case COLOR_SPACE_DOLBYVISION:
395+ case COLOR_SPACE_APPCTRL:
396+ case COLOR_SPACE_CUSTOMPOINTS:
397+ case COLOR_SPACE_UNKNOWN:
398+ /* do nothing */
399+ break;
400+ }
401+
402+ REG_SET(DP_MSA_COLORIMETRY, 0, DP_MSA_MISC0, misc0);
403+ REG_WRITE(DP_MSA_MISC, misc1); /* MSA_MISC1 */
404+
405+ /* dcn new register
406+ * dc_crtc_timing is vesa dmt struct. data from edid
407+ */
408+ REG_SET_2(DP_MSA_TIMING_PARAM1, 0,
409+ DP_MSA_HTOTAL, crtc_timing->h_total,
410+ DP_MSA_VTOTAL, crtc_timing->v_total);
411+
412+ /* calculate from vesa timing parameters
413+ * h_active_start related to leading edge of sync
414+ */
415+
416+ h_blank = crtc_timing->h_total - crtc_timing->h_border_left -
417+ crtc_timing->h_addressable - crtc_timing->h_border_right;
418+
419+ h_back_porch = h_blank - crtc_timing->h_front_porch -
420+ crtc_timing->h_sync_width;
421+
422+ /* start at beginning of left border */
423+ h_active_start = crtc_timing->h_sync_width + h_back_porch;
424+
425+
426+ v_active_start = crtc_timing->v_total - crtc_timing->v_border_top -
427+ crtc_timing->v_addressable - crtc_timing->v_border_bottom -
428+ crtc_timing->v_front_porch;
429+
430+
431+ /* start at beginning of left border */
432+ REG_SET_2(DP_MSA_TIMING_PARAM2, 0,
433+ DP_MSA_HSTART, h_active_start,
434+ DP_MSA_VSTART, v_active_start);
435+
436+ REG_SET_4(DP_MSA_TIMING_PARAM3, 0,
437+ DP_MSA_HSYNCWIDTH,
438+ crtc_timing->h_sync_width,
439+ DP_MSA_HSYNCPOLARITY,
440+ !crtc_timing->flags.HSYNC_POSITIVE_POLARITY,
441+ DP_MSA_VSYNCWIDTH,
442+ crtc_timing->v_sync_width,
443+ DP_MSA_VSYNCPOLARITY,
444+ !crtc_timing->flags.VSYNC_POSITIVE_POLARITY);
445+
446+ /* HWDITH include border or overscan */
447+ REG_SET_2(DP_MSA_TIMING_PARAM4, 0,
448+ DP_MSA_HWIDTH, crtc_timing->h_border_left +
449+ crtc_timing->h_addressable + crtc_timing->h_border_right,
450+ DP_MSA_VHEIGHT, crtc_timing->v_border_top +
451+ crtc_timing->v_addressable + crtc_timing->v_border_bottom);
452+}
453+
454+static void enc1_stream_encoder_set_stream_attribute_helper(
455+ struct dcn10_stream_encoder *enc1,
456+ struct dc_crtc_timing *crtc_timing)
457+{
458+ switch (crtc_timing->pixel_encoding) {
459+ case PIXEL_ENCODING_YCBCR422:
460+ REG_UPDATE(DIG_FE_CNTL, TMDS_PIXEL_ENCODING, 1);
461+ break;
462+ default:
463+ REG_UPDATE(DIG_FE_CNTL, TMDS_PIXEL_ENCODING, 0);
464+ break;
465+ }
466+ REG_UPDATE(DIG_FE_CNTL, TMDS_COLOR_FORMAT, 0);
467+}
468+
469+/* setup stream encoder in hdmi mode */
470+void enc1_stream_encoder_hdmi_set_stream_attribute(
471+ struct stream_encoder *enc,
472+ struct dc_crtc_timing *crtc_timing,
473+ int actual_pix_clk_khz,
474+ bool enable_audio)
475+{
476+ struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
477+ struct bp_encoder_control cntl = {0};
478+
479+ cntl.action = ENCODER_CONTROL_SETUP;
480+ cntl.engine_id = enc1->base.id;
481+ cntl.signal = SIGNAL_TYPE_HDMI_TYPE_A;
482+ cntl.enable_dp_audio = enable_audio;
483+ cntl.pixel_clock = actual_pix_clk_khz;
484+ cntl.lanes_number = LANE_COUNT_FOUR;
485+
486+ if (enc1->base.bp->funcs->encoder_control(
487+ enc1->base.bp, &cntl) != BP_RESULT_OK)
488+ return;
489+
490+ enc1_stream_encoder_set_stream_attribute_helper(enc1, crtc_timing);
491+
492+ /* setup HDMI engine */
493+ REG_UPDATE_5(HDMI_CONTROL,
494+ HDMI_PACKET_GEN_VERSION, 1,
495+ HDMI_KEEPOUT_MODE, 1,
496+ HDMI_DEEP_COLOR_ENABLE, 0,
497+ HDMI_DATA_SCRAMBLE_EN, 0,
498+ HDMI_CLOCK_CHANNEL_RATE, 0);
499+
500+
501+ switch (crtc_timing->display_color_depth) {
502+ case COLOR_DEPTH_888:
503+ REG_UPDATE(HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 0);
504+ break;
505+ case COLOR_DEPTH_101010:
506+ if (crtc_timing->pixel_encoding == PIXEL_ENCODING_YCBCR422) {
507+ REG_UPDATE_2(HDMI_CONTROL,
508+ HDMI_DEEP_COLOR_DEPTH, 1,
509+ HDMI_DEEP_COLOR_ENABLE, 0);
510+ } else {
511+ REG_UPDATE_2(HDMI_CONTROL,
512+ HDMI_DEEP_COLOR_DEPTH, 1,
513+ HDMI_DEEP_COLOR_ENABLE, 1);
514+ }
515+ break;
516+ case COLOR_DEPTH_121212:
517+ if (crtc_timing->pixel_encoding == PIXEL_ENCODING_YCBCR422) {
518+ REG_UPDATE_2(HDMI_CONTROL,
519+ HDMI_DEEP_COLOR_DEPTH, 2,
520+ HDMI_DEEP_COLOR_ENABLE, 0);
521+ } else {
522+ REG_UPDATE_2(HDMI_CONTROL,
523+ HDMI_DEEP_COLOR_DEPTH, 2,
524+ HDMI_DEEP_COLOR_ENABLE, 1);
525+ }
526+ break;
527+ case COLOR_DEPTH_161616:
528+ REG_UPDATE_2(HDMI_CONTROL,
529+ HDMI_DEEP_COLOR_DEPTH, 3,
530+ HDMI_DEEP_COLOR_ENABLE, 1);
531+ break;
532+ default:
533+ break;
534+ }
535+
536+ if (actual_pix_clk_khz >= HDMI_CLOCK_CHANNEL_RATE_MORE_340M) {
537+ /* enable HDMI data scrambler
538+ * HDMI_CLOCK_CHANNEL_RATE_MORE_340M
539+ * Clock channel frequency is 1/4 of character rate.
540+ */
541+ REG_UPDATE_2(HDMI_CONTROL,
542+ HDMI_DATA_SCRAMBLE_EN, 1,
543+ HDMI_CLOCK_CHANNEL_RATE, 1);
544+ } else if (crtc_timing->flags.LTE_340MCSC_SCRAMBLE) {
545+
546+ /* TODO: New feature for DCE11, still need to implement */
547+
548+ /* enable HDMI data scrambler
549+ * HDMI_CLOCK_CHANNEL_FREQ_EQUAL_TO_CHAR_RATE
550+ * Clock channel frequency is the same
551+ * as character rate
552+ */
553+ REG_UPDATE_2(HDMI_CONTROL,
554+ HDMI_DATA_SCRAMBLE_EN, 1,
555+ HDMI_CLOCK_CHANNEL_RATE, 0);
556+ }
557+
558+
559+ REG_UPDATE_3(HDMI_VBI_PACKET_CONTROL,
560+ HDMI_GC_CONT, 1,
561+ HDMI_GC_SEND, 1,
562+ HDMI_NULL_SEND, 1);
563+
564+ /* following belongs to audio */
565+ REG_UPDATE(HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_SEND, 1);
566+
567+ REG_UPDATE(AFMT_INFOFRAME_CONTROL0, AFMT_AUDIO_INFO_UPDATE, 1);
568+
569+ REG_UPDATE(HDMI_INFOFRAME_CONTROL1, HDMI_AUDIO_INFO_LINE,
570+ VBI_LINE_0 + 2);
571+
572+ REG_UPDATE(HDMI_GC, HDMI_GC_AVMUTE, 0);
573+}
574+
575+/* setup stream encoder in dvi mode */
576+void enc1_stream_encoder_dvi_set_stream_attribute(
577+ struct stream_encoder *enc,
578+ struct dc_crtc_timing *crtc_timing,
579+ bool is_dual_link)
580+{
581+ struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
582+ struct bp_encoder_control cntl = {0};
583+
584+ cntl.action = ENCODER_CONTROL_SETUP;
585+ cntl.engine_id = enc1->base.id;
586+ cntl.signal = is_dual_link ?
587+ SIGNAL_TYPE_DVI_DUAL_LINK : SIGNAL_TYPE_DVI_SINGLE_LINK;
588+ cntl.enable_dp_audio = false;
589+ cntl.pixel_clock = crtc_timing->pix_clk_khz;
590+ cntl.lanes_number = (is_dual_link) ? LANE_COUNT_EIGHT : LANE_COUNT_FOUR;
591+
592+ if (enc1->base.bp->funcs->encoder_control(
593+ enc1->base.bp, &cntl) != BP_RESULT_OK)
594+ return;
595+
596+ ASSERT(crtc_timing->pixel_encoding == PIXEL_ENCODING_RGB);
597+ ASSERT(crtc_timing->display_color_depth == COLOR_DEPTH_888);
598+ enc1_stream_encoder_set_stream_attribute_helper(enc1, crtc_timing);
599+}
600+
601+void enc1_stream_encoder_set_mst_bandwidth(
602+ struct stream_encoder *enc,
603+ struct fixed31_32 avg_time_slots_per_mtp)
604+{
605+ struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
606+ uint32_t x = dal_fixed31_32_floor(
607+ avg_time_slots_per_mtp);
608+ uint32_t y = dal_fixed31_32_ceil(
609+ dal_fixed31_32_shl(
610+ dal_fixed31_32_sub_int(
611+ avg_time_slots_per_mtp,
612+ x),
613+ 26));
614+
615+ REG_SET_2(DP_MSE_RATE_CNTL, 0,
616+ DP_MSE_RATE_X, x,
617+ DP_MSE_RATE_Y, y);
618+
619+ /* wait for update to be completed on the link */
620+ /* i.e. DP_MSE_RATE_UPDATE_PENDING field (read only) */
621+ /* is reset to 0 (not pending) */
622+ REG_WAIT(DP_MSE_RATE_UPDATE, DP_MSE_RATE_UPDATE_PENDING,
623+ 0,
624+ 10, DP_MST_UPDATE_MAX_RETRY);
625+}
626+
627+static void enc1_stream_encoder_update_hdmi_info_packets(
628+ struct stream_encoder *enc,
629+ const struct encoder_info_frame *info_frame)
630+{
631+ struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
632+
633+ /* for bring up, disable dp double TODO */
634+ REG_UPDATE(HDMI_DB_CONTROL, HDMI_DB_DISABLE, 1);
635+
636+ enc1_update_hdmi_info_packet(enc1, 0, &info_frame->avi);
637+ enc1_update_hdmi_info_packet(enc1, 1, &info_frame->vendor);
638+ enc1_update_hdmi_info_packet(enc1, 2, &info_frame->gamut);
639+ enc1_update_hdmi_info_packet(enc1, 3, &info_frame->spd);
640+ enc1_update_hdmi_info_packet(enc1, 4, &info_frame->hdrsmd);
641+}
642+
643+static void enc1_stream_encoder_stop_hdmi_info_packets(
644+ struct stream_encoder *enc)
645+{
646+ struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
647+
648+ /* stop generic packets 0 & 1 on HDMI */
649+ REG_SET_6(HDMI_GENERIC_PACKET_CONTROL0, 0,
650+ HDMI_GENERIC1_CONT, 0,
651+ HDMI_GENERIC1_LINE, 0,
652+ HDMI_GENERIC1_SEND, 0,
653+ HDMI_GENERIC0_CONT, 0,
654+ HDMI_GENERIC0_LINE, 0,
655+ HDMI_GENERIC0_SEND, 0);
656+
657+ /* stop generic packets 2 & 3 on HDMI */
658+ REG_SET_6(HDMI_GENERIC_PACKET_CONTROL1, 0,
659+ HDMI_GENERIC0_CONT, 0,
660+ HDMI_GENERIC0_LINE, 0,
661+ HDMI_GENERIC0_SEND, 0,
662+ HDMI_GENERIC1_CONT, 0,
663+ HDMI_GENERIC1_LINE, 0,
664+ HDMI_GENERIC1_SEND, 0);
665+
666+ /* stop generic packets 2 & 3 on HDMI */
667+ REG_SET_6(HDMI_GENERIC_PACKET_CONTROL2, 0,
668+ HDMI_GENERIC0_CONT, 0,
669+ HDMI_GENERIC0_LINE, 0,
670+ HDMI_GENERIC0_SEND, 0,
671+ HDMI_GENERIC1_CONT, 0,
672+ HDMI_GENERIC1_LINE, 0,
673+ HDMI_GENERIC1_SEND, 0);
674+
675+ REG_SET_6(HDMI_GENERIC_PACKET_CONTROL3, 0,
676+ HDMI_GENERIC0_CONT, 0,
677+ HDMI_GENERIC0_LINE, 0,
678+ HDMI_GENERIC0_SEND, 0,
679+ HDMI_GENERIC1_CONT, 0,
680+ HDMI_GENERIC1_LINE, 0,
681+ HDMI_GENERIC1_SEND, 0);
682+}
683+
684+void enc1_stream_encoder_update_dp_info_packets(
685+ struct stream_encoder *enc,
686+ const struct encoder_info_frame *info_frame)
687+{
688+ struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
689+ uint32_t value = 0;
690+
691+ if (info_frame->vsc.valid)
692+ enc1_update_generic_info_packet(
693+ enc1,
694+ 0, /* packetIndex */
695+ &info_frame->vsc);
696+
697+ if (info_frame->spd.valid)
698+ enc1_update_generic_info_packet(
699+ enc1,
700+ 2, /* packetIndex */
701+ &info_frame->spd);
702+
703+ if (info_frame->hdrsmd.valid)
704+ enc1_update_generic_info_packet(
705+ enc1,
706+ 3, /* packetIndex */
707+ &info_frame->hdrsmd);
708+
709+ /* enable/disable transmission of packet(s).
710+ * If enabled, packet transmission begins on the next frame
711+ */
712+ REG_UPDATE(DP_SEC_CNTL, DP_SEC_GSP0_ENABLE, info_frame->vsc.valid);
713+ REG_UPDATE(DP_SEC_CNTL, DP_SEC_GSP2_ENABLE, info_frame->spd.valid);
714+ REG_UPDATE(DP_SEC_CNTL, DP_SEC_GSP3_ENABLE, info_frame->hdrsmd.valid);
715+
716+
717+ /* This bit is the master enable bit.
718+ * When enabling secondary stream engine,
719+ * this master bit must also be set.
720+ * This register shared with audio info frame.
721+ * Therefore we need to enable master bit
722+ * if at least on of the fields is not 0
723+ */
724+ value = REG_READ(DP_SEC_CNTL);
725+ if (value)
726+ REG_UPDATE(DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, 1);
727+}
728+
729+void enc1_stream_encoder_stop_dp_info_packets(
730+ struct stream_encoder *enc)
731+{
732+ /* stop generic packets on DP */
733+ struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
734+ uint32_t value = 0;
735+
736+ REG_SET_10(DP_SEC_CNTL, 0,
737+ DP_SEC_GSP0_ENABLE, 0,
738+ DP_SEC_GSP1_ENABLE, 0,
739+ DP_SEC_GSP2_ENABLE, 0,
740+ DP_SEC_GSP3_ENABLE, 0,
741+ DP_SEC_GSP4_ENABLE, 0,
742+ DP_SEC_GSP5_ENABLE, 0,
743+ DP_SEC_GSP6_ENABLE, 0,
744+ DP_SEC_GSP7_ENABLE, 0,
745+ DP_SEC_MPG_ENABLE, 0,
746+ DP_SEC_STREAM_ENABLE, 0);
747+
748+ /* this register shared with audio info frame.
749+ * therefore we need to keep master enabled
750+ * if at least one of the fields is not 0 */
751+ value = REG_READ(DP_SEC_CNTL);
752+ if (value)
753+ REG_UPDATE(DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, 1);
754+
755+}
756+
757+void enc1_stream_encoder_dp_blank(
758+ struct stream_encoder *enc)
759+{
760+ struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
761+ uint32_t retries = 0;
762+ uint32_t reg1 = 0;
763+ uint32_t max_retries = DP_BLANK_MAX_RETRY * 10;
764+
765+ /* Note: For CZ, we are changing driver default to disable
766+ * stream deferred to next VBLANK. If results are positive, we
767+ * will make the same change to all DCE versions. There are a
768+ * handful of panels that cannot handle disable stream at
769+ * HBLANK and will result in a white line flash across the
770+ * screen on stream disable.
771+ */
772+ REG_GET(DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, &reg1);
773+ if ((reg1 & 0x1) == 0)
774+ /*stream not enabled*/
775+ return;
776+ /* Specify the video stream disable point
777+ * (2 = start of the next vertical blank)
778+ */
779+ REG_UPDATE(DP_VID_STREAM_CNTL, DP_VID_STREAM_DIS_DEFER, 2);
780+ /* Larger delay to wait until VBLANK - use max retry of
781+ * 10us*3000=30ms. This covers 16.6ms of typical 60 Hz mode +
782+ * a little more because we may not trust delay accuracy.
783+ */
784+ max_retries = DP_BLANK_MAX_RETRY * 150;
785+
786+ /* disable DP stream */
787+ REG_UPDATE(DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, 0);
788+
789+ /* the encoder stops sending the video stream
790+ * at the start of the vertical blanking.
791+ * Poll for DP_VID_STREAM_STATUS == 0
792+ */
793+
794+ REG_WAIT(DP_VID_STREAM_CNTL, DP_VID_STREAM_STATUS,
795+ 0,
796+ 10, max_retries);
797+
798+ ASSERT(retries <= max_retries);
799+
800+ /* Tell the DP encoder to ignore timing from CRTC, must be done after
801+ * the polling. If we set DP_STEER_FIFO_RESET before DP stream blank is
802+ * complete, stream status will be stuck in video stream enabled state,
803+ * i.e. DP_VID_STREAM_STATUS stuck at 1.
804+ */
805+
806+ REG_UPDATE(DP_STEER_FIFO, DP_STEER_FIFO_RESET, true);
807+}
808+
809+/* output video stream to link encoder */
810+void enc1_stream_encoder_dp_unblank(
811+ struct stream_encoder *enc,
812+ const struct encoder_unblank_param *param)
813+{
814+ struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
815+
816+ if (param->link_settings.link_rate != LINK_RATE_UNKNOWN) {
817+ uint32_t n_vid = 0x8000;
818+ uint32_t m_vid;
819+
820+ /* M / N = Fstream / Flink
821+ * m_vid / n_vid = pixel rate / link rate
822+ */
823+
824+ uint64_t m_vid_l = n_vid;
825+
826+ m_vid_l *= param->pixel_clk_khz;
827+ m_vid_l = div_u64(m_vid_l,
828+ param->link_settings.link_rate
829+ * LINK_RATE_REF_FREQ_IN_KHZ);
830+
831+ m_vid = (uint32_t) m_vid_l;
832+
833+ /* enable auto measurement */
834+
835+ REG_UPDATE(DP_VID_TIMING, DP_VID_M_N_GEN_EN, 0);
836+
837+ /* auto measurement need 1 full 0x8000 symbol cycle to kick in,
838+ * therefore program initial value for Mvid and Nvid
839+ */
840+
841+ REG_UPDATE(DP_VID_N, DP_VID_N, n_vid);
842+
843+ REG_UPDATE(DP_VID_M, DP_VID_M, m_vid);
844+
845+ REG_UPDATE(DP_VID_TIMING, DP_VID_M_N_GEN_EN, 1);
846+ }
847+
848+ /* set DIG_START to 0x1 to resync FIFO */
849+
850+ REG_UPDATE(DIG_FE_CNTL, DIG_START, 1);
851+
852+ /* switch DP encoder to CRTC data */
853+
854+ REG_UPDATE(DP_STEER_FIFO, DP_STEER_FIFO_RESET, 0);
855+
856+ /* wait 100us for DIG/DP logic to prime
857+ * (i.e. a few video lines)
858+ */
859+ udelay(100);
860+
861+ /* the hardware would start sending video at the start of the next DP
862+ * frame (i.e. rising edge of the vblank).
863+ * NOTE: We used to program DP_VID_STREAM_DIS_DEFER = 2 here, but this
864+ * register has no effect on enable transition! HW always guarantees
865+ * VID_STREAM enable at start of next frame, and this is not
866+ * programmable
867+ */
868+
869+ REG_UPDATE(DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, true);
870+}
871+
872+void enc1_stream_encoder_set_avmute(
873+ struct stream_encoder *enc,
874+ bool enable)
875+{
876+ struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
877+ unsigned int value = enable ? 1 : 0;
878+
879+ REG_UPDATE(HDMI_GC, HDMI_GC_AVMUTE, value);
880+}
881+
882+
883+#define DP_SEC_AUD_N__DP_SEC_AUD_N__DEFAULT 0x8000
884+#define DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE__AUTO_CALC 1
885+
886+#include "include/audio_types.h"
887+
888+/**
889+* speakersToChannels
890+*
891+* @brief
892+* translate speakers to channels
893+*
894+* FL - Front Left
895+* FR - Front Right
896+* RL - Rear Left
897+* RR - Rear Right
898+* RC - Rear Center
899+* FC - Front Center
900+* FLC - Front Left Center
901+* FRC - Front Right Center
902+* RLC - Rear Left Center
903+* RRC - Rear Right Center
904+* LFE - Low Freq Effect
905+*
906+* FC
907+* FLC FRC
908+* FL FR
909+*
910+* LFE
911+* ()
912+*
913+*
914+* RL RR
915+* RLC RRC
916+* RC
917+*
918+* ch 8 7 6 5 4 3 2 1
919+* 0b00000011 - - - - - - FR FL
920+* 0b00000111 - - - - - LFE FR FL
921+* 0b00001011 - - - - FC - FR FL
922+* 0b00001111 - - - - FC LFE FR FL
923+* 0b00010011 - - - RC - - FR FL
924+* 0b00010111 - - - RC - LFE FR FL
925+* 0b00011011 - - - RC FC - FR FL
926+* 0b00011111 - - - RC FC LFE FR FL
927+* 0b00110011 - - RR RL - - FR FL
928+* 0b00110111 - - RR RL - LFE FR FL
929+* 0b00111011 - - RR RL FC - FR FL
930+* 0b00111111 - - RR RL FC LFE FR FL
931+* 0b01110011 - RC RR RL - - FR FL
932+* 0b01110111 - RC RR RL - LFE FR FL
933+* 0b01111011 - RC RR RL FC - FR FL
934+* 0b01111111 - RC RR RL FC LFE FR FL
935+* 0b11110011 RRC RLC RR RL - - FR FL
936+* 0b11110111 RRC RLC RR RL - LFE FR FL
937+* 0b11111011 RRC RLC RR RL FC - FR FL
938+* 0b11111111 RRC RLC RR RL FC LFE FR FL
939+* 0b11000011 FRC FLC - - - - FR FL
940+* 0b11000111 FRC FLC - - - LFE FR FL
941+* 0b11001011 FRC FLC - - FC - FR FL
942+* 0b11001111 FRC FLC - - FC LFE FR FL
943+* 0b11010011 FRC FLC - RC - - FR FL
944+* 0b11010111 FRC FLC - RC - LFE FR FL
945+* 0b11011011 FRC FLC - RC FC - FR FL
946+* 0b11011111 FRC FLC - RC FC LFE FR FL
947+* 0b11110011 FRC FLC RR RL - - FR FL
948+* 0b11110111 FRC FLC RR RL - LFE FR FL
949+* 0b11111011 FRC FLC RR RL FC - FR FL
950+* 0b11111111 FRC FLC RR RL FC LFE FR FL
951+*
952+* @param
953+* speakers - speaker information as it comes from CEA audio block
954+*/
955+/* translate speakers to channels */
956+
957+union audio_cea_channels {
958+ uint8_t all;
959+ struct audio_cea_channels_bits {
960+ uint32_t FL:1;
961+ uint32_t FR:1;
962+ uint32_t LFE:1;
963+ uint32_t FC:1;
964+ uint32_t RL_RC:1;
965+ uint32_t RR:1;
966+ uint32_t RC_RLC_FLC:1;
967+ uint32_t RRC_FRC:1;
968+ } channels;
969+};
970+
971+struct audio_clock_info {
972+ /* pixel clock frequency*/
973+ uint32_t pixel_clock_in_10khz;
974+ /* N - 32KHz audio */
975+ uint32_t n_32khz;
976+ /* CTS - 32KHz audio*/
977+ uint32_t cts_32khz;
978+ uint32_t n_44khz;
979+ uint32_t cts_44khz;
980+ uint32_t n_48khz;
981+ uint32_t cts_48khz;
982+};
983+
984+/* 25.2MHz/1.001*/
985+/* 25.2MHz/1.001*/
986+/* 25.2MHz*/
987+/* 27MHz */
988+/* 27MHz*1.001*/
989+/* 27MHz*1.001*/
990+/* 54MHz*/
991+/* 54MHz*1.001*/
992+/* 74.25MHz/1.001*/
993+/* 74.25MHz*/
994+/* 148.5MHz/1.001*/
995+/* 148.5MHz*/
996+
997+static const struct audio_clock_info audio_clock_info_table[16] = {
998+ {2517, 4576, 28125, 7007, 31250, 6864, 28125},
999+ {2518, 4576, 28125, 7007, 31250, 6864, 28125},
1000+ {2520, 4096, 25200, 6272, 28000, 6144, 25200},
1001+ {2700, 4096, 27000, 6272, 30000, 6144, 27000},
1002+ {2702, 4096, 27027, 6272, 30030, 6144, 27027},
1003+ {2703, 4096, 27027, 6272, 30030, 6144, 27027},
1004+ {5400, 4096, 54000, 6272, 60000, 6144, 54000},
1005+ {5405, 4096, 54054, 6272, 60060, 6144, 54054},
1006+ {7417, 11648, 210937, 17836, 234375, 11648, 140625},
1007+ {7425, 4096, 74250, 6272, 82500, 6144, 74250},
1008+ {14835, 11648, 421875, 8918, 234375, 5824, 140625},
1009+ {14850, 4096, 148500, 6272, 165000, 6144, 148500},
1010+ {29670, 5824, 421875, 4459, 234375, 5824, 281250},
1011+ {29700, 3072, 222750, 4704, 247500, 5120, 247500},
1012+ {59340, 5824, 843750, 8918, 937500, 5824, 562500},
1013+ {59400, 3072, 445500, 9408, 990000, 6144, 594000}
1014+};
1015+
1016+static const struct audio_clock_info audio_clock_info_table_36bpc[14] = {
1017+ {2517, 9152, 84375, 7007, 48875, 9152, 56250},
1018+ {2518, 9152, 84375, 7007, 48875, 9152, 56250},
1019+ {2520, 4096, 37800, 6272, 42000, 6144, 37800},
1020+ {2700, 4096, 40500, 6272, 45000, 6144, 40500},
1021+ {2702, 8192, 81081, 6272, 45045, 8192, 54054},
1022+ {2703, 8192, 81081, 6272, 45045, 8192, 54054},
1023+ {5400, 4096, 81000, 6272, 90000, 6144, 81000},
1024+ {5405, 4096, 81081, 6272, 90090, 6144, 81081},
1025+ {7417, 11648, 316406, 17836, 351562, 11648, 210937},
1026+ {7425, 4096, 111375, 6272, 123750, 6144, 111375},
1027+ {14835, 11648, 632812, 17836, 703125, 11648, 421875},
1028+ {14850, 4096, 222750, 6272, 247500, 6144, 222750},
1029+ {29670, 5824, 632812, 8918, 703125, 5824, 421875},
1030+ {29700, 4096, 445500, 4704, 371250, 5120, 371250}
1031+};
1032+
1033+static const struct audio_clock_info audio_clock_info_table_48bpc[14] = {
1034+ {2517, 4576, 56250, 7007, 62500, 6864, 56250},
1035+ {2518, 4576, 56250, 7007, 62500, 6864, 56250},
1036+ {2520, 4096, 50400, 6272, 56000, 6144, 50400},
1037+ {2700, 4096, 54000, 6272, 60000, 6144, 54000},
1038+ {2702, 4096, 54054, 6267, 60060, 8192, 54054},
1039+ {2703, 4096, 54054, 6272, 60060, 8192, 54054},
1040+ {5400, 4096, 108000, 6272, 120000, 6144, 108000},
1041+ {5405, 4096, 108108, 6272, 120120, 6144, 108108},
1042+ {7417, 11648, 421875, 17836, 468750, 11648, 281250},
1043+ {7425, 4096, 148500, 6272, 165000, 6144, 148500},
1044+ {14835, 11648, 843750, 8918, 468750, 11648, 281250},
1045+ {14850, 4096, 297000, 6272, 330000, 6144, 297000},
1046+ {29670, 5824, 843750, 4459, 468750, 5824, 562500},
1047+ {29700, 3072, 445500, 4704, 495000, 5120, 495000}
1048+
1049+
1050+};
1051+
1052+static union audio_cea_channels speakers_to_channels(
1053+ struct audio_speaker_flags speaker_flags)
1054+{
1055+ union audio_cea_channels cea_channels = {0};
1056+
1057+ /* these are one to one */
1058+ cea_channels.channels.FL = speaker_flags.FL_FR;
1059+ cea_channels.channels.FR = speaker_flags.FL_FR;
1060+ cea_channels.channels.LFE = speaker_flags.LFE;
1061+ cea_channels.channels.FC = speaker_flags.FC;
1062+
1063+ /* if Rear Left and Right exist move RC speaker to channel 7
1064+ * otherwise to channel 5
1065+ */
1066+ if (speaker_flags.RL_RR) {
1067+ cea_channels.channels.RL_RC = speaker_flags.RL_RR;
1068+ cea_channels.channels.RR = speaker_flags.RL_RR;
1069+ cea_channels.channels.RC_RLC_FLC = speaker_flags.RC;
1070+ } else {
1071+ cea_channels.channels.RL_RC = speaker_flags.RC;
1072+ }
1073+
1074+ /* FRONT Left Right Center and REAR Left Right Center are exclusive */
1075+ if (speaker_flags.FLC_FRC) {
1076+ cea_channels.channels.RC_RLC_FLC = speaker_flags.FLC_FRC;
1077+ cea_channels.channels.RRC_FRC = speaker_flags.FLC_FRC;
1078+ } else {
1079+ cea_channels.channels.RC_RLC_FLC = speaker_flags.RLC_RRC;
1080+ cea_channels.channels.RRC_FRC = speaker_flags.RLC_RRC;
1081+ }
1082+
1083+ return cea_channels;
1084+}
1085+
1086+static uint32_t calc_max_audio_packets_per_line(
1087+ const struct audio_crtc_info *crtc_info)
1088+{
1089+ uint32_t max_packets_per_line;
1090+
1091+ max_packets_per_line =
1092+ crtc_info->h_total - crtc_info->h_active;
1093+
1094+ if (crtc_info->pixel_repetition)
1095+ max_packets_per_line *= crtc_info->pixel_repetition;
1096+
1097+ /* for other hdmi features */
1098+ max_packets_per_line -= 58;
1099+ /* for Control Period */
1100+ max_packets_per_line -= 16;
1101+ /* Number of Audio Packets per Line */
1102+ max_packets_per_line /= 32;
1103+
1104+ return max_packets_per_line;
1105+}
1106+
1107+static void get_audio_clock_info(
1108+ enum dc_color_depth color_depth,
1109+ uint32_t crtc_pixel_clock_in_khz,
1110+ uint32_t actual_pixel_clock_in_khz,
1111+ struct audio_clock_info *audio_clock_info)
1112+{
1113+ const struct audio_clock_info *clock_info;
1114+ uint32_t index;
1115+ uint32_t crtc_pixel_clock_in_10khz = crtc_pixel_clock_in_khz / 10;
1116+ uint32_t audio_array_size;
1117+
1118+ switch (color_depth) {
1119+ case COLOR_DEPTH_161616:
1120+ clock_info = audio_clock_info_table_48bpc;
1121+ audio_array_size = ARRAY_SIZE(
1122+ audio_clock_info_table_48bpc);
1123+ break;
1124+ case COLOR_DEPTH_121212:
1125+ clock_info = audio_clock_info_table_36bpc;
1126+ audio_array_size = ARRAY_SIZE(
1127+ audio_clock_info_table_36bpc);
1128+ break;
1129+ default:
1130+ clock_info = audio_clock_info_table;
1131+ audio_array_size = ARRAY_SIZE(
1132+ audio_clock_info_table);
1133+ break;
1134+ }
1135+
1136+ if (clock_info != NULL) {
1137+ /* search for exact pixel clock in table */
1138+ for (index = 0; index < audio_array_size; index++) {
1139+ if (clock_info[index].pixel_clock_in_10khz >
1140+ crtc_pixel_clock_in_10khz)
1141+ break; /* not match */
1142+ else if (clock_info[index].pixel_clock_in_10khz ==
1143+ crtc_pixel_clock_in_10khz) {
1144+ /* match found */
1145+ *audio_clock_info = clock_info[index];
1146+ return;
1147+ }
1148+ }
1149+ }
1150+
1151+ /* not found */
1152+ if (actual_pixel_clock_in_khz == 0)
1153+ actual_pixel_clock_in_khz = crtc_pixel_clock_in_khz;
1154+
1155+ /* See HDMI spec the table entry under
1156+ * pixel clock of "Other". */
1157+ audio_clock_info->pixel_clock_in_10khz =
1158+ actual_pixel_clock_in_khz / 10;
1159+ audio_clock_info->cts_32khz = actual_pixel_clock_in_khz;
1160+ audio_clock_info->cts_44khz = actual_pixel_clock_in_khz;
1161+ audio_clock_info->cts_48khz = actual_pixel_clock_in_khz;
1162+
1163+ audio_clock_info->n_32khz = 4096;
1164+ audio_clock_info->n_44khz = 6272;
1165+ audio_clock_info->n_48khz = 6144;
1166+}
1167+
1168+static void enc1_se_audio_setup(
1169+ struct stream_encoder *enc,
1170+ unsigned int az_inst,
1171+ struct audio_info *audio_info)
1172+{
1173+ struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
1174+
1175+ uint32_t speakers = 0;
1176+ uint32_t channels = 0;
1177+
1178+ ASSERT(audio_info);
1179+ if (audio_info == NULL)
1180+ /* This should not happen.it does so we don't get BSOD*/
1181+ return;
1182+
1183+ speakers = audio_info->flags.info.ALLSPEAKERS;
1184+ channels = speakers_to_channels(audio_info->flags.speaker_flags).all;
1185+
1186+ /* setup the audio stream source select (audio -> dig mapping) */
1187+ REG_SET(AFMT_AUDIO_SRC_CONTROL, 0, AFMT_AUDIO_SRC_SELECT, az_inst);
1188+
1189+ /* Channel allocation */
1190+ REG_UPDATE(AFMT_AUDIO_PACKET_CONTROL2, AFMT_AUDIO_CHANNEL_ENABLE, channels);
1191+}
1192+
1193+static void enc1_se_setup_hdmi_audio(
1194+ struct stream_encoder *enc,
1195+ const struct audio_crtc_info *crtc_info)
1196+{
1197+ struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
1198+
1199+ struct audio_clock_info audio_clock_info = {0};
1200+ uint32_t max_packets_per_line;
1201+
1202+ /* For now still do calculation, although this field is ignored when
1203+ * above HDMI_PACKET_GEN_VERSION set to 1
1204+ */
1205+ max_packets_per_line = calc_max_audio_packets_per_line(crtc_info);
1206+
1207+ /* HDMI_AUDIO_PACKET_CONTROL */
1208+ REG_UPDATE_2(HDMI_AUDIO_PACKET_CONTROL,
1209+ HDMI_AUDIO_PACKETS_PER_LINE, max_packets_per_line,
1210+ HDMI_AUDIO_DELAY_EN, 1);
1211+
1212+ /* AFMT_AUDIO_PACKET_CONTROL */
1213+ REG_UPDATE(AFMT_AUDIO_PACKET_CONTROL, AFMT_60958_CS_UPDATE, 1);
1214+
1215+ /* AFMT_AUDIO_PACKET_CONTROL2 */
1216+ REG_UPDATE_2(AFMT_AUDIO_PACKET_CONTROL2,
1217+ AFMT_AUDIO_LAYOUT_OVRD, 0,
1218+ AFMT_60958_OSF_OVRD, 0);
1219+
1220+ /* HDMI_ACR_PACKET_CONTROL */
1221+ REG_UPDATE_3(HDMI_ACR_PACKET_CONTROL,
1222+ HDMI_ACR_AUTO_SEND, 1,
1223+ HDMI_ACR_SOURCE, 0,
1224+ HDMI_ACR_AUDIO_PRIORITY, 0);
1225+
1226+ /* Program audio clock sample/regeneration parameters */
1227+ get_audio_clock_info(crtc_info->color_depth,
1228+ crtc_info->requested_pixel_clock,
1229+ crtc_info->calculated_pixel_clock,
1230+ &audio_clock_info);
1231+ DC_LOG_HW_AUDIO(
1232+ "\n%s:Input::requested_pixel_clock = %d" \
1233+ "calculated_pixel_clock = %d \n", __func__, \
1234+ crtc_info->requested_pixel_clock, \
1235+ crtc_info->calculated_pixel_clock);
1236+
1237+ /* HDMI_ACR_32_0__HDMI_ACR_CTS_32_MASK */
1238+ REG_UPDATE(HDMI_ACR_32_0, HDMI_ACR_CTS_32, audio_clock_info.cts_32khz);
1239+
1240+ /* HDMI_ACR_32_1__HDMI_ACR_N_32_MASK */
1241+ REG_UPDATE(HDMI_ACR_32_1, HDMI_ACR_N_32, audio_clock_info.n_32khz);
1242+
1243+ /* HDMI_ACR_44_0__HDMI_ACR_CTS_44_MASK */
1244+ REG_UPDATE(HDMI_ACR_44_0, HDMI_ACR_CTS_44, audio_clock_info.cts_44khz);
1245+
1246+ /* HDMI_ACR_44_1__HDMI_ACR_N_44_MASK */
1247+ REG_UPDATE(HDMI_ACR_44_1, HDMI_ACR_N_44, audio_clock_info.n_44khz);
1248+
1249+ /* HDMI_ACR_48_0__HDMI_ACR_CTS_48_MASK */
1250+ REG_UPDATE(HDMI_ACR_48_0, HDMI_ACR_CTS_48, audio_clock_info.cts_48khz);
1251+
1252+ /* HDMI_ACR_48_1__HDMI_ACR_N_48_MASK */
1253+ REG_UPDATE(HDMI_ACR_48_1, HDMI_ACR_N_48, audio_clock_info.n_48khz);
1254+
1255+ /* Video driver cannot know in advance which sample rate will
1256+ * be used by HD Audio driver
1257+ * HDMI_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE field is
1258+ * programmed below in interruppt callback
1259+ */
1260+
1261+ /* AFMT_60958_0__AFMT_60958_CS_CHANNEL_NUMBER_L_MASK &
1262+ * AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY_MASK
1263+ */
1264+ REG_UPDATE_2(AFMT_60958_0,
1265+ AFMT_60958_CS_CHANNEL_NUMBER_L, 1,
1266+ AFMT_60958_CS_CLOCK_ACCURACY, 0);
1267+
1268+ /* AFMT_60958_1 AFMT_60958_CS_CHALNNEL_NUMBER_R */
1269+ REG_UPDATE(AFMT_60958_1, AFMT_60958_CS_CHANNEL_NUMBER_R, 2);
1270+
1271+ /* AFMT_60958_2 now keep this settings until
1272+ * Programming guide comes out
1273+ */
1274+ REG_UPDATE_6(AFMT_60958_2,
1275+ AFMT_60958_CS_CHANNEL_NUMBER_2, 3,
1276+ AFMT_60958_CS_CHANNEL_NUMBER_3, 4,
1277+ AFMT_60958_CS_CHANNEL_NUMBER_4, 5,
1278+ AFMT_60958_CS_CHANNEL_NUMBER_5, 6,
1279+ AFMT_60958_CS_CHANNEL_NUMBER_6, 7,
1280+ AFMT_60958_CS_CHANNEL_NUMBER_7, 8);
1281+}
1282+
1283+static void enc1_se_setup_dp_audio(
1284+ struct stream_encoder *enc)
1285+{
1286+ struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
1287+
1288+ /* --- DP Audio packet configurations --- */
1289+
1290+ /* ATP Configuration */
1291+ REG_SET(DP_SEC_AUD_N, 0,
1292+ DP_SEC_AUD_N, DP_SEC_AUD_N__DP_SEC_AUD_N__DEFAULT);
1293+
1294+ /* Async/auto-calc timestamp mode */
1295+ REG_SET(DP_SEC_TIMESTAMP, 0, DP_SEC_TIMESTAMP_MODE,
1296+ DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE__AUTO_CALC);
1297+
1298+ /* --- The following are the registers
1299+ * copied from the SetupHDMI ---
1300+ */
1301+
1302+ /* AFMT_AUDIO_PACKET_CONTROL */
1303+ REG_UPDATE(AFMT_AUDIO_PACKET_CONTROL, AFMT_60958_CS_UPDATE, 1);
1304+
1305+ /* AFMT_AUDIO_PACKET_CONTROL2 */
1306+ /* Program the ATP and AIP next */
1307+ REG_UPDATE_2(AFMT_AUDIO_PACKET_CONTROL2,
1308+ AFMT_AUDIO_LAYOUT_OVRD, 0,
1309+ AFMT_60958_OSF_OVRD, 0);
1310+
1311+ /* AFMT_INFOFRAME_CONTROL0 */
1312+ REG_UPDATE(AFMT_INFOFRAME_CONTROL0, AFMT_AUDIO_INFO_UPDATE, 1);
1313+
1314+ /* AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY_MASK */
1315+ REG_UPDATE(AFMT_60958_0, AFMT_60958_CS_CLOCK_ACCURACY, 0);
1316+}
1317+
1318+static void enc1_se_enable_audio_clock(
1319+ struct stream_encoder *enc,
1320+ bool enable)
1321+{
1322+ struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
1323+
1324+ if (REG(AFMT_CNTL) == 0)
1325+ return; /* DCE8/10 does not have this register */
1326+
1327+ REG_UPDATE(AFMT_CNTL, AFMT_AUDIO_CLOCK_EN, !!enable);
1328+
1329+ /* wait for AFMT clock to turn on,
1330+ * expectation: this should complete in 1-2 reads
1331+ *
1332+ * REG_WAIT(AFMT_CNTL, AFMT_AUDIO_CLOCK_ON, !!enable, 1, 10);
1333+ *
1334+ * TODO: wait for clock_on does not work well. May need HW
1335+ * program sequence. But audio seems work normally even without wait
1336+ * for clock_on status change
1337+ */
1338+}
1339+
1340+static void enc1_se_enable_dp_audio(
1341+ struct stream_encoder *enc)
1342+{
1343+ struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
1344+
1345+ /* Enable Audio packets */
1346+ REG_UPDATE(DP_SEC_CNTL, DP_SEC_ASP_ENABLE, 1);
1347+
1348+ /* Program the ATP and AIP next */
1349+ REG_UPDATE_2(DP_SEC_CNTL,
1350+ DP_SEC_ATP_ENABLE, 1,
1351+ DP_SEC_AIP_ENABLE, 1);
1352+
1353+ /* Program STREAM_ENABLE after all the other enables. */
1354+ REG_UPDATE(DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, 1);
1355+}
1356+
1357+static void enc1_se_disable_dp_audio(
1358+ struct stream_encoder *enc)
1359+{
1360+ struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
1361+ uint32_t value = 0;
1362+
1363+ /* Disable Audio packets */
1364+ REG_UPDATE_5(DP_SEC_CNTL,
1365+ DP_SEC_ASP_ENABLE, 0,
1366+ DP_SEC_ATP_ENABLE, 0,
1367+ DP_SEC_AIP_ENABLE, 0,
1368+ DP_SEC_ACM_ENABLE, 0,
1369+ DP_SEC_STREAM_ENABLE, 0);
1370+
1371+ /* This register shared with encoder info frame. Therefore we need to
1372+ * keep master enabled if at least on of the fields is not 0
1373+ */
1374+ value = REG_READ(DP_SEC_CNTL);
1375+ if (value != 0)
1376+ REG_UPDATE(DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, 1);
1377+
1378+}
1379+
1380+void enc1_se_audio_mute_control(
1381+ struct stream_encoder *enc,
1382+ bool mute)
1383+{
1384+ struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
1385+
1386+ REG_UPDATE(AFMT_AUDIO_PACKET_CONTROL, AFMT_AUDIO_SAMPLE_SEND, !mute);
1387+}
1388+
1389+void enc1_se_dp_audio_setup(
1390+ struct stream_encoder *enc,
1391+ unsigned int az_inst,
1392+ struct audio_info *info)
1393+{
1394+ enc1_se_audio_setup(enc, az_inst, info);
1395+}
1396+
1397+void enc1_se_dp_audio_enable(
1398+ struct stream_encoder *enc)
1399+{
1400+ enc1_se_enable_audio_clock(enc, true);
1401+ enc1_se_setup_dp_audio(enc);
1402+ enc1_se_enable_dp_audio(enc);
1403+}
1404+
1405+void enc1_se_dp_audio_disable(
1406+ struct stream_encoder *enc)
1407+{
1408+ enc1_se_disable_dp_audio(enc);
1409+ enc1_se_enable_audio_clock(enc, false);
1410+}
1411+
1412+void enc1_se_hdmi_audio_setup(
1413+ struct stream_encoder *enc,
1414+ unsigned int az_inst,
1415+ struct audio_info *info,
1416+ struct audio_crtc_info *audio_crtc_info)
1417+{
1418+ enc1_se_enable_audio_clock(enc, true);
1419+ enc1_se_setup_hdmi_audio(enc, audio_crtc_info);
1420+ enc1_se_audio_setup(enc, az_inst, info);
1421+}
1422+
1423+void enc1_se_hdmi_audio_disable(
1424+ struct stream_encoder *enc)
1425+{
1426+ enc1_se_enable_audio_clock(enc, false);
1427+}
1428+
1429+
1430+void enc1_setup_stereo_sync(
1431+ struct stream_encoder *enc,
1432+ int tg_inst, bool enable)
1433+{
1434+ struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
1435+ REG_UPDATE(DIG_FE_CNTL, DIG_STEREOSYNC_SELECT, tg_inst);
1436+ REG_UPDATE(DIG_FE_CNTL, DIG_STEREOSYNC_GATE_EN, !enable);
1437+}
1438+
1439+
1440+static const struct stream_encoder_funcs dcn10_str_enc_funcs = {
1441+ .dp_set_stream_attribute =
1442+ enc1_stream_encoder_dp_set_stream_attribute,
1443+ .hdmi_set_stream_attribute =
1444+ enc1_stream_encoder_hdmi_set_stream_attribute,
1445+ .dvi_set_stream_attribute =
1446+ enc1_stream_encoder_dvi_set_stream_attribute,
1447+ .set_mst_bandwidth =
1448+ enc1_stream_encoder_set_mst_bandwidth,
1449+ .update_hdmi_info_packets =
1450+ enc1_stream_encoder_update_hdmi_info_packets,
1451+ .stop_hdmi_info_packets =
1452+ enc1_stream_encoder_stop_hdmi_info_packets,
1453+ .update_dp_info_packets =
1454+ enc1_stream_encoder_update_dp_info_packets,
1455+ .stop_dp_info_packets =
1456+ enc1_stream_encoder_stop_dp_info_packets,
1457+ .dp_blank =
1458+ enc1_stream_encoder_dp_blank,
1459+ .dp_unblank =
1460+ enc1_stream_encoder_dp_unblank,
1461+ .audio_mute_control = enc1_se_audio_mute_control,
1462+
1463+ .dp_audio_setup = enc1_se_dp_audio_setup,
1464+ .dp_audio_enable = enc1_se_dp_audio_enable,
1465+ .dp_audio_disable = enc1_se_dp_audio_disable,
1466+
1467+ .hdmi_audio_setup = enc1_se_hdmi_audio_setup,
1468+ .hdmi_audio_disable = enc1_se_hdmi_audio_disable,
1469+ .setup_stereo_sync = enc1_setup_stereo_sync,
1470+ .set_avmute = enc1_stream_encoder_set_avmute,
1471+};
1472+
1473+void dcn10_stream_encoder_construct(
1474+ struct dcn10_stream_encoder *enc1,
1475+ struct dc_context *ctx,
1476+ struct dc_bios *bp,
1477+ enum engine_id eng_id,
1478+ const struct dcn10_stream_enc_registers *regs,
1479+ const struct dcn10_stream_encoder_shift *se_shift,
1480+ const struct dcn10_stream_encoder_mask *se_mask)
1481+{
1482+ enc1->base.funcs = &dcn10_str_enc_funcs;
1483+ enc1->base.ctx = ctx;
1484+ enc1->base.id = eng_id;
1485+ enc1->base.bp = bp;
1486+ enc1->regs = regs;
1487+ enc1->se_shift = se_shift;
1488+ enc1->se_mask = se_mask;
1489+}
1490+
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h+524−0
@@ -0,0 +1,524 @@
1+/*
2+ * Copyright 2012-15 Advanced Micro Devices, Inc.
3+ *
4+ * Permission is hereby granted, free of charge, to any person obtaining a
5+ * copy of this software and associated documentation files (the "Software"),
6+ * to deal in the Software without restriction, including without limitation
7+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8+ * and/or sell copies of the Software, and to permit persons to whom the
9+ * Software is furnished to do so, subject to the following conditions:
10+ *
11+ * The above copyright notice and this permission notice shall be included in
12+ * all copies or substantial portions of the Software.
13+ *
14+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20+ * OTHER DEALINGS IN THE SOFTWARE.
21+ *
22+ * Authors: AMD
23+ *
24+ */
25+
26+#ifndef __DC_STREAM_ENCODER_DCN10_H__
27+#define __DC_STREAM_ENCODER_DCN10_H__
28+
29+#include "stream_encoder.h"
30+
31+#define DCN10STRENC_FROM_STRENC(stream_encoder)\
32+ container_of(stream_encoder, struct dcn10_stream_encoder, base)
33+
34+#define SE_COMMON_DCN_REG_LIST(id) \
35+ SRI(AFMT_CNTL, DIG, id), \
36+ SRI(AFMT_GENERIC_0, DIG, id), \
37+ SRI(AFMT_GENERIC_1, DIG, id), \
38+ SRI(AFMT_GENERIC_2, DIG, id), \
39+ SRI(AFMT_GENERIC_3, DIG, id), \
40+ SRI(AFMT_GENERIC_4, DIG, id), \
41+ SRI(AFMT_GENERIC_5, DIG, id), \
42+ SRI(AFMT_GENERIC_6, DIG, id), \
43+ SRI(AFMT_GENERIC_7, DIG, id), \
44+ SRI(AFMT_GENERIC_HDR, DIG, id), \
45+ SRI(AFMT_INFOFRAME_CONTROL0, DIG, id), \
46+ SRI(AFMT_VBI_PACKET_CONTROL, DIG, id), \
47+ SRI(AFMT_VBI_PACKET_CONTROL1, DIG, id), \
48+ SRI(AFMT_AUDIO_PACKET_CONTROL, DIG, id), \
49+ SRI(AFMT_AUDIO_PACKET_CONTROL2, DIG, id), \
50+ SRI(AFMT_AUDIO_SRC_CONTROL, DIG, id), \
51+ SRI(AFMT_60958_0, DIG, id), \
52+ SRI(AFMT_60958_1, DIG, id), \
53+ SRI(AFMT_60958_2, DIG, id), \
54+ SRI(DIG_FE_CNTL, DIG, id), \
55+ SRI(HDMI_CONTROL, DIG, id), \
56+ SRI(HDMI_DB_CONTROL, DIG, id), \
57+ SRI(HDMI_GC, DIG, id), \
58+ SRI(HDMI_GENERIC_PACKET_CONTROL0, DIG, id), \
59+ SRI(HDMI_GENERIC_PACKET_CONTROL1, DIG, id), \
60+ SRI(HDMI_GENERIC_PACKET_CONTROL2, DIG, id), \
61+ SRI(HDMI_GENERIC_PACKET_CONTROL3, DIG, id), \
62+ SRI(HDMI_INFOFRAME_CONTROL0, DIG, id), \
63+ SRI(HDMI_INFOFRAME_CONTROL1, DIG, id), \
64+ SRI(HDMI_VBI_PACKET_CONTROL, DIG, id), \
65+ SRI(HDMI_AUDIO_PACKET_CONTROL, DIG, id),\
66+ SRI(HDMI_ACR_PACKET_CONTROL, DIG, id),\
67+ SRI(HDMI_ACR_32_0, DIG, id),\
68+ SRI(HDMI_ACR_32_1, DIG, id),\
69+ SRI(HDMI_ACR_44_0, DIG, id),\
70+ SRI(HDMI_ACR_44_1, DIG, id),\
71+ SRI(HDMI_ACR_48_0, DIG, id),\
72+ SRI(HDMI_ACR_48_1, DIG, id),\
73+ SRI(DP_DB_CNTL, DP, id), \
74+ SRI(DP_MSA_MISC, DP, id), \
75+ SRI(DP_MSA_COLORIMETRY, DP, id), \
76+ SRI(DP_MSA_TIMING_PARAM1, DP, id), \
77+ SRI(DP_MSA_TIMING_PARAM2, DP, id), \
78+ SRI(DP_MSA_TIMING_PARAM3, DP, id), \
79+ SRI(DP_MSA_TIMING_PARAM4, DP, id), \
80+ SRI(DP_MSE_RATE_CNTL, DP, id), \
81+ SRI(DP_MSE_RATE_UPDATE, DP, id), \
82+ SRI(DP_PIXEL_FORMAT, DP, id), \
83+ SRI(DP_SEC_CNTL, DP, id), \
84+ SRI(DP_STEER_FIFO, DP, id), \
85+ SRI(DP_VID_M, DP, id), \
86+ SRI(DP_VID_N, DP, id), \
87+ SRI(DP_VID_STREAM_CNTL, DP, id), \
88+ SRI(DP_VID_TIMING, DP, id), \
89+ SRI(DP_SEC_AUD_N, DP, id), \
90+ SRI(DP_SEC_TIMESTAMP, DP, id)
91+
92+#define SE_DCN_REG_LIST(id)\
93+ SE_COMMON_DCN_REG_LIST(id)
94+
95+
96+struct dcn10_stream_enc_registers {
97+ uint32_t AFMT_CNTL;
98+ uint32_t AFMT_AVI_INFO0;
99+ uint32_t AFMT_AVI_INFO1;
100+ uint32_t AFMT_AVI_INFO2;
101+ uint32_t AFMT_AVI_INFO3;
102+ uint32_t AFMT_GENERIC_0;
103+ uint32_t AFMT_GENERIC_1;
104+ uint32_t AFMT_GENERIC_2;
105+ uint32_t AFMT_GENERIC_3;
106+ uint32_t AFMT_GENERIC_4;
107+ uint32_t AFMT_GENERIC_5;
108+ uint32_t AFMT_GENERIC_6;
109+ uint32_t AFMT_GENERIC_7;
110+ uint32_t AFMT_GENERIC_HDR;
111+ uint32_t AFMT_INFOFRAME_CONTROL0;
112+ uint32_t AFMT_VBI_PACKET_CONTROL;
113+ uint32_t AFMT_VBI_PACKET_CONTROL1;
114+ uint32_t AFMT_AUDIO_PACKET_CONTROL;
115+ uint32_t AFMT_AUDIO_PACKET_CONTROL2;
116+ uint32_t AFMT_AUDIO_SRC_CONTROL;
117+ uint32_t AFMT_60958_0;
118+ uint32_t AFMT_60958_1;
119+ uint32_t AFMT_60958_2;
120+ uint32_t DIG_FE_CNTL;
121+ uint32_t DP_MSE_RATE_CNTL;
122+ uint32_t DP_MSE_RATE_UPDATE;
123+ uint32_t DP_PIXEL_FORMAT;
124+ uint32_t DP_SEC_CNTL;
125+ uint32_t DP_STEER_FIFO;
126+ uint32_t DP_VID_M;
127+ uint32_t DP_VID_N;
128+ uint32_t DP_VID_STREAM_CNTL;
129+ uint32_t DP_VID_TIMING;
130+ uint32_t DP_SEC_AUD_N;
131+ uint32_t DP_SEC_TIMESTAMP;
132+ uint32_t HDMI_CONTROL;
133+ uint32_t HDMI_GC;
134+ uint32_t HDMI_GENERIC_PACKET_CONTROL0;
135+ uint32_t HDMI_GENERIC_PACKET_CONTROL1;
136+ uint32_t HDMI_GENERIC_PACKET_CONTROL2;
137+ uint32_t HDMI_GENERIC_PACKET_CONTROL3;
138+ uint32_t HDMI_GENERIC_PACKET_CONTROL4;
139+ uint32_t HDMI_GENERIC_PACKET_CONTROL5;
140+ uint32_t HDMI_INFOFRAME_CONTROL0;
141+ uint32_t HDMI_INFOFRAME_CONTROL1;
142+ uint32_t HDMI_VBI_PACKET_CONTROL;
143+ uint32_t HDMI_AUDIO_PACKET_CONTROL;
144+ uint32_t HDMI_ACR_PACKET_CONTROL;
145+ uint32_t HDMI_ACR_32_0;
146+ uint32_t HDMI_ACR_32_1;
147+ uint32_t HDMI_ACR_44_0;
148+ uint32_t HDMI_ACR_44_1;
149+ uint32_t HDMI_ACR_48_0;
150+ uint32_t HDMI_ACR_48_1;
151+ uint32_t DP_DB_CNTL;
152+ uint32_t DP_MSA_MISC;
153+ uint32_t DP_MSA_COLORIMETRY;
154+ uint32_t DP_MSA_TIMING_PARAM1;
155+ uint32_t DP_MSA_TIMING_PARAM2;
156+ uint32_t DP_MSA_TIMING_PARAM3;
157+ uint32_t DP_MSA_TIMING_PARAM4;
158+ uint32_t HDMI_DB_CONTROL;
159+};
160+
161+
162+#define SE_SF(reg_name, field_name, post_fix)\
163+ .field_name = reg_name ## __ ## field_name ## post_fix
164+
165+#define SE_COMMON_MASK_SH_LIST_SOC_BASE(mask_sh)\
166+ SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC_INDEX, mask_sh),\
167+ SE_SF(DIG0_AFMT_GENERIC_HDR, AFMT_GENERIC_HB0, mask_sh),\
168+ SE_SF(DIG0_AFMT_GENERIC_HDR, AFMT_GENERIC_HB1, mask_sh),\
169+ SE_SF(DIG0_AFMT_GENERIC_HDR, AFMT_GENERIC_HB2, mask_sh),\
170+ SE_SF(DIG0_AFMT_GENERIC_HDR, AFMT_GENERIC_HB3, mask_sh),\
171+ SE_SF(DP0_DP_PIXEL_FORMAT, DP_PIXEL_ENCODING, mask_sh),\
172+ SE_SF(DP0_DP_PIXEL_FORMAT, DP_COMPONENT_DEPTH, mask_sh),\
173+ SE_SF(DIG0_HDMI_CONTROL, HDMI_PACKET_GEN_VERSION, mask_sh),\
174+ SE_SF(DIG0_HDMI_CONTROL, HDMI_KEEPOUT_MODE, mask_sh),\
175+ SE_SF(DIG0_HDMI_CONTROL, HDMI_DEEP_COLOR_ENABLE, mask_sh),\
176+ SE_SF(DIG0_HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, mask_sh),\
177+ SE_SF(DIG0_HDMI_CONTROL, HDMI_DATA_SCRAMBLE_EN, mask_sh),\
178+ SE_SF(DIG0_HDMI_VBI_PACKET_CONTROL, HDMI_GC_CONT, mask_sh),\
179+ SE_SF(DIG0_HDMI_VBI_PACKET_CONTROL, HDMI_GC_SEND, mask_sh),\
180+ SE_SF(DIG0_HDMI_VBI_PACKET_CONTROL, HDMI_NULL_SEND, mask_sh),\
181+ SE_SF(DIG0_HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_SEND, mask_sh),\
182+ SE_SF(DIG0_AFMT_INFOFRAME_CONTROL0, AFMT_AUDIO_INFO_UPDATE, mask_sh),\
183+ SE_SF(DIG0_HDMI_INFOFRAME_CONTROL1, HDMI_AUDIO_INFO_LINE, mask_sh),\
184+ SE_SF(DIG0_HDMI_GC, HDMI_GC_AVMUTE, mask_sh),\
185+ SE_SF(DP0_DP_MSE_RATE_CNTL, DP_MSE_RATE_X, mask_sh),\
186+ SE_SF(DP0_DP_MSE_RATE_CNTL, DP_MSE_RATE_Y, mask_sh),\
187+ SE_SF(DP0_DP_MSE_RATE_UPDATE, DP_MSE_RATE_UPDATE_PENDING, mask_sh),\
188+ SE_SF(DP0_DP_SEC_CNTL, DP_SEC_GSP0_ENABLE, mask_sh),\
189+ SE_SF(DP0_DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, mask_sh),\
190+ SE_SF(DP0_DP_SEC_CNTL, DP_SEC_GSP1_ENABLE, mask_sh),\
191+ SE_SF(DP0_DP_SEC_CNTL, DP_SEC_GSP2_ENABLE, mask_sh),\
192+ SE_SF(DP0_DP_SEC_CNTL, DP_SEC_GSP3_ENABLE, mask_sh),\
193+ SE_SF(DP0_DP_SEC_CNTL, DP_SEC_MPG_ENABLE, mask_sh),\
194+ SE_SF(DP0_DP_VID_STREAM_CNTL, DP_VID_STREAM_DIS_DEFER, mask_sh),\
195+ SE_SF(DP0_DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, mask_sh),\
196+ SE_SF(DP0_DP_VID_STREAM_CNTL, DP_VID_STREAM_STATUS, mask_sh),\
197+ SE_SF(DP0_DP_STEER_FIFO, DP_STEER_FIFO_RESET, mask_sh),\
198+ SE_SF(DP0_DP_VID_TIMING, DP_VID_M_N_GEN_EN, mask_sh),\
199+ SE_SF(DP0_DP_VID_N, DP_VID_N, mask_sh),\
200+ SE_SF(DP0_DP_VID_M, DP_VID_M, mask_sh),\
201+ SE_SF(DIG0_DIG_FE_CNTL, DIG_START, mask_sh),\
202+ SE_SF(DIG0_AFMT_AUDIO_SRC_CONTROL, AFMT_AUDIO_SRC_SELECT, mask_sh),\
203+ SE_SF(DIG0_AFMT_AUDIO_PACKET_CONTROL2, AFMT_AUDIO_CHANNEL_ENABLE, mask_sh),\
204+ SE_SF(DIG0_HDMI_AUDIO_PACKET_CONTROL, HDMI_AUDIO_PACKETS_PER_LINE, mask_sh),\
205+ SE_SF(DIG0_HDMI_AUDIO_PACKET_CONTROL, HDMI_AUDIO_DELAY_EN, mask_sh),\
206+ SE_SF(DIG0_AFMT_AUDIO_PACKET_CONTROL, AFMT_60958_CS_UPDATE, mask_sh),\
207+ SE_SF(DIG0_AFMT_AUDIO_PACKET_CONTROL2, AFMT_AUDIO_LAYOUT_OVRD, mask_sh),\
208+ SE_SF(DIG0_AFMT_AUDIO_PACKET_CONTROL2, AFMT_60958_OSF_OVRD, mask_sh),\
209+ SE_SF(DIG0_HDMI_ACR_PACKET_CONTROL, HDMI_ACR_AUTO_SEND, mask_sh),\
210+ SE_SF(DIG0_HDMI_ACR_PACKET_CONTROL, HDMI_ACR_SOURCE, mask_sh),\
211+ SE_SF(DIG0_HDMI_ACR_PACKET_CONTROL, HDMI_ACR_AUDIO_PRIORITY, mask_sh),\
212+ SE_SF(DIG0_HDMI_ACR_32_0, HDMI_ACR_CTS_32, mask_sh),\
213+ SE_SF(DIG0_HDMI_ACR_32_1, HDMI_ACR_N_32, mask_sh),\
214+ SE_SF(DIG0_HDMI_ACR_44_0, HDMI_ACR_CTS_44, mask_sh),\
215+ SE_SF(DIG0_HDMI_ACR_44_1, HDMI_ACR_N_44, mask_sh),\
216+ SE_SF(DIG0_HDMI_ACR_48_0, HDMI_ACR_CTS_48, mask_sh),\
217+ SE_SF(DIG0_HDMI_ACR_48_1, HDMI_ACR_N_48, mask_sh),\
218+ SE_SF(DIG0_AFMT_60958_0, AFMT_60958_CS_CHANNEL_NUMBER_L, mask_sh),\
219+ SE_SF(DIG0_AFMT_60958_0, AFMT_60958_CS_CLOCK_ACCURACY, mask_sh),\
220+ SE_SF(DIG0_AFMT_60958_1, AFMT_60958_CS_CHANNEL_NUMBER_R, mask_sh),\
221+ SE_SF(DIG0_AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_2, mask_sh),\
222+ SE_SF(DIG0_AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_3, mask_sh),\
223+ SE_SF(DIG0_AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_4, mask_sh),\
224+ SE_SF(DIG0_AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_5, mask_sh),\
225+ SE_SF(DIG0_AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_6, mask_sh),\
226+ SE_SF(DIG0_AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_7, mask_sh),\
227+ SE_SF(DP0_DP_SEC_AUD_N, DP_SEC_AUD_N, mask_sh),\
228+ SE_SF(DP0_DP_SEC_TIMESTAMP, DP_SEC_TIMESTAMP_MODE, mask_sh),\
229+ SE_SF(DP0_DP_SEC_CNTL, DP_SEC_ASP_ENABLE, mask_sh),\
230+ SE_SF(DP0_DP_SEC_CNTL, DP_SEC_ATP_ENABLE, mask_sh),\
231+ SE_SF(DP0_DP_SEC_CNTL, DP_SEC_AIP_ENABLE, mask_sh),\
232+ SE_SF(DP0_DP_SEC_CNTL, DP_SEC_ACM_ENABLE, mask_sh),\
233+ SE_SF(DIG0_AFMT_AUDIO_PACKET_CONTROL, AFMT_AUDIO_SAMPLE_SEND, mask_sh),\
234+ SE_SF(DIG0_AFMT_CNTL, AFMT_AUDIO_CLOCK_EN, mask_sh),\
235+ SE_SF(DIG0_HDMI_CONTROL, HDMI_CLOCK_CHANNEL_RATE, mask_sh),\
236+ SE_SF(DIG0_DIG_FE_CNTL, TMDS_PIXEL_ENCODING, mask_sh),\
237+ SE_SF(DIG0_DIG_FE_CNTL, TMDS_COLOR_FORMAT, mask_sh),\
238+ SE_SF(DIG0_DIG_FE_CNTL, DIG_STEREOSYNC_SELECT, mask_sh),\
239+ SE_SF(DIG0_DIG_FE_CNTL, DIG_STEREOSYNC_GATE_EN, mask_sh),\
240+ SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC_LOCK_STATUS, mask_sh),\
241+ SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC_CONFLICT, mask_sh),\
242+ SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC_CONFLICT_CLR, mask_sh),\
243+ SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC0_FRAME_UPDATE_PENDING, mask_sh),\
244+ SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC1_FRAME_UPDATE_PENDING, mask_sh),\
245+ SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC2_FRAME_UPDATE_PENDING, mask_sh),\
246+ SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC3_FRAME_UPDATE_PENDING, mask_sh),\
247+ SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC4_FRAME_UPDATE_PENDING, mask_sh),\
248+ SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC5_FRAME_UPDATE_PENDING, mask_sh),\
249+ SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC6_FRAME_UPDATE_PENDING, mask_sh),\
250+ SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC7_FRAME_UPDATE_PENDING, mask_sh),\
251+ SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC0_FRAME_UPDATE, mask_sh),\
252+ SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC1_FRAME_UPDATE, mask_sh),\
253+ SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC2_FRAME_UPDATE, mask_sh),\
254+ SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC3_FRAME_UPDATE, mask_sh),\
255+ SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC4_FRAME_UPDATE, mask_sh),\
256+ SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC5_FRAME_UPDATE, mask_sh),\
257+ SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC6_FRAME_UPDATE, mask_sh),\
258+ SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC7_FRAME_UPDATE, mask_sh),\
259+ SE_SF(DP0_DP_SEC_CNTL, DP_SEC_GSP4_ENABLE, mask_sh),\
260+ SE_SF(DP0_DP_SEC_CNTL, DP_SEC_GSP5_ENABLE, mask_sh),\
261+ SE_SF(DP0_DP_SEC_CNTL, DP_SEC_GSP6_ENABLE, mask_sh),\
262+ SE_SF(DP0_DP_SEC_CNTL, DP_SEC_GSP7_ENABLE, mask_sh),\
263+ SE_SF(DP0_DP_DB_CNTL, DP_DB_DISABLE, mask_sh),\
264+ SE_SF(DP0_DP_MSA_COLORIMETRY, DP_MSA_MISC0, mask_sh),\
265+ SE_SF(DP0_DP_MSA_TIMING_PARAM1, DP_MSA_HTOTAL, mask_sh),\
266+ SE_SF(DP0_DP_MSA_TIMING_PARAM1, DP_MSA_VTOTAL, mask_sh),\
267+ SE_SF(DP0_DP_MSA_TIMING_PARAM2, DP_MSA_HSTART, mask_sh),\
268+ SE_SF(DP0_DP_MSA_TIMING_PARAM2, DP_MSA_VSTART, mask_sh),\
269+ SE_SF(DP0_DP_MSA_TIMING_PARAM3, DP_MSA_HSYNCWIDTH, mask_sh),\
270+ SE_SF(DP0_DP_MSA_TIMING_PARAM3, DP_MSA_HSYNCPOLARITY, mask_sh),\
271+ SE_SF(DP0_DP_MSA_TIMING_PARAM3, DP_MSA_VSYNCWIDTH, mask_sh),\
272+ SE_SF(DP0_DP_MSA_TIMING_PARAM3, DP_MSA_VSYNCPOLARITY, mask_sh),\
273+ SE_SF(DP0_DP_MSA_TIMING_PARAM4, DP_MSA_HWIDTH, mask_sh),\
274+ SE_SF(DP0_DP_MSA_TIMING_PARAM4, DP_MSA_VHEIGHT, mask_sh),\
275+ SE_SF(DIG0_HDMI_DB_CONTROL, HDMI_DB_DISABLE, mask_sh),\
276+ SE_SF(DP0_DP_VID_TIMING, DP_VID_N_MUL, mask_sh)
277+
278+#define SE_COMMON_MASK_SH_LIST_SOC(mask_sh)\
279+ SE_COMMON_MASK_SH_LIST_SOC_BASE(mask_sh)
280+
281+#define SE_COMMON_MASK_SH_LIST_DCN10(mask_sh)\
282+ SE_COMMON_MASK_SH_LIST_SOC(mask_sh),\
283+ SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL0, HDMI_GENERIC0_CONT, mask_sh),\
284+ SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL0, HDMI_GENERIC0_SEND, mask_sh),\
285+ SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL0, HDMI_GENERIC0_LINE, mask_sh),\
286+ SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL0, HDMI_GENERIC1_CONT, mask_sh),\
287+ SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL0, HDMI_GENERIC1_SEND, mask_sh),\
288+ SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL0, HDMI_GENERIC1_LINE, mask_sh)
289+
290+
291+#define SE_REG_FIELD_LIST_DCN1_0(type) \
292+ type AFMT_GENERIC_INDEX;\
293+ type AFMT_GENERIC_HB0;\
294+ type AFMT_GENERIC_HB1;\
295+ type AFMT_GENERIC_HB2;\
296+ type AFMT_GENERIC_HB3;\
297+ type AFMT_GENERIC_LOCK_STATUS;\
298+ type AFMT_GENERIC_CONFLICT;\
299+ type AFMT_GENERIC_CONFLICT_CLR;\
300+ type AFMT_GENERIC0_FRAME_UPDATE_PENDING;\
301+ type AFMT_GENERIC1_FRAME_UPDATE_PENDING;\
302+ type AFMT_GENERIC2_FRAME_UPDATE_PENDING;\
303+ type AFMT_GENERIC3_FRAME_UPDATE_PENDING;\
304+ type AFMT_GENERIC4_FRAME_UPDATE_PENDING;\
305+ type AFMT_GENERIC5_FRAME_UPDATE_PENDING;\
306+ type AFMT_GENERIC6_FRAME_UPDATE_PENDING;\
307+ type AFMT_GENERIC7_FRAME_UPDATE_PENDING;\
308+ type AFMT_GENERIC0_FRAME_UPDATE;\
309+ type AFMT_GENERIC1_FRAME_UPDATE;\
310+ type AFMT_GENERIC2_FRAME_UPDATE;\
311+ type AFMT_GENERIC3_FRAME_UPDATE;\
312+ type AFMT_GENERIC4_FRAME_UPDATE;\
313+ type AFMT_GENERIC5_FRAME_UPDATE;\
314+ type AFMT_GENERIC6_FRAME_UPDATE;\
315+ type AFMT_GENERIC7_FRAME_UPDATE;\
316+ type HDMI_GENERIC0_CONT;\
317+ type HDMI_GENERIC0_SEND;\
318+ type HDMI_GENERIC0_LINE;\
319+ type HDMI_GENERIC1_CONT;\
320+ type HDMI_GENERIC1_SEND;\
321+ type HDMI_GENERIC1_LINE;\
322+ type HDMI_GENERIC2_CONT;\
323+ type HDMI_GENERIC2_SEND;\
324+ type HDMI_GENERIC2_LINE;\
325+ type HDMI_GENERIC3_CONT;\
326+ type HDMI_GENERIC3_SEND;\
327+ type HDMI_GENERIC3_LINE;\
328+ type HDMI_GENERIC4_CONT;\
329+ type HDMI_GENERIC4_SEND;\
330+ type HDMI_GENERIC4_LINE;\
331+ type HDMI_GENERIC5_CONT;\
332+ type HDMI_GENERIC5_SEND;\
333+ type HDMI_GENERIC5_LINE;\
334+ type HDMI_GENERIC6_CONT;\
335+ type HDMI_GENERIC6_SEND;\
336+ type HDMI_GENERIC6_LINE;\
337+ type HDMI_GENERIC7_CONT;\
338+ type HDMI_GENERIC7_SEND;\
339+ type HDMI_GENERIC7_LINE;\
340+ type DP_PIXEL_ENCODING;\
341+ type DP_COMPONENT_DEPTH;\
342+ type HDMI_PACKET_GEN_VERSION;\
343+ type HDMI_KEEPOUT_MODE;\
344+ type HDMI_DEEP_COLOR_ENABLE;\
345+ type HDMI_CLOCK_CHANNEL_RATE;\
346+ type HDMI_DEEP_COLOR_DEPTH;\
347+ type HDMI_GC_CONT;\
348+ type HDMI_GC_SEND;\
349+ type HDMI_NULL_SEND;\
350+ type HDMI_DATA_SCRAMBLE_EN;\
351+ type HDMI_AUDIO_INFO_SEND;\
352+ type AFMT_AUDIO_INFO_UPDATE;\
353+ type HDMI_AUDIO_INFO_LINE;\
354+ type HDMI_GC_AVMUTE;\
355+ type DP_MSE_RATE_X;\
356+ type DP_MSE_RATE_Y;\
357+ type DP_MSE_RATE_UPDATE_PENDING;\
358+ type DP_SEC_GSP0_ENABLE;\
359+ type DP_SEC_STREAM_ENABLE;\
360+ type DP_SEC_GSP1_ENABLE;\
361+ type DP_SEC_GSP2_ENABLE;\
362+ type DP_SEC_GSP3_ENABLE;\
363+ type DP_SEC_GSP4_ENABLE;\
364+ type DP_SEC_GSP5_ENABLE;\
365+ type DP_SEC_GSP6_ENABLE;\
366+ type DP_SEC_GSP7_ENABLE;\
367+ type DP_SEC_MPG_ENABLE;\
368+ type DP_VID_STREAM_DIS_DEFER;\
369+ type DP_VID_STREAM_ENABLE;\
370+ type DP_VID_STREAM_STATUS;\
371+ type DP_STEER_FIFO_RESET;\
372+ type DP_VID_M_N_GEN_EN;\
373+ type DP_VID_N;\
374+ type DP_VID_M;\
375+ type DIG_START;\
376+ type AFMT_AUDIO_SRC_SELECT;\
377+ type AFMT_AUDIO_CHANNEL_ENABLE;\
378+ type HDMI_AUDIO_PACKETS_PER_LINE;\
379+ type HDMI_AUDIO_DELAY_EN;\
380+ type AFMT_60958_CS_UPDATE;\
381+ type AFMT_AUDIO_LAYOUT_OVRD;\
382+ type AFMT_60958_OSF_OVRD;\
383+ type HDMI_ACR_AUTO_SEND;\
384+ type HDMI_ACR_SOURCE;\
385+ type HDMI_ACR_AUDIO_PRIORITY;\
386+ type HDMI_ACR_CTS_32;\
387+ type HDMI_ACR_N_32;\
388+ type HDMI_ACR_CTS_44;\
389+ type HDMI_ACR_N_44;\
390+ type HDMI_ACR_CTS_48;\
391+ type HDMI_ACR_N_48;\
392+ type AFMT_60958_CS_CHANNEL_NUMBER_L;\
393+ type AFMT_60958_CS_CLOCK_ACCURACY;\
394+ type AFMT_60958_CS_CHANNEL_NUMBER_R;\
395+ type AFMT_60958_CS_CHANNEL_NUMBER_2;\
396+ type AFMT_60958_CS_CHANNEL_NUMBER_3;\
397+ type AFMT_60958_CS_CHANNEL_NUMBER_4;\
398+ type AFMT_60958_CS_CHANNEL_NUMBER_5;\
399+ type AFMT_60958_CS_CHANNEL_NUMBER_6;\
400+ type AFMT_60958_CS_CHANNEL_NUMBER_7;\
401+ type DP_SEC_AUD_N;\
402+ type DP_SEC_TIMESTAMP_MODE;\
403+ type DP_SEC_ASP_ENABLE;\
404+ type DP_SEC_ATP_ENABLE;\
405+ type DP_SEC_AIP_ENABLE;\
406+ type DP_SEC_ACM_ENABLE;\
407+ type AFMT_AUDIO_SAMPLE_SEND;\
408+ type AFMT_AUDIO_CLOCK_EN;\
409+ type TMDS_PIXEL_ENCODING;\
410+ type TMDS_COLOR_FORMAT;\
411+ type DIG_STEREOSYNC_SELECT;\
412+ type DIG_STEREOSYNC_GATE_EN;\
413+ type DP_DB_DISABLE;\
414+ type DP_MSA_MISC0;\
415+ type DP_MSA_HTOTAL;\
416+ type DP_MSA_VTOTAL;\
417+ type DP_MSA_HSTART;\
418+ type DP_MSA_VSTART;\
419+ type DP_MSA_HSYNCWIDTH;\
420+ type DP_MSA_HSYNCPOLARITY;\
421+ type DP_MSA_VSYNCWIDTH;\
422+ type DP_MSA_VSYNCPOLARITY;\
423+ type DP_MSA_HWIDTH;\
424+ type DP_MSA_VHEIGHT;\
425+ type HDMI_DB_DISABLE;\
426+ type DP_VID_N_MUL;\
427+ type DP_VID_M_DOUBLE_VALUE_EN
428+
429+struct dcn10_stream_encoder_shift {
430+ SE_REG_FIELD_LIST_DCN1_0(uint8_t);
431+};
432+
433+struct dcn10_stream_encoder_mask {
434+ SE_REG_FIELD_LIST_DCN1_0(uint32_t);
435+};
436+
437+struct dcn10_stream_encoder {
438+ struct stream_encoder base;
439+ const struct dcn10_stream_enc_registers *regs;
440+ const struct dcn10_stream_encoder_shift *se_shift;
441+ const struct dcn10_stream_encoder_mask *se_mask;
442+};
443+
444+void dcn10_stream_encoder_construct(
445+ struct dcn10_stream_encoder *enc1,
446+ struct dc_context *ctx,
447+ struct dc_bios *bp,
448+ enum engine_id eng_id,
449+ const struct dcn10_stream_enc_registers *regs,
450+ const struct dcn10_stream_encoder_shift *se_shift,
451+ const struct dcn10_stream_encoder_mask *se_mask);
452+
453+void enc1_update_generic_info_packet(
454+ struct dcn10_stream_encoder *enc1,
455+ uint32_t packet_index,
456+ const struct dc_info_packet *info_packet);
457+
458+void enc1_stream_encoder_dp_set_stream_attribute(
459+ struct stream_encoder *enc,
460+ struct dc_crtc_timing *crtc_timing,
461+ enum dc_color_space output_color_space);
462+
463+void enc1_stream_encoder_hdmi_set_stream_attribute(
464+ struct stream_encoder *enc,
465+ struct dc_crtc_timing *crtc_timing,
466+ int actual_pix_clk_khz,
467+ bool enable_audio);
468+
469+void enc1_stream_encoder_dvi_set_stream_attribute(
470+ struct stream_encoder *enc,
471+ struct dc_crtc_timing *crtc_timing,
472+ bool is_dual_link);
473+
474+void enc1_stream_encoder_set_mst_bandwidth(
475+ struct stream_encoder *enc,
476+ struct fixed31_32 avg_time_slots_per_mtp);
477+
478+void enc1_stream_encoder_update_dp_info_packets(
479+ struct stream_encoder *enc,
480+ const struct encoder_info_frame *info_frame);
481+
482+void enc1_stream_encoder_stop_dp_info_packets(
483+ struct stream_encoder *enc);
484+
485+void enc1_stream_encoder_dp_blank(
486+ struct stream_encoder *enc);
487+
488+void enc1_stream_encoder_dp_unblank(
489+ struct stream_encoder *enc,
490+ const struct encoder_unblank_param *param);
491+
492+void enc1_setup_stereo_sync(
493+ struct stream_encoder *enc,
494+ int tg_inst, bool enable);
495+
496+void enc1_stream_encoder_set_avmute(
497+ struct stream_encoder *enc,
498+ bool enable);
499+
500+void enc1_se_audio_mute_control(
501+ struct stream_encoder *enc,
502+ bool mute);
503+
504+void enc1_se_dp_audio_setup(
505+ struct stream_encoder *enc,
506+ unsigned int az_inst,
507+ struct audio_info *info);
508+
509+void enc1_se_dp_audio_enable(
510+ struct stream_encoder *enc);
511+
512+void enc1_se_dp_audio_disable(
513+ struct stream_encoder *enc);
514+
515+void enc1_se_hdmi_audio_setup(
516+ struct stream_encoder *enc,
517+ unsigned int az_inst,
518+ struct audio_info *info,
519+ struct audio_crtc_info *audio_crtc_info);
520+
521+void enc1_se_hdmi_audio_disable(
522+ struct stream_encoder *enc);
523+
524+#endif /* __DC_STREAM_ENCODER_DCN10_H__ */
drivers/gpu/drm/amd/display/dc/dm_services.h+4−0
@@ -341,6 +341,10 @@ bool dm_dmcu_set_pipe(struct dc_context *ctx, unsigned int controller_id); · 340 unmodified lines
341341
342342 unsigned long long dm_get_timestamp(struct dc_context *ctx);
343343
344+unsigned long long dm_get_elapse_time_in_ns(struct dc_context *ctx,
345+ unsigned long long current_time_stamp,
346+ unsigned long long last_time_stamp);
347+
344348 /*
345349 * performance tracing
346350 */
drivers/gpu/drm/amd/display/dc/dml/display_mode_lib.c+76−62
@@ -26,75 +26,89 @@ · 25 unmodified lines
2626 #include "display_mode_lib.h"
2727 #include "dc_features.h"
2828
29+static const struct _vcs_dpi_ip_params_st dcn1_0_ip = {
30+ .rob_buffer_size_kbytes = 64,
31+ .det_buffer_size_kbytes = 164,
32+ .dpte_buffer_size_in_pte_reqs = 42,
33+ .dpp_output_buffer_pixels = 2560,
34+ .opp_output_buffer_lines = 1,
35+ .pixel_chunk_size_kbytes = 8,
36+ .pte_enable = 1,
37+ .pte_chunk_size_kbytes = 2,
38+ .meta_chunk_size_kbytes = 2,
39+ .writeback_chunk_size_kbytes = 2,
40+ .line_buffer_size_bits = 589824,
41+ .max_line_buffer_lines = 12,
42+ .IsLineBufferBppFixed = 0,
43+ .LineBufferFixedBpp = -1,
44+ .writeback_luma_buffer_size_kbytes = 12,
45+ .writeback_chroma_buffer_size_kbytes = 8,
46+ .max_num_dpp = 4,
47+ .max_num_wb = 2,
48+ .max_dchub_pscl_bw_pix_per_clk = 4,
49+ .max_pscl_lb_bw_pix_per_clk = 2,
50+ .max_lb_vscl_bw_pix_per_clk = 4,
51+ .max_vscl_hscl_bw_pix_per_clk = 4,
52+ .max_hscl_ratio = 4,
53+ .max_vscl_ratio = 4,
54+ .hscl_mults = 4,
55+ .vscl_mults = 4,
56+ .max_hscl_taps = 8,
57+ .max_vscl_taps = 8,
58+ .dispclk_ramp_margin_percent = 1,
59+ .underscan_factor = 1.10,
60+ .min_vblank_lines = 14,
61+ .dppclk_delay_subtotal = 90,
62+ .dispclk_delay_subtotal = 42,
63+ .dcfclk_cstate_latency = 10,
64+ .max_inter_dcn_tile_repeaters = 8,
65+ .can_vstartup_lines_exceed_vsync_plus_back_porch_lines_minus_one = 0,
66+ .bug_forcing_LC_req_same_size_fixed = 0,
67+};
68+
69+static const struct _vcs_dpi_soc_bounding_box_st dcn1_0_soc = {
70+ .sr_exit_time_us = 9.0,
71+ .sr_enter_plus_exit_time_us = 11.0,
72+ .urgent_latency_us = 4.0,
73+ .writeback_latency_us = 12.0,
74+ .ideal_dram_bw_after_urgent_percent = 80.0,
75+ .max_request_size_bytes = 256,
76+ .downspread_percent = 0.5,
77+ .dram_page_open_time_ns = 50.0,
78+ .dram_rw_turnaround_time_ns = 17.5,
79+ .dram_return_buffer_per_channel_bytes = 8192,
80+ .round_trip_ping_latency_dcfclk_cycles = 128,
81+ .urgent_out_of_order_return_per_channel_bytes = 256,
82+ .channel_interleave_bytes = 256,
83+ .num_banks = 8,
84+ .num_chans = 2,
85+ .vmm_page_size_bytes = 4096,
86+ .dram_clock_change_latency_us = 17.0,
87+ .writeback_dram_clock_change_latency_us = 23.0,
88+ .return_bus_width_bytes = 64,
89+};
90+
2991 static void set_soc_bounding_box(struct _vcs_dpi_soc_bounding_box_st *soc, enum dml_project project)
3092 {
31− if (project == DML_PROJECT_RAVEN1) {
32− soc->sr_exit_time_us = 9.0;
33− soc->sr_enter_plus_exit_time_us = 11.0;
34− soc->urgent_latency_us = 4.0;
35− soc->writeback_latency_us = 12.0;
36− soc->ideal_dram_bw_after_urgent_percent = 80.0;
37− soc->max_request_size_bytes = 256;
38− soc->downspread_percent = 0.5;
39− soc->dram_page_open_time_ns = 50.0;
40− soc->dram_rw_turnaround_time_ns = 17.5;
41− soc->dram_return_buffer_per_channel_bytes = 8192;
42− soc->round_trip_ping_latency_dcfclk_cycles = 128;
43− soc->urgent_out_of_order_return_per_channel_bytes = 256;
44− soc->channel_interleave_bytes = 256;
45− soc->num_banks = 8;
46− soc->num_chans = 2;
47− soc->vmm_page_size_bytes = 4096;
48− soc->dram_clock_change_latency_us = 17.0;
49− soc->writeback_dram_clock_change_latency_us = 23.0;
50− soc->return_bus_width_bytes = 64;
51− } else {
52− BREAK_TO_DEBUGGER(); /* Invalid Project Specified */
93+ switch (project) {
94+ case DML_PROJECT_RAVEN1:
95+ *soc = dcn1_0_soc;
96+ break;
97+ default:
98+ ASSERT(0);
99+ break;
53100 }
54101 }
55102
56103 static void set_ip_params(struct _vcs_dpi_ip_params_st *ip, enum dml_project project)
57104 {
58− if (project == DML_PROJECT_RAVEN1) {
59− ip->rob_buffer_size_kbytes = 64;
60− ip->det_buffer_size_kbytes = 164;
61− ip->dpte_buffer_size_in_pte_reqs = 42;
62− ip->dpp_output_buffer_pixels = 2560;
63− ip->opp_output_buffer_lines = 1;
64− ip->pixel_chunk_size_kbytes = 8;
65− ip->pte_enable = 1;
66− ip->pte_chunk_size_kbytes = 2;
67− ip->meta_chunk_size_kbytes = 2;
68− ip->writeback_chunk_size_kbytes = 2;
69− ip->line_buffer_size_bits = 589824;
70− ip->max_line_buffer_lines = 12;
71− ip->IsLineBufferBppFixed = 0;
72− ip->LineBufferFixedBpp = -1;
73− ip->writeback_luma_buffer_size_kbytes = 12;
74− ip->writeback_chroma_buffer_size_kbytes = 8;
75− ip->max_num_dpp = 4;
76− ip->max_num_wb = 2;
77− ip->max_dchub_pscl_bw_pix_per_clk = 4;
78− ip->max_pscl_lb_bw_pix_per_clk = 2;
79− ip->max_lb_vscl_bw_pix_per_clk = 4;
80− ip->max_vscl_hscl_bw_pix_per_clk = 4;
81− ip->max_hscl_ratio = 4;
82− ip->max_vscl_ratio = 4;
83− ip->hscl_mults = 4;
84− ip->vscl_mults = 4;
85− ip->max_hscl_taps = 8;
86− ip->max_vscl_taps = 8;
87− ip->dispclk_ramp_margin_percent = 1;
88− ip->underscan_factor = 1.10;
89− ip->min_vblank_lines = 14;
90− ip->dppclk_delay_subtotal = 90;
91− ip->dispclk_delay_subtotal = 42;
92− ip->dcfclk_cstate_latency = 10;
93− ip->max_inter_dcn_tile_repeaters = 8;
94− ip->can_vstartup_lines_exceed_vsync_plus_back_porch_lines_minus_one = 0;
95− ip->bug_forcing_LC_req_same_size_fixed = 0;
96− } else {
97− BREAK_TO_DEBUGGER(); /* Invalid Project Specified */
105+ switch (project) {
106+ case DML_PROJECT_RAVEN1:
107+ *ip = dcn1_0_ip;
108+ break;
109+ default:
110+ ASSERT(0);
111+ break;
98112 }
99113 }
100114
drivers/gpu/drm/amd/display/dc/dml/display_mode_structs.h+3−2
@@ -215,8 +215,8 @@ struct writeback_st { · 214 unmodified lines
215215 int wb_vtaps_luma;
216216 int wb_htaps_chroma;
217217 int wb_vtaps_chroma;
218− int wb_hratio;
219− int wb_vratio;
218+ double wb_hratio;
219+ double wb_vratio;
220220 };
221221
222222 struct _vcs_dpi_display_output_params_st {
@@ -224,6 +224,7 @@ struct _vcs_dpi_display_output_params_st { · 1 unmodified line
224224 int output_bpp;
225225 int dsc_enable;
226226 int wb_enable;
227+ int num_active_wb;
227228 int opp_input_bpc;
228229 int output_type;
229230 int output_format;
drivers/gpu/drm/amd/display/dc/gpio/hw_factory.c+3−0
@@ -75,6 +75,9 @@ bool dal_hw_factory_init( · 74 unmodified lines
7575 return true;
7676 case DCE_VERSION_11_0:
7777 case DCE_VERSION_11_2:
78+#if defined(CONFIG_DRM_AMD_DC_VEGAM)
79+ case DCE_VERSION_11_22:
80+#endif
7881 dal_hw_factory_dce110_init(factory);
7982 return true;
8083 case DCE_VERSION_12_0:
drivers/gpu/drm/amd/display/dc/gpio/hw_translate.c+3−0
@@ -72,6 +72,9 @@ bool dal_hw_translate_init( · 71 unmodified lines
7272 case DCE_VERSION_10_0:
7373 case DCE_VERSION_11_0:
7474 case DCE_VERSION_11_2:
75+#if defined(CONFIG_DRM_AMD_DC_VEGAM)
76+ case DCE_VERSION_11_22:
77+#endif
7578 dal_hw_translate_dce110_init(translate);
7679 return true;
7780 case DCE_VERSION_12_0:
drivers/gpu/drm/amd/display/dc/i2caux/dce110/i2c_hw_engine_dce110.c+1−1
@@ -527,7 +527,7 @@ static void construct( · 526 unmodified lines
527527 REG_GET(MICROSECOND_TIME_BASE_DIV, XTAL_REF_DIV, &xtal_ref_div);
528528
529529 if (xtal_ref_div == 0) {
530− DC_LOG_WARNING("Invalid base timer divider\n",
530+ DC_LOG_WARNING("Invalid base timer divider [%s]\n",
531531 __func__);
532532 xtal_ref_div = 2;
533533 }
drivers/gpu/drm/amd/display/dc/i2caux/i2caux.c+3−0
@@ -83,6 +83,9 @@ struct i2caux *dal_i2caux_create( · 82 unmodified lines
8383 case DCE_VERSION_8_3:
8484 return dal_i2caux_dce80_create(ctx);
8585 case DCE_VERSION_11_2:
86+#if defined(CONFIG_DRM_AMD_DC_VEGAM)
87+ case DCE_VERSION_11_22:
88+#endif
8689 return dal_i2caux_dce112_create(ctx);
8790 case DCE_VERSION_11_0:
8891 return dal_i2caux_dce110_create(ctx);
drivers/gpu/drm/amd/display/dc/inc/core_types.h+1−5
@@ -95,11 +95,6 @@ struct resource_funcs { · 94 unmodified lines
9595 struct link_encoder *(*link_enc_create)(
9696 const struct encoder_init_data *init);
9797
98− enum dc_status (*validate_guaranteed)(
99− struct dc *dc,
100− struct dc_stream_state *stream,
101− struct dc_state *context);
102−
10398 bool (*validate_bandwidth)(
10499 struct dc *dc,
105100 struct dc_state *context);
@@ -250,6 +245,7 @@ struct dce_bw_output { · 144 unmodified lines
250245 bool all_displays_in_sync;
251246 struct dce_watermarks urgent_wm_ns[MAX_PIPES];
252247 struct dce_watermarks stutter_exit_wm_ns[MAX_PIPES];
248+ struct dce_watermarks stutter_entry_wm_ns[MAX_PIPES];
253249 struct dce_watermarks nbp_state_change_wm_ns[MAX_PIPES];
254250 int sclk_khz;
255251 int sclk_deep_sleep_khz;
drivers/gpu/drm/amd/display/dc/inc/dc_link_ddc.h+3−2
@@ -102,13 +102,14 @@ bool dal_ddc_service_query_ddc_data( · 101 unmodified lines
102102 uint8_t *read_buf,
103103 uint32_t read_size);
104104
105−ssize_t dal_ddc_service_read_dpcd_data(
105+enum ddc_result dal_ddc_service_read_dpcd_data(
106106 struct ddc_service *ddc,
107107 bool i2c,
108108 enum i2c_mot_mode mot,
109109 uint32_t address,
110110 uint8_t *data,
111− uint32_t len);
111+ uint32_t len,
112+ uint32_t *read);
112113
113114 enum ddc_result dal_ddc_service_write_dpcd_data(
114115 struct ddc_service *ddc,
drivers/gpu/drm/amd/display/dc/inc/dce_calcs.h+4−0
@@ -42,6 +42,10 @@ enum bw_calcs_version { · 41 unmodified lines
4242 BW_CALCS_VERSION_CARRIZO,
4343 BW_CALCS_VERSION_POLARIS10,
4444 BW_CALCS_VERSION_POLARIS11,
45+ BW_CALCS_VERSION_POLARIS12,
46+#if defined(CONFIG_DRM_AMD_DC_VEGAM)
47+ BW_CALCS_VERSION_VEGAM,
48+#endif
4549 BW_CALCS_VERSION_STONEY,
4650 BW_CALCS_VERSION_VEGA10
4751 };
drivers/gpu/drm/amd/display/dc/inc/hw/dchubbub.h+64−0
@@ -0,0 +1,64 @@
1+/*
2+ * Copyright 2012-15 Advanced Micro Devices, Inc.
3+ *
4+ * Permission is hereby granted, free of charge, to any person obtaining a
5+ * copy of this software and associated documentation files (the "Software"),
6+ * to deal in the Software without restriction, including without limitation
7+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8+ * and/or sell copies of the Software, and to permit persons to whom the
9+ * Software is furnished to do so, subject to the following conditions:
10+ *
11+ * The above copyright notice and this permission notice shall be included in
12+ * all copies or substantial portions of the Software.
13+ *
14+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20+ * OTHER DEALINGS IN THE SOFTWARE.
21+ *
22+ * Authors: AMD
23+ *
24+ */
25+
26+#ifndef __DAL_DCHUBBUB_H__
27+#define __DAL_DCHUBBUB_H__
28+
29+
30+enum dcc_control {
31+ dcc_control__256_256_xxx,
32+ dcc_control__128_128_xxx,
33+ dcc_control__256_64_64,
34+};
35+
36+enum segment_order {
37+ segment_order__na,
38+ segment_order__contiguous,
39+ segment_order__non_contiguous,
40+};
41+
42+
43+struct hubbub_funcs {
44+ void (*update_dchub)(
45+ struct hubbub *hubbub,
46+ struct dchub_init_data *dh_data);
47+
48+ bool (*get_dcc_compression_cap)(struct hubbub *hubbub,
49+ const struct dc_dcc_surface_param *input,
50+ struct dc_surface_dcc_cap *output);
51+
52+ bool (*dcc_support_swizzle)(
53+ enum swizzle_mode_values swizzle,
54+ unsigned int bytes_per_element,
55+ enum segment_order *segment_order_horz,
56+ enum segment_order *segment_order_vert);
57+
58+ bool (*dcc_support_pixel_format)(
59+ enum surface_pixel_format format,
60+ unsigned int *bytes_per_element);
61+};
62+
63+
64+#endif
drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h+17−1
@@ -44,7 +44,23 @@ struct dpp_grph_csc_adjustment { · 43 unmodified lines
4444 enum graphics_gamut_adjust_type gamut_adjust_type;
4545 };
4646
47+struct dcn_dpp_state {
48+ uint32_t igam_lut_mode;
49+ uint32_t igam_input_format;
50+ uint32_t dgam_lut_mode;
51+ uint32_t rgam_lut_mode;
52+ uint32_t gamut_remap_mode;
53+ uint32_t gamut_remap_c11_c12;
54+ uint32_t gamut_remap_c13_c14;
55+ uint32_t gamut_remap_c21_c22;
56+ uint32_t gamut_remap_c23_c24;
57+ uint32_t gamut_remap_c31_c32;
58+ uint32_t gamut_remap_c33_c34;
59+};
60+
4761 struct dpp_funcs {
62+ void (*dpp_read_state)(struct dpp *dpp, struct dcn_dpp_state *s);
63+
4864 void (*dpp_reset)(struct dpp *dpp);
4965
5066 void (*dpp_set_scaler)(struct dpp *dpp,
@@ -117,7 +133,7 @@ struct dpp_funcs { · 66 unmodified lines
117133 struct dpp *dpp_base,
118134 enum surface_pixel_format format,
119135 enum expansion_mode mode,
120− struct csc_transform input_csc_color_matrix,
136+ struct dc_csc_transform input_csc_color_matrix,
121137 enum dc_color_space input_color_space);
122138
123139 void (*dpp_full_bypass)(struct dpp *dpp_base);
drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h+1−1
@@ -56,7 +56,6 @@ struct hubp { · 55 unmodified lines
5656 bool power_gated;
5757 };
5858
59−
6059 struct hubp_funcs {
6160 void (*hubp_setup)(
6261 struct hubp *hubp,
@@ -121,6 +120,7 @@ struct hubp_funcs { · 58 unmodified lines
121120
122121 void (*hubp_clk_cntl)(struct hubp *hubp, bool enable);
123122 void (*hubp_vtg_sel)(struct hubp *hubp, uint32_t otg_inst);
123+ void (*hubp_read_state)(struct hubp *hubp);
124124
125125 };
126126
drivers/gpu/drm/amd/display/dc/inc/hw/hw_shared.h+5−5
@@ -140,11 +140,6 @@ enum opp_regamma { · 139 unmodified lines
140140 OPP_REGAMMA_USER
141141 };
142142
143−struct csc_transform {
144− uint16_t matrix[12];
145− bool enable_adjustment;
146−};
147−
148143 struct dc_bias_and_scale {
149144 uint16_t scale_red;
150145 uint16_t bias_red;
@@ -191,4 +186,9 @@ enum controller_dp_test_pattern { · 40 unmodified lines
191186 CONTROLLER_DP_TEST_PATTERN_COLORSQUARES_CEA
192187 };
193188
189+enum dc_lut_mode {
190+ LUT_BYPASS,
191+ LUT_RAM_A,
192+ LUT_RAM_B
193+};
194194 #endif /* __DAL_HW_SHARED_H__ */
drivers/gpu/drm/amd/display/dc/inc/hw/ipp.h+1−1
@@ -87,7 +87,7 @@ struct ipp_funcs { · 86 unmodified lines
8787 struct input_pixel_processor *ipp,
8888 enum surface_pixel_format format,
8989 enum expansion_mode mode,
90− struct csc_transform input_csc_color_matrix,
90+ struct dc_csc_transform input_csc_color_matrix,
9191 enum dc_color_space input_color_space);
9292
9393 /* DCE function to setup IPP. TODO: see if we can consolidate to setup */
drivers/gpu/drm/amd/display/dc/inc/hw/link_encoder.h+1−0
@@ -149,6 +149,7 @@ struct link_encoder_funcs { · 148 unmodified lines
149149 bool connect);
150150 void (*enable_hpd)(struct link_encoder *enc);
151151 void (*disable_hpd)(struct link_encoder *enc);
152+ bool (*is_dig_enabled)(struct link_encoder *enc);
152153 void (*destroy)(struct link_encoder **enc);
153154 };
154155
drivers/gpu/drm/amd/display/dc/inc/hw/mem_input.h+1−0
@@ -104,6 +104,7 @@ struct mem_input_funcs { · 103 unmodified lines
104104 struct mem_input *mem_input,
105105 struct dce_watermarks nbp,
106106 struct dce_watermarks stutter,
107+ struct dce_watermarks stutter_enter,
107108 struct dce_watermarks urgent,
108109 uint32_t total_dest_line_time_ns);
109110
drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h+17−0
@@ -105,7 +105,24 @@ struct mpc { · 104 unmodified lines
105105 struct mpcc mpcc_array[MAX_MPCC];
106106 };
107107
108+struct mpcc_state {
109+ uint32_t opp_id;
110+ uint32_t dpp_id;
111+ uint32_t bot_mpcc_id;
112+ uint32_t mode;
113+ uint32_t alpha_mode;
114+ uint32_t pre_multiplied_alpha;
115+ uint32_t overlap_only;
116+ uint32_t idle;
117+ uint32_t busy;
118+};
119+
108120 struct mpc_funcs {
121+ void (*read_mpcc_state)(
122+ struct mpc *mpc,
123+ int mpcc_inst,
124+ struct mpcc_state *s);
125+
109126 /*
110127 * Insert DPP into MPC tree based on specified blending position.
111128 * Only used for planes that are part of blending chain for OPP output
drivers/gpu/drm/amd/display/dc/inc/hw/stream_encoder.h+23−13
@@ -29,31 +29,40 @@ · 28 unmodified lines
2929 #define STREAM_ENCODER_H_
3030
3131 #include "audio_types.h"
32+#include "hw_shared.h"
3233
3334 struct dc_bios;
3435 struct dc_context;
3536 struct dc_crtc_timing;
3637
37−struct encoder_info_packet {
38− bool valid;
39− uint8_t hb0;
40− uint8_t hb1;
41− uint8_t hb2;
42− uint8_t hb3;
43− uint8_t sb[32];
38+enum dp_pixel_encoding_type {
39+ DP_PIXEL_ENCODING_TYPE_RGB444 = 0x00000000,
40+ DP_PIXEL_ENCODING_TYPE_YCBCR422 = 0x00000001,
41+ DP_PIXEL_ENCODING_TYPE_YCBCR444 = 0x00000002,
42+ DP_PIXEL_ENCODING_TYPE_RGB_WIDE_GAMUT = 0x00000003,
43+ DP_PIXEL_ENCODING_TYPE_Y_ONLY = 0x00000004,
44+ DP_PIXEL_ENCODING_TYPE_YCBCR420 = 0x00000005
45+};
46+
47+enum dp_component_depth {
48+ DP_COMPONENT_PIXEL_DEPTH_6BPC = 0x00000000,
49+ DP_COMPONENT_PIXEL_DEPTH_8BPC = 0x00000001,
50+ DP_COMPONENT_PIXEL_DEPTH_10BPC = 0x00000002,
51+ DP_COMPONENT_PIXEL_DEPTH_12BPC = 0x00000003,
52+ DP_COMPONENT_PIXEL_DEPTH_16BPC = 0x00000004
4453 };
4554
4655 struct encoder_info_frame {
4756 /* auxiliary video information */
48− struct encoder_info_packet avi;
49− struct encoder_info_packet gamut;
50− struct encoder_info_packet vendor;
57+ struct dc_info_packet avi;
58+ struct dc_info_packet gamut;
59+ struct dc_info_packet vendor;
5160 /* source product description */
52− struct encoder_info_packet spd;
61+ struct dc_info_packet spd;
5362 /* video stream configuration */
54− struct encoder_info_packet vsc;
63+ struct dc_info_packet vsc;
5564 /* HDR Static MetaData */
56− struct encoder_info_packet hdrsmd;
65+ struct dc_info_packet hdrsmd;
5766 };
5867
5968 struct encoder_unblank_param {
@@ -147,6 +156,7 @@ struct stream_encoder_funcs { · 87 unmodified lines
147156
148157 void (*set_avmute)(
149158 struct stream_encoder *enc, bool enable);
159+
150160 };
151161
152162 #endif /* STREAM_ENCODER_H_ */
drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h+3−0
@@ -140,6 +140,9 @@ struct timing_generator_funcs { · 139 unmodified lines
140140 void (*program_timing)(struct timing_generator *tg,
141141 const struct dc_crtc_timing *timing,
142142 bool use_vbios);
143+ void (*program_vline_interrupt)(struct timing_generator *optc,
144+ const struct dc_crtc_timing *dc_crtc_timing,
145+ unsigned long long vsync_delta);
143146 bool (*enable_crtc)(struct timing_generator *tg);
144147 bool (*disable_crtc)(struct timing_generator *tg);
145148 bool (*is_counter_moving)(struct timing_generator *tg);
drivers/gpu/drm/amd/display/dc/inc/hw/transform.h+1−1
@@ -252,7 +252,7 @@ struct transform_funcs { · 251 unmodified lines
252252 struct transform *xfm_base,
253253 enum surface_pixel_format format,
254254 enum expansion_mode mode,
255− struct csc_transform input_csc_color_matrix,
255+ struct dc_csc_transform input_csc_color_matrix,
256256 enum dc_color_space input_color_space);
257257
258258 void (*ipp_full_bypass)(struct transform *xfm_base);
drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h+16−1
@@ -32,6 +32,8 @@ · 31 unmodified lines
3232 #include "inc/hw/link_encoder.h"
3333 #include "core_status.h"
3434
35+#define EDP_BACKLIGHT_RAMP_DISABLE_LEVEL 0xFFFFFFFF
36+
3537 enum pipe_gating_control {
3638 PIPE_GATING_CONTROL_DISABLE = 0,
3739 PIPE_GATING_CONTROL_ENABLE,
@@ -63,6 +65,7 @@ struct dchub_init_data; · 25 unmodified lines
6365 struct dc_static_screen_events;
6466 struct resource_pool;
6567 struct resource_context;
68+struct stream_resource;
6669
6770 struct hw_sequencer_funcs {
6871
@@ -93,6 +96,12 @@ struct hw_sequencer_funcs { · 24 unmodified lines
9396 enum dc_color_space colorspace,
9497 uint16_t *matrix);
9598
99+ void (*program_output_csc)(struct dc *dc,
100+ struct pipe_ctx *pipe_ctx,
101+ enum dc_color_space colorspace,
102+ uint16_t *matrix,
103+ int opp_id);
104+
96105 void (*update_plane_addr)(
97106 const struct dc *dc,
98107 struct pipe_ctx *pipe_ctx);
@@ -154,6 +163,11 @@ struct hw_sequencer_funcs { · 55 unmodified lines
154163 struct dc *dc,
155164 struct pipe_ctx *pipe,
156165 bool lock);
166+ void (*blank_pixel_data)(
167+ struct dc *dc,
168+ struct stream_resource *stream_res,
169+ struct dc_stream_state *stream,
170+ bool blank);
157171
158172 void (*set_bandwidth)(
159173 struct dc *dc,
@@ -169,7 +183,7 @@ struct hw_sequencer_funcs { · 9 unmodified lines
169183 void (*set_static_screen_control)(struct pipe_ctx **pipe_ctx,
170184 int num_pipes, const struct dc_static_screen_events *events);
171185
172− enum dc_status (*prog_pixclk_crtc_otg)(
186+ enum dc_status (*enable_stream_timing)(
173187 struct pipe_ctx *pipe_ctx,
174188 struct dc_state *context,
175189 struct dc *dc);
@@ -201,6 +215,7 @@ struct hw_sequencer_funcs { · 25 unmodified lines
201215
202216 void (*set_cursor_position)(struct pipe_ctx *pipe);
203217 void (*set_cursor_attribute)(struct pipe_ctx *pipe);
218+
204219 };
205220
206221 void color_space_to_black_color(
drivers/gpu/drm/amd/display/dc/inc/reg_helper.h+56−0
@@ -183,6 +183,36 @@ · 182 unmodified lines
183183 FN(reg_name, f4), v4, \
184184 FN(reg_name, f5), v5)
185185
186+#define REG_GET_6(reg_name, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6) \
187+ generic_reg_get6(CTX, REG(reg_name), \
188+ FN(reg_name, f1), v1, \
189+ FN(reg_name, f2), v2, \
190+ FN(reg_name, f3), v3, \
191+ FN(reg_name, f4), v4, \
192+ FN(reg_name, f5), v5, \
193+ FN(reg_name, f6), v6)
194+
195+#define REG_GET_7(reg_name, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7) \
196+ generic_reg_get7(CTX, REG(reg_name), \
197+ FN(reg_name, f1), v1, \
198+ FN(reg_name, f2), v2, \
199+ FN(reg_name, f3), v3, \
200+ FN(reg_name, f4), v4, \
201+ FN(reg_name, f5), v5, \
202+ FN(reg_name, f6), v6, \
203+ FN(reg_name, f7), v7)
204+
205+#define REG_GET_8(reg_name, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7, f8, v8) \
206+ generic_reg_get8(CTX, REG(reg_name), \
207+ FN(reg_name, f1), v1, \
208+ FN(reg_name, f2), v2, \
209+ FN(reg_name, f3), v3, \
210+ FN(reg_name, f4), v4, \
211+ FN(reg_name, f5), v5, \
212+ FN(reg_name, f6), v6, \
213+ FN(reg_name, f7), v7, \
214+ FN(reg_name, f8), v8)
215+
186216 /* macro to poll and wait for a register field to read back given value */
187217
188218 #define REG_WAIT(reg_name, field, val, delay_between_poll_us, max_try) \
@@ -389,4 +419,30 @@ uint32_t generic_reg_get5(const struct dc_context *ctx, uint32_t addr, · 200 unmodified lines
389419 uint8_t shift4, uint32_t mask4, uint32_t *field_value4,
390420 uint8_t shift5, uint32_t mask5, uint32_t *field_value5);
391421
422+uint32_t generic_reg_get6(const struct dc_context *ctx, uint32_t addr,
423+ uint8_t shift1, uint32_t mask1, uint32_t *field_value1,
424+ uint8_t shift2, uint32_t mask2, uint32_t *field_value2,
425+ uint8_t shift3, uint32_t mask3, uint32_t *field_value3,
426+ uint8_t shift4, uint32_t mask4, uint32_t *field_value4,
427+ uint8_t shift5, uint32_t mask5, uint32_t *field_value5,
428+ uint8_t shift6, uint32_t mask6, uint32_t *field_value6);
429+
430+uint32_t generic_reg_get7(const struct dc_context *ctx, uint32_t addr,
431+ uint8_t shift1, uint32_t mask1, uint32_t *field_value1,
432+ uint8_t shift2, uint32_t mask2, uint32_t *field_value2,
433+ uint8_t shift3, uint32_t mask3, uint32_t *field_value3,
434+ uint8_t shift4, uint32_t mask4, uint32_t *field_value4,
435+ uint8_t shift5, uint32_t mask5, uint32_t *field_value5,
436+ uint8_t shift6, uint32_t mask6, uint32_t *field_value6,
437+ uint8_t shift7, uint32_t mask7, uint32_t *field_value7);
438+
439+uint32_t generic_reg_get8(const struct dc_context *ctx, uint32_t addr,
440+ uint8_t shift1, uint32_t mask1, uint32_t *field_value1,
441+ uint8_t shift2, uint32_t mask2, uint32_t *field_value2,
442+ uint8_t shift3, uint32_t mask3, uint32_t *field_value3,
443+ uint8_t shift4, uint32_t mask4, uint32_t *field_value4,
444+ uint8_t shift5, uint32_t mask5, uint32_t *field_value5,
445+ uint8_t shift6, uint32_t mask6, uint32_t *field_value6,
446+ uint8_t shift7, uint32_t mask7, uint32_t *field_value7,
447+ uint8_t shift8, uint32_t mask8, uint32_t *field_value8);
392448 #endif /* DRIVERS_GPU_DRM_AMD_DC_DEV_DC_INC_REG_HELPER_H_ */
drivers/gpu/drm/amd/display/dc/inc/resource.h+0−4
@@ -139,10 +139,6 @@ bool resource_validate_attach_surfaces( · 138 unmodified lines
139139 struct dc_state *context,
140140 const struct resource_pool *pool);
141141
142−void validate_guaranteed_copy_streams(
143− struct dc_state *context,
144− int max_streams);
145−
146142 void resource_validate_ctx_update_pointer_after_copy(
147143 const struct dc_state *src_ctx,
148144 struct dc_state *dst_ctx);
drivers/gpu/drm/amd/display/dc/irq_types.h+7−0
@@ -135,6 +135,13 @@ enum dc_irq_source { · 134 unmodified lines
135135 DC_IRQ_SOURCE_VBLANK5,
136136 DC_IRQ_SOURCE_VBLANK6,
137137
138+ DC_IRQ_SOURCE_DC1_VLINE0,
139+ DC_IRQ_SOURCE_DC2_VLINE0,
140+ DC_IRQ_SOURCE_DC3_VLINE0,
141+ DC_IRQ_SOURCE_DC4_VLINE0,
142+ DC_IRQ_SOURCE_DC5_VLINE0,
143+ DC_IRQ_SOURCE_DC6_VLINE0,
144+
138145 DAL_IRQ_SOURCES_NUMBER
139146 };
140147
drivers/gpu/drm/amd/display/include/dal_asic_id.h+14−2
@@ -98,7 +98,14 @@ · 97 unmodified lines
9898 (eChipRev < VI_POLARIS11_M_A0))
9999 #define ASIC_REV_IS_POLARIS11_M(eChipRev) ((eChipRev >= VI_POLARIS11_M_A0) && \
100100 (eChipRev < VI_POLARIS12_V_A0))
101+#if defined(CONFIG_DRM_AMD_DC_VEGAM)
102+#define VI_VEGAM_A0 110
103+#define ASIC_REV_IS_POLARIS12_V(eChipRev) ((eChipRev >= VI_POLARIS12_V_A0) && \
104+ (eChipRev < VI_VEGAM_A0))
105+#define ASIC_REV_IS_VEGAM(eChipRev) (eChipRev >= VI_VEGAM_A0)
106+#else
101107 #define ASIC_REV_IS_POLARIS12_V(eChipRev) (eChipRev >= VI_POLARIS12_V_A0)
108+#endif
102109
103110 /* DCE11 */
104111 #define CZ_CARRIZO_A0 0x01
@@ -113,9 +120,14 @@ · 8 unmodified lines
113120
114121 #define AI_GREENLAND_P_A0 1
115122 #define AI_GREENLAND_P_A1 2
123+#define AI_UNKNOWN 0xFF
116124
117−#define ASICREV_IS_GREENLAND_M(eChipRev) (eChipRev < AI_UNKNOWN)
118−#define ASICREV_IS_GREENLAND_P(eChipRev) (eChipRev < AI_UNKNOWN)
125+#define AI_VEGA12_P_A0 20
126+#define ASICREV_IS_GREENLAND_M(eChipRev) (eChipRev < AI_VEGA12_P_A0)
127+#define ASICREV_IS_GREENLAND_P(eChipRev) (eChipRev < AI_VEGA12_P_A0)
128+
129+#define ASICREV_IS_VEGA12_P(eChipRev) ((eChipRev >= AI_VEGA12_P_A0) && (eChipRev < AI_UNKNOWN))
130+#define ASICREV_IS_VEGA12_p(eChipRev) ((eChipRev >= AI_VEGA12_P_A0) && (eChipRev < AI_UNKNOWN))
119131
120132 /* DCN1_0 */
121133 #define INTERNAL_REV_RAVEN_A0 0x00 /* First spin of Raven */
drivers/gpu/drm/amd/display/include/dal_types.h+3−0
@@ -40,6 +40,9 @@ enum dce_version { · 39 unmodified lines
4040 DCE_VERSION_10_0,
4141 DCE_VERSION_11_0,
4242 DCE_VERSION_11_2,
43+#if defined(CONFIG_DRM_AMD_DC_VEGAM)
44+ DCE_VERSION_11_22,
45+#endif
4346 DCE_VERSION_12_0,
4447 DCE_VERSION_MAX,
4548 DCN_VERSION_1_0,
drivers/gpu/drm/amd/display/include/fixed31_32.h+19−21
@@ -26,8 +26,6 @@ · 25 unmodified lines
2626 #ifndef __DAL_FIXED31_32_H__
2727 #define __DAL_FIXED31_32_H__
2828
29−#include "os_types.h"
30−
3129 #define FIXED31_32_BITS_PER_FRACTIONAL_PART 32
3230
3331 /*
@@ -44,7 +42,7 @@ · 10 unmodified lines
4442 */
4543
4644 struct fixed31_32 {
47− int64_t value;
45+ long long value;
4846 };
4947
5048 /*
@@ -73,15 +71,15 @@ static const struct fixed31_32 dal_fixed31_32_ln2_div_2 = { 1488522236LL }; · 22 unmodified lines
7371 * result = numerator / denominator
7472 */
7573 struct fixed31_32 dal_fixed31_32_from_fraction(
76− int64_t numerator,
77− int64_t denominator);
74+ long long numerator,
75+ long long denominator);
7876
7977 /*
8078 * @brief
8179 * result = arg
8280 */
83−struct fixed31_32 dal_fixed31_32_from_int_nonconst(int64_t arg);
84−static inline struct fixed31_32 dal_fixed31_32_from_int(int64_t arg)
81+struct fixed31_32 dal_fixed31_32_from_int_nonconst(long long arg);
82+static inline struct fixed31_32 dal_fixed31_32_from_int(long long arg)
8583 {
8684 if (__builtin_constant_p(arg)) {
8785 struct fixed31_32 res;
@@ -213,7 +211,7 @@ static inline struct fixed31_32 dal_fixed31_32_clamp( · 125 unmodified lines
213211 */
214212 struct fixed31_32 dal_fixed31_32_shl(
215213 struct fixed31_32 arg,
216− uint8_t shift);
214+ unsigned char shift);
217215
218216 /*
219217 * @brief
@@ -221,7 +219,7 @@ struct fixed31_32 dal_fixed31_32_shl( · 1 unmodified line
221219 */
222220 static inline struct fixed31_32 dal_fixed31_32_shr(
223221 struct fixed31_32 arg,
224− uint8_t shift)
222+ unsigned char shift)
225223 {
226224 struct fixed31_32 res;
227225 res.value = arg.value >> shift;
@@ -246,7 +244,7 @@ struct fixed31_32 dal_fixed31_32_add( · 18 unmodified lines
246244 * result = arg1 + arg2
247245 */
248246 static inline struct fixed31_32 dal_fixed31_32_add_int(struct fixed31_32 arg1,
249− int32_t arg2)
247+ int arg2)
250248 {
251249 return dal_fixed31_32_add(arg1,
252250 dal_fixed31_32_from_int(arg2));
@@ -265,7 +263,7 @@ struct fixed31_32 dal_fixed31_32_sub( · 12 unmodified lines
265263 * result = arg1 - arg2
266264 */
267265 static inline struct fixed31_32 dal_fixed31_32_sub_int(struct fixed31_32 arg1,
268− int32_t arg2)
266+ int arg2)
269267 {
270268 return dal_fixed31_32_sub(arg1,
271269 dal_fixed31_32_from_int(arg2));
@@ -291,7 +289,7 @@ struct fixed31_32 dal_fixed31_32_mul( · 19 unmodified lines
291289 * result = arg1 * arg2
292290 */
293291 static inline struct fixed31_32 dal_fixed31_32_mul_int(struct fixed31_32 arg1,
294− int32_t arg2)
292+ int arg2)
295293 {
296294 return dal_fixed31_32_mul(arg1,
297295 dal_fixed31_32_from_int(arg2));
@@ -309,7 +307,7 @@ struct fixed31_32 dal_fixed31_32_sqr( · 11 unmodified lines
309307 * result = arg1 / arg2
310308 */
311309 static inline struct fixed31_32 dal_fixed31_32_div_int(struct fixed31_32 arg1,
312− int64_t arg2)
310+ long long arg2)
313311 {
314312 return dal_fixed31_32_from_fraction(arg1.value,
315313 dal_fixed31_32_from_int(arg2).value);
@@ -434,21 +432,21 @@ struct fixed31_32 dal_fixed31_32_pow( · 118 unmodified lines
434432 * @brief
435433 * result = floor(arg) := greatest integer lower than or equal to arg
436434 */
437−int32_t dal_fixed31_32_floor(
435+int dal_fixed31_32_floor(
438436 struct fixed31_32 arg);
439437
440438 /*
441439 * @brief
442440 * result = round(arg) := integer nearest to arg
443441 */
444−int32_t dal_fixed31_32_round(
442+int dal_fixed31_32_round(
445443 struct fixed31_32 arg);
446444
447445 /*
448446 * @brief
449447 * result = ceil(arg) := lowest integer greater than or equal to arg
450448 */
451−int32_t dal_fixed31_32_ceil(
449+int dal_fixed31_32_ceil(
452450 struct fixed31_32 arg);
453451
454452 /* the following two function are used in scaler hw programming to convert fixed
@@ -457,20 +455,20 @@ int32_t dal_fixed31_32_ceil( · 2 unmodified lines
457455 * fractional
458456 */
459457
460−uint32_t dal_fixed31_32_u2d19(
458+unsigned int dal_fixed31_32_u2d19(
461459 struct fixed31_32 arg);
462460
463−uint32_t dal_fixed31_32_u0d19(
461+unsigned int dal_fixed31_32_u0d19(
464462 struct fixed31_32 arg);
465463
466464
467−uint32_t dal_fixed31_32_clamp_u0d14(
465+unsigned int dal_fixed31_32_clamp_u0d14(
468466 struct fixed31_32 arg);
469467
470−uint32_t dal_fixed31_32_clamp_u0d10(
468+unsigned int dal_fixed31_32_clamp_u0d10(
471469 struct fixed31_32 arg);
472470
473−int32_t dal_fixed31_32_s4d19(
471+int dal_fixed31_32_s4d19(
474472 struct fixed31_32 arg);
475473
476474 #endif
drivers/gpu/drm/amd/display/include/logger_types.h+32−32
@@ -29,39 +29,39 @@ · 28 unmodified lines
2929 #include "os_types.h"
3030
3131 #define MAX_NAME_LEN 32
32−#define DC_LOG_ERROR(a, ...) dm_logger_write(DC_LOGGER, LOG_ERROR, a, ## __VA_ARGS__)
33−#define DC_LOG_WARNING(a, ...) dm_logger_write(DC_LOGGER, LOG_WARNING, a, ## __VA_ARGS__)
34−#define DC_LOG_DEBUG(a, ...) dm_logger_write(DC_LOGGER, LOG_DEBUG, a, ## __VA_ARGS__)
35−#define DC_LOG_DC(a, ...) dm_logger_write(DC_LOGGER, LOG_DC, a, ## __VA_ARGS__)
36−#define DC_LOG_DTN(a, ...) dm_logger_write(DC_LOGGER, LOG_DTN, a, ## __VA_ARGS__)
37−#define DC_LOG_SURFACE(a, ...) dm_logger_write(DC_LOGGER, LOG_SURFACE, a, ## __VA_ARGS__)
38−#define DC_LOG_HW_HOTPLUG(a, ...) dm_logger_write(DC_LOGGER, LOG_HW_HOTPLUG, a, ## __VA_ARGS__)
39−#define DC_LOG_HW_LINK_TRAINING(a, ...) dm_logger_write(DC_LOGGER, LOG_HW_LINK_TRAINING, a, ## __VA_ARGS__)
40−#define DC_LOG_HW_SET_MODE(a, ...) dm_logger_write(DC_LOGGER, LOG_HW_SET_MODE, a, ## __VA_ARGS__)
41−#define DC_LOG_HW_RESUME_S3(a, ...) dm_logger_write(DC_LOGGER, LOG_HW_RESUME_S3, a, ## __VA_ARGS__)
42−#define DC_LOG_HW_AUDIO(a, ...) dm_logger_write(DC_LOGGER, LOG_HW_AUDIO, a, ## __VA_ARGS__)
43−#define DC_LOG_HW_HPD_IRQ(a, ...) dm_logger_write(DC_LOGGER, LOG_HW_HPD_IRQ, a, ## __VA_ARGS__)
44−#define DC_LOG_MST(a, ...) dm_logger_write(DC_LOGGER, LOG_MST, a, ## __VA_ARGS__)
45−#define DC_LOG_SCALER(a, ...) dm_logger_write(DC_LOGGER, LOG_SCALER, a, ## __VA_ARGS__)
46−#define DC_LOG_BIOS(a, ...) dm_logger_write(DC_LOGGER, LOG_BIOS, a, ## __VA_ARGS__)
47−#define DC_LOG_BANDWIDTH_CALCS(a, ...) dm_logger_write(DC_LOGGER, LOG_BANDWIDTH_CALCS, a, ## __VA_ARGS__)
48−#define DC_LOG_BANDWIDTH_VALIDATION(a, ...) dm_logger_write(DC_LOGGER, LOG_BANDWIDTH_VALIDATION, a, ## __VA_ARGS__)
49−#define DC_LOG_I2C_AUX(a, ...) dm_logger_write(DC_LOGGER, LOG_I2C_AUX, a, ## __VA_ARGS__)
50−#define DC_LOG_SYNC(a, ...) dm_logger_write(DC_LOGGER, LOG_SYNC, a, ## __VA_ARGS__)
51−#define DC_LOG_BACKLIGHT(a, ...) dm_logger_write(DC_LOGGER, LOG_BACKLIGHT, a, ## __VA_ARGS__)
52−#define DC_LOG_FEATURE_OVERRIDE(a, ...) dm_logger_write(DC_LOGGER, LOG_FEATURE_OVERRIDE, a, ## __VA_ARGS__)
53−#define DC_LOG_DETECTION_EDID_PARSER(a, ...) dm_logger_write(DC_LOGGER, LOG_DETECTION_EDID_PARSER, a, ## __VA_ARGS__)
54−#define DC_LOG_DETECTION_DP_CAPS(a, ...) dm_logger_write(DC_LOGGER, LOG_DETECTION_DP_CAPS, a, ## __VA_ARGS__)
55−#define DC_LOG_RESOURCE(a, ...) dm_logger_write(DC_LOGGER, LOG_RESOURCE, a, ## __VA_ARGS__)
56−#define DC_LOG_DML(a, ...) dm_logger_write(DC_LOGGER, LOG_DML, a, ## __VA_ARGS__)
57−#define DC_LOG_EVENT_MODE_SET(a, ...) dm_logger_write(DC_LOGGER, LOG_EVENT_MODE_SET, a, ## __VA_ARGS__)
58−#define DC_LOG_EVENT_DETECTION(a, ...) dm_logger_write(DC_LOGGER, LOG_EVENT_DETECTION, a, ## __VA_ARGS__)
59−#define DC_LOG_EVENT_LINK_TRAINING(a, ...) dm_logger_write(DC_LOGGER, LOG_EVENT_LINK_TRAINING, a, ## __VA_ARGS__)
60−#define DC_LOG_EVENT_LINK_LOSS(a, ...) dm_logger_write(DC_LOGGER, LOG_EVENT_LINK_LOSS, a, ## __VA_ARGS__)
61−#define DC_LOG_EVENT_UNDERFLOW(a, ...) dm_logger_write(DC_LOGGER, LOG_EVENT_UNDERFLOW, a, ## __VA_ARGS__)
62−#define DC_LOG_IF_TRACE(a, ...) dm_logger_write(DC_LOGGER, LOG_IF_TRACE, a, ## __VA_ARGS__)
63−#define DC_LOG_PERF_TRACE(a, ...) dm_logger_write(DC_LOGGER, LOG_PERF_TRACE, a, ## __VA_ARGS__)
6432
33+#define DC_LOG_ERROR(...) DRM_ERROR(__VA_ARGS__)
34+#define DC_LOG_WARNING(...) DRM_WARN(__VA_ARGS__)
35+#define DC_LOG_DEBUG(...) DRM_DEBUG_KMS(__VA_ARGS__)
36+#define DC_LOG_DC(...) DRM_DEBUG_KMS(__VA_ARGS__)
37+#define DC_LOG_DTN(...) DRM_DEBUG_KMS(__VA_ARGS__)
38+#define DC_LOG_SURFACE(...) pr_debug("[SURFACE]:"__VA_ARGS__)
39+#define DC_LOG_HW_HOTPLUG(...) DRM_DEBUG_KMS(__VA_ARGS__)
40+#define DC_LOG_HW_LINK_TRAINING(...) pr_debug("[HW_LINK_TRAINING]:"__VA_ARGS__)
41+#define DC_LOG_HW_SET_MODE(...) DRM_DEBUG_KMS(__VA_ARGS__)
42+#define DC_LOG_HW_RESUME_S3(...) DRM_DEBUG_KMS(__VA_ARGS__)
43+#define DC_LOG_HW_AUDIO(...) pr_debug("[HW_AUDIO]:"__VA_ARGS__)
44+#define DC_LOG_HW_HPD_IRQ(...) DRM_DEBUG_KMS(__VA_ARGS__)
45+#define DC_LOG_MST(...) DRM_DEBUG_KMS(__VA_ARGS__)
46+#define DC_LOG_SCALER(...) pr_debug("[SCALER]:"__VA_ARGS__)
47+#define DC_LOG_BIOS(...) pr_debug("[BIOS]:"__VA_ARGS__)
48+#define DC_LOG_BANDWIDTH_CALCS(...) pr_debug("[BANDWIDTH_CALCS]:"__VA_ARGS__)
49+#define DC_LOG_BANDWIDTH_VALIDATION(...) DRM_DEBUG_KMS(__VA_ARGS__)
50+#define DC_LOG_I2C_AUX(...) DRM_DEBUG_KMS(__VA_ARGS__)
51+#define DC_LOG_SYNC(...) DRM_DEBUG_KMS(__VA_ARGS__)
52+#define DC_LOG_BACKLIGHT(...) DRM_DEBUG_KMS(__VA_ARGS__)
53+#define DC_LOG_FEATURE_OVERRIDE(...) DRM_DEBUG_KMS(__VA_ARGS__)
54+#define DC_LOG_DETECTION_EDID_PARSER(...) DRM_DEBUG_KMS(__VA_ARGS__)
55+#define DC_LOG_DETECTION_DP_CAPS(...) DRM_DEBUG_KMS(__VA_ARGS__)
56+#define DC_LOG_RESOURCE(...) DRM_DEBUG_KMS(__VA_ARGS__)
57+#define DC_LOG_DML(...) pr_debug("[DML]:"__VA_ARGS__)
58+#define DC_LOG_EVENT_MODE_SET(...) DRM_DEBUG_KMS(__VA_ARGS__)
59+#define DC_LOG_EVENT_DETECTION(...) DRM_DEBUG_KMS(__VA_ARGS__)
60+#define DC_LOG_EVENT_LINK_TRAINING(...) DRM_DEBUG_KMS(__VA_ARGS__)
61+#define DC_LOG_EVENT_LINK_LOSS(...) DRM_DEBUG_KMS(__VA_ARGS__)
62+#define DC_LOG_EVENT_UNDERFLOW(...) DRM_DEBUG_KMS(__VA_ARGS__)
63+#define DC_LOG_IF_TRACE(...) pr_debug("[IF_TRACE]:"__VA_ARGS__)
64+#define DC_LOG_PERF_TRACE(...) DRM_DEBUG_KMS(__VA_ARGS__)
6565
6666 struct dal_logger;
6767
drivers/gpu/drm/amd/display/modules/color/color_gamma.c+337−45
@@ -185,14 +185,14 @@ struct dividers { · 184 unmodified lines
185185
186186 static void build_coefficients(struct gamma_coefficients *coefficients, bool is_2_4)
187187 {
188− static const int32_t numerator01[] = { 31308, 180000};
189− static const int32_t numerator02[] = { 12920, 4500};
190− static const int32_t numerator03[] = { 55, 99};
191− static const int32_t numerator04[] = { 55, 99};
192− static const int32_t numerator05[] = { 2400, 2200};
188+ static const int32_t numerator01[] = { 31308, 180000};
189+ static const int32_t numerator02[] = { 12920, 4500};
190+ static const int32_t numerator03[] = { 55, 99};
191+ static const int32_t numerator04[] = { 55, 99};
192+ static const int32_t numerator05[] = { 2400, 2200};
193193
194− uint32_t i = 0;
195− uint32_t index = is_2_4 == true ? 0:1;
194+ uint32_t i = 0;
195+ uint32_t index = is_2_4 == true ? 0:1;
196196
197197 do {
198198 coefficients->a0[i] = dal_fixed31_32_from_fraction(
@@ -691,7 +691,7 @@ static void build_degamma(struct pwl_float_data_ex *curve, · 492 unmodified lines
691691 }
692692 }
693693
694−static bool scale_gamma(struct pwl_float_data *pwl_rgb,
694+static void scale_gamma(struct pwl_float_data *pwl_rgb,
695695 const struct dc_gamma *ramp,
696696 struct dividers dividers)
697697 {
@@ -752,11 +752,9 @@ static bool scale_gamma(struct pwl_float_data *pwl_rgb, · 54 unmodified lines
752752 dividers.divider3);
753753 rgb->b = dal_fixed31_32_mul(rgb_last->b,
754754 dividers.divider3);
755−
756− return true;
757755 }
758756
759−static bool scale_gamma_dx(struct pwl_float_data *pwl_rgb,
757+static void scale_gamma_dx(struct pwl_float_data *pwl_rgb,
760758 const struct dc_gamma *ramp,
761759 struct dividers dividers)
762760 {
@@ -818,8 +816,71 @@ static bool scale_gamma_dx(struct pwl_float_data *pwl_rgb, · 55 unmodified lines
818816 pwl_rgb[i-1].g, 2), pwl_rgb[i-2].g);
819817 pwl_rgb[i].b = dal_fixed31_32_sub(dal_fixed31_32_mul_int(
820818 pwl_rgb[i-1].b, 2), pwl_rgb[i-2].b);
819+}
821820
822− return true;
821+/* todo: all these scale_gamma functions are inherently the same but
822+ * take different structures as params or different format for ramp
823+ * values. We could probably implement it in a more generic fashion
824+ */
825+static void scale_user_regamma_ramp(struct pwl_float_data *pwl_rgb,
826+ const struct regamma_ramp *ramp,
827+ struct dividers dividers)
828+{
829+ unsigned short max_driver = 0xFFFF;
830+ unsigned short max_os = 0xFF00;
831+ unsigned short scaler = max_os;
832+ uint32_t i;
833+ struct pwl_float_data *rgb = pwl_rgb;
834+ struct pwl_float_data *rgb_last = rgb + GAMMA_RGB_256_ENTRIES - 1;
835+
836+ i = 0;
837+ do {
838+ if (ramp->gamma[i] > max_os ||
839+ ramp->gamma[i + 256] > max_os ||
840+ ramp->gamma[i + 512] > max_os) {
841+ scaler = max_driver;
842+ break;
843+ }
844+ i++;
845+ } while (i != GAMMA_RGB_256_ENTRIES);
846+
847+ i = 0;
848+ do {
849+ rgb->r = dal_fixed31_32_from_fraction(
850+ ramp->gamma[i], scaler);
851+ rgb->g = dal_fixed31_32_from_fraction(
852+ ramp->gamma[i + 256], scaler);
853+ rgb->b = dal_fixed31_32_from_fraction(
854+ ramp->gamma[i + 512], scaler);
855+
856+ ++rgb;
857+ ++i;
858+ } while (i != GAMMA_RGB_256_ENTRIES);
859+
860+ rgb->r = dal_fixed31_32_mul(rgb_last->r,
861+ dividers.divider1);
862+ rgb->g = dal_fixed31_32_mul(rgb_last->g,
863+ dividers.divider1);
864+ rgb->b = dal_fixed31_32_mul(rgb_last->b,
865+ dividers.divider1);
866+
867+ ++rgb;
868+
869+ rgb->r = dal_fixed31_32_mul(rgb_last->r,
870+ dividers.divider2);
871+ rgb->g = dal_fixed31_32_mul(rgb_last->g,
872+ dividers.divider2);
873+ rgb->b = dal_fixed31_32_mul(rgb_last->b,
874+ dividers.divider2);
875+
876+ ++rgb;
877+
878+ rgb->r = dal_fixed31_32_mul(rgb_last->r,
879+ dividers.divider3);
880+ rgb->g = dal_fixed31_32_mul(rgb_last->g,
881+ dividers.divider3);
882+ rgb->b = dal_fixed31_32_mul(rgb_last->b,
883+ dividers.divider3);
823884 }
824885
825886 /*
@@ -949,7 +1010,7 @@ static inline void copy_rgb_regamma_to_coordinates_x( · 123 unmodified lines
9491010 uint32_t i = 0;
9501011 const struct pwl_float_data_ex *rgb_regamma = rgb_ex;
9511012
952− while (i <= hw_points_num) {
1013+ while (i <= hw_points_num + 1) {
9531014 coords->regamma_y_red = rgb_regamma->r;
9541015 coords->regamma_y_green = rgb_regamma->g;
9551016 coords->regamma_y_blue = rgb_regamma->b;
@@ -1002,6 +1063,102 @@ static bool calculate_interpolated_hardware_curve( · 46 unmodified lines
10021063 return true;
10031064 }
10041065
1066+/* The "old" interpolation uses a complicated scheme to build an array of
1067+ * coefficients while also using an array of 0-255 normalized to 0-1
1068+ * Then there's another loop using both of the above + new scaled user ramp
1069+ * and we concatenate them. It also searches for points of interpolation and
1070+ * uses enums for positions.
1071+ *
1072+ * This function uses a different approach:
1073+ * user ramp is always applied on X with 0/255, 1/255, 2/255, ..., 255/255
1074+ * To find index for hwX , we notice the following:
1075+ * i/255 <= hwX < (i+1)/255 <=> i <= 255*hwX < i+1
1076+ * See apply_lut_1d which is the same principle, but on 4K entry 1D LUT
1077+ *
1078+ * Once the index is known, combined Y is simply:
1079+ * user_ramp(index) + (hwX-index/255)*(user_ramp(index+1) - user_ramp(index)
1080+ *
1081+ * We should switch to this method in all cases, it's simpler and faster
1082+ * ToDo one day - for now this only applies to ADL regamma to avoid regression
1083+ * for regular use cases (sRGB and PQ)
1084+ */
1085+static void interpolate_user_regamma(uint32_t hw_points_num,
1086+ struct pwl_float_data *rgb_user,
1087+ bool apply_degamma,
1088+ struct dc_transfer_func_distributed_points *tf_pts)
1089+{
1090+ uint32_t i;
1091+ uint32_t color = 0;
1092+ int32_t index;
1093+ int32_t index_next;
1094+ struct fixed31_32 *tf_point;
1095+ struct fixed31_32 hw_x;
1096+ struct fixed31_32 norm_factor =
1097+ dal_fixed31_32_from_int_nonconst(255);
1098+ struct fixed31_32 norm_x;
1099+ struct fixed31_32 index_f;
1100+ struct fixed31_32 lut1;
1101+ struct fixed31_32 lut2;
1102+ struct fixed31_32 delta_lut;
1103+ struct fixed31_32 delta_index;
1104+
1105+ i = 0;
1106+ /* fixed_pt library has problems handling too small values */
1107+ while (i != 32) {
1108+ tf_pts->red[i] = dal_fixed31_32_zero;
1109+ tf_pts->green[i] = dal_fixed31_32_zero;
1110+ tf_pts->blue[i] = dal_fixed31_32_zero;
1111+ ++i;
1112+ }
1113+ while (i <= hw_points_num + 1) {
1114+ for (color = 0; color < 3; color++) {
1115+ if (color == 0)
1116+ tf_point = &tf_pts->red[i];
1117+ else if (color == 1)
1118+ tf_point = &tf_pts->green[i];
1119+ else
1120+ tf_point = &tf_pts->blue[i];
1121+
1122+ if (apply_degamma) {
1123+ if (color == 0)
1124+ hw_x = coordinates_x[i].regamma_y_red;
1125+ else if (color == 1)
1126+ hw_x = coordinates_x[i].regamma_y_green;
1127+ else
1128+ hw_x = coordinates_x[i].regamma_y_blue;
1129+ } else
1130+ hw_x = coordinates_x[i].x;
1131+
1132+ norm_x = dal_fixed31_32_mul(norm_factor, hw_x);
1133+ index = dal_fixed31_32_floor(norm_x);
1134+ if (index < 0 || index > 255)
1135+ continue;
1136+
1137+ index_f = dal_fixed31_32_from_int_nonconst(index);
1138+ index_next = (index == 255) ? index : index + 1;
1139+
1140+ if (color == 0) {
1141+ lut1 = rgb_user[index].r;
1142+ lut2 = rgb_user[index_next].r;
1143+ } else if (color == 1) {
1144+ lut1 = rgb_user[index].g;
1145+ lut2 = rgb_user[index_next].g;
1146+ } else {
1147+ lut1 = rgb_user[index].b;
1148+ lut2 = rgb_user[index_next].b;
1149+ }
1150+
1151+ // we have everything now, so interpolate
1152+ delta_lut = dal_fixed31_32_sub(lut2, lut1);
1153+ delta_index = dal_fixed31_32_sub(norm_x, index_f);
1154+
1155+ *tf_point = dal_fixed31_32_add(lut1,
1156+ dal_fixed31_32_mul(delta_index, delta_lut));
1157+ }
1158+ ++i;
1159+ }
1160+}
1161+
10051162 static void build_new_custom_resulted_curve(
10061163 uint32_t hw_points_num,
10071164 struct dc_transfer_func_distributed_points *tf_pts)
@@ -1025,6 +1182,29 @@ static void build_new_custom_resulted_curve( · 17 unmodified lines
10251182 }
10261183 }
10271184
1185+static void apply_degamma_for_user_regamma(struct pwl_float_data_ex *rgb_regamma,
1186+ uint32_t hw_points_num)
1187+{
1188+ uint32_t i;
1189+
1190+ struct gamma_coefficients coeff;
1191+ struct pwl_float_data_ex *rgb = rgb_regamma;
1192+ const struct hw_x_point *coord_x = coordinates_x;
1193+
1194+ build_coefficients(&coeff, true);
1195+
1196+ i = 0;
1197+ while (i != hw_points_num + 1) {
1198+ rgb->r = translate_from_linear_space_ex(
1199+ coord_x->x, &coeff, 0);
1200+ rgb->g = rgb->r;
1201+ rgb->b = rgb->r;
1202+ ++coord_x;
1203+ ++rgb;
1204+ ++i;
1205+ }
1206+}
1207+
10281208 static bool map_regamma_hw_to_x_user(
10291209 const struct dc_gamma *ramp,
10301210 struct pixel_gamma_point *coeff128,
@@ -1062,6 +1242,7 @@ static bool map_regamma_hw_to_x_user( · 31 unmodified lines
10621242 }
10631243 }
10641244
1245+ /* this should be named differently, all it does is clamp to 0-1 */
10651246 build_new_custom_resulted_curve(hw_points_num, tf_pts);
10661247
10671248 return true;
@@ -1093,19 +1274,19 @@ bool mod_color_calculate_regamma_params(struct dc_transfer_func *output_tf, · 25 unmodified lines
10931274
10941275 output_tf->type = TF_TYPE_DISTRIBUTED_POINTS;
10951276
1096− rgb_user = kzalloc(sizeof(*rgb_user) * (ramp->num_entries + _EXTRA_POINTS),
1097− GFP_KERNEL);
1277+ rgb_user = kvzalloc(sizeof(*rgb_user) * (ramp->num_entries + _EXTRA_POINTS),
1278+ GFP_KERNEL);
10981279 if (!rgb_user)
10991280 goto rgb_user_alloc_fail;
1100− rgb_regamma = kzalloc(sizeof(*rgb_regamma) * (MAX_HW_POINTS + _EXTRA_POINTS),
1101− GFP_KERNEL);
1281+ rgb_regamma = kvzalloc(sizeof(*rgb_regamma) * (MAX_HW_POINTS + _EXTRA_POINTS),
1282+ GFP_KERNEL);
11021283 if (!rgb_regamma)
11031284 goto rgb_regamma_alloc_fail;
1104− axix_x = kzalloc(sizeof(*axix_x) * (ramp->num_entries + 3),
1105− GFP_KERNEL);
1285+ axix_x = kvzalloc(sizeof(*axix_x) * (ramp->num_entries + 3),
1286+ GFP_KERNEL);
11061287 if (!axix_x)
11071288 goto axix_x_alloc_fail;
1108− coeff = kzalloc(sizeof(*coeff) * (MAX_HW_POINTS + _EXTRA_POINTS), GFP_KERNEL);
1289+ coeff = kvzalloc(sizeof(*coeff) * (MAX_HW_POINTS + _EXTRA_POINTS), GFP_KERNEL);
11091290 if (!coeff)
11101291 goto coeff_alloc_fail;
11111292
@@ -1157,10 +1338,117 @@ bool mod_color_calculate_regamma_params(struct dc_transfer_func *output_tf, · 45 unmodified lines
11571338
11581339 ret = true;
11591340
1160− kfree(coeff);
1341+ kvfree(coeff);
11611342 coeff_alloc_fail:
1162− kfree(axix_x);
1343+ kvfree(axix_x);
11631344 axix_x_alloc_fail:
1345+ kvfree(rgb_regamma);
1346+rgb_regamma_alloc_fail:
1347+ kvfree(rgb_user);
1348+rgb_user_alloc_fail:
1349+ return ret;
1350+}
1351+
1352+bool calculate_user_regamma_coeff(struct dc_transfer_func *output_tf,
1353+ const struct regamma_lut *regamma)
1354+{
1355+ struct gamma_coefficients coeff;
1356+ const struct hw_x_point *coord_x = coordinates_x;
1357+ uint32_t i = 0;
1358+
1359+ do {
1360+ coeff.a0[i] = dal_fixed31_32_from_fraction(
1361+ regamma->coeff.A0[i], 10000000);
1362+ coeff.a1[i] = dal_fixed31_32_from_fraction(
1363+ regamma->coeff.A1[i], 1000);
1364+ coeff.a2[i] = dal_fixed31_32_from_fraction(
1365+ regamma->coeff.A2[i], 1000);
1366+ coeff.a3[i] = dal_fixed31_32_from_fraction(
1367+ regamma->coeff.A3[i], 1000);
1368+ coeff.user_gamma[i] = dal_fixed31_32_from_fraction(
1369+ regamma->coeff.gamma[i], 1000);
1370+
1371+ ++i;
1372+ } while (i != 3);
1373+
1374+ i = 0;
1375+ /* fixed_pt library has problems handling too small values */
1376+ while (i != 32) {
1377+ output_tf->tf_pts.red[i] = dal_fixed31_32_zero;
1378+ output_tf->tf_pts.green[i] = dal_fixed31_32_zero;
1379+ output_tf->tf_pts.blue[i] = dal_fixed31_32_zero;
1380+ ++coord_x;
1381+ ++i;
1382+ }
1383+ while (i != MAX_HW_POINTS + 1) {
1384+ output_tf->tf_pts.red[i] = translate_from_linear_space_ex(
1385+ coord_x->x, &coeff, 0);
1386+ output_tf->tf_pts.green[i] = translate_from_linear_space_ex(
1387+ coord_x->x, &coeff, 1);
1388+ output_tf->tf_pts.blue[i] = translate_from_linear_space_ex(
1389+ coord_x->x, &coeff, 2);
1390+ ++coord_x;
1391+ ++i;
1392+ }
1393+
1394+ // this function just clamps output to 0-1
1395+ build_new_custom_resulted_curve(MAX_HW_POINTS, &output_tf->tf_pts);
1396+ output_tf->type = TF_TYPE_DISTRIBUTED_POINTS;
1397+
1398+ return true;
1399+}
1400+
1401+bool calculate_user_regamma_ramp(struct dc_transfer_func *output_tf,
1402+ const struct regamma_lut *regamma)
1403+{
1404+ struct dc_transfer_func_distributed_points *tf_pts = &output_tf->tf_pts;
1405+ struct dividers dividers;
1406+
1407+ struct pwl_float_data *rgb_user = NULL;
1408+ struct pwl_float_data_ex *rgb_regamma = NULL;
1409+ bool ret = false;
1410+
1411+ if (regamma == NULL)
1412+ return false;
1413+
1414+ output_tf->type = TF_TYPE_DISTRIBUTED_POINTS;
1415+
1416+ rgb_user = kzalloc(sizeof(*rgb_user) * (GAMMA_RGB_256_ENTRIES + _EXTRA_POINTS),
1417+ GFP_KERNEL);
1418+ if (!rgb_user)
1419+ goto rgb_user_alloc_fail;
1420+
1421+ rgb_regamma = kzalloc(sizeof(*rgb_regamma) * (MAX_HW_POINTS + _EXTRA_POINTS),
1422+ GFP_KERNEL);
1423+ if (!rgb_regamma)
1424+ goto rgb_regamma_alloc_fail;
1425+
1426+ dividers.divider1 = dal_fixed31_32_from_fraction(3, 2);
1427+ dividers.divider2 = dal_fixed31_32_from_int(2);
1428+ dividers.divider3 = dal_fixed31_32_from_fraction(5, 2);
1429+
1430+ scale_user_regamma_ramp(rgb_user, &regamma->ramp, dividers);
1431+
1432+ if (regamma->flags.bits.applyDegamma == 1) {
1433+ apply_degamma_for_user_regamma(rgb_regamma, MAX_HW_POINTS);
1434+ copy_rgb_regamma_to_coordinates_x(coordinates_x,
1435+ MAX_HW_POINTS, rgb_regamma);
1436+ }
1437+
1438+ interpolate_user_regamma(MAX_HW_POINTS, rgb_user,
1439+ regamma->flags.bits.applyDegamma, tf_pts);
1440+
1441+ // no custom HDR curves!
1442+ tf_pts->end_exponent = 0;
1443+ tf_pts->x_point_at_y1_red = 1;
1444+ tf_pts->x_point_at_y1_green = 1;
1445+ tf_pts->x_point_at_y1_blue = 1;
1446+
1447+ // this function just clamps output to 0-1
1448+ build_new_custom_resulted_curve(MAX_HW_POINTS, tf_pts);
1449+
1450+ ret = true;
1451+
11641452 kfree(rgb_regamma);
11651453 rgb_regamma_alloc_fail:
11661454 kfree(rgb_user);
@@ -1192,19 +1480,19 @@ bool mod_color_calculate_degamma_params(struct dc_transfer_func *input_tf, · 25 unmodified lines
11921480
11931481 input_tf->type = TF_TYPE_DISTRIBUTED_POINTS;
11941482
1195− rgb_user = kzalloc(sizeof(*rgb_user) * (ramp->num_entries + _EXTRA_POINTS),
1196− GFP_KERNEL);
1483+ rgb_user = kvzalloc(sizeof(*rgb_user) * (ramp->num_entries + _EXTRA_POINTS),
1484+ GFP_KERNEL);
11971485 if (!rgb_user)
11981486 goto rgb_user_alloc_fail;
1199− curve = kzalloc(sizeof(*curve) * (MAX_HW_POINTS + _EXTRA_POINTS),
1200− GFP_KERNEL);
1487+ curve = kvzalloc(sizeof(*curve) * (MAX_HW_POINTS + _EXTRA_POINTS),
1488+ GFP_KERNEL);
12011489 if (!curve)
12021490 goto curve_alloc_fail;
1203− axix_x = kzalloc(sizeof(*axix_x) * (ramp->num_entries + _EXTRA_POINTS),
1204− GFP_KERNEL);
1491+ axix_x = kvzalloc(sizeof(*axix_x) * (ramp->num_entries + _EXTRA_POINTS),
1492+ GFP_KERNEL);
12051493 if (!axix_x)
12061494 goto axix_x_alloc_fail;
1207− coeff = kzalloc(sizeof(*coeff) * (MAX_HW_POINTS + _EXTRA_POINTS), GFP_KERNEL);
1495+ coeff = kvzalloc(sizeof(*coeff) * (MAX_HW_POINTS + _EXTRA_POINTS), GFP_KERNEL);
12081496 if (!coeff)
12091497 goto coeff_alloc_fail;
12101498
@@ -1246,13 +1534,13 @@ bool mod_color_calculate_degamma_params(struct dc_transfer_func *input_tf, · 35 unmodified lines
12461534
12471535 ret = true;
12481536
1249− kfree(coeff);
1537+ kvfree(coeff);
12501538 coeff_alloc_fail:
1251− kfree(axix_x);
1539+ kvfree(axix_x);
12521540 axix_x_alloc_fail:
1253− kfree(curve);
1541+ kvfree(curve);
12541542 curve_alloc_fail:
1255− kfree(rgb_user);
1543+ kvfree(rgb_user);
12561544 rgb_user_alloc_fail:
12571545
12581546 return ret;
@@ -1281,8 +1569,9 @@ bool mod_color_calculate_curve(enum dc_transfer_func_predefined trans, · 22 unmodified lines
12811569 }
12821570 ret = true;
12831571 } else if (trans == TRANSFER_FUNCTION_PQ) {
1284− rgb_regamma = kzalloc(sizeof(*rgb_regamma) * (MAX_HW_POINTS +
1285− _EXTRA_POINTS), GFP_KERNEL);
1572+ rgb_regamma = kvzalloc(sizeof(*rgb_regamma) *
1573+ (MAX_HW_POINTS + _EXTRA_POINTS),
1574+ GFP_KERNEL);
12861575 if (!rgb_regamma)
12871576 goto rgb_regamma_alloc_fail;
12881577 points->end_exponent = 7;
@@ -1302,11 +1591,12 @@ bool mod_color_calculate_curve(enum dc_transfer_func_predefined trans, · 13 unmodified lines
13021591 }
13031592 ret = true;
13041593
1305− kfree(rgb_regamma);
1594+ kvfree(rgb_regamma);
13061595 } else if (trans == TRANSFER_FUNCTION_SRGB ||
13071596 trans == TRANSFER_FUNCTION_BT709) {
1308− rgb_regamma = kzalloc(sizeof(*rgb_regamma) * (MAX_HW_POINTS +
1309− _EXTRA_POINTS), GFP_KERNEL);
1597+ rgb_regamma = kvzalloc(sizeof(*rgb_regamma) *
1598+ (MAX_HW_POINTS + _EXTRA_POINTS),
1599+ GFP_KERNEL);
13101600 if (!rgb_regamma)
13111601 goto rgb_regamma_alloc_fail;
13121602 points->end_exponent = 0;
@@ -1324,7 +1614,7 @@ bool mod_color_calculate_curve(enum dc_transfer_func_predefined trans, · 11 unmodified lines
13241614 }
13251615 ret = true;
13261616
1327− kfree(rgb_regamma);
1617+ kvfree(rgb_regamma);
13281618 }
13291619 rgb_regamma_alloc_fail:
13301620 return ret;
@@ -1348,8 +1638,9 @@ bool mod_color_calculate_degamma_curve(enum dc_transfer_func_predefined trans, · 17 unmodified lines
13481638 }
13491639 ret = true;
13501640 } else if (trans == TRANSFER_FUNCTION_PQ) {
1351− rgb_degamma = kzalloc(sizeof(*rgb_degamma) * (MAX_HW_POINTS +
1352− _EXTRA_POINTS), GFP_KERNEL);
1641+ rgb_degamma = kvzalloc(sizeof(*rgb_degamma) *
1642+ (MAX_HW_POINTS + _EXTRA_POINTS),
1643+ GFP_KERNEL);
13531644 if (!rgb_degamma)
13541645 goto rgb_degamma_alloc_fail;
13551646
@@ -1364,11 +1655,12 @@ bool mod_color_calculate_degamma_curve(enum dc_transfer_func_predefined trans, · 8 unmodified lines
13641655 }
13651656 ret = true;
13661657
1367− kfree(rgb_degamma);
1658+ kvfree(rgb_degamma);
13681659 } else if (trans == TRANSFER_FUNCTION_SRGB ||
13691660 trans == TRANSFER_FUNCTION_BT709) {
1370− rgb_degamma = kzalloc(sizeof(*rgb_degamma) * (MAX_HW_POINTS +
1371− _EXTRA_POINTS), GFP_KERNEL);
1661+ rgb_degamma = kvzalloc(sizeof(*rgb_degamma) *
1662+ (MAX_HW_POINTS + _EXTRA_POINTS),
1663+ GFP_KERNEL);
13721664 if (!rgb_degamma)
13731665 goto rgb_degamma_alloc_fail;
13741666
@@ -1382,7 +1674,7 @@ bool mod_color_calculate_degamma_curve(enum dc_transfer_func_predefined trans, · 7 unmodified lines
13821674 }
13831675 ret = true;
13841676
1385− kfree(rgb_degamma);
1677+ kvfree(rgb_degamma);
13861678 }
13871679 points->end_exponent = 0;
13881680 points->x_point_at_y1_red = 1;
drivers/gpu/drm/amd/display/modules/color/color_gamma.h+47−1
@@ -32,6 +32,47 @@ struct dc_transfer_func_distributed_points; · 31 unmodified lines
3232 struct dc_rgb_fixed;
3333 enum dc_transfer_func_predefined;
3434
35+/* For SetRegamma ADL interface support
36+ * Must match escape type
37+ */
38+union regamma_flags {
39+ unsigned int raw;
40+ struct {
41+ unsigned int gammaRampArray :1; // RegammaRamp is in use
42+ unsigned int gammaFromEdid :1; //gamma from edid is in use
43+ unsigned int gammaFromEdidEx :1; //gamma from edid is in use , but only for Display Id 1.2
44+ unsigned int gammaFromUser :1; //user custom gamma is used
45+ unsigned int coeffFromUser :1; //coeff. A0-A3 from user is in use
46+ unsigned int coeffFromEdid :1; //coeff. A0-A3 from edid is in use
47+ unsigned int applyDegamma :1; //flag for additional degamma correction in driver
48+ unsigned int gammaPredefinedSRGB :1; //flag for SRGB gamma
49+ unsigned int gammaPredefinedPQ :1; //flag for PQ gamma
50+ unsigned int gammaPredefinedPQ2084Interim :1; //flag for PQ gamma, lower max nits
51+ unsigned int gammaPredefined36 :1; //flag for 3.6 gamma
52+ unsigned int gammaPredefinedReset :1; //flag to return to previous gamma
53+ } bits;
54+};
55+
56+struct regamma_ramp {
57+ unsigned short gamma[256*3]; // gamma ramp packed in same way as OS windows ,r , g & b
58+};
59+
60+struct regamma_coeff {
61+ int gamma[3];
62+ int A0[3];
63+ int A1[3];
64+ int A2[3];
65+ int A3[3];
66+};
67+
68+struct regamma_lut {
69+ union regamma_flags flags;
70+ union {
71+ struct regamma_ramp ramp;
72+ struct regamma_coeff coeff;
73+ };
74+};
75+
3576 void setup_x_points_distribution(void);
3677 void precompute_pq(void);
3778 void precompute_de_pq(void);
@@ -45,9 +86,14 @@ bool mod_color_calculate_degamma_params(struct dc_transfer_func *output_tf, · 7 unmodified lines
4586 bool mod_color_calculate_curve(enum dc_transfer_func_predefined trans,
4687 struct dc_transfer_func_distributed_points *points);
4788
48−bool mod_color_calculate_degamma_curve(enum dc_transfer_func_predefined trans,
89+bool mod_color_calculate_degamma_curve(enum dc_transfer_func_predefined trans,
4990 struct dc_transfer_func_distributed_points *points);
5091
92+bool calculate_user_regamma_coeff(struct dc_transfer_func *output_tf,
93+ const struct regamma_lut *regamma);
94+
95+bool calculate_user_regamma_ramp(struct dc_transfer_func *output_tf,
96+ const struct regamma_lut *regamma);
5197
5298
5399 #endif /* COLOR_MOD_COLOR_GAMMA_H_ */
drivers/gpu/drm/amd/display/modules/stats/stats.c+43−22
@@ -115,18 +115,22 @@ struct mod_stats *mod_stats_create(struct dc *dc) · 114 unmodified lines
115115 &reg_data, sizeof(unsigned int), &flag))
116116 core_stats->enabled = reg_data;
117117
118− core_stats->entries = DAL_STATS_ENTRIES_REGKEY_DEFAULT;
119− if (dm_read_persistent_data(dc->ctx, NULL, NULL,
120− DAL_STATS_ENTRIES_REGKEY,
121− &reg_data, sizeof(unsigned int), &flag)) {
122− if (reg_data > DAL_STATS_ENTRIES_REGKEY_MAX)
123− core_stats->entries = DAL_STATS_ENTRIES_REGKEY_MAX;
124− else
125− core_stats->entries = reg_data;
126− }
118+ if (core_stats->enabled) {
119+ core_stats->entries = DAL_STATS_ENTRIES_REGKEY_DEFAULT;
120+ if (dm_read_persistent_data(dc->ctx, NULL, NULL,
121+ DAL_STATS_ENTRIES_REGKEY,
122+ &reg_data, sizeof(unsigned int), &flag)) {
123+ if (reg_data > DAL_STATS_ENTRIES_REGKEY_MAX)
124+ core_stats->entries = DAL_STATS_ENTRIES_REGKEY_MAX;
125+ else
126+ core_stats->entries = reg_data;
127+ }
127128
128− core_stats->time = kzalloc(sizeof(struct stats_time_cache) * core_stats->entries,
129− GFP_KERNEL);
129+ core_stats->time = kzalloc(sizeof(struct stats_time_cache) * core_stats->entries,
130+ GFP_KERNEL);
131+ } else {
132+ core_stats->entries = 0;
133+ }
130134
131135 if (core_stats->time == NULL)
132136 goto fail_construct;
@@ -187,7 +191,7 @@ void mod_stats_dump(struct mod_stats *mod_stats) · 54 unmodified lines
187191
188192 for (int i = 0; i < core_stats->index && i < core_stats->entries; i++) {
189193 dm_logger_write(logger, LOG_PROFILING,
190− "%u %u %u %u %u %u %u %u %u %u %u %u %u %u %u %u %u %u %u\n",
194+ "%u %u %u %u %u %u %u %u %u %u %u %u %u %u %u %u %u %u %u",
191195 time[i].render_time_in_us,
192196 time[i].avg_render_time_in_us_last_ten,
193197 time[i].min_window,
@@ -227,7 +231,7 @@ void mod_stats_reset_data(struct mod_stats *mod_stats) · 33 unmodified lines
227231 memset(core_stats->time, 0,
228232 sizeof(struct stats_time_cache) * core_stats->entries);
229233
230− core_stats->index = 0;
234+ core_stats->index = 1;
231235 }
232236
233237 void mod_stats_update_flip(struct mod_stats *mod_stats,
@@ -250,7 +254,7 @@ void mod_stats_update_flip(struct mod_stats *mod_stats, · 16 unmodified lines
250254
251255 time[index].flip_timestamp_in_ns = timestamp_in_ns;
252256 time[index].render_time_in_us =
253− timestamp_in_ns - time[index - 1].flip_timestamp_in_ns;
257+ (timestamp_in_ns - time[index - 1].flip_timestamp_in_ns) / 1000;
254258
255259 if (index >= 10) {
256260 for (unsigned int i = 0; i < 10; i++)
@@ -261,10 +265,12 @@ void mod_stats_update_flip(struct mod_stats *mod_stats, · 4 unmodified lines
261265
262266 if (time[index].num_vsync_between_flips > 0)
263267 time[index].vsync_to_flip_time_in_us =
264− timestamp_in_ns - time[index].vupdate_timestamp_in_ns;
268+ (timestamp_in_ns -
269+ time[index].vupdate_timestamp_in_ns) / 1000;
265270 else
266271 time[index].vsync_to_flip_time_in_us =
267− timestamp_in_ns - time[index - 1].vupdate_timestamp_in_ns;
272+ (timestamp_in_ns -
273+ time[index - 1].vupdate_timestamp_in_ns) / 1000;
268274
269275 core_stats->index++;
270276 }
@@ -275,6 +281,8 @@ void mod_stats_update_vupdate(struct mod_stats *mod_stats, · 4 unmodified lines
275281 struct core_stats *core_stats = NULL;
276282 struct stats_time_cache *time = NULL;
277283 unsigned int index = 0;
284+ unsigned int num_vsyncs = 0;
285+ unsigned int prev_vsync_in_ns = 0;
278286
279287 if (mod_stats == NULL)
280288 return;
@@ -286,14 +294,27 @@ void mod_stats_update_vupdate(struct mod_stats *mod_stats, · 5 unmodified lines
286294
287295 time = core_stats->time;
288296 index = core_stats->index;
297+ num_vsyncs = time[index].num_vsync_between_flips;
298+
299+ if (num_vsyncs < MOD_STATS_NUM_VSYNCS) {
300+ if (num_vsyncs == 0) {
301+ prev_vsync_in_ns =
302+ time[index - 1].vupdate_timestamp_in_ns;
303+
304+ time[index].flip_to_vsync_time_in_us =
305+ (timestamp_in_ns -
306+ time[index - 1].flip_timestamp_in_ns) /
307+ 1000;
308+ } else {
309+ prev_vsync_in_ns =
310+ time[index].vupdate_timestamp_in_ns;
311+ }
289312
290− time[index].vupdate_timestamp_in_ns = timestamp_in_ns;
291− if (time[index].num_vsync_between_flips < MOD_STATS_NUM_VSYNCS)
292− time[index].v_sync_time_in_us[time[index].num_vsync_between_flips] =
293− timestamp_in_ns - time[index - 1].vupdate_timestamp_in_ns;
294− time[index].flip_to_vsync_time_in_us =
295− timestamp_in_ns - time[index - 1].flip_timestamp_in_ns;
313+ time[index].v_sync_time_in_us[num_vsyncs] =
314+ (timestamp_in_ns - prev_vsync_in_ns) / 1000;
315+ }
296316
317+ time[index].vupdate_timestamp_in_ns = timestamp_in_ns;
297318 time[index].num_vsync_between_flips++;
298319 }
299320
drivers/gpu/drm/amd/include/amd_shared.h+20−0
@@ -109,6 +109,26 @@ enum amd_powergating_state { · 108 unmodified lines
109109 #define AMD_PG_SUPPORT_GFX_PIPELINE (1 << 12)
110110 #define AMD_PG_SUPPORT_MMHUB (1 << 13)
111111
112+enum PP_FEATURE_MASK {
113+ PP_SCLK_DPM_MASK = 0x1,
114+ PP_MCLK_DPM_MASK = 0x2,
115+ PP_PCIE_DPM_MASK = 0x4,
116+ PP_SCLK_DEEP_SLEEP_MASK = 0x8,
117+ PP_POWER_CONTAINMENT_MASK = 0x10,
118+ PP_UVD_HANDSHAKE_MASK = 0x20,
119+ PP_SMC_VOLTAGE_CONTROL_MASK = 0x40,
120+ PP_VBI_TIME_SUPPORT_MASK = 0x80,
121+ PP_ULV_MASK = 0x100,
122+ PP_ENABLE_GFX_CG_THRU_SMU = 0x200,
123+ PP_CLOCK_STRETCH_MASK = 0x400,
124+ PP_OD_FUZZY_FAN_CONTROL_MASK = 0x800,
125+ PP_SOCCLK_DPM_MASK = 0x1000,
126+ PP_DCEFCLK_DPM_MASK = 0x2000,
127+ PP_OVERDRIVE_MASK = 0x4000,
128+ PP_GFXOFF_MASK = 0x8000,
129+ PP_ACG_MASK = 0x10000,
130+};
131+
112132 struct amd_ip_funcs {
113133 /* Name of IP block */
114134 char *name;
drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_1_0_offset.h+16−3
@@ -3895,6 +3895,10 @@ · 3894 unmodified lines
38953895 #define mmCM0_CM_MEM_PWR_CTRL_BASE_IDX 2
38963896 #define mmCM0_CM_MEM_PWR_STATUS 0x0d33
38973897 #define mmCM0_CM_MEM_PWR_STATUS_BASE_IDX 2
3898+#define mmCM0_CM_TEST_DEBUG_INDEX 0x0d35
3899+#define mmCM0_CM_TEST_DEBUG_INDEX_BASE_IDX 2
3900+#define mmCM0_CM_TEST_DEBUG_DATA 0x0d36
3901+#define mmCM0_CM_TEST_DEBUG_DATA_BASE_IDX 2
38983902
38993903
39003904 // addressBlock: dce_dc_dpp0_dispdec_dpp_dcperfmon_dc_perfmon_dispdec
@@ -4367,7 +4371,10 @@ · 466 unmodified lines
43674371 #define mmCM1_CM_MEM_PWR_CTRL_BASE_IDX 2
43684372 #define mmCM1_CM_MEM_PWR_STATUS 0x0e4e
43694373 #define mmCM1_CM_MEM_PWR_STATUS_BASE_IDX 2
4370−
4374+#define mmCM1_CM_TEST_DEBUG_INDEX 0x0e50
4375+#define mmCM1_CM_TEST_DEBUG_INDEX_BASE_IDX 2
4376+#define mmCM1_CM_TEST_DEBUG_DATA 0x0e51
4377+#define mmCM1_CM_TEST_DEBUG_DATA_BASE_IDX 2
43714378
43724379 // addressBlock: dce_dc_dpp1_dispdec_dpp_dcperfmon_dc_perfmon_dispdec
43734380 // base address: 0x399c
@@ -4839,7 +4846,10 @@ · 465 unmodified lines
48394846 #define mmCM2_CM_MEM_PWR_CTRL_BASE_IDX 2
48404847 #define mmCM2_CM_MEM_PWR_STATUS 0x0f69
48414848 #define mmCM2_CM_MEM_PWR_STATUS_BASE_IDX 2
4842−
4849+#define mmCM2_CM_TEST_DEBUG_INDEX 0x0f6b
4850+#define mmCM2_CM_TEST_DEBUG_INDEX_BASE_IDX 2
4851+#define mmCM2_CM_TEST_DEBUG_DATA 0x0f6c
4852+#define mmCM2_CM_TEST_DEBUG_DATA_BASE_IDX 2
48434853
48444854 // addressBlock: dce_dc_dpp2_dispdec_dpp_dcperfmon_dc_perfmon_dispdec
48454855 // base address: 0x3e08
@@ -5311,7 +5321,10 @@ · 465 unmodified lines
53115321 #define mmCM3_CM_MEM_PWR_CTRL_BASE_IDX 2
53125322 #define mmCM3_CM_MEM_PWR_STATUS 0x1084
53135323 #define mmCM3_CM_MEM_PWR_STATUS_BASE_IDX 2
5314−
5324+#define mmCM3_CM_TEST_DEBUG_INDEX 0x1086
5325+#define mmCM3_CM_TEST_DEBUG_INDEX_BASE_IDX 2
5326+#define mmCM3_CM_TEST_DEBUG_DATA 0x1087
5327+#define mmCM3_CM_TEST_DEBUG_DATA_BASE_IDX 2
53155328
53165329 // addressBlock: dce_dc_dpp3_dispdec_dpp_dcperfmon_dc_perfmon_dispdec
53175330 // base address: 0x4274
drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_1_0_sh_mask.h+8−0
@@ -14049,6 +14049,14 @@ · 14048 unmodified lines
1404914049 #define CM0_CM_MEM_PWR_STATUS__RGAM_MEM_PWR_STATE__SHIFT 0x2
1405014050 #define CM0_CM_MEM_PWR_STATUS__SHARED_MEM_PWR_STATE_MASK 0x00000003L
1405114051 #define CM0_CM_MEM_PWR_STATUS__RGAM_MEM_PWR_STATE_MASK 0x0000000CL
14052+//CM0_CM_TEST_DEBUG_INDEX
14053+#define CM0_CM_TEST_DEBUG_INDEX__CM_TEST_DEBUG_INDEX__SHIFT 0x0
14054+#define CM0_CM_TEST_DEBUG_INDEX__CM_TEST_DEBUG_WRITE_EN__SHIFT 0x8
14055+#define CM0_CM_TEST_DEBUG_INDEX__CM_TEST_DEBUG_INDEX_MASK 0x000000FFL
14056+#define CM0_CM_TEST_DEBUG_INDEX__CM_TEST_DEBUG_WRITE_EN_MASK 0x00000100L
14057+//CM0_CM_TEST_DEBUG_DATA
14058+#define CM0_CM_TEST_DEBUG_DATA__CM_TEST_DEBUG_DATA__SHIFT 0x0
14059+#define CM0_CM_TEST_DEBUG_DATA__CM_TEST_DEBUG_DATA_MASK 0xFFFFFFFFL
1405214060
1405314061
1405414062 // addressBlock: dce_dc_dpp0_dispdec_dpp_dcperfmon_dc_perfmon_dispdec
drivers/gpu/drm/amd/include/asic_reg/df/df_1_7_default.h+26−0
@@ -0,0 +1,26 @@
1+/*
2+ * Copyright (C) 2018 Advanced Micro Devices, Inc.
3+ *
4+ * Permission is hereby granted, free of charge, to any person obtaining a
5+ * copy of this software and associated documentation files (the "Software"),
6+ * to deal in the Software without restriction, including without limitation
7+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8+ * and/or sell copies of the Software, and to permit persons to whom the
9+ * Software is furnished to do so, subject to the following conditions:
10+ *
11+ * The above copyright notice and this permission notice shall be included
12+ * in all copies or substantial portions of the Software.
13+ *
14+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
15+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17+ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
18+ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
19+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
20+ */
21+#ifndef _df_1_7_DEFAULT_HEADER
22+#define _df_1_7_DEFAULT_HEADER
23+
24+#define mmFabricConfigAccessControl_DEFAULT 0x00000000
25+
26+#endif
drivers/gpu/drm/amd/include/asic_reg/df/df_1_7_offset.h+33−0
@@ -0,0 +1,33 @@
1+/*
2+ * Copyright (C) 2018 Advanced Micro Devices, Inc.
3+ *
4+ * Permission is hereby granted, free of charge, to any person obtaining a
5+ * copy of this software and associated documentation files (the "Software"),
6+ * to deal in the Software without restriction, including without limitation
7+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8+ * and/or sell copies of the Software, and to permit persons to whom the
9+ * Software is furnished to do so, subject to the following conditions:
10+ *
11+ * The above copyright notice and this permission notice shall be included
12+ * in all copies or substantial portions of the Software.
13+ *
14+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
15+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17+ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
18+ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
19+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
20+ */
21+#ifndef _df_1_7_OFFSET_HEADER
22+#define _df_1_7_OFFSET_HEADER
23+
24+#define mmFabricConfigAccessControl 0x0410
25+#define mmFabricConfigAccessControl_BASE_IDX 0
26+
27+#define mmDF_PIE_AON0_DfGlobalClkGater 0x00fc
28+#define mmDF_PIE_AON0_DfGlobalClkGater_BASE_IDX 0
29+
30+#define mmDF_CS_AON0_DramBaseAddress0 0x0044
31+#define mmDF_CS_AON0_DramBaseAddress0_BASE_IDX 0
32+
33+#endif
drivers/gpu/drm/amd/include/asic_reg/df/df_1_7_sh_mask.h+48−0
@@ -0,0 +1,48 @@
1+/*
2+ * Copyright (C) 2018 Advanced Micro Devices, Inc.
3+ *
4+ * Permission is hereby granted, free of charge, to any person obtaining a
5+ * copy of this software and associated documentation files (the "Software"),
6+ * to deal in the Software without restriction, including without limitation
7+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8+ * and/or sell copies of the Software, and to permit persons to whom the
9+ * Software is furnished to do so, subject to the following conditions:
10+ *
11+ * The above copyright notice and this permission notice shall be included
12+ * in all copies or substantial portions of the Software.
13+ *
14+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
15+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17+ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
18+ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
19+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
20+ */
21+#ifndef _df_1_7_SH_MASK_HEADER
22+#define _df_1_7_SH_MASK_HEADER
23+
24+/* FabricConfigAccessControl */
25+#define FabricConfigAccessControl__CfgRegInstAccEn__SHIFT 0x0
26+#define FabricConfigAccessControl__CfgRegInstAccRegLock__SHIFT 0x1
27+#define FabricConfigAccessControl__CfgRegInstID__SHIFT 0x10
28+#define FabricConfigAccessControl__CfgRegInstAccEn_MASK 0x00000001L
29+#define FabricConfigAccessControl__CfgRegInstAccRegLock_MASK 0x00000002L
30+#define FabricConfigAccessControl__CfgRegInstID_MASK 0x00FF0000L
31+
32+/* DF_PIE_AON0_DfGlobalClkGater */
33+#define DF_PIE_AON0_DfGlobalClkGater__MGCGMode__SHIFT 0x0
34+#define DF_PIE_AON0_DfGlobalClkGater__MGCGMode_MASK 0x0000000FL
35+
36+/* DF_CS_AON0_DramBaseAddress0 */
37+#define DF_CS_AON0_DramBaseAddress0__AddrRngVal__SHIFT 0x0
38+#define DF_CS_AON0_DramBaseAddress0__LgcyMmioHoleEn__SHIFT 0x1
39+#define DF_CS_AON0_DramBaseAddress0__IntLvNumChan__SHIFT 0x4
40+#define DF_CS_AON0_DramBaseAddress0__IntLvAddrSel__SHIFT 0x8
41+#define DF_CS_AON0_DramBaseAddress0__DramBaseAddr__SHIFT 0xc
42+#define DF_CS_AON0_DramBaseAddress0__AddrRngVal_MASK 0x00000001L
43+#define DF_CS_AON0_DramBaseAddress0__LgcyMmioHoleEn_MASK 0x00000002L
44+#define DF_CS_AON0_DramBaseAddress0__IntLvNumChan_MASK 0x000000F0L
45+#define DF_CS_AON0_DramBaseAddress0__IntLvAddrSel_MASK 0x00000700L
46+#define DF_CS_AON0_DramBaseAddress0__DramBaseAddr_MASK 0xFFFFF000L
47+
48+#endif
drivers/gpu/drm/amd/include/atombios.h+7−0
@@ -632,6 +632,13 @@ typedef struct _COMPUTE_MEMORY_CLOCK_PARAM_PARAMETERS_V2_2 · 631 unmodified lines
632632 ULONG ulReserved;
633633 }COMPUTE_MEMORY_CLOCK_PARAM_PARAMETERS_V2_2;
634634
635+typedef struct _COMPUTE_MEMORY_CLOCK_PARAM_PARAMETERS_V2_3
636+{
637+ COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V4 ulClock;
638+ USHORT usMclk_fcw_frac; //fractional divider of fcw = usSclk_fcw_frac/65536
639+ USHORT usMclk_fcw_int; //integer divider of fcwc
640+}COMPUTE_MEMORY_CLOCK_PARAM_PARAMETERS_V2_3;
641+
635642 //Input parameter of DynamicMemorySettingsTable
636643 //when ATOM_COMPUTE_CLOCK_FREQ.ulComputeClockFlag = COMPUTE_MEMORY_PLL_PARAM
637644 typedef struct _DYNAMICE_MEMORY_SETTINGS_PARAMETER
drivers/gpu/drm/amd/include/atomfirmware.h+168−2
@@ -501,6 +501,32 @@ enum atom_cooling_solution_id{ · 500 unmodified lines
501501 LIQUID_COOLING = 0x01
502502 };
503503
504+struct atom_firmware_info_v3_2 {
505+ struct atom_common_table_header table_header;
506+ uint32_t firmware_revision;
507+ uint32_t bootup_sclk_in10khz;
508+ uint32_t bootup_mclk_in10khz;
509+ uint32_t firmware_capability; // enum atombios_firmware_capability
510+ uint32_t main_call_parser_entry; /* direct address of main parser call in VBIOS binary. */
511+ uint32_t bios_scratch_reg_startaddr; // 1st bios scratch register dword address
512+ uint16_t bootup_vddc_mv;
513+ uint16_t bootup_vddci_mv;
514+ uint16_t bootup_mvddc_mv;
515+ uint16_t bootup_vddgfx_mv;
516+ uint8_t mem_module_id;
517+ uint8_t coolingsolution_id; /*0: Air cooling; 1: Liquid cooling ... */
518+ uint8_t reserved1[2];
519+ uint32_t mc_baseaddr_high;
520+ uint32_t mc_baseaddr_low;
521+ uint8_t board_i2c_feature_id; // enum of atom_board_i2c_feature_id_def
522+ uint8_t board_i2c_feature_gpio_id; // i2c id find in gpio_lut data table gpio_id
523+ uint8_t board_i2c_feature_slave_addr;
524+ uint8_t reserved3;
525+ uint16_t bootup_mvddq_mv;
526+ uint16_t bootup_mvpp_mv;
527+ uint32_t zfbstartaddrin16mb;
528+ uint32_t reserved2[3];
529+};
504530
505531 /*
506532 ***************************************************************************
@@ -1169,7 +1195,29 @@ struct atom_gfx_info_v2_2 · 662 unmodified lines
11691195 uint32_t rlc_gpu_timer_refclk;
11701196 };
11711197
1172−
1198+struct atom_gfx_info_v2_3 {
1199+ struct atom_common_table_header table_header;
1200+ uint8_t gfxip_min_ver;
1201+ uint8_t gfxip_max_ver;
1202+ uint8_t max_shader_engines;
1203+ uint8_t max_tile_pipes;
1204+ uint8_t max_cu_per_sh;
1205+ uint8_t max_sh_per_se;
1206+ uint8_t max_backends_per_se;
1207+ uint8_t max_texture_channel_caches;
1208+ uint32_t regaddr_cp_dma_src_addr;
1209+ uint32_t regaddr_cp_dma_src_addr_hi;
1210+ uint32_t regaddr_cp_dma_dst_addr;
1211+ uint32_t regaddr_cp_dma_dst_addr_hi;
1212+ uint32_t regaddr_cp_dma_command;
1213+ uint32_t regaddr_cp_status;
1214+ uint32_t regaddr_rlc_gpu_clock_32;
1215+ uint32_t rlc_gpu_timer_refclk;
1216+ uint8_t active_cu_per_sh;
1217+ uint8_t active_rb_per_se;
1218+ uint16_t gcgoldenoffset;
1219+ uint32_t rm21_sram_vmin_value;
1220+};
11731221
11741222 /*
11751223 ***************************************************************************
@@ -1198,6 +1246,76 @@ struct atom_smu_info_v3_1 · 22 unmodified lines
11981246 uint8_t fw_ctf_polarity; // GPIO polarity for CTF
11991247 };
12001248
1249+struct atom_smu_info_v3_2 {
1250+ struct atom_common_table_header table_header;
1251+ uint8_t smuip_min_ver;
1252+ uint8_t smuip_max_ver;
1253+ uint8_t smu_rsd1;
1254+ uint8_t gpuclk_ss_mode;
1255+ uint16_t sclk_ss_percentage;
1256+ uint16_t sclk_ss_rate_10hz;
1257+ uint16_t gpuclk_ss_percentage; // in unit of 0.001%
1258+ uint16_t gpuclk_ss_rate_10hz;
1259+ uint32_t core_refclk_10khz;
1260+ uint8_t ac_dc_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for AC/DC switching, =0xff means invalid
1261+ uint8_t ac_dc_polarity; // GPIO polarity for AC/DC switching
1262+ uint8_t vr0hot_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for VR0 HOT event, =0xff means invalid
1263+ uint8_t vr0hot_polarity; // GPIO polarity for VR0 HOT event
1264+ uint8_t vr1hot_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for VR1 HOT event , =0xff means invalid
1265+ uint8_t vr1hot_polarity; // GPIO polarity for VR1 HOT event
1266+ uint8_t fw_ctf_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for CTF, =0xff means invalid
1267+ uint8_t fw_ctf_polarity; // GPIO polarity for CTF
1268+ uint8_t pcc_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for PCC, =0xff means invalid
1269+ uint8_t pcc_gpio_polarity; // GPIO polarity for CTF
1270+ uint16_t smugoldenoffset;
1271+ uint32_t gpupll_vco_freq_10khz;
1272+ uint32_t bootup_smnclk_10khz;
1273+ uint32_t bootup_socclk_10khz;
1274+ uint32_t bootup_mp0clk_10khz;
1275+ uint32_t bootup_mp1clk_10khz;
1276+ uint32_t bootup_lclk_10khz;
1277+ uint32_t bootup_dcefclk_10khz;
1278+ uint32_t ctf_threshold_override_value;
1279+ uint32_t reserved[5];
1280+};
1281+
1282+struct atom_smu_info_v3_3 {
1283+ struct atom_common_table_header table_header;
1284+ uint8_t smuip_min_ver;
1285+ uint8_t smuip_max_ver;
1286+ uint8_t smu_rsd1;
1287+ uint8_t gpuclk_ss_mode;
1288+ uint16_t sclk_ss_percentage;
1289+ uint16_t sclk_ss_rate_10hz;
1290+ uint16_t gpuclk_ss_percentage; // in unit of 0.001%
1291+ uint16_t gpuclk_ss_rate_10hz;
1292+ uint32_t core_refclk_10khz;
1293+ uint8_t ac_dc_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for AC/DC switching, =0xff means invalid
1294+ uint8_t ac_dc_polarity; // GPIO polarity for AC/DC switching
1295+ uint8_t vr0hot_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for VR0 HOT event, =0xff means invalid
1296+ uint8_t vr0hot_polarity; // GPIO polarity for VR0 HOT event
1297+ uint8_t vr1hot_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for VR1 HOT event , =0xff means invalid
1298+ uint8_t vr1hot_polarity; // GPIO polarity for VR1 HOT event
1299+ uint8_t fw_ctf_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for CTF, =0xff means invalid
1300+ uint8_t fw_ctf_polarity; // GPIO polarity for CTF
1301+ uint8_t pcc_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for PCC, =0xff means invalid
1302+ uint8_t pcc_gpio_polarity; // GPIO polarity for CTF
1303+ uint16_t smugoldenoffset;
1304+ uint32_t gpupll_vco_freq_10khz;
1305+ uint32_t bootup_smnclk_10khz;
1306+ uint32_t bootup_socclk_10khz;
1307+ uint32_t bootup_mp0clk_10khz;
1308+ uint32_t bootup_mp1clk_10khz;
1309+ uint32_t bootup_lclk_10khz;
1310+ uint32_t bootup_dcefclk_10khz;
1311+ uint32_t ctf_threshold_override_value;
1312+ uint32_t syspll3_0_vco_freq_10khz;
1313+ uint32_t syspll3_1_vco_freq_10khz;
1314+ uint32_t bootup_fclk_10khz;
1315+ uint32_t bootup_waflclk_10khz;
1316+ uint32_t reserved[3];
1317+};
1318+
12011319 /*
12021320 ***************************************************************************
12031321 Data Table smc_dpm_info structure
@@ -1283,7 +1401,6 @@ struct atom_smc_dpm_info_v4_1 · 79 unmodified lines
12831401 uint32_t boardreserved[10];
12841402 };
12851403
1286−
12871404 /*
12881405 ***************************************************************************
12891406 Data Table asic_profiling_info structure
@@ -1864,6 +1981,55 @@ enum atom_smu9_syspll0_clock_id · 574 unmodified lines
18641981 SMU9_SYSPLL0_DISPCLK_ID = 11, // DISPCLK
18651982 };
18661983
1984+enum atom_smu11_syspll_id {
1985+ SMU11_SYSPLL0_ID = 0,
1986+ SMU11_SYSPLL1_0_ID = 1,
1987+ SMU11_SYSPLL1_1_ID = 2,
1988+ SMU11_SYSPLL1_2_ID = 3,
1989+ SMU11_SYSPLL2_ID = 4,
1990+ SMU11_SYSPLL3_0_ID = 5,
1991+ SMU11_SYSPLL3_1_ID = 6,
1992+};
1993+
1994+
1995+enum atom_smu11_syspll0_clock_id {
1996+ SMU11_SYSPLL0_SOCCLK_ID = 0, // SOCCLK
1997+ SMU11_SYSPLL0_MP0CLK_ID = 1, // MP0CLK
1998+ SMU11_SYSPLL0_DCLK_ID = 2, // DCLK
1999+ SMU11_SYSPLL0_VCLK_ID = 3, // VCLK
2000+ SMU11_SYSPLL0_ECLK_ID = 4, // ECLK
2001+ SMU11_SYSPLL0_DCEFCLK_ID = 5, // DCEFCLK
2002+};
2003+
2004+
2005+enum atom_smu11_syspll1_0_clock_id {
2006+ SMU11_SYSPLL1_0_UCLKA_ID = 0, // UCLK_a
2007+};
2008+
2009+enum atom_smu11_syspll1_1_clock_id {
2010+ SMU11_SYSPLL1_0_UCLKB_ID = 0, // UCLK_b
2011+};
2012+
2013+enum atom_smu11_syspll1_2_clock_id {
2014+ SMU11_SYSPLL1_0_FCLK_ID = 0, // FCLK
2015+};
2016+
2017+enum atom_smu11_syspll2_clock_id {
2018+ SMU11_SYSPLL2_GFXCLK_ID = 0, // GFXCLK
2019+};
2020+
2021+enum atom_smu11_syspll3_0_clock_id {
2022+ SMU11_SYSPLL3_0_WAFCLK_ID = 0, // WAFCLK
2023+ SMU11_SYSPLL3_0_DISPCLK_ID = 1, // DISPCLK
2024+ SMU11_SYSPLL3_0_DPREFCLK_ID = 2, // DPREFCLK
2025+};
2026+
2027+enum atom_smu11_syspll3_1_clock_id {
2028+ SMU11_SYSPLL3_1_MP1CLK_ID = 0, // MP1CLK
2029+ SMU11_SYSPLL3_1_SMNCLK_ID = 1, // SMNCLK
2030+ SMU11_SYSPLL3_1_LCLK_ID = 2, // LCLK
2031+};
2032+
18672033 struct atom_get_smu_clock_info_output_parameters_v3_1
18682034 {
18692035 union {
drivers/gpu/drm/amd/include/cgs_common.h+0−170
@@ -42,20 +42,6 @@ enum cgs_ind_reg { · 41 unmodified lines
4242 CGS_IND_REG__AUDIO_ENDPT
4343 };
4444
45−/**
46− * enum cgs_engine - Engines that can be statically power-gated
47− */
48−enum cgs_engine {
49− CGS_ENGINE__UVD,
50− CGS_ENGINE__VCE,
51− CGS_ENGINE__VP8,
52− CGS_ENGINE__ACP_DMA,
53− CGS_ENGINE__ACP_DSP0,
54− CGS_ENGINE__ACP_DSP1,
55− CGS_ENGINE__ISP,
56− /* ... */
57−};
58−
5945 /*
6046 * enum cgs_ucode_id - Firmware types for different IPs
6147 */
@@ -76,17 +62,6 @@ enum cgs_ucode_id { · 14 unmodified lines
7662 CGS_UCODE_ID_MAXIMUM,
7763 };
7864
79−/*
80− * enum cgs_resource_type - GPU resource type
81− */
82−enum cgs_resource_type {
83− CGS_RESOURCE_TYPE_MMIO = 0,
84− CGS_RESOURCE_TYPE_FB,
85− CGS_RESOURCE_TYPE_IO,
86− CGS_RESOURCE_TYPE_DOORBELL,
87− CGS_RESOURCE_TYPE_ROM,
88−};
89−
9065 /**
9166 * struct cgs_firmware_info - Firmware information
9267 */
@@ -104,17 +79,6 @@ struct cgs_firmware_info { · 11 unmodified lines
10479 bool is_kicker;
10580 };
10681
107−struct cgs_mode_info {
108− uint32_t refresh_rate;
109− uint32_t vblank_time_us;
110−};
111−
112−struct cgs_display_info {
113− uint32_t display_count;
114− uint32_t active_display_mask;
115− struct cgs_mode_info *mode_info;
116−};
117−
11882 typedef unsigned long cgs_handle_t;
11983
12084 /**
@@ -170,119 +134,18 @@ typedef void (*cgs_write_ind_register_t)(struct cgs_device *cgs_device, enum cgs · 49 unmodified lines
170134 #define CGS_WREG32_FIELD_IND(device, space, reg, field, val) \
171135 cgs_write_ind_register(device, space, ix##reg, (cgs_read_ind_register(device, space, ix##reg) & ~CGS_REG_FIELD_MASK(reg, field)) | (val) << CGS_REG_FIELD_SHIFT(reg, field))
172136
173−/**
174− * cgs_get_pci_resource() - provide access to a device resource (PCI BAR)
175− * @cgs_device: opaque device handle
176− * @resource_type: Type of Resource (MMIO, IO, ROM, FB, DOORBELL)
177− * @size: size of the region
178− * @offset: offset from the start of the region
179− * @resource_base: base address (not including offset) returned
180− *
181− * Return: 0 on success, -errno otherwise
182− */
183−typedef int (*cgs_get_pci_resource_t)(struct cgs_device *cgs_device,
184− enum cgs_resource_type resource_type,
185− uint64_t size,
186− uint64_t offset,
187− uint64_t *resource_base);
188−
189−/**
190− * cgs_atom_get_data_table() - Get a pointer to an ATOM BIOS data table
191− * @cgs_device: opaque device handle
192− * @table: data table index
193− * @size: size of the table (output, may be NULL)
194− * @frev: table format revision (output, may be NULL)
195− * @crev: table content revision (output, may be NULL)
196− *
197− * Return: Pointer to start of the table, or NULL on failure
198− */
199−typedef const void *(*cgs_atom_get_data_table_t)(
200− struct cgs_device *cgs_device, unsigned table,
201− uint16_t *size, uint8_t *frev, uint8_t *crev);
202−
203−/**
204− * cgs_atom_get_cmd_table_revs() - Get ATOM BIOS command table revisions
205− * @cgs_device: opaque device handle
206− * @table: data table index
207− * @frev: table format revision (output, may be NULL)
208− * @crev: table content revision (output, may be NULL)
209− *
210− * Return: 0 on success, -errno otherwise
211− */
212−typedef int (*cgs_atom_get_cmd_table_revs_t)(struct cgs_device *cgs_device, unsigned table,
213− uint8_t *frev, uint8_t *crev);
214−
215−/**
216− * cgs_atom_exec_cmd_table() - Execute an ATOM BIOS command table
217− * @cgs_device: opaque device handle
218− * @table: command table index
219− * @args: arguments
220− *
221− * Return: 0 on success, -errno otherwise
222− */
223−typedef int (*cgs_atom_exec_cmd_table_t)(struct cgs_device *cgs_device,
224− unsigned table, void *args);
225−
226−/**
227− * cgs_get_firmware_info - Get the firmware information from core driver
228− * @cgs_device: opaque device handle
229− * @type: the firmware type
230− * @info: returend firmware information
231− *
232− * Return: 0 on success, -errno otherwise
233− */
234137 typedef int (*cgs_get_firmware_info)(struct cgs_device *cgs_device,
235138 enum cgs_ucode_id type,
236139 struct cgs_firmware_info *info);
237140
238−typedef int (*cgs_rel_firmware)(struct cgs_device *cgs_device,
239− enum cgs_ucode_id type);
240−
241−typedef int(*cgs_set_powergating_state)(struct cgs_device *cgs_device,
242− enum amd_ip_block_type block_type,
243− enum amd_powergating_state state);
244−
245−typedef int(*cgs_set_clockgating_state)(struct cgs_device *cgs_device,
246− enum amd_ip_block_type block_type,
247− enum amd_clockgating_state state);
248−
249−typedef int(*cgs_get_active_displays_info)(
250− struct cgs_device *cgs_device,
251− struct cgs_display_info *info);
252−
253−typedef int (*cgs_notify_dpm_enabled)(struct cgs_device *cgs_device, bool enabled);
254−
255−typedef int (*cgs_is_virtualization_enabled_t)(void *cgs_device);
256−
257−typedef int (*cgs_enter_safe_mode)(struct cgs_device *cgs_device, bool en);
258−
259−typedef void (*cgs_lock_grbm_idx)(struct cgs_device *cgs_device, bool lock);
260−
261141 struct cgs_ops {
262142 /* MMIO access */
263143 cgs_read_register_t read_register;
264144 cgs_write_register_t write_register;
265145 cgs_read_ind_register_t read_ind_register;
266146 cgs_write_ind_register_t write_ind_register;
267− /* PCI resources */
268− cgs_get_pci_resource_t get_pci_resource;
269− /* ATOM BIOS */
270− cgs_atom_get_data_table_t atom_get_data_table;
271− cgs_atom_get_cmd_table_revs_t atom_get_cmd_table_revs;
272− cgs_atom_exec_cmd_table_t atom_exec_cmd_table;
273147 /* Firmware Info */
274148 cgs_get_firmware_info get_firmware_info;
275− cgs_rel_firmware rel_firmware;
276− /* cg pg interface*/
277− cgs_set_powergating_state set_powergating_state;
278− cgs_set_clockgating_state set_clockgating_state;
279− /* display manager */
280− cgs_get_active_displays_info get_active_displays_info;
281− /* notify dpm enabled */
282− cgs_notify_dpm_enabled notify_dpm_enabled;
283− cgs_is_virtualization_enabled_t is_virtualization_enabled;
284− cgs_enter_safe_mode enter_safe_mode;
285− cgs_lock_grbm_idx lock_grbm_idx;
286149 };
287150
288151 struct cgs_os_ops; /* To be define in OS-specific CGS header */
@@ -309,40 +172,7 @@ struct cgs_device · 20 unmodified lines
309172 #define cgs_write_ind_register(dev,space,index,value) \
310173 CGS_CALL(write_ind_register,dev,space,index,value)
311174
312−#define cgs_atom_get_data_table(dev,table,size,frev,crev) \
313− CGS_CALL(atom_get_data_table,dev,table,size,frev,crev)
314−#define cgs_atom_get_cmd_table_revs(dev,table,frev,crev) \
315− CGS_CALL(atom_get_cmd_table_revs,dev,table,frev,crev)
316−#define cgs_atom_exec_cmd_table(dev,table,args) \
317− CGS_CALL(atom_exec_cmd_table,dev,table,args)
318−
319175 #define cgs_get_firmware_info(dev, type, info) \
320176 CGS_CALL(get_firmware_info, dev, type, info)
321−#define cgs_rel_firmware(dev, type) \
322− CGS_CALL(rel_firmware, dev, type)
323−#define cgs_set_powergating_state(dev, block_type, state) \
324− CGS_CALL(set_powergating_state, dev, block_type, state)
325−#define cgs_set_clockgating_state(dev, block_type, state) \
326− CGS_CALL(set_clockgating_state, dev, block_type, state)
327−#define cgs_notify_dpm_enabled(dev, enabled) \
328− CGS_CALL(notify_dpm_enabled, dev, enabled)
329−
330−#define cgs_get_active_displays_info(dev, info) \
331− CGS_CALL(get_active_displays_info, dev, info)
332−
333−#define cgs_get_pci_resource(cgs_device, resource_type, size, offset, \
334− resource_base) \
335− CGS_CALL(get_pci_resource, cgs_device, resource_type, size, offset, \
336− resource_base)
337−
338−#define cgs_is_virtualization_enabled(cgs_device) \
339− CGS_CALL(is_virtualization_enabled, cgs_device)
340−
341−#define cgs_enter_safe_mode(cgs_device, en) \
342− CGS_CALL(enter_safe_mode, cgs_device, en)
343−
344−#define cgs_lock_grbm_idx(cgs_device, lock) \
345− CGS_CALL(lock_grbm_idx, cgs_device, lock)
346−
347177
348178 #endif /* _CGS_COMMON_H */
drivers/gpu/drm/amd/include/kgd_pp_interface.h+1−12
@@ -94,6 +94,7 @@ enum pp_clock_type { · 93 unmodified lines
9494 PP_PCIE,
9595 OD_SCLK,
9696 OD_MCLK,
97+ OD_RANGE,
9798 };
9899
99100 enum amd_pp_sensors {
@@ -149,13 +150,6 @@ struct pp_states_info { · 49 unmodified lines
149150 uint32_t states[16];
150151 };
151152
152−struct pp_gpu_power {
153− uint32_t vddc_power;
154− uint32_t vddci_power;
155− uint32_t max_gpu_power;
156− uint32_t average_gpu_power;
157−};
158−
159153 #define PP_GROUP_MASK 0xF0000000
160154 #define PP_GROUP_SHIFT 28
161155
@@ -246,11 +240,6 @@ struct amd_pm_funcs { · 84 unmodified lines
246240 int (*load_firmware)(void *handle);
247241 int (*wait_for_fw_loading_complete)(void *handle);
248242 int (*set_clockgating_by_smu)(void *handle, uint32_t msg_id);
249− int (*notify_smu_memory_info)(void *handle, uint32_t virtual_addr_low,
250− uint32_t virtual_addr_hi,
251− uint32_t mc_addr_low,
252− uint32_t mc_addr_hi,
253− uint32_t size);
254243 int (*set_power_limit)(void *handle, uint32_t n);
255244 int (*get_power_limit)(void *handle, uint32_t *limit, bool default_limit);
256245 /* export to DC */
drivers/gpu/drm/amd/powerplay/amd_powerplay.c+158−331
@@ -25,30 +25,16 @@ · 24 unmodified lines
2525 #include <linux/kernel.h>
2626 #include <linux/gfp.h>
2727 #include <linux/slab.h>
28+#include <linux/firmware.h>
2829 #include "amd_shared.h"
2930 #include "amd_powerplay.h"
3031 #include "power_state.h"
3132 #include "amdgpu.h"
3233 #include "hwmgr.h"
3334
34−#define PP_DPM_DISABLED 0xCCCC
35−
36−static int pp_dpm_dispatch_tasks(void *handle, enum amd_pp_task task_id,
37− enum amd_pm_state_type *user_state);
3835
3936 static const struct amd_pm_funcs pp_dpm_funcs;
4037
41−static inline int pp_check(struct pp_hwmgr *hwmgr)
42−{
43− if (hwmgr == NULL || hwmgr->smumgr_funcs == NULL)
44− return -EINVAL;
45−
46− if (hwmgr->pm_en == 0 || hwmgr->hwmgr_func == NULL)
47− return PP_DPM_DISABLED;
48−
49− return 0;
50−}
51−
5238 static int amd_powerplay_create(struct amdgpu_device *adev)
5339 {
5440 struct pp_hwmgr *hwmgr;
@@ -61,19 +47,21 @@ static int amd_powerplay_create(struct amdgpu_device *adev) · 6 unmodified lines
6147 return -ENOMEM;
6248
6349 hwmgr->adev = adev;
64− hwmgr->pm_en = (amdgpu_dpm != 0 && !amdgpu_sriov_vf(adev)) ? true : false;
50+ hwmgr->not_vf = !amdgpu_sriov_vf(adev);
51+ hwmgr->pm_en = (amdgpu_dpm && hwmgr->not_vf) ? true : false;
6552 hwmgr->device = amdgpu_cgs_create_device(adev);
6653 mutex_init(&hwmgr->smu_lock);
6754 hwmgr->chip_family = adev->family;
6855 hwmgr->chip_id = adev->asic_type;
69− hwmgr->feature_mask = amdgpu_pp_feature_mask;
56+ hwmgr->feature_mask = adev->powerplay.pp_feature;
57+ hwmgr->display_config = &adev->pm.pm_display_cfg;
7058 adev->powerplay.pp_handle = hwmgr;
7159 adev->powerplay.pp_funcs = &pp_dpm_funcs;
7260 return 0;
7361 }
7462
7563
76−static int amd_powerplay_destroy(struct amdgpu_device *adev)
64+static void amd_powerplay_destroy(struct amdgpu_device *adev)
7765 {
7866 struct pp_hwmgr *hwmgr = adev->powerplay.pp_handle;
7967
@@ -82,8 +70,6 @@ static int amd_powerplay_destroy(struct amdgpu_device *adev) · 2 unmodified lines
8270
8371 kfree(hwmgr);
8472 hwmgr = NULL;
85−
86− return 0;
8773 }
8874
8975 static int pp_early_init(void *handle)
@@ -109,18 +95,9 @@ static int pp_sw_init(void *handle) · 19 unmodified lines
10995 struct pp_hwmgr *hwmgr = adev->powerplay.pp_handle;
11096 int ret = 0;
11197
112− ret = pp_check(hwmgr);
113−
114− if (ret >= 0) {
115− if (hwmgr->smumgr_funcs->smu_init == NULL)
116− return -EINVAL;
117−
118− ret = hwmgr->smumgr_funcs->smu_init(hwmgr);
98+ ret = hwmgr_sw_init(hwmgr);
11999
120− phm_register_irq_handlers(hwmgr);
121−
122− pr_debug("amdgpu: powerplay sw initialized\n");
123− }
100+ pr_debug("powerplay sw init %s\n", ret ? "failed" : "successfully");
124101
125102 return ret;
126103 }
@@ -129,16 +106,14 @@ static int pp_sw_fini(void *handle) · 2 unmodified lines
129106 {
130107 struct amdgpu_device *adev = handle;
131108 struct pp_hwmgr *hwmgr = adev->powerplay.pp_handle;
132− int ret = 0;
133109
134− ret = pp_check(hwmgr);
135− if (ret >= 0) {
136− if (hwmgr->smumgr_funcs->smu_fini != NULL)
137− hwmgr->smumgr_funcs->smu_fini(hwmgr);
138− }
110+ hwmgr_sw_fini(hwmgr);
139111
140− if (adev->firmware.load_type == AMDGPU_FW_LOAD_SMU)
112+ if (adev->firmware.load_type == AMDGPU_FW_LOAD_SMU) {
113+ release_firmware(adev->pm.fw);
114+ adev->pm.fw = NULL;
141115 amdgpu_ucode_fini_bo(adev);
116+ }
142117
143118 return 0;
144119 }
@@ -152,55 +127,76 @@ static int pp_hw_init(void *handle) · 7 unmodified lines
152127 if (adev->firmware.load_type == AMDGPU_FW_LOAD_SMU)
153128 amdgpu_ucode_init_bo(adev);
154129
155− ret = pp_check(hwmgr);
130+ ret = hwmgr_hw_init(hwmgr);
156131
157− if (ret >= 0) {
158− if (hwmgr->smumgr_funcs->start_smu == NULL)
159− return -EINVAL;
132+ if (ret)
133+ pr_err("powerplay hw init failed\n");
160134
161− if (hwmgr->smumgr_funcs->start_smu(hwmgr)) {
162− pr_err("smc start failed\n");
163− hwmgr->smumgr_funcs->smu_fini(hwmgr);
164− return -EINVAL;
165− }
166− if (ret == PP_DPM_DISABLED)
167− goto exit;
168− ret = hwmgr_hw_init(hwmgr);
169− if (ret)
170− goto exit;
171− }
172135 return ret;
173−exit:
174− hwmgr->pm_en = 0;
175− cgs_notify_dpm_enabled(hwmgr->device, false);
176− return 0;
177−
178136 }
179137
180138 static int pp_hw_fini(void *handle)
181139 {
182140 struct amdgpu_device *adev = handle;
183141 struct pp_hwmgr *hwmgr = adev->powerplay.pp_handle;
184− int ret = 0;
185142
186− ret = pp_check(hwmgr);
187− if (ret == 0)
188− hwmgr_hw_fini(hwmgr);
143+ hwmgr_hw_fini(hwmgr);
189144
190145 return 0;
191146 }
192147
148+static void pp_reserve_vram_for_smu(struct amdgpu_device *adev)
149+{
150+ int r = -EINVAL;
151+ void *cpu_ptr = NULL;
152+ uint64_t gpu_addr;
153+ struct pp_hwmgr *hwmgr = adev->powerplay.pp_handle;
154+
155+ if (amdgpu_bo_create_kernel(adev, adev->pm.smu_prv_buffer_size,
156+ PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT,
157+ &adev->pm.smu_prv_buffer,
158+ &gpu_addr,
159+ &cpu_ptr)) {
160+ DRM_ERROR("amdgpu: failed to create smu prv buffer\n");
161+ return;
162+ }
163+
164+ if (hwmgr->hwmgr_func->notify_cac_buffer_info)
165+ r = hwmgr->hwmgr_func->notify_cac_buffer_info(hwmgr,
166+ lower_32_bits((unsigned long)cpu_ptr),
167+ upper_32_bits((unsigned long)cpu_ptr),
168+ lower_32_bits(gpu_addr),
169+ upper_32_bits(gpu_addr),
170+ adev->pm.smu_prv_buffer_size);
171+
172+ if (r) {
173+ amdgpu_bo_free_kernel(&adev->pm.smu_prv_buffer, NULL, NULL);
174+ adev->pm.smu_prv_buffer = NULL;
175+ DRM_ERROR("amdgpu: failed to notify SMU buffer address\n");
176+ }
177+}
178+
193179 static int pp_late_init(void *handle)
194180 {
195181 struct amdgpu_device *adev = handle;
196182 struct pp_hwmgr *hwmgr = adev->powerplay.pp_handle;
197− int ret = 0;
198−
199− ret = pp_check(hwmgr);
183+ int ret;
200184
201− if (ret == 0)
202− pp_dpm_dispatch_tasks(hwmgr,
185+ if (hwmgr && hwmgr->pm_en) {
186+ mutex_lock(&hwmgr->smu_lock);
187+ hwmgr_handle_task(hwmgr,
203188 AMD_PP_TASK_COMPLETE_INIT, NULL);
189+ mutex_unlock(&hwmgr->smu_lock);
190+ }
191+ if (adev->pm.smu_prv_buffer_size != 0)
192+ pp_reserve_vram_for_smu(adev);
193+
194+ if (hwmgr->hwmgr_func->gfx_off_control &&
195+ (hwmgr->feature_mask & PP_GFXOFF_MASK)) {
196+ ret = hwmgr->hwmgr_func->gfx_off_control(hwmgr, true);
197+ if (ret)
198+ pr_err("gfx off enabling failed!\n");
199+ }
204200
205201 return 0;
206202 }
@@ -209,6 +205,8 @@ static void pp_late_fini(void *handle) · 2 unmodified lines
209205 {
210206 struct amdgpu_device *adev = handle;
211207
208+ if (adev->pm.smu_prv_buffer)
209+ amdgpu_bo_free_kernel(&adev->pm.smu_prv_buffer, NULL, NULL);
212210 amd_powerplay_destroy(adev);
213211 }
214212
@@ -233,12 +231,18 @@ static int pp_set_powergating_state(void *handle, · 18 unmodified lines
233231 {
234232 struct amdgpu_device *adev = handle;
235233 struct pp_hwmgr *hwmgr = adev->powerplay.pp_handle;
236− int ret = 0;
234+ int ret;
237235
238− ret = pp_check(hwmgr);
236+ if (!hwmgr || !hwmgr->pm_en)
237+ return 0;
239238
240− if (ret)
241− return ret;
239+ if (hwmgr->hwmgr_func->gfx_off_control) {
240+ /* Enable/disable GFX off through SMU */
241+ ret = hwmgr->hwmgr_func->gfx_off_control(hwmgr,
242+ state == AMD_PG_STATE_GATE);
243+ if (ret)
244+ pr_err("gfx off control failed!\n");
245+ }
242246
243247 if (hwmgr->hwmgr_func->enable_per_cu_power_gating == NULL) {
244248 pr_info("%s was not implemented.\n", __func__);
@@ -254,38 +258,16 @@ static int pp_suspend(void *handle) · 9 unmodified lines
254258 {
255259 struct amdgpu_device *adev = handle;
256260 struct pp_hwmgr *hwmgr = adev->powerplay.pp_handle;
257− int ret = 0;
258261
259− ret = pp_check(hwmgr);
260− if (ret == 0)
261− hwmgr_hw_suspend(hwmgr);
262− return 0;
262+ return hwmgr_suspend(hwmgr);
263263 }
264264
265265 static int pp_resume(void *handle)
266266 {
267267 struct amdgpu_device *adev = handle;
268268 struct pp_hwmgr *hwmgr = adev->powerplay.pp_handle;
269− int ret;
270−
271− ret = pp_check(hwmgr);
272−
273− if (ret < 0)
274− return ret;
275−
276− if (hwmgr->smumgr_funcs->start_smu == NULL)
277− return -EINVAL;
278−
279− if (hwmgr->smumgr_funcs->start_smu(hwmgr)) {
280− pr_err("smc start failed\n");
281− hwmgr->smumgr_funcs->smu_fini(hwmgr);
282− return -EINVAL;
283− }
284−
285− if (ret == PP_DPM_DISABLED)
286− return 0;
287269
288− return hwmgr_hw_resume(hwmgr);
270+ return hwmgr_resume(hwmgr);
289271 }
290272
291273 static int pp_set_clockgating_state(void *handle,
@@ -334,12 +316,9 @@ static int pp_dpm_fw_loading_complete(void *handle) · 42 unmodified lines
334316 static int pp_set_clockgating_by_smu(void *handle, uint32_t msg_id)
335317 {
336318 struct pp_hwmgr *hwmgr = handle;
337− int ret = 0;
338−
339− ret = pp_check(hwmgr);
340319
341− if (ret)
342− return ret;
320+ if (!hwmgr || !hwmgr->pm_en)
321+ return -EINVAL;
343322
344323 if (hwmgr->hwmgr_func->update_clock_gatings == NULL) {
345324 pr_info("%s was not implemented.\n", __func__);
@@ -362,10 +341,10 @@ static void pp_dpm_en_umd_pstate(struct pp_hwmgr *hwmgr, · 16 unmodified lines
362341 if (*level & profile_mode_mask) {
363342 hwmgr->saved_dpm_level = hwmgr->dpm_level;
364343 hwmgr->en_umd_pstate = true;
365− cgs_set_clockgating_state(hwmgr->device,
344+ amdgpu_device_ip_set_clockgating_state(hwmgr->adev,
366345 AMD_IP_BLOCK_TYPE_GFX,
367346 AMD_CG_STATE_UNGATE);
368− cgs_set_powergating_state(hwmgr->device,
347+ amdgpu_device_ip_set_powergating_state(hwmgr->adev,
369348 AMD_IP_BLOCK_TYPE_GFX,
370349 AMD_PG_STATE_UNGATE);
371350 }
@@ -375,10 +354,10 @@ static void pp_dpm_en_umd_pstate(struct pp_hwmgr *hwmgr, · 3 unmodified lines
375354 if (*level == AMD_DPM_FORCED_LEVEL_PROFILE_EXIT)
376355 *level = hwmgr->saved_dpm_level;
377356 hwmgr->en_umd_pstate = false;
378− cgs_set_clockgating_state(hwmgr->device,
357+ amdgpu_device_ip_set_clockgating_state(hwmgr->adev,
379358 AMD_IP_BLOCK_TYPE_GFX,
380359 AMD_CG_STATE_GATE);
381− cgs_set_powergating_state(hwmgr->device,
360+ amdgpu_device_ip_set_powergating_state(hwmgr->adev,
382361 AMD_IP_BLOCK_TYPE_GFX,
383362 AMD_PG_STATE_GATE);
384363 }
@@ -389,12 +368,9 @@ static int pp_dpm_force_performance_level(void *handle, · 4 unmodified lines
389368 enum amd_dpm_forced_level level)
390369 {
391370 struct pp_hwmgr *hwmgr = handle;
392− int ret = 0;
393371
394− ret = pp_check(hwmgr);
395−
396− if (ret)
397− return ret;
372+ if (!hwmgr || !hwmgr->pm_en)
373+ return -EINVAL;
398374
399375 if (level == hwmgr->dpm_level)
400376 return 0;
@@ -412,13 +388,10 @@ static enum amd_dpm_forced_level pp_dpm_get_performance_level( · 11 unmodified lines
412388 void *handle)
413389 {
414390 struct pp_hwmgr *hwmgr = handle;
415− int ret = 0;
416391 enum amd_dpm_forced_level level;
417392
418− ret = pp_check(hwmgr);
419−
420− if (ret)
421− return ret;
393+ if (!hwmgr || !hwmgr->pm_en)
394+ return -EINVAL;
422395
423396 mutex_lock(&hwmgr->smu_lock);
424397 level = hwmgr->dpm_level;
@@ -429,13 +402,10 @@ static enum amd_dpm_forced_level pp_dpm_get_performance_level( · 4 unmodified lines
429402 static uint32_t pp_dpm_get_sclk(void *handle, bool low)
430403 {
431404 struct pp_hwmgr *hwmgr = handle;
432− int ret = 0;
433405 uint32_t clk = 0;
434406
435− ret = pp_check(hwmgr);
436−
437− if (ret)
438− return ret;
407+ if (!hwmgr || !hwmgr->pm_en)
408+ return 0;
439409
440410 if (hwmgr->hwmgr_func->get_sclk == NULL) {
441411 pr_info("%s was not implemented.\n", __func__);
@@ -450,13 +420,10 @@ static uint32_t pp_dpm_get_sclk(void *handle, bool low) · 8 unmodified lines
450420 static uint32_t pp_dpm_get_mclk(void *handle, bool low)
451421 {
452422 struct pp_hwmgr *hwmgr = handle;
453− int ret = 0;
454423 uint32_t clk = 0;
455424
456− ret = pp_check(hwmgr);
457−
458− if (ret)
459− return ret;
425+ if (!hwmgr || !hwmgr->pm_en)
426+ return 0;
460427
461428 if (hwmgr->hwmgr_func->get_mclk == NULL) {
462429 pr_info("%s was not implemented.\n", __func__);
@@ -471,11 +438,8 @@ static uint32_t pp_dpm_get_mclk(void *handle, bool low) · 8 unmodified lines
471438 static void pp_dpm_powergate_vce(void *handle, bool gate)
472439 {
473440 struct pp_hwmgr *hwmgr = handle;
474− int ret = 0;
475441
476− ret = pp_check(hwmgr);
477−
478− if (ret)
442+ if (!hwmgr || !hwmgr->pm_en)
479443 return;
480444
481445 if (hwmgr->hwmgr_func->powergate_vce == NULL) {
@@ -490,11 +454,8 @@ static void pp_dpm_powergate_vce(void *handle, bool gate) · 8 unmodified lines
490454 static void pp_dpm_powergate_uvd(void *handle, bool gate)
491455 {
492456 struct pp_hwmgr *hwmgr = handle;
493− int ret = 0;
494−
495− ret = pp_check(hwmgr);
496457
497− if (ret)
458+ if (!hwmgr || !hwmgr->pm_en)
498459 return;
499460
500461 if (hwmgr->hwmgr_func->powergate_uvd == NULL) {
@@ -512,10 +473,8 @@ static int pp_dpm_dispatch_tasks(void *handle, enum amd_pp_task task_id, · 11 unmodified lines
512473 int ret = 0;
513474 struct pp_hwmgr *hwmgr = handle;
514475
515− ret = pp_check(hwmgr);
516−
517− if (ret)
518− return ret;
476+ if (!hwmgr || !hwmgr->pm_en)
477+ return -EINVAL;
519478
520479 mutex_lock(&hwmgr->smu_lock);
521480 ret = hwmgr_handle_task(hwmgr, task_id, user_state);
@@ -528,15 +487,9 @@ static enum amd_pm_state_type pp_dpm_get_current_power_state(void *handle) · 6 unmodified lines
528487 {
529488 struct pp_hwmgr *hwmgr = handle;
530489 struct pp_power_state *state;
531− int ret = 0;
532490 enum amd_pm_state_type pm_type;
533491
534− ret = pp_check(hwmgr);
535−
536− if (ret)
537− return ret;
538−
539− if (hwmgr->current_ps == NULL)
492+ if (!hwmgr || !hwmgr->pm_en || !hwmgr->current_ps)
540493 return -EINVAL;
541494
542495 mutex_lock(&hwmgr->smu_lock);
@@ -568,11 +521,8 @@ static enum amd_pm_state_type pp_dpm_get_current_power_state(void *handle) · 25 unmodified lines
568521 static void pp_dpm_set_fan_control_mode(void *handle, uint32_t mode)
569522 {
570523 struct pp_hwmgr *hwmgr = handle;
571− int ret = 0;
572−
573− ret = pp_check(hwmgr);
574524
575− if (ret)
525+ if (!hwmgr || !hwmgr->pm_en)
576526 return;
577527
578528 if (hwmgr->hwmgr_func->set_fan_control_mode == NULL) {
@@ -587,13 +537,10 @@ static void pp_dpm_set_fan_control_mode(void *handle, uint32_t mode) · 8 unmodified lines
587537 static uint32_t pp_dpm_get_fan_control_mode(void *handle)
588538 {
589539 struct pp_hwmgr *hwmgr = handle;
590− int ret = 0;
591540 uint32_t mode = 0;
592541
593− ret = pp_check(hwmgr);
594−
595− if (ret)
596− return ret;
542+ if (!hwmgr || !hwmgr->pm_en)
543+ return 0;
597544
598545 if (hwmgr->hwmgr_func->get_fan_control_mode == NULL) {
599546 pr_info("%s was not implemented.\n", __func__);
@@ -610,10 +557,8 @@ static int pp_dpm_set_fan_speed_percent(void *handle, uint32_t percent) · 10 unmodified lines
610557 struct pp_hwmgr *hwmgr = handle;
611558 int ret = 0;
612559
613− ret = pp_check(hwmgr);
614−
615− if (ret)
616− return ret;
560+ if (!hwmgr || !hwmgr->pm_en)
561+ return -EINVAL;
617562
618563 if (hwmgr->hwmgr_func->set_fan_speed_percent == NULL) {
619564 pr_info("%s was not implemented.\n", __func__);
@@ -630,10 +575,8 @@ static int pp_dpm_get_fan_speed_percent(void *handle, uint32_t *speed) · 10 unmodified lines
630575 struct pp_hwmgr *hwmgr = handle;
631576 int ret = 0;
632577
633− ret = pp_check(hwmgr);
634−
635− if (ret)
636− return ret;
578+ if (!hwmgr || !hwmgr->pm_en)
579+ return -EINVAL;
637580
638581 if (hwmgr->hwmgr_func->get_fan_speed_percent == NULL) {
639582 pr_info("%s was not implemented.\n", __func__);
@@ -651,10 +594,8 @@ static int pp_dpm_get_fan_speed_rpm(void *handle, uint32_t *rpm) · 11 unmodified lines
651594 struct pp_hwmgr *hwmgr = handle;
652595 int ret = 0;
653596
654− ret = pp_check(hwmgr);
655−
656− if (ret)
657− return ret;
597+ if (!hwmgr || !hwmgr->pm_en)
598+ return -EINVAL;
658599
659600 if (hwmgr->hwmgr_func->get_fan_speed_rpm == NULL)
660601 return -EINVAL;
@@ -670,16 +611,10 @@ static int pp_dpm_get_pp_num_states(void *handle, · 9 unmodified lines
670611 {
671612 struct pp_hwmgr *hwmgr = handle;
672613 int i;
673− int ret = 0;
674614
675615 memset(data, 0, sizeof(*data));
676616
677− ret = pp_check(hwmgr);
678−
679− if (ret)
680− return ret;
681−
682− if (hwmgr->ps == NULL)
617+ if (!hwmgr || !hwmgr->pm_en ||!hwmgr->ps)
683618 return -EINVAL;
684619
685620 mutex_lock(&hwmgr->smu_lock);
@@ -713,15 +648,9 @@ static int pp_dpm_get_pp_num_states(void *handle, · 27 unmodified lines
713648 static int pp_dpm_get_pp_table(void *handle, char **table)
714649 {
715650 struct pp_hwmgr *hwmgr = handle;
716− int ret = 0;
717651 int size = 0;
718652
719− ret = pp_check(hwmgr);
720−
721− if (ret)
722− return ret;
723−
724− if (!hwmgr->soft_pp_table)
653+ if (!hwmgr || !hwmgr->pm_en ||!hwmgr->soft_pp_table)
725654 return -EINVAL;
726655
727656 mutex_lock(&hwmgr->smu_lock);
@@ -736,10 +665,6 @@ static int amd_powerplay_reset(void *handle) · 8 unmodified lines
736665 struct pp_hwmgr *hwmgr = handle;
737666 int ret;
738667
739− ret = pp_check(hwmgr);
740− if (ret)
741− return ret;
742−
743668 ret = hwmgr_hw_fini(hwmgr);
744669 if (ret)
745670 return ret;
@@ -754,40 +679,38 @@ static int amd_powerplay_reset(void *handle) · 8 unmodified lines
754679 static int pp_dpm_set_pp_table(void *handle, const char *buf, size_t size)
755680 {
756681 struct pp_hwmgr *hwmgr = handle;
757− int ret = 0;
682+ int ret = -ENOMEM;
758683
759− ret = pp_check(hwmgr);
760−
761− if (ret)
762− return ret;
684+ if (!hwmgr || !hwmgr->pm_en)
685+ return -EINVAL;
763686
764687 mutex_lock(&hwmgr->smu_lock);
765688 if (!hwmgr->hardcode_pp_table) {
766689 hwmgr->hardcode_pp_table = kmemdup(hwmgr->soft_pp_table,
767690 hwmgr->soft_pp_table_size,
768691 GFP_KERNEL);
769− if (!hwmgr->hardcode_pp_table) {
770− mutex_unlock(&hwmgr->smu_lock);
771− return -ENOMEM;
772− }
692+ if (!hwmgr->hardcode_pp_table)
693+ goto err;
773694 }
774695
775696 memcpy(hwmgr->hardcode_pp_table, buf, size);
776697
777698 hwmgr->soft_pp_table = hwmgr->hardcode_pp_table;
778− mutex_unlock(&hwmgr->smu_lock);
779699
780700 ret = amd_powerplay_reset(handle);
781701 if (ret)
782− return ret;
702+ goto err;
783703
784704 if (hwmgr->hwmgr_func->avfs_control) {
785705 ret = hwmgr->hwmgr_func->avfs_control(hwmgr, false);
786706 if (ret)
787− return ret;
707+ goto err;
788708 }
789−
709+ mutex_unlock(&hwmgr->smu_lock);
790710 return 0;
711+err:
712+ mutex_unlock(&hwmgr->smu_lock);
713+ return ret;
791714 }
792715
793716 static int pp_dpm_force_clock_level(void *handle,
@@ -796,10 +719,8 @@ static int pp_dpm_force_clock_level(void *handle, · 2 unmodified lines
796719 struct pp_hwmgr *hwmgr = handle;
797720 int ret = 0;
798721
799− ret = pp_check(hwmgr);
800−
801− if (ret)
802− return ret;
722+ if (!hwmgr || !hwmgr->pm_en)
723+ return -EINVAL;
803724
804725 if (hwmgr->hwmgr_func->force_clock_level == NULL) {
805726 pr_info("%s was not implemented.\n", __func__);
@@ -820,10 +741,8 @@ static int pp_dpm_print_clock_levels(void *handle, · 14 unmodified lines
820741 struct pp_hwmgr *hwmgr = handle;
821742 int ret = 0;
822743
823− ret = pp_check(hwmgr);
824−
825− if (ret)
826− return ret;
744+ if (!hwmgr || !hwmgr->pm_en)
745+ return -EINVAL;
827746
828747 if (hwmgr->hwmgr_func->print_clock_levels == NULL) {
829748 pr_info("%s was not implemented.\n", __func__);
@@ -840,10 +759,8 @@ static int pp_dpm_get_sclk_od(void *handle) · 10 unmodified lines
840759 struct pp_hwmgr *hwmgr = handle;
841760 int ret = 0;
842761
843− ret = pp_check(hwmgr);
844−
845− if (ret)
846− return ret;
762+ if (!hwmgr || !hwmgr->pm_en)
763+ return -EINVAL;
847764
848765 if (hwmgr->hwmgr_func->get_sclk_od == NULL) {
849766 pr_info("%s was not implemented.\n", __func__);
@@ -860,10 +777,8 @@ static int pp_dpm_set_sclk_od(void *handle, uint32_t value) · 10 unmodified lines
860777 struct pp_hwmgr *hwmgr = handle;
861778 int ret = 0;
862779
863− ret = pp_check(hwmgr);
864−
865− if (ret)
866− return ret;
780+ if (!hwmgr || !hwmgr->pm_en)
781+ return -EINVAL;
867782
868783 if (hwmgr->hwmgr_func->set_sclk_od == NULL) {
869784 pr_info("%s was not implemented.\n", __func__);
@@ -881,10 +796,8 @@ static int pp_dpm_get_mclk_od(void *handle) · 11 unmodified lines
881796 struct pp_hwmgr *hwmgr = handle;
882797 int ret = 0;
883798
884− ret = pp_check(hwmgr);
885−
886− if (ret)
887− return ret;
799+ if (!hwmgr || !hwmgr->pm_en)
800+ return -EINVAL;
888801
889802 if (hwmgr->hwmgr_func->get_mclk_od == NULL) {
890803 pr_info("%s was not implemented.\n", __func__);
@@ -901,10 +814,8 @@ static int pp_dpm_set_mclk_od(void *handle, uint32_t value) · 10 unmodified lines
901814 struct pp_hwmgr *hwmgr = handle;
902815 int ret = 0;
903816
904− ret = pp_check(hwmgr);
905−
906− if (ret)
907− return ret;
817+ if (!hwmgr || !hwmgr->pm_en)
818+ return -EINVAL;
908819
909820 if (hwmgr->hwmgr_func->set_mclk_od == NULL) {
910821 pr_info("%s was not implemented.\n", __func__);
@@ -922,11 +833,7 @@ static int pp_dpm_read_sensor(void *handle, int idx, · 11 unmodified lines
922833 struct pp_hwmgr *hwmgr = handle;
923834 int ret = 0;
924835
925− ret = pp_check(hwmgr);
926− if (ret)
927− return ret;
928−
929− if (value == NULL)
836+ if (!hwmgr || !hwmgr->pm_en || !value)
930837 return -EINVAL;
931838
932839 switch (idx) {
@@ -948,14 +855,11 @@ static struct amd_vce_state* · 15 unmodified lines
948855 pp_dpm_get_vce_clock_state(void *handle, unsigned idx)
949856 {
950857 struct pp_hwmgr *hwmgr = handle;
951− int ret = 0;
952−
953− ret = pp_check(hwmgr);
954858
955− if (ret)
859+ if (!hwmgr || !hwmgr->pm_en)
956860 return NULL;
957861
958− if (hwmgr && idx < hwmgr->num_vce_state_tables)
862+ if (idx < hwmgr->num_vce_state_tables)
959863 return &hwmgr->vce_states[idx];
960864 return NULL;
961865 }
@@ -964,7 +868,7 @@ static int pp_get_power_profile_mode(void *handle, char *buf) · 2 unmodified lines
964868 {
965869 struct pp_hwmgr *hwmgr = handle;
966870
967− if (!buf || pp_check(hwmgr))
871+ if (!hwmgr || !hwmgr->pm_en || !buf)
968872 return -EINVAL;
969873
970874 if (hwmgr->hwmgr_func->get_power_profile_mode == NULL) {
@@ -980,12 +884,12 @@ static int pp_set_power_profile_mode(void *handle, long *input, uint32_t size) · 9 unmodified lines
980884 struct pp_hwmgr *hwmgr = handle;
981885 int ret = -EINVAL;
982886
983− if (pp_check(hwmgr))
984− return -EINVAL;
887+ if (!hwmgr || !hwmgr->pm_en)
888+ return ret;
985889
986890 if (hwmgr->hwmgr_func->set_power_profile_mode == NULL) {
987891 pr_info("%s was not implemented.\n", __func__);
988− return -EINVAL;
892+ return ret;
989893 }
990894 mutex_lock(&hwmgr->smu_lock);
991895 if (hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_MANUAL)
@@ -998,7 +902,7 @@ static int pp_odn_edit_dpm_table(void *handle, uint32_t type, long *input, uint3 · 6 unmodified lines
998902 {
999903 struct pp_hwmgr *hwmgr = handle;
1000904
1001− if (pp_check(hwmgr))
905+ if (!hwmgr || !hwmgr->pm_en)
1002906 return -EINVAL;
1003907
1004908 if (hwmgr->hwmgr_func->odn_edit_dpm_table == NULL) {
@@ -1016,7 +920,7 @@ static int pp_dpm_switch_power_profile(void *handle, · 11 unmodified lines
1016920 long workload;
1017921 uint32_t index;
1018922
1019− if (pp_check(hwmgr))
923+ if (!hwmgr || !hwmgr->pm_en)
1020924 return -EINVAL;
1021925
1022926 if (hwmgr->hwmgr_func->set_power_profile_mode == NULL) {
@@ -1048,46 +952,12 @@ static int pp_dpm_switch_power_profile(void *handle, · 25 unmodified lines
1048952 return 0;
1049953 }
1050954
1051−static int pp_dpm_notify_smu_memory_info(void *handle,
1052− uint32_t virtual_addr_low,
1053− uint32_t virtual_addr_hi,
1054− uint32_t mc_addr_low,
1055− uint32_t mc_addr_hi,
1056− uint32_t size)
1057−{
1058− struct pp_hwmgr *hwmgr = handle;
1059− int ret = 0;
1060−
1061− ret = pp_check(hwmgr);
1062−
1063− if (ret)
1064− return ret;
1065−
1066− if (hwmgr->hwmgr_func->notify_cac_buffer_info == NULL) {
1067− pr_info("%s was not implemented.\n", __func__);
1068− return -EINVAL;
1069− }
1070−
1071− mutex_lock(&hwmgr->smu_lock);
1072−
1073− ret = hwmgr->hwmgr_func->notify_cac_buffer_info(hwmgr, virtual_addr_low,
1074− virtual_addr_hi, mc_addr_low, mc_addr_hi,
1075− size);
1076−
1077− mutex_unlock(&hwmgr->smu_lock);
1078−
1079− return ret;
1080−}
1081−
1082955 static int pp_set_power_limit(void *handle, uint32_t limit)
1083956 {
1084957 struct pp_hwmgr *hwmgr = handle;
1085− int ret = 0;
1086958
1087− ret = pp_check(hwmgr);
1088−
1089− if (ret)
1090− return ret;
959+ if (!hwmgr || !hwmgr->pm_en)
960+ return -EINVAL;
1091961
1092962 if (hwmgr->hwmgr_func->set_power_limit == NULL) {
1093963 pr_info("%s was not implemented.\n", __func__);
@@ -1104,20 +974,14 @@ static int pp_set_power_limit(void *handle, uint32_t limit) · 10 unmodified lines
1104974 hwmgr->hwmgr_func->set_power_limit(hwmgr, limit);
1105975 hwmgr->power_limit = limit;
1106976 mutex_unlock(&hwmgr->smu_lock);
1107− return ret;
977+ return 0;
1108978 }
1109979
1110980 static int pp_get_power_limit(void *handle, uint32_t *limit, bool default_limit)
1111981 {
1112982 struct pp_hwmgr *hwmgr = handle;
1113− int ret = 0;
1114−
1115− ret = pp_check(hwmgr);
1116983
1117− if (ret)
1118− return ret;
1119−
1120− if (limit == NULL)
984+ if (!hwmgr || !hwmgr->pm_en ||!limit)
1121985 return -EINVAL;
1122986
1123987 mutex_lock(&hwmgr->smu_lock);
@@ -1129,19 +993,16 @@ static int pp_get_power_limit(void *handle, uint32_t *limit, bool default_limit) · 5 unmodified lines
1129993
1130994 mutex_unlock(&hwmgr->smu_lock);
1131995
1132− return ret;
996+ return 0;
1133997 }
1134998
1135999 static int pp_display_configuration_change(void *handle,
11361000 const struct amd_pp_display_configuration *display_config)
11371001 {
11381002 struct pp_hwmgr *hwmgr = handle;
1139− int ret = 0;
11401003
1141− ret = pp_check(hwmgr);
1142−
1143− if (ret)
1144− return ret;
1004+ if (!hwmgr || !hwmgr->pm_en)
1005+ return -EINVAL;
11451006
11461007 mutex_lock(&hwmgr->smu_lock);
11471008 phm_store_dal_configuration_data(hwmgr, display_config);
@@ -1155,12 +1016,7 @@ static int pp_get_display_power_level(void *handle, · 7 unmodified lines
11551016 struct pp_hwmgr *hwmgr = handle;
11561017 int ret = 0;
11571018
1158− ret = pp_check(hwmgr);
1159−
1160− if (ret)
1161− return ret;
1162−
1163− if (output == NULL)
1019+ if (!hwmgr || !hwmgr->pm_en ||!output)
11641020 return -EINVAL;
11651021
11661022 mutex_lock(&hwmgr->smu_lock);
@@ -1177,10 +1033,8 @@ static int pp_get_current_clocks(void *handle, · 10 unmodified lines
11771033 struct pp_hwmgr *hwmgr = handle;
11781034 int ret = 0;
11791035
1180− ret = pp_check(hwmgr);
1181−
1182− if (ret)
1183− return ret;
1036+ if (!hwmgr || !hwmgr->pm_en)
1037+ return -EINVAL;
11841038
11851039 mutex_lock(&hwmgr->smu_lock);
11861040
@@ -1225,10 +1079,8 @@ static int pp_get_clock_by_type(void *handle, enum amd_pp_clock_type type, struc · 38 unmodified lines
12251079 struct pp_hwmgr *hwmgr = handle;
12261080 int ret = 0;
12271081
1228− ret = pp_check(hwmgr);
1229−
1230− if (ret)
1231− return ret;
1082+ if (!hwmgr || !hwmgr->pm_en)
1083+ return -EINVAL;
12321084
12331085 if (clocks == NULL)
12341086 return -EINVAL;
@@ -1246,11 +1098,7 @@ static int pp_get_clock_by_type_with_latency(void *handle, · 11 unmodified lines
12461098 struct pp_hwmgr *hwmgr = handle;
12471099 int ret = 0;
12481100
1249− ret = pp_check(hwmgr);
1250− if (ret)
1251− return ret;
1252−
1253− if (!clocks)
1101+ if (!hwmgr || !hwmgr->pm_en ||!clocks)
12541102 return -EINVAL;
12551103
12561104 mutex_lock(&hwmgr->smu_lock);
@@ -1266,11 +1114,7 @@ static int pp_get_clock_by_type_with_voltage(void *handle, · 9 unmodified lines
12661114 struct pp_hwmgr *hwmgr = handle;
12671115 int ret = 0;
12681116
1269− ret = pp_check(hwmgr);
1270− if (ret)
1271− return ret;
1272−
1273− if (!clocks)
1117+ if (!hwmgr || !hwmgr->pm_en ||!clocks)
12741118 return -EINVAL;
12751119
12761120 mutex_lock(&hwmgr->smu_lock);
@@ -1287,11 +1131,7 @@ static int pp_set_watermarks_for_clocks_ranges(void *handle, · 10 unmodified lines
12871131 struct pp_hwmgr *hwmgr = handle;
12881132 int ret = 0;
12891133
1290− ret = pp_check(hwmgr);
1291− if (ret)
1292− return ret;
1293−
1294− if (!wm_with_clock_ranges)
1134+ if (!hwmgr || !hwmgr->pm_en ||!wm_with_clock_ranges)
12951135 return -EINVAL;
12961136
12971137 mutex_lock(&hwmgr->smu_lock);
@@ -1308,11 +1148,7 @@ static int pp_display_clock_voltage_request(void *handle, · 10 unmodified lines
13081148 struct pp_hwmgr *hwmgr = handle;
13091149 int ret = 0;
13101150
1311− ret = pp_check(hwmgr);
1312− if (ret)
1313− return ret;
1314−
1315− if (!clock)
1151+ if (!hwmgr || !hwmgr->pm_en ||!clock)
13161152 return -EINVAL;
13171153
13181154 mutex_lock(&hwmgr->smu_lock);
@@ -1328,12 +1164,7 @@ static int pp_get_display_mode_validation_clocks(void *handle, · 9 unmodified lines
13281164 struct pp_hwmgr *hwmgr = handle;
13291165 int ret = 0;
13301166
1331− ret = pp_check(hwmgr);
1332−
1333− if (ret)
1334− return ret;
1335−
1336− if (clocks == NULL)
1167+ if (!hwmgr || !hwmgr->pm_en ||!clocks)
13371168 return -EINVAL;
13381169
13391170 mutex_lock(&hwmgr->smu_lock);
@@ -1348,12 +1179,9 @@ static int pp_get_display_mode_validation_clocks(void *handle, · 8 unmodified lines
13481179 static int pp_set_mmhub_powergating_by_smu(void *handle)
13491180 {
13501181 struct pp_hwmgr *hwmgr = handle;
1351− int ret = 0;
13521182
1353− ret = pp_check(hwmgr);
1354−
1355− if (ret)
1356− return ret;
1183+ if (!hwmgr || !hwmgr->pm_en)
1184+ return -EINVAL;
13571185
13581186 if (hwmgr->hwmgr_func->set_mmhub_powergating_by_smu == NULL) {
13591187 pr_info("%s was not implemented.\n", __func__);
@@ -1390,7 +1218,6 @@ static const struct amd_pm_funcs pp_dpm_funcs = { · 30 unmodified lines
13901218 .get_vce_clock_state = pp_dpm_get_vce_clock_state,
13911219 .switch_power_profile = pp_dpm_switch_power_profile,
13921220 .set_clockgating_by_smu = pp_set_clockgating_by_smu,
1393− .notify_smu_memory_info = pp_dpm_notify_smu_memory_info,
13941221 .get_power_profile_mode = pp_get_power_profile_mode,
13951222 .set_power_profile_mode = pp_set_power_profile_mode,
13961223 .odn_edit_dpm_table = pp_odn_edit_dpm_table,
drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c+5−17
@@ -75,8 +75,7 @@ int phm_set_power_state(struct pp_hwmgr *hwmgr, · 74 unmodified lines
7575
7676 int phm_enable_dynamic_state_management(struct pp_hwmgr *hwmgr)
7777 {
78− int ret = 1;
79− bool enabled;
78+ int ret = -EINVAL;;
8079 PHM_FUNC_CHECK(hwmgr);
8180
8281 if (smum_is_dpm_running(hwmgr)) {
@@ -87,17 +86,12 @@ int phm_enable_dynamic_state_management(struct pp_hwmgr *hwmgr) · 4 unmodified lines
8786 if (NULL != hwmgr->hwmgr_func->dynamic_state_management_enable)
8887 ret = hwmgr->hwmgr_func->dynamic_state_management_enable(hwmgr);
8988
90− enabled = ret == 0;
91−
92− cgs_notify_dpm_enabled(hwmgr->device, enabled);
93−
9489 return ret;
9590 }
9691
9792 int phm_disable_dynamic_state_management(struct pp_hwmgr *hwmgr)
9893 {
99− int ret = -1;
100− bool enabled;
94+ int ret = -EINVAL;
10195
10296 PHM_FUNC_CHECK(hwmgr);
10397
@@ -109,10 +103,6 @@ int phm_disable_dynamic_state_management(struct pp_hwmgr *hwmgr) · 5 unmodified lines
109103 if (hwmgr->hwmgr_func->dynamic_state_management_disable)
110104 ret = hwmgr->hwmgr_func->dynamic_state_management_disable(hwmgr);
111105
112− enabled = ret == 0 ? false : true;
113−
114− cgs_notify_dpm_enabled(hwmgr->device, enabled);
115−
116106 return ret;
117107 }
118108
@@ -275,13 +265,11 @@ int phm_store_dal_configuration_data(struct pp_hwmgr *hwmgr, · 156 unmodified lines
275265 if (display_config == NULL)
276266 return -EINVAL;
277267
278− hwmgr->display_config = *display_config;
279−
280268 if (NULL != hwmgr->hwmgr_func->set_deep_sleep_dcefclk)
281− hwmgr->hwmgr_func->set_deep_sleep_dcefclk(hwmgr, hwmgr->display_config.min_dcef_deep_sleep_set_clk);
269+ hwmgr->hwmgr_func->set_deep_sleep_dcefclk(hwmgr, display_config->min_dcef_deep_sleep_set_clk);
282270
283− for (index = 0; index < hwmgr->display_config.num_path_including_non_display; index++) {
284− if (hwmgr->display_config.displays[index].controller_id != 0)
271+ for (index = 0; index < display_config->num_path_including_non_display; index++) {
272+ if (display_config->displays[index].controller_id != 0)
285273 number_of_active_display++;
286274 }
287275
drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c+72−18
@@ -40,6 +40,7 @@ extern const struct pp_smumgr_func iceland_smu_funcs; · 39 unmodified lines
4040 extern const struct pp_smumgr_func tonga_smu_funcs;
4141 extern const struct pp_smumgr_func fiji_smu_funcs;
4242 extern const struct pp_smumgr_func polaris10_smu_funcs;
43+extern const struct pp_smumgr_func vegam_smu_funcs;
4344 extern const struct pp_smumgr_func vega10_smu_funcs;
4445 extern const struct pp_smumgr_func vega12_smu_funcs;
4546 extern const struct pp_smumgr_func smu10_smu_funcs;
@@ -76,7 +77,7 @@ static void hwmgr_init_workload_prority(struct pp_hwmgr *hwmgr) · 30 unmodified lines
7677
7778 int hwmgr_early_init(struct pp_hwmgr *hwmgr)
7879 {
79− if (hwmgr == NULL)
80+ if (!hwmgr)
8081 return -EINVAL;
8182
8283 hwmgr->usec_timeout = AMD_MAX_USEC_TIMEOUT;
@@ -95,7 +96,8 @@ int hwmgr_early_init(struct pp_hwmgr *hwmgr) · 12 unmodified lines
9596 hwmgr->smumgr_funcs = &ci_smu_funcs;
9697 ci_set_asic_special_caps(hwmgr);
9798 hwmgr->feature_mask &= ~(PP_VBI_TIME_SUPPORT_MASK |
98− PP_ENABLE_GFX_CG_THRU_SMU);
99+ PP_ENABLE_GFX_CG_THRU_SMU |
100+ PP_GFXOFF_MASK);
99101 hwmgr->pp_table_version = PP_TABLE_V0;
100102 hwmgr->od_enabled = false;
101103 smu7_init_function_pointers(hwmgr);
@@ -103,9 +105,11 @@ int hwmgr_early_init(struct pp_hwmgr *hwmgr) · 1 unmodified line
103105 case AMDGPU_FAMILY_CZ:
104106 hwmgr->od_enabled = false;
105107 hwmgr->smumgr_funcs = &smu8_smu_funcs;
108+ hwmgr->feature_mask &= ~PP_GFXOFF_MASK;
106109 smu8_init_function_pointers(hwmgr);
107110 break;
108111 case AMDGPU_FAMILY_VI:
112+ hwmgr->feature_mask &= ~PP_GFXOFF_MASK;
109113 switch (hwmgr->chip_id) {
110114 case CHIP_TOPAZ:
111115 hwmgr->smumgr_funcs = &iceland_smu_funcs;
@@ -133,12 +137,18 @@ int hwmgr_early_init(struct pp_hwmgr *hwmgr) · 21 unmodified lines
133137 polaris_set_asic_special_caps(hwmgr);
134138 hwmgr->feature_mask &= ~(PP_UVD_HANDSHAKE_MASK);
135139 break;
140+ case CHIP_VEGAM:
141+ hwmgr->smumgr_funcs = &vegam_smu_funcs;
142+ polaris_set_asic_special_caps(hwmgr);
143+ hwmgr->feature_mask &= ~(PP_UVD_HANDSHAKE_MASK);
144+ break;
136145 default:
137146 return -EINVAL;
138147 }
139148 smu7_init_function_pointers(hwmgr);
140149 break;
141150 case AMDGPU_FAMILY_AI:
151+ hwmgr->feature_mask &= ~PP_GFXOFF_MASK;
142152 switch (hwmgr->chip_id) {
143153 case CHIP_VEGA10:
144154 hwmgr->smumgr_funcs = &vega10_smu_funcs;
@@ -170,22 +180,58 @@ int hwmgr_early_init(struct pp_hwmgr *hwmgr) · 25 unmodified lines
170180 return 0;
171181 }
172182
183+int hwmgr_sw_init(struct pp_hwmgr *hwmgr)
184+{
185+ if (!hwmgr|| !hwmgr->smumgr_funcs || !hwmgr->smumgr_funcs->smu_init)
186+ return -EINVAL;
187+
188+ phm_register_irq_handlers(hwmgr);
189+
190+ return hwmgr->smumgr_funcs->smu_init(hwmgr);
191+}
192+
193+
194+int hwmgr_sw_fini(struct pp_hwmgr *hwmgr)
195+{
196+ if (hwmgr && hwmgr->smumgr_funcs && hwmgr->smumgr_funcs->smu_fini)
197+ hwmgr->smumgr_funcs->smu_fini(hwmgr);
198+
199+ return 0;
200+}
201+
173202 int hwmgr_hw_init(struct pp_hwmgr *hwmgr)
174203 {
175204 int ret = 0;
176205
177− if (hwmgr == NULL)
206+ if (!hwmgr || !hwmgr->smumgr_funcs)
178207 return -EINVAL;
179208
180− if (hwmgr->pptable_func == NULL ||
181− hwmgr->pptable_func->pptable_init == NULL ||
182− hwmgr->hwmgr_func->backend_init == NULL)
183− return -EINVAL;
209+ if (hwmgr->smumgr_funcs->start_smu) {
210+ ret = hwmgr->smumgr_funcs->start_smu(hwmgr);
211+ if (ret) {
212+ pr_err("smc start failed\n");
213+ return -EINVAL;
214+ }
215+ }
216+
217+ if (!hwmgr->pm_en)
218+ return 0;
219+
220+ if (!hwmgr->pptable_func ||
221+ !hwmgr->pptable_func->pptable_init ||
222+ !hwmgr->hwmgr_func->backend_init) {
223+ hwmgr->pm_en = false;
224+ pr_info("dpm not supported \n");
225+ return 0;
226+ }
184227
185228 ret = hwmgr->pptable_func->pptable_init(hwmgr);
186229 if (ret)
187230 goto err;
188231
232+ ((struct amdgpu_device *)hwmgr->adev)->pm.no_fan =
233+ hwmgr->thermal_controller.fanInfo.bNoFan;
234+
189235 ret = hwmgr->hwmgr_func->backend_init(hwmgr);
190236 if (ret)
191237 goto err1;
@@ -206,6 +252,8 @@ int hwmgr_hw_init(struct pp_hwmgr *hwmgr) · 14 unmodified lines
206252 if (ret)
207253 goto err2;
208254
255+ ((struct amdgpu_device *)hwmgr->adev)->pm.dpm_enabled = true;
256+
209257 return 0;
210258 err2:
211259 if (hwmgr->hwmgr_func->backend_fini)
@@ -214,14 +262,13 @@ err1: · 2 unmodified lines
214262 if (hwmgr->pptable_func->pptable_fini)
215263 hwmgr->pptable_func->pptable_fini(hwmgr);
216264 err:
217− pr_err("amdgpu: powerplay initialization failed\n");
218265 return ret;
219266 }
220267
221268 int hwmgr_hw_fini(struct pp_hwmgr *hwmgr)
222269 {
223− if (hwmgr == NULL)
224− return -EINVAL;
270+ if (!hwmgr || !hwmgr->pm_en)
271+ return 0;
225272
226273 phm_stop_thermal_controller(hwmgr);
227274 psm_set_boot_states(hwmgr);
@@ -236,12 +283,12 @@ int hwmgr_hw_fini(struct pp_hwmgr *hwmgr) · 8 unmodified lines
236283 return psm_fini_power_state_table(hwmgr);
237284 }
238285
239−int hwmgr_hw_suspend(struct pp_hwmgr *hwmgr)
286+int hwmgr_suspend(struct pp_hwmgr *hwmgr)
240287 {
241288 int ret = 0;
242289
243− if (hwmgr == NULL)
244− return -EINVAL;
290+ if (!hwmgr || !hwmgr->pm_en)
291+ return 0;
245292
246293 phm_disable_smc_firmware_ctf(hwmgr);
247294 ret = psm_set_boot_states(hwmgr);
@@ -255,13 +302,23 @@ int hwmgr_hw_suspend(struct pp_hwmgr *hwmgr) · 7 unmodified lines
255302 return ret;
256303 }
257304
258−int hwmgr_hw_resume(struct pp_hwmgr *hwmgr)
305+int hwmgr_resume(struct pp_hwmgr *hwmgr)
259306 {
260307 int ret = 0;
261308
262− if (hwmgr == NULL)
309+ if (!hwmgr)
263310 return -EINVAL;
264311
312+ if (hwmgr->smumgr_funcs && hwmgr->smumgr_funcs->start_smu) {
313+ if (hwmgr->smumgr_funcs->start_smu(hwmgr)) {
314+ pr_err("smc start failed\n");
315+ return -EINVAL;
316+ }
317+ }
318+
319+ if (!hwmgr->pm_en)
320+ return 0;
321+
265322 ret = phm_setup_asic(hwmgr);
266323 if (ret)
267324 return ret;
@@ -270,9 +327,6 @@ int hwmgr_hw_resume(struct pp_hwmgr *hwmgr) · 2 unmodified lines
270327 if (ret)
271328 return ret;
272329 ret = phm_start_thermal_controller(hwmgr);
273− if (ret)
274− return ret;
275−
276330 ret |= psm_set_performance_states(hwmgr);
277331 if (ret)
278332 return ret;
drivers/gpu/drm/amd/powerplay/hwmgr/pp_psm.c+1−1
@@ -46,7 +46,7 @@ int psm_init_power_state_table(struct pp_hwmgr *hwmgr) · 45 unmodified lines
4646 sizeof(struct pp_power_state);
4747
4848 if (table_entries == 0 || size == 0) {
49− pr_warn("Please check whether power state management is suppported on this asic\n");
49+ pr_warn("Please check whether power state management is supported on this asic\n");
5050 return 0;
5151 }
5252
drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.c+135−69
@@ -23,7 +23,8 @@ · 22 unmodified lines
2323 #include "pp_debug.h"
2424 #include <linux/module.h>
2525 #include <linux/slab.h>
26−
26+#include <linux/delay.h>
27+#include "atom.h"
2728 #include "ppatomctrl.h"
2829 #include "atombios.h"
2930 #include "cgs_common.h"
@@ -128,7 +129,6 @@ static int atomctrl_set_mc_reg_address_table( · 98 unmodified lines
128129 return 0;
129130 }
130131
131−
132132 int atomctrl_initialize_mc_reg_table(
133133 struct pp_hwmgr *hwmgr,
134134 uint8_t module_index,
@@ -141,7 +141,7 @@ int atomctrl_initialize_mc_reg_table( · 6 unmodified lines
141141 u16 size;
142142
143143 vram_info = (ATOM_VRAM_INFO_HEADER_V2_1 *)
144− cgs_atom_get_data_table(hwmgr->device,
144+ smu_atom_get_data_table(hwmgr->adev,
145145 GetIndexIntoMasterTable(DATA, VRAM_Info), &size, &frev, &crev);
146146
147147 if (module_index >= vram_info->ucNumOfVRAMModule) {
@@ -174,6 +174,8 @@ int atomctrl_set_engine_dram_timings_rv770( · 26 unmodified lines
174174 uint32_t engine_clock,
175175 uint32_t memory_clock)
176176 {
177+ struct amdgpu_device *adev = hwmgr->adev;
178+
177179 SET_ENGINE_CLOCK_PS_ALLOCATION engine_clock_parameters;
178180
179181 /* They are both in 10KHz Units. */
@@ -184,9 +186,10 @@ int atomctrl_set_engine_dram_timings_rv770( · 4 unmodified lines
184186 /* in 10 khz units.*/
185187 engine_clock_parameters.sReserved.ulClock =
186188 cpu_to_le32(memory_clock & SET_CLOCK_FREQ_MASK);
187− return cgs_atom_exec_cmd_table(hwmgr->device,
189+
190+ return amdgpu_atom_execute_table(adev->mode_info.atom_context,
188191 GetIndexIntoMasterTable(COMMAND, DynamicMemorySettings),
189− &engine_clock_parameters);
192+ (uint32_t *)&engine_clock_parameters);
190193 }
191194
192195 /**
@@ -203,7 +206,7 @@ static ATOM_VOLTAGE_OBJECT_INFO *get_voltage_info_table(void *device) · 10 unmodified lines
203206 union voltage_object_info *voltage_info;
204207
205208 voltage_info = (union voltage_object_info *)
206− cgs_atom_get_data_table(device, index,
209+ smu_atom_get_data_table(device, index,
207210 &size, &frev, &crev);
208211
209212 if (voltage_info != NULL)
@@ -247,16 +250,16 @@ int atomctrl_get_memory_pll_dividers_si( · 37 unmodified lines
247250 pp_atomctrl_memory_clock_param *mpll_param,
248251 bool strobe_mode)
249252 {
253+ struct amdgpu_device *adev = hwmgr->adev;
250254 COMPUTE_MEMORY_CLOCK_PARAM_PARAMETERS_V2_1 mpll_parameters;
251255 int result;
252256
253257 mpll_parameters.ulClock = cpu_to_le32(clock_value);
254258 mpll_parameters.ucInputFlag = (uint8_t)((strobe_mode) ? 1 : 0);
255259
256− result = cgs_atom_exec_cmd_table
257− (hwmgr->device,
260+ result = amdgpu_atom_execute_table(adev->mode_info.atom_context,
258261 GetIndexIntoMasterTable(COMMAND, ComputeMemoryClockParam),
259− &mpll_parameters);
262+ (uint32_t *)&mpll_parameters);
260263
261264 if (0 == result) {
262265 mpll_param->mpll_fb_divider.clk_frac =
@@ -295,14 +298,15 @@ int atomctrl_get_memory_pll_dividers_si( · 32 unmodified lines
295298 int atomctrl_get_memory_pll_dividers_vi(struct pp_hwmgr *hwmgr,
296299 uint32_t clock_value, pp_atomctrl_memory_clock_param *mpll_param)
297300 {
301+ struct amdgpu_device *adev = hwmgr->adev;
298302 COMPUTE_MEMORY_CLOCK_PARAM_PARAMETERS_V2_2 mpll_parameters;
299303 int result;
300304
301305 mpll_parameters.ulClock.ulClock = cpu_to_le32(clock_value);
302306
303− result = cgs_atom_exec_cmd_table(hwmgr->device,
307+ result = amdgpu_atom_execute_table(adev->mode_info.atom_context,
304308 GetIndexIntoMasterTable(COMMAND, ComputeMemoryClockParam),
305− &mpll_parameters);
309+ (uint32_t *)&mpll_parameters);
306310
307311 if (!result)
308312 mpll_param->mpll_post_divider =
@@ -311,19 +315,49 @@ int atomctrl_get_memory_pll_dividers_vi(struct pp_hwmgr *hwmgr, · 2 unmodified lines
311315 return result;
312316 }
313317
318+int atomctrl_get_memory_pll_dividers_ai(struct pp_hwmgr *hwmgr,
319+ uint32_t clock_value,
320+ pp_atomctrl_memory_clock_param_ai *mpll_param)
321+{
322+ struct amdgpu_device *adev = hwmgr->adev;
323+ COMPUTE_MEMORY_CLOCK_PARAM_PARAMETERS_V2_3 mpll_parameters = {0};
324+ int result;
325+
326+ mpll_parameters.ulClock.ulClock = cpu_to_le32(clock_value);
327+
328+ result = amdgpu_atom_execute_table(adev->mode_info.atom_context,
329+ GetIndexIntoMasterTable(COMMAND, ComputeMemoryClockParam),
330+ (uint32_t *)&mpll_parameters);
331+
332+ /* VEGAM's mpll takes sometime to finish computing */
333+ udelay(10);
334+
335+ if (!result) {
336+ mpll_param->ulMclk_fcw_int =
337+ le16_to_cpu(mpll_parameters.usMclk_fcw_int);
338+ mpll_param->ulMclk_fcw_frac =
339+ le16_to_cpu(mpll_parameters.usMclk_fcw_frac);
340+ mpll_param->ulClock =
341+ le32_to_cpu(mpll_parameters.ulClock.ulClock);
342+ mpll_param->ulPostDiv = mpll_parameters.ulClock.ucPostDiv;
343+ }
344+
345+ return result;
346+}
347+
314348 int atomctrl_get_engine_pll_dividers_kong(struct pp_hwmgr *hwmgr,
315349 uint32_t clock_value,
316350 pp_atomctrl_clock_dividers_kong *dividers)
317351 {
352+ struct amdgpu_device *adev = hwmgr->adev;
318353 COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V4 pll_parameters;
319354 int result;
320355
321356 pll_parameters.ulClock = cpu_to_le32(clock_value);
322357
323− result = cgs_atom_exec_cmd_table
324− (hwmgr->device,
358+ result = amdgpu_atom_execute_table(adev->mode_info.atom_context,
325359 GetIndexIntoMasterTable(COMMAND, ComputeMemoryEnginePLL),
326− &pll_parameters);
360+ (uint32_t *)&pll_parameters);
327361
328362 if (0 == result) {
329363 dividers->pll_post_divider = pll_parameters.ucPostDiv;
@@ -338,16 +372,16 @@ int atomctrl_get_engine_pll_dividers_vi( · 8 unmodified lines
338372 uint32_t clock_value,
339373 pp_atomctrl_clock_dividers_vi *dividers)
340374 {
375+ struct amdgpu_device *adev = hwmgr->adev;
341376 COMPUTE_GPU_CLOCK_OUTPUT_PARAMETERS_V1_6 pll_patameters;
342377 int result;
343378
344379 pll_patameters.ulClock.ulClock = cpu_to_le32(clock_value);
345380 pll_patameters.ulClock.ucPostDiv = COMPUTE_GPUCLK_INPUT_FLAG_SCLK;
346381
347− result = cgs_atom_exec_cmd_table
348− (hwmgr->device,
382+ result = amdgpu_atom_execute_table(adev->mode_info.atom_context,
349383 GetIndexIntoMasterTable(COMMAND, ComputeMemoryEnginePLL),
350− &pll_patameters);
384+ (uint32_t *)&pll_patameters);
351385
352386 if (0 == result) {
353387 dividers->pll_post_divider =
@@ -375,16 +409,16 @@ int atomctrl_get_engine_pll_dividers_ai(struct pp_hwmgr *hwmgr, · 21 unmodified lines
375409 uint32_t clock_value,
376410 pp_atomctrl_clock_dividers_ai *dividers)
377411 {
412+ struct amdgpu_device *adev = hwmgr->adev;
378413 COMPUTE_GPU_CLOCK_OUTPUT_PARAMETERS_V1_7 pll_patameters;
379414 int result;
380415
381416 pll_patameters.ulClock.ulClock = cpu_to_le32(clock_value);
382417 pll_patameters.ulClock.ucPostDiv = COMPUTE_GPUCLK_INPUT_FLAG_SCLK;
383418
384− result = cgs_atom_exec_cmd_table
385− (hwmgr->device,
419+ result = amdgpu_atom_execute_table(adev->mode_info.atom_context,
386420 GetIndexIntoMasterTable(COMMAND, ComputeMemoryEnginePLL),
387− &pll_patameters);
421+ (uint32_t *)&pll_patameters);
388422
389423 if (0 == result) {
390424 dividers->usSclk_fcw_frac = le16_to_cpu(pll_patameters.usSclk_fcw_frac);
@@ -407,6 +441,7 @@ int atomctrl_get_dfs_pll_dividers_vi( · 16 unmodified lines
407441 uint32_t clock_value,
408442 pp_atomctrl_clock_dividers_vi *dividers)
409443 {
444+ struct amdgpu_device *adev = hwmgr->adev;
410445 COMPUTE_GPU_CLOCK_OUTPUT_PARAMETERS_V1_6 pll_patameters;
411446 int result;
412447
@@ -414,10 +449,9 @@ int atomctrl_get_dfs_pll_dividers_vi( · 1 unmodified line
414449 pll_patameters.ulClock.ucPostDiv =
415450 COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK;
416451
417− result = cgs_atom_exec_cmd_table
418− (hwmgr->device,
452+ result = amdgpu_atom_execute_table(adev->mode_info.atom_context,
419453 GetIndexIntoMasterTable(COMMAND, ComputeMemoryEnginePLL),
420− &pll_patameters);
454+ (uint32_t *)&pll_patameters);
421455
422456 if (0 == result) {
423457 dividers->pll_post_divider =
@@ -452,7 +486,7 @@ uint32_t atomctrl_get_reference_clock(struct pp_hwmgr *hwmgr) · 28 unmodified lines
452486 uint32_t clock;
453487
454488 fw_info = (ATOM_FIRMWARE_INFO *)
455− cgs_atom_get_data_table(hwmgr->device,
489+ smu_atom_get_data_table(hwmgr->adev,
456490 GetIndexIntoMasterTable(DATA, FirmwareInfo),
457491 &size, &frev, &crev);
458492
@@ -476,7 +510,7 @@ bool atomctrl_is_voltage_controlled_by_gpio_v3( · 17 unmodified lines
476510 uint8_t voltage_mode)
477511 {
478512 ATOM_VOLTAGE_OBJECT_INFO_V3_1 *voltage_info =
479− (ATOM_VOLTAGE_OBJECT_INFO_V3_1 *)get_voltage_info_table(hwmgr->device);
513+ (ATOM_VOLTAGE_OBJECT_INFO_V3_1 *)get_voltage_info_table(hwmgr->adev);
480514 bool ret;
481515
482516 PP_ASSERT_WITH_CODE((NULL != voltage_info),
@@ -495,7 +529,7 @@ int atomctrl_get_voltage_table_v3( · 12 unmodified lines
495529 pp_atomctrl_voltage_table *voltage_table)
496530 {
497531 ATOM_VOLTAGE_OBJECT_INFO_V3_1 *voltage_info =
498− (ATOM_VOLTAGE_OBJECT_INFO_V3_1 *)get_voltage_info_table(hwmgr->device);
532+ (ATOM_VOLTAGE_OBJECT_INFO_V3_1 *)get_voltage_info_table(hwmgr->adev);
499533 const ATOM_VOLTAGE_OBJECT_V3 *voltage_object;
500534 unsigned int i;
501535
@@ -572,7 +606,7 @@ static ATOM_GPIO_PIN_LUT *get_gpio_lookup_table(void *device) · 70 unmodified lines
572606 void *table_address;
573607
574608 table_address = (ATOM_GPIO_PIN_LUT *)
575− cgs_atom_get_data_table(device,
609+ smu_atom_get_data_table(device,
576610 GetIndexIntoMasterTable(DATA, GPIO_Pin_LUT),
577611 &size, &frev, &crev);
578612
@@ -592,7 +626,7 @@ bool atomctrl_get_pp_assign_pin( · 13 unmodified lines
592626 {
593627 bool bRet = false;
594628 ATOM_GPIO_PIN_LUT *gpio_lookup_table =
595− get_gpio_lookup_table(hwmgr->device);
629+ get_gpio_lookup_table(hwmgr->adev);
596630
597631 PP_ASSERT_WITH_CODE((NULL != gpio_lookup_table),
598632 "Could not find GPIO lookup Table in BIOS.", return false);
@@ -613,7 +647,7 @@ int atomctrl_calculate_voltage_evv_on_sclk( · 14 unmodified lines
613647 bool debug)
614648 {
615649 ATOM_ASIC_PROFILING_INFO_V3_4 *getASICProfilingInfo;
616−
650+ struct amdgpu_device *adev = hwmgr->adev;
617651 EFUSE_LINEAR_FUNC_PARAM sRO_fuse;
618652 EFUSE_LINEAR_FUNC_PARAM sCACm_fuse;
619653 EFUSE_LINEAR_FUNC_PARAM sCACb_fuse;
@@ -640,7 +674,7 @@ int atomctrl_calculate_voltage_evv_on_sclk( · 20 unmodified lines
640674 int result;
641675
642676 getASICProfilingInfo = (ATOM_ASIC_PROFILING_INFO_V3_4 *)
643− cgs_atom_get_data_table(hwmgr->device,
677+ smu_atom_get_data_table(hwmgr->adev,
644678 GetIndexIntoMasterTable(DATA, ASIC_ProfilingInfo),
645679 NULL, NULL, NULL);
646680
@@ -706,9 +740,9 @@ int atomctrl_calculate_voltage_evv_on_sclk( · 59 unmodified lines
706740
707741 sOutput_FuseValues.sEfuse = sInput_FuseValues;
708742
709− result = cgs_atom_exec_cmd_table(hwmgr->device,
743+ result = amdgpu_atom_execute_table(adev->mode_info.atom_context,
710744 GetIndexIntoMasterTable(COMMAND, ReadEfuseValue),
711− &sOutput_FuseValues);
745+ (uint32_t *)&sOutput_FuseValues);
712746
713747 if (result)
714748 return result;
@@ -727,9 +761,9 @@ int atomctrl_calculate_voltage_evv_on_sclk( · 12 unmodified lines
727761
728762 sOutput_FuseValues.sEfuse = sInput_FuseValues;
729763
730− result = cgs_atom_exec_cmd_table(hwmgr->device,
764+ result = amdgpu_atom_execute_table(adev->mode_info.atom_context,
731765 GetIndexIntoMasterTable(COMMAND, ReadEfuseValue),
732− &sOutput_FuseValues);
766+ (uint32_t *)&sOutput_FuseValues);
733767
734768 if (result)
735769 return result;
@@ -747,9 +781,9 @@ int atomctrl_calculate_voltage_evv_on_sclk( · 11 unmodified lines
747781 sInput_FuseValues.ucBitLength = sCACb_fuse.ucEfuseLength;
748782 sOutput_FuseValues.sEfuse = sInput_FuseValues;
749783
750− result = cgs_atom_exec_cmd_table(hwmgr->device,
784+ result = amdgpu_atom_execute_table(adev->mode_info.atom_context,
751785 GetIndexIntoMasterTable(COMMAND, ReadEfuseValue),
752− &sOutput_FuseValues);
786+ (uint32_t *)&sOutput_FuseValues);
753787
754788 if (result)
755789 return result;
@@ -768,9 +802,9 @@ int atomctrl_calculate_voltage_evv_on_sclk( · 12 unmodified lines
768802
769803 sOutput_FuseValues.sEfuse = sInput_FuseValues;
770804
771− result = cgs_atom_exec_cmd_table(hwmgr->device,
805+ result = amdgpu_atom_execute_table(adev->mode_info.atom_context,
772806 GetIndexIntoMasterTable(COMMAND, ReadEfuseValue),
773− &sOutput_FuseValues);
807+ (uint32_t *)&sOutput_FuseValues);
774808
775809 if (result)
776810 return result;
@@ -790,9 +824,9 @@ int atomctrl_calculate_voltage_evv_on_sclk( · 13 unmodified lines
790824
791825 sOutput_FuseValues.sEfuse = sInput_FuseValues;
792826
793− result = cgs_atom_exec_cmd_table(hwmgr->device,
827+ result = amdgpu_atom_execute_table(adev->mode_info.atom_context,
794828 GetIndexIntoMasterTable(COMMAND, ReadEfuseValue),
795− &sOutput_FuseValues);
829+ (uint32_t *)&sOutput_FuseValues);
796830 if (result)
797831 return result;
798832
@@ -811,9 +845,9 @@ int atomctrl_calculate_voltage_evv_on_sclk( · 12 unmodified lines
811845 sInput_FuseValues.ucBitLength = sKv_b_fuse.ucEfuseLength;
812846 sOutput_FuseValues.sEfuse = sInput_FuseValues;
813847
814− result = cgs_atom_exec_cmd_table(hwmgr->device,
848+ result = amdgpu_atom_execute_table(adev->mode_info.atom_context,
815849 GetIndexIntoMasterTable(COMMAND, ReadEfuseValue),
816− &sOutput_FuseValues);
850+ (uint32_t *)&sOutput_FuseValues);
817851
818852 if (result)
819853 return result;
@@ -842,9 +876,9 @@ int atomctrl_calculate_voltage_evv_on_sclk( · 22 unmodified lines
842876
843877 sOutput_FuseValues.sEfuse = sInput_FuseValues;
844878
845− result = cgs_atom_exec_cmd_table(hwmgr->device,
879+ result = amdgpu_atom_execute_table(adev->mode_info.atom_context,
846880 GetIndexIntoMasterTable(COMMAND, ReadEfuseValue),
847− &sOutput_FuseValues);
881+ (uint32_t *)&sOutput_FuseValues);
848882
849883 if (result)
850884 return result;
@@ -1053,8 +1087,9 @@ int atomctrl_get_voltage_evv_on_sclk( · 202 unmodified lines
10531087 uint32_t sclk, uint16_t virtual_voltage_Id,
10541088 uint16_t *voltage)
10551089 {
1056− int result;
1090+ struct amdgpu_device *adev = hwmgr->adev;
10571091 GET_VOLTAGE_INFO_INPUT_PARAMETER_V1_2 get_voltage_info_param_space;
1092+ int result;
10581093
10591094 get_voltage_info_param_space.ucVoltageType =
10601095 voltage_type;
@@ -1065,9 +1100,9 @@ int atomctrl_get_voltage_evv_on_sclk( · 4 unmodified lines
10651100 get_voltage_info_param_space.ulSCLKFreq =
10661101 cpu_to_le32(sclk);
10671102
1068− result = cgs_atom_exec_cmd_table(hwmgr->device,
1103+ result = amdgpu_atom_execute_table(adev->mode_info.atom_context,
10691104 GetIndexIntoMasterTable(COMMAND, GetVoltageInfo),
1070− &get_voltage_info_param_space);
1105+ (uint32_t *)&get_voltage_info_param_space);
10711106
10721107 if (0 != result)
10731108 return result;
@@ -1088,9 +1123,10 @@ int atomctrl_get_voltage_evv(struct pp_hwmgr *hwmgr, · 14 unmodified lines
10881123 uint16_t virtual_voltage_id,
10891124 uint16_t *voltage)
10901125 {
1126+ struct amdgpu_device *adev = hwmgr->adev;
1127+ GET_VOLTAGE_INFO_INPUT_PARAMETER_V1_2 get_voltage_info_param_space;
10911128 int result;
10921129 int entry_id;
1093− GET_VOLTAGE_INFO_INPUT_PARAMETER_V1_2 get_voltage_info_param_space;
10941130
10951131 /* search for leakage voltage ID 0xff01 ~ 0xff08 and sckl */
10961132 for (entry_id = 0; entry_id < hwmgr->dyn_state.vddc_dependency_on_sclk->count; entry_id++) {
@@ -1111,9 +1147,9 @@ int atomctrl_get_voltage_evv(struct pp_hwmgr *hwmgr, · 14 unmodified lines
11111147 get_voltage_info_param_space.ulSCLKFreq =
11121148 cpu_to_le32(hwmgr->dyn_state.vddc_dependency_on_sclk->entries[entry_id].clk);
11131149
1114− result = cgs_atom_exec_cmd_table(hwmgr->device,
1150+ result = amdgpu_atom_execute_table(adev->mode_info.atom_context,
11151151 GetIndexIntoMasterTable(COMMAND, GetVoltageInfo),
1116− &get_voltage_info_param_space);
1152+ (uint32_t *)&get_voltage_info_param_space);
11171153
11181154 if (0 != result)
11191155 return result;
@@ -1135,7 +1171,7 @@ uint32_t atomctrl_get_mpll_reference_clock(struct pp_hwmgr *hwmgr) · 15 unmodified lines
11351171 u16 size;
11361172
11371173 fw_info = (ATOM_COMMON_TABLE_HEADER *)
1138− cgs_atom_get_data_table(hwmgr->device,
1174+ smu_atom_get_data_table(hwmgr->adev,
11391175 GetIndexIntoMasterTable(DATA, FirmwareInfo),
11401176 &size, &frev, &crev);
11411177
@@ -1167,7 +1203,7 @@ static ATOM_ASIC_INTERNAL_SS_INFO *asic_internal_ss_get_ss_table(void *device) · 25 unmodified lines
11671203 u16 size;
11681204
11691205 table = (ATOM_ASIC_INTERNAL_SS_INFO *)
1170− cgs_atom_get_data_table(device,
1206+ smu_atom_get_data_table(device,
11711207 GetIndexIntoMasterTable(DATA, ASIC_InternalSS_Info),
11721208 &size, &frev, &crev);
11731209
@@ -1188,7 +1224,7 @@ static int asic_internal_ss_get_ss_asignment(struct pp_hwmgr *hwmgr, · 14 unmodified lines
11881224
11891225 memset(ssEntry, 0x00, sizeof(pp_atomctrl_internal_ss_info));
11901226
1191− table = asic_internal_ss_get_ss_table(hwmgr->device);
1227+ table = asic_internal_ss_get_ss_table(hwmgr->adev);
11921228
11931229 if (NULL == table)
11941230 return -1;
@@ -1260,9 +1296,10 @@ int atomctrl_get_engine_clock_spread_spectrum( · 65 unmodified lines
12601296 ASIC_INTERNAL_ENGINE_SS, engine_clock, ssInfo);
12611297 }
12621298
1263−int atomctrl_read_efuse(void *device, uint16_t start_index,
1299+int atomctrl_read_efuse(struct pp_hwmgr *hwmgr, uint16_t start_index,
12641300 uint16_t end_index, uint32_t mask, uint32_t *efuse)
12651301 {
1302+ struct amdgpu_device *adev = hwmgr->adev;
12661303 int result;
12671304 READ_EFUSE_VALUE_PARAMETER efuse_param;
12681305
@@ -1272,9 +1309,9 @@ int atomctrl_read_efuse(void *device, uint16_t start_index, · 3 unmodified lines
12721309 efuse_param.sEfuse.ucBitLength = (uint8_t)
12731310 ((end_index - start_index) + 1);
12741311
1275− result = cgs_atom_exec_cmd_table(device,
1312+ result = amdgpu_atom_execute_table(adev->mode_info.atom_context,
12761313 GetIndexIntoMasterTable(COMMAND, ReadEfuseValue),
1277− &efuse_param);
1314+ (uint32_t *)&efuse_param);
12781315 if (!result)
12791316 *efuse = le32_to_cpu(efuse_param.ulEfuseValue) & mask;
12801317
@@ -1284,6 +1321,7 @@ int atomctrl_read_efuse(void *device, uint16_t start_index, · 3 unmodified lines
12841321 int atomctrl_set_ac_timing_ai(struct pp_hwmgr *hwmgr, uint32_t memory_clock,
12851322 uint8_t level)
12861323 {
1324+ struct amdgpu_device *adev = hwmgr->adev;
12871325 DYNAMICE_MEMORY_SETTINGS_PARAMETER_V2_1 memory_clock_parameters;
12881326 int result;
12891327
@@ -1293,10 +1331,9 @@ int atomctrl_set_ac_timing_ai(struct pp_hwmgr *hwmgr, uint32_t memory_clock, · 3 unmodified lines
12931331 ADJUST_MC_SETTING_PARAM;
12941332 memory_clock_parameters.asDPMMCReg.ucMclkDPMState = level;
12951333
1296− result = cgs_atom_exec_cmd_table
1297− (hwmgr->device,
1334+ result = amdgpu_atom_execute_table(adev->mode_info.atom_context,
12981335 GetIndexIntoMasterTable(COMMAND, DynamicMemorySettings),
1299− &memory_clock_parameters);
1336+ (uint32_t *)&memory_clock_parameters);
13001337
13011338 return result;
13021339 }
@@ -1304,7 +1341,7 @@ int atomctrl_set_ac_timing_ai(struct pp_hwmgr *hwmgr, uint32_t memory_clock, · 1 unmodified line
13041341 int atomctrl_get_voltage_evv_on_sclk_ai(struct pp_hwmgr *hwmgr, uint8_t voltage_type,
13051342 uint32_t sclk, uint16_t virtual_voltage_Id, uint32_t *voltage)
13061343 {
1307−
1344+ struct amdgpu_device *adev = hwmgr->adev;
13081345 int result;
13091346 GET_VOLTAGE_INFO_INPUT_PARAMETER_V1_3 get_voltage_info_param_space;
13101347
@@ -1313,9 +1350,9 @@ int atomctrl_get_voltage_evv_on_sclk_ai(struct pp_hwmgr *hwmgr, uint8_t voltage_ · 2 unmodified lines
13131350 get_voltage_info_param_space.usVoltageLevel = cpu_to_le16(virtual_voltage_Id);
13141351 get_voltage_info_param_space.ulSCLKFreq = cpu_to_le32(sclk);
13151352
1316− result = cgs_atom_exec_cmd_table(hwmgr->device,
1353+ result = amdgpu_atom_execute_table(adev->mode_info.atom_context,
13171354 GetIndexIntoMasterTable(COMMAND, GetVoltageInfo),
1318− &get_voltage_info_param_space);
1355+ (uint32_t *)&get_voltage_info_param_space);
13191356
13201357 if (0 != result)
13211358 return result;
@@ -1334,7 +1371,7 @@ int atomctrl_get_smc_sclk_range_table(struct pp_hwmgr *hwmgr, struct pp_atom_ctr · 12 unmodified lines
13341371 u16 size;
13351372
13361373 ATOM_SMU_INFO_V2_1 *psmu_info =
1337− (ATOM_SMU_INFO_V2_1 *)cgs_atom_get_data_table(hwmgr->device,
1374+ (ATOM_SMU_INFO_V2_1 *)smu_atom_get_data_table(hwmgr->adev,
13381375 GetIndexIntoMasterTable(DATA, SMU_Info),
13391376 &size, &frev, &crev);
13401377
@@ -1362,7 +1399,7 @@ int atomctrl_get_avfs_information(struct pp_hwmgr *hwmgr, · 21 unmodified lines
13621399 return -EINVAL;
13631400
13641401 profile = (ATOM_ASIC_PROFILING_INFO_V3_6 *)
1365− cgs_atom_get_data_table(hwmgr->device,
1402+ smu_atom_get_data_table(hwmgr->adev,
13661403 GetIndexIntoMasterTable(DATA, ASIC_ProfilingInfo),
13671404 NULL, NULL, NULL);
13681405 if (!profile)
@@ -1402,7 +1439,7 @@ int atomctrl_get_svi2_info(struct pp_hwmgr *hwmgr, uint8_t voltage_type, · 33 unmodified lines
14021439 uint16_t *load_line)
14031440 {
14041441 ATOM_VOLTAGE_OBJECT_INFO_V3_1 *voltage_info =
1405− (ATOM_VOLTAGE_OBJECT_INFO_V3_1 *)get_voltage_info_table(hwmgr->device);
1442+ (ATOM_VOLTAGE_OBJECT_INFO_V3_1 *)get_voltage_info_table(hwmgr->adev);
14061443
14071444 const ATOM_VOLTAGE_OBJECT_V3 *voltage_object;
14081445
@@ -1421,16 +1458,17 @@ int atomctrl_get_svi2_info(struct pp_hwmgr *hwmgr, uint8_t voltage_type, · 12 unmodified lines
14211458
14221459 int atomctrl_get_leakage_id_from_efuse(struct pp_hwmgr *hwmgr, uint16_t *virtual_voltage_id)
14231460 {
1424− int result;
1461+ struct amdgpu_device *adev = hwmgr->adev;
14251462 SET_VOLTAGE_PS_ALLOCATION allocation;
14261463 SET_VOLTAGE_PARAMETERS_V1_3 *voltage_parameters =
14271464 (SET_VOLTAGE_PARAMETERS_V1_3 *)&allocation.sASICSetVoltage;
1465+ int result;
14281466
14291467 voltage_parameters->ucVoltageMode = ATOM_GET_LEAKAGE_ID;
14301468
1431− result = cgs_atom_exec_cmd_table(hwmgr->device,
1469+ result = amdgpu_atom_execute_table(adev->mode_info.atom_context,
14321470 GetIndexIntoMasterTable(COMMAND, SetVoltage),
1433− voltage_parameters);
1471+ (uint32_t *)voltage_parameters);
14341472
14351473 *virtual_voltage_id = voltage_parameters->usVoltageLevel;
14361474
@@ -1453,7 +1491,7 @@ int atomctrl_get_leakage_vddc_base_on_leakage(struct pp_hwmgr *hwmgr, · 16 unmodified lines
14531491 ix = GetIndexIntoMasterTable(DATA, ASIC_ProfilingInfo);
14541492
14551493 profile = (ATOM_ASIC_PROFILING_INFO_V2_1 *)
1456− cgs_atom_get_data_table(hwmgr->device,
1494+ smu_atom_get_data_table(hwmgr->adev,
14571495 ix,
14581496 NULL, NULL, NULL);
14591497 if (!profile)
@@ -1498,3 +1536,31 @@ int atomctrl_get_leakage_vddc_base_on_leakage(struct pp_hwmgr *hwmgr, · 38 unmodified lines
14981536
14991537 return 0;
15001538 }
1539+
1540+void atomctrl_get_voltage_range(struct pp_hwmgr *hwmgr, uint32_t *max_vddc,
1541+ uint32_t *min_vddc)
1542+{
1543+ void *profile;
1544+
1545+ profile = smu_atom_get_data_table(hwmgr->adev,
1546+ GetIndexIntoMasterTable(DATA, ASIC_ProfilingInfo),
1547+ NULL, NULL, NULL);
1548+
1549+ if (profile) {
1550+ switch (hwmgr->chip_id) {
1551+ case CHIP_TONGA:
1552+ case CHIP_FIJI:
1553+ *max_vddc = le32_to_cpu(((ATOM_ASIC_PROFILING_INFO_V3_3 *)profile)->ulMaxVddc/4);
1554+ *min_vddc = le32_to_cpu(((ATOM_ASIC_PROFILING_INFO_V3_3 *)profile)->ulMinVddc/4);
1555+ break;
1556+ case CHIP_POLARIS11:
1557+ case CHIP_POLARIS10:
1558+ case CHIP_POLARIS12:
1559+ *max_vddc = le32_to_cpu(((ATOM_ASIC_PROFILING_INFO_V3_6 *)profile)->ulMaxVddc/100);
1560+ *min_vddc = le32_to_cpu(((ATOM_ASIC_PROFILING_INFO_V3_6 *)profile)->ulMinVddc/100);
1561+ break;
1562+ default:
1563+ return;
1564+ }
1565+ }
1566+}
drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.h+14−1
@@ -146,6 +146,14 @@ struct pp_atomctrl_memory_clock_param { · 145 unmodified lines
146146 };
147147 typedef struct pp_atomctrl_memory_clock_param pp_atomctrl_memory_clock_param;
148148
149+struct pp_atomctrl_memory_clock_param_ai {
150+ uint32_t ulClock;
151+ uint32_t ulPostDiv;
152+ uint16_t ulMclk_fcw_frac;
153+ uint16_t ulMclk_fcw_int;
154+};
155+typedef struct pp_atomctrl_memory_clock_param_ai pp_atomctrl_memory_clock_param_ai;
156+
149157 struct pp_atomctrl_internal_ss_info {
150158 uint32_t speed_spectrum_percentage; /* in 1/100 percentage */
151159 uint32_t speed_spectrum_rate; /* in KHz */
@@ -295,10 +303,12 @@ extern bool atomctrl_is_voltage_controlled_by_gpio_v3(struct pp_hwmgr *hwmgr, ui · 143 unmodified lines
295303 extern int atomctrl_get_voltage_table_v3(struct pp_hwmgr *hwmgr, uint8_t voltage_type, uint8_t voltage_mode, pp_atomctrl_voltage_table *voltage_table);
296304 extern int atomctrl_get_memory_pll_dividers_vi(struct pp_hwmgr *hwmgr,
297305 uint32_t clock_value, pp_atomctrl_memory_clock_param *mpll_param);
306+extern int atomctrl_get_memory_pll_dividers_ai(struct pp_hwmgr *hwmgr,
307+ uint32_t clock_value, pp_atomctrl_memory_clock_param_ai *mpll_param);
298308 extern int atomctrl_get_engine_pll_dividers_kong(struct pp_hwmgr *hwmgr,
299309 uint32_t clock_value,
300310 pp_atomctrl_clock_dividers_kong *dividers);
301−extern int atomctrl_read_efuse(void *device, uint16_t start_index,
311+extern int atomctrl_read_efuse(struct pp_hwmgr *hwmgr, uint16_t start_index,
302312 uint16_t end_index, uint32_t mask, uint32_t *efuse);
303313 extern int atomctrl_calculate_voltage_evv_on_sclk(struct pp_hwmgr *hwmgr, uint8_t voltage_type,
304314 uint32_t sclk, uint16_t virtual_voltage_Id, uint16_t *voltage, uint16_t dpm_level, bool debug);
@@ -320,5 +330,8 @@ extern int atomctrl_get_leakage_vddc_base_on_leakage(struct pp_hwmgr *hwmgr, · 15 unmodified lines
320330 uint16_t virtual_voltage_id,
321331 uint16_t efuse_voltage_id);
322332 extern int atomctrl_get_leakage_id_from_efuse(struct pp_hwmgr *hwmgr, uint16_t *virtual_voltage_id);
333+
334+extern void atomctrl_get_voltage_range(struct pp_hwmgr *hwmgr, uint32_t *max_vddc,
335+ uint32_t *min_vddc);
323336 #endif
324337
drivers/gpu/drm/amd/powerplay/hwmgr/ppatomfwctrl.c+47−52
@@ -23,9 +23,9 @@ · 22 unmodified lines
2323
2424 #include "ppatomfwctrl.h"
2525 #include "atomfirmware.h"
26+#include "atom.h"
2627 #include "pp_debug.h"
2728
28−
2929 static const union atom_voltage_object_v4 *pp_atomfwctrl_lookup_voltage_type_v4(
3030 const struct atom_voltage_objects_info_v4_1 *voltage_object_info_table,
3131 uint8_t voltage_type, uint8_t voltage_mode)
@@ -38,35 +38,34 @@ static const union atom_voltage_object_v4 *pp_atomfwctrl_lookup_voltage_type_v4( · 6 unmodified lines
3838
3939 while (offset < size) {
4040 const union atom_voltage_object_v4 *voltage_object =
41− (const union atom_voltage_object_v4 *)(start + offset);
41+ (const union atom_voltage_object_v4 *)(start + offset);
4242
43− if (voltage_type == voltage_object->gpio_voltage_obj.header.voltage_type &&
44− voltage_mode == voltage_object->gpio_voltage_obj.header.voltage_mode)
45− return voltage_object;
43+ if (voltage_type == voltage_object->gpio_voltage_obj.header.voltage_type &&
44+ voltage_mode == voltage_object->gpio_voltage_obj.header.voltage_mode)
45+ return voltage_object;
4646
47− offset += le16_to_cpu(voltage_object->gpio_voltage_obj.header.object_size);
47+ offset += le16_to_cpu(voltage_object->gpio_voltage_obj.header.object_size);
4848
49− }
49+ }
5050
51− return NULL;
51+ return NULL;
5252 }
5353
5454 static struct atom_voltage_objects_info_v4_1 *pp_atomfwctrl_get_voltage_info_table(
5555 struct pp_hwmgr *hwmgr)
5656 {
57− const void *table_address;
58− uint16_t idx;
57+ const void *table_address;
58+ uint16_t idx;
5959
60− idx = GetIndexIntoMasterDataTable(voltageobject_info);
61− table_address = cgs_atom_get_data_table(hwmgr->device,
62− idx, NULL, NULL, NULL);
60+ idx = GetIndexIntoMasterDataTable(voltageobject_info);
61+ table_address = smu_atom_get_data_table(hwmgr->adev,
62+ idx, NULL, NULL, NULL);
6363
64− PP_ASSERT_WITH_CODE(
65− table_address,
66− "Error retrieving BIOS Table Address!",
67− return NULL);
64+ PP_ASSERT_WITH_CODE(table_address,
65+ "Error retrieving BIOS Table Address!",
66+ return NULL);
6867
69− return (struct atom_voltage_objects_info_v4_1 *)table_address;
68+ return (struct atom_voltage_objects_info_v4_1 *)table_address;
7069 }
7170
7271 /**
@@ -167,7 +166,7 @@ static struct atom_gpio_pin_lut_v2_1 *pp_atomfwctrl_get_gpio_lookup_table( · 94 unmodified lines
167166 uint16_t idx;
168167
169168 idx = GetIndexIntoMasterDataTable(gpio_pin_lut);
170− table_address = cgs_atom_get_data_table(hwmgr->device,
169+ table_address = smu_atom_get_data_table(hwmgr->adev,
171170 idx, NULL, NULL, NULL);
172171 PP_ASSERT_WITH_CODE(table_address,
173172 "Error retrieving BIOS Table Address!",
@@ -248,28 +247,30 @@ int pp_atomfwctrl_get_gpu_pll_dividers_vega10(struct pp_hwmgr *hwmgr, · 74 unmodified lines
248247 uint32_t clock_type, uint32_t clock_value,
249248 struct pp_atomfwctrl_clock_dividers_soc15 *dividers)
250249 {
250+ struct amdgpu_device *adev = hwmgr->adev;
251251 struct compute_gpu_clock_input_parameter_v1_8 pll_parameters;
252252 struct compute_gpu_clock_output_parameter_v1_8 *pll_output;
253− int result;
254253 uint32_t idx;
255254
256255 pll_parameters.gpuclock_10khz = (uint32_t)clock_value;
257256 pll_parameters.gpu_clock_type = clock_type;
258257
259258 idx = GetIndexIntoMasterCmdTable(computegpuclockparam);
260− result = cgs_atom_exec_cmd_table(hwmgr->device, idx, &pll_parameters);
261−
262− if (!result) {
263− pll_output = (struct compute_gpu_clock_output_parameter_v1_8 *)
264− &pll_parameters;
265− dividers->ulClock = le32_to_cpu(pll_output->gpuclock_10khz);
266− dividers->ulDid = le32_to_cpu(pll_output->dfs_did);
267− dividers->ulPll_fb_mult = le32_to_cpu(pll_output->pll_fb_mult);
268− dividers->ulPll_ss_fbsmult = le32_to_cpu(pll_output->pll_ss_fbsmult);
269− dividers->usPll_ss_slew_frac = le16_to_cpu(pll_output->pll_ss_slew_frac);
270− dividers->ucPll_ss_enable = pll_output->pll_ss_enable;
271− }
272− return result;
259+
260+ if (amdgpu_atom_execute_table(
261+ adev->mode_info.atom_context, idx, (uint32_t *)&pll_parameters))
262+ return -EINVAL;
263+
264+ pll_output = (struct compute_gpu_clock_output_parameter_v1_8 *)
265+ &pll_parameters;
266+ dividers->ulClock = le32_to_cpu(pll_output->gpuclock_10khz);
267+ dividers->ulDid = le32_to_cpu(pll_output->dfs_did);
268+ dividers->ulPll_fb_mult = le32_to_cpu(pll_output->pll_fb_mult);
269+ dividers->ulPll_ss_fbsmult = le32_to_cpu(pll_output->pll_ss_fbsmult);
270+ dividers->usPll_ss_slew_frac = le16_to_cpu(pll_output->pll_ss_slew_frac);
271+ dividers->ucPll_ss_enable = pll_output->pll_ss_enable;
272+
273+ return 0;
273274 }
274275
275276 int pp_atomfwctrl_get_avfs_information(struct pp_hwmgr *hwmgr,
@@ -283,7 +284,7 @@ int pp_atomfwctrl_get_avfs_information(struct pp_hwmgr *hwmgr, · 7 unmodified lines
283284
284285 idx = GetIndexIntoMasterDataTable(asic_profiling_info);
285286 profile = (struct atom_asic_profiling_info_v4_1 *)
286− cgs_atom_get_data_table(hwmgr->device,
287+ smu_atom_get_data_table(hwmgr->adev,
287288 idx, NULL, NULL, NULL);
288289
289290 if (!profile)
@@ -467,7 +468,7 @@ int pp_atomfwctrl_get_gpio_information(struct pp_hwmgr *hwmgr, · 177 unmodified lines
467468
468469 idx = GetIndexIntoMasterDataTable(smu_info);
469470 info = (struct atom_smu_info_v3_1 *)
470− cgs_atom_get_data_table(hwmgr->device,
471+ smu_atom_get_data_table(hwmgr->adev,
471472 idx, NULL, NULL, NULL);
472473
473474 if (!info) {
@@ -487,8 +488,9 @@ int pp_atomfwctrl_get_gpio_information(struct pp_hwmgr *hwmgr, · 13 unmodified lines
487488 return 0;
488489 }
489490
490−int pp_atomfwctrl__get_clk_information_by_clkid(struct pp_hwmgr *hwmgr, BIOS_CLKID id, uint32_t *frequency)
491+int pp_atomfwctrl_get_clk_information_by_clkid(struct pp_hwmgr *hwmgr, BIOS_CLKID id, uint32_t *frequency)
491492 {
493+ struct amdgpu_device *adev = hwmgr->adev;
492494 struct atom_get_smu_clock_info_parameters_v3_1 parameters;
493495 struct atom_get_smu_clock_info_output_parameters_v3_1 *output;
494496 uint32_t ix;
@@ -497,13 +499,13 @@ int pp_atomfwctrl__get_clk_information_by_clkid(struct pp_hwmgr *hwmgr, BIOS_CLK · 2 unmodified lines
497499 parameters.command = GET_SMU_CLOCK_INFO_V3_1_GET_CLOCK_FREQ;
498500
499501 ix = GetIndexIntoMasterCmdTable(getsmuclockinfo);
500− if (!cgs_atom_exec_cmd_table(hwmgr->device, ix, &parameters)) {
501− output = (struct atom_get_smu_clock_info_output_parameters_v3_1 *)&parameters;
502− *frequency = output->atom_smu_outputclkfreq.smu_clock_freq_hz / 10000;
503− } else {
504− pr_info("Error execute_table getsmuclockinfo!");
505− return -1;
506− }
502+
503+ if (amdgpu_atom_execute_table(
504+ adev->mode_info.atom_context, ix, (uint32_t *)&parameters))
505+ return -EINVAL;
506+
507+ output = (struct atom_get_smu_clock_info_output_parameters_v3_1 *)&parameters;
508+ *frequency = output->atom_smu_outputclkfreq.smu_clock_freq_hz / 10000;
507509
508510 return 0;
509511 }
@@ -513,11 +515,10 @@ int pp_atomfwctrl_get_vbios_bootup_values(struct pp_hwmgr *hwmgr, · 3 unmodified lines
513515 {
514516 struct atom_firmware_info_v3_1 *info = NULL;
515517 uint16_t ix;
516− uint32_t frequency = 0;
517518
518519 ix = GetIndexIntoMasterDataTable(firmwareinfo);
519520 info = (struct atom_firmware_info_v3_1 *)
520− cgs_atom_get_data_table(hwmgr->device,
521+ smu_atom_get_data_table(hwmgr->adev,
521522 ix, NULL, NULL, NULL);
522523
523524 if (!info) {
@@ -536,12 +537,6 @@ int pp_atomfwctrl_get_vbios_bootup_values(struct pp_hwmgr *hwmgr, · 12 unmodified lines
536537 boot_values->ulSocClk = 0;
537538 boot_values->ulDCEFClk = 0;
538539
539− if (!pp_atomfwctrl__get_clk_information_by_clkid(hwmgr, SMU9_SYSPLL0_SOCCLK_ID, &frequency))
540− boot_values->ulSocClk = frequency;
541−
542− if (!pp_atomfwctrl__get_clk_information_by_clkid(hwmgr, SMU9_SYSPLL0_DCEFCLK_ID, &frequency))
543− boot_values->ulDCEFClk = frequency;
544−
545540 return 0;
546541 }
547542
@@ -553,7 +548,7 @@ int pp_atomfwctrl_get_smc_dpm_information(struct pp_hwmgr *hwmgr, · 5 unmodified lines
553548
554549 ix = GetIndexIntoMasterDataTable(smc_dpm_info);
555550 info = (struct atom_smc_dpm_info_v4_1 *)
556− cgs_atom_get_data_table(hwmgr->device,
551+ smu_atom_get_data_table(hwmgr->adev,
557552 ix, NULL, NULL, NULL);
558553 if (!info) {
559554 pr_info("Error retrieving BIOS Table Address!");
drivers/gpu/drm/amd/powerplay/hwmgr/ppatomfwctrl.h+2−0
@@ -230,6 +230,8 @@ int pp_atomfwctrl_get_vbios_bootup_values(struct pp_hwmgr *hwmgr, · 229 unmodified lines
230230 struct pp_atomfwctrl_bios_boot_up_values *boot_values);
231231 int pp_atomfwctrl_get_smc_dpm_information(struct pp_hwmgr *hwmgr,
232232 struct pp_atomfwctrl_smc_dpm_parameters *param);
233+int pp_atomfwctrl_get_clk_information_by_clkid(struct pp_hwmgr *hwmgr,
234+ BIOS_CLKID id, uint32_t *frequency);
233235
234236 #endif
235237
drivers/gpu/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c+38−1
@@ -141,7 +141,7 @@ static const void *get_powerplay_table(struct pp_hwmgr *hwmgr) · 140 unmodified lines
141141
142142 if (!table_address) {
143143 table_address = (ATOM_Tonga_POWERPLAYTABLE *)
144− cgs_atom_get_data_table(hwmgr->device,
144+ smu_atom_get_data_table(hwmgr->adev,
145145 index, &size, &frev, &crev);
146146 hwmgr->soft_pp_table = table_address; /*Cache the result in RAM.*/
147147 hwmgr->soft_pp_table_size = size;
@@ -728,6 +728,32 @@ static int get_mm_clock_voltage_table( · 580 unmodified lines
728728 return 0;
729729 }
730730
731+static int get_gpio_table(struct pp_hwmgr *hwmgr,
732+ struct phm_ppt_v1_gpio_table **pp_tonga_gpio_table,
733+ const ATOM_Tonga_GPIO_Table *atom_gpio_table)
734+{
735+ uint32_t table_size;
736+ struct phm_ppt_v1_gpio_table *pp_gpio_table;
737+ struct phm_ppt_v1_information *pp_table_information =
738+ (struct phm_ppt_v1_information *)(hwmgr->pptable);
739+
740+ table_size = sizeof(struct phm_ppt_v1_gpio_table);
741+ pp_gpio_table = kzalloc(table_size, GFP_KERNEL);
742+ if (!pp_gpio_table)
743+ return -ENOMEM;
744+
745+ if (pp_table_information->vdd_dep_on_sclk->count <
746+ atom_gpio_table->ucVRHotTriggeredSclkDpmIndex)
747+ PP_ASSERT_WITH_CODE(false,
748+ "SCLK DPM index for VRHot cannot exceed the total sclk level count!",);
749+ else
750+ pp_gpio_table->vrhot_triggered_sclk_dpm_index =
751+ atom_gpio_table->ucVRHotTriggeredSclkDpmIndex;
752+
753+ *pp_tonga_gpio_table = pp_gpio_table;
754+
755+ return 0;
756+}
731757 /**
732758 * Private Function used during initialization.
733759 * Initialize clock voltage dependency
@@ -761,11 +787,15 @@ static int init_clock_voltage_dependency( · 27 unmodified lines
761787 const PPTable_Generic_SubTable_Header *pcie_table =
762788 (const PPTable_Generic_SubTable_Header *)(((unsigned long) powerplay_table) +
763789 le16_to_cpu(powerplay_table->usPCIETableOffset));
790+ const ATOM_Tonga_GPIO_Table *gpio_table =
791+ (const ATOM_Tonga_GPIO_Table *)(((unsigned long) powerplay_table) +
792+ le16_to_cpu(powerplay_table->usGPIOTableOffset));
764793
765794 pp_table_information->vdd_dep_on_sclk = NULL;
766795 pp_table_information->vdd_dep_on_mclk = NULL;
767796 pp_table_information->mm_dep_table = NULL;
768797 pp_table_information->pcie_table = NULL;
798+ pp_table_information->gpio_table = NULL;
769799
770800 if (powerplay_table->usMMDependencyTableOffset != 0)
771801 result = get_mm_clock_voltage_table(hwmgr,
@@ -810,6 +840,10 @@ static int init_clock_voltage_dependency( · 38 unmodified lines
810840 result = get_valid_clk(hwmgr, &pp_table_information->valid_sclk_values,
811841 pp_table_information->vdd_dep_on_sclk);
812842
843+ if (!result && gpio_table)
844+ result = get_gpio_table(hwmgr, &pp_table_information->gpio_table,
845+ gpio_table);
846+
813847 return result;
814848 }
815849
@@ -1116,6 +1150,9 @@ static int pp_tables_v1_0_uninitialize(struct pp_hwmgr *hwmgr) · 300 unmodified lines
11161150 kfree(pp_table_information->pcie_table);
11171151 pp_table_information->pcie_table = NULL;
11181152
1153+ kfree(pp_table_information->gpio_table);
1154+ pp_table_information->gpio_table = NULL;
1155+
11191156 kfree(hwmgr->pptable);
11201157 hwmgr->pptable = NULL;
11211158
drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c+2−2
@@ -837,7 +837,7 @@ static const ATOM_PPLIB_POWERPLAYTABLE *get_powerplay_table( · 836 unmodified lines
837837 hwmgr->soft_pp_table = &soft_dummy_pp_table[0];
838838 hwmgr->soft_pp_table_size = sizeof(soft_dummy_pp_table);
839839 } else {
840− table_addr = cgs_atom_get_data_table(hwmgr->device,
840+ table_addr = smu_atom_get_data_table(hwmgr->adev,
841841 GetIndexIntoMasterTable(DATA, PowerPlayInfo),
842842 &size, &frev, &crev);
843843 hwmgr->soft_pp_table = table_addr;
@@ -1058,7 +1058,7 @@ static int init_overdrive_limits(struct pp_hwmgr *hwmgr, · 214 unmodified lines
10581058 return 0;
10591059
10601060 /* We assume here that fw_info is unchanged if this call fails.*/
1061− fw_info = cgs_atom_get_data_table(hwmgr->device,
1061+ fw_info = smu_atom_get_data_table(hwmgr->adev,
10621062 GetIndexIntoMasterTable(DATA, FirmwareInfo),
10631063 &size, &frev, &crev);
10641064
drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c+158−28
@@ -34,7 +34,7 @@ · 33 unmodified lines
3434 #include "rv_ppsmc.h"
3535 #include "smu10_hwmgr.h"
3636 #include "power_state.h"
37−#include "pp_soc15.h"
37+#include "soc15_common.h"
3838
3939 #define SMU10_MAX_DEEPSLEEP_DIVIDER_ID 5
4040 #define SMU10_MINIMUM_ENGINE_CLOCK 800 /* 8Mhz, the low boundary of engine clock allowed on this chip */
@@ -42,6 +42,13 @@ · 1 unmodified line
4242 #define SMU10_DISPCLK_BYPASS_THRESHOLD 10000 /* 100Mhz */
4343 #define SMC_RAM_END 0x40000
4444
45+#define mmPWR_MISC_CNTL_STATUS 0x0183
46+#define mmPWR_MISC_CNTL_STATUS_BASE_IDX 0
47+#define PWR_MISC_CNTL_STATUS__PWR_GFX_RLC_CGPG_EN__SHIFT 0x0
48+#define PWR_MISC_CNTL_STATUS__PWR_GFXOFF_STATUS__SHIFT 0x1
49+#define PWR_MISC_CNTL_STATUS__PWR_GFX_RLC_CGPG_EN_MASK 0x00000001L
50+#define PWR_MISC_CNTL_STATUS__PWR_GFXOFF_STATUS_MASK 0x00000006L
51+
4552 static const unsigned long SMU10_Magic = (unsigned long) PHM_Rv_Magic;
4653
4754
@@ -74,11 +81,15 @@ static int smu10_initialize_dpm_defaults(struct pp_hwmgr *hwmgr) · 26 unmodified lines
7481 smu10_data->thermal_auto_throttling_treshold = 0;
7582 smu10_data->is_nb_dpm_enabled = 1;
7683 smu10_data->dpm_flags = 1;
77− smu10_data->gfx_off_controled_by_driver = false;
7884 smu10_data->need_min_deep_sleep_dcefclk = true;
7985 smu10_data->num_active_display = 0;
8086 smu10_data->deep_sleep_dcefclk = 0;
8187
88+ if (hwmgr->feature_mask & PP_GFXOFF_MASK)
89+ smu10_data->gfx_off_controled_by_driver = true;
90+ else
91+ smu10_data->gfx_off_controled_by_driver = false;
92+
8293 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
8394 PHM_PlatformCaps_SclkDeepSleep);
8495
@@ -161,7 +172,7 @@ static int smu10_set_clock_limit(struct pp_hwmgr *hwmgr, const void *input) · 76 unmodified lines
161172 struct PP_Clocks clocks = {0};
162173 struct pp_display_clock_request clock_req;
163174
164− clocks.dcefClock = hwmgr->display_config.min_dcef_set_clk;
175+ clocks.dcefClock = hwmgr->display_config->min_dcef_set_clk;
165176 clock_req.clock_type = amd_pp_dcf_clock;
166177 clock_req.clock_freq_in_khz = clocks.dcefClock * 10;
167178
@@ -206,12 +217,18 @@ static int smu10_set_power_state_tasks(struct pp_hwmgr *hwmgr, const void *input · 38 unmodified lines
206217 static int smu10_init_power_gate_state(struct pp_hwmgr *hwmgr)
207218 {
208219 struct smu10_hwmgr *smu10_data = (struct smu10_hwmgr *)(hwmgr->backend);
220+ struct amdgpu_device *adev = hwmgr->adev;
209221
210222 smu10_data->vcn_power_gated = true;
211223 smu10_data->isp_tileA_power_gated = true;
212224 smu10_data->isp_tileB_power_gated = true;
213225
214− return 0;
226+ if (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG)
227+ return smum_send_msg_to_smc_with_parameter(hwmgr,
228+ PPSMC_MSG_SetGfxCGPG,
229+ true);
230+ else
231+ return 0;
215232 }
216233
217234
@@ -237,13 +254,31 @@ static int smu10_power_off_asic(struct pp_hwmgr *hwmgr) · 19 unmodified lines
237254 return smu10_reset_cc6_data(hwmgr);
238255 }
239256
257+static bool smu10_is_gfx_on(struct pp_hwmgr *hwmgr)
258+{
259+ uint32_t reg;
260+ struct amdgpu_device *adev = hwmgr->adev;
261+
262+ reg = RREG32_SOC15(PWR, 0, mmPWR_MISC_CNTL_STATUS);
263+ if ((reg & PWR_MISC_CNTL_STATUS__PWR_GFXOFF_STATUS_MASK) ==
264+ (0x2 << PWR_MISC_CNTL_STATUS__PWR_GFXOFF_STATUS__SHIFT))
265+ return true;
266+
267+ return false;
268+}
269+
240270 static int smu10_disable_gfx_off(struct pp_hwmgr *hwmgr)
241271 {
242272 struct smu10_hwmgr *smu10_data = (struct smu10_hwmgr *)(hwmgr->backend);
243273
244− if (smu10_data->gfx_off_controled_by_driver)
274+ if (smu10_data->gfx_off_controled_by_driver) {
245275 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_DisableGfxOff);
246276
277+ /* confirm gfx is back to "on" state */
278+ while (!smu10_is_gfx_on(hwmgr))
279+ msleep(1);

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drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.h+1−2

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drivers/gpu/drm/amd/powerplay/hwmgr/smu7_clockpowergating.c+8−8

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drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.h+2−1

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