Main changes for 4.18. I'd like to do a separate pull for vega20 later this week or next. Highlights: - Reserve pre-OS scanout buffer during init for seemless transition from console to driver - VEGAM support - Improved GPU scheduler documentation - Initial gfxoff support for raven - SR-IOV fixes - Default to non-AGP on PowerPC for radeon - Fine grained clock voltage control for vega10 - Power profiles for vega10 - Further clean up of powerplay/driver interface - Underlay fixes - Display link bw updates - Gamma fixes - Scatter/Gather display support on CZ/ST - Misc bug fixes and clean ups [airlied: fixup v3d vs scheduler API change]
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| @@ -78,6 +78,12 @@ extern "C" { · 77 unmodified lines | ||
| 78 | 78 | #define AMDGPU_GEM_DOMAIN_GDS 0x8 |
| 79 | 79 | #define AMDGPU_GEM_DOMAIN_GWS 0x10 |
| 80 | 80 | #define AMDGPU_GEM_DOMAIN_OA 0x20 |
| 81 | +#define AMDGPU_GEM_DOMAIN_MASK (AMDGPU_GEM_DOMAIN_CPU | \ | |
| 82 | + AMDGPU_GEM_DOMAIN_GTT | \ | |
| 83 | + AMDGPU_GEM_DOMAIN_VRAM | \ | |
| 84 | + AMDGPU_GEM_DOMAIN_GDS | \ | |
| 85 | + AMDGPU_GEM_DOMAIN_GWS | \ | |
| 86 | + AMDGPU_GEM_DOMAIN_OA) | |
| 81 | 87 | |
| 82 | 88 | /* Flag that CPU access will be required for the case of VRAM domain */ |
| 83 | 89 | #define AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED (1 << 0) |
| @@ -95,6 +101,10 @@ extern "C" { · 11 unmodified lines | ||
| 95 | 101 | #define AMDGPU_GEM_CREATE_VM_ALWAYS_VALID (1 << 6) |
| 96 | 102 | /* Flag that BO sharing will be explicitly synchronized */ |
| 97 | 103 | #define AMDGPU_GEM_CREATE_EXPLICIT_SYNC (1 << 7) |
| 104 | +/* Flag that indicates allocating MQD gart on GFX9, where the mtype | |
| 105 | + * for the second page onward should be set to NC. | |
| 106 | + */ | |
| 107 | +#define AMDGPU_GEM_CREATE_MQD_GFX9 (1 << 8) | |
| 98 | 108 | |
| 99 | 109 | struct drm_amdgpu_gem_create_in { |
| 100 | 110 | /** the requested memory size */ |
| @@ -520,6 +530,10 @@ union drm_amdgpu_cs { · 419 unmodified lines | ||
| 520 | 530 | /* Preempt flag, IB should set Pre_enb bit if PREEMPT flag detected */ |
| 521 | 531 | #define AMDGPU_IB_FLAG_PREEMPT (1<<2) |
| 522 | 532 | |
| 533 | +/* The IB fence should do the L2 writeback but not invalidate any shader | |
| 534 | + * caches (L2/vL1/sL1/I$). */ | |
| 535 | +#define AMDGPU_IB_FLAG_TC_WB_NOT_INVALIDATE (1 << 3) | |
| 536 | + | |
| 523 | 537 | struct drm_amdgpu_cs_chunk_ib { |
| 524 | 538 | __u32 _pad; |
| 525 | 539 | /** AMDGPU_IB_FLAG_* */ |
| @@ -620,6 +634,12 @@ struct drm_amdgpu_cs_chunk_data { · 94 unmodified lines | ||
| 620 | 634 | #define AMDGPU_INFO_FW_ASD 0x0d |
| 621 | 635 | /* Subquery id: Query VCN firmware version */ |
| 622 | 636 | #define AMDGPU_INFO_FW_VCN 0x0e |
| 637 | + /* Subquery id: Query GFX RLC SRLC firmware version */ | |
| 638 | + #define AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_CNTL 0x0f | |
| 639 | + /* Subquery id: Query GFX RLC SRLG firmware version */ | |
| 640 | + #define AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_GPM_MEM 0x10 | |
| 641 | + /* Subquery id: Query GFX RLC SRLS firmware version */ | |
| 642 | + #define AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_SRM_MEM 0x11 | |
| 623 | 643 | /* number of bytes moved for TTM migration */ |
| 624 | 644 | #define AMDGPU_INFO_NUM_BYTES_MOVED 0x0f |
| 625 | 645 | /* the used VRAM size */ |