Merge tag 'drm-intel-fixes-2018-11-22' of git://anongit.freedesktop.org/drm/drm-intel into drm-fixes

- Fix for fastboot DSI panel boot time flicker regression, also fixes Bugzilla #108225 - Fix Bugzilla #101269 to avoid GPU hangs on Sandybridge machines - Avoid GPU hang on error capture on Broxton with Vt-d enabled - Avoid missing GPU relocations on Pineview and Bearlake (Gen3)

Dave Airlie committed 7 years ago

Commit 98c9cdf2 parents 8cf6f36 f5591567 files · +112 −4Browse files

Unified · Split

7 files

drivers/gpu/drm/i915/i915_gem_execbuffer.c +6 −1
drivers/gpu/drm/i915/i915_gem_gtt.c +5 −0
drivers/gpu/drm/i915/i915_gpu_error.c +14 −1
drivers/gpu/drm/i915/i915_gpu_error.h +7 −1
drivers/gpu/drm/i915/intel_display.c +39 −0
drivers/gpu/drm/i915/intel_drv.h +1 −0
drivers/gpu/drm/i915/intel_pm.c +40 −1

drivers/gpu/drm/i915/i915_gem_execbuffer.c+6−1

 		else if (gen >= 4)
 			len = 4;
 		else
-			len = 3;
+			len = 6;
 		batch = reloc_gpu(eb, vma, len);
 		if (IS_ERR(batch))
 			*batch++ = MI_STORE_DWORD_IMM | MI_MEM_VIRTUAL;
 			*batch++ = addr;
 			*batch++ = target_offset;
+			/* And again for good measure (blb/pnv) */
+			*batch++ = MI_STORE_DWORD_IMM | MI_MEM_VIRTUAL;
+			*batch++ = addr;
+			*batch++ = target_offset;
 		}
 		goto out;

drivers/gpu/drm/i915/i915_gem_gtt.c+5−0

 		ggtt->vm.insert_page    = bxt_vtd_ggtt_insert_page__BKL;
 		if (ggtt->vm.clear_range != nop_clear_range)
 			ggtt->vm.clear_range = bxt_vtd_ggtt_clear_range__BKL;
+		/* Prevent recursively calling stop_machine() and deadlocks. */
+		dev_info(dev_priv->drm.dev,
+			 "Disabling error capture for VT-d workaround\n");
+		i915_disable_error_state(dev_priv, -ENODEV);
 	}
 	ggtt->invalidate = gen6_ggtt_invalidate;

drivers/gpu/drm/i915/i915_gpu_error.c+14−1

 		return 0;
 	}
+	if (IS_ERR(error))
+		return PTR_ERR(error);
 	if (*error->error_msg)
 		err_printf(m, "%s\n", error->error_msg);
 	err_printf(m, "Kernel: " UTS_RELEASE "\n");
 	error = i915_capture_gpu_state(i915);
 	if (!error) {
 		DRM_DEBUG_DRIVER("out of memory, not capturing error state\n");
+		i915_disable_error_state(i915, -ENOMEM);
 		return;
 	}
 	i915->gpu_error.first_error = NULL;
 	spin_unlock_irq(&i915->gpu_error.lock);
-	i915_gpu_state_put(error);
+	if (!IS_ERR(error))
+		i915_gpu_state_put(error);
+}
+void i915_disable_error_state(struct drm_i915_private *i915, int err)
+{
+	spin_lock_irq(&i915->gpu_error.lock);
+	if (!i915->gpu_error.first_error)
+		i915->gpu_error.first_error = ERR_PTR(err);
+	spin_unlock_irq(&i915->gpu_error.lock);
 }

drivers/gpu/drm/i915/i915_gpu_error.h+7−1

 struct i915_gpu_state *i915_first_error_state(struct drm_i915_private *i915);
 void i915_reset_error_state(struct drm_i915_private *i915);
+void i915_disable_error_state(struct drm_i915_private *i915, int err);
 #else
 static inline struct i915_gpu_state *
 i915_first_error_state(struct drm_i915_private *i915)
 {
-	return NULL;
+	return ERR_PTR(-ENODEV);
 }
 static inline void i915_reset_error_state(struct drm_i915_private *i915)
 {
 }
+static inline void i915_disable_error_state(struct drm_i915_private *i915,
+					    int err)
+{
+}
 #endif /* IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR) */
 #endif /* _I915_GPU_ERROR_H_ */

drivers/gpu/drm/i915/intel_display.c+39−0

@@ -2890,6 +2890,7 @@ intel_find_initial_plane_obj(struct intel_crtc *intel_crtc, · 2889 unmodified lines
2890	return;	2890	return;
2891		2891
2892	valid_fb:	2892	valid_fb:
		2893	intel_state->base.rotation = plane_config->rotation;
2893	intel_fill_fb_ggtt_view(&intel_state->view, fb,	2894	intel_fill_fb_ggtt_view(&intel_state->view, fb,
2894	intel_state->base.rotation);	2895	intel_state->base.rotation);
2895	intel_state->color_plane[0].stride =	2896	intel_state->color_plane[0].stride =
@@ -7882,8 +7883,15 @@ i9xx_get_initial_plane_config(struct intel_crtc *crtc, · 4986 unmodified lines
7882	plane_config->tiling = I915_TILING_X;	7883	plane_config->tiling = I915_TILING_X;
7883	fb->modifier = I915_FORMAT_MOD_X_TILED;	7884	fb->modifier = I915_FORMAT_MOD_X_TILED;
7884	}	7885	}
		7886
		7887	if (val & DISPPLANE_ROTATE_180)
		7888	plane_config->rotation = DRM_MODE_ROTATE_180;
7885	}	7889	}
7886		7890
		7891	if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B &&
		7892	val & DISPPLANE_MIRROR)
		7893	plane_config->rotation \|= DRM_MODE_REFLECT_X;
		7894
7887	pixel_format = val & DISPPLANE_PIXFORMAT_MASK;	7895	pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
7888	fourcc = i9xx_format_to_fourcc(pixel_format);	7896	fourcc = i9xx_format_to_fourcc(pixel_format);
7889	fb->format = drm_format_info(fourcc);	7897	fb->format = drm_format_info(fourcc);
@@ -8952,6 +8960,29 @@ skylake_get_initial_plane_config(struct intel_crtc *crtc, · 1062 unmodified lines
8952	goto error;	8960	goto error;
8953	}	8961	}
8954		8962
		8963	/*
		8964	* DRM_MODE_ROTATE_ is counter clockwise to stay compatible with Xrandr
		8965	* while i915 HW rotation is clockwise, thats why this swapping.
		8966	*/
		8967	switch (val & PLANE_CTL_ROTATE_MASK) {
		8968	case PLANE_CTL_ROTATE_0:
		8969	plane_config->rotation = DRM_MODE_ROTATE_0;
		8970	break;
		8971	case PLANE_CTL_ROTATE_90:
		8972	plane_config->rotation = DRM_MODE_ROTATE_270;
		8973	break;
		8974	case PLANE_CTL_ROTATE_180:
		8975	plane_config->rotation = DRM_MODE_ROTATE_180;
		8976	break;
		8977	case PLANE_CTL_ROTATE_270:
		8978	plane_config->rotation = DRM_MODE_ROTATE_90;
		8979	break;
		8980	}
		8981
		8982	if (INTEL_GEN(dev_priv) >= 10 &&
		8983	val & PLANE_CTL_FLIP_HORIZONTAL)
		8984	plane_config->rotation \|= DRM_MODE_REFLECT_X;
		8985
8955	base = I915_READ(PLANE_SURF(pipe, plane_id)) & 0xfffff000;	8986	base = I915_READ(PLANE_SURF(pipe, plane_id)) & 0xfffff000;
8956	plane_config->base = base;	8987	plane_config->base = base;
8957		8988
@@ -15267,6 +15298,14 @@ retry: · 6309 unmodified lines
15267	ret = drm_atomic_add_affected_planes(state, crtc);	15298	ret = drm_atomic_add_affected_planes(state, crtc);
15268	if (ret)	15299	if (ret)
15269	goto out;	15300	goto out;
		15301
		15302	/*
		15303	* FIXME hack to force a LUT update to avoid the
		15304	* plane update forcing the pipe gamma on without
		15305	* having a proper LUT loaded. Remove once we
		15306	* have readout for pipe gamma enable.
		15307	*/
		15308	crtc_state->color_mgmt_changed = true;
15270	}	15309	}
15271	}	15310	}
15272		15311

drivers/gpu/drm/i915/intel_drv.h+1−0

@@ -547,6 +547,7 @@ struct intel_initial_plane_config { · 546 unmodified lines
547	unsigned int tiling;	547	unsigned int tiling;
548	int size;	548	int size;
549	u32 base;	549	u32 base;
		550	u8 rotation;
550	};	551	};
551		552
552	#define SKL_MIN_SRC_W 8	553	#define SKL_MIN_SRC_W 8

drivers/gpu/drm/i915/intel_pm.c+40−1

@@ -2493,6 +2493,9 @@ static uint32_t ilk_compute_pri_wm(const struct intel_crtc_state *cstate, · 2492 unmodified lines
2493	uint32_t method1, method2;	2493	uint32_t method1, method2;
2494	int cpp;	2494	int cpp;
2495		2495
		2496	if (mem_value == 0)
		2497	return U32_MAX;
		2498
2496	if (!intel_wm_plane_visible(cstate, pstate))	2499	if (!intel_wm_plane_visible(cstate, pstate))
2497	return 0;	2500	return 0;
2498		2501
@@ -2522,6 +2525,9 @@ static uint32_t ilk_compute_spr_wm(const struct intel_crtc_state *cstate, · 23 unmodified lines
2522	uint32_t method1, method2;	2525	uint32_t method1, method2;
2523	int cpp;	2526	int cpp;
2524		2527
		2528	if (mem_value == 0)
		2529	return U32_MAX;
		2530
2525	if (!intel_wm_plane_visible(cstate, pstate))	2531	if (!intel_wm_plane_visible(cstate, pstate))
2526	return 0;	2532	return 0;
2527		2533
@@ -2545,6 +2551,9 @@ static uint32_t ilk_compute_cur_wm(const struct intel_crtc_state *cstate, · 17 unmodified lines
2545	{	2551	{
2546	int cpp;	2552	int cpp;
2547		2553
		2554	if (mem_value == 0)
		2555	return U32_MAX;
		2556
2548	if (!intel_wm_plane_visible(cstate, pstate))	2557	if (!intel_wm_plane_visible(cstate, pstate))
2549	return 0;	2558	return 0;
2550		2559
@@ -3008,6 +3017,34 @@ static void snb_wm_latency_quirk(struct drm_i915_private *dev_priv) · 457 unmodified lines
3008	intel_print_wm_latency(dev_priv, "Cursor", dev_priv->wm.cur_latency);	3017	intel_print_wm_latency(dev_priv, "Cursor", dev_priv->wm.cur_latency);
3009	}	3018	}
3010		3019
		3020	static void snb_wm_lp3_irq_quirk(struct drm_i915_private *dev_priv)
		3021	{
		3022	/*
		3023	* On some SNB machines (Thinkpad X220 Tablet at least)
		3024	* LP3 usage can cause vblank interrupts to be lost.
		3025	* The DEIIR bit will go high but it looks like the CPU
		3026	* never gets interrupted.
		3027	*
		3028	* It's not clear whether other interrupt source could
		3029	* be affected or if this is somehow limited to vblank
		3030	* interrupts only. To play it safe we disable LP3
		3031	* watermarks entirely.
		3032	*/
		3033	if (dev_priv->wm.pri_latency[3] == 0 &&
		3034	dev_priv->wm.spr_latency[3] == 0 &&
		3035	dev_priv->wm.cur_latency[3] == 0)
		3036	return;
		3037
		3038	dev_priv->wm.pri_latency[3] = 0;
		3039	dev_priv->wm.spr_latency[3] = 0;
		3040	dev_priv->wm.cur_latency[3] = 0;
		3041
		3042	DRM_DEBUG_KMS("LP3 watermarks disabled due to potential for lost interrupts\n");
		3043	intel_print_wm_latency(dev_priv, "Primary", dev_priv->wm.pri_latency);
		3044	intel_print_wm_latency(dev_priv, "Sprite", dev_priv->wm.spr_latency);
		3045	intel_print_wm_latency(dev_priv, "Cursor", dev_priv->wm.cur_latency);
		3046	}
		3047
3011	static void ilk_setup_wm_latency(struct drm_i915_private *dev_priv)	3048	static void ilk_setup_wm_latency(struct drm_i915_private *dev_priv)
3012	{	3049	{
3013	intel_read_wm_latency(dev_priv, dev_priv->wm.pri_latency);	3050	intel_read_wm_latency(dev_priv, dev_priv->wm.pri_latency);
@@ -3024,8 +3061,10 @@ static void ilk_setup_wm_latency(struct drm_i915_private *dev_priv) · 10 unmodified lines
3024	intel_print_wm_latency(dev_priv, "Sprite", dev_priv->wm.spr_latency);	3061	intel_print_wm_latency(dev_priv, "Sprite", dev_priv->wm.spr_latency);
3025	intel_print_wm_latency(dev_priv, "Cursor", dev_priv->wm.cur_latency);	3062	intel_print_wm_latency(dev_priv, "Cursor", dev_priv->wm.cur_latency);
3026		3063
3027	if (IS_GEN6(dev_priv))	3064	if (IS_GEN6(dev_priv)) {
3028	snb_wm_latency_quirk(dev_priv);	3065	snb_wm_latency_quirk(dev_priv);
		3066	snb_wm_lp3_irq_quirk(dev_priv);
		3067	}
3029	}	3068	}
3030		3069
3031	static void skl_setup_wm_latency(struct drm_i915_private *dev_priv)	3070	static void skl_setup_wm_latency(struct drm_i915_private *dev_priv)

Merge tag 'drm-intel-fixes-2018-11-22' of git://anongit.freedesktop.org/drm/drm-intel into drm-fixes

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