RAS ECC event will combine with GPU reset event, due to ECC interrupts are caused by uncorrectable error that triggers GPU reset. v2: Fix misleading-indentation warning v3: fix build with CONFIG_HSA_AMD disabled
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| @@ -211,6 +211,11 @@ struct kfd_ioctl_dbg_wave_control_args { · 210 unmodified lines | |||
| 211 | #define KFD_HW_EXCEPTION_GPU_HANG 0 | 211 | #define KFD_HW_EXCEPTION_GPU_HANG 0 |
| 212 | #define KFD_HW_EXCEPTION_ECC 1 | 212 | #define KFD_HW_EXCEPTION_ECC 1 |
| 213 | 213 | ||
| 214 | /* For kfd_hsa_memory_exception_data.ErrorType */ | ||
| 215 | #define KFD_MEM_ERR_NO_RAS 0 | ||
| 216 | #define KFD_MEM_ERR_SRAM_ECC 1 | ||
| 217 | #define KFD_MEM_ERR_POISON_CONSUMED 2 | ||
| 218 | #define KFD_MEM_ERR_GPU_HANG 3 | ||
| 214 | 219 | ||
| 215 | struct kfd_ioctl_create_event_args { | 220 | struct kfd_ioctl_create_event_args { |
| 216 | __u64 event_page_offset; /* from KFD */ | 221 | __u64 event_page_offset; /* from KFD */ |
| @@ -250,7 +255,12 @@ struct kfd_hsa_memory_exception_data { · 33 unmodified lines | |||
| 250 | struct kfd_memory_exception_failure failure; | 255 | struct kfd_memory_exception_failure failure; |
| 251 | __u64 va; | 256 | __u64 va; |
| 252 | __u32 gpu_id; | 257 | __u32 gpu_id; |
| 253 | __u32 pad; | 258 | __u32 ErrorType; /* 0 = no RAS error, |
| 259 | * 1 = ECC_SRAM, | ||
| 260 | * 2 = Link_SYNFLOOD (poison), | ||
| 261 | * 3 = GPU hang (not attributable to a specific cause), | ||
| 262 | * other values reserved | ||
| 263 | */ | ||
| 254 | }; | 264 | }; |
| 255 | 265 | ||
| 256 | /* hw exception data */ | 266 | /* hw exception data */ |