irq: Fix typos in comments

Fix ~36 single-word typos in the IRQ, irqchip and irqdomain code comments.

Ingo Molnar committed 5 years ago

Commit a359f751 parent c93a5e223 files · +36 −36Browse files

Unified · Split

23 files

drivers/irqchip/irq-aspeed-vic.c +2 −2
drivers/irqchip/irq-bcm7120-l2.c +1 −1
drivers/irqchip/irq-csky-apb-intc.c +1 −1
drivers/irqchip/irq-gic-v2m.c +1 −1
drivers/irqchip/irq-gic-v3-its.c +5 −5
drivers/irqchip/irq-gic-v3.c +1 −1
drivers/irqchip/irq-loongson-pch-pic.c +1 −1
drivers/irqchip/irq-meson-gpio.c +1 −1
drivers/irqchip/irq-mtk-cirq.c +1 −1
drivers/irqchip/irq-mxs.c +2 −2
drivers/irqchip/irq-sun4i.c +1 −1
drivers/irqchip/irq-ti-sci-inta.c +1 −1
drivers/irqchip/irq-vic.c +2 −2
drivers/irqchip/irq-xilinx-intc.c +1 −1
include/linux/irq.h +2 −2
include/linux/irqdesc.h +1 −1
kernel/irq/chip.c +1 −1
kernel/irq/dummychip.c +1 −1
kernel/irq/irqdesc.c +1 −1
kernel/irq/irqdomain.c +4 −4
kernel/irq/manage.c +3 −3
kernel/irq/msi.c +1 −1
kernel/irq/timings.c +1 −1

@@ -71,7 +71,7 @@ static void vic_init_hw(struct aspeed_vic *vic) · 70 unmodified lines
71	71	writel(0, vic->base + AVIC_INT_SELECT);
72	72	writel(0, vic->base + AVIC_INT_SELECT + 4);
73	73
74		− /* Some interrupts have a programable high/low level trigger
	74	+ /* Some interrupts have a programmable high/low level trigger
75	75	* (4 GPIO direct inputs), for now we assume this was configured
76	76	* by firmware. We read which ones are edge now.
77	77	*/
@@ -203,7 +203,7 @@ static int __init avic_of_init(struct device_node *node, · 125 unmodified lines
203	203	}
204	204	vic->base = regs;
205	205
206		− /* Initialize soures, all masked */
	206	+ /* Initialize sources, all masked */
207	207	vic_init_hw(vic);
208	208
209	209	/* Ready to receive interrupts */

drivers/irqchip/irq-bcm7120-l2.c+1−1

@@ -309,7 +309,7 @@ static int __init bcm7120_l2_intc_probe(struct device_node *dn, · 308 unmodified lines
309	309
310	310	if (data->can_wake) {
311	311	/* This IRQ chip can wake the system, set all
312		− * relevant child interupts in wake_enabled mask
	312	+ * relevant child interrupts in wake_enabled mask
313	313	*/
314	314	gc->wake_enabled = 0xffffffff;
315	315	gc->wake_enabled &= ~gc->unused;

drivers/irqchip/irq-csky-apb-intc.c+1−1

@@ -176,7 +176,7 @@ gx_intc_init(struct device_node node, struct device_node parent) · 175 unmodified lines
176	176	writel(0x0, reg_base + GX_INTC_NEN63_32);
177	177
178	178	/*
179		− * Initial mask reg with all unmasked, because we only use enalbe reg
	179	+ * Initial mask reg with all unmasked, because we only use enable reg
180	180	*/
181	181	writel(0x0, reg_base + GX_INTC_NMASK31_00);
182	182	writel(0x0, reg_base + GX_INTC_NMASK63_32);

drivers/irqchip/irq-gic-v2m.c+1−1

@@ -371,7 +371,7 @@ static int __init gicv2m_init_one(struct fwnode_handle *fwnode, · 370 unmodified lines
371	371	* the MSI data is the absolute value within the range from
372	372	* spi_start to (spi_start + num_spis).
373	373	*
374		− * Broadom NS2 GICv2m implementation has an erratum where the MSI data
	374	+ * Broadcom NS2 GICv2m implementation has an erratum where the MSI data
375	375	* is 'spi_number - 32'
376	376	*
377	377	* Reading that register fails on the Graviton implementation

drivers/irqchip/irq-gic-v3-its.c+5−5

@@ -1492,7 +1492,7 @@ static void its_vlpi_set_doorbell(struct irq_data *d, bool enable) · 1491 unmodified lines
1492	1492	*
1493	1493	* Ideally, we'd issue a VMAPTI to set the doorbell to its LPI
1494	1494	* value or to 1023, depending on the enable bit. But that
1495		− * would be issueing a mapping for an /existing/ DevID+EventID
	1495	+ * would be issuing a mapping for an /existing/ DevID+EventID
1496	1496	* pair, which is UNPREDICTABLE. Instead, let's issue a VMOVI
1497	1497	* to the /same/ vPE, using this opportunity to adjust the
1498	1498	* doorbell. Mouahahahaha. We loves it, Precious.
@@ -3122,7 +3122,7 @@ static void its_cpu_init_lpis(void) · 1623 unmodified lines
3122	3122
3123	3123	/*
3124	3124	* It's possible for CPU to receive VLPIs before it is
3125		− * sheduled as a vPE, especially for the first CPU, and the
	3125	+ * scheduled as a vPE, especially for the first CPU, and the
3126	3126	* VLPI with INTID larger than 2^(IDbits+1) will be considered
3127	3127	* as out of range and dropped by GIC.
3128	3128	* So we initialize IDbits to known value to avoid VLPI drop.
@@ -3616,7 +3616,7 @@ static void its_irq_domain_free(struct irq_domain *domain, unsigned int virq, · 487 unmodified lines
3616	3616
3617	3617	/*
3618	3618	* If all interrupts have been freed, start mopping the
3619		− * floor. This is conditionned on the device not being shared.
	3619	+ * floor. This is conditioned on the device not being shared.
3620	3620	*/
3621	3621	if (!its_dev->shared &&
3622	3622	bitmap_empty(its_dev->event_map.lpi_map,
@@ -4194,7 +4194,7 @@ static int its_sgi_set_affinity(struct irq_data *d, · 571 unmodified lines
4194	4194	{
4195	4195	/*
4196	4196	* There is no notion of affinity for virtual SGIs, at least
4197		− * not on the host (since they can only be targetting a vPE).
	4197	+ * not on the host (since they can only be targeting a vPE).
4198	4198	* Tell the kernel we've done whatever it asked for.
4199	4199	*/
4200	4200	irq_data_update_effective_affinity(d, mask_val);
@@ -4239,7 +4239,7 @@ static int its_sgi_get_irqchip_state(struct irq_data *d, · 38 unmodified lines
4239	4239	/*
4240	4240	* Locking galore! We can race against two different events:
4241	4241	*
4242		− * - Concurent vPE affinity change: we must make sure it cannot
	4242	+ * - Concurrent vPE affinity change: we must make sure it cannot
4243	4243	* happen, or we'll talk to the wrong redistributor. This is
4244	4244	* identical to what happens with vLPIs.
4245	4245	*

drivers/irqchip/irq-gic-v3.c+1−1

@@ -1379,7 +1379,7 @@ static int gic_irq_domain_translate(struct irq_domain *d, · 1378 unmodified lines
1379	1379
1380	1380	/*
1381	1381	* Make it clear that broken DTs are... broken.
1382		− * Partitionned PPIs are an unfortunate exception.
	1382	+ * Partitioned PPIs are an unfortunate exception.
1383	1383	*/
1384	1384	WARN_ON(*type == IRQ_TYPE_NONE &&
1385	1385	fwspec->param[0] != GIC_IRQ_TYPE_PARTITION);

drivers/irqchip/irq-loongson-pch-pic.c+1−1

@@ -163,7 +163,7 @@ static void pch_pic_reset(struct pch_pic *priv) · 162 unmodified lines
163	163	int i;
164	164
165	165	for (i = 0; i < PIC_COUNT; i++) {
166		− /* Write vectore ID */
	166	+ /* Write vectored ID */
167	167	writeb(priv->ht_vec_base + i, priv->base + PCH_INT_HTVEC(i));
168	168	/* Hardcode route to HT0 Lo */
169	169	writeb(1, priv->base + PCH_INT_ROUTE(i));

drivers/irqchip/irq-meson-gpio.c+1−1

@@ -227,7 +227,7 @@ meson_gpio_irq_request_channel(struct meson_gpio_irq_controller *ctl, · 226 unmodified lines
227	227
228	228	/*
229	229	* Get the hwirq number assigned to this channel through
230		− * a pointer the channel_irq table. The added benifit of this
	230	+ * a pointer the channel_irq table. The added benefit of this
231	231	* method is that we can also retrieve the channel index with
232	232	* it, using the table base.
233	233	*/

drivers/irqchip/irq-mtk-cirq.c+1−1

@@ -217,7 +217,7 @@ static void mtk_cirq_resume(void) · 216 unmodified lines
217	217	{
218	218	u32 value;
219	219
220		− /* flush recored interrupts, will send signals to parent controller */
	220	+ /* flush recorded interrupts, will send signals to parent controller */
221	221	value = readl_relaxed(cirq_data->base + CIRQ_CONTROL);
222	222	writel_relaxed(value \| CIRQ_FLUSH, cirq_data->base + CIRQ_CONTROL);
223	223

drivers/irqchip/irq-mxs.c+2−2

@@ -58,7 +58,7 @@ struct icoll_priv { · 57 unmodified lines
58	58	static struct icoll_priv icoll_priv;
59	59	static struct irq_domain *icoll_domain;
60	60
61		−/* calculate bit offset depending on number of intterupt per register */
	61	+/* calculate bit offset depending on number of interrupt per register */
62	62	static u32 icoll_intr_bitshift(struct irq_data *d, u32 bit)
63	63	{
64	64	/*
@@ -68,7 +68,7 @@ static u32 icoll_intr_bitshift(struct irq_data *d, u32 bit) · 3 unmodified lines
68	68	return bit << ((d->hwirq & 3) << 3);
69	69	}
70	70
71		−/* calculate mem offset depending on number of intterupt per register */
	71	+/* calculate mem offset depending on number of interrupt per register */
72	72	static void __iomem icoll_intr_reg(struct irq_data d)
73	73	{
74	74	/* offset = hwirq / intr_per_reg * 0x10 */

drivers/irqchip/irq-sun4i.c+1−1

@@ -189,7 +189,7 @@ static void __exception_irq_entry sun4i_handle_irq(struct pt_regs *regs) · 188 unmodified lines
189	189	* 3) spurious irq
190	190	* So if we immediately get a reading of 0, check the irq-pending reg
191	191	* to differentiate between 2 and 3. We only do this once to avoid
192		− * the extra check in the common case of 1 hapening after having
	192	+ * the extra check in the common case of 1 happening after having
193	193	* read the vector-reg once.
194	194	*/
195	195	hwirq = readl(irq_ic_data->irq_base + SUN4I_IRQ_VECTOR_REG) >> 2;

drivers/irqchip/irq-ti-sci-inta.c+1−1

@@ -78,7 +78,7 @@ struct ti_sci_inta_vint_desc { · 77 unmodified lines
78	78	* struct ti_sci_inta_irq_domain - Structure representing a TISCI based
79	79	* Interrupt Aggregator IRQ domain.
80	80	* @sci: Pointer to TISCI handle
81		− * @vint: TISCI resource pointer representing IA inerrupts.
	81	+ * @vint: TISCI resource pointer representing IA interrupts.
82	82	* @global_event: TISCI resource pointer representing global events.
83	83	* @vint_list: List of the vints active in the system
84	84	* @vint_mutex: Mutex to protect vint_list

drivers/irqchip/irq-vic.c+2−2

@@ -163,7 +163,7 @@ static struct syscore_ops vic_syscore_ops = { · 162 unmodified lines
163	163	};
164	164
165	165	/**
166		− * vic_pm_init - initicall to register VIC pm
	166	+ * vic_pm_init - initcall to register VIC pm
167	167	*
168	168	* This is called via late_initcall() to register
169	169	* the resources for the VICs due to the early
@@ -397,7 +397,7 @@ static void __init vic_clear_interrupts(void __iomem *base) · 227 unmodified lines
397	397	/*
398	398	* The PL190 cell from ARM has been modified by ST to handle 64 interrupts.
399	399	* The original cell has 32 interrupts, while the modified one has 64,
400		− * replocating two blocks 0x00..0x1f in 0x20..0x3f. In that case
	400	+ * replicating two blocks 0x00..0x1f in 0x20..0x3f. In that case
401	401	* the probe function is called twice, with base set to offset 000
402	402	* and 020 within the page. We call this "second block".
403	403	*/

drivers/irqchip/irq-xilinx-intc.c+1−1

@@ -210,7 +210,7 @@ static int __init xilinx_intc_of_init(struct device_node *intc, · 209 unmodified lines
210	210
211	211	/*
212	212	* Disable all external interrupts until they are
213		− * explicity requested.
	213	+ * explicitly requested.
214	214	*/
215	215	xintc_write(irqc, IER, 0);
216	216

include/linux/irq.h+2−2

@@ -116,7 +116,7 @@ enum { · 115 unmodified lines
116	116	* IRQ_SET_MASK_NOCPY - OK, chip did update irq_common_data.affinity
117	117	* IRQ_SET_MASK_OK_DONE - Same as IRQ_SET_MASK_OK for core. Special code to
118	118	* support stacked irqchips, which indicates skipping
119		− * all descendent irqchips.
	119	+ * all descendant irqchips.
120	120	*/
121	121	enum {
122	122	IRQ_SET_MASK_OK = 0,
@@ -302,7 +302,7 @@ static inline bool irqd_is_level_type(struct irq_data *d) · 179 unmodified lines
302	302
303	303	/*
304	304	* Must only be called of irqchip.irq_set_affinity() or low level
305		− * hieararchy domain allocation functions.
	305	+ * hierarchy domain allocation functions.
306	306	*/
307	307	static inline void irqd_set_single_target(struct irq_data *d)
308	308	{

include/linux/irqdesc.h+1−1

@@ -32,7 +32,7 @@ struct pt_regs; · 31 unmodified lines
32	32	* @last_unhandled: aging timer for unhandled count
33	33	* @irqs_unhandled: stats field for spurious unhandled interrupts
34	34	* @threads_handled: stats field for deferred spurious detection of threaded handlers
35		− * @threads_handled_last: comparator field for deferred spurious detection of theraded handlers
	35	+ * @threads_handled_last: comparator field for deferred spurious detection of threaded handlers
36	36	* @lock: locking for SMP
37	37	* @affinity_hint: hint to user space for preferred irq affinity
38	38	* @affinity_notify: context for notification of affinity changes

kernel/irq/chip.c+1−1

@@ -808,7 +808,7 @@ void handle_edge_irq(struct irq_desc *desc) · 807 unmodified lines
808	808	/*
809	809	* When another irq arrived while we were handling
810	810	* one, we could have masked the irq.
811		− * Renable it, if it was not disabled in meantime.
	811	+ * Reenable it, if it was not disabled in meantime.
812	812	*/
813	813	if (unlikely(desc->istate & IRQS_PENDING)) {
814	814	if (!irqd_irq_disabled(&desc->irq_data) &&

kernel/irq/dummychip.c+1−1

@@ -13,7 +13,7 @@ · 12 unmodified lines
13	13
14	14	/*
15	15	* What should we do if we get a hw irq event on an illegal vector?
16		− * Each architecture has to answer this themself.
	16	+ * Each architecture has to answer this themselves.
17	17	*/
18	18	static void ack_bad(struct irq_data *data)
19	19	{

kernel/irq/irqdesc.c+1−1

@@ -31,7 +31,7 @@ static int __init irq_affinity_setup(char *str) · 30 unmodified lines
31	31	cpulist_parse(str, irq_default_affinity);
32	32	/*
33	33	* Set at least the boot cpu. We don't want to end up with
34		− * bugreports caused by random comandline masks
	34	+ * bugreports caused by random commandline masks
35	35	*/
36	36	cpumask_set_cpu(smp_processor_id(), irq_default_affinity);
37	37	return 1;

kernel/irq/irqdomain.c+4−4

@@ -62,7 +62,7 @@ EXPORT_SYMBOL_GPL(irqchip_fwnode_ops); · 61 unmodified lines
62	62	* @name: Optional user provided domain name
63	63	* @pa: Optional user-provided physical address
64	64	*
65		− * Allocate a struct irqchip_fwid, and return a poiner to the embedded
	65	+ * Allocate a struct irqchip_fwid, and return a pointer to the embedded
66	66	* fwnode_handle (or NULL on failure).
67	67	*
68	68	* Note: The types IRQCHIP_FWNODE_NAMED and IRQCHIP_FWNODE_NAMED_ID are
@@ -665,7 +665,7 @@ unsigned int irq_create_mapping_affinity(struct irq_domain *domain, · 596 unmodified lines
665	665
666	666	pr_debug("irq_create_mapping(0x%p, 0x%lx)\n", domain, hwirq);
667	667
668		− /* Look for default domain if nececssary */
	668	+ /* Look for default domain if necessary */
669	669	if (domain == NULL)
670	670	domain = irq_default_domain;
671	671	if (domain == NULL) {
@@ -906,7 +906,7 @@ unsigned int irq_find_mapping(struct irq_domain *domain, · 234 unmodified lines
906	906	{
907	907	struct irq_data *data;
908	908
909		− /* Look for default domain if nececssary */
	909	+ /* Look for default domain if necessary */
910	910	if (domain == NULL)
911	911	domain = irq_default_domain;
912	912	if (domain == NULL)
@@ -1436,7 +1436,7 @@ int irq_domain_alloc_irqs_hierarchy(struct irq_domain *domain, · 523 unmodified lines
1436	1436	* The whole process to setup an IRQ has been split into two steps.
1437	1437	* The first step, __irq_domain_alloc_irqs(), is to allocate IRQ
1438	1438	* descriptor and required hardware resources. The second step,
1439		− * irq_domain_activate_irq(), is to program hardwares with preallocated
	1439	+ * irq_domain_activate_irq(), is to program the hardware with preallocated
1440	1440	* resources. In this way, it's easier to rollback when failing to
1441	1441	* allocate resources.
1442	1442	*/

kernel/irq/manage.c+3−3

@@ -326,7 +326,7 @@ static bool irq_set_affinity_deactivated(struct irq_data *data, · 325 unmodified lines
326	326	* If the interrupt is not yet activated, just store the affinity
327	327	* mask and do not call the chip driver at all. On activation the
328	328	* driver has to make sure anyway that the interrupt is in a
329		− * useable state so startup works.
	329	+ * usable state so startup works.
330	330	*/
331	331	if (!IS_ENABLED(CONFIG_IRQ_DOMAIN_HIERARCHY) \|\|
332	332	irqd_is_activated(data) \|\| !irqd_affinity_on_activate(data))
@@ -1054,7 +1054,7 @@ again: · 721 unmodified lines
1054	1054	* to IRQS_INPROGRESS and the irq line is masked forever.
1055	1055	*
1056	1056	* This also serializes the state of shared oneshot handlers
1057		− * versus "desc->threads_onehsot \|= action->thread_mask;" in
	1057	+ * versus "desc->threads_oneshot \|= action->thread_mask;" in
1058	1058	* irq_wake_thread(). See the comment there which explains the
1059	1059	* serialization.
1060	1060	*/
@@ -1909,7 +1909,7 @@ static struct irqaction __free_irq(struct irq_desc desc, void *dev_id) · 848 unmodified lines
1909	1909	/* Last action releases resources */
1910	1910	if (!desc->action) {
1911	1911	/*
1912		− * Reaquire bus lock as irq_release_resources() might
	1912	+ * Reacquire bus lock as irq_release_resources() might
1913	1913	* require it to deallocate resources over the slow bus.
1914	1914	*/
1915	1915	chip_bus_lock(desc);

kernel/irq/msi.c+1−1

@@ -5,7 +5,7 @@ · 4 unmodified lines
5	5	*
6	6	* This file is licensed under GPLv2.
7	7	*
8		− * This file contains common code to support Message Signalled Interrupt for
	8	+ * This file contains common code to support Message Signaled Interrupts for
9	9	* PCI compatible and non PCI compatible devices.
10	10	*/
11	11	#include <linux/types.h>

kernel/irq/timings.c+1−1

@@ -485,7 +485,7 @@ static inline void irq_timings_store(int irq, struct irqt_stat *irqs, u64 ts) · 484 unmodified lines
485	485
486	486	/*
487	487	* The interrupt triggered more than one second apart, that
488		− * ends the sequence as predictible for our purpose. In this
	488	+ * ends the sequence as predictable for our purpose. In this
489	489	* case, assume we have the beginning of a sequence and the
490	490	* timestamp is the first value. As it is impossible to
491	491	* predict anything at this point, return.

irq: Fix typos in comments

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