Pull ARM SoC devicetree updates from Arnd Bergmann: "As usual, this is the bulk of the updates for the SoC tree, adding more devices to existing files, addressing issues from ever improving automated checking, and fixing minor issues. The most interesting bits as usual are the new platforms. All the newly supported SoCs belong into existing families this time: - Qualcomm gets support for two newly announced platforms, both of which can now work in production environments: the SDX65 5G modem that can run a minimal Linux on its Cortex-A7 core, and the Snapdragon 8 Gen 1, their latest high-end phone SoC. - Renesas adds support for R-Car S4-8, the most recent automotive Server/Communication SoC. - TI adds support for J721s2, a new automotive SoC in the K3 family. - Mediatek MT7986a/b is a SoC used in Wifi routers, the latest generation following their popular MT76xx series. Only basic support is added for now. - NXP i.MX8 ULP8 is a new low-power variant of the widespread i.MX8 series. - TI SPEAr320s is a minor variant of the old SPEAr320 SoC that we have supported for a long time. New boards with the existing SoCs include - Aspeed AST2500/AST2600 BMCs in TYAN, Facebook and Yadro servers - AT91/SAMA5 based evaluation board - NXP gains twenty new development and industrial boards for their i.MX and Layerscape SoCs - Intel IXP4xx now supports the final two machines in device tree that were previously only supported in old style board files. - Mediatek MT6589 is used in the Fairphone FP1 phone from 2013, while MT8183 is used in the Acer Chromebook 314. - Qualcomm gains support for the reference machines using the two new SoCs, plus a number of Chromebook variants and phones based on the Snapdragon 7c, 845 and 888 SoCs, including various Sony Xperia devices and the Microsoft Surface Duo 2. - ST STM32 now supports the Engicam i.Core STM32MP1 carrier board. - Tegra now boots various older Android devices based on 32-bit chips out of the box, including a number of ASUS Transformer tablets. There is also a new Jetson AGX Orin developer kit. - Apple support adds the missing device trees for all the remaining M1 Macbook and iMac variants, though not yet the M1 Pro/Max versions. - Allwinner now supports another version of the Tanix TX6 set-top box based on the H6 SoC. - Broadcom gains support for the Netgear RAXE500 Wireless router based on BCM4908" * tag 'dt-5.17' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (574 commits) Revert "ARM: dts: BCM5301X: define RTL8365MB switch on Asus RT-AC88U" arm64: dts: qcom: sm6125: Avoid using missing SM6125_VDDCX arm64: dts: qcom: sm8450-qrd: Enable USB nodes arm64: dts: qcom: sm8450: Add usb nodes ARM: dts: aspeed: add LCLK setting into LPC KCS nodes dt-bindings: ipmi: bt-bmc: add 'clocks' as a required property ARM: dts: aspeed: add LCLK setting into LPC IBT node ARM: dts: aspeed: p10: Add TPM device ARM: dts: aspeed: p10: Enable USB host ports ARM: dts: aspeed: Add TYAN S8036 BMC machine ARM: dts: aspeed: tyan-s7106: Add uart_routing and fix vuart config ARM: dts: aspeed: Adding Facebook Bletchley BMC ARM: dts: aspeed: g220a: Enable secondary flash ARM: dts: Add openbmc-flash-layout-64-alt.dtsi ARM: dts: aspeed: Add secure boot controller node dt-bindings: aspeed: Add Secure Boot Controller bindings ARM: dts: Remove "spidev" nodes dt-bindings: pinctrl: samsung: Add pin drive definitions for Exynos850 dt-bindings: arm: samsung: Document E850-96 board binding dt-bindings: Add vendor prefix for WinLink ...
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| 1 | /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ | ||
| 2 | /* | ||
| 3 | * Copyright (c) 2021, Qualcomm Innovation Center, Inc. All rights reserved. | ||
| 4 | */ | ||
| 5 | |||
| 6 | #ifndef _DT_BINDINGS_CLK_QCOM_GCC_SDX65_H | ||
| 7 | #define _DT_BINDINGS_CLK_QCOM_GCC_SDX65_H | ||
| 8 | |||
| 9 | /* GCC clocks */ | ||
| 10 | #define GPLL0 0 | ||
| 11 | #define GPLL0_OUT_EVEN 1 | ||
| 12 | #define GCC_AHB_PCIE_LINK_CLK 2 | ||
| 13 | #define GCC_BLSP1_AHB_CLK 3 | ||
| 14 | #define GCC_BLSP1_QUP1_I2C_APPS_CLK 4 | ||
| 15 | #define GCC_BLSP1_QUP1_I2C_APPS_CLK_SRC 5 | ||
| 16 | #define GCC_BLSP1_QUP1_SPI_APPS_CLK 6 | ||
| 17 | #define GCC_BLSP1_QUP1_SPI_APPS_CLK_SRC 7 | ||
| 18 | #define GCC_BLSP1_QUP2_I2C_APPS_CLK 8 | ||
| 19 | #define GCC_BLSP1_QUP2_I2C_APPS_CLK_SRC 9 | ||
| 20 | #define GCC_BLSP1_QUP2_SPI_APPS_CLK 10 | ||
| 21 | #define GCC_BLSP1_QUP2_SPI_APPS_CLK_SRC 11 | ||
| 22 | #define GCC_BLSP1_QUP3_I2C_APPS_CLK 12 | ||
| 23 | #define GCC_BLSP1_QUP3_I2C_APPS_CLK_SRC 13 | ||
| 24 | #define GCC_BLSP1_QUP3_SPI_APPS_CLK 14 | ||
| 25 | #define GCC_BLSP1_QUP3_SPI_APPS_CLK_SRC 15 | ||
| 26 | #define GCC_BLSP1_QUP4_I2C_APPS_CLK 16 | ||
| 27 | #define GCC_BLSP1_QUP4_I2C_APPS_CLK_SRC 17 | ||
| 28 | #define GCC_BLSP1_QUP4_SPI_APPS_CLK 18 | ||
| 29 | #define GCC_BLSP1_QUP4_SPI_APPS_CLK_SRC 19 | ||
| 30 | #define GCC_BLSP1_SLEEP_CLK 20 | ||
| 31 | #define GCC_BLSP1_UART1_APPS_CLK 21 | ||
| 32 | #define GCC_BLSP1_UART1_APPS_CLK_SRC 22 | ||
| 33 | #define GCC_BLSP1_UART2_APPS_CLK 23 | ||
| 34 | #define GCC_BLSP1_UART2_APPS_CLK_SRC 24 | ||
| 35 | #define GCC_BLSP1_UART3_APPS_CLK 25 | ||
| 36 | #define GCC_BLSP1_UART3_APPS_CLK_SRC 26 | ||
| 37 | #define GCC_BLSP1_UART4_APPS_CLK 27 | ||
| 38 | #define GCC_BLSP1_UART4_APPS_CLK_SRC 28 | ||
| 39 | #define GCC_BOOT_ROM_AHB_CLK 29 | ||
| 40 | #define GCC_CPUSS_AHB_CLK 30 | ||
| 41 | #define GCC_CPUSS_AHB_CLK_SRC 31 | ||
| 42 | #define GCC_CPUSS_AHB_POSTDIV_CLK_SRC 32 | ||
| 43 | #define GCC_CPUSS_GNOC_CLK 33 | ||
| 44 | #define GCC_GP1_CLK 34 | ||
| 45 | #define GCC_GP1_CLK_SRC 35 | ||
| 46 | #define GCC_GP2_CLK 36 | ||
| 47 | #define GCC_GP2_CLK_SRC 37 | ||
| 48 | #define GCC_GP3_CLK 38 | ||
| 49 | #define GCC_GP3_CLK_SRC 39 | ||
| 50 | #define GCC_PCIE_0_CLKREF_EN 40 | ||
| 51 | #define GCC_PCIE_AUX_CLK 41 | ||
| 52 | #define GCC_PCIE_AUX_CLK_SRC 42 | ||
| 53 | #define GCC_PCIE_AUX_PHY_CLK_SRC 43 | ||
| 54 | #define GCC_PCIE_CFG_AHB_CLK 44 | ||
| 55 | #define GCC_PCIE_MSTR_AXI_CLK 45 | ||
| 56 | #define GCC_PCIE_PIPE_CLK 46 | ||
| 57 | #define GCC_PCIE_PIPE_CLK_SRC 47 | ||
| 58 | #define GCC_PCIE_RCHNG_PHY_CLK 48 | ||
| 59 | #define GCC_PCIE_RCHNG_PHY_CLK_SRC 49 | ||
| 60 | #define GCC_PCIE_SLEEP_CLK 50 | ||
| 61 | #define GCC_PCIE_SLV_AXI_CLK 51 | ||
| 62 | #define GCC_PCIE_SLV_Q2A_AXI_CLK 52 | ||
| 63 | #define GCC_PDM2_CLK 53 | ||
| 64 | #define GCC_PDM2_CLK_SRC 54 | ||
| 65 | #define GCC_PDM_AHB_CLK 55 | ||
| 66 | #define GCC_PDM_XO4_CLK 56 | ||
| 67 | #define GCC_RX1_USB2_CLKREF_EN 57 | ||
| 68 | #define GCC_SDCC1_AHB_CLK 58 | ||
| 69 | #define GCC_SDCC1_APPS_CLK 59 | ||
| 70 | #define GCC_SDCC1_APPS_CLK_SRC 60 | ||
| 71 | #define GCC_SPMI_FETCHER_AHB_CLK 61 | ||
| 72 | #define GCC_SPMI_FETCHER_CLK 62 | ||
| 73 | #define GCC_SPMI_FETCHER_CLK_SRC 63 | ||
| 74 | #define GCC_SYS_NOC_CPUSS_AHB_CLK 64 | ||
| 75 | #define GCC_USB30_MASTER_CLK 65 | ||
| 76 | #define GCC_USB30_MASTER_CLK_SRC 66 | ||
| 77 | #define GCC_USB30_MOCK_UTMI_CLK 67 | ||
| 78 | #define GCC_USB30_MOCK_UTMI_CLK_SRC 68 | ||
| 79 | #define GCC_USB30_MOCK_UTMI_POSTDIV_CLK_SRC 69 | ||
| 80 | #define GCC_USB30_MSTR_AXI_CLK 70 | ||
| 81 | #define GCC_USB30_SLEEP_CLK 71 | ||
| 82 | #define GCC_USB30_SLV_AHB_CLK 72 | ||
| 83 | #define GCC_USB3_PHY_AUX_CLK 73 | ||
| 84 | #define GCC_USB3_PHY_AUX_CLK_SRC 74 | ||
| 85 | #define GCC_USB3_PHY_PIPE_CLK 75 | ||
| 86 | #define GCC_USB3_PHY_PIPE_CLK_SRC 76 | ||
| 87 | #define GCC_USB3_PRIM_CLKREF_EN 77 | ||
| 88 | #define GCC_USB_PHY_CFG_AHB2PHY_CLK 78 | ||
| 89 | #define GCC_XO_DIV4_CLK 79 | ||
| 90 | #define GCC_XO_PCIE_LINK_CLK 80 | ||
| 91 | |||
| 92 | /* GCC resets */ | ||
| 93 | #define GCC_BLSP1_QUP1_BCR 0 | ||
| 94 | #define GCC_BLSP1_QUP2_BCR 1 | ||
| 95 | #define GCC_BLSP1_QUP3_BCR 2 | ||
| 96 | #define GCC_BLSP1_QUP4_BCR 3 | ||
| 97 | #define GCC_BLSP1_UART1_BCR 4 | ||
| 98 | #define GCC_BLSP1_UART2_BCR 5 | ||
| 99 | #define GCC_BLSP1_UART3_BCR 6 | ||
| 100 | #define GCC_BLSP1_UART4_BCR 7 | ||
| 101 | #define GCC_PCIE_BCR 8 | ||
| 102 | #define GCC_PCIE_LINK_DOWN_BCR 9 | ||
| 103 | #define GCC_PCIE_NOCSR_COM_PHY_BCR 10 | ||
| 104 | #define GCC_PCIE_PHY_BCR 11 | ||
| 105 | #define GCC_PCIE_PHY_CFG_AHB_BCR 12 | ||
| 106 | #define GCC_PCIE_PHY_COM_BCR 13 | ||
| 107 | #define GCC_PCIE_PHY_NOCSR_COM_PHY_BCR 14 | ||
| 108 | #define GCC_PDM_BCR 15 | ||
| 109 | #define GCC_QUSB2PHY_BCR 16 | ||
| 110 | #define GCC_SDCC1_BCR 17 | ||
| 111 | #define GCC_SPMI_FETCHER_BCR 18 | ||
| 112 | #define GCC_TCSR_PCIE_BCR 19 | ||
| 113 | #define GCC_USB30_BCR 20 | ||
| 114 | #define GCC_USB3_PHY_BCR 21 | ||
| 115 | #define GCC_USB3PHY_PHY_BCR 22 | ||
| 116 | #define GCC_USB_PHY_CFG_AHB2PHY_BCR 23 | ||
| 117 | |||
| 118 | /* GCC power domains */ | ||
| 119 | #define USB30_GDSC 0 | ||
| 120 | #define PCIE_GDSC 1 | ||
| 121 | |||
| 122 | #endif | ||
| @@ -0,0 +1,244 @@ | |||
| 1 | /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ | ||
| 2 | /* | ||
| 3 | * Copyright (c) 2020, The Linux Foundation. All rights reserved. | ||
| 4 | * Copyright (c) 2021, Linaro Limited | ||
| 5 | */ | ||
| 6 | |||
| 7 | #ifndef _DT_BINDINGS_CLK_QCOM_GCC_SM8450_H | ||
| 8 | #define _DT_BINDINGS_CLK_QCOM_GCC_SM8450_H | ||
| 9 | |||
| 10 | /* GCC HW clocks */ | ||
| 11 | #define CORE_BI_PLL_TEST_SE 0 | ||
| 12 | #define PCIE_0_PIPE_CLK 1 | ||
| 13 | #define PCIE_1_PHY_AUX_CLK 2 | ||
| 14 | #define PCIE_1_PIPE_CLK 3 | ||
| 15 | #define UFS_PHY_RX_SYMBOL_0_CLK 4 | ||
| 16 | #define UFS_PHY_RX_SYMBOL_1_CLK 5 | ||
| 17 | #define UFS_PHY_TX_SYMBOL_0_CLK 6 | ||
| 18 | #define USB3_PHY_WRAPPER_GCC_USB30_PIPE_CLK 7 | ||
| 19 | |||
| 20 | /* GCC clocks */ | ||
| 21 | #define GCC_AGGRE_NOC_PCIE_0_AXI_CLK 8 | ||
| 22 | #define GCC_AGGRE_NOC_PCIE_1_AXI_CLK 9 | ||
| 23 | #define GCC_AGGRE_UFS_PHY_AXI_CLK 10 | ||
| 24 | #define GCC_AGGRE_UFS_PHY_AXI_HW_CTL_CLK 11 | ||
| 25 | #define GCC_AGGRE_USB3_PRIM_AXI_CLK 12 | ||
| 26 | #define GCC_ANOC_PCIE_PWRCTL_CLK 13 | ||
| 27 | #define GCC_BOOT_ROM_AHB_CLK 14 | ||
| 28 | #define GCC_CAMERA_AHB_CLK 15 | ||
| 29 | #define GCC_CAMERA_HF_AXI_CLK 16 | ||
| 30 | #define GCC_CAMERA_SF_AXI_CLK 17 | ||
| 31 | #define GCC_CAMERA_XO_CLK 18 | ||
| 32 | #define GCC_CFG_NOC_PCIE_ANOC_AHB_CLK 19 | ||
| 33 | #define GCC_CFG_NOC_USB3_PRIM_AXI_CLK 20 | ||
| 34 | #define GCC_CPUSS_AHB_CLK 21 | ||
| 35 | #define GCC_CPUSS_AHB_CLK_SRC 22 | ||
| 36 | #define GCC_CPUSS_AHB_POSTDIV_CLK_SRC 23 | ||
| 37 | #define GCC_CPUSS_CONFIG_NOC_SF_CLK 24 | ||
| 38 | #define GCC_DDRSS_GPU_AXI_CLK 25 | ||
| 39 | #define GCC_DDRSS_PCIE_SF_TBU_CLK 26 | ||
| 40 | #define GCC_DISP_AHB_CLK 27 | ||
| 41 | #define GCC_DISP_HF_AXI_CLK 28 | ||
| 42 | #define GCC_DISP_SF_AXI_CLK 29 | ||
| 43 | #define GCC_DISP_XO_CLK 30 | ||
| 44 | #define GCC_EUSB3_0_CLKREF_EN 31 | ||
| 45 | #define GCC_GP1_CLK 32 | ||
| 46 | #define GCC_GP1_CLK_SRC 33 | ||
| 47 | #define GCC_GP2_CLK 34 | ||
| 48 | #define GCC_GP2_CLK_SRC 35 | ||
| 49 | #define GCC_GP3_CLK 36 | ||
| 50 | #define GCC_GP3_CLK_SRC 37 | ||
| 51 | #define GCC_GPLL0 38 | ||
| 52 | #define GCC_GPLL0_OUT_EVEN 39 | ||
| 53 | #define GCC_GPLL4 40 | ||
| 54 | #define GCC_GPLL9 41 | ||
| 55 | #define GCC_GPU_CFG_AHB_CLK 42 | ||
| 56 | #define GCC_GPU_GPLL0_CLK_SRC 43 | ||
| 57 | #define GCC_GPU_GPLL0_DIV_CLK_SRC 44 | ||
| 58 | #define GCC_GPU_MEMNOC_GFX_CLK 45 | ||
| 59 | #define GCC_GPU_SNOC_DVM_GFX_CLK 46 | ||
| 60 | #define GCC_PCIE_0_AUX_CLK 47 | ||
| 61 | #define GCC_PCIE_0_AUX_CLK_SRC 48 | ||
| 62 | #define GCC_PCIE_0_CFG_AHB_CLK 49 | ||
| 63 | #define GCC_PCIE_0_CLKREF_EN 50 | ||
| 64 | #define GCC_PCIE_0_MSTR_AXI_CLK 51 | ||
| 65 | #define GCC_PCIE_0_PHY_RCHNG_CLK 52 | ||
| 66 | #define GCC_PCIE_0_PHY_RCHNG_CLK_SRC 53 | ||
| 67 | #define GCC_PCIE_0_PIPE_CLK 54 | ||
| 68 | #define GCC_PCIE_0_PIPE_CLK_SRC 55 | ||
| 69 | #define GCC_PCIE_0_SLV_AXI_CLK 56 | ||
| 70 | #define GCC_PCIE_0_SLV_Q2A_AXI_CLK 57 | ||
| 71 | #define GCC_PCIE_1_AUX_CLK 58 | ||
| 72 | #define GCC_PCIE_1_AUX_CLK_SRC 59 | ||
| 73 | #define GCC_PCIE_1_CFG_AHB_CLK 60 | ||
| 74 | #define GCC_PCIE_1_CLKREF_EN 61 | ||
| 75 | #define GCC_PCIE_1_MSTR_AXI_CLK 62 | ||
| 76 | #define GCC_PCIE_1_PHY_AUX_CLK 63 | ||
| 77 | #define GCC_PCIE_1_PHY_AUX_CLK_SRC 64 | ||
| 78 | #define GCC_PCIE_1_PHY_RCHNG_CLK 65 | ||
| 79 | #define GCC_PCIE_1_PHY_RCHNG_CLK_SRC 66 | ||
| 80 | #define GCC_PCIE_1_PIPE_CLK 67 | ||
| 81 | #define GCC_PCIE_1_PIPE_CLK_SRC 68 | ||
| 82 | #define GCC_PCIE_1_SLV_AXI_CLK 69 | ||
| 83 | #define GCC_PCIE_1_SLV_Q2A_AXI_CLK 70 | ||
| 84 | #define GCC_PDM2_CLK 71 | ||
| 85 | #define GCC_PDM2_CLK_SRC 72 | ||
| 86 | #define GCC_PDM_AHB_CLK 73 | ||
| 87 | #define GCC_PDM_XO4_CLK 74 | ||
| 88 | #define GCC_QMIP_CAMERA_NRT_AHB_CLK 75 | ||
| 89 | #define GCC_QMIP_CAMERA_RT_AHB_CLK 76 | ||
| 90 | #define GCC_QMIP_DISP_AHB_CLK 77 | ||
| 91 | #define GCC_QMIP_GPU_AHB_CLK 78 | ||
| 92 | #define GCC_QMIP_PCIE_AHB_CLK 79 | ||
| 93 | #define GCC_QMIP_VIDEO_CV_CPU_AHB_CLK 80 | ||
| 94 | #define GCC_QMIP_VIDEO_CVP_AHB_CLK 81 | ||
| 95 | #define GCC_QMIP_VIDEO_V_CPU_AHB_CLK 82 | ||
| 96 | #define GCC_QMIP_VIDEO_VCODEC_AHB_CLK 83 | ||
| 97 | #define GCC_QUPV3_WRAP0_CORE_2X_CLK 84 | ||
| 98 | #define GCC_QUPV3_WRAP0_CORE_CLK 85 | ||
| 99 | #define GCC_QUPV3_WRAP0_S0_CLK 86 | ||
| 100 | #define GCC_QUPV3_WRAP0_S0_CLK_SRC 87 | ||
| 101 | #define GCC_QUPV3_WRAP0_S1_CLK 88 | ||
| 102 | #define GCC_QUPV3_WRAP0_S1_CLK_SRC 89 | ||
| 103 | #define GCC_QUPV3_WRAP0_S2_CLK 90 | ||
| 104 | #define GCC_QUPV3_WRAP0_S2_CLK_SRC 91 | ||
| 105 | #define GCC_QUPV3_WRAP0_S3_CLK 92 | ||
| 106 | #define GCC_QUPV3_WRAP0_S3_CLK_SRC 93 | ||
| 107 | #define GCC_QUPV3_WRAP0_S4_CLK 94 | ||
| 108 | #define GCC_QUPV3_WRAP0_S4_CLK_SRC 95 | ||
| 109 | #define GCC_QUPV3_WRAP0_S5_CLK 96 | ||
| 110 | #define GCC_QUPV3_WRAP0_S5_CLK_SRC 97 | ||
| 111 | #define GCC_QUPV3_WRAP0_S6_CLK 98 | ||
| 112 | #define GCC_QUPV3_WRAP0_S6_CLK_SRC 99 | ||
| 113 | #define GCC_QUPV3_WRAP0_S7_CLK 100 | ||
| 114 | #define GCC_QUPV3_WRAP0_S7_CLK_SRC 101 | ||
| 115 | #define GCC_QUPV3_WRAP1_CORE_2X_CLK 102 | ||
| 116 | #define GCC_QUPV3_WRAP1_CORE_CLK 103 | ||
| 117 | #define GCC_QUPV3_WRAP1_S0_CLK 104 | ||
| 118 | #define GCC_QUPV3_WRAP1_S0_CLK_SRC 105 | ||
| 119 | #define GCC_QUPV3_WRAP1_S1_CLK 106 | ||
| 120 | #define GCC_QUPV3_WRAP1_S1_CLK_SRC 107 | ||
| 121 | #define GCC_QUPV3_WRAP1_S2_CLK 108 | ||
| 122 | #define GCC_QUPV3_WRAP1_S2_CLK_SRC 109 | ||
| 123 | #define GCC_QUPV3_WRAP1_S3_CLK 110 | ||
| 124 | #define GCC_QUPV3_WRAP1_S3_CLK_SRC 111 | ||
| 125 | #define GCC_QUPV3_WRAP1_S4_CLK 112 | ||
| 126 | #define GCC_QUPV3_WRAP1_S4_CLK_SRC 113 | ||
| 127 | #define GCC_QUPV3_WRAP1_S5_CLK 114 | ||
| 128 | #define GCC_QUPV3_WRAP1_S5_CLK_SRC 115 | ||
| 129 | #define GCC_QUPV3_WRAP1_S6_CLK 116 | ||
| 130 | #define GCC_QUPV3_WRAP1_S6_CLK_SRC 117 | ||
| 131 | #define GCC_QUPV3_WRAP2_CORE_2X_CLK 118 | ||
| 132 | #define GCC_QUPV3_WRAP2_CORE_CLK 119 | ||
| 133 | #define GCC_QUPV3_WRAP2_S0_CLK 120 | ||
| 134 | #define GCC_QUPV3_WRAP2_S0_CLK_SRC 121 | ||
| 135 | #define GCC_QUPV3_WRAP2_S1_CLK 122 | ||
| 136 | #define GCC_QUPV3_WRAP2_S1_CLK_SRC 123 | ||
| 137 | #define GCC_QUPV3_WRAP2_S2_CLK 124 | ||
| 138 | #define GCC_QUPV3_WRAP2_S2_CLK_SRC 125 | ||
| 139 | #define GCC_QUPV3_WRAP2_S3_CLK 126 | ||
| 140 | #define GCC_QUPV3_WRAP2_S3_CLK_SRC 127 | ||
| 141 | #define GCC_QUPV3_WRAP2_S4_CLK 128 | ||
| 142 | #define GCC_QUPV3_WRAP2_S4_CLK_SRC 129 | ||
| 143 | #define GCC_QUPV3_WRAP2_S5_CLK 130 | ||
| 144 | #define GCC_QUPV3_WRAP2_S5_CLK_SRC 131 | ||
| 145 | #define GCC_QUPV3_WRAP2_S6_CLK 132 | ||
| 146 | #define GCC_QUPV3_WRAP2_S6_CLK_SRC 133 | ||
| 147 | #define GCC_QUPV3_WRAP_0_M_AHB_CLK 134 | ||
| 148 | #define GCC_QUPV3_WRAP_0_S_AHB_CLK 135 | ||
| 149 | #define GCC_QUPV3_WRAP_1_M_AHB_CLK 136 | ||
| 150 | #define GCC_QUPV3_WRAP_1_S_AHB_CLK 137 | ||
| 151 | #define GCC_QUPV3_WRAP_2_M_AHB_CLK 138 | ||
| 152 | #define GCC_QUPV3_WRAP_2_S_AHB_CLK 139 | ||
| 153 | #define GCC_SDCC2_AHB_CLK 140 | ||
| 154 | #define GCC_SDCC2_APPS_CLK 141 | ||
| 155 | #define GCC_SDCC2_APPS_CLK_SRC 142 | ||
| 156 | #define GCC_SDCC2_AT_CLK 143 | ||
| 157 | #define GCC_SDCC4_AHB_CLK 144 | ||
| 158 | #define GCC_SDCC4_APPS_CLK 145 | ||
| 159 | #define GCC_SDCC4_APPS_CLK_SRC 146 | ||
| 160 | #define GCC_SDCC4_AT_CLK 147 | ||
| 161 | #define GCC_SYS_NOC_CPUSS_AHB_CLK 148 | ||
| 162 | #define GCC_UFS_0_CLKREF_EN 149 | ||
| 163 | #define GCC_UFS_PHY_AHB_CLK 150 | ||
| 164 | #define GCC_UFS_PHY_AXI_CLK 151 | ||
| 165 | #define GCC_UFS_PHY_AXI_CLK_SRC 152 | ||
| 166 | #define GCC_UFS_PHY_AXI_HW_CTL_CLK 153 | ||
| 167 | #define GCC_UFS_PHY_ICE_CORE_CLK 154 | ||
| 168 | #define GCC_UFS_PHY_ICE_CORE_CLK_SRC 155 | ||
| 169 | #define GCC_UFS_PHY_ICE_CORE_HW_CTL_CLK 156 | ||
| 170 | #define GCC_UFS_PHY_PHY_AUX_CLK 157 | ||
| 171 | #define GCC_UFS_PHY_PHY_AUX_CLK_SRC 158 | ||
| 172 | #define GCC_UFS_PHY_PHY_AUX_HW_CTL_CLK 159 | ||
| 173 | #define GCC_UFS_PHY_RX_SYMBOL_0_CLK 160 | ||
| 174 | #define GCC_UFS_PHY_RX_SYMBOL_0_CLK_SRC 161 | ||
| 175 | #define GCC_UFS_PHY_RX_SYMBOL_1_CLK 162 | ||
| 176 | #define GCC_UFS_PHY_RX_SYMBOL_1_CLK_SRC 163 | ||
| 177 | #define GCC_UFS_PHY_TX_SYMBOL_0_CLK 164 | ||
| 178 | #define GCC_UFS_PHY_TX_SYMBOL_0_CLK_SRC 165 | ||
| 179 | #define GCC_UFS_PHY_UNIPRO_CORE_CLK 166 | ||
| 180 | #define GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC 167 | ||
| 181 | #define GCC_UFS_PHY_UNIPRO_CORE_HW_CTL_CLK 168 | ||
| 182 | #define GCC_USB30_PRIM_MASTER_CLK 169 | ||
| 183 | #define GCC_USB30_PRIM_MASTER_CLK_SRC 170 | ||
| 184 | #define GCC_USB30_PRIM_MOCK_UTMI_CLK 171 | ||
| 185 | #define GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC 172 | ||
| 186 | #define GCC_USB30_PRIM_MOCK_UTMI_POSTDIV_CLK_SRC 173 | ||
| 187 | #define GCC_USB30_PRIM_SLEEP_CLK 174 | ||
| 188 | #define GCC_USB3_0_CLKREF_EN 175 | ||
| 189 | #define GCC_USB3_PRIM_PHY_AUX_CLK 176 | ||
| 190 | #define GCC_USB3_PRIM_PHY_AUX_CLK_SRC 177 | ||
| 191 | #define GCC_USB3_PRIM_PHY_COM_AUX_CLK 178 | ||
| 192 | #define GCC_USB3_PRIM_PHY_PIPE_CLK 179 | ||
| 193 | #define GCC_USB3_PRIM_PHY_PIPE_CLK_SRC 180 | ||
| 194 | #define GCC_VIDEO_AHB_CLK 181 | ||
| 195 | #define GCC_VIDEO_AXI0_CLK 182 | ||
| 196 | #define GCC_VIDEO_AXI1_CLK 183 | ||
| 197 | #define GCC_VIDEO_XO_CLK 184 | ||
| 198 | |||
| 199 | /* GCC resets */ | ||
| 200 | #define GCC_CAMERA_BCR 0 | ||
| 201 | #define GCC_DISPLAY_BCR 1 | ||
| 202 | #define GCC_GPU_BCR 2 | ||
| 203 | #define GCC_MMSS_BCR 3 | ||
| 204 | #define GCC_PCIE_0_BCR 4 | ||
| 205 | #define GCC_PCIE_0_LINK_DOWN_BCR 5 | ||
| 206 | #define GCC_PCIE_0_NOCSR_COM_PHY_BCR 6 | ||
| 207 | #define GCC_PCIE_0_PHY_BCR 7 | ||
| 208 | #define GCC_PCIE_0_PHY_NOCSR_COM_PHY_BCR 8 | ||
| 209 | #define GCC_PCIE_1_BCR 9 | ||
| 210 | #define GCC_PCIE_1_LINK_DOWN_BCR 10 | ||
| 211 | #define GCC_PCIE_1_NOCSR_COM_PHY_BCR 11 | ||
| 212 | #define GCC_PCIE_1_PHY_BCR 12 | ||
| 213 | #define GCC_PCIE_1_PHY_NOCSR_COM_PHY_BCR 13 | ||
| 214 | #define GCC_PCIE_PHY_BCR 14 | ||
| 215 | #define GCC_PCIE_PHY_CFG_AHB_BCR 15 | ||
| 216 | #define GCC_PCIE_PHY_COM_BCR 16 | ||
| 217 | #define GCC_PDM_BCR 17 | ||
| 218 | #define GCC_QUPV3_WRAPPER_0_BCR 18 | ||
| 219 | #define GCC_QUPV3_WRAPPER_1_BCR 19 | ||
| 220 | #define GCC_QUPV3_WRAPPER_2_BCR 20 | ||
| 221 | #define GCC_QUSB2PHY_PRIM_BCR 21 | ||
| 222 | #define GCC_QUSB2PHY_SEC_BCR 22 | ||
| 223 | #define GCC_SDCC2_BCR 23 | ||
| 224 | #define GCC_SDCC4_BCR 24 | ||
| 225 | #define GCC_UFS_PHY_BCR 25 | ||
| 226 | #define GCC_USB30_PRIM_BCR 26 | ||
| 227 | #define GCC_USB3_DP_PHY_PRIM_BCR 27 | ||
| 228 | #define GCC_USB3_DP_PHY_SEC_BCR 28 | ||
| 229 | #define GCC_USB3_PHY_PRIM_BCR 29 | ||
| 230 | #define GCC_USB3_PHY_SEC_BCR 30 | ||
| 231 | #define GCC_USB3PHY_PHY_PRIM_BCR 31 | ||
| 232 | #define GCC_USB3PHY_PHY_SEC_BCR 32 | ||
| 233 | #define GCC_USB_PHY_CFG_AHB2PHY_BCR 33 | ||
| 234 | #define GCC_VIDEO_AXI0_CLK_ARES 34 | ||
| 235 | #define GCC_VIDEO_AXI1_CLK_ARES 35 | ||
| 236 | #define GCC_VIDEO_BCR 36 | ||
| 237 | |||
| 238 | /* GCC power domains */ | ||
| 239 | #define PCIE_0_GDSC 0 | ||
| 240 | #define PCIE_1_GDSC 1 | ||
| 241 | #define UFS_PHY_GDSC 2 | ||
| 242 | #define USB30_PRIM_GDSC 3 | ||
| 243 | |||
| 244 | #endif | ||
| @@ -113,7 +113,7 @@ · 112 unmodified lines | |||
| 113 | #define CLK_USB_OHCI0 91 | 113 | #define CLK_USB_OHCI0 91 |
| 114 | 114 | ||
| 115 | #define CLK_USB_OHCI1 93 | 115 | #define CLK_USB_OHCI1 93 |
| 116 | 116 | #define CLK_DRAM 94 | |
| 117 | #define CLK_DRAM_VE 95 | 117 | #define CLK_DRAM_VE 95 |
| 118 | #define CLK_DRAM_CSI 96 | 118 | #define CLK_DRAM_CSI 96 |
| 119 | #define CLK_DRAM_DEINTERLACE 97 | 119 | #define CLK_DRAM_DEINTERLACE 97 |
| @@ -126,7 +126,7 @@ · 125 unmodified lines | |||
| 126 | #define CLK_USB_OHCI1 93 | 126 | #define CLK_USB_OHCI1 93 |
| 127 | #define CLK_USB_OHCI2 94 | 127 | #define CLK_USB_OHCI2 94 |
| 128 | #define CLK_USB_OHCI3 95 | 128 | #define CLK_USB_OHCI3 95 |
| 129 | 129 | #define CLK_DRAM 96 | |
| 130 | #define CLK_DRAM_VE 97 | 130 | #define CLK_DRAM_VE 97 |
| 131 | #define CLK_DRAM_CSI 98 | 131 | #define CLK_DRAM_CSI 98 |
| 132 | #define CLK_DRAM_DEINTERLACE 99 | 132 | #define CLK_DRAM_DEINTERLACE 99 |
| @@ -4,11 +4,31 @@ · 3 unmodified lines | |||
| 4 | #ifndef DT_BINDINGS_CLOCK_TEGRA234_CLOCK_H | 4 | #ifndef DT_BINDINGS_CLOCK_TEGRA234_CLOCK_H |
| 5 | #define DT_BINDINGS_CLOCK_TEGRA234_CLOCK_H | 5 | #define DT_BINDINGS_CLOCK_TEGRA234_CLOCK_H |
| 6 | 6 | ||
| 7 | /** | ||
| 8 | * @file | ||
| 9 | * @defgroup bpmp_clock_ids Clock ID's | ||
| 10 | * @{ | ||
| 11 | */ | ||
| 12 | /** | ||
| 13 | * @brief controls the EMC clock frequency. | ||
| 14 | * @details Doing a clk_set_rate on this clock will select the | ||
| 15 | * appropriate clock source, program the source rate and execute a | ||
| 16 | * specific sequence to switch to the new clock source for both memory | ||
| 17 | * controllers. This can be used to control the balance between memory | ||
| 18 | * throughput and memory controller power. | ||
| 19 | */ | ||
| 20 | #define TEGRA234_CLK_EMC 31U | ||
| 7 | /** @brief output of gate CLK_ENB_FUSE */ | 21 | /** @brief output of gate CLK_ENB_FUSE */ |
| 8 | #define TEGRA234_CLK_FUSE 40 | 22 | #define TEGRA234_CLK_FUSE 40U |
| 9 | /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC4 */ | 23 | /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC4 */ |
| 10 | #define TEGRA234_CLK_SDMMC4 123 | 24 | #define TEGRA234_CLK_SDMMC4 123U |
| 11 | /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_UARTA */ | 25 | /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_UARTA */ |
| 12 | #define TEGRA234_CLK_UARTA 155 | 26 | #define TEGRA234_CLK_UARTA 155U |
| 27 | /** @brief CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC_LEGACY_TM switch divider output */ | ||
| 28 | #define TEGRA234_CLK_SDMMC_LEGACY_TM 219U | ||
| 29 | /** @brief PLL controlled by CLK_RST_CONTROLLER_PLLC4_BASE */ | ||
| 30 | #define TEGRA234_CLK_PLLC4 237U | ||
| 31 | /** @brief 32K input clock provided by PMIC */ | ||
| 32 | #define TEGRA234_CLK_CLK_32K 289U | ||
| 13 | 33 | ||
| 14 | #endif | 34 | #endif |
| @@ -0,0 +1,32 @@ | |||
| 1 | /* SPDX-License-Identifier: (GPL-2.0 OR MIT) */ | ||
| 2 | |||
| 3 | #ifndef DT_BINDINGS_MEMORY_TEGRA234_MC_H | ||
| 4 | #define DT_BINDINGS_MEMORY_TEGRA234_MC_H | ||
| 5 | |||
| 6 | /* special clients */ | ||
| 7 | #define TEGRA234_SID_INVALID 0x00 | ||
| 8 | #define TEGRA234_SID_PASSTHROUGH 0x7f | ||
| 9 | |||
| 10 | |||
| 11 | /* NISO1 stream IDs */ | ||
| 12 | #define TEGRA234_SID_SDMMC4 0x02 | ||
| 13 | #define TEGRA234_SID_BPMP 0x10 | ||
| 14 | |||
| 15 | /* | ||
| 16 | * memory client IDs | ||
| 17 | */ | ||
| 18 | |||
| 19 | /* sdmmcd memory read client */ | ||
| 20 | #define TEGRA234_MEMORY_CLIENT_SDMMCRAB 0x63 | ||
| 21 | /* sdmmcd memory write client */ | ||
| 22 | #define TEGRA234_MEMORY_CLIENT_SDMMCWAB 0x67 | ||
| 23 | /* BPMP read client */ | ||
| 24 | #define TEGRA234_MEMORY_CLIENT_BPMPR 0x93 | ||
| 25 | /* BPMP write client */ | ||
| 26 | #define TEGRA234_MEMORY_CLIENT_BPMPW 0x94 | ||
| 27 | /* BPMPDMA read client */ | ||
| 28 | #define TEGRA234_MEMORY_CLIENT_BPMPDMAR 0x95 | ||
| 29 | /* BPMPDMA write client */ | ||
| 30 | #define TEGRA234_MEMORY_CLIENT_BPMPDMAW 0x96 | ||
| 31 | |||
| 32 | #endif | ||
| @@ -38,4 +38,7 @@ · 37 unmodified lines | |||
| 38 | #define AM64X_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode)) | 38 | #define AM64X_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode)) |
| 39 | #define AM64X_MCU_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode)) | 39 | #define AM64X_MCU_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode)) |
| 40 | 40 | ||
| 41 | #define J721S2_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode)) | ||
| 42 | #define J721S2_WKUP_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode)) | ||
| 43 | |||
| 41 | #endif | 44 | #endif |
| @@ -36,7 +36,10 @@ · 35 unmodified lines | |||
| 36 | #define EXYNOS5260_PIN_DRV_LV4 2 | 36 | #define EXYNOS5260_PIN_DRV_LV4 2 |
| 37 | #define EXYNOS5260_PIN_DRV_LV6 3 | 37 | #define EXYNOS5260_PIN_DRV_LV6 3 |
| 38 | 38 | ||
| 39 | /* Drive strengths for Exynos5410, Exynos542x and Exynos5800 */ | 39 | /* |
| 40 | * Drive strengths for Exynos5410, Exynos542x, Exynos5800 and Exynos850 (except | ||
| 41 | * GPIO_HSI block) | ||
| 42 | */ | ||
| 40 | #define EXYNOS5420_PIN_DRV_LV1 0 | 43 | #define EXYNOS5420_PIN_DRV_LV1 0 |
| 41 | #define EXYNOS5420_PIN_DRV_LV2 1 | 44 | #define EXYNOS5420_PIN_DRV_LV2 1 |
| 42 | #define EXYNOS5420_PIN_DRV_LV3 2 | 45 | #define EXYNOS5420_PIN_DRV_LV3 2 |
| @@ -56,6 +59,14 @@ · 13 unmodified lines | |||
| 56 | #define EXYNOS5433_PIN_DRV_SLOW_SR5 0xc | 59 | #define EXYNOS5433_PIN_DRV_SLOW_SR5 0xc |
| 57 | #define EXYNOS5433_PIN_DRV_SLOW_SR6 0xf | 60 | #define EXYNOS5433_PIN_DRV_SLOW_SR6 0xf |
| 58 | 61 | ||
| 62 | /* Drive strengths for Exynos850 GPIO_HSI block */ | ||
| 63 | #define EXYNOS850_HSI_PIN_DRV_LV1 0 /* 1x */ | ||
| 64 | #define EXYNOS850_HSI_PIN_DRV_LV1_5 1 /* 1.5x */ | ||
| 65 | #define EXYNOS850_HSI_PIN_DRV_LV2 2 /* 2x */ | ||
| 66 | #define EXYNOS850_HSI_PIN_DRV_LV2_5 3 /* 2.5x */ | ||
| 67 | #define EXYNOS850_HSI_PIN_DRV_LV3 4 /* 3x */ | ||
| 68 | #define EXYNOS850_HSI_PIN_DRV_LV4 5 /* 4x */ | ||
| 69 | |||
| 59 | #define EXYNOS_PIN_FUNC_INPUT 0 | 70 | #define EXYNOS_PIN_FUNC_INPUT 0 |
| 60 | #define EXYNOS_PIN_FUNC_OUTPUT 1 | 71 | #define EXYNOS_PIN_FUNC_OUTPUT 1 |
| 61 | #define EXYNOS_PIN_FUNC_2 2 | 72 | #define EXYNOS_PIN_FUNC_2 2 |
| @@ -0,0 +1,26 @@ | |||
| 1 | /* SPDX-License-Identifier: (GPL-2.0 OR MIT) */ | ||
| 2 | /* | ||
| 3 | * Copyright 2021 NXP | ||
| 4 | */ | ||
| 5 | |||
| 6 | #ifndef __DT_BINDINGS_IMX8ULP_POWER_H__ | ||
| 7 | #define __DT_BINDINGS_IMX8ULP_POWER_H__ | ||
| 8 | |||
| 9 | #define IMX8ULP_PD_DMA1 0 | ||
| 10 | #define IMX8ULP_PD_FLEXSPI2 1 | ||
| 11 | #define IMX8ULP_PD_USB0 2 | ||
| 12 | #define IMX8ULP_PD_USDHC0 3 | ||
| 13 | #define IMX8ULP_PD_USDHC1 4 | ||
| 14 | #define IMX8ULP_PD_USDHC2_USB1 5 | ||
| 15 | #define IMX8ULP_PD_DCNANO 6 | ||
| 16 | #define IMX8ULP_PD_EPDC 7 | ||
| 17 | #define IMX8ULP_PD_DMA2 8 | ||
| 18 | #define IMX8ULP_PD_GPU2D 9 | ||
| 19 | #define IMX8ULP_PD_GPU3D 10 | ||
| 20 | #define IMX8ULP_PD_HIFI4 11 | ||
| 21 | #define IMX8ULP_PD_ISI 12 | ||
| 22 | #define IMX8ULP_PD_MIPI_CSI 13 | ||
| 23 | #define IMX8ULP_PD_MIPI_DSI 14 | ||
| 24 | #define IMX8ULP_PD_PXP 15 | ||
| 25 | |||
| 26 | #endif | ||
| @@ -4,7 +4,15 @@ · 3 unmodified lines | |||
| 4 | #ifndef DT_BINDINGS_RESET_TEGRA234_RESET_H | 4 | #ifndef DT_BINDINGS_RESET_TEGRA234_RESET_H |
| 5 | #define DT_BINDINGS_RESET_TEGRA234_RESET_H | 5 | #define DT_BINDINGS_RESET_TEGRA234_RESET_H |
| 6 | 6 | ||
| 7 | #define TEGRA234_RESET_SDMMC4 85 | 7 | /** |
| 8 | #define TEGRA234_RESET_UARTA 100 | 8 | * @file |
| 9 | * @defgroup bpmp_reset_ids Reset ID's | ||
| 10 | * @brief Identifiers for Resets controllable by firmware | ||
| 11 | * @{ | ||
| 12 | */ | ||
| 13 | #define TEGRA234_RESET_SDMMC4 85U | ||
| 14 | #define TEGRA234_RESET_UARTA 100U | ||
| 15 | |||
| 16 | /** @} */ | ||
| 9 | 17 | ||
| 10 | #endif | 18 | #endif |