History

Merge branch 'i2c/for-4.3' of git://git.kernel.org/pub/scm/linux/kernel/git/wsa/linux

Pull i2c updates from Wolfram Sang: "Features: - new drivers: Renesas EMEV2, register based MUX, NXP LPC2xxx - core: scans DT and assigns wakeup interrupts. no driver changes needed. - core: some refcouting issues fixed and better API for that - core: new helper function for best effort block read emulation - slave framework: proper DT bindings and userspace instantiation - some bigger work for xiic, pxa, omap drivers .. and quite a number of smaller driver fixes, cleanups, improvements" * 'i2c/for-4.3' of git://git.kernel.org/pub/scm/linux/kernel/git/wsa/linux: (65 commits) i2c: mux: reg Change ioread endianness for readback i2c: mux: reg: fix compilation warnings i2c: mux: reg: simplify register size checking i2c: muxes: fix leaked i2c adapter device node references i2c: allow specifying separate wakeup interrupt in device tree of/irq: export of_get_irq_byname() i2c: xgene-slimpro: dma_mapping_error() doesn't return an error code i2c: Replace I2C_CROS_EC_TUNNEL dependency eeprom: at24: use i2c_smbus_read_i2c_block_data_or_emulated i2c: core: Add support for best effort block read emulation i2c: lpc2k: add driver i2c: mux: Add register-based mux i2c-mux-reg i2c: dt: describe generic bindings i2c: slave: print warning if slave flag not set i2c: support 10 bit and slave addresses in sysfs 'new_device' i2c: take address space into account when checking for used addresses i2c: apply DT flags when probing i2c: make address check indpendent from client struct i2c: rename address check functions i2c: apply address offset for slaves, too ...

Linus Torvalds committed 11 years ago

Commit acceba52 parents c191761 5a7388246 files · +2189 −524Browse files

Unified · Split

46 files
  1. Documentation/devicetree/bindings/hwmon/ina209.txt +0 −0
  2. Documentation/devicetree/bindings/hwmon/ina2xx.txt +0 −0
  3. Documentation/devicetree/bindings/hwmon/max6697.txt +0 −0
  4. Documentation/devicetree/bindings/i2c/i2c-cadence.txt +5 −1
  5. Documentation/devicetree/bindings/i2c/i2c-emev2.txt +22 −0
  6. Documentation/devicetree/bindings/i2c/i2c-lpc2k.txt +33 −0
  7. Documentation/devicetree/bindings/i2c/i2c-mux-reg.txt +74 −0
  8. Documentation/devicetree/bindings/i2c/i2c.txt +45 −0
  9. Documentation/devicetree/bindings/i2c/trivial-devices.txt +2 −0
  10. Documentation/devicetree/bindings/rtc/ti,bq32k.txt +0 −0
  11. Documentation/i2c/busses/i2c-parport +1 −0
  12. Documentation/i2c/slave-interface +6 −3
  13. Documentation/i2c/ten-bit-addresses +4 −0
  14. drivers/clk/shmobile/clk-emev2.c +6 −0
  15. drivers/i2c/busses/Kconfig +18 −1
  16. drivers/i2c/busses/Makefile +2 −0
  17. drivers/i2c/busses/i2c-cadence.c +58 −11
  18. drivers/i2c/busses/i2c-designware-core.c +1 −2
  19. drivers/i2c/busses/i2c-designware-pcidrv.c +2 −2
  20. drivers/i2c/busses/i2c-emev2.c +332 −0
  21. drivers/i2c/busses/i2c-lpc2k.c +513 −0
  22. drivers/i2c/busses/i2c-mt65xx.c +17 −4
  23. drivers/i2c/busses/i2c-omap.c +299 −301
  24. drivers/i2c/busses/i2c-parport.c +13 −12
  25. drivers/i2c/busses/i2c-parport.h +8 −0
  26. drivers/i2c/busses/i2c-pxa.c +50 −62
  27. drivers/i2c/busses/i2c-tegra.c +50 −2
  28. drivers/i2c/busses/i2c-viperboard.c +5 −5
  29. drivers/i2c/busses/i2c-xgene-slimpro.c +4 −4
  30. drivers/i2c/busses/i2c-xiic.c +34 −40
  31. drivers/i2c/i2c-core.c +194 −35
  32. drivers/i2c/i2c-slave-eeprom.c +0 −1
  33. drivers/i2c/muxes/Kconfig +11 −0
  34. drivers/i2c/muxes/Makefile +1 −0
  35. drivers/i2c/muxes/i2c-arb-gpio-challenge.c +2 −1
  36. drivers/i2c/muxes/i2c-mux-gpio.c +1 −0
  37. drivers/i2c/muxes/i2c-mux-pca9541.c +0 −1
  38. drivers/i2c/muxes/i2c-mux-pca954x.c +0 −1
  39. drivers/i2c/muxes/i2c-mux-pinctrl.c +1 −0
  40. drivers/i2c/muxes/i2c-mux-reg.c +290 −0
  41. drivers/misc/eeprom/at24.c +6 −31
  42. drivers/misc/eeprom/max6875.c +1 −0
  43. drivers/of/irq.c +1 −0
  44. include/dt-bindings/i2c/i2c.h +18 −0
  45. include/linux/i2c.h +15 −4
  46. include/linux/platform_data/i2c-mux-reg.h +44 −0
Documentation/devicetree/bindings/hwmon/ina209.txtrenamed from Documentation/devicetree/bindings/i2c/ina209.txt+0−0

File renamed without changes.

Documentation/devicetree/bindings/hwmon/ina2xx.txtrenamed from Documentation/devicetree/bindings/i2c/ina2xx.txt+0−0

File renamed without changes.

Documentation/devicetree/bindings/hwmon/max6697.txtrenamed from Documentation/devicetree/bindings/i2c/max6697.txt+0−0

File renamed without changes.

Documentation/devicetree/bindings/i2c/i2c-cadence.txt+5−1
@@ -2,7 +2,11 @@ Binding for the Cadence I2C controller · 1 unmodified line
22
33 Required properties:
44 - reg: Physical base address and size of the controller's register area.
5− - compatible: Compatibility string. Must be 'cdns,i2c-r1p10'.
5+ - compatible: Should contain one of:
6+ * "cdns,i2c-r1p10"
7+ Note: Use this when cadence i2c controller version 1.0 is used.
8+ * "cdns,i2c-r1p14"
9+ Note: Use this when cadence i2c controller version 1.4 is used.
610 - clocks: Input clock specifier. Refer to common clock bindings.
711 - interrupts: Interrupt specifier. Refer to interrupt bindings.
812 - #address-cells: Should be 1.
Documentation/devicetree/bindings/i2c/i2c-emev2.txt+22−0
@@ -0,0 +1,22 @@
1+Device tree configuration for Renesas EMEV2 IIC controller
2+
3+Required properties:
4+- compatible : "renesas,iic-emev2"
5+- reg : address start and address range size of device
6+- interrupts : specifier for the IIC controller interrupt
7+- clocks : phandle to the IP core SCLK
8+- clock-names : must be "sclk"
9+- #address-cells : should be <1>
10+- #size-cells : should be <0>
11+
12+Example:
13+
14+ iic0: i2c@e0070000 {
15+ #address-cells = <1>;
16+ #size-cells = <0>;
17+ compatible = "renesas,iic-emev2";
18+ reg = <0xe0070000 0x28>;
19+ interrupts = <0 32 IRQ_TYPE_EDGE_RISING>;
20+ clocks = <&iic0_sclk>;
21+ clock-names = "sclk";
22+ };
Documentation/devicetree/bindings/i2c/i2c-lpc2k.txt+33−0
@@ -0,0 +1,33 @@
1+NXP I2C controller for LPC2xxx/178x/18xx/43xx
2+
3+Required properties:
4+ - compatible: must be "nxp,lpc1788-i2c"
5+ - reg: physical address and length of the device registers
6+ - interrupts: a single interrupt specifier
7+ - clocks: clock for the device
8+ - #address-cells: should be <1>
9+ - #size-cells: should be <0>
10+
11+Optional properties:
12+- clock-frequency: the desired I2C bus clock frequency in Hz; in
13+ absence of this property the default value is used (100 kHz).
14+
15+Example:
16+i2c0: i2c@400a1000 {
17+ compatible = "nxp,lpc1788-i2c";
18+ reg = <0x400a1000 0x1000>;
19+ interrupts = <18>;
20+ clocks = <&ccu1 CLK_APB1_I2C0>;
21+ #address-cells = <1>;
22+ #size-cells = <0>;
23+};
24+
25+&i2c0 {
26+ clock-frequency = <400000>;
27+
28+ lm75@48 {
29+ compatible = "nxp,lm75";
30+ reg = <0x48>;
31+ };
32+};
33+
Documentation/devicetree/bindings/i2c/i2c-mux-reg.txt+74−0
@@ -0,0 +1,74 @@
1+Register-based I2C Bus Mux
2+
3+This binding describes an I2C bus multiplexer that uses a single register
4+to route the I2C signals.
5+
6+Required properties:
7+- compatible: i2c-mux-reg
8+- i2c-parent: The phandle of the I2C bus that this multiplexer's master-side
9+ port is connected to.
10+* Standard I2C mux properties. See mux.txt in this directory.
11+* I2C child bus nodes. See mux.txt in this directory.
12+
13+Optional properties:
14+- reg: this pair of <offset size> specifies the register to control the mux.
15+ The <offset size> depends on its parent node. It can be any memory-mapped
16+ address. The size must be either 1, 2, or 4 bytes. If reg is omitted, the
17+ resource of this device will be used.
18+- little-endian: The existence indicates the register is in little endian.
19+- big-endian: The existence indicates the register is in big endian.
20+ If both little-endian and big-endian are omitted, the endianness of the
21+ CPU will be used.
22+- write-only: The existence indicates the register is write-only.
23+- idle-state: value to set the muxer to when idle. When no value is
24+ given, it defaults to the last value used.
25+
26+Whenever an access is made to a device on a child bus, the value set
27+in the revelant node's reg property will be output to the register.
28+
29+If an idle state is defined, using the idle-state (optional) property,
30+whenever an access is not being made to a device on a child bus, the
31+register will be set according to the idle value.
32+
33+If an idle state is not defined, the most recently used value will be
34+left programmed into the register.
35+
36+Example of a mux on PCIe card, the host is a powerpc SoC (big endian):
37+
38+ i2c-mux {
39+ /* the <offset size> depends on the address translation
40+ * of the parent device. If omitted, device resource
41+ * will be used instead. The size is to determine
42+ * whether iowrite32, iowrite16, or iowrite8 will be used.
43+ */
44+ reg = <0x6028 0x4>;
45+ little-endian; /* little endian register on PCIe */
46+ compatible = "i2c-mux-reg";
47+ #address-cells = <1>;
48+ #size-cells = <0>;
49+ i2c-parent = <&i2c1>;
50+ i2c@0 {
51+ reg = <0>;
52+ #address-cells = <1>;
53+ #size-cells = <0>;
54+
55+ si5338: clock-generator@70 {
56+ compatible = "silabs,si5338";
57+ reg = <0x70>;
58+ /* other stuff */
59+ };
60+ };
61+
62+ i2c@1 {
63+ /* data is written using iowrite32 */
64+ reg = <1>;
65+ #address-cells = <1>;
66+ #size-cells = <0>;
67+
68+ si5338: clock-generator@70 {
69+ compatible = "silabs,si5338";
70+ reg = <0x70>;
71+ /* other stuff */
72+ };
73+ };
74+ };
Documentation/devicetree/bindings/i2c/i2c.txt+45−0
@@ -0,0 +1,45 @@
1+Generic device tree bindings for I2C busses
2+===========================================
3+
4+This document describes generic bindings which can be used to describe I2C
5+busses in a device tree.
6+
7+Required properties
8+-------------------
9+
10+- #address-cells - should be <1>. Read more about addresses below.
11+- #size-cells - should be <0>.
12+- compatible - name of I2C bus controller following generic names
13+ recommended practice.
14+
15+For other required properties e.g. to describe register sets,
16+clocks, etc. check the binding documentation of the specific driver.
17+
18+The cells properties above define that an address of children of an I2C bus
19+are described by a single value. This is usually a 7 bit address. However,
20+flags can be attached to the address. I2C_TEN_BIT_ADDRESS is used to mark a 10
21+bit address. It is needed to avoid the ambiguity between e.g. a 7 bit address
22+of 0x50 and a 10 bit address of 0x050 which, in theory, can be on the same bus.
23+Another flag is I2C_OWN_SLAVE_ADDRESS to mark addresses on which we listen to
24+be devices ourselves.
25+
26+Optional properties
27+-------------------
28+
29+These properties may not be supported by all drivers. However, if a driver
30+wants to support one of the below features, it should adapt the bindings below.
31+
32+- clock-frequency - frequency of bus clock in Hz.
33+- wakeup-source - device can be used as a wakeup source.
34+
35+- interrupts - interrupts used by the device.
36+- interrupt-names - "irq" and "wakeup" names are recognized by I2C core,
37+ other names are left to individual drivers.
38+
39+Binding may contain optional "interrupts" property, describing interrupts
40+used by the device. I2C core will assign "irq" interrupt (or the very first
41+interrupt if not using interrupt names) as primary interrupt for the slave.
42+
43+Also, if device is marked as a wakeup source, I2C core will set up "wakeup"
44+interrupt for the device. If "wakeup" interrupt name is not present in the
45+binding, then primary interrupt will be used as wakeup interrupt.
Documentation/devicetree/bindings/i2c/trivial-devices.txt+2−0
@@ -95,6 +95,8 @@ stm,m41t00 Serial Access TIMEKEEPER · 94 unmodified lines
9595 stm,m41t62 Serial real-time clock (RTC) with alarm
9696 stm,m41t80 M41T80 - SERIAL ACCESS RTC WITH ALARMS
9797 taos,tsl2550 Ambient Light Sensor with SMBUS/Two Wire Serial Interface
98+ti,ads7828 8-Channels, 12-bit ADC
99+ti,ads7830 8-Channels, 8-bit ADC
98100 ti,tsc2003 I2C Touch-Screen Controller
99101 ti,tmp102 Low Power Digital Temperature Sensor with SMBUS/Two Wire Serial Interface
100102 ti,tmp103 Low Power Digital Temperature Sensor with SMBUS/Two Wire Serial Interface
Documentation/devicetree/bindings/rtc/ti,bq32k.txtrenamed from Documentation/devicetree/bindings/i2c/ti,bq32k.txt+0−0

File renamed without changes.

Documentation/i2c/busses/i2c-parport+1−0
@@ -20,6 +20,7 @@ It currently supports the following devices: · 19 unmodified lines
2020 * (type=5) Analog Devices evaluation boards: ADM1025, ADM1030, ADM1031
2121 * (type=6) Barco LPT->DVI (K5800236) adapter
2222 * (type=7) One For All JP1 parallel port adapter
23+ * (type=8) VCT-jig
2324
2425 These devices use different pinout configurations, so you have to tell
2526 the driver what you have, using the type module parameter. There is no
Documentation/i2c/slave-interface+6−3
@@ -31,10 +31,13 @@ User manual · 30 unmodified lines
3131 ===========
3232
3333 I2C slave backends behave like standard I2C clients. So, you can instantiate
34−them as described in the document 'instantiating-devices'. A quick example for
35−instantiating the slave-eeprom driver from userspace at address 0x64 on bus 1:
34+them as described in the document 'instantiating-devices'. The only difference
35+is that i2c slave backends have their own address space. So, you have to add
36+0x1000 to the address you would originally request. An example for
37+instantiating the slave-eeprom driver from userspace at the 7 bit address 0x64
38+on bus 1:
3639
37− # echo slave-24c02 0x64 > /sys/bus/i2c/devices/i2c-1/new_device
40+ # echo slave-24c02 0x1064 > /sys/bus/i2c/devices/i2c-1/new_device
3841
3942 Each backend should come with separate documentation to describe its specific
4043 behaviour and setup.
Documentation/i2c/ten-bit-addresses+4−0
@@ -2,6 +2,10 @@ The I2C protocol knows about two kinds of device addresses: normal 7 bit · 1 unmodified line
22 addresses, and an extended set of 10 bit addresses. The sets of addresses
33 do not intersect: the 7 bit address 0x10 is not the same as the 10 bit
44 address 0x10 (though a single device could respond to both of them).
5+To avoid ambiguity, the user sees 10 bit addresses mapped to a different
6+address space, namely 0xa000-0xa3ff. The leading 0xa (= 10) represents the
7+10 bit mode. This is used for creating device names in sysfs. It is also
8+needed when instantiating 10 bit devices via the new_device file in sysfs.
59
610 I2C messages to and from 10-bit address devices have a different format.
711 See the I2C specification for the details.
drivers/clk/shmobile/clk-emev2.c+6−0
@@ -28,6 +28,8 @@ · 27 unmodified lines
2828 #define USIBU1_RSTCTRL 0x0ac
2929 #define USIBU2_RSTCTRL 0x0b0
3030 #define USIBU3_RSTCTRL 0x0b4
31+#define IIC0_RSTCTRL 0x0dc
32+#define IIC1_RSTCTRL 0x0e0
3133 #define STI_RSTCTRL 0x124
3234 #define STI_CLKSEL 0x688
3335
@@ -66,6 +68,10 @@ static void __init emev2_smu_init(void) · 32 unmodified lines
6668 emev2_smu_write(2, USIBU1_RSTCTRL);
6769 emev2_smu_write(2, USIBU2_RSTCTRL);
6870 emev2_smu_write(2, USIBU3_RSTCTRL);
71+
72+ /* deassert reset for IIC0->IIC1 */
73+ emev2_smu_write(1, IIC0_RSTCTRL);
74+ emev2_smu_write(1, IIC1_RSTCTRL);
6975 }
7076
7177 static void __init emev2_smu_clkdiv_init(struct device_node *np)
drivers/i2c/busses/Kconfig+18−1
@@ -526,6 +526,13 @@ config I2C_EG20T · 525 unmodified lines
526526 ML7213/ML7223/ML7831 is companion chip for Intel Atom E6xx series.
527527 ML7213/ML7223/ML7831 is completely compatible for Intel EG20T PCH.
528528
529+config I2C_EMEV2
530+ tristate "EMMA Mobile series I2C adapter"
531+ depends on HAVE_CLK
532+ help
533+ If you say yes to this option, support will be included for the
534+ I2C interface on the Renesas Electronics EM/EV family of processors.
535+
529536 config I2C_EXYNOS5
530537 tristate "Exynos5 high-speed I2C driver"
531538 depends on ARCH_EXYNOS && OF
@@ -612,6 +619,16 @@ config I2C_KEMPLD · 80 unmodified lines
612619 This driver can also be built as a module. If so, the module
613620 will be called i2c-kempld.
614621
622+config I2C_LPC2K
623+ tristate "I2C bus support for NXP LPC2K/LPC178x/18xx/43xx"
624+ depends on OF && (ARCH_LPC18XX || COMPILE_TEST)
625+ help
626+ This driver supports the I2C interface found several NXP
627+ devices including LPC2xxx, LPC178x/7x and LPC18xx/43xx.
628+
629+ This driver can also be built as a module. If so, the module
630+ will be called i2c-lpc2k.
631+
615632 config I2C_MESON
616633 tristate "Amlogic Meson I2C controller"
617634 depends on ARCH_MESON
@@ -1123,7 +1140,7 @@ config I2C_SIBYTE · 505 unmodified lines
11231140
11241141 config I2C_CROS_EC_TUNNEL
11251142 tristate "ChromeOS EC tunnel I2C bus"
1126− depends on CROS_EC_PROTO
1143+ depends on MFD_CROS_EC
11271144 help
11281145 If you say yes here you get an I2C bus that will tunnel i2c commands
11291146 through to the other side of the ChromeOS EC to the i2c bus
drivers/i2c/busses/Makefile+2−0
@@ -48,6 +48,7 @@ i2c-designware-pci-objs := i2c-designware-pcidrv.o · 47 unmodified lines
4848 obj-$(CONFIG_I2C_DIGICOLOR) += i2c-digicolor.o
4949 obj-$(CONFIG_I2C_EFM32) += i2c-efm32.o
5050 obj-$(CONFIG_I2C_EG20T) += i2c-eg20t.o
51+obj-$(CONFIG_I2C_EMEV2) += i2c-emev2.o
5152 obj-$(CONFIG_I2C_EXYNOS5) += i2c-exynos5.o
5253 obj-$(CONFIG_I2C_GPIO) += i2c-gpio.o
5354 obj-$(CONFIG_I2C_HIGHLANDER) += i2c-highlander.o
@@ -58,6 +59,7 @@ obj-$(CONFIG_I2C_IMX) += i2c-imx.o · 4 unmodified lines
5859 obj-$(CONFIG_I2C_IOP3XX) += i2c-iop3xx.o
5960 obj-$(CONFIG_I2C_JZ4780) += i2c-jz4780.o
6061 obj-$(CONFIG_I2C_KEMPLD) += i2c-kempld.o
62+obj-$(CONFIG_I2C_LPC2K) += i2c-lpc2k.o
6163 obj-$(CONFIG_I2C_MESON) += i2c-meson.o
6264 obj-$(CONFIG_I2C_MPC) += i2c-mpc.o
6365 obj-$(CONFIG_I2C_MT65XX) += i2c-mt65xx.o
drivers/i2c/busses/i2c-cadence.c+58−11
@@ -17,6 +17,7 @@ · 16 unmodified lines
1717 #include <linux/io.h>
1818 #include <linux/module.h>
1919 #include <linux/platform_device.h>
20+#include <linux/of.h>
2021
2122 /* Register offsets for the I2C device. */
2223 #define CDNS_I2C_CR_OFFSET 0x00 /* Control Register, RW */
@@ -113,6 +114,8 @@ · 90 unmodified lines
113114
114115 #define CDNS_I2C_TIMEOUT_MAX 0xFF
115116
117+#define CDNS_I2C_BROKEN_HOLD_BIT BIT(0)
118+
116119 #define cdns_i2c_readreg(offset) readl_relaxed(id->membase + offset)
117120 #define cdns_i2c_writereg(val, offset) writel_relaxed(val, id->membase + offset)
118121
@@ -135,6 +138,7 @@ · 16 unmodified lines
135138 * @bus_hold_flag: Flag used in repeated start for clearing HOLD bit
136139 * @clk: Pointer to struct clk
137140 * @clk_rate_change_nb: Notifier block for clock rate changes
141+ * @quirks: flag for broken hold bit usage in r1p10
138142 */
139143 struct cdns_i2c {
140144 void __iomem *membase;
@@ -154,6 +158,11 @@ struct cdns_i2c { · 13 unmodified lines
154158 unsigned int bus_hold_flag;
155159 struct clk *clk;
156160 struct notifier_block clk_rate_change_nb;
161+ u32 quirks;
162+};
163+
164+struct cdns_platform_data {
165+ u32 quirks;
157166 };
158167
159168 #define to_cdns_i2c(_nb) container_of(_nb, struct cdns_i2c, \
@@ -172,6 +181,12 @@ static void cdns_i2c_clear_bus_hold(struct cdns_i2c *id) · 12 unmodified lines
172181 cdns_i2c_writereg(reg & ~CDNS_I2C_CR_HOLD, CDNS_I2C_CR_OFFSET);
173182 }
174183
184+static inline bool cdns_is_holdquirk(struct cdns_i2c *id, bool hold_wrkaround)
185+{
186+ return (hold_wrkaround &&
187+ (id->curr_recv_count == CDNS_I2C_FIFO_DEPTH + 1));
188+}
189+
175190 /**
176191 * cdns_i2c_isr - Interrupt handler for the I2C device
177192 * @irq: irq number for the I2C device
@@ -186,6 +201,7 @@ static irqreturn_t cdns_i2c_isr(int irq, void *ptr) · 8 unmodified lines
186201 {
187202 unsigned int isr_status, avail_bytes, updatetx;
188203 unsigned int bytes_to_send;
204+ bool hold_quirk;
189205 struct cdns_i2c *id = ptr;
190206 /* Signal completion only after everything is updated */
191207 int done_flag = 0;
@@ -208,6 +224,8 @@ static irqreturn_t cdns_i2c_isr(int irq, void *ptr) · 16 unmodified lines
208224 if (id->recv_count > id->curr_recv_count)
209225 updatetx = 1;
210226
227+ hold_quirk = (id->quirks & CDNS_I2C_BROKEN_HOLD_BIT) && updatetx;
228+
211229 /* When receiving, handle data interrupt and completion interrupt */
212230 if (id->p_recv_buf &&
213231 ((isr_status & CDNS_I2C_IXR_COMP) ||
@@ -229,8 +247,7 @@ static irqreturn_t cdns_i2c_isr(int irq, void *ptr) · 15 unmodified lines
229247 id->recv_count--;
230248 id->curr_recv_count--;
231249
232− if (updatetx &&
233− (id->curr_recv_count == CDNS_I2C_FIFO_DEPTH + 1))
250+ if (cdns_is_holdquirk(id, hold_quirk))
234251 break;
235252 }
236253
@@ -241,8 +258,7 @@ static irqreturn_t cdns_i2c_isr(int irq, void *ptr) · 4 unmodified lines
241258 * maintain transfer size non-zero while performing a large
242259 * receive operation.
243260 */
244− if (updatetx &&
245− (id->curr_recv_count == CDNS_I2C_FIFO_DEPTH + 1)) {
261+ if (cdns_is_holdquirk(id, hold_quirk)) {
246262 /* wait while fifo is full */
247263 while (cdns_i2c_readreg(CDNS_I2C_XFER_SIZE_OFFSET) !=
248264 (id->curr_recv_count - CDNS_I2C_FIFO_DEPTH))
@@ -264,6 +280,22 @@ static irqreturn_t cdns_i2c_isr(int irq, void *ptr) · 15 unmodified lines
264280 CDNS_I2C_XFER_SIZE_OFFSET);
265281 id->curr_recv_count = id->recv_count;
266282 }
283+ } else if (id->recv_count && !hold_quirk &&
284+ !id->curr_recv_count) {
285+
286+ /* Set the slave address in address register*/
287+ cdns_i2c_writereg(id->p_msg->addr & CDNS_I2C_ADDR_MASK,
288+ CDNS_I2C_ADDR_OFFSET);
289+
290+ if (id->recv_count > CDNS_I2C_TRANSFER_SIZE) {
291+ cdns_i2c_writereg(CDNS_I2C_TRANSFER_SIZE,
292+ CDNS_I2C_XFER_SIZE_OFFSET);
293+ id->curr_recv_count = CDNS_I2C_TRANSFER_SIZE;
294+ } else {
295+ cdns_i2c_writereg(id->recv_count,
296+ CDNS_I2C_XFER_SIZE_OFFSET);
297+ id->curr_recv_count = id->recv_count;
298+ }
267299 }
268300
269301 /* Clear hold (if not repeated start) and signal completion */
@@ -535,11 +567,13 @@ static int cdns_i2c_master_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, · 265 unmodified lines
535567 int ret, count;
536568 u32 reg;
537569 struct cdns_i2c *id = adap->algo_data;
570+ bool hold_quirk;
538571
539572 /* Check if the bus is free */
540573 if (cdns_i2c_readreg(CDNS_I2C_SR_OFFSET) & CDNS_I2C_SR_BA)
541574 return -EAGAIN;
542575
576+ hold_quirk = !!(id->quirks & CDNS_I2C_BROKEN_HOLD_BIT);
543577 /*
544578 * Set the flag to one when multiple messages are to be
545579 * processed with a repeated start.
@@ -552,7 +586,7 @@ static int cdns_i2c_master_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, · 6 unmodified lines
552586 * followed by any other message, an error is returned
553587 * indicating that this sequence is not supported.
554588 */
555− for (count = 0; count < num - 1; count++) {
589+ for (count = 0; (count < num - 1 && hold_quirk); count++) {
556590 if (msgs[count].flags & I2C_M_RD) {
557591 dev_warn(adap->dev.parent,
558592 "Can't do repeated start after a receive message\n");
@@ -815,6 +849,17 @@ static int __maybe_unused cdns_i2c_resume(struct device *_dev) · 256 unmodified lines
815849 static SIMPLE_DEV_PM_OPS(cdns_i2c_dev_pm_ops, cdns_i2c_suspend,
816850 cdns_i2c_resume);
817851
852+static const struct cdns_platform_data r1p10_i2c_def = {
853+ .quirks = CDNS_I2C_BROKEN_HOLD_BIT,
854+};
855+
856+static const struct of_device_id cdns_i2c_of_match[] = {
857+ { .compatible = "cdns,i2c-r1p10", .data = &r1p10_i2c_def },
858+ { .compatible = "cdns,i2c-r1p14",},
859+ { /* end of table */ }
860+};
861+MODULE_DEVICE_TABLE(of, cdns_i2c_of_match);
862+
818863 /**
819864 * cdns_i2c_probe - Platform registration call
820865 * @pdev: Handle to the platform device structure
@@ -830,6 +875,7 @@ static int cdns_i2c_probe(struct platform_device *pdev) · 9 unmodified lines
830875 struct resource *r_mem;
831876 struct cdns_i2c *id;
832877 int ret;
878+ const struct of_device_id *match;
833879
834880 id = devm_kzalloc(&pdev->dev, sizeof(*id), GFP_KERNEL);
835881 if (!id)
@@ -837,6 +883,12 @@ static int cdns_i2c_probe(struct platform_device *pdev) · 1 unmodified line
837883
838884 platform_set_drvdata(pdev, id);
839885
886+ match = of_match_node(cdns_i2c_of_match, pdev->dev.of_node);
887+ if (match && match->data) {
888+ const struct cdns_platform_data *data = match->data;
889+ id->quirks = data->quirks;
890+ }
891+
840892 r_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
841893 id->membase = devm_ioremap_resource(&pdev->dev, r_mem);
842894 if (IS_ERR(id->membase))
@@ -844,6 +896,7 @@ static int cdns_i2c_probe(struct platform_device *pdev) · 1 unmodified line
844896
845897 id->irq = platform_get_irq(pdev, 0);
846898
899+ id->adap.owner = THIS_MODULE;
847900 id->adap.dev.of_node = pdev->dev.of_node;
848901 id->adap.algo = &cdns_i2c_algo;
849902 id->adap.timeout = CDNS_I2C_TIMEOUT;
@@ -935,12 +988,6 @@ static int cdns_i2c_remove(struct platform_device *pdev) · 85 unmodified lines
935988 return 0;
936989 }
937990
938−static const struct of_device_id cdns_i2c_of_match[] = {
939− { .compatible = "cdns,i2c-r1p10", },
940− { /* end of table */ }
941−};
942−MODULE_DEVICE_TABLE(of, cdns_i2c_of_match);
943−
944991 static struct platform_driver cdns_i2c_drv = {
945992 .driver = {
946993 .name = DRIVER_NAME,
drivers/i2c/busses/i2c-designware-core.c+1−2
@@ -777,8 +777,7 @@ irqreturn_t i2c_dw_isr(int this_irq, void *dev_id) · 776 unmodified lines
777777
778778 enabled = dw_readl(dev, DW_IC_ENABLE);
779779 stat = dw_readl(dev, DW_IC_RAW_INTR_STAT);
780− dev_dbg(dev->dev, "%s: %s enabled= 0x%x stat=0x%x\n", __func__,
781− dev->adapter.name, enabled, stat);
780+ dev_dbg(dev->dev, "%s: enabled=%#x stat=%#x\n", __func__, enabled, stat);
782781 if (!enabled || !(stat & ~DW_IC_INTR_ACTIVITY))
783782 return IRQ_NONE;
784783
drivers/i2c/busses/i2c-designware-pcidrv.c+2−2
@@ -260,8 +260,8 @@ static int i2c_dw_pci_probe(struct pci_dev *pdev, · 259 unmodified lines
260260
261261 snprintf(adap->name, sizeof(adap->name), "i2c-designware-pci");
262262
263− r = devm_request_irq(&pdev->dev, pdev->irq, i2c_dw_isr, IRQF_SHARED,
264− adap->name, dev);
263+ r = devm_request_irq(&pdev->dev, pdev->irq, i2c_dw_isr,
264+ IRQF_SHARED | IRQF_COND_SUSPEND, adap->name, dev);
265265 if (r) {
266266 dev_err(&pdev->dev, "failure requesting irq %i\n", dev->irq);
267267 return r;
drivers/i2c/busses/i2c-emev2.c+332−0
@@ -0,0 +1,332 @@
1+/*
2+ * I2C driver for the Renesas EMEV2 SoC
3+ *
4+ * Copyright (C) 2015 Wolfram Sang <wsa@sang-engineering.com>
5+ * Copyright 2013 Codethink Ltd.
6+ * Copyright 2010-2015 Renesas Electronics Corporation
7+ *
8+ * This program is free software; you can redistribute it and/or modify
9+ * it under the terms of the GNU General Public License version 2
10+ * as published by the Free Software Foundation.
11+ */
12+
13+#include <linux/clk.h>
14+#include <linux/completion.h>
15+#include <linux/device.h>
16+#include <linux/i2c.h>
17+#include <linux/init.h>
18+#include <linux/interrupt.h>
19+#include <linux/io.h>
20+#include <linux/kernel.h>
21+#include <linux/module.h>
22+#include <linux/of_device.h>
23+#include <linux/platform_device.h>
24+#include <linux/sched.h>
25+
26+/* I2C Registers */
27+#define I2C_OFS_IICACT0 0x00 /* start */
28+#define I2C_OFS_IIC0 0x04 /* shift */
29+#define I2C_OFS_IICC0 0x08 /* control */
30+#define I2C_OFS_SVA0 0x0c /* slave address */
31+#define I2C_OFS_IICCL0 0x10 /* clock select */
32+#define I2C_OFS_IICX0 0x14 /* extension */
33+#define I2C_OFS_IICS0 0x18 /* status */
34+#define I2C_OFS_IICSE0 0x1c /* status For emulation */
35+#define I2C_OFS_IICF0 0x20 /* IIC flag */
36+
37+/* I2C IICACT0 Masks */
38+#define I2C_BIT_IICE0 0x0001
39+
40+/* I2C IICC0 Masks */
41+#define I2C_BIT_LREL0 0x0040
42+#define I2C_BIT_WREL0 0x0020
43+#define I2C_BIT_SPIE0 0x0010
44+#define I2C_BIT_WTIM0 0x0008
45+#define I2C_BIT_ACKE0 0x0004
46+#define I2C_BIT_STT0 0x0002
47+#define I2C_BIT_SPT0 0x0001
48+
49+/* I2C IICCL0 Masks */
50+#define I2C_BIT_SMC0 0x0008
51+#define I2C_BIT_DFC0 0x0004
52+
53+/* I2C IICSE0 Masks */
54+#define I2C_BIT_MSTS0 0x0080
55+#define I2C_BIT_ALD0 0x0040
56+#define I2C_BIT_EXC0 0x0020
57+#define I2C_BIT_COI0 0x0010
58+#define I2C_BIT_TRC0 0x0008
59+#define I2C_BIT_ACKD0 0x0004
60+#define I2C_BIT_STD0 0x0002
61+#define I2C_BIT_SPD0 0x0001
62+
63+/* I2C IICF0 Masks */
64+#define I2C_BIT_STCF 0x0080
65+#define I2C_BIT_IICBSY 0x0040
66+#define I2C_BIT_STCEN 0x0002
67+#define I2C_BIT_IICRSV 0x0001
68+
69+struct em_i2c_device {
70+ void __iomem *base;
71+ struct i2c_adapter adap;
72+ struct completion msg_done;
73+ struct clk *sclk;
74+};
75+
76+static inline void em_clear_set_bit(struct em_i2c_device *priv, u8 clear, u8 set, u8 reg)
77+{
78+ writeb((readb(priv->base + reg) & ~clear) | set, priv->base + reg);
79+}
80+
81+static int em_i2c_wait_for_event(struct em_i2c_device *priv)
82+{
83+ unsigned long time_left;
84+ int status;
85+
86+ reinit_completion(&priv->msg_done);
87+
88+ time_left = wait_for_completion_timeout(&priv->msg_done, priv->adap.timeout);
89+
90+ if (!time_left)
91+ return -ETIMEDOUT;
92+
93+ status = readb(priv->base + I2C_OFS_IICSE0);
94+ return status & I2C_BIT_ALD0 ? -EAGAIN : status;
95+}
96+
97+static void em_i2c_stop(struct em_i2c_device *priv)
98+{
99+ /* Send Stop condition */
100+ em_clear_set_bit(priv, 0, I2C_BIT_SPT0 | I2C_BIT_SPIE0, I2C_OFS_IICC0);
101+
102+ /* Wait for stop condition */
103+ em_i2c_wait_for_event(priv);
104+}
105+
106+static void em_i2c_reset(struct i2c_adapter *adap)
107+{
108+ struct em_i2c_device *priv = i2c_get_adapdata(adap);
109+ int retr;
110+
111+ /* If I2C active */
112+ if (readb(priv->base + I2C_OFS_IICACT0) & I2C_BIT_IICE0) {
113+ /* Disable I2C operation */
114+ writeb(0, priv->base + I2C_OFS_IICACT0);
115+
116+ retr = 1000;
117+ while (readb(priv->base + I2C_OFS_IICACT0) == 1 && retr)
118+ retr--;
119+ WARN_ON(retr == 0);
120+ }
121+
122+ /* Transfer mode set */
123+ writeb(I2C_BIT_DFC0, priv->base + I2C_OFS_IICCL0);
124+
125+ /* Can Issue start without detecting a stop, Reservation disabled. */
126+ writeb(I2C_BIT_STCEN | I2C_BIT_IICRSV, priv->base + I2C_OFS_IICF0);
127+
128+ /* I2C enable, 9 bit interrupt mode */
129+ writeb(I2C_BIT_WTIM0, priv->base + I2C_OFS_IICC0);
130+
131+ /* Enable I2C operation */
132+ writeb(I2C_BIT_IICE0, priv->base + I2C_OFS_IICACT0);
133+
134+ retr = 1000;
135+ while (readb(priv->base + I2C_OFS_IICACT0) == 0 && retr)
136+ retr--;
137+ WARN_ON(retr == 0);
138+}
139+
140+static int __em_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg *msg,
141+ int stop)
142+{
143+ struct em_i2c_device *priv = i2c_get_adapdata(adap);
144+ int count, status, read = !!(msg->flags & I2C_M_RD);
145+
146+ /* Send start condition */
147+ em_clear_set_bit(priv, 0, I2C_BIT_ACKE0 | I2C_BIT_WTIM0, I2C_OFS_IICC0);
148+ em_clear_set_bit(priv, 0, I2C_BIT_STT0, I2C_OFS_IICC0);
149+
150+ /* Send slave address and R/W type */
151+ writeb((msg->addr << 1) | read, priv->base + I2C_OFS_IIC0);
152+
153+ /* Wait for transaction */
154+ status = em_i2c_wait_for_event(priv);
155+ if (status < 0)
156+ goto out_reset;
157+
158+ /* Received NACK (result of setting slave address and R/W) */
159+ if (!(status & I2C_BIT_ACKD0)) {
160+ em_i2c_stop(priv);
161+ goto out;
162+ }
163+
164+ /* Extra setup for read transactions */
165+ if (read) {
166+ /* 8 bit interrupt mode */
167+ em_clear_set_bit(priv, I2C_BIT_WTIM0, I2C_BIT_ACKE0, I2C_OFS_IICC0);
168+ em_clear_set_bit(priv, I2C_BIT_WTIM0, I2C_BIT_WREL0, I2C_OFS_IICC0);
169+
170+ /* Wait for transaction */
171+ status = em_i2c_wait_for_event(priv);
172+ if (status < 0)
173+ goto out_reset;
174+ }
175+
176+ /* Send / receive data */
177+ for (count = 0; count < msg->len; count++) {
178+ if (read) { /* Read transaction */
179+ msg->buf[count] = readb(priv->base + I2C_OFS_IIC0);
180+ em_clear_set_bit(priv, 0, I2C_BIT_WREL0, I2C_OFS_IICC0);
181+
182+ } else { /* Write transaction */
183+ /* Received NACK */
184+ if (!(status & I2C_BIT_ACKD0)) {
185+ em_i2c_stop(priv);
186+ goto out;
187+ }
188+
189+ /* Write data */
190+ writeb(msg->buf[count], priv->base + I2C_OFS_IIC0);
191+ }
192+
193+ /* Wait for R/W transaction */
194+ status = em_i2c_wait_for_event(priv);
195+ if (status < 0)
196+ goto out_reset;
197+ }
198+
199+ if (stop)
200+ em_i2c_stop(priv);
201+
202+ return count;
203+
204+out_reset:
205+ em_i2c_reset(adap);
206+out:
207+ return status < 0 ? status : -ENXIO;
208+}
209+
210+static int em_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs,
211+ int num)
212+{
213+ struct em_i2c_device *priv = i2c_get_adapdata(adap);
214+ int ret, i;
215+
216+ if (readb(priv->base + I2C_OFS_IICF0) & I2C_BIT_IICBSY)
217+ return -EAGAIN;
218+
219+ for (i = 0; i < num; i++) {
220+ ret = __em_i2c_xfer(adap, &msgs[i], (i == (num - 1)));
221+ if (ret < 0)
222+ return ret;
223+ }
224+
225+ /* I2C transfer completed */
226+ return num;
227+}
228+
229+static irqreturn_t em_i2c_irq_handler(int this_irq, void *dev_id)
230+{
231+ struct em_i2c_device *priv = dev_id;
232+
233+ complete(&priv->msg_done);
234+ return IRQ_HANDLED;
235+}
236+
237+static u32 em_i2c_func(struct i2c_adapter *adap)
238+{
239+ return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
240+}
241+
242+static struct i2c_algorithm em_i2c_algo = {
243+ .master_xfer = em_i2c_xfer,
244+ .functionality = em_i2c_func,
245+};
246+
247+static int em_i2c_probe(struct platform_device *pdev)
248+{
249+ struct em_i2c_device *priv;
250+ struct resource *r;
251+ int irq, ret;
252+
253+ priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
254+ if (!priv)
255+ return -ENOMEM;
256+
257+ r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
258+ priv->base = devm_ioremap_resource(&pdev->dev, r);
259+ if (IS_ERR(priv->base))
260+ return PTR_ERR(priv->base);
261+
262+ strlcpy(priv->adap.name, "EMEV2 I2C", sizeof(priv->adap.name));
263+
264+ priv->sclk = devm_clk_get(&pdev->dev, "sclk");
265+ if (IS_ERR(priv->sclk))
266+ return PTR_ERR(priv->sclk);
267+
268+ clk_prepare_enable(priv->sclk);
269+
270+ priv->adap.timeout = msecs_to_jiffies(100);
271+ priv->adap.retries = 5;
272+ priv->adap.dev.parent = &pdev->dev;
273+ priv->adap.algo = &em_i2c_algo;
274+ priv->adap.owner = THIS_MODULE;
275+ priv->adap.dev.of_node = pdev->dev.of_node;
276+
277+ init_completion(&priv->msg_done);
278+
279+ platform_set_drvdata(pdev, priv);
280+ i2c_set_adapdata(&priv->adap, priv);
281+
282+ em_i2c_reset(&priv->adap);
283+
284+ irq = platform_get_irq(pdev, 0);
285+ ret = devm_request_irq(&pdev->dev, irq, em_i2c_irq_handler, 0,
286+ "em_i2c", priv);
287+ if (ret)
288+ goto err_clk;
289+
290+ ret = i2c_add_adapter(&priv->adap);
291+
292+ if (ret)
293+ goto err_clk;
294+
295+ dev_info(&pdev->dev, "Added i2c controller %d, irq %d\n", priv->adap.nr, irq);
296+
297+ return 0;
298+
299+err_clk:
300+ clk_disable_unprepare(priv->sclk);
301+ return ret;
302+}
303+
304+static int em_i2c_remove(struct platform_device *dev)
305+{
306+ struct em_i2c_device *priv = platform_get_drvdata(dev);
307+
308+ i2c_del_adapter(&priv->adap);
309+ clk_disable_unprepare(priv->sclk);
310+
311+ return 0;
312+}
313+
314+static const struct of_device_id em_i2c_ids[] = {
315+ { .compatible = "renesas,iic-emev2", },
316+ { }
317+};
318+
319+static struct platform_driver em_i2c_driver = {
320+ .probe = em_i2c_probe,
321+ .remove = em_i2c_remove,
322+ .driver = {
323+ .name = "em-i2c",
324+ .of_match_table = em_i2c_ids,
325+ }
326+};
327+module_platform_driver(em_i2c_driver);
328+
329+MODULE_DESCRIPTION("EMEV2 I2C bus driver");
330+MODULE_AUTHOR("Ian Molton and Wolfram Sang <wsa@sang-engineering.com>");
331+MODULE_LICENSE("GPL v2");
332+MODULE_DEVICE_TABLE(of, em_i2c_ids);
drivers/i2c/busses/i2c-lpc2k.c+513−0
@@ -0,0 +1,513 @@
1+/*
2+ * Copyright (C) 2011 NXP Semiconductors
3+ *
4+ * Code portions referenced from the i2x-pxa and i2c-pnx drivers
5+ *
6+ * Make SMBus byte and word transactions work on LPC178x/7x
7+ * Copyright (c) 2012
8+ * Alexander Potashev, Emcraft Systems, aspotashev@emcraft.com
9+ * Anton Protopopov, Emcraft Systems, antonp@emcraft.com
10+ *
11+ * Copyright (C) 2015 Joachim Eastwood <manabian@gmail.com>
12+ *
13+ * This program is free software; you can redistribute it and/or modify
14+ * it under the terms of the GNU General Public License as published by
15+ * the Free Software Foundation; either version 2 of the License, or
16+ * (at your option) any later version.
17+ *
18+ */
19+
20+#include <linux/clk.h>
21+#include <linux/errno.h>
22+#include <linux/i2c.h>
23+#include <linux/interrupt.h>
24+#include <linux/io.h>
25+#include <linux/kernel.h>
26+#include <linux/module.h>
27+#include <linux/of.h>
28+#include <linux/of_device.h>
29+#include <linux/platform_device.h>
30+#include <linux/sched.h>
31+#include <linux/time.h>
32+
33+/* LPC24xx register offsets and bits */
34+#define LPC24XX_I2CONSET 0x00
35+#define LPC24XX_I2STAT 0x04
36+#define LPC24XX_I2DAT 0x08
37+#define LPC24XX_I2ADDR 0x0c
38+#define LPC24XX_I2SCLH 0x10
39+#define LPC24XX_I2SCLL 0x14
40+#define LPC24XX_I2CONCLR 0x18
41+
42+#define LPC24XX_AA BIT(2)
43+#define LPC24XX_SI BIT(3)
44+#define LPC24XX_STO BIT(4)
45+#define LPC24XX_STA BIT(5)
46+#define LPC24XX_I2EN BIT(6)
47+
48+#define LPC24XX_STO_AA (LPC24XX_STO | LPC24XX_AA)
49+#define LPC24XX_CLEAR_ALL (LPC24XX_AA | LPC24XX_SI | LPC24XX_STO | \
50+ LPC24XX_STA | LPC24XX_I2EN)
51+
52+/* I2C SCL clock has different duty cycle depending on mode */
53+#define I2C_STD_MODE_DUTY 46
54+#define I2C_FAST_MODE_DUTY 36
55+#define I2C_FAST_MODE_PLUS_DUTY 38
56+
57+/*
58+ * 26 possible I2C status codes, but codes applicable only
59+ * to master are listed here and used in this driver
60+ */
61+enum {
62+ M_BUS_ERROR = 0x00,
63+ M_START = 0x08,
64+ M_REPSTART = 0x10,
65+ MX_ADDR_W_ACK = 0x18,
66+ MX_ADDR_W_NACK = 0x20,
67+ MX_DATA_W_ACK = 0x28,
68+ MX_DATA_W_NACK = 0x30,
69+ M_DATA_ARB_LOST = 0x38,
70+ MR_ADDR_R_ACK = 0x40,
71+ MR_ADDR_R_NACK = 0x48,
72+ MR_DATA_R_ACK = 0x50,
73+ MR_DATA_R_NACK = 0x58,
74+ M_I2C_IDLE = 0xf8,
75+};
76+
77+struct lpc2k_i2c {
78+ void __iomem *base;
79+ struct clk *clk;
80+ int irq;
81+ wait_queue_head_t wait;
82+ struct i2c_adapter adap;
83+ struct i2c_msg *msg;
84+ int msg_idx;
85+ int msg_status;
86+ int is_last;
87+};
88+
89+static void i2c_lpc2k_reset(struct lpc2k_i2c *i2c)
90+{
91+ /* Will force clear all statuses */
92+ writel(LPC24XX_CLEAR_ALL, i2c->base + LPC24XX_I2CONCLR);
93+ writel(0, i2c->base + LPC24XX_I2ADDR);
94+ writel(LPC24XX_I2EN, i2c->base + LPC24XX_I2CONSET);
95+}
96+
97+static int i2c_lpc2k_clear_arb(struct lpc2k_i2c *i2c)
98+{
99+ unsigned long timeout = jiffies + msecs_to_jiffies(1000);
100+
101+ /*
102+ * If the transfer needs to abort for some reason, we'll try to
103+ * force a stop condition to clear any pending bus conditions
104+ */
105+ writel(LPC24XX_STO, i2c->base + LPC24XX_I2CONSET);
106+
107+ /* Wait for status change */
108+ while (readl(i2c->base + LPC24XX_I2STAT) != M_I2C_IDLE) {
109+ if (time_after(jiffies, timeout)) {
110+ /* Bus was not idle, try to reset adapter */
111+ i2c_lpc2k_reset(i2c);
112+ return -EBUSY;
113+ }
114+
115+ cpu_relax();
116+ }
117+
118+ return 0;
119+}
120+
121+static void i2c_lpc2k_pump_msg(struct lpc2k_i2c *i2c)
122+{
123+ unsigned char data;
124+ u32 status;
125+
126+ /*
127+ * I2C in the LPC2xxx series is basically a state machine.
128+ * Just run through the steps based on the current status.
129+ */
130+ status = readl(i2c->base + LPC24XX_I2STAT);
131+
132+ switch (status) {
133+ case M_START:
134+ case M_REPSTART:
135+ /* Start bit was just sent out, send out addr and dir */
136+ data = i2c->msg->addr << 1;
137+ if (i2c->msg->flags & I2C_M_RD)
138+ data |= 1;
139+
140+ writel(data, i2c->base + LPC24XX_I2DAT);
141+ writel(LPC24XX_STA, i2c->base + LPC24XX_I2CONCLR);
142+ break;
143+
144+ case MX_ADDR_W_ACK:
145+ case MX_DATA_W_ACK:
146+ /*
147+ * Address or data was sent out with an ACK. If there is more
148+ * data to send, send it now
149+ */
150+ if (i2c->msg_idx < i2c->msg->len) {
151+ writel(i2c->msg->buf[i2c->msg_idx],
152+ i2c->base + LPC24XX_I2DAT);
153+ } else if (i2c->is_last) {
154+ /* Last message, send stop */
155+ writel(LPC24XX_STO_AA, i2c->base + LPC24XX_I2CONSET);
156+ writel(LPC24XX_SI, i2c->base + LPC24XX_I2CONCLR);
157+ i2c->msg_status = 0;
158+ disable_irq_nosync(i2c->irq);
159+ } else {
160+ i2c->msg_status = 0;
161+ disable_irq_nosync(i2c->irq);
162+ }
163+
164+ i2c->msg_idx++;
165+ break;
166+
167+ case MR_ADDR_R_ACK:
168+ /* Receive first byte from slave */
169+ if (i2c->msg->len == 1) {
170+ /* Last byte, return NACK */
171+ writel(LPC24XX_AA, i2c->base + LPC24XX_I2CONCLR);
172+ } else {
173+ /* Not last byte, return ACK */
174+ writel(LPC24XX_AA, i2c->base + LPC24XX_I2CONSET);
175+ }
176+
177+ writel(LPC24XX_STA, i2c->base + LPC24XX_I2CONCLR);
178+ break;
179+
180+ case MR_DATA_R_NACK:
181+ /*
182+ * The I2C shows NACK status on reads, so we need to accept
183+ * the NACK as an ACK here. This should be ok, as the real
184+ * BACK would of been caught on the address write.
185+ */
186+ case MR_DATA_R_ACK:
187+ /* Data was received */
188+ if (i2c->msg_idx < i2c->msg->len) {
189+ i2c->msg->buf[i2c->msg_idx] =
190+ readl(i2c->base + LPC24XX_I2DAT);
191+ }
192+
193+ /* If transfer is done, send STOP */
194+ if (i2c->msg_idx >= i2c->msg->len - 1 && i2c->is_last) {
195+ writel(LPC24XX_STO_AA, i2c->base + LPC24XX_I2CONSET);
196+ writel(LPC24XX_SI, i2c->base + LPC24XX_I2CONCLR);
197+ i2c->msg_status = 0;
198+ }
199+
200+ /* Message is done */
201+ if (i2c->msg_idx >= i2c->msg->len - 1) {
202+ i2c->msg_status = 0;
203+ disable_irq_nosync(i2c->irq);
204+ }
205+
206+ /*
207+ * One pre-last data input, send NACK to tell the slave that
208+ * this is going to be the last data byte to be transferred.
209+ */
210+ if (i2c->msg_idx >= i2c->msg->len - 2) {
211+ /* One byte left to receive - NACK */
212+ writel(LPC24XX_AA, i2c->base + LPC24XX_I2CONCLR);
213+ } else {
214+ /* More than one byte left to receive - ACK */
215+ writel(LPC24XX_AA, i2c->base + LPC24XX_I2CONSET);
216+ }
217+
218+ writel(LPC24XX_STA, i2c->base + LPC24XX_I2CONCLR);
219+ i2c->msg_idx++;
220+ break;
221+
222+ case MX_ADDR_W_NACK:
223+ case MX_DATA_W_NACK:
224+ case MR_ADDR_R_NACK:
225+ /* NACK processing is done */
226+ writel(LPC24XX_STO_AA, i2c->base + LPC24XX_I2CONSET);
227+ i2c->msg_status = -ENXIO;
228+ disable_irq_nosync(i2c->irq);
229+ break;
230+
231+ case M_DATA_ARB_LOST:
232+ /* Arbitration lost */
233+ i2c->msg_status = -EAGAIN;
234+
235+ /* Release the I2C bus */
236+ writel(LPC24XX_STA | LPC24XX_STO, i2c->base + LPC24XX_I2CONCLR);
237+ disable_irq_nosync(i2c->irq);
238+ break;
239+
240+ default:
241+ /* Unexpected statuses */
242+ i2c->msg_status = -EIO;
243+ disable_irq_nosync(i2c->irq);
244+ break;
245+ }
246+
247+ /* Exit on failure or all bytes transferred */
248+ if (i2c->msg_status != -EBUSY)
249+ wake_up(&i2c->wait);
250+
251+ /*
252+ * If `msg_status` is zero, then `lpc2k_process_msg()`
253+ * is responsible for clearing the SI flag.
254+ */
255+ if (i2c->msg_status != 0)
256+ writel(LPC24XX_SI, i2c->base + LPC24XX_I2CONCLR);
257+}
258+
259+static int lpc2k_process_msg(struct lpc2k_i2c *i2c, int msgidx)
260+{
261+ /* A new transfer is kicked off by initiating a start condition */
262+ if (!msgidx) {
263+ writel(LPC24XX_STA, i2c->base + LPC24XX_I2CONSET);
264+ } else {
265+ /*
266+ * A multi-message I2C transfer continues where the
267+ * previous I2C transfer left off and uses the
268+ * current condition of the I2C adapter.
269+ */
270+ if (unlikely(i2c->msg->flags & I2C_M_NOSTART)) {
271+ WARN_ON(i2c->msg->len == 0);
272+
273+ if (!(i2c->msg->flags & I2C_M_RD)) {
274+ /* Start transmit of data */
275+ writel(i2c->msg->buf[0],
276+ i2c->base + LPC24XX_I2DAT);
277+ i2c->msg_idx++;
278+ }
279+ } else {
280+ /* Start or repeated start */
281+ writel(LPC24XX_STA, i2c->base + LPC24XX_I2CONSET);
282+ }
283+
284+ writel(LPC24XX_SI, i2c->base + LPC24XX_I2CONCLR);
285+ }
286+
287+ enable_irq(i2c->irq);
288+
289+ /* Wait for transfer completion */
290+ if (wait_event_timeout(i2c->wait, i2c->msg_status != -EBUSY,
291+ msecs_to_jiffies(1000)) == 0) {
292+ disable_irq_nosync(i2c->irq);
293+
294+ return -ETIMEDOUT;
295+ }
296+
297+ return i2c->msg_status;
298+}
299+
300+static int i2c_lpc2k_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs,
301+ int msg_num)
302+{
303+ struct lpc2k_i2c *i2c = i2c_get_adapdata(adap);
304+ int ret, i;
305+ u32 stat;
306+
307+ /* Check for bus idle condition */
308+ stat = readl(i2c->base + LPC24XX_I2STAT);
309+ if (stat != M_I2C_IDLE) {
310+ /* Something is holding the bus, try to clear it */
311+ return i2c_lpc2k_clear_arb(i2c);
312+ }
313+
314+ /* Process a single message at a time */
315+ for (i = 0; i < msg_num; i++) {
316+ /* Save message pointer and current message data index */
317+ i2c->msg = &msgs[i];
318+ i2c->msg_idx = 0;
319+ i2c->msg_status = -EBUSY;
320+ i2c->is_last = (i == (msg_num - 1));
321+
322+ ret = lpc2k_process_msg(i2c, i);
323+ if (ret)
324+ return ret;
325+ }
326+
327+ return msg_num;
328+}
329+
330+static irqreturn_t i2c_lpc2k_handler(int irq, void *dev_id)
331+{
332+ struct lpc2k_i2c *i2c = dev_id;
333+
334+ if (readl(i2c->base + LPC24XX_I2CONSET) & LPC24XX_SI) {
335+ i2c_lpc2k_pump_msg(i2c);
336+ return IRQ_HANDLED;
337+ }
338+
339+ return IRQ_NONE;
340+}
341+
342+static u32 i2c_lpc2k_functionality(struct i2c_adapter *adap)
343+{
344+ /* Only emulated SMBus for now */
345+ return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
346+}
347+
348+static const struct i2c_algorithm i2c_lpc2k_algorithm = {
349+ .master_xfer = i2c_lpc2k_xfer,
350+ .functionality = i2c_lpc2k_functionality,
351+};
352+
353+static int i2c_lpc2k_probe(struct platform_device *pdev)
354+{
355+ struct lpc2k_i2c *i2c;
356+ struct resource *res;
357+ u32 bus_clk_rate;
358+ u32 scl_high;
359+ u32 clkrate;
360+ int ret;
361+
362+ i2c = devm_kzalloc(&pdev->dev, sizeof(*i2c), GFP_KERNEL);
363+ if (!i2c)
364+ return -ENOMEM;
365+
366+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
367+ i2c->base = devm_ioremap_resource(&pdev->dev, res);
368+ if (IS_ERR(i2c->base))
369+ return PTR_ERR(i2c->base);
370+
371+ i2c->irq = platform_get_irq(pdev, 0);
372+ if (i2c->irq < 0) {
373+ dev_err(&pdev->dev, "can't get interrupt resource\n");
374+ return i2c->irq;
375+ }
376+
377+ init_waitqueue_head(&i2c->wait);
378+
379+ i2c->clk = devm_clk_get(&pdev->dev, NULL);
380+ if (IS_ERR(i2c->clk)) {
381+ dev_err(&pdev->dev, "error getting clock\n");
382+ return PTR_ERR(i2c->clk);
383+ }
384+
385+ ret = clk_prepare_enable(i2c->clk);
386+ if (ret) {
387+ dev_err(&pdev->dev, "unable to enable clock.\n");
388+ return ret;
389+ }
390+
391+ ret = devm_request_irq(&pdev->dev, i2c->irq, i2c_lpc2k_handler, 0,
392+ dev_name(&pdev->dev), i2c);
393+ if (ret < 0) {
394+ dev_err(&pdev->dev, "can't request interrupt.\n");
395+ goto fail_clk;
396+ }
397+
398+ disable_irq_nosync(i2c->irq);
399+
400+ /* Place controller is a known state */
401+ i2c_lpc2k_reset(i2c);
402+
403+ ret = of_property_read_u32(pdev->dev.of_node, "clock-frequency",
404+ &bus_clk_rate);
405+ if (ret)
406+ bus_clk_rate = 100000; /* 100 kHz default clock rate */
407+
408+ clkrate = clk_get_rate(i2c->clk);
409+ if (clkrate == 0) {
410+ dev_err(&pdev->dev, "can't get I2C base clock\n");
411+ ret = -EINVAL;
412+ goto fail_clk;
413+ }
414+
415+ /* Setup I2C dividers to generate clock with proper duty cycle */
416+ clkrate = clkrate / bus_clk_rate;
417+ if (bus_clk_rate <= 100000)
418+ scl_high = (clkrate * I2C_STD_MODE_DUTY) / 100;
419+ else if (bus_clk_rate <= 400000)
420+ scl_high = (clkrate * I2C_FAST_MODE_DUTY) / 100;
421+ else
422+ scl_high = (clkrate * I2C_FAST_MODE_PLUS_DUTY) / 100;
423+
424+ writel(scl_high, i2c->base + LPC24XX_I2SCLH);
425+ writel(clkrate - scl_high, i2c->base + LPC24XX_I2SCLL);
426+
427+ platform_set_drvdata(pdev, i2c);
428+
429+ i2c_set_adapdata(&i2c->adap, i2c);
430+ i2c->adap.owner = THIS_MODULE;
431+ strlcpy(i2c->adap.name, "LPC2K I2C adapter", sizeof(i2c->adap.name));
432+ i2c->adap.algo = &i2c_lpc2k_algorithm;
433+ i2c->adap.dev.parent = &pdev->dev;
434+ i2c->adap.dev.of_node = pdev->dev.of_node;
435+
436+ ret = i2c_add_adapter(&i2c->adap);
437+ if (ret < 0) {
438+ dev_err(&pdev->dev, "failed to add adapter!\n");
439+ goto fail_clk;
440+ }
441+
442+ dev_info(&pdev->dev, "LPC2K I2C adapter\n");
443+
444+ return 0;
445+
446+fail_clk:
447+ clk_disable_unprepare(i2c->clk);
448+ return ret;
449+}
450+
451+static int i2c_lpc2k_remove(struct platform_device *dev)
452+{
453+ struct lpc2k_i2c *i2c = platform_get_drvdata(dev);
454+
455+ i2c_del_adapter(&i2c->adap);
456+ clk_disable_unprepare(i2c->clk);
457+
458+ return 0;
459+}
460+
461+#ifdef CONFIG_PM
462+static int i2c_lpc2k_suspend(struct device *dev)
463+{
464+ struct platform_device *pdev = to_platform_device(dev);
465+ struct lpc2k_i2c *i2c = platform_get_drvdata(pdev);
466+
467+ clk_disable(i2c->clk);
468+
469+ return 0;
470+}
471+
472+static int i2c_lpc2k_resume(struct device *dev)
473+{
474+ struct platform_device *pdev = to_platform_device(dev);
475+ struct lpc2k_i2c *i2c = platform_get_drvdata(pdev);
476+
477+ clk_enable(i2c->clk);
478+ i2c_lpc2k_reset(i2c);
479+
480+ return 0;
481+}
482+
483+static const struct dev_pm_ops i2c_lpc2k_dev_pm_ops = {
484+ .suspend_noirq = i2c_lpc2k_suspend,
485+ .resume_noirq = i2c_lpc2k_resume,
486+};
487+
488+#define I2C_LPC2K_DEV_PM_OPS (&i2c_lpc2k_dev_pm_ops)
489+#else
490+#define I2C_LPC2K_DEV_PM_OPS NULL
491+#endif
492+
493+static const struct of_device_id lpc2k_i2c_match[] = {
494+ { .compatible = "nxp,lpc1788-i2c" },
495+ {},
496+};
497+MODULE_DEVICE_TABLE(of, lpc2k_i2c_match);
498+
499+static struct platform_driver i2c_lpc2k_driver = {
500+ .probe = i2c_lpc2k_probe,
501+ .remove = i2c_lpc2k_remove,
502+ .driver = {
503+ .name = "lpc2k-i2c",
504+ .pm = I2C_LPC2K_DEV_PM_OPS,
505+ .of_match_table = lpc2k_i2c_match,
506+ },
507+};
508+module_platform_driver(i2c_lpc2k_driver);
509+
510+MODULE_AUTHOR("Kevin Wells <kevin.wells@nxp.com>");
511+MODULE_DESCRIPTION("I2C driver for LPC2xxx devices");
512+MODULE_LICENSE("GPL");
513+MODULE_ALIAS("platform:lpc2k-i2c");
drivers/i2c/busses/i2c-mt65xx.c+17−4
@@ -59,6 +59,7 @@ · 58 unmodified lines
5959 #define I2C_DMA_START_EN 0x0001
6060 #define I2C_DMA_INT_FLAG_NONE 0x0000
6161 #define I2C_DMA_CLR_FLAG 0x0000
62+#define I2C_DMA_HARD_RST 0x0002
6263
6364 #define I2C_DEFAULT_SPEED 100000 /* hz */
6465 #define MAX_FS_MODE_SPEED 400000
@@ -81,6 +82,7 @@ enum DMA_REGS_OFFSET { · 16 unmodified lines
8182 OFFSET_INT_FLAG = 0x0,
8283 OFFSET_INT_EN = 0x04,
8384 OFFSET_EN = 0x08,
85+ OFFSET_RST = 0x0c,
8486 OFFSET_CON = 0x18,
8587 OFFSET_TX_MEM_ADDR = 0x1c,
8688 OFFSET_RX_MEM_ADDR = 0x20,
@@ -262,6 +264,10 @@ static void mtk_i2c_init_hw(struct mtk_i2c *i2c) · 175 unmodified lines
262264 I2C_CONTROL_CLK_EXT_EN | I2C_CONTROL_DMA_EN;
263265 writew(control_reg, i2c->base + OFFSET_CONTROL);
264266 writew(I2C_DELAY_LEN, i2c->base + OFFSET_DELAY_LEN);
267+
268+ writel(I2C_DMA_HARD_RST, i2c->pdmabase + OFFSET_RST);
269+ udelay(50);
270+ writel(I2C_DMA_CLR_FLAG, i2c->pdmabase + OFFSET_RST);
265271 }
266272
267273 /*
@@ -551,15 +557,22 @@ static irqreturn_t mtk_i2c_irq(int irqno, void *dev_id) · 283 unmodified lines
551557 {
552558 struct mtk_i2c *i2c = dev_id;
553559 u16 restart_flag = 0;
560+ u16 intr_stat;
554561
555562 if (i2c->dev_comp->auto_restart)
556563 restart_flag = I2C_RS_TRANSFER;
557564
558− i2c->irq_stat = readw(i2c->base + OFFSET_INTR_STAT);
559− writew(restart_flag | I2C_HS_NACKERR | I2C_ACKERR
560− | I2C_TRANSAC_COMP, i2c->base + OFFSET_INTR_STAT);
565+ intr_stat = readw(i2c->base + OFFSET_INTR_STAT);
566+ writew(intr_stat, i2c->base + OFFSET_INTR_STAT);
561567
562− complete(&i2c->msg_complete);
568+ /*
569+ * when occurs ack error, i2c controller generate two interrupts
570+ * first is the ack error interrupt, then the complete interrupt
571+ * i2c->irq_stat need keep the two interrupt value.
572+ */
573+ i2c->irq_stat |= intr_stat;
574+ if (i2c->irq_stat & (I2C_TRANSAC_COMP | restart_flag))
575+ complete(&i2c->msg_complete);
563576
564577 return IRQ_HANDLED;
565578 }
drivers/i2c/busses/i2c-omap.c+299−301
@@ -270,35 +270,35 @@ static const u8 reg_map_ip_v2[] = { · 269 unmodified lines
270270 [OMAP_I2C_IP_V2_IRQENABLE_CLR] = 0x30,
271271 };
272272
273−static inline void omap_i2c_write_reg(struct omap_i2c_dev *i2c_dev,
273+static inline void omap_i2c_write_reg(struct omap_i2c_dev *omap,
274274 int reg, u16 val)
275275 {
276− writew_relaxed(val, i2c_dev->base +
277− (i2c_dev->regs[reg] << i2c_dev->reg_shift));
276+ writew_relaxed(val, omap->base +
277+ (omap->regs[reg] << omap->reg_shift));
278278 }
279279
280−static inline u16 omap_i2c_read_reg(struct omap_i2c_dev *i2c_dev, int reg)
280+static inline u16 omap_i2c_read_reg(struct omap_i2c_dev *omap, int reg)
281281 {
282− return readw_relaxed(i2c_dev->base +
283− (i2c_dev->regs[reg] << i2c_dev->reg_shift));
282+ return readw_relaxed(omap->base +
283+ (omap->regs[reg] << omap->reg_shift));
284284 }
285285
286−static void __omap_i2c_init(struct omap_i2c_dev *dev)
286+static void __omap_i2c_init(struct omap_i2c_dev *omap)
287287 {
288288
289− omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, 0);
289+ omap_i2c_write_reg(omap, OMAP_I2C_CON_REG, 0);
290290
291291 /* Setup clock prescaler to obtain approx 12MHz I2C module clock: */
292− omap_i2c_write_reg(dev, OMAP_I2C_PSC_REG, dev->pscstate);
292+ omap_i2c_write_reg(omap, OMAP_I2C_PSC_REG, omap->pscstate);
293293
294294 /* SCL low and high time values */
295− omap_i2c_write_reg(dev, OMAP_I2C_SCLL_REG, dev->scllstate);
296− omap_i2c_write_reg(dev, OMAP_I2C_SCLH_REG, dev->sclhstate);
297− if (dev->rev >= OMAP_I2C_REV_ON_3430_3530)
298− omap_i2c_write_reg(dev, OMAP_I2C_WE_REG, dev->westate);
295+ omap_i2c_write_reg(omap, OMAP_I2C_SCLL_REG, omap->scllstate);
296+ omap_i2c_write_reg(omap, OMAP_I2C_SCLH_REG, omap->sclhstate);
297+ if (omap->rev >= OMAP_I2C_REV_ON_3430_3530)
298+ omap_i2c_write_reg(omap, OMAP_I2C_WE_REG, omap->westate);
299299
300300 /* Take the I2C module out of reset: */
301− omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, OMAP_I2C_CON_EN);
301+ omap_i2c_write_reg(omap, OMAP_I2C_CON_REG, OMAP_I2C_CON_EN);
302302
303303 /*
304304 * NOTE: right after setting CON_EN, STAT_BB could be 0 while the
@@ -310,32 +310,32 @@ static void __omap_i2c_init(struct omap_i2c_dev *dev) · 5 unmodified lines
310310 * Don't write to this register if the IE state is 0 as it can
311311 * cause deadlock.
312312 */
313− if (dev->iestate)
314− omap_i2c_write_reg(dev, OMAP_I2C_IE_REG, dev->iestate);
313+ if (omap->iestate)
314+ omap_i2c_write_reg(omap, OMAP_I2C_IE_REG, omap->iestate);
315315 }
316316
317−static int omap_i2c_reset(struct omap_i2c_dev *dev)
317+static int omap_i2c_reset(struct omap_i2c_dev *omap)
318318 {
319319 unsigned long timeout;
320320 u16 sysc;
321321
322− if (dev->rev >= OMAP_I2C_OMAP1_REV_2) {
323− sysc = omap_i2c_read_reg(dev, OMAP_I2C_SYSC_REG);
322+ if (omap->rev >= OMAP_I2C_OMAP1_REV_2) {
323+ sysc = omap_i2c_read_reg(omap, OMAP_I2C_SYSC_REG);
324324
325325 /* Disable I2C controller before soft reset */
326− omap_i2c_write_reg(dev, OMAP_I2C_CON_REG,
327− omap_i2c_read_reg(dev, OMAP_I2C_CON_REG) &
326+ omap_i2c_write_reg(omap, OMAP_I2C_CON_REG,
327+ omap_i2c_read_reg(omap, OMAP_I2C_CON_REG) &
328328 ~(OMAP_I2C_CON_EN));
329329
330− omap_i2c_write_reg(dev, OMAP_I2C_SYSC_REG, SYSC_SOFTRESET_MASK);
330+ omap_i2c_write_reg(omap, OMAP_I2C_SYSC_REG, SYSC_SOFTRESET_MASK);
331331 /* For some reason we need to set the EN bit before the
332332 * reset done bit gets set. */
333333 timeout = jiffies + OMAP_I2C_TIMEOUT;
334− omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, OMAP_I2C_CON_EN);
335− while (!(omap_i2c_read_reg(dev, OMAP_I2C_SYSS_REG) &
334+ omap_i2c_write_reg(omap, OMAP_I2C_CON_REG, OMAP_I2C_CON_EN);
335+ while (!(omap_i2c_read_reg(omap, OMAP_I2C_SYSS_REG) &
336336 SYSS_RESETDONE_MASK)) {
337337 if (time_after(jiffies, timeout)) {
338− dev_warn(dev->dev, "timeout waiting "
338+ dev_warn(omap->dev, "timeout waiting "
339339 "for controller reset\n");
340340 return -ETIMEDOUT;
341341 }
@@ -343,18 +343,18 @@ static int omap_i2c_reset(struct omap_i2c_dev *dev) · 1 unmodified line
343343 }
344344
345345 /* SYSC register is cleared by the reset; rewrite it */
346− omap_i2c_write_reg(dev, OMAP_I2C_SYSC_REG, sysc);
346+ omap_i2c_write_reg(omap, OMAP_I2C_SYSC_REG, sysc);
347347
348− if (dev->rev > OMAP_I2C_REV_ON_3430_3530) {
348+ if (omap->rev > OMAP_I2C_REV_ON_3430_3530) {
349349 /* Schedule I2C-bus monitoring on the next transfer */
350− dev->bb_valid = 0;
350+ omap->bb_valid = 0;
351351 }
352352 }
353353
354354 return 0;
355355 }
356356
357−static int omap_i2c_init(struct omap_i2c_dev *dev)
357+static int omap_i2c_init(struct omap_i2c_dev *omap)
358358 {
359359 u16 psc = 0, scll = 0, sclh = 0;
360360 u16 fsscll = 0, fssclh = 0, hsscll = 0, hssclh = 0;
@@ -362,23 +362,23 @@ static int omap_i2c_init(struct omap_i2c_dev *dev) · 1 unmodified line
362362 unsigned long internal_clk = 0;
363363 struct clk *fclk;
364364
365− if (dev->rev >= OMAP_I2C_REV_ON_3430_3530) {
365+ if (omap->rev >= OMAP_I2C_REV_ON_3430_3530) {
366366 /*
367367 * Enabling all wakup sources to stop I2C freezing on
368368 * WFI instruction.
369369 * REVISIT: Some wkup sources might not be needed.
370370 */
371− dev->westate = OMAP_I2C_WE_ALL;
371+ omap->westate = OMAP_I2C_WE_ALL;
372372 }
373373
374− if (dev->flags & OMAP_I2C_FLAG_ALWAYS_ARMXOR_CLK) {
374+ if (omap->flags & OMAP_I2C_FLAG_ALWAYS_ARMXOR_CLK) {
375375 /*
376376 * The I2C functional clock is the armxor_ck, so there's
377377 * no need to get "armxor_ck" separately. Now, if OMAP2420
378378 * always returns 12MHz for the functional clock, we can
379379 * do this bit unconditionally.
380380 */
381− fclk = clk_get(dev->dev, "fck");
381+ fclk = clk_get(omap->dev, "fck");
382382 fclk_rate = clk_get_rate(fclk);
383383 clk_put(fclk);
384384
@@ -395,7 +395,7 @@ static int omap_i2c_init(struct omap_i2c_dev *dev) · 10 unmodified lines
395395 psc = fclk_rate / 12000000;
396396 }
397397
398− if (!(dev->flags & OMAP_I2C_FLAG_SIMPLE_CLOCK)) {
398+ if (!(omap->flags & OMAP_I2C_FLAG_SIMPLE_CLOCK)) {
399399
400400 /*
401401 * HSI2C controller internal clk rate should be 19.2 Mhz for
@@ -403,14 +403,14 @@ static int omap_i2c_init(struct omap_i2c_dev *dev) · 1 unmodified line
403403 * to get longer filter period for better noise suppression.
404404 * The filter is iclk (fclk for HS) period.
405405 */
406− if (dev->speed > 400 ||
407− dev->flags & OMAP_I2C_FLAG_FORCE_19200_INT_CLK)
406+ if (omap->speed > 400 ||
407+ omap->flags & OMAP_I2C_FLAG_FORCE_19200_INT_CLK)
408408 internal_clk = 19200;
409− else if (dev->speed > 100)
409+ else if (omap->speed > 100)
410410 internal_clk = 9600;
411411 else
412412 internal_clk = 4000;
413− fclk = clk_get(dev->dev, "fck");
413+ fclk = clk_get(omap->dev, "fck");
414414 fclk_rate = clk_get_rate(fclk) / 1000;
415415 clk_put(fclk);
416416
@@ -419,7 +419,7 @@ static int omap_i2c_init(struct omap_i2c_dev *dev) · 2 unmodified lines
419419 psc = psc - 1;
420420
421421 /* If configured for High Speed */
422− if (dev->speed > 400) {
422+ if (omap->speed > 400) {
423423 unsigned long scl;
424424
425425 /* For first phase of HS mode */
@@ -428,20 +428,20 @@ static int omap_i2c_init(struct omap_i2c_dev *dev) · 2 unmodified lines
428428 fssclh = (scl / 3) - 5;
429429
430430 /* For second phase of HS mode */
431− scl = fclk_rate / dev->speed;
431+ scl = fclk_rate / omap->speed;
432432 hsscll = scl - (scl / 3) - 7;
433433 hssclh = (scl / 3) - 5;
434− } else if (dev->speed > 100) {
434+ } else if (omap->speed > 100) {
435435 unsigned long scl;
436436
437437 /* Fast mode */
438− scl = internal_clk / dev->speed;
438+ scl = internal_clk / omap->speed;
439439 fsscll = scl - (scl / 3) - 7;
440440 fssclh = (scl / 3) - 5;
441441 } else {
442442 /* Standard mode */
443− fsscll = internal_clk / (dev->speed * 2) - 7;
444− fssclh = internal_clk / (dev->speed * 2) - 5;
443+ fsscll = internal_clk / (omap->speed * 2) - 7;
444+ fssclh = internal_clk / (omap->speed * 2) - 5;
445445 }
446446 scll = (hsscll << OMAP_I2C_SCLL_HSSCLL) | fsscll;
447447 sclh = (hssclh << OMAP_I2C_SCLH_HSSCLH) | fssclh;
@@ -450,25 +450,25 @@ static int omap_i2c_init(struct omap_i2c_dev *dev) · 2 unmodified lines
450450 fclk_rate /= (psc + 1) * 1000;
451451 if (psc > 2)
452452 psc = 2;
453− scll = fclk_rate / (dev->speed * 2) - 7 + psc;
454− sclh = fclk_rate / (dev->speed * 2) - 7 + psc;
453+ scll = fclk_rate / (omap->speed * 2) - 7 + psc;
454+ sclh = fclk_rate / (omap->speed * 2) - 7 + psc;
455455 }
456456
457− dev->iestate = (OMAP_I2C_IE_XRDY | OMAP_I2C_IE_RRDY |
457+ omap->iestate = (OMAP_I2C_IE_XRDY | OMAP_I2C_IE_RRDY |
458458 OMAP_I2C_IE_ARDY | OMAP_I2C_IE_NACK |
459− OMAP_I2C_IE_AL) | ((dev->fifo_size) ?
459+ OMAP_I2C_IE_AL) | ((omap->fifo_size) ?
460460 (OMAP_I2C_IE_RDR | OMAP_I2C_IE_XDR) : 0);
461461
462− dev->pscstate = psc;
463− dev->scllstate = scll;
464− dev->sclhstate = sclh;
462+ omap->pscstate = psc;
463+ omap->scllstate = scll;
464+ omap->sclhstate = sclh;
465465
466− if (dev->rev <= OMAP_I2C_REV_ON_3430_3530) {
466+ if (omap->rev <= OMAP_I2C_REV_ON_3430_3530) {
467467 /* Not implemented */
468− dev->bb_valid = 1;
468+ omap->bb_valid = 1;
469469 }
470470
471− __omap_i2c_init(dev);
471+ __omap_i2c_init(omap);
472472
473473 return 0;
474474 }
@@ -476,14 +476,14 @@ static int omap_i2c_init(struct omap_i2c_dev *dev) · 1 unmodified line
476476 /*
477477 * Waiting on Bus Busy
478478 */
479−static int omap_i2c_wait_for_bb(struct omap_i2c_dev *dev)
479+static int omap_i2c_wait_for_bb(struct omap_i2c_dev *omap)
480480 {
481481 unsigned long timeout;
482482
483483 timeout = jiffies + OMAP_I2C_TIMEOUT;
484− while (omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG) & OMAP_I2C_STAT_BB) {
484+ while (omap_i2c_read_reg(omap, OMAP_I2C_STAT_REG) & OMAP_I2C_STAT_BB) {
485485 if (time_after(jiffies, timeout))
486− return i2c_recover_bus(&dev->adapter);
486+ return i2c_recover_bus(&omap->adapter);
487487 msleep(1);
488488 }
489489
@@ -518,19 +518,19 @@ static int omap_i2c_wait_for_bb(struct omap_i2c_dev *dev) · 28 unmodified lines
518518 * 3. Any transfer started in the middle of another master's transfer
519519 * results in unpredictable results and data corruption
520520 */
521−static int omap_i2c_wait_for_bb_valid(struct omap_i2c_dev *dev)
521+static int omap_i2c_wait_for_bb_valid(struct omap_i2c_dev *omap)
522522 {
523523 unsigned long bus_free_timeout = 0;
524524 unsigned long timeout;
525525 int bus_free = 0;
526526 u16 stat, systest;
527527
528− if (dev->bb_valid)
528+ if (omap->bb_valid)
529529 return 0;
530530
531531 timeout = jiffies + OMAP_I2C_TIMEOUT;
532532 while (1) {
533− stat = omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG);
533+ stat = omap_i2c_read_reg(omap, OMAP_I2C_STAT_REG);
534534 /*
535535 * We will see BB or BF event in a case IP had detected any
536536 * activity on the I2C bus. Now IP correctly tracks the bus
@@ -543,7 +543,7 @@ static int omap_i2c_wait_for_bb_valid(struct omap_i2c_dev *dev) · 6 unmodified lines
543543 * Otherwise, we must look signals on the bus to make
544544 * the right decision.
545545 */
546− systest = omap_i2c_read_reg(dev, OMAP_I2C_SYSTEST_REG);
546+ systest = omap_i2c_read_reg(omap, OMAP_I2C_SYSTEST_REG);
547547 if ((systest & OMAP_I2C_SYSTEST_SCL_I_FUNC) &&
548548 (systest & OMAP_I2C_SYSTEST_SDA_I_FUNC)) {
549549 if (!bus_free) {
@@ -564,22 +564,22 @@ static int omap_i2c_wait_for_bb_valid(struct omap_i2c_dev *dev) · 14 unmodified lines
564564 }
565565
566566 if (time_after(jiffies, timeout)) {
567− dev_warn(dev->dev, "timeout waiting for bus ready\n");
567+ dev_warn(omap->dev, "timeout waiting for bus ready\n");
568568 return -ETIMEDOUT;
569569 }
570570
571571 msleep(1);
572572 }
573573
574− dev->bb_valid = 1;
574+ omap->bb_valid = 1;
575575 return 0;
576576 }
577577
578−static void omap_i2c_resize_fifo(struct omap_i2c_dev *dev, u8 size, bool is_rx)
578+static void omap_i2c_resize_fifo(struct omap_i2c_dev *omap, u8 size, bool is_rx)
579579 {
580580 u16 buf;
581581
582− if (dev->flags & OMAP_I2C_FLAG_NO_FIFO)
582+ if (omap->flags & OMAP_I2C_FLAG_NO_FIFO)
583583 return;
584584
585585 /*
@@ -589,29 +589,29 @@ static void omap_i2c_resize_fifo(struct omap_i2c_dev *dev, u8 size, bool is_rx) · 3 unmodified lines
589589 * then we might use draining feature to transfer the remaining bytes.
590590 */
591591
592− dev->threshold = clamp(size, (u8) 1, dev->fifo_size);
592+ omap->threshold = clamp(size, (u8) 1, omap->fifo_size);
593593
594− buf = omap_i2c_read_reg(dev, OMAP_I2C_BUF_REG);
594+ buf = omap_i2c_read_reg(omap, OMAP_I2C_BUF_REG);
595595
596596 if (is_rx) {
597597 /* Clear RX Threshold */
598598 buf &= ~(0x3f << 8);
599− buf |= ((dev->threshold - 1) << 8) | OMAP_I2C_BUF_RXFIF_CLR;
599+ buf |= ((omap->threshold - 1) << 8) | OMAP_I2C_BUF_RXFIF_CLR;
600600 } else {
601601 /* Clear TX Threshold */
602602 buf &= ~0x3f;
603− buf |= (dev->threshold - 1) | OMAP_I2C_BUF_TXFIF_CLR;
603+ buf |= (omap->threshold - 1) | OMAP_I2C_BUF_TXFIF_CLR;
604604 }
605605
606− omap_i2c_write_reg(dev, OMAP_I2C_BUF_REG, buf);
606+ omap_i2c_write_reg(omap, OMAP_I2C_BUF_REG, buf);
607607
608− if (dev->rev < OMAP_I2C_REV_ON_3630)
609− dev->b_hw = 1; /* Enable hardware fixes */
608+ if (omap->rev < OMAP_I2C_REV_ON_3630)
609+ omap->b_hw = 1; /* Enable hardware fixes */
610610
611611 /* calculate wakeup latency constraint for MPU */
612− if (dev->set_mpu_wkup_lat != NULL)
613− dev->latency = (1000000 * dev->threshold) /
614− (1000 * dev->speed / 8);
612+ if (omap->set_mpu_wkup_lat != NULL)
613+ omap->latency = (1000000 * omap->threshold) /
614+ (1000 * omap->speed / 8);
615615 }
616616
617617 /*
@@ -620,42 +620,42 @@ static void omap_i2c_resize_fifo(struct omap_i2c_dev *dev, u8 size, bool is_rx) · 2 unmodified lines
620620 static int omap_i2c_xfer_msg(struct i2c_adapter *adap,
621621 struct i2c_msg *msg, int stop)
622622 {
623− struct omap_i2c_dev *dev = i2c_get_adapdata(adap);
623+ struct omap_i2c_dev *omap = i2c_get_adapdata(adap);
624624 unsigned long timeout;
625625 u16 w;
626626
627− dev_dbg(dev->dev, "addr: 0x%04x, len: %d, flags: 0x%x, stop: %d\n",
627+ dev_dbg(omap->dev, "addr: 0x%04x, len: %d, flags: 0x%x, stop: %d\n",
628628 msg->addr, msg->len, msg->flags, stop);
629629
630630 if (msg->len == 0)
631631 return -EINVAL;
632632
633− dev->receiver = !!(msg->flags & I2C_M_RD);
634− omap_i2c_resize_fifo(dev, msg->len, dev->receiver);
633+ omap->receiver = !!(msg->flags & I2C_M_RD);
634+ omap_i2c_resize_fifo(omap, msg->len, omap->receiver);
635635
636− omap_i2c_write_reg(dev, OMAP_I2C_SA_REG, msg->addr);
636+ omap_i2c_write_reg(omap, OMAP_I2C_SA_REG, msg->addr);
637637
638638 /* REVISIT: Could the STB bit of I2C_CON be used with probing? */
639− dev->buf = msg->buf;
640− dev->buf_len = msg->len;
639+ omap->buf = msg->buf;
640+ omap->buf_len = msg->len;
641641
642− /* make sure writes to dev->buf_len are ordered */
642+ /* make sure writes to omap->buf_len are ordered */
643643 barrier();
644644
645− omap_i2c_write_reg(dev, OMAP_I2C_CNT_REG, dev->buf_len);
645+ omap_i2c_write_reg(omap, OMAP_I2C_CNT_REG, omap->buf_len);
646646
647647 /* Clear the FIFO Buffers */
648− w = omap_i2c_read_reg(dev, OMAP_I2C_BUF_REG);
648+ w = omap_i2c_read_reg(omap, OMAP_I2C_BUF_REG);
649649 w |= OMAP_I2C_BUF_RXFIF_CLR | OMAP_I2C_BUF_TXFIF_CLR;
650− omap_i2c_write_reg(dev, OMAP_I2C_BUF_REG, w);
650+ omap_i2c_write_reg(omap, OMAP_I2C_BUF_REG, w);
651651
652− reinit_completion(&dev->cmd_complete);
653− dev->cmd_err = 0;
652+ reinit_completion(&omap->cmd_complete);
653+ omap->cmd_err = 0;
654654
655655 w = OMAP_I2C_CON_EN | OMAP_I2C_CON_MST | OMAP_I2C_CON_STT;
656656
657657 /* High speed configuration */
658− if (dev->speed > 400)
658+ if (omap->speed > 400)
659659 w |= OMAP_I2C_CON_OPMODE_HS;
660660
661661 if (msg->flags & I2C_M_STOP)
@@ -665,27 +665,27 @@ static int omap_i2c_xfer_msg(struct i2c_adapter *adap, · 3 unmodified lines
665665 if (!(msg->flags & I2C_M_RD))
666666 w |= OMAP_I2C_CON_TRX;
667667
668− if (!dev->b_hw && stop)
668+ if (!omap->b_hw && stop)
669669 w |= OMAP_I2C_CON_STP;
670670 /*
671671 * NOTE: STAT_BB bit could became 1 here if another master occupy
672672 * the bus. IP successfully complete transfer when the bus will be
673673 * free again (BB reset to 0).
674674 */
675− omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, w);
675+ omap_i2c_write_reg(omap, OMAP_I2C_CON_REG, w);
676676
677677 /*
678678 * Don't write stt and stp together on some hardware.
679679 */
680− if (dev->b_hw && stop) {
680+ if (omap->b_hw && stop) {
681681 unsigned long delay = jiffies + OMAP_I2C_TIMEOUT;
682− u16 con = omap_i2c_read_reg(dev, OMAP_I2C_CON_REG);
682+ u16 con = omap_i2c_read_reg(omap, OMAP_I2C_CON_REG);
683683 while (con & OMAP_I2C_CON_STT) {
684− con = omap_i2c_read_reg(dev, OMAP_I2C_CON_REG);
684+ con = omap_i2c_read_reg(omap, OMAP_I2C_CON_REG);
685685
686686 /* Let the user know if i2c is in a bad state */
687687 if (time_after(jiffies, delay)) {
688− dev_err(dev->dev, "controller timed out "
688+ dev_err(omap->dev, "controller timed out "
689689 "waiting for start condition to finish\n");
690690 return -ETIMEDOUT;
691691 }
@@ -694,42 +694,42 @@ static int omap_i2c_xfer_msg(struct i2c_adapter *adap, · 2 unmodified lines
694694
695695 w |= OMAP_I2C_CON_STP;
696696 w &= ~OMAP_I2C_CON_STT;
697− omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, w);
697+ omap_i2c_write_reg(omap, OMAP_I2C_CON_REG, w);
698698 }
699699
700700 /*
701701 * REVISIT: We should abort the transfer on signals, but the bus goes
702702 * into arbitration and we're currently unable to recover from it.
703703 */
704− timeout = wait_for_completion_timeout(&dev->cmd_complete,
704+ timeout = wait_for_completion_timeout(&omap->cmd_complete,
705705 OMAP_I2C_TIMEOUT);
706706 if (timeout == 0) {
707− dev_err(dev->dev, "controller timed out\n");
708− omap_i2c_reset(dev);
709− __omap_i2c_init(dev);
707+ dev_err(omap->dev, "controller timed out\n");
708+ omap_i2c_reset(omap);
709+ __omap_i2c_init(omap);
710710 return -ETIMEDOUT;
711711 }
712712
713− if (likely(!dev->cmd_err))
713+ if (likely(!omap->cmd_err))
714714 return 0;
715715
716716 /* We have an error */
717− if (dev->cmd_err & (OMAP_I2C_STAT_ROVR | OMAP_I2C_STAT_XUDF)) {
718− omap_i2c_reset(dev);
719− __omap_i2c_init(dev);
717+ if (omap->cmd_err & (OMAP_I2C_STAT_ROVR | OMAP_I2C_STAT_XUDF)) {
718+ omap_i2c_reset(omap);
719+ __omap_i2c_init(omap);
720720 return -EIO;
721721 }
722722
723− if (dev->cmd_err & OMAP_I2C_STAT_AL)
723+ if (omap->cmd_err & OMAP_I2C_STAT_AL)
724724 return -EAGAIN;
725725
726− if (dev->cmd_err & OMAP_I2C_STAT_NACK) {
726+ if (omap->cmd_err & OMAP_I2C_STAT_NACK) {
727727 if (msg->flags & I2C_M_IGNORE_NAK)
728728 return 0;
729729
730− w = omap_i2c_read_reg(dev, OMAP_I2C_CON_REG);
730+ w = omap_i2c_read_reg(omap, OMAP_I2C_CON_REG);
731731 w |= OMAP_I2C_CON_STP;
732− omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, w);
732+ omap_i2c_write_reg(omap, OMAP_I2C_CON_REG, w);
733733 return -EREMOTEIO;
734734 }
735735 return -EIO;
@@ -743,24 +743,24 @@ static int omap_i2c_xfer_msg(struct i2c_adapter *adap, · 7 unmodified lines
743743 static int
744744 omap_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num)
745745 {
746− struct omap_i2c_dev *dev = i2c_get_adapdata(adap);
746+ struct omap_i2c_dev *omap = i2c_get_adapdata(adap);
747747 int i;
748748 int r;
749749
750− r = pm_runtime_get_sync(dev->dev);
750+ r = pm_runtime_get_sync(omap->dev);
751751 if (r < 0)
752752 goto out;
753753
754− r = omap_i2c_wait_for_bb_valid(dev);
754+ r = omap_i2c_wait_for_bb_valid(omap);
755755 if (r < 0)
756756 goto out;
757757
758− r = omap_i2c_wait_for_bb(dev);
758+ r = omap_i2c_wait_for_bb(omap);
759759 if (r < 0)
760760 goto out;
761761
762− if (dev->set_mpu_wkup_lat != NULL)
763− dev->set_mpu_wkup_lat(dev->dev, dev->latency);
762+ if (omap->set_mpu_wkup_lat != NULL)
763+ omap->set_mpu_wkup_lat(omap->dev, omap->latency);
764764
765765 for (i = 0; i < num; i++) {
766766 r = omap_i2c_xfer_msg(adap, &msgs[i], (i == (num - 1)));
@@ -771,14 +771,14 @@ omap_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num) · 4 unmodified lines
771771 if (r == 0)
772772 r = num;
773773
774− omap_i2c_wait_for_bb(dev);
774+ omap_i2c_wait_for_bb(omap);
775775
776− if (dev->set_mpu_wkup_lat != NULL)
777− dev->set_mpu_wkup_lat(dev->dev, -1);
776+ if (omap->set_mpu_wkup_lat != NULL)
777+ omap->set_mpu_wkup_lat(omap->dev, -1);
778778
779779 out:
780− pm_runtime_mark_last_busy(dev->dev);
781− pm_runtime_put_autosuspend(dev->dev);
780+ pm_runtime_mark_last_busy(omap->dev);
781+ pm_runtime_put_autosuspend(omap->dev);
782782 return r;
783783 }
784784
@@ -790,19 +790,19 @@ omap_i2c_func(struct i2c_adapter *adap) · 5 unmodified lines
790790 }
791791
792792 static inline void
793−omap_i2c_complete_cmd(struct omap_i2c_dev *dev, u16 err)
793+omap_i2c_complete_cmd(struct omap_i2c_dev *omap, u16 err)
794794 {
795− dev->cmd_err |= err;
796− complete(&dev->cmd_complete);
795+ omap->cmd_err |= err;
796+ complete(&omap->cmd_complete);
797797 }
798798
799799 static inline void
800−omap_i2c_ack_stat(struct omap_i2c_dev *dev, u16 stat)
800+omap_i2c_ack_stat(struct omap_i2c_dev *omap, u16 stat)
801801 {
802− omap_i2c_write_reg(dev, OMAP_I2C_STAT_REG, stat);
802+ omap_i2c_write_reg(omap, OMAP_I2C_STAT_REG, stat);
803803 }
804804
805−static inline void i2c_omap_errata_i207(struct omap_i2c_dev *dev, u16 stat)
805+static inline void i2c_omap_errata_i207(struct omap_i2c_dev *omap, u16 stat)
806806 {
807807 /*
808808 * I2C Errata(Errata Nos. OMAP2: 1.67, OMAP3: 1.8)
@@ -813,17 +813,17 @@ static inline void i2c_omap_errata_i207(struct omap_i2c_dev *dev, u16 stat) · 4 unmodified lines
813813 */
814814 if (stat & OMAP_I2C_STAT_RDR) {
815815 /* Step 1: If RDR is set, clear it */
816− omap_i2c_ack_stat(dev, OMAP_I2C_STAT_RDR);
816+ omap_i2c_ack_stat(omap, OMAP_I2C_STAT_RDR);
817817
818818 /* Step 2: */
819− if (!(omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG)
819+ if (!(omap_i2c_read_reg(omap, OMAP_I2C_STAT_REG)
820820 & OMAP_I2C_STAT_BB)) {
821821
822822 /* Step 3: */
823− if (omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG)
823+ if (omap_i2c_read_reg(omap, OMAP_I2C_STAT_REG)
824824 & OMAP_I2C_STAT_RDR) {
825− omap_i2c_ack_stat(dev, OMAP_I2C_STAT_RDR);
826− dev_dbg(dev->dev, "RDR when bus is busy.\n");
825+ omap_i2c_ack_stat(omap, OMAP_I2C_STAT_RDR);
826+ dev_dbg(omap->dev, "RDR when bus is busy.\n");
827827 }
828828
829829 }
@@ -836,50 +836,50 @@ static inline void i2c_omap_errata_i207(struct omap_i2c_dev *dev, u16 stat) · 6 unmodified lines
836836 static irqreturn_t
837837 omap_i2c_omap1_isr(int this_irq, void *dev_id)
838838 {
839− struct omap_i2c_dev *dev = dev_id;
839+ struct omap_i2c_dev *omap = dev_id;
840840 u16 iv, w;
841841
842− if (pm_runtime_suspended(dev->dev))
842+ if (pm_runtime_suspended(omap->dev))
843843 return IRQ_NONE;
844844
845− iv = omap_i2c_read_reg(dev, OMAP_I2C_IV_REG);
845+ iv = omap_i2c_read_reg(omap, OMAP_I2C_IV_REG);
846846 switch (iv) {
847847 case 0x00: /* None */
848848 break;
849849 case 0x01: /* Arbitration lost */
850− dev_err(dev->dev, "Arbitration lost\n");
851− omap_i2c_complete_cmd(dev, OMAP_I2C_STAT_AL);
850+ dev_err(omap->dev, "Arbitration lost\n");
851+ omap_i2c_complete_cmd(omap, OMAP_I2C_STAT_AL);
852852 break;
853853 case 0x02: /* No acknowledgement */
854− omap_i2c_complete_cmd(dev, OMAP_I2C_STAT_NACK);
855− omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, OMAP_I2C_CON_STP);
854+ omap_i2c_complete_cmd(omap, OMAP_I2C_STAT_NACK);
855+ omap_i2c_write_reg(omap, OMAP_I2C_CON_REG, OMAP_I2C_CON_STP);
856856 break;
857857 case 0x03: /* Register access ready */
858− omap_i2c_complete_cmd(dev, 0);
858+ omap_i2c_complete_cmd(omap, 0);
859859 break;
860860 case 0x04: /* Receive data ready */
861− if (dev->buf_len) {
862− w = omap_i2c_read_reg(dev, OMAP_I2C_DATA_REG);
863− *dev->buf++ = w;
864− dev->buf_len--;
865− if (dev->buf_len) {
866− *dev->buf++ = w >> 8;
867− dev->buf_len--;
861+ if (omap->buf_len) {
862+ w = omap_i2c_read_reg(omap, OMAP_I2C_DATA_REG);
863+ *omap->buf++ = w;
864+ omap->buf_len--;
865+ if (omap->buf_len) {
866+ *omap->buf++ = w >> 8;
867+ omap->buf_len--;
868868 }
869869 } else
870− dev_err(dev->dev, "RRDY IRQ while no data requested\n");
870+ dev_err(omap->dev, "RRDY IRQ while no data requested\n");
871871 break;
872872 case 0x05: /* Transmit data ready */
873− if (dev->buf_len) {
874− w = *dev->buf++;
875− dev->buf_len--;
876− if (dev->buf_len) {
877− w |= *dev->buf++ << 8;
878− dev->buf_len--;
873+ if (omap->buf_len) {
874+ w = *omap->buf++;
875+ omap->buf_len--;
876+ if (omap->buf_len) {
877+ w |= *omap->buf++ << 8;
878+ omap->buf_len--;
879879 }
880− omap_i2c_write_reg(dev, OMAP_I2C_DATA_REG, w);
880+ omap_i2c_write_reg(omap, OMAP_I2C_DATA_REG, w);
881881 } else
882− dev_err(dev->dev, "XRDY IRQ while no data to send\n");
882+ dev_err(omap->dev, "XRDY IRQ while no data to send\n");
883883 break;
884884 default:
885885 return IRQ_NONE;
@@ -896,28 +896,28 @@ omap_i2c_omap1_isr(int this_irq, void *dev_id) · 10 unmodified lines
896896 * data to DATA_REG. Otherwise some data bytes can be lost while transferring
897897 * them from the memory to the I2C interface.
898898 */
899−static int errata_omap3_i462(struct omap_i2c_dev *dev)
899+static int errata_omap3_i462(struct omap_i2c_dev *omap)
900900 {
901901 unsigned long timeout = 10000;
902902 u16 stat;
903903
904904 do {
905− stat = omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG);
905+ stat = omap_i2c_read_reg(omap, OMAP_I2C_STAT_REG);
906906 if (stat & OMAP_I2C_STAT_XUDF)
907907 break;
908908
909909 if (stat & (OMAP_I2C_STAT_NACK | OMAP_I2C_STAT_AL)) {
910− omap_i2c_ack_stat(dev, (OMAP_I2C_STAT_XRDY |
910+ omap_i2c_ack_stat(omap, (OMAP_I2C_STAT_XRDY |
911911 OMAP_I2C_STAT_XDR));
912912 if (stat & OMAP_I2C_STAT_NACK) {
913− dev->cmd_err |= OMAP_I2C_STAT_NACK;
914− omap_i2c_ack_stat(dev, OMAP_I2C_STAT_NACK);
913+ omap->cmd_err |= OMAP_I2C_STAT_NACK;
914+ omap_i2c_ack_stat(omap, OMAP_I2C_STAT_NACK);
915915 }
916916
917917 if (stat & OMAP_I2C_STAT_AL) {
918− dev_err(dev->dev, "Arbitration lost\n");
919− dev->cmd_err |= OMAP_I2C_STAT_AL;
920− omap_i2c_ack_stat(dev, OMAP_I2C_STAT_AL);
918+ dev_err(omap->dev, "Arbitration lost\n");
919+ omap->cmd_err |= OMAP_I2C_STAT_AL;
920+ omap_i2c_ack_stat(omap, OMAP_I2C_STAT_AL);
921921 }
922922
923923 return -EIO;
@@ -927,61 +927,61 @@ static int errata_omap3_i462(struct omap_i2c_dev *dev) · 3 unmodified lines
927927 } while (--timeout);
928928
929929 if (!timeout) {
930− dev_err(dev->dev, "timeout waiting on XUDF bit\n");
930+ dev_err(omap->dev, "timeout waiting on XUDF bit\n");
931931 return 0;
932932 }
933933
934934 return 0;
935935 }
936936
937−static void omap_i2c_receive_data(struct omap_i2c_dev *dev, u8 num_bytes,
937+static void omap_i2c_receive_data(struct omap_i2c_dev *omap, u8 num_bytes,
938938 bool is_rdr)
939939 {
940940 u16 w;
941941
942942 while (num_bytes--) {
943− w = omap_i2c_read_reg(dev, OMAP_I2C_DATA_REG);
944− *dev->buf++ = w;
945− dev->buf_len--;
943+ w = omap_i2c_read_reg(omap, OMAP_I2C_DATA_REG);
944+ *omap->buf++ = w;
945+ omap->buf_len--;
946946
947947 /*
948948 * Data reg in 2430, omap3 and
949949 * omap4 is 8 bit wide
950950 */
951− if (dev->flags & OMAP_I2C_FLAG_16BIT_DATA_REG) {
952− *dev->buf++ = w >> 8;
953− dev->buf_len--;
951+ if (omap->flags & OMAP_I2C_FLAG_16BIT_DATA_REG) {
952+ *omap->buf++ = w >> 8;
953+ omap->buf_len--;
954954 }
955955 }
956956 }
957957
958−static int omap_i2c_transmit_data(struct omap_i2c_dev *dev, u8 num_bytes,
958+static int omap_i2c_transmit_data(struct omap_i2c_dev *omap, u8 num_bytes,
959959 bool is_xdr)
960960 {
961961 u16 w;
962962
963963 while (num_bytes--) {
964− w = *dev->buf++;
965− dev->buf_len--;
964+ w = *omap->buf++;
965+ omap->buf_len--;
966966
967967 /*
968968 * Data reg in 2430, omap3 and
969969 * omap4 is 8 bit wide
970970 */
971− if (dev->flags & OMAP_I2C_FLAG_16BIT_DATA_REG) {
972− w |= *dev->buf++ << 8;
973− dev->buf_len--;
971+ if (omap->flags & OMAP_I2C_FLAG_16BIT_DATA_REG) {
972+ w |= *omap->buf++ << 8;
973+ omap->buf_len--;
974974 }
975975
976− if (dev->errata & I2C_OMAP_ERRATA_I462) {
976+ if (omap->errata & I2C_OMAP_ERRATA_I462) {
977977 int ret;
978978
979− ret = errata_omap3_i462(dev);
979+ ret = errata_omap3_i462(omap);
980980 if (ret < 0)
981981 return ret;
982982 }
983983
984− omap_i2c_write_reg(dev, OMAP_I2C_DATA_REG, w);
984+ omap_i2c_write_reg(omap, OMAP_I2C_DATA_REG, w);
985985 }
986986
987987 return 0;
@@ -990,19 +990,19 @@ static int omap_i2c_transmit_data(struct omap_i2c_dev *dev, u8 num_bytes, · 2 unmodified lines
990990 static irqreturn_t
991991 omap_i2c_isr(int irq, void *dev_id)
992992 {
993− struct omap_i2c_dev *dev = dev_id;
993+ struct omap_i2c_dev *omap = dev_id;
994994 irqreturn_t ret = IRQ_HANDLED;
995995 u16 mask;
996996 u16 stat;
997997
998− spin_lock(&dev->lock);
999− mask = omap_i2c_read_reg(dev, OMAP_I2C_IE_REG);
1000− stat = omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG);
998+ spin_lock(&omap->lock);
999+ mask = omap_i2c_read_reg(omap, OMAP_I2C_IE_REG);
1000+ stat = omap_i2c_read_reg(omap, OMAP_I2C_STAT_REG);
10011001
10021002 if (stat & mask)
10031003 ret = IRQ_WAKE_THREAD;
10041004
1005− spin_unlock(&dev->lock);
1005+ spin_unlock(&omap->lock);
10061006
10071007 return ret;
10081008 }
@@ -1010,20 +1010,20 @@ omap_i2c_isr(int irq, void *dev_id) · 1 unmodified line
10101010 static irqreturn_t
10111011 omap_i2c_isr_thread(int this_irq, void *dev_id)
10121012 {
1013− struct omap_i2c_dev *dev = dev_id;
1013+ struct omap_i2c_dev *omap = dev_id;
10141014 unsigned long flags;
10151015 u16 bits;
10161016 u16 stat;
10171017 int err = 0, count = 0;
10181018
1019− spin_lock_irqsave(&dev->lock, flags);
1019+ spin_lock_irqsave(&omap->lock, flags);
10201020 do {
1021− bits = omap_i2c_read_reg(dev, OMAP_I2C_IE_REG);
1022− stat = omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG);
1021+ bits = omap_i2c_read_reg(omap, OMAP_I2C_IE_REG);
1022+ stat = omap_i2c_read_reg(omap, OMAP_I2C_STAT_REG);
10231023 stat &= bits;
10241024
10251025 /* If we're in receiver mode, ignore XDR/XRDY */
1026− if (dev->receiver)
1026+ if (omap->receiver)
10271027 stat &= ~(OMAP_I2C_STAT_XDR | OMAP_I2C_STAT_XRDY);
10281028 else
10291029 stat &= ~(OMAP_I2C_STAT_RDR | OMAP_I2C_STAT_RRDY);
@@ -1033,32 +1033,32 @@ omap_i2c_isr_thread(int this_irq, void *dev_id) · 3 unmodified lines
10331033 goto out;
10341034 }
10351035
1036− dev_dbg(dev->dev, "IRQ (ISR = 0x%04x)\n", stat);
1036+ dev_dbg(omap->dev, "IRQ (ISR = 0x%04x)\n", stat);
10371037 if (count++ == 100) {
1038− dev_warn(dev->dev, "Too much work in one IRQ\n");
1038+ dev_warn(omap->dev, "Too much work in one IRQ\n");
10391039 break;
10401040 }
10411041
10421042 if (stat & OMAP_I2C_STAT_NACK) {
10431043 err |= OMAP_I2C_STAT_NACK;
1044− omap_i2c_ack_stat(dev, OMAP_I2C_STAT_NACK);
1044+ omap_i2c_ack_stat(omap, OMAP_I2C_STAT_NACK);
10451045 }
10461046
10471047 if (stat & OMAP_I2C_STAT_AL) {
1048− dev_err(dev->dev, "Arbitration lost\n");
1048+ dev_err(omap->dev, "Arbitration lost\n");
10491049 err |= OMAP_I2C_STAT_AL;
1050− omap_i2c_ack_stat(dev, OMAP_I2C_STAT_AL);
1050+ omap_i2c_ack_stat(omap, OMAP_I2C_STAT_AL);
10511051 }
10521052
10531053 /*
10541054 * ProDB0017052: Clear ARDY bit twice
10551055 */
10561056 if (stat & OMAP_I2C_STAT_ARDY)
1057− omap_i2c_ack_stat(dev, OMAP_I2C_STAT_ARDY);
1057+ omap_i2c_ack_stat(omap, OMAP_I2C_STAT_ARDY);
10581058
10591059 if (stat & (OMAP_I2C_STAT_ARDY | OMAP_I2C_STAT_NACK |
10601060 OMAP_I2C_STAT_AL)) {
1061− omap_i2c_ack_stat(dev, (OMAP_I2C_STAT_RRDY |
1061+ omap_i2c_ack_stat(omap, (OMAP_I2C_STAT_RRDY |
10621062 OMAP_I2C_STAT_RDR |
10631063 OMAP_I2C_STAT_XRDY |
10641064 OMAP_I2C_STAT_XDR |
@@ -1069,28 +1069,28 @@ omap_i2c_isr_thread(int this_irq, void *dev_id) · 4 unmodified lines
10691069 if (stat & OMAP_I2C_STAT_RDR) {
10701070 u8 num_bytes = 1;
10711071
1072− if (dev->fifo_size)
1073− num_bytes = dev->buf_len;
1072+ if (omap->fifo_size)
1073+ num_bytes = omap->buf_len;
10741074
1075− if (dev->errata & I2C_OMAP_ERRATA_I207) {
1076− i2c_omap_errata_i207(dev, stat);
1077− num_bytes = (omap_i2c_read_reg(dev,
1075+ if (omap->errata & I2C_OMAP_ERRATA_I207) {
1076+ i2c_omap_errata_i207(omap, stat);
1077+ num_bytes = (omap_i2c_read_reg(omap,
10781078 OMAP_I2C_BUFSTAT_REG) >> 8) & 0x3F;
10791079 }
10801080
1081− omap_i2c_receive_data(dev, num_bytes, true);
1082− omap_i2c_ack_stat(dev, OMAP_I2C_STAT_RDR);
1081+ omap_i2c_receive_data(omap, num_bytes, true);
1082+ omap_i2c_ack_stat(omap, OMAP_I2C_STAT_RDR);
10831083 continue;
10841084 }
10851085
10861086 if (stat & OMAP_I2C_STAT_RRDY) {
10871087 u8 num_bytes = 1;
10881088
1089− if (dev->threshold)
1090− num_bytes = dev->threshold;
1089+ if (omap->threshold)
1090+ num_bytes = omap->threshold;
10911091
1092− omap_i2c_receive_data(dev, num_bytes, false);
1093− omap_i2c_ack_stat(dev, OMAP_I2C_STAT_RRDY);
1092+ omap_i2c_receive_data(omap, num_bytes, false);
1093+ omap_i2c_ack_stat(omap, OMAP_I2C_STAT_RRDY);
10941094 continue;
10951095 }
10961096
@@ -1098,14 +1098,14 @@ omap_i2c_isr_thread(int this_irq, void *dev_id) · 1 unmodified line
10981098 u8 num_bytes = 1;
10991099 int ret;
11001100
1101− if (dev->fifo_size)
1102− num_bytes = dev->buf_len;
1101+ if (omap->fifo_size)
1102+ num_bytes = omap->buf_len;
11031103
1104− ret = omap_i2c_transmit_data(dev, num_bytes, true);
1104+ ret = omap_i2c_transmit_data(omap, num_bytes, true);
11051105 if (ret < 0)
11061106 break;
11071107
1108− omap_i2c_ack_stat(dev, OMAP_I2C_STAT_XDR);
1108+ omap_i2c_ack_stat(omap, OMAP_I2C_STAT_XDR);
11091109 continue;
11101110 }
11111111
@@ -1113,36 +1113,36 @@ omap_i2c_isr_thread(int this_irq, void *dev_id) · 1 unmodified line
11131113 u8 num_bytes = 1;
11141114 int ret;
11151115
1116− if (dev->threshold)
1117− num_bytes = dev->threshold;
1116+ if (omap->threshold)
1117+ num_bytes = omap->threshold;
11181118
1119− ret = omap_i2c_transmit_data(dev, num_bytes, false);
1119+ ret = omap_i2c_transmit_data(omap, num_bytes, false);
11201120 if (ret < 0)
11211121 break;
11221122
1123− omap_i2c_ack_stat(dev, OMAP_I2C_STAT_XRDY);
1123+ omap_i2c_ack_stat(omap, OMAP_I2C_STAT_XRDY);
11241124 continue;
11251125 }
11261126
11271127 if (stat & OMAP_I2C_STAT_ROVR) {
1128− dev_err(dev->dev, "Receive overrun\n");
1128+ dev_err(omap->dev, "Receive overrun\n");
11291129 err |= OMAP_I2C_STAT_ROVR;
1130− omap_i2c_ack_stat(dev, OMAP_I2C_STAT_ROVR);
1130+ omap_i2c_ack_stat(omap, OMAP_I2C_STAT_ROVR);
11311131 break;
11321132 }
11331133
11341134 if (stat & OMAP_I2C_STAT_XUDF) {
1135− dev_err(dev->dev, "Transmit underflow\n");
1135+ dev_err(omap->dev, "Transmit underflow\n");
11361136 err |= OMAP_I2C_STAT_XUDF;
1137− omap_i2c_ack_stat(dev, OMAP_I2C_STAT_XUDF);
1137+ omap_i2c_ack_stat(omap, OMAP_I2C_STAT_XUDF);
11381138 break;
11391139 }
11401140 } while (stat);
11411141
1142− omap_i2c_complete_cmd(dev, err);
1142+ omap_i2c_complete_cmd(omap, err);
11431143
11441144 out:
1145− spin_unlock_irqrestore(&dev->lock, flags);
1145+ spin_unlock_irqrestore(&omap->lock, flags);
11461146
11471147 return IRQ_HANDLED;
11481148 }
@@ -1284,7 +1284,7 @@ static struct i2c_bus_recovery_info omap_i2c_bus_recovery_info = { · 135 unmodified lines
12841284 static int
12851285 omap_i2c_probe(struct platform_device *pdev)
12861286 {
1287− struct omap_i2c_dev *dev;
1287+ struct omap_i2c_dev *omap;
12881288 struct i2c_adapter *adap;
12891289 struct resource *mem;
12901290 const struct omap_i2c_bus_platform_data *pdata =
@@ -1302,46 +1302,46 @@ omap_i2c_probe(struct platform_device *pdev) · 11 unmodified lines
13021302 return irq;
13031303 }
13041304
1305− dev = devm_kzalloc(&pdev->dev, sizeof(struct omap_i2c_dev), GFP_KERNEL);
1306− if (!dev)
1305+ omap = devm_kzalloc(&pdev->dev, sizeof(struct omap_i2c_dev), GFP_KERNEL);
1306+ if (!omap)
13071307 return -ENOMEM;
13081308
13091309 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1310− dev->base = devm_ioremap_resource(&pdev->dev, mem);
1311− if (IS_ERR(dev->base))
1312− return PTR_ERR(dev->base);
1310+ omap->base = devm_ioremap_resource(&pdev->dev, mem);
1311+ if (IS_ERR(omap->base))
1312+ return PTR_ERR(omap->base);
13131313
13141314 match = of_match_device(of_match_ptr(omap_i2c_of_match), &pdev->dev);
13151315 if (match) {
13161316 u32 freq = 100000; /* default to 100000 Hz */
13171317
13181318 pdata = match->data;
1319− dev->flags = pdata->flags;
1319+ omap->flags = pdata->flags;
13201320
13211321 of_property_read_u32(node, "clock-frequency", &freq);
13221322 /* convert DT freq value in Hz into kHz for speed */
1323− dev->speed = freq / 1000;
1323+ omap->speed = freq / 1000;
13241324 } else if (pdata != NULL) {
1325− dev->speed = pdata->clkrate;
1326− dev->flags = pdata->flags;
1327− dev->set_mpu_wkup_lat = pdata->set_mpu_wkup_lat;
1325+ omap->speed = pdata->clkrate;
1326+ omap->flags = pdata->flags;
1327+ omap->set_mpu_wkup_lat = pdata->set_mpu_wkup_lat;
13281328 }
13291329
1330− dev->dev = &pdev->dev;
1331− dev->irq = irq;
1330+ omap->dev = &pdev->dev;
1331+ omap->irq = irq;
13321332
1333− spin_lock_init(&dev->lock);
1333+ spin_lock_init(&omap->lock);
13341334
1335− platform_set_drvdata(pdev, dev);
1336− init_completion(&dev->cmd_complete);
1335+ platform_set_drvdata(pdev, omap);
1336+ init_completion(&omap->cmd_complete);
13371337
1338− dev->reg_shift = (dev->flags >> OMAP_I2C_FLAG_BUS_SHIFT__SHIFT) & 3;
1338+ omap->reg_shift = (omap->flags >> OMAP_I2C_FLAG_BUS_SHIFT__SHIFT) & 3;
13391339
1340− pm_runtime_enable(dev->dev);
1341− pm_runtime_set_autosuspend_delay(dev->dev, OMAP_I2C_PM_TIMEOUT);
1342− pm_runtime_use_autosuspend(dev->dev);
1340+ pm_runtime_enable(omap->dev);
1341+ pm_runtime_set_autosuspend_delay(omap->dev, OMAP_I2C_PM_TIMEOUT);
1342+ pm_runtime_use_autosuspend(omap->dev);
13431343
1344− r = pm_runtime_get_sync(dev->dev);
1344+ r = pm_runtime_get_sync(omap->dev);
13451345 if (r < 0)
13461346 goto err_free_mem;
13471347
@@ -1351,42 +1351,42 @@ omap_i2c_probe(struct platform_device *pdev) · 3 unmodified lines
13511351 * Also since the omap_i2c_read_reg uses reg_map_ip_* a
13521352 * readw_relaxed is done.
13531353 */
1354− rev = readw_relaxed(dev->base + 0x04);
1354+ rev = readw_relaxed(omap->base + 0x04);
13551355
1356− dev->scheme = OMAP_I2C_SCHEME(rev);
1357− switch (dev->scheme) {
1356+ omap->scheme = OMAP_I2C_SCHEME(rev);
1357+ switch (omap->scheme) {
13581358 case OMAP_I2C_SCHEME_0:
1359− dev->regs = (u8 *)reg_map_ip_v1;
1360− dev->rev = omap_i2c_read_reg(dev, OMAP_I2C_REV_REG);
1361− minor = OMAP_I2C_REV_SCHEME_0_MAJOR(dev->rev);
1362− major = OMAP_I2C_REV_SCHEME_0_MAJOR(dev->rev);
1359+ omap->regs = (u8 *)reg_map_ip_v1;
1360+ omap->rev = omap_i2c_read_reg(omap, OMAP_I2C_REV_REG);
1361+ minor = OMAP_I2C_REV_SCHEME_0_MAJOR(omap->rev);
1362+ major = OMAP_I2C_REV_SCHEME_0_MAJOR(omap->rev);
13631363 break;
13641364 case OMAP_I2C_SCHEME_1:
13651365 /* FALLTHROUGH */
13661366 default:
1367− dev->regs = (u8 *)reg_map_ip_v2;
1367+ omap->regs = (u8 *)reg_map_ip_v2;
13681368 rev = (rev << 16) |
1369− omap_i2c_read_reg(dev, OMAP_I2C_IP_V2_REVNB_LO);
1369+ omap_i2c_read_reg(omap, OMAP_I2C_IP_V2_REVNB_LO);
13701370 minor = OMAP_I2C_REV_SCHEME_1_MINOR(rev);
13711371 major = OMAP_I2C_REV_SCHEME_1_MAJOR(rev);
1372− dev->rev = rev;
1372+ omap->rev = rev;
13731373 }
13741374
1375− dev->errata = 0;
1375+ omap->errata = 0;
13761376
1377− if (dev->rev >= OMAP_I2C_REV_ON_2430 &&
1378− dev->rev < OMAP_I2C_REV_ON_4430_PLUS)
1379− dev->errata |= I2C_OMAP_ERRATA_I207;
1377+ if (omap->rev >= OMAP_I2C_REV_ON_2430 &&
1378+ omap->rev < OMAP_I2C_REV_ON_4430_PLUS)
1379+ omap->errata |= I2C_OMAP_ERRATA_I207;
13801380
1381− if (dev->rev <= OMAP_I2C_REV_ON_3430_3530)
1382− dev->errata |= I2C_OMAP_ERRATA_I462;
1381+ if (omap->rev <= OMAP_I2C_REV_ON_3430_3530)
1382+ omap->errata |= I2C_OMAP_ERRATA_I462;
13831383
1384− if (!(dev->flags & OMAP_I2C_FLAG_NO_FIFO)) {
1384+ if (!(omap->flags & OMAP_I2C_FLAG_NO_FIFO)) {
13851385 u16 s;
13861386
13871387 /* Set up the fifo size - Get total size */
1388− s = (omap_i2c_read_reg(dev, OMAP_I2C_BUFSTAT_REG) >> 14) & 0x3;
1389− dev->fifo_size = 0x8 << s;
1388+ s = (omap_i2c_read_reg(omap, OMAP_I2C_BUFSTAT_REG) >> 14) & 0x3;
1389+ omap->fifo_size = 0x8 << s;
13901390
13911391 /*
13921392 * Set up notification threshold as half the total available
@@ -1394,36 +1394,36 @@ omap_i2c_probe(struct platform_device *pdev) · 1 unmodified line
13941394 * call back latencies.
13951395 */
13961396
1397− dev->fifo_size = (dev->fifo_size / 2);
1397+ omap->fifo_size = (omap->fifo_size / 2);
13981398
1399− if (dev->rev < OMAP_I2C_REV_ON_3630)
1400− dev->b_hw = 1; /* Enable hardware fixes */
1399+ if (omap->rev < OMAP_I2C_REV_ON_3630)
1400+ omap->b_hw = 1; /* Enable hardware fixes */
14011401
14021402 /* calculate wakeup latency constraint for MPU */
1403− if (dev->set_mpu_wkup_lat != NULL)
1404− dev->latency = (1000000 * dev->fifo_size) /
1405− (1000 * dev->speed / 8);
1403+ if (omap->set_mpu_wkup_lat != NULL)
1404+ omap->latency = (1000000 * omap->fifo_size) /
1405+ (1000 * omap->speed / 8);
14061406 }
14071407
14081408 /* reset ASAP, clearing any IRQs */
1409− omap_i2c_init(dev);
1409+ omap_i2c_init(omap);
14101410
1411− if (dev->rev < OMAP_I2C_OMAP1_REV_2)
1412− r = devm_request_irq(&pdev->dev, dev->irq, omap_i2c_omap1_isr,
1413− IRQF_NO_SUSPEND, pdev->name, dev);
1411+ if (omap->rev < OMAP_I2C_OMAP1_REV_2)
1412+ r = devm_request_irq(&pdev->dev, omap->irq, omap_i2c_omap1_isr,
1413+ IRQF_NO_SUSPEND, pdev->name, omap);
14141414 else
1415− r = devm_request_threaded_irq(&pdev->dev, dev->irq,
1415+ r = devm_request_threaded_irq(&pdev->dev, omap->irq,
14161416 omap_i2c_isr, omap_i2c_isr_thread,
14171417 IRQF_NO_SUSPEND | IRQF_ONESHOT,
1418− pdev->name, dev);
1418+ pdev->name, omap);
14191419
14201420 if (r) {
1421− dev_err(dev->dev, "failure requesting irq %i\n", dev->irq);
1421+ dev_err(omap->dev, "failure requesting irq %i\n", omap->irq);
14221422 goto err_unuse_clocks;
14231423 }
14241424
1425− adap = &dev->adapter;
1426− i2c_set_adapdata(adap, dev);
1425+ adap = &omap->adapter;
1426+ i2c_set_adapdata(adap, omap);
14271427 adap->owner = THIS_MODULE;
14281428 adap->class = I2C_CLASS_DEPRECATED;
14291429 strlcpy(adap->name, "OMAP I2C adapter", sizeof(adap->name));
@@ -1436,21 +1436,21 @@ omap_i2c_probe(struct platform_device *pdev) · 6 unmodified lines
14361436 adap->nr = pdev->id;
14371437 r = i2c_add_numbered_adapter(adap);
14381438 if (r) {
1439− dev_err(dev->dev, "failure adding adapter\n");
1439+ dev_err(omap->dev, "failure adding adapter\n");
14401440 goto err_unuse_clocks;
14411441 }
14421442
1443− dev_info(dev->dev, "bus %d rev%d.%d at %d kHz\n", adap->nr,
1444− major, minor, dev->speed);
1443+ dev_info(omap->dev, "bus %d rev%d.%d at %d kHz\n", adap->nr,
1444+ major, minor, omap->speed);
14451445
1446− pm_runtime_mark_last_busy(dev->dev);
1447− pm_runtime_put_autosuspend(dev->dev);
1446+ pm_runtime_mark_last_busy(omap->dev);
1447+ pm_runtime_put_autosuspend(omap->dev);
14481448
14491449 return 0;
14501450
14511451 err_unuse_clocks:
1452− omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, 0);
1453− pm_runtime_put(dev->dev);
1452+ omap_i2c_write_reg(omap, OMAP_I2C_CON_REG, 0);
1453+ pm_runtime_put(omap->dev);
14541454 pm_runtime_disable(&pdev->dev);
14551455 err_free_mem:
14561456
@@ -1459,16 +1459,16 @@ err_free_mem: · 2 unmodified lines
14591459
14601460 static int omap_i2c_remove(struct platform_device *pdev)
14611461 {
1462− struct omap_i2c_dev *dev = platform_get_drvdata(pdev);
1462+ struct omap_i2c_dev *omap = platform_get_drvdata(pdev);
14631463 int ret;
14641464
1465− i2c_del_adapter(&dev->adapter);
1465+ i2c_del_adapter(&omap->adapter);
14661466 ret = pm_runtime_get_sync(&pdev->dev);
14671467 if (ret < 0)
14681468 return ret;
14691469
1470− omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, 0);
1471− pm_runtime_put(&pdev->dev);
1470+ omap_i2c_write_reg(omap, OMAP_I2C_CON_REG, 0);
1471+ pm_runtime_put_sync(&pdev->dev);
14721472 pm_runtime_disable(&pdev->dev);
14731473 return 0;
14741474 }
@@ -1476,24 +1476,23 @@ static int omap_i2c_remove(struct platform_device *pdev) · 1 unmodified line
14761476 #ifdef CONFIG_PM
14771477 static int omap_i2c_runtime_suspend(struct device *dev)
14781478 {
1479− struct platform_device *pdev = to_platform_device(dev);
1480− struct omap_i2c_dev *_dev = platform_get_drvdata(pdev);
1479+ struct omap_i2c_dev *omap = dev_get_drvdata(dev);
14811480
1482− _dev->iestate = omap_i2c_read_reg(_dev, OMAP_I2C_IE_REG);
1481+ omap->iestate = omap_i2c_read_reg(omap, OMAP_I2C_IE_REG);
14831482
1484− if (_dev->scheme == OMAP_I2C_SCHEME_0)
1485− omap_i2c_write_reg(_dev, OMAP_I2C_IE_REG, 0);
1483+ if (omap->scheme == OMAP_I2C_SCHEME_0)
1484+ omap_i2c_write_reg(omap, OMAP_I2C_IE_REG, 0);
14861485 else
1487− omap_i2c_write_reg(_dev, OMAP_I2C_IP_V2_IRQENABLE_CLR,
1486+ omap_i2c_write_reg(omap, OMAP_I2C_IP_V2_IRQENABLE_CLR,
14881487 OMAP_I2C_IP_V2_INTERRUPTS_MASK);
14891488
1490− if (_dev->rev < OMAP_I2C_OMAP1_REV_2) {
1491− omap_i2c_read_reg(_dev, OMAP_I2C_IV_REG); /* Read clears */
1489+ if (omap->rev < OMAP_I2C_OMAP1_REV_2) {
1490+ omap_i2c_read_reg(omap, OMAP_I2C_IV_REG); /* Read clears */
14921491 } else {
1493− omap_i2c_write_reg(_dev, OMAP_I2C_STAT_REG, _dev->iestate);
1492+ omap_i2c_write_reg(omap, OMAP_I2C_STAT_REG, omap->iestate);
14941493
14951494 /* Flush posted write */
1496− omap_i2c_read_reg(_dev, OMAP_I2C_STAT_REG);
1495+ omap_i2c_read_reg(omap, OMAP_I2C_STAT_REG);
14971496 }
14981497
14991498 pinctrl_pm_select_sleep_state(dev);
@@ -1503,15 +1502,14 @@ static int omap_i2c_runtime_suspend(struct device *dev) · 3 unmodified lines
15031502
15041503 static int omap_i2c_runtime_resume(struct device *dev)
15051504 {
1506− struct platform_device *pdev = to_platform_device(dev);
1507− struct omap_i2c_dev *_dev = platform_get_drvdata(pdev);
1505+ struct omap_i2c_dev *omap = dev_get_drvdata(dev);
15081506
15091507 pinctrl_pm_select_default_state(dev);
15101508
1511− if (!_dev->regs)
1509+ if (!omap->regs)
15121510 return 0;
15131511
1514− __omap_i2c_init(_dev);
1512+ __omap_i2c_init(omap);
15151513
15161514 return 0;
15171515 }
drivers/i2c/busses/i2c-parport.c+13−12
@@ -20,6 +20,8 @@ · 19 unmodified lines
2020 GNU General Public License for more details.
2121 * ------------------------------------------------------------------------ */
2222
23+#define pr_fmt(fmt) "i2c-parport: " fmt
24+
2325 #include <linux/kernel.h>
2426 #include <linux/module.h>
2527 #include <linux/init.h>
@@ -176,26 +178,24 @@ static void i2c_parport_attach(struct parport *port) · 150 unmodified lines
176178 break;
177179 }
178180 if (i == MAX_DEVICE) {
179− pr_debug("i2c-parport: Not using parport%d.\n", port->number);
181+ pr_debug("Not using parport%d.\n", port->number);
180182 return;
181183 }
182184
183185 adapter = kzalloc(sizeof(struct i2c_par), GFP_KERNEL);
184− if (adapter == NULL) {
185− printk(KERN_ERR "i2c-parport: Failed to kzalloc\n");
186+ if (!adapter)
186187 return;
187− }
188188 memset(&i2c_parport_cb, 0, sizeof(i2c_parport_cb));
189189 i2c_parport_cb.flags = PARPORT_FLAG_EXCL;
190190 i2c_parport_cb.irq_func = i2c_parport_irq;
191191 i2c_parport_cb.private = adapter;
192192
193− pr_debug("i2c-parport: attaching to %s\n", port->name);
193+ pr_debug("attaching to %s\n", port->name);
194194 parport_disable_irq(port);
195195 adapter->pdev = parport_register_dev_model(port, "i2c-parport",
196196 &i2c_parport_cb, i);
197197 if (!adapter->pdev) {
198− printk(KERN_ERR "i2c-parport: Unable to register with parport\n");
198+ pr_err("Unable to register with parport\n");
199199 goto err_free;
200200 }
201201
@@ -215,7 +215,8 @@ static void i2c_parport_attach(struct parport *port) · 13 unmodified lines
215215 adapter->adapter.dev.parent = port->physport->dev;
216216
217217 if (parport_claim_or_block(adapter->pdev) < 0) {
218− printk(KERN_ERR "i2c-parport: Could not claim parallel port\n");
218+ dev_err(&adapter->pdev->dev,
219+ "Could not claim parallel port\n");
219220 goto err_unregister;
220221 }
221222
@@ -230,7 +231,7 @@ static void i2c_parport_attach(struct parport *port) · 8 unmodified lines
230231 }
231232
232233 if (i2c_bit_add_bus(&adapter->adapter) < 0) {
233− printk(KERN_ERR "i2c-parport: Unable to register with I2C\n");
234+ dev_err(&adapter->pdev->dev, "Unable to register with I2C\n");
234235 goto err_unregister;
235236 }
236237
@@ -242,8 +243,8 @@ static void i2c_parport_attach(struct parport *port) · 5 unmodified lines
242243 if (adapter->ara)
243244 parport_enable_irq(port);
244245 else
245− printk(KERN_WARNING "i2c-parport: Failed to register "
246− "ARA client\n");
246+ dev_warn(&adapter->pdev->dev,
247+ "Failed to register ARA client\n");
247248 }
248249
249250 /* Add the new adapter to the list */
@@ -298,12 +299,12 @@ static struct parport_driver i2c_parport_driver = { · 48 unmodified lines
298299 static int __init i2c_parport_init(void)
299300 {
300301 if (type < 0) {
301− printk(KERN_WARNING "i2c-parport: adapter type unspecified\n");
302+ pr_warn("adapter type unspecified\n");
302303 return -ENODEV;
303304 }
304305
305306 if (type >= ARRAY_SIZE(adapter_parm)) {
306− printk(KERN_WARNING "i2c-parport: invalid type (%d)\n", type);
307+ pr_warn("invalid type (%d)\n", type);
307308 return -ENODEV;
308309 }
309310
drivers/i2c/busses/i2c-parport.h+8−0
@@ -89,6 +89,13 @@ static const struct adapter_parm adapter_parm[] = { · 88 unmodified lines
8989 .getsda = { 0x80, PORT_STAT, 1 },
9090 .init = { 0x04, PORT_DATA, 1 },
9191 },
92+ /* type 8: VCT-jig */
93+ {
94+ .setsda = { 0x04, PORT_DATA, 1 },
95+ .setscl = { 0x01, PORT_DATA, 1 },
96+ .getsda = { 0x40, PORT_STAT, 0 },
97+ .getscl = { 0x80, PORT_STAT, 1 },
98+ },
9299 };
93100
94101 static int type = -1;
@@ -103,4 +110,5 @@ MODULE_PARM_DESC(type, · 8 unmodified lines
103110 " 5 = ADM1025, ADM1030 and ADM1031 evaluation boards\n"
104111 " 6 = Barco LPT->DVI (K5800236) adapter\n"
105112 " 7 = One For All JP1 parallel port adapter\n"
113+ " 8 = VCT-jig\n"
106114 );
drivers/i2c/busses/i2c-pxa.c+50−62
@@ -132,6 +132,7 @@ struct pxa_i2c { · 131 unmodified lines
132132 unsigned int msg_idx;
133133 unsigned int msg_ptr;
134134 unsigned int slave_addr;
135+ unsigned int req_slave_addr;
135136
136137 struct i2c_adapter adap;
137138 struct clk *clk;
@@ -253,15 +254,20 @@ static void i2c_pxa_show_state(struct pxa_i2c *i2c, int lno, const char *fname) · 115 unmodified lines
253254 static void i2c_pxa_scream_blue_murder(struct pxa_i2c *i2c, const char *why)
254255 {
255256 unsigned int i;
256− printk(KERN_ERR "i2c: error: %s\n", why);
257− printk(KERN_ERR "i2c: msg_num: %d msg_idx: %d msg_ptr: %d\n",
257+ struct device *dev = &i2c->adap.dev;
258+
259+ dev_err(dev, "slave_0x%x error: %s\n",
260+ i2c->req_slave_addr >> 1, why);
261+ dev_err(dev, "msg_num: %d msg_idx: %d msg_ptr: %d\n",
258262 i2c->msg_num, i2c->msg_idx, i2c->msg_ptr);
259− printk(KERN_ERR "i2c: ICR: %08x ISR: %08x\n",
260− readl(_ICR(i2c)), readl(_ISR(i2c)));
261− printk(KERN_DEBUG "i2c: log: ");
263+ dev_err(dev, "IBMR: %08x IDBR: %08x ICR: %08x ISR: %08x\n",
264+ readl(_IBMR(i2c)), readl(_IDBR(i2c)), readl(_ICR(i2c)),
265+ readl(_ISR(i2c)));
266+ dev_dbg(dev, "log: ");
262267 for (i = 0; i < i2c->irqlogidx; i++)
263− printk("[%08x:%08x] ", i2c->isrlog[i], i2c->icrlog[i]);
264− printk("\n");
268+ pr_debug("[%08x:%08x] ", i2c->isrlog[i], i2c->icrlog[i]);
269+
270+ pr_debug("\n");
265271 }
266272
267273 #else /* ifdef DEBUG */
@@ -459,7 +465,7 @@ static void i2c_pxa_reset(struct pxa_i2c *i2c) · 191 unmodified lines
459465 writel(I2C_ISR_INIT, _ISR(i2c));
460466 writel(readl(_ICR(i2c)) & ~ICR_UR, _ICR(i2c));
461467
462− if (i2c->reg_isar)
468+ if (i2c->reg_isar && IS_ENABLED(CONFIG_I2C_PXA_SLAVE))
463469 writel(i2c->slave_addr, _ISAR(i2c));
464470
465471 /* set control register values */
@@ -638,6 +644,7 @@ static inline void i2c_pxa_start_message(struct pxa_i2c *i2c) · 172 unmodified lines
638644 * Step 1: target slave address into IDBR
639645 */
640646 writel(i2c_pxa_addr_byte(i2c->msg), _IDBR(i2c));
647+ i2c->req_slave_addr = i2c_pxa_addr_byte(i2c->msg);
641648
642649 /*
643650 * Step 2: initiate the write.
@@ -745,8 +752,10 @@ static int i2c_pxa_do_pio_xfer(struct pxa_i2c *i2c, · 101 unmodified lines
745752 ret = i2c->msg_idx;
746753
747754 out:
748− if (timeout == 0)
755+ if (timeout == 0) {
749756 i2c_pxa_scream_blue_murder(i2c, "timeout");
757+ ret = I2C_RETRY;
758+ }
750759
751760 return ret;
752761 }
@@ -949,6 +958,7 @@ static void i2c_pxa_irq_txempty(struct pxa_i2c *i2c, u32 isr) · 196 unmodified lines
949958 * Write the next address.
950959 */
951960 writel(i2c_pxa_addr_byte(i2c->msg), _IDBR(i2c));
961+ i2c->req_slave_addr = i2c_pxa_addr_byte(i2c->msg);
952962
953963 /*
954964 * And trigger a repeated start, and send the byte.
@@ -1114,7 +1124,9 @@ static int i2c_pxa_probe_dt(struct platform_device *pdev, struct pxa_i2c *i2c, · 159 unmodified lines
11141124 i2c->use_pio = 1;
11151125 if (of_get_property(np, "mrvl,i2c-fast-mode", NULL))
11161126 i2c->fast_mode = 1;
1117− *i2c_types = (u32)(of_id->data);
1127+
1128+ *i2c_types = (enum pxa_i2c_types)(of_id->data);
1129+
11181130 return 0;
11191131 }
11201132
@@ -1146,10 +1158,19 @@ static int i2c_pxa_probe(struct platform_device *dev) · 25 unmodified lines
11461158 struct resource *res = NULL;
11471159 int ret, irq;
11481160
1149− i2c = kzalloc(sizeof(struct pxa_i2c), GFP_KERNEL);
1150− if (!i2c) {
1151− ret = -ENOMEM;
1152− goto emalloc;
1161+ i2c = devm_kzalloc(&dev->dev, sizeof(struct pxa_i2c), GFP_KERNEL);
1162+ if (!i2c)
1163+ return -ENOMEM;
1164+
1165+ res = platform_get_resource(dev, IORESOURCE_MEM, 0);
1166+ i2c->reg_base = devm_ioremap_resource(&dev->dev, res);
1167+ if (IS_ERR(i2c->reg_base))
1168+ return PTR_ERR(i2c->reg_base);
1169+
1170+ irq = platform_get_irq(dev, 0);
1171+ if (irq < 0) {
1172+ dev_err(&dev->dev, "no irq resource: %d\n", irq);
1173+ return irq;
11531174 }
11541175
11551176 /* Default adapter num to device id; i2c_pxa_probe_dt can override. */
@@ -1159,19 +1180,7 @@ static int i2c_pxa_probe(struct platform_device *dev) · 3 unmodified lines
11591180 if (ret > 0)
11601181 ret = i2c_pxa_probe_pdata(dev, i2c, &i2c_type);
11611182 if (ret < 0)
1162− goto eclk;
1163−
1164− res = platform_get_resource(dev, IORESOURCE_MEM, 0);
1165− irq = platform_get_irq(dev, 0);
1166− if (res == NULL || irq < 0) {
1167− ret = -ENODEV;
1168− goto eclk;
1169− }
1170−
1171− if (!request_mem_region(res->start, resource_size(res), res->name)) {
1172− ret = -ENOMEM;
1173− goto eclk;
1174− }
1183+ return ret;
11751184
11761185 i2c->adap.owner = THIS_MODULE;
11771186 i2c->adap.retries = 5;
@@ -1181,16 +1190,10 @@ static int i2c_pxa_probe(struct platform_device *dev) · 3 unmodified lines
11811190
11821191 strlcpy(i2c->adap.name, "pxa_i2c-i2c", sizeof(i2c->adap.name));
11831192
1184− i2c->clk = clk_get(&dev->dev, NULL);
1193+ i2c->clk = devm_clk_get(&dev->dev, NULL);
11851194 if (IS_ERR(i2c->clk)) {
1186− ret = PTR_ERR(i2c->clk);
1187− goto eclk;
1188− }
1189−
1190− i2c->reg_base = ioremap(res->start, resource_size(res));
1191− if (!i2c->reg_base) {
1192− ret = -EIO;
1193− goto eremap;
1195+ dev_err(&dev->dev, "failed to get the clk: %ld\n", PTR_ERR(i2c->clk));
1196+ return PTR_ERR(i2c->clk);
11941197 }
11951198
11961199 i2c->reg_ibmr = i2c->reg_base + pxa_reg_layout[i2c_type].ibmr;
@@ -1232,10 +1235,13 @@ static int i2c_pxa_probe(struct platform_device *dev) · 35 unmodified lines
12321235 i2c->adap.algo = &i2c_pxa_pio_algorithm;
12331236 } else {
12341237 i2c->adap.algo = &i2c_pxa_algorithm;
1235− ret = request_irq(irq, i2c_pxa_handler, IRQF_SHARED,
1236− dev_name(&dev->dev), i2c);
1237− if (ret)
1238+ ret = devm_request_irq(&dev->dev, irq, i2c_pxa_handler,
1239+ IRQF_SHARED | IRQF_NO_SUSPEND,
1240+ dev_name(&dev->dev), i2c);
1241+ if (ret) {
1242+ dev_err(&dev->dev, "failed to request irq: %d\n", ret);
12381243 goto ereqirq;
1244+ }
12391245 }
12401246
12411247 i2c_pxa_reset(i2c);
@@ -1248,33 +1254,22 @@ static int i2c_pxa_probe(struct platform_device *dev) · 6 unmodified lines
12481254
12491255 ret = i2c_add_numbered_adapter(&i2c->adap);
12501256 if (ret < 0) {
1251− printk(KERN_INFO "I2C: Failed to add bus\n");
1252− goto eadapt;
1257+ dev_err(&dev->dev, "failed to add bus: %d\n", ret);
1258+ goto ereqirq;
12531259 }
12541260
12551261 platform_set_drvdata(dev, i2c);
12561262
12571263 #ifdef CONFIG_I2C_PXA_SLAVE
1258− printk(KERN_INFO "I2C: %s: PXA I2C adapter, slave address %d\n",
1259− dev_name(&i2c->adap.dev), i2c->slave_addr);
1264+ dev_info(&i2c->adap.dev, " PXA I2C adapter, slave address %d\n",
1265+ i2c->slave_addr);
12601266 #else
1261− printk(KERN_INFO "I2C: %s: PXA I2C adapter\n",
1262− dev_name(&i2c->adap.dev));
1267+ dev_info(&i2c->adap.dev, " PXA I2C adapter\n");
12631268 #endif
12641269 return 0;
12651270
1266−eadapt:
1267− if (!i2c->use_pio)
1268− free_irq(irq, i2c);
12691271 ereqirq:
12701272 clk_disable_unprepare(i2c->clk);
1271− iounmap(i2c->reg_base);
1272−eremap:
1273− clk_put(i2c->clk);
1274−eclk:
1275− kfree(i2c);
1276−emalloc:
1277− release_mem_region(res->start, resource_size(res));
12781273 return ret;
12791274 }
12801275
@@ -1283,15 +1278,8 @@ static int i2c_pxa_remove(struct platform_device *dev) · 2 unmodified lines
12831278 struct pxa_i2c *i2c = platform_get_drvdata(dev);
12841279
12851280 i2c_del_adapter(&i2c->adap);
1286− if (!i2c->use_pio)
1287− free_irq(i2c->irq, i2c);
12881281
12891282 clk_disable_unprepare(i2c->clk);
1290− clk_put(i2c->clk);
1291−
1292− iounmap(i2c->reg_base);
1293− release_mem_region(i2c->iobase, i2c->iosize);
1294− kfree(i2c);
12951283
12961284 return 0;
12971285 }
drivers/i2c/busses/i2c-tegra.c+50−2
@@ -100,6 +100,12 @@ · 99 unmodified lines
100100 #define I2C_HEADER_CONTINUE_XFER (1<<15)
101101 #define I2C_HEADER_MASTER_ADDR_SHIFT 12
102102 #define I2C_HEADER_SLAVE_ADDR_SHIFT 1
103+
104+#define I2C_CONFIG_LOAD 0x08C
105+#define I2C_MSTR_CONFIG_LOAD (1 << 0)
106+#define I2C_SLV_CONFIG_LOAD (1 << 1)
107+#define I2C_TIMEOUT_CONFIG_LOAD (1 << 2)
108+
103109 /*
104110 * msg_end_type: The bus control which need to be send at end of transfer.
105111 * @MSG_END_STOP: Send stop pulse at end of transfer.
@@ -121,6 +127,8 @@ enum msg_end_type { · 15 unmodified lines
121127 * @has_single_clk_source: The i2c controller has single clock source. Tegra30
122128 * and earlier Socs has two clock sources i.e. div-clk and
123129 * fast-clk.
130+ * @has_config_load_reg: Has the config load register to load the new
131+ * configuration.
124132 * @clk_divisor_hs_mode: Clock divisor in HS mode.
125133 * @clk_divisor_std_fast_mode: Clock divisor in standard/fast mode. It is
126134 * applicable if there is no fast clock source i.e. single clock
@@ -131,8 +139,10 @@ struct tegra_i2c_hw_feature { · 4 unmodified lines
131139 bool has_continue_xfer_support;
132140 bool has_per_pkt_xfer_complete_irq;
133141 bool has_single_clk_source;
142+ bool has_config_load_reg;
134143 int clk_divisor_hs_mode;
135144 int clk_divisor_std_fast_mode;
145+ u16 clk_divisor_fast_plus_mode;
136146 };
137147
138148 /**
@@ -172,6 +182,7 @@ struct tegra_i2c_dev { · 33 unmodified lines
172182 size_t msg_buf_remaining;
173183 int msg_read;
174184 u32 bus_clk_rate;
185+ u16 clk_divisor_non_hs_mode;
175186 bool is_suspended;
176187 };
177188
@@ -410,6 +421,7 @@ static int tegra_i2c_init(struct tegra_i2c_dev *i2c_dev) · 232 unmodified lines
410421 u32 val;
411422 int err = 0;
412423 u32 clk_divisor;
424+ unsigned long timeout = jiffies + HZ;
413425
414426 err = tegra_i2c_clock_enable(i2c_dev);
415427 if (err < 0) {
@@ -431,7 +443,7 @@ static int tegra_i2c_init(struct tegra_i2c_dev *i2c_dev) · 15 unmodified lines
431443
432444 /* Make sure clock divisor programmed correctly */
433445 clk_divisor = i2c_dev->hw->clk_divisor_hs_mode;
434− clk_divisor |= i2c_dev->hw->clk_divisor_std_fast_mode <<
446+ clk_divisor |= i2c_dev->clk_divisor_non_hs_mode <<
435447 I2C_CLK_DIVISOR_STD_FAST_MODE_SHIFT;
436448 i2c_writel(i2c_dev, clk_divisor, I2C_CLK_DIVISOR);
437449
@@ -451,6 +463,18 @@ static int tegra_i2c_init(struct tegra_i2c_dev *i2c_dev) · 13 unmodified lines
451463 if (tegra_i2c_flush_fifos(i2c_dev))
452464 err = -ETIMEDOUT;
453465
466+ if (i2c_dev->hw->has_config_load_reg) {
467+ i2c_writel(i2c_dev, I2C_MSTR_CONFIG_LOAD, I2C_CONFIG_LOAD);
468+ while (i2c_readl(i2c_dev, I2C_CONFIG_LOAD) != 0) {
469+ if (time_after(jiffies, timeout)) {
470+ dev_warn(i2c_dev->dev,
471+ "timeout waiting for config load\n");
472+ return -ETIMEDOUT;
473+ }
474+ msleep(1);
475+ }
476+ }
477+
454478 tegra_i2c_clock_disable(i2c_dev);
455479
456480 if (i2c_dev->irq_disabled) {
@@ -681,6 +705,8 @@ static const struct tegra_i2c_hw_feature tegra20_i2c_hw = { · 224 unmodified lines
681705 .has_single_clk_source = false,
682706 .clk_divisor_hs_mode = 3,
683707 .clk_divisor_std_fast_mode = 0,
708+ .clk_divisor_fast_plus_mode = 0,
709+ .has_config_load_reg = false,
684710 };
685711
686712 static const struct tegra_i2c_hw_feature tegra30_i2c_hw = {
@@ -689,6 +715,8 @@ static const struct tegra_i2c_hw_feature tegra30_i2c_hw = { · 2 unmodified lines
689715 .has_single_clk_source = false,
690716 .clk_divisor_hs_mode = 3,
691717 .clk_divisor_std_fast_mode = 0,
718+ .clk_divisor_fast_plus_mode = 0,
719+ .has_config_load_reg = false,
692720 };
693721
694722 static const struct tegra_i2c_hw_feature tegra114_i2c_hw = {
@@ -697,10 +725,23 @@ static const struct tegra_i2c_hw_feature tegra114_i2c_hw = { · 2 unmodified lines
697725 .has_single_clk_source = true,
698726 .clk_divisor_hs_mode = 1,
699727 .clk_divisor_std_fast_mode = 0x19,
728+ .clk_divisor_fast_plus_mode = 0x10,
729+ .has_config_load_reg = false,
730+};
731+
732+static const struct tegra_i2c_hw_feature tegra124_i2c_hw = {
733+ .has_continue_xfer_support = true,
734+ .has_per_pkt_xfer_complete_irq = true,
735+ .has_single_clk_source = true,
736+ .clk_divisor_hs_mode = 1,
737+ .clk_divisor_std_fast_mode = 0x19,
738+ .clk_divisor_fast_plus_mode = 0x10,
739+ .has_config_load_reg = true,
700740 };
701741
702742 /* Match table for of_platform binding */
703743 static const struct of_device_id tegra_i2c_of_match[] = {
744+ { .compatible = "nvidia,tegra124-i2c", .data = &tegra124_i2c_hw, },
704745 { .compatible = "nvidia,tegra114-i2c", .data = &tegra114_i2c_hw, },
705746 { .compatible = "nvidia,tegra30-i2c", .data = &tegra30_i2c_hw, },
706747 { .compatible = "nvidia,tegra20-i2c", .data = &tegra20_i2c_hw, },
@@ -793,7 +834,14 @@ static int tegra_i2c_probe(struct platform_device *pdev) · 86 unmodified lines
793834 }
794835 }
795836
796− clk_multiplier *= (i2c_dev->hw->clk_divisor_std_fast_mode + 1);
837+ i2c_dev->clk_divisor_non_hs_mode =
838+ i2c_dev->hw->clk_divisor_std_fast_mode;
839+ if (i2c_dev->hw->clk_divisor_fast_plus_mode &&
840+ (i2c_dev->bus_clk_rate == 1000000))
841+ i2c_dev->clk_divisor_non_hs_mode =
842+ i2c_dev->hw->clk_divisor_fast_plus_mode;
843+
844+ clk_multiplier *= (i2c_dev->clk_divisor_non_hs_mode + 1);
797845 ret = clk_set_rate(i2c_dev->div_clk,
798846 i2c_dev->bus_clk_rate * clk_multiplier);
799847 if (ret) {
drivers/i2c/busses/i2c-viperboard.c+5−5
@@ -391,11 +391,11 @@ static int vprbrd_i2c_probe(struct platform_device *pdev) · 390 unmodified lines
391391 VPRBRD_USB_REQUEST_I2C_FREQ, VPRBRD_USB_TYPE_OUT,
392392 0x0000, 0x0000, &vb_i2c->bus_freq_param, 1,
393393 VPRBRD_USB_TIMEOUT_MS);
394− if (ret != 1) {
395− dev_err(&pdev->dev,
396− "failure setting i2c_bus_freq to %d\n", i2c_bus_freq);
397− return -EIO;
398− }
394+ if (ret != 1) {
395+ dev_err(&pdev->dev, "failure setting i2c_bus_freq to %d\n",
396+ i2c_bus_freq);
397+ return -EIO;
398+ }
399399 } else {
400400 dev_err(&pdev->dev,
401401 "invalid i2c_bus_freq setting:%d\n", i2c_bus_freq);
drivers/i2c/busses/i2c-xgene-slimpro.c+4−4
@@ -198,10 +198,10 @@ static int slimpro_i2c_blkrd(struct slimpro_i2c_dev *ctx, u32 chip, u32 addr, · 197 unmodified lines
198198 int rc;
199199
200200 paddr = dma_map_single(ctx->dev, ctx->dma_buffer, readlen, DMA_FROM_DEVICE);
201− rc = dma_mapping_error(ctx->dev, paddr);
202− if (rc) {
201+ if (dma_mapping_error(ctx->dev, paddr)) {
203202 dev_err(&ctx->adapter.dev, "Error in mapping dma buffer %p\n",
204203 ctx->dma_buffer);
204+ rc = -ENOMEM;
205205 goto err;
206206 }
207207
@@ -241,10 +241,10 @@ static int slimpro_i2c_blkwr(struct slimpro_i2c_dev *ctx, u32 chip, · 33 unmodified lines
241241 memcpy(ctx->dma_buffer, data, writelen);
242242 paddr = dma_map_single(ctx->dev, ctx->dma_buffer, writelen,
243243 DMA_TO_DEVICE);
244− rc = dma_mapping_error(ctx->dev, paddr);
245− if (rc) {
244+ if (dma_mapping_error(ctx->dev, paddr)) {
246245 dev_err(&ctx->adapter.dev, "Error in mapping dma buffer %p\n",
247246 ctx->dma_buffer);
247+ rc = -ENOMEM;
248248 goto err;
249249 }
250250
drivers/i2c/busses/i2c-xiic.c+34−40
@@ -283,7 +283,7 @@ static void xiic_reinit(struct xiic_i2c *i2c) · 282 unmodified lines
283283 /* Enable interrupts */
284284 xiic_setreg32(i2c, XIIC_DGIER_OFFSET, XIIC_GINTR_ENABLE_MASK);
285285
286− xiic_irq_clr_en(i2c, XIIC_INTR_AAS_MASK | XIIC_INTR_ARB_LOST_MASK);
286+ xiic_irq_clr_en(i2c, XIIC_INTR_ARB_LOST_MASK);
287287 }
288288
289289 static void xiic_deinit(struct xiic_i2c *i2c)
@@ -358,8 +358,9 @@ static void xiic_wakeup(struct xiic_i2c *i2c, int code) · 68 unmodified lines
358358 wake_up(&i2c->wait);
359359 }
360360
361−static void xiic_process(struct xiic_i2c *i2c)
361+static irqreturn_t xiic_process(int irq, void *dev_id)
362362 {
363+ struct xiic_i2c *i2c = dev_id;
363364 u32 pend, isr, ier;
364365 u32 clr = 0;
365366
@@ -368,6 +369,7 @@ static void xiic_process(struct xiic_i2c *i2c) · 2 unmodified lines
368369 * To find which interrupts are pending; AND interrupts pending with
369370 * interrupts masked.
370371 */
372+ spin_lock(&i2c->lock);
371373 isr = xiic_getreg32(i2c, XIIC_IISR_OFFSET);
372374 ier = xiic_getreg32(i2c, XIIC_IIER_OFFSET);
373375 pend = isr & ier;
@@ -378,11 +380,6 @@ static void xiic_process(struct xiic_i2c *i2c) · 4 unmodified lines
378380 __func__, xiic_getreg8(i2c, XIIC_SR_REG_OFFSET),
379381 i2c->tx_msg, i2c->nmsgs);
380382
381− /* Do not processes a devices interrupts if the device has no
382− * interrupts pending
383− */
384− if (!pend)
385− return;
386383
387384 /* Service requesting interrupt */
388385 if ((pend & XIIC_INTR_ARB_LOST_MASK) ||
@@ -402,13 +399,15 @@ static void xiic_process(struct xiic_i2c *i2c) · 13 unmodified lines
402399 */
403400 xiic_reinit(i2c);
404401
402+ if (i2c->rx_msg)
403+ xiic_wakeup(i2c, STATE_ERROR);
405404 if (i2c->tx_msg)
406405 xiic_wakeup(i2c, STATE_ERROR);
407−
408− } else if (pend & XIIC_INTR_RX_FULL_MASK) {
406+ }
407+ if (pend & XIIC_INTR_RX_FULL_MASK) {
409408 /* Receive register/FIFO is full */
410409
411− clr = XIIC_INTR_RX_FULL_MASK;
410+ clr |= XIIC_INTR_RX_FULL_MASK;
412411 if (!i2c->rx_msg) {
413412 dev_dbg(i2c->adap.dev.parent,
414413 "%s unexpexted RX IRQ\n", __func__);
@@ -441,9 +440,10 @@ static void xiic_process(struct xiic_i2c *i2c) · 26 unmodified lines
441440 __xiic_start_xfer(i2c);
442441 }
443442 }
444− } else if (pend & XIIC_INTR_BNB_MASK) {
443+ }
444+ if (pend & XIIC_INTR_BNB_MASK) {
445445 /* IIC bus has transitioned to not busy */
446− clr = XIIC_INTR_BNB_MASK;
446+ clr |= XIIC_INTR_BNB_MASK;
447447
448448 /* The bus is not busy, disable BusNotBusy interrupt */
449449 xiic_irq_dis(i2c, XIIC_INTR_BNB_MASK);
@@ -456,12 +456,12 @@ static void xiic_process(struct xiic_i2c *i2c) · 6 unmodified lines
456456 xiic_wakeup(i2c, STATE_DONE);
457457 else
458458 xiic_wakeup(i2c, STATE_ERROR);
459−
460− } else if (pend & (XIIC_INTR_TX_EMPTY_MASK | XIIC_INTR_TX_HALF_MASK)) {
459+ }
460+ if (pend & (XIIC_INTR_TX_EMPTY_MASK | XIIC_INTR_TX_HALF_MASK)) {
461461 /* Transmit register/FIFO is empty or ½ empty */
462462
463− clr = pend &
464− (XIIC_INTR_TX_EMPTY_MASK | XIIC_INTR_TX_HALF_MASK);
463+ clr |= (pend &
464+ (XIIC_INTR_TX_EMPTY_MASK | XIIC_INTR_TX_HALF_MASK));
465465
466466 if (!i2c->tx_msg) {
467467 dev_dbg(i2c->adap.dev.parent,
@@ -492,16 +492,13 @@ static void xiic_process(struct xiic_i2c *i2c) · 24 unmodified lines
492492 * make sure to disable tx half
493493 */
494494 xiic_irq_dis(i2c, XIIC_INTR_TX_HALF_MASK);
495− } else {
496− /* got IRQ which is not acked */
497− dev_err(i2c->adap.dev.parent, "%s Got unexpected IRQ\n",
498− __func__);
499− clr = pend;
500495 }
501496 out:
502497 dev_dbg(i2c->adap.dev.parent, "%s clr: 0x%x\n", __func__, clr);
503498
504499 xiic_setreg32(i2c, XIIC_IISR_OFFSET, clr);
500+ spin_unlock(&i2c->lock);
501+ return IRQ_HANDLED;
505502 }
506503
507504 static int xiic_bus_busy(struct xiic_i2c *i2c)
@@ -525,7 +522,7 @@ static int xiic_busy(struct xiic_i2c *i2c) · 17 unmodified lines
525522 */
526523 err = xiic_bus_busy(i2c);
527524 while (err && tries--) {
528− mdelay(1);
525+ msleep(1);
529526 err = xiic_bus_busy(i2c);
530527 }
531528
@@ -602,19 +599,21 @@ static void xiic_start_send(struct xiic_i2c *i2c) · 70 unmodified lines
602599 static irqreturn_t xiic_isr(int irq, void *dev_id)
603600 {
604601 struct xiic_i2c *i2c = dev_id;
605−
606− spin_lock(&i2c->lock);
607− /* disable interrupts globally */
608− xiic_setreg32(i2c, XIIC_DGIER_OFFSET, 0);
602+ u32 pend, isr, ier;
603+ irqreturn_t ret = IRQ_NONE;
604+ /* Do not processes a devices interrupts if the device has no
605+ * interrupts pending
606+ */
609607
610608 dev_dbg(i2c->adap.dev.parent, "%s entry\n", __func__);
611609
612− xiic_process(i2c);
613−
614− xiic_setreg32(i2c, XIIC_DGIER_OFFSET, XIIC_GINTR_ENABLE_MASK);
615− spin_unlock(&i2c->lock);
610+ isr = xiic_getreg32(i2c, XIIC_IISR_OFFSET);
611+ ier = xiic_getreg32(i2c, XIIC_IIER_OFFSET);
612+ pend = isr & ier;
613+ if (pend)
614+ ret = IRQ_WAKE_THREAD;
616615
617− return IRQ_HANDLED;
616+ return ret;
618617 }
619618
620619 static void __xiic_start_xfer(struct xiic_i2c *i2c)
@@ -663,16 +662,8 @@ static void __xiic_start_xfer(struct xiic_i2c *i2c) · 42 unmodified lines
663662
664663 static void xiic_start_xfer(struct xiic_i2c *i2c)
665664 {
666− unsigned long flags;
667−
668− spin_lock_irqsave(&i2c->lock, flags);
669− xiic_reinit(i2c);
670− /* disable interrupts globally */
671− xiic_setreg32(i2c, XIIC_DGIER_OFFSET, 0);
672− spin_unlock_irqrestore(&i2c->lock, flags);
673665
674666 __xiic_start_xfer(i2c);
675− xiic_setreg32(i2c, XIIC_DGIER_OFFSET, XIIC_GINTR_ENABLE_MASK);
676667 }
677668
678669 static int xiic_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, int num)
@@ -755,7 +746,10 @@ static int xiic_i2c_probe(struct platform_device *pdev) · 76 unmodified lines
755746 spin_lock_init(&i2c->lock);
756747 init_waitqueue_head(&i2c->wait);
757748
758− ret = devm_request_irq(&pdev->dev, irq, xiic_isr, 0, pdev->name, i2c);
749+ ret = devm_request_threaded_irq(&pdev->dev, irq, xiic_isr,
750+ xiic_process, IRQF_ONESHOT,
751+ pdev->name, i2c);
752+
759753 if (ret < 0) {
760754 dev_err(&pdev->dev, "Cannot claim IRQ\n");
761755 return ret;
drivers/i2c/i2c-core.c+194−35
@@ -27,6 +27,7 @@ · 26 unmodified lines
2727 I2C slave support (c) 2014 by Wolfram Sang <wsa@sang-engineering.com>
2828 */
2929
30+#include <dt-bindings/i2c/i2c.h>
3031 #include <linux/module.h>
3132 #include <linux/kernel.h>
3233 #include <linux/delay.h>
@@ -47,6 +48,7 @@ · 14 unmodified lines
4748 #include <linux/rwsem.h>
4849 #include <linux/pm_runtime.h>
4950 #include <linux/pm_domain.h>
51+#include <linux/pm_wakeirq.h>
5052 #include <linux/acpi.h>
5153 #include <linux/jump_label.h>
5254 #include <asm/uaccess.h>
@@ -57,6 +59,9 @@ · 4 unmodified lines
5759 #define CREATE_TRACE_POINTS
5860 #include <trace/events/i2c.h>
5961
62+#define I2C_ADDR_OFFSET_TEN_BIT 0xa000
63+#define I2C_ADDR_OFFSET_SLAVE 0x1000
64+
6065 /* core_lock protects i2c_adapter_idr, and guarantees
6166 that device detection, deletion of detected devices, and attach_adapter
6267 calls are serialized */
@@ -641,11 +646,13 @@ static int i2c_device_probe(struct device *dev) · 578 unmodified lines
641646 if (!client->irq) {
642647 int irq = -ENOENT;
643648
644− if (dev->of_node)
645− irq = of_irq_get(dev->of_node, 0);
646− else if (ACPI_COMPANION(dev))
649+ if (dev->of_node) {
650+ irq = of_irq_get_byname(dev->of_node, "irq");
651+ if (irq == -EINVAL || irq == -ENODATA)
652+ irq = of_irq_get(dev->of_node, 0);
653+ } else if (ACPI_COMPANION(dev)) {
647654 irq = acpi_dev_gpio_irq_get(ACPI_COMPANION(dev), 0);
648−
655+ }
649656 if (irq == -EPROBE_DEFER)
650657 return irq;
651658 if (irq < 0)
@@ -658,23 +665,49 @@ static int i2c_device_probe(struct device *dev) · 6 unmodified lines
658665 if (!driver->probe || !driver->id_table)
659666 return -ENODEV;
660667
661− if (!device_can_wakeup(&client->dev))
662− device_init_wakeup(&client->dev,
663− client->flags & I2C_CLIENT_WAKE);
668+ if (client->flags & I2C_CLIENT_WAKE) {
669+ int wakeirq = -ENOENT;
670+
671+ if (dev->of_node) {
672+ wakeirq = of_irq_get_byname(dev->of_node, "wakeup");
673+ if (wakeirq == -EPROBE_DEFER)
674+ return wakeirq;
675+ }
676+
677+ device_init_wakeup(&client->dev, true);
678+
679+ if (wakeirq > 0 && wakeirq != client->irq)
680+ status = dev_pm_set_dedicated_wake_irq(dev, wakeirq);
681+ else if (client->irq > 0)
682+ status = dev_pm_set_wake_irq(dev, wakeirq);
683+ else
684+ status = 0;
685+
686+ if (status)
687+ dev_warn(&client->dev, "failed to set up wakeup irq");
688+ }
689+
664690 dev_dbg(dev, "probe\n");
665691
666692 status = of_clk_set_defaults(dev->of_node, false);
667693 if (status < 0)
668− return status;
694+ goto err_clear_wakeup_irq;
669695
670696 status = dev_pm_domain_attach(&client->dev, true);
671697 if (status != -EPROBE_DEFER) {
672698 status = driver->probe(client, i2c_match_id(driver->id_table,
673699 client));
674700 if (status)
675− dev_pm_domain_detach(&client->dev, true);
701+ goto err_detach_pm_domain;
676702 }
677703
704+ return 0;
705+
706+err_detach_pm_domain:
707+ dev_pm_domain_detach(&client->dev, true);
708+err_clear_wakeup_irq:
709+ dev_pm_clear_wake_irq(&client->dev);
710+ device_init_wakeup(&client->dev, false);
678711 return status;
679712 }
680713
@@ -694,6 +727,10 @@ static int i2c_device_remove(struct device *dev) · 13 unmodified lines
694727 }
695728
696729 dev_pm_domain_detach(&client->dev, true);
730+
731+ dev_pm_clear_wake_irq(&client->dev);
732+ device_init_wakeup(&client->dev, false);
733+
697734 return status;
698735 }
699736
@@ -778,17 +815,32 @@ struct i2c_client *i2c_verify_client(struct device *dev) · 78 unmodified lines
778815 EXPORT_SYMBOL(i2c_verify_client);
779816
780817
818+/* Return a unique address which takes the flags of the client into account */
819+static unsigned short i2c_encode_flags_to_addr(struct i2c_client *client)
820+{
821+ unsigned short addr = client->addr;
822+
823+ /* For some client flags, add an arbitrary offset to avoid collisions */
824+ if (client->flags & I2C_CLIENT_TEN)
825+ addr |= I2C_ADDR_OFFSET_TEN_BIT;
826+
827+ if (client->flags & I2C_CLIENT_SLAVE)
828+ addr |= I2C_ADDR_OFFSET_SLAVE;
829+
830+ return addr;
831+}
832+
781833 /* This is a permissive address validity check, I2C address map constraints
782834 * are purposely not enforced, except for the general call address. */
783−static int i2c_check_client_addr_validity(const struct i2c_client *client)
835+static int i2c_check_addr_validity(unsigned addr, unsigned short flags)
784836 {
785− if (client->flags & I2C_CLIENT_TEN) {
837+ if (flags & I2C_CLIENT_TEN) {
786838 /* 10-bit address, all values are valid */
787− if (client->addr > 0x3ff)
839+ if (addr > 0x3ff)
788840 return -EINVAL;
789841 } else {
790842 /* 7-bit address, reject the general call address */
791− if (client->addr == 0x00 || client->addr > 0x7f)
843+ if (addr == 0x00 || addr > 0x7f)
792844 return -EINVAL;
793845 }
794846 return 0;
@@ -798,7 +850,7 @@ static int i2c_check_client_addr_validity(const struct i2c_client *client) · 3 unmodified lines
798850 * device uses a reserved address, then it shouldn't be probed. 7-bit
799851 * addressing is assumed, 10-bit address devices are rare and should be
800852 * explicitly enumerated. */
801−static int i2c_check_addr_validity(unsigned short addr)
853+static int i2c_check_7bit_addr_validity_strict(unsigned short addr)
802854 {
803855 /*
804856 * Reserved addresses per I2C specification:
@@ -820,7 +872,7 @@ static int __i2c_check_addr_busy(struct device *dev, void *addrp) · 15 unmodified lines
820872 struct i2c_client *client = i2c_verify_client(dev);
821873 int addr = *(int *)addrp;
822874
823− if (client && client->addr == addr)
875+ if (client && i2c_encode_flags_to_addr(client) == addr)
824876 return -EBUSY;
825877 return 0;
826878 }
@@ -923,10 +975,8 @@ static void i2c_dev_set_name(struct i2c_adapter *adap, · 96 unmodified lines
923975 return;
924976 }
925977
926− /* For 10-bit clients, add an arbitrary offset to avoid collisions */
927978 dev_set_name(&client->dev, "%d-%04x", i2c_adapter_id(adap),
928− client->addr | ((client->flags & I2C_CLIENT_TEN)
929− ? 0xa000 : 0));
979+ i2c_encode_flags_to_addr(client));
930980 }
931981
932982 /**
@@ -968,8 +1018,7 @@ i2c_new_device(struct i2c_adapter *adap, struct i2c_board_info const *info) · 35 unmodified lines
9681018
9691019 strlcpy(client->name, info->type, sizeof(client->name));
9701020
971− /* Check for address validity */
972− status = i2c_check_client_addr_validity(client);
1021+ status = i2c_check_addr_validity(client->addr, client->flags);
9731022 if (status) {
9741023 dev_err(&adap->dev, "Invalid %d-bit I2C address 0x%02hx\n",
9751024 client->flags & I2C_CLIENT_TEN ? 10 : 7, client->addr);
@@ -977,7 +1026,7 @@ i2c_new_device(struct i2c_adapter *adap, struct i2c_board_info const *info) · 1 unmodified line
9771026 }
9781027
9791028 /* Check for address business */
980− status = i2c_check_addr_busy(adap, client->addr);
1029+ status = i2c_check_addr_busy(adap, i2c_encode_flags_to_addr(client));
9811030 if (status)
9821031 goto out_err;
9831032
@@ -1142,6 +1191,16 @@ i2c_sysfs_new_device(struct device *dev, struct device_attribute *attr, · 158 unmodified lines
11421191 return -EINVAL;
11431192 }
11441193
1194+ if ((info.addr & I2C_ADDR_OFFSET_TEN_BIT) == I2C_ADDR_OFFSET_TEN_BIT) {
1195+ info.addr &= ~I2C_ADDR_OFFSET_TEN_BIT;
1196+ info.flags |= I2C_CLIENT_TEN;
1197+ }
1198+
1199+ if (info.addr & I2C_ADDR_OFFSET_SLAVE) {
1200+ info.addr &= ~I2C_ADDR_OFFSET_SLAVE;
1201+ info.flags |= I2C_CLIENT_SLAVE;
1202+ }
1203+
11451204 client = i2c_new_device(adap, &info);
11461205 if (!client)
11471206 return -EINVAL;
@@ -1193,7 +1252,7 @@ i2c_sysfs_delete_device(struct device *dev, struct device_attribute *attr, · 45 unmodified lines
11931252 i2c_adapter_depth(adap));
11941253 list_for_each_entry_safe(client, next, &adap->userspace_clients,
11951254 detected) {
1196− if (client->addr == addr) {
1255+ if (i2c_encode_flags_to_addr(client) == addr) {
11971256 dev_info(dev, "%s: Deleting device %s at 0x%02hx\n",
11981257 "delete_device", client->name, client->addr);
11991258
@@ -1273,7 +1332,8 @@ static struct i2c_client *of_i2c_register_device(struct i2c_adapter *adap, · 73 unmodified lines
12731332 struct i2c_client *result;
12741333 struct i2c_board_info info = {};
12751334 struct dev_archdata dev_ad = {};
1276− const __be32 *addr;
1335+ const __be32 *addr_be;
1336+ u32 addr;
12771337 int len;
12781338
12791339 dev_dbg(&adap->dev, "of_i2c: register %s\n", node->full_name);
@@ -1284,20 +1344,31 @@ static struct i2c_client *of_i2c_register_device(struct i2c_adapter *adap, · 4 unmodified lines
12841344 return ERR_PTR(-EINVAL);
12851345 }
12861346
1287− addr = of_get_property(node, "reg", &len);
1288− if (!addr || (len < sizeof(*addr))) {
1347+ addr_be = of_get_property(node, "reg", &len);
1348+ if (!addr_be || (len < sizeof(*addr_be))) {
12891349 dev_err(&adap->dev, "of_i2c: invalid reg on %s\n",
12901350 node->full_name);
12911351 return ERR_PTR(-EINVAL);
12921352 }
12931353
1294− info.addr = be32_to_cpup(addr);
1295− if (info.addr > (1 << 10) - 1) {
1354+ addr = be32_to_cpup(addr_be);
1355+ if (addr & I2C_TEN_BIT_ADDRESS) {
1356+ addr &= ~I2C_TEN_BIT_ADDRESS;
1357+ info.flags |= I2C_CLIENT_TEN;
1358+ }
1359+
1360+ if (addr & I2C_OWN_SLAVE_ADDRESS) {
1361+ addr &= ~I2C_OWN_SLAVE_ADDRESS;
1362+ info.flags |= I2C_CLIENT_SLAVE;
1363+ }
1364+
1365+ if (i2c_check_addr_validity(addr, info.flags)) {
12961366 dev_err(&adap->dev, "of_i2c: invalid addr=%x on %s\n",
12971367 info.addr, node->full_name);
12981368 return ERR_PTR(-EINVAL);
12991369 }
13001370
1371+ info.addr = addr;
13011372 info.of_node = of_node_get(node);
13021373 info.archdata = &dev_ad;
13031374
@@ -1371,6 +1442,24 @@ struct i2c_adapter *of_find_i2c_adapter_by_node(struct device_node *node) · 67 unmodified lines
13711442 return adapter;
13721443 }
13731444 EXPORT_SYMBOL(of_find_i2c_adapter_by_node);
1445+
1446+/* must call i2c_put_adapter() when done with returned i2c_adapter device */
1447+struct i2c_adapter *of_get_i2c_adapter_by_node(struct device_node *node)
1448+{
1449+ struct i2c_adapter *adapter;
1450+
1451+ adapter = of_find_i2c_adapter_by_node(node);
1452+ if (!adapter)
1453+ return NULL;
1454+
1455+ if (!try_module_get(adapter->owner)) {
1456+ put_device(&adapter->dev);
1457+ adapter = NULL;
1458+ }
1459+
1460+ return adapter;
1461+}
1462+EXPORT_SYMBOL(of_get_i2c_adapter_by_node);
13741463 #else
13751464 static void of_i2c_register_devices(struct i2c_adapter *adap) { }
13761465 #endif /* CONFIG_OF */
@@ -2262,14 +2351,14 @@ static int i2c_detect_address(struct i2c_client *temp_client, · 885 unmodified lines
22622351 int err;
22632352
22642353 /* Make sure the address is valid */
2265− err = i2c_check_addr_validity(addr);
2354+ err = i2c_check_7bit_addr_validity_strict(addr);
22662355 if (err) {
22672356 dev_warn(&adapter->dev, "Invalid probe address 0x%02x\n",
22682357 addr);
22692358 return err;
22702359 }
22712360
2272− /* Skip if already in use */
2361+ /* Skip if already in use (7 bit, no need to encode flags) */
22732362 if (i2c_check_addr_busy(adapter, addr))
22742363 return 0;
22752364
@@ -2379,13 +2468,13 @@ i2c_new_probed_device(struct i2c_adapter *adap, · 103 unmodified lines
23792468
23802469 for (i = 0; addr_list[i] != I2C_CLIENT_END; i++) {
23812470 /* Check address validity */
2382− if (i2c_check_addr_validity(addr_list[i]) < 0) {
2471+ if (i2c_check_7bit_addr_validity_strict(addr_list[i]) < 0) {
23832472 dev_warn(&adap->dev, "Invalid 7-bit address "
23842473 "0x%02x\n", addr_list[i]);
23852474 continue;
23862475 }
23872476
2388− /* Check address availability */
2477+ /* Check address availability (7 bit, no need to encode flags) */
23892478 if (i2c_check_addr_busy(adap, addr_list[i])) {
23902479 dev_dbg(&adap->dev, "Address 0x%02x already in "
23912480 "use, not probing\n", addr_list[i]);
@@ -2413,9 +2502,15 @@ struct i2c_adapter *i2c_get_adapter(int nr) · 21 unmodified lines
24132502
24142503 mutex_lock(&core_lock);
24152504 adapter = idr_find(&i2c_adapter_idr, nr);
2416− if (adapter && !try_module_get(adapter->owner))
2505+ if (!adapter)
2506+ goto exit;
2507+
2508+ if (try_module_get(adapter->owner))
2509+ get_device(&adapter->dev);
2510+ else
24172511 adapter = NULL;
24182512
2513+ exit:
24192514 mutex_unlock(&core_lock);
24202515 return adapter;
24212516 }
@@ -2423,8 +2518,11 @@ EXPORT_SYMBOL(i2c_get_adapter); · 1 unmodified line
24232518
24242519 void i2c_put_adapter(struct i2c_adapter *adap)
24252520 {
2426− if (adap)
2427− module_put(adap->owner);
2521+ if (!adap)
2522+ return;
2523+
2524+ put_device(&adap->dev);
2525+ module_put(adap->owner);
24282526 }
24292527 EXPORT_SYMBOL(i2c_put_adapter);
24302528
@@ -2942,6 +3040,63 @@ trace: · 511 unmodified lines
29423040 }
29433041 EXPORT_SYMBOL(i2c_smbus_xfer);
29443042
3043+/**
3044+ * i2c_smbus_read_i2c_block_data_or_emulated - read block or emulate
3045+ * @client: Handle to slave device
3046+ * @command: Byte interpreted by slave
3047+ * @length: Size of data block; SMBus allows at most I2C_SMBUS_BLOCK_MAX bytes
3048+ * @values: Byte array into which data will be read; big enough to hold
3049+ * the data returned by the slave. SMBus allows at most
3050+ * I2C_SMBUS_BLOCK_MAX bytes.
3051+ *
3052+ * This executes the SMBus "block read" protocol if supported by the adapter.
3053+ * If block read is not supported, it emulates it using either word or byte
3054+ * read protocols depending on availability.
3055+ *
3056+ * The addresses of the I2C slave device that are accessed with this function
3057+ * must be mapped to a linear region, so that a block read will have the same
3058+ * effect as a byte read. Before using this function you must double-check
3059+ * if the I2C slave does support exchanging a block transfer with a byte
3060+ * transfer.
3061+ */
3062+s32 i2c_smbus_read_i2c_block_data_or_emulated(const struct i2c_client *client,
3063+ u8 command, u8 length, u8 *values)
3064+{
3065+ u8 i = 0;
3066+ int status;
3067+
3068+ if (length > I2C_SMBUS_BLOCK_MAX)
3069+ length = I2C_SMBUS_BLOCK_MAX;
3070+
3071+ if (i2c_check_functionality(client->adapter, I2C_FUNC_SMBUS_READ_I2C_BLOCK))
3072+ return i2c_smbus_read_i2c_block_data(client, command, length, values);
3073+
3074+ if (!i2c_check_functionality(client->adapter, I2C_FUNC_SMBUS_READ_BYTE_DATA))
3075+ return -EOPNOTSUPP;
3076+
3077+ if (i2c_check_functionality(client->adapter, I2C_FUNC_SMBUS_READ_WORD_DATA)) {
3078+ while ((i + 2) <= length) {
3079+ status = i2c_smbus_read_word_data(client, command + i);
3080+ if (status < 0)
3081+ return status;
3082+ values[i] = status & 0xff;
3083+ values[i + 1] = status >> 8;
3084+ i += 2;
3085+ }
3086+ }
3087+
3088+ while (i < length) {
3089+ status = i2c_smbus_read_byte_data(client, command + i);
3090+ if (status < 0)
3091+ return status;
3092+ values[i] = status;
3093+ i++;
3094+ }
3095+
3096+ return i;
3097+}
3098+EXPORT_SYMBOL(i2c_smbus_read_i2c_block_data_or_emulated);
3099+
29453100 #if IS_ENABLED(CONFIG_I2C_SLAVE)
29463101 int i2c_slave_register(struct i2c_client *client, i2c_slave_cb_t slave_cb)
29473102 {
@@ -2952,9 +3107,13 @@ int i2c_slave_register(struct i2c_client *client, i2c_slave_cb_t slave_cb) · 4 unmodified lines
29523107 return -EINVAL;
29533108 }
29543109
3110+ if (!(client->flags & I2C_CLIENT_SLAVE))
3111+ dev_warn(&client->dev, "%s: client slave flag not set. You might see address collisions\n",
3112+ __func__);
3113+
29553114 if (!(client->flags & I2C_CLIENT_TEN)) {
29563115 /* Enforce stricter address checking */
2957− ret = i2c_check_addr_validity(client->addr);
3116+ ret = i2c_check_7bit_addr_validity_strict(client->addr);
29583117 if (ret) {
29593118 dev_err(&client->dev, "%s: invalid address\n", __func__);
29603119 return ret;
drivers/i2c/i2c-slave-eeprom.c+0−1
@@ -157,7 +157,6 @@ MODULE_DEVICE_TABLE(i2c, i2c_slave_eeprom_id); · 156 unmodified lines
157157 static struct i2c_driver i2c_slave_eeprom_driver = {
158158 .driver = {
159159 .name = "i2c-slave-eeprom",
160− .owner = THIS_MODULE,
161160 },
162161 .probe = i2c_slave_eeprom_probe,
163162 .remove = i2c_slave_eeprom_remove,
drivers/i2c/muxes/Kconfig+11−0
@@ -61,4 +61,15 @@ config I2C_MUX_PINCTRL · 60 unmodified lines
6161 This driver can also be built as a module. If so, the module will be
6262 called pinctrl-i2cmux.
6363
64+config I2C_MUX_REG
65+ tristate "Register-based I2C multiplexer"
66+ help
67+ If you say yes to this option, support will be included for a
68+ register based I2C multiplexer. This driver provides access to
69+ I2C busses connected through a MUX, which is controlled
70+ by a single register.
71+
72+ This driver can also be built as a module. If so, the module
73+ will be called i2c-mux-reg.
74+
6475 endmenu
drivers/i2c/muxes/Makefile+1−0
@@ -7,5 +7,6 @@ obj-$(CONFIG_I2C_MUX_GPIO) += i2c-mux-gpio.o · 6 unmodified lines
77 obj-$(CONFIG_I2C_MUX_PCA9541) += i2c-mux-pca9541.o
88 obj-$(CONFIG_I2C_MUX_PCA954x) += i2c-mux-pca954x.o
99 obj-$(CONFIG_I2C_MUX_PINCTRL) += i2c-mux-pinctrl.o
10+obj-$(CONFIG_I2C_MUX_REG) += i2c-mux-reg.o
1011
1112 ccflags-$(CONFIG_I2C_DEBUG_BUS) := -DDEBUG
drivers/i2c/muxes/i2c-arb-gpio-challenge.c+2−1
@@ -196,7 +196,8 @@ static int i2c_arbitrator_probe(struct platform_device *pdev) · 195 unmodified lines
196196 dev_err(dev, "Cannot parse i2c-parent\n");
197197 return -EINVAL;
198198 }
199− arb->parent = of_find_i2c_adapter_by_node(parent_np);
199+ arb->parent = of_get_i2c_adapter_by_node(parent_np);
200+ of_node_put(parent_np);
200201 if (!arb->parent) {
201202 dev_err(dev, "Cannot find parent bus\n");
202203 return -EPROBE_DEFER;
drivers/i2c/muxes/i2c-mux-gpio.c+1−0
@@ -76,6 +76,7 @@ static int i2c_mux_gpio_probe_dt(struct gpiomux *mux, · 75 unmodified lines
7676 return -ENODEV;
7777 }
7878 adapter = of_find_i2c_adapter_by_node(adapter_np);
79+ of_node_put(adapter_np);
7980 if (!adapter)
8081 return -EPROBE_DEFER;
8182
drivers/i2c/muxes/i2c-mux-pca9541.c+0−1
@@ -386,7 +386,6 @@ static int pca9541_remove(struct i2c_client *client) · 385 unmodified lines
386386 static struct i2c_driver pca9541_driver = {
387387 .driver = {
388388 .name = "pca9541",
389− .owner = THIS_MODULE,
390389 },
391390 .probe = pca9541_probe,
392391 .remove = pca9541_remove,
drivers/i2c/muxes/i2c-mux-pca954x.c+0−1
@@ -300,7 +300,6 @@ static struct i2c_driver pca954x_driver = { · 299 unmodified lines
300300 .driver = {
301301 .name = "pca954x",
302302 .pm = &pca954x_pm,
303− .owner = THIS_MODULE,
304303 },
305304 .probe = pca954x_probe,
306305 .remove = pca954x_remove,
drivers/i2c/muxes/i2c-mux-pinctrl.c+1−0
@@ -111,6 +111,7 @@ static int i2c_mux_pinctrl_parse_dt(struct i2c_mux_pinctrl *mux, · 110 unmodified lines
111111 return -ENODEV;
112112 }
113113 adapter = of_find_i2c_adapter_by_node(adapter_np);
114+ of_node_put(adapter_np);
114115 if (!adapter) {
115116 dev_err(mux->dev, "Cannot find parent bus\n");
116117 return -EPROBE_DEFER;
drivers/i2c/muxes/i2c-mux-reg.c+290−0
@@ -0,0 +1,290 @@
1+/*
2+ * I2C multiplexer using a single register
3+ *
4+ * Copyright 2015 Freescale Semiconductor
5+ * York Sun <yorksun@freescale.com>
6+ *
7+ * This program is free software; you can redistribute it and/or modify it
8+ * under the terms of the GNU General Public License as published by the
9+ * Free Software Foundation; either version 2 of the License, or (at your
10+ * option) any later version.
11+ */
12+
13+#include <linux/i2c.h>
14+#include <linux/i2c-mux.h>
15+#include <linux/init.h>
16+#include <linux/io.h>
17+#include <linux/module.h>
18+#include <linux/of_address.h>
19+#include <linux/platform_data/i2c-mux-reg.h>
20+#include <linux/platform_device.h>
21+#include <linux/slab.h>
22+
23+struct regmux {
24+ struct i2c_adapter *parent;
25+ struct i2c_adapter **adap; /* child busses */
26+ struct i2c_mux_reg_platform_data data;
27+};
28+
29+static int i2c_mux_reg_set(const struct regmux *mux, unsigned int chan_id)
30+{
31+ if (!mux->data.reg)
32+ return -EINVAL;
33+
34+ /*
35+ * Write to the register, followed by a read to ensure the write is
36+ * completed on a "posted" bus, for example PCI or write buffers.
37+ * The endianness of reading doesn't matter and the return data
38+ * is not used.
39+ */
40+ switch (mux->data.reg_size) {
41+ case 4:
42+ if (mux->data.little_endian)
43+ iowrite32(chan_id, mux->data.reg);
44+ else
45+ iowrite32be(chan_id, mux->data.reg);
46+ if (!mux->data.write_only)
47+ ioread32(mux->data.reg);
48+ break;
49+ case 2:
50+ if (mux->data.little_endian)
51+ iowrite16(chan_id, mux->data.reg);
52+ else
53+ iowrite16be(chan_id, mux->data.reg);
54+ if (!mux->data.write_only)
55+ ioread16(mux->data.reg);
56+ break;
57+ case 1:
58+ iowrite8(chan_id, mux->data.reg);
59+ if (!mux->data.write_only)
60+ ioread8(mux->data.reg);
61+ break;
62+ }
63+
64+ return 0;
65+}
66+
67+static int i2c_mux_reg_select(struct i2c_adapter *adap, void *data,
68+ unsigned int chan)
69+{
70+ struct regmux *mux = data;
71+
72+ return i2c_mux_reg_set(mux, chan);
73+}
74+
75+static int i2c_mux_reg_deselect(struct i2c_adapter *adap, void *data,
76+ unsigned int chan)
77+{
78+ struct regmux *mux = data;
79+
80+ if (mux->data.idle_in_use)
81+ return i2c_mux_reg_set(mux, mux->data.idle);
82+
83+ return 0;
84+}
85+
86+#ifdef CONFIG_OF
87+static int i2c_mux_reg_probe_dt(struct regmux *mux,
88+ struct platform_device *pdev)
89+{
90+ struct device_node *np = pdev->dev.of_node;
91+ struct device_node *adapter_np, *child;
92+ struct i2c_adapter *adapter;
93+ struct resource res;
94+ unsigned *values;
95+ int i = 0;
96+
97+ if (!np)
98+ return -ENODEV;
99+
100+ adapter_np = of_parse_phandle(np, "i2c-parent", 0);
101+ if (!adapter_np) {
102+ dev_err(&pdev->dev, "Cannot parse i2c-parent\n");
103+ return -ENODEV;
104+ }
105+ adapter = of_find_i2c_adapter_by_node(adapter_np);
106+ of_node_put(adapter_np);
107+ if (!adapter)
108+ return -EPROBE_DEFER;
109+
110+ mux->parent = adapter;
111+ mux->data.parent = i2c_adapter_id(adapter);
112+ put_device(&adapter->dev);
113+
114+ mux->data.n_values = of_get_child_count(np);
115+ if (of_find_property(np, "little-endian", NULL)) {
116+ mux->data.little_endian = true;
117+ } else if (of_find_property(np, "big-endian", NULL)) {
118+ mux->data.little_endian = false;
119+ } else {
120+#if defined(__BYTE_ORDER) ? __BYTE_ORDER == __LITTLE_ENDIAN : \
121+ defined(__LITTLE_ENDIAN)
122+ mux->data.little_endian = true;
123+#elif defined(__BYTE_ORDER) ? __BYTE_ORDER == __BIG_ENDIAN : \
124+ defined(__BIG_ENDIAN)
125+ mux->data.little_endian = false;
126+#else
127+#error Endianness not defined?
128+#endif
129+ }
130+ if (of_find_property(np, "write-only", NULL))
131+ mux->data.write_only = true;
132+ else
133+ mux->data.write_only = false;
134+
135+ values = devm_kzalloc(&pdev->dev,
136+ sizeof(*mux->data.values) * mux->data.n_values,
137+ GFP_KERNEL);
138+ if (!values) {
139+ dev_err(&pdev->dev, "Cannot allocate values array");
140+ return -ENOMEM;
141+ }
142+
143+ for_each_child_of_node(np, child) {
144+ of_property_read_u32(child, "reg", values + i);
145+ i++;
146+ }
147+ mux->data.values = values;
148+
149+ if (!of_property_read_u32(np, "idle-state", &mux->data.idle))
150+ mux->data.idle_in_use = true;
151+
152+ /* map address from "reg" if exists */
153+ if (of_address_to_resource(np, 0, &res)) {
154+ mux->data.reg_size = resource_size(&res);
155+ mux->data.reg = devm_ioremap_resource(&pdev->dev, &res);
156+ if (IS_ERR(mux->data.reg))
157+ return PTR_ERR(mux->data.reg);
158+ }
159+
160+ return 0;
161+}
162+#else
163+static int i2c_mux_reg_probe_dt(struct regmux *mux,
164+ struct platform_device *pdev)
165+{
166+ return 0;
167+}
168+#endif
169+
170+static int i2c_mux_reg_probe(struct platform_device *pdev)
171+{
172+ struct regmux *mux;
173+ struct i2c_adapter *parent;
174+ struct resource *res;
175+ int (*deselect)(struct i2c_adapter *, void *, u32);
176+ unsigned int class;
177+ int i, ret, nr;
178+
179+ mux = devm_kzalloc(&pdev->dev, sizeof(*mux), GFP_KERNEL);
180+ if (!mux)
181+ return -ENOMEM;
182+
183+ platform_set_drvdata(pdev, mux);
184+
185+ if (dev_get_platdata(&pdev->dev)) {
186+ memcpy(&mux->data, dev_get_platdata(&pdev->dev),
187+ sizeof(mux->data));
188+
189+ parent = i2c_get_adapter(mux->data.parent);
190+ if (!parent)
191+ return -EPROBE_DEFER;
192+
193+ mux->parent = parent;
194+ } else {
195+ ret = i2c_mux_reg_probe_dt(mux, pdev);
196+ if (ret < 0) {
197+ dev_err(&pdev->dev, "Error parsing device tree");
198+ return ret;
199+ }
200+ }
201+
202+ if (!mux->data.reg) {
203+ dev_info(&pdev->dev,
204+ "Register not set, using platform resource\n");
205+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
206+ mux->data.reg_size = resource_size(res);
207+ mux->data.reg = devm_ioremap_resource(&pdev->dev, res);
208+ if (IS_ERR(mux->data.reg))
209+ return PTR_ERR(mux->data.reg);
210+ }
211+
212+ if (mux->data.reg_size != 4 && mux->data.reg_size != 2 &&
213+ mux->data.reg_size != 1) {
214+ dev_err(&pdev->dev, "Invalid register size\n");
215+ return -EINVAL;
216+ }
217+
218+ mux->adap = devm_kzalloc(&pdev->dev,
219+ sizeof(*mux->adap) * mux->data.n_values,
220+ GFP_KERNEL);
221+ if (!mux->adap) {
222+ dev_err(&pdev->dev, "Cannot allocate i2c_adapter structure");
223+ return -ENOMEM;
224+ }
225+
226+ if (mux->data.idle_in_use)
227+ deselect = i2c_mux_reg_deselect;
228+ else
229+ deselect = NULL;
230+
231+ for (i = 0; i < mux->data.n_values; i++) {
232+ nr = mux->data.base_nr ? (mux->data.base_nr + i) : 0;
233+ class = mux->data.classes ? mux->data.classes[i] : 0;
234+
235+ mux->adap[i] = i2c_add_mux_adapter(mux->parent, &pdev->dev, mux,
236+ nr, mux->data.values[i],
237+ class, i2c_mux_reg_select,
238+ deselect);
239+ if (!mux->adap[i]) {
240+ ret = -ENODEV;
241+ dev_err(&pdev->dev, "Failed to add adapter %d\n", i);
242+ goto add_adapter_failed;
243+ }
244+ }
245+
246+ dev_dbg(&pdev->dev, "%d port mux on %s adapter\n",
247+ mux->data.n_values, mux->parent->name);
248+
249+ return 0;
250+
251+add_adapter_failed:
252+ for (; i > 0; i--)
253+ i2c_del_mux_adapter(mux->adap[i - 1]);
254+
255+ return ret;
256+}
257+
258+static int i2c_mux_reg_remove(struct platform_device *pdev)
259+{
260+ struct regmux *mux = platform_get_drvdata(pdev);
261+ int i;
262+
263+ for (i = 0; i < mux->data.n_values; i++)
264+ i2c_del_mux_adapter(mux->adap[i]);
265+
266+ i2c_put_adapter(mux->parent);
267+
268+ return 0;
269+}
270+
271+static const struct of_device_id i2c_mux_reg_of_match[] = {
272+ { .compatible = "i2c-mux-reg", },
273+ {},
274+};
275+MODULE_DEVICE_TABLE(of, i2c_mux_reg_of_match);
276+
277+static struct platform_driver i2c_mux_reg_driver = {
278+ .probe = i2c_mux_reg_probe,
279+ .remove = i2c_mux_reg_remove,
280+ .driver = {
281+ .name = "i2c-mux-reg",
282+ },
283+};
284+
285+module_platform_driver(i2c_mux_reg_driver);
286+
287+MODULE_DESCRIPTION("Register-based I2C multiplexer driver");
288+MODULE_AUTHOR("York Sun <yorksun@freescale.com>");
289+MODULE_LICENSE("GPL");
290+MODULE_ALIAS("platform:i2c-mux-reg");
drivers/misc/eeprom/at24.c+6−31
@@ -186,19 +186,11 @@ static ssize_t at24_eeprom_read(struct at24_data *at24, char *buf, · 185 unmodified lines
186186 if (count > io_limit)
187187 count = io_limit;
188188
189− switch (at24->use_smbus) {
190− case I2C_SMBUS_I2C_BLOCK_DATA:
189+ if (at24->use_smbus) {
191190 /* Smaller eeproms can work given some SMBus extension calls */
192191 if (count > I2C_SMBUS_BLOCK_MAX)
193192 count = I2C_SMBUS_BLOCK_MAX;
194− break;
195− case I2C_SMBUS_WORD_DATA:
196− count = 2;
197− break;
198− case I2C_SMBUS_BYTE_DATA:
199− count = 1;
200− break;
201− default:
193+ } else {
202194 /*
203195 * When we have a better choice than SMBus calls, use a
204196 * combined I2C message. Write address; then read up to
@@ -229,27 +221,10 @@ static ssize_t at24_eeprom_read(struct at24_data *at24, char *buf, · 24 unmodified lines
229221 timeout = jiffies + msecs_to_jiffies(write_timeout);
230222 do {
231223 read_time = jiffies;
232− switch (at24->use_smbus) {
233− case I2C_SMBUS_I2C_BLOCK_DATA:
234− status = i2c_smbus_read_i2c_block_data(client, offset,
235− count, buf);
236− break;
237− case I2C_SMBUS_WORD_DATA:
238− status = i2c_smbus_read_word_data(client, offset);
239− if (status >= 0) {
240− buf[0] = status & 0xff;
241− buf[1] = status >> 8;
242− status = count;
243− }
244− break;
245− case I2C_SMBUS_BYTE_DATA:
246− status = i2c_smbus_read_byte_data(client, offset);
247− if (status >= 0) {
248− buf[0] = status;
249− status = count;
250− }
251− break;
252− default:
224+ if (at24->use_smbus) {
225+ status = i2c_smbus_read_i2c_block_data_or_emulated(client, offset,
226+ count, buf);
227+ } else {
253228 status = i2c_transfer(client->adapter, msg, 2);
254229 if (status == 2)
255230 status = count;
drivers/misc/eeprom/max6875.c+1−0
@@ -191,6 +191,7 @@ static const struct i2c_device_id max6875_id[] = { · 190 unmodified lines
191191 { "max6875", 0 },
192192 { }
193193 };
194+MODULE_DEVICE_TABLE(i2c, max6875_id);
194195
195196 static struct i2c_driver max6875_driver = {
196197 .driver = {
drivers/of/irq.c+1−0
@@ -432,6 +432,7 @@ int of_irq_get_byname(struct device_node *dev, const char *name) · 431 unmodified lines
432432
433433 return of_irq_get(dev, index);
434434 }
435+EXPORT_SYMBOL_GPL(of_irq_get_byname);
435436
436437 /**
437438 * of_irq_count - Count the number of IRQs a node uses
include/dt-bindings/i2c/i2c.h+18−0
@@ -0,0 +1,18 @@
1+/*
2+ * This header provides constants for I2C bindings
3+ *
4+ * Copyright (C) 2015 by Sang Engineering
5+ * Copyright (C) 2015 by Renesas Electronics Corporation
6+ *
7+ * Wolfram Sang <wsa@sang-engineering.com>
8+ *
9+ * GPLv2 only
10+ */
11+
12+#ifndef _DT_BINDINGS_I2C_I2C_H
13+#define _DT_BINDINGS_I2C_I2C_H
14+
15+#define I2C_TEN_BIT_ADDRESS (1 << 31)
16+#define I2C_OWN_SLAVE_ADDRESS (1 << 30)
17+
18+#endif
include/linux/i2c.h+15−4
@@ -121,6 +121,9 @@ extern s32 i2c_smbus_read_i2c_block_data(const struct i2c_client *client, · 120 unmodified lines
121121 extern s32 i2c_smbus_write_i2c_block_data(const struct i2c_client *client,
122122 u8 command, u8 length,
123123 const u8 *values);
124+extern s32
125+i2c_smbus_read_i2c_block_data_or_emulated(const struct i2c_client *client,
126+ u8 command, u8 length, u8 *values);
124127 #endif /* I2C */
125128
126129 /**
@@ -550,11 +553,12 @@ void i2c_lock_adapter(struct i2c_adapter *); · 423 unmodified lines
550553 void i2c_unlock_adapter(struct i2c_adapter *);
551554
552555 /*flags for the client struct: */
553−#define I2C_CLIENT_PEC 0x04 /* Use Packet Error Checking */
554−#define I2C_CLIENT_TEN 0x10 /* we have a ten bit chip address */
556+#define I2C_CLIENT_PEC 0x04 /* Use Packet Error Checking */
557+#define I2C_CLIENT_TEN 0x10 /* we have a ten bit chip address */
555558 /* Must equal I2C_M_TEN below */
556−#define I2C_CLIENT_WAKE 0x80 /* for board_info; true iff can wake */
557−#define I2C_CLIENT_SCCB 0x9000 /* Use Omnivision SCCB protocol */
559+#define I2C_CLIENT_SLAVE 0x20 /* we are the slave */
560+#define I2C_CLIENT_WAKE 0x80 /* for board_info; true iff can wake */
561+#define I2C_CLIENT_SCCB 0x9000 /* Use Omnivision SCCB protocol */
558562 /* Must match I2C_M_STOP|IGNORE_NAK */
559563
560564 /* i2c adapter classes (bitmask) */
@@ -638,6 +642,8 @@ extern struct i2c_client *of_find_i2c_device_by_node(struct device_node *node); · 77 unmodified lines
638642 /* must call put_device() when done with returned i2c_adapter device */
639643 extern struct i2c_adapter *of_find_i2c_adapter_by_node(struct device_node *node);
640644
645+/* must call i2c_put_adapter() when done with returned i2c_adapter device */
646+struct i2c_adapter *of_get_i2c_adapter_by_node(struct device_node *node);
641647 #else
642648
643649 static inline struct i2c_client *of_find_i2c_device_by_node(struct device_node *node)
@@ -649,6 +655,11 @@ static inline struct i2c_adapter *of_find_i2c_adapter_by_node(struct device_node · 5 unmodified lines
649655 {
650656 return NULL;
651657 }
658+
659+static inline struct i2c_adapter *of_get_i2c_adapter_by_node(struct device_node *node)
660+{
661+ return NULL;
662+}
652663 #endif /* CONFIG_OF */
653664
654665 #endif /* _LINUX_I2C_H */
include/linux/platform_data/i2c-mux-reg.h+44−0
@@ -0,0 +1,44 @@
1+/*
2+ * I2C multiplexer using a single register
3+ *
4+ * Copyright 2015 Freescale Semiconductor
5+ * York Sun <yorksun@freescale.com>
6+ *
7+ * This program is free software; you can redistribute it and/or modify it
8+ * under the terms of the GNU General Public License as published by the
9+ * Free Software Foundation; either version 2 of the License, or (at your
10+ * option) any later version.
11+ */
12+
13+#ifndef __LINUX_PLATFORM_DATA_I2C_MUX_REG_H
14+#define __LINUX_PLATFORM_DATA_I2C_MUX_REG_H
15+
16+/**
17+ * struct i2c_mux_reg_platform_data - Platform-dependent data for i2c-mux-reg
18+ * @parent: Parent I2C bus adapter number
19+ * @base_nr: Base I2C bus number to number adapters from or zero for dynamic
20+ * @values: Array of value for each channel
21+ * @n_values: Number of multiplexer channels
22+ * @little_endian: Indicating if the register is in little endian
23+ * @write_only: Reading the register is not allowed by hardware
24+ * @classes: Optional I2C auto-detection classes
25+ * @idle: Value to write to mux when idle
26+ * @idle_in_use: indicate if idle value is in use
27+ * @reg: Virtual address of the register to switch channel
28+ * @reg_size: register size in bytes
29+ */
30+struct i2c_mux_reg_platform_data {
31+ int parent;
32+ int base_nr;
33+ const unsigned int *values;
34+ int n_values;
35+ bool little_endian;
36+ bool write_only;
37+ const unsigned int *classes;
38+ u32 idle;
39+ bool idle_in_use;
40+ void __iomem *reg;
41+ resource_size_t reg_size;
42+};
43+
44+#endif /* __LINUX_PLATFORM_DATA_I2C_MUX_REG_H */