History

Merge tag 'timers-clocksource-2026-08-17' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip

Pull clocksource/event driver updates from Thomas Gleixner: - Remove redundant dev_err() and dev_err_probe() invocations in various drivers - Handle SWAP_IO_SPACE correctly in the rtl-otto driver - Make the Samsumg PWM timer driver PREEMPT_RT compatible - Ensure that the SUN4I timer is programmed with a delta larger than zero as a zero delta causes the the timer to be disabled - The usual fixes and improvements all over the place * tag 'timers-clocksource-2026-08-17' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: clocksource/drivers/armada: Unwind timer clock on init failure clocksource/drivers/rtl-otto: Change driver to use __raw reads and writes clocksource/drivers/samsung_pwm: Switch to raw_spinlock_t type clocksource/drivers/clps711x: Do not unmap clocksource MMIO clocksource/drivers/nxp-pit: Fix IRQ leak on cpuhp_setup_state error path clocksource/drivers/timer-sun4i: Advertise a real minimum delta clocksource: Remove redundant dev_err()/dev_err_probe() clocksource/drivers/sh_cmt: Use named initializers for platform_device_id arrays clocksource/drivers/sh_mtu2: Drop unused assignment of platform_device_id

Linus Torvalds committed 2 months ago

Commit b0239dd2 parents 030c9f8 0eaed8917 files · +62 −58Browse files

Unified · Split

17 files
  1. drivers/clocksource/arm_arch_timer_mmio.c +1 −3
  2. drivers/clocksource/clps711x-timer.c +1 −1
  3. drivers/clocksource/em_sti.c +1 −3
  4. drivers/clocksource/samsung_pwm_timer.c +11 −11
  5. drivers/clocksource/sh_cmt.c +2 −2
  6. drivers/clocksource/sh_mtu2.c +2 −2
  7. drivers/clocksource/sh_tmu.c +2 −2
  8. drivers/clocksource/timer-armada-370-xp.c +15 −3
  9. drivers/clocksource/timer-nxp-pit.c +3 −1
  10. drivers/clocksource/timer-nxp-stm.c +1 −1
  11. drivers/clocksource/timer-rtl-otto.c +7 −7
  12. drivers/clocksource/timer-sun4i.c +1 −1
  13. drivers/clocksource/timer-sun5i.c +1 −3
  14. drivers/clocksource/timer-tegra186.c +1 −3
  15. drivers/clocksource/timer-ti-dm.c +1 −3
  16. drivers/pwm/pwm-samsung.c +11 −11
  17. include/clocksource/samsung_pwm.h +1 −1
drivers/clocksource/arm_arch_timer_mmio.c+1−3
@@ -313,10 +313,8 @@ static int arch_timer_mmio_frame_register(struct platform_device *pdev, · 312 unmodified lines
313 ret = devm_request_irq(&pdev->dev, irq, arch_timer_mmio_handler,313 ret = devm_request_irq(&pdev->dev, irq, arch_timer_mmio_handler,
314 IRQF_TIMER | IRQF_NO_AUTOEN, "arch_mem_timer",314 IRQF_TIMER | IRQF_NO_AUTOEN, "arch_mem_timer",
315 &at->evt);315 &at->evt);
316 if (ret) {316 if (ret)
317 dev_err(&pdev->dev, "Failed to request mem timer irq\n");
318 return ret;317 return ret;
319 }
320 318
321 /* Afer this point, we're not allowed to fail anymore */319 /* Afer this point, we're not allowed to fail anymore */
322 arch_timer_mmio_setup(at, irq);320 arch_timer_mmio_setup(at, irq);
drivers/clocksource/clps711x-timer.c+1−1
@@ -94,7 +94,7 @@ static int __init clps711x_timer_init(struct device_node *np) · 93 unmodified lines
94 switch (of_alias_get_id(np, "timer")) {94 switch (of_alias_get_id(np, "timer")) {
95 case CLPS711X_CLKSRC_CLOCKSOURCE:95 case CLPS711X_CLKSRC_CLOCKSOURCE:
96 clps711x_clksrc_init(clock, base);96 clps711x_clksrc_init(clock, base);
97 break;97 return 0;
98 case CLPS711X_CLKSRC_CLOCKEVENT:98 case CLPS711X_CLKSRC_CLOCKEVENT:
99 ret = _clps711x_clkevt_init(clock, base, irq);99 ret = _clps711x_clkevt_init(clock, base, irq);
100 break;100 break;
drivers/clocksource/em_sti.c+1−3
@@ -300,10 +300,8 @@ static int em_sti_probe(struct platform_device *pdev) · 299 unmodified lines
300 ret = devm_request_irq(&pdev->dev, irq, em_sti_interrupt,300 ret = devm_request_irq(&pdev->dev, irq, em_sti_interrupt,
301 IRQF_TIMER | IRQF_IRQPOLL | IRQF_NOBALANCING,301 IRQF_TIMER | IRQF_IRQPOLL | IRQF_NOBALANCING,
302 dev_name(&pdev->dev), p);302 dev_name(&pdev->dev), p);
303 if (ret) {303 if (ret)
304 dev_err(&pdev->dev, "failed to request low IRQ\n");
305 return ret;304 return ret;
306 }
307 305
308 /* get hold of clock */306 /* get hold of clock */
309 p->clk = devm_clk_get(&pdev->dev, "sclk");307 p->clk = devm_clk_get(&pdev->dev, "sclk");
drivers/clocksource/samsung_pwm_timer.c+11−11
@@ -56,7 +56,7 @@ · 55 unmodified lines
56#define TCON_AUTORELOAD(chan) \56#define TCON_AUTORELOAD(chan) \
57 ((chan < 5) ? _TCON_AUTORELOAD(chan) : _TCON_AUTORELOAD4(chan))57 ((chan < 5) ? _TCON_AUTORELOAD(chan) : _TCON_AUTORELOAD4(chan))
58 58
59DEFINE_SPINLOCK(samsung_pwm_lock);59DEFINE_RAW_SPINLOCK(samsung_pwm_lock);
60EXPORT_SYMBOL(samsung_pwm_lock);60EXPORT_SYMBOL(samsung_pwm_lock);
61 61
62struct samsung_pwm_clocksource {62struct samsung_pwm_clocksource {
@@ -87,14 +87,14 @@ static void samsung_timer_set_prescale(unsigned int channel, u16 prescale) · 24 unmodified lines
87 if (channel >= 2)87 if (channel >= 2)
88 shift = TCFG0_PRESCALER1_SHIFT;88 shift = TCFG0_PRESCALER1_SHIFT;
89 89
90 spin_lock_irqsave(&samsung_pwm_lock, flags);90 raw_spin_lock_irqsave(&samsung_pwm_lock, flags);
91 91
92 reg = readl(pwm.base + REG_TCFG0);92 reg = readl(pwm.base + REG_TCFG0);
93 reg &= ~(TCFG0_PRESCALER_MASK << shift);93 reg &= ~(TCFG0_PRESCALER_MASK << shift);
94 reg |= (prescale - 1) << shift;94 reg |= (prescale - 1) << shift;
95 writel(reg, pwm.base + REG_TCFG0);95 writel(reg, pwm.base + REG_TCFG0);
96 96
97 spin_unlock_irqrestore(&samsung_pwm_lock, flags);97 raw_spin_unlock_irqrestore(&samsung_pwm_lock, flags);
98}98}
99 99
100static void samsung_timer_set_divisor(unsigned int channel, u8 divisor)100static void samsung_timer_set_divisor(unsigned int channel, u8 divisor)
@@ -106,14 +106,14 @@ static void samsung_timer_set_divisor(unsigned int channel, u8 divisor) · 5 unmodified lines
106 106
107 bits = (fls(divisor) - 1) - pwm.variant.div_base;107 bits = (fls(divisor) - 1) - pwm.variant.div_base;
108 108
109 spin_lock_irqsave(&samsung_pwm_lock, flags);109 raw_spin_lock_irqsave(&samsung_pwm_lock, flags);
110 110
111 reg = readl(pwm.base + REG_TCFG1);111 reg = readl(pwm.base + REG_TCFG1);
112 reg &= ~(TCFG1_MUX_MASK << shift);112 reg &= ~(TCFG1_MUX_MASK << shift);
113 reg |= bits << shift;113 reg |= bits << shift;
114 writel(reg, pwm.base + REG_TCFG1);114 writel(reg, pwm.base + REG_TCFG1);
115 115
116 spin_unlock_irqrestore(&samsung_pwm_lock, flags);116 raw_spin_unlock_irqrestore(&samsung_pwm_lock, flags);
117}117}
118 118
119static void samsung_time_stop(unsigned int channel)119static void samsung_time_stop(unsigned int channel)
@@ -124,13 +124,13 @@ static void samsung_time_stop(unsigned int channel) · 4 unmodified lines
124 if (channel > 0)124 if (channel > 0)
125 ++channel;125 ++channel;
126 126
127 spin_lock_irqsave(&samsung_pwm_lock, flags);127 raw_spin_lock_irqsave(&samsung_pwm_lock, flags);
128 128
129 tcon = readl_relaxed(pwm.base + REG_TCON);129 tcon = readl_relaxed(pwm.base + REG_TCON);
130 tcon &= ~TCON_START(channel);130 tcon &= ~TCON_START(channel);
131 writel_relaxed(tcon, pwm.base + REG_TCON);131 writel_relaxed(tcon, pwm.base + REG_TCON);
132 132
133 spin_unlock_irqrestore(&samsung_pwm_lock, flags);133 raw_spin_unlock_irqrestore(&samsung_pwm_lock, flags);
134}134}
135 135
136static void samsung_time_setup(unsigned int channel, unsigned long tcnt)136static void samsung_time_setup(unsigned int channel, unsigned long tcnt)
@@ -142,7 +142,7 @@ static void samsung_time_setup(unsigned int channel, unsigned long tcnt) · 5 unmodified lines
142 if (tcon_chan > 0)142 if (tcon_chan > 0)
143 ++tcon_chan;143 ++tcon_chan;
144 144
145 spin_lock_irqsave(&samsung_pwm_lock, flags);145 raw_spin_lock_irqsave(&samsung_pwm_lock, flags);
146 146
147 tcon = readl_relaxed(pwm.base + REG_TCON);147 tcon = readl_relaxed(pwm.base + REG_TCON);
148 148
@@ -153,7 +153,7 @@ static void samsung_time_setup(unsigned int channel, unsigned long tcnt) · 4 unmodified lines
153 writel_relaxed(tcnt, pwm.base + REG_TCMPB(channel));153 writel_relaxed(tcnt, pwm.base + REG_TCMPB(channel));
154 writel_relaxed(tcon, pwm.base + REG_TCON);154 writel_relaxed(tcon, pwm.base + REG_TCON);
155 155
156 spin_unlock_irqrestore(&samsung_pwm_lock, flags);156 raw_spin_unlock_irqrestore(&samsung_pwm_lock, flags);
157}157}
158 158
159static void samsung_time_start(unsigned int channel, bool periodic)159static void samsung_time_start(unsigned int channel, bool periodic)
@@ -164,7 +164,7 @@ static void samsung_time_start(unsigned int channel, bool periodic) · 4 unmodified lines
164 if (channel > 0)164 if (channel > 0)
165 ++channel;165 ++channel;
166 166
167 spin_lock_irqsave(&samsung_pwm_lock, flags);167 raw_spin_lock_irqsave(&samsung_pwm_lock, flags);
168 168
169 tcon = readl_relaxed(pwm.base + REG_TCON);169 tcon = readl_relaxed(pwm.base + REG_TCON);
170 170
@@ -178,7 +178,7 @@ static void samsung_time_start(unsigned int channel, bool periodic) · 7 unmodified lines
178 178
179 writel_relaxed(tcon, pwm.base + REG_TCON);179 writel_relaxed(tcon, pwm.base + REG_TCON);
180 180
181 spin_unlock_irqrestore(&samsung_pwm_lock, flags);181 raw_spin_unlock_irqrestore(&samsung_pwm_lock, flags);
182}182}
183 183
184static int samsung_set_next_event(unsigned long cycles,184static int samsung_set_next_event(unsigned long cycles,
drivers/clocksource/sh_cmt.c+2−2
@@ -974,8 +974,8 @@ static int sh_cmt_map_memory(struct sh_cmt_device *cmt) · 973 unmodified lines
974}974}
975 975
976static const struct platform_device_id sh_cmt_id_table[] = {976static const struct platform_device_id sh_cmt_id_table[] = {
977 { "sh-cmt-16", (kernel_ulong_t)&sh_cmt_info[SH_CMT_16BIT] },977 { .name = "sh-cmt-16", .driver_data = (kernel_ulong_t)&sh_cmt_info[SH_CMT_16BIT] },
978 { "sh-cmt-32", (kernel_ulong_t)&sh_cmt_info[SH_CMT_32BIT] },978 { .name = "sh-cmt-32", .driver_data = (kernel_ulong_t)&sh_cmt_info[SH_CMT_32BIT] },
979 { }979 { }
980};980};
981MODULE_DEVICE_TABLE(platform, sh_cmt_id_table);981MODULE_DEVICE_TABLE(platform, sh_cmt_id_table);
drivers/clocksource/sh_mtu2.c+2−2
@@ -484,8 +484,8 @@ static int sh_mtu2_probe(struct platform_device *pdev) · 483 unmodified lines
484}484}
485 485
486static const struct platform_device_id sh_mtu2_id_table[] = {486static const struct platform_device_id sh_mtu2_id_table[] = {
487 { "sh-mtu2", 0 },487 { .name = "sh-mtu2" },
488 { },488 { }
489};489};
490MODULE_DEVICE_TABLE(platform, sh_mtu2_id_table);490MODULE_DEVICE_TABLE(platform, sh_mtu2_id_table);
491 491
drivers/clocksource/sh_tmu.c+2−2
@@ -614,8 +614,8 @@ static int sh_tmu_probe(struct platform_device *pdev) · 613 unmodified lines
614}614}
615 615
616static const struct platform_device_id sh_tmu_id_table[] = {616static const struct platform_device_id sh_tmu_id_table[] = {
617 { "sh-tmu", SH_TMU },617 { .name = "sh-tmu", .driver_data = SH_TMU },
618 { "sh-tmu-sh3", SH_TMU_SH3 },618 { .name = "sh-tmu-sh3", .driver_data = SH_TMU_SH3 },
619 { }619 { }
620};620};
621MODULE_DEVICE_TABLE(platform, sh_tmu_id_table);621MODULE_DEVICE_TABLE(platform, sh_tmu_id_table);
drivers/clocksource/timer-armada-370-xp.c+15−3
@@ -349,7 +349,11 @@ static int __init armada_xp_timer_init(struct device_node *np) · 348 unmodified lines
349 349
350 timer_clk = clk_get_rate(clk);350 timer_clk = clk_get_rate(clk);
351 351
352 return armada_370_xp_timer_common_init(np);352 ret = armada_370_xp_timer_common_init(np);
353 if (ret)
354 clk_disable_unprepare(clk);
355
356 return ret;
353}357}
354TIMER_OF_DECLARE(armada_xp, "marvell,armada-xp-timer",358TIMER_OF_DECLARE(armada_xp, "marvell,armada-xp-timer",
355 armada_xp_timer_init);359 armada_xp_timer_init);
@@ -387,7 +391,11 @@ static int __init armada_375_timer_init(struct device_node *np) · 31 unmodified lines
387 timer25Mhz = false;391 timer25Mhz = false;
388 }392 }
389 393
390 return armada_370_xp_timer_common_init(np);394 ret = armada_370_xp_timer_common_init(np);
395 if (ret)
396 clk_disable_unprepare(clk);
397
398 return ret;
391}399}
392TIMER_OF_DECLARE(armada_375, "marvell,armada-375-timer",400TIMER_OF_DECLARE(armada_375, "marvell,armada-375-timer",
393 armada_375_timer_init);401 armada_375_timer_init);
@@ -410,7 +418,11 @@ static int __init armada_370_timer_init(struct device_node *np) · 16 unmodified lines
410 timer_clk = clk_get_rate(clk) / TIMER_DIVIDER;418 timer_clk = clk_get_rate(clk) / TIMER_DIVIDER;
411 timer25Mhz = false;419 timer25Mhz = false;
412 420
413 return armada_370_xp_timer_common_init(np);421 ret = armada_370_xp_timer_common_init(np);
422 if (ret)
423 clk_disable_unprepare(clk);
424
425 return ret;
414}426}
415TIMER_OF_DECLARE(armada_370, "marvell,armada-370-timer",427TIMER_OF_DECLARE(armada_370, "marvell,armada-370-timer",
416 armada_370_timer_init);428 armada_370_timer_init);
drivers/clocksource/timer-nxp-pit.c+3−1
@@ -328,8 +328,10 @@ static int pit_timer_init(struct device_node *np) · 327 unmodified lines
328 if (pit_instances == max_pit_instances) {328 if (pit_instances == max_pit_instances) {
329 ret = cpuhp_setup_state(CPUHP_AP_ONLINE_DYN, "PIT timer:starting",329 ret = cpuhp_setup_state(CPUHP_AP_ONLINE_DYN, "PIT timer:starting",
330 pit_clockevent_starting_cpu, NULL);330 pit_clockevent_starting_cpu, NULL);
331 if (ret < 0)331 if (ret < 0) {
332 pit_clockevent_per_cpu_exit(pit, pit_instances);
332 goto out_pit_clocksource_unregister;333 goto out_pit_clocksource_unregister;
334 }
333 }335 }
334 336
335 return 0;337 return 0;
drivers/clocksource/timer-nxp-stm.c+1−1
@@ -441,7 +441,7 @@ static int nxp_stm_timer_probe(struct platform_device *pdev) · 440 unmodified lines
441 ret = devm_request_irq(dev, irq, nxp_stm_module_interrupt,441 ret = devm_request_irq(dev, irq, nxp_stm_module_interrupt,
442 IRQF_TIMER | IRQF_NOBALANCING, name, stm_timer);442 IRQF_TIMER | IRQF_NOBALANCING, name, stm_timer);
443 if (ret)443 if (ret)
444 return dev_err_probe(dev, ret, "Unable to allocate interrupt line\n");444 return ret;
445 445
446 ret = nxp_stm_clocksource_init(dev, stm_timer, name, base, clk);446 ret = nxp_stm_clocksource_init(dev, stm_timer, name, base, clk);
447 if (ret)447 if (ret)
drivers/clocksource/timer-rtl-otto.c+7−7
@@ -56,37 +56,37 @@ struct rttm_cs { · 55 unmodified lines
56/* Simple internal register functions */56/* Simple internal register functions */
57static inline unsigned int rttm_get_counter(void __iomem *base)57static inline unsigned int rttm_get_counter(void __iomem *base)
58{58{
59 return ioread32(base + RTTM_CNT);59 return __raw_readl(base + RTTM_CNT);
60}60}
61 61
62static inline void rttm_set_period(void __iomem *base, unsigned int period)62static inline void rttm_set_period(void __iomem *base, unsigned int period)
63{63{
64 iowrite32(period, base + RTTM_DATA);64 __raw_writel(period, base + RTTM_DATA);
65}65}
66 66
67static inline void rttm_disable_timer(void __iomem *base)67static inline void rttm_disable_timer(void __iomem *base)
68{68{
69 iowrite32(0, base + RTTM_CTRL);69 __raw_writel(0, base + RTTM_CTRL);
70}70}
71 71
72static inline void rttm_enable_timer(void __iomem *base, u32 mode, u32 divisor)72static inline void rttm_enable_timer(void __iomem *base, u32 mode, u32 divisor)
73{73{
74 iowrite32(RTTM_CTRL_ENABLE | mode | divisor, base + RTTM_CTRL);74 __raw_writel(RTTM_CTRL_ENABLE | mode | divisor, base + RTTM_CTRL);
75}75}
76 76
77static inline void rttm_ack_irq(void __iomem *base)77static inline void rttm_ack_irq(void __iomem *base)
78{78{
79 iowrite32(ioread32(base + RTTM_INT) | RTTM_INT_PENDING, base + RTTM_INT);79 __raw_writel(__raw_readl(base + RTTM_INT) | RTTM_INT_PENDING, base + RTTM_INT);
80}80}
81 81
82static inline void rttm_enable_irq(void __iomem *base)82static inline void rttm_enable_irq(void __iomem *base)
83{83{
84 iowrite32(RTTM_INT_ENABLE, base + RTTM_INT);84 __raw_writel(RTTM_INT_ENABLE, base + RTTM_INT);
85}85}
86 86
87static inline void rttm_disable_irq(void __iomem *base)87static inline void rttm_disable_irq(void __iomem *base)
88{88{
89 iowrite32(0, base + RTTM_INT);89 __raw_writel(0, base + RTTM_INT);
90}90}
91 91
92/* Aggregated control functions for kernel clock framework */92/* Aggregated control functions for kernel clock framework */
drivers/clocksource/timer-sun4i.c+1−1
@@ -208,7 +208,7 @@ static int __init sun4i_timer_init(struct device_node *node) · 207 unmodified lines
208 sun4i_timer_clear_interrupt(timer_of_base(&to));208 sun4i_timer_clear_interrupt(timer_of_base(&to));
209 209
210 clockevents_config_and_register(&to.clkevt, timer_of_rate(&to),210 clockevents_config_and_register(&to.clkevt, timer_of_rate(&to),
211 TIMER_SYNC_TICKS, 0xffffffff);211 TIMER_SYNC_TICKS + 1, 0xffffffff);
212 212
213 /* Enable timer0 interrupt */213 /* Enable timer0 interrupt */
214 val = readl(timer_of_base(&to) + TIMER_IRQ_EN_REG);214 val = readl(timer_of_base(&to) + TIMER_IRQ_EN_REG);
drivers/clocksource/timer-sun5i.c+1−3
@@ -247,10 +247,8 @@ static int sun5i_setup_clockevent(struct platform_device *pdev, · 246 unmodified lines
247 ret = devm_request_irq(dev, irq, sun5i_timer_interrupt,247 ret = devm_request_irq(dev, irq, sun5i_timer_interrupt,
248 IRQF_TIMER | IRQF_IRQPOLL,248 IRQF_TIMER | IRQF_IRQPOLL,
249 "sun5i_timer0", ce);249 "sun5i_timer0", ce);
250 if (ret) {250 if (ret)
251 dev_err(dev, "Unable to register interrupt\n");
252 return ret;251 return ret;
253 }
254 252
255 return 0;253 return 0;
256}254}
drivers/clocksource/timer-tegra186.c+1−3
@@ -532,10 +532,8 @@ static int tegra186_timer_probe(struct platform_device *pdev) · 531 unmodified lines
532 if (kernel_wdt) {532 if (kernel_wdt) {
533 err = devm_request_irq(dev, irq, tegra186_wdt_irq, 0,533 err = devm_request_irq(dev, irq, tegra186_wdt_irq, 0,
534 dev_name(dev), kernel_wdt);534 dev_name(dev), kernel_wdt);
535 if (err < 0) {535 if (err < 0)
536 dev_err(dev, "failed to request kernel WDT IRQ: %d\n", err);
537 goto unregister_usec;536 goto unregister_usec;
538 }
539 537
540 tegra186_wdt_set_timeout(&kernel_wdt->base, TEGRA186_KERNEL_WDT_TIMEOUT);538 tegra186_wdt_set_timeout(&kernel_wdt->base, TEGRA186_KERNEL_WDT_TIMEOUT);
541 tegra186_wdt_enable(kernel_wdt);539 tegra186_wdt_enable(kernel_wdt);
drivers/clocksource/timer-ti-dm.c+1−3
@@ -1375,10 +1375,8 @@ static int omap_dm_timer_setup_clockevent(struct dmtimer *timer) · 1374 unmodified lines
1375 1375
1376 ret = devm_request_irq(dev, timer->irq, omap_dm_timer_evt_interrupt,1376 ret = devm_request_irq(dev, timer->irq, omap_dm_timer_evt_interrupt,
1377 IRQF_TIMER, "omap_dm_timer_clockevent", clkevt);1377 IRQF_TIMER, "omap_dm_timer_clockevent", clkevt);
1378 if (ret) {1378 if (ret)
1379 dev_err(dev, "Failed to request interrupt: %d\n", ret);
1380 return ret;1379 return ret;
1381 }
1382 1380
1383 __omap_dm_timer_int_enable(timer, OMAP_TIMER_INT_OVERFLOW);1381 __omap_dm_timer_int_enable(timer, OMAP_TIMER_INT_OVERFLOW);
1384 1382
drivers/pwm/pwm-samsung.c+11−11
@@ -102,7 +102,7 @@ struct samsung_pwm_chip { · 101 unmodified lines
102 * IP. Should this change, both drivers will need to be modified to102 * IP. Should this change, both drivers will need to be modified to
103 * properly synchronize accesses to particular instances.103 * properly synchronize accesses to particular instances.
104 */104 */
105static DEFINE_SPINLOCK(samsung_pwm_lock);105static DEFINE_RAW_SPINLOCK(samsung_pwm_lock);
106#endif106#endif
107 107
108static inline108static inline
@@ -141,14 +141,14 @@ static void pwm_samsung_set_divisor(struct samsung_pwm_chip *our_chip, · 32 unmodified lines
141 141
142 bits = (fls(divisor) - 1) - our_chip->variant.div_base;142 bits = (fls(divisor) - 1) - our_chip->variant.div_base;
143 143
144 spin_lock_irqsave(&samsung_pwm_lock, flags);144 raw_spin_lock_irqsave(&samsung_pwm_lock, flags);
145 145
146 reg = readl(our_chip->base + REG_TCFG1);146 reg = readl(our_chip->base + REG_TCFG1);
147 reg &= ~(TCFG1_MUX_MASK << shift);147 reg &= ~(TCFG1_MUX_MASK << shift);
148 reg |= bits << shift;148 reg |= bits << shift;
149 writel(reg, our_chip->base + REG_TCFG1);149 writel(reg, our_chip->base + REG_TCFG1);
150 150
151 spin_unlock_irqrestore(&samsung_pwm_lock, flags);151 raw_spin_unlock_irqrestore(&samsung_pwm_lock, flags);
152}152}
153 153
154static int pwm_samsung_is_tdiv(struct samsung_pwm_chip *our_chip, unsigned int chan)154static int pwm_samsung_is_tdiv(struct samsung_pwm_chip *our_chip, unsigned int chan)
@@ -249,7 +249,7 @@ static int pwm_samsung_enable(struct pwm_chip *chip, struct pwm_device *pwm) · 94 unmodified lines
249 unsigned long flags;249 unsigned long flags;
250 u32 tcon;250 u32 tcon;
251 251
252 spin_lock_irqsave(&samsung_pwm_lock, flags);252 raw_spin_lock_irqsave(&samsung_pwm_lock, flags);
253 253
254 tcon = readl(our_chip->base + REG_TCON);254 tcon = readl(our_chip->base + REG_TCON);
255 255
@@ -263,7 +263,7 @@ static int pwm_samsung_enable(struct pwm_chip *chip, struct pwm_device *pwm) · 7 unmodified lines
263 263
264 our_chip->disabled_mask &= ~BIT(pwm->hwpwm);264 our_chip->disabled_mask &= ~BIT(pwm->hwpwm);
265 265
266 spin_unlock_irqrestore(&samsung_pwm_lock, flags);266 raw_spin_unlock_irqrestore(&samsung_pwm_lock, flags);
267 267
268 return 0;268 return 0;
269}269}
@@ -275,7 +275,7 @@ static void pwm_samsung_disable(struct pwm_chip *chip, struct pwm_device *pwm) · 5 unmodified lines
275 unsigned long flags;275 unsigned long flags;
276 u32 tcon;276 u32 tcon;
277 277
278 spin_lock_irqsave(&samsung_pwm_lock, flags);278 raw_spin_lock_irqsave(&samsung_pwm_lock, flags);
279 279
280 tcon = readl(our_chip->base + REG_TCON);280 tcon = readl(our_chip->base + REG_TCON);
281 tcon &= ~TCON_AUTORELOAD(tcon_chan);281 tcon &= ~TCON_AUTORELOAD(tcon_chan);
@@ -290,7 +290,7 @@ static void pwm_samsung_disable(struct pwm_chip *chip, struct pwm_device *pwm) · 8 unmodified lines
290 290
291 our_chip->disabled_mask |= BIT(pwm->hwpwm);291 our_chip->disabled_mask |= BIT(pwm->hwpwm);
292 292
293 spin_unlock_irqrestore(&samsung_pwm_lock, flags);293 raw_spin_unlock_irqrestore(&samsung_pwm_lock, flags);
294}294}
295 295
296static void pwm_samsung_manual_update(struct samsung_pwm_chip *our_chip,296static void pwm_samsung_manual_update(struct samsung_pwm_chip *our_chip,
@@ -298,11 +298,11 @@ static void pwm_samsung_manual_update(struct samsung_pwm_chip *our_chip, · 1 unmodified line
298{298{
299 unsigned long flags;299 unsigned long flags;
300 300
301 spin_lock_irqsave(&samsung_pwm_lock, flags);301 raw_spin_lock_irqsave(&samsung_pwm_lock, flags);
302 302
303 __pwm_samsung_manual_update(our_chip, pwm);303 __pwm_samsung_manual_update(our_chip, pwm);
304 304
305 spin_unlock_irqrestore(&samsung_pwm_lock, flags);305 raw_spin_unlock_irqrestore(&samsung_pwm_lock, flags);
306}306}
307 307
308static int __pwm_samsung_config(struct pwm_chip *chip, struct pwm_device *pwm,308static int __pwm_samsung_config(struct pwm_chip *chip, struct pwm_device *pwm,
@@ -390,7 +390,7 @@ static void pwm_samsung_set_invert(struct samsung_pwm_chip *our_chip, · 81 unmodified lines
390 unsigned long flags;390 unsigned long flags;
391 u32 tcon;391 u32 tcon;
392 392
393 spin_lock_irqsave(&samsung_pwm_lock, flags);393 raw_spin_lock_irqsave(&samsung_pwm_lock, flags);
394 394
395 tcon = readl(our_chip->base + REG_TCON);395 tcon = readl(our_chip->base + REG_TCON);
396 396
@@ -404,7 +404,7 @@ static void pwm_samsung_set_invert(struct samsung_pwm_chip *our_chip, · 7 unmodified lines
404 404
405 writel(tcon, our_chip->base + REG_TCON);405 writel(tcon, our_chip->base + REG_TCON);
406 406
407 spin_unlock_irqrestore(&samsung_pwm_lock, flags);407 raw_spin_unlock_irqrestore(&samsung_pwm_lock, flags);
408}408}
409 409
410static int pwm_samsung_set_polarity(struct pwm_chip *chip,410static int pwm_samsung_set_polarity(struct pwm_chip *chip,
include/clocksource/samsung_pwm.h+1−1
@@ -15,7 +15,7 @@ · 14 unmodified lines
15 * spinlock is not shared between both drivers.15 * spinlock is not shared between both drivers.
16 */16 */
17#ifdef CONFIG_CLKSRC_SAMSUNG_PWM17#ifdef CONFIG_CLKSRC_SAMSUNG_PWM
18extern spinlock_t samsung_pwm_lock;18extern raw_spinlock_t samsung_pwm_lock;
19#endif19#endif
20 20
21struct samsung_pwm_variant {21struct samsung_pwm_variant {