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Merge branches 'apple/dart', 'arm/mediatek', 'arm/msm', 'arm/smmu', 'ppc/pamu', 'x86/vt-d', 'x86/amd' and 'vfio-notifier-fix' into next

Joerg Roedel committed 4 years ago

Commit b0dacee8 parents ee53543 de78657 8b9ad48 b11deb2 cae8d1f 0d647b3 42bb5aa fa7e9ec787 files · +9031 −4685Browse files

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41 files
  1. include/asm-generic/bug.h +6 −5
  2. include/dt-bindings/clock/microchip,mpfs-clock.h +4 −1
  3. include/dt-bindings/memory/mt8186-memory-port.h +217 −0
  4. include/dt-bindings/memory/mt8195-memory-port.h +408 −0
  5. include/dt-bindings/memory/mtk-memory-port.h +2 −0
  6. include/linux/amba/bus.h +8 −0
  7. include/linux/bio.h +4 −1
  8. include/linux/blk-mq.h +0 −1
  9. include/linux/cpu.h +1 −1
  10. include/linux/device/bus.h +3 −0
  11. include/linux/fsl/mc.h +8 −0
  12. include/linux/intel-iommu.h +2 −1
  13. include/linux/intel-svm.h +1 −1
  14. include/linux/iommu.h +44 −25
  15. include/linux/kernel.h +1 −1
  16. include/linux/mtd/mtd.h +2 −4
  17. include/linux/netdev_features.h +2 −2
  18. include/linux/netdevice.h +9 −12
  19. include/linux/pci.h +8 −0
  20. include/linux/platform_device.h +8 −2
  21. include/linux/stmmac.h +1 −0
  22. include/linux/sunrpc/clnt.h +1 −0
  23. include/linux/thunderbolt.h +2 −0
  24. include/linux/usb/pd_bdo.h +1 −1
  25. include/memory/renesas-rpc-if.h +1 −0
  26. include/net/bluetooth/hci.h +1 −0
  27. include/net/bluetooth/hci_core.h +4 −1
  28. include/net/inet_hashtables.h +1 −1
  29. include/net/ip6_tunnel.h +1 −1
  30. include/net/ip_tunnels.h +1 −1
  31. include/net/secure_seq.h +2 −2
  32. include/net/tc_act/tc_pedit.h +1 −0
  33. include/net/tcp.h +8 −0
  34. include/net/xsk_buff_pool.h +1 −0
  35. include/soc/mscc/ocelot_vcap.h +1 −1
  36. include/trace/events/sched.h +3 −3
  37. include/uapi/linux/elf.h +1 −1
  38. include/uapi/linux/fb.h +1 −1
  39. include/uapi/linux/kvm.h +9 −1
  40. include/uapi/linux/rfkill.h +1 −1
  41. include/uapi/linux/virtio_ids.h +7 −7
include/asm-generic/bug.h+6−5
@@ -21,6 +21,12 @@ · 20 unmodified lines
21#include <linux/panic.h>21#include <linux/panic.h>
22#include <linux/printk.h>22#include <linux/printk.h>
23 23
24struct warn_args;
25struct pt_regs;
26
27void __warn(const char *file, int line, void *caller, unsigned taint,
28 struct pt_regs *regs, struct warn_args *args);
29
24#ifdef CONFIG_BUG30#ifdef CONFIG_BUG
25 31
26#ifdef CONFIG_GENERIC_BUG32#ifdef CONFIG_GENERIC_BUG
@@ -110,11 +116,6 @@ extern __printf(1, 2) void __warn_printk(const char *fmt, ...); · 83 unmodified lines
110#endif116#endif
111 117
112/* used internally by panic.c */118/* used internally by panic.c */
113struct warn_args;
114struct pt_regs;
115
116void __warn(const char *file, int line, void *caller, unsigned taint,
117 struct pt_regs *regs, struct warn_args *args);
118 119
119#ifndef WARN_ON120#ifndef WARN_ON
120#define WARN_ON(condition) ({ \121#define WARN_ON(condition) ({ \
include/dt-bindings/clock/microchip,mpfs-clock.h+4−1
@@ -1,7 +1,7 @@
1/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */1/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
2/*2/*
3 * Daire McNamara,<daire.mcnamara@microchip.com>3 * Daire McNamara,<daire.mcnamara@microchip.com>
4 * Copyright (C) 2020 Microchip Technology Inc. All rights reserved.4 * Copyright (C) 2020-2022 Microchip Technology Inc. All rights reserved.
5 */5 */
6 6
7#ifndef _DT_BINDINGS_CLK_MICROCHIP_MPFS_H_7#ifndef _DT_BINDINGS_CLK_MICROCHIP_MPFS_H_
@@ -42,4 +42,7 @@ · 34 unmodified lines
42#define CLK_ATHENA 3142#define CLK_ATHENA 31
43#define CLK_CFM 3243#define CLK_CFM 32
44 44
45#define CLK_RTCREF 33
46#define CLK_MSSPLL 34
47
45#endif /* _DT_BINDINGS_CLK_MICROCHIP_MPFS_H_ */48#endif /* _DT_BINDINGS_CLK_MICROCHIP_MPFS_H_ */
include/dt-bindings/memory/mt8186-memory-port.h+217−0
@@ -0,0 +1,217 @@
1/* SPDX-License-Identifier: GPL-2.0-only */
2/*
3 * Copyright (c) 2022 MediaTek Inc.
4 *
5 * Author: Anan Sun <anan.sun@mediatek.com>
6 * Author: Yong Wu <yong.wu@mediatek.com>
7 */
8#ifndef _DT_BINDINGS_MEMORY_MT8186_LARB_PORT_H_
9#define _DT_BINDINGS_MEMORY_MT8186_LARB_PORT_H_
10
11#include <dt-bindings/memory/mtk-memory-port.h>
12
13/*
14 * MM IOMMU supports 16GB dma address. We separate it to four ranges:
15 * 0 ~ 4G; 4G ~ 8G; 8G ~ 12G; 12G ~ 16G, we could adjust these masters
16 * locate in anyone region. BUT:
17 * a) Make sure all the ports inside a larb are in one range.
18 * b) The iova of any master can NOT cross the 4G/8G/12G boundary.
19 *
20 * This is the suggested mapping in this SoC:
21 *
22 * modules dma-address-region larbs-ports
23 * disp 0 ~ 4G larb0/1/2
24 * vcodec 4G ~ 8G larb4/7
25 * cam/mdp 8G ~ 12G the other larbs.
26 * N/A 12G ~ 16G
27 * CCU0 0x24000_0000 ~ 0x243ff_ffff larb13: port 9/10
28 * CCU1 0x24400_0000 ~ 0x247ff_ffff larb14: port 4/5
29 */
30
31/* MM IOMMU ports */
32/* LARB 0 -- MMSYS */
33#define IOMMU_PORT_L0_DISP_POSTMASK0 MTK_M4U_ID(0, 0)
34#define IOMMU_PORT_L0_REVERSED MTK_M4U_ID(0, 1)
35#define IOMMU_PORT_L0_OVL_RDMA0 MTK_M4U_ID(0, 2)
36#define IOMMU_PORT_L0_DISP_FAKE0 MTK_M4U_ID(0, 3)
37
38/* LARB 1 -- MMSYS */
39#define IOMMU_PORT_L1_DISP_RDMA1 MTK_M4U_ID(1, 0)
40#define IOMMU_PORT_L1_OVL_2L_RDMA0 MTK_M4U_ID(1, 1)
41#define IOMMU_PORT_L1_DISP_RDMA0 MTK_M4U_ID(1, 2)
42#define IOMMU_PORT_L1_DISP_WDMA0 MTK_M4U_ID(1, 3)
43#define IOMMU_PORT_L1_DISP_FAKE1 MTK_M4U_ID(1, 4)
44
45/* LARB 2 -- MMSYS */
46#define IOMMU_PORT_L2_MDP_RDMA0 MTK_M4U_ID(2, 0)
47#define IOMMU_PORT_L2_MDP_RDMA1 MTK_M4U_ID(2, 1)
48#define IOMMU_PORT_L2_MDP_WROT0 MTK_M4U_ID(2, 2)
49#define IOMMU_PORT_L2_MDP_WROT1 MTK_M4U_ID(2, 3)
50#define IOMMU_PORT_L2_DISP_FAKE0 MTK_M4U_ID(2, 4)
51
52/* LARB 4 -- VDEC */
53#define IOMMU_PORT_L4_HW_VDEC_MC_EXT MTK_M4U_ID(4, 0)
54#define IOMMU_PORT_L4_HW_VDEC_UFO_EXT MTK_M4U_ID(4, 1)
55#define IOMMU_PORT_L4_HW_VDEC_PP_EXT MTK_M4U_ID(4, 2)
56#define IOMMU_PORT_L4_HW_VDEC_PRED_RD_EXT MTK_M4U_ID(4, 3)
57#define IOMMU_PORT_L4_HW_VDEC_PRED_WR_EXT MTK_M4U_ID(4, 4)
58#define IOMMU_PORT_L4_HW_VDEC_PPWRAP_EXT MTK_M4U_ID(4, 5)
59#define IOMMU_PORT_L4_HW_VDEC_TILE_EXT MTK_M4U_ID(4, 6)
60#define IOMMU_PORT_L4_HW_VDEC_VLD_EXT MTK_M4U_ID(4, 7)
61#define IOMMU_PORT_L4_HW_VDEC_VLD2_EXT MTK_M4U_ID(4, 8)
62#define IOMMU_PORT_L4_HW_VDEC_AVC_MV_EXT MTK_M4U_ID(4, 9)
63#define IOMMU_PORT_L4_HW_VDEC_UFO_ENC_EXT MTK_M4U_ID(4, 10)
64#define IOMMU_PORT_L4_HW_VDEC_RG_CTRL_DMA_EXT MTK_M4U_ID(4, 11)
65#define IOMMU_PORT_L4_HW_MINI_MDP_R0_EXT MTK_M4U_ID(4, 12)
66#define IOMMU_PORT_L4_HW_MINI_MDP_W0_EXT MTK_M4U_ID(4, 13)
67
68/* LARB 7 -- VENC */
69#define IOMMU_PORT_L7_VENC_RCPU MTK_M4U_ID(7, 0)
70#define IOMMU_PORT_L7_VENC_REC MTK_M4U_ID(7, 1)
71#define IOMMU_PORT_L7_VENC_BSDMA MTK_M4U_ID(7, 2)
72#define IOMMU_PORT_L7_VENC_SV_COMV MTK_M4U_ID(7, 3)
73#define IOMMU_PORT_L7_VENC_RD_COMV MTK_M4U_ID(7, 4)
74#define IOMMU_PORT_L7_VENC_CUR_LUMA MTK_M4U_ID(7, 5)
75#define IOMMU_PORT_L7_VENC_CUR_CHROMA MTK_M4U_ID(7, 6)
76#define IOMMU_PORT_L7_VENC_REF_LUMA MTK_M4U_ID(7, 7)
77#define IOMMU_PORT_L7_VENC_REF_CHROMA MTK_M4U_ID(7, 8)
78#define IOMMU_PORT_L7_JPGENC_Y_RDMA MTK_M4U_ID(7, 9)
79#define IOMMU_PORT_L7_JPGENC_C_RDMA MTK_M4U_ID(7, 10)
80#define IOMMU_PORT_L7_JPGENC_Q_TABLE MTK_M4U_ID(7, 11)
81#define IOMMU_PORT_L7_JPGENC_BSDMA MTK_M4U_ID(7, 12)
82
83/* LARB 8 -- WPE */
84#define IOMMU_PORT_L8_WPE_RDMA_0 MTK_M4U_ID(8, 0)
85#define IOMMU_PORT_L8_WPE_RDMA_1 MTK_M4U_ID(8, 1)
86#define IOMMU_PORT_L8_WPE_WDMA_0 MTK_M4U_ID(8, 2)
87
88/* LARB 9 -- IMG-1 */
89#define IOMMU_PORT_L9_IMG_IMGI_D1 MTK_M4U_ID(9, 0)
90#define IOMMU_PORT_L9_IMG_IMGBI_D1 MTK_M4U_ID(9, 1)
91#define IOMMU_PORT_L9_IMG_DMGI_D1 MTK_M4U_ID(9, 2)
92#define IOMMU_PORT_L9_IMG_DEPI_D1 MTK_M4U_ID(9, 3)
93#define IOMMU_PORT_L9_IMG_LCE_D1 MTK_M4U_ID(9, 4)
94#define IOMMU_PORT_L9_IMG_SMTI_D1 MTK_M4U_ID(9, 5)
95#define IOMMU_PORT_L9_IMG_SMTO_D2 MTK_M4U_ID(9, 6)
96#define IOMMU_PORT_L9_IMG_SMTO_D1 MTK_M4U_ID(9, 7)
97#define IOMMU_PORT_L9_IMG_CRZO_D1 MTK_M4U_ID(9, 8)
98#define IOMMU_PORT_L9_IMG_IMG3O_D1 MTK_M4U_ID(9, 9)
99#define IOMMU_PORT_L9_IMG_VIPI_D1 MTK_M4U_ID(9, 10)
100#define IOMMU_PORT_L9_IMG_SMTI_D5 MTK_M4U_ID(9, 11)
101#define IOMMU_PORT_L9_IMG_TIMGO_D1 MTK_M4U_ID(9, 12)
102#define IOMMU_PORT_L9_IMG_UFBC_W0 MTK_M4U_ID(9, 13)
103#define IOMMU_PORT_L9_IMG_UFBC_R0 MTK_M4U_ID(9, 14)
104#define IOMMU_PORT_L9_IMG_WPE_RDMA1 MTK_M4U_ID(9, 15)
105#define IOMMU_PORT_L9_IMG_WPE_RDMA0 MTK_M4U_ID(9, 16)
106#define IOMMU_PORT_L9_IMG_WPE_WDMA MTK_M4U_ID(9, 17)
107#define IOMMU_PORT_L9_IMG_MFB_RDMA0 MTK_M4U_ID(9, 18)
108#define IOMMU_PORT_L9_IMG_MFB_RDMA1 MTK_M4U_ID(9, 19)
109#define IOMMU_PORT_L9_IMG_MFB_RDMA2 MTK_M4U_ID(9, 20)
110#define IOMMU_PORT_L9_IMG_MFB_RDMA3 MTK_M4U_ID(9, 21)
111#define IOMMU_PORT_L9_IMG_MFB_RDMA4 MTK_M4U_ID(9, 22)
112#define IOMMU_PORT_L9_IMG_MFB_RDMA5 MTK_M4U_ID(9, 23)
113#define IOMMU_PORT_L9_IMG_MFB_WDMA0 MTK_M4U_ID(9, 24)
114#define IOMMU_PORT_L9_IMG_MFB_WDMA1 MTK_M4U_ID(9, 25)
115#define IOMMU_PORT_L9_IMG_RESERVE6 MTK_M4U_ID(9, 26)
116#define IOMMU_PORT_L9_IMG_RESERVE7 MTK_M4U_ID(9, 27)
117#define IOMMU_PORT_L9_IMG_RESERVE8 MTK_M4U_ID(9, 28)
118
119/* LARB 11 -- IMG-2 */
120#define IOMMU_PORT_L11_IMG_IMGI_D1 MTK_M4U_ID(11, 0)
121#define IOMMU_PORT_L11_IMG_IMGBI_D1 MTK_M4U_ID(11, 1)
122#define IOMMU_PORT_L11_IMG_DMGI_D1 MTK_M4U_ID(11, 2)
123#define IOMMU_PORT_L11_IMG_DEPI_D1 MTK_M4U_ID(11, 3)
124#define IOMMU_PORT_L11_IMG_LCE_D1 MTK_M4U_ID(11, 4)
125#define IOMMU_PORT_L11_IMG_SMTI_D1 MTK_M4U_ID(11, 5)
126#define IOMMU_PORT_L11_IMG_SMTO_D2 MTK_M4U_ID(11, 6)
127#define IOMMU_PORT_L11_IMG_SMTO_D1 MTK_M4U_ID(11, 7)
128#define IOMMU_PORT_L11_IMG_CRZO_D1 MTK_M4U_ID(11, 8)
129#define IOMMU_PORT_L11_IMG_IMG3O_D1 MTK_M4U_ID(11, 9)
130#define IOMMU_PORT_L11_IMG_VIPI_D1 MTK_M4U_ID(11, 10)
131#define IOMMU_PORT_L11_IMG_SMTI_D5 MTK_M4U_ID(11, 11)
132#define IOMMU_PORT_L11_IMG_TIMGO_D1 MTK_M4U_ID(11, 12)
133#define IOMMU_PORT_L11_IMG_UFBC_W0 MTK_M4U_ID(11, 13)
134#define IOMMU_PORT_L11_IMG_UFBC_R0 MTK_M4U_ID(11, 14)
135#define IOMMU_PORT_L11_IMG_WPE_RDMA1 MTK_M4U_ID(11, 15)
136#define IOMMU_PORT_L11_IMG_WPE_RDMA0 MTK_M4U_ID(11, 16)
137#define IOMMU_PORT_L11_IMG_WPE_WDMA MTK_M4U_ID(11, 17)
138#define IOMMU_PORT_L11_IMG_MFB_RDMA0 MTK_M4U_ID(11, 18)
139#define IOMMU_PORT_L11_IMG_MFB_RDMA1 MTK_M4U_ID(11, 19)
140#define IOMMU_PORT_L11_IMG_MFB_RDMA2 MTK_M4U_ID(11, 20)
141#define IOMMU_PORT_L11_IMG_MFB_RDMA3 MTK_M4U_ID(11, 21)
142#define IOMMU_PORT_L11_IMG_MFB_RDMA4 MTK_M4U_ID(11, 22)
143#define IOMMU_PORT_L11_IMG_MFB_RDMA5 MTK_M4U_ID(11, 23)
144#define IOMMU_PORT_L11_IMG_MFB_WDMA0 MTK_M4U_ID(11, 24)
145#define IOMMU_PORT_L11_IMG_MFB_WDMA1 MTK_M4U_ID(11, 25)
146#define IOMMU_PORT_L11_IMG_RESERVE6 MTK_M4U_ID(11, 26)
147#define IOMMU_PORT_L11_IMG_RESERVE7 MTK_M4U_ID(11, 27)
148#define IOMMU_PORT_L11_IMG_RESERVE8 MTK_M4U_ID(11, 28)
149
150/* LARB 13 -- CAM */
151#define IOMMU_PORT_L13_CAM_MRAWI MTK_M4U_ID(13, 0)
152#define IOMMU_PORT_L13_CAM_MRAWO_0 MTK_M4U_ID(13, 1)
153#define IOMMU_PORT_L13_CAM_MRAWO_1 MTK_M4U_ID(13, 2)
154#define IOMMU_PORT_L13_CAM_CAMSV_4 MTK_M4U_ID(13, 6)
155#define IOMMU_PORT_L13_CAM_CAMSV_5 MTK_M4U_ID(13, 7)
156#define IOMMU_PORT_L13_CAM_CAMSV_6 MTK_M4U_ID(13, 8)
157#define IOMMU_PORT_L13_CAM_CCUI MTK_M4U_ID(13, 9)
158#define IOMMU_PORT_L13_CAM_CCUO MTK_M4U_ID(13, 10)
159#define IOMMU_PORT_L13_CAM_FAKE MTK_M4U_ID(13, 11)
160
161/* LARB 14 -- CAM */
162#define IOMMU_PORT_L14_CAM_CCUI MTK_M4U_ID(14, 4)
163#define IOMMU_PORT_L14_CAM_CCUO MTK_M4U_ID(14, 5)
164
165/* LARB 16 -- RAW-A */
166#define IOMMU_PORT_L16_CAM_IMGO_R1_A MTK_M4U_ID(16, 0)
167#define IOMMU_PORT_L16_CAM_RRZO_R1_A MTK_M4U_ID(16, 1)
168#define IOMMU_PORT_L16_CAM_CQI_R1_A MTK_M4U_ID(16, 2)
169#define IOMMU_PORT_L16_CAM_BPCI_R1_A MTK_M4U_ID(16, 3)
170#define IOMMU_PORT_L16_CAM_YUVO_R1_A MTK_M4U_ID(16, 4)
171#define IOMMU_PORT_L16_CAM_UFDI_R2_A MTK_M4U_ID(16, 5)
172#define IOMMU_PORT_L16_CAM_RAWI_R2_A MTK_M4U_ID(16, 6)
173#define IOMMU_PORT_L16_CAM_RAWI_R3_A MTK_M4U_ID(16, 7)
174#define IOMMU_PORT_L16_CAM_AAO_R1_A MTK_M4U_ID(16, 8)
175#define IOMMU_PORT_L16_CAM_AFO_R1_A MTK_M4U_ID(16, 9)
176#define IOMMU_PORT_L16_CAM_FLKO_R1_A MTK_M4U_ID(16, 10)
177#define IOMMU_PORT_L16_CAM_LCESO_R1_A MTK_M4U_ID(16, 11)
178#define IOMMU_PORT_L16_CAM_CRZO_R1_A MTK_M4U_ID(16, 12)
179#define IOMMU_PORT_L16_CAM_LTMSO_R1_A MTK_M4U_ID(16, 13)
180#define IOMMU_PORT_L16_CAM_RSSO_R1_A MTK_M4U_ID(16, 14)
181#define IOMMU_PORT_L16_CAM_AAHO_R1_A MTK_M4U_ID(16, 15)
182#define IOMMU_PORT_L16_CAM_LSCI_R1_A MTK_M4U_ID(16, 16)
183
184/* LARB 17 -- RAW-B */
185#define IOMMU_PORT_L17_CAM_IMGO_R1_B MTK_M4U_ID(17, 0)
186#define IOMMU_PORT_L17_CAM_RRZO_R1_B MTK_M4U_ID(17, 1)
187#define IOMMU_PORT_L17_CAM_CQI_R1_B MTK_M4U_ID(17, 2)
188#define IOMMU_PORT_L17_CAM_BPCI_R1_B MTK_M4U_ID(17, 3)
189#define IOMMU_PORT_L17_CAM_YUVO_R1_B MTK_M4U_ID(17, 4)
190#define IOMMU_PORT_L17_CAM_UFDI_R2_B MTK_M4U_ID(17, 5)
191#define IOMMU_PORT_L17_CAM_RAWI_R2_B MTK_M4U_ID(17, 6)
192#define IOMMU_PORT_L17_CAM_RAWI_R3_B MTK_M4U_ID(17, 7)
193#define IOMMU_PORT_L17_CAM_AAO_R1_B MTK_M4U_ID(17, 8)
194#define IOMMU_PORT_L17_CAM_AFO_R1_B MTK_M4U_ID(17, 9)
195#define IOMMU_PORT_L17_CAM_FLKO_R1_B MTK_M4U_ID(17, 10)
196#define IOMMU_PORT_L17_CAM_LCESO_R1_B MTK_M4U_ID(17, 11)
197#define IOMMU_PORT_L17_CAM_CRZO_R1_B MTK_M4U_ID(17, 12)
198#define IOMMU_PORT_L17_CAM_LTMSO_R1_B MTK_M4U_ID(17, 13)
199#define IOMMU_PORT_L17_CAM_RSSO_R1_B MTK_M4U_ID(17, 14)
200#define IOMMU_PORT_L17_CAM_AAHO_R1_B MTK_M4U_ID(17, 15)
201#define IOMMU_PORT_L17_CAM_LSCI_R1_B MTK_M4U_ID(17, 16)
202
203/* LARB 19 -- IPE */
204#define IOMMU_PORT_L19_IPE_DVS_RDMA MTK_M4U_ID(19, 0)
205#define IOMMU_PORT_L19_IPE_DVS_WDMA MTK_M4U_ID(19, 1)
206#define IOMMU_PORT_L19_IPE_DVP_RDMA MTK_M4U_ID(19, 2)
207#define IOMMU_PORT_L19_IPE_DVP_WDMA MTK_M4U_ID(19, 3)
208
209/* LARB 20 -- IPE */
210#define IOMMU_PORT_L20_IPE_FDVT_RDA MTK_M4U_ID(20, 0)
211#define IOMMU_PORT_L20_IPE_FDVT_RDB MTK_M4U_ID(20, 1)
212#define IOMMU_PORT_L20_IPE_FDVT_WRA MTK_M4U_ID(20, 2)
213#define IOMMU_PORT_L20_IPE_FDVT_WRB MTK_M4U_ID(20, 3)
214#define IOMMU_PORT_L20_IPE_RSC_RDMA0 MTK_M4U_ID(20, 4)
215#define IOMMU_PORT_L20_IPE_RSC_WDMA MTK_M4U_ID(20, 5)
216
217#endif
include/dt-bindings/memory/mt8195-memory-port.h+408−0
@@ -0,0 +1,408 @@
1/* SPDX-License-Identifier: GPL-2.0-only */
2/*
3 * Copyright (c) 2022 MediaTek Inc.
4 * Author: Yong Wu <yong.wu@mediatek.com>
5 */
6#ifndef _DT_BINDINGS_MEMORY_MT8195_LARB_PORT_H_
7#define _DT_BINDINGS_MEMORY_MT8195_LARB_PORT_H_
8
9#include <dt-bindings/memory/mtk-memory-port.h>
10
11/*
12 * MM IOMMU supports 16GB dma address. We separate it to four ranges:
13 * 0 ~ 4G; 4G ~ 8G; 8G ~ 12G; 12G ~ 16G, we could adjust these masters
14 * locate in anyone region. BUT:
15 * a) Make sure all the ports inside a larb are in one range.
16 * b) The iova of any master can NOT cross the 4G/8G/12G boundary.
17 *
18 * This is the suggested mapping in this SoC:
19 *
20 * modules dma-address-region larbs-ports
21 * disp 0 ~ 4G larb0/1/2/3
22 * vcodec 4G ~ 8G larb19/20/21/22/23/24
23 * cam/mdp 8G ~ 12G the other larbs.
24 * N/A 12G ~ 16G
25 * CCU0 0x24000_0000 ~ 0x243ff_ffff larb18: port 0/1
26 * CCU1 0x24400_0000 ~ 0x247ff_ffff larb18: port 2/3
27 *
28 * This SoC have two IOMMU HWs, this is the detailed connected information:
29 * iommu-vdo: larb0/2/5/7/9/10/11/13/17/19/21/24/25/28
30 * iommu-vpp: larb1/3/4/6/8/12/14/16/18/20/22/23/26/27
31 */
32
33/* MM IOMMU ports */
34/* larb0 */
35#define M4U_PORT_L0_DISP_RDMA0 MTK_M4U_ID(0, 0)
36#define M4U_PORT_L0_DISP_WDMA0 MTK_M4U_ID(0, 1)
37#define M4U_PORT_L0_DISP_OVL0_RDMA0 MTK_M4U_ID(0, 2)
38#define M4U_PORT_L0_DISP_OVL0_RDMA1 MTK_M4U_ID(0, 3)
39#define M4U_PORT_L0_DISP_OVL0_HDR MTK_M4U_ID(0, 4)
40#define M4U_PORT_L0_DISP_FAKE0 MTK_M4U_ID(0, 5)
41
42/* larb1 */
43#define M4U_PORT_L1_DISP_RDMA0 MTK_M4U_ID(1, 0)
44#define M4U_PORT_L1_DISP_WDMA0 MTK_M4U_ID(1, 1)
45#define M4U_PORT_L1_DISP_OVL0_RDMA0 MTK_M4U_ID(1, 2)
46#define M4U_PORT_L1_DISP_OVL0_RDMA1 MTK_M4U_ID(1, 3)
47#define M4U_PORT_L1_DISP_OVL0_HDR MTK_M4U_ID(1, 4)
48#define M4U_PORT_L1_DISP_FAKE0 MTK_M4U_ID(1, 5)
49
50/* larb2 */
51#define M4U_PORT_L2_MDP_RDMA0 MTK_M4U_ID(2, 0)
52#define M4U_PORT_L2_MDP_RDMA2 MTK_M4U_ID(2, 1)
53#define M4U_PORT_L2_MDP_RDMA4 MTK_M4U_ID(2, 2)
54#define M4U_PORT_L2_MDP_RDMA6 MTK_M4U_ID(2, 3)
55#define M4U_PORT_L2_DISP_FAKE1 MTK_M4U_ID(2, 4)
56
57/* larb3 */
58#define M4U_PORT_L3_MDP_RDMA1 MTK_M4U_ID(3, 0)
59#define M4U_PORT_L3_MDP_RDMA3 MTK_M4U_ID(3, 1)
60#define M4U_PORT_L3_MDP_RDMA5 MTK_M4U_ID(3, 2)
61#define M4U_PORT_L3_MDP_RDMA7 MTK_M4U_ID(3, 3)
62#define M4U_PORT_L3_HDR_DS MTK_M4U_ID(3, 4)
63#define M4U_PORT_L3_HDR_ADL MTK_M4U_ID(3, 5)
64#define M4U_PORT_L3_DISP_FAKE1 MTK_M4U_ID(3, 6)
65
66/* larb4 */
67#define M4U_PORT_L4_MDP_RDMA MTK_M4U_ID(4, 0)
68#define M4U_PORT_L4_MDP_FG MTK_M4U_ID(4, 1)
69#define M4U_PORT_L4_MDP_OVL MTK_M4U_ID(4, 2)
70#define M4U_PORT_L4_MDP_WROT MTK_M4U_ID(4, 3)
71#define M4U_PORT_L4_FAKE MTK_M4U_ID(4, 4)
72
73/* larb5 */
74#define M4U_PORT_L5_SVPP1_MDP_RDMA MTK_M4U_ID(5, 0)
75#define M4U_PORT_L5_SVPP1_MDP_FG MTK_M4U_ID(5, 1)
76#define M4U_PORT_L5_SVPP1_MDP_OVL MTK_M4U_ID(5, 2)
77#define M4U_PORT_L5_SVPP1_MDP_WROT MTK_M4U_ID(5, 3)
78#define M4U_PORT_L5_SVPP2_MDP_RDMA MTK_M4U_ID(5, 4)
79#define M4U_PORT_L5_SVPP2_MDP_FG MTK_M4U_ID(5, 5)
80#define M4U_PORT_L5_SVPP2_MDP_WROT MTK_M4U_ID(5, 6)
81#define M4U_PORT_L5_FAKE MTK_M4U_ID(5, 7)
82
83/* larb6 */
84#define M4U_PORT_L6_SVPP3_MDP_RDMA MTK_M4U_ID(6, 0)
85#define M4U_PORT_L6_SVPP3_MDP_FG MTK_M4U_ID(6, 1)
86#define M4U_PORT_L6_SVPP3_MDP_WROT MTK_M4U_ID(6, 2)
87#define M4U_PORT_L6_FAKE MTK_M4U_ID(6, 3)
88
89/* larb7 */
90#define M4U_PORT_L7_IMG_WPE_RDMA0 MTK_M4U_ID(7, 0)
91#define M4U_PORT_L7_IMG_WPE_RDMA1 MTK_M4U_ID(7, 1)
92#define M4U_PORT_L7_IMG_WPE_WDMA0 MTK_M4U_ID(7, 2)
93
94/* larb8 */
95#define M4U_PORT_L8_IMG_WPE_RDMA0 MTK_M4U_ID(8, 0)
96#define M4U_PORT_L8_IMG_WPE_RDMA1 MTK_M4U_ID(8, 1)
97#define M4U_PORT_L8_IMG_WPE_WDMA0 MTK_M4U_ID(8, 2)
98
99/* larb9 */
100#define M4U_PORT_L9_IMG_IMGI_T1_A MTK_M4U_ID(9, 0)
101#define M4U_PORT_L9_IMG_IMGBI_T1_A MTK_M4U_ID(9, 1)
102#define M4U_PORT_L9_IMG_IMGCI_T1_A MTK_M4U_ID(9, 2)
103#define M4U_PORT_L9_IMG_SMTI_T1_A MTK_M4U_ID(9, 3)
104#define M4U_PORT_L9_IMG_TNCSTI_T1_A MTK_M4U_ID(9, 4)
105#define M4U_PORT_L9_IMG_TNCSTI_T4_A MTK_M4U_ID(9, 5)
106#define M4U_PORT_L9_IMG_YUVO_T1_A MTK_M4U_ID(9, 6)
107#define M4U_PORT_L9_IMG_TIMGO_T1_A MTK_M4U_ID(9, 7)
108#define M4U_PORT_L9_IMG_YUVO_T2_A MTK_M4U_ID(9, 8)
109#define M4U_PORT_L9_IMG_IMGI_T1_B MTK_M4U_ID(9, 9)
110#define M4U_PORT_L9_IMG_IMGBI_T1_B MTK_M4U_ID(9, 10)
111#define M4U_PORT_L9_IMG_IMGCI_T1_B MTK_M4U_ID(9, 11)
112#define M4U_PORT_L9_IMG_YUVO_T5_A MTK_M4U_ID(9, 12)
113#define M4U_PORT_L9_IMG_SMTI_T1_B MTK_M4U_ID(9, 13)
114#define M4U_PORT_L9_IMG_TNCSO_T1_A MTK_M4U_ID(9, 14)
115#define M4U_PORT_L9_IMG_SMTO_T1_A MTK_M4U_ID(9, 15)
116#define M4U_PORT_L9_IMG_TNCSTO_T1_A MTK_M4U_ID(9, 16)
117#define M4U_PORT_L9_IMG_YUVO_T2_B MTK_M4U_ID(9, 17)
118#define M4U_PORT_L9_IMG_YUVO_T5_B MTK_M4U_ID(9, 18)
119#define M4U_PORT_L9_IMG_SMTO_T1_B MTK_M4U_ID(9, 19)
120
121/* larb10 */
122#define M4U_PORT_L10_IMG_IMGI_D1_A MTK_M4U_ID(10, 0)
123#define M4U_PORT_L10_IMG_IMGCI_D1_A MTK_M4U_ID(10, 1)
124#define M4U_PORT_L10_IMG_DEPI_D1_A MTK_M4U_ID(10, 2)
125#define M4U_PORT_L10_IMG_DMGI_D1_A MTK_M4U_ID(10, 3)
126#define M4U_PORT_L10_IMG_VIPI_D1_A MTK_M4U_ID(10, 4)
127#define M4U_PORT_L10_IMG_TNRWI_D1_A MTK_M4U_ID(10, 5)
128#define M4U_PORT_L10_IMG_RECI_D1_A MTK_M4U_ID(10, 6)
129#define M4U_PORT_L10_IMG_SMTI_D1_A MTK_M4U_ID(10, 7)
130#define M4U_PORT_L10_IMG_SMTI_D6_A MTK_M4U_ID(10, 8)
131#define M4U_PORT_L10_IMG_PIMGI_P1_A MTK_M4U_ID(10, 9)
132#define M4U_PORT_L10_IMG_PIMGBI_P1_A MTK_M4U_ID(10, 10)
133#define M4U_PORT_L10_IMG_PIMGCI_P1_A MTK_M4U_ID(10, 11)
134#define M4U_PORT_L10_IMG_PIMGI_P1_B MTK_M4U_ID(10, 12)
135#define M4U_PORT_L10_IMG_PIMGBI_P1_B MTK_M4U_ID(10, 13)
136#define M4U_PORT_L10_IMG_PIMGCI_P1_B MTK_M4U_ID(10, 14)
137#define M4U_PORT_L10_IMG_IMG3O_D1_A MTK_M4U_ID(10, 15)
138#define M4U_PORT_L10_IMG_IMG4O_D1_A MTK_M4U_ID(10, 16)
139#define M4U_PORT_L10_IMG_IMG3CO_D1_A MTK_M4U_ID(10, 17)
140#define M4U_PORT_L10_IMG_FEO_D1_A MTK_M4U_ID(10, 18)
141#define M4U_PORT_L10_IMG_IMG2O_D1_A MTK_M4U_ID(10, 19)
142#define M4U_PORT_L10_IMG_TNRWO_D1_A MTK_M4U_ID(10, 20)
143#define M4U_PORT_L10_IMG_SMTO_D1_A MTK_M4U_ID(10, 21)
144#define M4U_PORT_L10_IMG_WROT_P1_A MTK_M4U_ID(10, 22)
145#define M4U_PORT_L10_IMG_WROT_P1_B MTK_M4U_ID(10, 23)
146
147/* larb11 */
148#define M4U_PORT_L11_IMG_WPE_EIS_RDMA0_A MTK_M4U_ID(11, 0)
149#define M4U_PORT_L11_IMG_WPE_EIS_RDMA1_A MTK_M4U_ID(11, 1)
150#define M4U_PORT_L11_IMG_WPE_EIS_WDMA0_A MTK_M4U_ID(11, 2)
151#define M4U_PORT_L11_IMG_WPE_TNR_RDMA0_A MTK_M4U_ID(11, 3)
152#define M4U_PORT_L11_IMG_WPE_TNR_RDMA1_A MTK_M4U_ID(11, 4)
153#define M4U_PORT_L11_IMG_WPE_TNR_WDMA0_A MTK_M4U_ID(11, 5)
154#define M4U_PORT_L11_IMG_WPE_EIS_CQ0_A MTK_M4U_ID(11, 6)
155#define M4U_PORT_L11_IMG_WPE_EIS_CQ1_A MTK_M4U_ID(11, 7)
156#define M4U_PORT_L11_IMG_WPE_TNR_CQ0_A MTK_M4U_ID(11, 8)
157#define M4U_PORT_L11_IMG_WPE_TNR_CQ1_A MTK_M4U_ID(11, 9)
158
159/* larb12 */
160#define M4U_PORT_L12_IMG_FDVT_RDA MTK_M4U_ID(12, 0)
161#define M4U_PORT_L12_IMG_FDVT_RDB MTK_M4U_ID(12, 1)
162#define M4U_PORT_L12_IMG_FDVT_WRA MTK_M4U_ID(12, 2)
163#define M4U_PORT_L12_IMG_FDVT_WRB MTK_M4U_ID(12, 3)
164#define M4U_PORT_L12_IMG_ME_RDMA MTK_M4U_ID(12, 4)
165#define M4U_PORT_L12_IMG_ME_WDMA MTK_M4U_ID(12, 5)
166#define M4U_PORT_L12_IMG_DVS_RDMA MTK_M4U_ID(12, 6)
167#define M4U_PORT_L12_IMG_DVS_WDMA MTK_M4U_ID(12, 7)
168#define M4U_PORT_L12_IMG_DVP_RDMA MTK_M4U_ID(12, 8)
169#define M4U_PORT_L12_IMG_DVP_WDMA MTK_M4U_ID(12, 9)
170
171/* larb13 */
172#define M4U_PORT_L13_CAM_CAMSV_CQI_E1 MTK_M4U_ID(13, 0)
173#define M4U_PORT_L13_CAM_CAMSV_CQI_E2 MTK_M4U_ID(13, 1)
174#define M4U_PORT_L13_CAM_GCAMSV_A_IMGO_0 MTK_M4U_ID(13, 2)
175#define M4U_PORT_L13_CAM_SCAMSV_A_IMGO_0 MTK_M4U_ID(13, 3)
176#define M4U_PORT_L13_CAM_GCAMSV_B_IMGO_0 MTK_M4U_ID(13, 4)
177#define M4U_PORT_L13_CAM_GCAMSV_B_IMGO_1 MTK_M4U_ID(13, 5)
178#define M4U_PORT_L13_CAM_GCAMSV_A_UFEO_0 MTK_M4U_ID(13, 6)
179#define M4U_PORT_L13_CAM_GCAMSV_B_UFEO_0 MTK_M4U_ID(13, 7)
180#define M4U_PORT_L13_CAM_PDAI_0 MTK_M4U_ID(13, 8)
181#define M4U_PORT_L13_CAM_FAKE MTK_M4U_ID(13, 9)
182
183/* larb14 */
184#define M4U_PORT_L14_CAM_GCAMSV_A_IMGO_1 MTK_M4U_ID(14, 0)
185#define M4U_PORT_L14_CAM_SCAMSV_A_IMGO_1 MTK_M4U_ID(14, 1)
186#define M4U_PORT_L14_CAM_GCAMSV_B_IMGO_0 MTK_M4U_ID(14, 2)
187#define M4U_PORT_L14_CAM_GCAMSV_B_IMGO_1 MTK_M4U_ID(14, 3)
188#define M4U_PORT_L14_CAM_SCAMSV_B_IMGO_0 MTK_M4U_ID(14, 4)
189#define M4U_PORT_L14_CAM_SCAMSV_B_IMGO_1 MTK_M4U_ID(14, 5)
190#define M4U_PORT_L14_CAM_IPUI MTK_M4U_ID(14, 6)
191#define M4U_PORT_L14_CAM_IPU2I MTK_M4U_ID(14, 7)
192#define M4U_PORT_L14_CAM_IPUO MTK_M4U_ID(14, 8)
193#define M4U_PORT_L14_CAM_IPU2O MTK_M4U_ID(14, 9)
194#define M4U_PORT_L14_CAM_IPU3O MTK_M4U_ID(14, 10)
195#define M4U_PORT_L14_CAM_GCAMSV_A_UFEO_1 MTK_M4U_ID(14, 11)
196#define M4U_PORT_L14_CAM_GCAMSV_B_UFEO_1 MTK_M4U_ID(14, 12)
197#define M4U_PORT_L14_CAM_PDAI_1 MTK_M4U_ID(14, 13)
198#define M4U_PORT_L14_CAM_PDAO MTK_M4U_ID(14, 14)
199
200/* larb15: null */
201
202/* larb16 */
203#define M4U_PORT_L16_CAM_IMGO_R1 MTK_M4U_ID(16, 0)
204#define M4U_PORT_L16_CAM_CQI_R1 MTK_M4U_ID(16, 1)
205#define M4U_PORT_L16_CAM_CQI_R2 MTK_M4U_ID(16, 2)
206#define M4U_PORT_L16_CAM_BPCI_R1 MTK_M4U_ID(16, 3)
207#define M4U_PORT_L16_CAM_LSCI_R1 MTK_M4U_ID(16, 4)
208#define M4U_PORT_L16_CAM_RAWI_R2 MTK_M4U_ID(16, 5)
209#define M4U_PORT_L16_CAM_RAWI_R3 MTK_M4U_ID(16, 6)
210#define M4U_PORT_L16_CAM_UFDI_R2 MTK_M4U_ID(16, 7)
211#define M4U_PORT_L16_CAM_UFDI_R3 MTK_M4U_ID(16, 8)
212#define M4U_PORT_L16_CAM_RAWI_R4 MTK_M4U_ID(16, 9)
213#define M4U_PORT_L16_CAM_RAWI_R5 MTK_M4U_ID(16, 10)
214#define M4U_PORT_L16_CAM_AAI_R1 MTK_M4U_ID(16, 11)
215#define M4U_PORT_L16_CAM_FHO_R1 MTK_M4U_ID(16, 12)
216#define M4U_PORT_L16_CAM_AAO_R1 MTK_M4U_ID(16, 13)
217#define M4U_PORT_L16_CAM_TSFSO_R1 MTK_M4U_ID(16, 14)
218#define M4U_PORT_L16_CAM_FLKO_R1 MTK_M4U_ID(16, 15)
219
220/* larb17 */
221#define M4U_PORT_L17_CAM_YUVO_R1 MTK_M4U_ID(17, 0)
222#define M4U_PORT_L17_CAM_YUVO_R3 MTK_M4U_ID(17, 1)
223#define M4U_PORT_L17_CAM_YUVCO_R1 MTK_M4U_ID(17, 2)
224#define M4U_PORT_L17_CAM_YUVO_R2 MTK_M4U_ID(17, 3)
225#define M4U_PORT_L17_CAM_RZH1N2TO_R1 MTK_M4U_ID(17, 4)
226#define M4U_PORT_L17_CAM_DRZS4NO_R1 MTK_M4U_ID(17, 5)
227#define M4U_PORT_L17_CAM_TNCSO_R1 MTK_M4U_ID(17, 6)
228
229/* larb18 */
230#define M4U_PORT_L18_CAM_CCUI MTK_M4U_ID(18, 0)
231#define M4U_PORT_L18_CAM_CCUO MTK_M4U_ID(18, 1)
232#define M4U_PORT_L18_CAM_CCUI2 MTK_M4U_ID(18, 2)
233#define M4U_PORT_L18_CAM_CCUO2 MTK_M4U_ID(18, 3)
234
235/* larb19 */
236#define M4U_PORT_L19_VENC_RCPU MTK_M4U_ID(19, 0)
237#define M4U_PORT_L19_VENC_REC MTK_M4U_ID(19, 1)
238#define M4U_PORT_L19_VENC_BSDMA MTK_M4U_ID(19, 2)
239#define M4U_PORT_L19_VENC_SV_COMV MTK_M4U_ID(19, 3)
240#define M4U_PORT_L19_VENC_RD_COMV MTK_M4U_ID(19, 4)
241#define M4U_PORT_L19_VENC_NBM_RDMA MTK_M4U_ID(19, 5)
242#define M4U_PORT_L19_VENC_NBM_RDMA_LITE MTK_M4U_ID(19, 6)
243#define M4U_PORT_L19_JPGENC_Y_RDMA MTK_M4U_ID(19, 7)
244#define M4U_PORT_L19_JPGENC_C_RDMA MTK_M4U_ID(19, 8)
245#define M4U_PORT_L19_JPGENC_Q_TABLE MTK_M4U_ID(19, 9)
246#define M4U_PORT_L19_VENC_SUB_W_LUMA MTK_M4U_ID(19, 10)
247#define M4U_PORT_L19_VENC_FCS_NBM_RDMA MTK_M4U_ID(19, 11)
248#define M4U_PORT_L19_JPGENC_BSDMA MTK_M4U_ID(19, 12)
249#define M4U_PORT_L19_JPGDEC_WDMA0 MTK_M4U_ID(19, 13)
250#define M4U_PORT_L19_JPGDEC_BSDMA0 MTK_M4U_ID(19, 14)
251#define M4U_PORT_L19_VENC_NBM_WDMA MTK_M4U_ID(19, 15)
252#define M4U_PORT_L19_VENC_NBM_WDMA_LITE MTK_M4U_ID(19, 16)
253#define M4U_PORT_L19_VENC_FCS_NBM_WDMA MTK_M4U_ID(19, 17)
254#define M4U_PORT_L19_JPGDEC_WDMA1 MTK_M4U_ID(19, 18)
255#define M4U_PORT_L19_JPGDEC_BSDMA1 MTK_M4U_ID(19, 19)
256#define M4U_PORT_L19_JPGDEC_BUFF_OFFSET1 MTK_M4U_ID(19, 20)
257#define M4U_PORT_L19_JPGDEC_BUFF_OFFSET0 MTK_M4U_ID(19, 21)
258#define M4U_PORT_L19_VENC_CUR_LUMA MTK_M4U_ID(19, 22)
259#define M4U_PORT_L19_VENC_CUR_CHROMA MTK_M4U_ID(19, 23)
260#define M4U_PORT_L19_VENC_REF_LUMA MTK_M4U_ID(19, 24)
261#define M4U_PORT_L19_VENC_REF_CHROMA MTK_M4U_ID(19, 25)
262#define M4U_PORT_L19_VENC_SUB_R_CHROMA MTK_M4U_ID(19, 26)
263
264/* larb20 */
265#define M4U_PORT_L20_VENC_RCPU MTK_M4U_ID(20, 0)
266#define M4U_PORT_L20_VENC_REC MTK_M4U_ID(20, 1)
267#define M4U_PORT_L20_VENC_BSDMA MTK_M4U_ID(20, 2)
268#define M4U_PORT_L20_VENC_SV_COMV MTK_M4U_ID(20, 3)
269#define M4U_PORT_L20_VENC_RD_COMV MTK_M4U_ID(20, 4)
270#define M4U_PORT_L20_VENC_NBM_RDMA MTK_M4U_ID(20, 5)
271#define M4U_PORT_L20_VENC_NBM_RDMA_LITE MTK_M4U_ID(20, 6)
272#define M4U_PORT_L20_JPGENC_Y_RDMA MTK_M4U_ID(20, 7)
273#define M4U_PORT_L20_JPGENC_C_RDMA MTK_M4U_ID(20, 8)
274#define M4U_PORT_L20_JPGENC_Q_TABLE MTK_M4U_ID(20, 9)
275#define M4U_PORT_L20_VENC_SUB_W_LUMA MTK_M4U_ID(20, 10)
276#define M4U_PORT_L20_VENC_FCS_NBM_RDMA MTK_M4U_ID(20, 11)
277#define M4U_PORT_L20_JPGENC_BSDMA MTK_M4U_ID(20, 12)
278#define M4U_PORT_L20_JPGDEC_WDMA0 MTK_M4U_ID(20, 13)
279#define M4U_PORT_L20_JPGDEC_BSDMA0 MTK_M4U_ID(20, 14)
280#define M4U_PORT_L20_VENC_NBM_WDMA MTK_M4U_ID(20, 15)
281#define M4U_PORT_L20_VENC_NBM_WDMA_LITE MTK_M4U_ID(20, 16)
282#define M4U_PORT_L20_VENC_FCS_NBM_WDMA MTK_M4U_ID(20, 17)
283#define M4U_PORT_L20_JPGDEC_WDMA1 MTK_M4U_ID(20, 18)
284#define M4U_PORT_L20_JPGDEC_BSDMA1 MTK_M4U_ID(20, 19)
285#define M4U_PORT_L20_JPGDEC_BUFF_OFFSET1 MTK_M4U_ID(20, 20)
286#define M4U_PORT_L20_JPGDEC_BUFF_OFFSET0 MTK_M4U_ID(20, 21)
287#define M4U_PORT_L20_VENC_CUR_LUMA MTK_M4U_ID(20, 22)
288#define M4U_PORT_L20_VENC_CUR_CHROMA MTK_M4U_ID(20, 23)
289#define M4U_PORT_L20_VENC_REF_LUMA MTK_M4U_ID(20, 24)
290#define M4U_PORT_L20_VENC_REF_CHROMA MTK_M4U_ID(20, 25)
291#define M4U_PORT_L20_VENC_SUB_R_CHROMA MTK_M4U_ID(20, 26)
292
293/* larb21 */
294#define M4U_PORT_L21_VDEC_MC_EXT MTK_M4U_ID(21, 0)
295#define M4U_PORT_L21_VDEC_UFO_EXT MTK_M4U_ID(21, 1)
296#define M4U_PORT_L21_VDEC_PP_EXT MTK_M4U_ID(21, 2)
297#define M4U_PORT_L21_VDEC_PRED_RD_EXT MTK_M4U_ID(21, 3)
298#define M4U_PORT_L21_VDEC_PRED_WR_EXT MTK_M4U_ID(21, 4)
299#define M4U_PORT_L21_VDEC_PPWRAP_EXT MTK_M4U_ID(21, 5)
300#define M4U_PORT_L21_VDEC_TILE_EXT MTK_M4U_ID(21, 6)
301#define M4U_PORT_L21_VDEC_VLD_EXT MTK_M4U_ID(21, 7)
302#define M4U_PORT_L21_VDEC_VLD2_EXT MTK_M4U_ID(21, 8)
303#define M4U_PORT_L21_VDEC_AVC_MV_EXT MTK_M4U_ID(21, 9)
304
305/* larb22 */
306#define M4U_PORT_L22_VDEC_MC_EXT MTK_M4U_ID(22, 0)
307#define M4U_PORT_L22_VDEC_UFO_EXT MTK_M4U_ID(22, 1)
308#define M4U_PORT_L22_VDEC_PP_EXT MTK_M4U_ID(22, 2)
309#define M4U_PORT_L22_VDEC_PRED_RD_EXT MTK_M4U_ID(22, 3)
310#define M4U_PORT_L22_VDEC_PRED_WR_EXT MTK_M4U_ID(22, 4)
311#define M4U_PORT_L22_VDEC_PPWRAP_EXT MTK_M4U_ID(22, 5)
312#define M4U_PORT_L22_VDEC_TILE_EXT MTK_M4U_ID(22, 6)
313#define M4U_PORT_L22_VDEC_VLD_EXT MTK_M4U_ID(22, 7)
314#define M4U_PORT_L22_VDEC_VLD2_EXT MTK_M4U_ID(22, 8)
315#define M4U_PORT_L22_VDEC_AVC_MV_EXT MTK_M4U_ID(22, 9)
316
317/* larb23 */
318#define M4U_PORT_L23_VDEC_UFO_ENC_EXT MTK_M4U_ID(23, 0)
319#define M4U_PORT_L23_VDEC_RDMA_EXT MTK_M4U_ID(23, 1)
320
321/* larb24 */
322#define M4U_PORT_L24_VDEC_LAT0_VLD_EXT MTK_M4U_ID(24, 0)
323#define M4U_PORT_L24_VDEC_LAT0_VLD2_EXT MTK_M4U_ID(24, 1)
324#define M4U_PORT_L24_VDEC_LAT0_AVC_MC_EXT MTK_M4U_ID(24, 2)
325#define M4U_PORT_L24_VDEC_LAT0_PRED_RD_EXT MTK_M4U_ID(24, 3)
326#define M4U_PORT_L24_VDEC_LAT0_TILE_EXT MTK_M4U_ID(24, 4)
327#define M4U_PORT_L24_VDEC_LAT0_WDMA_EXT MTK_M4U_ID(24, 5)
328#define M4U_PORT_L24_VDEC_LAT1_VLD_EXT MTK_M4U_ID(24, 6)
329#define M4U_PORT_L24_VDEC_LAT1_VLD2_EXT MTK_M4U_ID(24, 7)
330#define M4U_PORT_L24_VDEC_LAT1_AVC_MC_EXT MTK_M4U_ID(24, 8)
331#define M4U_PORT_L24_VDEC_LAT1_PRED_RD_EXT MTK_M4U_ID(24, 9)
332#define M4U_PORT_L24_VDEC_LAT1_TILE_EXT MTK_M4U_ID(24, 10)
333#define M4U_PORT_L24_VDEC_LAT1_WDMA_EXT MTK_M4U_ID(24, 11)
334
335/* larb25 */
336#define M4U_PORT_L25_CAM_MRAW0_LSCI_M1 MTK_M4U_ID(25, 0)
337#define M4U_PORT_L25_CAM_MRAW0_CQI_M1 MTK_M4U_ID(25, 1)
338#define M4U_PORT_L25_CAM_MRAW0_CQI_M2 MTK_M4U_ID(25, 2)
339#define M4U_PORT_L25_CAM_MRAW0_IMGO_M1 MTK_M4U_ID(25, 3)
340#define M4U_PORT_L25_CAM_MRAW0_IMGBO_M1 MTK_M4U_ID(25, 4)
341#define M4U_PORT_L25_CAM_MRAW2_LSCI_M1 MTK_M4U_ID(25, 5)
342#define M4U_PORT_L25_CAM_MRAW2_CQI_M1 MTK_M4U_ID(25, 6)
343#define M4U_PORT_L25_CAM_MRAW2_CQI_M2 MTK_M4U_ID(25, 7)
344#define M4U_PORT_L25_CAM_MRAW2_IMGO_M1 MTK_M4U_ID(25, 8)
345#define M4U_PORT_L25_CAM_MRAW2_IMGBO_M1 MTK_M4U_ID(25, 9)
346#define M4U_PORT_L25_CAM_MRAW0_AFO_M1 MTK_M4U_ID(25, 10)
347#define M4U_PORT_L25_CAM_MRAW2_AFO_M1 MTK_M4U_ID(25, 11)
348
349/* larb26 */
350#define M4U_PORT_L26_CAM_MRAW1_LSCI_M1 MTK_M4U_ID(26, 0)
351#define M4U_PORT_L26_CAM_MRAW1_CQI_M1 MTK_M4U_ID(26, 1)
352#define M4U_PORT_L26_CAM_MRAW1_CQI_M2 MTK_M4U_ID(26, 2)
353#define M4U_PORT_L26_CAM_MRAW1_IMGO_M1 MTK_M4U_ID(26, 3)
354#define M4U_PORT_L26_CAM_MRAW1_IMGBO_M1 MTK_M4U_ID(26, 4)
355#define M4U_PORT_L26_CAM_MRAW3_LSCI_M1 MTK_M4U_ID(26, 5)
356#define M4U_PORT_L26_CAM_MRAW3_CQI_M1 MTK_M4U_ID(26, 6)
357#define M4U_PORT_L26_CAM_MRAW3_CQI_M2 MTK_M4U_ID(26, 7)
358#define M4U_PORT_L26_CAM_MRAW3_IMGO_M1 MTK_M4U_ID(26, 8)
359#define M4U_PORT_L26_CAM_MRAW3_IMGBO_M1 MTK_M4U_ID(26, 9)
360#define M4U_PORT_L26_CAM_MRAW1_AFO_M1 MTK_M4U_ID(26, 10)
361#define M4U_PORT_L26_CAM_MRAW3_AFO_M1 MTK_M4U_ID(26, 11)
362
363/* larb27 */
364#define M4U_PORT_L27_CAM_IMGO_R1 MTK_M4U_ID(27, 0)
365#define M4U_PORT_L27_CAM_CQI_R1 MTK_M4U_ID(27, 1)
366#define M4U_PORT_L27_CAM_CQI_R2 MTK_M4U_ID(27, 2)
367#define M4U_PORT_L27_CAM_BPCI_R1 MTK_M4U_ID(27, 3)
368#define M4U_PORT_L27_CAM_LSCI_R1 MTK_M4U_ID(27, 4)
369#define M4U_PORT_L27_CAM_RAWI_R2 MTK_M4U_ID(27, 5)
370#define M4U_PORT_L27_CAM_RAWI_R3 MTK_M4U_ID(27, 6)
371#define M4U_PORT_L27_CAM_UFDI_R2 MTK_M4U_ID(27, 7)
372#define M4U_PORT_L27_CAM_UFDI_R3 MTK_M4U_ID(27, 8)
373#define M4U_PORT_L27_CAM_RAWI_R4 MTK_M4U_ID(27, 9)
374#define M4U_PORT_L27_CAM_RAWI_R5 MTK_M4U_ID(27, 10)
375#define M4U_PORT_L27_CAM_AAI_R1 MTK_M4U_ID(27, 11)
376#define M4U_PORT_L27_CAM_FHO_R1 MTK_M4U_ID(27, 12)
377#define M4U_PORT_L27_CAM_AAO_R1 MTK_M4U_ID(27, 13)
378#define M4U_PORT_L27_CAM_TSFSO_R1 MTK_M4U_ID(27, 14)
379#define M4U_PORT_L27_CAM_FLKO_R1 MTK_M4U_ID(27, 15)
380
381/* larb28 */
382#define M4U_PORT_L28_CAM_YUVO_R1 MTK_M4U_ID(28, 0)
383#define M4U_PORT_L28_CAM_YUVO_R3 MTK_M4U_ID(28, 1)
384#define M4U_PORT_L28_CAM_YUVCO_R1 MTK_M4U_ID(28, 2)
385#define M4U_PORT_L28_CAM_YUVO_R2 MTK_M4U_ID(28, 3)
386#define M4U_PORT_L28_CAM_RZH1N2TO_R1 MTK_M4U_ID(28, 4)
387#define M4U_PORT_L28_CAM_DRZS4NO_R1 MTK_M4U_ID(28, 5)
388#define M4U_PORT_L28_CAM_TNCSO_R1 MTK_M4U_ID(28, 6)
389
390/* Infra iommu ports */
391/* PCIe1: read: BIT16; write BIT17. */
392#define IOMMU_PORT_INFRA_PCIE1 MTK_IFAIOMMU_PERI_ID(16)
393/* PCIe0: read: BIT18; write BIT19. */
394#define IOMMU_PORT_INFRA_PCIE0 MTK_IFAIOMMU_PERI_ID(18)
395#define IOMMU_PORT_INFRA_SSUSB_P3_R MTK_IFAIOMMU_PERI_ID(20)
396#define IOMMU_PORT_INFRA_SSUSB_P3_W MTK_IFAIOMMU_PERI_ID(21)
397#define IOMMU_PORT_INFRA_SSUSB_P2_R MTK_IFAIOMMU_PERI_ID(22)
398#define IOMMU_PORT_INFRA_SSUSB_P2_W MTK_IFAIOMMU_PERI_ID(23)
399#define IOMMU_PORT_INFRA_SSUSB_P1_1_R MTK_IFAIOMMU_PERI_ID(24)
400#define IOMMU_PORT_INFRA_SSUSB_P1_1_W MTK_IFAIOMMU_PERI_ID(25)
401#define IOMMU_PORT_INFRA_SSUSB_P1_0_R MTK_IFAIOMMU_PERI_ID(26)
402#define IOMMU_PORT_INFRA_SSUSB_P1_0_W MTK_IFAIOMMU_PERI_ID(27)
403#define IOMMU_PORT_INFRA_SSUSB2_R MTK_IFAIOMMU_PERI_ID(28)
404#define IOMMU_PORT_INFRA_SSUSB2_W MTK_IFAIOMMU_PERI_ID(29)
405#define IOMMU_PORT_INFRA_SSUSB_R MTK_IFAIOMMU_PERI_ID(30)
406#define IOMMU_PORT_INFRA_SSUSB_W MTK_IFAIOMMU_PERI_ID(31)
407
408#endif
include/dt-bindings/memory/mtk-memory-port.h+2−0
@@ -12,4 +12,6 @@ · 11 unmodified lines
12#define MTK_M4U_TO_LARB(id) (((id) >> 5) & 0x1f)12#define MTK_M4U_TO_LARB(id) (((id) >> 5) & 0x1f)
13#define MTK_M4U_TO_PORT(id) ((id) & 0x1f)13#define MTK_M4U_TO_PORT(id) ((id) & 0x1f)
14 14
15#define MTK_IFAIOMMU_PERI_ID(port) MTK_M4U_ID(0, port)
16
15#endif17#endif
include/linux/amba/bus.h+8−0
@@ -79,6 +79,14 @@ struct amba_driver { · 78 unmodified lines
79 void (*remove)(struct amba_device *);79 void (*remove)(struct amba_device *);
80 void (*shutdown)(struct amba_device *);80 void (*shutdown)(struct amba_device *);
81 const struct amba_id *id_table;81 const struct amba_id *id_table;
82 /*
83 * For most device drivers, no need to care about this flag as long as
84 * all DMAs are handled through the kernel DMA API. For some special
85 * ones, for example VFIO drivers, they know how to manage the DMA
86 * themselves and set this flag so that the IOMMU layer will allow them
87 * to setup and manage their own I/O address space.
88 */
89 bool driver_managed_dma;
82};90};
83 91
84/*92/*
include/linux/bio.h+4−1
@@ -269,6 +269,7 @@ struct folio_iter { · 268 unmodified lines
269 size_t offset;269 size_t offset;
270 size_t length;270 size_t length;
271 /* private: for use by the iterator */271 /* private: for use by the iterator */
272 struct folio *_next;
272 size_t _seg_count;273 size_t _seg_count;
273 int _i;274 int _i;
274};275};
@@ -283,6 +284,7 @@ static inline void bio_first_folio(struct folio_iter *fi, struct bio *bio, · 8 unmodified lines
283 PAGE_SIZE * (bvec->bv_page - &fi->folio->page);284 PAGE_SIZE * (bvec->bv_page - &fi->folio->page);
284 fi->_seg_count = bvec->bv_len;285 fi->_seg_count = bvec->bv_len;
285 fi->length = min(folio_size(fi->folio) - fi->offset, fi->_seg_count);286 fi->length = min(folio_size(fi->folio) - fi->offset, fi->_seg_count);
287 fi->_next = folio_next(fi->folio);
286 fi->_i = i;288 fi->_i = i;
287}289}
288 290
@@ -290,9 +292,10 @@ static inline void bio_next_folio(struct folio_iter *fi, struct bio *bio) · 1 unmodified line
290{292{
291 fi->_seg_count -= fi->length;293 fi->_seg_count -= fi->length;
292 if (fi->_seg_count) {294 if (fi->_seg_count) {
293 fi->folio = folio_next(fi->folio);295 fi->folio = fi->_next;
294 fi->offset = 0;296 fi->offset = 0;
295 fi->length = min(folio_size(fi->folio), fi->_seg_count);297 fi->length = min(folio_size(fi->folio), fi->_seg_count);
298 fi->_next = folio_next(fi->folio);
296 } else if (fi->_i + 1 < bio->bi_vcnt) {299 } else if (fi->_i + 1 < bio->bi_vcnt) {
297 bio_first_folio(fi, bio, fi->_i + 1);300 bio_first_folio(fi, bio, fi->_i + 1);
298 } else {301 } else {
include/linux/blk-mq.h+0−1
@@ -163,7 +163,6 @@ struct request { · 162 unmodified lines
163 struct rb_node rb_node; /* sort/lookup */163 struct rb_node rb_node; /* sort/lookup */
164 struct bio_vec special_vec;164 struct bio_vec special_vec;
165 void *completion_data;165 void *completion_data;
166 int error_count; /* for legacy drivers, don't use */
167 };166 };
168 167
169 168
include/linux/cpu.h+1−1
@@ -167,7 +167,7 @@ static inline int suspend_disable_secondary_cpus(void) { return 0; } · 166 unmodified lines
167static inline void suspend_enable_secondary_cpus(void) { }167static inline void suspend_enable_secondary_cpus(void) { }
168#endif /* !CONFIG_PM_SLEEP_SMP */168#endif /* !CONFIG_PM_SLEEP_SMP */
169 169
170void cpu_startup_entry(enum cpuhp_state state);170void __noreturn cpu_startup_entry(enum cpuhp_state state);
171 171
172void cpu_idle_poll_ctrl(bool enable);172void cpu_idle_poll_ctrl(bool enable);
173 173
include/linux/device/bus.h+3−0
@@ -59,6 +59,8 @@ struct fwnode_handle; · 58 unmodified lines
59 * bus supports.59 * bus supports.
60 * @dma_configure: Called to setup DMA configuration on a device on60 * @dma_configure: Called to setup DMA configuration on a device on
61 * this bus.61 * this bus.
62 * @dma_cleanup: Called to cleanup DMA configuration on a device on
63 * this bus.
62 * @pm: Power management operations of this bus, callback the specific64 * @pm: Power management operations of this bus, callback the specific
63 * device driver's pm-ops.65 * device driver's pm-ops.
64 * @iommu_ops: IOMMU specific operations for this bus, used to attach IOMMU66 * @iommu_ops: IOMMU specific operations for this bus, used to attach IOMMU
@@ -103,6 +105,7 @@ struct bus_type { · 38 unmodified lines
103 int (*num_vf)(struct device *dev);105 int (*num_vf)(struct device *dev);
104 106
105 int (*dma_configure)(struct device *dev);107 int (*dma_configure)(struct device *dev);
108 void (*dma_cleanup)(struct device *dev);
106 109
107 const struct dev_pm_ops *pm;110 const struct dev_pm_ops *pm;
108 111
include/linux/fsl/mc.h+8−0
@@ -32,6 +32,13 @@ struct fsl_mc_io; · 31 unmodified lines
32 * @shutdown: Function called at shutdown time to quiesce the device32 * @shutdown: Function called at shutdown time to quiesce the device
33 * @suspend: Function called when a device is stopped33 * @suspend: Function called when a device is stopped
34 * @resume: Function called when a device is resumed34 * @resume: Function called when a device is resumed
35 * @driver_managed_dma: Device driver doesn't use kernel DMA API for DMA.
36 * For most device drivers, no need to care about this flag
37 * as long as all DMAs are handled through the kernel DMA API.
38 * For some special ones, for example VFIO drivers, they know
39 * how to manage the DMA themselves and set this flag so that
40 * the IOMMU layer will allow them to setup and manage their
41 * own I/O address space.
35 *42 *
36 * Generic DPAA device driver object for device drivers that are registered43 * Generic DPAA device driver object for device drivers that are registered
37 * with a DPRC bus. This structure is to be embedded in each device-specific44 * with a DPRC bus. This structure is to be embedded in each device-specific
@@ -45,6 +52,7 @@ struct fsl_mc_driver { · 7 unmodified lines
45 void (*shutdown)(struct fsl_mc_device *dev);52 void (*shutdown)(struct fsl_mc_device *dev);
46 int (*suspend)(struct fsl_mc_device *dev, pm_message_t state);53 int (*suspend)(struct fsl_mc_device *dev, pm_message_t state);
47 int (*resume)(struct fsl_mc_device *dev);54 int (*resume)(struct fsl_mc_device *dev);
55 bool driver_managed_dma;
48};56};
49 57
50#define to_fsl_mc_driver(_drv) \58#define to_fsl_mc_driver(_drv) \
include/linux/intel-iommu.h+2−1
@@ -539,7 +539,8 @@ struct dmar_domain { · 538 unmodified lines
539 539
540 u8 has_iotlb_device: 1;540 u8 has_iotlb_device: 1;
541 u8 iommu_coherency: 1; /* indicate coherency of iommu access */541 u8 iommu_coherency: 1; /* indicate coherency of iommu access */
542 u8 iommu_snooping: 1; /* indicate snooping control feature */542 u8 force_snooping : 1; /* Create IOPTEs with snoop control */
543 u8 set_pte_snp:1;
543 544
544 struct list_head devices; /* all devices' list */545 struct list_head devices; /* all devices' list */
545 struct iova_domain iovad; /* iova's that belong to this domain */546 struct iova_domain iovad; /* iova's that belong to this domain */
include/linux/intel-svm.h+1−1
@@ -9,7 +9,7 @@ · 8 unmodified lines
9#define __INTEL_SVM_H__9#define __INTEL_SVM_H__
10 10
11/* Page Request Queue depth */11/* Page Request Queue depth */
12#define PRQ_ORDER 212#define PRQ_ORDER 4
13#define PRQ_RING_MASK ((0x1000 << PRQ_ORDER) - 0x20)13#define PRQ_RING_MASK ((0x1000 << PRQ_ORDER) - 0x20)
14#define PRQ_DEPTH ((0x1000 << PRQ_ORDER) >> 5)14#define PRQ_DEPTH ((0x1000 << PRQ_ORDER) >> 5)
15 15
include/linux/iommu.h+44−25
@@ -103,10 +103,11 @@ static inline bool iommu_is_dma_domain(struct iommu_domain *domain) · 102 unmodified lines
103}103}
104 104
105enum iommu_cap {105enum iommu_cap {
106 IOMMU_CAP_CACHE_COHERENCY, /* IOMMU can enforce cache coherent DMA106 IOMMU_CAP_CACHE_COHERENCY, /* IOMMU_CACHE is supported */
107 transactions */
108 IOMMU_CAP_INTR_REMAP, /* IOMMU supports interrupt isolation */107 IOMMU_CAP_INTR_REMAP, /* IOMMU supports interrupt isolation */
109 IOMMU_CAP_NOEXEC, /* IOMMU_NOEXEC flag */108 IOMMU_CAP_NOEXEC, /* IOMMU_NOEXEC flag */
109 IOMMU_CAP_PRE_BOOT_PROTECTION, /* Firmware says it used the IOMMU for
110 DMA protection and we should too */
110};111};
111 112
112/* These are the possible reserved region types */113/* These are the possible reserved region types */
@@ -272,6 +273,9 @@ struct iommu_ops { · 159 unmodified lines
272 * @iotlb_sync: Flush all queued ranges from the hardware TLBs and empty flush273 * @iotlb_sync: Flush all queued ranges from the hardware TLBs and empty flush
273 * queue274 * queue
274 * @iova_to_phys: translate iova to physical address275 * @iova_to_phys: translate iova to physical address
276 * @enforce_cache_coherency: Prevent any kind of DMA from bypassing IOMMU_CACHE,
277 * including no-snoop TLPs on PCIe or other platform
278 * specific mechanisms.
275 * @enable_nesting: Enable nesting279 * @enable_nesting: Enable nesting
276 * @set_pgtable_quirks: Set io page table quirks (IO_PGTABLE_QUIRK_*)280 * @set_pgtable_quirks: Set io page table quirks (IO_PGTABLE_QUIRK_*)
277 * @free: Release the domain after use.281 * @free: Release the domain after use.
@@ -300,6 +304,7 @@ struct iommu_domain_ops { · 22 unmodified lines
300 phys_addr_t (*iova_to_phys)(struct iommu_domain *domain,304 phys_addr_t (*iova_to_phys)(struct iommu_domain *domain,
301 dma_addr_t iova);305 dma_addr_t iova);
302 306
307 bool (*enforce_cache_coherency)(struct iommu_domain *domain);
303 int (*enable_nesting)(struct iommu_domain *domain);308 int (*enable_nesting)(struct iommu_domain *domain);
304 int (*set_pgtable_quirks)(struct iommu_domain *domain,309 int (*set_pgtable_quirks)(struct iommu_domain *domain,
305 unsigned long quirks);310 unsigned long quirks);
@@ -407,16 +412,10 @@ static inline const struct iommu_ops *dev_iommu_ops(struct device *dev) · 101 unmodified lines
407 return dev->iommu->iommu_dev->ops;412 return dev->iommu->iommu_dev->ops;
408}413}
409 414
410#define IOMMU_GROUP_NOTIFY_ADD_DEVICE 1 /* Device added */
411#define IOMMU_GROUP_NOTIFY_DEL_DEVICE 2 /* Pre Device removed */
412#define IOMMU_GROUP_NOTIFY_BIND_DRIVER 3 /* Pre Driver bind */
413#define IOMMU_GROUP_NOTIFY_BOUND_DRIVER 4 /* Post Driver bind */
414#define IOMMU_GROUP_NOTIFY_UNBIND_DRIVER 5 /* Pre Driver unbind */
415#define IOMMU_GROUP_NOTIFY_UNBOUND_DRIVER 6 /* Post Driver unbind */
416
417extern int bus_set_iommu(struct bus_type *bus, const struct iommu_ops *ops);415extern int bus_set_iommu(struct bus_type *bus, const struct iommu_ops *ops);
418extern int bus_iommu_probe(struct bus_type *bus);416extern int bus_iommu_probe(struct bus_type *bus);
419extern bool iommu_present(struct bus_type *bus);417extern bool iommu_present(struct bus_type *bus);
418extern bool device_iommu_capable(struct device *dev, enum iommu_cap cap);
420extern bool iommu_capable(struct bus_type *bus, enum iommu_cap cap);419extern bool iommu_capable(struct bus_type *bus, enum iommu_cap cap);
421extern struct iommu_domain *iommu_domain_alloc(struct bus_type *bus);420extern struct iommu_domain *iommu_domain_alloc(struct bus_type *bus);
422extern struct iommu_group *iommu_group_get_by_id(int id);421extern struct iommu_group *iommu_group_get_by_id(int id);
@@ -478,10 +477,6 @@ extern int iommu_group_for_each_dev(struct iommu_group *group, void *data, · 55 unmodified lines
478extern struct iommu_group *iommu_group_get(struct device *dev);477extern struct iommu_group *iommu_group_get(struct device *dev);
479extern struct iommu_group *iommu_group_ref_get(struct iommu_group *group);478extern struct iommu_group *iommu_group_ref_get(struct iommu_group *group);
480extern void iommu_group_put(struct iommu_group *group);479extern void iommu_group_put(struct iommu_group *group);
481extern int iommu_group_register_notifier(struct iommu_group *group,
482 struct notifier_block *nb);
483extern int iommu_group_unregister_notifier(struct iommu_group *group,
484 struct notifier_block *nb);
485extern int iommu_register_device_fault_handler(struct device *dev,480extern int iommu_register_device_fault_handler(struct device *dev,
486 iommu_dev_fault_handler_t handler,481 iommu_dev_fault_handler_t handler,
487 void *data);482 void *data);
@@ -675,6 +670,13 @@ struct iommu_sva *iommu_sva_bind_device(struct device *dev, · 187 unmodified lines
675void iommu_sva_unbind_device(struct iommu_sva *handle);670void iommu_sva_unbind_device(struct iommu_sva *handle);
676u32 iommu_sva_get_pasid(struct iommu_sva *handle);671u32 iommu_sva_get_pasid(struct iommu_sva *handle);
677 672
673int iommu_device_use_default_domain(struct device *dev);
674void iommu_device_unuse_default_domain(struct device *dev);
675
676int iommu_group_claim_dma_owner(struct iommu_group *group, void *owner);
677void iommu_group_release_dma_owner(struct iommu_group *group);
678bool iommu_group_dma_owner_claimed(struct iommu_group *group);
679
678#else /* CONFIG_IOMMU_API */680#else /* CONFIG_IOMMU_API */
679 681
680struct iommu_ops {};682struct iommu_ops {};
@@ -689,6 +691,11 @@ static inline bool iommu_present(struct bus_type *bus) · 8 unmodified lines
689 return false;691 return false;
690}692}
691 693
694static inline bool device_iommu_capable(struct device *dev, enum iommu_cap cap)
695{
696 return false;
697}
698
692static inline bool iommu_capable(struct bus_type *bus, enum iommu_cap cap)699static inline bool iommu_capable(struct bus_type *bus, enum iommu_cap cap)
693{700{
694 return false;701 return false;
@@ -871,18 +878,6 @@ static inline void iommu_group_put(struct iommu_group *group) · 176 unmodified lines
871{878{
872}879}
873 880
874static inline int iommu_group_register_notifier(struct iommu_group *group,
875 struct notifier_block *nb)
876{
877 return -ENODEV;
878}
879
880static inline int iommu_group_unregister_notifier(struct iommu_group *group,
881 struct notifier_block *nb)
882{
883 return 0;
884}
885
886static inline881static inline
887int iommu_register_device_fault_handler(struct device *dev,882int iommu_register_device_fault_handler(struct device *dev,
888 iommu_dev_fault_handler_t handler,883 iommu_dev_fault_handler_t handler,
@@ -1031,6 +1026,30 @@ static inline struct iommu_fwspec *dev_iommu_fwspec_get(struct device *dev) · 142 unmodified lines
1031{1026{
1032 return NULL;1027 return NULL;
1033}1028}
1029
1030static inline int iommu_device_use_default_domain(struct device *dev)
1031{
1032 return 0;
1033}
1034
1035static inline void iommu_device_unuse_default_domain(struct device *dev)
1036{
1037}
1038
1039static inline int
1040iommu_group_claim_dma_owner(struct iommu_group *group, void *owner)
1041{
1042 return -ENODEV;
1043}
1044
1045static inline void iommu_group_release_dma_owner(struct iommu_group *group)
1046{
1047}
1048
1049static inline bool iommu_group_dma_owner_claimed(struct iommu_group *group)
1050{
1051 return false;
1052}
1034#endif /* CONFIG_IOMMU_API */1053#endif /* CONFIG_IOMMU_API */
1035 1054
1036/**1055/**
include/linux/kernel.h+1−1
@@ -285,7 +285,7 @@ static inline char *hex_byte_pack_upper(char *buf, u8 byte) · 284 unmodified lines
285 return buf;285 return buf;
286}286}
287 287
288extern int hex_to_bin(char ch);288extern int hex_to_bin(unsigned char ch);
289extern int __must_check hex2bin(u8 *dst, const char *src, size_t count);289extern int __must_check hex2bin(u8 *dst, const char *src, size_t count);
290extern char *bin2hex(char *dst, const void *src, size_t count);290extern char *bin2hex(char *dst, const void *src, size_t count);
291 291
include/linux/mtd/mtd.h+2−4
@@ -389,10 +389,8 @@ struct mtd_info { · 388 unmodified lines
389 /* List of partitions attached to this MTD device */389 /* List of partitions attached to this MTD device */
390 struct list_head partitions;390 struct list_head partitions;
391 391
392 union {392 struct mtd_part part;
393 struct mtd_part part;393 struct mtd_master master;
394 struct mtd_master master;
395 };
396};394};
397 395
398static inline struct mtd_info *mtd_get_master(struct mtd_info *mtd)396static inline struct mtd_info *mtd_get_master(struct mtd_info *mtd)
include/linux/netdev_features.h+2−2
@@ -169,7 +169,7 @@ enum { · 168 unmodified lines
169#define NETIF_F_HW_HSR_FWD __NETIF_F(HW_HSR_FWD)169#define NETIF_F_HW_HSR_FWD __NETIF_F(HW_HSR_FWD)
170#define NETIF_F_HW_HSR_DUP __NETIF_F(HW_HSR_DUP)170#define NETIF_F_HW_HSR_DUP __NETIF_F(HW_HSR_DUP)
171 171
172/* Finds the next feature with the highest number of the range of start till 0.172/* Finds the next feature with the highest number of the range of start-1 till 0.
173 */173 */
174static inline int find_next_netdev_feature(u64 feature, unsigned long start)174static inline int find_next_netdev_feature(u64 feature, unsigned long start)
175{175{
@@ -188,7 +188,7 @@ static inline int find_next_netdev_feature(u64 feature, unsigned long start) · 12 unmodified lines
188 for ((bit) = find_next_netdev_feature((mask_addr), \188 for ((bit) = find_next_netdev_feature((mask_addr), \
189 NETDEV_FEATURE_COUNT); \189 NETDEV_FEATURE_COUNT); \
190 (bit) >= 0; \190 (bit) >= 0; \
191 (bit) = find_next_netdev_feature((mask_addr), (bit) - 1))191 (bit) = find_next_netdev_feature((mask_addr), (bit)))
192 192
193/* Features valid for ethtool to change */193/* Features valid for ethtool to change */
194/* = all defined minus driver/device-class-related */194/* = all defined minus driver/device-class-related */
include/linux/netdevice.h+9−12
@@ -199,10 +199,10 @@ struct net_device_stats { · 198 unmodified lines
199 * Try to fit them in a single cache line, for dev_get_stats() sake.199 * Try to fit them in a single cache line, for dev_get_stats() sake.
200 */200 */
201struct net_device_core_stats {201struct net_device_core_stats {
202 local_t rx_dropped;202 unsigned long rx_dropped;
203 local_t tx_dropped;203 unsigned long tx_dropped;
204 local_t rx_nohandler;204 unsigned long rx_nohandler;
205} __aligned(4 * sizeof(local_t));205} __aligned(4 * sizeof(unsigned long));
206 206
207#include <linux/cache.h>207#include <linux/cache.h>
208#include <linux/skbuff.h>208#include <linux/skbuff.h>
@@ -3843,15 +3843,15 @@ static __always_inline bool __is_skb_forwardable(const struct net_device *dev, · 3634 unmodified lines
3843 return false;3843 return false;
3844}3844}
3845 3845
3846struct net_device_core_stats *netdev_core_stats_alloc(struct net_device *dev);3846struct net_device_core_stats __percpu *netdev_core_stats_alloc(struct net_device *dev);
3847 3847
3848static inline struct net_device_core_stats *dev_core_stats(struct net_device *dev)3848static inline struct net_device_core_stats __percpu *dev_core_stats(struct net_device *dev)
3849{3849{
3850 /* This READ_ONCE() pairs with the write in netdev_core_stats_alloc() */3850 /* This READ_ONCE() pairs with the write in netdev_core_stats_alloc() */
3851 struct net_device_core_stats __percpu *p = READ_ONCE(dev->core_stats);3851 struct net_device_core_stats __percpu *p = READ_ONCE(dev->core_stats);
3852 3852
3853 if (likely(p))3853 if (likely(p))
3854 return this_cpu_ptr(p);3854 return p;
3855 3855
3856 return netdev_core_stats_alloc(dev);3856 return netdev_core_stats_alloc(dev);
3857}3857}
@@ -3859,14 +3859,11 @@ static inline struct net_device_core_stats *dev_core_stats(struct net_device *de · 1 unmodified line
3859#define DEV_CORE_STATS_INC(FIELD) \3859#define DEV_CORE_STATS_INC(FIELD) \
3860static inline void dev_core_stats_##FIELD##_inc(struct net_device *dev) \3860static inline void dev_core_stats_##FIELD##_inc(struct net_device *dev) \
3861{ \3861{ \
3862 struct net_device_core_stats *p; \3862 struct net_device_core_stats __percpu *p; \
3863 \3863 \
3864 preempt_disable(); \
3865 p = dev_core_stats(dev); \3864 p = dev_core_stats(dev); \
3866 \
3867 if (p) \3865 if (p) \
3868 local_inc(&p->FIELD); \3866 this_cpu_inc(p->FIELD); \
3869 preempt_enable(); \
3870}3867}
3871DEV_CORE_STATS_INC(rx_dropped)3868DEV_CORE_STATS_INC(rx_dropped)
3872DEV_CORE_STATS_INC(tx_dropped)3869DEV_CORE_STATS_INC(tx_dropped)
include/linux/pci.h+8−0
@@ -895,6 +895,13 @@ struct module; · 894 unmodified lines
895 * created once it is bound to the driver.895 * created once it is bound to the driver.
896 * @driver: Driver model structure.896 * @driver: Driver model structure.
897 * @dynids: List of dynamically added device IDs.897 * @dynids: List of dynamically added device IDs.
898 * @driver_managed_dma: Device driver doesn't use kernel DMA API for DMA.
899 * For most device drivers, no need to care about this flag
900 * as long as all DMAs are handled through the kernel DMA API.
901 * For some special ones, for example VFIO drivers, they know
902 * how to manage the DMA themselves and set this flag so that
903 * the IOMMU layer will allow them to setup and manage their
904 * own I/O address space.
898 */905 */
899struct pci_driver {906struct pci_driver {
900 struct list_head node;907 struct list_head node;
@@ -913,6 +920,7 @@ struct pci_driver { · 12 unmodified lines
913 const struct attribute_group **dev_groups;920 const struct attribute_group **dev_groups;
914 struct device_driver driver;921 struct device_driver driver;
915 struct pci_dynids dynids;922 struct pci_dynids dynids;
923 bool driver_managed_dma;
916};924};
917 925
918static inline struct pci_driver *to_pci_driver(struct device_driver *drv)926static inline struct pci_driver *to_pci_driver(struct device_driver *drv)
include/linux/platform_device.h+8−2
@@ -210,6 +210,14 @@ struct platform_driver { · 209 unmodified lines
210 struct device_driver driver;210 struct device_driver driver;
211 const struct platform_device_id *id_table;211 const struct platform_device_id *id_table;
212 bool prevent_deferred_probe;212 bool prevent_deferred_probe;
213 /*
214 * For most device drivers, no need to care about this flag as long as
215 * all DMAs are handled through the kernel DMA API. For some special
216 * ones, for example VFIO drivers, they know how to manage the DMA
217 * themselves and set this flag so that the IOMMU layer will allow them
218 * to setup and manage their own I/O address space.
219 */
220 bool driver_managed_dma;
213};221};
214 222
215#define to_platform_driver(drv) (container_of((drv), struct platform_driver, \223#define to_platform_driver(drv) (container_of((drv), struct platform_driver, \
@@ -328,8 +336,6 @@ extern int platform_pm_restore(struct device *dev); · 112 unmodified lines
328#define platform_pm_restore NULL336#define platform_pm_restore NULL
329#endif337#endif
330 338
331extern int platform_dma_configure(struct device *dev);
332
333#ifdef CONFIG_PM_SLEEP339#ifdef CONFIG_PM_SLEEP
334#define USE_PLATFORM_PM_SLEEP_OPS \340#define USE_PLATFORM_PM_SLEEP_OPS \
335 .suspend = platform_pm_suspend, \341 .suspend = platform_pm_suspend, \
include/linux/stmmac.h+1−0
@@ -270,5 +270,6 @@ struct plat_stmmacenet_data { · 269 unmodified lines
270 int msi_rx_base_vec;270 int msi_rx_base_vec;
271 int msi_tx_base_vec;271 int msi_tx_base_vec;
272 bool use_phy_wol;272 bool use_phy_wol;
273 bool sph_disable;
273};274};
274#endif275#endif
include/linux/sunrpc/clnt.h+1−0
@@ -160,6 +160,7 @@ struct rpc_add_xprt_test { · 159 unmodified lines
160#define RPC_CLNT_CREATE_NO_RETRANS_TIMEOUT (1UL << 9)160#define RPC_CLNT_CREATE_NO_RETRANS_TIMEOUT (1UL << 9)
161#define RPC_CLNT_CREATE_SOFTERR (1UL << 10)161#define RPC_CLNT_CREATE_SOFTERR (1UL << 10)
162#define RPC_CLNT_CREATE_REUSEPORT (1UL << 11)162#define RPC_CLNT_CREATE_REUSEPORT (1UL << 11)
163#define RPC_CLNT_CREATE_CONNECTED (1UL << 12)
163 164
164struct rpc_clnt *rpc_create(struct rpc_create_args *args);165struct rpc_clnt *rpc_create(struct rpc_create_args *args);
165struct rpc_clnt *rpc_bind_new_program(struct rpc_clnt *,166struct rpc_clnt *rpc_bind_new_program(struct rpc_clnt *,
include/linux/thunderbolt.h+2−0
@@ -465,6 +465,7 @@ static inline struct tb_xdomain *tb_service_parent(struct tb_service *svc) · 464 unmodified lines
465 * @msix_ida: Used to allocate MSI-X vectors for rings465 * @msix_ida: Used to allocate MSI-X vectors for rings
466 * @going_away: The host controller device is about to disappear so when466 * @going_away: The host controller device is about to disappear so when
467 * this flag is set, avoid touching the hardware anymore.467 * this flag is set, avoid touching the hardware anymore.
468 * @iommu_dma_protection: An IOMMU will isolate external-facing ports.
468 * @interrupt_work: Work scheduled to handle ring interrupt when no469 * @interrupt_work: Work scheduled to handle ring interrupt when no
469 * MSI-X is used.470 * MSI-X is used.
470 * @hop_count: Number of rings (end point hops) supported by NHI.471 * @hop_count: Number of rings (end point hops) supported by NHI.
@@ -479,6 +480,7 @@ struct tb_nhi { · 8 unmodified lines
479 struct tb_ring **rx_rings;480 struct tb_ring **rx_rings;
480 struct ida msix_ida;481 struct ida msix_ida;
481 bool going_away;482 bool going_away;
483 bool iommu_dma_protection;
482 struct work_struct interrupt_work;484 struct work_struct interrupt_work;
483 u32 hop_count;485 u32 hop_count;
484 unsigned long quirks;486 unsigned long quirks;
include/linux/usb/pd_bdo.h+1−1
@@ -15,7 +15,7 @@ · 14 unmodified lines
15#define BDO_MODE_CARRIER2 (5 << 28)15#define BDO_MODE_CARRIER2 (5 << 28)
16#define BDO_MODE_CARRIER3 (6 << 28)16#define BDO_MODE_CARRIER3 (6 << 28)
17#define BDO_MODE_EYE (7 << 28)17#define BDO_MODE_EYE (7 << 28)
18#define BDO_MODE_TESTDATA (8 << 28)18#define BDO_MODE_TESTDATA (8U << 28)
19 19
20#define BDO_MODE_MASK(mode) ((mode) & 0xf0000000)20#define BDO_MODE_MASK(mode) ((mode) & 0xf0000000)
21 21
include/memory/renesas-rpc-if.h+1−0
@@ -72,6 +72,7 @@ struct rpcif { · 71 unmodified lines
72 enum rpcif_type type;72 enum rpcif_type type;
73 enum rpcif_data_dir dir;73 enum rpcif_data_dir dir;
74 u8 bus_size;74 u8 bus_size;
75 u8 xfer_size;
75 void *buffer;76 void *buffer;
76 u32 xferlen;77 u32 xferlen;
77 u32 smcr;78 u32 smcr;
include/net/bluetooth/hci.h+1−0
@@ -578,6 +578,7 @@ enum { · 577 unmodified lines
578#define HCI_ERROR_CONNECTION_TIMEOUT 0x08578#define HCI_ERROR_CONNECTION_TIMEOUT 0x08
579#define HCI_ERROR_REJ_LIMITED_RESOURCES 0x0d579#define HCI_ERROR_REJ_LIMITED_RESOURCES 0x0d
580#define HCI_ERROR_REJ_BAD_ADDR 0x0f580#define HCI_ERROR_REJ_BAD_ADDR 0x0f
581#define HCI_ERROR_INVALID_PARAMETERS 0x12
581#define HCI_ERROR_REMOTE_USER_TERM 0x13582#define HCI_ERROR_REMOTE_USER_TERM 0x13
582#define HCI_ERROR_REMOTE_LOW_RESOURCES 0x14583#define HCI_ERROR_REMOTE_LOW_RESOURCES 0x14
583#define HCI_ERROR_REMOTE_POWER_OFF 0x15584#define HCI_ERROR_REMOTE_POWER_OFF 0x15
include/net/bluetooth/hci_core.h+4−1
@@ -36,6 +36,9 @@ · 35 unmodified lines
36/* HCI priority */36/* HCI priority */
37#define HCI_PRIO_MAX 737#define HCI_PRIO_MAX 7
38 38
39/* HCI maximum id value */
40#define HCI_MAX_ID 10000
41
39/* HCI Core structures */42/* HCI Core structures */
40struct inquiry_data {43struct inquiry_data {
41 bdaddr_t bdaddr;44 bdaddr_t bdaddr;
@@ -1156,7 +1159,7 @@ int hci_conn_switch_role(struct hci_conn *conn, __u8 role); · 1114 unmodified lines
1156 1159
1157void hci_conn_enter_active_mode(struct hci_conn *conn, __u8 force_active);1160void hci_conn_enter_active_mode(struct hci_conn *conn, __u8 force_active);
1158 1161
1159void hci_le_conn_failed(struct hci_conn *conn, u8 status);1162void hci_conn_failed(struct hci_conn *conn, u8 status);
1160 1163
1161/*1164/*
1162 * hci_conn_get() and hci_conn_put() are used to control the life-time of an1165 * hci_conn_get() and hci_conn_put() are used to control the life-time of an
include/net/inet_hashtables.h+1−1
@@ -425,7 +425,7 @@ static inline void sk_rcv_saddr_set(struct sock *sk, __be32 addr) · 424 unmodified lines
425}425}
426 426
427int __inet_hash_connect(struct inet_timewait_death_row *death_row,427int __inet_hash_connect(struct inet_timewait_death_row *death_row,
428 struct sock *sk, u32 port_offset,428 struct sock *sk, u64 port_offset,
429 int (*check_established)(struct inet_timewait_death_row *,429 int (*check_established)(struct inet_timewait_death_row *,
430 struct sock *, __u16,430 struct sock *, __u16,
431 struct inet_timewait_sock **));431 struct inet_timewait_sock **));
include/net/ip6_tunnel.h+1−1
@@ -58,7 +58,7 @@ struct ip6_tnl { · 57 unmodified lines
58 58
59 /* These fields used only by GRE */59 /* These fields used only by GRE */
60 __u32 i_seqno; /* The last seen seqno */60 __u32 i_seqno; /* The last seen seqno */
61 __u32 o_seqno; /* The last output seqno */61 atomic_t o_seqno; /* The last output seqno */
62 int hlen; /* tun_hlen + encap_hlen */62 int hlen; /* tun_hlen + encap_hlen */
63 int tun_hlen; /* Precalculated header length */63 int tun_hlen; /* Precalculated header length */
64 int encap_hlen; /* Encap header length (FOU,GUE) */64 int encap_hlen; /* Encap header length (FOU,GUE) */
include/net/ip_tunnels.h+1−1
@@ -116,7 +116,7 @@ struct ip_tunnel { · 115 unmodified lines
116 116
117 /* These four fields used only by GRE */117 /* These four fields used only by GRE */
118 u32 i_seqno; /* The last seen seqno */118 u32 i_seqno; /* The last seen seqno */
119 u32 o_seqno; /* The last output seqno */119 atomic_t o_seqno; /* The last output seqno */
120 int tun_hlen; /* Precalculated header length */120 int tun_hlen; /* Precalculated header length */
121 121
122 /* These four fields used only by ERSPAN */122 /* These four fields used only by ERSPAN */
include/net/secure_seq.h+2−2
@@ -4,8 +4,8 @@ · 3 unmodified lines
4 4
5#include <linux/types.h>5#include <linux/types.h>
6 6
7u32 secure_ipv4_port_ephemeral(__be32 saddr, __be32 daddr, __be16 dport);7u64 secure_ipv4_port_ephemeral(__be32 saddr, __be32 daddr, __be16 dport);
8u32 secure_ipv6_port_ephemeral(const __be32 *saddr, const __be32 *daddr,8u64 secure_ipv6_port_ephemeral(const __be32 *saddr, const __be32 *daddr,
9 __be16 dport);9 __be16 dport);
10u32 secure_tcp_seq(__be32 saddr, __be32 daddr,10u32 secure_tcp_seq(__be32 saddr, __be32 daddr,
11 __be16 sport, __be16 dport);11 __be16 sport, __be16 dport);
include/net/tc_act/tc_pedit.h+1−0
@@ -14,6 +14,7 @@ struct tcf_pedit { · 13 unmodified lines
14 struct tc_action common;14 struct tc_action common;
15 unsigned char tcfp_nkeys;15 unsigned char tcfp_nkeys;
16 unsigned char tcfp_flags;16 unsigned char tcfp_flags;
17 u32 tcfp_off_max_hint;
17 struct tc_pedit_key *tcfp_keys;18 struct tc_pedit_key *tcfp_keys;
18 struct tcf_pedit_key_ex *tcfp_keys_ex;19 struct tcf_pedit_key_ex *tcfp_keys_ex;
19};20};
include/net/tcp.h+8−0
@@ -480,6 +480,7 @@ int __cookie_v4_check(const struct iphdr *iph, const struct tcphdr *th, · 479 unmodified lines
480 u32 cookie);480 u32 cookie);
481struct sock *cookie_v4_check(struct sock *sk, struct sk_buff *skb);481struct sock *cookie_v4_check(struct sock *sk, struct sk_buff *skb);
482struct request_sock *cookie_tcp_reqsk_alloc(const struct request_sock_ops *ops,482struct request_sock *cookie_tcp_reqsk_alloc(const struct request_sock_ops *ops,
483 const struct tcp_request_sock_ops *af_ops,
483 struct sock *sk, struct sk_buff *skb);484 struct sock *sk, struct sk_buff *skb);
484#ifdef CONFIG_SYN_COOKIES485#ifdef CONFIG_SYN_COOKIES
485 486
@@ -620,6 +621,7 @@ void tcp_synack_rtt_meas(struct sock *sk, struct request_sock *req); · 134 unmodified lines
620void tcp_reset(struct sock *sk, struct sk_buff *skb);621void tcp_reset(struct sock *sk, struct sk_buff *skb);
621void tcp_skb_mark_lost_uncond_verify(struct tcp_sock *tp, struct sk_buff *skb);622void tcp_skb_mark_lost_uncond_verify(struct tcp_sock *tp, struct sk_buff *skb);
622void tcp_fin(struct sock *sk);623void tcp_fin(struct sock *sk);
624void tcp_check_space(struct sock *sk);
623 625
624/* tcp_timer.c */626/* tcp_timer.c */
625void tcp_init_xmit_timers(struct sock *);627void tcp_init_xmit_timers(struct sock *);
@@ -1042,6 +1044,7 @@ struct rate_sample { · 416 unmodified lines
1042 int losses; /* number of packets marked lost upon ACK */1044 int losses; /* number of packets marked lost upon ACK */
1043 u32 acked_sacked; /* number of packets newly (S)ACKed upon ACK */1045 u32 acked_sacked; /* number of packets newly (S)ACKed upon ACK */
1044 u32 prior_in_flight; /* in flight before this ACK */1046 u32 prior_in_flight; /* in flight before this ACK */
1047 u32 last_end_seq; /* end_seq of most recently ACKed packet */
1045 bool is_app_limited; /* is sample from packet with bubble in pipe? */1048 bool is_app_limited; /* is sample from packet with bubble in pipe? */
1046 bool is_retrans; /* is sample from retransmission? */1049 bool is_retrans; /* is sample from retransmission? */
1047 bool is_ack_delayed; /* is this (likely) a delayed ACK? */1050 bool is_ack_delayed; /* is this (likely) a delayed ACK? */
@@ -1164,6 +1167,11 @@ void tcp_rate_gen(struct sock *sk, u32 delivered, u32 lost, · 116 unmodified lines
1164 bool is_sack_reneg, struct rate_sample *rs);1167 bool is_sack_reneg, struct rate_sample *rs);
1165void tcp_rate_check_app_limited(struct sock *sk);1168void tcp_rate_check_app_limited(struct sock *sk);
1166 1169
1170static inline bool tcp_skb_sent_after(u64 t1, u64 t2, u32 seq1, u32 seq2)
1171{
1172 return t1 > t2 || (t1 == t2 && after(seq1, seq2));
1173}
1174
1167/* These functions determine how the current flow behaves in respect of SACK1175/* These functions determine how the current flow behaves in respect of SACK
1168 * handling. SACK is negotiated with the peer, and therefore it can vary1176 * handling. SACK is negotiated with the peer, and therefore it can vary
1169 * between different flows.1177 * between different flows.
include/net/xsk_buff_pool.h+1−0
@@ -97,6 +97,7 @@ int xp_assign_dev(struct xsk_buff_pool *pool, struct net_device *dev, · 96 unmodified lines
97 u16 queue_id, u16 flags);97 u16 queue_id, u16 flags);
98int xp_assign_dev_shared(struct xsk_buff_pool *pool, struct xdp_umem *umem,98int xp_assign_dev_shared(struct xsk_buff_pool *pool, struct xdp_umem *umem,
99 struct net_device *dev, u16 queue_id);99 struct net_device *dev, u16 queue_id);
100int xp_alloc_tx_descs(struct xsk_buff_pool *pool, struct xdp_sock *xs);
100void xp_destroy(struct xsk_buff_pool *pool);101void xp_destroy(struct xsk_buff_pool *pool);
101void xp_get_pool(struct xsk_buff_pool *pool);102void xp_get_pool(struct xsk_buff_pool *pool);
102bool xp_put_pool(struct xsk_buff_pool *pool);103bool xp_put_pool(struct xsk_buff_pool *pool);
include/soc/mscc/ocelot_vcap.h+1−1
@@ -681,7 +681,6 @@ struct ocelot_vcap_id { · 680 unmodified lines
681 681
682struct ocelot_vcap_filter {682struct ocelot_vcap_filter {
683 struct list_head list;683 struct list_head list;
684 struct list_head trap_list;
685 684
686 enum ocelot_vcap_filter_type type;685 enum ocelot_vcap_filter_type type;
687 int block_id;686 int block_id;
@@ -695,6 +694,7 @@ struct ocelot_vcap_filter { · 7 unmodified lines
695 struct ocelot_vcap_stats stats;694 struct ocelot_vcap_stats stats;
696 /* For VCAP IS1 and IS2 */695 /* For VCAP IS1 and IS2 */
697 bool take_ts;696 bool take_ts;
697 bool is_trap;
698 unsigned long ingress_port_mask;698 unsigned long ingress_port_mask;
699 /* For VCAP ES0 */699 /* For VCAP ES0 */
700 struct ocelot_vcap_port ingress_port;700 struct ocelot_vcap_port ingress_port;
include/trace/events/sched.h+3−3
@@ -222,11 +222,11 @@ static inline long __trace_sched_switch_state(bool preempt, · 221 unmodified lines
222TRACE_EVENT(sched_switch,222TRACE_EVENT(sched_switch,
223 223
224 TP_PROTO(bool preempt,224 TP_PROTO(bool preempt,
225 unsigned int prev_state,
226 struct task_struct *prev,225 struct task_struct *prev,
227 struct task_struct *next),226 struct task_struct *next,
227 unsigned int prev_state),
228 228
229 TP_ARGS(preempt, prev_state, prev, next),229 TP_ARGS(preempt, prev, next, prev_state),
230 230
231 TP_STRUCT__entry(231 TP_STRUCT__entry(
232 __array( char, prev_comm, TASK_COMM_LEN )232 __array( char, prev_comm, TASK_COMM_LEN )
include/uapi/linux/elf.h+1−1
@@ -42,7 +42,7 @@ typedef __s64 Elf64_Sxword; · 41 unmodified lines
42 42
43 43
44/* ARM MTE memory tag segment type */44/* ARM MTE memory tag segment type */
45#define PT_ARM_MEMTAG_MTE (PT_LOPROC + 0x1)45#define PT_AARCH64_MEMTAG_MTE (PT_LOPROC + 0x2)
46 46
47/*47/*
48 * Extended Numbering48 * Extended Numbering
include/uapi/linux/fb.h+1−1
@@ -182,7 +182,7 @@ struct fb_fix_screeninfo { · 181 unmodified lines
182 *182 *
183 * For pseudocolor: offset and length should be the same for all color183 * For pseudocolor: offset and length should be the same for all color
184 * components. Offset specifies the position of the least significant bit184 * components. Offset specifies the position of the least significant bit
185 * of the pallette index in a pixel value. Length indicates the number185 * of the palette index in a pixel value. Length indicates the number
186 * of available palette entries (i.e. # of entries = 1 << length).186 * of available palette entries (i.e. # of entries = 1 << length).
187 */187 */
188struct fb_bitfield {188struct fb_bitfield {
include/uapi/linux/kvm.h+9−1
@@ -445,7 +445,13 @@ struct kvm_run { · 444 unmodified lines
445#define KVM_SYSTEM_EVENT_RESET 2445#define KVM_SYSTEM_EVENT_RESET 2
446#define KVM_SYSTEM_EVENT_CRASH 3446#define KVM_SYSTEM_EVENT_CRASH 3
447 __u32 type;447 __u32 type;
448 __u64 flags;448 __u32 ndata;
449 union {
450#ifndef __KERNEL__
451 __u64 flags;
452#endif
453 __u64 data[16];
454 };
449 } system_event;455 } system_event;
450 /* KVM_EXIT_S390_STSI */456 /* KVM_EXIT_S390_STSI */
451 struct {457 struct {
@@ -1144,6 +1150,8 @@ struct kvm_ppc_resize_hpt { · 692 unmodified lines
1144#define KVM_CAP_S390_MEM_OP_EXTENSION 2111150#define KVM_CAP_S390_MEM_OP_EXTENSION 211
1145#define KVM_CAP_PMU_CAPABILITY 2121151#define KVM_CAP_PMU_CAPABILITY 212
1146#define KVM_CAP_DISABLE_QUIRKS2 2131152#define KVM_CAP_DISABLE_QUIRKS2 213
1153/* #define KVM_CAP_VM_TSC_CONTROL 214 */
1154#define KVM_CAP_SYSTEM_EVENT_DATA 215
1147 1155
1148#ifdef KVM_CAP_IRQ_ROUTING1156#ifdef KVM_CAP_IRQ_ROUTING
1149 1157
include/uapi/linux/rfkill.h+1−1
@@ -184,7 +184,7 @@ struct rfkill_event_ext { · 183 unmodified lines
184#define RFKILL_IOC_NOINPUT 1184#define RFKILL_IOC_NOINPUT 1
185#define RFKILL_IOCTL_NOINPUT _IO(RFKILL_IOC_MAGIC, RFKILL_IOC_NOINPUT)185#define RFKILL_IOCTL_NOINPUT _IO(RFKILL_IOC_MAGIC, RFKILL_IOC_NOINPUT)
186#define RFKILL_IOC_MAX_SIZE 2186#define RFKILL_IOC_MAX_SIZE 2
187#define RFKILL_IOCTL_MAX_SIZE _IOW(RFKILL_IOC_MAGIC, RFKILL_IOC_EXT_SIZE, __u32)187#define RFKILL_IOCTL_MAX_SIZE _IOW(RFKILL_IOC_MAGIC, RFKILL_IOC_MAX_SIZE, __u32)
188 188
189/* and that's all userspace gets */189/* and that's all userspace gets */
190 190
include/uapi/linux/virtio_ids.h+7−7
@@ -73,12 +73,12 @@ · 72 unmodified lines
73 * Virtio Transitional IDs73 * Virtio Transitional IDs
74 */74 */
75 75
76#define VIRTIO_TRANS_ID_NET 1000 /* transitional virtio net */76#define VIRTIO_TRANS_ID_NET 0x1000 /* transitional virtio net */
77#define VIRTIO_TRANS_ID_BLOCK 1001 /* transitional virtio block */77#define VIRTIO_TRANS_ID_BLOCK 0x1001 /* transitional virtio block */
78#define VIRTIO_TRANS_ID_BALLOON 1002 /* transitional virtio balloon */78#define VIRTIO_TRANS_ID_BALLOON 0x1002 /* transitional virtio balloon */
79#define VIRTIO_TRANS_ID_CONSOLE 1003 /* transitional virtio console */79#define VIRTIO_TRANS_ID_CONSOLE 0x1003 /* transitional virtio console */
80#define VIRTIO_TRANS_ID_SCSI 1004 /* transitional virtio SCSI */80#define VIRTIO_TRANS_ID_SCSI 0x1004 /* transitional virtio SCSI */
81#define VIRTIO_TRANS_ID_RNG 1005 /* transitional virtio rng */81#define VIRTIO_TRANS_ID_RNG 0x1005 /* transitional virtio rng */
82#define VIRTIO_TRANS_ID_9P 1009 /* transitional virtio 9p console */82#define VIRTIO_TRANS_ID_9P 0x1009 /* transitional virtio 9p console */
83 83
84#endif /* _LINUX_VIRTIO_IDS_H */84#endif /* _LINUX_VIRTIO_IDS_H */