Merge tag 'gvt-next-2018-09-04' drm-intel-next-2018-09-06-1: UAPI Changes: - GGTT coherency GETPARAM: GGTT has turned out to be non-coherent for some platforms, which we've failed to communicate to userspace so far. SNA was modified to do extra flushing on non-coherent GGTT access, while Mesa will mitigate by always requiring WC mapping (which is non-coherent anyway). - Neuter Resource Streamer uAPI: There never really were users for the feature, so neuter it while keeping the interface bits for compatibility. This is a long due item from past. Cross-subsystem Changes: - Backmerge of branch drm-next-4.19 for DP_DPCD_REV_14 changes Core Changes: - None Driver Changes: - A load of Icelake (ICL) enabling patches (Paulo, Manasi) - Enabled full PPGTT for IVB,VLV and HSW (Chris) - Bugzilla #107113: Distribute DDB based on display resolutions (Mahesh) - Bugzillas #100023,#107476,#94921: Support limited range DP displays (Jani) - Bugzilla #107503: Increase LSPCON timeout (Fredrik) - Avoid boosting GPU due to an occasional stall in interactive workloads (Chris) - Apply GGTT coherency W/A only for affected systems instead of all (Chris) - Fix for infinite link training loop for faulty USB-C MST hubs (Nathan) - Keep KMS functional on Gen4 and earlier when GPU is wedged (Chris) - Stop holding ppGTT reference from closed VMAs (Chris) - Clear error registers after error capture (Lionel) - Various Icelake fixes (Anusha, Jyoti, Ville, Tvrtko) - Add missing Coffeelake (CFL) PCI IDs (Rodrigo) - Flush execlists tasklet directly from reset-finish (Chris) - Fix LPE audio runtime PM (Chris) - Fix detection of out of range surface positions (GLK/CNL) (Ville) - Remove wait-for-idle for PSR2 (Dhinakaran) - Power down existing display hardware resources when display is disabled (Chris) - Don't allow runtime power management if RC6 doesn't exist (Chris) - Add debugging checks for runtime power management paths (Imre) - Increase symmetry in display power init/fini paths (Imre) - Isolate GVT specific macros from i915_reg.h (Lucas) - Increase symmetry in power management enable/disable paths (Chris) - Increase IP disable timeout to 100 ms to avoid DRM_ERROR (Imre) - Fix memory leak from HDMI HDCP write function (Brian, Rodrigo) - Reject Y/Yf tiling on interlaced modes (Ville) - Use a cached mapping for the physical HWS on older gens (Chris) - Force slow path of writing relocations to buffer if unable to write to userspace (Chris) - Do a full device reset after being wedged (Chris) - Keep forcewake counts over reset (in case of debugfs user) (Imre, Chris) - Avoid false-positive errors from power wells during init (Imre) - Reset engines forcibly in exchange of declaring whole device wedged (Mika) - Reduce context HW ID lifetime in preparation for Icelake (Chris) - Attempt to recover from module load failures (Chris) - Keep select interrupts over a reset to avoid missing/losing them (Chris) - GuC submission backend improvements (Jakub) - Terminate context images with BB_END (Chris, Lionel) - Make GCC evaluate GGTT view struct size assertions again (Ville) - Add selftest to exercise suspend/hibernate code-paths for GEM (Chris) - Use a full emulation of a user ppgtt context in selftests (Chris) - Exercise resetting in the middle of a wait-on-fence in selftests (Chris) - Fix coherency issues on selftests for Baytrail (Chris) - Various other GEM fixes / self-test updates (Chris, Matt) - GuC doorbell self-tests (Daniele) - PSR mode control through debugfs for IGTs (Maarten) - Degrade expected WM latency errors to DRM_DEBUG_KMS (Chris) - Cope with errors better in MST link training (Dhinakaran) - Fix WARN on KBL external displays (Azhar) - Power well code cleanups (Imre) - Fixes to PSR debugging (Dhinakaran) - Make forcewake errors louder for easier catching in CI (WARNs) (Chris) - Fortify tiling code against programmer errors (Chris) - Bunch of fixes for CI exposed corner cases (multiple authors, mostly Chris) Signed-off-by: Dave Airlie <airlied@redhat.com>
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| @@ -529,6 +529,28 @@ typedef struct drm_i915_irq_wait { · 528 unmodified lines | ||
| 529 | 529 | */ |
| 530 | 530 | #define I915_PARAM_CS_TIMESTAMP_FREQUENCY 51 |
| 531 | 531 | |
| 532 | +/* | |
| 533 | + * Once upon a time we supposed that writes through the GGTT would be | |
| 534 | + * immediately in physical memory (once flushed out of the CPU path). However, | |
| 535 | + * on a few different processors and chipsets, this is not necessarily the case | |
| 536 | + * as the writes appear to be buffered internally. Thus a read of the backing | |
| 537 | + * storage (physical memory) via a different path (with different physical tags | |
| 538 | + * to the indirect write via the GGTT) will see stale values from before | |
| 539 | + * the GGTT write. Inside the kernel, we can for the most part keep track of | |
| 540 | + * the different read/write domains in use (e.g. set-domain), but the assumption | |
| 541 | + * of coherency is baked into the ABI, hence reporting its true state in this | |
| 542 | + * parameter. | |
| 543 | + * | |
| 544 | + * Reports true when writes via mmap_gtt are immediately visible following an | |
| 545 | + * lfence to flush the WCB. | |
| 546 | + * | |
| 547 | + * Reports false when writes via mmap_gtt are indeterminately delayed in an in | |
| 548 | + * internal buffer and are _not_ immediately visible to third parties accessing | |
| 549 | + * directly via mmap_cpu/mmap_wc. Use of mmap_gtt as part of an IPC | |
| 550 | + * communications channel when reporting false is strongly disadvised. | |
| 551 | + */ | |
| 552 | +#define I915_PARAM_MMAP_GTT_COHERENT 52 | |
| 553 | + | |
| 532 | 554 | typedef struct drm_i915_getparam { |
| 533 | 555 | __s32 param; |
| 534 | 556 | /* |