History

Merge tag 'drm-fixes-2023-12-01' of git://anongit.freedesktop.org/drm/drm

Pull drm fixes from Dave Airlie: "Weekly fixes, mostly amdgpu fixes with a scattering of nouveau, i915, and a couple of reverts. Hopefully it will quieten down in coming weeks. drm: - Revert unexport of prime helpers for fd/handle conversion dma_resv: - Do not double add fences in dma_resv_add_fence. gpuvm: - Fix GPUVM license identifier. i915: - Mark internal GSC engine with reserved uabi class - Take VGA converters into account in eDP probe - Fix intel_pre_plane_updates() call to ensure workarounds get applied panel: - Revert panel fixes as they require exporting device_is_dependent. nouveau: - fix oversized allocations in new vm path - fix zero-length array - remove a stray lock nt36523: - Fix error check for nt36523. amdgpu: - DMUB fix - DCN 3.5 fixes - XGMI fix - DCN 3.2 fixes - Vangogh suspend fix - NBIO 7.9 fix - GFX11 golden register fix - Backlight fix - NBIO 7.11 fix - IB test overflow fix - DCN 3.1.4 fixes - fix a runtime pm ref count - Retimer fix - ABM fix - DCN 3.1.5 fix - Fix AGP addressing - Fix possible memory leak in SMU error path - Make sure PME is enabled in D3 - Fix possible NULL pointer dereference in debugfs - EEPROM fix - GC 9.4.3 fix amdkfd: - IP version check fix - Fix memory leak in pqm_uninit()" * tag 'drm-fixes-2023-12-01' of git://anongit.freedesktop.org/drm/drm: (53 commits) Revert "drm/prime: Unexport helpers for fd/handle conversion" drm/amdgpu: Use another offset for GC 9.4.3 remap drm/amd/display: Fix some HostVM parameters in DML drm/amdkfd: Free gang_ctx_bo and wptr_bo in pqm_uninit drm/amdgpu: Update EEPROM I2C address for smu v13_0_0 drm/amd/display: Allow DTBCLK disable for DCN35 drm/amdgpu: Fix cat debugfs amdgpu_regs_didt causes kernel null pointer drm/amd: Enable PCIe PME from D3 drm/amd/pm: fix a memleak in aldebaran_tables_init drm/amdgpu: fix AGP addressing when GART is not at 0 drm/amd/display: update dcn315 lpddr pstate latency drm/amd/display: fix ABM disablement drm/amd/display: Fix black screen on video playback with embedded panel drm/amd/display: Fix conversions between bytes and KB drm/amdkfd: Use common function for IP version check drm/amd/display: Remove config update drm/amd/display: Update DCN35 clock table policy drm/amd/display: force toggle rate wa for first link training for a retimer drm/amdgpu: correct the amdgpu runtime dereference usage count drm/amd/display: Update min Z8 residency time to 2100 for DCN314 ...

Linus Torvalds committed 2 years ago

Commit b1e51582 parents c9a925b 908f60667 files · +537 −302Browse files

Unified · Split

67 files
  1. drivers/dma-buf/dma-resv.c +1 −1
  2. drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c +1 −1
  3. drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c +6 −0
  4. drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +4 −0
  5. drivers/gpu/drm/amd/amdgpu/amdgpu_display.c +3 −6
  6. drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c +2 −0
  7. drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c +3 −0
  8. drivers/gpu/drm/amd/amdgpu/amdgpu_object.c +7 −3
  9. drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c +6 −0
  10. drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c +1 −3
  11. drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c +9 −1
  12. drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c +2 −2
  13. drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c +2 −2
  14. drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c +2 −2
  15. drivers/gpu/drm/amd/amdgpu/nbio_v7_11.c +9 −9
  16. drivers/gpu/drm/amd/amdgpu/nbio_v7_9.c +0 −5
  17. drivers/gpu/drm/amd/amdgpu/soc15.c +5 −0
  18. drivers/gpu/drm/amd/amdkfd/kfd_priv.h +1 −1
  19. drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c +33 −21
  20. drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +5 −3
  21. drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c +4 −4
  22. drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c +79 −80
  23. drivers/gpu/drm/amd/display/dc/dc.h +1 −1
  24. drivers/gpu/drm/amd/display/dc/dc_types.h +0 −4
  25. drivers/gpu/drm/amd/display/dc/dcn314/dcn314_resource.c +1 −1
  26. drivers/gpu/drm/amd/display/dc/dcn35/dcn35_pg_cntl.c +10 −0
  27. drivers/gpu/drm/amd/display/dc/dcn35/dcn35_resource.c +8 −1
  28. drivers/gpu/drm/amd/display/dc/dml/dc_features.h +1 −1
  29. drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c +1 −14
  30. drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c +14 −9
  31. drivers/gpu/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c +80 −4
  32. drivers/gpu/drm/amd/display/dc/dml/dcn35/dcn35_fpu.h +2 −0
  33. drivers/gpu/drm/amd/display/dc/dml2/display_mode_core.c +8 −8
  34. drivers/gpu/drm/amd/display/dc/dml2/dml2_translation_helper.c +40 −20
  35. drivers/gpu/drm/amd/display/dc/dml2/dml2_wrapper.h +2 −0
  36. drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c +2 −4
  37. drivers/gpu/drm/amd/display/dc/link/link_detection.c +1 −1
  38. drivers/gpu/drm/amd/display/dc/link/link_dpms.c +1 −2
  39. drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_fixed_vs_pe_retimer.c +3 −3
  40. drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c +3 −13
  41. drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.h +0 −1
  42. drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c +1 −0
  43. drivers/gpu/drm/amd/include/asic_reg/gc/gc_11_0_0_offset.h +2 −0
  44. drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_7_11_0_offset.h +2 −0
  45. drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_7_11_0_sh_mask.h +29 −0
  46. drivers/gpu/drm/amd/include/kgd_pp_interface.h +1 −0
  47. drivers/gpu/drm/amd/pm/amdgpu_dpm.c +18 −0
  48. drivers/gpu/drm/amd/pm/inc/amdgpu_dpm.h +2 −0
  49. drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c +10 −0
  50. drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h +5 −0
  51. drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c +2 −3
  52. drivers/gpu/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c +4 −1
  53. drivers/gpu/drm/amd/pm/swsmu/smu_internal.h +1 −0
  54. drivers/gpu/drm/bridge/panel.c +0 −17
  55. drivers/gpu/drm/drm_gpuvm.c +1 −1
  56. drivers/gpu/drm/drm_prime.c +18 −15
  57. drivers/gpu/drm/i915/display/intel_display.c +2 −1
  58. drivers/gpu/drm/i915/display/intel_dp.c +22 −6
  59. drivers/gpu/drm/i915/gt/intel_engine_user.c +22 −17
  60. drivers/gpu/drm/nouveau/include/nvrm/535.113.01/nvidia/generated/g_os_nvoc.h +1 −1
  61. drivers/gpu/drm/nouveau/nouveau_bo.c +3 −2
  62. drivers/gpu/drm/nouveau/nvkm/subdev/gsp/r535.c +2 −4
  63. drivers/gpu/drm/panel/panel-boe-tv101wum-nl6.c +1 −0
  64. drivers/gpu/drm/panel/panel-novatek-nt36523.c +2 −2
  65. include/drm/drm_gpuvm.h +1 −1
  66. include/drm/drm_prime.h +7 −0
  67. include/linux/dma-fence.h +15 −0
drivers/dma-buf/dma-resv.c+1−1
@@ -301,7 +301,7 @@ void dma_resv_add_fence(struct dma_resv *obj, struct dma_fence *fence, · 300 unmodified lines
301301
302302 dma_resv_list_entry(fobj, i, obj, &old, &old_usage);
303303 if ((old->context == fence->context && old_usage >= usage &&
304− dma_fence_is_later(fence, old)) ||
304+ dma_fence_is_later_or_same(fence, old)) ||
305305 dma_fence_is_signaled(old)) {
306306 dma_resv_list_set(fobj, i, fence, usage);
307307 dma_fence_put(old);
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c+1−1
@@ -547,7 +547,7 @@ int amdgpu_amdkfd_get_xgmi_bandwidth_mbytes(struct amdgpu_device *dst, · 546 unmodified lines
547547 struct amdgpu_device *adev = dst, *peer_adev;
548548 int num_links;
549549
550− if (adev->asic_type != CHIP_ALDEBARAN)
550+ if (amdgpu_ip_version(adev, GC_HWIP, 0) < IP_VERSION(9, 4, 2))
551551 return 0;
552552
553553 if (src)
drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c+6−0
@@ -638,6 +638,9 @@ static ssize_t amdgpu_debugfs_regs_didt_read(struct file *f, char __user *buf, · 637 unmodified lines
638638 if (size & 0x3 || *pos & 0x3)
639639 return -EINVAL;
640640
641+ if (!adev->didt_rreg)
642+ return -EOPNOTSUPP;
643+
641644 r = pm_runtime_get_sync(adev_to_drm(adev)->dev);
642645 if (r < 0) {
643646 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
@@ -694,6 +697,9 @@ static ssize_t amdgpu_debugfs_regs_didt_write(struct file *f, const char __user · 50 unmodified lines
694697 if (size & 0x3 || *pos & 0x3)
695698 return -EINVAL;
696699
700+ if (!adev->didt_wreg)
701+ return -EOPNOTSUPP;
702+
697703 r = pm_runtime_get_sync(adev_to_drm(adev)->dev);
698704 if (r < 0) {
699705 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c+4−0
@@ -4538,6 +4538,10 @@ int amdgpu_device_suspend(struct drm_device *dev, bool fbcon) · 4537 unmodified lines
45384538 if (amdgpu_sriov_vf(adev))
45394539 amdgpu_virt_release_full_gpu(adev, false);
45404540
4541+ r = amdgpu_dpm_notify_rlc_state(adev, false);
4542+ if (r)
4543+ return r;
4544+
45414545 return 0;
45424546 }
45434547
drivers/gpu/drm/amd/amdgpu/amdgpu_display.c+3−6
@@ -340,14 +340,11 @@ int amdgpu_display_crtc_set_config(struct drm_mode_set *set, · 339 unmodified lines
340340 adev->have_disp_power_ref = true;
341341 return ret;
342342 }
343− /* if we have no active crtcs, then drop the power ref
344− * we got before
343+ /* if we have no active crtcs, then go to
344+ * drop the power ref we got before
345345 */
346− if (!active && adev->have_disp_power_ref) {
347− pm_runtime_put_autosuspend(dev->dev);
346+ if (!active && adev->have_disp_power_ref)
348347 adev->have_disp_power_ref = false;
349− }
350−
351348 out:
352349 /* drop the power reference we got coming in here */
353350 pm_runtime_put_autosuspend(dev->dev);
drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c+2−0
@@ -2263,6 +2263,8 @@ retry_init: · 2262 unmodified lines
22632263 pm_runtime_mark_last_busy(ddev->dev);
22642264 pm_runtime_put_autosuspend(ddev->dev);
22652265
2266+ pci_wake_from_d3(pdev, TRUE);
2267+
22662268 /*
22672269 * For runpm implemented via BACO, PMFW will handle the
22682270 * timing for BACO in and out:
drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c+3−0
@@ -181,6 +181,9 @@ uint64_t amdgpu_gmc_agp_addr(struct ttm_buffer_object *bo) · 180 unmodified lines
181181 {
182182 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev);
183183
184+ if (!bo->ttm)
185+ return AMDGPU_BO_INVALID_OFFSET;
186+
184187 if (bo->ttm->num_pages != 1 || bo->ttm->caching == ttm_cached)
185188 return AMDGPU_BO_INVALID_OFFSET;
186189
drivers/gpu/drm/amd/amdgpu/amdgpu_object.c+7−3
@@ -1527,10 +1527,14 @@ u64 amdgpu_bo_gpu_offset(struct amdgpu_bo *bo) · 1526 unmodified lines
15271527 u64 amdgpu_bo_gpu_offset_no_check(struct amdgpu_bo *bo)
15281528 {
15291529 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
1530− uint64_t offset;
1530+ uint64_t offset = AMDGPU_BO_INVALID_OFFSET;
15311531
1532− offset = (bo->tbo.resource->start << PAGE_SHIFT) +
1533− amdgpu_ttm_domain_start(adev, bo->tbo.resource->mem_type);
1532+ if (bo->tbo.resource->mem_type == TTM_PL_TT)
1533+ offset = amdgpu_gmc_agp_addr(&bo->tbo);
1534+
1535+ if (offset == AMDGPU_BO_INVALID_OFFSET)
1536+ offset = (bo->tbo.resource->start << PAGE_SHIFT) +
1537+ amdgpu_ttm_domain_start(adev, bo->tbo.resource->mem_type);
15341538
15351539 return amdgpu_gmc_sign_extend(offset);
15361540 }
drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c+6−0
@@ -214,6 +214,12 @@ static bool __get_eeprom_i2c_addr(struct amdgpu_device *adev, · 213 unmodified lines
214214 control->i2c_address = EEPROM_I2C_MADDR_0;
215215 return true;
216216 case IP_VERSION(13, 0, 0):
217+ if (strnstr(atom_ctx->vbios_pn, "D707",
218+ sizeof(atom_ctx->vbios_pn)))
219+ control->i2c_address = EEPROM_I2C_MADDR_0;
220+ else
221+ control->i2c_address = EEPROM_I2C_MADDR_4;
222+ return true;
217223 case IP_VERSION(13, 0, 6):
218224 case IP_VERSION(13, 0, 10):
219225 control->i2c_address = EEPROM_I2C_MADDR_4;
drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c+1−3
@@ -959,10 +959,8 @@ int amdgpu_ttm_alloc_gart(struct ttm_buffer_object *bo) · 958 unmodified lines
959959 return 0;
960960
961961 addr = amdgpu_gmc_agp_addr(bo);
962− if (addr != AMDGPU_BO_INVALID_OFFSET) {
963− bo->resource->start = addr >> PAGE_SHIFT;
962+ if (addr != AMDGPU_BO_INVALID_OFFSET)
964963 return 0;
965− }
966964
967965 /* allocate GART space */
968966 placement.num_placement = 1;
drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c+9−1
@@ -89,6 +89,10 @@ MODULE_FIRMWARE("amdgpu/gc_11_5_0_me.bin"); · 88 unmodified lines
8989 MODULE_FIRMWARE("amdgpu/gc_11_5_0_mec.bin");
9090 MODULE_FIRMWARE("amdgpu/gc_11_5_0_rlc.bin");
9191
92+static const struct soc15_reg_golden golden_settings_gc_11_0[] = {
93+ SOC15_REG_GOLDEN_VALUE(GC, 0, regTCP_CNTL, 0x20000000, 0x20000000)
94+};
95+
9296 static const struct soc15_reg_golden golden_settings_gc_11_0_1[] =
9397 {
9498 SOC15_REG_GOLDEN_VALUE(GC, 0, regCGTT_GS_NGG_CLK_CTRL, 0x9fff8fff, 0x00000010),
@@ -304,6 +308,10 @@ static void gfx_v11_0_init_golden_registers(struct amdgpu_device *adev) · 209 unmodified lines
304308 default:
305309 break;
306310 }
311+ soc15_program_register_sequence(adev,
312+ golden_settings_gc_11_0,
313+ (const u32)ARRAY_SIZE(golden_settings_gc_11_0));
314+
307315 }
308316
309317 static void gfx_v11_0_write_data_to_reg(struct amdgpu_ring *ring, int eng_sel,
@@ -419,7 +427,7 @@ static int gfx_v11_0_ring_test_ib(struct amdgpu_ring *ring, long timeout) · 109 unmodified lines
419427 adev->wb.wb[index] = cpu_to_le32(0xCAFEDEAD);
420428 cpu_ptr = &adev->wb.wb[index];
421429
422− r = amdgpu_ib_get(adev, NULL, 16, AMDGPU_IB_POOL_DIRECT, &ib);
430+ r = amdgpu_ib_get(adev, NULL, 20, AMDGPU_IB_POOL_DIRECT, &ib);
423431 if (r) {
424432 DRM_ERROR("amdgpu: failed to get ib (%ld).\n", r);
425433 goto err1;
drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c+2−2
@@ -883,8 +883,8 @@ static int gfx_v8_0_ring_test_ib(struct amdgpu_ring *ring, long timeout) · 882 unmodified lines
883883 gpu_addr = adev->wb.gpu_addr + (index * 4);
884884 adev->wb.wb[index] = cpu_to_le32(0xCAFEDEAD);
885885 memset(&ib, 0, sizeof(ib));
886− r = amdgpu_ib_get(adev, NULL, 16,
887− AMDGPU_IB_POOL_DIRECT, &ib);
886+
887+ r = amdgpu_ib_get(adev, NULL, 20, AMDGPU_IB_POOL_DIRECT, &ib);
888888 if (r)
889889 goto err1;
890890
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c+2−2
@@ -1039,8 +1039,8 @@ static int gfx_v9_0_ring_test_ib(struct amdgpu_ring *ring, long timeout) · 1038 unmodified lines
10391039 gpu_addr = adev->wb.gpu_addr + (index * 4);
10401040 adev->wb.wb[index] = cpu_to_le32(0xCAFEDEAD);
10411041 memset(&ib, 0, sizeof(ib));
1042− r = amdgpu_ib_get(adev, NULL, 16,
1043− AMDGPU_IB_POOL_DIRECT, &ib);
1042+
1043+ r = amdgpu_ib_get(adev, NULL, 20, AMDGPU_IB_POOL_DIRECT, &ib);
10441044 if (r)
10451045 goto err1;
10461046
drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c+2−2
@@ -297,8 +297,8 @@ static int gfx_v9_4_3_ring_test_ib(struct amdgpu_ring *ring, long timeout) · 296 unmodified lines
297297 gpu_addr = adev->wb.gpu_addr + (index * 4);
298298 adev->wb.wb[index] = cpu_to_le32(0xCAFEDEAD);
299299 memset(&ib, 0, sizeof(ib));
300− r = amdgpu_ib_get(adev, NULL, 16,
301− AMDGPU_IB_POOL_DIRECT, &ib);
300+
301+ r = amdgpu_ib_get(adev, NULL, 20, AMDGPU_IB_POOL_DIRECT, &ib);
302302 if (r)
303303 goto err1;
304304
drivers/gpu/drm/amd/amdgpu/nbio_v7_11.c+9−9
@@ -259,17 +259,17 @@ const struct nbio_hdp_flush_reg nbio_v7_11_hdp_flush_reg = { · 258 unmodified lines
259259
260260 static void nbio_v7_11_init_registers(struct amdgpu_device *adev)
261261 {
262−/* uint32_t def, data;
262+ uint32_t def, data;
263+
264+ def = data = RREG32_SOC15(NBIO, 0, regBIF_BIF256_CI256_RC3X4_USB4_PCIE_MST_CTRL_3);
265+ data = REG_SET_FIELD(data, BIF_BIF256_CI256_RC3X4_USB4_PCIE_MST_CTRL_3,
266+ CI_SWUS_MAX_READ_REQUEST_SIZE_MODE, 1);
267+ data = REG_SET_FIELD(data, BIF_BIF256_CI256_RC3X4_USB4_PCIE_MST_CTRL_3,
268+ CI_SWUS_MAX_READ_REQUEST_SIZE_PRIV, 1);
263269
264− def = data = RREG32_SOC15(NBIO, 0, regBIF_BIF256_CI256_RC3X4_USB4_PCIE_MST_CTRL_3);
265− data = REG_SET_FIELD(data, BIF_BIF256_CI256_RC3X4_USB4_PCIE_MST_CTRL_3,
266− CI_SWUS_MAX_READ_REQUEST_SIZE_MODE, 1);
267− data = REG_SET_FIELD(data, BIF_BIF256_CI256_RC3X4_USB4_PCIE_MST_CTRL_3,
268− CI_SWUS_MAX_READ_REQUEST_SIZE_PRIV, 1);
270+ if (def != data)
271+ WREG32_SOC15(NBIO, 0, regBIF_BIF256_CI256_RC3X4_USB4_PCIE_MST_CTRL_3, data);
269272
270− if (def != data)
271− WREG32_SOC15(NBIO, 0, regBIF_BIF256_CI256_RC3X4_USB4_PCIE_MST_CTRL_3, data);
272−*/
273273 }
274274
275275 static void nbio_v7_11_update_medium_grain_clock_gating(struct amdgpu_device *adev,
drivers/gpu/drm/amd/amdgpu/nbio_v7_9.c+0−5
@@ -611,11 +611,6 @@ static void nbio_v7_9_handle_ras_controller_intr_no_bifring(struct amdgpu_device · 610 unmodified lines
611611
612612 dev_info(adev->dev, "RAS controller interrupt triggered "
613613 "by NBIF error\n");
614−
615− /* ras_controller_int is dedicated for nbif ras error,
616− * not the global interrupt for sync flood
617− */
618− amdgpu_ras_reset_gpu(adev);
619614 }
620615
621616 amdgpu_ras_error_data_fini(&err_data);
drivers/gpu/drm/amd/amdgpu/soc15.c+5−0
@@ -1161,6 +1161,11 @@ static int soc15_common_early_init(void *handle) · 1160 unmodified lines
11611161 AMD_PG_SUPPORT_VCN_DPG |
11621162 AMD_PG_SUPPORT_JPEG;
11631163 adev->external_rev_id = adev->rev_id + 0x46;
1164+ /* GC 9.4.3 uses MMIO register region hole at a different offset */
1165+ if (!amdgpu_sriov_vf(adev)) {
1166+ adev->rmmio_remap.reg_offset = 0x1A000;
1167+ adev->rmmio_remap.bus_addr = adev->rmmio_base + 0x1A000;
1168+ }
11641169 break;
11651170 default:
11661171 /* FIXME: not supported yet */
drivers/gpu/drm/amd/amdkfd/kfd_priv.h+1−1
@@ -1128,7 +1128,7 @@ static inline struct kfd_node *kfd_node_by_irq_ids(struct amdgpu_device *adev, · 1127 unmodified lines
11281128 struct kfd_dev *dev = adev->kfd.dev;
11291129 uint32_t i;
11301130
1131− if (adev->ip_versions[GC_HWIP][0] != IP_VERSION(9, 4, 3))
1131+ if (KFD_GC_VERSION(dev) != IP_VERSION(9, 4, 3))
11321132 return dev->nodes[0];
11331133
11341134 for (i = 0; i < dev->num_nodes; i++)
drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c+33−21
@@ -169,16 +169,43 @@ int pqm_init(struct process_queue_manager *pqm, struct kfd_process *p) · 168 unmodified lines
169169 return 0;
170170 }
171171
172+static void pqm_clean_queue_resource(struct process_queue_manager *pqm,
173+ struct process_queue_node *pqn)
174+{
175+ struct kfd_node *dev;
176+ struct kfd_process_device *pdd;
177+
178+ dev = pqn->q->device;
179+
180+ pdd = kfd_get_process_device_data(dev, pqm->process);
181+ if (!pdd) {
182+ pr_err("Process device data doesn't exist\n");
183+ return;
184+ }
185+
186+ if (pqn->q->gws) {
187+ if (KFD_GC_VERSION(pqn->q->device) != IP_VERSION(9, 4, 3) &&
188+ !dev->kfd->shared_resources.enable_mes)
189+ amdgpu_amdkfd_remove_gws_from_process(
190+ pqm->process->kgd_process_info, pqn->q->gws);
191+ pdd->qpd.num_gws = 0;
192+ }
193+
194+ if (dev->kfd->shared_resources.enable_mes) {
195+ amdgpu_amdkfd_free_gtt_mem(dev->adev, pqn->q->gang_ctx_bo);
196+ if (pqn->q->wptr_bo)
197+ amdgpu_amdkfd_free_gtt_mem(dev->adev, pqn->q->wptr_bo);
198+ }
199+}
200+
172201 void pqm_uninit(struct process_queue_manager *pqm)
173202 {
174203 struct process_queue_node *pqn, *next;
175204
176205 list_for_each_entry_safe(pqn, next, &pqm->queues, process_queue_list) {
177− if (pqn->q && pqn->q->gws &&
178− KFD_GC_VERSION(pqn->q->device) != IP_VERSION(9, 4, 3) &&
179− !pqn->q->device->kfd->shared_resources.enable_mes)
180− amdgpu_amdkfd_remove_gws_from_process(pqm->process->kgd_process_info,
181− pqn->q->gws);
206+ if (pqn->q)
207+ pqm_clean_queue_resource(pqm, pqn);
208+
182209 kfd_procfs_del_queue(pqn->q);
183210 uninit_queue(pqn->q);
184211 list_del(&pqn->process_queue_list);
@@ -461,22 +488,7 @@ int pqm_destroy_queue(struct process_queue_manager *pqm, unsigned int qid) · 276 unmodified lines
461488 goto err_destroy_queue;
462489 }
463490
464− if (pqn->q->gws) {
465− if (KFD_GC_VERSION(pqn->q->device) != IP_VERSION(9, 4, 3) &&
466− !dev->kfd->shared_resources.enable_mes)
467− amdgpu_amdkfd_remove_gws_from_process(
468− pqm->process->kgd_process_info,
469− pqn->q->gws);
470− pdd->qpd.num_gws = 0;
471− }
472−
473− if (dev->kfd->shared_resources.enable_mes) {
474− amdgpu_amdkfd_free_gtt_mem(dev->adev,
475− pqn->q->gang_ctx_bo);
476− if (pqn->q->wptr_bo)
477− amdgpu_amdkfd_free_gtt_mem(dev->adev, pqn->q->wptr_bo);
478−
479− }
491+ pqm_clean_queue_resource(pqm, pqn);
480492 uninit_queue(pqn->q);
481493 }
482494
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c+5−3
@@ -6267,7 +6267,7 @@ int amdgpu_dm_connector_atomic_set_property(struct drm_connector *connector, · 6266 unmodified lines
62676267 dm_new_state->underscan_enable = val;
62686268 ret = 0;
62696269 } else if (property == adev->mode_info.abm_level_property) {
6270− dm_new_state->abm_level = val;
6270+ dm_new_state->abm_level = val ?: ABM_LEVEL_IMMEDIATE_DISABLE;
62716271 ret = 0;
62726272 }
62736273
@@ -6312,7 +6312,8 @@ int amdgpu_dm_connector_atomic_get_property(struct drm_connector *connector, · 38 unmodified lines
63126312 *val = dm_state->underscan_enable;
63136313 ret = 0;
63146314 } else if (property == adev->mode_info.abm_level_property) {
6315− *val = dm_state->abm_level;
6315+ *val = (dm_state->abm_level != ABM_LEVEL_IMMEDIATE_DISABLE) ?
6316+ dm_state->abm_level : 0;
63166317 ret = 0;
63176318 }
63186319
@@ -6385,7 +6386,8 @@ void amdgpu_dm_connector_funcs_reset(struct drm_connector *connector) · 66 unmodified lines
63856386 state->pbn = 0;
63866387
63876388 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
6388− state->abm_level = amdgpu_dm_abm_level;
6389+ state->abm_level = amdgpu_dm_abm_level ?:
6390+ ABM_LEVEL_IMMEDIATE_DISABLE;
63896391
63906392 __drm_atomic_helper_connector_reset(connector, &state->base);
63916393 }
drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c+4−4
@@ -334,7 +334,7 @@ static struct wm_table lpddr5_wm_table = { · 333 unmodified lines
334334 {
335335 .wm_inst = WM_A,
336336 .wm_type = WM_TYPE_PSTATE_CHG,
337− .pstate_latency_us = 11.65333,
337+ .pstate_latency_us = 129.0,
338338 .sr_exit_time_us = 11.5,
339339 .sr_enter_plus_exit_time_us = 14.5,
340340 .valid = true,
@@ -342,7 +342,7 @@ static struct wm_table lpddr5_wm_table = { · 1 unmodified line
342342 {
343343 .wm_inst = WM_B,
344344 .wm_type = WM_TYPE_PSTATE_CHG,
345− .pstate_latency_us = 11.65333,
345+ .pstate_latency_us = 129.0,
346346 .sr_exit_time_us = 11.5,
347347 .sr_enter_plus_exit_time_us = 14.5,
348348 .valid = true,
@@ -350,7 +350,7 @@ static struct wm_table lpddr5_wm_table = { · 1 unmodified line
350350 {
351351 .wm_inst = WM_C,
352352 .wm_type = WM_TYPE_PSTATE_CHG,
353− .pstate_latency_us = 11.65333,
353+ .pstate_latency_us = 129.0,
354354 .sr_exit_time_us = 11.5,
355355 .sr_enter_plus_exit_time_us = 14.5,
356356 .valid = true,
@@ -358,7 +358,7 @@ static struct wm_table lpddr5_wm_table = { · 1 unmodified line
358358 {
359359 .wm_inst = WM_D,
360360 .wm_type = WM_TYPE_PSTATE_CHG,
361− .pstate_latency_us = 11.65333,
361+ .pstate_latency_us = 129.0,
362362 .sr_exit_time_us = 11.5,
363363 .sr_enter_plus_exit_time_us = 14.5,
364364 .valid = true,
drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c+79−80
@@ -232,6 +232,10 @@ void dcn35_update_clocks(struct clk_mgr *clk_mgr_base, · 231 unmodified lines
232232 if (dc->work_arounds.skip_clock_update)
233233 return;
234234
235+ /* DTBCLK is fixed, so set a default if unspecified. */
236+ if (new_clocks->dtbclk_en && !new_clocks->ref_dtbclk_khz)
237+ new_clocks->ref_dtbclk_khz = 600000;
238+
235239 /*
236240 * if it is safe to lower, but we are already in the lower state, we don't have to do anything
237241 * also if safe to lower is false, we just go in the higher state
@@ -265,8 +269,10 @@ void dcn35_update_clocks(struct clk_mgr *clk_mgr_base, · 27 unmodified lines
265269
266270 if (!clk_mgr_base->clks.dtbclk_en && new_clocks->dtbclk_en) {
267271 dcn35_smu_set_dtbclk(clk_mgr, true);
268− dcn35_update_clocks_update_dtb_dto(clk_mgr, context, clk_mgr_base->clks.ref_dtbclk_khz);
269272 clk_mgr_base->clks.dtbclk_en = new_clocks->dtbclk_en;
273+
274+ dcn35_update_clocks_update_dtb_dto(clk_mgr, context, new_clocks->ref_dtbclk_khz);
275+ clk_mgr_base->clks.ref_dtbclk_khz = new_clocks->ref_dtbclk_khz;
270276 }
271277
272278 /* check that we're not already in D0 */
@@ -314,17 +320,12 @@ void dcn35_update_clocks(struct clk_mgr *clk_mgr_base, · 41 unmodified lines
314320 update_dispclk = true;
315321 }
316322
317− if (!new_clocks->dtbclk_en) {
318− new_clocks->ref_dtbclk_khz = 600000;
319− }
320−
321323 /* clock limits are received with MHz precision, divide by 1000 to prevent setting clocks at every call */
322324 if (!dc->debug.disable_dtb_ref_clk_switch &&
323− should_set_clock(safe_to_lower, new_clocks->ref_dtbclk_khz / 1000, clk_mgr_base->clks.ref_dtbclk_khz / 1000)) {
324− /* DCCG requires KHz precision for DTBCLK */
325− dcn35_smu_set_dtbclk(clk_mgr, true);
326−
327− dcn35_update_clocks_update_dtb_dto(clk_mgr, context, clk_mgr_base->clks.ref_dtbclk_khz);
325+ should_set_clock(safe_to_lower, new_clocks->ref_dtbclk_khz / 1000,
326+ clk_mgr_base->clks.ref_dtbclk_khz / 1000)) {
327+ dcn35_update_clocks_update_dtb_dto(clk_mgr, context, new_clocks->ref_dtbclk_khz);
328+ clk_mgr_base->clks.ref_dtbclk_khz = new_clocks->ref_dtbclk_khz;
328329 }
329330
330331 if (dpp_clock_lowered) {
@@ -443,32 +444,32 @@ static struct wm_table ddr5_wm_table = { · 112 unmodified lines
443444 .wm_inst = WM_A,
444445 .wm_type = WM_TYPE_PSTATE_CHG,
445446 .pstate_latency_us = 11.72,
446− .sr_exit_time_us = 9,
447− .sr_enter_plus_exit_time_us = 11,
447+ .sr_exit_time_us = 14.0,
448+ .sr_enter_plus_exit_time_us = 16.0,
448449 .valid = true,
449450 },
450451 {
451452 .wm_inst = WM_B,
452453 .wm_type = WM_TYPE_PSTATE_CHG,
453454 .pstate_latency_us = 11.72,
454− .sr_exit_time_us = 9,
455− .sr_enter_plus_exit_time_us = 11,
455+ .sr_exit_time_us = 14.0,
456+ .sr_enter_plus_exit_time_us = 16.0,
456457 .valid = true,
457458 },
458459 {
459460 .wm_inst = WM_C,
460461 .wm_type = WM_TYPE_PSTATE_CHG,
461462 .pstate_latency_us = 11.72,
462− .sr_exit_time_us = 9,
463− .sr_enter_plus_exit_time_us = 11,
463+ .sr_exit_time_us = 14.0,
464+ .sr_enter_plus_exit_time_us = 16.0,
464465 .valid = true,
465466 },
466467 {
467468 .wm_inst = WM_D,
468469 .wm_type = WM_TYPE_PSTATE_CHG,
469470 .pstate_latency_us = 11.72,
470− .sr_exit_time_us = 9,
471− .sr_enter_plus_exit_time_us = 11,
471+ .sr_exit_time_us = 14.0,
472+ .sr_enter_plus_exit_time_us = 16.0,
472473 .valid = true,
473474 },
474475 }
@@ -480,32 +481,32 @@ static struct wm_table lpddr5_wm_table = { · 5 unmodified lines
480481 .wm_inst = WM_A,
481482 .wm_type = WM_TYPE_PSTATE_CHG,
482483 .pstate_latency_us = 11.65333,
483− .sr_exit_time_us = 11.5,
484− .sr_enter_plus_exit_time_us = 14.5,
484+ .sr_exit_time_us = 14.0,
485+ .sr_enter_plus_exit_time_us = 16.0,
485486 .valid = true,
486487 },
487488 {
488489 .wm_inst = WM_B,
489490 .wm_type = WM_TYPE_PSTATE_CHG,
490491 .pstate_latency_us = 11.65333,
491− .sr_exit_time_us = 11.5,
492− .sr_enter_plus_exit_time_us = 14.5,
492+ .sr_exit_time_us = 14.0,
493+ .sr_enter_plus_exit_time_us = 16.0,
493494 .valid = true,
494495 },
495496 {
496497 .wm_inst = WM_C,
497498 .wm_type = WM_TYPE_PSTATE_CHG,
498499 .pstate_latency_us = 11.65333,
499− .sr_exit_time_us = 11.5,
500− .sr_enter_plus_exit_time_us = 14.5,
500+ .sr_exit_time_us = 14.0,
501+ .sr_enter_plus_exit_time_us = 16.0,
501502 .valid = true,
502503 },
503504 {
504505 .wm_inst = WM_D,
505506 .wm_type = WM_TYPE_PSTATE_CHG,
506507 .pstate_latency_us = 11.65333,
507− .sr_exit_time_us = 11.5,
508− .sr_enter_plus_exit_time_us = 14.5,
508+ .sr_exit_time_us = 14.0,
509+ .sr_enter_plus_exit_time_us = 16.0,
509510 .valid = true,
510511 },
511512 }
@@ -515,11 +516,6 @@ static DpmClocks_t_dcn35 dummy_clocks; · 3 unmodified lines
515516
516517 static struct dcn35_watermarks dummy_wms = { 0 };
517518
518−static struct dcn35_ss_info_table ss_info_table = {
519− .ss_divider = 1000,
520− .ss_percentage = {0, 0, 375, 375, 375}
521−};
522−
523519 static void dcn35_build_watermark_ranges(struct clk_bw_params *bw_params, struct dcn35_watermarks *table)
524520 {
525521 int i, num_valid_sets;
@@ -653,27 +649,47 @@ static unsigned int convert_wck_ratio(uint8_t wck_ratio) · 127 unmodified lines
653649 return 1;
654650 }
655651
652+static inline uint32_t calc_dram_speed_mts(const MemPstateTable_t *entry)
653+{
654+ return entry->UClk * convert_wck_ratio(entry->WckRatio) * 2;
655+}
656+
656657 static void dcn35_clk_mgr_helper_populate_bw_params(struct clk_mgr_internal *clk_mgr,
657658 struct integrated_info *bios_info,
658659 DpmClocks_t_dcn35 *clock_table)
659660 {
660661 struct clk_bw_params *bw_params = clk_mgr->base.bw_params;
661662 struct clk_limit_table_entry def_max = bw_params->clk_table.entries[bw_params->clk_table.num_entries - 1];
662− uint32_t max_pstate = 0, max_uclk = 0, max_fclk = 0;
663− uint32_t min_pstate = 0, max_dispclk = 0, max_dppclk = 0;
663+ uint32_t max_fclk = 0, min_pstate = 0, max_dispclk = 0, max_dppclk = 0;
664+ uint32_t max_pstate = 0, max_dram_speed_mts = 0, min_dram_speed_mts = 0;
664665 int i;
665666
667+ /* Determine min/max p-state values. */
666668 for (i = 0; i < clock_table->NumMemPstatesEnabled; i++) {
667− if (is_valid_clock_value(clock_table->MemPstateTable[i].UClk) &&
668− clock_table->MemPstateTable[i].UClk > max_uclk) {
669− max_uclk = clock_table->MemPstateTable[i].UClk;
669+ uint32_t dram_speed_mts = calc_dram_speed_mts(&clock_table->MemPstateTable[i]);
670+
671+ if (is_valid_clock_value(dram_speed_mts) && dram_speed_mts > max_dram_speed_mts) {
672+ max_dram_speed_mts = dram_speed_mts;
670673 max_pstate = i;
671674 }
672675 }
673676
674− /* We expect the table to contain at least one valid Uclk entry. */
675− ASSERT(is_valid_clock_value(max_uclk));
677+ min_dram_speed_mts = max_dram_speed_mts;
678+ min_pstate = max_pstate;
679+
680+ for (i = 0; i < clock_table->NumMemPstatesEnabled; i++) {
681+ uint32_t dram_speed_mts = calc_dram_speed_mts(&clock_table->MemPstateTable[i]);
682+
683+ if (is_valid_clock_value(dram_speed_mts) && dram_speed_mts < min_dram_speed_mts) {
684+ min_dram_speed_mts = dram_speed_mts;
685+ min_pstate = i;
686+ }
687+ }
676688
689+ /* We expect the table to contain at least one valid P-state entry. */
690+ ASSERT(clock_table->NumMemPstatesEnabled &&
691+ is_valid_clock_value(max_dram_speed_mts) &&
692+ is_valid_clock_value(min_dram_speed_mts));
677693
678694 /* dispclk and dppclk can be max at any voltage, same number of levels for both */
679695 if (clock_table->NumDispClkLevelsEnabled <= NUM_DISPCLK_DPM_LEVELS &&
@@ -683,47 +699,46 @@ static void dcn35_clk_mgr_helper_populate_bw_params(struct clk_mgr_internal *clk · 3 unmodified lines
683699 max_dppclk = find_max_clk_value(clock_table->DppClocks,
684700 clock_table->NumDispClkLevelsEnabled);
685701 } else {
702+ /* Invalid number of entries in the table from PMFW. */
686703 ASSERT(0);
687704 }
688− if (clock_table->NumFclkLevelsEnabled <= NUM_FCLK_DPM_LEVELS)
689− max_fclk = find_max_clk_value(clock_table->FclkClocks_Freq,
690− clock_table->NumFclkLevelsEnabled);
691705
692− for (i = 0; i < clock_table->NumMemPstatesEnabled; i++) {
693− uint32_t min_uclk = clock_table->MemPstateTable[0].UClk;
694− int j;
706+ /* Base the clock table on dcfclk, need at least one entry regardless of pmfw table */
707+ ASSERT(clock_table->NumDcfClkLevelsEnabled > 0);
695708
696− for (j = 1; j < clock_table->NumMemPstatesEnabled; j++) {
697− if (is_valid_clock_value(clock_table->MemPstateTable[j].UClk) &&
698− clock_table->MemPstateTable[j].UClk < min_uclk &&
699− clock_table->MemPstateTable[j].Voltage <= clock_table->SocVoltage[i]) {
700− min_uclk = clock_table->MemPstateTable[j].UClk;
701− min_pstate = j;
702− }
703− }
709+ max_fclk = find_max_clk_value(clock_table->FclkClocks_Freq, clock_table->NumFclkLevelsEnabled);
704710
711+ for (i = 0; i < clock_table->NumDcfClkLevelsEnabled; i++) {
712+ int j;
713+
714+ /* First search defaults for the clocks we don't read using closest lower or equal default dcfclk */
705715 for (j = bw_params->clk_table.num_entries - 1; j > 0; j--)
706716 if (bw_params->clk_table.entries[j].dcfclk_mhz <= clock_table->DcfClocks[i])
707− break;
717+ break;
708718
709719 bw_params->clk_table.entries[i].phyclk_mhz = bw_params->clk_table.entries[j].phyclk_mhz;
710720 bw_params->clk_table.entries[i].phyclk_d18_mhz = bw_params->clk_table.entries[j].phyclk_d18_mhz;
711721 bw_params->clk_table.entries[i].dtbclk_mhz = bw_params->clk_table.entries[j].dtbclk_mhz;
712− bw_params->clk_table.entries[i].fclk_mhz = max_fclk;
722+
723+ /* Now update clocks we do read */
713724 bw_params->clk_table.entries[i].memclk_mhz = clock_table->MemPstateTable[min_pstate].MemClk;
714725 bw_params->clk_table.entries[i].voltage = clock_table->MemPstateTable[min_pstate].Voltage;
715726 bw_params->clk_table.entries[i].dcfclk_mhz = clock_table->DcfClocks[i];
716727 bw_params->clk_table.entries[i].socclk_mhz = clock_table->SocClocks[i];
717728 bw_params->clk_table.entries[i].dispclk_mhz = max_dispclk;
718729 bw_params->clk_table.entries[i].dppclk_mhz = max_dppclk;
719− bw_params->clk_table.entries[i].wck_ratio = convert_wck_ratio(
720− clock_table->MemPstateTable[min_pstate].WckRatio);
721− }
730+ bw_params->clk_table.entries[i].wck_ratio =
731+ convert_wck_ratio(clock_table->MemPstateTable[min_pstate].WckRatio);
732+
733+ /* Dcfclk and Fclk are tied, but at a different ratio */
734+ bw_params->clk_table.entries[i].fclk_mhz = min(max_fclk, 2 * clock_table->DcfClocks[i]);
735+ }
722736
723737 /* Make sure to include at least one entry at highest pstate */
724738 if (max_pstate != min_pstate || i == 0) {
725739 if (i > MAX_NUM_DPM_LVL - 1)
726740 i = MAX_NUM_DPM_LVL - 1;
741+
727742 bw_params->clk_table.entries[i].fclk_mhz = max_fclk;
728743 bw_params->clk_table.entries[i].memclk_mhz = clock_table->MemPstateTable[max_pstate].MemClk;
729744 bw_params->clk_table.entries[i].voltage = clock_table->MemPstateTable[max_pstate].Voltage;
@@ -739,6 +754,7 @@ static void dcn35_clk_mgr_helper_populate_bw_params(struct clk_mgr_internal *clk · 9 unmodified lines
739754 }
740755 bw_params->clk_table.num_entries = i--;
741756
757+ /* Make sure all highest clocks are included*/
742758 bw_params->clk_table.entries[i].socclk_mhz =
743759 find_max_clk_value(clock_table->SocClocks, NUM_SOCCLK_DPM_LEVELS);
744760 bw_params->clk_table.entries[i].dispclk_mhz =
@@ -757,6 +773,11 @@ static void dcn35_clk_mgr_helper_populate_bw_params(struct clk_mgr_internal *clk · 12 unmodified lines
757773 bw_params->clk_table.num_entries_per_clk.num_fclk_levels = clock_table->NumFclkLevelsEnabled;
758774 bw_params->clk_table.num_entries_per_clk.num_memclk_levels = clock_table->NumMemPstatesEnabled;
759775 bw_params->clk_table.num_entries_per_clk.num_socclk_levels = clock_table->NumSocClkLevelsEnabled;
776+
777+ /*
778+ * Set any 0 clocks to max default setting. Not an issue for
779+ * power since we aren't doing switching in such case anyway
780+ */
760781 for (i = 0; i < bw_params->clk_table.num_entries; i++) {
761782 if (!bw_params->clk_table.entries[i].fclk_mhz) {
762783 bw_params->clk_table.entries[i].fclk_mhz = def_max.fclk_mhz;
@@ -965,21 +986,6 @@ struct clk_mgr_funcs dcn35_fpga_funcs = { · 202 unmodified lines
965986 .get_dtb_ref_clk_frequency = dcn31_get_dtb_ref_freq_khz,
966987 };
967988
968−static void dcn35_read_ss_info_from_lut(struct clk_mgr_internal *clk_mgr)
969−{
970− uint32_t clock_source;
971− struct dc_context *ctx = clk_mgr->base.ctx;
972−
973− REG_GET(CLK1_CLK2_BYPASS_CNTL, CLK2_BYPASS_SEL, &clock_source);
974−
975− clk_mgr->dprefclk_ss_percentage = ss_info_table.ss_percentage[clock_source];
976−
977− if (clk_mgr->dprefclk_ss_percentage != 0) {
978− clk_mgr->ss_on_dprefclk = true;
979− clk_mgr->dprefclk_ss_divider = ss_info_table.ss_divider;
980− }
981−}
982−
983989 void dcn35_clk_mgr_construct(
984990 struct dc_context *ctx,
985991 struct clk_mgr_dcn35 *clk_mgr,
@@ -1043,17 +1049,11 @@ void dcn35_clk_mgr_construct( · 57 unmodified lines
10431049 dcn35_dump_clk_registers(&clk_mgr->base.base.boot_snapshot, &clk_mgr->base.base, &log_info);
10441050
10451051 clk_mgr->base.base.dprefclk_khz = dcn35_smu_get_dprefclk(&clk_mgr->base);
1046− clk_mgr->base.base.clks.ref_dtbclk_khz = dcn35_smu_get_dtbclk(&clk_mgr->base);
1052+ clk_mgr->base.base.clks.ref_dtbclk_khz = 600000;
10471053
1048− if (!clk_mgr->base.base.clks.ref_dtbclk_khz)
1049− dcn35_smu_set_dtbclk(&clk_mgr->base, true);
1050−
1051− clk_mgr->base.base.clks.dtbclk_en = true;
10521054 dce_clock_read_ss_info(&clk_mgr->base);
10531055 /*when clk src is from FCH, it could have ss, same clock src as DPREF clk*/
10541056
1055− dcn35_read_ss_info_from_lut(&clk_mgr->base);
1056−
10571057 clk_mgr->base.base.bw_params = &dcn35_bw_params;
10581058
10591059 if (clk_mgr->base.base.ctx->dc->debug.pstate_enabled) {
@@ -1129,7 +1129,6 @@ void dcn35_clk_mgr_construct( · 69 unmodified lines
11291129 ctx->dc->debug.disable_dpp_power_gate = false;
11301130 ctx->dc->debug.disable_hubp_power_gate = false;
11311131 ctx->dc->debug.disable_dsc_power_gate = false;
1132− ctx->dc->debug.disable_hpo_power_gate = false;
11331132 } else {
11341133 /*let's reset the config control flag*/
11351134 ctx->dc->config.disable_ips = DMUB_IPS_DISABLE_ALL; /*pmfw not support it, disable it all*/
drivers/gpu/drm/amd/display/dc/dc.h+1−1
@@ -874,6 +874,7 @@ struct dc_debug_options { · 873 unmodified lines
874874 unsigned int seamless_boot_odm_combine;
875875 unsigned int force_odm_combine_4to1; //bit vector based on otg inst
876876 int minimum_z8_residency_time;
877+ int minimum_z10_residency_time;
877878 bool disable_z9_mpc;
878879 unsigned int force_fclk_khz;
879880 bool enable_tri_buf;
@@ -1608,7 +1609,6 @@ struct dc_link { · 728 unmodified lines
16081609 enum edp_revision edp_revision;
16091610 union dpcd_sink_ext_caps dpcd_sink_ext_caps;
16101611
1611− struct backlight_settings backlight_settings;
16121612 struct psr_settings psr_settings;
16131613
16141614 struct replay_settings replay_settings;
drivers/gpu/drm/amd/display/dc/dc_types.h+0−4
@@ -991,10 +991,6 @@ struct link_mst_stream_allocation_table { · 990 unmodified lines
991991 struct link_mst_stream_allocation stream_allocations[MAX_CONTROLLER_NUM];
992992 };
993993
994−struct backlight_settings {
995− uint32_t backlight_millinits;
996−};
997−
998994 /* PSR feature flags */
999995 struct psr_settings {
1000996 bool psr_feature_enabled; // PSR is supported by sink
drivers/gpu/drm/amd/display/dc/dcn314/dcn314_resource.c+1−1
@@ -871,7 +871,7 @@ static const struct dc_plane_cap plane_cap = { · 870 unmodified lines
871871 static const struct dc_debug_options debug_defaults_drv = {
872872 .disable_z10 = false,
873873 .enable_z9_disable_interface = true,
874− .minimum_z8_residency_time = 2000,
874+ .minimum_z8_residency_time = 2100,
875875 .psr_skip_crtc_disable = true,
876876 .replay_skip_crtc_disabled = true,
877877 .disable_dmcu = true,
drivers/gpu/drm/amd/display/dc/dcn35/dcn35_pg_cntl.c+10−0
@@ -261,6 +261,7 @@ void pg_cntl35_hpo_pg_control(struct pg_cntl *pg_cntl, bool power_on) · 260 unmodified lines
261261 uint32_t power_gate = power_on ? 0 : 1;
262262 uint32_t pwr_status = power_on ? 0 : 2;
263263 uint32_t org_ip_request_cntl;
264+ uint32_t power_forceon;
264265 bool block_enabled;
265266
266267 if (pg_cntl->ctx->dc->debug.ignore_pg ||
@@ -277,6 +278,10 @@ void pg_cntl35_hpo_pg_control(struct pg_cntl *pg_cntl, bool power_on) · 10 unmodified lines
277278 return;
278279 }
279280
281+ REG_GET(DOMAIN25_PG_CONFIG, DOMAIN_POWER_FORCEON, &power_forceon);
282+ if (power_forceon)
283+ return;
284+
280285 REG_GET(DC_IP_REQUEST_CNTL, IP_REQUEST_EN, &org_ip_request_cntl);
281286 if (org_ip_request_cntl == 0)
282287 REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 1);
@@ -304,6 +309,7 @@ void pg_cntl35_io_clk_pg_control(struct pg_cntl *pg_cntl, bool power_on) · 21 unmodified lines
304309 uint32_t power_gate = power_on ? 0 : 1;
305310 uint32_t pwr_status = power_on ? 0 : 2;
306311 uint32_t org_ip_request_cntl;
312+ uint32_t power_forceon;
307313 bool block_enabled;
308314
309315 if (pg_cntl->ctx->dc->debug.ignore_pg ||
@@ -319,6 +325,10 @@ void pg_cntl35_io_clk_pg_control(struct pg_cntl *pg_cntl, bool power_on) · 9 unmodified lines
319325 return;
320326 }
321327
328+ REG_GET(DOMAIN22_PG_CONFIG, DOMAIN_POWER_FORCEON, &power_forceon);
329+ if (power_forceon)
330+ return;
331+
322332 REG_GET(DC_IP_REQUEST_CNTL, IP_REQUEST_EN, &org_ip_request_cntl);
323333 if (org_ip_request_cntl == 0)
324334 REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 1);
drivers/gpu/drm/amd/display/dc/dcn35/dcn35_resource.c+8−1
@@ -1712,6 +1712,13 @@ static bool dcn35_validate_bandwidth(struct dc *dc, · 1711 unmodified lines
17121712
17131713 out = dml2_validate(dc, context, fast_validate);
17141714
1715+ if (fast_validate)
1716+ return out;
1717+
1718+ DC_FP_START();
1719+ dcn35_decide_zstate_support(dc, context);
1720+ DC_FP_END();
1721+
17151722 return out;
17161723 }
17171724
@@ -1857,7 +1864,7 @@ static bool dcn35_resource_construct( · 139 unmodified lines
18571864
18581865 /* Use pipe context based otg sync logic */
18591866 dc->config.use_pipe_ctx_sync_logic = true;
1860− dc->config.use_default_clock_table = false;
1867+
18611868 /* read VBIOS LTTPR caps */
18621869 {
18631870 if (ctx->dc_bios->funcs->get_lttpr_caps) {
drivers/gpu/drm/amd/display/dc/dml/dc_features.h+1−1
@@ -36,7 +36,7 @@ · 35 unmodified lines
3636 * Define the maximum amount of states supported by the ASIC. Every ASIC has a
3737 * specific number of states; this macro defines the maximum number of states.
3838 */
39−#define DC__VOLTAGE_STATES 20
39+#define DC__VOLTAGE_STATES 40
4040 #define DC__NUM_DPP__4 1
4141 #define DC__NUM_DPP__0_PRESENT 1
4242 #define DC__NUM_DPP__1_PRESENT 1
drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c+1−14
@@ -950,10 +950,8 @@ static enum dcn_zstate_support_state decide_zstate_support(struct dc *dc, struc · 949 unmodified lines
950950 {
951951 int plane_count;
952952 int i;
953− unsigned int min_dst_y_next_start_us;
954953
955954 plane_count = 0;
956− min_dst_y_next_start_us = 0;
957955 for (i = 0; i < dc->res_pool->pipe_count; i++) {
958956 if (context->res_ctx.pipe_ctx[i].plane_state)
959957 plane_count++;
@@ -975,26 +973,15 @@ static enum dcn_zstate_support_state decide_zstate_support(struct dc *dc, struc · 15 unmodified lines
975973 else if (context->stream_count == 1 && context->streams[0]->signal == SIGNAL_TYPE_EDP) {
976974 struct dc_link *link = context->streams[0]->sink->link;
977975 struct dc_stream_status *stream_status = &context->stream_status[0];
978− struct dc_stream_state *current_stream = context->streams[0];
979976 int minmum_z8_residency = dc->debug.minimum_z8_residency_time > 0 ? dc->debug.minimum_z8_residency_time : 1000;
980977 bool allow_z8 = context->bw_ctx.dml.vba.StutterPeriod > (double)minmum_z8_residency;
981978 bool is_pwrseq0 = link->link_index == 0;
982− bool isFreesyncVideo;
983−
984− isFreesyncVideo = current_stream->adjust.v_total_min == current_stream->adjust.v_total_max;
985− isFreesyncVideo = isFreesyncVideo && current_stream->timing.v_total < current_stream->adjust.v_total_min;
986− for (i = 0; i < dc->res_pool->pipe_count; i++) {
987− if (context->res_ctx.pipe_ctx[i].stream == current_stream && isFreesyncVideo) {
988− min_dst_y_next_start_us = context->res_ctx.pipe_ctx[i].dlg_regs.min_dst_y_next_start_us;
989− break;
990− }
991− }
992979
993980 /* Don't support multi-plane configurations */
994981 if (stream_status->plane_count > 1)
995982 return DCN_ZSTATE_SUPPORT_DISALLOW;
996983
997− if (is_pwrseq0 && (context->bw_ctx.dml.vba.StutterPeriod > 5000.0 || min_dst_y_next_start_us > 5000))
984+ if (is_pwrseq0 && context->bw_ctx.dml.vba.StutterPeriod > 5000.0)
998985 return DCN_ZSTATE_SUPPORT_ALLOW;
999986 else if (is_pwrseq0 && link->psr_settings.psr_version == DC_PSR_VERSION_1 && !link->panel_config.psr.disable_psr)
1000987 return allow_z8 ? DCN_ZSTATE_SUPPORT_ALLOW_Z8_Z10_ONLY : DCN_ZSTATE_SUPPORT_ALLOW_Z10_ONLY;
drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c+14−9
@@ -1192,13 +1192,16 @@ static bool update_pipe_slice_table_with_split_flags( · 1191 unmodified lines
11921192 */
11931193 struct pipe_ctx *pipe;
11941194 bool odm;
1195− int i;
1195+ int dc_pipe_idx, dml_pipe_idx = 0;
11961196 bool updated = false;
11971197
1198− for (i = 0; i < dc->res_pool->pipe_count; i++) {
1199− pipe = &context->res_ctx.pipe_ctx[i];
1198+ for (dc_pipe_idx = 0;
1199+ dc_pipe_idx < dc->res_pool->pipe_count; dc_pipe_idx++) {
1200+ pipe = &context->res_ctx.pipe_ctx[dc_pipe_idx];
1201+ if (resource_is_pipe_type(pipe, FREE_PIPE))
1202+ continue;
12001203
1201− if (merge[i]) {
1204+ if (merge[dc_pipe_idx]) {
12021205 if (resource_is_pipe_type(pipe, OPP_HEAD))
12031206 /* merging OPP head means reducing ODM slice
12041207 * count by 1
@@ -1213,17 +1216,18 @@ static bool update_pipe_slice_table_with_split_flags( · 8 unmodified lines
12131216 updated = true;
12141217 }
12151218
1216− if (split[i]) {
1217− odm = vba->ODMCombineEnabled[vba->pipe_plane[i]] !=
1219+ if (split[dc_pipe_idx]) {
1220+ odm = vba->ODMCombineEnabled[vba->pipe_plane[dml_pipe_idx]] !=
12181221 dm_odm_combine_mode_disabled;
12191222 if (odm && resource_is_pipe_type(pipe, OPP_HEAD))
12201223 update_slice_table_for_stream(
1221− table, pipe->stream, split[i] - 1);
1224+ table, pipe->stream, split[dc_pipe_idx] - 1);
12221225 else if (!odm && resource_is_pipe_type(pipe, DPP_PIPE))
12231226 update_slice_table_for_plane(table, pipe,
1224− pipe->plane_state, split[i] - 1);
1227+ pipe->plane_state, split[dc_pipe_idx] - 1);
12251228 updated = true;
12261229 }
1230+ dml_pipe_idx++;
12271231 }
12281232 return updated;
12291233 }
@@ -2231,6 +2235,7 @@ void dcn32_calculate_wm_and_dlg_fpu(struct dc *dc, struct dc_state *context, · 1001 unmodified lines
22312235 int i, pipe_idx, vlevel_temp = 0;
22322236 double dcfclk = dcn3_2_soc.clock_limits[0].dcfclk_mhz;
22332237 double dcfclk_from_validation = context->bw_ctx.dml.vba.DCFCLKState[vlevel][context->bw_ctx.dml.vba.maxMpcComb];
2238+ double dram_speed_from_validation = context->bw_ctx.dml.vba.DRAMSpeed;
22342239 double dcfclk_from_fw_based_mclk_switching = dcfclk_from_validation;
22352240 bool pstate_en = context->bw_ctx.dml.vba.DRAMClockChangeSupport[vlevel][context->bw_ctx.dml.vba.maxMpcComb] !=
22362241 dm_dram_clock_change_unsupported;
@@ -2418,7 +2423,7 @@ void dcn32_calculate_wm_and_dlg_fpu(struct dc *dc, struct dc_state *context, · 181 unmodified lines
24182423 }
24192424
24202425 if (dc->clk_mgr->bw_params->wm_table.nv_entries[WM_C].valid) {
2421− min_dram_speed_mts = context->bw_ctx.dml.vba.DRAMSpeed;
2426+ min_dram_speed_mts = dram_speed_from_validation;
24222427 min_dram_speed_mts_margin = 160;
24232428
24242429 context->bw_ctx.dml.soc.dram_clock_change_latency_us =
drivers/gpu/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c+80−4
@@ -164,10 +164,10 @@ struct _vcs_dpi_soc_bounding_box_st dcn3_5_soc = { · 163 unmodified lines
164164 },
165165 },
166166 .num_states = 5,
167− .sr_exit_time_us = 9.0,
168− .sr_enter_plus_exit_time_us = 11.0,
169− .sr_exit_z8_time_us = 50.0, /*changed from 442.0*/
170− .sr_enter_plus_exit_z8_time_us = 50.0,/*changed from 560.0*/
167+ .sr_exit_time_us = 14.0,
168+ .sr_enter_plus_exit_time_us = 16.0,
169+ .sr_exit_z8_time_us = 525.0,
170+ .sr_enter_plus_exit_z8_time_us = 715.0,
171171 .fclk_change_latency_us = 20.0,
172172 .usr_retraining_latency_us = 2,
173173 .writeback_latency_us = 12.0,
@@ -329,6 +329,48 @@ void dcn35_update_bw_bounding_box_fpu(struct dc *dc, · 155 unmodified lines
329329 /*temp till dml2 fully work without dml1*/
330330 dml_init_instance(&dc->dml, &dcn3_5_soc, &dcn3_5_ip,
331331 DML_PROJECT_DCN31);
332+
333+ /*copy to dml2, before dml2_create*/
334+ if (clk_table->num_entries > 2) {
335+
336+ for (i = 0; i < clk_table->num_entries; i++) {
337+ dc->dml2_options.bbox_overrides.clks_table.num_states =
338+ clk_table->num_entries;
339+ dc->dml2_options.bbox_overrides.clks_table.clk_entries[i].dcfclk_mhz =
340+ clock_limits[i].dcfclk_mhz;
341+ dc->dml2_options.bbox_overrides.clks_table.clk_entries[i].fclk_mhz =
342+ clock_limits[i].fabricclk_mhz;
343+ dc->dml2_options.bbox_overrides.clks_table.clk_entries[i].dispclk_mhz =
344+ clock_limits[i].dispclk_mhz;
345+ dc->dml2_options.bbox_overrides.clks_table.clk_entries[i].dppclk_mhz =
346+ clock_limits[i].dppclk_mhz;
347+ dc->dml2_options.bbox_overrides.clks_table.clk_entries[i].socclk_mhz =
348+ clock_limits[i].socclk_mhz;
349+ dc->dml2_options.bbox_overrides.clks_table.clk_entries[i].memclk_mhz =
350+ clk_table->entries[i].memclk_mhz * clk_table->entries[i].wck_ratio;
351+ dc->dml2_options.bbox_overrides.clks_table.num_entries_per_clk.num_dcfclk_levels =
352+ clk_table->num_entries;
353+ dc->dml2_options.bbox_overrides.clks_table.num_entries_per_clk.num_fclk_levels =
354+ clk_table->num_entries;
355+ dc->dml2_options.bbox_overrides.clks_table.num_entries_per_clk.num_dispclk_levels =
356+ clk_table->num_entries;
357+ dc->dml2_options.bbox_overrides.clks_table.num_entries_per_clk.num_dppclk_levels =
358+ clk_table->num_entries;
359+ dc->dml2_options.bbox_overrides.clks_table.num_entries_per_clk.num_socclk_levels =
360+ clk_table->num_entries;
361+ dc->dml2_options.bbox_overrides.clks_table.num_entries_per_clk.num_memclk_levels =
362+ clk_table->num_entries;
363+ }
364+ }
365+
366+ /* Update latency values */
367+ dc->dml2_options.bbox_overrides.dram_clock_change_latency_us = dcn3_5_soc.dram_clock_change_latency_us;
368+
369+ dc->dml2_options.bbox_overrides.sr_exit_latency_us = dcn3_5_soc.sr_exit_time_us;
370+ dc->dml2_options.bbox_overrides.sr_enter_plus_exit_latency_us = dcn3_5_soc.sr_enter_plus_exit_time_us;
371+
372+ dc->dml2_options.bbox_overrides.sr_exit_z8_time_us = dcn3_5_soc.sr_exit_z8_time_us;
373+ dc->dml2_options.bbox_overrides.sr_enter_plus_exit_z8_time_us = dcn3_5_soc.sr_enter_plus_exit_z8_time_us;
332374 }
333375
334376 static bool is_dual_plane(enum surface_pixel_format format)
@@ -507,3 +549,37 @@ int dcn35_populate_dml_pipes_from_context_fpu(struct dc *dc, · 172 unmodified lines
507549
508550 return pipe_cnt;
509551 }
552+
553+void dcn35_decide_zstate_support(struct dc *dc, struct dc_state *context)
554+{
555+ enum dcn_zstate_support_state support = DCN_ZSTATE_SUPPORT_DISALLOW;
556+ unsigned int i, plane_count = 0;
557+
558+ for (i = 0; i < dc->res_pool->pipe_count; i++) {
559+ if (context->res_ctx.pipe_ctx[i].plane_state)
560+ plane_count++;
561+ }
562+
563+ if (plane_count == 0) {
564+ support = DCN_ZSTATE_SUPPORT_ALLOW;
565+ } else if (plane_count == 1 && context->stream_count == 1 && context->streams[0]->signal == SIGNAL_TYPE_EDP) {
566+ struct dc_link *link = context->streams[0]->sink->link;
567+ bool is_pwrseq0 = link && link->link_index == 0;
568+ bool is_psr1 = link && link->psr_settings.psr_version == DC_PSR_VERSION_1 && !link->panel_config.psr.disable_psr;
569+ int minmum_z8_residency =
570+ dc->debug.minimum_z8_residency_time > 0 ? dc->debug.minimum_z8_residency_time : 1000;
571+ bool allow_z8 = context->bw_ctx.dml.vba.StutterPeriod > (double)minmum_z8_residency;
572+ int minmum_z10_residency =
573+ dc->debug.minimum_z10_residency_time > 0 ? dc->debug.minimum_z10_residency_time : 5000;
574+ bool allow_z10 = context->bw_ctx.dml.vba.StutterPeriod > (double)minmum_z10_residency;
575+
576+ if (is_pwrseq0 && allow_z10)
577+ support = DCN_ZSTATE_SUPPORT_ALLOW;
578+ else if (is_pwrseq0 && is_psr1)
579+ support = allow_z8 ? DCN_ZSTATE_SUPPORT_ALLOW_Z8_Z10_ONLY : DCN_ZSTATE_SUPPORT_ALLOW_Z10_ONLY;
580+ else if (allow_z8)
581+ support = DCN_ZSTATE_SUPPORT_ALLOW_Z8_ONLY;
582+ }
583+
584+ context->bw_ctx.bw.dcn.clk.zstate_support = support;
585+}
drivers/gpu/drm/amd/display/dc/dml/dcn35/dcn35_fpu.h+2−0
@@ -39,4 +39,6 @@ int dcn35_populate_dml_pipes_from_context_fpu(struct dc *dc, · 38 unmodified lines
3939 display_e2e_pipe_params_st *pipes,
4040 bool fast_validate);
4141
42+void dcn35_decide_zstate_support(struct dc *dc, struct dc_state *context);
43+
4244 #endif
drivers/gpu/drm/amd/display/dc/dml2/display_mode_core.c+8−8
@@ -6329,7 +6329,7 @@ static void dml_prefetch_check(struct display_mode_lib_st *mode_lib) · 6328 unmodified lines
63296329 mode_lib->ms.NoOfDPPThisState,
63306330 mode_lib->ms.dpte_group_bytes,
63316331 s->HostVMInefficiencyFactor,
6332− mode_lib->ms.soc.hostvm_min_page_size_kbytes,
6332+ mode_lib->ms.soc.hostvm_min_page_size_kbytes * 1024,
63336333 mode_lib->ms.cache_display_cfg.plane.HostVMMaxPageTableLevels);
63346334
63356335 s->NextMaxVStartup = s->MaxVStartupAllPlanes[j];
@@ -6542,7 +6542,7 @@ static void dml_prefetch_check(struct display_mode_lib_st *mode_lib) · 206 unmodified lines
65426542 mode_lib->ms.cache_display_cfg.plane.HostVMEnable,
65436543 mode_lib->ms.cache_display_cfg.plane.HostVMMaxPageTableLevels,
65446544 mode_lib->ms.cache_display_cfg.plane.GPUVMEnable,
6545− mode_lib->ms.soc.hostvm_min_page_size_kbytes,
6545+ mode_lib->ms.soc.hostvm_min_page_size_kbytes * 1024,
65466546 mode_lib->ms.PDEAndMetaPTEBytesPerFrame[j][k],
65476547 mode_lib->ms.MetaRowBytes[j][k],
65486548 mode_lib->ms.DPTEBytesPerRow[j][k],
@@ -7687,7 +7687,7 @@ dml_bool_t dml_core_mode_support(struct display_mode_lib_st *mode_lib) · 1138 unmodified lines
76877687 CalculateVMRowAndSwath_params->HostVMMaxNonCachedPageTableLevels = mode_lib->ms.cache_display_cfg.plane.HostVMMaxPageTableLevels;
76887688 CalculateVMRowAndSwath_params->GPUVMMaxPageTableLevels = mode_lib->ms.cache_display_cfg.plane.GPUVMMaxPageTableLevels;
76897689 CalculateVMRowAndSwath_params->GPUVMMinPageSizeKBytes = mode_lib->ms.cache_display_cfg.plane.GPUVMMinPageSizeKBytes;
7690− CalculateVMRowAndSwath_params->HostVMMinPageSize = mode_lib->ms.soc.hostvm_min_page_size_kbytes;
7690+ CalculateVMRowAndSwath_params->HostVMMinPageSize = mode_lib->ms.soc.hostvm_min_page_size_kbytes * 1024;
76917691 CalculateVMRowAndSwath_params->PTEBufferModeOverrideEn = mode_lib->ms.cache_display_cfg.plane.PTEBufferModeOverrideEn;
76927692 CalculateVMRowAndSwath_params->PTEBufferModeOverrideVal = mode_lib->ms.cache_display_cfg.plane.PTEBufferMode;
76937693 CalculateVMRowAndSwath_params->PTEBufferSizeNotExceeded = mode_lib->ms.PTEBufferSizeNotExceededPerState;
@@ -7957,7 +7957,7 @@ dml_bool_t dml_core_mode_support(struct display_mode_lib_st *mode_lib) · 263 unmodified lines
79577957 UseMinimumDCFCLK_params->GPUVMMaxPageTableLevels = mode_lib->ms.cache_display_cfg.plane.GPUVMMaxPageTableLevels;
79587958 UseMinimumDCFCLK_params->HostVMEnable = mode_lib->ms.cache_display_cfg.plane.HostVMEnable;
79597959 UseMinimumDCFCLK_params->NumberOfActiveSurfaces = mode_lib->ms.num_active_planes;
7960− UseMinimumDCFCLK_params->HostVMMinPageSize = mode_lib->ms.soc.hostvm_min_page_size_kbytes;
7960+ UseMinimumDCFCLK_params->HostVMMinPageSize = mode_lib->ms.soc.hostvm_min_page_size_kbytes * 1024;
79617961 UseMinimumDCFCLK_params->HostVMMaxNonCachedPageTableLevels = mode_lib->ms.cache_display_cfg.plane.HostVMMaxPageTableLevels;
79627962 UseMinimumDCFCLK_params->DynamicMetadataVMEnabled = mode_lib->ms.ip.dynamic_metadata_vm_enabled;
79637963 UseMinimumDCFCLK_params->ImmediateFlipRequirement = s->ImmediateFlipRequiredFinal;
@@ -8699,7 +8699,7 @@ void dml_core_mode_programming(struct display_mode_lib_st *mode_lib, const struc · 735 unmodified lines
86998699 CalculateVMRowAndSwath_params->HostVMMaxNonCachedPageTableLevels = mode_lib->ms.cache_display_cfg.plane.HostVMMaxPageTableLevels;
87008700 CalculateVMRowAndSwath_params->GPUVMMaxPageTableLevels = mode_lib->ms.cache_display_cfg.plane.GPUVMMaxPageTableLevels;
87018701 CalculateVMRowAndSwath_params->GPUVMMinPageSizeKBytes = mode_lib->ms.cache_display_cfg.plane.GPUVMMinPageSizeKBytes;
8702− CalculateVMRowAndSwath_params->HostVMMinPageSize = mode_lib->ms.soc.hostvm_min_page_size_kbytes;
8702+ CalculateVMRowAndSwath_params->HostVMMinPageSize = mode_lib->ms.soc.hostvm_min_page_size_kbytes * 1024;
87038703 CalculateVMRowAndSwath_params->PTEBufferModeOverrideEn = mode_lib->ms.cache_display_cfg.plane.PTEBufferModeOverrideEn;
87048704 CalculateVMRowAndSwath_params->PTEBufferModeOverrideVal = mode_lib->ms.cache_display_cfg.plane.PTEBufferMode;
87058705 CalculateVMRowAndSwath_params->PTEBufferSizeNotExceeded = s->dummy_boolean_array[0];
@@ -8805,7 +8805,7 @@ void dml_core_mode_programming(struct display_mode_lib_st *mode_lib, const struc · 99 unmodified lines
88058805 mode_lib->ms.cache_display_cfg.hw.DPPPerSurface,
88068806 locals->dpte_group_bytes,
88078807 s->HostVMInefficiencyFactor,
8808− mode_lib->ms.soc.hostvm_min_page_size_kbytes,
8808+ mode_lib->ms.soc.hostvm_min_page_size_kbytes * 1024,
88098809 mode_lib->ms.cache_display_cfg.plane.HostVMMaxPageTableLevels);
88108810
88118811 locals->TCalc = 24.0 / locals->DCFCLKDeepSleep;
@@ -8995,7 +8995,7 @@ void dml_core_mode_programming(struct display_mode_lib_st *mode_lib, const struc · 183 unmodified lines
89958995 CalculatePrefetchSchedule_params->GPUVMEnable = mode_lib->ms.cache_display_cfg.plane.GPUVMEnable;
89968996 CalculatePrefetchSchedule_params->HostVMEnable = mode_lib->ms.cache_display_cfg.plane.HostVMEnable;
89978997 CalculatePrefetchSchedule_params->HostVMMaxNonCachedPageTableLevels = mode_lib->ms.cache_display_cfg.plane.HostVMMaxPageTableLevels;
8998− CalculatePrefetchSchedule_params->HostVMMinPageSize = mode_lib->ms.soc.hostvm_min_page_size_kbytes;
8998+ CalculatePrefetchSchedule_params->HostVMMinPageSize = mode_lib->ms.soc.hostvm_min_page_size_kbytes * 1024;
89998999 CalculatePrefetchSchedule_params->DynamicMetadataEnable = mode_lib->ms.cache_display_cfg.plane.DynamicMetadataEnable[k];
90009000 CalculatePrefetchSchedule_params->DynamicMetadataVMEnabled = mode_lib->ms.ip.dynamic_metadata_vm_enabled;
90019001 CalculatePrefetchSchedule_params->DynamicMetadataLinesBeforeActiveRequired = mode_lib->ms.cache_display_cfg.plane.DynamicMetadataLinesBeforeActiveRequired[k];
@@ -9240,7 +9240,7 @@ void dml_core_mode_programming(struct display_mode_lib_st *mode_lib, const struc · 238 unmodified lines
92409240 mode_lib->ms.cache_display_cfg.plane.HostVMEnable,
92419241 mode_lib->ms.cache_display_cfg.plane.HostVMMaxPageTableLevels,
92429242 mode_lib->ms.cache_display_cfg.plane.GPUVMEnable,
9243− mode_lib->ms.soc.hostvm_min_page_size_kbytes,
9243+ mode_lib->ms.soc.hostvm_min_page_size_kbytes * 1024,
92449244 locals->PDEAndMetaPTEBytesFrame[k],
92459245 locals->MetaRowByte[k],
92469246 locals->PixelPTEBytesPerRow[k],
drivers/gpu/drm/amd/display/dc/dml2/dml2_translation_helper.c+40−20
@@ -341,25 +341,42 @@ void dml2_init_soc_states(struct dml2_context *dml2, const struct dc *in_dc, · 340 unmodified lines
341341 break;
342342 }
343343
344− /* Override from passed values, mainly for debugging purposes, if available */
345− if (dml2->config.bbox_overrides.sr_exit_latency_us) {
346− p->in_states->state_array[0].sr_exit_time_us = dml2->config.bbox_overrides.sr_exit_latency_us;
347− }
344+ /* Override from passed values, if available */
345+ for (i = 0; i < p->in_states->num_states; i++) {
346+ if (dml2->config.bbox_overrides.sr_exit_latency_us) {
347+ p->in_states->state_array[i].sr_exit_time_us =
348+ dml2->config.bbox_overrides.sr_exit_latency_us;
349+ }
348350
349− if (dml2->config.bbox_overrides.sr_enter_plus_exit_latency_us) {
350− p->in_states->state_array[0].sr_enter_plus_exit_time_us = dml2->config.bbox_overrides.sr_enter_plus_exit_latency_us;
351− }
351+ if (dml2->config.bbox_overrides.sr_enter_plus_exit_latency_us) {
352+ p->in_states->state_array[i].sr_enter_plus_exit_time_us =
353+ dml2->config.bbox_overrides.sr_enter_plus_exit_latency_us;
354+ }
352355
353− if (dml2->config.bbox_overrides.urgent_latency_us) {
354− p->in_states->state_array[0].urgent_latency_pixel_data_only_us = dml2->config.bbox_overrides.urgent_latency_us;
355− }
356+ if (dml2->config.bbox_overrides.sr_exit_z8_time_us) {
357+ p->in_states->state_array[i].sr_exit_z8_time_us =
358+ dml2->config.bbox_overrides.sr_exit_z8_time_us;
359+ }
356360
357− if (dml2->config.bbox_overrides.dram_clock_change_latency_us) {
358− p->in_states->state_array[0].dram_clock_change_latency_us = dml2->config.bbox_overrides.dram_clock_change_latency_us;
359− }
361+ if (dml2->config.bbox_overrides.sr_enter_plus_exit_z8_time_us) {
362+ p->in_states->state_array[i].sr_enter_plus_exit_z8_time_us =
363+ dml2->config.bbox_overrides.sr_enter_plus_exit_z8_time_us;
364+ }
365+
366+ if (dml2->config.bbox_overrides.urgent_latency_us) {
367+ p->in_states->state_array[i].urgent_latency_pixel_data_only_us =
368+ dml2->config.bbox_overrides.urgent_latency_us;
369+ }
360370
361− if (dml2->config.bbox_overrides.fclk_change_latency_us) {
362− p->in_states->state_array[0].fclk_change_latency_us = dml2->config.bbox_overrides.fclk_change_latency_us;
371+ if (dml2->config.bbox_overrides.dram_clock_change_latency_us) {
372+ p->in_states->state_array[i].dram_clock_change_latency_us =
373+ dml2->config.bbox_overrides.dram_clock_change_latency_us;
374+ }
375+
376+ if (dml2->config.bbox_overrides.fclk_change_latency_us) {
377+ p->in_states->state_array[i].fclk_change_latency_us =
378+ dml2->config.bbox_overrides.fclk_change_latency_us;
379+ }
363380 }
364381
365382 /* DCFCLK stas values are project specific */
@@ -498,8 +515,8 @@ void dml2_translate_socbb_params(const struct dc *in, struct soc_bounding_box_st · 132 unmodified lines
498515 out->do_urgent_latency_adjustment = in_soc_params->do_urgent_latency_adjustment;
499516 out->dram_channel_width_bytes = (dml_uint_t)in_soc_params->dram_channel_width_bytes;
500517 out->fabric_datapath_to_dcn_data_return_bytes = (dml_uint_t)in_soc_params->fabric_datapath_to_dcn_data_return_bytes;
501− out->gpuvm_min_page_size_kbytes = in_soc_params->gpuvm_min_page_size_bytes * 1024;
502− out->hostvm_min_page_size_kbytes = in_soc_params->hostvm_min_page_size_bytes * 1024;
518+ out->gpuvm_min_page_size_kbytes = in_soc_params->gpuvm_min_page_size_bytes / 1024;
519+ out->hostvm_min_page_size_kbytes = in_soc_params->hostvm_min_page_size_bytes / 1024;
503520 out->mall_allocated_for_dcn_mbytes = (dml_uint_t)in_soc_params->mall_allocated_for_dcn_mbytes;
504521 out->max_avg_dram_bw_use_normal_percent = in_soc_params->max_avg_dram_bw_use_normal_percent;
505522 out->max_avg_fabric_bw_use_normal_percent = in_soc_params->max_avg_fabric_bw_use_normal_percent;
@@ -1040,9 +1057,12 @@ void map_dc_state_into_dml_display_cfg(struct dml2_context *dml2, struct dc_stat · 534 unmodified lines
10401057 }
10411058
10421059 //Generally these are set by referencing our latest BB/IP params in dcn32_resource.c file
1043− dml_dispcfg->plane.GPUVMEnable = true;
1044− dml_dispcfg->plane.GPUVMMaxPageTableLevels = 4;
1045− dml_dispcfg->plane.HostVMEnable = false;
1060+ dml_dispcfg->plane.GPUVMEnable = dml2->v20.dml_core_ctx.ip.gpuvm_enable;
1061+ dml_dispcfg->plane.GPUVMMaxPageTableLevels = dml2->v20.dml_core_ctx.ip.gpuvm_max_page_table_levels;
1062+ dml_dispcfg->plane.HostVMEnable = dml2->v20.dml_core_ctx.ip.hostvm_enable;
1063+ dml_dispcfg->plane.HostVMMaxPageTableLevels = dml2->v20.dml_core_ctx.ip.hostvm_max_page_table_levels;
1064+ if (dml2->v20.dml_core_ctx.ip.hostvm_enable)
1065+ dml2->v20.dml_core_ctx.policy.AllowForPStateChangeOrStutterInVBlankFinal = dml_prefetch_support_uclk_fclk_and_stutter;
10461066
10471067 dml2_populate_pipe_to_plane_index_mapping(dml2, context);
10481068
drivers/gpu/drm/amd/display/dc/dml2/dml2_wrapper.h+2−0
@@ -139,6 +139,8 @@ struct dml2_soc_bbox_overrides { · 138 unmodified lines
139139 double urgent_latency_us;
140140 double sr_exit_latency_us;
141141 double sr_enter_plus_exit_latency_us;
142+ double sr_exit_z8_time_us;
143+ double sr_enter_plus_exit_z8_time_us;
142144 double dram_clock_change_latency_us;
143145 double fclk_change_latency_us;
144146 unsigned int dram_num_chan;
drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c+2−4
@@ -487,8 +487,7 @@ bool dcn32_set_mcm_luts( · 486 unmodified lines
487487 if (plane_state->blend_tf->type == TF_TYPE_HWPWL)
488488 lut_params = &plane_state->blend_tf->pwl;
489489 else if (plane_state->blend_tf->type == TF_TYPE_DISTRIBUTED_POINTS) {
490− cm_helper_translate_curve_to_hw_format(plane_state->ctx,
491− plane_state->blend_tf,
490+ cm3_helper_translate_curve_to_hw_format(plane_state->blend_tf,
492491 &dpp_base->regamma_params, false);
493492 lut_params = &dpp_base->regamma_params;
494493 }
@@ -503,8 +502,7 @@ bool dcn32_set_mcm_luts( · 8 unmodified lines
503502 else if (plane_state->in_shaper_func->type == TF_TYPE_DISTRIBUTED_POINTS) {
504503 // TODO: dpp_base replace
505504 ASSERT(false);
506− cm_helper_translate_curve_to_hw_format(plane_state->ctx,
507− plane_state->in_shaper_func,
505+ cm3_helper_translate_curve_to_hw_format(plane_state->in_shaper_func,
508506 &dpp_base->shaper_params, true);
509507 lut_params = &dpp_base->shaper_params;
510508 }
drivers/gpu/drm/amd/display/dc/link/link_detection.c+1−1
@@ -879,7 +879,7 @@ static bool detect_link_and_local_sink(struct dc_link *link, · 878 unmodified lines
879879 (link->dpcd_sink_ext_caps.bits.oled == 1)) {
880880 dpcd_set_source_specific_data(link);
881881 msleep(post_oui_delay);
882− set_cached_brightness_aux(link);
882+ set_default_brightness_aux(link);
883883 }
884884
885885 return true;
drivers/gpu/drm/amd/display/dc/link/link_dpms.c+1−2
@@ -2142,8 +2142,7 @@ static enum dc_status enable_link_dp(struct dc_state *state, · 2141 unmodified lines
21422142 if (link->dpcd_sink_ext_caps.bits.oled == 1 ||
21432143 link->dpcd_sink_ext_caps.bits.sdr_aux_backlight_control == 1 ||
21442144 link->dpcd_sink_ext_caps.bits.hdr_aux_backlight_control == 1) {
2145− set_cached_brightness_aux(link);
2146−
2145+ set_default_brightness_aux(link);
21472146 if (link->dpcd_sink_ext_caps.bits.oled == 1)
21482147 msleep(bl_oled_enable_delay);
21492148 edp_backlight_enable_aux(link, true);
drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_fixed_vs_pe_retimer.c+3−3
@@ -115,7 +115,7 @@ static enum link_training_result perform_fixed_vs_pe_nontransparent_training_seq · 114 unmodified lines
115115 lt_settings->cr_pattern_time = 16000;
116116
117117 /* Fixed VS/PE specific: Toggle link rate */
118− apply_toggle_rate_wa = (link->vendor_specific_lttpr_link_rate_wa == target_rate);
118+ apply_toggle_rate_wa = ((link->vendor_specific_lttpr_link_rate_wa == target_rate) || (link->vendor_specific_lttpr_link_rate_wa == 0));
119119 target_rate = get_dpcd_link_rate(&lt_settings->link_settings);
120120 toggle_rate = (target_rate == 0x6) ? 0xA : 0x6;
121121
@@ -271,7 +271,7 @@ enum link_training_result dp_perform_fixed_vs_pe_training_sequence_legacy( · 149 unmodified lines
271271 /* Vendor specific: Toggle link rate */
272272 toggle_rate = (rate == 0x6) ? 0xA : 0x6;
273273
274− if (link->vendor_specific_lttpr_link_rate_wa == rate) {
274+ if (link->vendor_specific_lttpr_link_rate_wa == rate || link->vendor_specific_lttpr_link_rate_wa == 0) {
275275 core_link_write_dpcd(
276276 link,
277277 DP_LINK_BW_SET,
@@ -617,7 +617,7 @@ enum link_training_result dp_perform_fixed_vs_pe_training_sequence( · 339 unmodified lines
617617 /* Vendor specific: Toggle link rate */
618618 toggle_rate = (rate == 0x6) ? 0xA : 0x6;
619619
620− if (link->vendor_specific_lttpr_link_rate_wa == rate) {
620+ if (link->vendor_specific_lttpr_link_rate_wa == rate || link->vendor_specific_lttpr_link_rate_wa == 0) {
621621 core_link_write_dpcd(
622622 link,
623623 DP_LINK_BW_SET,
drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c+3−13
@@ -170,7 +170,6 @@ bool edp_set_backlight_level_nits(struct dc_link *link, · 169 unmodified lines
170170 *(uint32_t *)&dpcd_backlight_set.backlight_level_millinits = backlight_millinits;
171171 *(uint16_t *)&dpcd_backlight_set.backlight_transition_time_ms = (uint16_t)transition_time_in_ms;
172172
173− link->backlight_settings.backlight_millinits = backlight_millinits;
174173
175174 if (!link->dpcd_caps.panel_luminance_control) {
176175 if (core_link_write_dpcd(link, DP_SOURCE_BACKLIGHT_LEVEL,
@@ -288,9 +287,9 @@ bool set_default_brightness_aux(struct dc_link *link) · 111 unmodified lines
288287 if (link && link->dpcd_sink_ext_caps.bits.oled == 1) {
289288 if (!read_default_bl_aux(link, &default_backlight))
290289 default_backlight = 150000;
291− // if < 1 nits or > 5000, it might be wrong readback
292− if (default_backlight < 1000 || default_backlight > 5000000)
293− default_backlight = 150000; //
290+ // if > 5000, it might be wrong readback
291+ if (default_backlight > 5000000)
292+ default_backlight = 150000;
294293
295294 return edp_set_backlight_level_nits(link, true,
296295 default_backlight, 0);
@@ -298,15 +297,6 @@ bool set_default_brightness_aux(struct dc_link *link) · 1 unmodified line
298297 return false;
299298 }
300299
301−bool set_cached_brightness_aux(struct dc_link *link)
302−{
303− if (link->backlight_settings.backlight_millinits)
304− return edp_set_backlight_level_nits(link, true,
305− link->backlight_settings.backlight_millinits, 0);
306− else
307− return set_default_brightness_aux(link);
308− return false;
309−}
310300 bool edp_is_ilr_optimization_enabled(struct dc_link *link)
311301 {
312302 if (link->dpcd_caps.edp_supported_link_rates_count == 0 || !link->panel_config.ilr.optimize_edp_link_rate)
drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.h+0−1
@@ -30,7 +30,6 @@ · 29 unmodified lines
3030 enum dp_panel_mode dp_get_panel_mode(struct dc_link *link);
3131 void dp_set_panel_mode(struct dc_link *link, enum dp_panel_mode panel_mode);
3232 bool set_default_brightness_aux(struct dc_link *link);
33−bool set_cached_brightness_aux(struct dc_link *link);
3433 void edp_panel_backlight_power_on(struct dc_link *link, bool wait_for_hpd);
3534 int edp_get_backlight_level(const struct dc_link *link);
3635 bool edp_get_backlight_level_nits(struct dc_link *link,
drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c+1−0
@@ -1077,6 +1077,7 @@ enum dmub_status dmub_srv_wait_for_inbox0_ack(struct dmub_srv *dmub, uint32_t ti · 1076 unmodified lines
10771077 ack = dmub->hw_funcs.read_inbox0_ack_register(dmub);
10781078 if (ack)
10791079 return DMUB_STATUS_OK;
1080+ udelay(1);
10801081 }
10811082 return DMUB_STATUS_TIMEOUT;
10821083 }
drivers/gpu/drm/amd/include/asic_reg/gc/gc_11_0_0_offset.h+2−0
@@ -6369,6 +6369,8 @@ · 6368 unmodified lines
63696369 #define regTCP_INVALIDATE_BASE_IDX 1
63706370 #define regTCP_STATUS 0x19a1
63716371 #define regTCP_STATUS_BASE_IDX 1
6372+#define regTCP_CNTL 0x19a2
6373+#define regTCP_CNTL_BASE_IDX 1
63726374 #define regTCP_CNTL2 0x19a3
63736375 #define regTCP_CNTL2_BASE_IDX 1
63746376 #define regTCP_DEBUG_INDEX 0x19a5
drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_7_11_0_offset.h+2−0
@@ -781,6 +781,8 @@ · 780 unmodified lines
781781 #define regBIF_BIF256_CI256_RC3X4_USB4_PCIE_CNTL2_BASE_IDX 5
782782 #define regBIF_BIF256_CI256_RC3X4_USB4_PCIE_TX_POWER_CTRL_1 0x420187
783783 #define regBIF_BIF256_CI256_RC3X4_USB4_PCIE_TX_POWER_CTRL_1_BASE_IDX 5
784+#define regBIF_BIF256_CI256_RC3X4_USB4_PCIE_MST_CTRL_3 0x4201c6
785+#define regBIF_BIF256_CI256_RC3X4_USB4_PCIE_MST_CTRL_3_BASE_IDX 5
784786
785787
786788 // addressBlock: nbio_nbif0_bif_cfg_dev0_rc_bifcfgdecp
drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_7_11_0_sh_mask.h+29−0
@@ -24646,6 +24646,35 @@ · 24645 unmodified lines
2464624646 //BIF_BIF256_CI256_RC3X4_USB4_PCIE_TX_POWER_CTRL_1
2464724647 #define BIF_BIF256_CI256_RC3X4_USB4_PCIE_TX_POWER_CTRL_1__MST_MEM_LS_EN_MASK 0x00000001L
2464824648 #define BIF_BIF256_CI256_RC3X4_USB4_PCIE_TX_POWER_CTRL_1__REPLAY_MEM_LS_EN_MASK 0x00000008L
24649+//BIF_BIF256_CI256_RC3X4_USB4_PCIE_MST_CTRL_3
24650+#define BIF_BIF256_CI256_RC3X4_USB4_PCIE_MST_CTRL_3__CI_SWUS_MAX_PAYLOAD_SIZE_MODE__SHIFT 0x8
24651+#define BIF_BIF256_CI256_RC3X4_USB4_PCIE_MST_CTRL_3__CI_SWUS_PRIV_MAX_PAYLOAD_SIZE__SHIFT 0x9
24652+#define BIF_BIF256_CI256_RC3X4_USB4_PCIE_MST_CTRL_3__CI_10BIT_TAG_EN_OVERRIDE__SHIFT 0xb
24653+#define BIF_BIF256_CI256_RC3X4_USB4_PCIE_MST_CTRL_3__CI_SWUS_10BIT_TAG_EN_OVERRIDE__SHIFT 0xd
24654+#define BIF_BIF256_CI256_RC3X4_USB4_PCIE_MST_CTRL_3__MST_DROP_SYNC_FLOOD_EN__SHIFT 0xf
24655+#define BIF_BIF256_CI256_RC3X4_USB4_PCIE_MST_CTRL_3__CI_MAX_PAYLOAD_SIZE_MODE__SHIFT 0x10
24656+#define BIF_BIF256_CI256_RC3X4_USB4_PCIE_MST_CTRL_3__CI_PRIV_MAX_PAYLOAD_SIZE__SHIFT 0x11
24657+#define BIF_BIF256_CI256_RC3X4_USB4_PCIE_MST_CTRL_3__CI_MAX_READ_REQUEST_SIZE_MODE__SHIFT 0x14
24658+#define BIF_BIF256_CI256_RC3X4_USB4_PCIE_MST_CTRL_3__CI_PRIV_MAX_READ_REQUEST_SIZE__SHIFT 0x15
24659+#define BIF_BIF256_CI256_RC3X4_USB4_PCIE_MST_CTRL_3__CI_MAX_READ_SAFE_MODE__SHIFT 0x18
24660+#define BIF_BIF256_CI256_RC3X4_USB4_PCIE_MST_CTRL_3__CI_EXTENDED_TAG_EN_OVERRIDE__SHIFT 0x19
24661+#define BIF_BIF256_CI256_RC3X4_USB4_PCIE_MST_CTRL_3__CI_SWUS_MAX_READ_REQUEST_SIZE_MODE__SHIFT 0x1b
24662+#define BIF_BIF256_CI256_RC3X4_USB4_PCIE_MST_CTRL_3__CI_SWUS_MAX_READ_REQUEST_SIZE_PRIV__SHIFT 0x1c
24663+#define BIF_BIF256_CI256_RC3X4_USB4_PCIE_MST_CTRL_3__CI_SWUS_EXTENDED_TAG_EN_OVERRIDE__SHIFT 0x1e
24664+#define BIF_BIF256_CI256_RC3X4_USB4_PCIE_MST_CTRL_3__CI_SWUS_MAX_PAYLOAD_SIZE_MODE_MASK 0x00000100L
24665+#define BIF_BIF256_CI256_RC3X4_USB4_PCIE_MST_CTRL_3__CI_SWUS_PRIV_MAX_PAYLOAD_SIZE_MASK 0x00000600L
24666+#define BIF_BIF256_CI256_RC3X4_USB4_PCIE_MST_CTRL_3__CI_10BIT_TAG_EN_OVERRIDE_MASK 0x00001800L
24667+#define BIF_BIF256_CI256_RC3X4_USB4_PCIE_MST_CTRL_3__CI_SWUS_10BIT_TAG_EN_OVERRIDE_MASK 0x00006000L
24668+#define BIF_BIF256_CI256_RC3X4_USB4_PCIE_MST_CTRL_3__MST_DROP_SYNC_FLOOD_EN_MASK 0x00008000L
24669+#define BIF_BIF256_CI256_RC3X4_USB4_PCIE_MST_CTRL_3__CI_MAX_PAYLOAD_SIZE_MODE_MASK 0x00010000L
24670+#define BIF_BIF256_CI256_RC3X4_USB4_PCIE_MST_CTRL_3__CI_PRIV_MAX_PAYLOAD_SIZE_MASK 0x000E0000L
24671+#define BIF_BIF256_CI256_RC3X4_USB4_PCIE_MST_CTRL_3__CI_MAX_READ_REQUEST_SIZE_MODE_MASK 0x00100000L
24672+#define BIF_BIF256_CI256_RC3X4_USB4_PCIE_MST_CTRL_3__CI_PRIV_MAX_READ_REQUEST_SIZE_MASK 0x00E00000L
24673+#define BIF_BIF256_CI256_RC3X4_USB4_PCIE_MST_CTRL_3__CI_MAX_READ_SAFE_MODE_MASK 0x01000000L
24674+#define BIF_BIF256_CI256_RC3X4_USB4_PCIE_MST_CTRL_3__CI_EXTENDED_TAG_EN_OVERRIDE_MASK 0x06000000L
24675+#define BIF_BIF256_CI256_RC3X4_USB4_PCIE_MST_CTRL_3__CI_SWUS_MAX_READ_REQUEST_SIZE_MODE_MASK 0x08000000L
24676+#define BIF_BIF256_CI256_RC3X4_USB4_PCIE_MST_CTRL_3__CI_SWUS_MAX_READ_REQUEST_SIZE_PRIV_MASK 0x30000000L
24677+#define BIF_BIF256_CI256_RC3X4_USB4_PCIE_MST_CTRL_3__CI_SWUS_EXTENDED_TAG_EN_OVERRIDE_MASK 0xC0000000L
2464924678
2465024679 // addressBlock: nbio_nbif0_bif_cfg_dev0_rc_bifcfgdecp
2465124680 //BIF_CFG_DEV0_RC0_VENDOR_ID
drivers/gpu/drm/amd/include/kgd_pp_interface.h+1−0
@@ -444,6 +444,7 @@ struct amd_pm_funcs { · 443 unmodified lines
444444 struct dpm_clocks *clock_table);
445445 int (*get_smu_prv_buf_details)(void *handle, void **addr, size_t *size);
446446 void (*pm_compute_clocks)(void *handle);
447+ int (*notify_rlc_state)(void *handle, bool en);
447448 };
448449
449450 struct metrics_table_header {
drivers/gpu/drm/amd/pm/amdgpu_dpm.c+18−0
@@ -181,6 +181,24 @@ int amdgpu_dpm_set_mp1_state(struct amdgpu_device *adev, · 180 unmodified lines
181181 return ret;
182182 }
183183
184+int amdgpu_dpm_notify_rlc_state(struct amdgpu_device *adev, bool en)
185+{
186+ int ret = 0;
187+ const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;
188+
189+ if (pp_funcs && pp_funcs->notify_rlc_state) {
190+ mutex_lock(&adev->pm.mutex);
191+
192+ ret = pp_funcs->notify_rlc_state(
193+ adev->powerplay.pp_handle,
194+ en);
195+
196+ mutex_unlock(&adev->pm.mutex);
197+ }
198+
199+ return ret;
200+}
201+
184202 bool amdgpu_dpm_is_baco_supported(struct amdgpu_device *adev)
185203 {
186204 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;
drivers/gpu/drm/amd/pm/inc/amdgpu_dpm.h+2−0
@@ -415,6 +415,8 @@ int amdgpu_dpm_mode1_reset(struct amdgpu_device *adev); · 414 unmodified lines
415415 int amdgpu_dpm_set_mp1_state(struct amdgpu_device *adev,
416416 enum pp_mp1_state mp1_state);
417417
418+int amdgpu_dpm_notify_rlc_state(struct amdgpu_device *adev, bool en);
419+
418420 int amdgpu_dpm_set_gfx_power_up_by_imu(struct amdgpu_device *adev);
419421
420422 int amdgpu_dpm_baco_exit(struct amdgpu_device *adev);
drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c+10−0
@@ -1710,6 +1710,16 @@ static int smu_disable_dpms(struct smu_context *smu) · 1709 unmodified lines
17101710 }
17111711 }
17121712
1713+ /* Notify SMU RLC is going to be off, stop RLC and SMU interaction.
1714+ * otherwise SMU will hang while interacting with RLC if RLC is halted
1715+ * this is a WA for Vangogh asic which fix the SMU hang issue.
1716+ */
1717+ ret = smu_notify_rlc_state(smu, false);
1718+ if (ret) {
1719+ dev_err(adev->dev, "Fail to notify rlc status!\n");
1720+ return ret;
1721+ }
1722+
17131723 if (amdgpu_ip_version(adev, GC_HWIP, 0) >= IP_VERSION(9, 4, 2) &&
17141724 !((adev->flags & AMD_IS_APU) && adev->gfx.imu.funcs) &&
17151725 !amdgpu_sriov_vf(adev) && adev->gfx.rlc.funcs->stop)
drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h+5−0
@@ -1360,6 +1360,11 @@ struct pptable_funcs { · 1359 unmodified lines
13601360 * management.
13611361 */
13621362 int (*dpm_set_umsch_mm_enable)(struct smu_context *smu, bool enable);
1363+
1364+ /**
1365+ * @notify_rlc_state: Notify RLC power state to SMU.
1366+ */
1367+ int (*notify_rlc_state)(struct smu_context *smu, bool en);
13631368 };
13641369
13651370 typedef enum {
drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c+2−3
@@ -2193,8 +2193,7 @@ static int vangogh_get_dpm_clock_table(struct smu_context *smu, struct dpm_clock · 2192 unmodified lines
21932193 return 0;
21942194 }
21952195
2196−
2197−static int vangogh_system_features_control(struct smu_context *smu, bool en)
2196+static int vangogh_notify_rlc_state(struct smu_context *smu, bool en)
21982197 {
21992198 struct amdgpu_device *adev = smu->adev;
22002199 int ret = 0;
@@ -2523,7 +2522,7 @@ static const struct pptable_funcs vangogh_ppt_funcs = { · 322 unmodified lines
25232522 .print_clk_levels = vangogh_common_print_clk_levels,
25242523 .set_default_dpm_table = vangogh_set_default_dpm_tables,
25252524 .set_fine_grain_gfx_freq_parameters = vangogh_set_fine_grain_gfx_freq_parameters,
2526− .system_features_control = vangogh_system_features_control,
2525+ .notify_rlc_state = vangogh_notify_rlc_state,
25272526 .feature_is_enabled = smu_cmn_feature_is_enabled,
25282527 .set_power_profile_mode = vangogh_set_power_profile_mode,
25292528 .get_power_profile_mode = vangogh_get_power_profile_mode,
drivers/gpu/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c+4−1
@@ -257,8 +257,11 @@ static int aldebaran_tables_init(struct smu_context *smu) · 256 unmodified lines
257257 }
258258
259259 smu_table->ecc_table = kzalloc(tables[SMU_TABLE_ECCINFO].size, GFP_KERNEL);
260− if (!smu_table->ecc_table)
260+ if (!smu_table->ecc_table) {
261+ kfree(smu_table->metrics_table);
262+ kfree(smu_table->gpu_metrics_table);
261263 return -ENOMEM;
264+ }
262265
263266 return 0;
264267 }
drivers/gpu/drm/amd/pm/swsmu/smu_internal.h+1−0
@@ -97,6 +97,7 @@ · 96 unmodified lines
9797 #define smu_get_default_config_table_settings(smu, config_table) smu_ppt_funcs(get_default_config_table_settings, -EOPNOTSUPP, smu, config_table)
9898 #define smu_set_config_table(smu, config_table) smu_ppt_funcs(set_config_table, -EOPNOTSUPP, smu, config_table)
9999 #define smu_init_pptable_microcode(smu) smu_ppt_funcs(init_pptable_microcode, 0, smu)
100+#define smu_notify_rlc_state(smu, en) smu_ppt_funcs(notify_rlc_state, 0, smu, en)
100101
101102 #endif
102103 #endif
drivers/gpu/drm/bridge/panel.c+0−17
@@ -4,8 +4,6 @@ · 3 unmodified lines
44 * Copyright (C) 2017 Broadcom
55 */
66
7−#include <linux/device.h>
8−
97 #include <drm/drm_atomic_helper.h>
108 #include <drm/drm_bridge.h>
119 #include <drm/drm_connector.h>
@@ -21,7 +19,6 @@ struct panel_bridge { · 9 unmodified lines
2119 struct drm_bridge bridge;
2220 struct drm_connector connector;
2321 struct drm_panel *panel;
24− struct device_link *link;
2522 u32 connector_type;
2623 };
2724
@@ -63,24 +60,13 @@ static int panel_bridge_attach(struct drm_bridge *bridge, · 35 unmodified lines
6360 {
6461 struct panel_bridge *panel_bridge = drm_bridge_to_panel_bridge(bridge);
6562 struct drm_connector *connector = &panel_bridge->connector;
66− struct drm_panel *panel = panel_bridge->panel;
67− struct drm_device *drm_dev = bridge->dev;
6863 int ret;
6964
70− panel_bridge->link = device_link_add(drm_dev->dev, panel->dev,
71− DL_FLAG_STATELESS);
72− if (!panel_bridge->link) {
73− DRM_ERROR("Failed to add device link between %s and %s\n",
74− dev_name(drm_dev->dev), dev_name(panel->dev));
75− return -EINVAL;
76− }
77−
7865 if (flags & DRM_BRIDGE_ATTACH_NO_CONNECTOR)
7966 return 0;
8067
8168 if (!bridge->encoder) {
8269 DRM_ERROR("Missing encoder\n");
83− device_link_del(panel_bridge->link);
8470 return -ENODEV;
8571 }
8672
@@ -92,7 +78,6 @@ static int panel_bridge_attach(struct drm_bridge *bridge, · 5 unmodified lines
9278 panel_bridge->connector_type);
9379 if (ret) {
9480 DRM_ERROR("Failed to initialize connector\n");
95− device_link_del(panel_bridge->link);
9681 return ret;
9782 }
9883
@@ -115,8 +100,6 @@ static void panel_bridge_detach(struct drm_bridge *bridge) · 16 unmodified lines
115100 struct panel_bridge *panel_bridge = drm_bridge_to_panel_bridge(bridge);
116101 struct drm_connector *connector = &panel_bridge->connector;
117102
118− device_link_del(panel_bridge->link);
119−
120103 /*
121104 * Cleanup the connector if we know it was initialized.
122105 *
drivers/gpu/drm/drm_gpuvm.c+1−1
@@ -1,4 +1,4 @@
1−// SPDX-License-Identifier: GPL-2.0 OR MIT
1+// SPDX-License-Identifier: GPL-2.0-only OR MIT
22 /*
33 * Copyright (c) 2022 Red Hat.
44 *
drivers/gpu/drm/drm_prime.c+18−15
@@ -278,7 +278,7 @@ void drm_gem_dmabuf_release(struct dma_buf *dma_buf) · 277 unmodified lines
278278 }
279279 EXPORT_SYMBOL(drm_gem_dmabuf_release);
280280
281−/*
281+/**
282282 * drm_gem_prime_fd_to_handle - PRIME import function for GEM drivers
283283 * @dev: drm_device to import into
284284 * @file_priv: drm file-private structure
@@ -292,9 +292,9 @@ EXPORT_SYMBOL(drm_gem_dmabuf_release); · 7 unmodified lines
292292 *
293293 * Returns 0 on success or a negative error code on failure.
294294 */
295−static int drm_gem_prime_fd_to_handle(struct drm_device *dev,
296− struct drm_file *file_priv, int prime_fd,
297− uint32_t *handle)
295+int drm_gem_prime_fd_to_handle(struct drm_device *dev,
296+ struct drm_file *file_priv, int prime_fd,
297+ uint32_t *handle)
298298 {
299299 struct dma_buf *dma_buf;
300300 struct drm_gem_object *obj;
@@ -360,6 +360,7 @@ out_put: · 59 unmodified lines
360360 dma_buf_put(dma_buf);
361361 return ret;
362362 }
363+EXPORT_SYMBOL(drm_gem_prime_fd_to_handle);
363364
364365 int drm_prime_fd_to_handle_ioctl(struct drm_device *dev, void *data,
365366 struct drm_file *file_priv)
@@ -408,7 +409,7 @@ static struct dma_buf *export_and_register_object(struct drm_device *dev, · 42 unmodified lines
408409 return dmabuf;
409410 }
410411
411−/*
412+/**
412413 * drm_gem_prime_handle_to_fd - PRIME export function for GEM drivers
413414 * @dev: dev to export the buffer from
414415 * @file_priv: drm file-private structure
@@ -421,10 +422,10 @@ static struct dma_buf *export_and_register_object(struct drm_device *dev, · 6 unmodified lines
421422 * The actual exporting from GEM object to a dma-buf is done through the
422423 * &drm_gem_object_funcs.export callback.
423424 */
424−static int drm_gem_prime_handle_to_fd(struct drm_device *dev,
425− struct drm_file *file_priv, uint32_t handle,
426− uint32_t flags,
427− int *prime_fd)
425+int drm_gem_prime_handle_to_fd(struct drm_device *dev,
426+ struct drm_file *file_priv, uint32_t handle,
427+ uint32_t flags,
428+ int *prime_fd)
428429 {
429430 struct drm_gem_object *obj;
430431 int ret = 0;
@@ -506,6 +507,7 @@ out_unlock: · 75 unmodified lines
506507
507508 return ret;
508509 }
510+EXPORT_SYMBOL(drm_gem_prime_handle_to_fd);
509511
510512 int drm_prime_handle_to_fd_ioctl(struct drm_device *dev, void *data,
511513 struct drm_file *file_priv)
@@ -864,9 +866,9 @@ EXPORT_SYMBOL(drm_prime_get_contiguous_size); · 352 unmodified lines
864866 * @obj: GEM object to export
865867 * @flags: flags like DRM_CLOEXEC and DRM_RDWR
866868 *
867− * This is the implementation of the &drm_gem_object_funcs.export functions
868− * for GEM drivers using the PRIME helpers. It is used as the default for
869− * drivers that do not set their own.
869+ * This is the implementation of the &drm_gem_object_funcs.export functions for GEM drivers
870+ * using the PRIME helpers. It is used as the default in
871+ * drm_gem_prime_handle_to_fd().
870872 */
871873 struct dma_buf *drm_gem_prime_export(struct drm_gem_object *obj,
872874 int flags)
@@ -962,9 +964,10 @@ EXPORT_SYMBOL(drm_gem_prime_import_dev); · 89 unmodified lines
962964 * @dev: drm_device to import into
963965 * @dma_buf: dma-buf object to import
964966 *
965− * This is the implementation of the gem_prime_import functions for GEM
966− * drivers using the PRIME helpers. It is the default for drivers that do
967− * not set their own &drm_driver.gem_prime_import.
967+ * This is the implementation of the gem_prime_import functions for GEM drivers
968+ * using the PRIME helpers. Drivers can use this as their
969+ * &drm_driver.gem_prime_import implementation. It is used as the default
970+ * implementation in drm_gem_prime_fd_to_handle().
968971 *
969972 * Drivers must arrange to call drm_prime_gem_destroy() from their
970973 * &drm_gem_object_funcs.free hook when using this function.
drivers/gpu/drm/i915/display/intel_display.c+2−1
@@ -6853,10 +6853,11 @@ static void intel_commit_modeset_disables(struct intel_atomic_state *state) · 6852 unmodified lines
68536853 if (!intel_crtc_needs_modeset(new_crtc_state))
68546854 continue;
68556855
6856+ intel_pre_plane_update(state, crtc);
6857+
68566858 if (!old_crtc_state->hw.active)
68576859 continue;
68586860
6859− intel_pre_plane_update(state, crtc);
68606861 intel_crtc_disable_planes(state, crtc);
68616862 }
68626863
drivers/gpu/drm/i915/display/intel_dp.c+22−6
@@ -6037,8 +6037,7 @@ static bool intel_edp_init_connector(struct intel_dp *intel_dp, · 6036 unmodified lines
60376037 * (eg. Acer Chromebook C710), so we'll check it only if multiple
60386038 * ports are attempting to use the same AUX CH, according to VBT.
60396039 */
6040− if (intel_bios_dp_has_shared_aux_ch(encoder->devdata) &&
6041− !intel_digital_port_connected(encoder)) {
6040+ if (intel_bios_dp_has_shared_aux_ch(encoder->devdata)) {
60426041 /*
60436042 * If this fails, presume the DPCD answer came
60446043 * from some other port using the same AUX CH.
@@ -6046,10 +6045,27 @@ static bool intel_edp_init_connector(struct intel_dp *intel_dp, · 1 unmodified line
60466045 * FIXME maybe cleaner to check this before the
60476046 * DPCD read? Would need sort out the VDD handling...
60486047 */
6049− drm_info(&dev_priv->drm,
6050− "[ENCODER:%d:%s] HPD is down, disabling eDP\n",
6051− encoder->base.base.id, encoder->base.name);
6052− goto out_vdd_off;
6048+ if (!intel_digital_port_connected(encoder)) {
6049+ drm_info(&dev_priv->drm,
6050+ "[ENCODER:%d:%s] HPD is down, disabling eDP\n",
6051+ encoder->base.base.id, encoder->base.name);
6052+ goto out_vdd_off;
6053+ }
6054+
6055+ /*
6056+ * Unfortunately even the HPD based detection fails on
6057+ * eg. Asus B360M-A (CFL+CNP), so as a last resort fall
6058+ * back to checking for a VGA branch device. Only do this
6059+ * on known affected platforms to minimize false positives.
6060+ */
6061+ if (DISPLAY_VER(dev_priv) == 9 && drm_dp_is_branch(intel_dp->dpcd) &&
6062+ (intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_TYPE_MASK) ==
6063+ DP_DWN_STRM_PORT_TYPE_ANALOG) {
6064+ drm_info(&dev_priv->drm,
6065+ "[ENCODER:%d:%s] VGA converter detected, disabling eDP\n",
6066+ encoder->base.base.id, encoder->base.name);
6067+ goto out_vdd_off;
6068+ }
60536069 }
60546070
60556071 mutex_lock(&dev_priv->drm.mode_config.mutex);
drivers/gpu/drm/i915/gt/intel_engine_user.c+22−17
@@ -41,12 +41,15 @@ void intel_engine_add_user(struct intel_engine_cs *engine) · 40 unmodified lines
4141 llist_add(&engine->uabi_llist, &engine->i915->uabi_engines_llist);
4242 }
4343
44−static const u8 uabi_classes[] = {
44+#define I915_NO_UABI_CLASS ((u16)(-1))
45+
46+static const u16 uabi_classes[] = {
4547 [RENDER_CLASS] = I915_ENGINE_CLASS_RENDER,
4648 [COPY_ENGINE_CLASS] = I915_ENGINE_CLASS_COPY,
4749 [VIDEO_DECODE_CLASS] = I915_ENGINE_CLASS_VIDEO,
4850 [VIDEO_ENHANCEMENT_CLASS] = I915_ENGINE_CLASS_VIDEO_ENHANCE,
4951 [COMPUTE_CLASS] = I915_ENGINE_CLASS_COMPUTE,
52+ [OTHER_CLASS] = I915_NO_UABI_CLASS, /* Not exposed to users, no uabi class. */
5053 };
5154
5255 static int engine_cmp(void *priv, const struct list_head *A,
@@ -200,6 +203,7 @@ static void engine_rename(struct intel_engine_cs *engine, const char *name, u16 · 147 unmodified lines
200203
201204 void intel_engines_driver_register(struct drm_i915_private *i915)
202205 {
206+ u16 name_instance, other_instance = 0;
203207 struct legacy_ring ring = {};
204208 struct list_head *it, *next;
205209 struct rb_node **p, *prev;
@@ -216,27 +220,28 @@ void intel_engines_driver_register(struct drm_i915_private *i915) · 10 unmodified lines
216220 if (intel_gt_has_unrecoverable_error(engine->gt))
217221 continue; /* ignore incomplete engines */
218222
219− /*
220− * We don't want to expose the GSC engine to the users, but we
221− * still rename it so it is easier to identify in the debug logs
222− */
223− if (engine->id == GSC0) {
224− engine_rename(engine, "gsc", 0);
225− continue;
226− }
227−
228223 GEM_BUG_ON(engine->class >= ARRAY_SIZE(uabi_classes));
229224 engine->uabi_class = uabi_classes[engine->class];
225+ if (engine->uabi_class == I915_NO_UABI_CLASS) {
226+ name_instance = other_instance++;
227+ } else {
228+ GEM_BUG_ON(engine->uabi_class >=
229+ ARRAY_SIZE(i915->engine_uabi_class_count));
230+ name_instance =
231+ i915->engine_uabi_class_count[engine->uabi_class]++;
232+ }
233+ engine->uabi_instance = name_instance;
230234
231− GEM_BUG_ON(engine->uabi_class >=
232− ARRAY_SIZE(i915->engine_uabi_class_count));
233− engine->uabi_instance =
234− i915->engine_uabi_class_count[engine->uabi_class]++;
235−
236− /* Replace the internal name with the final user facing name */
235+ /*
236+ * Replace the internal name with the final user and log facing
237+ * name.
238+ */
237239 engine_rename(engine,
238240 intel_engine_class_repr(engine->class),
239− engine->uabi_instance);
241+ name_instance);
242+
243+ if (engine->uabi_class == I915_NO_UABI_CLASS)
244+ continue;
240245
241246 rb_link_node(&engine->uabi_node, prev, p);
242247 rb_insert_color(&engine->uabi_node, &i915->uabi_engines);
drivers/gpu/drm/nouveau/include/nvrm/535.113.01/nvidia/generated/g_os_nvoc.h+1−1
@@ -38,7 +38,7 @@ typedef struct PACKED_REGISTRY_TABLE · 37 unmodified lines
3838 {
3939 NvU32 size;
4040 NvU32 numEntries;
41− PACKED_REGISTRY_ENTRY entries[0];
41+ PACKED_REGISTRY_ENTRY entries[] __counted_by(numEntries);
4242 } PACKED_REGISTRY_TABLE;
4343
4444 #endif
drivers/gpu/drm/nouveau/nouveau_bo.c+3−2
@@ -318,8 +318,9 @@ nouveau_bo_alloc(struct nouveau_cli *cli, u64 *size, int *align, u32 domain, · 317 unmodified lines
318318 (!vmm->page[i].host || vmm->page[i].shift > PAGE_SHIFT))
319319 continue;
320320
321− if (pi < 0)
322− pi = i;
321+ /* pick the last one as it will be smallest. */
322+ pi = i;
323+
323324 /* Stop once the buffer is larger than the current page size. */
324325 if (*size >= 1ULL << vmm->page[i].shift)
325326 break;
drivers/gpu/drm/nouveau/nvkm/subdev/gsp/r535.c+2−4
@@ -365,10 +365,8 @@ r535_gsp_rpc_send(struct nvkm_gsp *gsp, void *argv, bool wait, u32 repc) · 364 unmodified lines
365365 }
366366
367367 ret = r535_gsp_cmdq_push(gsp, rpc);
368− if (ret) {
369− mutex_unlock(&gsp->cmdq.mutex);
368+ if (ret)
370369 return ERR_PTR(ret);
371− }
372370
373371 if (wait) {
374372 msg = r535_gsp_msg_recv(gsp, fn, repc);
@@ -1048,7 +1046,7 @@ r535_gsp_rpc_set_registry(struct nvkm_gsp *gsp) · 673 unmodified lines
10481046 char *strings;
10491047 int str_offset;
10501048 int i;
1051− size_t rpc_size = sizeof(*rpc) + sizeof(rpc->entries[0]) * NV_GSP_REG_NUM_ENTRIES;
1049+ size_t rpc_size = struct_size(rpc, entries, NV_GSP_REG_NUM_ENTRIES);
10521050
10531051 /* add strings + null terminator */
10541052 for (i = 0; i < NV_GSP_REG_NUM_ENTRIES; i++)
drivers/gpu/drm/panel/panel-boe-tv101wum-nl6.c+1−0
@@ -1764,6 +1764,7 @@ static const struct panel_desc starry_qfh032011_53g_desc = { · 1763 unmodified lines
17641764 .mode_flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_SYNC_PULSE |
17651765 MIPI_DSI_MODE_LPM,
17661766 .init_cmds = starry_qfh032011_53g_init_cmd,
1767+ .lp11_before_reset = true,
17671768 };
17681769
17691770 static const struct drm_display_mode starry_himax83102_j02_default_mode = {
drivers/gpu/drm/panel/panel-novatek-nt36523.c+2−2
@@ -1254,9 +1254,9 @@ static int nt36523_probe(struct mipi_dsi_device *dsi) · 1253 unmodified lines
12541254 return dev_err_probe(dev, -EPROBE_DEFER, "cannot get secondary DSI host\n");
12551255
12561256 pinfo->dsi[1] = mipi_dsi_device_register_full(dsi1_host, info);
1257− if (!pinfo->dsi[1]) {
1257+ if (IS_ERR(pinfo->dsi[1])) {
12581258 dev_err(dev, "cannot get secondary DSI device\n");
1259− return -ENODEV;
1259+ return PTR_ERR(pinfo->dsi[1]);
12601260 }
12611261 }
12621262
include/drm/drm_gpuvm.h+1−1
@@ -1,4 +1,4 @@
1−/* SPDX-License-Identifier: GPL-2.0 OR MIT */
1+/* SPDX-License-Identifier: GPL-2.0-only OR MIT */
22
33 #ifndef __DRM_GPUVM_H__
44 #define __DRM_GPUVM_H__
include/drm/drm_prime.h+7−0
@@ -60,12 +60,19 @@ enum dma_data_direction; · 59 unmodified lines
6060
6161 struct drm_device;
6262 struct drm_gem_object;
63+struct drm_file;
6364
6465 /* core prime functions */
6566 struct dma_buf *drm_gem_dmabuf_export(struct drm_device *dev,
6667 struct dma_buf_export_info *exp_info);
6768 void drm_gem_dmabuf_release(struct dma_buf *dma_buf);
6869
70+int drm_gem_prime_fd_to_handle(struct drm_device *dev,
71+ struct drm_file *file_priv, int prime_fd, uint32_t *handle);
72+int drm_gem_prime_handle_to_fd(struct drm_device *dev,
73+ struct drm_file *file_priv, uint32_t handle, uint32_t flags,
74+ int *prime_fd);
75+
6976 /* helper functions for exporting */
7077 int drm_gem_map_attach(struct dma_buf *dma_buf,
7178 struct dma_buf_attachment *attach);
include/linux/dma-fence.h+15−0
@@ -498,6 +498,21 @@ static inline bool dma_fence_is_later(struct dma_fence *f1, · 497 unmodified lines
498498 return __dma_fence_is_later(f1->seqno, f2->seqno, f1->ops);
499499 }
500500
501+/**
502+ * dma_fence_is_later_or_same - return true if f1 is later or same as f2
503+ * @f1: the first fence from the same context
504+ * @f2: the second fence from the same context
505+ *
506+ * Returns true if f1 is chronologically later than f2 or the same fence. Both
507+ * fences must be from the same context, since a seqno is not re-used across
508+ * contexts.
509+ */
510+static inline bool dma_fence_is_later_or_same(struct dma_fence *f1,
511+ struct dma_fence *f2)
512+{
513+ return f1 == f2 || dma_fence_is_later(f1, f2);
514+}
515+
501516 /**
502517 * dma_fence_later - return the chronologically later fence
503518 * @f1: the first fence from the same context