Pull MIPS fixes from Ralf Baechle: - MIPS didn't define the new ioremap_uc. Defined it as an alias for ioremap_uncached. - Replace workaround for MIPS16 build issue with a correct one. * git://git.linux-mips.org/pub/scm/ralf/upstream-linus: MIPS: Define ioremap_uc MIPS: UAPI: Ignore __arch_swab{16,32,64} when using MIPS16 Revert "MIPS: UAPI: Fix unrecognized opcode WSBH/DSBH/DSHD when using MIPS16."
Unified · Split
| @@ -256,6 +256,7 @@ static inline void __iomem * __ioremap_mode(phys_addr_t offset, unsigned long si · 255 unmodified lines | ||
| 256 | 256 | */ |
| 257 | 257 | #define ioremap_nocache(offset, size) \ |
| 258 | 258 | __ioremap_mode((offset), (size), _CACHE_UNCACHED) |
| 259 | +#define ioremap_uc ioremap_nocache | |
| 259 | 260 | |
| 260 | 261 | /* |
| 261 | 262 | * ioremap_cachable - map bus memory into CPU space |
| @@ -13,16 +13,15 @@ · 12 unmodified lines | ||
| 13 | 13 | |
| 14 | 14 | #define __SWAB_64_THRU_32__ |
| 15 | 15 | |
| 16 | −#if (defined(__mips_isa_rev) && (__mips_isa_rev >= 2)) || \ | |
| 17 | − defined(_MIPS_ARCH_LOONGSON3A) | |
| 16 | +#if !defined(__mips16) && \ | |
| 17 | + ((defined(__mips_isa_rev) && (__mips_isa_rev >= 2)) || \ | |
| 18 | + defined(_MIPS_ARCH_LOONGSON3A)) | |
| 18 | 19 | |
| 19 | −static inline __attribute__((nomips16)) __attribute_const__ | |
| 20 | − __u16 __arch_swab16(__u16 x) | |
| 20 | +static inline __attribute_const__ __u16 __arch_swab16(__u16 x) | |
| 21 | 21 | { |
| 22 | 22 | __asm__( |
| 23 | 23 | " .set push \n" |
| 24 | 24 | " .set arch=mips32r2 \n" |
| 25 | − " .set nomips16 \n" | |
| 26 | 25 | " wsbh %0, %1 \n" |
| 27 | 26 | " .set pop \n" |
| 28 | 27 | : "=r" (x) |
| @@ -32,13 +31,11 @@ static inline __attribute__((nomips16)) __attribute_const__ · 3 unmodified lines | ||
| 32 | 31 | } |
| 33 | 32 | #define __arch_swab16 __arch_swab16 |
| 34 | 33 | |
| 35 | −static inline __attribute__((nomips16)) __attribute_const__ | |
| 36 | − __u32 __arch_swab32(__u32 x) | |
| 34 | +static inline __attribute_const__ __u32 __arch_swab32(__u32 x) | |
| 37 | 35 | { |
| 38 | 36 | __asm__( |
| 39 | 37 | " .set push \n" |
| 40 | 38 | " .set arch=mips32r2 \n" |
| 41 | − " .set nomips16 \n" | |
| 42 | 39 | " wsbh %0, %1 \n" |
| 43 | 40 | " rotr %0, %0, 16 \n" |
| 44 | 41 | " .set pop \n" |
| @@ -54,13 +51,11 @@ static inline __attribute__((nomips16)) __attribute_const__ · 9 unmodified lines | ||
| 54 | 51 | * 64-bit kernel on r2 CPUs. |
| 55 | 52 | */ |
| 56 | 53 | #ifdef __mips64 |
| 57 | −static inline __attribute__((nomips16)) __attribute_const__ | |
| 58 | − __u64 __arch_swab64(__u64 x) | |
| 54 | +static inline __attribute_const__ __u64 __arch_swab64(__u64 x) | |
| 59 | 55 | { |
| 60 | 56 | __asm__( |
| 61 | 57 | " .set push \n" |
| 62 | 58 | " .set arch=mips64r2 \n" |
| 63 | − " .set nomips16 \n" | |
| 64 | 59 | " dsbh %0, %1 \n" |
| 65 | 60 | " dshd %0, %0 \n" |
| 66 | 61 | " .set pop \n" |
| @@ -71,5 +66,5 @@ static inline __attribute__((nomips16)) __attribute_const__ · 4 unmodified lines | ||
| 71 | 66 | } |
| 72 | 67 | #define __arch_swab64 __arch_swab64 |
| 73 | 68 | #endif /* __mips64 */ |
| 74 | −#endif /* MIPS R2 or newer or Loongson 3A */ | |
| 69 | +#endif /* (not __mips16) and (MIPS R2 or newer or Loongson 3A) */ | |
| 75 | 70 | #endif /* _ASM_SWAB_H */ |